Parser doesn't understand constraint implication operator ('->')

[veripoolbot]

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Author Name: Dave Storrar
Original Redmine Issue: 1064 from https://www.veripool.org
Original Date: 2016-05-29

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The following code produces a parsing error:

class testcase;
  rand bit [3:0] a, b;
  constraint c { (a == 0) -> (b == 1); }
endclass

%Error: testcase.sv:3: syntax error, unexpected '}'

I see a comment in the VParseBison.y that seems to relate to a conflict between the 2009 and 2012 SystemVerilog versions, but I'm not familiar with Bison, so can't work out what should be happening.

Hope you can help.

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-06-05T20:35:48Z

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I spent about 3 hours trying to fix this, sorry it's a big mess due to ambiguities in the Verilog language specification, so give me some more time. For the moment you may want to `ifndef around it.

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-09-09T02:07:26Z

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Sorry, but after days of trying this appears almost impossible to fix using the current parser. I'm going to have to abandon fixing this for the time being. If you or a Bison expert wants to provide a patch, excellent!

[veripoolbot]

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Original Redmine Comment
Author Name: Dave Storrar
Original Date: 2016-09-09T08:20:54Z

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Thanks for making the attempt, I'll just have to work-around it.

Will let you know if I find a Bison expert ;-)