[Tracking Issue] SparseTIR Compatibility with Software Pipelining and Async Copy

[yzh119]

The pipeline and async copy feature in CUDA 11 can overlap data movement and computation.

TVM has already supported compiler passes such as InjectSoftwarePipeline/InjectDoubleBuffer/etc (https://github.com/apache/tvm-rfcs/blob/main/rfcs/0077-async-pipeline.md), however, we have not made these passes compatible with sparse workloads, which limits the performance of SparseTIR generated kernels.