From f67d7320c49e05e4f1d586685f71246eea25fcdf Mon Sep 17 00:00:00 2001 From: "Wu, Zhenyu" Date: Fri, 27 Dec 2024 14:13:27 +0800 Subject: [PATCH] :bento: Add assets/gel/davincihd1080p_arm.gel --- .pre-commit-config.yaml | 2 +- ...vincihd_arm.gel => davincihd1080p_arm.gel} | 128 ++++--- assets/gel/davincihd_dsp.gel | 352 ------------------ scripts/burn.js | 8 +- 4 files changed, 84 insertions(+), 406 deletions(-) rename assets/gel/{davincihd_arm.gel => davincihd1080p_arm.gel} (90%) delete mode 100644 assets/gel/davincihd_dsp.gel diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index ff60bfe..04cc3f4 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -1,5 +1,5 @@ --- -exclude: ^build-aux/git-version-gen$ +exclude: ^assets/gel/ repos: - repo: https://github.com/pre-commit/pre-commit-hooks diff --git a/assets/gel/davincihd_arm.gel b/assets/gel/davincihd1080p_arm.gel similarity index 90% rename from assets/gel/davincihd_arm.gel rename to assets/gel/davincihd1080p_arm.gel index 36145b3..5815647 100644 --- a/assets/gel/davincihd_arm.gel +++ b/assets/gel/davincihd1080p_arm.gel @@ -1,10 +1,17 @@ /* ------------------------------------------------------------------------ * * * - * davincihd_arm.gel * - * Version 0.99 * + * davincihd1080p_arm.gel * + * Version 1.15 * * * * This GEL file is designed to be used in conjunction with * - * CCStudio 3.2+ and the DM6467 based EVM. * + * CCStudio 3.3+ and the DaVinci HD1080p based EVM. * + * * + * Version History * + * v0.11 - Updated Refresh Rate * + * v0.12 - Pll0 DIV2/DIV3 updated to correct ratios * + * v0.13 - Unused PLL1 registers removed (1/14/2010) * + * v1.14 - Unused PINMUX0 field removed (7/01/2010) * + * v1.15 - DDR2 Settings updated (7/28/2010) * * * * ------------------------------------------------------------------------ */ /* ------------------------------------------------------------------------ * @@ -26,20 +33,23 @@ StartUp( ) * ------------------------------------------------------------------------ */ OnTargetConnect( ) { - GEL_TextOut( "\nDaVinci HD ARM Startup Sequence\n\n" ); + GEL_TextOut( "\nDaVinci HD1080p ARM Startup Sequence\n\n" ); Disable_IRQ_Flush_Cache( ); // Clean up system state Enable_Instruction_Cache( ); // Enable I-Cache Setup_Pin_Mux( ); // Setup Pin Mux Setup_Psc_All_On( ); // Setup All Power Domains - // Setup_Pll0_594_MHz_OscIn( ); // Setup Pll0 [DSP @ 594 MHz, ARM @ 297 MHz] - Setup_DDR_297_MHz( ); // Setup DDR2 [297 MHz] + /* Setup_Pll0_990_MHz_OscIn( ); // Setup Pll0 [DSP @ 990 MHz, ARM @ 247.5 MHz] */ + Setup_DDR_396_MHz( ); // Setup DDR2 [396 MHz] + +// Setup_EMIFCS2_NandFlash_8Bit( );// Setup NAND Flash - Setup_EMIFCS2_NandFlash_8Bit( );// Setup NAND Flash +// DSP_Boot_from_L2_ram( ); // Boot DSP from L2 + + psc_change_state( 31 , 0 ); // I2C Off + psc_change_state( 31 , 3 ); // I2C On - // DSP_Boot_from_L2_ram( ); // Boot DSP from L2 - DSP_Boot_from_DDR2(); GEL_TextOut( "\nStartup Complete.\n\n" ); } @@ -53,7 +63,7 @@ OnTargetConnect( ) OnPreFileLoaded( ) { /* - * GEL_Reset() is used to deal with the worst case scenario of + * GEL_Reset() is used to deal with the worst case senario of * unknown target state. If for some reason a reset is not desired * upon target connection, GEL_Reset() may be removed and replaced * with something "less brutal" like a cache initialization @@ -90,7 +100,7 @@ OnRestart( int nErrorCode ) GEL_TextOut( "\n" ); } -menuitem "DaVinci HD Memory Map"; +menuitem "DaVinci HD1080pMemory Map"; /* ------------------------------------------------------------------------ * * * @@ -214,7 +224,7 @@ Clear_Memory_Map( ) GEL_MapReset( ); } -menuitem "DaVinci HD Functions"; +menuitem "DaVinci HD1080p Functions"; _wait( int delay ) { @@ -295,7 +305,7 @@ Disable_VPSS( ) /* ------------------------------------------------------------------------ * * * * Disable_EDMA( ) * - * Disable EDMA events and interrupts, clear any pending events * + * Disabe EDMA events and interrupts, clear any pending events * * * * ------------------------------------------------------------------------ */ Disable_EDMA( ) @@ -335,7 +345,7 @@ hotmenu Enable_Instruction_Cache( ) CPSR = 0x400000d3; // Set to supervisor mode, disable IRQ/FIQ REG_CP15_I_CACHE = 1; // Enable Instruction Cache -} +} /* ------------------------------------------------------------------------ * * * @@ -370,7 +380,6 @@ Setup_Pin_Mux( ) | ( 0 << 20 ) // [2]TSSIMUX [VP_DIN[7:0]] | ( 0 << 18 ) // [2]PTSOMUX [VP_DIN[7:0]] | ( 0 << 16 ) // [2]PTSIMUX [VP_DIN[15:8]] - | ( 0 << 5 ) // PINTD [GPIO5] | ( 0 << 2 ) // PCIEN [no PCI] | ( 0 << 1 ) // HPIEN [no HPI] | ( 1 << 0 ); // ATAEN [ATA/NAND]*/ @@ -519,7 +528,7 @@ psc_change_state( int id, int state ) * clock_source <- 0: Onchip Oscillator * * 1: External Clock * * * - * pll_mult <- 21: 22x Multiplier * 27MHz Clk = 594 MHz * + * pll_mult <- 29: Multiplier(30) * 33MHz Clk = 990 MHz * * * * ------------------------------------------------------------------------ */ setup_pll_0( int clock_source, int pll_mult ) @@ -539,7 +548,7 @@ setup_pll_0( int clock_source, int pll_mult ) unsigned int* pll_div8 = ( unsigned int* )( 0x01c40970 ); unsigned int* pll_div9 = ( unsigned int* )( 0x01c40974 ); - int pll0_freq = 27 * ( pll_mult + 1 ); + int pll0_freq = 33 * ( pll_mult + 1 ); int dsp_freq = pll0_freq; int arm_freq = pll0_freq / 2; int postdiv = 0; @@ -597,16 +606,16 @@ setup_pll_0( int clock_source, int pll_mult ) * Div9: VLYNQ */ *pll_div1 = 0x8000 | 0; // DSP - *pll_div2 = 0x8000 | 1; // ARM/PCI/HDVICP - *pll_div3 = 0x8000 | 3; // Peripherals - *pll_div4 = 0x8000 | 5; // ATA divider +// *pll_div2 = 0x8000 | 3; // ARM/PCI/HDVICP 247.5 +// *pll_div3 = 0x8000 | 7; // EMIFA, HPI, Peripherals + *pll_div4 = 0x8000 | 9; // ATA divider 99 //*pll_div5 = 0x8000 | 7; //*pll_div6 = 0x8000 | 7; //*pll_div7 = 0x8000 | 7; - *pll_div8 = 0x8000 | 7; // Video Clock - *pll_div9 = 0x8000 | 5; // VLYNQ divider + *pll_div8 = 0x8000 | 12; // Video Clock 76.15 + *pll_div9 = 0x8000 | 9; // VLYNQ divider //*pll_bpdiv = 0x8000 | bpdiv; // Bypass divider - //*pll_postdiv= 0x8000 | postdiv; // Post divider + //*pll_postdiv= 0x8000 | postdiv; // Post divider *pll_cmd |= 0x0001; // GO _wait( 2000 ); @@ -624,9 +633,9 @@ setup_pll_0( int clock_source, int pll_mult ) _wait( 2000 ); *pll_ctl |= 0x0001; - pll0_freq = 27 * ( ( *pll_pllm & 0x3f ) + 1 ); + pll0_freq = 33 * ( ( *pll_pllm & 0x3f ) + 1 ); dsp_freq = pll0_freq; - arm_freq = pll0_freq / 2; + arm_freq = pll0_freq / 4; GEL_TextOut( "(DSP = %d MHz + ",,,,, dsp_freq ); GEL_TextOut( "ARM = %d MHz + ",,,,, arm_freq ); @@ -640,10 +649,10 @@ setup_pll_0( int clock_source, int pll_mult ) } hotmenu -Setup_Pll0_594_MHz_OscIn( ) +Setup_Pll0_990_MHz_OscIn( ) { - /* DSP @ [594 MHz] & ARM @ [297 MHz] w/ Onchip Oscillator */ - setup_pll_0( 0, 21 ); + /* DSP @ [990 MHz] & ARM @ [297 MHz] w/ Onchip Oscillator */ + setup_pll_0( 0, 29 ); } /* ------------------------------------------------------------------------ * @@ -654,10 +663,10 @@ Setup_Pll0_594_MHz_OscIn( ) * 1: External Clock * * * * pll_mult <- PLL Multiplier * - * 23: 24x Multiplier * 27MHz Clk = 648 MHz * + * 23: Multiplier(=24) * 33MHz Clk = 792MHz * * * * ddr2_div <- DDR2 divider ( For pll1 ) * - * 1: 648 MHz Clk / (2*2)x Divider = 162 MHz * + * 0: 792 MHz Clk / (2 * Divider(=1)) = 396MHz * * * * ------------------------------------------------------------------------ */ setup_pll_1( int clock_source, int pll_mult, int ddr2_div ) @@ -667,12 +676,9 @@ setup_pll_1( int clock_source, int pll_mult, int ddr2_div ) unsigned int* pll_cmd = ( unsigned int* )( 0x01c40d38 ); unsigned int* pll_stat = ( unsigned int* )( 0x01c40d3c ); unsigned int* pll_div1 = ( unsigned int* )( 0x01c40d18 ); - unsigned int* pll_div2 = ( unsigned int* )( 0x01c40d1c ); - unsigned int* pll_bpdiv = ( unsigned int* )( 0x01c40d2c ); - int pll1_freq = 27 * ( pll_mult + 1 ); + int pll1_freq = 33 * ( pll_mult + 1 ); int ddr2_freq = pll1_freq / ( 2 * ( ddr2_div + 1 ) ); - int bpdiv = 1; GEL_TextOut( "Setup PLL1 " ); @@ -721,8 +727,8 @@ setup_pll_1( int clock_source, int pll_mult, int ddr2_div ) * Step 9 - Load PLL dividers ( must be in a 1/3/6 ratio ) * 1:DDR2 */ - *pll_bpdiv = 0x8000 | bpdiv; - *pll_div2 = 0x8000 | ( ddr2_div & 0x1f ); + + *pll_div1 = 0x8000 | ( ddr2_div & 0x1f ); *pll_cmd |= 0x0001; // Set phase alignment while( ( *pll_stat & 1 ) != 0 );// Wait for phase alignment @@ -740,8 +746,8 @@ setup_pll_1( int clock_source, int pll_mult, int ddr2_div ) _wait( 2000 ); *pll_ctl |= 0x0001; - pll1_freq = 27 * ( ( *pll_pllm & 0x3f ) + 1 ); - ddr2_freq = pll1_freq / ( 2 * ( ( *pll_div2 & 0x1f ) + 1 ) ); + pll1_freq = 33 * ( ( *pll_pllm & 0x3f ) + 1 ); + ddr2_freq = pll1_freq / ( 2 * ( ( *pll_div1 & 0x1f ) + 1 ) ); GEL_TextOut( "(DDR2 Phy = %d MHz + ",,,,, ddr2_freq ); @@ -782,15 +788,35 @@ setup_ddr2( int freq ) /* * Step 3 - DDR2 Initialization */ - DDR_DDRPHYCR = 0x00008AC7; // DLL powered, ReadLatency=7 - DDR_SDBCR = 0x08D78A32; // DDR Bank: 32-bit bus, CAS=5, - // 8 banks, 1024-word pg, unlocl - DDR_SDTIMR = 0x4B245C12; - DDR_SDTIMR2 = 0x3B2BC742; - DDR_SDRCR = 0x90D; // Refresh Control [ 7.8 us * 297 MHz ] + DDR_DDRPHYCR = 0x00004006; // DLL powered, ReadLatency=6 + DDR_SDBCR = 0x00138a32; // DDR Bank: 32-bit bus, CAS=5, + // 8 banks, 1024-word pg - DDR_SDBCR = 0x08570A32; // Lock values + if ( freq == 396 ) // 2.53ns + { + DDR_SDTIMR = 0 // DDR Timing Register + | (50 << 25 ) // tRFC = ( 127.5 ns / 2.53 ns ) - 1 + | ( 4 << 22 ) // tRP = ( 12.5 ns / 2.53 ns ) - 1 + | ( 4 << 19 ) // tRCD = ( 12.5 ns / 2.53 ns ) - 1 + | ( 5 << 16 ) // tWR = ( 15 ns / 2.53 ns ) - 1 + | (17 << 11 ) // tRAS = ( 45 ns / 2.53 ns ) - 1 + | (22 << 6 ) // tRC = ( 57.5 ns / 2.53 ns ) - 1 + | ( 3 << 3 ) // tRRD = ( 10 ns / 2.53 ns ) - 1 + | ( 2 << 0 ); // tWTR = ( 7.5 ns / 2.53 ns ) - 1 + + DDR_SDTIMR2 = 0 // DDR Timing Register 2 + | ( 8 << 27) // T_RASMAX = (tRASmax/refresh_rate) - 1; tRASmax =70us, refreshrate = 7.8us + | ( 3 << 25) // tXP = 2 tCKE = 3 + | ( 54 << 16) // tXSNR= ( 137.5 ns / 2.53 ns ) - 1 + | ( 199<< 8 ) // tXSRD= ( 200 cycles ) - 1 + | ( 2 << 5 ) // tRTP = ( 7.5 ns / 2.53 ns ) - 1 + | ( 2 << 0 ); // tCKE = ( 3 cycles ) - 1 + + refresh_rate = 3088; // 7.8 us * 396 MHz + } + DDR_SDBCR = 0x00130a32; // DDR Bank: cannot modify + DDR_SDRCR = refresh_rate; // Refresh Control [ 7.8 usec * freq ] /* * Step 4 - Dummy Read from DDR2 @@ -807,11 +833,11 @@ setup_ddr2( int freq ) } hotmenu -Setup_DDR_297_MHz( ) +Setup_DDR_396_MHz( ) { - /* [DDR @ 297 MHz] w/ Onchip Oscillator */ - setup_pll_1( 0, 21, 0 ); - setup_ddr2( 297 ); + /* [DDR @ 396 MHz] w/ Onchip Oscillator */ + setup_pll_1( 0, 23, 0 ); + setup_ddr2( 396 ); } /* ------------------------------------------------------------------------ * @@ -891,7 +917,7 @@ Setup_EMIFCS2_NandFlash_8Bit( ) GEL_TextOut( "[Done]\n" ); } -menuitem "DaVinci HD Boot Mode"; +menuitem "DaVinci HD1080p Boot Mode"; /* ------------------------------------------------------------------------ * * * @@ -963,7 +989,7 @@ Boot_Mode_Reader( ) GEL_TextOut( "\n" ); } -menuitem "DaVinci HD DSP"; +menuitem "DaVinci HD1080p DSP"; /* ------------------------------------------------------------------------ * * * diff --git a/assets/gel/davincihd_dsp.gel b/assets/gel/davincihd_dsp.gel deleted file mode 100644 index dd9e3aa..0000000 --- a/assets/gel/davincihd_dsp.gel +++ /dev/null @@ -1,352 +0,0 @@ -/* ------------------------------------------------------------------------ * - * * - * evmdm6467_dsp.gel * - * Version 0.03 * - * * - * This GEL file is designed to be used in conjunction with * - * CCStudio 3.2+ and the DM646x based EVM. * - * * - * ------------------------------------------------------------------------ */ -/* ------------------------------------------------------------------------ * - * * - * StartUp( ) * - * Setup Memory Map * - * * - * ------------------------------------------------------------------------ */ -StartUp( ) -{ - Setup_Memory_Map( ); -} - -/* ------------------------------------------------------------------------ * - * * - * OnTargetConnect( ) * - * Setup PinMux, Power, PLLs, DDR, & EMIF * - * * - * ------------------------------------------------------------------------ */ -OnTargetConnect( ) -{ - GEL_TextOut( "\nDaVinci HD Startup Sequence\n\n" ); - - Setup_Cache( ); // Setup L1P/L1D Cache - - GEL_TextOut( "\nStartup Complete.\n\n" ); -} - -/* ------------------------------------------------------------------------ * - * * - * OnPreFileLoaded( ) * - * This function is called automatically when the 'Load Program' * - * Menu item is selected. * - * * - * ------------------------------------------------------------------------ */ -OnPreFileLoaded( ) -{ - /* - * GEL_Reset() is used to deal with the worst case scenario of - * unknown target state. If for some reason a reset is not desired - * upon target connection, GEL_Reset() may be removed and replaced - * with something "less brutal" like a cache initialization - * function. - */ - GEL_Reset( ); - - Disable_VPSS( ); // Disable VPSS - - GEL_TextOut( "Clear L2 Cache in DDR Range\n" ); - GEL_MemoryFill( 0x01848200, 0, 0x40, 0 ); - Setup_Cache( ); // Invalidate Cache - - Disable_EDMA( ); // Disable EDMA - - IER = 0; // Disable DSP interrupts - IFR = 0; - - GEL_TextOut( "\n" ); -} - -/* ------------------------------------------------------------------------ * - * * - * OnRestart( ) * - * This function is called by CCS when you do Debug->Restart. * - * The goal is to put the C6x into a known good state with respect to * - * cache, edma and interrupts. * - * Failure to do this can cause problems when you restart and * - * run your application code multiple times. This is different * - * then OnPreFileLoaded() which will do a GEL_Reset() to get the * - * C6x into a known good state. * - * * - * ------------------------------------------------------------------------ */ -OnRestart( int nErrorCode ) -{ - /* - * Turn off L2 for DDR. The app should manage these for coherency - * in the application. Disable L2 cache in the DDR memory space - */ - GEL_TextOut( "Clear L2 Cache in DDR Range\n" ); - GEL_MemoryFill( 0x01848200, 0, 0x40, 0 ); - - Setup_Cache( ); // Setup Cache - - Disable_EDMA( ); // Disable EDMA - - IER = 0; // Disable DSP interrupts - IFR = 0; - GEL_TextOut( "\n" ); -} - -menuitem "DaVinci EVM Memory Map"; - -/* ------------------------------------------------------------------------ * - * * - * Setup_Memory_Map( ) * - * Setup the Memory Map for ARM side only. * - * * - * ------------------------------------------------------------------------ */ -hotmenu -Setup_Memory_Map( ) -{ - GEL_MapOn( ); - GEL_MapReset( ); - - /* ARM RAM & ROM */ - GEL_MapAddStr( 0x10010000, 0, 0x00004000, "R|W|AS4", 0 ); // ARM RAM0 Data - GEL_MapAddStr( 0x10014000, 0, 0x00004000, "R|W|AS4", 0 ); // ARM RAM1 Data - GEL_MapAddStr( 0x10018000, 0, 0x00008000, "R|AS4", 0 ); // ARM ROM Data - - /* DSP CFG */ - GEL_MapAddStr( 0x01800000, 0, 0x00010000, "R|W|AS4", 0 ); // C64x+ Intr Ctrl - GEL_MapAddStr( 0x01810000, 0, 0x00001000, "R|W|AS4", 0 ); // C64x+ Powerdown Ctrl - GEL_MapAddStr( 0x01811000, 0, 0x00001000, "R|W|AS4", 0 ); // C64x+ Security ID - GEL_MapAddStr( 0x01812000, 0, 0x00001000, "R|W|AS4", 0 ); // C64x+ Revision ID - GEL_MapAddStr( 0x01820000, 0, 0x00010000, "R|W|AS4", 0 ); // C64x+ EMC - GEL_MapAddStr( 0x01840000, 0, 0x00010000, "R|W|AS4", 0 ); // C64x+ Memory System - - /* Peripherals */ - GEL_MapAddStr( 0x01c00000, 0, 0x00000644, "R|W|AS4", 0 ); // EDMA Channel Ctrl - GEL_MapAddStr( 0x01c01000, 0, 0x00000098, "R|W|AS4", 0 ); // EDMA Channel Ctrl - GEL_MapAddStr( 0x01c02000, 0, 0x00000098, "R|W|AS4", 0 ); // EDMA Channel Ctrl - GEL_MapAddStr( 0x01c02200, 0, 0x00000098, "R|W|AS4", 0 ); // EDMA Channel Ctrl - GEL_MapAddStr( 0x01c10000, 0, 0x000003d8, "R|W|AS4", 0 ); // EDMA Transfer Ctrl 0 - GEL_MapAddStr( 0x01c10400, 0, 0x000003d8, "R|W|AS4", 0 ); // EDMA Transfer Ctrl 1 - GEL_MapAddStr( 0x01c10800, 0, 0x000003d8, "R|W|AS4", 0 ); // EDMA Transfer Ctrl 2 - GEL_MapAddStr( 0x01c10c00, 0, 0x000003d8, "R|W|AS4", 0 ); // EDMA Transfer Ctrl 3 - GEL_MapAddStr( 0x01c12000, 0, 0x00000400, "R|W|AS4", 0 ); // Video Port - GEL_MapAddStr( 0x01c12800, 0, 0x00000800, "R|W|AS4", 0 ); // Graphics Engine - GEL_MapAddStr( 0x01c13000, 0, 0x00000400, "R|W|AS4", 0 ); // Stream I/O 0 - GEL_MapAddStr( 0x01c13400, 0, 0x00000400, "R|W|AS4", 0 ); // Stream I/O 1 - GEL_MapAddStr( 0x01c1a000, 0, 0x00000800, "R|W|AS4", 0 ); // PCI Control - GEL_MapAddStr( 0x01c20000, 0, 0x00000060, "R|W|AS4", 0 ); // UART 0 - GEL_MapAddStr( 0x01c20400, 0, 0x00000060, "R|W|AS4", 0 ); // UART 1 - GEL_MapAddStr( 0x01c20800, 0, 0x00000060, "R|W|AS4", 0 ); // UART 2 - GEL_MapAddStr( 0x01c21000, 0, 0x0000003c, "R|W|AS4", 0 ); // I2C - GEL_MapAddStr( 0x01c21400, 0, 0x00000028, "R|W|AS4", 0 ); // Timer 0 - GEL_MapAddStr( 0x01c21800, 0, 0x00000028, "R|W|AS4", 0 ); // Timer 1 - GEL_MapAddStr( 0x01c21c00, 0, 0x0000002c, "R|W|AS4", 0 ); // Timer 2 WDT - GEL_MapAddStr( 0x01c22000, 0, 0x0000001c, "R|W|AS4", 0 ); // PWM 0 - GEL_MapAddStr( 0x01c22400, 0, 0x0000001c, "R|W|AS4", 0 ); // PWM 1 - GEL_MapAddStr( 0x01c26000, 0, 0x00000058, "R|W|AS4", 0 ); // CRGEN0 - GEL_MapAddStr( 0x01c26400, 0, 0x00000058, "R|W|AS4", 0 ); // CRGEN1 - GEL_MapAddStr( 0x01c40000, 0, 0x00000080, "R|W|AS4", 0 ); // Device System - GEL_MapAddStr( 0x01c40400, 0, 0x00000400, "R|W|AS4", 0 ); // Security Controller - GEL_MapAddStr( 0x01c40800, 0, 0x00000178, "R|W|AS4", 0 ); // PLL0 - GEL_MapAddStr( 0x01c40c00, 0, 0x00000154, "R|W|AS4", 0 ); // PLL1 - GEL_MapAddStr( 0x01c41000, 0, 0x00000518, "R|W|AS4", 0 ); // PSC Domain Control - GEL_MapAddStr( 0x01c41800, 0, 0x000000b8, "R|W|AS4", 0 ); // PSC Module Status - GEL_MapAddStr( 0x01c41a00, 0, 0x000000b8, "R|W|AS4", 0 ); // PSC Module Control - GEL_MapAddStr( 0x01c64000, 0, 0x00002000, "R|W|AS4", 0 ); // USB 2.0 - GEL_MapAddStr( 0x01c66000, 0, 0x0000007c, "R|W|AS2", 0 ); // ATA - GEL_MapAddStr( 0x01c66800, 0, 0x00000068, "R|W|AS4", 0 ); // SPI - GEL_MapAddStr( 0x01c67000, 0, 0x00000060, "R|W|AS4", 0 ); // GPIO - GEL_MapAddStr( 0x01c67800, 0, 0x00000800, "R|W|AS4", 0 ); // HPI - GEL_MapAddStr( 0x01c80000, 0, 0x00000280, "R|W|AS4", 0 ); // EMAC Control - GEL_MapAddStr( 0x01c81000, 0, 0x00000078, "R|W|AS4", 0 ); // EMAC Module - GEL_MapAddStr( 0x01c82000, 0, 0x00002000, "R|W|AS4", 0 ); // EMAC Module RAM - GEL_MapAddStr( 0x01c84000, 0, 0x00000090, "R|W|AS4", 0 ); // MDIO - GEL_MapAddStr( 0x01d11000, 0, 0x00001400, "R|W|AS4", 0 ); // MCASP0 - GEL_MapAddStr( 0x01d11400, 0, 0x00000400, "R|W|AS4", 0 ); // MCASP0 Data - GEL_MapAddStr( 0x01d11800, 0, 0x00000400, "R|W|AS4", 0 ); // MCASP1 - GEL_MapAddStr( 0x01d11c00, 0, 0x00000400, "R|W|AS4", 0 ); // MCASP1 Data - GEL_MapAddStr( 0x02000000, 0, 0x00200000, "R|W|AS4", 0 ); // HD-VICP0 - GEL_MapAddStr( 0x02200000, 0, 0x00200000, "R|W|AS4", 0 ); // HD-VICP1 - - /* HD-VICP0 */ - GEL_MapAddStr( 0x00400000, 0, 0x00100000, "R|W|AS4", 0 ); // HD-VICP0 - GEL_MapAddStr( 0x11400000, 0, 0x00100000, "R|W|AS4", 0 ); // HD-VICP0 - GEL_MapAddStr( 0x40400000, 0, 0x00040000, "R|W|AS4", 0 ); // HD-VICP0 R/W Port - GEL_MapAddStr( 0x40440000, 0, 0x00040000, "R|W|AS4", 0 ); // HD-VICP0 R-Only Port - GEL_MapAddStr( 0x40480000, 0, 0x00040000, "R|W|AS4", 0 ); // HD-VICP0 W-Only Port - - /* HD-VICP1 */ - GEL_MapAddStr( 0x00600000, 0, 0x00100000, "R|W|AS4", 0 ); // HD-VICP1 - GEL_MapAddStr( 0x11600000, 0, 0x00100000, "R|W|AS4", 0 ); // HD-VICP1 - GEL_MapAddStr( 0x40600000, 0, 0x00040000, "R|W|AS4", 0 ); // HD-VICP1 R/W Port - GEL_MapAddStr( 0x40640000, 0, 0x00040000, "R|W|AS4", 0 ); // HD-VICP1 R-Only Port - GEL_MapAddStr( 0x40680000, 0, 0x00040000, "R|W|AS4", 0 ); // HD-VICP1 W-Only Port - - /* DSP RAM */ - GEL_MapAddStr( 0x00818000, 0, 0x00020000, "R|W|AS4", 0 ); // DSP L2 RAM/Cache - GEL_MapAddStr( 0x00e00000, 0, 0x00008000, "R|W|AS4", 0 ); // DSP L1P Cache/RAM - GEL_MapAddStr( 0x00f00000, 0, 0x00008000, "R|W|AS4", 0 ); // DSP L1D Cache/RAM - GEL_MapAddStr( 0x11818000, 0, 0x00020000, "R|W|AS4", 0 ); // DSP L2 RAM/Cache - GEL_MapAddStr( 0x11e00000, 0, 0x00008000, "R|W|AS4", 0 ); // DSP L1P Cache/RAM - GEL_MapAddStr( 0x11f00000, 0, 0x00008000, "R|W|AS4", 0 ); // DSP L1D Cache/RAM - - /* DDR2 */ - GEL_MapAddStr( 0x20000000, 0, 0x000000f4, "R|W|AS4", 0 ); // DDR2 Control - GEL_MapAddStr( 0x80000000, 0, 0x40000000, "R|W|AS4", 0 ); // DDR2 SDRAM - - /* EMIFA */ - GEL_MapAddStr( 0x20008000, 0, 0x00000080, "R|W|AS4", 0 ); // EMIFA Control - GEL_MapAddStr( 0x42000000, 0, 0x02000000, "R|W|AS4", 0 ); // AEMIF CS2 - GEL_MapAddStr( 0x44000000, 0, 0x02000000, "R|W|AS4", 0 ); // AEMIF CS3 - GEL_MapAddStr( 0x46000000, 0, 0x02000000, "R|W|AS4", 0 ); // AEMIF CS4 - GEL_MapAddStr( 0x48000000, 0, 0x02000000, "R|W|AS4", 0 ); // AEMIF CS5 - - /* VLYNQ */ - GEL_MapAddStr( 0x20010000, 0, 0x00000048, "R|W|AS4", 0 ); // VLYNQ Control - //GEL_MapAddStr( 0x20010080, 0, 0x00000068, "R|W|AS4", 0 ); // VLYNQ Control Remote - GEL_MapAddStr( 0x4c000000, 0, 0x04000000, "R|W|AS4", 0 ); // VLYNQ Remote Devices - - /* PCI */ - GEL_MapAddStr( 0x30000000, 0, 0x10000000, "R|W|AS4", 0 ); // PCI Address Space - -} - -/* ------------------------------------------------------------------------ * - * * - * Clear_Memory_Map( ) * - * Clear the Memory Map * - * * - * ------------------------------------------------------------------------ */ -hotmenu -Clear_Memory_Map( ) -{ - GEL_MapOff( ); - GEL_MapReset( ); -} - -menuitem "DaVinci HD Functions"; - -/* ------------------------------------------------------------------------ * - * * - * Setup_Cache( ) * - * Invalidate old cache and setup cache for operation * - * * - * ------------------------------------------------------------------------ */ -hotmenu -Setup_Cache( ) -{ - int l1p, l1d, l2; - - GEL_TextOut( "Setup Cache " ); - #define CACHE_L2CFG *( unsigned int* )( 0x01840000 ) - #define CACHE_L2INV *( unsigned int* )( 0x01845008 ) - #define CACHE_L1PCFG *( unsigned int* )( 0x01840020 ) - #define CACHE_L1PINV *( unsigned int* )( 0x01845028 ) - #define CACHE_L1DCFG *( unsigned int* )( 0x01840040 ) - #define CACHE_L1DINV *( unsigned int* )( 0x01845048 ) - - CACHE_L1PINV = 1; // L1P invalidated - CACHE_L1PCFG = 7; // L1P on, MAX size - CACHE_L1DINV = 1; // L1D invalidated - CACHE_L1DCFG = 7; // L1D on, MAX size - CACHE_L2INV = 1; // L2 invalidated - CACHE_L2CFG = 0; // L2 off, use as RAM - - l1p = CACHE_L1PCFG; - if ( l1p == 0 ) - GEL_TextOut( "(L1P = 0K) + " ); - if ( l1p == 1 ) - GEL_TextOut( "(L1P = 4K) + " ); - if ( l1p == 2 ) - GEL_TextOut( "(L1P = 8K) + " ); - if ( l1p == 3 ) - GEL_TextOut( "(L1P = 16K) + " ); - if ( l1p >= 4 ) - GEL_TextOut( "(L1P = 32K) + " ); - - l1d = CACHE_L1DCFG; - if ( l1d == 0 ) - GEL_TextOut( "(L1D = 0K) + " ); - if ( l1d == 1 ) - GEL_TextOut( "(L1D = 4K) + " ); - if ( l1d == 2 ) - GEL_TextOut( "(L1D = 8K) + " ); - if ( l1d == 3 ) - GEL_TextOut( "(L1D = 16K) + " ); - if ( l1d >= 4 ) - GEL_TextOut( "(L1D = 32K) + " ); - - l2 = CACHE_L2CFG; - if ( l2 == 0 ) - GEL_TextOut( "(L2 = ALL SRAM)... " ); - else if ( l2 == 1 ) - GEL_TextOut( "(L2 = 31/32 SRAM)... " ); - else if ( l2 == 2 ) - GEL_TextOut( "(L2 = 15/16 SRAM)... " ); - else if ( l2 == 3 ) - GEL_TextOut( "(L2 = 7/8 SRAM)... " ); - else if ( l2 == 7 ) - GEL_TextOut( "(L2 = 3/4 SRAM)... " ); - - GEL_TextOut( "[Done]\n" ); -} - -/* ------------------------------------------------------------------------ * - * * - * Disable_VPSS( ) * - * Disable VPFE & VPBE * - * * - * ------------------------------------------------------------------------ */ -Disable_VPSS( ) -{ - #define VPIF_CHCTRL0 *( unsigned int* )( 0x01c12004 ) - #define VPIF_CHCTRL1 *( unsigned int* )( 0x01c12008 ) - #define VPIF_CHCTRL2 *( unsigned int* )( 0x01c1200c ) - #define VPIF_CHCTRL3 *( unsigned int* )( 0x01c12010 ) - #define VPIF_INTEN *( unsigned int* )( 0x01c12020 ) - #define VPIF_INTENCLR *( unsigned int* )( 0x01c12028 ) - - GEL_TextOut( "Disable VPSS\n" ); - VPIF_CHCTRL0 = 0; - VPIF_CHCTRL1 = 0; - VPIF_CHCTRL2 = 0; - VPIF_CHCTRL3 = 0; - - VPIF_INTEN = 0; - VPIF_INTENCLR = 0x0f; - - /* Clear Channels */ - //GEL_MemoryFill( 0x01c12040, 0, 104, 0 ); // Channel 0-3 -} - -/* ------------------------------------------------------------------------ * - * * - * Disable_EDMA( ) * - * Disable EDMA events and interrupts, clear any pending events * - * * - * ------------------------------------------------------------------------ */ -Disable_EDMA( ) -{ - #define EDMA_3CC_IECRH *( int* )( 0x01C0105C ) - #define EDMA_3CC_EECRH *( int* )( 0x01C0102C ) - #define EDMA_3CC_ICRH *( int* )( 0x01C01074 ) - #define EDMA_3CC_ECRH *( int* )( 0x01C0100C ) - - #define EDMA_3CC_IECR *( int* )( 0x01C01058 ) - #define EDMA_3CC_EECR *( int* )( 0x01C01028 ) - #define EDMA_3CC_ICR *( int* )( 0x01C01070 ) - #define EDMA_3CC_ECR *( int* )( 0x01C01008 ) - - GEL_TextOut( "Disable EDMA events\n" ); - EDMA_3CC_IECRH = 0xFFFFFFFF; // IERH ( disable high interrupts ) - EDMA_3CC_EECRH = 0xFFFFFFFF; // EERH ( disable high events ) - EDMA_3CC_ICRH = 0xFFFFFFFF; // ICRH ( clear high interrupts ) - EDMA_3CC_ECRH = 0xFFFFFFFF; // ICRH ( clear high events ) - - EDMA_3CC_IECR = 0xFFFFFFFF; // IER ( disable low interrupts ) - EDMA_3CC_EECR = 0xFFFFFFFF; // EER ( disable low events ) - EDMA_3CC_ICR = 0xFFFFFFFF; // ICR ( clear low interrupts ) - EDMA_3CC_ECR = 0xFFFFFFFF; // ICRH ( clear low events ) -} diff --git a/scripts/burn.js b/scripts/burn.js index 55d999f..0c5011c 100755 --- a/scripts/burn.js +++ b/scripts/burn.js @@ -7,10 +7,14 @@ ds.setConfig("targetConfigs/TMS320DM6467.ccxml"); var arm926 = ds.openSession( "Texas Instruments XDS100v3 USB Debug Probe/ARM926" ); -arm926.expression.evaluate('GEL_LoadGel("assets/gel/davincihd_arm.gel")'); +// /opt/ccstudio/ccs/ccs_base/emulation/boards/evmdm6467/gel/davincihd1080p_arm.gel +// comment Setup_Pll0_990_MHz_OscIn() +arm926.expression.evaluate('GEL_LoadGel("assets/gel/davincihd1080p_arm.gel")'); arm926.target.connect(); +// after OnTargetConnect() +arm926.expression.evaluate('DSP_Boot_from_DDR2()'); var c64xp = ds.openSession("Texas Instruments XDS100v3 USB Debug Probe/C64XP"); -c64xp.expression.evaluate('GEL_LoadGel("assets/gel/davincihd_dsp.gel")'); +c64xp.expression.evaluate('GEL_LoadGel("/opt/ccstudio/ccs/ccs_base/emulation/boards/evmdm6467/gel/davincihd1080p_dsp.gel")'); c64xp.target.connect(); c64xp.memory.loadProgram("x264.out", ["x264.out"].concat(arguments)); c64xp.clock.runBenchmark();