From a9185ffb48ae13e3ee3b05fc1ab602c63cb16943 Mon Sep 17 00:00:00 2001 From: Robin Mueller Date: Tue, 17 Sep 2024 10:14:32 +0200 Subject: [PATCH] more smaller improvements --- examples/simple/examples/timer-ticks.rs | 5 +++-- va416xx-hal/src/timer.rs | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/examples/simple/examples/timer-ticks.rs b/examples/simple/examples/timer-ticks.rs index 2f13b58..ffa7821 100644 --- a/examples/simple/examples/timer-ticks.rs +++ b/examples/simple/examples/timer-ticks.rs @@ -5,6 +5,7 @@ use core::cell::Cell; use cortex_m_rt::entry; use critical_section::Mutex; +use embedded_hal::delay::DelayNs; use panic_rtt_target as _; use rtt_target::{rprintln, rtt_init_print}; use simple_examples::peb1; @@ -35,7 +36,7 @@ fn main() -> ! { .xtal_n_clk_with_src_freq(peb1::EXTCLK_FREQ) .freeze(&mut dp.sysconfig) .unwrap(); - let _ = set_up_ms_tick(&mut dp.sysconfig, dp.tim0, &clocks); + let mut delay_provider = set_up_ms_tick(&mut dp.sysconfig, dp.tim0, &clocks); let mut second_timer = CountdownTimer::new(&mut dp.sysconfig, dp.tim1, &clocks); second_timer.start(1.Hz()); second_timer.listen(); @@ -47,7 +48,7 @@ fn main() -> ! { let second = critical_section::with(|cs| SEC_COUNTER.borrow(cs).get()); rprintln!("Second counter: {}", second); } - cortex_m::asm::delay(10000); + delay_provider.delay_ms(1000); } } diff --git a/va416xx-hal/src/timer.rs b/va416xx-hal/src/timer.rs index 100d0a7..82feb39 100644 --- a/va416xx-hal/src/timer.rs +++ b/va416xx-hal/src/timer.rs @@ -587,7 +587,7 @@ impl CountdownTimer { pub fn load(&mut self, timeout: impl Into) { self.tim.reg().ctrl().modify(|_, w| w.enable().clear_bit()); self.curr_freq = timeout.into(); - self.rst_val = self.clock.raw() / self.curr_freq.raw(); + self.rst_val = self.clock.raw() / self.curr_freq.raw() - 1; self.set_reload(self.rst_val); // Decrementing counter, to set the reset value. self.set_count(0); @@ -610,7 +610,7 @@ impl CountdownTimer { #[inline(always)] pub fn enable(&mut self) { - self.tim.reg().ctrl().modify(|_, w| w.enable().set_bit()); + self.tim.reg().enable().write(|w| unsafe { w.bits(1) }); } #[inline(always)]