README.md

WM8731

⚠Warning

1️⃣Please add files in order to avoid the program reporting missing files.

How to do: Assignments → Settings → Files

File Name	Type	Library	Design Entry/Synthesis Tool	HDL Version
src_dsp/config.sv	SystemVerilog HDL File			Default
src_dsp/fir.sv	SystemVerilog HDL File			Default
src_top/define.v	Verilog HDL File			Default
src_top/i2c_control.v	Verilog HDL File			Default
src_top/i2c_config.v	Verilog HDL File			Default
src_top/codec.v	Verilog HDL File			Default
src_top/top.v	Verilog HDL File			Default
wrapper.v	Verilog HDL File			Default
pll.qip	IP Variation File (.qip)
pll.sip	Quartus Prime SIP File

2️⃣ Turn off Auto DSP Block Replacement to avoid the case where the program reports insufficient resources

How to do: Assignments → Settings → Compiler Settings → Advanced Settings (Synthesis) → Set Logic Element option for DSP Block Balancing settings

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📝 Other information will be updated later