From 09ec715317d15cfa0916bb92c8d4faaacdb37a30 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Mon, 16 Oct 2023 18:57:39 +0200 Subject: [PATCH] Initial commit Signed-off-by: Gerard Marull-Paretas --- .github/workflows/ci.yml | 30 + .gitignore | 15 + .gitmodules | 3 + Cargo.toml | 28 + LICENSE-APACHE | 201 + LICENSE-MIT | 25 + Makefile | 22 + README.md | 42 + build.rs | 16 + chiptool | 1 + device.x | 31 + src/_vectors.rs | 88 + src/adc.rs | 115 + src/adc/regs.rs | 1563 ++++ src/adc/vals.rs | 244 + src/can.rs | 58 + src/can/regs.rs | 601 ++ src/can/vals.rs | 180 + src/common.rs | 69 + src/common/sealed.rs | 5 + src/crc.rs | 39 + src/crc/regs.rs | 102 + src/crc/vals.rs | 63 + src/gpio.rs | 89 + src/gpio/regs.rs | 162 + src/gpio/vals.rs | 34 + src/gptimer.rs | 29 + src/gptimer/regs.rs | 90 + src/gptimer/vals.rs | 58 + src/i2c.rs | 99 + src/i2c/regs.rs | 384 + src/i2c/vals.rs | 337 + src/lib.rs | 155 + src/memctl.rs | 49 + src/memctl/regs.rs | 294 + src/memctl/vals.rs | 186 + src/rtc.rs | 49 + src/rtc/regs.rs | 369 + src/rtc/vals.rs | 90 + src/scc.rs | 174 + src/scc/regs.rs | 1118 +++ src/scc/vals.rs | 2571 +++++++ src/ssp.rs | 64 + src/ssp/regs.rs | 493 ++ src/ssp/vals.rs | 271 + src/timer.rs | 82 + src/timer/regs.rs | 632 ++ src/timer/vals.rs | 323 + src/usart.rs | 69 + src/usart/regs.rs | 428 ++ src/usart/vals.rs | 204 + src/wwdt.rs | 49 + src/wwdt/regs.rs | 205 + src/wwdt/vals.rs | 117 + svd/PAC55XX.svd | 13243 ++++++++++++++++++++++++++++++++++ svd/PAC55XX.transforms.yaml | 148 + svd/PAC55XX.yaml | 75 + 57 files changed, 26281 insertions(+) create mode 100644 .github/workflows/ci.yml create mode 100644 .gitignore create mode 100644 .gitmodules create mode 100644 Cargo.toml create mode 100644 LICENSE-APACHE create mode 100644 LICENSE-MIT create mode 100644 Makefile create mode 100644 README.md create mode 100644 build.rs create mode 160000 chiptool create mode 100644 device.x create mode 100644 src/_vectors.rs create mode 100644 src/adc.rs create mode 100644 src/adc/regs.rs create mode 100644 src/adc/vals.rs create mode 100644 src/can.rs create mode 100644 src/can/regs.rs create mode 100644 src/can/vals.rs create mode 100644 src/common.rs create mode 100644 src/common/sealed.rs create mode 100644 src/crc.rs create mode 100644 src/crc/regs.rs create mode 100644 src/crc/vals.rs create mode 100644 src/gpio.rs create mode 100644 src/gpio/regs.rs create mode 100644 src/gpio/vals.rs create mode 100644 src/gptimer.rs create mode 100644 src/gptimer/regs.rs create mode 100644 src/gptimer/vals.rs create mode 100644 src/i2c.rs create mode 100644 src/i2c/regs.rs create mode 100644 src/i2c/vals.rs create mode 100644 src/lib.rs create mode 100644 src/memctl.rs create mode 100644 src/memctl/regs.rs create mode 100644 src/memctl/vals.rs create mode 100644 src/rtc.rs create mode 100644 src/rtc/regs.rs create mode 100644 src/rtc/vals.rs create mode 100644 src/scc.rs create mode 100644 src/scc/regs.rs create mode 100644 src/scc/vals.rs create mode 100644 src/ssp.rs create mode 100644 src/ssp/regs.rs create mode 100644 src/ssp/vals.rs create mode 100644 src/timer.rs create mode 100644 src/timer/regs.rs create mode 100644 src/timer/vals.rs create mode 100644 src/usart.rs create mode 100644 src/usart/regs.rs create mode 100644 src/usart/vals.rs create mode 100644 src/wwdt.rs create mode 100644 src/wwdt/regs.rs create mode 100644 src/wwdt/vals.rs create mode 100644 svd/PAC55XX.svd create mode 100644 svd/PAC55XX.transforms.yaml create mode 100644 svd/PAC55XX.yaml diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml new file mode 100644 index 0000000..973098f --- /dev/null +++ b/.github/workflows/ci.yml @@ -0,0 +1,30 @@ +name: CI + +on: + push: + branches: [main] + pull_request: + branches: [main] + +jobs: + ci: + name: CI + runs-on: ubuntu-24.04 + env: {"RUSTFLAGS": "-Dwarnings"} + steps: + - uses: actions/checkout@v4 + with: + submodules: true + + - uses: dtolnay/rust-toolchain@stable + with: + target: thumbv7em-none-eabihf + + - name: Install dependencies + run: cargo install svdtools form + + - name: Generate + run: make + + - name: Check + run: cargo check --features=rt diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..c5037eb --- /dev/null +++ b/.gitignore @@ -0,0 +1,15 @@ +# Generated by Cargo +# will have compiled files and executables +debug/ +target/ +.idea/ + +# Remove Cargo.lock from gitignore if creating an executable, leave it for libraries +# More information here https://doc.rust-lang.org/cargo/guide/cargo-toml-vs-cargo-lock.html +Cargo.lock + +# These are backup files generated by rustfmt +**/*.rs.bk + +*.patched +*.swp diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..b33fba2 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "chiptool"] + path = chiptool + url = https://github.com/embassy-rs/chiptool diff --git a/Cargo.toml b/Cargo.toml new file mode 100644 index 0000000..ee4d723 --- /dev/null +++ b/Cargo.toml @@ -0,0 +1,28 @@ +[package] +name = "pac55xx-pac" +authors = ["Gerard Marull-Paretas "] +description = "Peripheral Access Crate (PAC) for PAC55XX" +repository = "https://github.com/teslabs/pac55xx-pac" +readme = "README.md" +keywords = ["embedded", "no_std", "qorvo", "pac55xx"] +categories = ["embedded", "no-std"] +license = "MIT/Apache-2.0" +edition = "2021" +include = [ + "src/*", + "build.rs", + "device.x", + "Cargo.toml", + "README.md", +] +version = "0.3.0" + +[dependencies] +cortex-m = "0.7.7" +cortex-m-rt = { version = ">=0.6.15,<0.8", optional = true } + +[features] +rt = ["cortex-m-rt/device"] + +[workspace] +members = ["chiptool"] diff --git a/LICENSE-APACHE b/LICENSE-APACHE new file mode 100644 index 0000000..16fe87b --- /dev/null +++ b/LICENSE-APACHE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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IN NO EVENT +SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR +IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..4ae00f9 --- /dev/null +++ b/Makefile @@ -0,0 +1,22 @@ +SVDTOOL := svdtools +CHIPTOOL := target/release/chiptool + +all: patch crate fmt + +svd/PAC55XX.svd.patched: svd/PAC55XX.yaml svd/PAC55XX.svd + $(SVDTOOL) patch $< + +patch: svd/PAC55XX.svd.patched + +crate: svd/PAC55XX.svd.patched $(CHIPTOOL) + $(CHIPTOOL) generate --svd svd/PAC55XX.svd.patched --transform svd/PAC55XX.transforms.yaml + rm -rf src + sed -i.orig 's/# ! \[no_std\]/# ! [no_std] # ! [allow(non_camel_case_types)]/g' lib.rs + form -i lib.rs -o src + rm lib.rs lib.rs.orig + +fmt: + cargo fmt --package=pac55xx-pac + +$(CHIPTOOL): + cargo build --release --package=chiptool diff --git a/README.md b/README.md new file mode 100644 index 0000000..6c65875 --- /dev/null +++ b/README.md @@ -0,0 +1,42 @@ +# pac55xx-pac + +This is a [Peripheral Access Crate](https://rust-embedded.github.io/book/start/registers.html) +for Qorvo PAC55XX microcontrollers. + +This crate has been automatically generated from a custom SVD file +using [chiptool](https://github.com/embassy-rs/chiptool/). + +## Supported chips + +- **PAC55XX**: [Documentation](https://www.qorvo.com/products/power-solutions/intelligent-motor-controllers) + +## Generation + +Install [svdtools](https://github.com/rust-embedded/svdtools/) and +[form](https://github.com/djmcgill/form): + +```sh +cargo install svdtools form +``` + +Make sure submodules are initialized: + +```sh +git submodule update --init +``` + +Then, run: + +```sh +make +``` + +## License + +Licensed under either of + +- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or + http://www.apache.org/licenses/LICENSE-2.0) +- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT) + +at your option. diff --git a/build.rs b/build.rs new file mode 100644 index 0000000..597923f --- /dev/null +++ b/build.rs @@ -0,0 +1,16 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/chiptool b/chiptool new file mode 160000 index 0000000..2a63600 --- /dev/null +++ b/chiptool @@ -0,0 +1 @@ +Subproject commit 2a636008ca334e02a211edbc912a7a49cedf82be diff --git a/device.x b/device.x new file mode 100644 index 0000000..ecfa176 --- /dev/null +++ b/device.x @@ -0,0 +1,31 @@ +PROVIDE(MEMCTL = DefaultHandler); +PROVIDE(WWDT = DefaultHandler); +PROVIDE(RTC = DefaultHandler); +PROVIDE(ADC0 = DefaultHandler); +PROVIDE(ADC1 = DefaultHandler); +PROVIDE(ADC2 = DefaultHandler); +PROVIDE(ADC3 = DefaultHandler); +PROVIDE(TIMERA = DefaultHandler); +PROVIDE(TIMERB = DefaultHandler); +PROVIDE(TIMERC = DefaultHandler); +PROVIDE(TIMERD = DefaultHandler); +PROVIDE(TIMERAQEP = DefaultHandler); +PROVIDE(TIMERBQEP = DefaultHandler); +PROVIDE(TIMERCQEP = DefaultHandler); +PROVIDE(TIMERDQEP = DefaultHandler); +PROVIDE(GPIOA = DefaultHandler); +PROVIDE(GPIOB = DefaultHandler); +PROVIDE(GPIOC = DefaultHandler); +PROVIDE(GPIOD = DefaultHandler); +PROVIDE(GPIOE = DefaultHandler); +PROVIDE(GPIOF = DefaultHandler); +PROVIDE(GPIOG = DefaultHandler); +PROVIDE(I2C = DefaultHandler); +PROVIDE(USARTA_SSPA = DefaultHandler); +PROVIDE(USARTB_SSPB = DefaultHandler); +PROVIDE(USARTC_SSPC = DefaultHandler); +PROVIDE(USARTD_SSPD = DefaultHandler); +PROVIDE(CAN = DefaultHandler); +PROVIDE(GPTIMERA = DefaultHandler); +PROVIDE(GPTIMERB = DefaultHandler); +PROVIDE(SCC = DefaultHandler); diff --git a/src/_vectors.rs b/src/_vectors.rs new file mode 100644 index 0000000..f0724cf --- /dev/null +++ b/src/_vectors.rs @@ -0,0 +1,88 @@ +extern "C" { + fn MEMCTL(); + fn WWDT(); + fn RTC(); + fn ADC0(); + fn ADC1(); + fn ADC2(); + fn ADC3(); + fn TIMERA(); + fn TIMERB(); + fn TIMERC(); + fn TIMERD(); + fn TIMERAQEP(); + fn TIMERBQEP(); + fn TIMERCQEP(); + fn TIMERDQEP(); + fn GPIOA(); + fn GPIOB(); + fn GPIOC(); + fn GPIOD(); + fn GPIOE(); + fn GPIOF(); + fn GPIOG(); + fn I2C(); + fn USARTA_SSPA(); + fn USARTB_SSPB(); + fn USARTC_SSPC(); + fn USARTD_SSPD(); + fn CAN(); + fn GPTIMERA(); + fn GPTIMERB(); + fn SCC(); +} +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 31] = [ + Vector { _handler: MEMCTL }, + Vector { _handler: WWDT }, + Vector { _handler: RTC }, + Vector { _handler: ADC0 }, + Vector { _handler: ADC1 }, + Vector { _handler: ADC2 }, + Vector { _handler: ADC3 }, + Vector { _handler: TIMERA }, + Vector { _handler: TIMERB }, + Vector { _handler: TIMERC }, + Vector { _handler: TIMERD }, + Vector { + _handler: TIMERAQEP, + }, + Vector { + _handler: TIMERBQEP, + }, + Vector { + _handler: TIMERCQEP, + }, + Vector { + _handler: TIMERDQEP, + }, + Vector { _handler: GPIOA }, + Vector { _handler: GPIOB }, + Vector { _handler: GPIOC }, + Vector { _handler: GPIOD }, + Vector { _handler: GPIOE }, + Vector { _handler: GPIOF }, + Vector { _handler: GPIOG }, + Vector { _handler: I2C }, + Vector { + _handler: USARTA_SSPA, + }, + Vector { + _handler: USARTB_SSPB, + }, + Vector { + _handler: USARTC_SSPC, + }, + Vector { + _handler: USARTD_SSPD, + }, + Vector { _handler: CAN }, + Vector { _handler: GPTIMERA }, + Vector { _handler: GPTIMERB }, + Vector { _handler: SCC }, +]; diff --git a/src/adc.rs b/src/adc.rs new file mode 100644 index 0000000..bd72805 --- /dev/null +++ b/src/adc.rs @@ -0,0 +1,115 @@ +#[doc = "Analog to Digital Converter (ADC) and Dynamic Triggering and Sampling Engine (DTSE)"] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Adc { + ptr: *mut u8, +} +unsafe impl Send for Adc {} +unsafe impl Sync for Adc {} +impl Adc { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "EMUX Control"] + #[inline(always)] + pub const fn emuxctl(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "EMUX Data"] + #[inline(always)] + pub const fn emuxdata(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } + #[doc = "ADC Control"] + #[inline(always)] + pub const fn adcctl(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } + } + #[doc = "ADC Result"] + #[inline(always)] + pub const fn adcres(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } + #[doc = "ADC Interrupt Control"] + #[inline(always)] + pub const fn adcint(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } + } + #[doc = "DTSE Trigger Entry 0 to 3"] + #[inline(always)] + pub const fn dtsetrigent0to3( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) } + } + #[doc = "DTSE Trigger Entry 4 to 7"] + #[inline(always)] + pub const fn dtsetrigent4to7( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) } + } + #[doc = "DTSE Trigger Entry 8 to 11"] + #[inline(always)] + pub const fn dtsetrigent8to11( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) } + } + #[doc = "DTSE Trigger Entry 12 to 15"] + #[inline(always)] + pub const fn dtsetrigent12to15( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) } + } + #[doc = "DTSE Trigger Entry 16 to 19"] + #[inline(always)] + pub const fn dtsetrigent16to19( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) } + } + #[doc = "DTSE Trigger Entry 20 to 23"] + #[inline(always)] + pub const fn dtsetrigent20to23( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) } + } + #[doc = "DTSE Trigger Entry 24 to 27"] + #[inline(always)] + pub const fn dtsetrigent24to27( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) } + } + #[doc = "DTSE Trigger Entry 28 to 31"] + #[inline(always)] + pub const fn dtsetrigent28to31( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) } + } + #[doc = "DTSE Sequence Configuration"] + #[inline(always)] + pub const fn dtseseqcfg( + self, + n: usize, + ) -> crate::common::Reg { + assert!(n < 24usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize + n * 4usize) as _) } + } + #[doc = "DTSE Result"] + #[inline(always)] + pub const fn dtseres(self, n: usize) -> crate::common::Reg { + assert!(n < 24usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize + n * 4usize) as _) } + } +} +pub mod regs; +pub mod vals; diff --git a/src/adc/regs.rs b/src/adc/regs.rs new file mode 100644 index 0000000..bdbdb23 --- /dev/null +++ b/src/adc/regs.rs @@ -0,0 +1,1563 @@ +#[doc = "ADC Control"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Adcctl(pub u32); +impl Adcctl { + #[doc = "ADC Clock Divider"] + #[inline(always)] + pub const fn adcdiv(&self) -> super::vals::Adcdiv { + let val = (self.0 >> 0usize) & 0x0f; + super::vals::Adcdiv::from_bits(val as u8) + } + #[doc = "ADC Clock Divider"] + #[inline(always)] + pub fn set_adcdiv(&mut self, val: super::vals::Adcdiv) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize); + } + #[doc = "ADC Channel Select"] + #[inline(always)] + pub const fn channel(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x07; + val as u8 + } + #[doc = "ADC Channel Select"] + #[inline(always)] + pub fn set_channel(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val as u32) & 0x07) << 4usize); + } + #[doc = "ADC Busy"] + #[inline(always)] + pub const fn adbusy(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "ADC Busy"] + #[inline(always)] + pub fn set_adbusy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "ADC Mode"] + #[inline(always)] + pub const fn mode(&self) -> super::vals::Mode { + let val = (self.0 >> 8usize) & 0x03; + super::vals::Mode::from_bits(val as u8) + } + #[doc = "ADC Mode"] + #[inline(always)] + pub fn set_mode(&mut self, val: super::vals::Mode) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); + } + #[doc = "ADC Repeat"] + #[inline(always)] + pub const fn repeat(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "ADC Repeat"] + #[inline(always)] + pub fn set_repeat(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "ADC Start"] + #[inline(always)] + pub const fn start(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "ADC Start"] + #[inline(always)] + pub fn set_start(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "ADC Enable"] + #[inline(always)] + pub const fn enable(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "ADC Enable"] + #[inline(always)] + pub fn set_enable(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Manual Conversion Complete Interrupt Enable"] + #[inline(always)] + pub const fn intenman(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Manual Conversion Complete Interrupt Enable"] + #[inline(always)] + pub fn set_intenman(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "EMUX Complete Interrupt Enable"] + #[inline(always)] + pub const fn intenemux(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "EMUX Complete Interrupt Enable"] + #[inline(always)] + pub fn set_intenemux(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Sequence Collision Interrupt Enable"] + #[inline(always)] + pub const fn intencol(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Sequence Collision Interrupt Enable"] + #[inline(always)] + pub fn set_intencol(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "ADC Accuracy Mode Enable"] + #[inline(always)] + pub const fn enacc(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "ADC Accuracy Mode Enable"] + #[inline(always)] + pub fn set_enacc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } +} +impl Default for Adcctl { + #[inline(always)] + fn default() -> Adcctl { + Adcctl(0) + } +} +#[doc = "ADC Interrupt Control"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Adcint(pub u32); +impl Adcint { + #[doc = "DTSE Sequence Interrupt Flag"] + #[inline(always)] + pub const fn intf(&self, n: usize) -> bool { + assert!(n < 24usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "DTSE Sequence Interrupt Flag"] + #[inline(always)] + pub fn set_intf(&mut self, n: usize, val: bool) { + assert!(n < 24usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "DTSE Manual Conversion Complete Interrupt Flag"] + #[inline(always)] + pub const fn intfman(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "DTSE Manual Conversion Complete Interrupt Flag"] + #[inline(always)] + pub fn set_intfman(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "DTSE EMUX Complete Interrupt Flag"] + #[inline(always)] + pub const fn intfemux(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "DTSE EMUX Complete Interrupt Flag"] + #[inline(always)] + pub fn set_intfemux(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "DTSE Sequence Collision Interrupt Flag"] + #[inline(always)] + pub const fn intfcol(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "DTSE Sequence Collision Interrupt Flag"] + #[inline(always)] + pub fn set_intfcol(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "ADCIRQ Interrupt Flag"] + #[inline(always)] + pub const fn adcirqif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 28usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "ADCIRQ Interrupt Flag"] + #[inline(always)] + pub fn set_adcirqif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 28usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } +} +impl Default for Adcint { + #[inline(always)] + fn default() -> Adcint { + Adcint(0) + } +} +#[doc = "ADC Result"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Adcres(pub u32); +impl Adcres { + #[doc = "ADC Conversion Result (manual mode)"] + #[inline(always)] + pub const fn adcres(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "ADC Conversion Result (manual mode)"] + #[inline(always)] + pub fn set_adcres(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } +} +impl Default for Adcres { + #[inline(always)] + fn default() -> Adcres { + Adcres(0) + } +} +#[doc = "DTSE Result"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Dtseres(pub u32); +impl Dtseres { + #[doc = "DTSE Conversion Result"] + #[inline(always)] + pub const fn res(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "DTSE Conversion Result"] + #[inline(always)] + pub fn set_res(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } +} +impl Default for Dtseres { + #[inline(always)] + fn default() -> Dtseres { + Dtseres(0) + } +} +#[doc = "DTSE Sequence Configuration"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Dtseseqcfg(pub u32); +impl Dtseseqcfg { + #[doc = "EMUX Control"] + #[inline(always)] + pub const fn emuxc(&self) -> super::vals::DtseseqcfgEmuxc { + let val = (self.0 >> 0usize) & 0x03; + super::vals::DtseseqcfgEmuxc::from_bits(val as u8) + } + #[doc = "EMUX Control"] + #[inline(always)] + pub fn set_emuxc(&mut self, val: super::vals::DtseseqcfgEmuxc) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + #[doc = "Channel"] + #[inline(always)] + pub const fn channel(&self) -> u8 { + let val = (self.0 >> 2usize) & 0x07; + val as u8 + } + #[doc = "Channel"] + #[inline(always)] + pub fn set_channel(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 2usize)) | (((val as u32) & 0x07) << 2usize); + } + #[doc = "Final sequence of series"] + #[inline(always)] + pub const fn seqdone(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Final sequence of series"] + #[inline(always)] + pub fn set_seqdone(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "EMUX Data"] + #[inline(always)] + pub const fn emuxd(&self) -> u8 { + let val = (self.0 >> 8usize) & 0xff; + val as u8 + } + #[doc = "EMUX Data"] + #[inline(always)] + pub fn set_emuxd(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); + } + #[doc = "IRQ Number to assert"] + #[inline(always)] + pub const fn irqnum(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x03; + val as u8 + } + #[doc = "IRQ Number to assert"] + #[inline(always)] + pub fn set_irqnum(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize); + } + #[doc = "Assert IRQ after converting this sequence"] + #[inline(always)] + pub const fn irqen(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Assert IRQ after converting this sequence"] + #[inline(always)] + pub fn set_irqen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "No ADC conversion"] + #[inline(always)] + pub const fn nocvt(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "No ADC conversion"] + #[inline(always)] + pub fn set_nocvt(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } +} +impl Default for Dtseseqcfg { + #[inline(always)] + fn default() -> Dtseseqcfg { + Dtseseqcfg(0) + } +} +#[doc = "DTSE Trigger Entry 0 to 3"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Dtsetrigent0to3(pub u32); +impl Dtsetrigent0to3 { + #[doc = "DTSE Trigger 0 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig0cfgidx(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 0 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig0cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); + } + #[doc = "DTSE Trigger 0 Edge Configuration"] + #[inline(always)] + pub const fn trig0edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 5usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 0 Edge Configuration"] + #[inline(always)] + pub fn set_trig0edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 5usize)) | (((val.to_bits() as u32) & 0x03) << 5usize); + } + #[doc = "Force Trigger 0"] + #[inline(always)] + pub const fn force0(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 0"] + #[inline(always)] + pub fn set_force0(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "DTSE Trigger 1 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig1cfgidx(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 1 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig1cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); + } + #[doc = "DTSE Trigger 1 Edge Configuration"] + #[inline(always)] + pub const fn trig1edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 13usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 1 Edge Configuration"] + #[inline(always)] + pub fn set_trig1edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 13usize)) | (((val.to_bits() as u32) & 0x03) << 13usize); + } + #[doc = "Force Trigger 1"] + #[inline(always)] + pub const fn force1(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 1"] + #[inline(always)] + pub fn set_force1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "DTSE Trigger 2 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig2cfgidx(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 2 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig2cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize); + } + #[doc = "DTSE Trigger 2 Edge Configuration"] + #[inline(always)] + pub const fn trig2edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 21usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 2 Edge Configuration"] + #[inline(always)] + pub fn set_trig2edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 21usize)) | (((val.to_bits() as u32) & 0x03) << 21usize); + } + #[doc = "Force Trigger 2"] + #[inline(always)] + pub const fn force2(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 2"] + #[inline(always)] + pub fn set_force2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "DTSE Trigger 3 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig3cfgidx(&self) -> u8 { + let val = (self.0 >> 24usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 3 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig3cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 24usize)) | (((val as u32) & 0x1f) << 24usize); + } + #[doc = "DTSE Trigger 3 Edge Configuration"] + #[inline(always)] + pub const fn trig3edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 29usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 3 Edge Configuration"] + #[inline(always)] + pub fn set_trig3edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 29usize)) | (((val.to_bits() as u32) & 0x03) << 29usize); + } + #[doc = "Force Trigger 3"] + #[inline(always)] + pub const fn force3(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 3"] + #[inline(always)] + pub fn set_force3(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } +} +impl Default for Dtsetrigent0to3 { + #[inline(always)] + fn default() -> Dtsetrigent0to3 { + Dtsetrigent0to3(0) + } +} +#[doc = "DTSE Trigger Entry 12 to 15"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Dtsetrigent12to15(pub u32); +impl Dtsetrigent12to15 { + #[doc = "DTSE Trigger 12 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig12cfgidx(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 12 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig12cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); + } + #[doc = "DTSE Trigger 12 Edge Configuration"] + #[inline(always)] + pub const fn trig12edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 5usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 12 Edge Configuration"] + #[inline(always)] + pub fn set_trig12edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 5usize)) | (((val.to_bits() as u32) & 0x03) << 5usize); + } + #[doc = "Force Trigger 12"] + #[inline(always)] + pub const fn force12(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 12"] + #[inline(always)] + pub fn set_force12(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "DTSE Trigger 13 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig13cfgidx(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 13 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig13cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); + } + #[doc = "DTSE Trigger 13 Edge Configuration"] + #[inline(always)] + pub const fn trig13edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 13usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 13 Edge Configuration"] + #[inline(always)] + pub fn set_trig13edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 13usize)) | (((val.to_bits() as u32) & 0x03) << 13usize); + } + #[doc = "Force Trigger 13"] + #[inline(always)] + pub const fn force13(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 13"] + #[inline(always)] + pub fn set_force13(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "DTSE Trigger 14 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig14cfgidx(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 14 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig14cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize); + } + #[doc = "DTSE Trigger 14 Edge Configuration"] + #[inline(always)] + pub const fn trig14edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 21usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 14 Edge Configuration"] + #[inline(always)] + pub fn set_trig14edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 21usize)) | (((val.to_bits() as u32) & 0x03) << 21usize); + } + #[doc = "Force Trigger 14"] + #[inline(always)] + pub const fn force14(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 14"] + #[inline(always)] + pub fn set_force14(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "DTSE Trigger 15 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig15cfgidx(&self) -> u8 { + let val = (self.0 >> 24usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 15 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig15cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 24usize)) | (((val as u32) & 0x1f) << 24usize); + } + #[doc = "DTSE Trigger 15 Edge Configuration"] + #[inline(always)] + pub const fn trig15edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 29usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 15 Edge Configuration"] + #[inline(always)] + pub fn set_trig15edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 29usize)) | (((val.to_bits() as u32) & 0x03) << 29usize); + } + #[doc = "Force Trigger 15"] + #[inline(always)] + pub const fn force15(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 15"] + #[inline(always)] + pub fn set_force15(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } +} +impl Default for Dtsetrigent12to15 { + #[inline(always)] + fn default() -> Dtsetrigent12to15 { + Dtsetrigent12to15(0) + } +} +#[doc = "DTSE Trigger Entry 16 to 19"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Dtsetrigent16to19(pub u32); +impl Dtsetrigent16to19 { + #[doc = "DTSE Trigger 16 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig16cfgidx(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 16 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig16cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); + } + #[doc = "DTSE Trigger 16 Edge Configuration"] + #[inline(always)] + pub const fn trig16edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 5usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 16 Edge Configuration"] + #[inline(always)] + pub fn set_trig16edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 5usize)) | (((val.to_bits() as u32) & 0x03) << 5usize); + } + #[doc = "Force Trigger 16"] + #[inline(always)] + pub const fn force16(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 16"] + #[inline(always)] + pub fn set_force16(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "DTSE Trigger 17 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig17cfgidx(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 17 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig17cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); + } + #[doc = "DTSE Trigger 17 Edge Configuration"] + #[inline(always)] + pub const fn trig17edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 13usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 17 Edge Configuration"] + #[inline(always)] + pub fn set_trig17edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 13usize)) | (((val.to_bits() as u32) & 0x03) << 13usize); + } + #[doc = "Force Trigger 17"] + #[inline(always)] + pub const fn force17(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 17"] + #[inline(always)] + pub fn set_force17(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "DTSE Trigger 18 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig18cfgidx(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 18 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig18cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize); + } + #[doc = "DTSE Trigger 18 Edge Configuration"] + #[inline(always)] + pub const fn trig18edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 21usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 18 Edge Configuration"] + #[inline(always)] + pub fn set_trig18edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 21usize)) | (((val.to_bits() as u32) & 0x03) << 21usize); + } + #[doc = "Force Trigger 18"] + #[inline(always)] + pub const fn force18(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 18"] + #[inline(always)] + pub fn set_force18(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "DTSE Trigger 19 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig19cfgidx(&self) -> u8 { + let val = (self.0 >> 24usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 19 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig19cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 24usize)) | (((val as u32) & 0x1f) << 24usize); + } + #[doc = "DTSE Trigger 19 Edge Configuration"] + #[inline(always)] + pub const fn trig19edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 29usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 19 Edge Configuration"] + #[inline(always)] + pub fn set_trig19edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 29usize)) | (((val.to_bits() as u32) & 0x03) << 29usize); + } + #[doc = "Force Trigger 19"] + #[inline(always)] + pub const fn force19(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 19"] + #[inline(always)] + pub fn set_force19(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } +} +impl Default for Dtsetrigent16to19 { + #[inline(always)] + fn default() -> Dtsetrigent16to19 { + Dtsetrigent16to19(0) + } +} +#[doc = "DTSE Trigger Entry 20 to 23"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Dtsetrigent20to23(pub u32); +impl Dtsetrigent20to23 { + #[doc = "DTSE Trigger 20 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig20cfgidx(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 20 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig20cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); + } + #[doc = "DTSE Trigger 20 Edge Configuration"] + #[inline(always)] + pub const fn trig20edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 5usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 20 Edge Configuration"] + #[inline(always)] + pub fn set_trig20edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 5usize)) | (((val.to_bits() as u32) & 0x03) << 5usize); + } + #[doc = "Force Trigger 20"] + #[inline(always)] + pub const fn force20(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 20"] + #[inline(always)] + pub fn set_force20(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "DTSE Trigger 21 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig21cfgidx(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 21 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig21cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); + } + #[doc = "DTSE Trigger 21 Edge Configuration"] + #[inline(always)] + pub const fn trig21edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 13usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 21 Edge Configuration"] + #[inline(always)] + pub fn set_trig21edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 13usize)) | (((val.to_bits() as u32) & 0x03) << 13usize); + } + #[doc = "Force Trigger 21"] + #[inline(always)] + pub const fn force21(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 21"] + #[inline(always)] + pub fn set_force21(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "DTSE Trigger 22 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig22cfgidx(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 22 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig22cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize); + } + #[doc = "DTSE Trigger 22 Edge Configuration"] + #[inline(always)] + pub const fn trig22edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 21usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 22 Edge Configuration"] + #[inline(always)] + pub fn set_trig22edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 21usize)) | (((val.to_bits() as u32) & 0x03) << 21usize); + } + #[doc = "Force Trigger 22"] + #[inline(always)] + pub const fn force22(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 22"] + #[inline(always)] + pub fn set_force22(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "DTSE Trigger 23 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig23cfgidx(&self) -> u8 { + let val = (self.0 >> 24usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 23 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig23cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 24usize)) | (((val as u32) & 0x1f) << 24usize); + } + #[doc = "DTSE Trigger 23 Edge Configuration"] + #[inline(always)] + pub const fn trig23edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 29usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 23 Edge Configuration"] + #[inline(always)] + pub fn set_trig23edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 29usize)) | (((val.to_bits() as u32) & 0x03) << 29usize); + } + #[doc = "Force Trigger 23"] + #[inline(always)] + pub const fn force23(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 23"] + #[inline(always)] + pub fn set_force23(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } +} +impl Default for Dtsetrigent20to23 { + #[inline(always)] + fn default() -> Dtsetrigent20to23 { + Dtsetrigent20to23(0) + } +} +#[doc = "DTSE Trigger Entry 24 to 27"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Dtsetrigent24to27(pub u32); +impl Dtsetrigent24to27 { + #[doc = "DTSE Trigger 24 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig24cfgidx(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 24 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig24cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); + } + #[doc = "DTSE Trigger 24 Edge Configuration"] + #[inline(always)] + pub const fn trig24edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 5usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 24 Edge Configuration"] + #[inline(always)] + pub fn set_trig24edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 5usize)) | (((val.to_bits() as u32) & 0x03) << 5usize); + } + #[doc = "Force Trigger 24"] + #[inline(always)] + pub const fn force24(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 24"] + #[inline(always)] + pub fn set_force24(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "DTSE Trigger 25 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig25cfgidx(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 25 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig25cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); + } + #[doc = "DTSE Trigger 25 Edge Configuration"] + #[inline(always)] + pub const fn trig25edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 13usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 25 Edge Configuration"] + #[inline(always)] + pub fn set_trig25edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 13usize)) | (((val.to_bits() as u32) & 0x03) << 13usize); + } + #[doc = "Force Trigger 25"] + #[inline(always)] + pub const fn force25(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 25"] + #[inline(always)] + pub fn set_force25(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "DTSE Trigger 26 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig26cfgidx(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 26 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig26cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize); + } + #[doc = "DTSE Trigger 26 Edge Configuration"] + #[inline(always)] + pub const fn trig26edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 21usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 26 Edge Configuration"] + #[inline(always)] + pub fn set_trig26edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 21usize)) | (((val.to_bits() as u32) & 0x03) << 21usize); + } + #[doc = "Force Trigger 26"] + #[inline(always)] + pub const fn force26(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 26"] + #[inline(always)] + pub fn set_force26(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "DTSE Trigger 27 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig27cfgidx(&self) -> u8 { + let val = (self.0 >> 24usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 27 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig27cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 24usize)) | (((val as u32) & 0x1f) << 24usize); + } + #[doc = "DTSE Trigger 27 Edge Configuration"] + #[inline(always)] + pub const fn trig27edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 29usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 27 Edge Configuration"] + #[inline(always)] + pub fn set_trig27edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 29usize)) | (((val.to_bits() as u32) & 0x03) << 29usize); + } + #[doc = "Force Trigger 27"] + #[inline(always)] + pub const fn force27(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 27"] + #[inline(always)] + pub fn set_force27(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } +} +impl Default for Dtsetrigent24to27 { + #[inline(always)] + fn default() -> Dtsetrigent24to27 { + Dtsetrigent24to27(0) + } +} +#[doc = "DTSE Trigger Entry 28 to 31"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Dtsetrigent28to31(pub u32); +impl Dtsetrigent28to31 { + #[doc = "DTSE Trigger 28 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig28cfgidx(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 28 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig28cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); + } + #[doc = "DTSE Trigger 28 Edge Configuration"] + #[inline(always)] + pub const fn trig28edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 5usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 28 Edge Configuration"] + #[inline(always)] + pub fn set_trig28edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 5usize)) | (((val.to_bits() as u32) & 0x03) << 5usize); + } + #[doc = "Force Trigger 28"] + #[inline(always)] + pub const fn force28(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 28"] + #[inline(always)] + pub fn set_force28(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "DTSE Trigger 29 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig29cfgidx(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 29 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig29cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); + } + #[doc = "DTSE Trigger 29 Edge Configuration"] + #[inline(always)] + pub const fn trig29edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 13usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 29 Edge Configuration"] + #[inline(always)] + pub fn set_trig29edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 13usize)) | (((val.to_bits() as u32) & 0x03) << 13usize); + } + #[doc = "Force Trigger 29"] + #[inline(always)] + pub const fn force29(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 29"] + #[inline(always)] + pub fn set_force29(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "DTSE Trigger 30 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig30cfgidx(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 30 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig30cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize); + } + #[doc = "DTSE Trigger 30 Edge Configuration"] + #[inline(always)] + pub const fn trig30edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 21usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 30 Edge Configuration"] + #[inline(always)] + pub fn set_trig30edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 21usize)) | (((val.to_bits() as u32) & 0x03) << 21usize); + } + #[doc = "Force Trigger 30"] + #[inline(always)] + pub const fn force30(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 30"] + #[inline(always)] + pub fn set_force30(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "DTSE Trigger 31 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig31cfgidx(&self) -> u8 { + let val = (self.0 >> 24usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 31 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig31cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 24usize)) | (((val as u32) & 0x1f) << 24usize); + } + #[doc = "DTSE Trigger 31 Edge Configuration"] + #[inline(always)] + pub const fn trig31edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 29usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 31 Edge Configuration"] + #[inline(always)] + pub fn set_trig31edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 29usize)) | (((val.to_bits() as u32) & 0x03) << 29usize); + } + #[doc = "Force Trigger 31"] + #[inline(always)] + pub const fn force31(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 31"] + #[inline(always)] + pub fn set_force31(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } +} +impl Default for Dtsetrigent28to31 { + #[inline(always)] + fn default() -> Dtsetrigent28to31 { + Dtsetrigent28to31(0) + } +} +#[doc = "DTSE Trigger Entry 4 to 7"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Dtsetrigent4to7(pub u32); +impl Dtsetrigent4to7 { + #[doc = "DTSE Trigger 4 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig4cfgidx(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 4 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig4cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); + } + #[doc = "DTSE Trigger 4 Edge Configuration"] + #[inline(always)] + pub const fn trig4edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 5usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 4 Edge Configuration"] + #[inline(always)] + pub fn set_trig4edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 5usize)) | (((val.to_bits() as u32) & 0x03) << 5usize); + } + #[doc = "Force Trigger 4"] + #[inline(always)] + pub const fn force4(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 4"] + #[inline(always)] + pub fn set_force4(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "DTSE Trigger 5 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig5cfgidx(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 5 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig5cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); + } + #[doc = "DTSE Trigger 5 Edge Configuration"] + #[inline(always)] + pub const fn trig5edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 13usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 5 Edge Configuration"] + #[inline(always)] + pub fn set_trig5edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 13usize)) | (((val.to_bits() as u32) & 0x03) << 13usize); + } + #[doc = "Force Trigger 5"] + #[inline(always)] + pub const fn force5(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 5"] + #[inline(always)] + pub fn set_force5(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "DTSE Trigger 6 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig6cfgidx(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 6 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig6cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize); + } + #[doc = "DTSE Trigger 6 Edge Configuration"] + #[inline(always)] + pub const fn trig6edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 21usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 6 Edge Configuration"] + #[inline(always)] + pub fn set_trig6edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 21usize)) | (((val.to_bits() as u32) & 0x03) << 21usize); + } + #[doc = "Force Trigger 6"] + #[inline(always)] + pub const fn force6(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 6"] + #[inline(always)] + pub fn set_force6(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "DTSE Trigger 7 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig7cfgidx(&self) -> u8 { + let val = (self.0 >> 24usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 7 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig7cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 24usize)) | (((val as u32) & 0x1f) << 24usize); + } + #[doc = "DTSE Trigger 7 Edge Configuration"] + #[inline(always)] + pub const fn trig7edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 29usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 7 Edge Configuration"] + #[inline(always)] + pub fn set_trig7edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 29usize)) | (((val.to_bits() as u32) & 0x03) << 29usize); + } + #[doc = "Force Trigger 7"] + #[inline(always)] + pub const fn force7(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 7"] + #[inline(always)] + pub fn set_force7(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } +} +impl Default for Dtsetrigent4to7 { + #[inline(always)] + fn default() -> Dtsetrigent4to7 { + Dtsetrigent4to7(0) + } +} +#[doc = "DTSE Trigger Entry 8 to 11"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Dtsetrigent8to11(pub u32); +impl Dtsetrigent8to11 { + #[doc = "DTSE Trigger 8 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig8cfgidx(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 8 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig8cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); + } + #[doc = "DTSE Trigger 8 Edge Configuration"] + #[inline(always)] + pub const fn trig8edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 5usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 8 Edge Configuration"] + #[inline(always)] + pub fn set_trig8edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 5usize)) | (((val.to_bits() as u32) & 0x03) << 5usize); + } + #[doc = "Force Trigger 8"] + #[inline(always)] + pub const fn force8(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 8"] + #[inline(always)] + pub fn set_force8(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "DTSE Trigger 9 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig9cfgidx(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 9 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig9cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); + } + #[doc = "DTSE Trigger 9 Edge Configuration"] + #[inline(always)] + pub const fn trig9edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 13usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 9 Edge Configuration"] + #[inline(always)] + pub fn set_trig9edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 13usize)) | (((val.to_bits() as u32) & 0x03) << 13usize); + } + #[doc = "Force Trigger 9"] + #[inline(always)] + pub const fn force9(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 9"] + #[inline(always)] + pub fn set_force9(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "DTSE Trigger 10 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig10cfgidx(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 10 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig10cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize); + } + #[doc = "DTSE Trigger 10 Edge Configuration"] + #[inline(always)] + pub const fn trig10edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 21usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 10 Edge Configuration"] + #[inline(always)] + pub fn set_trig10edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 21usize)) | (((val.to_bits() as u32) & 0x03) << 21usize); + } + #[doc = "Force Trigger 10"] + #[inline(always)] + pub const fn force10(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 10"] + #[inline(always)] + pub fn set_force10(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "DTSE Trigger 11 Sequence Configuration Entry Index"] + #[inline(always)] + pub const fn trig11cfgidx(&self) -> u8 { + let val = (self.0 >> 24usize) & 0x1f; + val as u8 + } + #[doc = "DTSE Trigger 11 Sequence Configuration Entry Index"] + #[inline(always)] + pub fn set_trig11cfgidx(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 24usize)) | (((val as u32) & 0x1f) << 24usize); + } + #[doc = "DTSE Trigger 11 Edge Configuration"] + #[inline(always)] + pub const fn trig11edge(&self) -> super::vals::Trigedge { + let val = (self.0 >> 29usize) & 0x03; + super::vals::Trigedge::from_bits(val as u8) + } + #[doc = "DTSE Trigger 11 Edge Configuration"] + #[inline(always)] + pub fn set_trig11edge(&mut self, val: super::vals::Trigedge) { + self.0 = (self.0 & !(0x03 << 29usize)) | (((val.to_bits() as u32) & 0x03) << 29usize); + } + #[doc = "Force Trigger 11"] + #[inline(always)] + pub const fn force11(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "Force Trigger 11"] + #[inline(always)] + pub fn set_force11(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } +} +impl Default for Dtsetrigent8to11 { + #[inline(always)] + fn default() -> Dtsetrigent8to11 { + Dtsetrigent8to11(0) + } +} +#[doc = "EMUX Control"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Emuxctl(pub u32); +impl Emuxctl { + #[doc = "EMUX Clock Divider"] + #[inline(always)] + pub const fn emuxdiv(&self) -> super::vals::Emuxdiv { + let val = (self.0 >> 0usize) & 0x0f; + super::vals::Emuxdiv::from_bits(val as u8) + } + #[doc = "EMUX Clock Divider"] + #[inline(always)] + pub fn set_emuxdiv(&mut self, val: super::vals::Emuxdiv) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize); + } + #[doc = "EMUX Busy"] + #[inline(always)] + pub const fn emuxbusy(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "EMUX Busy"] + #[inline(always)] + pub fn set_emuxbusy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "EMUX Mode"] + #[inline(always)] + pub const fn emuxmode(&self) -> super::vals::Emuxmode { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Emuxmode::from_bits(val as u8) + } + #[doc = "EMUX Mode"] + #[inline(always)] + pub fn set_emuxmode(&mut self, val: super::vals::Emuxmode) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize); + } +} +impl Default for Emuxctl { + #[inline(always)] + fn default() -> Emuxctl { + Emuxctl(0) + } +} +#[doc = "EMUX Data"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Emuxdata(pub u32); +impl Emuxdata { + #[doc = "Write data onto the EMUX"] + #[inline(always)] + pub const fn emuxdata(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Write data onto the EMUX"] + #[inline(always)] + pub fn set_emuxdata(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } +} +impl Default for Emuxdata { + #[inline(always)] + fn default() -> Emuxdata { + Emuxdata(0) + } +} diff --git a/src/adc/vals.rs b/src/adc/vals.rs new file mode 100644 index 0000000..fbd2b15 --- /dev/null +++ b/src/adc/vals.rs @@ -0,0 +1,244 @@ +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Adcdiv { + #[doc = "SCLK/1"] + SCLK1 = 0x0, + #[doc = "SCLK/2"] + SCLK2 = 0x01, + #[doc = "SCLK/3"] + SCLK3 = 0x02, + #[doc = "SCLK/4"] + SCLK4 = 0x03, + #[doc = "SCLK/5"] + SCLK5 = 0x04, + #[doc = "SCLK/6"] + SCLK6 = 0x05, + #[doc = "SCLK/7"] + SCLK7 = 0x06, + #[doc = "SCLK/8"] + SCLK8 = 0x07, + #[doc = "SCLK/9"] + SCLK9 = 0x08, + #[doc = "SCLK/10"] + SCLK10 = 0x09, + #[doc = "SCLK/11"] + SCLK11 = 0x0a, + #[doc = "SCLK/12"] + SCLK12 = 0x0b, + #[doc = "SCLK/13"] + SCLK13 = 0x0c, + #[doc = "SCLK/14"] + SCLK14 = 0x0d, + #[doc = "SCLK/15"] + SCLK15 = 0x0e, + #[doc = "SCLK/16"] + SCLK16 = 0x0f, +} +impl Adcdiv { + #[inline(always)] + pub const fn from_bits(val: u8) -> Adcdiv { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Adcdiv { + #[inline(always)] + fn from(val: u8) -> Adcdiv { + Adcdiv::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Adcdiv) -> u8 { + Adcdiv::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum DtseseqcfgEmuxc { + #[doc = "Do not send EMUX command"] + NO_EMUX_CMD = 0x0, + #[doc = "Send EMUX command before sample and hold"] + EMUX_CMD_BEFORE_SAMPLE = 0x01, + #[doc = "Send EMUX command after conversion is complete"] + EMUX_CMD_AFTER_CONVERSION = 0x02, + _RESERVED_3 = 0x03, +} +impl DtseseqcfgEmuxc { + #[inline(always)] + pub const fn from_bits(val: u8) -> DtseseqcfgEmuxc { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for DtseseqcfgEmuxc { + #[inline(always)] + fn from(val: u8) -> DtseseqcfgEmuxc { + DtseseqcfgEmuxc::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: DtseseqcfgEmuxc) -> u8 { + DtseseqcfgEmuxc::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Emuxdiv { + #[doc = "SCLK/1"] + SCLK1 = 0x0, + #[doc = "SCLK/2"] + SCLK2 = 0x01, + #[doc = "SCLK/3"] + SCLK3 = 0x02, + #[doc = "SCLK/4"] + SCLK4 = 0x03, + #[doc = "SCLK/5"] + SCLK5 = 0x04, + #[doc = "SCLK/6"] + SCLK6 = 0x05, + #[doc = "SCLK/7"] + SCLK7 = 0x06, + #[doc = "SCLK/8"] + SCLK8 = 0x07, + #[doc = "SCLK/9"] + SCLK9 = 0x08, + #[doc = "SCLK/10"] + SCLK10 = 0x09, + #[doc = "SCLK/11"] + SCLK11 = 0x0a, + #[doc = "SCLK/12"] + SCLK12 = 0x0b, + #[doc = "SCLK/13"] + SCLK13 = 0x0c, + #[doc = "SCLK/14"] + SCLK14 = 0x0d, + #[doc = "SCLK/15"] + SCLK15 = 0x0e, + _RESERVED_f = 0x0f, +} +impl Emuxdiv { + #[inline(always)] + pub const fn from_bits(val: u8) -> Emuxdiv { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Emuxdiv { + #[inline(always)] + fn from(val: u8) -> Emuxdiv { + Emuxdiv::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Emuxdiv) -> u8 { + Emuxdiv::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Emuxmode { + #[doc = "Write EMUX data from EMUXDATA register"] + DATA_FROM_EMUXDATA = 0x0, + #[doc = "Write EMUX data from DTSE sequencer commands"] + DATA_FROM_DTSE = 0x01, +} +impl Emuxmode { + #[inline(always)] + pub const fn from_bits(val: u8) -> Emuxmode { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Emuxmode { + #[inline(always)] + fn from(val: u8) -> Emuxmode { + Emuxmode::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Emuxmode) -> u8 { + Emuxmode::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Mode { + #[doc = "Manual mode"] + MANUAL = 0x0, + #[doc = "DTSE mode"] + DTSE = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, +} +impl Mode { + #[inline(always)] + pub const fn from_bits(val: u8) -> Mode { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Mode { + #[inline(always)] + fn from(val: u8) -> Mode { + Mode::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Mode) -> u8 { + Mode::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Trigedge { + #[doc = "Unused"] + UNUSED = 0x0, + #[doc = "Rising edge"] + RISING_EDGE = 0x01, + #[doc = "Falling edge"] + FALLING_EDGE = 0x02, + #[doc = "Both edges"] + BOTH_EDGES = 0x03, +} +impl Trigedge { + #[inline(always)] + pub const fn from_bits(val: u8) -> Trigedge { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Trigedge { + #[inline(always)] + fn from(val: u8) -> Trigedge { + Trigedge::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Trigedge) -> u8 { + Trigedge::to_bits(val) + } +} diff --git a/src/can.rs b/src/can.rs new file mode 100644 index 0000000..31d8160 --- /dev/null +++ b/src/can.rs @@ -0,0 +1,58 @@ +#[doc = "Controller Area Network"] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Can { + ptr: *mut u8, +} +unsafe impl Send for Can {} +unsafe impl Sync for Can {} +impl Can { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "CAN Mode Register/Command Register/Status Register/Interrupt Status or ACK Register"] + #[inline(always)] + pub const fn mr_cmr_sr_isr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "CAN Interrupt Mask Register/Receive Message Counter Register/Bus Timing 0 Register/Bus Timing 1 Register"] + #[inline(always)] + pub const fn imr_rmc_btr0_btr1( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } + #[doc = "CAN Transmit Buffer register"] + #[inline(always)] + pub const fn txbuf(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } + } + #[doc = "CAN Receive Buffer register"] + #[inline(always)] + pub const fn rxbuf(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } + #[doc = "CAN Acceptance Code register"] + #[inline(always)] + pub const fn acr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } + } + #[doc = "CAN Acceptance Mask register"] + #[inline(always)] + pub const fn amr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } + } + #[doc = "CAN Error Code Capture register/Receive Error Counter Register/Transmit Error Counter Register/Arbitration Lost Code Capture Register"] + #[inline(always)] + pub const fn ecc_rxerr_txerr_alc( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } + } +} +pub mod regs; +pub mod vals; diff --git a/src/can/regs.rs b/src/can/regs.rs new file mode 100644 index 0000000..b00690c --- /dev/null +++ b/src/can/regs.rs @@ -0,0 +1,601 @@ +#[doc = "CAN Acceptance Code register"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Acr(pub u32); +impl Acr { + #[doc = "Acceptance code"] + #[inline(always)] + pub const fn acr(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Acceptance code"] + #[inline(always)] + pub fn set_acr(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for Acr { + #[inline(always)] + fn default() -> Acr { + Acr(0) + } +} +#[doc = "CAN Acceptance Mask register"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Amr(pub u32); +impl Amr { + #[doc = "Acceptance code mask"] + #[inline(always)] + pub const fn amr(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Acceptance code mask"] + #[inline(always)] + pub fn set_amr(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for Amr { + #[inline(always)] + fn default() -> Amr { + Amr(0) + } +} +#[doc = "CAN Error Code Capture register/Receive Error Counter Register/Transmit Error Counter Register/Arbitration Lost Code Capture Register"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct EccRxerrTxerrAlc(pub u32); +impl EccRxerrTxerrAlc { + #[doc = "Bit error occurred"] + #[inline(always)] + pub const fn ber(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Bit error occurred"] + #[inline(always)] + pub fn set_ber(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Stuff error occurred"] + #[inline(always)] + pub const fn stfer(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Stuff error occurred"] + #[inline(always)] + pub fn set_stfer(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "CRC error occurred"] + #[inline(always)] + pub const fn crcer(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "CRC error occurred"] + #[inline(always)] + pub fn set_crcer(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Form error occurred"] + #[inline(always)] + pub const fn frmer(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Form error occurred"] + #[inline(always)] + pub fn set_frmer(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Acknowledge error occurred"] + #[inline(always)] + pub const fn acker(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Acknowledge error occurred"] + #[inline(always)] + pub fn set_acker(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Direction of transfer while error occurred"] + #[inline(always)] + pub const fn edir(&self) -> super::vals::Edir { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Edir::from_bits(val as u8) + } + #[doc = "Direction of transfer while error occurred"] + #[inline(always)] + pub fn set_edir(&mut self, val: super::vals::Edir) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize); + } + #[doc = "Set when CANTXERR is major or equal to 96"] + #[inline(always)] + pub const fn txwrn(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Set when CANTXERR is major or equal to 96"] + #[inline(always)] + pub fn set_txwrn(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Set when CANRXERR is major or equal to 96"] + #[inline(always)] + pub const fn rxwrn(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Set when CANRXERR is major or equal to 96"] + #[inline(always)] + pub fn set_rxwrn(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Receive error counter"] + #[inline(always)] + pub const fn rxerr(&self) -> u8 { + let val = (self.0 >> 8usize) & 0xff; + val as u8 + } + #[doc = "Receive error counter"] + #[inline(always)] + pub fn set_rxerr(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); + } + #[doc = "Transmit error counter"] + #[inline(always)] + pub const fn txerr(&self) -> u8 { + let val = (self.0 >> 16usize) & 0xff; + val as u8 + } + #[doc = "Transmit error counter"] + #[inline(always)] + pub fn set_txerr(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); + } + #[doc = "Arbitration lost capture"] + #[inline(always)] + pub const fn alc(&self) -> super::vals::Alc { + let val = (self.0 >> 24usize) & 0x1f; + super::vals::Alc::from_bits(val as u8) + } + #[doc = "Arbitration lost capture"] + #[inline(always)] + pub fn set_alc(&mut self, val: super::vals::Alc) { + self.0 = (self.0 & !(0x1f << 24usize)) | (((val.to_bits() as u32) & 0x1f) << 24usize); + } +} +impl Default for EccRxerrTxerrAlc { + #[inline(always)] + fn default() -> EccRxerrTxerrAlc { + EccRxerrTxerrAlc(0) + } +} +#[doc = "CAN Interrupt Mask Register/Receive Message Counter Register/Bus Timing 0 Register/Bus Timing 1 Register"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct ImrRmcBtr0Btr1(pub u32); +impl ImrRmcBtr0Btr1 { + #[doc = "Data Overrun Interrupt Mask"] + #[inline(always)] + pub const fn doim(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Data Overrun Interrupt Mask"] + #[inline(always)] + pub fn set_doim(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Bus Error Interrupt Mask"] + #[inline(always)] + pub const fn beim(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Bus Error Interrupt Mask"] + #[inline(always)] + pub fn set_beim(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Transmit Interrupt Mask"] + #[inline(always)] + pub const fn tim(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Transmit Interrupt Mask"] + #[inline(always)] + pub fn set_tim(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Receive Interrupt Mask"] + #[inline(always)] + pub const fn rim(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Receive Interrupt Mask"] + #[inline(always)] + pub fn set_rim(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Error Passive Interrupt Mask"] + #[inline(always)] + pub const fn epim(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Error Passive Interrupt Mask"] + #[inline(always)] + pub fn set_epim(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Error Warning Interrupt Mask"] + #[inline(always)] + pub const fn ewim(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Error Warning Interrupt Mask"] + #[inline(always)] + pub fn set_ewim(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Arbitration Lost Interrupt Mask"] + #[inline(always)] + pub const fn alim(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Arbitration Lost Interrupt Mask"] + #[inline(always)] + pub fn set_alim(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Number of frames stored in the receive FIFO"] + #[inline(always)] + pub const fn rmc(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x1f; + val as u8 + } + #[doc = "Number of frames stored in the receive FIFO"] + #[inline(always)] + pub fn set_rmc(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); + } + #[doc = "Baud rate prescaler"] + #[inline(always)] + pub const fn brp(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x3f; + val as u8 + } + #[doc = "Baud rate prescaler"] + #[inline(always)] + pub fn set_brp(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 16usize)) | (((val as u32) & 0x3f) << 16usize); + } + #[doc = "Synchronization jump width"] + #[inline(always)] + pub const fn sjw(&self) -> u8 { + let val = (self.0 >> 22usize) & 0x03; + val as u8 + } + #[doc = "Synchronization jump width"] + #[inline(always)] + pub fn set_sjw(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 22usize)) | (((val as u32) & 0x03) << 22usize); + } + #[doc = "Number of clock cycles per Time segment 1"] + #[inline(always)] + pub const fn tseg1(&self) -> u8 { + let val = (self.0 >> 24usize) & 0x0f; + val as u8 + } + #[doc = "Number of clock cycles per Time segment 1"] + #[inline(always)] + pub fn set_tseg1(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 24usize)) | (((val as u32) & 0x0f) << 24usize); + } + #[doc = "Number of clock cycles per Time segment 2"] + #[inline(always)] + pub const fn tseg2(&self) -> u8 { + let val = (self.0 >> 28usize) & 0x07; + val as u8 + } + #[doc = "Number of clock cycles per Time segment 2"] + #[inline(always)] + pub fn set_tseg2(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 28usize)) | (((val as u32) & 0x07) << 28usize); + } + #[doc = "Number of bus level samples"] + #[inline(always)] + pub const fn sam(&self) -> super::vals::Sam { + let val = (self.0 >> 31usize) & 0x01; + super::vals::Sam::from_bits(val as u8) + } + #[doc = "Number of bus level samples"] + #[inline(always)] + pub fn set_sam(&mut self, val: super::vals::Sam) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); + } +} +impl Default for ImrRmcBtr0Btr1 { + #[inline(always)] + fn default() -> ImrRmcBtr0Btr1 { + ImrRmcBtr0Btr1(0) + } +} +#[doc = "CAN Mode Register/Command Register/Status Register/Interrupt Status or ACK Register"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct MrCmrSrIsr(pub u32); +impl MrCmrSrIsr { + #[doc = "Hardware filter acceptance scheme"] + #[inline(always)] + pub const fn afm(&self) -> super::vals::Afm { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Afm::from_bits(val as u8) + } + #[doc = "Hardware filter acceptance scheme"] + #[inline(always)] + pub fn set_afm(&mut self, val: super::vals::Afm) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + #[doc = "Listen-only mode"] + #[inline(always)] + pub const fn lom(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Listen-only mode"] + #[inline(always)] + pub fn set_lom(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Reset mode"] + #[inline(always)] + pub const fn rm(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Reset mode"] + #[inline(always)] + pub fn set_rm(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Abort Transmission"] + #[inline(always)] + pub const fn at(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Abort Transmission"] + #[inline(always)] + pub fn set_at(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Transmit request"] + #[inline(always)] + pub const fn tr(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Transmit request"] + #[inline(always)] + pub fn set_tr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "Bus Off Status"] + #[inline(always)] + pub const fn bs(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Bus Off Status"] + #[inline(always)] + pub fn set_bs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "Error Status"] + #[inline(always)] + pub const fn es(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Error Status"] + #[inline(always)] + pub fn set_es(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Transmit Status"] + #[inline(always)] + pub const fn ts(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Transmit Status"] + #[inline(always)] + pub fn set_ts(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Receive Status"] + #[inline(always)] + pub const fn rs(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "Receive Status"] + #[inline(always)] + pub fn set_rs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } + #[doc = "Transmit Buffer Status"] + #[inline(always)] + pub const fn tbs(&self) -> bool { + let val = (self.0 >> 20usize) & 0x01; + val != 0 + } + #[doc = "Transmit Buffer Status"] + #[inline(always)] + pub fn set_tbs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); + } + #[doc = "Data Overrun Status"] + #[inline(always)] + pub const fn dso(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "Data Overrun Status"] + #[inline(always)] + pub fn set_dso(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "Receive Buffer Status"] + #[inline(always)] + pub const fn rbs(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "Receive Buffer Status"] + #[inline(always)] + pub fn set_rbs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "Data Overrun Interrupt"] + #[inline(always)] + pub const fn doi(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "Data Overrun Interrupt"] + #[inline(always)] + pub fn set_doi(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "Bus Error Interrupt"] + #[inline(always)] + pub const fn bei(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "Bus Error Interrupt"] + #[inline(always)] + pub fn set_bei(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "Transmit Interrupt"] + #[inline(always)] + pub const fn ti(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "Transmit Interrupt"] + #[inline(always)] + pub fn set_ti(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "Receive Interrupt"] + #[inline(always)] + pub const fn ri(&self) -> bool { + let val = (self.0 >> 27usize) & 0x01; + val != 0 + } + #[doc = "Receive Interrupt"] + #[inline(always)] + pub fn set_ri(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); + } + #[doc = "Error Passive Interrupt"] + #[inline(always)] + pub const fn epi(&self) -> bool { + let val = (self.0 >> 28usize) & 0x01; + val != 0 + } + #[doc = "Error Passive Interrupt"] + #[inline(always)] + pub fn set_epi(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); + } + #[doc = "Error Warning Interrupt"] + #[inline(always)] + pub const fn ewi(&self) -> bool { + let val = (self.0 >> 29usize) & 0x01; + val != 0 + } + #[doc = "Error Warning Interrupt"] + #[inline(always)] + pub fn set_ewi(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); + } + #[doc = "Arbitration Lost Interrupt"] + #[inline(always)] + pub const fn ali(&self) -> bool { + let val = (self.0 >> 30usize) & 0x01; + val != 0 + } + #[doc = "Arbitration Lost Interrupt"] + #[inline(always)] + pub fn set_ali(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); + } +} +impl Default for MrCmrSrIsr { + #[inline(always)] + fn default() -> MrCmrSrIsr { + MrCmrSrIsr(0) + } +} +#[doc = "CAN Receive Buffer register"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Rxbuf(pub u32); +impl Rxbuf { + #[doc = "Receive buffer data"] + #[inline(always)] + pub const fn rxbuf(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Receive buffer data"] + #[inline(always)] + pub fn set_rxbuf(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for Rxbuf { + #[inline(always)] + fn default() -> Rxbuf { + Rxbuf(0) + } +} +#[doc = "CAN Transmit Buffer register"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Txbuf(pub u32); +impl Txbuf { + #[doc = "Transmit buffer data"] + #[inline(always)] + pub const fn txbuf(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Transmit buffer data"] + #[inline(always)] + pub fn set_txbuf(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for Txbuf { + #[inline(always)] + fn default() -> Txbuf { + Txbuf(0) + } +} diff --git a/src/can/vals.rs b/src/can/vals.rs new file mode 100644 index 0000000..de18743 --- /dev/null +++ b/src/can/vals.rs @@ -0,0 +1,180 @@ +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Afm { + #[doc = "Dual filter"] + DUAL = 0x0, + #[doc = "Single filter"] + SINGLE = 0x01, +} +impl Afm { + #[inline(always)] + pub const fn from_bits(val: u8) -> Afm { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Afm { + #[inline(always)] + fn from(val: u8) -> Afm { + Afm::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Afm) -> u8 { + Afm::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Alc { + #[doc = "Arbitration lost in ID28/10"] + ID28_10 = 0x0, + #[doc = "Arbitration lost in ID28/9"] + ID28_9 = 0x01, + #[doc = "Arbitration lost in ID28/8"] + ID28_8 = 0x02, + #[doc = "Arbitration lost in ID28/7"] + ID28_7 = 0x03, + #[doc = "Arbitration lost in ID28/6"] + ID28_6 = 0x04, + #[doc = "Arbitration lost in ID28/5"] + ID28_5 = 0x05, + #[doc = "Arbitration lost in ID28/4"] + ID28_4 = 0x06, + #[doc = "Arbitration lost in ID28/3"] + ID28_3 = 0x07, + #[doc = "Arbitration lost in ID28/2"] + ID28_2 = 0x08, + #[doc = "Arbitration lost in ID28/1"] + ID28_1 = 0x09, + #[doc = "Arbitration lost in ID28/0"] + ID28_0 = 0x0a, + #[doc = "Arbitration lost in SRR/RTR"] + SRR_RTR = 0x0b, + #[doc = "Arbitration lost in IDE bit"] + IDE = 0x0c, + #[doc = "Arbitration lost in ID17^24"] + ID_17_24 = 0x0d, + #[doc = "Arbitration lost in ID16^24"] + ID_16_14 = 0x0e, + #[doc = "Arbitration lost in ID15^24"] + ID_15_24 = 0x0f, + #[doc = "Arbitration lost in ID14^24"] + ID_14_24 = 0x10, + #[doc = "Arbitration lost in ID13^24"] + ID_13_24 = 0x11, + #[doc = "Arbitration lost in ID12^24"] + ID_12_24 = 0x12, + #[doc = "Arbitration lost in ID11^24"] + ID_11_24 = 0x13, + #[doc = "Arbitration lost in ID10^24"] + ID_10_24 = 0x14, + #[doc = "Arbitration lost in ID9^24"] + ID_9_24 = 0x15, + #[doc = "Arbitration lost in ID8^24"] + ID_8_24 = 0x16, + #[doc = "Arbitration lost in ID7^24"] + ID_7_24 = 0x17, + #[doc = "Arbitration lost in ID6^24"] + ID_6_24 = 0x18, + #[doc = "Arbitration lost in ID5^24"] + ID_5_24 = 0x19, + #[doc = "Arbitration lost in ID4^24"] + ID_4_24 = 0x1a, + #[doc = "Arbitration lost in ID3^24"] + ID_3_24 = 0x1b, + #[doc = "Arbitration lost in ID2^24"] + ID_2_24 = 0x1c, + #[doc = "Arbitration lost in ID1^24"] + ID_1_24 = 0x1d, + #[doc = "Arbitration lost in ID0^24"] + ID_0_24 = 0x1e, + #[doc = "Arbitration lost in RTR"] + RTR = 0x1f, +} +impl Alc { + #[inline(always)] + pub const fn from_bits(val: u8) -> Alc { + unsafe { core::mem::transmute(val & 0x1f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Alc { + #[inline(always)] + fn from(val: u8) -> Alc { + Alc::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Alc) -> u8 { + Alc::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Edir { + #[doc = "Transmission"] + TX = 0x0, + #[doc = "Reception"] + RX = 0x01, +} +impl Edir { + #[inline(always)] + pub const fn from_bits(val: u8) -> Edir { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Edir { + #[inline(always)] + fn from(val: u8) -> Edir { + Edir::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Edir) -> u8 { + Edir::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Sam { + #[doc = "One sample"] + ONE = 0x0, + #[doc = "Three samples"] + THREE = 0x01, +} +impl Sam { + #[inline(always)] + pub const fn from_bits(val: u8) -> Sam { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Sam { + #[inline(always)] + fn from(val: u8) -> Sam { + Sam::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Sam) -> u8 { + Sam::to_bits(val) + } +} diff --git a/src/common.rs b/src/common.rs new file mode 100644 index 0000000..fa2bf9e --- /dev/null +++ b/src/common.rs @@ -0,0 +1,69 @@ +use core::marker::PhantomData; +#[derive(Copy, Clone, PartialEq, Eq)] +pub struct RW; +#[derive(Copy, Clone, PartialEq, Eq)] +pub struct R; +#[derive(Copy, Clone, PartialEq, Eq)] +pub struct W; +mod sealed; +pub trait Access: sealed::Access + Copy {} +impl Access for R {} +impl Access for W {} +impl Access for RW {} +pub trait Read: Access {} +impl Read for RW {} +impl Read for R {} +pub trait Write: Access {} +impl Write for RW {} +impl Write for W {} +#[derive(Copy, Clone, PartialEq, Eq)] +pub struct Reg { + ptr: *mut u8, + phantom: PhantomData<*mut (T, A)>, +} +unsafe impl Send for Reg {} +unsafe impl Sync for Reg {} +impl Reg { + #[allow(clippy::missing_safety_doc)] + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut T) -> Self { + Self { + ptr: ptr as _, + phantom: PhantomData, + } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut T { + self.ptr as _ + } +} +impl Reg { + #[inline(always)] + pub fn read(&self) -> T { + unsafe { (self.ptr as *mut T).read_volatile() } + } +} +impl Reg { + #[inline(always)] + pub fn write_value(&self, val: T) { + unsafe { (self.ptr as *mut T).write_volatile(val) } + } +} +impl Reg { + #[inline(always)] + pub fn write(&self, f: impl FnOnce(&mut T) -> R) -> R { + let mut val = Default::default(); + let res = f(&mut val); + self.write_value(val); + res + } +} +impl Reg { + #[inline(always)] + pub fn modify(&self, f: impl FnOnce(&mut T) -> R) -> R { + let mut val = self.read(); + let res = f(&mut val); + self.write_value(val); + res + } +} diff --git a/src/common/sealed.rs b/src/common/sealed.rs new file mode 100644 index 0000000..ca8ba20 --- /dev/null +++ b/src/common/sealed.rs @@ -0,0 +1,5 @@ +use super::*; +pub trait Access {} +impl Access for R {} +impl Access for W {} +impl Access for RW {} diff --git a/src/crc.rs b/src/crc.rs new file mode 100644 index 0000000..ccae395 --- /dev/null +++ b/src/crc.rs @@ -0,0 +1,39 @@ +#[doc = "Cyclic Redundancy Check"] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Crc { + ptr: *mut u8, +} +unsafe impl Send for Crc {} +unsafe impl Sync for Crc {} +impl Crc { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "CRC Control"] + #[inline(always)] + pub const fn ctl(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "CRC Data Input"] + #[inline(always)] + pub const fn datain(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } + #[doc = "CRC Seed Value"] + #[inline(always)] + pub const fn seed(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } + } + #[doc = "CRC Data Output"] + #[inline(always)] + pub const fn out(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } +} +pub mod regs; +pub mod vals; diff --git a/src/crc/regs.rs b/src/crc/regs.rs new file mode 100644 index 0000000..72d431b --- /dev/null +++ b/src/crc/regs.rs @@ -0,0 +1,102 @@ +#[doc = "CRC Control"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Ctl(pub u32); +impl Ctl { + #[doc = "CRC Polynomial Select"] + #[inline(always)] + pub const fn polysel(&self) -> super::vals::Polysel { + let val = (self.0 >> 0usize) & 0x03; + super::vals::Polysel::from_bits(val as u8) + } + #[doc = "CRC Polynomial Select"] + #[inline(always)] + pub fn set_polysel(&mut self, val: super::vals::Polysel) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + #[doc = "CRC Data Width"] + #[inline(always)] + pub const fn datawidth(&self) -> super::vals::Datawidth { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Datawidth::from_bits(val as u8) + } + #[doc = "CRC Data Width"] + #[inline(always)] + pub fn set_datawidth(&mut self, val: super::vals::Datawidth) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); + } + #[doc = "Reflect DATAOUT output data from CRC engine"] + #[inline(always)] + pub const fn outref(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Reflect DATAOUT output data from CRC engine"] + #[inline(always)] + pub fn set_outref(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Reflect DATAIN input data to CRC engine"] + #[inline(always)] + pub const fn inref(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Reflect DATAIN input data to CRC engine"] + #[inline(always)] + pub fn set_inref(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } +} +impl Default for Ctl { + #[inline(always)] + fn default() -> Ctl { + Ctl(0) + } +} +#[doc = "CRC Data Output"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Out(pub u32); +impl Out { + #[doc = "CRC data output value"] + #[inline(always)] + pub const fn crcout(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "CRC data output value"] + #[inline(always)] + pub fn set_crcout(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } +} +impl Default for Out { + #[inline(always)] + fn default() -> Out { + Out(0) + } +} +#[doc = "CRC Seed Value"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Seed(pub u32); +impl Seed { + #[doc = "CRC Seed Value"] + #[inline(always)] + pub const fn crcseed(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "CRC Seed Value"] + #[inline(always)] + pub fn set_crcseed(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } +} +impl Default for Seed { + #[inline(always)] + fn default() -> Seed { + Seed(0) + } +} diff --git a/src/crc/vals.rs b/src/crc/vals.rs new file mode 100644 index 0000000..c3ef735 --- /dev/null +++ b/src/crc/vals.rs @@ -0,0 +1,63 @@ +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Datawidth { + #[doc = "32 bits"] + BITS32 = 0x0, + #[doc = "8 bits"] + BITS8 = 0x01, +} +impl Datawidth { + #[inline(always)] + pub const fn from_bits(val: u8) -> Datawidth { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Datawidth { + #[inline(always)] + fn from(val: u8) -> Datawidth { + Datawidth::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Datawidth) -> u8 { + Datawidth::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Polysel { + #[doc = "CRC-16-CCITT"] + CRC_16_CCITT = 0x0, + #[doc = "CRC-16-IBM"] + CRC_16_IBM = 0x01, + #[doc = "CRC-8-Dallas/Maxim"] + CRC_8_DALLAS_MAXIM = 0x02, + _RESERVED_3 = 0x03, +} +impl Polysel { + #[inline(always)] + pub const fn from_bits(val: u8) -> Polysel { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Polysel { + #[inline(always)] + fn from(val: u8) -> Polysel { + Polysel::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Polysel) -> u8 { + Polysel::to_bits(val) + } +} diff --git a/src/gpio.rs b/src/gpio.rs new file mode 100644 index 0000000..73d3743 --- /dev/null +++ b/src/gpio.rs @@ -0,0 +1,89 @@ +#[doc = "General Purpose Input/Output"] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Gpio { + ptr: *mut u8, +} +unsafe impl Send for Gpio {} +unsafe impl Sync for Gpio {} +impl Gpio { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "GPIO Pin Mode Select"] + #[inline(always)] + pub const fn mode(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "GPIO Data Output Write Mask"] + #[inline(always)] + pub const fn outmask(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } + #[doc = "GPIO Data Output Value"] + #[inline(always)] + pub const fn out(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } + } + #[doc = "GPIO Data Input Value"] + #[inline(always)] + pub const fn in_(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } + #[doc = "GPIO Interrupt Enable"] + #[inline(always)] + pub const fn inten(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } + } + #[doc = "GPIO Interrupt Flag Raw"] + #[inline(always)] + pub const fn intflagraw(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } + } + #[doc = "GPIO Interrupt Flag Masked"] + #[inline(always)] + pub const fn intflagmasked(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } + } + #[doc = "GPIO Interrupt Clear"] + #[inline(always)] + pub const fn intclear(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } + } + #[doc = "GPIO Interrupt Type"] + #[inline(always)] + pub const fn inttype(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } + } + #[doc = "GPIO Interrupt Value"] + #[inline(always)] + pub const fn intvalue(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } + } + #[doc = "GPIO Interrupt Edge Both"] + #[inline(always)] + pub const fn intedgeboth(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } + } + #[doc = "GPIO De-bounce Filter"] + #[inline(always)] + pub const fn debounce(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } + } + #[doc = "GPIO Data Output Set"] + #[inline(always)] + pub const fn doset(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } + } + #[doc = "GPIO Data Output Clear"] + #[inline(always)] + pub const fn doclear(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } + } +} +pub mod regs; +pub mod vals; diff --git a/src/gpio/regs.rs b/src/gpio/regs.rs new file mode 100644 index 0000000..898f091 --- /dev/null +++ b/src/gpio/regs.rs @@ -0,0 +1,162 @@ +#[doc = "GPIO Data Output Clear"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Doclear(pub u32); +impl Doclear { + #[doc = "Pin 0 data output clear"] + #[inline(always)] + pub const fn p(&self, n: usize) -> bool { + assert!(n < 8usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Pin 0 data output clear"] + #[inline(always)] + pub fn set_p(&mut self, n: usize, val: bool) { + assert!(n < 8usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } +} +impl Default for Doclear { + #[inline(always)] + fn default() -> Doclear { + Doclear(0) + } +} +#[doc = "GPIO Data Output Set"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Doset(pub u32); +impl Doset { + #[doc = "Pin 0 data output set"] + #[inline(always)] + pub const fn p(&self, n: usize) -> bool { + assert!(n < 8usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Pin 0 data output set"] + #[inline(always)] + pub fn set_p(&mut self, n: usize, val: bool) { + assert!(n < 8usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } +} +impl Default for Doset { + #[inline(always)] + fn default() -> Doset { + Doset(0) + } +} +#[doc = "GPIO Data Input Value"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct In(pub u32); +impl In { + #[doc = "Pin 0 input data value"] + #[inline(always)] + pub const fn p(&self, n: usize) -> bool { + assert!(n < 8usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Pin 0 input data value"] + #[inline(always)] + pub fn set_p(&mut self, n: usize, val: bool) { + assert!(n < 8usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } +} +impl Default for In { + #[inline(always)] + fn default() -> In { + In(0) + } +} +#[doc = "GPIO Pin Mode Select"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Mode(pub u32); +impl Mode { + #[doc = "Pin 0 mode"] + #[inline(always)] + pub const fn p(&self, n: usize) -> super::vals::P { + assert!(n < 8usize); + let offs = 0usize + n * 2usize; + let val = (self.0 >> offs) & 0x03; + super::vals::P::from_bits(val as u8) + } + #[doc = "Pin 0 mode"] + #[inline(always)] + pub fn set_p(&mut self, n: usize, val: super::vals::P) { + assert!(n < 8usize); + let offs = 0usize + n * 2usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs); + } +} +impl Default for Mode { + #[inline(always)] + fn default() -> Mode { + Mode(0) + } +} +#[doc = "GPIO Data Output Value"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Out(pub u32); +impl Out { + #[doc = "Pin 0 output data value"] + #[inline(always)] + pub const fn p(&self, n: usize) -> bool { + assert!(n < 8usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Pin 0 output data value"] + #[inline(always)] + pub fn set_p(&mut self, n: usize, val: bool) { + assert!(n < 8usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } +} +impl Default for Out { + #[inline(always)] + fn default() -> Out { + Out(0) + } +} +#[doc = "GPIO Data Output Write Mask"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Outmask(pub u32); +impl Outmask { + #[doc = "Pin 0 output data mask"] + #[inline(always)] + pub const fn p(&self, n: usize) -> bool { + assert!(n < 8usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Pin 0 output data mask"] + #[inline(always)] + pub fn set_p(&mut self, n: usize, val: bool) { + assert!(n < 8usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } +} +impl Default for Outmask { + #[inline(always)] + fn default() -> Outmask { + Outmask(0) + } +} diff --git a/src/gpio/vals.rs b/src/gpio/vals.rs new file mode 100644 index 0000000..15a7e95 --- /dev/null +++ b/src/gpio/vals.rs @@ -0,0 +1,34 @@ +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum P { + #[doc = "Analog input"] + ANALOG = 0x0, + #[doc = "Push-pull output"] + PUSH_PULL_OUTPUT = 0x01, + #[doc = "Open-drain output"] + OPEN_DRAIN_OUTPUT = 0x02, + #[doc = "High-impedance input"] + HIGH_IMPEDANCE_INPUT = 0x03, +} +impl P { + #[inline(always)] + pub const fn from_bits(val: u8) -> P { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for P { + #[inline(always)] + fn from(val: u8) -> P { + P::from_bits(val) + } +} +impl From

for u8 { + #[inline(always)] + fn from(val: P) -> u8 { + P::to_bits(val) + } +} diff --git a/src/gptimer.rs b/src/gptimer.rs new file mode 100644 index 0000000..be9b300 --- /dev/null +++ b/src/gptimer.rs @@ -0,0 +1,29 @@ +#[doc = "General Purpose Timer"] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Gptimer { + ptr: *mut u8, +} +unsafe impl Send for Gptimer {} +unsafe impl Sync for Gptimer {} +impl Gptimer { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "GPTimer Control"] + #[inline(always)] + pub const fn ctl(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "GPTimer Counter"] + #[inline(always)] + pub const fn ctr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } +} +pub mod regs; +pub mod vals; diff --git a/src/gptimer/regs.rs b/src/gptimer/regs.rs new file mode 100644 index 0000000..ff261df --- /dev/null +++ b/src/gptimer/regs.rs @@ -0,0 +1,90 @@ +#[doc = "GPTimer Control"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Ctl(pub u32); +impl Ctl { + #[doc = "Enable"] + #[inline(always)] + pub const fn en(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Enable"] + #[inline(always)] + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Interrupt Enable"] + #[inline(always)] + pub const fn ie(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Interrupt Enable"] + #[inline(always)] + pub fn set_ie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Interrupt Flag"] + #[inline(always)] + pub const fn if_(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Interrupt Flag"] + #[inline(always)] + pub fn set_if_(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Clock Divider"] + #[inline(always)] + pub const fn div(&self) -> super::vals::Div { + let val = (self.0 >> 3usize) & 0x0f; + super::vals::Div::from_bits(val as u8) + } + #[doc = "Clock Divider"] + #[inline(always)] + pub fn set_div(&mut self, val: super::vals::Div) { + self.0 = (self.0 & !(0x0f << 3usize)) | (((val.to_bits() as u32) & 0x0f) << 3usize); + } + #[doc = "Count-down value"] + #[inline(always)] + pub const fn cdv(&self) -> u32 { + let val = (self.0 >> 8usize) & 0x00ff_ffff; + val as u32 + } + #[doc = "Count-down value"] + #[inline(always)] + pub fn set_cdv(&mut self, val: u32) { + self.0 = (self.0 & !(0x00ff_ffff << 8usize)) | (((val as u32) & 0x00ff_ffff) << 8usize); + } +} +impl Default for Ctl { + #[inline(always)] + fn default() -> Ctl { + Ctl(0) + } +} +#[doc = "GPTimer Counter"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Ctr(pub u32); +impl Ctr { + #[doc = "Counter value"] + #[inline(always)] + pub const fn ctr(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x00ff_ffff; + val as u32 + } + #[doc = "Counter value"] + #[inline(always)] + pub fn set_ctr(&mut self, val: u32) { + self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); + } +} +impl Default for Ctr { + #[inline(always)] + fn default() -> Ctr { + Ctr(0) + } +} diff --git a/src/gptimer/vals.rs b/src/gptimer/vals.rs new file mode 100644 index 0000000..056f735 --- /dev/null +++ b/src/gptimer/vals.rs @@ -0,0 +1,58 @@ +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Div { + #[doc = "PCLK/1"] + PCLK1 = 0x0, + #[doc = "PCLK/2"] + PCLK2 = 0x01, + #[doc = "PCLK/4"] + PCLK4 = 0x02, + #[doc = "PCLK/8"] + PCLK8 = 0x03, + #[doc = "PCLK/16"] + PCLK16 = 0x04, + #[doc = "PCLK/32"] + PCLK32 = 0x05, + #[doc = "PCLK/64"] + PCLK64 = 0x06, + #[doc = "PCLK/128"] + PCLK128 = 0x07, + #[doc = "PCLK/256"] + PCLK256 = 0x08, + #[doc = "PCLK/512"] + PCLK512 = 0x09, + #[doc = "PCLK/1024"] + PCLK1024 = 0x0a, + #[doc = "PCLK/2048"] + PCLK2048 = 0x0b, + #[doc = "PCLK/4096"] + PCLK4096 = 0x0c, + #[doc = "PCLK/8192"] + PCLK8192 = 0x0d, + #[doc = "PCLK/16384"] + PCLK16384 = 0x0e, + #[doc = "PCLK/32768"] + PCLK32768 = 0x0f, +} +impl Div { + #[inline(always)] + pub const fn from_bits(val: u8) -> Div { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Div { + #[inline(always)] + fn from(val: u8) -> Div { + Div::from_bits(val) + } +} +impl From

for u8 { + #[inline(always)] + fn from(val: Div) -> u8 { + Div::to_bits(val) + } +} diff --git a/src/i2c.rs b/src/i2c.rs new file mode 100644 index 0000000..55b0095 --- /dev/null +++ b/src/i2c.rs @@ -0,0 +1,99 @@ +#[doc = "Inter-Integrated Circuit"] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct I2c { + ptr: *mut u8, +} +unsafe impl Send for I2c {} +unsafe impl Sync for I2c {} +impl I2c { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "I2C Control Set"] + #[inline(always)] + pub const fn conset(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "I2C Control Clear"] + #[inline(always)] + pub const fn conclr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } + #[doc = "I2C Status"] + #[inline(always)] + pub const fn stat(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } + } + #[doc = "I2C Data"] + #[inline(always)] + pub const fn dat(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } + #[doc = "I2C Clock Control"] + #[inline(always)] + pub const fn clk(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } + } + #[doc = "I2C Slave Address"] + #[inline(always)] + pub const fn adr0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } + } + #[doc = "I2C Slave Address Mask"] + #[inline(always)] + pub const fn adrm0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } + } + #[doc = "I2C Extended Slave Address 0"] + #[inline(always)] + pub const fn xadr0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } + } + #[doc = "I2C Extended Slave Address Mask 0"] + #[inline(always)] + pub const fn xadrm0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } + } + #[doc = "I2C Software Reset"] + #[inline(always)] + pub const fn rst(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } + } + #[doc = "I2C Slave Address"] + #[inline(always)] + pub const fn adr1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } + } + #[doc = "I2C Slave Address Mask"] + #[inline(always)] + pub const fn adrm1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } + } + #[doc = "I2C Slave Address"] + #[inline(always)] + pub const fn adr2(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } + } + #[doc = "I2C Slave Address Mask"] + #[inline(always)] + pub const fn adrm2(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } + } + #[doc = "I2C Slave Address"] + #[inline(always)] + pub const fn adr3(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) } + } + #[doc = "I2C Slave Address Mask"] + #[inline(always)] + pub const fn adrm3(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) } + } +} +pub mod regs; +pub mod vals; diff --git a/src/i2c/regs.rs b/src/i2c/regs.rs new file mode 100644 index 0000000..fe59f2b --- /dev/null +++ b/src/i2c/regs.rs @@ -0,0 +1,384 @@ +#[doc = "I2C Slave Address"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Adr(pub u32); +impl Adr { + #[doc = "General Call Enable"] + #[inline(always)] + pub const fn gc(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "General Call Enable"] + #[inline(always)] + pub fn set_gc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Slave Address"] + #[inline(always)] + pub const fn addr(&self) -> u8 { + let val = (self.0 >> 1usize) & 0x7f; + val as u8 + } + #[doc = "Slave Address"] + #[inline(always)] + pub fn set_addr(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 1usize)) | (((val as u32) & 0x7f) << 1usize); + } +} +impl Default for Adr { + #[inline(always)] + fn default() -> Adr { + Adr(0) + } +} +#[doc = "I2C Slave Address Mask"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Adrm(pub u32); +impl Adrm { + #[doc = "Slave Address Mask"] + #[inline(always)] + pub const fn mask(&self) -> u8 { + let val = (self.0 >> 1usize) & 0x7f; + val as u8 + } + #[doc = "Slave Address Mask"] + #[inline(always)] + pub fn set_mask(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 1usize)) | (((val as u32) & 0x7f) << 1usize); + } +} +impl Default for Adrm { + #[inline(always)] + fn default() -> Adrm { + Adrm(0) + } +} +#[doc = "I2C Clock Control"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Clk(pub u32); +impl Clk { + #[doc = "Fscl = PCLK / (2^M * (N+1) * 10)"] + #[inline(always)] + pub const fn n(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Fscl = PCLK / (2^M * (N+1) * 10)"] + #[inline(always)] + pub fn set_n(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "Fsamp = PCLK / 2^M"] + #[inline(always)] + pub const fn m(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x07; + val as u8 + } + #[doc = "Fsamp = PCLK / 2^M"] + #[inline(always)] + pub fn set_m(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val as u32) & 0x07) << 4usize); + } +} +impl Default for Clk { + #[inline(always)] + fn default() -> Clk { + Clk(0) + } +} +#[doc = "I2C Control Clear"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Conclr(pub u32); +impl Conclr { + #[doc = "Assert Acknowledge Clear"] + #[inline(always)] + pub const fn aac(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Assert Acknowledge Clear"] + #[inline(always)] + pub fn set_aac(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "I2C Interrupt Clear"] + #[inline(always)] + pub const fn sic(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "I2C Interrupt Clear"] + #[inline(always)] + pub fn set_sic(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "START Flag Clear"] + #[inline(always)] + pub const fn stac(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "START Flag Clear"] + #[inline(always)] + pub fn set_stac(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "I2C Disable"] + #[inline(always)] + pub const fn i2cenc(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "I2C Disable"] + #[inline(always)] + pub fn set_i2cenc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "I2C Interrupt Disable"] + #[inline(always)] + pub const fn i2ciec(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "I2C Interrupt Disable"] + #[inline(always)] + pub fn set_i2ciec(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } +} +impl Default for Conclr { + #[inline(always)] + fn default() -> Conclr { + Conclr(0) + } +} +#[doc = "I2C Control Set"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Conset(pub u32); +impl Conset { + #[doc = "Slave Address Flag"] + #[inline(always)] + pub const fn adrf(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Slave Address Flag"] + #[inline(always)] + pub fn set_adrf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Extended Slave Address Flag (10-bit addressing)"] + #[inline(always)] + pub const fn xadrf(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Extended Slave Address Flag (10-bit addressing)"] + #[inline(always)] + pub fn set_xadrf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Assert Acknowledge Flag"] + #[inline(always)] + pub const fn aa(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Assert Acknowledge Flag"] + #[inline(always)] + pub fn set_aa(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "I2C Interrupt Flag"] + #[inline(always)] + pub const fn si(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "I2C Interrupt Flag"] + #[inline(always)] + pub fn set_si(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "STOP Flag"] + #[inline(always)] + pub const fn sto(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "STOP Flag"] + #[inline(always)] + pub fn set_sto(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "START Flag"] + #[inline(always)] + pub const fn sta(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "START Flag"] + #[inline(always)] + pub fn set_sta(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "I2C Enable"] + #[inline(always)] + pub const fn i2cen(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "I2C Enable"] + #[inline(always)] + pub fn set_i2cen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "I2C Interrupt Enable"] + #[inline(always)] + pub const fn i2cie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "I2C Interrupt Enable"] + #[inline(always)] + pub fn set_i2cie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "General Call Flag"] + #[inline(always)] + pub const fn gcf(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "General Call Flag"] + #[inline(always)] + pub fn set_gcf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } +} +impl Default for Conset { + #[inline(always)] + fn default() -> Conset { + Conset(0) + } +} +#[doc = "I2C Data"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Dat(pub u32); +impl Dat { + #[doc = "Data values received or to be transmitted"] + #[inline(always)] + pub const fn data(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Data values received or to be transmitted"] + #[inline(always)] + pub fn set_data(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } +} +impl Default for Dat { + #[inline(always)] + fn default() -> Dat { + Dat(0) + } +} +#[doc = "I2C Software Reset"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Rst(pub u32); +impl Rst { + #[doc = "I2C Software Reset"] + #[inline(always)] + pub const fn rst(&self) -> super::vals::Rst { + let val = (self.0 >> 0usize) & 0xff; + super::vals::Rst::from_bits(val as u8) + } + #[doc = "I2C Software Reset"] + #[inline(always)] + pub fn set_rst(&mut self, val: super::vals::Rst) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); + } +} +impl Default for Rst { + #[inline(always)] + fn default() -> Rst { + Rst(0) + } +} +#[doc = "I2C Status"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Stat(pub u32); +impl Stat { + #[doc = "Status code for I2C engine"] + #[inline(always)] + pub const fn status(&self) -> super::vals::Status { + let val = (self.0 >> 0usize) & 0xff; + super::vals::Status::from_bits(val as u8) + } + #[doc = "Status code for I2C engine"] + #[inline(always)] + pub fn set_status(&mut self, val: super::vals::Status) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); + } +} +impl Default for Stat { + #[inline(always)] + fn default() -> Stat { + Stat(0) + } +} +#[doc = "I2C Extended Slave Address 0"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Xadr0(pub u32); +impl Xadr0 { + #[doc = "Extended Slave Address"] + #[inline(always)] + pub const fn addr(&self) -> u16 { + let val = (self.0 >> 1usize) & 0x03ff; + val as u16 + } + #[doc = "Extended Slave Address"] + #[inline(always)] + pub fn set_addr(&mut self, val: u16) { + self.0 = (self.0 & !(0x03ff << 1usize)) | (((val as u32) & 0x03ff) << 1usize); + } +} +impl Default for Xadr0 { + #[inline(always)] + fn default() -> Xadr0 { + Xadr0(0) + } +} +#[doc = "I2C Extended Slave Address Mask 0"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Xadrm0(pub u32); +impl Xadrm0 { + #[doc = "Extended Slave Address Mask"] + #[inline(always)] + pub const fn mask(&self) -> u16 { + let val = (self.0 >> 1usize) & 0x03ff; + val as u16 + } + #[doc = "Extended Slave Address Mask"] + #[inline(always)] + pub fn set_mask(&mut self, val: u16) { + self.0 = (self.0 & !(0x03ff << 1usize)) | (((val as u32) & 0x03ff) << 1usize); + } +} +impl Default for Xadrm0 { + #[inline(always)] + fn default() -> Xadrm0 { + Xadrm0(0) + } +} diff --git a/src/i2c/vals.rs b/src/i2c/vals.rs new file mode 100644 index 0000000..70fea6f --- /dev/null +++ b/src/i2c/vals.rs @@ -0,0 +1,337 @@ +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub struct Rst(pub u8); +impl Rst { + #[doc = "Perform I2C software reset"] + pub const RESET: Self = Self(0x07); +} +impl Rst { + pub const fn from_bits(val: u8) -> Rst { + Self(val & 0xff) + } + pub const fn to_bits(self) -> u8 { + self.0 + } +} +impl From for Rst { + #[inline(always)] + fn from(val: u8) -> Rst { + Rst::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Rst) -> u8 { + Rst::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Status { + #[doc = "Bus Error (master mode only)"] + BUS_ERROR = 0x0, + _RESERVED_1 = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, + #[doc = "START condition transmitted"] + START = 0x08, + _RESERVED_9 = 0x09, + _RESERVED_a = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, + #[doc = "Repeated START condition transmitted"] + RSTART = 0x10, + _RESERVED_11 = 0x11, + _RESERVED_12 = 0x12, + _RESERVED_13 = 0x13, + _RESERVED_14 = 0x14, + _RESERVED_15 = 0x15, + _RESERVED_16 = 0x16, + _RESERVED_17 = 0x17, + #[doc = "Address and Write bit transmitted, ACK received"] + SLAW_TX_ACK = 0x18, + _RESERVED_19 = 0x19, + _RESERVED_1a = 0x1a, + _RESERVED_1b = 0x1b, + _RESERVED_1c = 0x1c, + _RESERVED_1d = 0x1d, + _RESERVED_1e = 0x1e, + _RESERVED_1f = 0x1f, + #[doc = "Address and Write bit transmitted, NACK received"] + SLAW_TX_NACK = 0x20, + _RESERVED_21 = 0x21, + _RESERVED_22 = 0x22, + _RESERVED_23 = 0x23, + _RESERVED_24 = 0x24, + _RESERVED_25 = 0x25, + _RESERVED_26 = 0x26, + _RESERVED_27 = 0x27, + #[doc = "Data byte transmitted in master mode, ACK received"] + MDATA_TX_ACK = 0x28, + _RESERVED_29 = 0x29, + _RESERVED_2a = 0x2a, + _RESERVED_2b = 0x2b, + _RESERVED_2c = 0x2c, + _RESERVED_2d = 0x2d, + _RESERVED_2e = 0x2e, + _RESERVED_2f = 0x2f, + #[doc = "Data byte transmitted in master mode, NACK received"] + MDATA_TX_NACK = 0x30, + _RESERVED_31 = 0x31, + _RESERVED_32 = 0x32, + _RESERVED_33 = 0x33, + _RESERVED_34 = 0x34, + _RESERVED_35 = 0x35, + _RESERVED_36 = 0x36, + _RESERVED_37 = 0x37, + #[doc = "Arbitration lost in address or data byte"] + ARB_LOST = 0x38, + _RESERVED_39 = 0x39, + _RESERVED_3a = 0x3a, + _RESERVED_3b = 0x3b, + _RESERVED_3c = 0x3c, + _RESERVED_3d = 0x3d, + _RESERVED_3e = 0x3e, + _RESERVED_3f = 0x3f, + #[doc = "Address and read bit transmitted, ACK received"] + SLAR_TX_ACK = 0x40, + _RESERVED_41 = 0x41, + _RESERVED_42 = 0x42, + _RESERVED_43 = 0x43, + _RESERVED_44 = 0x44, + _RESERVED_45 = 0x45, + _RESERVED_46 = 0x46, + _RESERVED_47 = 0x47, + #[doc = "Address and read bit transmitted, NACK received"] + SLAR_TX_NACK = 0x48, + _RESERVED_49 = 0x49, + _RESERVED_4a = 0x4a, + _RESERVED_4b = 0x4b, + _RESERVED_4c = 0x4c, + _RESERVED_4d = 0x4d, + _RESERVED_4e = 0x4e, + _RESERVED_4f = 0x4f, + #[doc = "Data byte received in master mode, ACK transmitted"] + MDATA_RX_ACK = 0x50, + _RESERVED_51 = 0x51, + _RESERVED_52 = 0x52, + _RESERVED_53 = 0x53, + _RESERVED_54 = 0x54, + _RESERVED_55 = 0x55, + _RESERVED_56 = 0x56, + _RESERVED_57 = 0x57, + #[doc = "Data byte received in master mode, NACK transmitted"] + MDATA_RX_NACK = 0x58, + _RESERVED_59 = 0x59, + _RESERVED_5a = 0x5a, + _RESERVED_5b = 0x5b, + _RESERVED_5c = 0x5c, + _RESERVED_5d = 0x5d, + _RESERVED_5e = 0x5e, + _RESERVED_5f = 0x5f, + #[doc = "Slave address and write bit received, ACK transmitted"] + SLAW_RX_ACK = 0x60, + _RESERVED_61 = 0x61, + _RESERVED_62 = 0x62, + _RESERVED_63 = 0x63, + _RESERVED_64 = 0x64, + _RESERVED_65 = 0x65, + _RESERVED_66 = 0x66, + _RESERVED_67 = 0x67, + #[doc = "Arbitration lost in address as master, slave address and write bit received, ACK transmitted"] + ARB_LOST_SLAW_RX_ACK = 0x68, + _RESERVED_69 = 0x69, + _RESERVED_6a = 0x6a, + _RESERVED_6b = 0x6b, + _RESERVED_6c = 0x6c, + _RESERVED_6d = 0x6d, + _RESERVED_6e = 0x6e, + _RESERVED_6f = 0x6f, + #[doc = "General call received, ACK returned"] + GC_ACK = 0x70, + _RESERVED_71 = 0x71, + _RESERVED_72 = 0x72, + _RESERVED_73 = 0x73, + _RESERVED_74 = 0x74, + _RESERVED_75 = 0x75, + _RESERVED_76 = 0x76, + _RESERVED_77 = 0x77, + _RESERVED_78 = 0x78, + _RESERVED_79 = 0x79, + _RESERVED_7a = 0x7a, + _RESERVED_7b = 0x7b, + _RESERVED_7c = 0x7c, + _RESERVED_7d = 0x7d, + _RESERVED_7e = 0x7e, + _RESERVED_7f = 0x7f, + #[doc = "Data byte received after slave address received, ACK transmitted"] + SDATA_RX_ACK = 0x80, + _RESERVED_81 = 0x81, + _RESERVED_82 = 0x82, + _RESERVED_83 = 0x83, + _RESERVED_84 = 0x84, + _RESERVED_85 = 0x85, + _RESERVED_86 = 0x86, + _RESERVED_87 = 0x87, + #[doc = "Data byte received after slave address received, NACK transmitted"] + SDATA_RX_NACK = 0x88, + _RESERVED_89 = 0x89, + _RESERVED_8a = 0x8a, + _RESERVED_8b = 0x8b, + _RESERVED_8c = 0x8c, + _RESERVED_8d = 0x8d, + _RESERVED_8e = 0x8e, + _RESERVED_8f = 0x8f, + #[doc = "Data byte received after general call address received, ACK transmitted"] + DATA_RX_GC_ACK = 0x90, + _RESERVED_91 = 0x91, + _RESERVED_92 = 0x92, + _RESERVED_93 = 0x93, + _RESERVED_94 = 0x94, + _RESERVED_95 = 0x95, + _RESERVED_96 = 0x96, + _RESERVED_97 = 0x97, + _RESERVED_98 = 0x98, + _RESERVED_99 = 0x99, + _RESERVED_9a = 0x9a, + _RESERVED_9b = 0x9b, + _RESERVED_9c = 0x9c, + _RESERVED_9d = 0x9d, + _RESERVED_9e = 0x9e, + _RESERVED_9f = 0x9f, + #[doc = "STOP or repeated START condition received in slave mode"] + STOP_RSTART_RX = 0xa0, + _RESERVED_a1 = 0xa1, + _RESERVED_a2 = 0xa2, + _RESERVED_a3 = 0xa3, + _RESERVED_a4 = 0xa4, + _RESERVED_a5 = 0xa5, + _RESERVED_a6 = 0xa6, + _RESERVED_a7 = 0xa7, + #[doc = "Address and read bit received, ACK transmitted"] + SLAR_RX_ACK = 0xa8, + _RESERVED_a9 = 0xa9, + _RESERVED_aa = 0xaa, + _RESERVED_ab = 0xab, + _RESERVED_ac = 0xac, + _RESERVED_ad = 0xad, + _RESERVED_ae = 0xae, + _RESERVED_af = 0xaf, + #[doc = "Arbitration lost in address as master, address and read bit received, ACK transmitted"] + ARB_LOST_SLAR_RX_ACK = 0xb0, + _RESERVED_b1 = 0xb1, + _RESERVED_b2 = 0xb2, + _RESERVED_b3 = 0xb3, + _RESERVED_b4 = 0xb4, + _RESERVED_b5 = 0xb5, + _RESERVED_b6 = 0xb6, + _RESERVED_b7 = 0xb7, + #[doc = "Data byte transmitted in slave mode, ACK received"] + SDATA_TX_ACK = 0xb8, + _RESERVED_b9 = 0xb9, + _RESERVED_ba = 0xba, + _RESERVED_bb = 0xbb, + _RESERVED_bc = 0xbc, + _RESERVED_bd = 0xbd, + _RESERVED_be = 0xbe, + _RESERVED_bf = 0xbf, + #[doc = "Data byte transmitted in slave mode, NACK received"] + SDATA_TX_NACK = 0xc0, + _RESERVED_c1 = 0xc1, + _RESERVED_c2 = 0xc2, + _RESERVED_c3 = 0xc3, + _RESERVED_c4 = 0xc4, + _RESERVED_c5 = 0xc5, + _RESERVED_c6 = 0xc6, + _RESERVED_c7 = 0xc7, + #[doc = "Last data byte transmitted in slave mode, ACK received"] + SDATA_LAST_TX_ACK = 0xc8, + _RESERVED_c9 = 0xc9, + _RESERVED_ca = 0xca, + _RESERVED_cb = 0xcb, + _RESERVED_cc = 0xcc, + _RESERVED_cd = 0xcd, + _RESERVED_ce = 0xce, + _RESERVED_cf = 0xcf, + #[doc = "Last data byte transmitted in slave mode, NACK received"] + SDATA_LAST_TX_NACK = 0xd0, + _RESERVED_d1 = 0xd1, + _RESERVED_d2 = 0xd2, + _RESERVED_d3 = 0xd3, + _RESERVED_d4 = 0xd4, + _RESERVED_d5 = 0xd5, + _RESERVED_d6 = 0xd6, + _RESERVED_d7 = 0xd7, + _RESERVED_d8 = 0xd8, + _RESERVED_d9 = 0xd9, + _RESERVED_da = 0xda, + _RESERVED_db = 0xdb, + _RESERVED_dc = 0xdc, + _RESERVED_dd = 0xdd, + _RESERVED_de = 0xde, + _RESERVED_df = 0xdf, + #[doc = "Second address byte received in slave mode, ACK transmitted"] + SECOND_ADDR_TX_ACK = 0xe0, + _RESERVED_e1 = 0xe1, + _RESERVED_e2 = 0xe2, + _RESERVED_e3 = 0xe3, + _RESERVED_e4 = 0xe4, + _RESERVED_e5 = 0xe5, + _RESERVED_e6 = 0xe6, + _RESERVED_e7 = 0xe7, + _RESERVED_e8 = 0xe8, + _RESERVED_e9 = 0xe9, + _RESERVED_ea = 0xea, + _RESERVED_eb = 0xeb, + _RESERVED_ec = 0xec, + _RESERVED_ed = 0xed, + _RESERVED_ee = 0xee, + _RESERVED_ef = 0xef, + #[doc = "Second address byte received in slave mode, NACK transmitted"] + SECOND_ADDR_TX_NACK = 0xf0, + _RESERVED_f1 = 0xf1, + _RESERVED_f2 = 0xf2, + _RESERVED_f3 = 0xf3, + _RESERVED_f4 = 0xf4, + _RESERVED_f5 = 0xf5, + _RESERVED_f6 = 0xf6, + _RESERVED_f7 = 0xf7, + #[doc = "No relevant status information"] + NO_INFO = 0xf8, + _RESERVED_f9 = 0xf9, + _RESERVED_fa = 0xfa, + _RESERVED_fb = 0xfb, + _RESERVED_fc = 0xfc, + _RESERVED_fd = 0xfd, + _RESERVED_fe = 0xfe, + _RESERVED_ff = 0xff, +} +impl Status { + #[inline(always)] + pub const fn from_bits(val: u8) -> Status { + unsafe { core::mem::transmute(val & 0xff) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Status { + #[inline(always)] + fn from(val: u8) -> Status { + Status::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Status) -> u8 { + Status::to_bits(val) + } +} diff --git a/src/lib.rs b/src/lib.rs new file mode 100644 index 0000000..34d8f2a --- /dev/null +++ b/src/lib.rs @@ -0,0 +1,155 @@ +#![no_std] +#![allow(non_camel_case_types)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2a63600 2024-11-04))"] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub enum Interrupt { + #[doc = "0 - MEMCTL Interrupt"] + MEMCTL = 0, + #[doc = "1 - WWDT Interrupt"] + WWDT = 1, + #[doc = "2 - RTC Interrupt"] + RTC = 2, + #[doc = "3 - ADC 0 Interrupt"] + ADC0 = 3, + #[doc = "4 - ADC 1 Interrupt"] + ADC1 = 4, + #[doc = "5 - ADC 2 Interrupt"] + ADC2 = 5, + #[doc = "6 - ADC 3 Interrupt"] + ADC3 = 6, + #[doc = "7 - Timer A Interrupt"] + TIMERA = 7, + #[doc = "8 - Timer B Interrupt"] + TIMERB = 8, + #[doc = "9 - Timer C Interrupt"] + TIMERC = 9, + #[doc = "10 - Timer D Interrupt"] + TIMERD = 10, + #[doc = "11 - Timer A QEP Interrupt"] + TIMERAQEP = 11, + #[doc = "12 - Timer B QEP Interrupt"] + TIMERBQEP = 12, + #[doc = "13 - Timer C QEP Interrupt"] + TIMERCQEP = 13, + #[doc = "14 - Timer D QEP Interrupt"] + TIMERDQEP = 14, + #[doc = "15 - GPIOA Interrupt"] + GPIOA = 15, + #[doc = "16 - GPIO B Interrupt"] + GPIOB = 16, + #[doc = "17 - GPIO C Interrupt"] + GPIOC = 17, + #[doc = "18 - GPIO D Interrupt"] + GPIOD = 18, + #[doc = "19 - GPIO E Interrupt"] + GPIOE = 19, + #[doc = "20 - GPIO F Interrupt"] + GPIOF = 20, + #[doc = "21 - GPIO G Interrupt"] + GPIOG = 21, + #[doc = "22 - I2C Interrupt"] + I2C = 22, + #[doc = "23 - USART/SSP A Interrupt"] + USARTA_SSPA = 23, + #[doc = "24 - USART/SSP B Interrupt"] + USARTB_SSPB = 24, + #[doc = "25 - USART/SSP C Interrupt"] + USARTC_SSPC = 25, + #[doc = "26 - USART/SSP D Interrupt"] + USARTD_SSPD = 26, + #[doc = "27 - CAN Interrupt"] + CAN = 27, + #[doc = "28 - GPTimer A Interrupt"] + GPTIMERA = 28, + #[doc = "29 - GPTimer B Interrupt"] + GPTIMERB = 29, + #[doc = "30 - SCC Interrupt"] + SCC = 30, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[cfg(feature = "rt")] +mod _vectors; +#[doc = "Analog to Digital Converter (ADC) and Dynamic Triggering and Sampling Engine (DTSE)"] +pub const ADC: adc::Adc = unsafe { adc::Adc::from_ptr(0x4000_0000usize as _) }; +#[doc = "Inter-Integrated Circuit"] +pub const I2C: i2c::I2c = unsafe { i2c::I2c::from_ptr(0x4001_0000usize as _) }; +#[doc = "Universal Synchronous Asynchronous Receive Transmit"] +pub const USARTA: usart::Usart = unsafe { usart::Usart::from_ptr(0x4002_0000usize as _) }; +#[doc = "Synchronous Serial Peripheral"] +pub const SSPA: ssp::Ssp = unsafe { ssp::Ssp::from_ptr(0x4002_0000usize as _) }; +#[doc = "Universal Synchronous Asynchronous Receive Transmit"] +pub const USARTB: usart::Usart = unsafe { usart::Usart::from_ptr(0x4003_0000usize as _) }; +#[doc = "Synchronous Serial Peripheral"] +pub const SSPB: ssp::Ssp = unsafe { ssp::Ssp::from_ptr(0x4003_0000usize as _) }; +#[doc = "Universal Synchronous Asynchronous Receive Transmit"] +pub const USARTC: usart::Usart = unsafe { usart::Usart::from_ptr(0x4004_0000usize as _) }; +#[doc = "Synchronous Serial Peripheral"] +pub const SSPC: ssp::Ssp = unsafe { ssp::Ssp::from_ptr(0x4004_0000usize as _) }; +#[doc = "Universal Synchronous Asynchronous Receive Transmit"] +pub const USARTD: usart::Usart = unsafe { usart::Usart::from_ptr(0x4005_0000usize as _) }; +#[doc = "Synchronous Serial Peripheral"] +pub const SSPD: ssp::Ssp = unsafe { ssp::Ssp::from_ptr(0x4005_0000usize as _) }; +#[doc = "Timer"] +pub const TIMERA: timer::Timer = unsafe { timer::Timer::from_ptr(0x4006_0000usize as _) }; +#[doc = "Timer"] +pub const TIMERB: timer::Timer = unsafe { timer::Timer::from_ptr(0x4007_0000usize as _) }; +#[doc = "Timer"] +pub const TIMERC: timer::Timer = unsafe { timer::Timer::from_ptr(0x4008_0000usize as _) }; +#[doc = "Timer"] +pub const TIMERD: timer::Timer = unsafe { timer::Timer::from_ptr(0x4009_0000usize as _) }; +#[doc = "Controller Area Network"] +pub const CAN: can::Can = unsafe { can::Can::from_ptr(0x400a_0000usize as _) }; +#[doc = "General Purpose Timer"] +pub const GPTIMERA: gptimer::Gptimer = unsafe { gptimer::Gptimer::from_ptr(0x400b_0000usize as _) }; +#[doc = "General Purpose Timer"] +pub const GPTIMERB: gptimer::Gptimer = unsafe { gptimer::Gptimer::from_ptr(0x400c_0000usize as _) }; +#[doc = "Memory Controller"] +pub const MEMCTL: memctl::Memctl = unsafe { memctl::Memctl::from_ptr(0x400d_0000usize as _) }; +#[doc = "System and Clock Control"] +pub const SCC: scc::Scc = unsafe { scc::Scc::from_ptr(0x400d_0400usize as _) }; +#[doc = "Windowed Watchdog Timer"] +pub const WWDT: wwdt::Wwdt = unsafe { wwdt::Wwdt::from_ptr(0x400d_0800usize as _) }; +#[doc = "Real-Time Clock (RTC) with Calendar"] +pub const RTC: rtc::Rtc = unsafe { rtc::Rtc::from_ptr(0x400d_0c00usize as _) }; +#[doc = "Cyclic Redundancy Check"] +pub const CRC: crc::Crc = unsafe { crc::Crc::from_ptr(0x400d_1000usize as _) }; +#[doc = "General Purpose Input/Output"] +pub const GPIOA: gpio::Gpio = unsafe { gpio::Gpio::from_ptr(0x400d_1400usize as _) }; +#[doc = "General Purpose Input/Output"] +pub const GPIOB: gpio::Gpio = unsafe { gpio::Gpio::from_ptr(0x400d_1800usize as _) }; +#[doc = "General Purpose Input/Output"] +pub const GPIOC: gpio::Gpio = unsafe { gpio::Gpio::from_ptr(0x400d_1c00usize as _) }; +#[doc = "General Purpose Input/Output"] +pub const GPIOD: gpio::Gpio = unsafe { gpio::Gpio::from_ptr(0x400d_2000usize as _) }; +#[doc = "General Purpose Input/Output"] +pub const GPIOE: gpio::Gpio = unsafe { gpio::Gpio::from_ptr(0x400d_2400usize as _) }; +#[doc = "General Purpose Input/Output"] +pub const GPIOF: gpio::Gpio = unsafe { gpio::Gpio::from_ptr(0x400d_2800usize as _) }; +#[doc = "General Purpose Input/Output"] +pub const GPIOG: gpio::Gpio = unsafe { gpio::Gpio::from_ptr(0x400d_2c00usize as _) }; +#[doc = r" Number available in the NVIC for configuring priority"] +#[cfg(feature = "rt")] +pub const NVIC_PRIO_BITS: u8 = 3; +#[cfg(feature = "rt")] +pub use cortex_m_rt::interrupt; +#[cfg(feature = "rt")] +pub use Interrupt as interrupt; +pub mod adc; +pub mod can; +pub mod common; +pub mod crc; +pub mod gpio; +pub mod gptimer; +pub mod i2c; +pub mod memctl; +pub mod rtc; +pub mod scc; +pub mod ssp; +pub mod timer; +pub mod usart; +pub mod wwdt; diff --git a/src/memctl.rs b/src/memctl.rs new file mode 100644 index 0000000..6f71d1a --- /dev/null +++ b/src/memctl.rs @@ -0,0 +1,49 @@ +#[doc = "Memory Controller"] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Memctl { + ptr: *mut u8, +} +unsafe impl Send for Memctl {} +unsafe impl Sync for Memctl {} +impl Memctl { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Memory Controller Configuration"] + #[inline(always)] + pub const fn memctl(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "Memory Controller Status"] + #[inline(always)] + pub const fn memstatus(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } + #[doc = "FLASH Lock Access"] + #[inline(always)] + pub const fn flashlock(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } + } + #[doc = "FLASH Page"] + #[inline(always)] + pub const fn flashpage(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } + #[doc = "SWD Unlock"] + #[inline(always)] + pub const fn swdunlock(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } + } + #[doc = "FLASH Erase"] + #[inline(always)] + pub const fn flasherase(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } + } +} +pub mod regs; +pub mod vals; diff --git a/src/memctl/regs.rs b/src/memctl/regs.rs new file mode 100644 index 0000000..4f94ce4 --- /dev/null +++ b/src/memctl/regs.rs @@ -0,0 +1,294 @@ +#[doc = "FLASH Erase"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Flasherase(pub u32); +impl Flasherase { + #[doc = "Key for erase operations"] + #[inline(always)] + pub const fn key(&self) -> super::vals::Key { + let val = (self.0 >> 0usize) & 0xffff_ffff; + super::vals::Key::from_bits(val as u32) + } + #[doc = "Key for erase operations"] + #[inline(always)] + pub fn set_key(&mut self, val: super::vals::Key) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) + | (((val.to_bits() as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for Flasherase { + #[inline(always)] + fn default() -> Flasherase { + Flasherase(0) + } +} +#[doc = "FLASH Lock Access"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Flashlock(pub u32); +impl Flashlock { + #[doc = "Flash Lock Value for Memory Controller Operations"] + #[inline(always)] + pub const fn flashlock(&self) -> super::vals::Flashlock { + let val = (self.0 >> 0usize) & 0xffff_ffff; + super::vals::Flashlock::from_bits(val as u32) + } + #[doc = "Flash Lock Value for Memory Controller Operations"] + #[inline(always)] + pub fn set_flashlock(&mut self, val: super::vals::Flashlock) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) + | (((val.to_bits() as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for Flashlock { + #[inline(always)] + fn default() -> Flashlock { + Flashlock(0) + } +} +#[doc = "FLASH Page"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Flashpage(pub u32); +impl Flashpage { + #[doc = "Flash page selection"] + #[inline(always)] + pub const fn page(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x7f; + val as u8 + } + #[doc = "Flash page selection"] + #[inline(always)] + pub fn set_page(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize); + } +} +impl Default for Flashpage { + #[inline(always)] + fn default() -> Flashpage { + Flashpage(0) + } +} +#[doc = "Memory Controller Configuration"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Memctl(pub u32); +impl Memctl { + #[doc = "FLASH Access Wait States"] + #[inline(always)] + pub const fn wstate(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "FLASH Access Wait States"] + #[inline(always)] + pub fn set_wstate(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "MCLK Divider"] + #[inline(always)] + pub const fn mclkdiv(&self) -> super::vals::Mclkdiv { + let val = (self.0 >> 4usize) & 0x0f; + super::vals::Mclkdiv::from_bits(val as u8) + } + #[doc = "MCLK Divider"] + #[inline(always)] + pub fn set_mclkdiv(&mut self, val: super::vals::Mclkdiv) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val.to_bits() as u32) & 0x0f) << 4usize); + } + #[doc = "Write Word Data Count"] + #[inline(always)] + pub const fn writewordcnt(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x03; + val as u8 + } + #[doc = "Write Word Data Count"] + #[inline(always)] + pub fn set_writewordcnt(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize); + } + #[doc = "ECC Single bit Error Interrupt Enable"] + #[inline(always)] + pub const fn seie(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "ECC Single bit Error Interrupt Enable"] + #[inline(always)] + pub fn set_seie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "ECC Dual bit Error Interrupt Enable"] + #[inline(always)] + pub const fn deie(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "ECC Dual bit Error Interrupt Enable"] + #[inline(always)] + pub fn set_deie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Invalid Memory Address Access Interrupt Enable"] + #[inline(always)] + pub const fn invaddrie(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Invalid Memory Address Access Interrupt Enable"] + #[inline(always)] + pub fn set_invaddrie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "FLASH Standby Mode"] + #[inline(always)] + pub const fn stdby(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "FLASH Standby Mode"] + #[inline(always)] + pub fn set_stdby(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } + #[doc = "SRAM ECC Disable"] + #[inline(always)] + pub const fn eccdis(&self) -> bool { + let val = (self.0 >> 20usize) & 0x01; + val != 0 + } + #[doc = "SRAM ECC Disable"] + #[inline(always)] + pub fn set_eccdis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); + } + #[doc = "FLASH Read Cache Disable"] + #[inline(always)] + pub const fn cachedis(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "FLASH Read Cache Disable"] + #[inline(always)] + pub fn set_cachedis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "MCLK Mux Select"] + #[inline(always)] + pub const fn mclksel(&self) -> super::vals::Mclksel { + let val = (self.0 >> 22usize) & 0x01; + super::vals::Mclksel::from_bits(val as u8) + } + #[doc = "MCLK Mux Select"] + #[inline(always)] + pub fn set_mclksel(&mut self, val: super::vals::Mclksel) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val.to_bits() as u32) & 0x01) << 22usize); + } +} +impl Default for Memctl { + #[inline(always)] + fn default() -> Memctl { + Memctl(0) + } +} +#[doc = "Memory Controller Status"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Memstatus(pub u32); +impl Memstatus { + #[doc = "FLASH Write Busy"] + #[inline(always)] + pub const fn wbusy(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "FLASH Write Busy"] + #[inline(always)] + pub fn set_wbusy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "FLASH Erase Busy"] + #[inline(always)] + pub const fn ebusy(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "FLASH Erase Busy"] + #[inline(always)] + pub fn set_ebusy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Number of bytes written to FLASH for the write data buffer"] + #[inline(always)] + pub const fn writewordcnt(&self) -> super::vals::Writewordcnt { + let val = (self.0 >> 8usize) & 0x03; + super::vals::Writewordcnt::from_bits(val as u8) + } + #[doc = "Number of bytes written to FLASH for the write data buffer"] + #[inline(always)] + pub fn set_writewordcnt(&mut self, val: super::vals::Writewordcnt) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); + } + #[doc = "ECC Single bit Error Detection Flag"] + #[inline(always)] + pub const fn se(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "ECC Single bit Error Detection Flag"] + #[inline(always)] + pub fn set_se(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "ECC Dual bit Error Detection Flag"] + #[inline(always)] + pub const fn de(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "ECC Dual bit Error Detection Flag"] + #[inline(always)] + pub fn set_de(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Invalid Memory Address Access Flag"] + #[inline(always)] + pub const fn invaddr(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Invalid Memory Address Access Flag"] + #[inline(always)] + pub fn set_invaddr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } +} +impl Default for Memstatus { + #[inline(always)] + fn default() -> Memstatus { + Memstatus(0) + } +} +#[doc = "SWD Unlock"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Swdunlock(pub u32); +impl Swdunlock { + #[doc = "Key for SWD unlock"] + #[inline(always)] + pub const fn key_swdunlock(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Key for SWD unlock"] + #[inline(always)] + pub fn set_key_swdunlock(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for Swdunlock { + #[inline(always)] + fn default() -> Swdunlock { + Swdunlock(0) + } +} diff --git a/src/memctl/vals.rs b/src/memctl/vals.rs new file mode 100644 index 0000000..7623b3d --- /dev/null +++ b/src/memctl/vals.rs @@ -0,0 +1,186 @@ +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub struct Flashlock(pub u32); +impl Flashlock { + #[doc = "Reset value"] + pub const RESET: Self = Self(0x0); + #[doc = "Allow write and erase operations"] + pub const ALLOW_WRITE_ERASE_FLASH: Self = Self(0x43df_140a); + #[doc = "Allow write to INFO2.SWDFUSE register"] + pub const ALLOW_WRITE_INFO2SWDFUSE: Self = Self(0x79b4_f762); + #[doc = "Allow write to MEMCTRL register"] + pub const ALLOW_WRITE_MEMCTL: Self = Self(0xd513_b490); +} +impl Flashlock { + pub const fn from_bits(val: u32) -> Flashlock { + Self(val & 0xffff_ffff) + } + pub const fn to_bits(self) -> u32 { + self.0 + } +} +impl From for Flashlock { + #[inline(always)] + fn from(val: u32) -> Flashlock { + Flashlock::from_bits(val) + } +} +impl From for u32 { + #[inline(always)] + fn from(val: Flashlock) -> u32 { + Flashlock::to_bits(val) + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub struct Key(pub u32); +impl Key { + #[doc = "Mass page erase"] + pub const MASS_PAGE_ERASE: Self = Self(0x09ee_76c9); + #[doc = "INFO-3 Erase"] + pub const INFO_3_ERASE: Self = Self(0x1266_ff45); + #[doc = "Page erase"] + pub const PAGE_ERASE: Self = Self(0x8c79_9ca7); +} +impl Key { + pub const fn from_bits(val: u32) -> Key { + Self(val & 0xffff_ffff) + } + pub const fn to_bits(self) -> u32 { + self.0 + } +} +impl From for Key { + #[inline(always)] + fn from(val: u32) -> Key { + Key::from_bits(val) + } +} +impl From for u32 { + #[inline(always)] + fn from(val: Key) -> u32 { + Key::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Mclkdiv { + #[doc = "/1"] + DIV1 = 0x0, + #[doc = "/2"] + DIV2 = 0x01, + #[doc = "/3"] + DIV3 = 0x02, + #[doc = "/4"] + DIV4 = 0x03, + #[doc = "/5"] + DIV5 = 0x04, + #[doc = "/6"] + DIV6 = 0x05, + #[doc = "/7"] + DIV7 = 0x06, + #[doc = "/8"] + DIV8 = 0x07, + #[doc = "/9"] + DIV9 = 0x08, + #[doc = "/10"] + DIV10 = 0x09, + #[doc = "/11"] + DIV11 = 0x0a, + #[doc = "/12"] + DIV12 = 0x0b, + #[doc = "/13"] + DIV13 = 0x0c, + #[doc = "/14"] + DIV14 = 0x0d, + #[doc = "/15"] + DIV15 = 0x0e, + #[doc = "/16"] + DIV16 = 0x0f, +} +impl Mclkdiv { + #[inline(always)] + pub const fn from_bits(val: u8) -> Mclkdiv { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Mclkdiv { + #[inline(always)] + fn from(val: u8) -> Mclkdiv { + Mclkdiv::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Mclkdiv) -> u8 { + Mclkdiv::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Mclksel { + #[doc = "ROSCCLK as MCLK"] + ROSCCLK = 0x0, + #[doc = "HCLK/MCLKDIV as MCLK"] + MCLK = 0x01, +} +impl Mclksel { + #[inline(always)] + pub const fn from_bits(val: u8) -> Mclksel { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Mclksel { + #[inline(always)] + fn from(val: u8) -> Mclksel { + Mclksel::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Mclksel) -> u8 { + Mclksel::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Writewordcnt { + #[doc = "4 bytes"] + BYTES4 = 0x0, + #[doc = "8 bytes"] + BYTES8 = 0x01, + #[doc = "12 bytes"] + BYTES12 = 0x02, + #[doc = "16 bytes"] + BYTES16 = 0x03, +} +impl Writewordcnt { + #[inline(always)] + pub const fn from_bits(val: u8) -> Writewordcnt { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Writewordcnt { + #[inline(always)] + fn from(val: u8) -> Writewordcnt { + Writewordcnt::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Writewordcnt) -> u8 { + Writewordcnt::to_bits(val) + } +} diff --git a/src/rtc.rs b/src/rtc.rs new file mode 100644 index 0000000..f4cce4e --- /dev/null +++ b/src/rtc.rs @@ -0,0 +1,49 @@ +#[doc = "Real-Time Clock (RTC) with Calendar"] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Rtc { + ptr: *mut u8, +} +unsafe impl Send for Rtc {} +unsafe impl Sync for Rtc {} +impl Rtc { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "RTC Control"] + #[inline(always)] + pub const fn ctl(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "RTC Time"] + #[inline(always)] + pub const fn time(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } + #[doc = "RTC Date"] + #[inline(always)] + pub const fn date(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } + } + #[doc = "RTC Time Setting"] + #[inline(always)] + pub const fn timeset(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } + #[doc = "RTC Date Setting"] + #[inline(always)] + pub const fn dateset(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } + } + #[doc = "RTC Alarm Setting"] + #[inline(always)] + pub const fn alarmset(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } + } +} +pub mod regs; +pub mod vals; diff --git a/src/rtc/regs.rs b/src/rtc/regs.rs new file mode 100644 index 0000000..01d6cba --- /dev/null +++ b/src/rtc/regs.rs @@ -0,0 +1,369 @@ +#[doc = "RTC Alarm Setting"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Alarmset(pub u32); +impl Alarmset { + #[doc = "Minute alarm"] + #[inline(always)] + pub const fn minutealarm(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x7f; + val as u8 + } + #[doc = "Minute alarm"] + #[inline(always)] + pub fn set_minutealarm(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize); + } + #[doc = "Minute alarm enable"] + #[inline(always)] + pub const fn minutealarmen(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Minute alarm enable"] + #[inline(always)] + pub fn set_minutealarmen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Hour alarm"] + #[inline(always)] + pub const fn houralarm(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x3f; + val as u8 + } + #[doc = "Hour alarm"] + #[inline(always)] + pub fn set_houralarm(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize); + } + #[doc = "Hour alarm enable"] + #[inline(always)] + pub const fn houralarmen(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Hour alarm enable"] + #[inline(always)] + pub fn set_houralarmen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Day of week alarm"] + #[inline(always)] + pub const fn dayofweekalarm(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x07; + val as u8 + } + #[doc = "Day of week alarm"] + #[inline(always)] + pub fn set_dayofweekalarm(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 16usize)) | (((val as u32) & 0x07) << 16usize); + } + #[doc = "Day of week alarm enable"] + #[inline(always)] + pub const fn dayofweekalarmen(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "Day of week alarm enable"] + #[inline(always)] + pub fn set_dayofweekalarmen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } + #[doc = "Day alarm"] + #[inline(always)] + pub const fn dayalarm(&self) -> u8 { + let val = (self.0 >> 24usize) & 0x3f; + val as u8 + } + #[doc = "Day alarm"] + #[inline(always)] + pub fn set_dayalarm(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 24usize)) | (((val as u32) & 0x3f) << 24usize); + } + #[doc = "Day alarm enable"] + #[inline(always)] + pub const fn dayalarmen(&self) -> bool { + let val = (self.0 >> 30usize) & 0x01; + val != 0 + } + #[doc = "Day alarm enable"] + #[inline(always)] + pub fn set_dayalarmen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); + } +} +impl Default for Alarmset { + #[inline(always)] + fn default() -> Alarmset { + Alarmset(0) + } +} +#[doc = "RTC Control"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Ctl(pub u32); +impl Ctl { + #[doc = "Enable RTC"] + #[inline(always)] + pub const fn en(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Enable RTC"] + #[inline(always)] + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Alarm match interrupt enable"] + #[inline(always)] + pub const fn ie(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Alarm match interrupt enable"] + #[inline(always)] + pub fn set_ie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Alarm match interrupt flag"] + #[inline(always)] + pub const fn if_(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Alarm match interrupt flag"] + #[inline(always)] + pub fn set_if_(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Clock divider for the RTC input clock (FRCLK)"] + #[inline(always)] + pub const fn clkdiv(&self) -> super::vals::Clkdiv { + let val = (self.0 >> 4usize) & 0x1f; + super::vals::Clkdiv::from_bits(val as u8) + } + #[doc = "Clock divider for the RTC input clock (FRCLK)"] + #[inline(always)] + pub fn set_clkdiv(&mut self, val: super::vals::Clkdiv) { + self.0 = (self.0 & !(0x1f << 4usize)) | (((val.to_bits() as u32) & 0x1f) << 4usize); + } + #[doc = "Set the internal TIME/DATA with TIMESET/DATESET values"] + #[inline(always)] + pub const fn setcal(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "Set the internal TIME/DATA with TIMESET/DATESET values"] + #[inline(always)] + pub fn set_setcal(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } +} +impl Default for Ctl { + #[inline(always)] + fn default() -> Ctl { + Ctl(0) + } +} +#[doc = "RTC Date"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Date(pub u32); +impl Date { + #[doc = "Day of week"] + #[inline(always)] + pub const fn dayofweek(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x07; + val as u8 + } + #[doc = "Day of week"] + #[inline(always)] + pub fn set_dayofweek(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); + } + #[doc = "Day"] + #[inline(always)] + pub const fn day(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x3f; + val as u8 + } + #[doc = "Day"] + #[inline(always)] + pub fn set_day(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize); + } + #[doc = "Month"] + #[inline(always)] + pub const fn month(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x1f; + val as u8 + } + #[doc = "Month"] + #[inline(always)] + pub fn set_month(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize); + } + #[doc = "Year"] + #[inline(always)] + pub const fn year(&self) -> u8 { + let val = (self.0 >> 24usize) & 0xff; + val as u8 + } + #[doc = "Year"] + #[inline(always)] + pub fn set_year(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 24usize)) | (((val as u32) & 0xff) << 24usize); + } +} +impl Default for Date { + #[inline(always)] + fn default() -> Date { + Date(0) + } +} +#[doc = "RTC Date Setting"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Dateset(pub u32); +impl Dateset { + #[doc = "Day of week"] + #[inline(always)] + pub const fn dayofweek(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x07; + val as u8 + } + #[doc = "Day of week"] + #[inline(always)] + pub fn set_dayofweek(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); + } + #[doc = "Day"] + #[inline(always)] + pub const fn day(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x3f; + val as u8 + } + #[doc = "Day"] + #[inline(always)] + pub fn set_day(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize); + } + #[doc = "Month"] + #[inline(always)] + pub const fn month(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x1f; + val as u8 + } + #[doc = "Month"] + #[inline(always)] + pub fn set_month(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize); + } + #[doc = "Year"] + #[inline(always)] + pub const fn year(&self) -> u8 { + let val = (self.0 >> 24usize) & 0xff; + val as u8 + } + #[doc = "Year"] + #[inline(always)] + pub fn set_year(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 24usize)) | (((val as u32) & 0xff) << 24usize); + } +} +impl Default for Dateset { + #[inline(always)] + fn default() -> Dateset { + Dateset(0) + } +} +#[doc = "RTC Time"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Time(pub u32); +impl Time { + #[doc = "Seconds"] + #[inline(always)] + pub const fn seconds(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x7f; + val as u8 + } + #[doc = "Seconds"] + #[inline(always)] + pub fn set_seconds(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize); + } + #[doc = "Minutes"] + #[inline(always)] + pub const fn minutes(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x7f; + val as u8 + } + #[doc = "Minutes"] + #[inline(always)] + pub fn set_minutes(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 8usize)) | (((val as u32) & 0x7f) << 8usize); + } + #[doc = "Hours"] + #[inline(always)] + pub const fn hours(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x3f; + val as u8 + } + #[doc = "Hours"] + #[inline(always)] + pub fn set_hours(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 16usize)) | (((val as u32) & 0x3f) << 16usize); + } +} +impl Default for Time { + #[inline(always)] + fn default() -> Time { + Time(0) + } +} +#[doc = "RTC Time Setting"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Timeset(pub u32); +impl Timeset { + #[doc = "Seconds"] + #[inline(always)] + pub const fn seconds(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x7f; + val as u8 + } + #[doc = "Seconds"] + #[inline(always)] + pub fn set_seconds(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize); + } + #[doc = "Minutes"] + #[inline(always)] + pub const fn minutes(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x7f; + val as u8 + } + #[doc = "Minutes"] + #[inline(always)] + pub fn set_minutes(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 8usize)) | (((val as u32) & 0x7f) << 8usize); + } + #[doc = "Hours"] + #[inline(always)] + pub const fn hours(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x3f; + val as u8 + } + #[doc = "Hours"] + #[inline(always)] + pub fn set_hours(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 16usize)) | (((val as u32) & 0x3f) << 16usize); + } +} +impl Default for Timeset { + #[inline(always)] + fn default() -> Timeset { + Timeset(0) + } +} diff --git a/src/rtc/vals.rs b/src/rtc/vals.rs new file mode 100644 index 0000000..a0f32a0 --- /dev/null +++ b/src/rtc/vals.rs @@ -0,0 +1,90 @@ +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Clkdiv { + #[doc = "FRCLK/1"] + DIV1 = 0x0, + #[doc = "FRCLK/2"] + DIV2 = 0x01, + #[doc = "FRCLK/3"] + DIV3 = 0x02, + #[doc = "FRCLK/4"] + DIV4 = 0x03, + #[doc = "FRCLK/5"] + DIV5 = 0x04, + #[doc = "FRCLK/6"] + DIV6 = 0x05, + #[doc = "FRCLK/7"] + DIV7 = 0x06, + #[doc = "FRCLK/8"] + DIV8 = 0x07, + #[doc = "FRCLK/9"] + DIV9 = 0x08, + #[doc = "FRCLK/10"] + DIV10 = 0x09, + #[doc = "FRCLK/11"] + DIV11 = 0x0a, + #[doc = "FRCLK/12"] + DIV12 = 0x0b, + #[doc = "FRCLK/13"] + DIV13 = 0x0c, + #[doc = "FRCLK/14"] + DIV14 = 0x0d, + #[doc = "FRCLK/15"] + DIV15 = 0x0e, + #[doc = "FRCLK/16"] + DIV16 = 0x0f, + #[doc = "FRCLK/17"] + DIV17 = 0x10, + #[doc = "FRCLK/18"] + DIV18 = 0x11, + #[doc = "FRCLK/19"] + DIV19 = 0x12, + #[doc = "FRCLK/20"] + DIV20 = 0x13, + #[doc = "FRCLK/21"] + DIV21 = 0x14, + #[doc = "FRCLK/22"] + DIV22 = 0x15, + #[doc = "FRCLK/23"] + DIV23 = 0x16, + #[doc = "FRCLK/24"] + DIV24 = 0x17, + #[doc = "FRCLK/25"] + DIV25 = 0x18, + #[doc = "FRCLK/26"] + DIV26 = 0x19, + #[doc = "FRCLK/27"] + DIV27 = 0x1a, + #[doc = "FRCLK/28"] + DIV28 = 0x1b, + #[doc = "FRCLK/29"] + DIV29 = 0x1c, + #[doc = "FRCLK/30"] + DIV30 = 0x1d, + #[doc = "FRCLK/31"] + DIV31 = 0x1e, + #[doc = "FRCLK/32"] + DIV32 = 0x1f, +} +impl Clkdiv { + #[inline(always)] + pub const fn from_bits(val: u8) -> Clkdiv { + unsafe { core::mem::transmute(val & 0x1f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Clkdiv { + #[inline(always)] + fn from(val: u8) -> Clkdiv { + Clkdiv::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Clkdiv) -> u8 { + Clkdiv::to_bits(val) + } +} diff --git a/src/scc.rs b/src/scc.rs new file mode 100644 index 0000000..1fa8087 --- /dev/null +++ b/src/scc.rs @@ -0,0 +1,174 @@ +#[doc = "System and Clock Control"] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Scc { + ptr: *mut u8, +} +unsafe impl Send for Scc {} +unsafe impl Sync for Scc {} +impl Scc { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Configuration"] + #[inline(always)] + pub const fn ccsctl(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "PLL Configuration"] + #[inline(always)] + pub const fn ccspllctl(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } + #[doc = "ROSC Trim Configuration"] + #[inline(always)] + pub const fn ccsrosctrim(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } + } + #[doc = "PA Peripheral MUX Select"] + #[inline(always)] + pub const fn pamuxsel(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } + #[doc = "PB Peripheral MUX Select"] + #[inline(always)] + pub const fn pbmuxsel(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } + } + #[doc = "PC Peripheral MUX Select"] + #[inline(always)] + pub const fn pcmuxsel(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } + } + #[doc = "PD Peripheral MUX Select"] + #[inline(always)] + pub const fn pdmuxsel(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } + } + #[doc = "PE Peripheral MUX Select"] + #[inline(always)] + pub const fn pemuxsel(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } + } + #[doc = "PF Peripheral MUX Select"] + #[inline(always)] + pub const fn pfmuxsel(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } + } + #[doc = "PG Peripheral MUX Select"] + #[inline(always)] + pub const fn pgmuxsel(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } + } + #[doc = "Weak Pull-up Enable"] + #[inline(always)] + pub const fn papuen(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } + } + #[doc = "Weak Pull-up Enable"] + #[inline(always)] + pub const fn pbpuen(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } + } + #[doc = "Weak Pull-up Enable"] + #[inline(always)] + pub const fn pcpuen(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } + } + #[doc = "Weak Pull-up Enable"] + #[inline(always)] + pub const fn pdpuen(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } + } + #[doc = "Weak Pull-up Enable"] + #[inline(always)] + pub const fn pepuen(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) } + } + #[doc = "Weak Pull-up Enable"] + #[inline(always)] + pub const fn pfpuen(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) } + } + #[doc = "Weak Pull-up Enable"] + #[inline(always)] + pub const fn pgpuen(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) } + } + #[doc = "Weak Pull-down Enable"] + #[inline(always)] + pub const fn papden(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) } + } + #[doc = "Weak Pull-down Enable"] + #[inline(always)] + pub const fn pbpden(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) } + } + #[doc = "Weak Pull-down Enable"] + #[inline(always)] + pub const fn pcpden(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) } + } + #[doc = "Weak Pull-down Enable"] + #[inline(always)] + pub const fn pdpden(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) } + } + #[doc = "Weak Pull-down Enable"] + #[inline(always)] + pub const fn pepden(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) } + } + #[doc = "Weak Pull-down Enable"] + #[inline(always)] + pub const fn pfpden(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) } + } + #[doc = "Weak Pull-down Enable"] + #[inline(always)] + pub const fn pgpden(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) } + } + #[doc = "Drive Strength/Schmitt Trigger"] + #[inline(always)] + pub const fn pads(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) } + } + #[doc = "Drive Strength/Schmitt Trigger"] + #[inline(always)] + pub const fn pbds(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x64usize) as _) } + } + #[doc = "Drive Strength/Schmitt Trigger"] + #[inline(always)] + pub const fn pcds(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) } + } + #[doc = "Drive Strength/Schmitt Trigger"] + #[inline(always)] + pub const fn pdds(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x6cusize) as _) } + } + #[doc = "Drive Strength/Schmitt Trigger"] + #[inline(always)] + pub const fn peds(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x70usize) as _) } + } + #[doc = "Drive Strength/Schmitt Trigger"] + #[inline(always)] + pub const fn pfds(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x74usize) as _) } + } + #[doc = "Drive Strength/Schmitt Trigger"] + #[inline(always)] + pub const fn pgds(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x78usize) as _) } + } +} +pub mod regs; +pub mod vals; diff --git a/src/scc/regs.rs b/src/scc/regs.rs new file mode 100644 index 0000000..43afead --- /dev/null +++ b/src/scc/regs.rs @@ -0,0 +1,1118 @@ +#[doc = "Configuration"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Ccsctl(pub u32); +impl Ccsctl { + #[doc = "FRCLK MUX Select"] + #[inline(always)] + pub const fn frclkmuxsel(&self) -> super::vals::Frclkmuxsel { + let val = (self.0 >> 0usize) & 0x03; + super::vals::Frclkmuxsel::from_bits(val as u8) + } + #[doc = "FRCLK MUX Select"] + #[inline(always)] + pub fn set_frclkmuxsel(&mut self, val: super::vals::Frclkmuxsel) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + #[doc = "ROSC Enable"] + #[inline(always)] + pub const fn roscen(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "ROSC Enable"] + #[inline(always)] + pub fn set_roscen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "SCLK Mux Select"] + #[inline(always)] + pub const fn sclkmuxsel(&self) -> super::vals::Sclkmuxsel { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Sclkmuxsel::from_bits(val as u8) + } + #[doc = "SCLK Mux Select"] + #[inline(always)] + pub fn set_sclkmuxsel(&mut self, val: super::vals::Sclkmuxsel) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize); + } + #[doc = "Clock Fail Enable"] + #[inline(always)] + pub const fn clkfailen(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Clock Fail Enable"] + #[inline(always)] + pub fn set_clkfailen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Clock Fail Mux Select"] + #[inline(always)] + pub const fn clkfailmuxsel(&self) -> super::vals::Clkfailmuxsel { + let val = (self.0 >> 6usize) & 0x01; + super::vals::Clkfailmuxsel::from_bits(val as u8) + } + #[doc = "Clock Fail Mux Select"] + #[inline(always)] + pub fn set_clkfailmuxsel(&mut self, val: super::vals::Clkfailmuxsel) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); + } + #[doc = "Clock Fail Interrupt Flag"] + #[inline(always)] + pub const fn clkfailif(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Clock Fail Interrupt Flag"] + #[inline(always)] + pub fn set_clkfailif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "1.8V LDO Enable"] + #[inline(always)] + pub const fn ldoen(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "1.8V LDO Enable"] + #[inline(always)] + pub fn set_ldoen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Software Reset"] + #[inline(always)] + pub const fn swreset(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Software Reset"] + #[inline(always)] + pub fn set_swreset(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "PCLK Enable"] + #[inline(always)] + pub const fn pclken(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "PCLK Enable"] + #[inline(always)] + pub fn set_pclken(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "ACLK Enable"] + #[inline(always)] + pub const fn aclken(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "ACLK Enable"] + #[inline(always)] + pub fn set_aclken(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "ADCCLK Enable"] + #[inline(always)] + pub const fn adclken(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "ADCCLK Enable"] + #[inline(always)] + pub fn set_adclken(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "SysTick Clock Sleep Enable"] + #[inline(always)] + pub const fn stclkslpen(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "SysTick Clock Sleep Enable"] + #[inline(always)] + pub fn set_stclkslpen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "PCLK Divider"] + #[inline(always)] + pub const fn pclkdiv(&self) -> super::vals::Pclkdiv { + let val = (self.0 >> 16usize) & 0x07; + super::vals::Pclkdiv::from_bits(val as u8) + } + #[doc = "PCLK Divider"] + #[inline(always)] + pub fn set_pclkdiv(&mut self, val: super::vals::Pclkdiv) { + self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize); + } + #[doc = "ACLK Divider"] + #[inline(always)] + pub const fn aclkdiv(&self) -> super::vals::Aclkdiv { + let val = (self.0 >> 20usize) & 0x07; + super::vals::Aclkdiv::from_bits(val as u8) + } + #[doc = "ACLK Divider"] + #[inline(always)] + pub fn set_aclkdiv(&mut self, val: super::vals::Aclkdiv) { + self.0 = (self.0 & !(0x07 << 20usize)) | (((val.to_bits() as u32) & 0x07) << 20usize); + } + #[doc = "HCLK Divider"] + #[inline(always)] + pub const fn hclkdiv(&self) -> super::vals::Hclkdiv { + let val = (self.0 >> 24usize) & 0x07; + super::vals::Hclkdiv::from_bits(val as u8) + } + #[doc = "HCLK Divider"] + #[inline(always)] + pub fn set_hclkdiv(&mut self, val: super::vals::Hclkdiv) { + self.0 = (self.0 & !(0x07 << 24usize)) | (((val.to_bits() as u32) & 0x07) << 24usize); + } + #[doc = "USART A Mode"] + #[inline(always)] + pub const fn usamode(&self) -> super::vals::Usmode { + let val = (self.0 >> 28usize) & 0x01; + super::vals::Usmode::from_bits(val as u8) + } + #[doc = "USART A Mode"] + #[inline(always)] + pub fn set_usamode(&mut self, val: super::vals::Usmode) { + self.0 = (self.0 & !(0x01 << 28usize)) | (((val.to_bits() as u32) & 0x01) << 28usize); + } + #[doc = "USART B Mode"] + #[inline(always)] + pub const fn usbmode(&self) -> super::vals::Usmode { + let val = (self.0 >> 29usize) & 0x01; + super::vals::Usmode::from_bits(val as u8) + } + #[doc = "USART B Mode"] + #[inline(always)] + pub fn set_usbmode(&mut self, val: super::vals::Usmode) { + self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); + } + #[doc = "USART C Mode"] + #[inline(always)] + pub const fn uscmode(&self) -> super::vals::Usmode { + let val = (self.0 >> 30usize) & 0x01; + super::vals::Usmode::from_bits(val as u8) + } + #[doc = "USART C Mode"] + #[inline(always)] + pub fn set_uscmode(&mut self, val: super::vals::Usmode) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); + } + #[doc = "USART D Mode"] + #[inline(always)] + pub const fn usdmode(&self) -> super::vals::Usmode { + let val = (self.0 >> 31usize) & 0x01; + super::vals::Usmode::from_bits(val as u8) + } + #[doc = "USART D Mode"] + #[inline(always)] + pub fn set_usdmode(&mut self, val: super::vals::Usmode) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); + } +} +impl Default for Ccsctl { + #[inline(always)] + fn default() -> Ccsctl { + Ccsctl(0) + } +} +#[doc = "PLL Configuration"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Ccspllctl(pub u32); +impl Ccspllctl { + #[doc = "PLL Enable"] + #[inline(always)] + pub const fn pllen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "PLL Enable"] + #[inline(always)] + pub fn set_pllen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "PLL Bypass"] + #[inline(always)] + pub const fn pllbp(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "PLL Bypass"] + #[inline(always)] + pub fn set_pllbp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "PLL Output Divider"] + #[inline(always)] + pub const fn plloutdiv(&self) -> super::vals::Plloutdiv { + let val = (self.0 >> 2usize) & 0x03; + super::vals::Plloutdiv::from_bits(val as u8) + } + #[doc = "PLL Output Divider"] + #[inline(always)] + pub fn set_plloutdiv(&mut self, val: super::vals::Plloutdiv) { + self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); + } + #[doc = "PLL Input Divider"] + #[inline(always)] + pub const fn pllindiv(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "PLL Input Divider"] + #[inline(always)] + pub fn set_pllindiv(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + #[doc = "PLL Feedback Divider"] + #[inline(always)] + pub const fn pllfbdiv(&self) -> u16 { + let val = (self.0 >> 8usize) & 0x3fff; + val as u16 + } + #[doc = "PLL Feedback Divider"] + #[inline(always)] + pub fn set_pllfbdiv(&mut self, val: u16) { + self.0 = (self.0 & !(0x3fff << 8usize)) | (((val as u32) & 0x3fff) << 8usize); + } + #[doc = "PLL Lock Status"] + #[inline(always)] + pub const fn plllock(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "PLL Lock Status"] + #[inline(always)] + pub fn set_plllock(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } +} +impl Default for Ccspllctl { + #[inline(always)] + fn default() -> Ccspllctl { + Ccspllctl(0) + } +} +#[doc = "ROSC Trim Configuration"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Ccsrosctrim(pub u32); +impl Ccsrosctrim { + #[doc = "ROSC Trim Value"] + #[inline(always)] + pub const fn trim(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x7f; + val as u8 + } + #[doc = "ROSC Trim Value"] + #[inline(always)] + pub fn set_trim(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize); + } +} +impl Default for Ccsrosctrim { + #[inline(always)] + fn default() -> Ccsrosctrim { + Ccsrosctrim(0) + } +} +#[doc = "PA Peripheral MUX Select"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Pamuxsel(pub u32); +impl Pamuxsel { + #[doc = "PA0 MUX Select"] + #[inline(always)] + pub const fn pa0(&self) -> super::vals::Pa0 { + let val = (self.0 >> 0usize) & 0x07; + super::vals::Pa0::from_bits(val as u8) + } + #[doc = "PA0 MUX Select"] + #[inline(always)] + pub fn set_pa0(&mut self, val: super::vals::Pa0) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); + } + #[doc = "PA1 MUX Select"] + #[inline(always)] + pub const fn pa1(&self) -> super::vals::Pa1 { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Pa1::from_bits(val as u8) + } + #[doc = "PA1 MUX Select"] + #[inline(always)] + pub fn set_pa1(&mut self, val: super::vals::Pa1) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize); + } + #[doc = "PA2 MUX Select"] + #[inline(always)] + pub const fn pa2(&self) -> super::vals::Pa2 { + let val = (self.0 >> 8usize) & 0x07; + super::vals::Pa2::from_bits(val as u8) + } + #[doc = "PA2 MUX Select"] + #[inline(always)] + pub fn set_pa2(&mut self, val: super::vals::Pa2) { + self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u32) & 0x07) << 8usize); + } + #[doc = "PA3 MUX Select"] + #[inline(always)] + pub const fn pa3(&self) -> super::vals::Pa3 { + let val = (self.0 >> 12usize) & 0x07; + super::vals::Pa3::from_bits(val as u8) + } + #[doc = "PA3 MUX Select"] + #[inline(always)] + pub fn set_pa3(&mut self, val: super::vals::Pa3) { + self.0 = (self.0 & !(0x07 << 12usize)) | (((val.to_bits() as u32) & 0x07) << 12usize); + } + #[doc = "PA4 MUX Select"] + #[inline(always)] + pub const fn pa4(&self) -> super::vals::Pa4 { + let val = (self.0 >> 16usize) & 0x07; + super::vals::Pa4::from_bits(val as u8) + } + #[doc = "PA4 MUX Select"] + #[inline(always)] + pub fn set_pa4(&mut self, val: super::vals::Pa4) { + self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize); + } + #[doc = "PA5 MUX Select"] + #[inline(always)] + pub const fn pa5(&self) -> super::vals::Pa5 { + let val = (self.0 >> 20usize) & 0x07; + super::vals::Pa5::from_bits(val as u8) + } + #[doc = "PA5 MUX Select"] + #[inline(always)] + pub fn set_pa5(&mut self, val: super::vals::Pa5) { + self.0 = (self.0 & !(0x07 << 20usize)) | (((val.to_bits() as u32) & 0x07) << 20usize); + } + #[doc = "PA6 MUX Select"] + #[inline(always)] + pub const fn pa6(&self) -> super::vals::Pa6 { + let val = (self.0 >> 24usize) & 0x07; + super::vals::Pa6::from_bits(val as u8) + } + #[doc = "PA6 MUX Select"] + #[inline(always)] + pub fn set_pa6(&mut self, val: super::vals::Pa6) { + self.0 = (self.0 & !(0x07 << 24usize)) | (((val.to_bits() as u32) & 0x07) << 24usize); + } + #[doc = "PA7 MUX Select"] + #[inline(always)] + pub const fn pa7(&self) -> super::vals::Pa7 { + let val = (self.0 >> 28usize) & 0x07; + super::vals::Pa7::from_bits(val as u8) + } + #[doc = "PA7 MUX Select"] + #[inline(always)] + pub fn set_pa7(&mut self, val: super::vals::Pa7) { + self.0 = (self.0 & !(0x07 << 28usize)) | (((val.to_bits() as u32) & 0x07) << 28usize); + } +} +impl Default for Pamuxsel { + #[inline(always)] + fn default() -> Pamuxsel { + Pamuxsel(0) + } +} +#[doc = "PB Peripheral MUX Select"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Pbmuxsel(pub u32); +impl Pbmuxsel { + #[doc = "PB0 MUX Select"] + #[inline(always)] + pub const fn pb0(&self) -> super::vals::Pb0 { + let val = (self.0 >> 0usize) & 0x07; + super::vals::Pb0::from_bits(val as u8) + } + #[doc = "PB0 MUX Select"] + #[inline(always)] + pub fn set_pb0(&mut self, val: super::vals::Pb0) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); + } + #[doc = "PB1 MUX Select"] + #[inline(always)] + pub const fn pb1(&self) -> super::vals::Pb1 { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Pb1::from_bits(val as u8) + } + #[doc = "PB1 MUX Select"] + #[inline(always)] + pub fn set_pb1(&mut self, val: super::vals::Pb1) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize); + } + #[doc = "PB2 MUX Select"] + #[inline(always)] + pub const fn pb2(&self) -> super::vals::Pb2 { + let val = (self.0 >> 8usize) & 0x07; + super::vals::Pb2::from_bits(val as u8) + } + #[doc = "PB2 MUX Select"] + #[inline(always)] + pub fn set_pb2(&mut self, val: super::vals::Pb2) { + self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u32) & 0x07) << 8usize); + } + #[doc = "PB3 MUX Select"] + #[inline(always)] + pub const fn pb3(&self) -> super::vals::Pb3 { + let val = (self.0 >> 12usize) & 0x07; + super::vals::Pb3::from_bits(val as u8) + } + #[doc = "PB3 MUX Select"] + #[inline(always)] + pub fn set_pb3(&mut self, val: super::vals::Pb3) { + self.0 = (self.0 & !(0x07 << 12usize)) | (((val.to_bits() as u32) & 0x07) << 12usize); + } + #[doc = "PB4 MUX Select"] + #[inline(always)] + pub const fn pb4(&self) -> super::vals::Pb4 { + let val = (self.0 >> 16usize) & 0x07; + super::vals::Pb4::from_bits(val as u8) + } + #[doc = "PB4 MUX Select"] + #[inline(always)] + pub fn set_pb4(&mut self, val: super::vals::Pb4) { + self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize); + } + #[doc = "PB5 MUX Select"] + #[inline(always)] + pub const fn pb5(&self) -> super::vals::Pb5 { + let val = (self.0 >> 20usize) & 0x07; + super::vals::Pb5::from_bits(val as u8) + } + #[doc = "PB5 MUX Select"] + #[inline(always)] + pub fn set_pb5(&mut self, val: super::vals::Pb5) { + self.0 = (self.0 & !(0x07 << 20usize)) | (((val.to_bits() as u32) & 0x07) << 20usize); + } + #[doc = "PB6 MUX Select"] + #[inline(always)] + pub const fn pb6(&self) -> super::vals::Pb6 { + let val = (self.0 >> 24usize) & 0x07; + super::vals::Pb6::from_bits(val as u8) + } + #[doc = "PB6 MUX Select"] + #[inline(always)] + pub fn set_pb6(&mut self, val: super::vals::Pb6) { + self.0 = (self.0 & !(0x07 << 24usize)) | (((val.to_bits() as u32) & 0x07) << 24usize); + } + #[doc = "PB7 MUX Select"] + #[inline(always)] + pub const fn pb7(&self) -> super::vals::Pb7 { + let val = (self.0 >> 28usize) & 0x07; + super::vals::Pb7::from_bits(val as u8) + } + #[doc = "PB7 MUX Select"] + #[inline(always)] + pub fn set_pb7(&mut self, val: super::vals::Pb7) { + self.0 = (self.0 & !(0x07 << 28usize)) | (((val.to_bits() as u32) & 0x07) << 28usize); + } +} +impl Default for Pbmuxsel { + #[inline(always)] + fn default() -> Pbmuxsel { + Pbmuxsel(0) + } +} +#[doc = "PC Peripheral MUX Select"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Pcmuxsel(pub u32); +impl Pcmuxsel { + #[doc = "PC0 MUX Select"] + #[inline(always)] + pub const fn pc0(&self) -> super::vals::Pc0 { + let val = (self.0 >> 0usize) & 0x07; + super::vals::Pc0::from_bits(val as u8) + } + #[doc = "PC0 MUX Select"] + #[inline(always)] + pub fn set_pc0(&mut self, val: super::vals::Pc0) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); + } + #[doc = "PC1 MUX Select"] + #[inline(always)] + pub const fn pc1(&self) -> super::vals::Pc1 { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Pc1::from_bits(val as u8) + } + #[doc = "PC1 MUX Select"] + #[inline(always)] + pub fn set_pc1(&mut self, val: super::vals::Pc1) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize); + } + #[doc = "PC2 MUX Select"] + #[inline(always)] + pub const fn pc2(&self) -> super::vals::Pc2 { + let val = (self.0 >> 8usize) & 0x07; + super::vals::Pc2::from_bits(val as u8) + } + #[doc = "PC2 MUX Select"] + #[inline(always)] + pub fn set_pc2(&mut self, val: super::vals::Pc2) { + self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u32) & 0x07) << 8usize); + } + #[doc = "PC3 MUX Select"] + #[inline(always)] + pub const fn pc3(&self) -> super::vals::Pc3 { + let val = (self.0 >> 12usize) & 0x07; + super::vals::Pc3::from_bits(val as u8) + } + #[doc = "PC3 MUX Select"] + #[inline(always)] + pub fn set_pc3(&mut self, val: super::vals::Pc3) { + self.0 = (self.0 & !(0x07 << 12usize)) | (((val.to_bits() as u32) & 0x07) << 12usize); + } + #[doc = "PC4 MUX Select"] + #[inline(always)] + pub const fn pc4(&self) -> super::vals::Pc4 { + let val = (self.0 >> 16usize) & 0x07; + super::vals::Pc4::from_bits(val as u8) + } + #[doc = "PC4 MUX Select"] + #[inline(always)] + pub fn set_pc4(&mut self, val: super::vals::Pc4) { + self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize); + } + #[doc = "PC5 MUX Select"] + #[inline(always)] + pub const fn pc5(&self) -> super::vals::Pc5 { + let val = (self.0 >> 20usize) & 0x07; + super::vals::Pc5::from_bits(val as u8) + } + #[doc = "PC5 MUX Select"] + #[inline(always)] + pub fn set_pc5(&mut self, val: super::vals::Pc5) { + self.0 = (self.0 & !(0x07 << 20usize)) | (((val.to_bits() as u32) & 0x07) << 20usize); + } + #[doc = "PC6 MUX Select"] + #[inline(always)] + pub const fn pc6(&self) -> super::vals::Pc6 { + let val = (self.0 >> 24usize) & 0x07; + super::vals::Pc6::from_bits(val as u8) + } + #[doc = "PC6 MUX Select"] + #[inline(always)] + pub fn set_pc6(&mut self, val: super::vals::Pc6) { + self.0 = (self.0 & !(0x07 << 24usize)) | (((val.to_bits() as u32) & 0x07) << 24usize); + } + #[doc = "PC7 MUX Select"] + #[inline(always)] + pub const fn pc7(&self) -> super::vals::Pc7 { + let val = (self.0 >> 28usize) & 0x07; + super::vals::Pc7::from_bits(val as u8) + } + #[doc = "PC7 MUX Select"] + #[inline(always)] + pub fn set_pc7(&mut self, val: super::vals::Pc7) { + self.0 = (self.0 & !(0x07 << 28usize)) | (((val.to_bits() as u32) & 0x07) << 28usize); + } +} +impl Default for Pcmuxsel { + #[inline(always)] + fn default() -> Pcmuxsel { + Pcmuxsel(0) + } +} +#[doc = "PD Peripheral MUX Select"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Pdmuxsel(pub u32); +impl Pdmuxsel { + #[doc = "PD0 MUX Select"] + #[inline(always)] + pub const fn pd0(&self) -> super::vals::Pd0 { + let val = (self.0 >> 0usize) & 0x07; + super::vals::Pd0::from_bits(val as u8) + } + #[doc = "PD0 MUX Select"] + #[inline(always)] + pub fn set_pd0(&mut self, val: super::vals::Pd0) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); + } + #[doc = "PD1 MUX Select"] + #[inline(always)] + pub const fn pd1(&self) -> super::vals::Pd1 { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Pd1::from_bits(val as u8) + } + #[doc = "PD1 MUX Select"] + #[inline(always)] + pub fn set_pd1(&mut self, val: super::vals::Pd1) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize); + } + #[doc = "PD2 MUX Select"] + #[inline(always)] + pub const fn pd2(&self) -> super::vals::Pd2 { + let val = (self.0 >> 8usize) & 0x07; + super::vals::Pd2::from_bits(val as u8) + } + #[doc = "PD2 MUX Select"] + #[inline(always)] + pub fn set_pd2(&mut self, val: super::vals::Pd2) { + self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u32) & 0x07) << 8usize); + } + #[doc = "PD3 MUX Select"] + #[inline(always)] + pub const fn pd3(&self) -> super::vals::Pd3 { + let val = (self.0 >> 12usize) & 0x07; + super::vals::Pd3::from_bits(val as u8) + } + #[doc = "PD3 MUX Select"] + #[inline(always)] + pub fn set_pd3(&mut self, val: super::vals::Pd3) { + self.0 = (self.0 & !(0x07 << 12usize)) | (((val.to_bits() as u32) & 0x07) << 12usize); + } + #[doc = "PD4 MUX Select"] + #[inline(always)] + pub const fn pd4(&self) -> super::vals::Pd4 { + let val = (self.0 >> 16usize) & 0x07; + super::vals::Pd4::from_bits(val as u8) + } + #[doc = "PD4 MUX Select"] + #[inline(always)] + pub fn set_pd4(&mut self, val: super::vals::Pd4) { + self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize); + } + #[doc = "PD5 MUX Select"] + #[inline(always)] + pub const fn pd5(&self) -> super::vals::Pd5 { + let val = (self.0 >> 20usize) & 0x07; + super::vals::Pd5::from_bits(val as u8) + } + #[doc = "PD5 MUX Select"] + #[inline(always)] + pub fn set_pd5(&mut self, val: super::vals::Pd5) { + self.0 = (self.0 & !(0x07 << 20usize)) | (((val.to_bits() as u32) & 0x07) << 20usize); + } + #[doc = "PD6 MUX Select"] + #[inline(always)] + pub const fn pd6(&self) -> super::vals::Pd6 { + let val = (self.0 >> 24usize) & 0x07; + super::vals::Pd6::from_bits(val as u8) + } + #[doc = "PD6 MUX Select"] + #[inline(always)] + pub fn set_pd6(&mut self, val: super::vals::Pd6) { + self.0 = (self.0 & !(0x07 << 24usize)) | (((val.to_bits() as u32) & 0x07) << 24usize); + } + #[doc = "PD7 MUX Select"] + #[inline(always)] + pub const fn pd7(&self) -> super::vals::Pd7 { + let val = (self.0 >> 28usize) & 0x07; + super::vals::Pd7::from_bits(val as u8) + } + #[doc = "PD7 MUX Select"] + #[inline(always)] + pub fn set_pd7(&mut self, val: super::vals::Pd7) { + self.0 = (self.0 & !(0x07 << 28usize)) | (((val.to_bits() as u32) & 0x07) << 28usize); + } +} +impl Default for Pdmuxsel { + #[inline(always)] + fn default() -> Pdmuxsel { + Pdmuxsel(0) + } +} +#[doc = "Drive Strength/Schmitt Trigger"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Pds(pub u32); +impl Pds { + #[doc = "Drive Strength"] + #[inline(always)] + pub const fn pds(&self, n: usize) -> super::vals::Pds { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x07; + super::vals::Pds::from_bits(val as u8) + } + #[doc = "Drive Strength"] + #[inline(always)] + pub fn set_pds(&mut self, n: usize, val: super::vals::Pds) { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x07 << offs)) | (((val.to_bits() as u32) & 0x07) << offs); + } + #[doc = "Schmitt Trigger Enable"] + #[inline(always)] + pub const fn pst(&self, n: usize) -> bool { + assert!(n < 8usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Schmitt Trigger Enable"] + #[inline(always)] + pub fn set_pst(&mut self, n: usize, val: bool) { + assert!(n < 8usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } +} +impl Default for Pds { + #[inline(always)] + fn default() -> Pds { + Pds(0) + } +} +#[doc = "PE Peripheral MUX Select"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Pemuxsel(pub u32); +impl Pemuxsel { + #[doc = "PE0 MUX Select"] + #[inline(always)] + pub const fn pe0(&self) -> super::vals::Pe0 { + let val = (self.0 >> 0usize) & 0x07; + super::vals::Pe0::from_bits(val as u8) + } + #[doc = "PE0 MUX Select"] + #[inline(always)] + pub fn set_pe0(&mut self, val: super::vals::Pe0) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); + } + #[doc = "PE1 MUX Select"] + #[inline(always)] + pub const fn pe1(&self) -> super::vals::Pe1 { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Pe1::from_bits(val as u8) + } + #[doc = "PE1 MUX Select"] + #[inline(always)] + pub fn set_pe1(&mut self, val: super::vals::Pe1) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize); + } + #[doc = "PE2 MUX Select"] + #[inline(always)] + pub const fn pe2(&self) -> super::vals::Pe2 { + let val = (self.0 >> 8usize) & 0x07; + super::vals::Pe2::from_bits(val as u8) + } + #[doc = "PE2 MUX Select"] + #[inline(always)] + pub fn set_pe2(&mut self, val: super::vals::Pe2) { + self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u32) & 0x07) << 8usize); + } + #[doc = "PE3 MUX Select"] + #[inline(always)] + pub const fn pe3(&self) -> super::vals::Pe3 { + let val = (self.0 >> 12usize) & 0x07; + super::vals::Pe3::from_bits(val as u8) + } + #[doc = "PE3 MUX Select"] + #[inline(always)] + pub fn set_pe3(&mut self, val: super::vals::Pe3) { + self.0 = (self.0 & !(0x07 << 12usize)) | (((val.to_bits() as u32) & 0x07) << 12usize); + } + #[doc = "PE4 MUX Select"] + #[inline(always)] + pub const fn pe4(&self) -> super::vals::Pe4 { + let val = (self.0 >> 16usize) & 0x07; + super::vals::Pe4::from_bits(val as u8) + } + #[doc = "PE4 MUX Select"] + #[inline(always)] + pub fn set_pe4(&mut self, val: super::vals::Pe4) { + self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize); + } + #[doc = "PE5 MUX Select"] + #[inline(always)] + pub const fn pe5(&self) -> super::vals::Pe5 { + let val = (self.0 >> 20usize) & 0x07; + super::vals::Pe5::from_bits(val as u8) + } + #[doc = "PE5 MUX Select"] + #[inline(always)] + pub fn set_pe5(&mut self, val: super::vals::Pe5) { + self.0 = (self.0 & !(0x07 << 20usize)) | (((val.to_bits() as u32) & 0x07) << 20usize); + } + #[doc = "PE6 MUX Select"] + #[inline(always)] + pub const fn pe6(&self) -> super::vals::Pe6 { + let val = (self.0 >> 24usize) & 0x07; + super::vals::Pe6::from_bits(val as u8) + } + #[doc = "PE6 MUX Select"] + #[inline(always)] + pub fn set_pe6(&mut self, val: super::vals::Pe6) { + self.0 = (self.0 & !(0x07 << 24usize)) | (((val.to_bits() as u32) & 0x07) << 24usize); + } + #[doc = "PE7 MUX Select"] + #[inline(always)] + pub const fn pe7(&self) -> super::vals::Pe7 { + let val = (self.0 >> 28usize) & 0x07; + super::vals::Pe7::from_bits(val as u8) + } + #[doc = "PE7 MUX Select"] + #[inline(always)] + pub fn set_pe7(&mut self, val: super::vals::Pe7) { + self.0 = (self.0 & !(0x07 << 28usize)) | (((val.to_bits() as u32) & 0x07) << 28usize); + } +} +impl Default for Pemuxsel { + #[inline(always)] + fn default() -> Pemuxsel { + Pemuxsel(0) + } +} +#[doc = "PF Peripheral MUX Select"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Pfmuxsel(pub u32); +impl Pfmuxsel { + #[doc = "PF0 MUX Select"] + #[inline(always)] + pub const fn pf0(&self) -> super::vals::Pf0 { + let val = (self.0 >> 0usize) & 0x07; + super::vals::Pf0::from_bits(val as u8) + } + #[doc = "PF0 MUX Select"] + #[inline(always)] + pub fn set_pf0(&mut self, val: super::vals::Pf0) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); + } + #[doc = "PF1 MUX Select"] + #[inline(always)] + pub const fn pf1(&self) -> super::vals::Pf1 { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Pf1::from_bits(val as u8) + } + #[doc = "PF1 MUX Select"] + #[inline(always)] + pub fn set_pf1(&mut self, val: super::vals::Pf1) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize); + } + #[doc = "PF2 MUX Select"] + #[inline(always)] + pub const fn pf2(&self) -> super::vals::Pf2 { + let val = (self.0 >> 8usize) & 0x07; + super::vals::Pf2::from_bits(val as u8) + } + #[doc = "PF2 MUX Select"] + #[inline(always)] + pub fn set_pf2(&mut self, val: super::vals::Pf2) { + self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u32) & 0x07) << 8usize); + } + #[doc = "PF3 MUX Select"] + #[inline(always)] + pub const fn pf3(&self) -> super::vals::Pf3 { + let val = (self.0 >> 12usize) & 0x07; + super::vals::Pf3::from_bits(val as u8) + } + #[doc = "PF3 MUX Select"] + #[inline(always)] + pub fn set_pf3(&mut self, val: super::vals::Pf3) { + self.0 = (self.0 & !(0x07 << 12usize)) | (((val.to_bits() as u32) & 0x07) << 12usize); + } + #[doc = "PF4 MUX Select"] + #[inline(always)] + pub const fn pf4(&self) -> super::vals::Pf4 { + let val = (self.0 >> 16usize) & 0x07; + super::vals::Pf4::from_bits(val as u8) + } + #[doc = "PF4 MUX Select"] + #[inline(always)] + pub fn set_pf4(&mut self, val: super::vals::Pf4) { + self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize); + } + #[doc = "PF5 MUX Select"] + #[inline(always)] + pub const fn pf5(&self) -> super::vals::Pf5 { + let val = (self.0 >> 20usize) & 0x07; + super::vals::Pf5::from_bits(val as u8) + } + #[doc = "PF5 MUX Select"] + #[inline(always)] + pub fn set_pf5(&mut self, val: super::vals::Pf5) { + self.0 = (self.0 & !(0x07 << 20usize)) | (((val.to_bits() as u32) & 0x07) << 20usize); + } + #[doc = "PF6 MUX Select"] + #[inline(always)] + pub const fn pf6(&self) -> super::vals::Pf6 { + let val = (self.0 >> 24usize) & 0x07; + super::vals::Pf6::from_bits(val as u8) + } + #[doc = "PF6 MUX Select"] + #[inline(always)] + pub fn set_pf6(&mut self, val: super::vals::Pf6) { + self.0 = (self.0 & !(0x07 << 24usize)) | (((val.to_bits() as u32) & 0x07) << 24usize); + } + #[doc = "PF7 MUX Select"] + #[inline(always)] + pub const fn pf7(&self) -> super::vals::Pf7 { + let val = (self.0 >> 28usize) & 0x07; + super::vals::Pf7::from_bits(val as u8) + } + #[doc = "PF7 MUX Select"] + #[inline(always)] + pub fn set_pf7(&mut self, val: super::vals::Pf7) { + self.0 = (self.0 & !(0x07 << 28usize)) | (((val.to_bits() as u32) & 0x07) << 28usize); + } +} +impl Default for Pfmuxsel { + #[inline(always)] + fn default() -> Pfmuxsel { + Pfmuxsel(0) + } +} +#[doc = "PG Peripheral MUX Select"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Pgmuxsel(pub u32); +impl Pgmuxsel { + #[doc = "PG0 MUX Select"] + #[inline(always)] + pub const fn pg0(&self) -> super::vals::Pg0 { + let val = (self.0 >> 0usize) & 0x07; + super::vals::Pg0::from_bits(val as u8) + } + #[doc = "PG0 MUX Select"] + #[inline(always)] + pub fn set_pg0(&mut self, val: super::vals::Pg0) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); + } + #[doc = "PG1 MUX Select"] + #[inline(always)] + pub const fn pg1(&self) -> super::vals::Pg1 { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Pg1::from_bits(val as u8) + } + #[doc = "PG1 MUX Select"] + #[inline(always)] + pub fn set_pg1(&mut self, val: super::vals::Pg1) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize); + } + #[doc = "PG2 MUX Select"] + #[inline(always)] + pub const fn pg2(&self) -> super::vals::Pg2 { + let val = (self.0 >> 8usize) & 0x07; + super::vals::Pg2::from_bits(val as u8) + } + #[doc = "PG2 MUX Select"] + #[inline(always)] + pub fn set_pg2(&mut self, val: super::vals::Pg2) { + self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u32) & 0x07) << 8usize); + } + #[doc = "PG3 MUX Select"] + #[inline(always)] + pub const fn pg3(&self) -> super::vals::Pg3 { + let val = (self.0 >> 12usize) & 0x07; + super::vals::Pg3::from_bits(val as u8) + } + #[doc = "PG3 MUX Select"] + #[inline(always)] + pub fn set_pg3(&mut self, val: super::vals::Pg3) { + self.0 = (self.0 & !(0x07 << 12usize)) | (((val.to_bits() as u32) & 0x07) << 12usize); + } + #[doc = "PG4 MUX Select"] + #[inline(always)] + pub const fn pg4(&self) -> super::vals::Pg4 { + let val = (self.0 >> 16usize) & 0x07; + super::vals::Pg4::from_bits(val as u8) + } + #[doc = "PG4 MUX Select"] + #[inline(always)] + pub fn set_pg4(&mut self, val: super::vals::Pg4) { + self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize); + } + #[doc = "PG5 MUX Select"] + #[inline(always)] + pub const fn pg5(&self) -> super::vals::Pg5 { + let val = (self.0 >> 20usize) & 0x07; + super::vals::Pg5::from_bits(val as u8) + } + #[doc = "PG5 MUX Select"] + #[inline(always)] + pub fn set_pg5(&mut self, val: super::vals::Pg5) { + self.0 = (self.0 & !(0x07 << 20usize)) | (((val.to_bits() as u32) & 0x07) << 20usize); + } + #[doc = "PG6 MUX Select"] + #[inline(always)] + pub const fn pg6(&self) -> super::vals::Pg6 { + let val = (self.0 >> 24usize) & 0x07; + super::vals::Pg6::from_bits(val as u8) + } + #[doc = "PG6 MUX Select"] + #[inline(always)] + pub fn set_pg6(&mut self, val: super::vals::Pg6) { + self.0 = (self.0 & !(0x07 << 24usize)) | (((val.to_bits() as u32) & 0x07) << 24usize); + } + #[doc = "PG7 MUX Select"] + #[inline(always)] + pub const fn pg7(&self) -> super::vals::Pg7 { + let val = (self.0 >> 28usize) & 0x07; + super::vals::Pg7::from_bits(val as u8) + } + #[doc = "PG7 MUX Select"] + #[inline(always)] + pub fn set_pg7(&mut self, val: super::vals::Pg7) { + self.0 = (self.0 & !(0x07 << 28usize)) | (((val.to_bits() as u32) & 0x07) << 28usize); + } +} +impl Default for Pgmuxsel { + #[inline(always)] + fn default() -> Pgmuxsel { + Pgmuxsel(0) + } +} +#[doc = "Weak Pull-down Enable"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Ppden(pub u32); +impl Ppden { + #[doc = "Weak Pull-down Enable"] + #[inline(always)] + pub const fn p(&self, n: usize) -> bool { + assert!(n < 8usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Weak Pull-down Enable"] + #[inline(always)] + pub fn set_p(&mut self, n: usize, val: bool) { + assert!(n < 8usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } +} +impl Default for Ppden { + #[inline(always)] + fn default() -> Ppden { + Ppden(0) + } +} +#[doc = "Weak Pull-up Enable"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Ppuen(pub u32); +impl Ppuen { + #[doc = "Weak Pull-up Enable"] + #[inline(always)] + pub const fn p(&self, n: usize) -> bool { + assert!(n < 8usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Weak Pull-up Enable"] + #[inline(always)] + pub fn set_p(&mut self, n: usize, val: bool) { + assert!(n < 8usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } +} +impl Default for Ppuen { + #[inline(always)] + fn default() -> Ppuen { + Ppuen(0) + } +} diff --git a/src/scc/vals.rs b/src/scc/vals.rs new file mode 100644 index 0000000..1a01130 --- /dev/null +++ b/src/scc/vals.rs @@ -0,0 +1,2571 @@ +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Aclkdiv { + #[doc = "SCLK/1"] + SCLK1 = 0x0, + #[doc = "SCLK/2"] + SCLK2 = 0x01, + #[doc = "SCLK/3"] + SCLK3 = 0x02, + #[doc = "SCLK/4"] + SCLK4 = 0x03, + #[doc = "SCLK/5"] + SCLK5 = 0x04, + #[doc = "SCLK/6"] + SCLK6 = 0x05, + #[doc = "SCLK/7"] + SCLK7 = 0x06, + #[doc = "SCLK/8"] + SCLK8 = 0x07, +} +impl Aclkdiv { + #[inline(always)] + pub const fn from_bits(val: u8) -> Aclkdiv { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Aclkdiv { + #[inline(always)] + fn from(val: u8) -> Aclkdiv { + Aclkdiv::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Aclkdiv) -> u8 { + Aclkdiv::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Clkfailmuxsel { + #[doc = "FRCLK selected as input to Clock Fail"] + FRCLK = 0x0, + #[doc = "PLLCLK selected as input to Clock Fail"] + PLLCLK = 0x01, +} +impl Clkfailmuxsel { + #[inline(always)] + pub const fn from_bits(val: u8) -> Clkfailmuxsel { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Clkfailmuxsel { + #[inline(always)] + fn from(val: u8) -> Clkfailmuxsel { + Clkfailmuxsel::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Clkfailmuxsel) -> u8 { + Clkfailmuxsel::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Frclkmuxsel { + #[doc = "ROSC selected as input to FRCLK"] + ROSC = 0x0, + #[doc = "CLKREF selected as input to FRCLK"] + CLKREF = 0x01, + _RESERVED_2 = 0x02, + #[doc = "External Clock selected as input to FRCLK"] + EXTCLK = 0x03, +} +impl Frclkmuxsel { + #[inline(always)] + pub const fn from_bits(val: u8) -> Frclkmuxsel { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Frclkmuxsel { + #[inline(always)] + fn from(val: u8) -> Frclkmuxsel { + Frclkmuxsel::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Frclkmuxsel) -> u8 { + Frclkmuxsel::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Hclkdiv { + #[doc = "SCLK/1"] + SCLK1 = 0x0, + #[doc = "SCLK/2"] + SCLK2 = 0x01, + #[doc = "SCLK/3"] + SCLK3 = 0x02, + #[doc = "SCLK/4"] + SCLK4 = 0x03, + #[doc = "SCLK/5"] + SCLK5 = 0x04, + #[doc = "SCLK/6"] + SCLK6 = 0x05, + #[doc = "SCLK/7"] + SCLK7 = 0x06, + #[doc = "SCLK/8"] + SCLK8 = 0x07, +} +impl Hclkdiv { + #[inline(always)] + pub const fn from_bits(val: u8) -> Hclkdiv { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Hclkdiv { + #[inline(always)] + fn from(val: u8) -> Hclkdiv { + Hclkdiv::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Hclkdiv) -> u8 { + Hclkdiv::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pa0 { + #[doc = "GPIO"] + GPIOA0 = 0x0, + _RESERVED_1 = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl Pa0 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pa0 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pa0 { + #[inline(always)] + fn from(val: u8) -> Pa0 { + Pa0::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pa0) -> u8 { + Pa0::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pa1 { + #[doc = "GPIO"] + GPIOA1 = 0x0, + #[doc = "EMUX Data"] + EMUXD = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl Pa1 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pa1 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pa1 { + #[inline(always)] + fn from(val: u8) -> Pa1 { + Pa1::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pa1) -> u8 { + Pa1::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pa2 { + #[doc = "GPIO"] + GPIOA2 = 0x0, + #[doc = "EMUX Clock"] + EMUXC = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl Pa2 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pa2 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pa2 { + #[inline(always)] + fn from(val: u8) -> Pa2 { + Pa2::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pa2) -> u8 { + Pa2::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pa3 { + #[doc = "GPIO"] + GPIOA3 = 0x0, + #[doc = "USART A SCLK"] + USASCLK = 0x01, + #[doc = "USART B SCLK"] + USBSCLK = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl Pa3 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pa3 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pa3 { + #[inline(always)] + fn from(val: u8) -> Pa3 { + Pa3::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pa3) -> u8 { + Pa3::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pa4 { + #[doc = "GPIO"] + GPIOA4 = 0x0, + #[doc = "USART A MOSI/TX"] + USAMOSI = 0x01, + #[doc = "USART B MOSI/TX"] + USBMOSI = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl Pa4 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pa4 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pa4 { + #[inline(always)] + fn from(val: u8) -> Pa4 { + Pa4::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pa4) -> u8 { + Pa4::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pa5 { + #[doc = "GPIO"] + GPIOA5 = 0x0, + #[doc = "USART A MISO/RX"] + USAMISO = 0x01, + #[doc = "USART B MISO/RX"] + USBMISO = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl Pa5 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pa5 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pa5 { + #[inline(always)] + fn from(val: u8) -> Pa5 { + Pa5::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pa5) -> u8 { + Pa5::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pa6 { + #[doc = "GPIO"] + GPIOA6 = 0x0, + #[doc = "USART A SPI Slave Select"] + USASS = 0x01, + #[doc = "USART B SPI Slave Select"] + USBSS = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl Pa6 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pa6 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pa6 { + #[inline(always)] + fn from(val: u8) -> Pa6 { + Pa6::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pa6) -> u8 { + Pa6::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pa7 { + #[doc = "GPIO"] + GPIOA7 = 0x0, + _RESERVED_1 = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl Pa7 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pa7 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pa7 { + #[inline(always)] + fn from(val: u8) -> Pa7 { + Pa7::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pa7) -> u8 { + Pa7::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pb0 { + #[doc = "GPIO"] + GPIOB0 = 0x0, + #[doc = "Timer A PWM0"] + TAPWM0 = 0x01, + #[doc = "Timer B PWM0"] + TBPWM0 = 0x02, + _RESERVED_3 = 0x03, + #[doc = "Timer C PWM0"] + TCPWM0 = 0x04, + #[doc = "Timer D PWM0"] + TDPWM0 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl Pb0 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pb0 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pb0 { + #[inline(always)] + fn from(val: u8) -> Pb0 { + Pb0::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pb0) -> u8 { + Pb0::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pb1 { + #[doc = "GPIO"] + GPIOB1 = 0x0, + #[doc = "Timer A PWM1"] + TAPWM1 = 0x01, + #[doc = "Timer B PWM1"] + TBPWM1 = 0x02, + _RESERVED_3 = 0x03, + #[doc = "Timer C PWM1"] + TCPWM1 = 0x04, + #[doc = "Timer D PWM1"] + TDPWM1 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl Pb1 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pb1 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pb1 { + #[inline(always)] + fn from(val: u8) -> Pb1 { + Pb1::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pb1) -> u8 { + Pb1::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pb2 { + #[doc = "GPIO"] + GPIOB2 = 0x0, + #[doc = "Timer A PWM2"] + TAPWM2 = 0x01, + #[doc = "Timer B PWM2"] + TBPWM2 = 0x02, + _RESERVED_3 = 0x03, + #[doc = "Timer C PWM2"] + TCPWM2 = 0x04, + #[doc = "Timer D PWM2"] + TDPWM2 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl Pb2 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pb2 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pb2 { + #[inline(always)] + fn from(val: u8) -> Pb2 { + Pb2::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pb2) -> u8 { + Pb2::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pb3 { + #[doc = "GPIO"] + GPIOB3 = 0x0, + #[doc = "Timer A PWM3"] + TAPWM3 = 0x01, + #[doc = "Timer B PWM3"] + TBPWM3 = 0x02, + _RESERVED_3 = 0x03, + #[doc = "Timer C PWM3"] + TCPWM3 = 0x04, + #[doc = "Timer D PWM3"] + TDPWM3 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl Pb3 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pb3 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pb3 { + #[inline(always)] + fn from(val: u8) -> Pb3 { + Pb3::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pb3) -> u8 { + Pb3::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pb4 { + #[doc = "GPIO"] + GPIOB4 = 0x0, + #[doc = "Timer A PWM4"] + TAPWM4 = 0x01, + #[doc = "Timer B PWM4"] + TBPWM4 = 0x02, + #[doc = "Timer C PWM0"] + TCPWM0 = 0x03, + #[doc = "Timer C PWM4"] + TCPWM4 = 0x04, + #[doc = "Timer D PWM4"] + TDPWM4 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl Pb4 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pb4 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pb4 { + #[inline(always)] + fn from(val: u8) -> Pb4 { + Pb4::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pb4) -> u8 { + Pb4::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pb5 { + #[doc = "GPIO"] + GPIOB5 = 0x0, + #[doc = "Timer A PWM5"] + TAPWM5 = 0x01, + #[doc = "Timer B PWM5"] + TBPWM5 = 0x02, + #[doc = "Timer C PWM1"] + TCPWM1 = 0x03, + #[doc = "Timer C PWM5"] + TCPWM5 = 0x04, + #[doc = "Timer D PWM5"] + TDPWM5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl Pb5 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pb5 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pb5 { + #[inline(always)] + fn from(val: u8) -> Pb5 { + Pb5::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pb5) -> u8 { + Pb5::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pb6 { + #[doc = "GPIO"] + GPIOB6 = 0x0, + #[doc = "Timer A PWM6"] + TAPWM6 = 0x01, + #[doc = "Timer B PWM6"] + TBPWM6 = 0x02, + #[doc = "Timer C PWM2"] + TCPWM2 = 0x03, + #[doc = "Timer C PWM6"] + TCPWM6 = 0x04, + #[doc = "Timer D PWM6"] + TDPWM6 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl Pb6 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pb6 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pb6 { + #[inline(always)] + fn from(val: u8) -> Pb6 { + Pb6::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pb6) -> u8 { + Pb6::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pb7 { + #[doc = "GPIO"] + GPIOB7 = 0x0, + #[doc = "Timer A PWM7"] + TAPWM7 = 0x01, + #[doc = "Timer B PWM7"] + TBPWM7 = 0x02, + #[doc = "Timer C PWM3"] + TCPWM3 = 0x03, + #[doc = "Timer C PWM7"] + TCPWM7 = 0x04, + #[doc = "Timer D PWM7"] + TDPWM7 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl Pb7 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pb7 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pb7 { + #[inline(always)] + fn from(val: u8) -> Pb7 { + Pb7::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pb7) -> u8 { + Pb7::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pc0 { + #[doc = "GPIO"] + GPIOC0 = 0x0, + #[doc = "Timer B PWM0"] + TBPWM0 = 0x01, + #[doc = "Timer C PWM0"] + TCPWM0 = 0x02, + #[doc = "Timer B QEP Index"] + TBQEPIDX = 0x03, + #[doc = "USART B MOSI/TX"] + USBMOSI = 0x04, + #[doc = "USART C SPI Clock"] + USCSCLK = 0x05, + #[doc = "CAN Rx Data"] + CANRXD = 0x06, + #[doc = "I2C SCL"] + I2CSCL = 0x07, +} +impl Pc0 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pc0 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pc0 { + #[inline(always)] + fn from(val: u8) -> Pc0 { + Pc0::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pc0) -> u8 { + Pc0::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pc1 { + #[doc = "GPIO"] + GPIOC1 = 0x0, + #[doc = "Timer B PWM1"] + TBPWM1 = 0x01, + #[doc = "Timer C PWM1"] + TCPWM1 = 0x02, + #[doc = "Timer B QEP Phase A"] + TBQEPPHA = 0x03, + #[doc = "USART B MISO/RX"] + USBMISO = 0x04, + #[doc = "USART C Slave Select"] + USCSS = 0x05, + #[doc = "CAN Tx Data"] + CANTXD = 0x06, + #[doc = "I2C SDA"] + I2CSDA = 0x07, +} +impl Pc1 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pc1 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pc1 { + #[inline(always)] + fn from(val: u8) -> Pc1 { + Pc1::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pc1) -> u8 { + Pc1::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pc2 { + #[doc = "GPIO"] + GPIOC2 = 0x0, + #[doc = "Timer B PWM2"] + TBPWM2 = 0x01, + #[doc = "Timer C PWM2"] + TCPWM2 = 0x02, + #[doc = "Timer B QEP Phase B"] + TBQEPPHB = 0x03, + #[doc = "USART B SCLK"] + USBSCLK = 0x04, + #[doc = "USART C MOSI/TX"] + USCMOSI = 0x05, + _RESERVED_6 = 0x06, + #[doc = "EMUX Data"] + EMUXD = 0x07, +} +impl Pc2 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pc2 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pc2 { + #[inline(always)] + fn from(val: u8) -> Pc2 { + Pc2::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pc2) -> u8 { + Pc2::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pc3 { + #[doc = "GPIO"] + GPIOC3 = 0x0, + #[doc = "Timer B PWM3"] + TBPWM3 = 0x01, + #[doc = "Timer C PWM3"] + TCPWM3 = 0x02, + _RESERVED_3 = 0x03, + #[doc = "USART B Slave Select"] + USBSS = 0x04, + #[doc = "USART C MISO/RX"] + USCMISO = 0x05, + _RESERVED_6 = 0x06, + #[doc = "EMUX Clock"] + EMUXC = 0x07, +} +impl Pc3 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pc3 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pc3 { + #[inline(always)] + fn from(val: u8) -> Pc3 { + Pc3::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pc3) -> u8 { + Pc3::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pc4 { + #[doc = "GPIO"] + GPIOC4 = 0x0, + #[doc = "Timer B PWM4"] + TBPWM4 = 0x01, + #[doc = "Timer C PWM4"] + TCPWM4 = 0x02, + #[doc = "Timer C QEP Index"] + TCQEPIDX = 0x03, + #[doc = "USART B MOSI/TX"] + USBMOSI = 0x04, + #[doc = "USART C SPI Clock"] + USCSCLK = 0x05, + #[doc = "CAN Rx Data"] + CANRXD = 0x06, + #[doc = "I2C SCL"] + I2CSCL = 0x07, +} +impl Pc4 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pc4 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pc4 { + #[inline(always)] + fn from(val: u8) -> Pc4 { + Pc4::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pc4) -> u8 { + Pc4::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pc5 { + #[doc = "GPIO"] + GPIOC5 = 0x0, + #[doc = "Timer B PWM5"] + TBPWM5 = 0x01, + #[doc = "Timer C PWM5"] + TCPWM5 = 0x02, + #[doc = "Timer C QEP Phase A"] + TCQEPPHA = 0x03, + #[doc = "USART B MISO/RX"] + USBMISO = 0x04, + #[doc = "USART C Slave Select"] + USCSS = 0x05, + #[doc = "CAN Tx Data"] + CANTXD = 0x06, + #[doc = "I2C SDA"] + I2CSDA = 0x07, +} +impl Pc5 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pc5 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pc5 { + #[inline(always)] + fn from(val: u8) -> Pc5 { + Pc5::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pc5) -> u8 { + Pc5::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pc6 { + #[doc = "GPIO"] + GPIOC6 = 0x0, + #[doc = "Timer B PWM6"] + TBPWM6 = 0x01, + #[doc = "Timer C PWM6"] + TCPWM6 = 0x02, + #[doc = "Timer C QEP Phase B"] + TCQEPPHB = 0x03, + #[doc = "USART B SCLK"] + USBSCLK = 0x04, + #[doc = "USART C MOSI/TX"] + USCMOSI = 0x05, + _RESERVED_6 = 0x06, + #[doc = "EMUX Data"] + EMUXD = 0x07, +} +impl Pc6 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pc6 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pc6 { + #[inline(always)] + fn from(val: u8) -> Pc6 { + Pc6::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pc6) -> u8 { + Pc6::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pc7 { + #[doc = "GPIO"] + GPIOC7 = 0x0, + #[doc = "Timer B PWM7"] + TBPWM7 = 0x01, + #[doc = "Timer C PWM7"] + TCPWM7 = 0x02, + _RESERVED_3 = 0x03, + #[doc = "USART B Slave Select"] + USBSS = 0x04, + #[doc = "USART C MISO/RX"] + USCMISO = 0x05, + #[doc = "FRCLK Output"] + FRCLK = 0x06, + #[doc = "EMUX Clock"] + EMUXC = 0x07, +} +impl Pc7 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pc7 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pc7 { + #[inline(always)] + fn from(val: u8) -> Pc7 { + Pc7::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pc7) -> u8 { + Pc7::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pclkdiv { + #[doc = "HCLK/1"] + HCLK1 = 0x0, + #[doc = "HCLK/2"] + HCLK2 = 0x01, + #[doc = "HCLK/3"] + HCLK3 = 0x02, + #[doc = "HCLK/4"] + HCLK4 = 0x03, + #[doc = "HCLK/5"] + HCLK5 = 0x04, + #[doc = "HCLK/6"] + HCLK6 = 0x05, + #[doc = "HCLK/7"] + HCLK7 = 0x06, + #[doc = "HCLK/8"] + HCLK8 = 0x07, +} +impl Pclkdiv { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pclkdiv { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pclkdiv { + #[inline(always)] + fn from(val: u8) -> Pclkdiv { + Pclkdiv::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pclkdiv) -> u8 { + Pclkdiv::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pd0 { + #[doc = "GPIO"] + GPIOD0 = 0x0, + #[doc = "Timer B PWM0"] + TBPWM0 = 0x01, + #[doc = "Timer C PWM0"] + TCPWM0 = 0x02, + #[doc = "Timer D QEP Index"] + TDQEPIDX = 0x03, + _RESERVED_4 = 0x04, + #[doc = "USART C SPI Clock"] + USCSCLK = 0x05, + #[doc = "CAN Tx Data"] + CANTXD = 0x06, + #[doc = "EMUX Data"] + EMUXD = 0x07, +} +impl Pd0 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pd0 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pd0 { + #[inline(always)] + fn from(val: u8) -> Pd0 { + Pd0::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pd0) -> u8 { + Pd0::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pd1 { + #[doc = "GPIO"] + GPIOD1 = 0x0, + #[doc = "Timer B PWM1"] + TBPWM1 = 0x01, + #[doc = "Timer C PWM1"] + TCPWM1 = 0x02, + #[doc = "Timer D QEP Phase A"] + TDQEPPHA = 0x03, + _RESERVED_4 = 0x04, + #[doc = "USART C Slave Select"] + USCSS = 0x05, + #[doc = "CAN Rx Data"] + CANRXD = 0x06, + #[doc = "EMUX Clock"] + EMUXC = 0x07, +} +impl Pd1 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pd1 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pd1 { + #[inline(always)] + fn from(val: u8) -> Pd1 { + Pd1::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pd1) -> u8 { + Pd1::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pd2 { + #[doc = "GPIO"] + GPIOD2 = 0x0, + #[doc = "Timer B PWM2"] + TBPWM2 = 0x01, + #[doc = "Timer C PWM2"] + TCPWM2 = 0x02, + #[doc = "Timer D QEP Phase B"] + TDQEPPHB = 0x03, + _RESERVED_4 = 0x04, + #[doc = "USART C MOSI/TX"] + USCMOSI = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl Pd2 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pd2 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pd2 { + #[inline(always)] + fn from(val: u8) -> Pd2 { + Pd2::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pd2) -> u8 { + Pd2::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pd3 { + #[doc = "GPIO"] + GPIOD3 = 0x0, + #[doc = "Timer B PWM3"] + TBPWM3 = 0x01, + #[doc = "Timer C PWM3"] + TCPWM3 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + #[doc = "USART C MISO/RX"] + USCMISO = 0x05, + #[doc = "FRCLK output"] + FRCLK = 0x06, + #[doc = "TRACE Data 3 output"] + TRACED3 = 0x07, +} +impl Pd3 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pd3 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pd3 { + #[inline(always)] + fn from(val: u8) -> Pd3 { + Pd3::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pd3) -> u8 { + Pd3::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pd4 { + #[doc = "GPIO"] + GPIOD4 = 0x0, + #[doc = "Timer B PWM4"] + TBPWM4 = 0x01, + #[doc = "Timer C PWM4"] + TCPWM4 = 0x02, + #[doc = "Timer D QEP Index"] + TDQEPIDX = 0x03, + #[doc = "Timer B QEP Index"] + TBQEPIDX = 0x04, + #[doc = "USART D SPI Clock"] + USDSCLK = 0x05, + #[doc = "TRACE Data 3 output"] + TRACED3 = 0x06, + #[doc = "USART D MOSI/TX"] + USDMOSI = 0x07, +} +impl Pd4 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pd4 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pd4 { + #[inline(always)] + fn from(val: u8) -> Pd4 { + Pd4::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pd4) -> u8 { + Pd4::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pd5 { + #[doc = "GPIO"] + GPIOD5 = 0x0, + #[doc = "Timer B PWM5"] + TBPWM5 = 0x01, + #[doc = "Timer C PWM5"] + TCPWM5 = 0x02, + #[doc = "Timer D QEP Phase A"] + TDQEPPHA = 0x03, + #[doc = "Timer D QEP Phase B"] + TDQEPPHB = 0x04, + #[doc = "USART D Slave Select"] + USDSS = 0x05, + #[doc = "CAN Rx Data"] + CANRXD = 0x06, + #[doc = "USART D MISO/RX"] + USDMISO = 0x07, +} +impl Pd5 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pd5 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pd5 { + #[inline(always)] + fn from(val: u8) -> Pd5 { + Pd5::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pd5) -> u8 { + Pd5::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pd6 { + #[doc = "GPIO"] + GPIOD6 = 0x0, + #[doc = "Timer B PWM6"] + TBPWM6 = 0x01, + #[doc = "Timer C PWM6"] + TCPWM6 = 0x02, + #[doc = "Timer D QEP Phase B"] + TDQEPPHB = 0x03, + #[doc = "Timer B QEP Phase B"] + TBQEPPHB = 0x04, + #[doc = "USART D MOSI/TX"] + USDMOSI = 0x05, + #[doc = "CAN Tx Data"] + CANTXD = 0x06, + #[doc = "I2C SDA"] + I2CSDA = 0x07, +} +impl Pd6 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pd6 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pd6 { + #[inline(always)] + fn from(val: u8) -> Pd6 { + Pd6::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pd6) -> u8 { + Pd6::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pd7 { + #[doc = "GPIO"] + GPIOD7 = 0x0, + #[doc = "Timer B PWM7"] + TBPWM7 = 0x01, + #[doc = "Timer C PWM7"] + TCPWM7 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + #[doc = "USART C MISO/RX"] + USDMISO = 0x05, + #[doc = "CAN Rx Data"] + CANRXD = 0x06, + #[doc = "I2C SCL"] + I2CSCL = 0x07, +} +impl Pd7 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pd7 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pd7 { + #[inline(always)] + fn from(val: u8) -> Pd7 { + Pd7::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pd7) -> u8 { + Pd7::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pds { + #[doc = "6 mA"] + DS_6MA = 0x0, + #[doc = "8 mA"] + DS_8MA = 0x01, + #[doc = "11 mA"] + DS_11MA = 0x02, + #[doc = "14 mA"] + DS_14MA = 0x03, + #[doc = "17 mA"] + DS_17MA = 0x04, + #[doc = "20 mA"] + DS_20MA = 0x05, + #[doc = "22 mA"] + DS_22MA = 0x06, + #[doc = "25 mA"] + DS_25MA = 0x07, +} +impl Pds { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pds { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pds { + #[inline(always)] + fn from(val: u8) -> Pds { + Pds::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pds) -> u8 { + Pds::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pe0 { + #[doc = "GPIO"] + GPIOE0 = 0x0, + #[doc = "Timer C PWM4"] + TCPWM4 = 0x01, + #[doc = "Timer D PWM0"] + TDPWM0 = 0x02, + #[doc = "Timer A QEP Index"] + TAQEPIDX = 0x03, + #[doc = "Timer B QEP Index"] + TBQEPIDX = 0x04, + #[doc = "USART C SPI Clock"] + USCSCLK = 0x05, + #[doc = "I2C SCL"] + I2CSCL = 0x06, + #[doc = "EMUX Clock"] + EMUXC = 0x07, +} +impl Pe0 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pe0 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pe0 { + #[inline(always)] + fn from(val: u8) -> Pe0 { + Pe0::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pe0) -> u8 { + Pe0::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pe1 { + #[doc = "GPIO"] + GPIOE1 = 0x0, + #[doc = "Timer C PWM5"] + TCPWM5 = 0x01, + #[doc = "Timer D PWM1"] + TDPWM1 = 0x02, + #[doc = "Timer A QEP Phase A"] + TAQEPPHA = 0x03, + #[doc = "Timer B QEP Phase A"] + TBQEPPHA = 0x04, + #[doc = "USART C Slave Select"] + USCSS = 0x05, + #[doc = "I2C SDA"] + I2CSDA = 0x06, + #[doc = "EMUX Data"] + EMUXD = 0x07, +} +impl Pe1 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pe1 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pe1 { + #[inline(always)] + fn from(val: u8) -> Pe1 { + Pe1::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pe1) -> u8 { + Pe1::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pe2 { + #[doc = "GPIO"] + GPIOE2 = 0x0, + #[doc = "Timer C PWM6"] + TCPWM6 = 0x01, + #[doc = "Timer D PWM2"] + TDPWM2 = 0x02, + #[doc = "Timer A QEP Phase B"] + TAQEPPHB = 0x03, + #[doc = "Timer B QEP Phase B"] + TBQEPPHB = 0x04, + #[doc = "USART C MOSI/TX"] + USCMOSI = 0x05, + #[doc = "CAN Rx Data"] + CANRXD = 0x06, + #[doc = "External clock input"] + EXTCLK = 0x07, +} +impl Pe2 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pe2 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pe2 { + #[inline(always)] + fn from(val: u8) -> Pe2 { + Pe2::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pe2) -> u8 { + Pe2::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pe3 { + #[doc = "GPIO"] + GPIOE3 = 0x0, + #[doc = "Timer C PWM7"] + TCPWM7 = 0x01, + #[doc = "Timer D PWM3"] + TDPWM3 = 0x02, + #[doc = "FRCLK Output"] + FRCLK = 0x03, + _RESERVED_4 = 0x04, + #[doc = "USART C MISO/RX"] + USCMISO = 0x05, + #[doc = "CAN Tx Data"] + CANTXD = 0x06, + _RESERVED_7 = 0x07, +} +impl Pe3 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pe3 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pe3 { + #[inline(always)] + fn from(val: u8) -> Pe3 { + Pe3::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pe3) -> u8 { + Pe3::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pe4 { + #[doc = "GPIO"] + GPIOE4 = 0x0, + #[doc = "Timer C PWM4"] + TCPWM4 = 0x01, + #[doc = "Timer D PWM4"] + TDPWM4 = 0x02, + #[doc = "Timer D QEP Index"] + TDQEPIDX = 0x03, + #[doc = "USART B SCLK"] + USBSCLK = 0x04, + #[doc = "USART D MOSI/TX"] + USDMOSI = 0x05, + #[doc = "I2C SCL"] + I2CSCL = 0x06, + _RESERVED_7 = 0x07, +} +impl Pe4 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pe4 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pe4 { + #[inline(always)] + fn from(val: u8) -> Pe4 { + Pe4::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pe4) -> u8 { + Pe4::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pe5 { + #[doc = "GPIO"] + GPIOE5 = 0x0, + #[doc = "Timer C PWM5"] + TCPWM5 = 0x01, + #[doc = "Timer D PWM5"] + TDPWM5 = 0x02, + #[doc = "Timer D QEP Phase A"] + TDQEPPHA = 0x03, + #[doc = "USART B Slave Select"] + USBSS = 0x04, + #[doc = "USART D MISO/RX"] + USDMISO = 0x05, + #[doc = "I2C SDA"] + I2CSDA = 0x06, + _RESERVED_7 = 0x07, +} +impl Pe5 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pe5 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pe5 { + #[inline(always)] + fn from(val: u8) -> Pe5 { + Pe5::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pe5) -> u8 { + Pe5::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pe6 { + #[doc = "GPIO"] + GPIOE6 = 0x0, + #[doc = "Timer C PWM6"] + TCPWM6 = 0x01, + #[doc = "Timer D PWM6"] + TDPWM6 = 0x02, + #[doc = "Timer D QEP Phase B"] + TDQEPPHB = 0x03, + #[doc = "USART B MOSI/TX"] + USBMOSI = 0x04, + #[doc = "USART D SCLK"] + USDSCLK = 0x05, + #[doc = "CAN RX Data"] + CANRXD = 0x06, + _RESERVED_7 = 0x07, +} +impl Pe6 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pe6 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pe6 { + #[inline(always)] + fn from(val: u8) -> Pe6 { + Pe6::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pe6) -> u8 { + Pe6::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pe7 { + #[doc = "GPIO"] + GPIOE7 = 0x0, + #[doc = "Timer C PWM7"] + TCPWM7 = 0x01, + #[doc = "Timer D PWM7"] + TDPWM7 = 0x02, + _RESERVED_3 = 0x03, + #[doc = "USART B MISO/RX"] + USBMISO = 0x04, + #[doc = "USART D Slave Select"] + USDSS = 0x05, + #[doc = "CAN TX Data"] + CANTXD = 0x06, + _RESERVED_7 = 0x07, +} +impl Pe7 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pe7 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pe7 { + #[inline(always)] + fn from(val: u8) -> Pe7 { + Pe7::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pe7) -> u8 { + Pe7::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pf0 { + #[doc = "GPIO"] + GPIOF0 = 0x0, + #[doc = "Timer C PWM0"] + TCPWM0 = 0x01, + #[doc = "Timer D PWM0"] + TDPWM0 = 0x02, + #[doc = "TCK/SWDCLK"] + TCK_SWDCLK = 0x03, + #[doc = "Timer B QEP Index"] + TBQEPIDX = 0x04, + #[doc = "USART B SPI Clock"] + USBSCLK = 0x05, + #[doc = "Trace Data 2 output"] + TRACED2 = 0x06, + #[doc = "Trace Clock"] + TRACECLK = 0x07, +} +impl Pf0 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pf0 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pf0 { + #[inline(always)] + fn from(val: u8) -> Pf0 { + Pf0::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pf0) -> u8 { + Pf0::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pf1 { + #[doc = "GPIO"] + GPIOF1 = 0x0, + #[doc = "Timer C PWM1"] + TCPWM1 = 0x01, + #[doc = "Timer D PWM1"] + TDPWM1 = 0x02, + #[doc = "TMS/SWDIO"] + TMS_SWDIO = 0x03, + #[doc = "Timer B QEP Phase A"] + TBQEPPHA = 0x04, + #[doc = "USART B Slave Select"] + USBSS = 0x05, + #[doc = "Trace Data 1 output"] + TRACED1 = 0x06, + #[doc = "Trace Data 0 output"] + TRACED0 = 0x07, +} +impl Pf1 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pf1 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pf1 { + #[inline(always)] + fn from(val: u8) -> Pf1 { + Pf1::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pf1) -> u8 { + Pf1::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pf2 { + #[doc = "GPIO"] + GPIOF2 = 0x0, + #[doc = "Timer C PWM2"] + TCPWM2 = 0x01, + #[doc = "Timer D PWM2"] + TDPWM2 = 0x02, + #[doc = "Test Data In"] + TDI = 0x03, + #[doc = "Timer B QEP Phase B"] + TBQEPPHB = 0x04, + #[doc = "USART B MOSI/TX"] + USBMOSI = 0x05, + #[doc = "Trace Data 0 output"] + TRACED0 = 0x06, + #[doc = "Trace Data 1 output"] + TRACED1 = 0x07, +} +impl Pf2 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pf2 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pf2 { + #[inline(always)] + fn from(val: u8) -> Pf2 { + Pf2::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pf2) -> u8 { + Pf2::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pf3 { + #[doc = "GPIO"] + GPIOF3 = 0x0, + #[doc = "Timer C PWM3"] + TCPWM3 = 0x01, + #[doc = "Timer D PWM3"] + TDPWM3 = 0x02, + #[doc = "Test Data Out"] + TDO = 0x03, + #[doc = "FRCLK Output"] + FRCLK = 0x04, + #[doc = "USART B MISO/RX"] + USBMISO = 0x05, + #[doc = "Trace Clock"] + TRACECLK = 0x06, + #[doc = "Trace Data 2 output"] + TRACED2 = 0x07, +} +impl Pf3 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pf3 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pf3 { + #[inline(always)] + fn from(val: u8) -> Pf3 { + Pf3::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pf3) -> u8 { + Pf3::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pf4 { + #[doc = "GPIO"] + GPIOF4 = 0x0, + #[doc = "Timer C PWM4"] + TCPWM4 = 0x01, + #[doc = "Timer D PWM4"] + TDPWM4 = 0x02, + _RESERVED_3 = 0x03, + #[doc = "Timer C QEP Index"] + TCQEPIDX = 0x04, + #[doc = "USART D SCLK"] + USDSCLK = 0x05, + #[doc = "Trace Data 3 output"] + TRACED3 = 0x06, + #[doc = "EMUX Clock"] + EMUXC = 0x07, +} +impl Pf4 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pf4 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pf4 { + #[inline(always)] + fn from(val: u8) -> Pf4 { + Pf4::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pf4) -> u8 { + Pf4::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pf5 { + #[doc = "GPIO"] + GPIOF5 = 0x0, + #[doc = "Timer C PWM5"] + TCPWM5 = 0x01, + #[doc = "Timer D PWM5"] + TDPWM5 = 0x02, + _RESERVED_3 = 0x03, + #[doc = "Timer C QEP Phase A"] + TCQEPPHA = 0x04, + #[doc = "USART D Slave Select"] + USDSS = 0x05, + _RESERVED_6 = 0x06, + #[doc = "EMUX Data"] + EMUXD = 0x07, +} +impl Pf5 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pf5 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pf5 { + #[inline(always)] + fn from(val: u8) -> Pf5 { + Pf5::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pf5) -> u8 { + Pf5::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pf6 { + #[doc = "GPIO"] + GPIOF6 = 0x0, + #[doc = "Timer C PWM6"] + TCPWM6 = 0x01, + #[doc = "Timer D PWM6"] + TDPWM6 = 0x02, + _RESERVED_3 = 0x03, + #[doc = "Timer C QEP Phase B"] + TCQEPPHB = 0x04, + #[doc = "USART D MOSI/TX"] + USDMOSI = 0x05, + #[doc = "CAN RX Data"] + CANRXD = 0x06, + #[doc = "I2C SCL"] + I2CSCL = 0x07, +} +impl Pf6 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pf6 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pf6 { + #[inline(always)] + fn from(val: u8) -> Pf6 { + Pf6::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pf6) -> u8 { + Pf6::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pf7 { + #[doc = "GPIO"] + GPIOF7 = 0x0, + #[doc = "Timer C PWM7"] + TCPWM7 = 0x01, + #[doc = "Timer D PWM7"] + TDPWM7 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + #[doc = "USART D MISO/RX"] + USDMISO = 0x05, + #[doc = "CAN TX Data"] + CANTXD = 0x06, + #[doc = "I2C SDA"] + I2CSDA = 0x07, +} +impl Pf7 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pf7 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pf7 { + #[inline(always)] + fn from(val: u8) -> Pf7 { + Pf7::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pf7) -> u8 { + Pf7::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pg0 { + #[doc = "GPIO"] + GPIOG0 = 0x0, + #[doc = "Timer C PWM0"] + TCPWM0 = 0x01, + #[doc = "Timer D PWM0"] + TDPWM0 = 0x02, + #[doc = "EMUX Clock"] + EMUXC = 0x03, + _RESERVED_4 = 0x04, + #[doc = "USART D SPI Clock"] + USDSCLK = 0x05, + #[doc = "Trace Clock"] + TRACECLK = 0x06, + #[doc = "Timer C QEP Index"] + TCQEPIDX = 0x07, +} +impl Pg0 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pg0 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pg0 { + #[inline(always)] + fn from(val: u8) -> Pg0 { + Pg0::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pg0) -> u8 { + Pg0::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pg1 { + #[doc = "GPIO"] + GPIOG1 = 0x0, + #[doc = "Timer C PWM1"] + TCPWM1 = 0x01, + #[doc = "Timer D PWM1"] + TDPWM1 = 0x02, + #[doc = "EMUX Data"] + EMUXD = 0x03, + _RESERVED_4 = 0x04, + #[doc = "USART D Slave Select"] + USDSS = 0x05, + #[doc = "Trace Data 0 output"] + TRACED0 = 0x06, + #[doc = "Timer C QEP Phase A"] + TCQEPPHA = 0x07, +} +impl Pg1 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pg1 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pg1 { + #[inline(always)] + fn from(val: u8) -> Pg1 { + Pg1::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pg1) -> u8 { + Pg1::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pg2 { + #[doc = "GPIO"] + GPIOG2 = 0x0, + #[doc = "Timer C PWM2"] + TCPWM2 = 0x01, + #[doc = "Timer D PWM2"] + TDPWM2 = 0x02, + #[doc = "FRCLK Output"] + FRCLK = 0x03, + _RESERVED_4 = 0x04, + #[doc = "USART D MOSI/TX"] + USDMOSI = 0x05, + #[doc = "Trace Data 1 output"] + TRACED1 = 0x06, + #[doc = "Timer C QEP Phase B"] + TCQEPPHB = 0x07, +} +impl Pg2 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pg2 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pg2 { + #[inline(always)] + fn from(val: u8) -> Pg2 { + Pg2::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pg2) -> u8 { + Pg2::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pg3 { + #[doc = "GPIO"] + GPIOG3 = 0x0, + #[doc = "Timer C PWM3"] + TCPWM3 = 0x01, + #[doc = "Timer D PWM3"] + TDPWM3 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + #[doc = "USART D MISO/RX"] + USDMISO = 0x05, + #[doc = "Trace Data 2 output"] + TRACED2 = 0x06, + _RESERVED_7 = 0x07, +} +impl Pg3 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pg3 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pg3 { + #[inline(always)] + fn from(val: u8) -> Pg3 { + Pg3::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pg3) -> u8 { + Pg3::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pg4 { + #[doc = "GPIO"] + GPIOG4 = 0x0, + #[doc = "Timer C PWM4"] + TCPWM4 = 0x01, + #[doc = "Timer D PWM4"] + TDPWM4 = 0x02, + #[doc = "EMUX Data"] + EMUXD = 0x03, + #[doc = "I2C SCL"] + I2CSCL = 0x04, + #[doc = "USART D Slave Select"] + USDSS = 0x05, + #[doc = "Trace Data 3 output"] + TRACED3 = 0x06, + #[doc = "Timer D QEP Index"] + TDQEPIDX = 0x07, +} +impl Pg4 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pg4 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pg4 { + #[inline(always)] + fn from(val: u8) -> Pg4 { + Pg4::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pg4) -> u8 { + Pg4::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pg5 { + #[doc = "GPIO"] + GPIOG5 = 0x0, + #[doc = "Timer C PWM5"] + TCPWM5 = 0x01, + #[doc = "Timer D PWM5"] + TDPWM5 = 0x02, + #[doc = "EMUX Clock"] + EMUXC = 0x03, + _RESERVED_4 = 0x04, + #[doc = "USART D MOSI/TX"] + USDMOSI = 0x05, + #[doc = "CAN RX Data"] + CANRXD = 0x06, + #[doc = "Timer D QEP Phase A"] + TDQEPPHA = 0x07, +} +impl Pg5 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pg5 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pg5 { + #[inline(always)] + fn from(val: u8) -> Pg5 { + Pg5::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pg5) -> u8 { + Pg5::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pg6 { + #[doc = "GPIO"] + GPIOG6 = 0x0, + #[doc = "Timer C PWM6"] + TCPWM6 = 0x01, + #[doc = "Timer D PWM6"] + TDPWM6 = 0x02, + #[doc = "I2C SDA"] + I2CSDA = 0x03, + _RESERVED_4 = 0x04, + #[doc = "USART D MISO/RX"] + USDMISO = 0x05, + #[doc = "CAN TX Data"] + CANTXD = 0x06, + #[doc = "Timer D QEP Phase B"] + TDQEPPHB = 0x07, +} +impl Pg6 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pg6 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pg6 { + #[inline(always)] + fn from(val: u8) -> Pg6 { + Pg6::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pg6) -> u8 { + Pg6::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Pg7 { + #[doc = "GPIO"] + GPIOG7 = 0x0, + _RESERVED_1 = 0x01, + #[doc = "Timer D QEP Index"] + TDQEPIDX = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + #[doc = "USART D SPI Clock"] + USDSCLK = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl Pg7 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pg7 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pg7 { + #[inline(always)] + fn from(val: u8) -> Pg7 { + Pg7::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pg7) -> u8 { + Pg7::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Plloutdiv { + #[doc = "/1"] + DIV1 = 0x0, + #[doc = "/2"] + DIV2 = 0x01, + #[doc = "/4"] + DIV4 = 0x02, + #[doc = "/8"] + DIV8 = 0x03, +} +impl Plloutdiv { + #[inline(always)] + pub const fn from_bits(val: u8) -> Plloutdiv { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Plloutdiv { + #[inline(always)] + fn from(val: u8) -> Plloutdiv { + Plloutdiv::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Plloutdiv) -> u8 { + Plloutdiv::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Sclkmuxsel { + #[doc = "FRCLK selected as input to SCLK"] + FRCLK = 0x0, + #[doc = "PLLCLK selected as input to SCLK"] + PLLCLK = 0x01, +} +impl Sclkmuxsel { + #[inline(always)] + pub const fn from_bits(val: u8) -> Sclkmuxsel { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Sclkmuxsel { + #[inline(always)] + fn from(val: u8) -> Sclkmuxsel { + Sclkmuxsel::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Sclkmuxsel) -> u8 { + Sclkmuxsel::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Usmode { + #[doc = "SSP Mode"] + SSP = 0x0, + #[doc = "UART Mode"] + UART = 0x01, +} +impl Usmode { + #[inline(always)] + pub const fn from_bits(val: u8) -> Usmode { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Usmode { + #[inline(always)] + fn from(val: u8) -> Usmode { + Usmode::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Usmode) -> u8 { + Usmode::to_bits(val) + } +} diff --git a/src/ssp.rs b/src/ssp.rs new file mode 100644 index 0000000..c295989 --- /dev/null +++ b/src/ssp.rs @@ -0,0 +1,64 @@ +#[doc = "Synchronous Serial Peripheral"] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Ssp { + ptr: *mut u8, +} +unsafe impl Send for Ssp {} +unsafe impl Sync for Ssp {} +impl Ssp { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "SSP Control Register"] + #[inline(always)] + pub const fn con(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "SSP Status Register"] + #[inline(always)] + pub const fn stat(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } + #[doc = "SSP Data Register"] + #[inline(always)] + pub const fn dat(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } + } + #[doc = "SSP Clock Register"] + #[inline(always)] + pub const fn clk(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } + #[doc = "SSP Interrupt Mask Set/Clear Register"] + #[inline(always)] + pub const fn imsc(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } + } + #[doc = "SSP Raw Interrupt Status Register"] + #[inline(always)] + pub const fn ris(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } + } + #[doc = "SSP Masked Interrupt Status Register"] + #[inline(always)] + pub const fn mis(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } + } + #[doc = "SSP Interrupt Clear Register"] + #[inline(always)] + pub const fn clr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } + } + #[doc = "SSP Slave Select Control Register"] + #[inline(always)] + pub const fn sscr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } + } +} +pub mod regs; +pub mod vals; diff --git a/src/ssp/regs.rs b/src/ssp/regs.rs new file mode 100644 index 0000000..afcdbac --- /dev/null +++ b/src/ssp/regs.rs @@ -0,0 +1,493 @@ +#[doc = "SSP Clock Register"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Clk(pub u32); +impl Clk { + #[doc = "N Value"] + #[inline(always)] + pub const fn n(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "N Value"] + #[inline(always)] + pub fn set_n(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "M Value"] + #[inline(always)] + pub const fn m(&self) -> u8 { + let val = (self.0 >> 8usize) & 0xff; + val as u8 + } + #[doc = "M Value"] + #[inline(always)] + pub fn set_m(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); + } +} +impl Default for Clk { + #[inline(always)] + fn default() -> Clk { + Clk(0) + } +} +#[doc = "SSP Interrupt Clear Register"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Clr(pub u32); +impl Clr { + #[doc = "Receive FIFO Overrun Interrupt Clear"] + #[inline(always)] + pub const fn roic(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Receive FIFO Overrun Interrupt Clear"] + #[inline(always)] + pub fn set_roic(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Receive FIFO Timeout Interrupt Clear"] + #[inline(always)] + pub const fn rtic(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Receive FIFO Timeout Interrupt Clear"] + #[inline(always)] + pub fn set_rtic(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } +} +impl Default for Clr { + #[inline(always)] + fn default() -> Clr { + Clr(0) + } +} +#[doc = "SSP Control Register"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Con(pub u32); +impl Con { + #[doc = "Data Size Select"] + #[inline(always)] + pub const fn dss(&self) -> super::vals::Dss { + let val = (self.0 >> 0usize) & 0x1f; + super::vals::Dss::from_bits(val as u8) + } + #[doc = "Data Size Select"] + #[inline(always)] + pub fn set_dss(&mut self, val: super::vals::Dss) { + self.0 = (self.0 & !(0x1f << 0usize)) | (((val.to_bits() as u32) & 0x1f) << 0usize); + } + #[doc = "Frame Format"] + #[inline(always)] + pub const fn frf(&self) -> super::vals::Frf { + let val = (self.0 >> 5usize) & 0x03; + super::vals::Frf::from_bits(val as u8) + } + #[doc = "Frame Format"] + #[inline(always)] + pub fn set_frf(&mut self, val: super::vals::Frf) { + self.0 = (self.0 & !(0x03 << 5usize)) | (((val.to_bits() as u32) & 0x03) << 5usize); + } + #[doc = "Clock Out Polarity"] + #[inline(always)] + pub const fn cpo(&self) -> super::vals::Cpo { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Cpo::from_bits(val as u8) + } + #[doc = "Clock Out Polarity"] + #[inline(always)] + pub fn set_cpo(&mut self, val: super::vals::Cpo) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize); + } + #[doc = "Clock Phase"] + #[inline(always)] + pub const fn cph(&self) -> super::vals::Cph { + let val = (self.0 >> 8usize) & 0x01; + super::vals::Cph::from_bits(val as u8) + } + #[doc = "Clock Phase"] + #[inline(always)] + pub fn set_cph(&mut self, val: super::vals::Cph) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize); + } + #[doc = "Slave Output Disable"] + #[inline(always)] + pub const fn sod(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Slave Output Disable"] + #[inline(always)] + pub fn set_sod(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Master/Slave Mode"] + #[inline(always)] + pub const fn ms(&self) -> super::vals::Ms { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Ms::from_bits(val as u8) + } + #[doc = "Master/Slave Mode"] + #[inline(always)] + pub fn set_ms(&mut self, val: super::vals::Ms) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.to_bits() as u32) & 0x01) << 10usize); + } + #[doc = "SSP Enable"] + #[inline(always)] + pub const fn sspen(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "SSP Enable"] + #[inline(always)] + pub fn set_sspen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Loopback Mode"] + #[inline(always)] + pub const fn lbm(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Loopback Mode"] + #[inline(always)] + pub fn set_lbm(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "LSB First"] + #[inline(always)] + pub const fn lsbfirst(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "LSB First"] + #[inline(always)] + pub fn set_lsbfirst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } +} +impl Default for Con { + #[inline(always)] + fn default() -> Con { + Con(0) + } +} +#[doc = "SSP Data Register"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Dat(pub u32); +impl Dat { + #[doc = "Data"] + #[inline(always)] + pub const fn data(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Data"] + #[inline(always)] + pub fn set_data(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for Dat { + #[inline(always)] + fn default() -> Dat { + Dat(0) + } +} +#[doc = "SSP Interrupt Mask Set/Clear Register"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Imsc(pub u32); +impl Imsc { + #[doc = "Receive Overrun Interrupt Mask"] + #[inline(always)] + pub const fn rorim(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Receive Overrun Interrupt Mask"] + #[inline(always)] + pub fn set_rorim(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Receive Timeout Interrupt Mask"] + #[inline(always)] + pub const fn rtim(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Receive Timeout Interrupt Mask"] + #[inline(always)] + pub fn set_rtim(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Receive FIFO Interrupt Mask"] + #[inline(always)] + pub const fn rxim(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Receive FIFO Interrupt Mask"] + #[inline(always)] + pub fn set_rxim(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Transmit FIFO Interrupt Mask"] + #[inline(always)] + pub const fn txim(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Transmit FIFO Interrupt Mask"] + #[inline(always)] + pub fn set_txim(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } +} +impl Default for Imsc { + #[inline(always)] + fn default() -> Imsc { + Imsc(0) + } +} +#[doc = "SSP Masked Interrupt Status Register"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Mis(pub u32); +impl Mis { + #[doc = "Receive Overrun Masked Interrupt Status"] + #[inline(always)] + pub const fn rormis(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Receive Overrun Masked Interrupt Status"] + #[inline(always)] + pub fn set_rormis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Receive Timeout Masked Interrupt Status"] + #[inline(always)] + pub const fn rtmis(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Receive Timeout Masked Interrupt Status"] + #[inline(always)] + pub fn set_rtmis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Receive FIFO Masked Interrupt Status"] + #[inline(always)] + pub const fn rxmis(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Receive FIFO Masked Interrupt Status"] + #[inline(always)] + pub fn set_rxmis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Transmit FIFO Masked Interrupt Status"] + #[inline(always)] + pub const fn txmis(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Transmit FIFO Masked Interrupt Status"] + #[inline(always)] + pub fn set_txmis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } +} +impl Default for Mis { + #[inline(always)] + fn default() -> Mis { + Mis(0) + } +} +#[doc = "SSP Raw Interrupt Status Register"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Ris(pub u32); +impl Ris { + #[doc = "Receive Overrun Raw Interrupt Status"] + #[inline(always)] + pub const fn rorris(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Receive Overrun Raw Interrupt Status"] + #[inline(always)] + pub fn set_rorris(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Receive Timeout Raw Interrupt Status"] + #[inline(always)] + pub const fn rtris(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Receive Timeout Raw Interrupt Status"] + #[inline(always)] + pub fn set_rtris(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Receive FIFO Raw Interrupt Status"] + #[inline(always)] + pub const fn rxris(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Receive FIFO Raw Interrupt Status"] + #[inline(always)] + pub fn set_rxris(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Transmit FIFO Raw Interrupt Status"] + #[inline(always)] + pub const fn txris(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Transmit FIFO Raw Interrupt Status"] + #[inline(always)] + pub fn set_txris(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } +} +impl Default for Ris { + #[inline(always)] + fn default() -> Ris { + Ris(0) + } +} +#[doc = "SSP Slave Select Control Register"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Sscr(pub u32); +impl Sscr { + #[doc = "Slave Select"] + #[inline(always)] + pub const fn selss(&self) -> super::vals::Selss { + let val = (self.0 >> 0usize) & 0x03; + super::vals::Selss::from_bits(val as u8) + } + #[doc = "Slave Select"] + #[inline(always)] + pub fn set_selss(&mut self, val: super::vals::Selss) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + #[doc = "Slave Select Software Control"] + #[inline(always)] + pub const fn swsel(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Slave Select Software Control"] + #[inline(always)] + pub fn set_swsel(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Slave Select State"] + #[inline(always)] + pub const fn swss(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Slave Select State"] + #[inline(always)] + pub fn set_swss(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Slave Select Pull-high"] + #[inline(always)] + pub const fn sphdontcare(&self) -> super::vals::Sphdontcare { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Sphdontcare::from_bits(val as u8) + } + #[doc = "Slave Select Pull-high"] + #[inline(always)] + pub fn set_sphdontcare(&mut self, val: super::vals::Sphdontcare) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize); + } +} +impl Default for Sscr { + #[inline(always)] + fn default() -> Sscr { + Sscr(0) + } +} +#[doc = "SSP Status Register"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Stat(pub u32); +impl Stat { + #[doc = "Transmit FIFO Empty"] + #[inline(always)] + pub const fn tfe(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Transmit FIFO Empty"] + #[inline(always)] + pub fn set_tfe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Transmit FIFO Not Full"] + #[inline(always)] + pub const fn tnf(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Transmit FIFO Not Full"] + #[inline(always)] + pub fn set_tnf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Receive FIFO Not Empty"] + #[inline(always)] + pub const fn rne(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Receive FIFO Not Empty"] + #[inline(always)] + pub fn set_rne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Receive FIFO Full"] + #[inline(always)] + pub const fn rff(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Receive FIFO Full"] + #[inline(always)] + pub fn set_rff(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Busy"] + #[inline(always)] + pub const fn bsy(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Busy"] + #[inline(always)] + pub fn set_bsy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } +} +impl Default for Stat { + #[inline(always)] + fn default() -> Stat { + Stat(0) + } +} diff --git a/src/ssp/vals.rs b/src/ssp/vals.rs new file mode 100644 index 0000000..66f1f3a --- /dev/null +++ b/src/ssp/vals.rs @@ -0,0 +1,271 @@ +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Cph { + #[doc = "First edge"] + FIRST_EDGE = 0x0, + #[doc = "Second edge"] + SECOND_EDGE = 0x01, +} +impl Cph { + #[inline(always)] + pub const fn from_bits(val: u8) -> Cph { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Cph { + #[inline(always)] + fn from(val: u8) -> Cph { + Cph::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Cph) -> u8 { + Cph::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Cpo { + #[doc = "Active High"] + ACTIVE_HIGH = 0x0, + #[doc = "Active Low"] + ACTIVE_LOW = 0x01, +} +impl Cpo { + #[inline(always)] + pub const fn from_bits(val: u8) -> Cpo { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Cpo { + #[inline(always)] + fn from(val: u8) -> Cpo { + Cpo::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Cpo) -> u8 { + Cpo::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Dss { + _RESERVED_0 = 0x0, + _RESERVED_1 = 0x01, + _RESERVED_2 = 0x02, + #[doc = "4-bit transfer"] + BITS4 = 0x03, + #[doc = "5-bit transfer"] + BITS5 = 0x04, + #[doc = "6-bit transfer"] + BITS6 = 0x05, + #[doc = "7-bit transfer"] + BITS7 = 0x06, + #[doc = "8-bit transfer"] + BITS8 = 0x07, + #[doc = "9-bit transfer"] + BITS9 = 0x08, + #[doc = "10-bit transfer"] + BITS10 = 0x09, + #[doc = "11-bit transfer"] + BITS11 = 0x0a, + #[doc = "12-bit transfer"] + BITS12 = 0x0b, + #[doc = "13-bit transfer"] + BITS13 = 0x0c, + #[doc = "14-bit transfer"] + BITS14 = 0x0d, + #[doc = "15-bit transfer"] + BITS15 = 0x0e, + #[doc = "16-bit transfer"] + BITS16 = 0x0f, + #[doc = "17-bit transfer"] + BITS17 = 0x10, + #[doc = "18-bit transfer"] + BITS18 = 0x11, + #[doc = "19-bit transfer"] + BITS19 = 0x12, + #[doc = "20-bit transfer"] + BITS20 = 0x13, + #[doc = "21-bit transfer"] + BITS21 = 0x14, + #[doc = "22-bit transfer"] + BITS22 = 0x15, + #[doc = "23-bit transfer"] + BITS23 = 0x16, + #[doc = "24-bit transfer"] + BITS24 = 0x17, + #[doc = "25-bit transfer"] + BITS25 = 0x18, + #[doc = "26-bit transfer"] + BITS26 = 0x19, + #[doc = "27-bit transfer"] + BITS27 = 0x1a, + #[doc = "28-bit transfer"] + BITS28 = 0x1b, + #[doc = "29-bit transfer"] + BITS29 = 0x1c, + #[doc = "30-bit transfer"] + BITS30 = 0x1d, + #[doc = "31-bit transfer"] + BITS31 = 0x1e, + #[doc = "32-bit transfer"] + BITS32 = 0x1f, +} +impl Dss { + #[inline(always)] + pub const fn from_bits(val: u8) -> Dss { + unsafe { core::mem::transmute(val & 0x1f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Dss { + #[inline(always)] + fn from(val: u8) -> Dss { + Dss::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Dss) -> u8 { + Dss::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Frf { + #[doc = "SPI (Motorola)"] + SPI = 0x0, + #[doc = "Synchronous Serial Format (TI)"] + TI = 0x01, + #[doc = "Microwire (National Semiconductor)"] + MICROWIRE = 0x02, + _RESERVED_3 = 0x03, +} +impl Frf { + #[inline(always)] + pub const fn from_bits(val: u8) -> Frf { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Frf { + #[inline(always)] + fn from(val: u8) -> Frf { + Frf::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Frf) -> u8 { + Frf::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Ms { + #[doc = "Master"] + MASTER = 0x0, + #[doc = "Slave"] + SLAVE = 0x01, +} +impl Ms { + #[inline(always)] + pub const fn from_bits(val: u8) -> Ms { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Ms { + #[inline(always)] + fn from(val: u8) -> Ms { + Ms::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Ms) -> u8 { + Ms::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Selss { + #[doc = "Slave Select Enabled"] + SS_ENABLED = 0x0, + _RESERVED_1 = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, +} +impl Selss { + #[inline(always)] + pub const fn from_bits(val: u8) -> Selss { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Selss { + #[inline(always)] + fn from(val: u8) -> Selss { + Selss::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Selss) -> u8 { + Selss::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Sphdontcare { + #[doc = "SS cannot be pulled high after transfer"] + NO_PULL_HIGH = 0x0, + #[doc = "SS must be pulled high after transfer"] + PULL_HIGH = 0x01, +} +impl Sphdontcare { + #[inline(always)] + pub const fn from_bits(val: u8) -> Sphdontcare { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Sphdontcare { + #[inline(always)] + fn from(val: u8) -> Sphdontcare { + Sphdontcare::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Sphdontcare) -> u8 { + Sphdontcare::to_bits(val) + } +} diff --git a/src/timer.rs b/src/timer.rs new file mode 100644 index 0000000..e551ad4 --- /dev/null +++ b/src/timer.rs @@ -0,0 +1,82 @@ +#[doc = "Timer"] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Timer { + ptr: *mut u8, +} +unsafe impl Send for Timer {} +unsafe impl Sync for Timer {} +impl Timer { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Timer Control"] + #[inline(always)] + pub const fn ctl(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "Timer Interrupt Control"] + #[inline(always)] + pub const fn int(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } + #[doc = "Timer Period"] + #[inline(always)] + pub const fn prd(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } + } + #[doc = "Timer Counter"] + #[inline(always)] + pub const fn ctr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } + #[doc = "Timer CCR Control"] + #[inline(always)] + pub const fn cctl(self, n: usize) -> crate::common::Reg { + assert!(n < 8usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize + n * 8usize) as _) } + } + #[doc = "Timer CCR Counter"] + #[inline(always)] + pub const fn cctr(self, n: usize) -> crate::common::Reg { + assert!(n < 8usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0104usize + n * 8usize) as _) } + } + #[doc = "Timer Dead-Time Generator Control"] + #[inline(always)] + pub const fn dtgctl(self, n: usize) -> crate::common::Reg { + assert!(n < 4usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize + n * 4usize) as _) } + } + #[doc = "Timer QEP Control"] + #[inline(always)] + pub const fn qepctl(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0300usize) as _) } + } + #[doc = "Timer QEP Counter"] + #[inline(always)] + pub const fn qepctr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0304usize) as _) } + } + #[doc = "Timer QEP Maximum Counter"] + #[inline(always)] + pub const fn qepmax(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0308usize) as _) } + } + #[doc = "Timer QEP Interrupt Enable"] + #[inline(always)] + pub const fn qepier(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x030cusize) as _) } + } + #[doc = "Timer QEP Interrupt Enable"] + #[inline(always)] + pub const fn qepif(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0310usize) as _) } + } +} +pub mod regs; +pub mod vals; diff --git a/src/timer/regs.rs b/src/timer/regs.rs new file mode 100644 index 0000000..bfe6736 --- /dev/null +++ b/src/timer/regs.rs @@ -0,0 +1,632 @@ +#[doc = "Timer CCR Control"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Cctl(pub u32); +impl Cctl { + #[doc = "CCR Mode"] + #[inline(always)] + pub const fn ccmode(&self) -> super::vals::CctlCcmode { + let val = (self.0 >> 0usize) & 0x01; + super::vals::CctlCcmode::from_bits(val as u8) + } + #[doc = "CCR Mode"] + #[inline(always)] + pub fn set_ccmode(&mut self, val: super::vals::CctlCcmode) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + #[doc = "CCR Interrupt Enable"] + #[inline(always)] + pub const fn ccinten(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "CCR Interrupt Enable"] + #[inline(always)] + pub fn set_ccinten(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Capture Mode Interrupt Edge Setting"] + #[inline(always)] + pub const fn ccintedge(&self) -> super::vals::CctlCcintedge { + let val = (self.0 >> 2usize) & 0x03; + super::vals::CctlCcintedge::from_bits(val as u8) + } + #[doc = "Capture Mode Interrupt Edge Setting"] + #[inline(always)] + pub fn set_ccintedge(&mut self, val: super::vals::CctlCcintedge) { + self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); + } + #[doc = "Invert CCR Output"] + #[inline(always)] + pub const fn ccoutinv(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Invert CCR Output"] + #[inline(always)] + pub fn set_ccoutinv(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "CCR Register Latch Mode"] + #[inline(always)] + pub const fn cclatch(&self) -> super::vals::CctlCclatch { + let val = (self.0 >> 5usize) & 0x03; + super::vals::CctlCclatch::from_bits(val as u8) + } + #[doc = "CCR Register Latch Mode"] + #[inline(always)] + pub fn set_cclatch(&mut self, val: super::vals::CctlCclatch) { + self.0 = (self.0 & !(0x03 << 5usize)) | (((val.to_bits() as u32) & 0x03) << 5usize); + } + #[doc = "Write 1 to force compare event (self-clearing)"] + #[inline(always)] + pub const fn ccforce(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Write 1 to force compare event (self-clearing)"] + #[inline(always)] + pub fn set_ccforce(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "CC Interrupt Skip Counter"] + #[inline(always)] + pub const fn ccintskip(&self) -> super::vals::CctlCcintskip { + let val = (self.0 >> 8usize) & 0x0f; + super::vals::CctlCcintskip::from_bits(val as u8) + } + #[doc = "CC Interrupt Skip Counter"] + #[inline(always)] + pub fn set_ccintskip(&mut self, val: super::vals::CctlCcintskip) { + self.0 = (self.0 & !(0x0f << 8usize)) | (((val.to_bits() as u32) & 0x0f) << 8usize); + } +} +impl Default for Cctl { + #[inline(always)] + fn default() -> Cctl { + Cctl(0) + } +} +#[doc = "Timer CCR Counter"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Cctr(pub u32); +impl Cctr { + #[doc = "Capture/Compare Value"] + #[inline(always)] + pub const fn ctr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Capture/Compare Value"] + #[inline(always)] + pub fn set_ctr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + #[doc = "Delay count to use before compare events"] + #[inline(always)] + pub const fn delay(&self) -> u16 { + let val = (self.0 >> 16usize) & 0xffff; + val as u16 + } + #[doc = "Delay count to use before compare events"] + #[inline(always)] + pub fn set_delay(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); + } +} +impl Default for Cctr { + #[inline(always)] + fn default() -> Cctr { + Cctr(0) + } +} +#[doc = "Timer Control"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Ctl(pub u32); +impl Ctl { + #[doc = "Timer Mode"] + #[inline(always)] + pub const fn mode(&self) -> super::vals::Mode { + let val = (self.0 >> 0usize) & 0x03; + super::vals::Mode::from_bits(val as u8) + } + #[doc = "Timer Mode"] + #[inline(always)] + pub fn set_mode(&mut self, val: super::vals::Mode) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + #[doc = "Timer Period Latch Mode"] + #[inline(always)] + pub const fn prdlatch(&self) -> super::vals::Prdlatch { + let val = (self.0 >> 2usize) & 0x03; + super::vals::Prdlatch::from_bits(val as u8) + } + #[doc = "Timer Period Latch Mode"] + #[inline(always)] + pub fn set_prdlatch(&mut self, val: super::vals::Prdlatch) { + self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); + } + #[doc = "Timer Slave Synchronization"] + #[inline(always)] + pub const fn ssync(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Timer Slave Synchronization"] + #[inline(always)] + pub fn set_ssync(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Single Shot Timer"] + #[inline(always)] + pub const fn single(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Single Shot Timer"] + #[inline(always)] + pub fn set_single(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Timer Input Clock Divider"] + #[inline(always)] + pub const fn clkdiv(&self) -> super::vals::Clkdiv { + let val = (self.0 >> 6usize) & 0x07; + super::vals::Clkdiv::from_bits(val as u8) + } + #[doc = "Timer Input Clock Divider"] + #[inline(always)] + pub fn set_clkdiv(&mut self, val: super::vals::Clkdiv) { + self.0 = (self.0 & !(0x07 << 6usize)) | (((val.to_bits() as u32) & 0x07) << 6usize); + } + #[doc = "Timer Clock Source"] + #[inline(always)] + pub const fn clksrc(&self) -> super::vals::Clksrc { + let val = (self.0 >> 9usize) & 0x01; + super::vals::Clksrc::from_bits(val as u8) + } + #[doc = "Timer Clock Source"] + #[inline(always)] + pub fn set_clksrc(&mut self, val: super::vals::Clksrc) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.to_bits() as u32) & 0x01) << 9usize); + } + #[doc = "Dead-Time Generator Clock Source"] + #[inline(always)] + pub const fn dtgclk(&self) -> super::vals::Dtgclk { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Dtgclk::from_bits(val as u8) + } + #[doc = "Dead-Time Generator Clock Source"] + #[inline(always)] + pub fn set_dtgclk(&mut self, val: super::vals::Dtgclk) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.to_bits() as u32) & 0x01) << 10usize); + } + #[doc = "Write 1 to Latch Period and all CCTRs"] + #[inline(always)] + pub const fn latch(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Write 1 to Latch Period and all CCTRs"] + #[inline(always)] + pub fn set_latch(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Timer Clear"] + #[inline(always)] + pub const fn clr(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Timer Clear"] + #[inline(always)] + pub fn set_clr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Base timer interrupt enable"] + #[inline(always)] + pub const fn baseie(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Base timer interrupt enable"] + #[inline(always)] + pub fn set_baseie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } +} +impl Default for Ctl { + #[inline(always)] + fn default() -> Ctl { + Ctl(0) + } +} +#[doc = "Timer Counter"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Ctr(pub u32); +impl Ctr { + #[doc = "Timer Counter Value"] + #[inline(always)] + pub const fn counter(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Timer Counter Value"] + #[inline(always)] + pub fn set_counter(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } +} +impl Default for Ctr { + #[inline(always)] + fn default() -> Ctr { + Ctr(0) + } +} +#[doc = "Timer Dead-Time Generator Control"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Dtgctl(pub u32); +impl Dtgctl { + #[doc = "Rising edge delay"] + #[inline(always)] + pub const fn red(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "Rising edge delay"] + #[inline(always)] + pub fn set_red(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } + #[doc = "Falling edge delay"] + #[inline(always)] + pub const fn fed(&self) -> u16 { + let val = (self.0 >> 16usize) & 0x0fff; + val as u16 + } + #[doc = "Falling edge delay"] + #[inline(always)] + pub fn set_fed(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); + } + #[doc = "Dead-time generator enable"] + #[inline(always)] + pub const fn dten(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "Dead-time generator enable"] + #[inline(always)] + pub fn set_dten(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } +} +impl Default for Dtgctl { + #[inline(always)] + fn default() -> Dtgctl { + Dtgctl(0) + } +} +#[doc = "Timer Interrupt Control"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Int(pub u32); +impl Int { + #[doc = "CCR Interrupt Flag"] + #[inline(always)] + pub const fn ccrif(&self, n: usize) -> bool { + assert!(n < 8usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "CCR Interrupt Flag"] + #[inline(always)] + pub fn set_ccrif(&mut self, n: usize, val: bool) { + assert!(n < 8usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Base Timer Interrupt Flag"] + #[inline(always)] + pub const fn baseif(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Base Timer Interrupt Flag"] + #[inline(always)] + pub fn set_baseif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } +} +impl Default for Int { + #[inline(always)] + fn default() -> Int { + Int(0) + } +} +#[doc = "Timer Period"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Prd(pub u32); +impl Prd { + #[doc = "Timer Period Value"] + #[inline(always)] + pub const fn prd(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Timer Period Value"] + #[inline(always)] + pub fn set_prd(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } +} +impl Default for Prd { + #[inline(always)] + fn default() -> Prd { + Prd(0) + } +} +#[doc = "Timer QEP Control"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Qepctl(pub u32); +impl Qepctl { + #[doc = "QEP Enable"] + #[inline(always)] + pub const fn qepen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "QEP Enable"] + #[inline(always)] + pub fn set_qepen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Count on A/B"] + #[inline(always)] + pub const fn cntab(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Count on A/B"] + #[inline(always)] + pub fn set_cntab(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Count on edge"] + #[inline(always)] + pub const fn cntedge(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Count on edge"] + #[inline(always)] + pub fn set_cntedge(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Motor direction"] + #[inline(always)] + pub const fn dir(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Motor direction"] + #[inline(always)] + pub fn set_dir(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Index reset"] + #[inline(always)] + pub const fn idxrst(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Index reset"] + #[inline(always)] + pub fn set_idxrst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "QEP input clock divider"] + #[inline(always)] + pub const fn clkdiv(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x07; + val as u8 + } + #[doc = "QEP input clock divider"] + #[inline(always)] + pub fn set_clkdiv(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 8usize)) | (((val as u32) & 0x07) << 8usize); + } +} +impl Default for Qepctl { + #[inline(always)] + fn default() -> Qepctl { + Qepctl(0) + } +} +#[doc = "Timer QEP Counter"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Qepctr(pub u32); +impl Qepctr { + #[doc = "Counter value"] + #[inline(always)] + pub const fn ctr(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Counter value"] + #[inline(always)] + pub fn set_ctr(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for Qepctr { + #[inline(always)] + fn default() -> Qepctr { + Qepctr(0) + } +} +#[doc = "Timer QEP Interrupt Enable"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Qepier(pub u32); +impl Qepier { + #[doc = "Direction change interrupt enable"] + #[inline(always)] + pub const fn dirie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Direction change interrupt enable"] + #[inline(always)] + pub fn set_dirie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Phase A rising edge interrupt enable"] + #[inline(always)] + pub const fn phaie(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Phase A rising edge interrupt enable"] + #[inline(always)] + pub fn set_phaie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Phase B rising edge interrupt enable"] + #[inline(always)] + pub const fn phbie(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Phase B rising edge interrupt enable"] + #[inline(always)] + pub fn set_phbie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Counter wrap interrupt enable"] + #[inline(always)] + pub const fn wrie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Counter wrap interrupt enable"] + #[inline(always)] + pub fn set_wrie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Index event interrupt enable"] + #[inline(always)] + pub const fn idxevie(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Index event interrupt enable"] + #[inline(always)] + pub fn set_idxevie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } +} +impl Default for Qepier { + #[inline(always)] + fn default() -> Qepier { + Qepier(0) + } +} +#[doc = "Timer QEP Interrupt Enable"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Qepif(pub u32); +impl Qepif { + #[doc = "Direction change interrupt flag"] + #[inline(always)] + pub const fn dirif(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Direction change interrupt flag"] + #[inline(always)] + pub fn set_dirif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Phase A rising edge interrupt flag"] + #[inline(always)] + pub const fn phaif(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Phase A rising edge interrupt flag"] + #[inline(always)] + pub fn set_phaif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Phase B rising edge interrupt flag"] + #[inline(always)] + pub const fn phbif(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Phase B rising edge interrupt flag"] + #[inline(always)] + pub fn set_phbif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Counter wrap interrupt flag"] + #[inline(always)] + pub const fn wrif(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Counter wrap interrupt flag"] + #[inline(always)] + pub fn set_wrif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Index event interrupt flag"] + #[inline(always)] + pub const fn idxevif(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Index event interrupt flag"] + #[inline(always)] + pub fn set_idxevif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } +} +impl Default for Qepif { + #[inline(always)] + fn default() -> Qepif { + Qepif(0) + } +} +#[doc = "Timer QEP Maximum Counter"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Qepmax(pub u32); +impl Qepmax { + #[doc = "Maximum Counter value"] + #[inline(always)] + pub const fn ctrmax(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Maximum Counter value"] + #[inline(always)] + pub fn set_ctrmax(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for Qepmax { + #[inline(always)] + fn default() -> Qepmax { + Qepmax(0) + } +} diff --git a/src/timer/vals.rs b/src/timer/vals.rs new file mode 100644 index 0000000..ecb32c2 --- /dev/null +++ b/src/timer/vals.rs @@ -0,0 +1,323 @@ +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum CctlCcintedge { + #[doc = "Rising Edge Interrupt"] + RISING = 0x0, + #[doc = "Falling Edge Interrupt"] + FALLING = 0x01, + #[doc = "Rising and Falling Edge Interrupt"] + BOTH = 0x02, + _RESERVED_3 = 0x03, +} +impl CctlCcintedge { + #[inline(always)] + pub const fn from_bits(val: u8) -> CctlCcintedge { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for CctlCcintedge { + #[inline(always)] + fn from(val: u8) -> CctlCcintedge { + CctlCcintedge::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: CctlCcintedge) -> u8 { + CctlCcintedge::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum CctlCcintskip { + #[doc = "Don't skip CCR matches before interrupt"] + NONE = 0x0, + #[doc = "Skip 1 CCR match before interrupt"] + SKIP1 = 0x01, + #[doc = "Skip 2 CCR matches before interrupt"] + SKIP2 = 0x02, + #[doc = "Skip 3 CCR matches before interrupt"] + SKIP3 = 0x03, + #[doc = "Skip 4 CCR matches before interrupt"] + SKIP4 = 0x04, + #[doc = "Skip 5 CCR matches before interrupt"] + SKIP5 = 0x05, + #[doc = "Skip 6 CCR matches before interrupt"] + SKIP6 = 0x06, + #[doc = "Skip 7 CCR matches before interrupt"] + SKIP7 = 0x07, + #[doc = "Skip 8 CCR matches before interrupt"] + SKIP8 = 0x08, + #[doc = "Skip 9 CCR matches before interrupt"] + SKIP9 = 0x09, + #[doc = "Skip 10 CCR matches before interrupt"] + SKIP10 = 0x0a, + #[doc = "Skip 11 CCR matches before interrupt"] + SKIP11 = 0x0b, + #[doc = "Skip 12 CCR matches before interrupt"] + SKIP12 = 0x0c, + #[doc = "Skip 13 CCR matches before interrupt"] + SKIP13 = 0x0d, + #[doc = "Skip 14 CCR matches before interrupt"] + SKIP14 = 0x0e, + #[doc = "Skip 15 CCR matches before interrupt"] + SKIP15 = 0x0f, +} +impl CctlCcintskip { + #[inline(always)] + pub const fn from_bits(val: u8) -> CctlCcintskip { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for CctlCcintskip { + #[inline(always)] + fn from(val: u8) -> CctlCcintskip { + CctlCcintskip::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: CctlCcintskip) -> u8 { + CctlCcintskip::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum CctlCclatch { + #[doc = "Compare(latch on CTR=0)/ Capture(latch on rising edge)"] + CTR_ZERO_OR_RISING_EDGE = 0x0, + #[doc = "Compare(latch on CTR=Period)/ Capture(latch on falling edge)"] + CTR_PERIOD_OR_FALLING_EDGE = 0x01, + #[doc = "Compare(latch immediately)/ Capture(latch on both edges)"] + IMMEDIATE_OR_BOTH_EDGES = 0x02, + _RESERVED_3 = 0x03, +} +impl CctlCclatch { + #[inline(always)] + pub const fn from_bits(val: u8) -> CctlCclatch { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for CctlCclatch { + #[inline(always)] + fn from(val: u8) -> CctlCclatch { + CctlCclatch::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: CctlCclatch) -> u8 { + CctlCclatch::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum CctlCcmode { + #[doc = "Compare Mode"] + COMPARE = 0x0, + #[doc = "Capture Mode"] + CAPTURE = 0x01, +} +impl CctlCcmode { + #[inline(always)] + pub const fn from_bits(val: u8) -> CctlCcmode { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for CctlCcmode { + #[inline(always)] + fn from(val: u8) -> CctlCcmode { + CctlCcmode::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: CctlCcmode) -> u8 { + CctlCcmode::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Clkdiv { + #[doc = "Timer input clock /1"] + DIV1 = 0x0, + #[doc = "Timer input clock /2"] + DIV2 = 0x01, + #[doc = "Timer input clock /4"] + DIV4 = 0x02, + #[doc = "Timer input clock /8"] + DIV8 = 0x03, + #[doc = "Timer input clock /16"] + DIV16 = 0x04, + #[doc = "Timer input clock /32"] + DIV32 = 0x05, + #[doc = "Timer input clock /64"] + DIV64 = 0x06, + #[doc = "Timer input clock /128"] + DIV128 = 0x07, +} +impl Clkdiv { + #[inline(always)] + pub const fn from_bits(val: u8) -> Clkdiv { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Clkdiv { + #[inline(always)] + fn from(val: u8) -> Clkdiv { + Clkdiv::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Clkdiv) -> u8 { + Clkdiv::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Clksrc { + #[doc = "PCLK selected as input to timer"] + PCLK = 0x0, + #[doc = "ACLK selected as input to timer"] + ACLK = 0x01, +} +impl Clksrc { + #[inline(always)] + pub const fn from_bits(val: u8) -> Clksrc { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Clksrc { + #[inline(always)] + fn from(val: u8) -> Clksrc { + Clksrc::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Clksrc) -> u8 { + Clksrc::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Dtgclk { + #[doc = "Before input clock divider"] + BEFORE_DIV = 0x0, + #[doc = "After input clock divider"] + AFTER_DIV = 0x01, +} +impl Dtgclk { + #[inline(always)] + pub const fn from_bits(val: u8) -> Dtgclk { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Dtgclk { + #[inline(always)] + fn from(val: u8) -> Dtgclk { + Dtgclk::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Dtgclk) -> u8 { + Dtgclk::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Mode { + #[doc = "Disabled"] + DISABLED = 0x0, + #[doc = "Up mode"] + UP = 0x01, + #[doc = "Up/Down mode"] + UP_DOWN = 0x02, + #[doc = "Asymmetric mode"] + ASYMMETRIC = 0x03, +} +impl Mode { + #[inline(always)] + pub const fn from_bits(val: u8) -> Mode { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Mode { + #[inline(always)] + fn from(val: u8) -> Mode { + Mode::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Mode) -> u8 { + Mode::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Prdlatch { + #[doc = "Period is latched when CTR = 0"] + CTR_0 = 0x0, + #[doc = "Period is latched when CTR = Period (PRD)"] + CTR_PERIOD = 0x01, + #[doc = "Period is latched immediately upon register write"] + IMMEDIATE = 0x02, + _RESERVED_3 = 0x03, +} +impl Prdlatch { + #[inline(always)] + pub const fn from_bits(val: u8) -> Prdlatch { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Prdlatch { + #[inline(always)] + fn from(val: u8) -> Prdlatch { + Prdlatch::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Prdlatch) -> u8 { + Prdlatch::to_bits(val) + } +} diff --git a/src/usart.rs b/src/usart.rs new file mode 100644 index 0000000..cd47635 --- /dev/null +++ b/src/usart.rs @@ -0,0 +1,69 @@ +#[doc = "Universal Synchronous Asynchronous Receive Transmit"] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Usart { + ptr: *mut u8, +} +unsafe impl Send for Usart {} +unsafe impl Sync for Usart {} +impl Usart { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "UART A Receive Buffer"] + #[inline(always)] + pub const fn rbr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "UART A Transmit Holding"] + #[inline(always)] + pub const fn thr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } + #[doc = "UART A Divisor Latch"] + #[inline(always)] + pub const fn dlr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } + } + #[doc = "UART A Interrupt Enable"] + #[inline(always)] + pub const fn ier(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } + #[doc = "UART A Interrupt Identification"] + #[inline(always)] + pub const fn iir(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } + } + #[doc = "UART A FIFO Control"] + #[inline(always)] + pub const fn fcr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } + } + #[doc = "UART A Line Control"] + #[inline(always)] + pub const fn lcr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } + } + #[doc = "UART A Line Status"] + #[inline(always)] + pub const fn lsr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } + } + #[doc = "UART A Scratch Pad"] + #[inline(always)] + pub const fn scr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } + } + #[doc = "Enhanced Feature"] + #[inline(always)] + pub const fn efr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } + } +} +pub mod regs; +pub mod vals; diff --git a/src/usart/regs.rs b/src/usart/regs.rs new file mode 100644 index 0000000..3c58681 --- /dev/null +++ b/src/usart/regs.rs @@ -0,0 +1,428 @@ +#[doc = "UART A Divisor Latch"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Dlr(pub u32); +impl Dlr { + #[doc = "Divisor Latch Register (Baudrate = PCLK / (16 * DLR))"] + #[inline(always)] + pub const fn dlr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Divisor Latch Register (Baudrate = PCLK / (16 * DLR))"] + #[inline(always)] + pub fn set_dlr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } +} +impl Default for Dlr { + #[inline(always)] + fn default() -> Dlr { + Dlr(0) + } +} +#[doc = "Enhanced Feature"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Efr(pub u32); +impl Efr { + #[doc = "Enable Enhanced Mode"] + #[inline(always)] + pub const fn erfen(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Enable Enhanced Mode"] + #[inline(always)] + pub fn set_erfen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } +} +impl Default for Efr { + #[inline(always)] + fn default() -> Efr { + Efr(0) + } +} +#[doc = "UART A FIFO Control"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Fcr(pub u32); +impl Fcr { + #[doc = "FIFO Enable"] + #[inline(always)] + pub const fn fifoen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "FIFO Enable"] + #[inline(always)] + pub fn set_fifoen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "RX FIFO Reset"] + #[inline(always)] + pub const fn rxfiforst(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "RX FIFO Reset"] + #[inline(always)] + pub fn set_rxfiforst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "TX FIFO Reset"] + #[inline(always)] + pub const fn txfiforst(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "TX FIFO Reset"] + #[inline(always)] + pub fn set_txfiforst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "TX FIFO Trigger Level"] + #[inline(always)] + pub const fn txtl(&self) -> super::vals::Txtl { + let val = (self.0 >> 4usize) & 0x03; + super::vals::Txtl::from_bits(val as u8) + } + #[doc = "TX FIFO Trigger Level"] + #[inline(always)] + pub fn set_txtl(&mut self, val: super::vals::Txtl) { + self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); + } + #[doc = "RX FIFO Trigger Level"] + #[inline(always)] + pub const fn rxtl(&self) -> super::vals::Rxtl { + let val = (self.0 >> 6usize) & 0x03; + super::vals::Rxtl::from_bits(val as u8) + } + #[doc = "RX FIFO Trigger Level"] + #[inline(always)] + pub fn set_rxtl(&mut self, val: super::vals::Rxtl) { + self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize); + } +} +impl Default for Fcr { + #[inline(always)] + fn default() -> Fcr { + Fcr(0) + } +} +#[doc = "UART A Interrupt Enable"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Ier(pub u32); +impl Ier { + #[doc = "Enable the UART RX Buffer Full Interrupt"] + #[inline(always)] + pub const fn rbrie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Enable the UART RX Buffer Full Interrupt"] + #[inline(always)] + pub fn set_rbrie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Enable the UART TX Holding Register Empty Interrupt"] + #[inline(always)] + pub const fn threie(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Enable the UART TX Holding Register Empty Interrupt"] + #[inline(always)] + pub fn set_threie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Enable the UART RX Line Status Interrupt"] + #[inline(always)] + pub const fn rlsie(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Enable the UART RX Line Status Interrupt"] + #[inline(always)] + pub fn set_rlsie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } +} +impl Default for Ier { + #[inline(always)] + fn default() -> Ier { + Ier(0) + } +} +#[doc = "UART A Interrupt Identification"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Iir(pub u32); +impl Iir { + #[doc = "Interrupt Status"] + #[inline(always)] + pub const fn intstatus(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Interrupt Status"] + #[inline(always)] + pub fn set_intstatus(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Interrupt Identification"] + #[inline(always)] + pub const fn intid(&self) -> super::vals::Intid { + let val = (self.0 >> 1usize) & 0x07; + super::vals::Intid::from_bits(val as u8) + } + #[doc = "Interrupt Identification"] + #[inline(always)] + pub fn set_intid(&mut self, val: super::vals::Intid) { + self.0 = (self.0 & !(0x07 << 1usize)) | (((val.to_bits() as u32) & 0x07) << 1usize); + } +} +impl Default for Iir { + #[inline(always)] + fn default() -> Iir { + Iir(0) + } +} +#[doc = "UART A Line Control"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Lcr(pub u32); +impl Lcr { + #[doc = "Word Length Select"] + #[inline(always)] + pub const fn wls(&self) -> super::vals::Wls { + let val = (self.0 >> 0usize) & 0x03; + super::vals::Wls::from_bits(val as u8) + } + #[doc = "Word Length Select"] + #[inline(always)] + pub fn set_wls(&mut self, val: super::vals::Wls) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + #[doc = "Stop Bit Select"] + #[inline(always)] + pub const fn sbs(&self) -> super::vals::Sbs { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Sbs::from_bits(val as u8) + } + #[doc = "Stop Bit Select"] + #[inline(always)] + pub fn set_sbs(&mut self, val: super::vals::Sbs) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); + } + #[doc = "Parity Enable"] + #[inline(always)] + pub const fn pen(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Parity Enable"] + #[inline(always)] + pub fn set_pen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Parity Select"] + #[inline(always)] + pub const fn psel(&self) -> super::vals::Psel { + let val = (self.0 >> 4usize) & 0x03; + super::vals::Psel::from_bits(val as u8) + } + #[doc = "Parity Select"] + #[inline(always)] + pub fn set_psel(&mut self, val: super::vals::Psel) { + self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); + } + #[doc = "Break Control"] + #[inline(always)] + pub const fn bcon(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Break Control"] + #[inline(always)] + pub fn set_bcon(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } +} +impl Default for Lcr { + #[inline(always)] + fn default() -> Lcr { + Lcr(0) + } +} +#[doc = "UART A Line Status"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Lsr(pub u32); +impl Lsr { + #[doc = "Receiver Data Ready"] + #[inline(always)] + pub const fn rdr(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Receiver Data Ready"] + #[inline(always)] + pub fn set_rdr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Overrun Error"] + #[inline(always)] + pub const fn oe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Overrun Error"] + #[inline(always)] + pub fn set_oe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Parity Error"] + #[inline(always)] + pub const fn pe(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Parity Error"] + #[inline(always)] + pub fn set_pe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Framing Error"] + #[inline(always)] + pub const fn fe(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Framing Error"] + #[inline(always)] + pub fn set_fe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Break Interrupt"] + #[inline(always)] + pub const fn bi(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Break Interrupt"] + #[inline(always)] + pub fn set_bi(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Transmitter Holding Register Empty"] + #[inline(always)] + pub const fn thre(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Transmitter Holding Register Empty"] + #[inline(always)] + pub fn set_thre(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmitter Empty"] + #[inline(always)] + pub const fn temt(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmitter Empty"] + #[inline(always)] + pub fn set_temt(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Error in RX FIFO"] + #[inline(always)] + pub const fn rxfe(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Error in RX FIFO"] + #[inline(always)] + pub fn set_rxfe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } +} +impl Default for Lsr { + #[inline(always)] + fn default() -> Lsr { + Lsr(0) + } +} +#[doc = "UART A Receive Buffer"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Rbr(pub u32); +impl Rbr { + #[doc = "Oldest received character in the UART RX FIFO"] + #[inline(always)] + pub const fn rbr(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Oldest received character in the UART RX FIFO"] + #[inline(always)] + pub fn set_rbr(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } +} +impl Default for Rbr { + #[inline(always)] + fn default() -> Rbr { + Rbr(0) + } +} +#[doc = "UART A Scratch Pad"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Scr(pub u32); +impl Scr { + #[doc = "Readable/writable byte"] + #[inline(always)] + pub const fn pad(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Readable/writable byte"] + #[inline(always)] + pub fn set_pad(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } +} +impl Default for Scr { + #[inline(always)] + fn default() -> Scr { + Scr(0) + } +} +#[doc = "UART A Transmit Holding"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Thr(pub u32); +impl Thr { + #[doc = "Place a character in the UART TX FIFO"] + #[inline(always)] + pub const fn thr(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Place a character in the UART TX FIFO"] + #[inline(always)] + pub fn set_thr(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } +} +impl Default for Thr { + #[inline(always)] + fn default() -> Thr { + Thr(0) + } +} diff --git a/src/usart/vals.rs b/src/usart/vals.rs new file mode 100644 index 0000000..2b685c8 --- /dev/null +++ b/src/usart/vals.rs @@ -0,0 +1,204 @@ +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Intid { + _RESERVED_0 = 0x0, + #[doc = "TX Holding Register Empty"] + TX_HOLDING_REGISTER_EMPTY = 0x01, + #[doc = "Receive Data Available"] + RX_DATA_AVAILABLE = 0x02, + #[doc = "Receive Line Status"] + RX_LINE_STATUS = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + #[doc = "Receive FIFO Character Timeout"] + RX_FIFO_TIMEOUT = 0x06, + _RESERVED_7 = 0x07, +} +impl Intid { + #[inline(always)] + pub const fn from_bits(val: u8) -> Intid { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Intid { + #[inline(always)] + fn from(val: u8) -> Intid { + Intid::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Intid) -> u8 { + Intid::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Psel { + #[doc = "Odd parity"] + ODD_PARITY = 0x0, + #[doc = "Even parity"] + EVEN_PARITY = 0x01, + #[doc = "Forced 1 sticky parity"] + FORCED_1_STICKY_PARITY = 0x02, + #[doc = "Forced 0 sticky parity"] + FORCED_0_STICKY_PARITY = 0x03, +} +impl Psel { + #[inline(always)] + pub const fn from_bits(val: u8) -> Psel { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Psel { + #[inline(always)] + fn from(val: u8) -> Psel { + Psel::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Psel) -> u8 { + Psel::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Rxtl { + #[doc = "1 character"] + FIFO1 = 0x0, + #[doc = "4 characters"] + FIFO4 = 0x01, + #[doc = "8 characters"] + FIFO8 = 0x02, + #[doc = "14 characters"] + FIFO14 = 0x03, +} +impl Rxtl { + #[inline(always)] + pub const fn from_bits(val: u8) -> Rxtl { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Rxtl { + #[inline(always)] + fn from(val: u8) -> Rxtl { + Rxtl::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Rxtl) -> u8 { + Rxtl::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Sbs { + #[doc = "1 stop bit"] + ONE = 0x0, + #[doc = "2 stop bits (1.5 if LCR.WLS = 0)"] + TWO = 0x01, +} +impl Sbs { + #[inline(always)] + pub const fn from_bits(val: u8) -> Sbs { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Sbs { + #[inline(always)] + fn from(val: u8) -> Sbs { + Sbs::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Sbs) -> u8 { + Sbs::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Txtl { + #[doc = "1 character"] + FIFO1 = 0x0, + #[doc = "4 characters"] + FIFO4 = 0x01, + #[doc = "8 characters"] + FIFO8 = 0x02, + #[doc = "14 characters"] + FIFO14 = 0x03, +} +impl Txtl { + #[inline(always)] + pub const fn from_bits(val: u8) -> Txtl { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Txtl { + #[inline(always)] + fn from(val: u8) -> Txtl { + Txtl::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Txtl) -> u8 { + Txtl::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Wls { + #[doc = "5 bits"] + WL5 = 0x0, + #[doc = "6 bits"] + WL6 = 0x01, + #[doc = "7 bits"] + WL7 = 0x02, + #[doc = "8 bits"] + WL8 = 0x03, +} +impl Wls { + #[inline(always)] + pub const fn from_bits(val: u8) -> Wls { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Wls { + #[inline(always)] + fn from(val: u8) -> Wls { + Wls::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Wls) -> u8 { + Wls::to_bits(val) + } +} diff --git a/src/wwdt.rs b/src/wwdt.rs new file mode 100644 index 0000000..ce6db49 --- /dev/null +++ b/src/wwdt.rs @@ -0,0 +1,49 @@ +#[doc = "Windowed Watchdog Timer"] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Wwdt { + ptr: *mut u8, +} +unsafe impl Send for Wwdt {} +unsafe impl Sync for Wwdt {} +impl Wwdt { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "WWDT Control"] + #[inline(always)] + pub const fn ctl(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "WWDT Load Counter Value"] + #[inline(always)] + pub const fn cdctl(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } + #[doc = "WWDT Counter"] + #[inline(always)] + pub const fn ctr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } + } + #[doc = "WWDT Interrupt Flag"] + #[inline(always)] + pub const fn flag(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } + #[doc = "WWDT Interrupt Clear"] + #[inline(always)] + pub const fn clear(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } + } + #[doc = "WWDT Lock"] + #[inline(always)] + pub const fn lock(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } + } +} +pub mod regs; +pub mod vals; diff --git a/src/wwdt/regs.rs b/src/wwdt/regs.rs new file mode 100644 index 0000000..6481519 --- /dev/null +++ b/src/wwdt/regs.rs @@ -0,0 +1,205 @@ +#[doc = "WWDT Load Counter Value"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Cdctl(pub u32); +impl Cdctl { + #[doc = "WWDT count-down value"] + #[inline(always)] + pub const fn cdv(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "WWDT count-down value"] + #[inline(always)] + pub fn set_cdv(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + #[doc = "WWDT window value"] + #[inline(always)] + pub const fn window(&self) -> u16 { + let val = (self.0 >> 16usize) & 0xffff; + val as u16 + } + #[doc = "WWDT window value"] + #[inline(always)] + pub fn set_window(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); + } +} +impl Default for Cdctl { + #[inline(always)] + fn default() -> Cdctl { + Cdctl(0) + } +} +#[doc = "WWDT Interrupt Clear"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Clear(pub u32); +impl Clear { + #[doc = "WWDT clear"] + #[inline(always)] + pub const fn value(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "WWDT clear"] + #[inline(always)] + pub fn set_value(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for Clear { + #[inline(always)] + fn default() -> Clear { + Clear(0) + } +} +#[doc = "WWDT Control"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Ctl(pub u32); +impl Ctl { + #[doc = "Enable WWDT"] + #[inline(always)] + pub const fn en(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Enable WWDT"] + #[inline(always)] + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Enable WWDT interrupt"] + #[inline(always)] + pub const fn inten(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Enable WWDT interrupt"] + #[inline(always)] + pub fn set_inten(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Enable WWDT POR reset"] + #[inline(always)] + pub const fn rsten(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Enable WWDT POR reset"] + #[inline(always)] + pub fn set_rsten(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "WWDT input clock source"] + #[inline(always)] + pub const fn clksel(&self) -> super::vals::Clksel { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Clksel::from_bits(val as u8) + } + #[doc = "WWDT input clock source"] + #[inline(always)] + pub fn set_clksel(&mut self, val: super::vals::Clksel) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize); + } + #[doc = "WWDT input clock divider"] + #[inline(always)] + pub const fn clkdiv(&self) -> super::vals::Clkdiv { + let val = (self.0 >> 4usize) & 0x0f; + super::vals::Clkdiv::from_bits(val as u8) + } + #[doc = "WWDT input clock divider"] + #[inline(always)] + pub fn set_clkdiv(&mut self, val: super::vals::Clkdiv) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val.to_bits() as u32) & 0x0f) << 4usize); + } +} +impl Default for Ctl { + #[inline(always)] + fn default() -> Ctl { + Ctl(0) + } +} +#[doc = "WWDT Counter"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Ctr(pub u32); +impl Ctr { + #[doc = "WWDT counter value"] + #[inline(always)] + pub const fn cnt(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "WWDT counter value"] + #[inline(always)] + pub fn set_cnt(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } +} +impl Default for Ctr { + #[inline(always)] + fn default() -> Ctr { + Ctr(0) + } +} +#[doc = "WWDT Interrupt Flag"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Flag(pub u32); +impl Flag { + #[doc = "WWDT interrupt flag"] + #[inline(always)] + pub const fn if_(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "WWDT interrupt flag"] + #[inline(always)] + pub fn set_if_(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "WWDT reset flag"] + #[inline(always)] + pub const fn rstf(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "WWDT reset flag"] + #[inline(always)] + pub fn set_rstf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } +} +impl Default for Flag { + #[inline(always)] + fn default() -> Flag { + Flag(0) + } +} +#[doc = "WWDT Lock"] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Lock(pub u32); +impl Lock { + #[doc = "WWDT lock"] + #[inline(always)] + pub const fn value(&self) -> super::vals::Value { + let val = (self.0 >> 0usize) & 0xffff_ffff; + super::vals::Value::from_bits(val as u32) + } + #[doc = "WWDT lock"] + #[inline(always)] + pub fn set_value(&mut self, val: super::vals::Value) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) + | (((val.to_bits() as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for Lock { + #[inline(always)] + fn default() -> Lock { + Lock(0) + } +} diff --git a/src/wwdt/vals.rs b/src/wwdt/vals.rs new file mode 100644 index 0000000..96b1a20 --- /dev/null +++ b/src/wwdt/vals.rs @@ -0,0 +1,117 @@ +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Clkdiv { + #[doc = "/1"] + DIV1 = 0x0, + #[doc = "/2"] + DIV2 = 0x01, + #[doc = "/4"] + DIV4 = 0x02, + #[doc = "/8"] + DIV8 = 0x03, + #[doc = "/16"] + DIV16 = 0x04, + #[doc = "/32"] + DIV32 = 0x05, + #[doc = "/64"] + DIV64 = 0x06, + #[doc = "/128"] + DIV128 = 0x07, + #[doc = "/256"] + DIV256 = 0x08, + #[doc = "/512"] + DIV512 = 0x09, + #[doc = "/1024"] + DIV1024 = 0x0a, + #[doc = "/2048"] + DIV2048 = 0x0b, + #[doc = "/4096"] + DIV4096 = 0x0c, + #[doc = "/8192"] + DIV8192 = 0x0d, + #[doc = "/16384"] + DIV16384 = 0x0e, + #[doc = "/32768"] + DIV32768 = 0x0f, +} +impl Clkdiv { + #[inline(always)] + pub const fn from_bits(val: u8) -> Clkdiv { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Clkdiv { + #[inline(always)] + fn from(val: u8) -> Clkdiv { + Clkdiv::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Clkdiv) -> u8 { + Clkdiv::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub enum Clksel { + #[doc = "FRCLK as WWDT clock"] + FRCLK = 0x0, + #[doc = "ROSCCLK as WWDT clock"] + ROSCCLK = 0x01, +} +impl Clksel { + #[inline(always)] + pub const fn from_bits(val: u8) -> Clksel { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Clksel { + #[inline(always)] + fn from(val: u8) -> Clksel { + Clksel::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Clksel) -> u8 { + Clksel::to_bits(val) + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub struct Value(pub u32); +impl Value { + #[doc = "WWDT registers are read-only"] + pub const READ_ONLY: Self = Self(0x55aa_6698); + #[doc = "WWDT registers available for write"] + pub const ALLOW_WRITE: Self = Self(0x55aa_6699); +} +impl Value { + pub const fn from_bits(val: u32) -> Value { + Self(val & 0xffff_ffff) + } + pub const fn to_bits(self) -> u32 { + self.0 + } +} +impl From for Value { + #[inline(always)] + fn from(val: u32) -> Value { + Value::from_bits(val) + } +} +impl From for u32 { + #[inline(always)] + fn from(val: Value) -> u32 { + Value::to_bits(val) + } +} diff --git a/svd/PAC55XX.svd b/svd/PAC55XX.svd new file mode 100644 index 0000000..7c74ccd --- /dev/null +++ b/svd/PAC55XX.svd @@ -0,0 +1,13243 @@ + + + Qorvo, Inc. + Qorvo + PAC55XX + PAC55XX + 1.0 + ARM Cortex-M4 processor with FPU, running up to 150MHz with a set of analog and digital peripherals for power and motor control applications. + Apache-2.0 OR MIT + + CM4 + r0p1 + little + true + true + 3 + true + + 8 + 32 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADC + Analog to Digital Converter (ADC) and Dynamic Triggering and Sampling Engine (DTSE) + 0x40000000 + + 0x0 + 0x10000 + registers + + + ADC0 + ADC 0 Interrupt + 3 + + + ADC1 + ADC 1 Interrupt + 4 + + + ADC2 + ADC 2 Interrupt + 5 + + + ADC3 + ADC 3 Interrupt + 6 + + + + EMUXCTL + EMUX Control + 0x0 + + + EMUXDIV + EMUX Clock Divider + 0 + 4 + read-write + + EMUXDIV + read-write + + SCLK1 + SCLK/1 + 0 + + + SCLK2 + SCLK/2 + 1 + + + SCLK3 + SCLK/3 + 2 + + + SCLK4 + SCLK/4 + 3 + + + SCLK5 + SCLK/5 + 4 + + + SCLK6 + SCLK/6 + 5 + + + SCLK7 + SCLK/7 + 6 + + + SCLK8 + SCLK/8 + 7 + + + SCLK9 + SCLK/9 + 8 + + + SCLK10 + SCLK/10 + 9 + + + SCLK11 + SCLK/11 + 10 + + + SCLK12 + SCLK/12 + 11 + + + SCLK13 + SCLK/13 + 12 + + + SCLK14 + SCLK/14 + 13 + + + SCLK15 + SCLK/15 + 14 + + + + + EMUXBUSY + EMUX Busy + 4 + 1 + read-only + + + EMUXMODE + EMUX Mode + 5 + 1 + read-write + + EMUXMODE + read-write + + DATA_FROM_EMUXDATA + Write EMUX data from EMUXDATA register + 0 + + + DATA_FROM_DTSE + Write EMUX data from DTSE sequencer commands + 1 + + + + + + + EMUXDATA + EMUX Data + 0x4 + + + EMUXDATA + Write data onto the EMUX + 0 + 8 + read-write + + + + + ADCCTL + ADC Control + 0x8 + + + ADCDIV + ADC Clock Divider + 0 + 4 + read-write + + ADCDIV + read-write + + SCLK1 + SCLK/1 + 0 + + + SCLK2 + SCLK/2 + 1 + + + SCLK3 + SCLK/3 + 2 + + + SCLK4 + SCLK/4 + 3 + + + SCLK5 + SCLK/5 + 4 + + + SCLK6 + SCLK/6 + 5 + + + SCLK7 + SCLK/7 + 6 + + + SCLK8 + SCLK/8 + 7 + + + SCLK9 + SCLK/9 + 8 + + + SCLK10 + SCLK/10 + 9 + + + SCLK11 + SCLK/11 + 10 + + + SCLK12 + SCLK/12 + 11 + + + SCLK13 + SCLK/13 + 12 + + + SCLK14 + SCLK/14 + 13 + + + SCLK15 + SCLK/15 + 14 + + + SCLK16 + SCLK/16 + 15 + + + + + CHANNEL + ADC Channel Select + 4 + 3 + read-write + + + ADBUSY + ADC Busy + 7 + 1 + read-only + + + MODE + ADC Mode + 8 + 2 + read-write + + ADCMODE + read-write + + MANUAL + Manual mode + 0 + + + DTSE + DTSE mode + 1 + + + + + REPEAT + ADC Repeat + 10 + 1 + read-write + + + START + ADC Start + 11 + 1 + write-only + + + ENABLE + ADC Enable + 12 + 1 + read-write + + + INTENMAN + Manual Conversion Complete Interrupt Enable + 13 + 1 + read-write + + + INTENEMUX + EMUX Complete Interrupt Enable + 14 + 1 + read-write + + + INTENCOL + Sequence Collision Interrupt Enable + 15 + 1 + read-write + + + ENACC + ADC Accuracy Mode Enable + 18 + 1 + read-write + + + + + ADCRES + ADC Result + 0xC + + + ADCRES + ADC Conversion Result (manual mode) + 0 + 12 + read-only + + + + + ADCINT + ADC Interrupt Control + 0x10 + + + INTF0 + DTSE Sequence 0 Interrupt Flag + 0 + 1 + write-only + + + INTF1 + DTSE Sequence 1 Interrupt Flag + 1 + 1 + write-only + + + INTF2 + DTSE Sequence 2 Interrupt Flag + 2 + 1 + write-only + + + INTF3 + DTSE Sequence 3 Interrupt Flag + 3 + 1 + write-only + + + INTF4 + DTSE Sequence 4 Interrupt Flag + 4 + 1 + write-only + + + INTF5 + DTSE Sequence 5 Interrupt Flag + 5 + 1 + write-only + + + INTF6 + DTSE Sequence 6 Interrupt Flag + 6 + 1 + write-only + + + INTF7 + DTSE Sequence 7 Interrupt Flag + 7 + 1 + write-only + + + INTF8 + DTSE Sequence 8 Interrupt Flag + 8 + 1 + write-only + + + INTF9 + DTSE Sequence 9 Interrupt Flag + 9 + 1 + write-only + + + INTF10 + DTSE Sequence 10 Interrupt Flag + 10 + 1 + write-only + + + INTF11 + DTSE Sequence 11 Interrupt Flag + 11 + 1 + write-only + + + INTF12 + DTSE Sequence 12 Interrupt Flag + 12 + 1 + write-only + + + INTF13 + DTSE Sequence 13 Interrupt Flag + 13 + 1 + write-only + + + INTF14 + DTSE Sequence 14 Interrupt Flag + 14 + 1 + write-only + + + INTF15 + DTSE Sequence 15 Interrupt Flag + 15 + 1 + write-only + + + INTF16 + DTSE Sequence 16 Interrupt Flag + 16 + 1 + write-only + + + INTF17 + DTSE Sequence 17 Interrupt Flag + 17 + 1 + write-only + + + INTF18 + DTSE Sequence 18 Interrupt Flag + 18 + 1 + write-only + + + INTF19 + DTSE Sequence 19 Interrupt Flag + 19 + 1 + write-only + + + INTF20 + DTSE Sequence 20 Interrupt Flag + 20 + 1 + write-only + + + INTF21 + DTSE Sequence 21 Interrupt Flag + 21 + 1 + write-only + + + INTF22 + DTSE Sequence 22 Interrupt Flag + 22 + 1 + write-only + + + INTF23 + DTSE Sequence 23 Interrupt Flag + 23 + 1 + write-only + + + INTFMAN + DTSE Manual Conversion Complete Interrupt Flag + 24 + 1 + write-only + + + INTFEMUX + DTSE EMUX Complete Interrupt Flag + 25 + 1 + write-only + + + INTFCOL + DTSE Sequence Collision Interrupt Flag + 26 + 1 + write-only + + + ADCIRQ0IF + ADCIRQ0 Interrupt Flag + 28 + 1 + write-only + + + ADCIRQ1IF + ADCIRQ1 Interrupt Flag + 29 + 1 + write-only + + + ADCIRQ2IF + ADCIRQ2 Interrupt Flag + 30 + 1 + write-only + + + ADCIRQ3IF + ADCIRQ3 Interrupt Flag + 31 + 1 + write-only + + + + + DTSETRIGENT0TO3 + DTSE Trigger Entry 0 to 3 + 0x40 + + + TRIG0CFGIDX + DTSE Trigger 0 Sequence Configuration Entry Index + 0 + 5 + read-write + + + TRIG0EDGE + DTSE Trigger 0 Edge Configuration + 5 + 2 + read-write + + TRIG0EDGE + read-write + + UNUSED + Unused + 0 + + + RISING_EDGE + Rising edge + 1 + + + FALLING_EDGE + Falling edge + 2 + + + BOTH_EDGES + Both edges + 3 + + + + + FORCE0 + Force Trigger 0 + 7 + 1 + write-only + + + TRIG1CFGIDX + DTSE Trigger 1 Sequence Configuration Entry Index + 8 + 5 + read-write + + + TRIG1EDGE + DTSE Trigger 1 Edge Configuration + 13 + 2 + read-write + + + + FORCE1 + Force Trigger 1 + 15 + 1 + write-only + + + TRIG2CFGIDX + DTSE Trigger 2 Sequence Configuration Entry Index + 16 + 5 + read-write + + + TRIG2EDGE + DTSE Trigger 2 Edge Configuration + 21 + 2 + read-write + + + + FORCE2 + Force Trigger 2 + 23 + 1 + write-only + + + TRIG3CFGIDX + DTSE Trigger 3 Sequence Configuration Entry Index + 24 + 5 + read-write + + + TRIG3EDGE + DTSE Trigger 3 Edge Configuration + 29 + 2 + read-write + + + + FORCE3 + Force Trigger 3 + 31 + 1 + write-only + + + + + DTSETRIGENT4TO7 + DTSE Trigger Entry 4 to 7 + 0x44 + + + TRIG4CFGIDX + DTSE Trigger 4 Sequence Configuration Entry Index + 0 + 5 + read-write + + + TRIG4EDGE + DTSE Trigger 4 Edge Configuration + 5 + 2 + read-write + + TRIG4EDGE + read-write + + UNUSED + Unused + 0 + + + RISING_EDGE + Rising edge + 1 + + + FALLING_EDGE + Falling edge + 2 + + + BOTH_EDGES + Both edges + 3 + + + + + FORCE4 + Force Trigger 4 + 7 + 1 + write-only + + + TRIG5CFGIDX + DTSE Trigger 5 Sequence Configuration Entry Index + 8 + 5 + read-write + + + TRIG5EDGE + DTSE Trigger 5 Edge Configuration + 13 + 2 + read-write + + + + FORCE5 + Force Trigger 5 + 15 + 1 + write-only + + + TRIG6CFGIDX + DTSE Trigger 6 Sequence Configuration Entry Index + 16 + 5 + read-write + + + TRIG6EDGE + DTSE Trigger 6 Edge Configuration + 21 + 2 + read-write + + + + FORCE6 + Force Trigger 6 + 23 + 1 + write-only + + + TRIG7CFGIDX + DTSE Trigger 7 Sequence Configuration Entry Index + 24 + 5 + read-write + + + TRIG7EDGE + DTSE Trigger 7 Edge Configuration + 29 + 2 + read-write + + + + FORCE7 + Force Trigger 7 + 31 + 1 + write-only + + + + + DTSETRIGENT8TO11 + DTSE Trigger Entry 8 to 11 + 0x48 + + + TRIG8CFGIDX + DTSE Trigger 8 Sequence Configuration Entry Index + 0 + 5 + read-write + + + TRIG8EDGE + DTSE Trigger 8 Edge Configuration + 5 + 2 + read-write + + TRIG8EDGE + read-write + + UNUSED + Unused + 0 + + + RISING_EDGE + Rising edge + 1 + + + FALLING_EDGE + Falling edge + 2 + + + BOTH_EDGES + Both edges + 3 + + + + + FORCE8 + Force Trigger 8 + 7 + 1 + write-only + + + TRIG9CFGIDX + DTSE Trigger 9 Sequence Configuration Entry Index + 8 + 5 + read-write + + + TRIG9EDGE + DTSE Trigger 9 Edge Configuration + 13 + 2 + read-write + + + + FORCE9 + Force Trigger 9 + 15 + 1 + write-only + + + TRIG10CFGIDX + DTSE Trigger 10 Sequence Configuration Entry Index + 16 + 5 + read-write + + + TRIG10EDGE + DTSE Trigger 10 Edge Configuration + 21 + 2 + read-write + + + + FORCE10 + Force Trigger 10 + 23 + 1 + write-only + + + TRIG11CFGIDX + DTSE Trigger 11 Sequence Configuration Entry Index + 24 + 5 + read-write + + + TRIG11EDGE + DTSE Trigger 11 Edge Configuration + 29 + 2 + read-write + + + + FORCE11 + Force Trigger 11 + 31 + 1 + write-only + + + + + DTSETRIGENT12TO15 + DTSE Trigger Entry 12 to 15 + 0x4C + + + TRIG12CFGIDX + DTSE Trigger 12 Sequence Configuration Entry Index + 0 + 5 + read-write + + + TRIG12EDGE + DTSE Trigger 12 Edge Configuration + 5 + 2 + read-write + + TRIG12EDGE + read-write + + UNUSED + Unused + 0 + + + RISING_EDGE + Rising edge + 1 + + + FALLING_EDGE + Falling edge + 2 + + + BOTH_EDGES + Both edges + 3 + + + + + FORCE12 + Force Trigger 12 + 7 + 1 + write-only + + + TRIG13CFGIDX + DTSE Trigger 13 Sequence Configuration Entry Index + 8 + 5 + read-write + + + TRIG13EDGE + DTSE Trigger 13 Edge Configuration + 13 + 2 + read-write + + + + FORCE13 + Force Trigger 13 + 15 + 1 + write-only + + + TRIG14CFGIDX + DTSE Trigger 14 Sequence Configuration Entry Index + 16 + 5 + read-write + + + TRIG14EDGE + DTSE Trigger 14 Edge Configuration + 21 + 2 + read-write + + + + FORCE14 + Force Trigger 14 + 23 + 1 + write-only + + + TRIG15CFGIDX + DTSE Trigger 15 Sequence Configuration Entry Index + 24 + 5 + read-write + + + TRIG15EDGE + DTSE Trigger 15 Edge Configuration + 29 + 2 + read-write + + + + FORCE15 + Force Trigger 15 + 31 + 1 + write-only + + + + + DTSETRIGENT16TO19 + DTSE Trigger Entry 16 to 19 + 0x50 + + + TRIG16CFGIDX + DTSE Trigger 16 Sequence Configuration Entry Index + 0 + 5 + read-write + + + TRIG16EDGE + DTSE Trigger 16 Edge Configuration + 5 + 2 + read-write + + TRIG16EDGE + read-write + + UNUSED + Unused + 0 + + + RISING_EDGE + Rising edge + 1 + + + FALLING_EDGE + Falling edge + 2 + + + BOTH_EDGES + Both edges + 3 + + + + + FORCE16 + Force Trigger 16 + 7 + 1 + write-only + + + TRIG17CFGIDX + DTSE Trigger 17 Sequence Configuration Entry Index + 8 + 5 + read-write + + + TRIG17EDGE + DTSE Trigger 17 Edge Configuration + 13 + 2 + read-write + + + + FORCE17 + Force Trigger 17 + 15 + 1 + write-only + + + TRIG18CFGIDX + DTSE Trigger 18 Sequence Configuration Entry Index + 16 + 5 + read-write + + + TRIG18EDGE + DTSE Trigger 18 Edge Configuration + 21 + 2 + read-write + + + + FORCE18 + Force Trigger 18 + 23 + 1 + write-only + + + TRIG19CFGIDX + DTSE Trigger 19 Sequence Configuration Entry Index + 24 + 5 + read-write + + + TRIG19EDGE + DTSE Trigger 19 Edge Configuration + 29 + 2 + read-write + + + + FORCE19 + Force Trigger 19 + 31 + 1 + write-only + + + + + DTSETRIGENT20TO23 + DTSE Trigger Entry 20 to 23 + 0x54 + + + TRIG20CFGIDX + DTSE Trigger 20 Sequence Configuration Entry Index + 0 + 5 + read-write + + + TRIG20EDGE + DTSE Trigger 20 Edge Configuration + 5 + 2 + read-write + + TRIG20EDGE + read-write + + UNUSED + Unused + 0 + + + RISING_EDGE + Rising edge + 1 + + + FALLING_EDGE + Falling edge + 2 + + + BOTH_EDGES + Both edges + 3 + + + + + FORCE20 + Force Trigger 20 + 7 + 1 + write-only + + + TRIG21CFGIDX + DTSE Trigger 21 Sequence Configuration Entry Index + 8 + 5 + read-write + + + TRIG21EDGE + DTSE Trigger 21 Edge Configuration + 13 + 2 + read-write + + + + FORCE21 + Force Trigger 21 + 15 + 1 + write-only + + + TRIG22CFGIDX + DTSE Trigger 22 Sequence Configuration Entry Index + 16 + 5 + read-write + + + TRIG22EDGE + DTSE Trigger 22 Edge Configuration + 21 + 2 + read-write + + + + FORCE22 + Force Trigger 22 + 23 + 1 + write-only + + + TRIG23CFGIDX + DTSE Trigger 23 Sequence Configuration Entry Index + 24 + 5 + read-write + + + TRIG23EDGE + DTSE Trigger 23 Edge Configuration + 29 + 2 + read-write + + + + FORCE23 + Force Trigger 23 + 31 + 1 + write-only + + + + + DTSETRIGENT24TO27 + DTSE Trigger Entry 24 to 27 + 0x58 + + + TRIG24CFGIDX + DTSE Trigger 24 Sequence Configuration Entry Index + 0 + 5 + read-write + + + TRIG24EDGE + DTSE Trigger 24 Edge Configuration + 5 + 2 + read-write + + TRIG24EDGE + read-write + + UNUSED + Unused + 0 + + + RISING_EDGE + Rising edge + 1 + + + FALLING_EDGE + Falling edge + 2 + + + BOTH_EDGES + Both edges + 3 + + + + + FORCE24 + Force Trigger 24 + 7 + 1 + write-only + + + TRIG25CFGIDX + DTSE Trigger 25 Sequence Configuration Entry Index + 8 + 5 + read-write + + + TRIG25EDGE + DTSE Trigger 25 Edge Configuration + 13 + 2 + read-write + + + + FORCE25 + Force Trigger 25 + 15 + 1 + write-only + + + TRIG26CFGIDX + DTSE Trigger 26 Sequence Configuration Entry Index + 16 + 5 + read-write + + + TRIG26EDGE + DTSE Trigger 26 Edge Configuration + 21 + 2 + read-write + + + + FORCE26 + Force Trigger 26 + 23 + 1 + write-only + + + TRIG27CFGIDX + DTSE Trigger 27 Sequence Configuration Entry Index + 24 + 5 + read-write + + + TRIG27EDGE + DTSE Trigger 27 Edge Configuration + 29 + 2 + read-write + + + + FORCE27 + Force Trigger 27 + 31 + 1 + write-only + + + + + DTSETRIGENT28TO31 + DTSE Trigger Entry 28 to 31 + 0x5C + + + TRIG28CFGIDX + DTSE Trigger 28 Sequence Configuration Entry Index + 0 + 5 + read-write + + + TRIG28EDGE + DTSE Trigger 28 Edge Configuration + 5 + 2 + read-write + + TRIG28EDGE + read-write + + UNUSED + Unused + 0 + + + RISING_EDGE + Rising edge + 1 + + + FALLING_EDGE + Falling edge + 2 + + + BOTH_EDGES + Both edges + 3 + + + + + FORCE28 + Force Trigger 28 + 7 + 1 + write-only + + + TRIG29CFGIDX + DTSE Trigger 29 Sequence Configuration Entry Index + 8 + 5 + read-write + + + TRIG29EDGE + DTSE Trigger 29 Edge Configuration + 13 + 2 + read-write + + + + FORCE29 + Force Trigger 29 + 15 + 1 + write-only + + + TRIG30CFGIDX + DTSE Trigger 30 Sequence Configuration Entry Index + 16 + 5 + read-write + + + TRIG30EDGE + DTSE Trigger 30 Edge Configuration + 21 + 2 + read-write + + + + FORCE30 + Force Trigger 30 + 23 + 1 + write-only + + + TRIG31CFGIDX + DTSE Trigger 31 Sequence Configuration Entry Index + 24 + 5 + read-write + + + TRIG31EDGE + DTSE Trigger 31 Edge Configuration + 29 + 2 + read-write + + + + FORCE31 + Force Trigger 31 + 31 + 1 + write-only + + + + + DTSESEQCFG0 + DTSE Sequence Configuration 0 + 0x80 + + + EMUXC + EMUX Control + 0 + 2 + read-write + + EMUXC + read-write + + NO_EMUX_CMD + Do not send EMUX command + 0 + + + EMUX_CMD_BEFORE_SAMPLE + Send EMUX command before sample and hold + 1 + + + EMUX_CMD_AFTER_CONVERSION + Send EMUX command after conversion is complete + 2 + + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG1 + DTSE Sequence Configuration 1 + 0x84 + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG2 + DTSE Sequence Configuration 2 + 0x88 + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG3 + DTSE Sequence Configuration 3 + 0x8C + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG4 + DTSE Sequence Configuration 4 + 0x90 + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG5 + DTSE Sequence Configuration 5 + 0x94 + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG6 + DTSE Sequence Configuration 6 + 0x98 + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG7 + DTSE Sequence Configuration 7 + 0x9C + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG8 + DTSE Sequence Configuration 8 + 0xA0 + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG9 + DTSE Sequence Configuration 9 + 0xA4 + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG10 + DTSE Sequence Configuration 10 + 0xA8 + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG11 + DTSE Sequence Configuration 11 + 0xAC + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG12 + DTSE Sequence Configuration 12 + 0xB0 + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG13 + DTSE Sequence Configuration 13 + 0xB4 + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG14 + DTSE Sequence Configuration 14 + 0xB8 + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG15 + DTSE Sequence Configuration 15 + 0xBC + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG16 + DTSE Sequence Configuration 16 + 0xC0 + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG17 + DTSE Sequence Configuration 17 + 0xC4 + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG18 + DTSE Sequence Configuration 18 + 0xC8 + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG19 + DTSE Sequence Configuration 19 + 0xCC + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG20 + DTSE Sequence Configuration 20 + 0xD0 + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG21 + DTSE Sequence Configuration 21 + 0xD4 + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG22 + DTSE Sequence Configuration 22 + 0xD8 + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSESEQCFG23 + DTSE Sequence Configuration 23 + 0xDC + + + EMUXC + EMUX Control + 0 + 2 + read-write + + + + CHANNEL + Channel + 2 + 3 + read-write + + + SEQDONE + Final sequence of series + 7 + 1 + read-write + + + EMUXD + EMUX Data + 8 + 8 + read-write + + + IRQNUM + IRQ Number to assert + 16 + 2 + read-write + + + IRQEN + Assert IRQ after converting this sequence + 18 + 1 + read-write + + + NOCVT + No ADC conversion + 19 + 1 + read-write + + + + + DTSERES0 + DTSE Result 0 + 0x200 + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES1 + DTSE Result 1 + 0x204 + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES2 + DTSE Result 2 + 0x208 + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES3 + DTSE Result 3 + 0x20C + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES4 + DTSE Result 4 + 0x210 + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES5 + DTSE Result 5 + 0x214 + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES6 + DTSE Result 6 + 0x218 + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES7 + DTSE Result 7 + 0x21C + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES8 + DTSE Result 8 + 0x220 + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES9 + DTSE Result 9 + 0x224 + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES10 + DTSE Result 10 + 0x228 + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES11 + DTSE Result 11 + 0x22C + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES12 + DTSE Result 12 + 0x230 + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES13 + DTSE Result 13 + 0x234 + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES14 + DTSE Result 14 + 0x238 + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES15 + DTSE Result 15 + 0x23C + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES16 + DTSE Result 16 + 0x240 + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES17 + DTSE Result 17 + 0x244 + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES18 + DTSE Result 18 + 0x248 + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES19 + DTSE Result 19 + 0x24C + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES20 + DTSE Result 20 + 0x250 + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES21 + DTSE Result 21 + 0x254 + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES22 + DTSE Result 22 + 0x258 + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + DTSERES23 + DTSE Result 23 + 0x25C + + + RES + DTSE Conversion Result + 0 + 12 + read-only + + + + + + + I2C + Inter-Integrated Circuit + 0x40010000 + + 0x0 + 0x10000 + registers + + + I2C + I2C Interrupt + 22 + + + + CONSET + I2C Control Set + 0x0 + + + ADRF + Slave Address Flag + 0 + 1 + read-only + + + XADRF + Extended Slave Address Flag (10-bit addressing) + 1 + 1 + read-only + + + AA + Assert Acknowledge Flag + 2 + 1 + read-write + + + SI + I2C Interrupt Flag + 3 + 1 + read-only + + + STO + STOP Flag + 4 + 1 + write-only + + + STA + START Flag + 5 + 1 + write-only + + + I2CEN + I2C Enable + 6 + 1 + read-write + + + I2CIE + I2C Interrupt Enable + 7 + 1 + read-write + + + GCF + General Call Flag + 8 + 1 + read-write + + + + + CONCLR + I2C Control Clear + 0x4 + + + AAC + Assert Acknowledge Clear + 2 + 1 + read-write + + + SIC + I2C Interrupt Clear + 3 + 1 + read-write + + + STAC + START Flag Clear + 5 + 1 + read-write + + + I2CENC + I2C Disable + 6 + 1 + read-write + + + I2CIEC + I2C Interrupt Disable + 7 + 1 + read-write + + + + + STAT + I2C Status + 0x8 + + + STATUS + Status code for I2C engine + 0 + 8 + read-only + + STATUS + read + + BUS_ERROR + Bus Error (master mode only) + 0 + + + START + START condition transmitted + 8 + + + RSTART + Repeated START condition transmitted + 16 + + + SLAW_TX_ACK + Address and Write bit transmitted, ACK received + 24 + + + SLAW_TX_NACK + Address and Write bit transmitted, NACK received + 32 + + + MDATA_TX_ACK + Data byte transmitted in master mode, ACK received + 40 + + + MDATA_TX_NACK + Data byte transmitted in master mode, NACK received + 48 + + + ARB_LOST + Arbitration lost in address or data byte + 56 + + + SLAR_TX_ACK + Address and read bit transmitted, ACK received + 64 + + + SLAR_TX_NACK + Address and read bit transmitted, NACK received + 72 + + + MDATA_RX_ACK + Data byte received in master mode, ACK transmitted + 80 + + + MDATA_RX_NACK + Data byte received in master mode, NACK transmitted + 88 + + + SLAW_RX_ACK + Slave address and write bit received, ACK transmitted + 96 + + + ARB_LOST_SLAW_RX_ACK + Arbitration lost in address as master, slave address and write bit received, ACK transmitted + 104 + + + GC_ACK + General call received, ACK returned + 112 + + + SDATA_RX_ACK + Data byte received after slave address received, ACK transmitted + 128 + + + SDATA_RX_NACK + Data byte received after slave address received, NACK transmitted + 136 + + + DATA_RX_GC_ACK + Data byte received after general call address received, ACK transmitted + 144 + + + STOP_RSTART_RX + STOP or repeated START condition received in slave mode + 160 + + + SLAR_RX_ACK + Address and read bit received, ACK transmitted + 168 + + + ARB_LOST_SLAR_RX_ACK + Arbitration lost in address as master, address and read bit received, ACK transmitted + 176 + + + SDATA_TX_ACK + Data byte transmitted in slave mode, ACK received + 184 + + + SDATA_TX_NACK + Data byte transmitted in slave mode, NACK received + 192 + + + SDATA_LAST_TX_ACK + Last data byte transmitted in slave mode, ACK received + 200 + + + SDATA_LAST_TX_NACK + Last data byte transmitted in slave mode, NACK received + 208 + + + SECOND_ADDR_TX_ACK + Second address byte received in slave mode, ACK transmitted + 224 + + + SECOND_ADDR_TX_NACK + Second address byte received in slave mode, NACK transmitted + 240 + + + NO_INFO + No relevant status information + 248 + + + + + + + DAT + I2C Data + 0xC + + + DATA + Data values received or to be transmitted + 0 + 8 + read-write + + + + + CLK + I2C Clock Control + 0x10 + + + N + Fscl = PCLK / (2^M * (N+1) * 10) + 0 + 4 + read-write + + + M + Fsamp = PCLK / 2^M + 4 + 3 + read-write + + + + + ADR0 + I2C Slave Address 0 + 0x14 + + + GC + General Call Enable + 0 + 1 + read-write + + + ADDR + Slave Address + 1 + 7 + read-write + + + + + ADRM0 + I2C Slave Address Mask 0 + 0x18 + + + MASK + Slave Address Mask + 1 + 7 + read-write + + + + + XADR0 + I2C Extended Slave Address 0 + 0x1C + + + ADDR + Extended Slave Address + 1 + 10 + read-write + + + + + XADRM0 + I2C Extended Slave Address Mask 0 + 0x20 + + + MASK + Extended Slave Address Mask + 1 + 10 + read-write + + + + + RST + I2C Software Reset + 0x24 + + + RST + I2C Software Reset + 0 + 8 + read-write + + RST + read-write + + RESET + Perform I2C software reset + 7 + + + + + + + ADR1 + I2C Slave Address 1 + 0x28 + + + GC + General Call Enable + 0 + 1 + read-write + + + ADDR + Slave Address + 1 + 7 + read-write + + + + + ADRM1 + I2C Slave Address Mask 1 + 0x2C + + + MASK + Slave Address Mask + 1 + 7 + read-write + + + + + ADR2 + I2C Slave Address 2 + 0x30 + + + GC + General Call Enable + 0 + 1 + read-write + + + ADDR + Slave Address + 1 + 7 + read-write + + + + + ADRM2 + I2C Slave Address Mask 2 + 0x34 + + + MASK + Slave Address Mask + 1 + 7 + read-write + + + + + ADR3 + I2C Slave Address 3 + 0x38 + + + GC + General Call Enable + 0 + 1 + read-write + + + ADDR + Slave Address + 1 + 7 + read-write + + + + + ADRM3 + I2C Slave Address Mask 3 + 0x3C + + + MASK + Slave Address Mask + 1 + 7 + read-write + + + + + + + USARTA + Universal Synchronous Asynchronous Receive Transmit A + 0x40020000 + USART + + 0x0 + 0x10000 + registers + + + USARTA_SSPA + USART/SSP A Interrupt + 23 + + + + RBR + UART A Receive Buffer + 0x0 + + + RBR + Oldest received character in the UART RX FIFO + 0 + 8 + read-only + + + + + THR + UART A Transmit Holding + 0x4 + + + THR + Place a character in the UART TX FIFO + 0 + 8 + write-only + + + + + DLR + UART A Divisor Latch + 0x8 + + + DLR + Divisor Latch Register (Baudrate = PCLK / (16 * DLR)) + 0 + 16 + read-write + + + + + IER + UART A Interrupt Enable + 0xC + + + RBRIE + Enable the UART RX Buffer Full Interrupt + 0 + 1 + read-write + + + THREIE + Enable the UART TX Holding Register Empty Interrupt + 1 + 1 + read-write + + + RLSIE + Enable the UART RX Line Status Interrupt + 2 + 1 + read-write + + + + + IIR + UART A Interrupt Identification + 0x10 + + + INTSTATUS + Interrupt Status + 0 + 1 + read-only + + + INTID + Interrupt Identification + 1 + 3 + read-only + + INTID + read + + TX_HOLDING_REGISTER_EMPTY + TX Holding Register Empty + 1 + + + RX_DATA_AVAILABLE + Receive Data Available + 2 + + + RX_LINE_STATUS + Receive Line Status + 3 + + + RX_FIFO_TIMEOUT + Receive FIFO Character Timeout + 6 + + + + + + + FCR + UART A FIFO Control + 0x14 + + + FIFOEN + FIFO Enable + 0 + 1 + read-write + + + RXFIFORST + RX FIFO Reset + 1 + 1 + read-write + + + TXFIFORST + TX FIFO Reset + 2 + 1 + read-write + + + TXTL + TX FIFO Trigger Level + 4 + 2 + read-write + + RXTL + read-write + + FIFO1 + 1 character + 0 + + + FIFO4 + 4 characters + 1 + + + FIFO8 + 8 characters + 2 + + + FIFO14 + 14 characters + 3 + + + + + RXTL + RX FIFO Trigger Level + 6 + 2 + read-write + + RXTL + read-write + + FIFO1 + 1 character + 0 + + + FIFO4 + 4 characters + 1 + + + FIFO8 + 8 characters + 2 + + + FIFO14 + 14 characters + 3 + + + + + + + LCR + UART A Line Control + 0x18 + + + WLS + Word Length Select + 0 + 2 + read-write + + WLS + read-write + + WL5 + 5 bits + 0 + + + WL6 + 6 bits + 1 + + + WL7 + 7 bits + 2 + + + WL8 + 8 bits + 3 + + + + + SBS + Stop Bit Select + 2 + 1 + read-write + + SBS + read-write + + ONE + 1 stop bit + 0 + + + TWO + 2 stop bits (1.5 if LCR.WLS = 0) + 1 + + + + + PEN + Parity Enable + 3 + 1 + read-write + + + PSEL + Parity Select + 4 + 2 + read-write + + PSEL + read-write + + ODD_PARITY + Odd parity + 0 + + + EVEN_PARITY + Even parity + 1 + + + FORCED_1_STICKY_PARITY + Forced 1 sticky parity + 2 + + + FORCED_0_STICKY_PARITY + Forced 0 sticky parity + 3 + + + + + BCON + Break Control + 6 + 1 + read-write + + + + + LSR + UART A Line Status + 0x20 + + + RDR + Receiver Data Ready + 0 + 1 + read-only + + + OE + Overrun Error + 1 + 1 + read-only + + + PE + Parity Error + 2 + 1 + read-only + + + FE + Framing Error + 3 + 1 + read-only + + + BI + Break Interrupt + 4 + 1 + read-only + + + THRE + Transmitter Holding Register Empty + 5 + 1 + read-only + + + TEMT + Transmitter Empty + 6 + 1 + read-only + + + RXFE + Error in RX FIFO + 7 + 1 + read-only + + + + + SCR + UART A Scratch Pad + 0x28 + + + PAD + Readable/writable byte + 0 + 8 + read-write + + + + + EFR + Enhanced Feature + 0x2C + + + ERFEN + Enable Enhanced Mode + 4 + 1 + read-write + + + + + + + USARTB + USART + Universal Synchronous Asynchronous Receive Transmit B + 0x40030000 + + USARTB_SSPB + USART/SSP B Interrupt + 24 + + + + USARTC + Universal Synchronous Asynchronous Receive Transmit C + 0x40040000 + + USARTC_SSPC + USART/SSP C Interrupt + 25 + + + + USARTD + USART + 0x40050000 + + USARTD_SSPD + USART/SSP D Interrupt + 26 + + + + SSPA + Synchronous Serial Peripheral A + 0x40020000 + SSP + USARTA + + 0x0 + 0x10000 + registers + + + + CON + SSP Control Register + 0x0 + read-write + + + DSS + Data Size Select + 0 + 5 + read-write + + DSS + read-write + + BITS4 + 4-bit transfer + 3 + + + BITS5 + 5-bit transfer + 4 + + + BITS6 + 6-bit transfer + 5 + + + BITS7 + 7-bit transfer + 6 + + + BITS8 + 8-bit transfer + 7 + + + BITS9 + 9-bit transfer + 8 + + + BITS10 + 10-bit transfer + 9 + + + BITS11 + 11-bit transfer + 10 + + + BITS12 + 12-bit transfer + 11 + + + BITS13 + 13-bit transfer + 12 + + + BITS14 + 14-bit transfer + 13 + + + BITS15 + 15-bit transfer + 14 + + + BITS16 + 16-bit transfer + 15 + + + BITS17 + 17-bit transfer + 16 + + + BITS18 + 18-bit transfer + 17 + + + BITS19 + 19-bit transfer + 18 + + + BITS20 + 20-bit transfer + 19 + + + BITS21 + 21-bit transfer + 20 + + + BITS22 + 22-bit transfer + 21 + + + BITS23 + 23-bit transfer + 22 + + + BITS24 + 24-bit transfer + 23 + + + BITS25 + 25-bit transfer + 24 + + + BITS26 + 26-bit transfer + 25 + + + BITS27 + 27-bit transfer + 26 + + + BITS28 + 28-bit transfer + 27 + + + BITS29 + 29-bit transfer + 28 + + + BITS30 + 30-bit transfer + 29 + + + BITS31 + 31-bit transfer + 30 + + + BITS32 + 32-bit transfer + 31 + + + + + FRF + Frame Format + 5 + 2 + read-write + + FRF + read-write + + SPI + SPI (Motorola) + 0 + + + TI + Synchronous Serial Format (TI) + 1 + + + MICROWIRE + Microwire (National Semiconductor) + 2 + + + + + CPO + Clock Out Polarity + 7 + 1 + read-write + + CPO + read-write + + ACTIVE_HIGH + Active High + 0 + + + ACTIVE_LOW + Active Low + 1 + + + + + CPH + Clock Phase + 8 + 1 + read-write + + CPH + read-write + + FIRST_EDGE + First edge + 0 + + + SECOND_EDGE + Second edge + 1 + + + + + SOD + Slave Output Disable + 9 + 1 + read-write + + + MS + Master/Slave Mode + 10 + 1 + read-write + + MS + read-write + + MASTER + Master + 0 + + + SLAVE + Slave + 1 + + + + + SSPEN + SSP Enable + 11 + 1 + read-write + + + LBM + Loopback Mode + 12 + 1 + read-write + + + LSBFIRST + LSB First + 13 + 1 + read-write + + + + + STAT + SSP Status Register + 0x4 + read-only + + + TFE + Transmit FIFO Empty + 0 + 1 + read-only + + + TNF + Transmit FIFO Not Full + 1 + 1 + read-only + + + RNE + Receive FIFO Not Empty + 2 + 1 + read-only + + + RFF + Receive FIFO Full + 3 + 1 + read-only + + + BSY + Busy + 4 + 1 + read-only + + + + + DAT + SSP Data Register + 0x8 + read-write + + + DATA + Data + 0 + 32 + read-write + + + + + CLK + SSP Clock Register + 0xC + read-write + + + N + N Value + 0 + 8 + read-write + + + 2 + 254 + + + + + M + M Value + 8 + 8 + read-write + + + + + IMSC + SSP Interrupt Mask Set/Clear Register + 0x10 + read-write + + + RORIM + Receive Overrun Interrupt Mask + 0 + 1 + read-write + + + RTIM + Receive Timeout Interrupt Mask + 1 + 1 + read-write + + + RXIM + Receive FIFO Interrupt Mask + 2 + 1 + read-write + + + TXIM + Transmit FIFO Interrupt Mask + 3 + 1 + read-write + + + + + RIS + SSP Raw Interrupt Status Register + 0x14 + read-only + + + RORRIS + Receive Overrun Raw Interrupt Status + 0 + 1 + read-only + + + RTRIS + Receive Timeout Raw Interrupt Status + 1 + 1 + read-only + + + RXRIS + Receive FIFO Raw Interrupt Status + 2 + 1 + read-only + + + TXRIS + Transmit FIFO Raw Interrupt Status + 3 + 1 + read-only + + + + + MIS + SSP Masked Interrupt Status Register + 0x18 + read-only + + + RORMIS + Receive Overrun Masked Interrupt Status + 0 + 1 + read-only + + + RTMIS + Receive Timeout Masked Interrupt Status + 1 + 1 + read-only + + + RXMIS + Receive FIFO Masked Interrupt Status + 2 + 1 + read-only + + + TXMIS + Transmit FIFO Masked Interrupt Status + 3 + 1 + read-only + + + + + CLR + SSP Interrupt Clear Register + 0x1C + write-only + + + ROIC + Receive FIFO Overrun Interrupt Clear + 0 + 1 + write-only + + + RTIC + Receive FIFO Timeout Interrupt Clear + 1 + 1 + write-only + + + + + SSCR + SSP Slave Select Control Register + 0x28 + read-write + + + SELSS + Slave Select + 0 + 2 + read-write + + SELSS + read-write + + SS_ENABLED + Slave Select Enabled + 0 + + + + + SWSEL + Slave Select Software Control + 2 + 1 + read-write + + + SWSS + Slave Select State + 3 + 1 + read-write + + + SPHDONTCARE + Slave Select Pull-high + 4 + 1 + read-write + + SPHDONTCARE + read-write + + NO_PULL_HIGH + SS cannot be pulled high after transfer + 0 + + + PULL_HIGH + SS must be pulled high after transfer + 1 + + + + + + + + + SSPB + Synchronous Serial Peripheral B + 0x40030000 + USARTB + + + SSPC + Synchronous Serial Peripheral C + 0x40040000 + USARTC + + + SSPD + Synchronous Serial Peripheral D + 0x40050000 + USARTD + + + TIMERA + Timer A + 0x40060000 + TIMER + + 0x0 + 0x10000 + registers + + + TIMERA + Timer A Interrupt + 7 + + + TIMERAQEP + Timer A QEP Interrupt + 11 + + + + CTL + Timer Control + 0x0 + 0x20 + read-write + 0x00000000 + + + MODE + Timer Mode + 0 + 2 + read-write + + TIMERMODE + read-write + + DISABLED + Disabled + 0 + + + UP + Up mode + 1 + + + UP_DOWN + Up/Down mode + 2 + + + ASYMMETRIC + Asymmetric mode + 3 + + + + + PRDLATCH + Timer Period Latch Mode + 2 + 2 + read-write + + PRDLATCH + read-write + + CTR_0 + Period is latched when CTR = 0 + 0 + + + CTR_PERIOD + Period is latched when CTR = Period (PRD) + 1 + + + IMMEDIATE + Period is latched immediately upon register write + 2 + + + + + SSYNC + Timer Slave Synchronization + 4 + 1 + read-write + + + SINGLE + Single Shot Timer + 5 + 1 + read-write + + + CLKDIV + Timer Input Clock Divider + 6 + 3 + read-write + + + DIV1 + Timer input clock /1 + 0 + + + DIV2 + Timer input clock /2 + 1 + + + DIV4 + Timer input clock /4 + 2 + + + DIV8 + Timer input clock /8 + 3 + + + DIV16 + Timer input clock /16 + 4 + + + DIV32 + Timer input clock /32 + 5 + + + DIV64 + Timer input clock /64 + 6 + + + DIV128 + Timer input clock /128 + 7 + + + + + CLKSRC + Timer Clock Source + 9 + 1 + read-write + + + PCLK + PCLK selected as input to timer + 0 + + + ACLK + ACLK selected as input to timer + 1 + + + + + DTGCLK + Dead-Time Generator Clock Source + 10 + 1 + read-write + + + BEFORE_DIV + Before input clock divider + 0 + + + AFTER_DIV + After input clock divider + 1 + + + + + LATCH + Write 1 to Latch Period and all CCTRs + 11 + 1 + read-write + + + CLR + Timer Clear + 12 + 1 + read-write + + + BASEIE + Base timer interrupt enable + 13 + 1 + read-write + + + + + INT + Timer Interrupt Control + 0x4 + + + CCR0IF + CCR 0 Interrupt Flag + 0 + 1 + write-only + + + CCR1IF + CCR 1 Interrupt Flag + 1 + 1 + write-only + + + CCR2IF + CCR 2 Interrupt Flag + 2 + 1 + write-only + + + CCR3IF + CCR 3 Interrupt Flag + 3 + 1 + write-only + + + CCR4IF + CCR 4 Interrupt Flag + 4 + 1 + write-only + + + CCR5IF + CCR 5 Interrupt Flag + 5 + 1 + write-only + + + CCR6IF + CCR 6 Interrupt Flag + 6 + 1 + write-only + + + CCR7IF + CCR 7 Interrupt Flag + 7 + 1 + write-only + + + BASEIF + Base Timer Interrupt Flag + 8 + 1 + write-only + + + + + PRD + Timer Period + 0x8 + + + PRD + Timer Period Value + 0 + 16 + read-write + + + + + CTR + Timer Counter + 0xC + + + COUNTER + Timer Counter Value + 0 + 16 + read-write + + + + + CCTL0 + Timer CCR Control + 0x100 + 0x20 + read-write + 0x00000000 + + + CCMODE + CCR Mode + 0 + 1 + read-write + + CCMODE + read-write + + COMPARE + Compare Mode + 0 + + + CAPTURE + Capture Mode + 1 + + + + + CCINTEN + CCR Interrupt Enable + 1 + 1 + read-write + + + CCINTEDGE + Capture Mode Interrupt Edge Setting + 2 + 2 + read-write + + CCINTEDGE + read-write + + RISING + Rising Edge Interrupt + 0 + + + FALLING + Falling Edge Interrupt + 1 + + + BOTH + Rising and Falling Edge Interrupt + 2 + + + + + CCOUTINV + Invert CCR Output + 4 + 1 + read-write + + + CCLATCH + CCR Register Latch Mode + 5 + 2 + read-write + + CCLATCH + read-write + + CTR_ZERO_OR_RISING_EDGE + Compare(latch on CTR=0)/ Capture(latch on rising edge) + 0 + + + CTR_PERIOD_OR_FALLING_EDGE + Compare(latch on CTR=Period)/ Capture(latch on falling edge) + 1 + + + IMMEDIATE_OR_BOTH_EDGES + Compare(latch immediately)/ Capture(latch on both edges) + 2 + + + + + CCFORCE + Write 1 to force compare event (self-clearing) + 7 + 1 + read-write + + + CCINTSKIP + CC Interrupt Skip Counter + 8 + 4 + read-write + + CCINTSKIP + read-write + + NONE + Don't skip CCR matches before interrupt + 0 + + + SKIP1 + Skip 1 CCR match before interrupt + 1 + + + SKIP2 + Skip 2 CCR matches before interrupt + 2 + + + SKIP3 + Skip 3 CCR matches before interrupt + 3 + + + SKIP4 + Skip 4 CCR matches before interrupt + 4 + + + SKIP5 + Skip 5 CCR matches before interrupt + 5 + + + SKIP6 + Skip 6 CCR matches before interrupt + 6 + + + SKIP7 + Skip 7 CCR matches before interrupt + 7 + + + SKIP8 + Skip 8 CCR matches before interrupt + 8 + + + SKIP9 + Skip 9 CCR matches before interrupt + 9 + + + SKIP10 + Skip 10 CCR matches before interrupt + 10 + + + SKIP11 + Skip 11 CCR matches before interrupt + 11 + + + SKIP12 + Skip 12 CCR matches before interrupt + 12 + + + SKIP13 + Skip 13 CCR matches before interrupt + 13 + + + SKIP14 + Skip 14 CCR matches before interrupt + 14 + + + SKIP15 + Skip 15 CCR matches before interrupt + 15 + + + + + + + CCTR0 + Timer CCR Counter + 0x104 + + + CTR + Capture/Compare value + 0 + 16 + read-write + + + DELAY + Delay count to use before compare events + 16 + 16 + read-write + + + + + CCTL1 + Timer CCR Control 1 + 0x108 + 0x20 + read-write + 0x00000000 + + + CCMODE + CCR Mode + 0 + 1 + read-write + + + + CCINTEN + CCR Interrupt Enable + 1 + 1 + read-write + + + CCINTEDGE + Capture Mode Interrupt Edge Setting + 2 + 2 + read-write + + + + CCOUTINV + Invert CCR Output + 4 + 1 + read-write + + + CCLATCH + CCR Register Latch Mode + 5 + 2 + read-write + + + + CCFORCE + Write 1 to force compare event (self-clearing) + 7 + 1 + read-write + + + CCINTSKIP + CC Interrupt Skip Counter + 8 + 4 + read-write + + + + + + CCTR1 + Timer CCR Counter 1 + 0x10C + + + CTR + Capture/Compare Value + 0 + 16 + read-write + + + DELAY + Delay count to use before compare events + 16 + 16 + read-write + + + + + CCTL2 + Timer CCR Control 2 + 0x110 + 0x20 + read-write + 0x00000000 + + + CCMODE + CCR Mode + 0 + 1 + read-write + + + + CCINTEN + CCR Interrupt Enable + 1 + 1 + read-write + + + CCINTEDGE + Capture Mode Interrupt Edge Setting + 2 + 2 + read-write + + + + CCOUTINV + Invert CCR Output + 4 + 1 + read-write + + + CCLATCH + CCR Register Latch Mode + 5 + 2 + read-write + + + + CCFORCE + Write 1 to force compare event (self-clearing) + 7 + 1 + read-write + + + CCINTSKIP + CC Interrupt Skip Counter + 8 + 4 + read-write + + + + + + CCTR2 + Timer CCR Counter 2 + 0x114 + + + CTR + Capture/Compare Value + 0 + 16 + read-write + + + DELAY + Delay count to use before compare events + 16 + 16 + read-write + + + + + CCTL3 + Timer CCR Control 3 + 0x118 + 0x20 + read-write + 0x00000000 + + + CCMODE + CCR Mode + 0 + 1 + read-write + + + + CCINTEN + CCR Interrupt Enable + 1 + 1 + read-write + + + CCINTEDGE + Capture Mode Interrupt Edge Setting + 2 + 2 + read-write + + + + CCOUTINV + Invert CCR Output + 4 + 1 + read-write + + + CCLATCH + CCR Register Latch Mode + 5 + 2 + read-write + + + + CCFORCE + Write 1 to force compare event (self-clearing) + 7 + 1 + read-write + + + CCINTSKIP + CC Interrupt Skip Counter + 8 + 4 + read-write + + + + + + CCTR3 + Timer CCR Counter 3 + 0x11C + + + CTR + Capture/Compare Value + 0 + 16 + read-write + + + DELAY + Delay count to use before compare events + 16 + 16 + read-write + + + + + CCTL4 + Timer CCR Control 4 + 0x120 + 0x20 + read-write + 0x00000000 + + + CCMODE + CCR Mode + 0 + 1 + read-write + + + + CCINTEN + CCR Interrupt Enable + 1 + 1 + read-write + + + CCINTEDGE + Capture Mode Interrupt Edge Setting + 2 + 2 + read-write + + + + CCOUTINV + Invert CCR Output + 4 + 1 + read-write + + + CCLATCH + CCR Register Latch Mode + 5 + 2 + read-write + + + + CCFORCE + Write 1 to force compare event (self-clearing) + 7 + 1 + read-write + + + CCINTSKIP + CC Interrupt Skip Counter + 8 + 4 + read-write + + + + + + CCTR4 + Timer CCR Counter 4 + 0x124 + + + CTR + Capture/Compare Value + 0 + 16 + read-write + + + DELAY + Delay count to use before compare events + 16 + 16 + read-write + + + + + CCTL5 + Timer CCR Control 5 + 0x128 + 0x20 + read-write + 0x00000000 + + + CCMODE + CCR Mode + 0 + 1 + read-write + + + + CCINTEN + CCR Interrupt Enable + 1 + 1 + read-write + + + CCINTEDGE + Capture Mode Interrupt Edge Setting + 2 + 2 + read-write + + + + CCOUTINV + Invert CCR Output + 4 + 1 + read-write + + + CCLATCH + CCR Register Latch Mode + 5 + 2 + read-write + + + + CCFORCE + Write 1 to force compare event (self-clearing) + 7 + 1 + read-write + + + CCINTSKIP + CC Interrupt Skip Counter + 8 + 4 + read-write + + + + + + CCTR5 + Timer CCR Counter 5 + 0x12C + + + CTR + Capture/Compare Value + 0 + 16 + read-write + + + DELAY + Delay count to use before compare events + 16 + 16 + read-write + + + + + CCTL6 + Timer CCR Control 6 + 0x130 + 0x20 + read-write + 0x00000000 + + + CCMODE + CCR Mode + 0 + 1 + read-write + + + + CCINTEN + CCR Interrupt Enable + 1 + 1 + read-write + + + CCINTEDGE + Capture Mode Interrupt Edge Setting + 2 + 2 + read-write + + + + CCOUTINV + Invert CCR Output + 4 + 1 + read-write + + + CCLATCH + CCR Register Latch Mode + 5 + 2 + read-write + + + + CCFORCE + Write 1 to force compare event (self-clearing) + 7 + 1 + read-write + + + CCINTSKIP + CC Interrupt Skip Counter + 8 + 4 + read-write + + + + + + CCTR6 + Timer CCR Counter 6 + 0x134 + + + CTR + Capture/Compare Value + 0 + 16 + read-write + + + DELAY + Delay count to use before compare events + 16 + 16 + read-write + + + + + CCTL7 + Timer CCR Control 7 + 0x138 + 0x20 + read-write + 0x00000000 + + + CCMODE + CCR Mode + 0 + 1 + read-write + + + + CCINTEN + CCR Interrupt Enable + 1 + 1 + read-write + + + CCINTEDGE + Capture Mode Interrupt Edge Setting + 2 + 2 + read-write + + + + CCOUTINV + Invert CCR Output + 4 + 1 + read-write + + + CCLATCH + CCR Register Latch Mode + 5 + 2 + read-write + + + + CCFORCE + Write 1 to force compare event (self-clearing) + 7 + 1 + read-write + + + CCINTSKIP + CC Interrupt Skip Counter + 8 + 4 + read-write + + + + + + CCTR7 + Timer CCR Counter 7 + 0x13C + + + CTR + Capture/Compare Value + 0 + 16 + read-write + + + DELAY + Delay count to use before compare events + 16 + 16 + read-write + + + + + DTGCTL0 + Timer Dead-Time Generator Control + 0x200 + + + RED + Rising edge delay + 0 + 12 + read-write + + + FED + Falling edge delay + 16 + 12 + read-write + + + DTEN + Dead-time generator enable + 31 + 1 + read-write + + + + + DTGCTL1 + Timer DTG Control 1 + 0x204 + + + RED + Rising edge delay + 0 + 12 + read-write + + + FED + Falling edge delay + 16 + 12 + read-write + + + DTEN + Dead-time generator enable + 31 + 1 + read-write + + + + + DTGCTL2 + Timer DTG Control 2 + 0x208 + + + RED + Rising edge delay + 0 + 12 + read-write + + + FED + Falling edge delay + 16 + 12 + read-write + + + DTEN + Dead-time generator enable + 31 + 1 + read-write + + + + + DTGCTL3 + Timer DTG Control 3 + 0x20C + + + RED + Rising edge delay + 0 + 12 + read-write + + + FED + Falling edge delay + 16 + 12 + read-write + + + DTEN + Dead-time generator enable + 31 + 1 + read-write + + + + + QEPCTL + Timer QEP Control + 0x300 + read-write + + + QEPEN + QEP Enable + 0 + 1 + read-write + + + CNTAB + Count on A/B + 1 + 1 + read-write + + + CNTEDGE + Count on edge + 2 + 1 + read-write + + + DIR + Motor direction + 3 + 1 + read-write + + + IDXRST + Index reset + 4 + 1 + read-write + + + CLKDIV + QEP input clock divider + 8 + 3 + read-write + + + + + QEPCTR + Timer QEP Counter + 0x304 + read-write + + + CTR + Counter value + 0 + 32 + read-write + + + + + QEPMAX + Timer QEP Maximum Counter + 0x308 + read-write + + + CTRMAX + Maximum Counter value + 0 + 32 + read-write + + + + + QEPIER + Timer QEP Interrupt Enable + 0x30C + read-write + + + DIRIE + Direction change interrupt enable + 0 + 1 + read-write + + + PHAIE + Phase A rising edge interrupt enable + 1 + 1 + read-write + + + PHBIE + Phase B rising edge interrupt enable + 2 + 1 + read-write + + + WRIE + Counter wrap interrupt enable + 3 + 1 + read-write + + + IDXEVIE + Index event interrupt enable + 4 + 1 + read-write + + + + + QEPIF + Timer QEP Interrupt Enable + 0x310 + read-write + + + DIRIF + Direction change interrupt flag + 0 + 1 + read-write + + + PHAIF + Phase A rising edge interrupt flag + 1 + 1 + read-write + + + PHBIF + Phase B rising edge interrupt flag + 2 + 1 + read-write + + + WRIF + Counter wrap interrupt flag + 3 + 1 + read-write + + + IDXEVIF + Index event interrupt flag + 4 + 1 + read-write + + + + + + + TIMERB + Timer B + 0x40070000 + + TIMERB + Timer B Interrupt + 8 + + + TIMERBQEP + Timer B QEP Interrupt + 12 + + + + TIMERC + Timer C + 0x40080000 + + TIMERC + Timer C Interrupt + 9 + + + TIMERCQEP + Timer C QEP Interrupt + 13 + + + + TIMERD + Timer D + 0x40090000 + + TIMERD + Timer D Interrupt + 10 + + + TIMERDQEP + Timer D QEP Interrupt + 14 + + + + CAN + Controller Area Network + 0x400A0000 + + 0x0 + 0x10000 + registers + + + CAN + CAN Interrupt + 27 + + + + MR_CMR_SR_ISR + CAN Mode Register/Command Register/Status Register/Interrupt Status or ACK Register + 0x0 + + + AFM + Hardware filter acceptance scheme + 0 + 1 + read-write + + + DUAL + Dual filter + 0 + + + SINGLE + Single filter + 1 + + + + + LOM + Listen-only mode + 1 + 1 + read-write + + + RM + Reset mode + 2 + 1 + read-write + + + AT + Abort Transmission + 9 + 1 + read-write + + + TR + Transmit request + 10 + 1 + read-write + + + BS + Bus Off Status + 16 + 1 + read-only + + + ES + Error Status + 17 + 1 + read-only + + + TS + Transmit Status + 18 + 1 + read-only + + + RS + Receive Status + 19 + 1 + read-only + + + TBS + Transmit Buffer Status + 20 + 1 + read-only + + + DSO + Data Overrun Status + 21 + 1 + read-only + + + RBS + Receive Buffer Status + 22 + 1 + read-only + + + DOI + Data Overrun Interrupt + 24 + 1 + read-write + + + BEI + Bus Error Interrupt + 25 + 1 + read-write + + + TI + Transmit Interrupt + 26 + 1 + read-write + + + RI + Receive Interrupt + 27 + 1 + read-write + + + EPI + Error Passive Interrupt + 28 + 1 + read-write + + + EWI + Error Warning Interrupt + 29 + 1 + read-write + + + ALI + Arbitration Lost Interrupt + 30 + 1 + read-write + + + + + IMR_RMC_BTR0_BTR1 + CAN Interrupt Mask Register/Receive Message Counter Register/Bus Timing 0 Register/Bus Timing 1 Register + 0x4 + read-write + + + DOIM + Data Overrun Interrupt Mask + 0 + 1 + read-write + + + BEIM + Bus Error Interrupt Mask + 1 + 1 + read-write + + + TIM + Transmit Interrupt Mask + 2 + 1 + read-write + + + RIM + Receive Interrupt Mask + 3 + 1 + read-write + + + EPIM + Error Passive Interrupt Mask + 4 + 1 + read-write + + + EWIM + Error Warning Interrupt Mask + 5 + 1 + read-write + + + ALIM + Arbitration Lost Interrupt Mask + 6 + 1 + read-write + + + RMC + Number of frames stored in the receive FIFO + 8 + 5 + read-only + + + BRP + Baud rate prescaler + 16 + 6 + read-write + + + SJW + Synchronization jump width + 22 + 2 + read-write + + + TSEG1 + Number of clock cycles per Time segment 1 + 24 + 4 + read-write + + + TSEG2 + Number of clock cycles per Time segment 2 + 28 + 3 + read-write + + + SAM + Number of bus level samples + 31 + 1 + read-write + + + ONE + One sample + 0 + + + THREE + Three samples + 1 + + + + + + + TXBUF + CAN Transmit Buffer register + 0x8 + + + TXBUF + Transmit buffer data + 0 + 32 + read-write + + + + + RXBUF + CAN Receive Buffer register + 0xC + + + RXBUF + Receive buffer data + 0 + 32 + read-only + + + + + ACR + CAN Acceptance Code register + 0x10 + + + ACR + Acceptance code + 0 + 32 + read-write + + + + + AMR + CAN Acceptance Mask register + 0x14 + + + AMR + Acceptance code mask + 0 + 32 + read-write + + + + + ECC_RXERR_TXERR_ALC + CAN Error Code Capture register/Receive Error Counter Register/Transmit Error Counter Register/Arbitration Lost Code Capture Register + 0x18 + read-only + + + BER + Bit error occurred + 0 + 1 + read-only + + + STFER + Stuff error occurred + 1 + 1 + read-only + + + CRCER + CRC error occurred + 2 + 1 + read-only + + + FRMER + Form error occurred + 3 + 1 + read-only + + + ACKER + Acknowledge error occurred + 4 + 1 + read-only + + + EDIR + Direction of transfer while error occurred + 5 + 1 + read-only + + + TX + Transmission + 0 + + + RX + Reception + 1 + + + + + TXWRN + Set when CANTXERR is major or equal to 96 + 6 + 1 + read-only + + + RXWRN + Set when CANRXERR is major or equal to 96 + 7 + 1 + read-only + + + RXERR + Receive error counter + 8 + 8 + read-only + + + TXERR + Transmit error counter + 16 + 8 + read-only + + + ALC + Arbitration lost capture + 24 + 5 + read-only + + + ID28_10 + Arbitration lost in ID28/10 + 0 + + + ID28_9 + Arbitration lost in ID28/9 + 1 + + + ID28_8 + Arbitration lost in ID28/8 + 2 + + + ID28_7 + Arbitration lost in ID28/7 + 3 + + + ID28_6 + Arbitration lost in ID28/6 + 4 + + + ID28_5 + Arbitration lost in ID28/5 + 5 + + + ID28_4 + Arbitration lost in ID28/4 + 6 + + + ID28_3 + Arbitration lost in ID28/3 + 7 + + + ID28_2 + Arbitration lost in ID28/2 + 8 + + + ID28_1 + Arbitration lost in ID28/1 + 9 + + + ID28_0 + Arbitration lost in ID28/0 + 10 + + + SRR_RTR + Arbitration lost in SRR/RTR + 11 + + + IDE + Arbitration lost in IDE bit + 12 + + + ID_17_24 + Arbitration lost in ID17^24 + 13 + + + ID_16_14 + Arbitration lost in ID16^24 + 14 + + + ID_15_24 + Arbitration lost in ID15^24 + 15 + + + ID_14_24 + Arbitration lost in ID14^24 + 16 + + + ID_13_24 + Arbitration lost in ID13^24 + 17 + + + ID_12_24 + Arbitration lost in ID12^24 + 18 + + + ID_11_24 + Arbitration lost in ID11^24 + 19 + + + ID_10_24 + Arbitration lost in ID10^24 + 20 + + + ID_9_24 + Arbitration lost in ID9^24 + 21 + + + ID_8_24 + Arbitration lost in ID8^24 + 22 + + + ID_7_24 + Arbitration lost in ID7^24 + 23 + + + ID_6_24 + Arbitration lost in ID6^24 + 24 + + + ID_5_24 + Arbitration lost in ID5^24 + 25 + + + ID_4_24 + Arbitration lost in ID4^24 + 26 + + + ID_3_24 + Arbitration lost in ID3^24 + 27 + + + ID_2_24 + Arbitration lost in ID2^24 + 28 + + + ID_1_24 + Arbitration lost in ID1^24 + 29 + + + ID_0_24 + Arbitration lost in ID0^24 + 30 + + + RTR + Arbitration lost in RTR + 31 + + + + + + + + + GPTIMERA + General Purpose Timer A + 0x400B0000 + GPTIMER + + 0x0 + 0x10000 + registers + + + GPTIMERA + GPTimer A Interrupt + 28 + + + + CTL + GPTimer Control + 0x0 + + + EN + Enable + 0 + 1 + read-write + + + IE + Interrupt Enable + 1 + 1 + read-write + + + IF + Interrupt Flag + 2 + 1 + + + DIV + Clock Divider + 3 + 4 + read-write + + DIV + read-write + + PCLK1 + PCLK/1 + 0 + + + PCLK2 + PCLK/2 + 1 + + + PCLK4 + PCLK/4 + 2 + + + PCLK8 + PCLK/8 + 3 + + + PCLK16 + PCLK/16 + 4 + + + PCLK32 + PCLK/32 + 5 + + + PCLK64 + PCLK/64 + 6 + + + PCLK128 + PCLK/128 + 7 + + + PCLK256 + PCLK/256 + 8 + + + PCLK512 + PCLK/512 + 9 + + + PCLK1024 + PCLK/1024 + 10 + + + PCLK2048 + PCLK/2048 + 11 + + + PCLK4096 + PCLK/4096 + 12 + + + PCLK8192 + PCLK/8192 + 13 + + + PCLK16384 + PCLK/16384 + 14 + + + PCLK32768 + PCLK/32768 + 15 + + + + + CDV + Count-down value + 8 + 24 + read-write + + + + + CTR + GPTimer Counter + 0x4 + + + CTR + Counter value + 0 + 24 + read-write + + + + + + + GPTIMERB + General Purpose Timer B + 0x400C0000 + + GPTIMERB + GPTimer B Interrupt + 29 + + + + MEMCTL + Memory Controller + 0x400D0000 + + 0x0 + 0x400 + registers + + + MEMCTL + MEMCTL Interrupt + 0 + + + + MEMCTL + Memory Controller Configuration + 0x0 + 0x20 + read-write + + + WSTATE + FLASH Access Wait States + 0 + 4 + read-write + + + MCLKDIV + MCLK Divider + 4 + 4 + read-write + + + DIV1 + /1 + 0 + + + DIV2 + /2 + 1 + + + DIV3 + /3 + 2 + + + DIV4 + /4 + 3 + + + DIV5 + /5 + 4 + + + DIV6 + /6 + 5 + + + DIV7 + /7 + 6 + + + DIV8 + /8 + 7 + + + DIV9 + /9 + 8 + + + DIV10 + /10 + 9 + + + DIV11 + /11 + 10 + + + DIV12 + /12 + 11 + + + DIV13 + /13 + 12 + + + DIV14 + /14 + 13 + + + DIV15 + /15 + 14 + + + DIV16 + /16 + 15 + + + + + WRITEWORDCNT + Write Word Data Count + 8 + 2 + read-write + + + SEIE + ECC Single bit Error Interrupt Enable + 16 + 1 + read-write + + + DEIE + ECC Dual bit Error Interrupt Enable + 17 + 1 + read-write + + + INVADDRIE + Invalid Memory Address Access Interrupt Enable + 18 + 1 + read-write + + + STDBY + FLASH Standby Mode + 19 + 1 + read-write + + + ECCDIS + SRAM ECC Disable + 20 + 1 + read-write + + + CACHEDIS + FLASH Read Cache Disable + 21 + 1 + read-write + + + MCLKSEL + MCLK Mux Select + 22 + 1 + read-write + + + ROSCCLK + ROSCCLK as MCLK + 0 + + + MCLK + HCLK/MCLKDIV as MCLK + 1 + + + + + + + MEMSTATUS + Memory Controller Status + 0x4 + 0x20 + read-write + + + WBUSY + FLASH Write Busy + 0 + 1 + read-write + + + EBUSY + FLASH Erase Busy + 1 + 1 + read-write + + + WRITEWORDCNT + Number of bytes written to FLASH for the write data buffer + 8 + 2 + read-write + + + BYTES4 + 4 bytes + 0 + + + BYTES8 + 8 bytes + 1 + + + BYTES12 + 12 bytes + 2 + + + BYTES16 + 16 bytes + 3 + + + + + SE + ECC Single bit Error Detection Flag + 16 + 1 + read-write + + + DE + ECC Dual bit Error Detection Flag + 17 + 1 + read-write + + + INVADDR + Invalid Memory Address Access Flag + 18 + 1 + read-write + + + + + FLASHLOCK + FLASH Lock Access + 0x8 + + + FLASHLOCK + Flash Lock Value for Memory Controller Operations + 0 + 32 + read-write + + FLASHLOCK + read-write + + RESET + Reset value + 0 + + + ALLOW_WRITE_ERASE_FLASH + Allow write and erase operations + 1138693130 + + + ALLOW_WRITE_INFO2SWDFUSE + Allow write to INFO2.SWDFUSE register + 2041902946 + + + ALLOW_WRITE_MEMCTL + Allow write to MEMCTRL register + 3574838416 + + + + + + + FLASHPAGE + FLASH Page + 0xC + + + PAGE + Flash page selection + 0 + 7 + read-write + + + + + SWDUNLOCK + SWD Unlock + 0x10 + + + KEY_SWDUNLOCK + Key for SWD unlock + 0 + 32 + write-only + + + + + FLASHERASE + FLASH Erase + 0x20 + + + KEY + Key for erase operations + 0 + 32 + read-write + + FLASHLOCK + read-write + + PAGE_ERASE + Page erase + 2356780199 + + + MASS_PAGE_ERASE + Mass page erase + 166622921 + + + INFO_3_ERASE + INFO-3 Erase + 308739909 + + + + + + + + + SCC + System and Clock Control + 0x400D0400 + read-write + + 0x0 + 0x400 + registers + + + SCC + SCC Interrupt + 30 + + + + CCSCTL + Configuration + 0x0 + 0x20 + read-write + + + FRCLKMUXSEL + FRCLK MUX Select + 0 + 2 + read-write + + + ROSC + ROSC selected as input to FRCLK + 0 + + + CLKREF + CLKREF selected as input to FRCLK + 1 + + + EXTCLK + External Clock selected as input to FRCLK + 3 + + + + + ROSCEN + ROSC Enable + 2 + 1 + read-write + + + SCLKMUXSEL + SCLK Mux Select + 4 + 1 + read-write + + + FRCLK + FRCLK selected as input to SCLK + 0 + + + PLLCLK + PLLCLK selected as input to SCLK + 1 + + + + + CLKFAILEN + Clock Fail Enable + 5 + 1 + read-write + + + CLKFAILMUXSEL + Clock Fail Mux Select + 6 + 1 + read-write + + + FRCLK + FRCLK selected as input to Clock Fail + 0 + + + PLLCLK + PLLCLK selected as input to Clock Fail + 1 + + + + + CLKFAILIF + Clock Fail Interrupt Flag + 7 + 1 + read-write + + + LDOEN + 1.8V LDO Enable + 8 + 1 + read-write + + + SWRESET + Software Reset + 11 + 1 + read-write + + + PCLKEN + PCLK Enable + 12 + 1 + read-write + + + ACLKEN + ACLK Enable + 13 + 1 + read-write + + + ADCLKEN + ADCCLK Enable + 14 + 1 + read-write + + + STCLKSLPEN + SysTick Clock Sleep Enable + 15 + 1 + read-write + + + PCLKDIV + PCLK Divider + 16 + 3 + read-write + + + HCLK1 + HCLK/1 + 0 + + + HCLK2 + HCLK/2 + 1 + + + HCLK3 + HCLK/3 + 2 + + + HCLK4 + HCLK/4 + 3 + + + HCLK5 + HCLK/5 + 4 + + + HCLK6 + HCLK/6 + 5 + + + HCLK7 + HCLK/7 + 6 + + + HCLK8 + HCLK/8 + 7 + + + + + ACLKDIV + ACLK Divider + 20 + 3 + read-write + + + SCLK1 + SCLK/1 + 0 + + + SCLK2 + SCLK/2 + 1 + + + SCLK3 + SCLK/3 + 2 + + + SCLK4 + SCLK/4 + 3 + + + SCLK5 + SCLK/5 + 4 + + + SCLK6 + SCLK/6 + 5 + + + SCLK7 + SCLK/7 + 6 + + + SCLK8 + SCLK/8 + 7 + + + + + HCLKDIV + HCLK Divider + 24 + 3 + read-write + + + SCLK1 + SCLK/1 + 0 + + + SCLK2 + SCLK/2 + 1 + + + SCLK3 + SCLK/3 + 2 + + + SCLK4 + SCLK/4 + 3 + + + SCLK5 + SCLK/5 + 4 + + + SCLK6 + SCLK/6 + 5 + + + SCLK7 + SCLK/7 + 6 + + + SCLK8 + SCLK/8 + 7 + + + + + USAMODE + USART A Mode + 28 + 1 + read-write + + USMODE + + SSP + SSP Mode + 0 + + + UART + UART Mode + 1 + + + + + USBMODE + USART B Mode + 29 + 1 + read-write + + + + USCMODE + USART C Mode + 30 + 1 + read-write + + + + USDMODE + USART D Mode + 31 + 1 + read-write + + + + + + CCSPLLCTL + PLL Configuration + 0x4 + read-write + + + PLLEN + PLL Enable + 0 + 1 + read-write + + + PLLBP + PLL Bypass + 1 + 1 + read-write + + + PLLOUTDIV + PLL Output Divider + 2 + 2 + read-write + + PLLOUTDIV + read-write + + DIV1 + /1 + 0 + + + DIV2 + /2 + 1 + + + DIV4 + /4 + 2 + + + DIV8 + /8 + 3 + + + + + PLLINDIV + PLL Input Divider + 4 + 4 + read-write + + + 1 + 15 + + + + + PLLFBDIV + PLL Feedback Divider + 8 + 14 + read-write + + + 4 + 16383 + + + + + PLLLOCK + PLL Lock Status + 24 + 1 + read-write + + + + + CCSROSCTRIM + ROSC Trim Configuration + 0x8 + 0x20 + read-write + + + TRIM + ROSC Trim Value + 0 + 7 + read-write + + + + + PAMUXSEL + PA Peripheral MUX Select + 0xC + 0x20 + read-write + 0x00000000 + + + PA0 + PA0 MUX Select + 0 + 3 + read-write + + + GPIOA0 + GPIO + 0 + + + + + PA1 + PA1 MUX Select + 4 + 3 + read-write + + + GPIOA1 + GPIO + 0 + + + EMUXD + EMUX Data + 1 + + + + + PA2 + PA2 MUX Select + 8 + 3 + read-write + + + GPIOA2 + GPIO + 0 + + + EMUXC + EMUX Clock + 1 + + + + + PA3 + PA3 MUX Select + 12 + 3 + read-write + + + GPIOA3 + GPIO + 0 + + + USASCLK + USART A SCLK + 1 + + + USBSCLK + USART B SCLK + 2 + + + + + PA4 + PA4 MUX Select + 16 + 3 + read-write + + + GPIOA4 + GPIO + 0 + + + USAMOSI + USART A MOSI/TX + 1 + + + USBMOSI + USART B MOSI/TX + 2 + + + + + PA5 + PA5 MUX Select + 20 + 3 + read-write + + + GPIOA5 + GPIO + 0 + + + USAMISO + USART A MISO/RX + 1 + + + USBMISO + USART B MISO/RX + 2 + + + + + PA6 + PA6 MUX Select + 24 + 3 + read-write + + + GPIOA6 + GPIO + 0 + + + USASS + USART A SPI Slave Select + 1 + + + USBSS + USART B SPI Slave Select + 2 + + + + + PA7 + PA7 MUX Select + 28 + 3 + read-write + + + GPIOA7 + GPIO + 0 + + + + + + + PBMUXSEL + PB Peripheral MUX Select + 0x10 + 0x20 + read-write + 0x00000000 + + + PB0 + PB0 MUX Select + 0 + 3 + read-write + + + GPIOB0 + GPIO + 0 + + + TAPWM0 + Timer A PWM0 + 1 + + + TBPWM0 + Timer B PWM0 + 2 + + + TCPWM0 + Timer C PWM0 + 4 + + + TDPWM0 + Timer D PWM0 + 5 + + + + + PB1 + PB1 MUX Select + 4 + 3 + read-write + + + GPIOB1 + GPIO + 0 + + + TAPWM1 + Timer A PWM1 + 1 + + + TBPWM1 + Timer B PWM1 + 2 + + + TCPWM1 + Timer C PWM1 + 4 + + + TDPWM1 + Timer D PWM1 + 5 + + + + + PB2 + PB2 MUX Select + 8 + 3 + read-write + + + GPIOB2 + GPIO + 0 + + + TAPWM2 + Timer A PWM2 + 1 + + + TBPWM2 + Timer B PWM2 + 2 + + + TCPWM2 + Timer C PWM2 + 4 + + + TDPWM2 + Timer D PWM2 + 5 + + + + + PB3 + PB3 MUX Select + 12 + 3 + read-write + + + GPIOB3 + GPIO + 0 + + + TAPWM3 + Timer A PWM3 + 1 + + + TBPWM3 + Timer B PWM3 + 2 + + + TCPWM3 + Timer C PWM3 + 4 + + + TDPWM3 + Timer D PWM3 + 5 + + + + + PB4 + PB4 MUX Select + 16 + 3 + read-write + + + GPIOB4 + GPIO + 0 + + + TAPWM4 + Timer A PWM4 + 1 + + + TBPWM4 + Timer B PWM4 + 2 + + + TCPWM0 + Timer C PWM0 + 3 + + + TCPWM4 + Timer C PWM4 + 4 + + + TDPWM4 + Timer D PWM4 + 5 + + + + + PB5 + PB5 MUX Select + 20 + 3 + read-write + + + GPIOB5 + GPIO + 0 + + + TAPWM5 + Timer A PWM5 + 1 + + + TBPWM5 + Timer B PWM5 + 2 + + + TCPWM1 + Timer C PWM1 + 3 + + + TCPWM5 + Timer C PWM5 + 4 + + + TDPWM5 + Timer D PWM5 + 5 + + + + + PB6 + PB6 MUX Select + 24 + 3 + read-write + + + GPIOB6 + GPIO + 0 + + + TAPWM6 + Timer A PWM6 + 1 + + + TBPWM6 + Timer B PWM6 + 2 + + + TCPWM2 + Timer C PWM2 + 3 + + + TCPWM6 + Timer C PWM6 + 4 + + + TDPWM6 + Timer D PWM6 + 5 + + + + + PB7 + PB7 MUX Select + 28 + 3 + read-write + + + GPIOB7 + GPIO + 0 + + + TAPWM7 + Timer A PWM7 + 1 + + + TBPWM7 + Timer B PWM7 + 2 + + + TCPWM3 + Timer C PWM3 + 3 + + + TCPWM7 + Timer C PWM7 + 4 + + + TDPWM7 + Timer D PWM7 + 5 + + + + + + + PCMUXSEL + PC Peripheral MUX Select + 0x14 + 0x20 + read-write + 0x00000000 + + + PC0 + PC0 MUX Select + 0 + 3 + read-write + + + GPIOC0 + GPIO + 0 + + + TBPWM0 + Timer B PWM0 + 1 + + + TCPWM0 + Timer C PWM0 + 2 + + + TBQEPIDX + Timer B QEP Index + 3 + + + USBMOSI + USART B MOSI/TX + 4 + + + USCSCLK + USART C SPI Clock + 5 + + + CANRXD + CAN Rx Data + 6 + + + I2CSCL + I2C SCL + 7 + + + + + PC1 + PC1 MUX Select + 4 + 3 + read-write + + + GPIOC1 + GPIO + 0 + + + TBPWM1 + Timer B PWM1 + 1 + + + TCPWM1 + Timer C PWM1 + 2 + + + TBQEPPHA + Timer B QEP Phase A + 3 + + + USBMISO + USART B MISO/RX + 4 + + + USCSS + USART C Slave Select + 5 + + + CANTXD + CAN Tx Data + 6 + + + I2CSDA + I2C SDA + 7 + + + + + PC2 + PC2 MUX Select + 8 + 3 + read-write + + + GPIOC2 + GPIO + 0 + + + TBPWM2 + Timer B PWM2 + 1 + + + TCPWM2 + Timer C PWM2 + 2 + + + TBQEPPHB + Timer B QEP Phase B + 3 + + + USBSCLK + USART B SCLK + 4 + + + USCMOSI + USART C MOSI/TX + 5 + + + EMUXD + EMUX Data + 7 + + + + + PC3 + PC3 MUX Select + 12 + 3 + read-write + + + GPIOC3 + GPIO + 0 + + + TBPWM3 + Timer B PWM3 + 1 + + + TCPWM3 + Timer C PWM3 + 2 + + + USBSS + USART B Slave Select + 4 + + + USCMISO + USART C MISO/RX + 5 + + + EMUXC + EMUX Clock + 7 + + + + + PC4 + PC4 MUX Select + 16 + 3 + read-write + + + GPIOC4 + GPIO + 0 + + + TBPWM4 + Timer B PWM4 + 1 + + + TCPWM4 + Timer C PWM4 + 2 + + + TCQEPIDX + Timer C QEP Index + 3 + + + USBMOSI + USART B MOSI/TX + 4 + + + USCSCLK + USART C SPI Clock + 5 + + + CANRXD + CAN Rx Data + 6 + + + I2CSCL + I2C SCL + 7 + + + + + PC5 + PC5 MUX Select + 20 + 3 + read-write + + + GPIOC5 + GPIO + 0 + + + TBPWM5 + Timer B PWM5 + 1 + + + TCPWM5 + Timer C PWM5 + 2 + + + TCQEPPHA + Timer C QEP Phase A + 3 + + + USBMISO + USART B MISO/RX + 4 + + + USCSS + USART C Slave Select + 5 + + + CANTXD + CAN Tx Data + 6 + + + I2CSDA + I2C SDA + 7 + + + + + PC6 + PC6 MUX Select + 24 + 3 + read-write + + + GPIOC6 + GPIO + 0 + + + TBPWM6 + Timer B PWM6 + 1 + + + TCPWM6 + Timer C PWM6 + 2 + + + TCQEPPHB + Timer C QEP Phase B + 3 + + + USBSCLK + USART B SCLK + 4 + + + USCMOSI + USART C MOSI/TX + 5 + + + EMUXD + EMUX Data + 7 + + + + + PC7 + PC7 MUX Select + 28 + 3 + read-write + + + GPIOC7 + GPIO + 0 + + + TBPWM7 + Timer B PWM7 + 1 + + + TCPWM7 + Timer C PWM7 + 2 + + + USBSS + USART B Slave Select + 4 + + + USCMISO + USART C MISO/RX + 5 + + + FRCLK + FRCLK Output + 6 + + + EMUXC + EMUX Clock + 7 + + + + + + + PDMUXSEL + PD Peripheral MUX Select + 0x18 + 0x20 + read-write + 0x00000000 + + + PD0 + PD0 MUX Select + 0 + 3 + read-write + + + GPIOD0 + GPIO + 0 + + + TBPWM0 + Timer B PWM0 + 1 + + + TCPWM0 + Timer C PWM0 + 2 + + + TDQEPIDX + Timer D QEP Index + 3 + + + USCSCLK + USART C SPI Clock + 5 + + + CANTXD + CAN Tx Data + 6 + + + EMUXD + EMUX Data + 7 + + + + + PD1 + PD1 MUX Select + 4 + 3 + read-write + + + GPIOD1 + GPIO + 0 + + + TBPWM1 + Timer B PWM1 + 1 + + + TCPWM1 + Timer C PWM1 + 2 + + + TDQEPPHA + Timer D QEP Phase A + 3 + + + USCSS + USART C Slave Select + 5 + + + CANRXD + CAN Rx Data + 6 + + + EMUXC + EMUX Clock + 7 + + + + + PD2 + PD2 MUX Select + 8 + 3 + read-write + + + GPIOD2 + GPIO + 0 + + + TBPWM2 + Timer B PWM2 + 1 + + + TCPWM2 + Timer C PWM2 + 2 + + + TDQEPPHB + Timer D QEP Phase B + 3 + + + USCMOSI + USART C MOSI/TX + 5 + + + + + PD3 + PD3 MUX Select + 12 + 3 + read-write + + + GPIOD3 + GPIO + 0 + + + TBPWM3 + Timer B PWM3 + 1 + + + TCPWM3 + Timer C PWM3 + 2 + + + USCMISO + USART C MISO/RX + 5 + + + FRCLK + FRCLK output + 6 + + + TRACED3 + TRACE Data 3 output + 7 + + + + + PD4 + PD4 MUX Select + 16 + 3 + read-write + + + GPIOD4 + GPIO + 0 + + + TBPWM4 + Timer B PWM4 + 1 + + + TCPWM4 + Timer C PWM4 + 2 + + + TDQEPIDX + Timer D QEP Index + 3 + + + TBQEPIDX + Timer B QEP Index + 4 + + + USDSCLK + USART D SPI Clock + 5 + + + TRACED3 + TRACE Data 3 output + 6 + + + USDMOSI + USART D MOSI/TX + 7 + + + + + PD5 + PD5 MUX Select + 20 + 3 + read-write + + + GPIOD5 + GPIO + 0 + + + TBPWM5 + Timer B PWM5 + 1 + + + TCPWM5 + Timer C PWM5 + 2 + + + TDQEPPHA + Timer D QEP Phase A + 3 + + + TDQEPPHB + Timer D QEP Phase B + 4 + + + USDSS + USART D Slave Select + 5 + + + CANRXD + CAN Rx Data + 6 + + + USDMISO + USART D MISO/RX + 7 + + + + + PD6 + PD6 MUX Select + 24 + 3 + read-write + + + GPIOD6 + GPIO + 0 + + + TBPWM6 + Timer B PWM6 + 1 + + + TCPWM6 + Timer C PWM6 + 2 + + + TDQEPPHB + Timer D QEP Phase B + 3 + + + TBQEPPHB + Timer B QEP Phase B + 4 + + + USDMOSI + USART D MOSI/TX + 5 + + + CANTXD + CAN Tx Data + 6 + + + I2CSDA + I2C SDA + 7 + + + + + PD7 + PD7 MUX Select + 28 + 3 + read-write + + + GPIOD7 + GPIO + 0 + + + TBPWM7 + Timer B PWM7 + 1 + + + TCPWM7 + Timer C PWM7 + 2 + + + USDMISO + USART C MISO/RX + 5 + + + CANRXD + CAN Rx Data + 6 + + + I2CSCL + I2C SCL + 7 + + + + + + + PEMUXSEL + PE Peripheral MUX Select + 0x1C + 0x20 + read-write + 0x00000000 + + + PE0 + PE0 MUX Select + 0 + 3 + read-write + + + GPIOE0 + GPIO + 0 + + + TCPWM4 + Timer C PWM4 + 1 + + + TDPWM0 + Timer D PWM0 + 2 + + + TAQEPIDX + Timer A QEP Index + 3 + + + TBQEPIDX + Timer B QEP Index + 4 + + + USCSCLK + USART C SPI Clock + 5 + + + I2CSCL + I2C SCL + 6 + + + EMUXC + EMUX Clock + 7 + + + + + PE1 + PE1 MUX Select + 4 + 3 + read-write + + + GPIOE1 + GPIO + 0 + + + TCPWM5 + Timer C PWM5 + 1 + + + TDPWM1 + Timer D PWM1 + 2 + + + TAQEPPHA + Timer A QEP Phase A + 3 + + + TBQEPPHA + Timer B QEP Phase A + 4 + + + USCSS + USART C Slave Select + 5 + + + I2CSDA + I2C SDA + 6 + + + EMUXD + EMUX Data + 7 + + + + + PE2 + PE2 MUX Select + 8 + 3 + read-write + + + GPIOE2 + GPIO + 0 + + + TCPWM6 + Timer C PWM6 + 1 + + + TDPWM2 + Timer D PWM2 + 2 + + + TAQEPPHB + Timer A QEP Phase B + 3 + + + TBQEPPHB + Timer B QEP Phase B + 4 + + + USCMOSI + USART C MOSI/TX + 5 + + + CANRXD + CAN Rx Data + 6 + + + EXTCLK + External clock input + 7 + + + + + PE3 + PE3 MUX Select + 12 + 3 + read-write + + + GPIOE3 + GPIO + 0 + + + TCPWM7 + Timer C PWM7 + 1 + + + TDPWM3 + Timer D PWM3 + 2 + + + FRCLK + FRCLK Output + 3 + + + USCMISO + USART C MISO/RX + 5 + + + CANTXD + CAN Tx Data + 6 + + + + + PE4 + PE4 MUX Select + 16 + 3 + read-write + + + GPIOE4 + GPIO + 0 + + + TCPWM4 + Timer C PWM4 + 1 + + + TDPWM4 + Timer D PWM4 + 2 + + + TDQEPIDX + Timer D QEP Index + 3 + + + USBSCLK + USART B SCLK + 4 + + + USDMOSI + USART D MOSI/TX + 5 + + + I2CSCL + I2C SCL + 6 + + + + + PE5 + PE5 MUX Select + 20 + 3 + read-write + + + GPIOE5 + GPIO + 0 + + + TCPWM5 + Timer C PWM5 + 1 + + + TDPWM5 + Timer D PWM5 + 2 + + + TDQEPPHA + Timer D QEP Phase A + 3 + + + USBSS + USART B Slave Select + 4 + + + USDMISO + USART D MISO/RX + 5 + + + I2CSDA + I2C SDA + 6 + + + + + PE6 + PE6 MUX Select + 24 + 3 + read-write + + + GPIOE6 + GPIO + 0 + + + TCPWM6 + Timer C PWM6 + 1 + + + TDPWM6 + Timer D PWM6 + 2 + + + TDQEPPHB + Timer D QEP Phase B + 3 + + + USBMOSI + USART B MOSI/TX + 4 + + + USDSCLK + USART D SCLK + 5 + + + CANRXD + CAN RX Data + 6 + + + + + PE7 + PE7 MUX Select + 28 + 3 + read-write + + + GPIOE7 + GPIO + 0 + + + TCPWM7 + Timer C PWM7 + 1 + + + TDPWM7 + Timer D PWM7 + 2 + + + USBMISO + USART B MISO/RX + 4 + + + USDSS + USART D Slave Select + 5 + + + CANTXD + CAN TX Data + 6 + + + + + + + PFMUXSEL + PF Peripheral MUX Select + 0x20 + 0x20 + read-write + 0x00000000 + + + PF0 + PF0 MUX Select + 0 + 3 + read-write + + + GPIOF0 + GPIO + 0 + + + TCPWM0 + Timer C PWM0 + 1 + + + TDPWM0 + Timer D PWM0 + 2 + + + TCK_SWDCLK + TCK/SWDCLK + 3 + + + TBQEPIDX + Timer B QEP Index + 4 + + + USBSCLK + USART B SPI Clock + 5 + + + TRACED2 + Trace Data 2 output + 6 + + + TRACECLK + Trace Clock + 7 + + + + + PF1 + PF1 MUX Select + 4 + 3 + read-write + + + GPIOF1 + GPIO + 0 + + + TCPWM1 + Timer C PWM1 + 1 + + + TDPWM1 + Timer D PWM1 + 2 + + + TMS_SWDIO + TMS/SWDIO + 3 + + + TBQEPPHA + Timer B QEP Phase A + 4 + + + USBSS + USART B Slave Select + 5 + + + TRACED1 + Trace Data 1 output + 6 + + + TRACED0 + Trace Data 0 output + 7 + + + + + PF2 + PF2 MUX Select + 8 + 3 + read-write + + + GPIOF2 + GPIO + 0 + + + TCPWM2 + Timer C PWM2 + 1 + + + TDPWM2 + Timer D PWM2 + 2 + + + TDI + Test Data In + 3 + + + TBQEPPHB + Timer B QEP Phase B + 4 + + + USBMOSI + USART B MOSI/TX + 5 + + + TRACED0 + Trace Data 0 output + 6 + + + TRACED1 + Trace Data 1 output + 7 + + + + + PF3 + PF3 MUX Select + 12 + 3 + read-write + + + GPIOF3 + GPIO + 0 + + + TCPWM3 + Timer C PWM3 + 1 + + + TDPWM3 + Timer D PWM3 + 2 + + + TDO + Test Data Out + 3 + + + FRCLK + FRCLK Output + 4 + + + USBMISO + USART B MISO/RX + 5 + + + TRACECLK + Trace Clock + 6 + + + TRACED2 + Trace Data 2 output + 7 + + + + + PF4 + PF4 MUX Select + 16 + 3 + read-write + + + GPIOF4 + GPIO + 0 + + + TCPWM4 + Timer C PWM4 + 1 + + + TDPWM4 + Timer D PWM4 + 2 + + + TCQEPIDX + Timer C QEP Index + 4 + + + USDSCLK + USART D SCLK + 5 + + + TRACED3 + Trace Data 3 output + 6 + + + EMUXC + EMUX Clock + 7 + + + + + PF5 + PF5 MUX Select + 20 + 3 + read-write + + + GPIOF5 + GPIO + 0 + + + TCPWM5 + Timer C PWM5 + 1 + + + TDPWM5 + Timer D PWM5 + 2 + + + TCQEPPHA + Timer C QEP Phase A + 4 + + + USDSS + USART D Slave Select + 5 + + + EMUXD + EMUX Data + 7 + + + + + PF6 + PF6 MUX Select + 24 + 3 + read-write + + + GPIOF6 + GPIO + 0 + + + TCPWM6 + Timer C PWM6 + 1 + + + TDPWM6 + Timer D PWM6 + 2 + + + TCQEPPHB + Timer C QEP Phase B + 4 + + + USDMOSI + USART D MOSI/TX + 5 + + + CANRXD + CAN RX Data + 6 + + + I2CSCL + I2C SCL + 7 + + + + + PF7 + PF7 MUX Select + 28 + 3 + read-write + + + GPIOF7 + GPIO + 0 + + + TCPWM7 + Timer C PWM7 + 1 + + + TDPWM7 + Timer D PWM7 + 2 + + + USDMISO + USART D MISO/RX + 5 + + + CANTXD + CAN TX Data + 6 + + + I2CSDA + I2C SDA + 7 + + + + + + + PGMUXSEL + PG Peripheral MUX Select + 0x24 + 0x20 + read-write + 0x00000000 + + + PG0 + PG0 MUX Select + 0 + 3 + read-write + + + GPIOG0 + GPIO + 0 + + + TCPWM0 + Timer C PWM0 + 1 + + + TDPWM0 + Timer D PWM0 + 2 + + + EMUXC + EMUX Clock + 3 + + + USDSCLK + USART D SPI Clock + 5 + + + TRACECLK + Trace Clock + 6 + + + TCQEPIDX + Timer C QEP Index + 7 + + + + + PG1 + PG1 MUX Select + 4 + 3 + read-write + + + GPIOG1 + GPIO + 0 + + + TCPWM1 + Timer C PWM1 + 1 + + + TDPWM1 + Timer D PWM1 + 2 + + + EMUXD + EMUX Data + 3 + + + USDSS + USART D Slave Select + 5 + + + TRACED0 + Trace Data 0 output + 6 + + + TCQEPPHA + Timer C QEP Phase A + 7 + + + + + PG2 + PG2 MUX Select + 8 + 3 + read-write + + + GPIOG2 + GPIO + 0 + + + TCPWM2 + Timer C PWM2 + 1 + + + TDPWM2 + Timer D PWM2 + 2 + + + FRCLK + FRCLK Output + 3 + + + USDMOSI + USART D MOSI/TX + 5 + + + TRACED1 + Trace Data 1 output + 6 + + + TCQEPPHB + Timer C QEP Phase B + 7 + + + + + PG3 + PG3 MUX Select + 12 + 3 + read-write + + + GPIOG3 + GPIO + 0 + + + TCPWM3 + Timer C PWM3 + 1 + + + TDPWM3 + Timer D PWM3 + 2 + + + USDMISO + USART D MISO/RX + 5 + + + TRACED2 + Trace Data 2 output + 6 + + + + + PG4 + PG4 MUX Select + 16 + 3 + read-write + + + GPIOG4 + GPIO + 0 + + + TCPWM4 + Timer C PWM4 + 1 + + + TDPWM4 + Timer D PWM4 + 2 + + + EMUXD + EMUX Data + 3 + + + I2CSCL + I2C SCL + 4 + + + USDSS + USART D Slave Select + 5 + + + TRACED3 + Trace Data 3 output + 6 + + + TDQEPIDX + Timer D QEP Index + 7 + + + + + PG5 + PG5 MUX Select + 20 + 3 + read-write + + + GPIOG5 + GPIO + 0 + + + TCPWM5 + Timer C PWM5 + 1 + + + TDPWM5 + Timer D PWM5 + 2 + + + EMUXC + EMUX Clock + 3 + + + USDMOSI + USART D MOSI/TX + 5 + + + CANRXD + CAN RX Data + 6 + + + TDQEPPHA + Timer D QEP Phase A + 7 + + + + + PG6 + PG6 MUX Select + 24 + 3 + read-write + + + GPIOG6 + GPIO + 0 + + + TCPWM6 + Timer C PWM6 + 1 + + + TDPWM6 + Timer D PWM6 + 2 + + + I2CSDA + I2C SDA + 3 + + + USDMISO + USART D MISO/RX + 5 + + + CANTXD + CAN TX Data + 6 + + + TDQEPPHB + Timer D QEP Phase B + 7 + + + + + PG7 + PG7 MUX Select + 28 + 3 + read-write + + + GPIOG7 + GPIO + 0 + + + TDQEPIDX + Timer D QEP Index + 2 + + + USDSCLK + USART D SPI Clock + 5 + + + + + + + PAPUEN + PA Weak Pull-up Enable + 0x28 + + + P0 + Pin 0 weak pull-up enabled + 0 + 1 + read-write + + + P1 + Pin 1 weak pull-up enabled + 1 + 1 + read-write + + + P2 + Pin 2 weak pull-up enabled + 2 + 1 + read-write + + + P3 + Pin 3 weak pull-up enabled + 3 + 1 + read-write + + + P4 + Pin 4 weak pull-up enabled + 4 + 1 + read-write + + + P5 + Pin 5 weak pull-up enabled + 5 + 1 + read-write + + + P6 + Pin 6 weak pull-up enabled + 6 + 1 + read-write + + + P7 + Pin 7 weak pull-up enabled + 7 + 1 + read-write + + + + + PBPUEN + PB Weak Pull-up Enable + 0x2C + + + P0 + Pin 0 weak pull-up enabled + 0 + 1 + read-write + + + P1 + Pin 1 weak pull-up enabled + 1 + 1 + read-write + + + P2 + Pin 2 weak pull-up enabled + 2 + 1 + read-write + + + P3 + Pin 3 weak pull-up enabled + 3 + 1 + read-write + + + P4 + Pin 4 weak pull-up enabled + 4 + 1 + read-write + + + P5 + Pin 5 weak pull-up enabled + 5 + 1 + read-write + + + P6 + Pin 6 weak pull-up enabled + 6 + 1 + read-write + + + P7 + Pin 7 weak pull-up enabled + 7 + 1 + read-write + + + + + PCPUEN + PC Weak Pull-up Enable + 0x30 + + + P0 + Pin 0 weak pull-up enabled + 0 + 1 + read-write + + + P1 + Pin 1 weak pull-up enabled + 1 + 1 + read-write + + + P2 + Pin 2 weak pull-up enabled + 2 + 1 + read-write + + + P3 + Pin 3 weak pull-up enabled + 3 + 1 + read-write + + + P4 + Pin 4 weak pull-up enabled + 4 + 1 + read-write + + + P5 + Pin 5 weak pull-up enabled + 5 + 1 + read-write + + + P6 + Pin 6 weak pull-up enabled + 6 + 1 + read-write + + + P7 + Pin 7 weak pull-up enabled + 7 + 1 + read-write + + + + + PDPUEN + PD Weak Pull-up Enable + 0x34 + + + P0 + Pin 0 weak pull-up enabled + 0 + 1 + read-write + + + P1 + Pin 1 weak pull-up enabled + 1 + 1 + read-write + + + P2 + Pin 2 weak pull-up enabled + 2 + 1 + read-write + + + P3 + Pin 3 weak pull-up enabled + 3 + 1 + read-write + + + P4 + Pin 4 weak pull-up enabled + 4 + 1 + read-write + + + P5 + Pin 5 weak pull-up enabled + 5 + 1 + read-write + + + P6 + Pin 6 weak pull-up enabled + 6 + 1 + read-write + + + P7 + Pin 7 weak pull-up enabled + 7 + 1 + read-write + + + + + PEPUEN + PE Weak Pull-up Enable + 0x38 + + + P0 + Pin 0 weak pull-up enabled + 0 + 1 + read-write + + + P1 + Pin 1 weak pull-up enabled + 1 + 1 + read-write + + + P2 + Pin 2 weak pull-up enabled + 2 + 1 + read-write + + + P3 + Pin 3 weak pull-up enabled + 3 + 1 + read-write + + + P4 + Pin 4 weak pull-up enabled + 4 + 1 + read-write + + + P5 + Pin 5 weak pull-up enabled + 5 + 1 + read-write + + + P6 + Pin 6 weak pull-up enabled + 6 + 1 + read-write + + + P7 + Pin 7 weak pull-up enabled + 7 + 1 + read-write + + + + + PFPUEN + PF Weak Pull-up Enable + 0x3C + + + P0 + Pin 0 weak pull-up enabled + 0 + 1 + read-write + + + P1 + Pin 1 weak pull-up enabled + 1 + 1 + read-write + + + P2 + Pin 2 weak pull-up enabled + 2 + 1 + read-write + + + P3 + Pin 3 weak pull-up enabled + 3 + 1 + read-write + + + P4 + Pin 4 weak pull-up enabled + 4 + 1 + read-write + + + P5 + Pin 5 weak pull-up enabled + 5 + 1 + read-write + + + P6 + Pin 6 weak pull-up enabled + 6 + 1 + read-write + + + P7 + Pin 7 weak pull-up enabled + 7 + 1 + read-write + + + + + PGPUEN + PG Weak Pull-up Enable + 0x40 + + + P0 + Pin 0 weak pull-up enabled + 0 + 1 + read-write + + + P1 + Pin 1 weak pull-up enabled + 1 + 1 + read-write + + + P2 + Pin 2 weak pull-up enabled + 2 + 1 + read-write + + + P3 + Pin 3 weak pull-up enabled + 3 + 1 + read-write + + + P4 + Pin 4 weak pull-up enabled + 4 + 1 + read-write + + + P5 + Pin 5 weak pull-up enabled + 5 + 1 + read-write + + + P6 + Pin 6 weak pull-up enabled + 6 + 1 + read-write + + + P7 + Pin 7 weak pull-up enabled + 7 + 1 + read-write + + + + + PAPDEN + PA Weak Pull-down Enable + 0x44 + + + P0 + Pin 0 weak pull-down enabled + 0 + 1 + read-write + + + P1 + Pin 1 weak pull-down enabled + 1 + 1 + read-write + + + P2 + Pin 2 weak pull-down enabled + 2 + 1 + read-write + + + P3 + Pin 3 weak pull-down enabled + 3 + 1 + read-write + + + P4 + Pin 4 weak pull-down enabled + 4 + 1 + read-write + + + P5 + Pin 5 weak pull-down enabled + 5 + 1 + read-write + + + P6 + Pin 6 weak pull-down enabled + 6 + 1 + read-write + + + P7 + Pin 7 weak pull-down enabled + 7 + 1 + read-write + + + + + PBPDEN + PB Weak Pull-down Enable + 0x48 + + + P0 + Pin 0 weak pull-down enabled + 0 + 1 + read-write + + + P1 + Pin 1 weak pull-down enabled + 1 + 1 + read-write + + + P2 + Pin 2 weak pull-down enabled + 2 + 1 + read-write + + + P3 + Pin 3 weak pull-down enabled + 3 + 1 + read-write + + + P4 + Pin 4 weak pull-down enabled + 4 + 1 + read-write + + + P5 + Pin 5 weak pull-down enabled + 5 + 1 + read-write + + + P6 + Pin 6 weak pull-down enabled + 6 + 1 + read-write + + + P7 + Pin 7 weak pull-down enabled + 7 + 1 + read-write + + + + + PCPDEN + PC Weak Pull-down Enable + 0x4C + + + P0 + Pin 0 weak pull-down enabled + 0 + 1 + read-write + + + P1 + Pin 1 weak pull-down enabled + 1 + 1 + read-write + + + P2 + Pin 2 weak pull-down enabled + 2 + 1 + read-write + + + P3 + Pin 3 weak pull-down enabled + 3 + 1 + read-write + + + P4 + Pin 4 weak pull-down enabled + 4 + 1 + read-write + + + P5 + Pin 5 weak pull-down enabled + 5 + 1 + read-write + + + P6 + Pin 6 weak pull-down enabled + 6 + 1 + read-write + + + P7 + Pin 7 weak pull-down enabled + 7 + 1 + read-write + + + + + PDPDEN + PD Weak Pull-down Enable + 0x50 + + + P0 + Pin 0 weak pull-down enabled + 0 + 1 + read-write + + + P1 + Pin 1 weak pull-down enabled + 1 + 1 + read-write + + + P2 + Pin 2 weak pull-down enabled + 2 + 1 + read-write + + + P3 + Pin 3 weak pull-down enabled + 3 + 1 + read-write + + + P4 + Pin 4 weak pull-down enabled + 4 + 1 + read-write + + + P5 + Pin 5 weak pull-down enabled + 5 + 1 + read-write + + + P6 + Pin 6 weak pull-down enabled + 6 + 1 + read-write + + + P7 + Pin 7 weak pull-down enabled + 7 + 1 + read-write + + + + + PEPDEN + PE Weak Pull-down Enable + 0x54 + + + P0 + Pin 0 weak pull-down enabled + 0 + 1 + read-write + + + P1 + Pin 1 weak pull-down enabled + 1 + 1 + read-write + + + P2 + Pin 2 weak pull-down enabled + 2 + 1 + read-write + + + P3 + Pin 3 weak pull-down enabled + 3 + 1 + read-write + + + P4 + Pin 4 weak pull-down enabled + 4 + 1 + read-write + + + P5 + Pin 5 weak pull-down enabled + 5 + 1 + read-write + + + P6 + Pin 6 weak pull-down enabled + 6 + 1 + read-write + + + P7 + Pin 7 weak pull-down enabled + 7 + 1 + read-write + + + + + PFPDEN + PF Weak Pull-down Enable + 0x58 + + + P0 + Pin 0 weak pull-down enabled + 0 + 1 + read-write + + + P1 + Pin 1 weak pull-down enabled + 1 + 1 + read-write + + + P2 + Pin 2 weak pull-down enabled + 2 + 1 + read-write + + + P3 + Pin 3 weak pull-down enabled + 3 + 1 + read-write + + + P4 + Pin 4 weak pull-down enabled + 4 + 1 + read-write + + + P5 + Pin 5 weak pull-down enabled + 5 + 1 + read-write + + + P6 + Pin 6 weak pull-down enabled + 6 + 1 + read-write + + + P7 + Pin 7 weak pull-down enabled + 7 + 1 + read-write + + + + + PGPDEN + PG Weak Pull-down Enable + 0x5C + + + P0 + Pin 0 weak pull-down enabled + 0 + 1 + read-write + + + P1 + Pin 1 weak pull-down enabled + 1 + 1 + read-write + + + P2 + Pin 2 weak pull-down enabled + 2 + 1 + read-write + + + P3 + Pin 3 weak pull-down enabled + 3 + 1 + read-write + + + P4 + Pin 4 weak pull-down enabled + 4 + 1 + read-write + + + P5 + Pin 5 weak pull-down enabled + 5 + 1 + read-write + + + P6 + Pin 6 weak pull-down enabled + 6 + 1 + read-write + + + P7 + Pin 7 weak pull-down enabled + 7 + 1 + read-write + + + + + PADS + PA Drive Strength/Schmitt Trigger + 0x60 + + + P0DS + Pin 0 Drive Strength + 0 + 3 + read-write + + DS + read-write + + DS_6MA + 6 mA + 0 + + + DS_8MA + 8 mA + 1 + + + DS_11MA + 11 mA + 2 + + + DS_14MA + 14 mA + 3 + + + DS_17MA + 17 mA + 4 + + + DS_20MA + 20 mA + 5 + + + DS_22MA + 22 mA + 6 + + + DS_25MA + 25 mA + 7 + + + + + P0ST + Pin 0 Schmitt Trigger Enable + 3 + 1 + read-write + + + P1DS + Pin 1 Drive Strength + 4 + 3 + read-write + + + + P1ST + Pin 1 Schmitt Trigger Enable + 7 + 1 + read-write + + + P2DS + Pin 2 Drive Strength + 8 + 3 + read-write + + + + P2ST + Pin 2 Schmitt Trigger Enable + 11 + 1 + read-write + + + P3DS + Pin 3 Drive Strength + 12 + 3 + read-write + + + + P3ST + Pin 3 Schmitt Trigger Enable + 15 + 1 + read-write + + + P4DS + Pin 4 Drive Strength + 16 + 3 + read-write + + + + P4ST + Pin 4 Schmitt Trigger Enable + 19 + 1 + read-write + + + P5DS + Pin 5 Drive Strength + 20 + 3 + read-write + + + + P5ST + Pin 5 Schmitt Trigger Enable + 23 + 1 + read-write + + + P6DS + Pin 6 Drive Strength + 24 + 3 + read-write + + + + P6ST + Pin 6 Schmitt Trigger Enable + 27 + 1 + read-write + + + P7DS + Pin 7 Drive Strength + 28 + 3 + read-write + + + + P7ST + Pin 7 Schmitt Trigger Enable + 31 + 1 + read-write + + + + + PBDS + PB Drive Strength/Schmitt Trigger + 0x64 + + + P0DS + Pin 0 Drive Strength + 0 + 3 + read-write + + + + P0ST + Pin 0 Schmitt Trigger Enable + 3 + 1 + read-write + + + P1DS + Pin 1 Drive Strength + 4 + 3 + read-write + + + + P1ST + Pin 1 Schmitt Trigger Enable + 7 + 1 + read-write + + + P2DS + Pin 2 Drive Strength + 8 + 3 + read-write + + + + P2ST + Pin 2 Schmitt Trigger Enable + 11 + 1 + read-write + + + P3DS + Pin 3 Drive Strength + 12 + 3 + read-write + + + + P3ST + Pin 3 Schmitt Trigger Enable + 15 + 1 + read-write + + + P4DS + Pin 4 Drive Strength + 16 + 3 + read-write + + + + P4ST + Pin 4 Schmitt Trigger Enable + 19 + 1 + read-write + + + P5DS + Pin 5 Drive Strength + 20 + 3 + read-write + + + + P5ST + Pin 5 Schmitt Trigger Enable + 23 + 1 + read-write + + + P6DS + Pin 6 Drive Strength + 24 + 3 + read-write + + + + P6ST + Pin 6 Schmitt Trigger Enable + 27 + 1 + read-write + + + P7DS + Pin 7 Drive Strength + 28 + 3 + read-write + + + + P7ST + Pin 7 Schmitt Trigger Enable + 31 + 1 + read-write + + + + + PCDS + PC Drive Strength/Schmitt Trigger + 0x68 + + + P0DS + Pin 0 Drive Strength + 0 + 3 + read-write + + + + P0ST + Pin 0 Schmitt Trigger Enable + 3 + 1 + read-write + + + P1DS + Pin 1 Drive Strength + 4 + 3 + read-write + + + + P1ST + Pin 1 Schmitt Trigger Enable + 7 + 1 + read-write + + + P2DS + Pin 2 Drive Strength + 8 + 3 + read-write + + + + P2ST + Pin 2 Schmitt Trigger Enable + 11 + 1 + read-write + + + P3DS + Pin 3 Drive Strength + 12 + 3 + read-write + + + + P3ST + Pin 3 Schmitt Trigger Enable + 15 + 1 + read-write + + + P4DS + Pin 4 Drive Strength + 16 + 3 + read-write + + + + P4ST + Pin 4 Schmitt Trigger Enable + 19 + 1 + read-write + + + P5DS + Pin 5 Drive Strength + 20 + 3 + read-write + + + + P5ST + Pin 5 Schmitt Trigger Enable + 23 + 1 + read-write + + + P6DS + Pin 6 Drive Strength + 24 + 3 + read-write + + + + P6ST + Pin 6 Schmitt Trigger Enable + 27 + 1 + read-write + + + P7DS + Pin 7 Drive Strength + 28 + 3 + read-write + + + + P7ST + Pin 7 Schmitt Trigger Enable + 31 + 1 + read-write + + + + + PDDS + PD Drive Strength/Schmitt Trigger + 0x6C + + + P0DS + Pin 0 Drive Strength + 0 + 3 + read-write + + + + P0ST + Pin 0 Schmitt Trigger Enable + 3 + 1 + read-write + + + P1DS + Pin 1 Drive Strength + 4 + 3 + read-write + + + + P1ST + Pin 1 Schmitt Trigger Enable + 7 + 1 + read-write + + + P2DS + Pin 2 Drive Strength + 8 + 3 + read-write + + + + P2ST + Pin 2 Schmitt Trigger Enable + 11 + 1 + read-write + + + P3DS + Pin 3 Drive Strength + 12 + 3 + read-write + + + + P3ST + Pin 3 Schmitt Trigger Enable + 15 + 1 + read-write + + + P4DS + Pin 4 Drive Strength + 16 + 3 + read-write + + + + P4ST + Pin 4 Schmitt Trigger Enable + 19 + 1 + read-write + + + P5DS + Pin 5 Drive Strength + 20 + 3 + read-write + + + + P5ST + Pin 5 Schmitt Trigger Enable + 23 + 1 + read-write + + + P6DS + Pin 6 Drive Strength + 24 + 3 + read-write + + + + P6ST + Pin 6 Schmitt Trigger Enable + 27 + 1 + read-write + + + P7DS + Pin 7 Drive Strength + 28 + 3 + read-write + + + + P7ST + Pin 7 Schmitt Trigger Enable + 31 + 1 + read-write + + + + + PEDS + PE Drive Strength/Schmitt Trigger + 0x70 + + + P0DS + Pin 0 Drive Strength + 0 + 3 + read-write + + + + P0ST + Pin 0 Schmitt Trigger Enable + 3 + 1 + read-write + + + P1DS + Pin 1 Drive Strength + 4 + 3 + read-write + + + + P1ST + Pin 1 Schmitt Trigger Enable + 7 + 1 + read-write + + + P2DS + Pin 2 Drive Strength + 8 + 3 + read-write + + + + P2ST + Pin 2 Schmitt Trigger Enable + 11 + 1 + read-write + + + P3DS + Pin 3 Drive Strength + 12 + 3 + read-write + + + + P3ST + Pin 3 Schmitt Trigger Enable + 15 + 1 + read-write + + + P4DS + Pin 4 Drive Strength + 16 + 3 + read-write + + + + P4ST + Pin 4 Schmitt Trigger Enable + 19 + 1 + read-write + + + P5DS + Pin 5 Drive Strength + 20 + 3 + read-write + + + + P5ST + Pin 5 Schmitt Trigger Enable + 23 + 1 + read-write + + + P6DS + Pin 6 Drive Strength + 24 + 3 + read-write + + + + P6ST + Pin 6 Schmitt Trigger Enable + 27 + 1 + read-write + + + P7DS + Pin 7 Drive Strength + 28 + 3 + read-write + + + + P7ST + Pin 7 Schmitt Trigger Enable + 31 + 1 + read-write + + + + + PFDS + PF Drive Strength/Schmitt Trigger + 0x74 + + + P0DS + Pin 0 Drive Strength + 0 + 3 + read-write + + + + P0ST + Pin 0 Schmitt Trigger Enable + 3 + 1 + read-write + + + P1DS + Pin 1 Drive Strength + 4 + 3 + read-write + + + + P1ST + Pin 1 Schmitt Trigger Enable + 7 + 1 + read-write + + + P2DS + Pin 2 Drive Strength + 8 + 3 + read-write + + + + P2ST + Pin 2 Schmitt Trigger Enable + 11 + 1 + read-write + + + P3DS + Pin 3 Drive Strength + 12 + 3 + read-write + + + + P3ST + Pin 3 Schmitt Trigger Enable + 15 + 1 + read-write + + + P4DS + Pin 4 Drive Strength + 16 + 3 + read-write + + + + P4ST + Pin 4 Schmitt Trigger Enable + 19 + 1 + read-write + + + P5DS + Pin 5 Drive Strength + 20 + 3 + read-write + + + + P5ST + Pin 5 Schmitt Trigger Enable + 23 + 1 + read-write + + + P6DS + Pin 6 Drive Strength + 24 + 3 + read-write + + + + P6ST + Pin 6 Schmitt Trigger Enable + 27 + 1 + read-write + + + P7DS + Pin 7 Drive Strength + 28 + 3 + read-write + + + + P7ST + Pin 7 Schmitt Trigger Enable + 31 + 1 + read-write + + + + + PGDS + PG Drive Strength/Schmitt Trigger + 0x78 + + + P0DS + Pin 0 Drive Strength + 0 + 3 + read-write + + + + P0ST + Pin 0 Schmitt Trigger Enable + 3 + 1 + read-write + + + P1DS + Pin 1 Drive Strength + 4 + 3 + read-write + + + + P1ST + Pin 1 Schmitt Trigger Enable + 7 + 1 + read-write + + + P2DS + Pin 2 Drive Strength + 8 + 3 + read-write + + + + P2ST + Pin 2 Schmitt Trigger Enable + 11 + 1 + read-write + + + P3DS + Pin 3 Drive Strength + 12 + 3 + read-write + + + + P3ST + Pin 3 Schmitt Trigger Enable + 15 + 1 + read-write + + + P4DS + Pin 4 Drive Strength + 16 + 3 + read-write + + + + P4ST + Pin 4 Schmitt Trigger Enable + 19 + 1 + read-write + + + P5DS + Pin 5 Drive Strength + 20 + 3 + read-write + + + + P5ST + Pin 5 Schmitt Trigger Enable + 23 + 1 + read-write + + + P6DS + Pin 6 Drive Strength + 24 + 3 + read-write + + + + P6ST + Pin 6 Schmitt Trigger Enable + 27 + 1 + read-write + + + P7DS + Pin 7 Drive Strength + 28 + 3 + read-write + + + + P7ST + Pin 7 Schmitt Trigger Enable + 31 + 1 + read-write + + + + + + + WWDT + Windowed Watchdog Timer + 0x400D0800 + + 0x0 + 0x400 + registers + + + WWDT + WWDT Interrupt + 1 + + + + CTL + WWDT Control + 0x0 + + + EN + Enable WWDT + 0 + 1 + read-write + + + INTEN + Enable WWDT interrupt + 1 + 1 + read-write + + + RSTEN + Enable WWDT POR reset + 2 + 1 + read-write + + + CLKSEL + WWDT input clock source + 3 + 1 + read-write + + CLKSEL + read-write + + FRCLK + FRCLK as WWDT clock + 0 + + + ROSCCLK + ROSCCLK as WWDT clock + 1 + + + + + CLKDIV + WWDT input clock divider + 4 + 4 + read-write + + CLKDIV + read-write + + DIV1 + /1 + 0 + + + DIV2 + /2 + 1 + + + DIV4 + /4 + 2 + + + DIV8 + /8 + 3 + + + DIV16 + /16 + 4 + + + DIV32 + /32 + 5 + + + DIV64 + /64 + 6 + + + DIV128 + /128 + 7 + + + DIV256 + /256 + 8 + + + DIV512 + /512 + 9 + + + DIV1024 + /1024 + 10 + + + DIV2048 + /2048 + 11 + + + DIV4096 + /4096 + 12 + + + DIV8192 + /8192 + 13 + + + DIV16384 + /16384 + 14 + + + DIV32768 + /32768 + 15 + + + + + + + CDCTL + WWDT Load Counter Value + 0x4 + + + CDV + WWDT count-down value + 0 + 16 + read-write + + + WINDOW + WWDT window value + 16 + 16 + read-write + + + + + CTR + WWDT Counter + 0x8 + read-only + + + CNT + WWDT counter value + 0 + 16 + read-only + + + + + FLAG + WWDT Interrupt Flag + 0xC + + + IF + WWDT interrupt flag + 0 + 1 + read-write + + + RSTF + WWDT reset flag + 1 + 1 + read-write + + + + + CLEAR + WWDT Interrupt Clear + 0x10 + write-only + + + VALUE + WWDT clear + 0 + 32 + write-only + + + + + LOCK + WWDT Lock + 0x14 + + + VALUE + WWDT lock + 0 + 32 + read-write + + VALUE + read-write + + READ_ONLY + WWDT registers are read-only + 1437230744 + + + ALLOW_WRITE + WWDT registers available for write + 1437230745 + + + + + + + + + RTC + Real-Time Clock (RTC) with Calendar + 0x400D0C00 + + 0x0 + 0x400 + registers + + + RTC + RTC Interrupt + 2 + + + + CTL + RTC Control + 0x0 + + + EN + Enable RTC + 0 + 1 + read-write + + + IE + Alarm match interrupt enable + 1 + 1 + read-write + + + IF + Alarm match interrupt flag + 2 + 1 + read-write + + + CLKDIV + Clock divider for the RTC input clock (FRCLK) + 4 + 5 + read-write + + CLKDIV + read-write + + DIV1 + FRCLK/1 + 0 + + + DIV2 + FRCLK/2 + 1 + + + DIV3 + FRCLK/3 + 2 + + + DIV4 + FRCLK/4 + 3 + + + DIV5 + FRCLK/5 + 4 + + + DIV6 + FRCLK/6 + 5 + + + DIV7 + FRCLK/7 + 6 + + + DIV8 + FRCLK/8 + 7 + + + DIV9 + FRCLK/9 + 8 + + + DIV10 + FRCLK/10 + 9 + + + DIV11 + FRCLK/11 + 10 + + + DIV12 + FRCLK/12 + 11 + + + DIV13 + FRCLK/13 + 12 + + + DIV14 + FRCLK/14 + 13 + + + DIV15 + FRCLK/15 + 14 + + + DIV16 + FRCLK/16 + 15 + + + DIV17 + FRCLK/17 + 16 + + + DIV18 + FRCLK/18 + 17 + + + DIV19 + FRCLK/19 + 18 + + + DIV20 + FRCLK/20 + 19 + + + DIV21 + FRCLK/21 + 20 + + + DIV22 + FRCLK/22 + 21 + + + DIV23 + FRCLK/23 + 22 + + + DIV24 + FRCLK/24 + 23 + + + DIV25 + FRCLK/25 + 24 + + + DIV26 + FRCLK/26 + 25 + + + DIV27 + FRCLK/27 + 26 + + + DIV28 + FRCLK/28 + 27 + + + DIV29 + FRCLK/29 + 28 + + + DIV30 + FRCLK/30 + 29 + + + DIV31 + FRCLK/31 + 30 + + + DIV32 + FRCLK/32 + 31 + + + + + SETCAL + Set the internal TIME/DATA with TIMESET/DATESET values + 31 + 1 + read-write + + + + + TIME + RTC Time + 0x4 + + + SECONDS + Seconds + 0 + 7 + read-write + + + MINUTES + Minutes + 8 + 7 + read-write + + + HOURS + Hours + 16 + 6 + read-write + + + + + DATE + RTC Date + 0x8 + + + DAYOFWEEK + Day of week + 0 + 3 + read-write + + + DAY + Day + 8 + 6 + read-write + + + MONTH + Month + 16 + 5 + read-write + + + YEAR + Year + 24 + 8 + read-write + + + + + TIMESET + RTC Time Setting + 0xC + + + SECONDS + Seconds + 0 + 7 + read-write + + + MINUTES + Minutes + 8 + 7 + read-write + + + HOURS + Hours + 16 + 6 + read-write + + + + + DATESET + RTC Date Setting + 0x10 + + + DAYOFWEEK + Day of week + 0 + 3 + read-write + + + DAY + Day + 8 + 6 + read-write + + + MONTH + Month + 16 + 5 + read-write + + + YEAR + Year + 24 + 8 + read-write + + + + + ALARMSET + RTC Alarm Setting + 0x14 + + + MINUTEALARM + Minute alarm + 0 + 7 + read-write + + + MINUTEALARMEN + Minute alarm enable + 7 + 1 + read-write + + + HOURALARM + Hour alarm + 8 + 6 + read-write + + + HOURALARMEN + Hour alarm enable + 14 + 1 + read-write + + + DAYOFWEEKALARM + Day of week alarm + 16 + 3 + read-write + + + DAYOFWEEKALARMEN + Day of week alarm enable + 19 + 1 + read-write + + + DAYALARM + Day alarm + 24 + 6 + read-write + + + DAYALARMEN + Day alarm enable + 30 + 1 + read-write + + + + + + + CRC + Cyclic Redundancy Check + 0x400D1000 + + 0x0 + 0x400 + registers + + + + CTL + CRC Control + 0x0 + + + POLYSEL + CRC Polynomial Select + 0 + 2 + read-write + + POLYSEL + read-write + + CRC_16_CCITT + CRC-16-CCITT + 0 + + + CRC_16_IBM + CRC-16-IBM + 1 + + + CRC_8_DALLAS_MAXIM + CRC-8-Dallas/Maxim + 2 + + + + + DATAWIDTH + CRC Data Width + 2 + 1 + read-write + + DATAWIDTH + read-write + + BITS32 + 32 bits + 0 + + + BITS8 + 8 bits + 1 + + + + + OUTREF + Reflect DATAOUT output data from CRC engine + 3 + 1 + read-write + + + INREF + Reflect DATAIN input data to CRC engine + 4 + 1 + read-write + + + + + DATAIN + CRC Data Input + 0x4 + + + SEED + CRC Seed Value + 0x8 + + + CRCSEED + CRC Seed Value + 0 + 16 + read-write + + + + + OUT + CRC Data Output + 0xC + + + CRCOUT + CRC data output value + 0 + 16 + read-only + + + + + + + GPIOA + General Purpose Input/Output A + 0x400D1400 + GPIO + + 0x0 + 0x400 + registers + + + GPIOA + GPIOA Interrupt + 15 + + + + MODE + GPIO Pin Mode Select + 0x0 + + + P0 + Pin 0 mode + 0 + 2 + read-write + + PINMODE + read-write + + ANALOG + Analog input + 0 + + + PUSH_PULL_OUTPUT + Push-pull output + 1 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 2 + + + HIGH_IMPEDANCE_INPUT + High-impedance input + 3 + + + + + P1 + Pin 1 mode + 2 + 2 + read-write + + + + P2 + Pin 2 mode + 4 + 2 + read-write + + + + P3 + Pin 3 mode + 6 + 2 + read-write + + + + P4 + Pin 4 mode + 8 + 2 + read-write + + + + P5 + Pin 5 mode + 10 + 2 + read-write + + + + P6 + Pin 6 mode + 12 + 2 + read-write + + + + P7 + Pin 7 mode + 14 + 2 + read-write + + + + + + OUTMASK + GPIO Data Output Write Mask + 0x4 + + + P0 + Pin 0 output data mask + 0 + 1 + read-write + + + P1 + Pin 1 output data mask + 1 + 1 + read-write + + + P2 + Pin 2 output data mask + 2 + 1 + read-write + + + P3 + Pin 3 output data mask + 3 + 1 + read-write + + + P4 + Pin 4 output data mask + 4 + 1 + read-write + + + P5 + Pin 5 output data mask + 5 + 1 + read-write + + + P6 + Pin 6 output data mask + 6 + 1 + read-write + + + P7 + Pin 7 output data mask + 7 + 1 + read-write + + + + + OUT + GPIO Data Output Value + 0x8 + + + P0 + Pin 0 output data value + 0 + 1 + read-write + + + P1 + Pin 1 output data value + 1 + 1 + read-write + + + P2 + Pin 2 output data value + 2 + 1 + read-write + + + P3 + Pin 3 output data value + 3 + 1 + read-write + + + P4 + Pin 4 output data value + 4 + 1 + read-write + + + P5 + Pin 5 output data value + 5 + 1 + read-write + + + P6 + Pin 6 output data value + 6 + 1 + read-write + + + P7 + Pin 7 output data value + 7 + 1 + read-write + + + + + IN + GPIO Data Input Value + 0xC + + + P0 + Pin 0 input data value + 0 + 1 + read-write + + + P1 + Pin 1 input data value + 1 + 1 + read-write + + + P2 + Pin 2 input data value + 2 + 1 + read-write + + + P3 + Pin 3 input data value + 3 + 1 + read-write + + + P4 + Pin 4 input data value + 4 + 1 + read-write + + + P5 + Pin 5 input data value + 5 + 1 + read-write + + + P6 + Pin 6 input data value + 6 + 1 + read-write + + + P7 + Pin 7 input data value + 7 + 1 + read-write + + + + + INTEN + GPIO Interrupt Enable + 0x10 + + + INTFLAGRAW + GPIO Interrupt Flag Raw + 0x14 + + + INTFLAGMASKED + GPIO Interrupt Flag Masked + 0x18 + + + INTCLEAR + GPIO Interrupt Clear + 0x1C + + + INTTYPE + GPIO Interrupt Type + 0x20 + + + INTVALUE + GPIO Interrupt Value + 0x24 + + + INTEDGEBOTH + GPIO Interrupt Edge Both + 0x28 + + + DEBOUNCE + GPIO De-bounce Filter + 0x2C + + + DOSET + GPIO Data Output Set + 0x30 + + + P0 + Pin 0 data output set + 0 + 1 + read-write + + + P1 + Pin 1 data output set + 1 + 1 + read-write + + + P2 + Pin 2 data output set + 2 + 1 + read-write + + + P3 + Pin 3 data output set + 3 + 1 + read-write + + + P4 + Pin 4 data output set + 4 + 1 + read-write + + + P5 + Pin 5 data output set + 5 + 1 + read-write + + + P6 + Pin 6 data output set + 6 + 1 + read-write + + + P7 + Pin 7 data output set + 7 + 1 + read-write + + + + + DOCLEAR + GPIO Data Output Clear + 0x34 + + + P0 + Pin 0 data output clear + 0 + 1 + read-write + + + P1 + Pin 1 data output clear + 1 + 1 + read-write + + + P2 + Pin 2 data output clear + 2 + 1 + read-write + + + P3 + Pin 3 data output clear + 3 + 1 + read-write + + + P4 + Pin 4 data output clear + 4 + 1 + read-write + + + P5 + Pin 5 data output clear + 5 + 1 + read-write + + + P6 + Pin 6 data output clear + 6 + 1 + read-write + + + P7 + Pin 7 data output clear + 7 + 1 + read-write + + + + + + + GPIOB + General Purpose Input/Output B + 0x400D1800 + + GPIOB + GPIO B Interrupt + 16 + + + + GPIOC + General Purpose Input/Output C + 0x400D1C00 + + GPIOC + GPIO C Interrupt + 17 + + + + GPIOD + General Purpose Input/Output D + 0x400D2000 + + GPIOD + GPIO D Interrupt + 18 + + + + GPIOE + General Purpose Input/Output E + 0x400D2400 + + GPIOE + GPIO E Interrupt + 19 + + + + GPIOF + General Purpose Input/Output F + 0x400D2800 + + GPIOF + GPIO F Interrupt + 20 + + + + GPIOG + General Purpose Input/Output G + 0x400D2C00 + + GPIOG + GPIO G Interrupt + 21 + + + + diff --git a/svd/PAC55XX.transforms.yaml b/svd/PAC55XX.transforms.yaml new file mode 100644 index 0000000..2110907 --- /dev/null +++ b/svd/PAC55XX.transforms.yaml @@ -0,0 +1,148 @@ +transforms: + # ADC ---------------------------------------------------------------------- + # ADC: INT + - !MakeFieldArray + fieldsets: adc::regs::Adcint + from: intf\d+ + to: intf + - !MakeFieldArray + fieldsets: adc::regs::Adcint + from: adcirq\dif + to: adcirqif + # ADC: DTSETRIGENT*TO* + - !MergeEnums + from: adc::vals::Trig\d+edge + to: adc::vals::Trigedge + # ADC: DTSESEQCFG + - !MergeEnums + from: adc::vals::Dtseseqcfg\d+Emuxc + to: adc::vals::DtseseqcfgEmuxc + - !MakeRegisterArray + blocks: adc::Adc + from: dtseseqcfg\d+ + to: dtseseqcfg + - !MergeFieldsets + from: adc::regs::Dtseseqcfg\d+ + to: adc::regs::Dtseseqcfg + # ADC: DTSERES + - !MergeFieldsets + from: adc::regs::Dtseres\d+ + to: adc::regs::Dtseres + - !MakeRegisterArray + blocks: adc::Adc + from: dtseres\d+ + to: dtseres + + # GPIO --------------------------------------------------------------------- + - !Rename + from: gpioa::(.*) + to: gpio::$1 + - !Rename + from: gpio::Gpioa + to: gpio::Gpio + + # GPIO: MODE|OUTMASK|OUT|IN|DOSET|DOCLEAR + - !MergeEnums + from: gpio::vals::P\d + to: gpio::vals::P + - !MakeFieldArray + fieldsets: gpio::regs::(Mode|Outmask|Out|In|Doset|Doclear) + from: p(.*)\d + to: p + + # GPTIMER ------------------------------------------------------------------ + - !Rename + from: gptimera::(.*) + to: gptimer::$1 + - !Rename + from: gptimer::Gptimera + to: gptimer::Gptimer + + # I2C ---------------------------------------------------------------------- + - !MergeFieldsets + from: i2c::regs::Adr\d + to: i2c::regs::Adr + - !MergeFieldsets + from: i2c::regs::Adrm\d + to: i2c::regs::Adrm + + # SCC ---------------------------------------------------------------------- + # SCC: CCSCTL + - !MergeEnums + from: scc::vals::Us[a-d]mode + to: scc::vals::Usmode + + # SCC: P[A-G]P[U|D]EN + - !MergeFieldsets + from: scc::regs::P[a-g]puen + to: scc::regs::Ppuen + - !MergeFieldsets + from: scc::regs::P[a-g]pden + to: scc::regs::Ppden + - !MakeFieldArray + fieldsets: scc::regs::Pp[u|d]en + from: p\d + to: p + + # SCC: P[A-G]DS + - !MergeEnums + from: scc::vals::P[a-g]dsP\dds + to: scc::vals::Pds + - !MergeEnums + from: scc::vals::P[a-g]dsP\dst + to: scc::vals::Pst + - !MergeFieldsets + from: scc::regs::P[a-g]ds + to: scc::regs::Pds + - !MakeFieldArray + fieldsets: scc::regs::Pds + from: p\d(ds|st) + to: p$1 + + # SSP ---------------------------------------------------------------------- + - !Rename + from: sspa::(.*) + to: ssp::$1 + - !Rename + from: ssp::Sspa + to: ssp::Ssp + + # TIMER -------------------------------------------------------------------- + - !Rename + from: timera::(.*) + to: timer::$1 + - !Rename + from: timer::Timera + to: timer::Timer + # TIMER: INT + - !MakeFieldArray + fieldsets: timer::regs::Int + from: ccr\dif + to: ccrif + # TIMER: CCTL + - !MergeEnums + from: timer::vals::Cctl\d(.*) + to: timer::vals::Cctl$1 + - !MergeFieldsets + from: timer::regs::Cct(l|r)\d + to: timer::regs::Cct$1 + - !MakeRegisterArray + blocks: timer::Timer + from: cct(l|r)\d + to: cct$1 + # TIMER: DGCTL + - !MergeFieldsets + from: timer::regs::Dtgctl\d + to: timer::regs::Dtgctl + - !MakeRegisterArray + blocks: timer::Timer + from: dtgctl\d + to: dtgctl + + # USART -------------------------------------------------------------------- + - !Rename + from: usarta::(.*) + to: usart::$1 + - !Rename + from: usart::Usarta + to: usart::Usart diff --git a/svd/PAC55XX.yaml b/svd/PAC55XX.yaml new file mode 100644 index 0000000..3f78358 --- /dev/null +++ b/svd/PAC55XX.yaml @@ -0,0 +1,75 @@ +_svd: "PAC55XX.svd" + +# Adjust here description of arrayed registers/fields, so that generation always +# generates zero-diff. + +_modify: + GPIO*: + description: "General Purpose Input/Output" + GPTIMER*: + description: "General Purpose Timer" + SSP*: + description: "Synchronous Serial Peripheral" + TIMER*: + description: "Timer" + USART*: + description: "Universal Synchronous Asynchronous Receive Transmit" + +ADC: + _modify: + DTSERES*: + description: "DTSE Result" + DTSESEQCFG*: + description: "DTSE Sequence Configuration" + + ADCINT: + _modify: + ADCIRQ*IF: + description: "ADCIRQ Interrupt Flag" + INTF*[0-9]: + description: "DTSE Sequence Interrupt Flag" + +I2C: + _modify: + ADR*: + description: "I2C Slave Address" + ADRM*: + description: "I2C Slave Address Mask" + +SCC: + _modify: + P*DS: + description: "Drive Strength/Schmitt Trigger" + P*PUEN: + description: "Weak Pull-up Enable" + P*PDEN: + description: "Weak Pull-down Enable" + + P*PUEN: + _modify: + P*: + description: "Weak Pull-up Enable" + P*PDEN: + _modify: + P*: + description: "Weak Pull-down Enable" + P*DS: + _modify: + P*DS: + description: "Drive Strength" + P*ST: + description: "Schmitt Trigger Enable" + +TIMER*: + _modify: + CCTL*: + description: "Timer CCR Control" + CCTR*: + description: "Timer CCR Counter" + DTGCTL*: + description: "Timer Dead-Time Generator Control" + + INT: + _modify: + CCR*IF: + description: "CCR Interrupt Flag"