diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u595xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u595xx.h index 2a187b4a12..f9da0df15d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u595xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u595xx.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file partition_stm32u595xx.h * @author MCD Application Team - * @brief CMSIS STM32U599xx Device Initial Setup for Secure / Non-Secure Zones + * @brief CMSIS STM32U595xx Device Initial Setup for Secure / Non-Secure Zones * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. * * This file contains: diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f7xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f7xx.h index 627156cc38..36e09bbb10 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f7xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f7xx.h @@ -1,8 +1,8 @@ /** ****************************************************************************** - * @file partition_stm32u5f9xx.h + * @file partition_stm32u5f7xx.h * @author MCD Application Team - * @brief CMSIS STM32U5F9xx Device Initial Setup for Secure / Non-Secure Zones + * @brief CMSIS STM32U5F7xx Device Initial Setup for Secure / Non-Secure Zones * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. * * This file contains: diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f7xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f7xx.h index 723478ad75..515f70e902 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f7xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f7xx.h @@ -26361,11 +26361,11 @@ typedef struct */ /******************************* ADC Instances ********************************/ -#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS)|| \ - ((INSTANCE) == ADC1_S) || \ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S) || \ ((INSTANCE) == ADC2_NS) || \ ((INSTANCE) == ADC2_S) || \ - ((INSTANCE) == ADC4_NS)|| \ + ((INSTANCE) == ADC4_NS) || \ ((INSTANCE) == ADC4_S)) #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g7xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g7xx.h index f460e275c0..7e18d0f3b7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g7xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g7xx.h @@ -27335,11 +27335,11 @@ typedef struct */ /******************************* ADC Instances ********************************/ -#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS)|| \ - ((INSTANCE) == ADC1_S) || \ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S) || \ ((INSTANCE) == ADC2_NS) || \ ((INSTANCE) == ADC2_S) || \ - ((INSTANCE) == ADC4_NS)|| \ + ((INSTANCE) == ADC4_NS) || \ ((INSTANCE) == ADC4_S)) #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h index 5519775501..52dd767b45 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h @@ -66,14 +66,14 @@ /* #define STM32U585xx */ /*!< STM32U585CIU6 STM32U585CIT6 STM32U585RIT6 STM32U585VIT6 STM32U585AII6 STM32U585QII6 STM32U585ZIT6 STM32U585OIY6Q STM32U585VIT6Q STM32U585QEI6Q STM32U585RIT6Q STM32U585AII6Q STM32U585CIU6Q STM32U585CIT6Q STM32U585ZET6Q Devices */ /* #define STM32U595xx */ /*!< STM32U595AJH6 STM32U595ZJT6 STM32U595QJI6 STM32U595VJT6 STM32U595RJT6 STM32U595AJH6Q STM32U595ZJY6QTR STM32U595ZJT6Q STM32U595QJI6Q STM32U595VJT6Q STM32U595RJT6Q STM32U595AIH6 STM32U595ZIT6 STM32U595QII6 STM32U595VIT6 STM32U595RIT6 STM32U595AIH6Q STM32U595ZIY6QTR STM32U595ZIT6Q STM32U595QII6Q STM32U595VIT6Q STM32U595RIT6Q Devices */ /* #define STM32U599xx */ /*!< STM32U599VJT6 STM32U599NJH6Q STM32U599BJY6QTR STM32U599ZJY6QTR STM32U599ZJT6Q STM32U599VJT6Q STM32U599NIH6Q STM32U599ZIY6QTR STM32U599ZIT6Q STM32U599VIT6Q Devices */ - /* #define STM32U5A5xx */ /*!< STM32U5A5AJH6 STM32U5A5ZJT6 STM32U5A5QJI6 STM32U5A5VJT6 STM32U5A5RJT6 STM32U5A5AJH6Q STM32U5A5ZJY6QTR STM32U5A5ZJT6Q STM32U5A5QJI6Q STM32U5A5VJT6Q STM32U5A5RJT6Q Devices */ + /* #define STM32U5A5xx */ /*!< STM32U5A5AJH6 STM32U5A5ZJT6 STM32U5A5QJI6 STM32U5A5VJT6 STM32U5A5RJT6 STM32U5A5AJH6Q STM32U5A5ZJY6QTR STM32U5A5ZJT6Q STM32U5A5QJI6Q STM32U5A5VJT6Q STM32U5A5RJT6Q STM32U5A5QII3Q Devices */ /* #define STM32U5A9xx */ /*!< STM32U5A9NJH6Q STM32U5A9BJY6QTR STM32U5A9ZJY6QTR STM32U5A9ZJT6Q STM32U5A9VJT6Q Devices */ - /* #define STM32U5F7xx */ /*!< STM32U5F7VJT6Q STM32U5F7VJT6 Devices STM32U5F7VIT6Q STM32U5F7VIT6 Devices */ + /* #define STM32U5F7xx */ /*!< STM32U5F7VJT6Q STM32U5F7VJT6 STM32U5F7VIT6Q STM32U5F7VIT6 Devices */ /* #define STM32U5G7xx */ /*!< STM32U5G7VJT6Q STM32U5G7VJT6 Devices */ - /* #define STM32U5F9xx */ /*!< STM32U5F9NJH6Q STM32U5F9BJY6QTR STM32U5F9ZJJ6QTR STM32U5F9ZJT6Q STM32U5F9VJT6Q Devices */ + /* #define STM32U5F9xx */ /*!< STM32U5F9NJH6Q STM32U5F9BJY6QTR STM32U5F9ZJJ6QTR STM32U5F9ZJT6Q STM32U5F9VJT6Q STM32U5F9ZIJ6QTR STM32U5F9ZIT6Q STM32U5F9VIT6Q Devices */ /* #define STM32U5G9xx */ /*!< STM32U5G9NJH6Q STM32U5G9BJY6QTR STM32U5G9ZJJ6QTR STM32U5G9ZJT6Q STM32U5G9VJT6Q Devices */ - /* #define STM32U535xx */ /*!< STM32U535CET6 STM32U535CEU6 STM32U535RET6 STM32U535REI6 STM32U535VET6 STM32U535VEI6 STM32U535CET6Q STM32U535CEU6Q STM32U535RET6Q STM32U535REI6Q STM32U535VET6Q STM32U535VEI6Q STM32U535NEY6Q STM32U535JEY6Q Device */ - /* #define STM32U545xx */ /*!< STM32U545CET6 STM32U545CEU6 STM32U545RET6 STM32U545REI6 STM32U545VET6 STM32U545VEI6 STM32U545CET6Q STM32U545CEU6Q STM32U545RET6Q STM32U545REI6Q STM32U545VET6Q STM32U545VEI6Q STM32U545NEY6Q STM32U545JEY6Q Device */ + /* #define STM32U535xx */ /*!< STM32U535CET6 STM32U535CEU6 STM32U535RET6 STM32U535REI6 STM32U535VET6 STM32U535VEI6 STM32U535CET6Q STM32U535CEU6Q STM32U535RET6Q STM32U535REI6Q STM32U535VET6Q STM32U535VEI6Q STM32U535NEY6Q STM32U535JEY6Q Devices */ + /* #define STM32U545xx */ /*!< STM32U545CET6 STM32U545CEU6 STM32U545RET6 STM32U545REI6 STM32U545VET6 STM32U545VEI6 STM32U545CET6Q STM32U545CEU6Q STM32U545RET6Q STM32U545REI6Q STM32U545VET6Q STM32U545VEI6Q STM32U545NEY6Q STM32U545JEY6Q Devices */ #endif /* Tip: To avoid modifying this file each time you need to switch between these @@ -89,11 +89,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number 1.3.0 + * @brief CMSIS Device version number 1.3.1 */ #define __STM32U5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32U5_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ -#define __STM32U5_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32U5_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32U5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32U5_CMSIS_VERSION ((__STM32U5_CMSIS_VERSION_MAIN << 24U)\ |(__STM32U5_CMSIS_VERSION_SUB1 << 16U)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Release_Notes.html index 1083f827a1..afffc85ad5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Release_Notes.html @@ -30,11 +30,25 @@

Release Notes for  STM32U5xx C

Update History

- +

Main Changes

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

    +
  • Update STM32U5A5xx devices list with STM32U5A5QII3Q under “stm32u5xx.h” file
    • +
+

Backward Compatibility

+
    +
  • N/A
    • +
+
+
+
+ +
+

Main Changes

+

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

+
  • Support of new STM32U5F9xx, STM32U5G9xx, STM32U5F7xx and STM32U5G7xx devices:
    • Add “stm32u5f9xx.h”, “stm32u5g9xx.h”, “stm32u5f7xx.h” and “stm32u5g7xx.h” files
      • @@ -42,7 +56,7 @@

      Main Changes

    • Add linker files for EWARM and STM32CubeIDE toolchains of STM32U5F9xx/STM32U5G9xx/STM32U5F7xx/STM32U5G7xx devices
-

Backward Compatibility

+

Backward Compatibility

  • N/A
@@ -51,7 +65,7 @@

Backward Compatibility

-

Main Changes

+

Main Changes

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

  • Support of stm32u535xx and stm32u545xx devices: @@ -104,7 +118,7 @@

    Main Changes

  • Rename ADC4_PW_VREFSECSMP to ADC4_PWRR_VREFSECSMP
-

Backward Compatibility

+

Backward Compatibility

  • N/A
@@ -113,7 +127,7 @@

Backward Compatibility

-

Main Changes

+

Main Changes

  • CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)
      @@ -143,7 +157,7 @@

      Main Changes

      -

      Main Changes

      +

      Main Changes

      • Rename OTG_FS_BASE_NS to USB_OTG_FS_BASE_NS define
      • Rename OTG_FS_BASE_S to USB_OTG_FS_BASE_S define
        • @@ -155,7 +169,7 @@

        Main Changes

        -

        Main Changes

        +

        Main Changes

        • First official release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)
        diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 5d25504345..80132be290 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -16,7 +16,7 @@ * STM32L4: 1.7.3 * STM32L5: 1.0.5 * STM32MP1: 1.6.0 - * STM32U5: 1.3.0 + * STM32U5: 1.3.1 * STM32WB: 1.12.0 * STM32WL: 1.2.0