diff --git a/Makefile b/Makefile
index a0a4a75..2575c96 100644
--- a/Makefile
+++ b/Makefile
@@ -89,14 +89,14 @@ formal-tests: $(FORMAL_VERIF_DONE)
 # VERILATOR
 LINT_VERILATOR=$(DIR_HDL)/.lint-verilator
 $(LINT_VERILATOR): $(HDL_DONE)
-	@set e; (cd $(DIR_HDL) && verilator --lint-only smaesh_hpc.v && touch $(LINT_VERILATOR) || exit 1)  
+	@set e; (cd $(DIR_HDL) && verilator --lint-only smaesh_hpc.sv && touch $(LINT_VERILATOR) || exit 1)  
 
 lint-verilator: $(LINT_VERILATOR)
 # VERIBLE
 VERIBLE?=verible-verilog-lint
 LINT_VERIBLE=$(DIR_HDL)/.lint-verible
 $(LINT_VERIBLE): $(HDL_DONE)
-	@set e; ($(VERIBLE) $(DIR_HDL)/*.v --rules -parameter-name-style,-always-comb && touch $(LINT_VERIBLE) || exit 1)
+	@set e; ($(VERIBLE) $(DIR_HDL)/*.v $(DIR_HDL)/*.sv --rules -parameter-name-style,-always-comb && touch $(LINT_VERIBLE) || exit 1)
 
 lint-verible: $(LINT_VERIBLE)
 # lint all
diff --git a/formal_verif/Makefile b/formal_verif/Makefile
index 8140e42..32024f6 100644
--- a/formal_verif/Makefile
+++ b/formal_verif/Makefile
@@ -49,7 +49,7 @@ export TOPLEVEL_LANG ?= verilog
 export SIM_BUILD ?= $(WORK_SYNTH)
 # Sources related
 export VERILOG_INCLUDE_DIRS?= $(HDL_DIR)
-export VERILOG_SOURCES ?= $(SYNTH_NETLIST_VERILOG) $(HDL_DIR)/smaesh_hpc.v 
+export VERILOG_SOURCES ?= $(SYNTH_NETLIST_VERILOG) $(HDL_DIR)/smaesh_hpc.sv 
 # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
 export TOPLEVEL ?= smaesh_hpc
 # MODULE is the basename of the Python test file
diff --git a/formal_verif/synth.tcl b/formal_verif/synth.tcl
index b9533e8..f0cf47c 100755
--- a/formal_verif/synth.tcl
+++ b/formal_verif/synth.tcl
@@ -3,7 +3,7 @@ set MAIN_MODULE $::env(MAIN_MODULE)
 set OUT_DIR $::env(OUT_DIR)
 set MATCHI_CELLS $::env(MATCHI_CELLS) 
 
-set MAIN_PATH $IMPLEM_DIR/$MAIN_MODULE.v
+set MAIN_PATH $IMPLEM_DIR/$MAIN_MODULE.sv
 set LIB $MATCHI_CELLS
 set LIB_V $LIB.v
 set LIB $LIB.lib
diff --git a/func_tests/Makefile b/func_tests/Makefile
index e009ec5..5eee8e7 100644
--- a/func_tests/Makefile
+++ b/func_tests/Makefile
@@ -19,7 +19,7 @@ export TOPLEVEL_LANG ?= verilog
 export SIM_BUILD ?= $(WORK_CASE)
 # Sources related
 export VERILOG_INCLUDE_DIRS?= $(RTL_DIR_HDL)
-export VERILOG_SOURCES ?= $(RTL_DIR_HDL)/*.v
+export VERILOG_SOURCES ?= $(RTL_DIR_HDL)/*.v $(RTL_DIR_HDL)/*.sv
 # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
 export TOPLEVEL ?= smaesh_hpc
 # MODULE is the basename of the Python test file
diff --git a/gather_sources.sh b/gather_sources.sh
index ec9cee6..80f4308 100755
--- a/gather_sources.sh
+++ b/gather_sources.sh
@@ -16,7 +16,7 @@ mkdir -p $OUT_DIR
 # Iterate over each directory
 for var in "$@"; do
 	dir="$SCRIPT_DIR/$var"
-	files=$(find $dir -name '*.v' -o -name '*.vh')
+	files=$(find $dir -name '*.v' -o -name '*.vh' -o -name '*.sv')
 	for file in $files; do
 		cp $file $OUT_DIR
 		echo "$file copied to $OUT_DIR"
diff --git a/hdl/smaesh_hpc/MSKaes_32bits_core.v b/hdl/smaesh_hpc/MSKaes_32bits_core.sv
similarity index 100%
rename from hdl/smaesh_hpc/MSKaes_32bits_core.v
rename to hdl/smaesh_hpc/MSKaes_32bits_core.sv
diff --git a/hdl/smaesh_hpc/MSKaes_32bits_fsm.v b/hdl/smaesh_hpc/MSKaes_32bits_fsm.sv
similarity index 100%
rename from hdl/smaesh_hpc/MSKaes_32bits_fsm.v
rename to hdl/smaesh_hpc/MSKaes_32bits_fsm.sv
diff --git a/hdl/smaesh_hpc/MSKaes_32bits_key_datapath.v b/hdl/smaesh_hpc/MSKaes_32bits_key_datapath.sv
similarity index 100%
rename from hdl/smaesh_hpc/MSKaes_32bits_key_datapath.v
rename to hdl/smaesh_hpc/MSKaes_32bits_key_datapath.sv
diff --git a/hdl/smaesh_hpc/MSKaes_32bits_state_datapath.v b/hdl/smaesh_hpc/MSKaes_32bits_state_datapath.sv
similarity index 100%
rename from hdl/smaesh_hpc/MSKaes_32bits_state_datapath.v
rename to hdl/smaesh_hpc/MSKaes_32bits_state_datapath.sv
diff --git a/hdl/smaesh_hpc/MSKaes_rcon.v b/hdl/smaesh_hpc/MSKaes_rcon.sv
similarity index 100%
rename from hdl/smaesh_hpc/MSKaes_rcon.v
rename to hdl/smaesh_hpc/MSKaes_rcon.sv
diff --git a/hdl/smaesh_hpc/MSKbit0_sharing.v b/hdl/smaesh_hpc/MSKbit0_sharing.sv
similarity index 100%
rename from hdl/smaesh_hpc/MSKbit0_sharing.v
rename to hdl/smaesh_hpc/MSKbit0_sharing.sv
diff --git a/hdl/smaesh_hpc/MSKdata_holder_low_level.v b/hdl/smaesh_hpc/MSKdata_holder_low_level.sv
similarity index 100%
rename from hdl/smaesh_hpc/MSKdata_holder_low_level.v
rename to hdl/smaesh_hpc/MSKdata_holder_low_level.sv
diff --git a/hdl/smaesh_hpc/MSKkey_holder.v b/hdl/smaesh_hpc/MSKkey_holder.sv
similarity index 100%
rename from hdl/smaesh_hpc/MSKkey_holder.v
rename to hdl/smaesh_hpc/MSKkey_holder.sv
diff --git a/hdl/smaesh_hpc/MSKrefresh_tree.v b/hdl/smaesh_hpc/MSKrefresh_tree.sv
similarity index 100%
rename from hdl/smaesh_hpc/MSKrefresh_tree.v
rename to hdl/smaesh_hpc/MSKrefresh_tree.sv
diff --git a/hdl/smaesh_hpc/mixcolumn/MSKaesMC.v b/hdl/smaesh_hpc/mixcolumn/MSKaesMC.sv
similarity index 100%
rename from hdl/smaesh_hpc/mixcolumn/MSKaesMC.v
rename to hdl/smaesh_hpc/mixcolumn/MSKaesMC.sv
diff --git a/hdl/smaesh_hpc/mixcolumn/MSKaesMC_inverse.v b/hdl/smaesh_hpc/mixcolumn/MSKaesMC_inverse.sv
similarity index 100%
rename from hdl/smaesh_hpc/mixcolumn/MSKaesMC_inverse.v
rename to hdl/smaesh_hpc/mixcolumn/MSKaesMC_inverse.sv
diff --git a/hdl/smaesh_hpc/mixcolumn/aes_mc_single_column.v b/hdl/smaesh_hpc/mixcolumn/aes_mc_single_column.sv
similarity index 100%
rename from hdl/smaesh_hpc/mixcolumn/aes_mc_single_column.v
rename to hdl/smaesh_hpc/mixcolumn/aes_mc_single_column.sv
diff --git a/hdl/smaesh_hpc/mixcolumn/aes_mc_single_column_inverse.v b/hdl/smaesh_hpc/mixcolumn/aes_mc_single_column_inverse.sv
similarity index 100%
rename from hdl/smaesh_hpc/mixcolumn/aes_mc_single_column_inverse.v
rename to hdl/smaesh_hpc/mixcolumn/aes_mc_single_column_inverse.sv
diff --git a/hdl/smaesh_hpc/mixcolumn/xtime.v b/hdl/smaesh_hpc/mixcolumn/xtime.sv
similarity index 100%
rename from hdl/smaesh_hpc/mixcolumn/xtime.v
rename to hdl/smaesh_hpc/mixcolumn/xtime.sv
diff --git a/hdl/smaesh_hpc/rnd_gen/prng_top.v b/hdl/smaesh_hpc/rnd_gen/prng_top.sv
similarity index 100%
rename from hdl/smaesh_hpc/rnd_gen/prng_top.v
rename to hdl/smaesh_hpc/rnd_gen/prng_top.sv
diff --git a/hdl/smaesh_hpc/rnd_gen/trivium_prng.v b/hdl/smaesh_hpc/rnd_gen/trivium_prng.sv
similarity index 100%
rename from hdl/smaesh_hpc/rnd_gen/trivium_prng.v
rename to hdl/smaesh_hpc/rnd_gen/trivium_prng.sv
diff --git a/hdl/smaesh_hpc/sbox/gen_sbox.v b/hdl/smaesh_hpc/sbox/gen_sbox.sv
similarity index 100%
rename from hdl/smaesh_hpc/sbox/gen_sbox.v
rename to hdl/smaesh_hpc/sbox/gen_sbox.sv
diff --git a/hdl/smaesh_hpc/serial_shares_words_counter.v b/hdl/smaesh_hpc/serial_shares_words_counter.sv
similarity index 100%
rename from hdl/smaesh_hpc/serial_shares_words_counter.v
rename to hdl/smaesh_hpc/serial_shares_words_counter.sv
diff --git a/hdl/smaesh_hpc/shares2shbus.v b/hdl/smaesh_hpc/shares2shbus.sv
similarity index 100%
rename from hdl/smaesh_hpc/shares2shbus.v
rename to hdl/smaesh_hpc/shares2shbus.sv
diff --git a/hdl/smaesh_hpc/shbus2shares.v b/hdl/smaesh_hpc/shbus2shares.sv
similarity index 100%
rename from hdl/smaesh_hpc/shbus2shares.v
rename to hdl/smaesh_hpc/shbus2shares.sv
diff --git a/hdl/smaesh_hpc/smaesh_arbitrer.v b/hdl/smaesh_hpc/smaesh_arbitrer.sv
similarity index 100%
rename from hdl/smaesh_hpc/smaesh_arbitrer.v
rename to hdl/smaesh_hpc/smaesh_arbitrer.sv
diff --git a/hdl/smaesh_hpc/smaesh_hpc.v b/hdl/smaesh_hpc/smaesh_hpc.sv
similarity index 100%
rename from hdl/smaesh_hpc/smaesh_hpc.v
rename to hdl/smaesh_hpc/smaesh_hpc.sv