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What's going on here

On branch arm-sve, the library assume a register width, 256 (--enable-sve256) or 512 (--enable-sve) bits. Commit to pick at the moment for the basic stuff: e16fb9d029368c9b8c4212f660577fce47ccb3ff. This should work with the ARM HPC Compiler version 19.1 or newer. On that branch, newer commits add 'half-sve' when using --enable-sve, using masking to get 256-bits SIMD from a 512 bits register - this require ARM HPC Compiler version 19.3 or newer.

On branch arm-sve-alt, masking is always used. --enable-sve creates codelets for 128, 256 and 512 bits SIMD. They are only used if the hardware as a width equal or larger than the codelet. This requires ARM HPC Compiler version 19.3 or newer.

Branch riscv-v only add support for the RISC-V cycle counter (for RV64 & RV32).