diff --git a/hammer/technology/sky130/extra/sram22/sram-cache-gen.py b/hammer/technology/sky130/extra/sram22/sram-cache-gen.py index 667437463..d494fcb48 100755 --- a/hammer/technology/sky130/extra/sram22/sram-cache-gen.py +++ b/hammer/technology/sky130/extra/sram22/sram-cache-gen.py @@ -10,28 +10,25 @@ import sys import re import json +import os from typing import List def main(args: List[str]) -> int: if len(args) != 3: - print("Usage: ./sram-cache-gen.py list-of-srams-1-per-line.txt output-file.json") - print("E.g.: ./sram-cache-gen.py srams.txt sram-cache.json") + print("Usage: ./sram-cache-gen.py /path/to/sram22_sky130_macros output-file.json") + print("E.g.: ./sram-cache-gen.py /tools/C/me/sram22_sky130_macros sram-cache.json") return 1 - list_of_srams = [] # type: List[str] - with open(sys.argv[1]) as f: - for line in f: - list_of_srams.append(line) - - print(str(len(list_of_srams)) + " SRAMs to cache") + list_of_srams: List[str] = [d.name for d in os.scandir(sys.argv[1]) if d.is_dir()] + print(f"Found {len(list_of_srams)} SRAMS to cache") sram_dicts = [] for sram_name in list_of_srams: # SRAM22-generated single-port RAMs - if sram_name.startswith("sramgen_"): - match = re.match(r"sramgen_sram_(\d+)x(\d+)m(\d+)w(\d+)(\D*)", sram_name) + if sram_name.startswith("sram22_"): + match = re.match(r"^sram22_(\d+)x(\d+)m(\d+)w(\d+)$", sram_name) if match: width = int(match.group(2)) mask_gran = int(match.group(4)) @@ -56,7 +53,7 @@ def main(args: List[str]) -> int: port_dict['clock port polarity'] = "active high" port_dict['write enable port name'] = "we" - port_dict['write enable port polarity'] = "active high" # ??? + port_dict['write enable port polarity'] = "active high" port_dict['output port name'] = "dout" port_dict['output port polarity'] = "active high" @@ -74,11 +71,7 @@ def main(args: List[str]) -> int: sram_dicts.append(sram_dict.copy()) else: - print("Unsupported memory: {n}".format(n=sram_name), file=sys.stderr) - return 1 - else: - print("Unsupported memory: {n}".format(n=sram_name), file=sys.stderr) - return 1 + print("Skipping unsupported memory: {n}".format(n=sram_name), file=sys.stderr) with open(sys.argv[2], "w") as f: json.dump(sram_dicts, f, indent=2) diff --git a/hammer/technology/sky130/extra/sram22/sram-cache.json b/hammer/technology/sky130/extra/sram22/sram-cache.json index aa288f5cc..0738db46e 100644 --- a/hammer/technology/sky130/extra/sram22/sram-cache.json +++ b/hammer/technology/sky130/extra/sram22/sram-cache.json @@ -1,14 +1,14 @@ [ { "type": "sram", - "name": "sramgen_sram_32x32m2w8_replica_v1", + "name": "sram22_1024x32m8w8", "source": "sram22", - "depth": "32", + "depth": "1024", "width": 32, "family": "1rw", "mask": "true", "vt": "svt", - "mux": 2, + "mux": 8, "ports": [ { "address port name": "addr", @@ -29,7 +29,7 @@ }, { "type": "sram", - "name": "sramgen_sram_64x32m4w32_replica_v1", + "name": "sram22_64x32m4w32", "source": "sram22", "depth": "64", "width": 32, @@ -54,7 +54,32 @@ }, { "type": "sram", - "name": "sramgen_sram_512x32m4w8_replica_v1", + "name": "sram22_1024x32m8w32", + "source": "sram22", + "depth": "1024", + "width": 32, + "family": "1rw", + "mask": "true", + "vt": "svt", + "mux": 8, + "ports": [ + { + "address port name": "addr", + "address port polarity": "active high", + "clock port name": "clk", + "clock port polarity": "active high", + "write enable port name": "we", + "write enable port polarity": "active high", + "output port name": "dout", + "output port polarity": "active high", + "input port name": "din", + "input port polarity": "active high" + } + ] + }, + { + "type": "sram", + "name": "sram22_512x32m4w32", "source": "sram22", "depth": "512", "width": 32, @@ -62,6 +87,31 @@ "mask": "true", "vt": "svt", "mux": 4, + "ports": [ + { + "address port name": "addr", + "address port polarity": "active high", + "clock port name": "clk", + "clock port polarity": "active high", + "write enable port name": "we", + "write enable port polarity": "active high", + "output port name": "dout", + "output port polarity": "active high", + "input port name": "din", + "input port polarity": "active high" + } + ] + }, + { + "type": "sram", + "name": "sram22_2048x32m8w8", + "source": "sram22", + "depth": "2048", + "width": 32, + "family": "1rw", + "mask": "true", + "vt": "svt", + "mux": 8, "ports": [ { "address port name": "addr", @@ -82,14 +132,14 @@ }, { "type": "sram", - "name": "sramgen_sram_1024x32m8w8_replica_v1", + "name": "sram22_512x32m4w8", "source": "sram22", - "depth": "1024", + "depth": "512", "width": 32, "family": "1rw", "mask": "true", "vt": "svt", - "mux": 8, + "mux": 4, "ports": [ { "address port name": "addr", @@ -110,9 +160,9 @@ }, { "type": "sram", - "name": "sramgen_sram_1024x32m8w32_replica_v1", + "name": "sram22_4096x32m8w8", "source": "sram22", - "depth": "1024", + "depth": "4096", "width": 32, "family": "1rw", "mask": "true", @@ -129,20 +179,23 @@ "output port name": "dout", "output port polarity": "active high", "input port name": "din", - "input port polarity": "active high" + "input port polarity": "active high", + "mask port name": "wmask", + "mask granularity": 8, + "mask port polarity": "active high" } ] }, { "type": "sram", - "name": "sramgen_sram_1024x64m8w32_replica_v1", + "name": "sram22_64x4m4w2", "source": "sram22", - "depth": "1024", - "width": 64, + "depth": "64", + "width": 4, "family": "1rw", "mask": "true", "vt": "svt", - "mux": 8, + "mux": 4, "ports": [ { "address port name": "addr", @@ -156,21 +209,21 @@ "input port name": "din", "input port polarity": "active high", "mask port name": "wmask", - "mask granularity": 32, + "mask granularity": 2, "mask port polarity": "active high" } ] }, { "type": "sram", - "name": "sramgen_sram_2048x32m8w8_replica_v1", + "name": "sram22_256x32m4w8", "source": "sram22", - "depth": "2048", + "depth": "256", "width": 32, "family": "1rw", "mask": "true", "vt": "svt", - "mux": 8, + "mux": 4, "ports": [ { "address port name": "addr", @@ -191,7 +244,7 @@ }, { "type": "sram", - "name": "sramgen_sram_4096x8m8w8_replica_v1", + "name": "sram22_4096x8m8w8", "source": "sram22", "depth": "4096", "width": 8, @@ -216,14 +269,67 @@ }, { "type": "sram", - "name": "sramgen_sram_4096x32m8w8_replica_v1", + "name": "sram22_64x32m4w8", "source": "sram22", - "depth": "4096", + "depth": "64", "width": 32, "family": "1rw", "mask": "true", "vt": "svt", - "mux": 8, + "mux": 4, + "ports": [ + { + "address port name": "addr", + "address port polarity": "active high", + "clock port name": "clk", + "clock port polarity": "active high", + "write enable port name": "we", + "write enable port polarity": "active high", + "output port name": "dout", + "output port polarity": "active high", + "input port name": "din", + "input port polarity": "active high", + "mask port name": "wmask", + "mask granularity": 8, + "mask port polarity": "active high" + } + ] + }, + { + "type": "sram", + "name": "sram22_64x24m4w24", + "source": "sram22", + "depth": "64", + "width": 24, + "family": "1rw", + "mask": "true", + "vt": "svt", + "mux": 4, + "ports": [ + { + "address port name": "addr", + "address port polarity": "active high", + "clock port name": "clk", + "clock port polarity": "active high", + "write enable port name": "we", + "write enable port polarity": "active high", + "output port name": "dout", + "output port polarity": "active high", + "input port name": "din", + "input port polarity": "active high" + } + ] + }, + { + "type": "sram", + "name": "sram22_512x64m4w8", + "source": "sram22", + "depth": "512", + "width": 64, + "family": "1rw", + "mask": "true", + "vt": "svt", + "mux": 4, "ports": [ { "address port name": "addr", diff --git a/hammer/technology/sky130/extra/sram22/srams.txt b/hammer/technology/sky130/extra/sram22/srams.txt deleted file mode 100644 index 8383b8e4a..000000000 --- a/hammer/technology/sky130/extra/sram22/srams.txt +++ /dev/null @@ -1,9 +0,0 @@ -sramgen_sram_32x32m2w8_replica_v1 -sramgen_sram_64x32m4w32_replica_v1 -sramgen_sram_512x32m4w8_replica_v1 -sramgen_sram_1024x32m8w8_replica_v1 -sramgen_sram_1024x32m8w32_replica_v1 -sramgen_sram_1024x64m8w32_replica_v1 -sramgen_sram_2048x32m8w8_replica_v1 -sramgen_sram_4096x8m8w8_replica_v1 -sramgen_sram_4096x32m8w8_replica_v1 \ No newline at end of file diff --git a/hammer/technology/sky130/sram_compiler/__init__.py b/hammer/technology/sky130/sram_compiler/__init__.py index 7185d341b..e710304e1 100644 --- a/hammer/technology/sky130/sram_compiler/__init__.py +++ b/hammer/technology/sky130/sram_compiler/__init__.py @@ -37,7 +37,7 @@ def generate_sram(self, params: SRAMParameters, corner: MMMCCorner) -> ExtraLibr self.logger.error("SKY130 SRAM cache does not support family:{f}".format(f=params.family)) return ExtraLibrary(prefix=None, library=None) # type: ignore - if params.name.startswith("sramgen_sram"): + if params.name.startswith("sram22"): self.logger.info(f"Compiling {params.family} memories to SRAM22 instances") # s=round(round(params.width*params.depth/8, -3)/1000) # size in kiB w=params.width @@ -52,10 +52,19 @@ def generate_sram(self, params: SRAMParameters, corner: MMMCCorner) -> ExtraLibr # temp = str(int(corner.temp.value_in_units("C"))).replace(".","p")) base_dir=self.get_setting('technology.sky130.sram22_sky130_macros') - lib_path="{b}/{n}/{n}_{c}.lib".format(b=base_dir,n=sram_name,c=corner_str) - if not os.path.exists(lib_path): - self.logger.error(f"SKY130 {params.family} SRAM cache does not support corner: {corner_str}") - + + found = False + for fidelity in ["rcc", "rc", "c"]: + lib_path="{b}/{n}/{n}_{c}.{f}.lib".format(b=base_dir,n=sram_name,c=corner_str, f=fidelity) + if os.path.exists(lib_path): + found = True + break + else: + self.logger.warning(f"SKY130 {params.name} SRAM cache does not support corner {corner_str} with {fidelity} extraction") + + if not found: + self.logger.error(f"SKY130 {params.name} SRAM cache does not support corner {corner_str}") + return ExtraLibrary(prefix=None, library=Library( name=sram_name, nldm_liberty_file=lib_path,