-
Notifications
You must be signed in to change notification settings - Fork 1
/
Copy pathi2s_ns0921.eda.rpt
95 lines (79 loc) · 5.75 KB
/
i2s_ns0921.eda.rpt
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
EDA Netlist Writer report for i2s_ns0921
Fri Jul 16 09:28:16 2021
Quartus Prime Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. EDA Netlist Writer Summary
3. Simulation Settings
4. Simulation Generated Files
5. EDA Netlist Writer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Altera and sold by Altera or its
authorized distributors. Please refer to the applicable
agreement for further details.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Fri Jul 16 09:28:16 2021 ;
; Revision Name ; i2s_ns0921 ;
; Top-level Entity Name ; i2s_ns0921 ;
; Family ; MAX II ;
; Simulation Files Creation ; Successful ;
+---------------------------+---------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Option ; Setting ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Tool Name ; ModelSim-Altera (Verilog) ;
; Generate netlist for functional simulation only ; Off ;
; Time scale ; 1 ps ;
; Truncate long hierarchy paths ; Off ;
; Map illegal HDL characters ; Off ;
; Flatten buses into individual nodes ; Off ;
; Maintain hierarchy ; Off ;
; Bring out device-wide set/reset signals as ports ; Off ;
; Enable glitch filtering ; Off ;
; Do not write top level VHDL entity ; Off ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
; Architecture name in VHDL output netlist ; structure ;
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
+---------------------------------------------------------------------------------------------------+---------------------------+
+--------------------------------------------------------------------+
; Simulation Generated Files ;
+--------------------------------------------------------------------+
; Generated Files ;
+--------------------------------------------------------------------+
; /home/naoki/altera/i2s_ns0921/simulation/modelsim/i2s_ns0921.vo ;
; /home/naoki/altera/i2s_ns0921/simulation/modelsim/i2s_ns0921_v.sdo ;
+--------------------------------------------------------------------+
+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
Info: Processing started: Fri Jul 16 09:28:14 2021
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off i2s_ns0921 -c i2s_ns0921
Info (204018): Generated files "i2s_ns0921.vo" and "i2s_ns0921_v.sdo" in directory "/home/naoki/altera/i2s_ns0921/simulation/modelsim/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 1231 megabytes
Info: Processing ended: Fri Jul 16 09:28:16 2021
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01