From f9a073f7817d8dd427315d6574a6db304bb8dc93 Mon Sep 17 00:00:00 2001
From: Pietra Ferreira <pietra.ferreira@embecosm.com>
Date: Fri, 21 Aug 2020 08:45:47 +0100
Subject: [PATCH] Added support for CORE-V hardware loop

Added two relocations REL12 and RELU5, the CORE-V INSN_CLASSes, the MATCH
and MASKs and the hardware loop instructions.

bfd/ChangeLog:

	* bfd-in2.h: Added CORE-V hardware loop specific relocations.
	* elfnn-riscv.c: Added relocations for CORE-V hardware loop.
	* elfxx-riscv.c: Added relocations and amend howto lookup.
	* riscv.c: Added BFD_RELOC_RISCV_CVPCREL_UI12 and
	BFD_RELOC_RISCV_CVPCREL_URS1.

gas/ChangeLog:

	* config/tc-riscv.c: Added CORE-V harware loop support.
	* config/tc-riscv.h: Likewise.
	* doc/c-riscv.texi: Noted Xcorev as additional ISA extension
	for CORE-V.

gas/testsuite/ChangeLog:

	* gas/riscv/cv-hwloop-01.d: Added new test.
	* gas/riscv/cv-hwloop-01.l: Likewise.
	* gas/riscv/cv-hwloop-01.s: Likewise.
	* gas/riscv/cv-hwloop-02.d: Likewise.
	* gas/riscv/cv-hwloop-02.l: Likewise.
	* gas/riscv/cv-hwloop-02.s: Likewise.
	* gas/riscv/cv-hwloop-03.d: Likewise.
	* gas/riscv/cv-hwloop-03.l: Likewise.
	* gas/riscv/cv-hwloop-03.s: Likewise.
	* gas/riscv/cv-hwloop-04.d: Likewise.
	* gas/riscv/cv-hwloop-04.l: Likewise.
	* gas/riscv/cv-hwloop-04.s: Likewise.
	* gas/riscv/cv-hwloop-05.d: Likewise.
	* gas/riscv/cv-hwloop-05.l: Likewise.
	* gas/riscv/cv-hwloop-05.s: Likewise.
	* gas/riscv/cv-hwloop-06.d: Likewise.
	* gas/riscv/cv-hwloop-06.l: Likewise.
	* gas/riscv/cv-hwloop-06.s: Likewise.
	* gas/riscv/cv-hwloop-07.d: Likewise.
	* gas/riscv/cv-hwloop-07.l: Likewise.
	* gas/riscv/cv-hwloop-07.s: Likewise.
	* gas/riscv/cv-hwloop-08.d: Likewise.
	* gas/riscv/cv-hwloop-08.l: Likewise.
	* gas/riscv/cv-hwloop-08.s: Likewise.
	* gas/riscv/cv-hwloop-count.d: Likewise.
	* gas/riscv/cv-hwloop-count.s: Likewise.
	* gas/riscv/cv-hwloop-counti.d: Likewise.
	* gas/riscv/cv-hwloop-counti.s: Likewise.
	* gas/riscv/cv-hwloop-endi.d: Likewise.
	* gas/riscv/cv-hwloop-endi.s: Likewise.
	* gas/riscv/cv-hwloop-setup.d: Likewise.
	* gas/riscv/cv-hwloop-setup.s: Likewise.
	* gas/riscv/cv-hwloop-setupi.d: Likewise.
	* gas/riscv/cv-hwloop-setupi.s: Likewise.
	* gas/riscv/cv-hwloop-starti.d: Likewise.
	* gas/riscv/cv-hwloop-starti.s: Likewise.
	* gas/riscv/cv-hwloop-09.d: Likewise.
	* gas/riscv/cv-hwloop-09.l: Likewise.
	* gas/riscv/cv-hwloop-09.s: Likewise.
	* gas/riscv/cv-hwloop-10.d: Likewise.
	* gas/riscv/cv-hwloop-10.l: Likewise.
	* gas/riscv/cv-hwloop-10.s: Likewise.

include/ChangeLog:

	* elf/riscv.h: Added CORE-V hardware loop specific relocations.
	* opcode/riscv.h: Added CORE-V hardware loop specific masks and
	CORE-V instruction class. Added macros for unsigned I type
	immediate and loop number.

ld/ChangeLog:

	* emultempl/riscvelf.em: Added initial CORE-V support.

ld/testsuite/ChangeLog:

	* ld-riscv-elf/ld-riscv-elf.exp: Added CORE-V hardware loop
	  tests.
	* ld-riscv-elf/cv-hwloop-starti.s: Added new test.
	* ld-riscv-elf/cv-hwloop-starti.d: Likewise.
	* ld-riscv-elf/cv-hwloop-endi.d: Likewise.
	* ld-riscv-elf/cv-hwloop-endi.s: Likewise.
	* ld-riscv-elf/cv-hwloop-setup.d: Likewise.
	* ld-riscv-elf/cv-hwloop-setup.s: Likewise.
	* ld-riscv-elf/cv-hwloop-setupi.d: Likewise.
	* ld-riscv-elf/cv-hwloop-setupi.s: Likewise.

opcodes/ChangeLog:

	* riscv-dis.c: Added CORE-V hardware loop support.
	* riscv-opc.c: Likewise.

Signed-off-by: Mary Bennett <mary.bennett@embecosm.com>

Added new boundary tests & fixed boundary check bug in hwloop & mac

Signed-off-by: Jessica Mills <jessica.mills@embecosm.com>

RISC-V: Fixed the overflow values for cv relocations

Issue #73: https://github.com/openhwgroup/corev-binutils-gdb/issues/73

The issue describes a problem with the hardware loop relocations; they do
not properly check for overflow. The function bfd_check_overflow in
bfd/reloc.c was used to check for overflow by the assembler. It has now
been moved to the linker.

Files Changed:

 * bfd/elfnn-riscv.c (perform_relocation): Added overflow check for
   R_RELOC_RISCV_CVPCREL_UI12 and R_RELOC_RISCV_CVPCREL_URS1.
 * gas/config/tc-riscv.c(md_apply_fix): Removed the assembler
   relocation overflow check for R_RELOC_RISCV_CVPCREL_UI12 and
   R_RELOC_RISCV_CVPCREL_URS1.

ld/testsuite/ld-riscv-elf:
 * cv-hwlp-pass.d: New test.
 * cv-hwlp-pass.s: Likewise.
 * cv-hwlp-setupi-2.d: Likewise.
 * cv-hwlp-setupi-2.s: Likewise.
 * cv-hwlp-setupi-fail.d: Likewise.
 * cv-hwlp-setupi-fail.l: Likewise.
 * cv-hwlp-setupi-fail.s: Likewise.
 * cv-hwlp-starti-2.d: Likewise.
 * cv-hwlp-starti-2.s: Likewise.
 * cv-hwlp-starti-fail.d: Likewise.
 * cv-hwlp-starti-fail.l: Likewise.
 * cv-hwlp-starti-fail.s: Likewise.
 * ld-riscv-elf.exp: Likewise.
---
 bfd/ChangeLog.COREV                           |  17 +
 bfd/bfd-in2.h                                 |   4 +
 bfd/elfnn-riscv.c                             |  31 ++
 bfd/elfxx-riscv.c                             |  84 +++--
 bfd/libbfd.h                                  |   2 +
 bfd/reloc.c                                   |   7 +
 gas/ChangeLog.COREV                           |  36 ++
 gas/config/tc-riscv.c                         | 174 ++++++++-
 gas/doc/c-riscv.texi                          |   5 +
 gas/testsuite/ChangeLog.COREV                 | 330 ++++++++++++++++++
 gas/testsuite/gas/riscv/cv-hwlp-count.d       |  12 +
 gas/testsuite/gas/riscv/cv-hwlp-count.s       |   4 +
 gas/testsuite/gas/riscv/cv-hwlp-counti.d      |  12 +
 gas/testsuite/gas/riscv/cv-hwlp-counti.s      |   4 +
 gas/testsuite/gas/riscv/cv-hwlp-end.d         |  12 +
 gas/testsuite/gas/riscv/cv-hwlp-end.s         |   4 +
 gas/testsuite/gas/riscv/cv-hwlp-endi.d        |  13 +
 gas/testsuite/gas/riscv/cv-hwlp-endi.s        |   5 +
 gas/testsuite/gas/riscv/cv-hwlp-fail-march.d  |   3 +
 gas/testsuite/gas/riscv/cv-hwlp-fail-march.l  |   8 +
 gas/testsuite/gas/riscv/cv-hwlp-fail-march.s  |   8 +
 .../gas/riscv/cv-hwlp-fail-operand-01.d       |   3 +
 .../gas/riscv/cv-hwlp-fail-operand-01.l       |  13 +
 .../gas/riscv/cv-hwlp-fail-operand-01.s       |  14 +
 .../gas/riscv/cv-hwlp-fail-operand-02.d       |   3 +
 .../gas/riscv/cv-hwlp-fail-operand-02.l       |   4 +
 .../gas/riscv/cv-hwlp-fail-operand-02.s       |   5 +
 .../gas/riscv/cv-hwlp-fail-operand-03.d       |   3 +
 .../gas/riscv/cv-hwlp-fail-operand-03.l       |   5 +
 .../gas/riscv/cv-hwlp-fail-operand-03.s       |   6 +
 .../gas/riscv/cv-hwlp-fail-operand-04.d       |   3 +
 .../gas/riscv/cv-hwlp-fail-operand-04.l       |   3 +
 .../gas/riscv/cv-hwlp-fail-operand-04.s       |   4 +
 .../gas/riscv/cv-hwlp-fail-operand-05.d       |   3 +
 .../gas/riscv/cv-hwlp-fail-operand-05.l       |  34 ++
 .../gas/riscv/cv-hwlp-fail-operand-05.s       |  34 ++
 .../gas/riscv/cv-hwlp-fail-operand-06.d       |   3 +
 .../gas/riscv/cv-hwlp-fail-operand-06.l       |   9 +
 .../gas/riscv/cv-hwlp-fail-operand-06.s       |  10 +
 .../gas/riscv/cv-hwlp-fail-operand-07.d       |   3 +
 .../gas/riscv/cv-hwlp-fail-operand-07.l       |   4 +
 .../gas/riscv/cv-hwlp-fail-operand-07.s       |   5 +
 .../gas/riscv/cv-hwlp-fail-operand-08.d       |   3 +
 .../gas/riscv/cv-hwlp-fail-operand-08.l       |   3 +
 .../gas/riscv/cv-hwlp-fail-operand-08.s       |   4 +
 .../gas/riscv/cv-hwlp-fail-operand-09.d       |   3 +
 .../gas/riscv/cv-hwlp-fail-operand-09.l       |   5 +
 .../gas/riscv/cv-hwlp-fail-operand-09.s       |   6 +
 .../gas/riscv/cv-hwlp-fail-operand-10.d       |   3 +
 .../gas/riscv/cv-hwlp-fail-operand-10.l       |   3 +
 .../gas/riscv/cv-hwlp-fail-operand-10.s       |   4 +
 .../gas/riscv/cv-hwlp-fail-operand-11.d       |   3 +
 .../gas/riscv/cv-hwlp-fail-operand-11.l       |   2 +
 .../gas/riscv/cv-hwlp-fail-operand-11.s       |   3 +
 gas/testsuite/gas/riscv/cv-hwlp-setup.d       |  13 +
 gas/testsuite/gas/riscv/cv-hwlp-setup.s       |   5 +
 gas/testsuite/gas/riscv/cv-hwlp-setupi.d      |  12 +
 gas/testsuite/gas/riscv/cv-hwlp-setupi.s      |   4 +
 gas/testsuite/gas/riscv/cv-hwlp-start.d       |  12 +
 gas/testsuite/gas/riscv/cv-hwlp-start.s       |   4 +
 gas/testsuite/gas/riscv/cv-hwlp-starti.d      |  13 +
 gas/testsuite/gas/riscv/cv-hwlp-starti.s      |   5 +
 include/ChangeLog.COREV                       |  26 ++
 include/elf/riscv.h                           |   3 +
 include/opcode/riscv-opc.h                    |  25 ++
 include/opcode/riscv.h                        |  19 +
 ld/ChangeLog.COREV                            |   3 +
 ld/testsuite/ChangeLog.COREV                  |  32 ++
 ld/testsuite/ld-riscv-elf/cv-hwlp-endi.d      |  21 ++
 ld/testsuite/ld-riscv-elf/cv-hwlp-endi.s      |  11 +
 ld/testsuite/ld-riscv-elf/cv-hwlp-pass.d      |  83 +++++
 ld/testsuite/ld-riscv-elf/cv-hwlp-pass.s      |  33 ++
 ld/testsuite/ld-riscv-elf/cv-hwlp-setup.d     |  21 ++
 ld/testsuite/ld-riscv-elf/cv-hwlp-setup.s     |  11 +
 ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-2.d  |  13 +
 ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-2.s  |  42 +++
 .../ld-riscv-elf/cv-hwlp-setupi-fail.d        |   4 +
 .../ld-riscv-elf/cv-hwlp-setupi-fail.l        |   2 +
 .../ld-riscv-elf/cv-hwlp-setupi-fail.s        |  23 ++
 ld/testsuite/ld-riscv-elf/cv-hwlp-setupi.d    |  21 ++
 ld/testsuite/ld-riscv-elf/cv-hwlp-setupi.s    |  11 +
 ld/testsuite/ld-riscv-elf/cv-hwlp-starti-2.d  |  15 +
 ld/testsuite/ld-riscv-elf/cv-hwlp-starti-2.s  | 276 +++++++++++++++
 .../ld-riscv-elf/cv-hwlp-starti-fail.d        |   4 +
 .../ld-riscv-elf/cv-hwlp-starti-fail.l        |   2 +
 .../ld-riscv-elf/cv-hwlp-starti-fail.s        | 113 ++++++
 ld/testsuite/ld-riscv-elf/cv-hwlp-starti.d    |  21 ++
 ld/testsuite/ld-riscv-elf/cv-hwlp-starti.s    |  11 +
 ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp    |   9 +
 opcodes/ChangeLog.COREV                       |  20 ++
 opcodes/riscv-dis.c                           |  39 ++-
 opcodes/riscv-opc.c                           |  10 +
 92 files changed, 1950 insertions(+), 30 deletions(-)
 create mode 100644 bfd/ChangeLog.COREV
 create mode 100644 gas/ChangeLog.COREV
 create mode 100644 gas/testsuite/ChangeLog.COREV
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-count.d
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-count.s
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-counti.d
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-counti.s
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-end.d
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-end.s
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-endi.d
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-endi.s
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-march.d
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-march.l
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-march.s
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-01.d
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-01.l
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-01.s
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-02.d
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-02.l
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-02.s
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-03.d
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-03.l
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-03.s
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-04.d
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-04.l
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-04.s
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-05.d
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-05.l
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-05.s
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-06.d
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-06.l
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-06.s
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-07.d
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-07.l
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-07.s
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-08.d
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-08.l
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-08.s
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-09.d
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-09.l
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-09.s
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-10.d
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-10.l
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-10.s
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-11.d
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-11.l
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-fail-operand-11.s
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-setup.d
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-setup.s
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-setupi.d
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-setupi.s
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-start.d
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-start.s
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-starti.d
 create mode 100644 gas/testsuite/gas/riscv/cv-hwlp-starti.s
 create mode 100644 include/ChangeLog.COREV
 create mode 100644 ld/ChangeLog.COREV
 create mode 100644 ld/testsuite/ChangeLog.COREV
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-hwlp-endi.d
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-hwlp-endi.s
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-hwlp-pass.d
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-hwlp-pass.s
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-hwlp-setup.d
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-hwlp-setup.s
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-2.d
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-2.s
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-fail.d
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-fail.l
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-fail.s
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-hwlp-setupi.d
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-hwlp-setupi.s
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-hwlp-starti-2.d
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-hwlp-starti-2.s
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-hwlp-starti-fail.d
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-hwlp-starti-fail.l
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-hwlp-starti-fail.s
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-hwlp-starti.d
 create mode 100644 ld/testsuite/ld-riscv-elf/cv-hwlp-starti.s
 create mode 100644 opcodes/ChangeLog.COREV

diff --git a/bfd/ChangeLog.COREV b/bfd/ChangeLog.COREV
new file mode 100644
index 00000000000..70a10306033
--- /dev/null
+++ b/bfd/ChangeLog.COREV
@@ -0,0 +1,17 @@
+2020-11-10  Mary Bennett  <mary.bennett@embecosm.com>
+
+	* elfnn-riscv.c (perform_relocation): Renamed macros for clarity -
+	ENCODE_I1TYPE_UIMM -> ENCODE_CV_HWLP_UIMM5
+	ENCODE_I1TYPE_LN   -> ENCODE_CV_HWLP_LN
+	* elfxx-riscv.c: Renamed macros for clarity -
+	EXTRACT_I1TYPE_UIMM-> EXTRACT_CV_HWLP_UIMM5
+	EXTRACT_I1TYPE_LN  -> EXTRACT_CV_HWLP_LN
+	EXTRACT_ITYPE_UIMM -> EXTRACT_CV_HWLP_UIMM12
+
+2020-09-10  Pietra Ferreira  <pietra.ferreira@embecosm.com>
+
+	* bfd-in2.h: Added CORE-V hardware loop specific relocations.
+	* elfnn-riscv.c: Added relocations for CORE-V hardware loop.
+	* elfxx-riscv.c: Added relocations and amend howto lookup.
+	* bfd/riscv.c: Added BFD_RELOC_RISCV_CVPCREL_UI12 and
+	BFD_RELOC_RISCV_CVPCREL_URS1.
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 1c4f75ae244..ae85fc11839 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -5441,6 +5441,10 @@ number for the SBIC, SBIS, SBI and CBI instructions  */
   BFD_RELOC_RISCV_SET_ULEB128,
   BFD_RELOC_RISCV_SUB_ULEB128,
 
+/* CORE-V relocations.  */
+  BFD_RELOC_RISCV_CVPCREL_UI12,
+  BFD_RELOC_RISCV_CVPCREL_URS1,
+
 /* Renesas RL78 Relocations.  */
   BFD_RELOC_RL78_NEG8,
   BFD_RELOC_RL78_NEG16,
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index 09aa7be225e..4459d2feccf 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -4,6 +4,13 @@
    Contributed by Andrew Waterman (andrew@sifive.com).
    Based on TILE-Gx and MIPS targets.
 
+   Modified for CORE-V by:
+   Mary Bennett (mary.bennett@embecosm.com)
+   Pietra Ferreira (pietra.ferreira@embecosm.com)
+   Jessica Mills (jessica.mills@embecosm.com)
+
+   Some of these changes are (C) Open Hardware Group, pending FSF assignment.
+
    This file is part of BFD, the Binary File Descriptor library.
 
    This program is free software; you can redistribute it and/or modify
@@ -1752,6 +1759,27 @@ perform_relocation (const reloc_howto_type *howto,
       value = ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
       break;
 
+    /* CORE-V Specific Relocations.  */
+    case R_RISCV_CVPCREL_UI12:
+      if (bfd_check_overflow (howto->complain_on_overflow, 12, 0,
+	    bfd_get_reloc_size (howto) * 8, value >> howto->rightshift)
+		     != bfd_reloc_overflow)
+      {
+        value = ENCODE_ITYPE_IMM (value >> howto->rightshift);
+        break;
+      }
+      return bfd_reloc_overflow;
+
+    case R_RISCV_CVPCREL_URS1:
+      if (bfd_check_overflow (howto->complain_on_overflow, 5, 0,
+	    bfd_get_reloc_size (howto) * 8, value >> howto->rightshift)
+		     != bfd_reloc_overflow)
+      {
+	value = ENCODE_CV_HWLP_UIMM5 (value >> howto->rightshift);
+	break;
+      }
+      return bfd_reloc_overflow;
+
     case R_RISCV_LO12_I:
     case R_RISCV_GPREL_I:
     case R_RISCV_TPREL_LO12_I:
@@ -2500,6 +2528,9 @@ riscv_elf_relocate_section (bfd *output_bfd,
 	case R_RISCV_SET32:
 	case R_RISCV_32_PCREL:
 	case R_RISCV_DELETE:
+	/* CORE-V Specific.  */
+	case R_RISCV_CVPCREL_URS1:
+	case R_RISCV_CVPCREL_UI12:
 	  /* These require no special handling beyond perform_relocation.  */
 	  break;
 
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 5e78bc7873f..121ea23051c 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -879,6 +879,37 @@ static reloc_howto_type howto_table[] =
 	 0,				/* src_mask */
 	 0,				/* dst_mask */
 	 false),			/* pcrel_offset */
+
+  /* CORE-V Specific.  */
+  /* 12-bit PC-relative offset, for hwloop.  */
+  HOWTO (R_RISCV_CVPCREL_UI12,		/* type */
+	 2,				/* rightshift */
+	 2,				/* size */
+	 32,				/* bitsize */
+	 true,				/* pc_relative */
+	 0,				/* bitpos */
+	 complain_overflow_unsigned,	/* complain_on_overflow */
+	 bfd_elf_generic_reloc,		/* special_function */
+	 "R_RISCV_CVPCREL_UI12",	/* name */
+	 false,				/* partial_inplace */
+	 0,				/* src_mask */
+	 ENCODE_ITYPE_IMM (-1U),	/* dst_mask */
+	 true),				/* pcrel_offset */
+
+  /* Unsigned 5-bit PC-relative offset, for hwloop.  */
+  HOWTO (R_RISCV_CVPCREL_URS1,		/* type */
+	 2,				/* rightshift */
+	 1,				/* size */
+	 32,				/* bitsize */
+	 true,				/* pc_relative */
+	 0,				/* bitpos */
+	 complain_overflow_unsigned,	/* complain_on_overflow */
+	 bfd_elf_generic_reloc,		/* special_function */
+	 "R_RISCV_CVPCREL_URS1",	/* name */
+	 false,				/* partial_inplace */
+	 0,				/* src_mask */
+	 ENCODE_CV_HWLP_UIMM5 (-1U),	/* dst_mask */
+	 true),				/* pcrel_offset */
 };
 
 /* A mapping from BFD reloc types to RISC-V ELF reloc types.  */
@@ -942,47 +973,53 @@ static const struct elf_reloc_map riscv_reloc_map[] =
   { BFD_RELOC_RISCV_32_PCREL, R_RISCV_32_PCREL },
   { BFD_RELOC_RISCV_SET_ULEB128, R_RISCV_SET_ULEB128 },
   { BFD_RELOC_RISCV_SUB_ULEB128, R_RISCV_SUB_ULEB128 },
+  /* CORE-V Specific.  */
+  { BFD_RELOC_RISCV_CVPCREL_UI12, R_RISCV_CVPCREL_UI12 },
+  { BFD_RELOC_RISCV_CVPCREL_URS1, R_RISCV_CVPCREL_URS1 },
 };
 
-/* Given a BFD reloc type, return a howto structure.  */
-
 reloc_howto_type *
-riscv_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
-			 bfd_reloc_code_real_type code)
+riscv_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name)
 {
   unsigned int i;
 
-  for (i = 0; i < ARRAY_SIZE (riscv_reloc_map); i++)
-    if (riscv_reloc_map[i].bfd_val == code)
-      return &howto_table[(int) riscv_reloc_map[i].elf_val];
+  for (i = 0; i < ARRAY_SIZE (howto_table); i++)
+    if (howto_table[i].name && strcasecmp (howto_table[i].name, r_name) == 0)
+      return &howto_table[i];
 
-  bfd_set_error (bfd_error_bad_value);
   return NULL;
 }
 
 reloc_howto_type *
-riscv_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name)
+riscv_elf_rtype_to_howto (bfd *abfd, unsigned int r_type)
 {
   unsigned int i;
-
   for (i = 0; i < ARRAY_SIZE (howto_table); i++)
-    if (howto_table[i].name && strcasecmp (howto_table[i].name, r_name) == 0)
-      return &howto_table[i];
+    {
+      if (r_type == howto_table[i].type)
+	return &howto_table[i];
+    }
 
+  (*_bfd_error_handler) (_("%pB: unsupported relocation type %#x"),
+			 abfd, r_type);
+  bfd_set_error (bfd_error_bad_value);
   return NULL;
 }
 
+/* Given a BFD reloc type, return a howto structure.  */
+
 reloc_howto_type *
-riscv_elf_rtype_to_howto (bfd *abfd, unsigned int r_type)
+riscv_reloc_type_lookup (bfd *abfd,
+			 bfd_reloc_code_real_type code)
 {
-  if (r_type >= ARRAY_SIZE (howto_table))
-    {
-      (*_bfd_error_handler) (_("%pB: unsupported relocation type %#x"),
-			     abfd, r_type);
-      bfd_set_error (bfd_error_bad_value);
-      return NULL;
-    }
-  return &howto_table[r_type];
+  unsigned int i;
+
+  for (i = 0; i < ARRAY_SIZE (riscv_reloc_map); i++)
+    if (riscv_reloc_map[i].bfd_val == code)
+      return riscv_elf_rtype_to_howto(abfd, riscv_reloc_map[i].elf_val);
+
+  bfd_set_error (bfd_error_bad_value);
+  return NULL;
 }
 
 /* Special_function of RISCV_ADD and RISCV_SUB relocations.  */
@@ -1354,6 +1391,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
   /* CORE-V ISA extension spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html */
   {"xcvmac",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xcvalu",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xcvhwlp",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadba",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadbb",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadbs",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
@@ -2556,6 +2594,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xcvmac");
     case INSN_CLASS_XCVALU:
       return riscv_subset_supports (rps, "xcvalu");
+    case INSN_CLASS_XCVHWLP:
+      return riscv_subset_supports (rps, "xcvhwlp");
     case INSN_CLASS_XTHEADBA:
       return riscv_subset_supports (rps, "xtheadba");
     case INSN_CLASS_XTHEADBB:
@@ -2800,6 +2840,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "xcvmac";
     case INSN_CLASS_XCVALU:
       return "xcvalu";
+    case INSN_CLASS_XCVHWLP:
+      return "xcvhwlp";
     case INSN_CLASS_XTHEADBA:
       return "xtheadba";
     case INSN_CLASS_XTHEADBB:
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index d5f42f22c08..bc32564eef0 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -2422,6 +2422,8 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
   "BFD_RELOC_RISCV_32_PCREL",
   "BFD_RELOC_RISCV_SET_ULEB128",
   "BFD_RELOC_RISCV_SUB_ULEB128",
+  "BFD_RELOC_RISCV_CVPCREL_UI12",
+  "BFD_RELOC_RISCV_CVPCREL_URS1",
   "BFD_RELOC_RL78_NEG8",
   "BFD_RELOC_RL78_NEG16",
   "BFD_RELOC_RL78_NEG24",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index 2ac883d0eac..7ef9006a124 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -5055,6 +5055,13 @@ ENUMX
 ENUMDOC
   RISC-V relocations.
 
+ENUM
+  BFD_RELOC_RISCV_CVPCREL_UI12
+ENUMX
+  BFD_RELOC_RISCV_CVPCREL_URS1
+ENUMDOC
+  CORE-V relocations.
+
 ENUM
   BFD_RELOC_RL78_NEG8
 ENUMX
diff --git a/gas/ChangeLog.COREV b/gas/ChangeLog.COREV
new file mode 100644
index 00000000000..5014804f764
--- /dev/null
+++ b/gas/ChangeLog.COREV
@@ -0,0 +1,36 @@
+2021-08-23  Jessica Mills  <jessica.mills@embecosm.com>
+
+	* config/tc-riscv.c (riscv_ip): Fix boundary bug for hardware loop
+	branch operands - upper boundary of long branch offset changed from
+	4094 to 8191 and short offset from 30 to 63.
+
+2020-11-24  Jessica Mills  <jessica.mills@embecosm.com>
+
+	* doc/c-riscv.texi: Added details on CORE-V hardware loop,
+	multiply-accumulate and general ALU ops ISA options.
+
+2020-11-19  Jessica Mills  <jessica.mills@embecosm.com>
+
+	* config/tc-riscv.c: Fixed bug in hardware loop operand boundary
+	checks (b1 and b2).
+
+2020-11-10  Mary Bennett  <mary.bennett@embecosm.com>
+
+	* config/tc-riscv.c (validate_riscv_insn): Renamed macros for clarity -
+	ENCODE_I1TYPE_UIMM -> ENCODE_CV_HWLP_UIMM5
+	ENCODE_I1TYPE_LN   -> ENCODE_CV_HWLP_LN
+	* config/tc-riscv.c (md_apply_fix): Renamed macros for clarity -
+	ENCODE_I1TYPE_UIMM -> ENCODE_CV_HWLP_UIMM5
+
+2020-10-05  Mary Bennett <mary.bennett@embecosm.com>
+
+	* config/tc-riscv.c: Fixed issue arising from incorrect CORE-V
+	hardware loop masks and added support for xcorevhwlp and new
+	error messages.
+
+2020-09-10  Pietra Ferreira  <pietra.ferreira@embecosm.com>
+
+	* config/tc-riscv.c: Added CORE-V hardware loop support.
+	* config/tc-riscv.h: Likewise.
+	* doc/c-riscv.texi: Noted Xcorev as additional ISA extension
+	 for CORE-V.
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index a58471591fb..620a1291ad0 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -4,6 +4,13 @@
    Contributed by Andrew Waterman (andrew@sifive.com).
    Based on MIPS target.
 
+   Modified for CORE-V by:
+   Mary Bennett (mary.bennett@embecosm.com)
+   Pietra Ferreira (pietra.ferreira@embecosm.com)
+   Jessica Mills (jessica.mills@embecosm.com)
+
+   Some of these changes are (C) Open Hardware Group, pending FSF assignment.
+
    This file is part of GAS.
 
    GAS is free software; you can redistribute it and/or modify
@@ -1366,10 +1373,29 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 	case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
 	case 'A': break; /* Macro operand, must be symbol.  */
 	case 'B': break; /* Macro operand, must be symbol or constant.  */
+	case 'b': /* CORE-V Specific.  */
+	  if (oparg[1] == '1')
+	    {
+	      used_bits |= ENCODE_ITYPE_IMM(-1U);
+	      ++oparg; break;
+	    }
+	  else if (oparg[1] == '2')
+	    {
+	      used_bits |= ENCODE_CV_HWLP_UIMM5(-1U);
+	      ++oparg; break;
+	    }
+	  break;
 	case 'c': break; /* Macro operand, must be symbol or constant.  */
 	case 'I': break; /* Macro operand, must be constant.  */
 	case 'D': /* RD, floating point.  */
-	case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
+	case 'd': 
+	  if (oparg[1] == 'i')
+	    {
+	      used_bits |= ENCODE_CV_HWLP_LN(-1U);
+	      ++oparg;
+	      break;
+	    }    
+	  USE_BITS (OP_MASK_RD, OP_SH_RD); break;
 	case 'y': USE_BITS (OP_MASK_BS,	OP_SH_BS); break;
 	case 'Y': USE_BITS (OP_MASK_RNUM, OP_SH_RNUM); break;
 	case 'Z': /* RS1, CSR number.  */
@@ -1387,7 +1413,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 	case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
 	case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
 	case 'o': /* ITYPE immediate, load displacement.  */
-	case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
+	case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); if (oparg[1] == 'i') ++oparg; break;
 	case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break;
 	case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break;
 	case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
@@ -3213,6 +3239,19 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 	      break;
 
 	    case 'd': /* Destination register.  */
+	      if (oparg[1] == 'i')
+		{
+		  ++oparg;
+		  my_getExpression (imm_expr, asarg);
+		  asarg = expr_parse_end;
+		  if (imm_expr->X_op != O_constant ||
+		      imm_expr->X_add_number < 0 || imm_expr->X_add_number > 1)
+		    as_bad (_("%s loop number must be 0 or 1"),
+			    ip->insn_mo->name);
+		  INSERT_OPERAND (LN, *ip, imm_expr->X_add_number);
+		  continue;
+		}
+	      /* Fall through */
 	    case 's': /* Source register.  */
 	    case 't': /* Target register.  */
 	    case 'r': /* RS3 */
@@ -3295,7 +3334,80 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 	      *imm_reloc = BFD_RELOC_32;
 	      asarg = expr_parse_end;
 	      continue;
-
+	      /* CORE-V Specific.
+	         b1: pc rel 12 bits offset for cv.starti and cv.endi
+	             sign-extended immediate as pc rel displacement for hwloop
+	         b2: pc rel 5 bits unsigned offset for cv.setupi  */
+	    case 'b':
+	      if (oparg[1] == '1')
+		{
+		  ++oparg;
+		  my_getExpression (imm_expr, asarg);
+		  if ((imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant)
+		      || reg_lookup (&asarg, RCLASS_GPR, &regno))
+		    as_bad(_("%s immediate value must be a constant or label"),
+			   ip->insn_mo->name);
+		  if (imm_expr->X_op == O_constant)
+		    {
+		      asarg = expr_parse_end;
+		      if (imm_expr->X_add_number < 0 ||
+			  ((imm_expr->X_add_number>>2) > 4095))
+			as_bad (_("%ld constant out of range for %s, range:[0, %d]"),
+				imm_expr->X_add_number, ip->insn_mo->name, 16380);
+		      else if ((imm_expr->X_add_number % 4) != 0)
+			{
+			  as_warn (_("constant for %s must be a multiple of 4: "
+				     "%ld truncated to %ld"),
+				   ip->insn_mo->name, imm_expr->X_add_number,
+				   imm_expr->X_add_number-(imm_expr->X_add_number % 4));
+			  imm_expr->X_add_number--;
+			}
+		      INSERT_OPERAND (IMM12, *ip, (imm_expr->X_add_number>>2));
+		    }
+		  else
+		  {
+		    asarg = expr_parse_end;
+		    *imm_reloc = BFD_RELOC_RISCV_CVPCREL_UI12;
+		  }
+		}
+	      else if (oparg[1] == '2')
+		{
+		  ++oparg;
+		  my_getExpression (imm_expr, asarg);
+		  if ((imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant)
+		      || reg_lookup (&asarg, RCLASS_GPR, &regno))
+		    as_bad(_("%s immediate value must be a constant or label"),
+			   ip->insn_mo->name);
+		  asarg = expr_parse_end;
+		  if (imm_expr->X_op == O_constant)
+		    {
+		      asarg = expr_parse_end;
+		      if (imm_expr->X_add_number < 0 ||
+			  ((imm_expr->X_add_number>>2) > 31))
+			as_bad (_("%ld constant out of range for cv.setupi, "
+				  "range:[0, %d]"), imm_expr->X_add_number, 127);
+		      else if ((imm_expr->X_add_number % 4) != 0)
+			{
+			  as_warn (_("constant for cv.setupi must be a multiple of 4: "
+				     "%ld truncated to %ld"),
+				   imm_expr->X_add_number,
+				   imm_expr->X_add_number-(imm_expr->X_add_number % 4));
+			  imm_expr->X_add_number--;
+			}
+		      INSERT_OPERAND (IMM5, *ip, (imm_expr->X_add_number>>2));
+		    }
+		  else
+		  {
+		    asarg = expr_parse_end;
+		    *imm_reloc = BFD_RELOC_RISCV_CVPCREL_URS1;
+		  }
+		}
+	      else
+		{
+		  my_getExpression (imm_expr, asarg);
+		  asarg = expr_parse_end;
+		}
+	      continue;
 	    case 'B':
 	      my_getExpression (imm_expr, asarg);
 	      normalize_constant_expr (imm_expr);
@@ -3306,11 +3418,30 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 	        *imm_reloc = BFD_RELOC_32;
 	      asarg = expr_parse_end;
 	      continue;
-
-	    case 'j': /* Sign-extended immediate.  */
-	      p = percent_op_itype;
-	      *imm_reloc = BFD_RELOC_RISCV_LO12_I;
-	      goto alu_op;
+	    case 'j': /* Unsigned immediate.  */
+	      /* ji is CORE-V Specific.  */
+	      if (oparg[1] == 'i')
+		{
+		  /* immediate loop count, we don't want to use
+		     BFD_RELOC_RISCV_LO12_I to avoid colliding with relaxation */
+		  ++oparg;
+		  my_getExpression (imm_expr, asarg);
+		  check_absolute_expr (ip, imm_expr, FALSE);
+		  asarg = expr_parse_end;
+		  if (imm_expr->X_add_number >= (int) RISCV_IMM_REACH ||
+		      imm_expr->X_add_number < 0)
+		    as_bad (_("%ld constant out of range for %s, range:[0, %d]"),
+			    imm_expr->X_add_number, ip->insn_mo->name,
+			    ((int) RISCV_IMM_REACH) -1);
+		  INSERT_OPERAND (IMM12, *ip, imm_expr->X_add_number);
+		  continue;
+		}
+	      else
+		{
+		  p = percent_op_itype;
+		  *imm_reloc = BFD_RELOC_RISCV_LO12_I;
+		  goto alu_op;
+		}
 	    case 'q': /* Store displacement.  */
 	      p = percent_op_stype;
 	      *imm_reloc = BFD_RELOC_RISCV_LO12_S;
@@ -4249,6 +4380,33 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 	}
       break;
 
+    /* CORE-V Specific.  */
+    case BFD_RELOC_RISCV_CVPCREL_UI12:
+      if (fixP->fx_addsy)
+	{
+	  reloc_howto_type *howto;
+
+	  /* Fill in a tentative value to improve objdump readability.  */
+	  howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
+	  bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
+	  bfd_vma delta = (target - md_pcrel_from (fixP)) >> howto->rightshift;
+	  bfd_putl32 (bfd_getl32 (buf) | ENCODE_ITYPE_IMM (delta), buf);
+	}
+      break;
+
+    case BFD_RELOC_RISCV_CVPCREL_URS1:
+      if (fixP->fx_addsy)
+	{
+	  reloc_howto_type *howto;
+
+	  /* Fill in a tentative value to improve objdump readability.  */
+	  howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
+	  bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
+	  bfd_vma delta = (target - md_pcrel_from (fixP)) >> howto->rightshift;
+	  bfd_putl32 (bfd_getl32 (buf) | ENCODE_CV_HWLP_UIMM5 (delta), buf);
+	}
+      break;
+
     case BFD_RELOC_12_PCREL:
       if (fixP->fx_addsy)
 	{
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 6865caa1977..41fac1f29e3 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -755,6 +755,11 @@ The Xcvalu extension provides instructions for general ALU operations.
 
 It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
 
+@item Xcvhwlp
+The Xcvhwlp extension provides instructions for hardware loop operations.
+
+It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+
 @item XTheadBa
 The XTheadBa extension provides instructions for address calculations.
 
diff --git a/gas/testsuite/ChangeLog.COREV b/gas/testsuite/ChangeLog.COREV
new file mode 100644
index 00000000000..e9d46b06f75
--- /dev/null
+++ b/gas/testsuite/ChangeLog.COREV
@@ -0,0 +1,330 @@
+2021-08-23  Jessica Mills  <jessica.mills@embecosm.com>
+
+	* gas/riscv/cv-alu-extbs.d: Fix test after encoding change.
+	* gas/riscv/cv-alu-extbs.s: Likewise.
+	* gas/riscv/cv-alu-extbz.d: Likewise.
+	* gas/riscv/cv-alu-exths.d: Likewise.
+	* gas/riscv/cv-alu-exthz.d: Likewise.
+	* gas/riscv/cv-alu-march-rv32i-xcorev.d: Amend test with branch
+	offset boundary change.
+	* gas/riscv/cv-hwlp-endi.d: Likewise.
+	* gas/riscv/cv-hwlp-endi.s: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-01.l: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-01.s: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-02.l: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-02.s: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-03.l: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-03.s: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-04.l: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-04.s: Likewise.
+	* gas/riscv/cv-hwlp-setup.d: Likewise.
+	* gas/riscv/cv-hwlp-setup.s: Likewise.
+	* gas/riscv/cv-hwlp-starti.d: Likewise.
+	* gas/riscv/cv-hwlp-starti.s: Likewise.
+
+2021-01-15  Jessica Mills  <jessica.mills@embecosm.com>
+
+	* gas/riscv/cv-hwloop-count.d: Renamed to cv-hwlp-count.d.
+	* gas/riscv/cv-hwloop-count.s: Renamed to cv-hwlp-count.s.
+	* gas/riscv/cv-hwloop-counti.d: Renamed to cv-hwlp-counti.d.
+	* gas/riscv/cv-hwloop-counti.s: Renamed to cv-hwlp-counti.s.
+	* gas/riscv/cv-hwloop-endi.d: Renamed to cv-hwlp-endi.d.
+	* gas/riscv/cv-hwloop-endi.s: Renamed to cv-hwlp-endi.s.
+	* gas/riscv/cv-hwloop-setup.d: Renamed to cv-hwlp-setup.d.
+	* gas/riscv/cv-hwloop-setup.s: Renamed to cv-hwlp-setup.s.
+	* gas/riscv/cv-hwloop-setupi.d: Renamed to cv-hwlp-setupi.d.
+	* gas/riscv/cv-hwloop-setupi.s: Renamed to cv-hwlp-setupi.s.
+	* gas/riscv/cv-hwloop-starti.d: Renamed to cv-hwlp-starti.d.
+	* gas/riscv/cv-hwloop-starti.s: Renamed to cv-hwlp-starti.s.
+	* gas/riscv/cv-hwlp-fail-march.d: Added new test.
+	* gas/riscv/cv-hwlp-fail-march.l: Likewise.
+	* gas/riscv/cv-hwlp-fail-march.s: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-01.d: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-01.l: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-01.s: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-02.d: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-02.l: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-02.s: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-03.d: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-03.l: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-03.s: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-04.d: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-04.l: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-04.s: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-05.d: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-05.l: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-05.s: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-06.d: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-06.l: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-06.s: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-07.d: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-07.l: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-07.s: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-09.d: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-09.l: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-09.s: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-10.d: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-10.l: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-10.s: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-11.d: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-11.l: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-11.s: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-12.d: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-12.l: Likewise.
+	* gas/riscv/cv-hwlp-fail-operand-12.s: Likewise.
+	* gas/riscv/cv-hwloop-01.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-01.d.
+	* gas/riscv/cv-hwloop-01.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-01.l.
+	* gas/riscv/cv-hwloop-01.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-01.s.
+	* gas/riscv/cv-hwloop-02.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-01.d.
+	* gas/riscv/cv-hwloop-02.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-01.l.
+	* gas/riscv/cv-hwloop-02.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-01.s.
+	* gas/riscv/cv-hwloop-03.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-02.d.
+	* gas/riscv/cv-hwloop-03.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-02.l.
+	* gas/riscv/cv-hwloop-03.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-02.s.
+	* gas/riscv/cv-hwloop-04.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-03.d.
+	* gas/riscv/cv-hwloop-04.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-03.l.
+	* gas/riscv/cv-hwloop-04.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-03.s.
+	* gas/riscv/cv-hwloop-05.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-03.d.
+	* gas/riscv/cv-hwloop-05.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-03.l.
+	* gas/riscv/cv-hwloop-05.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-03.s.
+	* gas/riscv/cv-hwloop-06.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-04.d.
+	* gas/riscv/cv-hwloop-06.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-04.l.
+	* gas/riscv/cv-hwloop-06.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-04.s.
+	* gas/riscv/cv-hwloop-07.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-05.d.
+	* gas/riscv/cv-hwloop-07.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-05.l.
+	* gas/riscv/cv-hwloop-07.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-05.s.
+	* gas/riscv/cv-hwloop-08.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-05.d.
+	* gas/riscv/cv-hwloop-08.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-05.l.
+	* gas/riscv/cv-hwloop-08.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-05.s.
+	* gas/riscv/cv-hwloop-09.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-06.d.
+	* gas/riscv/cv-hwloop-09.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-06.l.
+	* gas/riscv/cv-hwloop-09.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-06.s.
+	* gas/riscv/cv-hwloop-10.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-06.d.
+	* gas/riscv/cv-hwloop-10.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-06.l.
+	* gas/riscv/cv-hwloop-10.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-06.s.
+	* gas/riscv/cv-hwloop-11.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-07.d.
+	* gas/riscv/cv-hwloop-11.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-07.l.
+	* gas/riscv/cv-hwloop-11.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-07.s.
+	* gas/riscv/cv-hwloop-12.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-08.d.
+	* gas/riscv/cv-hwloop-12.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-08.l.
+	* gas/riscv/cv-hwloop-12.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-08.s.
+	* gas/riscv/cv-hwloop-13.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-09.d.
+	* gas/riscv/cv-hwloop-13.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-09.l.
+	* gas/riscv/cv-hwloop-13.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-09.s.
+	* gas/riscv/cv-hwloop-14.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-10.d.
+	* gas/riscv/cv-hwloop-14.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-10.l.
+	* gas/riscv/cv-hwloop-14.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-10.s.
+	* gas/riscv/cv-hwloop-15.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-11.d.
+	* gas/riscv/cv-hwloop-15.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-11.l.
+	* gas/riscv/cv-hwloop-15.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-11.s.
+	* gas/riscv/cv-hwloop-16.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-01.d.
+	* gas/riscv/cv-hwloop-16.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-01.l.
+	* gas/riscv/cv-hwloop-16.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-01.s.
+	* gas/riscv/cv-hwloop-17.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-01.d.
+	* gas/riscv/cv-hwloop-17.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-01.l.
+	* gas/riscv/cv-hwloop-17.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-01.s.
+	* gas/riscv/cv-hwloop-18.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-03.d.
+	* gas/riscv/cv-hwloop-18.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-03.l.
+	* gas/riscv/cv-hwloop-18.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-03.s.
+	* gas/riscv/cv-hwloop-19.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-03.d.
+	* gas/riscv/cv-hwloop-19.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-03.l.
+	* gas/riscv/cv-hwloop-19.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-03.s.
+	* gas/riscv/cv-hwloop-20.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-05.d.
+	* gas/riscv/cv-hwloop-20.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-05.l.
+	* gas/riscv/cv-hwloop-20.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-05.s.
+	* gas/riscv/cv-hwloop-21.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-05.d.
+	* gas/riscv/cv-hwloop-21.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-05.l.
+	* gas/riscv/cv-hwloop-21.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-05.s.
+	* gas/riscv/cv-hwloop-22.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-06.d.
+	* gas/riscv/cv-hwloop-22.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-06.l.
+	* gas/riscv/cv-hwloop-22.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-06.s.
+	* gas/riscv/cv-hwloop-23.d: Deleted, content subsumed into
+	cv-hwlp-fail-operand-06.d.
+	* gas/riscv/cv-hwloop-23.l: Deleted, content subsumed into
+	cv-hwlp-fail-operand-06.l.
+	* gas/riscv/cv-hwloop-23.s: Deleted, content subsumed into
+	cv-hwlp-fail-operand-06.s.
+
+2020-11-19  Jessica Mills  <jessica.mills@embecosm.com>
+
+	* cv-hwloop-16.d: Added new boundary test.
+	* cv-hwloop-16.l: Likewise.
+	* cv-hwloop-16.s: Likewise.
+	* cv-hwloop-17.d: Likewise.
+	* cv-hwloop-17.l: Likewise.
+	* cv-hwloop-17.s: Likewise.
+	* cv-hwloop-18.d: Likewise.
+	* cv-hwloop-18.l: Likewise.
+	* cv-hwloop-18.s: Likewise.
+	* cv-hwloop-19.d: Likewise.
+	* cv-hwloop-19.l: Likewise.
+	* cv-hwloop-19.s: Likewise.
+	* cv-hwloop-20.d: Likewise.
+	* cv-hwloop-20.l: Likewise.
+	* cv-hwloop-20.s: Likewise.
+	* cv-hwloop-21.d: Likewise.
+	* cv-hwloop-21.l: Likewise.
+	* cv-hwloop-21.s: Likewise.
+	* cv-hwloop-22.d: Likewise.
+	* cv-hwloop-22.l: Likewise.
+	* cv-hwloop-22.s: Likewise.
+	* cv-hwloop-23.d: Likewise.
+	* cv-hwloop-23.l: Likewise.
+	* cv-hwloop-23.s: Likewise.
+	* cv-hwloop-09.s: Fixed incorrect comment.
+	* cv-hwloop-10.s: Likewise.
+	* cv-mac-07.d: Added new boundary test.
+	* cv-mac-07.l: Likewise.
+	* cv-mac-07.s: Likewise.
+	* cv-mac-08.d: Likewise.
+	* cv-mac-08.l: Likewise.
+	* cv-mac-08.s: Likewise.
+	* cv-mac-05.l: Changed to non-boundary value.
+	* cv-mac-05.s: Likewise.
+
+2020-10-30  Mary Bennett  <mary.bennett@embecosm.com>
+
+	* gas/riscv/cv-hwloop-01.d: Changed march option to xcorehwlp.
+	* gas/riscv/cv-hwloop-02.d: Likewise.
+	* gas/riscv/cv-hwloop-03.d: Likewise.
+	* gas/riscv/cv-hwloop-04.d: Likewise.
+	* gas/riscv/cv-hwloop-05.d: Likewise.
+	* gas/riscv/cv-hwloop-06.d: Likewise.
+	* gas/riscv/cv-hwloop-07.d: Likewise.
+	* gas/riscv/cv-hwloop-08.d: Likewise.
+	* gas/riscv/cv-hwloop-count.d: Likewise.
+	* gas/riscv/cv-hwloop-counti.d: Likewise.
+	* gas/riscv/cv-hwloop-endi.d: Likewise.
+	* gas/riscv/cv-hwloop-setup.d: Likewise.
+	* gas/riscv/cv-hwloop-setupi.d: Likewise.
+	* gas/riscv/cv-hwloop-starti.d: Likewise.
+	* gas/riscv/cv-hwloop-09.d: Likewise.
+	* gas/riscv/cv-hwloop-10.d: Likewise.
+	* gas/riscv/cv-hwloop-11.d: Added new test.
+	* gas/riscv/cv-hwloop-11.l: Likewise.
+	* gas/riscv/cv-hwloop-11.s: Likewise.
+	* gas/riscv/cv-hwloop-12.d: Likewise.
+	* gas/riscv/cv-hwloop-12.l: Likewise.
+	* gas/riscv/cv-hwloop-12.s: Likewise.
+	* gas/riscv/cv-hwloop-13.d: Likewise.
+	* gas/riscv/cv-hwloop-13.l: Likewise.
+	* gas/riscv/cv-hwloop-13.s: Likewise.
+	* gas/riscv/cv-hwloop-14.d: Likewise.
+	* gas/riscv/cv-hwloop-14.l: Likewise.
+	* gas/riscv/cv-hwloop-14.s: Likewise.
+	* gas/riscv/cv-hwloop-15.d: Likewise.
+	* gas/riscv/cv-hwloop-15.l: Likewise.
+	* gas/riscv/cv-hwloop-15.s: Likewise.
+	* gas/riscv/cv-march-rv32i-xcorev.s: Added test for march option.
+	* gas/riscv/cv-march-rv32i-xcorev.d: Likewise.
+
+2020-09-10  Pietra Ferreira  <pietra.ferreira@embecosm.com>
+
+	* gas/riscv/cv-hwloop-01.d: Added new test.
+	* gas/riscv/cv-hwloop-01.l: Likewise.
+	* gas/riscv/cv-hwloop-01.s: Likewise.
+	* gas/riscv/cv-hwloop-02.d: Likewise.
+	* gas/riscv/cv-hwloop-02.l: Likewise.
+	* gas/riscv/cv-hwloop-02.s: Likewise.
+	* gas/riscv/cv-hwloop-03.d: Likewise.
+	* gas/riscv/cv-hwloop-03.l: Likewise.
+	* gas/riscv/cv-hwloop-03.s: Likewise.
+	* gas/riscv/cv-hwloop-04.d: Likewise.
+	* gas/riscv/cv-hwloop-04.l: Likewise.
+	* gas/riscv/cv-hwloop-04.s: Likewise.
+	* gas/riscv/cv-hwloop-05.d: Likewise.
+	* gas/riscv/cv-hwloop-05.l: Likewise.
+	* gas/riscv/cv-hwloop-05.s: Likewise.
+	* gas/riscv/cv-hwloop-06.d: Likewise.
+	* gas/riscv/cv-hwloop-06.l: Likewise.
+	* gas/riscv/cv-hwloop-06.s: Likewise.
+	* gas/riscv/cv-hwloop-07.d: Likewise.
+	* gas/riscv/cv-hwloop-07.l: Likewise.
+	* gas/riscv/cv-hwloop-07.s: Likewise.
+	* gas/riscv/cv-hwloop-08.d: Likewise.
+	* gas/riscv/cv-hwloop-08.l: Likewise.
+	* gas/riscv/cv-hwloop-08.s: Likewise.
+	* gas/riscv/cv-hwloop-count.d: Likewise.
+	* gas/riscv/cv-hwloop-count.s: Likewise.
+	* gas/riscv/cv-hwloop-counti.d: Likewise.
+	* gas/riscv/cv-hwloop-counti.s: Likewise.
+	* gas/riscv/cv-hwloop-endi.d: Likewise.
+	* gas/riscv/cv-hwloop-endi.s: Likewise.
+	* gas/riscv/cv-hwloop-setup.d: Likewise.
+	* gas/riscv/cv-hwloop-setup.s: Likewise.
+	* gas/riscv/cv-hwloop-setupi.d: Likewise.
+	* gas/riscv/cv-hwloop-setupi.s: Likewise.
+	* gas/riscv/cv-hwloop-starti.d: Likewise.
+	* gas/riscv/cv-hwloop-starti.s: Likewise.
+	* gas/riscv/cv-hwloop-09.d: Likewise.
+	* gas/riscv/cv-hwloop-09.l: Likewise.
+	* gas/riscv/cv-hwloop-09.s: Likewise.
+	* gas/riscv/cv-hwloop-10.d: Likewise.
+	* gas/riscv/cv-hwloop-10.l: Likewise.
+	* gas/riscv/cv-hwloop-10.s: Likewise.
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-count.d b/gas/testsuite/gas/riscv/cv-hwlp-count.d
new file mode 100644
index 00000000000..615521a9785
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-count.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvhwlp
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+0002c52b[ 	]+cv.count[ 	]+0,t0
+[ 	]+4:[ 	]+0005c5ab[ 	]+cv.count[ 	]+1,a1
+[ 	]+8:[ 	]+000ec52b[ 	]+cv.count[ 	]+0,t4
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-count.s b/gas/testsuite/gas/riscv/cv-hwlp-count.s
new file mode 100644
index 00000000000..341f7e1bb94
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-count.s
@@ -0,0 +1,4 @@
+target:
+	cv.count 0, t0
+	cv.count 1, a1
+	cv.count 0, t4
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-counti.d b/gas/testsuite/gas/riscv/cv-hwlp-counti.d
new file mode 100644
index 00000000000..1245fd46a1a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-counti.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvhwlp
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+0000442b[ 	]+cv.counti[ 	]+0,0
+[ 	]+4:[ 	]+791044ab[ 	]+cv.counti[ 	]+1,1937
+[ 	]+8:[ 	]+fff0442b[ 	]+cv.counti[ 	]+0,4095
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-counti.s b/gas/testsuite/gas/riscv/cv-hwlp-counti.s
new file mode 100644
index 00000000000..481ac67139e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-counti.s
@@ -0,0 +1,4 @@
+target:
+	cv.counti 0, 0
+	cv.counti 1, 1937
+	cv.counti 0, 4095
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-end.d b/gas/testsuite/gas/riscv/cv-hwlp-end.d
new file mode 100644
index 00000000000..f55f1236b24
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-end.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvhwlp
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+0002c32b[ 	]+cv.end[ 	]+0,t0
+[ 	]+4:[ 	]+0005c3ab[ 	]+cv.end[ 	]+1,a1
+[ 	]+8:[ 	]+000ec32b[ 	]+cv.end[ 	]+0,t4
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-end.s b/gas/testsuite/gas/riscv/cv-hwlp-end.s
new file mode 100644
index 00000000000..2b9de2409bd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-end.s
@@ -0,0 +1,4 @@
+target:
+	cv.end 0, t0
+	cv.end 1, a1
+	cv.end 0, t4
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-endi.d b/gas/testsuite/gas/riscv/cv-hwlp-endi.d
new file mode 100644
index 00000000000..dae5b32db0f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-endi.d
@@ -0,0 +1,13 @@
+#as: -march=rv32i_xcvhwlp
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+0000422b[ 	]+cv.endi[ 	]+0,0 <target>
+[ 	]+4:[ 	]+108042ab[ 	]+cv.endi[ 	]+1,424 +<target\+0x424>
+[ 	]+8:[ 	]+7ff0422b[ 	]+cv.endi[ 	]+0,2004 +<target\+0x2004>
+[ 	]+c:[ 	]+fff042ab[ 	]+cv.endi[ 	]+1,8 +<target\+0x8>
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-endi.s b/gas/testsuite/gas/riscv/cv-hwlp-endi.s
new file mode 100644
index 00000000000..d3e16cc24d4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-endi.s
@@ -0,0 +1,5 @@
+target:
+	cv.endi 0, 0
+	cv.endi 1, 1056
+	cv.endi 0, 8188
+	cv.endi 1, 16380
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-march.d b/gas/testsuite/gas/riscv/cv-hwlp-fail-march.d
new file mode 100644
index 00000000000..79483c5e7b4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-march.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: cv-hwlp-fail-march.s
+#error_output: cv-hwlp-fail-march.l
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-march.l b/gas/testsuite/gas/riscv/cv-hwlp-fail-march.l
new file mode 100644
index 00000000000..6723c46c3e0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-march.l
@@ -0,0 +1,8 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `cv.starti 1,320', extension `xcvhwlp' required
+.*: Error: unrecognized opcode `cv.endi 1,1056', extension `xcvhwlp' required
+.*: Error: unrecognized opcode `cv.setupi 1,488,12', extension `xcvhwlp' required
+.*: Error: unrecognized opcode `cv.setup 1,t5,488', extension `xcvhwlp' required
+.*: Error: unrecognized opcode `cv.count 1,a1', extension `xcvhwlp' required
+.*: Error: unrecognized opcode `cv.counti 1,1937', extension `xcvhwlp' required
+
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-march.s b/gas/testsuite/gas/riscv/cv-hwlp-fail-march.s
new file mode 100644
index 00000000000..54a7247f4fb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-march.s
@@ -0,0 +1,8 @@
+# Absence of xcvhwlp march option disables all CORE-V hwlp extensions
+target:
+	cv.starti 1, 320
+	cv.endi   1, 1056
+	cv.setupi 1, 488, 12
+	cv.setup  1, t5, 488
+	cv.count  1, a1
+	cv.counti 1, 1937
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-01.d b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-01.d
new file mode 100644
index 00000000000..9b0abe6ecc6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-01.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvhwlp
+#source: cv-hwlp-fail-operand-01.s
+#error_output: cv-hwlp-fail-operand-01.l
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-01.l b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-01.l
new file mode 100644
index 00000000000..a214ccc4bfb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-01.l
@@ -0,0 +1,13 @@
+.*: Assembler messages:
+.*: Error: -1 constant out of range for cv.starti, range:\[0, 16380\]
+.*: Error: -1 constant out of range for cv.endi, range:\[0, 16380\]
+.*: Error: -1 constant out of range for cv.setup, range:\[0, 16380\]
+.*: Error: -6 constant out of range for cv.starti, range:\[0, 16380\]
+.*: Error: -94 constant out of range for cv.endi, range:\[0, 16380\]
+.*: Error: -842 constant out of range for cv.setup, range:\[0, 16380\]
+.*: Error: 16384 constant out of range for cv.starti, range:\[0, 16380\]
+.*: Error: 16384 constant out of range for cv.endi, range:\[0, 16380\]
+.*: Error: 16384 constant out of range for cv.setup, range:\[0, 16380\]
+.*: Error: 89444 constant out of range for cv.starti, range:\[0, 16380]
+.*: Error: 3624724 constant out of range for cv.endi, range:\[0, 16380\]
+.*: Error: 20394 constant out of range for cv.setup, range:\[0, 16380\]
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-01.s b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-01.s
new file mode 100644
index 00000000000..1dfec61da88
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-01.s
@@ -0,0 +1,14 @@
+# Branch offset must be an even integer in range:[0, 8191]
+target:
+	cv.starti 0, -1
+	cv.endi 1, -1
+	cv.setup 0, t1, -1
+	cv.starti 0, -6
+	cv.endi 1, -94
+	cv.setup 0, t2, -842
+	cv.starti 0, 16384
+	cv.endi 1, 16384
+	cv.setup 0, t3, 16384
+	cv.starti 0, 89444
+	cv.endi 1, 3624724
+	cv.setup 0, t4, 20394
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-02.d b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-02.d
new file mode 100644
index 00000000000..e762323dbb7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-02.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvhwlp
+#source: cv-hwlp-fail-operand-02.s
+#warning_output: cv-hwlp-fail-operand-02.l
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-02.l b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-02.l
new file mode 100644
index 00000000000..178c655a759
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-02.l
@@ -0,0 +1,4 @@
+.*Assembler messages:
+.*Warning: constant for cv.starti must be a multiple of 4: 105 truncated to 104
+.*Warning: constant for cv.endi must be a multiple of 4: 8191 truncated to 8188
+.*Warning: constant for cv.setup must be a multiple of 4: 9 truncated to 8
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-02.s b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-02.s
new file mode 100644
index 00000000000..f1a6d105575
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-02.s
@@ -0,0 +1,5 @@
+# An odd branch offset will truncate to an even integer
+target:
+	cv.starti 0, 105
+	cv.endi 0, 8191
+	cv.setup 0, t6, 9
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-03.d b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-03.d
new file mode 100644
index 00000000000..9ff0c0e927c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-03.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvhwlp
+#source: cv-hwlp-fail-operand-03.s
+#error_output: cv-hwlp-fail-operand-03.l
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-03.l b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-03.l
new file mode 100644
index 00000000000..6daeb019ebe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-03.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: -1 constant out of range for cv.setupi, range:\[0, 127\]
+.*: Error: -14 constant out of range for cv.setupi, range:\[0, 127\]
+.*: Error: 128 constant out of range for cv.setupi, range:\[0, 127\]
+.*: Error: 7366 constant out of range for cv.setupi, range:\[0, 127\]
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-03.s b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-03.s
new file mode 100644
index 00000000000..d54e2cad642
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-03.s
@@ -0,0 +1,6 @@
+# Branch offset must be an integer multiple of 4 in range:[0, 124]
+target:
+	cv.setupi 0, 1056, -1
+	cv.setupi 0, 14, -14
+	cv.setupi 0, 67, 128
+	cv.setupi 0, 356, 7366
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-04.d b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-04.d
new file mode 100644
index 00000000000..3de2248bc24
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-04.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvhwlp
+#source: cv-hwlp-fail-operand-04.s
+#warning_output: cv-hwlp-fail-operand-04.l
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-04.l b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-04.l
new file mode 100644
index 00000000000..c0eff51f851
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-04.l
@@ -0,0 +1,3 @@
+.*Assembler messages:
+.*Warning: constant for cv.setupi must be a multiple of 4: 63 truncated to 60
+.*Warning: constant for cv.setupi must be a multiple of 4: 5 truncated to 4
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-04.s b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-04.s
new file mode 100644
index 00000000000..abdf124cc74
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-04.s
@@ -0,0 +1,4 @@
+# An odd branch offset will truncate to an integer multiple of 4
+target:
+	cv.setupi 0, 1056, 63
+	cv.setupi 0, 56, 5
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-05.d b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-05.d
new file mode 100644
index 00000000000..6a70f9d71c7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-05.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvhwlp
+#source: cv-hwlp-fail-operand-05.s
+#error_output: cv-hwlp-fail-operand-05.l
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-05.l b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-05.l
new file mode 100644
index 00000000000..d8650b31098
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-05.l
@@ -0,0 +1,34 @@
+.*: Assembler messages:
+.*: Error: cv.starti loop number must be 0 or 1
+.*: Error: cv.start loop number must be 0 or 1
+.*: Error: cv.endi loop number must be 0 or 1
+.*: Error: cv.end loop number must be 0 or 1
+.*: Error: cv.setupi loop number must be 0 or 1
+.*: Error: cv.setup loop number must be 0 or 1
+.*: Error: cv.count loop number must be 0 or 1
+.*: Error: cv.counti loop number must be 0 or 1
+.*: Error: cv.starti loop number must be 0 or 1
+.*: Error: cv.start loop number must be 0 or 1
+.*: Error: cv.endi loop number must be 0 or 1
+.*: Error: cv.end loop number must be 0 or 1
+.*: Error: cv.setupi loop number must be 0 or 1
+.*: Error: cv.setup loop number must be 0 or 1
+.*: Error: cv.count loop number must be 0 or 1
+.*: Error: cv.counti loop number must be 0 or 1
+.*: Error: cv.starti loop number must be 0 or 1
+.*: Error: cv.start loop number must be 0 or 1
+.*: Error: cv.endi loop number must be 0 or 1
+.*: Error: cv.end loop number must be 0 or 1
+.*: Error: cv.setupi loop number must be 0 or 1
+.*: Error: cv.setup loop number must be 0 or 1
+.*: Error: cv.count loop number must be 0 or 1
+.*: Error: cv.counti loop number must be 0 or 1
+.*: Error: cv.starti loop number must be 0 or 1
+.*: Error: cv.start loop number must be 0 or 1
+.*: Error: cv.endi loop number must be 0 or 1
+.*: Error: cv.end loop number must be 0 or 1
+.*: Error: cv.setupi loop number must be 0 or 1
+.*: Error: cv.setup loop number must be 0 or 1
+.*: Error: cv.count loop number must be 0 or 1
+.*: Error: cv.counti loop number must be 0 or 1
+
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-05.s b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-05.s
new file mode 100644
index 00000000000..3a26e3eaf52
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-05.s
@@ -0,0 +1,34 @@
+# Loop number must be 0 or 1
+target:
+	cv.starti -1, 320
+        cv.start  -1, t5
+	cv.endi   -1, 1056
+        cv.end    -1, t5
+	cv.setupi -1, 488, 12
+	cv.setup  -1, t5, 488
+	cv.count  -1, a1
+	cv.counti -1, 1937
+	cv.starti -39, 320
+        cv.start  -93, t2
+	cv.endi   -329, 1056
+        cv.end    -293, t2
+	cv.setupi -1823, 488, 12
+	cv.setup  -493, t5, 488
+	cv.count  -76, a1
+	cv.counti -3954, 1937
+	cv.starti 2, 320
+        cv.start  2, t1
+	cv.endi   2, 1056
+        cv.end    2, t1
+	cv.setupi 2, 488, 12
+	cv.setup  2, t5, 488
+	cv.count  2, a1
+	cv.counti 2, 1937
+	cv.starti 235, 320
+        cv.start  222, a0
+	cv.endi   6546, 1056
+        cv.end    2334, a0
+	cv.setupi 134, 488, 12
+	cv.setup  4, t5, 488
+	cv.count  6, a1
+	cv.counti 393, 1937
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-06.d b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-06.d
new file mode 100644
index 00000000000..3ba45148d6f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-06.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvhwlp
+#source: cv-hwlp-fail-operand-06.s
+#error_output: cv-hwlp-fail-operand-06.l
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-06.l b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-06.l
new file mode 100644
index 00000000000..69286cadd5b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-06.l
@@ -0,0 +1,9 @@
+.*: Assembler messages:
+.*: Error: -1 constant out of range for cv.counti, range:\[0, 4095\]
+.*: Error: -1 constant out of range for cv.setupi, range:\[0, 4095\]
+.*: Error: -832 constant out of range for cv.counti, range:\[0, 4095\]
+.*: Error: -291 constant out of range for cv.setupi, range:\[0, 4095\]
+.*: Error: 4096 constant out of range for cv.counti, range:\[0, 4095\]
+.*: Error: 4096 constant out of range for cv.setupi, range:\[0, 4095\]
+.*: Error: 74285 constant out of range for cv.counti, range:\[0, 4095\]
+.*: Error: 8334 constant out of range for cv.setupi, range:\[0, 4095\]
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-06.s b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-06.s
new file mode 100644
index 00000000000..7fca280b75d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-06.s
@@ -0,0 +1,10 @@
+# Loop count must be positive integer in range:[0, 4095]
+target:
+	cv.counti 0, -1
+	cv.setupi 0, -1, 4
+	cv.counti 0, -832
+	cv.setupi 0, -291, 8
+	cv.counti 0, 4096
+	cv.setupi 0, 4096, 8
+	cv.counti 0, 74285
+	cv.setupi 0, 8334, 8
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-07.d b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-07.d
new file mode 100644
index 00000000000..f6c81128b98
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-07.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvhwlp
+#source: cv-hwlp-fail-operand-07.s
+#error_output: cv-hwlp-fail-operand-07.l
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-07.l b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-07.l
new file mode 100644
index 00000000000..dfa8f8382c4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-07.l
@@ -0,0 +1,4 @@
+.*: Assembler messages:
+.*: Error: cv.starti immediate value must be a constant or label
+.*: Error: cv.endi immediate value must be a constant or label
+.*: Error: cv.setup immediate value must be a constant or label
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-07.s b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-07.s
new file mode 100644
index 00000000000..d1756204f28
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-07.s
@@ -0,0 +1,5 @@
+# Branch offset must be an absolute integer or symbol
+target:
+	cv.starti 0, t1
+	cv.endi 0, t2
+	cv.setup 0, t0, t6
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-08.d b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-08.d
new file mode 100644
index 00000000000..4339fe036c3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-08.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvhwlp
+#source: cv-hwlp-fail-operand-08.s
+#error_output: cv-hwlp-fail-operand-08.l
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-08.l b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-08.l
new file mode 100644
index 00000000000..c53daff12fc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-08.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: cv.starti loop number must be 0 or 1
+.*: Error: cv.start loop number must be 0 or 1
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-08.s b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-08.s
new file mode 100644
index 00000000000..fde725d1fea
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-08.s
@@ -0,0 +1,4 @@
+# Loop number must be an absolute integer
+target:
+	cv.starti t0, 8
+        cv.start  t0, t1
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-09.d b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-09.d
new file mode 100644
index 00000000000..be105cdc072
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-09.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvhwlp
+#source: cv-hwlp-fail-operand-09.s
+#error_output: cv-hwlp-fail-operand-09.l
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-09.l b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-09.l
new file mode 100644
index 00000000000..ef1cf200ce6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-09.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.start 0,9'
+.*: Error: illegal operands `cv.end 0,12'
+.*: Error: illegal operands `cv.count 0,8'
+.*: Error: illegal operands `cv.setup 0,483,16'
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-09.s b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-09.s
new file mode 100644
index 00000000000..9605cc6a04b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-09.s
@@ -0,0 +1,6 @@
+# Loop count register must be of type register
+target:
+        cv.start 0, 9
+        cv.end   0, 12
+	cv.count 0, 8
+	cv.setup 0, 483, 16
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-10.d b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-10.d
new file mode 100644
index 00000000000..77a6af53fc3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-10.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvhwlp
+#source: cv-hwlp-fail-operand-10.s
+#error_output: cv-hwlp-fail-operand-10.l
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-10.l b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-10.l
new file mode 100644
index 00000000000..15557041511
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-10.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: instruction cv.counti requires absolute expression
+.*: Error: instruction cv.setupi requires absolute expression
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-10.s b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-10.s
new file mode 100644
index 00000000000..5ab7a978308
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-10.s
@@ -0,0 +1,4 @@
+# Loop count must be an absolute integer
+target:
+	cv.counti 0, t1
+	cv.setupi 0, t6, 16
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-11.d b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-11.d
new file mode 100644
index 00000000000..abcb3be91d1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-11.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvhwlp
+#source: cv-hwlp-fail-operand-11.s
+#error_output: cv-hwlp-fail-operand-11.l
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-11.l b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-11.l
new file mode 100644
index 00000000000..600eb5171bd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-11.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Error: cv.setupi immediate value must be a constant or label
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-11.s b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-11.s
new file mode 100644
index 00000000000..d2ace80e1fb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-fail-operand-11.s
@@ -0,0 +1,3 @@
+# Branch offset must be an absolute integer or symbol
+target:
+	cv.setupi 0, 8, t1
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-setup.d b/gas/testsuite/gas/riscv/cv-hwlp-setup.d
new file mode 100644
index 00000000000..7e29c796067
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-setup.d
@@ -0,0 +1,13 @@
+#as: -march=rv32i_xcvhwlp
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+0002c72b[ 	]+cv.setup[ 	]+0,t0,0 <target>
+[ 	]+4:[ 	]+07af47ab[ 	]+cv.setup[ 	]+1,t5,1ec <target\+0x1ec>
+[ 	]+8:[ 	]+7ff5472b[ 	]+cv.setup[ 	]+0,a0,2004 <target\+0x2004>
+[ 	]+c:[ 	]+fffe47ab[ 	]+cv.setup[ 	]+1,t3,8 <target\+0x8>
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-setup.s b/gas/testsuite/gas/riscv/cv-hwlp-setup.s
new file mode 100644
index 00000000000..3273fa85de1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-setup.s
@@ -0,0 +1,5 @@
+target:
+	cv.setup 0, t0, 0
+	cv.setup 1, t5, 488
+	cv.setup 0, a0, 8188
+	cv.setup 1, t3, 16380
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-setupi.d b/gas/testsuite/gas/riscv/cv-hwlp-setupi.d
new file mode 100644
index 00000000000..bda05c9d465
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-setupi.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvhwlp
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+0000462b[ 	]+cv.setupi[ 	]+0,0,0 <target>
+[ 	]+4:[ 	]+1e8346ab[ 	]+cv.setupi[ 	]+1,488,1c <target\+0x1c>
+[ 	]+8:[ 	]+fff7c62b[ 	]+cv.setupi[ 	]+0,4095,44 <target\+0x44>
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-setupi.s b/gas/testsuite/gas/riscv/cv-hwlp-setupi.s
new file mode 100644
index 00000000000..051bdac848b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-setupi.s
@@ -0,0 +1,4 @@
+target:
+	cv.setupi 0, 0, 0
+	cv.setupi 1, 488, 24
+	cv.setupi 0, 4095, 60
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-start.d b/gas/testsuite/gas/riscv/cv-hwlp-start.d
new file mode 100644
index 00000000000..287cb0ab8ec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-start.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvhwlp
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+0002c12b[ 	]+cv.start[ 	]+0,t0
+[ 	]+4:[ 	]+0005c1ab[ 	]+cv.start[ 	]+1,a1
+[ 	]+8:[ 	]+000ec12b[ 	]+cv.start[ 	]+0,t4
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-start.s b/gas/testsuite/gas/riscv/cv-hwlp-start.s
new file mode 100644
index 00000000000..9b61003abe8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-start.s
@@ -0,0 +1,4 @@
+target:
+	cv.start 0, t0
+	cv.start 1, a1
+	cv.start 0, t4
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-starti.d b/gas/testsuite/gas/riscv/cv-hwlp-starti.d
new file mode 100644
index 00000000000..8f1f0ae2b87
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-starti.d
@@ -0,0 +1,13 @@
+#as: -march=rv32i_xcvhwlp
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+0000402b[ 	]+cv.starti[ 	]+0,0 <target>
+[ 	]+4:[ 	]+2f3040ab[ 	]+cv.starti[ 	]+1,bd0 +<target\+0xbd0>
+[ 	]+8:[ 	]+7ff0402b[ 	]+cv.starti[ 	]+0,2004 +<target\+0x2004>
+[ 	]+c:[ 	]+fff040ab[ 	]+cv.starti[ 	]+1,8 +<target\+0x8>
diff --git a/gas/testsuite/gas/riscv/cv-hwlp-starti.s b/gas/testsuite/gas/riscv/cv-hwlp-starti.s
new file mode 100644
index 00000000000..47bccbc0bcc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-hwlp-starti.s
@@ -0,0 +1,5 @@
+target:
+	cv.starti 0, 0
+	cv.starti 1, 3020
+	cv.starti 0, 8188
+	cv.starti 1, 16380
diff --git a/include/ChangeLog.COREV b/include/ChangeLog.COREV
new file mode 100644
index 00000000000..d438dc25bc7
--- /dev/null
+++ b/include/ChangeLog.COREV
@@ -0,0 +1,26 @@
+2021-08-23  Jessica Mills  <jessica.mills@embecosm.com>
+
+	* opcode/riscv-opc.h: Fix hexadecimal number format inconsistencies
+	for matches and masks.
+
+2020-11-10  Mary Bennett  <mary.bennett@embecosm.com>
+
+	* opcode/riscv.h (riscv_pred_succ): Renamed macros for clarity -
+	ENCODE_I1TYPE_UIMM -> ENCODE_CV_HWLP_UIMM5
+	ENCODE_I1TYPE_LN   -> ENCODE_CV_HWLP_LN
+	EXTRACT_I1TYPE_UIMM-> EXTRACT_CV_HWLP_UIMM5
+	EXTRACT_I1TYPE_LN  -> EXTRACT_CV_HWLP_LN
+	EXTRACT_ITYPE_UIMM -> EXTRACT_CV_HWLP_UIMM12
+
+2020-10-05  Mary Bennett <mary.bennett@embecosm.com>
+
+	* opcode/riscv-opc.h: Fixed incorrect masks for CORE-V hardware loop
+	instructions.
+	* opcode/riscv.h: Added support for xcorevhwlp.
+
+2020-09-10  Pietra Ferreira  <pietra.ferreira@embecosm.com>
+
+	* elf/riscv.h: Added CORE-V hardware loop specific relocations.
+	* opcode/riscv.h: Added CORE-V hardware loop specific masks and
+	CORE-V instruction class. Added macros for unsigned I type
+	immediate and loop number.
diff --git a/include/elf/riscv.h b/include/elf/riscv.h
index 0aa8b3359c4..cca5c02dc49 100644
--- a/include/elf/riscv.h
+++ b/include/elf/riscv.h
@@ -90,6 +90,9 @@ START_RELOC_NUMBERS (elf_riscv_reloc_type)
   /* Reserved 59 for R_RISCV_PLT32.  */
   RELOC_NUMBER (R_RISCV_SET_ULEB128, 60)
   RELOC_NUMBER (R_RISCV_SUB_ULEB128, 61)
+  /* CORE-V Specific Relocations.  */
+  RELOC_NUMBER (R_RISCV_CVPCREL_UI12, 224)
+  RELOC_NUMBER (R_RISCV_CVPCREL_URS1, 225)
 END_RELOC_NUMBERS (R_RISCV_max)
 
 /* Processor specific flags for the ELF header e_flags field.  */
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 7c89a53b591..c9e98d56147 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2,6 +2,13 @@
    Copyright (C) 2011-2023 Free Software Foundation, Inc.
    Contributed by Andrew Waterman
 
+   Modified for CORE-V by:
+   Mary Bennett (mary.bennett@embecosm.com)
+   Pietra Ferreira (pietra.ferreira@embecosm.com)
+   Jessica Mills (jessica.mills@embecosm.com)
+
+   Some of these changes are (C) Open Hardware Group, pending FSF assignment.
+
    This file is part of GDB, GAS, and the GNU binutils.
 
    GDB, GAS, and the GNU binutils are free software; you can redistribute
@@ -2424,6 +2431,23 @@
 #define MASK_CV_SUBRN 0xc000707f
 #define MATCH_CV_SUBURN 0xc000305b
 #define MASK_CV_SUBURN 0xc000707f
+/* Vendor-specific (CORE-V) Xcvhwlp instructions. */
+#define MASK_CV_START  0xfff07f7f
+#define MASK_CV_STARTI 0xfff7f
+#define MASK_CV_END    0xfff07f7f
+#define MASK_CV_ENDI   0xfff7f
+#define MASK_CV_COUNT  0xfff07f7f
+#define MASK_CV_COUNTI 0xfff7f
+#define MASK_CV_SETUP  0x7f7f
+#define MASK_CV_SETUPI 0x7f7f
+#define MATCH_CV_START  0x412b
+#define MATCH_CV_STARTI 0x402b
+#define MATCH_CV_END    0x432b
+#define MATCH_CV_ENDI   0x422b
+#define MATCH_CV_COUNT  0x452b
+#define MATCH_CV_COUNTI 0x442b
+#define MATCH_CV_SETUP  0x472b
+#define MATCH_CV_SETUPI 0x462b
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 #define MATCH_TH_ADDSL 0x0000100b
 #define MASK_TH_ADDSL 0xf800707f
@@ -3096,6 +3120,7 @@
 #define CSR_VTYPE 0xc21
 #define CSR_VLENB 0xc22
 #endif /* RISCV_ENCODING_H */
+
 #ifdef DECLARE_INSN
 DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
 DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 88b0556399f..2659e5c9c97 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -117,6 +117,12 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   (RV_X(x, 20, 5))
 #define EXTRACT_CV_IS3_UIMM5(x) \
   (RV_X(x, 25, 5))
+#define EXTRACT_CV_HWLP_UIMM5(x) \
+  (RV_X(x, 15, 5))
+#define EXTRACT_CV_HWLP_LN(x) \
+  (RV_X(x, 7, 1))
+#define EXTRACT_CV_HWLP_UIMM12(x) \
+  (RV_X(x, 20, 12))
 
 #define ENCODE_ITYPE_IMM(x) \
   (RV_X(x, 0, 12) << 20)
@@ -173,6 +179,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   (RV_X(x, 0, 5) << 20)
 #define ENCODE_CV_IS3_UIMM5(x) \
   (RV_X(x, 0, 5) << 25)
+#define ENCODE_CV_HWLP_UIMM5(x) \
+  (RV_X(x, 0, 5) << 15)
+#define ENCODE_CV_HWLP_LN(x) \
+  (RV_X(x, 0, 1) << 7)
 
 #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
 #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
@@ -265,6 +275,14 @@ static inline unsigned int riscv_insn_length (insn_t insn)
 #define OP_MASK_RL		0x1
 #define OP_SH_RL		25
 
+/* CORE-V Specific.  */
+#define OP_MASK_IMM12           0xfff
+#define OP_SH_IMM12             20
+#define OP_MASK_IMM5            0x1f
+#define OP_SH_IMM5              15
+#define OP_MASK_LN              0x1
+#define OP_SH_LN                7
+
 #define OP_MASK_CSR		0xfffU
 #define OP_SH_CSR		20
 
@@ -455,6 +473,7 @@ enum riscv_insn_class
   INSN_CLASS_H,
   INSN_CLASS_XCVMAC,
   INSN_CLASS_XCVALU,
+  INSN_CLASS_XCVHWLP,
   INSN_CLASS_XTHEADBA,
   INSN_CLASS_XTHEADBB,
   INSN_CLASS_XTHEADBS,
diff --git a/ld/ChangeLog.COREV b/ld/ChangeLog.COREV
new file mode 100644
index 00000000000..d45be3f4181
--- /dev/null
+++ b/ld/ChangeLog.COREV
@@ -0,0 +1,3 @@
+2020-09-10  Pietra Ferreira  <pietra.ferreira@embecosm.com>
+
+	* emultempl/riscvelf.em: Added initial CORE-V support.
diff --git a/ld/testsuite/ChangeLog.COREV b/ld/testsuite/ChangeLog.COREV
new file mode 100644
index 00000000000..16573a88b27
--- /dev/null
+++ b/ld/testsuite/ChangeLog.COREV
@@ -0,0 +1,32 @@
+2021-08-23  Jessica Mills  <jessica.mills@embecosm.com>
+
+	* ld-riscv-elf/ld-riscv-elf.exp: Renamed CORE-V hwlp tests to match
+	-march option for the instruction set.
+	* ld-riscv-elf/cv-hwloop-starti.s: Renamed to cv-hwlp-starti.s.
+	* ld-riscv-elf/cv-hwloop-starti.d: Renamed to cv-hwlp-starti.d.
+	* ld-riscv-elf/cv-hwloop-endi.d: Renamed to cv-hwlp-endi.d.
+	* ld-riscv-elf/cv-hwloop-endi.s: Renamed to cv-hwlp-endi.s.
+	* ld-riscv-elf/cv-hwloop-setup.d: Renamed to cv-hwlp-setup.d.
+	* ld-riscv-elf/cv-hwloop-setup.s: Renamed to cv-hwlp-setup.s.
+	* ld-riscv-elf/cv-hwloop-setupi.d: Renamed to cv-hwlp-setupi.d.
+	* ld-riscv-elf/cv-hwloop-setupi.s: Renamed to cv-hwlp-setupi.s.
+
+2020-10-21  Mary Bennett  <mary.bennett@embecosm.com>
+
+	* ld-riscv-elf/cv-hwloop-starti.d: Changed march option to xcorevhwlp.
+	* ld-riscv-elf/cv-hwloop-endi.d: Likewise.
+	* ld-riscv-elf/cv-hwloop-setup.d: Likewise.
+	* ld-riscv-elf/cv-hwloop-setupi.d: Likewise.
+
+2020-09-10  Pietra Ferreira  <pietra.ferreira@embecosm.com>
+
+	* ld-riscv-elf/ld-riscv-elf.exp: Added CORE-V hardware loop
+	tests.
+	* ld-riscv-elf/cv-hwloop-starti.s: Added new test.
+	* ld-riscv-elf/cv-hwloop-starti.d: Likewise.
+	* ld-riscv-elf/cv-hwloop-endi.d: Likewise.
+	* ld-riscv-elf/cv-hwloop-endi.s: Likewise.
+	* ld-riscv-elf/cv-hwloop-setup.d: Likewise.
+	* ld-riscv-elf/cv-hwloop-setup.s: Likewise.
+	* ld-riscv-elf/cv-hwloop-setupi.d: Likewise.
+	* ld-riscv-elf/cv-hwloop-setupi.s: Likewise.
diff --git a/ld/testsuite/ld-riscv-elf/cv-hwlp-endi.d b/ld/testsuite/ld-riscv-elf/cv-hwlp-endi.d
new file mode 100644
index 00000000000..a72c1eb0f9d
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-hwlp-endi.d
@@ -0,0 +1,21 @@
+#name: endi relocation
+#source: cv-hwlp-endi.s
+#as: -march=rv32i_xcvhwlp
+#ld: -melf32lriscv
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+.* <func>:
+.*:[[:space:]]+00008067[[:space:]]+ret
+
+.* <_start>:
+.*:[[:space:]]+0020422b[[:space:]]+cv.endi[[:space:]]+0,.*[[:space:]]+<L2>
+.*:[[:space:]]+ff9ff0ef[[:space:]]+jal[[:space:]]+10074[[:space:]]+<func>
+
+.* <L2>:
+.*:[[:space:]]+00000013[[:space:]]+nop
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/cv-hwlp-endi.s b/ld/testsuite/ld-riscv-elf/cv-hwlp-endi.s
new file mode 100644
index 00000000000..becca4bf9c9
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-hwlp-endi.s
@@ -0,0 +1,11 @@
+        .option nopic
+        .text
+        .align 1
+        .globl _start
+        .type _start, @function
+
+func:   ret
+_start:
+        cv.endi       0,L2
+        call func
+L2:     nop
diff --git a/ld/testsuite/ld-riscv-elf/cv-hwlp-pass.d b/ld/testsuite/ld-riscv-elf/cv-hwlp-pass.d
new file mode 100644
index 00000000000..94dd75aadd3
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-hwlp-pass.d
@@ -0,0 +1,83 @@
+#as: -march=rv32ixcvhwlp1p0
+#ld: -melf32lriscv
+#objdump: -dr
+
+.*:[    ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <_start>:
+.*:[[:space:]]+2310c62b[[:space:]]+cv.setupi[[:space:]]+0,561,4[[:space:]]+<_start\+0x4>
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+
+0+084 <lp0>:
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+2310c62b[[:space:]]+cv.setupi[[:space:]]+0,561,8c[[:space:]]+<lp0\+0x8>
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+
+0+10c <lp1>:
+.*:[[:space:]]+0000[[:space:]]+.2byte[[:space:]]+0x0
+[[:space:]]+\.\.\.
diff --git a/ld/testsuite/ld-riscv-elf/cv-hwlp-pass.s b/ld/testsuite/ld-riscv-elf/cv-hwlp-pass.s
new file mode 100644
index 00000000000..c7ef2c955e4
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-hwlp-pass.s
@@ -0,0 +1,33 @@
+# Use alignment to confuse hardware loop length
+#
+#    Macro to generate word length NOPS
+#
+    .macro wnops count=1
+    .option norvc
+    nop
+    .ifne \count
+    wnops "(\count-1)"
+    .endif
+    .endm
+#
+#    Declare as a global function so it will link
+#
+    .global    _start
+    .func _start
+_start:
+    .option norvc
+    # We can't control whether this loop will be aligned or not, but if
+    # it is not, then the next one will be.
+    cv.setupi 0, 561, lp0
+    wnops    20
+    .balign    8
+    wnops    9
+lp0:
+    nop
+    # We can't control whether this loop will be aligned or not, but if
+    # it is not, then the previous one will have been.
+    cv.setupi 0, 561, lp1
+    wnops    20
+    .balign    8
+    wnops    9
+lp1:
diff --git a/ld/testsuite/ld-riscv-elf/cv-hwlp-setup.d b/ld/testsuite/ld-riscv-elf/cv-hwlp-setup.d
new file mode 100644
index 00000000000..229e93458ee
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-hwlp-setup.d
@@ -0,0 +1,21 @@
+#name: setup relocation
+#source: cv-hwlp-setup.s
+#as: -march=rv32i_xcvhwlp
+#ld: -melf32lriscv
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+.* <func>:
+.*:[[:space:]]+00008067[[:space:]]+ret
+
+.* <_start>:
+.*:[[:space:]]+0025472b[[:space:]]+cv.setup[[:space:]]+0,a0,.*[[:space:]]+<L2>
+.*:[[:space:]]+ff9ff0ef[[:space:]]+jal[[:space:]]+10074[[:space:]]+<func>
+
+.* <L2>:
+.*:[[:space:]]+00000013[[:space:]]+nop
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/cv-hwlp-setup.s b/ld/testsuite/ld-riscv-elf/cv-hwlp-setup.s
new file mode 100644
index 00000000000..e6f245b78c9
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-hwlp-setup.s
@@ -0,0 +1,11 @@
+        .option nopic
+        .text
+        .align 1
+        .globl _start
+        .type _start, @function
+
+func:   ret
+_start:
+        cv.setup       0,a0,L2
+        call func
+L2:     nop
diff --git a/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-2.d b/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-2.d
new file mode 100644
index 00000000000..2cee593e9af
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-2.d
@@ -0,0 +1,13 @@
+#as: -march=rv32ixcvhwlp1p0
+#ld: -melf32lriscv
+#objdump: -dr
+
+.*:[    ]+file format .*
+
+
+Disassembly of section .text:
+
+00010078 <_start>:
+.*:[[:space:]]+2311c62b[[:space:]]+cv.setupi[[:space:]]+0,561,10084[[:space:]]+<lp0>
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
diff --git a/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-2.s b/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-2.s
new file mode 100644
index 00000000000..d536a05823c
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-2.s
@@ -0,0 +1,42 @@
+#
+#    Declare as a global function so it will link
+#
+    .global    _start
+    .func _start
+_start:
+    .option norvc
+    # We can't control whether this loop will be aligned or not, but if
+    # it is not, then the next one will be.
+    cv.setupi 0, 561, lp0
+    nop
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    nop
+lp0:
diff --git a/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-fail.d b/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-fail.d
new file mode 100644
index 00000000000..4c1a77319c1
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-fail.d
@@ -0,0 +1,4 @@
+#source: cv-hwlp-setupi-fail.s
+#as: -march=rv32ixcvhwlp1p0
+#ld: -melf32lriscv
+#error_output: cv-hwlp-setupi-fail.l
diff --git a/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-fail.l b/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-fail.l
new file mode 100644
index 00000000000..3b630872a8b
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-fail.l
@@ -0,0 +1,2 @@
+.*: in function \`_start\':
+.*: relocation truncated to fit: R_RISCV_CVPCREL_URS1 against \`lp0\'
diff --git a/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-fail.s b/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-fail.s
new file mode 100644
index 00000000000..37c5ceed3f5
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi-fail.s
@@ -0,0 +1,23 @@
+# Test if symbolic arguments to setupi work.
+#
+#	Macro to generate word length NOPS
+#
+	.macro wnops count=1
+	nop
+	nop
+	.ifne \count
+	wnops "(\count-1)"
+	.endif
+	.endm
+#
+#	Declare as a global function so it will link
+#
+	.global	_start
+	.func _start
+_start:
+	cv.setupi 0, 42, lp0
+	wnops	29
+lp0:
+	cv.setupi 0, 561, lp1
+	wnops	30
+lp1:
diff --git a/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi.d b/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi.d
new file mode 100644
index 00000000000..c000a75b0ce
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi.d
@@ -0,0 +1,21 @@
+#name: setupi relocation
+#source: cv-hwlp-setupi.s
+#as: -march=rv32i_xcvhwlp
+#ld: -melf32lriscv
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+.* <func>:
+.*:[[:space:]]+00008067[[:space:]]+ret
+
+.* <_start>:
+.*:[[:space:]]+00a1462b[[:space:]]+cv.setupi[[:space:]]+0,10,.*[[:space:]]+<L2>
+.*:[[:space:]]+ff9ff0ef[[:space:]]+jal[[:space:]]+10074[[:space:]]+<func>
+
+.* <L2>:
+.*:[[:space:]]+00000013[[:space:]]+nop
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi.s b/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi.s
new file mode 100644
index 00000000000..6bbdf7582ea
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-hwlp-setupi.s
@@ -0,0 +1,11 @@
+        .option nopic
+        .text
+        .align 1
+        .globl _start
+        .type _start, @function
+
+func:   ret
+_start:
+        cv.setupi       0,10,L2
+        call func
+L2:     nop
diff --git a/ld/testsuite/ld-riscv-elf/cv-hwlp-starti-2.d b/ld/testsuite/ld-riscv-elf/cv-hwlp-starti-2.d
new file mode 100644
index 00000000000..06973cc2205
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-hwlp-starti-2.d
@@ -0,0 +1,15 @@
+#as: -march=rv32ixcvhwlp1p0
+#ld: -melf32lriscv
+#objdump: -dr
+
+.*:[    ]+file format .*
+
+
+Disassembly of section .text:
+
+00010078 <_start>:
+.*:[[:space:]]+08c0402b[[:space:]]+cv.starti[[:space:]]+0,102a8[[:space:]]+<lp0\+0x21c>
+.*:[[:space:]]+0040422b[[:space:]]+cv.endi[[:space:]]+0,1008c[[:space:]]+<lp0>
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
+.*:[[:space:]]+00000013[[:space:]]+nop
diff --git a/ld/testsuite/ld-riscv-elf/cv-hwlp-starti-2.s b/ld/testsuite/ld-riscv-elf/cv-hwlp-starti-2.s
new file mode 100644
index 00000000000..f1979beae3a
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-hwlp-starti-2.s
@@ -0,0 +1,276 @@
+#
+#    Declare as a global function so it will link
+#
+    .global    _start
+    .func _start
+_start:
+    .option norvc
+    # We can't control whether this loop will be aligned or not, but if
+    # it is not, then the next one will be.
+    cv.starti 0, 560
+    cv.endi 0, lp0
+    nop
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    .balign    8
+    nop
+lp0:
diff --git a/ld/testsuite/ld-riscv-elf/cv-hwlp-starti-fail.d b/ld/testsuite/ld-riscv-elf/cv-hwlp-starti-fail.d
new file mode 100644
index 00000000000..06ae085cab0
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-hwlp-starti-fail.d
@@ -0,0 +1,4 @@
+#source: cv-hwlp-starti-fail.s
+#as: -march=rv32ixcvhwlp1p0
+#ld: -melf32lriscv
+#error_output: cv-hwlp-starti-fail.l
diff --git a/ld/testsuite/ld-riscv-elf/cv-hwlp-starti-fail.l b/ld/testsuite/ld-riscv-elf/cv-hwlp-starti-fail.l
new file mode 100644
index 00000000000..b480c5f35e3
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-hwlp-starti-fail.l
@@ -0,0 +1,2 @@
+.*: in function \`lp0\':
+.*: relocation truncated to fit: R_RISCV_CVPCREL_UI12 against \`lp1\'
diff --git a/ld/testsuite/ld-riscv-elf/cv-hwlp-starti-fail.s b/ld/testsuite/ld-riscv-elf/cv-hwlp-starti-fail.s
new file mode 100644
index 00000000000..d12316a8256
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-hwlp-starti-fail.s
@@ -0,0 +1,113 @@
+# Test if symbolic arguments to starti work.
+#
+#	Macro to generate word length NOPS
+#
+	.macro wnops count=1
+	nop
+	nop
+	.ifne \count
+	wnops "(\count-1)"
+	.endif
+	.endm
+#
+#	Declare as a global function so it will link
+#
+	.global	_start
+	.func _start
+_start:
+	cv.starti 0, 40
+	cv.endi 0, lp0
+	wnops	29
+lp0:
+	cv.starti 0, 560
+	cv.endi 0, lp1
+	wnops	90
+	nop
+	wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+        nop
+        wnops   90
+lp1:
diff --git a/ld/testsuite/ld-riscv-elf/cv-hwlp-starti.d b/ld/testsuite/ld-riscv-elf/cv-hwlp-starti.d
new file mode 100644
index 00000000000..f170cf922e7
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-hwlp-starti.d
@@ -0,0 +1,21 @@
+#name: starti relocation
+#source: cv-hwlp-starti.s
+#as: -march=rv32i_xcvhwlp
+#ld: -melf32lriscv
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+.* <func>:
+.*:[[:space:]]+00008067[[:space:]]+ret
+
+.* <_start>:
+.*:[[:space:]]+0020402b[[:space:]]+cv.starti[[:space:]]+0,.*[[:space:]]+<L2>
+.*:[[:space:]]+ff9ff0ef[[:space:]]+jal[[:space:]]+10074[[:space:]]+<func>
+
+.* <L2>:
+.*:[[:space:]]+00000013[[:space:]]+nop
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/cv-hwlp-starti.s b/ld/testsuite/ld-riscv-elf/cv-hwlp-starti.s
new file mode 100644
index 00000000000..db8fe5f9533
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/cv-hwlp-starti.s
@@ -0,0 +1,11 @@
+        .option nopic
+        .text
+        .align 1
+        .globl _start
+        .type _start, @function
+
+func:   ret
+_start:
+        cv.starti       0,L2
+        call func
+L2:     nop
diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
index 947a266ba72..5d44226da29 100644
--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
@@ -173,6 +173,15 @@ if [istarget "riscv*-*-*"] {
     run_dump_test "attr-phdr"
     run_dump_test "relax-max-align-gp"
     run_dump_test "uleb128"
+    # CORE-V Specific Tests
+    run_dump_test "cv-hwlp-starti"
+    run_dump_test "cv-hwlp-endi"
+    run_dump_test "cv-hwlp-setup"
+    run_dump_test "cv-hwlp-setupi"
+    run_dump_test "cv-hwlp-setupi-fail"
+    run_dump_test "cv-hwlp-starti-fail"
+    run_dump_test "cv-hwlp-setupi-2"
+    run_dump_test "cv-hwlp-starti-2"
     run_ld_link_tests [list \
 	[list "Weak reference 32" "-T weakref.ld -m[riscv_choose_ilp32_emul]" "" \
 	    "-march=rv32i -mabi=ilp32" {weakref32.s} \
diff --git a/opcodes/ChangeLog.COREV b/opcodes/ChangeLog.COREV
new file mode 100644
index 00000000000..ebf7e36f409
--- /dev/null
+++ b/opcodes/ChangeLog.COREV
@@ -0,0 +1,20 @@
+2021-08-28  Jessica Mills  <jessica.mills@embecosm.com>
+
+	* riscv-opc.c (MATCH_CV_EXTHS, MATCH_CV_EXTHZ, MATCH_CV_EXTBS)
+	(MATCH_CV_EXTBZ): Add new match.
+	(riscv_opcodes): Fix indentation inconsistencies.
+
+2020-11-10  Mary Bennett  <mary.bennett@embecosm.com>
+
+	* riscv-opc.c (print_insn_args): Renamed macros for clarity -
+	EXTRACT_I1TYPE_UIMM-> EXTRACT_CV_HWLP_UIMM5
+	EXTRACT_ITYPE_UIMM -> EXTRACT_CV_HWLP_UIMM12
+
+2020-10-08  Mary Bennett  <mary.bennett@embecosm.com>
+
+	* riscv-opc.c: Added support for corevhwlp.
+
+2020-09-10  Pietra Ferreira  <pietra.ferreira@embecosm.com>
+
+	* riscv-dis.c: Added CORE-V hardware loop support.
+	* riscv-opc.c: Likewise.
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 83f4e7f5356..4beb9168978 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -4,6 +4,13 @@
    Contributed by Andrew Waterman (andrew@sifive.com).
    Based on MIPS target.
 
+   Modified for CORE-V by:
+   Mary Bennett (mary.bennett@embecosm.com)
+   Pietra Ferreira (pietra.ferreira@embecosm.com)
+   Jessica Mills (jessica.mills@embecosm.com)
+
+   Some of these changes are (C) Open Hardware Group, pending FSF assignment.
+
    This file is part of the GNU opcodes library.
 
    This library is free software; you can redistribute it and/or modify
@@ -429,6 +436,21 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	    print (info->stream, dis_style_immediate, "0");
 	  break;
 
+	/* CORE-V Specific.  */
+	case 'b':
+	  if (oparg[1] == '1')
+	    {
+	      info->target = (EXTRACT_ITYPE_IMM (l)<<2) + pc; ++oparg;
+	      (*info->print_address_func) (info->target, info);
+	      break;
+            }
+	  else if (oparg[1] == '2')
+	    {
+	      info->target = (EXTRACT_CV_HWLP_UIMM5 (l)<<2) + pc; ++oparg;
+	      (*info->print_address_func) (info->target, info);
+	      break;
+	    }
+	/* Fall through.  */
 	case 's':
 	  if ((l & MASK_JALR) == MATCH_JALR)
 	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
@@ -464,6 +486,13 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	  maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
 	  /* Fall through.  */
 	case 'j':
+		/* ji is CORE-V Specific.  */
+	  if (oparg[1] == 'i')
+	    {
+	      ++oparg;
+	      print (info->stream, dis_style_immediate, "%d", (int) EXTRACT_CV_HWLP_UIMM12 (l));
+	      break;
+	    }
 	  if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
 	      || (l & MASK_JALR) == MATCH_JALR)
 	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
@@ -497,7 +526,15 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	    pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l);
 	  else if ((l & MASK_C_LUI) == MATCH_C_LUI)
 	    pd->hi_addr[rd] = EXTRACT_CITYPE_LUI_IMM (l);
-	  print (info->stream, dis_style_register, "%s", riscv_gpr_names[rd]);
+	  if (oparg[1] == 'i')
+	    {
+	      ++oparg;
+	      /* di refers to just bit 7. Therefore we have masked the top 4 bits
+	       *  of rd, bits 11 to 7. */
+	      print (info->stream, dis_style_immediate, "%d", (int) (rd & 0b00001));
+	    }
+	  else
+	    print (info->stream, dis_style_register, "%s", riscv_gpr_names[rd]);
 	  break;
 
 	case 'y':
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 4cee97e43bf..e92c732fd28 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2100,6 +2100,16 @@ const struct riscv_opcode riscv_opcodes[] =
 {"cv.subrnr",  0, INSN_CLASS_XCVALU, "d,s,t",     MATCH_CV_SUBRNR,  MASK_CV_SUBRNR, match_opcode, 0},
 {"cv.suburnr", 0, INSN_CLASS_XCVALU, "d,s,t",     MATCH_CV_SUBURNR, MASK_CV_SUBURNR, match_opcode, 0},
 
+/* Vendor-specific (CORE-V) Xcvhwlp instructions.  */
+{"cv.start",  0, INSN_CLASS_XCVHWLP, "di,s",     MATCH_CV_START,  MASK_CV_START,  match_opcode, 0},
+{"cv.starti", 0, INSN_CLASS_XCVHWLP, "di,b1",    MATCH_CV_STARTI, MASK_CV_STARTI, match_opcode, 0},
+{"cv.end",    0, INSN_CLASS_XCVHWLP, "di,s",     MATCH_CV_END,    MASK_CV_END,    match_opcode, 0},
+{"cv.endi",   0, INSN_CLASS_XCVHWLP, "di,b1",    MATCH_CV_ENDI,   MASK_CV_ENDI,   match_opcode, 0},
+{"cv.count",  0, INSN_CLASS_XCVHWLP, "di,s",     MATCH_CV_COUNT,  MASK_CV_COUNT,  match_opcode, 0},
+{"cv.counti", 0, INSN_CLASS_XCVHWLP, "di,ji",    MATCH_CV_COUNTI, MASK_CV_COUNTI, match_opcode, 0},
+{"cv.setup",  0, INSN_CLASS_XCVHWLP, "di,s,b1",  MATCH_CV_SETUP,  MASK_CV_SETUP,  match_opcode, 0},
+{"cv.setupi", 0, INSN_CLASS_XCVHWLP, "di,ji,b2", MATCH_CV_SETUPI, MASK_CV_SETUPI, match_opcode, 0},
+
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 {"th.addsl",    0, INSN_CLASS_XTHEADBA,    "d,s,t,Xtu2@25",   MATCH_TH_ADDSL,    MASK_TH_ADDSL,    match_opcode, 0},