From d415802ca856334f6d6e0be9ae2cefe4ddbe597e Mon Sep 17 00:00:00 2001 From: NandniJamnadas Date: Fri, 7 Oct 2022 12:32:42 +0100 Subject: [PATCH] PULP: Added Event Load Instructions + Tests Version 1.0.0 extension in assembler The event load instruction cv.elw is only supported if the PULP_CLUSTER parameter is set to 1. The event load performs a load word and can cause the CV32E41P to enter a sleep state bfd/ * elfxx-riscv.c: (riscv_multi_subset_supports): Added INSN_CLASS_XCOREVELW. * elfxx-riscv.c: (riscv_multi_subset_supports_ext): Likewise. gas/ * testsuite/gas/riscv/cv-elw-pass.d: Added supported instruction test. * testsuite/gas/riscv/cv-elw-pass.s: Likewise. * testsuite/gas/riscv/cv-elw-fail.d: Added unsupported instruction test. * testsuite/gas/riscv/cv-elw-fail.s: Likewise. * testsuite/gas/riscv/cv-elw-pass.l: Likewise. include/ * opcode/riscv-opc.h: Added corresponding MATCH and MASK instruction opcode macros. * opcode/riscv-opc.h: Added corresponding DECLARE_INSN. * opcode/riscv.h: (riscv_insn_class) Added INSN_CLASS_COREV_ELW. opcodes/ * riscv-opc.c: (riscv_opcode) Added event load instructions. Signed-off-by: NandniJamnadas --- bfd/elfxx-riscv.c | 5 ++ gas/config/tc-riscv.c | 2 +- gas/doc/c-riscv.texi | 5 ++ gas/testsuite/gas/riscv/cv-elw-fail.d | 3 ++ gas/testsuite/gas/riscv/cv-elw-fail.l | 5 ++ gas/testsuite/gas/riscv/cv-elw-fail.s | 8 ++++ gas/testsuite/gas/riscv/cv-elw-march-fail.d | 3 ++ gas/testsuite/gas/riscv/cv-elw-march-fail.l | 38 +++++++++++++++ gas/testsuite/gas/riscv/cv-elw-march-fail.s | 42 +++++++++++++++++ gas/testsuite/gas/riscv/cv-elw-march-xcorev.d | 46 +++++++++++++++++++ gas/testsuite/gas/riscv/cv-elw-march-xcorev.s | 42 +++++++++++++++++ gas/testsuite/gas/riscv/cv-elw-pass.d | 46 +++++++++++++++++++ gas/testsuite/gas/riscv/cv-elw-pass.s | 42 +++++++++++++++++ include/opcode/riscv-opc.h | 3 ++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 3 ++ 16 files changed, 293 insertions(+), 1 deletion(-) create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-elw-march-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-elw-march-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-elw-march-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-elw-march-xcorev.d create mode 100644 gas/testsuite/gas/riscv/cv-elw-march-xcorev.s create mode 100644 gas/testsuite/gas/riscv/cv-elw-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-elw-pass.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 0b091e039cc..eb5e254870a 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1394,6 +1394,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xcvhwlp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xcvmem", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xcvbi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xcvelw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2602,6 +2603,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xcvmem"); case INSN_CLASS_XCVBI: return riscv_subset_supports (rps, "xcvbi"); + case INSN_CLASS_XCVELW: + return riscv_subset_supports (rps, "xcvelw"); case INSN_CLASS_XTHEADBA: return riscv_subset_supports (rps, "xtheadba"); case INSN_CLASS_XTHEADBB: @@ -2852,6 +2855,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xcvmem"; case INSN_CLASS_XCVBI: return "xcvbi"; + case INSN_CLASS_XCVELW: + return "xcvelw"; case INSN_CLASS_XTHEADBA: return "xtheadba"; case INSN_CLASS_XTHEADBB: diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 4d2bc4c6cc6..0f0f07278c3 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1400,7 +1400,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) used_bits |= ENCODE_CV_HWLP_LN(-1U); ++oparg; break; - } + } USE_BITS (OP_MASK_RD, OP_SH_RD); break; case 'y': USE_BITS (OP_MASK_BS, OP_SH_BS); break; case 'Y': USE_BITS (OP_MASK_RNUM, OP_SH_RNUM); break; diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 7edde3162fe..1fe936c5c77 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -770,6 +770,11 @@ The Xcvbi extension provides instructions for branch immediate operations. It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html} +@item Xcvelw +The Xcvelw extension provides instructions for event load word operations. + +It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html} + @item XTheadBa The XTheadBa extension provides instructions for address calculations. diff --git a/gas/testsuite/gas/riscv/cv-elw-fail.d b/gas/testsuite/gas/riscv/cv-elw-fail.d new file mode 100644 index 00000000000..d7fd1d1a6cb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-elw-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcvelw +#source: cv-elw-fail.s +#error_output: cv-elw-fail.l diff --git a/gas/testsuite/gas/riscv/cv-elw-fail.l b/gas/testsuite/gas/riscv/cv-elw-fail.l new file mode 100644 index 00000000000..4d3f15ba138 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-elw-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.elw x5,-2049\(x6\)' +.*: Error: illegal operands `cv.elw x5,2048\(x6\)' +.*: Error: illegal operands `cv.elw x-1,1024\(x-1\)' +.*: Error: illegal operands `cv.elw x32,1024\(x32\)' \ No newline at end of file diff --git a/gas/testsuite/gas/riscv/cv-elw-fail.s b/gas/testsuite/gas/riscv/cv-elw-fail.s new file mode 100644 index 00000000000..4ce122297f4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-elw-fail.s @@ -0,0 +1,8 @@ +target: + # Immediate Boundary Tests + cv.elw x5,-2049(x6) + cv.elw x5,2048(x6) + + # Register Boundary Tests + cv.elw x-1,1024(x-1) + cv.elw x32,1024(x32) diff --git a/gas/testsuite/gas/riscv/cv-elw-march-fail.d b/gas/testsuite/gas/riscv/cv-elw-march-fail.d new file mode 100644 index 00000000000..2deb7ac1bee --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-elw-march-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i +#source: cv-elw-march-fail.s +#error_output: cv-elw-march-fail.l diff --git a/gas/testsuite/gas/riscv/cv-elw-march-fail.l b/gas/testsuite/gas/riscv/cv-elw-march-fail.l new file mode 100644 index 00000000000..e80988bf6fa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-elw-march-fail.l @@ -0,0 +1,38 @@ +.*: Assembler messages: +.*: Error: unrecognized opcode `cv.elw x5,-2048\(x6\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x5,0\(x6\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x5,20\(x6\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x5,2047\(x6\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x31,2047\(x31\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x0,0\(x0\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x1,1024\(x1\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x2,1024\(x2\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x3,1024\(x3\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x4,1024\(x4\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x5,1024\(x5\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x6,1024\(x6\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x7,1024\(x7\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x8,1024\(x8\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x9,1024\(x9\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x10,1024\(x10\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x11,1024\(x11\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x12,1024\(x12\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x13,1024\(x13\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x14,1024\(x14\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x15,1024\(x15\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x16,1024\(x16\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x17,1024\(x17\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x18,1024\(x18\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x19,1024\(x19\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x20,1024\(x20\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x21,1024\(x21\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x22,1024\(x22\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x23,1024\(x23\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x24,1024\(x24\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x25,1024\(x25\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x26,1024\(x26\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x27,1024\(x27\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x28,1024\(x28\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x29,1024\(x29\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x30,1024\(x30\)', extension `xcorevelw' or `xcorev' required +.*: Error: unrecognized opcode `cv.elw x31,1024\(x31\)', extension `xcorevelw' or `xcorev' required diff --git a/gas/testsuite/gas/riscv/cv-elw-march-fail.s b/gas/testsuite/gas/riscv/cv-elw-march-fail.s new file mode 100644 index 00000000000..8728f1cbdee --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-elw-march-fail.s @@ -0,0 +1,42 @@ +target: + # Immediate Boundary Tests + cv.elw x5,-2048(x6) + cv.elw x5,0(x6) + cv.elw x5,20(x6) + cv.elw x5,2047(x6) + cv.elw x31,2047(x31) + + # Register Boundary Tests + cv.elw x0,0(x0) + cv.elw x1,1024(x1) + cv.elw x2,1024(x2) + cv.elw x3,1024(x3) + cv.elw x4,1024(x4) + cv.elw x5,1024(x5) + cv.elw x6,1024(x6) + cv.elw x7,1024(x7) + cv.elw x8,1024(x8) + cv.elw x9,1024(x9) + cv.elw x10,1024(x10) + cv.elw x11,1024(x11) + cv.elw x12,1024(x12) + cv.elw x13,1024(x13) + cv.elw x14,1024(x14) + cv.elw x15,1024(x15) + cv.elw x16,1024(x16) + cv.elw x17,1024(x17) + cv.elw x18,1024(x18) + cv.elw x19,1024(x19) + cv.elw x20,1024(x20) + cv.elw x21,1024(x21) + cv.elw x22,1024(x22) + cv.elw x23,1024(x23) + cv.elw x24,1024(x24) + cv.elw x25,1024(x25) + cv.elw x26,1024(x26) + cv.elw x27,1024(x27) + cv.elw x28,1024(x28) + cv.elw x29,1024(x29) + cv.elw x30,1024(x30) + cv.elw x31,1024(x31) + \ No newline at end of file diff --git a/gas/testsuite/gas/riscv/cv-elw-march-xcorev.d b/gas/testsuite/gas/riscv/cv-elw-march-xcorev.d new file mode 100644 index 00000000000..5d80990f7b1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-elw-march-xcorev.d @@ -0,0 +1,46 @@ +#as: -march=rv32i_xcorev1p0 +#source: cv-elw-pass.s +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+0:[ ]+80036283[ ]+cv.elw[ ]+t0,-2048\(t1\) +[ ]+4:[ ]+00036283[ ]+cv.elw[ ]+t0,0\(t1\) +[ ]+8:[ ]+01436283[ ]+cv.elw[ ]+t0,20\(t1\) +[ ]+c:[ ]+7ff36283[ ]+cv.elw[ ]+t0,2047\(t1\) +[ ]+10:[ ]+7fffef83[ ]+cv.elw[ ]+t6,2047\(t6\) +[ ]+14:[ ]+00006003[ ]+cv.elw[ ]+zero,0\(zero\) # 0 +[ ]+18:[ ]+4000e083[ ]+cv.elw[ ]+ra,1024\(ra\) +[ ]+1c:[ ]+40016103[ ]+cv.elw[ ]+sp,1024\(sp\) +[ ]+20:[ ]+4001e183[ ]+cv.elw[ ]+gp,1024\(gp\) +[ ]+24:[ ]+40026203[ ]+cv.elw[ ]+tp,1024\(tp\) # 400 +[ ]+28:[ ]+4002e283[ ]+cv.elw[ ]+t0,1024\(t0\) +[ ]+2c:[ ]+40036303[ ]+cv.elw[ ]+t1,1024\(t1\) +[ ]+30:[ ]+4003e383[ ]+cv.elw[ ]+t2,1024\(t2\) +[ ]+34:[ ]+40046403[ ]+cv.elw[ ]+s0,1024\(s0\) +[ ]+38:[ ]+4004e483[ ]+cv.elw[ ]+s1,1024\(s1\) +[ ]+3c:[ ]+40056503[ ]+cv.elw[ ]+a0,1024\(a0\) +[ ]+40:[ ]+4005e583[ ]+cv.elw[ ]+a1,1024\(a1\) +[ ]+44:[ ]+40066603[ ]+cv.elw[ ]+a2,1024\(a2\) +[ ]+48:[ ]+4006e683[ ]+cv.elw[ ]+a3,1024\(a3\) +[ ]+4c:[ ]+40076703[ ]+cv.elw[ ]+a4,1024\(a4\) +[ ]+50:[ ]+4007e783[ ]+cv.elw[ ]+a5,1024\(a5\) +[ ]+54:[ ]+40086803[ ]+cv.elw[ ]+a6,1024\(a6\) +[ ]+58:[ ]+4008e883[ ]+cv.elw[ ]+a7,1024\(a7\) +[ ]+5c:[ ]+40096903[ ]+cv.elw[ ]+s2,1024\(s2\) +[ ]+60:[ ]+4009e983[ ]+cv.elw[ ]+s3,1024\(s3\) +[ ]+64:[ ]+400a6a03[ ]+cv.elw[ ]+s4,1024\(s4\) +[ ]+68:[ ]+400aea83[ ]+cv.elw[ ]+s5,1024\(s5\) +[ ]+6c:[ ]+400b6b03[ ]+cv.elw[ ]+s6,1024\(s6\) +[ ]+70:[ ]+400beb83[ ]+cv.elw[ ]+s7,1024\(s7\) +[ ]+74:[ ]+400c6c03[ ]+cv.elw[ ]+s8,1024\(s8\) +[ ]+78:[ ]+400cec83[ ]+cv.elw[ ]+s9,1024\(s9\) +[ ]+7c:[ ]+400d6d03[ ]+cv.elw[ ]+s10,1024\(s10\) +[ ]+80:[ ]+400ded83[ ]+cv.elw[ ]+s11,1024\(s11\) +[ ]+84:[ ]+400e6e03[ ]+cv.elw[ ]+t3,1024\(t3\) +[ ]+88:[ ]+400eee83[ ]+cv.elw[ ]+t4,1024\(t4\) +[ ]+8c:[ ]+400f6f03[ ]+cv.elw[ ]+t5,1024\(t5\) +[ ]+90:[ ]+400fef83[ ]+cv.elw[ ]+t6,1024\(t6\) diff --git a/gas/testsuite/gas/riscv/cv-elw-march-xcorev.s b/gas/testsuite/gas/riscv/cv-elw-march-xcorev.s new file mode 100644 index 00000000000..ed6d1882f06 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-elw-march-xcorev.s @@ -0,0 +1,42 @@ +target: + # Immediate Boundary Tests + cv.elw x5,-2048(x6) + cv.elw x5,0(x6) + cv.elw x5,20(x6) + cv.elw x5,2047(x6) + cv.elw x31,2047(x31) + + # Register Boundary Tests + cv.elw x0,0(x0) + cv.elw x1,1024(x1) + cv.elw x2,1024(x2) + cv.elw x3,1024(x3) + cv.elw x4,1024(x4) + cv.elw x5,1024(x5) + cv.elw x6,1024(x6) + cv.elw x7,1024(x7) + cv.elw x8,1024(x8) + cv.elw x9,1024(x9) + cv.elw x10,1024(x10) + cv.elw x11,1024(x11) + cv.elw x12,1024(x12) + cv.elw x13,1024(x13) + cv.elw x14,1024(x14) + cv.elw x15,1024(x15) + cv.elw x16,1024(x16) + cv.elw x17,1024(x17) + cv.elw x18,1024(x18) + cv.elw x19,1024(x19) + cv.elw x20,1024(x20) + cv.elw x21,1024(x21) + cv.elw x22,1024(x22) + cv.elw x23,1024(x23) + cv.elw x24,1024(x24) + cv.elw x25,1024(x25) + cv.elw x26,1024(x26) + cv.elw x27,1024(x27) + cv.elw x28,1024(x28) + cv.elw x29,1024(x29) + cv.elw x30,1024(x30) + cv.elw x31,1024(x31) + \ No newline at end of file diff --git a/gas/testsuite/gas/riscv/cv-elw-pass.d b/gas/testsuite/gas/riscv/cv-elw-pass.d new file mode 100644 index 00000000000..fed2c870e7e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-elw-pass.d @@ -0,0 +1,46 @@ +#as: -march=rv32i_xcvelw +#source: cv-elw-pass.s +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+0:[ ]+80036283[ ]+cv.elw[ ]+t0,-2048\(t1\) +[ ]+4:[ ]+00036283[ ]+cv.elw[ ]+t0,0\(t1\) +[ ]+8:[ ]+01436283[ ]+cv.elw[ ]+t0,20\(t1\) +[ ]+c:[ ]+7ff36283[ ]+cv.elw[ ]+t0,2047\(t1\) +[ ]+10:[ ]+7fffef83[ ]+cv.elw[ ]+t6,2047\(t6\) +[ ]+14:[ ]+00006003[ ]+cv.elw[ ]+zero,0\(zero\) # 0 +[ ]+18:[ ]+4000e083[ ]+cv.elw[ ]+ra,1024\(ra\) +[ ]+1c:[ ]+40016103[ ]+cv.elw[ ]+sp,1024\(sp\) +[ ]+20:[ ]+4001e183[ ]+cv.elw[ ]+gp,1024\(gp\) +[ ]+24:[ ]+40026203[ ]+cv.elw[ ]+tp,1024\(tp\) # 400 +[ ]+28:[ ]+4002e283[ ]+cv.elw[ ]+t0,1024\(t0\) +[ ]+2c:[ ]+40036303[ ]+cv.elw[ ]+t1,1024\(t1\) +[ ]+30:[ ]+4003e383[ ]+cv.elw[ ]+t2,1024\(t2\) +[ ]+34:[ ]+40046403[ ]+cv.elw[ ]+s0,1024\(s0\) +[ ]+38:[ ]+4004e483[ ]+cv.elw[ ]+s1,1024\(s1\) +[ ]+3c:[ ]+40056503[ ]+cv.elw[ ]+a0,1024\(a0\) +[ ]+40:[ ]+4005e583[ ]+cv.elw[ ]+a1,1024\(a1\) +[ ]+44:[ ]+40066603[ ]+cv.elw[ ]+a2,1024\(a2\) +[ ]+48:[ ]+4006e683[ ]+cv.elw[ ]+a3,1024\(a3\) +[ ]+4c:[ ]+40076703[ ]+cv.elw[ ]+a4,1024\(a4\) +[ ]+50:[ ]+4007e783[ ]+cv.elw[ ]+a5,1024\(a5\) +[ ]+54:[ ]+40086803[ ]+cv.elw[ ]+a6,1024\(a6\) +[ ]+58:[ ]+4008e883[ ]+cv.elw[ ]+a7,1024\(a7\) +[ ]+5c:[ ]+40096903[ ]+cv.elw[ ]+s2,1024\(s2\) +[ ]+60:[ ]+4009e983[ ]+cv.elw[ ]+s3,1024\(s3\) +[ ]+64:[ ]+400a6a03[ ]+cv.elw[ ]+s4,1024\(s4\) +[ ]+68:[ ]+400aea83[ ]+cv.elw[ ]+s5,1024\(s5\) +[ ]+6c:[ ]+400b6b03[ ]+cv.elw[ ]+s6,1024\(s6\) +[ ]+70:[ ]+400beb83[ ]+cv.elw[ ]+s7,1024\(s7\) +[ ]+74:[ ]+400c6c03[ ]+cv.elw[ ]+s8,1024\(s8\) +[ ]+78:[ ]+400cec83[ ]+cv.elw[ ]+s9,1024\(s9\) +[ ]+7c:[ ]+400d6d03[ ]+cv.elw[ ]+s10,1024\(s10\) +[ ]+80:[ ]+400ded83[ ]+cv.elw[ ]+s11,1024\(s11\) +[ ]+84:[ ]+400e6e03[ ]+cv.elw[ ]+t3,1024\(t3\) +[ ]+88:[ ]+400eee83[ ]+cv.elw[ ]+t4,1024\(t4\) +[ ]+8c:[ ]+400f6f03[ ]+cv.elw[ ]+t5,1024\(t5\) +[ ]+90:[ ]+400fef83[ ]+cv.elw[ ]+t6,1024\(t6\) diff --git a/gas/testsuite/gas/riscv/cv-elw-pass.s b/gas/testsuite/gas/riscv/cv-elw-pass.s new file mode 100644 index 00000000000..ed6d1882f06 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-elw-pass.s @@ -0,0 +1,42 @@ +target: + # Immediate Boundary Tests + cv.elw x5,-2048(x6) + cv.elw x5,0(x6) + cv.elw x5,20(x6) + cv.elw x5,2047(x6) + cv.elw x31,2047(x31) + + # Register Boundary Tests + cv.elw x0,0(x0) + cv.elw x1,1024(x1) + cv.elw x2,1024(x2) + cv.elw x3,1024(x3) + cv.elw x4,1024(x4) + cv.elw x5,1024(x5) + cv.elw x6,1024(x6) + cv.elw x7,1024(x7) + cv.elw x8,1024(x8) + cv.elw x9,1024(x9) + cv.elw x10,1024(x10) + cv.elw x11,1024(x11) + cv.elw x12,1024(x12) + cv.elw x13,1024(x13) + cv.elw x14,1024(x14) + cv.elw x15,1024(x15) + cv.elw x16,1024(x16) + cv.elw x17,1024(x17) + cv.elw x18,1024(x18) + cv.elw x19,1024(x19) + cv.elw x20,1024(x20) + cv.elw x21,1024(x21) + cv.elw x22,1024(x22) + cv.elw x23,1024(x23) + cv.elw x24,1024(x24) + cv.elw x25,1024(x25) + cv.elw x26,1024(x26) + cv.elw x27,1024(x27) + cv.elw x28,1024(x28) + cv.elw x29,1024(x29) + cv.elw x30,1024(x30) + cv.elw x31,1024(x31) + \ No newline at end of file diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index faa176d8f35..209c5a0ffe9 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2484,6 +2484,9 @@ #define MATCH_CV_BEQIMM 0x600b #define MASK_CV_BNEIMM 0x707f #define MASK_CV_BEQIMM 0x707f +/* Vendor-specific (CORE-V) Xcvelw instructions. */ +#define MATCH_CV_ELW 0x6003 +#define MASK_CV_ELW 0x707f /* Vendor-specific (T-Head) XTheadBa instructions. */ #define MATCH_TH_ADDSL 0x0000100b #define MASK_TH_ADDSL 0xf800707f diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 3e289338cda..ad2fb1f5288 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -481,6 +481,7 @@ enum riscv_insn_class INSN_CLASS_XCVHWLP, INSN_CLASS_XCVMEM, INSN_CLASS_XCVBI, + INSN_CLASS_XCVELW, INSN_CLASS_XTHEADBA, INSN_CLASS_XTHEADBB, INSN_CLASS_XTHEADBS, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 5d27522907d..2580eb0817d 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2278,6 +2278,9 @@ const struct riscv_opcode riscv_opcodes[] = {"cv.beqimm", 0, INSN_CLASS_XCVBI, "s,b4,p", MATCH_CV_BEQIMM, MASK_CV_BEQIMM, match_opcode, 0}, {"cv.bneimm", 0, INSN_CLASS_XCVBI, "s,b4,p", MATCH_CV_BNEIMM, MASK_CV_BNEIMM, match_opcode, 0}, +/* Event Load */ +{"cv.elw", 0, INSN_CLASS_XCVELW, "d,o(s)", MATCH_CV_ELW, MASK_CV_ELW, match_opcode, 0}, + /* Terminate the list. */ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} };