From 25ea49088d00962811fa70765f904165bb82585a Mon Sep 17 00:00:00 2001 From: Jiawei Date: Fri, 21 Apr 2023 15:57:25 +0800 Subject: [PATCH] RISC-V: Add Zcmp cm.mv instructions testcases. --- gas/testsuite/gas/riscv/zc-test-no-zcmp.d | 24 +++++++++++++++++++ gas/testsuite/gas/riscv/zc-zcmp-mv-mix.d | 22 +++++++++++++++++ gas/testsuite/gas/riscv/zc-zcmp-mv-mix.s | 16 +++++++++++++ gas/testsuite/gas/riscv/zc-zcmp-mva01s.d | 22 +++++++++++++++++ gas/testsuite/gas/riscv/zc-zcmp-mva01s.s | 19 +++++++++++++++ gas/testsuite/gas/riscv/zc-zcmp-mvsa01-fail.d | 3 +++ gas/testsuite/gas/riscv/zc-zcmp-mvsa01-fail.l | 7 ++++++ gas/testsuite/gas/riscv/zc-zcmp-mvsa01-fail.s | 10 ++++++++ gas/testsuite/gas/riscv/zc-zcmp-mvsa01.d | 24 +++++++++++++++++++ gas/testsuite/gas/riscv/zc-zcmp-mvsa01.s | 19 +++++++++++++++ 10 files changed, 166 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zc-test-no-zcmp.d create mode 100644 gas/testsuite/gas/riscv/zc-zcmp-mv-mix.d create mode 100644 gas/testsuite/gas/riscv/zc-zcmp-mv-mix.s create mode 100644 gas/testsuite/gas/riscv/zc-zcmp-mva01s.d create mode 100644 gas/testsuite/gas/riscv/zc-zcmp-mva01s.s create mode 100644 gas/testsuite/gas/riscv/zc-zcmp-mvsa01-fail.d create mode 100644 gas/testsuite/gas/riscv/zc-zcmp-mvsa01-fail.l create mode 100644 gas/testsuite/gas/riscv/zc-zcmp-mvsa01-fail.s create mode 100644 gas/testsuite/gas/riscv/zc-zcmp-mvsa01.d create mode 100644 gas/testsuite/gas/riscv/zc-zcmp-mvsa01.s diff --git a/gas/testsuite/gas/riscv/zc-test-no-zcmp.d b/gas/testsuite/gas/riscv/zc-test-no-zcmp.d new file mode 100644 index 00000000000..b23c3996091 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-test-no-zcmp.d @@ -0,0 +1,24 @@ +#as: -march=rv64i_zca +#source: zc-zcmp-mv-mix.s +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s1 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s6,a1 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s2 +0+006 : +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s3,a1 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s3 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s3,a1 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s3 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a1,s2 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s3 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s3,a1 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s3,a2 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a1,s3 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s4 diff --git a/gas/testsuite/gas/riscv/zc-zcmp-mv-mix.d b/gas/testsuite/gas/riscv/zc-zcmp-mv-mix.d new file mode 100644 index 00000000000..01b81e92694 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcmp-mv-mix.d @@ -0,0 +1,22 @@ +#as: -march=rv64i_zca_zcmp +#source: zc-zcmp-mv-mix.s +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s1 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s6,a1 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s2 +0+006 : +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s3,a1 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s3 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s3,a1 +[ ]*[0-9a-f]+:[ ]+adea[ ]+cm.mva01s[ ]+s3,s2 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s3 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s3,a1 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s3,a2 +[ ]*[0-9a-f]+:[ ]+ae6e[ ]+cm.mva01s[ ]+s4,s3 diff --git a/gas/testsuite/gas/riscv/zc-zcmp-mv-mix.s b/gas/testsuite/gas/riscv/zc-zcmp-mv-mix.s new file mode 100644 index 00000000000..f7b0d1d18d9 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcmp-mv-mix.s @@ -0,0 +1,16 @@ +target: + mv a0, s1 + mv s6, a1 + mv a0, s2 +L2: + mv s3, a1 + mv a0, s3 + mv s3, a1 + # merge + mv a0, s3 + mv a1, s2 + mv a0, s3 + mv s3, a1 + mv s3, a2 + mv a1, s3 + mv a0, s4 diff --git a/gas/testsuite/gas/riscv/zc-zcmp-mva01s.d b/gas/testsuite/gas/riscv/zc-zcmp-mva01s.d new file mode 100644 index 00000000000..56b7f6d00af --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcmp-mva01s.d @@ -0,0 +1,22 @@ +#as: -march=rv64i_zca_zcmp +#source: zc-zcmp-mva01s.s +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s1 +[ ]*[0-9a-f]+:[ ]+acea[ ]+cm.mva01s[ ]+s1,s2 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s1 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s8 +[ ]*[0-9a-f]+:[ ]+adfe[ ]+cm.mva01s[ ]+s3,s7 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s1 +0+00c : +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a1,s3 +[ ]*[0-9a-f]+:[ ]+ac7e[ ]+cm.mva01s[ ]+s0,s7 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s4 +[ ]*[0-9a-f]+:[ ]+ac7e[ ]+cm.mva01s[ ]+s0,s7 +[ ]*[0-9a-f]+:[ ]+affe[ ]+cm.mva01s[ ]+s7,s7 diff --git a/gas/testsuite/gas/riscv/zc-zcmp-mva01s.s b/gas/testsuite/gas/riscv/zc-zcmp-mva01s.s new file mode 100644 index 00000000000..6435ef667c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcmp-mva01s.s @@ -0,0 +1,19 @@ +target: + mv a0, s1 # dst registers should be one a0 and one a1 + # merge + mv a0, s1 + mv a1, s2 + mv a0, s1 + mv a0, s8 # s0 is out of range + # merge + mv a1, s7 + mv a0, s3 + mv a0, s1 # can't merge across label. +L2: + mv a1, s3 + cm.mva01s s0, s7 + mv a0, s4 + cm.mva01s s0, s7 + # merge + mv a1, s7 + mv a0, s7 diff --git a/gas/testsuite/gas/riscv/zc-zcmp-mvsa01-fail.d b/gas/testsuite/gas/riscv/zc-zcmp-mvsa01-fail.d new file mode 100644 index 00000000000..2ade61af97e --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcmp-mvsa01-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64i_zca_zcmp +#source: zc-zcmp-mvsa01-fail.s +#error_output: zc-zcmp-mvsa01-fail.l diff --git a/gas/testsuite/gas/riscv/zc-zcmp-mvsa01-fail.l b/gas/testsuite/gas/riscv/zc-zcmp-mvsa01-fail.l new file mode 100644 index 00000000000..89746049d51 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcmp-mvsa01-fail.l @@ -0,0 +1,7 @@ +.*: Assembler messages: +.*: Error: illegal operands `cm.mvsa01 s0,s0' +.*: Error: illegal operands `cm.mvsa01 s1,s1' +.*: Error: illegal operands `cm.mvsa01 s7,s7' +.*: Error: illegal operands `cm.mvsa01 s0,s8' +.*: Error: illegal operands `cm.mvsa01 s8,s0' +.*: Error: illegal operands `cm.mvsa01 s0,a0' diff --git a/gas/testsuite/gas/riscv/zc-zcmp-mvsa01-fail.s b/gas/testsuite/gas/riscv/zc-zcmp-mvsa01-fail.s new file mode 100644 index 00000000000..608ac862af3 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcmp-mvsa01-fail.s @@ -0,0 +1,10 @@ +target: + # sreg1 != sreg2 + cm.mvsa01 s0,s0 + cm.mvsa01 s1,s1 + cm.mvsa01 s7,s7 + + # invalid range + cm.mvsa01 s0,s8 + cm.mvsa01 s8,s0 + cm.mvsa01 s0,a0 diff --git a/gas/testsuite/gas/riscv/zc-zcmp-mvsa01.d b/gas/testsuite/gas/riscv/zc-zcmp-mvsa01.d new file mode 100644 index 00000000000..d5ac9600464 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcmp-mvsa01.d @@ -0,0 +1,24 @@ +#as: -march=rv64i_zca_zcmp +#source: zc-zcmp-mvsa01.s +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s1,a0 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s2,a0 +[ ]*[0-9a-f]+:[ ]+acaa[ ]+cm.mvsa01[ ]+s1,s2 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s1,a0 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s8,a0 +[ ]*[0-9a-f]+:[ ]+adbe[ ]+cm.mvsa01[ ]+s3,s7 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s1,a0 +0+00e : +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s3,a1 +[ ]*[0-9a-f]+:[ ]+ac3e[ ]+cm.mvsa01[ ]+s0,s7 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s4,a0 +[ ]*[0-9a-f]+:[ ]+ac3e[ ]+cm.mvsa01[ ]+s0,s7 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s7,a1 +[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s7,a0 diff --git a/gas/testsuite/gas/riscv/zc-zcmp-mvsa01.s b/gas/testsuite/gas/riscv/zc-zcmp-mvsa01.s new file mode 100644 index 00000000000..2302aa9bd2c --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcmp-mvsa01.s @@ -0,0 +1,19 @@ +target: + mv s1, a0 # src registers should be one a0 and one a1 + mv s2, a0 + # merge + mv s1, a0 + mv s2, a1 + mv s1, a0 + mv s8, a0 # s0 is out of range + # merge + mv s7, a1 + mv s3, a0 + mv s1, a0 # can't merge across label. +L2: + mv s3, a1 + cm.mvsa01 s0, s7 + mv s4, a0 + cm.mvsa01 s0, s7 + mv s7, a1 # dst can't be the same + mv s7, a0