diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index b62f2adb993..0b091e039cc 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1393,6 +1393,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xcvhwlp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xcvmem", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xcvbi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2599,6 +2600,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xcvhwlp"); case INSN_CLASS_XCVMEM: return riscv_subset_supports (rps, "xcvmem"); + case INSN_CLASS_XCVBI: + return riscv_subset_supports (rps, "xcvbi"); case INSN_CLASS_XTHEADBA: return riscv_subset_supports (rps, "xtheadba"); case INSN_CLASS_XTHEADBB: @@ -2847,6 +2850,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xcvhwlp"; case INSN_CLASS_XCVMEM: return "xcvmem"; + case INSN_CLASS_XCVBI: + return "xcvbi"; case INSN_CLASS_XTHEADBA: return "xtheadba"; case INSN_CLASS_XTHEADBB: diff --git a/gas/ChangeLog.COREV b/gas/ChangeLog.COREV index 4cb6976122a..77b61387081 100644 --- a/gas/ChangeLog.COREV +++ b/gas/ChangeLog.COREV @@ -1,3 +1,14 @@ +2021-08-10 Nazareno Bruschi + + * config/tc-riscv.c (riscv_multi_subset_supports): Add immediate + branching instruction class. + (validate_riscv_insn, riscv_ip): Rename macro + ENCODE_CV_ALU_UIMM5 -> ENCODE_CV_UIMM5. + (validate_riscv_insn, riscv_ip): Add immediate branching + operand and modify PC-relative offset operand. + * doc/c-riscv.texi: Add details on CORE-V immediate + branching ops ISA options. + 2021-08-06 Enrico Tabanelli * config/tc-riscv.c (riscv_multi_subset_supports): Add diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index e0ad8673ccc..4d2bc4c6cc6 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1385,6 +1385,11 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) used_bits |= ENCODE_CV_HWLP_UIMM5(-1U); ++oparg; break; } + else if (oparg[1] == '4') + { + used_bits |= ENCODE_CV_UIMM5(-1U); + ++oparg; break; + } break; case 'c': break; /* Macro operand, must be symbol or constant. */ case 'I': break; /* Macro operand, must be constant. */ @@ -3337,9 +3342,13 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, asarg = expr_parse_end; continue; /* CORE-V Specific. - b1: pc rel 12 bits offset for cv.starti and cv.endi - sign-extended immediate as pc rel displacement for hwloop - b2: pc rel 5 bits unsigned offset for cv.setupi */ + b1: pc rel 12 bits offset for cv.starti and cv.endi + sign-extended immediate as pc rel displacement for hwloop + b2: pc rel 5 bits unsigned offset for cv.setupi + b3: 5 bits usigned offset for MAC + b4: 5 bits signed immediate bits[24..20] + bi: 5 bits unsigned offset for cv.clip and cv.clipu + ALU luimm5 [24...20] */ case 'b': if (oparg[1] == '1') { @@ -3404,6 +3413,17 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, *imm_reloc = BFD_RELOC_RISCV_CVPCREL_URS1; } } + else if (oparg[1] == '4') + { + my_getExpression (imm_expr, asarg); + check_absolute_expr (ip, imm_expr, FALSE); + asarg = expr_parse_end; + if (imm_expr->X_add_number<-16 || imm_expr->X_add_number>15) + as_bad(_("immediate value must be 5-bit signed, %ld is out of range"), + imm_expr->X_add_number); + ip->insn_opcode |= ENCODE_CV_UIMM5 (imm_expr->X_add_number); + ++oparg; + } else { my_getExpression (imm_expr, asarg); diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index e8c3ba962c7..7edde3162fe 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -765,6 +765,11 @@ The Xcvmem extension provides instructions for post inc load/store operations. It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html} +@item Xcvbi +The Xcvbi extension provides instructions for branch immediate operations. + +It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html} + @item XTheadBa The XTheadBa extension provides instructions for address calculations. diff --git a/gas/testsuite/ChangeLog.COREV b/gas/testsuite/ChangeLog.COREV index fe6c1c277fa..9ae54c885f5 100644 --- a/gas/testsuite/ChangeLog.COREV +++ b/gas/testsuite/ChangeLog.COREV @@ -1,3 +1,27 @@ +2021-08-10 Nazareno Bruschi + + * gas/riscv/cv-bi-beqimm.d: Add immediate branching test. + * gas/riscv/cv-bi-beqimm.s: Likewise. + * gas/riscv/cv-bi-bneimm.d: Likewise. + * gas/riscv/cv-bi-bneimm.s: Likewise. + * gas/riscv/cv-bi-fail-march.d: Likewise. + * gas/riscv/cv-bi-fail-march.l: Likewise. + * gas/riscv/cv-bi-fail-march.s: Likewise. + * gas/riscv/cv-bi-fail-operand-01.d: Likewise. + * gas/riscv/cv-bi-fail-operand-01.l: Likewise. + * gas/riscv/cv-bi-fail-operand-01.s: Likewise. + * gas/riscv/cv-bi-fail-operand-02.d: Likewise. + * gas/riscv/cv-bi-fail-operand-02.l: Likewise. + * gas/riscv/cv-bi-fail-operand-02.s: Likewise. + * gas/riscv/cv-bi-fail-operand-03.d: Likewise. + * gas/riscv/cv-bi-fail-operand-03.l: Likewise. + * gas/riscv/cv-bi-fail-operand-03.s: Likewise. + * gas/riscv/cv-bi-fail-operand-04.d: Likewise. + * gas/riscv/cv-bi-fail-operand-04.l: Likewise. + * gas/riscv/cv-bi-fail-operand-04.s: Likewise. + * gas/riscv/cv-bi-march-rv32i-xcorev.d: Likewise. + * gas/riscv/cv-bi-march-rv32i-xcorev.s: Likewise. + 2021-08-06 Enrico Tabanelli * gas/riscv/cv-mem-fail-operand-01.d: Add post-increment diff --git a/gas/testsuite/gas/riscv/cv-bi-beqimm.d b/gas/testsuite/gas/riscv/cv-bi-beqimm.d new file mode 100644 index 00000000000..97ef57d91cc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-bi-beqimm.d @@ -0,0 +1,12 @@ +#as: -march=rv32i_xcvbi +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+0:[ ]+0102e00b[ ]+cv.beqimm[ ]+t0,-16,0 + +[ ]+4:[ ]+fe5eee8b[ ]+cv.beqimm[ ]+t4,5,0 + +[ ]+8:[ ]+fef3ec8b[ ]+cv.beqimm[ ]+t2,15,0 + diff --git a/gas/testsuite/gas/riscv/cv-bi-beqimm.s b/gas/testsuite/gas/riscv/cv-bi-beqimm.s new file mode 100644 index 00000000000..7fbb8f27515 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-bi-beqimm.s @@ -0,0 +1,4 @@ +foo: + cv.beqimm t0, -16, foo + cv.beqimm t4, 5, foo + cv.beqimm t2, 15, foo diff --git a/gas/testsuite/gas/riscv/cv-bi-bneimm.d b/gas/testsuite/gas/riscv/cv-bi-bneimm.d new file mode 100644 index 00000000000..7dddf408107 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-bi-bneimm.d @@ -0,0 +1,12 @@ +#as: -march=rv32i_xcvbi +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+0:[ ]+0102f00b[ ]+cv.bneimm[ ]+t0,-16,0 + +[ ]+4:[ ]+fe5efe8b[ ]+cv.bneimm[ ]+t4,5,0 + +[ ]+8:[ ]+fef3fc8b[ ]+cv.bneimm[ ]+t2,15,0 + diff --git a/gas/testsuite/gas/riscv/cv-bi-bneimm.s b/gas/testsuite/gas/riscv/cv-bi-bneimm.s new file mode 100644 index 00000000000..8014e6a8a4f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-bi-bneimm.s @@ -0,0 +1,4 @@ +foo: + cv.bneimm t0, -16, foo + cv.bneimm t4, 5, foo + cv.bneimm t2, 15, foo diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-march.d b/gas/testsuite/gas/riscv/cv-bi-fail-march.d new file mode 100644 index 00000000000..7a24146afe2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-bi-fail-march.d @@ -0,0 +1,3 @@ +#as: -march=rv32i +#source: cv-bi-fail-march.s +#error_output: cv-bi-fail-march.l diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-march.l b/gas/testsuite/gas/riscv/cv-bi-fail-march.l new file mode 100644 index 00000000000..c351c64d414 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-bi-fail-march.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: unrecognized opcode `cv.beqimm t2,1,foo', extension `xcvbi' required +.*: Error: unrecognized opcode `cv.bneimm t2,1,foo', extension `xcvbi' required diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-march.s b/gas/testsuite/gas/riscv/cv-bi-fail-march.s new file mode 100644 index 00000000000..b7fa16de240 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-bi-fail-march.s @@ -0,0 +1,5 @@ +# Absence of xcorev or xcorevbi march option disables all CORE-V +# immediate branching extensions. +foo: + cv.beqimm t2, 1, foo + cv.bneimm t2, 1, foo diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d new file mode 100644 index 00000000000..cc73fdd6492 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcvbi +#source: cv-bi-fail-operand-01.s +#error_output: cv-bi-fail-operand-01.l diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l new file mode 100644 index 00000000000..c76c5139429 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.beqimm 20,10,foo' +.*: Error: illegal operands `cv.bneimm 8,-4,foo' diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s new file mode 100644 index 00000000000..7c529d4d045 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s @@ -0,0 +1,4 @@ +# Comparison target must be a register +foo: + cv.beqimm 20, 10, foo + cv.bneimm 8, -4, foo diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d new file mode 100644 index 00000000000..39741b9ed2b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcvbi +#source: cv-bi-fail-operand-02.s +#error_output: cv-bi-fail-operand-02.l diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l new file mode 100644 index 00000000000..7c766fb072a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: instruction cv.beqimm requires absolute expression +.*: Error: instruction cv.bneimm requires absolute expression diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s new file mode 100644 index 00000000000..5c8874cb9ac --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s @@ -0,0 +1,4 @@ +# Comparison value must be an immediate +foo: + cv.beqimm t0, t1, foo + cv.bneimm t3, t4, foo diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d new file mode 100644 index 00000000000..141efdeacc6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcvbi +#source: cv-bi-fail-operand-03.s +#error_output: cv-bi-fail-operand-03.l diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l new file mode 100644 index 00000000000..e32058eac91 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l @@ -0,0 +1,9 @@ +.*: Assembler messages: +.*: Error: immediate value must be 5-bit signed, -17 is out of range +.*: Error: immediate value must be 5-bit signed, -32 is out of range +.*: Error: immediate value must be 5-bit signed, 16 is out of range +.*: Error: immediate value must be 5-bit signed, 44 is out of range +.*: Error: immediate value must be 5-bit signed, -17 is out of range +.*: Error: immediate value must be 5-bit signed, -32 is out of range +.*: Error: immediate value must be 5-bit signed, 16 is out of range +.*: Error: immediate value must be 5-bit signed, 44 is out of range diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s new file mode 100644 index 00000000000..9c7f67b4aed --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s @@ -0,0 +1,10 @@ +# Comparison value must be an immediate in range [-16, +15] +foo: + cv.beqimm t0, -17, foo + cv.beqimm t2, -32, foo + cv.beqimm t4, 16, foo + cv.beqimm t3, 44, foo + cv.bneimm t0, -17, foo + cv.bneimm t2, -32, foo + cv.bneimm t4, 16, foo + cv.bneimm t3, 44, foo diff --git a/gas/testsuite/gas/riscv/cv-bi-march-rv32i-xcorev.d b/gas/testsuite/gas/riscv/cv-bi-march-rv32i-xcorev.d new file mode 100644 index 00000000000..baa250cb705 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-bi-march-rv32i-xcorev.d @@ -0,0 +1,11 @@ +#as: -march=rv32i_xcvbi +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+0:[ ]+0013e00b[ ]+cv.beqimm[ ]+t2,1,0 + +[ ]+4:[ ]+ff02fe8b[ ]+cv.bneimm[ ]+t0,-16,0 + diff --git a/gas/testsuite/gas/riscv/cv-bi-march-rv32i-xcorev.s b/gas/testsuite/gas/riscv/cv-bi-march-rv32i-xcorev.s new file mode 100644 index 00000000000..d0b20d515ca --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-bi-march-rv32i-xcorev.s @@ -0,0 +1,4 @@ +# xcorev march option works for all CORE-V immediate branching extensions +foo: + cv.beqimm t2, 1, foo + cv.bneimm t0, -16, foo diff --git a/include/ChangeLog.COREV b/include/ChangeLog.COREV index 297d7420bbd..57ec01ef992 100644 --- a/include/ChangeLog.COREV +++ b/include/ChangeLog.COREV @@ -1,3 +1,13 @@ +2021-08-10 Nazareno Bruschi + + * opcode/riscv-opc.h: Add immediate branching matches and + masks. + * opcode/riscv.h (riscv_insn_class, EXTRACT_CV_BI_IMM5): + Add immediate branching class and macros for 5-bit signed + immediate. + (ENCODE_CV_ALU_UIMM5): Rename macro as ENCODE_CV_UIMM5. + (RV_IMM_SIGN_N): Add macro for general sign extraction. + 2021-08-06 Enrico Tabanelli * riscv-opc.h: Add post-increment and register-indexed diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 93ffaf81b24..faa176d8f35 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2479,6 +2479,11 @@ #define MASK_CV_SPOST 0x707f #define MASK_CV_SRRPOST 0xfe00707f #define MASK_CV_SRR 0xfe00707f +/* Vendor-specific (CORE-V) Xcvbi instructions. */ +#define MATCH_CV_BNEIMM 0x700b +#define MATCH_CV_BEQIMM 0x600b +#define MASK_CV_BNEIMM 0x707f +#define MASK_CV_BEQIMM 0x707f /* Vendor-specific (T-Head) XTheadBa instructions. */ #define MATCH_TH_ADDSL 0x0000100b #define MASK_TH_ADDSL 0xf800707f diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 9539fcdaf06..3e289338cda 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -55,6 +55,7 @@ static inline unsigned int riscv_insn_length (insn_t insn) #define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1)) #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) #define RV_X_SIGNED(x, s, n) (RV_X(x, s, n) | ((-(RV_X(x, (s + n - 1), 1))) << (n))) +#define RV_IMM_SIGN_N(x, s, n) (-(((x) >> ((s) + (n) - 1)) & 1)) #define EXTRACT_ITYPE_IMM(x) \ (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12)) @@ -123,6 +124,8 @@ static inline unsigned int riscv_insn_length (insn_t insn) (RV_X(x, 7, 1)) #define EXTRACT_CV_HWLP_UIMM12(x) \ (RV_X(x, 20, 12)) +#define EXTRACT_CV_BI_IMM5(x) \ + (RV_X(x, 20, 5) | (RV_IMM_SIGN_N(x, 20, 5) << 5)) #define ENCODE_ITYPE_IMM(x) \ (RV_X(x, 0, 12) << 20) @@ -183,6 +186,8 @@ static inline unsigned int riscv_insn_length (insn_t insn) (RV_X(x, 0, 5) << 15) #define ENCODE_CV_HWLP_LN(x) \ (RV_X(x, 0, 1) << 7) +#define ENCODE_CV_UIMM5(x) \ + (RV_X(x, 0, 5) << 20) #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x)) #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x)) @@ -475,6 +480,7 @@ enum riscv_insn_class INSN_CLASS_XCVALU, INSN_CLASS_XCVHWLP, INSN_CLASS_XCVMEM, + INSN_CLASS_XCVBI, INSN_CLASS_XTHEADBA, INSN_CLASS_XTHEADBB, INSN_CLASS_XTHEADBS, diff --git a/ld/testsuite/ChangeLog.COREV b/ld/testsuite/ChangeLog.COREV index 16573a88b27..7bc7fc62068 100644 --- a/ld/testsuite/ChangeLog.COREV +++ b/ld/testsuite/ChangeLog.COREV @@ -1,3 +1,21 @@ +2021-08-23 Lin Sinan + + * ld-riscv-elf/cv-bi-beqimm.d: Remove hard coded address. + * ld-riscv-elf/cv-bi-bneimm.d: Likewise. + * ld-riscv-elf/cv-hwlp-starti.d: Likewise. + * ld-riscv-elf/cv-hwlp-endi.d: Likewise. + * ld-riscv-elf/cv-hwlp-setupi.d: Likewise. + * ld-riscv-elf/cv-hwlp-setup.d: Likewise. + +2021-08-10 Nazareno Bruschi + + * ld-riscv-elf/cv-bi-beqimm.d: Add new test. + * ld-riscv-elf/cv-bi-beqimm.s: Likewise. + * ld-riscv-elf/cv-bi-bneimm.d: Likewise. + * ld-riscv-elf/cv-bi-bneimm.s: Likewise. + * ld-riscv-elf/ld-riscv-elf.exp: Add CORE-V immediate + branching tests. + 2021-08-23 Jessica Mills * ld-riscv-elf/ld-riscv-elf.exp: Renamed CORE-V hwlp tests to match diff --git a/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d b/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d new file mode 100644 index 00000000000..b50d3846c1c --- /dev/null +++ b/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d @@ -0,0 +1,21 @@ +#name: beqimm relocation +#source: cv-bi-beqimm.s +#as: -march=rv32i_xcvbi +#ld: -melf32lriscv +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +.* : +.*:[[:space:]]+00008067[[:space:]]+ret + +.* <_start>: +.*:[[:space:]]+0102e40b[[:space:]]+cv.beqimm[[:space:]]+t0,-16,.*[[:space:]]+ +.*:[[:space:]]+ff9ff0ef[[:space:]]+jal[[:space:]]+10074[[:space:]]+ + +.* : +.*:[[:space:]]+00000013[[:space:]]+nop +#pass diff --git a/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s b/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s new file mode 100644 index 00000000000..88a6b293e69 --- /dev/null +++ b/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s @@ -0,0 +1,11 @@ + .option nopic + .text + .align 1 + .globl _start + .type _start, @function + +func: ret +_start: + cv.beqimm t0, -16, L2 + call func +L2: nop diff --git a/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d b/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d new file mode 100644 index 00000000000..52231a14b71 --- /dev/null +++ b/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d @@ -0,0 +1,21 @@ +#name: bneimm relocation +#source: cv-bi-bneimm.s +#as: -march=rv32i_xcvbi +#ld: -melf32lriscv +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +.* : +.*:[[:space:]]+00008067[[:space:]]+ret + +.* <_start>: +.*:[[:space:]]+0102f40b[[:space:]]+cv.bneimm[[:space:]]+t0,-16,.*[[:space:]]+ +.*:[[:space:]]+ff9ff0ef[[:space:]]+jal[[:space:]]+10074[[:space:]]+ + +.* : +.*:[[:space:]]+00000013[[:space:]]+nop +#pass diff --git a/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s b/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s new file mode 100644 index 00000000000..0f514f02e1b --- /dev/null +++ b/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s @@ -0,0 +1,11 @@ + .option nopic + .text + .align 1 + .globl _start + .type _start, @function + +func: ret +_start: + cv.bneimm t0, -16, L2 + call func +L2: nop diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp index 5d44226da29..42522656977 100644 --- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp +++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp @@ -182,6 +182,8 @@ if [istarget "riscv*-*-*"] { run_dump_test "cv-hwlp-starti-fail" run_dump_test "cv-hwlp-setupi-2" run_dump_test "cv-hwlp-starti-2" + run_dump_test "cv-bi-bneimm" + run_dump_test "cv-bi-beqimm" run_ld_link_tests [list \ [list "Weak reference 32" "-T weakref.ld -m[riscv_choose_ilp32_emul]" "" \ "-march=rv32i -mabi=ilp32" {weakref32.s} \ diff --git a/opcodes/ChangeLog.COREV b/opcodes/ChangeLog.COREV index 47e82f3e933..9aa05a368ab 100644 --- a/opcodes/ChangeLog.COREV +++ b/opcodes/ChangeLog.COREV @@ -1,3 +1,10 @@ +2021-08-10 Nazareno Bruschi + + * riscv-dis.c (print_insn_args): Add immediate branching + operand. + * riscv-opc.c (riscv_opcodes): Add immediate branching + opcodes. + 2021-08-06 Enrico Tabanelli * riscv-dis.c (print_insn_args): Add post-increment symbol. diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index c0aa6dd468e..67d66e7132e 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -451,6 +451,12 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info (*info->print_address_func) (info->target, info); break; } + else if (oparg[1] == '4') + { + print (info->stream, dis_style_immediate, "%d", ((int) EXTRACT_CV_BI_IMM5 (l))); + ++oparg; + break; + } /* Fall through. */ case 's': if ((l & MASK_JALR) == MATCH_JALR) diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 723e85d34cb..5d27522907d 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2274,6 +2274,10 @@ const struct riscv_opcode riscv_opcodes[] = {"cv.sw", 0, INSN_CLASS_XCVMEM, "t,d(s)", MATCH_CV_SWRR, MASK_CV_SRR, match_opcode, 0}, {"cv.sw", 0, INSN_CLASS_XCVMEM, "t,(s),d", MATCH_CV_SWRRPOST, MASK_CV_SRRPOST, match_opcode, 0}, +/* Immediate branching */ +{"cv.beqimm", 0, INSN_CLASS_XCVBI, "s,b4,p", MATCH_CV_BEQIMM, MASK_CV_BEQIMM, match_opcode, 0}, +{"cv.bneimm", 0, INSN_CLASS_XCVBI, "s,b4,p", MATCH_CV_BNEIMM, MASK_CV_BNEIMM, match_opcode, 0}, + /* Terminate the list. */ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} };