From 45c03b710b82816b3ef445296f78394f3f825c00 Mon Sep 17 00:00:00 2001 From: Evgeny Ukhanov Date: Thu, 27 Feb 2020 02:29:21 +0200 Subject: [PATCH 01/15] Added AMO test asm --- Tests/asm/Makefile | 4 ++-- Tests/asm/src/amo.add.S | 15 +++++++++++++++ Tests/asm/src/mem.S | 6 ++++++ 3 files changed, 23 insertions(+), 2 deletions(-) create mode 100644 Tests/asm/src/amo.add.S diff --git a/Tests/asm/Makefile b/Tests/asm/Makefile index 1e1369e..8d0aab2 100644 --- a/Tests/asm/Makefile +++ b/Tests/asm/Makefile @@ -9,8 +9,8 @@ ELF=$(addprefix build/,$(TESTS)) ELF32=$(addsuffix 32,$(ELF)) ELF64=$(addsuffix 64,$(ELF)) -RISCVCC64=riscv64-unknown-elf-gcc -march=rv64im -mabi=lp64 -static -nostdlib -nostartfiles -mcmodel=medany -RISCVCC32=riscv32-unknown-elf-gcc -march=rv32im -mabi=ilp32 -static -nostdlib -nostartfiles -mcmodel=medany +RISCVCC64=riscv64-unknown-elf-gcc -march=rv64ima -mabi=lp64 -static -nostdlib -nostartfiles -mcmodel=medany +RISCVCC32=riscv32-unknown-elf-gcc -march=rv32ima -mabi=ilp32 -static -nostdlib -nostartfiles -mcmodel=medany build32: $(ELF32) diff --git a/Tests/asm/src/amo.add.S b/Tests/asm/src/amo.add.S new file mode 100644 index 0000000..743af76 --- /dev/null +++ b/Tests/asm/src/amo.add.S @@ -0,0 +1,15 @@ +.section ".text" + .globl main +main: + li a0, 0xffffffff80000000 + li a1, 0xfffffffffffff800 + la a3, amo_operand + sw a0, 0(a3) + amoadd.w a4, a1, 0(a3) + ret + + .data + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/Tests/asm/src/mem.S b/Tests/asm/src/mem.S index 0ef8c1d..03c12e3 100644 --- a/Tests/asm/src/mem.S +++ b/Tests/asm/src/mem.S @@ -27,6 +27,12 @@ main: sh x3, -10(x2) sw x3, 10(x2) sw x3, -10(x2) + + auipc a3,0x1 + addi a3,a3,-8 + sw a0, 10(a3) + addi a1,a1,-8 + #ifdef x64 sd x3, 10(x2) sd x3, -10(x2) From a3cf72c6fbe6926e1a1d757ea118c0d9f90af86b Mon Sep 17 00:00:00 2001 From: Evgeny Ukhanov Date: Tue, 3 Mar 2020 01:29:53 +0200 Subject: [PATCH 02/15] Debug AMO.ADD --- ExecuteA.fs | 10 ++++++++- ExecuteI.fs | 2 +- Tests/Tests.fsproj | 2 ++ Tests/asm/src/amo.add.S | 8 ++++---- Tests/rv32a/amo.fs | 45 +++++++++++++++++++++++++++++++++++++++++ 5 files changed, 61 insertions(+), 6 deletions(-) create mode 100644 Tests/rv32a/amo.fs diff --git a/ExecuteA.fs b/ExecuteA.fs index dcb9b8f..4b4eca6 100644 --- a/ExecuteA.fs +++ b/ExecuteA.fs @@ -50,12 +50,20 @@ let execAMOADD_W (rd : Register) (rs1 : Register) (rs2 : Register) (mstate : Mac let addr = mstate.getRegister rs1 let rs2Val = mstate.getRegister rs2 + printf "AMOADD_W:\nrs1: %d[%X]\nrs2: %d[%x]\n\n" rs1 addr rs2 rs2Val + + printfn "mstate.Memory: %A\n" mstate.Memory + let memResult = loadWord mstate.Memory addr + printfn "memResult: %A" memResult if memResult.IsNone then mstate.setRunState (Trap (MemAddress addr)) - else + else let resMemOp = (int64 memResult.Value) + rs2Val + printf "MemValue: %x + %x\nresMemOp: %X\n" (int64 memResult.Value) rs2Val resMemOp let mstate = mstate.storeMemoryWord addr resMemOp + printf "storeMemoryWord: %X[%X]" addr resMemOp + printf "RD: %d[%x]" rd (int64 memResult.Value) let mstate = mstate.setRegister rd (int64 memResult.Value) mstate.incPC diff --git a/ExecuteI.fs b/ExecuteI.fs index a6f2fea..eaf93c7 100644 --- a/ExecuteI.fs +++ b/ExecuteI.fs @@ -197,7 +197,7 @@ let execSH (rs1 : Register) (rs2 : Register) (imm12 : InstrField) (mstate : Mach let execSW (rs1 : Register) (rs2 : Register) (imm12 : InstrField) (mstate : MachineState) = let addr = (mstate.getRegister rs1) + int64 imm12 let rs2Val = mstate.getRegister rs2 - let mstate = mstate.storeMemoryWord addr rs2Val + let mstate = mstate.storeMemoryWord addr rs2Val mstate.incPC //================================================= diff --git a/Tests/Tests.fsproj b/Tests/Tests.fsproj index 13b9861..5eb4001 100644 --- a/Tests/Tests.fsproj +++ b/Tests/Tests.fsproj @@ -37,6 +37,8 @@ + + diff --git a/Tests/asm/src/amo.add.S b/Tests/asm/src/amo.add.S index 743af76..4684ec8 100644 --- a/Tests/asm/src/amo.add.S +++ b/Tests/asm/src/amo.add.S @@ -8,8 +8,8 @@ main: amoadd.w a4, a1, 0(a3) ret - .data - .bss - .align 3 +.data + .bss + .align 3 amo_operand: - .dword 0 + .dword 0 diff --git a/Tests/rv32a/amo.fs b/Tests/rv32a/amo.fs new file mode 100644 index 0000000..c6174a3 --- /dev/null +++ b/Tests/rv32a/amo.fs @@ -0,0 +1,45 @@ +module Tests.rv32a.amo + +open Xunit + +open ISA.RISCV +open ISA.RISCV.Arch + +//=============================================== +// ALU tests +let ALU (instrs: InstrField array) = + // Init MachineState + let addr = 0x80000000L + let mstate = MachineState.InitMachineState Map.empty RV64ia true + let mstate = mstate.setPC addr + + let m = Array.fold (fun m i -> + let executor = Decoder.Decode m i + Assert.NotEqual(executor, None) + let m = executor.Value m + Assert.True(mstate.PC < m.PC) + m + ) mstate instrs + Array.fold (fun _ r -> printf "%X " r) () m.Registers + let a0 = m.getRegister 10 + Assert.Equal(a0, 0xffffffff80000000L) + let a1 = m.getRegister 11 + Assert.Equal(a1, 0xfffffffffffff800L) + let a3 = m.getRegister 13 + Assert.Equal(a3, 0X80001000L) + let a4 = m.getRegister 14 + Assert.Equal(a4, 0XFFFFFFFF80000000L) + + +[] +[] +let ``AMO.ADD`` () = + ALU [| + 0x80000537 + 0x80000593 + 0x00001697 + 0xff868693 + 0x00a6a023 + 0x00b6a72f + |] + \ No newline at end of file From 5a82fba0ced5ba39ad75302bf4e4bb6d4e3abd76 Mon Sep 17 00:00:00 2001 From: Evgeny Ukhanov Date: Tue, 3 Mar 2020 11:50:09 +0200 Subject: [PATCH 03/15] Changed AMO.ADD tests and AMO ALU tester --- ExecuteA.fs | 8 -------- Tests/Tests.fsproj | 2 +- Tests/asm/src/amo.add.S | 9 ++++++++- Tests/{rv32a => rv64a}/amo.fs | 16 ++++++++++------ 4 files changed, 19 insertions(+), 16 deletions(-) rename Tests/{rv32a => rv64a}/amo.fs (72%) diff --git a/ExecuteA.fs b/ExecuteA.fs index 4b4eca6..0e6c78d 100644 --- a/ExecuteA.fs +++ b/ExecuteA.fs @@ -50,20 +50,12 @@ let execAMOADD_W (rd : Register) (rs1 : Register) (rs2 : Register) (mstate : Mac let addr = mstate.getRegister rs1 let rs2Val = mstate.getRegister rs2 - printf "AMOADD_W:\nrs1: %d[%X]\nrs2: %d[%x]\n\n" rs1 addr rs2 rs2Val - - printfn "mstate.Memory: %A\n" mstate.Memory - let memResult = loadWord mstate.Memory addr - printfn "memResult: %A" memResult if memResult.IsNone then mstate.setRunState (Trap (MemAddress addr)) else let resMemOp = (int64 memResult.Value) + rs2Val - printf "MemValue: %x + %x\nresMemOp: %X\n" (int64 memResult.Value) rs2Val resMemOp let mstate = mstate.storeMemoryWord addr resMemOp - printf "storeMemoryWord: %X[%X]" addr resMemOp - printf "RD: %d[%x]" rd (int64 memResult.Value) let mstate = mstate.setRegister rd (int64 memResult.Value) mstate.incPC diff --git a/Tests/Tests.fsproj b/Tests/Tests.fsproj index 5eb4001..28c6b25 100644 --- a/Tests/Tests.fsproj +++ b/Tests/Tests.fsproj @@ -37,7 +37,7 @@ - + diff --git a/Tests/asm/src/amo.add.S b/Tests/asm/src/amo.add.S index 4684ec8..3dcc8b6 100644 --- a/Tests/asm/src/amo.add.S +++ b/Tests/asm/src/amo.add.S @@ -5,7 +5,14 @@ main: li a1, 0xfffffffffffff800 la a3, amo_operand sw a0, 0(a3) - amoadd.w a4, a1, 0(a3) + amoadd.w a4, a1, 0(a3); a4 = 0xffffffff80000000 + lw a5, 0(a3); a5 = 0x000000007ffff800 + + # try again after a cache miss + li a1, 0xffffffff80000000 + amoadd.w a6, a1, 0(a3); a6 = 0x000000007ffff800 + lw a7, 0(a3); a7 = 0xfffffffffffff800 + ret .data diff --git a/Tests/rv32a/amo.fs b/Tests/rv64a/amo.fs similarity index 72% rename from Tests/rv32a/amo.fs rename to Tests/rv64a/amo.fs index c6174a3..16c5479 100644 --- a/Tests/rv32a/amo.fs +++ b/Tests/rv64a/amo.fs @@ -4,6 +4,7 @@ open Xunit open ISA.RISCV open ISA.RISCV.Arch +open ISA.RISCV.MachineState //=============================================== // ALU tests @@ -12,19 +13,19 @@ let ALU (instrs: InstrField array) = let addr = 0x80000000L let mstate = MachineState.InitMachineState Map.empty RV64ia true let mstate = mstate.setPC addr + let mstate = mstate.setRunState RunMachineState.Run - let m = Array.fold (fun m i -> + let m = Array.fold (fun (m : MachineState) i -> + let pc = m.PC let executor = Decoder.Decode m i Assert.NotEqual(executor, None) let m = executor.Value m - Assert.True(mstate.PC < m.PC) + Assert.Equal(m.RunState, RunMachineState.Run) + Assert.Equal(pc + 4L, m.PC) m ) mstate instrs - Array.fold (fun _ r -> printf "%X " r) () m.Registers let a0 = m.getRegister 10 Assert.Equal(a0, 0xffffffff80000000L) - let a1 = m.getRegister 11 - Assert.Equal(a1, 0xfffffffffffff800L) let a3 = m.getRegister 13 Assert.Equal(a3, 0X80001000L) let a4 = m.getRegister 14 @@ -41,5 +42,8 @@ let ``AMO.ADD`` () = 0xff868693 0x00a6a023 0x00b6a72f + 0x0006a783 + 0x800005b7 + 0x00b6a82f + 0x0006a883 |] - \ No newline at end of file From ce99304fcd43784b87ae4c93834ada1444504302 Mon Sep 17 00:00:00 2001 From: Evgeny Ukhanov Date: Sun, 8 Mar 2020 23:28:05 +0200 Subject: [PATCH 04/15] Changed AMO.ADD tests --- Tests/rv32m/alu.fs | 24 ++++++++++++------------ Tests/rv64a/amo.fs | 46 +++++++++++++++++++++++++--------------------- 2 files changed, 37 insertions(+), 33 deletions(-) diff --git a/Tests/rv32m/alu.fs b/Tests/rv32m/alu.fs index 778f298..ddb892c 100644 --- a/Tests/rv32m/alu.fs +++ b/Tests/rv32m/alu.fs @@ -57,18 +57,18 @@ let ALU instr x1 x2 x3 = let ``MUL: x3 = x2 * x1`` ( x3, x1, x2) = ALU 0x021101b3 x1 x2 x3 -//[] -//[] -//[] -//[] -//[] -//[] -//[] -//[] -//[] -//[] -//[] -//[] +[] +[] +[] +[] +[] +[] +[] +[] +[] +[] +[] +[] let ``MULH: x3 = half (x2 * x1)`` (x3, x1, x2) = ALU 0x021111b3 x1 x2 x3 diff --git a/Tests/rv64a/amo.fs b/Tests/rv64a/amo.fs index 16c5479..a5c49fc 100644 --- a/Tests/rv64a/amo.fs +++ b/Tests/rv64a/amo.fs @@ -8,7 +8,7 @@ open ISA.RISCV.MachineState //=============================================== // ALU tests -let ALU (instrs: InstrField array) = +let ALU (instrs: InstrField array) (a4 : int64) (a5 : int64) (a6 : int64) (a7 : int64)= // Init MachineState let addr = 0x80000000L let mstate = MachineState.InitMachineState Map.empty RV64ia true @@ -24,26 +24,30 @@ let ALU (instrs: InstrField array) = Assert.Equal(pc + 4L, m.PC) m ) mstate instrs - let a0 = m.getRegister 10 - Assert.Equal(a0, 0xffffffff80000000L) - let a3 = m.getRegister 13 - Assert.Equal(a3, 0X80001000L) - let a4 = m.getRegister 14 - Assert.Equal(a4, 0XFFFFFFFF80000000L) + let x14 = m.getRegister 14 + let x15 = m.getRegister 15 + let x16 = m.getRegister 16 + let x17 = m.getRegister 17 + + Assert.Equal(x14, a4) + Assert.Equal(x15, a5) + Assert.Equal(x16, a6) + Assert.Equal(x17, a7) [] -[] -let ``AMO.ADD`` () = - ALU [| - 0x80000537 - 0x80000593 - 0x00001697 - 0xff868693 - 0x00a6a023 - 0x00b6a72f - 0x0006a783 - 0x800005b7 - 0x00b6a82f - 0x0006a883 - |] +[] +let ``AMO.ADD`` (a4, a5, a6, a7) = + let instrSet = [| + 0x80000537 + 0x80000593 + 0x00001697 + 0xff868693 + 0x00a6a023 + 0x00b6a72f + 0x0006a783 + 0x800005b7 + 0x00b6a82f + 0x0006a883 + |] + ALU instrSet a4 a5 From 35d8c8e0cf6c7cf223dde28993770ede63062e62 Mon Sep 17 00:00:00 2001 From: Evgeny Ukhanov Date: Mon, 9 Mar 2020 13:28:28 +0200 Subject: [PATCH 05/15] Extend AMO assembler tests --- Tests/asm/src/amo.add.S | 22 -------------------- Tests/asm/src/amo.add_w.S | 42 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 22 deletions(-) delete mode 100644 Tests/asm/src/amo.add.S create mode 100644 Tests/asm/src/amo.add_w.S diff --git a/Tests/asm/src/amo.add.S b/Tests/asm/src/amo.add.S deleted file mode 100644 index 3dcc8b6..0000000 --- a/Tests/asm/src/amo.add.S +++ /dev/null @@ -1,22 +0,0 @@ -.section ".text" - .globl main -main: - li a0, 0xffffffff80000000 - li a1, 0xfffffffffffff800 - la a3, amo_operand - sw a0, 0(a3) - amoadd.w a4, a1, 0(a3); a4 = 0xffffffff80000000 - lw a5, 0(a3); a5 = 0x000000007ffff800 - - # try again after a cache miss - li a1, 0xffffffff80000000 - amoadd.w a6, a1, 0(a3); a6 = 0x000000007ffff800 - lw a7, 0(a3); a7 = 0xfffffffffffff800 - - ret - -.data - .bss - .align 3 -amo_operand: - .dword 0 diff --git a/Tests/asm/src/amo.add_w.S b/Tests/asm/src/amo.add_w.S new file mode 100644 index 0000000..ddd3e1d --- /dev/null +++ b/Tests/asm/src/amo.add_w.S @@ -0,0 +1,42 @@ +.section ".text" + .globl main +main: + li a0, 0xffffffff80000000 + li a1, 0xfffffffffffff800 + la a3, amo_operand + sw a0, 0(a3) + amoadd.w a4, a1, 0(a3); a4 = 0xffffffff80000000 + lw a5, 0(a3); a5 = 0x000000007ffff800 + + # try again after a cache miss + li a2, 0xffffffff80000000 + amoadd.w a6, a2, 0(a3); a6 = 0x000000007ffff800 + lw a7, 0(a3); a7 = 0xfffffffffffff800 + + #=================================== + # AMO.AND.W + amoand.w a4, a1, 0(a3); a4 = 0xffffffff80000000 + lw a5, 0(a3); a5 = 0xffffffff80000000 + + # try again after a cache miss + li a2, 0x0000000080000000 + amoand.w a6, a2, 0(a3); a6 = 0xffffffff80000000 + lw a7, 0(a3); a7 = 0xffffffff80000000 + + #=================================== + # AMO.MAX.W + amomax.w a4, a1, 0(a3); a4 = 0xffffffff80000000 + lw a5, 0(a3); a5 = 0xfffffffffffff800 + + li a2, 1 + sw x0, 0(a3) + amomax.w a6, a2, 0(a3); a6 = 0 + lw a7, 0(a3); a7 = 1 + + ret + +.data + .bss + .align 3 +amo_operand: + .dword 0 From dcf1c044be9e5c5d5e4a4ec4f8b1fe5a8d938b9d Mon Sep 17 00:00:00 2001 From: Evgeny Ukhanov Date: Tue, 28 Apr 2020 20:55:11 +0300 Subject: [PATCH 06/15] AMO: added Asm test sources --- DecodeA.fs | 2 + Decoder.fs | 2 + Tests/asm/asm-source-tests/rv64ua/Makefrag | 13 +++ Tests/asm/asm-source-tests/rv64ua/amoadd_d.S | 47 ++++++++ Tests/asm/asm-source-tests/rv64ua/amoadd_w.S | 48 ++++++++ Tests/asm/asm-source-tests/rv64ua/amoand_d.S | 48 ++++++++ Tests/asm/asm-source-tests/rv64ua/amoand_w.S | 48 ++++++++ Tests/asm/asm-source-tests/rv64ua/amomax_d.S | 48 ++++++++ Tests/asm/asm-source-tests/rv64ua/amomax_w.S | 48 ++++++++ Tests/asm/asm-source-tests/rv64ua/amomaxu_d.S | 48 ++++++++ Tests/asm/asm-source-tests/rv64ua/amomaxu_w.S | 48 ++++++++ Tests/asm/asm-source-tests/rv64ua/amomin_d.S | 48 ++++++++ Tests/asm/asm-source-tests/rv64ua/amomin_w.S | 48 ++++++++ Tests/asm/asm-source-tests/rv64ua/amominu_d.S | 49 ++++++++ Tests/asm/asm-source-tests/rv64ua/amominu_w.S | 49 ++++++++ Tests/asm/asm-source-tests/rv64ua/amoor_d.S | 48 ++++++++ Tests/asm/asm-source-tests/rv64ua/amoor_w.S | 48 ++++++++ Tests/asm/asm-source-tests/rv64ua/amoswap_d.S | 48 ++++++++ Tests/asm/asm-source-tests/rv64ua/amoswap_w.S | 48 ++++++++ Tests/asm/asm-source-tests/rv64ua/amoxor_d.S | 48 ++++++++ Tests/asm/asm-source-tests/rv64ua/amoxor_w.S | 48 ++++++++ Tests/asm/asm-source-tests/rv64ua/lrsc.S | 102 +++++++++++++++++ Tests/asm/disasm | 93 ++++++++++++++++ Tests/asm/src/amo.add_w.S | 42 ------- Tests/asm/src/amo.lrsc.w.S | 36 ++++++ Tests/asm/src/amo_w.S | 105 ++++++++++++++++++ Tests/rv64a/amo.fs | 28 ++++- 27 files changed, 1244 insertions(+), 44 deletions(-) create mode 100644 Tests/asm/asm-source-tests/rv64ua/Makefrag create mode 100644 Tests/asm/asm-source-tests/rv64ua/amoadd_d.S create mode 100644 Tests/asm/asm-source-tests/rv64ua/amoadd_w.S create mode 100644 Tests/asm/asm-source-tests/rv64ua/amoand_d.S create mode 100644 Tests/asm/asm-source-tests/rv64ua/amoand_w.S create mode 100644 Tests/asm/asm-source-tests/rv64ua/amomax_d.S create mode 100644 Tests/asm/asm-source-tests/rv64ua/amomax_w.S create mode 100644 Tests/asm/asm-source-tests/rv64ua/amomaxu_d.S create mode 100644 Tests/asm/asm-source-tests/rv64ua/amomaxu_w.S create mode 100644 Tests/asm/asm-source-tests/rv64ua/amomin_d.S create mode 100644 Tests/asm/asm-source-tests/rv64ua/amomin_w.S create mode 100644 Tests/asm/asm-source-tests/rv64ua/amominu_d.S create mode 100644 Tests/asm/asm-source-tests/rv64ua/amominu_w.S create mode 100644 Tests/asm/asm-source-tests/rv64ua/amoor_d.S create mode 100644 Tests/asm/asm-source-tests/rv64ua/amoor_w.S create mode 100644 Tests/asm/asm-source-tests/rv64ua/amoswap_d.S create mode 100644 Tests/asm/asm-source-tests/rv64ua/amoswap_w.S create mode 100644 Tests/asm/asm-source-tests/rv64ua/amoxor_d.S create mode 100644 Tests/asm/asm-source-tests/rv64ua/amoxor_w.S create mode 100644 Tests/asm/asm-source-tests/rv64ua/lrsc.S create mode 100644 Tests/asm/disasm delete mode 100644 Tests/asm/src/amo.add_w.S create mode 100644 Tests/asm/src/amo.lrsc.w.S create mode 100644 Tests/asm/src/amo_w.S diff --git a/DecodeA.fs b/DecodeA.fs index 3735892..77c5a27 100644 --- a/DecodeA.fs +++ b/DecodeA.fs @@ -37,6 +37,8 @@ let Decode (instr: InstrField) : InstructionA = let rl = instr.bitSlice 25 25 let aq = instr.bitSlice 26 26 + printfn "%X[%X] %X" opcode 0b0101111 funct3 + match (opcode) with | 0b0101111 when funct3 = 0b010 -> match funct7 with diff --git a/Decoder.fs b/Decoder.fs index 27d0038..bbd1761 100644 --- a/Decoder.fs +++ b/Decoder.fs @@ -17,7 +17,9 @@ let Decode (mstate : MachineState) (instr: InstrField) : execFunc option = let decM = M.Decode mstate instr let decM64 = M64.Decode mstate instr let decA = A.Decode instr + printfn "decA: %A" decA let decA64 = A64.Decode instr + printfn "decA64: %A" decA64 // Check is instruction should be executed let execI32 = diff --git a/Tests/asm/asm-source-tests/rv64ua/Makefrag b/Tests/asm/asm-source-tests/rv64ua/Makefrag new file mode 100644 index 0000000..3af8856 --- /dev/null +++ b/Tests/asm/asm-source-tests/rv64ua/Makefrag @@ -0,0 +1,13 @@ +#======================================================================= +# Makefrag for rv64ua tests +#----------------------------------------------------------------------- + +rv64ua_sc_tests = \ + amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoxor_d amoswap_d \ + amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ + lrsc \ + +rv64ua_p_tests = $(addprefix rv64ua-p-, $(rv64ua_sc_tests)) +rv64ua_v_tests = $(addprefix rv64ua-v-, $(rv64ua_sc_tests)) + +spike_tests += $(rv64ua_p_tests) $(rv64ua_v_tests) diff --git a/Tests/asm/asm-source-tests/rv64ua/amoadd_d.S b/Tests/asm/asm-source-tests/rv64ua/amoadd_d.S new file mode 100644 index 0000000..05b2f38 --- /dev/null +++ b/Tests/asm/asm-source-tests/rv64ua/amoadd_d.S @@ -0,0 +1,47 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoadd_d.S +#----------------------------------------------------------------------------- +# +# Test amoadd.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amoadd.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xffffffff7ffff800, \ + amoadd.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff7ffff000, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/Tests/asm/asm-source-tests/rv64ua/amoadd_w.S b/Tests/asm/asm-source-tests/rv64ua/amoadd_w.S new file mode 100644 index 0000000..d076d45 --- /dev/null +++ b/Tests/asm/asm-source-tests/rv64ua/amoadd_w.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoadd_w.S +#----------------------------------------------------------------------------- +# +# Test amoadd.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amoadd.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x000000007ffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x000000007ffff800, \ + li a1, 0xffffffff80000000; \ + amoadd.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/Tests/asm/asm-source-tests/rv64ua/amoand_d.S b/Tests/asm/asm-source-tests/rv64ua/amoand_d.S new file mode 100644 index 0000000..c1148c0 --- /dev/null +++ b/Tests/asm/asm-source-tests/rv64ua/amoand_d.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoand_d.S +#----------------------------------------------------------------------------- +# +# Test amoand.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amoand.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xffffffff80000000, \ + li a1, 0x0000000080000000; \ + amoand.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/Tests/asm/asm-source-tests/rv64ua/amoand_w.S b/Tests/asm/asm-source-tests/rv64ua/amoand_w.S new file mode 100644 index 0000000..7fe3bd0 --- /dev/null +++ b/Tests/asm/asm-source-tests/rv64ua/amoand_w.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoand.w.S +#----------------------------------------------------------------------------- +# +# Test amoand.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amoand.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xffffffff80000000, \ + li a1, 0x0000000080000000; \ + amoand.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/Tests/asm/asm-source-tests/rv64ua/amomax_d.S b/Tests/asm/asm-source-tests/rv64ua/amomax_d.S new file mode 100644 index 0000000..b7f8703 --- /dev/null +++ b/Tests/asm/asm-source-tests/rv64ua/amomax_d.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomax_d.S +#----------------------------------------------------------------------------- +# +# Test amomax.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amomax.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 1; \ + sd x0, 0(a3); \ + amomax.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 1, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/Tests/asm/asm-source-tests/rv64ua/amomax_w.S b/Tests/asm/asm-source-tests/rv64ua/amomax_w.S new file mode 100644 index 0000000..f986205 --- /dev/null +++ b/Tests/asm/asm-source-tests/rv64ua/amomax_w.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomax_d.S +#----------------------------------------------------------------------------- +# +# Test amomax.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 1; \ + sw x0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 1, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/Tests/asm/asm-source-tests/rv64ua/amomaxu_d.S b/Tests/asm/asm-source-tests/rv64ua/amomaxu_d.S new file mode 100644 index 0000000..227ac4c --- /dev/null +++ b/Tests/asm/asm-source-tests/rv64ua/amomaxu_d.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomaxu_d.S +#----------------------------------------------------------------------------- +# +# Test amomaxu.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amomaxu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sd x0, 0(a3); \ + amomaxu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/Tests/asm/asm-source-tests/rv64ua/amomaxu_w.S b/Tests/asm/asm-source-tests/rv64ua/amomaxu_w.S new file mode 100644 index 0000000..eb27d07 --- /dev/null +++ b/Tests/asm/asm-source-tests/rv64ua/amomaxu_w.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomaxu_d.S +#----------------------------------------------------------------------------- +# +# Test amomaxu.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sw x0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/Tests/asm/asm-source-tests/rv64ua/amomin_d.S b/Tests/asm/asm-source-tests/rv64ua/amomin_d.S new file mode 100644 index 0000000..ee6bbf3 --- /dev/null +++ b/Tests/asm/asm-source-tests/rv64ua/amomin_d.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomin_d.S +#----------------------------------------------------------------------------- +# +# Test amomin.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amomin.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sd x0, 0(a3); \ + amomin.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/Tests/asm/asm-source-tests/rv64ua/amomin_w.S b/Tests/asm/asm-source-tests/rv64ua/amomin_w.S new file mode 100644 index 0000000..1337d2c --- /dev/null +++ b/Tests/asm/asm-source-tests/rv64ua/amomin_w.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomin_d.S +#----------------------------------------------------------------------------- +# +# Test amomin.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sw x0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/Tests/asm/asm-source-tests/rv64ua/amominu_d.S b/Tests/asm/asm-source-tests/rv64ua/amominu_d.S new file mode 100644 index 0000000..08bfb5b --- /dev/null +++ b/Tests/asm/asm-source-tests/rv64ua/amominu_d.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amominu_d.S +#----------------------------------------------------------------------------- +# +# Test amominu.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amominu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sd x0, 0(a3); \ + amominu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + diff --git a/Tests/asm/asm-source-tests/rv64ua/amominu_w.S b/Tests/asm/asm-source-tests/rv64ua/amominu_w.S new file mode 100644 index 0000000..f45f856 --- /dev/null +++ b/Tests/asm/asm-source-tests/rv64ua/amominu_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amominu_d.S +#----------------------------------------------------------------------------- +# +# Test amominu.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sw x0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + diff --git a/Tests/asm/asm-source-tests/rv64ua/amoor_d.S b/Tests/asm/asm-source-tests/rv64ua/amoor_d.S new file mode 100644 index 0000000..6f71495 --- /dev/null +++ b/Tests/asm/asm-source-tests/rv64ua/amoor_d.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoor_d.S +#----------------------------------------------------------------------------- +# +# Test amoor.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amoor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 1; \ + amoor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffffffffffff801, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/Tests/asm/asm-source-tests/rv64ua/amoor_w.S b/Tests/asm/asm-source-tests/rv64ua/amoor_w.S new file mode 100644 index 0000000..e64b8c2 --- /dev/null +++ b/Tests/asm/asm-source-tests/rv64ua/amoor_w.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoor.w.S +#----------------------------------------------------------------------------- +# +# Test amoor.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amoor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 1; \ + amoor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffffffffffff801, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/Tests/asm/asm-source-tests/rv64ua/amoswap_d.S b/Tests/asm/asm-source-tests/rv64ua/amoswap_d.S new file mode 100644 index 0000000..6b07d74 --- /dev/null +++ b/Tests/asm/asm-source-tests/rv64ua/amoswap_d.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoswap.d.S +#----------------------------------------------------------------------------- +# +# Test amoswap.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amoswap.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 0x0000000080000000; \ + amoswap.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/Tests/asm/asm-source-tests/rv64ua/amoswap_w.S b/Tests/asm/asm-source-tests/rv64ua/amoswap_w.S new file mode 100644 index 0000000..c4276dc --- /dev/null +++ b/Tests/asm/asm-source-tests/rv64ua/amoswap_w.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoswap_w.S +#----------------------------------------------------------------------------- +# +# Test amoswap.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amoswap.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 0x0000000080000000; \ + amoswap.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/Tests/asm/asm-source-tests/rv64ua/amoxor_d.S b/Tests/asm/asm-source-tests/rv64ua/amoxor_d.S new file mode 100644 index 0000000..8305434 --- /dev/null +++ b/Tests/asm/asm-source-tests/rv64ua/amoxor_d.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoxor_d.S +#----------------------------------------------------------------------------- +# +# Test amoxor.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amoxor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x000000007ffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x000000007ffff800, \ + li a1, 1; \ + amoxor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x000000007ffff801, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/Tests/asm/asm-source-tests/rv64ua/amoxor_w.S b/Tests/asm/asm-source-tests/rv64ua/amoxor_w.S new file mode 100644 index 0000000..1b6fc48 --- /dev/null +++ b/Tests/asm/asm-source-tests/rv64ua/amoxor_w.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoxor_w.S +#----------------------------------------------------------------------------- +# +# Test amoxor.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amoxor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x7ffff800, \ + li a1, 0xc0000001; \ + amoxor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffbffff801, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/Tests/asm/asm-source-tests/rv64ua/lrsc.S b/Tests/asm/asm-source-tests/rv64ua/lrsc.S new file mode 100644 index 0000000..c7589d7 --- /dev/null +++ b/Tests/asm/asm-source-tests/rv64ua/lrsc.S @@ -0,0 +1,102 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lrsr.S +#----------------------------------------------------------------------------- +# +# Test LR/SC instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + +# get a unique core id +la a0, coreid +li a1, 1 +amoadd.w a2, a1, (a0) + +# for now, only run this on core 0 +1:li a3, 1 +bgeu a2, a3, 1b + +1: lw a1, (a0) +bltu a1, a3, 1b + +# make sure that sc without a reservation fails. +TEST_CASE( 2, a4, 1, \ + la a0, foo; \ + li a5, 0xdeadbeef; \ + sc.w a4, a5, (a0); \ +) + +# make sure the failing sc did not commit into memory +TEST_CASE( 3, a4, 0, \ + lw a4, foo; \ +) + +# make sure that sc with the wrong reservation fails. +# TODO is this actually mandatory behavior? +TEST_CASE( 4, a4, 1, \ + la a0, foo; \ + la a1, fooTest3; \ + lr.w a1, (a1); \ + sc.w a4, a1, (a0); \ +) + +#define LOG_ITERATIONS 10 + +# have each core add its coreid+1 to foo 1024 times +la a0, foo +li a1, 1<: +80000000: 000010ef jal ra,80001000
+80000004: 0000006f j 80000004 <_start+0x4> + +Disassembly of section .text: + +80001000
: +80001000: 80000537 lui a0,0x80000 +80001004: 80000593 li a1,-2048 +80001008: 00001697 auipc a3,0x1 +8000100c: ff868693 addi a3,a3,-8 # 80002000 +80001010: 00a6a023 sw a0,0(a3) +80001014: 00b6a72f amoadd.w a4,a1,(a3) +80001018: 0006a783 lw a5,0(a3) +8000101c: 80000637 lui a2,0x80000 +80001020: 00c6a82f amoadd.w a6,a2,(a3) +80001024: 0006a883 lw a7,0(a3) +80001028: 60b6a72f amoand.w a4,a1,(a3) +8000102c: 0006a783 lw a5,0(a3) +80001030: 80000637 lui a2,0x80000 +80001034: 60c6a82f amoand.w a6,a2,(a3) +80001038: 0006a883 lw a7,0(a3) +8000103c: 40b6a72f amoor.w a4,a1,(a3) +80001040: 0006a783 lw a5,0(a3) +80001044: 00100613 li a2,1 +80001048: 40c6a82f amoor.w a6,a2,(a3) +8000104c: 0006a883 lw a7,0(a3) +80001050: 20b6a72f amoxor.w a4,a1,(a3) +80001054: 0006a783 lw a5,0(a3) +80001058: c0000637 lui a2,0xc0000 +8000105c: 00160613 addi a2,a2,1 # c0000001 <_end+0x3fffdff9> +80001060: 20c6a82f amoxor.w a6,a2,(a3) +80001064: 0006a883 lw a7,0(a3) +80001068: 08b6a72f amoswap.w a4,a1,(a3) +8000106c: 0006a783 lw a5,0(a3) +80001070: 80000637 lui a2,0x80000 +80001074: 08c6a82f amoswap.w a6,a2,(a3) +80001078: 0006a883 lw a7,0(a3) +8000107c: a0b6a72f amomax.w a4,a1,(a3) +80001080: 0006a783 lw a5,0(a3) +80001084: 00100613 li a2,1 +80001088: 0006a023 sw zero,0(a3) +8000108c: a0c6a82f amomax.w a6,a2,(a3) +80001090: 0006a883 lw a7,0(a3) +80001094: e0b6a72f amomaxu.w a4,a1,(a3) +80001098: 0006a783 lw a5,0(a3) +8000109c: fff00613 li a2,-1 +800010a0: 0006a023 sw zero,0(a3) +800010a4: e0c6a82f amomaxu.w a6,a2,(a3) +800010a8: 0006a883 lw a7,0(a3) +800010ac: 80b6a72f amomin.w a4,a1,(a3) +800010b0: 0006a783 lw a5,0(a3) +800010b4: fff00613 li a2,-1 +800010b8: 0006a023 sw zero,0(a3) +800010bc: 80c6a82f amomin.w a6,a2,(a3) +800010c0: 0006a883 lw a7,0(a3) +800010c4: c0b6a72f amominu.w a4,a1,(a3) +800010c8: 0006a783 lw a5,0(a3) +800010cc: fff00613 li a2,-1 +800010d0: 0006a023 sw zero,0(a3) +800010d4: c0c6a82f amominu.w a6,a2,(a3) +800010d8: 0006a883 lw a7,0(a3) +800010dc: 00008067 ret + +Disassembly of section .bss: + +80002000 : + ... + +Disassembly of section .riscv.attributes: + +00000000 <.riscv.attributes>: + 0: 2341 jal 580 + 2: 0000 unimp + 4: 7200 flw fs0,32(a2) + 6: 7369 lui t1,0xffffa + 8: 01007663 bgeu zero,a6,14 + c: 0019 c.nop 6 + e: 0000 unimp + 10: 7205 lui tp,0xfffe1 + 12: 3376 fld ft6,376(sp) + 14: 6932 flw fs2,12(sp) + 16: 7032 flw ft0,44(sp) + 18: 5f30 lw a2,120(a4) + 1a: 326d jal fffff9c4 <_end+0x7fffd9bc> + 1c: 3070 fld fa2,224(s0) + 1e: 615f 7032 0030 0x307032615f diff --git a/Tests/asm/src/amo.add_w.S b/Tests/asm/src/amo.add_w.S deleted file mode 100644 index ddd3e1d..0000000 --- a/Tests/asm/src/amo.add_w.S +++ /dev/null @@ -1,42 +0,0 @@ -.section ".text" - .globl main -main: - li a0, 0xffffffff80000000 - li a1, 0xfffffffffffff800 - la a3, amo_operand - sw a0, 0(a3) - amoadd.w a4, a1, 0(a3); a4 = 0xffffffff80000000 - lw a5, 0(a3); a5 = 0x000000007ffff800 - - # try again after a cache miss - li a2, 0xffffffff80000000 - amoadd.w a6, a2, 0(a3); a6 = 0x000000007ffff800 - lw a7, 0(a3); a7 = 0xfffffffffffff800 - - #=================================== - # AMO.AND.W - amoand.w a4, a1, 0(a3); a4 = 0xffffffff80000000 - lw a5, 0(a3); a5 = 0xffffffff80000000 - - # try again after a cache miss - li a2, 0x0000000080000000 - amoand.w a6, a2, 0(a3); a6 = 0xffffffff80000000 - lw a7, 0(a3); a7 = 0xffffffff80000000 - - #=================================== - # AMO.MAX.W - amomax.w a4, a1, 0(a3); a4 = 0xffffffff80000000 - lw a5, 0(a3); a5 = 0xfffffffffffff800 - - li a2, 1 - sw x0, 0(a3) - amomax.w a6, a2, 0(a3); a6 = 0 - lw a7, 0(a3); a7 = 1 - - ret - -.data - .bss - .align 3 -amo_operand: - .dword 0 diff --git a/Tests/asm/src/amo.lrsc.w.S b/Tests/asm/src/amo.lrsc.w.S new file mode 100644 index 0000000..4e13357 --- /dev/null +++ b/Tests/asm/src/amo.lrsc.w.S @@ -0,0 +1,36 @@ +.section ".text" + .globl main +#define LOG_ITERATIONS 10 + +main: + la a0, foo + li a5, 0xdeadbeef + sc.w a4, a5, (a0); a4 = 1 + + lw a4, foo; a4 = 0 + + la a0, foo + la a1, fooTest3 + lr.w a1, (a1) + sc.w a4, a1, (a0); a4 = 1 + + lw a0, foo + slli a1, a3, LOG_ITERATIONS-1 +1: sub a0, a0, a1 + addi a3, a3, -1 + bgez a3, 1b; a0 = 0 + + la a0, foo +1: lr.w a1, (a0) + sc.w a1, x0, (a0) + bnez a1, 1b + sc.w a1, x0, (a0); a1 = 1 + + ret + +.data +coreid: .word 0 +barrier: .word 0 +foo: .word 0 +.skip 1024 +fooTest3: .word 0 diff --git a/Tests/asm/src/amo_w.S b/Tests/asm/src/amo_w.S new file mode 100644 index 0000000..68eadc5 --- /dev/null +++ b/Tests/asm/src/amo_w.S @@ -0,0 +1,105 @@ +.section ".text" + .globl main +main: + li a0, 0xffffffff80000000 + li a1, 0xfffffffffffff800 + la a3, amo_operand + sw a0, 0(a3) + + #=================================== + # AMOADD.W + amoadd.w a4, a1, 0(a3); a4 = 0xffffffff80000000 + lw a5, 0(a3); a5 = 0x000000007ffff800 + + # try again after a cache miss + li a2, 0xffffffff80000000 + amoadd.w a6, a2, 0(a3); a6 = 0x000000007ffff800 + lw a7, 0(a3); a7 = 0xfffffffffffff800 + + #=================================== + # AMOAND.W + amoand.w a4, a1, 0(a3); a4 = 0xffffffff80000000 + lw a5, 0(a3); a5 = 0xffffffff80000000 + + # try again after a cache miss + li a2, 0x0000000080000000 + amoand.w a6, a2, 0(a3); a6 = 0xffffffff80000000 + lw a7, 0(a3); a7 = 0xffffffff80000000 + + #=================================== + # AMOOR.W + amoor.w a4, a1, 0(a3); a4 = 0xffffffff80000000 + lw a5, 0(a3); a5 = 0xfffffffffffff800 + + # try again after a cache miss + li a2, 1 + amoor.w a6, a2, 0(a3); a6 = 0xfffffffffffff800 + lw a7, 0(a3); a7 = 0xfffffffffffff801 + + #=================================== + # AMOXOR.W + amoxor.w a4, a1, 0(a3); a4 = 0xffffffff80000000 + lw a5, 0(a3); a5 = 0x7ffff800 + + # try again after a cache miss + li a2, 0xc0000001 + amoxor.w a6, a2, 0(a3); a6 = 0x7ffff800 + lw a7, 0(a3); a7 = 0xffffffffbffff801 + + #=================================== + # AMOSWAP.W + amoswap.w a4, a1, 0(a3); a4 = 0xffffffff80000000 + lw a5, 0(a3); a5 = 0xfffffffffffff800 + + # try again after a cache miss + li a2, 0x0000000080000000 + amoswap.w a6, a2, 0(a3); a6 = 0xfffffffffffff800 + lw a7, 0(a3); a7 = 0xffffffff80000000 + + #=================================== + # AMOMAX.W + amomax.w a4, a1, 0(a3); a4 = 0xffffffff80000000 + lw a5, 0(a3); a5 = 0xfffffffffffff800 + + li a2, 1 + sw x0, 0(a3) + amomax.w a6, a2, 0(a3); a6 = 0 + lw a7, 0(a3); a7 = 1 + + #=================================== + # AMOMAXU.W + amomaxu.w a4, a1, 0(a3); a4 = 0xffffffff80000000 + lw a5, 0(a3); a5 = 0xfffffffffffff800 + + li a2, 0xffffffffffffffff + sw x0, 0(a3) + amomaxu.w a6, a2, 0(a3); a6 = 0 + lw a7, 0(a3); a7 = 0xffffffffffffffff + + #=================================== + # AMOMIN.W + amomin.w a4, a1, 0(a3); a4 = 0xffffffff80000000 + lw a5, 0(a3); a5 = 0xffffffff80000000 + + li a2, 0xffffffffffffffff + sw x0, 0(a3) + amomin.w a6, a2, 0(a3); a6 = 0 + lw a7, 0(a3); a7 = 0xffffffffffffffff + + #=================================== + # AMOMINU.W + amominu.w a4, a1, 0(a3); a4 = 0xffffffff80000000 + lw a5, 0(a3); a5 = 0xffffffff80000000 + + li a2, 0xffffffffffffffff + sw x0, 0(a3) + amominu.w a6, a2, 0(a3); a6 = 0 + lw a7, 0(a3); a7 = 0 + + ret + +.data + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/Tests/rv64a/amo.fs b/Tests/rv64a/amo.fs index a5c49fc..e9a88a7 100644 --- a/Tests/rv64a/amo.fs +++ b/Tests/rv64a/amo.fs @@ -10,6 +10,7 @@ open ISA.RISCV.MachineState // ALU tests let ALU (instrs: InstrField array) (a4 : int64) (a5 : int64) (a6 : int64) (a7 : int64)= // Init MachineState + printfn "ALU tests" let addr = 0x80000000L let mstate = MachineState.InitMachineState Map.empty RV64ia true let mstate = mstate.setPC addr @@ -18,6 +19,7 @@ let ALU (instrs: InstrField array) (a4 : int64) (a5 : int64) (a6 : int64) (a7 let m = Array.fold (fun (m : MachineState) i -> let pc = m.PC let executor = Decoder.Decode m i + printfn "executor: %A: 0x%X" executor.IsSome i Assert.NotEqual(executor, None) let m = executor.Value m Assert.Equal(m.RunState, RunMachineState.Run) @@ -29,6 +31,10 @@ let ALU (instrs: InstrField array) (a4 : int64) (a5 : int64) (a6 : int64) (a7 let x16 = m.getRegister 16 let x17 = m.getRegister 17 + printfn "x14 %X = %X" x14 a4 + printfn "x15 %X = %X" x15 a5 + printfn "x16 %X = %X" x16 a6 + printfn "x17 %X = %X\N" x17 a7 Assert.Equal(x14, a4) Assert.Equal(x15, a5) Assert.Equal(x16, a6) @@ -36,7 +42,7 @@ let ALU (instrs: InstrField array) (a4 : int64) (a5 : int64) (a6 : int64) (a7 [] -[] +[] let ``AMO.ADD`` (a4, a5, a6, a7) = let instrSet = [| 0x80000537 @@ -50,4 +56,22 @@ let ``AMO.ADD`` (a4, a5, a6, a7) = 0x00b6a82f 0x0006a883 |] - ALU instrSet a4 a5 + printfn "ALU AMO.ADD" + ALU instrSet a4 a5 a6 a7 + +[] +[] +let ``AMO.AND`` (a4, a5, a6, a7) = + let instrSet = [| + 0x80000537 + 0x80000593 + 0x00001697 + 0xff868693 + 0x00a6a023 + 0x60b6a72f + 0x0006a783 + 0x80000637 + 0x60c6a82f + 0x0006a883 + |] + ALU instrSet a4 a5 a6 a7 From 9cef77c2045fadc4773bc664cd6e14ddf9a79cc7 Mon Sep 17 00:00:00 2001 From: Evgeny Ukhanov Date: Wed, 29 Apr 2020 02:17:49 +0300 Subject: [PATCH 07/15] Fix AMO decoder --- DecodeA.fs | 24 +++++++++++------------- Decoder.fs | 2 -- Tests/rv64a/amo.fs | 5 +---- 3 files changed, 12 insertions(+), 19 deletions(-) diff --git a/DecodeA.fs b/DecodeA.fs index 77c5a27..c5605c2 100644 --- a/DecodeA.fs +++ b/DecodeA.fs @@ -37,22 +37,20 @@ let Decode (instr: InstrField) : InstructionA = let rl = instr.bitSlice 25 25 let aq = instr.bitSlice 26 26 - printfn "%X[%X] %X" opcode 0b0101111 funct3 - match (opcode) with | 0b0101111 when funct3 = 0b010 -> match funct7 with - | 00010 -> LR_W {| rd = rd; rs1 = rs1; aq = aq; rl = rl |} - | 00011 -> SC_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} - | 00001 -> AMOSWAP_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} - | 00000 -> AMOADD_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} - | 00100 -> AMOXOR_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} - | 01100 -> AMOAND_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} - | 01000 -> AMOOR_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} - | 10000 -> AMOMIN_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} - | 10100 -> AMOMAX_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} - | 11000 -> AMOMINU_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} - | 11100 -> AMOMAXU_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} + | 0b00010 -> LR_W {| rd = rd; rs1 = rs1; aq = aq; rl = rl |} + | 0b00011 -> SC_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} + | 0b00001 -> AMOSWAP_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} + | 0b00000 -> AMOADD_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} + | 0b00100 -> AMOXOR_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} + | 0b01100 -> AMOAND_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} + | 0b01000 -> AMOOR_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} + | 0b10000 -> AMOMIN_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} + | 0b10100 -> AMOMAX_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} + | 0b11000 -> AMOMINU_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} + | 0b11100 -> AMOMAXU_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} | _ -> None | _ -> None diff --git a/Decoder.fs b/Decoder.fs index bbd1761..27d0038 100644 --- a/Decoder.fs +++ b/Decoder.fs @@ -17,9 +17,7 @@ let Decode (mstate : MachineState) (instr: InstrField) : execFunc option = let decM = M.Decode mstate instr let decM64 = M64.Decode mstate instr let decA = A.Decode instr - printfn "decA: %A" decA let decA64 = A64.Decode instr - printfn "decA64: %A" decA64 // Check is instruction should be executed let execI32 = diff --git a/Tests/rv64a/amo.fs b/Tests/rv64a/amo.fs index e9a88a7..9ac1d4d 100644 --- a/Tests/rv64a/amo.fs +++ b/Tests/rv64a/amo.fs @@ -10,7 +10,6 @@ open ISA.RISCV.MachineState // ALU tests let ALU (instrs: InstrField array) (a4 : int64) (a5 : int64) (a6 : int64) (a7 : int64)= // Init MachineState - printfn "ALU tests" let addr = 0x80000000L let mstate = MachineState.InitMachineState Map.empty RV64ia true let mstate = mstate.setPC addr @@ -19,7 +18,6 @@ let ALU (instrs: InstrField array) (a4 : int64) (a5 : int64) (a6 : int64) (a7 let m = Array.fold (fun (m : MachineState) i -> let pc = m.PC let executor = Decoder.Decode m i - printfn "executor: %A: 0x%X" executor.IsSome i Assert.NotEqual(executor, None) let m = executor.Value m Assert.Equal(m.RunState, RunMachineState.Run) @@ -42,7 +40,7 @@ let ALU (instrs: InstrField array) (a4 : int64) (a5 : int64) (a6 : int64) (a7 [] -[] +[] let ``AMO.ADD`` (a4, a5, a6, a7) = let instrSet = [| 0x80000537 @@ -56,7 +54,6 @@ let ``AMO.ADD`` (a4, a5, a6, a7) = 0x00b6a82f 0x0006a883 |] - printfn "ALU AMO.ADD" ALU instrSet a4 a5 a6 a7 [] From 67c02407cca5d946ac47f26846c34ac62f552912 Mon Sep 17 00:00:00 2001 From: Evgeny Ukhanov Date: Fri, 29 May 2020 01:22:36 +0300 Subject: [PATCH 08/15] AMO: added AMO.OR tests and small changes for AMO.ADD --- Tests/asm/Makefile | 2 +- Tests/asm/disasm | 35 ++++++++++------------------------- Tests/rv64a/amo.fs | 24 ++++++++++++++++++++---- 3 files changed, 31 insertions(+), 30 deletions(-) diff --git a/Tests/asm/Makefile b/Tests/asm/Makefile index 8d0aab2..8b126e1 100644 --- a/Tests/asm/Makefile +++ b/Tests/asm/Makefile @@ -9,7 +9,7 @@ ELF=$(addprefix build/,$(TESTS)) ELF32=$(addsuffix 32,$(ELF)) ELF64=$(addsuffix 64,$(ELF)) -RISCVCC64=riscv64-unknown-elf-gcc -march=rv64ima -mabi=lp64 -static -nostdlib -nostartfiles -mcmodel=medany +RISCVCC64=riscv64-unknown-elf-gcc -march=rv64ima -mabi=lp64 -static -nostdlib -nostartfiles -mcmodel=medany RISCVCC32=riscv32-unknown-elf-gcc -march=rv32ima -mabi=ilp32 -static -nostdlib -nostartfiles -mcmodel=medany build32: $(ELF32) diff --git a/Tests/asm/disasm b/Tests/asm/disasm index 3c30b6d..7b22611 100644 --- a/Tests/asm/disasm +++ b/Tests/asm/disasm @@ -11,83 +11,68 @@ Disassembly of section .text.init: Disassembly of section .text: 80001000
: +; Common 80001000: 80000537 lui a0,0x80000 80001004: 80000593 li a1,-2048 80001008: 00001697 auipc a3,0x1 8000100c: ff868693 addi a3,a3,-8 # 80002000 80001010: 00a6a023 sw a0,0(a3) +; AMD.ADD 80001014: 00b6a72f amoadd.w a4,a1,(a3) 80001018: 0006a783 lw a5,0(a3) 8000101c: 80000637 lui a2,0x80000 80001020: 00c6a82f amoadd.w a6,a2,(a3) 80001024: 0006a883 lw a7,0(a3) +; AMD.AND 80001028: 60b6a72f amoand.w a4,a1,(a3) 8000102c: 0006a783 lw a5,0(a3) 80001030: 80000637 lui a2,0x80000 80001034: 60c6a82f amoand.w a6,a2,(a3) 80001038: 0006a883 lw a7,0(a3) +; AMO.OR 8000103c: 40b6a72f amoor.w a4,a1,(a3) 80001040: 0006a783 lw a5,0(a3) 80001044: 00100613 li a2,1 80001048: 40c6a82f amoor.w a6,a2,(a3) 8000104c: 0006a883 lw a7,0(a3) +; AMO.XOR 80001050: 20b6a72f amoxor.w a4,a1,(a3) 80001054: 0006a783 lw a5,0(a3) 80001058: c0000637 lui a2,0xc0000 8000105c: 00160613 addi a2,a2,1 # c0000001 <_end+0x3fffdff9> 80001060: 20c6a82f amoxor.w a6,a2,(a3) 80001064: 0006a883 lw a7,0(a3) +; AMO.SWAP 80001068: 08b6a72f amoswap.w a4,a1,(a3) 8000106c: 0006a783 lw a5,0(a3) 80001070: 80000637 lui a2,0x80000 80001074: 08c6a82f amoswap.w a6,a2,(a3) 80001078: 0006a883 lw a7,0(a3) +; AMO.MAX 8000107c: a0b6a72f amomax.w a4,a1,(a3) 80001080: 0006a783 lw a5,0(a3) 80001084: 00100613 li a2,1 80001088: 0006a023 sw zero,0(a3) 8000108c: a0c6a82f amomax.w a6,a2,(a3) 80001090: 0006a883 lw a7,0(a3) +; AMO.MAXU 80001094: e0b6a72f amomaxu.w a4,a1,(a3) 80001098: 0006a783 lw a5,0(a3) 8000109c: fff00613 li a2,-1 800010a0: 0006a023 sw zero,0(a3) 800010a4: e0c6a82f amomaxu.w a6,a2,(a3) 800010a8: 0006a883 lw a7,0(a3) +; AMO.MIN 800010ac: 80b6a72f amomin.w a4,a1,(a3) 800010b0: 0006a783 lw a5,0(a3) 800010b4: fff00613 li a2,-1 800010b8: 0006a023 sw zero,0(a3) 800010bc: 80c6a82f amomin.w a6,a2,(a3) 800010c0: 0006a883 lw a7,0(a3) +; AMO.MINU 800010c4: c0b6a72f amominu.w a4,a1,(a3) 800010c8: 0006a783 lw a5,0(a3) 800010cc: fff00613 li a2,-1 800010d0: 0006a023 sw zero,0(a3) 800010d4: c0c6a82f amominu.w a6,a2,(a3) 800010d8: 0006a883 lw a7,0(a3) -800010dc: 00008067 ret - -Disassembly of section .bss: - -80002000 : - ... - -Disassembly of section .riscv.attributes: - -00000000 <.riscv.attributes>: - 0: 2341 jal 580 - 2: 0000 unimp - 4: 7200 flw fs0,32(a2) - 6: 7369 lui t1,0xffffa - 8: 01007663 bgeu zero,a6,14 - c: 0019 c.nop 6 - e: 0000 unimp - 10: 7205 lui tp,0xfffe1 - 12: 3376 fld ft6,376(sp) - 14: 6932 flw fs2,12(sp) - 16: 7032 flw ft0,44(sp) - 18: 5f30 lw a2,120(a4) - 1a: 326d jal fffff9c4 <_end+0x7fffd9bc> - 1c: 3070 fld fa2,224(s0) - 1e: 615f 7032 0030 0x307032615f diff --git a/Tests/rv64a/amo.fs b/Tests/rv64a/amo.fs index 9ac1d4d..d702b49 100644 --- a/Tests/rv64a/amo.fs +++ b/Tests/rv64a/amo.fs @@ -29,10 +29,6 @@ let ALU (instrs: InstrField array) (a4 : int64) (a5 : int64) (a6 : int64) (a7 let x16 = m.getRegister 16 let x17 = m.getRegister 17 - printfn "x14 %X = %X" x14 a4 - printfn "x15 %X = %X" x15 a5 - printfn "x16 %X = %X" x16 a6 - printfn "x17 %X = %X\N" x17 a7 Assert.Equal(x14, a4) Assert.Equal(x15, a5) Assert.Equal(x16, a6) @@ -48,6 +44,7 @@ let ``AMO.ADD`` (a4, a5, a6, a7) = 0x00001697 0xff868693 0x00a6a023 + 0x00b6a72f 0x0006a783 0x800005b7 @@ -65,6 +62,7 @@ let ``AMO.AND`` (a4, a5, a6, a7) = 0x00001697 0xff868693 0x00a6a023 + 0x60b6a72f 0x0006a783 0x80000637 @@ -72,3 +70,21 @@ let ``AMO.AND`` (a4, a5, a6, a7) = 0x0006a883 |] ALU instrSet a4 a5 a6 a7 + +[] +[] +let ``AMO.OR`` (a4, a5, a6, a7) = + let instrSet = [| + 0x80000537 + 0x80000593 + 0x00001697 + 0xff868693 + 0x00a6a023 + + 0x40b6a72f + 0x0006a783 + 0x00100613 + 0x40c6a82f + 0x0006a883 + |] + ALU instrSet a4 a5 a6 a7 From 5d3c78c42d8d1da34d833002dc9d39964337216c Mon Sep 17 00:00:00 2001 From: Evgeny Ukhanov Date: Fri, 29 May 2020 12:23:05 +0300 Subject: [PATCH 09/15] AMO: added AMO.XOR tests --- Tests/rv64a/amo.fs | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Tests/rv64a/amo.fs b/Tests/rv64a/amo.fs index d702b49..173dc4b 100644 --- a/Tests/rv64a/amo.fs +++ b/Tests/rv64a/amo.fs @@ -88,3 +88,22 @@ let ``AMO.OR`` (a4, a5, a6, a7) = 0x0006a883 |] ALU instrSet a4 a5 a6 a7 + +[] +[] +let ``AMO.XOR`` (a4, a5, a6, a7) = + let instrSet = [| + 0x80000537 + 0x80000593 + 0x00001697 + 0xff868693 + 0x00a6a023 + + 0x20b6a72f + 0x0006a783 + 0xc0000637 + 0x00160613 + 0x20c6a82f + 0x0006a883 + |] + ALU instrSet a4 a5 a6 a7 From 9a70b9db8b4ae0dc62abf180225f01067fe488f1 Mon Sep 17 00:00:00 2001 From: Evgeny Ukhanov Date: Sun, 31 May 2020 00:08:20 +0300 Subject: [PATCH 10/15] AMO: added AMO.SWAP tests --- Tests/rv64a/amo.fs | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Tests/rv64a/amo.fs b/Tests/rv64a/amo.fs index 173dc4b..35a16d2 100644 --- a/Tests/rv64a/amo.fs +++ b/Tests/rv64a/amo.fs @@ -107,3 +107,21 @@ let ``AMO.XOR`` (a4, a5, a6, a7) = 0x0006a883 |] ALU instrSet a4 a5 a6 a7 + +[] +[] +let ``AMO.SWAP`` (a4, a5, a6, a7) = + let instrSet = [| + 0x80000537 + 0x80000593 + 0x00001697 + 0xff868693 + 0x00a6a023 + + 0x08b6a72f + 0x0006a783 + 0x80000637 + 0x08c6a82f + 0x0006a883 + |] + ALU instrSet a4 a5 a6 a7 From 28fd1e33576c9c0046e8aee7f78857163836ef09 Mon Sep 17 00:00:00 2001 From: Evgeny Ukhanov Date: Sun, 31 May 2020 12:01:38 +0300 Subject: [PATCH 11/15] AMO: added AMO.MAX tests --- Tests/rv64a/amo.fs | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Tests/rv64a/amo.fs b/Tests/rv64a/amo.fs index 35a16d2..ae17cff 100644 --- a/Tests/rv64a/amo.fs +++ b/Tests/rv64a/amo.fs @@ -125,3 +125,22 @@ let ``AMO.SWAP`` (a4, a5, a6, a7) = 0x0006a883 |] ALU instrSet a4 a5 a6 a7 + +[] +[] +let ``AMO.MAX`` (a4, a5, a6, a7) = + let instrSet = [| + 0x80000537 + 0x80000593 + 0x00001697 + 0xff868693 + 0x00a6a023 + + 0xa0b6a72f + 0x0006a783 + 0x00100613 + 0x0006a023 + 0xa0c6a82f + 0x0006a883 + |] + ALU instrSet a4 a5 a6 a7 From 41ff21f290781390745a1f1c1efb5084f6477060 Mon Sep 17 00:00:00 2001 From: Evgeny Ukhanov Date: Mon, 1 Jun 2020 08:12:30 +0300 Subject: [PATCH 12/15] AMO: added AMO.MAXU tests --- Tests/rv64a/amo.fs | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Tests/rv64a/amo.fs b/Tests/rv64a/amo.fs index ae17cff..4522bb9 100644 --- a/Tests/rv64a/amo.fs +++ b/Tests/rv64a/amo.fs @@ -144,3 +144,22 @@ let ``AMO.MAX`` (a4, a5, a6, a7) = 0x0006a883 |] ALU instrSet a4 a5 a6 a7 + +[] +[] +let ``AMO.MAXU`` (a4, a5, a6, a7) = + let instrSet = [| + 0x80000537 + 0x80000593 + 0x00001697 + 0xff868693 + 0x00a6a023 + + 0xe0b6a72f + 0x0006a783 + 0xfff00613 + 0x0006a023 + 0xe0c6a82f + 0x0006a883 + |] + ALU instrSet a4 a5 a6 a7 From c79f59518062d1d56bee10f085ef0d463f7a4afa Mon Sep 17 00:00:00 2001 From: Evgeny Ukhanov Date: Tue, 2 Jun 2020 08:31:20 +0300 Subject: [PATCH 13/15] AMO: added AMO.MIN tests --- Tests/rv64a/amo.fs | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Tests/rv64a/amo.fs b/Tests/rv64a/amo.fs index 4522bb9..94719de 100644 --- a/Tests/rv64a/amo.fs +++ b/Tests/rv64a/amo.fs @@ -163,3 +163,22 @@ let ``AMO.MAXU`` (a4, a5, a6, a7) = 0x0006a883 |] ALU instrSet a4 a5 a6 a7 + +[] +[] +let ``AMO.MIN`` (a4, a5, a6, a7) = + let instrSet = [| + 0x80000537 + 0x80000593 + 0x00001697 + 0xff868693 + 0x00a6a023 + + 0x80b6a72f + 0x0006a783 + 0xfff00613 + 0x0006a023 + 0x80c6a82f + 0x0006a883 + |] + ALU instrSet a4 a5 a6 a7 From c83c3ff275432aee5cb8249157ac6aee8661df46 Mon Sep 17 00:00:00 2001 From: Evgeny Ukhanov Date: Wed, 3 Jun 2020 07:53:40 +0300 Subject: [PATCH 14/15] AMO: added AMO.MINU tests --- Tests/rv64a/amo.fs | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Tests/rv64a/amo.fs b/Tests/rv64a/amo.fs index 94719de..77afd94 100644 --- a/Tests/rv64a/amo.fs +++ b/Tests/rv64a/amo.fs @@ -182,3 +182,22 @@ let ``AMO.MIN`` (a4, a5, a6, a7) = 0x0006a883 |] ALU instrSet a4 a5 a6 a7 + +[] +[] +let ``AMO.MINU`` (a4, a5, a6, a7) = + let instrSet = [| + 0x80000537 + 0x80000593 + 0x00001697 + 0xff868693 + 0x00a6a023 + + 0xc0b6a72f + 0x0006a783 + 0xfff00613 + 0x0006a023 + 0xc0c6a82f + 0x0006a883 + |] + ALU instrSet a4 a5 a6 a7 From 487563c20c2a8cff39cb55ce076e848d90b37ec4 Mon Sep 17 00:00:00 2001 From: Evgeny Ukhanov Date: Tue, 31 Mar 2020 21:37:16 +0300 Subject: [PATCH 15/15] AMO: added besic AMO.D asm --- Tests/asm/Makefile | 3 +- Tests/asm/src/amo.lrsc.w.S | 19 ++++++++--- Tests/asm/src/amo_d.S | 70 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 87 insertions(+), 5 deletions(-) create mode 100644 Tests/asm/src/amo_d.S diff --git a/Tests/asm/Makefile b/Tests/asm/Makefile index 8b126e1..0999daa 100644 --- a/Tests/asm/Makefile +++ b/Tests/asm/Makefile @@ -9,7 +9,8 @@ ELF=$(addprefix build/,$(TESTS)) ELF32=$(addsuffix 32,$(ELF)) ELF64=$(addsuffix 64,$(ELF)) -RISCVCC64=riscv64-unknown-elf-gcc -march=rv64ima -mabi=lp64 -static -nostdlib -nostartfiles -mcmodel=medany +# RISCVCC64=riscv64-unknown-elf-gcc -march=rv64ima -mabi=lp64 -static -nostdlib -nostartfiles -mcmodel=medany +RISCVCC64=riscv64-unknown-linux-gnu-gcc -march=rv64ima -mabi=lp64 -static -nostdlib -nostartfiles -mcmodel=medany RISCVCC32=riscv32-unknown-elf-gcc -march=rv32ima -mabi=ilp32 -static -nostdlib -nostartfiles -mcmodel=medany build32: $(ELF32) diff --git a/Tests/asm/src/amo.lrsc.w.S b/Tests/asm/src/amo.lrsc.w.S index 4e13357..d36d82c 100644 --- a/Tests/asm/src/amo.lrsc.w.S +++ b/Tests/asm/src/amo.lrsc.w.S @@ -3,28 +3,39 @@ #define LOG_ITERATIONS 10 main: + la a0, coreid + li a1, 1 + amoadd.w a2, a1, (a0) + + 1:li a3, 1 + bgeu a2, a3, 1b + + 1: lw a1, (a0) + bltu a1, a3, 1b + + # ====================================== la a0, foo li a5, 0xdeadbeef sc.w a4, a5, (a0); a4 = 1 - lw a4, foo; a4 = 0 + lw a5, foo; a5 = 0 la a0, foo la a1, fooTest3 lr.w a1, (a1) - sc.w a4, a1, (a0); a4 = 1 + sc.w a6, a1, (a0); a6 = 1 lw a0, foo slli a1, a3, LOG_ITERATIONS-1 1: sub a0, a0, a1 addi a3, a3, -1 - bgez a3, 1b; a0 = 0 + bgez a3, 1b la a0, foo 1: lr.w a1, (a0) sc.w a1, x0, (a0) bnez a1, 1b - sc.w a1, x0, (a0); a1 = 1 + sc.w a7, x0, (a0); a7 = 1 ret diff --git a/Tests/asm/src/amo_d.S b/Tests/asm/src/amo_d.S new file mode 100644 index 0000000..aabfcbb --- /dev/null +++ b/Tests/asm/src/amo_d.S @@ -0,0 +1,70 @@ +.section ".text" + .globl main +main: + li a0, 0xffffffff80000000 + li a1, 0xfffffffffffff800 + la a3, amo_operand + sw a0, 0(a3) + + #=================================== + # AMOADD.D + amoadd.d a4, a1, 0(a3); a4 = 0xffffffff80000000 + ld a5, 0(a3); a5 = 0xffffffff7ffff800 + + # try again after a cache miss + amoadd.d a6, a1, 0(a3); a6 = 0xffffffff7ffff800 + ld a7, 0(a3); a7 = 0xffffffff7ffff000 + + #=================================== + # AMOAND.D + amoand.d a4, a1, 0(a3); a4 = 0xffffffff80000000 + ld a5, 0(a3); a5 = 0xffffffff80000000 + + # try again after a cache miss + li a1, 0x0000000080000000; + amoand.d a6, a1, 0(a3); a6 = 0xffffffff80000000 + ld a7, 0(a3); a7 = 0x0000000080000000 + + #=================================== + # AMOOR.D + amoor.d a4, a1, 0(a3); a4 = 0xffffffff80000000 + ld a5, 0(a3); a5 = 0xfffffffffffff800 + + # try again after a cache miss + li a1, 1; + amoor.d a6, a1, 0(a3); a6 = 0xfffffffffffff800 + ld a7, 0(a3); a7 = 0xfffffffffffff801 + + #=================================== + # AMOXOR.D + amoxor.d a4, a1, 0(a3); a4 = 0xffffffff80000000 + ld a5, 0(a3); a5 = 0x000000007ffff800 + + # try again after a cache miss + li a1, 1; + amoxor.d a6, a1, 0(a3); a6 = 0x000000007ffff800 + ld a7, 0(a3); a7 = 0x000000007ffff801 + + #=================================== + # AMOSWAP.D + # try again after a cache miss + + #=================================== + # AMOMAX.D + + #=================================== + # AMOMAXU.D + + #=================================== + # AMOMIN.D + + #=================================== + # AMOMINU.D + + ret + +.data + .bss + .align 3 +amo_operand: + .dword 0