diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..933a05f --- /dev/null +++ b/.gitignore @@ -0,0 +1,5 @@ +*.o +*.d +*.lds +*.map +*.hex \ No newline at end of file diff --git a/BIOS.S b/BIOS.S new file mode 100644 index 0000000..7d9f661 --- /dev/null +++ b/BIOS.S @@ -0,0 +1,297 @@ +.syntax unified +.thumb +.thumb_func +.code 16 +//.text + +//********************* (C) COPYRIGHT 2009 e-Design Co.,Ltd. ********************* +// File Name : ASM.c +// Version : DS203_APP Ver 2.5x Author : bure +//******************************************************************************// + +BIOS: +//=============================================================================== +// System function entrance +//=============================================================================== +// void CTR_HP(void) USB_HP_Interrupt +//------------------------------------------------------------------------------- + .globl __CTR_HP +.thumb_func + . = BIOS + 0x01 +__CTR_HP: +//=============================================================================== +// void USB_Istr(void) USB_LP_Interrupt +//------------------------------------------------------------------------------- + .globl __USB_Istr +.thumb_func + . = BIOS + 0x05 +__USB_Istr: +//=============================================================================== +// void __LCD_Initial(void) +//------------------------------------------------------------------------------- + .globl __LCD_Initial +.thumb_func + . = BIOS + 0x09 +__LCD_Initial : +//=============================================================================== +// void __Point_SCR(u16 x0, u16 y0) +//------------------------------------------------------------------------------- + .globl __Point_SCR +.thumb_func + . = BIOS + 0x0D +__Point_SCR : +//=============================================================================== +// void __LCD_SetPixl(u16 Color) +//------------------------------------------------------------------------------- + .globl __LCD_SetPixl +.thumb_func + . = BIOS + 0x11 +__LCD_SetPixl : +//=============================================================================== +// void __Clear_Screen(u16 Color) +//------------------------------------------------------------------------------- + .globl __Clear_Screen +.thumb_func + . = BIOS + 0x15 +__Clear_Screen : +//=============================================================================== +// u16 __Get_TAB_8x14(u8 Code, u16 Row) +//------------------------------------------------------------------------------- + .globl __Get_TAB_8x14 +.thumb_func + . = BIOS + 0x19 +__Get_TAB_8x14 : +//=============================================================================== +// void __LCD_Set_Block(u16 x1, u16 x2, u16 y1, u16 y2) +//------------------------------------------------------------------------------- + .globl __LCD_Set_Block +.thumb_func + . = BIOS + 0x1D +__LCD_Set_Block : +//=============================================================================== +// void __LCD_DMA_Ready(void) Wait LCD data DMA ready +//------------------------------------------------------------------------------- + .globl __LCD_DMA_Ready +.thumb_func + . = BIOS + 0x21 +__LCD_DMA_Ready : +//=============================================================================== +// void __LCD_Copy(uc16 *pBuffer, u16 NumPixel) Send a row data to LCD +//------------------------------------------------------------------------------- + .globl __LCD_Copy +.thumb_func + . = BIOS + 0x25 +__LCD_Copy: +//=============================================================================== +// void __LCD_Fill(u16 *pBuffer, u16 NumPixel) Fill number of pixel by DMA +//------------------------------------------------------------------------------- + .globl __LCD_Fill +.thumb_func + . = BIOS + 0x29 +__LCD_Fill: +//=============================================================================== +// void __Row_DMA_Ready(void) Wait row base data DMA ready +//------------------------------------------------------------------------------- + .globl __Row_DMA_Ready +.thumb_func + . = BIOS + 0x2D +__Row_DMA_Ready : +//=============================================================================== +// void __Row_Copy(uc16 *S_Buffer,u16 *T_Buffer) Copy one row base data to buffer +//------------------------------------------------------------------------------- + .globl __Row_Copy +.thumb_func + . = BIOS + 0x31 +__Row_Copy: +//=============================================================================== +// u32 __Read_FIFO(void) +//------------------------------------------------------------------------------- + .globl __Read_FIFO +.thumb_func + . = BIOS + 0x35 +__Read_FIFO: +//=============================================================================== +// u32 __Input_Lic(u16 x0, u8 y0, u16 Color)// Return: 32Bits Licence +//------------------------------------------------------------------------------- + .globl __Input_Lic +.thumb_func + . = BIOS + 0x39 +__Input_Lic: +//=============================================================================== +// u32 GetDev_SN(void)// Get 32bits Device Serial Number +//------------------------------------------------------------------------------- + .globl __GetDev_SN +.thumb_func + . = BIOS + 0x3D +__GetDev_SN: +//=============================================================================== +// u8 __Chk_SYS(u32 Licence) Check SYS licence RET: 1 = licence ok +//------------------------------------------------------------------------------- + .globl __Chk_SYS +.thumb_func + . = BIOS + 0x41 +__Chk_SYS: +//=============================================================================== +// u8 __Ident(u32 Dev_ID, u32 Proj_ID, u32 Lic_No) RET: 1 = licence ok +//------------------------------------------------------------------------------- + .globl __Ident +.thumb_func + . = BIOS + 0x45 +__Ident: +//=============================================================================== +// void __Display_Str(u16 x0, u16 y0, u16 Color, u8 Mode, u8 *s) +//------------------------------------------------------------------------------- + .globl __Display_Str +.thumb_func + . = BIOS + 0x49 +__Display_Str: +//=============================================================================== +// void __Set(u8 Device, u32 Value) Hardware control device Settings +//------------------------------------------------------------------------------- + .globl __Set +.thumb_func + . = BIOS + 0x4D +__Set: +//=============================================================================== +// void Set_Param(u8 RegAddr, u8 Parameter) Trigger control parameter set +//------------------------------------------------------------------------------- + .globl __Set_Param +.thumb_func + . = BIOS + 0x51 +__Set_Param: +//=============================================================================== +// u32 __Get(u8 Kind) Get hardware attribute & status +//------------------------------------------------------------------------------- + .globl __Get +.thumb_func + . = BIOS + 0x55 +__Get: +//=============================================================================== +// void __ExtFlash_PageWR(u8* pBuffer, u32 WriteAddr)// +//------------------------------------------------------------------------------- + .globl __ExtFlash_PageWR +.thumb_func + . = BIOS + 0x59 +__ExtFlash_PageWR: +//=============================================================================== +// void __Disk_Buff_RD(u8* pBuffer, u32 ReadAddr, u16 NumByteToRead)// +//------------------------------------------------------------------------------- + .globl __ExtFlash_PageRD +.thumb_func + . = BIOS + 0x5D +__ExtFlash_PageRD: +//=============================================================================== +// u8 ReadDiskData(u8* pBuffer, u32 ReadAddr, u16 Lenght) +//------------------------------------------------------------------------------- + .globl __ReadDiskData +.thumb_func + . = BIOS + 0x61 +__ReadDiskData: +//=============================================================================== +// u8 ProgDiskPage(u8* pBuffer, u32 ProgAddr) +//------------------------------------------------------------------------------- + .globl __ProgDiskPage +.thumb_func + . = BIOS + 0x65 +__ProgDiskPage: +//=============================================================================== +// u16 __LCD_GetPixl(void) +//------------------------------------------------------------------------------- + .globl __LCD_GetPixl +.thumb_func + . = BIOS + 0x69 +__LCD_GetPixl : +//=============================================================================== + // void __USB_Init(void) +//------------------------------------------------------------------------------- + .globl __USB_Init +.thumb_func + . = BIOS + 0x6D +__USB_Init: +//=============================================================================== +// u8 __FLASH_Erase(u32 Address) RET: 1 = ok +//------------------------------------------------------------------------------- + .globl __FLASH_Erase +.thumb_func + . = BIOS + 0x71 +__FLASH_Erase: +//=============================================================================== +// u8 __FLASH_Prog(u32 Address, u16 Data) RET: 1 = ok +//------------------------------------------------------------------------------- + .globl __FLASH_Prog +.thumb_func + . = BIOS + 0x75 +__FLASH_Prog: +//=============================================================================== +// void __FLASH_Unlock(void) +//------------------------------------------------------------------------------- + .globl __FLASH_Unlock +.thumb_func + . = BIOS + 0x79 +__FLASH_Unlock: +//=============================================================================== +// void __FLASH_Lock(void) +//------------------------------------------------------------------------------- + .globl __FLASH_Lock +.thumb_func + . = BIOS + 0x7D +__FLASH_Lock: +//=============================================================================== +// u8* __Chk_DFU(void) +//------------------------------------------------------------------------------- + .globl __Chk_DFU +.thumb_func + . = BIOS + 0x81 +__Chk_DFU: +//=============================================================================== +// u8* __Chk_HDW(void) +//------------------------------------------------------------------------------- + .globl __Chk_HDW +.thumb_func + . = BIOS + 0x85 +__Chk_HDW: +//=============================================================================== +// u8 __OpenFileWr(u8* Buffer, u8* FileName, u16* Cluster, u32* pDirAddr)// +//------------------------------------------------------------------------------- + .globl __OpenFileWr +.thumb_func + . = BIOS + 0x89 +__OpenFileWr: +//=============================================================================== +// u8 __OpenFileRd(u8* Buffer, u8* FileName, u16* Cluster, u32* pDirAddr)// +//------------------------------------------------------------------------------- + .globl __OpenFileRd +.thumb_func + . = BIOS + 0x8D +__OpenFileRd: +//=============================================================================== +// u8 __ReadFileSec(u8* Buffer, u16* Cluster)// +//------------------------------------------------------------------------------- + .globl __ReadFileSec +.thumb_func + . = BIOS + 0x91 +__ReadFileSec: +//=============================================================================== +// u8 __ProgFileSec(u8* Buffer, u16* Cluster)// +//------------------------------------------------------------------------------- + .globl __ProgFileSec +.thumb_func + . = BIOS + 0x95 +__ProgFileSec: +//=============================================================================== +// u8 __CloseFile(u8* Buffer, u32 Lenght, u16* Cluster, u32* pDirAddr)// +//------------------------------------------------------------------------------- + .globl __CloseFile +.thumb_func + . = BIOS + 0x99 +__CloseFile: +//=============================================================================== +// void __Row_Fill(uc16 *S_Buffer,u16 *T_Buffer) Fill one row base data to buffer +//------------------------------------------------------------------------------- + .globl __Row_Fill +.thumb_func + . = BIOS + 0x9D +__Row_Fill: +//=============================================================================== + +//******************************* END OF FILE *********************************** diff --git a/Calibrat.c b/Calibrat.c new file mode 100644 index 0000000..fee63a5 --- /dev/null +++ b/Calibrat.c @@ -0,0 +1,561 @@ +/********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ******************** + File Name : Calibrat.c + Version : DS203_APP Ver 2.3x Author : bure +*******************************************************************************/ +#include "Interrupt.h" +#include "Function.h" +#include "Calibrat.h" +#include "Process.h" +#include "File.h" +#include "BIOS.h" +#include "Menu.h" + +const char VS_STR[8][12] ={"250-300mV", "!0.5-0.6V!","!1.0-1.2V!","!2.5-3.0V!", + "!5.0-6.0V!"," !10-12V! "," !25-30V! "," !50-60V! "}; +const char V_UNIT1[8] ={'m','V','m','V','V',' ','k','V'}; +const char CenterStr[5][12]= {"-+","-< o( ) >+","-< (o) >+","-< ( )o >+","-< ( ) o>+"}; +const char CenterStep[32]= "CENTER CAL SOURCE ON ADC STEP "; + +const char ClockEntry[5][39]= {" COMPENSATE FOR CPU CLOCK ","CONNECT FREQ COUNTER TO WAVE OUT(1MHZ)", + "ENTER ERROR IN PPM: +IF HIGH -IF LOW ","L TOGGLE TO CHANGE-PRESS 2 TO CONTINUE", + " ( ) "}; + + //shift > 3 char +s16 PPM_Comp=0; +u8 CalibrateMode=0; + +void ClearTop(void); + +/******************************************************************************* + Calibrat : Calibrat routine +*******************************************************************************/ +void Calibrat(u8 Channel) +{ + + s8 Ma1[10], Mb1[10], Ma3[10], Mb3[10]; + u16 Ma2[10], Mb2[10], i, j; + s16 TmpA, TmpB; + u8 Range, k = 0, m, Step, Tmp, V_min, V_max; + s8 Offset; + char n[10]; + u16 BatLevel[2]={0,0}; + char PPM_Str[5]; + + Key_Buffer = 0; + __Set(STANDBY, DN); // exit the power saving state + //__Set(BACKLIGHT, 10*(Title[BK_LIGHT][CLASS].Value+1)); + BackLight(0); + __Clear_Screen(BLACK); // clear the screen + + Delayms(300); + + Title[OUTPUT][KIND].Value=PWM; //set to PWM + Title[OUTPUT][FRQN].Value=18; //set to 1mhz + Title[OUTPUT][DUTYPWM].Value=15000; //set to 50% + GenAdjustMode=0; + Sweep=0; + Update_Output(); + + j=0; + for(i=200;i>144;i-=11){ + if(i==156)i=145; + Print_Str(40,i,0x0405,PRN,(char*) ClockEntry[j++]); + } + + while(Key_Buffer){}; //wait for key release + while(1){ + s16ToDec3(PPM_Str, PPM_Comp); + Print_Str(176,145,0x0405,PRN,PPM_Str); + if(Key_Buffer==K_INDEX_DEC) {if(PPM_Comp>-999)PPM_Comp--;} // K5 left toggle - + if(Key_Buffer==K_INDEX_INC) {if(PPM_Comp<999)PPM_Comp++;} // K5 left toggle - + if(Key_Buffer==KEY2)break; + Key_Buffer = 0; + } + + Title[OUTPUT][KIND].Value=6; //set to OFF + Update_Output(); + + Key_Buffer = 0; + __Clear_Screen(BLACK); // clear the screen + + __Set(ADC_MODE, SEPARATE); // Set Separate mode + __Set(ADC_CTRL, EN); + __Set(TRIGG_MODE, UNCONDITION); // set any trigger + _Status = RUN; + __Set(BEEP_VOLUME, 5*(Title[VOLUME][CLASS].Value-1)); // Reload volume + Beep_mS = 500; // buzzer ring 500mS + Range = 0; + Step = 0; + m = 0; + + __Set(T_BASE_PSC, X_Attr[_100uS].PSC); // T_BASE = 100uS + __Set(T_BASE_ARR, X_Attr[_100uS].ARR); + + __Set(CH_A_COUPLE, DC); + __Set(CH_B_COUPLE, DC); + + for(j=0; j<220; j+=20){ // draw table + for(i=0; i<399; i++){ + __Point_SCR(i, j); + __LCD_SetPixl(WHT); + } + } + + for(i=0; i<399; i++){ + __Point_SCR(i, 239); + __LCD_SetPixl(WHT); + } + __Point_SCR( 0, 0); + for(j= 0; j<239; j++) __LCD_SetPixl(WHT); + + for(i=44;i<333;i+=44){ + __Point_SCR(i,20); + for(j=20; j<201; j++) __LCD_SetPixl(WHT); + if(i==132)i+=24; + } + + __Point_SCR(398, 0); + for(j= 0; j<239; j++) __LCD_SetPixl(WHT); + + Print_Str( 6, 185, 0x0005, PRN, "CH_A"); // display the form title bar + Print_Str( 49, 185, 0x0005, PRN, "ZERO"); + Print_Str( 93, 185, 0x0005, PRN, "DIFF"); + Print_Str(137, 185, 0x0005, PRN, "VOLTAGE"); + Print_Str(206, 185, 0x0105, PRN, "CH_B"); + Print_Str(249, 185, 0x0105, PRN, "ZERO"); + Print_Str(293, 185, 0x0105, PRN, "DIFF"); + Print_Str(338, 185, 0x0105, PRN, "VOLTAGE"); + + for(i=0; i<=G_Attr[0].Yp_Max; i++){ + Print_Str( 6, 166-(i*20), 0x0005, PRN, Y_Attr[i].STR); // display range + Print_Str(206, 166-(i*20), 0x0105, PRN, Y_Attr[i].STR); + Ma1[i] = Ka1[i]; Ma2[i] = Ka2[i]; Ma3[i] = Ka3[i]; // backup parameters before calibration + Mb1[i] = Kb1[i]; Mb2[i] = Kb2[i]; Mb3[i] = Kb3[i]; + } + + while (1){ + +/* + if (__Get(USB_POWER)>0) PD_Cnt = 600; + if(PD_Cnt == 0){ + __Set(BACKLIGHT, 0); // turn off the backlight + __Set(STANDBY, EN); // enter low power state + return; + } +*/ + + PD_Cnt = 600; // do we need to enable standby timer in calibration mode? + + __Set(CH_A_RANGE, Range); __Set(CH_B_RANGE, Range); + Delayms(20); + __Set(FIFO_CLR, W_PTR); + Delayms(20); + a_Avg = 2048; b_Avg = 2048; + V_max=0; V_min=0; + + for(i=0; i <4096; i++){ + TransferFIFO(i,0); + Tmp=(DataBuf[i] & 0xFF )-ADCoffset; + if(Channel == TRACK1){ + if(i==0)V_max=V_min=Tmp; + if(Tmp>V_max)V_max=Tmp; + if(Tmp>8) & 0xFF )-ADCoffset; + if(Channel == TRACK2){ + if(i==0)V_max=V_min=Tmp; + if(Tmp>V_max)V_max=Tmp; + if(Tmp2)Offset=2; Offset+=2; //limit to +/- 2 steps + Print_Str( 3*8, 208, 0x0305, PRN,(char*)CenterStep); //31 chars + Print_Str( 36*8, 208, 0x0405, PRN,(char*)CenterStr[Offset]); //11 chars + }else{ + TmpA = Ka1[Range] +(Ka2[Range]*(a_Avg/4096)+ 512)/1024; //for offset calibration w/no signal + TmpB = Kb1[Range] +(Kb2[Range]*(b_Avg/4096)+ 512)/1024; + } + + if(Blink){ + Blink = 0; + switch (Step){ + case 0: + Range = 0; + SetOffset(0,Range,40); + SetOffset(1,Range,40); + + Print_Str( 2*8, 222, 0x0305, PRN, "CAL W/LOW BATT (1/4 CHARGE) THEN W/AC CHARGER"); + Print_Str( 8, 208, 0x0305, PRN, " PLEASE CONNECT"); + Print_Str(29*8, 208, 0x0305, PRN, "INPUT TO "); + Print_Str(38*8, 208, 0x0405, PRN, "GND "); + Print_Str( 8, 6, 0x0305, PRN, " PRESS KEY TO CONFIRM THE INPUT VOLTAGE "); + Print_Str(10*8, 6, 0x0405, Twink, " "); + if(Channel == TRACK1){ + Print_Str( 23*8, 208, 0x0005, PRN, " CH_A "); + for(i=0; i<=G_Attr[0].Yp_Max; i++){ + Ka1[i] = 0; Ka2[i] = 1024; Ka3[i] = 0; // set calibration parameters to initial values + } + } + if(Channel == TRACK2){ + Print_Str( 23*8, 208, 0x0105, PRN, " CH_B "); + for(i=0; i<=G_Attr[0].Yp_Max; i++){ + Kb1[i] = 0; Kb2[i] = 1024; Kb3[i] = 0; // set calibration parameters of initial values + } + } + break; + case 1: + Print_Str( 8, 6, 0x0305, PRN, " AUTOMATIC CALIBRATION IN PROGRESS... "); + if(Channel == TRACK1){ + s8ToPercen(n, TmpA - 40); + Print_Str( 45, 166-(Range*20), 0x0005, INV, n); + Ka1[Range] -= TmpA - 40; + } + if(Channel == TRACK2){ + s8ToPercen(n, TmpB - 40); + Print_Str(245, 166-(Range*20), 0x0105, INV, n); + Kb1[Range] -= TmpB - 40; + } + Range++; + if(Range > G_Attr[0].Yp_Max){ + Range = 0; Step++; + } + SetOffset(0,Range,40); + SetOffset(1,Range,40); + k = 0; + break; + case 2: + k++; + if(k >= 8) k = 0; + if(Channel == TRACK1){ + s8ToPercen(n, TmpA - 40); + Print_Str( 45, 166-(Range*20), 0x0005, PRN, n); + if(TmpA - 40 != 0) Ka1[Range] -= TmpA - 40; + else k = 0; + } + if(Channel == TRACK2){ + s8ToPercen(n, TmpB - 40); + Print_Str(245, 166-(Range*20), 0x0105, PRN, n); + if(TmpB - 40 != 0) Kb1[Range] -= TmpB - 40; + else k = 0; + } + if(k == 0) Range++; + if(Range > G_Attr[0].Yp_Max){ + Range = 0; Step++; + } + SetOffset(0,Range,40); + SetOffset(1,Range,40); + break; + case 3: + k++; + SetOffset(0,Range,160); + SetOffset(1,Range,160); + if((Channel == TRACK1)&&(TmpA > 140)) Step++; + if((Channel == TRACK2)&&(TmpB > 140)) Step++; + if(k > 20) Step++; + break; + case 4: + k = 0; + if(Channel == TRACK1){ + s8ToPercen(n, TmpA - 160); + Print_Str( 89, 166-(Range*20), 0x0005, INV, n); + Ka3[Range] -= (1024*(TmpA-160)+80)/160; + } + if(Channel == TRACK2){ + s8ToPercen(n, TmpB - 160); + Print_Str(289, 166-(Range*20), 0x0105, INV, n); + Kb3[Range] -= (1024*(TmpB-160)+80)/160; + } + Range++; + if(Range > G_Attr[0].Yp_Max){ + Range = 0; Step++; + } + SetOffset(0,Range,160); + SetOffset(1,Range,160); + break; + case 5: + k++; + if(k >= 8) k = 0; + if(Channel == TRACK1){ + s8ToPercen(n, TmpA - 160); + Print_Str( 89, 166-(Range*20), 0x0005, PRN, n); + if(TmpA - 160 != 0) Ka3[Range] -= (1024*(TmpA-160)+80)/160; + else k = 0; + } + if(Channel == TRACK2){ + s8ToPercen(n, TmpB - 160); + Print_Str(289, 166-(Range*20), 0x0105, PRN, n); + if(TmpB - 160 != 0) Kb3[Range] -= (1024*(TmpB-160)+80)/160; + else k = 0; + } + if(k == 0) Range++; + if(Range > G_Attr[0].Yp_Max){ + Range = 0; Step++; + } + SetOffset(0,Range,160); + SetOffset(1,Range,160); + break; + case 6: + k++; + if(k > 20) Step++; + Range = 0; + if(m < 2){ + SetOffset(0,Range,40); + SetOffset(1,Range,40); + if((Channel == TRACK1)&&(TmpA < 50)){ + Step = 1; + m++; + } + if((Channel == TRACK2)&&(TmpB < 50)){ + Step = 1; + m++; + } + } else { + SetOffset(0,Range,25); + SetOffset(1,Range,25); + if((Channel == TRACK1)&&(TmpA < 55)) Step++; + if((Channel == TRACK2)&&(TmpB < 55)) Step++; + } + + if(Step==7){ + if(Channel == TRACK1){ + BatLevel[0]=__Get(V_BATTERY); //capture corresponding bat level right after setting offsets + for(i=0; i<=G_Attr[0].Yp_Max; i++) Ka2[i] = Ma2[i]; //load previously saved values as starting point + } //so as to not have to start all over + if(Channel == TRACK2){ + BatLevel[1]=__Get(V_BATTERY); + for(i=0; i<=G_Attr[0].Yp_Max; i++) Kb2[i] = Mb2[i]; + } + ClearTop(); + } + break; + case 7: + Print_Str( 4*8, 222, 0x0305, PRN, " INPUT "); + Print_Str(11*8, 222, 0x0405, Twink, (char*)VS_STR[Range]); + Print_Str(20*8, 222, 0x0305, PRN, " STANDARD VOLTAGE TO "); + Print_Str( 8, 6, 0x0305, PRN, "MODIFY VOLTAGE: ... "); + Print_Str(18*8, 6, 0x0405, Twink, "-"); + Print_Str(22*8, 6, 0x0405, Twink, "+"); + Print_Str(27*8, 6, 0x0305, PRN, "SELECT RANGE: --- "); + Print_Str(42*8, 6, 0x0405, Twink, "<"); + Print_Str(46*8, 6, 0x0405, Twink, ">"); + if(Channel == TRACK1){ + if(TmpA > 10){ + Int2Str(n, TmpA * Y_Attr[Range].SCALE, V_UNIT, 4, UNSIGN,1); //show 4 digits, with decimal shifted left 1, with + } else { //values read at X10 scale. Allows better precision + Int2Str(n, 0, V_UNIT, 3, SIGN,0); //while adjusting gain calibration, -25 already done + } + Print_Str( 134, 166-(Range*20), 0x0005, Twink, n); + Print_Str(41*8, 222, 0x0005, PRN, "CH_A "); + } + if(Channel == TRACK2){ + if(TmpB > 10){ + Int2Str(n, TmpB * Y_Attr[Range].SCALE, V_UNIT, 4, UNSIGN,1); + } else { + Int2Str(n, 0, V_UNIT, 3, SIGN,0); + } + Print_Str( 334, 166-(Range*20), 0x0105, Twink, n); + Print_Str(41*8, 222, 0x0105, PRN, "CH_B "); + } + break; + case 8: //" PRESS --- TO SELECT THE NEXT OPERATION" + m = 0; + Print_Str( 8, 6, 0x0305, PRN, " PRESS --- "); + Print_Str(12*8, 6, 0x0405, Twink, "<"); + Print_Str(16*8, 6, 0x0405, Twink, ">"); + Print_Str(17*8, 6, 0x0305, PRN, " TO SELECT THE NEXT OPERATION "); + Print_Str( 8, 216, 0x0305, PRN, " PRESS TO "); + //Print_Str(14*8, 216, 0x0405, PRN, "CONFIRM THE RE-CALIBRATION "); + Print_Str(14*8, 216, 0x0405, PRN, "RESTART THE RE-CALIBRATION "); + Print_Str( 9*8, 216, 0x0405, Twink, " "); + if(Channel == TRACK1) Print_Str(41*8, 216, 0x0005, PRN, "CH_A "); + if(Channel == TRACK2) Print_Str(41*8, 216, 0x0105, PRN, "CH_B "); + break; //" PRESS TO CONFIRM THE RE-CALIBRATION CH_A " + case 9: // "SELECT THE CALIBRATION CH_A " + Print_Str( 9*8, 216, 0x0405, Twink, " "); + Print_Str(14*8, 216, 0x0405, PRN, "SELECT THE CALIBRATION "); + if(Channel == TRACK1) Print_Str(37*8, 216, 0x0105, PRN, "CH_B "); + if(Channel == TRACK2) Print_Str(37*8, 216, 0x0005, PRN, "CH_A "); + break; + case 10: // "Exit WITHOUT SAVING RESULTS " + Print_Str( 9*8, 216, 0x0405, Twink, " "); + Print_Str(14*8, 216, 0x0405, PRN, "Exit WITHOUT SAVING RESULTS "); + break; + case 11: // "Exit AND SAVE CALIBRATION RESULTS" + Print_Str(8, 222, 0x0405, PRN, "PRESS BUTTON 2 TO SAVE IF CALIBRATING WITH BATT"); + Print_Str(8, 208, 0x0405, PRN, " PRESS BUTTON 3 IF CALIBRATING WITH AC ADAPTER "); + break; + case 12: // "Exit AND RESTORE SYSTEM DEFAULTS " + Print_Str( 9*8, 216, 0x0405, Twink, " "); + Print_Str(14*8, 216, 0x0405, PRN, "Exit AND RESTORE SYSTEM DEFAULTS "); + break; + } + } + if(Key_Buffer){ + PD_Cnt = 600; // reset the waiting timer to 600 seconds + if((Range <= G_Attr[0].Yp_Max)&&(Step == 7)){ + if(Channel == TRACK1){ + Print_Str(134, 166-(Range*20), 0x0005, PRN, n); + } + if(Channel == TRACK2){ + Print_Str(334, 166-(Range*20), 0x0105, PRN, n); + } + } + switch (Key_Buffer){ + case KEY2: + if(Step == 0) Step++; + if((Step == 8)||(Step == 9)){ + ClearTop(); + if(Step == 9) Channel = 1 - Channel; + for(i=0; i<=G_Attr[0].Yp_Max; i++){ + if(Channel == TRACK1){ + Print_Str( 45, 166-(i*20), 0x0005, PRN, " "); + Print_Str( 89, 166-(i*20), 0x0005, PRN, " "); + Print_Str(134, 166-(i*20), 0x0005, PRN, " "); + } + if(Channel == TRACK2){ + Print_Str(245, 166-(i*20), 0x0105, PRN, " "); + Print_Str(289, 166-(i*20), 0x0105, PRN, " "); + Print_Str(334, 166-(i*20), 0x0105, PRN, " "); + } + } + Step = 0;; + } + if(Step >= 10){ + if(Step == 10){ + for(i=0; i<=G_Attr[0].Yp_Max; i++){ + Ka1[i] = Ma1[i]; Ka2[i] = Ma2[i]; Ka3[i] = Ma3[i]; + Kb1[i] = Mb1[i]; Kb2[i] = Mb2[i]; Kb3[i] = Mb3[i]; + } + Save_Param(0); // do not save the calibration parameters + ClearTop(); + Print_Str( 8, 216, 0x0405, PRN, " CALIBRATION DATA NOT SAVED "); + } + if(Step == 11){ + + if(BatLevel[0]>0){ + LoBatLevel[0]=BatLevel[0]; //Low battery correction reference levels + for(i=0;i<10;i++){ + LKa1[i]=Ka1[i]; + LKa2[i]=Ka2[i]; + LKa3[i]=Ka3[i]; + } + } + + if(BatLevel[1]>0){ + LoBatLevel[1]=BatLevel[1]; + for(i=0;i<10;i++){ + LKb1[i]=Kb1[i]; + LKb2[i]=Kb2[i]; + LKb3[i]=Kb3[i]; + } + } + + Save_Param(0); // save parameters after correction " + ClearTop(); + Print_Str( 8, 216, 0x0405, PRN, "SAVING THE CALIBRATION DATA FROM BAT LOW CORRECT"); + } + if(Step == 12){ + + InitiateCalData(); + LoBatLevel[0]=0; + LoBatLevel[1]=0; + HiBatLevel[0]=0; + HiBatLevel[1]=0; + PPM_Comp=0; + + Save_Param(0); // clear the calibration parameters, save the default values + ClearTop(); + Print_Str( 8, 216, 0x0405, PRN, " RESTORED DEFAULT CALIBRATION DATA "); + } + Delayms(900); + App_init(1); + Config_init(); + return; + } + break; + case KEY3: + if(Step == 11){ + if(BatLevel[0]>0){ + HiBatLevel[0]=BatLevel[0]; //High battery correction reference levels + for(i=0;i<10;i++){ + HKa1[i]=Ka1[i]; + HKa2[i]=Ka2[i]; + HKa3[i]=Ka3[i]; + } + } + if(BatLevel[1]>0){ + HiBatLevel[1]=BatLevel[1]; + for(i=0;i<10;i++){ + HKb1[i]=Kb1[i]; + HKb2[i]=Kb2[i]; + HKb3[i]=Kb3[i]; + } + } + Save_Param(0); // save parameters after correction " + ClearTop(); + Print_Str( 8, 216, 0x0405, PRN, " SAVING THE CALIBRATION DATA FROM HIGH CORRECT "); + Delayms(900); + App_init(1); + Config_init(); + return; + } + + break; + case K_ITEM_DEC: + if((Step == 7)&&(Range > 0)) Range--; + if( Step >= 9) {ClearTop(); Step--;} + if( Step == 8) Step = 12; + break; + case K_ITEM_INC: + if(Step >= 8) {ClearTop();Step++;} + if(Step > 12) Step = 8; + if(Step == 7) Range++; + if(Range > G_Attr[0].Yp_Max){ + Range = 0; + ClearTop(); + Step++; + } + break; + case K_INDEX_DEC: + if(Step == 7){ + if((Channel == TRACK1)&&(TmpA > 35)) Ka2[Range] --; //all were -=2/+=2 + if((Channel == TRACK2)&&(TmpB > 35)) Kb2[Range] --; + } + break; + case K_INDEX_INC: + if(Step == 7){ + if((Channel == TRACK1)&&(TmpA > 35)) Ka2[Range] ++; + if((Channel == TRACK2)&&(TmpB > 35)) Kb2[Range] ++; + } + break; + } + Key_Buffer = 0; + } + } +} + +void ClearTop(void){ +u8 i; +u16 j; + for(i=201;i<239;i++){ + for (j=1;j<398;j++){ + __Point_SCR(j,i); + __LCD_SetPixl(BLACK); + } + } +} + + +/********************************* END OF FILE ******************************/ diff --git a/Draw.c b/Draw.c new file mode 100644 index 0000000..81ec3cc --- /dev/null +++ b/Draw.c @@ -0,0 +1,2319 @@ + //******************** (C) COPYRIGHT 2009 e-Design Co.,Ltd. ********************* +// File Name : Draw.c +// Version : DS203_APP Ver 2.3x Author : bure +//*******************************************************************************/ +#include +#include "Interrupt.h" +#include "Process.h" +#include "Draw.h" +#include "Menu.h" +#include "BIOS.h" +#include "Function.h" +#include "File.h" + +void LoadBuffer(u16 Row, u8 buffer,u8 *y,u8 *Dot_Hide,u8 service); +void LoadFFTbuffer(u16 Row,u8 buffer); +void Print_Str_Row(u16 Row, u16* LCD_Buffer, u16 x0, s16 y0, char *s); +void DisplayFFtValues(u16 Row,u8 buffer); +void DisplayDbScale(u16 Row, u8 buffer, u8 service); +void Base1(u8 buffer); +void LoadBaseBuffers(void); //load all 3 buffers +void TraceShadow(u8 start,u8 limit,u8 buffer); +void VernierMark(u8 buffer,u16 color); +void LoadXYBuffer(u16 Row); +void ClearFFTbuffer(void); +s32 ScaleXposi(void); +void NFreqParse(u8 index,u8 suffix); +u16 ColorIndexGen(u8 level); +void DrawPixel(u16 x,u8 y, u16 color); +void DrawBase(u16 x,u16 color); +void DisplayDetFrqn(u16 Row, u8 buffer); +void Uart(); +void PrintUart(u16 Row, u8 buffer, u8 service); +void i2c(void); +void LoadChars(u8 service); +void InitiateCharArrays(void); +void Spi(void); +void SpiChart(u16 Row,u8 buffer); +u8 BitReadPosition(u16 i); +u8 DigChLockout=0; +void PrintText(u16 x,u8 y,char *s); +void PrintConfigName(void); +void DisplayCursorValues(u16 Row, u8 buffer); +void DisplayDeltaValues(u16 Row, u8 buffer); + + +char Nfreq[9]; +char Nsuffix[3]; +u16 MAX_X; +uc16 RULE_BASE[8] ={0x020,0x040,0x080,0x040,0x020,0x010,0x008,0x010}; +u8 OffsetX; +u8 OffsetY; +s16 FactorX; +s16 FactorY; +s16 FactorY13; +u16 SpecRow = 25; +u8 SpecLine = 0; +s32 Tmp2; +s16 skip; +u8 UpdateBackground; +u8 Rdiscard=0; //post-signal trace blanking +char DbScaleStr[3]; +//uc16 COLOR_INDEX=0x050F; //red fft values display +u16 COLOR_INDEX=0x0503; //green fft values display + //0x0500 = cyan w black bg + //0x0501 = yellow w black bg +u16 Count_FPS = 0; +u8 SpecMode=0; +u8 InitXY=1; +u8 XYper=0; +u8 FrameCount; +u8 ClearPerst; +u8 PerstFrameNumber=0; +u8 Raw=0; +u8 UpdateScale; +s16 DetFrqn[12]; +uc8 DetFrqAdj[10]= {110,108,106,104,104,104,104,104,104,104}; +u16 RowMem, RowMemPeak; +u16 XYLimit=234; +u8 ListBottom; +u8 DisableCursorDisplay=0; +u8 EnableCursorDisplay=0; + +u32 BaudRate; +u8 FrameSize=10; +u8 DataSize=8; +u8 Parity=0; +char AscChar[2][3][17]; +char AscCharB[2][3][17]; +char HexChar[6][49]; +char HexCharB[6][49]; +u8 ArrayIndex; +u16 BitDuration; +u8 Mask=1; +u8 DataAdj=0; +u8 ValidFrame; +typedef struct{ + u8 Data; + u16 Index; + u16 End; + u8 DataB; + u8 BitsPerWord; +}ByteInfo; +ByteInfo ByteArray[96]; +u8 SpiMode=0; +u8 SpiBitOrder=0; +s16 SpiNumBits=8; +u8 SpiAdj=0; +u8 WordEndFlag=0; +u8 SpiChartFlag=0; +u16 ClockPeriod=0xFFFF; +s16 ChartIndex=0x7FFF; +u16 TcurDelta=30; +u8 OSBuffer=0; +u8 Hbold=0; +u16 Limit=299; +u8 SkipFirstRow=0; +u8 CursorDisplaySelect=0; + +const char CursorTypeStr[5][4]={{'T','1',':',0},{'T','2',':',0},{'V','1',':',0},{'V','2',':',0},{'T','r',':',0}}; + +uc8 Mark_TAB_1[7] ={0x00,0x00,0x42,0xFE,0x02,0x00,0x00}; // Mark 1 +uc8 Mark_TAB_2[7] ={0x00,0x46,0x8A,0x92,0x92,0x62,0x00}; // Mark 2 +uc8 Mark_TAB_3[7] ={0x00,0x44,0x82,0x92,0x92,0x6C,0x00}; // Mark 3 +uc8 Mark_TAB_4[7] ={0x00,0x18,0x28,0x4A,0xFE,0x0A,0x00}; // Mark 4 +uc8 Mark_TAB_T[7] ={0x00,0x40,0x40,0x7E,0x40,0x40,0x00}; // Mark T + +uc8 Mark_TAB[5][7] ={{0x00,0x00,0x42,0xFE,0x02,0x00,0x00}, // Mark 1 + {0x00,0x46,0x8A,0x92,0x92,0x62,0x00}, // Mark 2 + {0x00,0x44,0x82,0x92,0x92,0x6C,0x00}, // Mark 3 + {0x00,0x18,0x28,0x4A,0xFE,0x0A,0x00}, // Mark 4 + {0x00,0x40,0x40,0x7E,0x40,0x40,0x00}}; // Mark T + + uc16 FrameCountRef[22]= {18000,9000,3600,1800,900,362,182,92, 49, 29, 15, 12, 12,12,12,12,12,12,12,12,12,12}; +// 1 500 200 100 50 20 10 5 2 1 500 200 time base + +//uc16 Char_TAB_8x11[744] = { +//uc16 Char_TAB_8x11[752] = { // used when adding extra character +//uc16 Char_TAB_8x11[747] = { // used when adding 3 pix wide period + uc16 Char_TAB_8x11[768] = { // used when adding 3 pix period and extra char + 0x000,0x000,0x000,0x780,0x040,0x020,0x020,0x020, // "the upper left corner +// 0x020,0x020,0x040,0x780,0x000,0x000,0x000,0x000, // # the upper right corner + 0x1FC,0x1FC,0x1FC,0x1FC,0x1FC,0x1FC,0x1FC,0x000, // # box +// 0x000,0x000,0x000,0x00F,0x010,0x020,0x020,0x020, // $ lower left corner +// 0x070,0x0F8,0x1FC,0x1FC,0x1FC,0x0F8,0x070,0x000, // $ dot + 0x006,0x00C,0x018,0x030,0x060,0x0C0,0x180,0x000, // $ backslash + 0x30C,0x18C,0x0C0,0x060,0x030,0x318,0x30C,0x000, // % + 0x000,0x180,0x260,0x21C,0x26A,0x284,0x140,0x000, // & + 0x202,0x202,0x202,0x202,0x202,0x202,0x3FE,0x000, // ' battery Last empty + 0x000,0x000,0x0F8,0x1FC,0x306,0x202,0x000,0x000, // ( + 0x000,0x000,0x202,0x306,0x1FC,0x0F8,0x000,0x000, // ) + 0x000,0x18C,0x0D8,0x070,0x070,0x0D8,0x18C,0x000, // * x + 0x000,0x020,0x020,0x0F8,0x0F8,0x020,0x020,0x000, // + + 0x020,0x020,0x010,0x00F,0x000,0x000,0x000,0x000, // , the lower right corner + 0x000,0x020,0x020,0x020,0x020,0x020,0x020,0x000, // - + 0x000,0x000,0x300,0x300,0x000,0x000,0x000,0x000, // . + 0x180,0x0C0,0x060,0x030,0x018,0x00C,0x006,0x000, // / + 0x1FC,0x3FE,0x242,0x222,0x212,0x3FE,0x1FC,0x000, // 0 + 0x000,0x208,0x20C,0x3FE,0x3FE,0x200,0x200,0x000, // 1 + 0x304,0x386,0x2C2,0x262,0x232,0x31E,0x30C,0x000, // 2 + 0x104,0x306,0x222,0x222,0x222,0x3FE,0x1DC,0x000, // 3 + 0x060,0x070,0x058,0x24C,0x3FE,0x3FE,0x240,0x000, // 4 + 0x11E,0x21E,0x212,0x212,0x212,0x3F2,0x1E2,0x000, // 5 + 0x1F8,0x3FC,0x226,0x222,0x222,0x3E0,0x1C0,0x000, // 6 + 0x006,0x006,0x3C2,0x3E2,0x032,0x01E,0x00E,0x000, // 7 + 0x1DC,0x3FE,0x222,0x222,0x222,0x3FE,0x1DC,0x000, // 8 + 0x01C,0x23E,0x222,0x222,0x322,0x1FE,0x0FC,0x000, // 9 + 0x000,0x000,0x000,0x198,0x198,0x000,0x000,0x000, // : + 0x2FA,0x2FA,0x2FA,0x2FA,0x2FA,0x2FA,0x2FA,0x2FA, // ; battery body + 0x000,0x020,0x070,0x0D8,0x18C,0x306,0x202,0x000, // < + 0x090,0x090,0x090,0x090,0x090,0x090,0x000,0x000, // = + 0x000,0x202,0x306,0x18C,0x0D8,0x070,0x020,0x000, // > + //0x018,0x01C,0x004,0x344,0x364,0x03C,0x018,0x000, // ? + //0x07F,0x008,0x0D4,0x322,0x441,0x300,0x0C0,0x000, // ? Kv + 0x070,0x0F8,0x1FC,0x1FC,0x1FC,0x0F8,0x070,0x000, // ? dot + //0x1F8,0x104,0x272,0x272,0x2F2,0x284,0x078,0x000, // @ + 0x3FE,0x020,0x3FE,0x000,0x320,0x2A0,0x260,0x000, // @ Hz + 0x3F0,0x3F8,0x04C,0x046,0x04C,0x3F8,0x3F0,0x000, // A + 0x202,0x3FE,0x3FE,0x222,0x222,0x3FE,0x1DC,0x000, // B + 0x0F8,0x1FC,0x306,0x202,0x202,0x306,0x18C,0x000, // C + 0x202,0x3FE,0x3FE,0x202,0x306,0x1FC,0x0F8,0x000, // D + 0x202,0x3FE,0x3FE,0x222,0x272,0x306,0x38E,0x000, // E + 0x202,0x3FE,0x3FE,0x222,0x072,0x006,0x00E,0x000, // F + 0x0F8,0x1FC,0x306,0x222,0x222,0x1E6,0x3EC,0x000, // G + 0x3FE,0x3FE,0x020,0x020,0x020,0x3FE,0x3FE,0x000, // H + 0x000,0x000,0x202,0x3FE,0x3FE,0x202,0x000,0x000, // I + 0x1C0,0x3C0,0x200,0x202,0x3FE,0x1FE,0x002,0x000, // J + 0x202,0x3FE,0x3FE,0x030,0x0F8,0x3CE,0x306,0x000, // K + 0x202,0x3FE,0x3FE,0x202,0x200,0x200,0x300,0x000, // L + 0x3FE,0x3FE,0x01C,0x038,0x01C,0x3FE,0x3FE,0x000, // M + 0x3FE,0x3FE,0x01C,0x038,0x070,0x3FE,0x3FE,0x000, // N + 0x0F8,0x1FC,0x306,0x202,0x306,0x1FC,0x0F8,0x000, // O + 0x202,0x3FE,0x3FE,0x222,0x022,0x03E,0x01C,0x000, // P + 0x1FC,0x3FE,0x202,0x282,0x302,0x3FE,0x1FC,0x000, // Q + 0x202,0x3FE,0x3FE,0x022,0x062,0x3FE,0x39C,0x000, // R + 0x10C,0x31E,0x232,0x222,0x262,0x3CE,0x18C,0x000, // S + 0x000,0x00E,0x206,0x3FE,0x3FE,0x206,0x00E,0x000, // T + 0x1FE,0x3FE,0x200,0x200,0x200,0x3FE,0x1FE,0x000, // U + 0x07E,0x0FE,0x180,0x300,0x180,0x0FE,0x07E,0x000, // V + 0x0FE,0x3FE,0x380,0x1E0,0x380,0x3FE,0x0FE,0x000, // W + 0x306,0x3DE,0x0F8,0x020,0x0F8,0x3DE,0x306,0x000, // X + 0x000,0x01E,0x23E,0x3E0,0x3E0,0x23E,0x01E,0x000, // Y + 0x38E,0x3C6,0x262,0x232,0x31E,0x38E,0x000,0x000, // Z + 0x200,0x300,0x2C0,0x220,0x218,0x204,0x3FE,0x000, // [ Triangle + 0x000,0x022,0x042,0x1FE,0x3FE,0x240,0x220,0x000, // \ falling edge + 0x020,0x010,0x008,0x006,0x008,0x010,0x020,0x020, // ] Pointer + 0x000,0x220,0x210,0x3FC,0x3FE,0x012,0x022,0x000, // ^ rising edge + 0x000,0x200,0x200,0x200,0x200,0x200,0x200,0x000, // _ under the dash + 0x202,0x202,0x202,0x202,0x202,0x202,0x202,0x202, // ` battery itself empty + 0x1C0,0x3E8,0x228,0x228,0x1F8,0x3F0,0x200,0x000, // a + 0x202,0x3FE,0x1FE,0x220,0x220,0x3E0,0x1C0,0x000, // b + 0x1E0,0x3F0,0x210,0x210,0x210,0x330,0x120,0x000, // c + 0x000,0x1C0,0x3E0,0x220,0x222,0x3FE,0x3FE,0x000, // d + 0x1E0,0x3F0,0x250,0x250,0x250,0x370,0x160,0x000, // e + 0x000,0x220,0x3FC,0x3FE,0x222,0x002,0x004,0x000, // f + 0x130,0x378,0x248,0x248,0x3F8,0x1F8,0x000,0x000, // g + 0x202,0x3FE,0x3FE,0x020,0x010,0x3F0,0x3E0,0x000, // h + 0x000,0x000,0x200,0x3F6,0x3F6,0x200,0x000,0x000, // i + 0x000,0x100,0x300,0x210,0x3F6,0x1F6,0x000,0x000, // j + 0x202,0x3FE,0x3FE,0x062,0x0F0,0x398,0x308,0x000, // k + 0x000,0x000,0x202,0x3FE,0x3FE,0x200,0x000,0x000, // l + 0x3F8,0x3F8,0x018,0x3F0,0x018,0x3F8,0x3F0,0x000, // m + 0x008,0x3F8,0x3F0,0x008,0x008,0x3F8,0x3F0,0x000, // n + 0x000,0x1F0,0x3F8,0x208,0x208,0x3F8,0x1F0,0x000, // o + 0x208,0x3F8,0x3F0,0x248,0x048,0x078,0x030,0x000, // p + 0x030,0x078,0x048,0x248,0x3F8,0x3F8,0x200,0x000, // q + 0x208,0x3F8,0x3F0,0x218,0x008,0x018,0x030,0x000, // r + 0x000,0x110,0x338,0x268,0x248,0x3D8,0x190,0x000, // s + 0x010,0x010,0x1F8,0x3FC,0x210,0x310,0x100,0x000, // t + 0x1F8,0x3F8,0x200,0x200,0x1F8,0x3F8,0x200,0x000, // u + 0x000,0x0F8,0x1F8,0x300,0x300,0x1F8,0x0F8,0x000, // v + 0x0F8,0x3F8,0x300,0x180,0x300,0x3F8,0x0F8,0x000, // w + 0x208,0x318,0x1B0,0x0E0,0x1B0,0x318,0x208,0x000, // x + 0x038,0x278,0x240,0x240,0x240,0x1F8,0x0F8,0x000, // y + 0x318,0x388,0x2C8,0x268,0x238,0x318,0x000,0x000, // z + 0x0F8,0x088,0x38E,0x022,0x2FA,0x2FA,0x2FA,0x2FA, // { battery head + 0x000,0x000,0x000,0x3FE,0x3FE,0x000,0x000,0x000, // | + 0x2FA,0x2FA,0x2FA,0x2FA,0x2FA,0x202,0x3FE,0x000, // } battery last + 0x0F8,0x088,0x38E,0x202,0x202,0x202,0x202,0x202, // ~ battery empty head + //0x300,0x300,0x000}; // 3 pix wide proportional period (#127) + 0x300,0x300,0x000,0x000,0x000,0x000,0x000,0x000, // 3 pix wide proportional period (#127) + 0x03C,0X00A,0x03C,0x000,0x3E0,0x220,0x1C0,0x000, //"ad" i2c address word id (#128) + 0x000,0x100,0x200,0x7FC,0X200,0X100,0X000,0X000};// down arrow (#129) + + //0x000,0x004,0x002,0x1FF,0X002,0X004,0X000,0X000};// up arrow (#129) + +char HexLookup[3]; + +sc8 DbScale[29]= +{-40,-37,-35,-33,-32,-31,-30,-29,-28,-27,-27,-26,-25,-25,-24,-24,-23,-23,-22,-22, +-21,-21,-21,-20,-20,-20,-20,-19,-19}; + +u16 Color[16] = { CYAN, // #0 TRACK1 + YEL, // #1 TRACK2 + PURPL, // #2 TRACK3 + GRN, // #3 TRACK4 + WHT, // #4 VERNIE + BLACK, // #5 SCRN + ORANGE, // #6 X_POSI + //BLUE, // #7 TRIGG + PURPL, // #7 TRIGG + CYAN, // #8 VERNIE + GRAY, // #9 GRID + WHT, // #10 TEXT + //GRN, // #11 TEXT2 + //0x47E8, // #11 TEXT2 (bright green with 1/4 blue and red + 0x87F0, // #11 TEXT2 (bright green with 1/2 blue and red + BLUE, // #12 TEXT3 + //GRAY, // #13 BLOCK + 0x7BEF, // #13 DARK GRAY + YEL_, // #14 SIDE + RED }; // #15 NOTE + +trigg V_Trigg[4] = {// Value, Flag:( HID=0x04, UPDAT=0x02 ) + { 175, UPDAT + HID }, + { 116, UPDAT }, + { 75, UPDAT + HID }, + { 35, UPDAT + HID }, + }; + +u16 LCD_Buffer[2][240]; +u16 Base4Buffer[201]; +u16 Base3Buffer[201]; +u16 Base2Buffer[201]; + +/******************************************************************************* + Get_TAB_8x11 +*******************************************************************************/ +u16 Get_TAB_8x11(u8 Code, u8 Row) +{ + return Char_TAB_8x11[((Code-0x22)*8)+Row]; +} +/******************************************************************************* + Print_Str: +*******************************************************************************/ +void Print_Str(u16 x0, u16 y0, u16 Type, u8 Mode, char *s) +{ + signed short i, j, b; + __LCD_Set_Block(x0, LCD_X2, y0, y0+10); + + if(SkipFirstRow==0){ + for (j=0; j<11;++j){ + if(Mode == 0) __LCD_SetPixl(Color[Type & 0x0F]); //Normal replace Display + else __LCD_SetPixl(Color[Type >> 0x8]); //Inverse replace Display + } + x0++; // a string to add a blank row + } + + while (*s!=0) { + for(i=0;i<8;++i){ + if((*s==0x20)||(*s==0x21)) b = 0x0000; + else b = Get_TAB_8x11(*s, i); + if((*s==0x21)&&(i==4)) break; + for(j=0;j<11;++j){ + if((b << j)& 0x400) { + if(Mode == 0) __LCD_SetPixl(Color[Type >> 0x8]); + else __LCD_SetPixl(Color[Type & 0x0F]); + } else { + if(Mode == 0) __LCD_SetPixl(Color[Type & 0x0F]); + else __LCD_SetPixl(Color[Type >> 0x8]); + } + } + } + if(*s==0x21) x0 +=4; // display position horizontally +4 ("!" character - shift by 1/2 a character) + else x0 += 8; // display position horizontally +8 + ++s; // string pointer +1 + } + __LCD_Set_Block(LCD_X1,LCD_X2,LCD_Y1,LCD_Y2); // restore the full-size window +} + +void PrintConfigName(void){ +char Str[2]={0,0}; +u8 i; +u8 j=0; + + if((_4_source!=SPEC_A)&&(_4_source!=SPEC_B)&&(ListOverride)){ + for(i=204;i>126;i-=11){ + Str[0]=ConfigFileName[j++]; //print config name + PrintText(0,i,Str); + } + } + __LCD_Set_Block(LCD_X1,LCD_X2,LCD_Y1,LCD_Y2); // restore the full-size window +} + + +void PrintText(u16 x, u8 y,char *s){ +u8 i; +u16 j,b; + + __LCD_Set_Block(x,x+6,y,y+10); + + while (*s!=0) { + for(i=0;i<7;++i){ + if((*s==32)||(*s==95)) b = 0x0000; + else b = Get_TAB_8x11(*s, i); + + for(j=0;j<11;++j){ + if((b << j)& 0x400) { + __LCD_SetPixl(WHT); + } else { + __LCD_SetPixl(BLACK); + } + } + + } + x += 8; // display position horizontally +8 + ++s; // string pointer +1 + } +} + + +/******************************************************************************* +Print_Str2: +*******************************************************************************/ +void Print_Str2(u16 x0,u16 x1,u16 y0, u16 Type, u8 Mode, char *s,u8 LeadingBlanks,u8 TrailingBlanks) +{ +u8 LeadingLine=0; + + signed short i, j, b; + u8 xm, ym; + __LCD_Set_Block(x0, x1, y0, y0+21); + + if(LeadingBlanks>10){ //special case to add 1 leading line + LeadingBlanks-=10; + LeadingLine=1; + } + + for (i=0;i> 0x8]); //Inverse replace Display + } + x0+=2; // a string to add a blank row + } + while (*s!=0) { + for(i=0;i<8;++i){ + if((*s==0x20)||(*s==0x21)) b = 0x0000; + else b = Get_TAB_8x11(*s, i); + if((*s==0x21)&&(i==4)) break; + for(xm=0;xm<2;++xm){ + for(j=0;j<11;++j){ + if((b << j)& 0x400) { + if(Mode == 0) for(ym=0;ym<2;++ym) __LCD_SetPixl(Color[Type >> 0x8]); + else for(ym=0;ym<2;++ym) __LCD_SetPixl(Color[Type & 0x0F]); + } else { + if(Mode == 0) for(ym=0;ym<2;++ym) __LCD_SetPixl(Color[Type & 0x0F]); + else for(ym=0;ym<2;++ym) __LCD_SetPixl(Color[Type >> 0x8]); + } + } + } + } + if(*s==0x21) x0 +=8; // display position horizontally +4 ("!" character - shift by 1/2 a character) + else x0 += 16; // display position horizontally +8 + ++s; // string pointer +1 + } + + for (i=0;i Now done externally +} + + + +/*******************************************d************************************ + Draw_Row : to ease the DMA conflict, in two buffers alternately +*******************************************************************************/ +void Draw_Row(u16 Row) +{ + u8 i, y[8], Dot_Hide[8]; //,Zm=0,Zn=0; + s16 Tmp, m, n; + + if((_T_base<11)&&((ClearLeadingEdge)||(_Mode==NORHLD))){ + if(OsBufferLogicFlag){ + skip = MIN_X+JumpCnt-(StartOffset+1); + }else{ + skip = MIN_X+JumpCnt-_X_posi.Value; + if(OsChartFlag)skip--; + } + }else skip=0x7FFF; + + if(ChartLogic())ChartIndex=(JumpCnt+11)-_X_posi.Value;else ChartIndex=0x7FFF; + +if((Row > MIN_X)&&(Row <= MAX_X)){ // waveform display data preprocessing + m = (Row - MIN_X-1)* 4; + n = (Row - MIN_X) * 4; + + for(i = 0; i < 8; i += 2) { + if( ((OsBufferLogicFlag)||(OsChartFlag)) &&(i>2))break; // Digital channels cannot be displayed in OS mode + Dot_Hide[i] = 0; + y[i] = TrackBuff[m + i/2]; // endpoint to extract + y[i+1] = TrackBuff[n + i/2]; + + if(y[i]>199)y[i]= 199; // bounds + else if(y[i]<1)y[i]=1; + if(y[i+1]>199)y[i+1]=199; + else if(y[i+1]<1)y[i+1]=1; + + if(y[i] == y[i+1]){ + if((y[i] == Y_BASE+1)||(y[i] == Y_SIZE-1)){ + if( (((!OsBufferLogicFlag)||(OSAvg))&&(!OsChartFlag)) ||(y[i]==TrackBuff[m + 2+(i/2)])|| + ((y[i]==1)&&(TrackBuff[m + 2+(i/2)]==0)))Dot_Hide[i] = 1; //regular mode or not being drawn down by OS data + }else{ // else if((FPGAosFlag==0)||(!OsBufferLogicFlag)){ + if((y[i] >= Y_BASE+2)&&(Hbold<1)) y[i] -= 1; // alt config, allows OS display bold on display 2 & 3 + if((y[i+1] <= Y_BASE+Y_SIZE-2)&&(Hbold<2)) y[i+1] += 1; // non OS modes: 1, 2 or 3 bold lines + //if((y[i] >= Y_BASE+2)&&(Hbold<2)) y[i] -= 1; // OS modes: bold only on 3 + //if((y[i+1] <= Y_BASE+Y_SIZE-2)&&(Hbold<1)) y[i+1] += 1; + //if((y[i+1] <= Y_BASE+Y_SIZE-2)&&((Hbold<1)||((OsBufferLogicFlag)&&(OS_Bold))))y[i+1] += 1;//Hyst OS_Bold flag for dir os bold on 2 + } + } + + if(y[i] > y[i+1]){ // order of + Tmp = y[i+1]; y[i+1]= y[i]; y[i]= Tmp; + } + if( ( ((OsBufferLogicFlag)&&(!OSAvg))||(OsChartFlag) ) &&(Row>(MIN_X+1))){ + if(TrackBuff[m + 2+(i/2)] MIN_X)&&(Row < MAX_X)){ + LoadBuffer(Row,1,y,Dot_Hide,1); +//------------------------- Draw the Trigg Vernie data ------------------------- + if (_Mode!=SCAN){ + + for(i=0;i<4;i++){ + if((Title[TRIGG][SOURCE].Value == i)&&(Title[i][SOURCE].Value != HIDE)) + LCD_Buffer[1][V_Trigg[i].Value] |= Color[i]; + } + + if(Title[TRIGG][SOURCE].Value == 4){ //display both trigger verniers in alt mode + LCD_Buffer[1][V_Trigg[TRACK1].Value] |= Color[0]; + LCD_Buffer[1][V_Trigg[TRACK2].Value] |= Color[1]; + } + +//------------------------- Draw the X Vernie data ----------------------------- + Tmp2=ScaleXposi(); + + if(Tmp2 > MIN_X) { + if((Row == Tmp2)&&((_X_posi.Flag & HID)== 0)){ + for(i = 1; i < Y_SIZE; i+=3) LCD_Buffer[1][i] |= ORANGE; //X vernier + } + if((Row == Tmp2-1)||(Row == Tmp2+1)){ //mid portion for marks, aligned with borders, 2 outside pix + LCD_Buffer[1][Y_SIZE] = ORANGE; + LCD_Buffer[1][Y_BASE] = ORANGE; + } + if(Row == Tmp2)VernierMark(1,ORANGE); + } + }//if mode !scan + + Tmp = MIN_X + Title[T_VERNIE][T1].Value; + if((Row == Tmp)&&((Title[T_VERNIE][T1].Flag & HID)== 0)){ + for(i = 1; i < Y_SIZE; i+=3) LCD_Buffer[1][i] |= WHT; //T1 vernier + } + if((Row == Tmp-1)||(Row == Tmp+1)){ //mark mid portions minus mid + LCD_Buffer[1][Y_SIZE] = WHT; + LCD_Buffer[1][Y_BASE] = WHT; + } + if(Row == Tmp)VernierMark(1,WHT); + Tmp = MIN_X + Title[T_VERNIE][T2].Value; + if((Row == Tmp)&&((Title[T_VERNIE][T2].Flag & HID)== 0)){ + for(i = 1; i < Y_SIZE; i+=3) LCD_Buffer[1][i] |= WHT; + } + if((Row == Tmp-1)||(Row == Tmp+1)){ + LCD_Buffer[1][Y_SIZE] = WHT; + LCD_Buffer[1][Y_BASE] = WHT; + } + if(Row == Tmp)VernierMark(1,WHT); + }else{ //if row>min x & < max x //CHANGED +//------------------------- Draw the Y Vernie data ----------------------------- + + for(Tmp=-1;Tmp<2;Tmp++)LCD_Buffer[1][Title[V_VERNIE][V1].Value+Tmp] |= WHT; + for(Tmp=-1;Tmp<2;Tmp++)LCD_Buffer[1][Title[V_VERNIE][V2].Value+Tmp] |= WHT; + } + if((((Det&1)&&(_1_source))||((Det&2)&&(_2_source)))&&(ShowFFT==0))DisplayDbScale(Row,1,1); + LoadFFTbuffer(Row,1); + if(Sweep==1)DisplayDetFrqn(Row,1);else EnableMeterCalc=0; + if(!((Current==OUTPUT)&&(_Det==1)&&(_Kind==8)&&((Key_Buffer==K_INDEX_DEC)||(Key_Buffer==K_INDEX_INC)))){ + if(UartLogic())PrintUart(Row,1,0); + if(i2cLogic())PrintUart(Row,1,1); + if(SpiLogic())PrintUart(Row,1,2); + } + + if((Row<192)&&(ShowFFT==0)&&(((CursorDisplayTimer)||(FlagMeter))&&(EnableCursorDisplay))) + DisplayCursorValues(Row,1); + if((Row>311)&&(CursorDisplayTimer)) + DisplayDeltaValues(Row,1); + + if ((Current==9)&&(_Det==3))PrintDir(Row,1,0); + __LCD_Copy(LCD_Buffer[1], Y_SIZE+1); // Odd row Transitive + +} else { // Even row process + +//----------------------- Fill the row base data ------------------------------- + + if(Row+1 == MAX_X)Base1(1); + else if(Row+1 == MIN_X); + else if((Row+1 - MIN_X)%30 == 0) __Row_Copy(Base4Buffer, LCD_Buffer[1]); + else if((Row+1 - MIN_X)%6 == 0) __Row_Copy(Base3Buffer, LCD_Buffer[1]); + else __Row_Copy(Base2Buffer, LCD_Buffer[1]); + + +//------------------------- Draw the Y Vernie data ----------------------------- + if((Row==MIN_X+1)||(Row==MAX_X-1)){ + LCD_Buffer[0][Title[V_VERNIE][V1].Value] |= WHT; + LCD_Buffer[0][Title[V_VERNIE][V2].Value] |= WHT; + } + if((Title[V_VERNIE][V1].Flag & HID)== 0) + LCD_Buffer[0][Title[V_VERNIE][V1].Value] |= WHT; + if((Title[V_VERNIE][V2].Flag & HID)== 0) + LCD_Buffer[0][Title[V_VERNIE][V2].Value] |= WHT; +//------------------------- Draw the Curve data -------------------------------- + if((Row > MIN_X)&&(Row < MAX_X))LoadBuffer(Row,0,y,Dot_Hide,1); +//------------------------- Draw the X Vernie data ----------------------------- + if (_Mode!=SCAN){ + Tmp2=ScaleXposi(); + + if(Tmp2 > MIN_X) { + if((Row == Tmp2)&&((_X_posi.Flag & HID)== 0)){ + for(i = 1; i < Y_SIZE; i+=3) LCD_Buffer[0][i] |= ORANGE; + } + if((Row == Tmp2-1)||(Row == Tmp2+1)){ + LCD_Buffer[0][Y_SIZE] = ORANGE; + LCD_Buffer[0][Y_BASE] = ORANGE; + } + if(Row == Tmp2)VernierMark(0,ORANGE); + } + } + + Tmp = MIN_X + Title[T_VERNIE][T1].Value; + if((Row == Tmp)&&((Title[T_VERNIE][T1].Flag & HID)== 0)){ + for(i = 1; i < Y_SIZE; i+=3) LCD_Buffer[0][i] |= WHT; + } + if((Row == Tmp-1)||(Row == Tmp+1)){ + LCD_Buffer[0][Y_SIZE] = WHT; + LCD_Buffer[0][Y_BASE] = WHT; + } + if(Row == Tmp)VernierMark(0,WHT); + Tmp = MIN_X + Title[T_VERNIE][T2].Value; + if((Row == Tmp)&&((Title[T_VERNIE][T2].Flag & HID)== 0)){ + for(i = 1; i < Y_SIZE; i+=3) LCD_Buffer[0][i] |= WHT; + } + if((Row == Tmp-1)||(Row == Tmp+1)){ + LCD_Buffer[0][Y_SIZE] = WHT; + LCD_Buffer[0][Y_BASE] = WHT; + } + if(Row == Tmp)VernierMark(0,WHT); + + if((((Det&1)&&(_1_source))||((Det&2)&&(_2_source)))&&(ShowFFT==0))DisplayDbScale(Row,0,1); + LoadFFTbuffer(Row,0); + if(Sweep==1)DisplayDetFrqn(Row,0);else EnableMeterCalc=0; + if(!((Current==OUTPUT)&&(_Det==1)&&(_Kind==8)&&((Key_Buffer==K_INDEX_DEC)||(Key_Buffer==K_INDEX_INC)))){ + if(UartLogic())PrintUart(Row,0,0); + if(i2cLogic())PrintUart(Row,0,1); + if(SpiLogic())PrintUart(Row,0,2); + } + + if((Row<192)&&(ShowFFT==0)&&(((CursorDisplayTimer)||(FlagMeter))&&(EnableCursorDisplay))) + DisplayCursorValues(Row,0); + if((Row>311)&&(CursorDisplayTimer)) + DisplayDeltaValues(Row,0); + + if ((Current==9)&&(_Det==3))PrintDir(Row,0,0); + __LCD_Copy(LCD_Buffer[0], Y_SIZE+1); // Even row Transitive + + }//even row process + + }else if((_State.Value==0)&&(Row > MIN_X)&&(Row < MAX_X)){ //persistence mode + if((_T_base>10)||(Row!=skip)){ + if(ClearPerst!=1)LoadBuffer(Row,0,y,Dot_Hide,0); //ClearPerst==1 denotes variable timer to display after loading X frames + __Point_SCR(Row, MIN_Y); + } + LoadFFTbuffer(Row,0); + } +} + +/***************u16 Color[16] = { CYAN, // #0 TRACK1 + YEL, // #1 TRACK2 + PURPL, // #2 TRACK3 + GRN, // #3 TRACK4 + WHT, // #4 VERNIE + BLACK, // #5 SCRN + ORANGE, // #6 X_POSI + BLUE, // #7 TRIGG + CYAN, // #8 VERNIE + GRAY, // #9 GRID + WHT, // #10 TEXT + GRN, // #11 TEXT2 + BLUE, // #12 TEXT3 + GRAY, // #13 BLOCK + YEL, // #14 SIDE + RED }; // #15 NOTE +**************************************************************** + Draw_Window : +*******************************************************************************/ +void Draw_Window(void) +{ + s32 Tmp; + u16 Row,i,Offset,SpecLimit; + s16 h=0; + u16 TrackColor=0; + u8 j,end=0; + + if(FlagMeter)Limit=213;else Limit=299; + ListBottom=174+11; + for(i=0;i<15;i++){if(Label[i][0]==0)break;else ListBottom-=11;} + Base1(1); + __Row_DMA_Ready(); + __Row_Copy(Base2Buffer, LCD_Buffer[0]); + + //if(_4_source>13)COLOR_INDEX=0x0500; else COLOR_INDEX=0x0501; //sets fft values display to source channel color (need to change uc) + + if(((ShowFFT==1)||(_4_source==SPEC_A))&&(_Mode!=X_Y)){ + + if(_T_base==8){ //special case to align with data flow and other timebases + Delayms(2); + Count_FPS++; + Delayms(4); + } + + if(DownConvertMode==0){ + FFTflag=1; + Display_Value(FRQ); //calculate NFreq using meter routine, sets N_UNIT and ShiftDigits for proper display + FFTflag=0; + } + + PeakFreq = 2; //Called for as array index for LCD_Buffer @ -2. Less than 2 could put index out of bounds + imax = 0; + for (i=1; i < FFTSize/2; i++) { + if (PeakFreq < fi[i]) { + PeakFreq= fi[i] ; + imax = i; + } + } + + if((AutoFFT==1)&&((EnableFFT==2)||(_T_base>7)||(freerun))){ //auto fft is on if =1 + if(FFTGain>7)FFTGain=7; //auto gain limit + if((PeakFreq==198)&&(FFTGain>0))FFTGain--; + else{ + if(PeakFreq<100){ + if(FFTGain<7)FFTGain++; + if((PeakFreq<78)&&(FFTGain<7))FFTGain++; + } + } + } + if(EnableFFT==2)EnableFFT=0; + + if(DownConvertMode==0){ + Int2Str(NFreqStr, NFreq,N_UNIT, 4, UNSIGN,ShiftDigits); + Int2Str(FreqDivStr, ((NFreq / FFTBins) * 30),N_UNIT, 4, UNSIGN,ShiftDigits); + + Tmp=(NFreq/FFTBins)*_T1; + if((ChartLogic())&&(Tmp<1000))Tmp=0x80000000; + Int2Str(FreqT1Str, Tmp,N_UNIT, 4, UNSIGN,ShiftDigits); + + Tmp=(NFreq/FFTBins)*imax; + if((ChartLogic())&&(Tmp<1000))Tmp=0x80000000; + if (imax>0)Int2Str(PeakFreqStr, Tmp, N_UNIT, 4, UNSIGN,ShiftDigits); + } + + } + + + if ((_Mode!=X_Y)&&(((_4_source!=SPEC_A)&&(_4_source!=SPEC_B))||(ChartLogic()))){ + Count_FPS++; + if((_Mode==NORHLD)&&(PerstFrameNumber>0)){ + if(ClearPerst==0){ + if(FrameCount>PerstFrameNumber){ + FrameCount=0; + ClearPerst=1; + //if(PerstFrameNumber>50)PersHoldTimer=50;else PersHoldTimer=PerstFrameNumber; //adds delay after x frames displayed + PersHoldTimer=0; //no delay + }else if(FrameEndFlag)FrameCount++; + } + if((ClearPerst==1)&&(PersHoldTimer==0))ClearPerst=2; + }else ClearPerst=0; + + if(_4_source>11) NFreqParse(1,0); + + TcurDelta=(((_T2-_T1)*_Kp1)+512)/1024; + + if(!((Current==OUTPUT)&&(_Det==1)&&(_Kind==8)&&((Key_Buffer==K_INDEX_DEC)||(Key_Buffer==K_INDEX_INC)))){ + if(UartLogic())Uart(); + if(i2cLogic())i2c(); + if(SpiLogic())Spi(); + } + + for(Row = MIN_X; Row <= MAX_X; ++Row){ + + if(!(OsBufferLogicFlag||OsChartFlag)){ + + if (Row<(discard + MIN_X)){ //blanks first few pixels of traces to eliminate noise + Color[TR_1]=0x0000; //process makes these into a hor line so "low brightness" + Color[TR_2]=0x0000; //in draw row does not turn them on + } + + if (Row>(404-Rdiscard)){ //post-signal blanking for dig ch triggering jitter stabilization + Color[TR_1]=0x0000; + Color[TR_2]=0x0000; //404 aligns with x_size @ 392 and IP routine bailing out @ 392 + Color[TR_3]=0x0000; + Color[TR_4]=0x0000; + } + + if ((Row>382)&&(Row<398)){ //post trace blanking of detector trace + if((Det&1)&&_1_source)Color[TR_1]=0x0000; + if((Det&2)&&_2_source)Color[TR_2]=0x0000; + } + + if ((Title[TRIGG][SOURCE].Value<2)||(Title[TRIGG][SOURCE].Value==4))end=discard+5; else end=discard; //was 4, changed to 5 + + if (Row<(MIN_X+end)){ //blanks first pixels shifted in dig channels to align with analog chs + Color[TR_3]=0x0000; + } + + if ((_4_source==A_add_B)||(_4_source==A_sub_B))end=discard; + + if (Row<(MIN_X+end)){ //blanks first pixels shifted in dig channels to align with analog chs + Color[TR_4]=0x0000; + } + + } //if !OsBufferLogicFlag + + Draw_Row(Row); //Modo oscilloscopio + if((Row<(discard+5+MIN_X))||(Row>(404-Rdiscard))) { //was4, changed to 5 + Color[TR_1]=0xFFE0; //return to correct colors + Color[TR_2]=0x07FF; + Color[TR_3]=0xF81F; + Color[TR_4]=0x07E0; + } + + if ((Row>382)&&(Row<398)){ //post trace blanking of detector trace, return to correct colors + if ((Det&1)&&_1_source)Color[TR_1]=0xFFE0; + if((Det&2)&&_2_source)Color[TR_2]=0x07FF; + } + + } //end for loop + } //if mode !XY... + + if(ClearPerst==2)ClearPerst=0; + + if (_Mode==X_Y){ + PrintConfigName(); + Count_FPS++; + FactorX=((s16)OffsetX-100)+((-ADCoffset)+Ka1[_A_Range]); + FactorY=((s16)OffsetY-100)+((-ADCoffset)+Kb1[_B_Range]); + FactorY13=FactorY+13; //for direct screen access, need offset 13 + if(EditListActive(1))XYLimit=310;else XYLimit=234; + for(Row = MIN_X; Row <= MAX_X; ++Row) LoadXYBuffer(Row); + __LCD_DMA_Ready(); + __Row_DMA_Ready(); + if((XYper)&&(EditListActive(1)))PrintDir(0,0,1); + InitXY=0; + } + +if(((_4_source==SPEC_A)||(_4_source==SPEC_B))&&(!ChartLogic())){ + if((_Mode!=X_Y)&&(_State.Value==0)&&((FrameEndFlag==1)||((SpecFrameCount>FrameCountRef[_T_base])&&((_T_base>10) ||(_Mode==SCAN) || + ((FrameEndFlag==0)&&(__Get(FIFO_START)==0)))))){ //spectrograph/MAP modes + + if(SpecMode>0){ + if(_1_source){h=(a_Max-a_Min)/(4/SpecMode);TrackColor=CYAN_;} //scale and remove offset using last frame + else if(_2_source){h=(b_Max-b_Min)/(4/SpecMode);TrackColor=YEL_;} //done vars (not accumulated) + if(h<0)h=-h; + } + if((FrameEndFlag==0)&&(_Mode!=AUTO)&&(_Mode!=SCAN)&&(__Get(FIFO_START)==0)){ + for (i=0; i(ListBottom+MIN_Y))SpecLimit=Limit;else SpecLimit=X_SIZE; + }else SpecLimit=X_SIZE; + + for (i=0; iMIN_X)&&(iSpecLimit)continue; + if(_1_source)__LCD_SetPixl(ColorIndexGen(TrackBuff[(i-6)*4])); + else if(_2_source)__LCD_SetPixl(ColorIndexGen(TrackBuff[((i-6)*4)+1])); + }else if((i>3)&&(i<9)&&(SpecLine>(MIN_Y+1))){ + __LCD_SetPixl(0); + DrawPixel(i,SpecLine-1,YEL_); + if(_T_base>9)DrawPixel(i,SpecLine-2,YEL_); + }else __LCD_SetPixl(0); + } + + if(FlagMeter==0)for(i=397;i<400;i++)DrawPixel(i,SpecLine,0); + if((SpecLine==MIN_Y)||(SpecLine==MAX_Y))for(i=0;i>>> need to reset specrow @ 25 every time mode is engaged + + ClearScreenArea(0,26,12,214); + UpdateScale=0; + + Print_Str(0,193+MIN_Y,0x050E,INV,"sec"); + if(_T_base<2)Offset=128;else Offset=512; + for(i=34;i<195;i+=34){ //draw freq scale in spec mode + for(j=20;j<25;j++)DrawPixel(j,i+MIN_Y,YEL_); + Tmp=((NFreq+Offset)/255)*i; + Int2Str(NFreqStr,Tmp,N_UNIT, 4, UNSIGN,ShiftDigits); + NFreqParse(0,1); + if(Nfreq[2]==46){Nfreq[2]=0;j=4;}else j=0; //remove trailing periods, shift over + Print_Str(j,i+(MIN_Y+2),0x0508,INV,Nfreq); + Print_Str(4,i+3,0x0508,INV,Nsuffix); + } + } + if(SpecRow==25)SecondsTick=0; + if(AutoFFT==0){for(i=0;i<200;i++){if(fi[i]<51){fi[i]=(fi[i]*fi[i]*fi[i])/2500;}}} // x^3/50^2 noise suppression in log mode + + for (i=Y_BASE+1;i<200;i++) { + if(SpecMode==0){ + LCD_Buffer[SpecRow & 1][i] = ColorIndexGen(fi[i-Y_BASE]); //spec display only + }else if(SpecMode==1){ + if((i>=(150-h))&&(i<=(150+h))) //spec + envelope display(1/2size) + LCD_Buffer[SpecRow & 1][i] = TrackColor; + else LCD_Buffer[SpecRow & 1][i] = ColorIndexGen(fi[i-Y_BASE]); + }else{ + if((i>=(100-h))&&(i<=(100+h)))LCD_Buffer[SpecRow & 1][i] = TrackColor; //envelope display only full size + else LCD_Buffer[SpecRow & 1][i] = BLACK; + } + } + + if ((EditListActive(1))&&(SpecRow>Limit)){ + PrintDir(SpecRow,SpecRow&1,0); + } + + if(SpecRow5)&&(SecondsTick==0)&&(SpecRow MAX_X) SpecRow = 25; + } + + if(_Mode==AUTO)SpecFrameCount=3;else SpecFrameCount=0; //reset interrupt based frame timing + } //if mode != xy +} // is in spec a or b + + if((FrameEndFlag)&&(ResetEnableFFT==0))EnableFFT=1; + ResetEnableFFT=0; + FrameEndFlag=0; + RowMemPeak = RowMem; + + __LCD_DMA_Ready(); + __Row_DMA_Ready(); + + if ((Current==9)&&(_Det==3)&&((ListLogic())||(_Mode==NORHLD)))PrintDir(0,0,1); + +} +/******************************************************************************* + Draw_Mark : Routine per un marcatore laterale +*******************************************************************************/ +void Draw_Mark(u16 m, u16 n) +{ + u16 i, j, Tmp; + + V_Trigg[2].Value=Title[2][POSI].Value + 10; // show ch3 and 4 trigger points at their actual values + V_Trigg[3].Value=Title[3][POSI].Value + 10; + + if(m < 4) { if((Title[m][POSI].Value > 200-3)||(Title[m][POSI].Value <3))return; } //shut off at bottom too + else { if((V_Trigg[n].Value > 200-3)||(V_Trigg[n].Value <3))return; } + + for(i = 0; i <= 10; ++i){ + if(i < 7){ + if(m < 4){ //Y position mark + Tmp = Mark_TAB[m][i]; + __Point_SCR(i, Title[m][POSI].Value +(MIN_Y-4)); + } else { + Tmp = Mark_TAB[4][i]; + __Point_SCR(i, V_Trigg[n].Value +(MIN_Y-4)); //Trigg vernier position mark + } + for(j = 0; j < 8; ++j){ + if(Tmp & 1) __LCD_SetPixl(BLACK); + else __LCD_SetPixl(Color[n]); + Tmp >>= 1; + } + __LCD_SetPixl(Color[n]); + } else { + if(m < 4){ + __Point_SCR(i, Title[m][POSI].Value +(MIN_Y-10)+ i); + for(j=Title[m][POSI].Value+(MIN_Y-10)+i;j<(Title[m][POSI].Value+(MIN_Y+11)-i);++j) //Y position mark + __LCD_SetPixl(Color[n]); + } else { + __Point_SCR(i, V_Trigg[n].Value +(MIN_Y-10)+ i); + for(j=V_Trigg[n].Value+(MIN_Y-10)+i;j<(V_Trigg[n].Value+(MIN_Y+11)-i);++j) //Trigg vernier position mark + __LCD_SetPixl(Color[n]); + } + } + } +} +/******************************************************************************* + Update_Mark : Disegna Marcatori laterali +*******************************************************************************/ +void Update_Mark(void) +{ + s16 i, Tmp; + u8 j=0; + __Row_DMA_Ready(); + + ClearScreenArea(0,11,MIN_Y-2,MAX_Y+3); + + if(ConfNameTimer>0)PrintConfigName(); //marks cover text + + for(i=0;i<4;i++){ + if(Title[i][SOURCE].Value!=HIDE)Draw_Mark(i,i); // Display Track mark + if(_Tr_source==i)Draw_Mark(TRIGG,i); // Display Trigg mark + } + if(_Tr_source == 4) { + Draw_Mark(TRIGG, TRACK1); // Display Trigg1 mark + Draw_Mark(TRIGG, TRACK2); // Display Trigg2 mark + } + if(SpiLogic()){ + if(_1_source)Draw_Mark(TRIGG, TRACK1); // Display Trigg marks in spi mode + if(_2_source)Draw_Mark(TRIGG, TRACK2); + } + if(i2cLogic()){ + if(_1_source)Draw_Mark(TRIGG, TRACK1); // Display Trigg marks in i2c mode + } + + if(ConfNameTimer==0)PrintConfigName(); //text covers marks + + __Point_SCR(MAX_X+1, MIN_Y-2); //up/down 1 more as above + for(j = MIN_Y-2; j < MAX_Y+3; ++j) __LCD_SetPixl(BLACK); // Clear next to last row + __Point_SCR(MAX_X+2, MIN_Y-2); + for(j = MIN_Y-2; j < MAX_Y+3; ++j) __LCD_SetPixl(BLACK); // Clear last row + for(i = MIN_X; i <= MAX_X+1; ++i)DrawBase(i,BLACK); + + __Point_SCR(MIN_X-1, Title[V_VERNIE][V1].Value +(MIN_Y - 2)); //draw "base" of V vernier marks + for(i = 0; i < 5; ++i) __LCD_SetPixl(WHT); + __Point_SCR(MIN_X-1, Title[V_VERNIE][V2].Value +(MIN_Y - 2)); + for(i = 0; i < 5; ++i) __LCD_SetPixl(WHT); + __Point_SCR(MAX_X+1, Title[V_VERNIE][V1].Value +(MIN_Y - 2)); + for(i = 0; i < 5; ++i) __LCD_SetPixl(WHT); + __Point_SCR(MAX_X+1, Title[V_VERNIE][V2].Value +(MIN_Y - 2)); + for(i = 0; i < 5; ++i) __LCD_SetPixl(WHT); + + Tmp2=ScaleXposi(); + + if(Tmp2 > MIN_X){ //X position trigger point vernier "base" marks + for(i = Tmp2 - 2; i <= Tmp2 + 2; ++i)DrawBase(i,ORANGE); + } + Tmp = MIN_X + Title[T_VERNIE][T1].Value; //T vernier base marks + for(i = Tmp - 2; i <= Tmp + 2; ++i)DrawBase(i,WHT); + Tmp = MIN_X + Title[T_VERNIE][T2].Value; + for(i = Tmp - 2; i <= Tmp + 2; ++i)DrawBase(i,WHT); +} +/******************************************************************************* + Update_View_Area: Disegna rettangolo con zig zag posizione buffer +*******************************************************************************/ +void Update_View_Area(void) +{ + s16 i, j, k; + u16 color; + + for(i=89;i<310;i++){ + __Point_SCR(i, 0); + for(j=0; j<12; ++j) __LCD_SetPixl(ORANGE); + if(i==90)i+=217; + } + + if(OSBuffer==0)color=ORANGE; else{ + if(OSAvg)color=GRN;else{ + if(FPGAosFlag)color=BLUE; else color=RED; + } + } + + for(i=91; i<307; i+=8){ + for(j=0; j<8; ++j){ + __Point_SCR(i+j, 0); + for(k=0; k<12; ++k){ + if((0x01 << k)& RULE_BASE[j])__LCD_SetPixl(color); + else __LCD_SetPixl(BLACK); + } + } + } + __Point_SCR(307,0); + for (i=0;i<12;i++) __LCD_SetPixl(BLACK); + + if (((FlagFrameMode ==1)&&(_Mode!=SGL))||(OSBuffer)) { + + if(OSBuffer==0)color=WHT; else color=ORANGE; + __Point_SCR(0 + 91 , 0); // disegna rettangolo per buffer ridotto draw rectangle to buffer reduced + for(j=0;j<9;++j) __LCD_SetPixl(color); + __Point_SCR(15 + 91 + 200, 0); + for(j=0;j<9;++j) __LCD_SetPixl(color); + for(i=0;i<216;++i){ + DrawPixel(i + 91,0,color); + DrawPixel(i + 91,9,color); + } + + if ((Options&1)>0) { + if (((_Mode==NORH)||(_Mode==NORHLD)||(_Mode==NORC))&&(_T_base < 10)&&(!OsBufferLogicFlag)){ + Print_Str(Title[7][3].XPOS, 0,Title[7][3].Color[Title[7][0].Value], PRN,"T"); //active in this mode, normal color + }else{ + Print_Str(Title[7][3].XPOS, 0,0x0905, PRN,"T"); //greyed out, not active + } + } + } + else + { + __Point_SCR(0 + 91 + (_X_posi.Value * 200)/3720, 0); //3796 + for(j=0;j<9;++j) __LCD_SetPixl(WHT); + __Point_SCR(15 + 91 + (_X_posi.Value * 200)/3720, 0); + for(j=0;j<9;++j) __LCD_SetPixl(WHT); + for(i=0;i<16;++i){ + DrawPixel(i + 91 +(_X_posi.Value * 200)/3720, 0,WHT); + DrawPixel(i + 91 +(_X_posi.Value * 200)/3720, 9,WHT); + } + } + _X_View.Flag &= !UPDAT; + DisplaySamples(); +} +/******************************************************************************* +Clear_Meter_Area Pulisce l'area sotto ai meter per quando vengono rivisualizzati +*******************************************************************************/ +void Clear_Meter_Area(void) +{ + ClearScreenArea(312,400,11,216); + _X_View.Flag &= !UPDAT; +} + +void LoadXYBuffer(u16 Row){ +u8 i,buffer; +s16 TempY; +register u16 RegTemp=BufferSize-1; +u16 h; + + if(((Row>37)&&(Row>8)&0xFF)+FactorY13; + if((TempY>14)&&(TempY<212)){ + DrawPixel(Row,TempY,GRN); + } + } + } + + }else{ //regular mode + for(h = 0; h <=RegTemp; ++h){ + if(((DataBuf[h]&0xFF)+FactorX)==Row){ + TempY=((DataBuf[h]>>8)&0xFF)+FactorY; + if((TempY>1)&&(TempY<199)){ + LCD_Buffer[buffer][TempY] |= GRN; + } + } + } + if((Current==9)&&(_Det==3))PrintDir(Row,buffer,0); +DrawCross: + if ((Row<(OffsetX+5)) && (Row>(OffsetX-5)))LCD_Buffer[buffer][OffsetY] |=PURPL; + if ((Row==OffsetX))for(i=OffsetY-4;i37 +} + + +void DisplayDetFrqn(u16 Row, u8 buffer){ +u16 i,End; +u8 j; +s32 Tmp; +static u8 PrintFlag=1; +static u16 xpos; +static u8 ypos=1; +u16 ReadPos; +u16 ReadARR; +u32 SamplingPeriod; +u32 Tim2Period; +s16 Tim2Shifts; +static char Str1[12]; + + if((ShowFFT==0)&&(CurDefTime)&&(_Kind<4)&&(Sweep==1)){ + + EnableMeterCalc=1; + if(LastFreqReadout==0)return; + if(FlagMeter)End=280;else End=340; + + for(i=(MIN_X+18);i<(MIN_X+End);i+=30){ + if((Row>=i)&&(Row<(i+33))){ + if(Row==(MIN_X+18)){ + ReadPos=(_T1+_T2)/2; + if(A_Tab[_Frqn]<201)ReadARR=((100000*ScaleIndex[_Frqn])+(LastFreqReadout/2))/LastFreqReadout; //use rounding for 500hz ranges and up + else ReadARR=(100000*ScaleIndex[_Frqn])/LastFreqReadout; //use no rounding for lower frequency ranges <500hz + SamplingPeriod=(((X_Attr[_T_base].PSC+1)*(X_Attr[_T_base].ARR+1)*100)+36)/72; //X this by 100 for x10nS and full scale range + Tim2Period=((TIM2->ARR+1)*SweepMod*100)/SweepStep; //as above + + for(j=0;j<12;j++){ + Tmp=ReadPos-((j+1)*30); //how far away (+or-)from readposition each display is in number of samples + if(Tmp>0)Tim2Shifts=(s32)((SamplingPeriod*Tmp)+(Tim2Period/2))/(s32)Tim2Period; + else Tim2Shifts=(s32)((SamplingPeriod*Tmp)-(Tim2Period/2))/(s32)Tim2Period; + if(A_Tab[_Frqn]<201){ //500hz and up FREQUENCY DISPLAY TRACKING +//====================500 HZ AND UP COMPENSATION=================================================== + if(Tim2Shifts>0)Tim2Shifts=((Tim2Shifts*DetFrqAdj[SweepIndex])+50)/100; //INCREASING factor DECREASES display freq values LEFT of sample + else Tim2Shifts=((Tim2Shifts*DetFrqAdj[SweepIndex])-50)/100; //INCREASING factor INCREASES display freq values RIGHT of sample +//================================================================================================= + DetFrqn[j]=(s16)ReadARR+Tim2Shifts; +//====================500 HZ AND UP BOUNDS LIMIT=================================================== + if((_Frqn==8)&&(DetFrqn[j]<100))DetFrqn[j]=0; //500HZ SPECIAL CASE RIGHT BOUNDS LIMIT >flag out of bounds for disabling + else if(DetFrqn[j]<39)DetFrqn[j]=0; //RIGHT BOUNDS LIMIT REST + else if(DetFrqn[j]>(A_Tab[_Frqn]+105))DetFrqn[j]=0; //LEFT BOUNDS LIMIT +//================================================================================================= + }else{ //200hz and down FREQUENCY DISPLAY TRACKING +//====================200 HZ AND DOWN COMPENSATION=================================================== + if(Tim2Shifts>0)Tim2Shifts=((Tim2Shifts*120)+50)/100; //INCREASING factor DECREASES display freq values LEFT of sample + else Tim2Shifts=((Tim2Shifts*120)-50)/100; //INCREASING factor INCREASES display freq values RIGHT of sample +//================================================================================================= + Tmp=((ReadARR-((ReadARR+(A_Tab[_Frqn]+1))/2))*600)/((ReadARR+A_Tab[_Frqn]+1)); //contains X TIM2shifts in relation to freq range default ARR + Tmp+=Tim2Shifts; + DetFrqn[j]=(((A_Tab[_Frqn]+1)*(300+Tmp))+((300-Tmp)/2))/(300-Tmp); //shifts back to individual display positions, gives ARR +//====================200 HZ AND DOWN BOUNDS LIMIT=================================================== + if((Tmp<-102)||(Tmp>105))DetFrqn[j]=0; //RIGHT AND LEFT BOUNDS LIMIT +//================================================================================================= + } + } + }//if(Row==MIN_X + if(Row==i){ + Tmp=DetFrqn[(i-MIN_X)/30]; + if(Tmp>0)PrintFlag=1;else PrintFlag=0; //do not show out of bounds values + Tmp=(1000000000/Tmp)*ScaleIndex[_Frqn]; //calculate frequency at each division (scale=4) + Int2Str(Str1,Tmp, F_UNIT, 3, UNSIGN, 4); + if(Str1[0]==46){for(j=0;j<3;j++)Str1[j]=Str1[j+1]; Str1[3]=0;} //remove leading periods, not needed without suffixes + for(j=0;j<5;j++){if(Str1[j]==46)Str1[j]=127;} //proportional 3pix period so displays are not too wide + Str1[4]=0; + if((i-(MIN_X+18))%60==0)ypos=1;else ypos=6; + xpos=i; + } + + if(PrintFlag){ + Print_Str_Row(Row, LCD_Buffer[buffer],xpos,ypos,Str1); + if((Row-MIN_X)%30==0){ + for(j=(ypos+11);j<(ypos+17);j++)LCD_Buffer[buffer][j]=GRN; + } + } + }//if((Row>=i + }//for + }else EnableMeterCalc=0; //if showfft=0 + +} + +void InitiateCharArrays(void){ +u16 i; +char *p,*q; + + p=AscChar[0][0]; + q=AscCharB[0][0]; + for(i=0;i<102;i++){*p++=0;*q++=0;} + p=&HexChar[0][0]; + q=&HexCharB[0][0]; + for(i=0;i<294;i++){*p++=0;*q++=0;} +} + +void Uart(void){ +u16 Iterations=0; +u16 i; +u8 j; +static u16 Start=90; +u8 End; +u8 Tmp; +u16 FrameSamples=TcurDelta; +u16 LoString=TcurDelta; +u16 HiString=TcurDelta; +register u8 DataByte; +register u8 PrevDataByte; + + if(_T1>=_T2)return; + BitDuration=(FrameSamples+(FrameSize/2))/FrameSize; + End=FrameSize-(2+Parity); + + if(T1Start==1){ + if(Current==T_VERNIE){ + Start=IndexPosition(_T1,1)+_X_posi.Value; + if(Start<1)Start=1; + } + }else Start=90; + +Restart: + for(i=0;i<96;i++)ByteArray[i].Data=0; + ArrayIndex=0; + ValidFrame=1; + + for(i=Start;i<(bag_max_buf-FrameSamples);i++){ //limit to end of buffer - 1 frame size + DataByte=((DataBuf[i]&0xFF)-ADCoffset); + PrevDataByte=((DataBuf[i-1]&0xFF)-ADCoffset); + + if(DataByteCh1TLevel)HiString++;else HiString=0; + + if(((Title[TRACK1][1].Value==3)&& ( (PrevDataByte>Ch1TLevel)||(LoStringCh1TLevel))){ + + ByteArray[ArrayIndex].Index=i; //record on screen position of each captured frame start bit + for(j=0;jCh1TLevel)ByteArray[ArrayIndex].Data|=Mask<95)break; //move to next byte + + i+=(FrameSamples-((BitDuration+1)/2)); //move index to middle of stop bit + + //with start bit recognized, look for stop bit, if not found set validframe to 0 to shift start position and restart scan + if(((Title[TRACK1][1].Value==3)&&(((DataBuf[i]&0xFF)-ADCoffset)Ch1TLevel)&&(((DataBuf[i+1]&0xFF)-ADCoffset)>Ch1TLevel)))ValidFrame=0; + if((ValidFrame==0)&&(T1Start==0)){ + if(Iterations<(FrameSamples*2)){ //limit tries to 2 frame lengths, if not sync'ed by then ValidFrame stays at 0 + Iterations++; + Start++; + goto Restart; + }else break; + } + + }//if + //if(Key_Buffer)break; + }//for + + LoadChars(0); +} + + +void LoadChars(u8 service){ +u8 i,j; +u8 Tmp,end; +u16 Counter=0; +char *p,*s; + + InitiateCharArrays(); + if(service==2)end=2;else end=1; + for(j=0;j0){ + if(ByteArray[i-1].End & 0x1000){ // if byte following a 10 bit address frame + AscChar[i/48][(i/16)%3][i%16]=128; // special "ad" char for second part of 10 bit address + } + } + } + if((service<2)||((SpiNumBits>0)&&(SpiNumBits<9))){ + p=&HexChar[i/16][(i%16)*3]; //copy 2 bytes + add space or null if at end + Char2Hex(HexLookup,ByteArray[i].Data); + s=(char*)HexLookup; + *p++=*s++;*p++=*s++; + if((i%16)==15)*p++=0;else*p++=0x20; + } + } + if((j==1)&&((SpiNumBits>0)&&(SpiNumBits<9))){ + p=&HexCharB[i/16][(i%16)*3]; //copy 2 bytes + add space or null if at end + Char2Hex(HexLookup,ByteArray[i].DataB); + s=(char*)HexLookup; + *p++=*s++;*p++=*s++; + if((i%16)==15)*p++=0;else*p++=0x20; //if end of array dimension, add null otherwise add space and go on + } + + }//for i + }//for j + + if((service==2)&&((SpiNumBits<=0)||(SpiNumBits>8))){ //SPI chart with variable word length + Counter=0; + for(i=0;i<96;i++){ + if(i==ArrayIndex){ + HexChar[Counter/48][Counter%48]=0; + HexCharB[Counter/48][Counter%48]=0; + return; + } + if((ByteArray[i].Index>0)&&(ByteArray[i].BitsPerWord>0)){ //id start of word + for(j=0;j<((ByteArray[i].BitsPerWord+7)/8);j++){ + if((j==0)&&((((ByteArray[i].BitsPerWord+7)/8)*2)>(48-(Counter%48)))) //move to next line if not enough room for full word + while(Counter%48){Counter++;if(Counter>(5*48))break;} + + Char2Hex(HexLookup,ByteArray[i+j].Data); + HexChar[Counter/48][Counter%48]=HexLookup[0]; //high nibbles + Char2Hex(HexLookup,ByteArray[i+j].DataB); + HexCharB[Counter/48][Counter%48]=HexLookup[0]; + Counter++; + + Char2Hex(HexLookup,ByteArray[i+j].Data); + HexChar[Counter/48][Counter%48]=HexLookup[1]; //low nibbles + Char2Hex(HexLookup,ByteArray[i+j].DataB); + HexCharB[Counter/48][Counter%48]=HexLookup[1]; + Counter++; + + if(Counter>=(6*48))return; + } + if(((Counter%48)<46)&&((Counter%48)>0)){ //no spaces needed at end or start of lines + HexChar[Counter/48][Counter%48]=0x20; //spaces between words + HexCharB[Counter/48][Counter%48]=0x20; + Counter++; + } + } + } + + } + +} + +void SpiChart(u16 Row,u8 buffer){ //displays words with varying lengths +u8 i,j,x1,x2,x3,x4; + + COLOR_INDEX=0x0504; + if((A_Posi ChA is below + {x3=90;x4=63;x1=187;x2=160;} //if ChA is above and ChC used as clock, need to show ChB below + + for(i=0;i<2;i++){ + for(j=0;j<3;j++){ + if((SpiNumBits==7)||(SpiNumBits==8)){ + if(j==1)COLOR_INDEX=0x0501;else COLOR_INDEX=0x0504; + Print_Str_Row(Row, LCD_Buffer[buffer],13+(j*(16*8)),x1-(i*11),AscChar[i][j]); + if(_3_source)Print_Str_Row(Row, LCD_Buffer[buffer],13+(j*(16*8)),x3-(i*11),AscCharB[i][j]); + Print_Str_Row(Row, LCD_Buffer[buffer],17,x2-((((i*3)+j)*11)+(i*5)),HexChar[(i*3)+j]); + if(_3_source)Print_Str_Row(Row, LCD_Buffer[buffer],17,x4-((((i*3)+j)*11)+(i*5)),HexCharB[(i*3)+j]); + }else{ + Print_Str_Row(Row, LCD_Buffer[buffer],13,x2-((((i*3)+j)*11)+(i*5)),HexChar[(i*3)+j]); + if(_3_source)Print_Str_Row(Row, LCD_Buffer[buffer],13,x4-((((i*3)+j)*11)+(i*5)),HexCharB[(i*3)+j]); + } + } + } +} + +void PrintDir(u16 Row, u8 buffer,u8 Mode){ +u8 i,j,h,y=174,LastY=174; +u16 x; +char Transfer[13]; + + if(FlagMeter)x=214;else x=300; + SkipFirstRow=1; //aligns Print_Str with Print_Str_Row + + if(Title[9][0].Value==1){ + for(i=0;i<15;i++){ + + for(j=0;j<13;j++)Transfer[j]=Label[i][j]; + for(j=0;j<8;j++){ + switch(Transfer[j]){ //process unavailable chars to display dot + case 39: //' + case 64: //@ + Transfer[j]=63; + break; + default: + if(((Transfer[j]>32)&&(Transfer[j]<37))||(Transfer[j]>124))Transfer[j]=63; + } + } + + if(i==Title[9][3].Value){ //if item position is selected (blink) + if(Mode==2){ + COLOR_INDEX=0x0405; //selection hilighted but not blinking + }else{ + if(Twink)COLOR_INDEX=0x0504;else COLOR_INDEX=0x0405; //selection blinking + } + + }else{ + COLOR_INDEX=0x0504; + for(h=0;h<8;h++){ + if(SelectedFileName[h]!=Label[i][h])break; + if(h==7)COLOR_INDEX=0x0405; //if file has been recently loaded or saved + } + } + + if(Label[i][0]!=0){ + if(Mode==0){ + Print_Str_Row(Row, LCD_Buffer[buffer],x,y,Transfer); //write to screen buffer + }else if((Mode==1)||(Mode==2)){ + Print_Str(x,y+MIN_Y,COLOR_INDEX,INV,Transfer); //direct write to screen (mode 2= no blinking) + }else{ + for(j=0;j<12;j++)Transfer[j]=' '; //direct write cleared list to screen + Print_Str(x,y+MIN_Y,0x0504,INV,Transfer); + } + LastY=y; + } + y-=11; + + } + + if(DownConvertMode){ + j=LastY-5; + if((Row>(x-7))&&(Row=x)&&(Row<(x+(8*12)))){ + for(i=j;i print uart, =1> print i2c, =2> print spi +u8 i,j; +char *p; +char HexStr[32]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; //32 bytes max for 192 possible SPI bits +static u8 Read=0; +static u8 BytesPerWord=1; + +if(SpiNumBits>0)BytesPerWord=((SpiNumBits+7)/8); + +if((Row > MIN_X)&&(Row < MAX_X)){ + for(i=0;i<96;i++){ + if(i>=ArrayIndex)break; + + if(service==0){ + if((IndexPosition(Row,1)+_X_posi.Value)>=(ByteArray[i].Index)&&(IndexPosition(Row,1)+_X_posi.Value)<=(ByteArray[i].Index+(TcurDelta)+9)){ + + COLOR_INDEX=0x0509; //GRAY + Print_Str_Row(Row, LCD_Buffer[buffer],IndexPosition((ByteArray[i].Index+MIN_X+1)-(_X_posi.Value),0),112,"<"); //bar at start of frame + Print_Str_Row(Row, LCD_Buffer[buffer],IndexPosition((ByteArray[i].Index+(TcurDelta)+MIN_X)-(_X_posi.Value+((8*1024)/_Kp1)),0),112,">"); //bar at end of frame + COLOR_INDEX=0x0504; //WHITE + HexStr[0]=AscChar[i/48][(i/16)%3][i%16];HexStr[1]=0; + Print_Str_Row(Row, LCD_Buffer[buffer],IndexPosition((ByteArray[i].Index+((((TcurDelta)+1)/2)-((4*_Kp1)/1024))+MIN_X)-_X_posi.Value,0),112,HexStr); //ascii char + COLOR_INDEX=0x050B; //GREEN + Char2Hex(HexLookup,ByteArray[i].Data); + Print_Str_Row(Row, LCD_Buffer[buffer],IndexPosition((ByteArray[i].Index+((((TcurDelta)+1)/2)-((8*_Kp1)/1024))+MIN_X)-_X_posi.Value,0),101,(char*)HexLookup); //hex value + + } + } + + if(service==1){ + if( (IndexPosition(Row,1)+_X_posi.Value) >=(ByteArray[i].Index)&& + (IndexPosition(Row,1)+_X_posi.Value)<=((ByteArray[i].End & 0xFFF)+9)){ + + if(ByteArray[i].End & 0x2000){ //if address word + if(ByteArray[i].End & 0x8000)Read=1;else Read=0; + } + + if(Read){if(ByteArray[i].End & 0x4000)COLOR_INDEX=0x050F; else COLOR_INDEX=0x050B;} + else COLOR_INDEX=0x050D; + Print_Str_Row(Row, LCD_Buffer[buffer],IndexPosition((ByteArray[i].Index+MIN_X+1)-(_X_posi.Value),0),112,"<"); //bar at start of frame + + if(Read)COLOR_INDEX=0x050D; else {if(ByteArray[i].End & 0x4000)COLOR_INDEX=0x050F; + else COLOR_INDEX=0x050B;} + Print_Str_Row(Row, LCD_Buffer[buffer],IndexPosition(((ByteArray[i].End & 0xFFF)+MIN_X) + -(_X_posi.Value+8),0),112,">"); + + if((ByteArray[i].End&0x2000)||((i>0)&&(ByteArray[i-1].End&0x1000)))COLOR_INDEX=0x0507;else COLOR_INDEX=0x0504; //add frame + HexStr[0]=AscChar[i/48][(i/16)%3][i%16];HexStr[1]=0; + Print_Str_Row(Row, LCD_Buffer[buffer],IndexPosition((ByteArray[i].Index+(((((ByteArray[i].End & 0xFFF) + -ByteArray[i].Index)/2)-4)+MIN_X)-_X_posi.Value),0),112,HexStr); //ascii char + + if((ByteArray[i].End&0x2000)||((i>0)&&(ByteArray[i-1].End&0x1000)))COLOR_INDEX=0x0507;else COLOR_INDEX=0x050B; //add frame + Char2Hex(HexLookup,ByteArray[i].Data); + Print_Str_Row(Row, LCD_Buffer[buffer],IndexPosition((ByteArray[i].Index+(((((ByteArray[i].End & 0xFFF) //hex value + -ByteArray[i].Index)/2)-8)+MIN_X)-_X_posi.Value),0),101,(char*)HexLookup); + + } + } + + if(service==2){ + if(SpiNumBits<=0){ //INCLUDED 0 + if(ByteArray[i].BitsPerWord>0){ + Read=ByteArray[i].BitsPerWord; + BytesPerWord=(((Read-1)/8)+1); + } + }else Read=SpiNumBits; + + if(((IndexPosition(Row,1)+_X_posi.Value)>=ByteArray[i].Index)&&((IndexPosition(Row,1)+_X_posi.Value)<= + (ByteArray[i].End+12))){ //was End+9 + + COLOR_INDEX=0x0509; + Print_Str_Row(Row, LCD_Buffer[buffer],IndexPosition((ByteArray[i].Index+MIN_X+1)-(_X_posi.Value+8),0)+8,_1_posi-15,"<"); //CH A "<" + Print_Str_Row(Row, LCD_Buffer[buffer],IndexPosition((ByteArray[i].End+MIN_X) + -(_X_posi.Value+6),0),_1_posi-15,">"); //CH A ">" + if((_2_source)&&(_3_source)){ + Print_Str_Row(Row, LCD_Buffer[buffer],IndexPosition((ByteArray[i].Index+MIN_X+1)-(_X_posi.Value+8),0)+8,_2_posi-15,"<"); //CH B "<" + Print_Str_Row(Row, LCD_Buffer[buffer],IndexPosition((ByteArray[i].End+MIN_X) + -(_X_posi.Value+6),0),_2_posi-15,">"); //CH B ">" + } + + COLOR_INDEX=0x0504; //WHITE + if((Read==7)||(Read==8)){ + HexStr[0]=AscChar[i/48][(i/16)%3][i%16]; + }else HexStr[0]=63; + HexStr[1]=0; + + Print_Str_Row(Row, LCD_Buffer[buffer],IndexPosition((ByteArray[i].Index+((((ByteArray[i].End + -ByteArray[i].Index)/2))+MIN_X)-_X_posi.Value),0)-3,_1_posi-15,HexStr); //CH A ASCII + + if((_2_source)&&(_3_source)){ + if((Read==7)||(Read==8)){ + HexStr[0]=AscCharB[i/48][(i/16)%3][i%16]; + }else HexStr[0]=63; + Print_Str_Row(Row, LCD_Buffer[buffer],IndexPosition(((ByteArray[i].Index+((((ByteArray[i].End + -ByteArray[i].Index))/2))+MIN_X)-_X_posi.Value),0)-3,_2_posi-15,HexStr); //CH B ASCII + } + + COLOR_INDEX=0x050B; //GREEN + + p=HexStr; + for(j=0;j0)&&(ByteArray[i-1].End & 0x1000))){ //add frame or 2nd byte of 10 bit address + HexStr[0]=AscChar[i/48][(i/16)%3][i%16];HexStr[1]=0; + Print_Str_Row(Row, LCD_Buffer[buffer],13+((i%48)*8),90-((i/48)*11),HexStr); + HexStr[0]=HexChar[i/16][((i%16)*3)]; + HexStr[1]=HexChar[i/16][((i%16)*3)+1]; + HexStr[2]=0; + Print_Str_Row(Row, LCD_Buffer[buffer],17+(((i%16)*3)*8),63-(((i/16)*11)+((i/48)*5)),HexStr); + } + } + } + + COLOR_INDEX=0x0503; + }//if row +} + +u16 IndexPosition(s16 Position,u8 service){ +if(service)return(((Position-150)*_Kp1)/1024)+150; + else return(((Position-150)*1024)/_Kp1)+150; +} + +void Spi(void){ +u16 i; +s16 TargetBit=0; +u8 BitNumber=8, BytesPerWord=1; +u8 Start=90; + + for(i=0;i<96;i++){ByteArray[i].Data=0;ByteArray[i].Index=0; + ByteArray[i].End=0;ByteArray[i].DataB=0;ByteArray[i].BitsPerWord=0;} + ArrayIndex=0; + + if(SpiNumBits>0){ //normal mode with defined word length + BytesPerWord=((SpiNumBits+7)/8); + if(SpiBitOrder)TargetBit=0;else TargetBit=(SpiNumBits-1); + }else{ //in "reset word after space" mode + + if(SpiNumBits==0){ + ClockPeriod=0xFFFF; //initiate WordEndFlag function in auto mode + Start=90; + }else{ + if(SpiNumBits>-120)Start=(135+SpiNumBits);else Start=15; //SpiNumBits has been limited to prevent possible out of bounds errors + } + + for(i=Start;i<(bag_max_buf-1);i++){ //setup to find in between clock bursts spaces and word lengths + if(BitReadPosition(i)){ + if(WordEndFlag){ //beginning of new word at this point + if(TargetBit>0){ //if start position of new word, not at beginning + ByteArray[ArrayIndex].BitsPerWord=TargetBit; //store previous word length in bits + if((ArrayIndex+(((TargetBit-1)/8)+1))<96){ + ArrayIndex+=(((TargetBit-1)/8)+1); //advance ArrayIndex enough bytes to contain all bits from previous word + }else break; + ByteArray[ArrayIndex].Index=i; //new start position + TargetBit=1; + }else {ByteArray[ArrayIndex].Index=i;TargetBit=1;} //first word position, TargetBit will not advance, so do it here + WordEndFlag=0; + }else if(TargetBit<192)TargetBit++; //count word bits + } + } + if(WordEndFlag)ByteArray[ArrayIndex].BitsPerWord=TargetBit; //record word length if not done + if(WordEndFlag==0)ByteArray[ArrayIndex].Index=0xFFFF; //if WordEndFlag=0, means end of buffer at mid word, cancel + } + + ArrayIndex=0; //initiate ArrayIndex + if(SpiNumBits==0)ClockPeriod=0xFFFF; //initiate auto mode + for(i=Start;i<(bag_max_buf-1);i++){ //scan for data + + if(BitReadPosition(i)){ + + if(SpiNumBits<=0){ + if(ByteArray[ArrayIndex].Index==i){ //TargetBit is index, shifts through ALL bit positions to load ByteArray + TargetBit=ByteArray[ArrayIndex].BitsPerWord; //BitNumber = bits per word recorded from array. Here, varies from word to word + BytesPerWord=(((TargetBit-1)/8)+1); + BitNumber=TargetBit; + if(SpiBitOrder)TargetBit=0;else TargetBit--; + }else if(ByteArray[ArrayIndex].Index==0xFFFF){ByteArray[ArrayIndex].Index=0;break;} //end of decoding flag + }else BitNumber=SpiNumBits; //preset bit numbers + + if(((DataBuf[i]&0xFF)-ADCoffset)>Ch1TLevel){ //if ch A bit is set + ByteArray[ArrayIndex+((BytesPerWord-(TargetBit/8))-1)].Data|=1<<(TargetBit%8); + } + if((_3_source)&&(((((DataBuf[i]>>8)&0xFF)-ADCoffset))>Ch2TLevel)){ //if ch C used as clock, read ch B bits + ByteArray[ArrayIndex+((BytesPerWord-(TargetBit/8))-1)].DataB|=1<<(TargetBit%8); + } + + if(SpiBitOrder){ //LSB FIRST "<" + if(TargetBit==0){ + ByteArray[ArrayIndex].Index=i; //start of word + if(_3_source)ByteArray[ArrayIndex].Index-=5; //compensate for digital/analog ch offset + if(SpiNumBits>0)ByteArray[ArrayIndex].BitsPerWord=SpiNumBits; + } + TargetBit++; + if(TargetBit>=BitNumber){ //advance bit position, shift to new word + TargetBit=0; + ByteArray[ArrayIndex].End=i; //end of word + if(_3_source)ByteArray[ArrayIndex].End-=5; + ArrayIndex+=BytesPerWord; + } + }else{ //MSB FIRST ">" + if(TargetBit==(BitNumber-1)){ + ByteArray[ArrayIndex].Index=i; //start of word + if(_3_source)ByteArray[ArrayIndex].Index-=5; + if(SpiNumBits>0)ByteArray[ArrayIndex].BitsPerWord=SpiNumBits; + } + if(TargetBit<=0){ + TargetBit=(BitNumber-1); + ByteArray[ArrayIndex].End=i; //end of word + if(_3_source)ByteArray[ArrayIndex].End-=5; + ArrayIndex+=BytesPerWord; + }else TargetBit--; + } + if(ArrayIndex>95){ + if(ArrayIndex==96)break; + ArrayIndex-=BytesPerWord; + ByteArray[ArrayIndex].Index=0; + break; + } + } + } + LoadChars(2); +} + +u8 BitReadPosition(u16 i){ //flags a valid spi read position +static u16 SpiIdleSamples=0,PrevIPos=0; +register u8 PrevClock,Clock; +u8 Read=0; + if(_3_source){ //use ch C as clock if available + Clock=((DataBuf[i-4]>>16)&1); + PrevClock=((DataBuf[i-5]>>16)&1); + switch(SpiMode){ + case 0: + case 3: + if((PrevClock==0)&&(Clock==1))Read=1; + break; + case 1: + case 2: + if((PrevClock==1)&&(Clock==0))Read=1; + } + }else{ //if ch C not available, use ch B as clock + Clock=((DataBuf[i+1]>>8)&0xFF)-ADCoffset; + PrevClock=((DataBuf[i]>>8)&0xFF)-ADCoffset; + switch(SpiMode){ + case 0: + case 3: + if((PrevClock=Ch2TLevel))Read=1; + break; + case 1: + case 2: + if((PrevClock>=Ch2TLevel)&&(Clock8)){ //inter-clock bursts space detection + if(Read==0)SpiIdleSamples++;else SpiIdleSamples=0; + if(SpiIdleSamples>4096)SpiIdleSamples=4096; + if(SpiNumBits==0){ + if(SpiIdleSamples>(ClockPeriod*2))WordEndFlag=1; + }else{ + if(SpiIdleSamples>(-SpiNumBits))WordEndFlag=1; + } + } + return Read; +} + +void i2c(void){ +u16 i; +u8 Frame=0; +u8 BitPosition=8; +u16 BitStore=0; +u16 Tmp=0; +register u8 PrevData,Data,PrevClock,Clock; + + for(i=0;i<96;i++){ByteArray[i].Data=0;ByteArray[i].Index=0;ByteArray[i].End=0;} + ArrayIndex=0; + + for(i=90;i<(bag_max_buf-1);i++){ + PrevData=((DataBuf[i-1]&0xFF)-ADCoffset); //ch a + Data=((DataBuf[i]&0xFF)-ADCoffset); //ch a + PrevClock=((DataBuf[i]>>8)&0xFF)-ADCoffset; //ch b + Clock=((DataBuf[i+1]>>8)&0xFF)-ADCoffset; //ch b + + if((PrevData>=Ch1TLevel)&&(DataCh2TLevel)) //start/restart of frame + {Frame=1;BitPosition=8;BitStore=0;} + if((PrevData=Ch1TLevel)&&(Clock>Ch2TLevel))Frame=0; //end of frame + + if(Frame){ + if(BitPosition==7){ + if((PrevClock>=Ch2TLevel)&&(Clock=Ch2TLevel)&&(Clock=Ch2TLevel)){ //read position + if(BitPosition==8){ + ByteArray[ArrayIndex].Index=i; + } + if(Data>Ch1TLevel)BitStore|=(1<>4)==0x1E){ //10 bit address id + ByteArray[ArrayIndex].End|=0x1000; //set bit 12: 10bit address flag + ByteArray[ArrayIndex].Data=(BitStore>>2)&3; //display 2 MSB of 10 bit address + }else ByteArray[ArrayIndex].Data=(BitStore>>2); //if 7 bit address + if((BitStore>>1)&1)ByteArray[ArrayIndex].End|=0x8000; //W/R bit 15 (0=W, 1=R) + if(BitStore&1)ByteArray[ArrayIndex].End|=0x4000; //Ack bit 14 (0=Ack, 1=NAck) + ByteArray[ArrayIndex].End|=0x2000; //set bit 13 to id address word + Frame=2; //End bits 0-11 used to store ending position of word + }else{ //Frame=2 > data frames + ByteArray[ArrayIndex].Data=BitStore>>1; + if(BitStore&1)ByteArray[ArrayIndex].End|=0x4000; //Ack bit 14 (0=Ack, 1=NAck) + } + BitStore=0; + ArrayIndex++;if(ArrayIndex>95)break; //move to next byte + } + } + }//if frame + + }//for scanning databuf + LoadChars(1); +} + +void DisplayDbScale(u16 Row, u8 buffer, u8 service){ +u8 j=189; +s8 i,DB[8]={3,0,-2,-4,-7,-10,-14,-20}; +s32 Tmp; +u8 Charact; +char DbString[4]; + + if((AutoFFT==0)&&(service==0)){ //setup array to display log db scale + for(i=-1;i<7;i++){ + DB[i+1]=i*-10; + } + } + + if(Row>266){ + if((service==0)&&(DownConvertMode==0)){ + Print_Str_Row(Row, LCD_Buffer[buffer], 267,189, "db" ); //print "db" on top line + } + for(i=0;i<8;i++){ //print db values in auto and manual modes + if(service==0){if(AutoFFT>0)Tmp=DB[i]-(FFTGain*6);else Tmp=DB[i];} + else Tmp=DB[i]; //print db values for detector mode + s8ToDec2(DbString,Tmp); + if((Tmp>-10)&&(Tmp<10))Tmp=4; else Tmp=0; + if(FlagMeter==0)Tmp+=88; + Print_Str_Row(Row, LCD_Buffer[buffer], 284+Tmp,j,DbString); + if(j==189)j-=19;else j-=25; + } + } + + + if(service==0){ + if(AutoFFT==0){ //print v2 cursor db value + Tmp=(-(((200-Title[V_VERNIE][V2].Value)*10)+12)/25)+10; + }else{ + Tmp=Title[V_VERNIE][V2].Value; //retrieve cursor position + Tmp=(Tmp*100)/(100+((244-Tmp)/2)); //scale to get original value + Tmp=((1300+(Tmp/2))/Tmp); //convert to ratio, refered to 0db, upscaled by 10 + Charact=0; + while(Tmp>99){ //calculate log10 + Tmp/=10; + Charact++; + } + Tmp=(2*((Charact*100)+Log10Mant[Tmp]))/10; //convert to decibels, scaled back down + if(Title[V_VERNIE][V2].Value>179){ + Tmp=(Title[V_VERNIE][V2].Value-180)/5; + }else if(Title[V_VERNIE][V2].Value<29){ + Tmp=DbScale[Title[V_VERNIE][V2].Value]; + }else Tmp=-Tmp; + Tmp-=(FFTGain*6); //add gain + } + + s8ToDec2(DbString,(s8)Tmp); + if((Tmp>-10)&&(Tmp<10))Tmp=4; else Tmp=0; + if(DownConvertMode){Tmp+=(6*8);COLOR_INDEX=0x0504;} + Print_Str_Row(Row, LCD_Buffer[buffer],242+Tmp,189,DbString); + COLOR_INDEX=0x0503; + } + +} + +void DisplayFFtValues(u16 Row,u8 buffer){ +u8 Yadj=0; + if((_Mode!=NORHLD)&&((FlagMeter>0)||((DownConvertMode)&&(FFTt1Mode==0)))){ + if ( PeakFreq>5){ + + if ( RowMemPeak < 15)RowMemPeak = 15; + if ( RowMemPeak > 253)RowMemPeak = 253; + if (PeakFreq+14 > 178) { + Print_Str_Row(Row, LCD_Buffer[buffer], RowMemPeak+2, 178, PeakFreqStr); + } else { + Print_Str_Row(Row, LCD_Buffer[buffer], RowMemPeak+2, PeakFreq+14, PeakFreqStr); + } + + } + } + + if(DownConvertMode)Yadj=(3*8); + if(Row<54)Print_Str_Row(Row, LCD_Buffer[buffer], 21, 189, "Div:" ); + if(Row<(110+Yadj))Print_Str_Row(Row, LCD_Buffer[buffer], 53,189, FreqDivStr); + if((Row>(123+Yadj))&&(Row<(149+Yadj)))Print_Str_Row(Row, LCD_Buffer[buffer], 124+Yadj,189, "T1:" ); + if((Row>(147+Yadj))&&(Row<(205+(Yadj*2))))Print_Str_Row(Row, LCD_Buffer[buffer], 148+Yadj,189, FreqT1Str); + if(DownConvertMode)Yadj=(6*8); + if((Row>(217+Yadj))&&(Row<(243+Yadj)))Print_Str_Row(Row, LCD_Buffer[buffer], 218+Yadj,189, "V2:"); + + if(Row>267){ + if(DownConvertMode){ + Print_Str_Row(Row, LCD_Buffer[buffer],274,61, "Start="); + Print_Str_Row(Row, LCD_Buffer[buffer],274,50, BaseFreqStr); + Print_Str_Row(Row, LCD_Buffer[buffer],274,21, "End="); + Print_Str_Row(Row, LCD_Buffer[buffer],274,10, NFreqStr); + }else{ + Print_Str_Row(Row, LCD_Buffer[buffer], 280, 1, Nsuffix); + Print_Str_Row(Row, LCD_Buffer[buffer], 268,10, Nfreq); + } + } +} + +void LoadBuffer(u16 Row, u8 buffer,u8 *y,u8 *Dot_Hide,u8 service){ + u8 i=0,j=0,h=0,end; + u16 Col=0,Dim[4]={0x4200,0x0208,0x4008,0x0200}; + + Dim[0]>>=FastDim; + Dim[1]>>=FastDim; + + if((OsBufferLogicFlag)||(DigChLockout)||(OsChartFlag))end=3; + else{if(ShowFFT)end=5;else end=7;} + + if( (_Mode==NORHLD)&&(Current==FILE)&&(Row>Limit)&&(_Det==3)&&(Title[9][0].Value==1) ){ + for(i=0;iListBottom){y[i]=ListBottom;Dot_Hide[i]=1;} //limit to bottom of list + } + + if(service){ //normal draw + + if((_T_base>7)||(Row!=skip) ||((_T_base>3)&&(_Mode!=SCAN))){ + for(j=0;j5)Col-=Dim[h]; + for(i=y[j]; i<=y[j+1]; ++i) LCD_Buffer[buffer][i] |=Col; + } + } + } + + if((Row==ChartIndex)||(Row==(ChartIndex-1))){ + for(i=191;i<199;i++)LCD_Buffer[buffer][i] |= YEL_; + } + + }else{ //persistence mode + + for(j=0;j5)Col-=Dim[h]; + for(i=y[j]; i<=y[j+1]; ++i) __LCD_SetPixl(Col); + } + } + } + } + +} + +void LoadFFTbuffer(u16 Row,u8 buffer){ + s16 fftx, val= 0; + u8 i; //,j; + + if((Row > MIN_X)&&(Row < MAX_X)){ + // FFT /////// + if (ShowFFT==1){ + + if((ClearPerst)||(Update)||(_Mode!=NORHLD)||(UpdateBackground==3)){ + + if(DownConvertMode)COLOR_INDEX=0x0504; + DisplayFFtValues(Row,buffer); + COLOR_INDEX=0x0503; + + if(!((_Mode==NORHLD)&&(AutoFFT==1))) //AutoFFT=0 sets log, other values: 1=Auto on, 2-X = AutoFFT OFF, =FFTgain+1 + {if(Row>241)DisplayDbScale(Row,buffer,0);} + } + + fftx = Row - MIN_X; // starts at 1 + if (fftx < (FFTSize/2)-1) { + val = fi[fftx]; + if (val >= 200) val = 199; + if(PeakFreq>198)PeakFreq=198; + + if(_Mode!=NORHLD){ + + if(fi[fftx+1]>173)TraceShadow(174,fi[fftx+1]+2,buffer); + if(fi[fftx-1]>173)TraceShadow(174,fi[fftx-1]+2,buffer); + + for(i=Y_BASE+1;i173)LCD_Buffer[buffer][i]=BLACK; + if((FlagMeter>0)||((DownConvertMode)&&(FFTt1Mode==0))){ + if ((fftx == imax - 4) || (fftx == imax + 4)) { + for (i=PeakFreq - 1; iLimit)&&(_Det==3)&&(Title[9][0].Value==1) ){ + if(val>ListBottom)val=ListBottom; + } + + __Point_SCR(Row,MIN_Y); + for(i=Y_BASE+1;i= w) && (Row < (w + Width))) { + i = Row - w; + if((*s==0x20)||(*s==33)) b = 0x0000; else b = Get_TAB_8x11(*s, i); //add space and half space characters + for (y = YStart; y < CHAR_HEIGHT; y++) { + if((b << y)& 0x400) { + LCD_Buffer[y0 + y] = Color[COLOR_INDEX & 0x0F]; //Normal replace Display + } else { + LCD_Buffer[y0 + y] = Color[COLOR_INDEX >> 0x8]; //Inverse replace Display + } + } + break; + } + + w += Width; + s++; + } +} + +void VernierMark(u8 buffer,u16 color){ + LCD_Buffer[buffer][Y_SIZE] = color; + LCD_Buffer[buffer][Y_SIZE-1] = color; + LCD_Buffer[buffer][Y_BASE+1] = color; + LCD_Buffer[buffer][Y_BASE] = color; +} + +void LoadBaseBuffers(void){ +u8 i; + + for(i=0;i<201;i++){ + Base2Buffer[i]=BLACK; + Base3Buffer[i]=BLACK; + Base4Buffer[i]=BLACK; + } + Base2Buffer[0]=GRAY; + Base2Buffer[200]=GRAY; + for(i=0;i<201;i+=25)Base3Buffer[i]=GRAY; + for(i=0;i<201;i+=5)Base4Buffer[i]=GRAY; + LoadNwave(); +} + + +void TraceShadow(u8 start,u8 limit,u8 buffer){ +u8 i; + if(limit>199)limit=199; + for(i=start;i198)level=198; + + //RED + if((level>100)&&(level<148)){ //ramp up 1/2 - 3/4, max 3/4 - 1 + r=((level-100)*2)/3; + }else if(level>147)r=31; + + //GREEN + if((level>50)&&(level<98)){ //ramp up 1/4 - 1/2, max 1/2 - 3/4, ramp down 3/4 - 1 + g=((level-50)*4)/3; + }else if(level>150){ + g=((198-level)*4)/3; + }else if(level>97) g=63; + + //BLUE + if(level<48){ //ramp up 0 - 1/4, max 1/4 - 3/4, ramp down 3/4 - 1 + b=(level*2)/3; + }else if(level>150){ + b=((198-level)*2)/3; + }else b=31; + + color=r; + color|=((u16)g<<5); + color|=((u16)b<<11); + return color; +} + +void DrawPixel(u16 x,u8 y, u16 color){ + __Point_SCR(x,y); + __LCD_SetPixl(color); +} + +void DrawBase(u16 x,u16 color){ + DrawPixel(x,MIN_Y-1,color); + DrawPixel(x,MAX_Y+1,color); +} + +u8 UartLogic(void){ + return ((Title[TRACK1][1].Value>2)&&(Title[TRACK1][1].Value<5)&&(_4_source<10)&&(_Mode!=X_Y)&&(!ChartLogic())); +} + +u8 i2cLogic(void){ + return ((Title[TRACK1][1].Value==5)&&(Title[TRACK2][1].Value==3)&&(_4_source<10)&&(_Mode!=X_Y)&&(!ChartLogic())); +} + +u8 SpiLogic(void){ + return ((Title[TRACK1][1].Value==6)&&(Title[TRACK2][1].Value==4)&&(_4_source<10)&&(_Mode!=X_Y)&&(!ChartLogic())); +} + +void UpdateMarkLogic(void){ + if ((_Mode!=X_Y)&&(((_4_source!=SPEC_A)&&(_4_source!=SPEC_B))||(ChartLogic()))) Update_Mark(); +} + +void DisplayDeltaValues(u16 Row, u8 buffer){ +char HalfSpace[2]={'!',0}; + if((FlagMeter==0)&&(DownConvertMode==0)&&((Current==T_VERNIE)||(Current==V_VERNIE))){ + COLOR_INDEX=0x0005+(u16)(_Meas_V_Track<<8); + if(Row>314)Print_Str_Row(Row, LCD_Buffer[buffer],315,184,(char*)DELTA_V[0]); + COLOR_INDEX=0x0500+_Meas_V_Track; + if(Row>338){Print_Str_Row(Row, LCD_Buffer[buffer],339,184,HalfSpace); + Print_Str_Row(Row, LCD_Buffer[buffer],343,184,VNumStr);} + COLOR_INDEX=0x0405; + if(Row>314)Print_Str_Row(Row, LCD_Buffer[buffer],315,169,(char*)DELTA_T[Title[10][2].Value]); + COLOR_INDEX=0x0504; + if(Row>338){Print_Str_Row(Row, LCD_Buffer[buffer],339,169,HalfSpace); + Print_Str_Row(Row, LCD_Buffer[buffer],343,169,TNumStr);} + COLOR_INDEX=0x0503; + } +} + +void DisplayCursorValues(u16 Row, u8 buffer){ + if(CursorDisplaySelect<4){ + COLOR_INDEX=0x0504; + }else if(CursorDisplaySelect<8){ + COLOR_INDEX=0x0500+_Meas_V_Track; + }else{ + COLOR_INDEX=0x0500+_Tr_source; + } + + if(Row<42)Print_Str_Row(Row, LCD_Buffer[buffer],17,189,(char*)CursorTypeStr[CursorDisplaySelect/2]); + if(Row>35){ + if(MinBypass==0){ + Print_Str_Row(Row, LCD_Buffer[buffer],17+(8*3),189,CursorDisplayStr); + }else if(MinBypass==1){ + Print_Str_Row(Row, LCD_Buffer[buffer],17+(8*3),189,CursorDisplayStrM); + Print_Str_Row(Row, LCD_Buffer[buffer],17+(8*7),189,CursorDisplayStr); + }else if(MinBypass==2){ + Print_Str_Row(Row, LCD_Buffer[buffer],17+(8*3),189,CursorDisplayStrH); + Print_Str_Row(Row, LCD_Buffer[buffer],17+(8*7),189,CursorDisplayStrM); + Print_Str_Row(Row, LCD_Buffer[buffer],17+(8*11),189,CursorDisplayStr); + } + } + COLOR_INDEX=0x0503; +} + +/******************************** END OF FILE *********************************/ + diff --git a/FWLib/inc/Command Prompt.lnk b/FWLib/inc/Command Prompt.lnk new file mode 100644 index 0000000..e1d71a7 Binary files /dev/null and b/FWLib/inc/Command Prompt.lnk differ diff --git a/FWLib/inc/cortexm3_macro.h b/FWLib/inc/cortexm3_macro.h new file mode 100644 index 0000000..6adbc3b --- /dev/null +++ b/FWLib/inc/cortexm3_macro.h @@ -0,0 +1,53 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : cortexm3_macro.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : Header file for cortexm3_macro.s. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CORTEXM3_MACRO_H +#define __CORTEXM3_MACRO_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_type.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void __WFI(void); +void __WFE(void); +void __SEV(void); +void __ISB(void); +void __DSB(void); +void __DMB(void); +void __SVC(void); +u32 __MRS_CONTROL(void); +void __MSR_CONTROL(u32 Control); +u32 __MRS_PSP(void); +void __MSR_PSP(u32 TopOfProcessStack); +u32 __MRS_MSP(void); +void __MSR_MSP(u32 TopOfMainStack); +void __RESETPRIMASK(void); +void __SETPRIMASK(void); +u32 __READ_PRIMASK(void); +void __RESETFAULTMASK(void); +void __SETFAULTMASK(void); +u32 __READ_FAULTMASK(void); +void __BASEPRICONFIG(u32 NewPriority); +u32 __GetBASEPRI(void); +u16 __REV_HalfWord(u16 Data); +u32 __REV_Word(u32 Data); + +#endif /* __CORTEXM3_MACRO_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/FWLib/inc/stm32f10x_dac.h b/FWLib/inc/stm32f10x_dac.h new file mode 100644 index 0000000..e93806e --- /dev/null +++ b/FWLib/inc/stm32f10x_dac.h @@ -0,0 +1,167 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_dac.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* DAC firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DAC_H +#define __STM32F10x_DAC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* DAC Init structure definition */ +typedef struct +{ + u32 DAC_Trigger; + u32 DAC_WaveGeneration; + u32 DAC_LFSRUnmask_TriangleAmplitude; + u32 DAC_OutputBuffer; +}DAC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* DAC trigger selection */ +#define DAC_Trigger_None ((u32)0x00000000) +#define DAC_Trigger_T6_TRGO ((u32)0x00000004) +#define DAC_Trigger_T8_TRGO ((u32)0x0000000C) +#define DAC_Trigger_T7_TRGO ((u32)0x00000014) +#define DAC_Trigger_T5_TRGO ((u32)0x0000001C) +#define DAC_Trigger_T2_TRGO ((u32)0x00000024) +#define DAC_Trigger_T4_TRGO ((u32)0x0000002C) +#define DAC_Trigger_Ext_IT9 ((u32)0x00000034) +#define DAC_Trigger_Software ((u32)0x0000003C) + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ + ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ + ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ + ((TRIGGER) == DAC_Trigger_Software)) + +/* DAC wave generation */ +#define DAC_WaveGeneration_None ((u32)0x00000000) +#define DAC_WaveGeneration_Noise ((u32)0x00000040) +#define DAC_WaveGeneration_Triangle ((u32)0x00000080) + +#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ + ((WAVE) == DAC_WaveGeneration_Noise) || \ + ((WAVE) == DAC_WaveGeneration_Triangle)) + +/* DAC noise wave generation mask / triangle wave generation max amplitude */ +#define DAC_LFSRUnmask_Bit0 ((u32)0x00000000) +#define DAC_LFSRUnmask_Bits1_0 ((u32)0x00000100) +#define DAC_LFSRUnmask_Bits2_0 ((u32)0x00000200) +#define DAC_LFSRUnmask_Bits3_0 ((u32)0x00000300) +#define DAC_LFSRUnmask_Bits4_0 ((u32)0x00000400) +#define DAC_LFSRUnmask_Bits5_0 ((u32)0x00000500) +#define DAC_LFSRUnmask_Bits6_0 ((u32)0x00000600) +#define DAC_LFSRUnmask_Bits7_0 ((u32)0x00000700) +#define DAC_LFSRUnmask_Bits8_0 ((u32)0x00000800) +#define DAC_LFSRUnmask_Bits9_0 ((u32)0x00000900) +#define DAC_LFSRUnmask_Bits10_0 ((u32)0x00000A00) +#define DAC_LFSRUnmask_Bits11_0 ((u32)0x00000B00) + +#define DAC_TriangleAmplitude_1 ((u32)0x00000000) +#define DAC_TriangleAmplitude_3 ((u32)0x00000100) +#define DAC_TriangleAmplitude_7 ((u32)0x00000200) +#define DAC_TriangleAmplitude_15 ((u32)0x00000300) +#define DAC_TriangleAmplitude_31 ((u32)0x00000400) +#define DAC_TriangleAmplitude_63 ((u32)0x00000500) +#define DAC_TriangleAmplitude_127 ((u32)0x00000600) +#define DAC_TriangleAmplitude_255 ((u32)0x00000700) +#define DAC_TriangleAmplitude_511 ((u32)0x00000800) +#define DAC_TriangleAmplitude_1023 ((u32)0x00000900) +#define DAC_TriangleAmplitude_2047 ((u32)0x00000A00) +#define DAC_TriangleAmplitude_4095 ((u32)0x00000B00) + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ + ((VALUE) == DAC_TriangleAmplitude_1) || \ + ((VALUE) == DAC_TriangleAmplitude_3) || \ + ((VALUE) == DAC_TriangleAmplitude_7) || \ + ((VALUE) == DAC_TriangleAmplitude_15) || \ + ((VALUE) == DAC_TriangleAmplitude_31) || \ + ((VALUE) == DAC_TriangleAmplitude_63) || \ + ((VALUE) == DAC_TriangleAmplitude_127) || \ + ((VALUE) == DAC_TriangleAmplitude_255) || \ + ((VALUE) == DAC_TriangleAmplitude_511) || \ + ((VALUE) == DAC_TriangleAmplitude_1023) || \ + ((VALUE) == DAC_TriangleAmplitude_2047) || \ + ((VALUE) == DAC_TriangleAmplitude_4095)) + +/* DAC output buffer */ +#define DAC_OutputBuffer_Enable ((u32)0x00000000) +#define DAC_OutputBuffer_Disable ((u32)0x00000002) + +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ + ((STATE) == DAC_OutputBuffer_Disable)) + +/* DAC Channel selection */ +#define DAC_Channel_1 ((u32)0x00000000) +#define DAC_Channel_2 ((u32)0x00000010) + +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ + ((CHANNEL) == DAC_Channel_2)) + +/* DAC data alignement */ +#define DAC_Align_12b_R ((u32)0x00000000) +#define DAC_Align_12b_L ((u32)0x00000004) +#define DAC_Align_8b_R ((u32)0x00000008) + +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ + ((ALIGN) == DAC_Align_12b_L) || \ + ((ALIGN) == DAC_Align_8b_R)) + +/* DAC wave generation */ +#define DAC_Wave_Noise ((u32)0x00000040) +#define DAC_Wave_Triangle ((u32)0x00000080) + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ + ((WAVE) == DAC_Wave_Triangle)) + +/* DAC data ------------------------------------------------------------------*/ +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +void DAC_DeInit(void); +void DAC_Init(u32 DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(u32 DAC_Channel, FunctionalState NewState); +void DAC_DMACmd(u32 DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(u32 DAC_Channel, FunctionalState NewState); +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); +void DAC_WaveGenerationCmd(u32 DAC_Channel, u32 DAC_Wave, FunctionalState NewState); +void DAC_SetChannel1Data(u32 DAC_Align, u16 Data); +void DAC_SetChannel2Data(u32 DAC_Align, u16 Data); +void DAC_SetDualChannelData(u32 DAC_Align, u16 Data2, u16 Data1); +u16 DAC_GetDataOutputValue(u32 DAC_Channel); + +#endif /*__STM32F10x_DAC_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/FWLib/inc/stm32f10x_dma.h b/FWLib/inc/stm32f10x_dma.h new file mode 100644 index 0000000..ac81f31 --- /dev/null +++ b/FWLib/inc/stm32f10x_dma.h @@ -0,0 +1,297 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_dma.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* DMA firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DMA_H +#define __STM32F10x_DMA_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* DMA Init structure definition */ +typedef struct +{ + u32 DMA_PeripheralBaseAddr; + u32 DMA_MemoryBaseAddr; + u32 DMA_DIR; + u32 DMA_BufferSize; + u32 DMA_PeripheralInc; + u32 DMA_MemoryInc; + u32 DMA_PeripheralDataSize; + u32 DMA_MemoryDataSize; + u32 DMA_Mode; + u32 DMA_Priority; + u32 DMA_M2M; +}DMA_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +#define IS_DMA_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == DMA1_Channel1_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA1_Channel2_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA1_Channel3_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA1_Channel4_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA1_Channel5_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA1_Channel6_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA1_Channel7_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA2_Channel1_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA2_Channel2_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA2_Channel3_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA2_Channel4_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA2_Channel5_BASE)) + +/* DMA data transfer direction -----------------------------------------------*/ +#define DMA_DIR_PeripheralDST ((u32)0x00000010) +#define DMA_DIR_PeripheralSRC ((u32)0x00000000) + +#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ + ((DIR) == DMA_DIR_PeripheralSRC)) + +/* DMA peripheral incremented mode -------------------------------------------*/ +#define DMA_PeripheralInc_Enable ((u32)0x00000040) +#define DMA_PeripheralInc_Disable ((u32)0x00000000) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ + ((STATE) == DMA_PeripheralInc_Disable)) + +/* DMA memory incremented mode -----------------------------------------------*/ +#define DMA_MemoryInc_Enable ((u32)0x00000080) +#define DMA_MemoryInc_Disable ((u32)0x00000000) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ + ((STATE) == DMA_MemoryInc_Disable)) + +/* DMA peripheral data size --------------------------------------------------*/ +#define DMA_PeripheralDataSize_Byte ((u32)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((u32)0x00000100) +#define DMA_PeripheralDataSize_Word ((u32)0x00000200) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ + ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ + ((SIZE) == DMA_PeripheralDataSize_Word)) + +/* DMA memory data size ------------------------------------------------------*/ +#define DMA_MemoryDataSize_Byte ((u32)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((u32)0x00000400) +#define DMA_MemoryDataSize_Word ((u32)0x00000800) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ + ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ + ((SIZE) == DMA_MemoryDataSize_Word)) + +/* DMA circular/normal mode --------------------------------------------------*/ +#define DMA_Mode_Circular ((u32)0x00000020) +#define DMA_Mode_Normal ((u32)0x00000000) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) + +/* DMA priority level --------------------------------------------------------*/ +#define DMA_Priority_VeryHigh ((u32)0x00003000) +#define DMA_Priority_High ((u32)0x00002000) +#define DMA_Priority_Medium ((u32)0x00001000) +#define DMA_Priority_Low ((u32)0x00000000) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ + ((PRIORITY) == DMA_Priority_High) || \ + ((PRIORITY) == DMA_Priority_Medium) || \ + ((PRIORITY) == DMA_Priority_Low)) + +/* DMA memory to memory ------------------------------------------------------*/ +#define DMA_M2M_Enable ((u32)0x00004000) +#define DMA_M2M_Disable ((u32)0x00000000) + +#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) + +/* DMA interrupts definition -------------------------------------------------*/ +#define DMA_IT_TC ((u32)0x00000002) +#define DMA_IT_HT ((u32)0x00000004) +#define DMA_IT_TE ((u32)0x00000008) + +#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) + +/* For DMA1 */ +#define DMA1_IT_GL1 ((u32)0x00000001) +#define DMA1_IT_TC1 ((u32)0x00000002) +#define DMA1_IT_HT1 ((u32)0x00000004) +#define DMA1_IT_TE1 ((u32)0x00000008) +#define DMA1_IT_GL2 ((u32)0x00000010) +#define DMA1_IT_TC2 ((u32)0x00000020) +#define DMA1_IT_HT2 ((u32)0x00000040) +#define DMA1_IT_TE2 ((u32)0x00000080) +#define DMA1_IT_GL3 ((u32)0x00000100) +#define DMA1_IT_TC3 ((u32)0x00000200) +#define DMA1_IT_HT3 ((u32)0x00000400) +#define DMA1_IT_TE3 ((u32)0x00000800) +#define DMA1_IT_GL4 ((u32)0x00001000) +#define DMA1_IT_TC4 ((u32)0x00002000) +#define DMA1_IT_HT4 ((u32)0x00004000) +#define DMA1_IT_TE4 ((u32)0x00008000) +#define DMA1_IT_GL5 ((u32)0x00010000) +#define DMA1_IT_TC5 ((u32)0x00020000) +#define DMA1_IT_HT5 ((u32)0x00040000) +#define DMA1_IT_TE5 ((u32)0x00080000) +#define DMA1_IT_GL6 ((u32)0x00100000) +#define DMA1_IT_TC6 ((u32)0x00200000) +#define DMA1_IT_HT6 ((u32)0x00400000) +#define DMA1_IT_TE6 ((u32)0x00800000) +#define DMA1_IT_GL7 ((u32)0x01000000) +#define DMA1_IT_TC7 ((u32)0x02000000) +#define DMA1_IT_HT7 ((u32)0x04000000) +#define DMA1_IT_TE7 ((u32)0x08000000) +/* For DMA2 */ +#define DMA2_IT_GL1 ((u32)0x10000001) +#define DMA2_IT_TC1 ((u32)0x10000002) +#define DMA2_IT_HT1 ((u32)0x10000004) +#define DMA2_IT_TE1 ((u32)0x10000008) +#define DMA2_IT_GL2 ((u32)0x10000010) +#define DMA2_IT_TC2 ((u32)0x10000020) +#define DMA2_IT_HT2 ((u32)0x10000040) +#define DMA2_IT_TE2 ((u32)0x10000080) +#define DMA2_IT_GL3 ((u32)0x10000100) +#define DMA2_IT_TC3 ((u32)0x10000200) +#define DMA2_IT_HT3 ((u32)0x10000400) +#define DMA2_IT_TE3 ((u32)0x10000800) +#define DMA2_IT_GL4 ((u32)0x10001000) +#define DMA2_IT_TC4 ((u32)0x10002000) +#define DMA2_IT_HT4 ((u32)0x10004000) +#define DMA2_IT_TE4 ((u32)0x10008000) +#define DMA2_IT_GL5 ((u32)0x10010000) +#define DMA2_IT_TC5 ((u32)0x10020000) +#define DMA2_IT_HT5 ((u32)0x10040000) +#define DMA2_IT_TE5 ((u32)0x10080000) + +#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) +#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ + ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ + ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ + ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ + ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ + ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ + ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ + ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ + ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ + ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ + ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ + ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ + ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ + ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ + ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ + ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ + ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ + ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ + ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ + ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ + ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ + ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ + ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ + ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) + +/* DMA flags definition ------------------------------------------------------*/ +/* For DMA1 */ +#define DMA1_FLAG_GL1 ((u32)0x00000001) +#define DMA1_FLAG_TC1 ((u32)0x00000002) +#define DMA1_FLAG_HT1 ((u32)0x00000004) +#define DMA1_FLAG_TE1 ((u32)0x00000008) +#define DMA1_FLAG_GL2 ((u32)0x00000010) +#define DMA1_FLAG_TC2 ((u32)0x00000020) +#define DMA1_FLAG_HT2 ((u32)0x00000040) +#define DMA1_FLAG_TE2 ((u32)0x00000080) +#define DMA1_FLAG_GL3 ((u32)0x00000100) +#define DMA1_FLAG_TC3 ((u32)0x00000200) +#define DMA1_FLAG_HT3 ((u32)0x00000400) +#define DMA1_FLAG_TE3 ((u32)0x00000800) +#define DMA1_FLAG_GL4 ((u32)0x00001000) +#define DMA1_FLAG_TC4 ((u32)0x00002000) +#define DMA1_FLAG_HT4 ((u32)0x00004000) +#define DMA1_FLAG_TE4 ((u32)0x00008000) +#define DMA1_FLAG_GL5 ((u32)0x00010000) +#define DMA1_FLAG_TC5 ((u32)0x00020000) +#define DMA1_FLAG_HT5 ((u32)0x00040000) +#define DMA1_FLAG_TE5 ((u32)0x00080000) +#define DMA1_FLAG_GL6 ((u32)0x00100000) +#define DMA1_FLAG_TC6 ((u32)0x00200000) +#define DMA1_FLAG_HT6 ((u32)0x00400000) +#define DMA1_FLAG_TE6 ((u32)0x00800000) +#define DMA1_FLAG_GL7 ((u32)0x01000000) +#define DMA1_FLAG_TC7 ((u32)0x02000000) +#define DMA1_FLAG_HT7 ((u32)0x04000000) +#define DMA1_FLAG_TE7 ((u32)0x08000000) +/* For DMA2 */ +#define DMA2_FLAG_GL1 ((u32)0x10000001) +#define DMA2_FLAG_TC1 ((u32)0x10000002) +#define DMA2_FLAG_HT1 ((u32)0x10000004) +#define DMA2_FLAG_TE1 ((u32)0x10000008) +#define DMA2_FLAG_GL2 ((u32)0x10000010) +#define DMA2_FLAG_TC2 ((u32)0x10000020) +#define DMA2_FLAG_HT2 ((u32)0x10000040) +#define DMA2_FLAG_TE2 ((u32)0x10000080) +#define DMA2_FLAG_GL3 ((u32)0x10000100) +#define DMA2_FLAG_TC3 ((u32)0x10000200) +#define DMA2_FLAG_HT3 ((u32)0x10000400) +#define DMA2_FLAG_TE3 ((u32)0x10000800) +#define DMA2_FLAG_GL4 ((u32)0x10001000) +#define DMA2_FLAG_TC4 ((u32)0x10002000) +#define DMA2_FLAG_HT4 ((u32)0x10004000) +#define DMA2_FLAG_TE4 ((u32)0x10008000) +#define DMA2_FLAG_GL5 ((u32)0x10010000) +#define DMA2_FLAG_TC5 ((u32)0x10020000) +#define DMA2_FLAG_HT5 ((u32)0x10040000) +#define DMA2_FLAG_TE5 ((u32)0x10080000) + +#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) +#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ + ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ + ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ + ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ + ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ + ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ + ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ + ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ + ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ + ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ + ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ + ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ + ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ + ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ + ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ + ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ + ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ + ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ + ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ + ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ + ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ + ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ + ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ + ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) + +/* DMA Buffer Size -----------------------------------------------------------*/ +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, u32 DMA_IT, FunctionalState NewState); +u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG); +void DMA_ClearFlag(u32 DMA_FLAG); +ITStatus DMA_GetITStatus(u32 DMA_IT); +void DMA_ClearITPendingBit(u32 DMA_IT); + +#endif /*__STM32F10x_DMA_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/FWLib/inc/stm32f10x_flash.h b/FWLib/inc/stm32f10x_flash.h new file mode 100644 index 0000000..ccee6b8 --- /dev/null +++ b/FWLib/inc/stm32f10x_flash.h @@ -0,0 +1,208 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_flash.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* FLASH firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FLASH_H +#define __STM32F10x_FLASH_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +#ifdef _FLASH_PROG +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT +}FLASH_Status; +#endif + +/* Flash Latency -------------------------------------------------------------*/ +#define FLASH_Latency_0 ((u32)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((u32)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((u32)0x00000002) /* FLASH Two Latency cycles */ + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ + ((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2)) + +/* Half Cycle Enable/Disable -------------------------------------------------*/ +#define FLASH_HalfCycleAccess_Enable ((u32)0x00000008) /* FLASH Half Cycle Enable */ +#define FLASH_HalfCycleAccess_Disable ((u32)0x00000000) /* FLASH Half Cycle Disable */ + +#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ + ((STATE) == FLASH_HalfCycleAccess_Disable)) + + +/* Prefetch Buffer Enable/Disable --------------------------------------------*/ +#define FLASH_PrefetchBuffer_Enable ((u32)0x00000010) /* FLASH Prefetch Buffer Enable */ +#define FLASH_PrefetchBuffer_Disable ((u32)0x00000000) /* FLASH Prefetch Buffer Disable */ + +#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ + ((STATE) == FLASH_PrefetchBuffer_Disable)) + +#ifdef _FLASH_PROG +/* Option Bytes Write Protection ---------------------------------------------*/ +/* Values to be used with STM32F10Xxx Medium-density devices: FLASH memory density + ranges between 32 and 128 Kbytes with page size equal to 1 Kbytes */ +#define FLASH_WRProt_Pages0to3 ((u32)0x00000001) /* Write protection of page 0 to 3 */ +#define FLASH_WRProt_Pages4to7 ((u32)0x00000002) /* Write protection of page 4 to 7 */ +#define FLASH_WRProt_Pages8to11 ((u32)0x00000004) /* Write protection of page 8 to 11 */ +#define FLASH_WRProt_Pages12to15 ((u32)0x00000008) /* Write protection of page 12 to 15 */ +#define FLASH_WRProt_Pages16to19 ((u32)0x00000010) /* Write protection of page 16 to 19 */ +#define FLASH_WRProt_Pages20to23 ((u32)0x00000020) /* Write protection of page 20 to 23 */ +#define FLASH_WRProt_Pages24to27 ((u32)0x00000040) /* Write protection of page 24 to 27 */ +#define FLASH_WRProt_Pages28to31 ((u32)0x00000080) /* Write protection of page 28 to 31 */ +#define FLASH_WRProt_Pages32to35 ((u32)0x00000100) /* Write protection of page 32 to 35 */ +#define FLASH_WRProt_Pages36to39 ((u32)0x00000200) /* Write protection of page 36 to 39 */ +#define FLASH_WRProt_Pages40to43 ((u32)0x00000400) /* Write protection of page 40 to 43 */ +#define FLASH_WRProt_Pages44to47 ((u32)0x00000800) /* Write protection of page 44 to 47 */ +#define FLASH_WRProt_Pages48to51 ((u32)0x00001000) /* Write protection of page 48 to 51 */ +#define FLASH_WRProt_Pages52to55 ((u32)0x00002000) /* Write protection of page 52 to 55 */ +#define FLASH_WRProt_Pages56to59 ((u32)0x00004000) /* Write protection of page 56 to 59 */ +#define FLASH_WRProt_Pages60to63 ((u32)0x00008000) /* Write protection of page 60 to 63 */ +#define FLASH_WRProt_Pages64to67 ((u32)0x00010000) /* Write protection of page 64 to 67 */ +#define FLASH_WRProt_Pages68to71 ((u32)0x00020000) /* Write protection of page 68 to 71 */ +#define FLASH_WRProt_Pages72to75 ((u32)0x00040000) /* Write protection of page 72 to 75 */ +#define FLASH_WRProt_Pages76to79 ((u32)0x00080000) /* Write protection of page 76 to 79 */ +#define FLASH_WRProt_Pages80to83 ((u32)0x00100000) /* Write protection of page 80 to 83 */ +#define FLASH_WRProt_Pages84to87 ((u32)0x00200000) /* Write protection of page 84 to 87 */ +#define FLASH_WRProt_Pages88to91 ((u32)0x00400000) /* Write protection of page 88 to 91 */ +#define FLASH_WRProt_Pages92to95 ((u32)0x00800000) /* Write protection of page 92 to 95 */ +#define FLASH_WRProt_Pages96to99 ((u32)0x01000000) /* Write protection of page 96 to 99 */ +#define FLASH_WRProt_Pages100to103 ((u32)0x02000000) /* Write protection of page 100 to 103 */ +#define FLASH_WRProt_Pages104to107 ((u32)0x04000000) /* Write protection of page 104 to 107 */ +#define FLASH_WRProt_Pages108to111 ((u32)0x08000000) /* Write protection of page 108 to 111 */ +#define FLASH_WRProt_Pages112to115 ((u32)0x10000000) /* Write protection of page 112 to 115 */ +#define FLASH_WRProt_Pages116to119 ((u32)0x20000000) /* Write protection of page 115 to 119 */ +#define FLASH_WRProt_Pages120to123 ((u32)0x40000000) /* Write protection of page 120 to 123 */ +#define FLASH_WRProt_Pages124to127 ((u32)0x80000000) /* Write protection of page 124 to 127 */ +/* Values to be used with STM32F10Xxx High-density devices: FLASH memory density + ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */ +#define FLASH_WRProt_Pages0to1 ((u32)0x00000001) /* Write protection of page 0 to 1 */ +#define FLASH_WRProt_Pages2to3 ((u32)0x00000002) /* Write protection of page 2 to 3 */ +#define FLASH_WRProt_Pages4to5 ((u32)0x00000004) /* Write protection of page 4 to 5 */ +#define FLASH_WRProt_Pages6to7 ((u32)0x00000008) /* Write protection of page 6 to 7 */ +#define FLASH_WRProt_Pages8to9 ((u32)0x00000010) /* Write protection of page 8 to 9 */ +#define FLASH_WRProt_Pages10to11 ((u32)0x00000020) /* Write protection of page 10 to 11 */ +#define FLASH_WRProt_Pages12to13 ((u32)0x00000040) /* Write protection of page 12 to 13 */ +#define FLASH_WRProt_Pages14to15 ((u32)0x00000080) /* Write protection of page 14 to 15 */ +#define FLASH_WRProt_Pages16to17 ((u32)0x00000100) /* Write protection of page 16 to 17 */ +#define FLASH_WRProt_Pages18to19 ((u32)0x00000200) /* Write protection of page 18 to 19 */ +#define FLASH_WRProt_Pages20to21 ((u32)0x00000400) /* Write protection of page 20 to 21 */ +#define FLASH_WRProt_Pages22to23 ((u32)0x00000800) /* Write protection of page 22 to 23 */ +#define FLASH_WRProt_Pages24to25 ((u32)0x00001000) /* Write protection of page 24 to 25 */ +#define FLASH_WRProt_Pages26to27 ((u32)0x00002000) /* Write protection of page 26 to 27 */ +#define FLASH_WRProt_Pages28to29 ((u32)0x00004000) /* Write protection of page 28 to 29 */ +#define FLASH_WRProt_Pages30to31 ((u32)0x00008000) /* Write protection of page 30 to 31 */ +#define FLASH_WRProt_Pages32to33 ((u32)0x00010000) /* Write protection of page 32 to 33 */ +#define FLASH_WRProt_Pages34to35 ((u32)0x00020000) /* Write protection of page 34 to 35 */ +#define FLASH_WRProt_Pages36to37 ((u32)0x00040000) /* Write protection of page 36 to 37 */ +#define FLASH_WRProt_Pages38to39 ((u32)0x00080000) /* Write protection of page 38 to 39 */ +#define FLASH_WRProt_Pages40to41 ((u32)0x00100000) /* Write protection of page 40 to 41 */ +#define FLASH_WRProt_Pages42to43 ((u32)0x00200000) /* Write protection of page 42 to 43 */ +#define FLASH_WRProt_Pages44to45 ((u32)0x00400000) /* Write protection of page 44 to 45 */ +#define FLASH_WRProt_Pages46to47 ((u32)0x00800000) /* Write protection of page 46 to 47 */ +#define FLASH_WRProt_Pages48to49 ((u32)0x01000000) /* Write protection of page 48 to 49 */ +#define FLASH_WRProt_Pages50to51 ((u32)0x02000000) /* Write protection of page 50 to 51 */ +#define FLASH_WRProt_Pages52to53 ((u32)0x04000000) /* Write protection of page 52 to 53 */ +#define FLASH_WRProt_Pages54to55 ((u32)0x08000000) /* Write protection of page 54 to 55 */ +#define FLASH_WRProt_Pages56to57 ((u32)0x10000000) /* Write protection of page 56 to 57 */ +#define FLASH_WRProt_Pages58to59 ((u32)0x20000000) /* Write protection of page 58 to 59 */ +#define FLASH_WRProt_Pages60to61 ((u32)0x40000000) /* Write protection of page 60 to 61 */ +#define FLASH_WRProt_Pages62to255 ((u32)0x80000000) /* Write protection of page 62 to 255 */ +#define FLASH_WRProt_AllPages ((u32)0xFFFFFFFF) /* Write protection of all Pages */ + +#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) + +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF)) +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) + +/* Option Bytes IWatchdog ----------------------------------------------------*/ +#define OB_IWDG_SW ((u16)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((u16)0x0000) /* Hardware IWDG selected */ + +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +/* Option Bytes nRST_STOP ----------------------------------------------------*/ +#define OB_STOP_NoRST ((u16)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((u16)0x0000) /* Reset generated when entering in STOP */ + +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) + +/* Option Bytes nRST_STDBY ---------------------------------------------------*/ +#define OB_STDBY_NoRST ((u16)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((u16)0x0000) /* Reset generated when entering in STANDBY */ + +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) + +/* FLASH Interrupts ----------------------------------------------------------*/ +#define FLASH_IT_ERROR ((u32)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((u32)0x00001000) /* End of FLASH Operation Interrupt source */ + +#define IS_FLASH_IT(IT) ((((IT) & (u32)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) + +/* FLASH Flags ---------------------------------------------------------------*/ +#define FLASH_FLAG_BSY ((u32)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((u32)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((u32)0x00000004) /* FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((u32)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((u32)0x00000001) /* FLASH Option Byte error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) + +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ + ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_OPTERR)) +#endif + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void FLASH_SetLatency(u32 FLASH_Latency); +void FLASH_HalfCycleAccessCmd(u32 FLASH_HalfCycleAccess); +void FLASH_PrefetchBufferCmd(u32 FLASH_PrefetchBuffer); + +#ifdef _FLASH_PROG +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(u32 Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(u32 Address, u32 Data); +FLASH_Status FLASH_ProgramHalfWord(u32 Address, u16 Data); +FLASH_Status FLASH_ProgramOptionByteData(u32 Address, u8 Data); +FLASH_Status FLASH_EnableWriteProtection(u32 FLASH_Pages); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(u16 OB_IWDG, u16 OB_STOP, u16 OB_STDBY); +u32 FLASH_GetUserOptionByte(void); +u32 FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +FlagStatus FLASH_GetPrefetchBufferStatus(void); +void FLASH_ITConfig(u16 FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(u16 FLASH_FLAG); +void FLASH_ClearFlag(u16 FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(u32 Timeout); +#endif + +#endif /* __STM32F10x_FLASH_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/FWLib/inc/stm32f10x_fsmc.h b/FWLib/inc/stm32f10x_fsmc.h new file mode 100644 index 0000000..fa0925e --- /dev/null +++ b/FWLib/inc/stm32f10x_fsmc.h @@ -0,0 +1,345 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_fsmc.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* FSMC firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FSMC_H +#define __STM32F10x_FSMC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Timing parameters For NOR/SRAM Banks */ +typedef struct +{ + u32 FSMC_AddressSetupTime; + u32 FSMC_AddressHoldTime; + u32 FSMC_DataSetupTime; + u32 FSMC_BusTurnAroundDuration; + u32 FSMC_CLKDivision; + u32 FSMC_DataLatency; + u32 FSMC_AccessMode; +}FSMC_NORSRAMTimingInitTypeDef; + +/* FSMC NOR/SRAM Init structure definition */ +typedef struct +{ + u32 FSMC_Bank; + u32 FSMC_DataAddressMux; + u32 FSMC_MemoryType; + u32 FSMC_MemoryDataWidth; + u32 FSMC_BurstAccessMode; + u32 FSMC_WaitSignalPolarity; + u32 FSMC_WrapMode; + u32 FSMC_WaitSignalActive; + u32 FSMC_WriteOperation; + u32 FSMC_WaitSignal; + u32 FSMC_ExtendedMode; + u32 FSMC_WriteBurst; + /* Timing Parameters for write and read access if the ExtendedMode is not used*/ + FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; + /* Timing Parameters for write access if the ExtendedMode is used*/ + FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; +}FSMC_NORSRAMInitTypeDef; + +/* Timing parameters For FSMC NAND and PCCARD Banks */ +typedef struct +{ + u32 FSMC_SetupTime; + u32 FSMC_WaitSetupTime; + u32 FSMC_HoldSetupTime; + u32 FSMC_HiZSetupTime; +}FSMC_NAND_PCCARDTimingInitTypeDef; + +/* FSMC NAND Init structure definition */ +typedef struct +{ + u32 FSMC_Bank; + u32 FSMC_Waitfeature; + u32 FSMC_MemoryDataWidth; + u32 FSMC_ECC; + u32 FSMC_ECCPageSize; + u32 FSMC_AddressLowMapping; + u32 FSMC_TCLRSetupTime; + u32 FSMC_TARSetupTime; + /* FSMC Common Space Timing */ + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; + /* FSMC Attribute Space Timing */ + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; +}FSMC_NANDInitTypeDef; + +/* FSMC PCCARD Init structure definition */ +typedef struct +{ + u32 FSMC_Waitfeature; + u32 FSMC_AddressLowMapping; + u32 FSMC_TCLRSetupTime; + u32 FSMC_TARSetupTime; + /* FSMC Common Space Timing */ + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; + /* FSMC Attribute Space Timing */ + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; + /* FSMC IO Space Timing */ + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; +}FSMC_PCCARDInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/*-------------------------------FSMC Banks definitions ----------------------*/ +#define FSMC_Bank1_NORSRAM1 ((u32)0x00000000) +#define FSMC_Bank1_NORSRAM2 ((u32)0x00000002) +#define FSMC_Bank1_NORSRAM3 ((u32)0x00000004) +#define FSMC_Bank1_NORSRAM4 ((u32)0x00000006) +#define FSMC_Bank2_NAND ((u32)0x00000010) +#define FSMC_Bank3_NAND ((u32)0x00000100) +#define FSMC_Bank4_PCCARD ((u32)0x00001000) + +#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ + ((BANK) == FSMC_Bank1_NORSRAM2) || \ + ((BANK) == FSMC_Bank1_NORSRAM3) || \ + ((BANK) == FSMC_Bank1_NORSRAM4)) + + +#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND)) + +#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + + +/*------------------------------- NOR/SRAM Banks -----------------------------*/ +/* FSMC Data/Address Bus Multiplexing ----------------------------------------*/ +#define FSMC_DataAddressMux_Disable ((u32)0x00000000) +#define FSMC_DataAddressMux_Enable ((u32)0x00000002) + +#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ + ((MUX) == FSMC_DataAddressMux_Enable)) + +/* FSMC Memory Type ----------------------------------------------------------*/ +#define FSMC_MemoryType_SRAM ((u32)0x00000000) +#define FSMC_MemoryType_PSRAM ((u32)0x00000004) +#define FSMC_MemoryType_NOR ((u32)0x00000008) + +#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ + ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ + ((MEMORY) == FSMC_MemoryType_NOR)) + +/* FSMC Data Width ----------------------------------------------------------*/ +#define FSMC_MemoryDataWidth_8b ((u32)0x00000000) +#define FSMC_MemoryDataWidth_16b ((u32)0x00000010) + +#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ + ((WIDTH) == FSMC_MemoryDataWidth_16b)) + + +/* FSMC Burst Access Mode ----------------------------------------------------*/ +#define FSMC_BurstAccessMode_Disable ((u32)0x00000000) +#define FSMC_BurstAccessMode_Enable ((u32)0x00000100) + +#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ + ((STATE) == FSMC_BurstAccessMode_Enable)) + +/* FSMC Wait Signal Polarity -------------------------------------------------*/ +#define FSMC_WaitSignalPolarity_Low ((u32)0x00000000) +#define FSMC_WaitSignalPolarity_High ((u32)0x00000200) + +#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ + ((POLARITY) == FSMC_WaitSignalPolarity_High)) + +/* FSMC Wrap Mode ------------------------------------------------------------*/ +#define FSMC_WrapMode_Disable ((u32)0x00000000) +#define FSMC_WrapMode_Enable ((u32)0x00000400) + +#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ + ((MODE) == FSMC_WrapMode_Enable)) + +/* FSMC Wait Timing ----------------------------------------------------------*/ +#define FSMC_WaitSignalActive_BeforeWaitState ((u32)0x00000000) +#define FSMC_WaitSignalActive_DuringWaitState ((u32)0x00000800) + +#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ + ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) + +/* FSMC Write Operation ------------------------------------------------------*/ +#define FSMC_WriteOperation_Disable ((u32)0x00000000) +#define FSMC_WriteOperation_Enable ((u32)0x00001000) + +#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ + ((OPERATION) == FSMC_WriteOperation_Enable)) + +/* FSMC Wait Signal ----------------------------------------------------------*/ +#define FSMC_WaitSignal_Disable ((u32)0x00000000) +#define FSMC_WaitSignal_Enable ((u32)0x00002000) + +#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ + ((SIGNAL) == FSMC_WaitSignal_Enable)) + +/* FSMC Extended Mode --------------------------------------------------------*/ +#define FSMC_ExtendedMode_Disable ((u32)0x00000000) +#define FSMC_ExtendedMode_Enable ((u32)0x00004000) + +#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ + ((MODE) == FSMC_ExtendedMode_Enable)) + +/* FSMC Write Burst ----------------------------------------------------------*/ +#define FSMC_WriteBurst_Disable ((u32)0x00000000) +#define FSMC_WriteBurst_Enable ((u32)0x00080000) + +#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ + ((BURST) == FSMC_WriteBurst_Enable)) + +/* FSMC Address Setup Time ---------------------------------------------------*/ +#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) + +/* FSMC Address Hold Time ----------------------------------------------------*/ +#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) + +/* FSMC Data Setup Time ------------------------------------------------------*/ +#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) + +/* FSMC Bus Turn around Duration ---------------------------------------------*/ +#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) + +/* FSMC CLK Division ---------------------------------------------------------*/ +#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) + +/* FSMC Data Latency ---------------------------------------------------------*/ +#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) + +/* FSMC Access Mode ----------------------------------------------------------*/ +#define FSMC_AccessMode_A ((u32)0x00000000) +#define FSMC_AccessMode_B ((u32)0x10000000) +#define FSMC_AccessMode_C ((u32)0x20000000) +#define FSMC_AccessMode_D ((u32)0x30000000) + +#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ + ((MODE) == FSMC_AccessMode_B) || \ + ((MODE) == FSMC_AccessMode_C) || \ + ((MODE) == FSMC_AccessMode_D)) + +/*----------------------------- NAND and PCCARD Banks ------------------------*/ +/* FSMC Wait feature ---------------------------------------------------------*/ +#define FSMC_Waitfeature_Disable ((u32)0x00000000) +#define FSMC_Waitfeature_Enable ((u32)0x00000002) + +#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ + ((FEATURE) == FSMC_Waitfeature_Enable)) + +/* FSMC Memory Data Width ----------------------------------------------------*/ +#define FSMC_MemoryDataWidth_8b ((u32)0x00000000) +#define FSMC_MemoryDataWidth_16b ((u32)0x00000010) + +#define IS_FSMC_DATA_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ + ((WIDTH) == FSMC_MemoryDataWidth_16b)) + +/* FSMC ECC ------------------------------------------------------------------*/ +#define FSMC_ECC_Disable ((u32)0x00000000) +#define FSMC_ECC_Enable ((u32)0x00000040) + +#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ + ((STATE) == FSMC_ECC_Enable)) + +/* FSMC ECC Page Size --------------------------------------------------------*/ +#define FSMC_ECCPageSize_256Bytes ((u32)0x00000000) +#define FSMC_ECCPageSize_512Bytes ((u32)0x00020000) +#define FSMC_ECCPageSize_1024Bytes ((u32)0x00040000) +#define FSMC_ECCPageSize_2048Bytes ((u32)0x00060000) +#define FSMC_ECCPageSize_4096Bytes ((u32)0x00080000) +#define FSMC_ECCPageSize_8192Bytes ((u32)0x000A0000) + +#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_8192Bytes)) + +/* FSMC Address Low Mapping --------------------------------------------------*/ +#define FSMC_AddressLowMapping_Direct ((u32)0x00000000) +#define FSMC_AddressLowMapping_InDirect ((u32)0x00000100) + +#define IS_FSMC_ADDRESS_LOW_MAPPING(MAPPING) (((MAPPING) == FSMC_AddressLowMapping_Direct) || \ + ((MAPPING) == FSMC_AddressLowMapping_InDirect)) +/* FSMC TCLR Setup Time ------------------------------------------------------*/ +#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) + +/* FSMC TAR Setup Time -------------------------------------------------------*/ +#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) + +/* FSMC Setup Time ----------------------------------------------------*/ +#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) + +/* FSMC Wait Setup Time -----------------------------------------------*/ +#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) + +/* FSMC Hold Setup Time -----------------------------------------------*/ +#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) + +/* FSMC HiZ Setup Time ------------------------------------------------*/ +#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) + +/* FSMC Interrupt sources ----------------------------------------------------*/ +#define FSMC_IT_RisingEdge ((u32)0x00000008) +#define FSMC_IT_Level ((u32)0x00000010) +#define FSMC_IT_FallingEdge ((u32)0x00000020) + +#define IS_FSMC_IT(IT) ((((IT) & (u32)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) + +#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ + ((IT) == FSMC_IT_Level) || \ + ((IT) == FSMC_IT_FallingEdge)) + +/* FSMC Flags ----------------------------------------------------------------*/ +#define FSMC_FLAG_RisingEdge ((u32)0x00000001) +#define FSMC_FLAG_Level ((u32)0x00000002) +#define FSMC_FLAG_FallingEdge ((u32)0x00000004) +#define FSMC_FLAG_FEMPT ((u32)0x00000040) + +#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ + ((FLAG) == FSMC_FLAG_Level) || \ + ((FLAG) == FSMC_FLAG_FallingEdge) || \ + ((FLAG) == FSMC_FLAG_FEMPT)) + +#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void FSMC_NORSRAMDeInit(u32 FSMC_Bank); +void FSMC_NANDDeInit(u32 FSMC_Bank); +void FSMC_PCCARDDeInit(void); +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMCmd(u32 FSMC_Bank, FunctionalState NewState); +void FSMC_NANDCmd(u32 FSMC_Bank, FunctionalState NewState); +void FSMC_PCCARDCmd(FunctionalState NewState); +void FSMC_NANDECCCmd(u32 FSMC_Bank, FunctionalState NewState); +u32 FSMC_GetECC(u32 FSMC_Bank); +void FSMC_ITConfig(u32 FSMC_Bank, u32 FSMC_IT, FunctionalState NewState); +FlagStatus FSMC_GetFlagStatus(u32 FSMC_Bank, u32 FSMC_FLAG); +void FSMC_ClearFlag(u32 FSMC_Bank, u32 FSMC_FLAG); +ITStatus FSMC_GetITStatus(u32 FSMC_Bank, u32 FSMC_IT); +void FSMC_ClearITPendingBit(u32 FSMC_Bank, u32 FSMC_IT); + +#endif /*__STM32F10x_FSMC_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/FWLib/inc/stm32f10x_gpio.h b/FWLib/inc/stm32f10x_gpio.h new file mode 100644 index 0000000..a1a7b45 --- /dev/null +++ b/FWLib/inc/stm32f10x_gpio.h @@ -0,0 +1,237 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_gpio.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* GPIO firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_GPIO_H +#define __STM32F10x_GPIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +#define IS_GPIO_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == GPIOA_BASE) || \ + ((*(u32*)&(PERIPH)) == GPIOB_BASE) || \ + ((*(u32*)&(PERIPH)) == GPIOC_BASE) || \ + ((*(u32*)&(PERIPH)) == GPIOD_BASE) || \ + ((*(u32*)&(PERIPH)) == GPIOE_BASE) || \ + ((*(u32*)&(PERIPH)) == GPIOF_BASE) || \ + ((*(u32*)&(PERIPH)) == GPIOG_BASE)) + +/* Output Maximum frequency selection ----------------------------------------*/ +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +}GPIOSpeed_TypeDef; + +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ + ((SPEED) == GPIO_Speed_50MHz)) + +/* Configuration Mode enumeration --------------------------------------------*/ +typedef enum +{ GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +}GPIOMode_TypeDef; + +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ + ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ + ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ + ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) + +/* GPIO Init structure definition */ +typedef struct +{ + u16 GPIO_Pin; + GPIOSpeed_TypeDef GPIO_Speed; + GPIOMode_TypeDef GPIO_Mode; +}GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration -----------------------------------------*/ +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) + +/* Exported constants --------------------------------------------------------*/ +/* GPIO pins define ----------------------------------------------------------*/ +#define GPIO_Pin_0 ((u16)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((u16)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((u16)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((u16)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((u16)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((u16)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((u16)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((u16)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((u16)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((u16)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((u16)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((u16)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((u16)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((u16)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((u16)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((u16)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((u16)0xFFFF) /* All pins selected */ + +#define IS_GPIO_PIN(PIN) ((((PIN) & (u16)0x00) == 0x00) && ((PIN) != (u16)0x00)) + +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) + +/* GPIO Remap define ---------------------------------------------------------*/ +#define GPIO_Remap_SPI1 ((u32)0x00000001) /* SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((u32)0x00000002) /* I2C1 Alternate Function mapping */ +#define GPIO_Remap_USART1 ((u32)0x00000004) /* USART1 Alternate Function mapping */ +#define GPIO_Remap_USART2 ((u32)0x00000008) /* USART2 Alternate Function mapping */ +#define GPIO_PartialRemap_USART3 ((u32)0x00140010) /* USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((u32)0x00140030) /* USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((u32)0x00160040) /* TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((u32)0x001600C0) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((u32)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((u32)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((u32)0x00180300) /* TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((u32)0x001A0800) /* TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((u32)0x001A0C00) /* TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((u32)0x00001000) /* TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN ((u32)0x001D4000) /* CAN Alternate Function mapping */ +#define GPIO_Remap2_CAN ((u32)0x001D6000) /* CAN Alternate Function mapping */ +#define GPIO_Remap_PD01 ((u32)0x00008000) /* PD01 Alternate Function mapping */ +#define GPIO_Remap_TIM5CH4_LSI ((u32)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */ +#define GPIO_Remap_ADC1_ETRGINJ ((u32)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((u32)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGINJ ((u32)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGREG ((u32)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_SWJ_NoJTRST ((u32)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ +#define GPIO_Remap_SWJ_JTAGDisable ((u32)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */ +#define GPIO_Remap_SWJ_Disable ((u32)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */ + + +#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ + ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ + ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ + ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ + ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ + ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ + ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ + ((REMAP) == GPIO_Remap1_CAN) || ((REMAP) == GPIO_Remap2_CAN) || \ + ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ + ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ + ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ + ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| \ + ((REMAP) == GPIO_Remap_SWJ_Disable)) + +/* GPIO Port Sources ---------------------------------------------------------*/ +#define GPIO_PortSourceGPIOA ((u8)0x00) +#define GPIO_PortSourceGPIOB ((u8)0x01) +#define GPIO_PortSourceGPIOC ((u8)0x02) +#define GPIO_PortSourceGPIOD ((u8)0x03) +#define GPIO_PortSourceGPIOE ((u8)0x04) +#define GPIO_PortSourceGPIOF ((u8)0x05) +#define GPIO_PortSourceGPIOG ((u8)0x06) + +#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOE)) + +#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOG)) + +/* GPIO Pin sources ----------------------------------------------------------*/ +#define GPIO_PinSource0 ((u8)0x00) +#define GPIO_PinSource1 ((u8)0x01) +#define GPIO_PinSource2 ((u8)0x02) +#define GPIO_PinSource3 ((u8)0x03) +#define GPIO_PinSource4 ((u8)0x04) +#define GPIO_PinSource5 ((u8)0x05) +#define GPIO_PinSource6 ((u8)0x06) +#define GPIO_PinSource7 ((u8)0x07) +#define GPIO_PinSource8 ((u8)0x08) +#define GPIO_PinSource9 ((u8)0x09) +#define GPIO_PinSource10 ((u8)0x0A) +#define GPIO_PinSource11 ((u8)0x0B) +#define GPIO_PinSource12 ((u8)0x0C) +#define GPIO_PinSource13 ((u8)0x0D) +#define GPIO_PinSource14 ((u8)0x0E) +#define GPIO_PinSource15 ((u8)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ + ((PINSOURCE) == GPIO_PinSource1) || \ + ((PINSOURCE) == GPIO_PinSource2) || \ + ((PINSOURCE) == GPIO_PinSource3) || \ + ((PINSOURCE) == GPIO_PinSource4) || \ + ((PINSOURCE) == GPIO_PinSource5) || \ + ((PINSOURCE) == GPIO_PinSource6) || \ + ((PINSOURCE) == GPIO_PinSource7) || \ + ((PINSOURCE) == GPIO_PinSource8) || \ + ((PINSOURCE) == GPIO_PinSource9) || \ + ((PINSOURCE) == GPIO_PinSource10) || \ + ((PINSOURCE) == GPIO_PinSource11) || \ + ((PINSOURCE) == GPIO_PinSource12) || \ + ((PINSOURCE) == GPIO_PinSource13) || \ + ((PINSOURCE) == GPIO_PinSource14) || \ + ((PINSOURCE) == GPIO_PinSource15)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); +u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); +u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); +void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource); + +#endif /* __STM32F10x_GPIO_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/FWLib/inc/stm32f10x_lib.h b/FWLib/inc/stm32f10x_lib.h new file mode 100644 index 0000000..0c63477 --- /dev/null +++ b/FWLib/inc/stm32f10x_lib.h @@ -0,0 +1,124 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_lib.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file includes the peripherals header files in the +* user application. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_LIB_H +#define __STM32F10x_LIB_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +#ifdef _ADC + #include "stm32f10x_adc.h" +#endif /*_ADC */ + +#ifdef _BKP + #include "stm32f10x_bkp.h" +#endif /*_BKP */ + +#ifdef _CAN + #include "stm32f10x_can.h" +#endif /*_CAN */ + +#ifdef _CRC + #include "stm32f10x_crc.h" +#endif /*_CRC */ + +#ifdef _DAC + #include "stm32f10x_dac.h" +#endif /*_DAC */ + +#ifdef _DBGMCU + #include "stm32f10x_dbgmcu.h" +#endif /*_DBGMCU */ + +#ifdef _DMA + #include "stm32f10x_dma.h" +#endif /*_DMA */ + +#ifdef _EXTI + #include "stm32f10x_exti.h" +#endif /*_EXTI */ + +#ifdef _FLASH + #include "stm32f10x_flash.h" +#endif /*_FLASH */ + +#ifdef _FSMC + #include "stm32f10x_fsmc.h" +#endif /*_FSMC */ + +#ifdef _GPIO + #include "stm32f10x_gpio.h" +#endif /*_GPIO */ + +#ifdef _I2C + #include "stm32f10x_i2c.h" +#endif /*_I2C */ + +#ifdef _IWDG + #include "stm32f10x_iwdg.h" +#endif /*_IWDG */ + +#ifdef _NVIC + #include "stm32f10x_nvic.h" +#endif /*_NVIC */ + +#ifdef _PWR + #include "stm32f10x_pwr.h" +#endif /*_PWR */ + +#ifdef _RCC + #include "stm32f10x_rcc.h" +#endif /*_RCC */ + +#ifdef _RTC + #include "stm32f10x_rtc.h" +#endif /*_RTC */ + +#ifdef _SDIO + #include "stm32f10x_sdio.h" +#endif /*_SDIO */ + +#ifdef _SPI + #include "stm32f10x_spi.h" +#endif /*_SPI */ + +#ifdef _SysTick + #include "stm32f10x_systick.h" +#endif /*_SysTick */ + +#ifdef _TIM + #include "stm32f10x_tim.h" +#endif /*_TIM */ + +#ifdef _USART + #include "stm32f10x_usart.h" +#endif /*_USART */ + +#ifdef _WWDG + #include "stm32f10x_wwdg.h" +#endif /*_WWDG */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void debug(void); + +#endif /* __STM32F10x_LIB_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/FWLib/inc/stm32f10x_map.h b/FWLib/inc/stm32f10x_map.h new file mode 100644 index 0000000..d3dec16 --- /dev/null +++ b/FWLib/inc/stm32f10x_map.h @@ -0,0 +1,7603 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_map.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the peripheral register's definitions, +* bits definitions and memory mapping. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_MAP_H +#define __STM32F10x_MAP_H + +#ifndef EXT + #define EXT extern +#endif /* EXT */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_conf.h" +#include "stm32f10x_type.h" +#include "cortexm3_macro.h" + +/* Exported types ------------------------------------------------------------*/ +/******************************************************************************/ +/* Peripheral registers structures */ +/******************************************************************************/ + +/*------------------------ Analog to Digital Converter -----------------------*/ +typedef struct +{ + vu32 SR; + vu32 CR1; + vu32 CR2; + vu32 SMPR1; + vu32 SMPR2; + vu32 JOFR1; + vu32 JOFR2; + vu32 JOFR3; + vu32 JOFR4; + vu32 HTR; + vu32 LTR; + vu32 SQR1; + vu32 SQR2; + vu32 SQR3; + vu32 JSQR; + vu32 JDR1; + vu32 JDR2; + vu32 JDR3; + vu32 JDR4; + vu32 DR; +} ADC_TypeDef; + +/*------------------------ Backup Registers ----------------------------------*/ +typedef struct +{ + u32 RESERVED0; + vu16 DR1; + u16 RESERVED1; + vu16 DR2; + u16 RESERVED2; + vu16 DR3; + u16 RESERVED3; + vu16 DR4; + u16 RESERVED4; + vu16 DR5; + u16 RESERVED5; + vu16 DR6; + u16 RESERVED6; + vu16 DR7; + u16 RESERVED7; + vu16 DR8; + u16 RESERVED8; + vu16 DR9; + u16 RESERVED9; + vu16 DR10; + u16 RESERVED10; + vu16 RTCCR; + u16 RESERVED11; + vu16 CR; + u16 RESERVED12; + vu16 CSR; + u16 RESERVED13[5]; + vu16 DR11; + u16 RESERVED14; + vu16 DR12; + u16 RESERVED15; + vu16 DR13; + u16 RESERVED16; + vu16 DR14; + u16 RESERVED17; + vu16 DR15; + u16 RESERVED18; + vu16 DR16; + u16 RESERVED19; + vu16 DR17; + u16 RESERVED20; + vu16 DR18; + u16 RESERVED21; + vu16 DR19; + u16 RESERVED22; + vu16 DR20; + u16 RESERVED23; + vu16 DR21; + u16 RESERVED24; + vu16 DR22; + u16 RESERVED25; + vu16 DR23; + u16 RESERVED26; + vu16 DR24; + u16 RESERVED27; + vu16 DR25; + u16 RESERVED28; + vu16 DR26; + u16 RESERVED29; + vu16 DR27; + u16 RESERVED30; + vu16 DR28; + u16 RESERVED31; + vu16 DR29; + u16 RESERVED32; + vu16 DR30; + u16 RESERVED33; + vu16 DR31; + u16 RESERVED34; + vu16 DR32; + u16 RESERVED35; + vu16 DR33; + u16 RESERVED36; + vu16 DR34; + u16 RESERVED37; + vu16 DR35; + u16 RESERVED38; + vu16 DR36; + u16 RESERVED39; + vu16 DR37; + u16 RESERVED40; + vu16 DR38; + u16 RESERVED41; + vu16 DR39; + u16 RESERVED42; + vu16 DR40; + u16 RESERVED43; + vu16 DR41; + u16 RESERVED44; + vu16 DR42; + u16 RESERVED45; +} BKP_TypeDef; + +/*------------------------ Controller Area Network ---------------------------*/ +typedef struct +{ + vu32 TIR; + vu32 TDTR; + vu32 TDLR; + vu32 TDHR; +} CAN_TxMailBox_TypeDef; + +typedef struct +{ + vu32 RIR; + vu32 RDTR; + vu32 RDLR; + vu32 RDHR; +} CAN_FIFOMailBox_TypeDef; + +typedef struct +{ + vu32 FR1; + vu32 FR2; +} CAN_FilterRegister_TypeDef; + +typedef struct +{ + vu32 MCR; + vu32 MSR; + vu32 TSR; + vu32 RF0R; + vu32 RF1R; + vu32 IER; + vu32 ESR; + vu32 BTR; + u32 RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + u32 RESERVED1[12]; + vu32 FMR; + vu32 FM1R; + u32 RESERVED2; + vu32 FS1R; + u32 RESERVED3; + vu32 FFA1R; + u32 RESERVED4; + vu32 FA1R; + u32 RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[14]; +} CAN_TypeDef; + +/*------------------------ CRC calculation unit ------------------------------*/ +typedef struct +{ + vu32 DR; + vu8 IDR; + u8 RESERVED0; + u16 RESERVED1; + vu32 CR; +} CRC_TypeDef; + + +/*------------------------ Digital to Analog Converter -----------------------*/ +typedef struct +{ + vu32 CR; + vu32 SWTRIGR; + vu32 DHR12R1; + vu32 DHR12L1; + vu32 DHR8R1; + vu32 DHR12R2; + vu32 DHR12L2; + vu32 DHR8R2; + vu32 DHR12RD; + vu32 DHR12LD; + vu32 DHR8RD; + vu32 DOR1; + vu32 DOR2; +} DAC_TypeDef; + +/*------------------------ Debug MCU -----------------------------------------*/ +typedef struct +{ + vu32 IDCODE; + vu32 CR; +}DBGMCU_TypeDef; + +/*------------------------ DMA Controller ------------------------------------*/ +typedef struct +{ + vu32 CCR; + vu32 CNDTR; + vu32 CPAR; + vu32 CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + vu32 ISR; + vu32 IFCR; +} DMA_TypeDef; + +/*------------------------ External Interrupt/Event Controller ---------------*/ +typedef struct +{ + vu32 IMR; + vu32 EMR; + vu32 RTSR; + vu32 FTSR; + vu32 SWIER; + vu32 PR; +} EXTI_TypeDef; + +/*------------------------ FLASH and Option Bytes Registers ------------------*/ +typedef struct +{ + vu32 ACR; + vu32 KEYR; + vu32 OPTKEYR; + vu32 SR; + vu32 CR; + vu32 AR; + vu32 RESERVED; + vu32 OBR; + vu32 WRPR; +} FLASH_TypeDef; + +typedef struct +{ + vu16 RDP; + vu16 USER; + vu16 Data0; + vu16 Data1; + vu16 WRP0; + vu16 WRP1; + vu16 WRP2; + vu16 WRP3; +} OB_TypeDef; + +/*------------------------ Flexible Static Memory Controller -----------------*/ +typedef struct +{ + vu32 BTCR[8]; +} FSMC_Bank1_TypeDef; + +typedef struct +{ + vu32 BWTR[7]; +} FSMC_Bank1E_TypeDef; + +typedef struct +{ + vu32 PCR2; + vu32 SR2; + vu32 PMEM2; + vu32 PATT2; + u32 RESERVED0; + vu32 ECCR2; +} FSMC_Bank2_TypeDef; + +typedef struct +{ + vu32 PCR3; + vu32 SR3; + vu32 PMEM3; + vu32 PATT3; + u32 RESERVED0; + vu32 ECCR3; +} FSMC_Bank3_TypeDef; + +typedef struct +{ + vu32 PCR4; + vu32 SR4; + vu32 PMEM4; + vu32 PATT4; + vu32 PIO4; +} FSMC_Bank4_TypeDef; + +/*------------------------ General Purpose and Alternate Function IO ---------*/ +typedef struct +{ + vu32 CRL; + vu32 CRH; + vu32 IDR; + vu32 ODR; + vu32 BSRR; + vu32 BRR; + vu32 LCKR; +} GPIO_TypeDef; + +typedef struct +{ + vu32 EVCR; + vu32 MAPR; + vu32 EXTICR[4]; +} AFIO_TypeDef; + +/*------------------------ Inter-integrated Circuit Interface ----------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 OAR1; + u16 RESERVED2; + vu16 OAR2; + u16 RESERVED3; + vu16 DR; + u16 RESERVED4; + vu16 SR1; + u16 RESERVED5; + vu16 SR2; + u16 RESERVED6; + vu16 CCR; + u16 RESERVED7; + vu16 TRISE; + u16 RESERVED8; +} I2C_TypeDef; + +/*------------------------ Independent WATCHDOG ------------------------------*/ +typedef struct +{ + vu32 KR; + vu32 PR; + vu32 RLR; + vu32 SR; +} IWDG_TypeDef; + +/*------------------------ Nested Vectored Interrupt Controller --------------*/ +typedef struct +{ + vu32 ISER[2]; + u32 RESERVED0[30]; + vu32 ICER[2]; + u32 RSERVED1[30]; + vu32 ISPR[2]; + u32 RESERVED2[30]; + vu32 ICPR[2]; + u32 RESERVED3[30]; + vu32 IABR[2]; + u32 RESERVED4[62]; + vu32 IPR[15]; +} NVIC_TypeDef; + +typedef struct +{ + vuc32 CPUID; + vu32 ICSR; + vu32 VTOR; + vu32 AIRCR; + vu32 SCR; + vu32 CCR; + vu32 SHPR[3]; + vu32 SHCSR; + vu32 CFSR; + vu32 HFSR; + vu32 DFSR; + vu32 MMFAR; + vu32 BFAR; + vu32 AFSR; +} SCB_TypeDef; + +/*------------------------ Power Control -------------------------------------*/ +typedef struct +{ + vu32 CR; + vu32 CSR; +} PWR_TypeDef; + +/*------------------------ Reset and Clock Control ---------------------------*/ +typedef struct +{ + vu32 CR; + vu32 CFGR; + vu32 CIR; + vu32 APB2RSTR; + vu32 APB1RSTR; + vu32 AHBENR; + vu32 APB2ENR; + vu32 APB1ENR; + vu32 BDCR; + vu32 CSR; +} RCC_TypeDef; + +/*------------------------ Real-Time Clock -----------------------------------*/ +typedef struct +{ + vu16 CRH; + u16 RESERVED0; + vu16 CRL; + u16 RESERVED1; + vu16 PRLH; + u16 RESERVED2; + vu16 PRLL; + u16 RESERVED3; + vu16 DIVH; + u16 RESERVED4; + vu16 DIVL; + u16 RESERVED5; + vu16 CNTH; + u16 RESERVED6; + vu16 CNTL; + u16 RESERVED7; + vu16 ALRH; + u16 RESERVED8; + vu16 ALRL; + u16 RESERVED9; +} RTC_TypeDef; + +/*------------------------ SD host Interface ---------------------------------*/ +typedef struct +{ + vu32 POWER; + vu32 CLKCR; + vu32 ARG; + vu32 CMD; + vuc32 RESPCMD; + vuc32 RESP1; + vuc32 RESP2; + vuc32 RESP3; + vuc32 RESP4; + vu32 DTIMER; + vu32 DLEN; + vu32 DCTRL; + vuc32 DCOUNT; + vuc32 STA; + vu32 ICR; + vu32 MASK; + u32 RESERVED0[2]; + vuc32 FIFOCNT; + u32 RESERVED1[13]; + vu32 FIFO; +} SDIO_TypeDef; + +/*------------------------ Serial Peripheral Interface -----------------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 SR; + u16 RESERVED2; + vu16 DR; + u16 RESERVED3; + vu16 CRCPR; + u16 RESERVED4; + vu16 RXCRCR; + u16 RESERVED5; + vu16 TXCRCR; + u16 RESERVED6; + vu16 I2SCFGR; + u16 RESERVED7; + vu16 I2SPR; + u16 RESERVED8; +} SPI_TypeDef; + +/*------------------------ SystemTick ----------------------------------------*/ +typedef struct +{ + vu32 CTRL; + vu32 LOAD; + vu32 VAL; + vuc32 CALIB; +} SysTick_TypeDef; + +/*------------------------ TIM -----------------------------------------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 SMCR; + u16 RESERVED2; + vu16 DIER; + u16 RESERVED3; + vu16 SR; + u16 RESERVED4; + vu16 EGR; + u16 RESERVED5; + vu16 CCMR1; + u16 RESERVED6; + vu16 CCMR2; + u16 RESERVED7; + vu16 CCER; + u16 RESERVED8; + vu16 CNT; + u16 RESERVED9; + vu16 PSC; + u16 RESERVED10; + vu16 ARR; + u16 RESERVED11; + vu16 RCR; + u16 RESERVED12; + vu16 CCR1; + u16 RESERVED13; + vu16 CCR2; + u16 RESERVED14; + vu16 CCR3; + u16 RESERVED15; + vu16 CCR4; + u16 RESERVED16; + vu16 BDTR; + u16 RESERVED17; + vu16 DCR; + u16 RESERVED18; + vu16 DMAR; + u16 RESERVED19; +} TIM_TypeDef; + +/*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/ +typedef struct +{ + vu16 SR; + u16 RESERVED0; + vu16 DR; + u16 RESERVED1; + vu16 BRR; + u16 RESERVED2; + vu16 CR1; + u16 RESERVED3; + vu16 CR2; + u16 RESERVED4; + vu16 CR3; + u16 RESERVED5; + vu16 GTPR; + u16 RESERVED6; +} USART_TypeDef; + +/*------------------------ Window WATCHDOG -----------------------------------*/ +typedef struct +{ + vu32 CR; + vu32 CFR; + vu32 SR; +} WWDG_TypeDef; + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Peripheral and SRAM base address in the alias region */ +#define PERIPH_BB_BASE ((u32)0x42000000) +#define SRAM_BB_BASE ((u32)0x22000000) + +/* Peripheral and SRAM base address in the bit-band region */ +#define SRAM_BASE ((u32)0x20000000) +#define PERIPH_BASE ((u32)0x40000000) + +/* FSMC registers base address */ +#define FSMC_R_BASE ((u32)0xA0000000) + +/* Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN_BASE (APB1PERIPH_BASE + 0x6400) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) + +#define SDIO_BASE (PERIPH_BASE + 0x18000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) + +/* Flash registers base address */ +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) +/* Flash Option Bytes base address */ +#define OB_BASE ((u32)0x1FFFF800) + +/* FSMC Bankx registers base address */ +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((u32)0xE0042000) + +/* System Control Space memory map */ +#define SCS_BASE ((u32)0xE000E000) + +#define SysTick_BASE (SCS_BASE + 0x0010) +#define NVIC_BASE (SCS_BASE + 0x0100) +#define SCB_BASE (SCS_BASE + 0x0D00) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ + +/*------------------------ Non Debug Mode ------------------------------------*/ +#ifndef DEBUG +#ifdef _TIM2 + #define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#endif /*_TIM2 */ + +#ifdef _TIM3 + #define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#endif /*_TIM3 */ + +#ifdef _TIM4 + #define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#endif /*_TIM4 */ + +#ifdef _TIM5 + #define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#endif /*_TIM5 */ + +#ifdef _TIM6 + #define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#endif /*_TIM6 */ + +#ifdef _TIM7 + #define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#endif /*_TIM7 */ + +#ifdef _RTC + #define RTC ((RTC_TypeDef *) RTC_BASE) +#endif /*_RTC */ + +#ifdef _WWDG + #define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#endif /*_WWDG */ + +#ifdef _IWDG + #define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#endif /*_IWDG */ + +#ifdef _SPI2 + #define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#endif /*_SPI2 */ + +#ifdef _SPI3 + #define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#endif /*_SPI3 */ + +#ifdef _USART2 + #define USART2 ((USART_TypeDef *) USART2_BASE) +#endif /*_USART2 */ + +#ifdef _USART3 + #define USART3 ((USART_TypeDef *) USART3_BASE) +#endif /*_USART3 */ + +#ifdef _UART4 + #define UART4 ((USART_TypeDef *) UART4_BASE) +#endif /*_UART4 */ + +#ifdef _UART5 + #define UART5 ((USART_TypeDef *) UART5_BASE) +#endif /*_USART5 */ + +#ifdef _I2C1 + #define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#endif /*_I2C1 */ + +#ifdef _I2C2 + #define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#endif /*_I2C2 */ + +#ifdef _CAN + #define CAN ((CAN_TypeDef *) CAN_BASE) +#endif /*_CAN */ + +#ifdef _BKP + #define BKP ((BKP_TypeDef *) BKP_BASE) +#endif /*_BKP */ + +#ifdef _PWR + #define PWR ((PWR_TypeDef *) PWR_BASE) +#endif /*_PWR */ + +#ifdef _DAC + #define DAC ((DAC_TypeDef *) DAC_BASE) +#endif /*_DAC */ + +#ifdef _AFIO + #define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#endif /*_AFIO */ + +#ifdef _EXTI + #define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#endif /*_EXTI */ + +#ifdef _GPIOA + #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#endif /*_GPIOA */ + +#ifdef _GPIOB + #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#endif /*_GPIOB */ + +#ifdef _GPIOC + #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#endif /*_GPIOC */ + +#ifdef _GPIOD + #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#endif /*_GPIOD */ + +#ifdef _GPIOE + #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#endif /*_GPIOE */ + +#ifdef _GPIOF + #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#endif /*_GPIOF */ + +#ifdef _GPIOG + #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#endif /*_GPIOG */ + +#ifdef _ADC1 + #define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#endif /*_ADC1 */ + +#ifdef _ADC2 + #define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#endif /*_ADC2 */ + +#ifdef _TIM1 + #define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#endif /*_TIM1 */ + +#ifdef _SPI1 + #define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#endif /*_SPI1 */ + +#ifdef _TIM8 + #define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#endif /*_TIM8 */ + +#ifdef _USART1 + #define USART1 ((USART_TypeDef *) USART1_BASE) +#endif /*_USART1 */ + +#ifdef _ADC3 + #define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#endif /*_ADC3 */ + +#ifdef _SDIO + #define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#endif /*_SDIO */ + +#ifdef _DMA + #define DMA1 ((DMA_TypeDef *) DMA1_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#endif /*_DMA */ + +#ifdef _DMA1_Channel1 + #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#endif /*_DMA1_Channel1 */ + +#ifdef _DMA1_Channel2 + #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#endif /*_DMA1_Channel2 */ + +#ifdef _DMA1_Channel3 + #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#endif /*_DMA1_Channel3 */ + +#ifdef _DMA1_Channel4 + #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#endif /*_DMA1_Channel4 */ + +#ifdef _DMA1_Channel5 + #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#endif /*_DMA1_Channel5 */ + +#ifdef _DMA1_Channel6 + #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#endif /*_DMA1_Channel6 */ + +#ifdef _DMA1_Channel7 + #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#endif /*_DMA1_Channel7 */ + +#ifdef _DMA2_Channel1 + #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#endif /*_DMA2_Channel1 */ + +#ifdef _DMA2_Channel2 + #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#endif /*_DMA2_Channel2 */ + +#ifdef _DMA2_Channel3 + #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#endif /*_DMA2_Channel3 */ + +#ifdef _DMA2_Channel4 + #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#endif /*_DMA2_Channel4 */ + +#ifdef _DMA2_Channel5 + #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#endif /*_DMA2_Channel5 */ + +#ifdef _RCC + #define RCC ((RCC_TypeDef *) RCC_BASE) +#endif /*_RCC */ + +#ifdef _CRC + #define CRC ((CRC_TypeDef *) CRC_BASE) +#endif /*_CRC */ + +#ifdef _FLASH + #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) + #define OB ((OB_TypeDef *) OB_BASE) +#endif /*_FLASH */ + +#ifdef _FSMC + #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) + #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) + #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) + #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) + #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#endif /*_FSMC */ + +#ifdef _DBGMCU + #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#endif /*_DBGMCU */ + +#ifdef _SysTick + #define SysTick ((SysTick_TypeDef *) SysTick_BASE) +#endif /*_SysTick */ + +#ifdef _NVIC + #define NVIC ((NVIC_TypeDef *) NVIC_BASE) + #define SCB ((SCB_TypeDef *) SCB_BASE) +#endif /*_NVIC */ + +/*------------------------ Debug Mode ----------------------------------------*/ +#else /* DEBUG */ +#ifdef _TIM2 + EXT TIM_TypeDef *TIM2; +#endif /*_TIM2 */ + +#ifdef _TIM3 + EXT TIM_TypeDef *TIM3; +#endif /*_TIM3 */ + +#ifdef _TIM4 + EXT TIM_TypeDef *TIM4; +#endif /*_TIM4 */ + +#ifdef _TIM5 + EXT TIM_TypeDef *TIM5; +#endif /*_TIM5 */ + +#ifdef _TIM6 + EXT TIM_TypeDef *TIM6; +#endif /*_TIM6 */ + +#ifdef _TIM7 + EXT TIM_TypeDef *TIM7; +#endif /*_TIM7 */ + +#ifdef _RTC + EXT RTC_TypeDef *RTC; +#endif /*_RTC */ + +#ifdef _WWDG + EXT WWDG_TypeDef *WWDG; +#endif /*_WWDG */ + +#ifdef _IWDG + EXT IWDG_TypeDef *IWDG; +#endif /*_IWDG */ + +#ifdef _SPI2 + EXT SPI_TypeDef *SPI2; +#endif /*_SPI2 */ + +#ifdef _SPI3 + EXT SPI_TypeDef *SPI3; +#endif /*_SPI3 */ + +#ifdef _USART2 + EXT USART_TypeDef *USART2; +#endif /*_USART2 */ + +#ifdef _USART3 + EXT USART_TypeDef *USART3; +#endif /*_USART3 */ + +#ifdef _UART4 + EXT USART_TypeDef *UART4; +#endif /*_UART4 */ + +#ifdef _UART5 + EXT USART_TypeDef *UART5; +#endif /*_UART5 */ + +#ifdef _I2C1 + EXT I2C_TypeDef *I2C1; +#endif /*_I2C1 */ + +#ifdef _I2C2 + EXT I2C_TypeDef *I2C2; +#endif /*_I2C2 */ + +#ifdef _CAN + EXT CAN_TypeDef *CAN; +#endif /*_CAN */ + +#ifdef _BKP + EXT BKP_TypeDef *BKP; +#endif /*_BKP */ + +#ifdef _PWR + EXT PWR_TypeDef *PWR; +#endif /*_PWR */ + +#ifdef _DAC + EXT DAC_TypeDef *DAC; +#endif /*_DAC */ + +#ifdef _AFIO + EXT AFIO_TypeDef *AFIO; +#endif /*_AFIO */ + +#ifdef _EXTI + EXT EXTI_TypeDef *EXTI; +#endif /*_EXTI */ + +#ifdef _GPIOA + EXT GPIO_TypeDef *GPIOA; +#endif /*_GPIOA */ + +#ifdef _GPIOB + EXT GPIO_TypeDef *GPIOB; +#endif /*_GPIOB */ + +#ifdef _GPIOC + EXT GPIO_TypeDef *GPIOC; +#endif /*_GPIOC */ + +#ifdef _GPIOD + EXT GPIO_TypeDef *GPIOD; +#endif /*_GPIOD */ + +#ifdef _GPIOE + EXT GPIO_TypeDef *GPIOE; +#endif /*_GPIOE */ + +#ifdef _GPIOF + EXT GPIO_TypeDef *GPIOF; +#endif /*_GPIOF */ + +#ifdef _GPIOG + EXT GPIO_TypeDef *GPIOG; +#endif /*_GPIOG */ + +#ifdef _ADC1 + EXT ADC_TypeDef *ADC1; +#endif /*_ADC1 */ + +#ifdef _ADC2 + EXT ADC_TypeDef *ADC2; +#endif /*_ADC2 */ + +#ifdef _TIM1 + EXT TIM_TypeDef *TIM1; +#endif /*_TIM1 */ + +#ifdef _SPI1 + EXT SPI_TypeDef *SPI1; +#endif /*_SPI1 */ + +#ifdef _TIM8 + EXT TIM_TypeDef *TIM8; +#endif /*_TIM8 */ + +#ifdef _USART1 + EXT USART_TypeDef *USART1; +#endif /*_USART1 */ + +#ifdef _ADC3 + EXT ADC_TypeDef *ADC3; +#endif /*_ADC3 */ + +#ifdef _SDIO + EXT SDIO_TypeDef *SDIO; +#endif /*_SDIO */ + +#ifdef _DMA + EXT DMA_TypeDef *DMA1; + EXT DMA_TypeDef *DMA2; +#endif /*_DMA */ + +#ifdef _DMA1_Channel1 + EXT DMA_Channel_TypeDef *DMA1_Channel1; +#endif /*_DMA1_Channel1 */ + +#ifdef _DMA1_Channel2 + EXT DMA_Channel_TypeDef *DMA1_Channel2; +#endif /*_DMA1_Channel2 */ + +#ifdef _DMA1_Channel3 + EXT DMA_Channel_TypeDef *DMA1_Channel3; +#endif /*_DMA1_Channel3 */ + +#ifdef _DMA1_Channel4 + EXT DMA_Channel_TypeDef *DMA1_Channel4; +#endif /*_DMA1_Channel4 */ + +#ifdef _DMA1_Channel5 + EXT DMA_Channel_TypeDef *DMA1_Channel5; +#endif /*_DMA1_Channel5 */ + +#ifdef _DMA1_Channel6 + EXT DMA_Channel_TypeDef *DMA1_Channel6; +#endif /*_DMA1_Channel6 */ + +#ifdef _DMA1_Channel7 + EXT DMA_Channel_TypeDef *DMA1_Channel7; +#endif /*_DMA1_Channel7 */ + +#ifdef _DMA2_Channel1 + EXT DMA_Channel_TypeDef *DMA2_Channel1; +#endif /*_DMA2_Channel1 */ + +#ifdef _DMA2_Channel2 + EXT DMA_Channel_TypeDef *DMA2_Channel2; +#endif /*_DMA2_Channel2 */ + +#ifdef _DMA2_Channel3 + EXT DMA_Channel_TypeDef *DMA2_Channel3; +#endif /*_DMA2_Channel3 */ + +#ifdef _DMA2_Channel4 + EXT DMA_Channel_TypeDef *DMA2_Channel4; +#endif /*_DMA2_Channel4 */ + +#ifdef _DMA2_Channel5 + EXT DMA_Channel_TypeDef *DMA2_Channel5; +#endif /*_DMA2_Channel5 */ + +#ifdef _RCC + EXT RCC_TypeDef *RCC; +#endif /*_RCC */ + +#ifdef _CRC + EXT CRC_TypeDef *CRC; +#endif /*_CRC */ + +#ifdef _FLASH + EXT FLASH_TypeDef *FLASH; + EXT OB_TypeDef *OB; +#endif /*_FLASH */ + +#ifdef _FSMC + EXT FSMC_Bank1_TypeDef *FSMC_Bank1; + EXT FSMC_Bank1E_TypeDef *FSMC_Bank1E; + EXT FSMC_Bank2_TypeDef *FSMC_Bank2; + EXT FSMC_Bank3_TypeDef *FSMC_Bank3; + EXT FSMC_Bank4_TypeDef *FSMC_Bank4; +#endif /*_FSMC */ + +#ifdef _DBGMCU + EXT DBGMCU_TypeDef *DBGMCU; +#endif /*_DBGMCU */ + +#ifdef _SysTick + EXT SysTick_TypeDef *SysTick; +#endif /*_SysTick */ + +#ifdef _NVIC + EXT NVIC_TypeDef *NVIC; + EXT SCB_TypeDef *SCB; +#endif /*_NVIC */ + +#endif /* DEBUG */ + +/* Exported constants --------------------------------------------------------*/ +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((u32)0xFFFFFFFF) /* Data register bits */ + + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((u8)0xFF) /* General-purpose 8-bit data register bits */ + + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((u8)0x01) /* RESET bit */ + + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPDS ((u16)0x0001) /* Low-Power Deepsleep */ +#define PWR_CR_PDDS ((u16)0x0002) /* Power Down Deepsleep */ +#define PWR_CR_CWUF ((u16)0x0004) /* Clear Wakeup Flag */ +#define PWR_CR_CSBF ((u16)0x0008) /* Clear Standby Flag */ +#define PWR_CR_PVDE ((u16)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CR_PLS ((u16)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 ((u16)0x0020) /* Bit 0 */ +#define PWR_CR_PLS_1 ((u16)0x0040) /* Bit 1 */ +#define PWR_CR_PLS_2 ((u16)0x0080) /* Bit 2 */ + +/* PVD level configuration */ +#define PWR_CR_PLS_2V2 ((u16)0x0000) /* PVD level 2.2V */ +#define PWR_CR_PLS_2V3 ((u16)0x0020) /* PVD level 2.3V */ +#define PWR_CR_PLS_2V4 ((u16)0x0040) /* PVD level 2.4V */ +#define PWR_CR_PLS_2V5 ((u16)0x0060) /* PVD level 2.5V */ +#define PWR_CR_PLS_2V6 ((u16)0x0080) /* PVD level 2.6V */ +#define PWR_CR_PLS_2V7 ((u16)0x00A0) /* PVD level 2.7V */ +#define PWR_CR_PLS_2V8 ((u16)0x00C0) /* PVD level 2.8V */ +#define PWR_CR_PLS_2V9 ((u16)0x00E0) /* PVD level 2.9V */ + +#define PWR_CR_DBP ((u16)0x0100) /* Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((u16)0x0001) /* Wakeup Flag */ +#define PWR_CSR_SBF ((u16)0x0002) /* Standby Flag */ +#define PWR_CSR_PVDO ((u16)0x0004) /* PVD Output */ +#define PWR_CSR_EWUP ((u16)0x0100) /* Enable WKUP pin */ + + + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR11 register *******************/ +#define BKP_DR11_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR12 register *******************/ +#define BKP_DR12_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR13 register *******************/ +#define BKP_DR13_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR14 register *******************/ +#define BKP_DR14_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR15 register *******************/ +#define BKP_DR15_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR16 register *******************/ +#define BKP_DR16_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR17 register *******************/ +#define BKP_DR17_D ((u16)0xFFFF) /* Backup data */ + + +/****************** Bit definition for BKP_DR18 register ********************/ +#define BKP_DR18_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR19 register *******************/ +#define BKP_DR19_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR20 register *******************/ +#define BKP_DR20_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR21 register *******************/ +#define BKP_DR21_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR22 register *******************/ +#define BKP_DR22_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR23 register *******************/ +#define BKP_DR23_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR24 register *******************/ +#define BKP_DR24_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR25 register *******************/ +#define BKP_DR25_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR26 register *******************/ +#define BKP_DR26_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR27 register *******************/ +#define BKP_DR27_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR28 register *******************/ +#define BKP_DR28_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR29 register *******************/ +#define BKP_DR29_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR30 register *******************/ +#define BKP_DR30_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR31 register *******************/ +#define BKP_DR31_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR32 register *******************/ +#define BKP_DR32_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR33 register *******************/ +#define BKP_DR33_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR34 register *******************/ +#define BKP_DR34_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR35 register *******************/ +#define BKP_DR35_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR36 register *******************/ +#define BKP_DR36_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR37 register *******************/ +#define BKP_DR37_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR38 register *******************/ +#define BKP_DR38_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR39 register *******************/ +#define BKP_DR39_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR40 register *******************/ +#define BKP_DR40_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR41 register *******************/ +#define BKP_DR41_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR42 register *******************/ +#define BKP_DR42_D ((u16)0xFFFF) /* Backup data */ + + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL ((u16)0x007F) /* Calibration value */ +#define BKP_RTCCR_CCO ((u16)0x0080) /* Calibration Clock Output */ +#define BKP_RTCCR_ASOE ((u16)0x0100) /* Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS ((u16)0x0200) /* Alarm or Second Output Selection */ + + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE ((u8)0x01) /* TAMPER pin enable */ +#define BKP_CR_TPAL ((u8)0x02) /* TAMPER pin active level */ + + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE ((u16)0x0001) /* Clear Tamper event */ +#define BKP_CSR_CTI ((u16)0x0002) /* Clear Tamper Interrupt */ +#define BKP_CSR_TPIE ((u16)0x0004) /* TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF ((u16)0x0100) /* Tamper Event Flag */ +#define BKP_CSR_TIF ((u16)0x0200) /* Tamper Interrupt Flag */ + + + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION ((u32)0x00000001) /* Internal High Speed clock enable */ +#define RCC_CR_HSIRDY ((u32)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM ((u32)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_CR_HSICAL ((u32)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_CR_HSEON ((u32)0x00010000) /* External High Speed clock enable */ +#define RCC_CR_HSERDY ((u32)0x00020000) /* External High Speed clock ready flag */ +#define RCC_CR_HSEBYP ((u32)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CR_CSSON ((u32)0x00080000) /* Clock Security System enable */ +#define RCC_CR_PLLON ((u32)0x01000000) /* PLL enable */ +#define RCC_CR_PLLRDY ((u32)0x02000000) /* PLL clock ready flag */ + + +/******************* Bit definition for RCC_CFGR register *******************/ +#define RCC_CFGR_SW ((u32)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 ((u32)0x00000001) /* Bit 0 */ +#define RCC_CFGR_SW_1 ((u32)0x00000002) /* Bit 1 */ + +/* SW configuration */ +#define RCC_CFGR_SW_HSI ((u32)0x00000000) /* HSI selected as system clock */ +#define RCC_CFGR_SW_HSE ((u32)0x00000001) /* HSE selected as system clock */ +#define RCC_CFGR_SW_PLL ((u32)0x00000002) /* PLL selected as system clock */ + +#define RCC_CFGR_SWS ((u32)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 ((u32)0x00000004) /* Bit 0 */ +#define RCC_CFGR_SWS_1 ((u32)0x00000008) /* Bit 1 */ + +/* SWS configuration */ +#define RCC_CFGR_SWS_HSI ((u32)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE ((u32)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL ((u32)0x00000008) /* PLL used as system clock */ + +#define RCC_CFGR_HPRE ((u32)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 ((u32)0x00000010) /* Bit 0 */ +#define RCC_CFGR_HPRE_1 ((u32)0x00000020) /* Bit 1 */ +#define RCC_CFGR_HPRE_2 ((u32)0x00000040) /* Bit 2 */ +#define RCC_CFGR_HPRE_3 ((u32)0x00000080) /* Bit 3 */ + +/* HPRE configuration */ +#define RCC_CFGR_HPRE_DIV1 ((u32)0x00000000) /* SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 ((u32)0x00000080) /* SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 ((u32)0x00000090) /* SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 ((u32)0x000000A0) /* SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 ((u32)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 ((u32)0x000000C0) /* SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 ((u32)0x000000D0) /* SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 ((u32)0x000000E0) /* SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 ((u32)0x000000F0) /* SYSCLK divided by 512 */ + +#define RCC_CFGR_PPRE1 ((u32)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 ((u32)0x00000100) /* Bit 0 */ +#define RCC_CFGR_PPRE1_1 ((u32)0x00000200) /* Bit 1 */ +#define RCC_CFGR_PPRE1_2 ((u32)0x00000400) /* Bit 2 */ + +/* PPRE1 configuration */ +#define RCC_CFGR_PPRE1_DIV1 ((u32)0x00000000) /* HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 ((u32)0x00000400) /* HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 ((u32)0x00000500) /* HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 ((u32)0x00000600) /* HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 ((u32)0x00000700) /* HCLK divided by 16 */ + +#define RCC_CFGR_PPRE2 ((u32)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 ((u32)0x00000800) /* Bit 0 */ +#define RCC_CFGR_PPRE2_1 ((u32)0x00001000) /* Bit 1 */ +#define RCC_CFGR_PPRE2_2 ((u32)0x00002000) /* Bit 2 */ + +/* PPRE2 configuration */ +#define RCC_CFGR_PPRE2_DIV1 ((u32)0x00000000) /* HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 ((u32)0x00002000) /* HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 ((u32)0x00002800) /* HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 ((u32)0x00003000) /* HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 ((u32)0x00003800) /* HCLK divided by 16 */ + +#define RCC_CFGR_ADCPRE ((u32)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_CFGR_ADCPRE_0 ((u32)0x00004000) /* Bit 0 */ +#define RCC_CFGR_ADCPRE_1 ((u32)0x00008000) /* Bit 1 */ + +/* ADCPPRE configuration */ +#define RCC_CFGR_ADCPRE_DIV2 ((u32)0x00000000) /* PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 ((u32)0x00004000) /* PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 ((u32)0x00008000) /* PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 ((u32)0x0000C000) /* PCLK2 divided by 8 */ + +#define RCC_CFGR_PLLSRC ((u32)0x00010000) /* PLL entry clock source */ +#define RCC_CFGR_PLLXTPRE ((u32)0x00020000) /* HSE divider for PLL entry */ + +#define RCC_CFGR_PLLMULL ((u32)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMULL_0 ((u32)0x00040000) /* Bit 0 */ +#define RCC_CFGR_PLLMULL_1 ((u32)0x00080000) /* Bit 1 */ +#define RCC_CFGR_PLLMULL_2 ((u32)0x00100000) /* Bit 2 */ +#define RCC_CFGR_PLLMULL_3 ((u32)0x00200000) /* Bit 3 */ + +/* PLLMUL configuration */ +#define RCC_CFGR_PLLMULL2 ((u32)0x00000000) /* PLL input clock*2 */ +#define RCC_CFGR_PLLMULL3 ((u32)0x00040000) /* PLL input clock*3 */ +#define RCC_CFGR_PLLMULL4 ((u32)0x00080000) /* PLL input clock*4 */ +#define RCC_CFGR_PLLMULL5 ((u32)0x000C0000) /* PLL input clock*5 */ +#define RCC_CFGR_PLLMULL6 ((u32)0x00100000) /* PLL input clock*6 */ +#define RCC_CFGR_PLLMULL7 ((u32)0x00140000) /* PLL input clock*7 */ +#define RCC_CFGR_PLLMULL8 ((u32)0x00180000) /* PLL input clock*8 */ +#define RCC_CFGR_PLLMULL9 ((u32)0x001C0000) /* PLL input clock*9 */ +#define RCC_CFGR_PLLMULL10 ((u32)0x00200000) /* PLL input clock10 */ +#define RCC_CFGR_PLLMULL11 ((u32)0x00240000) /* PLL input clock*11 */ +#define RCC_CFGR_PLLMULL12 ((u32)0x00280000) /* PLL input clock*12 */ +#define RCC_CFGR_PLLMULL13 ((u32)0x002C0000) /* PLL input clock*13 */ +#define RCC_CFGR_PLLMULL14 ((u32)0x00300000) /* PLL input clock*14 */ +#define RCC_CFGR_PLLMULL15 ((u32)0x00340000) /* PLL input clock*15 */ +#define RCC_CFGR_PLLMULL16 ((u32)0x00380000) /* PLL input clock*16 */ + +#define RCC_CFGR_USBPRE ((u32)0x00400000) /* USB prescaler */ + +#define RCC_CFGR_MCO ((u32)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_CFGR_MCO_0 ((u32)0x01000000) /* Bit 0 */ +#define RCC_CFGR_MCO_1 ((u32)0x02000000) /* Bit 1 */ +#define RCC_CFGR_MCO_2 ((u32)0x04000000) /* Bit 2 */ + +/* MCO configuration */ +#define RCC_CFGR_MCO_NOCLOCK ((u32)0x00000000) /* No clock */ +#define RCC_CFGR_MCO_SYSCLK ((u32)0x04000000) /* System clock selected */ +#define RCC_CFGR_MCO_HSI ((u32)0x05000000) /* Internal 8 MHz RC oscillator clock selected */ +#define RCC_CFGR_MCO_HSE ((u32)0x06000000) /* External 1-25 MHz oscillator clock selected */ +#define RCC_CFGR_MCO_PLL ((u32)0x07000000) /* PLL clock divided by 2 selected*/ + + +/******************* Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF ((u32)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF ((u32)0x00000002) /* LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF ((u32)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF ((u32)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF ((u32)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF ((u32)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE ((u32)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE ((u32)0x00000200) /* LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE ((u32)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE ((u32)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE ((u32)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC ((u32)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC ((u32)0x00020000) /* LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC ((u32)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC ((u32)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC ((u32)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC ((u32)0x00800000) /* Clock Security System Interrupt Clear */ + + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST ((u16)0x0001) /* Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST ((u16)0x0004) /* I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST ((u16)0x0008) /* IO port B reset */ +#define RCC_APB2RSTR_IOPCRST ((u16)0x0010) /* IO port C reset */ +#define RCC_APB2RSTR_IOPDRST ((u16)0x0020) /* IO port D reset */ +#define RCC_APB2RSTR_IOPERST ((u16)0x0040) /* IO port E reset */ +#define RCC_APB2RSTR_IOPFRST ((u16)0x0080) /* IO port F reset */ +#define RCC_APB2RSTR_IOPGRST ((u16)0x0100) /* IO port G reset */ +#define RCC_APB2RSTR_ADC1RST ((u16)0x0200) /* ADC 1 interface reset */ +#define RCC_APB2RSTR_ADC2RST ((u16)0x0400) /* ADC 2 interface reset */ +#define RCC_APB2RSTR_TIM1RST ((u16)0x0800) /* TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST ((u16)0x1000) /* SPI 1 reset */ +#define RCC_APB2RSTR_TIM8RST ((u16)0x2000) /* TIM8 Timer reset */ +#define RCC_APB2RSTR_USART1RST ((u16)0x4000) /* USART1 reset */ +#define RCC_APB2RSTR_ADC3RST ((u16)0x8000) /* ADC3 interface reset */ + + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST ((u32)0x00000001) /* Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST ((u32)0x00000002) /* Timer 3 reset */ +#define RCC_APB1RSTR_TIM4RST ((u32)0x00000004) /* Timer 4 reset */ +#define RCC_APB1RSTR_TIM5RST ((u32)0x00000008) /* Timer 5 reset */ +#define RCC_APB1RSTR_TIM6RST ((u32)0x00000010) /* Timer 6 reset */ +#define RCC_APB1RSTR_TIM7RST ((u32)0x00000020) /* Timer 7 reset */ +#define RCC_APB1RSTR_WWDGRST ((u32)0x00000800) /* Window Watchdog reset */ +#define RCC_APB1RSTR_SPI2RST ((u32)0x00004000) /* SPI 2 reset */ +#define RCC_APB1RSTR_SPI3RST ((u32)0x00008000) /* SPI 3 reset */ +#define RCC_APB1RSTR_USART2RST ((u32)0x00020000) /* USART 2 reset */ +#define RCC_APB1RSTR_USART3RST ((u32)0x00040000) /* RUSART 3 reset */ +#define RCC_APB1RSTR_UART4RST ((u32)0x00080000) /* USART 4 reset */ +#define RCC_APB1RSTR_UART5RST ((u32)0x00100000) /* USART 5 reset */ +#define RCC_APB1RSTR_I2C1RST ((u32)0x00200000) /* I2C 1 reset */ +#define RCC_APB1RSTR_I2C2RST ((u32)0x00400000) /* I2C 2 reset */ +#define RCC_APB1RSTR_USBRST ((u32)0x00800000) /* USB reset */ +#define RCC_APB1RSTR_CANRST ((u32)0x02000000) /* CAN reset */ +#define RCC_APB1RSTR_BKPRST ((u32)0x08000000) /* Backup interface reset */ +#define RCC_APB1RSTR_PWRRST ((u32)0x10000000) /* Power interface reset */ +#define RCC_APB1RSTR_DACRST ((u32)0x20000000) /* DAC interface reset */ + + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMA1EN ((u16)0x0001) /* DMA1 clock enable */ +#define RCC_AHBENR_DMA2EN ((u16)0x0002) /* DMA2 clock enable */ +#define RCC_AHBENR_SRAMEN ((u16)0x0004) /* SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN ((u16)0x0010) /* FLITF clock enable */ +#define RCC_AHBENR_CRCEN ((u16)0x0040) /* CRC clock enable */ +#define RCC_AHBENR_FSMCEN ((u16)0x0100) /* FSMC clock enable */ +#define RCC_AHBENR_SDIOEN ((u16)0x0400) /* SDIO clock enable */ + + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN ((u16)0x0001) /* Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN ((u16)0x0004) /* I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN ((u16)0x0008) /* I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN ((u16)0x0010) /* I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN ((u16)0x0020) /* I/O port D clock enable */ +#define RCC_APB2ENR_IOPEEN ((u16)0x0040) /* I/O port E clock enable */ +#define RCC_APB2ENR_IOPFEN ((u16)0x0080) /* I/O port F clock enable */ +#define RCC_APB2ENR_IOPGEN ((u16)0x0100) /* I/O port G clock enable */ +#define RCC_APB2ENR_ADC1EN ((u16)0x0200) /* ADC 1 interface clock enable */ +#define RCC_APB2ENR_ADC2EN ((u16)0x0400) /* ADC 2 interface clock enable */ +#define RCC_APB2ENR_TIM1EN ((u16)0x0800) /* TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN ((u16)0x1000) /* SPI 1 clock enable */ +#define RCC_APB2ENR_TIM8EN ((u16)0x2000) /* TIM8 Timer clock enable */ +#define RCC_APB2ENR_USART1EN ((u16)0x4000) /* USART1 clock enable */ +#define RCC_APB2ENR_ADC3EN ((u16)0x8000) /* DMA1 clock enable */ + + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN ((u32)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN ((u32)0x00000002) /* Timer 3 clock enable */ +#define RCC_APB1ENR_TIM4EN ((u32)0x00000004) /* Timer 4 clock enable */ +#define RCC_APB1ENR_TIM5EN ((u32)0x00000008) /* Timer 5 clock enable */ +#define RCC_APB1ENR_TIM6EN ((u32)0x00000010) /* Timer 6 clock enable */ +#define RCC_APB1ENR_TIM7EN ((u32)0x00000020) /* Timer 7 clock enable */ +#define RCC_APB1ENR_WWDGEN ((u32)0x00000800) /* Window Watchdog clock enable */ +#define RCC_APB1ENR_SPI2EN ((u32)0x00004000) /* SPI 2 clock enable */ +#define RCC_APB1ENR_SPI3EN ((u32)0x00008000) /* SPI 3 clock enable */ +#define RCC_APB1ENR_USART2EN ((u32)0x00020000) /* USART 2 clock enable */ +#define RCC_APB1ENR_USART3EN ((u32)0x00040000) /* USART 3 clock enable */ +#define RCC_APB1ENR_UART4EN ((u32)0x00080000) /* USART 4 clock enable */ +#define RCC_APB1ENR_UART5EN ((u32)0x00100000) /* USART 5 clock enable */ +#define RCC_APB1ENR_I2C1EN ((u32)0x00200000) /* I2C 1 clock enable */ +#define RCC_APB1ENR_I2C2EN ((u32)0x00400000) /* I2C 2 clock enable */ +#define RCC_APB1ENR_USBEN ((u32)0x00800000) /* USB clock enable */ +#define RCC_APB1ENR_CANEN ((u32)0x02000000) /* CAN clock enable */ +#define RCC_APB1ENR_BKPEN ((u32)0x08000000) /* Backup interface clock enable */ +#define RCC_APB1ENR_PWREN ((u32)0x10000000) /* Power interface clock enable */ +#define RCC_APB1ENR_DACEN ((u32)0x20000000) /* DAC interface clock enable */ + + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON ((u32)0x00000001) /* External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY ((u32)0x00000002) /* External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP ((u32)0x00000004) /* External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL ((u32)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 ((u32)0x00000100) /* Bit 0 */ +#define RCC_BDCR_RTCSEL_1 ((u32)0x00000200) /* Bit 1 */ +/* RTC congiguration */ +#define RCC_BDCR_RTCSEL_NOCLOCK ((u32)0x00000000) /* No clock */ +#define RCC_BDCR_RTCSEL_LSE ((u32)0x00000100) /* LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI ((u32)0x00000200) /* LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE ((u32)0x00000300) /* HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN ((u32)0x00008000) /* RTC clock enable */ +#define RCC_BDCR_BDRST ((u32)0x00010000) /* Backup domain software reset */ + + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION ((u32)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY ((u32)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF ((u32)0x01000000) /* Remove reset flag */ +#define RCC_CSR_PINRSTF ((u32)0x04000000) /* PIN reset flag */ +#define RCC_CSR_PORRSTF ((u32)0x08000000) /* POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF ((u32)0x10000000) /* Software Reset flag */ +#define RCC_CSR_IWDGRSTF ((u32)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF ((u32)0x40000000) /* Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF ((u32)0x80000000) /* Low-Power reset flag */ + + + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function IO */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE ((u32)0x33333333) /* Port x mode bits */ + +#define GPIO_CRL_MODE0 ((u32)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 ((u32)0x00000001) /* Bit 0 */ +#define GPIO_CRL_MODE0_1 ((u32)0x00000002) /* Bit 1 */ + +#define GPIO_CRL_MODE1 ((u32)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 ((u32)0x00000010) /* Bit 0 */ +#define GPIO_CRL_MODE1_1 ((u32)0x00000020) /* Bit 1 */ + +#define GPIO_CRL_MODE2 ((u32)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 ((u32)0x00000100) /* Bit 0 */ +#define GPIO_CRL_MODE2_1 ((u32)0x00000200) /* Bit 1 */ + +#define GPIO_CRL_MODE3 ((u32)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 ((u32)0x00001000) /* Bit 0 */ +#define GPIO_CRL_MODE3_1 ((u32)0x00002000) /* Bit 1 */ + +#define GPIO_CRL_MODE4 ((u32)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 ((u32)0x00010000) /* Bit 0 */ +#define GPIO_CRL_MODE4_1 ((u32)0x00020000) /* Bit 1 */ + +#define GPIO_CRL_MODE5 ((u32)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 ((u32)0x00100000) /* Bit 0 */ +#define GPIO_CRL_MODE5_1 ((u32)0x00200000) /* Bit 1 */ + +#define GPIO_CRL_MODE6 ((u32)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 ((u32)0x01000000) /* Bit 0 */ +#define GPIO_CRL_MODE6_1 ((u32)0x02000000) /* Bit 1 */ + +#define GPIO_CRL_MODE7 ((u32)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 ((u32)0x10000000) /* Bit 0 */ +#define GPIO_CRL_MODE7_1 ((u32)0x20000000) /* Bit 1 */ + + +#define GPIO_CRL_CNF ((u32)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CRL_CNF0 ((u32)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 ((u32)0x00000004) /* Bit 0 */ +#define GPIO_CRL_CNF0_1 ((u32)0x00000008) /* Bit 1 */ + +#define GPIO_CRL_CNF1 ((u32)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 ((u32)0x00000040) /* Bit 0 */ +#define GPIO_CRL_CNF1_1 ((u32)0x00000080) /* Bit 1 */ + +#define GPIO_CRL_CNF2 ((u32)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 ((u32)0x00000400) /* Bit 0 */ +#define GPIO_CRL_CNF2_1 ((u32)0x00000800) /* Bit 1 */ + +#define GPIO_CRL_CNF3 ((u32)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 ((u32)0x00004000) /* Bit 0 */ +#define GPIO_CRL_CNF3_1 ((u32)0x00008000) /* Bit 1 */ + +#define GPIO_CRL_CNF4 ((u32)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 ((u32)0x00040000) /* Bit 0 */ +#define GPIO_CRL_CNF4_1 ((u32)0x00080000) /* Bit 1 */ + +#define GPIO_CRL_CNF5 ((u32)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 ((u32)0x00400000) /* Bit 0 */ +#define GPIO_CRL_CNF5_1 ((u32)0x00800000) /* Bit 1 */ + +#define GPIO_CRL_CNF6 ((u32)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 ((u32)0x04000000) /* Bit 0 */ +#define GPIO_CRL_CNF6_1 ((u32)0x08000000) /* Bit 1 */ + +#define GPIO_CRL_CNF7 ((u32)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 ((u32)0x40000000) /* Bit 0 */ +#define GPIO_CRL_CNF7_1 ((u32)0x80000000) /* Bit 1 */ + + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE ((u32)0x33333333) /* Port x mode bits */ + +#define GPIO_CRH_MODE8 ((u32)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 ((u32)0x00000001) /* Bit 0 */ +#define GPIO_CRH_MODE8_1 ((u32)0x00000002) /* Bit 1 */ + +#define GPIO_CRH_MODE9 ((u32)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 ((u32)0x00000010) /* Bit 0 */ +#define GPIO_CRH_MODE9_1 ((u32)0x00000020) /* Bit 1 */ + +#define GPIO_CRH_MODE10 ((u32)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 ((u32)0x00000100) /* Bit 0 */ +#define GPIO_CRH_MODE10_1 ((u32)0x00000200) /* Bit 1 */ + +#define GPIO_CRH_MODE11 ((u32)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 ((u32)0x00001000) /* Bit 0 */ +#define GPIO_CRH_MODE11_1 ((u32)0x00002000) /* Bit 1 */ + +#define GPIO_CRH_MODE12 ((u32)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 ((u32)0x00010000) /* Bit 0 */ +#define GPIO_CRH_MODE12_1 ((u32)0x00020000) /* Bit 1 */ + +#define GPIO_CRH_MODE13 ((u32)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 ((u32)0x00100000) /* Bit 0 */ +#define GPIO_CRH_MODE13_1 ((u32)0x00200000) /* Bit 1 */ + +#define GPIO_CRH_MODE14 ((u32)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 ((u32)0x01000000) /* Bit 0 */ +#define GPIO_CRH_MODE14_1 ((u32)0x02000000) /* Bit 1 */ + +#define GPIO_CRH_MODE15 ((u32)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 ((u32)0x10000000) /* Bit 0 */ +#define GPIO_CRH_MODE15_1 ((u32)0x20000000) /* Bit 1 */ + + +#define GPIO_CRH_CNF ((u32)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CRH_CNF8 ((u32)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 ((u32)0x00000004) /* Bit 0 */ +#define GPIO_CRH_CNF8_1 ((u32)0x00000008) /* Bit 1 */ + +#define GPIO_CRH_CNF9 ((u32)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 ((u32)0x00000040) /* Bit 0 */ +#define GPIO_CRH_CNF9_1 ((u32)0x00000080) /* Bit 1 */ + +#define GPIO_CRH_CNF10 ((u32)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 ((u32)0x00000400) /* Bit 0 */ +#define GPIO_CRH_CNF10_1 ((u32)0x00000800) /* Bit 1 */ + +#define GPIO_CRH_CNF11 ((u32)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 ((u32)0x00004000) /* Bit 0 */ +#define GPIO_CRH_CNF11_1 ((u32)0x00008000) /* Bit 1 */ + +#define GPIO_CRH_CNF12 ((u32)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 ((u32)0x00040000) /* Bit 0 */ +#define GPIO_CRH_CNF12_1 ((u32)0x00080000) /* Bit 1 */ + +#define GPIO_CRH_CNF13 ((u32)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 ((u32)0x00400000) /* Bit 0 */ +#define GPIO_CRH_CNF13_1 ((u32)0x00800000) /* Bit 1 */ + +#define GPIO_CRH_CNF14 ((u32)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 ((u32)0x04000000) /* Bit 0 */ +#define GPIO_CRH_CNF14_1 ((u32)0x08000000) /* Bit 1 */ + +#define GPIO_CRH_CNF15 ((u32)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 ((u32)0x40000000) /* Bit 0 */ +#define GPIO_CRH_CNF15_1 ((u32)0x80000000) /* Bit 1 */ + + +/******************* Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0 ((u16)0x0001) /* Port input data, bit 0 */ +#define GPIO_IDR_IDR1 ((u16)0x0002) /* Port input data, bit 1 */ +#define GPIO_IDR_IDR2 ((u16)0x0004) /* Port input data, bit 2 */ +#define GPIO_IDR_IDR3 ((u16)0x0008) /* Port input data, bit 3 */ +#define GPIO_IDR_IDR4 ((u16)0x0010) /* Port input data, bit 4 */ +#define GPIO_IDR_IDR5 ((u16)0x0020) /* Port input data, bit 5 */ +#define GPIO_IDR_IDR6 ((u16)0x0040) /* Port input data, bit 6 */ +#define GPIO_IDR_IDR7 ((u16)0x0080) /* Port input data, bit 7 */ +#define GPIO_IDR_IDR8 ((u16)0x0100) /* Port input data, bit 8 */ +#define GPIO_IDR_IDR9 ((u16)0x0200) /* Port input data, bit 9 */ +#define GPIO_IDR_IDR10 ((u16)0x0400) /* Port input data, bit 10 */ +#define GPIO_IDR_IDR11 ((u16)0x0800) /* Port input data, bit 11 */ +#define GPIO_IDR_IDR12 ((u16)0x1000) /* Port input data, bit 12 */ +#define GPIO_IDR_IDR13 ((u16)0x2000) /* Port input data, bit 13 */ +#define GPIO_IDR_IDR14 ((u16)0x4000) /* Port input data, bit 14 */ +#define GPIO_IDR_IDR15 ((u16)0x8000) /* Port input data, bit 15 */ + + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0 ((u16)0x0001) /* Port output data, bit 0 */ +#define GPIO_ODR_ODR1 ((u16)0x0002) /* Port output data, bit 1 */ +#define GPIO_ODR_ODR2 ((u16)0x0004) /* Port output data, bit 2 */ +#define GPIO_ODR_ODR3 ((u16)0x0008) /* Port output data, bit 3 */ +#define GPIO_ODR_ODR4 ((u16)0x0010) /* Port output data, bit 4 */ +#define GPIO_ODR_ODR5 ((u16)0x0020) /* Port output data, bit 5 */ +#define GPIO_ODR_ODR6 ((u16)0x0040) /* Port output data, bit 6 */ +#define GPIO_ODR_ODR7 ((u16)0x0080) /* Port output data, bit 7 */ +#define GPIO_ODR_ODR8 ((u16)0x0100) /* Port output data, bit 8 */ +#define GPIO_ODR_ODR9 ((u16)0x0200) /* Port output data, bit 9 */ +#define GPIO_ODR_ODR10 ((u16)0x0400) /* Port output data, bit 10 */ +#define GPIO_ODR_ODR11 ((u16)0x0800) /* Port output data, bit 11 */ +#define GPIO_ODR_ODR12 ((u16)0x1000) /* Port output data, bit 12 */ +#define GPIO_ODR_ODR13 ((u16)0x2000) /* Port output data, bit 13 */ +#define GPIO_ODR_ODR14 ((u16)0x4000) /* Port output data, bit 14 */ +#define GPIO_ODR_ODR15 ((u16)0x8000) /* Port output data, bit 15 */ + + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0 ((u32)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSRR_BS1 ((u32)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSRR_BS2 ((u32)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSRR_BS3 ((u32)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSRR_BS4 ((u32)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSRR_BS5 ((u32)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSRR_BS6 ((u32)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSRR_BS7 ((u32)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSRR_BS8 ((u32)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSRR_BS9 ((u32)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSRR_BS10 ((u32)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSRR_BS11 ((u32)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSRR_BS12 ((u32)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSRR_BS13 ((u32)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSRR_BS14 ((u32)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSRR_BS15 ((u32)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSRR_BR0 ((u32)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSRR_BR1 ((u32)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSRR_BR2 ((u32)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSRR_BR3 ((u32)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSRR_BR4 ((u32)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSRR_BR5 ((u32)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSRR_BR6 ((u32)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSRR_BR7 ((u32)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSRR_BR8 ((u32)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSRR_BR9 ((u32)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSRR_BR10 ((u32)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSRR_BR11 ((u32)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSRR_BR12 ((u32)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSRR_BR13 ((u32)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSRR_BR14 ((u32)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSRR_BR15 ((u32)0x80000000) /* Port x Reset bit 15 */ + + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0 ((u16)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BRR_BR1 ((u16)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BRR_BR2 ((u16)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BRR_BR3 ((u16)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BRR_BR4 ((u16)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BRR_BR5 ((u16)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BRR_BR6 ((u16)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BRR_BR7 ((u16)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BRR_BR8 ((u16)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BRR_BR9 ((u16)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BRR_BR10 ((u16)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BRR_BR11 ((u16)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BRR_BR12 ((u16)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BRR_BR13 ((u16)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BRR_BR14 ((u16)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BRR_BR15 ((u16)0x8000) /* Port x Reset bit 15 */ + + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0 ((u32)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1 ((u32)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2 ((u32)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3 ((u32)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4 ((u32)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5 ((u32)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6 ((u32)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7 ((u32)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8 ((u32)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9 ((u32)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10 ((u32)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11 ((u32)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12 ((u32)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13 ((u32)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14 ((u32)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15 ((u32)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK ((u32)0x00010000) /* Lock key */ + + +/*----------------------------------------------------------------------------*/ + + +/****************** Bit definition for AFIO_EVCR register *******************/ +#define AFIO_EVCR_PIN ((u8)0x0F) /* PIN[3:0] bits (Pin selection) */ +#define AFIO_EVCR_PIN_0 ((u8)0x01) /* Bit 0 */ +#define AFIO_EVCR_PIN_1 ((u8)0x02) /* Bit 1 */ +#define AFIO_EVCR_PIN_2 ((u8)0x04) /* Bit 2 */ +#define AFIO_EVCR_PIN_3 ((u8)0x08) /* Bit 3 */ + +/* PIN configuration */ +#define AFIO_EVCR_PIN_PX0 ((u8)0x00) /* Pin 0 selected */ +#define AFIO_EVCR_PIN_PX1 ((u8)0x01) /* Pin 1 selected */ +#define AFIO_EVCR_PIN_PX2 ((u8)0x02) /* Pin 2 selected */ +#define AFIO_EVCR_PIN_PX3 ((u8)0x03) /* Pin 3 selected */ +#define AFIO_EVCR_PIN_PX4 ((u8)0x04) /* Pin 4 selected */ +#define AFIO_EVCR_PIN_PX5 ((u8)0x05) /* Pin 5 selected */ +#define AFIO_EVCR_PIN_PX6 ((u8)0x06) /* Pin 6 selected */ +#define AFIO_EVCR_PIN_PX7 ((u8)0x07) /* Pin 7 selected */ +#define AFIO_EVCR_PIN_PX8 ((u8)0x08) /* Pin 8 selected */ +#define AFIO_EVCR_PIN_PX9 ((u8)0x09) /* Pin 9 selected */ +#define AFIO_EVCR_PIN_PX10 ((u8)0x0A) /* Pin 10 selected */ +#define AFIO_EVCR_PIN_PX11 ((u8)0x0B) /* Pin 11 selected */ +#define AFIO_EVCR_PIN_PX12 ((u8)0x0C) /* Pin 12 selected */ +#define AFIO_EVCR_PIN_PX13 ((u8)0x0D) /* Pin 13 selected */ +#define AFIO_EVCR_PIN_PX14 ((u8)0x0E) /* Pin 14 selected */ +#define AFIO_EVCR_PIN_PX15 ((u8)0x0F) /* Pin 15 selected */ + +#define AFIO_EVCR_PORT ((u8)0x70) /* PORT[2:0] bits (Port selection) */ +#define AFIO_EVCR_PORT_0 ((u8)0x10) /* Bit 0 */ +#define AFIO_EVCR_PORT_1 ((u8)0x20) /* Bit 1 */ +#define AFIO_EVCR_PORT_2 ((u8)0x40) /* Bit 2 */ + +/* PORT configuration */ +#define AFIO_EVCR_PORT_PA ((u8)0x00) /* Port A selected */ +#define AFIO_EVCR_PORT_PB ((u8)0x10) /* Port B selected */ +#define AFIO_EVCR_PORT_PC ((u8)0x20) /* Port C selected */ +#define AFIO_EVCR_PORT_PD ((u8)0x30) /* Port D selected */ +#define AFIO_EVCR_PORT_PE ((u8)0x40) /* Port E selected */ + +#define AFIO_EVCR_EVOE ((u8)0x80) /* Event Output Enable */ + + +/****************** Bit definition for AFIO_MAPR register *******************/ +#define AFIO_MAPR_SPI1 _REMAP ((u32)0x00000001) /* SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP ((u32)0x00000002) /* I2C1 remapping */ +#define AFIO_MAPR_USART1_REMAP ((u32)0x00000004) /* USART1 remapping */ +#define AFIO_MAPR_USART2_REMAP ((u32)0x00000008) /* USART2 remapping */ + +#define AFIO_MAPR_USART3_REMAP ((u32)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_MAPR_USART3_REMAP_0 ((u32)0x00000010) /* Bit 0 */ +#define AFIO_MAPR_USART3_REMAP_1 ((u32)0x00000020) /* Bit 1 */ + +/* USART3_REMAP configuration */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP ((u32)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((u32)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((u32)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_MAPR_TIM1_REMAP ((u32)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_MAPR_TIM1_REMAP_0 ((u32)0x00000040) /* Bit 0 */ +#define AFIO_MAPR_TIM1_REMAP_1 ((u32)0x00000080) /* Bit 1 */ + +/* TIM1_REMAP configuration */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((u32)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((u32)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((u32)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_MAPR_TIM2_REMAP ((u32)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_MAPR_TIM2_REMAP_0 ((u32)0x00000100) /* Bit 0 */ +#define AFIO_MAPR_TIM2_REMAP_1 ((u32)0x00000200) /* Bit 1 */ + +/* TIM2_REMAP configuration */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((u32)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((u32)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((u32)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((u32)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_MAPR_TIM3_REMAP ((u32)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_MAPR_TIM3_REMAP_0 ((u32)0x00000400) /* Bit 0 */ +#define AFIO_MAPR_TIM3_REMAP_1 ((u32)0x00000800) /* Bit 1 */ + +/* TIM3_REMAP configuration */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((u32)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((u32)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((u32)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_MAPR_TIM4_REMAP ((u32)0x00001000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ + +#define AFIO_MAPR_CAN_REMAP ((u32)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_MAPR_CAN_REMAP_0 ((u32)0x00002000) /* Bit 0 */ +#define AFIO_MAPR_CAN_REMAP_1 ((u32)0x00004000) /* Bit 1 */ + +/* CAN_REMAP configuration */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 ((u32)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2 ((u32)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3 ((u32)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_MAPR_PD01_REMAP ((u32)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_MAPR_TIM5CH4_IREMAP ((u32)0x00010000) /* TIM5 Channel4 Internal Remap */ +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((u32)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((u32)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((u32)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((u32)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */ + +#define AFIO_MAPR_SWJ_CFG ((u32)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_MAPR_SWJ_CFG_0 ((u32)0x01000000) /* Bit 0 */ +#define AFIO_MAPR_SWJ_CFG_1 ((u32)0x02000000) /* Bit 1 */ +#define AFIO_MAPR_SWJ_CFG_2 ((u32)0x04000000) /* Bit 2 */ + +/* SWJ_CFG configuration */ +#define AFIO_MAPR_SWJ_CFG_RESET ((u32)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((u32)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((u32)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_MAPR_SWJ_CFG_DISABLE ((u32)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ + + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((u16)0x000F) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((u16)0x00F0) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((u16)0x0F00) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((u16)0xF000) /* EXTI 3 configuration */ + +/* EXTI0 configuration */ +#define AFIO_EXTICR1_EXTI0_PA ((u16)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((u16)0x0001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((u16)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((u16)0x0003) /* PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((u16)0x0004) /* PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((u16)0x0005) /* PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((u16)0x0006) /* PG[0] pin */ + +/* EXTI1 configuration */ +#define AFIO_EXTICR1_EXTI1_PA ((u16)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((u16)0x0010) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((u16)0x0020) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((u16)0x0030) /* PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((u16)0x0040) /* PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((u16)0x0050) /* PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((u16)0x0060) /* PG[1] pin */ + +/* EXTI2 configuration */ +#define AFIO_EXTICR1_EXTI2_PA ((u16)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((u16)0x0100) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((u16)0x0200) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((u16)0x0300) /* PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((u16)0x0400) /* PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((u16)0x0500) /* PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((u16)0x0600) /* PG[2] pin */ + +/* EXTI3 configuration */ +#define AFIO_EXTICR1_EXTI3_PA ((u16)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((u16)0x1000) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((u16)0x2000) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((u16)0x3000) /* PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((u16)0x4000) /* PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((u16)0x5000) /* PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((u16)0x6000) /* PG[3] pin */ + + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((u16)0x000F) /* EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((u16)0x00F0) /* EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((u16)0x0F00) /* EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((u16)0xF000) /* EXTI 7 configuration */ + +/* EXTI4 configuration */ +#define AFIO_EXTICR2_EXTI4_PA ((u16)0x0000) /* PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((u16)0x0001) /* PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((u16)0x0002) /* PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((u16)0x0003) /* PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((u16)0x0004) /* PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((u16)0x0005) /* PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((u16)0x0006) /* PG[4] pin */ + +/* EXTI5 configuration */ +#define AFIO_EXTICR2_EXTI5_PA ((u16)0x0000) /* PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((u16)0x0010) /* PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((u16)0x0020) /* PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((u16)0x0030) /* PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((u16)0x0040) /* PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((u16)0x0050) /* PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((u16)0x0060) /* PG[5] pin */ + +/* EXTI6 configuration */ +#define AFIO_EXTICR2_EXTI6_PA ((u16)0x0000) /* PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((u16)0x0100) /* PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((u16)0x0200) /* PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((u16)0x0300) /* PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((u16)0x0400) /* PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((u16)0x0500) /* PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((u16)0x0600) /* PG[6] pin */ + +/* EXTI7 configuration */ +#define AFIO_EXTICR2_EXTI7_PA ((u16)0x0000) /* PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((u16)0x1000) /* PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((u16)0x2000) /* PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((u16)0x3000) /* PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((u16)0x4000) /* PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((u16)0x5000) /* PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((u16)0x6000) /* PG[7] pin */ + + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((u16)0x000F) /* EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((u16)0x00F0) /* EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((u16)0x0F00) /* EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((u16)0xF000) /* EXTI 11 configuration */ + +/* EXTI8 configuration */ +#define AFIO_EXTICR3_EXTI8_PA ((u16)0x0000) /* PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((u16)0x0001) /* PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((u16)0x0002) /* PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((u16)0x0003) /* PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((u16)0x0004) /* PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((u16)0x0005) /* PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((u16)0x0006) /* PG[8] pin */ + +/* EXTI9 configuration */ +#define AFIO_EXTICR3_EXTI9_PA ((u16)0x0000) /* PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((u16)0x0010) /* PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((u16)0x0020) /* PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((u16)0x0030) /* PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((u16)0x0040) /* PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((u16)0x0050) /* PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((u16)0x0060) /* PG[9] pin */ + +/* EXTI10 configuration */ +#define AFIO_EXTICR3_EXTI10_PA ((u16)0x0000) /* PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((u16)0x0100) /* PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((u16)0x0200) /* PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((u16)0x0300) /* PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((u16)0x0400) /* PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((u16)0x0500) /* PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((u16)0x0600) /* PG[10] pin */ + +/* EXTI11 configuration */ +#define AFIO_EXTICR3_EXTI11_PA ((u16)0x0000) /* PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((u16)0x1000) /* PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((u16)0x2000) /* PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((u16)0x3000) /* PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((u16)0x4000) /* PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((u16)0x5000) /* PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((u16)0x6000) /* PG[11] pin */ + + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((u16)0x000F) /* EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((u16)0x00F0) /* EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((u16)0x0F00) /* EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((u16)0xF000) /* EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTICR4_EXTI12_PA ((u16)0x0000) /* PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((u16)0x0001) /* PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((u16)0x0002) /* PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((u16)0x0003) /* PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((u16)0x0004) /* PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((u16)0x0005) /* PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((u16)0x0006) /* PG[12] pin */ + +/* EXTI13 configuration */ +#define AFIO_EXTICR4_EXTI13_PA ((u16)0x0000) /* PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((u16)0x0010) /* PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((u16)0x0020) /* PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((u16)0x0030) /* PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((u16)0x0040) /* PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((u16)0x0050) /* PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((u16)0x0060) /* PG[13] pin */ + +/* EXTI14 configuration */ +#define AFIO_EXTICR4_EXTI14_PA ((u16)0x0000) /* PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((u16)0x0100) /* PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((u16)0x0200) /* PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((u16)0x0300) /* PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((u16)0x0400) /* PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((u16)0x0500) /* PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((u16)0x0600) /* PG[14] pin */ + +/* EXTI15 configuration */ +#define AFIO_EXTICR4_EXTI15_PA ((u16)0x0000) /* PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((u16)0x1000) /* PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((u16)0x2000) /* PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((u16)0x3000) /* PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((u16)0x4000) /* PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((u16)0x5000) /* PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((u16)0x6000) /* PG[15] pin */ + + + +/******************************************************************************/ +/* */ +/* SystemTick */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SysTick_CTRL register *****************/ +#define SysTick_CTRL_ENABLE ((u32)0x00000001) /* Counter enable */ +#define SysTick_CTRL_TICKINT ((u32)0x00000002) /* Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((u32)0x00000004) /* Clock source */ +#define SysTick_CTRL_COUNTFLAG ((u32)0x00010000) /* Count Flag */ + + +/***************** Bit definition for SysTick_LOAD register *****************/ +#define SysTick_LOAD_RELOAD ((u32)0x00FFFFFF) /* Value to load into the SysTick Current Value Register when the counter reaches 0 */ + + +/***************** Bit definition for SysTick_VAL register ******************/ +#define SysTick_VAL_CURRENT ((u32)0x00FFFFFF) /* Current value at the time the register is accessed */ + + +/***************** Bit definition for SysTick_CALIB register ****************/ +#define SysTick_CALIB_TENMS ((u32)0x00FFFFFF) /* Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((u32)0x40000000) /* Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((u32)0x80000000) /* The reference clock is not provided */ + + + +/******************************************************************************/ +/* */ +/* Nested Vectored Interrupt Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for NVIC_ISER register *******************/ +#define NVIC_ISER_SETENA ((u32)0xFFFFFFFF) /* Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((u32)0x00000001) /* bit 0 */ +#define NVIC_ISER_SETENA_1 ((u32)0x00000002) /* bit 1 */ +#define NVIC_ISER_SETENA_2 ((u32)0x00000004) /* bit 2 */ +#define NVIC_ISER_SETENA_3 ((u32)0x00000008) /* bit 3 */ +#define NVIC_ISER_SETENA_4 ((u32)0x00000010) /* bit 4 */ +#define NVIC_ISER_SETENA_5 ((u32)0x00000020) /* bit 5 */ +#define NVIC_ISER_SETENA_6 ((u32)0x00000040) /* bit 6 */ +#define NVIC_ISER_SETENA_7 ((u32)0x00000080) /* bit 7 */ +#define NVIC_ISER_SETENA_8 ((u32)0x00000100) /* bit 8 */ +#define NVIC_ISER_SETENA_9 ((u32)0x00000200) /* bit 9 */ +#define NVIC_ISER_SETENA_10 ((u32)0x00000400) /* bit 10 */ +#define NVIC_ISER_SETENA_11 ((u32)0x00000800) /* bit 11 */ +#define NVIC_ISER_SETENA_12 ((u32)0x00001000) /* bit 12 */ +#define NVIC_ISER_SETENA_13 ((u32)0x00002000) /* bit 13 */ +#define NVIC_ISER_SETENA_14 ((u32)0x00004000) /* bit 14 */ +#define NVIC_ISER_SETENA_15 ((u32)0x00008000) /* bit 15 */ +#define NVIC_ISER_SETENA_16 ((u32)0x00010000) /* bit 16 */ +#define NVIC_ISER_SETENA_17 ((u32)0x00020000) /* bit 17 */ +#define NVIC_ISER_SETENA_18 ((u32)0x00040000) /* bit 18 */ +#define NVIC_ISER_SETENA_19 ((u32)0x00080000) /* bit 19 */ +#define NVIC_ISER_SETENA_20 ((u32)0x00100000) /* bit 20 */ +#define NVIC_ISER_SETENA_21 ((u32)0x00200000) /* bit 21 */ +#define NVIC_ISER_SETENA_22 ((u32)0x00400000) /* bit 22 */ +#define NVIC_ISER_SETENA_23 ((u32)0x00800000) /* bit 23 */ +#define NVIC_ISER_SETENA_24 ((u32)0x01000000) /* bit 24 */ +#define NVIC_ISER_SETENA_25 ((u32)0x02000000) /* bit 25 */ +#define NVIC_ISER_SETENA_26 ((u32)0x04000000) /* bit 26 */ +#define NVIC_ISER_SETENA_27 ((u32)0x08000000) /* bit 27 */ +#define NVIC_ISER_SETENA_28 ((u32)0x10000000) /* bit 28 */ +#define NVIC_ISER_SETENA_29 ((u32)0x20000000) /* bit 29 */ +#define NVIC_ISER_SETENA_30 ((u32)0x40000000) /* bit 30 */ +#define NVIC_ISER_SETENA_31 ((u32)0x80000000) /* bit 31 */ + + + +/****************** Bit definition for NVIC_ICER register *******************/ +#define NVIC_ICER_CLRENA ((u32)0xFFFFFFFF) /* Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((u32)0x00000001) /* bit 0 */ +#define NVIC_ICER_CLRENA_1 ((u32)0x00000002) /* bit 1 */ +#define NVIC_ICER_CLRENA_2 ((u32)0x00000004) /* bit 2 */ +#define NVIC_ICER_CLRENA_3 ((u32)0x00000008) /* bit 3 */ +#define NVIC_ICER_CLRENA_4 ((u32)0x00000010) /* bit 4 */ +#define NVIC_ICER_CLRENA_5 ((u32)0x00000020) /* bit 5 */ +#define NVIC_ICER_CLRENA_6 ((u32)0x00000040) /* bit 6 */ +#define NVIC_ICER_CLRENA_7 ((u32)0x00000080) /* bit 7 */ +#define NVIC_ICER_CLRENA_8 ((u32)0x00000100) /* bit 8 */ +#define NVIC_ICER_CLRENA_9 ((u32)0x00000200) /* bit 9 */ +#define NVIC_ICER_CLRENA_10 ((u32)0x00000400) /* bit 10 */ +#define NVIC_ICER_CLRENA_11 ((u32)0x00000800) /* bit 11 */ +#define NVIC_ICER_CLRENA_12 ((u32)0x00001000) /* bit 12 */ +#define NVIC_ICER_CLRENA_13 ((u32)0x00002000) /* bit 13 */ +#define NVIC_ICER_CLRENA_14 ((u32)0x00004000) /* bit 14 */ +#define NVIC_ICER_CLRENA_15 ((u32)0x00008000) /* bit 15 */ +#define NVIC_ICER_CLRENA_16 ((u32)0x00010000) /* bit 16 */ +#define NVIC_ICER_CLRENA_17 ((u32)0x00020000) /* bit 17 */ +#define NVIC_ICER_CLRENA_18 ((u32)0x00040000) /* bit 18 */ +#define NVIC_ICER_CLRENA_19 ((u32)0x00080000) /* bit 19 */ +#define NVIC_ICER_CLRENA_20 ((u32)0x00100000) /* bit 20 */ +#define NVIC_ICER_CLRENA_21 ((u32)0x00200000) /* bit 21 */ +#define NVIC_ICER_CLRENA_22 ((u32)0x00400000) /* bit 22 */ +#define NVIC_ICER_CLRENA_23 ((u32)0x00800000) /* bit 23 */ +#define NVIC_ICER_CLRENA_24 ((u32)0x01000000) /* bit 24 */ +#define NVIC_ICER_CLRENA_25 ((u32)0x02000000) /* bit 25 */ +#define NVIC_ICER_CLRENA_26 ((u32)0x04000000) /* bit 26 */ +#define NVIC_ICER_CLRENA_27 ((u32)0x08000000) /* bit 27 */ +#define NVIC_ICER_CLRENA_28 ((u32)0x10000000) /* bit 28 */ +#define NVIC_ICER_CLRENA_29 ((u32)0x20000000) /* bit 29 */ +#define NVIC_ICER_CLRENA_30 ((u32)0x40000000) /* bit 30 */ +#define NVIC_ICER_CLRENA_31 ((u32)0x80000000) /* bit 31 */ + + +/****************** Bit definition for NVIC_ISPR register *******************/ +#define NVIC_ISPR_SETPEND ((u32)0xFFFFFFFF) /* Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((u32)0x00000001) /* bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((u32)0x00000002) /* bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((u32)0x00000004) /* bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((u32)0x00000008) /* bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((u32)0x00000010) /* bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((u32)0x00000020) /* bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((u32)0x00000040) /* bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((u32)0x00000080) /* bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((u32)0x00000100) /* bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((u32)0x00000200) /* bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((u32)0x00000400) /* bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((u32)0x00000800) /* bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((u32)0x00001000) /* bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((u32)0x00002000) /* bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((u32)0x00004000) /* bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((u32)0x00008000) /* bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((u32)0x00010000) /* bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((u32)0x00020000) /* bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((u32)0x00040000) /* bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((u32)0x00080000) /* bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((u32)0x00100000) /* bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((u32)0x00200000) /* bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((u32)0x00400000) /* bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((u32)0x00800000) /* bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((u32)0x01000000) /* bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((u32)0x02000000) /* bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((u32)0x04000000) /* bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((u32)0x08000000) /* bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((u32)0x10000000) /* bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((u32)0x20000000) /* bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((u32)0x40000000) /* bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((u32)0x80000000) /* bit 31 */ + + +/****************** Bit definition for NVIC_ICPR register *******************/ +#define NVIC_ICPR_CLRPEND ((u32)0xFFFFFFFF) /* Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((u32)0x00000001) /* bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((u32)0x00000002) /* bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((u32)0x00000004) /* bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((u32)0x00000008) /* bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((u32)0x00000010) /* bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((u32)0x00000020) /* bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((u32)0x00000040) /* bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((u32)0x00000080) /* bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((u32)0x00000100) /* bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((u32)0x00000200) /* bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((u32)0x00000400) /* bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((u32)0x00000800) /* bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((u32)0x00001000) /* bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((u32)0x00002000) /* bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((u32)0x00004000) /* bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((u32)0x00008000) /* bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((u32)0x00010000) /* bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((u32)0x00020000) /* bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((u32)0x00040000) /* bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((u32)0x00080000) /* bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((u32)0x00100000) /* bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((u32)0x00200000) /* bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((u32)0x00400000) /* bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((u32)0x00800000) /* bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((u32)0x01000000) /* bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((u32)0x02000000) /* bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((u32)0x04000000) /* bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((u32)0x08000000) /* bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((u32)0x10000000) /* bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((u32)0x20000000) /* bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((u32)0x40000000) /* bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((u32)0x80000000) /* bit 31 */ + + +/****************** Bit definition for NVIC_IABR register *******************/ +#define NVIC_IABR_ACTIVE ((u32)0xFFFFFFFF) /* Interrupt active flags */ +#define NVIC_IABR_ACTIVE_0 ((u32)0x00000001) /* bit 0 */ +#define NVIC_IABR_ACTIVE_1 ((u32)0x00000002) /* bit 1 */ +#define NVIC_IABR_ACTIVE_2 ((u32)0x00000004) /* bit 2 */ +#define NVIC_IABR_ACTIVE_3 ((u32)0x00000008) /* bit 3 */ +#define NVIC_IABR_ACTIVE_4 ((u32)0x00000010) /* bit 4 */ +#define NVIC_IABR_ACTIVE_5 ((u32)0x00000020) /* bit 5 */ +#define NVIC_IABR_ACTIVE_6 ((u32)0x00000040) /* bit 6 */ +#define NVIC_IABR_ACTIVE_7 ((u32)0x00000080) /* bit 7 */ +#define NVIC_IABR_ACTIVE_8 ((u32)0x00000100) /* bit 8 */ +#define NVIC_IABR_ACTIVE_9 ((u32)0x00000200) /* bit 9 */ +#define NVIC_IABR_ACTIVE_10 ((u32)0x00000400) /* bit 10 */ +#define NVIC_IABR_ACTIVE_11 ((u32)0x00000800) /* bit 11 */ +#define NVIC_IABR_ACTIVE_12 ((u32)0x00001000) /* bit 12 */ +#define NVIC_IABR_ACTIVE_13 ((u32)0x00002000) /* bit 13 */ +#define NVIC_IABR_ACTIVE_14 ((u32)0x00004000) /* bit 14 */ +#define NVIC_IABR_ACTIVE_15 ((u32)0x00008000) /* bit 15 */ +#define NVIC_IABR_ACTIVE_16 ((u32)0x00010000) /* bit 16 */ +#define NVIC_IABR_ACTIVE_17 ((u32)0x00020000) /* bit 17 */ +#define NVIC_IABR_ACTIVE_18 ((u32)0x00040000) /* bit 18 */ +#define NVIC_IABR_ACTIVE_19 ((u32)0x00080000) /* bit 19 */ +#define NVIC_IABR_ACTIVE_20 ((u32)0x00100000) /* bit 20 */ +#define NVIC_IABR_ACTIVE_21 ((u32)0x00200000) /* bit 21 */ +#define NVIC_IABR_ACTIVE_22 ((u32)0x00400000) /* bit 22 */ +#define NVIC_IABR_ACTIVE_23 ((u32)0x00800000) /* bit 23 */ +#define NVIC_IABR_ACTIVE_24 ((u32)0x01000000) /* bit 24 */ +#define NVIC_IABR_ACTIVE_25 ((u32)0x02000000) /* bit 25 */ +#define NVIC_IABR_ACTIVE_26 ((u32)0x04000000) /* bit 26 */ +#define NVIC_IABR_ACTIVE_27 ((u32)0x08000000) /* bit 27 */ +#define NVIC_IABR_ACTIVE_28 ((u32)0x10000000) /* bit 28 */ +#define NVIC_IABR_ACTIVE_29 ((u32)0x20000000) /* bit 29 */ +#define NVIC_IABR_ACTIVE_30 ((u32)0x40000000) /* bit 30 */ +#define NVIC_IABR_ACTIVE_31 ((u32)0x80000000) /* bit 31 */ + + +/****************** Bit definition for NVIC_PRI0 register *******************/ +#define NVIC_IPR0_PRI_0 ((u32)0x000000FF) /* Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((u32)0x0000FF00) /* Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((u32)0x00FF0000) /* Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((u32)0xFF000000) /* Priority of interrupt 3 */ + + +/****************** Bit definition for NVIC_PRI1 register *******************/ +#define NVIC_IPR1_PRI_4 ((u32)0x000000FF) /* Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((u32)0x0000FF00) /* Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((u32)0x00FF0000) /* Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((u32)0xFF000000) /* Priority of interrupt 7 */ + + +/****************** Bit definition for NVIC_PRI2 register *******************/ +#define NVIC_IPR2_PRI_8 ((u32)0x000000FF) /* Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((u32)0x0000FF00) /* Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((u32)0x00FF0000) /* Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((u32)0xFF000000) /* Priority of interrupt 11 */ + + +/****************** Bit definition for NVIC_PRI3 register *******************/ +#define NVIC_IPR3_PRI_12 ((u32)0x000000FF) /* Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((u32)0x0000FF00) /* Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((u32)0x00FF0000) /* Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((u32)0xFF000000) /* Priority of interrupt 15 */ + + +/****************** Bit definition for NVIC_PRI4 register *******************/ +#define NVIC_IPR4_PRI_16 ((u32)0x000000FF) /* Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((u32)0x0000FF00) /* Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((u32)0x00FF0000) /* Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((u32)0xFF000000) /* Priority of interrupt 19 */ + + +/****************** Bit definition for NVIC_PRI5 register *******************/ +#define NVIC_IPR5_PRI_20 ((u32)0x000000FF) /* Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((u32)0x0000FF00) /* Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((u32)0x00FF0000) /* Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((u32)0xFF000000) /* Priority of interrupt 23 */ + + +/****************** Bit definition for NVIC_PRI6 register *******************/ +#define NVIC_IPR6_PRI_24 ((u32)0x000000FF) /* Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((u32)0x0000FF00) /* Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((u32)0x00FF0000) /* Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((u32)0xFF000000) /* Priority of interrupt 27 */ + + +/****************** Bit definition for NVIC_PRI7 register *******************/ +#define NVIC_IPR7_PRI_28 ((u32)0x000000FF) /* Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((u32)0x0000FF00) /* Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((u32)0x00FF0000) /* Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((u32)0xFF000000) /* Priority of interrupt 31 */ + + +/****************** Bit definition for SCB_CPUID register *******************/ +#define SCB_CPUID_REVISION ((u32)0x0000000F) /* Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((u32)0x0000FFF0) /* Number of processor within family */ +#define SCB_CPUID_Constant ((u32)0x000F0000) /* Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((u32)0x00F00000) /* Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((u32)0xFF000000) /* Implementer code. ARM is 0x41 */ + + +/******************* Bit definition for SCB_ICSR register *******************/ +#define SCB_ICSR_VECTACTIVE ((u32)0x000001FF) /* Active ISR number field */ +#define SCB_ICSR_RETTOBASE ((u32)0x00000800) /* All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((u32)0x003FF000) /* Pending ISR number field */ +#define SCB_ICSR_ISRPENDING ((u32)0x00400000) /* Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT ((u32)0x00800000) /* It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((u32)0x02000000) /* Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((u32)0x04000000) /* Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((u32)0x08000000) /* Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((u32)0x10000000) /* Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((u32)0x80000000) /* Set pending NMI bit */ + + +/******************* Bit definition for SCB_VTOR register *******************/ +#define SCB_VTOR_TBLOFF ((u32)0x1FFFFF80) /* Vector table base offset field */ +#define SCB_VTOR_TBLBASE ((u32)0x20000000) /* Table base in code(0) or RAM(1) */ + + +/****************** Bit definition for SCB_AIRCR register *******************/ +#define SCB_AIRCR_VECTRESET ((u32)0x00000001) /* System Reset bit */ +#define SCB_AIRCR_VECTCLRACTIVE ((u32)0x00000002) /* Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((u32)0x00000004) /* Requests chip control logic to generate a reset */ + +#define SCB_AIRCR_PRIGROUP ((u32)0x00000700) /* PRIGROUP[2:0] bits (Priority group) */ +#define SCB_AIRCR_PRIGROUP_0 ((u32)0x00000100) /* Bit 0 */ +#define SCB_AIRCR_PRIGROUP_1 ((u32)0x00000200) /* Bit 1 */ +#define SCB_AIRCR_PRIGROUP_2 ((u32)0x00000400) /* Bit 2 */ + +/* prority group configuration */ +#define SCB_AIRCR_PRIGROUP0 ((u32)0x00000000) /* Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ +#define SCB_AIRCR_PRIGROUP1 ((u32)0x00000100) /* Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP2 ((u32)0x00000200) /* Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP3 ((u32)0x00000300) /* Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP4 ((u32)0x00000400) /* Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP5 ((u32)0x00000500) /* Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP6 ((u32)0x00000600) /* Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP7 ((u32)0x00000700) /* Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ + +#define SCB_AIRCR_ENDIANESS ((u32)0x00008000) /* Data endianness bit */ +#define SCB_AIRCR_VECTKEY ((u32)0xFFFF0000) /* Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ + + +/******************* Bit definition for SCB_SCR register ********************/ +#define SCB_SCR_SLEEPONEXIT ((u8)0x02) /* Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((u8)0x04) /* Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((u8)0x10) /* Wake up from WFE */ + + +/******************** Bit definition for SCB_CCR register *******************/ +#define SCB_CCR_NONBASETHRDENA ((u16)0x0001) /* Thread mode can be entered from any level in Handler mode by controlled return value */ +#define SCB_CCR_USERSETMPEND ((u16)0x0002) /* Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ +#define SCB_CCR_UNALIGN_TRP ((u16)0x0008) /* Trap for unaligned access */ +#define SCB_CCR_DIV_0_TRP ((u16)0x0010) /* Trap on Divide by 0 */ +#define SCB_CCR_BFHFNMIGN ((u16)0x0100) /* Handlers running at priority -1 and -2 */ +#define SCB_CCR_STKALIGN ((u16)0x0200) /* On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + + +/******************* Bit definition for SCB_SHPR register ********************/ +#define SCB_SHPR_PRI_N ((u32)0x000000FF) /* Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 ((u32)0x0000FF00) /* Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 ((u32)0x00FF0000) /* Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 ((u32)0xFF000000) /* Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + + +/****************** Bit definition for SCB_SHCSR register *******************/ +#define SCB_SHCSR_MEMFAULTACT ((u32)0x00000001) /* MemManage is active */ +#define SCB_SHCSR_BUSFAULTACT ((u32)0x00000002) /* BusFault is active */ +#define SCB_SHCSR_USGFAULTACT ((u32)0x00000008) /* UsageFault is active */ +#define SCB_SHCSR_SVCALLACT ((u32)0x00000080) /* SVCall is active */ +#define SCB_SHCSR_MONITORACT ((u32)0x00000100) /* Monitor is active */ +#define SCB_SHCSR_PENDSVACT ((u32)0x00000400) /* PendSV is active */ +#define SCB_SHCSR_SYSTICKACT ((u32)0x00000800) /* SysTick is active */ +#define SCB_SHCSR_USGFAULTPENDED ((u32)0x00001000) /* Usage Fault is pended */ +#define SCB_SHCSR_MEMFAULTPENDED ((u32)0x00002000) /* MemManage is pended */ +#define SCB_SHCSR_BUSFAULTPENDED ((u32)0x00004000) /* Bus Fault is pended */ +#define SCB_SHCSR_SVCALLPENDED ((u32)0x00008000) /* SVCall is pended */ +#define SCB_SHCSR_MEMFAULTENA ((u32)0x00010000) /* MemManage enable */ +#define SCB_SHCSR_BUSFAULTENA ((u32)0x00020000) /* Bus Fault enable */ +#define SCB_SHCSR_USGFAULTENA ((u32)0x00040000) /* UsageFault enable */ + + +/******************* Bit definition for SCB_CFSR register *******************/ +/* MFSR */ +#define SCB_CFSR_IACCVIOL ((u32)0x00000001) /* Instruction access violation */ +#define SCB_CFSR_DACCVIOL ((u32)0x00000002) /* Data access violation */ +#define SCB_CFSR_MUNSTKERR ((u32)0x00000008) /* Unstacking error */ +#define SCB_CFSR_MSTKERR ((u32)0x00000010) /* Stacking error */ +#define SCB_CFSR_MMARVALID ((u32)0x00000080) /* Memory Manage Address Register address valid flag */ +/* BFSR */ +#define SCB_CFSR_IBUSERR ((u32)0x00000100) /* Instruction bus error flag */ +#define SCB_CFSR_PRECISERR ((u32)0x00000200) /* Precise data bus error */ +#define SCB_CFSR_IMPRECISERR ((u32)0x00000400) /* Imprecise data bus error */ +#define SCB_CFSR_UNSTKERR ((u32)0x00000800) /* Unstacking error */ +#define SCB_CFSR_STKERR ((u32)0x00001000) /* Stacking error */ +#define SCB_CFSR_BFARVALID ((u32)0x00008000) /* Bus Fault Address Register address valid flag */ +/* UFSR */ +#define SCB_CFSR_UNDEFINSTR ((u32)0x00010000) /* The processor attempt to excecute an undefined instruction */ +#define SCB_CFSR_INVSTATE ((u32)0x00020000) /* Invalid combination of EPSR and instruction */ +#define SCB_CFSR_INVPC ((u32)0x00040000) /* Attempt to load EXC_RETURN into pc illegally */ +#define SCB_CFSR_NOCP ((u32)0x00080000) /* Attempt to use a coprocessor instruction */ +#define SCB_CFSR_UNALIGNED ((u32)0x01000000) /* Fault occurs when there is an attempt to make an unaligned memory access */ +#define SCB_CFSR_DIVBYZERO ((u32)0x02000000) /* Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ + + +/******************* Bit definition for SCB_HFSR register *******************/ +#define SCB_HFSR_VECTTBL ((u32)0x00000002) /* Fault occures because of vector table read on exception processing */ +#define SCB_HFSR_FORCED ((u32)0x40000000) /* Hard Fault activated when a configurable Fault was received and cannot activate */ +#define SCB_HFSR_DEBUGEVT ((u32)0x80000000) /* Fault related to debug */ + + +/******************* Bit definition for SCB_DFSR register *******************/ +#define SCB_DFSR_HALTED ((u8)0x01) /* Halt request flag */ +#define SCB_DFSR_BKPT ((u8)0x02) /* BKPT flag */ +#define SCB_DFSR_DWTTRAP ((u8)0x04) /* Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((u8)0x08) /* Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((u8)0x10) /* External debug request flag */ + + +/******************* Bit definition for SCB_MMFAR register ******************/ +#define SCB_MMFAR_ADDRESS ((u32)0xFFFFFFFF) /* Mem Manage fault address field */ + + +/******************* Bit definition for SCB_BFAR register *******************/ +#define SCB_BFAR_ADDRESS ((u32)0xFFFFFFFF) /* Bus fault address field */ + + +/******************* Bit definition for SCB_afsr register *******************/ +#define SCB_AFSR_IMPDEF ((u32)0xFFFFFFFF) /* Implementation defined */ + + + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0 ((u32)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1 ((u32)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2 ((u32)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3 ((u32)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4 ((u32)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5 ((u32)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6 ((u32)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7 ((u32)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8 ((u32)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9 ((u32)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10 ((u32)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11 ((u32)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12 ((u32)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13 ((u32)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14 ((u32)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15 ((u32)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16 ((u32)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17 ((u32)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18 ((u32)0x00040000) /* Interrupt Mask on line 18 */ + + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0 ((u32)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EMR_MR1 ((u32)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EMR_MR2 ((u32)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EMR_MR3 ((u32)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EMR_MR4 ((u32)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EMR_MR5 ((u32)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EMR_MR6 ((u32)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EMR_MR7 ((u32)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EMR_MR8 ((u32)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EMR_MR9 ((u32)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EMR_MR10 ((u32)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EMR_MR11 ((u32)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EMR_MR12 ((u32)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EMR_MR13 ((u32)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EMR_MR14 ((u32)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EMR_MR15 ((u32)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EMR_MR16 ((u32)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EMR_MR17 ((u32)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EMR_MR18 ((u32)0x00040000) /* Event Mask on line 18 */ + + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0 ((u32)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1 ((u32)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2 ((u32)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3 ((u32)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4 ((u32)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5 ((u32)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6 ((u32)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7 ((u32)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8 ((u32)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9 ((u32)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10 ((u32)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11 ((u32)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12 ((u32)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13 ((u32)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14 ((u32)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15 ((u32)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16 ((u32)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17 ((u32)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18 ((u32)0x00040000) /* Rising trigger event configuration bit of line 18 */ + + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0 ((u32)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1 ((u32)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2 ((u32)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3 ((u32)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4 ((u32)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5 ((u32)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6 ((u32)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7 ((u32)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8 ((u32)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9 ((u32)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10 ((u32)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11 ((u32)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12 ((u32)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13 ((u32)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14 ((u32)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15 ((u32)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16 ((u32)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17 ((u32)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18 ((u32)0x00040000) /* Falling trigger event configuration bit of line 18 */ + + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0 ((u32)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1 ((u32)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2 ((u32)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3 ((u32)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4 ((u32)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5 ((u32)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6 ((u32)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7 ((u32)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8 ((u32)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9 ((u32)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10 ((u32)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11 ((u32)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12 ((u32)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13 ((u32)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14 ((u32)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15 ((u32)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16 ((u32)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17 ((u32)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18 ((u32)0x00040000) /* Software Interrupt on line 18 */ + + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0 ((u32)0x00000001) /* Pending bit 0 */ +#define EXTI_PR_PR1 ((u32)0x00000002) /* Pending bit 1 */ +#define EXTI_PR_PR2 ((u32)0x00000004) /* Pending bit 2 */ +#define EXTI_PR_PR3 ((u32)0x00000008) /* Pending bit 3 */ +#define EXTI_PR_PR4 ((u32)0x00000010) /* Pending bit 4 */ +#define EXTI_PR_PR5 ((u32)0x00000020) /* Pending bit 5 */ +#define EXTI_PR_PR6 ((u32)0x00000040) /* Pending bit 6 */ +#define EXTI_PR_PR7 ((u32)0x00000080) /* Pending bit 7 */ +#define EXTI_PR_PR8 ((u32)0x00000100) /* Pending bit 8 */ +#define EXTI_PR_PR9 ((u32)0x00000200) /* Pending bit 9 */ +#define EXTI_PR_PR10 ((u32)0x00000400) /* Pending bit 10 */ +#define EXTI_PR_PR11 ((u32)0x00000800) /* Pending bit 11 */ +#define EXTI_PR_PR12 ((u32)0x00001000) /* Pending bit 12 */ +#define EXTI_PR_PR13 ((u32)0x00002000) /* Pending bit 13 */ +#define EXTI_PR_PR14 ((u32)0x00004000) /* Pending bit 14 */ +#define EXTI_PR_PR15 ((u32)0x00008000) /* Pending bit 15 */ +#define EXTI_PR_PR16 ((u32)0x00010000) /* Pending bit 16 */ +#define EXTI_PR_PR17 ((u32)0x00020000) /* Pending bit 17 */ +#define EXTI_PR_PR18 ((u32)0x00040000) /* Trigger request occurred on the external interrupt line 18 */ + + + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1 ((u32)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1 ((u32)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1 ((u32)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1 ((u32)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2 ((u32)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2 ((u32)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2 ((u32)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2 ((u32)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3 ((u32)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3 ((u32)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3 ((u32)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3 ((u32)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4 ((u32)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4 ((u32)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4 ((u32)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4 ((u32)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5 ((u32)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5 ((u32)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5 ((u32)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5 ((u32)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6 ((u32)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6 ((u32)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6 ((u32)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6 ((u32)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7 ((u32)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7 ((u32)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7 ((u32)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7 ((u32)0x08000000) /* Channel 7 Transfer Error flag */ + + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1 ((u32)0x00000001) /* Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1 ((u32)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1 ((u32)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1 ((u32)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2 ((u32)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2 ((u32)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2 ((u32)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2 ((u32)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3 ((u32)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3 ((u32)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3 ((u32)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3 ((u32)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4 ((u32)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4 ((u32)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4 ((u32)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4 ((u32)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5 ((u32)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5 ((u32)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5 ((u32)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5 ((u32)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6 ((u32)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6 ((u32)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6 ((u32)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6 ((u32)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7 ((u32)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7 ((u32)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7 ((u32)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7 ((u32)0x08000000) /* Channel 7 Transfer Error clear */ + + +/******************* Bit definition for DMA_CCR1 register *******************/ +#define DMA_CCR1_EN ((u16)0x0001) /* Channel enable*/ +#define DMA_CCR1_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CCR1_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR1_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR1_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR1_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR1_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR1_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR1_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR1_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR1_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR1_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR1_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR1_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR1_PL ((u16)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR1_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR1_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR1_MEM2MEM ((u16)0x4000) /* Memory to memory mode */ + + +/******************* Bit definition for DMA_CCR2 register *******************/ +#define DMA_CCR2_EN ((u16)0x0001) /* Channel enable */ +#define DMA_CCR2_TCIE ((u16)0x0002) /* ransfer complete interrupt enable */ +#define DMA_CCR2_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR2_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR2_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR2_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR2_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR2_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR2_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR2_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR2_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR2_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR2_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR2_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR2_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR2_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR2_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR2_MEM2MEM ((u16)0x4000) /* Memory to memory mode */ + + +/******************* Bit definition for DMA_CCR3 register *******************/ +#define DMA_CCR3_EN ((u16)0x0001) /* Channel enable */ +#define DMA_CCR3_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CCR3_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR3_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR3_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR3_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR3_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR3_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR3_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR3_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR3_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR3_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR3_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR3_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR3_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR3_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR3_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR3_MEM2MEM ((u16)0x4000) /* Memory to memory mode */ + + +/******************* Bit definition for DMA_CCR4 register *******************/ +#define DMA_CCR4_EN ((u16)0x0001) /* Channel enable */ +#define DMA_CCR4_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CCR4_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR4_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR4_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR4_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR4_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR4_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR4_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR4_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR4_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR4_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR4_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR4_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR4_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR4_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR4_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR4_MEM2MEM ((u16)0x4000) /* Memory to memory mode */ + + +/****************** Bit definition for DMA_CCR5 register *******************/ +#define DMA_CCR5_EN ((u16)0x0001) /* Channel enable */ +#define DMA_CCR5_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CCR5_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR5_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR5_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR5_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR5_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR5_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR5_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR5_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR5_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR5_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR5_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR5_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR5_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR5_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR5_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR5_MEM2MEM ((u16)0x4000) /* Memory to memory mode enable */ + + +/******************* Bit definition for DMA_CCR6 register *******************/ +#define DMA_CCR6_EN ((u16)0x0001) /* Channel enable */ +#define DMA_CCR6_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CCR6_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR6_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR6_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR6_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR6_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR6_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR6_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR6_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR6_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR6_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR6_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR6_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR6_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR6_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR6_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR6_MEM2MEM ((u16)0x4000) /* Memory to memory mode */ + + +/******************* Bit definition for DMA_CCR7 register *******************/ +#define DMA_CCR7_EN ((u16)0x0001) /* Channel enable */ +#define DMA_CCR7_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CCR7_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR7_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR7_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR7_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR7_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR7_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR7_PSIZE , ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR7_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR7_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR7_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR7_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR7_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR7_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR7_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR7_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR7_MEM2MEM ((u16)0x4000) /* Memory to memory mode enable */ + + +/****************** Bit definition for DMA_CNDTR1 register ******************/ +#define DMA_CNDTR1_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CNDTR2 register ******************/ +#define DMA_CNDTR2_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CNDTR3 register ******************/ +#define DMA_CNDTR3_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CNDTR4 register ******************/ +#define DMA_CNDTR4_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CNDTR5 register ******************/ +#define DMA_CNDTR5_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CNDTR6 register ******************/ +#define DMA_CNDTR6_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CNDTR7 register ******************/ +#define DMA_CNDTR7_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CPAR1 register *******************/ +#define DMA_CPAR1_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR2 register *******************/ +#define DMA_CPAR2_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR3 register *******************/ +#define DMA_CPAR3_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR4 register *******************/ +#define DMA_CPAR4_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR5 register *******************/ +#define DMA_CPAR5_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR6 register *******************/ +#define DMA_CPAR6_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR7 register *******************/ +#define DMA_CPAR7_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CMAR1 register *******************/ +#define DMA_CMAR1_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + +/****************** Bit definition for DMA_CMAR2 register *******************/ +#define DMA_CMAR2_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + +/****************** Bit definition for DMA_CMAR3 register *******************/ +#define DMA_CMAR3_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + +/****************** Bit definition for DMA_CMAR4 register *******************/ +#define DMA_CMAR4_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + +/****************** Bit definition for DMA_CMAR5 register *******************/ +#define DMA_CMAR5_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + +/****************** Bit definition for DMA_CMAR6 register *******************/ +#define DMA_CMAR6_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + +/****************** Bit definition for DMA_CMAR7 register *******************/ +#define DMA_CMAR7_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((u8)0x01) /* Analog watchdog flag */ +#define ADC_SR_EOC ((u8)0x02) /* End of conversion */ +#define ADC_SR_JEOC ((u8)0x04) /* Injected channel end of conversion */ +#define ADC_SR_JSTRT ((u8)0x08) /* Injected channel Start flag */ +#define ADC_SR_STRT ((u8)0x10) /* Regular channel Start flag */ + + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH ((u32)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CR1_AWDCH_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_CR1_AWDCH_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_CR1_AWDCH_2 ((u32)0x00000004) /* Bit 2 */ +#define ADC_CR1_AWDCH_3 ((u32)0x00000008) /* Bit 3 */ +#define ADC_CR1_AWDCH_4 ((u32)0x00000010) /* Bit 4 */ + +#define ADC_CR1_EOCIE ((u32)0x00000020) /* Interrupt enable for EOC */ +#define ADC_CR1_AWDIE ((u32)0x00000040) /* AAnalog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE ((u32)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_CR1_SCAN ((u32)0x00000100) /* Scan mode */ +#define ADC_CR1_AWDSGL ((u32)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO ((u32)0x00000400) /* Automatic injected group conversion */ +#define ADC_CR1_DISCEN ((u32)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN ((u32)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_CR1_DISCNUM ((u32)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CR1_DISCNUM_0 ((u32)0x00002000) /* Bit 0 */ +#define ADC_CR1_DISCNUM_1 ((u32)0x00004000) /* Bit 1 */ +#define ADC_CR1_DISCNUM_2 ((u32)0x00008000) /* Bit 2 */ + +#define ADC_CR1_DUALMOD ((u32)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_CR1_DUALMOD_0 ((u32)0x00010000) /* Bit 0 */ +#define ADC_CR1_DUALMOD_1 ((u32)0x00020000) /* Bit 1 */ +#define ADC_CR1_DUALMOD_2 ((u32)0x00040000) /* Bit 2 */ +#define ADC_CR1_DUALMOD_3 ((u32)0x00080000) /* Bit 3 */ + +#define ADC_CR1_JAWDEN ((u32)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN ((u32)0x00800000) /* Analog watchdog enable on regular channels */ + + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON ((u32)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CR2_CONT ((u32)0x00000002) /* Continuous Conversion */ +#define ADC_CR2_CAL ((u32)0x00000004) /* A/D Calibration */ +#define ADC_CR2_RSTCAL ((u32)0x00000008) /* Reset Calibration */ +#define ADC_CR2_DMA ((u32)0x00000100) /* Direct Memory access mode */ +#define ADC_CR2_ALIGN ((u32)0x00000800) /* Data Alignment */ + +#define ADC_CR2_JEXTSEL ((u32)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_CR2_JEXTSEL_0 ((u32)0x00001000) /* Bit 0 */ +#define ADC_CR2_JEXTSEL_1 ((u32)0x00002000) /* Bit 1 */ +#define ADC_CR2_JEXTSEL_2 ((u32)0x00004000) /* Bit 2 */ + +#define ADC_CR2_JEXTTRIG ((u32)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_CR2_EXTSEL ((u32)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_CR2_EXTSEL_0 ((u32)0x00020000) /* Bit 0 */ +#define ADC_CR2_EXTSEL_1 ((u32)0x00040000) /* Bit 1 */ +#define ADC_CR2_EXTSEL_2 ((u32)0x00080000) /* Bit 2 */ + +#define ADC_CR2_EXTTRIG ((u32)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_CR2_JSWSTART ((u32)0x00200000) /* Start Conversion of injected channels */ +#define ADC_CR2_SWSTART ((u32)0x00400000) /* Start Conversion of regular channels */ +#define ADC_CR2_TSVREFE ((u32)0x00800000) /* Temperature Sensor and VREFINT Enable */ + + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP10 ((u32)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMPR1_SMP10_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_SMPR1_SMP10_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_SMPR1_SMP10_2 ((u32)0x00000004) /* Bit 2 */ + +#define ADC_SMPR1_SMP11 ((u32)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMPR1_SMP11_0 ((u32)0x00000008) /* Bit 0 */ +#define ADC_SMPR1_SMP11_1 ((u32)0x00000010) /* Bit 1 */ +#define ADC_SMPR1_SMP11_2 ((u32)0x00000020) /* Bit 2 */ + +#define ADC_SMPR1_SMP12 ((u32)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMPR1_SMP12_0 ((u32)0x00000040) /* Bit 0 */ +#define ADC_SMPR1_SMP12_1 ((u32)0x00000080) /* Bit 1 */ +#define ADC_SMPR1_SMP12_2 ((u32)0x00000100) /* Bit 2 */ + +#define ADC_SMPR1_SMP13 ((u32)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMPR1_SMP13_0 ((u32)0x00000200) /* Bit 0 */ +#define ADC_SMPR1_SMP13_1 ((u32)0x00000400) /* Bit 1 */ +#define ADC_SMPR1_SMP13_2 ((u32)0x00000800) /* Bit 2 */ + +#define ADC_SMPR1_SMP14 ((u32)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMPR1_SMP14_0 ((u32)0x00001000) /* Bit 0 */ +#define ADC_SMPR1_SMP14_1 ((u32)0x00002000) /* Bit 1 */ +#define ADC_SMPR1_SMP14_2 ((u32)0x00004000) /* Bit 2 */ + +#define ADC_SMPR1_SMP15 ((u32)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMPR1_SMP15_0 ((u32)0x00008000) /* Bit 0 */ +#define ADC_SMPR1_SMP15_1 ((u32)0x00010000) /* Bit 1 */ +#define ADC_SMPR1_SMP15_2 ((u32)0x00020000) /* Bit 2 */ + +#define ADC_SMPR1_SMP16 ((u32)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMPR1_SMP16_0 ((u32)0x00040000) /* Bit 0 */ +#define ADC_SMPR1_SMP16_1 ((u32)0x00080000) /* Bit 1 */ +#define ADC_SMPR1_SMP16_2 ((u32)0x00100000) /* Bit 2 */ + +#define ADC_SMPR1_SMP17 ((u32)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMPR1_SMP17_0 ((u32)0x00200000) /* Bit 0 */ +#define ADC_SMPR1_SMP17_1 ((u32)0x00400000) /* Bit 1 */ +#define ADC_SMPR1_SMP17_2 ((u32)0x00800000) /* Bit 2 */ + + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP0 ((u32)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMPR2_SMP0_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_SMPR2_SMP0_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_SMPR2_SMP0_2 ((u32)0x00000004) /* Bit 2 */ + +#define ADC_SMPR2_SMP1 ((u32)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMPR2_SMP1_0 ((u32)0x00000008) /* Bit 0 */ +#define ADC_SMPR2_SMP1_1 ((u32)0x00000010) /* Bit 1 */ +#define ADC_SMPR2_SMP1_2 ((u32)0x00000020) /* Bit 2 */ + +#define ADC_SMPR2_SMP2 ((u32)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMPR2_SMP2_0 ((u32)0x00000040) /* Bit 0 */ +#define ADC_SMPR2_SMP2_1 ((u32)0x00000080) /* Bit 1 */ +#define ADC_SMPR2_SMP2_2 ((u32)0x00000100) /* Bit 2 */ + +#define ADC_SMPR2_SMP3 ((u32)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMPR2_SMP3_0 ((u32)0x00000200) /* Bit 0 */ +#define ADC_SMPR2_SMP3_1 ((u32)0x00000400) /* Bit 1 */ +#define ADC_SMPR2_SMP3_2 ((u32)0x00000800) /* Bit 2 */ + +#define ADC_SMPR2_SMP4 ((u32)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMPR2_SMP4_0 ((u32)0x00001000) /* Bit 0 */ +#define ADC_SMPR2_SMP4_1 ((u32)0x00002000) /* Bit 1 */ +#define ADC_SMPR2_SMP4_2 ((u32)0x00004000) /* Bit 2 */ + +#define ADC_SMPR2_SMP5 ((u32)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR2_SMP5_0 ((u32)0x00008000) /* Bit 0 */ +#define ADC_SMPR2_SMP5_1 ((u32)0x00010000) /* Bit 1 */ +#define ADC_SMPR2_SMP5_2 ((u32)0x00020000) /* Bit 2 */ + +#define ADC_SMPR2_SMP6 ((u32)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMPR2_SMP6_0 ((u32)0x00040000) /* Bit 0 */ +#define ADC_SMPR2_SMP6_1 ((u32)0x00080000) /* Bit 1 */ +#define ADC_SMPR2_SMP6_2 ((u32)0x00100000) /* Bit 2 */ + +#define ADC_SMPR2_SMP7 ((u32)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMPR2_SMP7_0 ((u32)0x00200000) /* Bit 0 */ +#define ADC_SMPR2_SMP7_1 ((u32)0x00400000) /* Bit 1 */ +#define ADC_SMPR2_SMP7_2 ((u32)0x00800000) /* Bit 2 */ + +#define ADC_SMPR2_SMP8 ((u32)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMPR2_SMP8_0 ((u32)0x01000000) /* Bit 0 */ +#define ADC_SMPR2_SMP8_1 ((u32)0x02000000) /* Bit 1 */ +#define ADC_SMPR2_SMP8_2 ((u32)0x04000000) /* Bit 2 */ + +#define ADC_SMPR2_SMP9 ((u32)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMPR2_SMP9_0 ((u32)0x08000000) /* Bit 0 */ +#define ADC_SMPR2_SMP9_1 ((u32)0x10000000) /* Bit 1 */ +#define ADC_SMPR2_SMP9_2 ((u32)0x20000000) /* Bit 2 */ + + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1 ((u16)0x0FFF) /* Data offset for injected channel 1 */ + + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2 ((u16)0x0FFF) /* Data offset for injected channel 2 */ + + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3 ((u16)0x0FFF) /* Data offset for injected channel 3 */ + + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4 ((u16)0x0FFF) /* Data offset for injected channel 4 */ + + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT ((u16)0x0FFF) /* Analog watchdog high threshold */ + + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT ((u16)0x0FFF) /* Analog watchdog low threshold */ + + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_SQ13 ((u32)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQR1_SQ13_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_SQR1_SQ13_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_SQR1_SQ13_2 ((u32)0x00000004) /* Bit 2 */ +#define ADC_SQR1_SQ13_3 ((u32)0x00000008) /* Bit 3 */ +#define ADC_SQR1_SQ13_4 ((u32)0x00000010) /* Bit 4 */ + +#define ADC_SQR1_SQ14 ((u32)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQR1_SQ14_0 ((u32)0x00000020) /* Bit 0 */ +#define ADC_SQR1_SQ14_1 ((u32)0x00000040) /* Bit 1 */ +#define ADC_SQR1_SQ14_2 ((u32)0x00000080) /* Bit 2 */ +#define ADC_SQR1_SQ14_3 ((u32)0x00000100) /* Bit 3 */ +#define ADC_SQR1_SQ14_4 ((u32)0x00000200) /* Bit 4 */ + +#define ADC_SQR1_SQ15 ((u32)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQR1_SQ15_0 ((u32)0x00000400) /* Bit 0 */ +#define ADC_SQR1_SQ15_1 ((u32)0x00000800) /* Bit 1 */ +#define ADC_SQR1_SQ15_2 ((u32)0x00001000) /* Bit 2 */ +#define ADC_SQR1_SQ15_3 ((u32)0x00002000) /* Bit 3 */ +#define ADC_SQR1_SQ15_4 ((u32)0x00004000) /* Bit 4 */ + +#define ADC_SQR1_SQ16 ((u32)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQR1_SQ16_0 ((u32)0x00008000) /* Bit 0 */ +#define ADC_SQR1_SQ16_1 ((u32)0x00010000) /* Bit 1 */ +#define ADC_SQR1_SQ16_2 ((u32)0x00020000) /* Bit 2 */ +#define ADC_SQR1_SQ16_3 ((u32)0x00040000) /* Bit 3 */ +#define ADC_SQR1_SQ16_4 ((u32)0x00080000) /* Bit 4 */ + +#define ADC_SQR1_L ((u32)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_SQR1_L_0 ((u32)0x00100000) /* Bit 0 */ +#define ADC_SQR1_L_1 ((u32)0x00200000) /* Bit 1 */ +#define ADC_SQR1_L_2 ((u32)0x00400000) /* Bit 2 */ +#define ADC_SQR1_L_3 ((u32)0x00800000) /* Bit 3 */ + + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ7 ((u32)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQR2_SQ7_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_SQR2_SQ7_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_SQR2_SQ7_2 ((u32)0x00000004) /* Bit 2 */ +#define ADC_SQR2_SQ7_3 ((u32)0x00000008) /* Bit 3 */ +#define ADC_SQR2_SQ7_4 ((u32)0x00000010) /* Bit 4 */ + +#define ADC_SQR2_SQ8 ((u32)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQR2_SQ8_0 ((u32)0x00000020) /* Bit 0 */ +#define ADC_SQR2_SQ8_1 ((u32)0x00000040) /* Bit 1 */ +#define ADC_SQR2_SQ8_2 ((u32)0x00000080) /* Bit 2 */ +#define ADC_SQR2_SQ8_3 ((u32)0x00000100) /* Bit 3 */ +#define ADC_SQR2_SQ8_4 ((u32)0x00000200) /* Bit 4 */ + +#define ADC_SQR2_SQ9 ((u32)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQR2_SQ9_0 ((u32)0x00000400) /* Bit 0 */ +#define ADC_SQR2_SQ9_1 ((u32)0x00000800) /* Bit 1 */ +#define ADC_SQR2_SQ9_2 ((u32)0x00001000) /* Bit 2 */ +#define ADC_SQR2_SQ9_3 ((u32)0x00002000) /* Bit 3 */ +#define ADC_SQR2_SQ9_4 ((u32)0x00004000) /* Bit 4 */ + +#define ADC_SQR2_SQ10 ((u32)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQR2_SQ10_0 ((u32)0x00008000) /* Bit 0 */ +#define ADC_SQR2_SQ10_1 ((u32)0x00010000) /* Bit 1 */ +#define ADC_SQR2_SQ10_2 ((u32)0x00020000) /* Bit 2 */ +#define ADC_SQR2_SQ10_3 ((u32)0x00040000) /* Bit 3 */ +#define ADC_SQR2_SQ10_4 ((u32)0x00080000) /* Bit 4 */ + +#define ADC_SQR2_SQ11 ((u32)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQR2_SQ11_0 ((u32)0x00100000) /* Bit 0 */ +#define ADC_SQR2_SQ11_1 ((u32)0x00200000) /* Bit 1 */ +#define ADC_SQR2_SQ11_2 ((u32)0x00400000) /* Bit 2 */ +#define ADC_SQR2_SQ11_3 ((u32)0x00800000) /* Bit 3 */ +#define ADC_SQR2_SQ11_4 ((u32)0x01000000) /* Bit 4 */ + +#define ADC_SQR2_SQ12 ((u32)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQR2_SQ12_0 ((u32)0x02000000) /* Bit 0 */ +#define ADC_SQR2_SQ12_1 ((u32)0x04000000) /* Bit 1 */ +#define ADC_SQR2_SQ12_2 ((u32)0x08000000) /* Bit 2 */ +#define ADC_SQR2_SQ12_3 ((u32)0x10000000) /* Bit 3 */ +#define ADC_SQR2_SQ12_4 ((u32)0x20000000) /* Bit 4 */ + + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ1 ((u32)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQR3_SQ1_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_SQR3_SQ1_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_SQR3_SQ1_2 ((u32)0x00000004) /* Bit 2 */ +#define ADC_SQR3_SQ1_3 ((u32)0x00000008) /* Bit 3 */ +#define ADC_SQR3_SQ1_4 ((u32)0x00000010) /* Bit 4 */ + +#define ADC_SQR3_SQ2 ((u32)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQR3_SQ2_0 ((u32)0x00000020) /* Bit 0 */ +#define ADC_SQR3_SQ2_1 ((u32)0x00000040) /* Bit 1 */ +#define ADC_SQR3_SQ2_2 ((u32)0x00000080) /* Bit 2 */ +#define ADC_SQR3_SQ2_3 ((u32)0x00000100) /* Bit 3 */ +#define ADC_SQR3_SQ2_4 ((u32)0x00000200) /* Bit 4 */ + +#define ADC_SQR3_SQ3 ((u32)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQR3_SQ3_0 ((u32)0x00000400) /* Bit 0 */ +#define ADC_SQR3_SQ3_1 ((u32)0x00000800) /* Bit 1 */ +#define ADC_SQR3_SQ3_2 ((u32)0x00001000) /* Bit 2 */ +#define ADC_SQR3_SQ3_3 ((u32)0x00002000) /* Bit 3 */ +#define ADC_SQR3_SQ3_4 ((u32)0x00004000) /* Bit 4 */ + +#define ADC_SQR3_SQ4 ((u32)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQR3_SQ4_0 ((u32)0x00008000) /* Bit 0 */ +#define ADC_SQR3_SQ4_1 ((u32)0x00010000) /* Bit 1 */ +#define ADC_SQR3_SQ4_2 ((u32)0x00020000) /* Bit 2 */ +#define ADC_SQR3_SQ4_3 ((u32)0x00040000) /* Bit 3 */ +#define ADC_SQR3_SQ4_4 ((u32)0x00080000) /* Bit 4 */ + +#define ADC_SQR3_SQ5 ((u32)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQR3_SQ5_0 ((u32)0x00100000) /* Bit 0 */ +#define ADC_SQR3_SQ5_1 ((u32)0x00200000) /* Bit 1 */ +#define ADC_SQR3_SQ5_2 ((u32)0x00400000) /* Bit 2 */ +#define ADC_SQR3_SQ5_3 ((u32)0x00800000) /* Bit 3 */ +#define ADC_SQR3_SQ5_4 ((u32)0x01000000) /* Bit 4 */ + +#define ADC_SQR3_SQ6 ((u32)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQR3_SQ6_0 ((u32)0x02000000) /* Bit 0 */ +#define ADC_SQR3_SQ6_1 ((u32)0x04000000) /* Bit 1 */ +#define ADC_SQR3_SQ6_2 ((u32)0x08000000) /* Bit 2 */ +#define ADC_SQR3_SQ6_3 ((u32)0x10000000) /* Bit 3 */ +#define ADC_SQR3_SQ6_4 ((u32)0x20000000) /* Bit 4 */ + + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1 ((u32)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQR_JSQ1_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_JSQR_JSQ1_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_JSQR_JSQ1_2 ((u32)0x00000004) /* Bit 2 */ +#define ADC_JSQR_JSQ1_3 ((u32)0x00000008) /* Bit 3 */ +#define ADC_JSQR_JSQ1_4 ((u32)0x00000010) /* Bit 4 */ + +#define ADC_JSQR_JSQ2 ((u32)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQR_JSQ2_0 ((u32)0x00000020) /* Bit 0 */ +#define ADC_JSQR_JSQ2_1 ((u32)0x00000040) /* Bit 1 */ +#define ADC_JSQR_JSQ2_2 ((u32)0x00000080) /* Bit 2 */ +#define ADC_JSQR_JSQ2_3 ((u32)0x00000100) /* Bit 3 */ +#define ADC_JSQR_JSQ2_4 ((u32)0x00000200) /* Bit 4 */ + +#define ADC_JSQR_JSQ3 ((u32)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQR_JSQ3_0 ((u32)0x00000400) /* Bit 0 */ +#define ADC_JSQR_JSQ3_1 ((u32)0x00000800) /* Bit 1 */ +#define ADC_JSQR_JSQ3_2 ((u32)0x00001000) /* Bit 2 */ +#define ADC_JSQR_JSQ3_3 ((u32)0x00002000) /* Bit 3 */ +#define ADC_JSQR_JSQ3_4 ((u32)0x00004000) /* Bit 4 */ + +#define ADC_JSQR_JSQ4 ((u32)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQR_JSQ4_0 ((u32)0x00008000) /* Bit 0 */ +#define ADC_JSQR_JSQ4_1 ((u32)0x00010000) /* Bit 1 */ +#define ADC_JSQR_JSQ4_2 ((u32)0x00020000) /* Bit 2 */ +#define ADC_JSQR_JSQ4_3 ((u32)0x00040000) /* Bit 3 */ +#define ADC_JSQR_JSQ4_4 ((u32)0x00080000) /* Bit 4 */ + +#define ADC_JSQR_JL ((u32)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JSQR_JL_0 ((u32)0x00100000) /* Bit 0 */ +#define ADC_JSQR_JL_1 ((u32)0x00200000) /* Bit 1 */ + + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA ((u16)0xFFFF) /* Injected data */ + + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA ((u16)0xFFFF) /* Injected data */ + + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA ((u16)0xFFFF) /* Injected data */ + + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA ((u16)0xFFFF) /* Injected data */ + + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA ((u32)0x0000FFFF) /* Regular data */ +#define ADC_DR_ADC2DATA ((u32)0xFFFF0000) /* ADC2 data */ + + + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1 ((u32)0x00000001) /* DAC channel1 enable */ +#define DAC_CR_BOFF1 ((u32)0x00000002) /* DAC channel1 output buffer disable */ +#define DAC_CR_TEN1 ((u32)0x00000004) /* DAC channel1 Trigger enable */ + +#define DAC_CR_TSEL1 ((u32)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_CR_TSEL1_0 ((u32)0x00000008) /* Bit 0 */ +#define DAC_CR_TSEL1_1 ((u32)0x00000010) /* Bit 1 */ +#define DAC_CR_TSEL1_2 ((u32)0x00000020) /* Bit 2 */ + +#define DAC_CR_WAVE1 ((u32)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE1_0 ((u32)0x00000040) /* Bit 0 */ +#define DAC_CR_WAVE1_1 ((u32)0x00000080) /* Bit 1 */ + +#define DAC_CR_MAMP1 ((u32)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_CR_MAMP1_0 ((u32)0x00000100) /* Bit 0 */ +#define DAC_CR_MAMP1_1 ((u32)0x00000200) /* Bit 1 */ +#define DAC_CR_MAMP1_2 ((u32)0x00000400) /* Bit 2 */ +#define DAC_CR_MAMP1_3 ((u32)0x00000800) /* Bit 3 */ + +#define DAC_CR_DMAEN1 ((u32)0x00001000) /* DAC channel1 DMA enable */ +#define DAC_CR_EN2 ((u32)0x00010000) /* DAC channel2 enable */ +#define DAC_CR_BOFF2 ((u32)0x00020000) /* DAC channel2 output buffer disable */ +#define DAC_CR_TEN2 ((u32)0x00040000) /* DAC channel2 Trigger enable */ + +#define DAC_CR_TSEL2 ((u32)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_CR_TSEL2_0 ((u32)0x00080000) /* Bit 0 */ +#define DAC_CR_TSEL2_1 ((u32)0x00100000) /* Bit 1 */ +#define DAC_CR_TSEL2_2 ((u32)0x00200000) /* Bit 2 */ + +#define DAC_CR_WAVE2 ((u32)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE2_0 ((u32)0x00400000) /* Bit 0 */ +#define DAC_CR_WAVE2_1 ((u32)0x00800000) /* Bit 1 */ + +#define DAC_CR_MAMP2 ((u32)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_CR_MAMP2_0 ((u32)0x01000000) /* Bit 0 */ +#define DAC_CR_MAMP2_1 ((u32)0x02000000) /* Bit 1 */ +#define DAC_CR_MAMP2_2 ((u32)0x04000000) /* Bit 2 */ +#define DAC_CR_MAMP2_3 ((u32)0x08000000) /* Bit 3 */ + +#define DAC_CR_DMAEN2 ((u32)0x10000000) /* DAC channel2 DMA enabled */ + + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((u8)0x01) /* DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 ((u8)0x02) /* DAC channel2 software trigger */ + + +/***************** Bit definition for DAC_DHR12R1 register ******************/ +#define DAC_DHR12R1_DACC1DHR ((u16)0x0FFF) /* DAC channel1 12-bit Right aligned data */ + + +/***************** Bit definition for DAC_DHR12L1 register ******************/ +#define DAC_DHR12L1_DACC1DHR ((u16)0xFFF0) /* DAC channel1 12-bit Left aligned data */ + + +/****************** Bit definition for DAC_DHR8R1 register ******************/ +#define DAC_DHR8R1_DACC1DHR ((u8)0xFF) /* DAC channel1 8-bit Right aligned data */ + + +/***************** Bit definition for DAC_DHR12R2 register ******************/ +#define DAC_DHR12R2_DACC2DHR ((u16)0x0FFF) /* DAC channel2 12-bit Right aligned data */ + + +/***************** Bit definition for DAC_DHR12L2 register ******************/ +#define DAC_DHR12L2_DACC2DHR ((u16)0xFFF0) /* DAC channel2 12-bit Left aligned data */ + + +/****************** Bit definition for DAC_DHR8R2 register ******************/ +#define DAC_DHR8R2_DACC2DHR ((u8)0xFF) /* DAC channel2 8-bit Right aligned data */ + + +/***************** Bit definition for DAC_DHR12RD register ******************/ +#define DAC_DHR12RD_DACC1DHR ((u32)0x00000FFF) /* DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12RD_DACC2DHR ((u32)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */ + + +/***************** Bit definition for DAC_DHR12LD register ******************/ +#define DAC_DHR12LD_DACC1DHR ((u32)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12LD_DACC2DHR ((u32)0xFFF00000) /* DAC channel2 12-bit Left aligned data */ + + +/****************** Bit definition for DAC_DHR8RD register ******************/ +#define DAC_DHR8RD_DACC1DHR ((u16)0x00FF) /* DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8RD_DACC2DHR ((u16)0xFF00) /* DAC channel2 8-bit Right aligned data */ + + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DOR1_DACC1DOR ((u16)0x0FFF) /* DAC channel1 data output */ + + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DOR2_DACC2DOR ((u16)0x0FFF) /* DAC channel2 data output */ + + + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN ((u16)0x0001) /* Counter enable */ +#define TIM_CR1_UDIS ((u16)0x0002) /* Update disable */ +#define TIM_CR1_URS ((u16)0x0004) /* Update request source */ +#define TIM_CR1_OPM ((u16)0x0008) /* One pulse mode */ +#define TIM_CR1_DIR ((u16)0x0010) /* Direction */ + +#define TIM_CR1_CMS ((u16)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CR1_CMS_0 ((u16)0x0020) /* Bit 0 */ +#define TIM_CR1_CMS_1 ((u16)0x0040) /* Bit 1 */ + +#define TIM_CR1_ARPE ((u16)0x0080) /* Auto-reload preload enable */ + +#define TIM_CR1_CKD ((u16)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CR1_CKD_0 ((u16)0x0100) /* Bit 0 */ +#define TIM_CR1_CKD_1 ((u16)0x0200) /* Bit 1 */ + + +/******************* Bit definition for TIM_CR2 register ********************/ +#define TIM_CR2_CCPC ((u16)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CR2_CCUS ((u16)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CR2_CCDS ((u16)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_CR2_MMS ((u16)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_CR2_MMS_0 ((u16)0x0010) /* Bit 0 */ +#define TIM_CR2_MMS_1 ((u16)0x0020) /* Bit 1 */ +#define TIM_CR2_MMS_2 ((u16)0x0040) /* Bit 2 */ + +#define TIM_CR2_TI1S ((u16)0x0080) /* TI1 Selection */ +#define TIM_CR2_OIS1 ((u16)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_CR2_OIS1N ((u16)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_CR2_OIS2 ((u16)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_CR2_OIS2N ((u16)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_CR2_OIS3 ((u16)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_CR2_OIS3N ((u16)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_CR2_OIS4 ((u16)0x4000) /* Output Idle state 4 (OC4 output) */ + + +/******************* Bit definition for TIM_SMCR register *******************/ +#define TIM_SMCR_SMS ((u16)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMCR_SMS_0 ((u16)0x0001) /* Bit 0 */ +#define TIM_SMCR_SMS_1 ((u16)0x0002) /* Bit 1 */ +#define TIM_SMCR_SMS_2 ((u16)0x0004) /* Bit 2 */ + +#define TIM_SMCR_TS ((u16)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_SMCR_TS_0 ((u16)0x0010) /* Bit 0 */ +#define TIM_SMCR_TS_1 ((u16)0x0020) /* Bit 1 */ +#define TIM_SMCR_TS_2 ((u16)0x0040) /* Bit 2 */ + +#define TIM_SMCR_MSM ((u16)0x0080) /* Master/slave mode */ + +#define TIM_SMCR_ETF ((u16)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_SMCR_ETF_0 ((u16)0x0100) /* Bit 0 */ +#define TIM_SMCR_ETF_1 ((u16)0x0200) /* Bit 1 */ +#define TIM_SMCR_ETF_2 ((u16)0x0400) /* Bit 2 */ +#define TIM_SMCR_ETF_3 ((u16)0x0800) /* Bit 3 */ + +#define TIM_SMCR_ETPS ((u16)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_SMCR_ETPS_0 ((u16)0x1000) /* Bit 0 */ +#define TIM_SMCR_ETPS_1 ((u16)0x2000) /* Bit 1 */ + +#define TIM_SMCR_ECE ((u16)0x4000) /* External clock enable */ +#define TIM_SMCR_ETP ((u16)0x8000) /* External trigger polarity */ + + +/******************* Bit definition for TIM_DIER register *******************/ +#define TIM_DIER_UIE ((u16)0x0001) /* Update interrupt enable */ +#define TIM_DIER_CC1IE ((u16)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_DIER_CC2IE ((u16)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_DIER_CC3IE ((u16)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_DIER_CC4IE ((u16)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_DIER_COMIE ((u16)0x0020) /* COM interrupt enable */ +#define TIM_DIER_TIE ((u16)0x0040) /* Trigger interrupt enable */ +#define TIM_DIER_BIE ((u16)0x0080) /* Break interrupt enable */ +#define TIM_DIER_UDE ((u16)0x0100) /* Update DMA request enable */ +#define TIM_DIER_CC1DE ((u16)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_DIER_CC2DE ((u16)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_DIER_CC3DE ((u16)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_DIER_CC4DE ((u16)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_DIER_COMDE ((u16)0x2000) /* COM DMA request enable */ +#define TIM_DIER_TDE ((u16)0x4000) /* Trigger DMA request enable */ + + +/******************** Bit definition for TIM_SR register ********************/ +#define TIM_SR_UIF ((u16)0x0001) /* Update interrupt Flag */ +#define TIM_SR_CC1IF ((u16)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_SR_CC2IF ((u16)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_SR_CC3IF ((u16)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_SR_CC4IF ((u16)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_SR_COMIF ((u16)0x0020) /* COM interrupt Flag */ +#define TIM_SR_TIF ((u16)0x0040) /* Trigger interrupt Flag */ +#define TIM_SR_BIF ((u16)0x0080) /* Break interrupt Flag */ +#define TIM_SR_CC1OF ((u16)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_SR_CC2OF ((u16)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_SR_CC3OF ((u16)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_SR_CC4OF ((u16)0x1000) /* Capture/Compare 4 Overcapture Flag */ + + +/******************* Bit definition for TIM_EGR register ********************/ +#define TIM_EGR_UG ((u8)0x01) /* Update Generation */ +#define TIM_EGR_CC1G ((u8)0x02) /* Capture/Compare 1 Generation */ +#define TIM_EGR_CC2G ((u8)0x04) /* Capture/Compare 2 Generation */ +#define TIM_EGR_CC3G ((u8)0x08) /* Capture/Compare 3 Generation */ +#define TIM_EGR_CC4G ((u8)0x10) /* Capture/Compare 4 Generation */ +#define TIM_EGR_COMG ((u8)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_EGR_TG ((u8)0x40) /* Trigger Generation */ +#define TIM_EGR_BG ((u8)0x80) /* Break Generation */ + + +/****************** Bit definition for TIM_CCMR1 register *******************/ +#define TIM_CCMR1_CC1S ((u16)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CCMR1_CC1S_0 ((u16)0x0001) /* Bit 0 */ +#define TIM_CCMR1_CC1S_1 ((u16)0x0002) /* Bit 1 */ + +#define TIM_CCMR1_OC1FE ((u16)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_CCMR1_OC1PE ((u16)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_CCMR1_OC1M ((u16)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_CCMR1_OC1M_0 ((u16)0x0010) /* Bit 0 */ +#define TIM_CCMR1_OC1M_1 ((u16)0x0020) /* Bit 1 */ +#define TIM_CCMR1_OC1M_2 ((u16)0x0040) /* Bit 2 */ + +#define TIM_CCMR1_OC1CE ((u16)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CCMR1_CC2S ((u16)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CCMR1_CC2S_0 ((u16)0x0100) /* Bit 0 */ +#define TIM_CCMR1_CC2S_1 ((u16)0x0200) /* Bit 1 */ + +#define TIM_CCMR1_OC2FE ((u16)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_CCMR1_OC2PE ((u16)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_CCMR1_OC2M ((u16)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_CCMR1_OC2M_0 ((u16)0x1000) /* Bit 0 */ +#define TIM_CCMR1_OC2M_1 ((u16)0x2000) /* Bit 1 */ +#define TIM_CCMR1_OC2M_2 ((u16)0x4000) /* Bit 2 */ + +#define TIM_CCMR1_OC2CE ((u16)0x8000) /* Output Compare 2 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR1_IC1PSC ((u16)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_CCMR1_IC1PSC_0 ((u16)0x0004) /* Bit 0 */ +#define TIM_CCMR1_IC1PSC_1 ((u16)0x0008) /* Bit 1 */ + +#define TIM_CCMR1_IC1F ((u16)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_CCMR1_IC1F_0 ((u16)0x0010) /* Bit 0 */ +#define TIM_CCMR1_IC1F_1 ((u16)0x0020) /* Bit 1 */ +#define TIM_CCMR1_IC1F_2 ((u16)0x0040) /* Bit 2 */ +#define TIM_CCMR1_IC1F_3 ((u16)0x0080) /* Bit 3 */ + +#define TIM_CCMR1_IC2PSC ((u16)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_CCMR1_IC2PSC_0 ((u16)0x0400) /* Bit 0 */ +#define TIM_CCMR1_IC2PSC_1 ((u16)0x0800) /* Bit 1 */ + +#define TIM_CCMR1_IC2F ((u16)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_CCMR1_IC2F_0 ((u16)0x1000) /* Bit 0 */ +#define TIM_CCMR1_IC2F_1 ((u16)0x2000) /* Bit 1 */ +#define TIM_CCMR1_IC2F_2 ((u16)0x4000) /* Bit 2 */ +#define TIM_CCMR1_IC2F_3 ((u16)0x8000) /* Bit 3 */ + + +/****************** Bit definition for TIM_CCMR2 register *******************/ +#define TIM_CCMR2_CC3S ((u16)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CCMR2_CC3S_0 ((u16)0x0001) /* Bit 0 */ +#define TIM_CCMR2_CC3S_1 ((u16)0x0002) /* Bit 1 */ + +#define TIM_CCMR2_OC3FE ((u16)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_CCMR2_OC3PE ((u16)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_CCMR2_OC3M ((u16)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_CCMR2_OC3M_0 ((u16)0x0010) /* Bit 0 */ +#define TIM_CCMR2_OC3M_1 ((u16)0x0020) /* Bit 1 */ +#define TIM_CCMR2_OC3M_2 ((u16)0x0040) /* Bit 2 */ + +#define TIM_CCMR2_OC3CE ((u16)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CCMR2_CC4S ((u16)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CCMR2_CC4S_0 ((u16)0x0100) /* Bit 0 */ +#define TIM_CCMR2_CC4S_1 ((u16)0x0200) /* Bit 1 */ + +#define TIM_CCMR2_OC4FE ((u16)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_CCMR2_OC4PE ((u16)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_CCMR2_OC4M ((u16)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_CCMR2_OC4M_0 ((u16)0x1000) /* Bit 0 */ +#define TIM_CCMR2_OC4M_1 ((u16)0x2000) /* Bit 1 */ +#define TIM_CCMR2_OC4M_2 ((u16)0x4000) /* Bit 2 */ + +#define TIM_CCMR2_OC4CE ((u16)0x8000) /* Output Compare 4 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR2_IC3PSC ((u16)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_CCMR2_IC3PSC_0 ((u16)0x0004) /* Bit 0 */ +#define TIM_CCMR2_IC3PSC_1 ((u16)0x0008) /* Bit 1 */ + +#define TIM_CCMR2_IC3F ((u16)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_CCMR2_IC3F_0 ((u16)0x0010) /* Bit 0 */ +#define TIM_CCMR2_IC3F_1 ((u16)0x0020) /* Bit 1 */ +#define TIM_CCMR2_IC3F_2 ((u16)0x0040) /* Bit 2 */ +#define TIM_CCMR2_IC3F_3 ((u16)0x0080) /* Bit 3 */ + +#define TIM_CCMR2_IC4PSC ((u16)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_CCMR2_IC4PSC_0 ((u16)0x0400) /* Bit 0 */ +#define TIM_CCMR2_IC4PSC_1 ((u16)0x0800) /* Bit 1 */ + +#define TIM_CCMR2_IC4F ((u16)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_CCMR2_IC4F_0 ((u16)0x1000) /* Bit 0 */ +#define TIM_CCMR2_IC4F_1 ((u16)0x2000) /* Bit 1 */ +#define TIM_CCMR2_IC4F_2 ((u16)0x4000) /* Bit 2 */ +#define TIM_CCMR2_IC4F_3 ((u16)0x8000) /* Bit 3 */ + + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CCER_CC1E ((u16)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CCER_CC1P ((u16)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CCER_CC1NE ((u16)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CCER_CC1NP ((u16)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CCER_CC2E ((u16)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CCER_CC2P ((u16)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CCER_CC2NE ((u16)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CCER_CC2NP ((u16)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CCER_CC3E ((u16)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CCER_CC3P ((u16)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CCER_CC3NE ((u16)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CCER_CC3NP ((u16)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CCER_CC4E ((u16)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CCER_CC4P ((u16)0x2000) /* Capture/Compare 4 output Polarity */ + + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT_CNT ((u16)0xFFFF) /* Counter Value */ + + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC_PSC ((u16)0xFFFF) /* Prescaler Value */ + + +/******************* Bit definition for TIM_ARR register ********************/ +#define TIM_ARR_ARR ((u16)0xFFFF) /* actual auto-reload Value */ + + +/******************* Bit definition for TIM_RCR register ********************/ +#define TIM_RCR_REP ((u8)0xFF) /* Repetition Counter Value */ + + +/******************* Bit definition for TIM_CCR1 register *******************/ +#define TIM_CCR1_CCR1 ((u16)0xFFFF) /* Capture/Compare 1 Value */ + + +/******************* Bit definition for TIM_CCR2 register *******************/ +#define TIM_CCR2_CCR2 ((u16)0xFFFF) /* Capture/Compare 2 Value */ + + +/******************* Bit definition for TIM_CCR3 register *******************/ +#define TIM_CCR3_CCR3 ((u16)0xFFFF) /* Capture/Compare 3 Value */ + + +/******************* Bit definition for TIM_CCR4 register *******************/ +#define TIM_CCR4_CCR4 ((u16)0xFFFF) /* Capture/Compare 4 Value */ + + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_BDTR_DTG ((u16)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_BDTR_DTG_0 ((u16)0x0001) /* Bit 0 */ +#define TIM_BDTR_DTG_1 ((u16)0x0002) /* Bit 1 */ +#define TIM_BDTR_DTG_2 ((u16)0x0004) /* Bit 2 */ +#define TIM_BDTR_DTG_3 ((u16)0x0008) /* Bit 3 */ +#define TIM_BDTR_DTG_4 ((u16)0x0010) /* Bit 4 */ +#define TIM_BDTR_DTG_5 ((u16)0x0020) /* Bit 5 */ +#define TIM_BDTR_DTG_6 ((u16)0x0040) /* Bit 6 */ +#define TIM_BDTR_DTG_7 ((u16)0x0080) /* Bit 7 */ + +#define TIM_BDTR_LOCK ((u16)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_BDTR_LOCK_0 ((u16)0x0100) /* Bit 0 */ +#define TIM_BDTR_LOCK_1 ((u16)0x0200) /* Bit 1 */ + +#define TIM_BDTR_OSSI ((u16)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_BDTR_OSSR ((u16)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BDTR_BKE ((u16)0x1000) /* Break enable */ +#define TIM_BDTR_BKP ((u16)0x2000) /* Break Polarity */ +#define TIM_BDTR_AOE ((u16)0x4000) /* Automatic Output enable */ +#define TIM_BDTR_MOE ((u16)0x8000) /* Main Output enable */ + + +/******************* Bit definition for TIM_DCR register ********************/ +#define TIM_DCR_DBA ((u16)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DCR_DBA_0 ((u16)0x0001) /* Bit 0 */ +#define TIM_DCR_DBA_1 ((u16)0x0002) /* Bit 1 */ +#define TIM_DCR_DBA_2 ((u16)0x0004) /* Bit 2 */ +#define TIM_DCR_DBA_3 ((u16)0x0008) /* Bit 3 */ +#define TIM_DCR_DBA_4 ((u16)0x0010) /* Bit 4 */ + +#define TIM_DCR_DBL ((u16)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DCR_DBL_0 ((u16)0x0100) /* Bit 0 */ +#define TIM_DCR_DBL_1 ((u16)0x0200) /* Bit 1 */ +#define TIM_DCR_DBL_2 ((u16)0x0400) /* Bit 2 */ +#define TIM_DCR_DBL_3 ((u16)0x0800) /* Bit 3 */ +#define TIM_DCR_DBL_4 ((u16)0x1000) /* Bit 4 */ + + +/******************* Bit definition for TIM_DMAR register *******************/ +#define TIM_DMAR_DMAB ((u16)0xFFFF) /* DMA register for burst accesses */ + + + +/******************************************************************************/ +/* */ +/* Real-Time Clock */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CRH register ********************/ +#define RTC_CRH_SECIE ((u8)0x01) /* Second Interrupt Enable */ +#define RTC_CRH_ALRIE ((u8)0x02) /* Alarm Interrupt Enable */ +#define RTC_CRH_OWIE ((u8)0x04) /* OverfloW Interrupt Enable */ + + +/******************* Bit definition for RTC_CRL register ********************/ +#define RTC_CRL_SECF ((u8)0x01) /* Second Flag */ +#define RTC_CRL_ALRF ((u8)0x02) /* Alarm Flag */ +#define RTC_CRL_OWF ((u8)0x04) /* OverfloW Flag */ +#define RTC_CRL_RSF ((u8)0x08) /* Registers Synchronized Flag */ +#define RTC_CRL_CNF ((u8)0x10) /* Configuration Flag */ +#define RTC_CRL_RTOFF ((u8)0x20) /* RTC operation OFF */ + + +/******************* Bit definition for RTC_PRLH register *******************/ +#define RTC_PRLH_PRL ((u16)0x000F) /* RTC Prescaler Reload Value High */ + + +/******************* Bit definition for RTC_PRLL register *******************/ +#define RTC_PRLL_PRL ((u16)0xFFFF) /* RTC Prescaler Reload Value Low */ + + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((u16)0x000F) /* RTC Clock Divider High */ + + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((u16)0xFFFF) /* RTC Clock Divider Low */ + + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((u16)0xFFFF) /* RTC Counter High */ + + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((u16)0xFFFF) /* RTC Counter Low */ + + +/******************* Bit definition for RTC_ALRH register *******************/ +#define RTC_ALRH_RTC_ALR ((u16)0xFFFF) /* RTC Alarm High */ + + +/******************* Bit definition for RTC_ALRL register *******************/ +#define RTC_ALRL_RTC_ALR ((u16)0xFFFF) /* RTC Alarm Low */ + + + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY ((u16)0xFFFF) /* Key value (write only, read 0000h) */ + + +/******************* Bit definition for IWDG_PR register ********************/ +#define IWDG_PR_PR ((u8)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 ((u8)0x01) /* Bit 0 */ +#define IWDG_PR_PR_1 ((u8)0x02) /* Bit 1 */ +#define IWDG_PR_PR_2 ((u8)0x04) /* Bit 2 */ + + +/******************* Bit definition for IWDG_RLR register *******************/ +#define IWDG_RLR_RL ((u16)0x0FFF) /* Watchdog counter reload value */ + + +/******************* Bit definition for IWDG_SR register ********************/ +#define IWDG_SR_PVU ((u8)0x01) /* Watchdog prescaler value update */ +#define IWDG_SR_RVU ((u8)0x02) /* Watchdog counter reload value update */ + + + +/******************************************************************************/ +/* */ +/* Window WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CR register ********************/ +#define WWDG_CR_T ((u8)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CR_T0 ((u8)0x01) /* Bit 0 */ +#define WWDG_CR_T1 ((u8)0x02) /* Bit 1 */ +#define WWDG_CR_T2 ((u8)0x04) /* Bit 2 */ +#define WWDG_CR_T3 ((u8)0x08) /* Bit 3 */ +#define WWDG_CR_T4 ((u8)0x10) /* Bit 4 */ +#define WWDG_CR_T5 ((u8)0x20) /* Bit 5 */ +#define WWDG_CR_T6 ((u8)0x40) /* Bit 6 */ + +#define WWDG_CR_WDGA ((u8)0x80) /* Activation bit */ + + +/******************* Bit definition for WWDG_CFR register *******************/ +#define WWDG_CFR_W ((u16)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFR_W0 ((u16)0x0001) /* Bit 0 */ +#define WWDG_CFR_W1 ((u16)0x0002) /* Bit 1 */ +#define WWDG_CFR_W2 ((u16)0x0004) /* Bit 2 */ +#define WWDG_CFR_W3 ((u16)0x0008) /* Bit 3 */ +#define WWDG_CFR_W4 ((u16)0x0010) /* Bit 4 */ +#define WWDG_CFR_W5 ((u16)0x0020) /* Bit 5 */ +#define WWDG_CFR_W6 ((u16)0x0040) /* Bit 6 */ + +#define WWDG_CFR_WDGTB ((u16)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFR_WDGTB0 ((u16)0x0080) /* Bit 0 */ +#define WWDG_CFR_WDGTB1 ((u16)0x0100) /* Bit 1 */ + +#define WWDG_CFR_EWI ((u16)0x0200) /* Early Wakeup Interrupt */ + + +/******************* Bit definition for WWDG_SR register ********************/ +#define WWDG_SR_EWIF ((u8)0x01) /* Early Wakeup Interrupt Flag */ + + + +/******************************************************************************/ +/* */ +/* Flexible Static Memory Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for FSMC_BCR1 register *******************/ +#define FSMC_BCR1_MBKEN ((u32)0x00000001) /* Memory bank enable bit */ +#define FSMC_BCR1_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */ + +#define FSMC_BCR1_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR1_MTYP_0 ((u32)0x00000004) /* Bit 0 */ +#define FSMC_BCR1_MTYP_1 ((u32)0x00000008) /* Bit 1 */ + +#define FSMC_BCR1_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR1_MWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BCR1_MWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_BCR1_FACCEN ((u32)0x00000040) /* Flash access enable */ +#define FSMC_BCR1_BURSTEN ((u32)0x00000100) /* Burst enable bit */ +#define FSMC_BCR1_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit */ +#define FSMC_BCR1_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */ +#define FSMC_BCR1_WAITCFG ((u32)0x00000800) /* Wait timing configuration */ +#define FSMC_BCR1_WREN ((u32)0x00001000) /* Write enable bit */ +#define FSMC_BCR1_WAITEN ((u32)0x00002000) /* Wait enable bit */ +#define FSMC_BCR1_EXTMOD ((u32)0x00004000) /* Extended mode enable */ +#define FSMC_BCR1_CBURSTRW ((u32)0x00080000) /* Write burst enable */ + + +/****************** Bit definition for FSMC_BCR2 register *******************/ +#define FSMC_BCR2_MBKEN ((u32)0x00000001) /* Memory bank enable bit */ +#define FSMC_BCR2_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */ + +#define FSMC_BCR2_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR2_MTYP_0 ((u32)0x00000004) /* Bit 0 */ +#define FSMC_BCR2_MTYP_1 ((u32)0x00000008) /* Bit 1 */ + +#define FSMC_BCR2_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR2_MWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BCR2_MWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_BCR2_FACCEN ((u32)0x00000040) /* Flash access enable */ +#define FSMC_BCR2_BURSTEN ((u32)0x00000100) /* Burst enable bit */ +#define FSMC_BCR2_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit */ +#define FSMC_BCR2_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */ +#define FSMC_BCR2_WAITCFG ((u32)0x00000800) /* Wait timing configuration */ +#define FSMC_BCR2_WREN ((u32)0x00001000) /* Write enable bit */ +#define FSMC_BCR2_WAITEN ((u32)0x00002000) /* Wait enable bit */ +#define FSMC_BCR2_EXTMOD ((u32)0x00004000) /* Extended mode enable */ +#define FSMC_BCR2_CBURSTRW ((u32)0x00080000) /* Write burst enable */ + + +/****************** Bit definition for FSMC_BCR3 register *******************/ +#define FSMC_BCR3_MBKEN ((u32)0x00000001) /* Memory bank enable bit */ +#define FSMC_BCR3_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */ + +#define FSMC_BCR3_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR3_MTYP_0 ((u32)0x00000004) /* Bit 0 */ +#define FSMC_BCR3_MTYP_1 ((u32)0x00000008) /* Bit 1 */ + +#define FSMC_BCR3_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR3_MWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BCR3_MWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_BCR3_FACCEN ((u32)0x00000040) /* Flash access enable */ +#define FSMC_BCR3_BURSTEN ((u32)0x00000100) /* Burst enable bit */ +#define FSMC_BCR3_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit. */ +#define FSMC_BCR3_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */ +#define FSMC_BCR3_WAITCFG ((u32)0x00000800) /* Wait timing configuration */ +#define FSMC_BCR3_WREN ((u32)0x00001000) /* Write enable bit */ +#define FSMC_BCR3_WAITEN ((u32)0x00002000) /* Wait enable bit */ +#define FSMC_BCR3_EXTMOD ((u32)0x00004000) /* Extended mode enable */ +#define FSMC_BCR3_CBURSTRW ((u32)0x00080000) /* Write burst enable */ + + +/****************** Bit definition for FSMC_BCR4 register *******************/ +#define FSMC_BCR4_MBKEN ((u32)0x00000001) /* Memory bank enable bit */ +#define FSMC_BCR4_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */ + +#define FSMC_BCR4_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR4_MTYP_0 ((u32)0x00000004) /* Bit 0 */ +#define FSMC_BCR4_MTYP_1 ((u32)0x00000008) /* Bit 1 */ + +#define FSMC_BCR4_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR4_MWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BCR4_MWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_BCR4_FACCEN ((u32)0x00000040) /* Flash access enable */ +#define FSMC_BCR4_BURSTEN ((u32)0x00000100) /* Burst enable bit */ +#define FSMC_BCR4_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit */ +#define FSMC_BCR4_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */ +#define FSMC_BCR4_WAITCFG ((u32)0x00000800) /* Wait timing configuration */ +#define FSMC_BCR4_WREN ((u32)0x00001000) /* Write enable bit */ +#define FSMC_BCR4_WAITEN ((u32)0x00002000) /* Wait enable bit */ +#define FSMC_BCR4_EXTMOD ((u32)0x00004000) /* Extended mode enable */ +#define FSMC_BCR4_CBURSTRW ((u32)0x00080000) /* Write burst enable */ + + +/****************** Bit definition for FSMC_BTR1 register ******************/ +#define FSMC_BTR1_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR1_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BTR1_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BTR1_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BTR1_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BTR1_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR1_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BTR1_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BTR1_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BTR1_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BTR1_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR1_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BTR1_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BTR1_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BTR1_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BTR1_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR1_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BTR1_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BTR1_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BTR1_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BTR1_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR1_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BTR1_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BTR1_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BTR1_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BTR1_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR1_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BTR1_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BTR1_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BTR1_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BTR1_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR1_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BTR1_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_BTR2 register *******************/ +#define FSMC_BTR2_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR2_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BTR2_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BTR2_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BTR2_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BTR2_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR2_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BTR2_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BTR2_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BTR2_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BTR2_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR2_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BTR2_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BTR2_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BTR2_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BTR2_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR2_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BTR2_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BTR2_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BTR2_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BTR2_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR2_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BTR2_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BTR2_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BTR2_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BTR2_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR2_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BTR2_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BTR2_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BTR2_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BTR2_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR2_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BTR2_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/******************* Bit definition for FSMC_BTR3 register *******************/ +#define FSMC_BTR3_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR3_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BTR3_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BTR3_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BTR3_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BTR3_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR3_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BTR3_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BTR3_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BTR3_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BTR3_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR3_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BTR3_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BTR3_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BTR3_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BTR3_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR3_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BTR3_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BTR3_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BTR3_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BTR3_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR3_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BTR3_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BTR3_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BTR3_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BTR3_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR3_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BTR3_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BTR3_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BTR3_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BTR3_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR3_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BTR3_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_BTR4 register *******************/ +#define FSMC_BTR4_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR4_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BTR4_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BTR4_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BTR4_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BTR4_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR4_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BTR4_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BTR4_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BTR4_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BTR4_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR4_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BTR4_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BTR4_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BTR4_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BTR4_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR4_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BTR4_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BTR4_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BTR4_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BTR4_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR4_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BTR4_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BTR4_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BTR4_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BTR4_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR4_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BTR4_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BTR4_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BTR4_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BTR4_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR4_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BTR4_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_BWTR1 register ******************/ +#define FSMC_BWTR1_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR1_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BWTR1_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BWTR1_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BWTR1_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BWTR1_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR1_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BWTR1_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BWTR1_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BWTR1_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BWTR1_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR1_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BWTR1_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BWTR1_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BWTR1_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BWTR1_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BWTR1_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BWTR1_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BWTR1_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BWTR1_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BWTR1_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR1_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BWTR1_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BWTR1_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BWTR1_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BWTR1_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR1_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BWTR1_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BWTR1_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BWTR1_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BWTR1_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR1_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BWTR1_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_BWTR2 register ******************/ +#define FSMC_BWTR2_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR2_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BWTR2_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BWTR2_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BWTR2_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BWTR2_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR2_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BWTR2_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BWTR2_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BWTR2_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BWTR2_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR2_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BWTR2_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BWTR2_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BWTR2_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BWTR2_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BWTR2_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BWTR2_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BWTR2_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BWTR2_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BWTR2_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR2_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BWTR2_CLKDIV_1 ((u32)0x00200000) /* Bit 1*/ +#define FSMC_BWTR2_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BWTR2_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BWTR2_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR2_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BWTR2_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BWTR2_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BWTR2_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BWTR2_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR2_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BWTR2_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_BWTR3 register ******************/ +#define FSMC_BWTR3_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR3_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BWTR3_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BWTR3_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BWTR3_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BWTR3_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR3_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BWTR3_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BWTR3_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BWTR3_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BWTR3_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR3_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BWTR3_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BWTR3_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BWTR3_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BWTR3_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BWTR3_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BWTR3_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BWTR3_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BWTR3_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BWTR3_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR3_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BWTR3_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BWTR3_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BWTR3_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BWTR3_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR3_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BWTR3_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BWTR3_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BWTR3_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BWTR3_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR3_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BWTR3_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_BWTR4 register ******************/ +#define FSMC_BWTR4_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR4_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BWTR4_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BWTR4_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BWTR4_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BWTR4_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR4_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BWTR4_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BWTR4_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BWTR4_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BWTR4_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR4_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BWTR4_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BWTR4_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BWTR4_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BWTR4_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BWTR4_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BWTR4_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BWTR4_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BWTR4_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BWTR4_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR4_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BWTR4_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BWTR4_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BWTR4_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BWTR4_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR4_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BWTR4_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BWTR4_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BWTR4_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BWTR4_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR4_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BWTR4_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_PCR2 register *******************/ +#define FSMC_PCR2_PWAITEN ((u32)0x00000002) /* Wait feature enable bit */ +#define FSMC_PCR2_PBKEN ((u32)0x00000004) /* PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR2_PTYP ((u32)0x00000008) /* Memory type */ + +#define FSMC_PCR2_PWID ((u32)0x00000030) /* PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR2_PWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_PCR2_PWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_PCR2_ECCEN ((u32)0x00000040) /* ECC computation logic enable bit */ +#define FSMC_PCR2_ADLOW ((u32)0x00000100) /* Address low bit delivery */ + +#define FSMC_PCR2_TCLR ((u32)0x00001E00) /* TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR2_TCLR_0 ((u32)0x00000200) /* Bit 0 */ +#define FSMC_PCR2_TCLR_1 ((u32)0x00000400) /* Bit 1 */ +#define FSMC_PCR2_TCLR_2 ((u32)0x00000800) /* Bit 2 */ +#define FSMC_PCR2_TCLR_3 ((u32)0x00001000) /* Bit 3 */ + +#define FSMC_PCR2_TAR ((u32)0x0001E000) /* TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR2_TAR_0 ((u32)0x00002000) /* Bit 0 */ +#define FSMC_PCR2_TAR_1 ((u32)0x00004000) /* Bit 1 */ +#define FSMC_PCR2_TAR_2 ((u32)0x00008000) /* Bit 2 */ +#define FSMC_PCR2_TAR_3 ((u32)0x00010000) /* Bit 3 */ + +#define FSMC_PCR2_ECCPS ((u32)0x000E0000) /* ECCPS[1:0] bits (ECC page size) */ +#define FSMC_PCR2_ECCPS_0 ((u32)0x00020000) /* Bit 0 */ +#define FSMC_PCR2_ECCPS_1 ((u32)0x00040000) /* Bit 1 */ +#define FSMC_PCR2_ECCPS_2 ((u32)0x00080000) /* Bit 2 */ + + +/****************** Bit definition for FSMC_PCR3 register *******************/ +#define FSMC_PCR3_PWAITEN ((u32)0x00000002) /* Wait feature enable bit */ +#define FSMC_PCR3_PBKEN ((u32)0x00000004) /* PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR3_PTYP ((u32)0x00000008) /* Memory type */ + +#define FSMC_PCR3_PWID ((u32)0x00000030) /* PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR3_PWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_PCR3_PWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_PCR3_ECCEN ((u32)0x00000040) /* ECC computation logic enable bit */ +#define FSMC_PCR3_ADLOW ((u32)0x00000100) /* Address low bit delivery */ + +#define FSMC_PCR3_TCLR ((u32)0x00001E00) /* TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR3_TCLR_0 ((u32)0x00000200) /* Bit 0 */ +#define FSMC_PCR3_TCLR_1 ((u32)0x00000400) /* Bit 1 */ +#define FSMC_PCR3_TCLR_2 ((u32)0x00000800) /* Bit 2 */ +#define FSMC_PCR3_TCLR_3 ((u32)0x00001000) /* Bit 3 */ + +#define FSMC_PCR3_TAR ((u32)0x0001E000) /* TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR3_TAR_0 ((u32)0x00002000) /* Bit 0 */ +#define FSMC_PCR3_TAR_1 ((u32)0x00004000) /* Bit 1 */ +#define FSMC_PCR3_TAR_2 ((u32)0x00008000) /* Bit 2 */ +#define FSMC_PCR3_TAR_3 ((u32)0x00010000) /* Bit 3 */ + +#define FSMC_PCR3_ECCPS ((u32)0x000E0000) /* ECCPS[2:0] bits (ECC page size) */ +#define FSMC_PCR3_ECCPS_0 ((u32)0x00020000) /* Bit 0 */ +#define FSMC_PCR3_ECCPS_1 ((u32)0x00040000) /* Bit 1 */ +#define FSMC_PCR3_ECCPS_2 ((u32)0x00080000) /* Bit 2 */ + + +/****************** Bit definition for FSMC_PCR4 register *******************/ +#define FSMC_PCR4_PWAITEN ((u32)0x00000002) /* Wait feature enable bit */ +#define FSMC_PCR4_PBKEN ((u32)0x00000004) /* PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR4_PTYP ((u32)0x00000008) /* Memory type */ + +#define FSMC_PCR4_PWID ((u32)0x00000030) /* PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR4_PWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_PCR4_PWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_PCR4_ECCEN ((u32)0x00000040) /* ECC computation logic enable bit */ +#define FSMC_PCR4_ADLOW ((u32)0x00000100) /* Address low bit delivery */ + +#define FSMC_PCR4_TCLR ((u32)0x00001E00) /* TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR4_TCLR_0 ((u32)0x00000200) /* Bit 0 */ +#define FSMC_PCR4_TCLR_1 ((u32)0x00000400) /* Bit 1 */ +#define FSMC_PCR4_TCLR_2 ((u32)0x00000800) /* Bit 2 */ +#define FSMC_PCR4_TCLR_3 ((u32)0x00001000) /* Bit 3 */ + +#define FSMC_PCR4_TAR ((u32)0x0001E000) /* TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR4_TAR_0 ((u32)0x00002000) /* Bit 0 */ +#define FSMC_PCR4_TAR_1 ((u32)0x00004000) /* Bit 1 */ +#define FSMC_PCR4_TAR_2 ((u32)0x00008000) /* Bit 2 */ +#define FSMC_PCR4_TAR_3 ((u32)0x00010000) /* Bit 3 */ + +#define FSMC_PCR4_ECCPS ((u32)0x000E0000) /* ECCPS[2:0] bits (ECC page size) */ +#define FSMC_PCR4_ECCPS_0 ((u32)0x00020000) /* Bit 0 */ +#define FSMC_PCR4_ECCPS_1 ((u32)0x00040000) /* Bit 1 */ +#define FSMC_PCR4_ECCPS_2 ((u32)0x00080000) /* Bit 2 */ + + +/******************* Bit definition for FSMC_SR2 register *******************/ +#define FSMC_SR2_IRS ((u8)0x01) /* Interrupt Rising Edge status */ +#define FSMC_SR2_ILS ((u8)0x02) /* Interrupt Level status */ +#define FSMC_SR2_IFS ((u8)0x04) /* Interrupt Falling Edge status */ +#define FSMC_SR2_IREN ((u8)0x08) /* Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR2_ILEN ((u8)0x10) /* Interrupt Level detection Enable bit */ +#define FSMC_SR2_IFEN ((u8)0x20) /* Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR2_FEMPT ((u8)0x40) /* FIFO empty */ + + +/******************* Bit definition for FSMC_SR3 register *******************/ +#define FSMC_SR3_IRS ((u8)0x01) /* Interrupt Rising Edge status */ +#define FSMC_SR3_ILS ((u8)0x02) /* Interrupt Level status */ +#define FSMC_SR3_IFS ((u8)0x04) /* Interrupt Falling Edge status */ +#define FSMC_SR3_IREN ((u8)0x08) /* Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR3_ILEN ((u8)0x10) /* Interrupt Level detection Enable bit */ +#define FSMC_SR3_IFEN ((u8)0x20) /* Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR3_FEMPT ((u8)0x40) /* FIFO empty */ + + +/******************* Bit definition for FSMC_SR4 register *******************/ +#define FSMC_SR4_IRS ((u8)0x01) /* Interrupt Rising Edge status */ +#define FSMC_SR4_ILS ((u8)0x02) /* Interrupt Level status */ +#define FSMC_SR4_IFS ((u8)0x04) /* Interrupt Falling Edge status */ +#define FSMC_SR4_IREN ((u8)0x08) /* Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR4_ILEN ((u8)0x10) /* Interrupt Level detection Enable bit */ +#define FSMC_SR4_IFEN ((u8)0x20) /* Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR4_FEMPT ((u8)0x40) /* FIFO empty */ + + +/****************** Bit definition for FSMC_PMEM2 register ******************/ +#define FSMC_PMEM2_MEMSET2 ((u32)0x000000FF) /* MEMSET2[7:0] bits (Common memory 2 setup time) */ +#define FSMC_PMEM2_MEMSET2_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PMEM2_MEMSET2_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PMEM2_MEMSET2_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PMEM2_MEMSET2_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PMEM2_MEMSET2_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PMEM2_MEMSET2_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PMEM2_MEMSET2_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PMEM2_MEMSET2_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PMEM2_MEMWAIT2 ((u32)0x0000FF00) /* MEMWAIT2[7:0] bits (Common memory 2 wait time) */ +#define FSMC_PMEM2_MEMWAIT2_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PMEM2_MEMWAIT2_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PMEM2_MEMWAIT2_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PMEM2_MEMWAIT2_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PMEM2_MEMWAIT2_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PMEM2_MEMWAIT2_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PMEM2_MEMWAIT2_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PMEM2_MEMWAIT2_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PMEM2_MEMHOLD2 ((u32)0x00FF0000) /* MEMHOLD2[7:0] bits (Common memory 2 hold time) */ +#define FSMC_PMEM2_MEMHOLD2_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PMEM2_MEMHOLD2_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PMEM2_MEMHOLD2_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PMEM2_MEMHOLD2_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PMEM2_MEMHOLD2_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PMEM2_MEMHOLD2_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PMEM2_MEMHOLD2_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PMEM2_MEMHOLD2_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PMEM2_MEMHIZ2 ((u32)0xFF000000) /* MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ +#define FSMC_PMEM2_MEMHIZ2_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PMEM2_MEMHIZ2_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PMEM2_MEMHIZ2_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PMEM2_MEMHIZ2_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PMEM2_MEMHIZ2_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PMEM2_MEMHIZ2_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PMEM2_MEMHIZ2_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PMEM2_MEMHIZ2_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_PMEM3 register ******************/ +#define FSMC_PMEM3_MEMSET3 ((u32)0x000000FF) /* MEMSET3[7:0] bits (Common memory 3 setup time) */ +#define FSMC_PMEM3_MEMSET3_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PMEM3_MEMSET3_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PMEM3_MEMSET3_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PMEM3_MEMSET3_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PMEM3_MEMSET3_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PMEM3_MEMSET3_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PMEM3_MEMSET3_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PMEM3_MEMSET3_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PMEM3_MEMWAIT3 ((u32)0x0000FF00) /* MEMWAIT3[7:0] bits (Common memory 3 wait time) */ +#define FSMC_PMEM3_MEMWAIT3_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PMEM3_MEMWAIT3_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PMEM3_MEMWAIT3_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PMEM3_MEMWAIT3_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PMEM3_MEMWAIT3_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PMEM3_MEMWAIT3_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PMEM3_MEMWAIT3_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PMEM3_MEMWAIT3_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PMEM3_MEMHOLD3 ((u32)0x00FF0000) /* MEMHOLD3[7:0] bits (Common memory 3 hold time) */ +#define FSMC_PMEM3_MEMHOLD3_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PMEM3_MEMHOLD3_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PMEM3_MEMHOLD3_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PMEM3_MEMHOLD3_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PMEM3_MEMHOLD3_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PMEM3_MEMHOLD3_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PMEM3_MEMHOLD3_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PMEM3_MEMHOLD3_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PMEM3_MEMHIZ3 ((u32)0xFF000000) /* MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ +#define FSMC_PMEM3_MEMHIZ3_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PMEM3_MEMHIZ3_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PMEM3_MEMHIZ3_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PMEM3_MEMHIZ3_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PMEM3_MEMHIZ3_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PMEM3_MEMHIZ3_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PMEM3_MEMHIZ3_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PMEM3_MEMHIZ3_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_PMEM4 register ******************/ +#define FSMC_PMEM4_MEMSET4 ((u32)0x000000FF) /* MEMSET4[7:0] bits (Common memory 4 setup time) */ +#define FSMC_PMEM4_MEMSET4_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PMEM4_MEMSET4_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PMEM4_MEMSET4_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PMEM4_MEMSET4_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PMEM4_MEMSET4_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PMEM4_MEMSET4_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PMEM4_MEMSET4_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PMEM4_MEMSET4_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PMEM4_MEMWAIT4 ((u32)0x0000FF00) /* MEMWAIT4[7:0] bits (Common memory 4 wait time) */ +#define FSMC_PMEM4_MEMWAIT4_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PMEM4_MEMWAIT4_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PMEM4_MEMWAIT4_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PMEM4_MEMWAIT4_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PMEM4_MEMWAIT4_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PMEM4_MEMWAIT4_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PMEM4_MEMWAIT4_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PMEM4_MEMWAIT4_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PMEM4_MEMHOLD4 ((u32)0x00FF0000) /* MEMHOLD4[7:0] bits (Common memory 4 hold time) */ +#define FSMC_PMEM4_MEMHOLD4_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PMEM4_MEMHOLD4_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PMEM4_MEMHOLD4_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PMEM4_MEMHOLD4_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PMEM4_MEMHOLD4_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PMEM4_MEMHOLD4_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PMEM4_MEMHOLD4_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PMEM4_MEMHOLD4_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PMEM4_MEMHIZ4 ((u32)0xFF000000) /* MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ +#define FSMC_PMEM4_MEMHIZ4_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PMEM4_MEMHIZ4_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PMEM4_MEMHIZ4_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PMEM4_MEMHIZ4_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PMEM4_MEMHIZ4_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PMEM4_MEMHIZ4_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PMEM4_MEMHIZ4_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PMEM4_MEMHIZ4_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_PATT2 register ******************/ +#define FSMC_PATT2_ATTSET2 ((u32)0x000000FF) /* ATTSET2[7:0] bits (Attribute memory 2 setup time) */ +#define FSMC_PATT2_ATTSET2_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PATT2_ATTSET2_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PATT2_ATTSET2_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PATT2_ATTSET2_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PATT2_ATTSET2_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PATT2_ATTSET2_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PATT2_ATTSET2_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PATT2_ATTSET2_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PATT2_ATTWAIT2 ((u32)0x0000FF00) /* ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ +#define FSMC_PATT2_ATTWAIT2_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PATT2_ATTWAIT2_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PATT2_ATTWAIT2_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PATT2_ATTWAIT2_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PATT2_ATTWAIT2_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PATT2_ATTWAIT2_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PATT2_ATTWAIT2_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PATT2_ATTWAIT2_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PATT2_ATTHOLD2 ((u32)0x00FF0000) /* ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ +#define FSMC_PATT2_ATTHOLD2_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PATT2_ATTHOLD2_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PATT2_ATTHOLD2_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PATT2_ATTHOLD2_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PATT2_ATTHOLD2_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PATT2_ATTHOLD2_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PATT2_ATTHOLD2_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PATT2_ATTHOLD2_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PATT2_ATTHIZ2 ((u32)0xFF000000) /* ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ +#define FSMC_PATT2_ATTHIZ2_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PATT2_ATTHIZ2_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PATT2_ATTHIZ2_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PATT2_ATTHIZ2_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PATT2_ATTHIZ2_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PATT2_ATTHIZ2_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PATT2_ATTHIZ2_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PATT2_ATTHIZ2_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_PATT3 register ******************/ +#define FSMC_PATT3_ATTSET3 ((u32)0x000000FF) /* ATTSET3[7:0] bits (Attribute memory 3 setup time) */ +#define FSMC_PATT3_ATTSET3_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PATT3_ATTSET3_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PATT3_ATTSET3_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PATT3_ATTSET3_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PATT3_ATTSET3_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PATT3_ATTSET3_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PATT3_ATTSET3_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PATT3_ATTSET3_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PATT3_ATTWAIT3 ((u32)0x0000FF00) /* ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ +#define FSMC_PATT3_ATTWAIT3_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PATT3_ATTWAIT3_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PATT3_ATTWAIT3_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PATT3_ATTWAIT3_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PATT3_ATTWAIT3_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PATT3_ATTWAIT3_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PATT3_ATTWAIT3_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PATT3_ATTWAIT3_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PATT3_ATTHOLD3 ((u32)0x00FF0000) /* ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ +#define FSMC_PATT3_ATTHOLD3_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PATT3_ATTHOLD3_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PATT3_ATTHOLD3_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PATT3_ATTHOLD3_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PATT3_ATTHOLD3_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PATT3_ATTHOLD3_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PATT3_ATTHOLD3_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PATT3_ATTHOLD3_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PATT3_ATTHIZ3 ((u32)0xFF000000) /* ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ +#define FSMC_PATT3_ATTHIZ3_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PATT3_ATTHIZ3_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PATT3_ATTHIZ3_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PATT3_ATTHIZ3_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PATT3_ATTHIZ3_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PATT3_ATTHIZ3_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PATT3_ATTHIZ3_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PATT3_ATTHIZ3_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_PATT4 register ******************/ +#define FSMC_PATT4_ATTSET4 ((u32)0x000000FF) /* ATTSET4[7:0] bits (Attribute memory 4 setup time) */ +#define FSMC_PATT4_ATTSET4_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PATT4_ATTSET4_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PATT4_ATTSET4_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PATT4_ATTSET4_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PATT4_ATTSET4_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PATT4_ATTSET4_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PATT4_ATTSET4_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PATT4_ATTSET4_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PATT4_ATTWAIT4 ((u32)0x0000FF00) /* ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ +#define FSMC_PATT4_ATTWAIT4_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PATT4_ATTWAIT4_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PATT4_ATTWAIT4_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PATT4_ATTWAIT4_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PATT4_ATTWAIT4_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PATT4_ATTWAIT4_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PATT4_ATTWAIT4_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PATT4_ATTWAIT4_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PATT4_ATTHOLD4 ((u32)0x00FF0000) /* ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ +#define FSMC_PATT4_ATTHOLD4_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PATT4_ATTHOLD4_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PATT4_ATTHOLD4_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PATT4_ATTHOLD4_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PATT4_ATTHOLD4_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PATT4_ATTHOLD4_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PATT4_ATTHOLD4_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PATT4_ATTHOLD4_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PATT4_ATTHIZ4 ((u32)0xFF000000) /* ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ +#define FSMC_PATT4_ATTHIZ4_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PATT4_ATTHIZ4_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PATT4_ATTHIZ4_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PATT4_ATTHIZ4_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PATT4_ATTHIZ4_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PATT4_ATTHIZ4_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PATT4_ATTHIZ4_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PATT4_ATTHIZ4_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_PIO4 register *******************/ +#define FSMC_PIO4_IOSET4 ((u32)0x000000FF) /* IOSET4[7:0] bits (I/O 4 setup time) */ +#define FSMC_PIO4_IOSET4_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PIO4_IOSET4_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PIO4_IOSET4_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PIO4_IOSET4_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PIO4_IOSET4_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PIO4_IOSET4_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PIO4_IOSET4_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PIO4_IOSET4_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PIO4_IOWAIT4 ((u32)0x0000FF00) /* IOWAIT4[7:0] bits (I/O 4 wait time) */ +#define FSMC_PIO4_IOWAIT4_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PIO4_IOWAIT4_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PIO4_IOWAIT4_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PIO4_IOWAIT4_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PIO4_IOWAIT4_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PIO4_IOWAIT4_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PIO4_IOWAIT4_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PIO4_IOWAIT4_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PIO4_IOHOLD4 ((u32)0x00FF0000) /* IOHOLD4[7:0] bits (I/O 4 hold time) */ +#define FSMC_PIO4_IOHOLD4_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PIO4_IOHOLD4_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PIO4_IOHOLD4_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PIO4_IOHOLD4_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PIO4_IOHOLD4_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PIO4_IOHOLD4_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PIO4_IOHOLD4_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PIO4_IOHOLD4_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PIO4_IOHIZ4 ((u32)0xFF000000) /* IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ +#define FSMC_PIO4_IOHIZ4_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PIO4_IOHIZ4_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PIO4_IOHIZ4_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PIO4_IOHIZ4_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PIO4_IOHIZ4_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PIO4_IOHIZ4_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PIO4_IOHIZ4_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PIO4_IOHIZ4_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_ECCR2 register ******************/ +#define FSMC_ECCR2_ECC2 ((u32)0xFFFFFFFF) /* ECC result */ + +/****************** Bit definition for FSMC_ECCR3 register ******************/ +#define FSMC_ECCR3_ECC3 ((u32)0xFFFFFFFF) /* ECC result */ + + + +/******************************************************************************/ +/* */ +/* SD host Interface */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for SDIO_POWER register ******************/ +#define SDIO_POWER_PWRCTRL ((u8)0x03) /* PWRCTRL[1:0] bits (Power supply control bits) */ +#define SDIO_POWER_PWRCTRL_0 ((u8)0x01) /* Bit 0 */ +#define SDIO_POWER_PWRCTRL_1 ((u8)0x02) /* Bit 1 */ + + +/****************** Bit definition for SDIO_CLKCR register ******************/ +#define SDIO_CLKCR_CLKDIV ((u16)0x00FF) /* Clock divide factor */ +#define SDIO_CLKCR_CLKEN ((u16)0x0100) /* Clock enable bit */ +#define SDIO_CLKCR_PWRSAV ((u16)0x0200) /* Power saving configuration bit */ +#define SDIO_CLKCR_BYPASS ((u16)0x0400) /* Clock divider bypass enable bit */ + +#define SDIO_CLKCR_WIDBUS ((u16)0x1800) /* WIDBUS[1:0] bits (Wide bus mode enable bit) */ +#define SDIO_CLKCR_WIDBUS_0 ((u16)0x0800) /* Bit 0 */ +#define SDIO_CLKCR_WIDBUS_1 ((u16)0x1000) /* Bit 1 */ + +#define SDIO_CLKCR_NEGEDGE ((u16)0x2000) /* SDIO_CK dephasing selection bit */ +#define SDIO_CLKCR_HWFC_EN ((u16)0x4000) /* HW Flow Control enable */ + + +/******************* Bit definition for SDIO_ARG register *******************/ +#define SDIO_ARG_CMDARG ((u32)0xFFFFFFFF) /* Command argument */ + + +/******************* Bit definition for SDIO_CMD register *******************/ +#define SDIO_CMD_CMDINDEX ((u16)0x003F) /* Command Index */ + +#define SDIO_CMD_WAITRESP ((u16)0x00C0) /* WAITRESP[1:0] bits (Wait for response bits) */ +#define SDIO_CMD_WAITRESP_0 ((u16)0x0040) /* Bit 0 */ +#define SDIO_CMD_WAITRESP_1 ((u16)0x0080) /* Bit 1 */ + +#define SDIO_CMD_WAITINT ((u16)0x0100) /* CPSM Waits for Interrupt Request */ +#define SDIO_CMD_WAITPEND ((u16)0x0200) /* CPSM Waits for ends of data transfer (CmdPend internal signal) */ +#define SDIO_CMD_CPSMEN ((u16)0x0400) /* Command path state machine (CPSM) Enable bit */ +#define SDIO_CMD_SDIOSUSPEND ((u16)0x0800) /* SD I/O suspend command */ +#define SDIO_CMD_ENCMDCOMPL ((u16)0x1000) /* Enable CMD completion */ +#define SDIO_CMD_NIEN ((u16)0x2000) /* Not Interrupt Enable */ +#define SDIO_CMD_CEATACMD ((u16)0x4000) /* CE-ATA command */ + + +/***************** Bit definition for SDIO_RESPCMD register *****************/ +#define SDIO_RESPCMD_RESPCMD ((u8)0x3F) /* Response command index */ + + +/****************** Bit definition for SDIO_RESP0 register ******************/ +#define SDIO_RESP0_CARDSTATUS0 ((u32)0xFFFFFFFF) /* Card Status */ + + +/****************** Bit definition for SDIO_RESP1 register ******************/ +#define SDIO_RESP1_CARDSTATUS1 ((u32)0xFFFFFFFF) /* Card Status */ + + +/****************** Bit definition for SDIO_RESP2 register ******************/ +#define SDIO_RESP2_CARDSTATUS2 ((u32)0xFFFFFFFF) /* Card Status */ + + +/****************** Bit definition for SDIO_RESP3 register ******************/ +#define SDIO_RESP3_CARDSTATUS3 ((u32)0xFFFFFFFF) /* Card Status */ + + +/****************** Bit definition for SDIO_RESP4 register ******************/ +#define SDIO_RESP4_CARDSTATUS4 ((u32)0xFFFFFFFF) /* Card Status */ + + +/****************** Bit definition for SDIO_DTIMER register *****************/ +#define SDIO_DTIMER_DATATIME ((u32)0xFFFFFFFF) /* Data timeout period. */ + + +/****************** Bit definition for SDIO_DLEN register *******************/ +#define SDIO_DLEN_DATALENGTH ((u32)0x01FFFFFF) /* Data length value */ + + +/****************** Bit definition for SDIO_DCTRL register ******************/ +#define SDIO_DCTRL_DTEN ((u16)0x0001) /* Data transfer enabled bit */ +#define SDIO_DCTRL_DTDIR ((u16)0x0002) /* Data transfer direction selection */ +#define SDIO_DCTRL_DTMODE ((u16)0x0004) /* Data transfer mode selection */ +#define SDIO_DCTRL_DMAEN ((u16)0x0008) /* DMA enabled bit */ + +#define SDIO_DCTRL_DBLOCKSIZE ((u16)0x00F0) /* DBLOCKSIZE[3:0] bits (Data block size) */ +#define SDIO_DCTRL_DBLOCKSIZE_0 ((u16)0x0010) /* Bit 0 */ +#define SDIO_DCTRL_DBLOCKSIZE_1 ((u16)0x0020) /* Bit 1 */ +#define SDIO_DCTRL_DBLOCKSIZE_2 ((u16)0x0040) /* Bit 2 */ +#define SDIO_DCTRL_DBLOCKSIZE_3 ((u16)0x0080) /* Bit 3 */ + +#define SDIO_DCTRL_RWSTART ((u16)0x0100) /* Read wait start */ +#define SDIO_DCTRL_RWSTOP ((u16)0x0200) /* Read wait stop */ +#define SDIO_DCTRL_RWMOD ((u16)0x0400) /* Read wait mode */ +#define SDIO_DCTRL_SDIOEN ((u16)0x0800) /* SD I/O enable functions */ + + +/****************** Bit definition for SDIO_DCOUNT register *****************/ +#define SDIO_DCOUNT_DATACOUNT ((u32)0x01FFFFFF) /* Data count value */ + + +/****************** Bit definition for SDIO_STA register ********************/ +#define SDIO_STA_CCRCFAIL ((u32)0x00000001) /* Command response received (CRC check failed) */ +#define SDIO_STA_DCRCFAIL ((u32)0x00000002) /* Data block sent/received (CRC check failed) */ +#define SDIO_STA_CTIMEOUT ((u32)0x00000004) /* Command response timeout */ +#define SDIO_STA_DTIMEOUT ((u32)0x00000008) /* Data timeout */ +#define SDIO_STA_TXUNDERR ((u32)0x00000010) /* Transmit FIFO underrun error */ +#define SDIO_STA_RXOVERR ((u32)0x00000020) /* Received FIFO overrun error */ +#define SDIO_STA_CMDREND ((u32)0x00000040) /* Command response received (CRC check passed) */ +#define SDIO_STA_CMDSENT ((u32)0x00000080) /* Command sent (no response required) */ +#define SDIO_STA_DATAEND ((u32)0x00000100) /* Data end (data counter, SDIDCOUNT, is zero) */ +#define SDIO_STA_STBITERR ((u32)0x00000200) /* Start bit not detected on all data signals in wide bus mode */ +#define SDIO_STA_DBCKEND ((u32)0x00000400) /* Data block sent/received (CRC check passed) */ +#define SDIO_STA_CMDACT ((u32)0x00000800) /* Command transfer in progress */ +#define SDIO_STA_TXACT ((u32)0x00001000) /* Data transmit in progress */ +#define SDIO_STA_RXACT ((u32)0x00002000) /* Data receive in progress */ +#define SDIO_STA_TXFIFOHE ((u32)0x00004000) /* Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ +#define SDIO_STA_RXFIFOHF ((u32)0x00008000) /* Receive FIFO Half Full: there are at least 8 words in the FIFO */ +#define SDIO_STA_TXFIFOF ((u32)0x00010000) /* Transmit FIFO full */ +#define SDIO_STA_RXFIFOF ((u32)0x00020000) /* Receive FIFO full */ +#define SDIO_STA_TXFIFOE ((u32)0x00040000) /* Transmit FIFO empty */ +#define SDIO_STA_RXFIFOE ((u32)0x00080000) /* Receive FIFO empty */ +#define SDIO_STA_TXDAVL ((u32)0x00100000) /* Data available in transmit FIFO */ +#define SDIO_STA_RXDAVL ((u32)0x00200000) /* Data available in receive FIFO */ +#define SDIO_STA_SDIOIT ((u32)0x00400000) /* SDIO interrupt received */ +#define SDIO_STA_CEATAEND ((u32)0x00800000) /* CE-ATA command completion signal received for CMD61 */ + + +/******************* Bit definition for SDIO_ICR register *******************/ +#define SDIO_ICR_CCRCFAILC ((u32)0x00000001) /* CCRCFAIL flag clear bit */ +#define SDIO_ICR_DCRCFAILC ((u32)0x00000002) /* DCRCFAIL flag clear bit */ +#define SDIO_ICR_CTIMEOUTC ((u32)0x00000004) /* CTIMEOUT flag clear bit */ +#define SDIO_ICR_DTIMEOUTC ((u32)0x00000008) /* DTIMEOUT flag clear bit */ +#define SDIO_ICR_TXUNDERRC ((u32)0x00000010) /* TXUNDERR flag clear bit */ +#define SDIO_ICR_RXOVERRC ((u32)0x00000020) /* RXOVERR flag clear bit */ +#define SDIO_ICR_CMDRENDC ((u32)0x00000040) /* CMDREND flag clear bit */ +#define SDIO_ICR_CMDSENTC ((u32)0x00000080) /* CMDSENT flag clear bit */ +#define SDIO_ICR_DATAENDC ((u32)0x00000100) /* DATAEND flag clear bit */ +#define SDIO_ICR_STBITERRC ((u32)0x00000200) /* STBITERR flag clear bit */ +#define SDIO_ICR_DBCKENDC ((u32)0x00000400) /* DBCKEND flag clear bit */ +#define SDIO_ICR_SDIOITC ((u32)0x00400000) /* SDIOIT flag clear bit */ +#define SDIO_ICR_CEATAENDC ((u32)0x00800000) /* CEATAEND flag clear bit */ + + +/****************** Bit definition for SDIO_MASK register *******************/ +#define SDIO_MASK_CCRCFAILIE ((u32)0x00000001) /* Command CRC Fail Interrupt Enable */ +#define SDIO_MASK_DCRCFAILIE ((u32)0x00000002) /* Data CRC Fail Interrupt Enable */ +#define SDIO_MASK_CTIMEOUTIE ((u32)0x00000004) /* Command TimeOut Interrupt Enable */ +#define SDIO_MASK_DTIMEOUTIE ((u32)0x00000008) /* Data TimeOut Interrupt Enable */ +#define SDIO_MASK_TXUNDERRIE ((u32)0x00000010) /* Tx FIFO UnderRun Error Interrupt Enable */ +#define SDIO_MASK_RXOVERRIE ((u32)0x00000020) /* Rx FIFO OverRun Error Interrupt Enable */ +#define SDIO_MASK_CMDRENDIE ((u32)0x00000040) /* Command Response Received Interrupt Enable */ +#define SDIO_MASK_CMDSENTIE ((u32)0x00000080) /* Command Sent Interrupt Enable */ +#define SDIO_MASK_DATAENDIE ((u32)0x00000100) /* Data End Interrupt Enable */ +#define SDIO_MASK_STBITERRIE ((u32)0x00000200) /* Start Bit Error Interrupt Enable */ +#define SDIO_MASK_DBCKENDIE ((u32)0x00000400) /* Data Block End Interrupt Enable */ +#define SDIO_MASK_CMDACTIE ((u32)0x00000800) /* CCommand Acting Interrupt Enable */ +#define SDIO_MASK_TXACTIE ((u32)0x00001000) /* Data Transmit Acting Interrupt Enable */ +#define SDIO_MASK_RXACTIE ((u32)0x00002000) /* Data receive acting interrupt enabled */ +#define SDIO_MASK_TXFIFOHEIE ((u32)0x00004000) /* Tx FIFO Half Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOHFIE ((u32)0x00008000) /* Rx FIFO Half Full interrupt Enable */ +#define SDIO_MASK_TXFIFOFIE ((u32)0x00010000) /* Tx FIFO Full interrupt Enable */ +#define SDIO_MASK_RXFIFOFIE ((u32)0x00020000) /* Rx FIFO Full interrupt Enable */ +#define SDIO_MASK_TXFIFOEIE ((u32)0x00040000) /* Tx FIFO Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOEIE ((u32)0x00080000) /* Rx FIFO Empty interrupt Enable */ +#define SDIO_MASK_TXDAVLIE ((u32)0x00100000) /* Data available in Tx FIFO interrupt Enable */ +#define SDIO_MASK_RXDAVLIE ((u32)0x00200000) /* Data available in Rx FIFO interrupt Enable */ +#define SDIO_MASK_SDIOITIE ((u32)0x00400000) /* SDIO Mode Interrupt Received interrupt Enable */ +#define SDIO_MASK_CEATAENDIE ((u32)0x00800000) /* CE-ATA command completion signal received Interrupt Enable */ + + +/***************** Bit definition for SDIO_FIFOCNT register *****************/ +#define SDIO_FIFOCNT_FIFOCOUNT ((u32)0x00FFFFFF) /* Remaining number of words to be written to or read from the FIFO */ + + +/****************** Bit definition for SDIO_FIFO register *******************/ +#define SDIO_FIFO_FIFODATA ((u32)0xFFFFFFFF) /* Receive and transmit FIFO data */ + + + +/******************************************************************************/ +/* */ +/* USB */ +/* */ +/******************************************************************************/ + +/* Endpoint-specific registers */ +/******************* Bit definition for USB_EP0R register *******************/ +#define USB_EP0R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP0R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP0R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP0R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP0R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP0R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP0R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP0R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP0R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP0R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP0R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP0R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP0R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP0R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP0R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP0R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP1R register *******************/ +#define USB_EP1R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP1R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP1R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP1R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP1R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP1R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP1R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP1R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP1R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP1R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP1R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP1R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP1R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP1R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP1R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP1R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP2R register *******************/ +#define USB_EP2R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP2R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP2R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP2R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP2R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP2R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP2R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP2R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP2R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP2R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP2R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP2R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP2R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP2R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP2R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP2R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP3R register *******************/ +#define USB_EP3R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP3R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP3R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP3R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP3R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP3R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP3R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP3R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP3R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP3R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP3R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP3R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP3R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP3R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP3R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP3R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP4R register *******************/ +#define USB_EP4R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP4R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP4R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP4R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP4R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP4R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP4R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP4R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP4R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP4R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP4R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP4R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP4R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP4R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP4R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP4R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP5R register *******************/ +#define USB_EP5R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP5R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP5R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP5R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP5R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP5R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP5R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP5R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP5R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP5R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP5R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP5R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP5R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP5R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP5R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP5R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP6R register *******************/ +#define USB_EP6R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP6R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP6R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP6R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP6R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP6R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP6R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP6R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP6R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP6R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP6R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP6R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP6R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP6R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP6R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP6R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP7R register *******************/ +#define USB_EP7R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP7R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP7R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP7R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP7R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP7R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP7R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP7R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP7R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP7R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP7R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP7R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP7R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP7R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP7R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP7R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/* Common registers */ +/******************* Bit definition for USB_CNTR register *******************/ +#define USB_CNTR_FRES ((u16)0x0001) /* Force USB Reset */ +#define USB_CNTR_PDWN ((u16)0x0002) /* Power down */ +#define USB_CNTR_LP_MODE ((u16)0x0004) /* Low-power mode */ +#define USB_CNTR_FSUSP ((u16)0x0008) /* Force suspend */ +#define USB_CNTR_RESUME ((u16)0x0010) /* Resume request */ +#define USB_CNTR_ESOFM ((u16)0x0100) /* Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM ((u16)0x0200) /* Start Of Frame Interrupt Mask */ +#define USB_CNTR_RESETM ((u16)0x0400) /* RESET Interrupt Mask */ +#define USB_CNTR_SUSPM ((u16)0x0800) /* Suspend mode Interrupt Mask */ +#define USB_CNTR_WKUPM ((u16)0x1000) /* Wakeup Interrupt Mask */ +#define USB_CNTR_ERRM ((u16)0x2000) /* Error Interrupt Mask */ +#define USB_CNTR_PMAOVRM ((u16)0x4000) /* Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CNTR_CTRM ((u16)0x8000) /* Correct Transfer Interrupt Mask */ + + +/******************* Bit definition for USB_ISTR register *******************/ +#define USB_ISTR_EP_ID ((u16)0x000F) /* Endpoint Identifier */ +#define USB_ISTR_DIR ((u16)0x0010) /* Direction of transaction */ +#define USB_ISTR_ESOF ((u16)0x0100) /* Expected Start Of Frame */ +#define USB_ISTR_SOF ((u16)0x0200) /* Start Of Frame */ +#define USB_ISTR_RESET ((u16)0x0400) /* USB RESET request */ +#define USB_ISTR_SUSP ((u16)0x0800) /* Suspend mode request */ +#define USB_ISTR_WKUP ((u16)0x1000) /* Wake up */ +#define USB_ISTR_ERR ((u16)0x2000) /* Error */ +#define USB_ISTR_PMAOVR ((u16)0x4000) /* Packet Memory Area Over / Underrun */ +#define USB_ISTR_CTR ((u16)0x8000) /* Correct Transfer */ + + +/******************* Bit definition for USB_FNR register ********************/ +#define USB_FNR_FN ((u16)0x07FF) /* Frame Number */ +#define USB_FNR_LSOF ((u16)0x1800) /* Lost SOF */ +#define USB_FNR_LCK ((u16)0x2000) /* Locked */ +#define USB_FNR_RXDM ((u16)0x4000) /* Receive Data - Line Status */ +#define USB_FNR_RXDP ((u16)0x8000) /* Receive Data + Line Status */ + + +/****************** Bit definition for USB_DADDR register *******************/ +#define USB_DADDR_ADD ((u8)0x7F) /* ADD[6:0] bits (Device Address) */ +#define USB_DADDR_ADD0 ((u8)0x01) /* Bit 0 */ +#define USB_DADDR_ADD1 ((u8)0x02) /* Bit 1 */ +#define USB_DADDR_ADD2 ((u8)0x04) /* Bit 2 */ +#define USB_DADDR_ADD3 ((u8)0x08) /* Bit 3 */ +#define USB_DADDR_ADD4 ((u8)0x10) /* Bit 4 */ +#define USB_DADDR_ADD5 ((u8)0x20) /* Bit 5 */ +#define USB_DADDR_ADD6 ((u8)0x40) /* Bit 6 */ + +#define USB_DADDR_EF ((u8)0x80) /* Enable Function */ + + +/****************** Bit definition for USB_BTABLE register ******************/ +#define USB_BTABLE_BTABLE ((u16)0xFFF8) /* Buffer Table */ + + +/* Buffer descriptor table */ +/***************** Bit definition for USB_ADDR0_TX register *****************/ +#define USB_ADDR0_TX_ADDR0_TX ((u16)0xFFFE) /* Transmission Buffer Address 0 */ + + +/***************** Bit definition for USB_ADDR1_TX register *****************/ +#define USB_ADDR1_TX_ADDR1_TX ((u16)0xFFFE) /* Transmission Buffer Address 1 */ + + +/***************** Bit definition for USB_ADDR2_TX register *****************/ +#define USB_ADDR2_TX_ADDR2_TX ((u16)0xFFFE) /* Transmission Buffer Address 2 */ + + +/***************** Bit definition for USB_ADDR3_TX register *****************/ +#define USB_ADDR3_TX_ADDR3_TX ((u16)0xFFFE) /* Transmission Buffer Address 3 */ + + +/***************** Bit definition for USB_ADDR4_TX register *****************/ +#define USB_ADDR4_TX_ADDR4_TX ((u16)0xFFFE) /* Transmission Buffer Address 4 */ + + +/***************** Bit definition for USB_ADDR5_TX register *****************/ +#define USB_ADDR5_TX_ADDR5_TX ((u16)0xFFFE) /* Transmission Buffer Address 5 */ + + +/***************** Bit definition for USB_ADDR6_TX register *****************/ +#define USB_ADDR6_TX_ADDR6_TX ((u16)0xFFFE) /* Transmission Buffer Address 6 */ + + +/***************** Bit definition for USB_ADDR7_TX register *****************/ +#define USB_ADDR7_TX_ADDR7_TX ((u16)0xFFFE) /* Transmission Buffer Address 7 */ + + +/*----------------------------------------------------------------------------*/ + + +/***************** Bit definition for USB_COUNT0_TX register ****************/ +#define USB_COUNT0_TX_COUNT0_TX ((u16)0x03FF) /* Transmission Byte Count 0 */ + + +/***************** Bit definition for USB_COUNT1_TX register ****************/ +#define USB_COUNT1_TX_COUNT1_TX ((u16)0x03FF) /* Transmission Byte Count 1 */ + + +/***************** Bit definition for USB_COUNT2_TX register ****************/ +#define USB_COUNT2_TX_COUNT2_TX ((u16)0x03FF) /* Transmission Byte Count 2 */ + + +/***************** Bit definition for USB_COUNT3_TX register ****************/ +#define USB_COUNT3_TX_COUNT3_TX ((u16)0x03FF) /* Transmission Byte Count 3 */ + + +/***************** Bit definition for USB_COUNT4_TX register ****************/ +#define USB_COUNT4_TX_COUNT4_TX ((u16)0x03FF) /* Transmission Byte Count 4 */ + +/***************** Bit definition for USB_COUNT5_TX register ****************/ +#define USB_COUNT5_TX_COUNT5_TX ((u16)0x03FF) /* Transmission Byte Count 5 */ + + +/***************** Bit definition for USB_COUNT6_TX register ****************/ +#define USB_COUNT6_TX_COUNT6_TX ((u16)0x03FF) /* Transmission Byte Count 6 */ + + +/***************** Bit definition for USB_COUNT7_TX register ****************/ +#define USB_COUNT7_TX_COUNT7_TX ((u16)0x03FF) /* Transmission Byte Count 7 */ + + +/*----------------------------------------------------------------------------*/ + + +/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ +#define USB_COUNT0_TX_0_COUNT0_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 0 (low) */ + +/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ +#define USB_COUNT0_TX_1_COUNT0_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 0 (high) */ + + + +/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ +#define USB_COUNT1_TX_0_COUNT1_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 1 (low) */ + +/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ +#define USB_COUNT1_TX_1_COUNT1_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 1 (high) */ + + + +/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ +#define USB_COUNT2_TX_0_COUNT2_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 2 (low) */ + +/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ +#define USB_COUNT2_TX_1_COUNT2_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 2 (high) */ + + + +/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ +#define USB_COUNT3_TX_0_COUNT3_TX_0 ((u16)0x000003FF) /* Transmission Byte Count 3 (low) */ + +/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ +#define USB_COUNT3_TX_1_COUNT3_TX_1 ((u16)0x03FF0000) /* Transmission Byte Count 3 (high) */ + + + +/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ +#define USB_COUNT4_TX_0_COUNT4_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 4 (low) */ + +/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ +#define USB_COUNT4_TX_1_COUNT4_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 4 (high) */ + + + +/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ +#define USB_COUNT5_TX_0_COUNT5_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 5 (low) */ + +/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ +#define USB_COUNT5_TX_1_COUNT5_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 5 (high) */ + + + +/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ +#define USB_COUNT6_TX_0_COUNT6_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 6 (low) */ + +/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ +#define USB_COUNT6_TX_1_COUNT6_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 6 (high) */ + + + +/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ +#define USB_COUNT7_TX_0_COUNT7_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 7 (low) */ + +/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ +#define USB_COUNT7_TX_1_COUNT7_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 7 (high) */ + + +/*----------------------------------------------------------------------------*/ + + +/***************** Bit definition for USB_ADDR0_RX register *****************/ +#define USB_ADDR0_RX_ADDR0_RX ((u16)0xFFFE) /* Reception Buffer Address 0 */ + + +/***************** Bit definition for USB_ADDR1_RX register *****************/ +#define USB_ADDR1_RX_ADDR1_RX ((u16)0xFFFE) /* Reception Buffer Address 1 */ + + +/***************** Bit definition for USB_ADDR2_RX register *****************/ +#define USB_ADDR2_RX_ADDR2_RX ((u16)0xFFFE) /* Reception Buffer Address 2 */ + + +/***************** Bit definition for USB_ADDR3_RX register *****************/ +#define USB_ADDR3_RX_ADDR3_RX ((u16)0xFFFE) /* Reception Buffer Address 3 */ + + +/***************** Bit definition for USB_ADDR4_RX register *****************/ +#define USB_ADDR4_RX_ADDR4_RX ((u16)0xFFFE) /* Reception Buffer Address 4 */ + + +/***************** Bit definition for USB_ADDR5_RX register *****************/ +#define USB_ADDR5_RX_ADDR5_RX ((u16)0xFFFE) /* Reception Buffer Address 5 */ + + +/***************** Bit definition for USB_ADDR6_RX register *****************/ +#define USB_ADDR6_RX_ADDR6_RX ((u16)0xFFFE) /* Reception Buffer Address 6 */ + + +/***************** Bit definition for USB_ADDR7_RX register *****************/ +#define USB_ADDR7_RX_ADDR7_RX ((u16)0xFFFE) /* Reception Buffer Address 7 */ + + +/*----------------------------------------------------------------------------*/ + + +/***************** Bit definition for USB_COUNT0_RX register ****************/ +#define USB_COUNT0_RX_COUNT0_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT0_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT0_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT0_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT0_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT0_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT0_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT0_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/***************** Bit definition for USB_COUNT1_RX register ****************/ +#define USB_COUNT1_RX_COUNT1_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT1_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT1_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT1_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT1_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT1_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT1_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT1_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/***************** Bit definition for USB_COUNT2_RX register ****************/ +#define USB_COUNT2_RX_COUNT2_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT2_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT2_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT2_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT2_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT2_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT2_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT2_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/***************** Bit definition for USB_COUNT3_RX register ****************/ +#define USB_COUNT3_RX_COUNT3_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT3_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT3_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT3_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT3_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT3_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT3_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT3_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/***************** Bit definition for USB_COUNT4_RX register ****************/ +#define USB_COUNT4_RX_COUNT4_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT4_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT4_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT4_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT4_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT4_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT4_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT4_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/***************** Bit definition for USB_COUNT5_RX register ****************/ +#define USB_COUNT5_RX_COUNT5_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT5_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT5_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT5_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT5_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT5_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT5_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT5_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + +/***************** Bit definition for USB_COUNT6_RX register ****************/ +#define USB_COUNT6_RX_COUNT6_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT6_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT6_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT6_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT6_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT6_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT6_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT6_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/***************** Bit definition for USB_COUNT7_RX register ****************/ +#define USB_COUNT7_RX_COUNT7_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT7_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT7_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT7_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT7_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT7_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT7_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT7_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/*----------------------------------------------------------------------------*/ + + +/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ +#define USB_COUNT0_RX_0_COUNT0_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT0_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ +#define USB_COUNT0_RX_1_COUNT0_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT0_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ +#define USB_COUNT1_RX_0_COUNT1_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT1_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ +#define USB_COUNT1_RX_1_COUNT1_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT1_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ +#define USB_COUNT2_RX_0_COUNT2_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT2_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ +#define USB_COUNT2_RX_1_COUNT2_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT2_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ +#define USB_COUNT3_RX_0_COUNT3_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT3_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ +#define USB_COUNT3_RX_1_COUNT3_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT3_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ +#define USB_COUNT4_RX_0_COUNT4_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT4_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ +#define USB_COUNT4_RX_1_COUNT4_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT4_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ +#define USB_COUNT5_RX_0_COUNT5_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT5_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ +#define USB_COUNT5_RX_1_COUNT5_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT5_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ +#define USB_COUNT6_RX_0_COUNT6_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT6_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ +#define USB_COUNT6_RX_1_COUNT6_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT6_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ +#define USB_COUNT7_RX_0_COUNT7_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT7_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ +#define USB_COUNT7_RX_1_COUNT7_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT7_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/******************************************************************************/ +/* */ +/* Controller Area Network */ +/* */ +/******************************************************************************/ + +/* CAN control and status registers */ +/******************* Bit definition for CAN_MCR register ********************/ +#define CAN_MCR_INRQ ((u16)0x0001) /* Initialization Request */ +#define CAN_MCR_SLEEP ((u16)0x0002) /* Sleep Mode Request */ +#define CAN_MCR_TXFP ((u16)0x0004) /* Transmit FIFO Priority */ +#define CAN_MCR_RFLM ((u16)0x0008) /* Receive FIFO Locked Mode */ +#define CAN_MCR_NART ((u16)0x0010) /* No Automatic Retransmission */ +#define CAN_MCR_AWUM ((u16)0x0020) /* Automatic Wakeup Mode */ +#define CAN_MCR_ABOM ((u16)0x0040) /* Automatic Bus-Off Management */ +#define CAN_MCR_TTCM ((u16)0x0080) /* Time Triggered Communication Mode */ +#define CAN_MCR_RESET ((u16)0x8000) /* bxCAN software master reset */ + + +/******************* Bit definition for CAN_MSR register ********************/ +#define CAN_MSR_INAK ((u16)0x0001) /* Initialization Acknowledge */ +#define CAN_MSR_SLAK ((u16)0x0002) /* Sleep Acknowledge */ +#define CAN_MSR_ERRI ((u16)0x0004) /* Error Interrupt */ +#define CAN_MSR_WKUI ((u16)0x0008) /* Wakeup Interrupt */ +#define CAN_MSR_SLAKI ((u16)0x0010) /* Sleep Acknowledge Interrupt */ +#define CAN_MSR_TXM ((u16)0x0100) /* Transmit Mode */ +#define CAN_MSR_RXM ((u16)0x0200) /* Receive Mode */ +#define CAN_MSR_SAMP ((u16)0x0400) /* Last Sample Point */ +#define CAN_MSR_RX ((u16)0x0800) /* CAN Rx Signal */ + + +/******************* Bit definition for CAN_TSR register ********************/ +#define CAN_TSR_RQCP0 ((u32)0x00000001) /* Request Completed Mailbox0 */ +#define CAN_TSR_TXOK0 ((u32)0x00000002) /* Transmission OK of Mailbox0 */ +#define CAN_TSR_ALST0 ((u32)0x00000004) /* Arbitration Lost for Mailbox0 */ +#define CAN_TSR_TERR0 ((u32)0x00000008) /* Transmission Error of Mailbox0 */ +#define CAN_TSR_ABRQ0 ((u32)0x00000080) /* Abort Request for Mailbox0 */ +#define CAN_TSR_RQCP1 ((u32)0x00000100) /* Request Completed Mailbox1 */ +#define CAN_TSR_TXOK1 ((u32)0x00000200) /* Transmission OK of Mailbox1 */ +#define CAN_TSR_ALST1 ((u32)0x00000400) /* Arbitration Lost for Mailbox1 */ +#define CAN_TSR_TERR1 ((u32)0x00000800) /* Transmission Error of Mailbox1 */ +#define CAN_TSR_ABRQ1 ((u32)0x00008000) /* Abort Request for Mailbox 1 */ +#define CAN_TSR_RQCP2 ((u32)0x00010000) /* Request Completed Mailbox2 */ +#define CAN_TSR_TXOK2 ((u32)0x00020000) /* Transmission OK of Mailbox 2 */ +#define CAN_TSR_ALST2 ((u32)0x00040000) /* Arbitration Lost for mailbox 2 */ +#define CAN_TSR_TERR2 ((u32)0x00080000) /* Transmission Error of Mailbox 2 */ +#define CAN_TSR_ABRQ2 ((u32)0x00800000) /* Abort Request for Mailbox 2 */ +#define CAN_TSR_CODE ((u32)0x03000000) /* Mailbox Code */ + +#define CAN_TSR_TME ((u32)0x1C000000) /* TME[2:0] bits */ +#define CAN_TSR_TME0 ((u32)0x04000000) /* Transmit Mailbox 0 Empty */ +#define CAN_TSR_TME1 ((u32)0x08000000) /* Transmit Mailbox 1 Empty */ +#define CAN_TSR_TME2 ((u32)0x10000000) /* Transmit Mailbox 2 Empty */ + +#define CAN_TSR_LOW ((u32)0xE0000000) /* LOW[2:0] bits */ +#define CAN_TSR_LOW0 ((u32)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSR_LOW1 ((u32)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSR_LOW2 ((u32)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ + + +/******************* Bit definition for CAN_RF0R register *******************/ +#define CAN_RF0R_FMP0 ((u8)0x03) /* FIFO 0 Message Pending */ +#define CAN_RF0R_FULL0 ((u8)0x08) /* FIFO 0 Full */ +#define CAN_RF0R_FOVR0 ((u8)0x10) /* FIFO 0 Overrun */ +#define CAN_RF0R_RFOM0 ((u8)0x20) /* Release FIFO 0 Output Mailbox */ + + +/******************* Bit definition for CAN_RF1R register *******************/ +#define CAN_RF1R_FMP1 ((u8)0x03) /* FIFO 1 Message Pending */ +#define CAN_RF1R_FULL1 ((u8)0x08) /* FIFO 1 Full */ +#define CAN_RF1R_FOVR1 ((u8)0x10) /* FIFO 1 Overrun */ +#define CAN_RF1R_RFOM1 ((u8)0x20) /* Release FIFO 1 Output Mailbox */ + + +/******************** Bit definition for CAN_IER register *******************/ +#define CAN_IER_TMEIE ((u32)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ +#define CAN_IER_FMPIE0 ((u32)0x00000002) /* FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE0 ((u32)0x00000004) /* FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE0 ((u32)0x00000008) /* FIFO Overrun Interrupt Enable */ +#define CAN_IER_FMPIE1 ((u32)0x00000010) /* FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE1 ((u32)0x00000020) /* FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE1 ((u32)0x00000040) /* FIFO Overrun Interrupt Enable */ +#define CAN_IER_EWGIE ((u32)0x00000100) /* Error Warning Interrupt Enable */ +#define CAN_IER_EPVIE ((u32)0x00000200) /* Error Passive Interrupt Enable */ +#define CAN_IER_BOFIE ((u32)0x00000400) /* Bus-Off Interrupt Enable */ +#define CAN_IER_LECIE ((u32)0x00000800) /* Last Error Code Interrupt Enable */ +#define CAN_IER_ERRIE ((u32)0x00008000) /* Error Interrupt Enable */ +#define CAN_IER_WKUIE ((u32)0x00010000) /* Wakeup Interrupt Enable */ +#define CAN_IER_SLKIE ((u32)0x00020000) /* Sleep Interrupt Enable */ + + +/******************** Bit definition for CAN_ESR register *******************/ +#define CAN_ESR_EWGF ((u32)0x00000001) /* Error Warning Flag */ +#define CAN_ESR_EPVF ((u32)0x00000002) /* Error Passive Flag */ +#define CAN_ESR_BOFF ((u32)0x00000004) /* Bus-Off Flag */ + +#define CAN_ESR_LEC ((u32)0x00000070) /* LEC[2:0] bits (Last Error Code) */ +#define CAN_ESR_LEC_0 ((u32)0x00000010) /* Bit 0 */ +#define CAN_ESR_LEC_1 ((u32)0x00000020) /* Bit 1 */ +#define CAN_ESR_LEC_2 ((u32)0x00000040) /* Bit 2 */ + +#define CAN_ESR_TEC ((u32)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ESR_REC ((u32)0xFF000000) /* Receive Error Counter */ + + +/******************* Bit definition for CAN_BTR register ********************/ +#define CAN_BTR_BRP ((u32)0x000003FF) /* Baud Rate Prescaler */ +#define CAN_BTR_TS1 ((u32)0x000F0000) /* Time Segment 1 */ +#define CAN_BTR_TS2 ((u32)0x00700000) /* Time Segment 2 */ +#define CAN_BTR_SJW ((u32)0x03000000) /* Resynchronization Jump Width */ +#define CAN_BTR_LBKM ((u32)0x40000000) /* Loop Back Mode (Debug) */ +#define CAN_BTR_SILM ((u32)0x80000000) /* Silent Mode */ + + +/* Mailbox registers */ +/****************** Bit definition for CAN_TI0R register ********************/ +#define CAN_TI0R_TXRQ ((u32)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TI0R_RTR ((u32)0x00000002) /* Remote Transmission Request */ +#define CAN_TI0R_IDE ((u32)0x00000004) /* Identifier Extension */ +#define CAN_TI0R_EXID ((u32)0x001FFFF8) /* Extended Identifier */ +#define CAN_TI0R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */ + + +/****************** Bit definition for CAN_TDT0R register *******************/ +#define CAN_TDT0R_DLC ((u32)0x0000000F) /* Data Length Code */ +#define CAN_TDT0R_TGT ((u32)0x00000100) /* Transmit Global Time */ +#define CAN_TDT0R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */ + + +/****************** Bit definition for CAN_TDL0R register *******************/ +#define CAN_TDL0R_DATA0 ((u32)0x000000FF) /* Data byte 0 */ +#define CAN_TDL0R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */ +#define CAN_TDL0R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */ +#define CAN_TDL0R_DATA3 ((u32)0xFF000000) /* Data byte 3 */ + + +/****************** Bit definition for CAN_TDH0R register *******************/ +#define CAN_TDH0R_DATA4 ((u32)0x000000FF) /* Data byte 4 */ +#define CAN_TDH0R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */ +#define CAN_TDH0R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */ +#define CAN_TDH0R_DATA7 ((u32)0xFF000000) /* Data byte 7 */ + + +/******************* Bit definition for CAN_TI1R register *******************/ +#define CAN_TI1R_TXRQ ((u32)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TI1R_RTR ((u32)0x00000002) /* Remote Transmission Request */ +#define CAN_TI1R_IDE ((u32)0x00000004) /* Identifier Extension */ +#define CAN_TI1R_EXID ((u32)0x001FFFF8) /* Extended Identifier */ +#define CAN_TI1R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */ + + +/******************* Bit definition for CAN_TDT1R register ******************/ +#define CAN_TDT1R_DLC ((u32)0x0000000F) /* Data Length Code */ +#define CAN_TDT1R_TGT ((u32)0x00000100) /* Transmit Global Time */ +#define CAN_TDT1R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */ + + +/******************* Bit definition for CAN_TDL1R register ******************/ +#define CAN_TDL1R_DATA0 ((u32)0x000000FF) /* Data byte 0 */ +#define CAN_TDL1R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */ +#define CAN_TDL1R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */ +#define CAN_TDL1R_DATA3 ((u32)0xFF000000) /* Data byte 3 */ + + +/******************* Bit definition for CAN_TDH1R register ******************/ +#define CAN_TDH1R_DATA4 ((u32)0x000000FF) /* Data byte 4 */ +#define CAN_TDH1R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */ +#define CAN_TDH1R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */ +#define CAN_TDH1R_DATA7 ((u32)0xFF000000) /* Data byte 7 */ + + +/******************* Bit definition for CAN_TI2R register *******************/ +#define CAN_TI2R_TXRQ ((u32)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TI2R_RTR ((u32)0x00000002) /* Remote Transmission Request */ +#define CAN_TI2R_IDE ((u32)0x00000004) /* Identifier Extension */ +#define CAN_TI2R_EXID ((u32)0x001FFFF8) /* Extended identifier */ +#define CAN_TI2R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */ + + +/******************* Bit definition for CAN_TDT2R register ******************/ +#define CAN_TDT2R_DLC ((u32)0x0000000F) /* Data Length Code */ +#define CAN_TDT2R_TGT ((u32)0x00000100) /* Transmit Global Time */ +#define CAN_TDT2R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */ + + +/******************* Bit definition for CAN_TDL2R register ******************/ +#define CAN_TDL2R_DATA0 ((u32)0x000000FF) /* Data byte 0 */ +#define CAN_TDL2R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */ +#define CAN_TDL2R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */ +#define CAN_TDL2R_DATA3 ((u32)0xFF000000) /* Data byte 3 */ + + +/******************* Bit definition for CAN_TDH2R register ******************/ +#define CAN_TDH2R_DATA4 ((u32)0x000000FF) /* Data byte 4 */ +#define CAN_TDH2R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */ +#define CAN_TDH2R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */ +#define CAN_TDH2R_DATA7 ((u32)0xFF000000) /* Data byte 7 */ + + +/******************* Bit definition for CAN_RI0R register *******************/ +#define CAN_RI0R_RTR ((u32)0x00000002) /* Remote Transmission Request */ +#define CAN_RI0R_IDE ((u32)0x00000004) /* Identifier Extension */ +#define CAN_RI0R_EXID ((u32)0x001FFFF8) /* Extended Identifier */ +#define CAN_RI0R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */ + + +/******************* Bit definition for CAN_RDT0R register ******************/ +#define CAN_RDT0R_DLC ((u32)0x0000000F) /* Data Length Code */ +#define CAN_RDT0R_FMI ((u32)0x0000FF00) /* Filter Match Index */ +#define CAN_RDT0R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */ + + +/******************* Bit definition for CAN_RDL0R register ******************/ +#define CAN_RDL0R_DATA0 ((u32)0x000000FF) /* Data byte 0 */ +#define CAN_RDL0R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */ +#define CAN_RDL0R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */ +#define CAN_RDL0R_DATA3 ((u32)0xFF000000) /* Data byte 3 */ + + +/******************* Bit definition for CAN_RDH0R register ******************/ +#define CAN_RDH0R_DATA4 ((u32)0x000000FF) /* Data byte 4 */ +#define CAN_RDH0R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */ +#define CAN_RDH0R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */ +#define CAN_RDH0R_DATA7 ((u32)0xFF000000) /* Data byte 7 */ + + +/******************* Bit definition for CAN_RI1R register *******************/ +#define CAN_RI1R_RTR ((u32)0x00000002) /* Remote Transmission Request */ +#define CAN_RI1R_IDE ((u32)0x00000004) /* Identifier Extension */ +#define CAN_RI1R_EXID ((u32)0x001FFFF8) /* Extended identifier */ +#define CAN_RI1R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */ + + +/******************* Bit definition for CAN_RDT1R register ******************/ +#define CAN_RDT1R_DLC ((u32)0x0000000F) /* Data Length Code */ +#define CAN_RDT1R_FMI ((u32)0x0000FF00) /* Filter Match Index */ +#define CAN_RDT1R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */ + + +/******************* Bit definition for CAN_RDL1R register ******************/ +#define CAN_RDL1R_DATA0 ((u32)0x000000FF) /* Data byte 0 */ +#define CAN_RDL1R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */ +#define CAN_RDL1R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */ +#define CAN_RDL1R_DATA3 ((u32)0xFF000000) /* Data byte 3 */ + + +/******************* Bit definition for CAN_RDH1R register ******************/ +#define CAN_RDH1R_DATA4 ((u32)0x000000FF) /* Data byte 4 */ +#define CAN_RDH1R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */ +#define CAN_RDH1R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */ +#define CAN_RDH1R_DATA7 ((u32)0xFF000000) /* Data byte 7 */ + +/* CAN filter registers */ +/******************* Bit definition for CAN_FMR register ********************/ +#define CAN_FMR_FINIT ((u8)0x01) /* Filter Init Mode */ + + +/******************* Bit definition for CAN_FM1R register *******************/ +#define CAN_FM1R_FBM ((u16)0x3FFF) /* Filter Mode */ +#define CAN_FM1R_FBM0 ((u16)0x0001) /* Filter Init Mode bit 0 */ +#define CAN_FM1R_FBM1 ((u16)0x0002) /* Filter Init Mode bit 1 */ +#define CAN_FM1R_FBM2 ((u16)0x0004) /* Filter Init Mode bit 2 */ +#define CAN_FM1R_FBM3 ((u16)0x0008) /* Filter Init Mode bit 3 */ +#define CAN_FM1R_FBM4 ((u16)0x0010) /* Filter Init Mode bit 4 */ +#define CAN_FM1R_FBM5 ((u16)0x0020) /* Filter Init Mode bit 5 */ +#define CAN_FM1R_FBM6 ((u16)0x0040) /* Filter Init Mode bit 6 */ +#define CAN_FM1R_FBM7 ((u16)0x0080) /* Filter Init Mode bit 7 */ +#define CAN_FM1R_FBM8 ((u16)0x0100) /* Filter Init Mode bit 8 */ +#define CAN_FM1R_FBM9 ((u16)0x0200) /* Filter Init Mode bit 9 */ +#define CAN_FM1R_FBM10 ((u16)0x0400) /* Filter Init Mode bit 10 */ +#define CAN_FM1R_FBM11 ((u16)0x0800) /* Filter Init Mode bit 11 */ +#define CAN_FM1R_FBM12 ((u16)0x1000) /* Filter Init Mode bit 12 */ +#define CAN_FM1R_FBM13 ((u16)0x2000) /* Filter Init Mode bit 13 */ + + +/******************* Bit definition for CAN_FS1R register *******************/ +#define CAN_FS1R_FSC ((u16)0x3FFF) /* Filter Scale Configuration */ +#define CAN_FS1R_FSC0 ((u16)0x0001) /* Filter Scale Configuration bit 0 */ +#define CAN_FS1R_FSC1 ((u16)0x0002) /* Filter Scale Configuration bit 1 */ +#define CAN_FS1R_FSC2 ((u16)0x0004) /* Filter Scale Configuration bit 2 */ +#define CAN_FS1R_FSC3 ((u16)0x0008) /* Filter Scale Configuration bit 3 */ +#define CAN_FS1R_FSC4 ((u16)0x0010) /* Filter Scale Configuration bit 4 */ +#define CAN_FS1R_FSC5 ((u16)0x0020) /* Filter Scale Configuration bit 5 */ +#define CAN_FS1R_FSC6 ((u16)0x0040) /* Filter Scale Configuration bit 6 */ +#define CAN_FS1R_FSC7 ((u16)0x0080) /* Filter Scale Configuration bit 7 */ +#define CAN_FS1R_FSC8 ((u16)0x0100) /* Filter Scale Configuration bit 8 */ +#define CAN_FS1R_FSC9 ((u16)0x0200) /* Filter Scale Configuration bit 9 */ +#define CAN_FS1R_FSC10 ((u16)0x0400) /* Filter Scale Configuration bit 10 */ +#define CAN_FS1R_FSC11 ((u16)0x0800) /* Filter Scale Configuration bit 11 */ +#define CAN_FS1R_FSC12 ((u16)0x1000) /* Filter Scale Configuration bit 12 */ +#define CAN_FS1R_FSC13 ((u16)0x2000) /* Filter Scale Configuration bit 13 */ + + +/****************** Bit definition for CAN_FFA1R register *******************/ +#define CAN_FFA1R_FFA ((u16)0x3FFF) /* Filter FIFO Assignment */ +#define CAN_FFA1R_FFA0 ((u16)0x0001) /* Filter FIFO Assignment for Filter 0 */ +#define CAN_FFA1R_FFA1 ((u16)0x0002) /* Filter FIFO Assignment for Filter 1 */ +#define CAN_FFA1R_FFA2 ((u16)0x0004) /* Filter FIFO Assignment for Filter 2 */ +#define CAN_FFA1R_FFA3 ((u16)0x0008) /* Filter FIFO Assignment for Filter 3 */ +#define CAN_FFA1R_FFA4 ((u16)0x0010) /* Filter FIFO Assignment for Filter 4 */ +#define CAN_FFA1R_FFA5 ((u16)0x0020) /* Filter FIFO Assignment for Filter 5 */ +#define CAN_FFA1R_FFA6 ((u16)0x0040) /* Filter FIFO Assignment for Filter 6 */ +#define CAN_FFA1R_FFA7 ((u16)0x0080) /* Filter FIFO Assignment for Filter 7 */ +#define CAN_FFA1R_FFA8 ((u16)0x0100) /* Filter FIFO Assignment for Filter 8 */ +#define CAN_FFA1R_FFA9 ((u16)0x0200) /* Filter FIFO Assignment for Filter 9 */ +#define CAN_FFA1R_FFA10 ((u16)0x0400) /* Filter FIFO Assignment for Filter 10 */ +#define CAN_FFA1R_FFA11 ((u16)0x0800) /* Filter FIFO Assignment for Filter 11 */ +#define CAN_FFA1R_FFA12 ((u16)0x1000) /* Filter FIFO Assignment for Filter 12 */ +#define CAN_FFA1R_FFA13 ((u16)0x2000) /* Filter FIFO Assignment for Filter 13 */ + + +/******************* Bit definition for CAN_FA1R register *******************/ +#define CAN_FA1R_FACT ((u16)0x3FFF) /* Filter Active */ +#define CAN_FA1R_FACT0 ((u16)0x0001) /* Filter 0 Active */ +#define CAN_FA1R_FACT1 ((u16)0x0002) /* Filter 1 Active */ +#define CAN_FA1R_FACT2 ((u16)0x0004) /* Filter 2 Active */ +#define CAN_FA1R_FACT3 ((u16)0x0008) /* Filter 3 Active */ +#define CAN_FA1R_FACT4 ((u16)0x0010) /* Filter 4 Active */ +#define CAN_FA1R_FACT5 ((u16)0x0020) /* Filter 5 Active */ +#define CAN_FA1R_FACT6 ((u16)0x0040) /* Filter 6 Active */ +#define CAN_FA1R_FACT7 ((u16)0x0080) /* Filter 7 Active */ +#define CAN_FA1R_FACT8 ((u16)0x0100) /* Filter 8 Active */ +#define CAN_FA1R_FACT9 ((u16)0x0200) /* Filter 9 Active */ +#define CAN_FA1R_FACT10 ((u16)0x0400) /* Filter 10 Active */ +#define CAN_FA1R_FACT11 ((u16)0x0800) /* Filter 11 Active */ +#define CAN_FA1R_FACT12 ((u16)0x1000) /* Filter 12 Active */ +#define CAN_FA1R_FACT13 ((u16)0x2000) /* Filter 13 Active */ + + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F0R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F0R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F0R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F0R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F0R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F0R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F0R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F0R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F0R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F0R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F0R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F0R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F0R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F0R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F0R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F0R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F0R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F0R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F0R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F0R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F0R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F0R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F0R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F0R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F0R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F0R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F0R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F0R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F0R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F0R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F0R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F1R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F1R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F1R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F1R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F1R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F1R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F1R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F1R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F1R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F1R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F1R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F1R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F1R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F1R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F1R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F1R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F1R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F1R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F1R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F1R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F1R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F1R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F1R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F1R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F1R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F1R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F1R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F1R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F1R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F1R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F1R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F2R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F2R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F2R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F2R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F2R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F2R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F2R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F2R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F2R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F2R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F2R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F2R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F2R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F2R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F2R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F2R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F2R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F2R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F2R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F2R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F2R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F2R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F2R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F2R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F2R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F2R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F2R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F2R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F2R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F2R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F2R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F3R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F3R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F3R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F3R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F3R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F3R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F3R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F3R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F3R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F3R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F3R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F3R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F3R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F3R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F3R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F3R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F3R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F3R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F3R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F3R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F3R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F3R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F3R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F3R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F3R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F3R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F3R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F3R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F3R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F3R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F3R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F4R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F4R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F4R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F4R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F4R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F4R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F4R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F4R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F4R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F4R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F4R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F4R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F4R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F4R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F4R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F4R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F4R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F4R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F4R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F4R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F4R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F4R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F4R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F4R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F4R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F4R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F4R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F4R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F4R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F4R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F4R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F5R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F5R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F5R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F5R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F5R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F5R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F5R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F5R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F5R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F5R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F5R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F5R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F5R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F5R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F5R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F5R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F5R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F5R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F5R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F5R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F5R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F5R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F5R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F5R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F5R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F5R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F5R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F5R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F5R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F5R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F5R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F6R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F6R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F6R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F6R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F6R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F6R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F6R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F6R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F6R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F6R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F6R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F6R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F6R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F6R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F6R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F6R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F6R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F6R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F6R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F6R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F6R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F6R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F6R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F6R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F6R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F6R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F6R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F6R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F6R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F6R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F6R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F7R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F7R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F7R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F7R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F7R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F7R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F7R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F7R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F7R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F7R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F7R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F7R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F7R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F7R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F7R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F7R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F7R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F7R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F7R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F7R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F7R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F7R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F7R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F7R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F7R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F7R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F7R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F7R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F7R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F7R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F7R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F8R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F8R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F8R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F8R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F8R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F8R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F8R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F8R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F8R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F8R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F8R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F8R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F8R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F8R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F8R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F8R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F8R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F8R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F8R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F8R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F8R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F8R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F8R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F8R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F8R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F8R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F8R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F8R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F8R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F8R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F8R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F9R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F9R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F9R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F9R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F9R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F9R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F9R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F9R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F9R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F9R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F9R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F9R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F9R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F9R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F9R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F9R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F9R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F9R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F9R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F9R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F9R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F9R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F9R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F9R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F9R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F9R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F9R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F9R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F9R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F9R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F9R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F10R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F10R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F10R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F10R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F10R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F10R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F10R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F10R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F10R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F10R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F10R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F10R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F10R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F10R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F10R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F10R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F10R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F10R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F10R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F10R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F10R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F10R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F10R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F10R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F10R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F10R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F10R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F10R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F10R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F10R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F10R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F11R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F11R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F11R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F11R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F11R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F11R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F11R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F11R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F11R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F11R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F11R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F11R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F11R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F11R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F11R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F11R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F11R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F11R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F11R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F11R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F11R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F11R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F11R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F11R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F11R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F11R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F11R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F11R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F11R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F11R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F11R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F12R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F12R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F12R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F12R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F12R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F12R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F12R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F12R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F12R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F12R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F12R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F12R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F12R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F12R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F12R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F12R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F12R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F12R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F12R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F12R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F12R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F12R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F12R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F12R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F12R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F12R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F12R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F12R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F12R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F12R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F12R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F13R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F13R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F13R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F13R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F13R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F13R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F13R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F13R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F13R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F13R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F13R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F13R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F13R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F13R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F13R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F13R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F13R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F13R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F13R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F13R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F13R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F13R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F13R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F13R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F13R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F13R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F13R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F13R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F13R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F13R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F13R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F0R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F0R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F0R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F0R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F0R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F0R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F0R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F0R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F0R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F0R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F0R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F0R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F0R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F0R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F0R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F0R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F0R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F0R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F0R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F0R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F0R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F0R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F0R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F0R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F0R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F0R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F0R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F0R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F0R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F0R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F0R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F1R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F1R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F1R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F1R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F1R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F1R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F1R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F1R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F1R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F1R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F1R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F1R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F1R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F1R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F1R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F1R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F1R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F1R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F1R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F1R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F1R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F1R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F1R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F1R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F1R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F1R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F1R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F1R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F1R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F1R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F1R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F2R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F2R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F2R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F2R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F2R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F2R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F2R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F2R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F2R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F2R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F2R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F2R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F2R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F2R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F2R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F2R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F2R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F2R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F2R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F2R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F2R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F2R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F2R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F2R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F2R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F2R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F2R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F2R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F2R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F2R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F2R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F3R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F3R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F3R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F3R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F3R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F3R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F3R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F3R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F3R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F3R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F3R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F3R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F3R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F3R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F3R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F3R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F3R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F3R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F3R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F3R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F3R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F3R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F3R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F3R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F3R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F3R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F3R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F3R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F3R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F3R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F3R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F4R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F4R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F4R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F4R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F4R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F4R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F4R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F4R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F4R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F4R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F4R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F4R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F4R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F4R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F4R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F4R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F4R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F4R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F4R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F4R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F4R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F4R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F4R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F4R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F4R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F4R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F4R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F4R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F4R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F4R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F4R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F5R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F5R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F5R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F5R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F5R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F5R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F5R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F5R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F5R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F5R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F5R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F5R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F5R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F5R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F5R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F5R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F5R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F5R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F5R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F5R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F5R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F5R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F5R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F5R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F5R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F5R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F5R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F5R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F5R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F5R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F5R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F6R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F6R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F6R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F6R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F6R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F6R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F6R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F6R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F6R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F6R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F6R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F6R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F6R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F6R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F6R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F6R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F6R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F6R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F6R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F6R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F6R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F6R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F6R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F6R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F6R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F6R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F6R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F6R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F6R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F6R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F6R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F7R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F7R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F7R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F7R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F7R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F7R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F7R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F7R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F7R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F7R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F7R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F7R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F7R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F7R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F7R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F7R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F7R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F7R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F7R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F7R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F7R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F7R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F7R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F7R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F7R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F7R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F7R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F7R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F7R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F7R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F7R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F8R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F8R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F8R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F8R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F8R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F8R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F8R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F8R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F8R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F8R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F8R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F8R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F8R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F8R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F8R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F8R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F8R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F8R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F8R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F8R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F8R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F8R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F8R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F8R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F8R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F8R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F8R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F8R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F8R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F8R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F8R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F9R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F9R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F9R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F9R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F9R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F9R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F9R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F9R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F9R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F9R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F9R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F9R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F9R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F9R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F9R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F9R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F9R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F9R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F9R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F9R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F9R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F9R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F9R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F9R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F9R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F9R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F9R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F9R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F9R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F9R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F9R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F10R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F10R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F10R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F10R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F10R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F10R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F10R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F10R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F10R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F10R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F10R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F10R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F10R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F10R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F10R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F10R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F10R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F10R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F10R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F10R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F10R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F10R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F10R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F10R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F10R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F10R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F10R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F10R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F10R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F10R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F10R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F11R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F11R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F11R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F11R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F11R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F11R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F11R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F11R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F11R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F11R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F11R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F11R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F11R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F11R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F11R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F11R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F11R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F11R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F11R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F11R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F11R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F11R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F11R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F11R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F11R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F11R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F11R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F11R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F11R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F11R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F11R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F12R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F12R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F12R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F12R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F12R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F12R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F12R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F12R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F12R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F12R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F12R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F12R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F12R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F12R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F12R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F12R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F12R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F12R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F12R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F12R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F12R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F12R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F12R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F12R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F12R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F12R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F12R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F12R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F12R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F12R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F12R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F13R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F13R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F13R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F13R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F13R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F13R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F13R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F13R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F13R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F13R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F13R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F13R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F13R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F13R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F13R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F13R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F13R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F13R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F13R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F13R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F13R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F13R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F13R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F13R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F13R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F13R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F13R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F13R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F13R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F13R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F13R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA ((u16)0x0001) /* Clock Phase */ +#define SPI_CR1_CPOL ((u16)0x0002) /* Clock Polarity */ +#define SPI_CR1_MSTR ((u16)0x0004) /* Master Selection */ + +#define SPI_CR1_BR ((u16)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CR1_BR_0 ((u16)0x0008) /* Bit 0 */ +#define SPI_CR1_BR_1 ((u16)0x0010) /* Bit 1 */ +#define SPI_CR1_BR_2 ((u16)0x0020) /* Bit 2 */ + +#define SPI_CR1_SPE ((u16)0x0040) /* SPI Enable */ +#define SPI_CR1_LSBFIRST ((u16)0x0080) /* Frame Format */ +#define SPI_CR1_SSI ((u16)0x0100) /* Internal slave select */ +#define SPI_CR1_SSM ((u16)0x0200) /* Software slave management */ +#define SPI_CR1_RXONLY ((u16)0x0400) /* Receive only */ +#define SPI_CR1_DFF ((u16)0x0800) /* Data Frame Format */ +#define SPI_CR1_CRCNEXT ((u16)0x1000) /* Transmit CRC next */ +#define SPI_CR1_CRCEN ((u16)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE ((u16)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE ((u16)0x8000) /* Bidirectional data mode enable */ + + +/******************* Bit definition for SPI_CR2 register ********************/ +#define SPI_CR2_RXDMAEN ((u8)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN ((u8)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE ((u8)0x04) /* SS Output Enable */ +#define SPI_CR2_ERRIE ((u8)0x20) /* Error Interrupt Enable */ +#define SPI_CR2_RXNEIE ((u8)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CR2_TXEIE ((u8)0x80) /* Tx buffer Empty Interrupt Enable */ + + +/******************** Bit definition for SPI_SR register ********************/ +#define SPI_SR_RXNE ((u8)0x01) /* Receive buffer Not Empty */ +#define SPI_SR_TXE ((u8)0x02) /* Transmit buffer Empty */ +#define SPI_SR_CHSIDE ((u8)0x04) /* Channel side */ +#define SPI_SR_UDR ((u8)0x08) /* Underrun flag */ +#define SPI_SR_CRCERR ((u8)0x10) /* CRC Error flag */ +#define SPI_SR_MODF ((u8)0x20) /* Mode fault */ +#define SPI_SR_OVR ((u8)0x40) /* Overrun flag */ +#define SPI_SR_BSY ((u8)0x80) /* Busy flag */ + + +/******************** Bit definition for SPI_DR register ********************/ +#define SPI_DR_DR ((u16)0xFFFF) /* Data Register */ + + +/******************* Bit definition for SPI_CRCPR register ******************/ +#define SPI_CRCPR_CRCPOLY ((u16)0xFFFF) /* CRC polynomial register */ + + +/****************** Bit definition for SPI_RXCRCR register ******************/ +#define SPI_RXCRCR_RXCRC ((u16)0xFFFF) /* Rx CRC Register */ + + +/****************** Bit definition for SPI_TXCRCR register ******************/ +#define SPI_TXCRCR_TXCRC ((u16)0xFFFF) /* Tx CRC Register */ + + +/****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN ((u16)0x0001) /* Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN ((u16)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 ((u16)0x0002) /* Bit 0 */ +#define SPI_I2SCFGR_DATLEN_1 ((u16)0x0004) /* Bit 1 */ + +#define SPI_I2SCFGR_CKPOL ((u16)0x0008) /* steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD ((u16)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 ((u16)0x0010) /* Bit 0 */ +#define SPI_I2SCFGR_I2SSTD_1 ((u16)0x0020) /* Bit 1 */ + +#define SPI_I2SCFGR_PCMSYNC ((u16)0x0080) /* PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG ((u16)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 ((u16)0x0100) /* Bit 0 */ +#define SPI_I2SCFGR_I2SCFG_1 ((u16)0x0200) /* Bit 1 */ + +#define SPI_I2SCFGR_I2SE ((u16)0x0400) /* I2S Enable */ +#define SPI_I2SCFGR_I2SMOD ((u16)0x0800) /* I2S mode selection */ + + +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV ((u16)0x00FF) /* I2S Linear prescaler */ +#define SPI_I2SPR_ODD ((u16)0x0100) /* Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE ((u16)0x0200) /* Master Clock Output Enable */ + + + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CR1 register ********************/ +#define I2C_CR1_PE ((u16)0x0001) /* Peripheral Enable */ +#define I2C_CR1_SMBUS ((u16)0x0002) /* SMBus Mode */ +#define I2C_CR1_SMBTYPE ((u16)0x0008) /* SMBus Type */ +#define I2C_CR1_ENARP ((u16)0x0010) /* ARP Enable */ +#define I2C_CR1_ENPEC ((u16)0x0020) /* PEC Enable */ +#define I2C_CR1_ENGC ((u16)0x0040) /* General Call Enable */ +#define I2C_CR1_NOSTRETCH ((u16)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CR1_START ((u16)0x0100) /* Start Generation */ +#define I2C_CR1_STOP ((u16)0x0200) /* Stop Generation */ +#define I2C_CR1_ACK ((u16)0x0400) /* Acknowledge Enable */ +#define I2C_CR1_POS ((u16)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CR1_PEC ((u16)0x1000) /* Packet Error Checking */ +#define I2C_CR1_ALERT ((u16)0x2000) /* SMBus Alert */ +#define I2C_CR1_SWRST ((u16)0x8000) /* Software Reset */ + + +/******************* Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_FREQ ((u16)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CR2_FREQ_0 ((u16)0x0001) /* Bit 0 */ +#define I2C_CR2_FREQ_1 ((u16)0x0002) /* Bit 1 */ +#define I2C_CR2_FREQ_2 ((u16)0x0004) /* Bit 2 */ +#define I2C_CR2_FREQ_3 ((u16)0x0008) /* Bit 3 */ +#define I2C_CR2_FREQ_4 ((u16)0x0010) /* Bit 4 */ +#define I2C_CR2_FREQ_5 ((u16)0x0020) /* Bit 5 */ + +#define I2C_CR2_ITERREN ((u16)0x0100) /* Error Interrupt Enable */ +#define I2C_CR2_ITEVTEN ((u16)0x0200) /* Event Interrupt Enable */ +#define I2C_CR2_ITBUFEN ((u16)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CR2_DMAEN ((u16)0x0800) /* DMA Requests Enable */ +#define I2C_CR2_LAST ((u16)0x1000) /* DMA Last Transfer */ + + +/******************* Bit definition for I2C_OAR1 register *******************/ +#define I2C_OAR1_ADD1_7 ((u16)0x00FE) /* Interface Address */ +#define I2C_OAR1_ADD8_9 ((u16)0x0300) /* Interface Address */ + +#define I2C_OAR1_ADD0 ((u16)0x0001) /* Bit 0 */ +#define I2C_OAR1_ADD1 ((u16)0x0002) /* Bit 1 */ +#define I2C_OAR1_ADD2 ((u16)0x0004) /* Bit 2 */ +#define I2C_OAR1_ADD3 ((u16)0x0008) /* Bit 3 */ +#define I2C_OAR1_ADD4 ((u16)0x0010) /* Bit 4 */ +#define I2C_OAR1_ADD5 ((u16)0x0020) /* Bit 5 */ +#define I2C_OAR1_ADD6 ((u16)0x0040) /* Bit 6 */ +#define I2C_OAR1_ADD7 ((u16)0x0080) /* Bit 7 */ +#define I2C_OAR1_ADD8 ((u16)0x0100) /* Bit 8 */ +#define I2C_OAR1_ADD9 ((u16)0x0200) /* Bit 9 */ + +#define I2C_OAR1_ADDMODE ((u16)0x8000) /* Addressing Mode (Slave mode) */ + + +/******************* Bit definition for I2C_OAR2 register *******************/ +#define I2C_OAR2_ENDUAL ((u8)0x01) /* Dual addressing mode enable */ +#define I2C_OAR2_ADD2 ((u8)0xFE) /* Interface address */ + + +/******************** Bit definition for I2C_DR register ********************/ +#define I2C_DR_DR ((u8)0xFF) /* 8-bit Data Register */ + + +/******************* Bit definition for I2C_SR1 register ********************/ +#define I2C_SR1_SB ((u16)0x0001) /* Start Bit (Master mode) */ +#define I2C_SR1_ADDR ((u16)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_SR1_BTF ((u16)0x0004) /* Byte Transfer Finished */ +#define I2C_SR1_ADD10 ((u16)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_SR1_STOPF ((u16)0x0010) /* Stop detection (Slave mode) */ +#define I2C_SR1_RXNE ((u16)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_SR1_TXE ((u16)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_SR1_BERR ((u16)0x0100) /* Bus Error */ +#define I2C_SR1_ARLO ((u16)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_SR1_AF ((u16)0x0400) /* Acknowledge Failure */ +#define I2C_SR1_OVR ((u16)0x0800) /* Overrun/Underrun */ +#define I2C_SR1_PECERR ((u16)0x1000) /* PEC Error in reception */ +#define I2C_SR1_TIMEOUT ((u16)0x4000) /* Timeout or Tlow Error */ +#define I2C_SR1_SMBALERT ((u16)0x8000) /* SMBus Alert */ + + +/******************* Bit definition for I2C_SR2 register ********************/ +#define I2C_SR2_MSL ((u16)0x0001) /* Master/Slave */ +#define I2C_SR2_BUSY ((u16)0x0002) /* Bus Busy */ +#define I2C_SR2_TRA ((u16)0x0004) /* Transmitter/Receiver */ +#define I2C_SR2_GENCALL ((u16)0x0010) /* General Call Address (Slave mode) */ +#define I2C_SR2_SMBDEFAULT ((u16)0x0020) /* SMBus Device Default Address (Slave mode) */ +#define I2C_SR2_SMBHOST ((u16)0x0040) /* SMBus Host Header (Slave mode) */ +#define I2C_SR2_DUALF ((u16)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_SR2_PEC ((u16)0xFF00) /* Packet Error Checking Register */ + + +/******************* Bit definition for I2C_CCR register ********************/ +#define I2C_CCR_CCR ((u16)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CCR_DUTY ((u16)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CCR_FS ((u16)0x8000) /* I2C Master Mode Selection */ + + +/****************** Bit definition for I2C_TRISE register *******************/ +#define I2C_TRISE_TRISE ((u8)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ + + + +/******************************************************************************/ +/* */ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for USART_SR register *******************/ +#define USART_SR_PE ((u16)0x0001) /* Parity Error */ +#define USART_SR_FE ((u16)0x0002) /* Framing Error */ +#define USART_SR_NE ((u16)0x0004) /* Noise Error Flag */ +#define USART_SR_ORE ((u16)0x0008) /* OverRun Error */ +#define USART_SR_IDLE ((u16)0x0010) /* IDLE line detected */ +#define USART_SR_RXNE ((u16)0x0020) /* Read Data Register Not Empty */ +#define USART_SR_TC ((u16)0x0040) /* Transmission Complete */ +#define USART_SR_TXE ((u16)0x0080) /* Transmit Data Register Empty */ +#define USART_SR_LBD ((u16)0x0100) /* LIN Break Detection Flag */ +#define USART_SR_CTS ((u16)0x0200) /* CTS Flag */ + + +/******************* Bit definition for USART_DR register *******************/ +#define USART_DR_DR ((u16)0x01FF) /* Data value */ + + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((u16)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((u16)0xFFF0) /* Mantissa of USARTDIV */ + + +/****************** Bit definition for USART_CR1 register *******************/ +#define USART_CR1_SBK ((u16)0x0001) /* Send Break */ +#define USART_CR1_RWU ((u16)0x0002) /* Receiver wakeup */ +#define USART_CR1_RE ((u16)0x0004) /* Receiver Enable */ +#define USART_CR1_TE ((u16)0x0008) /* Transmitter Enable */ +#define USART_CR1_IDLEIE ((u16)0x0010) /* IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE ((u16)0x0020) /* RXNE Interrupt Enable */ +#define USART_CR1_TCIE ((u16)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE ((u16)0x0080) /* PE Interrupt Enable */ +#define USART_CR1_PEIE ((u16)0x0100) /* PE Interrupt Enable */ +#define USART_CR1_PS ((u16)0x0200) /* Parity Selection */ +#define USART_CR1_PCE ((u16)0x0400) /* Parity Control Enable */ +#define USART_CR1_WAKE ((u16)0x0800) /* Wakeup method */ +#define USART_CR1_M ((u16)0x1000) /* Word length */ +#define USART_CR1_UE ((u16)0x2000) /* USART Enable */ + + +/****************** Bit definition for USART_CR2 register *******************/ +#define USART_CR2_ADD ((u16)0x000F) /* Address of the USART node */ +#define USART_CR2_LBDL ((u16)0x0020) /* LIN Break Detection Length */ +#define USART_CR2_LBDIE ((u16)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL ((u16)0x0100) /* Last Bit Clock pulse */ +#define USART_CR2_CPHA ((u16)0x0200) /* Clock Phase */ +#define USART_CR2_CPOL ((u16)0x0400) /* Clock Polarity */ +#define USART_CR2_CLKEN ((u16)0x0800) /* Clock Enable */ + +#define USART_CR2_STOP ((u16)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CR2_STOP_0 ((u16)0x1000) /* Bit 0 */ +#define USART_CR2_STOP_1 ((u16)0x2000) /* Bit 1 */ + +#define USART_CR2_LINEN ((u16)0x4000) /* LIN mode enable */ + + +/****************** Bit definition for USART_CR3 register *******************/ +#define USART_CR3_EIE ((u16)0x0001) /* Error Interrupt Enable */ +#define USART_CR3_IREN ((u16)0x0002) /* IrDA mode Enable */ +#define USART_CR3_IRLP ((u16)0x0004) /* IrDA Low-Power */ +#define USART_CR3_HDSEL ((u16)0x0008) /* Half-Duplex Selection */ +#define USART_CR3_NACK ((u16)0x0010) /* Smartcard NACK enable */ +#define USART_CR3_SCEN ((u16)0x0020) /* Smartcard mode enable */ +#define USART_CR3_DMAR ((u16)0x0040) /* DMA Enable Receiver */ +#define USART_CR3_DMAT ((u16)0x0080) /* DMA Enable Transmitter */ +#define USART_CR3_RTSE ((u16)0x0100) /* RTS Enable */ +#define USART_CR3_CTSE ((u16)0x0200) /* CTS Enable */ +#define USART_CR3_CTSIE ((u16)0x0400) /* CTS Interrupt Enable */ + + +/****************** Bit definition for USART_GTPR register ******************/ +#define USART_GTPR_PSC ((u16)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GTPR_PSC_0 ((u16)0x0001) /* Bit 0 */ +#define USART_GTPR_PSC_1 ((u16)0x0002) /* Bit 1 */ +#define USART_GTPR_PSC_2 ((u16)0x0004) /* Bit 2 */ +#define USART_GTPR_PSC_3 ((u16)0x0008) /* Bit 3 */ +#define USART_GTPR_PSC_4 ((u16)0x0010) /* Bit 4 */ +#define USART_GTPR_PSC_5 ((u16)0x0020) /* Bit 5 */ +#define USART_GTPR_PSC_6 ((u16)0x0040) /* Bit 6 */ +#define USART_GTPR_PSC_7 ((u16)0x0080) /* Bit 7 */ + +#define USART_GTPR_GT ((u16)0xFF00) /* Guard time value */ + + + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for DBGMCU_IDCODE register *****************/ +#define DBGMCU_IDCODE_DEV_ID ((u32)0x00000FFF) /* Device Identifier */ + +#define DBGMCU_IDCODE_REV_ID ((u32)0xFFFF0000) /* REV_ID[15:0] bits (Revision Identifier) */ +#define DBGMCU_IDCODE_REV_ID_0 ((u32)0x00010000) /* Bit 0 */ +#define DBGMCU_IDCODE_REV_ID_1 ((u32)0x00020000) /* Bit 1 */ +#define DBGMCU_IDCODE_REV_ID_2 ((u32)0x00040000) /* Bit 2 */ +#define DBGMCU_IDCODE_REV_ID_3 ((u32)0x00080000) /* Bit 3 */ +#define DBGMCU_IDCODE_REV_ID_4 ((u32)0x00100000) /* Bit 4 */ +#define DBGMCU_IDCODE_REV_ID_5 ((u32)0x00200000) /* Bit 5 */ +#define DBGMCU_IDCODE_REV_ID_6 ((u32)0x00400000) /* Bit 6 */ +#define DBGMCU_IDCODE_REV_ID_7 ((u32)0x00800000) /* Bit 7 */ +#define DBGMCU_IDCODE_REV_ID_8 ((u32)0x01000000) /* Bit 8 */ +#define DBGMCU_IDCODE_REV_ID_9 ((u32)0x02000000) /* Bit 9 */ +#define DBGMCU_IDCODE_REV_ID_10 ((u32)0x04000000) /* Bit 10 */ +#define DBGMCU_IDCODE_REV_ID_11 ((u32)0x08000000) /* Bit 11 */ +#define DBGMCU_IDCODE_REV_ID_12 ((u32)0x10000000) /* Bit 12 */ +#define DBGMCU_IDCODE_REV_ID_13 ((u32)0x20000000) /* Bit 13 */ +#define DBGMCU_IDCODE_REV_ID_14 ((u32)0x40000000) /* Bit 14 */ +#define DBGMCU_IDCODE_REV_ID_15 ((u32)0x80000000) /* Bit 15 */ + + +/****************** Bit definition for DBGMCU_CR register *******************/ +#define DBGMCU_CR_DBG_SLEEP ((u32)0x00000001) /* Debug Sleep Mode */ +#define DBGMCU_CR_DBG_STOP ((u32)0x00000002) /* Debug Stop Mode */ +#define DBGMCU_CR_DBG_STANDBY ((u32)0x00000004) /* Debug Standby mode */ +#define DBGMCU_CR_TRACE_IOEN ((u32)0x00000020) /* Trace Pin Assignment Control */ + +#define DBGMCU_CR_TRACE_MODE ((u32)0x000000C0) /* TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ +#define DBGMCU_CR_TRACE_MODE_0 ((u32)0x00000040) /* Bit 0 */ +#define DBGMCU_CR_TRACE_MODE_1 ((u32)0x00000080) /* Bit 1 */ + +#define DBGMCU_CR_DBG_IWDG_STOP ((u32)0x00000100) /* Debug Independent Watchdog stopped when Core is halted */ +#define DBGMCU_CR_DBG_WWDG_STOP ((u32)0x00000200) /* Debug Window Watchdog stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM1_STOP ((u32)0x00000400) /* TIM1 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM2_STOP ((u32)0x00000800) /* TIM2 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM3_STOP ((u32)0x00001000) /* TIM3 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM4_STOP ((u32)0x00002000) /* TIM4 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_CAN_STOP ((u32)0x00004000) /* Debug CAN stopped when Core is halted */ +#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((u32)0x00008000) /* SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((u32)0x00010000) /* SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM5_STOP ((u32)0x00020000) /* TIM5 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM6_STOP ((u32)0x00040000) /* TIM6 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM7_STOP ((u32)0x00080000) /* TIM7 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM8_STOP ((u32)0x00100000) /* TIM8 counter stopped when core is halted */ + + + +/******************************************************************************/ +/* */ +/* FLASH and Option Bytes Registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACR register ******************/ +#define FLASH_ACR_LATENCY ((u8)0x07) /* LATENCY[2:0] bits (Latency) */ +#define FLASH_ACR_LATENCY_0 ((u8)0x01) /* Bit 0 */ +#define FLASH_ACR_LATENCY_1 ((u8)0x02) /* Bit 1 */ +#define FLASH_ACR_LATENCY_2 ((u8)0x04) /* Bit 2 */ + +#define FLASH_ACR_HLFCYA ((u8)0x08) /* Flash Half Cycle Access Enable */ +#define FLASH_ACR_PRFTBE ((u8)0x10) /* Prefetch Buffer Enable */ +#define FLASH_ACR_PRFTBS ((u8)0x20) /* Prefetch Buffer Status */ + + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((u32)0xFFFFFFFF) /* FPEC Key */ + + +/***************** Bit definition for FLASH_OPTKEYR register ****************/ +#define FLASH_OPTKEYR_OPTKEYR ((u32)0xFFFFFFFF) /* Option Byte Key */ + + +/****************** Bit definition for FLASH_SR register *******************/ +#define FLASH_SR_BSY ((u8)0x01) /* Busy */ +#define FLASH_SR_PGERR ((u8)0x04) /* Programming Error */ +#define FLASH_SR_WRPRTERR ((u8)0x10) /* Write Protection Error */ +#define FLASH_SR_EOP ((u8)0x20) /* End of operation */ + + +/******************* Bit definition for FLASH_CR register *******************/ +#define FLASH_CR_PG ((u16)0x0001) /* Programming */ +#define FLASH_CR_PER ((u16)0x0002) /* Page Erase */ +#define FLASH_CR_MER ((u16)0x0004) /* Mass Erase */ +#define FLASH_CR_OPTPG ((u16)0x0010) /* Option Byte Programming */ +#define FLASH_CR_OPTER ((u16)0x0020) /* Option Byte Erase */ +#define FLASH_CR_STRT ((u16)0x0040) /* Start */ +#define FLASH_CR_LOCK ((u16)0x0080) /* Lock */ +#define FLASH_CR_OPTWRE ((u16)0x0200) /* Option Bytes Write Enable */ +#define FLASH_CR_ERRIE ((u16)0x0400) /* Error Interrupt Enable */ +#define FLASH_CR_EOPIE ((u16)0x1000) /* End of operation interrupt enable */ + + +/******************* Bit definition for FLASH_AR register *******************/ +#define FLASH_AR_FAR ((u32)0xFFFFFFFF) /* Flash Address */ + + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((u16)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((u16)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((u16)0x03FC) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((u16)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STOP ((u16)0x0008) /* nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((u16)0x0010) /* nRST_STDBY */ +#define FLASH_OBR_Notused ((u16)0x03E0) /* Not used */ + + +/****************** Bit definition for FLASH_WRPR register ******************/ +#define FLASH_WRPR_WRP ((u32)0xFFFFFFFF) /* Write Protect */ + + +/*----------------------------------------------------------------------------*/ + + +/****************** Bit definition for FLASH_RDP register *******************/ +#define FLASH_RDP_RDP ((u32)0x000000FF) /* Read protection option byte */ +#define FLASH_RDP_nRDP ((u32)0x0000FF00) /* Read protection complemented option byte */ + + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((u32)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((u32)0xFF000000) /* User complemented option byte */ + + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((u32)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((u32)0x0000FF00) /* User data storage complemented option byte */ + + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((u32)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((u32)0xFF000000) /* User data storage complemented option byte */ + + +/****************** Bit definition for FLASH_WRP0 register ******************/ +#define FLASH_WRP0_WRP0 ((u32)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRP0_nWRP0 ((u32)0x0000FF00) /* Flash memory write protection complemented option bytes */ + + +/****************** Bit definition for FLASH_WRP1 register ******************/ +#define FLASH_WRP1_WRP1 ((u32)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRP1_nWRP1 ((u32)0xFF000000) /* Flash memory write protection complemented option bytes */ + + +/****************** Bit definition for FLASH_WRP2 register ******************/ +#define FLASH_WRP2_WRP2 ((u32)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRP2_nWRP2 ((u32)0x0000FF00) /* Flash memory write protection complemented option bytes */ + + +/****************** Bit definition for FLASH_WRP3 register ******************/ +#define FLASH_WRP3_WRP3 ((u32)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRP3_nWRP3 ((u32)0xFF000000) /* Flash memory write protection complemented option bytes */ + + +/* Exported macro ------------------------------------------------------------*/ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = 0x0) + +#define WRITE_REG(REG, VAL) ((REG) = VAL) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~CLEARMASK)) | (SETMASK))) + +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM32F10x_MAP_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/FWLib/inc/stm32f10x_nvic.h b/FWLib/inc/stm32f10x_nvic.h new file mode 100644 index 0000000..d108d14 --- /dev/null +++ b/FWLib/inc/stm32f10x_nvic.h @@ -0,0 +1,287 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_nvic.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* NVIC firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_NVIC_H +#define __STM32F10x_NVIC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* NVIC Init Structure definition */ +typedef struct +{ + u8 NVIC_IRQChannel; + u8 NVIC_IRQChannelPreemptionPriority; + u8 NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* IRQ Channels --------------------------------------------------------------*/ +#define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */ +#define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */ +#define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */ +#define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */ +#define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */ +#define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */ +#define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */ +#define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */ +#define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */ +#define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */ +#define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */ +#define DMA1_Channel1_IRQChannel ((u8)0x0B) /* DMA1 Channel 1 global Interrupt */ +#define DMA1_Channel2_IRQChannel ((u8)0x0C) /* DMA1 Channel 2 global Interrupt */ +#define DMA1_Channel3_IRQChannel ((u8)0x0D) /* DMA1 Channel 3 global Interrupt */ +#define DMA1_Channel4_IRQChannel ((u8)0x0E) /* DMA1 Channel 4 global Interrupt */ +#define DMA1_Channel5_IRQChannel ((u8)0x0F) /* DMA1 Channel 5 global Interrupt */ +#define DMA1_Channel6_IRQChannel ((u8)0x10) /* DMA1 Channel 6 global Interrupt */ +#define DMA1_Channel7_IRQChannel ((u8)0x11) /* DMA1 Channel 7 global Interrupt */ +#define ADC1_2_IRQChannel ((u8)0x12) /* ADC1 et ADC2 global Interrupt */ +#define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */ +#define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */ +#define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */ +#define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */ +#define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */ +#define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */ +#define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */ +#define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */ +#define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */ +#define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */ +#define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */ +#define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */ +#define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */ +#define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */ +#define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */ +#define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */ +#define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */ +#define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */ +#define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */ +#define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */ +#define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */ +#define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */ +#define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */ +#define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */ +#define TIM8_BRK_IRQChannel ((u8)0x2B) /* TIM8 Break Interrupt */ +#define TIM8_UP_IRQChannel ((u8)0x2C) /* TIM8 Update Interrupt */ +#define TIM8_TRG_COM_IRQChannel ((u8)0x2D) /* TIM8 Trigger and Commutation Interrupt */ +#define TIM8_CC_IRQChannel ((u8)0x2E) /* TIM8 Capture Compare Interrupt */ +#define ADC3_IRQChannel ((u8)0x2F) /* ADC3 global Interrupt */ +#define FSMC_IRQChannel ((u8)0x30) /* FSMC global Interrupt */ +#define SDIO_IRQChannel ((u8)0x31) /* SDIO global Interrupt */ +#define TIM5_IRQChannel ((u8)0x32) /* TIM5 global Interrupt */ +#define SPI3_IRQChannel ((u8)0x33) /* SPI3 global Interrupt */ +#define UART4_IRQChannel ((u8)0x34) /* UART4 global Interrupt */ +#define UART5_IRQChannel ((u8)0x35) /* UART5 global Interrupt */ +#define TIM6_IRQChannel ((u8)0x36) /* TIM6 global Interrupt */ +#define TIM7_IRQChannel ((u8)0x37) /* TIM7 global Interrupt */ +#define DMA2_Channel1_IRQChannel ((u8)0x38) /* DMA2 Channel 1 global Interrupt */ +#define DMA2_Channel2_IRQChannel ((u8)0x39) /* DMA2 Channel 2 global Interrupt */ +#define DMA2_Channel3_IRQChannel ((u8)0x3A) /* DMA2 Channel 3 global Interrupt */ +#define DMA2_Channel4_5_IRQChannel ((u8)0x3B) /* DMA2 Channel 4 and DMA2 Channel 5 global Interrupt */ + + +#define IS_NVIC_IRQ_CHANNEL(CHANNEL) (((CHANNEL) == WWDG_IRQChannel) || \ + ((CHANNEL) == PVD_IRQChannel) || \ + ((CHANNEL) == TAMPER_IRQChannel) || \ + ((CHANNEL) == RTC_IRQChannel) || \ + ((CHANNEL) == FLASH_IRQChannel) || \ + ((CHANNEL) == RCC_IRQChannel) || \ + ((CHANNEL) == EXTI0_IRQChannel) || \ + ((CHANNEL) == EXTI1_IRQChannel) || \ + ((CHANNEL) == EXTI2_IRQChannel) || \ + ((CHANNEL) == EXTI3_IRQChannel) || \ + ((CHANNEL) == EXTI4_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel1_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel2_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel3_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel4_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel5_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel6_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel7_IRQChannel) || \ + ((CHANNEL) == ADC1_2_IRQChannel) || \ + ((CHANNEL) == USB_HP_CAN_TX_IRQChannel) || \ + ((CHANNEL) == USB_LP_CAN_RX0_IRQChannel) || \ + ((CHANNEL) == CAN_RX1_IRQChannel) || \ + ((CHANNEL) == CAN_SCE_IRQChannel) || \ + ((CHANNEL) == EXTI9_5_IRQChannel) || \ + ((CHANNEL) == TIM1_BRK_IRQChannel) || \ + ((CHANNEL) == TIM1_UP_IRQChannel) || \ + ((CHANNEL) == TIM1_TRG_COM_IRQChannel) || \ + ((CHANNEL) == TIM1_CC_IRQChannel) || \ + ((CHANNEL) == TIM2_IRQChannel) || \ + ((CHANNEL) == TIM3_IRQChannel) || \ + ((CHANNEL) == TIM4_IRQChannel) || \ + ((CHANNEL) == I2C1_EV_IRQChannel) || \ + ((CHANNEL) == I2C1_ER_IRQChannel) || \ + ((CHANNEL) == I2C2_EV_IRQChannel) || \ + ((CHANNEL) == I2C2_ER_IRQChannel) || \ + ((CHANNEL) == SPI1_IRQChannel) || \ + ((CHANNEL) == SPI2_IRQChannel) || \ + ((CHANNEL) == USART1_IRQChannel) || \ + ((CHANNEL) == USART2_IRQChannel) || \ + ((CHANNEL) == USART3_IRQChannel) || \ + ((CHANNEL) == EXTI15_10_IRQChannel) || \ + ((CHANNEL) == RTCAlarm_IRQChannel) || \ + ((CHANNEL) == USBWakeUp_IRQChannel) || \ + ((CHANNEL) == TIM8_BRK_IRQChannel) || \ + ((CHANNEL) == TIM8_UP_IRQChannel) || \ + ((CHANNEL) == TIM8_TRG_COM_IRQChannel) || \ + ((CHANNEL) == TIM8_CC_IRQChannel) || \ + ((CHANNEL) == ADC3_IRQChannel) || \ + ((CHANNEL) == FSMC_IRQChannel) || \ + ((CHANNEL) == SDIO_IRQChannel) || \ + ((CHANNEL) == TIM5_IRQChannel) || \ + ((CHANNEL) == SPI3_IRQChannel) || \ + ((CHANNEL) == UART4_IRQChannel) || \ + ((CHANNEL) == UART5_IRQChannel) || \ + ((CHANNEL) == TIM6_IRQChannel) || \ + ((CHANNEL) == TIM7_IRQChannel) || \ + ((CHANNEL) == DMA2_Channel1_IRQChannel) || \ + ((CHANNEL) == DMA2_Channel2_IRQChannel) || \ + ((CHANNEL) == DMA2_Channel3_IRQChannel) || \ + ((CHANNEL) == DMA2_Channel4_5_IRQChannel)) + + +/* System Handlers -----------------------------------------------------------*/ +#define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */ +#define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */ +#define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */ +#define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */ +#define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */ +#define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */ +#define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */ +#define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */ +#define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */ + +#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \ + ((HANDLER) == SystemHandler_BusFault) || \ + ((HANDLER) == SystemHandler_UsageFault)) + +#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \ + ((HANDLER) == SystemHandler_BusFault) || \ + ((HANDLER) == SystemHandler_UsageFault) || \ + ((HANDLER) == SystemHandler_SVCall) || \ + ((HANDLER) == SystemHandler_DebugMonitor) || \ + ((HANDLER) == SystemHandler_PSV) || \ + ((HANDLER) == SystemHandler_SysTick)) + +#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \ + ((HANDLER) == SystemHandler_BusFault) || \ + ((HANDLER) == SystemHandler_SVCall)) + +#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_NMI) || \ + ((HANDLER) == SystemHandler_PSV) || \ + ((HANDLER) == SystemHandler_SysTick)) + +#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_PSV) || \ + ((HANDLER) == SystemHandler_SysTick)) + +#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \ + ((HANDLER) == SystemHandler_BusFault) || \ + ((HANDLER) == SystemHandler_UsageFault) || \ + ((HANDLER) == SystemHandler_SVCall) || \ + ((HANDLER) == SystemHandler_DebugMonitor) || \ + ((HANDLER) == SystemHandler_PSV) || \ + ((HANDLER) == SystemHandler_SysTick)) + +#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_HardFault) || \ + ((HANDLER) == SystemHandler_MemoryManage) || \ + ((HANDLER) == SystemHandler_BusFault) || \ + ((HANDLER) == SystemHandler_UsageFault) || \ + ((HANDLER) == SystemHandler_DebugMonitor)) + +#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \ + ((HANDLER) == SystemHandler_BusFault)) + + +/* Vector Table Base ---------------------------------------------------------*/ +#define NVIC_VectTab_RAM ((u32)0x20000000) +#define NVIC_VectTab_FLASH ((u32)0x08000000) + +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) + +/* System Low Power ----------------------------------------------------------*/ +#define NVIC_LP_SEVONPEND ((u8)0x10) +#define NVIC_LP_SLEEPDEEP ((u8)0x04) +#define NVIC_LP_SLEEPONEXIT ((u8)0x02) + +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) + +/* Preemption Priority Group -------------------------------------------------*/ +#define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF) +#define IS_NVIC_BASE_PRI(PRI) ((PRI) < 0x10) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NVIC_DeInit(void); +void NVIC_SCBDeInit(void); +void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SETPRIMASK(void); +void NVIC_RESETPRIMASK(void); +void NVIC_SETFAULTMASK(void); +void NVIC_RESETFAULTMASK(void); +void NVIC_BASEPRICONFIG(u32 NewPriority); +u32 NVIC_GetBASEPRI(void); +u16 NVIC_GetCurrentPendingIRQChannel(void); +ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel); +void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel); +void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel); +u16 NVIC_GetCurrentActiveHandler(void); +ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel); +u32 NVIC_GetCPUID(void); +void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset); +void NVIC_GenerateSystemReset(void); +void NVIC_GenerateCoreReset(void); +void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState); +void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState); +void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority, + u8 SystemHandlerSubPriority); +ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler); +void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler); +void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler); +ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler); +u32 NVIC_GetFaultHandlerSources(u32 SystemHandler); +u32 NVIC_GetFaultAddress(u32 SystemHandler); + +#endif /* __STM32F10x_NVIC_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/FWLib/inc/stm32f10x_rcc.h b/FWLib/inc/stm32f10x_rcc.h new file mode 100644 index 0000000..43c061a --- /dev/null +++ b/FWLib/inc/stm32f10x_rcc.h @@ -0,0 +1,288 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_rcc.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* RCC firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RCC_H +#define __STM32F10x_RCC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u32 SYSCLK_Frequency; + u32 HCLK_Frequency; + u32 PCLK1_Frequency; + u32 PCLK2_Frequency; + u32 ADCCLK_Frequency; +}RCC_ClocksTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* HSE configuration */ +#define RCC_HSE_OFF ((u32)0x00000000) +#define RCC_HSE_ON ((u32)0x00010000) +#define RCC_HSE_Bypass ((u32)0x00040000) + +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_Bypass)) + +/* PLL entry clock source */ +#define RCC_PLLSource_HSI_Div2 ((u32)0x00000000) +#define RCC_PLLSource_HSE_Div1 ((u32)0x00010000) +#define RCC_PLLSource_HSE_Div2 ((u32)0x00030000) + +#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div2)) + +/* PLL multiplication factor */ +#define RCC_PLLMul_2 ((u32)0x00000000) +#define RCC_PLLMul_3 ((u32)0x00040000) +#define RCC_PLLMul_4 ((u32)0x00080000) +#define RCC_PLLMul_5 ((u32)0x000C0000) +#define RCC_PLLMul_6 ((u32)0x00100000) +#define RCC_PLLMul_7 ((u32)0x00140000) +#define RCC_PLLMul_8 ((u32)0x00180000) +#define RCC_PLLMul_9 ((u32)0x001C0000) +#define RCC_PLLMul_10 ((u32)0x00200000) +#define RCC_PLLMul_11 ((u32)0x00240000) +#define RCC_PLLMul_12 ((u32)0x00280000) +#define RCC_PLLMul_13 ((u32)0x002C0000) +#define RCC_PLLMul_14 ((u32)0x00300000) +#define RCC_PLLMul_15 ((u32)0x00340000) +#define RCC_PLLMul_16 ((u32)0x00380000) + +#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ + ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ + ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ + ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ + ((MUL) == RCC_PLLMul_16)) + +/* System clock source */ +#define RCC_SYSCLKSource_HSI ((u32)0x00000000) +#define RCC_SYSCLKSource_HSE ((u32)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((u32)0x00000002) + +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) + +/* AHB clock source */ +#define RCC_SYSCLK_Div1 ((u32)0x00000000) +#define RCC_SYSCLK_Div2 ((u32)0x00000080) +#define RCC_SYSCLK_Div4 ((u32)0x00000090) +#define RCC_SYSCLK_Div8 ((u32)0x000000A0) +#define RCC_SYSCLK_Div16 ((u32)0x000000B0) +#define RCC_SYSCLK_Div64 ((u32)0x000000C0) +#define RCC_SYSCLK_Div128 ((u32)0x000000D0) +#define RCC_SYSCLK_Div256 ((u32)0x000000E0) +#define RCC_SYSCLK_Div512 ((u32)0x000000F0) + +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ + ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ + ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ + ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ + ((HCLK) == RCC_SYSCLK_Div512)) + +/* APB1/APB2 clock source */ +#define RCC_HCLK_Div1 ((u32)0x00000000) +#define RCC_HCLK_Div2 ((u32)0x00000400) +#define RCC_HCLK_Div4 ((u32)0x00000500) +#define RCC_HCLK_Div8 ((u32)0x00000600) +#define RCC_HCLK_Div16 ((u32)0x00000700) + +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ + ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ + ((PCLK) == RCC_HCLK_Div16)) + +/* RCC Interrupt source */ +#define RCC_IT_LSIRDY ((u8)0x01) +#define RCC_IT_LSERDY ((u8)0x02) +#define RCC_IT_HSIRDY ((u8)0x04) +#define RCC_IT_HSERDY ((u8)0x08) +#define RCC_IT_PLLRDY ((u8)0x10) +#define RCC_IT_CSS ((u8)0x80) + +#define IS_RCC_IT(IT) ((((IT) & (u8)0xE0) == 0x00) && ((IT) != 0x00)) +#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) +#define IS_RCC_CLEAR_IT(IT) ((((IT) & (u8)0x60) == 0x00) && ((IT) != 0x00)) + +/* USB clock source */ +#define RCC_USBCLKSource_PLLCLK_1Div5 ((u8)0x00) +#define RCC_USBCLKSource_PLLCLK_Div1 ((u8)0x01) + +#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ + ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) + +/* ADC clock source */ +#define RCC_PCLK2_Div2 ((u32)0x00000000) +#define RCC_PCLK2_Div4 ((u32)0x00004000) +#define RCC_PCLK2_Div6 ((u32)0x00008000) +#define RCC_PCLK2_Div8 ((u32)0x0000C000) + +#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ + ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) + +/* LSE configuration */ +#define RCC_LSE_OFF ((u8)0x00) +#define RCC_LSE_ON ((u8)0x01) +#define RCC_LSE_Bypass ((u8)0x04) + +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_Bypass)) + +/* RTC clock source */ +#define RCC_RTCCLKSource_LSE ((u32)0x00000100) +#define RCC_RTCCLKSource_LSI ((u32)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((u32)0x00000300) + +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ + ((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) + +/* AHB peripheral */ +#define RCC_AHBPeriph_DMA1 ((u32)0x00000001) +#define RCC_AHBPeriph_DMA2 ((u32)0x00000002) +#define RCC_AHBPeriph_SRAM ((u32)0x00000004) +#define RCC_AHBPeriph_FLITF ((u32)0x00000010) +#define RCC_AHBPeriph_CRC ((u32)0x00000040) +#define RCC_AHBPeriph_FSMC ((u32)0x00000100) +#define RCC_AHBPeriph_SDIO ((u32)0x00000400) + +#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) + +/* APB2 peripheral */ +#define RCC_APB2Periph_AFIO ((u32)0x00000001) +#define RCC_APB2Periph_GPIOA ((u32)0x00000004) +#define RCC_APB2Periph_GPIOB ((u32)0x00000008) +#define RCC_APB2Periph_GPIOC ((u32)0x00000010) +#define RCC_APB2Periph_GPIOD ((u32)0x00000020) +#define RCC_APB2Periph_GPIOE ((u32)0x00000040) +#define RCC_APB2Periph_GPIOF ((u32)0x00000080) +#define RCC_APB2Periph_GPIOG ((u32)0x00000100) +#define RCC_APB2Periph_ADC1 ((u32)0x00000200) +#define RCC_APB2Periph_ADC2 ((u32)0x00000400) +#define RCC_APB2Periph_TIM1 ((u32)0x00000800) +#define RCC_APB2Periph_SPI1 ((u32)0x00001000) +#define RCC_APB2Periph_TIM8 ((u32)0x00002000) +#define RCC_APB2Periph_USART1 ((u32)0x00004000) +#define RCC_APB2Periph_ADC3 ((u32)0x00008000) +#define RCC_APB2Periph_ALL ((u32)0x0000FFFD) + +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF0002) == 0x00) && ((PERIPH) != 0x00)) + +/* APB1 peripheral */ +#define RCC_APB1Periph_TIM2 ((u32)0x00000001) +#define RCC_APB1Periph_TIM3 ((u32)0x00000002) +#define RCC_APB1Periph_TIM4 ((u32)0x00000004) +#define RCC_APB1Periph_TIM5 ((u32)0x00000008) +#define RCC_APB1Periph_TIM6 ((u32)0x00000010) +#define RCC_APB1Periph_TIM7 ((u32)0x00000020) +#define RCC_APB1Periph_WWDG ((u32)0x00000800) +#define RCC_APB1Periph_SPI2 ((u32)0x00004000) +#define RCC_APB1Periph_SPI3 ((u32)0x00008000) +#define RCC_APB1Periph_USART2 ((u32)0x00020000) +#define RCC_APB1Periph_USART3 ((u32)0x00040000) +#define RCC_APB1Periph_UART4 ((u32)0x00080000) +#define RCC_APB1Periph_UART5 ((u32)0x00100000) +#define RCC_APB1Periph_I2C1 ((u32)0x00200000) +#define RCC_APB1Periph_I2C2 ((u32)0x00400000) +#define RCC_APB1Periph_USB ((u32)0x00800000) +#define RCC_APB1Periph_CAN ((u32)0x02000000) +#define RCC_APB1Periph_BKP ((u32)0x08000000) +#define RCC_APB1Periph_PWR ((u32)0x10000000) +#define RCC_APB1Periph_DAC ((u32)0x20000000) +#define RCC_APB1Periph_ALL ((u32)0x3AFEC83F) + +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC50137C0) == 0x00) && ((PERIPH) != 0x00)) + +/* Clock source to output on MCO pin */ +#define RCC_MCO_NoClock ((u8)0x00) +#define RCC_MCO_SYSCLK ((u8)0x04) +#define RCC_MCO_HSI ((u8)0x05) +#define RCC_MCO_HSE ((u8)0x06) +#define RCC_MCO_PLLCLK_Div2 ((u8)0x07) + +#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ + ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ + ((MCO) == RCC_MCO_PLLCLK_Div2)) + +/* RCC Flag */ +#define RCC_FLAG_HSIRDY ((u8)0x21) +#define RCC_FLAG_HSERDY ((u8)0x31) +#define RCC_FLAG_PLLRDY ((u8)0x39) +#define RCC_FLAG_LSERDY ((u8)0x41) +#define RCC_FLAG_LSIRDY ((u8)0x61) +#define RCC_FLAG_PINRST ((u8)0x7A) +#define RCC_FLAG_PORRST ((u8)0x7B) +#define RCC_FLAG_SFTRST ((u8)0x7C) +#define RCC_FLAG_IWDGRST ((u8)0x7D) +#define RCC_FLAG_WWDGRST ((u8)0x7E) +#define RCC_FLAG_LPWRRST ((u8)0x7F) + +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ + ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ + ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ + ((FLAG) == RCC_FLAG_LPWRRST)) + +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void RCC_DeInit(void); +void RCC_HSEConfig(u32 RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource); +u8 RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(u32 RCC_SYSCLK); +void RCC_PCLK1Config(u32 RCC_HCLK); +void RCC_PCLK2Config(u32 RCC_HCLK); +void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState); +void RCC_USBCLKConfig(u32 RCC_USBCLKSource); +void RCC_ADCCLKConfig(u32 RCC_PCLK2); +void RCC_LSEConfig(u8 RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); +void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(u8 RCC_MCO); +FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(u8 RCC_IT); +void RCC_ClearITPendingBit(u8 RCC_IT); + +#endif /* __STM32F10x_RCC_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/FWLib/inc/stm32f10x_sdio.h b/FWLib/inc/stm32f10x_sdio.h new file mode 100644 index 0000000..f71ac32 --- /dev/null +++ b/FWLib/inc/stm32f10x_sdio.h @@ -0,0 +1,337 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_sdio.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* SDIO firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SDIO_H +#define __STM32F10x_SDIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u8 SDIO_ClockDiv; + u32 SDIO_ClockEdge; + u32 SDIO_ClockBypass; + u32 SDIO_ClockPowerSave; + u32 SDIO_BusWide; + u32 SDIO_HardwareFlowControl; +} SDIO_InitTypeDef; + +typedef struct +{ + u32 SDIO_Argument; + u32 SDIO_CmdIndex; + u32 SDIO_Response; + u32 SDIO_Wait; + u32 SDIO_CPSM; +} SDIO_CmdInitTypeDef; + +typedef struct +{ + u32 SDIO_DataTimeOut; + u32 SDIO_DataLength; + u32 SDIO_DataBlockSize; + u32 SDIO_TransferDir; + u32 SDIO_TransferMode; + u32 SDIO_DPSM; +} SDIO_DataInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* SDIO Clock Edge -----------------------------------------------------------*/ +#define SDIO_ClockEdge_Rising ((u32)0x00000000) +#define SDIO_ClockEdge_Falling ((u32)0x00002000) + +#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ + ((EDGE) == SDIO_ClockEdge_Falling)) +/* SDIO Clock Bypass ----------------------------------------------------------*/ +#define SDIO_ClockBypass_Disable ((u32)0x00000000) +#define SDIO_ClockBypass_Enable ((u32)0x00000400) + +#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ + ((BYPASS) == SDIO_ClockBypass_Enable)) + +/* SDIO Clock Power Save ----------------------------------------------------*/ +#define SDIO_ClockPowerSave_Disable ((u32)0x00000000) +#define SDIO_ClockPowerSave_Enable ((u32)0x00000200) + +#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ + ((SAVE) == SDIO_ClockPowerSave_Enable)) + +/* SDIO Bus Wide -------------------------------------------------------------*/ +#define SDIO_BusWide_1b ((u32)0x00000000) +#define SDIO_BusWide_4b ((u32)0x00000800) +#define SDIO_BusWide_8b ((u32)0x00001000) + +#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ + ((WIDE) == SDIO_BusWide_8b)) + +/* SDIO Hardware Flow Control -----------------------------------------------*/ +#define SDIO_HardwareFlowControl_Disable ((u32)0x00000000) +#define SDIO_HardwareFlowControl_Enable ((u32)0x00004000) + +#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ + ((CONTROL) == SDIO_HardwareFlowControl_Enable)) + +/* SDIO Power State ----------------------------------------------------------*/ +#define SDIO_PowerState_OFF ((u32)0x00000000) +#define SDIO_PowerState_ON ((u32)0x00000003) + +#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) + +/* SDIO Interrupt soucres ----------------------------------------------------*/ +#define SDIO_IT_CCRCFAIL ((u32)0x00000001) +#define SDIO_IT_DCRCFAIL ((u32)0x00000002) +#define SDIO_IT_CTIMEOUT ((u32)0x00000004) +#define SDIO_IT_DTIMEOUT ((u32)0x00000008) +#define SDIO_IT_TXUNDERR ((u32)0x00000010) +#define SDIO_IT_RXOVERR ((u32)0x00000020) +#define SDIO_IT_CMDREND ((u32)0x00000040) +#define SDIO_IT_CMDSENT ((u32)0x00000080) +#define SDIO_IT_DATAEND ((u32)0x00000100) +#define SDIO_IT_STBITERR ((u32)0x00000200) +#define SDIO_IT_DBCKEND ((u32)0x00000400) +#define SDIO_IT_CMDACT ((u32)0x00000800) +#define SDIO_IT_TXACT ((u32)0x00001000) +#define SDIO_IT_RXACT ((u32)0x00002000) +#define SDIO_IT_TXFIFOHE ((u32)0x00004000) +#define SDIO_IT_RXFIFOHF ((u32)0x00008000) +#define SDIO_IT_TXFIFOF ((u32)0x00010000) +#define SDIO_IT_RXFIFOF ((u32)0x00020000) +#define SDIO_IT_TXFIFOE ((u32)0x00040000) +#define SDIO_IT_RXFIFOE ((u32)0x00080000) +#define SDIO_IT_TXDAVL ((u32)0x00100000) +#define SDIO_IT_RXDAVL ((u32)0x00200000) +#define SDIO_IT_SDIOIT ((u32)0x00400000) +#define SDIO_IT_CEATAEND ((u32)0x00800000) + +#define IS_SDIO_IT(IT) ((((IT) & (u32)0xFF000000) == 0x00) && ((IT) != (u32)0x00)) + +/* SDIO Command Index -------------------------------------------------------*/ +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) + +/* SDIO Response Type --------------------------------------------------------*/ +#define SDIO_Response_No ((u32)0x00000000) +#define SDIO_Response_Short ((u32)0x00000040) +#define SDIO_Response_Long ((u32)0x000000C0) + +#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ + ((RESPONSE) == SDIO_Response_Short) || \ + ((RESPONSE) == SDIO_Response_Long)) + +/* SDIO Wait Interrupt State -------------------------------------------------*/ +#define SDIO_Wait_No ((u32)0x00000000) /* SDIO No Wait, TimeOut is enabled */ +#define SDIO_Wait_IT ((u32)0x00000100) /* SDIO Wait Interrupt Request */ +#define SDIO_Wait_Pend ((u32)0x00000200) /* SDIO Wait End of transfer */ + +#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ + ((WAIT) == SDIO_Wait_Pend)) + +/* SDIO CPSM State -----------------------------------------------------------*/ +#define SDIO_CPSM_Disable ((u32)0x00000000) +#define SDIO_CPSM_Enable ((u32)0x00000400) + +#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) + +/* SDIO Response Registers ---------------------------------------------------*/ +#define SDIO_RESP1 ((u32)0x00000000) +#define SDIO_RESP2 ((u32)0x00000004) +#define SDIO_RESP3 ((u32)0x00000008) +#define SDIO_RESP4 ((u32)0x0000000C) + +#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ + ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) + +/* SDIO Data Length ----------------------------------------------------------*/ +#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) + +/* SDIO Data Block Size ------------------------------------------------------*/ +#define SDIO_DataBlockSize_1b ((u32)0x00000000) +#define SDIO_DataBlockSize_2b ((u32)0x00000010) +#define SDIO_DataBlockSize_4b ((u32)0x00000020) +#define SDIO_DataBlockSize_8b ((u32)0x00000030) +#define SDIO_DataBlockSize_16b ((u32)0x00000040) +#define SDIO_DataBlockSize_32b ((u32)0x00000050) +#define SDIO_DataBlockSize_64b ((u32)0x00000060) +#define SDIO_DataBlockSize_128b ((u32)0x00000070) +#define SDIO_DataBlockSize_256b ((u32)0x00000080) +#define SDIO_DataBlockSize_512b ((u32)0x00000090) +#define SDIO_DataBlockSize_1024b ((u32)0x000000A0) +#define SDIO_DataBlockSize_2048b ((u32)0x000000B0) +#define SDIO_DataBlockSize_4096b ((u32)0x000000C0) +#define SDIO_DataBlockSize_8192b ((u32)0x000000D0) +#define SDIO_DataBlockSize_16384b ((u32)0x000000E0) + +#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ + ((SIZE) == SDIO_DataBlockSize_2b) || \ + ((SIZE) == SDIO_DataBlockSize_4b) || \ + ((SIZE) == SDIO_DataBlockSize_8b) || \ + ((SIZE) == SDIO_DataBlockSize_16b) || \ + ((SIZE) == SDIO_DataBlockSize_32b) || \ + ((SIZE) == SDIO_DataBlockSize_64b) || \ + ((SIZE) == SDIO_DataBlockSize_128b) || \ + ((SIZE) == SDIO_DataBlockSize_256b) || \ + ((SIZE) == SDIO_DataBlockSize_512b) || \ + ((SIZE) == SDIO_DataBlockSize_1024b) || \ + ((SIZE) == SDIO_DataBlockSize_2048b) || \ + ((SIZE) == SDIO_DataBlockSize_4096b) || \ + ((SIZE) == SDIO_DataBlockSize_8192b) || \ + ((SIZE) == SDIO_DataBlockSize_16384b)) + +/* SDIO Transfer Direction ---------------------------------------------------*/ +#define SDIO_TransferDir_ToCard ((u32)0x00000000) +#define SDIO_TransferDir_ToSDIO ((u32)0x00000002) + +#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ + ((DIR) == SDIO_TransferDir_ToSDIO)) + +/* SDIO Transfer Type --------------------------------------------------------*/ +#define SDIO_TransferMode_Block ((u32)0x00000000) +#define SDIO_TransferMode_Stream ((u32)0x00000004) + +#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ + ((MODE) == SDIO_TransferMode_Block)) + +/* SDIO DPSM State -----------------------------------------------------------*/ +#define SDIO_DPSM_Disable ((u32)0x00000000) +#define SDIO_DPSM_Enable ((u32)0x00000001) + +#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) + +/* SDIO Flags ----------------------------------------------------------------*/ +#define SDIO_FLAG_CCRCFAIL ((u32)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((u32)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((u32)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((u32)0x00000008) +#define SDIO_FLAG_TXUNDERR ((u32)0x00000010) +#define SDIO_FLAG_RXOVERR ((u32)0x00000020) +#define SDIO_FLAG_CMDREND ((u32)0x00000040) +#define SDIO_FLAG_CMDSENT ((u32)0x00000080) +#define SDIO_FLAG_DATAEND ((u32)0x00000100) +#define SDIO_FLAG_STBITERR ((u32)0x00000200) +#define SDIO_FLAG_DBCKEND ((u32)0x00000400) +#define SDIO_FLAG_CMDACT ((u32)0x00000800) +#define SDIO_FLAG_TXACT ((u32)0x00001000) +#define SDIO_FLAG_RXACT ((u32)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((u32)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((u32)0x00008000) +#define SDIO_FLAG_TXFIFOF ((u32)0x00010000) +#define SDIO_FLAG_RXFIFOF ((u32)0x00020000) +#define SDIO_FLAG_TXFIFOE ((u32)0x00040000) +#define SDIO_FLAG_RXFIFOE ((u32)0x00080000) +#define SDIO_FLAG_TXDAVL ((u32)0x00100000) +#define SDIO_FLAG_RXDAVL ((u32)0x00200000) +#define SDIO_FLAG_SDIOIT ((u32)0x00400000) +#define SDIO_FLAG_CEATAEND ((u32)0x00800000) + +#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_TXUNDERR) || \ + ((FLAG) == SDIO_FLAG_RXOVERR) || \ + ((FLAG) == SDIO_FLAG_CMDREND) || \ + ((FLAG) == SDIO_FLAG_CMDSENT) || \ + ((FLAG) == SDIO_FLAG_DATAEND) || \ + ((FLAG) == SDIO_FLAG_STBITERR) || \ + ((FLAG) == SDIO_FLAG_DBCKEND) || \ + ((FLAG) == SDIO_FLAG_CMDACT) || \ + ((FLAG) == SDIO_FLAG_TXACT) || \ + ((FLAG) == SDIO_FLAG_RXACT) || \ + ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOF) || \ + ((FLAG) == SDIO_FLAG_RXFIFOF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOE) || \ + ((FLAG) == SDIO_FLAG_TXDAVL) || \ + ((FLAG) == SDIO_FLAG_RXDAVL) || \ + ((FLAG) == SDIO_FLAG_SDIOIT) || \ + ((FLAG) == SDIO_FLAG_CEATAEND)) + +#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFF3FF800) == 0x00) && ((FLAG) != (u32)0x00)) + +#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ + ((IT) == SDIO_IT_DCRCFAIL) || \ + ((IT) == SDIO_IT_CTIMEOUT) || \ + ((IT) == SDIO_IT_DTIMEOUT) || \ + ((IT) == SDIO_IT_TXUNDERR) || \ + ((IT) == SDIO_IT_RXOVERR) || \ + ((IT) == SDIO_IT_CMDREND) || \ + ((IT) == SDIO_IT_CMDSENT) || \ + ((IT) == SDIO_IT_DATAEND) || \ + ((IT) == SDIO_IT_STBITERR) || \ + ((IT) == SDIO_IT_DBCKEND) || \ + ((IT) == SDIO_IT_CMDACT) || \ + ((IT) == SDIO_IT_TXACT) || \ + ((IT) == SDIO_IT_RXACT) || \ + ((IT) == SDIO_IT_TXFIFOHE) || \ + ((IT) == SDIO_IT_RXFIFOHF) || \ + ((IT) == SDIO_IT_TXFIFOF) || \ + ((IT) == SDIO_IT_RXFIFOF) || \ + ((IT) == SDIO_IT_TXFIFOE) || \ + ((IT) == SDIO_IT_RXFIFOE) || \ + ((IT) == SDIO_IT_TXDAVL) || \ + ((IT) == SDIO_IT_RXDAVL) || \ + ((IT) == SDIO_IT_SDIOIT) || \ + ((IT) == SDIO_IT_CEATAEND)) + +#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (u32)0xFF3FF800) == 0x00) && ((IT) != (u32)0x00)) + +/* SDIO Read Wait Mode -------------------------------------------------------*/ +#define SDIO_ReadWaitMode_CLK ((u32)0x00000000) +#define SDIO_ReadWaitMode_DATA2 ((u32)0x00000001) + +#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ + ((MODE) == SDIO_ReadWaitMode_DATA2)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void SDIO_DeInit(void); +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockCmd(FunctionalState NewState); +void SDIO_SetPowerState(u32 SDIO_PowerState); +u32 SDIO_GetPowerState(void); +void SDIO_ITConfig(u32 SDIO_IT, FunctionalState NewState); +void SDIO_DMACmd(FunctionalState NewState); +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); +u8 SDIO_GetCommandResponse(void); +u32 SDIO_GetResponse(u32 SDIO_RESP); +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +u32 SDIO_GetDataCounter(void); +u32 SDIO_ReadData(void); +void SDIO_WriteData(u32 Data); +u32 SDIO_GetFIFOCount(void); +void SDIO_StartSDIOReadWait(FunctionalState NewState); +void SDIO_StopSDIOReadWait(FunctionalState NewState); +void SDIO_SetSDIOReadWaitMode(u32 SDIO_ReadWaitMode); +void SDIO_SetSDIOOperation(FunctionalState NewState); +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); +void SDIO_CommandCompletionCmd(FunctionalState NewState); +void SDIO_CEATAITCmd(FunctionalState NewState); +void SDIO_SendCEATACmd(FunctionalState NewState); +FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG); +void SDIO_ClearFlag(u32 SDIO_FLAG); +ITStatus SDIO_GetITStatus(u32 SDIO_IT); +void SDIO_ClearITPendingBit(u32 SDIO_IT); + +#endif /* __STM32F10x_SDIO_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/FWLib/inc/stm32f10x_spi.h b/FWLib/inc/stm32f10x_spi.h new file mode 100644 index 0000000..186b67b --- /dev/null +++ b/FWLib/inc/stm32f10x_spi.h @@ -0,0 +1,198 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_spi.h +* Author : MCD Application Team +* Version : V1.0 +* Date : 10/08/2007 +* Description : This file contains all the functions prototypes for the +* SPI firmware library. +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SPI_H +#define __STM32F10x_SPI_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* SPI Init structure definition */ +typedef struct +{ + u16 SPI_Direction; + u16 SPI_Mode; + u16 SPI_DataSize; + u16 SPI_CPOL; + u16 SPI_CPHA; + u16 SPI_NSS; + u16 SPI_BaudRatePrescaler; + u16 SPI_FirstBit; + u16 SPI_CRCPolynomial; +}SPI_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* SPI data direction mode */ +#define SPI_Direction_2Lines_FullDuplex ((u16)0x0000) +#define SPI_Direction_2Lines_RxOnly ((u16)0x0400) +#define SPI_Direction_1Line_Rx ((u16)0x8000) +#define SPI_Direction_1Line_Tx ((u16)0xC000) + +#define IS_SPI_DIRECTION_MODE(MODE) ((MODE == SPI_Direction_2Lines_FullDuplex) || \ + (MODE == SPI_Direction_2Lines_RxOnly) || \ + (MODE == SPI_Direction_1Line_Rx) || \ + (MODE == SPI_Direction_1Line_Tx)) + +/* SPI master/slave mode */ +#define SPI_Mode_Master ((u16)0x0104) +#define SPI_Mode_Slave ((u16)0x0000) + +#define IS_SPI_MODE(MODE) ((MODE == SPI_Mode_Master) || \ + (MODE == SPI_Mode_Slave)) + +/* SPI data size */ +#define SPI_DataSize_16b ((u16)0x0800) +#define SPI_DataSize_8b ((u16)0x0000) + +#define IS_SPI_DATASIZE(DATASIZE) ((DATASIZE == SPI_DataSize_16b) || \ + (DATASIZE == SPI_DataSize_8b)) + +/* SPI Clock Polarity */ +#define SPI_CPOL_Low ((u16)0x0000) +#define SPI_CPOL_High ((u16)0x0002) + +#define IS_SPI_CPOL(CPOL) ((CPOL == SPI_CPOL_Low) || \ + (CPOL == SPI_CPOL_High)) + +/* SPI Clock Phase */ +#define SPI_CPHA_1Edge ((u16)0x0000) +#define SPI_CPHA_2Edge ((u16)0x0001) + +#define IS_SPI_CPHA(CPHA) ((CPHA == SPI_CPHA_1Edge) || \ + (CPHA == SPI_CPHA_2Edge)) + +/* SPI Slave Select management */ +#define SPI_NSS_Soft ((u16)0x0200) +#define SPI_NSS_Hard ((u16)0x0000) + +#define IS_SPI_NSS(NSS) ((NSS == SPI_NSS_Soft) || \ + (NSS == SPI_NSS_Hard)) + +/* SPI BaudRate Prescaler */ +#define SPI_BaudRatePrescaler_2 ((u16)0x0000) +#define SPI_BaudRatePrescaler_4 ((u16)0x0008) +#define SPI_BaudRatePrescaler_8 ((u16)0x0010) +#define SPI_BaudRatePrescaler_16 ((u16)0x0018) +#define SPI_BaudRatePrescaler_32 ((u16)0x0020) +#define SPI_BaudRatePrescaler_64 ((u16)0x0028) +#define SPI_BaudRatePrescaler_128 ((u16)0x0030) +#define SPI_BaudRatePrescaler_256 ((u16)0x0038) + +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) ((PRESCALER == SPI_BaudRatePrescaler_2) || \ + (PRESCALER == SPI_BaudRatePrescaler_4) || \ + (PRESCALER == SPI_BaudRatePrescaler_8) || \ + (PRESCALER == SPI_BaudRatePrescaler_16) || \ + (PRESCALER == SPI_BaudRatePrescaler_32) || \ + (PRESCALER == SPI_BaudRatePrescaler_64) || \ + (PRESCALER == SPI_BaudRatePrescaler_128) || \ + (PRESCALER == SPI_BaudRatePrescaler_256)) + +/* SPI MSB/LSB transmission */ +#define SPI_FirstBit_MSB ((u16)0x0000) +#define SPI_FirstBit_LSB ((u16)0x0080) + +#define IS_SPI_FIRST_BIT(BIT) ((BIT == SPI_FirstBit_MSB) || \ + (BIT == SPI_FirstBit_LSB)) + +/* SPI DMA transfer requests */ +#define SPI_DMAReq_Tx ((u16)0x0002) +#define SPI_DMAReq_Rx ((u16)0x0001) + +#define IS_SPI_DMA_REQ(REQ) (((REQ & (u16)0xFFFC) == 0x00) && (REQ != 0x00)) + +/* SPI NSS internal software mangement */ +#define SPI_NSSInternalSoft_Set ((u16)0x0100) +#define SPI_NSSInternalSoft_Reset ((u16)0xFEFF) + +#define IS_SPI_NSS_INTERNAL(INTERNAL) ((INTERNAL == SPI_NSSInternalSoft_Set) || \ + (INTERNAL == SPI_NSSInternalSoft_Reset)) + +/* SPI CRC Transmit/Receive */ +#define SPI_CRC_Tx ((u8)0x00) +#define SPI_CRC_Rx ((u8)0x01) + +#define IS_SPI_CRC(CRC) ((CRC == SPI_CRC_Tx) || (CRC == SPI_CRC_Rx)) + +/* SPI direction transmit/receive */ +#define SPI_Direction_Rx ((u16)0xBFFF) +#define SPI_Direction_Tx ((u16)0x4000) + +#define IS_SPI_DIRECTION(DIRECTION) ((DIRECTION == SPI_Direction_Rx) || \ + (DIRECTION == SPI_Direction_Tx)) + +/* SPI interrupts definition */ +#define SPI_IT_TXE ((u8)0x71) +#define SPI_IT_RXNE ((u8)0x60) +#define SPI_IT_ERR ((u8)0x50) + +#define IS_SPI_CONFIG_IT(IT) ((IT == SPI_IT_TXE) || (IT == SPI_IT_RXNE) || \ + (IT == SPI_IT_ERR)) + +#define SPI_IT_OVR ((u8)0x56) +#define SPI_IT_MODF ((u8)0x55) +#define SPI_IT_CRCERR ((u8)0x54) + +#define IS_SPI_CLEAR_IT(IT) ((IT == SPI_IT_OVR) || (IT == SPI_IT_MODF) || \ + (IT == SPI_IT_CRCERR)) + +#define IS_SPI_GET_IT(IT) ((IT == SPI_IT_TXE) || (IT == SPI_IT_RXNE) || \ + (IT == SPI_IT_OVR) || (IT == SPI_IT_MODF) || \ + (IT == SPI_IT_CRCERR)) + +/* SPI flags definition */ +#define SPI_FLAG_RXNE ((u16)0x0001) +#define SPI_FLAG_TXE ((u16)0x0002) +#define SPI_FLAG_CRCERR ((u16)0x0010) +#define SPI_FLAG_MODF ((u16)0x0020) +#define SPI_FLAG_OVR ((u16)0x0040) +#define SPI_FLAG_BSY ((u16)0x0080) + +#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xFF8F) == 0x00) && (FLAG != 0x00)) +#define IS_SPI_GET_FLAG(FLAG) ((FLAG == SPI_FLAG_BSY) || (FLAG == SPI_FLAG_OVR) || \ + (FLAG == SPI_FLAG_MODF) || (FLAG == SPI_FLAG_CRCERR) || \ + (FLAG == SPI_FLAG_TXE) || (FLAG == SPI_FLAG_RXNE)) + +/* SPI CRC polynomial --------------------------------------------------------*/ +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (POLYNOMIAL >= 0x1) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void SPI_DeInit(SPI_TypeDef* SPIx); +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_ITConfig(SPI_TypeDef* SPIx, u8 SPI_IT, FunctionalState NewState); +void SPI_DMACmd(SPI_TypeDef* SPIx, u16 SPI_DMAReq, FunctionalState NewState); +void SPI_SendData(SPI_TypeDef* SPIx, u16 Data); +u16 SPI_ReceiveData(SPI_TypeDef* SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, u16 SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, u16 SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +u16 SPI_GetCRC(SPI_TypeDef* SPIx, u8 SPI_CRC); +u16 SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, u16 SPI_Direction); +FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_FLAG); +void SPI_ClearFlag(SPI_TypeDef* SPIx, u16 SPI_FLAG); +ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_IT); +void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, u8 SPI_IT); + +#endif /*__STM32F10x_SPI_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/FWLib/inc/stm32f10x_type.h b/FWLib/inc/stm32f10x_type.h new file mode 100644 index 0000000..5563de3 --- /dev/null +++ b/FWLib/inc/stm32f10x_type.h @@ -0,0 +1,80 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_type.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the common data types used for the +* STM32F10x firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_TYPE_H +#define __STM32F10x_TYPE_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +typedef signed long s32; +typedef signed short s16; +typedef signed char s8; + +typedef signed long const sc32; /* Read Only */ +typedef signed short const sc16; /* Read Only */ +typedef signed char const sc8; /* Read Only */ + +typedef volatile signed long vs32; +typedef volatile signed short vs16; +typedef volatile signed char vs8; + +typedef volatile signed long const vsc32; /* Read Only */ +typedef volatile signed short const vsc16; /* Read Only */ +typedef volatile signed char const vsc8; /* Read Only */ + +typedef unsigned long u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef unsigned long const uc32; /* Read Only */ +typedef unsigned short const uc16; /* Read Only */ +typedef unsigned char const uc8; /* Read Only */ + +typedef volatile unsigned long vu32; +typedef volatile unsigned short vu16; +typedef volatile unsigned char vu8; + +typedef volatile unsigned long const vuc32; /* Read Only */ +typedef volatile unsigned short const vuc16; /* Read Only */ +typedef volatile unsigned char const vuc8; /* Read Only */ + +typedef enum {FALSE = 0, TRUE = !FALSE} bool; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#define U8_MAX ((u8)255) +#define S8_MAX ((s8)127) +#define S8_MIN ((s8)-128) +#define U16_MAX ((u16)65535u) +#define S16_MAX ((s16)32767) +#define S16_MIN ((s16)-32768) +#define U32_MAX ((u32)4294967295uL) +#define S32_MAX ((s32)2147483647) +#define S32_MIN ((s32)-2147483648) + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM32F10x_TYPE_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/FWLib/inc/stm32f10x_usart.h b/FWLib/inc/stm32f10x_usart.h new file mode 100644 index 0000000..b80b886 --- /dev/null +++ b/FWLib/inc/stm32f10x_usart.h @@ -0,0 +1,253 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_usart.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* USART firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_USART_H +#define __STM32F10x_USART_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* USART Init Structure definition */ +typedef struct +{ + u32 USART_BaudRate; + u16 USART_WordLength; + u16 USART_StopBits; + u16 USART_Parity; + u16 USART_Mode; + u16 USART_HardwareFlowControl; +} USART_InitTypeDef; + +/* USART Clock Init Structure definition */ +typedef struct +{ + u16 USART_Clock; + u16 USART_CPOL; + u16 USART_CPHA; + u16 USART_LastBit; +} USART_ClockInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +#define IS_USART_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \ + ((*(u32*)&(PERIPH)) == USART2_BASE) || \ + ((*(u32*)&(PERIPH)) == USART3_BASE) || \ + ((*(u32*)&(PERIPH)) == UART4_BASE) || \ + ((*(u32*)&(PERIPH)) == UART5_BASE)) + +#define IS_USART_123_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \ + ((*(u32*)&(PERIPH)) == USART2_BASE) || \ + ((*(u32*)&(PERIPH)) == USART3_BASE)) + +#define IS_USART_1234_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \ + ((*(u32*)&(PERIPH)) == USART2_BASE) || \ + ((*(u32*)&(PERIPH)) == USART3_BASE) || \ + ((*(u32*)&(PERIPH)) == UART4_BASE)) + +/* USART Word Length ---------------------------------------------------------*/ +#define USART_WordLength_8b ((u16)0x0000) +#define USART_WordLength_9b ((u16)0x1000) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ + ((LENGTH) == USART_WordLength_9b)) + +/* USART Stop Bits -----------------------------------------------------------*/ +#define USART_StopBits_1 ((u16)0x0000) +#define USART_StopBits_0_5 ((u16)0x1000) +#define USART_StopBits_2 ((u16)0x2000) +#define USART_StopBits_1_5 ((u16)0x3000) + +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ + ((STOPBITS) == USART_StopBits_0_5) || \ + ((STOPBITS) == USART_StopBits_2) || \ + ((STOPBITS) == USART_StopBits_1_5)) +/* USART Parity --------------------------------------------------------------*/ +#define USART_Parity_No ((u16)0x0000) +#define USART_Parity_Even ((u16)0x0400) +#define USART_Parity_Odd ((u16)0x0600) + +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ + ((PARITY) == USART_Parity_Even) || \ + ((PARITY) == USART_Parity_Odd)) + +/* USART Mode ----------------------------------------------------------------*/ +#define USART_Mode_Rx ((u16)0x0004) +#define USART_Mode_Tx ((u16)0x0008) + +#define IS_USART_MODE(MODE) ((((MODE) & (u16)0xFFF3) == 0x00) && ((MODE) != (u16)0x00)) + +/* USART Hardware Flow Control -----------------------------------------------*/ +#define USART_HardwareFlowControl_None ((u16)0x0000) +#define USART_HardwareFlowControl_RTS ((u16)0x0100) +#define USART_HardwareFlowControl_CTS ((u16)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((u16)0x0300) + +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == USART_HardwareFlowControl_None) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS) || \ + ((CONTROL) == USART_HardwareFlowControl_CTS) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) + +#define IS_USART_PERIPH_HFC(PERIPH, HFC) ((((*(u32*)&(PERIPH)) != UART4_BASE) && \ + ((*(u32*)&(PERIPH)) != UART5_BASE)) \ + || ((HFC) == USART_HardwareFlowControl_None)) + +/* USART Clock ---------------------------------------------------------------*/ +#define USART_Clock_Disable ((u16)0x0000) +#define USART_Clock_Enable ((u16)0x0800) + +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ + ((CLOCK) == USART_Clock_Enable)) + +/* USART Clock Polarity ------------------------------------------------------*/ +#define USART_CPOL_Low ((u16)0x0000) +#define USART_CPOL_High ((u16)0x0400) + +#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) + +/* USART Clock Phase ---------------------------------------------------------*/ +#define USART_CPHA_1Edge ((u16)0x0000) +#define USART_CPHA_2Edge ((u16)0x0200) +#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) + +/* USART Last Bit ------------------------------------------------------------*/ +#define USART_LastBit_Disable ((u16)0x0000) +#define USART_LastBit_Enable ((u16)0x0100) + +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ + ((LASTBIT) == USART_LastBit_Enable)) + +/* USART Interrupt definition ------------------------------------------------*/ +#define USART_IT_PE ((u16)0x0028) +#define USART_IT_TXE ((u16)0x0727) +#define USART_IT_TC ((u16)0x0626) +#define USART_IT_RXNE ((u16)0x0525) +#define USART_IT_IDLE ((u16)0x0424) +#define USART_IT_LBD ((u16)0x0846) +#define USART_IT_CTS ((u16)0x096A) +#define USART_IT_ERR ((u16)0x0060) +#define USART_IT_ORE ((u16)0x0360) +#define USART_IT_NE ((u16)0x0260) +#define USART_IT_FE ((u16)0x0160) + +#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) + +#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ + ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) + +#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) + +#define IS_USART_PERIPH_IT(PERIPH, USART_IT) ((((*(u32*)&(PERIPH)) != UART4_BASE) && \ + ((*(u32*)&(PERIPH)) != UART5_BASE)) \ + || ((USART_IT) != USART_IT_CTS)) + +/* USART DMA Requests --------------------------------------------------------*/ +#define USART_DMAReq_Tx ((u16)0x0080) +#define USART_DMAReq_Rx ((u16)0x0040) + +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (u16)0xFF3F) == 0x00) && ((DMAREQ) != (u16)0x00)) + +/* USART WakeUp methods ------------------------------------------------------*/ +#define USART_WakeUp_IdleLine ((u16)0x0000) +#define USART_WakeUp_AddressMark ((u16)0x0800) + +#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ + ((WAKEUP) == USART_WakeUp_AddressMark)) + +/* USART LIN Break Detection Length ------------------------------------------*/ +#define USART_LINBreakDetectLength_10b ((u16)0x0000) +#define USART_LINBreakDetectLength_11b ((u16)0x0020) + +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ + (((LENGTH) == USART_LINBreakDetectLength_10b) || \ + ((LENGTH) == USART_LINBreakDetectLength_11b)) + +/* USART IrDA Low Power ------------------------------------------------------*/ +#define USART_IrDAMode_LowPower ((u16)0x0004) +#define USART_IrDAMode_Normal ((u16)0x0000) + +#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ + ((MODE) == USART_IrDAMode_Normal)) + +/* USART Flags ---------------------------------------------------------------*/ +#define USART_FLAG_CTS ((u16)0x0200) +#define USART_FLAG_LBD ((u16)0x0100) +#define USART_FLAG_TXE ((u16)0x0080) +#define USART_FLAG_TC ((u16)0x0040) +#define USART_FLAG_RXNE ((u16)0x0020) +#define USART_FLAG_IDLE ((u16)0x0010) +#define USART_FLAG_ORE ((u16)0x0008) +#define USART_FLAG_NE ((u16)0x0004) +#define USART_FLAG_FE ((u16)0x0002) +#define USART_FLAG_PE ((u16)0x0001) + +#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ + ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ + ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ + ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ + ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (u16)0xFC9F) == 0x00) && ((FLAG) != (u16)0x00)) + +#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(u32*)&(PERIPH)) != UART4_BASE) &&\ + ((*(u32*)&(PERIPH)) != UART5_BASE)) \ + || ((USART_FLAG) != USART_FLAG_CTS)) + +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) +#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) +#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void USART_DeInit(USART_TypeDef* USARTx); +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address); +void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef* USARTx, u16 Data); +u16 USART_ReceiveData(USART_TypeDef* USARTx); +void USART_SendBreak(USART_TypeDef* USARTx); +void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT); + +#endif /* __STM32F10x_USART_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/Files.c b/Files.c new file mode 100644 index 0000000..9256ec6 --- /dev/null +++ b/Files.c @@ -0,0 +1,1480 @@ +/********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ******************** + File Name : File.c + Version : DS203_APP Ver 2.5x Author : bure +*******************************************************************************/ +#include +#include "Function.h" +#include "Process.h" +#include "BIOS.h" +#include "File.h" +#include "Menu.h" +#include "Calibrat.h" +#include "Interrupt.h" + +u16 SectorSize = 0; +u8 flash_mode = 0; +u8 SecBuff[LARGEST_SECTOR_SIZE]; +uc8 DiskDevInfo_8M[]={"8MB Internal"}; +void Print_Clk(u8 Phase); +u8 OverWriteWarn(void); +void ProcessConfigName(void); +void FileMessage(u8 i); +u8 WriteFileSec(u8* SecBuff, u16* pCluster, u32* pDirAddr); +s32 CSVdata(u8 Ch,u8 Inv,u16 i,u8 data); +u8 CSVdataModeLogic(void); + +u8 SaveShortBuffXpos; +u8 FileBuff[1600]; +u16 TempPar[74]; +u8 Versions; +u16 ArbtSampleNumber; +u32 UartFileSize=0; +char Label[15][13]; +char Ext[4]={'C','F','G',0}; +u16 DirRange=0; +char SelectedFileName[9]; +char ConfigFileName[9]; +char LastAccessedConfig[9]={32,32,32,32,32,32,32,32,0}; +u8 Edited=0; +u8 BufferRestore=0; +u32 RootStart=0x00004000; +u32 RootStop =0x00007F00; +uc32 FatStart=0x00001000; +u16 CSVposition; + +const char Offset[5]= {" Os="}; + +const char SPeriod[7]= {" PER="}; +const char Sampling[4][14]={ {" ChA: VOLTS"},{" ChB: VOLTS"},{" ChC: 0= "},{" ChD: 0= "} }; +const char OSsampling[4][14]={ {" ChA:HI VOLTS"},{" ChA:LO VOLTS"},{" ChB:HI VOLTS"},{" ChB:LO VOLTS"} }; + +const char SamplingPeriod[22][8]={ {"33.333mS"},{"16.667mS"},{"6.6667mS"},{"3.3333mS"},{"1.6667mS"},{"666.67uS"},{"333.33uS"}, + {"166.67uS"},{"66.667uS"},{"33.333uS"},{"16.667uS"},{"6.6667uS"},{"3.3333uS"},{"1.6667uS"}, + {"666.67nS"},{"333.33nS"},{"166.67nS"},{"69.444nS"},{"41.667nS"},{"27.778nS"},{"13.889nS"}, + {"13.889nS"} }; + +const char SubSamplingPeriod[13][8]= { {"3.3333mS"},{"6.6667mS"},{"16.667mS"},{"33.333mS"},{"66.667mS"},{"166.7mS"},{"333.33mS"}, + {"500.00mS"},{"1.0000 S"},{"2.0000 S"},{"4.0000 S"},{"10.000 S"},{"20.000 S"} }; + +const char DigSampling[4][12]={ {" ChA X "},{" ChB X "},{" ChC +20=1"},{" ChD +20=1"} }; +const char AmplitudeSteps[8][6]= { {"2.00mV"},{"4.00mV"},{"8.00mV"},{"20.0mV"},{"40.0mV"},{"80.0mV"},{"200 mV"},{"400 mV"} }; +const char AmplitudeX10Steps[8][6]= { {"20.0mV"},{"40.0mV"},{"80.0mV"},{"200 mV"},{"400 mV"},{"800 mV"},{"2.00 V"},{"4.00 V"} }; + +const char ErrorCode[5][6]={" OK "," FULL"," NONE"," ERR"," CNCL"}; + +const char Clk[4][2]={"|","/","-","$"}; + +uc16 BMP_Color[16] = { WHT, CYAN, CYAN_, YEL, YEL_, PURPL, PURPL_, GRN, //for 16 color BMP's + GRN_, GRAY, ORANGE, BLUE, RED, BLACK, 0x87F0, 0x7BEF}; + + //16 color BMP file header +uc8 BmpHead16[54] = { 0X42, 0X4D, 0XF8, 0XBB, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X76, 0X0, 0X00, 0X00, 0X28, 0X00, + 0X00, 0X00, 0X90, 0X01, 0X00, 0X00, 0XF0, 0X00, 0X00, 0X00, 0X01, 0X0, 0X04, 0X00, 0X00, 0X00, + 0X00, 0X00, 0X82, 0XBB, 0X00, 0X00, 0X12, 0X0B, 0X00, 0X00, 0X12, 0XB, 0X00, 0X00, 0X10, 0X00, + 0X00, 0X00, 0X00, 0X00, 0X00, 0X00}; + //byte 28= 0x04 bits/pixel + //64K color BMP file header +uc8 BmpHead64[66] = { 0X42, 0X4D, 0X42, 0XEE, 0X02, 0X00, 0X00, 0X00, 0X00, 0X00, 0X42, 0X0, 0X00, 0X00, 0X28, 0X00, + 0X00, 0X00, 0X90, 0X01, 0X00, 0X00, 0XF0, 0X00, 0X00, 0X00, 0X01, 0X0, 0X10, 0X00, 0X03, 0X00, + 0X00, 0X00, 0X00, 0XEE, 0X02, 0X00, 0X12, 0X0B, 0X00, 0X00, 0X12, 0XB, 0X00, 0X00, 0X00, 0X00, + 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X1F, 0X00, 0X00, 0X00, 0XE0, 0X07,0X00, 0X00, 0X00, 0XF8, + 0X00, 0X00}; + //byte 28= 0x10 bits/pixel + +/******************************************************************************* +Initialize the file system return value: 0x00 = successful +Primarily sets variables for flash_mode and SectorSize +*******************************************************************************/ +u8 InitFileSystem() { + u32 ptr; + u8 Ver[8]; + + if (SectorSize!=0) return 0; + + ptr=__Get(DFUVER); + memcpy(Ver,(u8*)ptr,5); + ptr=(Ver[1]-'0')*100 +(Ver[3]-'0')*10 +(Ver[4]-'0'); + if(ptr<=311){ + flash_mode=FLASH_2M; + SectorSize = FLASH_2M_SECTOR_SIZE; + } + else{ + ptr=__Get(DEVICEINFO); + if(memcmp((u8*)ptr,DiskDevInfo_8M,3)==0){ + flash_mode=FLASH_8M; + SectorSize = FLASH_8M_SECTOR_SIZE; + } + else { + flash_mode=FLASH_2M; + SectorSize = FLASH_2M_SECTOR_SIZE; + } + } + if (SectorSize>LARGEST_SECTOR_SIZE) { //This should never happen + SectorSize = 0; + return 255; + } + + if(flash_mode==FLASH_2M){ //root dir starting/ending addresses + RootStart=0x00004000; + RootStop =0x00007F00; + }else{ + RootStart=0x00003000; + RootStop =0x00006F00; + } + + return 0; + } + + +/******************************************************************************* + Print_Clk: progress indicator +*******************************************************************************/ +void Print_Clk(u8 Phase) +{ + if((AutoSaveBuf==0)||(ChartLogic()==0))Print_Str(250,0,0x0405,INV,(char*)Clk[Phase]); +} + +/******************************************************************************* +Open the specified file extension input: The file extension return value: 0x00 = successful +*******************************************************************************/ +u8 Make_Filename(u8 FileNum, char* FileName) +{ + char Num[4]; + + u8ToDec3(Num, FileNum,0); + FileName[4] = Num[0]; + FileName[5] = Num[1]; + FileName[6] = Num[2]; + return InitFileSystem(); +} +/******************************************************************************* +Obtained corresponds to the current color palette number +*******************************************************************************/ +u8 Color_Num(u16 Color) //for 16 color BMP's +{ + if(Color == WHT) return 0; +//else if(Color== CYAN ) return 1; + else if((Color== CYAN)||(Color==0xEF60)||(Color==0xF7A0)) return 1; +//else if(Color== YEL ) return 3; + else if((Color== YEL) ||(Color==0x077D)||(Color==0x07BE)) return 3; + else if(Color== PURPL ) return 5; + else if(Color== GRN ) return 7; +//else if(Color== CYAN_ ) return 2; + else if((Color==CYAN_)||(Color==0xDEE0))return 2; //include alt fast dims +//else if(Color== YEL_ ) return 4; + else if((Color== YEL_)||(Color==0x06FB))return 4; + else if(Color== PURPL_) return 6; + else if(Color== GRN_ ) return 8; + else if(Color== GRAY ) return 9; + else if(Color== ORANGE) return 10; + else if(Color== BLUE ) return 11; + else if(Color== RED ) return 12; + //else return 13; + else if(Color== BLACK ) return 13; //add black as viable color so background saves properly + else if(Color== 0x87F0) return 14; //bright green used in serial decoding hex values and arrows added + else if(Color== 0x7BEF) return 15; //dark gray for i2c arrows + else return 9; //anything else would be grid background mixed with something so show grid, not black holes +} + +u8 Save_Img(void){ + + u32 i; + u16 j=0,k=0; + char ChkSum=0,RChkSum=0; + u16 pCluster[3]; + u32 pDirAddr[1]; + if (InitFileSystem()!=0) return 10; //does not use make_filename so may not be initiated + + if(__OpenFileWr(SecBuff,"ROM_IMG BIN", pCluster, pDirAddr)!=OK) return DISK_ERR; + for(i=0;i<0x80000;i++){ //SecBuff here will be either 512 or 4096 + SecBuff[j]=*(char*)(0x8000000+i); + ChkSum^=SecBuff[j]; + if(++j>=SectorSize){ + j=WriteFileSec(SecBuff, pCluster, pDirAddr); + if(j)return j; + j=0; + Print_Clk((k++>>1)& 3); // progress indication + } + } + if(__CloseFile(SecBuff,0x80000,pCluster,pDirAddr)!= OK) return WR_ERR; + + i=__OpenFileRd(SecBuff,"ROM_IMG BIN",pCluster,pDirAddr); //check file for checksum + if(i != OK) return i; + j=0; + for(i=0;i<0x80000;i++){ + if((j>=SectorSize)||(j==0)){ + j=0; + if(__ReadFileSec(SecBuff,pCluster)!= OK) return RD_ERR; + Print_Clk((k++>>1)& 3); // progress indication + } + RChkSum^=SecBuff[j++]; + } + if(RChkSum!=ChkSum)return WR_ERR; + return 0; + +} + +/******************************************************************************* +Load_Dat: Load the saved screen image of the original data input: The file number return value: 0x00 = successful +*******************************************************************************/ +u8 Load_Dat(u8 FileNum) +{ + char Filename[12] = "FILE DAT"; + u16 i; + u16 pCluster[3]; + u32 pDirAddr[1]; + + if ((Current==9)&&(_Det==3)){ + for(i=0;i<8;i++)Filename[i]=SelectedFileName[i]; + }else{ + if (Make_Filename(FileNum, Filename)!=0) return 1; + } + + i = __OpenFileRd(SecBuff, Filename, pCluster, pDirAddr); + if(i != OK) return i; + + if(flash_mode==FLASH_2M){ + for(i=0; i<4; i++){ + if(__ReadFileSec(SecBuff, pCluster)!= OK) return RD_ERR; + memcpy(&FileBuff[i*400], SecBuff,400); + } + } + else{ + if(__ReadFileSec(SecBuff, pCluster)!= OK) return RD_ERR; + for(i=0; i<4; i++) + memcpy(&FileBuff[i*400], &SecBuff[i*512],400); + } + + return 0; +} +/******************************************************************************* +Save_Dat: save current screen to display the original image data input: the file number return value: 0x00 = success +*******************************************************************************/ +u8 Save_Dat(u8 FileNum) +{ + char Filename[13] = "FILE DAT"; + u16 i, j; + u16 pCluster[3]; + u32 pDirAddr[1]; + + if ((Current==9)&&(_Det==3)){ + for(i=0;i<8;i++)Filename[i]=SelectedFileName[i]; + }else{ + if (Make_Filename(FileNum, Filename)!=0) return 1; + } + + if(__OpenFileWr(SecBuff, Filename, pCluster, pDirAddr)!=OK) return DISK_ERR; + + memset(SecBuff, 0, LARGEST_SECTOR_SIZE);//512 + + if(flash_mode==FLASH_8M){ + for(j=0; j<4; j++){ + for(i=0; i<397; i++) SecBuff[i+j*512] = TrackBuff[i*4 + j]; + SecBuff[397+j*512] = Title[j][POSI].Value; + } + i=WriteFileSec(SecBuff, pCluster, pDirAddr); + if(i)return i; + Print_Clk(j & 3); // progress indication + } + else + { + for(j=0; j<4; j++){ + for(i=0; i<397; i++) SecBuff[i]= TrackBuff[i*4 + j]; + SecBuff[397] = Title[j][POSI].Value; + i=WriteFileSec(SecBuff, pCluster, pDirAddr); + if(i)return i; + Print_Clk(j & 3); // progress indication + } + } + + if(__CloseFile(SecBuff, 0x0800, pCluster, pDirAddr)!= OK) return WR_ERR; + return OK; +} +/******************************************************************************* +Save_Bmp: save the current screen image as BMP input: file number return value: 0x00 = successful +*******************************************************************************/ +u8 Save_Bmp(u8 FileNum) +{ + u32 FileSize; + char Filename[12] = "IMAG BMP"; + u16 k, i,x=0, y=0, j, ColorH, ColorL; //, tmp; // j, ColorH, ColorL; + register u16 tmp; + u16 pCluster[3]; + u32 pDirAddr[1]; + + if ((Current==9)&&(_Det==3)){ + for(i=0;i<8;i++)Filename[i]=SelectedFileName[i]; + }else{ + if (Make_Filename(FileNum, Filename)!=0) return 1; + } + + if(__OpenFileRd(SecBuff, Filename, pCluster, pDirAddr)==0){ // original file exists + if(OverWriteWarn())return 200; + if(DeleteFile(SecBuff,Filename))return WR_ERR; + } + + if(__OpenFileWr(SecBuff, Filename, pCluster, pDirAddr)!=OK) return DISK_ERR; + +if((_4_source==10)||(_4_source==11)){ //only save in 64K color if displaying spectrograph or map + memcpy(SecBuff, BmpHead64, 66); //64K COLOR BMP + i = 0x0042; // the image data stored address + k = 0; + for(y=0; y<240; y++){ + for(x=0; x<400 ; x++){ + __Point_SCR(x, y); + tmp =__LCD_GetPixl(); + SecBuff[i++]=tmp&0xFF; SecBuff[i++]=tmp>>8; + if(i>=SectorSize){ //512 + i=WriteFileSec(SecBuff, pCluster, pDirAddr); + if(i)return i; + Print_Clk((k++ >>1)& 3); // progress indicator + i=0; + } + } + } + FileSize=0x2F000; +}else{ + memcpy(SecBuff, BmpHead16, 54); //16 COLOR BMP + i = 0x0036; // palette to store the starting address + for(j=0; j<16; ++j){ + SecBuff[j*4 +i+0]=(BMP_Color[j]& 0xF800)>>8; // Blue + SecBuff[j*4 +i+1]=(BMP_Color[j]& 0x07E0)>>3; // Green + SecBuff[j*4 +i+2]=(BMP_Color[j]& 0x001F)<<3; // Red + SecBuff[j*4 +i+3]= 0; // Alpha + } + i = 0x0076; // the image data stored address + k = 0; + for(y=0; y<240; y++){ + for(x=0; x<400 ; x+=2){ + __Point_SCR(x, y); + ColorH =__LCD_GetPixl(); + __Point_SCR(x+1, y); + ColorL =__LCD_GetPixl(); + SecBuff[i] =(Color_Num(ColorH)<<4)+ Color_Num(ColorL); + i++; + if(i>=SectorSize){ + i=WriteFileSec(SecBuff, pCluster, pDirAddr); + if(i)return i; + Print_Clk((k++ >>1)& 3); // progress indicator + i=0; + } + } + } + FileSize=0xBC00; +} + if(i!=0){ + i=WriteFileSec(SecBuff, pCluster, pDirAddr); + if(i)return i; + } + + if(__CloseFile(SecBuff, FileSize, pCluster, pDirAddr)!= OK) return WR_ERR; //2nd var just seems to be size stamp, alterbios + return 0; //does not seem to care +} + +u8 Load_Bmp(u8 FileNum){ + u8 i,y,start,FinishFactor; + u16 j,h,x; + char Filename[13] = "IMAG BMP"; + + u16 pCluster[3]; + u32 pDirAddr[1]; + + if ((Current==9)&&(_Det==3)){ + for(i=0;i<8;i++)Filename[i]=SelectedFileName[i]; + }else{ + if (Make_Filename(FileNum, Filename)!=0) return 1; + } + + i = __OpenFileRd(SecBuff, Filename, pCluster, pDirAddr); + if(i != OK) return i; + if(__ReadFileSec(SecBuff, pCluster)!= OK) return RD_ERR; + + if(flash_mode==FLASH_8M)FinishFactor=8; else FinishFactor=1; + + if(SecBuff[28]==16){ //if file is 64k color type + x=0; + y=0; + for(h=0; h<(376/FinishFactor); h++){ + if(h==0)start=66;else start=0; + for(j=start;j<(512*FinishFactor);j+=2){ + __Point_SCR(x,y); + __LCD_SetPixl(((u16)(SecBuff[j+1]<<8))|SecBuff[j]); + if(x<399)x++;else {x=0;y++;} + if((x>=399)&&(y>=239))goto EndOfFile; + } + if(__ReadFileSec(SecBuff, pCluster)!= OK) return RD_ERR; + } + }else if(SecBuff[28]==4){ //16 color type + x=0; + y=0; + for(h=0; h<(96/FinishFactor); h++){ + if(h==0)start=0x0076;else start=0; + for(j=start;j<(512*FinishFactor);j++){ + __Point_SCR(x,y); + __LCD_SetPixl(BMP_Color[SecBuff[j]>>4]); + __Point_SCR(x+1,y); + __LCD_SetPixl(BMP_Color[SecBuff[j]&0x0F]); + if(x<398)x+=2;else {x=0;y++;} + if((x>=398)&&(y>=239))goto EndOfFile; + } + if(__ReadFileSec(SecBuff, pCluster)!= OK) return RD_ERR; + } + } + +EndOfFile: + return 0; +} + + +/******************************************************************************* +Save_Buf: save the data collection buffer in BUF format input: file number return value: 0x00 = successful +*******************************************************************************/ +u8 Save_Buf(u8 FileNum) +{ + u8 i; + u16 j; + char Filename[12] = "DATA BUF"; + u16* p ; + + u16 pCluster[3]; + u32 pDirAddr[1]; + + if ((Current==9)&&(_Det==3)){ + for(i=0;i<8;i++)Filename[i]=SelectedFileName[i]; + }else{ + if (Make_Filename(FileNum, Filename)!=0) return 1; + } + + if(__OpenFileRd(SecBuff, Filename, pCluster, pDirAddr)==0){ // original file exists + if((AutoSaveBuf==0)||(ChartLogic()==0)){ + if(OverWriteWarn())return 200; + } + if(DeleteFile(SecBuff,Filename))return WR_ERR; + } + if(__OpenFileWr(SecBuff, Filename, pCluster, pDirAddr)!=OK) return DISK_ERR; + + if(OSBufferLogic()){ //store OS data in unused part of DataBuf + for(i=0;i<2;i++){ + for(j=512;j<1024;j++){ + DataBuf[j+(i*512)]&=0x00FFFFFF; + DataBuf[j+(i*512)]|=(u32)OsFFTData[i][j-512]<<24; + } + } + for(i=0;i<2;i++){ + for(j=1536;j<2048;j++){ + DataBuf[j+(i*512)]&=0x00FFFFFF; + DataBuf[j+(i*512)]|=(u32)RMSdata[i][j-1536]<<24; + } + } + } + + for(i=0; i<(BUFFER_SIZE/SectorSize); i++){ // < 16384/ 512 or 4096 = 32 or 4 + memcpy(SecBuff, &(DataBuf[i*SectorSize/4]), SectorSize); + j=WriteFileSec(SecBuff, pCluster, pDirAddr); + if(j)return j; + Print_Clk((i >>1)& 3); // progress indication + } + memset(SecBuff, 0, 512); + p =(u16*)SecBuff; + for(i=0; i<4; i++){ // save each corresponding value in the display menu + *p++ = Title[i][0].Value; + *p++ = Title[i][1].Value; + *p++ = Title[i][2].Value; + *p++ = Title[i][3].Value; + } + *p++ = Title[6][0].Value; + *p++ = Title[6][1].Value; + + *p++ = 0x00FF & Ka1[_A_Range]; + *p++ = Ka2[_A_Range]; + *p++ = 0x00FF & Kb1[_B_Range]; + *p++ = Kb2[_B_Range]; + *p++ = OSBuffer; + *p++ = FlagFrameMode; + *p++ = OSAvg; + *p++ = SubIndex; + + *p++ = Title[7][0].Value; + *p++ = Title[7][1].Value; + *p++ = ChartMode; + *p++ = FPGAosFlag; + + i=WriteFileSec(SecBuff, pCluster, pDirAddr); + if(i)return i; + + if(__CloseFile(SecBuff, 0x4200, pCluster, pDirAddr)!= OK) return WR_ERR; + return 0; +} + + +u8 WriteFileSec(u8* SecBuff, u16* pCluster, u32* pDirAddr){ + if(*pCluster>2040){ //if trying to write beyond the end of the drive + __CloseFile(SecBuff, 0, pCluster, pDirAddr); //will result in a 0 length file and use up space, but at least will + return OVER; //not destroy the file allocation table by looping around + }else{ + if(__ProgFileSec(SecBuff, pCluster)!= OK) return WR_ERR; + } + return 0; +} + + + +u8 Load_Arbt(u8 FileNum){ + u8 *p; + u16 i,Sample=0; + u8 Tmp,j=0,Start=0; + char ParseStr[6]; + u16 pCluster[3]; + u32 pDirAddr[1]; + char Filename[12] = "DATA ARB"; + + if ((Current==9)&&(_Det==3)){ + for(i=0;i<8;i++)Filename[i]=SelectedFileName[i]; + }else{ + if (Make_Filename(FileNum, Filename)!=0) return 1; + } + + i = __OpenFileRd(SecBuff, Filename, pCluster, pDirAddr); + if(i != OK) return i; + if(__ReadFileSec(SecBuff, pCluster)!= OK) return RD_ERR; + p=(u8*)SecBuff; + + while(*p==48){p++;Start++;} //strip off any leading 0's + while(*p!=44){ + if((*p>47)&&(*p<58))ParseStr[j++]=*p++;else p++; //retrieve "header" containing number of samples to be used + Start++; + if((j>3)||(Start>200))return 1; //return ERR if samples >3 digits or comma not found after 200 chars + } //break out and continue once comma delimiter is found + p++; //move past delimiter + ArbtSampleNumber=AsciiToU16(ParseStr,j); + j=0; + if((ArbtSampleNumber<2)||(ArbtSampleNumber>720)) //return ERR if number of samples out of range + {ArbtSampleNumber=0;return 1;} + + while(Sample<720){ + + for(i=Start;i4095)ATT_DATA[Sample]=4095; //clip if out of range + j=0; Sample++; //reset string position counter and advance sample position + }else{ //start loading string here + if((Tmp>47)&&(Tmp<58))ParseStr[j++]=Tmp; //eliminate white space or other non relevant chars + if(j>4)j=4; //limit to 5 valid characters + } + + if(Sample>(ArbtSampleNumber-1))goto EndOfFile; //if sample goes to ArbtSampleNmber, is now past base 0 sample number index + + }//for(i=Start + + Start=0; + if(__ReadFileSec(SecBuff, pCluster)!= OK) return RD_ERR; + p=(u8*)SecBuff; + + } + +EndOfFile: + return 0; +} + +u8 ReadDir(char *ext){ //Load 10 filenames matching extension in Label, starting with match # DirRange + u16 n,EntryCounter=0; + u8 i; + u32 pDirAddr[1]; + u8 pBuffer[266]; + u8 LabelIndex=0; + + for(n=0;n<15;n++){ + for(i=0;i<13;i++)Label[n][i]=0; + } + + for(*pDirAddr=RootStart; *pDirAddr=DirRange){ //start offset for next files + for(i=0;i<8;i++)Label[LabelIndex][i]=pBuffer[n+i]; //copy first 8 chars of filename + Label[LabelIndex][8]=0x2E; //"." + for(i=0;i<3;i++)Label[LabelIndex][9+i]=ext[i]; //extension + LabelIndex++; + } + EntryCounter++; + } + if(LabelIndex>=15)return LabelIndex; //list is full + *pDirAddr += 32; + } + } + return LabelIndex; +} + +u8 DeleteFile(u8* pBuffer, char* FileName){ + u32 pDirAddr[1]; + u16 pCluster[1]; + u16 i=0,n,Offset; + + for(*pDirAddr=RootStart; *pDirAddr=3072)return RD_ERR; + if(i++>2048)return RD_ERR; //all good things MUST come to an end + + if(*pCluster&1){ + *pCluster=pBuffer[Offset+1]; //Most Significant byte, save value pointing to next link before zeroing + *pCluster=(*pCluster<<4)+(pBuffer[Offset]>>4); //Shift to proper position and add little endian nibble + pBuffer[Offset]&=0x0F; //zero, to release link + pBuffer[Offset+1]=0; + }else{ + *pCluster=pBuffer[Offset+1]&0x0F; //Construct 12 bit entry within proper 2 bytes of double entry "triplet", + *pCluster=(*pCluster<<8)+pBuffer[Offset]; //depending on whether the entry number is odd or even.(Convolutions + pBuffer[Offset]=0; //courtesy of Microsoft et al. who just HAD to pack a 12 bit entry into + pBuffer[Offset+1]&=0xF0; //1.5 bytes instead of 2, thus saving a small fraction of 1% of drive + } //space on a typical floppy; bytes were precious in the age of floppies...) + }while(*pCluster<0xFF0); + if(__ProgDiskPage(pBuffer,FatStart)!=0)return WR_ERR; //write section back to disk + //synch FAT2 with FAT1 + if(__ReadDiskData(pBuffer,0x1000,0x1000)!= OK) return RD_ERR; + if(__ProgDiskPage(pBuffer,0x2000)!= OK) return WR_ERR; + + if(*pCluster<0xFF0)return RD_ERR; //end of file to be deleted not found, return error + return 0; +} + +void FileMessage(u8 i){ + + if((i==3)||(i==4))i-=2; else{ + if(i==200)i=4;else if(i>0)i=3; + } + Print_Str(230, 0,0x050A, PRN,(char*)ErrorCode[i]); + if((_Curr[2].Value==BUF)&&(_Curr[0].Value == LOAD))Delayms(300);else Delayms(900); + _Curr[1].Flag |= UPDAT; + _Curr[2].Flag |= UPDAT; +} + +u8 Load_Uart(u8 FileNum){ + u16 n=0; + u8 i; + u16 pCluster[3]; + u32 pDirAddr[1]; + u8 pBuffer[266]; + char Filename[12] = "DATA UAR"; + UartFileSize=0; + + if ((Current==9)&&(_Det==3)){ + for(i=0;i<8;i++)Filename[i]=SelectedFileName[i]; + }else{ + if (Make_Filename(FileNum, Filename)!=0) return 1; + } + i = __OpenFileRd(SecBuff, Filename, pCluster, pDirAddr); + if(i != OK) return i; + + for(*pDirAddr=RootStart; *pDirAddr4096)UartFileSize=4096; //limit to size of SecBuff + n=0; + while(n1)ChartMode=0; + if(FPGAosFlag>1)FPGAosFlag=0; + + if(Title[3][0].Value < 11){ //set proper menu sub items for ch 4 + if(Detail[3]==2)Detail[3]++; + }else{ + if(Detail[3]==3)Detail[3]--; + } + + if(OSBufferLogic()){ //restore OS data + for(i=0;i<2;i++){ + for(h=512;h<1024;h++){ + OsFFTData[i][h-512]=DataBuf[h+(i*512)]>>24; + } + } + for(i=0;i<2;i++){ + for(h=1536;h<2048;h++){ + RMSdata[i][h-1536]=DataBuf[h+(i*512)]>>24; + } + } + } + + Title[RUNNING][STATE].Value = 2; // set to "HOLD" status + Title[RUNNING][STATE].Flag |= UPDAT; // set the update flag + XposRef=GetXposRef(_X_posi.Value); + UpdateFileMenu(); + BufferRestore=1; + return 0; +} + +void save_parameter(void){ +u16 *p; +u8 i,j; + + if(TempPar[0]!=0xAA55){ //do not save temp parameters again if already saved, indicates original parms not restored + p = TempPar; //and BUF parameters still active from previous BUF load(s) + *p++ = 0xAA55; + for(i=0; i<4; i++){ // save each corresponding value in the display menu + for(j=0;j<4;j++)*p++ = Title[i][j].Value; + } + *p++ = Title[6][0].Value; + *p++ = Title[6][1].Value; + for(i=0; i<8; i++){ + *p++ = 0x00FF & Ka1[i]; + *p++ = Ka2[i]; + *p++ = 0x00FF & Kb1[i]; + *p++ = Kb2[i]; + } + *p++ = OSBuffer; + *p++ = FlagFrameMode; + *p++ = OSAvg; + *p++ = Title[6][2].Value; //xpos + *p++ = SubIndex; + + *p++ = Title[7][0].Value; + *p++ = Title[7][1].Value; + *p++ = Detail[3]; //sub menu position of ch 4 + *p++ = ChartMode; + *p++ = FPGAosFlag; + } + +} + + +void reset_parameter(void) +{ + u16* p; + u8 i,j; + + p=TempPar; + p++; + if(TempPar[0]!=0xAA55) return; + for(i=0; i<4; i++){ + for(j=0;j<4;j++){ + Title[i][j].Value = *p++; // restore + Title[i][j].Flag = UPDAT; + } + } + Title[6][0].Value = *p++; + Title[6][1].Value = *p++; + Title[6][0].Flag = UPDAT; + Title[6][1].Flag = UPDAT; + + for(i=0; i<8; i++){ + Ka1[i] = (s8)(*p++ );//& 0xff); + Ka2[i] = (*p++ ); + Kb1[i] = (s8)(*p++);// & 0xff); + Kb2[i] = (*p++); + } + OSBuffer = *p++; + FlagFrameMode = *p++; + OSAvg = *p++; + Title[6][2].Value = *p++; + SubIndex = *p++; + + Title[7][0].Value = *p++; + Title[7][1].Value = *p++; + Title[7][0].Flag = UPDAT; + Title[7][1].Flag = UPDAT; + Title[7][2].Flag = UPDAT; + + Detail[3] = *p++; //sub menu position of ch 4 + ChartMode = *p++; + FPGAosFlag = *p++; + p = TempPar; + *p++ = 0; +} + +u8 CSVdataModeLogic(void){ + return(((OSBufferLogic()==0)&&(DigChLockout==0)&&((!ChartLogic())||(ChartMode==0))) + &&((_3_source)||(_4_source==1)||(_4_source==4)||(_4_source==5)) ); +} + +s32 CSVdata(u8 Ch,u8 Inv,u16 i,u8 data){ +u8 range=Title[Ch][RANGE].Value; +s32 temp; +s8 *p1[2];u16 *p2[2]; +p1[0]=Ka1;p1[1]=Kb1;p2[0]=Ka2;p2[1]=Kb2; + + p1[Ch]+=range;temp=*p1[Ch]+((data-ADCoffset)-Title[Ch][POSI].Value); + p2[Ch]+=range;if(CalFlag>0)temp=(*p2[Ch]*temp)/1024; + temp*= Y_Attr[range].SCALE; + if(Title[Ch][SOURCE].Value>2)temp*=10; + if(Inv)temp=-temp; + return temp; +} + +/******************************************************************************* +Save_Csv: save the acquisition buffer in CSV format input: file number return value: 0x00 = successful +*******************************************************************************/ +u8 Save_Csv(u8 FileNum) +{ + char Num[4][6]; + char Val[4]; + char Filename[12] = "DATA CSV"; + u32 i, k = 0,length = SectorSize; + s32 temp; + u8 count, j,h=1,m=1; + u16 n = 0; + + u16 pCluster[3]; + u32 pDirAddr[1]; + + if ((Current==9)&&(_Det==3)){ + for(i=0;i<8;i++)Filename[i]=SelectedFileName[i]; + }else{ + if (Make_Filename(FileNum, Filename)!=0) return 1; + } + + length = SectorSize; + + if(__OpenFileRd(SecBuff, Filename, pCluster, pDirAddr)==0){ // original file exists + if((AutoSaveBuf==0)||(ChartLogic()==0)){ + if(OverWriteWarn())return 200; + } + if(DeleteFile(SecBuff,Filename))return WR_ERR; + } + if(__OpenFileWr(SecBuff, Filename, pCluster, pDirAddr)!=OK) return DISK_ERR; + +//============================================HEADERS=========================================== + + memcpy(&SecBuff[k],SPeriod,7);k+=7; + if(ChartLogic()){memcpy(&SecBuff[k],SubSamplingPeriod[SubIndex-1],8);k+=8;} + else {memcpy(&SecBuff[k],SamplingPeriod[_T_base],8);k+=8;} + SecBuff[k++]=0x2C; + + for(i=0;i<4;i++){ + + if(CSVdataModeLogic()){ + memcpy(&SecBuff[k],Offset,4);k+=4; + u8ToDec3(Val,Title[i][POSI].Value,0); + memcpy(&SecBuff[k],Val,3);k+=3; + } + if(i<2){ + if(CSVdataModeLogic()){ + memcpy(&SecBuff[k],DigSampling[i],7);k+=7; + if(Title[i][0].Value>2){memcpy(&SecBuff[k],AmplitudeX10Steps[Title[i][RANGE].Value],6);k+=6;} + else {memcpy(&SecBuff[k],AmplitudeSteps[Title[i][RANGE].Value],6);k+=6;} + }else if((OSBufferLogic())||((ChartLogic())&&(ChartMode))){ + memcpy(&SecBuff[k],OSsampling[i],13);k+=13; + }else{ + memcpy(&SecBuff[k],Sampling[i],13);k+=13; + } + }else{ + if(CSVdataModeLogic()){ + memcpy(&SecBuff[k],DigSampling[i],10);k+=10; + }else if((OSBufferLogic())||((ChartLogic())&&(ChartMode))){ + memcpy(&SecBuff[k],OSsampling[i],13);k+=13; + }else{ + SecBuff[k++]=0x2C; + break; + } + } + SecBuff[k++]=0x2C; + } + SecBuff[k++] = 0x0d; + SecBuff[k++] = 0x0a; + + if((OSBufferLogic())&&(!FPGAosFlag)&&(_T_Range==16))m=2; + if(_T_Range>16){ + if(CSVdataModeLogic())h=4;else h=2; + m=2; + }else if((OSBufferLogic())&&(FPGAosFlag))h=2; + if((_T_Range>17)&&(OSBufferLogic()==0)&&(FPGAosFlag==0))h=3; + if(_T_Range>19)h=4; + + for(i=(discard+h); i4)){ //HOURS + for(j=0;j<4;j++){ + if(MinBypass==2){ + if(CursorDisplayStrH[j]>0){ + SecBuff[k++] = CursorDisplayStrH[j]; + }else SecBuff[k++] = 32; + }else SecBuff[k++] = 32; + if(k >= length){ + k=WriteFileSec(SecBuff, pCluster, pDirAddr); + if(k)return k; + Print_Clk((n++ >>1)& 3); // progress indicator + k=0; + } + } + for(j=0;j<4;j++){ //MINUTES + if(MinBypass>0){ + if(CursorDisplayStrM[j]>0){ + SecBuff[k++] = CursorDisplayStrM[j]; + }else SecBuff[k++] = 32; + }else SecBuff[k++] = 32; + if(k >= length){ + k=WriteFileSec(SecBuff, pCluster, pDirAddr); + if(k)return k; + Print_Clk((n++ >>1)& 3); // progress indicator + k=0; + } + } + } + + for(j=0;j<(8+Neg);j++){ //SECONDS + if(CursorDisplayStr[j]>0){ + SecBuff[k++] = CursorDisplayStr[j]; + }else SecBuff[k++] = 32; + if(k >= length){ + k=WriteFileSec(SecBuff, pCluster, pDirAddr); + if(k)return k; + Print_Clk((n++ >>1)& 3); // progress indicator + k=0; + } + } + SecBuff[k++] = 0x2c; + if(k >= length){ + k=WriteFileSec(SecBuff, pCluster, pDirAddr); + if(k)return k; + Print_Clk((n++ >>1)& 3); // progress indicator + k=0; + } + +//============================================DATA=========================================== + //CH A + if(CSVdataModeLogic()){ //direct buffer value copy mode w/digital ch's + temp=Ka1[_A_Range]+((Ka2[_A_Range]*((DataBuf[i] & 0xff)-ADCoffset))+512)/1024; + u8ToDec3(Num[0],temp,0); + temp = Kb1[_B_Range]+((Kb2[_B_Range]*(((DataBuf[i] & 0xff00)>>8)-ADCoffset))+512)/1024; + u8ToDec3(Num[1],temp,0); + temp=Title[TRACK3][POSI].Value; + if((DataBuf[i]&0x010000)!=0)temp+=20; + u8ToDec3(Num[2],temp,0); + temp=Title[TRACK4][POSI].Value; + if((DataBuf[i]&0x020000)!=0)temp+=20; + u8ToDec3(Num[3],temp,0); + }else{ //scaled voltage display mode without digital ch's + S32ToFloat3(Num[0],CSVdata(0,InvertA,i,(DataBuf[i]&0xff))); //CH A is always in same field + if((OSBufferLogic())||((ChartLogic())&&(ChartMode))){ + S32ToFloat3(Num[1],CSVdata(0,InvertA,i,((DataBuf[i]&0xff0000)>>16))); //OS data for chA stored in chC > chB + S32ToFloat3(Num[2],CSVdata(1,InvertB,i,((DataBuf[i]&0xff00)>>8))); //CH B > chC + S32ToFloat3(Num[3],CSVdata(1,InvertB,i,((DataBuf[i]&0xff000000)>>24))); //OS data for chB stored in chD > chD + }else{ + S32ToFloat3(Num[1],CSVdata(1,InvertB,i,((DataBuf[i]&0xff00)>>8))); //CH B + } + } + + for(j=0; j<4; j++){ + if((j>1)&&(!((CSVdataModeLogic())||((OSBufferLogic())||((ChartLogic())&&(ChartMode)))))){ //do not export digital chs if not enabled + SecBuff[k++] = 0x2c; //or if they do not contain OS data + if(k >= length){ + k=WriteFileSec(SecBuff, pCluster, pDirAddr); + if(k)return k; + Print_Clk((n++ >>1)& 3); // progress indicator + k = 0; + } + break; + } + for(count=0; count<6; count++){ + if(Num[j][count] == 0) break; + SecBuff[k++] = Num[j][count]; + if(k >= length){ + k=WriteFileSec(SecBuff, pCluster, pDirAddr); + if(k)return k; + Print_Clk((n++ >>1)& 3); // progress indicator + k = 0; + } + } + SecBuff[k++] = 0x2c; + if(k >= length){ + k=WriteFileSec(SecBuff, pCluster, pDirAddr); + if(k)return k; + Print_Clk((n++ >>1)& 3); // progress indicator + k = 0; + } + } + + if(i<(bag_max_buf-1))SecBuff[k++] = 0x0d; + if(k >= length){ + k=WriteFileSec(SecBuff, pCluster, pDirAddr); + if(k)return k; + Print_Clk((n++ >>1)& 3); // progress indicator + k = 0; + } + if(i<(bag_max_buf-1))SecBuff[k++] = 0x0a; + if(k >= length){ + k=WriteFileSec(SecBuff, pCluster, pDirAddr); + if(k)return k; + Print_Clk((n++ >>1)& 3); // progress indicator + k = 0; + } + } +//==========================================CLOSE FILE=========================================== + + if(k != 0){ + memset(&SecBuff[k],0,(length-k)); + j=WriteFileSec(SecBuff, pCluster, pDirAddr); + if(j)return j; + Print_Clk((n >>1)& 3); // progress indicator + } + if(__CloseFile(SecBuff, (n*length)+k, pCluster, pDirAddr)!= OK) return WR_ERR; + return OK; +} +/******************************************************************************* +Load_Parameter: ¼ÓÔØ֮ǰµÄ¹¤×÷²ÎÊý Return: 0= Success +*******************************************************************************/ +u8 Load_Param(u8 FileNum) +{ + u8 Sum = 0,BootLoad=0; + char Filename[12]="CONF CFG"; + u16 i; + //s8 j; + u16* p =(u16*)SecBuff; + + u16 pCluster[3]; + u32 pDirAddr[1]; + Versions = 0x06; + + if(((Current==9)&&(_Det==3))||(AutoSetFlag)){ + for(i=0;i<8;i++)ConfigFileName[i]=Filename[i]=SelectedFileName[i]; + + ProcessConfigName(); + + ListOverride=1; + }else{ + if(FileNum==0){ + Word2Hex(Filename, __GetDev_SN()); + if (InitFileSystem()!=0) return 1; + Filename[8] = 'W'; Filename[9] = 'P'; Filename[10] = 'T'; + BootLoad=1; + }else Make_Filename(FileNum, Filename); + ListOverride=0; + } + + i = __OpenFileRd(SecBuff, Filename, pCluster, pDirAddr); + if(i != OK) return i; + + if(__ReadFileSec(SecBuff, pCluster)!= OK) return RD_ERR; + + //if((Versions !=(*p & 0xFF))&&((Versions+0x10)!=(*p & 0xFF))) return VER_ERR; // works with either V6 or V 0x16 + if(Versions !=(*p & 0xFF)) return VER_ERR; + Versions=(*p & 0xFF); + + for(i=0; i<512; ++i) Sum += SecBuff[i]; + if(Sum != 0) return SUM_ERR; // checksum error + Current =(*p++ >>8); // restore Current Title + for(i=0; i<7; i++){ + Detail[i*2] = *p; + Detail[i*2+1]= (*p++ >>8); // restore Detail + } + for(i=0; i<13; i++){ + Title[i][0].Value = *p++; //restore each corresponding value in the display menu + Title[i][1].Value = *p++; + Title[i][2].Value = *p++; + Title[i][3].Value = *p++; + } + for(i=0; i<9; i++){ + Meter[i].Item = *p; + Meter[i].Track =(*p++ >>8); // load measurements and the measurement object + } + + if(BootLoad==0){ + for(i=0; i<10; i++){ + Ka1[i] = *p; // restore the original channel A low error correction coefficient + Kb1[i] =(*p++ >>8); // restore the original B-channel low error correction coefficient + Ka2[i] = *p++; // restore the original channel A gain error correction factor + Kb2[i] = *p++; // restore the B-channel gain error correction coefficient + Ka3[i] = *p; // restore the original channel A high error correction coefficient + Kb3[i] =(*p++ >>8); // restore the original B-channel high error correction factor + } + }else{ // do not load correction factors if not loading boot config + p+=40; // allows updating calibration without interference from different configs + } + + + V_Trigg[A].Value = *p++; + V_Trigg[B].Value = *p++; // restore the original A and B channel trigger threshold + FlagFrameMode= *p; + CurDefTime=(*p++ >>8); // CurDefTime w/flagframemode + FlagMeter= *p; + UpdateMeter=(*p++ >>8); // add additional values in a way compatible with original version + TrgAuto=*p; + CalFlag=(*p++ >>8); // add CalFlag + OffsetX=*p; + SaveShortBuffXpos=(*p++ >>8); // add Short Buffer Xpos + OffsetY=*p; + Options=(*p++ >>8); // add Options + + if(BootLoad){ + LoBatLevel[0]=*p++; + LoBatLevel[1]=*p++; + HiBatLevel[0]=*p++; + HiBatLevel[1]=*p++; + for(i=0; i<10; i++){ + LKa1[i] = *p; + LKb1[i] =(*p++ >>8); + LKa2[i] = *p++; + LKb2[i] = *p++; + LKa3[i] = *p; + LKb3[i] =(*p++ >>8); + } + for(i=0; i<10; i++){ + HKa1[i] = *p; + HKb1[i] =(*p++ >>8); + HKa2[i] = *p++; + HKb2[i] = *p++; + HKa3[i] = *p; + HKb3[i] =(*p++ >>8); + } + PPM_Comp = *p++; + }else p+=85; + + PerstFrameNumber = *p++; + Raw = *p++; + PrevShift = *p++; GenFreqShift=PrevShift; + GenAdjustMode = *p++; + + if(BootLoad){ //"system" variable, only load on boot + Sum=*p; + if((*p++>>8)==0xAB)ADCoffset=Sum; else ADCoffset=54; //0xAB "key" assures default of 54 if ADCoffset value not originally saved + }else p++; + + SweepIndex = *p++; + Sweep = *p++; + BurstLimit = *p++; + Det = *p++; + FineAdjust= *p++; + DataSize= *p++; + SpiMode= *p++; + SpiBitOrder= *p++; + SpiNumBits= (s16)*p++; + SpiAdj= *p++; + SubIndex= *p++; + GenBaudIndex= *p++; + GenUartMode= *p++; + GenUartStopBits= *p++; + OSBuffer= *p++; + OSAvg= *p++; + if(BootLoad)FastDim=*p++;else p++; //"system" variable, only load on boot + FreeRunEnable= *p++; + FPGAosFlag= *p++; + if(BootLoad)OS_Range=*p++;else p++; //"system" variable, only load on boot + if(BootLoad)Hbold=*p++;else p++; //"system" variable, only load on boot + ChartMode= *p++; + if(BootLoad)LoBeepLevel=*p++;else p++; //"system" variable, only load on boot + if(BootLoad)DisableCursorDisplay=*p++;else p++; + + + if((GenUartMode<1)||(GenUartMode>6))GenUartMode=3; //default to 8N + if((GenBaudIndex<16)||(GenBaudIndex>15871))GenBaudIndex=7500; + if(SpiNumBits<-145)SpiNumBits=8; //these would flag read errors from possible corrupt config files + if(SpiNumBits>192)SpiNumBits=8; + if(SpiAdj>3)SpiAdj=0; + if(SpiBitOrder>1)SpiBitOrder=0; + if(SpiMode>3)SpiMode=0; + if(SubIndex>13)SubIndex=0; + if(FastDim>3)FastDim=0; + if(OS_Range>5)OS_Range=0; + if(Hbold>2)Hbold=0; + if(LoBeepLevel>9)LoBeepLevel=0; + if(DisableCursorDisplay>3)DisableCursorDisplay=0; + + return OK; +} +/******************************************************************************* + Save_Parameter: save the current operating parameters Return: 0= Success +*******************************************************************************/ +u8 Save_Param(u8 FileNum) // save the operating parameters table +{ + u8 Sum = 0; + char Filename[12]="CONF CFG"; + u16 i, Tmp[2]; + u16* p =(u16*)SecBuff; + u8 transfer; + //u8 MissingFileFlag=1; + + u16 pCluster[3]; + u32 pDirAddr[1]; + if (InitFileSystem()!=0) return 1; + Versions=0x06; + + if (Edited){ + for(i=0;i<8;i++)ConfigFileName[i]=Filename[i]=SelectedFileName[i]; + ProcessConfigName(); + }else{ + if(FileNum==0){ + Word2Hex(Filename, __GetDev_SN()); + Filename[8] = 'W'; Filename[9] = 'P'; Filename[10] = 'T'; + }else Make_Filename(FileNum, Filename); + } + + switch (__OpenFileRd(SecBuff, Filename, pCluster, pDirAddr)){ + case OK: // original WPT file exists + //MissingFileFlag=0; + Tmp[0] = *pCluster; + + + if((FileNum==0)&&(Edited==0)){ + Filename[8] = 'B'; Filename[9] = 'A'; Filename[10] = 'K'; // turn into a BAK file + if(__OpenFileWr(SecBuff, Filename, pCluster, pDirAddr)!= OK) return DISK_ERR; + if(__ReadFileSec(SecBuff, Tmp )!= OK) return RD_ERR; + i=WriteFileSec(SecBuff, pCluster, pDirAddr); + if(i)return i; + if(__CloseFile(SecBuff, 512, pCluster, pDirAddr)!= OK) return WR_ERR;/**/ + }else{ + if(__OpenFileWr(SecBuff, Filename, pCluster, pDirAddr)!= OK) return DISK_ERR; + memset(SecBuff, 0, SectorSize); + if(Edited)goto SkipOpenFileWr; + } + + + case NEW: // original WPT file does not exist + + + if(Edited==0){ + if(FileNum==0){ + Filename[8] = 'W'; Filename[9] = 'P'; Filename[10] = 'T'; // create WPT files + if(__OpenFileWr(SecBuff, Filename, pCluster, pDirAddr)!= OK) return DISK_ERR; + memset(SecBuff, 0, 512); + }//else if((MissingFileFlag==1)&&(flash_mode==FLASH_2M))return WR_ERR; // do not write new additional config files unless they already exist to prevent corruption (only on 2MB drives) + }else{ + if(__OpenFileWr(SecBuff, Filename, pCluster, pDirAddr)!= OK) return DISK_ERR; + memset(SecBuff, 0, SectorSize); + } +SkipOpenFileWr: + + *p++ =(Current <<8)+ Versions; // save the parameter table version number and the current Title + + for(i=0; i<7; i++){ + *p++ =(Detail[i*2+1]<<8)+ Detail[i*2]; // Save the Detail + } + for(i=0; i<13; i++){ // Save display each value of the corresponding item in the menu + *p++ = Title[i][0].Value; + *p++ = Title[i][1].Value; + *p++ = Title[i][2].Value; + *p++ = Title[i][3].Value; + } + for(i=0; i<9; i++){ + *p++ =(Meter[i].Track<<8)+ Meter[i].Item; // Save the measurement items and measurement object + } + for(i=0; i<10; i++){ + transfer=Ka1[i]; //load into unsigned var first, prevents error with added signed CH-A value spilling over into shifted CH-B when negative + *p++ = (Kb1[i]<<8)+ transfer; + *p++ = Ka2[i]; // save the current channel A gain error correction coefficient + *p++ = Kb2[i]; // save the current B-channel gain error correction factor + transfer=Ka3[i]; + *p++ = (Kb3[i]<<8)+ transfer; + } + *p++ = V_Trigg[A].Value; + *p++ = V_Trigg[B].Value; // save the current A and B channels trigger threshold + *p++ = (CurDefTime<<8)+FlagFrameMode; // include Cursor defined selection + *p++ = (UpdateMeter<<8)+FlagMeter; // include meter "page" along with flag + *p++ = (CalFlag<<8)+TrgAuto; // include wave amplitude calibration flag + *p++ = (SaveShortBuffXpos<<8)+OffsetX; // include short buffer xpos + *p++ = (Options<<8)+OffsetY; // include Options + *p++ = LoBatLevel[0]; + *p++ = LoBatLevel[1]; + *p++ = HiBatLevel[0]; + *p++ = HiBatLevel[1]; + for(i=0; i<10; i++){ //save low batt level data + transfer=LKa1[i]; + *p++ = (LKb1[i]<<8)+ transfer; + *p++ = LKa2[i]; + *p++ = LKb2[i]; + transfer=LKa3[i]; + *p++ = (LKb3[i]<<8)+ transfer; + } + for(i=0; i<10; i++){ //save high batt level data + transfer=HKa1[i]; + *p++ = (HKb1[i]<<8)+ transfer; + *p++ = HKa2[i]; + *p++ = HKb2[i]; + transfer=HKa3[i]; + *p++ = (HKb3[i]<<8)+ transfer; + } + *p++ = PPM_Comp; + *p++ = PerstFrameNumber; + *p++ = Raw; + *p++ = GenFreqShift; + *p++ = GenAdjustMode; + *p++ = (0xAB<<8)+ADCoffset; //use 0xAB as id key to insure reload picks up only saved value + *p++ = SweepIndex; + *p++ = Sweep; + *p++ = BurstLimit; + *p++ = Det; + *p++ = FineAdjust; + *p++ = DataSize; + *p++ = SpiMode; + *p++ = SpiBitOrder; + *p++ = SpiNumBits; + *p++ = SpiAdj; + *p++ = SubIndex; + *p++ = GenBaudIndex; + *p++ = GenUartMode; + *p++ = GenUartStopBits; + *p++ = OSBuffer; + *p++ = OSAvg; + *p++ = FastDim; + *p++ = FreeRunEnable; + *p++ = FPGAosFlag; + *p++ = OS_Range; + *p++ = Hbold; + *p++ = ChartMode; + *p++ = LoBeepLevel; + *p++ = DisableCursorDisplay; + + for(i=0; i<511; i++) Sum += SecBuff[i]; // calculate the parameter table checksum + SecBuff[511] = (~Sum)+ 1; + i=WriteFileSec(SecBuff, pCluster, pDirAddr); + if(i)return i; + if(__CloseFile(SecBuff, 512, pCluster, pDirAddr)!= OK) return WR_ERR; + return OK; + default: return WR_ERR; + } +} + +u8 OverWriteWarn(void){ + while(Read_Keys()){} + Print_Str((8*11)+3, 0, 0x0405, PRN, "Warning:File already exists"); + Key_Buffer=0; + while (1){if(Key_Buffer>0)break;} + Update_View_Area(); + _Curr[0].Flag |= UPDAT; + _Curr[1].Flag |= UPDAT; + _Curr[2].Flag |= UPDAT; + Display_Title(); + Print_Str(230, 0, (SCRN<<8)+ TEXT1, PRN, " > "); + if(Key_Buffer!=K_INDEX_S){Key_Buffer=0;return 1;} + return 0; +} + +void ProcessConfigName(void){ +s8 j; +u8 i; + + for(j=7;j>=0;j--){ //remove trailing spaces and underscores for config file display + if((ConfigFileName[j]==32)||(ConfigFileName[j]==95))ConfigFileName[j]=0;else break; + } + for(i=0;i<8;i++)if(ConfigFileName[i]==95)ConfigFileName[i]=32; //change all other underscores to spaces for vertical display + for(i=0;i<8;i++){ + switch(ConfigFileName[i]){ //process unavailable chars to display dot + case 39: //' + case 64: //@ + ConfigFileName[i]=63; + break; + default: + if(((ConfigFileName[i]>32)&&(ConfigFileName[i]<37))||(ConfigFileName[i]>124))ConfigFileName[i]=63; //limit to char array bounds + } + } + +} + +void UpdateFileMenu(void){ +u8 i; + Update_View_Area(); + if(Current==FILE){ + for(i=0;i<3;i++)Title[FILE][i].Flag |= UPDAT; + } +} + +/******************************** END OF FILE *********************************/ + diff --git a/Function.c b/Function.c new file mode 100644 index 0000000..949b10e --- /dev/null +++ b/Function.c @@ -0,0 +1,720 @@ +/********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ******************** + File Name : Function.c + Version : DS203 APP Ver 2.5x Author : bure & Kewei +*******************************************************************************/ +#include "Interrupt.h" +#include "Function.h" +#include "BIOS.h" +#include "Menu.h" +#include "Process.h" +#include "File.h" + +// Since we only use 3/4 of N_WAVE, we define only +// this many samples, in order to conserve data space. + +u8 SetLowVolume=0; +s16 Sinewave[N_WAVE-N_WAVE/4]; + +sc16 SineQuad[129] = { + 0, 402, 804, 1206, 1608, 2009, 2410, 2811, + 3212, 3612, 4011, 4410, 4808, 5205, 5602, 5998, + 6393, 6786, 7179, 7571, 7962, 8351, 8739, 9126, + 9512, 9896, 10278, 10659, 11039, 11417, 11793, 12167, + 12539, 12910, 13279, 13645, 14010, 14372, 14732, 15090, + 15446, 15800, 16151, 16499, 16846, 17189, 17530, 17869, + 18204, 18537, 18868, 19195, 19519, 19841, 20159, 20475, + 20787, 21096, 21403, 21705, 22005, 22301, 22594, 22884, + 23170, 23452, 23731, 24007, 24279, 24547, 24811, 25072, + 25329, 25582, 25832, 26077, 26319, 26556, 26790, 27019, + 27245, 27466, 27683, 27896, 28105, 28310, 28510, 28706, + 28898, 29085, 29268, 29447, 29621, 29791, 29956, 30117, + 30273, 30424, 30571, 30714, 30852, 30985, 31113, 31237, + 31356, 31470, 31580, 31685, 31785, 31880, 31971, 32057, + 32137, 32213, 32285, 32351, 32412, 32469, 32521, 32567, + 32609, 32646, 32678, 32705, 32728, 32745, 32757, 32765, + 32767}; + +void LoadNwave(void){ +u16 i; +u8 j=0; + for(i=0;i<384;i++){ + if(i<128)Sinewave[i]=SineQuad[j++]; + else if(i<256)Sinewave[i]=SineQuad[j--]; + else Sinewave[i]=-SineQuad[j++]; + } +} + +/******************************************************************************* + +*******************************************************************************/ +u32 Power(u8 x, u8 y) +{ + u32 m = x; + + if(y == 0) return 1; + while (--y) m *= x; + return m; +} +/******************************************************************************* + delayms: milliseconds (mS) time delay procedure Input: milliseconds to wait (72MHz frequency case) +*******************************************************************************/ +void Delayms(u16 mS) +{ + Delay_Cnt = mS; //note that this times in steps of 20mS, with 1st 20mS being indefined: EG 1-20= ?-20, 21-40=?+20 + while (Delay_Cnt > 0){} +} + +/******************************************************************************* + Sign_int2Str: 32-digit switch to e-bit effective number of strings + dimensionless string +******************************************************************************/ + +void Int2Str(char *p, s32 n,const char *pUnit, u8 e, u8 Mode, s8 ShiftDigits) +{ + s32 i, j, m, c,mm; //e= number of digits + char *k; //Mode= SIGN=0 UNSIGN=1 STD=2 + u8 v=0; + u8 numdigits=e; + char id=pUnit[0]; + if((Mode==0)&&((n>=100000000)||(n<=-100000000)))ShiftDigits=3; //special case for volts>100 to use "V" and remove period + s32 nn=n; + if(n == 0x80000000) + { // This value is defined as an invalid value + *p++ = ' '; + *p++ = '.'; + while(--e) *p++ = ' '; + if ((id=='u')&&(numdigits==3))*p++=' '; + *p = 0; return; + } + if(Mode == SIGN) + { + if(n>0) + { + *p++ = '+'; + v='+'; + } + if(n<0) + { + *p++ = '-'; + n=-n; + v='-'; + } + if(n==0) + { + *p++ = '0'; + *p = '.'; + } + } + m = n; //n= s32 number input + i = 0; + c = 5; + + while(m >= 10) // detection of n significant digits + { //m holds input + m /= 10; //divide by 10 > In integer math, this just gets rid of the last digit + if(++i > e) //count digits, add the one just eliminated and compare with e + c *= 10; //if larger than e, multiply c (initiated at 5) by 10 + } //number of significant digits than e calculate the rounded median + + if(i >= e) // plus the rounded value + n += c; //add 5xxx to the next digit after e number of digits, provides half digit bias for rounding off + m = n; //reload input with added bias into m + mm= n; + i = 0; + + while(m >= 10) // re-detection of n significant digits + { + m /= 10; + i++; + } + + i++; //to make up for i equaling number of digits minus 1 + //n now holds input, biased with 5 after least significant digit according to e number of digits + + + i-=ShiftDigits; //shift number of digits back down to correct number if using up-scaling to increase resolution + + + if(e > 3) //i holds the number of digits in input number + { + m = (i-1)/3; + i %= 3; + if(i == 0) + i = 3; + } + else //e=3 or less, normal integer division/modulo + { + m = i/3; + i %= 3; + } + + p += e; //p=output string pointer, inc by called for number of digits + k = p+1; //pointer position for suffix + + while(n >= Power(10, e)) //strip away non significant digits, leaving the called for e number of digits in n + n /= 10; // interception of the highest e effective number of bits(digits...) + + + for(j=0; j0)m=1; //allows up-scaling to place decimal point in proper place, m now no longer relevant otherwise. + + if ((_T_Range<3)&&(id=='u')&&(numdigits==3)) while(*pUnit++); // special case for very large deltaT intervals, move to proper suffix + + do *k++ = *pUnit; // copy desired string + nul + while(*pUnit++); // dimensional character string + + while(e--) //in modes other than SIGN, p has only been increased by e... + { + *p-- = '0'+(n%10); // copy the digits of the value, n has had non significant digits stripped off + n /= 10; // strip away last digit + if((Mode != STD)&&(m > 0)&&(i == e)) //&&(Mode != SIGN) + { //if Mode is SIGN or UNSIGN, m>0 input (n) has at least as many digits as e(called for), + //*p-- = '.'; //i=e(digit position in number), insert point and move pointer down 1 position + if(ChartLogic()){ + if((Mode==0)&&((mm>=100000000)||(mm<=-100000000)))*p-- = ' ';else *p-- = '.'; // special case with rounding S>100, remove period + }else{ + if((Mode==0)&&((nn>=100000000)||(nn<=-100000000)))*p-- = ' ';else *p-- = '.'; // special case v>100, remove period + } + } + } + + if((Mode!=STD)&&(Mode!=SIGN)&&(m==0)) //mode is UNSIGN + { //this is putting a 0. in front of a shifted range, + p++; //*p++; //putting a 0. effectively shifts the range, so it is also effectively changing the suffix, + *p-- = '.'; //throws reading way off. Need to not put point, either spaces of 0's + *p= '0'; //OR keep range suffix the same...> fixed by shifting digits + } + + if((Mode==STD)&&(m==0)) //m>0 if, with e(called for #of digits)>3 and original n(input number) had greater than 3 digits + *p-- = ' '; //OR, if e=3 or less, original n had greater than 2 digits + //insert space, but p now points on char before position passed (?) + + if((Mode == SIGN)&&(p[1] == '.')&&(p[0] != '0')){ + if ((id=='u')&&(numdigits==3)){ // identify time vernier, no need for +, allow suffix to show properly + p[0]='0'; + }else{ + p[7]=0; + p[6]=p[5]; + p[5]=p[4]; + p[4]=p[3]; + p[3]=p[2]; + p[2]='.'; + p[1]='0'; + if(v=='-') + p[0]='-'; + else + p[0]='+'; + } + } + + if ((id=='u')&&(numdigits==3)){ // identify time vernier + if (p[0]=='+')p[0]=' '; // strip off "+" sign on rest of readings to match values that start with 0 + if (nn<100){p--; p[0]='0'; p[1]='.';} // special case for very small values + } +} + + +/******************************************************************************* + Two ASCII character Change to 1 Byte HEX data +*******************************************************************************/ +/* +u8 Str2Byte(char x,char y) // double-ASCII characters to 1 byte binary number //these 2 functions not used... +{ + uc8 Hexcode[17]="0123456789ABCDEF"; + u8 i, Temp=0; + + if(x>='a' && x<='z') x-=32; // lowercase change to uppercase + if(y>='a' && y<='z') y-=32; // lowercase change to uppercase + for(i=0;i<16;i++){ + if(Hexcode[i]==x) Temp+=i*16; // characters into the high four hexadecimal values + } + for(i=0;i<16;i++){ + if(Hexcode[i]==y) Temp+=i; // characters into four hexadecimal values + } + return Temp; +} + +// ******************************************************************************* +// u16ToDec5: Change 2 Byte to 5 decimal number string +// ******************************************************************************* + +void u16ToDec5(char *p, u16 n) +{ + *p++ = '0'+n/10000; + n %= 10000; + *p++ = '0'+n/1000; + n %= 1000; + *p++ = '0'+n/100; + n %= 100; + *p++ = '0'+n/10; + n %= 10; + *p++ = '0'+n; + *p = 0; +} +*/ +/******************************************************************************* + u8ToDec3: Change Byte to 3 decimal number string +*******************************************************************************/ +void u8ToDec3(char *p, u16 n,u8 service) //will also work as u16 to decimal 3 +{ +u8 i; + if(service){*p++ = '0'+n/1000; n %= 1000;} //allow function to work as a u16 to decimal 4 + for(i=100;i>0;i/=10){ + *p++ = '0'+n/i; + n %=i; + } + *p = 0; +} + +void u32ToDec7(char*p,u32 n){ //need to consolidate these functions to a uToDec(x decimals) +u32 i; + for(i=1000000;i>0;i/=10){ + *p++ = '0'+n/i; + n %=i; + } + *p = 0; +} + +/******************************************************************************* + s8ToPercen: Change sign char to +(-)x.xx string +*******************************************************************************/ +void s8ToPercen(char *p, s8 n) +{ + if(n >= 0) *p++ = '+'; + else { + *p++ = '-'; + n = -n; + } + *p++ = '0'+n/100; + n %= 100; + *p++ = '.'; + *p++ = '0'+n/10; + n %= 10; + *p++ = '0'+n; + *p = 0; +} +/******************************************************************************* + u8ToDec2: Change Byte to 2 decimal number string +*******************************************************************************/ +void u8ToDec2(char *p, u8 n) +{ +// *p++ = '0'+n/100; + n %= 100; + *p++ = '0'+n/10; + n %= 10; + *p++ = '0'+n; + *p = 0; +} +/******************************************************************************* + Char2Hex: Change Byte to 2 hex number string +*******************************************************************************/ +void Char2Hex(char *p, u8 n) +{ + if(n/16>9) *p++ = 'A'+(n/16-10); + else *p++ = '0'+n/16; + n %= 16; + if(n>9) *p++ = 'A'+(n-10); + else *p++ = '0'+n; + *p = 0; +} +/******************************************************************************* + Shor2Hex: Change 2Bytes to 4 hex number string +*******************************************************************************/ +/* +void Shor2Hex(char *p, u16 n) +{ + if(n/0x1000 >9) *p++ = 'A'+(n/0x1000-10); + else *p++ = '0'+ n/0x1000; + n %= 0x1000; + if(n/0x100 >9) *p++ = 'A'+(n/0x100-10); + else *p++ = '0'+ n/0x100; + n %= 0x100; + if(n/0x10 >9) *p++ = 'A'+(n/0x10-10); + else *p++ = '0'+ n/0x10; + n %= 0x10; + if(n >9) *p++ = 'A'+(n-10); + else *p++ = '0'+n; + *p = 0; +}*/ + +/******************************************************************************* + Word2Hex: Change 4 Bytes to 8 hex number string +*******************************************************************************/ + +void Word2Hex(char *p, u32 n){ +u32 Ref=0x10000000; + do{ + if(n/Ref>9)*p++='A'+(n/Ref-10); + else *p++='0'+n/Ref; + n %=Ref; + Ref/=0x10; + }while(Ref>0); + *p = 0; +} + +/******************************************************************************* + Int_sqrt: unsigned int square root +*******************************************************************************/ +u32 Int_sqrt(u32 n) + + +/*{ u32 k; + if ( n == 0 ) return 0; + k = 2*Int_sqrt(n/4)+1; + if ( k*k > n ) return k-1; + else return k; +}*/ + +{ + u8 Round=0; + unsigned int c = 0x8000; + unsigned int g = 0x8000; + + if (n<10000000)Round=1; //round off only smaller values, otherwise up-scaling limits dynamic range + + if(Round)n*=100; //scale up to allow bias to center zero for integer math, provides proper rounding off + for(;;) { + if(g*g > n) + g ^= c; + c >>= 1; + if(c == 0){ + if(Round)g+=5; //add bias + if(Round)g/=10; //scale back down, was scaled up to the square root of 100, =10 + return g; + } + g |= c; + } +} + +/******************************************************************************* +Read_Keys: Key status process Return: KeyCode +*******************************************************************************/ +u8 Read_Keys(void) +{ + u16 Key_Status, Key_Status_Now; + u8 KeyCode=0; + + Key_Status_Now = ~__Get(KEY_STATUS);//~KeyScan(); + Key_Status = Key_Status_Now &(~Key_Status_Last); + if(Key_Status){ // New key push on + SetLowVolume=0; + Key_Wait_Cnt=30; // Close auto repeat 25=500mS + Key_Mid_Speed=100; + if(Key_Status & K_ITEM_D_STATUS) KeyCode = K_ITEM_DEC; // K9 right toggle - + if(Key_Status & K_ITEM_S_STATUS) KeyCode = K_ITEM_S; // K10 + if(Key_Status & KEY3_STATUS) KeyCode = KEY3; // K3 + if(Key_Status & KEY4_STATUS) KeyCode = KEY4; // K4 + if(Key_Status & K_INDEX_D_STATUS) KeyCode = K_INDEX_DEC; // K5 left toggle - + if(Key_Status & K_INDEX_I_STATUS) KeyCode = K_INDEX_INC; // K6 left toggle + + if(Key_Status & K_INDEX_S_STATUS) KeyCode = K_INDEX_S; // K7 + if(Key_Status & KEY2_STATUS) KeyCode = KEY2; // K2 + if(Key_Status & KEY1_STATUS) KeyCode = KEY1; // K1 + if(Key_Status & K_ITEM_I_STATUS) KeyCode = K_ITEM_INC; // K8 right toggle + + } else { + if(Key_Status_Now & Key_Status_Last){ // Key push hold on + if((Key_Wait_Cnt || Key_Repeat_Cnt)==0){ + if(Key_Status_Now & K_INDEX_D_STATUS) KeyCode = K_INDEX_DEC; // K5 + if(Key_Status_Now & K_INDEX_I_STATUS) KeyCode = K_INDEX_INC; // K6 + + if((Key_Status_Now & K_INDEX_D_STATUS)||(Key_Status_Now & K_INDEX_I_STATUS)){ + switch (Current){ //fast toggle repeat rate for: + case T_VERNIE: //time cursors + case V_VERNIE: //volt cursors + Key_Repeat_Cnt = 2; + break; + case TRIGG: + //if (Detail[Current]==2) Key_Repeat_Cnt = 2; else Key_Repeat_Cnt = 5; //trigger cursors + if ((_Det==2)||(_Det==3))Key_Repeat_Cnt = 2; else Key_Repeat_Cnt = 5; //trigger level or trigger delay value + break; + case OUTPUT: + if ((_Det==2)||(_Det==3))Key_Repeat_Cnt = 2; else Key_Repeat_Cnt = 5; //PWM duty cycle or out level + + if((_Det==1)&&(_Kind==8)&&(GenUartAdj==0))Key_Repeat_Cnt = 2; + + if((_Det==1)&&(GenAdjustMode==1)&&((((Sweep==0)||(Sweep>2))&&(_Kind<5))||(_Kind==7))){ + if(((_Kind<5)&&(Sweep==3)&&((_Frqn>13)||((SweepIndex<2)&&(_Frqn>5))))&&((FineAdjust==0)||(FineAdjust>=FineAdjustLimit))){ + Key_Repeat_Cnt = 5; + }else Key_Repeat_Cnt = 2; + } + + break; + case T_BASE: + if ((_Det==2)||(_Det==3)) Key_Repeat_Cnt = 2; else Key_Repeat_Cnt = 5; //xpos in large buffer mode + break; + case TRACK1: + case TRACK2: + if((SpiLogic())&&(_Det==1)&&(SpiAdj==3)){Key_Repeat_Cnt = 2;break;} + case TRACK3: + case TRACK4: + if (Detail[Current]==3) Key_Repeat_Cnt = 2; else Key_Repeat_Cnt = 5; //ypos in track menus + if((_4_source>11)&&(Current==3)&&(_Det==1)){ + if(DownConvertMode){ + if((FFTt1Mode==0)&&(Key_Status_Now & K_INDEX_I_STATUS))Key_Repeat_Cnt=15; + }else{ + if(FFTt1Mode)Key_Repeat_Cnt = 2; + } + } + break; + default: + Key_Repeat_Cnt = 5; + } + } + + if(Key_Status_Now & K_ITEM_D_STATUS) {KeyCode = K_ITEM_DEC; Key_Repeat_Cnt = 5;} // K9 + if(Key_Status_Now & K_ITEM_I_STATUS) {KeyCode = K_ITEM_INC; Key_Repeat_Cnt = 5;} // K8 + if(Key_Repeat_Cnt==2){ + SetLowVolume=1; + }else SetLowVolume=0; + } + }else SetLowVolume=0; + } + Key_Status_Last = Key_Status_Now; + return KeyCode; +} + +void s16ToDec3(char *p, s16 n){ //Change signed 16 bit int to +/-xxx string +u8 i; + if(n >= 0) *p++ = '+'; + else { + *p++ = '-'; + n = -n; + } + for(i=100;i>0;i/=10){ + *p++ = '0'+n/i; + n %=i; + } + *p = 0; +} + + +u16 AsciiToU16(char *p,u8 n){ + u8 i; + u16 Value=0; + for(i=1;i<=n;i++)Value+=((*p++-48)*Power(10,(n-i))); + return Value; +} + +void s8ToDec2(char *p, s8 n){ //Change signed 8 bit int(99 to -99) to +/-xx string + if(n > 0) *p++ = '+'; + else if(n < 0){ + *p++ = '-'; + n = -n; + }else *p++= ' '; + + //if((n/10)>0)*p++ = '0'+n/10;else *p++=' '; + if((n/10)>0)*p++ = '0'+n/10; + + n %= 10; + *p++ = '0'+n; + *p = 0; +} + +void S32ToFloat3(char *p,s32 n){ //converts uV to volts with 3 digits floating point precision +s8 i,Ndigits=-1,Neg=0; //need 6 char array inc term nul +s32 nn; + + n/=1000; //convert uV to mV: smallest value called for here is 2000uV + if(n==0){*p++='0';*p=0;return;} + if(n<0){n=-n;Neg=1;} + if(n>999999)n=999999; //limit to 999V to prevent overflow + nn=n; + + while(nn>0){ //# of digits to strip off to get to most significant digit + nn/=10; + Ndigits++; + } + if(Neg) *p++='-'; + + if(Ndigits<3) *p++='.'; //for values less than unity + if(Ndigits<2) *p++='0'; + if(Ndigits==0)*p++='0'; + + for(i=Ndigits;i>=0;i--){ + *p++=48+((n/Power(10,i))%10); //select and write digits + if(i==(Ndigits-2))break; //stop after 3 digits + if(i==3)*p++='.'; //write "floating point" to proper location + } + *p=0; +} + +/************************************************************************ + + FFT Audio Analysis + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + +************************************************************************/ + +// Fixed-point in-place Fast Fourier Transform +// All data are fixed-point short integers, in which -32768 +// to +32768 represent -1.0 to +1.0 respectively. Integer +// arithmetic is used for speed, instead of the more natural +// floating-point. +// +// For the forward FFT (time -> freq), fixed scaling is +// performed to prevent arithmetic overflow, and to map a 0dB +// sine/cosine wave (i.e. amplitude = 32767) to two -6dB freq +// coefficients. +// +// Written by: Tom Roberts 11/8/89 +// Made portable: Malcolm Slaney 12/15/94 malcolm@interval.com +// Enhanced: Dimitrios P. Bouras 14 Jun 2006 dbouras@ieee.org +// Ported to PIC18F: Simon Inns 20110104 +// Ported to stm32: Pedro Simões 2012-03-10 pmos69@hotmail.com + +/* +fix_fft() - perform forward fast Fourier transform. +fr[n],fi[n] are real and imaginary arrays, both INPUT AND +RESULT (in-place FFT), with 0 <= n < 2**m +*/ + +void fix_fft(s32 fr[], s32 fi[], short size) // m = number of bits of the FFT size (ex: 1024 -> 10 bits) +{ // using 32 bit bins allows 18db greater dynamic range + + long int mr = 0, nn, i, j, l, k, istep, n, tr, ti, qr, qi ; + short wr, wi, m; + u8 shift=0; + + if(AutoFFT==0)shift=1; + + m = LOG2_FFTSize; + + n = size; + + nn = n - 1; + + /* max FFT size = N_WAVE */ + + /* decimation in time - re-order data */ + for (m=1; m<=nn; ++m) + { + l = n; + do + { + l >>= 1; + } while (mr+l > nn); + + mr = (mr & (l-1)) + l; + if (mr <= m) continue; + + tr = fr[m]; + fr[m] = fr[mr]; + fr[mr] = tr; + ti = fi[m]; + fi[m] = fi[mr]; + fi[mr] = ti; + } + + l = 1; + k = LOG2_N_WAVE-1; + + while (l < n) + { + /* + fixed scaling, for proper normalization -- + there will be log2(n) passes, so this results + in an overall factor of 1/n, distributed to + maximize arithmetic accuracy. + + It may not be obvious, but the shift will be + performed on each data point exactly once, + during this pass. + */ + + // Variables for multiplication code + long int c; + + istep = l << 1; + for (m=0; m>= 1; + wi >>= 1; + + for (i=m; i>shift))>>(14-shift); //shift extends dynamic range for log display + if(tr&1)tr++; tr>>=1; + c=(wi*(fi[j]>>shift))>>(14-shift); + if(c&1)c++; + tr-=c>>1; + + ti=(wr*(fi[j]>>shift))>>(14-shift); + if(ti&1)ti++; ti>>=1; + c=(wi*(fr[j]>>shift))>>(14-shift); + if(c&1)c++; + ti+=c>>1; + + qr = fr[i]>>1; + qi = fi[i]>>1; + + fr[j] = qr - tr; + fi[j] = qi - ti; + fr[i] = qr + tr; + fi[i] = qi + ti; + + } + } + + --k; + l = istep; + } +} + +void ProcessFileName(void){ //processes EditChar results into SelectedFileName for saving +s8 i,j,h,leading; + leading=1; + + for(i=0;i<8;i++)SelectedFileName[i]=EditChar[i][0]; + + for(i=0;i<8;i++){ //remove leading spaces + if(SelectedFileName[i]==32){ + if(leading){ + for(h=0;h<7;h++){ //make sure all are removed + for(j=i;j<7;j++)SelectedFileName[j]=SelectedFileName[j+1]; + SelectedFileName[7]=32; + if(SelectedFileName[i]!=32){leading=0;break;} + } + }else SelectedFileName[i]=95; //replace remaining spaces with underscores + }else{ + leading=0; //retrieve original non supported char + if(_Curr[2].Value==CFG){if(SelectedFileName[i]==63)SelectedFileName[i]=LastAccessedConfig[i];} + } + + } + for(i=7;i>=0;i--){ + if(SelectedFileName[i]==95){ + SelectedFileName[i]=32; //replace trailing underscores with spaces leaving + }else break; //only in-name underscores + } + if(SelectedFileName[0]==32){ //if filename entered is all spaces, no valid char + for(i=0;i<8;i++){ //will be shifted to first position. Replace all + SelectedFileName[i]=95; //with underscores to produce valid name. + } + } +} + + +/********************************* END OF FILE ********************************/ diff --git a/Interrupt.c b/Interrupt.c new file mode 100644 index 0000000..031986d --- /dev/null +++ b/Interrupt.c @@ -0,0 +1,685 @@ +/********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ******************** + File Name : Interrupt.c + Version : DS203_APP Ver 2.3x Author : bure +*******************************************************************************/ +#include "Interrupt.h" +#include "Function.h" +#include "Menu.h" +#include "BIOS.h" +#include "Process.h" + +vu8 Cursor_Cnt, Key_Wait_Cnt, Key_Repeat_Cnt, Key_Buffer, Cnt_20mS, Key_Mid_Speed=0; // , IntCount, ModInit=0; +vu16 Cnt_mS; + +vu8 Twink, Blink,ClearStatus=0; +u8 Volume=20, Light, LoBeepLevel=0; +vu16 Delay_Cnt, Beep_mS, Key_Status_Last, Sec_Cnt, PD_Cnt, NotificationTimer=0,DelayLoopBreak=0,SpecFrameCount, + PersHoldTimer, SecondsTick, ConfNameTimer, CursorDisplayTimer, AutoSetTimer; +vu8 Tim2Factor=1; +u16 ToneBurstCounter=0; +vu8 BurstLimit=0; +u8 SweepResetFlag; +vs16 NoiseIP[100]; +vs16 FilterOut; +vu32 LimitTransfer; +vu8 FineAdjust=2; +u8 FineAdjustLimit=4; +vu16 FineAdjustFactor[17]={10000,5000,2000,1000,500,200,100,50,20,10,5,2,1,1,1,1,1}; + +vu32 Wait_Cnt; + +void NMIException(void) +{} + +void HardFaultException(void) +{ + while (1) {} +} + +void MemManageException(void) +{ + while (1) {} +} + +void BusFaultException(void) +{ + while (1) {} +} +void UsageFaultException(void) +{ + while (1) {} +} + +void DebugMonitor(void) +{} + +void SVCHandler(void) +{} + +void PendSVC(void) +{} + +void SysTickHandler(void) +{} + +void WWDG_IRQHandler(void) +{} + +void PVD_IRQHandler(void) +{} + +void TAMPER_IRQHandler(void) +{} + +void RTC_IRQHandler(void) +{} + +void FLASH_IRQHandler(void) +{} + +void RCC_IRQHandler(void) +{} + +void EXTI0_IRQHandler(void) +{} + +void EXTI1_IRQHandler(void) +{} + +void EXTI2_IRQHandler(void) +{} + +void EXTI3_IRQHandler(void) +{} + +void EXTI4_IRQHandler(void) +{} + +void DMA1_Channel1_IRQHandler(void) +{} + +void DMA1_Channel2_IRQHandler(void) +{} + +void DMA1_Channel3_IRQHandler(void) +{} + +void DMA1_Channel4_IRQHandler(void) +{} + +void DMA1_Channel5_IRQHandler(void) +{} + +void DMA1_Channel6_IRQHandler(void) +{} + +void DMA1_Channel7_IRQHandler(void) +{} + +void ADC1_2_IRQHandler(void) +{} + +void USB_HP_CAN_TX_IRQHandler(void) +{ + __CTR_HP(); +} + +void USB_LP_CAN_RX0_IRQHandler(void) +{ + __USB_Istr(); +} + +void CAN_RX1_IRQHandler(void) +{} + +void CAN_SCE_IRQHandler(void) +{} + +void EXTI9_5_IRQHandler(void) +{} + +void TIM1_BRK_IRQHandler(void) +{} + +void TIM1_UP_IRQHandler(void) +{} + +void TIM1_TRG_COM_IRQHandler(void) +{} + +void TIM1_CC_IRQHandler(void) +{} + +void TIM2_IRQHandler(void) +{ + + u16 i; + u32 Limit=0; + u32 Reset; + + Reset=LimitTransfer; + if((_Kind==5)&&(_Frqn>15))DAC->DHR12R1=(u32)RandomGen(); // take over seeding from int4 above 100khz limit + +//==============================================SWEEP MODE=============================================== +if(_Kind<5){ + if((Sweep==1)&&((Cnt_mS%SweepMod)==0)){ //SWEEP MODE +//------------------------------------------RESET SWEEP TO START----------------------------------------- + + if(GenFreqShift<=-100){ // >>> NEED TO TEST UPDATE EVENT FLAG AT INIT + + if(_Frqn<=SweepIndex){ //LOW FREQS AND FAST SWEEP RATES (just to keep program going, not normally used...) + + if(SweepResetFlag==0){ + + if(_Kind == PWM){ + TIM4->SR &= 0xFFFE; //update event bit reset + }else { + DMA2->IFCR |= 0x2000; //reset finish bit + } + SweepResetFlag=1; + goto BypassFunction; + + }else{ + + if(_Kind == PWM){ + if((TIM4->SR&1)==0)goto BypassFunction; + }else { + if((DMA2->ISR & 0x2000)==0)goto BypassFunction; + } + SweepResetFlag=0; + GenFreqShift=100; //reset and use as counter to generate space + ClearStatus=1; //starts space between sweeps + + if(_Kind == PWM){ + for(i=0;i<720;i++)ATT_DATA[i]=2048; //clear ATT_DATA to create space + __Set(ANALOG_ARR, A_Tab[9]); //shuts off PWM, turns on Analog + }else{ + for(i=0;i<720;i++)ATT_DATA[i]=2048; //clear ATT_DATA to create space + OutputAdjust(); + } + + } //if sweepresetflag + + }else{ //HIGH FREQS AND LOW SWEEP RATES, (if GenFreqShift<=-100) + //END OF SWEEP: SHUT OFF WAVE AND START SPACE + GenFreqShift=100; //reset and use as counter to generate space + ClearStatus=1; //starts space between sweeps + Limit=0; + + if(_Kind == PWM){ + + if(_Frqn<15){ + TIM4->SR &= 0xFFFD; //capture compare event bit reset + while(Limit++SR&2){ //wait for capture compare event + TIM4->CCMR1=0x005C; //force output high + break; + } + } + TIM4->SR &= 0xFFFE; //update event bit reset + Limit=0; while(Limit++SR&1)break;} //wait for wave (forced high) to finish + TIM4->CCMR1=0x0078; //restore capture compare output + }else if(_Frqn<17){ + while(Limit++<7){} //delay, attempt to catch wave when high + } + + GPIOB->CRL = 0x34BBB438; // puts PWM port(TIM4/PB6) in input, floating mode + configures other bits + TIM4->CR1 = 0x0080; // SQR_OUT = Disable. Stops counter 0x80=auto reload preload enable + // PA4 and PB6 hard wired together as common output + GPIOA->CRL = 0x111011BB; // puts analog (DAC port PA4) in input, analog mode + configures other bits + DAC->CR = 0x0003; // DAC= Enable without output buffer (connects DAC to port PA4, also PB6 through external connection) + TIM7->CR1 = 0x0085; // DAC_CLK = Enable (update on overflow only) + TIM4->EGR=0x0001; // generate update event for full reset in case counter stopped before reset + }else { + + if((_Frqn==15)&&(_Kind<2)&&(SweepIndex==8))for(i=0;i<(M_Factor*48);i++)Waste++; //100Khz delay for sine/triangle + + DMA2->IFCR |= 0x2000; //reset finish bit + while((DMA2->ISR & 0x2000)==0){if(Limit++>Reset)break;} //wait for waveform to finish + DMA2->IFCR|=0x00002000; //clear transfer complete int flag + + for(i=0;i<720;i++)ATT_DATA[i]=2048; //clear ATT_DATA to create space + OutputAdjust(); + } + } //if(_Frqn<=SweepIndex), else +//------------------------------------------SWEEP/SPACE COUNT DOWN----------------------------------------- + }else{ //if(GenFreqShift<=-100) + GenFreqShift-=SweepStep; //sweep or use to create space + if((ClearStatus)&&(GenFreqShift<40)){ //end space space=100-xx mS + GenFreqShift=100; //reset after space + if(_Kind == PWM){ //START OF NEW SWEEP + TIM4->CNT=TIM4->ARR; //load counter to auto reload value for quick reset + TIM4->CCER=0x0001; //turn PWM back on if turned off + TIM4->PSC = D_Tab[_Frqn].PSC; + GPIOA->CRL |= 0x40000; // DAC_OUT = Disable (puts analog port(PA4)in input, floating mode) + TIM7->CR1 = 0x0084; // DAC clock disable + DAC->CR = 0; // DAC = Disable + EnablePWM=1; + }else{ + DMA2_Channel4->CCR &= ~DMA_CCR1_EN; + WaveGen(); //reload ATT_DATA + ResetDMA2_Ch4Params(720/ScaleIndex[_Frqn]); + } + ClearStatus=0; + } + + } + if(ClearStatus==0) OutputAdjust(); + +//==============================================BURST MODE=============================================== + }else if((Sweep>1)&&((Cnt_mS%SweepMod)==0)){ +//------------------------------------------RESET BURST TO START----------------------------------------- + + if((ClearStatus==0)&&(ToneBurstCounter>=BurstLimit)){ //burst limit = xx to 200 + + if(_Frqn<=SweepIndex){ //FOR LOW FREQS AND HIGH SWEEP SPEEDS + + if(SweepResetFlag==0){ + if(_Kind == PWM){ + TIM4->SR &= 0xFFFE; //update event bit reset + }else { + DMA2->IFCR |= 0x2000; //reset finish bit + } + SweepResetFlag=1; + goto BypassFunction; + }else{ + if(_Kind == PWM){ + if((TIM4->SR&1)==0)goto BypassFunction; //this section to provide program flow only, not likely to be + }else { //using burst freq lower than burst rate + if((DMA2->ISR & 0x2000)==0)goto BypassFunction; + } + SweepResetFlag=0; + ToneBurstCounter=0; + ClearStatus=1; //starts space between sweep + if(_Kind == PWM){ + TIM4->CCER=0x0000; //shut off PWM + }else{ + for(i=0;i<720;i++)ATT_DATA[i]=2048; //clear ATT_DATA to create space + } + OutputAdjust(); //reset for beginning of new burst + } //if sweepresetflag + + }else{ //HIGH FREQS AND LOW SWEEP SPEEDS + //END BURST, START SPACE + ToneBurstCounter=0; + ClearStatus=1; //starts space between sweeps + Limit=0; + + if(((SweepIndex<2)&&(_Frqn>5))||(_Frqn>13))for(i=0;i<(FineAdjust*FineAdjustFactor[_Frqn-6]);i++)Waste++; + + if(_Kind == PWM){ //SHUT OFF PWM + TIM4->SR &= 0xFFFE; //update event bit reset + while((TIM4->SR&1)==0){if(Limit++>Reset)break;} //wait for timer to reset signaling end of waveform + TIM4->CCER=0x0000; //shut off PWM + }else { //SHUT OFF ANALOG WAVES + DMA2->IFCR |= 0x2000; //reset finish bit + while((DMA2->ISR & 0x2000)==0){if(Limit++>Reset)break;} //wait for waveform to finish + for(i=0;i<720;i++)ATT_DATA[i]=2048; //clear ATT_DATA to create space + } + OutputAdjust(); //reset for beginning of new burst + + } //if(_Frqn<=SweepIndex) +//------------------------------------------BURST/SPACE COUNTDOWN----------------------------------------- + }else{ //((ClearStatus==0)&&(ToneBurstCounter>BurstLimit)) + + ToneBurstCounter+=SweepStep; //sweep or use to create space + if((ClearStatus)&&(ToneBurstCounter>((200-BurstLimit)+60))){ //END SPACE, START NEW BURST + ToneBurstCounter=0; //reset after space + if(SweepIndex<2)Cnt_mS=19; //ModInit=1;else ModInit=0; //special case for sweepmod>1 + if(_Kind == PWM){ + TIM4->CNT=0x0000; //reset counter + TIM4->CCER=0x0001; //TURN PWM BACK ON + }else{ //TURN ANALOG WAVES BACK ON + DMA2_Channel4->CCR &= ~DMA_CCR1_EN; + WaveGen(); //reload ATT_DATA + ResetDMA2_Ch4Params(720/ScaleIndex[_Frqn]); + } + ClearStatus=0; + } + + } + if(ClearStatus==0)OutputAdjust(); + + } //if sweep>1 +} +//===================================================END==================================================== +BypassFunction: + + TIM2->SR=0; +} + + + +void TIM3_IRQHandler(void) +{ + + u8 KeyCode; + + SpecFrameCount++; + __Set(KEY_IF_RST, 0); //Clear TIM3 interrupt flag + if(Cnt_mS > 0) Cnt_mS--; + else { + + //Cnt_mS=20; //use with 1mS IRQ timing + if((SweepIndex<2)&&(Sweep>1)&&(_Kind<5)) + Cnt_mS=19; else Cnt_mS=20; //resetting to 19 provides correct 20mS timing since it includes 0 (necessary for SweepIndex 0 and 1) + //reset to 20 since other parts of program already compensate for this + + if(Wait_Cnt >0) Wait_Cnt--; //for Synchro + if(Delay_Cnt >20) Delay_Cnt -= 20; + else Delay_Cnt = 0; + if(Beep_mS >=20) Beep_mS -= 20; + else __Set(BEEP_VOLUME, 0); // Beep off + if(Cnt_20mS < 50) Cnt_20mS++; //here again, this goes from 0 to 50, providing 1.02 seconds timing but is not a big issue here + else { // Do it pre sec. + Cnt_20mS = 0; + __Set(BETTERY_DT, 1); //Battery Detect + Sec_Cnt++; + if(PD_Cnt > 0) PD_Cnt--; + } + Cursor_Cnt++; + if (NotificationTimer==80)Cursor_Cnt=0; //synchronize blinker with message + if(Cursor_Cnt >= 15) { //12*20mS=240mS 15=300ms + Cursor_Cnt=0; + Twink=!Twink; + Blink = BLINK; + } + if(SecondsTick>0)SecondsTick--; //int based timers + if(DelayLoopBreak>0)DelayLoopBreak--; + if(NotificationTimer>0)NotificationTimer--; + if(PersHoldTimer>0)PersHoldTimer--; + if(ConfNameTimer>0)ConfNameTimer--; + if(CursorDisplayTimer>0)CursorDisplayTimer--; + if(AutoSetTimer>0)AutoSetTimer--; + + if(Key_Mid_Speed) Key_Mid_Speed--; + if(Key_Wait_Cnt) Key_Wait_Cnt--; + if(Key_Repeat_Cnt) Key_Repeat_Cnt--; + KeyCode=Read_Keys(); + if(KeyCode !=0) { + Key_Buffer = KeyCode; + if(SetLowVolume){ + __Set(BEEP_VOLUME,((9-LoBeepLevel)*5*(Title[VOLUME][CLASS].Value-1))/9); // Fast key repeat volume + }else{ + __Set(BEEP_VOLUME, 5*(Title[VOLUME][CLASS].Value-1)); // Volume + } + Beep_mS = 60; + } + } +} + + + +void TIM4_IRQHandler(void){ //noise filter + u16 i; + static s32 tmp; + static u8 index; + static u8 SeedIndex=0; + + if(_Kind==5){ + if(InitiateNoise){ + DAC->DHR12R2=(u32)RandomGen(); + tmp=0; + index=0; + InitiateNoise=0; + FilterOut=0x0800; + for(i=0;i<100;i++)NoiseIP[i]=0; + tmp=0; + }else{ + if(_Frqn<8){ + DAC->DHR12R1=(u32)FilterOut; + NoiseIP[index]=((u32)DAC->DOR2&0x0FFF)-0x0800; + tmp+=NoiseIP[index]; + if(index<99)tmp-=NoiseIP[index+1]; + else {tmp-=NoiseIP[0]; DAC->DHR12R2=(u32)RandomGen();} //seed for DAC2 from seed generator mod 100 + if(_Frqn<3)FilterOut=(tmp/25)+0x0800; //normalize output + else if(_Frqn<6)FilterOut=(tmp/27)+0x0800; + else FilterOut=(tmp/30)+0x0800; + if(++index>99)index=0; + }else if(_Frqn<14){ + DAC->DHR12R1=(u32)FilterOut; + NoiseIP[index]=((u32)DAC->DOR2&0x0FFF)-0x0800; + tmp+=NoiseIP[index]; + if(index<9)tmp-=NoiseIP[index+1]; + else tmp-=NoiseIP[0]; + if(++SeedIndex>17){DAC->DHR12R2=(u32)RandomGen();SeedIndex=0;} //seed for DAC2 from seed generator mod 17 + if(_Frqn<12)FilterOut=(tmp/10)+0x0800; + else FilterOut=(tmp/8)+0x0800; + if(++index>9)index=0; + }else if(++SeedIndex>(17)){DAC->DHR12R1=(u32)RandomGen();SeedIndex=0;} + + } + if(FilterOut<0)FilterOut=0;else if(FilterOut>0x0FFF)FilterOut=0x0FFF; //provide proper clipping limits + } + TIM4->SR=0; +} + +void I2C1_EV_IRQHandler(void) +{} + +void I2C1_ER_IRQHandler(void) +{} + +void I2C2_EV_IRQHandler(void) +{} + +void I2C2_ER_IRQHandler(void) +{} + +void SPI1_IRQHandler(void) +{} + +void SPI2_IRQHandler(void) +{} + +void USART1_IRQHandler(void) +{} + +void USART2_IRQHandler(void) +{} + +void USART3_IRQHandler(void) +{} + +void EXTI15_10_IRQHandler(void) +{} + +void RTCAlarm_IRQHandler(void) +{} + +void USBWakeUp_IRQHandler(void) +{} +/******************************************************************************* +* Function Name : TIM8_BRK_IRQHandler +* Description : This function handles TIM8 Break interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM8_BRK_IRQHandler(void) +{} + +/******************************************************************************* +* Function Name : TIM8_UP_IRQHandler +* Description : This function handles TIM8 overflow and update interrupt +* request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM8_UP_IRQHandler(void) +{} + +/******************************************************************************* +* Function Name : TIM8_TRG_COM_IRQHandler +* Description : This function handles TIM8 Trigger and commutation interrupts +* requests. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM8_TRG_COM_IRQHandler(void) +{} + +/******************************************************************************* +* Function Name : TIM8_CC_IRQHandler +* Description : This function handles TIM8 capture compare interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM8_CC_IRQHandler(void) +{} + +/******************************************************************************* +* Function Name : ADC3_IRQHandler +* Description : This function handles ADC3 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ADC3_IRQHandler(void) +{} + +/******************************************************************************* +* Function Name : FSMC_IRQHandler +* Description : This function handles FSMC global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void FSMC_IRQHandler(void) +{} + +/******************************************************************************* +* Function Name : SDIO_IRQHandler +* Description : This function handles SDIO global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_IRQHandler(void) +{ + /* Process All SDIO Interrupt Sources */ +// SD_ProcessIRQSrc(); + +} + +/******************************************************************************* +* Function Name : TIM5_IRQHandler +* Description : This function handles TIM5 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM5_IRQHandler(void) +{} + +/******************************************************************************* +* Function Name : SPI3_IRQHandler +* Description : This function handles SPI3 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SPI3_IRQHandler(void) +{} + +/******************************************************************************* +* Function Name : UART4_IRQHandler +* Description : This function handles UART4 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART4_IRQHandler(void) +{} + +/******************************************************************************* +* Function Name : UART5_IRQHandler +* Description : This function handles UART5 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART5_IRQHandler(void) +{} + +/******************************************************************************* +* Function Name : TIM6_IRQHandler +* Description : This function handles TIM6 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM6_IRQHandler(void) +{} + +/******************************************************************************* +* Function Name : TIM7_IRQHandler +* Description : This function handles TIM7 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM7_IRQHandler(void) +{} + +/******************************************************************************* +* Function Name : DMA2_Channel1_IRQHandler +* Description : This function handles DMA2 Channel 1 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA2_Channel1_IRQHandler(void) +{} + +/******************************************************************************* +* Function Name : DMA2_Channel2_IRQHandler +* Description : This function handles DMA2 Channel 2 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA2_Channel2_IRQHandler(void) +{} + +/******************************************************************************* +* Function Name : DMA2_Channel3_IRQHandler +* Description : This function handles DMA2 Channel 3 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA2_Channel3_IRQHandler(void) +{} + +/******************************************************************************* +* Function Name : DMA2_Channel4_5_IRQHandler +* Description : This function handles DMA2 Channel 4 and DMA2 Channel 5 +* interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA2_Channel4_5_IRQHandler(void) +{} + +/********************************* END OF FILE ********************************/ + + + + + + + + + + + + + + + + diff --git a/Main.c b/Main.c new file mode 100644 index 0000000..a9be1d7 --- /dev/null +++ b/Main.c @@ -0,0 +1,3533 @@ + +/********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ******************** + File Name : Main.c + Version : DS203_APP Ver 2.5x Author : bure +*******************************************************************************/ +#include "Interrupt.h" +#include "Function.h" +#include "Calibrat.h" +#include "Process.h" +#include "Draw.h" +#include "BIOS.h" +#include "Menu.h" +#include "File.h" +#include + +/******************************************************************************* +Version changes +APP V2.30: since this version no longer to compatible PCB_V2.6 the following version of the motherboard + Since this version is no longer compatible SYS_V1.31 the following version + Sleep timing was revised to 600 seconds (Main.c) + Modify, and add a new SYS library functions (BIOS.s) + Modify the boot information display program (Main.c) +APP V2.31: an increase of boot identify FPGA load configuration completion discriminant (Main.c) + Increase the Licence rights management functionality Demo program example (Ident.c, Main.c),, + Modified analog channel correction function entry and exit operations (calibrat.c) + Increase the the 144MHz alternately sampling mode function (Process.c) +APP V2.32 from the version from the IAR 4.42 and version 5.0 can be used in parallel + Source did not change, the increase of the folder IAR_V5_Prpject +APP V2.33 modified scan <1uS, display the refresh BUG (Process.c,) + Modified in the calibration state, the operation message BUG (Calibrat.c) +APP V2.34 changed by channel separate calibration (Calibrat.c & Main.c,) + Modify the calibration mode of operation (option Calibrat.c) +APP V2.35 modified in the calibration process BUG (Calibrat.c), + Modified, <5uS scan, the suspension can not BUG (Process.c) + To optimize the display data handler (Process.c) + Increase of the analog channel automatic zero balance function (Main.c, Process.c, Calibrat.c) +APP V2.36 part of the calibration operation into automatic mode (Calibrat.c, Process.c, Function.c) + Modify the boot loader to the operating parameters (Main.c) +APP V2.37 to further improve and optimize the display data handler (Process.c) + Modify the 32-bit signed and unsigned integer conversion process rounded BUG (Function.c,) + Increase the pulse width duty cycle of the time and frequency measurement function (Process.c, Menu.c) +APP V2.40 increase write U disk to create the file function (Main.c, and Flies.c dosfs.c) + Modify the save file number is displayed when BUG (Menu.c) +APP V2.41 increase the file format for the BUF's read / write sample buffer data files (Main.c, Flies.c, Menu.c) + Increased the file format for the CSV export sample buffer data files (Main.c Flies.c, Menu.c) +APP V2.42 for space-saving file system to SYS_V1.40 module (ASM.s, Flies.c, dosfs.c) + Changed use "SerialNo.WPT" file is stored parameter table (Flies.c) + Note: the APP V2.42 or later must be used in conjunction with the SYS V1.40 or later +APP V2.43 modify the adjustment of the analog channels stalls BUG (Main.c), +APP V2.44 modified to save the parameters in the calibration operation BUG (Calibrat.c), + Increase the power load parameters, the success of Tips (Main.c) +APP V2.45 modified to read and write BUF file recovery Display the corresponding menu BUG (Files.c) + Delete the read test information when the BUF file feedback (Main.c) +APP V2.50 rewrite based on the new FAT12 file system, file read and write procedures (Files.c, ASM.s) + Changes to TH, TL measurements the display BUG (Menu.c,) + Optimized with dimensionless values ??show the correlation function (Menu.c Function.c, Calibrat.c) + Modify the pulse width trigger the BUG (Process.c) +APP V2.51 modify Vmin and Vmax, Vpp measured BUG (Process.c) +*******************************************************************************/ + +#define APP_VERSION "GCCv1.7W6.5 APP(2.51+SmTech1.8+PMOS69 fixes)" +#define APP_REVISION "Revision(W6.5) by Wildcat " + + +#define LINE2 "!PRESS > !#! !?! !]! < O > < O > !" +#define LINE3 "! < ADJ > !< MENU > " +#define LINE5 "!SHORT> !HOLD! AUTO METERS SELECT SET TRG !BUFFER " +#define LINE6 " !reset TRIG sav/ld ITEM CHANNEL!(spec/env)" +#define LINE7 " !(config) !(XYper)/ (Change) " +#define LINE4 " (Raw-Nor)/ !(Spc)! " +#define LINE8 " (Spc Func) (Func) " +#define LINE9 " !CH on! " +#define LINE10 " LONG!> V/DIV !MAN STAND! T-BASE MTR PGE !MENU/MTR " +#define LINE11 " !short TRIG BY !short (w/mtrs! on)! " +#define LINE12 " !cut !cut !WAV CAL STDBY TIM!" +#define LINE13 " !(w/mtrs !off) " +#define LINE14 " !METERS! " +#define LINE15 " HOLD!> CHART !CAL! SAVE CURSOR TRIGGER !HOLD " +#define LINE16 " (adj)!config RSTRCT HOLDOFF MIN/MAX! " + +typedef struct {char*ChartLine;}DisplayLine; +DisplayLine DisplayChart[15]= {{(char*)LINE2},{(char*)LINE3},{(char*)LINE5},{(char*)LINE6},{(char*)LINE7},{(char*)LINE4},{(char*)LINE8}, + {(char*)LINE9},{(char*)LINE10},{(char*)LINE11},{(char*)LINE12},{(char*)LINE13},{(char*)LINE14}, + {(char*)LINE15},{(char*)LINE16}}; + +//uc8 PROJECT_STR[20] = "Demo PROG. Ver 1.00"; +u8 OldCurrent; +u8 OldDet; +u8 FlagFrameMode; +u8 OldFrame; +u8 FlagMeter; +u8 TrgAuto; +u16 OldPosX; +u16 OldPosY; +s16 PreviousTrigSelect[4]; +u8 LastSelected=0; +u8 XposFlag=0; +u8 C_Dmeter[8]={4,8,9,10,11,4,10,11}; +u8 UpdateMeter=4; +u8 Timeout=1; +extern u8 _vectors[]; +u8 ShortBuffXpos; +u32 Tmp; +u8 SelectiveUpdate=0; +u8 UpdateFlag=0; +u8 BTwinkState=0; +u8 SaveCurrent[2]={0,0}; +u8 ChStatus[4]={0,0,0,0}; +u8 ABTrigStatus=0; +u8 ChOnStatus[2]={1,1}; +u8 RefreshDisplay=0; +u8 OSStatus=0; +const char NoneStr[13]="None "; +//const char ErrorCode[5][6]={" OK "," FULL"," NONE"," ERR"," CNCL"}; +const char DisableSTR[37]="SCOPE DISABLED- PRESS ANY KEY TO RUN"; + +u8 OldMeter; +u8 TrgAutoOld; +u16 OldTrack1X; +u16 OldTrack2X; +s16 _Vt1Old; +s16 _Vt2Old; +u16 XposRef; //Xpos compensated for interpolated ranges to show equivalent screen position +u8 UpdateCount=0; +u8 ShowFFT=0; +extern u8 UpdateWindow; +u8 ClearDir=0; + +void UpdateBigMeters(void); +void EnableTitleMeters(u8 Service); +void UpdateMeterPage(void); +u8 ConfigFile(u8 service); +//void FileMessage(u8 i); +//u16 GetXpos(u16 XposRef); +u16 GetHoldoffIndPos(void); +void EnableChannel(u8 track); +void UpdateTriggerMem(void); +void SelUpdate(u8 detail); +void TriggFlagUpdate(void); +void MessageHandler(u8 number); +void CurDetailUpdate(void); +void ChannelStatus(u8 service); +void MeterUpdate(u8 start,u8 limit); +void TrigMemory(u8 i); +void PWMdutyControl(u8 Dir); +void PWMscaleReset(u8 Dir); +void BurstAdjust(u8 Dir); +void InitChart(void); +void ProcessEditName(void); +void ResetEditList(void); +u8 LeftToggleSpecialFunctions(void); +u8 CursorSpeedLogic(u8 enable); +void UpdateFrameMode(void); + +NVIC_InitTypeDef NVIC_InitStructure; + +typedef struct {char*Message;}SelectMessage; +u8 MessageNumber; + +#define SAVESET " " +#define WAVCAL_ON " WAVE CALIBRATION - ON " //1 +#define WAVCAL_OFF " WAVE CALIBRATION - OFF " //2 +#define STDBYTIM_ON " STANDBY TIMER - ON " //3 +#define STDBYTIM_OFF " STANDBY TIMER - OFF " //4 +#define CURMETERS_ON "CURSOR SELECT METERS - ON " //5 +#define CURMETERS_OFF "CURSOR SELECT METERS - OFF" //6 +#define TRGHLD_ON " TRIGGER HOLDOFF - ON " //7 +#define TRGHLD_OFF " TRIGGER HOLDOFF - OFF " //8 +#define SHOWEDGE_ON " MIN/MAX HOLD ON " //9 +#define SHOWEDGE_OFF " MIN/MAX HOLD OFF " //10 +#define WAIT_RESET " WAITING FOR RESET... " //11 +#define NOR_DISPLAY " NORMAL WAVEFORM DISPLAY " //12 +#define RAW_DATA " RAW DATA DISPLAY " //13 +#define CUR_DIS_ON " CURSOR DISPLAY ON " //14 +#define CUR_DIS_OFF " CURSOR DISPLAY OFF " //15 + +//#define SHOWEDGE_ON " EDGE FILTER OFF " //9 +//#define SHOWEDGE_OFF " EDGE FILTER ON " //10 + +SelectMessage Show[16]= {{(char*)SAVESET},{(char*)WAVCAL_ON},{(char*)WAVCAL_OFF},{(char*)STDBYTIM_ON},{(char*)STDBYTIM_OFF},{ + (char*)CURMETERS_ON},{(char*)CURMETERS_OFF},{(char*)TRGHLD_ON},{(char*)TRGHLD_OFF},{ + (char*)SHOWEDGE_ON},{(char*)SHOWEDGE_OFF},{(char*)WAIT_RESET},{(char*)NOR_DISPLAY},{(char*)RAW_DATA},{ + (char*)CUR_DIS_ON},{(char*)CUR_DIS_OFF}}; + +uc16 TrigReset[22]= {300, 150, 100, 75, 35, 15, 10, 10, 5, 3, //for auto trig mode, set time to reset after loosing data + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2}; + +uc16 NoteTimer[3]= {250, 125, 50}; //*20ms + + +/******************************************************************************* + main : Main routine. +*******************************************************************************/ +int main(void) +{ + u16 Tmp; + s32 i; + u16 Second = 0;//,Offset, Result,Count_FPS = 0 + u8 j=0; + s16 TmpVT; + s16 Vt1Old=0; + s16 Vt2Old=0; + u16 loopcount=0; + char DelFileName[13]; + const char AutoStr[4][6]={"!Man!","!1/4!","!1/2!","!3/4!"}; + + NVIC_SetVectorTable(NVIC_VectTab_FLASH, (u32)&_vectors); + + __USB_Init(); + + if(__Get(FPGA_OK)== 0){ + __Display_Str(152, 30, YEL, PRN, "FPGA error"); + while (1){}; + } + __Display_Str(32, 50, WHT, PRN, APP_VERSION); + __Display_Str(96, 130, WHT, PRN, APP_REVISION); + Y_Attr = (Y_attr*)__Get(VERTICAL); + X_Attr = (X_attr*)__Get(HORIZONTAL); + G_Attr = (G_attr*)__Get(GLOBAL); + T_Attr = (T_attr*)__Get(TRIGGER); + + if(memcmp((u8*)__Get(13),"2.81",4)==0)HardwareVersion=1; else HardwareVersion=0; //HDWVER + + InitiateCalData(); + LoadBaseBuffers(); + Load_Attr(); // assignment Y_Attr + FineAdjust=2; + i = Load_Param(0); + if(i == 0) // read the default boot parameters + __Display_Str(88, 30, GRN, PRN, "Loaded configuration file"); + else + __Display_Str(80, 30, YEL, PRN, "Configuration file not found"); + + if(FineAdjust>4)FineAdjust=2; + Beep_mS = 500; + Key_Buffer=0; + Delayms(2000); + App_init(1); + + SetIRQ2Priority(); + + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0); + NVIC_InitStructure.NVIC_IRQChannel=TIM4_IRQChannel; //TIM4 IRQ setup for noise generator + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + +//----------------- TIM2_IRQ Used for sweep and burst generator ---------------- + TIM2->PSC =72-1; + TIM2->ARR =1000-1; // 1mS + TIM2->DIER =0x0001; // enable TIM2_IRQ + TIM2->CR1 = 0x0085; // enable timer + TIM_2IRQControl(); + + Config_init(); + OldMode=_Mode; + DisableCursorTimer=1; + Update=2; //=2 initiates delayed trig loop to prevent locking up with no trigger and empty buffer + Title[FILE][0].Value=LOAD; //preset file menu to load config files + Title[FILE][1].Value=0; //config file number (0=boot file) + Title[FILE][2].Value=CFG; + + GPIOC->BSRR = 0x00000010; //Set port C bit 4, sets C_D (ClR) + if((u16)__Get(0)==0x5731)FPGAver=1; //get FPGA version + __Set(32+5, 1); //load data + __Set(32+5, 1); //register + if((u16)__Get(0)==0x0101)FPGAsubVer=1; //get FPGA update version + GPIOC->BRR = 0x00000010; //Reset port C bit 4 + + if(FPGAver>0)StartOffset=14; else StartOffset=16; //for oversampling buffer function + +//-------------------------------------------------------------------------- ************** LOOP MAIN ***************** + while (1){ + +//-------------------------------------------------------------------------- Gestione Entra e Uscita da Modalità X Y + + if(_Kind!=PWM)PWAdjustMode=0; + if((ChartLogic())&&(ChartMode))OsChartFlag=1;else OsChartFlag=0; + + if (_Mode!=OldMode) + { + if (_Mode ==X_Y ){ // entra in XY_S + BackGround_Reset(1); + if (OldMode<6){ //4 + OldTrack1X=Title[TRACK1][POSI].Value; + OldTrack2X=Title[TRACK2][POSI].Value; + } + OffsetX=135; + OffsetY=100; + ChannelStatus(0); //save status + EnableChannel(TRACK1); + EnableChannel(TRACK2); + OldMeter=FlagMeter; + if (FlagMeter==0) {EnableMeter();UpdateMeterPage();} + _Vt1Old=_Vt1; + _Vt2Old=_Vt2; + Vt1Old=0; + Vt2Old=0; + TrgAutoOld=TrgAuto; + TrgAuto=2; + OldFrame=FrameMode; + FlagFrameMode=0; + } + + if ((_Mode<6) &&(OldMode>5)){ // esce da XY_S o XY_A + ChannelStatus(1); //restore status + Title[TRACK1][POSI].Value = OldTrack1X; + Title[TRACK2][POSI].Value = OldTrack2X; + BackGround_Reset(1); + if (OldMeter==0) DisableMeter(); + _Vt1=_Vt1Old; + _Vt2=_Vt2Old; + TrgAuto=TrgAutoOld; + if(OldFrame)FlagFrameMode=1; + Update_View_Area(); // in case file menu display was showing + } + } + + if(Title[TRIGG][SOURCE].Value !=4) OldMode=_Mode; + if (_Mode==X_Y)Title[TRACK1][POSI].Value=100; + if (_Mode==X_Y)Title[TRACK2][POSI].Value=100; + + if (_4_source>11)ShowFFT=1; + else{ + ShowFFT=0; + DownConvert=0; + if(DownConvertMode){DownConvertMode=0; DownConvertRestore();} + } + + OsBufferLogicFlag=OSBufferLogic(); + + //-------------------------------------------------------------------------- ********* LIFE ************* + if (((__Get(USB_POWER)>0)||(Timeout==0))&&(PD_Cnt>0)) PD_Cnt = 600; //don't time out into standby on external power or if timeout is disabled and not already in standby + if(PD_Cnt == 0){ + __Set(BACKLIGHT, 0); // turn off the backlight + __Set(STANDBY, EN); // enter low power states + } else { + + if((Update)&&((_Mode!=SCAN)||(ChartLogic()))){ + if((!ChartLogic())||(FrameMode==0)) + _X_posi.Value=GetXpos(XposRef); //align interpolated time bases with the others + } + + if (SelectiveUpdate&1){ // restore screen after removing chart + if (_Mode==X_Y){ + ClearScreenArea(0,400,214,215); //clear top line + } + ClearScreenArea(0,11,12,214); //clear left mark area + DisableCursorTimer=2; + } + + Synchro(); // simultaneous display of waveform data of each track + + if ((TrgAuto>0)&&(_Mode!=SCAN)&&(_Mode!=AUTO)&&(_Mode!=SGL)){ + if(__Get(FIFO_START)== 0){ //check to see if not triggered w/auto trig on + loopcount++; + if (loopcount>TrigReset[_T_base]){ //after proper wait time, re-initialize trig + if(Title[TRIGG][SOURCE].Value==4){ //in A&B mode, reset only non triggered ch + if((Sweep)&&(_Tr_kind==8)&&(_Kind<5)){ + if(TrigSourceEnable==0)_Vt2=_2_posi+10; + if(TrigSourceEnable==1)_Vt1=_1_posi+10; + }else{ + if(TrigSourceEnable==0)_Vt2=_2_posi; //alternate channel function call at end of synchro has shifted over to + if(TrigSourceEnable==1)_Vt1=_1_posi; //other ch if one ch is not triggered so need to reset alternate ch + } + Update_Trig(0); + }else{ + if((Sweep)&&(_Tr_kind==8)&&(_Kind<5)){ + _Vt1=_1_posi+10; //keep trig level away from zero for time based gen sweep/burst synch + _Vt2=_2_posi+10; + }else{ + _Vt1=_1_posi; // set trig at signal zero point in hope to get device to trigger + _Vt2=_2_posi; + } + Update_Trig(1); + } + UpdateMarkLogic(); + loopcount=0; + } + }else{ //if triggered + if(Title[TRIGG][SOURCE].Value==4){ //in A&B mode + if(TrigSourceEnable==0)ABTrigStatus|=1; //ch A is triggered + if(TrigSourceEnable==1)ABTrigStatus|=2; //ch B is triggered + if(ABTrigStatus==3) {loopcount=0;ABTrigStatus=0;} //if both ch are triggered, reset count and trigger status + }else loopcount=0; + } //if get fifo start else... + }else loopcount=0; //if trgauto>... + + if(ToggleName){ + if(ConfNameTimer==0){ + UpdateMarkLogic(); + ToggleName=0; + } + } + + if((FlagMeter==0)&&(Update)){ + Title[T_VERNIE][2].Flag &= 0xFD; + _D_V_Source.Flag &= 0xFD; + _Delta_V.Flag &= 0xFD; //shut update delta display flags with meter off + _Delta_T.Flag &= 0xFD; + } + +//============================================REGULAR METER TIMING==================================================== + if(Second != Sec_Cnt) { + Second = Sec_Cnt; + Result_FPS = Count_FPS; + Count_FPS = 0; + + if((__Get(V_BATTERY)>(PrevBatLevel+40))||(__Get(V_BATTERY)<(PrevBatLevel-40))){ //update with greater than 40Mv change (WAS +/-20Mv) + BatLevelCompensation(); + PrevBatLevel=__Get(V_BATTERY); + SetOffset(0,_A_Range,_1_posi); //provides update for Ka3 + SetOffset(1,_B_Range,_2_posi); + } + + Update_Battery(); + + if (FlagMeter==1){ // refresh the measured values ??per second + + if(EnableMeterCalc){ + DETflag=1; + Display_Value(FRQ); + DETflag=0; + }else LastFreqReadout=0; + + EnablePaS=1; + for(i=0; i<9; ++i) Display_Value(i); + if(((__Get(FIFO_START)!=0)||((_Mode!=NORH)&&(_Mode!=NORHLD)))||((DownConvertInitiate==1)&&(FFTt1Mode))){ //hold reset to show meter values when in normal mode not triggered + if((_T_base > 10)||((_T_base>8)&&(FastMode==1)))ResetSum();else SumResetFlag=1; //in slow mode wait until frame is completed before resetting + WaitForTrigFlag=0; + }else WaitForTrigFlag=1; //allows reset to occur prior to meter loads on triggering after holding values + } + + if(((FlagMeter==0)&&(EnableMeterCalc==0))&& + ((DownConvertMode==0)||(DownConvertInitiate==1)))ResetSum(); //DownConvert initiates here + + } + + if((ChartLogic())&&(CursorDisplaySelect<4))CalculateTvernier(1); //Xpos/Tvernier display moving update + +//============================================================================================================================ + + if (((Cnt_20mS%16)>7)&&((Cnt_20mS%16)<16)&&(UpdateFlag==1))UpdateFlag=0; + +//===========================================LARGE METER TIMING=========================================================== + if (((Cnt_20mS%16)>=0)&&((Cnt_20mS%16)<8)&&(UpdateFlag==0)){ //update meters %16= 3 times/sec %24= 2 times/sec %12= 4 times/sec + UpdateFlag=1; //note that big meter highlight blink rate is tied to update speed + if(UpdateCount==2){ + EnablePaS=1; //enables TH, TL and duty% to update 1/sec + UpdateCount=0; + }else{ + EnablePaS=0; + UpdateCount++; + } + + //if((_State.Value)&&(CursorDisplayTimer>20))CursorDisplayTimer=75; //allow hold to freeze cursor value display + //if((ChartLogic())&&(CursorDisplaySelect<4))CalculateTvernier(1); //Xpos/Tvernier display moving update 3/sec + + GenTrigColor(); //also monitor generator trig mode 3/sec + + if(_Kind == PWM)LimitTransfer=((D_Tab[_Frqn].PSC+1)*D_Tab[_Frqn].ARR)/2; //bailout calculations for sweep wave ending functions + else LimitTransfer=A_Tab[_Frqn]*(TIM7->PSC+1)*125; + + UpdateBigMeters(); + + if((FlagMeter!=1)&&(EnableMeterCalc)){ //allow to get frequency for detector mode display with meters off + DETflag=1; + Display_Value(FRQ); + DETflag=0; + } + + if (((FlagMeter==2)||((FlagMeter!=1)&&(EnableMeterCalc)))||((DownConvertMode)&&((DownConvertInitiate!=1)||(FFTt1Mode)))){ + if(((__Get(FIFO_START)!=0)||((_Mode!=NORH)&&(_Mode!=NORHLD)))||((DownConvertMode)&&(FFTt1Mode))){ + if((_T_base > 10)||((_T_base>8)&&(FastMode==1))){ + if((DownConvertMode)&&(DownConvertInitiate==0))Display_Value(0); + ResetSum(); + }else{ + SumResetFlag=1; //in slow mode wait until frame is completed before resetting + if((__Get(FIFO_START)==0)&&(DownConvertMode) //allows FFT1 mode to work without a triggered signal + &&(DownConvertInitiate==0)&&(FFTt1Mode))Display_Value(0); + } + WaitForTrigFlag=0; + }else WaitForTrigFlag=1; + } + + if ((FlagMeter==2)&&(UpdateMeter==4)){ + FlagMeter=1; //display value on small meter + Display_Value(0); + FlagMeter=2; //return + } + + } +//============================================================================================================================ + + if (FlagMeter>0){ + Display_Meter(); + } + Display_Title(); + //1-Twink, INV, OR PRN + if((Current != FILE)&&(NotificationTimer>4))Print_Str(95,0,0x0405,PRN,Show[MessageNumber].Message); //show message + if((Current != FILE)&&(NotificationTimer>0)&&(NotificationTimer<5)) {Update_View_Area(); NotificationTimer=0;} //end after delay + + if(Update){ // handle button to refresh item + if((DisableCursorTimer)&&(Update==2))DisableCursorTimer++; + UpdateCursorMeter(); + + if ((SelectiveUpdate&1)&&(FlagMeter>0))EnableMeter(); + for(i=0;i<4;i++){ + if (TrgAuto==i) Print_Str(365, 216, ((SCRN<<8)+Title[TRIGG][SOURCE].Value), i,(char*)AutoStr[i]); + } + if ((SelectiveUpdate & 0x02)==0)Update_Range(); //these 4 are exclusions, bit set prevents update + if ((SelectiveUpdate & 0x04)==0)Update_Base(); + if ((SelectiveUpdate & 0x08)==0)Update_Output(); + if ((SelectiveUpdate & 0x10)==0){if(Title[TRIGG][SOURCE].Value==4) Update_Trig(0); else Update_Trig(1);} + UpdateMarkLogic(); + BackLight(0); + + if (SelectiveUpdate & 0x20){ + ClearHoldFlag|=1; //transfer clear hold calls as selectiveupdate gets reset + if(_T_base<11)SlowModeSkip=2; //slowmodeskip allows x frames to finish to properly update buffer + } + if (SelectiveUpdate & 0x40){ + ClearHoldFlag|=2; + if(_T_base<11)SlowModeSkip=2; + } + + Tmp=InvertA; + TmpVT=InvertB; + InvertA=0;InvertB=0; + if((!UartLogic())&&(!i2cLogic())&&(!SpiLogic())&&(_Mode!=X_Y)){ + if((Title[0][SOURCE].Value==2)||(Title[0][SOURCE].Value==4))InvertA=1; + if((Title[1][SOURCE].Value==2)||(Title[1][SOURCE].Value==4))InvertB=1; + } + + if((Tmp!=InvertA)||(TmpVT!=InvertB)){if(Title[TRIGG][SOURCE].Value==4) Update_Trig(0); else Update_Trig(1);} + + if (Current<4)Title[Current][3].Flag|= UPDAT; + if((Current == TRIGG) && (_Det==3)){ + if ((FrameMode==0)||((Options&1)==0)||(_Mode==AUTO)||(OsBufferLogicFlag)||(_Mode==X_Y)||(_Mode==SGL)||(_Mode==SCAN)||(_T_base>9)) _Det=0; + Title[Current][_Det].Flag |= UPDAT; + } + + if((Current != FILE)&&(NotificationTimer<43)) Update_View_Area(); //after 3/4 second, allow notification overwrite if button pushed + if (FlagMeter>0) { + _D_V_Source.Flag |= UPDAT; // Updat delta V + _Delta_V.Flag |= UPDAT; + _Delta_T.Flag |= UPDAT; // Updat delta T + }else{ + if ((Current == V_VERNIE)&&(_Det == 2)) _Det=0; + if ((Current == T_VERNIE)&&(_Det == 2)) _Det=0; + } + + if (FrameMode==2) SaveShortBuffXpos=XposRef; //save trig cursor in config file + if(Update)Update--; // Update finish + SelectiveUpdate=0; + UpdateScale=1; + OsBufferLogicFlag=OSBufferLogic(); + + if ((Current==FILE)&&(_Det==DIR)){ + if(Title[9][2].Value==7){ + Ext[0]='B';Ext[1]='I';Ext[2]='N';Ext[3]=0; + }else{ + for(i=0;i<3;i++)Ext[i]=F_EXT[Title[9][2].Value][i+1]; + } + + if(ClearDir){ + PrintDir(0,0,3); //clear file list when changing in SPEC or MAP modes + ClearDir=0; + } + ReadDir((char*)Ext); + if(Label[Title[9][3].Value][0]==0){if(Title[9][3].Value>0)Title[9][3].Value--;} //if presently selected last file non existant + if(Label[0][0]==0)for(i=0;i<13;i++)Label[0][i]=NoneStr[i]; //no files found + if(DirRange>0){if(Label[14][0]==0)for(i=0;i<13;i++)Label[14][i]=NoneStr[i];} //no more files found + PrintDir(0,0,2); + } + if((BufferRestore)&&(Title[RUNNING][STATE].Value==0)){UpdateFileMenu();BufferRestore=0;} + } + + if((FlagMeter==0)&&(ClearMeterAreaFlag)){Clear_Meter_Area();Update=1;} ClearMeterAreaFlag=0; + + if(_T_base > 10){ + if(UpdateBackground==3)UpdateBackground=0; + if(UpdateBackground==1)UpdateBackground=3; + } + + }//else, if power down + + if((_State.Value == HOLD)&&((__Get(FIFO_FULL)!= 0)||(__Get(FIFO_START)== 0))){ + _State.Value = 2; + _State.Flag |= UPDAT; + } + + if((ChartLogic())&&(FrameMode==0)){ + if(JumpCnt<=380)ScrollFlag=2; + } + + //-------------------------------------------------------------------------- TRIGGER AUTOMATICO + if((TrgAuto>0)&&((_Mode!=SCAN)||(AutoSetFlag))){ + + if((Current == TRIGG) && (_Det==2)){ + if (((_Mode==NORH)||(_Mode==NORHLD)||(_Mode==NORC))&&(_T_base < 10)&&(Options&1)&&(!OsBufferLogicFlag)) _Det=3; else _Det=0; + Title[Current][_Det].Flag |= UPDAT; + } + + if ((Title[TRIGG][SOURCE].Value == TRACK1)||((Title[TRIGG][SOURCE].Value==4)&&(TrigSourceEnable==0))){ + TmpVT=(((((aT_Min+Ka1[_A_Range])-_1_posi)*Ka2[_A_Range])/1024)+((aT_Max-aT_Min)*(TrgAuto*2)/8))+_1_posi; + + if ((TmpVT>Vt1Old +5) || (TmpVTVt2Old +5) || (TmpVT1){ //bail out of autoset + AutoSetFlag=0; + AutoSetTimer=0; + reset_parameter(); + if (_Mode!=SCAN) { + if(FlagFrameMode==0)XposRef=GetXposRef(OldPosi); + if(FlagFrameMode==1)XposRef=ShortBuffXpos; + _X_posi.Value=GetXpos(XposRef); + } + CurDefTime=OldCurDefTime; + if(MeterStatus){ + FlagMeter=MeterStatus; + EnableMeter(); + } + Update_Range(); + Update_Base(); + App_init(0); + goto bypasslongpress; + } + if(AutoSetTimer)AutoSetFlag=1; + AutoSetTimer=25; //x20mS double click timer + + while (Delay_Cnt > 1000) + { + if((__Get(KEY_STATUS)& KEY1_STATUS)!=0){ + _State.Flag |= UPDAT; // set the corresponding update flag + if((_State.Value==0)&&(AutoSetFlag==0)){ //0=run 1=hold also has 2 + ClearMeters(); //clears meters if untriggered in NORH + _State.Value=1; + }else{ + DigChLockout=0; + _State.Value=0; + if(ChartLogic())InitChart();else{ + SelectiveUpdate |=0x60; + if(_Mode!=NORH)ClearTrackBuff(1);else ClearLeadingEdge=1; //REMOVING NORH CONDITION WOULD CLEAR WAVE ALONG WITH METERS... + if(( (_Mode == SGL)||(_Mode==NORH)||(Options&4)||((FrameMode>0)&&(_T_base<3))||((FrameMode==0)&&(_T_base<6))) && (_Mode!=NORHLD) ){ //in run mode if frame >1 1/2 sec + if(!(ChartLogic())){__Set(FIFO_CLR, W_PTR);cleardatabuf(2);} + if(Options&4) {ClearHold(3);ClearMinMax(3);} + if(OsBufferLogicFlag)InitiateOSBuffers(); + if(_T_base<11)JumpCnt=0; + EnablePaS=1; + ResetSum(); + } + } + + if((_T_base<3)&&(_Mode!=SCAN)&&(_Mode!=NORHLD)){ + MessageNumber=11; //wait for reset + if(OSBufferLogic()){ + NotificationTimer=(NoteTimer[_T_base]*(150-_X_posi.Value))/150; + }else{ + NotificationTimer=NoteTimer[_T_base]; + } + } + if(_Mode==NORHLD){cleardatabuf(2);ClearFFTbuffer();} + //InitXY=1; //resets XY persistence if enabled. Using button 5 center press instead + //allows to see waveform prior to re-enabling by pressing button again + if(DownConvertMode)DownConvertShiftEnable=2; + } + goto bypasslongpress; + } //if get key status + } //while + + Beeper(125); BackLight(1); + while ((Delay_Cnt >0)&&(Delay_Cnt <=1000)){ // long press + if(Delay_Cnt<875)BackLight(0); + if((__Get(KEY_STATUS)& KEY1_STATUS)!=0){ + + _Curr[_Det].Flag |= UPDAT; + + if(((ListLogic())||(_Mode==X_Y))&&(EditListActive(1))){ + PrintDir(0,0,3); //clear file list when leaving + if(_Mode==X_Y)InitXY=1; + } + + switch (Current){ + case TRACK1: + if (_Det==RANGE){ + + if(_1_source==0){ + AlignTbaseSweep(4); + _1_source=ChOnStatus[0]; + LastSelected=1; + } else { + AlignTbaseSweep(5); + ChOnStatus[0]=_1_source; + _1_source=0; + } + + }else{ + if(Title[TRACK4][SOURCE].Value<10)EnableChannel(TRACK1); //if FFT on, do not turn channel trace on + } + break; + case TRACK2: + if (_Det==RANGE){ + + if(_2_source==0){ + AlignTbaseSweep(4); + _2_source=ChOnStatus[1]; + LastSelected=2; + } else { + AlignTbaseSweep(5); + ChOnStatus[1]=_2_source; + _2_source=0; + } + + }else{ + if(_4_source<10)EnableChannel(TRACK2); + } + break; + default: + if ((Title[TRACK1][SOURCE].Value != HIDE)&&(Title[TRACK2][SOURCE].Value == HIDE)){ //Cha A on B off + Current = TRACK1; + LastSelected=1; + }else if ((Title[TRACK1][SOURCE].Value == HIDE)&&(Title[TRACK2][SOURCE].Value != HIDE)){ //Cha B on A off + Current = TRACK2; + LastSelected=2; + }else if(_4_source<10){ //if FFT off //both on or off + switch (LastSelected){ + case 0: + case 1: + Current = TRACK1; + EnableChannel(TRACK1); + break; + case 2: + Current = TRACK2; + EnableChannel(TRACK2); + } //switch + }else{ //FFT on, both tracks on or both off + if(_4_source<14)Current=TRACK2;else Current=TRACK1; //go to ch v/div but do not turn on + } + } //switch + _Det = RANGE; + + Title[TRACK1][SOURCE].Flag |= UPDAT; + Title[TRACK2][SOURCE].Flag |= UPDAT; + CurDetailUpdate(); + goto bypasslongpress; + } // if get key status + + } //while delay count 0 to 1000 + + Beeper(60); + if(Delay_Cnt == 0){ + j=0; + for(i=204;i>49;i-=11){ + Print_Str(0,i,0x040C,PRN,DisplayChart[j++].ChartLine); + } + + Delayms(300); + Key_Buffer=0; + + while (1) { + if (Key_Buffer>0){ + SelectiveUpdate=1; + BackGround_Reset(1); + Update_View_Area(); + break; + } + } + } + + } //if key buffer + //-------------------------------------------------------------------------------------------------------------- + if(Key_Buffer== KEY2){ // ===--- TASTO 2 PREMUTO ---=== + Delay_Cnt = 3000; // Carica il temporizzatore del tasto permuto + while (Delay_Cnt > 2500){ // Se il tempo non è arrivato a 0 + if((__Get(KEY_STATUS)& KEY2_STATUS)!=0){ // CAMBIO MODO TRIGGER + DisableCursorTimer=1; + if ((Title[TRIGG][SOURCE].Value != TRACK3)&&(Title[TRIGG][SOURCE].Value != TRACK4)){ + _Curr[_Det].Flag |= UPDAT; + if (TrgAuto==0){ + TrgAuto=2; + Vt1Old=0; + Vt2Old=0; + }else { + TrgAuto++; // AUTO TRIGGER + } + if((Sweep)&&(_Tr_kind==8)&&(TrgAuto==2)&&(_Kind<5))TrgAuto++; //auto trig= 1/2 does not work well with kind=GEN + if (TrgAuto>3) {TrgAuto=1;} // short press + Title[Current][_Det].Flag |= UPDAT; + if ((Current == TRIGG) && (_Det==2)){ Title[Current][_Det].Flag |= UPDAT;_Det=0;} + } + goto bypasslongpress; + }//if get key + }//while + + Beeper(125); BackLight(1); + + while ((Delay_Cnt >0)&&(Delay_Cnt <=2500)){ // long press + if(Delay_Cnt<2375)BackLight(0); + if((__Get(KEY_STATUS)& KEY2_STATUS)!=0){ + if ((Title[TRIGG][SOURCE].Value != TRACK3)&&(Title[TRIGG][SOURCE].Value != TRACK4)){ + _Curr[_Det].Flag |= UPDAT; + if (TrgAuto>0) TrgAuto=0; + Current = TRIGG; + _Det=2; + Title[Current][_Det].Flag |= UPDAT; + } + goto bypasslongpress; + }// if get key status + } // while delay count + + Beeper(60); + if(Delay_Cnt == 0){ + DisableCursorTimer=1; + if(Current<2){ + CalibrateMode=1; + Calibrat(Current); + CalibrateMode=0; + goto BypassExclusions; + }else{ + + if((Current==T_BASE)&&(_Det==1)&&(OSBufferLogic()) + &&(FPGAsubVer)&&(FPGAosFlag)){ //Tbase RANGE sub menu + if(OS_RateSelect)OS_RateSelect=0;else OS_RateSelect=1; + goto bypassOSselect; + } + + if(Current!=9){ //not in file menu + if(OffsetSelect)OffsetSelect=0;else OffsetSelect=1; + goto bypassOSselect; + } + } //if current <2 else + + } // if delay cnt + } + //-------------------------------------------------------------------------------------------------------------- + if(Key_Buffer== KEY3){ // ===--- TASTO 3 PREMUTO --==== + + DisableCursorTimer=1; + if((Current!=FILE)||(_Curr[2].Value!=CFG)){ + Delay_Cnt = 1500; // Carica il temporizzatore del tasto permuto + while (Delay_Cnt > 1000){ //WAS >0 Se il tempo non è arrivato a 0 + if((__Get(KEY_STATUS)& KEY3_STATUS)!=0){ + + if(DownConvertMode==0){ + if (FlagMeter==2) //if in big meters, shut off + { + if (_Mode != X_Y){ + if((ListLogic())&&(EditListActive(1)))PrintDir(0,0,3); + DisableMeter(); + if((_4_source==SPEC_A)||(_4_source==SPEC_B)||(_Mode==NORHLD))Clear_Meter_Area(); + }else{ //toggle the 2 meters in xy mode, instead of shutting meters off + FlagMeter=1; + EnableMeter(); + } + goto bypasslongpress; + } + else + { + if (FlagMeter==1){ //if in small meters go to big meters + if(Current > METER_3)Current=METER_3; + if(UpdateMeter==4){ + if(Current==METER_1)Current=METER_2; + }else{ + if(Current==METER_0)Current=METER_1; + if((Current < METER_0)&&(Current>T_VERNIE))Current=T_VERNIE; //if not in meter item select mode + } + FlagMeter=2; + } + if( (FlagMeter==0)&&(ListLogic())&&(EditListActive(1)) )PrintDir(0,0,3); + EnableMeter(); //if meters off, go to small meters + goto bypasslongpress; + } + }else goto bypasslongpress; + + } //if get key status + } //while delay count + + Beeper(125); BackLight(1); + + while ((Delay_Cnt >0)&&(Delay_Cnt <=1000)){ // long press + if(Delay_Cnt<875)BackLight(0); + + if((__Get(KEY_STATUS)& KEY3_STATUS)!=0){ + + if(Title[OUTPUT][0].Value!=6){ //if generator is not turned off + Print_Str(15, 90, 0x0405, PRN, (char*)DisableSTR); + Delayms(900); + Key_Buffer=0; + __Set(BACKLIGHT, 4); // set backlight dim + while(1){if(Key_Buffer>0)break;} + InitXY=1; + Key_Buffer=0; + BackLight(0); + PD_Cnt = 600; + goto BypassUpdate; + }else{ + Print_Str(119, 90, 0x0405, PRN, "LONG PRESS-STANDBY"); + Delayms(900); + PD_Cnt = 0; + __Set(BACKLIGHT, 0); // turn off the backlight + __Set(STANDBY, EN); // enter low power states + goto bypasslongpress; + } + + } //IF GET KEY STATUS + } // WHILE DELAY COUNT... + + Beeper(60); + if(Delay_Cnt == 0){ //extra long press + for(i=0;i<3;i++)_Curr[i].Flag |= UPDAT; + SaveCurrent[0]=Current; //save current menu item position + SaveCurrent[1]=_Det; + Current=FILE; + Title[FILE][0].Value=0; //save file + Title[FILE][2].Value=4; //conf file + _Curr[1].Value=ConfigFileNumber; + + if(ListOverride){ + _Det=3; + ProcessEditName(); + }else _Det=1; + + for(i=0;i<3;i++)Title[FILE][i].Flag|=UPDAT; + + } + }else{ //Current = file + + if(_Curr[2].Value==CFG){ + if(_Curr[0].Value == SAVE){ + if(_Det==3){ + Edited=1; + ProcessFileName(); + for(i=0;i<8;i++)LastAccessedConfig[i]=SelectedFileName[i]; + ProcessEditName(); //loads processed name into edit function + ListOverride=1; + }else ListOverride=0; + + i=ConfigFile(SAVE); + Edited=0; + FileMessage(i); + }else{ + if ((Current==FILE)&&(_Det==DIR)){ + for(j=0;j<8;j++)LastAccessedConfig[j]=SelectedFileName[j]=Label[Title[9][3].Value][j]; + } + j=Title[FILE][3].Value; //keep present hilighted list position + i=ConfigFile(LOAD); + if(ListOverride){ //keep list after loading new config from it + Title[FILE][3].Value=j; + Detail[9]=3; + ProcessEditName(); //loads processed name into edit function + } + for(j=0;j<3;j++)Title[FILE][j].Flag|=UPDAT; + } + + } + } + + } //if key buffer + + //------------------------------------------------------------------------------------------------------------- + // ===--- TASTO 4 PREMUTO --==== + //Key 4 short press has been swapped with center press left toggle +if(Key_Buffer== KEY4){ + + Delay_Cnt = 1500; + while (Delay_Cnt > 1000) + { + if((__Get(KEY_STATUS)& KEY4_STATUS)!=0){ + + _Curr[_Det].Flag |= UPDAT; + + if((Current==FILE)&&(_Det==DIR)){ + if(ListLogic())PrintDir(0,0,3); //clear file list when leaving + Title[FILE][1].Flag |=UPDAT; + if((_Mode==X_Y)&&(Title[9][0].Value==1))InitXY=1; + } + + if((Current==OUTPUT)&&((_Kind==5)||(_Kind==7)||(_Kind==8))){ + if(_Det==0)_Det=1;else _Det=0; + goto BypassUpdate; + } + + if((Current==OUTPUT)&&(_Kind==6)){_Det=0;goto BypassUpdate;} + + if ((Current == TRACK3)&&(_Det == 0))_Det = 2; + + if ((Current == TRACK4)&&(_Det == 0)){ + if(_4_source>11)_Det=1;else _Det=2; //in fft modes, to engage MAG modes + if(_4_source>10)goto bypasslongpress; //in fft modes, 11=spec + }else if ((Current == TRACK4)&&(_Det == 2)&&(_4_source>9)){ //in map mode + _Det = 0; + goto bypasslongpress; + } + + if(Current==6){if(_Mode==X_Y){if(_Det==1)_Det=2;}else if((_Det==2)&&(_Mode!=NORHLD))_Det=3;} + + if ((((Options&1)==0)||(_Mode==AUTO)||(_Mode==X_Y)||(OsBufferLogicFlag)||(_Mode==SGL)|| + (_Mode==SCAN)||(_T_base>9))&&(Current == TRIGG)&&(_Det==2))_Det=3; //skip over det3 (will go to 0) + + + if((FlagMeter==0)&&((Current==V_VERNIE)||(Current==T_VERNIE))&&(_Det==V2)){ //skip meter select if meters off + _Curr[_Det].Flag |= UPDAT; + _Det=0; //go to V1 or T1 = 0 + }else{ + if(Current < METER_0){ // change the Detail + _Curr[_Det].Flag |= UPDAT; + if(_Det < 3) _Det += 1; + else _Det = 0; + if(Current == OUTPUT){if(Title[OUTPUT][KIND].Value==PWM){if(_Det==OUTATT)_Det=0;}else if(_Det==DUTYPWM)_Det+=1;} + if(_Curr[_Det].MARK & NOT) _Det = 0; + if(_Curr[_Det].MARK & NUM2) _Det = 0; + if((_Curr[_Det].MARK & NUM3)&&(Current != FILE)&& (Current != OUTPUT) ) _Det = 0; + + if((Current==FILE)&&(_Det==3)){ + if((_Curr[2].Value==7)&&(Title[FILE][0].Value==0))_Det=0; //do not edit ROM backup file + } + + _Curr[_Det].Flag |= BLINK; + } else { // change the measurement object + + if(Meter[Current-METER_0].Item>1){ //don't change source for VBT AND FPS (items 0 and 1) + Meter[Current-METER_0].Flag |= UPDAT; + + if((Meter[Current-METER_0].Item>VPP)||(Meter[Current-METER_0].Item==FRQ)){ + if(Meter[Current-METER_0].Track <= TRACK4) + Meter[Current-METER_0].Track += 1; + if(Meter[Current-METER_0].Track > TRACK4) + Meter[Current-METER_0].Track = TRACK1; + }else{ + if(Meter[Current-METER_0].Track==TRACK1) + Meter[Current-METER_0].Track=TRACK2; + else Meter[Current-METER_0].Track=TRACK1; + } + } + }//if current, else (if in meter section) + } + + if(EditListActive(0)){ //filename edit + CharValue=EditChar[CharIndex][0]; + } + + goto bypasslongpress; + } //if get key status + } //while delay count >0 + + Beeper(125); BackLight(1); + + while ((Delay_Cnt >0)&&(Delay_Cnt <=1000)){ // long press + if(Delay_Cnt<875)BackLight(0); + if((__Get(KEY_STATUS)& KEY4_STATUS)!=0){ + _Curr[_Det].Flag |= UPDAT; + + + if((_4_source>11)&&((DownConvertMode)||(FFTt1Mode))){ + if((Current==3)&&(_Det==1)){ + Current=10; + _Det=0; + goto bypasslongpress; + }else if((Current==10)&&(_Det==0)&&(Detail[3]==1)){ + Current=3; + _Det=1; + goto bypasslongpress; + } + } + + if(((ListLogic())||(_Mode==X_Y))&&(EditListActive(1))){ + PrintDir(0,0,3); //clear file list when leaving + if(_Mode==X_Y)InitXY=1; + } + if (Current==TRACK1)LastSelected=1; + if (Current==TRACK2)LastSelected=2; + Current = T_BASE; + _Det = BASE; + CurDetailUpdate(); + goto bypasslongpress; + } //if key status + } //while delay cnt + + Beeper(60); + if(Delay_Cnt == 0){ + DisableCursorTimer=1; + + if (CurDefTime==0){ + CurDefTime=1; + ClearMeters(); + if(Current != FILE){ + MessageHandler(5); //cur select meters on + } + Print_Str(153,216,0x0405,PRN, "X"); + }else{ + CurDefTime=0; + if(Current != FILE){ + MessageHandler(6); //cur select meters off + } + Print_Str(153,216,0x0405,PRN, " "); + } + } //if delay cnt + } //if key buffer + +//---------------------------------------------------------------------------------------------------------------- + if(Key_Buffer == K_INDEX_DEC){ // ===--- TASTO 5 --- PREMUTO --==== + + if((((_Mode==SCAN)&&(!ChartLogic()))||((ChartLogic())&&(FrameMode>0))) + &&(Current==T_BASE)&&(_Det==2))goto BypassUpdate; //bypass changing Xpos in chart mode short buffers + + if((_4_source>11)&&(Current==3)&&(_Det==1)){ + if(DownConvertMode){ + if(DownConvert==5)DownConvert=2; + else if(DownConvert==50)DownConvert=20; + else if(DownConvert==500)DownConvert=200; + else if(DownConvert>1)DownConvert/=2; + DownConvertShiftEnable=1; + }else if(FFTt1Mode){ + if(_T1>0)_T1--; + if(_T1>2)_T1-=CursorSpeedLogic(1); + } + goto BypassUpdate; + } + + if((DownConvertMode)&&(Current==T_BASE)&&(_Det==BASE))goto BypassUpdate; + + if((Current==T_BASE)&&(_Det==MODE)&&(FPGAver>0)&&(AutoTrigSelect)){ + if(FreeRunEnable>0)FreeRunEnable--; + goto BypassUpdate; + } + + if((OffsetSelect==1)&&(Current>1)&&(!((Current==T_BASE)&&(_Det==1)&&(FPGAsubVer)&&(FPGAosFlag)))){ + if(ADCoffset>0)ADCoffset--; + Update_Range(); + goto bypasslongpress; + } + + if((OffsetSelect==2)&&(Current>1)&&(!((Current==T_BASE)&&(_Det==1)&&(FPGAsubVer)&&(FPGAosFlag)))){ + if(PPM_Comp>-999)PPM_Comp--; + goto bypasslongpress; + } + + if(EditListActive(1)){ //file directory read + if(Title[9][3].Value>0)Title[9][3].Value--;else + {if(DirRange>0)DirRange--;} + goto bypasslongpress; + } + + if(EditListActive(0)){ //filename edit + if((CharValue>65)&&(CharValue<91))CharValue--; //letters + else if((CharValue>47)&&(CharValue<57))CharValue++; + else switch(CharValue){ + case 65: CharValue=32;break; + case 32: CharValue=48;break; + case 63: CharValue=48;break; //63= non available char flag + case 57: CharValue=95;break; + case 95: CharValue=45;break; + case 45: CharValue=41;break; + case 41: CharValue=40;break; + case 40: CharValue=38;break; + case 38: CharValue=37;break; + } + + EditChar[CharIndex][0]=CharValue; + UpdateEditBox(0); + goto bypasslongpress; + } + + if((OS_RateSelect)&&(Current==T_BASE)&&(_Det==1)&&(OSBufferLogic()) + &&(FPGAsubVer)&&(FPGAosFlag)){ //Tbase RANGE sub menu + if(OS_Range<5)OS_Range++; + Update_Base(); + goto BypassUpdate; + } + + if((Current==T_BASE)&&(_Det==BASE)&&(ChartLogic())&&(AutoSaveSelect)){ + if(AutoSaveSelect==1){if(AutoSaveBuf>0)AutoSaveBuf--;} + if(AutoSaveSelect==2)ChartMode=0; + goto BypassUpdate; + } + + if (_Mode == X_Y){ + if((Current == TRACK1)&&(_Det == POSI) && (OffsetX>45)) OffsetX=OffsetX-2; + if((Current == TRACK2)&&(_Det == POSI) && (OffsetY>30)) OffsetY=OffsetY-2; + } + SelUpdate(POSI); //clear min/max hold + + if(((Current==TRACK1)||(Current==TRACK2))&&(_Det==1))AlignTbaseSweep(0); //changing coupling mode + + if((Current==5)&&(_Det==1)&&(_Kind==8)){ //uart gen mode + if(GenUartAdj==0){ //adjust baud index, translate to baud rate + if(GenBaudAdjSpeed){ //fast mode + if(GenBaudIndex<800){ //set up break points for fast adj mode + GenBaudIndex+=20; + }else if(GenBaudIndex<2800){ + GenBaudIndex+=50; + }else if(GenBaudIndex<12970){ + GenBaudIndex+=100; + }else if(GenBaudIndex<14970){ + GenBaudIndex+=50; + }else{ + if(GenBaudIndex<15851)GenBaudIndex+=20;else GenBaudIndex=15871; + } + }else{if(GenBaudIndex<15871)GenBaudIndex++;} //fine mode + } + if(GenUartAdj==1)if(GenUartMode>1)GenUartMode--; + if(GenUartAdj==2)GenUartStopBits=0; + if(GenUartAdj==3)GenUartCont=0; + goto bypasslongpress; + } + + if((Current==BK_LIGHT)&&(HboldAdjust)){ + if(Hbold<2)Hbold++; + goto bypasslongpress; + } + + if((Current==BK_LIGHT)&&(FastDimAdjust)){ + if(FastDim>0)FastDim--; + goto bypasslongpress; + } + + if((Current==VOLUME)&&(AdjBeepLevel)){ + if(LoBeepLevel<9)LoBeepLevel++; + goto bypasslongpress; + } + + if((T1Start)&&(Current==T_VERNIE)&&((_Det==T1)||(_Det==T2))&&(Title[TRACK1][COUPLE].Value>2)&&(Title[TRACK1][COUPLE].Value<5)){ //in serial decode, tie T1 to T2 + if((_T1>0)&&(_T2>0)){_T1--;_T2--;} + goto bypasslongpress; + } + + if((SpiLogic())&&(Current==TRACK1)&&(_Det==1)&&(SpiAdj)){ + if(SpiAdj==1){ + if(SpiMode>0)SpiMode--; + } + if(SpiAdj==2)SpiBitOrder=1; + if(SpiAdj==3){ + if(SpiNumBits==2)SpiNumBits=0; else { + if(SpiNumBits==0)SpiNumBits=-3; else if(SpiNumBits>(-145))SpiNumBits--; + } + } + goto BypassUpdate; + } + + if((UartLogic())&&(Current==TRACK1)&&(_Det==1)&&(DataAdj==1)){ + if(DataSize>5){ + if(DataSize==15)DataSize=9;else DataSize--; + } + goto BypassUpdate; + } + + if((Current==OUTPUT)&&(_Det==0)&&(_Kind==0)){ //clear buffer before changing to Arbt + for(i=0;i<720;i++)ATT_DATA[i]=2048; + } + + if((Current==OUTPUT)&&(_Det==1)&&(GenAdjustMode==1)&&((_Kind<5)||(_Kind==7))){ //changing sweep or burst rate + + if(_Kind==7){ + if(GenFreqShift<100)GenFreqShift++; + OutputAdjust(); + }else{ + if((Sweep==1)||(Sweep==2)){ + if(SweepIndex>0)SweepIndex--; + TIM_2IRQControl(); + AlignTbaseSweep(2); + if(Title[TRIGG][SOURCE].Value==4) Update_Trig(0); else Update_Trig(1); + }else if(Sweep==3){ + + if((SweepIndex<2)&&(_Frqn>5)){ + if(FineAdjust>0)FineAdjust--;else BurstAdjust(0); + }else{if(_Frqn<14)BurstAdjust(0);else{if(FineAdjust>0)FineAdjust--;else BurstAdjust(0);}} + + TIM_2IRQControl(); + if(Title[TRIGG][SOURCE].Value==4) Update_Trig(0); else Update_Trig(1); + }else{ + if(GenFreqShift<100)GenFreqShift++; + OutputAdjust(); + } + } + + goto BypassUpdate; + } + + if(Current < METER_0){ + + for (i=0;i<4;i++){ + if ((Current==i)&&(_Det == SOURCE)){ //ch selected and submenu on source + if (Title[i][SOURCE].Value == 1){ //about to be shut down + if (Title[TRIGG][SOURCE].Value ==i){ //if trig selected + UpdateTriggerMem(); + TriggFlagUpdate(); + Update_Trig(1); + } //if not selected, about to be shut down, purge # from buffer + TrigMemory(i); + } //Title[i][source] + } //current= + } //for + + if((Current == TRIGG)&&(Detail[Current]==2)){ // trigger level adjustment + + j=1;if(SetLowVolume){j=2;if(FlagFrameMode==0)j++;} + for(i=0;i 0)V_Trigg[0].Value--; + if(V_Trigg[1].Value > 0)V_Trigg[1].Value--; + }else{ + if(V_Trigg[_Trigg[SOURCE].Value].Value > 0) + V_Trigg[_Trigg[SOURCE].Value].Value--; + } + } + + } else if ((Current == TRIGG)&&(_Det == 3)){ //trigger holdoff + if ((FrameMode==2)&&(_T_base < 10)){ + if (Title[7][3].Value>30) Title[7][3].Value-=30; else Title[7][3].Value=0; + Title[7][3].XPOS=GetHoldoffIndPos(); + SelectiveUpdate=0x1E; //do not update anything + } + } else if((Current == BK_LIGHT)||(Current == VOLUME)){// adjust backlight or volume + if(_Curr[1].Value > 0) _Curr[1].Value--; + } else if((Current == T_BASE)&&(_Det == XPOSI)){ // X_POSI adjustment + ClearMeters(); //clears meters if untriggered in NORH + + _X_View.Flag |= UPDAT; // refresh X_View + if (XposRef>150){ + if(SetLowVolume){ + if(Key_Mid_Speed)_Curr[_Det].Value-=6;else _Curr[_Det].Value-=30; + }else _Curr[_Det].Value--; + }else if(_Curr[_Det].Value>0){ + if(SetLowVolume){ + if(XposRef>30){ + XposRef-=4; + goto bypasslongpress; + } else _Curr[_Det].Value--; + }else _Curr[_Det].Value--; + } + XposRef=GetXposRef(_Curr[_Det].Value); + + } else if((Current==OUTPUT)&&(_Det==2)){ // PWM duty% adjust + if(PWAdjustMode){ + PWMdutyControl(1); + goto BypassUpdate; + }else {if(_Curr[_Det].Value>300)_Curr[_Det].Value-=300;else _Curr[_Det].Value=0;} + } else { // for other current item + if ((Current==TRACK1)&&(_Det==SOURCE)){ + + if(_1_source==0){ //ch A about to be turned on, else off + LastSelected=1; + SelectiveUpdate|=0x20; + AlignTbaseSweep(4); + }else if(_1_source==1)AlignTbaseSweep(5); + } + if ((Current==TRACK2)&&(_Det==SOURCE)){ + + if(_2_source==0){ //ch B about to be turned on, else off + LastSelected=2; + SelectiveUpdate|=0x40; + AlignTbaseSweep(4); + }else if(_2_source==1)AlignTbaseSweep(5); + } + + if((_Mode==NORHLD)&&(Current==6)&&(_Det==3)){ + if(PerstFrameNumber>0)PerstFrameNumber-=((PerstFrameNumber/65)+1); + }else{ + if ((Current == T_BASE)&&(_Det == BASE)){ + + if(_Curr[_Det].Value==0){ + + if((_Mode==SCAN)&&(SubIndex<13)){ + SubIndex++; + if(SubIndex==1)InitChart(); + } + + }else if(_Curr[_Det].Value>0)_Curr[_Det].Value--; + }else{ + + if(_Curr[_Det].Value > 0){ + _Curr[_Det].Value--; + if((Current==6)&&(_Det==3))_Curr[_Det].Value-=(_Curr[_Det].Value/65); //establish 3 breakpoints for speed change + SelUpdate(RANGE); + if ((Current<2)&&(_Det==RANGE))Update_Range(); + } + else if(_Curr[_Det].MARK & CIRC) _Curr[_Det].Value =_Curr[_Det].Limit; + + if(((Current==0)||(Current==1))&&(_Det==0)&&(_Mode==X_Y)){ + if(Title[Current][0].Value>0)Title[Current][0].Value--; + } + + } + } + + if((Current == TRIGG)&&(Detail[Current]==0)){ //trig source has just been changed + if(Title[TRIGG][SOURCE].Value==4){ //changed to AltAB + if(_Mode==X_Y){ + _Curr[_Det].Value--; + }else{ + OldMode=Title[T_BASE][MODE].Value; //save prev mode + ChannelStatus(0); //save status + } + } + if((Title[TRIGG][SOURCE].Value==3)&&(_Mode!=X_Y)){ //changed from AltAB + Title[T_BASE][MODE].Value=OldMode; //reset to prev mode + Title[T_BASE][MODE].Flag |= UPDAT; + ChannelStatus(1); //save status + Title[TRACK1][RANGE].Flag |= UPDAT; Title[TRACK2][RANGE].Flag |= UPDAT; + } + Title[T_BASE][BASE].Flag |= UPDAT; + } + + if ((Current == T_BASE)&&(_Det == BASE)){ + if(Sweep){if(Title[TRIGG][SOURCE].Value==4) Update_Trig(0); else Update_Trig(1);} + if(!OSBufferLogic()){if((__Get(FIFO_START)!=0)||((_Mode!=NORH)&&(_Mode!=NORHLD)))__Set(TRIGG_MODE, UNCONDITION);} //temporarily setting this allows x_attr to properly update if in untriggered condition + } + if((FrameMode<2)&&(Current == T_BASE)&&(_Det == BASE)){ + Tmp=GetXposRef(_X_posi.Value); + if (Tmp>150) XposRef=Tmp; //only align trig vernier when on screen when changing time bases + } + } + + if((Current==OUTPUT)&&(_Det==3)&&(Sweep)){ + if(FrameEndFlag)WaveGen(); + goto BypassUpdate; + } + + if((Current==OUTPUT)&&(_Det==1))PWMscaleReset(1); + + if((Current == T_BASE)&&(_Det == MODE)){ // T_BASE MODE selection //at this point mode has been changed + if (_Mode==SCAN) {if (FrameMode>0)ShortBuffXpos=XposRef; else OldPosi=GetXpos(XposRef);} //previous mode was auto + if (_Mode==X_Y) {if (FrameMode>0)XposRef=ShortBuffXpos; else XposRef=GetXposRef(OldPosi);} //previous mode was scan + + Title[RUNNING][STATE].Value = RUN; // STATE = RUNNING + Title[RUNNING][STATE].Flag |= UPDAT; // refresh RUNNING STATE + } + if((Current == OUTPUT)&&(_Kind<4)){ + if (Title[OUTPUT][FRQN].Value > 16) + Title[OUTPUT][FRQN].Value = 16; // upper limit of the analog signal frequency is 20KHz + } + + if(Current == FILE){ //changing file extensions + if(_Curr[0].Value == LOAD){ + //if(_Curr[2].Value == CSV){_Curr[2].Value = BUF;ResetEditList();} + //if(_Curr[2].Value == 7 ){_Curr[2].Value = 6 ;ResetEditList();} + } + if(_Curr[0].Value == 0){ //SAVE (edit filename) + if((_Curr[2].Value == 5)||(_Curr[2].Value == 6)){_Curr[2].Value = 4;ResetEditList();} + } + } + + if((Current == FILE)&&(_Curr[2].Value == CFG)) if(_Curr[1].Value > 9)_Curr[1].Value=9; + if((Current==FILE)&&(_Det==2))ResetEditList(); //reset list and edit defaults when changing file types + for(i=0;i<4;i++)_Curr[i].Flag |= UPDAT; + } else { + + Meter[Current-METER_0].Flag |= UPDAT; + + if(Meter[Current-METER_0].Item >VBT) + Meter[Current-METER_0].Item -= 1; + else + Meter[Current-METER_0].Item = TL; + + if((Meter[Current-METER_0].Track>1)&&(Meter[Current-METER_0].Track<4)){ + if(Meter[Current-METER_0].Item ==VPP)Meter[Current-METER_0].Item =FRQ; + if(Meter[Current-METER_0].Item ==RMS)Meter[Current-METER_0].Item =FPS; + } + + if(Meter[Current-METER_0].Item == FPS){ + SaveCurrent[0]=Current; + SaveCurrent[1]=Meter[Current-METER_0].Track; + Meter[Current-METER_0].Track = 4; + } + + if(Meter[Current-METER_0].Item == TL){ + if(Current==SaveCurrent[0]) + Meter[Current-METER_0].Track =SaveCurrent[1]; + else + Meter[Current-METER_0].Track = UpdateMeter; + } + + } + if(_Curr[_Det].Value>2)_Curr[_Det].Value-=(CursorSpeedLogic(0)); + } + //--------------------------------------------------------------------------------------------------------------------- + if(Key_Buffer == K_INDEX_S) + { // ===--- TASTO 5 centrale PREMUTO --==== + //center press left toggle has been swapped with key 4 short press + + DisableCursorTimer=1; + if ((Current != FILE)) { + + Delay_Cnt = 1500; + while (Delay_Cnt > 1000){ + + if((__Get(KEY_STATUS)& K_INDEX_S_STATUS)!=0){ + + if(OffsetSelect){ + OffsetSelect^=0x03; //toggle between =1 and =2 + goto bypassOSselect; + } + + if((Current==TRIGG)&&(_Det==2))DisableCursorTimer=0; + //SPECIAL FUNCTIONS FOR LEFT TOGGLE CENTER PRESS + if(LeftToggleSpecialFunctions())goto bypasslongpress; + + j=0; + for (i=0;i<4;i++){ + if(Title[i][SOURCE].Value != HIDE)j++; + } + if(j>0){ + if ((((_4_source==11)||(_4_source>13))&&(_1_source!=HIDE))|| + (((_4_source==10)||(_4_source==12)||(_4_source==13))&&(_2_source!=HIDE)))j--; + } + + if (j>2){ //if more than 2 active channels, use as shortcut to trigg source select + _Curr[_Det].Flag |= UPDAT; + for (i=0;i<4;i++){ + if (Current==i){ //================================================================ + if (Title[i][SOURCE].Value != HIDE){ + if (Title[TRIGG][SOURCE].Value !=i){ //if not already selected + for (j=0;j<3;j++) PreviousTrigSelect[j]=PreviousTrigSelect[(j+1)]; //lifo stack + PreviousTrigSelect[3]=Title[TRIGG][SOURCE].Value; //save previous + Title[TRIGG][SOURCE].Value = i; //set trig to selected track + if((i==3)&&((_4_source==11)||(_4_source>13)))Title[TRIGG][SOURCE].Value=0; //set to FFT channels + if((i==3)&&((_4_source==10)||(_4_source==12)||(_4_source==13)))Title[TRIGG][SOURCE].Value=1; + Update_Trig(1); + goto BypassShortcut; //if new source selected, do not use as shortcut + } + } //if turned on + } //if current + } //check all channels + + Current=TRIGG; //shortcut to trigg source select + _Det=SOURCE; +BypassShortcut: + TriggFlagUpdate(); + goto bypasslongpress; + } + Title[T_BASE][BASE].Flag |= UPDAT; + if((_Mode!=X_Y)&&(Title[TRIGG][SOURCE].Value==1)&&(Title[TRACK1][SOURCE].Value!=0)&&(Title[TRACK2][SOURCE].Value!=0)&&(Title[TRACK3][SOURCE].Value==0)&&(Title[TRACK4][SOURCE].Value==0)){ + OldMode=Title[T_BASE][MODE].Value; //if 2 analog chs are the only ones on and trigger source = chB + Title[TRIGG][SOURCE].Value=4; //cycle to include A&B mode + Update_Trig(1); + }else{ //cycle between any other 2 channels + for (i=0;i<4;i++){ + if (Title[i][SOURCE].Value != HIDE){ + if (Title[TRIGG][SOURCE].Value !=i){ //if not already selected + if(Title[TRIGG][SOURCE].Value==4){ //do not save A&B position + Title[T_BASE][MODE].Value=OldMode; + Title[T_BASE][MODE].Flag |= UPDAT; + Update_Base(); + }else{ + for (j=0;j<3;j++) PreviousTrigSelect[j]=PreviousTrigSelect[(j+1)]; //lifo stack + PreviousTrigSelect[3]=Title[TRIGG][SOURCE].Value; //save previous + } + Title[TRIGG][SOURCE].Value = i; //set trig to selected track + if((i==3)&&((_4_source==11)||(_4_source>13)))Title[TRIGG][SOURCE].Value=0; //set to FFT channels + if((i==3)&&((_4_source==10)||(_4_source==12)||(_4_source==13)))Title[TRIGG][SOURCE].Value=1; + TriggFlagUpdate(); + Update_Trig(1); + goto bypasslongpress; + } + } + } + } + + goto bypasslongpress; + } // if keystatus + } // while delay count + + Beeper(125); BackLight(1); + + while ((Delay_Cnt >0)&&(Delay_Cnt <=1000)){ // long press, change meter pages + if(Delay_Cnt<875)BackLight(0); + if((__Get(KEY_STATUS)& K_INDEX_S_STATUS)!=0){ + + if (FlagMeter>0){ + SaveCurrent[0]=0; //erase item source memory + SaveCurrent[1]=0; + if (UpdateMeter<4){ + if((FlagMeter==2)&&(UpdateMeter==3)&&(Current==METER_1))Current=METER_2; + UpdateMeter=UpdateMeter+1; + if ((_Mode==X_Y)&&(UpdateMeter>1)) UpdateMeter=4; + } + else{ //UpdateMeter==4, default pages for both meter types + if (FlagMeter==2){ + ClearScreenArea(314,399,125,180); + if((Current < METER_0)&&(Current>T_VERNIE))Current=T_VERNIE; + if((Current==METER_0)||(Current==METER_2))Current=METER_1; + } + UpdateMeter=0; + } + UpdateMeterPage(); + + }else{ // flagmeter=0 //toggle wave calibration + + if (CalFlag==0){ + CalFlag=1; + if(Current != FILE){ + MessageHandler(1); //wave calibration on + } + Print_Str(137,216,0x0405,PRN, "C"); + }else{ + CalFlag=0; + if(Current != FILE){ + MessageHandler(2); //wave calibration off + } + Print_Str(137,216,0x0405,PRN, "U"); + } + + } + goto bypasslongpress; + + } //if keypress + } // delay cnt + + Beeper(60); + if(Delay_Cnt == 0){ //extra long press + if ((Options&1)==0) { + Options|=1; + if (((_Mode==NORH)||(_Mode==NORHLD)||(_Mode==NORC))&&(_T_base < 10)&&(!OsBufferLogicFlag)){Current = TRIGG; _Det = 3;} + Title[Current][_Det].Flag |= UPDAT; + MessageHandler(7); //trigger holdoff on + }else{ + Options&=0xFE; + if ((Current==TRIGG)&&(_Det==3)) _Det=0; + Title[Current][_Det].Flag |= UPDAT; + MessageHandler(8); //trigger holdoff off + } + } + } // if current + + if(Current == FILE){ + Print_Str(230, 0, (SCRN<<8)+ TEXT1, PRN, " > "); + if(_Curr[0].Value == SAVE){ + + if(_Det==DIR){ + ProcessFileName(); + } + + switch (_Curr[2].Value){ + case BMP: + i = Save_Bmp(_Curr[1].Value); + if(_Det!=3)_Curr[1].Value++; + break; + case DAT: + i=Save_Dat(_Curr[1].Value); + if(_Det!=3)_Curr[1].Value++; + Delayms(900); + break; + case BUF: + i=Save_Buf(_Curr[1].Value); + if(_Det!=3)_Curr[1].Value++; + break; + case CSV: + i=Save_Csv(_Curr[1].Value); + if(_Det!=3)_Curr[1].Value++; + break; + case 4: //configuration file + if(_Det==3){ + Edited=1; + for(i=0;i<8;i++)LastAccessedConfig[i]=SelectedFileName[i]; + ListOverride=1; + ProcessEditName(); //loads processed name into edit function + }else ListOverride=0; + i=ConfigFile(SAVE); + Edited=0; + break; + case 5: //cannot save arb or uart files + case 6: + i=200; + break; + case 7: + i=Save_Img(); //ROM backup image file + } + + } else { //current = load + +reload: + if ((Current==FILE)&&(_Det==DIR)){ + for(i=0;i<8;i++)SelectedFileName[i]=Label[Title[9][3].Value][i]; + } + + i=0; + if(_Curr[2].Value==DAT) i = Load_Dat(_Curr[1].Value); + + + if(_Curr[2].Value==BUF){ + if(DownConvertMode){DownConvertMode=0; DownConvertRestore();} + i=Load_Buf(_Curr[1].Value); + if(_Det!=DIR)_Curr[1].Value++; + else{if(Title[9][3].Value<14)Title[9][3].Value++;else DirRange++;} + TempKp1=_Kp1; + if(ChartLogic())ClearLeadingEdge=0; + } + + + if(_Curr[2].Value==BMP){ + if(DownConvertMode){DownConvertMode=0; DownConvertRestore();} + i = Load_Bmp(_Curr[1].Value); + if((Current==FILE)&&(_Det==DIR)){ + if(i==0)for(j=0;j<8;j++)EditChar[j][0]=SelectedFileName[j]; + if(Title[9][3].Value<14)Title[9][3].Value++;else DirRange++; + + ReadDir((char*)Ext); + if((Label[Title[9][3].Value][0]==0)||(Label[Title[9][3].Value]==NoneStr)){ + if(Title[9][3].Value>0)Title[9][3].Value--; + } + + }else _Curr[1].Value++; + + Key_Buffer=0; + + + if(i==OK){ + FileMessage(i); + while (1) { + + if (Key_Buffer>0){ + App_init(0); + Delayms(150); + Config_init(); + + Update_View_Area(); + if(Key_Buffer==K_INDEX_S)goto reload; + if(Key_Buffer == K_ITEM_S){ + + if((Current==FILE)&&(_Det==DIR)){ //use block to allow prev BMP load in list + + if(Title[9][3].Value>0){ + Title[9][3].Value--; + for(j=0;j<8;j++){if(SelectedFileName[j]!=Label[Title[9][3].Value][j])break;} + if(j>6){ + if(Title[9][3].Value>0)Title[9][3].Value--; + else if(DirRange>0)DirRange--; + } + }else if(DirRange>0){ + DirRange--; + } + + }else{ + if(_Curr[1].Value>1)_Curr[1].Value-=2; + else _Curr[1].Value=0; + } + + goto reload; + } + if(FlagMeter)Clear_Meter_Area(); + goto bypasslongpress; //break; + } + } + }else if(FlagMeter){EnableMeter();Display_Title();} + + } + + if(_Curr[2].Value==CFG){ + j=Title[FILE][3].Value; //keep present hilighted list position + i=ConfigFile(LOAD); + Current=FILE; //stay in file menu if loading file with button 5 + if(ListOverride){ //keep list after loading new config + Title[FILE][3].Value=j; + for(j=0;j<8;j++)LastAccessedConfig[j]=SelectedFileName[j]; + _Det=3; + ProcessEditName(); //loads processed name into edit function + } + for(j=0;j<3;j++)Title[FILE][j].Flag|=UPDAT; + if(i == 0)goto bypasslongpress; + } + + if(_Curr[2].Value==5){ //load arbt file + i = Load_Arbt(_Curr[1].Value); + Update_Output(); + } + + if(_Curr[2].Value==6){ //load uart file + i = Load_Uart(_Curr[1].Value); + if(_Kind==8)StartUart=1; + } + + if(_Curr[2].Value==CSV){ //load CSV file not available + i = 200; + } + + if(_Curr[2].Value==7){ //load bin image not available + i = 200; + } + + if((_Det==DIR)&&(_Curr[2].Value<3)){ //use last loaded filename as edit default + if(i==0)for(j=0;j<8;j++)EditChar[j][0]=SelectedFileName[j]; + } + + }//if else (current=load) + + FileMessage(i); + } + + } + + //---------------------------------------------------------------------------------------------------------------- + if(Key_Buffer == K_INDEX_INC){ // ===--- TASTO 5 +++ PREMUTO --==== + + if((((_Mode==SCAN)&&(!ChartLogic()))||((ChartLogic())&&(FrameMode>0))) //no xpos in SCAN mode except large buf chart mode + &&(Current==T_BASE)&&(_Det==2))goto BypassUpdate; + + if((_4_source>11)&&(Current==3)&&(_Det==1)){ + if(DownConvertMode){ + if(DownConvert==2)DownConvert=5; + else if(DownConvert==20)DownConvert=50; + else if(DownConvert==200)DownConvert=500; + else if(DownConvert<1010)DownConvert*=2; + DownConvertShiftEnable=1; + goto BypassUpdate; + }else if(FFTt1Mode){ + if(_T1<255)_T1++; + if(_T1<253)_T1+=CursorSpeedLogic(1); + } + } + + + if((DownConvertMode)&&(Current==T_BASE)&&(_Det==BASE))goto BypassUpdate; + + if((Current==T_BASE)&&(_Det==MODE)&&(FPGAver>0)&&(AutoTrigSelect)){ + if(FreeRunEnable==0)FreeRunEnable++; + goto BypassUpdate; + } + + if((OS_RateSelect)&&(Current==T_BASE)&&(_Det==1)&&(OSBufferLogic()) + &&(FPGAsubVer)&&(FPGAosFlag)){ //Tbase RANGE sub menu + if(OS_Range>0)OS_Range--; + Update_Base(); + goto BypassUpdate; + } + + if((OffsetSelect==1)&&(Current>1)&&(!((Current==T_BASE)&&(_Det==1)&&(FPGAsubVer)&&(FPGAosFlag)))){ + if(ADCoffset<54)ADCoffset++; + Update_Range(); + goto bypasslongpress; + } + + if((OffsetSelect==2)&&(Current>1)&&(!((Current==T_BASE)&&(_Det==1)&&(FPGAsubVer)&&(FPGAosFlag)))){ + if(PPM_Comp<999)PPM_Comp++; + goto bypasslongpress; + } + + if(EditListActive(1)){ //file directory read + if(Title[9][3].Value<14)Title[9][3].Value++;else DirRange++; + goto bypasslongpress; + } + + if(EditListActive(0)){ //filename edit + + if((CharValue>64)&&(CharValue<90))CharValue++; + else if((CharValue>48)&&(CharValue<58))CharValue--; + else switch(CharValue){ + case 32: CharValue=65;break; + case 63: CharValue=65;break; //63= non available chars + case 37: CharValue=38;break; + case 38: CharValue=40;break; + case 40: CharValue=41;break; + case 41: CharValue=45;break; + case 45: CharValue=95;break; + case 95: CharValue=57;break; + case 48: CharValue=32;break; + } + + EditChar[CharIndex][0]=CharValue; + UpdateEditBox(0); + goto bypasslongpress; + } + + if((Current==T_BASE)&&(_Det==BASE)&&(ChartLogic())&&(AutoSaveSelect)){ + if(AutoSaveSelect==1){if(AutoSaveBuf<2)AutoSaveBuf++;} + if(AutoSaveSelect==2){ + if(ChartMode==0){ + ChartMode=1; + InitiateOSBuffers(); + } + } + goto BypassUpdate; + } + + if (_Mode == X_Y){ + if((Current == TRACK1)&&(_Det == POSI) && (OffsetX<215)) OffsetX=OffsetX+2; + if((Current == TRACK2)&&(_Det == POSI) && (OffsetY<170)) OffsetY=OffsetY+2; + } + SelUpdate(POSI); + + if(((Current==TRACK1)||(Current==TRACK2))&&(_Det==1))AlignTbaseSweep(1); //changing coupling mode + + if((Current==5)&&(_Det==1)&&(_Kind==8)){ //uart gen mode + if(GenUartAdj==0){ //adjust baud index, translate to baud rate + if(GenBaudAdjSpeed){ //fast mode + if(GenBaudIndex<800){ //set up break points for fast adj mode + if(GenBaudIndex>35)GenBaudIndex-=20;else GenBaudIndex=16; + }else if(GenBaudIndex<2800){ + GenBaudIndex-=50; + }else if(GenBaudIndex<12970){ + GenBaudIndex-=100; + }else if(GenBaudIndex<14970){ + GenBaudIndex-=50; + }else{ + GenBaudIndex-=20; + } + }else{if(GenBaudIndex>16)GenBaudIndex--;} + } + if(GenUartAdj==1)if(GenUartMode<6)GenUartMode++; + if(GenUartAdj==2)GenUartStopBits=1; + if(GenUartAdj==3)GenUartCont=1; + goto bypasslongpress; + } + + if((T1Start)&&(Current==T_VERNIE)&&((_Det==T1)||(_Det==T2))&&(Title[TRACK1][COUPLE].Value>2)&&(Title[TRACK1][COUPLE].Value<5)){ //in serial decode, tie T1 to T2 + if((_T10)Hbold--; + goto bypasslongpress; + } + + if((Current==BK_LIGHT)&&(FastDimAdjust)){ + if(FastDim<3)FastDim++; + goto bypasslongpress; + } + + if((Current==VOLUME)&&(AdjBeepLevel)){ + if(LoBeepLevel>0)LoBeepLevel--; + goto bypasslongpress; + } + + if((SpiLogic())&&(Current==TRACK1)&&(_Det==1)&&(SpiAdj)){ + if(SpiAdj==1){ + if(SpiMode<3)SpiMode++; + } + if(SpiAdj==2)SpiBitOrder=0; + if(SpiAdj==3){ + if(SpiNumBits==(-3))SpiNumBits=0; else { + if(SpiNumBits==0)SpiNumBits=2; else if(SpiNumBits<192)SpiNumBits++; + } + } + goto BypassUpdate; + } + + if((UartLogic())&&(Current==TRACK1)&&(_Det==1)&&(DataAdj==1)){ + if(DataSize<19){ + if(DataSize==9)DataSize=15;else DataSize++; + } + goto BypassUpdate; + } + + if((Current==OUTPUT)&&(_Det==1)&&(GenAdjustMode==1)&&((_Kind<5)||(_Kind==7))){ //changing sweep or burst rate + + if(_Kind==7){ + if(GenFreqShift>(-100))GenFreqShift--; + OutputAdjust(); + }else{ + if((Sweep==1)||(Sweep==2)){ + if(SweepIndex<9)SweepIndex++; + TIM_2IRQControl(); + AlignTbaseSweep(2); + if(Title[TRIGG][SOURCE].Value==4) Update_Trig(0); else Update_Trig(1); + }else if(Sweep==3){ + + if((SweepIndex<2)&&(_Frqn>5)){ + if(FineAdjust(-100))GenFreqShift--; + OutputAdjust(); + } + } + + goto BypassUpdate; + } + + if ((TrgAuto>0)&&(Current == TRIGG) && _Det==2) _Det=0; + if(Current < METER_0){ + + for (i=0;i<4;i++){ //tracks 1 through 4 + if ((Current==i)&&(_Det == SOURCE)){ + if (Title[TRIGG][SOURCE].Value ==i){ //if trig selected + + switch (Current){ //ch about to be shut down + case TRACK1: + case TRACK2: + //if (Title[i][SOURCE].Value == 2)UpdateTriggerMem(); + if (Title[i][SOURCE].Value == 4)UpdateTriggerMem(); + break; + case TRACK3: + if (Title[i][SOURCE].Value == 1)UpdateTriggerMem(); + break; + case TRACK4: + if (Title[i][SOURCE].Value == 9)UpdateTriggerMem(); + } + TriggFlagUpdate(); + Update_Trig(1); + + } //if title trig source... + TrigMemory(i); + } //if current=i + } //for + + if((Current == TRIGG)&&(Detail[Current]==2)){ // trigger level adjustment + + j=1;if(SetLowVolume){j=2;if(FlagFrameMode==0)j++;} + for(i=0;i>>>>> ALT X_POSI adjustment + ClearMeters(); //clears meters if untriggered in NORH + + _X_View.Flag |= UPDAT; + if (XposRef<151) { + if(SetLowVolume){ + if (XposRef<30)_Curr[_Det].Value++; + else{ + XposRef+=4; + goto bypasslongpress; + } + }else if (_Curr[_Det].Value < (_Curr[_Det].Limit))_Curr[_Det].Value++; + }else{ + if(SetLowVolume){ + if(_Curr[_Det].Value <(_Curr[_Det].Limit-30)){ + if(Key_Mid_Speed)_Curr[_Det].Value += 6; + else _Curr[_Det].Value += 30; + } + else if (_Curr[_Det].Value <(_Curr[_Det].Limit-6)) _Curr[_Det].Value +=6; + else if (_Curr[_Det].Value < (_Curr[_Det].Limit)) _Curr[_Det].Value ++; + }else if (_Curr[_Det].Value < (_Curr[_Det].Limit))_Curr[_Det].Value ++; + } + XposRef=GetXposRef(_Curr[_Det].Value); + + } else if ((Current == T_VERNIE) && ((_Det==T1) || (_Det==T2))){ + if (FlagMeter>0){ + if (_Curr[_Det].Value <(_Curr[_Det].Limit-95)) _Curr[_Det].Value ++; + if(_Curr[_Det].Value<(_Curr[_Det].Limit-97))_Curr[_Det].Value+=(CursorSpeedLogic(0)); + } + else + { + if (_Curr[_Det].Value <_Curr[_Det].Limit-(MIN_X-2)) _Curr[_Det].Value ++; + if(_Curr[_Det].Value<(_Curr[_Det].Limit-MIN_X))_Curr[_Det].Value+=(CursorSpeedLogic(0)); + } + } else if((Current==OUTPUT)&&(_Det==2)){ // PWM duty% adjust + if(PWAdjustMode){ + PWMdutyControl(0); + goto BypassUpdate; + }else{if(_Curr[_Det].Value<29399) _Curr[_Det].Value+=300; else _Curr[_Det].Value=29999;} + } else { // the current item for otheR + + if(_Curr[_Det].Value<(_Curr[_Det].Limit-2))_Curr[_Det].Value+=(CursorSpeedLogic(0)); + + if ((Current==TRACK1)&&(_Det==SOURCE)){ + + if(_1_source==0){ //ChA is about to be turned on + AlignTbaseSweep(4); + LastSelected=1; + SelectiveUpdate|=0x20; + }else if (_1_source==4)AlignTbaseSweep(5); + + } + if ((Current==TRACK2)&&(_Det==SOURCE)){ + if(_2_source==0){ //ChA is about to be turned on + AlignTbaseSweep(4); + LastSelected=2; + SelectiveUpdate|=0x40; + }else if (_2_source==4)AlignTbaseSweep(5); + } + + if((_Mode==NORHLD)&&(Current==6)&&(_Det==3)){ + if(PerstFrameNumber<252)PerstFrameNumber+=((PerstFrameNumber/65)+1); + + }else{ + + if ((Current == T_BASE)&&(_Det == BASE)){ + + if(_Curr[_Det].Value==0){ + if((_Mode==SCAN)&&(SubIndex>0))SubIndex--;else _Curr[_Det].Value++; + }else if(_Curr[_Det].Value< _Curr[_Det].Limit)_Curr[_Det].Value++; + + + }else{ + + if(_Curr[_Det].Value < _Curr[_Det].Limit){ + _Curr[_Det].Value++; + if((Current==6)&&(_Det==3))_Curr[_Det].Value+=(_Curr[_Det].Value/65); + SelUpdate(RANGE); + if ((Current<2)&&(_Det==RANGE))Update_Range(); + }else if(_Curr[_Det].MARK & CIRC)_Curr[_Det].Value = 0; + + if(((Current==0)||(Current==1))&&(_Det==0)&&(_Mode==X_Y)){ + if(Title[Current][0].Value>0)Title[Current][0].Value++; + if(Title[Current][0].Value>4)Title[Current][0].Value=0; + } + } + } + + if((Current==OUTPUT)&&(_Det==3)&&(Sweep)){ + if(FrameEndFlag)WaveGen(); + goto BypassUpdate; + } + + if((Current==OUTPUT)&&(_Det==1))PWMscaleReset(0); + + if((Current == TRIGG)&&(Detail[Current]==0)){ //trig source has just been changed + if(Title[TRIGG][SOURCE].Value==4){ //changed to AltAB + if(_Mode==X_Y){ + _Curr[_Det].Value=0; //skips over alt ab + }else{ + OldMode=Title[T_BASE][MODE].Value; //save prev mode + ChannelStatus(0); //save status + } + } + + if((Title[TRIGG][SOURCE].Value==0)&&(_Mode!=X_Y)){ //changed from AltAB + Title[T_BASE][MODE].Value=OldMode; //reset to prev mode + Title[T_BASE][MODE].Flag |= UPDAT; + ChannelStatus(1); //restore status + Title[TRACK1][RANGE].Flag |= UPDAT; Title[TRACK2][RANGE].Flag |= UPDAT; + } + Title[T_BASE][BASE].Flag |= UPDAT; + } + + if ((Current == T_BASE)&&(_Det == BASE)){ + if(Sweep){if(Title[TRIGG][SOURCE].Value==4) Update_Trig(0); else Update_Trig(1);} + if(!OSBufferLogic()){if((__Get(FIFO_START)!=0)||((_Mode!=NORH)&&(_Mode!=NORHLD)))__Set(TRIGG_MODE, UNCONDITION);} //temporarily setting this allows x_attr to properly update if in untriggered condition + } + if((FrameMode<2)&&(Current == T_BASE)&&(_Det == BASE)){ + if (XposRef>150)XposRef=GetXposRef(_X_posi.Value); + } + } + if((Current == T_BASE)&&(_Det == MODE)){ // T_BASE MODE selection //at this point, mode has been changed + if (_Mode==SCAN) {if (OldFrame>0)ShortBuffXpos=XposRef; else OldPosi=GetXpos(XposRef);} //previous mode was xy + if (_Mode==AUTO) {if (FrameMode>0)XposRef=ShortBuffXpos; else XposRef=GetXposRef(OldPosi);} //previous mode was scan + Title[RUNNING][STATE].Value = RUN; // STATE = RUNNING + Title[RUNNING][STATE].Flag |= UPDAT; // refresh RUNNING STATE + } + if((Current == OUTPUT)&&(_Kind<4)){ + if(Title[OUTPUT][FRQN].Value > 17) + Title[OUTPUT][FRQN].Value = 17; // upper limit of the analog signal frequency is 200KHz + } + + if(Current == FILE){ + if(_Curr[0].Value == 0){ //save/edit file + if((_Curr[2].Value == 5)||(_Curr[2].Value == 6)){_Curr[2].Value = 7;ResetEditList();} + } + } + + if((Current == FILE)&&(_Curr[2].Value == CFG)) if(_Curr[1].Value > 9)_Curr[1].Value=9; + if((Current==FILE)&&(_Det==2))ResetEditList(); //reset file list hilight to top when changing file types + for(i=0;i<4;i++)_Curr[i].Flag |= UPDAT; + } else { + // in meter section + Meter[Current-METER_0].Flag |= UPDAT; + + if(Meter[Current-METER_0].Item < TL) + Meter[Current-METER_0].Item += 1; + else{ + Meter[Current-METER_0].Item = VBT; + SaveCurrent[0]=Current; + SaveCurrent[1]=Meter[Current-METER_0].Track; + Meter[Current-METER_0].Track = 4; + } + + if(Meter[Current-METER_0].Item == VDC){ + if(Current==SaveCurrent[0]) + Meter[Current-METER_0].Track =SaveCurrent[1]; + else + Meter[Current-METER_0].Track = UpdateMeter; + } + + if((Meter[Current-METER_0].Track>1)&&(Meter[Current-METER_0].Track<4)){ + if(Meter[Current-METER_0].Item ==VDC)Meter[Current-METER_0].Item =FRQ; + if(Meter[Current-METER_0].Item ==MAX)Meter[Current-METER_0].Item =CIR; + } + } + } + //---------------------------------------------------------------------------------------------------------------- + if(Key_Buffer == K_ITEM_DEC){ // ===--- TASTO 6 --- PREMUTO --==== + if(Current < METER_0){ + _Curr[_Det].Flag|=UPDAT; + + if(EditListActive(0)){ //filename edit + if(CharIndex>0){ //allow right toggle to escape edit box + CharIndex--; + CharValue=EditChar[CharIndex][0]; + UpdateEditBox(3); + goto bypasslongpress; + } + } + + if((DownConvertMode)&&(DownConvertInitiate==0)&&(_4_source>11)&&(Current==3)&&(_Det==1)){ + DownConvertShiftEnable=0; + FFTdownConvert(2); + goto bypasslongpress; + } + + if((Current==FILE)&&(_Det==DIR)&&(_Mode==X_Y)&&(Title[9][0].Value==1))InitXY=1; + + if(Current==T_VERNIE){Current=V_VERNIE; goto NoDec;} //skip over file menu's regular place + + if(Current==FILE){ + if((_Det==3)&&(Title[FILE][3].Value>0)){ + Title[FILE][3].Value=0; + }else if((_Det==3)&&(DirRange>0)){ + if(DirRange>13)DirRange-=14;else DirRange=0; + }else{ + if((_Det==3)&&(ListLogic()))PrintDir(0,0,3); //clear file list when leaving + if((FlagMeter==1)||((FlagMeter==2)&&(UpdateMeter==4))){Current=VOLUME;goto NoDec;} + Current=T_VERNIE; + goto NoDec; + } + goto bypasslongpress; + } + + + if (FlagMeter>0){ + //if(Current == TRACK1) {Current = VOLUME;} //loop around + if(Current == TRACK1) {Current = TRACK1;} //don't loop around + else {Current --;} + } + else + { + //if(Current == TRACK1) {Current = T_VERNIE;} //loop around + if(Current == TRACK1) {Current = TRACK1;} //don't loop around + else {Current --;} + if ((Current == V_VERNIE)&&(_Det == 2)) _Det=0; //if meters off + if ((Current == T_VERNIE)&&(_Det == 2)) _Det=0; //if meters off + } + if (Current<4)Title[Current][3].Flag|= UPDAT; + if(Current == RUNNING) Current --; // Jump over Item 4 +NoDec: + CurDetailUpdate(); + if (Current==FILE){ + if((_Curr[2].Value == CFG)&&(_Curr[1].Value > 9))_Curr[1].Value=9; + for(i=0;i<4;i++)_Curr[i].Flag |= UPDAT; + } + + } else if (FlagMeter==1){ //IN METER SECTION + Meter[Current-METER_0].Flag |= UPDAT; + if(Current == METER_0) Current = METER_8; else Current --; + Meter[Current-METER_0].Flag |= BLINK; + } else if (FlagMeter==2){ + if (UpdateMeter!=4){if(Current==METER_1)Current=METER_3; else Current--;} + else{ + if(Current==METER_0){ + Meter[Current-METER_0].Flag &= (!UPDAT & !BLINK); + Current=METER_3; + }else if(Current==METER_2){ + Meter[Current-METER_0].Flag |= UPDAT; + Meter[Current-METER_0].Flag |= BLINK; + Current=METER_0; + }else Current--; + } + }else Current=T_VERNIE; + + } + //--------------------------------------------------------------------------------------------------------------------- + if(Key_Buffer == K_ITEM_S){ // ===--- TASTO 6 centrale PREMUTO --==== + + DisableCursorTimer=1; + Delay_Cnt = 1500; + while (Delay_Cnt > 1000){ + if((__Get(KEY_STATUS)& K_ITEM_S_STATUS)!=0){ + + if((Current==3)&&(_Det==1)&&(_4_source>11)&&(DownConvertMode==0)){ + if(FFTt1Mode)FFTt1Mode=0;else FFTt1Mode=1; + goto bypasslongpress; + } + + if(EditListActive(0)){ //reset hilighted char to space + EditChar[CharIndex][0]=32; + CharValue=32; + goto bypasslongpress; + } + + if((Current==FILE)&&(_Curr[2].Value==BUF)&&(_Curr[0].Value==LOAD)&&(_State.Value>0)){ + if (_Det==3){ + if(Title[9][3].Value>0){ + Title[9][3].Value--; + for(i=0;i<8;i++){if(SelectedFileName[i]!=Label[Title[9][3].Value][i])break;} + if(i>6){ + if(Title[9][3].Value>0)Title[9][3].Value--; + else if(DirRange>0)DirRange--; + } + }else if(DirRange>0){ + DirRange--; + } + ReadDir((char*)Ext); + for(i=0;i<8;i++)SelectedFileName[i]=Label[Title[9][3].Value][i]; + i=Load_Buf(_Curr[1].Value); + FileMessage(i); + if(Title[9][3].Value<14)Title[9][3].Value++;else DirRange++; + }else{ + if(_Curr[1].Value>1)_Curr[1].Value-=2;else _Curr[1].Value=0; + i=Load_Buf(_Curr[1].Value++); + Title[9][1].Flag|=UPDAT; + } + if(ChartLogic())ClearLeadingEdge=0; + goto bypasslongpress; + } + + if(Current==BK_LIGHT){ + FastDimAdjust=0; + if(HboldAdjust==0)HboldAdjust=1;else HboldAdjust=0; + goto bypasslongpress; + } + + if((Current==5)&&(_Det==1)&&(_Kind==8)){ //uart gen mode + if(GenUartAdj<3)GenUartAdj++;else GenUartAdj=0; + goto bypasslongpress; + } + + if((Current==OUTPUT)&&(_Det==1)&&(GenAdjustMode==1)&&(_Kind<5)){ + if(Sweep==0){ //shift from continuous to sweep mode, sweep rate adjust + PrevShift=GenFreqShift; + Sweep=1; + if(_Kind==4)Update_Output(); + } + else if(Sweep==1){ //shift from sweep mode to burst mode, burst rate adjust + GenFreqShift=PrevShift; + Sweep=2; + } + else if(Sweep==2)Sweep=3; //in burst mode, shift from burst rate to burst length adjust + else if(Sweep==3)Sweep=4; //in burst mode, shift from burst length to freq adjust + else if(Sweep==4){PrevShift=GenFreqShift; Sweep=0;} //shift from burst mode, freq adjust to continuous mode + TIM_2IRQControl(); + for(i=0;i<4;++i)Title[OUTPUT][i].Flag |= UPDAT; + if(Title[TRIGG][SOURCE].Value==4) Update_Trig(0); else Update_Trig(1); + if((Sweep==2)&&(_Kind==4))Update_Output(); + goto bypasslongpress; + } + + if((SpiLogic())&&((Current==TRACK1)||(Current==TRACK2))&&(_Det==1)&&(SpiAdj>0)){ + if(SpiAdj<3)SpiAdj++;else SpiAdj=1; + goto bypasslongpress; + } + + if((_4_source==11)&&(Current==TRACK4)) { + if(SpecMode<2)SpecMode++;else SpecMode=0; + Title[TRACK4][1].Value=SpecMode; + }else{ + if(Current != FILE){ + if(_Mode==X_Y)goto bypasslongpress; //don't change buffer size this way in xy mode + + if (FlagFrameMode==0){ //entering change from full buffer mode to single window + FlagFrameMode=1; + SelectiveUpdate |=0x60; + if (_Mode!=SCAN) { + //OldPosi=GetXpos(XposRef); + //XposRef=ShortBuffXpos; + + if(XposRef>150){ + OldPosi=GetXpos(XposRef); + }else{ + OldPosi=XposRef; + } + XposRef=ShortBuffXpos; + Update=2; + } + }else if(OSBuffer==0){ + OSBuffer=1; + OSAvg=1; + FPGAosFlag=0; + Update_Base(); + if(OSBufferLogic())InitiateOSBuffers(); + }else if(OSAvg==1){ + OSAvg=0; + FPGAosFlag=0; + }else if((OSBuffer==1)&&(OSAvg==0)&&(FPGAsubVer)&&(FPGAosFlag==0)){ + FPGAosFlag=1; + Update_Base(); + }else{ //entering change from short buffers to full buffer mode + if(_State.Value>0)DigChLockout=1; //when paused, don't display dig chs until reset, contains OS data at this point + OSBuffer=0; + OSAvg=0; + FPGAosFlag=0; + FlagFrameMode=0; + for(i=0;i<397;i++){ + TrackBuff[(i*4)+2] = _3_posi; + TrackBuff[(i*4)+3] = _4_posi; + } + SelectiveUpdate |=0x60; + + if(ChartLogic()){ // chart mode reset + ScrollFlag=2; + _X_posi.Value=0; + XposRef=GetXposRef(_X_posi.Value); + } + + Update_Base(); + if(Title[TRIGG][SOURCE].Value==4) Update_Trig(0); else Update_Trig(1); + if (_Mode!=SCAN) { + ShortBuffXpos=XposRef; + if(OldPosi>150){ + XposRef=GetXposRef(OldPosi); + }else XposRef=OldPosi; + } + if ((Current == TRIGG) && (_Det==3)) _Det=0; Title[Current][_Det].Flag |= UPDAT; + + } + AlignTbaseSweep(3); + Update_View_Area(); + +//====================================Changing buffer size while stopped in uart mode========================================== + if((Title[TRACK1][1].Value>2)&&(_Status == RUN)&&((_Mode==NORH)||(_Mode==NORHLD))&&(__Get(FIFO_START)==0)){ + RefreshDisplay=1; + } +//============================================================================================================================= + + }//if current !file + + }//else, 4source=11 + goto bypasslongpress; + } //if get key status + } //while + + Beeper(125); BackLight(1); + + while ((Delay_Cnt >0)&&(Delay_Cnt <=1000)){ // long press + if(Delay_Cnt<875)BackLight(0); + if((__Get(KEY_STATUS)& K_ITEM_S_STATUS)!=0){ + + if(EditListActive(0)){ //reset all hilighted chars to space + for(i=0;i<8;i++)EditChar[i][0]=32; + CharValue=32; + goto bypasslongpress; + } + + if((Current==FILE)&&(_Det==3)&&(_Curr[0].Value==LOAD)){ //file delete + + for(i=0;i<13;i++)DelFileName[i]=Label[Title[9][3].Value][i]; + for(i=0;i<8;i++){ + switch(DelFileName[i]){ //process unavailable chars to display dot + case 39: //' + case 64: //@ + DelFileName[i]=63; //dot + break; + default: + if(((DelFileName[i]>32)&&(DelFileName[i]<37))||(DelFileName[i]>124))DelFileName[i]=63; + } + } + Print_Str(92,0,0x0405,PRN,"WARNING DELETE "); + Print_Str(92+(8*15),0,0x0405,PRN,DelFileName); + + for(i=0;i<8;i++)DelFileName[i]=Label[Title[9][3].Value][i]; + for(i=0;i<3;i++)DelFileName[i+8]=Ext[i]; + DelFileName[11]=0; + + Key_Buffer=0; + while (1) { + if(Key_Buffer>0){ + if(Key_Buffer == K_ITEM_S){ + i=DeleteFile(SecBuff,DelFileName); + if(i==0){ + if(DirRange>0)DirRange--; + //if(ListLogic())PrintDir(0,0,3); //clear file list when changing in SPEC or MAP modes + if(ListLogic())ClearDir=1; //clear file list when changing in SPEC or MAP modes + } + FileMessage(i); + break; + }else{ + FileMessage(200); + break; + } + } + } + Delayms(200); + Update_View_Area(); + for(i=0;i<3;i++)Title[FILE][i].Flag|=UPDAT; + goto bypasslongpress; + } + + + if((Current==OUTPUT)&&(_Det==1)&&(GenAdjustMode==1)){ + if(Sweep==3){ //in burst mode, shift from burst length to burst rate adjust + Sweep=2; + goto bypasslongpress; + }else if(Sweep==4){ + Sweep=3; + goto bypasslongpress; + } + } + + _Curr[_Det].Flag |= UPDAT; + if (FlagMeter==0){ + if (((Current <= METER_8)&& (Current >= METER_0)) || (Current==BK_LIGHT) || (Current==VOLUME) ){ + Current=TRACK1 ; + } + + if(Current != FILE){ + if (Timeout==0){ + Timeout=1; + MessageHandler(3); //standby timer on + }else{ + Timeout=0; + MessageHandler(4); //standby timer off + } + } + + } else { //with meters on + if(Current < METER_0) { //shift over to meters + if(((ListLogic())||(_Mode==X_Y))&&(EditListActive(1))){ + PrintDir(0,0,3); //clear file list when leaving + if(_Mode==X_Y)InitXY=1; + } + OldCurrent=Current; + if(UpdateMeter==4)Current = METER_0;else Current=METER_1; + } else { //over to main menus, track1 + if(FlagMeter==1){ + MeterUpdate(0,9); + }else if(FlagMeter==2){ + MeterUpdate(0,4); + } + Current = OldCurrent; + if(Current==FILE)for(i=0;i<3;i++)Title[FILE][i].Flag|=UPDAT; + } + } + goto bypasslongpress; + + }//get key + }//delay count + + Beeper(60); + if(Delay_Cnt == 0){ //extra long press + + if ((Options&4)==0){ + Options|=4; //set bit 2 + MeterUpdate(1,9); + if(Current != FILE){ + MessageHandler(9); + } + Print_Str(145,216,0x0405,PRN,"H"); + SelectiveUpdate |=0x60; + }else{ + Options&=0xFB; //clear bit 2 + MeterUpdate(1,9); + if(Current != FILE){ + MessageHandler(10); + } + Print_Str(145,216,0x0405,PRN," "); + } + } + } + + //--------------------------------------------------------------------------------------------------------------- + if(Key_Buffer == K_ITEM_INC){ // ===--- TASTO 6 +++ PREMUTO --==== + if(Current < METER_0){ + _Curr[_Det].Flag |= UPDAT; + + if(EditListActive(0)){ //filename edit + if(CharIndex<7)CharIndex++; + CharValue=EditChar[CharIndex][0]; + UpdateEditBox(1); + goto bypasslongpress; + } + + if((DownConvertMode)&&(DownConvertInitiate==0)&&(_4_source>11)&&(Current==3)&&(_Det==1)){ + DownConvertShiftEnable=0; + FFTdownConvert(1); + goto bypasslongpress; + } + + if(Current==FILE){ + if(_Det==3){ //scroll list down one page (limit to 14 to see last entry + + i=ReadDir((char*)Ext);if(i>0)i--; + if(Title[FILE][3].Value 9))_Curr[1].Value=9; + for(i=0;i<4;i++)_Curr[i].Flag |= UPDAT; + } + }else if (FlagMeter==1){ //IN METER SECTION + Meter[Current-METER_0].Flag |= UPDAT; + if(Current == METER_8) Current=METER_0; else Current ++; + Meter[Current-METER_0].Flag |= BLINK; + }else if (FlagMeter==2){ + if(UpdateMeter!=4){if(Current==METER_3)Current=METER_1;else Current++;} //skip over meter 0 (bat volt), not displayed w/3 big meters + else{ + if(Current == METER_0){ + Meter[Current-METER_0].Flag &= (!UPDAT & !BLINK); + Current=METER_2; + }else if(Current==METER_3){ + Current=METER_0; + Meter[Current-METER_0].Flag |= UPDAT; + Meter[Current-METER_0].Flag |= BLINK; + }else Current++; + } + } + + } + //---------------------------------------------------------------------------------------------------------------- + + +bypasslongpress: + if((Key_Buffer!=K_INDEX_DEC)&&(Key_Buffer!=K_INDEX_INC)){OffsetSelect=0;OS_RateSelect=0;} //reset on all buttons except adjusts +bypassOSselect: + + if(_4_source!=SPEC_A)SpecRow=25; + MeterDefaults(); + if((_1_source==0)&&(_2_source==0)&&(_3_source==0)&&(_4_source>9)){ //if FFT alone, set to proper ch + if(_4_source>13)Title[TRIGG][SOURCE].Value=0; + if((_4_source==13)||(_4_source==12))Title[TRIGG][SOURCE].Value=1; + TriggFlagUpdate(); + Update_Trig(1); + }else if (Title[TRIGG][SOURCE].Value==4){ //if trig source is a&b + Title[T_BASE][MODE].Value=NORH; //set normal trig mode + Title[T_BASE][MODE].Flag |= UPDAT; + if(Title[TRACK1][SOURCE].Value==0)Title[TRACK1][SOURCE].Value=1; //turn both analog channels on if selecting a&b trig mode + if(Title[TRACK2][SOURCE].Value==0)Title[TRACK2][SOURCE].Value=1; + Title[TRACK3][SOURCE].Value=HIDE; //shut down dig chs + Title[TRACK4][SOURCE].Value=HIDE; + for(i=0;i<4;i++)Title[i][SOURCE].Flag |= UPDAT; + Title[TRACK1][RANGE].Flag |= UPDAT; Title[TRACK2][RANGE].Flag |= UPDAT; + TriggFlagUpdate(); + } + + if((Current==OUTPUT)&&(_Det==3)){ + WaveGen(); + SelectiveUpdate|=0x08; + } + + if (Update!=2){ + //full updates + if((Current == T_BASE)&&(_Det == MODE)&&((Key_Buffer==K_INDEX_DEC)||(Key_Buffer==K_INDEX_INC)))goto BypassExclusions; + //note inclusions are 2 negates, eg: if current is not tbase, set bit to not update base + //update base inclusions + if (!((Current == T_BASE)&&(_Det == BASE)&&((Key_Buffer==K_INDEX_DEC)||(Key_Buffer==K_INDEX_INC))))SelectiveUpdate|=0x04; + //update trigger inclusions + if (!((((Current == TRIGG)&&((Title[TRIGG][SOURCE].Value<4)||(_Det<2)))||(Current<4)||((Current==T_VERNIE) + &&(Title[TRIGG][SOURCE].Value<4)))&&((Key_Buffer==K_INDEX_DEC)||(Key_Buffer==K_INDEX_INC)||(Key_Buffer==K_INDEX_S)))) + SelectiveUpdate|=0x10; + //update range inclusions + if (!((Current<4)&&(_Det<3)&&((Key_Buffer==K_INDEX_DEC)||(Key_Buffer==K_INDEX_INC))))SelectiveUpdate|=0x02; + + //shift Y positioning +BypassExclusions: + + if((Current<4)&&(_Det==3)&&((Key_Buffer==K_INDEX_DEC)||(Key_Buffer==K_INDEX_INC))){ + SetOffset(0,_A_Range,_1_posi); + SetOffset(1,_B_Range,_2_posi); + if((_Mode!=X_Y)&&(_4_source!=SPEC_A)&&(_4_source!=SPEC_B)&&(ListOverride)){ + ConfNameTimer=110; + ToggleName=1; + Update_Mark(); + } + } + + if((Current == T_BASE)&&(_Det == 2)&&((Key_Buffer==K_INDEX_DEC)||(Key_Buffer==K_INDEX_INC))){ + if((_Status == RUN)&&((((_Mode==NORH)||(_Mode==NORHLD))&&(__Get(FIFO_START)==0))||(_T_base <8))){ //trying to shift X position with device not triggered in run mode or at very slow speeds + _X_posi.Value=GetXpos(XposRef); //align interpolated time bases with the others + _State.Value=1; //shift to hold mode so data is not transfered + Process(); //update screen so x pos can be changed + _State.Value=0; //return to run mode + } + + if((ChartLogic())&&(FrameMode==0)){ + if((JumpCnt>(379+_X_posi.Value)))ScrollFlag=0;else ScrollFlag=2; + } + } + //NORMH mode: if changing timebase reset meters, + if ((Current==T_BASE)&&((_Mode==NORH)||(_Mode==NORHLD))&&(_Det == BASE)&&((Key_Buffer==K_INDEX_DEC)||(Key_Buffer==K_INDEX_INC))){ + EnablePaS=1; //enable resetsum to reset TH, TL, duty% + ResetSum(); + } + + if(_Mode==NORHLD){ + ClearTrackBuff(1); + UpdateBackground=1; + if((FrameMode==0)&&(_T_base<11)){ + __Set(FIFO_CLR, W_PTR); + JumpCnt=0; + } + } + + if((_State.Value==0)&&(TempPar[0]==0xAA55)){ + reset_parameter(); + XposRef=GetXposRef(_X_posi.Value); + Update_Base(); + if(!ChartLogic()){ + //ChartFlag=0; + Update_Trig(2); + } + Update_Range(); + } + Update = 1; + }//if update !=2 + //always include output exclusions + if (!((Current == OUTPUT)&&((Key_Buffer==K_INDEX_DEC)||(Key_Buffer==K_INDEX_INC)))) + {if(!((_Kind==8)&&(StartUart)))SelectiveUpdate|=0x08;} + else if(_Det==1)AlignTbaseSweep(2); //if changing frequencies, if in sweep/detector mode +BypassUpdate: + + if((Current==OUTPUT)&&(_Det==0)&&((Key_Buffer==K_INDEX_DEC)||(Key_Buffer==K_INDEX_INC)))Update_Output(); + + if((OSBufferLogic()!=OSStatus)){ + if(OSBufferLogic()){ + if((Current!=FILE)&&(_Curr[2].Value!=BUF))InitiateOSBuffers(); + PrevKind=0xFF; + } + Update_Base(); + if(Title[TRIGG][SOURCE].Value==4) Update_Trig(0); else Update_Trig(1); + } + + OSStatus=OSBufferLogic(); + if(_1_source>0)ChOnStatus[0]=_1_source; + if(_2_source>0)ChOnStatus[1]=_2_source; + Key_Buffer=0; + OsBufferLogicFlag=OSBufferLogic(); + + } + } + +} + +void MeterDefaults(void){ + + if ((UpdateMeter==4)&&(FlagMeter>0)){ + + Meter[0].Flag |= UPDAT; + Meter[0].Item = VBT; + Meter[0].Track = 4; + if(FlagMeter==1){ + MeterUpdate(1,9); + }else if(FlagMeter==2){ + MeterUpdate(1,4); + } + + if ((_Mode==X_Y) || ( (Title[TRACK3][SOURCE].Value == HIDE) && (Title[TRACK4][SOURCE].Value == HIDE))) + { + if(FlagMeter==1){ + Meter[1].Item = RMS; Meter[1].Track = 0; + Meter[2].Item = VDC; Meter[2].Track = 0; + Meter[3].Item = VPP; Meter[3].Track = 0; + Meter[4].Item = FRQ; Meter[4].Track = 0; + Meter[5].Item = RMS; Meter[5].Track = 1; + Meter[6].Item = VDC; Meter[6].Track = 1; + Meter[7].Item = VPP; Meter[7].Track = 1; + Meter[8].Item = FRQ; Meter[8].Track = 1; + }else{ + Meter[2].Item = VDC; Meter[2].Track = 0; + Meter[3].Item = VDC; Meter[3].Track = 1; + } + } + else + { + if(FlagMeter==1){ + Meter[1].Item = FRQ; Meter[1].Track = 0; + Meter[2].Item = VDC; Meter[2].Track = 0; + Meter[3].Item = FRQ; Meter[3].Track = 1; + Meter[4].Item = VDC; Meter[4].Track = 1; + Meter[5].Item = FRQ; Meter[5].Track = 2; + Meter[6].Item = CIR; Meter[6].Track = 2; + Meter[7].Item = FRQ; Meter[7].Track = 3; + Meter[8].Item = CIR; Meter[8].Track = 3; + }else{ + Meter[2].Item = VDC; Meter[2].Track = 0; + Meter[3].Item = VDC; Meter[3].Track = 1; + } + } + } +} + + +void DisableMeter(void) +{ + if (((Current <= METER_8)&& (Current >= METER_0)) || (Current==BK_LIGHT) || (Current==VOLUME) ){_Curr[_Det].Flag |= UPDAT;Current=TRACK1 ;} + FlagMeter=0;// modo no meter + MAX_X=(386+MIN_X); + if ((Current == V_VERNIE)&&(_Det == 2)) _Det=0; + if ((Current == T_VERNIE)&&(_Det == 2)) _Det=0; + } + +void EnableMeter(void) +{ + u8 i; + if(UartLogic()==0){ //enabling this causes T cursors to be moved to the left of meters when they are engaged + if (Title[T_VERNIE][T1].Value>Title[T_VERNIE][T1].Limit-95) Title[T_VERNIE][T1].Value=Title[T_VERNIE][T1].Limit-95; + if (Title[T_VERNIE][T2].Value>Title[T_VERNIE][T2].Limit-95) Title[T_VERNIE][T2].Value=Title[T_VERNIE][T2].Limit-95; + } + + Clear_Meter_Area(); + if (FlagMeter==0)FlagMeter=1; + MAX_X=(300 + MIN_X); + Update=1; + MeterDefaults(); + + if (FlagMeter==1){ + MeterUpdate(1,9); + EnableTitleMeters(1); + } + + if (FlagMeter==1){ + Display_Meter(); + for(i=0; i<9; ++i)Display_Value(i); + }else{ + UpdateBigMeters(); + if(UpdateMeter==4)EnableTitleMeters(1);else EnableTitleMeters(0); + } +} + +void EnableTitleMeters(u8 Service){ + + Title[V_VERNIE][2].Flag |= UPDAT; + Title[T_VERNIE][2].Flag |= UPDAT; + Title[V_VERNIE][3].Flag |= UPDAT; + Title[T_VERNIE][3].Flag |= UPDAT; + if(Service){ + Title[BK_LIGHT][0].Flag |= UPDAT; + Title[VOLUME][0].Flag |= UPDAT; + Title[BK_LIGHT][1].Flag |= UPDAT; + Title[VOLUME][1].Flag |= UPDAT; + Meter[0].Flag |= UPDAT; + Meter[0].Item = VBT; + Meter[0].Track = 4; } +} + +void UpdateBigMeters(void){ +u8 i; + if (FlagMeter==2){ + if(UpdateMeter==4){ + for (i=2;i<4;i++){ + if(i==(Current-METER_0)){ + BTwinkState=!BTwinkState; + BTwink=BTwinkState; + }else BTwink=1; + Display_Value(i); + } + }else{ + for (i=1;i<4;i++){ + if(i==(Current-METER_0)){ + BTwinkState=!BTwinkState; + BTwink=BTwinkState; + }else BTwink=1; + Display_Value(i); + } + } + } +} + +void UpdateMeterPage(void){ +u8 CounterUpdate; + + if(FlagMeter==2){ + if(UpdateMeter==4){ + ClearScreenArea(314,399,125,180); + EnableTitleMeters(1); + }else EnableTitleMeters(0); + } + + switch (UpdateMeter){ + case 0: + case 1: + if(FlagMeter==1){ + Meter[0].Flag |= UPDAT; + Meter[0].Item = VBT; + Meter[0].Track = 4; + } + + for(CounterUpdate=1;CounterUpdate<9;++CounterUpdate){ + Meter[CounterUpdate].Flag |= UPDAT; + Meter[CounterUpdate].Item = CounterUpdate+1; + Meter[CounterUpdate].Track = UpdateMeter; + } + break; + case 2: + + for(CounterUpdate=1;CounterUpdate<9;CounterUpdate++){ + Meter[CounterUpdate].Flag |= UPDAT; + Meter[CounterUpdate].Item = C_Dmeter[CounterUpdate-1]; + if (CounterUpdate<6)Meter[CounterUpdate].Track = 2; else Meter[CounterUpdate].Track = 3; + } + + if(FlagMeter==1){ + Meter[0].Flag |= UPDAT; + Meter[0].Item = VBT; + Meter[0].Track = 4; + }else{ + EnableTitleMeters(0); + } + break; + case 3: + + for(CounterUpdate=1;CounterUpdate<9;CounterUpdate++){ + Meter[CounterUpdate].Flag |= UPDAT; + Meter[CounterUpdate].Item = C_Dmeter[CounterUpdate-1]; + if (CounterUpdate<6)Meter[CounterUpdate].Track = 3; else Meter[CounterUpdate].Track = 2; + } + if(FlagMeter==1){ + Meter[0].Flag |= UPDAT; + Meter[0].Item = VBT; + Meter[0].Track = 4; + }else{ + EnableTitleMeters(0); + } + break; + case 4: + MeterDefaults(); + } // switch +} + +void Config_init(void){ + DownConvertMode=0; + if (FlagMeter>0)MAX_X=300+MIN_X; + else { + MAX_X=386+MIN_X; + if(Current>=METER_0)Current=T_VERNIE; + } + OldTrack1X=Title[TRACK1][POSI].Value; + OldTrack2X=Title[TRACK2][POSI].Value; + OldMeter=FlagMeter; + _Vt1Old=_Vt1; + _Vt2Old=_Vt2; + ClearTrackBuff(1); + SelectiveUpdate |=0x60; + Options|=2; //set bit 1, shuts off edge filter (shows sharp edges) + TrgAutoOld=TrgAuto; + if (FlagFrameMode>0){ + XposRef=SaveShortBuffXpos; + if(!ChartLogic())OldPosi=_X_posi.Value; + }else{ + XposRef=GetXposRef(_X_posi.Value); + ShortBuffXpos=SaveShortBuffXpos; + } + + InvertA=0;InvertB=0; + if((!UartLogic())&&(!i2cLogic())&&(!SpiLogic())&&(_Mode!=X_Y)){ + if((Title[0][SOURCE].Value==2)||(Title[0][SOURCE].Value==4))InvertA=1; + if((Title[1][SOURCE].Value==2)||(Title[1][SOURCE].Value==4))InvertB=1; + } + + Title[7][3].XPOS=GetHoldoffIndPos(); + __Set(TRIGG_MODE, UNCONDITION); //allows arrays to update if in untriggered condition + + if(OSBufferLogic()){ + InitiateOSBuffers(); + if((FPGAsubVer)&&(FPGAosFlag))_X_posi.Value=GetXpos(XposRef); + } + + PrevKind=0xFF; + VDiff[0]=(HiBatLevel[0]-LoBatLevel[0]); + VDiff[1]=(HiBatLevel[1]-LoBatLevel[1]); + BatLevelCompensation(); + AutoFFT=Title[TRACK4][2].Value; + if(AutoFFT>1)FFTGain=AutoFFT-2;else{if(AutoFFT==0)FFTGain=8;} + SpecMode=Title[TRACK4][1].Value; + //PerstFrameNumber=0; //allow saved frame# + Raw=0; //overwrite saved Raw so always off by default + ShowFFT=1; + OsBufferLogicFlag=OSBufferLogic(); + Process(); + Update_View_Area(); // in case file menu display was showing + PrevSweepIndex=-1; + PWAdjustMode=0; // prevents conflict when initializing + StartUart=0; + UartFileSize=0; + Update_Output(); + if((DataSize<5)||(DataSize>19))DataSize=8; + Ch1TLevel=_Vt1; //use UpdateTLevels here instead? Compensates for Ka1 and Ka2 + Ch2TLevel=_Vt2; + ChannelStatus(0); //save status + if(ChartLogic())InitChart(); + +} + +u16 GetHoldoffIndPos(void){ + return (((((Title[7][3].Value)*100)/3480)*207)/100)+91; +} + +u8 ConfigFile(u8 service){ +u8 i; + if(service==0){ //save config + + PWAdjustMode=0; + if (FrameMode==2){ + SaveShortBuffXpos=XposRef; + _X_posi.Value=OldPosi; + } else SaveShortBuffXpos=ShortBuffXpos; + + Current=SaveCurrent[0]; //return to menu item selected before saving config + _Det=SaveCurrent[1]; + i=Save_Param(Title[FILE][1].Value); + _Curr[_Det].Flag |= UPDAT; + + Title[FILE][0].Value=LOAD; //preset file menu to load config files + if(i==0)ConfigFileNumber=Title[FILE][1].Value; //file number + Title[FILE][2].Value=CFG; + + }else{ //load config + + ConfigFileNumber=_Curr[1].Value; + i = Load_Param(_Curr[1].Value); + TIM_2IRQControl(); + PrevSweepIndex=-1; + PWAdjustMode=0; // prevents conflict when initializing + ResetFlag=2; + StartUart=0; + UartFileSize=0; + InitiateUartGen=0; + Update_Output(); + + if(i == 0){ + __Set(TRIGG_MODE, UNCONDITION); //temporarily setting this allows x_attr to properly update if in untriggered condition + App_init(1); + Config_init(); + Title[FILE][0].Value=LOAD; //preset file menu to load config files + Title[FILE][1].Value=ConfigFileNumber; //file number + Title[FILE][2].Value=CFG; + Update_View_Area(); //in case new loaded config has current=file + Update=2; //to update delayed trigger loop under no trigger condition & bypass selective update + } + } + return i; + +} + +void EnableChannel(u8 track){ + + + if(Title[track][SOURCE].Value == HIDE) { + AlignTbaseSweep(4); + Title[track][SOURCE].Value = 1; + LastSelected=track+1; + Title[track][SOURCE].Flag|= UPDAT; + } + if(OSBufferLogic())Update_Trig(2); + +} + +void UpdateTriggerMem(void){ + u8 j; + Title[TRIGG][SOURCE].Value = PreviousTrigSelect[3]; + for (j=3;j>0;j--) PreviousTrigSelect[j]=PreviousTrigSelect[(j-1)]; + PreviousTrigSelect[0]=0; + +} + +void SelUpdate(u8 detail){ + if((Current<2)&&(_Det==detail))SelectiveUpdate|=(0x20+(Current*0x20)); +} + +void TriggFlagUpdate(void){ +u8 i; + for(i=0;i<3;i++)Title[TRIGG][i].Flag=UPDAT; +} + +void MessageHandler(u8 number){ + MessageNumber=number; + NotificationTimer=80; //x 20Ms +} + +void CurDetailUpdate(void){ + _Curr[_Det].Flag |= BLINK; + _Curr[_Det].Flag |= UPDAT; +} + +void ChannelStatus(u8 service){ +u8 i; + for(i=0;i<4;i++){ + if(service){ //restore channel status + Title[i][SOURCE].Value=ChStatus[i]; + Title[i][SOURCE].Flag |= UPDAT; + }else ChStatus[i]=Title[i][SOURCE].Value; //save channel status + } +} + + +void MeterUpdate(u8 start, u8 limit){ +u8 i; + for(i=start;i0;k--) PreviousTrigSelect[k]=PreviousTrigSelect[k-1]; + } +} + + +void BackLight(s8 shift){ +u8 tmp=Title[BK_LIGHT][CLASS].Value+1; + if(tmp>3)shift*=2; + if(tmp>8)shift=-shift; + __Set(BACKLIGHT, 10*(tmp+shift)); +} + +void PWMdutyControl(u8 Dir){ + if(Dir==1){if(TIM4->CCR1ARR)TIM4->CCR1++;else TIM4->CCR1=TIM4->ARR;} //decrease pulse length + if(Dir==0){if(TIM4->CCR1>1)TIM4->CCR1--;else TIM4->CCR1=1;} //increase pulse length + UpdatePWMDuty(1); +} + +void PWMscaleReset(u8 Dir){ +s32 Tmp; + + if((Sweep!=1)&&(PWAdjustMode==1)){ + if((_Frqn>10)||((_Frqn>9)&&(Dir==1))){ + if (TIM4->CCR1<(TIM4->ARR/2)){ //preserve negative pulses (duty%>50) + if(TIM4->CCR1>=(D_Tab[_Frqn].ARR/2)-1)TIM4->CCR1=(D_Tab[_Frqn].ARR/2)-1; + }else{ //positive pulses (duty%<50) + Tmp=TIM4->ARR-TIM4->CCR1; + Tmp=D_Tab[_Frqn].ARR-Tmp; + if(Tmp<(D_Tab[_Frqn].ARR/2))Tmp=(D_Tab[_Frqn].ARR)/2; + TIM4->CCR1=Tmp; + } + }else{ + + if (TIM4->CCR1<(TIM4->ARR/2)){ //negative pulses + if(Dir==0){ //shifting freq range up + Tmp= ( (TIM4->CCR1 * (D_Tab[_Frqn-1].PSC+1) ) / (D_Tab[_Frqn].PSC+1) ) ; + if(Tmp<(D_Tab[_Frqn].ARR/2)-1)TIM4->CCR1=Tmp;else TIM4->CCR1=(D_Tab[_Frqn].ARR/2)-1; + } + if(Dir==1){ //shifting freq range down + Tmp= ( (TIM4->CCR1 * (D_Tab[_Frqn+1].PSC+1) ) / (D_Tab[_Frqn].PSC+1) ) ; + if(Tmp>0)TIM4->CCR1=Tmp;else TIM4->CCR1=1; + } + }else{ //positive pulses + if(Dir==0){ + Tmp= ( ( ( (TIM4->ARR-TIM4->CCR1) * (D_Tab[_Frqn-1].PSC+1) * 10) / (D_Tab[_Frqn].PSC+1))+5 )/10 ; + if( Tmp<(D_Tab[_Frqn].ARR/2) )TIM4->CCR1= (D_Tab[_Frqn].ARR-(Tmp+1)); else TIM4->CCR1=(D_Tab[_Frqn].ARR/2); + } + if(Dir==1){ + Tmp= ( (TIM4->ARR-TIM4->CCR1) * (D_Tab[_Frqn+1].PSC+1) / (D_Tab[_Frqn].PSC+1)) ; + TIM4->CCR1= (D_Tab[_Frqn].ARR-Tmp) ; + } + } + + } + UpdatePWMDuty(0); + } +} + +void SetIRQ2Priority(void){ +u8 pre=0,sub=0; + + if(Sweep==1){ //SWEEP MODE + if(((_Kind==0)||(_Kind==2))&&(SweepIndex>7)&&(_Frqn==13)){pre=0;sub=1;} //20Khz sine, saw + else if(_Kind==1){pre=1;sub=1;} //triangle waves + } + if(Sweep>1){ //BURST MODE + if((_Kind==3)&&(_Frqn==15)){pre=1;sub=1;} //100Khz square waves + } + + + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); + NVIC_InitStructure.NVIC_IRQChannel=TIM2_IRQChannel; //TIM2 IRQ priority setup for sweep/burst generator + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = pre; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = sub; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +void BurstAdjust(u8 Dir){ + + if(Dir==1){ + if(SweepStep==1){ + if(BurstLimit<200)BurstLimit++; + }else{ + BurstLimit&=0xFE; + if(BurstLimit<200)BurstLimit+=2; + } + }else{ + if(SweepStep==1){ + if(BurstLimit>0)BurstLimit--; + }else{ + BurstLimit&=0xFE; + if(BurstLimit>0)BurstLimit-=2; + } + } +} + +void InitChart(void){ + if(ChartLogic()&&ChartMode)OsChartFlag=1;else OsChartFlag=0; + + __Set(FIFO_CLR, W_PTR); //clear any pending FPGA flags for good measure + + JumpCnt=0; //reset buffer scan + __Set(T_BASE_PSC, 100-1); //slow down write pointer so read ptr can catch up + __Set(T_BASE_ARR, 24000-1); + Process(); //move read pointer up to write ptr position + + __Set(TRIGG_MODE,3); //set up chart mode + __Set(V_THRESHOLD,255); + cleardatabuf(3); //clear buffers + ClearTrackBuff(2); + if(OsChartFlag)InitiateOSBuffers(); + ScrollFlag=2; + _X_posi.Value=0; //reset to start + XposRef=GetXposRef(_X_posi.Value); + JumpCnt=0; + + __Set(T_BASE_PSC, TbaseSub[SubIndex-1].Psc); //restore timebase + __Set(T_BASE_ARR, TbaseSub[SubIndex-1].Arr); + +} + +void ProcessEditName(void){ +u8 i; + + for(i=0;i<8;i++){ + + if(((LastAccessedConfig[i]>64)&&(LastAccessedConfig[i]<91))|| + ((LastAccessedConfig[i]>47)&&(LastAccessedConfig[i]<58)))EditChar[i][0]=LastAccessedConfig[i]; + else switch(LastAccessedConfig[i]){ + case 32: + case 95: + case 45: + case 41: + case 40: + case 38: + case 37: + EditChar[i][0]=LastAccessedConfig[i]; + break; + default: EditChar[i][0]=63; //63(dot)= flag to use original char in LastAccessedConfig + } + } +} + +void ResetEditList(void){ +u8 i; + Title[FILE][DIR].Value=0; + DirRange=0; + CharIndex=0; + for(i=0;i<15;i++)Label[i][0]=0; + if((ListOverride)&&(_Curr[2].Value==CFG)){ + for(i=0;i<8;i++)SelectedFileName[i]=0; + ProcessEditName(); + }else{ + for(i=0;i<8;i++){EditChar[i][0]=32;SelectedFileName[i]=0;} + } + + CharValue=32; +} + +u8 LeftToggleSpecialFunctions(void){ +u8 i; + + if((Current==3)&&(_4_source>11)&&(_Det==1)){ + if(ChartLogic())return 1; + if(DownConvertMode==0){ + FPGAosFlag=0; + OSBuffer=0; + OSAvg=0; + Update_Base(); + DownConvertMode=1; + DownConvertShiftEnable=0; + DCbase=_T_base; + DCmode=Title[6][0].Value; + DCframe=FlagFrameMode; + if(FastMode){ + FlagFrameMode=0; + UpdateFrameMode(); + Update_View_Area(); + } + DCmeter=FlagMeter; + DCt1=_T1; + DisableMeter(); + for(i=0;i<3;i++){Title[i][0].Value=0;Title[i][0].Flag |= UPDAT;} + Title[6][0].Value=2; //set mode to NORM + Title[6][0].Flag |= UPDAT; + if(DownConvert==0)DownConvert=1; + DownConvertInitiate=1; + }else{DownConvertMode=0; DownConvertRestore();} + return 1; + } + + if((FPGAver>0)&&(Current==T_BASE)&&(_Det==MODE)&&(_Mode==AUTO)){ + if(AutoTrigSelect)AutoTrigSelect=0;else AutoTrigSelect=1; + return 1; + } + + if((ChartLogic())&&(Current==T_BASE)&&(_Det==1)){ + if(AutoSaveSelect<2)AutoSaveSelect++;else AutoSaveSelect=0; + return 1; + } + + if(Current==BK_LIGHT){ + HboldAdjust=0; + if(FastDimAdjust==0)FastDimAdjust=1;else FastDimAdjust=0; + return 1; + } + + if(Current==VOLUME){ + if(AdjBeepLevel==0)AdjBeepLevel=1;else AdjBeepLevel=0; + return 1; + } + + if((Current==5)&&(_Det==1)&&(_Kind==8)){ //uart gen mode + if(GenBaudAdjSpeed==0)GenBaudAdjSpeed=1;else GenBaudAdjSpeed=0; + return 1; + } + + if((SpiLogic())&&(Current==TRACK1)&&(_Det==1)){ + if(SpiAdj==0)SpiAdj=1;else SpiAdj=0; + return 1; + } + + if((SpiLogic())&&(Current==TRACK2)&&(_Det==1)){ + if(SpiChartFlag==0)SpiChartFlag=1;else SpiChartFlag=0; + return 1; + } + + + if((UartLogic())&&(Current==T_VERNIE)){ + if(T1Start==0)T1Start=1;else T1Start=0; + return 1; + } + + if((UartLogic())&&(Current==TRACK1)&&(_Det==1)){ + if(DataAdj==0)DataAdj=1;else DataAdj=0; + return 1; + } + + if((Current==OUTPUT)&&(_Det==1)&&((_Kind<5)||(_Kind==7))){ + if(GenAdjustMode==1)GenAdjustMode=0;else GenAdjustMode=1; + return 1; + } + + if((Current==OUTPUT)&&(_Det==2)){ + if(PWAdjustMode==1)PWAdjustMode=0;else PWAdjustMode=1; + return 1; + } + + if((Current==T_VERNIE)&&(_Det==2)){ + if(DisableCursorDisplay&1){ + DisableCursorDisplay&=0xFE; + MessageHandler(14); + }else{ + DisableCursorDisplay|=1; + MessageHandler(15); + } + return 1; + } + + if((Current==V_VERNIE)&&(_Det==2)){ + if(DisableCursorDisplay&2){ + DisableCursorDisplay&=0xFD; + MessageHandler(14); + }else{ + DisableCursorDisplay|=2; + MessageHandler(15); + } + return 1; + } + + if(_Mode==X_Y){ + if(XYper)XYper=0;else XYper=1; + return 1; + } + if((_Mode==NORHLD)&&(Current==6)&&(_Det==0)){ + if(Raw)Raw=0;else Raw=1; + MessageHandler(12+Raw); + return 1; + } + return 0; +} + +u8 CursorSpeedLogic(u8 enable){ +u8 i=0; + if((SetLowVolume)&&((enable)||((((Current==T_VERNIE)||(Current==V_VERNIE)) //SetLowVolume is fast repeat key flag + &&(_Det<2))||((Current<4)&&(_Det==3))))){ + i=1; + if(FlagFrameMode==0)i++; + } + return i; +} + +void (UpdateFrameMode)(void){ +u16 Tmp; + + if (FlagFrameMode==1){ //short buffer mode + + if (_Mode==SCAN){ + if(_T_base>9) _X_posi.Value=150; else _X_posi.Value=0; + FrameMode=1; + }else{ + if(OsBufferLogicFlag){ //note this is only active in non interpolated ranges, so KP is not a factor + if(_X_posi.Value>150)_X_posi.Value=150; //limit xpos shift to left of screen in oversampling mode + if(_T_base<16) Tmp=(1208-(_X_posi.Value*8))+(StartOffset*8); + else Tmp=(908-(_X_posi.Value*6))+(StartOffset*6); + __Set_Param(8,(Tmp&0xFF)); //stabilize window position and shift trigger point to match xpos rather + __Set_Param(9,((Tmp>>8)&0xFF)); //than shifting window to keep buffer size at 512 (X8= 4096) + }else{ + if ((_Mode!=SGL)||(OsBufferLogicFlag)){ + Tmp= 150-(((1024 - X_Attr[Title[T_BASE][BASE].Value].KP)*150 + 512)/1024); + if (_X_posi.Value>Tmp) { + _X_posi.Value=Tmp; //allow xpos to shift to left of screen in short buffer mode, add this to buffer size + XposRef=GetXposRef(Tmp); + Update=1; + } + ShortBuffXpos=XposRef; + } + } + FrameMode=2; + } + + } + else //if in long buffer mode + { // shift trigger "splice" to left of screen + + if((SubIndex==0)||(_Mode!=SCAN)||(_T_base>0)){ + + if ((_Mode==SCAN)&&(_T_base>9)){ + if (XposFlag==0){ //if flag set and in fast scan modes do nothing after going once in block and setting xpos to 150 + _X_posi.Value=150; + Update=1; + XposFlag=1; + } + }else if (XposFlag==1){ //with flag set and all modes but scan with faster time bases + if (_Mode==SCAN)_X_posi.Value=0; //don't reset xpos if not in scan mode + XposFlag=0; + Update = 1; + }else if (_Mode==SCAN){ //if flag not set, after going into above and setting flag + if (_X_posi.Value>0){ //will drop in here as long as in scan mode with slower time base + _X_posi.Value=0; //make sure xpos is at zero and update if it's not after setting it to 0 + Update = 1; + } + } + + } + FrameMode=0; + } + + +} + +/********************************* END OF FILE ******************************/ diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..1219cb8 --- /dev/null +++ b/Makefile @@ -0,0 +1,61 @@ +#Mods to get this to work with V2.51 original code: +#add -mthumb to AFLAGS + +CROSS=arm-none-eabi- +CC=$(CROSS)gcc +OBJCOPY=$(CROSS)objcopy +LD=$(CROSS)ld +AS=$(CROSS)as +STRIP=$(CROSS)strip + +STM_LIB=FWLib/inc + +#ORIGINAL >>>> CFLAGS = -Wall -Os -I. -Iinc -Werror -mcpu=cortex-m3 -mthumb -msoft-float -MD -I $(STM_LIB) +#NEED AT LEAST >>>> CFLAGS = -Os -Iinc -mcpu=cortex-m3 -mthumb -fno-common -fzero-initialized-in-bss -I $(STM_LIB) + +#CFLAGS = -Wall -Os -I. -Iinc -Werror -mcpu=cortex-m3 -mthumb -fno-common -fzero-initialized-in-bss -msoft-float -MD -I $(STM_LIB) +CFLAGS = -Wall -O2 -I. -Iinc -Werror -mcpu=cortex-m3 -mthumb -fno-common -fzero-initialized-in-bss -msoft-float -MD -I $(STM_LIB) + +#-os = optimise for size +#-o2 = optimise for speed +#-I = directories for header files +#-Wall = turns on error warnings +#-Werror = makes all warnings into errors + +#AFLAGS = -mcpu=cortex-m3 +AFLAGS = -mcpu=cortex-m3 -mthumb +#LDFLAGS = -mcpu=cortex-m3 -lc -lnosys -mthumb -march=armv7 -mfix-cortex-m3-ldrd -msoft-float -lstm32 -nostartfiles + +LDFLAGS = -mcpu=cortex-m3 -lc -mthumb -march=armv7 -mfix-cortex-m3-ldrd -msoft-float -nostartfiles -Wl,-Map,$*.map + +# tried LDFLAGS = -mcpu=cortex-m3 -mthumb -march=armv7 -mfix-cortex-m3-ldrd -msoft-float + + +OBJS = Calibrat.o Draw.o Files.o Function.o Interrupt.o Main.o Menu.o Process.o BIOS.o startup.o stm32f10x_nvic.o +OBJS +=cortexm3_macro.o +#TARGETS = app1.hex app2.hex app3.hex +#TARGETS = app1.hex app2.hex +TARGETS = app1.hex + + +all: $(OBJS) $(TARGETS) + +.PHONY: clean + +clean: + rm -rf $(OBJS) $(TARGETS) + +.c.o: + $(CC) $(CFLAGS) -c -o $@ $*.c + +.S.o: + $(CC) $(AFLAGS) -c -o $@ $*.S + +%.elf: %.lds $(OBJS) + $(CC) -o $@ $(OBJS) $(LDFLAGS) -T $< + +%.bin: %.elf + $(OBJCOPY) -O binary $< $@ + +%.hex: %.elf + $(OBJCOPY) -O ihex $< $@ diff --git a/Menu.c b/Menu.c new file mode 100644 index 0000000..068d6f8 --- /dev/null +++ b/Menu.c @@ -0,0 +1,2476 @@ +/********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ******************** + File Name : Menu.c + Version : DS203_APP Ver 2.5x Author : bure +*******************************************************************************/ +#include +#include "Interrupt.h" +#include "Function.h" +#include "Process.h" +#include "Menu.h" +#include "Draw.h" +#include "BIOS.h" +#include "Calibrat.h" +#include "File.h" + +u16 Result_FPS; +u8 Cnt_InCharge; +u8 Cnt_Charged; +u8 Cnt_Batt; +u8 FlagInCharge; +u16 NSamples; +u8 MinTresh=1; //adjust this as the least significant amount to be displayed in V meters +u8 BTwink=0; +u8 ConfigFileNumber=0; +s16 Ga_Max; +s16 Gb_Max; +s16 Ga_Min; +s16 Gb_Min; +s16 GHa_Max; +s16 GHb_Max; +s16 GHa_Min; +s16 GHb_Min; +s8 ShiftDigits; +u8 AutoFFT; +s8 GenFreqShift=0; +u8 GenAdjustMode=0; +u16 CurrentARR=0; +uc8 TIM2Speed[10]= {1,2,1,2,4,10,10,20,50,100}; +u8 SweepMod=1; +u8 SweepStep=1; +u8 SweepIndex=2; +u8 Sweep=0; +s8 PrevShift=0; +u8 Det=0; +u8 GenTrigColorFlag; +u8 EnablePWM=1; +u8 PWAdjustMode=0; +u32 LastFreqReadout=0; +u8 EnableMeterCalc; +u8 T1Start=0; +u8 GenBaudAdjSpeed=0; //button 5 short press +u32 GenBaudRate=9600; // left toggle Adj=0 +u8 GenUartMode=3; //word size/parity left toggle Adj=1 +u8 GenUartCont=0; //1=continuous re-transmit left toggle Adj=2 +u8 GenUartAdj=0; //adj item button 6 short press +u16 GenBaudIndex=7500; //control for baud rate, default= 9600 Baud (72E6/7500) +u8 GenUartStopBits=0; //0=1 stop bit, 1=2 +u8 FastDimAdjust=0; +u8 FastDim=0; +u8 AutoSaveBuf=0; +u8 AutoSaveSelect=0; +u8 AutoTrigSelect=0; +u8 HboldAdjust=0; +u8 DETflag=0; +u8 ListOverride=0; +char EditChar[8][2]={{32,0},{32,0},{32,0},{32,0},{32,0},{32,0},{32,0},{32,0}}; +u8 CharIndex=0; +char CharValue=0x20; +u8 AdjBeepLevel=0; +u8 MinBypass=0; +u8 AutoSetFlag=0; +u8 AutoSequence=0; +u8 OldCurDefTime=0; +u16 OldPosi=0; +u8 MeterStatus=0; +u8 OldMode; +u8 Neg=0; +u8 DownConvertMode=0; + +const char GEN_UART_MODE_STR[6][4]={"7Pe","7Po","8N ","8Pe","8Po","9N "}; + +u32 TimeScaleCorrection(u32 Tmp, u8 Polarity, u16 Kp); +void CalculateTimeMeters(u32 Tmp, u32 m, u32 n, u16 Kp); +u32 Period(u8 Ch,u32 k); +u32 ClockAdjust(u32 Value); +u8 MeterChannelLogic(u8 i,u8 channel); +void UpdatePWMDuty(u8 service); +u8 ChDetLogic(u8 ch,u8 val); +u8 DetStatusLogic(u8 logic); +void SyncSweep(u8 track); +u8 ListLogic(void); +u16 KpCompensation(void); +void ProcessCursorDisplayStr(char* TmpStr); +void AutoSet(void); + +uc16 X100TbaseScale[7]={33333,16667,6667,3333,1667,667,333}; + +const char T_UNIT[12] ={'n','S', 0 ,'u','S', 0 ,'m','S', 0 ,'S',' ', 0 }; + +const char D_UNIT[15] ={'u','S', 0 ,'u','S', 0 ,'m','S', 0 ,'S',' ', 0 ,'S',' ', 0 }; //special for delta T, will not work right with "n" as 1st ch +const char M_UNIT[15] ={'u','S', 0 ,'u','S', 0 ,'M',' ', 0 ,'M',' ', 0 ,'M',' ', 0 }; + +const char DD_UNIT[15] ={'n','S', 0 ,'u','S', 0 ,'m','S', 0 ,' ','S', 0 ,' ','S', 0 }; //for T cursor display and CSV time field +const char MM_UNIT[15] ={'u','S', 0 ,'u','S', 0 ,'m',' ', 0 ,'m', 0 , 0 ,'m', 0 , 0 }; +const char H_UNIT[15] ={'u','S', 0 ,'u','S', 0 ,'m', 0 , 0 ,'h', 0 , 0 ,'h', 0 , 0 }; + +const char V_UNIT[12] ={'m','V', 0 ,'m','V', 0 ,'V',' ', 0 ,'V',' ', 0 }; //for delta V display +const char VV_UNIT[12] ={'m','V', 0 ,'m','V', 0 ,'V', 0 , 0 ,'V', 0 , 0 }; //for V cursor and trigger level displays + + char N_UNIT[12] ={ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 }; +const char S_UNIT[12] ={'/','S','e','c', 0 ,'/','S','e','c', 0 , 0 , 0 }; +const char P_UNIT[12] ={'%',' ', 0 ,'%',' ', 0 ,'%',' ', 0 , 0 , 0 , 0 }; +const char F_UNIT[12] ={'H','z', 0 ,'K','@', 0 ,'M','@', 0 ,'G','@', 0 }; //Used at high sweep rates so display works right +const char F_UNITSUB[12]={'m','@', 0 ,'H','z', 0 ,'K','@', 0 ,'M','@', 0 }; //added to keep original FREQ display working right at low sweep rates + +const char STATESTR[3][10] = {"!RUN!", "HOLD", "HOLD"}; // Running state str +//uc16 S_Inv[3] = {(SCRN<<8)+TEXT2, (SCRN<<8)+X_POSI, (SCRN<<8)+NOTE1}; // Running state Color + uc16 S_Inv[3] = {(SCRN<<8)+TRACK4, (SCRN<<8)+X_POSI, (SCRN<<8)+NOTE1}; // Running state Color + +const char BATT_STR[5][10] = {"~``'", "~``}", "~`;}", "~;;}", "{;;}"}; // Battery Status Str +/* +uc16 B_COLOR[5] = {(NOTE1<<8)+SCRN, (SIDE <<8)+SCRN, + (TEXT2<<8)+SCRN, (TEXT2<<8)+SCRN, + (TEXT2<<8)+SCRN}; */ // Battery Status Color +uc16 B_COLOR[5] = {(NOTE1<<8)+SCRN, (SIDE <<8)+SCRN, + (TRACK4<<8)+SCRN, (TRACK4<<8)+SCRN, + (TRACK4<<8)+SCRN}; // Battery Status Color + + + char CH_A_STR[5][10] = {" !OFF! ", "!CH(A)!", "!CH A !", "x10(A)", "x10 A "}; + char CH_B_STR[5][10] = {" !OFF! ", "!CH(B)!", "!CH B !", "x10(B)", "x10 B "}; + +const char XY_CH_A_STR[5][10] = {" !OFF! ", "CH!A=!X", "CH!A=!X", "X10A=X", "X10A=X"}; +const char XY_CH_B_STR[5][10] = {" !OFF! ", "CH!B=!Y", "CH!B=!Y", "X10B=Y", "X10B=Y"}; + +const char CH_C_STR[2][10] = {" !OFF! ", "!CH(C)!"}; +const char CH_D_STR[16][10] = { " !OFF! ", "!CH(D)!", "!(A+B)!", "!(A-B)!", + "!(C&D)!", "!(C|D)!", "!REC_A!", "!REC_B!", + "!REC_C!","!REC_D!"," !MAP! "," SPEC ","hFFT_B","sFFT_B","hFFT_A","sFFT_A"}; // Track source Str + +const char NO_RANGE[1] = ""; //" -- "; +const char NO_DEF[1] = ""; //"--"; + +const char YCOUPLE[7][10] = {"DC", "AC", "DT","TL","RS","i2","SP"}; // Track Couple Str +const char YCOUPLE_B[5][10] = {"DC", "AC", "DT","i2","SP"}; // Track Couple Str +char Vertical[15][10]; // Track Range Str +const char YPOSISTR[5] = {"YPOS"}; // Track Position Str +uc16 Y_INV[5] = {(SCRN<<8)+TR_1, (SCRN<<8)+TR_2, + + (SCRN<<8)+TR_3, (SCRN<<8)+TR_4, + (SCRN<<8)+VERNIE}; // Track Color 1 +uc16 Y_COLOR[5] = {(TR_1<<8)+SCRN, (TR_2<<8)+SCRN, + (TR_3<<8)+SCRN, (TR_4<<8)+SCRN, + (VERNIE<<8)+SCRN}; // Track Color 2 + +const char MODESTR[7][10] = {"TrOFF","!AUTO!", "NORML","NorCL","PERST","SINGL"," X_Y "}; // Sync Mode Str + +char BaseStr[30][10]; // Time Base b Str +const char XPOSISTR[5] = {"XPOS"}; +uc16 XCOLOR[2] = {(SCRN<<8)+X_POSI, (X_POSI<<8)+SCRN}; // Time Base Color + +const char FO_TYPE[9][10] = {"!SINUS!", "TRIANG", "! SAW !", "SQUARE", "! PWM !","!NOISE!","! OFF !","!ARBTR!"," UART "}; // Output Kind Str "Kd= %" + +const char FO_STR[23][10] = {"! 1Hz !", "! 2Hz !", "! 5Hz !", + " 10Hz ", " 20Hz ", " 50Hz ", "!100Hz!", + "!200Hz!", "!500Hz!", " 1KHz ", " 2KHz ", + " 5KHz ", "!10KHz!", "!20KHz!", "!50KHz!", + "100KHz", "200KHz", "500KHz", " 1MHz ", + " 2MHz ", " 4MHz ", " 6MHz ", " 8MHz "}; // Output Frequency Str + +const char SubStr[13][10]= {"100mS","200mS","500mS","! 1S !","! 2S !","! 5S !"," 10S "," 15S "," 30S ","! 1M !","! 2M !","! 5M !"," 10M "}; + +//uc16 O_COLOR[2] = {(SCRN<<8)+TEXT3, (TEXT3<<8)+SCRN}; // Output Frequency Color BLUE +//uc16 O_COLOR[2] = {(SCRN<<8)+NOTE1, (NOTE1<<8)+SCRN}; // Output Frequency Color RED + u16 O_COLOR[2] = {(SCRN<<8)+NOTE1, (NOTE1<<8)+SCRN}; // Output Frequency Color RED + +const char TRIGSTR[5][10] = {"TR A ", "TR B ", "TR C ", "TR D ", " A&B "}; // Trigger source Str + +const char TR_TYPE[9][10] = {":!\\!", ":!^!", "Vt", // Trigger Type Str + "L<[", "L>[", "H<[", "H>[", "GEN" }; // Seems clearer to state, for example: "low pulse less in width + // than delta T1-T2" as "L + {(char*)CH_A_STR,(u16*)Y_INV, 5-1, CIRC, 35, 228, 1, UPDAT}, // Track source 2 + {(char*)YCOUPLE, (u16*)Y_COLOR, 7-1, CIRC, 35, 216, 0, UPDAT}, // Track Couple + {(char*)Vertical,(u16*)Y_COLOR, 9-1, 0, 51, 216, 5, UPDAT}, // Track Range + {(char*)YPOSISTR,(u16*)Y_INV, 200, FIX, 0, 0, 150, UPDAT}, // Adj. Track Position 160 + }, + {//============================ Title Track2 Group =========================== <1> + {(char*)CH_B_STR,(u16*)Y_INV+1, 5-1, CIRC, 86, 228, 1, UPDAT}, // Track source 2 + {(char*)YCOUPLE_B,(u16*)Y_COLOR+1,5-1, CIRC, 86, 216, 1, UPDAT}, // Track Couple + {(char*)Vertical,(u16*)Y_COLOR+1, 9-1, 0, 102, 216, 1, UPDAT}, // Track Range + {(char*)YPOSISTR,(u16*)Y_INV+1, 200, FIX, 0, 0, 100, UPDAT}, // Adj. Track Position + }, + {//============================ Title Track3 Group =========================== <2> + {(char*)CH_C_STR,(u16*)Y_INV+2, 2-1, CIRC, 137, 228, 1, UPDAT}, // Track source + {(char*)NO_DEF , (u16*)Y_COLOR+2, 1-1, CIRC, 137, 216, 0, HID}, // Track Couple + {(char*)NO_RANGE,(u16*)Y_COLOR+2, 1-1, 0, 153, 216, 0, HID}, // Track Range + {(char*)YPOSISTR,(u16*)Y_INV+2, 200-1, FIX, 0, 0, 60, UPDAT}, // Adj. Track Position + }, + {//============================ Title Track4 Group =========================== <3> + {(char*)CH_D_STR,(u16*)Y_INV+3, 16-1, CIRC, 188, 228, 1, UPDAT}, // Track source + {(char*)NO_DEF , (u16*)Y_COLOR+4, 1-1, FIX, 233, 0, 0, UPDAT}, // Used to store SpecMode and display FFT MAG + {(char*)NO_RANGE,(u16*)T_INV, 10-1, FIX, 217, 0, 0, UPDAT}, // FFT Gain Adjust + {(char*)YPOSISTR,(u16*)Y_INV+3, 200-1, FIX, 0, 0, 20, UPDAT}, // Adj. Track Position + }, + {//================== Running State & Battery Status Group =================== <4> + {(char*)STATESTR,(u16*)S_Inv, 3-1, 0, 0, 228, 0, UPDAT}, // Running state + {(char*)BATT_STR,(u16*)B_COLOR, 5-1, 0, 0, 216, 0, UPDAT}, // Battery status + {(char*)BATT_STR,(u16*)B_COLOR, 5-1, NOT, 0, 0, 0, HID}, + {(char*)BATT_STR,(u16*)B_COLOR, 5-1, NOT, 0, 0, 0, HID}, + }, + {//======================= Title Output Signal Group ========================= <5> + {(char*)FO_TYPE, (u16*)O_COLOR, 9-1, CIRC, 239, 228, 3, UPDAT}, // Output Wave Kind 282 228 + {(char*)FO_STR, (u16*)O_COLOR+1,23-1, 0, 239, 216, 13, UPDAT}, // Output Frequency 282 216 + {(char*)NumStr, (u16*)O_COLOR, 30000, NUM3, 212, 216, 15000, UPDAT}, // Duty value 100 + {(char*)NumStr, (u16*)O_COLOR, 100, NUM3, 196, 216, 50, UPDAT}, // Attenuazione 251,202 + }, + {//========================= Title Time Base Group =========================== <6> + {(char*)MODESTR, (u16*)XCOLOR, 7-1, CIRC, 290, 228, 0, UPDAT}, // Sync Mode 5 numero modi 239 228 + {(char*)BaseStr, (u16*)XCOLOR+1, 22-1, 0, 290, 216, 17, UPDAT}, // Time Base Range 239 216 WAS 27 + {(char*)XPOSISTR,(u16*)XCOLOR, 3703, FIX, 366, 0, 0, UPDAT}, // Adj. X position 3795 + {(char*)NO_RANGE,(u16*)T_INV, 253, FIX, 159, 0, 32, UPDAT}, // Adj. buffer size for X_Y mode View window rule 3795 + }, + {//=====================;===== Title Trigger Group ====;====================== <7> + {(char*)TRIGSTR, (u16*)Y_INV, 5-1, CIRC, 333, 228, 1, UPDAT}, // Trigger source + {(char*)TR_TYPE, (u16*)Y_INV, 9-1, CIRC, 373, 228, 0, UPDAT}, // Trigger Kine was 8-1 + {(char*)VT_STR, (u16*)Y_COLOR, 200, FIX, 333, 216, 0, UPDAT}, // Adj. Trigger threshold + {(char*)DELAY_STR,(u16*)Y_COLOR, 3400, FIX, 92, 0, 0, UPDAT}, // Trigger holdoff value + }, + {//============================ Title Y Vernie Group ========================= <8> + {(char*)VERNIE1, (u16*)V_INV, 201-1, FIX, 35, 0, 180, UPDAT}, // V1 Vernie + {(char*)VERNIE2, (u16*)V_INV, 201-1, FIX, 62, 0, 40, UPDAT}, // V2 Vernie + {(char*)DELTA_V, (u16*)Y_INV, 2-1, CIRC, 314, 197, 0, UPDAT}, // Measure Track + {(char*)NumStr, (u16*)Y_COLOR, 240, NUM3, 342, 197, 70, UPDAT}, // Delta V value + }, + {//============================= Title File Group ============================ <9> + {(char*)F_FUNC, (u16*)F_INV, 2-1, CIRC, 126, 0, 0, 0}, // File function + {(char*)NumStr, (u16*)F_INV, 256-1, NUM3, 206, 0, 0, 1}, // File number + {(char*)F_EXT, (u16*)F_INV, 8-1, CIRC, 230, 0, 0, 0}, // Ext. name + {(char*)NO_RANGE,(u16*)F_INV, 15-1, FIX, 166, 0, 0, HID}, // Dir readout position + }, + {//============================ Title X Vernie Group ========================= <10> + {(char*)VERNIE3, (u16*)T_INV, 395, FIX, 312, 0, 80, UPDAT}, // T1 Vernie 300 + {(char*)VERNIE4, (u16*)T_INV, 395, FIX, 339, 0, 280, UPDAT}, // T2 Vernie 300 + {(char*)DELTA_T, (u16*)T_INV, 2-1, CIRC, 314, 182, 0, UPDAT}, // Delta T Str + {(char*)NumStr, (u16*)T_COLOR, 400, NUM3, 342, 182, 80, UPDAT}, // Delta T value 300 + }, + {//=========================== Title BackLight Group ========================= <11> + {(char*)BL_Str, (u16*)V_INV, 1-1, FIX, 314, 167, 0, HID}, // BackLight + {(char*)NumStr, (u16*)V_COLOR, 10-1, NUM2, 342, 167, 5, HID}, // Class + {(char*)NumStr, (u16*)V_INV, 0, NOT, 0, 0, 0, HID}, + {(char*)NumStr, (u16*)V_INV, 0, NOT, 0, 0, 0, HID}, + }, + {//============================ Title Volume Group =========================== <12> + {(char*)Vol_Str, (u16*)V_INV, 1-1, FIX, 314, 152, 0, HID}, // Volume + {(char*)NumStr, (u16*)V_COLOR, 10-1, NUM2, 342, 152, 5, HID}, // Class was 11-1, causing display error + {(char*)NumStr, (u16*)V_INV, 0, NOT, 0, 0, 0, HID}, + {(char*)NumStr, (u16*)V_INV, 0, NOT, 0, 0, 0, HID}, + }, +}; + + //.str +meter Meter[9]= //.track .item .flag +{ {(char*)METER, 4, VBT, 314, 342, 137, UPDAT}, // Meter #0 + {(char*)METER, 4, FPS, 314, 342, 122, UPDAT}, // Meter #1 + {(char*)METER, TRACK4, FRQ, 314, 342, 107, UPDAT}, // Meter #2 + {(char*)METER, TRACK3, CIR, 314, 342, 92, UPDAT}, // Meter #3 + {(char*)METER, TRACK3, DUT, 314, 342, 77, UPDAT}, // Meter #4 + {(char*)METER, TRACK2, TH, 314, 342, 62, UPDAT}, // Meter #5 + {(char*)METER, TRACK2, TL, 314, 342, 47, UPDAT}, // Meter #6 + {(char*)METER, TRACK1, VPP, 314, 342, 32, UPDAT}, // Meter #7 + {(char*)METER, TRACK1, VDC, 314, 342, 17, UPDAT}, // Meter #8 +}; + +void Display_Meter(void) // refresh measurements display +{ + u16 color; + u8 i; + u8 MeterLimit=9; + + if(FlagMeter==2){ + MeterLimit=1; + if(UpdateMeter!=4)MeterLimit=0; + } + + for(i=0; i= METER_0)&&(Current <(MeterLimit+METER_0))){ + if(Blink){ //----- the name of the display required flashing measurements + i = Current - METER_0; + Blink = 0; // Clr Blink Ctrl flag + + if(((Options&4)==4)&&((Meter[i].Item==MIN)||(Meter[i].Item==MAX))) + color=Y_INV[4];else color=Y_INV[Meter[i].Track]; + + Print_Str( + Meter[i].XPOS1, Meter[i].YPOS, // flashing coordinates + color, // flashing colors (belongs channel) + Twink, // flashing + Meter[i].Str +(Meter[i].Item *5)); // flashing the project name + + } + } +} + + +void Display_Value(u8 i) +{ + s32 Tmp = 0; + s32 Tmp2= 0; + u32 UTmp=0; + u16 Kp; + u32 k, n, m; + u8 j; + + Kp=KpCompensation(); + + k = _T_Range; m = 1; n = 1; + if(k < 9) m = Power(10, (11-k)/3); //9 //11 + else n = Power(10, (k- 9)/3); //9 + k = X_Attr[(k%3)+9].SCALE; + ShiftDigits=0; + +if(DETflag)goto CalculateDETvalues; +if(FFTflag)goto CalculateFFTvalues; +if((DownConvertInitiate)||(DownConvertMode))goto CalculateDownConvertValues; + + switch (Meter[i].Item){ + case VBT://--------------- calculation and display of battery voltage --------------- + Int2Str(NumStr, __Get(V_BATTERY)*1000, V_UNIT, 3, SIGN,0); + break; + case FPS://--------------- calculates and displays the frame count --------------- + Int2Str(NumStr, Result_FPS, S_UNIT, 3, STD,0); + for(j=0;j<11;j++)NumStr[j]=NumStr[j+1]; + break; + case VPP: + if(Meter[i].Track == TRACK1){ + if(MeterChannelLogic(i,TRACK1)){ + Tmp=Ga_Max+Ka1[_A_Range]-_1_posi; + Tmp=Ka2[_A_Range]*Tmp; + if (Tmp>0)Tmp+=512; else Tmp-=512; // Flip bias down when calculating negative values + Tmp2=Ga_Min+Ka1[_A_Range]-_1_posi; // otherwise neg values end up 1 LSB short after adding +1/2 LSB (+512/1024) + Tmp2=Ka2[_A_Range]*Tmp2; + if (Tmp2>0)Tmp2+=512; else Tmp2-=512; + Tmp=(Tmp/1024)-(Tmp2/1024); + if(Tmp <= MinTresh) Tmp = 0; + Tmp *= Y_Attr[_A_Range].SCALE; + if(_1_source>2)Tmp=Tmp*10; + }else Tmp=0; + } + if(Meter[i].Track == TRACK2){ + if(MeterChannelLogic(i,TRACK2)){ + Tmp=Gb_Max+Kb1[_B_Range]-_2_posi; + Tmp=Kb2[_B_Range]*Tmp; + if (Tmp>0)Tmp+=512; else Tmp-=512; + Tmp2=Gb_Min+Kb1[_B_Range]-_2_posi; + Tmp2=Kb2[_B_Range]*Tmp2; + if (Tmp2>0)Tmp2+=512; else Tmp2-=512; + Tmp=(Tmp/1024)-(Tmp2/1024); + if(Tmp <= MinTresh) Tmp = 0; + Tmp *= Y_Attr[_B_Range].SCALE; + if(_2_source>2)Tmp=Tmp*10; + }else Tmp=0; + } + Int2Str(NumStr, Tmp, V_UNIT, 3, SIGN,0); + break; + case VDC: + if(Meter[i].Track == TRACK1){ + if(MeterChannelLogic(i,TRACK1)){ + Tmp=((VxAvg[0]/NSamples)+Ka1[_A_Range]-_1_posi); + Tmp=Ka2[_A_Range]*Tmp; // Add signal level correction factor based on signal zero level rather than bottom of screen, prevents offsets from corrupting value + if (Tmp>0)Tmp+=512; else Tmp-=512; + Tmp/=1024; + if((Tmp >= -MinTresh)&&(Tmp <= MinTresh)) Tmp = 0; + Tmp *= Y_Attr[_A_Range].SCALE; + if(_1_source>2)Tmp=Tmp*10; + }else Tmp=0; + } + if(Meter[i].Track == TRACK2){ + if(MeterChannelLogic(i,TRACK2)){ + Tmp=((VxAvg[1]/NSamples)+Kb1[_B_Range]-_2_posi); + Tmp=Kb2[_B_Range]*Tmp; + if (Tmp>0)Tmp+=512; else Tmp-=512; + Tmp/=1024; + if((Tmp >= -MinTresh)&&(Tmp <= MinTresh)) Tmp = 0; + Tmp *= Y_Attr[_B_Range].SCALE; + if(_2_source>2)Tmp=Tmp*10; + }else Tmp=0; + } + Int2Str(NumStr, Tmp, V_UNIT, 3, SIGN,0); + break; + case RMS: + if(Meter[i].Track == TRACK1){ + if(MeterChannelLogic(i,TRACK1)){ + Tmp = (Ka2[_A_Range]*Int_sqrt(VxSsq[0]/NSamples)+ 512)/1024; // adding Ka1 here causes error in calc, already factored in in Process... + if(Tmp <= MinTresh) Tmp = 0; + Tmp *= Y_Attr[_A_Range].SCALE; + if(_1_source>2)Tmp=Tmp*10; + }else Tmp=0; + } + if(Meter[i].Track == TRACK2){ + if(MeterChannelLogic(i,TRACK2)){ + Tmp = (Kb2[_B_Range]*Int_sqrt(VxSsq[1]/NSamples)+ 512)/1024; + if(Tmp <= MinTresh) Tmp = 0; + Tmp *= Y_Attr[_B_Range].SCALE; + if(_2_source>2)Tmp=Tmp*10; + }else Tmp=0; + } + Int2Str(NumStr, Tmp, V_UNIT, 3, SIGN,0); //unsign + break; + case MAX: + if(Meter[i].Track == TRACK1){ + if(MeterChannelLogic(i,TRACK1)){ + Tmp=GHa_Max+Ka1[_A_Range]-_1_posi; + Tmp=Ka2[_A_Range]*Tmp; + if (Tmp>0)Tmp+=512; else Tmp-=512; + Tmp/=1024; + if((Tmp >= -MinTresh)&&(Tmp <= MinTresh)) Tmp = 0; + Tmp *= Y_Attr[_A_Range].SCALE; + if(_1_source>2)Tmp=Tmp*10; + }else Tmp=0; + } + if(Meter[i].Track == TRACK2){ + if(MeterChannelLogic(i,TRACK2)){ + Tmp=GHb_Max+Kb1[_B_Range]-_2_posi; + Tmp=Kb2[_B_Range]*Tmp; + if (Tmp>0)Tmp+=512; else Tmp-=512; + Tmp/=1024; + if((Tmp >= -MinTresh)&&(Tmp <= MinTresh)) Tmp = 0; + Tmp *= Y_Attr[_B_Range].SCALE; + if(_2_source>2)Tmp=Tmp*10; + }else Tmp=0; + } + + Int2Str(NumStr, Tmp, V_UNIT, 3, SIGN,0); + break; + case MIN: + if(Meter[i].Track == TRACK1){ + if(MeterChannelLogic(i,TRACK1)){ + Tmp=GHa_Min+Ka1[_A_Range]-_1_posi; + Tmp=Ka2[_A_Range]*Tmp; + if (Tmp>0)Tmp+=512; else Tmp-=512; + Tmp/=1024; + if((Tmp >= -MinTresh)&&(Tmp <= MinTresh)) Tmp = 0; + Tmp *= Y_Attr[_A_Range].SCALE; + if(_1_source>2)Tmp=Tmp*10; + }else Tmp=0; + } + if(Meter[i].Track == TRACK2){ + if(MeterChannelLogic(i,TRACK2)){ + Tmp=GHb_Min+Kb1[_B_Range]-_2_posi; + Tmp=Kb2[_B_Range]*Tmp; + if (Tmp>0)Tmp+=512; else Tmp-=512; + Tmp/=1024; + if((Tmp >= -MinTresh)&&(Tmp <= MinTresh)) Tmp = 0; + Tmp *= Y_Attr[_B_Range].SCALE; + if(_2_source>2)Tmp=Tmp*10; + }else Tmp=0; + } + Int2Str(NumStr, Tmp, V_UNIT, 3, SIGN,0); + break; + + case FRQ: + for(j=0;j<4;j++)if(MeterChannelLogic(i,j))UTmp=Sum[j]; + +CalculateDownConvertValues: + if(DownConvertMode){ + if(_4_source>13)UTmp=Sum[0]; + else if((_4_source==12)||(_4_source==13))UTmp=Sum[1]; + } + +CalculateDETvalues: + if(DETflag){ + if(Title[TRIGG][SOURCE].Value==0)UTmp=Sum[0]; + else if(Title[TRIGG][SOURCE].Value==1)UTmp=Sum[1]; + else {LastFreqReadout=0;return;} + } + UTmp=UpScale(UTmp,1); + +CalculateFFTvalues: + if(FFTflag)UTmp=500000000; + UTmp=ClockAdjust(UTmp); + + if((DownConvertMode)&&(FFTflag==0)&&(DownConvertInitiate==0)){ + LfreqPeriod=UTmp; + FFTdownConvert(3); + return; + } + + if(n < 10){ + + UTmp=(1000*((UTmp+(k/2))/k))/m; + + if((DownConvertInitiate==1)&&(FFTflag==0)){ + FreqIN=UTmp/1000; + FreqScaleShift=ShiftDigits; + return; + } + + if(DETflag){ + UTmp=(UTmp/100)*99; //for detector mode, -1% compensation for shifting freq in sweep mode + LastFreqReadout=UTmp/1000; + } + + if(FFTflag){ + if(ChartLogic()){ + UTmp=(((((72000000/(TbaseSub[SubIndex-1].Arr+1))*10000) /(TbaseSub[SubIndex-1].S_OS_Size))*100) + /(TbaseSub[SubIndex-1].Psc+1))/2; + ShiftDigits=3; + } + NFreq=UTmp;for(j=0;j<12;j++)N_UNIT[j]=F_UNITSUB[j]; + } else { + if(ChartLogic()){UTmp=0;ShiftDigits=0;} //don't calculate time meters when using chart + Int2Str(NumStr,UTmp, F_UNITSUB , 4, UNSIGN, ShiftDigits); + } + } + else{ + if(FFTflag){NFreq=UTmp;for(j=0;j<12;j++)N_UNIT[j]=F_UNIT[j];} + if(Kp==1024){ + UTmp=n*((UTmp+(k/2))/k); + + if(DownConvertInitiate==1){ + FreqIN=UTmp; + FreqScaleShift=ShiftDigits; + return; + } + + if(DETflag){ + UTmp=(UTmp/100)*99; //for detector mode, -1% compensation for shifting freq in sweep mode + LastFreqReadout=UTmp; + } + + if(FFTflag)NFreq=UTmp;else Int2Str(NumStr,UTmp, F_UNIT, 4, UNSIGN, ShiftDigits); + } + else{ //for interpolated ranges, adjust to prevent truncation errors in scaling to be further multiplied + UTmp=TimeScaleCorrection(UTmp,0,Kp); + if(Kp==24576){ + UTmp=((Kp*((((n/10)*((UTmp+(k/2))/k))+512)/1024))+5)/10; //Kp here X100 * n/10= /10 + }else{ + UTmp=((Kp*(((n*((UTmp+(k/2))/k))+512)/1024))+5)/10; //Kp X10 so need to /10 + } + + if(DownConvertInitiate==1){ + FreqIN=UTmp; + FreqScaleShift=ShiftDigits; + return; + } + + if(UTmp>0x7FFFFFFF){ //scale down if beyond s32 range + Tmp=(UTmp/10); + ShiftDigits--; + }else Tmp=UTmp; + + if(FFTflag)NFreq=Tmp;else Int2Str(NumStr,Tmp, F_UNIT, 4, UNSIGN, ShiftDigits); + } + } + + if(DETflag){ + j=ShiftDigits; + while(j>0){LastFreqReadout/=10;j--;} //cancel up-scaling for detector mode frequency readouts + } + +if(DETflag)return; +if(FFTflag)return; + + break; + case CIR: + for(j=0;j<4;j++)if(MeterChannelLogic(i,j))UTmp=Period(j,k); + CalculateTimeMeters(UTmp,m,n,Kp); + break; + case DUT: +if(EnablePaS){ //only update these once per second + for(j=0;j<4;j++)if(MeterChannelLogic(i,j))Tmp=((10000*PxS[j])/TxS[j])*10; + if(ChartLogic()){Tmp=0;ShiftDigits=0;} + Int2Str(NumStr, Tmp, P_UNIT, 4, UNSIGN,0); +} + break; + case TL: +if(EnablePaS){ + for(j=0;j<4;j++)if(MeterChannelLogic(i,j))UTmp=(UpScale(k*(TxS[j]-PxS[j]),1)+(TxN[j]/2))/TxN[j]; + CalculateTimeMeters(UTmp,m,n,Kp); +} + break; + case TH: +if(EnablePaS){ + for(j=0;j<4;j++)if(MeterChannelLogic(i,j))UTmp=(UpScale(k*PxS[j],1)+(TxN[j]/2))/TxN[j]; + CalculateTimeMeters(UTmp,m,n,Kp); +} + break; + + } //end switch + + if (FlagMeter==1){ + Print_Str( + Meter[i].XPOS2, Meter[i].YPOS, + Y_COLOR[Meter[i].Track], + PRN, + NumStr); // display the measured values + }else if (FlagMeter==2){ // display measured values and meter title in big meters + DisplayBigMeter(i); + } + +} + +void Display_Title(void) +{ + u16 i, j, TmpColor; //,BaseRatio; + u8 l; + u8 z; + char *p; + char Zero[2]; + Zero[1]=0; + CH_A_STR[2][5]=129; CH_A_STR[4][5]=129; + CH_B_STR[2][5]=129; CH_B_STR[4][5]=129; + +if(((Sweep)||(_Kind==5))&&(_Kind<6)){ + O_COLOR[0]=(SCRN<<8)+VERNIE; + O_COLOR[1]=(VERNIE<<8)+SCRN; +}else{ + O_COLOR[0]=(SCRN<<8)+NOTE1; + O_COLOR[1]=(NOTE1<<8)+SCRN; +} + + //if(TimedDeltaView>0)ShiftLeft=2; else ShiftLeft=0; //move it away from right edge to clear border + + if (_Mode==X_Y){ //replace menu title for chA and chB to show X_Y mode + Title[0][0].Str=(char*)XY_CH_A_STR; + Title[1][0].Str=(char*)XY_CH_B_STR; + }else{ //show regular title + Title[0][0].Str=(char*)CH_A_STR; + Title[1][0].Str=(char*)CH_B_STR; + } + + if ((Current == OUTPUT)&&((_Det==DUTYPWM) || (_Det==OUTATT))){ z=Twink; }else { z=INV;} + + if (Title[OUTPUT][KIND].Value == PWM) + { + u8ToDec3(Title[OUTPUT][DUTYPWM].Str,(Title[OUTPUT][DUTYPWM].Value+150)/300,0); + Print_Str(172, 216,(Title[OUTPUT][DUTYPWM].Color[0]), z, "Dut% "); //225,202[Title[OUTPUT][PWM].Value] + Print_Str(212, 216,O_COLOR[0],z,Title[OUTPUT][DUTYPWM].Str); + } + else + { + Print_Str(172, 216, (Title[OUTPUT][DUTYPWM].Color[0]), z, "Vo ");//230,202 + Int2Str(NumStr, (Title[OUTPUT][OUTATT].Value*28000), V_UNIT, 2, UNSIGN,0); //26000 + Print_Str(196,216,O_COLOR[0],z,NumStr); + } + + if (CalFlag==0){ + Print_Str(137,216,0x0405,PRN,"U"); + }else{ + Print_Str(137,216,0x0405,PRN,"C"); + } + + if (CurDefTime==0){ + Print_Str(153,216,0x0405,PRN," "); + }else{ + Print_Str(153,216,0x0405,PRN,"X"); + } + + if(Options&4){ + Print_Str(145,216,0x0405,PRN,"H"); + }else{ + Print_Str(145,216,0x0405,PRN," "); + } + + p=(char*)Zero; + if(ListOverride){ + *p=0x23; //box + }else{ + *p='0'+ConfigFileNumber; + } + + Print_Str(161,216,0x0405,PRN,Zero); + + if(NotificationTimer==0){ + FFTlevel(0); + DisplaySamples(); + } + + for(i = TRACK1; i <= VOLUME; ++i){ + + for(j = 0; j < 4; ++j){ + + + if(Title[i][j].Flag & UPDAT){ // need to refresh the Item + + + + Title[i][j].Flag &= ~UPDAT; // Clr Update flag + + + if((i == BATTERY)||(i == TRIGG)){ + + + if(Title[i][j].MARK & FIX){ // ---- Under fix mode + + if (!((i==TRIGG)&&(j==3)&&((NotificationTimer>0)||(Current==FILE)))){ // "T" delay + Print_Str( //notifications are displayed + Title[i][j].XPOS, Title[i][j].YPOS, + Title[i][j].Color[Title[i][0].Value], // Color variable + PRN, + Title[i][j].Str // String fixed + ); + } + + }else if((i == TRIGG)&&(j==1)){ //trig kind, to enable gen kind color shift + + if (GenTrigColorFlag)TmpColor=0x0509; + else TmpColor=Title[i][j].Color[Title[i][0].Value]; + + Print_Str( + Title[i][j].XPOS, Title[i][j].YPOS, + TmpColor, // Color variable + PRN, + Title[i][j].Str +(Title[i][j].Value * 10)// String variable + ); + + + + }else if(!(Title[i][j].MARK & NOT)){ // ---- Under other mode + Print_Str( + Title[i][j].XPOS, Title[i][j].YPOS, + Title[i][j].Color[Title[i][0].Value], // Color variable + PRN, + Title[i][j].Str +(Title[i][j].Value * 10)// String variable + ); + } + + } else { //not battery or trigg + + if(Title[i][j].MARK & FIX){ // ---- Under fix mode + + + if (!((i==9)&&(j==3))){ //DIR LIST OR EDIT BOX, SHOW REGULAR MENU HERE (default files) WHEN NOT SELECTED + Print_Str( + Title[i][j].XPOS, Title[i][j].YPOS, + Title[i][j].Color[0], // Color fixed + PRN, + Title[i][j].Str // String fixed + // battery and volume meter titles - not flashing + ); + } + + + + } else if(Title[i][j].MARK & NUM3){ // ---- Under NUM3 mode + + + if(i == V_VERNIE){ + CalculateVvernier(0); + Print_Str( + (Title[i][j].XPOS), Title[i][j].YPOS, + Title[i][j].Color[_Meas_V_Track], // Color fixed + PRN, + VNumStr // String for numerical + ); + } + + if(i == T_VERNIE){ + CalculateTvernier(0); //delta T service + Print_Str( + (Title[i][j].XPOS), Title[i][j].YPOS, //shift left when calling with no meters to clear right edge + Title[i][j].Color[0], // Color fixed + PRN, + TNumStr // String for numerical + ); + + } + + if(i==FILE){ + u8ToDec3(Title[FILE][1].Str, Title[FILE][1].Value,0); + Print_Str( + Title[FILE][1].XPOS, Title[FILE][1].YPOS, + Title[FILE][1].Color[0], // Color fixed + PRN, + Title[FILE][1].Str // String for numerical + ); + } + + } else if(Title[i][j].MARK == NUM2){ + NumStr[0]=' '; + if(i == BK_LIGHT){ // backlight percentage + if(Title[i][j].Value == 9){ + Int2Str(NumStr, 100, P_UNIT, 3, STD,0); + } else Int2Str(NumStr, 10*(Title[i][j].Value+1), P_UNIT, 2, STD,0); + } else { // volume percentage + if(Title[i][j].Value == 9){ //was 10, changed so volume ind works properly + Int2Str(NumStr, 100, P_UNIT, 3, STD,0); + } else Int2Str(NumStr, 10*(Title[i][j].Value+1), P_UNIT, 2, STD,0); + } + Print_Str( + Title[i][j].XPOS, Title[i][j].YPOS, + Title[i][j].Color[0], // Color fixed + PRN, + NumStr // String for numerical + //Battery and volume values + ); + } else if(Title[i][j].MARK != NOT){ + + if(i == V_VERNIE){ + Print_Str( + Title[i][j].XPOS, Title[i][j].YPOS, + Title[i][j].Color[_Meas_V_Track], // Color variable + PRN, + Title[i][j].Str +(Title[i][j].Value * 10) // String variable + //Delta V meter title + ); + } else if(i == T_VERNIE){ + Print_Str( + Title[i][j].XPOS, Title[i][j].YPOS, + Title[i][j].Color[0], // Color fixed + PRN, + Title[i][j].Str + (Title[i][j].Value * 4) // String variable + ); + }else{ + if (i<=1 && j==2 && Title[i][0].Value>2){ + + Print_Str( + Title[i][j].XPOS, Title[i][j].YPOS, + Title[i][j].Color[0], // Color fixed + PRN, + x10[Title[i][j].Value]// String variable + //ChA or ChB x10 value - not flasing + ); + + + }else if((i==6)&&(j==1)&&(ChartLogic())){ //for chart speed timebases + Print_Str( + Title[i][j].XPOS, Title[i][j].YPOS, + 0x0405, // Color fixed + PRN, + (char*)SubStr[SubIndex-1]); // String variable + + }else if((i==9)&&(j==0)){ //for file function display + Print_Str( + Title[i][j].XPOS, Title[i][j].YPOS, + Title[i][j].Color[0], // Color fixed + PRN, + Title[i][j].Str +(Title[i][j].Value * 11) // String variable + ); // String variable + + } else { + Print_Str( + Title[i][j].XPOS, Title[i][j].YPOS, + Title[i][j].Color[0], // Color fixed + PRN, + Title[i][j].Str +(Title[i][j].Value *10) // String variable + ); + } + + } + + } //end of else if(Title[i][j].MARK != NOT) + + }//end of else(if not battery or trigg) end of all other titles + + + + } else if((Current == i)&&(Detail[i] == j)&&(Blink)){ // current cursor position Item + + + + Blink = 0; + + if((i == BATTERY)||(i == TRIGG)){ + + if((Title[i][j].MARK & FIX)){ // ---- Under fix mode + + if (j==3) { //show delayed trigger "T" on view area<0)&&(NotificationTimer==0)) { + Print_Str(Title[i][j].XPOS, Title[i][j].YPOS, + Title[i][j].Color[Title[i][0].Value], // Color variable + Twink, + Title[i][j].Str); // String fixed + } + }else{ + Print_Str( + Title[i][j].XPOS, Title[i][j].YPOS, + Title[i][j].Color[Title[i][0].Value], // Color variable + Twink, + Title[i][j].Str // String fixed + ); + } + + }else if((i == TRIGG)&&(j==1)){ //trig kind, to enable gen kind color shift + + if (GenTrigColorFlag)TmpColor=0x0509; + else TmpColor=Title[i][j].Color[Title[i][0].Value]; + Print_Str( + Title[i][j].XPOS, Title[i][j].YPOS, + TmpColor, // Color variable + Twink, + Title[i][j].Str +(Title[i][j].Value * 10)// String variable + ); + + } else { // ---- Under other mode + Print_Str( + Title[i][j].XPOS, Title[i][j].YPOS, + Title[i][j].Color[Title[i][0].Value], // Color variable + Twink, + Title[i][j].Str +(Title[i][j].Value * 10)// String variable + ); + } + + + } else { //other than battery or trigg + + + if(Title[i][j].MARK & FIX){ // ---- Under fix mode + + if((Current==9)&&(_Det==3)&&(i==9)&&(j==3)&&(Title[FILE][0].Value==0)){ //EDIT BOX + for(l=0;l<8;l++){ + if(l==CharIndex){ + Print_Str( + Title[i][j].XPOS+(l*8), Title[i][j].YPOS, + Title[i][j].Color[0], // Color fixed + Twink, + EditChar[l] // String fixed < HILIGHTED + ); + }else{ + Print_Str( + Title[i][j].XPOS+(l*8), Title[i][j].YPOS, + Title[i][j].Color[0], // Color fixed + PRN, + EditChar[l] // String fixed < INDEXED + ); + } + + } + + }else if(!((Current==9)&&(_Det==3)&&(i==9)&&(j==3)&&(Title[FILE][0].Value==1))){ + Print_Str( + Title[i][j].XPOS, Title[i][j].YPOS, + Title[i][j].Color[0], // Color fixed + Twink, + Title[i][j].Str // String fixed + ); + } + + + }else if(Title[i][j].MARK != NUM3){ + if(i == V_VERNIE) + Print_Str( + Title[i][j].XPOS, Title[i][j].YPOS, + Title[i][j].Color[_Meas_V_Track], // Color variable + Twink, + Title[i][j].Str +(Title[i][j].Value * 10)// String variable + // Delta V meter title - flashing + );else if(i == T_VERNIE){ + Print_Str( + Title[i][j].XPOS, Title[i][j].YPOS, + Title[i][j].Color[0], // Color fixed + Twink, + Title[i][j].Str + (Title[i][j].Value * 4) // String variable + ); + }else{ + + if (i<=1 && j==2 && Title[i][0].Value>2){ + Print_Str( + Title[i][j].XPOS, Title[i][j].YPOS, + Title[i][j].Color[0], // Color fixed + Twink, + x10[Title[i][j].Value]// String variable + //ChA or ChB x10 value - flashing + ); + + + }else if((i==6)&&(j==1)&&(ChartLogic())){ //for chart speed timebases + Print_Str( + Title[i][j].XPOS, Title[i][j].YPOS, + 0x0405, // Color fixed + Twink, + (char*)SubStr[SubIndex-1]); // String variable + + + }else if((i==9)&&(j==0)){ //for file function display + Print_Str( + Title[i][j].XPOS, Title[i][j].YPOS, + Title[i][j].Color[0], // Color fixed + Twink, + Title[i][j].Str +(Title[i][j].Value * 11) // String variable + ); // String variable + + + }else + Print_Str( + Title[i][j].XPOS, Title[i][j].YPOS, + Title[i][j].Color[0], // Color fixed + Twink, + Title[i][j].Str +(Title[i][j].Value * 10)// String variable + //Upper menu titles and values - flashing + ); + } + } + if((i == FILE)&&(Title[i][j].MARK & NUM3)){ + u8ToDec3(Title[i][1].Str, Title[i][1].Value,0); + Print_Str( + Title[i][1].XPOS, Title[i][1].YPOS, + Title[i][1].Color[0], // Color fixed + Twink, + Title[i][1].Str // String for numerical + ); + + } + + + } + + } //if UPDAT (?) + } //for j + + } //for i + +} //function + +/******************************************************************************* + Load_Attr: load the hardware properties +*******************************************************************************/ +void Load_Attr(void) +{ + u16 i; + + for(i=0; i0) Cnt_InCharge--; + if (Cnt_Charged>0) Cnt_Charged--; + Cnt_Batt++; + if (Cnt_Batt>4) Cnt_Batt=1; + + if (__Get(CHARGE)==1){ + Cnt_Charged=4; + if (Cnt_InCharge==0)FlagInCharge=1; + } + else + { + Cnt_InCharge=4; + if (Cnt_Charged==0)FlagInCharge=0; + + } + + if (FlagInCharge==1){ //batteria in carica + Level = Cnt_Batt ; + } + else + { + Level =0; //3000,3500,3900,4100 (or) 3200,3600,3900,4100 (mod) 3400,3600,3800,3990 >Batt seemed to die off very fast after going from 1/2 to 1/4... + //3400,3625,3775,3975 > effort to even transition times a bit, seemed to spend most of it's time at mid bar + //if(Vb > 3000 ) Level +=1; + if(Vb > 3400 ) Level +=1; + //if(Vb > 3500 ) Level +=1; + + //if(Vb > 3600 ) Level +=1; + //if(Vb > 3800 ) Level +=1; + //if(Vb > 3990 ) Level +=1; + if(Vb > 3625 ) Level +=1; + if(Vb > 3775 ) Level +=1; + if(Vb > 3975 ) Level +=1; + + + } + if (Level>4) Level=4; + Print_Str( + Title[4][1].XPOS, Title[4][1].YPOS, + Title[4][1].Color[Level], + PRN, + (Title[4][1].Str + Level*10) + ); +} + + +void DisplayBigMeter(u8 MeterNum){ + + u16 color; + u8 j; + u8 BigMeterYpos1=0; + u8 BigMeterYpos2=0; + char BigMeterStr1[7]; //values + char BigMeterStr2[4]; //suffix + char BigMeterStr3[5]; //items + BigMeterStr1[5]=0; //termination nulls + BigMeterStr2[2]=0; + BigMeterStr3[3]=0; + char RefStr[10]=" DCmV?k!S"; //reference matching characters + + switch (MeterNum){ //meter positions + case 1: + BigMeterYpos1=154; + BigMeterYpos2=129; + break; + case 2: + BigMeterYpos1=97; + BigMeterYpos2=72; + break; //32 + case 3: + BigMeterYpos1=40; //25 + BigMeterYpos2=15; + } + + switch (Meter[MeterNum].Item){ //format string 1, values + case VBT: + case VDC...RMS: + case MAX...VPP: + if((NumStr[5]==RefStr[3])||(NumStr[5]==RefStr[4])){ //look for "m" or "V" for all volt meters + for (j=0;j<5;j++)BigMeterStr1[j]=NumStr[j]; + }else{ //if "KV" or ending of number, strip leading zero and replace with sign + BigMeterStr1[0]=NumStr[0]; //puts "-" or "+" sign before number, instead of leading "0" in 0.0 + for (j=1;j<5;j++)BigMeterStr1[j]=NumStr[j+1]; //ie: +.124 rather than 0.124 for some ranges so all of number fits + } + break; + case FPS: + BigMeterStr1[5]=0; + case FRQ: + case CIR...TL: + for (j=0;j<5;j++)BigMeterStr1[j]=NumStr[j]; + + } + + switch (Meter[MeterNum].Item){ //format string 2, suffix + case VBT: + case VDC...RMS: + case MAX...VPP: + if(NumStr[5]==RefStr[3]){ //"m", so copy 2 ("mV") + for (j=0;j<2;j++)BigMeterStr2[j]=NumStr[j+5]; + }else if((NumStr[5]==RefStr[4])||(NumStr[6]==RefStr[4])){ //"V" + BigMeterStr2[0]=RefStr[7]; //"!" + BigMeterStr2[1]=RefStr[4]; + BigMeterStr2[2]=RefStr[7]; + BigMeterStr2[3]=0; + }else{ + BigMeterStr2[0]=RefStr[6]; //"kV" character + BigMeterStr2[1]=RefStr[4]; + } + break; + case FRQ: + for (j=0;j<2;j++)BigMeterStr2[j]=NumStr[j+5]; //HZ, etc + break; + case CIR: + case TH: + case TL: + if(NumStr[5]==RefStr[8]){ //"S" + BigMeterStr2[0]=RefStr[7]; //"!" + BigMeterStr2[1]=RefStr[8]; + BigMeterStr2[2]=RefStr[7]; + BigMeterStr2[3]=0; + }else for (j=0;j<2;j++)BigMeterStr2[j]=NumStr[j+5]; //"uS" etc + break; + case DUT: + BigMeterStr2[0]=RefStr[7]; //"!" + BigMeterStr2[1]=NumStr[5]; + BigMeterStr2[2]=RefStr[7]; + BigMeterStr2[3]=0; + break; + case FPS: + for(j=0;j<2;j++)BigMeterStr2[j]=RefStr[0]; + } + + switch (Meter[MeterNum].Item){ //format string3, items + case VBT...DUT: + for (j=0;j<3;j++)BigMeterStr3[j]=METER[Meter[MeterNum].Item][j]; + break; + case TH...TL: + for (j=0;j<4;j++)BigMeterStr3[j]=METER[Meter[MeterNum].Item][j]; //"!TH!,!TL!" + BigMeterStr3[4]=0; //termination null moved to 5th place to allow for the 2 half spaces + } + + if((Meter[MeterNum].Item<9)||(EnablePaS)){ //only update TH,TL,%duty values once per second + Print_Str2( //display values //these generate much "bobbling" @3/sec due to uncompensated + 314,LCD_X2,BigMeterYpos1, //x and y positions //quantization errors from PxS starting and stopping at every wave + Y_COLOR[Meter[MeterNum].Track], //also extends averaging numbers if available (at the faster TB's) + PRN, + BigMeterStr1, + 3,3); //leading, trailing blanks + + Print_Str2( //display suffix + 313,347,BigMeterYpos2, + Y_COLOR[Meter[MeterNum].Track], + PRN, + BigMeterStr2, + 2,0); + } + + if(((Meter[MeterNum].Item==MIN)||(Meter[MeterNum].Item==MAX))&&((Options&4)==4)) + color=Y_COLOR[4]; else color=Y_COLOR[Meter[MeterNum].Track]; //display items in white for hold mode + + Print_Str2( + 346,LCD_X2,BigMeterYpos2, + color, + BTwink, + BigMeterStr3, + 12,1); //>10 leading blanks=leading line + (-10) leading blanks + + __LCD_Set_Block(LCD_X1,LCD_X2,LCD_Y1,LCD_Y2); // restore the full-size window + +} + +u32 TimeScaleCorrection(u32 Tmp, u8 Polarity, u16 Kp){ + //Compensates for truncation of "k" scaling values in interpolated ranges + //Prevents these errors to be further multiplied by IP scaling factors + //Uses modified (X10, X100) Kp IP scaling factors as reference + switch (Kp){ + case 24576: + case 8192: // 1/.1 uS/div, k returns 10ppm off + if(Polarity==0)Tmp-=(Tmp/100000); else Tmp+=(Tmp/100000); // k here equals 33333 in which error is neg as opposed to other + break; // k values + case 6144: // .5uS/div, k returns 20ppm off + if(Polarity==0)Tmp+=(Tmp/50000); else Tmp-=(Tmp/50000); + break; + case 9830: //2uS/div, k returns 50ppm off (eg: (6667-6666.6666666)/6667)*1e6 = 50) + case 4915: //.2uS/div, k returns 50ppm off, + kp returns 41ppm off = 91ppm off) + if(Polarity==0)Tmp+=(Tmp/10989); else Tmp-=(Tmp/10989); + } + return Tmp; +} + +u32 UpScale(u32 Tmp, u16 limit){ + + if(Tmp>4290){ //up scale,increases resolution with low number of waves counted when dividing with integer math + while(Tmp<429000000){ //specially in large buffer mode. Makes sure the maximum number of digits of precision can + Tmp*=10; //be considered under all conditions by making #'s as high as possible with + ShiftDigits++; //u32 variable minus some headroom for following adjustments. + } //ShiftDigits compensates for this in Int2Str + }else ShiftDigits=0; + + while(limit>1){ //scale back down if limit is called for + if(ShiftDigits>0)ShiftDigits--; else break; + Tmp/=10; + limit/=10; + } + return Tmp; +} + +void CalculateTimeMeters(u32 Tmp, u32 m, u32 n, u16 Kp){ +s32 STmp; + + if(ChartLogic()){Tmp=0;ShiftDigits=0;} //do not enable time meters while in chart mode + if(n<10){ + while((m>1)&&(ShiftDigits>0)){ //remove any up scaling in the lower ranges + m/=10; + ShiftDigits--; + } + if(Tmp <= 0x7FFFFFFF/m) Tmp*=m; + else Tmp = 0x80000000; + }else{ + Tmp=UpScale(Tmp,1); //up scale after dividing by TxN, so significant digits are not lost + if(Kp==1024){ + Tmp=((Tmp+(n/2))/n); + }else{ + Tmp=TimeScaleCorrection(Tmp,1,Kp); //add Kp IP scaled correction + Tmp=((Tmp+(n/2))/n); //sets range, with k factor selecting ranges within each decade + Tmp=UpScale(Tmp,10); //up scale after dividing by n, so significant digits are not lost, restrict by X10 to leave room for IP scaling + if(Kp==24576){ //IP scaling + Tmp=(102400*((Tmp+(Kp/2))/Kp)); //special case .1uS/div with Kp X 100 + }else Tmp=(10240*((Tmp+(Kp/2))/Kp)); //rest of IP ranges, Kp X 10 + } + } + + if(Tmp>0x7FFFFFFF){ //convert to signed var for Int2Str + STmp=(Tmp/10); + ShiftDigits--; + }else STmp=Tmp; + + if(ChartLogic()){STmp=0;ShiftDigits=0;} //don't calculate time meters when using chart + + Int2Str(NumStr, STmp, T_UNIT, 4, UNSIGN, ShiftDigits); +} + +u32 Period(u8 Ch,u32 k){ +u32 Tmp; + Tmp=UpScale(Sum[Ch],1); + Tmp=ClockAdjust(Tmp); + ShiftDigits=-ShiftDigits; //upscaled denominator so works backwards, invert shift + return(UpScale(((k*100000)/(Tmp/100000)),1)/10); //scales by e10 (100000*100000) for best resolution in all cases, +} // div/10 to bring down to original freq scaling of 1e9 + +u32 ClockAdjust(u32 Value){ + if((PPM_Comp>0)&&(PPM_Comp<1000)){ //do not use if out of range, indicating a read error + return Value+=(Value/(1000000/PPM_Comp)); + }else if((PPM_Comp<0)&&(PPM_Comp>-1000)){ + return Value-=(Value/(1000000/-PPM_Comp)); //change PPM_Comp to + so works correctly with unsigned var + }else return Value; +} + + +u8 MeterChannelLogic(u8 i,u8 channel){ + switch (channel){ + case 0: + return((Meter[i].Track == TRACK1)&&((_1_source != HIDE)||(_4_source>13))); + case 1: + return((Meter[i].Track == TRACK2)&&((_2_source != HIDE)||(_4_source==12)||(_4_source==13))); + case 2: + return((Meter[i].Track == TRACK3)&&(_3_source == CH_C)); + case 3: + return((Meter[i].Track == TRACK4)&&((_4_source == CH_D)||(_4_source == C_and_D)||(_4_source == C_or_D))); + } + return 0; + +} + +void FFTlevel(u8 service){ +char FFTorderSTR[5]; + + if((Current==TRACK4)&&(_Det==1)){ + if(DownConvertMode){ + if(FFTt1Mode){ + Print_Str(112,0,0x0405,PRN,"T1 MODE MAG= X "); + u8ToDec3(FFTorderSTR,DownConvert,1); + Print_Str(234,0,0x0405,PRN,(char*)FFTorderSTR); + }else{ + Print_Str(128,0,0x0405,PRN,"AUTO MAG= X "); + u8ToDec3(FFTorderSTR,DownConvert,1); + Print_Str(234,0,0x0405,PRN,(char*)FFTorderSTR); + } + }else{ + if(FFTt1Mode){ + Print_Str(112+(8*4),0,0x0405,Twink,"T1 MODE MAG= 0"); + }else{ + Print_Str(112+(8*5),0,0x0405,Twink, "AUTO MAG= 0"); + } + } + } + + if((Current==TRACK4)&&(_Det==2)){ + if(_4_source>10){ + AutoFFT=Title[TRACK4][2].Value; + if(AutoFFT>1)FFTGain=AutoFFT-2;else{if(AutoFFT==0)FFTGain=8;} + if(service)UpdateBackground=3; + else { + Print_Str(144,0,0x0405,PRN,"FFT Gain="); + Print_Str(216,0,0x0405,PRN,(char*)FFT_GAIN_STR[AutoFFT]); + } + }else _Det=0; + } +} + +void TIM_2IRQControl(void){ + if(((Sweep)&&(_Kind<6))||(_Kind==5)){ //sweeps or bursts/sec= (Tim2Factor*SweepStep)/SweepMod + // SweepStep = 1 1 1 1 1 1 2 2 2 2 + // TIM2Speed[] = {1,2,1,2,4,10,10,20,50,100}; //lookup table for tim2 speed divider (timer period=1000/x) + // SweepMod = 5 5 1 1 1 1 1 1 1 1 + TIM2->DIER = 0x0001; //enable TIM2_INT + if(SweepIndex>9)SweepIndex=2; //make sure we don't go out of bounds with improper config file read + Tim2Factor=TIM2Speed[SweepIndex]; //index sets timer speed + if(_Kind==5){ + TIM2->ARR=(1000/Tim2Factor)-4; //timer call, xx microseconds per IRQ call, + }else{ + TIM2->ARR=(1000/Tim2Factor)-1; //timer call, xx microseconds per IRQ call, + } + if(SweepIndex<2)SweepMod=5; else SweepMod=1; //modulus factor to slow down sweep function + if(SweepIndex>5)SweepStep=2; else SweepStep=1; //=1 step all 200, =2 step every other (100) + }else{ + TIM2->DIER = 0x0000; //disable TIM2_INT + WaveGen(); //in case stopped on space + TIM4->CCER=0x0001; //turns PWM timer back on (?) + OutputAdjust(); //reset to saved freq + } +} + +void OutputAdjust(void){ +s32 tmp; +u16 arr; +u16 PrevARR; +u16 i; + + if(_Kind==PWM)arr=D_Tab[_Frqn].ARR; + else if(_Kind==7)arr=ARBT_ARR; + else arr=A_Tab[_Frqn]; + if(arr>200) tmp=((arr*(300+GenFreqShift))+((300-GenFreqShift)/2))/(300-GenFreqShift); //WITH ROUNDING + else tmp=arr+GenFreqShift; + if(tmp>0xFFFF)tmp=0xFFFF; + + if(_Kind == PWM){ + if(tmp<9){ + if(Sweep==1){ + GenFreqShift=-100; + }else{ + tmp=8; + GenFreqShift=tmp-arr; + } + } + + PrevARR=TIM4->ARR; + __Set(DIGTAL_ARR,(u16)tmp); + + if((Sweep==1)||(PWAdjustMode==0)){ //sweep or reg PWM mode + i=(TIM4->ARR*(30000-Title[OUTPUT][DUTYPWM].Value))/30000; + if(i==0)i++; + if(i>(TIM4->ARR))i=(TIM4->ARR); //was -1 on both + TIM4->CCR1=i; + }else if(GenAdjustMode){ + if ( TIM4->CCR1<(PrevARR/2) ){ //preserve negative pulses (duty%>50) + if(TIM4->CCR1>=(tmp/2))TIM4->CCR1=(tmp/2); + }else{ //positive pulses (duty%<50) + TIM4->CCR1= tmp-(PrevARR-TIM4->CCR1); + if(TIM4->CCR1<=(tmp/2))TIM4->CCR1=(tmp/2); + } + UpdatePWMDuty(1); + } + + if((Sweep==1)&&(EnablePWM)){ + TIM4->CR1 = 0x0081; // SQR_OUT = Enable + GPIOB->CRL &= 0xF0FFFFFF; + GPIOB->CRL |= 0x0B000000; // PORT_SQR = Enable (puts PWM port(PB6) in output, push-pull) + EnablePWM=0; + } + + }else if((_Kind>4)&&(_Kind<7)){ // DAC noise or off mode + return; + }else{ + if(tmp<40){ + if((Sweep==1)&&(_Kind!=7)){ //if sweep mode, exclude arbitrary mode + GenFreqShift=-100; //end sweep + }else{ //if manual mode + tmp=39; //limit to sampling frequency of 1.8Mhz + GenFreqShift=tmp-arr; + } + } + __Set(ANALOG_ARR,tmp); + } + CurrentARR=tmp; + } + +void DisplaySamples(void){ +char TempStr[10]; +u32 UTmp=0; +u8 scale,i=0,j; +u16 offset; +char PPM_Str[5]; + + if(AutoSetFlag){ + if(AutoSetFlag==2){ + Print_Str(95+(4*8),0,0x0405,PRN, "AUTOSET: NO SIGNAL"); + }else{ + Print_Str(95+(4*8),0,0x0405,PRN, " AUTOSET "); + } + } + + if((OS_RateSelect)&&(Current==T_BASE)&&(_Det==1)&&(OSBufferLogic())&&(FPGAsubVer)&&(FPGAosFlag)){ //Tbase RANGE sub menu + Print_Str(99+(3*8),0,0x0405,PRN,(char*)OSrate[OS_Range]); + Print_Str(98+(12*8),0,0x0405,Twink,""); + } + + if((OffsetSelect==1)&&(Current>1)&&(!((Current==T_BASE)&&(_Det==1)&&(FPGAsubVer)&&(FPGAosFlag)))){ + u8ToDec2(TempStr,ADCoffset); + Print_Str(132+(8*2),0,0x0405,PRN,"ADCoffset= "); + Print_Str(131+(8*13),0,0x0405,Twink,""); + Print_Str(132+(8*13),0,0x0405,PRN,TempStr); + } + + if((OffsetSelect==2)&&(Current>1)&&(!((Current==T_BASE)&&(_Det==1)&&(FPGAsubVer)&&(FPGAosFlag)))){ + s16ToDec3(PPM_Str, PPM_Comp); + Print_Str(127,0,0x0405,PRN,"Clock PPM Adj="); + Print_Str(127+(8*14),0,0x0405,Twink,""); + Print_Str(127+(8*14),0,0x0405,PRN,PPM_Str); + } + + if((Current==T_BASE)&&(_Det==MODE)&&(_Mode==AUTO)){ + if((AutoTrigSelect)&&(FPGAver>0)){ + if(FreeRunEnable) Print_Str(95+(2*8),0,0x0405,PRN, " AUTO trig CONT WAVES "); + else Print_Str(95+(2*8),0,0x0405,PRN, "AUTO trig FAST RELEASE"); + } + } + + if((Current==T_BASE)&&(_Det==BASE)&&(ChartLogic())){ + if(AutoSaveSelect==1){ + if(AutoSaveBuf==0){ + Print_Str(95+(2*8),0,0x0405,PRN, "Chart auto save OFF "); + }else if(AutoSaveBuf==1){ + Print_Str(95+(2*8),0,0x0405,PRN, "Chart auto save BUF ON"); + }else if(AutoSaveBuf==2){ + Print_Str(95+(2*8),0,0x0405,PRN, "Chart auto save CSV ON"); + } + } + if(AutoSaveSelect==2){ + if(ChartMode==0){ + Print_Str(95+(2*8),0,0x0405,PRN, "CHART MODE= AVERAGE "); + }else if(ChartMode==1){ + Print_Str(95+(2*8),0,0x0405,PRN, "CHART MODE= OVERSAMPLE"); + } + } + } + + if((Current==VOLUME)&&(AdjBeepLevel)){ + u8ToDec2(TempStr,9-LoBeepLevel); + Print_Str(92+(5*8),0,0x0405,PRN,"Fast rep vol= "); + Print_Str(92+(19*8),0,0x0405,Twink,""); + Print_Str(93+(19*8),0,0x0405,PRN,TempStr); + } + + if(Current==BK_LIGHT){ + if(FastDimAdjust){ + u8ToDec2(TempStr,FastDim); + Print_Str(92+(5*8),0,0x0405,PRN,"Vert Dim Adj= "); + }else if (HboldAdjust){ + u8ToDec2(TempStr,3-Hbold); + Print_Str(92+(5*8),0,0x0405,PRN,"Hor Bold Adj= "); + }else goto ExitIfBlock; + Print_Str(92+(19*8),0,0x0405,Twink,""); + Print_Str(93+(19*8),0,0x0405,PRN,TempStr); + } +ExitIfBlock: + + + if((Current==5)&&(_Det==1)&&(_Kind==8)){ //uart gen mode + Print_Str(92,0,0x0405,PRN,"BAUD "); + if(GenBaudAdjSpeed)Print_Str(92+(5*8),0,0x0405,PRN,"FAST="); + else Print_Str(92+(5*8),0,0x0405,PRN,"FINE="); + u32ToDec7(TempStr,GenBaudRate); //GenBaudRate= 1200 to 4500000 + for(j=0;j<7;j++)if(TempStr[j]==48)TempStr[j]=32;else break; //strip off leading 0's + Print_Str(93+(10*8),0,0x0405,PRN,TempStr); + Print_Str(93+(17*8),0,0x0405,PRN," "); + + Print_Str(94+(18*8),0,0x0405,PRN,(char*)GEN_UART_MODE_STR[GenUartMode-1]); + Print_Str(94+(21*8),0,0x0405,PRN," "); + + if(GenUartStopBits==0)Print_Str(95+(22*8),0,0x0405,PRN,"1S"); + else Print_Str(95+(22*8),0,0x0405,PRN,"2S"); + Print_Str(95+(24*8),0,0x0405,PRN," "); + + if(GenUartCont)Print_Str(96+(25*8),0,0x0405,PRN,"C"); + else Print_Str(96+(25*8),0,0x0405,PRN,"1"); + + if(GenUartAdj==0)i=Twink;else i=PRN; //=blink on adjust positions + Print_Str(92+(10*8),0,0x0405,i,""); + if(GenUartAdj==1)i=Twink;else i=PRN; + Print_Str(93+(18*8),0,0x0405,i,""); + if(GenUartAdj==2)i=Twink;else i=PRN; + Print_Str(94+(22*8),0,0x0405,i,""); + if(GenUartAdj==3)i=Twink;else i=PRN; + Print_Str(95+(25*8),0,0x0405,i,""); + } + + if((SpiLogic())&&((Current==TRACK2)&&(_Det==1))){ + if(SpiChartFlag)Print_Str(117,0,0x0405,PRN,"SPI DECODE CHART ON"); + else Print_Str(117,0,0x0405,PRN,"SPI DECODE CHART OFF"); + } + if((SpiLogic())&&((Current==TRACK1)&&(_Det==1))){ + + Print_Str(100,0,0x0405,PRN,"Pol/Pha/Ord="); + if(SpiNumBits>0){ + i=SpiNumBits; + Print_Str(102+(8*15),0,0x0405,PRN," Bits="); + }else if(SpiNumBits<0){ + i=-SpiNumBits; + Print_Str(102+(8*15),0,0x0405,PRN," )!<"); + Print_Str(107+(8*21),0,0x0405,PRN,">!("); + }else{ + Print_Str(102+(8*15),0,0x0405,PRN," AUTO "); + } + + u8ToDec3(TempStr,i,0); + for(j=0;j<7;j++)if(TempStr[j]==48)TempStr[j]=32;else break; //strip off leading 0's + if(SpiNumBits>0){ + Print_Str(103+(8*21),0,0x0405,PRN,TempStr); //bits + }else if(SpiNumBits<0){ + Print_Str(107+(8*18),0,0x0405,PRN,TempStr); //bits + } + if(SpiMode&1)TempStr[0]=49;else TempStr[0]=48; + if(SpiMode&2)TempStr[1]=49;else TempStr[1]=48; + TempStr[2]=0; + Print_Str(101+(8*12),0,0x0405,PRN,TempStr); //mode + + if(SpiBitOrder)TempStr[0]=60;else TempStr[0]=62;TempStr[1]=0; + Print_Str(102+(8*14),0,0x0405,PRN,TempStr); //bit order + + if(SpiAdj==1)i=Twink;else i=PRN; //adjust mode + Print_Str(100+(8*12),0,0x0405,i,""); + if(SpiAdj==2)i=Twink;else i=PRN; //adjust bit order + Print_Str(101+(8*14),0,0x0405,i,""); + if(SpiAdj==3)i=Twink;else i=PRN; //adjust number of bits per word + if(SpiNumBits>0){ + Print_Str(102+(8*21),0,0x0405,i,""); + }else if(SpiNumBits<0){ + Print_Str(106+(8*18),0,0x0405,i,""); + }else{ + Print_Str(101+(8*18),0,0x0405,i,""); + } + } + + if((UartLogic())&&(((Current==TRACK1)&&(_Det==1))||(Current==T_VERNIE)||((Current==T_BASE)&&(_Det==1)))){ + + if(DataSize>9){ //datasize=5 to 9 (+10 if parity) + i=DataSize%10; + Parity=1; + }else {Parity=0;i=DataSize;} + FrameSize=i+2+Parity; + if(_T_base<15){ //<10uS/div + if(_T2>(_T1+2))UTmp=((1000000000/(_T2-_T1))*FrameSize)/X_Attr[_T_base].SCALE;else UTmp=0; + }else{ + if(_T2>(_T1+2))UTmp=(((1000000000/(_T2-_T1))*FrameSize)/X100TbaseScale[_T_base-15])*100;else UTmp=0; + } + + if(UTmp>9999999)UTmp=9999999; + u32ToDec7(TempStr,UTmp); + for(j=0;j<7;j++)if(TempStr[j]==48)TempStr[j]=32;else break; //strip off leading 0's + + if(T1Start==0){ + if(ValidFrame)Print_Str(93,0,0x0405,PRN,"T2-1="); + else Print_Str(93,0,0x0605,PRN,"T2-1="); + }else{ + if(ValidFrame)Print_Str(93,0,0x0305,PRN,"!T1+2!"); + else Print_Str(93,0,0x0F05,PRN,"!T1+2!"); + } + + Print_Str(133,0,0x0405,PRN,"BAUD="); + Print_Str(133+(8*5),0,0x0405,PRN,TempStr); + TempStr[0]=i+48;TempStr[1]=0; //convert to char, add terminating nul + Print_Str(133+(8*12),0,0x0405,PRN," DATA="); + if(((Current==TRACK1)&&(_Det==1))&&(Title[TRACK1][1].Value>2)&&(DataAdj))i=Twink;else i=PRN; + Print_Str(134+(8*18),0,0x0405,i,""); + Print_Str(135+(8*18),0,0x0405,PRN,TempStr); + + if(Parity)Print_Str(135+(8*19),0,0x0405,PRN," P"); + else Print_Str(135+(8*19),0,0x0405,PRN," N"); + } + + if((Current==6)&&(_Det==3)){ + if(_Mode==X_Y){ + u8ToDec3(TempStr,BufferSize,1); //u8ToDec3 also doubles as a u16to Dec4 with option 1 + Print_Str(160,0,0x0405,PRN,"SAMPLES="); + Print_Str(160+(8*8),0,0x0405,PRN,TempStr); + } + if(_Mode==NORHLD){ + u8ToDec3(TempStr,PerstFrameNumber,0); + Print_Str(160,0,0x0405,PRN,"FRAMES="); + if(PerstFrameNumber){ + Print_Str(160+(7*8),0,0x0405,PRN,TempStr); + }else{ + Print_Str(160+(7*8),0,0x0405,PRN,"CONT"); + } + } + } + + if((Current==5)&&(_Det==2)&&(PWAdjustMode)&&(_Kind==4)){ //pulse mode + + if (TIM4->CCR1> (TIM4->ARR/2)){ + if(_Frqn<3) UTmp=((u32)((TIM4->PSC+1)*((TIM4->ARR+1)-TIM4->CCR1)*100)/72)*10; + else UTmp=(u32)((TIM4->PSC+1)*((TIM4->ARR+1)-TIM4->CCR1)*1000)/72; + Print_Str(114,0,0x0405,PRN,"+PULSE LENGTH="); + }else{ + if(_Frqn<3)UTmp=((u32)((TIM4->PSC+1)*TIM4->CCR1*100)/72)*10; + else UTmp=(u32)((TIM4->PSC+1)*TIM4->CCR1*1000)/72; + Print_Str(114,0,0x0405,PRN,"-PULSE LENGTH="); + } + if(UTmp<1000)scale=4;else scale=0; + Int2Str(TempStr,(s32)UTmp,T_UNIT,4,UNSIGN,scale); + if(UTmp<1000){TempStr[0]=32;TempStr[1]=32;} + if((UTmp<100)&&(UTmp>0))TempStr[2]=32; + Print_Str(116+(8*14),0,0x0405,PRN,TempStr); + Print_Str(115+(8*14),0,0x0405,Twink,""); + } + + if((Current==5)&&(_Det==1)&&(GenAdjustMode)&&((_Kind<5)||(_Kind==7))){ + + if(_Kind==7)goto ArbtBypass; //do not engage sweep/burst functions with arbitrary wave mode + if(Sweep==1){ //adjust sweep period + + if(_Kind==PWM){ + if(_Frqn<18)i=10;else i=TrunkFactor[_Frqn-18]; + }else{ + if(_Frqn<9)i=10;else i=TrunkFactor[_Frqn-9]; + } + UTmp=((TIM2Speed[SweepIndex]*SweepStep*5)/SweepMod); + scale=1; + if(UTmp<200)UTmp=((100*i)/UTmp); + else {UTmp=((1000*i)/UTmp);scale=10;} + + u8ToDec3(TempStr,UTmp,1); //works as u16 to dec 4 with option 1 + for(i=0;i<4;i++)if(TempStr[i]==48)TempStr[i]=32;else break; //strip off leading 0's + if(scale==10){for(i=0;i<2;i++)TempStr[i]=TempStr[i+1];TempStr[2]=46;} + Print_Str(118,0,0x0405,PRN,"SWEEP PERIOD ="); + Print_Str(120+(8*14),0,0x0405,PRN,TempStr); + Print_Str(120+(8*18),0,0x0405,PRN,"mS"); + Print_Str(119+(8*14),0,0x0405,Twink,""); + + }else if((Sweep==2)||(Sweep==3)){ //adjust tone burst period + +//=================================DISPLAY BOTH RATE IN X/SEC AND PERIOD IN MS================================== + Print_Str(92,0,0x0405,PRN,"BURST RATE="); + Print_Str(94+(8*14),0,0x0405,PRN, "/S PER="); + + UTmp=((TIM2Speed[SweepIndex]*SweepStep*5)/SweepMod); //burst rate + if(UTmp>999)Print_Str(94+(8*11),0,0x0405,PRN,"!1K!");else{ + u8ToDec3(TempStr,UTmp,0); + for(i=0;i<3;i++)if(TempStr[i]==48)TempStr[i]=32;else break; + Print_Str(94+(8*11),0,0x0405,PRN,TempStr); + } + UTmp=1000000/UTmp; + offset=UTmp/100; //start offset + if(SweepIndex<6)offset/=2; //compensate for 50/s - 100/s breakpoint (CHECK IF OK ALL THE WAY DOWN) + if(SweepIndex<2)offset=4000; //4mS timing for cnt ms reset at 19 > 15 for mod 5=0 + UTmp=((UTmp*BurstLimit)+100)/200; + UTmp+=offset; + if(((SweepIndex<2)&&(_Frqn>5))||(_Frqn>13)) + UTmp+=((FineAdjust*3*FineAdjustFactor[_Frqn-6])/16); //fine adjust offset for high frequencies + + if(UTmp>=1000){ + i=0; + while(UTmp>=1000){UTmp/=10;i++;} //reduce to 3 decimals of precision, keep track of how much we divided + u8ToDec3(TempStr,UTmp,0); //convert to string, function modified to work with u16 as well + if(i==1){ //for 1.0mS to 9.9mS + TempStr[2]=TempStr[1]; //make space and add period + TempStr[1]=46; + } + if(i==2){ + TempStr[2]=TempStr[1]; //for 10mS to 99mS, shift right one decimal digit. + TempStr[1]=TempStr[0]; + TempStr[0]=32; + } + Print_Str(97+(8*24),0,0x0405,PRN,"mS"); //For 100mS and up (i=3) use as is + }else{ + u8ToDec3(TempStr,UTmp,0); + Print_Str(97+(8*24),0,0x0405,PRN,"uS"); + } + for(i=0;i<3;i++)if(TempStr[i]==48)TempStr[i]=32;else break; //strip off any leading zeros + Print_Str(96+(8*21),0,0x0405,PRN,TempStr); + + if(Sweep==2){ + Print_Str(181,0,0x0405,Twink,""); + Print_Str(263,0,0x0505,PRN,""); + }else{ + Print_Str(263,0,0x0405,Twink,""); + Print_Str(181,0,0x0505,PRN,""); + } +//============================================================================================================== + }else{ //sweep=4 and 0, adj freq display for burst (4) and continuous (0) +ArbtBypass: + scale=3; + if(_Kind==PWM){ + if(_Frqn>8){ + UTmp=720000000/((D_Tab[_Frqn].PSC+1)*(CurrentARR+1)); //scaled up x10 + scale=1; + }else{ + UTmp=720000000/(((D_Tab[_Frqn].PSC+1)*(CurrentARR+1))/100); //scaled up x1000 + } + }else if(_Kind==7){ + UTmp=((TIM7->PSC+1)*(CurrentARR+1)*ArbtSampleNumber); + if(UTmp>720000){ + UTmp=720000000/(UTmp/100); //scaled up x1000 + }else{ + UTmp=720000000/UTmp; //scaled up x10 + scale=1; + } + }else{ + if(_Frqn>13){ + UTmp=((10000000*ScaleIndex[_Frqn])/(CurrentARR+1))*10; + }else{ + UTmp=1000000000/(((CurrentARR+1)*10)/ScaleIndex[_Frqn]); //scaled up x1000 + } + if(_Frqn==0)UTmp/=2; //uses 36 Mhz clock + } + if(UTmp<1000)scale=0; + Int2Str(TempStr,UTmp, F_UNIT , 4, UNSIGN,scale); + + if((Sweep==4)&&(_Kind!=7)){ + Print_Str(120,0,0x0405,PRN,"BURST FREQ= "); + }else{ + Print_Str(120,0,0x0405,PRN,"FREQ OUTPUT= "); + } + Print_Str(120+(8*13),0,0x0405,PRN,TempStr); + Print_Str(119,0,0x0405,Twink,""); //puts vert blinking bar ahead of text + } + } + +} + + +void GenTrigColor(void){ +static u8 PrevGenTrigColorFlag; + + if((Sweep)&&(_Tr_kind==8)&&(_Kind<5)){ + if(Sweep==1){ + if(!((((s8)(_T_base-SweepIndex))<8)&&(((s8)(_T_base-_Frqn))<2)&&(((s8)(_Frqn-SweepIndex))>1)))GenTrigColorFlag=1; + else GenTrigColorFlag=0; + }else{ + if(!((((s8)(_T_base-SweepIndex))<6)&&(((s8)(_T_base-_Frqn))<2)&&(((s8)(_Frqn-SweepIndex))>1)))GenTrigColorFlag=1; + else GenTrigColorFlag=0; + } +/* + }else if((OSBufferLogic())&&(FPGAsubVer)&&(FPGAosFlag)&&(_Tr_kind<8)&&(_Tr_kind>3)){ //also use to grey out non valid OS time trig modes + if(_T1>_T2){ + if(((_T1-_T2)*FPGA_TbaseOS[Title[T_BASE][BASE].Value].OS_Size)>0xFFFF)GenTrigColorFlag=1;else GenTrigColorFlag=0; + }else{ + if(((_T2-_T1)*FPGA_TbaseOS[Title[T_BASE][BASE].Value].OS_Size)>0xFFFF)GenTrigColorFlag=1;else GenTrigColorFlag=0; + } +*/ + }else GenTrigColorFlag=0; + + if(GenTrigColorFlag!=PrevGenTrigColorFlag)Title[TRIGG][1].Flag=UPDAT; + PrevGenTrigColorFlag=GenTrigColorFlag; +} + +void UpdatePWMDuty(u8 service){ + if(service) Title[OUTPUT][DUTYPWM].Value=(((TIM4->ARR)-TIM4->CCR1)*30000)/(TIM4->ARR); + else Title[OUTPUT][DUTYPWM].Value=(((D_Tab[_Frqn].ARR)-TIM4->CCR1)*30000)/(D_Tab[_Frqn].ARR); + if(Title[OUTPUT][DUTYPWM].Value<1)Title[OUTPUT][DUTYPWM].Value=1; + if(Title[OUTPUT][DUTYPWM].Value>29999)Title[OUTPUT][DUTYPWM].Value=29999; +} + +void AlignTbaseSweep(u8 dir){ //call BEFORE engaging or changing coupling (0,1,4,5) and AFTER changing either sweep rate or frqn (2) +static s8 OldTbase=-1; + + if((Sweep==1)&&(_Kind<4)){ + + if(dir<2){ + if((ChDetLogic(Current,dir))&&(!DetStatusLogic(0))){OldTbase=_T_base; SyncSweep(1);} //if about to engage det mode save previous TB + else if((ChDetLogic(Current,2))&&(!DetStatusLogic(1))){ //if leaving with the only ch on with det mode //if in det mode and leaving restore previous TB + if(OldTbase>-1){ + _T_base=OldTbase; + Update_Base(); + Title[T_BASE][BASE].Flag |= UPDAT; + } + } + }else if(dir==2){ + if(DetStatusLogic(0)){ //if either ch is on in det mode + if((Current==OUTPUT)&&(_Det==1)&&(GenAdjustMode==0)) //freq range shift + SyncSweep(1); else SyncSweep(2); //non coupling shift call + OldTbase=-1; //assume changing sweep parameters means using function + } // in such case, stay in same TB when leaving + }else if(dir==3){ //for FrameMode changes + if(DetStatusLogic(0))SyncSweep(1); + }else if(dir<6){ //chs turned on with source selector + if((((Det&1)&&(Current==0))||((Det&2)&&(Current==1)))&&(!DetStatusLogic(1))){ //ch called has det on and both chs are not on + if(dir==4){ + OldTbase=_T_base; SyncSweep(1); + }else{ + if(OldTbase>-1){ + _T_base=OldTbase; + Update_Base(); + Title[T_BASE][BASE].Flag |= UPDAT; + } + } + } + } + + } //return to previous TB assuming selection was error +} + +void SyncSweep(u8 track){ + Delayms(20); + if(track==1){ + if(_Frqn<17){ //allow 16 > -5 =11 as will be reduced to 9 below + if(_Frqn>4)SweepIndex=_Frqn-5; + else SweepIndex=0; + if(_Frqn>9)SweepIndex-=2; + }else SweepIndex=9; + } + _T_base=SweepIndex+3; //use best timebase to fit sweep + if(_Frqn>9)_T_base++; //higher frequencies have shorter sweeps + if(FlagFrameMode==0){ + if(track==1){if(SweepIndex>1)SweepIndex-=2;else SweepIndex=0;} + if(track==2)_T_base+=2; + } + Update_Base(); + TIM_2IRQControl(); + Title[T_BASE][BASE].Flag |= UPDAT; + Delayms(20); +} + +u8 DetStatusLogic(u8 logic){ //test if at least 1 channel is on (0) or both (1) with detector mode + if(logic==0)return(((Title[TRACK1][COUPLE].Value==2)&&(_1_source))||((Title[TRACK2][COUPLE].Value==2)&&(_2_source))); + if(logic==1)return(((Title[TRACK1][COUPLE].Value==2)&&(_1_source))&&((Title[TRACK2][COUPLE].Value==2)&&(_2_source))); + return 0; +} + +u8 ChDetLogic(u8 ch,u8 val){ //tests if called channel is about to be changed to detector mode (0,1) or already on (2) + if(ch==0)return((Title[ch][COUPLE].Value==val)&&(_1_source)); + if(ch==1)return((Title[ch][COUPLE].Value==val)&&(_2_source)); + return 0; +} + +u8 ChartLogic(void){ + return ((_Mode==SCAN)&&(SubIndex>0)&&(_T_base==0)); +} + +u8 ListLogic(void){ + return ((_4_source==10)||(_4_source==11)); +} + +u8 EditListActive(u8 mode){ + return((Current==FILE)&&(_Det==DIR)&&(Title[9][0].Value==mode)); //mode 0=edit, 1=file list +} + +void UpdateEditBox(u8 mode){ + // left toggle right toggle > right toggle < + Print_Str( // modes 0=PRN, 1= PRN >> INV, 3= INV << PRN + Title[FILE][DIR].XPOS+(CharIndex*8), Title[FILE][DIR].YPOS, + Title[FILE][DIR].Color[0], // Color fixed + mode&1, // bit 0 sets INV for highliting < > with right toggle + EditChar[CharIndex] // String fixed < HILIGHTED CHAR + ); + + if((mode==1)&&(CharIndex>0)){ + Print_Str( + Title[FILE][DIR].XPOS+((CharIndex-1)*8), Title[FILE][DIR].YPOS, + Title[FILE][DIR].Color[0], + PRN, + EditChar[CharIndex-1] + ); + } + + if((mode==3)&&(CharIndex<7)){ + Print_Str( + Title[FILE][DIR].XPOS+((CharIndex+1)*8), Title[FILE][DIR].YPOS, + Title[FILE][DIR].Color[0], + PRN, + EditChar[CharIndex+1] + ); + } +} + +u16 KpCompensation(void){ + switch (_Kp1){ //add 1 or 2 digits of resolution to interpolation factors + case 983: + return 9830; + case 819: + return 8192; + case 614: + return 6144; + case 492: + return 4915; //actual correct value here is 49152, compensated for in TimeScaleCorrection + case 246: + return 24576; + default: + return 1024; + } +} + +void CalculateTvernier(u8 mode){ + s32 k=0, Min=0, Hr=0, n, m; + s8 shift=0,i=0; + u16 BaseRatio=TbaseSub[SubIndex-1].Ratio; + s16 LocalStartOffset=150; + u8 DminBypass=0; + u16 End=0,IpComp=0,Xposition=_X_posi.Value; + + Neg=0; + m = 1; n = 1; + k = _T_Range; //structure index to time bases + + if(mode==0){ + if(k < 9) m = Power(10, (11-k)/3); //in chart mode, all time bases are k = 0, m = 1000 + else n = Power(10, (k- 9)/3); + k = X_Attr[(k%3)+9].SCALE *(_T2 - _T1); + if(_T_Range<3)m=1; + if((_T_Range%3)==0)k+=((k+25000)/49999); + }else{ + MinBypass=0; //mode 0= delta T service, 1= Xpos + T1 + if(k < 6) shift= -((8-k)/3); //need 10x more precision for 5 digit time display, so use TB's 6-8 scale + else shift= (k-6)/3; + + if(CursorDisplaySelect&1)LocalStartOffset=0; + if(mode==2){ + if((OSBufferLogic())&&(FPGAosFlag==0))End=(_X_posi.Value-StartOffset);else End=0; + if((CursorDisplaySelect&1)==0){ + if(_T_Range>16)LocalStartOffset=150-(discard+2); + else LocalStartOffset=150-(discard+1); + } + Xposition=CSVposition; + }else{ + if(CursorDisplaySelect<2)End=_T1; + else if(CursorDisplaySelect<4)End=_T2; + } + + if(mode==1){ + switch(_Kp1){ //Kp1 interpolation truncation correction factors + case 246: + k=((((416667*Xposition)+50000)/100000)-LocalStartOffset)+End; + if(Xposition<1500){ + k*=333333; + }else{ //scale back so large IP factor doesn't overload at large xpos values + k*=33333; + k+=((k+50000)/99999); //10ppm compensation + rounding for 33333 scaling + shift=4; + } + break; + case 1024: + k=X_Attr[(k%3)+6].SCALE*((Xposition-LocalStartOffset)+End); //non IP ranges + break; + case 983: //2uS/div + case 492: //.2uS/div + IpComp=4710; //46ppm compensation for 2 IP ranges (41 IP correction + 5 truncation) + default: //rest of IP ranges + k=X_Attr[(k%3)+6].SCALE*(((((((102400000+IpComp)/KpCompensation())*Xposition)+5000)/10000)-LocalStartOffset)+End); + } + }else if(mode==2){ + + switch(_Kp1){ + case 246: //.1uS/div + if(Xposition<1100){ + k=1388888; + }else{ + k=138888; + shift=4; + } + break; + case 492: //.2uS/div + k=138888; + break; + case 614: //.5uS/div + k=277778; + break; + case 819: //1uS/div + k=416666; + break; + case 983: //2uS/div + k=69447; + break; + case 1024: + k=X_Attr[(k%3)+6].SCALE; //non IP ranges + } + k*=(Xposition-(LocalStartOffset-End)); + } + + } + + if(ChartLogic()){ + k+=((k+500000)/999999); //1ppm compensation + rounding for 333333 scaling + if(SubIndex>4){ + if(mode>0){ + if(k>(599999999/BaseRatio)){ //greater than 60 seconds + Min=k/60; //convert to minutes + k=k%(600000000/BaseRatio); + MinBypass=1; + } + if(Min>(599999999/BaseRatio)){ + Hr=Min/60; + Min=(Min%(600000000/BaseRatio)); + k=(k%(600000000/BaseRatio)); + MinBypass=2; + } + Min*=BaseRatio; + if(Min<9900000)Min=0; + Hr*=BaseRatio; + }else if(k>((119999999/BaseRatio)-33333)){ //greater than 119 seconds + k/=60; //convert to minutes + DminBypass=1; + } + k*=BaseRatio; + }else if(SubIndex<4){ + k/=BaseRatio; + } + } + + if((mode>0)&&(k<0)){k=-k;Neg=1;} + if(k>0){ + if(k <= 0x7FFFFFFF/m) k = (m * k)/n; + else k = 0x80000000; + }else k = 0x80000000; + + if(mode>0){ //Cursor time since start display + if((MinBypass)&&(k==0x80000000))k=0; + if(MinBypass==1){ + Int2Str(CursorDisplayStrM, Min, MM_UNIT, 4, UNSIGN,shift); + ProcessCursorDisplayStr(CursorDisplayStrM); + Int2Str(CursorDisplayStr, k, DD_UNIT, 5, UNSIGN,shift); + if(CursorDisplayStr[6]=='n'){CursorDisplayStr[6]=' ';CursorDisplayStr[7]='S';} + }else if(MinBypass==2){ + Int2Str(CursorDisplayStrH, Hr, H_UNIT, 4, UNSIGN,shift-3); + ProcessCursorDisplayStr(CursorDisplayStrH); + Int2Str(CursorDisplayStrM, Min, MM_UNIT, 4, UNSIGN,shift); + ProcessCursorDisplayStr(CursorDisplayStrM); + Int2Str(CursorDisplayStr, k, DD_UNIT, 5, UNSIGN,shift); + if(CursorDisplayStr[6]=='n'){CursorDisplayStr[6]=' ';CursorDisplayStr[7]='S';} + }else{ + Int2Str(CursorDisplayStr, k, DD_UNIT, 5, UNSIGN,shift); + if(k==0x80000000){ + for(i=0;i<8;i++)CursorDisplayStr[i]=' '; + if((Xposition==(LocalStartOffset-End))||(XposRef==(LocalStartOffset-End))){ + CursorDisplayStr[2]='0'; + CursorDisplayStr[5]=0; + } + }else if(Neg){ + for(i=9;i>0;i--)CursorDisplayStr[i]=CursorDisplayStr[i-1]; + CursorDisplayStr[0]='-'; + } + } + + }else{ + if(Title[T_VERNIE][2].Value==0){ //DELTA T DISPLAY + if(DminBypass){ + Int2Str(TNumStr, k, M_UNIT, 3, SIGN,0); + }else{ + Int2Str(TNumStr, k, D_UNIT, 3, SIGN,0); + if((_T_Range==3)&&(TNumStr[2]==' ')){ + TNumStr[2]='.'; + TNumStr[5]='S'; + TNumStr[6]=' '; + } + } + }else{ //FREQUENCY DISPLAY + n=0; + while(k>100000){k/=10;n++;} + k=((1000000000+(k/2))/k); + if(MinBypass)k = 0x80000000; //do not display frequency of less than 0.0083 Hz + if(_T_Range<3)Int2Str(TNumStr, k, F_UNITSUB, 4, UNSIGN,n); + else Int2Str(TNumStr, k, F_UNIT, 4, UNSIGN,n); + } + } + + +} + + +void ProcessCursorDisplayStr(char* TmpStr){ + if(TmpStr[1]=='.'){ + TmpStr[1]=TmpStr[0]; + TmpStr[0]=' '; + } + TmpStr[2]=TmpStr[5]; + if(TmpStr[2]=='u')TmpStr[2]='m'; + TmpStr[3]=' '; + TmpStr[4]=0; +} + +void CalculateVvernier(u8 mode){ +s32 k=0; + + if(mode>0)MinBypass=0; + if(mode==0){ //delta V calculations + k=(_V1_Vernie-_V2_Vernie)*_Meas_V_Scale; + if (Title[_Meas_V_Track][SOURCE].Value>2)k*=10; + Int2Str(VNumStr,k, V_UNIT, 3, SIGN,0); + return; + }else if(mode==1){ //V1 and V2 cursor display calculations + if(_Det==0)k=(_V1_Vernie-Title[_Meas_V_Track][POSI].Value)*_Meas_V_Scale; + else k=(_V2_Vernie-Title[_Meas_V_Track][POSI].Value)*_Meas_V_Scale; + if (Title[_Meas_V_Track][SOURCE].Value>2)k*=10; + }else{ //trigger display calculations + if(_Tr_source==0)k=(_Vt1-_1_posi)*Y_Attr[Title[0][2].Value].SCALE; + else if((_Tr_source==2)||(_Tr_source==3))k=1000*Y_Attr[0].SCALE; //default approx of 2.0 V trig for V2.81 FPGA digital inputs + else k=(_Vt2-_2_posi)*Y_Attr[Title[1][2].Value].SCALE; + if(((_Tr_source<2)||(_Tr_source==4))&&(Title[_Tr_source][SOURCE].Value>2))k*=10; + } + Int2Str(CursorDisplayStr,k, VV_UNIT, 3, SIGN,0); +} + +void AutoSet(void){ +u8 static AmaxLimit=0,Asignal=0,Bsignal=0,BmaxLimit=0,Abase=0,Bbase=0,AdjustFlag=0,RecurseLimit=75,AutoTrigStatus=0; +s16 static AminLimit=0,BminLimit=0,AtLevel=100,BtLevel=100; +u8 i; + + if(AutoSetFlag==1){ //initiate + save_parameter(); + Title[7][1].Value = 3; // >Vt trig type + OldCurDefTime=CurDefTime; + if (FlagFrameMode==0){ + FlagFrameMode=1; + if (_Mode!=SCAN)OldPosi=GetXpos(XposRef); + } + if(FlagMeter){MeterStatus=FlagMeter;FlagMeter=0;DisableMeter();} + else MeterStatus=0; + OSBuffer=1; OSAvg=0; //use 8x oversampling, minimizes aliasing + if(FPGAsubVer)FPGAosFlag=0; + InitiateOSBuffers(); + OsBufferLogicFlag=OSBufferLogic(); + ShowFFT=0; + App_init(0); + AutoSetFlag=2; AutoSequence=0; + CurDefTime=1; //narrow measuring window to clear signal settling from Ypos changes + Title[0][SOURCE].Value = 1; Title[1][SOURCE].Value = 1; + Title[2][SOURCE].Value = 0; Title[3][SOURCE].Value = 0; + if(Title[0][1].Value > 1)Title[0][1].Value = 0; + if(Title[1][1].Value > 1)Title[1][1].Value = 0; + Title[7][0].Value = 0; + _Mode=SCAN; _T_base=11; //use scan/auto modes to ensure waveform aquisition + _A_Range=0; _B_Range=0; + Asignal=0; Bsignal=0; + AdjustFlag=0; + _1_posi=100; _2_posi=100; + AutoTrigStatus=TrgAuto; + if(TrgAuto==0)TrgAuto=2; //use auto trig + Update_Base(); + Update_Range(); + Update_Trig(1); + Process(); + StartUart=0; UartFileSize=0; + Update_View_Area(); + XposRef=120;_X_posi.Value=GetXpos(XposRef); //expands single window buffer + AutoSetTimer=5; + return; + } + + if((FrameEndFlag)&&(AutoSetTimer==0)&&(AutoSetFlag==2)){ + if((a_Max>110)||(a_Min<90))Asignal=1; //treshold at +/- 20mV to reject noise and baseline DC offset + if((b_Max>110)||(b_Min<90))Bsignal=1; + if((Asignal==0)&&(Bsignal==0))return; //if no signal, loop back from here + else AutoSetFlag=3; + _T_base=21; + Update_Base(); + return; + } + + if(AutoSetFlag==3){ //set up according to which channels were found with signals + AutoSetFlag=4; + RecurseLimit=75; + if((Asignal)&&(Bsignal)){ + Title[0][SOURCE].Value = 1; Title[1][SOURCE].Value = 1; + Title[7][0].Value = 0; + _1_posi=50;_2_posi=150; + AmaxLimit=100; + AminLimit=5; + BmaxLimit=195; + BminLimit=100; + RecurseLimit=38; + }else if(Asignal){ + Title[0][SOURCE].Value = 1; Title[1][SOURCE].Value = 0; + Title[7][0].Value = 0; //trigger source + _1_posi=100; + AmaxLimit=190; + AminLimit=10; + }else if(Bsignal){ + Title[0][SOURCE].Value = 0; Title[1][SOURCE].Value = 1; + Title[7][0].Value = 1; + _2_posi=100; + BmaxLimit=190; + BminLimit=10; + } + Update_Trig(1); + AutoSetTimer=10; + return; + } + + Update_Trig(1); + + if((__Get(FIFO_START)==0)&&(_T_base<11)&&(AutoSetTimer==0) //DC only signal detected + &&(FrameEndFlag==0)){ + + if(AutoSetFlag<50){ //attempt to trigger on any AC riding on DC with auto trigger + AutoSetTimer=5; + AutoSetFlag++; + return; + } + Abase=7; //if can't trigger on AC component set timebase to 5mS/div: useful + Bbase=7; //to display powerline ripple, etc, and exit + goto Untriggered; + + }else if((FrameEndFlag)&&(AutoSetTimer==0)){ //if triggered (W/Tb<11) or mode=SCAN (scan is always triggered) + AutoSetTimer=5; //allows enough time for signal to settle after changing Ypos and V/div ranges + + if(AutoSequence==0){ + + if(!((Asignal)&&(Bsignal))){ //adjust Y positions to nearest screen major division + if((((Asignal)&&(a_Min!=a_Max))||((Bsignal)&&(b_Min!=b_Max)))||(_T_base<15)){ + _1_posi=100+(_1_posi-(((((a_Min+a_Max)/2)+12)/25)*25)); + _2_posi=100+(_2_posi-(((((b_Min+b_Max)/2)+12)/25)*25)); + if(_1_posi>175)_1_posi=175;else if(_1_posi<25)_1_posi=25; + if(_2_posi>175)_2_posi=175;else if(_2_posi<25)_2_posi=25; + } + } + + if((Asignal)&&(_A_Range<7)&&((a_Max>AmaxLimit)||(a_MinBmaxLimit)||(b_Min4)){ + if(((TaN<2)||(Asignal==0))&&((TbN<2)||(Bsignal==0))&&(_T_base>4)){ + _T_base--; //make sure full extent of + and - peaks are included. + if(_T_base<11)_Mode=AUTO; + Update_Base(); + Title[6][1].Flag |= UPDAT; + }else{ //with V range set, move out of block. + if(AdjustFlag==3){ + AutoSequence++; + return; + } + //readjust v ranges with proper timebase by increasing gain + re-testing + if( (((TaN>0)&&(Asignal))||((TbN>0)&&(Bsignal)) || (_T_base==4)) + &&(AdjustFlag==0) ){ + if(((a_Max-_1_posi)0)_A_Range--; + } + if(((b_Max-_2_posi)0)_B_Range--; + } + Update_Range(); + AdjustFlag=1; + return; + } + } + + } + + if((Asignal)&&(AutoSequence==1)){ //adjust timebase using A channel + AtLevel=_Vt1; //aquire chA trig level + Title[7][0].Value = 0; //trigger source + AutoSequence=2; + if((_T_base%3)==1){ + if(TaN>3)Abase=_T_base+1;else Abase=_T_base; //5-2 shift + }else{ + if(TaN>2)Abase=_T_base+1;else Abase=_T_base; //2-1 shift + } + if(Abase>21)Abase=21; + if(Bsignal){ + Title[7][0].Value = 1; //if B channel also active loop around to aquire trigger level + Update_Trig(1); + return; + } + }else if((Asignal==0)&&(AutoSequence==1)){ + AutoSequence=2; + } + + if((Bsignal)&&(AutoSequence==2)){ + BtLevel=_Vt2; //aquire chB trig level + AutoSequence=3; + if((_T_base%3)==1){ //adjust timebase using B channel + if(TbN>3)Bbase=_T_base+1;else Bbase=_T_base; + }else{ + if(TbN>2)Bbase=_T_base+1;else Bbase=_T_base; + } + if(Bbase>21)Bbase=21; + }else if((Bsignal==0)&&(AutoSequence==2)){ + AutoSequence=3; + Bbase=Abase; + } + + if(AutoSequence==3){ //exit out of function +Untriggered: + CurDefTime=OldCurDefTime; //return "borrowed" Cursor defined meter function setting + AutoSequence=0; + Title[2][SOURCE].Value=TempPar[9]; //restore digital channels + Title[3][SOURCE].Value=TempPar[13]; //and chD special functions + Title[6][0].Value=TempPar[17]; //restore timebase mode + if(_Mode==SCAN)_Mode=AUTO; //only allow triggered modes to persist + OSBuffer=TempPar[51]; //restore buffer mode + FlagFrameMode=TempPar[52]; + OSAvg=TempPar[53]; + FPGAosFlag=TempPar[60]; + _Vt1=AtLevel; //set aquired trigger levels + _Vt2=BtLevel; + + if((Asignal)&&(Bsignal)){ + Title[0][SOURCE].Value = 1; Title[1][SOURCE].Value = 1; //engage A&B trig mode if this was on at start and both ch's have signal + if(TempPar[56]==4){ + Title[7][0].Value=4; + if(OldMode==SCAN)OldMode=AUTO; //avoid untriggered mode after leaving function + _Mode=NORH; + Update_Trig(0); + }else{ + Title[7][0].Value=0; + Update_Trig(1); + } + _1_posi=50;_2_posi=150; + _T_base=(Abase+Bbase)/2; + UpdateMeter=4; //set meter page to A&B + }else{ + if(Asignal){ + Title[0][SOURCE].Value = 1; + Title[1][SOURCE].Value = 0; + Title[7][0].Value = 0; + _T_base=Abase; + UpdateMeter=0; //meter page = A + } + if(Bsignal){ + Title[1][SOURCE].Value = 1; + Title[0][SOURCE].Value = 0; + Title[7][0].Value = 1; + _T_base=Bbase; + UpdateMeter=1; //meter page = B + } + Update_Trig(1); + } + AutoSetFlag=0; //disable function + TempPar[0]=0; //discard saved parameters + Current=6;Detail[6]=1; //forces menu to timebase adjust position + for(i=0;i<4;i++)Title[i][0].Flag |= UPDAT; + Title[6][0].Flag |= UPDAT; + Title[7][0].Flag |= UPDAT; + UpdateMeterPage(); + TrgAuto=AutoTrigStatus; + Update_Base(); + Update_Range(); + if(MeterStatus){FlagMeter=MeterStatus;EnableMeter();} + ShowFFT=0; + App_init(0); //updates settings without clearing screen + XposRef=120; //sets Xpos to 1 major division from left edge of screen + _X_posi.Value=GetXpos(XposRef); + } + + } + +} + + + /******************************** END OF FILE *********************************/ + + \ No newline at end of file diff --git a/Process.c b/Process.c new file mode 100644 index 0000000..3d4c3e2 --- /dev/null +++ b/Process.c @@ -0,0 +1,3232 @@ +/******************** (C) COPYRIGHT 2009 e-Design Co.,Ltd. ********************* + File Name : Process.c + Version : DS203_APP Ver 2.3x Author : bure +*******************************************************************************/ +#include "Interrupt.h" +#include "Function.h" +#include "Process.h" +#include "Draw.h" +#include "Menu.h" +#include "BIOS.h" +#include "File.h" +#include "Calibrat.h" +#include "stm32f10x_map.h" + + +// FFT //////////////////////////////////////////////////////////////////// +s32 fr[FFTSize]; +s32 fi[FFTSize]; +u32 NFreq; +char NFreqStr[12]; +int imax; +short PeakFreq; +char BaseFreqStr[12]; +char PeakFreqStr[12]; +char FreqDivStr[12]; +char FreqT1Str[12]; +//////////////////////////////////////////////////////////////////////////// + +u32 Sum[4]={0,0,0,0}; //averaging accumulators +u16 NAvg[4]={0,0,0,0}; +u16 VNAvg[2]={0,0}; +s32 VxAvg[2]={0,0}; +s32 VxSsq[2]={0,0}; +u32 PxS[4]={0,0,0,0}; +u32 TxS[4]={0,0,0,0}; +u32 TxN[4]={0,0,0,0}; + +u16 TaS, TbS, TcS, TdS; // cycles accumulated +u16 PaS, PbS, PcS, PdS; // pulse width of the cumulative +u16 TaN, TbN, TcN, TdN; // Cycle Count +s16 a_Mid_H, a_Mid_L; +s16 b_Mid_H, b_Mid_L; + +s32 a_Avg, b_Avg, a_Ssq, b_Ssq; // use signed integers, allows values at bottom of screen to be read +s16 a_Max, b_Max, a_Min, b_Min; // 0 levels can get pushed up by calibration, bringing bottom of screen below 0 +s16 aT_Max, bT_Max, aT_Min, bT_Min; // for auto trigger, kept separate from meter data for curdeftime + +s16 Posi_412,Posi_41_2, Posi_41, Posi_42, Posi_4_2, Posi_4F1, Posi_4F2, Posi_4F3, Posi_4F4; +s16 c_Max=0, d_Max=0, A_Posi, B_Posi; +u8 BailoutFlag=0; +u16 JumpCnt,CountUnread; +u8 FrameMode; +u8 HoldOnNext =0; +u16 bag_max_buf = 4096; +u8 freerun=0; //flags for auto trig mode +u8 exitflag=0; +u8 entryflag=0; +u8 ADCoffset=54; //shifts ADC/FIFO operating area away from non-linear first xx steps into previously unused linear 200-255 step area +u16 TempKp1=1024; +u8 CalFlag; +u8 CurDefTime=0; +u8 Options; //options flag +u8 HoldResetFlag=0; +s16 Xtend; //buffer size control +u8 discard=0; //pre-signal trace blanking +s16 TrigSourceEnable=1; //for alternate triggering, end of cycling, will go to chA +u32 ReverseBitMask; +u32 BitMask; +u16 AltHoldoff=0; +s8 OldShift=0; +u8 ClearMeterAreaFlag=0; +u8 ScalingOffset=40; //centers Ka3 Y-position scaling factor on a step other than 0 + //25= same as calibration gain correction (Ka2) zero + //40= same as y-position alignment offset (Ka1) zero calibration point +u16 QStart[2]={0,0}; //quantization error start/stop reference positions +u16 QEnd[2]={0,0}; +u8 LastA_Mid=0; //trigger level points for time meter quantization error calculations +u8 LastB_Mid=0; +u8 FirstA_Mid=0; +u8 FirstB_Mid=0; +u8 SumResetFlag=0; //resets meter summing function +u32 UTmp; +u8 EnablePaS=1; //controls update speed of PaS and PbS derived calcs (TH, TL, %duty) in large meters +u8 ClearHoldFlag=0; +u8 SlowModeSkip=0; +u8 ClearLeadingEdge=0; //WAS 0 +u8 FFTflag=0; +u8 Normal=100; +u8 FrameEndFlag; +u8 FFTGain=0; +u16 BufferSize=512; +u8 EnableFFT; +u8 Filter=40; +u8 InitiateNoise; +s32 Waste; +s8 PrevSweepIndex=-1; +u8 ResetFlag=0; +u16 ARBT_ARR; +u8 M_Factor=1; +u8 WaitForTrigFlag=0; +s16 Ch1TLevel=100; +s16 Ch2TLevel=100; +u8 SerialStatus; +u8 StartUart=0; +u32 USART1_DR=((u32)(USART1_BASE + 0x04)); +u8 InitiateUartGen=0; +u8 OsTransferCompleteFlag; +//u8 OsFFTData[2][640]; +u8 OsFFTData[2][700]; +u8 AutoTrigIni=0; +//u8 RMSdata[2][640]; +u8 RMSdata[2][700]; +u8 InvertA=0; +u8 InvertB=0; +u8 ScrollFlag=2; +u8 ErrorFlag=0; +u8 FPGAver=0; +u8 FPGAsubVer=0; +u8 JComp=1; +u8 FreeRunEnable=1; +u8 FPGAosFlag=0; +u16 FPGA_OS_Size=0; +u8 OffsetSelect=0; +u8 ResetEnableFFT=0; +u8 FastMode=1; +u8 ChartMode=0; +u8 OsChartFlag=0; +u8 ToggleName=0; +u8 DisableCursorTimer=0; +u16 DownConvert=0; +u32 FreqIN; +u8 DownConvertInitiate=0; +u32 FFTScale=0; +u8 DCbase; +u8 DCframe; +u8 DCmode; +u8 DCmeter; +u8 FreqScaleShift; +u8 DownConvertShiftEnable=0; +u32 LfreqPeriod; +u16 PrecisionLevel=0; +u8 FFTt1Mode=0; +u16 DCt1=0; + +void Beeper(u16 ms); //alarms +void AlternateChannel(void); //for A&B mode +void SetOffset(u8 channel,u8 range, s16 Ypos); //sets Ka3,Kb3 zero level reference +void BatLevelCompensation(void); +s8 InterpolateS8(u8 Ch, s8 L8,s8 H8); //for battery level comp +u16 InterpolateU16(u8 Ch, u16 L16,u16 H16); +s16 QParam(u8 Ch, u16 Position,u8 service); //for Qerror +s32 QError(u8 Ch, u16 Start, u16 End, u32 Utmp); //quantization error compensation +void Average(u8 Ch); +void RunAvg(u8 Ch); +s32 VRunAvg(u8 Ch, s32 Value, s32 Sum); +void cleardatabuf(u8 service); +s32 Log10Process(u16 i); +u8 TriggerModeLogic(void); +void SetIRQ2Priority(void); +void CalculateArbtTimer(void); +void UpdateTLevels(void); +void SetTthreshold(u16 Time); +void UpdateCursorMeter(void); +void CursorDisplaySelectLogic(void); + +s16 WaveValue(u16 j); +u8 TriggerType=0; +u8 SubIndex=0; +s16 WindowPosition; + +//u8 StartOffset=16; //this displayed trigger point ~2 samples to left of trigger vernier on factory FPGA, ~4 on custom FPGA +u8 StartOffset=14; //NOTE: 2 sample delay buffer now used for data aligns with trigger's 2 sample delay so need default of 16(?) + +u8 OsBufferLogicFlag=0; +u8 OSAvg=0; +u8 PrevSource=0xFF,PrevKind=0xFF; +u8 InvTrig[8]={1,0,3,2,6,7,4,5}; +u8 HardwareVersion; + + +const SubTbase TbaseSub[13]={ + // .Psc .Arr .S_OS_Size .Ratio + {1-1, 2400-1, 100, 10}, //.1S + {1-1, 4800-1, 100 , 5}, //.2S + {1-1, 8000-1, 150 , 2}, //.5S + {1-1, 16000-1, 150 , 1}, //1S + {1-1, 32000-1, 150 , 2}, //2S + {1-1, 60000-1, 200 , 5}, //5S + {10-1, 12000-1, 200 , 10}, //10S + {10-1, 12000-1, 300 , 15}, //15S + {10-1, 24000-1, 300 , 30}, //30S + {10-1, 36000-1, 400 , 60}, //60S + {100-1, 7200-1, 400 , 120}, //2M + {100-1, 12000-1, 600 , 300}, //5M + {100-1, 24000-1, 600 , 600}}; //10M + + +const OSTbase TbaseOS[17]={ + // .Psc .Arr + {200-1,1500-1}, //1S + {100-1,1500-1}, //500MS + {40-1,1500-1}, //200MS + {40-1,750-1}, //100MS + {40-1,375-1}, //50MS + {16-1,375-1}, //20MS + {8-1,375-1}, //10MS + {4-1,375-1}, //5mS + {4-1,150-1}, //2MS + {2-1,150-1}, //1MS + {1-1,150-1}, //500uS + {1-1,60-1}, //200uS + {1-1,30-1}, //100uS + {1-1,15-1}, //50uS + {1-1,6-1}, //20uS + {1-1,3-1}, //10uS + {1-1,2-1}}; //5uS + +const FPGAosTbase FPGA_TbaseOS[20]={ + //.Psc .Arr .OS_Size .Limit + {1-1,40-1, 60000, 5 }, //1S + {1-1,20-1, 60000, 5 }, //500MS + {1-1,8-1, 60000, 5 }, //200MS + {1-1,4-1, 60000, 5 }, //100MS + {1-1,2-1, 60000, 5 }, //50MS + {1-1,1-1, 48000, 5 }, //20MS + {1-1,1-1, 24000, 5 }, //10MS + {1-1,1-1, 12000, 5 }, //5mS + {1-1,1-1, 4800 , 5 }, //2MS + {1-1,1-1, 2400 , 5 }, //1MS + {1-1,1-1, 1200 , 4 }, //500uS + {1-1,1-1, 480 , 5 }, //200uS + {1-1,1-1, 240 , 4 }, //100uS + {1-1,1-1, 120 , 3 }, //50uS + {1-1,1-1, 48 , 3 }, //20uS + {1-1,1-1, 24 , 2 }, //10uS + {1-1,1-1, 12 , 1 }, //5uS + {1-1,1-1, 5 , 0 }, //2uS + {1-1,1-1, 3 , 0 }, //1uS + {1-1,1-1, 2 , 0 }}; //.5uS + + +uc16 Wait[22]= {1000, 500, 200, 100, 65, 30, 20, 10, 5, 3, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2}; + +uc16 shortwait[22]= {600, 250, 100, 75, 35, 15, 10, 10, 5, 3, //for auto trig mode, set time to hold before going auto + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2 }; + + +uc16 TrigDelayLoop[10]= {2,4,10,20,40,100,200,400,1000,2000}; //for trig holdoff, sets how many time loops before allowing rest of program to function + +uc16 AltDelay[21]= {1000, 500, 300, 150, 75, 30, 15, 8, 4, 2}; //for alt trig mode, sets time to wait for trigger in other ch if untriggered + +uc16 TimeBase[22]= {50000,50000,20000,10000,5000,2000,1000,500,200,100,50,20,10,5,2,1,1,1,1,1,1,1}; + +Y_attr *Y_Attr; +X_attr *X_Attr; +G_attr *G_Attr; +T_attr *T_Attr; + +u32 DataBuf[4096]; //could save 4K of RAM here, using u16 + u8 struct +u8 TrackBuff [397 * 4]; // curve track: i +0, i +1, i +2, i +3, respectively, placed one on the 4th track data + +uc8 Log10Mant[100]={ 0, 0, 3, 5, 6, 7, 8, 8, 9, 10, 0, 4, 8,11,15,18,20,23,26,28,30,32,34,36,38, //0-9: scale x10, 10-99: scale x100 + 40,41,43,45,46,48,49,51,52,53,54,56,57,58,59,60,61,62,63,64,65,66,67,68,69, + 70,71,72,72,73,74,75,76,76,77,78,79,79,80,81,81,82,83,83,84,85,85,86,86,87, + 88,88,89,89,90,90,91,91,92,92,93,93,94,94,95,95,96,96,97,97,98,98,99,99,100}; + +uc8 Window[512]= //Hann window + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, + 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 8, + 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 17, 17, 18, 18, 19, + 20, 20, 21, 21, 22, 23, 23, 24, 25, 25, 26, 27, 28, 28, 29, 30, 30, 31, 32, 33, + 33, 34, 35, 36, 37, 37, 38, 39, 40, 41, 41, 42, 43, 44, 45, 46, 46, 47, 48, 49, + 50, 51, 52, 53, 53, 54, 55, 56, 57, 58, 59, 60, 61, 61, 62, 63, 64, 65, 66, 67, + 68, 69, 70, 71, 72, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 84, 85, + 86, 87, 88, 89, 90, 91, 92, 93, 93, 94, 95, 96, 97, 98, 99,100,101,101,102,103, + 104,105,106,106,107,108,109,110,111,111,112,113,114,115,115,116,117,118,118,119, + 120,121,121,122,123,124,124,125,126,126,127,128,128,129,130,130,131,131,132,133, + 133,134,134,135,135,136,137,137,138,138,139,139,140,140,140,141,141,142,142,143, + 143,143,144,144,144,145,145,145,146,146,146,147,147,147,147,148,148,148,148,148, + 149,149,149,149,149,149,149,150,150,150,150,150,150,150,150,150,150,150,150,150, + 150,150,150,150,150,149,149,149,149,149,149,149,148,148,148,148,148,147,147,147, + 147,146,146,146,145,145,145,144,144,144,143,143,143,142,142,141,141,140,140,140, + 139,139,138,138,137,137,136,135,135,134,134,133,133,132,131,131,130,130,129,128, + 128,127,126,126,125,124,124,123,122,121,121,120,119,118,118,117,116,115,115,114, + 113,112,111,111,110,109,108,107,106,106,105,104,103,102,101,101,100, 99, 98, 97, + 96, 95, 94, 93, 93, 92, 91, 90, 89, 88, 87, 86, 85, 84, 84, 83, 82, 81, 80, 79, + 78, 77, 76, 75, 74, 73, 72, 72, 71, 70, 69, 68, 67, 66, 65, 64, 63, 62, 61, 61, + 60, 59, 58, 57, 56, 55, 54, 53, 53, 52, 51, 50, 49, 48, 47, 46, 46, 45, 44, 43, + 42, 41, 41, 40, 39, 38, 37, 37, 36, 35, 34, 33, 33, 32, 31, 30, 30, 29, 28, 28, + 27, 26, 25, 25, 24, 23, 23, 22, 21, 21, 20, 20, 19, 18, 18, 17, 17, 16, 15, 15, + 14, 14, 13, 13, 12, 12, 11, 11, 10, 10, 9, 9, 8, 8, 8, 7, 7, 6, 6, 6, + 5, 5, 5, 4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, + 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + + s8 Ka1[10], Kb1[10]; + u16 Ka2[10], Kb2[10]; + s8 Ka3[10], Kb3[10]; + s8 HKa1[10], HKb1[10]; + u16 HKa2[10], HKb2[10]; + s8 HKa3[10], HKb3[10]; + s8 LKa1[10], LKb1[10]; + u16 LKa2[10], LKb2[10]; + s8 LKa3[10], LKb3[10]; + +u16 HiBatLevel[2]={0,0}; //high battery correction reference level +u16 LoBatLevel[2]={0,0}; //low battery correction reference level +u16 PrevBatLevel=0; +u16 VDiff[2]={0,0}; + +D_tab D_Tab[23] ={ // pulse waveform output driver table, based on the 72MHz frequency +// PSC ARR + { 2400-1,30000-1}, //1 0 + { 1200-1,30000-1}, //2 1 + { 480-1, 30000-1}, //5 2 + { 240-1, 30000-1}, //10 3 + { 120-1, 30000-1}, //20 4 + { 48-1, 30000-1}, //50 5 + { 24-1, 30000-1}, //100 6 + { 12-1, 30000-1}, //200 7 + { 5-1, 28800-1}, //500 8 + { 2-1, 36000-1}, //1K 9 + { 1-1, 36000-1}, //2K 10 + { 1-1, 14400-1}, //5K 11 + { 1-1, 7200-1}, //10K 12 + { 1-1, 3600-1}, //20K 13 + { 1-1, 1440-1}, //50K 14 + { 1-1, 720-1}, //100K 15 + { 1-1, 360-1}, //200K 16 + { 1-1, 144-1}, //500K 17 + { 1-1, 72-1}, + { 1-1, 36-1}, + { 1-1, 18-1}, + { 1-1, 12-1}, + { 1-1, 9-1}}; // 22 + + //previous versions used 1.8Mhz sampling rate for 25Khz range (@ 72samples/period) + +uc32 A_Freq[18]={1,2,5,10,20,50,100,200,500,1000,2000,5000,10000,20000,50000,100000,200000,500000}; + +uc8 ScaleIndex[17]={1,1,1,1,1,1,1,1,1,1,1,2,4,10,20,40,80}; //for max DAC sampling rate of 1.8Mhz(DAC is only rated to 1Mhz but seems OK @ 1.8Mhz) +uc16 A_Tab[17]={ + 50000-1, //1Hz uses 36Mhz clock, rest 72Mhz + 50000-1, + 20000-1, + 10000-1, + 5000-1, //all except noted @ 720 samples/period (=<1.44Mhz sampling rate) + 2000-1, + 1000-1, + 500-1, + 200-1, //500Hz + 100-1, //1Khz + 50-1, //2Khz + 40-1, //5Khz @ 360 samples/period (1.8Mhz sampling rate) + 40-1, //10Khz @ 180 samples/period (1.8Mhz sampling rate) + 50-1, //20Khz @ 72 samples/period (1.44Mhz sampling rate) + 40-1, //50Khz @ 36 samples/period (1.8Mhz sampling rate) 14 + 40-1, //100Khz@ 18 samples/period (1.8Mhz sampling rate) + 40-1}; //200Khz@ 9 samples/period (1.8Mhz sampling rate) + + +s16 ATT_DATA[720]; //could go up to 2880 to allow long arb digital streams + +sc16 SIN_QUAD[181]={ 2048 , 2066 , 2084 , 2102 , 2119 , 2137 , 2155 , 2173 , 2191 , 2209 , 2226 , + 2244 , 2262 , 2280 , 2297 , 2315 , 2333 , 2351 , 2368 , 2386 , 2403 , 2421 , + 2439 , 2456 , 2474 , 2491 , 2508 , 2526 , 2543 , 2561 , 2578 , 2595 , 2612 , + 2629 , 2646 , 2664 , 2681 , 2698 , 2714 , 2731 , 2748 , 2765 , 2782 , 2798 , + 2815 , 2831 , 2848 , 2864 , 2881 , 2897 , 2913 , 2929 , 2945 , 2961 , 2977 , + 2993 , 3009 , 3025 , 3040 , 3056 , 3072 , 3087 , 3102 , 3118 , 3133 , 3148 , + 3163 , 3178 , 3193 , 3207 , 3222 , 3237 , 3251 , 3266 , 3280 , 3294 , 3308 , + 3322 , 3336 , 3350 , 3364 , 3377 , 3391 , 3404 , 3418 , 3431 , 3444 , 3457 , + 3470 , 3483 , 3495 , 3508 , 3520 , 3533 , 3545 , 3557 , 3569 , 3581 , 3593 , + 3605 , 3616 , 3628 , 3639 , 3650 , 3661 , 3672 , 3683 , 3693 , 3704 , 3714 , + 3725 , 3735 , 3745 , 3755 , 3765 , 3774 , 3784 , 3793 , 3803 , 3812 , 3821 , + 3830 , 3838 , 3847 , 3855 , 3864 , 3872 , 3880 , 3888 , 3896 , 3903 , 3911 , + 3918 , 3925 , 3932 , 3939 , 3946 , 3953 , 3959 , 3965 , 3972 , 3978 , 3983 , + 3989 , 3995 , 4000 , 4006 , 4011 , 4016 , 4021 , 4025 , 4030 , 4034 , 4038 , + 4043 , 4046 , 4050 , 4054 , 4057 , 4061 , 4064 , 4067 , 4070 , 4073 , 4075 , + 4077 , 4080 , 4082 , 4084 , 4086 , 4087 , 4089 , 4090 , 4091 , 4092 , 4093 , + 4094 , 4094 , 4095 , 4095 , 4095 }; + +sc16 Sine100K[18]= // + {0x9C0,0xC59,0xE68,0xFAB, + 0xFFF,0xF70,0xDF5,0xBBD,0x90E, + 0x63E,0x3A5,0x196,0x053, + 0x000,0x08E,0x209,0x441,0x6F0}; + +sc16 Sine200K[9]= + {0xC59,0xFAB, + 0xF70,0xBBD, + 0x63E,0x196, + 0x000,0x209,0x6F0}; + +sc16 Triangle100K[18] = + {0x8E2,0xAA9,0xC70,0xE37, + 0xFFE,0xE37,0xC70,0xAA9,0x8E2, + 0x71B,0x554,0x38D,0x1C6, + 0x000,0x1C6,0x38D,0x554,0x71B}; + +sc16 Triangle200K[9] = + {0xAA9,0xE37, + 0xE37,0xAA9, + 0x71B,0x38D, + 0x000,0x38D,0x71B}; + +sc16 DIGI_DATA[2] = // Square wave data // + {2047,-2048}; + +void BackGround_Reset(u8 clear) +{ + u8 i, j; + u8 TitleLimit=13; + if ((FlagMeter==2)&&(UpdateMeter!=4))TitleLimit=11; + if(clear)__Clear_Screen(BLACK); + Delayms(100); + for(i=0; i2)Amode=0; //DC coupling for serial decode + if (Bmode>2)Bmode=0; + + __Set(CH_A_COUPLE, Amode); + __Set(CH_A_RANGE, Title[TRACK1][RANGE].Value); + SetOffset(0,_A_Range,_1_posi); + __Set(CH_B_COUPLE, Bmode); + __Set(CH_B_RANGE, Title[TRACK2][RANGE].Value); + SetOffset(1,_B_Range,_2_posi); + if(SerialStatus)UpdateTLevels(); + if((Sweep)||(Det)){ + Update_Output(); + if(Title[TRIGG][SOURCE].Value==4) Update_Trig(0); else Update_Trig(1); + } +} +/******************************************************************************* + Update_Base: +*******************************************************************************/ +void Update_Base(void) +{ + u16 i,Tmp; + u16 FPGA_ARR; + + if(DownConvertMode)return; + __Set(ADC_CTRL, EN); + if(ChartLogic()){ + + __Set(T_BASE_PSC, TbaseSub[SubIndex-1].Psc); + __Set(T_BASE_ARR, TbaseSub[SubIndex-1].Arr); + + __Set(32+0x0F,0x00); //shut off FPGA oversampling + __Set(32+0x10,0x00); + __Set_Param(8,0x96); + __Set_Param(9,0x00); //normal 150 sample pre-sampling depth + }else{ + i = Title[T_BASE][BASE].Value; + + if(OSBufferLogic()){ + + if((FPGAsubVer)&&(FPGAosFlag)){ + + if(OS_Range>FPGA_TbaseOS[_T_base].Limit)Tmp=FPGA_TbaseOS[_T_base].Limit; + else Tmp=OS_Range; + FPGA_OS_Size=FPGA_TbaseOS[_T_base].OS_Size>>Tmp; + FPGA_ARR=((FPGA_TbaseOS[_T_base].Arr+1)<> 8)); + __Set_Param(8,0x96); + __Set_Param(9,0x00); //normal 150 sample pre-sampling depth + __Set(T_BASE_PSC,FPGA_TbaseOS[i].Psc); //FPGA based oversampling + __Set(T_BASE_ARR,FPGA_ARR); + + if(XposRef>150)XposRef=150; + + }else{ + __Set(32+0x0F,0x00); //shut off FPGA oversampling + __Set(32+0x10,0x00); + if(_T_base<16) Tmp=(1208-(_X_posi.Value*8))+(StartOffset*8); + else Tmp=(908-(_X_posi.Value*6))+(StartOffset*6); + __Set_Param(8,(Tmp&0xFF)); //stabilize window position and shift trigger point to match xpos rather + __Set_Param(9,((Tmp>>8)&0xFF)); //than shifting window to keep buffer size at 512 (X8= 4096) + __Set(T_BASE_PSC,TbaseOS[i].Psc); + __Set(T_BASE_ARR,TbaseOS[i].Arr); + } + + }else{ + __Set(32+0x0F,0x00); //shut off FPGA oversampling + __Set(32+0x10,0x00); + __Set_Param(8,0x96); + __Set_Param(9,0x00); //normal 150 sample pre-sampling depth + __Set(T_BASE_PSC, X_Attr[i].PSC); + __Set(T_BASE_ARR, X_Attr[i].ARR); + } + + SubIndex=0; //reset extended time base if moving out of SCAN mode + } + Wait_Cnt = Wait[_T_base]; + if(_Mode!=SCAN){ + if(_Status == RUN) __Set(FIFO_CLR, W_PTR); // FIFO write pointer reset + if((_T_base>16)||(OSBufferLogic())){if(Title[TRIGG][SOURCE].Value==4) Update_Trig(0); else Update_Trig(1);} + JumpCnt=0; + } +} + +void FFTdownConvert(u8 service){ + +static u32 Divisor,WindowShiftFactor,AdjDivisor,Base,Fsamp=0,RefFreq,AdjBase; +static u16 FFTorderADJ; +static s8 i; +s8 h; +u32 Adj,Tmp=0,Tmp2,j; +u16 AdjustedARR=0; +u32 PreScale=0; + + if(((FreqIN==0)&&(FFTt1Mode==0))||(DownConvertMode==0))return; + if(service==4){ + if(FreqIN>5000000)DownConvertShiftEnable=60; + else if(FreqIN>1500000)DownConvertShiftEnable=30; + else DownConvertShiftEnable=15; + service=0; + } + if(service==3)goto ReadFreqMeter; //meter reads + else if((service)||(DownConvertShiftEnable==2))goto ShiftWindow; //window shifts + + while(1){ + + if(DownConvertInitiate){ + if(FFTt1Mode){ //"T1" mode + Tmp=(NFreq/FFTBins)*_T1; + if(_T_base<12)Tmp/=1000; + _T1=128; + DownConvert=1; //reset to base magnification + }else{ + Tmp=FreqIN; + for(i=0;i<(FreqScaleShift);i++)Tmp/=10; //establish proper frequency from prior scaling + } + if(Tmp<215){ + DownConvertMode=0; + DownConvertRestore(); + return; + } + }else Tmp=RefFreq; + RefFreq=Tmp; + + WindowShiftFactor=((90000000/Tmp)+11)/22; + if(WindowShiftFactor==0)WindowShiftFactor=1; + Adj=DownConvert*125; //shift halfway up sub-order + Adj-=(Adj%100); //remove offset to obtain sub-order base + FFTorderADJ=Adj/100; //store unscaled base order + Adj+=25; //restore offset + Divisor=((7200*Adj)/RefFreq)*100; //calculate division ratio + Divisor+=(((((7200*Adj)%RefFreq)*100)+(RefFreq/2))/RefFreq); //add and round last 2 significant digits of precision + + if(Divisor>429495){ //limits slowest screen refresh to approx 2 to 3 seconds + switch(DownConvert){ //and reasonably accurate <1Hz calculations + case 5: + case 50: + case 500: + DownConvert/=5; + DownConvert*=2; + break; + default: + if(DownConvert>1)DownConvert/=2;else return; + } + }else break; + } + +ShiftWindow: + if(service==1)Divisor+=WindowShiftFactor; + else if(service==2)Divisor-=WindowShiftFactor; + + if(Divisor<1200)_T_base=12;else _T_base=7; //allows proper selection of buffer aquisition modes + __Set_Param(8,0x96); + __Set_Param(9,0x00); //normal 150 sample pre-sampling depth + + if(Divisor<61356){ //setup prescaling + PreScale=1; + AdjustedARR=Divisor; + }else{ + PreScale=(Divisor/61356)+1; //try to find integral prescale + while((Divisor%PreScale)!=0){ + PreScale++; + } + if(PreScale<61356){ //if integral ratios found + AdjustedARR=(Divisor/PreScale); + }else{ //if not keep prescale small and use rounded ARR + i=1; + for(j=122712;j<429496;j+=61356){ + i++; + if(Divisor1000000){ + Fsamp=((72000000/AdjDivisor)*100); //calculate downconverted sampling base + Tmp=((((72000000%AdjDivisor)*10000)/AdjDivisor)*FFTorderADJ)/100; //x10000 correction factor + Base=(Fsamp*FFTorderADJ)+Tmp; //actual frequency at base + i=-1; + }else{ + Fsamp=((72000000/AdjDivisor)*1000); + Tmp=((((72000000%AdjDivisor)*10000)/AdjDivisor)*FFTorderADJ)/10; + Base=(Fsamp*FFTorderADJ)+Tmp; + i=0; + } + AdjBase=ClockAdjust(Base); //adjust with CPU clock frequency correction + +ReadFreqMeter: + if(service==3){ //offset from sub-order fold + if(i==-1)Tmp2=(((LfreqPeriod/(Power(10,(ShiftDigits+1))))+(AdjDivisor/2))/AdjDivisor)*72; + else Tmp2=(((LfreqPeriod+(AdjDivisor/2))/AdjDivisor)*72)/(Power(10,(ShiftDigits))); + + if(AdjBase<1000000){Tmp=10;h=i+1;}else{Tmp=1;h=i;} + Int2Str(BaseFreqStr,(AdjBase*Tmp), F_UNITSUB , 7, UNSIGN,h); + Int2Str(PeakFreqStr,((AdjBase+Tmp2)*Tmp), F_UNITSUB , 7, UNSIGN,h); + Int2Str(NFreqStr,((AdjBase+(Fsamp>>1))*Tmp), F_UNITSUB , 7, UNSIGN,h); + if(Fsamp>10000000)j=((AdjBase+((((Fsamp>>1)+128)/FFTBins)*_T1))*Tmp); + else j=(( AdjBase+(((Fsamp*_T1)+256)/512))*Tmp); + Int2Str(FreqT1Str,j,F_UNITSUB, 7, UNSIGN,h); + + if((Fsamp*15)>286331000)Tmp=(((Fsamp+(FFTBins/2))/FFTBins)*15); + else Tmp=((Fsamp*15)+(FFTBins/2))/FFTBins; + if(Tmp<1000){Tmp*=10000;j=4;} + else if(Tmp<10000){Tmp*=1000;j=3;} + else if(Tmp<100000){Tmp*=100;j=2;} + else if(Tmp<1000000){Tmp*=10;j=1;}else j=0; + Int2Str(FreqDivStr,Tmp,F_UNITSUB, 7, UNSIGN,j+i); + + if(i==-1)Tmp=RefFreq*100;else Tmp=RefFreq*1000; + + if((imax>20)&&(imax<215)&&(Base>1))))Tmp=(Base+Tmp2); + if((Base>Tmp)||(Tmp>(Base+(Fsamp>>1)))) + {for(j=0;j<10;j++)PeakFreqStr[j]='-';PeakFreqStr[10]=0;} + + if(FFTt1Mode==0){ + if(i==-1)RefFreq=Tmp/100;else RefFreq=Tmp/1000; + } + + } + + if(FFTt1Mode){ + if(((DownConvert>PrecisionLevel)&&(service==0)) + ||((DownConvert>=PrecisionLevel)&&((service==1)||(service==2)))){ + if(service==0)PrecisionLevel=DownConvert; + if((service==1)||(service==2))_T1=128; //reset T1 to middle of screen if shifting window + if(i==-1)RefFreq=(Base+(((Fsamp>>1)/FFTBins)*_T1))/100; + else RefFreq=(Base+(((Fsamp>>1)/FFTBins)*_T1))/1000; + } + } + +} + +/******************************************************************************* + Update_Output: +*******************************************************************************/ +void Update_Output(void) { +u16 i,BaudDiv; + + if((StartUart)&&(_Kind==8)){ //transmit uart data + DMA1_Channel4->CCR &=~DMA_CCR1_EN; //disable usart1 dma access + USART1->SR &=0xFFBF; //clear bit 6 (transmission complete bit, TC) + DMA1_Channel4->CNDTR =UartFileSize; //number of bytes to load + DMA1_Channel4->CCR |=0x00000001; //enable + StartUart=0; + return; + }else if(_Kind==8){ + if(InitiateUartGen==0)InitiateUartGen=1;else goto AdjUartGen; + }else InitiateUartGen=0; + + if(_Frqn==0)TIM7->PSC=1; else TIM7->PSC=0; //set DAC clock to 36Mhz for 1Hz to avoid ARR overload, 72Mhz for rest + SetIRQ2Priority(); + TIM_2IRQControl(); + if(Title[TRIGG][SOURCE].Value==4) Update_Trig(0); else Update_Trig(1); + M_Factor=1; + + TIM4->CR1 = 0x0080; // SQR_OUT = Disable. Stops counter 0x80=auto reload preload enable + TIM4->DIER = 0x0000; // disable TIM4_INT + TIM4->CR2 = 0x0000; // disable update event as output + + AFIO->MAPR =0x04000000; //reset remaped PB6 alt function + USART1->CR1 =0x0000; //disable usart1 + RCC->APB2ENR &=0xFFFFBFFF; //disable usart1 clock + DMA1_Channel4->CCR &=~DMA_CCR1_EN;//disable usart1 dma access + + if(ResetFlag){ + TIM4->EGR=0x0001; // generate update event for full reset + TIM2->EGR=0x0001; + ResetFlag--; + } + DAC->CR = 0x00000000; // reset both channels + + if(_Kind == PWM){ //(4) + + if(Sweep==1){ //if in sweep mode, initialize analog as well as it uses this along with PWM + Title[OUTPUT][DUTYPWM].Value=15000; + DMA2_Channel4->CCR &= ~DMA_CCR1_EN; + for(i=0;i<720;i++)ATT_DATA[i]=2048; + ResetDMA2_Ch4Params(72); + __Set(ANALOG_ARR, 40-1); + } + __Set(DIGTAL_PSC, D_Tab[_Frqn].PSC); + __Set(DIGTAL_ARR, D_Tab[_Frqn].ARR); + + i=((D_Tab[_Frqn].ARR+1)*(30000-Title[OUTPUT][DUTYPWM].Value))/30000; + if(i==0)i++; + if(i>(D_Tab[_Frqn].ARR+1))i=(D_Tab[_Frqn].ARR+1); + + if((Sweep==1)||(PWAdjustMode==0)){ + __Set(DIGTAL_CCR,i); + }else{ + GPIOB->CRL &= 0xF0FFFFFF; + GPIOB->CRL |= 0x0B000000; + TIM4->CR1 = 0x0081; + } + TIM4->EGR=0x0001; //reset + + }else if(_Kind==5){ // random noise mode + + if(_Frqn>18)_Frqn=18; // DAC refresh limit, 1Mhz + InitiateNoise=1; + if(PrevSweepIndex<0)PrevSweepIndex=SweepIndex; + DMA2_Channel4->CCR &=0xFFFFFFFE; // release DMA channel from DAC + DMA1_Channel4->CCR &= ~DMA_CCR1_EN; //make sure ch is off (same as ccrX) + GPIOB->CRL = 0x34BBB438; // puts PWM port(TIM4/PB6) in input, floating mode + configures other bits + GPIOA->CRL = 0x110011BB; // puts DAC2 port (PA5) in input, analog mode + + if(_Frqn<8)i=_Frqn+6; // 100x averaging filter @ <500hz + else if(_Frqn<14)i=_Frqn+3; // 10x filter for 500hz - 20Khz + else i=_Frqn; // above 20Khz no filtering + TIM4->PSC = D_Tab[i].PSC; // oversampling setup + TIM4->ARR = D_Tab[i].ARR; + + if(_Frqn<16){ + TIM4->DIER|=0x0001; // enable TIM4_INT, engages seeding @ <200Khz and filters for frequencies <=20Khz + }else{ + TIM4->DIER=0x0000; // seeding by TIM2_INT for freq limits > 100Khz + SweepIndex=_Frqn-13; + } + TIM_2IRQControl(); + + TIM4->CR2 = 0x0020; // use update event as output + TIM4->CR1 = 0x0085; // turn on DAC2 clock, preload arr, update only on overflow + + if(_Frqn<14){ + DAC->CR = 0x0B6C002C; // set up both DACs to trigger from TIM4 update event: DAC2=generator > filter > DAC1=output + DAC->CR |= 0x00010001; // enable both channels + }else{ // above 20Khz + DAC->CR = 0x00000B6C; // set up DAC1 for generator and output + DAC->CR |= 0x00000001; // enable DAC1 + } + return; + + }else if(_Kind==6){ // generator turned off DAC, PWM and TIM4_INT already shut down at top of function + // shut down additional resources + set output low + DMA2_Channel4->CCR&= 0xFFFFFFFE; // release DMA channel from DAC + TIM7->CR1 = 0x0084; // shut off DAC timer + GPIOA->CRL |= 0x00040000; // disconnect DAC if connected + GPIOB->CRL &= 0xF0FFFFFF; // reset bit 6 control + GPIOB->CRL |= 0x03000000; // enable bit 6 as output + GPIOB->ODR &= 0x0000FFBF; // reset bit 6 to set gen output low + if(PrevSweepIndex<0)PrevSweepIndex=SweepIndex; + return; + + }else if(_Kind==7){ //arbitrary waveforms + + while((ArbtSampleNumber*A_Freq[_Frqn])>1800000)_Frqn--; //limit frequency range so sampling rate is <1.8Mhz + Title[OUTPUT][1].Flag|= UPDAT; + DMA2_Channel4->CCR &= ~DMA_CCR1_EN; + ResetDMA2_Ch4Params(ArbtSampleNumber); + CalculateArbtTimer(); + + }else if(_Kind==8){ //UART OUTPUT + + GPIOA->CRL &=0xFFF0FFFF; //reset PA4 control + GPIOA->CRL |=0x00080000; //PA4 (DAC1 port) set to input pull up/down mode + GPIOA->ODR |=0x00000010; //pull up port so idle line stays high through external connection with PB6 + + TIM4->PSC = 2400-1; //Generate update event for full reset, sets disabled TIM4 output low. + __Set(DIGTAL_ARR, 3000-1); //Remapped alternate function appears to be logically or'd with default + TIM4->CCR1 = 3000-1; //alternate function, so default needs to be at 0 level or it will shut + TIM4->EGR=0x0001; //remapped off. Could not find this defined in STM32 programming reference... + + AFIO->MAPR =0x04000004; //remap PB6 alt function to USART1 TX + RCC->APB2ENR |=0x00004000; //enable usart1 clock + GPIOB->CRL &=0xF0FFFFFF; //reset PB6 control + GPIOB->CRL |=0x09000000; //PB6 set to alt function, B=50Mhz 9=10Mhz push-pull output + +AdjUartGen: + switch(GenUartMode){ + case 1: + USART1->CR1 =0x2408; //uart1 enable, 7Pe + break; + case 2: + USART1->CR1 =0x2608; //uart1 enable, 7Po + break; + case 3: + USART1->CR1 =0x2008; //uart1 enable, 8N + break; + case 4: + USART1->CR1 =0x3408; //uart1 enable, 8Pe + break; + case 5: + USART1->CR1 =0x3608; //uart1 enable, 8Po + break; + case 6: + USART1->CR1 =0x3008; //uart1 enable, 9N + } + + if(GenUartStopBits==0) + USART1->CR2 =0x0000; //1 stop bit, clock disabled + else USART1->CR2 =0x2000; //2 stop bits + USART1->CR3 =0x0088; //enable DMA for transmit, half duplex (mode allows remap of PB6 only) + + if(GenBaudIndex<8485){ //below 8485 divider = index for baud rates 8485 to 4.5M + BaudDiv=GenBaudIndex; + GenBaudRate=72000000/GenBaudIndex; + }else{ //above 8485 baud rate 1:1 ratio with index, baud rate calculated for all integers down to 1099 + GenBaudRate=((15871-GenBaudIndex)+1099); + BaudDiv=72000000/GenBaudRate; + } + USART1->BRR =BaudDiv; + USART1->SR &=0xFFBF; //clear bit 6 (transmission complete bit, TC) + + DMA1_Channel4->CCR &=~DMA_CCR1_EN; //disable usart1 dma access + DMA1_Channel4->CPAR =(u32)USART1_DR; //usart data register address + DMA1_Channel4->CMAR =(u32)SecBuff; //file data + DMA1_Channel4->CNDTR =0; //only initialize + DMA1_Channel4->CCR =0x00003000; //priority + + if(GenUartCont){ + DMA1_Channel4->CCR |=0x000000B0; //setup B > circular mode + }else{ + DMA1_Channel4->CCR |=0x00000090; //setup 9 > single mode + } + DMA1_Channel4->CCR |=0x00000001; //enable + + return; + + }else{ + + if(_Frqn>16)_Frqn=16; + DMA2_Channel4->CCR &= ~DMA_CCR1_EN; + WaveGen(); + ResetDMA2_Ch4Params(720/ScaleIndex[_Frqn]); + __Set(ANALOG_ARR, A_Tab[_Frqn]); + } + + if(PrevSweepIndex>=0){SweepIndex=PrevSweepIndex;PrevSweepIndex=-1;} + if(GenAdjustMode==0){GenFreqShift=0;PrevShift=0;} + + OutputAdjust(); + +} + + +void ResetDMA2_Ch4Params(u32 Count){ //This is an attempt to fix a *very* occasional loss of this DMA function while quickly + DMA2_Channel4->CPAR=DHR12R1_DAC; //shifting some gen menu functions by holding down repeat keys, requiring reboot. All relevant parms now reset + __Set(ANALOG_PTR, (u32)ATT_DATA); //DMA ch needs to be disabled before calling + __Set(ANALOG_CNT, Count); + DMA2_Channel4->CCR =0x00003000; //priority + DMA2_Channel4->CCR|=0x000005B0; //setup + DMA2_Channel4->CCR|=0x00000002; //turn transfer complete int on + DMA2_Channel4->CCR|=0x00000001; //enable + DMA2->IFCR|=0x00002000; //clear transfer complete int flag + TIM7->DIER=0x0100; //enable DMA call + TIM7->CR2 =0x0000; //system (V1.50-1.64, others?) sets bit 3 here for DMA call on update event, no such selection on basic timers +} //TIM 7 does not have capture compare mode, so DMA call is always on update event + + +void CalculateArbtTimer(void){ +u32 X; +u16 Y; + + X=72000000/(ArbtSampleNumber*A_Freq[_Frqn]); + if(X<10000){ + TIM7->PSC=0; + ARBT_ARR=X-1; + }else{ + Y=X/10000; + while((X%Y)!=0)Y++; // find an integral divider + if(Y>(X/Y)){ // if divider larger than divided, use as ARR so freq shift function can work correctly + TIM7->PSC=(X/Y)-1; + ARBT_ARR=(Y-1); + }else{ + TIM7->PSC=(Y-1); + ARBT_ARR=(X/Y)-1; + } + } + __Set(ANALOG_ARR,ARBT_ARR); +} + +/******************************************************************************* + Update_Trig: +*******************************************************************************/ +void Update_Trig(u8 service) +{ +u16 a; +u16 b; +u32 UTmp; + + AutoTrigIni=1; + TriggerType=_Tr_kind; + + a=((TempKp1*_T1)+512)/1024; //compensate for interpolated ranges + b=((TempKp1*_T2)+512)/1024; + if((OSBufferLogic())&&((FPGAsubVer==0)||(FPGAosFlag==0))){if(_T_base<16) {a*=8;b*=8;}else{a*=6;b*=6;}} + + if(_Tr_kind==8){ + if((Sweep)&&(_Kind<5)){ + UTmp=((1000/((TIM2Speed[SweepIndex]*SweepStep*5)/SweepMod))*750)/TimeBase[_T_base]; //calculate optimum period to trigger on + if(UTmp>200)UTmp=200; + if((OSBufferLogic())&&((FPGAsubVer==0)||(FPGAosFlag==0))){if(_T_base<16)UTmp*=8;else UTmp*=6;} + SetTthreshold(UTmp); + + if(service){ + if(Title[TRIGG][SOURCE].Value == TRACK1){ + if(_Vt1>_1_posi)TriggerType=5;else TriggerType=7; + } + if(Title[TRIGG][SOURCE].Value == TRACK2){ + if(_Vt2>_2_posi)TriggerType=5;else TriggerType=7; + } + }else{ + if(TrigSourceEnable == TRACK1){ + if(_Vt1>_1_posi)TriggerType=5;else TriggerType=7; + } + if(TrigSourceEnable == TRACK2){ + if(_Vt2>_2_posi)TriggerType=5;else TriggerType=7; + } + } + + if((_Kind==PWM)&&((Sweep>1)||(Det==0)))TriggerType=5; + + }else{ + TriggerType=3; //trigger on positive transition of continuous wave + } + + }else{ + + if(_T1 > _T2) SetTthreshold(a-b); + else SetTthreshold(b-a); + + } + + if((InvertA)&&((Title[TRIGG][SOURCE].Value==0)||((Title[TRIGG][SOURCE].Value==4)&&(TrigSourceEnable==0)))){ + a=((((-(_Vt1+Ka1[_A_Range]-_1_posi))*1024)/Ka2[_A_Range])&0xFF)+ADCoffset+_1_posi; + }else{ + a=((((_Vt1-Ka1[_A_Range]-_1_posi)*1024)/Ka2[_A_Range])&0xFF)+ADCoffset+_1_posi; + } + + if((InvertB)&&((Title[TRIGG][SOURCE].Value==1)||((Title[TRIGG][SOURCE].Value==4)&&(TrigSourceEnable==1)))){ + b=((((-(_Vt2+Kb1[_B_Range]-_2_posi))*1024)/Kb2[_B_Range])&0xFF)+ADCoffset+_2_posi; + }else{ + b=((((_Vt2-Kb1[_B_Range]-_2_posi)*1024)/Kb2[_B_Range])&0xFF)+ADCoffset+_2_posi; + } + + UpdateTLevels(); + + if(TriggerType>7)TriggerType=3; + +if(FPGAver==0){ //do not use with revised FPGA + if((_T_base>18)||(OSBufferLogic())){ //use time based triggering for OS and fastest timebases rather than edge or level trig + if((TriggerType==0)||(TriggerType==2)){ //more reliable for random, occasional triggers or noisy OS waveforms + TriggerType=7; //triggers if time exceeds threshold + SetTthreshold(0); //setting time to exceed at 0 turns these into an edge or level trigger + + } + if((TriggerType==1)||(TriggerType==3)){ + TriggerType=5; + SetTthreshold(0); //setting time to exceed at 0 turns these into an edge or level trigger + } + } +} + + + if(((Title[TRIGG][SOURCE].Value==0)&&(InvertA))||((Title[TRIGG][SOURCE].Value==1)&&(InvertB))|| + ((Title[TRIGG][SOURCE].Value==4)&&(((TrigSourceEnable==0)&&(InvertA))||((TrigSourceEnable==1)&&(InvertB))))) + TriggerType=InvTrig[TriggerType]; + + if(service){ //in regular trigger modes + + if( (((PrevSource!=_Tr_source)||(PrevKind!=TriggerType)))||(!OSBufferLogic())||(service==2))//does not reset trig mode in OS mode except when changing + __Set(TRIGG_MODE,(_Tr_source<< 3)+TriggerType); + PrevSource=_Tr_source; PrevKind=TriggerType; + + if(Title[TRIGG][SOURCE].Value == TRACK1){ + __Set(V_THRESHOLD,a); + } + if(Title[TRIGG][SOURCE].Value == TRACK2){ + __Set(V_THRESHOLD,b); + } + if((OSBufferLogic())&&((FPGAsubVer==0)||(FPGAosFlag==0))){ + if(_T_base<16) UTmp=(1208-(_X_posi.Value*8))+(StartOffset*8); + else UTmp=(908-(_X_posi.Value*6))+(StartOffset*6); + __Set_Param(8,(UTmp&0xFF)); //stabilize window position and shift trigger point to match xpos rather + __Set_Param(9,((UTmp>>8)&0xFF)); //than shifting window to keep buffer size at 512 (X8= 4096) + } + }else{ //in A&B trigger mode + __Set(TRIGG_MODE, (TrigSourceEnable<< 3)+TriggerType); //TRIGG_MODE = + if(TrigSourceEnable == TRACK1){ + __Set(V_THRESHOLD,a); + } + if(TrigSourceEnable == TRACK2){ + __Set(V_THRESHOLD,b); + } + } + if((Current==7)&&(_Det==2)&&(_Mode!=X_Y)&&(_4_source!=SPEC_A) + &&(_4_source!=SPEC_B)&&(ListOverride)){ + ConfNameTimer=110; + ToggleName=1; + Update_Mark(); + } +} + +void UpdateTLevels(void){ + Ch1TLevel=(((_Vt1-Ka1[_A_Range]-_1_posi)*1024)/Ka2[_A_Range])+_1_posi; + Ch2TLevel=(((_Vt2-Kb1[_B_Range]-_2_posi)*1024)/Kb2[_B_Range])+_2_posi; +} + +/******************************************************************************* + Process: Calculate processing buffer data +*******************************************************************************/ +void Process(void) +{ + s16 i, j = 0, k, V[8] = {0},a,b, n = 0,OsA=0,OsB=0,OsA_=0,OsB_=0; + s16 IValueA, IValueB, IVT1, IVT2; + s32 Tmp=0; + u8 Ch[4], C_D=0; + s8 Sa = 2, Sb = 2, Sc = 2, Sd = 2; // time status + u16 Ta, Tb, Tc, Td; // pulse width count + u16 Pa, Pb, Pc, Pd; // holds + side transition of wave for PaS + u8 jj; + s16 h; + s16 start,Tstart; //for cursor defined meters + u16 finish,Tstop; + s8 Shift=0; //jitter compensation value + u8 TriggerPosition=150; + u8 DTriggerPosition=150; + u8 TimeCalcHyst=2; //time based calculations trigger point hysteresis value + s16 AWavCenter; + s16 BWavCenter; + s32 X=0,Y=0; + u16 LeftSkirt=0; + + Waste=DataBuf[4095]&0x0000000F; + + if(UartLogic()||i2cLogic()||SpiLogic())SerialStatus=1;else SerialStatus=0; + Ta = Tb = Tc = Td = 0; + Pa = Pb = Pc = Pd = 0; + + TaS = 0; TbS = 0; TcS = 0; TdS = 0; + PaS = 0; PbS = 0; PcS = 0; PdS = 0; + TaN = 0; + TbN = 0; TcN = 0; TdN = 0; + + Posi_412 = _4_posi - _1_posi - _2_posi; + Posi_41_2 = _4_posi - _1_posi + _2_posi; + Posi_41 = _4_posi - _1_posi; + Posi_42 = _4_posi - _2_posi; + Posi_4_2 = _4_posi + _2_posi; + Posi_4F1 = _4_posi - FileBuff[ 397]; + Posi_4F2 = _4_posi - FileBuff[ 797]; + Posi_4F3 = _4_posi - FileBuff[ 1197]; + Posi_4F4 = _4_posi - FileBuff[1597]; + + A_Posi = _1_posi-Ka1[_A_Range]; + B_Posi = _2_posi-Kb1[_B_Range]; + + a_Max=-0x7FFF;a_Min=0x7FFF; //in case max is negative or min is positive (as with DC voltages) + b_Max=-0x7FFF;b_Min=0x7FFF; //originally would initiate @i=0 but with init @i=4 could transfer in slow mode before init + + aT_Max = A_Posi; bT_Max = B_Posi; // Used for calculating auto trigger + aT_Min = A_Posi; bT_Min = B_Posi; + + if((_3_posi + 20)>= Y_BASE+Y_SIZE) c_Max = Y_BASE+Y_SIZE-1; + else c_Max = _3_posi + 20; + if((_4_posi + 20)>= Y_BASE+Y_SIZE) d_Max = Y_BASE+Y_SIZE-1; + else d_Max = _4_posi + 20; + + if((ChartLogic())&&(FrameMode==0)&&(ScrollFlag>0)){ + if((JumpCnt>(380+_X_posi.Value))){_X_posi.Value=(JumpCnt-380);if((Current!=FILE)&&(NotificationTimer==0)) + Update_View_Area();ScrollFlag=1;} + if((ScrollFlag==1)&&(JumpCnt<=380)){_X_posi.Value=0;if(Current!=FILE)Update_View_Area();} + XposRef=GetXposRef(_X_posi.Value); + } + + if((OsBufferLogicFlag)&&(FPGAosFlag==0)){ + Xtend=119; //provides 512 samples for FFT + }else{ + if ((((_Mode==NORH)||(_Mode==NORHLD)||(_Mode==NORC))&&(!OsBufferLogicFlag)&&(_T_base < 10)&&(Options&1))||(_4_source>9)){ + Xtend=150; //stabilize buffer size in holdoff mode to cover pre-trigger section + }else{ //optimize size for best aquisition + Xtend=_X_posi.Value; + if (FlagMeter>0) Xtend-=86; + } + if(_4_source>9)Xtend+=56; else if(Det)Xtend+=20; //cover right end of FFT buffer or averaging filter in detector mode + } + + if(TriggerModeLogic())TriggerPosition=149;else TriggerPosition=150; //time based triggers occur 1 sample earlier + + switch (_T_base){ //digital ch trig positions for interpolated ranges + case 17: + DTriggerPosition=149; + break; + case 18: + DTriggerPosition=148; + break; + case 19: + if(TriggerModeLogic())DTriggerPosition=147;else DTriggerPosition=148; + break; + case 20: + if(TriggerModeLogic())DTriggerPosition=146;else DTriggerPosition=147; + break; + case 21: + if(TriggerModeLogic())DTriggerPosition=145;else DTriggerPosition=146; + } + + if(_Status==RUN)TempKp1=_Kp1; // eliminates improper change of wave timebase by Kp1 while in hold mode at faster timebases + if((OsBufferLogicFlag)&&((FPGAsubVer==0)||(FPGAosFlag==0))){ + k=StartOffset; + WindowPosition=0; + }else{ + k =((1024 - TempKp1)*TriggerPosition + 512)/1024 + _X_posi.Value; // window position in the calculation of the interpolation of the correction value + WindowPosition=_X_posi.Value; + Tmp=1792/Int_sqrt(TempKp1); + if(WindowPosition>Tmp)WindowPosition-=Tmp; else // shift window back to center FFT over display + WindowPosition=0; + if(WindowPosition>3582)WindowPosition=3582; // FFT window is 512, need to keep from going past last samples + if((OsBufferLogicFlag)&&(FPGAsubVer)&&(FPGAosFlag))Xtend+=WindowPosition; + } + + + + if(AutoSetFlag){ //autoset uses cursor defined function to filter out transients + if(AutoSequence==0){ + Tstart=200; + Tstop=get_bag_max_buf()-45; + }else{ + Tstart=160; + Tstop=get_bag_max_buf()-20; + } + }else{ + Tstart=Title[T_VERNIE][0].Value; + Tstop=Title[T_VERNIE][1].Value; + } + + start=(((((TempKp1*1000)/1024)*Tstart)+500)/1000)+k-((1024/TempKp1)/4); //calculate start/stop positions for + if((_T_base==20)&&(Title[7][0].Value<2))start--; //cursor defined meters + if(_T_base==19)start--; + if((_T_base==18)&&(Title[7][1].Value>3))start--; + finish=(((((TempKp1*1000)/1024)*Tstop)+500)/1000)+k; + + if ((Title[TRIGG][SOURCE].Value>1)&&(Title[TRIGG][SOURCE].Value<4)){start+=5;finish+=5;} // adjust to align with shifted wave when triggering from dig ch + + if(_Mode==X_Y){if(Title[6][3].Value<16)Title[6][3].Value=16;BufferSize=Title[6][3].Value*16;} + bag_max_buf = get_bag_max_buf(); + + if(AutoSetFlag==0){ + if(Title[T_VERNIE][T1].Value==0)start=0; // lock out time cursors from restricting measurements if + if(FlagMeter){ // at extreme right or left in cursor defined meter mode + if(Title[T_VERNIE][T2].Value>=300)finish=bag_max_buf; + }else{ + if(Title[T_VERNIE][T2].Value==386)finish=bag_max_buf; + } + } + + if (CurDefTime==0){ + NSamples=(bag_max_buf-4); //count starts @ i=4 to eliminate noise on some ranges + a_Avg=NSamples/2; + b_Avg=NSamples/2; + }else{ + if (finish>start){ + NSamples=(finish-start); + if (NSamples>1){ + NSamples--; + a_Avg=NSamples/2; + b_Avg=NSamples/2; + }else{ + a_Avg=A_Posi; + b_Avg=B_Posi; + } + }else{ + NSamples=1; + a_Avg=A_Posi; + b_Avg=B_Posi; + } + } + a_Ssq=b_Ssq=NSamples/2; + if((_4_source==15)||(_4_source==13))Normal=100; else Normal=80; //normalize FFT levels + + if ((exitflag==1)&&(JumpCnt!=0)) exitflag=0; // leave exitflag on at beginning of frame so if complete frame is done, allow freerun + + for(i=0; i 10)|| ( (_T_base>9)&& ( (FrameMode>0)||((FrameMode==0)&&(_Mode==NORHLD)) ) + &&(Current==FILE)&&(_Det==DIR)&&(Title[9][0].Value==1)&& (!ListLogic()) ) + ||((_T_base>9)&&(FrameMode==0)&& (((_Kind==5)&&(_Frqn>11))||(ShowFFT==1)))) || (freerun==1) + || ( (_T_base>9)&&( (Tim2Factor>20)||(((FrameMode==0)&& (SerialStatus))||(SpiLogic())) ) ) + || ( ( (_Mode==X_Y)||((SpiLogic())&&(FrameMode==0)&&(SpiChartFlag)&&((_3_source) + || (SpiNumBits==7)||(SpiNumBits==8)) &&(ArrayIndex>47))) && (_T_base>8) )) && (_Status == RUN) ){ + + Tmp=Update; //compiler optimizations: need to do something significant with Tmp or it dismisses the the while loops + if((FrameMode==0)&&(_T_base==10)&&(((_Kind==5)&&(_Frqn>11))||(ShowFFT==1)||(Tim2Factor>20))){ + while(1){if(Tmp++>(Waste+150))break;} //Proper timing for 500uS timebase in full buffer mode under various conditions + Waste=Tmp; + if((_Mode==NORHLD)&&((_Kind==5)&&(_Frqn>15)))while(1){if(Tmp++>100)break;} + } + Tmp=0; + if((FrameMode==0)&&(_T_base==11)&&(Sweep)&&(SweepIndex<6))while(1){if(Tmp++>25)break;} //timing for 200uS timebase + Waste=Tmp; + + if((FrameMode>0)&&(_T_base==10)&&(Current==FILE)&&(_Det==DIR)&&(Title[9][0].Value==1)&& (!ListLogic()) ){ + Tmp=Update; + if(_Mode==NORHLD){ + while(1){if(Tmp++>2600)break;} + }else{ + while(1){if(Tmp++>900)break;} + } + Waste=Tmp; + } + + if( (_Mode==NORHLD)&&(FrameMode==0)&&(_T_base==10)&&(Current==FILE)&&(_Det==DIR)&&(Title[9][0].Value==1)&& (!ListLogic()) ){ + Tmp=Update; + while(1){if(Tmp++>100)break;} + Waste=Tmp; + } + + if(Title[TRIGG][SOURCE].Value==4) TransferFIFO(i,1); else TransferFIFO(i,0); + FastMode=1; + + }else if( (__Get(FIFO_EMPTY)==0) &&(i == JumpCnt)&&(_Status == RUN)){ + if(Title[TRIGG][SOURCE].Value==4) TransferFIFO(i,1); else TransferFIFO(i,0); + if( ((!OsBufferLogicFlag)&&(!ChartLogic())) ||(OsTransferCompleteFlag)){ + OsTransferCompleteFlag=0; + JumpCnt++; + } + FastMode=0; + } + + V[A]=(DataBuf[i]&0xFF)-ADCoffset; + if(V[A]>=0)Ch[A]=V[A];else Ch[A]=0; + if(V[A]<-15)V[A]=-15; + + V[B]=((DataBuf[i]>>8)&0xFF)-ADCoffset; + if(V[B]>=0)Ch[B]=V[B];else Ch[B]=0; + if(V[B]<-15)V[B]=-15; + + IValueA=V[A]; + IValueB=V[B]; + + if(OsBufferLogicFlag||OsChartFlag){ + if((OSAvg)&&(!OsChartFlag)){ + V[A]=OsFFTData[0][i]-ADCoffset; + OsA=V[A]; + V[B]=OsFFTData[1][i]-ADCoffset; + OsB=V[B]; + }else{ + OsA=(((DataBuf[i]>>16)&0xFF)-ADCoffset); //accumulated minimum, maximum is already in V[x} + OsB=(((DataBuf[i]>>24)&0xFF)-ADCoffset); + } + + if((RMSdata[0][i]-ADCoffset)>=0)Ch[A]=(RMSdata[0][i]-ADCoffset);else Ch[A]=0; //2 lines take the place of commented above + if((RMSdata[1][i]-ADCoffset)>=0)Ch[B]=(RMSdata[1][i]-ADCoffset);else Ch[B]=0; + + if(OsA<-15)OsA=-15; + if(OsB<-15)OsB=-15; + } + + if(InvertA){ + V[A]-=A_Posi; + V[A]=-V[A]; + V[A]+=A_Posi; + if(OsBufferLogicFlag||OsChartFlag){ + if((OSAvg)&&(!OsChartFlag)){ + OsA=V[A]; + }else{ + OsA-=A_Posi; + OsA=-OsA; + OsA+=A_Posi; + Tmp=OsA; + OsA=V[A]; + V[A]=Tmp; + } + + Ch[A]-=A_Posi; + Ch[A]=-Ch[A]; //<< would be ok here << could use this for both averaging and OS modes...(?) + Ch[A]+=A_Posi; //takes the place of commented lines above + + if(OsA<-15)OsA=-15; + }else{ + if(V[A]>=0)Ch[A]=V[A];else Ch[A]=0; + } + if(V[A]<-15)V[A]=-15; + } + + if(InvertB){ + V[B]-=B_Posi; + V[B]=-V[B]; + V[B]+=B_Posi; + if(OsBufferLogicFlag||OsChartFlag){ + if((OSAvg)&&(!OsChartFlag)){ + OsB=V[B]; + }else{ + OsB-=B_Posi; + OsB=-OsB; + OsB+=B_Posi; + Tmp=OsB; + OsB=V[B]; + V[B]=Tmp; + } + + Ch[B]-=B_Posi; //as for ch A + Ch[B]=-Ch[B]; + Ch[B]+=B_Posi; + + if(OsB<-15)OsB=-15; + }else{ + if(V[B]>=0)Ch[B]=V[B];else Ch[B]=0; + } + if(V[B]<-15)V[B]=-15; + } + + if(OsA>255)OsA=255; + if(OsB>255)OsB=255; + if(V[A]>255)V[A]=255; + if(V[B]>255)V[B]=255; + + if(OsBufferLogicFlag){ + if(i == 4) { // used for auto trigger and time measurements in OS modes + aT_Max = Ch[A]; // statistics channel A maximum + bT_Max = Ch[B]; // statistics channel B maximum + aT_Min = aT_Max; // statistics channel A minimum + bT_Min = bT_Max; // statistics channel B minimum + }else{ // not the first values + if(Ch[A] > aT_Max) aT_Max = Ch[A]; // statistics channel A maximum + if(Ch[B] > bT_Max) bT_Max = Ch[B]; // statistics channel B maximum + if(Ch[A] < aT_Min) aT_Min = Ch[A]; // statistics channel A minimum + if(Ch[B] < bT_Min) bT_Min = Ch[B]; // statistics channel B minimum + } + }else{ + if(i == 4) { // used for auto trigger + aT_Max = V[A]; // statistics channel A maximum + bT_Max = V[B]; // statistics channel B maximum + aT_Min = aT_Max; // statistics channel A minimum + bT_Min = bT_Max; // statistics channel B minimum + }else{ // not the first values + if(V[A] > aT_Max) aT_Max = V[A]; // statistics channel A maximum + if(V[B] > bT_Max) bT_Max = V[B]; // statistics channel B maximum + if(V[A] < aT_Min) aT_Min = V[A]; // statistics channel A minimum + if(V[B] < bT_Min) bT_Min = V[B]; // statistics channel B minimum + } + } + + // FFT /////////////////////////////////////// + + + if((_4_source>10)&&(i>=WindowPosition)&&(i < (FFTSize+WindowPosition))&&(_Mode!=X_Y)&& ((EnableFFT==0)||(_T_base>7)||(_Mode==SCAN)||(_State.Value==2)) ){ + + if (((_4_source==SPEC_A)&&(_2_source))||(_4_source==13)||(_4_source==12)){ + if(OsBufferLogicFlag){ + Tmp=OsFFTData[1][i-WindowPosition]-ADCoffset; + if(Tmp<-15)Tmp=-15; + fr[i-WindowPosition]=(((Tmp-_2_posi)*Window[i-WindowPosition])/Normal)<<(2+FFTGain); + }else{ + fr[i-WindowPosition]=(((V[B]-_2_posi)*Window[i-WindowPosition])/Normal)<<(2+FFTGain); + } + } + + if (((_4_source==SPEC_A)&&(_1_source))||(_4_source>13) ){ + if(OsBufferLogicFlag){ + Tmp=OsFFTData[0][i-WindowPosition]-ADCoffset; + if(Tmp<-15)Tmp=-15; + fr[i-WindowPosition]=(((Tmp-_1_posi)*Window[i-WindowPosition])/Normal)<<(2+FFTGain); + }else{ + fr[i-WindowPosition]=(((V[A]-_1_posi)*Window[i-WindowPosition])/Normal)<<(2+FFTGain); + } + } + + } + + ////////////////////////////////////// FFT /// + + if(!OsBufferLogicFlag){if (i>5) {C_D = DataBuf[i-6] >>16;}else C_D=0;} // align digital chs with analogs + +//if(FlagMeter>0){ //could be used to speed up display refresh rate when meters are turned off? + if (((CurDefTime==0)&&(i>3)&&(istart)&&(i0)&&(i==(start+1)))) { // read first values - max = min = values + a_Max = V[A]; // statistics channel A maximum + b_Max = V[B]; // statistics channel B maximum + a_Min = a_Max; // statistics channel A minimum + b_Min = b_Max; // statistics channel B minimum + }else{ // not the first values + if(V[A] > a_Max) a_Max = V[A]; // statistics channel A maximum + if(V[B] > b_Max) b_Max = V[B]; // statistics channel B maximum + if(OsBufferLogicFlag){ + if(OsA < a_Min) a_Min = OsA; // statistics channel A minimum + if(OsB < b_Min) b_Min = OsB; // statistics channel A minimum + }else{ + if(V[A] < a_Min) a_Min = V[A]; // statistics channel A minimum + if(V[B] < b_Min) b_Min = V[B]; // statistics channel B minimum + } + } + } + + if((CurDefTime==0)||((i>start-1)&&(i<(finish+1)))){ //for time related measurements for both dig and analog channels + + if((i>3)&&(i<(bag_max_buf-3))){ + + if((CurDefTime==0)||(i a_Mid_H){ + if (Sa<2){ //don't initiate if value is above trigger point when starting out + if(Sa == 0){ + TaS = i; + LastA_Mid=a_Mid_H; //save relevant time meter trigger level for quantization compensation + if(Ta==0){ //use Ta to initiate + Ta=i; //first + crossing point saved + QStart[0]=i; //start position saved for quantization calcs + FirstA_Mid=a_Mid_H; + }else{ //after initialized, count + crossings, add + wave sampling count to PaS + TaN++; //increment TaN only after initial crossing point saved + PaS += Pa; //only add positive part if whole wave is considered + } + } + Sa = 1; + } + } else { + if(Ch[A] < a_Mid_L){ + if(Sa == 2){ + Sa=0; //initiate only after going below trigger point so partial wave does not get counted + PaS=0; //initiate PaS + } + if(Sa == 1){ + Sa = 0; + Pa = i-TaS; //save for PaS + } + } + } + + if(Ch[B] > b_Mid_H){ + if (Sb<2){ + if(Sb == 0){ + TbS = i; + LastB_Mid=b_Mid_H; //save relevant time meter trigger level for quantization compensation + if(Tb==0){ + Tb=i; + QStart[1]=i; //start position saved for quantization calcs + FirstB_Mid=b_Mid_H; + }else{ + TbN++; + PbS += Pb; + } + } + Sb = 1; + } + } else { + if(Ch[B] < b_Mid_L){ + if(Sb == 2){ + Sb=0; + PbS=0; + } + if(Sb == 1){ + Sb = 0; + Pb = i-TbS; + } + } + } + } + + if((i>10)&&((CurDefTime==0)||(i>start))){ //eliminate noise at start of wave causing errors in dig channels + + if(C_D & 1){ + if (Sc<2){ + if(Sc == 0){ + TcS = i; + if(Tc==0){ + Tc=i; + }else{ + TcN++; + PcS += Pc; + } + } + Sc = 1; + } + } else { + if(Sc == 2){ + Sc=0; + PcS=0; + } + if(Sc == 1){ + Sc = 0; + Pc = i-TcS; + } + } + + if(C_D & 2){ + if (Sd<2){ + if(Sd == 0){ + TdS = i; + if(Td==0){ + Td=i; + }else{ + TdN++; + PdS += Pd; + } + } + Sd = 1; + } + } else { + if(Sd == 2){ + Sd=0; + PdS=0; + } + if(Sd == 1){ + Sd = 0; + Pd = i-TdS; + } + } + + } //if i>8 + } //if i>3 + } //if curdeftime +//} //if flagmeter>0 + + if((JComp)&&(!OsBufferLogicFlag)){ + if((i==TriggerPosition)&&(_T_base > 16)&&(_Mode!=SCAN)&&(__Get(FIFO_START)!=0)){ //analog channels + if(InvertA)IVT1=((-(_Vt1-_1_posi))+_1_posi);else IVT1=_Vt1; + if(InvertB)IVT2=((-(_Vt2-_2_posi))+_2_posi);else IVT2=_Vt2; + if((Title[7][1].Value==1)||(Title[7][1].Value==3)||(Title[7][1].Value==4)||(Title[7][1].Value==5)){ //positive transitions + if ((Title[7][0].Value==0)||((Title[TRIGG][SOURCE].Value==4)&&(TrigSourceEnable==0))){ //select trigger channel + b=(Ka1[_A_Range]+A_Posi+(Ka2[_A_Range]*(IValueA-A_Posi)+ 512)/1024)-IVT1; + a=IVT1-(Ka1[_A_Range]+A_Posi+(Ka2[_A_Range]*(((DataBuf[TriggerPosition-1]& 0xFF)-ADCoffset)-A_Posi)+ 512)/1024); + }else if((Title[7][0].Value==1)||((Title[TRIGG][SOURCE].Value==4)&&(TrigSourceEnable==1))){ + b=(Kb1[_B_Range]+B_Posi+(Kb2[_B_Range]*(IValueB-B_Posi)+ 512)/1024)-IVT2; + a=IVT2-(Kb1[_B_Range]+B_Posi+(Kb2[_B_Range]*((((DataBuf[TriggerPosition-1]>>8)&0xFF)-ADCoffset)-B_Posi)+ 512)/1024); + }else goto bypasscalculate; + }else{ //negative transitions + if ((Title[7][0].Value==0)||((Title[TRIGG][SOURCE].Value==4)&&(TrigSourceEnable==0))){ + b=IVT1-(Ka1[_A_Range]+A_Posi+(Ka2[_A_Range]*(IValueA-A_Posi)+ 512)/1024); + a=(Ka1[_A_Range]+A_Posi+(Ka2[_A_Range]*(((DataBuf[TriggerPosition-1]& 0xFF)-ADCoffset)-A_Posi)+ 512)/1024)-IVT1; + }else if((Title[7][0].Value==1)||((Title[TRIGG][SOURCE].Value==4)&&(TrigSourceEnable==1))){ + b=IVT2-(Kb1[_B_Range]+B_Posi+(Kb2[_B_Range]*(IValueB-B_Posi)+ 512)/1024); + a=(Kb1[_B_Range]+B_Posi+(Kb2[_B_Range]*((((DataBuf[TriggerPosition-1]>>8)&0xFF)-ADCoffset)-B_Posi)+ 512)/1024)-IVT2; + }else goto bypasscalculate; + } + Shift=-((((b*102400)/((a+b)*TempKp1))+50)/100); //calculate jitter from analog channels + } + +bypasscalculate: //digital channels + + if ((i==155)&&(_T_base > 16)&&(_Mode!=SCAN)&&(__Get(FIFO_START)!=0)){ //calculate jitter position if trig from dig channels + if((Title[7][1].Value==1)||(Title[7][1].Value==3)||(Title[7][1].Value==4)||(Title[7][1].Value==5)){ //positive transitions + if (Title[7][0].Value==2){ + for (jj=DTriggerPosition;jj<155;jj++){ + if (((DataBuf[jj]>>16)&1)==1){Shift=((jj-DTriggerPosition)*1024)/TempKp1;break;} + } + }else if(Title[7][0].Value==3){ + for (jj=DTriggerPosition;jj<155;jj++){ + if (((DataBuf[jj]>>16)&2)==2){Shift=((jj-DTriggerPosition)*1024)/TempKp1;break;} + } + } + }else{ //negative transitions + if (Title[7][0].Value==2){ + for (jj=DTriggerPosition;jj<155;jj++){ + if (((DataBuf[jj]>>16)&1)==0){Shift=((jj-DTriggerPosition)*1024)/TempKp1;break;} + } + }else if(Title[7][0].Value==3){ + for (jj=DTriggerPosition;jj<155;jj++){ + if (((DataBuf[jj]>>16)&2)==0){Shift=((jj-DTriggerPosition)*1024)/TempKp1;break;} + } + } + } + } + } + + if(i >= k){ // pointer to reach the specified window position + // Use V[x] loaded above rather than unsigned Ch[x], prevents clipping. + + if (CalFlag>0) { + + Tmp=Ka2[_A_Range]*(V[A]-A_Posi) ; // Factor in gain correction for signal (Ka2) from signal zero point + if (Tmp>0)Tmp+=512; else Tmp-=512; // Flip bias if negative, allows proper compensation of negative values + V[A] = Ka1[_A_Range]+A_Posi+(Tmp/1024); + Tmp=Kb2[_B_Range]*(V[B]-B_Posi); + if (Tmp>0)Tmp+=512; else Tmp-=512; + V[B] = Kb1[_B_Range]+B_Posi+(Tmp/1024); + + if(OsBufferLogicFlag||OsChartFlag){ // adjust oversampling data + Tmp=Ka2[_A_Range]*(OsA-A_Posi) ; // Factor in gain correction for signal (Ka2) from signal zero point + if (Tmp>0)Tmp+=512; else Tmp-=512; // Flip bias if negative, allows proper compensation of negative values + OsA = Ka1[_A_Range]+A_Posi+(Tmp/1024); + Tmp=Kb2[_B_Range]*(OsB-B_Posi); + if (Tmp>0)Tmp+=512; else Tmp-=512; + OsB = Kb1[_B_Range]+B_Posi+(Tmp/1024); + } + + }else{ + V[A] = Ka1[_A_Range]+V[A]; // gain correction switched off + V[B] = Kb1[_B_Range]+V[B]; + if(OsBufferLogicFlag||OsChartFlag){ + OsA+=Ka1[_A_Range]; + OsB+=Kb1[_B_Range]; + } + } + if(OsA<0)OsA=0; + if(OsB<0)OsB=0; + + if((Title[TRACK1][COUPLE].Value==2)&&(_1_source)){ //filter=40 + if(i>=(Filter+28)){ + X=0; + for(h=(i-Filter);h198)Y=198; + Y=(Y*(100+((198-Y)/2)))/100; + V[A]=Y; + }else V[A]=0; + } + + if((Title[TRACK2][COUPLE].Value==2)&&(_2_source)){ + if(i>=(Filter+28)){ + X=0; + for(h=(i-Filter);h> 8) & 0xFF)-ADCoffset; + if(Tmp<0)Tmp=0; + Tmp=Tmp+Kb1[_B_Range]-_2_posi; + Tmp=(Kb2[_B_Range]*Tmp)/1024; + if(Tmp<0)Tmp=-Tmp; + if(_Kind==4){ + Tmp=((Tmp*225)+50)/100; + }else{ + Tmp=((Tmp*280)+50)/100; + } + X+=(Tmp*Tmp); + } + Y=(Int_sqrt(X/Filter)); + if(Y>198)Y=198; + Y=(Y*(100+((198-Y)/2)))/100; + V[B]=Y; + }else V[B]=0; + } + + while(j > 0 ){ + if ((Options&2)&&(_T_base<17)){ // prevent interpolate routine from interfering with non-interpolated time bases + if(OsBufferLogicFlag||OsChartFlag){ + Send_Data( V[A],V[B],OsA,OsB,n++); // send oversampling data over digital channels + }else{ + Send_Data( V[A_],V[B_],C_D,0,n++); + } + }else{ + + if((_T_base<20)&&(OsBufferLogicFlag)&&(FPGAsubVer)&&(FPGAosFlag)){ + Send_Data( V[A_]+((V[A]-V[A_])*(1024 - j))/1024, // the current CH_A point interpolation + V[B_]+((V[B]-V[B_])*(1024 - j))/1024, // the current CH_B point interpolation + OsA_+((OsA-OsA_)*(1024 - j))/1024, + OsB_+((OsB-OsB_)*(1024 - j))/1024, + n++); + }else{ + Send_Data( V[A_]+((V[A]-V[A_])*(1024 - j))/1024, // the current CH_A point interpolation + V[B_]+((V[B]-V[B_])*(1024 - j))/1024, // the current CH_B point interpolation + C_D,0, // current point digital channel values + n++); + } + + } + j -= TempKp1; + if(n >= X_SIZE){ k = 8192; break;} + } + + j += 1024; + V[A_] = V[A]; V[B_] = V[B]; + OsA_=OsA; OsB_=OsB; + } + + } // end of for loop + + if ((exitflag==1)&&(JumpCnt<(393+Xtend))) exitflag=0; //if exitflag was on at start, full frame finished allows freerun + + if ((FrameMode!=0) && (_T_base>11) && (_Mode==SCAN)) __Set(FIFO_CLR, W_PTR); + + if(Options&4){ //alarms + if(_Mode!=X_Y){ + + if(Title[V_VERNIE][V1].Value<200){ //lock out if at extreme top + h=a_Max-A_Posi; + h = (((Ka2[_A_Range]*h)+512)/1024); + h=h+_1_posi; + if((h>Title[V_VERNIE][V1].Value)&&(Title[0][0].Value!=0)&&(Title[V_VERNIE][2].Value==0)) Beeper(500); + + h=b_Max-B_Posi; + h = (((Kb2[_B_Range]*h)+512)/1024); + h=h+_2_posi; + if((h>Title[V_VERNIE][V1].Value)&&(Title[1][0].Value!=0)&&(Title[V_VERNIE][2].Value==1))Beeper(500); + } + + if(Title[V_VERNIE][V2].Value>0){ //lock out if at extreme bottom + h=a_Min-A_Posi; + h = (((Ka2[_A_Range]*h)+512)/1024); + h=h+_1_posi; + if((h0)&&(AutoSetFlag==0)){ //allow V cursors to adjust time meters trigger level + h=AWavCenter; + Tmp=h; + h=(((Ka2[_A_Range]*(h-A_Posi))+512)/1024)+_1_posi; + if(Title[V_VERNIE][V1].ValueTitle[V_VERNIE][V1].Value){ + Tmp+=(((1024*(Title[V_VERNIE][V2].Value-h))+((512*Ka2[_A_Range])/1024))/Ka2[_A_Range]); + AWavCenter=Tmp; + } + }else if(Title[V_VERNIE][V2].Value>h){ + AWavCenter+=(((1024*(Title[V_VERNIE][V2].Value-h))+((512*Ka2[_A_Range])/1024))/Ka2[_A_Range]); + } + h=BWavCenter; + Tmp=h; + h=(((Kb2[_B_Range]*(h-B_Posi))+512)/1024)+_2_posi; + if(Title[V_VERNIE][V1].ValueTitle[V_VERNIE][V1].Value){ + Tmp+=(((1024*(Title[V_VERNIE][V2].Value-h))+((512*Kb2[_B_Range])/1024))/Kb2[_B_Range]); + BWavCenter=Tmp; + } + }else if(Title[V_VERNIE][V2].Value>h){ + BWavCenter+=(((1024*(Title[V_VERNIE][V2].Value-h))+((512*Kb2[_B_Range])/1024))/Kb2[_B_Range]); + } + } + a_Mid_H = TimeCalcHyst +AWavCenter; + a_Mid_L = a_Mid_H - (2*TimeCalcHyst); + b_Mid_H = TimeCalcHyst +BWavCenter; + b_Mid_L = b_Mid_H - (2*TimeCalcHyst); + + QEnd[0]=TaS; //ending sampling positions for quantization error correction + QEnd[1]=TbS; + + TaS -= Ta; TbS -= Tb; TcS -= Tc; TdS -= Td; + + if((_Status == RUN)&&(Options&4)&&(ClearHoldFlag>0)){ //clear hold if in fast mode (after first loop) + if((_T_base > 10)||((_T_base < 11)&&((JumpCnt==get_bag_max_buf())||(freerun==1)))){ //if in slow mode, wait for frame to be done + if(SlowModeSkip==0){ + if(Title[TRIGG][SOURCE].Value<4){ //if not in ab mode + ClearMinMax(ClearHoldFlag); + ClearHold(ClearHoldFlag); + ClearHoldFlag=0; + }else{ //in ab mode + if((TrigSourceEnable==0)&&(ClearHoldFlag&1)){ + ClearMinMax(1); + ClearHold(1); + ClearHoldFlag--; //removes bit 1 (tested as set) + } + if((TrigSourceEnable==1)&&(ClearHoldFlag&2)){ + ClearMinMax(2); + ClearHold(2); + ClearHoldFlag&=0xFD; //removes bit 2 + } + } + }else if(SlowModeSkip>0) SlowModeSkip--; + } + } + + if(JumpCnt==get_bag_max_buf())ClearLeadingEdge=0; // WAS 0 if turned on by clear screen, reset at end of frame + + if((SumResetFlag==1)&&((JumpCnt==get_bag_max_buf())||(freerun==1)||(_Status!= RUN)||((DownConvertMode)&&(FFTt1Mode)))){ //in slow mode wait for all necessary loops + EnablePaS=1; // to complete frame + if((DownConvertMode)&&(DownConvertInitiate==0))Display_Value(0); + ResetSum(); //sync sum resets between meter reads and completed frames + SumResetFlag=0; + } + + if (WaitForTrigFlag){ //meter reset flag for normal modes when not triggered so display retains values while waiting + EnablePaS=1; //while allowing consequent trigger to display values properly + ResetSum(); + WaitForTrigFlag=0; + } + + if(a_Max>Ga_Max)Ga_Max=a_Max; //update peak from all frames into Gx_Max,Min + if(b_Max>Gb_Max)Gb_Max=b_Max; + if(a_MinGHa_Max)GHa_Max=a_Max;else if(HoldResetFlag&1)GHa_Max=a_Max; //if max is negative, establish start point + if(b_Max>GHb_Max)GHb_Max=b_Max;else if(HoldResetFlag&2)GHb_Max=b_Max; + if(a_Min13)||((Title[TRIGG][SOURCE].Value==0)&&(EnableMeterCalc))){ + UTmp= (1000000000/TaS)*TaN; //Calculate frequency using data from last frame + UTmp-=QError(0,QStart[0],QEnd[0],UTmp); //Adjust for any possible quantization error compensation + Average(0); //Include all previous data transfers and average + } + if((_2_source != HIDE)||(_4_source==12)||(_4_source==13)||((Title[TRIGG][SOURCE].Value==1)&&(EnableMeterCalc))){ + UTmp= (1000000000/TbS)*TbN; + UTmp-=QError(1,QStart[1],QEnd[1],UTmp); + Average(1); + } + if(_3_source == CH_C){ + UTmp= (1000000000/TcS)*TcN; + Average(2); + } + if((_4_source == CH_D)||(_4_source == C_and_D)||(_4_source == C_or_D)){ + UTmp = (1000000000/TdS)*TdN; + Average(3); + } + + if ((Title[TRIGG][SOURCE].Value>1)&&(Title[TRIGG][SOURCE].Value<4)){ //if triggering from digital chs, alignment with analog chs shifts waveforms to the right, + for(h=0; h<=(X_SIZE-5); h++){ //shift back to original position + for(i=0;i<4;i++){ + TrackBuff[h*4+i] = TrackBuff[(h+5)*4+i]; + } + } + } + +if (_T_base > 16){ //jitter compensation for interpolated modes + + if(Title[TRIGG][SOURCE].Value==4){ //if in A&B trig mode + + if(TrigSourceEnable==0){ + + if (Shift<0){ + for(h=X_SIZE;h>=-Shift; h--){ + TrackBuff[h*4] = TrackBuff[(h+Shift)*4]; + } + } + if (OldShift<0){ + for(h=X_SIZE;h>=-OldShift; h--){ + TrackBuff[h*4+1] = TrackBuff[(h+OldShift)*4+1]; + } + } + + }else if(TrigSourceEnable==1){ + + if (Shift<0){ + for(h=X_SIZE;h>=-Shift; h--){ + TrackBuff[h*4+1] = TrackBuff[(h+Shift)*4+1]; + } + } + if (OldShift<0){ + for(h=X_SIZE;h>=-OldShift; h--){ + TrackBuff[h*4] = TrackBuff[(h+OldShift)*4]; + } + } + + } + + Tmp=Shift; + if(OldShift0){ + for(h=0; h<=(X_SIZE-Shift); h++){ + for(i=0;i<4;i++){ + TrackBuff[h*4+i] = TrackBuff[(h+Shift)*4+i]; + } + } + }else if (Shift<0){ + for(h=X_SIZE;h>=-Shift; h--){ + for(i=0;i<4;i++){ + TrackBuff[h*4+i] = TrackBuff[(h+Shift)*4+i]; + } + } + } + + } //else... + +} //if Tbase... + + + if(!(OsBufferLogicFlag)){ + + if (_T_base < 17){ //pre signal blanking + if (_T_base > 10){ + discard=4; + }else discard=1; + if((_T_base==10)&&(SerialStatus))discard=4; + }else if (Shift<0){ + discard=-Shift; + }else discard=0; + if (_Mode==SGL) discard=4; + if(OsChartFlag)discard=0; + + if (Shift>0)Rdiscard=Shift;else Rdiscard=0; //Shift is >0 when in highest time bases triggered from digital channel + if (_T_base>16)Rdiscard+=7;else Rdiscard=0; //and is compensated for interpolation + + for(jj=0; jj(X_SIZE-Rdiscard); h--){ //post signal blanking + for(i=0;i<4;i++){ + TrackBuff[h*4+i] = TrackBuff[(X_SIZE-Rdiscard)*4+i]; + } + } + + }else discard=0; + + + if(Det){ //center filter output on wave + for(h=0; h<(X_SIZE-(Filter/2)); h++){ + if((Det&1)&&(_1_source)){ + TrackBuff[h*4] = TrackBuff[(h+(Filter/2))*4]; + } + if((Det&2)&&(_2_source)){ + TrackBuff[h*4+1] = TrackBuff[(h+(Filter/2))*4+1]; + } + } + for(h=(X_SIZE-(Filter/2)); h(392+Xtend))||((_State.Value==2)&&(DownConvertMode==0))){ //to carry enableFFT set at end of DrawWindow with FrameEndFlag + EnableFFT=1; //"Short circuits" loop in case of fast fall through with 1 frame + ResetEnableFFT=1; //Disables set at end of DrawWindow + } + } + + + // FFT ///////////////////////////// + u8 treshold=6; + if(AutoFFT==0)treshold=75; //log mode, uses high gain + if((_4_source>10)&&(_Mode!=X_Y)&& ((EnableFFT==1)||(_T_base>7)||(__Get(FIFO_START)==0)||(_Mode==SCAN)) ){ + EnableFFT=2; + for(i=0; i3){ //was 5 3 now works with i>5 on leftskirt conditional and fr[1] cleared + if((fi[i-2]>=fi[i-3])&&(fi[i-2]>fi[i-1])&&(fi[i-2]>treshold)){ //detect peak (i= -2 =peak), threshold + fi[i-2]=Int_sqrt((fi[i-2]*fi[i-2])+(fi[i-3]*fi[i-3])+(fi[i-1]*fi[i-1])); //sum with neighbors + fi[i-3]=2+(fi[i-2]>>2); //suppress left skirt (was >>3 for hamming W) + LeftSkirt=i-3; //save it's position + } + if(((i-5)==LeftSkirt)&&(i>5)){fi[i-3]=fi[i-5];LeftSkirt=0;} //suppress right skirt of summed peak if next bin skipped + } + + if(i>7){ + fi[i-7]=Log10Process(i-7); //Processed bins in summing mode + } + + }else{ + fi[i]=Log10Process(i); //In Hann only mode + } + } + + if((_4_source==15)||(_4_source==13)){ + for(i=249;i<256;i++){ + fi[i]=Log10Process(i); //Rest of bins in summing mode + } + } + } + //////////////////////////// FFT /// + + if((_T_base<11)&&(JumpCnt>=get_bag_max_buf())){ + if(UpdateBackground==3)UpdateBackground=0; + else if(UpdateBackground>0){ + UpdateBackground++; + if(_T_base<5)UpdateBackground=3; + } + } + if(_T_base>10)FrameEndFlag=1; +} + + +void Send_Data(s16 Va, s16 Vb, u8 C_D, u8 osB, u16 n) // output display data +{ + s32 Tmp = 0, i; + u8 Start; + if((Title[TRIGG][SOURCE].Value>1)&&(Title[TRIGG][SOURCE].Value<4))Start=5;else Start=0; + + i = n*4; + + if(Va >= Y_BASE+Y_SIZE) TrackBuff[i + TRACK1] = Y_BASE+Y_SIZE-1; + else if(Va <= Y_BASE+1) TrackBuff[i + TRACK1] = Y_BASE+1; + else TrackBuff[i + TRACK1] = Va; + if(Vb >= Y_BASE+Y_SIZE) TrackBuff[i + TRACK2] = Y_BASE+Y_SIZE-1; + else if(Vb <= Y_BASE+1) TrackBuff[i + TRACK2] = Y_BASE+1; + else TrackBuff[i + TRACK2] = Vb; + + + if(OsBufferLogicFlag||OsChartFlag){ + + if(C_D>= Y_BASE+Y_SIZE) TrackBuff[i + TRACK3] = Y_BASE+Y_SIZE-1; + else if(C_D<= Y_BASE+1) TrackBuff[i + TRACK3] = Y_BASE+1; + else TrackBuff[i + TRACK3] = C_D; + if(osB>= Y_BASE+Y_SIZE) TrackBuff[i + TRACK4] = Y_BASE+Y_SIZE-1; + else if(osB<= Y_BASE+1) TrackBuff[i + TRACK4] = Y_BASE+1; + else TrackBuff[i + TRACK4] = osB; + + }else{ + + if(C_D & 1) TrackBuff[i + TRACK3] = c_Max; + else TrackBuff[i + TRACK3] = _3_posi; + + switch (_4_source){ + case A_add_B: + Tmp = Posi_412 + Va + Vb; + break; + case A_sub_B: + Tmp = Posi_41_2 + Va - Vb; + break; + case C_and_D: + if((~C_D)& 3) Tmp = _4_posi; + else Tmp = d_Max; + break; + case C_or_D: + if(C_D & 3) Tmp = d_Max; + else Tmp = _4_posi; + break; + + if(n>=Start){ + case REC_1: + Tmp = Posi_4F1 + FileBuff[n-Start]; + break; + case REC_2: + Tmp = Posi_4F2 + FileBuff[n+400-Start]; + break; + case REC_3: + Tmp = Posi_4F3 + FileBuff[n+800-Start]; + break; + case REC_4: + Tmp = Posi_4F4 + FileBuff[n+1200-Start]; + break; + } + + case (10)...(15): //fft functions + break; + default: + if(C_D & 2) Tmp = d_Max; + else Tmp = _4_posi; + } + if(Tmp >= Y_BASE+Y_SIZE) TrackBuff[i + TRACK4] = Y_BASE+Y_SIZE-1; + else if(Tmp <= Y_BASE+1) TrackBuff[i + TRACK4] = Y_BASE+1; + else TrackBuff[i + TRACK4] = Tmp; + + } + +} + +/******************************************************************************* + Synchro: scan synchronization, waveform display by setting the mode +*******************************************************************************/ +void Synchro(void) // scan synchronization: AUTO, NORM, SGL, NONE, SCAN modes +{ +static u8 FreeRunOffStatus=0; +u32 waste=0; +if((Update)&&(_Mode==NORHLD))UpdateCursorMeter(); + +if((OsBufferLogicFlag)&&(FPGAsubVer)&&(FPGAosFlag)){ //force FPGA freerun mode when using FPGA OS + if((FreeRunOffStatus==0)&&(FreeRunEnable==0))FreeRunOffStatus=1; //store non OS freerun enable status before engaging + FreeRunEnable=1; //Turn ON freerun in FPGA OS mode by default, stays on +}else if(FreeRunOffStatus){ //return to previous freerun status on exiting FPGA OS + FreeRunOffStatus=0; //reset memory + FreeRunEnable=0; //turn off if it was off before entering OS mode +} + +freerun=0; +if((__Get(FIFO_START)!=0)||(_Mode!=AUTO)||(FreeRunEnable==0)){ + __Set(32+14, 0); + JComp=1; //Set FPGA FreeRun off +} + + if(HoldOnNext==1) { + _State.Value = HOLD; // for single mode + _State.Flag |= UPDAT; + HoldOnNext=0; + return; + } + +if (BailoutFlag>0) {BailoutFlag=0; goto BailOut;} //if in trigger delay + +if (FrameMode>0) //single frame buffer + { + switch (_Mode) + { + case X_Y: + case AUTO: + if(!OsBufferLogicFlag)__Set(TRIGG_MODE,(_Tr_source <<3)+TriggerType); + if((__Get(FIFO_START)!=0)||(_State.Value==2)){ + if (entryflag>0){ + JumpCnt=0; + entryflag=0; + } + Process(); + JComp=1; + Wait_Cnt=shortwait[_T_base]; + exitflag=1; + }else if ((Wait_Cnt==1)&&(_T_base < 9)){ + if (_T_base <6)__Set(FIFO_CLR, W_PTR); + }else if(Wait_Cnt ==0){ + if ((_T_base > 8)||((OsBufferLogicFlag)&&(FPGAosFlag==0)&&(_T_base > 7))){ + freerun=1; + if((FreeRunEnable)&&(FPGAver>0)){ + __Set(32+14, 1 ); + JComp=0; + } + entryflag=0; + }else{ + __Set(32+14, 0 ); + JComp=1; + freerun=2; + entryflag=1; + } + if (JumpCnt > (392+Xtend))JumpCnt = 0; + Process(); + } + break; + case NORH: + case NORHLD: + if(Title[TRIGG][SOURCE].Value !=4){ + if(!OsBufferLogicFlag)__Set(TRIGG_MODE,(_Tr_source <<3)+TriggerType); + } + if((__Get(FIFO_START)!=0)||(_State.Value==2)){ //if device triggered or in pause mode + Process(); + Wait_Cnt=Wait[_T_base]; + }else{ + if(Wait_Cnt==0){ + Wait_Cnt = 1; + } + } + break; + case NORC: + if(!OsBufferLogicFlag)__Set(TRIGG_MODE,(_Tr_source <<3)+TriggerType); + if((__Get(FIFO_START)!=0)||(_State.Value==2)){ + Process(); + Wait_Cnt=Wait[_T_base]; + } else if(Wait_Cnt==0) //was ==1 + { + ResetSum(); + if (_T_base < 7) cleardatabuf(2); + ClearTrackBuff(0); + Wait_Cnt=Wait[_T_base]; //added + } + break; + case SGL: + if(!OsBufferLogicFlag)__Set(TRIGG_MODE,(_Tr_source <<3)+TriggerType); + if((__Get(FIFO_START)!=0)||(_State.Value==2))Process(); + break; + case SCAN: + if (_T_base>11){ + __Set(TRIGG_MODE, UNCONDITION); // works best at high sweep rates + }else{ // works better at low rates + __Set(TRIGG_MODE,3); // same as track1 (0) <<3 + 3 (>vt) (do not use digital chs...) + __Set(V_THRESHOLD,255); // level then set out of range. Prevents triggering(vt>255), with fifo "splice" shifted left 150pix, gives smooth display at low speeds + } + if (_T_base>7){ + freerun=1; + Process(); + }else{ //tbase<8 + freerun=2; + if ((FlagMeter==0) && (JumpCnt> 389)) JumpCnt=0; + if ((FlagMeter>0) && (JumpCnt> 304)) JumpCnt=0; + Process(); + } + } //switch + } + else //regular large buffer mode + { + switch (_Mode) + { + case X_Y: + case AUTO: + __Set(TRIGG_MODE,(_Tr_source <<3)+TriggerType); + if((__Get(FIFO_START)!=0)||(_State.Value==2)){ + Process(); + JComp=1; + Wait_Cnt = Wait[_T_base]; + } else if(Wait_Cnt==0) { + if(_Mode==X_Y){ + if(JumpCnt>=BufferSize)JumpCnt = 0; + }else{ + if(JumpCnt >= 4095) JumpCnt = 0; + if((FreeRunEnable)&&(FPGAver>0)){ + __Set(32+14, 1 ); + JComp=0; + } + } + Process(); + } break; + case NORH: + case NORHLD: + if(Title[TRIGG][SOURCE].Value !=4) __Set(TRIGG_MODE,(_Tr_source <<3)+TriggerType); + if((__Get(FIFO_START)!=0)||(_State.Value==2)){ + Process(); + Wait_Cnt = Wait[_T_base]; + } else if(Wait_Cnt==0) { + Wait_Cnt = Wait[_T_base]; + } break; + case NORC: + __Set(TRIGG_MODE,(_Tr_source <<3)+TriggerType); + if((__Get(FIFO_START)!=0)||(_State.Value==2)){ + Process(); + Wait_Cnt = Wait[_T_base]; + } else if(Wait_Cnt==0) { + ResetSum(); + ClearTrackBuff(0); // clear screen + Wait_Cnt = Wait[_T_base]; + } break; + case SGL: + if(!OsBufferLogicFlag)__Set(TRIGG_MODE,(_Tr_source <<3)+TriggerType); + if((__Get(FIFO_START)!=0)||(_State.Value==2))Process(); + break; + case SCAN: + if (_T_base>11){ + __Set(TRIGG_MODE, UNCONDITION); + }else{ + __Set(TRIGG_MODE,3); + __Set(V_THRESHOLD,255); + } + if (_T_base>7){ + freerun=1; + Process(); + }else{ //tbase<8 + freerun=2; + if(ChartLogic()){ + if(JumpCnt >= 4095){ + JumpCnt = 0; + if(AutoSaveBuf==1){ + if(ErrorFlag==0)ErrorFlag=Save_Buf(Title[9][1].Value++); + }else if(AutoSaveBuf==2){ + if(ErrorFlag==0)ErrorFlag=Save_Csv(Title[9][1].Value++); + } + if(ErrorFlag){ErrorFlag=0;AutoSaveBuf=0;} + } + }else{ + if ((FlagMeter==0) && (JumpCnt> 389)) JumpCnt=0; + if ((FlagMeter>0) && (JumpCnt> 304)) JumpCnt=0; + } + Process(); + } + } + + } // end else (framemode=0) + + if (_Mode==SCAN) Wait_Cnt = 1; + + if(_Mode==X_Y){ + if(JumpCnt>=BufferSize){ + JumpCnt = 0; + __Set(FIFO_CLR, W_PTR); + FrameEndFlag=1; + } + } + + if ((FrameMode > 0)&&(_Mode!=SGL)){ // in single frame buffer mode + if (_Mode==SCAN){ + if ((FlagMeter==0) && (JumpCnt> 389)) JumpCnt=0; + if ((FlagMeter>0) && (JumpCnt> 304)) JumpCnt=0; + } + + if (JumpCnt>(392+Xtend)){ + if((__Get(FIFO_START)!=0)&&(freerun!=2)){ // resetting FIFO after start flag and frame completed provides proper triggering in single frame buffer mode + FrameEndFlag=1; + JumpCnt=0; + if ((Options&1)&&(_T_base < 10)&&(!OsBufferLogicFlag)&&(_Mode!=AUTO)&&(_Mode!=X_Y)&&(_Mode!=SGL)&&(_Mode!=SCAN)){ //trigger hold mode, works only with time bases where process is slower than data transfers + CountUnread=0; +BailOut: + if (Title[7][3].Value>0){ //add additional adjustable delay just before resetting write pointer + + DelayLoopBreak=50; //restrict max time in loop to 1 sec to prevent possible lockup with empty buffer + while (CountUnread1)break; //when initiating, drop out to reset FIFO + if(DelayLoopBreak==0)break; //interrupt based breakout after 1 sec if necessary + } + if ((CountUnread>0)&&((CountUnread%(TrigDelayLoop[_T_base]))==0)){ //Allow program to operate on a time base related interval while counting delay + BailoutFlag=1; + break; + } + } + + } //if Title... (trig hold value > 0) + } //if options... (set trigger hold mode) + + if (BailoutFlag==0){ + + if (Title[TRIGG][SOURCE].Value==4){AlternateChannel();AltHoldoff=AltDelay[_T_base];} + __Set(FIFO_CLR, W_PTR); + + } + + waste++; //compiler needs to do something with this or generates error... (used to read FIFO) + } //if get fifo start + } //if jumpcnt> + } //if framemode>0 + + if((_Status == RUN)&&((_T_base > 10)||((_T_base>9)&&(Tim2Factor>20)))&&(_T_base < 14)&&(_Mode != SGL)){ + if ((__Get(FIFO_START)!=0)&&(FrameMode >0)) { //prevents "double looping" in single window buffer mode + if ((Title[TRIGG][SOURCE].Value==4)&&(_Status == RUN)) AlternateChannel(); //causing problems in 50, 100, and 200uS/div ranges + __Set(FIFO_CLR, W_PTR); + } + } + + if ((_Status == RUN)&&(__Get(FIFO_FULL)!=0)){ // FIFO is full + if(_Mode != SGL) { + if (Title[TRIGG][SOURCE].Value==4){ + AlternateChannel(); + if(_T_base < 10)AltHoldoff=AltDelay[_T_base]; + } + __Set(FIFO_CLR, W_PTR); //if mode is not single // FIFO write pointer reset + + }else if(_T_base < 11){ //in SGL mode, added reset after moving to slow mode + __Set(FIFO_CLR, W_PTR); //also added reset JumpCnt on hold/run reset + } + + if(_Mode!=X_Y){ + if (FrameMode == 0)FrameEndFlag=1; + if(!ChartLogic())JumpCnt=0; //FIFO full jumpcnt reset irrelevant in scan/chart mode + } + + if(_Mode == SGL){ + HoldOnNext=1; + } + } + + if(AutoSetFlag)AutoSet(); + + if(((FrameEndFlag)||((DownConvertMode)&&(FFTt1Mode)))&&(DownConvertShiftEnable)){ + FFTdownConvert(0); + if(DownConvertShiftEnable==3)DownConvertShiftEnable=1; + else if (DownConvertShiftEnable==2)DownConvertShiftEnable=0; + else DownConvertShiftEnable--; + } + + if ((_Mode != AUTO)||(_T_base > 8)||(exitflag==0)||(entryflag==0)) Draw_Window(); //Executing time consuming screen update AFTER resetting FIFO rather than before + //allows enough time for START flag to register at fast time bases - fixes triggering + //issue of slow/random pulses not triggering + if ((_Status == RUN)&&(__Get(FIFO_START)==0)&&(Title[TRIGG][SOURCE].Value==4)){ //alternate channels after delay if selected ch not triggered + if(_T_base > 9){ + cleardatabuf(TrigSourceEnable); + AlternateChannel(); + __Set(FIFO_CLR, W_PTR); + }else{ + if(AltHoldoff==0){ + AltHoldoff=AltDelay[_T_base]; + cleardatabuf(TrigSourceEnable); + AlternateChannel(); + __Set(FIFO_CLR, W_PTR); + } + if(AltHoldoff>0)AltHoldoff--; + } + } + +} + +u16 get_bag_max_buf(void) { +u16 out = 4096; + if(((_Mode==SCAN)&&(!ChartLogic()))||((ChartLogic())&&(FrameMode>0))){ + if (FlagMeter==0)out=390; else out=305; + if (_4_source>9)out=512; //for FFT + if (_T_base>9) out=390+150; //moves trigger splice out of view to left edge of screen at fast time bases for cleaner display + //if (AutoSequence>0)out=670; + if (AutoSetFlag)out=670; + }else if (((FrameMode>0)&&(_Mode!=SGL))||(OsBufferLogicFlag)){ + out = (393+Xtend); //modify buffer size if meters are on or off or XPOS shifted + if(OsBufferLogicFlag)FlagFrameMode=1; + }else if(_Mode==X_Y)out=BufferSize; + if(out>4096)out=4096; + return out; +} + + +void Beeper(u16 ms){ + if(Beep_mS<20) __Set(BEEP_VOLUME, 5*(Title[VOLUME][CLASS].Value-1)); //don't call beeper if currently beeping, seems to shut it off... + Beep_mS = ms; +} + +void AlternateChannel(void){ + if(TrigSourceEnable==1)TrigSourceEnable=0; else TrigSourceEnable=1; //cycle to next channel + + if(TrigSourceEnable==0){ //set up ch if enabled + if(Title[0][0].Value==0){ //otherwise skip to next ch + TrigSourceEnable=1; + }else{ + ReverseBitMask=0xFFFFFF00; + BitMask=0xFF; + } + } + + if(TrigSourceEnable==1){ + if(Title[1][0].Value==0){ + TrigSourceEnable=0; + }else{ + ReverseBitMask= 0xFFFF00FF; + BitMask=0xFF00; + } + } + + Update_Trig(0); +} + + +void cleardatabuf(u8 service) //Clears/replaces n samples in DataBuf +{ + + u32 sample=(B_Posi+ADCoffset); + u16 i; + + sample <<= 8; + + if(((OsBufferLogicFlag)&&(!OSAvg))||(OsChartFlag)){ + sample|=((u32)(A_Posi+ADCoffset)<<16); + sample|=((u32)(B_Posi+ADCoffset)<<24); + } + + if(service==0){ //clear ch A + sample=(A_Posi+ADCoffset); + for (i=0; i> 8)& 0x00FF; + }else{ //Otherwise read lo/hi pair, if hi on empty buffer loop again + loA=Transfer & 0x00FF; + loB=(Transfer >> 8)& 0x00FF; + if(__Get(FIFO_EMPTY)==0)Transfer=__Read_FIFO();else return; + hiA=Transfer & 0x00FF; //If readable finish and load + hiB=(Transfer >> 8)& 0x00FF; + } + + }else{ + + if(_T_base<16)OSFactor=8;else OSFactor=6; + OsTransferCompleteFlag=0; + if(i==0){TmpA=0;TmpB=0;Counter=0;} + + while(Counter++7){ + if(_T_base==8){Waste=0; while(__Get(FIFO_EMPTY)){if(Waste++>5000)break;}} + Transfer=__Read_FIFO(); + }else{ + if(__Get(FIFO_EMPTY)==0)Transfer=__Read_FIFO();else {Counter--;return;} + } + + swap=Transfer&0xFF; + if(swap>hiA)hiA=swap; + if(swap>8)&0xFF; + if(swap>hiB)hiB=swap; + if(swap>8; + }else{ + swap=(Transfer&0xFF00)>>8; //peak display + Transfer&=0xFF; + if(TransferhiA)hiA=Transfer; + if(swap>hiB)hiB=swap; + } + ChartSampleCounter++; + + if(ChartSampleCounter>=TbaseSub[SubIndex-1].S_OS_Size){ + if(ChartMode==0){ //Averaging mode + loA/=TbaseSub[SubIndex-1].S_OS_Size; + loB/=TbaseSub[SubIndex-1].S_OS_Size; + DataBuf[i]=(loB<<8)+loA; + DataBuf[i]|=Transfer&0x00030000; //add digital channels sampled at end of period + loA=0; + loB=0; + }else{ //peak display + DataBuf[i]=hiA+(hiB<<8)+(loA<<16)+(loB<<24); + hiA=0; hiB=0; + loA=0x000000FF; loB=0x000000FF; + } + ChartSampleCounter=0; + OsTransferCompleteFlag=1; + break; + }else OsTransferCompleteFlag=0; + } + + }else{ + DataBuf[i] = __Read_FIFO(); //normal mode + }//if (chartmode && calibratemode==0), else (regular mode and calibrate mode) + + }//if (OS buffer mode && calibratemode==0), else + + }//if (service && !chartlogic),else (service= A&B mode) + +} + +void SetOffset(u8 channel,u8 range, s16 Ypos) { +s32 temp; + + if(channel==0)temp=Ka3[range];else temp=Kb3[range]; + temp=(1024+temp)*(Ypos-ScalingOffset); //set Ka3 zero axis, allows scaling optimisation + if(temp>0)temp+=512; else temp-=512; + temp=(temp/1024)+ADCoffset+ScalingOffset; + if (temp<0)temp=0; //should not go anywhere close to 0 but just to make sure + if(channel==0)__Set(CH_A_OFFSET, temp); else __Set(CH_B_OFFSET, temp); +} + +void BatLevelCompensation(void){ +u8 i; //make sure both sets are available or don't use + + if((LoBatLevel[0]>2800)&&(LoBatLevel[0]<5200)&&(HiBatLevel[0]>2800)&&(HiBatLevel[0]<5200)){ + for(i=0;i<10;i++){ + Ka1[i]=InterpolateS8(0,LKa1[i],HKa1[i]); + Ka2[i]=InterpolateU16(0,LKa2[i],HKa2[i]); + Ka3[i]=InterpolateS8(0,LKa3[i],HKa3[i]); + } + } + + if((LoBatLevel[1]>2800)&&(LoBatLevel[1]<5200)&&(HiBatLevel[1]>2800)&&(HiBatLevel[1]<5200)){ + for(i=0;i<10;i++){ + Kb1[i]=InterpolateS8(1,LKb1[i],HKb1[i]); + Kb2[i]=InterpolateU16(1,LKb2[i],HKb2[i]); + Kb3[i]=InterpolateS8(1,LKb3[i],HKb3[i]); + } + } +} + + +s8 InterpolateS8(u8 Ch, s8 L8,s8 H8){ +s32 Tmp; + Tmp=((__Get(V_BATTERY)-LoBatLevel[Ch])*(H8-L8)); + if(Tmp>0)Tmp+=(VDiff[Ch]/2); else Tmp-=(VDiff[Ch]/2); + return (Tmp/VDiff[Ch])+L8; +} + +u16 InterpolateU16(u8 Ch, u16 L16,u16 H16){ +s32 Tmp; + Tmp=((__Get(V_BATTERY)-LoBatLevel[Ch])*(H16-L16)); + if(Tmp>0)Tmp+=(VDiff[Ch]/2); else Tmp-=(VDiff[Ch]/2); + return (Tmp/VDiff[Ch])+L16; +} + +s32 QError(u8 Ch, u16 Start, u16 End, u32 Utmp){ +s32 b,ab,tmp=0; + //quantization error compensation; improves accuracy of frequency/period meters on analog channels + + b=(QParam(Ch,Start,1)*(QParam(Ch,End,0)+QParam(Ch,End,1)))-(QParam(Ch,End,1)*(QParam(Ch,Start,0)+QParam(Ch,Start,1))); + ab=(QParam(Ch,Start,0)+QParam(Ch,Start,1))*(QParam(Ch,End,0)+QParam(Ch,End,1)); + tmp=Utmp/ab; + tmp=tmp*b; + if(Ch==0)tmp=tmp/TaS; else tmp=tmp/TbS; + return tmp; + +} + +s16 QParam(u8 Ch, u16 Position,u8 service){ +u8 a[2],b[2]; + + if(OsBufferLogicFlag){ + b[Ch]=RMSdata[Ch][Position]-ADCoffset; + a[Ch]=RMSdata[Ch][Position-1]-ADCoffset; + }else{ + if(Ch==0){ + b[0]=(DataBuf[Position]& 0xFF)-ADCoffset; + a[0]=(DataBuf[Position-1]& 0xFF)-ADCoffset; + }else{ + b[1]=((DataBuf[Position]>>8)&0xFF)-ADCoffset; + a[1]=((DataBuf[Position-1]>>8)&0xFF)-ADCoffset; + } + } + + if((InvertA)&&(Ch==0)){ + b[0]-=A_Posi; + b[0]=-b[0]; + b[0]+=A_Posi; + + a[0]-=A_Posi; + a[0]=-a[0]; + a[0]+=A_Posi; + } + if((InvertB)&&(Ch>0)){ + b[1]-=B_Posi; + b[1]=-b[1]; + b[1]+=B_Posi; + + a[1]-=B_Posi; + a[1]=-a[1]; + a[1]+=B_Posi; + } + + if(service){ //"b" + if(Ch==0){ + return b[0]-LastA_Mid; + }else{ + return b[1]-LastB_Mid; + } + }else{ //"a" + if(Ch==0){ + return FirstA_Mid-a[0]; + }else{ + return FirstB_Mid-a[1]; + } + } + +} + + +void Average(u8 Ch){ + + //sum averaging of all FIFO transfers; improves resolution/accuracy of all meters at faster timebases (>~5mS/div) + + if((_T_base > 10)||((JumpCnt==get_bag_max_buf())&&(_T_base>6)&&(FrameMode>0))){ + RunAvg(Ch); //time/freq parameters + if(Ch==0){ //voltage values + VxAvg[0]=VRunAvg(0,a_Avg,VxAvg[0]); + VNAvg[0]--; //reset VN counters to do SSQ + VxSsq[0]=VRunAvg(0,a_Ssq,VxSsq[0]); + }else if(Ch==1){ + VxAvg[1]=VRunAvg(1,b_Avg,VxAvg[1]); + VNAvg[1]--; + VxSsq[1]=VRunAvg(1,b_Ssq,VxSsq[1]); + } + + switch(Ch){ //summing for TH, TL, %duty + case 0: + PxS[Ch]+=PaS; + TxS[Ch]+=TaS; + TxN[Ch]+=TaN; + break; + case 1: + PxS[Ch]+=PbS; + TxS[Ch]+=TbS; + TxN[Ch]+=TbN; + break; + case 2: + PxS[Ch]+=PcS; + TxS[Ch]+=TcS; + TxN[Ch]+=TcN; + break; + case 3: + PxS[Ch]+=PdS; + TxS[Ch]+=TdS; + TxN[Ch]+=TdN; + } + }else{ + Sum[Ch]=UTmp; //if frame rates slower than meter reads no summing possible + + switch(Ch){ + case 0: + VxAvg[Ch]=a_Avg; + VxSsq[Ch]=a_Ssq; + PxS[Ch]=PaS; + TxS[Ch]=TaS; + TxN[Ch]=TaN; + break; + case 1: + VxAvg[Ch]=b_Avg; + VxSsq[Ch]=b_Ssq; + PxS[Ch]=PbS; + TxS[Ch]=TbS; + TxN[Ch]=TbN; + break; + case 2: + PxS[Ch]=PcS; + TxS[Ch]=TcS; + TxN[Ch]=TcN; + break; + case 3: + PxS[Ch]=PdS; + TxS[Ch]=TdS; + TxN[Ch]=TdN; + } + } +} + +s32 VRunAvg(u8 Ch, s32 Value, s32 Sum){ //running average of voltage values + if(Value>Sum){ + Sum+=((Value-Sum)/++VNAvg[Ch]); + }else if(Sum>Value){ + Sum-=((Sum-Value)/++VNAvg[Ch]); + }else VNAvg[Ch]++; + return Sum; +} + +void RunAvg(u8 Ch){ + if(UTmp>Sum[Ch]){ //moving sum average for frequency/period + Sum[Ch]+=((UTmp-Sum[Ch])/++NAvg[Ch]); + }else if(Sum[Ch]>UTmp){ + Sum[Ch]-=((Sum[Ch]-UTmp)/++NAvg[Ch]); + }else NAvg[Ch]++; +} + + +void ResetSum(void){ +u8 Ch; + + if(DownConvertMode){ + if(DownConvertInitiate==1){ + PrecisionLevel=0; + Display_Value(0); + FlagFrameMode=1; + Update_View_Area(); + DownConvertInitiate=2; + }else if(DownConvertInitiate==2){ + FFTdownConvert(0); + DownConvertInitiate=0; + if((FFTt1Mode==0)&&(DownConvert>1))FFTdownConvert(4); + } + } + + for(Ch=0;Ch<4;Ch++){ + Sum[Ch]=0; + NAvg[Ch]=0; + } + + if(EnablePaS){ //only reset after read, 1/second for TH,TL,%duty in large meters + for(Ch=0;Ch<4;Ch++){ + PxS[Ch]=0; + TxS[Ch]=0; + TxN[Ch]=0; + } + + } + VxAvg[0]=A_Posi*NSamples; + VxAvg[1]=B_Posi*NSamples; + for(Ch=0;Ch<2;Ch++){ + VxSsq[Ch]=NSamples/2; + VNAvg[Ch]=0; + ClearMinMax(Ch+1); + } + +} + +void ClearMinMax(u8 Channels){ + if(Channels&1){Ga_Max=(-0x7FFF);Ga_Min=0x7FFF;} + if(Channels&2){Gb_Max=(-0x7FFF);Gb_Min=0x7FFF;} + if((Options&4)==0){ //if hold mode is not set, reset GHx as this is used to transfer max and min values + ClearHold(3); + } +} + +void ClearHold(u8 Channels){ + HoldResetFlag=Channels; + if(Channels&1){GHa_Max=A_Posi;GHa_Min=A_Posi;} + if(Channels&2){GHb_Max=B_Posi;GHb_Min=B_Posi;} +} + +void ClearTrackBuff(u8 service){ +u16 i; + if(service)ClearLeadingEdge=1; else ClearLeadingEdge=0; + + if(service==2){ + for(i=0;i<397;i++){ + TrackBuff[(i*4)] = A_Posi; + TrackBuff[(i*4)+1] = B_Posi; + TrackBuff[(i*4)+2] = _3_posi; + TrackBuff[(i*4)+3] = _4_posi; + } + }else{ + for(i=0; i99){ + n/=10; + Charact++; + } + n=((50*((Charact*100)+Log10Mant[n]))+50)/100; + } + } + if(n>198)n=198; + if(AutoFFT>0)n=(n*(100+((198-n)/2)))/100; //2:1 compression, used for regular scaling + return n; +} + +void WaveGen(void){ +u16 i; +u16 j=0; +u16 YShift=0; + + if(_Kind==SINE)YShift=4095; + + if(_Kind==SAW){ + for(i=0;i<(720/ScaleIndex[_Frqn]);i++) + ATT_DATA[i]=(((Title[OUTPUT][OUTATT].Value*WaveValue(j+=ScaleIndex[_Frqn]))/100)+2048); + }else if(_Kind==DIGI){ + for(i=0;i<(720/ScaleIndex[_Frqn]);i++) + ATT_DATA[i]=(((Title[OUTPUT][OUTATT].Value*DIGI_DATA[(i/(360/ScaleIndex[_Frqn]))])/100)+2048); + }else if(_Kind==7){ + return; + }else{ + if(_Frqn<15){ + for(i=0;i<(720/ScaleIndex[_Frqn]);i++){ + if(i<(180/ScaleIndex[_Frqn]))ATT_DATA[i]=(((Title[OUTPUT][OUTATT].Value*WaveValue(j+=ScaleIndex[_Frqn]))/100)+2048); + else if(i<(360/ScaleIndex[_Frqn]))ATT_DATA[i]=(((Title[OUTPUT][OUTATT].Value*WaveValue(j-=ScaleIndex[_Frqn]))/100)+2048); + else if(i<(540/ScaleIndex[_Frqn]))ATT_DATA[i]=YShift-(((Title[OUTPUT][OUTATT].Value*(WaveValue(j+=ScaleIndex[_Frqn]))/100)+2048)); + else ATT_DATA[i]=YShift-(((Title[OUTPUT][OUTATT].Value*(WaveValue(j-=ScaleIndex[_Frqn]))/100)+2048)); + } + + }else if(_Frqn==15){ + + if(_Kind==SINE){ + for(i=0;i<18;i++){ + ATT_DATA[i]=((Title[OUTPUT][OUTATT].Value*(Sine100K[i]-2048))/100)+2048; + } + } + if(_Kind==TRIANG){ + for(i=0;i<18;i++){ + ATT_DATA[i]=((Title[OUTPUT][OUTATT].Value*(Triangle100K[i]-2048))/100)+2048; + } + } + }else{ + if(_Kind==SINE){ + for(i=0;i<9;i++){ + ATT_DATA[i]=((Title[OUTPUT][OUTATT].Value*(Sine200K[i]-2048))/100)+2048; + } + } + if(_Kind==TRIANG){ + for(i=0;i<9;i++){ + ATT_DATA[i]=((Title[OUTPUT][OUTATT].Value*(Triangle200K[i]-2048))/100)+2048; + } + } + + } + } +} + + +s16 WaveValue(u16 j){ + if(_Kind==SINE) return (SIN_QUAD[j]-2048); + else if(_Kind==TRIANG)return (((11372*j)+500)/1000); + else if(_Kind==SAW)return (((5686*j)+500)/1000)-2048; + else return 0; +} + + +void InitiateCalData(void){ +u8 i; + + for(i=0;i<10;i++){ + + Ka1[i] = Kb1[i] = Ka3[i] = Kb3[i] = 0; + Ka2[i] = Kb2[i] = 1024; + + HKa1[i] = HKb1[i] = HKa3[i] = HKb3[i] = 0; + HKa2[i] = HKb2[i] = 1024; + + LKa1[i] = LKb1[i] = LKa3[i] = LKb3[i] = 0; + LKa2[i] = LKb2[i] = 1024; + } + +} + +void InitiateOSBuffers(void){ +u16 i; + for (i=0; i=WindowPosition)&&(i<(FFTSize+WindowPosition))){ + OsFFTData[0][i-WindowPosition]=DataBuf[i]&0xFF; + OsFFTData[1][i-WindowPosition]=(DataBuf[i]>>8)&0xFF; + } + } + for(i=0;i<397;i++){ + TrackBuff[(i*4)+2] = TrackBuff[(i*4)]; + TrackBuff[(i*4)+3] = TrackBuff[(i*4)+1]; + } + +} + +u16 RandomGen(void){ //random number gen to dynamically seed noise generator +static u32 Tmp=1746698375; + Tmp=((u32)1664525*Tmp)+(u32)1013904223; + Tmp>>=20; + return Tmp&0x00000FFF; +} + +u8 TriggerModeLogic(void){ + return(((Title[7][1].Value>3)&&(Title[7][1].Value<8))||((_T_base>18)&&(FPGAver==0))||((Sweep>0)&&(_Kind<5)&&(Title[7][1].Value==8))); +} + +u8 OSBufferLogic(void){ + return(((_T_base<17)||((_T_base<20)&&(FPGAsubVer)&&(FPGAosFlag)))&&(OSBuffer)&& + (!(((Title[0][1].Value==2)&&(_1_source))||((Title[1][1].Value==2)&&(_2_source))))&& + (_Mode!=X_Y)&&(!ChartLogic())&&(_Mode!=SCAN)&&(Title[TRIGG][SOURCE].Value!=4)&& + (!UartLogic())&&(!i2cLogic())&&(!SpiLogic())); +} + +void ClearMeters(void){ + if(((_Mode==NORH)||(_Mode==NORHLD))&&(__Get(FIFO_START)==0)){ + EnablePaS=1; + ResetSum(); + } +} + +u16 GetXposRef(u16 XPos){ + if(_Kp1==246){ + return((((102400000+(KpCompensation()/2))/KpCompensation())*XPos)+500)/1000; + }else if(_Kp1==1024){ + return XPos; + }else{ + return((((102400000+(KpCompensation()/2))/KpCompensation())*XPos)+5000)/10000; + } + +} + +u16 GetXpos(u16 XposRef){ + if(_Kp1==246){ + return(((((KpCompensation()*1000)+512)/1024)*XposRef)+50000)/100000; //align interpolated time bases with others + }else if(_Kp1==1024){ + return XposRef; + }else{ + return(((((KpCompensation()*10000)+512)/1024)*XposRef)+50000)/100000; + } +} + + +void SetTthreshold(u16 Time){ +u32 UTmp=Time*FPGA_OS_Size; + + if((OSBufferLogic())&&(FPGAsubVer)&&(FPGAosFlag)){ + __Set(T_THRESHOLD,(u16)(UTmp&0x0000FFFF)); + __Set(32+0x11,(u8)(UTmp>>16)&0x000000FF); + __Set(32+0x12,(u8)(UTmp>>24)&0x000000FF); + }else{ + __Set(T_THRESHOLD,Time); //bits 0-15 + if(FPGAsubVer){ + __Set(32+0x11,0); //bits 16-23 + __Set(32+0x12,0); //bits 24-31 + } + } +} + +void UpdateCursorMeter(void){ + CursorDisplaySelectLogic(); + if(CursorDisplaySelect<4)CalculateTvernier(1); //Xpos/Tvernier display + else if(CursorDisplaySelect<8)CalculateVvernier(1); //Vvernier display + else {CalculateVvernier(2);return;} //Trig vernier display + CalculateTvernier(0); + CalculateVvernier(0); +} + +void CursorDisplaySelectLogic(void){ //called from update +EnableCursorDisplay=1; +CursorDisplayTimer=150; + + if(((DisableCursorDisplay&1)==0)&&((Current==T_VERNIE)||((Current==T_BASE)&&(_Det==2)))){ + if(Detail[T_VERNIE]==0)CursorDisplaySelect=0; + else if(Detail[T_VERNIE]>0) CursorDisplaySelect=2; + if(_Mode==SCAN)CursorDisplaySelect++; + }else if(((DisableCursorDisplay&2)==0)&&(Current==V_VERNIE)){ + if(_Det==0)CursorDisplaySelect=4; + else CursorDisplaySelect=6; + if(_Meas_V_Track)CursorDisplaySelect++; + }else if(((DisableCursorDisplay&2)==0)&&(Current==TRIGG)&&(_Det==2)&&(TrgAuto==0)&&(_Mode!=SCAN)){ + CursorDisplaySelect=8; + }else{ + EnableCursorDisplay=0; + CursorDisplayTimer=0; + } + if(DisableCursorTimer){CursorDisplayTimer=0;DisableCursorTimer--;} + +} + +void DownConvertRestore(void){ + + DownConvertInitiate=0; + _T_base=DCbase; + Title[6][0].Value=DCmode; + Update_Base(); + FlagFrameMode=DCframe; + FlagMeter=DCmeter; + _T1=DCt1; + if(FlagMeter)EnableMeter(); + Title[6][0].Flag |= UPDAT; + Title[6][1].Flag |= UPDAT; + Update_View_Area(); +} + + +/******************************** END OF FILE *********************************/ + + + diff --git a/README.TXT b/README.TXT new file mode 100644 index 0000000..b573748 --- /dev/null +++ b/README.TXT @@ -0,0 +1,966 @@ + +Wildcat Community Edition revision(W6.5) + +Based on DSO203 GCC v1.7 APP (Revisions and notes for previous versions below) + +Developed and tested with: + - SYS 1.64 + - FPGA W1.1 (Custom FPGA for HW 2.81 archived with app) + - HW 2.81 + +>>V6.2 AND UP WILL OVERWRITE THE FPGA IF LOADED ON EARLIER UNITS. PLEASE MAKE SURE TO USE THE CORRECT VERSION FOR THE HARDWARE + +VERSIONs 6.0 and higher TO BE USED ONLY ON HARDWARE 2.81 OR HIGHER DEVICES +ANY FUTURE UPDATES FOR PRIOR HARDWARE VERSIONS WILL BE POSTED AS 5.X +VERSIONS 6.0 AND LATER WILL BE ONLY COMPATIBLE WITH HW 2.81 DEVICES AND LATER DUE TO LARGER RAM SIZE AVAILABLE IN +THESE. + +CHANGELOG TO VERSION W6.5: + +-Added high resolution FFT modes. + +-Shifted ROM addressing so both slot 3 and 4 are open. + + +CHANGELOG TO VERSION W6.4: + +-Added auto setting function. + +-Added cursor display to show position values of various cursors. + +-Added control to set fast auto key repeat buzzer volume. + +-Increased speed of T and V cursors, and also of Y position controls. + +-CSV update: added time field, limited export to size of buffer used. When used with digital channels turned off, analog + channels now display in actual voltage values referenced to the baseline, with oversampling data provided in an additional + field for each channel, rather than ADC step values. + +-Delta V/T and T1-T2 freq meter display while meters off are now part of cursor display routine and control, changed from direct + screen write to screen buffer write to eliminate flickering. + +-Fixed duty cycle on 1Mhz PWM signal used for frequency adjustment in calibration routine, setting resulted in a very narrow width. + Also prevents sweep/burst modes from interfering if enabled prior to calibration. + +-Fixed a condition where if the buffer mode was shifted out of large mode with xpos moved past a certain point to the right in + one of the fastest interpolated ranges and then the timebase was set to a lower speed, then shifted back again to large buffer mode, + xpos was not scaled correctly, causing the window to possibly "loop around" past the end of the buffer. Also fixes BUF files not + scaling XPOS correctly when loading non IP data while in an IP mode. + +-Fixed an issue with internal file writes where if a file of a longer length overwrote a shorter file (eg: BMP's and CSV's which's length + can vary), the internal file write function would return the end of file marker of the previous file as chaining info, potentially + sending writes back to overwrite the FAT. End of volume function in previous version prevented this, causing the new file to just be + truncated instead. Overwriting files with different lengths will now delete the previous file first, clearing all previous chaining info. + + +CHANGELOG TO VERSION W6.3: + +-Added file delete to directory functions. Also CSV and BIN (ROM image) files will now show in list. + +-Enabled digital channels to be displayed in chart mode when used in averaging mode. Digital channels are blanked out + in chart oversampling mode as digital channel buffers are used to store OS data for the analog channels. Also fixes display + noise in chart oversampling mode if channel D was enabled. + +-Disabled Spectrograph. MAP and all serial decode modes while in chart mode, engaging these either interfered with or disabled chart. + +-Enabled proper FFT function while in chart mode. + +-Added internal SYS file write address monitoring for 8MB devices, a file write while the drive was full would result in the address + "wrapping around" and overwriting the file allocation section, rendering the drive unreadable. Program will now stop file writes + before this happens. + +-Chart mode is now saved with BUF files to engage proper type of buffer when reloading these. + +-CSV file headers updated to display more information, also end of file now eliminates added nulls or data truncation, which can + confuse some charting/spreadsheet/editing programs. + +-Replaced HEX display lookup chart for decode modes with function generating these to save ROM space. + + +CHANGELOG TO VERSION W6.2: + +-Added directory list display to load files, also ability to name files before saving. + +-Fixed inability for FFT to update from buffer when in hold mode in the slower timebases. Also allows proper FFT + initiation and control while viewing a BUF file. + +-Fixed T1 - T2 delta time/frequency display while in chart mode, did not work right with oversampling mode added + in last update. Also, delta time shows in minutes if greater than 120 seconds. Frequency is blanked out if delta + time is greater than 120 seconds (8.3 millihertz) + +-Eliminated the delay at the end of auto reset used in persistence mode. Delay was set to 20mS x number of frames + displayed before reset, with a max of 50 or 1 second. Allows faster display refresh. + +-Changed positioning of byte indicator display in SPI decode so it will not be influenced by calibration factors. + +-Changed "IMG" type file save (actually a .BIN file) to "ROM" to better clarify it's purpose. + + +CHANGELOG TO VERSION W6.1: + +-Updated chart mode with oversampling to fix improper ADC operation at very slow timebases. + +-Added selection of either averaging or oversampling to chart mode controls. + +-Fixed long buffer mode not initiating when recalled from a config if device was in full speed buffer mode, + instead would go to non OS single window buffer mode. A subsequent load of the config could then engage long + buffer mode. + +-Changed detector mode frequency display so that it is no longer dependent on freq meters. Display will be enabled + if trigger source is on either chA or B if proper waveform is displayed within cursors on that channel while + in cursor restrict meter mode, regardless of whether freq meters are engaged or not. User manual has been updated + on how to use DET frequency display. + + +CHANGELOG TO VERSION W6.0: + +-Increased RAM allocation from 48K to 64K and call stack from 8K to 16K. Fixes a variety of potential problems + such as loss of meter functions or triggering issues after config file saves. + +-Fixed an issue where the program would crash if loading a saved configuration file with a full speed + sampling setting while in one of any of the OS modes if the saved configuration contained a long buffer + mode XPOS value greater than a certain value. XPOS was improperly initialized on loading config, leading + to array overflows. + +-Fixed shifting ChA/B DC offset levels after engaging FFT or other functions while in full speed buffer mode, + possibly leading to corrupted calibration data if saved. Increased OsFFTdata and RMSdata array sizes to take + account of increased size demand when engaging FFT with XPOS shifted towards left of screen, causing + overflowing into configuration data arrays. + +-Fixed Vmin, Vmax, and P-P meters not properly resetting at end of frames and keeping their max/min values + while in 500uS timebase if FFT is engaged or GEN set to one of the 2 fastest sweep/burst modes, subsequently + resetting on re-triggering event or setting changes. + + +LATER W5.x VERSIONS COMPILED FOR OLDER VERSIONS ONLY + + +CHANGELOG TO VERSION W5.1: + + -Added full speed buffer mode when used with Ver W1.1 FPGA on Hardware V2.81 devices + + -Added horizontal trace thickness control. + + -Added interlace mode reset: system sets this, now mode is reset to separate, was causing analog + trace offset between channels at fastest timebases when used with some ADC versions + + -Fixed UART generator function when attempting to send a non existing file, generator would send whatever + happened to be in the buffer anyways, using the number of bytes from previous transmission. + + -Fixed BMP, BUF and CSV files prematurely incrementing number values while saving. + + -Trigger delay function is now disabled in oversampling modes. + + -Added frequency display as alternative to delta time for Time cursors. Highlight T cursor display as + sub menu item (T1 > T2 > Display), toggle between time or corresponding frequency with left toggle. + + -Increased RAM access from 48KB to 64KB and stack size from 8KB to 16KB as a test for compatibility of + earlier processor with latest one but Reverted back to 48K/8K, earlier processors while having increased ROM + from specs still only appear to have 48K RAM. This may eventually necessitate 2 different versions + as program size increases with added functions only available with the later hardware. + + +CHANGELOG TO VERSION W5.0: + + -Detection of revised FPGA: Program will not shift to alternate time based mode when triggering + in level or edge mode at fastest timebases with new FPGA, improves triggering resolution. + + -Added option to select freerun in AUTO trig mode (only available with revised FPGA). + + -Fixed pixels left behind in meter section after loading BMP'S with meters on. + + -Fixed jitter stabilization not working at fastest timebases if either channel A or B was in invert mode. + + -Fixed BUF file loads not scaling time base right if loaded while in time bases > 5uS/div. + + -Added button 6 center press (right toggle) to view previous BMP/BUF files after loading file + with center press button 5 (left toggle, which also selects next BMP/BUF). + + -Fixed UAR file load not stopping transmission at end of file on 8MB devices when using generator + UART function. + + -Moved the "File already exists" notification off the screen so it does not get saved along with the + display in BMP save mode. + + -Increased hysteresis of battery level compensation to minimize frequency of shifting DC offsets + from varying loads on battery. + + -Fixed screen update after "scope disabled" notification while in XY mode with wave generator on. + + + +CHANGELOG TO VERSION W4.5: + + -Added version detection to properly implement the "2 least significant swapped bit issue" of + earlier FPGA versions. + + -Fixed initial calibration failing if device is in oversampling mode. + + -Added overwrite file warnings when saving BMP, CSV and BUF file formats. + + -BMP and BUF load functions now auto increment file numbers. + + -BMP load can now display next file with just one push of center button 5. + + -Fixed 16 color BMP load not covering entire screen on 8MB drive devices. + + -Added function to save entire ROM to an image file to restore a disabled device to it's + original state via JTAG header if ever necessary. + + -Extended Chart mode time base up to 100mS/div. + + -Added option to auto save incrementing BUF or CSV files at end of each acquired buffer in + full buffer chart mode. Provides continuous recording of long periods of data. + + -Disabled TH, TL, %duty and period time meters while in chart mode. + + -Fixed T cursor delta time display while in chart mode, now works up to 1000 seconds. + + +CHANGELOG TO VERSION W4.4: + + -Added averaging and oversampling buffer modes and related code to integrate with other functions + + -Changed the RAW/NORMAL control for persistence mode (center press left toggle) to work only when + menu is ON PERS rather than all the time with any menu (preventing trig source selection to work) + + -Changed the SPEC > SPEC-ENVELOPE > ENVELOPE control (center press right toggle) to work only when + menu is on SPEC rather than all the time with any menu (preventing buffer selection to work) + + -Updated BUF file save/load to function properly with chart mode. + + -Fixed incorrect Y position of .DAT files displayed with chD file rec function + + -Disabled XPOS in TrOFF mode UNLESS in large buffer chart mode.(XPOS was not doing anything useful) + + -Eliminated buffer reset in TrOFF and CHART and TrOFF modes when changing timebases, prevents previous + buffer contents from displaying, enabling disturbance free TB changes. + + -Provided proper initiation of chart mode when booting up, recalling config, coming out of standby + and loading saved BUF file. + + -Added bright adj for fast vert lines, select backlight menu, press left toggle center. Brightness + of >5 pix vert row is adjustable from dim (default) or 0, to 3 or bright. Fixes brightness + "flickering specks" effect on some screens (others need to be looked at from an angle to notice). + Visible with certain waveforms, EG: 6 sine waves filling screen at ~3/4 full scale amplitude. + Save setting by saving boot config (cfg file #0). + + -Added reset for auto trigger when trig update is called. + + -Various minor menu bug fixes. + + +CHANGELOG TO VERSION W4.3: + + -Added UART serial code to generator functions, along with .UAR file load function. + + -Updated UART DECODE so it can be used with the fastest timbases (2uS and faster) + + -Fixed an issue when shifting XPOS with UART decode while paused in the slower timebases +and the program auto-synchronizing on a continuous data stream where the decoded data would +blank out if the XPOS control toggle was held, and not reapear until it was released. + + +CHANGELOG TO VERSION W4.2: + + -Added chart mode. + + -In file write routine for .DAT format: changed read loop from <399 to <397 to prevent +out of bounds array access for TrackBuff[]. + + -Compiled seperate version with speed optimizations, resides in first 3 slots with rest of code +at 0x4C000. + + +CHANGELOG TO VERSION W4.1: + + -Added i2C and SPI decode functions. + + -Fixed an issue where a saved menu item was advanced when saving config files with button 3 +and using button 5 to confirm. Restored menu item was incorrectly advanced, rather than the +file number menu item. + + -Fixed a problem with serial decoding under some conditions intermittently triggering in the +500uS time base while in large buffer mode. + + -In serial decoding, fixed DataBuf array being accessed out of bounds if T1 cursor and Xpos +are all the way left to 0 in manual start mode. Does not seem to cause any issues but has the +potential to. + + -This version only available in 3 slot version, not enough room in ROM to compile with speed +optimisations to fit within 4 slots. + + +CHANGELOG TO VERSION W4.0: + + -NOTE: this version now utilizes 3 memory "slots". + + -Added sweep, burst, white noise, arbitrary and pulse generator functions. + + -Extended analog generator frequencies to 200Khz. + + -Added "detector" mode. + + -Added "GEN" trigger mode. + + -Added RS232/TTL decoding function. + + -Numerous internal changes so program works properly with added functions. + + -FFT "window" now shifts along with XPOS in large buffer mode rather than just reading beginning of buffer. + + -Added visual indicator (display brightness flashes) to beep indicating the start of long button press: +helps in noisy environments when rather faint beeper can't be heard. + + -Included an otherwise identical in function higher performance 4 "slot" version. + + + +CHANGELOG TO VERSION W3.4: + + -Fixed triggering issue in SINGLE mode in 2mS, 1mS and 500uS timebases (& possibly others) where the device +would trigger twice if data captured would exceed length of the buffer, making it impossible to see the start of the +captured waveform. + + -Fixed triggering issue after changing from AUTO to NORMAL modes at 500uS timebases and slower, where the +device would have to trigger one or more times before displaying a waveform. + + -Fixed a bug where meter readings were inaccurate or could change while in NORMAL mode with display frozen with +the latest waveform while not triggered, also causing subsequently triggered readings to be incorrect until +a sufficient number of samples were collected. + + -Modifications to level and edge triggering in the two fastest sweep ranges, improves signal acquisition for random/slow/ +intermittent signals. Some devices that have shown varying abilities in this respect should improve with this. + + -Fixed save 16 color BMP function to improve display screenshot quality. Parts of the display overlapping +the background grid were improperly copied. + + -Fixed a (likely rare) issue where push button contact "bounce" could cause a saved configuration to apparently +loose the ability to select menus upon loading it, caused by the menu focus being on meter select while meters +are off. This could happen if a saved config had the menu focus on meters and button 3, which is also used to +toggle meters on/off bounced while being used to save the config, simultaneously shutting meters off. + + +CHANGELOG TO VERSION W3.3: + +-Added LOG amplitude scaling option to FFT display. Use left toggle in Ch D menu in notification +area: LOG>AUTO>0db>+6db>....>+42db + +-Changed FFT buffers to 32 bit. Allows proper dynamic range so LOG display works properly, gain is +increased to +42db (+48 with log scale). Changed windowing from Hamming to Hann for better +compatibility with the increased dynamic range. + +-Updated internal generator output to produce high quality waveforms using up to 720 sample points + (gradually reducing at the highest frequencies to remain within DAC capabilities: 5khz range + samples @ 360, 10khz @ 180 and 20khz @ 72) + +-Added continuously variable frequency control for generator output: While in OUTPUT menu and freq + range item blinking, press left toggle center button to access frequency display in notification + area. Output frequency can be finely adjusted up or down with left toggle. Eg: if set to 100hz range, + frequency can be shifted from 50Hz to 200hz in steps of approx +/- 0.7% (0.7Hz). Note that at the + higher frequency ranges, highest frequency available will be limited and range step size increased + due to internal DAC sampling rate and clock divider limitations. + +-Added beeps to the beginning of long press and hold functions for push buttons. + +-Added frequency scaling and seconds ticks to spectrograph display. + +-Program will now only save BMP screenshots in 64K colors if spectrograph or map mode is + displayed, otherwise will save in 16 color mode so files are not unnecessarily large. Either + type will load for viewing. + +-Changed voltmeters from reading 0.XXX KV to XXX V when reading over 100 volts on X10 ranges + +-Added ability to shift the ADC operating "window" to compensate for hardware issues. While the ADC + provides 256 "steps" (8 bits), only 200 are used for the display. The original programs used steps + 0 to 200, discarding the top 56 at the top of the screen. Unfortunately, there is quite a bit of + non-linearity (compression) in the bottom 50 or so steps, causing distortion of the waveform. In + order to compensate for this, the operating point was shifted up by 54 steps, moving the entire + range into a more linear area. In addition to minimizing the distortion at the bottom, this also + helped the calibration procedure achieve better results, as it assumes linear ADC operation. + However there have been instances where the preamp failed to fully swing the signal to the top + of the ADC range, resulting in visible clipping below the top to the screen. This control can be + used if desired to bring the operation point down below the point where clipping occurs, albeit + at the expense of engaging down more into the non-linear area at the bottom of the range. + Change ADCoffset within a range of 0 to 54 by holding button 2 (as if to enter the calibration + routine) WHILE NOT in either chA or chB menu or one of their sub-menus. Then save settings in + config#0 in the normal way. + +-Fixed %Duty meter item (was not working at all in V3.2) + +-Fixed a bug where, if not triggered in normal modes, certain items on the display would not +be updated or would show incorrectly when changing settings until the device triggered again. + +-More code compacting to keep program within 2 program slots + misc minor bug fixes. + + + +CHANGELOG TO VERSION W3.2: + +-Added support for 8Mb devices, integrated bobtidey's code. (Untested at this time) + +-Added persistence mode: With oscilloscope trace, provides display more like an analog scope on +continuously changing waveforms by storing trace history over time. With FFT works as peak hold. +In XY mode, improves graphics of stationary patterns. Reset with any button, or freeze,then reset +with HOLD. OR While in Tbase/Mode menu, change menu item (button 4), selection will show number +of frames to "persist" in notification area before automatically resetting. Change with left +toggle. Select "cont" towards the left to disable auto resetting. Provides very fast frame rates +(up to >100 FPS in scope mode depending on signal and timebase). While in PERST mode, press left +toggle center button (normally trigger source shortcut) to toggle RAW or NORMAL trace. Raw mode +only displays data points, with no interpolation. Provides clearer display when many traces are +close together. Note: Display will not scroll with XPOS and verniers will not update positions +while in HOLD in persistence mode, must be in RUN mode. + +-Changed spectrograph mode to properly display at slow time bases > 500uS/div. D ch input +selection now shows only SPEC: Change input channel by switching ChA/ChB ON/OFF (ChA overrides ChB +if both are on). Also modified code so timing integrity (speed of update with triggered signal +vs not triggered) is maintained when using single frame buffer. Allows meaningful displays of +intermittent signals such as speech. + +-Added switchable amplitude envelope display with spectrograph. Use center press button 6 (normally +buffer size control) to select spec, spec + envelope or envelope. + +-Added 30db additional selectable input gain in 6db steps to all FFT based functions. Allows +readings on low level signals. With any FFT based mode engaged and ch D menu selected, press +menu item select (button 4). Menu will show input gain control in notification area rather than +Y position, change with left toggle. Move all the way left to select AUTO or to the right to select +a fixed value. Note that in persistence mode, if FFT gain is set to AUTO, db scale will not show, +since trace levels will be displayed from various scales. + +-Added "MAP" function. Displays changing waveform amplitude rather than frequency spectrum over +time (similar to Chip's "video" mode) Use ChA/ChB ON/OFF to change input channel. Note that Y +position will affect color of background, as this is part of the signal. + +-Updated XY mode. Now uses buffer variable from 256 to 4096 samples. While in XY mode, Mode/Tbase +menu will change item to samples display in notification area, instead of Xpos. Change size with +left toggle. Use smaller buffer size to speed up frame rate for moving patterns, larger to improve +graphics. Larger buffer allows a faster time base to be used, further improving graphics. Graphics +quality can also be set with timebase, then buffer can be increased to complete waveform. Best results +are typically obtained when buffer is just large enough to hold one complete waveform. With +stationary patterns, while in XY mode, press center left toggle (normally trigger source shortcut) +to toggle persistence mode: can greatly improves stationary graphics, depending on buffer and +timebase settings. + +-Changed BMP export function to save in 64K color format. Necessary for proper definition of fine +detail in spectrograph and map modes (requires Alterbios for older SYS versions or BMP files may get +corrupted). + +-Added the ability to load saved 64K color BMP screenshot files for viewing. + +-Eliminated vernier marks at left side of screen from overwriting spectrograph display when +auto trigger changed their position. + +-Shifted FFT summing mode engagement 2 more bins to the left, now provides proper displays at extreme +left of screen. Also FFT "peak" frequency display and indicator are turned off when meters are off. + +-Changed FPS meter code to show 3 digits. + +-Changed BUF file save/load to saving/restoring time base settings rather than generator output menu. + +-Various routine optimizations, refinements, minor bug fixes and code compacting to allow program to +still fit within 2 slots without giving up any functionality. + + + + +CHANGELOG TO VERSION W3.1: + +-Fixed color background for FFT values being used from out of bounds array index, producing faint +blue background (or possibly something else if recompiled) instead of black. Also changed FFT +frequencies display to green to match channel D color (provides better visibility than red). + +-Fixed inadequate buffer size being used under some conditions when using spectrograph function. + +-Fixed a bug where meter readings of one channel would show up on another channel if it was turned +off and FFT turned on. + +-Changed triggering selection logic to better integrate with FFT when not displaying trace. +When all channels are off, triggering will be set to FFT displayed channel. Also, trigger selection +shortcut will acknowledge FFT channels, if on, when switching trigger source, rather than channel D. + +-Changed V/div shortcut: now if selection is already on V/div, will toggle channel on/off, rather than +going to other analog channel's V/div and turning that one on, if off. Also if FFT is on with all +channels off, shortcut will go to the FFT's channel V/div but will not turn it on (long press again +to toggle channel trace on/off if desired). + +-Added V2 cursor = db in FFT mode, V2 cursor position added at top of screen. Helps calculate db +readings, particularly near bottom of screen. + +-Changed graphics of FFT freq displays so peak trace can be clearly seen through them, providing +better visibility at top of screen. + +-Changed most often called for background graphics refresh source from ROM constants to run time +loaded RAM arrays. Provides significant increase in frame refresh rate (specially in single frame +buffer mode) and reduction of ROM size allows program to still fit within 2 "slots" in spite of +increased size/complexity. + +-Start/Stop will now pause spectrograph. + +-Eliminated needless simultaneous drawing of hidden trace graphics while in spectrograph mode +(speeds up refresh). + +-FFT summing mode now engages a bin earlier at the extreme left in the spectrum. + + + +CHANGELOG TO VERSION W3: + +-Added Pmos69's FFT and spectrograph functions: + +-Added selectable Hamming window or adjacent bin summing, some amplitude compression and screen +calibration in decibels. Adjacent bin summing provides flat frequency response at the expense of +resolution restricted to every other bin. Provides flat response similar to a flat top window but +only expands bandwidth to 2 bins. + +-Corrected FFT frequency values displays. Also allowed meters to show with FFT on but channel turned +off. + +-Optimized code so still fits within 2 ROM "slots" (barely, beware if recompiling) - without +spilling into the 3rd. + + + + +CHANGELOG TO VERSION W2: + +-Added on-screen chart showing functions of all buttons. Hold button 1 (> 1- 1/2 sec). + Press any other button to execute it's normal function and exit chart or press button 1 + again to exit without doing anything. + + PRESS > [] O ^ + + + SHORT> HOLD AUTO METERS SELECT SET TRG BUFFER + reset TRIG sav/ld ITEM CHANNEL (spec/env) + (config) + + LONG> V/DIV MAN STAND T-BASE MTR PGE MENU/MTR + short TRIG BY short (w/mtrs on) + cut cut WAV CAL STDBY TIM + (w/mtrs off) + METERS + HOLD> CHART CAL SAVE CURSOR TRIGGER HOLD + (config) RSTRCT HOLDOFF MIN/MAX + +-Added "cursor defined meter" function. Hold button 4 to toggle mode. "X" symbol appears + in menu when mode active. When active, all meter readings are confined between the 2 (T1-T2) + time cursors. Move either cursor all the way right/left to disable that cursor: With T1 all + the way left, includes all samples from start of buffer, with T2 all the way right, includes + all samples all the way to the end of the buffer (Move Xpos to effectively change positions + of these cursors). Time based meters can have their trigger point moved by lowering V1 or + raising V2. Once these cursors reach the normal half way (between top and bottom waveform + peaks) reference point for the time meters, V1 will drag it down or V2 will drag it up, + allowing time measurements on selected parts of the waveform. Works in all modes whether + in run or hold and at all "X" positions. Useful for example to get correct frequency + readings on tone bursts and other parts of complex waveforms, specially in long buffer mode. + Also moving V1 below trigger level allows V2 to take precedence and set trigger point. + +-Jitter stabilization: gets rid of excessive internally generated jitter on the fastest + time bases. + +-Added alternate meters with bigger display. Change type with button 3: >Meters off > regular + meters > large meters. Default large meter page shows 2 meters with small globals (vol, + backlight, battery, etc) Other pages show 3 meters with small Delta V and Delta T. Change + page/source/item the same way you do with the regular meters. Large meters have a faster + display refresh of 3 times/sec for all readouts except for TH, TL and %duty which have 1/sec + timing to reduce "bobbling" and increase the number of values calculated in averaging. + +-Added A&B trigger mode: ability to trigger on 2 different waveforms simultaneously on + channels A and B. With both A and B channels on, change Trigg Source to A&B. Trig mode is + locked in Normal Hold in this function, and C & D channels are locked out in this mode. Also + can use trig source shortcut to enable mode if both A and B channels are turned on. Auto + trigger and trig level will move both A and B trig levels simultaneously. To change + individually, change trig source with left toggle push button to select A or B and change + trigger levels on each channel independently, then go back to A&B mode. Note that since + AUTO is not available in this mode, display will be frozen (as in regular NORM mode) + unless a triggered signal is connected to at least one of the inputs. + +-Modified meter item/source selection to show only relevant items depending on the source/ + item: When switching meter item source to digital channels for example, selection does not + show voltage meters. + +-Changed time based trigger type menu titles. For example, it seems clearer to show "trigger + on low pulse if longer than Delta T1- T2 cursors" as "L>Delta" rather than ">TL"... How many + users realize that the time based trigger function pulse widths are based on the difference + between the 2 time (T1 & T2) cursors (regardless of their position within the screen). + +-Added ability to save multiple configuration settings, up to 10. Hold button 3 down. When + saving config, file menu appears with "save config #0" as bootup default. Press button 3 + again to save as default (on boot-up) config file or change number with left toggle to + choose a different file number. To load a config file, go to file menu: Default after boot + up when choosing file menu will be "load config", with last saved file number flashing. Use + left toggle to select file number if desired (0 will always be the boot-up config)and press + center left toggle to load and stay in file menu (useful for browsing configs) or press + button 3 to load, and go to current "flashing" menu at time of save. File menu has been + moved to the extreme right at all times, making it easy to reach (just hold menu toggle + right). Program will only write to existing files to prevent file corruption when using + original system versions. Calibration data is only loaded from config #0, so calibration + can be updated without interference from additional configs. The number of the presently + loaded config file is shown as a digit 0-9 on the menu. See below for more info before + using this. + +-Added Trigger Holdoff function. Works in single screen buffer and Normal modes only (not + in Auto), up to 1Ms/div. (Inability of screen updates to keep up with data flow destroys + timing integrity at faster timebases, making added delay meaningless) Hold left toggle + center button, "T" indicator appears in buffer view area at bottom of screen in color of + triggering channel when activated. Indicator will be greyed out in unsupported modes and + time bases. Position of indicator shows amount of delay. Use TRIGG menu: source>type>level> + delay to change delay time. Move left toggle left or right in steps of one major screen + division to change delay. + +-Added HOLD mode for V max and V min. Max/Min meters in this mode hold maximum/minimum + values until reset. Function reads samples from all buffer transfers. Max and Min meter + items will be white in this mode as an indicator. Value will show source color. "H" also + shows on menu. Alarm function is also activated in this mode, when voltage exceeds V1 + vernier or drops below V2 vernier device sounds alert. Change source channel for alarms + with DeltaV and left toggle. (Move verniers to extreme top/bottom to shut off alarms). + Hold center right toggle menu selector to toggle hold mode. Reset with RUN/HOLD or by + changing Ypos, volt range or buffer size. When using with cursor defined meters mode, + readings and alarms are confined to between T1 and T1 cursors. + +-Trigger cursor can now be moved towards the left edge of screen in single window buffer + mode. Use "Xpos" in time base menu to move. + +-Improved accuracy, range and resolution of period/frequency meters. Frequency and Period + meter code completely re-written using more accurate computations with more digits of + resolution under all conditions and proper rounding off. + +-Added quantization error compensation for period and frequency meters using the analog + channels. Provides increased resolution for most waveforms, specially at low sample counts + such as in single frame buffer mode or using cursor defined meters. Depends on calculating + slope while crossing trigger points so waveforms with very sharp risetimes (=1 time sample + period for example) and waveforms very slowly crossing the trigger point will benefit less. + +-Incorporated all samples captured in calculations for all meters. Meters now read average + from all previous frames since last readout, rather than just the last frame before readout. + Helps out particularly at the faster timebases. The slower timebases (<5mS/div) will benefit + less from this as meter refresh rates start catching up with frame rates as the timebase is + set to slower values and fewer or no samples are lost to begin with. + +-Added ability to automatically compensate for battery voltage/ac power supply affecting + voltage calibration and DC offsets. Requires calibration to be done twice, once with a + somewhat low battery charge and then again with AC adapter connected. Program with save + the 2 sets of parameters for all ranges and will interpolate/extrapolate as necessary while + battery voltage/power supply changes. + +-Improved resolution of voltage calibration. Calibration now provides 4 digits of display + resolution as well as an indicator to set input reference voltage to the exact middle of + an ADC step, providing some effort to make the best of the limited 8 bits of resolution. + Voltage calibration now starts off from previous entries, rather than 0. This also allows + calibrating offsets (with auto calibration) without having to also calibrate voltage ranges + manually (move right toggle through range fields leaving whatever residual readings are + there and previous V cal settings will remain). + +-Changed Trigger Select shortcut (Center short press left toggle). Now if only 1 or 2 + channels are turned on, simply toggles trigger source between them. If A and B channels + are on, will also cycle through A&B trigger mode. If 3 or more channels are on, serves as + a shortcut to TRIGG>SOURCE and doesn't change anything. Previously a channel had to have + it's menu active (flashing) to set triggering to it by pressing this button. + +-Selective updating: Eliminates waveform disturbances, particularly at the lower timebases + (<500uS/div) while changing X pos, Y pos, trigger level, cursors and menu/item changes. + Program will now only change functions relevant to items being adjusted, rather than + updating everything each time a button is pushed. + +-Added ability to shut off standby timer while using battery, also ability to force device + into standby. + +-Fixed incorrect values in CSV file export, did not compensate for shifted ADC values. + +-Changed interpolation routine to more accurately represent the values in the buffer for + rising and falling edges, IP routine for the fastest timebases was modifying display at + all timebases. + +-Various other minor interface changes (Colors, alignment and movement of trigger cursor, + notifications, meter item selection) and fixes (dropped pixels, bug fixes, etc.) + +USING MULTIPLE CONFIGURATION FILES: + To prevent file corruption when using one of the original system versions, which are known + to corrupt saved files, the program will not write additional config files (other than the + regular #0 boot file) unless one already exists. In order to create these, the files already + on the drive should be first saved to a Windows machine, the drive should then be formatted, + and then the XXXXX.WPT file copied back first to the formatted drive, then the .BAK file. 9 + copies of the WPT file should then be made and renamed CONF001.CFG through CONF009.CFG and + copied to the device's drive before any other files are copied or created. This will ensure + that these small files stay at the beginning of the file allocation table, where they will + not get corrupted. Their small size requires no chaining info to be written to the FAT, so + their entries remain small, avoiding corruption which seems to occur only further down the + FAT. + Additional values are stored in the config files in a way that should be compatible with + older versions. A new config file though must be saved to hold settings for the added or + modified functions and the calibration values. + +CALIBRATION: + Recalibration will be necessary. This version works a bit differently than previous versions + so old settings probably will not be very accurate. When calibrating, try to center the + "step center" indicator by adjusting the voltage source. This is very sensitive so a way to + finely adjust the voltage will be necessary. If the indicator jumps around too much, there + likely is too much noise superimposed on the calibration voltage. Look at the signal with + the scope display, there should be a minimum of background noise. Nearby switched mode power + supplies and the like may need to be switched off. Changing the source a bit to find another + "step" can get rid of excessive noise, otherwise center the indicator as best as possible. + At the beginning of the calibration routine, a compensation value (in PPM) can be entered to + improve accuracy of the frequency and period meters. Generator output is set to 1Mhz at this + point and if connected to a frequency counter the error can be entered and will be used to + calibrate these meters. + + As the battery or AC adapter voltage changes, the DC offsets and voltage calibration are + affected somewhat. This version will now allow setting 2 different sets of calibration + tables. One can be done with a relatively low battery (say around 1/4 charge) and a second + set with a charger connected, which brings the supply voltage to around 4.3- 4.5V. Once + this is done the program will interpolate from the 2 and be able to correct the calibration + as the battery voltage changes, or if an AC adapter is used. + +>>> For a quick set up voltage calibration can be skipped and the calibration routine left + to auto calibrate (twice if bat level comp is desired). Skip through voltage calibration + fields without applying any input, leaving whatever residual values are there. Note that + any previously calibrated voltage values picked while booting up or loading CFG file #0 + will remain. This will at least remove undesirable DC offsets on each range and prevent + shifts of offsets as Y positions are changed. + + + + + +CHANGELOG FOR REVISION W: + +- Variable repeat rate for toggles, slow for menus, fast for verniers, etc. +- Main Menu will stop at left (CH-A), and at right on Time Vernier or Volume adj, will not + "go around". +- Program will attempt to set triggering to relevant channel, if shutting off a channel with + trigg set, will move trigger source to last selected ch. +- Will not time out into standby if USB power plugged in. +- "SCAN" mode renamed "TrOFF". Trigger levels/vernier do not show in this mode. +- "NorCL" (Normal-Clear) mode added (simulates regular CRT type scope, clears display if no + trigger) +- Single shot trigg mode automatically goes into full size buffer mode. +- Digital channels meter default displays changed to show only relevant meters (no volt meters) +- 20Khz Generator output shifted to 25Khz so 72 point sampling can work without special Sys + version. +- Trigg verniers disabled for digital channels (preset at 1/2) +- X_Y-A and X_Y-S removed, now only X_Y. Mode is triggered in AUTO mode to allow meters to + work correctly. (Move trigg source to unused ch to disable triggering if desired). + + +FIXES, MODIFICATIONS AND ADDITIONS: (List of most important issues, many others not listed) + +TRIGGERING: +- Re-sequencing of triggering functions to allow proper time for reset to bring up start flag + before attempting to read FIFO, allows analog channels to trigger properly on slow/random + signals at fastest timebases. +- Fixed a problem in the mid-range time bases where display would freeze or trigger very + sporadically. +- Implementation of proper triggering in single screen buffer mode. +- Integration of JackTheVendicator's single shot trigger mode. +- Various functions optimizing triggering for different timebases, triggering modes, etc. +- "SCAN" mode (now renamed "TrOFF") optimized with different routines for fast and slow time + bases. +- Single screen buffer mode now resets immediately after right edge of screen, also is + available at all time bases. +- Auto trigger fix to eliminate condition in some cases where device could not trigger + because trigg level was too far away from wave and auto function could not find wave + because device was not triggering. + +CALIBRATION: +- Gain calibration now modifies signal in relation to signal zero point, rather than screen + bottom. Prevents interfering with offset calibration and Y positioning. +- Signed variables now used to allow values at bottom of screen, which can be pushed up by + offset calibration, and then be below zero, to be read properly. +- ADC operating point shifted away from non-linearity at the bottom of screen. Allows + calibration routine to work more accurately. +- Fix for an error in FPGA where the 2 least significant bits of CH-B are swapped. +- Fix for an error in saving parameters to disk where CH-B offset compensation could be + corrupted if CH-A's value was negative. +- Signal gain calibration now switchable ON/OFF (Screen only, does not affect meters. + Improves wave quality by removing correction "steps", if present). + +FILES: +- Fixed BMP header. Header was missing a row of digits causing improper file and image size + to be listed. +- Added several additional parameters to be saved in "save config". (Config file still + compatible with previous versions) + +METERS: +- Values now corrected by calibration in reference to signal zero point, rather than screen + bottom. Prevents offsets and Y positioning from affecting accuracy. +- Time measurements in process completely re-written, eliminating the inclusion of partial + waves before triggering. While this only affected accuracy slightly in full frame buffer + mode, it introduced major inaccuracies in single screen buffer mode where at times only + a few waveforms are considered in the measurements. +- Frequency meter fixed so it works past ~2Mhz. This worked OK in original program, but + had wrong suffix. Subsequent fix for improper readout caused meter to malfunction past + around 2Mhz. +- Fixed Time and Voltage Vernier meter readouts so they display properly at very large and + very small time/voltage settings. + +GENERATOR: +- Shifting of amplitude variation from signal's zero point rather than screen bottom, + eliminates distortion at lower levels where bottom of wave is clipped. Note that this + results in an unchanging DC offset as level is varied... (use AC coupling to display + properly) +- Changed division ratios so proper frequency is produced/displayed without needing a + special SYS version (should work OK with it as well) Only issue with this is the + innability to produce 20Khz (produces 25Khz instead) Readout shows correct value. + +DISPLAY +- Improved linearity from ADC operating point shift. (Eliminates compression of wave at + bottom of screen). +- Bit swap correction on CH-B improves trace quality. +- Elimination of noise at beginning and end of trace on some ranges. +- Alignment of Digital channels with Analogs. Note that digital channels trailing at very + fast timebases is caused by delay introduced in Digital channel input stage. There is + no way to fix this at the software level, needs to be fixed in hardware. This same + input stage configuration also introduces instabilities when triggering from the + digital CHs at fast time bases. +- Brighter screen grid (was very faint...) +- Re-aligned trigger point with trigger vernier +- Fixed "time shift" at fastest timebases when changing time/div while on hold. + + +PREVIOUS REVISIONS: + + +DSO203 GCC v1.7 APP +------------------- + +Just some fixes over marcosin 1.8 version of the DSO203 APP and GCC compilation support. + +(Win32 GCC support by gabonator1) + + +Contribute or simply enjoy. + +Pedro Simões + +------------------------------------------- + +Access source in github: + https://github.com/pmos69/dso203_gcc + +or get a zip with the complete tree here: + https://github.com/pmos69/dso203_gcc/zipball/master + +------------------------------------------- + +Uses CodeSourcery Arm toolchain: + https://sourcery.mentor.com/sgpp/lite/arm/portal/release1802 +Just download the Windows TAR archive and unpack it somewhere, no installation is required. +Watch out for symlinks in the TAR you'll have to re-create them or copy/rename files to "fill the gaps" + +------------------------------------------- + +All thanks to: +- Seeed-Studio +- Marco Sinatti (marcosin) +- Gabriel Valky (gabonator1) + +------------------------------------------- + +v1.7 +- Fixed x10 probe modes - Division scales and meter values +- Calibration accuracy fix + +v1.6 +- Fixed X_Y modes - now operational again +- Fixed Min, Max and Vpp readings (initialization values) + +v1.5 +- Re-did a complete code merge of marcosin 1.8 & fixes into 2.51 by hand. - Now compiles with -Os +- X_Y modes don't work, and mess the buffer - Reset needed to proceed after using X_Y. + +v1.4 +- changed compile options: "-O3" replaced by "-O0 -fno-common -fzero-initialized-in-bss" +- removed explicit initialization of the FrameMode variable + +v1.3 +- initialized FrameMode variable at creation + Can now start correctly everytime. (at least on my DSO) + If you have problems with bogus display in full-buffer mode, try saving settings and restarting. + +v1.2: +- automatic chinese->english translation of all chinese comments in the source. + +v1.1: +- Updated with marcosin 1.8 release + +v1: +- Removed -fno-common and changes -Os to -O3 in compile options + APP still only starts correctly 1/3 of the times +- Fixed Vdc and RMS values display when in 1-page buffer mode (menu.c) + Calculation didn't take into account the buffer size when calculating the averages +- Fixed wrong calculations for Vdc and RMS (process.c) + the counters (a_Avg, b_Avg, a_Ssq, b_Ssq) were initialized with a value different than 0) + + +------------------------------------------- + +Marco Sinatti (marcosin) Revisions: + +Versione APP251_V1.0 Richiede FPGA V2.22 - SYS1.50 +-Tasto quadrato = Abilita il buffer ridotto a una schermata, disabilita lo scorrimento +-Tasto triangolo = cambio visualizzatori misure +-Corretto visualizzazione unità di misura della frequenza + +Versione APP251_1.1 Richiede FPGA V2.22 - SYS1.50 +-Aggiunto opzione portata x10 in modo da leggere la tensione corretta sui meter quando si utilizza la sonda x10 +-Aggiunto accesso veloce ai cursoti V1 V2 T1 T2 in modo da poter andare direttamente a fare misure senza scorrere tutti i menù. Premendo il tasto si accede a V1, ripremendolo a V2, etc... dopo T2 si torna alla posizione da cui si era partiti +-Aggiunto livello trigger automatico, si setta da solo al centro della forma d'onda, il tasto è comodo anche per accedere al volo al menù trigger +-Aggiunto indicatore della batteria in carica, mentre stà caricando il riempimento della batteria scorre +-Tolto la modalità NONE sulla base dei tempi, perchè era identica a SCAN +-Modificato l'indicazione dell'impostazione a frame singolo, adesso viene evidenziata con un rettandolo sull'indicatore del buffer in basso +-Migliorata l'acquisizione a frame singolo che lavorava male in alcune portate + +Versione APP251_1.3 Richiede FPGA V2.22 - SYS1.50 +-Visualizzazione a schermo intero nascondendo i meter +-Durante l'uso dei cursori, se i meter sono nascosti appare comunque il DeltaT e il DeltaV +-Risolto bug sulla visualizzazione della linea che appare sui primi pixel dello schermo +-Risolto bug aggiornamento livello trigger automatico +-Nella modalità trigger automatica si può decidere di impostare in automatico il livello a 1/2 1/4 3/4 della Vpp +-Modificato visualizzazione carica batteria con scorrimento quando effettivamente è in carica +-Aumentato velocità di scorrimento dei cursori di misurazione +-Modificato modalità di riduzione del buffer, adesso quando siamo in "frame singolo" in realtà lavora così: +SCAN = cattura e visualizza un solo frame, purtroppo non è un roll vero +NON SCAN = cattura 1,6 frame, in questo modo il trigger funziona bene, si ha la possibilità di scorrere la visualizzazione +-In modalità SCAN non si hanno più deformazioni della forma d'onda al centro dello schermo +-In modalità SCAN tolgo il riferimento della XPOS perchè non serve +-Aggiunto modalità PWM e regolazione ampiezza segnale in uscita, modificando il generatore di funzioni in questo modo: +SQUARE = Onda quadra da 0Hz-20Khz con ampiezza regolabile da 0 a 2,6V +TRIANG = Onda triangolare da 0Hz-20Khz con ampiezza regolabile da 0 a 2,6V +SEW = Onda a dente di sega da 0Hz-20Khz con ampiezza regolabile da 0 a 2,6V +SINUS = Onda sinusoidale da 0Hz-20Khz con ampiezza regolabile da 0 a 2,6V +PWM = Segnale PWM con duty regolabile da 0 a 100 %, frequenza da 10Hz a 8Mhz. + +Versione APP251_1.4 Richiede FPGA V2.22 - SYS1.50_1.6 +-Funzione X_Y (da terminare) +-Cambio rapido menù meter modificato, adesso con i canali C e D ad OFF quando si cambia i meter non li imposta sui canali disabilitati +-Sistemato SYS per il problema del range tensione +-Sistemato SYS sul menù calibrazione +-Rimodificato singolo frame, quando impostato non fa scorrere XPOS + +Versione APP251_1.5 Richiede FPGA V2.22 - SYS1.50_1.6 +-Corretto visulizzazione DeltaV quando X10 sul canale B (prendeva sempre il canale A) + +Versione APP251_1.6 Richiede FPGA V2.22 - SYS150_1.6 +-Modalità SCAN a singolo frame in vero ROLL +-Aggiunto 1-2-5Hz su generatore +-Portato frequenza massima generatore a 50Khz +-Aumentato da 36 a 72 campionamenti la generazione delle forme d'onda + +Versione APP251_1.7 Richiede FPGA V2.22 - SYS150_1.6 +-Invertito titolo generatore e tempo base +-Spostato meter duty e tensione generatore +-Implementato XY_S (scan) XY_A (auto) da terminare +-NORMAL migliorato, non cancella lo schermo quando attende un nuovo trigger +-------------- +Versione APP251_1.8 Richiede FPGA V2.22 - SYS150_1.6 +-Migliorato griglia e sistemato scala su modalità XY + + + + + + + + + + diff --git a/User Guide V5.6-6.5.pdf b/User Guide V5.6-6.5.pdf new file mode 100644 index 0000000..52a9fcf Binary files /dev/null and b/User Guide V5.6-6.5.pdf differ diff --git a/W1.1 FPGA/281_FPGA.BIN b/W1.1 FPGA/281_FPGA.BIN new file mode 100644 index 0000000..0881b23 Binary files /dev/null and b/W1.1 FPGA/281_FPGA.BIN differ diff --git a/W1.1 FPGA/AddrCtrl.v b/W1.1 FPGA/AddrCtrl.v new file mode 100644 index 0000000..b1fe187 --- /dev/null +++ b/W1.1 FPGA/AddrCtrl.v @@ -0,0 +1,106 @@ + /********************* (C) COPYRIGHT 2011 e-Design Co.,Ltd. ******************** + Pre-sampling FIFO address counter and control module + Version : FPGA CFG Ver 2.x Author : bure +*******************************************************************************/ +module AddrCtrl (Counter, OS_Size, FreeRun, ClrW, Wclk, Start, nRclk, RE, H_L, PerCnt, // Depth, PerCnt, Delay, + Ready, Sampled, Full, Empty, Wptr, Rptr); + + input [15:0]Counter;// Oversampling mode OS sample counter + input [15:0]OS_Size;// Oversampling mode OS factor + input FreeRun; // Flag for non triggered synchronized free running AUTO timebase mode + input ClrW; // Wr addr cnt rst -> Active high + input Wclk; // Wr clock -> rising edge + input Start; // Sync start -> active high + input nRclk; // Rd clock -> falling edge + input RE; // Rd cnt enable -> active high + input H_L; // Data output select -> 1/0: [17:16]/[15: 0]Dout->[15:0]DB + input [15:0]PerCnt; // Pre-sampling counter + + output Sampled; // Pre-sampling finish -> active high + output Ready; // Sampling start -> active high + output Full; // FIFO RAM is full -> active high + output Empty; // FIFO RAM is empty -> active high + output [11:0]Wptr; // written address pointer + output [11:0]Rptr; // Read address pointer + + reg Full; + reg Ready; + reg Loaded; // marked the Start address loaded ok + reg [11:0]Wptr; + reg [11:0]Rptr; + reg [12:0]Pcnt; + reg [11:0]Bptr; + reg [1:0]DelayCnt; + reg Sampled; + reg Empty; + + always@ ( posedge Wclk or posedge ClrW ) begin + if ( ClrW ) begin + Full <= 0; + Pcnt <= 0; + Sampled <= 0; + DelayCnt <= 2'b00; + Ready <= 0; + end else begin + + if ((Empty)&&(!Start)&&(FreeRun)) begin + Sampled <= 0; + Full <= 0; + Pcnt <= 0; + Wptr <= 0; + end + + if ((Start)&&(DelayCnt<3))begin + if(Counter==0)DelayCnt <= DelayCnt+1; + end + + if ( Pcnt >= PerCnt ) Sampled <= 1; + + if (!Full) begin + if(OS_Size)begin + if(Counter<2)Wptr <= Wptr + 1; + end else Wptr <= Wptr + 1; + end + + if(OS_Size)begin + if(Pcnt>=2047)begin + if ((FreeRun==0)||(Start==1)) Full <= Ready; else Full <= 1; + end else if(Counter>=OS_Size)Pcnt <= Pcnt +1; + end else begin + if ( Pcnt >= 4095 )begin + if ((FreeRun==0)||(Start==1)) Full <= Ready; else Full <= 1; + end else Pcnt <= Pcnt +1; + end + + if( (!Start )&&(FreeRun==0)&&(Pcnt >= PerCnt) ) Pcnt <= PerCnt; + + if ( DelayCnt == 1 ) begin + if(Counter==0)begin + Ready <= 1; + Bptr <= Wptr; + Pcnt <= PerCnt; + end + end + + end + end + + always @ (Rptr or Wptr) if ( Rptr == Wptr ) Empty <= 1; else Empty <=0; //read/write "splice" + + always @( posedge nRclk or posedge ClrW ) begin + if ( ClrW ) begin + Loaded <= 0; + Rptr <= 0; + end else begin + if ( ( H_L ) && RE && (~Loaded) && (Start) )begin + Loaded <= 1; + if(OS_Size)Rptr<=Bptr-(PerCnt*2); + else Rptr<=Bptr-PerCnt; + end else if ( H_L && RE ) Rptr <= Rptr + 1; + end + end + +endmodule + + + diff --git a/W1.1 FPGA/DP_RAM.v b/W1.1 FPGA/DP_RAM.v new file mode 100644 index 0000000..58e3e5c --- /dev/null +++ b/W1.1 FPGA/DP_RAM.v @@ -0,0 +1,82 @@ +/********************* (C) COPYRIGHT 2011 e-Design Co.,Ltd. ******************** + 4096 * 18Bits dual-port SRAM module + Version : FPGA CFG Ver 2.x Author : bure +*******************************************************************************/ + +module DP_RAM ( OS_Size, Din, Wclk, nRclk, Waddr, Raddr, Dout, Counter, A, B, CD ); + + input [15:0]OS_Size; // Oversampling factor control + input Wclk; // Wr clock -> rising edge + input nRclk; // Rd clock -> falling edge + input [11:0]Waddr; // written address + input [11:0]Raddr; // read address + input [17:0]Din; // input data + output [17:0]Dout; // output data + output [15:0]Counter; + output [7:0]A; // Output buffered input channel data to triggering (signal) section + output [7:0]B; + output [1:0]CD; + reg [15:0] Counter; // Oversampling mode sample counter + reg [7:0] ACC_A[1:0]; // Data accumulator/transfer + reg [7:0] ACC_B[1:0]; // Data accumulator/transfer + reg [17:0] Dout; // Data out/high level output + reg [17:0] Mem_data [4095:0]; + reg [17:0]TrigBuf[3:0] /* synthesis syn_noprune=1 */; // Trig buffer, holds 4 last ADC values + reg [1:0]TrigBufAddr; // 2 bit Trig buffer address, holds index to 4 TrigBuf subscripts + + reg [1:0] Multi; // Holds either chC/D or Oversampling index flag + reg [7:0]A; + reg [7:0]B; + reg [1:0]CD; + + always @( posedge Wclk ) begin + TrigBuf[TrigBufAddr]<=Din; //load latest data from ADC into 4 sample buffer + TrigBufAddr <= TrigBufAddr+1; + A<=TrigBuf[TrigBufAddr-2][ 7:0]; //Used for both triggering and data transfer + B<=TrigBuf[TrigBufAddr-2][15:8]; + CD<=TrigBuf[TrigBufAddr-2][17:16]; + + if(Counter<2)begin //in OS mode, writes 0-1 data sequence, kept at 0 in non OS mode + if(OS_Size)begin //OS_Size>0 denotes oversampling mode on + Multi<= 2'b01; //Reset Multi synch flag for OS lo/hi data (active low) + end else Multi<=CD; //if in non OS mode, use to carry ch C/D data + Mem_data[Waddr]<= {Multi,ACC_B[Counter],ACC_A[Counter]}; //load low, high data sequentially + end + + if(OS_Size)begin + if(Counter>=OS_Size)begin //Load OS data + Counter<=0; //Reset + Multi<=2'b00; //Synch flag for program (low active) + end else Counter<=Counter + 1; //Advance counter in OS mode + end else begin + Counter<=0; //Keep at 0 for non OS modes + end + + if(Counter==0)begin //reset to first acquired samples + ACC_A[0]<=A; //Also used for transfer in non OS modes + ACC_B[0]<=B; + end else begin + if(Counter==1)begin + if(A>ACC_A[0])ACC_A[1]<=A; //load highest of 2 first samples in high ACC as reset + else ACC_A[1]<=ACC_A[0]; + if(B>ACC_B[0])ACC_B[1]<=B; + else ACC_B[1]<=ACC_B[0]; + end else begin //Update accumulators + if(A>ACC_A[1])ACC_A[1]<=A; + if(B>ACC_B[1])ACC_B[1]<=B; + end + if(A Active high + input MCI; // Main clock input -> rising edge + input nRD; // FIFO read clock -> falling edge + input CE; // FIFO bus enable -> Active high + input H_L; // 1 = [17:16]Dout->[ 1:0]DB, 0 = [15:0]Dout->[15:0]DB + input C_D; // 1 = [15:0]Data->[15:0]DB + input SCK; // Serial input clock -> rising edge + input SDA; // Serial input data + input [17:0]Din; // FIFO write data + + output nPD; // ADC Power down Output + output CKA; // Clock_A + output CKB; // Clock_B + + inout [15:0]DB; // FIFO output data bus + + wire [11:0]R_Addr_Bus; // current read address + wire [11:0]W_Addr_Bus; // current Writen address + wire [17:0]Dout_Bus; // Internal data output Bus + wire [17:0]Din_Bus; // Internal data input Bus + wire [ 7:0]Tm_Link; + wire [ 7:0]Vt_Link; + wire [ 31:0]Tt_Link; + wire [ 7:0]Ctrl_Link; + wire Start_Link; + wire Full_Link; + wire Empty_Link; + wire Sampled_Link; + wire Ready_Link; + wire [15:0]PerCnt_Link; + wire FreeRun_Link; + wire [15:0]OS_Size_Link; + wire [15:0]Counter_Link; + wire [7:0]A_Link; + wire [7:0]B_Link; + wire [1:0]CD_Link; + + assign Din_Bus = { Din[17:16], ~Din[15:8], ~Din[7:0] }; + assign CKA=MCI; + assign CKB= (Ctrl_Link[1]) ? !MCI : MCI; + + AddrCtrl U1( + .Counter(Counter_Link), + .OS_Size(OS_Size_Link), + .FreeRun (FreeRun_Link), + .ClrW( ClrW ), + .Wclk( MCI ), + .Start( Start_Link ), + .nRclk( nRD ), + .RE( CE ), + .H_L( H_L ), + .PerCnt( PerCnt_Link ), + .Ready( Ready_Link ), + .Sampled(Sampled_Link), + .Full( Full_Link ), + .Empty( Empty_Link ), + .Rptr( R_Addr_Bus ), + .Wptr( W_Addr_Bus ) + ); + + DP_RAM U2( + .OS_Size(OS_Size_Link), + .Wclk( MCI ), + .nRclk( nRD ), + .Din( Din_Bus ), + .Raddr( R_Addr_Bus ), + .Waddr( W_Addr_Bus ), + .Dout( Dout_Bus ), + .Counter(Counter_Link), + .A(A_Link), + .B(B_Link), + .CD(CD_Link) + ); + + Signal U3( + .Reset( ClrW ), + .Mclk( MCI ), + .Trigg_Mode( Tm_Link ), + .Vthreshold( Vt_Link ), + .XTthreshold( Tt_Link ), + .A(A_Link), + .B(B_Link), + .CD(CD_Link), + .Sampled(Sampled_Link), + .Start( Start_Link ) + ); + + IO_Ctrl U4( + .CE( CE ), + .nRD( nRD ), + .SCK( SCK ), + .SDA( SDA ), + .Dout( Dout_Bus ), + .Start( Start_Link ), + .Full( Full_Link ), + .Empty( Empty_Link ), + .H_L( H_L ), + .C_D( C_D ), + .Ready( Ready_Link ), + .PerCnt( PerCnt_Link ), + .nPD( nPD ), + .Trigg_Mode( Tm_Link ), + .Vthreshold( Vt_Link ), + .XTthreshold( Tt_Link ), + .CtrlReg( Ctrl_Link ), + .DB( DB ), + .FreeRun (FreeRun_Link), + .OS_Size(OS_Size_Link) + ); + +endmodule + \ No newline at end of file diff --git a/W1.1 FPGA/IO_Ctrl.v b/W1.1 FPGA/IO_Ctrl.v new file mode 100644 index 0000000..c46703c --- /dev/null +++ b/W1.1 FPGA/IO_Ctrl.v @@ -0,0 +1,89 @@ +/********************* (C) COPYRIGHT 2011 e-Design Co.,Ltd. ******************** + Input & output control module + Version : FPGA CFG Ver 2.x Author : bure +*******************************************************************************/ + +module IO_Ctrl(CE, nRD, SCK, SDA, Dout, Start, Full, Empty, H_L, C_D, Ready, + PerCnt, nPD, Trigg_Mode, Vthreshold, XTthreshold, CtrlReg, DB, FreeRun, OS_Size); + + input CE; // Databus selece enable -> Active high + input nRD; // Databus read enable -> Active low + input SCK; // Serial input clock -> rising edge + input SDA; // Serial input data + input [17:0]Dout; // Output data + input Start; // Sync start -> active high + input Ready; // Sampling start -> active high + input Full; // FIFO RAM is full -> active high + input Empty; // FIFO RAM is empty -> active high + input H_L; // 0/1 = Status/[15:0]Din -> [15:0]DB + input C_D; // 1 = [15:0]Data -> [15:0]DB + + output [15:0]PerCnt; // Per-sampling counter + output nPD; // ADC power down -> Active low + output [ 7:0]Trigg_Mode; // Trigger Mode + output [ 7:0]Vthreshold; // Trigger voltage threshold + output [ 31:0]XTthreshold; // Trigger time threshold + output [ 7:0]CtrlReg; // bit0=nPD, bit1=Mode, + inout [15:0]DB; // Data bus to MCU + output FreeRun; + output [15:0]OS_Size; + + reg [ 7:0]Trigg_Mode; // Trigger Mode + reg [ 7:0]Vthreshold; // Trigger voltage threshold + reg [ 31:0]XTthreshold; // Trigger time threshold + reg [ 7:0]CtrlReg; + reg [ 7:0]RegAddr; + reg [ 7:0]DataBuff; + wire [15:0]DB_Mux ; + reg [ 7:0]Select; + wire [15:0]CD_Mux ; + reg [15:0]PerCnt; + reg [15:0]Data/* synthesis syn_preserve=1 */; + reg FreeRun; + reg [15:0]OS_Size; + + assign nPD = CtrlReg[0]; + assign CD_Mux = C_D ? Data[15:0] : { 10'h000, Start, Empty, Full, Ready, Dout[17:16] }; //Program uses Ready (2) as start flag + assign DB_Mux = H_L ? Dout[15:0] : CD_Mux; + assign DB = ( CE && !nRD ) ? DB_Mux : 16'hzzzz ; + + always @(posedge SCK) begin + DataBuff = { DataBuff[6:0], SDA }; + end + + always @( posedge SDA ) begin + if ( !SCK ) begin + if ( H_L ) begin + RegAddr = DataBuff; + case(Select) + 8'h00: Data<={8'h57,8'h31}; //For FPGA version ID: Ascii chars "W1" identifies revised fpga + 8'h01: Data<= 16'h0101; //Sub-version, identifies updates + default: Data<=0; + endcase + + end else begin + case( RegAddr ) + 8'h00: begin + Trigg_Mode = DataBuff; + PerCnt = 150; + end + 8'h01: Vthreshold[ 7:0] = DataBuff; + 8'h02: XTthreshold[ 7:0] = DataBuff; + 8'h03: XTthreshold[15:8] = DataBuff; + 8'h04: CtrlReg [ 7:0] = DataBuff; + 8'h05: Select [ 7:0] = DataBuff; + + 8'h08: PerCnt [ 7:0] = DataBuff; + 8'h09: PerCnt [15:8] = DataBuff; + + 8'h0E: FreeRun = DataBuff[0]; + 8'h0F: OS_Size [ 7:0] = DataBuff; + 8'h10: OS_Size [15:8] = DataBuff; + 8'h11: XTthreshold[23:16] = DataBuff; + 8'h12: XTthreshold[31:24] = DataBuff; + endcase + end //if H_L, else + end //if (!SCK) + end //always @(posedge SDA) + +endmodule \ No newline at end of file diff --git a/W1.1 FPGA/Pins.pcf b/W1.1 FPGA/Pins.pcf new file mode 100644 index 0000000..7d8d97c --- /dev/null +++ b/W1.1 FPGA/Pins.pcf @@ -0,0 +1,45 @@ +set_io CE P1 +set_io nRD P10 +set_io DB\[2\] K12 +set_io DB\[1\] P2 +set_io DB\[0\] P3 +set_io DB\[15\] P4 +set_io DB\[14\] P5 +set_io DB\[13\] P7 +set_io DB\[11\] N14 +set_io DB\[12\] P14 +set_io DB\[10\] M12 +set_io DB\[9\] L12 +set_io Din\[17\] M3 +set_io Din\[16\] K3 +set_io DB\[8\] L14 +set_io DB\[7\] K14 +set_io DB\[6\] H12 +set_io DB\[5\] G12 +set_io DB\[3\] J12 +set_io DB\[4\] G14 +set_io MCI P8 +set_io ClrW E14 +set_io H_L E12 +set_io C_D D14 +set_io SDA C14 +set_io SCK D12 +set_io nPD N1 +set_io CKB L1 +set_io Din\[15\] J1 +set_io Din\[14\] H1 +set_io Din\[13\] G1 +set_io Din\[12\] E1 +set_io Din\[11\] D1 +set_io Din\[10\] C1 +set_io Din\[9\] B1 +set_io Din\[8\] A1 +set_io Din\[3\] D7 +set_io Din\[4\] A6 +set_io Din\[6\] A4 +set_io Din\[7\] A3 +set_io Din\[5\] A5 +set_io CKA A2 +set_io Din\[1\] A11 +set_io Din\[0\] A10 +set_io Din\[2\] A12 \ No newline at end of file diff --git a/W1.1 FPGA/README.TXT b/W1.1 FPGA/README.TXT new file mode 100644 index 0000000..f5d1e55 --- /dev/null +++ b/W1.1 FPGA/README.TXT @@ -0,0 +1,46 @@ +FPGA version W1.1: +Revised FPGA for HARDWARE VERSION 2.81 and later devices ONLY. +>NOT compatible with previous HW versions + +Compatible with all SYS and program versions. +Instal by first copying the FPGA_281.ADR file to DFU virtual disk. +When volume reappears, copy 281_FPGA.BIN to DFU virtual disk. + +Based on an earlier published version (V2.50) + + +CHANGELOG TO VERSION FPGA W1.1: + + -Added oversampling mode support, access by sending a >0 OS_Size to + Set_ 0x0F and 0x10 addresses as lo/hi word bytes. Compatible with + previous programs with OS_Size=0. + + -Moved triggering buffer to the RAM module and included data transfer + to go through buffer as well. + + -Increased time trigger variable from 16 to 32 bits to work properly with + oversampling mode. 2 most significant added bytes transfered with Set_ 0x11 + and 0x12. Value sent needs to be multiplied by OS_Size+1. + + -Removed unused set_ sampling depth and delay to improve timing performance. + Any calls made to these will simply be disregarded. To my knowledge no + program uses these. + + +CHANGELOG TO VERSION FPGA W1: + -Added triggering data buffer so that calculations can be made from a + stable source rather than on the fly which requires critical timing, + possibly resulting in read/write collisions and corruption of triggering + data at the fastest timebases. + + -Extended time triggering accumulators from 12 bits to 32 bits, allows + detection of much longer time intervals for proper triggering functions + under these conditions. + + -Added freerun mode for more coherent waveform displays while untriggered + in AUTO mode at the faster timebases. + + -Eliminated unused meter data accumulators. To my knowledge no program + uses these, but rather performs the calculations externally. + + -Added ID string access so programs can indentify new version. \ No newline at end of file diff --git a/W1.1 FPGA/Signal.v b/W1.1 FPGA/Signal.v new file mode 100644 index 0000000..fab444e --- /dev/null +++ b/W1.1 FPGA/Signal.v @@ -0,0 +1,224 @@ +/********************* (C) COPYRIGHT 2011 e-Design Co.,Ltd. ******************** + Sync signal select and control module + Version : FPGA CFG Ver 2.x Author : bure +*******************************************************************************/ +module Signal( Reset, Mclk, Trigg_Mode, Vthreshold, XTthreshold, A, B, CD, + Sampled, Start); + + input Reset; // Trigger status rst -> Active high + input Mclk; // main clock + input [ 7:0]Trigg_Mode; // Trigger Mode + input [ 7:0]Vthreshold; // Trigger voltage threshold + input [31:0]XTthreshold; // Trigger time threshold + input [7:0]A; // Buffered inputs + input [7:0]B; + input [1:0]CD; + input Sampled; // Signals end of pre-trigger sampling + + output Start; // Sync start -> Active high + reg Start; + + wire [ 8:0]Delta_V1; + wire [ 8:0]Delta_V2; + wire [ 8:0]Delta_V3; + wire [ 8:0]Delta_V4; + + reg A_Flag; + reg A_Dt_L; + reg A_Dt_H; + reg A_Ut_L; + reg A_Ut_H; + reg [31:0]A_Cnt; //runs continuously while untriggered, using 32 bit reg instead of 12 bit to extend range + + reg B_Flag; + reg B_Dt_L; + reg B_Dt_H; + reg B_Ut_L; + reg B_Ut_H; + reg [31:0]B_Cnt; + + reg C_Flag; + reg C_Dt_L; + reg C_Dt_H; + reg C_Ut_L; + reg C_Ut_H; + reg [31:0]C_Cnt; + + reg D_Flag; + reg D_Dt_L; + reg D_Dt_H; + reg D_Ut_L; + reg D_Ut_H; + reg [31:0]D_Cnt; + + reg A_Hi; + reg A_Lo; + reg B_Hi; + reg B_Lo; + reg A_Rise; + reg A_Fall; + reg B_Rise; + reg B_Fall; + + assign Delta_V1[8:0] = (Vthreshold[7:0] + 12); + assign Delta_V2[8:0] = (Vthreshold[7:0] - 12); + assign Delta_V3[8:0] = (Vthreshold[7:0] + 1); + assign Delta_V4[8:0] = (Vthreshold[7:0] - 1); + + always @( posedge Mclk or posedge Reset ) begin + if ( Reset ) begin + Start <= 0; + A_Dt_L <= 0; + A_Dt_H <= 0; + A_Ut_L <= 0; + A_Ut_H <= 0; + B_Dt_L <= 0; + B_Dt_H <= 0; + B_Ut_L <= 0; + B_Ut_H <= 0; + C_Dt_L <= 0; + C_Dt_H <= 0; + C_Ut_L <= 0; + C_Ut_H <= 0; + D_Dt_L <= 0; + D_Dt_H <= 0; + D_Ut_L <= 0; + D_Ut_H <= 0; + A_Hi <= 0; + A_Lo <= 0; + A_Rise <= 0; + A_Fall <= 0; + B_Hi <= 0; + B_Lo <= 0; + B_Rise <= 0; + B_Fall <= 0; + end else begin + + // For CH_A Trigger + if ( A > Delta_V3 )begin + A_Hi <= Sampled; + end + if ( A < Delta_V4 )begin + A_Lo <= Sampled; + end + if ( A > Delta_V1 )begin + A_Rise <= Sampled; + end + if ( A < Delta_V2 )begin + A_Fall <= Sampled; + end + + if (( A > Delta_V3 )&&(~A_Flag )) begin + if ( A_Cnt < XTthreshold) A_Dt_L <= Sampled; + else A_Ut_L <= Sampled; + A_Flag <= 1; + A_Cnt <= 0; + end else + if (( A < Delta_V4 )&&( A_Flag )) begin + if ( A_Cnt < XTthreshold ) A_Dt_H <= Sampled; + else A_Ut_H <= Sampled; + A_Flag <= 0; + A_Cnt <= 0; + end else A_Cnt <= A_Cnt + 1; + + + // For CH_B Trigger + if ( B > Delta_V3 )begin + B_Hi <= Sampled; + end + if ( B < Delta_V4 )begin + B_Lo <= Sampled; + end + if ( B > Delta_V1 )begin + B_Rise <= Sampled; + end + if ( B < Delta_V2 )begin + B_Fall <= Sampled; + end + + if (( B > Delta_V3 )&&(~B_Flag )) begin + if ( B_Cnt < XTthreshold ) B_Dt_L <= Sampled; + else B_Ut_L <= Sampled; + B_Flag <= 1; + B_Cnt <= 0; + end else + if (( B < Delta_V4 )&&( B_Flag )) begin + if ( B_Cnt < XTthreshold ) B_Dt_H <= Sampled; + else B_Ut_H <= Sampled; + B_Flag <= 0; + B_Cnt <= 0; + end else B_Cnt <= B_Cnt + 1; + + + // For CH_C Trigger + if ( CD[0] != C_Flag ) begin + if ( C_Cnt < XTthreshold ) begin + if ( CD[0] ) C_Dt_L <= Sampled; + else C_Dt_H <= Sampled; + end else begin + if ( CD[0] ) C_Ut_L <= Sampled; + else C_Ut_H <= Sampled; + end + C_Cnt <= 0; + end else C_Cnt <= C_Cnt + 1; + C_Flag <= CD[0]; + + // For CH_D Trigger + if ( CD[1] != D_Flag ) begin + if ( D_Cnt < XTthreshold ) begin + if ( CD[1] ) D_Dt_L <= Sampled; + else D_Dt_H <= Sampled; + end else begin + if ( CD[1] ) D_Ut_L <= Sampled; + else D_Ut_H <= Sampled; + end + D_Cnt <= 0; + end else D_Cnt <= D_Cnt + 1; + D_Flag <= CD[1]; + + + case( Trigg_Mode ) + // For CH_A Trigger + 8'h00: if ( A < Vthreshold ) Start <= A_Rise; // Negedge + 8'h01: if ( A > Vthreshold ) Start <= A_Fall; // Posedge + 8'h02: if ( A < Vthreshold ) Start <= A_Hi; // L Level + 8'h03: if ( A > Vthreshold ) Start <= A_Lo; // H Level + 8'h04: Start <= A_Dt_L; // Pulse 0 < ConfigDt + 8'h05: Start <= A_Ut_L; // Pulse 0 > ConfigDt + 8'h06: Start <= A_Dt_H; // Pulse 1 < ConfigDt + 8'h07: Start <= A_Ut_H; // Pulse 1 > ConfigDt + + // For CH_B Trigger + 8'h08: if ( B < Vthreshold ) Start <= B_Rise; // Negedge + 8'h09: if ( B > Vthreshold ) Start <= B_Fall; // Posedge + 8'h0A: if ( B < Vthreshold ) Start <= B_Hi; // L Level + 8'h0B: if ( B > Vthreshold ) Start <= B_Lo; // H Level + 8'h0C: Start <= B_Dt_L; // Pulse 0 < ConfigDt + 8'h0D: Start <= B_Ut_L; // Pulse 0 > ConfigDt + 8'h0E: Start <= B_Dt_H; // Pulse 1 < ConfigDt + 8'h0F: Start <= B_Ut_H; // Pulse 1 > ConfigDt + + // For CH_C Trigger + 8'h10: if (( ~CD[0] )&&( C_Flag )) Start <= Sampled; // Negedge + 8'h11: if (( CD[0] )&&( ~C_Flag )) Start <= Sampled; // Posedge + 8'h12: if (( ~CD[0] )&&( C_Flag )) Start <= Sampled; // L Level + 8'h13: if (( CD[0] )&&( ~C_Flag )) Start <= Sampled; // H Level + 8'h14: Start <= C_Dt_L; // Pulse 0 < ConfigDt + 8'h15: Start <= C_Ut_L; // Pulse 0 > ConfigDt + 8'h16: Start <= C_Dt_H; // Pulse 1 < ConfigDt + 8'h17: Start <= C_Ut_H; // Pulse 1 > ConfigDt + // For CH_D Trigger + 8'h18: if (( ~CD[1] )&&( D_Flag )) Start <= Sampled; // Negedge + 8'h19: if (( CD[1] )&&( ~D_Flag )) Start <= Sampled; // Posedge + 8'h1A: if (( ~CD[1] )&&( D_Flag )) Start <= Sampled; // L Level + 8'h1B: if (( CD[1] )&&( ~D_Flag )) Start <= Sampled; // H Level + 8'h1C: Start <= D_Dt_L; // Pulse 0 < ConfigDt + 8'h1D: Start <= D_Ut_L; // Pulse 0 > ConfigDt + 8'h1E: Start <= D_Dt_H; // Pulse 1 < ConfigDt + 8'h1F: Start <= D_Ut_H; // Pulse 1 > ConfigDt + 8'h20: Start <= 1; //Uncondition trig mode + + endcase + end + end +endmodule \ No newline at end of file diff --git a/W1.1 FPGA/Time.sdc b/W1.1 FPGA/Time.sdc new file mode 100644 index 0000000..3dcac4f --- /dev/null +++ b/W1.1 FPGA/Time.sdc @@ -0,0 +1,12 @@ +#Clock +create_clock [get_ports {MCI} ] -name {MCI} -period 13.888 +create_clock [get_ports {nRD} ] -name {nRD} -period 100 +create_clock [get_ports {SCK} ] -name {SCK} -period 100 +create_clock [get_ports {SDA} ] -name {SDA} -period 100 +create_clock [get_ports {ClrW}] -name {ClrW} -period 100 +#Generated Clock +#Input Delay +#Output Delay +#Max-delay +#False Path +#Multi-cycle diff --git a/cortexm3_macro.s b/cortexm3_macro.s new file mode 100644 index 0000000..bd33940 --- /dev/null +++ b/cortexm3_macro.s @@ -0,0 +1,302 @@ +/* ******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** */ +/* * File Name : cortexm3_macro.s */ +/* * Author : MCD Application Team */ +/* * Version : V2.2.1 */ +/* * Date : 09/22/2008 */ +/* * Description : Instruction wrappers for special Cortex-M3 instructions. */ +/* * to be used with EWARM4.x toolchain. */ +/* ******************************************************************************* */ +/* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS */ +/* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. */ +/* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, */ +/* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE */ +/* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING */ +/* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. */ +/* ******************************************************************************* */ + +.syntax unified +.thumb +.text + + /* Exported functions */ + .globl __WFI + .globl __WFE + .globl __SEV + .globl __ISB + .globl __DSB + .globl __DMB + .globl __SVC + .globl __MRS_CONTROL + .globl __MSR_CONTROL + .globl __MRS_PSP + .globl __MSR_PSP + .globl __MRS_MSP + .globl __MSR_MSP + .globl __RESETPRIMASK + .globl __SETPRIMASK + .globl __READ_PRIMASK + .globl __RESETFAULTMASK + .globl __SETFAULTMASK + .globl __READ_FAULTMASK + .globl __BASEPRICONFIG + .globl __GetBASEPRI + .globl __REV_HalfWord + .globl __REV_Word + +/* ******************************************************************************* */ +/* Function Name : __WFI */ +/* Description : Assembler function for the WFI instruction. */ +/* Input : None */ +/* Return : None */ +/* ******************************************************************************* */ +__WFI: + + WFI + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __WFE */ +/* Description : Assembler function for the WFE instruction. */ +/* Input : None */ +/* Return : None */ +/* ******************************************************************************* */ +__WFE: + + WFE + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __SEV */ +/* Description : Assembler function for the SEV instruction. */ +/* Input : None */ +/* Return : None */ +/* ******************************************************************************* */ +__SEV: + + SEV + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __ISB */ +/* Description : Assembler function for the ISB instruction. */ +/* Input : None */ +/* Return : None */ +/* ******************************************************************************* */ +__ISB: + + ISB + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __DSB */ +/* Description : Assembler function for the DSB instruction. */ +/* Input : None */ +/* Return : None */ +/* ******************************************************************************* */ +__DSB: + + DSB + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __DMB */ +/* Description : Assembler function for the DMB instruction. */ +/* Input : None */ +/* Return : None */ +/* ******************************************************************************* */ +__DMB: + + DMB + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __SVC */ +/* Description : Assembler function for the SVC instruction. */ +/* Input : None */ +/* Return : None */ +/* ******************************************************************************* */ +__SVC: + + SVC 0x01 + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __MRS_CONTROL */ +/* Description : Assembler function for the MRS instruction. */ +/* Input : None */ +/* Return : - r0 : Cortex-M3 CONTROL register value. */ +/* ******************************************************************************* */ +__MRS_CONTROL: + + MRS r0, CONTROL + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __MSR_CONTROL */ +/* Description : Assembler function for the MSR instruction. */ +/* Input : - r0 : Cortex-M3 CONTROL register new value. */ +/* Return : None */ +/* ******************************************************************************* */ +__MSR_CONTROL: + + MSR CONTROL, r0 + ISB + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __MRS_PSP */ +/* Description : Assembler function for the MRS instruction. */ +/* Input : None */ +/* Return : - r0 : Process Stack value. */ +/* ******************************************************************************* */ +__MRS_PSP: + + MRS r0, PSP + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __MSR_PSP */ +/* Description : Assembler function for the MSR instruction. */ +/* Input : - r0 : Process Stack new value. */ +/* Return : None */ +/* ******************************************************************************* */ +__MSR_PSP: + + MSR PSP, r0 /* set Process Stack value */ + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __MRS_MSP */ +/* Description : Assembler function for the MRS instruction. */ +/* Input : None */ +/* Return : - r0 : Main Stack value. */ +/* ******************************************************************************* */ +__MRS_MSP: + + MRS r0, MSP + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __MSR_MSP */ +/* Description : Assembler function for the MSR instruction. */ +/* Input : - r0 : Main Stack new value. */ +/* Return : None */ +/* ******************************************************************************* */ +__MSR_MSP: + + MSR MSP, r0 /* set Main Stack value */ + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __RESETPRIMASK */ +/* Description : Assembler function to reset the PRIMASK. */ +/* Input : None */ +/* Return : None */ +/* ******************************************************************************* */ +__RESETPRIMASK: + + CPSIE i + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __SETPRIMASK */ +/* Description : Assembler function to set the PRIMASK. */ +/* Input : None */ +/* Return : None */ +/* ******************************************************************************* */ +__SETPRIMASK: + + CPSID i + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __READ_PRIMASK */ +/* Description : Assembler function to get the PRIMASK value. */ +/* Input : None */ +/* Return : - r0 : PRIMASK register value */ +/* ******************************************************************************* */ +__READ_PRIMASK: + + MRS r0, PRIMASK + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __RESETFAULTMASK */ +/* Description : Assembler function to reset the FAULTMASK. */ +/* Input : None */ +/* Return : None */ +/* ******************************************************************************* */ +__RESETFAULTMASK: + + CPSIE f + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __SETFAULTMASK */ +/* Description : Assembler function to set the FAULTMASK. */ +/* Input : None */ +/* Return : None */ +/* ******************************************************************************* */ +__SETFAULTMASK: + + CPSID f + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __READ_FAULTMASK */ +/* Description : Assembler function to get the FAULTMASK value. */ +/* Input : None */ +/* Return : - r0 : FAULTMASK register value */ +/* ******************************************************************************* */ +__READ_FAULTMASK: + + MRS r0, FAULTMASK + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __BASEPRICONFIG */ +/* Description : Assembler function to set the Base Priority. */ +/* Input : - r0 : Base Priority new value */ +/* Return : None */ +/* ******************************************************************************* */ +__BASEPRICONFIG: + + MSR BASEPRI, r0 + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __GetBASEPRI */ +/* Description : Assembler function to get the Base Priority value. */ +/* Input : None */ +/* Return : - r0 : Base Priority value */ +/* ******************************************************************************* */ +__GetBASEPRI: + + MRS r0, BASEPRI_MAX + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __REV_HalfWord */ +/* Description : Reverses the byte order in HalfWord(16-bit) input variable. */ +/* Input : - r0 : specifies the input variable */ +/* Return : - r0 : holds tve variable value after byte reversing. */ +/* ******************************************************************************* */ +__REV_HalfWord: + + REV16 r0, r0 + BX r14 + +/* ******************************************************************************* */ +/* Function Name : __REV_Word */ +/* Description : Reverses the byte order in Word(32-bit) input variable. */ +/* Input : - r0 : specifies the input variable */ +/* Return : - r0 : holds tve variable value after byte reversing. */ +/* ******************************************************************************* */ +__REV_Word: + + REV r0, r0 + BX r14 + +.end + +/* ******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE***** */ diff --git a/inc/BIOS.h b/inc/BIOS.h new file mode 100644 index 0000000..5fff3ee --- /dev/null +++ b/inc/BIOS.h @@ -0,0 +1,247 @@ +/********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ******************** + File Name : BIOS.h + Version : DS203_APP Ver 2.5x Author : bure +*******************************************************************************/ +#ifndef __BIOS_H +#define __BIOS_H + +#include "stm32f10x_lib.h" + + +//============================= Flash space allocation ================================= + +#define BIN_BASE ((u32)(0x0802C000)) // Size < 68KB +#define PRM_BASE BIN_BASE + 68*1024 // Size = 2KB +#define INF_BASE BIN_BASE + 70*1024 // Size < 10KB +#define APP4_BASE ((u32)(0x08024000)) // Size = 32KB +#define APP3_BASE ((u32)(0x0801C000)) // Size = 32KB +#define APP2_BASE ((u32)(0x08014000)) // Size = 32KB +#define APP1_BASE ((u32)(0x0800C000)) // Size = 32KB +#define SYS_BASE ((u32)(0x08004000)) // Size = 32KB +#define DFU_BASE ((u32)(0x08000000)) // Size = 16KB + +//====================== Function Set Object and Value defined ====================== + +#define CH_A_OFFSET 0 // A channel vertical displacement Value = 0~200 +#define CH_B_OFFSET 1 // B channel vertical displacement Value = 0~200 +#define BACKLIGHT 2 // backlight brightness Value = 0~100 +#define BEEP_VOLUME 3 // buzzer volume Value = 0~100 +#define BETTERY_DT 4 // battery voltage detector Value = 1: start +#define ADC_MODE 5 // ADC operating mode Value = 1/0 +#define FIFO_CLR 6 // FIFO pointer reset Value = 1/0: W_PTR/R_PTR + #define R_PTR 0 // FIFO read address pointer reset + #define W_PTR 1 // FIFO write address pointer is reset +#define T_BASE_PSC 7 // prescaler value Value = 0~65535 +#define T_BASE_ARR 8 // frequency Value = 0~65535 +#define CH_A_COUPLE 9 // A channel coupling method Value = 1/0: AC/DC + #define DC 0 + #define AC 1 +#define CH_A_RANGE 10 // A channel input range Value = 0~5 +#define CH_B_COUPLE 11 // B channel coupling method Value = 1/0: AC/DC +#define CH_B_RANGE 12 // B channel input range Value = 0~5 +#define ANALOG_ARR 13 // analog output divider value Value = 0~65535 +#define ANALOG_PTR 14 // analog output pointer Value = 0~65535 +#define ANALOG_CNT 15 // synthetic points of a week Value = 0~65535 +#define DIGTAL_PSC 16 // pulse output prescaler value Value = 0~65535 +#define DIGTAL_ARR 17 // pulse output divider value Value = 0~65535 +#define DIGTAL_CCR 18 // pulse output duty cycle value Value = 0~65535 +#define KEY_IF_RST 19 // timer interrupt flag reset Value = 0 +#define STANDBY 20 // to enter the power-down waiting Value = 0 +#define ANALOG_PSC 21 // only implemented in Marcosin's sys version +#define FPGA_RST 31 // FPGA Reset Value = 0 + +#define TRIGG_MODE 32+0 // trigger mode Value = Mode +#define V_THRESHOLD 32+1 // voltage trigger threshold Value = 0~200 +#define T_THRESHOLD 32+2 // pulse width trigger gate limit Value = 0~65535 +#define ADC_CTRL 32+4 // ADC status Value = 1/0 EN/DN +#define A_POSITION 32+5 // the zero position of CH_A Value = 0~200 +#define B_POSITION 32+6 // the zero position of CH_B Value = 0~200 +#define REG_ADDR 32+7 // the address determines which set of registers in the FPGA, the data read into the MCU + +//==================== Function Set TRIGG_MODE of Value defined ===================== +/* +CH_A Trigger source & kind select => +0x00: by Negedge; 0x01: by Posedge; 0x02: by low level; 0x03: by high level +0x04: TL < Delta_T; 0x05: TL > Delta_T; 0x06: TH < Delta_T; 0x07: TH > Delta_T; + +CH_B Trigger source & kind select => +0x08: by Negedge; 0x09: by Posedge; 0x0A: by low level; 0x0B: by high level +0x0C: TL < Delta_T; 0x0D: TL > Delta_T; 0x0E: TH < Delta_T; 0x0F: TH > Delta_T; + +CH_C Trigger source & kind select => +0x10: by Negedge; 0x11: by Posedge; 0x12: by low level; 0x13: by high level +0x04: TL < Delta_T; 0x05: TL > Delta_T; 0x06: TH < Delta_T; 0x07: TH > Delta_T; + +CH_D Trigger source & kind select => +0x18: by Negedge; 0x19: by Posedge; 0x1A: by low level; 0x1B: by high level +0x1C: TL < Delta_T; 0x1D: TL > Delta_T; 0x1E: TH < Delta_T; 0x1F: TH > Delta_T; + +0x20~0xFF => Unconditional trigger +*/ + +#define UNCONDITION 0x20 // unconditional trigger sampling + +//================ Function Set in ADC_CTRL the STANDBY Value defined ================ + +#define DN 0 +#define EN 1 + +//===================== Function Set ADC_MODE of Value defined ===================== + +#define SEPARATE 0 // ADC sampling mode independently +#define INTERLACE 1 // ADC Alternate Sampling mode + +//========================= Function Get Kind defined ============================ + +#define FIFO_DIGIT 0 // 16bits FIFO digital data +#define FIFO_EMPTY 1 // FIFO empty flag: 1 = empty +#define FIFO_START 2 // FIFO start flag: 1 = start +#define FIFO_FULL 3 // FIFO full flag: 1 = Full +#define KEY_STATUS 4 // Current keys status + #define K_ITEM_D_STATUS 0x0008 // 0 = Key push on + #define K_ITEM_S_STATUS 0x0040 // 0 = Key push on + #define KEY3_STATUS 0x0100 // 0 = Key push on + #define KEY4_STATUS 0x0200 // 0 = Key push on + #define K_INDEX_D_STATUS 0x0400 // 0 = Key push on + #define K_INDEX_I_STATUS 0x0800 // 0 = Key push on + #define K_INDEX_S_STATUS 0x1000 // 0 = Key push on + #define KEY2_STATUS 0x2000 // 0 = Key push on + #define KEY1_STATUS 0x4000 // 0 = Key push on + #define K_ITEM_I_STATUS 0x8000 // 0 = Key push on +#define USB_POWER 5 // USB power status: 1 = Power ON +#define V_BATTERY 6 // Battery voltage (mV) +#define VERTICAL 7 // vertical channel attribute pointer +#define HORIZONTAL 8 // horizontal channel attribute pointer +#define GLOBAL 9 // pointer to the whole property +#define TRIGGER 10 // trigger channel attribute pointer +#define FPGA_OK 11 // FPGA configuration was successful 1 = the FPGA config the ok +#define CHARGE 12 // battery charge status +#define HDWVER 13 // device hardware version number +#define DFUVER 14 // the DFU program module version number +#define SYSVER 15 // the SYS program module version number +#define FPGAVER 16 // version number of the FPGA configuration program +#define DEVICEINFO 18 //DISK=7 (FLASH 2M,OR 8M) + +#define ADC_DATA 32+0 // 0~7:ADC_CH_A 8~15:ADC_CH_B 16~17:CH_C&CH_D +#define PRE_SAMPLING 32+1 // 0~15:Pre-sampling depth +#define ALL_SAMPLING 32+2 // 0~15:Total sampling depth +#define CH_A_MIN_MAX 32+3 // 0~7:VMIN 8~15:VMAX +#define CH_A_V_SUM 32+4 // 0~15:CH_A voltage sum +#define CH_A_V_SSQ 32+5 // 0~15:CH_A voltage sum of squares +#define CH_A_NEDGE 32+6 // 0~15:CH_A number of edge +#define CH_A_FREQ 32+7 // 0~15:CH_A frequence +#define CH_A_PHW_MAX 32+8 // 0~15:CH_A pulse high width MAX +#define CH_A_PHW_MIN 32+9 // 0~15:CH_A pulse high width MIN +#define CH_A_PLW_MAX 32+10 // 0~15:CH_A pulse low width MAX +#define CH_A_PLW_MIN 32+11 // 0~15:CH_A pulse low width MIN + +// ============================================================================= + +typedef struct // hardware properties +{ + u16 LCD_X; // horizontal screen display points + u16 LCD_Y; // vertical screen display points + u16 Yp_Max; // maximum vertical gear + u16 Xp_Max; // maximum level stalls + u16 Tg_Num; // trigger the stalls in the maximum + u16 Yv_Max; // maximum vertical displacement + u16 Xt_Max; // maximum horizontal displacement + u16 Co_Max; // maximum coupling mode + u8 Ya_Num; // the number of analog channels + u8 Yd_Num; // the number of digital channels + u8 INSERT; // start using the interpolated stalls + u16 KpA1; // A channel shift compensation factor + u16 KpA2; // A channel displacement compensation coefficient + u16 KpB1; // B-channel displacement compensation coefficient + u16 KpB2; // B channel displacement compensation coefficient +} G_attr ; + +typedef struct // vertical channel properties +{ + char STR[8]; // stall identification string + s16 KA1; // A channel displacement error correction factor 1 + u16 KA2; // A channel slope error correction factor + s16 KB1; // B-channel displacement error correction factor 1 + u16 KB2; // B channel slope error correction factor + u32 SCALE; // vertical channel scale factor +} Y_attr ; + +typedef struct // horizontal channel properties +{ + char STR[8]; // stall identification string + s16 PSC; // prescaler coefficient + u16 ARR; // frequency coefficient + u16 CCR; // duty cycle coefficient + u16 KP; // interpolation coefficients + u32 SCALE; // horizontal channel scale factor +} X_attr ; + +typedef struct // chanel trigger properties +{ + char STR[8]; // trigger identification string + u8 CHx; // trigger channel number + u8 CMD; // trigger control word +} T_attr ; + +extern Y_attr *Y_Attr; +extern X_attr *X_Attr; +extern G_attr *G_Attr; +extern T_attr *T_Attr; + +//============================================================================== +// System function entrance +//============================================================================== + void __CTR_HP(void); //USB_HP_Interrupt + void __USB_Istr(void); //USB_LP_Interrupt + void __USB_Init(void); + + void __LCD_Initial(void); + void __Clear_Screen(u16 Color); + void __Point_SCR(u16 x0, u16 y0); + void __LCD_SetPixl(u16 Color); + u16 __LCD_GetPixl(void); + u16 __Get_TAB_8x14(u8 Code, u16 Row); + void __LCD_Set_Block(u16 x1, u16 x2, u16 y1, u16 y2); + + void __LCD_Copy(uc16 *pBuffer, u16 NumPixel); // Send a row data to LCD + void __LCD_Fill(u16 *pBuffer,u16 NumPixel); // Fill number of pixel by DMA + void __LCD_DMA_Ready(void); // Wait LCD data DMA ready + + void __Row_Copy(uc16 *S_Buffer,u16 *T_Buffer); // Copy one row base data to buffer + void __Row_DMA_Ready(void); // Wait row base data DMA ready + + u32 __Read_FIFO(void); // Read data from FIFO & Ptr+1 + void __Display_Str(u16 x0, u16 y0, u16 Color, u8 Mode, char *s); + + u32 __Input_Lic(u16 x0, u8 y0); //Return: 32Bits Licence + u32 __GetDev_SN(void); // Get 32bits Device Serial Number + + u8 __Ident(u32 Dev_ID, u32 Proj_ID, u32 Lic_No); + + void __Set_Param(u8 RegAddr, u8 Parameter); + void __Set(u8 Object, u32 Value); + u32 __Get(u8 Object); + + void __ExtFlash_PageRD(u8* pBuffer, u32 ReadAddr, u16 NumByteToRead); + void __ExtFlash_PageWR(u8* pBuffer, u32 WriteAddr); + u8 __ReadDiskData(u8* pBuffer, u32 ReadAddr, u16 Lenght); + u8 __ProgDiskPage(u8* pBuffer, u32 ProgAddr); + + u8 __FLASH_Erase(u32 Address); + u8 __FLASH_Prog(u32 Address, u16 Data); + void __FLASH_Unlock(void); + void __FLASH_Lock(void); + + u8 __Chk_SYS(u32 Licence); + u8* __Chk_DFU(void); + u8* __Chk_HDW(void); + + u8 __OpenFileWr(u8* Buffer, char* FileName, u16* Cluster, u32* pDirAddr); + u8 __OpenFileRd(u8* Buffer, char* FileName, u16* Cluster, u32* pDirAddr); + u8 __ReadFileSec(u8* Buffer, u16* Cluster); + u8 __ProgFileSec(u8* Buffer, u16* Cluster); + u8 __CloseFile(u8* Buffer, u32 Lenght, u16* Cluster, u32* pDirAddr); +/**/ + +#endif +/******************************* END OF FILE ********************************/ diff --git a/inc/Calibrat.h b/inc/Calibrat.h new file mode 100644 index 0000000..23d43be --- /dev/null +++ b/inc/Calibrat.h @@ -0,0 +1,22 @@ +/********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ******************** + File Name : Calibrat.h + Version : DS203_APP Ver 2.3x Author : bure +*******************************************************************************/ +#ifndef __CALIBRAT_H +#define __CALIBRAT_H + +#include "stm32f10x_lib.h" + +#define _100uS 12 // T_BASE = 100uS/Div +#define _2uS 17 // T_BASE = 2uS/Div + +extern s16 PPM_Comp; +extern u8 CalibrateMode; + +void Calibrat(u8 Channel); + + + +#endif + +/******************************* END OF FILE ********************************/ diff --git a/inc/Draw.h b/inc/Draw.h new file mode 100644 index 0000000..c737724 --- /dev/null +++ b/inc/Draw.h @@ -0,0 +1,144 @@ +/********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ******************** + File Name : Draw.h + Version : DS203_APP Ver 2.3x Author : bure +*******************************************************************************/ +#ifndef __DRAW_H +#define __DRAW_H + +#include "stm32f10x_lib.h" + +typedef struct +{ + s16 Value; + u8 Flag; // HID=0x04, UPDAT=0x02, < does not appear to be used +} trigg; + +//------------------- ÆÁÄ»ÏÔʾÑÕÉ«±àºÅ¶¨Òå ---------------------- +#define TR_1 0 +#define TR_2 1 +#define TR_3 2 +#define TR_4 3 +#define VERNIE 4 +#define SCRN 5 +#define GRID 9 +#define NOTE2 7 +#define NOTE3 8 +#define X_POSI 6 +#define TEXT1 10 +#define TEXT2 11 +#define TEXT3 12 +#define BLOCK 13 +#define SIDE 14 +#define NOTE1 15 + + +#define SINE 0 +#define TRIANG 1 +#define SAW 2 +#define DIGI 3 +#define PWM 4 + +#define PRN 0 // No inverse Display +#define INV 1 // Inverse Display + + +#define WHT 0xFFFF +#define CYAN 0xFFE0 +#define CYAN_ 0xBDE0 +#define YEL 0x07FF +#define YEL_ 0x05F7 +#define PURPL 0xF81F +#define PURPL_ 0xB817 +#define GRN 0x07E0 +#define GRN_ 0x05E0 +//#define GRAY 0x7BEF //original, dark gray +//#define GRAY 0x9DEF //greenish gray +//#define GRAY 0xBDF7 //bright gray +#define GRAY 0xA534 //medium gray +#define BLUE 0xF800 +#define ORANGE 0x051F +#define RED 0x001F +#define BLACK 0x0000 + + +#define LCD_X1 0 +#define LCD_X2 399 +#define LCD_Y1 0 +#define LCD_Y2 239 +#define X_SIZE 392 //386 300 400 +#define X_BASE 0 +#define Y_SIZE 200 +#define Y_BASE 0 +#define MIN_X 11 +#define MIN_Y 13 +#define TRACK_OFFSET 2 //2 +//#define MAX_X (X_SIZE + MIN_X) now variable, at most, with meters off=386 + min_x or 397 +#define MAX_Y (Y_SIZE + MIN_Y) + + +#define CHAR_WIDTH 8 +#define CHAR_HEIGHT 11 + +extern u16 XposRef; +extern u8 UpdateScale; +extern u16 SpecRow; +extern u8 Raw; +extern u8 PerstFrameNumber; +extern u8 XYper; +extern u8 InitXY; +extern u8 UpdateWindow; +extern u8 SpecMode; +extern u8 OffsetX; +extern u8 OffsetY; +extern u16 MAX_X; +extern u8 FlagFrameMode; +extern u8 FlagMeter; +extern u8 UpdateMeter; +extern u8 TrgAuto; +extern u8 UpdateBackground; +extern u16 Color[16]; +extern u16 Count_FPS; +extern trigg V_Trigg[4]; +extern s16 DetFrqn[12]; +extern u32 BaudRate; +extern u8 FrameSize; +extern u8 Parity; +extern u8 DataSize; +extern u8 DataAdj; +extern u8 ValidFrame; +extern u8 SpiMode; +extern u8 SpiBitOrder; +extern s16 SpiNumBits; +extern u8 SpiAdj; +extern u8 SpiChartFlag; +extern u8 ArrayIndex; +extern u8 OSBuffer; +extern u8 DigChLockout; +extern u8 Hbold; +extern u8 CursorDisplaySelect; +extern u8 DisableCursorDisplay; +extern u8 EnableCursorDisplay; + +u16 Get_TAB_8x11(u8 Code, u8 Row); +void Print_Str(u16 x0, u16 y0, u16 Color, u8 Mode, char *s); +void Print_Str2(u16 x0,u16 x1,u16 y0, u16 Type, u8 Mode, char *s,u8 LeadingBlanks,u8 TrailingBlanks); +void Draw_Row(u16 Row); +void Draw_Window(void); +void LoadBaseBuffers(void); + +void Draw_Mark(u16 m, u16 n); +void Update_Mark(void); +void Update_View_Area(void); +void Clear_Meter_Area(void); +void ClearFFTbuffer(void); +void ClearScreenArea(u16 x1,u16 x2,u8 y1,u8 y2); +u8 UartLogic(void); +u8 i2cLogic(void); +u8 SpiLogic(void); +u16 IndexPosition(s16 Position,u8 service); +void PrintDir(u16 Row, u8 buffer,u8 Mode); +void UpdateMarkLogic(void); + +#endif + +/********************************* END OF FILE ********************************/ diff --git a/inc/File.h b/inc/File.h new file mode 100644 index 0000000..60ed30d --- /dev/null +++ b/inc/File.h @@ -0,0 +1,74 @@ +/********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ******************** + File Name : file.h + Version : DS203_APP Ver 2.5x Author : bure +*******************************************************************************/ +#ifndef __FILE_H +#define __FILE_H + +#include "stm32f10x_lib.h" + +//#define FLASH_WAIT_TIMEOUT 100000 +//#define PAGE_0 0 +//#define PAGE_1 1 +//#define PAGE_2 2 +//#define PAGE_3 3 + +#define OK 0 // operation is completed +//#define SEC_ERR 1 // sectors read and write errors +//#define FAT_ERR 2 // FAT table to read and write errors +#define OVER 3 // operations overflow +#define NEW 4 // new directory entry +#define EMPT 4 // file does not exist +#define VER_ERR 5 // wrong version +#define SUM_ERR 6 // checksum error +#define RD_ERR 8 // sectors read error +#define WR_ERR 9 // sector write error +#define DISK_ERR 10 // disk error + +#define FLASH_8M 1 +#define FLASH_2M 0 +#define FLASH_2M_SECTOR_SIZE 512 +#define FLASH_8M_SECTOR_SIZE 4096 +#define LARGEST_SECTOR_SIZE 4096 +#define BUFFER_SIZE 16384 +extern u8 flash_mode; +extern u16 SectorSize; +extern u8 FileBuff[1600]; +extern u8 SaveShortBuffXpos; +extern u8 Versions; +extern u16 TempPar[74]; +extern u16 ArbtSampleNumber; +extern u32 UartFileSize; +extern u8 SecBuff[LARGEST_SECTOR_SIZE]; +extern char Label[15][13]; +extern char Ext[4]; +extern u16 DirRange; +extern char SelectedFileName[9]; +extern char ConfigFileName[9]; +extern char LastAccessedConfig[9]; +extern u8 Edited; +extern u8 BufferRestore; +extern u16 CSVposition; + +u8 Save_Bmp(u8 FileNum); +u8 Save_Dat(u8 FileNum); +u8 Load_Dat(u8 FileNum); +u8 Save_Buf(u8 FileNum); +u8 Load_Buf(u8 FileNum); +u8 Load_Bmp(u8 FileNum); +u8 Save_Csv(u8 FileNum); +u8 Make_Filename(u8 FileNum,char* FileName); +void reset_parameter(void); +u8 Load_Param(u8 FileNum); +u8 Save_Param(u8 FileNum); +u8 Load_Arbt(u8 FileNum); +u8 Load_Uart(u8 FileNum); +u8 Save_Img(void); +u8 ReadDir(char *ext); +void FileMessage(u8 i); +void UpdateFileMenu(void); +u8 DeleteFile(u8* pBuffer,char* FileName); +void save_parameter(void); + +#endif +/********************************* END OF FILE ********************************/ diff --git a/inc/Function.h b/inc/Function.h new file mode 100644 index 0000000..6e581cf --- /dev/null +++ b/inc/Function.h @@ -0,0 +1,71 @@ +/********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ******************** + File Name : Function.h + Version : DS203_APP Ver 2.3x Author : bure +*******************************************************************************/ +#ifndef __Function_H__ +#define __Function_H__ + +#include "stm32f10x_lib.h" + +/* +#define NO_KEY 0 +#define KEY1 1 +#define KEY2 2 +#define KEY3 3 +#define KEY4 4 +#define K_INDEX_DEC 5 +#define K_INDEX_INC 6 +#define K_INDEX_S 7 +#define K_ITEM_INC 8 +#define K_ITEM_DEC 9 +#define K_ITEM_S 10 +*/ + +#define NO_KEY 0 +#define KEY1 1 +#define KEY3 2 +#define KEY4 3 +#define K_ITEM_S 4 +#define K_INDEX_S 5 +#define KEY2 6 +#define K_ITEM_DEC 7 +#define K_ITEM_INC 8 +#define K_INDEX_DEC 9 +#define K_INDEX_INC 10 + + +#define SIGN 0 +#define UNSIGN 1 +#define STD 2 + +u32 Power(u8 x, u8 y); +void Delayms(u16 mS); +void Int2Str(char *p, s32 n,const char *pUnit, u8 e, u8 Mode, s8 ShiftDigits); +void u8ToDec3(char *p, u16 n,u8 service); +void u8ToDec2(char *p, u8 n); +void Word2Hex(char *p, u32 n); +void s16ToDec3(char *p, s16 n); +//void u16ToDec5(char *p, u16 n); +u32 Int_sqrt(u32 n); +u8 Read_Keys(void); +void s8ToPercen(char *p, s8 n); +void s8ToDec2(char *p, s8 n); +void LoadNwave(void); +u16 AsciiToU16(char *p,u8 n); +void u32ToDec7(char*p,u32 n); +void ProcessFileName(void); +void Char2Hex(char *p, u8 n); +void S32ToFloat3(char *p,s32 n); + +extern u8 SetLowVolume; + +#define N_WAVE 512 // full length of Sinewave[] +#define LOG2_N_WAVE 9 // log2(N_WAVE) +#define FFTSize 512 +#define FFTBins 256 +#define LOG2_FFTSize 9 +//extern void fix_fft(short fr[], short fi[], short m); +extern void fix_fft(s32 fr[], s32 fi[], short m); + +#endif +/********************************* END OF FILE ********************************/ diff --git a/inc/Interrupt.h b/inc/Interrupt.h new file mode 100644 index 0000000..2c06a0a --- /dev/null +++ b/inc/Interrupt.h @@ -0,0 +1,102 @@ +/********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ******************** + File Name : Interrupt.h + Version : DS203_APP Ver 2.3x Author : bure +*******************************************************************************/ + +#ifndef __Interrupt_H +#define __Interrupt_H + +#include "stm32f10x_lib.h" + +//extern vu8 Cursor_Cnt, Key_Wait_Cnt, Key_Repeat_Cnt, Key_Buffer, Cnt_mS, Cnt_20mS; +extern vu8 Cursor_Cnt, Key_Wait_Cnt, Key_Repeat_Cnt, Key_Buffer, Cnt_20mS; +extern vu16 Cnt_mS; +extern vu32 LimitTransfer; + +extern vu8 Twink, Blink; +extern u8 Volume, Light, LoBeepLevel; +extern vu16 Delay_Cnt, Beep_mS, Key_Status_Last, Sec_Cnt, PD_Cnt, NotificationTimer,DelayLoopBreak,SpecFrameCount, + PersHoldTimer,SecondsTick,ConfNameTimer, CursorDisplayTimer,AutoSetTimer; +extern vu8 Tim2Factor; +extern vu8 BurstLimit; +extern vu8 FineAdjust; +extern u8 FineAdjustLimit; +extern vu16 FineAdjustFactor[17]; +extern vu8 Key_Mid_Speed; + +extern vu32 Wait_Cnt; +void NMIException(void); +void HardFaultException(void); +void MemManageException(void); +void BusFaultException(void); +void UsageFaultException(void); +void DebugMonitor(void); +void SVCHandler(void); +void PendSVC(void); +void SysTickHandler(void); +void WWDG_IRQHandler(void); +void PVD_IRQHandler(void); +void TAMPER_IRQHandler(void); +void RTC_IRQHandler(void); +void FLASH_IRQHandler(void); +void RCC_IRQHandler(void); +void EXTI0_IRQHandler(void); +void EXTI1_IRQHandler(void); +void EXTI2_IRQHandler(void); +void EXTI3_IRQHandler(void); +void EXTI4_IRQHandler(void); +void DMA1_Channel1_IRQHandler(void); +void DMA1_Channel2_IRQHandler(void); +void DMA1_Channel3_IRQHandler(void); +void DMA1_Channel4_IRQHandler(void); +void DMA1_Channel5_IRQHandler(void); +void DMA1_Channel6_IRQHandler(void); +void DMA1_Channel7_IRQHandler(void); +void ADC1_2_IRQHandler(void); +void USB_HP_CAN_TX_IRQHandler(void); +void USB_LP_CAN_RX0_IRQHandler(void); +void CAN_RX1_IRQHandler(void); +void CAN_SCE_IRQHandler(void); +void EXTI9_5_IRQHandler(void); +void TIM1_BRK_IRQHandler(void); +void TIM1_UP_IRQHandler(void); +void TIM1_TRG_COM_IRQHandler(void); +void TIM1_CC_IRQHandler(void); +void TIM2_IRQHandler(void); +void TIM3_IRQHandler(void); +void TIM4_IRQHandler(void); +void I2C1_EV_IRQHandler(void); +void I2C1_ER_IRQHandler(void); +void I2C2_EV_IRQHandler(void); +void I2C2_ER_IRQHandler(void); +void SPI1_IRQHandler(void); +void SPI2_IRQHandler(void); +void USART1_IRQHandler(void); +void USART2_IRQHandler(void); +void USART3_IRQHandler(void); +void EXTI15_10_IRQHandler(void); +void RTCAlarm_IRQHandler(void); +void USBWakeUp_IRQHandler(void); +void TIM8_BRK_IRQHandler(void); +void TIM8_UP_IRQHandler(void); +void TIM8_TRG_COM_IRQHandler(void); +void TIM8_CC_IRQHandler(void); +void ADC3_IRQHandler(void); +void FSMC_IRQHandler(void); +void SDIO_IRQHandler(void); +void TIM5_IRQHandler(void); +void SPI3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void TIM6_IRQHandler(void); +void TIM7_IRQHandler(void); +void DMA2_Channel1_IRQHandler(void); +void DMA2_Channel2_IRQHandler(void); +void DMA2_Channel3_IRQHandler(void); +void DMA2_Channel4_5_IRQHandler(void); +void BackLight(s8 shift); + + +#endif /* __Interrupt_H */ + +/********************************* END OF FILE ********************************/ diff --git a/inc/Menu.h b/inc/Menu.h new file mode 100644 index 0000000..e57df6b --- /dev/null +++ b/inc/Menu.h @@ -0,0 +1,297 @@ +/********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ******************** + File Name : Menu.h + Version : DS203_APP Ver 2.4x Author : bure +*******************************************************************************/ +#ifndef __MENU_H +#define __MENU_H + +#include "stm32f10x_lib.h" + +//----------- The Detail menu constants MARK defined ----------- +#define NUM2 0x01 // display the Value of two values in the specified location +#define NUM3 0x02 // in the specified location to display the floating point value of the Value of 3 +#define CIRC 0x10 // the Detail Value in the regulation of head circulation +#define FIX 0x20 // the Detail Value change the identity of the corresponding string unchanged +#define NOT 0x80 // skip the Detail item choice + +//----------- Flag of the definition of variables in the Detail menu ----------- +#define HID 0x04 // display the Detail +#define UPDAT 0x02 // refresh the display of the Detail entry +#define BLINK 0x01 // the Detail display flashes + +#define BATTERY 4 + +//=============== MENU Main Menu item is number defined =============== +#define TRACK1 0 +#define TRACK2 1 +#define TRACK3 2 +#define TRACK4 3 + +#define RUNNING 4 +#define OUTPUT 5 + +#define T_BASE 6 +#define TRIGG 7 +#define V_VERNIE 8 +#define FILE 9 +#define T_VERNIE 10 +#define BK_LIGHT 11 +#define VOLUME 12 + +//------------- TRACKn submenu item number defined -------------- Dettagli TRACK +#define SOURCE 0 +#define COUPLE 1 +#define RANGE 2 +#define POSI 3 + +//............ TRACKn SOURCE item number defined ........... +#define HIDE 0 +#define CH_A 1 +#define CH_B 1 +#define CH_X10 2 +#define CH_C 1 +#define CH_D 1 +#define A_add_B 2 +#define A_sub_B 3 +#define C_and_D 4 +#define C_or_D 5 +#define REC_1 6 //FILE1,2..4 +#define REC_2 7 +#define REC_3 8 +#define REC_4 9 +#define SPEC_B 10 +#define SPEC_A 11 +#define FFT_B 12 +#define FFT_A 14 + + +//------------- RUNNING sub-menu item number defined ------------- +#define STATE 0 +#define STATUS 1 + +//.............. STATE sub-menu item number defined .............. +#define RUN 0 +#define HOLD 1 + +//-------------- T_BASE sub-menu item number defined ------------- +#define MODE 0 +#define BASE 1 +#define XPOSI 2 +#define VIEW 3 + + +//............. T_BASE Mode number defined ............ +#define SCAN 0 +#define AUTO 1 +#define NORH 2 +#define NORHLD 4 +#define NORC 3 +#define SGL 5 +#define X_Y 6 + + + +//-------------- OUTPUT sub-menu item number defined ------------- +#define KIND 0 +#define FRQN 1 +#define DUTYPWM 2 +#define OUTATT 3 + +//--------------- TRIGG sub-menu item number defined ------------- +#define SOURCE 0 +#define TR_KIND 1 +#define THRESHOLD 2 + +//------------- T_VERNIE sub-menu item number defined ------------ +#define T1 0 +#define T2 1 + +//------------- V_VERNIE sub-menu item number defined ------------ +#define V1 0 +#define V2 1 + +//--------------- FILE sub-menu item number defined -------------- +#define SAVE 0 +#define LOAD 1 +#define BMP 0 +#define DAT 1 +#define BUF 2 +#define CSV 3 +#define CFG 4 +#define DIR 3 + +//--------- BK_LIGHT & VOLUME sub menu item number defined -------- +#define CLASS 1 + +//============== METER main menu items defined number ============== +#define METER_0 13 +#define METER_1 14 +#define METER_2 15 +#define METER_3 16 +#define METER_4 17 +#define METER_5 18 +#define METER_6 19 +#define METER_7 20 +#define METER_8 21 + +//------------- METER in Item number defined ------------- + +#define VBT 0 +#define FPS 1 +#define VDC 2 +#define RMS 3 +#define FRQ 4 +#define MAX 5 +#define MIN 6 +#define VPP 7 +#define CIR 8 +#define DUT 9 +#define TH 10 +#define TL 11 + + +#define _Meas_V_Track (Title[V_VERNIE][2].Value) //Sorgente Delta V +#define _Meas_V_Range (Title[_Meas_V_Track][RANGE].Value) +#define _Meas_V_Scale (Y_Attr[_Meas_V_Range].SCALE) +#define _V1_Vernie (Title[V_VERNIE][0].Value) +#define _V2_Vernie (Title[V_VERNIE][1].Value) +#define _D_V_Source Title[V_VERNIE][2] +#define _Delta_V Title[V_VERNIE][3] +#define _Delta_T Title[T_VERNIE][3] +#define _T_Range (Title[T_BASE][1].Value) +#define _T_Scale (X_Attr[_T_Range].SCALE) +#define _T_KP (X_Attr[_T_Range].KP) + + +typedef struct +{ + char *Str; + u8 Track; + u8 Item; + uc16 XPOS1; + uc16 XPOS2; + uc8 YPOS; + u8 Flag; // HID=0x04, UPD=0x02, BLINK=0x01, +} meter; + + +typedef struct +{ + char *Str; + u16 *Color; + s16 Limit; // Max Value + uc8 MARK; // NUM=0x04, FIX=0x02, CIR=0x01, + u16 XPOS; + uc8 YPOS; + s16 Value; + u8 Flag; // HID=0x04, UPD=0x02, BLINK=0x01, +} menu; + +extern menu Title[13][4]; +extern meter Meter[9]; +extern u8 Current, Update,BTwink; +extern u8 Detail[14]; +extern char NumStr[12]; +extern u16 Result_FPS; +extern const char F_UNITSUB[12], F_UNIT[12], T_UNIT[12], S_UNIT[12], P_UNIT[12], V_UNIT[12]; +extern const char H_UNIT[15], DD_UNIT[15], MM_UNIT[15], VV_UNIT[12]; +extern char N_UNIT[12]; +extern u8 ConfigFileNumber; +extern s16 Ga_Max; +extern s16 Gb_Max; +extern s16 Ga_Min; +extern s16 Gb_Min; +extern s16 GHa_Max; +extern s16 GHb_Max; +extern s16 GHa_Min; +extern s16 GHb_Min; +extern s8 ShiftDigits; +extern u8 AutoFFT; +extern s8 GenFreqShift; +extern u8 GenAdjustMode; +extern uc16 Y_COLOR[5]; // Track Color 2 +extern uc8 TIM2Speed[10]; +extern u8 SweepMod; +extern u8 SweepStep; +extern u8 SweepIndex; +extern u8 Sweep; +extern s8 PrevShift; +extern u8 Det; +extern u8 GenTrigColorFlag; +extern u8 EnablePWM; +extern u8 PWAdjustMode; +extern u32 LastFreqReadout; +extern u8 EnableMeterCalc; +extern u8 T1Start; +extern u8 GenBaudAdjSpeed; +extern u32 GenBaudRate; +extern u8 GenUartMode; +extern u8 GenUartCont; +extern u8 GenUartAdj; +extern u16 GenBaudIndex; +extern u8 GenUartStopBits; +extern u8 FastDimAdjust; +extern u8 FastDim; +extern u8 AutoSaveBuf; +extern u8 AutoSaveSelect; +extern u8 AutoTrigSelect; +extern s8 OS_Range; +extern u8 OS_RateSelect; +extern u8 HboldAdjust; +extern u8 DETflag; +extern const char F_EXT[8][10]; +extern u8 ListOverride; +extern char EditChar[8][2]; +extern u8 CharIndex; +extern char CharValue; +extern u8 AdjBeepLevel; +extern char CursorDisplayStr[12]; +extern char CursorDisplayStrM[12]; +extern char CursorDisplayStrH[12]; +extern char VNumstr[12]; +extern const char DELTA_V[2][10]; +extern const char DELTA_T[2][4]; +extern char VNumStr[12]; +extern char TNumStr[12]; +extern u8 MinBypass; +extern u8 AutoSetFlag; +extern u8 AutoSequence; +extern u8 OldCurDefTime; +extern u16 OldPosi; +extern u8 MeterStatus; +extern u8 OldMode; +extern u8 Neg; +extern u8 DownConvertMode; + +void EnableMeter(void); +void DisableMeter(void); +void Display_Value(u8 i); +void Display_Title(void); +void Display_Meter(void); +void Load_Attr(void); +void Update_Battery(void); +void DisplayBigMeter(u8 MeterNum); +void MeterDefaults(void); +u32 UpScale(u32 Tmp, u16 limit); +void DisplaySamples(void); +void FFTlevel(u8 service); +void OutputAdjust(void); +void TIM_2IRQControl(void); +void GenTrigColor(void); +void UpdatePWMDuty(u8 service); +void AlignTbaseSweep(u8 dir); +u8 DetStatusLogic(u8 logic); +u8 ChartLogic(void); +void UpdateEditBox(u8 mode); +u8 ListLogic(void); +u8 EditListActive(u8 mode); +void CalculateVvernier(u8 mode); +void CalculateTvernier(u8 mode); +void AutoSet(void); +void UpdateMeterPage(void); +u16 KpCompensation(void); +u32 ClockAdjust(u32 Value); + +#endif + +/********************************* END OF FILE ********************************/ diff --git a/inc/Process.h b/inc/Process.h new file mode 100644 index 0000000..7bd2e17 --- /dev/null +++ b/inc/Process.h @@ -0,0 +1,273 @@ +/********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ******************** + File Name : Process.h + Version : DS203_APP Ver 2.3x Author : bure +*******************************************************************************/ +#ifndef __Process_h +#define __Process_h + +#include "stm32f10x_lib.h" +#include "Draw.h" + +//==================================================== +#define A 0 +#define B 1 +#define A_ 2 +#define B_ 3 + +//================== Structure variables, macro definitions ================== +#define _1_source Title[TRACK1][SOURCE].Value +#define _2_source Title[TRACK2][SOURCE].Value +#define _3_source Title[TRACK3][SOURCE].Value +#define _4_source Title[TRACK4][SOURCE].Value +#define _1_posi Title[TRACK1][POSI].Value +#define _2_posi Title[TRACK2][POSI].Value +#define _3_posi Title[TRACK3][POSI].Value +#define _4_posi Title[TRACK4][POSI].Value +#define _C_adj Title[TRACK3][RANGE].Value +#define _D_adj Title[TRACK4][RANGE].Value +#define _A_Range Title[TRACK1][RANGE].Value +#define _B_Range Title[TRACK2][RANGE].Value + +#define _Tr_source Title[TRIGG][SOURCE].Value +#define _Trigg Title[TRIGG] +#define _Tr_kind Title[TRIGG][TR_KIND].Value + +#define _File Title[FILE][0] + +#define _X_posi Title[T_BASE][XPOSI] +#define _X_View Title[T_BASE][VIEW] +#define _T_base Title[T_BASE][BASE].Value +#define _Mode (Title[T_BASE][MODE].Value) + +#define _A_Range Title[TRACK1][RANGE].Value +#define _B_Range Title[TRACK2][RANGE].Value + +#define _Kp1 X_Attr[Title[T_BASE][BASE].Value].KP // common sampling gear X interpolation coefficients +#define _Kp2 X_Attr[Title[T_BASE][BASE].Value+5].KP // X interpolation coefficients alternately sampling stalls +#define _INSERT G_Attr[0].INSERT // Start using the interpolated stalls + +#define _State Title[RUNNING][STATE] +#define _Status Title[RUNNING][STATE].Value + +#define _Curr Title[Current] +#define _Det Detail[Current] + +#define _Frqn Title[OUTPUT][FRQN].Value +#define _Kind Title[OUTPUT][KIND].Value +#define _Duty Title[OUTPUT][DUTYPWM].Value + +#define _T1 Title[T_VERNIE][T1].Value +#define _T2 Title[T_VERNIE][T2].Value + +#define _Vt1 V_Trigg[TRACK1].Value +#define _Vt2 V_Trigg[TRACK2].Value + +#define DHR12R1_DAC ((vu32)(0x40007400+0x08)); + +typedef struct // Âö³å²¨ÐÎÊä³öÇý¶¯±í +{ + uc16 PSC; // stall identification string + uc16 ARR; // frequency coefficient +} D_tab ; + +typedef struct{ + u16 Psc; + u16 Arr; + u16 S_OS_Size; + u16 Ratio; +}SubTbase; + +typedef struct{ + u16 Psc; + u16 Arr; +}OSTbase; + +typedef struct{ + u16 Psc; + u16 Arr; + u16 OS_Size; + u8 Limit; +}FPGAosTbase; + +extern u8 discard; +extern s16 Xtend; +extern u8 BailoutFlag; +extern u8 CurDefTime; +extern u16 NSamples; +extern u16 CountUnread; +extern u8 TrackBuff [397 * 4]; // X_Size presently set @ 392, some routines go to MAX_X (386+MIN_X or 397 w/meters off) +extern s32 a_Avg, b_Avg, a_Ssq, b_Ssq; +extern s16 a_Max, b_Max, a_Min, b_Min; // statistics of intermediate variables +extern s16 aT_Max, bT_Max, aT_Min, bT_Min; // for auto trig when using cursor restricted meters +extern u8 Rdiscard; +extern u8 FrameEndFlag; +extern u16 Tcs, Tcnt; + +extern u16 TaS, TbS, TcS, TdS; // cycles accumulated +extern u32 Sum[4]; +extern u16 NAvg[4]; +extern u16 VNAvg[2]; +extern s32 VxAvg[2]; +extern s32 VxSsq[2]; +extern u16 PaS, PbS, PcS, PdS; // pulse width of the cumulative +extern u16 TaN, TbN, TcN, TdN; // Cycle Count +extern u32 PxS[4]; +extern u32 TxS[4]; +extern u32 TxN[4]; +extern u8 FrameMode; +extern u8 FFTflag; +extern u8 EnableFFT; +extern uc16 A_Tab[17]; +extern D_tab D_Tab[23]; +extern const SubTbase TbaseSub[13]; +extern const FPGAosTbase FPGA_TbaseOS[20]; + +extern u8 Options; +extern u16 TempKp1; +extern u8 ADCoffset; +extern u8 CalFlag; +extern u16 JumpCnt; +extern s8 Kab; +extern s8 Ka1[10], Kb1[10]; +extern u16 Ka2[10], Kb2[10]; +extern s8 Ka3[10], Kb3[10]; +extern s8 HKa1[10], HKb1[10]; +extern u16 HKa2[10], HKb2[10]; +extern s8 HKa3[10], HKb3[10]; +extern s8 LKa1[10], LKb1[10]; +extern u16 LKa2[10], LKb2[10]; +extern s8 LKa3[10], LKb3[10]; +extern u32 DataBuf[4096]; // +extern u8 ScalingOffset; +extern char Vertical[15][10]; +extern s16 TrigSourceEnable; +extern u16 HiBatLevel[2]; +extern u16 LoBatLevel[2]; +extern u16 PrevBatLevel; +extern u16 VDiff[2]; +extern u8 SumResetFlag; +extern u8 EnablePaS; +extern u8 ClearHoldFlag; +extern u8 SlowModeSkip; +extern s16 A_Posi; +extern s16 B_Posi; +extern u8 ClearLeadingEdge; +extern u16 bag_max_buf; +extern u8 FFTGain; +extern u8 ClearMeterAreaFlag; +extern u16 BufferSize; +extern uc8 Log10Mant[100]; +extern u8 freerun; +extern uc8 ScaleIndex[17]; +extern s16 ATT_DATA[720]; +extern u8 Filter; +extern u16 NoiseBW; +extern u8 InitiateNoise; +extern u8 TriggerType; +extern s8 PrevSweepIndex; +extern u8 ResetFlag; +extern u16 ARBT_ARR; +extern uc32 A_Freq[18]; +extern s32 Waste; +extern u8 M_Factor; +extern u8 WaitForTrigFlag; +extern s16 Ch1TLevel; +extern s16 Ch2TLevel; +extern u8 SubIndex; +extern u8 StartUart; +extern u8 InitiateUartGen; +extern s16 WindowPosition; +extern u8 StartOffset; +extern u8 AutoTrigIni; +extern u8 OsBufferLogicFlag; +extern u8 OSAvg; +extern u8 PrevSource; +extern u8 PrevKind; +extern u8 OsFFTData[2][700]; +extern u8 RMSdata[2][700]; +extern u8 InvertA; +extern u8 InvertB; +extern u8 ScrollFlag; +extern u8 HardwareVersion; +extern u8 FPGAver; +extern u8 FreeRunEnable; +extern u8 FPGAsubVer; +extern u8 FPGAosFlag; +extern u16 FPGA_OS_Size; +extern u8 OffsetSelect; +extern u8 ResetEnableFFT; +extern u8 FastMode; +extern u8 ChartMode; +extern u8 OsChartFlag; +extern u8 ToggleName; +extern u8 DisableCursorTimer; +extern u16 DownConvert; +extern u32 FreqIN; +extern u8 DownConvertInitiate; +extern u32 FFTScale; +extern u8 DCbase; +extern u8 DCframe; +extern u8 DCmode; +extern u8 DCmeter; +extern u8 FreqScaleShift; +extern u8 DownConvertShiftEnable; +extern u32 LfreqPeriod; +extern u8 FFTt1Mode; +extern u16 DCt1; + +void BackGround_Reset(u8 clear); +void App_init(u8 ClearScreen); +void View_init(void); +void Update_Range(void); +void Update_Base(void); +void Update_Output(void); +void Update_Trig(u8 service); +void Process(void); +void Synchro(void); +void Send_Data(s16 Va, s16 Vb, u8 C_D, u8 osB, u16 n); +u16 get_bag_max_buf(); +void cleardatabuf(u8 service); +void Config_init(void); +void TransferFIFO(s16 i,u8 service); +void SetOffset(u8 channel,u8 range, s16 Ypos); +void BatLevelCompensation(void); +void ResetSum(void); +void ClearMinMax(u8 Channels); +void ClearHold(u8 Channels); +void ClearTrackBuff(u8 service); +void Beeper(u16 ms); +void WaveGen(void); +void InitiateCalData(void); +u16 RandomGen(void); +void SetIRQ2Priority(void); +void ResetDMA2_Ch4Params(u32 Count); +void ClearMeters(void); +u8 OSBufferLogic(void); +void InitiateOSBuffers(void); +u16 GetXposRef(u16 XPos); +u16 GetXpos(u16 XposRef); +void UpdateCursorMeter(void); +void CursorDisplaySelectLogic(void); +void FFTdownConvert(u8 service); +void DownConvertRestore(void); + +// FFT //////////////////////////////////////////////////////////////////// + +extern s32 fr[]; +extern s32 fi[]; + +extern u8 ShowFFT; +extern u32 NFreq; +extern char NFreqStr[]; +extern int imax; +extern short PeakFreq; +extern char BaseFreqStr[]; +extern char PeakFreqStr[]; +extern char FreqDivStr[]; +extern char FreqT1Str[]; + +///////////////////////////////////////////////////////////// FFT /////// + + +#endif +/******************************** END OF FILE *********************************/ diff --git a/inc/stm32f10x_conf.h b/inc/stm32f10x_conf.h new file mode 100644 index 0000000..90c1568 --- /dev/null +++ b/inc/stm32f10x_conf.h @@ -0,0 +1,175 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_conf.h +* Author : MCD Application Team +* Version : V2.2.1 +* Date : 09/22/2008 +* Description : Library configuration file. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CONF_H +#define __STM32F10x_CONF_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_type.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to compile the library in DEBUG mode, this will expanse + the "assert_param" macro in the firmware library code (see "Exported macro" + section below) */ +/* #define DEBUG 1*/ + +/* Comment the line below to disable the specific peripheral inclusion */ +/************************************* ADC ************************************/ +//#define _ADC +//#define _ADC1 +//#define _ADC2 +//#define _ADC3 + +/************************************* BKP ************************************/ +//#define _BKP + +/************************************* CAN ************************************/ +//#define _CAN + +/************************************* CRC ************************************/ +//#define _CRC + +/************************************* DAC ************************************/ +#define _DAC + +/************************************* DBGMCU *********************************/ +//#define _DBGMCU + +/************************************* DMA ************************************/ +#define _DMA +//#define _DMA1_Channel1 +//#define _DMA1_Channel2 +//#define _DMA1_Channel3 +#define _DMA1_Channel4 //used by USART1 +//#define _DMA1_Channel5 +//#define _DMA1_Channel6 +//#define _DMA1_Channel7 +//#define _DMA2_Channel1 +//#define _DMA2_Channel2 +//#define _DMA2_Channel3 +#define _DMA2_Channel4 +//#define _DMA2_Channel5 + +/************************************* EXTI ***********************************/ +//#define _EXTI + +/************************************* FLASH and Option Bytes *****************/ +#define _FLASH +/* Uncomment the line below to enable FLASH program/erase/protections functions, + otherwise only FLASH configuration (latency, prefetch, half cycle) functions + are enabled */ + #define _FLASH_PROG + +/************************************* FSMC ***********************************/ +#define _FSMC + +/************************************* GPIO ***********************************/ + +#define _GPIO +#define _GPIOA +#define _GPIOB +#define _GPIOC +#define _GPIOD +#define _GPIOE +#define _GPIOF +#define _GPIOG +#define _AFIO + +/************************************* I2C ************************************/ +//#define _I2C +//#define _I2C1 +//#define _I2C2 + +/************************************* IWDG ***********************************/ +//#define _IWDG + +/************************************* NVIC ***********************************/ +#define _NVIC + +/************************************* PWR ************************************/ +//#define _PWR + +/************************************* RCC ************************************/ +#define _RCC + +/************************************* RTC ************************************/ +//#define _RTC + +/************************************* SDIO ***********************************/ +#define _SDIO + +/************************************* SPI ************************************/ +#define _SPI +#define _SPI1 +#define _SPI2 +#define _SPI3 + +/************************************* SysTick ********************************/ +//#define _SysTick + +/************************************* TIM ************************************/ +//#define _TIM +#define _TIM1 //enabled for experimental chart mode +#define _TIM2 +#define _TIM3 +#define _TIM4 +//#define _TIM5 +#define _TIM6 +#define _TIM7 +//#define _TIM8 + +/************************************* USART **********************************/ +//#define _USART +#define _USART1 +//#define _USART2 +//#define _USART3 +//#define _UART4 +//#define _UART5 + +/************************************* WWDG ***********************************/ +//#define _WWDG + +/* In the following line adjust the value of External High Speed oscillator (HSE) + used in your application */ +#define HSE_Value ((u32)8000000) /* Value of the External oscillator in Hz*/ + +/* In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value */ +#define HSEStartUp_TimeOut ((u16)0x0500) /* Time out for HSE start up */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef DEBUG +/******************************************************************************* +* Macro Name : assert_param +* Description : The assert_param macro is used for function's parameters check. +* It is used only if the library is compiled in DEBUG mode. +* Input : - expr: If expr is false, it calls assert_failed function +* which reports the name of the source file and the source +* line number of the call that failed. +* If expr is true, it returns no value. +* Return : None +*******************************************************************************/ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(u8* file, u32 line); +#else + #define assert_param(expr) ((void)0) +#endif /* DEBUG */ + +#endif /* __STM32F10x_CONF_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/startup.c b/startup.c new file mode 100644 index 0000000..0d5c4d2 --- /dev/null +++ b/startup.c @@ -0,0 +1,311 @@ +#include "stm32f10x_lib.h" +#include "Interrupt.h" + +typedef void( *const intfunc )( void ); + +#define WEAK __attribute__ ((weak)) + +extern unsigned long _etext; +extern unsigned long _sidata; +extern unsigned long _sdata; +extern unsigned long _edata; +extern unsigned long _sbss; +extern unsigned long _ebss; +extern unsigned long _estack; + +void Reset_Handler(void) __attribute__((__interrupt__)); +void __Init_Data(void); +void Default_Handler(void); + +extern int main(void); +extern void __libc_init_array(void); + +void WEAK NMI_Handler(void); +void WEAK HardFault_Handler(void); +void WEAK MemManage_Handler(void); +void WEAK BusFault_Handler(void); +void WEAK UsageFault_Handler(void); +void WEAK MemManage_Handler(void); +void WEAK SVC_Handler(void); +void WEAK DebugMon_Handler(void); +void WEAK PendSV_Handler(void); +void WEAK SysTick_Handler(void); + +void WEAK WWDG_IRQHandler(void); +void WEAK PVD_IRQHandler(void); +void WEAK TAMPER_IRQHandler(void); +void WEAK RTC_IRQHandler(void); +void WEAK FLASH_IRQHandler(void); +void WEAK RCC_IRQHandler(void); +void WEAK EXTI0_IRQHandler(void); +void WEAK EXTI1_IRQHandler(void); +void WEAK EXTI2_IRQHandler(void); +void WEAK EXTI3_IRQHandler(void); +void WEAK EXTI4_IRQHandler(void); +void WEAK DMA1_Channel1_IRQHandler(void); +void WEAK DMA1_Channel2_IRQHandler(void); +void WEAK DMA1_Channel3_IRQHandler(void); +void WEAK DMA1_Channel4_IRQHandler(void); +void WEAK DMA1_Channel5_IRQHandler(void); +void WEAK DMA1_Channel6_IRQHandler(void); +void WEAK DMA1_Channel7_IRQHandler(void); +void WEAK ADC1_2_IRQHandler(void); +void WEAK USB_HP_CAN1_TX_IRQHandler(void); +void WEAK USB_LP_CAN1_RX0_IRQHandler(void); +void WEAK CAN1_RX1_IRQHandler(void); +void WEAK CAN1_SCE_IRQHandler(void); +void WEAK EXTI9_5_IRQHandler(void); +void WEAK TIM1_BRK_IRQHandler(void); +void WEAK TIM1_UP_IRQHandler(void); +void WEAK TIM1_TRG_COM_IRQHandler(void); +void WEAK TIM1_CC_IRQHandler(void); +void WEAK TIM2_IRQHandler(void); +void WEAK TIM3_IRQHandler(void); +void WEAK TIM4_IRQHandler(void); +void WEAK I2C1_EV_IRQHandler(void); +void WEAK I2C1_ER_IRQHandler(void); +void WEAK I2C2_EV_IRQHandler(void); +void WEAK I2C2_ER_IRQHandler(void); +void WEAK SPI1_IRQHandler(void); +void WEAK SPI2_IRQHandler(void); +void WEAK USART1_IRQHandler(void); +void WEAK USART2_IRQHandler(void); +void WEAK USART3_IRQHandler(void); +void WEAK EXTI15_10_IRQHandler(void); +void WEAK RTCAlarm_IRQHandler(void); +void WEAK USBWakeUp_IRQHandler(void); +void WEAK TIM8_BRK_IRQHandler(void); +void WEAK TIM8_UP_IRQHandler(void); +void WEAK TIM8_TRG_COM_IRQHandler(void); +void WEAK TIM8_CC_IRQHandler(void); +void WEAK ADC3_IRQHandler(void); +void WEAK FSMC_IRQHandler(void); +void WEAK SDIO_IRQHandler(void); +void WEAK TIM5_IRQHandler(void); +void WEAK SPI3_IRQHandler(void); +void WEAK UART4_IRQHandler(void); +void WEAK UART5_IRQHandler(void); +void WEAK TIM6_IRQHandler(void); +void WEAK TIM7_IRQHandler(void); +void WEAK DMA2_Channel1_IRQHandler(void); +void WEAK DMA2_Channel2_IRQHandler(void); +void WEAK DMA2_Channel3_IRQHandler(void); +void WEAK DMA2_Channel4_5_IRQHandler(void); + +__attribute__ ((section(".isr_vectors"))) +void (* const g_pfnVectors[])(void) = { + (intfunc)((unsigned long)&_estack), /* The stack pointer after relocation */ +#if 0 + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* NMI Handler */ + HardFault_Handler, /* Hard Fault Handler */ + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, /* Bus Fault Handler */ + UsageFault_Handler, /* Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* SVCall Handler */ + DebugMon_Handler, /* Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* PendSV Handler */ + SysTick_Handler, /* SysTick Handler */ + + /* External Interrupts */ + WWDG_IRQHandler, /* Window Watchdog */ + PVD_IRQHandler, /* PVD through EXTI Line detect */ + TAMPER_IRQHandler, /* Tamper */ + RTC_IRQHandler, /* RTC */ + FLASH_IRQHandler, /* Flash */ + RCC_IRQHandler, /* RCC */ + EXTI0_IRQHandler, /* EXTI Line 0 */ + EXTI1_IRQHandler, /* EXTI Line 1 */ + EXTI2_IRQHandler, /* EXTI Line 2 */ + EXTI3_IRQHandler, /* EXTI Line 3 */ + EXTI4_IRQHandler, /* EXTI Line 4 */ + DMA1_Channel1_IRQHandler, /* DMA1 Channel 1 */ + DMA1_Channel2_IRQHandler, /* DMA1 Channel 2 */ + DMA1_Channel3_IRQHandler, /* DMA1 Channel 3 */ + DMA1_Channel4_IRQHandler, /* DMA1 Channel 4 */ + DMA1_Channel5_IRQHandler, /* DMA1 Channel 5 */ + DMA1_Channel6_IRQHandler, /* DMA1 Channel 6 */ + DMA1_Channel7_IRQHandler, /* DMA1 Channel 7 */ + ADC1_2_IRQHandler, /* ADC1 & ADC2 */ + USB_HP_CAN1_TX_IRQHandler, /* USB High Priority or CAN1 TX */ + USB_LP_CAN1_RX0_IRQHandler, /* USB Low Priority or CAN1 RX0 */ + CAN1_RX1_IRQHandler, /* CAN1 RX1 */ + CAN1_SCE_IRQHandler, /* CAN1 SCE */ + EXTI9_5_IRQHandler, /* EXTI Line 9..5 */ + TIM1_BRK_IRQHandler, /* TIM1 Break */ + TIM1_UP_IRQHandler, /* TIM1 Update */ + TIM1_TRG_COM_IRQHandler, /* TIM1 Trigger and Commutation */ + TIM1_CC_IRQHandler, /* TIM1 Capture Compare */ + TIM2_IRQHandler, /* TIM2 */ + TIM3_IRQHandler, /* TIM3 */ + TIM4_IRQHandler, /* TIM4 */ + I2C1_EV_IRQHandler, /* I2C1 Event */ + I2C1_ER_IRQHandler, /* I2C1 Error */ + I2C2_EV_IRQHandler, /* I2C2 Event */ + I2C2_ER_IRQHandler, /* I2C2 Error */ + SPI1_IRQHandler, /* SPI1 */ + SPI2_IRQHandler, /* SPI2 */ + USART1_IRQHandler, /* USART1 */ + USART2_IRQHandler, /* USART2 */ + USART3_IRQHandler, /* USART3 */ + EXTI15_10_IRQHandler, /* EXTI Line 15..10 */ + RTCAlarm_IRQHandler, /* RTC Alarm through EXTI Line */ + USBWakeUp_IRQHandler, /* USB Wakeup from suspend */ + TIM8_BRK_IRQHandler, + TIM8_UP_IRQHandler, + TIM8_TRG_COM_IRQHandler, + TIM8_CC_IRQHandler, + ADC3_IRQHandler, + FSMC_IRQHandler, + SDIO_IRQHandler, + TIM5_IRQHandler, + SPI3_IRQHandler, + UART4_IRQHandler, + UART5_IRQHandler, + TIM6_IRQHandler, + TIM7_IRQHandler, + DMA2_Channel1_IRQHandler, + DMA2_Channel2_IRQHandler, + DMA2_Channel3_IRQHandler, + DMA2_Channel4_5_IRQHandler, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, + (intfunc)0xF1E0F85F /* @0x1E0. This is for boot in RAM mode for STM32F10x High Density devices. */ +#endif +Reset_Handler, NMIException, HardFaultException, +MemManageException, BusFaultException, UsageFaultException, 0, 0, +0, 0, SVCHandler, DebugMonitor, 0, PendSVC, SysTickHandler, +WWDG_IRQHandler, PVD_IRQHandler, TAMPER_IRQHandler, RTC_IRQHandler, +FLASH_IRQHandler, RCC_IRQHandler, EXTI0_IRQHandler, +EXTI1_IRQHandler, EXTI2_IRQHandler, EXTI3_IRQHandler, +EXTI4_IRQHandler, DMA1_Channel1_IRQHandler, +DMA1_Channel2_IRQHandler, DMA1_Channel3_IRQHandler, +DMA1_Channel4_IRQHandler, DMA1_Channel5_IRQHandler, +DMA1_Channel6_IRQHandler, DMA1_Channel7_IRQHandler, +ADC1_2_IRQHandler, USB_HP_CAN_TX_IRQHandler, +USB_LP_CAN_RX0_IRQHandler, CAN_RX1_IRQHandler, CAN_SCE_IRQHandler, +EXTI9_5_IRQHandler, TIM1_BRK_IRQHandler, TIM1_UP_IRQHandler, +TIM1_TRG_COM_IRQHandler, TIM1_CC_IRQHandler, TIM2_IRQHandler, +TIM3_IRQHandler, TIM4_IRQHandler, I2C1_EV_IRQHandler, +I2C1_ER_IRQHandler, I2C2_EV_IRQHandler, I2C2_ER_IRQHandler, +SPI1_IRQHandler, SPI2_IRQHandler, USART1_IRQHandler, +USART2_IRQHandler, USART3_IRQHandler, EXTI15_10_IRQHandler, +RTCAlarm_IRQHandler, USBWakeUp_IRQHandler, TIM8_BRK_IRQHandler, +TIM8_UP_IRQHandler, TIM8_TRG_COM_IRQHandler, TIM8_CC_IRQHandler, +ADC3_IRQHandler, FSMC_IRQHandler, SDIO_IRQHandler, TIM5_IRQHandler, +SPI3_IRQHandler, UART4_IRQHandler, UART5_IRQHandler, +TIM6_IRQHandler, TIM7_IRQHandler, DMA2_Channel1_IRQHandler, +DMA2_Channel2_IRQHandler, DMA2_Channel3_IRQHandler, +DMA2_Channel4_5_IRQHandler +}; + +void __Init_Data(void) { + unsigned long *src, *dst; + /* copy the data segment into ram */ + src = &_sidata; + dst = &_sdata; + if (src != dst) + while(dst < &_edata) + *(dst++) = *(src++); + + /* zero the bss segment */ + dst = &_sbss; + while(dst < &_ebss) + *(dst++) = 0; +} + +void Reset_Handler(void) { + /* Initialize data and bss */ + __Init_Data(); + main(); + while(1) {} +} + +#pragma weak MMI_Handler = Default_Handler +#pragma weak MemManage_Handler = Default_Handler +#pragma weak BusFault_Handler = Default_Handler +#pragma weak UsageFault_Handler = Default_Handler +#pragma weak SVC_Handler = Default_Handler +#pragma weak DebugMon_Handler = Default_Handler +#pragma weak PendSV_Handler = Default_Handler +#pragma weak SysTick_Handler = Default_Handler +#pragma weak WWDG_IRQHandler = Default_Handler +#pragma weak PVD_IRQHandler = Default_Handler +#pragma weak TAMPER_IRQHandler = Default_Handler +#pragma weak RTC_IRQHandler = Default_Handler +#pragma weak FLASH_IRQHandler = Default_Handler +#pragma weak RCC_IRQHandler = Default_Handler +#pragma weak EXTI0_IRQHandler = Default_Handler +#pragma weak EXTI1_IRQHandler = Default_Handler +#pragma weak EXTI2_IRQHandler = Default_Handler +#pragma weak EXTI3_IRQHandler = Default_Handler +#pragma weak EXTI4_IRQHandler = Default_Handler +#pragma weak DMA1_Channel1_IRQHandler = Default_Handler +#pragma weak DMA1_Channel2_IRQHandler = Default_Handler +#pragma weak DMA1_Channel3_IRQHandler = Default_Handler +#pragma weak DMA1_Channel4_IRQHandler = Default_Handler +#pragma weak DMA1_Channel5_IRQHandler = Default_Handler +#pragma weak DMA1_Channel6_IRQHandler = Default_Handler +#pragma weak DMA1_Channel7_IRQHandler = Default_Handler +#pragma weak ADC1_2_IRQHandler = Default_Handler +#pragma weak USB_HP_CAN1_TX_IRQHandler = Default_Handler +#pragma weak USB_LP_CAN1_RX0_IRQHandler = Default_Handler +#pragma weak CAN1_RX1_IRQHandler = Default_Handler +#pragma weak CAN1_SCE_IRQHandler = Default_Handler +#pragma weak EXTI9_5_IRQHandler = Default_Handler +#pragma weak TIM1_BRK_IRQHandler = Default_Handler +#pragma weak TIM1_UP_IRQHandler = Default_Handler +#pragma weak TIM1_TRG_COM_IRQHandler = Default_Handler +#pragma weak TIM1_CC_IRQHandler = Default_Handler +#pragma weak TIM2_IRQHandler = Default_Handler +#pragma weak TIM3_IRQHandler = Default_Handler +#pragma weak TIM4_IRQHandler = Default_Handler +#pragma weak I2C1_EV_IRQHandler = Default_Handler +#pragma weak I2C1_ER_IRQHandler = Default_Handler +#pragma weak I2C2_EV_IRQHandler = Default_Handler +#pragma weak I2C2_ER_IRQHandler = Default_Handler +#pragma weak SPI1_IRQHandler = Default_Handler +#pragma weak SPI2_IRQHandler = Default_Handler +#pragma weak USART1_IRQHandler = Default_Handler +#pragma weak USART2_IRQHandler = Default_Handler +#pragma weak USART3_IRQHandler = Default_Handler +#pragma weak EXTI15_10_IRQHandler = Default_Handler +#pragma weak RTCAlarm_IRQHandler = Default_Handler +#pragma weak USBWakeUp_IRQHandler = Default_Handler +#pragma weak TIM8_BRK_IRQHandler = Default_Handler +#pragma weak TIM8_UP_IRQHandler = Default_Handler +#pragma weak TIM8_TRG_COM_IRQHandler = Default_Handler +#pragma weak TIM8_CC_IRQHandler = Default_Handler +#pragma weak ADC3_IRQHandler = Default_Handler +#pragma weak FSMC_IRQHandler = Default_Handler +#pragma weak SDIO_IRQHandler = Default_Handler +#pragma weak TIM5_IRQHandler = Default_Handler +#pragma weak SPI3_IRQHandler = Default_Handler +#pragma weak UART4_IRQHandler = Default_Handler +#pragma weak UART5_IRQHandler = Default_Handler +#pragma weak TIM6_IRQHandler = Default_Handler +#pragma weak TIM7_IRQHandler = Default_Handler +#pragma weak DMA2_Channel1_IRQHandler = Default_Handler +#pragma weak DMA2_Channel2_IRQHandler = Default_Handler +#pragma weak DMA2_Channel3_IRQHandler = Default_Handler +#pragma weak DMA2_Channel4_5_IRQHandler = Default_Handler + +void Default_Handler(void) { + while (1) {} +} + +void _init(void) +{ +} diff --git a/stm32f10x_nvic.c b/stm32f10x_nvic.c new file mode 100644 index 0000000..90dd5bc --- /dev/null +++ b/stm32f10x_nvic.c @@ -0,0 +1,751 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_nvic.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the NVIC firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_nvic.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define AIRCR_VECTKEY_MASK ((u32)0x05FA0000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : NVIC_DeInit +* Description : Deinitializes the NVIC peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_DeInit(void) +{ + u32 index = 0; + + NVIC->ICER[0] = 0xFFFFFFFF; + NVIC->ICER[1] = 0x0FFFFFFF; + NVIC->ICPR[0] = 0xFFFFFFFF; + NVIC->ICPR[1] = 0x0FFFFFFF; + + for(index = 0; index < 0x0F; index++) + { + NVIC->IPR[index] = 0x00000000; + } +} + +/******************************************************************************* +* Function Name : NVIC_SCBDeInit +* Description : Deinitializes the SCB peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SCBDeInit(void) +{ + u32 index = 0x00; + + SCB->ICSR = 0x0A000000; + SCB->VTOR = 0x00000000; + SCB->AIRCR = AIRCR_VECTKEY_MASK; + SCB->SCR = 0x00000000; + SCB->CCR = 0x00000000; + for(index = 0; index < 0x03; index++) + { + SCB->SHPR[index] = 0; + } + SCB->SHCSR = 0x00000000; + SCB->CFSR = 0xFFFFFFFF; + SCB->HFSR = 0xFFFFFFFF; + SCB->DFSR = 0xFFFFFFFF; +} + +/******************************************************************************* +* Function Name : NVIC_PriorityGroupConfig +* Description : Configures the priority grouping: pre-emption priority +* and subpriority. +* Input : - NVIC_PriorityGroup: specifies the priority grouping bits +* length. This parameter can be one of the following values: +* - NVIC_PriorityGroup_0: 0 bits for pre-emption priority +* 4 bits for subpriority +* - NVIC_PriorityGroup_1: 1 bits for pre-emption priority +* 3 bits for subpriority +* - NVIC_PriorityGroup_2: 2 bits for pre-emption priority +* 2 bits for subpriority +* - NVIC_PriorityGroup_3: 3 bits for pre-emption priority +* 1 bits for subpriority +* - NVIC_PriorityGroup_4: 4 bits for pre-emption priority +* 0 bits for subpriority +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/******************************************************************************* +* Function Name : NVIC_Init +* Description : Initializes the NVIC peripheral according to the specified +* parameters in the NVIC_InitStruct. +* Input : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure +* that contains the configuration information for the +* specified NVIC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + u32 tmppriority = 0x00, tmpreg = 0x00, tmpmask = 0x00; + u32 tmppre = 0, tmpsub = 0x0F; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_InitStruct->NVIC_IRQChannel)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - (SCB->AIRCR & (u32)0x700))>> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = (u32)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; + + tmppriority = tmppriority << 0x04; + tmppriority = ((u32)tmppriority) << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08); + + tmpreg = NVIC->IPR[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)]; + tmpmask = (u32)0xFF << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08); + tmpreg &= ~tmpmask; + tmppriority &= tmpmask; + tmpreg |= tmppriority; + + NVIC->IPR[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)] = tmpreg; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] = + (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] = + (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F); + } +} + +/******************************************************************************* +* Function Name : NVIC_StructInit +* Description : Fills each NVIC_InitStruct member with its default value. +* Input : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct) +{ + /* NVIC_InitStruct members default value */ + NVIC_InitStruct->NVIC_IRQChannel = 0x00; + NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority = 0x00; + NVIC_InitStruct->NVIC_IRQChannelSubPriority = 0x00; + NVIC_InitStruct->NVIC_IRQChannelCmd = DISABLE; +} + +/******************************************************************************* +* Function Name : NVIC_SETPRIMASK +* Description : Enables the PRIMASK priority: Raises the execution priority to 0. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SETPRIMASK(void) +{ + __SETPRIMASK(); +} + +/******************************************************************************* +* Function Name : NVIC_RESETPRIMASK +* Description : Disables the PRIMASK priority. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_RESETPRIMASK(void) +{ + __RESETPRIMASK(); +} + +/******************************************************************************* +* Function Name : NVIC_SETFAULTMASK +* Description : Enables the FAULTMASK priority: Raises the execution priority to -1. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SETFAULTMASK(void) +{ + __SETFAULTMASK(); +} + +/******************************************************************************* +* Function Name : NVIC_RESETFAULTMASK +* Description : Disables the FAULTMASK priority. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_RESETFAULTMASK(void) +{ + __RESETFAULTMASK(); +} + +/******************************************************************************* +* Function Name : NVIC_BASEPRICONFIG +* Description : The execution priority can be changed from 15 (lowest + configurable priority) to 1. Writing a zero value will disable +* the mask of execution priority. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_BASEPRICONFIG(u32 NewPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_BASE_PRI(NewPriority)); + + __BASEPRICONFIG(NewPriority << 0x04); +} + +/******************************************************************************* +* Function Name : NVIC_GetBASEPRI +* Description : Returns the BASEPRI mask value. +* Input : None +* Output : None +* Return : BASEPRI register value +*******************************************************************************/ +u32 NVIC_GetBASEPRI(void) +{ + return (__GetBASEPRI()); +} + +/******************************************************************************* +* Function Name : NVIC_GetCurrentPendingIRQChannel +* Description : Returns the current pending IRQ channel identifier. +* Input : None +* Output : None +* Return : Pending IRQ Channel Identifier. +*******************************************************************************/ +u16 NVIC_GetCurrentPendingIRQChannel(void) +{ + return ((u16)((SCB->ICSR & (u32)0x003FF000) >> 0x0C)); +} + +/******************************************************************************* +* Function Name : NVIC_GetIRQChannelPendingBitStatus +* Description : Checks whether the specified IRQ Channel pending bit is set +* or not. +* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to check. +* Output : None +* Return : The new state of IRQ Channel pending bit(SET or RESET). +*******************************************************************************/ +ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel) +{ + ITStatus pendingirqstatus = RESET; + u32 tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel)); + + tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F)); + + if (((NVIC->ISPR[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp) + { + pendingirqstatus = SET; + } + else + { + pendingirqstatus = RESET; + } + return pendingirqstatus; +} + +/******************************************************************************* +* Function Name : NVIC_SetIRQChannelPendingBit +* Description : Sets the NVIC’s interrupt pending bit. +* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to Set. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel) +{ + /* Check the parameters */ + assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel)); + + *(vu32*) 0xE000EF00 = (u32)NVIC_IRQChannel; +} + +/******************************************************************************* +* Function Name : NVIC_ClearIRQChannelPendingBit +* Description : Clears the NVIC’s interrupt pending bit. +* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to clear. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel) +{ + /* Check the parameters */ + assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel)); + + NVIC->ICPR[(NVIC_IRQChannel >> 0x05)] = (u32)0x01 << (NVIC_IRQChannel & (u32)0x1F); +} + +/******************************************************************************* +* Function Name : NVIC_GetCurrentActiveHandler +* Description : Returns the current active Handler (IRQ Channel and +* SystemHandler) identifier. +* Input : None +* Output : None +* Return : Active Handler Identifier. +*******************************************************************************/ +u16 NVIC_GetCurrentActiveHandler(void) +{ + return ((u16)(SCB->ICSR & (u32)0x3FF)); +} + +/******************************************************************************* +* Function Name : NVIC_GetIRQChannelActiveBitStatus +* Description : Checks whether the specified IRQ Channel active bit is set +* or not. +* Input : - NVIC_IRQChannel: specifies the interrupt active bit to check. +* Output : None +* Return : The new state of IRQ Channel active bit(SET or RESET). +*******************************************************************************/ +ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel) +{ + ITStatus activeirqstatus = RESET; + u32 tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel)); + + tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F)); + + if (((NVIC->IABR[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp ) + { + activeirqstatus = SET; + } + else + { + activeirqstatus = RESET; + } + return activeirqstatus; +} + +/******************************************************************************* +* Function Name : NVIC_GetCPUID +* Description : Returns the ID number, the version number and the implementation +* details of the Cortex-M3 core. +* Input : None +* Output : None +* Return : CPU ID. +*******************************************************************************/ +u32 NVIC_GetCPUID(void) +{ + return (SCB->CPUID); +} + +/******************************************************************************* +* Function Name : NVIC_SetVectorTable +* Description : Sets the vector table location and Offset. +* Input : - NVIC_VectTab: specifies if the vector table is in RAM or +* FLASH memory. +* This parameter can be one of the following values: +* - NVIC_VectTab_RAM +* - NVIC_VectTab_FLASH +* - Offset: Vector Table base offset field. +* This value must be a multiple of 0x100. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset) +{ + /* Check the parameters */ + assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (u32)0x1FFFFF80); +} + +/******************************************************************************* +* Function Name : NVIC_GenerateSystemReset +* Description : Generates a system reset. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_GenerateSystemReset(void) +{ + SCB->AIRCR = AIRCR_VECTKEY_MASK | (u32)0x04; +} + +/******************************************************************************* +* Function Name : NVIC_GenerateCoreReset +* Description : Generates a Core (Core + NVIC) reset. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_GenerateCoreReset(void) +{ + SCB->AIRCR = AIRCR_VECTKEY_MASK | (u32)0x01; +} + +/******************************************************************************* +* Function Name : NVIC_SystemLPConfig +* Description : Selects the condition for the system to enter low power mode. +* Input : - LowPowerMode: Specifies the new mode for the system to enter +* low power mode. +* This parameter can be one of the following values: +* - NVIC_LP_SEVONPEND +* - NVIC_LP_SLEEPDEEP +* - NVIC_LP_SLEEPONEXIT +* - NewState: new state of LP condition. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (u32)(~(u32)LowPowerMode); + } +} + +/******************************************************************************* +* Function Name : NVIC_SystemHandlerConfig +* Description : Enables or disables the specified System Handlers. +* Input : - SystemHandler: specifies the system handler to be enabled +* or disabled. +* This parameter can be one of the following values: +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* - SystemHandler_UsageFault +* - NewState: new state of specified System Handlers. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState) +{ + u32 tmpreg = 0x00; + + /* Check the parameters */ + assert_param(IS_CONFIG_SYSTEM_HANDLER(SystemHandler)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + tmpreg = (u32)0x01 << (SystemHandler & (u32)0x1F); + + if (NewState != DISABLE) + { + SCB->SHCSR |= tmpreg; + } + else + { + SCB->SHCSR &= ~tmpreg; + } +} + +/******************************************************************************* +* Function Name : NVIC_SystemHandlerPriorityConfig +* Description : Configures the specified System Handlers priority. +* Input : - SystemHandler: specifies the system handler to be +* enabled or disabled. +* This parameter can be one of the following values: +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* - SystemHandler_UsageFault +* - SystemHandler_SVCall +* - SystemHandler_DebugMonitor +* - SystemHandler_PSV +* - SystemHandler_SysTick +* - SystemHandlerPreemptionPriority: new priority group of the +* specified system handlers. +* - SystemHandlerSubPriority: new sub priority of the specified +* system handlers. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority, + u8 SystemHandlerSubPriority) +{ + u32 tmp1 = 0x00, tmp2 = 0xFF, handlermask = 0x00; + u32 tmppriority = 0x00; + + /* Check the parameters */ + assert_param(IS_PRIORITY_SYSTEM_HANDLER(SystemHandler)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(SystemHandlerPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(SystemHandlerSubPriority)); + + tmppriority = (0x700 - (SCB->AIRCR & (u32)0x700))>> 0x08; + tmp1 = (0x4 - tmppriority); + tmp2 = tmp2 >> tmppriority; + + tmppriority = (u32)SystemHandlerPreemptionPriority << tmp1; + tmppriority |= SystemHandlerSubPriority & tmp2; + + tmppriority = tmppriority << 0x04; + tmp1 = SystemHandler & (u32)0xC0; + tmp1 = tmp1 >> 0x06; + tmp2 = (SystemHandler >> 0x08) & (u32)0x03; + tmppriority = tmppriority << (tmp2 * 0x08); + handlermask = (u32)0xFF << (tmp2 * 0x08); + + SCB->SHPR[tmp1] &= ~handlermask; + SCB->SHPR[tmp1] |= tmppriority; +} + +/******************************************************************************* +* Function Name : NVIC_GetSystemHandlerPendingBitStatus +* Description : Checks whether the specified System handlers pending bit is +* set or not. +* Input : - SystemHandler: specifies the system handler pending bit to +* check. +* This parameter can be one of the following values: +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* - SystemHandler_SVCall +* Output : None +* Return : The new state of System Handler pending bit(SET or RESET). +*******************************************************************************/ +ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler) +{ + ITStatus bitstatus = RESET; + u32 tmp = 0x00, tmppos = 0x00; + + /* Check the parameters */ + assert_param(IS_GET_PENDING_SYSTEM_HANDLER(SystemHandler)); + + tmppos = (SystemHandler >> 0x0A); + tmppos &= (u32)0x0F; + + tmppos = (u32)0x01 << tmppos; + + tmp = SCB->SHCSR & tmppos; + + if (tmp == tmppos) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : NVIC_SetSystemHandlerPendingBit +* Description : Sets System Handler pending bit. +* Input : - SystemHandler: specifies the system handler pending bit +* to be set. +* This parameter can be one of the following values: +* - SystemHandler_NMI +* - SystemHandler_PSV +* - SystemHandler_SysTick +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler) +{ + u32 tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_SET_PENDING_SYSTEM_HANDLER(SystemHandler)); + + /* Get the System Handler pending bit position */ + tmp = SystemHandler & (u32)0x1F; + /* Set the corresponding System Handler pending bit */ + SCB->ICSR |= ((u32)0x01 << tmp); +} + +/******************************************************************************* +* Function Name : NVIC_ClearSystemHandlerPendingBit +* Description : Clears System Handler pending bit. +* Input : - SystemHandler: specifies the system handler pending bit to +* be clear. +* This parameter can be one of the following values: +* - SystemHandler_PSV +* - SystemHandler_SysTick +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler) +{ + u32 tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_CLEAR_SYSTEM_HANDLER(SystemHandler)); + + /* Get the System Handler pending bit position */ + tmp = SystemHandler & (u32)0x1F; + /* Clear the corresponding System Handler pending bit */ + SCB->ICSR |= ((u32)0x01 << (tmp - 0x01)); +} + +/******************************************************************************* +* Function Name : NVIC_GetSystemHandlerActiveBitStatus +* Description : Checks whether the specified System handlers active bit is +* set or not. +* Input : - SystemHandler: specifies the system handler active bit to +* check. +* This parameter can be one of the following values: +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* - SystemHandler_UsageFault +* - SystemHandler_SVCall +* - SystemHandler_DebugMonitor +* - SystemHandler_PSV +* - SystemHandler_SysTick +* Output : None +* Return : The new state of System Handler active bit(SET or RESET). +*******************************************************************************/ +ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler) +{ + ITStatus bitstatus = RESET; + + u32 tmp = 0x00, tmppos = 0x00; + + /* Check the parameters */ + assert_param(IS_GET_ACTIVE_SYSTEM_HANDLER(SystemHandler)); + + tmppos = (SystemHandler >> 0x0E) & (u32)0x0F; + + tmppos = (u32)0x01 << tmppos; + + tmp = SCB->SHCSR & tmppos; + + if (tmp == tmppos) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : NVIC_GetFaultHandlerSources +* Description : Returns the system fault handlers sources. +* Input : - SystemHandler: specifies the system handler to get its fault +* sources. +* This parameter can be one of the following values: +* - SystemHandler_HardFault +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* - SystemHandler_UsageFault +* - SystemHandler_DebugMonitor +* Output : None +* Return : Source of the fault handler. +*******************************************************************************/ +u32 NVIC_GetFaultHandlerSources(u32 SystemHandler) +{ + u32 faultsources = 0x00; + u32 tmpreg = 0x00, tmppos = 0x00; + + /* Check the parameters */ + assert_param(IS_FAULT_SOURCE_SYSTEM_HANDLER(SystemHandler)); + + tmpreg = (SystemHandler >> 0x12) & (u32)0x03; + tmppos = (SystemHandler >> 0x14) & (u32)0x03; + + if (tmpreg == 0x00) + { + faultsources = SCB->HFSR; + } + else if (tmpreg == 0x01) + { + faultsources = SCB->CFSR >> (tmppos * 0x08); + if (tmppos != 0x02) + { + faultsources &= (u32)0x0F; + } + else + { + faultsources &= (u32)0xFF; + } + } + else + { + faultsources = SCB->DFSR; + } + return faultsources; +} + +/******************************************************************************* +* Function Name : NVIC_GetFaultAddress +* Description : Returns the address of the location that generated a fault +* handler. +* Input : - SystemHandler: specifies the system handler to get its +* fault address. +* This parameter can be one of the following values: +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* Output : None +* Return : Fault address. +*******************************************************************************/ +u32 NVIC_GetFaultAddress(u32 SystemHandler) +{ + u32 faultaddress = 0x00; + u32 tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_FAULT_ADDRESS_SYSTEM_HANDLER(SystemHandler)); + + tmp = (SystemHandler >> 0x16) & (u32)0x01; + + if (tmp == 0x00) + { + faultaddress = SCB->MMFAR; + } + else + { + faultaddress = SCB->BFAR; + } + return faultaddress; +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/