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tn214def.asm
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;
;This file has been modified to adapt it to ASXXXX syntax.
;
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : tn214def.inc
;* Title : Register/Bit Definitions for the ATtiny214
;* Created : 2021-03-01 11:29
;* Version : 1.00
;* Support e-mail : [email protected]
;* Target MCU : ATtiny214
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;*************************************************************************
; ***** SPECIFY DEVICE ***************************************************
SIGNATURE_000 = 0x1E
SIGNATURE_001 = 0x91
SIGNATURE_002 = 0x20
; ***** ABSOLUTE I/O REGISTER LOCATIONS **********************************
;*************************************************************************
;** AC0 - Analog Comparator
;*************************************************************************
AC0_CTRLA = 0x0670 ; Control A
AC0_MUXCTRLA = 0x0672 ; Mux Control A
AC0_INTCTRL = 0x0676 ; Interrupt Control
AC0_STATUS = 0x0677 ; Status
;*************************************************************************
;** ADC0 - Analog to Digital Converter
;*************************************************************************
ADC0_CTRLA = 0x0600 ; Control A
ADC0_CTRLB = 0x0601 ; Control B
ADC0_CTRLC = 0x0602 ; Control C
ADC0_CTRLD = 0x0603 ; Control D
ADC0_CTRLE = 0x0604 ; Control E
ADC0_SAMPCTRL = 0x0605 ; Sample Control
ADC0_MUXPOS = 0x0606 ; Positive mux input
ADC0_COMMAND = 0x0608 ; Command
ADC0_EVCTRL = 0x0609 ; Event Control
ADC0_INTCTRL = 0x060A ; Interrupt Control
ADC0_INTFLAGS = 0x060B ; Interrupt Flags
ADC0_DBGCTRL = 0x060C ; Debug Control
ADC0_TEMP = 0x060D ; Temporary Data
ADC0_RES = 0x0610 ; ADC Accumulator Result
ADC0_RESL = 0x0610 ; ADC Accumulator Result low byte
ADC0_RESH = 0x0611 ; ADC Accumulator Result hi byte
ADC0_WINLT = 0x0612 ; Window comparator low threshold
ADC0_WINLTL = 0x0612 ; Window comparator low threshold low byte
ADC0_WINLTH = 0x0613 ; Window comparator low threshold hi byte
ADC0_WINHT = 0x0614 ; Window comparator high threshold
ADC0_WINHTL = 0x0614 ; Window comparator high threshold low byte
ADC0_WINHTH = 0x0615 ; Window comparator high threshold hi byte
ADC0_CALIB = 0x0616 ; Calibration
;*************************************************************************
;** BOD - Bod interface
;*************************************************************************
BOD_CTRLA = 0x0080 ; Control A
BOD_CTRLB = 0x0081 ; Control B
BOD_VLMCTRLA = 0x0088 ; Voltage level monitor Control
BOD_INTCTRL = 0x0089 ; Voltage level monitor interrupt Control
BOD_INTFLAGS = 0x008A ; Voltage level monitor interrupt Flags
BOD_STATUS = 0x008B ; Voltage level monitor status
;*************************************************************************
;** CCL - Configurable Custom Logic
;*************************************************************************
CCL_CTRLA = 0x01C0 ; Control Register A
CCL_SEQCTRL0 = 0x01C1 ; Sequential Control 0
CCL_LUT0CTRLA = 0x01C5 ; LUT Control 0 A
CCL_LUT0CTRLB = 0x01C6 ; LUT Control 0 B
CCL_LUT0CTRLC = 0x01C7 ; LUT Control 0 C
CCL_TRUTH0 = 0x01C8 ; Truth 0
CCL_LUT1CTRLA = 0x01C9 ; LUT Control 1 A
CCL_LUT1CTRLB = 0x01CA ; LUT Control 1 B
CCL_LUT1CTRLC = 0x01CB ; LUT Control 1 C
CCL_TRUTH1 = 0x01CC ; Truth 1
;*************************************************************************
;** CLKCTRL - Clock controller
;*************************************************************************
CLKCTRL_MCLKCTRLA = 0x0060 ; MCLK Control A
CLKCTRL_MCLKCTRLB = 0x0061 ; MCLK Control B
CLKCTRL_MCLKLOCK = 0x0062 ; MCLK Lock
CLKCTRL_MCLKSTATUS = 0x0063 ; MCLK Status
CLKCTRL_OSC20MCTRLA = 0x0070 ; OSC20M Control A
CLKCTRL_OSC20MCALIBA = 0x0071 ; OSC20M Calibration A
CLKCTRL_OSC20MCALIBB = 0x0072 ; OSC20M Calibration B
CLKCTRL_OSC32KCTRLA = 0x0078 ; OSC32K Control A
CLKCTRL_XOSC32KCTRLA = 0x007C ; XOSC32K Control A
;*************************************************************************
;** CPU - CPU
;*************************************************************************
CPU_CCP = 0x0034 ; Configuration Change Protection
CPU_SPL = 0x003D ; Stack Pointer Low
CPU_SPH = 0x003E ; Stack Pointer High
CPU_SREG = 0x003F ; Status Register
;*************************************************************************
;** CPUINT - Interrupt Controller
;*************************************************************************
CPUINT_CTRLA = 0x0110 ; Control A
CPUINT_STATUS = 0x0111 ; Status
CPUINT_LVL0PRI = 0x0112 ; Interrupt Level 0 Priority
CPUINT_LVL1VEC = 0x0113 ; Interrupt Level 1 Priority Vector
;*************************************************************************
;** CRCSCAN - CRCSCAN
;*************************************************************************
CRCSCAN_CTRLA = 0x0120 ; Control A
CRCSCAN_CTRLB = 0x0121 ; Control B
CRCSCAN_STATUS = 0x0122 ; Status
;*************************************************************************
;** DAC0 - Digital to Analog Converter
;*************************************************************************
DAC0_CTRLA = 0x0680 ; Control Register A
DAC0_DATA = 0x0681 ; DATA Register
;*************************************************************************
;** EVSYS - Event System
;*************************************************************************
EVSYS_ASYNCSTROBE = 0x0180 ; Asynchronous Channel Strobe
EVSYS_SYNCSTROBE = 0x0181 ; Synchronous Channel Strobe
EVSYS_ASYNCCH0 = 0x0182 ; Asynchronous Channel 0 Generator Selection
EVSYS_ASYNCCH1 = 0x0183 ; Asynchronous Channel 1 Generator Selection
EVSYS_ASYNCCH2 = 0x0184 ; Asynchronous Channel 2 Generator Selection
EVSYS_ASYNCCH3 = 0x0185 ; Asynchronous Channel 3 Generator Selection
EVSYS_SYNCCH0 = 0x018A ; Synchronous Channel 0 Generator Selection
EVSYS_SYNCCH1 = 0x018B ; Synchronous Channel 1 Generator Selection
EVSYS_ASYNCUSER0 = 0x0192 ; Asynchronous User Ch 0 Input Selection - TCB0
EVSYS_ASYNCUSER1 = 0x0193 ; Asynchronous User Ch 1 Input Selection - ADC0
EVSYS_ASYNCUSER2 = 0x0194 ; Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0
EVSYS_ASYNCUSER3 = 0x0195 ; Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0
EVSYS_ASYNCUSER4 = 0x0196 ; Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1
EVSYS_ASYNCUSER5 = 0x0197 ; Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1
EVSYS_ASYNCUSER6 = 0x0198 ; Asynchronous User Ch 6 Input Selection - TCD0 Event 0
EVSYS_ASYNCUSER7 = 0x0199 ; Asynchronous User Ch 7 Input Selection - TCD0 Event 1
EVSYS_ASYNCUSER8 = 0x019A ; Asynchronous User Ch 8 Input Selection - Event Out 0
EVSYS_ASYNCUSER9 = 0x019B ; Asynchronous User Ch 9 Input Selection - Event Out 1
EVSYS_ASYNCUSER10 = 0x019C ; Asynchronous User Ch 10 Input Selection - Event Out 2
EVSYS_SYNCUSER0 = 0x01A2 ; Synchronous User Ch 0 Input Selection - TCA0
EVSYS_SYNCUSER1 = 0x01A3 ; Synchronous User Ch 1 Input Selection - USART0
;*************************************************************************
;** FUSE - Fuses
;*************************************************************************
FUSE_WDTCFG = 0x1280 ; Watchdog Configuration
FUSE_BODCFG = 0x1281 ; BOD Configuration
FUSE_OSCCFG = 0x1282 ; Oscillator Configuration
FUSE_TCD0CFG = 0x1284 ; TCD0 Configuration
FUSE_SYSCFG0 = 0x1285 ; System Configuration 0
FUSE_SYSCFG1 = 0x1286 ; System Configuration 1
FUSE_APPEND = 0x1287 ; Application Code Section End
FUSE_BOOTEND = 0x1288 ; Boot Section End
;*************************************************************************
;** GPIO - General Purpose IO
;*************************************************************************
GPIO_GPIOR0 = 0x001C ; General Purpose IO Register 0
GPIO_GPIOR1 = 0x001D ; General Purpose IO Register 1
GPIO_GPIOR2 = 0x001E ; General Purpose IO Register 2
GPIO_GPIOR3 = 0x001F ; General Purpose IO Register 3
;*************************************************************************
;** LOCKBIT - Lockbit
;*************************************************************************
LOCKBIT_LOCKBIT = 0x128A ; Lock bits
;*************************************************************************
;** NVMCTRL - Non-volatile Memory Controller
;*************************************************************************
NVMCTRL_CTRLA = 0x1000 ; Control A
NVMCTRL_CTRLB = 0x1001 ; Control B
NVMCTRL_STATUS = 0x1002 ; Status
NVMCTRL_INTCTRL = 0x1003 ; Interrupt Control
NVMCTRL_INTFLAGS = 0x1004 ; Interrupt Flags
NVMCTRL_DATA = 0x1006 ; Data
NVMCTRL_DATAL = 0x1006 ; Data low byte
NVMCTRL_DATAH = 0x1007 ; Data hi byte
NVMCTRL_ADDR = 0x1008 ; Address
NVMCTRL_ADDRL = 0x1008 ; Address low byte
NVMCTRL_ADDRH = 0x1009 ; Address hi byte
;*************************************************************************
;** PORTA - I/O Ports
;*************************************************************************
PORTA_DIR = 0x0400 ; Data Direction
PORTA_DIRSET = 0x0401 ; Data Direction Set
PORTA_DIRCLR = 0x0402 ; Data Direction Clear
PORTA_DIRTGL = 0x0403 ; Data Direction Toggle
PORTA_OUT = 0x0404 ; Output Value
PORTA_OUTSET = 0x0405 ; Output Value Set
PORTA_OUTCLR = 0x0406 ; Output Value Clear
PORTA_OUTTGL = 0x0407 ; Output Value Toggle
PORTA_IN = 0x0408 ; Input Value
PORTA_INTFLAGS = 0x0409 ; Interrupt Flags
PORTA_PIN0CTRL = 0x0410 ; Pin 0 Control
PORTA_PIN1CTRL = 0x0411 ; Pin 1 Control
PORTA_PIN2CTRL = 0x0412 ; Pin 2 Control
PORTA_PIN3CTRL = 0x0413 ; Pin 3 Control
PORTA_PIN4CTRL = 0x0414 ; Pin 4 Control
PORTA_PIN5CTRL = 0x0415 ; Pin 5 Control
PORTA_PIN6CTRL = 0x0416 ; Pin 6 Control
PORTA_PIN7CTRL = 0x0417 ; Pin 7 Control
;*************************************************************************
;** PORTB - I/O Ports
;*************************************************************************
PORTB_DIR = 0x0420 ; Data Direction
PORTB_DIRSET = 0x0421 ; Data Direction Set
PORTB_DIRCLR = 0x0422 ; Data Direction Clear
PORTB_DIRTGL = 0x0423 ; Data Direction Toggle
PORTB_OUT = 0x0424 ; Output Value
PORTB_OUTSET = 0x0425 ; Output Value Set
PORTB_OUTCLR = 0x0426 ; Output Value Clear
PORTB_OUTTGL = 0x0427 ; Output Value Toggle
PORTB_IN = 0x0428 ; Input Value
PORTB_INTFLAGS = 0x0429 ; Interrupt Flags
PORTB_PIN0CTRL = 0x0430 ; Pin 0 Control
PORTB_PIN1CTRL = 0x0431 ; Pin 1 Control
PORTB_PIN2CTRL = 0x0432 ; Pin 2 Control
PORTB_PIN3CTRL = 0x0433 ; Pin 3 Control
PORTB_PIN4CTRL = 0x0434 ; Pin 4 Control
PORTB_PIN5CTRL = 0x0435 ; Pin 5 Control
PORTB_PIN6CTRL = 0x0436 ; Pin 6 Control
PORTB_PIN7CTRL = 0x0437 ; Pin 7 Control
;*************************************************************************
;** PORTMUX - Port Multiplexer
;*************************************************************************
PORTMUX_CTRLA = 0x0200 ; Port Multiplexer Control A
PORTMUX_CTRLB = 0x0201 ; Port Multiplexer Control B
PORTMUX_CTRLC = 0x0202 ; Port Multiplexer Control C
PORTMUX_CTRLD = 0x0203 ; Port Multiplexer Control D
;*************************************************************************
;** RSTCTRL - Reset controller
;*************************************************************************
RSTCTRL_RSTFR = 0x0040 ; Reset Flags
RSTCTRL_SWRR = 0x0041 ; Software Reset
;*************************************************************************
;** RTC - Real-Time Counter
;*************************************************************************
RTC_CTRLA = 0x0140 ; Control A
RTC_STATUS = 0x0141 ; Status
RTC_INTCTRL = 0x0142 ; Interrupt Control
RTC_INTFLAGS = 0x0143 ; Interrupt Flags
RTC_TEMP = 0x0144 ; Temporary
RTC_DBGCTRL = 0x0145 ; Debug control
RTC_CLKSEL = 0x0147 ; Clock Select
RTC_CNT = 0x0148 ; Counter
RTC_CNTL = 0x0148 ; Counter low byte
RTC_CNTH = 0x0149 ; Counter hi byte
RTC_PER = 0x014A ; Period
RTC_PERL = 0x014A ; Period low byte
RTC_PERH = 0x014B ; Period hi byte
RTC_CMP = 0x014C ; Compare
RTC_CMPL = 0x014C ; Compare low byte
RTC_CMPH = 0x014D ; Compare hi byte
RTC_PITCTRLA = 0x0150 ; PIT Control A
RTC_PITSTATUS = 0x0151 ; PIT Status
RTC_PITINTCTRL = 0x0152 ; PIT Interrupt Control
RTC_PITINTFLAGS = 0x0153 ; PIT Interrupt Flags
RTC_PITDBGCTRL = 0x0155 ; PIT Debug control
;*************************************************************************
;** SIGROW - Signature row
;*************************************************************************
SIGROW_DEVICEID0 = 0x1100 ; Device ID Byte 0
SIGROW_DEVICEID1 = 0x1101 ; Device ID Byte 1
SIGROW_DEVICEID2 = 0x1102 ; Device ID Byte 2
SIGROW_SERNUM0 = 0x1103 ; Serial Number Byte 0
SIGROW_SERNUM1 = 0x1104 ; Serial Number Byte 1
SIGROW_SERNUM2 = 0x1105 ; Serial Number Byte 2
SIGROW_SERNUM3 = 0x1106 ; Serial Number Byte 3
SIGROW_SERNUM4 = 0x1107 ; Serial Number Byte 4
SIGROW_SERNUM5 = 0x1108 ; Serial Number Byte 5
SIGROW_SERNUM6 = 0x1109 ; Serial Number Byte 6
SIGROW_SERNUM7 = 0x110A ; Serial Number Byte 7
SIGROW_SERNUM8 = 0x110B ; Serial Number Byte 8
SIGROW_SERNUM9 = 0x110C ; Serial Number Byte 9
SIGROW_TEMPSENSE0 = 0x1120 ; Temperature Sensor Calibration Byte 0
SIGROW_TEMPSENSE1 = 0x1121 ; Temperature Sensor Calibration Byte 1
SIGROW_OSC16ERR3V = 0x1122 ; OSC16 error at 3V
SIGROW_OSC16ERR5V = 0x1123 ; OSC16 error at 5V
SIGROW_OSC20ERR3V = 0x1124 ; OSC20 error at 3V
SIGROW_OSC20ERR5V = 0x1125 ; OSC20 error at 5V
;*************************************************************************
;** SLPCTRL - Sleep Controller
;*************************************************************************
SLPCTRL_CTRLA = 0x0050 ; Control
;*************************************************************************
;** SPI0 - Serial Peripheral Interface
;*************************************************************************
SPI0_CTRLA = 0x0820 ; Control A
SPI0_CTRLB = 0x0821 ; Control B
SPI0_INTCTRL = 0x0822 ; Interrupt Control
SPI0_INTFLAGS = 0x0823 ; Interrupt Flags
SPI0_DATA = 0x0824 ; Data
;*************************************************************************
;** SYSCFG - System Configuration Registers
;*************************************************************************
SYSCFG_REVID = 0x0F01 ; Revision ID
SYSCFG_EXTBRK = 0x0F02 ; External Break
;*************************************************************************
;** TCA0 - 16-bit Timer/Counter Type A
;*************************************************************************
TCA0_SINGLE_CTRLA = 0x0A00 ; SINGLE Control A
TCA0_SINGLE_CTRLB = 0x0A01 ; SINGLE Control B
TCA0_SINGLE_CTRLC = 0x0A02 ; SINGLE Control C
TCA0_SINGLE_CTRLD = 0x0A03 ; SINGLE Control D
TCA0_SINGLE_CTRLECLR = 0x0A04 ; SINGLE Control E Clear
TCA0_SINGLE_CTRLESET = 0x0A05 ; SINGLE Control E Set
TCA0_SINGLE_CTRLFCLR = 0x0A06 ; SINGLE Control F Clear
TCA0_SINGLE_CTRLFSET = 0x0A07 ; SINGLE Control F Set
TCA0_SINGLE_EVCTRL = 0x0A09 ; SINGLE Event Control
TCA0_SINGLE_INTCTRL = 0x0A0A ; SINGLE Interrupt Control
TCA0_SINGLE_INTFLAGS = 0x0A0B ; SINGLE Interrupt Flags
TCA0_SINGLE_DBGCTRL = 0x0A0E ; SINGLE Degbug Control
TCA0_SINGLE_TEMP = 0x0A0F ; SINGLE Temporary data for 16-bit Access
TCA0_SINGLE_CNT = 0x0A20 ; SINGLE Count
TCA0_SINGLE_PER = 0x0A26 ; SINGLE Period
TCA0_SINGLE_CMP0 = 0x0A28 ; SINGLE Compare 0
TCA0_SINGLE_CMP1 = 0x0A2A ; SINGLE Compare 1
TCA0_SINGLE_CMP2 = 0x0A2C ; SINGLE Compare 2
TCA0_SINGLE_PERBUF = 0x0A36 ; SINGLE Period Buffer
TCA0_SINGLE_CMP0BUF = 0x0A38 ; SINGLE Compare 0 Buffer
TCA0_SINGLE_CMP1BUF = 0x0A3A ; SINGLE Compare 1 Buffer
TCA0_SINGLE_CMP2BUF = 0x0A3C ; SINGLE Compare 2 Buffer
TCA0_SPLIT_CTRLA = 0x0A00 ; SPLIT Control A
TCA0_SPLIT_CTRLB = 0x0A01 ; SPLIT Control B
TCA0_SPLIT_CTRLC = 0x0A02 ; SPLIT Control C
TCA0_SPLIT_CTRLD = 0x0A03 ; SPLIT Control D
TCA0_SPLIT_CTRLECLR = 0x0A04 ; SPLIT Control E Clear
TCA0_SPLIT_CTRLESET = 0x0A05 ; SPLIT Control E Set
TCA0_SPLIT_INTCTRL = 0x0A0A ; SPLIT Interrupt Control
TCA0_SPLIT_INTFLAGS = 0x0A0B ; SPLIT Interrupt Flags
TCA0_SPLIT_DBGCTRL = 0x0A0E ; SPLIT Degbug Control
TCA0_SPLIT_LCNT = 0x0A20 ; SPLIT Low Count
TCA0_SPLIT_HCNT = 0x0A21 ; SPLIT High Count
TCA0_SPLIT_LPER = 0x0A26 ; SPLIT Low Period
TCA0_SPLIT_HPER = 0x0A27 ; SPLIT High Period
TCA0_SPLIT_LCMP0 = 0x0A28 ; SPLIT Low Compare
TCA0_SPLIT_HCMP0 = 0x0A29 ; SPLIT High Compare
TCA0_SPLIT_LCMP1 = 0x0A2A ; SPLIT Low Compare
TCA0_SPLIT_HCMP1 = 0x0A2B ; SPLIT High Compare
TCA0_SPLIT_LCMP2 = 0x0A2C ; SPLIT Low Compare
TCA0_SPLIT_HCMP2 = 0x0A2D ; SPLIT High Compare
;*************************************************************************
;** TCB0 - 16-bit Timer Type B
;*************************************************************************
TCB0_CTRLA = 0x0A40 ; Control A
TCB0_CTRLB = 0x0A41 ; Control Register B
TCB0_EVCTRL = 0x0A44 ; Event Control
TCB0_INTCTRL = 0x0A45 ; Interrupt Control
TCB0_INTFLAGS = 0x0A46 ; Interrupt Flags
TCB0_STATUS = 0x0A47 ; Status
TCB0_DBGCTRL = 0x0A48 ; Debug Control
TCB0_TEMP = 0x0A49 ; Temporary Value
TCB0_CNT = 0x0A4A ; Count
TCB0_CNTL = 0x0A4A ; Count low byte
TCB0_CNTH = 0x0A4B ; Count hi byte
TCB0_CCMP = 0x0A4C ; Compare or Capture
TCB0_CCMPL = 0x0A4C ; Compare or Capture low byte
TCB0_CCMPH = 0x0A4D ; Compare or Capture hi byte
;*************************************************************************
;** TCD0 - Timer Counter D
;*************************************************************************
TCD0_CTRLA = 0x0A80 ; Control A
TCD0_CTRLB = 0x0A81 ; Control B
TCD0_CTRLC = 0x0A82 ; Control C
TCD0_CTRLD = 0x0A83 ; Control D
TCD0_CTRLE = 0x0A84 ; Control E
TCD0_EVCTRLA = 0x0A88 ; EVCTRLA
TCD0_EVCTRLB = 0x0A89 ; EVCTRLB
TCD0_INTCTRL = 0x0A8C ; Interrupt Control
TCD0_INTFLAGS = 0x0A8D ; Interrupt Flags
TCD0_STATUS = 0x0A8E ; Status
TCD0_INPUTCTRLA = 0x0A90 ; Input Control A
TCD0_INPUTCTRLB = 0x0A91 ; Input Control B
TCD0_FAULTCTRL = 0x0A92 ; Fault Control
TCD0_DLYCTRL = 0x0A94 ; Delay Control
TCD0_DLYVAL = 0x0A95 ; Delay value
TCD0_DITCTRL = 0x0A98 ; Dither Control A
TCD0_DITVAL = 0x0A99 ; Dither value
TCD0_DBGCTRL = 0x0A9E ; Debug Control
TCD0_CAPTUREA = 0x0AA2 ; Capture A
TCD0_CAPTUREAL = 0x0AA2 ; Capture A low byte
TCD0_CAPTUREAH = 0x0AA3 ; Capture A hi byte
TCD0_CAPTUREB = 0x0AA4 ; Capture B
TCD0_CAPTUREBL = 0x0AA4 ; Capture B low byte
TCD0_CAPTUREBH = 0x0AA5 ; Capture B hi byte
TCD0_CMPASET = 0x0AA8 ; Compare A Set
TCD0_CMPASETL = 0x0AA8 ; Compare A Set low byte
TCD0_CMPASETH = 0x0AA9 ; Compare A Set hi byte
TCD0_CMPACLR = 0x0AAA ; Compare A Clear
TCD0_CMPACLRL = 0x0AAA ; Compare A Clear low byte
TCD0_CMPACLRH = 0x0AAB ; Compare A Clear hi byte
TCD0_CMPBSET = 0x0AAC ; Compare B Set
TCD0_CMPBSETL = 0x0AAC ; Compare B Set low byte
TCD0_CMPBSETH = 0x0AAD ; Compare B Set hi byte
TCD0_CMPBCLR = 0x0AAE ; Compare B Clear
TCD0_CMPBCLRL = 0x0AAE ; Compare B Clear low byte
TCD0_CMPBCLRH = 0x0AAF ; Compare B Clear hi byte
;*************************************************************************
;** TWI0 - Two-Wire Interface
;*************************************************************************
TWI0_CTRLA = 0x0810 ; Control A
TWI0_DBGCTRL = 0x0812 ; Debug Control Register
TWI0_MCTRLA = 0x0813 ; Master Control A
TWI0_MCTRLB = 0x0814 ; Master Control B
TWI0_MSTATUS = 0x0815 ; Master Status
TWI0_MBAUD = 0x0816 ; Master Baurd Rate Control
TWI0_MADDR = 0x0817 ; Master Address
TWI0_MDATA = 0x0818 ; Master Data
TWI0_SCTRLA = 0x0819 ; Slave Control A
TWI0_SCTRLB = 0x081A ; Slave Control B
TWI0_SSTATUS = 0x081B ; Slave Status
TWI0_SADDR = 0x081C ; Slave Address
TWI0_SDATA = 0x081D ; Slave Data
TWI0_SADDRMASK = 0x081E ; Slave Address Mask
;*************************************************************************
;** USART0 - Universal Synchronous and Asynchronous Receiver and Transmitter
;*************************************************************************
USART0_RXDATAL = 0x0800 ; Receive Data Low Byte
USART0_RXDATAH = 0x0801 ; Receive Data High Byte
USART0_TXDATAL = 0x0802 ; Transmit Data Low Byte
USART0_TXDATAH = 0x0803 ; Transmit Data High Byte
USART0_STATUS = 0x0804 ; Status
USART0_CTRLA = 0x0805 ; Control A
USART0_CTRLB = 0x0806 ; Control B
USART0_CTRLC = 0x0807 ; Control C
USART0_BAUD = 0x0808 ; Baud Rate
USART0_BAUDL = 0x0808 ; Baud Rate low byte
USART0_BAUDH = 0x0809 ; Baud Rate hi byte
USART0_DBGCTRL = 0x080B ; Debug Control
USART0_EVCTRL = 0x080C ; Event Control
USART0_TXPLCTRL = 0x080D ; IRCOM Transmitter Pulse Length Control
USART0_RXPLCTRL = 0x080E ; IRCOM Receiver Pulse Length Control
;*************************************************************************
;** USERROW - User Row
;*************************************************************************
USERROW_USERROW0 = 0x1300 ; User Row Byte 0
USERROW_USERROW1 = 0x1301 ; User Row Byte 1
USERROW_USERROW2 = 0x1302 ; User Row Byte 2
USERROW_USERROW3 = 0x1303 ; User Row Byte 3
USERROW_USERROW4 = 0x1304 ; User Row Byte 4
USERROW_USERROW5 = 0x1305 ; User Row Byte 5
USERROW_USERROW6 = 0x1306 ; User Row Byte 6
USERROW_USERROW7 = 0x1307 ; User Row Byte 7
USERROW_USERROW8 = 0x1308 ; User Row Byte 8
USERROW_USERROW9 = 0x1309 ; User Row Byte 9
USERROW_USERROW10 = 0x130A ; User Row Byte 10
USERROW_USERROW11 = 0x130B ; User Row Byte 11
USERROW_USERROW12 = 0x130C ; User Row Byte 12
USERROW_USERROW13 = 0x130D ; User Row Byte 13
USERROW_USERROW14 = 0x130E ; User Row Byte 14
USERROW_USERROW15 = 0x130F ; User Row Byte 15
USERROW_USERROW16 = 0x1310 ; User Row Byte 16
USERROW_USERROW17 = 0x1311 ; User Row Byte 17
USERROW_USERROW18 = 0x1312 ; User Row Byte 18
USERROW_USERROW19 = 0x1313 ; User Row Byte 19
USERROW_USERROW20 = 0x1314 ; User Row Byte 20
USERROW_USERROW21 = 0x1315 ; User Row Byte 21
USERROW_USERROW22 = 0x1316 ; User Row Byte 22
USERROW_USERROW23 = 0x1317 ; User Row Byte 23
USERROW_USERROW24 = 0x1318 ; User Row Byte 24
USERROW_USERROW25 = 0x1319 ; User Row Byte 25
USERROW_USERROW26 = 0x131A ; User Row Byte 26
USERROW_USERROW27 = 0x131B ; User Row Byte 27
USERROW_USERROW28 = 0x131C ; User Row Byte 28
USERROW_USERROW29 = 0x131D ; User Row Byte 29
USERROW_USERROW30 = 0x131E ; User Row Byte 30
USERROW_USERROW31 = 0x131F ; User Row Byte 31
;*************************************************************************
;** VPORTA - Virtual Ports
;*************************************************************************
VPORTA_DIR = 0x0000 ; Data Direction
VPORTA_OUT = 0x0001 ; Output Value
VPORTA_IN = 0x0002 ; Input Value
VPORTA_INTFLAGS = 0x0003 ; Interrupt Flags
;*************************************************************************
;** VPORTB - Virtual Ports
;*************************************************************************
VPORTB_DIR = 0x0004 ; Data Direction
VPORTB_OUT = 0x0005 ; Output Value
VPORTB_IN = 0x0006 ; Input Value
VPORTB_INTFLAGS = 0x0007 ; Interrupt Flags
;*************************************************************************
;** VPORTC - Virtual Ports
;*************************************************************************
VPORTC_DIR = 0x0008 ; Data Direction
VPORTC_OUT = 0x0009 ; Output Value
VPORTC_IN = 0x000A ; Input Value
VPORTC_INTFLAGS = 0x000B ; Interrupt Flags
;*************************************************************************
;** VREF - Voltage reference
;*************************************************************************
VREF_CTRLA = 0x00A0 ; Control A
VREF_CTRLB = 0x00A1 ; Control B
;*************************************************************************
;** WDT - Watch-Dog Timer
;*************************************************************************
WDT_CTRLA = 0x0100 ; Control A
WDT_STATUS = 0x0101 ; Status
; ***** ALL MODULE BASE ADRESSES *****************************************
AC0_base = 0x0670 ; Analog Comparator
ADC0_base = 0x0600 ; Analog to Digital Converter
BOD_base = 0x0080 ; Bod interface
CCL_base = 0x01C0 ; Configurable Custom Logic
CLKCTRL_base = 0x0060 ; Clock controller
CPU_base = 0x0030 ; CPU
CPUINT_base = 0x0110 ; Interrupt Controller
CRCSCAN_base = 0x0120 ; CRCSCAN
DAC0_base = 0x0680 ; Digital to Analog Converter
EVSYS_base = 0x0180 ; Event System
FUSE_base = 0x1280 ; Fuses
GPIO_base = 0x001C ; General Purpose IO
LOCKBIT_base = 0x128A ; Lockbit
NVMCTRL_base = 0x1000 ; Non-volatile Memory Controller
PORTA_base = 0x0400 ; I/O Ports
PORTB_base = 0x0420 ; I/O Ports
PORTMUX_base = 0x0200 ; Port Multiplexer
RSTCTRL_base = 0x0040 ; Reset controller
RTC_base = 0x0140 ; Real-Time Counter
SIGROW_base = 0x1100 ; Signature row
SLPCTRL_base = 0x0050 ; Sleep Controller
SPI0_base = 0x0820 ; Serial Peripheral Interface
SYSCFG_base = 0x0F00 ; System Configuration Registers
TCA0_base = 0x0A00 ; 16-bit Timer/Counter Type A
TCB0_base = 0x0A40 ; 16-bit Timer Type B
TCD0_base = 0x0A80 ; Timer Counter D
TWI0_base = 0x0810 ; Two-Wire Interface
USART0_base = 0x0800 ; Universal Synchronous and Asynchronous Receiver and Transmitter
USERROW_base = 0x1300 ; User Row
VPORTA_base = 0x0000 ; Virtual Ports
VPORTB_base = 0x0004 ; Virtual Ports
VPORTC_base = 0x0008 ; Virtual Ports
VREF_base = 0x00A0 ; Voltage reference
WDT_base = 0x0100 ; Watch-Dog Timer
; ***** IO REGISTER OFFSETS **********************************************
;*************************************************************************
;** AC - Analog Comparator
;*************************************************************************
AC_CTRLA_offset = 0x00 ; Control A
AC_MUXCTRLA_offset = 0x02 ; Mux Control A
AC_INTCTRL_offset = 0x06 ; Interrupt Control
AC_STATUS_offset = 0x07 ; Status
;*************************************************************************
;** ADC - Analog to Digital Converter
;*************************************************************************
ADC_CTRLA_offset = 0x00 ; Control A
ADC_CTRLB_offset = 0x01 ; Control B
ADC_CTRLC_offset = 0x02 ; Control C
ADC_CTRLD_offset = 0x03 ; Control D
ADC_CTRLE_offset = 0x04 ; Control E
ADC_SAMPCTRL_offset = 0x05 ; Sample Control
ADC_MUXPOS_offset = 0x06 ; Positive mux input
ADC_COMMAND_offset = 0x08 ; Command
ADC_EVCTRL_offset = 0x09 ; Event Control
ADC_INTCTRL_offset = 0x0A ; Interrupt Control
ADC_INTFLAGS_offset = 0x0B ; Interrupt Flags
ADC_DBGCTRL_offset = 0x0C ; Debug Control
ADC_TEMP_offset = 0x0D ; Temporary Data
ADC_RES_offset = 0x10 ; ADC Accumulator Result
ADC_WINLT_offset = 0x12 ; Window comparator low threshold
ADC_WINHT_offset = 0x14 ; Window comparator high threshold
ADC_CALIB_offset = 0x16 ; Calibration
;*************************************************************************
;** BOD - Bod interface
;*************************************************************************
BOD_CTRLA_offset = 0x00 ; Control A
BOD_CTRLB_offset = 0x01 ; Control B
BOD_VLMCTRLA_offset = 0x08 ; Voltage level monitor Control
BOD_INTCTRL_offset = 0x09 ; Voltage level monitor interrupt Control
BOD_INTFLAGS_offset = 0x0A ; Voltage level monitor interrupt Flags
BOD_STATUS_offset = 0x0B ; Voltage level monitor status
;*************************************************************************
;** CCL - Configurable Custom Logic
;*************************************************************************
CCL_CTRLA_offset = 0x00 ; Control Register A
CCL_SEQCTRL0_offset = 0x01 ; Sequential Control 0
CCL_LUT0CTRLA_offset = 0x05 ; LUT Control 0 A
CCL_LUT0CTRLB_offset = 0x06 ; LUT Control 0 B
CCL_LUT0CTRLC_offset = 0x07 ; LUT Control 0 C
CCL_TRUTH0_offset = 0x08 ; Truth 0
CCL_LUT1CTRLA_offset = 0x09 ; LUT Control 1 A
CCL_LUT1CTRLB_offset = 0x0A ; LUT Control 1 B
CCL_LUT1CTRLC_offset = 0x0B ; LUT Control 1 C
CCL_TRUTH1_offset = 0x0C ; Truth 1
;*************************************************************************
;** CLKCTRL - Clock controller
;*************************************************************************
CLKCTRL_MCLKCTRLA_offset = 0x00 ; MCLK Control A
CLKCTRL_MCLKCTRLB_offset = 0x01 ; MCLK Control B
CLKCTRL_MCLKLOCK_offset = 0x02 ; MCLK Lock
CLKCTRL_MCLKSTATUS_offset = 0x03 ; MCLK Status
CLKCTRL_OSC20MCTRLA_offset = 0x10 ; OSC20M Control A
CLKCTRL_OSC20MCALIBA_offset = 0x11 ; OSC20M Calibration A
CLKCTRL_OSC20MCALIBB_offset = 0x12 ; OSC20M Calibration B
CLKCTRL_OSC32KCTRLA_offset = 0x18 ; OSC32K Control A
CLKCTRL_XOSC32KCTRLA_offset = 0x1C ; XOSC32K Control A
;*************************************************************************
;** CPU - CPU
;*************************************************************************
CPU_CCP_offset = 0x04 ; Configuration Change Protection
CPU_SPL_offset = 0x0D ; Stack Pointer Low
CPU_SPH_offset = 0x0E ; Stack Pointer High
CPU_SREG_offset = 0x0F ; Status Register
;*************************************************************************
;** CPUINT - Interrupt Controller
;*************************************************************************
CPUINT_CTRLA_offset = 0x00 ; Control A
CPUINT_STATUS_offset = 0x01 ; Status
CPUINT_LVL0PRI_offset = 0x02 ; Interrupt Level 0 Priority
CPUINT_LVL1VEC_offset = 0x03 ; Interrupt Level 1 Priority Vector
;*************************************************************************
;** CRCSCAN - CRCSCAN
;*************************************************************************
CRCSCAN_CTRLA_offset = 0x00 ; Control A
CRCSCAN_CTRLB_offset = 0x01 ; Control B
CRCSCAN_STATUS_offset = 0x02 ; Status
;*************************************************************************
;** DAC - Digital to Analog Converter
;*************************************************************************
DAC_CTRLA_offset = 0x00 ; Control Register A
DAC_DATA_offset = 0x01 ; DATA Register
;*************************************************************************
;** EVSYS - Event System
;*************************************************************************
EVSYS_ASYNCSTROBE_offset = 0x00 ; Asynchronous Channel Strobe
EVSYS_SYNCSTROBE_offset = 0x01 ; Synchronous Channel Strobe
EVSYS_ASYNCCH0_offset = 0x02 ; Asynchronous Channel 0 Generator Selection
EVSYS_ASYNCCH1_offset = 0x03 ; Asynchronous Channel 1 Generator Selection
EVSYS_ASYNCCH2_offset = 0x04 ; Asynchronous Channel 2 Generator Selection
EVSYS_ASYNCCH3_offset = 0x05 ; Asynchronous Channel 3 Generator Selection
EVSYS_SYNCCH0_offset = 0x0A ; Synchronous Channel 0 Generator Selection
EVSYS_SYNCCH1_offset = 0x0B ; Synchronous Channel 1 Generator Selection
EVSYS_ASYNCUSER0_offset = 0x12 ; Asynchronous User Ch 0 Input Selection - TCB0
EVSYS_ASYNCUSER1_offset = 0x13 ; Asynchronous User Ch 1 Input Selection - ADC0
EVSYS_ASYNCUSER2_offset = 0x14 ; Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0
EVSYS_ASYNCUSER3_offset = 0x15 ; Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0
EVSYS_ASYNCUSER4_offset = 0x16 ; Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1
EVSYS_ASYNCUSER5_offset = 0x17 ; Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1
EVSYS_ASYNCUSER6_offset = 0x18 ; Asynchronous User Ch 6 Input Selection - TCD0 Event 0
EVSYS_ASYNCUSER7_offset = 0x19 ; Asynchronous User Ch 7 Input Selection - TCD0 Event 1
EVSYS_ASYNCUSER8_offset = 0x1A ; Asynchronous User Ch 8 Input Selection - Event Out 0
EVSYS_ASYNCUSER9_offset = 0x1B ; Asynchronous User Ch 9 Input Selection - Event Out 1
EVSYS_ASYNCUSER10_offset = 0x1C ; Asynchronous User Ch 10 Input Selection - Event Out 2
EVSYS_SYNCUSER0_offset = 0x22 ; Synchronous User Ch 0 Input Selection - TCA0
EVSYS_SYNCUSER1_offset = 0x23 ; Synchronous User Ch 1 Input Selection - USART0
;*************************************************************************
;** FUSE - Fuses
;*************************************************************************
FUSE_WDTCFG_offset = 0x00 ; Watchdog Configuration
FUSE_BODCFG_offset = 0x01 ; BOD Configuration
FUSE_OSCCFG_offset = 0x02 ; Oscillator Configuration
FUSE_TCD0CFG_offset = 0x04 ; TCD0 Configuration
FUSE_SYSCFG0_offset = 0x05 ; System Configuration 0
FUSE_SYSCFG1_offset = 0x06 ; System Configuration 1
FUSE_APPEND_offset = 0x07 ; Application Code Section End
FUSE_BOOTEND_offset = 0x08 ; Boot Section End
;*************************************************************************
;** GPIO - General Purpose IO
;*************************************************************************
GPIO_GPIOR0_offset = 0x00 ; General Purpose IO Register 0
GPIO_GPIOR1_offset = 0x01 ; General Purpose IO Register 1
GPIO_GPIOR2_offset = 0x02 ; General Purpose IO Register 2
GPIO_GPIOR3_offset = 0x03 ; General Purpose IO Register 3
;*************************************************************************
;** LOCKBIT - Lockbit
;*************************************************************************
LOCKBIT_LOCKBIT_offset = 0x00 ; Lock bits
;*************************************************************************
;** NVMCTRL - Non-volatile Memory Controller
;*************************************************************************
NVMCTRL_CTRLA_offset = 0x00 ; Control A
NVMCTRL_CTRLB_offset = 0x01 ; Control B
NVMCTRL_STATUS_offset = 0x02 ; Status
NVMCTRL_INTCTRL_offset = 0x03 ; Interrupt Control
NVMCTRL_INTFLAGS_offset = 0x04 ; Interrupt Flags
NVMCTRL_DATA_offset = 0x06 ; Data
NVMCTRL_ADDR_offset = 0x08 ; Address
;*************************************************************************
;** PORT - I/O Ports
;*************************************************************************
PORT_DIR_offset = 0x00 ; Data Direction
PORT_DIRSET_offset = 0x01 ; Data Direction Set
PORT_DIRCLR_offset = 0x02 ; Data Direction Clear
PORT_DIRTGL_offset = 0x03 ; Data Direction Toggle
PORT_OUT_offset = 0x04 ; Output Value
PORT_OUTSET_offset = 0x05 ; Output Value Set
PORT_OUTCLR_offset = 0x06 ; Output Value Clear
PORT_OUTTGL_offset = 0x07 ; Output Value Toggle
PORT_IN_offset = 0x08 ; Input Value
PORT_INTFLAGS_offset = 0x09 ; Interrupt Flags
PORT_PIN0CTRL_offset = 0x10 ; Pin 0 Control
PORT_PIN1CTRL_offset = 0x11 ; Pin 1 Control
PORT_PIN2CTRL_offset = 0x12 ; Pin 2 Control
PORT_PIN3CTRL_offset = 0x13 ; Pin 3 Control
PORT_PIN4CTRL_offset = 0x14 ; Pin 4 Control
PORT_PIN5CTRL_offset = 0x15 ; Pin 5 Control
PORT_PIN6CTRL_offset = 0x16 ; Pin 6 Control
PORT_PIN7CTRL_offset = 0x17 ; Pin 7 Control
;*************************************************************************
;** PORTMUX - Port Multiplexer
;*************************************************************************
PORTMUX_CTRLA_offset = 0x00 ; Port Multiplexer Control A
PORTMUX_CTRLB_offset = 0x01 ; Port Multiplexer Control B
PORTMUX_CTRLC_offset = 0x02 ; Port Multiplexer Control C
PORTMUX_CTRLD_offset = 0x03 ; Port Multiplexer Control D
;*************************************************************************
;** RSTCTRL - Reset controller
;*************************************************************************
RSTCTRL_RSTFR_offset = 0x00 ; Reset Flags
RSTCTRL_SWRR_offset = 0x01 ; Software Reset
;*************************************************************************
;** RTC - Real-Time Counter
;*************************************************************************
RTC_CTRLA_offset = 0x00 ; Control A
RTC_STATUS_offset = 0x01 ; Status
RTC_INTCTRL_offset = 0x02 ; Interrupt Control
RTC_INTFLAGS_offset = 0x03 ; Interrupt Flags
RTC_TEMP_offset = 0x04 ; Temporary
RTC_DBGCTRL_offset = 0x05 ; Debug control
RTC_CLKSEL_offset = 0x07 ; Clock Select
RTC_CNT_offset = 0x08 ; Counter
RTC_PER_offset = 0x0A ; Period
RTC_CMP_offset = 0x0C ; Compare
RTC_PITCTRLA_offset = 0x10 ; PIT Control A
RTC_PITSTATUS_offset = 0x11 ; PIT Status
RTC_PITINTCTRL_offset = 0x12 ; PIT Interrupt Control
RTC_PITINTFLAGS_offset = 0x13 ; PIT Interrupt Flags
RTC_PITDBGCTRL_offset = 0x15 ; PIT Debug control
;*************************************************************************
;** SIGROW - Signature row
;*************************************************************************
SIGROW_DEVICEID0_offset = 0x00 ; Device ID Byte 0
SIGROW_DEVICEID1_offset = 0x01 ; Device ID Byte 1
SIGROW_DEVICEID2_offset = 0x02 ; Device ID Byte 2
SIGROW_SERNUM0_offset = 0x03 ; Serial Number Byte 0
SIGROW_SERNUM1_offset = 0x04 ; Serial Number Byte 1
SIGROW_SERNUM2_offset = 0x05 ; Serial Number Byte 2
SIGROW_SERNUM3_offset = 0x06 ; Serial Number Byte 3
SIGROW_SERNUM4_offset = 0x07 ; Serial Number Byte 4
SIGROW_SERNUM5_offset = 0x08 ; Serial Number Byte 5
SIGROW_SERNUM6_offset = 0x09 ; Serial Number Byte 6
SIGROW_SERNUM7_offset = 0x0A ; Serial Number Byte 7
SIGROW_SERNUM8_offset = 0x0B ; Serial Number Byte 8
SIGROW_SERNUM9_offset = 0x0C ; Serial Number Byte 9
SIGROW_TEMPSENSE0_offset = 0x20 ; Temperature Sensor Calibration Byte 0
SIGROW_TEMPSENSE1_offset = 0x21 ; Temperature Sensor Calibration Byte 1
SIGROW_OSC16ERR3V_offset = 0x22 ; OSC16 error at 3V
SIGROW_OSC16ERR5V_offset = 0x23 ; OSC16 error at 5V
SIGROW_OSC20ERR3V_offset = 0x24 ; OSC20 error at 3V
SIGROW_OSC20ERR5V_offset = 0x25 ; OSC20 error at 5V
;*************************************************************************
;** SLPCTRL - Sleep Controller
;*************************************************************************
SLPCTRL_CTRLA_offset = 0x00 ; Control
;*************************************************************************
;** SPI - Serial Peripheral Interface
;*************************************************************************
SPI_CTRLA_offset = 0x00 ; Control A
SPI_CTRLB_offset = 0x01 ; Control B
SPI_INTCTRL_offset = 0x02 ; Interrupt Control
SPI_INTFLAGS_offset = 0x03 ; Interrupt Flags
SPI_DATA_offset = 0x04 ; Data
;*************************************************************************
;** SYSCFG - System Configuration Registers
;*************************************************************************
SYSCFG_REVID_offset = 0x01 ; Revision ID
SYSCFG_EXTBRK_offset = 0x02 ; External Break
;*************************************************************************
;** TCA - 16-bit Timer/Counter Type A
;*************************************************************************
TCA_SINGLE_CTRLA_offset = 0x00 ; Control A
TCA_SINGLE_CTRLB_offset = 0x01 ; Control B
TCA_SINGLE_CTRLC_offset = 0x02 ; Control C
TCA_SINGLE_CTRLD_offset = 0x03 ; Control D
TCA_SINGLE_CTRLECLR_offset = 0x04 ; Control E Clear
TCA_SINGLE_CTRLESET_offset = 0x05 ; Control E Set
TCA_SINGLE_CTRLFCLR_offset = 0x06 ; Control F Clear
TCA_SINGLE_CTRLFSET_offset = 0x07 ; Control F Set
TCA_SINGLE_EVCTRL_offset = 0x09 ; Event Control
TCA_SINGLE_INTCTRL_offset = 0x0A ; Interrupt Control
TCA_SINGLE_INTFLAGS_offset = 0x0B ; Interrupt Flags
TCA_SINGLE_DBGCTRL_offset = 0x0E ; Degbug Control
TCA_SINGLE_TEMP_offset = 0x0F ; Temporary data for 16-bit Access
TCA_SINGLE_CNT_offset = 0x20 ; Count
TCA_SINGLE_PER_offset = 0x26 ; Period
TCA_SINGLE_CMP0_offset = 0x28 ; Compare 0
TCA_SINGLE_CMP1_offset = 0x2A ; Compare 1
TCA_SINGLE_CMP2_offset = 0x2C ; Compare 2
TCA_SINGLE_PERBUF_offset = 0x36 ; Period Buffer
TCA_SINGLE_CMP0BUF_offset = 0x38 ; Compare 0 Buffer
TCA_SINGLE_CMP1BUF_offset = 0x3A ; Compare 1 Buffer
TCA_SINGLE_CMP2BUF_offset = 0x3C ; Compare 2 Buffer
TCA_SPLIT_CTRLA_offset = 0x00 ; Control A
TCA_SPLIT_CTRLB_offset = 0x01 ; Control B
TCA_SPLIT_CTRLC_offset = 0x02 ; Control C
TCA_SPLIT_CTRLD_offset = 0x03 ; Control D
TCA_SPLIT_CTRLECLR_offset = 0x04 ; Control E Clear
TCA_SPLIT_CTRLESET_offset = 0x05 ; Control E Set
TCA_SPLIT_INTCTRL_offset = 0x0A ; Interrupt Control
TCA_SPLIT_INTFLAGS_offset = 0x0B ; Interrupt Flags
TCA_SPLIT_DBGCTRL_offset = 0x0E ; Degbug Control
TCA_SPLIT_LCNT_offset = 0x20 ; Low Count
TCA_SPLIT_HCNT_offset = 0x21 ; High Count
TCA_SPLIT_LPER_offset = 0x26 ; Low Period
TCA_SPLIT_HPER_offset = 0x27 ; High Period
TCA_SPLIT_LCMP0_offset = 0x28 ; Low Compare
TCA_SPLIT_HCMP0_offset = 0x29 ; High Compare
TCA_SPLIT_LCMP1_offset = 0x2A ; Low Compare
TCA_SPLIT_HCMP1_offset = 0x2B ; High Compare
TCA_SPLIT_LCMP2_offset = 0x2C ; Low Compare
TCA_SPLIT_HCMP2_offset = 0x2D ; High Compare
TCA_SINGLE_offset = 0x00 ;
TCA_SPLIT_offset = 0x00 ;
;*************************************************************************
;** TCB - 16-bit Timer Type B
;*************************************************************************
TCB_CTRLA_offset = 0x00 ; Control A
TCB_CTRLB_offset = 0x01 ; Control Register B
TCB_EVCTRL_offset = 0x04 ; Event Control
TCB_INTCTRL_offset = 0x05 ; Interrupt Control
TCB_INTFLAGS_offset = 0x06 ; Interrupt Flags
TCB_STATUS_offset = 0x07 ; Status
TCB_DBGCTRL_offset = 0x08 ; Debug Control
TCB_TEMP_offset = 0x09 ; Temporary Value
TCB_CNT_offset = 0x0A ; Count
TCB_CCMP_offset = 0x0C ; Compare or Capture
;*************************************************************************
;** TCD - Timer Counter D
;*************************************************************************
TCD_CTRLA_offset = 0x00 ; Control A
TCD_CTRLB_offset = 0x01 ; Control B
TCD_CTRLC_offset = 0x02 ; Control C
TCD_CTRLD_offset = 0x03 ; Control D
TCD_CTRLE_offset = 0x04 ; Control E
TCD_EVCTRLA_offset = 0x08 ; EVCTRLA
TCD_EVCTRLB_offset = 0x09 ; EVCTRLB
TCD_INTCTRL_offset = 0x0C ; Interrupt Control
TCD_INTFLAGS_offset = 0x0D ; Interrupt Flags
TCD_STATUS_offset = 0x0E ; Status
TCD_INPUTCTRLA_offset = 0x10 ; Input Control A
TCD_INPUTCTRLB_offset = 0x11 ; Input Control B
TCD_FAULTCTRL_offset = 0x12 ; Fault Control
TCD_DLYCTRL_offset = 0x14 ; Delay Control
TCD_DLYVAL_offset = 0x15 ; Delay value
TCD_DITCTRL_offset = 0x18 ; Dither Control A
TCD_DITVAL_offset = 0x19 ; Dither value
TCD_DBGCTRL_offset = 0x1E ; Debug Control
TCD_CAPTUREA_offset = 0x22 ; Capture A
TCD_CAPTUREB_offset = 0x24 ; Capture B
TCD_CMPASET_offset = 0x28 ; Compare A Set
TCD_CMPACLR_offset = 0x2A ; Compare A Clear
TCD_CMPBSET_offset = 0x2C ; Compare B Set
TCD_CMPBCLR_offset = 0x2E ; Compare B Clear
;*************************************************************************
;** TWI - Two-Wire Interface
;*************************************************************************
TWI_CTRLA_offset = 0x00 ; Control A
TWI_DBGCTRL_offset = 0x02 ; Debug Control Register
TWI_MCTRLA_offset = 0x03 ; Master Control A
TWI_MCTRLB_offset = 0x04 ; Master Control B
TWI_MSTATUS_offset = 0x05 ; Master Status
TWI_MBAUD_offset = 0x06 ; Master Baurd Rate Control
TWI_MADDR_offset = 0x07 ; Master Address
TWI_MDATA_offset = 0x08 ; Master Data
TWI_SCTRLA_offset = 0x09 ; Slave Control A
TWI_SCTRLB_offset = 0x0A ; Slave Control B
TWI_SSTATUS_offset = 0x0B ; Slave Status
TWI_SADDR_offset = 0x0C ; Slave Address
TWI_SDATA_offset = 0x0D ; Slave Data
TWI_SADDRMASK_offset = 0x0E ; Slave Address Mask
;*************************************************************************
;** USART - Universal Synchronous and Asynchronous Receiver and Transmitter
;*************************************************************************
USART_RXDATAL_offset = 0x00 ; Receive Data Low Byte
USART_RXDATAH_offset = 0x01 ; Receive Data High Byte
USART_TXDATAL_offset = 0x02 ; Transmit Data Low Byte
USART_TXDATAH_offset = 0x03 ; Transmit Data High Byte
USART_STATUS_offset = 0x04 ; Status
USART_CTRLA_offset = 0x05 ; Control A
USART_CTRLB_offset = 0x06 ; Control B
USART_CTRLC_offset = 0x07 ; Control C
USART_BAUD_offset = 0x08 ; Baud Rate
USART_DBGCTRL_offset = 0x0B ; Debug Control
USART_EVCTRL_offset = 0x0C ; Event Control
USART_TXPLCTRL_offset = 0x0D ; IRCOM Transmitter Pulse Length Control
USART_RXPLCTRL_offset = 0x0E ; IRCOM Receiver Pulse Length Control
;*************************************************************************
;** USERROW - User Row
;*************************************************************************