Urukul injection ignores switch and configuration state

[jordens]

Since core_cache _{cpld}_cfg is only used by injection, everything else (i.e. all experiments using that urukul) is unaware of it and conversely injection will be unaware of what cfg the experiments set. That state becomes inconsistent immediately in practice. Instead of core_cache, read the switch state (sta_read()) for each injection and build cfg from that. Also acknowledge and document that (1) all other cfg changes relative to ddb will be overwritten, (2) the channel will be reset (all DDS chip configuration lost), and (3) if the switch TTL RTIO channel is used and set high, injection is incapable of turning of the channel.

artiq/artiq/dashboard/moninj.py

Lines 616 to 626 in 2a7a72b

	cfg = self.core_cache.get("_{cpld}_cfg")
	if len(cfg) > 0:
	self.{cpld}.cfg_reg = cfg[0]
	else:
	delay(15*ms)
	self.{cpld}.init()
	self.core_cache.put("_{cpld}_cfg", [self.{cpld}.cfg_reg])
	cfg = self.core_cache.get("_{cpld}_cfg")
	delay(5*ms)
	self.{ch}.init()
	self.{ch}.cfg_sw({sw})

[jordens]

@Spaqin

[Spaqin]

The injection was made with several limitations in mind, mostly that cfg register is not readable from Urukul itself...

core_cache was used to determine whether or not CPLD needs initialization or not. Status register on its own won't tell me, as default values pre-init are as valid as they would be post validation.

However you have a point, this can be improved. We can also check for abnormalities in the cfg if the cached version doesn't exist - or maybe even cache the status register and compare against it, and update the cache when an external experiment changed something as well.

In similar manner, I'm thinking if it's possible to determine whether a dds channel was initialized too (read from dds register?).

Either way, thank you for the report :)

[jordens]

Right. Redesigning the CPLD gateware to remove those limitations is tracked at quartiq/urukul#7