diff --git a/arch/arm/src/stm32h5/Kconfig b/arch/arm/src/stm32h5/Kconfig index e133b916b62b1..7eaab1c75c826 100644 --- a/arch/arm/src/stm32h5/Kconfig +++ b/arch/arm/src/stm32h5/Kconfig @@ -3,28 +3,28 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -if ARCH_CHIP_STM32L5 +if ARCH_CHIP_STM32H5 -comment "STM32L5 Configuration Options" +comment "STM32H5 Configuration Options" choice prompt "STM32 L5 Chip Selection" - default ARCH_CHIP_STM32L552ZE - depends on ARCH_CHIP_STM32L5 + default ARCH_CHIP_STM32H552ZE + depends on ARCH_CHIP_STM32H5 -config ARCH_CHIP_STM32L552ZE - bool "STM32L552ZE" - select STM32L5_STM32L562XX - select STM32L5_FLASH_CONFIG_E - select STM32L5_IO_CONFIG_Z +config ARCH_CHIP_STM32H552ZE + bool "STM32H552ZE" + select STM32H5_STM32H562XX + select STM32H5_FLASH_CONFIG_E + select STM32H5_IO_CONFIG_Z ---help--- STM32 L5 Cortex M33, 512 Kb FLASH, 256 Kb SRAM -config ARCH_CHIP_STM32L562QE - bool "STM32L562QE" - select STM32L5_STM32L562XX - select STM32L5_FLASH_CONFIG_E - select STM32L5_IO_CONFIG_Q +config ARCH_CHIP_STM32H562QE + bool "STM32H562QE" + select STM32H5_STM32H562XX + select STM32H5_FLASH_CONFIG_E + select STM32H5_IO_CONFIG_Q ---help--- STM32 L5 Cortex M33, 512 Kb FLASH, 256 Kb SRAM @@ -32,24 +32,24 @@ endchoice # STM32 L5 Chip Selection # Chip families: -config STM32L5_STM32L562XX - # STM32L552 and STM32L562 devices documented in RM0439 +config STM32H5_STM32H562XX + # STM32H552 and STM32H562 devices documented in RM0439 bool default n select ARCH_HAVE_FPU - select STM32L5_HAVE_LPUART1 - select STM32L5_HAVE_USART1 - select STM32L5_HAVE_USART2 - select STM32L5_HAVE_USART3 - select STM32L5_HAVE_UART4 - select STM32L5_HAVE_UART5 + select STM32H5_HAVE_LPUART1 + select STM32H5_HAVE_USART1 + select STM32H5_HAVE_USART2 + select STM32H5_HAVE_USART3 + select STM32H5_HAVE_UART4 + select STM32H5_HAVE_UART5 choice prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32L5 - default STM32L5_FLASH_OVERRIDE_DEFAULT + depends on ARCH_CHIP_STM32H5 + default STM32H5_FLASH_OVERRIDE_DEFAULT ---help--- - STM32L5 series parts numbering (sans the package type) ends with a letter + STM32H5 series parts numbering (sans the package type) ends with a letter that designates the FLASH size. Designator Size in KiB @@ -65,128 +65,128 @@ choice STM32 Chip Selection. Examples: - If the STM32L576VE is chosen, the Flash configuration would be 'E', if a variant of + If the STM32H576VE is chosen, the Flash configuration would be 'E', if a variant of the part with a 1024 KiB Flash is released in the future one could simply select the 'G' designator here. - If an STM32L5xxx Series parts is chosen the default Flash configuration will be set + If an STM32H5xxx Series parts is chosen the default Flash configuration will be set herein and can be changed. -config STM32L5_FLASH_OVERRIDE_DEFAULT +config STM32H5_FLASH_OVERRIDE_DEFAULT bool "Default" -config STM32L5_FLASH_OVERRIDE_8 +config STM32H5_FLASH_OVERRIDE_8 bool "8 64 KB" -config STM32L5_FLASH_OVERRIDE_B +config STM32H5_FLASH_OVERRIDE_B bool "B 128 KB" -config STM32L5_FLASH_OVERRIDE_C +config STM32H5_FLASH_OVERRIDE_C bool "C 256 KB" -config STM32L5_FLASH_OVERRIDE_E +config STM32H5_FLASH_OVERRIDE_E bool "E 512 KB" -config STM32L5_FLASH_OVERRIDE_G +config STM32H5_FLASH_OVERRIDE_G bool "G 1024 KB" -config STM32L5_FLASH_OVERRIDE_I +config STM32H5_FLASH_OVERRIDE_I bool "I 2048 KB" endchoice # "Override Flash Size Designator" # Flash configurations -config STM32L5_FLASH_CONFIG_8 +config STM32H5_FLASH_CONFIG_8 bool default n - depends on STM32L5_STM32L512XX + depends on STM32H5_STM32H512XX -config STM32L5_FLASH_CONFIG_B +config STM32H5_FLASH_CONFIG_B bool default n - depends on STM32L5_STM32L5X1 || STM32L5_STM32L5X3 + depends on STM32H5_STM32H5X1 || STM32H5_STM32H5X3 -config STM32L5_FLASH_CONFIG_C +config STM32H5_FLASH_CONFIG_C bool default n - depends on !STM32L5_STM32L596XX + depends on !STM32H5_STM32H596XX -config STM32L5_FLASH_CONFIG_E +config STM32H5_FLASH_CONFIG_E bool default n -config STM32L5_FLASH_CONFIG_G +config STM32H5_FLASH_CONFIG_G bool default n - depends on STM32L5_STM32L5X5 || STM32L5_STM32L5X6 + depends on STM32H5_STM32H5X5 || STM32H5_STM32H5X6 -config STM32L5_FLASH_CONFIG_I +config STM32H5_FLASH_CONFIG_I bool default n - depends on STM32L5_STM32L5XR + depends on STM32H5_STM32H5XR # Pin/package configurations -config STM32L5_IO_CONFIG_K +config STM32H5_IO_CONFIG_K bool default n -config STM32L5_IO_CONFIG_T +config STM32H5_IO_CONFIG_T bool default n -config STM32L5_IO_CONFIG_C +config STM32H5_IO_CONFIG_C bool default n -config STM32L5_IO_CONFIG_R +config STM32H5_IO_CONFIG_R bool default n -config STM32L5_IO_CONFIG_J +config STM32H5_IO_CONFIG_J bool default n -config STM32L5_IO_CONFIG_M +config STM32H5_IO_CONFIG_M bool default n -config STM32L5_IO_CONFIG_V +config STM32H5_IO_CONFIG_V bool default n -config STM32L5_IO_CONFIG_Q +config STM32H5_IO_CONFIG_Q bool default n -config STM32L5_IO_CONFIG_Z +config STM32H5_IO_CONFIG_Z bool default n -config STM32L5_IO_CONFIG_A +config STM32H5_IO_CONFIG_A bool default n -comment "STM32L5 SRAM2 Options" +comment "STM32H5 SRAM2 Options" -config STM32L5_SRAM2_HEAP +config STM32H5_SRAM2_HEAP bool "SRAM2 is used for heap" default n - select STM32L5_SRAM2_INIT + select STM32H5_SRAM2_INIT ---help--- - The STM32L5 SRAM2 region has special properties (power, protection, parity) + The STM32H5 SRAM2 region has special properties (power, protection, parity) which may be used by the application for special purposes. But if these special properties are not needed, it may be instead added to the heap for use by malloc(). NOTE: you must also select an appropriate number of memory regions in the 'Memory Management' section. -config STM32L5_SRAM2_INIT +config STM32H5_SRAM2_INIT bool "SRAM2 is initialized to zero" default n ---help--- - The STM32L5 SRAM2 region has parity checking. However, when the system + The STM32H5 SRAM2 region has parity checking. However, when the system powers on, the memory is in an unknown state, and reads from uninitialized memory can trigger parity faults from the random data. This can be avoided by first writing to all locations to force the parity into a valid @@ -196,7 +196,7 @@ config STM32L5_SRAM2_INIT case, the board should handle the initialization itself at the appropriate time. -config STM32L5_USE_LEGACY_PINMAP +config STM32H5_USE_LEGACY_PINMAP bool "Use the legacy pinmap with GPIO_SPEED_xxx included." default y ---help--- @@ -206,55 +206,55 @@ config STM32L5_USE_LEGACY_PINMAP therefore is related to the layout and can only be properly set in board.h. - CONFIG_STM32L5_USE_LEGACY_PINMAP is provided, to allow lazy migration to + CONFIG_STM32H5_USE_LEGACY_PINMAP is provided, to allow lazy migration to using pinmaps without speeds. The work required to do this can be aided by running tools/stm32_pinmap_tool.py. The tools will take a board.h file and a legacy pinmap and output the required changes that one needs to make to a board.h file. - Eventually, CONFIG_STM32L5_USE_LEGACY_PINMAP will be deprecated and the + Eventually, CONFIG_STM32H5_USE_LEGACY_PINMAP will be deprecated and the legacy pinmaps removed from NuttX. Any new boards added should set - CONFIG_STM32L5_USE_LEGACY_PINMAP=n and fully define the pins in board.h + CONFIG_STM32H5_USE_LEGACY_PINMAP=n and fully define the pins in board.h -comment "STM32L5 Peripherals" +comment "STM32H5 Peripherals" -menu "STM32L5 Peripheral Support" +menu "STM32H5 Peripheral Support" # These "hidden" settings determine is a peripheral option is available for the # selection MCU -config STM32L5_HAVE_LPUART1 +config STM32H5_HAVE_LPUART1 bool default n -config STM32L5_HAVE_USART1 +config STM32H5_HAVE_USART1 bool default n -config STM32L5_HAVE_USART2 +config STM32H5_HAVE_USART2 bool default n -config STM32L5_HAVE_USART3 +config STM32H5_HAVE_USART3 bool default n -config STM32L5_HAVE_UART4 +config STM32H5_HAVE_UART4 bool default n -config STM32L5_HAVE_UART5 +config STM32H5_HAVE_UART5 bool default n # These "hidden" settings are the OR of individual peripheral selections # indicating that the general capability is required. -config STM32L5_SPI +config STM32H5_SPI bool default n -config STM32L5_USART +config STM32H5_USART bool default n @@ -268,106 +268,106 @@ comment "AHB3 Peripherals" comment "APB1 Peripherals" -config STM32L5_PWR +config STM32H5_PWR bool "PWR" default n -config STM32L5_RTC +config STM32H5_RTC bool "RTC" default n -config STM32L5_SPI2 +config STM32H5_SPI2 bool "SPI2" default n select SPI - select STM32L5_SPI + select STM32H5_SPI -config STM32L5_SPI3 +config STM32H5_SPI3 bool "SPI3" default n select SPI - select STM32L5_SPI + select STM32H5_SPI -config STM32L5_LPUART1 +config STM32H5_LPUART1 bool "LPUART1" default n - depends on STM32L5_HAVE_LPUART1 + depends on STM32H5_HAVE_LPUART1 select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART + select STM32H5_USART -config STM32L5_USART2 +config STM32H5_USART2 bool "USART2" default n - depends on STM32L5_HAVE_USART2 + depends on STM32H5_HAVE_USART2 select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART + select STM32H5_USART -config STM32L5_USART3 +config STM32H5_USART3 bool "USART3" default n - depends on STM32L5_HAVE_USART3 + depends on STM32H5_HAVE_USART3 select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART + select STM32H5_USART -config STM32L5_UART4 +config STM32H5_UART4 bool "UART4" default n - depends on STM32L5_HAVE_UART4 + depends on STM32H5_HAVE_UART4 select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART + select STM32H5_USART -config STM32L5_UART5 +config STM32H5_UART5 bool "UART5" default n - depends on STM32L5_HAVE_UART5 + depends on STM32H5_HAVE_UART5 select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART + select STM32H5_USART comment "APB2 Peripherals" -config STM32L5_SYSCFG +config STM32H5_SYSCFG bool "SYSCFG" default y -config STM32L5_SPI1 +config STM32H5_SPI1 bool "SPI1" default n select SPI - select STM32L5_SPI + select STM32H5_SPI -config STM32L5_USART1 +config STM32H5_USART1 bool "USART1" default n - depends on STM32L5_HAVE_USART1 + depends on STM32H5_HAVE_USART1 select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART + select STM32H5_USART endmenu -config STM32L5_SAI1PLL +config STM32H5_SAI1PLL bool "SAI1PLL" default n ---help--- - The STM32L5 has a separate PLL for the SAI1 block. + The STM32H5 has a separate PLL for the SAI1 block. Set this true and provide configuration parameters in board.h to use this PLL. -config STM32L5_SAI2PLL +config STM32H5_SAI2PLL bool "SAI2PLL" default n - depends on STM32L5_HAVE_SAI2 + depends on STM32H5_HAVE_SAI2 ---help--- - The STM32L5 has a separate PLL for the SAI2 block. + The STM32H5 has a separate PLL for the SAI2 block. Set this true and provide configuration parameters in board.h to use this PLL. -config STM32L5_FLASH_PREFETCH +config STM32H5_FLASH_PREFETCH bool "Enable FLASH Pre-fetch" default y ---help--- Enable FLASH prefetch -config STM32L5_DISABLE_IDLE_SLEEP_DURING_DEBUG +config STM32H5_DISABLE_IDLE_SLEEP_DURING_DEBUG bool "Disable IDLE Sleep (WFI) in debug mode" default n ---help--- @@ -376,21 +376,21 @@ config STM32L5_DISABLE_IDLE_SLEEP_DURING_DEBUG as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI instruction, the debugger will disconnect, terminating the debug session. -config ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG +config ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG bool "Custom clock configuration" default n ---help--- Enables special, board-specific STM32 clock configuration. -config STM32L5_HAVE_RTC_SUBSECONDS +config STM32H5_HAVE_RTC_SUBSECONDS bool select ARCH_HAVE_RTC_SUBSECONDS default y menu "RTC Configuration" - depends on STM32L5_RTC + depends on STM32H5_RTC -config STM32L5_RTC_MAGIC_REG +config STM32H5_RTC_MAGIC_REG int "BKP register" default 0 range 0 31 @@ -398,13 +398,13 @@ config STM32L5_RTC_MAGIC_REG The BKP register used to store/check the Magic value to determine if RTC is already setup -config STM32L5_RTC_MAGIC +config STM32H5_RTC_MAGIC hex "RTC Magic 1" default 0xfacefeed ---help--- Value used as Magic to determine if the RTC is already setup -config STM32L5_RTC_MAGIC_TIME_SET +config STM32H5_RTC_MAGIC_TIME_SET hex "RTC Magic 2" default 0xf00dface ---help--- @@ -413,29 +413,29 @@ config STM32L5_RTC_MAGIC_TIME_SET choice prompt "RTC clock source" - default STM32L5_RTC_LSECLOCK - depends on STM32L5_RTC + default STM32H5_RTC_LSECLOCK + depends on STM32H5_RTC -config STM32L5_RTC_LSECLOCK +config STM32H5_RTC_LSECLOCK bool "LSE clock" ---help--- Drive the RTC with the LSE clock -config STM32L5_RTC_LSICLOCK +config STM32H5_RTC_LSICLOCK bool "LSI clock" ---help--- Drive the RTC with the LSI clock -config STM32L5_RTC_HSECLOCK +config STM32H5_RTC_HSECLOCK bool "HSE clock" ---help--- Drive the RTC with the HSE clock, divided down to 1MHz. endchoice -if STM32L5_RTC_LSECLOCK +if STM32H5_RTC_LSECLOCK -config STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +config STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY bool "Automatically boost the LSE oscillator drive capability level until it starts-up" default n ---help--- @@ -448,27 +448,27 @@ config STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY 2 = Medium high drive capability 3 = High drive capability -config STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY +config STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY int "LSE oscillator drive capability level at LSE start-up" default 0 range 0 3 - depends on !STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + depends on !STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY ---help--- 0 = Low drive capability (default) 1 = Medium low drive capability 2 = Medium high drive capability 3 = High drive capability -config STM32L5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY +config STM32H5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY bool "Decrease LSE oscillator drive capability after LSE start-up" default n - depends on !STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + depends on !STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY ---help--- The LSE oscillator drive capability can remain at the level used during LSE start-up at run-time, or it can be reduced to the 'Low drive capability' once the LSE started up successfully. -endif # STM32L5_RTC_LSECLOCK +endif # STM32H5_RTC_LSECLOCK endmenu # RTC Configuration @@ -476,28 +476,28 @@ menu "Timer Configuration" if SCHED_TICKLESS -config STM32L5_ONESHOT +config STM32H5_ONESHOT bool default y -config STM32L5_FREERUN +config STM32H5_FREERUN bool default y -config STM32L5_TICKLESS_ONESHOT +config STM32H5_TICKLESS_ONESHOT int "Tickless one-shot timer channel" default 2 range 1 8 - depends on STM32L5_ONESHOT + depends on STM32H5_ONESHOT ---help--- If the Tickless OS feature is enabled, then one clock must be assigned to provide the one-shot timer needed by the OS. -config STM32L5_TICKLESS_FREERUN +config STM32H5_TICKLESS_FREERUN int "Tickless free-running timer channel" default 5 range 1 8 - depends on STM32L5_FREERUN + depends on STM32H5_FREERUN ---help--- If the Tickless OS feature is enabled, then one clock must be assigned to provide the free-running timer needed by the OS. @@ -506,14 +506,14 @@ endif # SCHED_TICKLESS if !SCHED_TICKLESS -config STM32L5_ONESHOT +config STM32H5_ONESHOT bool "TIM one-shot wrapper" default n ---help--- Enable a wrapper around the low level timer/counter functions to support one-shot timer. -config STM32L5_FREERUN +config STM32H5_FREERUN bool "TIM free-running wrapper" default n ---help--- @@ -522,228 +522,228 @@ config STM32L5_FREERUN endif # !SCHED_TICKLESS -config STM32L5_ONESHOT_MAXTIMERS +config STM32H5_ONESHOT_MAXTIMERS int "Maximum number of oneshot timers" default 1 range 1 8 - depends on STM32L5_ONESHOT + depends on STM32H5_ONESHOT ---help--- Determines the maximum number of oneshot timers that can be supported. This setting pre-allocates some minimal support for each of the timers and places an upper limit on the number of oneshot timers that you can use. -config STM32L5_LPTIM1_PWM +config STM32H5_LPTIM1_PWM bool "LPTIM1 PWM" default n - depends on STM32L5_LPTIM1 + depends on STM32H5_LPTIM1 select PWM ---help--- Reserve low-power timer 1 for use by PWM Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_LPTIM1 + to generate modulated outputs for such things as motor control. If STM32H5_LPTIM1 is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. -if STM32L5_LPTIM1_PWM +if STM32H5_LPTIM1_PWM choice prompt "LPTIM1 clock source" - default STM32L5_LPTIM1_CLK_APB1 + default STM32H5_LPTIM1_CLK_APB1 -config STM32L5_LPTIM1_CLK_APB1 +config STM32H5_LPTIM1_CLK_APB1 bool "Clock LPTIM1 from APB1" -config STM32L5_LPTIM1_CLK_LSE +config STM32H5_LPTIM1_CLK_LSE bool "Clock LPTIM1 from LSE" -config STM32L5_LPTIM1_CLK_LSI +config STM32H5_LPTIM1_CLK_LSI bool "Clock LPTIM1 from LSI" -config STM32L5_LPTIM1_CLK_HSI +config STM32H5_LPTIM1_CLK_HSI bool "Clock LPTIM1 from HSI" endchoice -endif # STM32L5_LPTIM1_PWM +endif # STM32H5_LPTIM1_PWM -config STM32L5_LPTIM2_PWM +config STM32H5_LPTIM2_PWM bool "LPTIM2 PWM" default n - depends on STM32L5_LPTIM2 + depends on STM32H5_LPTIM2 select PWM ---help--- Reserve low-power timer 2 for use by PWM Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_LPTIM2 + to generate modulated outputs for such things as motor control. If STM32H5_LPTIM2 is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. -if STM32L5_LPTIM2_PWM +if STM32H5_LPTIM2_PWM choice prompt "LPTIM2 clock source" - default STM32L5_LPTIM2_CLK_APB1 + default STM32H5_LPTIM2_CLK_APB1 -config STM32L5_LPTIM2_CLK_APB1 +config STM32H5_LPTIM2_CLK_APB1 bool "Clock LPTIM2 from APB1" -config STM32L5_LPTIM2_CLK_LSE +config STM32H5_LPTIM2_CLK_LSE bool "Clock LPTIM2 from LSE" -config STM32L5_LPTIM2_CLK_LSI +config STM32H5_LPTIM2_CLK_LSI bool "Clock LPTIM2 from LSI" -config STM32L5_LPTIM2_CLK_HSI +config STM32H5_LPTIM2_CLK_HSI bool "Clock LPTIM2 from HSI" endchoice -endif # STM32L5_LPTIM2_PWM +endif # STM32H5_LPTIM2_PWM -config STM32L5_TIM1_PWM +config STM32H5_TIM1_PWM bool "TIM1 PWM" default n - depends on STM32L5_TIM1 + depends on STM32H5_TIM1 select PWM select ARCH_HAVE_PWM_PULSECOUNT ---help--- Reserve timer 1 for use by PWM Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM1 + to generate modulated outputs for such things as motor control. If STM32H5_TIM1 is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. -if STM32L5_TIM1_PWM +if STM32H5_TIM1_PWM -config STM32L5_TIM1_MODE +config STM32H5_TIM1_MODE int "TIM1 Mode" default 0 range 0 4 ---help--- Specifies the timer mode. -if STM32L5_PWM_MULTICHAN +if STM32H5_PWM_MULTICHAN -config STM32L5_TIM1_CHANNEL1 +config STM32H5_TIM1_CHANNEL1 bool "TIM1 Channel 1" default n ---help--- Enables channel 1. -if STM32L5_TIM1_CHANNEL1 +if STM32H5_TIM1_CHANNEL1 -config STM32L5_TIM1_CH1MODE +config STM32H5_TIM1_CH1MODE int "TIM1 Channel 1 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM1_CH1OUT +config STM32H5_TIM1_CH1OUT bool "TIM1 Channel 1 Output" default n ---help--- Enables channel 1 output. -config STM32L5_TIM1_CH1NOUT +config STM32H5_TIM1_CH1NOUT bool "TIM1 Channel 1 Complementary Output" default n - depends on STM32L5_TIM1_CH1OUT + depends on STM32H5_TIM1_CH1OUT ---help--- Enables channel 1 complementary output. -endif # STM32L5_TIM1_CHANNEL1 +endif # STM32H5_TIM1_CHANNEL1 -config STM32L5_TIM1_CHANNEL2 +config STM32H5_TIM1_CHANNEL2 bool "TIM1 Channel 2" default n ---help--- Enables channel 2. -if STM32L5_TIM1_CHANNEL2 +if STM32H5_TIM1_CHANNEL2 -config STM32L5_TIM1_CH2MODE +config STM32H5_TIM1_CH2MODE int "TIM1 Channel 2 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM1_CH2OUT +config STM32H5_TIM1_CH2OUT bool "TIM1 Channel 2 Output" default n ---help--- Enables channel 2 output. -config STM32L5_TIM1_CH2NOUT +config STM32H5_TIM1_CH2NOUT bool "TIM1 Channel 2 Complemenrary Output" default n - depends on STM32L5_TIM1_CH2OUT + depends on STM32H5_TIM1_CH2OUT ---help--- Enables channel 2 complementary output. -endif # STM32L5_TIM1_CHANNEL2 +endif # STM32H5_TIM1_CHANNEL2 -config STM32L5_TIM1_CHANNEL3 +config STM32H5_TIM1_CHANNEL3 bool "TIM1 Channel 3" default n ---help--- Enables channel 3. -if STM32L5_TIM1_CHANNEL3 +if STM32H5_TIM1_CHANNEL3 -config STM32L5_TIM1_CH3MODE +config STM32H5_TIM1_CH3MODE int "TIM1 Channel 3 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM1_CH3OUT +config STM32H5_TIM1_CH3OUT bool "TIM1 Channel 3 Output" default n ---help--- Enables channel 3 output. -config STM32L5_TIM1_CH3NOUT +config STM32H5_TIM1_CH3NOUT bool "TIM1 Channel 3 Complementary Output" default n - depends on STM32L5_TIM1_CH3OUT + depends on STM32H5_TIM1_CH3OUT ---help--- Enables channel 3 complementary output. -endif # STM32L5_TIM1_CHANNEL3 +endif # STM32H5_TIM1_CHANNEL3 -config STM32L5_TIM1_CHANNEL5 +config STM32H5_TIM1_CHANNEL5 bool "TIM1 Channel 4" default n ---help--- Enables channel 4. -if STM32L5_TIM1_CHANNEL5 +if STM32H5_TIM1_CHANNEL5 -config STM32L5_TIM1_CH4MODE +config STM32H5_TIM1_CH4MODE int "TIM1 Channel 4 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM1_CH4OUT +config STM32H5_TIM1_CH4OUT bool "TIM1 Channel 4 Output" default n ---help--- Enables channel 4 output. -endif # STM32L5_TIM1_CHANNEL5 +endif # STM32H5_TIM1_CHANNEL5 -endif # STM32L5_PWM_MULTICHAN +endif # STM32H5_PWM_MULTICHAN -if !STM32L5_PWM_MULTICHAN +if !STM32H5_PWM_MULTICHAN -config STM32L5_TIM1_CHANNEL +config STM32H5_TIM1_CHANNEL int "TIM1 PWM Output Channel" default 1 range 1 4 @@ -751,139 +751,139 @@ config STM32L5_TIM1_CHANNEL If TIM1 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} -config STM32L5_TIM1_CHMODE +config STM32H5_TIM1_CHMODE int "TIM1 Channel Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -endif # !STM32L5_PWM_MULTICHAN +endif # !STM32H5_PWM_MULTICHAN -endif # STM32L5_TIM1_PWM +endif # STM32H5_TIM1_PWM -config STM32L5_TIM2_PWM +config STM32H5_TIM2_PWM bool "TIM2 PWM" default n - depends on STM32L5_TIM2 + depends on STM32H5_TIM2 select PWM select ARCH_HAVE_PWM_PULSECOUNT ---help--- Reserve timer 2 for use by PWM Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM2 + to generate modulated outputs for such things as motor control. If STM32H5_TIM2 is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. -if STM32L5_TIM2_PWM +if STM32H5_TIM2_PWM -config STM32L5_TIM2_MODE +config STM32H5_TIM2_MODE int "TIM2 Mode" default 0 range 0 4 ---help--- Specifies the timer mode. -if STM32L5_PWM_MULTICHAN +if STM32H5_PWM_MULTICHAN -config STM32L5_TIM2_CHANNEL1 +config STM32H5_TIM2_CHANNEL1 bool "TIM2 Channel 1" default n ---help--- Enables channel 1. -if STM32L5_TIM2_CHANNEL1 +if STM32H5_TIM2_CHANNEL1 -config STM32L5_TIM2_CH1MODE +config STM32H5_TIM2_CH1MODE int "TIM2 Channel 1 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM2_CH1OUT +config STM32H5_TIM2_CH1OUT bool "TIM2 Channel 1 Output" default n ---help--- Enables channel 1 output. -endif # STM32L5_TIM2_CHANNEL1 +endif # STM32H5_TIM2_CHANNEL1 -config STM32L5_TIM2_CHANNEL2 +config STM32H5_TIM2_CHANNEL2 bool "TIM2 Channel 2" default n ---help--- Enables channel 2. -if STM32L5_TIM2_CHANNEL2 +if STM32H5_TIM2_CHANNEL2 -config STM32L5_TIM2_CH2MODE +config STM32H5_TIM2_CH2MODE int "TIM2 Channel 2 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM2_CH2OUT +config STM32H5_TIM2_CH2OUT bool "TIM2 Channel 2 Output" default n ---help--- Enables channel 2 output. -endif # STM32L5_TIM2_CHANNEL2 +endif # STM32H5_TIM2_CHANNEL2 -config STM32L5_TIM2_CHANNEL3 +config STM32H5_TIM2_CHANNEL3 bool "TIM2 Channel 3" default n ---help--- Enables channel 3. -if STM32L5_TIM2_CHANNEL3 +if STM32H5_TIM2_CHANNEL3 -config STM32L5_TIM2_CH3MODE +config STM32H5_TIM2_CH3MODE int "TIM2 Channel 3 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM2_CH3OUT +config STM32H5_TIM2_CH3OUT bool "TIM2 Channel 3 Output" default n ---help--- Enables channel 3 output. -endif # STM32L5_TIM2_CHANNEL3 +endif # STM32H5_TIM2_CHANNEL3 -config STM32L5_TIM2_CHANNEL5 +config STM32H5_TIM2_CHANNEL5 bool "TIM2 Channel 4" default n ---help--- Enables channel 4. -if STM32L5_TIM2_CHANNEL5 +if STM32H5_TIM2_CHANNEL5 -config STM32L5_TIM2_CH4MODE +config STM32H5_TIM2_CH4MODE int "TIM2 Channel 4 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM2_CH4OUT +config STM32H5_TIM2_CH4OUT bool "TIM2 Channel 4 Output" default n ---help--- Enables channel 4 output. -endif # STM32L5_TIM2_CHANNEL5 +endif # STM32H5_TIM2_CHANNEL5 -endif # STM32L5_PWM_MULTICHAN +endif # STM32H5_PWM_MULTICHAN -if !STM32L5_PWM_MULTICHAN +if !STM32H5_PWM_MULTICHAN -config STM32L5_TIM2_CHANNEL +config STM32H5_TIM2_CHANNEL int "TIM2 PWM Output Channel" default 1 range 1 4 @@ -891,139 +891,139 @@ config STM32L5_TIM2_CHANNEL If TIM2 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} -config STM32L5_TIM2_CHMODE +config STM32H5_TIM2_CHMODE int "TIM2 Channel Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -endif # !STM32L5_PWM_MULTICHAN +endif # !STM32H5_PWM_MULTICHAN -endif # STM32L5_TIM2_PWM +endif # STM32H5_TIM2_PWM -config STM32L5_TIM3_PWM +config STM32H5_TIM3_PWM bool "TIM3 PWM" default n - depends on STM32L5_TIM3 + depends on STM32H5_TIM3 select PWM select ARCH_HAVE_PWM_PULSECOUNT ---help--- Reserve timer 3 for use by PWM Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM3 + to generate modulated outputs for such things as motor control. If STM32H5_TIM3 is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. -if STM32L5_TIM3_PWM +if STM32H5_TIM3_PWM -config STM32L5_TIM3_MODE +config STM32H5_TIM3_MODE int "TIM3 Mode" default 0 range 0 4 ---help--- Specifies the timer mode. -if STM32L5_PWM_MULTICHAN +if STM32H5_PWM_MULTICHAN -config STM32L5_TIM3_CHANNEL1 +config STM32H5_TIM3_CHANNEL1 bool "TIM3 Channel 1" default n ---help--- Enables channel 1. -if STM32L5_TIM3_CHANNEL1 +if STM32H5_TIM3_CHANNEL1 -config STM32L5_TIM3_CH1MODE +config STM32H5_TIM3_CH1MODE int "TIM3 Channel 1 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM3_CH1OUT +config STM32H5_TIM3_CH1OUT bool "TIM3 Channel 1 Output" default n ---help--- Enables channel 1 output. -endif # STM32L5_TIM3_CHANNEL1 +endif # STM32H5_TIM3_CHANNEL1 -config STM32L5_TIM3_CHANNEL2 +config STM32H5_TIM3_CHANNEL2 bool "TIM3 Channel 2" default n ---help--- Enables channel 2. -if STM32L5_TIM3_CHANNEL2 +if STM32H5_TIM3_CHANNEL2 -config STM32L5_TIM3_CH2MODE +config STM32H5_TIM3_CH2MODE int "TIM3 Channel 2 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM3_CH2OUT +config STM32H5_TIM3_CH2OUT bool "TIM3 Channel 2 Output" default n ---help--- Enables channel 2 output. -endif # STM32L5_TIM3_CHANNEL2 +endif # STM32H5_TIM3_CHANNEL2 -config STM32L5_TIM3_CHANNEL3 +config STM32H5_TIM3_CHANNEL3 bool "TIM3 Channel 3" default n ---help--- Enables channel 3. -if STM32L5_TIM3_CHANNEL3 +if STM32H5_TIM3_CHANNEL3 -config STM32L5_TIM3_CH3MODE +config STM32H5_TIM3_CH3MODE int "TIM3 Channel 3 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM3_CH3OUT +config STM32H5_TIM3_CH3OUT bool "TIM3 Channel 3 Output" default n ---help--- Enables channel 3 output. -endif # STM32L5_TIM3_CHANNEL3 +endif # STM32H5_TIM3_CHANNEL3 -config STM32L5_TIM3_CHANNEL5 +config STM32H5_TIM3_CHANNEL5 bool "TIM3 Channel 4" default n ---help--- Enables channel 4. -if STM32L5_TIM3_CHANNEL5 +if STM32H5_TIM3_CHANNEL5 -config STM32L5_TIM3_CH4MODE +config STM32H5_TIM3_CH4MODE int "TIM3 Channel 4 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM3_CH4OUT +config STM32H5_TIM3_CH4OUT bool "TIM3 Channel 4 Output" default n ---help--- Enables channel 4 output. -endif # STM32L5_TIM3_CHANNEL5 +endif # STM32H5_TIM3_CHANNEL5 -endif # STM32L5_PWM_MULTICHAN +endif # STM32H5_PWM_MULTICHAN -if !STM32L5_PWM_MULTICHAN +if !STM32H5_PWM_MULTICHAN -config STM32L5_TIM3_CHANNEL +config STM32H5_TIM3_CHANNEL int "TIM3 PWM Output Channel" default 1 range 1 4 @@ -1031,139 +1031,139 @@ config STM32L5_TIM3_CHANNEL If TIM3 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} -config STM32L5_TIM3_CHMODE +config STM32H5_TIM3_CHMODE int "TIM3 Channel Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -endif # !STM32L5_PWM_MULTICHAN +endif # !STM32H5_PWM_MULTICHAN -endif # STM32L5_TIM3_PWM +endif # STM32H5_TIM3_PWM -config STM32L5_TIM4_PWM +config STM32H5_TIM4_PWM bool "TIM4 PWM" default n - depends on STM32L5_TIM4 + depends on STM32H5_TIM4 select PWM select ARCH_HAVE_PWM_PULSECOUNT ---help--- Reserve timer 4 for use by PWM Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM4 + to generate modulated outputs for such things as motor control. If STM32H5_TIM4 is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. -if STM32L5_TIM4_PWM +if STM32H5_TIM4_PWM -config STM32L5_TIM4_MODE +config STM32H5_TIM4_MODE int "TIM4 Mode" default 0 range 0 4 ---help--- Specifies the timer mode. -if STM32L5_PWM_MULTICHAN +if STM32H5_PWM_MULTICHAN -config STM32L5_TIM4_CHANNEL1 +config STM32H5_TIM4_CHANNEL1 bool "TIM4 Channel 1" default n ---help--- Enables channel 1. -if STM32L5_TIM4_CHANNEL1 +if STM32H5_TIM4_CHANNEL1 -config STM32L5_TIM4_CH1MODE +config STM32H5_TIM4_CH1MODE int "TIM4 Channel 1 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM4_CH1OUT +config STM32H5_TIM4_CH1OUT bool "TIM4 Channel 1 Output" default n ---help--- Enables channel 1 output. -endif # STM32L5_TIM4_CHANNEL1 +endif # STM32H5_TIM4_CHANNEL1 -config STM32L5_TIM4_CHANNEL2 +config STM32H5_TIM4_CHANNEL2 bool "TIM4 Channel 2" default n ---help--- Enables channel 2. -if STM32L5_TIM4_CHANNEL2 +if STM32H5_TIM4_CHANNEL2 -config STM32L5_TIM4_CH2MODE +config STM32H5_TIM4_CH2MODE int "TIM4 Channel 2 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM4_CH2OUT +config STM32H5_TIM4_CH2OUT bool "TIM4 Channel 2 Output" default n ---help--- Enables channel 2 output. -endif # STM32L5_TIM4_CHANNEL2 +endif # STM32H5_TIM4_CHANNEL2 -config STM32L5_TIM4_CHANNEL3 +config STM32H5_TIM4_CHANNEL3 bool "TIM4 Channel 3" default n ---help--- Enables channel 3. -if STM32L5_TIM4_CHANNEL3 +if STM32H5_TIM4_CHANNEL3 -config STM32L5_TIM4_CH3MODE +config STM32H5_TIM4_CH3MODE int "TIM4 Channel 3 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM4_CH3OUT +config STM32H5_TIM4_CH3OUT bool "TIM4 Channel 3 Output" default n ---help--- Enables channel 3 output. -endif # STM32L5_TIM4_CHANNEL3 +endif # STM32H5_TIM4_CHANNEL3 -config STM32L5_TIM4_CHANNEL5 +config STM32H5_TIM4_CHANNEL5 bool "TIM4 Channel 4" default n ---help--- Enables channel 4. -if STM32L5_TIM4_CHANNEL5 +if STM32H5_TIM4_CHANNEL5 -config STM32L5_TIM4_CH4MODE +config STM32H5_TIM4_CH4MODE int "TIM4 Channel 4 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM4_CH4OUT +config STM32H5_TIM4_CH4OUT bool "TIM4 Channel 4 Output" default n ---help--- Enables channel 4 output. -endif # STM32L5_TIM4_CHANNEL5 +endif # STM32H5_TIM4_CHANNEL5 -endif # STM32L5_PWM_MULTICHAN +endif # STM32H5_PWM_MULTICHAN -if !STM32L5_PWM_MULTICHAN +if !STM32H5_PWM_MULTICHAN -config STM32L5_TIM4_CHANNEL +config STM32H5_TIM4_CHANNEL int "TIM4 PWM Output Channel" default 1 range 1 4 @@ -1171,139 +1171,139 @@ config STM32L5_TIM4_CHANNEL If TIM4 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} -config STM32L5_TIM4_CHMODE +config STM32H5_TIM4_CHMODE int "TIM4 Channel Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -endif # !STM32L5_PWM_MULTICHAN +endif # !STM32H5_PWM_MULTICHAN -endif # STM32L5_TIM4_PWM +endif # STM32H5_TIM4_PWM -config STM32L5_TIM5_PWM +config STM32H5_TIM5_PWM bool "TIM5 PWM" default n - depends on STM32L5_TIM5 + depends on STM32H5_TIM5 select PWM select ARCH_HAVE_PWM_PULSECOUNT ---help--- Reserve timer 5 for use by PWM Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM5 + to generate modulated outputs for such things as motor control. If STM32H5_TIM5 is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. -if STM32L5_TIM5_PWM +if STM32H5_TIM5_PWM -config STM32L5_TIM5_MODE +config STM32H5_TIM5_MODE int "TIM5 Mode" default 0 range 0 4 ---help--- Specifies the timer mode. -if STM32L5_PWM_MULTICHAN +if STM32H5_PWM_MULTICHAN -config STM32L5_TIM5_CHANNEL1 +config STM32H5_TIM5_CHANNEL1 bool "TIM5 Channel 1" default n ---help--- Enables channel 1. -if STM32L5_TIM5_CHANNEL1 +if STM32H5_TIM5_CHANNEL1 -config STM32L5_TIM5_CH1MODE +config STM32H5_TIM5_CH1MODE int "TIM5 Channel 1 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM5_CH1OUT +config STM32H5_TIM5_CH1OUT bool "TIM5 Channel 1 Output" default n ---help--- Enables channel 1 output. -endif # STM32L5_TIM5_CHANNEL1 +endif # STM32H5_TIM5_CHANNEL1 -config STM32L5_TIM5_CHANNEL2 +config STM32H5_TIM5_CHANNEL2 bool "TIM5 Channel 2" default n ---help--- Enables channel 2. -if STM32L5_TIM5_CHANNEL2 +if STM32H5_TIM5_CHANNEL2 -config STM32L5_TIM5_CH2MODE +config STM32H5_TIM5_CH2MODE int "TIM5 Channel 2 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM5_CH2OUT +config STM32H5_TIM5_CH2OUT bool "TIM5 Channel 2 Output" default n ---help--- Enables channel 2 output. -endif # STM32L5_TIM5_CHANNEL2 +endif # STM32H5_TIM5_CHANNEL2 -config STM32L5_TIM5_CHANNEL3 +config STM32H5_TIM5_CHANNEL3 bool "TIM5 Channel 3" default n ---help--- Enables channel 3. -if STM32L5_TIM5_CHANNEL3 +if STM32H5_TIM5_CHANNEL3 -config STM32L5_TIM5_CH3MODE +config STM32H5_TIM5_CH3MODE int "TIM5 Channel 3 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM5_CH3OUT +config STM32H5_TIM5_CH3OUT bool "TIM5 Channel 3 Output" default n ---help--- Enables channel 3 output. -endif # STM32L5_TIM5_CHANNEL3 +endif # STM32H5_TIM5_CHANNEL3 -config STM32L5_TIM5_CHANNEL5 +config STM32H5_TIM5_CHANNEL5 bool "TIM5 Channel 4" default n ---help--- Enables channel 4. -if STM32L5_TIM5_CHANNEL5 +if STM32H5_TIM5_CHANNEL5 -config STM32L5_TIM5_CH4MODE +config STM32H5_TIM5_CH4MODE int "TIM5 Channel 4 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM5_CH4OUT +config STM32H5_TIM5_CH4OUT bool "TIM5 Channel 4 Output" default n ---help--- Enables channel 4 output. -endif # STM32L5_TIM5_CHANNEL5 +endif # STM32H5_TIM5_CHANNEL5 -endif # STM32L5_PWM_MULTICHAN +endif # STM32H5_PWM_MULTICHAN -if !STM32L5_PWM_MULTICHAN +if !STM32H5_PWM_MULTICHAN -config STM32L5_TIM5_CHANNEL +config STM32H5_TIM5_CHANNEL int "TIM5 PWM Output Channel" default 1 range 1 4 @@ -1311,160 +1311,160 @@ config STM32L5_TIM5_CHANNEL If TIM5 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} -config STM32L5_TIM5_CHMODE +config STM32H5_TIM5_CHMODE int "TIM5 Channel Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -endif # !STM32L5_PWM_MULTICHAN +endif # !STM32H5_PWM_MULTICHAN -endif # STM32L5_TIM5_PWM +endif # STM32H5_TIM5_PWM -config STM32L5_TIM8_PWM +config STM32H5_TIM8_PWM bool "TIM8 PWM" default n - depends on STM32L5_TIM8 + depends on STM32H5_TIM8 select PWM select ARCH_HAVE_PWM_PULSECOUNT ---help--- Reserve timer 8 for use by PWM Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM8 + to generate modulated outputs for such things as motor control. If STM32H5_TIM8 is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. -if STM32L5_TIM8_PWM +if STM32H5_TIM8_PWM -config STM32L5_TIM8_MODE +config STM32H5_TIM8_MODE int "TIM8 Mode" default 0 range 0 4 ---help--- Specifies the timer mode. -if STM32L5_PWM_MULTICHAN +if STM32H5_PWM_MULTICHAN -config STM32L5_TIM8_CHANNEL1 +config STM32H5_TIM8_CHANNEL1 bool "TIM8 Channel 1" default n ---help--- Enables channel 1. -if STM32L5_TIM8_CHANNEL1 +if STM32H5_TIM8_CHANNEL1 -config STM32L5_TIM8_CH1MODE +config STM32H5_TIM8_CH1MODE int "TIM8 Channel 1 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM8_CH1OUT +config STM32H5_TIM8_CH1OUT bool "TIM8 Channel 1 Output" default n ---help--- Enables channel 1 output. -config STM32L5_TIM8_CH1NOUT +config STM32H5_TIM8_CH1NOUT bool "TIM8 Channel 1 Complementary Output" default n - depends on STM32L5_TIM8_CH1OUT + depends on STM32H5_TIM8_CH1OUT ---help--- Enables channel 1 complementary output. -endif # STM32L5_TIM8_CHANNEL1 +endif # STM32H5_TIM8_CHANNEL1 -config STM32L5_TIM8_CHANNEL2 +config STM32H5_TIM8_CHANNEL2 bool "TIM8 Channel 2" default n ---help--- Enables channel 2. -if STM32L5_TIM8_CHANNEL2 +if STM32H5_TIM8_CHANNEL2 -config STM32L5_TIM8_CH2MODE +config STM32H5_TIM8_CH2MODE int "TIM8 Channel 2 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM8_CH2OUT +config STM32H5_TIM8_CH2OUT bool "TIM8 Channel 2 Output" default n ---help--- Enables channel 2 output. -config STM32L5_TIM8_CH2NOUT +config STM32H5_TIM8_CH2NOUT bool "TIM8 Channel 2 Complementary Output" default n - depends on STM32L5_TIM8_CH2OUT + depends on STM32H5_TIM8_CH2OUT ---help--- Enables channel 2 complementary output. -endif # STM32L5_TIM8_CHANNEL2 +endif # STM32H5_TIM8_CHANNEL2 -config STM32L5_TIM8_CHANNEL3 +config STM32H5_TIM8_CHANNEL3 bool "TIM8 Channel 3" default n ---help--- Enables channel 3. -if STM32L5_TIM8_CHANNEL3 +if STM32H5_TIM8_CHANNEL3 -config STM32L5_TIM8_CH3MODE +config STM32H5_TIM8_CH3MODE int "TIM8 Channel 3 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM8_CH3OUT +config STM32H5_TIM8_CH3OUT bool "TIM8 Channel 3 Output" default n ---help--- Enables channel 3 output. -config STM32L5_TIM8_CH3NOUT +config STM32H5_TIM8_CH3NOUT bool "TIM8 Channel 3 Complementary Output" default n - depends on STM32L5_TIM8_CH3OUT + depends on STM32H5_TIM8_CH3OUT ---help--- Enables channel 3 complementary output. -endif # STM32L5_TIM8_CHANNEL3 +endif # STM32H5_TIM8_CHANNEL3 -config STM32L5_TIM8_CHANNEL5 +config STM32H5_TIM8_CHANNEL5 bool "TIM8 Channel 4" default n ---help--- Enables channel 4. -if STM32L5_TIM8_CHANNEL5 +if STM32H5_TIM8_CHANNEL5 -config STM32L5_TIM8_CH4MODE +config STM32H5_TIM8_CH4MODE int "TIM8 Channel 4 Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -config STM32L5_TIM8_CH4OUT +config STM32H5_TIM8_CH4OUT bool "TIM8 Channel 4 Output" default n ---help--- Enables channel 4 output. -endif # STM32L5_TIM8_CHANNEL5 +endif # STM32H5_TIM8_CHANNEL5 -endif # STM32L5_PWM_MULTICHAN +endif # STM32H5_PWM_MULTICHAN -if !STM32L5_PWM_MULTICHAN +if !STM32H5_PWM_MULTICHAN -config STM32L5_TIM8_CHANNEL +config STM32H5_TIM8_CHANNEL int "TIM8 PWM Output Channel" default 1 range 1 4 @@ -1472,92 +1472,92 @@ config STM32L5_TIM8_CHANNEL If TIM8 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} -config STM32L5_TIM8_CHMODE +config STM32H5_TIM8_CHMODE int "TIM8 Channel Mode" default 0 range 0 5 ---help--- Specifies the channel mode. -endif # !STM32L5_PWM_MULTICHAN +endif # !STM32H5_PWM_MULTICHAN -endif # STM32L5_TIM8_PWM +endif # STM32H5_TIM8_PWM -config STM32L5_TIM15_PWM +config STM32H5_TIM15_PWM bool "TIM15 PWM" default n - depends on STM32L5_TIM15 + depends on STM32H5_TIM15 select PWM ---help--- Reserve timer 15 for use by PWM Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM15 + to generate modulated outputs for such things as motor control. If STM32H5_TIM15 is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. -if STM32L5_TIM15_PWM +if STM32H5_TIM15_PWM -if STM32L5_PWM_MULTICHAN +if STM32H5_PWM_MULTICHAN -config STM32L5_TIM15_CHANNEL1 +config STM32H5_TIM15_CHANNEL1 bool "TIM15 Channel 1" default n ---help--- Enables channel 1. -if STM32L5_TIM15_CHANNEL1 +if STM32H5_TIM15_CHANNEL1 -config STM32L5_TIM15_CH1MODE +config STM32H5_TIM15_CH1MODE int "TIM15 Channel 1 Mode" default 0 range 0 3 ---help--- Specifies the channel mode. -config STM32L5_TIM15_CH1OUT +config STM32H5_TIM15_CH1OUT bool "TIM15 Channel 1 Output" default n ---help--- Enables channel 1 output. -config STM32L5_TIM15_CH1NOUT +config STM32H5_TIM15_CH1NOUT bool "TIM15 Channel 1 Complementary Output" default n - depends on STM32L5_TIM15_CH1OUT + depends on STM32H5_TIM15_CH1OUT ---help--- Enables channel 1 complementary output. -endif # STM32L5_TIM15_CHANNEL1 +endif # STM32H5_TIM15_CHANNEL1 -config STM32L5_TIM15_CHANNEL2 +config STM32H5_TIM15_CHANNEL2 bool "TIM15 Channel 2" default n ---help--- Enables channel 2. -if STM32L5_TIM15_CHANNEL2 +if STM32H5_TIM15_CHANNEL2 -config STM32L5_TIM15_CH2MODE +config STM32H5_TIM15_CH2MODE int "TIM15 Channel 2 Mode" default 0 range 0 3 ---help--- Specifies the channel mode. -config STM32L5_TIM15_CH2OUT +config STM32H5_TIM15_CH2OUT bool "TIM15 Channel 2 Output" default n ---help--- Enables channel 2 output. -endif # STM32L5_TIM15_CHANNEL2 +endif # STM32H5_TIM15_CHANNEL2 -endif # STM32L5_PWM_MULTICHAN +endif # STM32H5_PWM_MULTICHAN -if !STM32L5_PWM_MULTICHAN +if !STM32H5_PWM_MULTICHAN -config STM32L5_TIM15_CHANNEL +config STM32H5_TIM15_CHANNEL int "TIM15 PWM Output Channel" default 1 range 1 2 @@ -1565,69 +1565,69 @@ config STM32L5_TIM15_CHANNEL If TIM15 is enabled for PWM usage, you also need specifies the timer output channel {1,2} -config STM32L5_TIM15_CHMODE +config STM32H5_TIM15_CHMODE int "TIM15 Channel Mode" default 0 range 0 3 ---help--- Specifies the channel mode. -endif # !STM32L5_PWM_MULTICHAN +endif # !STM32H5_PWM_MULTICHAN -endif # STM32L5_TIM15_PWM +endif # STM32H5_TIM15_PWM -config STM32L5_TIM16_PWM +config STM32H5_TIM16_PWM bool "TIM16 PWM" default n - depends on STM32L5_TIM16 + depends on STM32H5_TIM16 select PWM ---help--- Reserve timer 16 for use by PWM Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM16 + to generate modulated outputs for such things as motor control. If STM32H5_TIM16 is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. -if STM32L5_TIM16_PWM +if STM32H5_TIM16_PWM -if STM32L5_PWM_MULTICHAN +if STM32H5_PWM_MULTICHAN -config STM32L5_TIM16_CHANNEL1 +config STM32H5_TIM16_CHANNEL1 bool "TIM16 Channel 1" default n ---help--- Enables channel 1. -if STM32L5_TIM16_CHANNEL1 +if STM32H5_TIM16_CHANNEL1 -config STM32L5_TIM16_CH1MODE +config STM32H5_TIM16_CH1MODE int "TIM16 Channel 1 Mode" default 0 range 0 1 ---help--- Specifies the channel mode. -config STM32L5_TIM16_CH1OUT +config STM32H5_TIM16_CH1OUT bool "TIM16 Channel 1 Output" default n ---help--- Enables channel 1 output. -config STM32L5_TIM16_CH1NOUT +config STM32H5_TIM16_CH1NOUT bool "TIM16 Channel 1 Complementary Output" default n - depends on STM32L5_TIM16_CH1OUT + depends on STM32H5_TIM16_CH1OUT ---help--- Enables channel 1 complementary output. -endif # STM32L5_TIM16_CHANNEL1 +endif # STM32H5_TIM16_CHANNEL1 -endif # STM32L5_PWM_MULTICHAN +endif # STM32H5_PWM_MULTICHAN -if !STM32L5_PWM_MULTICHAN +if !STM32H5_PWM_MULTICHAN -config STM32L5_TIM16_CHANNEL +config STM32H5_TIM16_CHANNEL int "TIM16 PWM Output Channel" default 1 range 1 1 @@ -1635,69 +1635,69 @@ config STM32L5_TIM16_CHANNEL If TIM16 is enabled for PWM usage, you also need specifies the timer output channel {1} -config STM32L5_TIM16_CHMODE +config STM32H5_TIM16_CHMODE int "TIM16 Channel Mode" default 0 range 0 1 ---help--- Specifies the channel mode. -endif # !STM32L5_PWM_MULTICHAN +endif # !STM32H5_PWM_MULTICHAN -endif # STM32L5_TIM16_PWM +endif # STM32H5_TIM16_PWM -config STM32L5_TIM17_PWM +config STM32H5_TIM17_PWM bool "TIM17 PWM" default n - depends on STM32L5_TIM17 + depends on STM32H5_TIM17 select PWM ---help--- Reserve timer 17 for use by PWM Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM17 + to generate modulated outputs for such things as motor control. If STM32H5_TIM17 is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. -if STM32L5_TIM17_PWM +if STM32H5_TIM17_PWM -if STM32L5_PWM_MULTICHAN +if STM32H5_PWM_MULTICHAN -config STM32L5_TIM17_CHANNEL1 +config STM32H5_TIM17_CHANNEL1 bool "TIM17 Channel 1" default n ---help--- Enables channel 1. -if STM32L5_TIM17_CHANNEL1 +if STM32H5_TIM17_CHANNEL1 -config STM32L5_TIM17_CH1MODE +config STM32H5_TIM17_CH1MODE int "TIM17 Channel 1 Mode" default 0 range 0 1 ---help--- Specifies the channel mode. -config STM32L5_TIM17_CH1OUT +config STM32H5_TIM17_CH1OUT bool "TIM17 Channel 1 Output" default n ---help--- Enables channel 1 output. -config STM32L5_TIM17_CH1NOUT +config STM32H5_TIM17_CH1NOUT bool "TIM17 Channel 1 Complementary Output" default n - depends on STM32L5_TIM17_CH1OUT + depends on STM32H5_TIM17_CH1OUT ---help--- Enables channel 1 complementary output. -endif # STM32L5_TIM17_CHANNEL1 +endif # STM32H5_TIM17_CHANNEL1 -endif # STM32L5_PWM_MULTICHAN +endif # STM32H5_PWM_MULTICHAN -if !STM32L5_PWM_MULTICHAN +if !STM32H5_PWM_MULTICHAN -config STM32L5_TIM17_CHANNEL +config STM32H5_TIM17_CHANNEL int "TIM17 PWM Output Channel" default 1 range 1 1 @@ -1705,34 +1705,34 @@ config STM32L5_TIM17_CHANNEL If TIM17 is enabled for PWM usage, you also need specifies the timer output channel {1} -config STM32L5_TIM17_CHMODE +config STM32H5_TIM17_CHMODE int "TIM17 Channel Mode" default 0 range 0 1 ---help--- Specifies the channel mode. -endif # !STM32L5_PWM_MULTICHAN +endif # !STM32H5_PWM_MULTICHAN -endif # STM32L5_TIM17_PWM +endif # STM32H5_TIM17_PWM -config STM32L5_PWM_MULTICHAN +config STM32H5_PWM_MULTICHAN bool "PWM Multiple Output Channels" default n - depends on STM32L5_TIM1_PWM || STM32L5_TIM2_PWM || STM32L5_TIM3_PWM || STM32L5_TIM4_PWM || STM32L5_TIM5_PWM || STM32L5_TIM8_PWM || STM32L5_TIM15_PWM || STM32L5_TIM16_PWM || STM32L5_TIM17_PWM + depends on STM32H5_TIM1_PWM || STM32H5_TIM2_PWM || STM32H5_TIM3_PWM || STM32H5_TIM4_PWM || STM32H5_TIM5_PWM || STM32H5_TIM8_PWM || STM32H5_TIM15_PWM || STM32H5_TIM16_PWM || STM32H5_TIM17_PWM select ARCH_HAVE_PWM_MULTICHAN ---help--- Specifies that the PWM driver supports multiple output channels per timer. -config STM32L5_TIM1_ADC +config STM32H5_TIM1_ADC bool "TIM1 ADC" default n - depends on STM32L5_TIM1 && STM32L5_ADC + depends on STM32H5_TIM1 && STM32H5_ADC ---help--- Reserve timer 1 for use by ADC - Timer devices may be used for different purposes. If STM32L5_TIM1 is + Timer devices may be used for different purposes. If STM32H5_TIM1 is defined then the following may also be defined to indicate that the timer is intended to be used for ADC conversion. Note that ADC usage requires two definition: Not only do you have to assign the timer @@ -1741,40 +1741,40 @@ config STM32L5_TIM1_ADC choice prompt "Select TIM1 ADC channel" - default STM32L5_TIM1_ADC1 - depends on STM32L5_TIM1_ADC + default STM32H5_TIM1_ADC1 + depends on STM32H5_TIM1_ADC -config STM32L5_TIM1_ADC1 +config STM32H5_TIM1_ADC1 bool "TIM1 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER + depends on STM32H5_ADC1 + select STM32H5_HAVE_ADC1_TIMER ---help--- Reserve TIM1 to trigger ADC1 -config STM32L5_TIM1_ADC2 +config STM32H5_TIM1_ADC2 bool "TIM1 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER + depends on STM32H5_ADC2 + select STM32H5_HAVE_ADC2_TIMER ---help--- Reserve TIM1 to trigger ADC2 -config STM32L5_TIM1_ADC3 +config STM32H5_TIM1_ADC3 bool "TIM1 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER + depends on STM32H5_ADC3 + select STM32H5_HAVE_ADC3_TIMER ---help--- Reserve TIM1 to trigger ADC3 endchoice -config STM32L5_TIM2_ADC +config STM32H5_TIM2_ADC bool "TIM2 ADC" default n - depends on STM32L5_TIM2 && STM32L5_ADC + depends on STM32H5_TIM2 && STM32H5_ADC ---help--- Reserve timer 2 for use by ADC - Timer devices may be used for different purposes. If STM32L5_TIM2 is + Timer devices may be used for different purposes. If STM32H5_TIM2 is defined then the following may also be defined to indicate that the timer is intended to be used for ADC conversion. Note that ADC usage requires two definition: Not only do you have to assign the timer @@ -1783,40 +1783,40 @@ config STM32L5_TIM2_ADC choice prompt "Select TIM2 ADC channel" - default STM32L5_TIM2_ADC1 - depends on STM32L5_TIM2_ADC + default STM32H5_TIM2_ADC1 + depends on STM32H5_TIM2_ADC -config STM32L5_TIM2_ADC1 +config STM32H5_TIM2_ADC1 bool "TIM2 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER + depends on STM32H5_ADC1 + select STM32H5_HAVE_ADC1_TIMER ---help--- Reserve TIM2 to trigger ADC1 -config STM32L5_TIM2_ADC2 +config STM32H5_TIM2_ADC2 bool "TIM2 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER + depends on STM32H5_ADC2 + select STM32H5_HAVE_ADC2_TIMER ---help--- Reserve TIM2 to trigger ADC2 -config STM32L5_TIM2_ADC3 +config STM32H5_TIM2_ADC3 bool "TIM2 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER + depends on STM32H5_ADC3 + select STM32H5_HAVE_ADC3_TIMER ---help--- Reserve TIM2 to trigger ADC3 endchoice -config STM32L5_TIM3_ADC +config STM32H5_TIM3_ADC bool "TIM3 ADC" default n - depends on STM32L5_TIM3 && STM32L5_ADC + depends on STM32H5_TIM3 && STM32H5_ADC ---help--- Reserve timer 3 for use by ADC - Timer devices may be used for different purposes. If STM32L5_TIM3 is + Timer devices may be used for different purposes. If STM32H5_TIM3 is defined then the following may also be defined to indicate that the timer is intended to be used for ADC conversion. Note that ADC usage requires two definition: Not only do you have to assign the timer @@ -1825,40 +1825,40 @@ config STM32L5_TIM3_ADC choice prompt "Select TIM3 ADC channel" - default STM32L5_TIM3_ADC1 - depends on STM32L5_TIM3_ADC + default STM32H5_TIM3_ADC1 + depends on STM32H5_TIM3_ADC -config STM32L5_TIM3_ADC1 +config STM32H5_TIM3_ADC1 bool "TIM3 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER + depends on STM32H5_ADC1 + select STM32H5_HAVE_ADC1_TIMER ---help--- Reserve TIM3 to trigger ADC1 -config STM32L5_TIM3_ADC2 +config STM32H5_TIM3_ADC2 bool "TIM3 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER + depends on STM32H5_ADC2 + select STM32H5_HAVE_ADC2_TIMER ---help--- Reserve TIM3 to trigger ADC2 -config STM32L5_TIM3_ADC3 +config STM32H5_TIM3_ADC3 bool "TIM3 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER + depends on STM32H5_ADC3 + select STM32H5_HAVE_ADC3_TIMER ---help--- Reserve TIM3 to trigger ADC3 endchoice -config STM32L5_TIM4_ADC +config STM32H5_TIM4_ADC bool "TIM4 ADC" default n - depends on STM32L5_TIM4 && STM32L5_ADC + depends on STM32H5_TIM4 && STM32H5_ADC ---help--- Reserve timer 4 for use by ADC - Timer devices may be used for different purposes. If STM32L5_TIM4 is + Timer devices may be used for different purposes. If STM32H5_TIM4 is defined then the following may also be defined to indicate that the timer is intended to be used for ADC conversion. Note that ADC usage requires two definition: Not only do you have to assign the timer @@ -1867,40 +1867,40 @@ config STM32L5_TIM4_ADC choice prompt "Select TIM4 ADC channel" - default STM32L5_TIM4_ADC1 - depends on STM32L5_TIM4_ADC + default STM32H5_TIM4_ADC1 + depends on STM32H5_TIM4_ADC -config STM32L5_TIM4_ADC1 +config STM32H5_TIM4_ADC1 bool "TIM4 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER + depends on STM32H5_ADC1 + select STM32H5_HAVE_ADC1_TIMER ---help--- Reserve TIM4 to trigger ADC1 -config STM32L5_TIM4_ADC2 +config STM32H5_TIM4_ADC2 bool "TIM4 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER + depends on STM32H5_ADC2 + select STM32H5_HAVE_ADC2_TIMER ---help--- Reserve TIM4 to trigger ADC2 -config STM32L5_TIM4_ADC3 +config STM32H5_TIM4_ADC3 bool "TIM4 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER + depends on STM32H5_ADC3 + select STM32H5_HAVE_ADC3_TIMER ---help--- Reserve TIM4 to trigger ADC3 endchoice -config STM32L5_TIM6_ADC +config STM32H5_TIM6_ADC bool "TIM6 ADC" default n - depends on STM32L5_TIM6 && STM32L5_ADC + depends on STM32H5_TIM6 && STM32H5_ADC ---help--- Reserve timer 6 for use by ADC - Timer devices may be used for different purposes. If STM32L5_TIM6 is + Timer devices may be used for different purposes. If STM32H5_TIM6 is defined then the following may also be defined to indicate that the timer is intended to be used for ADC conversion. Note that ADC usage requires two definition: Not only do you have to assign the timer @@ -1909,40 +1909,40 @@ config STM32L5_TIM6_ADC choice prompt "Select TIM6 ADC channel" - default STM32L5_TIM6_ADC1 - depends on STM32L5_TIM6_ADC + default STM32H5_TIM6_ADC1 + depends on STM32H5_TIM6_ADC -config STM32L5_TIM6_ADC1 +config STM32H5_TIM6_ADC1 bool "TIM6 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER + depends on STM32H5_ADC1 + select STM32H5_HAVE_ADC1_TIMER ---help--- Reserve TIM6 to trigger ADC1 -config STM32L5_TIM6_ADC2 +config STM32H5_TIM6_ADC2 bool "TIM6 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER + depends on STM32H5_ADC2 + select STM32H5_HAVE_ADC2_TIMER ---help--- Reserve TIM6 to trigger ADC2 -config STM32L5_TIM6_ADC3 +config STM32H5_TIM6_ADC3 bool "TIM6 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER + depends on STM32H5_ADC3 + select STM32H5_HAVE_ADC3_TIMER ---help--- Reserve TIM6 to trigger ADC3 endchoice -config STM32L5_TIM8_ADC +config STM32H5_TIM8_ADC bool "TIM8 ADC" default n - depends on STM32L5_TIM8 && STM32L5_ADC + depends on STM32H5_TIM8 && STM32H5_ADC ---help--- Reserve timer 8 for use by ADC - Timer devices may be used for different purposes. If STM32L5_TIM8 is + Timer devices may be used for different purposes. If STM32H5_TIM8 is defined then the following may also be defined to indicate that the timer is intended to be used for ADC conversion. Note that ADC usage requires two definition: Not only do you have to assign the timer @@ -1951,40 +1951,40 @@ config STM32L5_TIM8_ADC choice prompt "Select TIM8 ADC channel" - default STM32L5_TIM8_ADC1 - depends on STM32L5_TIM8_ADC + default STM32H5_TIM8_ADC1 + depends on STM32H5_TIM8_ADC -config STM32L5_TIM8_ADC1 +config STM32H5_TIM8_ADC1 bool "TIM8 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER + depends on STM32H5_ADC1 + select STM32H5_HAVE_ADC1_TIMER ---help--- Reserve TIM8 to trigger ADC1 -config STM32L5_TIM8_ADC2 +config STM32H5_TIM8_ADC2 bool "TIM8 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER + depends on STM32H5_ADC2 + select STM32H5_HAVE_ADC2_TIMER ---help--- Reserve TIM8 to trigger ADC2 -config STM32L5_TIM8_ADC3 +config STM32H5_TIM8_ADC3 bool "TIM8 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER + depends on STM32H5_ADC3 + select STM32H5_HAVE_ADC3_TIMER ---help--- Reserve TIM8 to trigger ADC3 endchoice -config STM32L5_TIM15_ADC +config STM32H5_TIM15_ADC bool "TIM15 ADC" default n - depends on STM32L5_TIM15 && STM32L5_ADC + depends on STM32H5_TIM15 && STM32H5_ADC ---help--- Reserve timer 15 for use by ADC - Timer devices may be used for different purposes. If STM32L5_TIM15 is + Timer devices may be used for different purposes. If STM32H5_TIM15 is defined then the following may also be defined to indicate that the timer is intended to be used for ADC conversion. Note that ADC usage requires two definition: Not only do you have to assign the timer @@ -1993,94 +1993,94 @@ config STM32L5_TIM15_ADC choice prompt "Select TIM15 ADC channel" - default STM32L5_TIM15_ADC1 - depends on STM32L5_TIM15_ADC + default STM32H5_TIM15_ADC1 + depends on STM32H5_TIM15_ADC -config STM32L5_TIM15_ADC1 +config STM32H5_TIM15_ADC1 bool "TIM15 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER + depends on STM32H5_ADC1 + select STM32H5_HAVE_ADC1_TIMER ---help--- Reserve TIM15 to trigger ADC1 -config STM32L5_TIM15_ADC2 +config STM32H5_TIM15_ADC2 bool "TIM15 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER + depends on STM32H5_ADC2 + select STM32H5_HAVE_ADC2_TIMER ---help--- Reserve TIM15 to trigger ADC2 -config STM32L5_TIM15_ADC3 +config STM32H5_TIM15_ADC3 bool "TIM15 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER + depends on STM32H5_ADC3 + select STM32H5_HAVE_ADC3_TIMER ---help--- Reserve TIM15 to trigger ADC3 endchoice -config STM32L5_HAVE_ADC1_TIMER +config STM32H5_HAVE_ADC1_TIMER bool -config STM32L5_HAVE_ADC2_TIMER +config STM32H5_HAVE_ADC2_TIMER bool -config STM32L5_HAVE_ADC3_TIMER +config STM32H5_HAVE_ADC3_TIMER bool -config STM32L5_ADC1_SAMPLE_FREQUENCY +config STM32H5_ADC1_SAMPLE_FREQUENCY int "ADC1 Sampling Frequency" default 100 - depends on STM32L5_HAVE_ADC1_TIMER + depends on STM32H5_HAVE_ADC1_TIMER ---help--- ADC1 sampling frequency. Default: 100Hz -config STM32L5_ADC1_TIMTRIG +config STM32H5_ADC1_TIMTRIG int "ADC1 Timer Trigger" default 0 range 0 4 - depends on STM32L5_HAVE_ADC1_TIMER + depends on STM32H5_HAVE_ADC1_TIMER ---help--- Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO -config STM32L5_ADC2_SAMPLE_FREQUENCY +config STM32H5_ADC2_SAMPLE_FREQUENCY int "ADC2 Sampling Frequency" default 100 - depends on STM32L5_HAVE_ADC2_TIMER + depends on STM32H5_HAVE_ADC2_TIMER ---help--- ADC2 sampling frequency. Default: 100Hz -config STM32L5_ADC2_TIMTRIG +config STM32H5_ADC2_TIMTRIG int "ADC2 Timer Trigger" default 0 range 0 4 - depends on STM32L5_HAVE_ADC2_TIMER + depends on STM32H5_HAVE_ADC2_TIMER ---help--- Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO -config STM32L5_ADC3_SAMPLE_FREQUENCY +config STM32H5_ADC3_SAMPLE_FREQUENCY int "ADC3 Sampling Frequency" default 100 - depends on STM32L5_HAVE_ADC3_TIMER + depends on STM32H5_HAVE_ADC3_TIMER ---help--- ADC3 sampling frequency. Default: 100Hz -config STM32L5_ADC3_TIMTRIG +config STM32H5_ADC3_TIMTRIG int "ADC3 Timer Trigger" default 0 range 0 4 - depends on STM32L5_HAVE_ADC3_TIMER + depends on STM32H5_HAVE_ADC3_TIMER ---help--- Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO -config STM32L5_TIM1_DAC +config STM32H5_TIM1_DAC bool "TIM1 DAC" default n - depends on STM32L5_TIM1 && STM32L5_DAC + depends on STM32H5_TIM1 && STM32H5_DAC ---help--- Reserve timer 1 for use by DAC - Timer devices may be used for different purposes. If STM32L5_TIM1 is + Timer devices may be used for different purposes. If STM32H5_TIM1 is defined then the following may also be defined to indicate that the timer is intended to be used for DAC conversion. Note that DAC usage requires two definition: Not only do you have to assign the timer @@ -2089,29 +2089,29 @@ config STM32L5_TIM1_DAC choice prompt "Select TIM1 DAC channel" - default STM32L5_TIM1_DAC1 - depends on STM32L5_TIM1_DAC + default STM32H5_TIM1_DAC1 + depends on STM32H5_TIM1_DAC -config STM32L5_TIM1_DAC1 +config STM32H5_TIM1_DAC1 bool "TIM1 DAC channel 1" ---help--- Reserve TIM1 to trigger DAC1 -config STM32L5_TIM1_DAC2 +config STM32H5_TIM1_DAC2 bool "TIM1 DAC channel 2" ---help--- Reserve TIM1 to trigger DAC2 endchoice -config STM32L5_TIM2_DAC +config STM32H5_TIM2_DAC bool "TIM2 DAC" default n - depends on STM32L5_TIM2 && STM32L5_DAC + depends on STM32H5_TIM2 && STM32H5_DAC ---help--- Reserve timer 2 for use by DAC - Timer devices may be used for different purposes. If STM32L5_TIM2 is + Timer devices may be used for different purposes. If STM32H5_TIM2 is defined then the following may also be defined to indicate that the timer is intended to be used for DAC conversion. Note that DAC usage requires two definition: Not only do you have to assign the timer @@ -2120,29 +2120,29 @@ config STM32L5_TIM2_DAC choice prompt "Select TIM2 DAC channel" - default STM32L5_TIM2_DAC1 - depends on STM32L5_TIM2_DAC + default STM32H5_TIM2_DAC1 + depends on STM32H5_TIM2_DAC -config STM32L5_TIM2_DAC1 +config STM32H5_TIM2_DAC1 bool "TIM2 DAC channel 1" ---help--- Reserve TIM2 to trigger DAC1 -config STM32L5_TIM2_DAC2 +config STM32H5_TIM2_DAC2 bool "TIM2 DAC channel 2" ---help--- Reserve TIM2 to trigger DAC2 endchoice -config STM32L5_TIM3_DAC +config STM32H5_TIM3_DAC bool "TIM3 DAC" default n - depends on STM32L5_TIM3 && STM32L5_DAC + depends on STM32H5_TIM3 && STM32H5_DAC ---help--- Reserve timer 3 for use by DAC - Timer devices may be used for different purposes. If STM32L5_TIM3 is + Timer devices may be used for different purposes. If STM32H5_TIM3 is defined then the following may also be defined to indicate that the timer is intended to be used for DAC conversion. Note that DAC usage requires two definition: Not only do you have to assign the timer @@ -2151,29 +2151,29 @@ config STM32L5_TIM3_DAC choice prompt "Select TIM3 DAC channel" - default STM32L5_TIM3_DAC1 - depends on STM32L5_TIM3_DAC + default STM32H5_TIM3_DAC1 + depends on STM32H5_TIM3_DAC -config STM32L5_TIM3_DAC1 +config STM32H5_TIM3_DAC1 bool "TIM3 DAC channel 1" ---help--- Reserve TIM3 to trigger DAC1 -config STM32L5_TIM3_DAC2 +config STM32H5_TIM3_DAC2 bool "TIM3 DAC channel 2" ---help--- Reserve TIM3 to trigger DAC2 endchoice -config STM32L5_TIM4_DAC +config STM32H5_TIM4_DAC bool "TIM4 DAC" default n - depends on STM32L5_TIM4 && STM32L5_DAC + depends on STM32H5_TIM4 && STM32H5_DAC ---help--- Reserve timer 4 for use by DAC - Timer devices may be used for different purposes. If STM32L5_TIM4 is + Timer devices may be used for different purposes. If STM32H5_TIM4 is defined then the following may also be defined to indicate that the timer is intended to be used for DAC conversion. Note that DAC usage requires two definition: Not only do you have to assign the timer @@ -2182,29 +2182,29 @@ config STM32L5_TIM4_DAC choice prompt "Select TIM4 DAC channel" - default STM32L5_TIM4_DAC1 - depends on STM32L5_TIM4_DAC + default STM32H5_TIM4_DAC1 + depends on STM32H5_TIM4_DAC -config STM32L5_TIM4_DAC1 +config STM32H5_TIM4_DAC1 bool "TIM4 DAC channel 1" ---help--- Reserve TIM4 to trigger DAC1 -config STM32L5_TIM4_DAC2 +config STM32H5_TIM4_DAC2 bool "TIM4 DAC channel 2" ---help--- Reserve TIM4 to trigger DAC2 endchoice -config STM32L5_TIM5_DAC +config STM32H5_TIM5_DAC bool "TIM5 DAC" default n - depends on STM32L5_TIM5 && STM32L5_DAC + depends on STM32H5_TIM5 && STM32H5_DAC ---help--- Reserve timer 5 for use by DAC - Timer devices may be used for different purposes. If STM32L5_TIM5 is + Timer devices may be used for different purposes. If STM32H5_TIM5 is defined then the following may also be defined to indicate that the timer is intended to be used for DAC conversion. Note that DAC usage requires two definition: Not only do you have to assign the timer @@ -2213,29 +2213,29 @@ config STM32L5_TIM5_DAC choice prompt "Select TIM5 DAC channel" - default STM32L5_TIM5_DAC1 - depends on STM32L5_TIM5_DAC + default STM32H5_TIM5_DAC1 + depends on STM32H5_TIM5_DAC -config STM32L5_TIM5_DAC1 +config STM32H5_TIM5_DAC1 bool "TIM5 DAC channel 1" ---help--- Reserve TIM5 to trigger DAC1 -config STM32L5_TIM5_DAC2 +config STM32H5_TIM5_DAC2 bool "TIM5 DAC channel 2" ---help--- Reserve TIM5 to trigger DAC2 endchoice -config STM32L5_TIM6_DAC +config STM32H5_TIM6_DAC bool "TIM6 DAC" default n - depends on STM32L5_TIM6 && STM32L5_DAC + depends on STM32H5_TIM6 && STM32H5_DAC ---help--- Reserve timer 6 for use by DAC - Timer devices may be used for different purposes. If STM32L5_TIM6 is + Timer devices may be used for different purposes. If STM32H5_TIM6 is defined then the following may also be defined to indicate that the timer is intended to be used for DAC conversion. Note that DAC usage requires two definition: Not only do you have to assign the timer @@ -2244,29 +2244,29 @@ config STM32L5_TIM6_DAC choice prompt "Select TIM6 DAC channel" - default STM32L5_TIM6_DAC1 - depends on STM32L5_TIM6_DAC + default STM32H5_TIM6_DAC1 + depends on STM32H5_TIM6_DAC -config STM32L5_TIM6_DAC1 +config STM32H5_TIM6_DAC1 bool "TIM6 DAC channel 1" ---help--- Reserve TIM6 to trigger DAC1 -config STM32L5_TIM6_DAC2 +config STM32H5_TIM6_DAC2 bool "TIM6 DAC channel 2" ---help--- Reserve TIM6 to trigger DAC2 endchoice -config STM32L5_TIM7_DAC +config STM32H5_TIM7_DAC bool "TIM7 DAC" default n - depends on STM32L5_TIM7 && STM32L5_DAC + depends on STM32H5_TIM7 && STM32H5_DAC ---help--- Reserve timer 7 for use by DAC - Timer devices may be used for different purposes. If STM32L5_TIM7 is + Timer devices may be used for different purposes. If STM32H5_TIM7 is defined then the following may also be defined to indicate that the timer is intended to be used for DAC conversion. Note that DAC usage requires two definition: Not only do you have to assign the timer @@ -2275,29 +2275,29 @@ config STM32L5_TIM7_DAC choice prompt "Select TIM7 DAC channel" - default STM32L5_TIM7_DAC1 - depends on STM32L5_TIM7_DAC + default STM32H5_TIM7_DAC1 + depends on STM32H5_TIM7_DAC -config STM32L5_TIM7_DAC1 +config STM32H5_TIM7_DAC1 bool "TIM7 DAC channel 1" ---help--- Reserve TIM7 to trigger DAC1 -config STM32L5_TIM7_DAC2 +config STM32H5_TIM7_DAC2 bool "TIM7 DAC channel 2" ---help--- Reserve TIM7 to trigger DAC2 endchoice -config STM32L5_TIM8_DAC +config STM32H5_TIM8_DAC bool "TIM8 DAC" default n - depends on STM32L5_TIM8 && STM32L5_DAC + depends on STM32H5_TIM8 && STM32H5_DAC ---help--- Reserve timer 8 for use by DAC - Timer devices may be used for different purposes. If STM32L5_TIM8 is + Timer devices may be used for different purposes. If STM32H5_TIM8 is defined then the following may also be defined to indicate that the timer is intended to be used for DAC conversion. Note that DAC usage requires two definition: Not only do you have to assign the timer @@ -2306,75 +2306,75 @@ config STM32L5_TIM8_DAC choice prompt "Select TIM8 DAC channel" - default STM32L5_TIM8_DAC1 - depends on STM32L5_TIM8_DAC + default STM32H5_TIM8_DAC1 + depends on STM32H5_TIM8_DAC -config STM32L5_TIM8_DAC1 +config STM32H5_TIM8_DAC1 bool "TIM8 DAC channel 1" ---help--- Reserve TIM8 to trigger DAC1 -config STM32L5_TIM8_DAC2 +config STM32H5_TIM8_DAC2 bool "TIM8 DAC channel 2" ---help--- Reserve TIM8 to trigger DAC2 endchoice -config STM32L5_TIM1_CAP +config STM32H5_TIM1_CAP bool "TIM1 Capture" default n - depends on STM32L5_HAVE_TIM1 + depends on STM32H5_HAVE_TIM1 ---help--- Reserve timer 1 for use by Capture Timer devices may be used for different purposes. One special purpose is to capture input. -config STM32L5_TIM2_CAP +config STM32H5_TIM2_CAP bool "TIM2 Capture" default n - depends on STM32L5_HAVE_TIM2 + depends on STM32H5_HAVE_TIM2 ---help--- Reserve timer 2 for use by Capture Timer devices may be used for different purposes. One special purpose is to capture input. -config STM32L5_TIM3_CAP +config STM32H5_TIM3_CAP bool "TIM3 Capture" default n - depends on STM32L5_HAVE_TIM3 + depends on STM32H5_HAVE_TIM3 ---help--- Reserve timer 3 for use by Capture Timer devices may be used for different purposes. One special purpose is to capture input. -config STM32L5_TIM4_CAP +config STM32H5_TIM4_CAP bool "TIM4 Capture" default n - depends on STM32L5_HAVE_TIM4 + depends on STM32H5_HAVE_TIM4 ---help--- Reserve timer 4 for use by Capture Timer devices may be used for different purposes. One special purpose is to capture input. -config STM32L5_TIM5_CAP +config STM32H5_TIM5_CAP bool "TIM5 Capture" default n - depends on STM32L5_HAVE_TIM5 + depends on STM32H5_HAVE_TIM5 ---help--- Reserve timer 5 for use by Capture Timer devices may be used for different purposes. One special purpose is to capture input. -config STM32L5_TIM8_CAP +config STM32H5_TIM8_CAP bool "TIM8 Capture" default n - depends on STM32L5_HAVE_TIM8 + depends on STM32H5_HAVE_TIM8 ---help--- Reserve timer 8 for use by Capture @@ -2384,52 +2384,52 @@ config STM32L5_TIM8_CAP endmenu # Timer Configuration menu "ADC Configuration" - depends on STM32L5_ADC + depends on STM32H5_ADC -config STM32L5_ADC1_DMA +config STM32H5_ADC1_DMA bool "ADC1 DMA" - depends on STM32L5_ADC1 + depends on STM32H5_ADC1 default n ---help--- If DMA is selected, then the ADC may be configured to support DMA transfer, which is necessary if multiple channels are read or if very high trigger frequencies are used. -config STM32L5_ADC2_DMA +config STM32H5_ADC2_DMA bool "ADC2 DMA" - depends on STM32L5_ADC2 + depends on STM32H5_ADC2 default n ---help--- If DMA is selected, then the ADC may be configured to support DMA transfer, which is necessary if multiple channels are read or if very high trigger frequencies are used. -config STM32L5_ADC3_DMA +config STM32H5_ADC3_DMA bool "ADC3 DMA" - depends on STM32L5_ADC3 + depends on STM32H5_ADC3 default n ---help--- If DMA is selected, then the ADC may be configured to support DMA transfer, which is necessary if multiple channels are read or if very high trigger frequencies are used. -config STM32L5_ADC1_OUTPUT_DFSDM +config STM32H5_ADC1_OUTPUT_DFSDM bool "ADC1 output to DFSDM" - depends on STM32L5_ADC1 && STM32L5_DFSDM1 && (STM32L5_STM32L596XX || STM32L5_STM32L5XR) + depends on STM32H5_ADC1 && STM32H5_DFSDM1 && (STM32H5_STM32H596XX || STM32H5_STM32H5XR) default n ---help--- Route ADC1 output directly to DFSDM parallel inputs. -config STM32L5_ADC2_OUTPUT_DFSDM +config STM32H5_ADC2_OUTPUT_DFSDM bool "ADC2 output to DFSDM" - depends on STM32L5_ADC2 && STM32L5_DFSDM1 && STM32L5_STM32L596XX + depends on STM32H5_ADC2 && STM32H5_DFSDM1 && STM32H5_STM32H596XX default n ---help--- Route ADC2 output directly to DFSDM parallel inputs. -config STM32L5_ADC3_OUTPUT_DFSDM +config STM32H5_ADC3_OUTPUT_DFSDM bool "ADC3 output to DFSDM" - depends on STM32L5_ADC3 && STM32L5_DFSDM1 && STM32L5_STM32L596XX + depends on STM32H5_ADC3 && STM32H5_DFSDM1 && STM32H5_STM32H596XX default n ---help--- Route ADC3 output directly to DFSDM parallel inputs. @@ -2437,11 +2437,11 @@ config STM32L5_ADC3_OUTPUT_DFSDM endmenu menu "DAC Configuration" - depends on STM32L5_DAC + depends on STM32H5_DAC -config STM32L5_DAC1_DMA +config STM32H5_DAC1_DMA bool "DAC1 DMA" - depends on STM32L5_DAC1 + depends on STM32H5_DAC1 default n ---help--- If DMA is selected, then a timer and output frequency must also be @@ -2449,34 +2449,34 @@ config STM32L5_DAC1_DMA supported by an EXTI trigger, but this feature is not currently supported by the driver. -if STM32L5_DAC1_DMA +if STM32H5_DAC1_DMA -config STM32L5_DAC1_TIMER +config STM32H5_DAC1_TIMER int "DAC1 timer" range 2 8 -config STM32L5_DAC1_TIMER_FREQUENCY +config STM32H5_DAC1_TIMER_FREQUENCY int "DAC1 timer frequency" default 100 ---help--- DAC1 output frequency. Default: 100Hz -config STM32L5_DAC1_DMA_BUFFER_SIZE +config STM32H5_DAC1_DMA_BUFFER_SIZE int "DAC1 DMA buffer size" default 1 endif -config STM32L5_DAC1_OUTPUT_ADC +config STM32H5_DAC1_OUTPUT_ADC bool "DAC1 output to ADC" - depends on STM32L5_DAC1 + depends on STM32H5_DAC1 default n ---help--- Route DAC1 output to ADC input instead of external pin. -config STM32L5_DAC2_DMA +config STM32H5_DAC2_DMA bool "DAC2 DMA" - depends on STM32L5_DAC2 + depends on STM32H5_DAC2 default n ---help--- If DMA is selected, then a timer and output frequency must also be @@ -2484,28 +2484,28 @@ config STM32L5_DAC2_DMA supported by an EXTI trigger, but this feature is not currently supported by the driver. -if STM32L5_DAC2_DMA +if STM32H5_DAC2_DMA -config STM32L5_DAC2_TIMER +config STM32H5_DAC2_TIMER int "DAC2 timer" default 0 range 2 8 -config STM32L5_DAC2_TIMER_FREQUENCY +config STM32H5_DAC2_TIMER_FREQUENCY int "DAC2 timer frequency" default 100 ---help--- DAC2 output frequency. Default: 100Hz -config STM32L5_DAC2_DMA_BUFFER_SIZE +config STM32H5_DAC2_DMA_BUFFER_SIZE int "DAC2 DMA buffer size" default 1 endif -config STM32L5_DAC2_OUTPUT_ADC +config STM32H5_DAC2_OUTPUT_ADC bool "DAC2 output to ADC" - depends on STM32L5_DAC2 + depends on STM32H5_DAC2 default n ---help--- Route DAC2 output to ADC input instead of external pin. @@ -2513,33 +2513,33 @@ config STM32L5_DAC2_OUTPUT_ADC endmenu menu "DFSDM Configuration" - depends on STM32L5_DFSDM1 + depends on STM32H5_DFSDM1 -config STM32L5_DFSDM1_FLT0 +config STM32H5_DFSDM1_FLT0 bool "DFSDM1 Filter 0" default n - select STM32L5_DFSDM + select STM32H5_DFSDM -config STM32L5_DFSDM1_FLT1 +config STM32H5_DFSDM1_FLT1 bool "DFSDM1 Filter 1" default n - select STM32L5_DFSDM + select STM32H5_DFSDM -config STM32L5_DFSDM1_FLT2 +config STM32H5_DFSDM1_FLT2 bool "DFSDM1 Filter 2" default n - depends on !STM32L5_STM32L5X3 - select STM32L5_DFSDM + depends on !STM32H5_STM32H5X3 + select STM32H5_DFSDM -config STM32L5_DFSDM1_FLT3 +config STM32H5_DFSDM1_FLT3 bool "DFSDM1 Filter 3" default n - depends on !STM32L5_STM32L5X3 - select STM32L5_DFSDM + depends on !STM32H5_STM32H5X3 + select STM32H5_DFSDM -config STM32L5_DFSDM1_DMA +config STM32H5_DFSDM1_DMA bool "DFSDM1 DMA" - depends on STM32L5_DFSDM + depends on STM32H5_DFSDM default n ---help--- If DMA is selected, then the DFSDM may be configured to support @@ -2548,28 +2548,28 @@ config STM32L5_DFSDM1_DMA endmenu -config STM32L5_SERIALDRIVER +config STM32H5_SERIALDRIVER bool -config STM32L5_1WIREDRIVER +config STM32H5_1WIREDRIVER bool menu "[LP]U[S]ART Configuration" - depends on STM32L5_USART + depends on STM32H5_USART choice prompt "LPUART1 Driver Configuration" - default STM32L5_LPUART1_SERIALDRIVER - depends on STM32L5_LPUART1 + default STM32H5_LPUART1_SERIALDRIVER + depends on STM32H5_LPUART1 -config STM32L5_LPUART1_SERIALDRIVER +config STM32H5_LPUART1_SERIALDRIVER bool "Standard serial driver" select LPUART1_SERIALDRIVER - select STM32L5_SERIALDRIVER + select STM32H5_SERIALDRIVER -config STM32L5_LPUART1_1WIREDRIVER +config STM32H5_LPUART1_1WIREDRIVER bool "1-Wire driver" - select STM32L5_1WIREDRIVER + select STM32H5_1WIREDRIVER endchoice # LPUART1 Driver Configuration @@ -2578,7 +2578,7 @@ if LPUART1_SERIALDRIVER config LPUART1_RS485 bool "RS-485 on LPUART1" default n - depends on STM32L5_LPUART1 + depends on STM32H5_LPUART1 ---help--- Enable RS-485 interface on LPUART1. Your board config will have to provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be @@ -2596,7 +2596,7 @@ config LPUART1_RS485_DIR_POLARITY config LPUART1_RXDMA bool "LPUART1 Rx DMA" default n - depends on STM32L5_LPUART1 && (STM32L5_DMA1 || STM32L5_DMA2 || STM32L5_DMAMUX) + depends on STM32H5_LPUART1 && (STM32H5_DMA1 || STM32H5_DMA2 || STM32H5_DMAMUX) ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors @@ -2604,17 +2604,17 @@ endif # LPUART1_SERIALDRIVER choice prompt "USART1 Driver Configuration" - default STM32L5_USART1_SERIALDRIVER - depends on STM32L5_USART1 + default STM32H5_USART1_SERIALDRIVER + depends on STM32H5_USART1 -config STM32L5_USART1_SERIALDRIVER +config STM32H5_USART1_SERIALDRIVER bool "Standard serial driver" select USART1_SERIALDRIVER - select STM32L5_SERIALDRIVER + select STM32H5_SERIALDRIVER -config STM32L5_USART1_1WIREDRIVER +config STM32H5_USART1_1WIREDRIVER bool "1-Wire driver" - select STM32L5_1WIREDRIVER + select STM32H5_1WIREDRIVER endchoice # USART1 Driver Configuration @@ -2623,7 +2623,7 @@ if USART1_SERIALDRIVER config USART1_RS485 bool "RS-485 on USART1" default n - depends on STM32L5_USART1 + depends on STM32H5_USART1 ---help--- Enable RS-485 interface on USART1. Your board config will have to provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be @@ -2641,7 +2641,7 @@ config USART1_RS485_DIR_POLARITY config USART1_RXDMA bool "USART1 Rx DMA" default n - depends on STM32L5_USART1 && (STM32L5_DMA1 || STM32L5_DMA2 || STM32L5_DMAMUX) + depends on STM32H5_USART1 && (STM32H5_DMA1 || STM32H5_DMA2 || STM32H5_DMAMUX) ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors @@ -2649,17 +2649,17 @@ endif # USART1_SERIALDRIVER choice prompt "USART2 Driver Configuration" - default STM32L5_USART2_SERIALDRIVER - depends on STM32L5_USART2 + default STM32H5_USART2_SERIALDRIVER + depends on STM32H5_USART2 -config STM32L5_USART2_SERIALDRIVER +config STM32H5_USART2_SERIALDRIVER bool "Standard serial driver" select USART2_SERIALDRIVER - select STM32L5_SERIALDRIVER + select STM32H5_SERIALDRIVER -config STM32L5_USART2_1WIREDRIVER +config STM32H5_USART2_1WIREDRIVER bool "1-Wire driver" - select STM32L5_1WIREDRIVER + select STM32H5_1WIREDRIVER endchoice # USART2 Driver Configuration @@ -2668,7 +2668,7 @@ if USART2_SERIALDRIVER config USART2_RS485 bool "RS-485 on USART2" default n - depends on STM32L5_USART2 + depends on STM32H5_USART2 ---help--- Enable RS-485 interface on USART2. Your board config will have to provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be @@ -2686,7 +2686,7 @@ config USART2_RS485_DIR_POLARITY config USART2_RXDMA bool "USART2 Rx DMA" default n - depends on STM32L5_USART2 && (STM32L5_DMA1 || STM32L5_DMAMUX) + depends on STM32H5_USART2 && (STM32H5_DMA1 || STM32H5_DMAMUX) ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors @@ -2694,17 +2694,17 @@ endif # USART2_SERIALDRIVER choice prompt "USART3 Driver Configuration" - default STM32L5_USART3_SERIALDRIVER - depends on STM32L5_USART3 + default STM32H5_USART3_SERIALDRIVER + depends on STM32H5_USART3 -config STM32L5_USART3_SERIALDRIVER +config STM32H5_USART3_SERIALDRIVER bool "Standard serial driver" select USART3_SERIALDRIVER - select STM32L5_SERIALDRIVER + select STM32H5_SERIALDRIVER -config STM32L5_USART3_1WIREDRIVER +config STM32H5_USART3_1WIREDRIVER bool "1-Wire driver" - select STM32L5_1WIREDRIVER + select STM32H5_1WIREDRIVER endchoice # USART3 Driver Configuration @@ -2713,7 +2713,7 @@ if USART3_SERIALDRIVER config USART3_RS485 bool "RS-485 on USART3" default n - depends on STM32L5_USART3 + depends on STM32H5_USART3 ---help--- Enable RS-485 interface on USART3. Your board config will have to provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be @@ -2731,7 +2731,7 @@ config USART3_RS485_DIR_POLARITY config USART3_RXDMA bool "USART3 Rx DMA" default n - depends on STM32L5_USART3 && (STM32L5_DMA1 || STM32L5_DMAMUX) + depends on STM32H5_USART3 && (STM32H5_DMA1 || STM32H5_DMAMUX) ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors @@ -2739,17 +2739,17 @@ endif # USART3_SERIALDRIVER choice prompt "UART4 Driver Configuration" - default STM32L5_UART4_SERIALDRIVER - depends on STM32L5_UART4 + default STM32H5_UART4_SERIALDRIVER + depends on STM32H5_UART4 -config STM32L5_UART4_SERIALDRIVER +config STM32H5_UART4_SERIALDRIVER bool "Standard serial driver" select UART4_SERIALDRIVER - select STM32L5_SERIALDRIVER + select STM32H5_SERIALDRIVER -config STM32L5_UART4_1WIREDRIVER +config STM32H5_UART4_1WIREDRIVER bool "1-Wire driver" - select STM32L5_1WIREDRIVER + select STM32H5_1WIREDRIVER endchoice # UART4 Driver Configuration @@ -2758,7 +2758,7 @@ if UART4_SERIALDRIVER config UART4_RS485 bool "RS-485 on UART4" default n - depends on STM32L5_UART4 + depends on STM32H5_UART4 ---help--- Enable RS-485 interface on UART4. Your board config will have to provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be @@ -2776,7 +2776,7 @@ config UART4_RS485_DIR_POLARITY config UART4_RXDMA bool "UART4 Rx DMA" default n - depends on STM32L5_UART4 && (STM32L5_DMA2 || STM32L5_DMAMUX) + depends on STM32H5_UART4 && (STM32H5_DMA2 || STM32H5_DMAMUX) ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors @@ -2784,17 +2784,17 @@ endif # UART4_SERIALDRIVER choice prompt "UART5 Driver Configuration" - default STM32L5_UART5_SERIALDRIVER - depends on STM32L5_UART5 + default STM32H5_UART5_SERIALDRIVER + depends on STM32H5_UART5 -config STM32L5_UART5_SERIALDRIVER +config STM32H5_UART5_SERIALDRIVER bool "Standard serial driver" select UART5_SERIALDRIVER - select STM32L5_SERIALDRIVER + select STM32H5_SERIALDRIVER -config STM32L5_UART5_1WIREDRIVER +config STM32H5_UART5_1WIREDRIVER bool "1-Wire driver" - select STM32L5_1WIREDRIVER + select STM32H5_1WIREDRIVER endchoice # UART5 Driver Configuration @@ -2803,7 +2803,7 @@ if UART5_SERIALDRIVER config UART5_RS485 bool "RS-485 on UART5" default n - depends on STM32L5_UART5 + depends on STM32H5_UART5 ---help--- Enable RS-485 interface on UART5. Your board config will have to provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be @@ -2821,17 +2821,17 @@ config UART5_RS485_DIR_POLARITY config UART5_RXDMA bool "UART5 Rx DMA" default n - depends on STM32L5_UART5 && (STM32L5_DMA2 || STM32L5_DMAMUX) + depends on STM32H5_UART5 && (STM32H5_DMA2 || STM32H5_DMAMUX) ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors endif # UART5_SERIALDRIVER -if STM32L5_SERIALDRIVER +if STM32H5_SERIALDRIVER comment "Serial Driver Configuration" -config STM32L5_SERIAL_RXDMA_BUFFER_SIZE +config STM32H5_SERIAL_RXDMA_BUFFER_SIZE int "Rx DMA buffer size" default 32 depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA @@ -2843,9 +2843,9 @@ config STM32L5_SERIAL_RXDMA_BUFFER_SIZE Value given here will be rounded up to next multiple of 32 bytes. -config STM32L5_SERIAL_DISABLE_REORDERING +config STM32H5_SERIAL_DISABLE_REORDERING bool "Disable reordering of ttySx devices." - depends on STM32L5_USART1 || STM32L5_USART2 || STM32L5_USART3 || STM32L5_UART4 || STM32L5_UART5 + depends on STM32H5_USART1 || STM32H5_USART2 || STM32H5_USART3 || STM32H5_UART4 || STM32H5_UART5 default n ---help--- NuttX per default reorders the serial ports (/dev/ttySx) so that the @@ -2857,9 +2857,9 @@ config STM32L5_SERIAL_DISABLE_REORDERING want the side effect of having all serial port names change when just the console is moved from serial to USB. -config STM32L5_FLOWCONTROL_BROKEN +config STM32H5_FLOWCONTROL_BROKEN bool "Use Software UART RTS flow control" - depends on STM32L5_USART + depends on STM32H5_USART default n ---help--- Enable UART RTS flow control using Software. Because STM @@ -2867,54 +2867,54 @@ config STM32L5_FLOWCONTROL_BROKEN nRTS after every byte received) Enable this setting workaround this issue by using software based management of RTS -config STM32L5_USART_BREAKS +config STM32H5_USART_BREAKS bool "Add TIOxSBRK to support sending Breaks" - depends on STM32L5_USART + depends on STM32H5_USART default n ---help--- Add TIOCxBRK routines to send a line break per the STM32 manual, the break will be a pulse based on the value M. This is not a BSD compatible break. -config STM32L5_SERIALBRK_BSDCOMPAT +config STM32H5_SERIALBRK_BSDCOMPAT bool "Use GPIO To send Break" - depends on STM32L5_USART && STM32L5_USART_BREAKS + depends on STM32H5_USART && STM32H5_USART_BREAKS default n ---help--- Enable using GPIO on the TX pin to send a BSD compatible break: TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32L5 U[S]ARTS have no way to leave the break on + The current STM32H5 U[S]ARTS have no way to leave the break on (TX=LOW) because software starts the break and then the hardware automatically clears the break. This makes it difficult to send a long break. -config STM32L5_USART_SINGLEWIRE +config STM32H5_USART_SINGLEWIRE bool "Single Wire Support" default n - depends on STM32L5_USART + depends on STM32H5_USART ---help--- Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32L5 serial driver. + TIOCSSINGLEWIRE ioctl in the STM32H5 serial driver. -config STM32L5_USART_INVERT +config STM32H5_USART_INVERT bool "Signal Invert Support" default n - depends on STM32L5_USART + depends on STM32H5_USART ---help--- Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32L5 serial driver. + TIOCSINVERT ioctl in the STM32H5 serial driver. -config STM32L5_USART_SWAP +config STM32H5_USART_SWAP bool "Swap RX/TX pins support" default n - depends on STM32L5_USART + depends on STM32H5_USART ---help--- Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32L5 serial driver. + TIOCSSWAP ioctl in the STM32H5 serial driver. if PM -config STM32L5_PM_SERIAL_ACTIVITY +config STM32H5_PM_SERIAL_ACTIVITY int "PM serial activity" default 10 ---help--- @@ -2922,14 +2922,14 @@ config STM32L5_PM_SERIAL_ACTIVITY interrupt. endif -endif # STM32L5_SERIALDRIVER +endif # STM32H5_SERIALDRIVER endmenu # U[S]ART Configuration menu "SPI Configuration" - depends on STM32L5_SPI + depends on STM32H5_SPI -config STM32L5_SPI_INTERRUPTS +config STM32H5_SPI_INTERRUPTS bool "Interrupt driver SPI" default n ---help--- @@ -2937,53 +2937,53 @@ config STM32L5_SPI_INTERRUPTS poll-waiting is recommended if the interrupt rate would be to high in the interrupt driven case. -config STM32L5_SPI_DMA +config STM32H5_SPI_DMA bool "SPI DMA" default n ---help--- - Use DMA to improve SPI transfer performance. Cannot be used with STM32L5_SPI_INTERRUPT. + Use DMA to improve SPI transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT. endmenu menu "I2C Configuration" - depends on STM32L5_I2C + depends on STM32H5_I2C -config STM32L5_I2C_DYNTIMEO +config STM32H5_I2C_DYNTIMEO bool "Use dynamic timeouts" default n - depends on STM32L5_I2C + depends on STM32H5_I2C -config STM32L5_I2C_DYNTIMEO_USECPERBYTE +config STM32H5_I2C_DYNTIMEO_USECPERBYTE int "Timeout Microseconds per Byte" default 500 - depends on STM32L5_I2C_DYNTIMEO + depends on STM32H5_I2C_DYNTIMEO -config STM32L5_I2C_DYNTIMEO_STARTSTOP +config STM32H5_I2C_DYNTIMEO_STARTSTOP int "Timeout for Start/Stop (Milliseconds)" default 1000 - depends on STM32L5_I2C_DYNTIMEO + depends on STM32H5_I2C_DYNTIMEO -config STM32L5_I2CTIMEOSEC +config STM32H5_I2CTIMEOSEC int "Timeout seconds" default 0 - depends on STM32L5_I2C + depends on STM32H5_I2C -config STM32L5_I2CTIMEOMS +config STM32H5_I2CTIMEOMS int "Timeout Milliseconds" default 500 - depends on STM32L5_I2C && !STM32L5_I2C_DYNTIMEO + depends on STM32H5_I2C && !STM32H5_I2C_DYNTIMEO -config STM32L5_I2CTIMEOTICKS +config STM32H5_I2CTIMEOTICKS int "Timeout for Done and Stop (ticks)" default 500 - depends on STM32L5_I2C && !STM32L5_I2C_DYNTIMEO + depends on STM32H5_I2C && !STM32H5_I2C_DYNTIMEO endmenu menu "SD/MMC Configuration" - depends on STM32L5_SDMMC + depends on STM32H5_SDMMC -config STM32L5_SDMMC_XFRDEBUG +config STM32H5_SDMMC_XFRDEBUG bool "SDMMC transfer debug" depends on DEBUG_FS_INFO default n @@ -2995,18 +2995,18 @@ config STM32L5_SDMMC_XFRDEBUG enabled, then DMA register will be collected as well. Requires also DEBUG_FS and CONFIG_DEBUG_INFO. -config STM32L5_SDMMC_DMA +config STM32H5_SDMMC_DMA bool "Support DMA data transfers" default n select SDIO_DMA - depends on STM32L5_DMA + depends on STM32H5_DMA ---help--- Support DMA data transfers. menu "SDMMC1 Configuration" - depends on STM32L5_SDMMC1 + depends on STM32H5_SDMMC1 -config STM32L5_SDMMC1_DMAPRIO +config STM32H5_SDMMC1_DMAPRIO hex "SDMMC1 DMA priority" default 0x00001000 ---help--- @@ -3025,35 +3025,35 @@ endmenu # SDMMC1 Configuration endmenu # SD/MMC Configuration menu "CAN driver configuration" - depends on STM32L5_CAN1 || STM32L5_CAN2 + depends on STM32H5_CAN1 || STM32H5_CAN2 -config STM32L5_CAN1_BAUD +config STM32H5_CAN1_BAUD int "CAN1 BAUD" default 250000 - depends on STM32L5_CAN1 + depends on STM32H5_CAN1 ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32L5_CAN1 is defined. + CAN1 BAUD rate. Required if CONFIG_STM32H5_CAN1 is defined. -config STM32L5_CAN2_BAUD +config STM32H5_CAN2_BAUD int "CAN2 BAUD" default 250000 - depends on STM32L5_CAN2 + depends on STM32H5_CAN2 ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32L5_CAN2 is defined. + CAN2 BAUD rate. Required if CONFIG_STM32H5_CAN2 is defined. -config STM32L5_CAN_TSEG1 +config STM32H5_CAN_TSEG1 int "TSEG1 quanta" default 6 ---help--- The number of CAN time quanta in segment 1. Default: 6 -config STM32L5_CAN_TSEG2 +config STM32H5_CAN_TSEG2 int "TSEG2 quanta" default 7 ---help--- The number of CAN time quanta in segment 2. Default: 7 -config STM32L5_CAN_REGDEBUG +config STM32H5_CAN_REGDEBUG bool "CAN Register level debug" depends on DEBUG_CAN_INFO default n @@ -3065,18 +3065,18 @@ endmenu menu "QEncoder Driver" depends on SENSORS_QENCODER - depends on STM32L5_TIM1 || STM32L5_TIM2 || STM32L5_TIM3 || STM32L5_TIM4 || STM32L5_TIM5 || STM32L5_TIM8 + depends on STM32H5_TIM1 || STM32H5_TIM2 || STM32H5_TIM3 || STM32H5_TIM4 || STM32H5_TIM5 || STM32H5_TIM8 -config STM32L5_TIM1_QE +config STM32H5_TIM1_QE bool "TIM1" default n - depends on STM32L5_TIM1 + depends on STM32H5_TIM1 ---help--- Reserve TIM1 for use by QEncoder. -if STM32L5_TIM1_QE +if STM32H5_TIM1_QE -config STM32L5_TIM1_QEPSC +config STM32H5_TIM1_QEPSC int "TIM1 pulse prescaler" default 1 ---help--- @@ -3085,16 +3085,16 @@ config STM32L5_TIM1_QEPSC endif -config STM32L5_TIM2_QE +config STM32H5_TIM2_QE bool "TIM2" default n - depends on STM32L5_TIM2 + depends on STM32H5_TIM2 ---help--- Reserve TIM2 for use by QEncoder. -if STM32L5_TIM2_QE +if STM32H5_TIM2_QE -config STM32L5_TIM2_QEPSC +config STM32H5_TIM2_QEPSC int "TIM2 pulse prescaler" default 1 ---help--- @@ -3103,16 +3103,16 @@ config STM32L5_TIM2_QEPSC endif -config STM32L5_TIM3_QE +config STM32H5_TIM3_QE bool "TIM3" default n - depends on STM32L5_TIM3 + depends on STM32H5_TIM3 ---help--- Reserve TIM3 for use by QEncoder. -if STM32L5_TIM3_QE +if STM32H5_TIM3_QE -config STM32L5_TIM3_QEPSC +config STM32H5_TIM3_QEPSC int "TIM3 pulse prescaler" default 1 ---help--- @@ -3121,16 +3121,16 @@ config STM32L5_TIM3_QEPSC endif -config STM32L5_TIM4_QE +config STM32H5_TIM4_QE bool "TIM4" default n - depends on STM32L5_TIM4 + depends on STM32H5_TIM4 ---help--- Reserve TIM4 for use by QEncoder. -if STM32L5_TIM4_QE +if STM32H5_TIM4_QE -config STM32L5_TIM4_QEPSC +config STM32H5_TIM4_QEPSC int "TIM4 pulse prescaler" default 1 ---help--- @@ -3139,16 +3139,16 @@ config STM32L5_TIM4_QEPSC endif -config STM32L5_TIM5_QE +config STM32H5_TIM5_QE bool "TIM5" default n - depends on STM32L5_TIM5 + depends on STM32H5_TIM5 ---help--- Reserve TIM5 for use by QEncoder. -if STM32L5_TIM5_QE +if STM32H5_TIM5_QE -config STM32L5_TIM5_QEPSC +config STM32H5_TIM5_QEPSC int "TIM5 pulse prescaler" default 1 ---help--- @@ -3157,16 +3157,16 @@ config STM32L5_TIM5_QEPSC endif -config STM32L5_TIM8_QE +config STM32H5_TIM8_QE bool "TIM8" default n - depends on STM32L5_TIM8 + depends on STM32H5_TIM8 ---help--- Reserve TIM8 for use by QEncoder. -if STM32L5_TIM8_QE +if STM32H5_TIM8_QE -config STM32L5_TIM8_QEPSC +config STM32H5_TIM8_QEPSC int "TIM8 pulse prescaler" default 1 ---help--- @@ -3175,65 +3175,65 @@ config STM32L5_TIM8_QEPSC endif -config STM32L5_QENCODER_FILTER +config STM32H5_QENCODER_FILTER bool "Enable filtering on STM32 QEncoder input" default y choice - depends on STM32L5_QENCODER_FILTER + depends on STM32H5_QENCODER_FILTER prompt "Input channel sampling frequency" - default STM32L5_QENCODER_SAMPLE_FDTS_4 + default STM32H5_QENCODER_SAMPLE_FDTS_4 -config STM32L5_QENCODER_SAMPLE_FDTS +config STM32H5_QENCODER_SAMPLE_FDTS bool "fDTS" -config STM32L5_QENCODER_SAMPLE_CKINT +config STM32H5_QENCODER_SAMPLE_CKINT bool "fCK_INT" -config STM32L5_QENCODER_SAMPLE_FDTS_2 +config STM32H5_QENCODER_SAMPLE_FDTS_2 bool "fDTS/2" -config STM32L5_QENCODER_SAMPLE_FDTS_4 +config STM32H5_QENCODER_SAMPLE_FDTS_4 bool "fDTS/4" -config STM32L5_QENCODER_SAMPLE_FDTS_8 +config STM32H5_QENCODER_SAMPLE_FDTS_8 bool "fDTS/8" -config STM32L5_QENCODER_SAMPLE_FDTS_16 +config STM32H5_QENCODER_SAMPLE_FDTS_16 bool "fDTS/16" -config STM32L5_QENCODER_SAMPLE_FDTS_32 +config STM32H5_QENCODER_SAMPLE_FDTS_32 bool "fDTS/32" endchoice choice - depends on STM32L5_QENCODER_FILTER + depends on STM32H5_QENCODER_FILTER prompt "Input channel event count" - default STM32L5_QENCODER_SAMPLE_EVENT_6 + default STM32H5_QENCODER_SAMPLE_EVENT_6 -config STM32L5_QENCODER_SAMPLE_EVENT_1 - depends on STM32L5_QENCODER_SAMPLE_FDTS +config STM32H5_QENCODER_SAMPLE_EVENT_1 + depends on STM32H5_QENCODER_SAMPLE_FDTS bool "1" -config STM32L5_QENCODER_SAMPLE_EVENT_2 - depends on STM32L5_QENCODER_SAMPLE_CKINT +config STM32H5_QENCODER_SAMPLE_EVENT_2 + depends on STM32H5_QENCODER_SAMPLE_CKINT bool "2" -config STM32L5_QENCODER_SAMPLE_EVENT_4 - depends on STM32L5_QENCODER_SAMPLE_CKINT +config STM32H5_QENCODER_SAMPLE_EVENT_4 + depends on STM32H5_QENCODER_SAMPLE_CKINT bool "4" -config STM32L5_QENCODER_SAMPLE_EVENT_5 - depends on STM32L5_QENCODER_SAMPLE_FDTS_16 || STM32L5_QENCODER_SAMPLE_FDTS_32 +config STM32H5_QENCODER_SAMPLE_EVENT_5 + depends on STM32H5_QENCODER_SAMPLE_FDTS_16 || STM32H5_QENCODER_SAMPLE_FDTS_32 bool "5" -config STM32L5_QENCODER_SAMPLE_EVENT_6 - depends on !STM32L5_QENCODER_SAMPLE_FDTS && !STM32L5_QENCODER_SAMPLE_CKINT +config STM32H5_QENCODER_SAMPLE_EVENT_6 + depends on !STM32H5_QENCODER_SAMPLE_FDTS && !STM32H5_QENCODER_SAMPLE_CKINT bool "6" -config STM32L5_QENCODER_SAMPLE_EVENT_8 - depends on !STM32L5_QENCODER_SAMPLE_FDTS +config STM32H5_QENCODER_SAMPLE_EVENT_8 + depends on !STM32H5_QENCODER_SAMPLE_FDTS bool "8" endchoice @@ -3241,25 +3241,25 @@ endchoice endmenu menu "SAI Configuration" - depends on STM32L5_SAI + depends on STM32H5_SAI choice prompt "Operation mode" - default STM32L5_SAI_DMA + default STM32H5_SAI_DMA ---help--- Select the operation mode the SAI driver should use. -config STM32L5_SAI_POLLING +config STM32H5_SAI_POLLING bool "Polling" ---help--- The SAI registers are polled for events. -config STM32L5_SAI_INTERRUPTS +config STM32H5_SAI_INTERRUPTS bool "Interrupt" ---help--- Select to enable interrupt driven SAI support. -config STM32L5_SAI_DMA +config STM32H5_SAI_DMA bool "DMA" ---help--- Use DMA to improve SAI transfer performance. @@ -3268,40 +3268,40 @@ endchoice # Operation mode choice prompt "SAI1 synchronization enable" - default STM32L5_SAI1_BOTH_ASYNC - depends on STM32L5_SAI1_A && STM32L5_SAI1_B + default STM32H5_SAI1_BOTH_ASYNC + depends on STM32H5_SAI1_A && STM32H5_SAI1_B ---help--- Select the synchronization mode of the SAI sub-blocks -config STM32L5_SAI1_BOTH_ASYNC +config STM32H5_SAI1_BOTH_ASYNC bool "Both asynchronous" -config STM32L5_SAI1_A_SYNC_WITH_B +config STM32H5_SAI1_A_SYNC_WITH_B bool "Block A is synchronous with Block B" -config STM32L5_SAI1_B_SYNC_WITH_A +config STM32H5_SAI1_B_SYNC_WITH_A bool "Block B is synchronous with Block A" endchoice # SAI1 synchronization enable choice prompt "SAI2 synchronization enable" - default STM32L5_SAI2_BOTH_ASYNC - depends on STM32L5_SAI2_A && STM32L5_SAI2_B + default STM32H5_SAI2_BOTH_ASYNC + depends on STM32H5_SAI2_A && STM32H5_SAI2_B ---help--- Select the synchronization mode of the SAI sub-blocks -config STM32L5_SAI2_BOTH_ASYNC +config STM32H5_SAI2_BOTH_ASYNC bool "Both asynchronous" -config STM32L5_SAI2_A_SYNC_WITH_B +config STM32H5_SAI2_A_SYNC_WITH_B bool "Block A is synchronous with Block B" -config STM32L5_SAI2_B_SYNC_WITH_A +config STM32H5_SAI2_B_SYNC_WITH_A bool "Block B is synchronous with Block A" endchoice # SAI2 synchronization enable endmenu -endif # ARCH_CHIP_STM32L5 +endif # ARCH_CHIP_STM32H5 diff --git a/boards/arm/stm32h5/nucleo-h563zi/Kconfig b/boards/arm/stm32h5/nucleo-h563zi/Kconfig new file mode 100644 index 0000000000000..e9b20410df91b --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_NUCLEO_H563ZI + +endif diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig new file mode 100644 index 0000000000000..4a92fef3728fd --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-h563zi" +CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y +CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32H563ZI=y +CONFIG_ARCH_CHIP_STM32H5=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV8M_STACKCHECK=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_STM32H5_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_STACKMONITOR=y +CONFIG_SYSTEM_TEE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h5/nucleo-h563zi/include/board.h b/boards/arm/stm32h5/nucleo-h563zi/include/board.h new file mode 100644 index 0000000000000..93bda1000a613 --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/include/board.h @@ -0,0 +1,204 @@ +/**************************************************************************** + * boards/arm/stm32l5/stm32l562e-dk/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* Currently the NUCLEO-H563ZI board support is restricted to running NuttX + * in the Non-Secure domain together with TrustedFirmware-M (TFM). In this + * setup the clock configuration is done by TFM, not by NuttX. The + * respective code is in STM32CubeL5/Projects/NUCLEO-H563ZI/Applications/TFM/ + * TFM_SBSFU_Boot/Src/boot_hal.c and configures the clocks as follows: + * + * System Clock source : PLL (MSI) + * SYSCLK(Hz) : 110000000 + * HCLK(Hz) : 110000000 + * AHB Prescaler : 1 + * APB1 Prescaler : 1 + * APB2 Prescaler : 1 + * MSI Frequency(Hz) : 4000000 + * PLLM : 1 + * PLLN : 55 + * PLLP : 2 + * PLLQ : 2 + * PLLR : 2 + * Flash Latency(WS) : 5 + * Voltage range : 0 + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * MSI - 4 MHz, autotrimmed via LSE + * HSE - not installed + * LSE - 32.768 kHz installed + */ + +#define STM32H5_HSI_FREQUENCY 16000000ul +#define STM32H5_LSI_FREQUENCY 32000 +#define STM32H5_MSI_FREQUENCY 4000000ul +#define STM32H5_LSE_FREQUENCY 32768 + +#define STM32H5_SYSCLK_FREQUENCY 110000000ul +#define STM32H5_HCLK_FREQUENCY STM32H5_SYSCLK_FREQUENCY +#define STM32H5_PCLK1_FREQUENCY STM32H5_HCLK_FREQUENCY +#define STM32H5_PCLK2_FREQUENCY (STM32H5_HCLK_FREQUENCY / 1) + +/* The timer clock frequencies are automatically defined by hardware. If the + * APB prescaler equals 1, the timer clock frequencies are set to the same + * frequency as that of the APB domain. Otherwise they are set to twice. + * Note: TIM1,15,16 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32H5_HCLK_FREQUENCY + +/* DMA Channel/Stream Selections ********************************************/ + +/* Alternate function pin selections ****************************************/ + +/* USART3: Connected to Arduino connector D0/D1 (or to STLink VCP if solder + * bridges SB123 to SB130 are re-worked accordingly). + */ + +#define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */ +#define GPIO_USART1_TX GPIO_USART1_TX_1 /* PA9 */ + +/* LED definitions **********************************************************/ + +/* The NUCLEO-H563ZI board has numerous LEDs but only two, LD9 a Red LED, + * and LD10 a Green LED, that can be controlled by software. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs + * in any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_NLEDS 2 + +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_RED BOARD_LED2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) + +/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in + * include/board.h and src/stm32_autoleds.c. The LEDs are used to encode OS- + * related events as follows: + * + * + * SYMBOL Meaning LED state + * Red Green + * ---------------------- -------------------------- ------ ----- + */ +#define LED_STARTED 0 /* NuttX has been started OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated ON OFF */ +#define LED_IRQSENABLED 2 /* Interrupts enabled ON ON */ +#define LED_STACKCREATED 3 /* Idle stack created OFF ON */ +#define LED_INIRQ 4 /* In an interrupt GLOW N/C */ +#define LED_SIGNAL 5 /* In a signal handler GLOW N/C */ +#define LED_ASSERTION 6 /* An assertion failed GLOW N/C */ +#define LED_PANIC 7 /* The system has crashed Blink OFF */ +#define LED_IDLE 8 /* MCU is is sleep mode N/C ON */ + +/* Thus if the Green LED is statically on, NuttX has successfully booted and + * is, apparently, idleing. If the Red LED is flashing at approximately 2Hz, + * then a fatal error has been detected and the system has halted. + */ + +/* Button definitions *******************************************************/ + +/* The Nucleo-L552ZE supports one button: Pushbutton B1, labeled "User", is + * connected to GPIO PC13. + * A high value will be sensed when the button is pressed. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32l5_board_initialize + * + * Description: + * All STM32H5 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices + * have been initialized. + * + ****************************************************************************/ + +void stm32l5_board_initialize(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h5/nucleo-h563zi/scripts/Make.defs b/boards/arm/stm32h5/nucleo-h563zi/scripts/Make.defs new file mode 100644 index 0000000000000..9a900b94509ff --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/scripts/Make.defs @@ -0,0 +1,38 @@ +############################################################################## +# boards/arm/stm32h5/nucleo-h563zi/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################## + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv8-m/Toolchain.defs + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)tfm-ns.ld + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32h5/nucleo-h563zi/scripts/tfm-ns.ld b/boards/arm/stm32h5/nucleo-h563zi/scripts/tfm-ns.ld new file mode 100644 index 0000000000000..ae910e64805ac --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/scripts/tfm-ns.ld @@ -0,0 +1,115 @@ +/**************************************************************************** + * boards/arm/stm32h5/nucleo-h563zi/scripts/tfm-ns.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This linker script supports running NuttX in the 'Non-Secure' (ns) domain + * in conjunction with TrustedFirmware-M (tfm). + * + * NuttX will run as the 'Non secure application' in the 'Non-Secure Image + * primary primary slot Area 1' in external flash. Compare [UM2671], + * Figure 8. Furthermore, see Figure 15 for the SRAM area used for 'Non- + * Secure application volatile data' + * + * While the 'Non-Secure Image primary slot Area 1' is actually one MiB large + * in the referenced setup, the image will be enriched with a header of 0x400 + * bytes and a trailer of 0x2000 bytes. Thus the 'flash' statement in the + * MEMORY definition below. + * + * References + * [UM2671] STMicroelectronics. UM2671: Getting started with STM32CubeL5 TFM + * application, 2nd edition, July 2020 + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x90000400, LENGTH = 0xFDC00 + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 192K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/.gitignore b/boards/arm/stm32h5/nucleo-h563zi/src/.gitignore new file mode 100644 index 0000000000000..726d936e1e339 --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/Makefile b/boards/arm/stm32h5/nucleo-h563zi/src/Makefile new file mode 100644 index 0000000000000..27f58d4ceedf5 --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/Makefile @@ -0,0 +1,40 @@ +############################################################################## +# boards/arm/stm32h5/nucleo-h563zi/src/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################## + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c stm32_bringup.c stm32_clockconfig.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_BOARDCTL),y) +CSRCS += stm32_appinit.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h b/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h new file mode 100644 index 0000000000000..eb941e582b042 --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h @@ -0,0 +1,117 @@ +/**************************************************************************** + * boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H +#define __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "stm32h5_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_PROC 1 +#define HAVE_RTC_DRIVER 1 + +#if !defined(CONFIG_FS_PROCFS) +# undef HAVE_PROC +#endif + +#if defined(HAVE_PROC) && defined(CONFIG_DISABLE_MOUNTPOINT) +# warning Mountpoints disabled. No procfs support +# undef HAVE_PROC +#endif + +/* Check if we can support the RTC driver */ + +#if !defined(CONFIG_RTC) || !defined(CONFIG_RTC_DRIVER) +# undef HAVE_RTC_DRIVER +#endif + +/* NUCLEO-H563ZI GPIOs ******************************************************/ + +/* LED I/O Color + * LD9 PD3 Red + * LD10 PG12 Green + * + * - When the I/O is LOW, the LED is on. + * - When the I/O is HIGH value, the LED is off + */ + +#define GPIO_LD9 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHZ | \ + GPIO_OUTPUT_SET | GPIO_PORTD | GPIO_PIN3) +#define GPIO_LD10 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHZ | \ + GPIO_OUTPUT_SET | GPIO_PORTG | GPIO_PIN12) + +/* Button definitions *******************************************************/ + +/* B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32 + * microcontroller. + */ + +#define MIN_IRQBUTTON BUTTON_USER +#define MAX_IRQBUTTON BUTTON_USER +#define NUM_IRQBUTTONS 1 + +#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | \ + GPIO_PORTC | GPIO_PIN13) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H */ diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_appinit.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_appinit.c new file mode 100644 index 0000000000000..af1977d125263 --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_appinit.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/stm32h5/nucleo-h563zi/src/stm32_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "nucleo-h563zi.h" + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ + /* Did we already initialize via board_late_initialize()? */ + +#ifndef CONFIG_BOARD_LATE_INITIALIZE + return stm32_bringup(); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_autoleds.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_autoleds.c new file mode 100644 index 0000000000000..f6931d3ec7c44 --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_autoleds.c @@ -0,0 +1,170 @@ +/**************************************************************************** + * boards/arm/stm32h5/nucleo-h563zi/src/stm32_autoleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32h5_gpio.h" +#include "nucleo-h563zi.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Indexed by BOARD_LED_ */ + +static const uint32_t g_ledmap[BOARD_NLEDS] = +{ + GPIO_LD10, + GPIO_LD9, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void phy_set_led(int led, bool state) +{ + /* Active Low */ + + stm32h5_gpiowrite(g_ledmap[led], !state); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + int i; + + /* Configure the LD9 and LD10 GPIOs for output. Initial state is OFF */ + + for (i = 0; i < nitems(g_ledmap); i++) + { + stm32h5_configgpio(g_ledmap[i]); + } +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + default: + break; + + case LED_HEAPALLOCATE: + phy_set_led(BOARD_LED_RED, true); + phy_set_led(BOARD_LED_GREEN, false); + break; + + case LED_IRQSENABLED: + phy_set_led(BOARD_LED_RED, true); + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_STACKCREATED: + phy_set_led(BOARD_LED_RED, false); + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_RED, true); + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_RED, true); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, true); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, true); + phy_set_led(BOARD_LED_GREEN, false); + break; + + case LED_IDLE: + phy_set_led(BOARD_LED_GREEN, true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + default: + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_RED, false); + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_RED, false); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, false); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, false); + phy_set_led(BOARD_LED_GREEN, false); + break; + + case LED_IDLE: + phy_set_led(BOARD_LED_GREEN, false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_boot.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_boot.c new file mode 100644 index 0000000000000..734a43d770a06 --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_boot.c @@ -0,0 +1,90 @@ +/**************************************************************************** + * boards/arm/stm32h5/nucleo-h563zi/src/stm32_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "arm_internal.h" +#include "nucleo-h563zi.h" +#include "stm32h5_pwr.h" + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32h5_board_initialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32h5_board_initialize(void) +{ + /* On the NUCLEO-H563ZI Vddio2 is supplied by Vdd_mcu. Thus, when the MCU + * is running Vddio2 is guaranteed to be valid. LED LD10 is driven by + * PG12, whose power is supplied by Vddio2. Thus, its important to report + * Vddio2 to be valid here. + */ + + stm32h5_pwr_vddio2_valid(true); + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization here if so configured */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c new file mode 100644 index 0000000000000..37fbc400cb1ca --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "nucleo-h563zi.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS +#ifdef CONFIG_INPUT_BUTTONS_LOWER + iinfo("Initializing button driver\n"); + + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + ierr("ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#else + /* Enable BUTTON support for some other purpose */ + + board_button_initialize(); +#endif +#endif /* CONFIG_INPUT_BUTTONS */ + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_buttons.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_buttons.c new file mode 100644 index 0000000000000..865b78a42b049 --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_buttons.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32h5/nucleo-h563zi/src/stm32_buttons.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32h5_gpio.h" +#include "nucleo-h563zi.h" + +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32h5_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check the state of the USER button. */ + + return stm32h5_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns a + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32h5_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c new file mode 100644 index 0000000000000..3546e849c247c --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c @@ -0,0 +1,48 @@ +/**************************************************************************** + * boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_board_clockconfig + * + * Description: + * Currently the NUCLEO-H563ZI board support is restricted to running NuttX + * in the Non-Secure domain together with TrustedFirmware-M (TFM). In this + * setup the clock configuration is done by TFM, not by NuttX. Thus, the + * board's configuration sets CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG + * to avoid the standard clock config logic to run and instead do just + * nothing in this function. + * + ****************************************************************************/ + +#if defined(CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG) +void stm32h5_board_clockconfig(void) +{ +} +#endif diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_userleds.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_userleds.c new file mode 100644 index 0000000000000..4d333261f1274 --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_userleds.c @@ -0,0 +1,123 @@ +/**************************************************************************** + * boards/arm/stm32h5/nucleo-h563zi/src/stm32_userleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "stm32h5_gpio.h" +#include "nucleo-h563zi.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration and is indexed by + * BOARD_LED_ + */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LD10, + GPIO_LD9, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the + * board_userled_initialize() is available to initialize the LEDs from user + * application logic. + * + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure LED1-2 GPIOs for output */ + + for (i = 0; i < nitems(g_ledcfg); i++) + { + stm32h5_configgpio(g_ledcfg[i]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled() is + * available to control the LEDs from user application logic. + * + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < nitems(g_ledcfg)) + { + stm32h5_gpiowrite(g_ledcfg[led], !ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled_all() + * is available to control the LED from user application logic. + * + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED1-2 GPIOs for output */ + + for (i = 0; i < nitems(g_ledcfg); i++) + { + stm32h5_gpiowrite(g_ledcfg[i], !(ledset & (1 << i))); + } +} + +#endif /* !CONFIG_ARCH_LEDS */