From 921b32663b356a25169427a2ad10b0baaef8c39b Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Thu, 10 Nov 2022 15:32:09 +0800 Subject: [PATCH] board: arm64: add pinctrl support for imx93 evk board 1. Added imx93-pinctrl dts binding yaml 2. Added imx93 pinctrl_soc.h header file 3. Updated imx93 dts to enable pinctrl for lpuart. Signed-off-by: Jiafei Pan --- .../arm64/mimx93_evk/mimx93_evk-pinctrl.dtsi | 19 ++++ boards/arm64/mimx93_evk/mimx93_evk_a55.dts | 4 + .../arm64/mimx93_evk/mimx93_evk_a55_defconfig | 1 + dts/arm64/nxp/nxp_mimx93_a55.dtsi | 4 + dts/bindings/pinctrl/nxp,imx93-pinctrl.yaml | 104 ++++++++++++++++++ soc/arm64/nxp_imx/mimx9/pinctrl_soc.h | 83 ++++++++++++++ 6 files changed, 215 insertions(+) create mode 100644 boards/arm64/mimx93_evk/mimx93_evk-pinctrl.dtsi create mode 100644 dts/bindings/pinctrl/nxp,imx93-pinctrl.yaml create mode 100644 soc/arm64/nxp_imx/mimx9/pinctrl_soc.h diff --git a/boards/arm64/mimx93_evk/mimx93_evk-pinctrl.dtsi b/boards/arm64/mimx93_evk/mimx93_evk-pinctrl.dtsi new file mode 100644 index 00000000000..50186a49b0a --- /dev/null +++ b/boards/arm64/mimx93_evk/mimx93_evk-pinctrl.dtsi @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2022, NXP + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include + +&pinctrl { + uart2_default: uart2_default { + group0 { + pinmux = <&iomuxc_uart2_rxd_uart_rx_uart2_rx>, + <&iomuxc_uart2_txd_uart_tx_uart2_tx>; + bias-pull-up; + slew-rate = "slightly_fast"; + drive-strength = "x5"; + }; + }; +}; diff --git a/boards/arm64/mimx93_evk/mimx93_evk_a55.dts b/boards/arm64/mimx93_evk/mimx93_evk_a55.dts index 7a10438b3cb..4ace0665671 100644 --- a/boards/arm64/mimx93_evk/mimx93_evk_a55.dts +++ b/boards/arm64/mimx93_evk/mimx93_evk_a55.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include "mimx93_evk-pinctrl.dtsi" / { model = "NXP i.MX93 A55"; @@ -32,4 +33,7 @@ &lpuart2 { status = "okay"; current-speed = <115200>; + /* clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; */ + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; }; diff --git a/boards/arm64/mimx93_evk/mimx93_evk_a55_defconfig b/boards/arm64/mimx93_evk/mimx93_evk_a55_defconfig index 3b22e7fbb13..2bcf6198a10 100644 --- a/boards/arm64/mimx93_evk/mimx93_evk_a55_defconfig +++ b/boards/arm64/mimx93_evk/mimx93_evk_a55_defconfig @@ -29,3 +29,4 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_CLOCK_CONTROL=y +CONFIG_PINCTRL=y diff --git a/dts/arm64/nxp/nxp_mimx93_a55.dtsi b/dts/arm64/nxp/nxp_mimx93_a55.dtsi index 0175829e767..48a8434ff68 100644 --- a/dts/arm64/nxp/nxp_mimx93_a55.dtsi +++ b/dts/arm64/nxp/nxp_mimx93_a55.dtsi @@ -64,6 +64,10 @@ compatible = "nxp,imx-iomuxc"; reg = <0x443c0000 DT_SIZE_K(64)>; status = "okay"; + pinctrl: pinctrl { + status = "okay"; + compatible = "nxp,imx93-pinctrl"; + }; }; ana_pll: ana_pll@44480000 { diff --git a/dts/bindings/pinctrl/nxp,imx93-pinctrl.yaml b/dts/bindings/pinctrl/nxp,imx93-pinctrl.yaml new file mode 100644 index 00000000000..5c046a76ffe --- /dev/null +++ b/dts/bindings/pinctrl/nxp,imx93-pinctrl.yaml @@ -0,0 +1,104 @@ +# Copyright (c) 2022 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: | + The node has the 'pinctrl' node label set in MCUX SoC's devicetree. These + nodes can be autogenerated using the MCUXpresso config tools combined with + the imx_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg + fields in a group select the pins to be configured, and the remaining + devicetree properties set configuration values for those pins + for example, here is an group configuring LPUART1 pins: + + group0 { + pinmux = <&iomuxc_uart2_rxd_uart_rx_uart2_rx, + &iomuxc_uart2_txd_uart_tx_uart2_tx>; + bias-pull-up; + slew-rate = "slow"; + drive-strength = "x1"; + }; + + This will select UART2_RXD as UART2 rx, and UART2_TXD as UART2 tx. + Both pins will be configured with a slow slew rate, and x1 drive + strength. + Note that the soc level iomuxc dts file can be examined to find the possible + pinmux options. Here are the affects of each property on the + IOMUXC SW_PAD_CTL register: + input-schmitt-enable: HYS=1 + drive-open-drain: OD=1 + bias-pull-down: PD=0 + bias-pull-up: PU + slew-rate: FSEL1= + drive-strength: DSE= + input-enable: SION=1 (in SW_MUX_CTL_PAD register) + + If only required properties are supplied, the pin will have the following + configuration: + HYS=0, + PD=0 + PU=0 + OD=0, + FSEL1=, + DSE=, + SION=0, + + +compatible: "nxp,imx93-pinctrl" + +include: base.yaml + +child-binding: + description: iMX pin controller pin group + child-binding: + description: | + iMX pin controller pin configuration node. + + include: + - name: pincfg-node.yaml + property-allowlist: + - input-schmitt-enable + - drive-open-drain + - input-enable + - bias-pull-up + - bias-pull-down + + properties: + pinmux: + required: true + type: phandles + description: | + Pin mux selections for this group. See the soc level iomuxc DTSI file + for a defined list of these options. + drive-strength: + required: true + type: string + enum: + - "x0" + - "x1" + - "x2" + - "x3" + - "x4" + - "x5" + - "x6" + description: | + Pin output drive strength. Sets the DSE field in the IOMUXC peripheral. + 00_0000 X0, No driver + 00_0001 X1 + 00_0011 X2 + 00_0111 X3 + 00_1111 X4 + 01_1111 X5 + 11_1111 X6 + slew-rate: + required: true + type: string + enum: + - "slow" + - "slightly_slow" + - "slightly_fast" + - "fast" + description: | + Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral + 0 SLOW — Slow Frequency Slew Rate + 1 Slightly SLOW — Slightly Slow Frequency Slew Rate + 2 Slightly FAST — Slightly Fast Frequency Slew Rate + 3 FAST — Fast Frequency Slew Rate diff --git a/soc/arm64/nxp_imx/mimx9/pinctrl_soc.h b/soc/arm64/nxp_imx/mimx9/pinctrl_soc.h new file mode 100644 index 00000000000..c3c66d532ec --- /dev/null +++ b/soc/arm64/nxp_imx/mimx9/pinctrl_soc.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2022, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_ARM64_NXP_IMX9_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM64_NXP_IMX9_PINCTRL_SOC_H_ + +#include +#include +#include "fsl_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC1_SW_PAD_CTL_PAD_HYS_SHIFT +#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC1_SW_PAD_CTL_PAD_OD_SHIFT +#define MCUX_IMX_BIAS_PULL_DOWN_SHIFT IOMUXC1_SW_PAD_CTL_PAD_PD_SHIFT +#define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC1_SW_PAD_CTL_PAD_PU_SHIFT +#define MCUX_IMX_BIAS_PULL_ENABLE_SHIFT IOMUXC1_SW_PAD_CTL_PAD_PE_SHIFT +#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC1_SW_PAD_CTL_PAD_FSEL1_SHIFT +#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC1_SW_PAD_CTL_PAD_DSE_SHIFT +#define MCUX_IMX_INPUT_ENABLE_SHIFT 23 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */ +#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1) + +#define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id) \ + ((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \ + (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \ + (DT_PROP(node_id, bias_pull_down) << MCUX_IMX_BIAS_PULL_DOWN_SHIFT) | \ + (DT_PROP(node_id, bias_pull_up) << MCUX_IMX_BIAS_PULL_UP_SHIFT) | \ + (DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \ + ((~(0xff << DT_ENUM_IDX(node_id, drive_strength))) << MCUX_IMX_DRIVE_STRENGTH_SHIFT) | \ + (DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT)) + + +/* This struct must be present. It is used by the mcux gpio driver */ +struct pinctrl_soc_pinmux { + uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */ + uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */ + uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */ + uint8_t mux_mode: 4; /*!< Mux value for SW_PAD_MUX register */ + uint32_t input_daisy:4; /*!< Mux value for SELECT_INPUT_DAISY register */ +}; + +struct pinctrl_soc_pin { + struct pinctrl_soc_pinmux pinmux; + uint32_t pin_ctrl_flags; /*!< value to write to IOMUXC_SW_PAD_CTL register */ +}; + +typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; + +/* This definition must be present. It is used by the mcux gpio driver */ +#define MCUX_IMX_PINMUX(node_id) \ + { \ + .mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \ + .config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \ + .input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \ + .mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \ + .input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \ + } + +#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \ + MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx)) + +#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \ + { \ + .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \ + .pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PINCFG_INIT(group_id), \ + }, + + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \ + DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}; \ + + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_ARM64_NXP_IMX9_PINCTRL_SOC_H_ */