Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Build an annotation-based cosim-wrapper code generator #3

Open
mkorbel1 opened this issue Feb 7, 2023 · 0 comments
Open

Build an annotation-based cosim-wrapper code generator #3

mkorbel1 opened this issue Feb 7, 2023 · 0 comments
Labels
enhancement New feature or request

Comments

@mkorbel1
Copy link
Contributor

mkorbel1 commented Feb 7, 2023

It can be tedious to build a cosim wrapper for a SystemVerilog module for cosimulation. Since enough information is provided anyways to build and simulate the module, it would be nice to have an annotation-based code generator which could build the wrapper with all ports already added.
@mkorbel1 mkorbel1 added the enhancement New feature or request label Feb 7, 2023
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
enhancement New feature or request
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
1 participant
@mkorbel1