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Add testing that SV # delays are properly handled #13

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mkorbel1 opened this issue Feb 8, 2023 · 0 comments
Open

Add testing that SV # delays are properly handled #13

mkorbel1 opened this issue Feb 8, 2023 · 0 comments
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enhancement New feature or request

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@mkorbel1
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mkorbel1 commented Feb 8, 2023

A # delay in the SystemVerilog simulator can result in signals changing at intermediate times between ticks and not edge triggered by any signal driven by ROHD Cosim. We should add better testing that these scenarios still function correctly.
@mkorbel1 mkorbel1 added the enhancement New feature or request label Feb 8, 2023
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