[enhancement] Scheduling: (send, receive) pairs on internal channels should be constrained together

[grebe]

What's hard to do? (limit 100 words)

Consider a proc A with the following schedule:

| x=recv(chIn); f(x) -|> x=g(x) -|> send(chInternal, h(x)) |

and a proc B that receives the result of proc A

| y=recv(chInternal); y=a(y) -|> y=b(y) -|> send(chOut, c(y)) |

The current scheduling implementation applies an IO delay to the recv(chInternal) (also the send), but that scheduling option should really only be for external channels.

Current best alternative workaround (limit 100 words)

Disable FIFO configs with bypass+no-register_pop_outputs. This impacts throughput and potentially deadlock behavior.

Your view of the "best case XLS enhancement" (limit 100 words)

It's not difficult to not add the IO delay to internal channels, but depending on the FIFO config (in particular, is bypass enabled and it pop output flopping disabled?) you may need the delay on recv(chInternal) to be constrained by the delay on the send. However, because they are in different pipelines, you need to say something like startTime(recv(chInternal)) = stageVar + (startTime(send(chInternal)) % clock_period_ps). Ideally we'd schedule all procs at once with constraints that allows the scheduler to decide if it's better to increase flop count in one proc to reduce flops in the other.

[grebe]

Also, we may want a separate codegen option for specifying delay behavior through FIFOs- the equality I wrote is only true if the FIFO has no delay.