From 462a6c65c4dd0518be6dd77c172900a2e7fc2a0f Mon Sep 17 00:00:00 2001
From: Pawel Czarnecki <pczarnecki@antmicro.com>
Date: Fri, 4 Oct 2024 14:09:56 +0200
Subject: [PATCH] CI/modules-zstd: Add calls to verilog simulation targets

Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
---
 .github/workflows/modules-zstd.yml | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/.github/workflows/modules-zstd.yml b/.github/workflows/modules-zstd.yml
index 002a0c23c7..0fc4edd996 100644
--- a/.github/workflows/modules-zstd.yml
+++ b/.github/workflows/modules-zstd.yml
@@ -75,6 +75,16 @@ jobs:
             bazel run -c opt $target -- --logtostderr;
           done
 
+      - name: Build and run verilog simulation of the ZSTD module components (opt)
+        if: ${{ !cancelled() }}
+        run: |
+          for target in $(bazel query 'filter(".*_cocotb_test$", kind(rule, //xls/modules/zstd/...))');
+          do
+            echo "running $target";
+            bazel run -c opt $target;
+            find sim_build ! -name "*.fst" -type f -exec rm -f {} +;
+          done
+
       - name: Build ZSTD place and route targets (opt)
         if: ${{ !cancelled() }}
         run: |