From ce85707c48207295c3f070c6ba48fdb14c08cedb Mon Sep 17 00:00:00 2001 From: erlingrj Date: Sun, 7 Jan 2024 14:48:05 +0100 Subject: [PATCH 1/2] Add clockPeriod as user option --- src/main/scala/Reaction.scala | 7 ++++--- src/main/scala/Reactor.scala | 5 +++-- src/main/scala/Token.scala | 2 +- src/main/scala/TriggerGenerator.scala | 2 +- src/main/scala/Utils.scala | 9 ++++----- 5 files changed, 13 insertions(+), 12 deletions(-) diff --git a/src/main/scala/Reaction.scala b/src/main/scala/Reaction.scala index de79a5c..f25535d 100644 --- a/src/main/scala/Reaction.scala +++ b/src/main/scala/Reaction.scala @@ -58,7 +58,7 @@ class ReactionPrecedencePorts(c: ReactionConfig) extends Bundle { class ReactionStatePorts() -abstract class Reaction (val c: ReactionConfig = ReactionConfig(0,0)) extends Module { +abstract class Reaction (val c: ReactionConfig = ReactionConfig(0,0))(implicit globalReactorConfig: GlobalReactorConfig) extends Module { import ReactionApi.{lf_set, lf_get, lf_present} implicit val instance: Reaction = this val io: ReactionIO @@ -80,7 +80,8 @@ abstract class Reaction (val c: ReactionConfig = ReactionConfig(0,0)) extends Mo val logicalTag = RegInit(0.U(64.W)) val physicalTag = RegInit(0.U(64.W)) - physicalTag := physicalTag + 1.U + physicalTag := physicalTag + globalReactorConfig.clockPeriod.nanoseconds.U + def driveDefaults(): Unit = { io.driveDefaults() precedenceIn.foreach(_.driveDefaults()) @@ -199,7 +200,7 @@ abstract class Reaction (val c: ReactionConfig = ReactionConfig(0,0)) extends Mo } } - assert(!(regCycles > 10000.U), "[Reaction] Reaction was running for over 10000cc assumed error") + assert(!(regCycles > 100000000.U), "[Reaction] Reaction was running for over 10000cc assumed error") // FIXME: These debug signals should be optional statusIO.state := regState diff --git a/src/main/scala/Reactor.scala b/src/main/scala/Reactor.scala index aa41e07..4a850ed 100644 --- a/src/main/scala/Reactor.scala +++ b/src/main/scala/Reactor.scala @@ -21,7 +21,8 @@ package object globals { case class GlobalReactorConfig( timeout: Time, standalone: Boolean, - triggerLatency: Int = 4 + triggerLatency: Int = 4, + clockPeriod: Time = Time.nsec(1) ) abstract class ReactorIO extends Bundle { @@ -99,7 +100,7 @@ class ReactorTriggerIO(cfg: ReactorTriggerConfig) extends Bundle { def allTimerTriggers = localTimerTriggers ++ containedTimerTriggers } -abstract class Reactor extends Module { +abstract class Reactor(implicit gc: GlobalReactorConfig) extends Module { // The Inputs and Outputs of the reactor val io: ReactorIO diff --git a/src/main/scala/Token.scala b/src/main/scala/Token.scala index 2661764..2d0ed84 100644 --- a/src/main/scala/Token.scala +++ b/src/main/scala/Token.scala @@ -134,7 +134,7 @@ abstract class TokenReadMaster[T1 <: Data, T2 <: Token[T1]](gen1: T1, gen2: T2) def read(addr: UInt, size: UInt): DecoupledIO[TokenRdResp[T1]] } -class ArrayTokenReadMaster[T1 <: Data](gen1: T1, gen2: ArrayToken[T1]) extends TokenReadMaster(gen1, gen2) { +class ArrayTokenReadMaster[T1 <: Data](gen1: T1, gen2: ArrayToken[T1]) extends TokenReadMaster(gen1, gen2) { val req = Decoupled(new ArrayTokenRdReq(gen1, gen2)) val resp = Flipped(Decoupled(new TokenRdResp(gen1))) diff --git a/src/main/scala/TriggerGenerator.scala b/src/main/scala/TriggerGenerator.scala index 7726cf8..d6a4f0a 100644 --- a/src/main/scala/TriggerGenerator.scala +++ b/src/main/scala/TriggerGenerator.scala @@ -42,7 +42,7 @@ class MainClock(implicit cfg: GlobalReactorConfig) extends Module { when(io.setTime.valid) { regClock := io.setTime.bits + cfg.triggerLatency.U }.otherwise { - regClock := regClock + 1.U + regClock := regClock + cfg.clockPeriod.nanoseconds.U } io.now := regClock } diff --git a/src/main/scala/Utils.scala b/src/main/scala/Utils.scala index 02ed265..3c6fb46 100644 --- a/src/main/scala/Utils.scala +++ b/src/main/scala/Utils.scala @@ -23,15 +23,14 @@ object CharacterizeUtils { val dummyParam = new DummyParams val zedboardPart = "xc7z020clg484-1" - def standalone(reactor: () => StandaloneTopReactor, buildDir: String): Unit = { + def standalone(reactor: () => StandaloneTopReactor, targetClockPeriod: Time, buildDir: String): Unit = { val genTop = (d: DummyParams) => reactor.apply() - VivadoSynth.characterizePoint(dummyParam, genTop, buildDir, zedboardPart,"StandaloneTopReactor") + VivadoSynth.characterizePoint(dummyParam, genTop, buildDir, zedboardPart, targetClockPeriod.nsec.toInt, "StandaloneTopReactor") } - def codesign(reactor: () => CodesignTopReactor, buildDir: String): Unit = { + def codesign(reactor: () => CodesignTopReactor, targetClockPeriod: Time, buildDir: String): Unit = { val genTop = (d: DummyParams) => reactor.apply() - VivadoSynth.characterizePoint(dummyParam, genTop, buildDir, zedboardPart, "CodesignTopReactor") - + VivadoSynth.characterizePoint(dummyParam, genTop, buildDir, zedboardPart, targetClockPeriod.nsec.toInt, "CodesignTopReactor") } } \ No newline at end of file From 6c8aecd0211acc4c1e58d1cdd9ae950880a25204 Mon Sep 17 00:00:00 2001 From: erlingrj Date: Sun, 7 Jan 2024 14:48:22 +0100 Subject: [PATCH 2/2] Bumpt fpga-tidbits --- fpga-tidbits | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga-tidbits b/fpga-tidbits index 447b9de..5e2d40e 160000 --- a/fpga-tidbits +++ b/fpga-tidbits @@ -1 +1 @@ -Subproject commit 447b9de90b2674ef3eff174d425f180581db6e13 +Subproject commit 5e2d40e7fa3549d11d3b0ddcb54364b7272d4321