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AutoDefs.h43
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;*********************************************************************************************
;* Automatic Definitions based on Board.h43 *
;*-------------------------------------------------------------------------------------------*
;* AutoDefs.h43 *
;* Author: eliaschr *
;* Copyright (c) 2019, Elias Chrysocheris *
;* *
;* This program is free software: you can redistribute it and/or modify *
;* it under the terms of the GNU General Public License as published by *
;* the Free Software Foundation, either version 3 of the License, or *
;* (at your option) any later version. *
;* *
;* This program is distributed in the hope that it will be useful, *
;* but WITHOUT ANY WARRANTY; without even the implied warranty of *
;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
;* GNU General Public License for more details. *
;* *
;* You should have received a copy of the GNU General Public License *
;* along with this program. If not, see <https://www.gnu.org/licenses/>. *
;*-------------------------------------------------------------------------------------------*
;* Here there are some automatic definitions computed. The reason is for the setup to be as *
;* simple as possible and the user intervention as less as possible. *
;* Example of automatic definitions is the computation of interrupt vectors according to *
;* the pins a resource is connected to. *
;*********************************************************************************************
;* Note: Correct format of the file is presented when tab space is set to 4
.title "Automatic Definitions based on Board.h43"
.width 94
.tab 4
.if ($isdefed("__BOARD_AUTO_DEFS__") == 0)
.if ($isdefed("__BOARD_DEFS__") == 0)
.emsg "Board.h43 should be included before AutoDefs.h43"
.endif
__BOARD_AUTO_DEFS__: .equ 1 ;Need to define this in order to avoid
; double inclusions
;----------------------------------------
; Keyboard Definitions
;========================================
.if (Board_KeyPort == 1) ;Lets define the keyboard registers needed
KBD_DIN: .equ P1IN ;Data input register from keyboard
KBD_DOUT: .equ P1OUT ;Data output register for keyboard
KBD_DIR: .equ P1DIR ;Direction selection register for key pins
KBD_REN: .equ P1REN ;Resistor setup register for key pins
KBD_SEL0: .equ P1SEL0 ;Special function selection registers
KBD_SEL1: .equ P1SEL1
KBD_INTE: .equ P1IE ;Interrupt enable register for keypresses
KBD_INTES: .equ P1IES ;Interrupt edge selector register
KBD_INTF: .equ P1IFG ;Interrupt flags reflecting the keypresses
KBD_INTV: .equ P1IV ;Interrupt vector register
.define "PORT1_VECTOR", KBD_Vector ;Interrupt Vector Segment
.elseif (Board_KeyPort == 2)
KBD_DIN: .equ P2IN
KBD_DOUT: .equ P2OUT
KBD_DIR: .equ P2DIR
KBD_REN: .equ P2REN
KBD_SEL0: .equ P2SEL0
KBD_SEL1: .equ P2SEL1
KBD_INTE: .equ P2IE
KBD_INTES: .equ P2IES
KBD_INTF: .equ P2IFG
KBD_INTV: .equ P2IV
.define "PORT2_VECTOR", KBD_Vector
.elseif (Board_KeyPort == 3)
KBD_DIN: .equ P3IN
KBD_DOUT: .equ P3OUT
KBD_DIR: .equ P3DIR
KBD_REN: .equ P3REN
KBD_SEL0: .equ P3SEL0
KBD_SEL1: .equ P3SEL1
KBD_INTE: .equ P3IE
KBD_INTES: .equ P3IES
KBD_INTF: .equ P3IFG
KBD_INTV: .equ P3IV
.define "PORT3_VECTOR", KBD_Vector
.elseif (Board_KeyPort == 4)
KBD_DIN: .equ P4IN
KBD_DOUT: .equ P4OUT
KBD_DIR: .equ P4DIR
KBD_REN: .equ P4REN
KBD_SEL0: .equ P4SEL0
KBD_SEL1: .equ P4SEL1
KBD_INTE: .equ P4IE
KBD_INTES: .equ P4IES
KBD_INTF: .equ P4IFG
KBD_INTV: .equ P4IV
.define "PORT4_VECTOR", KBD_Vector
.elseif (Board_KeyPort == 5)
KBD_DIN: .equ P5IN
KBD_DOUT: .equ P5OUT
KBD_DIR: .equ P5DIR
KBD_REN: .equ P5REN
KBD_SEL0: .equ P5SEL0
KBD_SEL1: .equ P5SEL1
KBD_INTE: .equ P5IE
KBD_INTES: .equ P5IES
KBD_INTF: .equ P5IFG
KBD_INTV: .equ P5IV
.define "PORT5_VECTOR", KBD_Vector
.elseif (Board_KeyPort == 6)
KBD_DIN: .equ P6IN
KBD_DOUT: .equ P6OUT
KBD_DIR: .equ P6DIR
KBD_REN: .equ P6REN
KBD_SEL0: .equ P6SEL0
KBD_SEL1: .equ P6SEL1
KBD_INTE: .equ P6IE
KBD_INTES: .equ P6IES
KBD_INTF: .equ P6IFG
KBD_INTV: .equ P6IV
.define "PORT6_VECTOR", KBD_Vector
.elseif (Board_KeyPort == 7)
KBD_DIN: .equ P7IN
KBD_DOUT: .equ P7OUT
KBD_DIR: .equ P7DIR
KBD_REN: .equ P7REN
KBD_SEL0: .equ P7SEL0
KBD_SEL1: .equ P7SEL1
KBD_INTE: .equ P7IE
KBD_INTES: .equ P7IES
KBD_INTF: .equ P7IFG
KBD_INTV: .equ P7IV
.define "PORT7_VECTOR", KBD_Vector
.elseif (Board_KeyPort == 8)
KBD_DIN: .equ P8IN
KBD_DOUT: .equ P8OUT
KBD_DIR: .equ P8DIR
KBD_REN: .equ P8REN
KBD_SEL0: .equ P8SEL0
KBD_SEL1: .equ P8SEL1
KBD_INTE: .equ P8IE
KBD_INTES: .equ P8IES
KBD_INTF: .equ P8IFG
KBD_INTV: .equ P8IV
.define "PORT8_VECTOR", KBD_Vector
.else
.emsg "Board_KeyPort definition in Board.h43 file has to be between 1 and 8"
.endif ;Board_KeyPort
;----------------------------------------
; Leds and Displays Definitions
;========================================
;The led/displays subsystem uses three ports. One port is the driver of the Leds/Segments of
; the displays. Each pin on this port selects which leds of the current group light up (logic
; 1) or stays off (logic 0). The second port is the Control port that selects which group is
; to be used. The leds and displays are all connected in a Common Cathode scheme. One common
; pin selects the leds, one selects the first display and another one selects the second
; display. The selected group is enabled when its associated common pin drives logic 0.
; The third port is for two leds, Anion and Tank Full, that do not take place at the scanning
; process. This is necessary if there will be no hack on the panel board, since these two leds
; have their anodes connected to power lane
;First lets define the registers of the "Data" port (selects which led to light up in a group)
; Not all of the registers are used, but they are set here for completeness
.if (Board_LedPort == 1)
LEDP_DIN: .equ P1IN ;Data input register from leds
LEDP_DOUT: .equ P1OUT ;Data output register for leds
LEDP_DIR: .equ P1DIR ;Direction selection register for led pins
LEDP_REN: .equ P1REN ;Resistor setup register for led pins
LEDP_SEL0: .equ P1SEL0 ;Special function selection registers
LEDP_SEL1: .equ P1SEL1
LEDP_INTE: .equ P1IE ;Interrupt enable register for leds
LEDP_INTES: .equ P1IES ;Interrupt edge selector register
LEDP_INTF: .equ P1IFG ;Interrupt flags register
LEDP_INTV: .equ P1IV ;Interrupt vector register
.define "PORT1_VECTOR", LEDP_Vector ;Interrupt Vector Memory Segment
.elseif (Board_LedPort == 2)
LEDP_DIN: .equ P2IN
LEDP_DOUT: .equ P2OUT
LEDP_DIR: .equ P2DIR
LEDP_REN: .equ P2REN
LEDP_SEL0: .equ P2SEL0
LEDP_SEL1: .equ P2SEL1
LEDP_INTE: .equ P2IE
LEDP_INTES: .equ P2IES
LEDP_INTF: .equ P2IFG
LEDP_INTV: .equ P2IV
.define "PORT2_VECTOR", LEDP_Vector
.elseif (Board_LedPort == 3)
LEDP_DIN: .equ P3IN
LEDP_DOUT: .equ P3OUT
LEDP_DIR: .equ P3DIR
LEDP_REN: .equ P3REN
LEDP_SEL0: .equ P3SEL0
LEDP_SEL1: .equ P3SEL1
LEDP_INTE: .equ P3IE
LEDP_INTES: .equ P3IES
LEDP_INTF: .equ P3IFG
LEDP_INTV: .equ P3IV
.define "PORT3_VECTOR", LEDP_Vector
.elseif (Board_LedPort == 4)
LEDP_DIN: .equ P4IN
LEDP_DOUT: .equ P4OUT
LEDP_DIR: .equ P4DIR
LEDP_REN: .equ P4REN
LEDP_SEL0: .equ P4SEL0
LEDP_SEL1: .equ P4SEL1
LEDP_INTE: .equ P4IE
LEDP_INTES: .equ P4IES
LEDP_INTF: .equ P4IFG
LEDP_INTV: .equ P4IV
.define "PORT4_VECTOR", LEDP_Vector
.elseif (Board_LedPort == 5)
LEDP_DIN: .equ P5IN
LEDP_DOUT: .equ P5OUT
LEDP_DIR: .equ P5DIR
LEDP_REN: .equ P5REN
LEDP_SEL0: .equ P5SEL0
LEDP_SEL1: .equ P5SEL1
LEDP_INTE: .equ P5IE
LEDP_INTES: .equ P5IES
LEDP_INTF: .equ P5IFG
LEDP_INTV: .equ P5IV
.define "PORT5_VECTOR", LEDP_Vector
.elseif (Board_LedPort == 6)
LEDP_DIN: .equ P6IN
LEDP_DOUT: .equ P6OUT
LEDP_DIR: .equ P6DIR
LEDP_REN: .equ P6REN
LEDP_SEL0: .equ P6SEL0
LEDP_SEL1: .equ P6SEL1
LEDP_INTE: .equ P6IE
LEDP_INTES: .equ P6IES
LEDP_INTF: .equ P6IFG
LEDP_INTV: .equ P6IV
.define "PORT6_VECTOR", LEDP_Vector
.elseif (Board_LedPort == 7)
LEDP_DIN: .equ P7IN
LEDP_DOUT: .equ P7OUT
LEDP_DIR: .equ P7DIR
LEDP_REN: .equ P7REN
LEDP_SEL0: .equ P7SEL0
LEDP_SEL1: .equ P7SEL1
LEDP_INTE: .equ P7IE
LEDP_INTES: .equ P7IES
LEDP_INTF: .equ P7IFG
LEDP_INTV: .equ P7IV
.define "PORT7_VECTOR", LEDP_Vector
.elseif (Board_LedPort == 8)
LEDP_DIN: .equ P8IN
LEDP_DOUT: .equ P8OUT
LEDP_DIR: .equ P8DIR
LEDP_REN: .equ P8REN
LEDP_SEL0: .equ P8SEL0
LEDP_SEL1: .equ P8SEL1
LEDP_INTE: .equ P8IE
LEDP_INTES: .equ P8IES
LEDP_INTF: .equ P8IFG
LEDP_INTV: .equ P8IV
.define "PORT8_VECTOR", LEDP_Vector
.else
.emsg "Board_LedPort definition in Board.h43 file has to be between 1 and 8"
.endif ;Board_LedPort
;Now lets define the registers of the "Group Selector" port.
; Not all of the registers are used, but they are set here for completeness
.if (Board_ComCtlPort == 1)
LEDC_DIN: .equ P1IN ;Data input register of led groups
LEDC_DOUT: .equ P1OUT ;Data output register for led groups
LEDC_DIR: .equ P1DIR ;Direction selection register for groups
LEDC_REN: .equ P1REN ;Resistor setup register for group pins
LEDC_SEL0: .equ P1SEL0 ;Special function selection registers
LEDC_SEL1: .equ P1SEL1
LEDC_INTE: .equ P1IE ;Interrupt enable register for led groups
LEDC_INTES: .equ P1IES ;Interrupt edge selector register
LEDC_INTF: .equ P1IFG ;Interrupt flags register
LEDC_INTV: .equ P1IV ;Interrupt vector register
.define "PORT1_VECTOR", LEDC_Vector ;Interrupt Vector Memory Segment
.elseif (Board_ComCtlPort == 2)
LEDC_DIN: .equ P2IN
LEDC_DOUT: .equ P2OUT
LEDC_DIR: .equ P2DIR
LEDC_REN: .equ P2REN
LEDC_SEL0: .equ P2SEL0
LEDC_SEL1: .equ P2SEL1
LEDC_INTE: .equ P2IE
LEDC_INTES: .equ P2IES
LEDC_INTF: .equ P2IFG
LEDC_INTV: .equ P2IV
.define "PORT2_VECTOR", LEDC_Vector
.elseif (Board_ComCtlPort == 3)
LEDC_DIN: .equ P3IN
LEDC_DOUT: .equ P3OUT
LEDC_DIR: .equ P3DIR
LEDC_REN: .equ P3REN
LEDC_SEL0: .equ P3SEL0
LEDC_SEL1: .equ P3SEL1
LEDC_INTE: .equ P3IE
LEDC_INTES: .equ P3IES
LEDC_INTF: .equ P3IFG
LEDC_INTV: .equ P3IV
.define "PORT3_VECTOR", LEDC_Vector
.elseif (Board_ComCtlPort == 4)
LEDC_DIN: .equ P4IN
LEDC_DOUT: .equ P4OUT
LEDC_DIR: .equ P4DIR
LEDC_REN: .equ P4REN
LEDC_SEL0: .equ P4SEL0
LEDC_SEL1: .equ P4SEL1
LEDC_INTE: .equ P4IE
LEDC_INTES: .equ P4IES
LEDC_INTF: .equ P4IFG
LEDC_INTV: .equ P4IV
.define "PORT4_VECTOR", LEDC_Vector
.elseif (Board_ComCtlPort == 5)
LEDC_DIN: .equ P5IN
LEDC_DOUT: .equ P5OUT
LEDC_DIR: .equ P5DIR
LEDC_REN: .equ P5REN
LEDC_SEL0: .equ P5SEL0
LEDC_SEL1: .equ P5SEL1
LEDC_INTE: .equ P5IE
LEDC_INTES: .equ P5IES
LEDC_INTF: .equ P5IFG
LEDC_INTV: .equ P5IV
.define "PORT5_VECTOR", LEDC_Vector
.elseif (Board_ComCtlPort == 6)
LEDC_DIN: .equ P6IN
LEDC_DOUT: .equ P6OUT
LEDC_DIR: .equ P6DIR
LEDC_REN: .equ P6REN
LEDC_SEL0: .equ P6SEL0
LEDC_SEL1: .equ P6SEL1
LEDC_INTE: .equ P6IE
LEDC_INTES: .equ P6IES
LEDC_INTF: .equ P6IFG
LEDC_INTV: .equ P6IV
.define "PORT6_VECTOR", LEDC_Vector
.elseif (Board_ComCtlPort == 7)
LEDC_DIN: .equ P7IN
LEDC_DOUT: .equ P7OUT
LEDC_DIR: .equ P7DIR
LEDC_REN: .equ P7REN
LEDC_SEL0: .equ P7SEL0
LEDC_SEL1: .equ P7SEL1
LEDC_INTE: .equ P7IE
LEDC_INTES: .equ P7IES
LEDC_INTF: .equ P7IFG
LEDC_INTV: .equ P7IV
.define "PORT7_VECTOR", LEDC_Vector
.elseif (Board_ComCtlPort == 8)
LEDC_DIN: .equ P8IN
LEDC_DOUT: .equ P8OUT
LEDC_DIR: .equ P8DIR
LEDC_REN: .equ P8REN
LEDC_SEL0: .equ P8SEL0
LEDC_SEL1: .equ P8SEL1
LEDC_INTE: .equ P8IE
LEDC_INTES: .equ P8IES
LEDC_INTF: .equ P8IFG
LEDC_INTV: .equ P8IV
.define "PORT8_VECTOR", LEDC_Vector
.else
.emsg "Board_ComCtlPort definition in Board.h43 file has to be between 1 and 8"
.endif ;Board_ComCtlPort
;Now lets define the registers for the "No Scanning" leds.
; Not all of the registers are used, but they are set here for completeness
.if (Board_NoScanLedPort == 1)
LEDNS_DIN: .equ P1IN ;Data input register of No-Scan leds
LEDNS_DOUT: .equ P1OUT ;Data output register for
LEDNS_DIR: .equ P1DIR ;Direction selection register for No-Scan
; leds
LEDNS_REN: .equ P1REN ;Resistor setup register for No-Scan leds
LEDNS_SEL0: .equ P1SEL0 ;Special function selection registers
LEDNS_SEL1: .equ P1SEL1
LEDNS_INTE: .equ P1IE ;Interrupt enable register for led groups
LEDNS_INTES: .equ P1IES ;Interrupt edge selector register
LEDNS_INTF: .equ P1IFG ;Interrupt flags register
LEDNS_INTV: .equ P1IV ;Interrupt vector register
.define "PORT1_VECTOR", LEDNS_Vector;Interrupt Vector Memory Segment
.elseif (Board_NoScanLedPort == 2)
LEDNS_DIN: .equ P2IN
LEDNS_DOUT: .equ P2OUT
LEDNS_DIR: .equ P2DIR
LEDNS_REN: .equ P2REN
LEDNS_SEL0: .equ P2SEL0
LEDNS_SEL1: .equ P2SEL1
LEDNS_INTE: .equ P2IE
LEDNS_INTES: .equ P2IES
LEDNS_INTF: .equ P2IFG
LEDNS_INTV: .equ P2IV
.define "PORT2_VECTOR", LEDNS_Vector
.elseif (Board_NoScanLedPort == 3)
LEDNS_DIN: .equ P3IN
LEDNS_DOUT: .equ P3OUT
LEDNS_DIR: .equ P3DIR
LEDNS_REN: .equ P3REN
LEDNS_SEL0: .equ P3SEL0
LEDNS_SEL1: .equ P3SEL1
LEDNS_INTE: .equ P3IE
LEDNS_INTES: .equ P3IES
LEDNS_INTF: .equ P3IFG
LEDNS_INTV: .equ P3IV
.define "PORT3_VECTOR", LEDNS_Vector
.elseif (Board_NoScanLedPort == 4)
LEDNS_DIN: .equ P4IN
LEDNS_DOUT: .equ P4OUT
LEDNS_DIR: .equ P4DIR
LEDNS_REN: .equ P4REN
LEDNS_SEL0: .equ P4SEL0
LEDNS_SEL1: .equ P4SEL1
LEDNS_INTE: .equ P4IE
LEDNS_INTES: .equ P4IES
LEDNS_INTF: .equ P4IFG
LEDNS_INTV: .equ P4IV
.define "PORT4_VECTOR", LEDNS_Vector
.elseif (Board_NoScanLedPort == 5)
LEDNS_DIN: .equ P5IN
LEDNS_DOUT: .equ P5OUT
LEDNS_DIR: .equ P5DIR
LEDNS_REN: .equ P5REN
LEDNS_SEL0: .equ P5SEL0
LEDNS_SEL1: .equ P5SEL1
LEDNS_INTE: .equ P5IE
LEDNS_INTES: .equ P5IES
LEDNS_INTF: .equ P5IFG
LEDNS_INTV: .equ P5IV
.define "PORT5_VECTOR", LEDNS_Vector
.elseif (Board_NoScanLedPort == 6)
LEDNS_DIN: .equ P6IN
LEDNS_DOUT: .equ P6OUT
LEDNS_DIR: .equ P6DIR
LEDNS_REN: .equ P6REN
LEDNS_SEL0: .equ P6SEL0
LEDNS_SEL1: .equ P6SEL1
LEDNS_INTE: .equ P6IE
LEDNS_INTES: .equ P6IES
LEDNS_INTF: .equ P6IFG
LEDNS_INTV: .equ P6IV
.define "PORT6_VECTOR", LEDNS_Vector
.elseif (Board_NoScanLedPort == 7)
LEDNS_DIN: .equ P7IN
LEDNS_DOUT: .equ P7OUT
LEDNS_DIR: .equ P7DIR
LEDNS_REN: .equ P7REN
LEDNS_SEL0: .equ P7SEL0
LEDNS_SEL1: .equ P7SEL1
LEDNS_INTE: .equ P7IE
LEDNS_INTES: .equ P7IES
LEDNS_INTF: .equ P7IFG
LEDNS_INTV: .equ P7IV
.define "PORT7_VECTOR", LEDNS_Vector
.elseif (Board_NoScanLedPort == 8)
LEDNS_DIN: .equ P8IN
LEDNS_DOUT: .equ P8OUT
LEDNS_DIR: .equ P8DIR
LEDNS_REN: .equ P8REN
LEDNS_SEL0: .equ P8SEL0
LEDNS_SEL1: .equ P8SEL1
LEDNS_INTE: .equ P8IE
LEDNS_INTES: .equ P8IES
LEDNS_INTF: .equ P8IFG
LEDNS_INTV: .equ P8IV
.define "PORT8_VECTOR", LEDNS_Vector
.else
.emsg "Board_NoScanLedPort definition in Board.h43 file has to be between 1 and 8"
.endif ;Board_NoScanLedPort
;----------------------------------------
; Buzzer Definitions
;========================================
;The Buzzer is a very simple peripheral. Just trigger it for a short time and you have a beep.
; Here we create its port definitions. Not all registers are used in the program but they are
; defined here for completeness.
.if (Board_BuzzerPort == 1)
BUZZP_DIN: .equ P1IN ;Data input register
BUZZP_DOUT: .equ P1OUT ;Data output register for triggering Buzz
BUZZP_DIR: .equ P1DIR ;Direction selection register
BUZZP_REN: .equ P1REN ;Resistor setup register
BUZZP_SEL0: .equ P1SEL0 ;Special function selection registers
BUZZP_SEL1: .equ P1SEL1
BUZZP_INTE: .equ P1IE ;Interrupt enable register
BUZZP_INTES: .equ P1IES ;Interrupt edge selector register
BUZZP_INTF: .equ P1IFG ;Interrupt flags register
BUZZP_INTV: .equ P1IV ;Interrupt vector register
.define "PORT1_VECTOR", BUZZP_Vector;Interrupt Vector Memory Segment
.elseif (Board_BuzzerPort == 2)
BUZZP_DIN: .equ P2IN
BUZZP_DOUT: .equ P2OUT
BUZZP_DIR: .equ P2DIR
BUZZP_REN: .equ P2REN
BUZZP_SEL0: .equ P2SEL0
BUZZP_SEL1: .equ P2SEL1
BUZZP_INTE: .equ P2IE
BUZZP_INTES: .equ P2IES
BUZZP_INTF: .equ P2IFG
BUZZP_INTV: .equ P2IV
.define "PORT2_VECTOR", BUZZP_Vector
.elseif (Board_BuzzerPort == 3)
BUZZP_DIN: .equ P3IN
BUZZP_DOUT: .equ P3OUT
BUZZP_DIR: .equ P3DIR
BUZZP_REN: .equ P3REN
BUZZP_SEL0: .equ P3SEL0
BUZZP_SEL1: .equ P3SEL1
BUZZP_INTE: .equ P3IE
BUZZP_INTES: .equ P3IES
BUZZP_INTF: .equ P3IFG
BUZZP_INTV: .equ P3IV
.define "PORT3_VECTOR", BUZZP_Vector
.elseif (Board_BuzzerPort == 4)
BUZZP_DIN: .equ P4IN
BUZZP_DOUT: .equ P4OUT
BUZZP_DIR: .equ P4DIR
BUZZP_REN: .equ P4REN
BUZZP_SEL0: .equ P4SEL0
BUZZP_SEL1: .equ P4SEL1
BUZZP_INTE: .equ P4IE
BUZZP_INTES: .equ P4IES
BUZZP_INTF: .equ P4IFG
BUZZP_INTV: .equ P4IV
.define "PORT4_VECTOR", BUZZP_Vector
.elseif (Board_BuzzerPort == 5)
BUZZP_DIN: .equ P5IN
BUZZP_DOUT: .equ P5OUT
BUZZP_DIR: .equ P5DIR
BUZZP_REN: .equ P5REN
BUZZP_SEL0: .equ P5SEL0
BUZZP_SEL1: .equ P5SEL1
BUZZP_INTE: .equ P5IE
BUZZP_INTES: .equ P5IES
BUZZP_INTF: .equ P5IFG
BUZZP_INTV: .equ P5IV
.define "PORT5_VECTOR", BUZZP_Vector
.elseif (Board_BuzzerPort == 6)
BUZZP_DIN: .equ P6IN
BUZZP_DOUT: .equ P6OUT
BUZZP_DIR: .equ P6DIR
BUZZP_REN: .equ P6REN
BUZZP_SEL0: .equ P6SEL0
BUZZP_SEL1: .equ P6SEL1
BUZZP_INTE: .equ P6IE
BUZZP_INTES: .equ P6IES
BUZZP_INTF: .equ P6IFG
BUZZP_INTV: .equ P6IV
.define "PORT6_VECTOR", BUZZP_Vector
.elseif (Board_BuzzerPort == 7)
BUZZP_DIN: .equ P7IN
BUZZP_DOUT: .equ P7OUT
BUZZP_DIR: .equ P7DIR
BUZZP_REN: .equ P7REN
BUZZP_SEL0: .equ P7SEL0
BUZZP_SEL1: .equ P7SEL1
BUZZP_INTE: .equ P7IE
BUZZP_INTES: .equ P7IES
BUZZP_INTF: .equ P7IFG
BUZZP_INTV: .equ P7IV
.define "PORT7_VECTOR", BUZZP_Vector
.elseif (Board_BuzzerPort == 8)
BUZZP_DIN: .equ P8IN
BUZZP_DOUT: .equ P8OUT
BUZZP_DIR: .equ P8DIR
BUZZP_REN: .equ P8REN
BUZZP_SEL0: .equ P8SEL0
BUZZP_SEL1: .equ P8SEL1
BUZZP_INTE: .equ P8IE
BUZZP_INTES: .equ P8IES
BUZZP_INTF: .equ P8IFG
BUZZP_INTV: .equ P8IV
.define "PORT8_VECTOR", BUZZP_Vector
.else
.emsg "Board_BuzzerPort definition in Board.h43 file has to be between 1 and 8"
.endif ;Board_BuzzerPort
;----------------------------------------
; Relays Definitions
;========================================
;In the system there are four relays that power up the high current loads. Here are the
; definitions that define the port registers according to the selected by the Board.h43
; definitions.
; Not all of the registers are used, but they are set here for completeness
.if (Board_RelPort == 1)
RELP_DIN: .equ P1IN ;Data input register
RELP_DOUT: .equ P1OUT ;Data output register for enabling relays
RELP_DIR: .equ P1DIR ;Direction selection register
RELP_REN: .equ P1REN ;Resistor setup register
RELP_SEL0: .equ P1SEL0 ;Special function selection registers
RELP_SEL1: .equ P1SEL1
RELP_INTE: .equ P1IE ;Interrupt enable register
RELP_INTES: .equ P1IES ;Interrupt edge selector register
RELP_INTF: .equ P1IFG ;Interrupt flags register
RELP_INTV: .equ P1IV ;Interrupt vector register
.define "PORT1_VECTOR", RELP_Vector;Interrupt Vector Memory Segment
.elseif (Board_RelPort == 2)
RELP_DIN: .equ P2IN
RELP_DOUT: .equ P2OUT
RELP_DIR: .equ P2DIR
RELP_REN: .equ P2REN
RELP_SEL0: .equ P2SEL0
RELP_SEL1: .equ P2SEL1
RELP_INTE: .equ P2IE
RELP_INTES: .equ P2IES
RELP_INTF: .equ P2IFG
RELP_INTV: .equ P2IV
.define "PORT2_VECTOR", RELP_Vector
.elseif (Board_RelPort == 3)
RELP_DIN: .equ P3IN
RELP_DOUT: .equ P3OUT
RELP_DIR: .equ P3DIR
RELP_REN: .equ P3REN
RELP_SEL0: .equ P3SEL0
RELP_SEL1: .equ P3SEL1
RELP_INTE: .equ P3IE
RELP_INTES: .equ P3IES
RELP_INTF: .equ P3IFG
RELP_INTV: .equ P3IV
.define "PORT3_VECTOR", RELP_Vector
.elseif (Board_RelPort == 4)
RELP_DIN: .equ P4IN
RELP_DOUT: .equ P4OUT
RELP_DIR: .equ P4DIR
RELP_REN: .equ P4REN
RELP_SEL0: .equ P4SEL0
RELP_SEL1: .equ P4SEL1
RELP_INTE: .equ P4IE
RELP_INTES: .equ P4IES
RELP_INTF: .equ P4IFG
RELP_INTV: .equ P4IV
.define "PORT4_VECTOR", RELP_Vector
.elseif (Board_RelPort == 5)
RELP_DIN: .equ P5IN
RELP_DOUT: .equ P5OUT
RELP_DIR: .equ P5DIR
RELP_REN: .equ P5REN
RELP_SEL0: .equ P5SEL0
RELP_SEL1: .equ P5SEL1
RELP_INTE: .equ P5IE
RELP_INTES: .equ P5IES
RELP_INTF: .equ P5IFG
RELP_INTV: .equ P5IV
.define "PORT5_VECTOR", RELP_Vector
.elseif (Board_RelPort == 6)
RELP_DIN: .equ P6IN
RELP_DOUT: .equ P6OUT
RELP_DIR: .equ P6DIR
RELP_REN: .equ P6REN
RELP_SEL0: .equ P6SEL0
RELP_SEL1: .equ P6SEL1
RELP_INTE: .equ P6IE
RELP_INTES: .equ P6IES
RELP_INTF: .equ P6IFG
RELP_INTV: .equ P6IV
.define "PORT6_VECTOR", RELP_Vector
.elseif (Board_RelPort == 7)
RELP_DIN: .equ P7IN
RELP_DOUT: .equ P7OUT
RELP_DIR: .equ P7DIR
RELP_REN: .equ P7REN
RELP_SEL0: .equ P7SEL0
RELP_SEL1: .equ P7SEL1
RELP_INTE: .equ P7IE
RELP_INTES: .equ P7IES
RELP_INTF: .equ P7IFG
RELP_INTV: .equ P7IV
.define "PORT7_VECTOR", RELP_Vector
.elseif (Board_RelPort == 8)
RELP_DIN: .equ P8IN
RELP_DOUT: .equ P8OUT
RELP_DIR: .equ P8DIR
RELP_REN: .equ P8REN
RELP_SEL0: .equ P8SEL0
RELP_SEL1: .equ P8SEL1
RELP_INTE: .equ P8IE
RELP_INTES: .equ P8IES
RELP_INTF: .equ P8IFG
RELP_INTV: .equ P8IV
.define "PORT8_VECTOR", RELP_Vector
.else
.emsg "Board_RelPort definition in Board.h43 file has to be between 1 and 8"
.endif ;Board_RelPort
;----------------------------------------
; NTC Definitions
;========================================
;The NTC sensor is placed on the compressor's cooler to monitor its temperature. In order to
; minimize the autoheating effect, it is controlled by an I/O that enables the sensor divider
; and another input to ADC module to measure its temperature.
;The following definition set is for setting the port registers according to selections made
; in Board.h43 file
.if (Board_NTCPort == 1)
NTCP_DIN: .equ P1IN ;Data input register
NTCP_DOUT: .equ P1OUT ;Data output register for enabling NTC
NTCP_DIR: .equ P1DIR ;Direction selection register
NTCP_REN: .equ P1REN ;Resistor setup register
NTCP_SEL0: .equ P1SEL0 ;Special function selection registers
NTCP_SEL1: .equ P1SEL1
NTCP_INTE: .equ P1IE ;Interrupt enable register
NTCP_INTES: .equ P1IES ;Interrupt edge selector register
NTCP_INTF: .equ P1IFG ;Interrupt flags register
NTCP_INTV: .equ P1IV ;Interrupt vector register
.define "PORT1_VECTOR", NTCP_Vector ;Interrupt Vector Memory Segment
.elseif (Board_NTCPort == 2)
NTCP_DIN: .equ P2IN
NTCP_DOUT: .equ P2OUT
NTCP_DIR: .equ P2DIR
NTCP_REN: .equ P2REN
NTCP_SEL0: .equ P2SEL0
NTCP_SEL1: .equ P2SEL1
NTCP_INTE: .equ P2IE
NTCP_INTES: .equ P2IES
NTCP_INTF: .equ P2IFG
NTCP_INTV: .equ P2IV
.define "PORT2_VECTOR", NTCP_Vector
.elseif (Board_NTCPort == 3)
NTCP_DIN: .equ P3IN
NTCP_DOUT: .equ P3OUT
NTCP_DIR: .equ P3DIR
NTCP_REN: .equ P3REN
NTCP_SEL0: .equ P3SEL0
NTCP_SEL1: .equ P3SEL1
NTCP_INTE: .equ P3IE
NTCP_INTES: .equ P3IES
NTCP_INTF: .equ P3IFG
NTCP_INTV: .equ P3IV
.define "PORT3_VECTOR", NTCP_Vector
.elseif (Board_NTCPort == 4)
NTCP_DIN: .equ P4IN
NTCP_DOUT: .equ P4OUT
NTCP_DIR: .equ P4DIR
NTCP_REN: .equ P4REN
NTCP_SEL0: .equ P4SEL0
NTCP_SEL1: .equ P4SEL1
NTCP_INTE: .equ P4IE
NTCP_INTES: .equ P4IES
NTCP_INTF: .equ P4IFG
NTCP_INTV: .equ P4IV
.define "PORT4_VECTOR", NTCP_Vector
.elseif (Board_NTCPort == 5)
NTCP_DIN: .equ P5IN
NTCP_DOUT: .equ P5OUT
NTCP_DIR: .equ P5DIR
NTCP_REN: .equ P5REN
NTCP_SEL0: .equ P5SEL0
NTCP_SEL1: .equ P5SEL1
NTCP_INTE: .equ P5IE
NTCP_INTES: .equ P5IES
NTCP_INTF: .equ P5IFG
NTCP_INTV: .equ P5IV
.define "PORT5_VECTOR", NTCP_Vector
.elseif (Board_NTCPort == 6)
NTCP_DIN: .equ P6IN
NTCP_DOUT: .equ P6OUT
NTCP_DIR: .equ P6DIR
NTCP_REN: .equ P6REN
NTCP_SEL0: .equ P6SEL0
NTCP_SEL1: .equ P6SEL1
NTCP_INTE: .equ P6IE
NTCP_INTES: .equ P6IES
NTCP_INTF: .equ P6IFG
NTCP_INTV: .equ P6IV
.define "PORT6_VECTOR", NTCP_Vector
.elseif (Board_NTCPort == 7)
NTCP_DIN: .equ P7IN
NTCP_DOUT: .equ P7OUT
NTCP_DIR: .equ P7DIR
NTCP_REN: .equ P7REN
NTCP_SEL0: .equ P7SEL0
NTCP_SEL1: .equ P7SEL1
NTCP_INTE: .equ P7IE
NTCP_INTES: .equ P7IES
NTCP_INTF: .equ P7IFG
NTCP_INTV: .equ P7IV
.define "PORT7_VECTOR", NTCP_Vector
.elseif (Board_NTCPort == 8)
NTCP_DIN: .equ P8IN
NTCP_DOUT: .equ P8OUT
NTCP_DIR: .equ P8DIR
NTCP_REN: .equ P8REN
NTCP_SEL0: .equ P8SEL0
NTCP_SEL1: .equ P8SEL1
NTCP_INTE: .equ P8IE
NTCP_INTES: .equ P8IES
NTCP_INTF: .equ P8IFG
NTCP_INTV: .equ P8IV
.define "PORT8_VECTOR", NTCP_Vector
.else
.emsg "Board_NTCPort definition in Board.h43 file has to be between 1 and 8"
.endif ;Board_NTCPort
;The following definitions are for the ADC channel and I/O pin the selected ADC channel is
; multiplexed
.if (Board_NTCChannel == 0)
NTCA_DIN: .equ P1IN ;Data Input Register
NTCA_DOUT: .equ P1OUT ;Data output register for enabling NTC
NTCA_DIR: .equ P1DIR ;Direction selection register
NTCA_REN: .equ P1REN ;Resistor setup register
NTCA_SEL0: .equ P1SEL0 ;Special function selection registers
NTCA_SEL1: .equ P1SEL1
NTCA_INTE: .equ P1IE ;Interrupt enable register
NTCA_INTES: .equ P1IES ;Interrupt edge selector register
NTCA_INTF: .equ P1IFG ;Interrupt flags register
NTCA_INTV: .equ P1IV ;Interrupt vector register
.define "PORT1_VECTOR", NTCA_Vector ;Interrupt Vector Memory Segment
NTCA_PMASK: .equ BIT0 ;Pin in the NTCA Port the Analog Input is
NTCA_IEMASK: .equ ADC12IE0 ;Associated Interrupt Enable of ADC
NTCA_IFGMASK: .equ ADC12IFG0 ;Associated Interrupt Flag of ADC
NTCA_IEREG: .equ ADC12IER0 ;Associated Interrupt Enable register
NTCA_IFGREG: .equ ADC12IFGR0 ;Associated Interrupt Flag register
.elseif (Board_NTCChannel == 1)
NTCA_DIN: .equ P1IN
NTCA_DOUT: .equ P1OUT
NTCA_DIR: .equ P1DIR
NTCA_REN: .equ P1REN
NTCA_SEL0: .equ P1SEL0
NTCA_SEL1: .equ P1SEL1
NTCA_INTE: .equ P1IE
NTCA_INTES: .equ P1IES
NTCA_INTF: .equ P1IFG
NTCA_INTV: .equ P1IV
.define "PORT1_VECTOR", NTCA_Vector
NTCA_PMASK: .equ BIT1
NTCA_IEMASK: .equ ADC12IE1
NTCA_IFGMASK: .equ ADC12IFG1
NTCA_IEREG: .equ ADC12IER0
NTCA_IFGREG: .equ ADC12IFGR0
.elseif (Board_NTCChannel == 2)
NTCA_DIN: .equ P1IN
NTCA_DOUT: .equ P1OUT
NTCA_DIR: .equ P1DIR
NTCA_REN: .equ P1REN
NTCA_SEL0: .equ P1SEL0
NTCA_SEL1: .equ P1SEL1
NTCA_INTE: .equ P1IE
NTCA_INTES: .equ P1IES
NTCA_INTF: .equ P1IFG
NTCA_INTV: .equ P1IV
.define "PORT1_VECTOR", NTCA_Vector
NTCA_PMASK: .equ BIT2
NTCA_IEMASK: .equ ADC12IE2
NTCA_IFGMASK: .equ ADC12IFG2
NTCA_IEREG: .equ ADC12IER0
NTCA_IFGREG: .equ ADC12IFGR0
.elseif (Board_NTCChannel == 3)
NTCA_DIN: .equ P1IN
NTCA_DOUT: .equ P1OUT
NTCA_DIR: .equ P1DIR
NTCA_REN: .equ P1REN
NTCA_SEL0: .equ P1SEL0
NTCA_SEL1: .equ P1SEL1
NTCA_INTE: .equ P1IE
NTCA_INTES: .equ P1IES
NTCA_INTF: .equ P1IFG
NTCA_INTV: .equ P1IV
.define "PORT1_VECTOR", NTCA_Vector
NTCA_PMASK: .equ BIT3
NTCA_IEMASK: .equ ADC12IE3
NTCA_IFGMASK: .equ ADC12IFG3
NTCA_IEREG: .equ ADC12IER0
NTCA_IFGREG: .equ ADC12IFGR0
.elseif (Board_NTCChannel == 4)
NTCA_DIN: .equ P1IN
NTCA_DOUT: .equ P1OUT
NTCA_DIR: .equ P1DIR
NTCA_REN: .equ P1REN
NTCA_SEL0: .equ P1SEL0
NTCA_SEL1: .equ P1SEL1
NTCA_INTE: .equ P1IE
NTCA_INTES: .equ P1IES
NTCA_INTF: .equ P1IFG
NTCA_INTV: .equ P1IV
.define "PORT1_VECTOR", NTCA_Vector
NTCA_PMASK: .equ BIT4
NTCA_IEMASK: .equ ADC12IE4
NTCA_IFGMASK: .equ ADC12IFG4
NTCA_IEREG: .equ ADC12IER0
NTCA_IFGREG: .equ ADC12IFGR0
.elseif (Board_NTCChannel == 5)
NTCA_DIN: .equ P1IN
NTCA_DOUT: .equ P1OUT
NTCA_DIR: .equ P1DIR
NTCA_REN: .equ P1REN
NTCA_SEL0: .equ P1SEL0
NTCA_SEL1: .equ P1SEL1
NTCA_INTE: .equ P1IE
NTCA_INTES: .equ P1IES
NTCA_INTF: .equ P1IFG
NTCA_INTV: .equ P1IV
.define "PORT1_VECTOR", NTCA_Vector
NTCA_PMASK: .equ BIT5
NTCA_IEMASK: .equ ADC12IE5
NTCA_IFGMASK: .equ ADC12IFG5
NTCA_IEREG: .equ ADC12IER0
NTCA_IFGREG: .equ ADC12IFGR0
.elseif (Board_NTCChannel == 6)
NTCA_DIN: .equ P2IN
NTCA_DOUT: .equ P2OUT
NTCA_DIR: .equ P2DIR
NTCA_REN: .equ P2REN
NTCA_SEL0: .equ P2SEL0
NTCA_SEL1: .equ P2SEL1
NTCA_INTE: .equ P2IE
NTCA_INTES: .equ P2IES
NTCA_INTF: .equ P2IFG
NTCA_INTV: .equ P2IV
.define "PORT2_VECTOR", NTCA_Vector
NTCA_PMASK: .equ BIT3
NTCA_IEMASK: .equ ADC12IE6
NTCA_IFGMASK: .equ ADC12IFG6
NTCA_IEREG: .equ ADC12IER0
NTCA_IFGREG: .equ ADC12IFGR0
.elseif (Board_NTCChannel == 7)
NTCA_DIN: .equ P2IN
NTCA_DOUT: .equ P2OUT
NTCA_DIR: .equ P2DIR
NTCA_REN: .equ P2REN
NTCA_SEL0: .equ P2SEL0
NTCA_SEL1: .equ P2SEL1
NTCA_INTE: .equ P2IE
NTCA_INTES: .equ P2IES
NTCA_INTF: .equ P2IFG
NTCA_INTV: .equ P2IV
.define "PORT2_VECTOR", NTCA_Vector
NTCA_PMASK: .equ BIT4
NTCA_IEMASK: .equ ADC12IE7
NTCA_IFGMASK: .equ ADC12IFG7
NTCA_IEREG: .equ ADC12IER0
NTCA_IFGREG: .equ ADC12IFGR0
.elseif (Board_NTCChannel == 8)
NTCA_DIN: .equ P4IN
NTCA_DOUT: .equ P4OUT
NTCA_DIR: .equ P4DIR
NTCA_REN: .equ P4REN
NTCA_SEL0: .equ P4SEL0
NTCA_SEL1: .equ P4SEL1
NTCA_INTE: .equ P4IE
NTCA_INTES: .equ P4IES
NTCA_INTF: .equ P4IFG
NTCA_INTV: .equ P4IV
.define "PORT4_VECTOR", NTCA_Vector
NTCA_PMASK: .equ BIT0
NTCA_IEMASK: .equ ADC12IE8
NTCA_IFGMASK: .equ ADC12IFG8
NTCA_IEREG: .equ ADC12IER0
NTCA_IFGREG: .equ ADC12IFGR0
.elseif (Board_NTCChannel == 9)
NTCA_DIN: .equ P4IN
NTCA_DOUT: .equ P4OUT
NTCA_DIR: .equ P4DIR
NTCA_REN: .equ P4REN
NTCA_SEL0: .equ P4SEL0
NTCA_SEL1: .equ P4SEL1
NTCA_INTE: .equ P4IE
NTCA_INTES: .equ P4IES
NTCA_INTF: .equ P4IFG
NTCA_INTV: .equ P4IV
.define "PORT4_VECTOR", NTCA_Vector
NTCA_PMASK: .equ BIT1
NTCA_IEMASK: .equ ADC12IE9
NTCA_IFGMASK: .equ ADC12IFG9
NTCA_IEREG: .equ ADC12IER0
NTCA_IFGREG: .equ ADC12IFGR0
.elseif (Board_NTCChannel == 10)
NTCA_DIN: .equ P4IN
NTCA_DOUT: .equ P4OUT
NTCA_DIR: .equ P4DIR
NTCA_REN: .equ P4REN
NTCA_SEL0: .equ P4SEL0
NTCA_SEL1: .equ P4SEL1
NTCA_INTE: .equ P4IE
NTCA_INTES: .equ P4IES
NTCA_INTF: .equ P4IFG
NTCA_INTV: .equ P4IV
.define "PORT4_VECTOR", NTCA_Vector
NTCA_PMASK: .equ BIT2
NTCA_IEMASK: .equ ADC12IE10
NTCA_IFGMASK: .equ ADC12IFG10
NTCA_IEREG: .equ ADC12IER0
NTCA_IFGREG: .equ ADC12IFGR0
.elseif (Board_NTCChannel == 11)
NTCA_DIN: .equ P4IN
NTCA_DOUT: .equ P4OUT
NTCA_DIR: .equ P4DIR
NTCA_REN: .equ P4REN
NTCA_SEL0: .equ P4SEL0
NTCA_SEL1: .equ P4SEL1
NTCA_INTE: .equ P4IE
NTCA_INTES: .equ P4IES
NTCA_INTF: .equ P4IFG
NTCA_INTV: .equ P4IV
.define "PORT4_VECTOR", NTCA_Vector
NTCA_PMASK: .equ BIT3
NTCA_IEMASK: .equ ADC12IE11
NTCA_IFGMASK: .equ ADC12IFG11
NTCA_IEREG: .equ ADC12IER0
NTCA_IFGREG: .equ ADC12IFGR0
.elseif (Board_NTCChannel == 12)
NTCA_DIN: .equ P3IN
NTCA_DOUT: .equ P3OUT
NTCA_DIR: .equ P3DIR
NTCA_REN: .equ P3REN
NTCA_SEL0: .equ P3SEL0
NTCA_SEL1: .equ P3SEL1