From de6df6be9e618ffe1a22a9cb28870ab15297181c Mon Sep 17 00:00:00 2001
From: Arturo Buzarra <arturo.buzarra@digi.com>
Date: Thu, 2 Mar 2023 14:20:06 +0100
Subject: [PATCH] ARM: dts: ccmp13-dvk: set 10/100 Ethernet PHY on shared MDIO1
 bus

The CCMP13 DVK board shares the MDIO bus #1 for both Ethernet PHYs,
so this commit reflects this with the following changes:

- Move the eth2 PHY definition to the mdio1 bus node
- Free the MDIO bus #2 lines (ETH2_MDIO and ETH2_MDC)
- Add support to the interrupt line for second Ethernet PHY
- Enable by default both Ethernet PHYs

https://onedigi.atlassian.net/browse/DEL-8338

Signed-off-by: Arturo Buzarra <arturo.buzarra@digi.com>
---
 arch/arm/dts/ccmp13-dvk.dts | 28 ++++++++++------------------
 1 file changed, 10 insertions(+), 18 deletions(-)

diff --git a/arch/arm/dts/ccmp13-dvk.dts b/arch/arm/dts/ccmp13-dvk.dts
index b9169668623..222003ee693 100644
--- a/arch/arm/dts/ccmp13-dvk.dts
+++ b/arch/arm/dts/ccmp13-dvk.dts
@@ -104,12 +104,20 @@
 			reset-assert-us = <1000>;
 			reset-deassert-us = <2000>;
 		};
+
+		phy0_eth2: ethernet-phy@1 {
+			reg = <1>;
+			compatible = "ethernet-phy-id0007.c0f0"; /* PHY ID for SMSC LAN8720Ai */
+			reset-gpios = <&gpioh 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			interrupt-parent = <&gpioh>;
+			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+		};
 	};
 };
 
 /* 10/100 Ethernet */
 &eth2 {
-	status = "disabled";
+	status = "okay";
 	pinctrl-0 = <&ccmp13_eth2_rmii_pins>;
 	pinctrl-1 = <&ccmp13_eth2_rmii_sleep_pins>;
 	pinctrl-names = "default", "sleep";
@@ -118,18 +126,6 @@
 	phy-handle = <&phy0_eth2>;
 	st,ext-phyclk;
 	phy-supply = <&reg_3v3_eth_pwr>;
-
-	mdio1 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "snps,dwmac-mdio";
-
-		phy0_eth2: ethernet-phy@0 {
-			reg = <0>;
-			compatible = "ethernet-phy-id0007.c0f0"; /* PHY ID for SMSC LAN8720Ai */
-			reset-gpios = <&gpioh 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-		};
-	};
 };
 
 &i2c2 {
@@ -441,9 +437,7 @@
 			pinmux = <STM32_PINMUX('F', 7,  AF11)>, /* ETH2_TXD0 */
 				 <STM32_PINMUX('G', 11, AF10)>, /* ETH2_TXD1 */
 				 <STM32_PINMUX('A', 11, AF13)>, /* ETH2_CLK */
-				 <STM32_PINMUX('F', 6,  AF11)>, /* ETH2_TX_EN */
-				 <STM32_PINMUX('B', 2,  AF11)>, /* ETH2_MDIO */
-				 <STM32_PINMUX('G', 5,  AF10)>; /* ETH2_MDC */
+				 <STM32_PINMUX('F', 6,  AF11)>; /* ETH2_TX_EN */
 			bias-disable;
 			drive-push-pull;
 			slew-rate = <1>;
@@ -464,8 +458,6 @@
 				 <STM32_PINMUX('G', 11, ANALOG)>, /* ETH2_TXD1 */
 				 <STM32_PINMUX('A', 11, ANALOG)>, /* ETH2_CLK */
 				 <STM32_PINMUX('F', 6,  ANALOG)>, /* ETH2_TX_EN */
-				 <STM32_PINMUX('B', 2,  ANALOG)>, /* ETH2_MDIO */
-				 <STM32_PINMUX('G', 5,  ANALOG)>, /* ETH2_MDC */
 				 <STM32_PINMUX('F', 4,  ANALOG)>, /* ETH2_RXD0 */
 				 <STM32_PINMUX('E', 2,  ANALOG)>, /* ETH2_RXD1 */
 				 <STM32_PINMUX('A', 12, ANALOG)>, /* ETH2_RX_DV */