diff --git a/procs/riscy-lib/RVRFile.bsv b/procs/riscy-lib/RVRFile.bsv
index fc5511cf..43d5628b 100644
--- a/procs/riscy-lib/RVRFile.bsv
+++ b/procs/riscy-lib/RVRFile.bsv
@@ -34,7 +34,7 @@ interface ArchRFile;
 endinterface
 
 // This is a merged GPR/FPU register file
-(* synthesize *)
+(* synthesize, gate_all_clocks *)
 module mkArchRFile( ArchRFile );
     let verbose = False;
     File fout = stdout;
@@ -73,7 +73,7 @@ endmodule
 import RegUtil::*;
 
 // wr < {rd1, rd2, rd3}
-(* synthesize *)
+(* synthesize, gate_all_clocks *)
 module mkBypassArchRFile( ArchRFile );
     let verbose = False;
     File fout = stdout;
diff --git a/recycle-bsv-lib b/recycle-bsv-lib
index 2566ec1a..5dd4908d 160000
--- a/recycle-bsv-lib
+++ b/recycle-bsv-lib
@@ -1 +1 @@
-Subproject commit 2566ec1a053f41b81f9f511bbf2314885b571930
+Subproject commit 5dd4908d808563ca207867ae7dd435d54118bdea