From 88085a5f6bbb74cb434ff62bacc5912f41fb913b Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 17:38:10 +0530 Subject: [PATCH] migrate C-extension opcodes (major) - the previous opcodes used ignore to define immediate fields instead of assigning arg names to it. This is made it difficult to parse and decode the instructions. - this commit assigns unique names to immediate fields in accordance to what has been done elsewhere. Note these names hold no correspondence to the spec and are defined here purely to ease decoding - This commit also splits the instructions which depend on F/D/Q in to their respective files as per new naming convention - c.nop encoding has been changed to include hints as well. --- opcodes-rv32c | 5 ----- opcodes-rv64c | 14 -------------- opcodes-rvc | 46 ---------------------------------------------- rv128_c | 15 +++++++++++++++ rv32_c | 5 +++++ rv32_c_f | 8 ++++++++ rv64_c | 17 +++++++++++++++++ rv_c | 32 ++++++++++++++++++++++++++++++++ rv_c_d | 8 ++++++++ 9 files changed, 85 insertions(+), 65 deletions(-) delete mode 100644 opcodes-rv32c delete mode 100644 opcodes-rv64c delete mode 100644 opcodes-rvc create mode 100644 rv128_c create mode 100644 rv32_c create mode 100644 rv32_c_f create mode 100644 rv64_c create mode 100644 rv_c create mode 100644 rv_c_d diff --git a/opcodes-rv32c b/opcodes-rv32c deleted file mode 100644 index d91f2883..00000000 --- a/opcodes-rv32c +++ /dev/null @@ -1,5 +0,0 @@ -# RV32C additions to RVC - -@c.srli.rv32 1..0=1 15..13=4 12=0 11..10=0 9..2=ignore -@c.srai.rv32 1..0=1 15..13=4 12=0 11..10=1 9..2=ignore -@c.slli.rv32 1..0=2 15..13=0 12=0 11..2=ignore diff --git a/opcodes-rv64c b/opcodes-rv64c deleted file mode 100644 index 7efc7c5a..00000000 --- a/opcodes-rv64c +++ /dev/null @@ -1,14 +0,0 @@ -# RV64C additions to RVC - -# C0 encoding space -@c.ld 1..0=0 15..13=3 12=ignore 11..2=ignore # c.flw for RV32 -@c.sd 1..0=0 15..13=7 12=ignore 11..2=ignore # c.fsw for RV32 - -# C1 encoding space -c.subw 1..0=1 15..13=4 12=1 11..10=3 9..7=ignore 6..5=0 4..2=ignore -c.addw 1..0=1 15..13=4 12=1 11..10=3 9..7=ignore 6..5=1 4..2=ignore -@c.addiw 1..0=1 15..13=1 12=ignore 11..2=ignore # c.jal for RV32 - -# C2 encoding space -@c.ldsp 1..0=2 15..13=3 12=ignore 11..2=ignore # c.flwsp for RV32 -@c.sdsp 1..0=2 15..13=7 12=ignore 11..2=ignore # c.fswsp for RV32 diff --git a/opcodes-rvc b/opcodes-rvc deleted file mode 100644 index 64fc19a6..00000000 --- a/opcodes-rvc +++ /dev/null @@ -1,46 +0,0 @@ -# compressed instructions - -# these aren't really pseudo-ops, but they overlay other encodings, -# so they are here to prevent parse_opcodes from barfing - -@c.nop 1..0=1 15..13=0 12=0 11..7=0 6..2=0 -@c.addi16sp 1..0=1 15..13=3 12=ignore 11..7=2 6..2=ignore -@c.jr 1..0=2 15..13=4 12=0 11..7=ignore 6..2=0 -@c.jalr 1..0=2 15..13=4 12=1 11..7=ignore 6..2=0 -@c.ebreak 1..0=2 15..13=4 12=1 11..7=0 6..2=0 - -# C0 encoding space -c.addi4spn 1..0=0 15..13=0 12=ignore 11..2=ignore -c.fld 1..0=0 15..13=1 12=ignore 11..2=ignore # c.lq for RV128 -c.lw 1..0=0 15..13=2 12=ignore 11..2=ignore -c.flw 1..0=0 15..13=3 12=ignore 11..2=ignore # c.ld for RV64 -c.fsd 1..0=0 15..13=5 12=ignore 11..2=ignore # c.sq for RV128 -c.sw 1..0=0 15..13=6 12=ignore 11..2=ignore -c.fsw 1..0=0 15..13=7 12=ignore 11..2=ignore # c.sd for RV64 - -# C1 encoding space -c.addi 1..0=1 15..13=0 12=ignore 11..2=ignore -c.jal 1..0=1 15..13=1 12=ignore 11..2=ignore # c.addiw for RV64 -c.li 1..0=1 15..13=2 12=ignore 11..2=ignore -c.lui 1..0=1 15..13=3 12=ignore 11..2=ignore # c.addi16sp when rd=2 -c.srli 1..0=1 15..13=4 12=ignore 11..10=0 9..2=ignore -c.srai 1..0=1 15..13=4 12=ignore 11..10=1 9..2=ignore -c.andi 1..0=1 15..13=4 12=ignore 11..10=2 9..2=ignore -c.sub 1..0=1 15..13=4 12=0 11..10=3 9..7=ignore 6..5=0 4..2=ignore -c.xor 1..0=1 15..13=4 12=0 11..10=3 9..7=ignore 6..5=1 4..2=ignore -c.or 1..0=1 15..13=4 12=0 11..10=3 9..7=ignore 6..5=2 4..2=ignore -c.and 1..0=1 15..13=4 12=0 11..10=3 9..7=ignore 6..5=3 4..2=ignore -c.j 1..0=1 15..13=5 12=ignore 11..2=ignore -c.beqz 1..0=1 15..13=6 12=ignore 11..2=ignore -c.bnez 1..0=1 15..13=7 12=ignore 11..2=ignore - -# C2 encoding space -c.slli 1..0=2 15..13=0 12=ignore 11..2=ignore -c.fldsp 1..0=2 15..13=1 12=ignore 11..2=ignore # c.lqsp for RV128 -c.lwsp 1..0=2 15..13=2 12=ignore 11..2=ignore -c.flwsp 1..0=2 15..13=3 12=ignore 11..2=ignore # c.ldsp for RV64 -c.mv 1..0=2 15..13=4 12=0 11..2=ignore # !rs2 = c.jr -c.add 1..0=2 15..13=4 12=1 11..2=ignore # !rs1 = c.ebreak; !rs2=c.jalr -c.fsdsp 1..0=2 15..13=5 12=ignore 11..2=ignore # c.sqsp for RV128 -c.swsp 1..0=2 15..13=6 12=ignore 11..2=ignore -c.fswsp 1..0=2 15..13=7 12=ignore 11..2=ignore # c.sdsp for RV64 diff --git a/rv128_c b/rv128_c new file mode 100644 index 00000000..beb6cd6f --- /dev/null +++ b/rv128_c @@ -0,0 +1,15 @@ +# quadrant 0 +c.lq rd_p rs1_p c_uimm9lo c_uimm9hi 1..0=0 15..13=1 +c.ld rd_p rs1_p c_uimm8lo c_uimm8hi 1..0=0 15..13=3 +c.sq rs1_p rs2_p c_uimm9hi c_uimm9lo 1..0=0 15..13=5 +c.sd rs1_p rs2_p c_uimm8hi c_uimm8lo 1..0=0 15..13=7 + +#quadrant 1 +c.addiw rd_rs1 c_imm6lo c_imm6hi 1..0=1 15..13=1 + +#quadrant 2 +c.lqsp rd c_uimm10sphi c_uimm10splo 1..0=2 15..13=1 +c.ldsp rd_n0 c_uimm9sphi c_uimm9splo 1..0=2 15..13=3 +c.sqsp c_rs2 c_uimm10sp_s 1..0=2 15..13=5 +c.sdsp c_rs2 c_uimm9sp_s 1..0=2 15..13=7 + diff --git a/rv32_c b/rv32_c new file mode 100644 index 00000000..d9a90722 --- /dev/null +++ b/rv32_c @@ -0,0 +1,5 @@ +# quadrant 1 +c.jal c_imm12 1..0=1 15..13=1 +$pseudo_op rv64_c::c.srli c.srli rd_rs1_p c_nzuimm5 1..0=1 15..13=4 12..10=0 +$pseudo_op rv64_c::c.srai c.srai rd_rs1_p c_nzuimm5 1..0=1 15..13=4 12..10=1 +$pseudo_op rv64_c::c.slli c.slli rd_rs1_n0 c_nzuimm6lo 1..0=2 15..12=0 diff --git a/rv32_c_f b/rv32_c_f new file mode 100644 index 00000000..8487c9a7 --- /dev/null +++ b/rv32_c_f @@ -0,0 +1,8 @@ +# quadrant 0 +c.flw rd_p rs1_p c_uimm7lo c_uimm7hi 1..0=0 15..13=3 +c.fsw rs1_p rs2_p c_uimm7lo c_uimm7hi 1..0=0 15..13=7 + +#quadrant 2 +c.flwsp rd c_uimm8sphi c_uimm8splo 1..0=2 15..13=3 +c.fswsp c_rs2 c_uimm8sp_s 1..0=2 15..13=7 + diff --git a/rv64_c b/rv64_c new file mode 100644 index 00000000..39d087a9 --- /dev/null +++ b/rv64_c @@ -0,0 +1,17 @@ +# quadrant 0 +c.ld rd_p rs1_p c_uimm8lo c_uimm8hi 1..0=0 15..13=3 +c.sd rs1_p rs2_p c_uimm8hi c_uimm8lo 1..0=0 15..13=7 + +#quadrant 1 +c.addiw rd_rs1 c_imm6lo c_imm6hi 1..0=1 15..13=1 +c.srli rd_rs1_p c_nzuimm6lo c_nzuimm6hi 1..0=1 15..13=4 11..10=0 +c.srai rd_rs1_p c_nzuimm6lo c_nzuimm6hi 1..0=1 15..13=4 11..10=1 +c.subw rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b111 6..5=0 +c.addw rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b111 6..5=1 + + +#quadrant 2 +c.slli rd_rs1_n0 c_nzuimm6hi c_nzuimm6lo 1..0=2 15..13=0 +c.ldsp rd_n0 c_uimm9sphi c_uimm9splo 1..0=2 15..13=3 +c.sdsp c_rs2 c_uimm9sp_s 1..0=2 15..13=7 + diff --git a/rv_c b/rv_c new file mode 100644 index 00000000..46b1e1c8 --- /dev/null +++ b/rv_c @@ -0,0 +1,32 @@ +# quadrant 0 +c.addi4spn rd_p c_nzuimm10 1..0=0 15..13=0 +c.lw rd_p rs1_p c_uimm7lo c_uimm7hi 1..0=0 15..13=2 +c.sw rs1_p rs2_p c_uimm7lo c_uimm7hi 1..0=0 15..13=6 + +#quadrant 1 +c.nop c_nzimm6hi c_nzimm6lo 1..0=1 15..13=0 11..7=0 +c.addi rd_rs1_n0 c_nzimm6lo c_nzimm6hi 1..0=1 15..13=0 +c.li rd c_imm6lo c_imm6hi 1..0=1 15..13=2 +c.addi16sp c_nzimm10hi c_nzimm10lo 1..0=1 15..13=3 11..7=2 +c.lui rd_n2 c_nzimm18hi c_nzimm18lo 1..0=1 15..13=3 +c.andi rd_rs1_p c_imm6hi c_imm6lo 1..0=1 15..13=4 11..10=2 +c.sub rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=0 +c.xor rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=1 +c.or rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=2 +c.and rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=3 +c.j c_imm12 1..0=1 15..13=5 +c.beqz rs1_p c_bimm9lo c_bimm9hi 1..0=1 15..13=6 +c.bnez rs1_p c_bimm9lo c_bimm9hi 1..0=1 15..13=7 + +#quadrant 2 +c.lwsp rd_n0 c_uimm8sphi c_uimm8splo 1..0=2 15..13=2 +c.jr rs1_n0 1..0=2 15..13=4 12=0 6..2=0 +c.mv rd c_rs2_n0 1..0=2 15..13=4 12=0 +c.ebreak 1..0=2 15..13=4 12=1 11..2=0 +c.jalr c_rs1_n0 1..0=2 15..13=4 12=1 6..2=0 +c.add rd_rs1 c_rs2_n0 1..0=2 15..13=4 12=1 +c.swsp c_rs2 c_uimm8sp_s 1..0=2 15..13=6 + + + + diff --git a/rv_c_d b/rv_c_d new file mode 100644 index 00000000..cd49b447 --- /dev/null +++ b/rv_c_d @@ -0,0 +1,8 @@ +#quadrant 0 +c.fld rd_p rs1_p c_uimm8lo c_uimm8hi 1..0=0 15..13=1 +c.fsd rs1_p rs2_p c_uimm8lo c_uimm8hi 1..0=0 15..13=5 + +#quadrant 2 +c.fldsp rd c_uimm9sphi c_uimm9splo 1..0=2 15..13=1 +c.fsdsp c_rs2 c_uimm9sp_s 1..0=2 15..13=5 +