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test-1.out
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This is PINS'24 compiler (pushdown machine):
FP => 65532: -1
SP => 65528: -1
0: PUSH 0
FP => 65532: -1
65528: -1
SP => 65524: 0
5: NAME main
FP => 65532: -1
65528: -1
65524: 0
SP => 65520: 22
10: CALL
65532: -1
65528: -1
FP => 65524: 0 ... SL
65520: 65532 ... FP *** main ***
SP => 65516: 11 ... RA
[1.1:1.17] 22: PUSH 0
65532: -1
65528: -1
FP => 65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.1:1.17] SP => 65512: 0
[1.1:1.17] 27: POPN
65532: -1
65528: -1
FP => 65524: 0 ... SL
65520: 65532 ... FP *** main ***
SP => 65516: 11 ... RA
[1.16:1.16] 28: PUSH 5
65532: -1
65528: -1
FP => 65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] SP => 65512: 5
[1.12:1.17] 33: REGN.FP
65532: -1
65528: -1
FP => 65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5
[1.12:1.17] SP => 65508: 65524
[1.12:1.17] 34: LOAD
65532: -1
65528: -1
FP => 65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5
[1.12:1.17] SP => 65508: 0
[1.12:1.17] 35: NAME inc
65532: -1
65528: -1
FP => 65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5
[1.12:1.17] 65508: 0
[1.12:1.17] SP => 65504: 47
[1.12:1.17] 40: CALL
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] SP => 65500: 41 ... RA
[3.1:3.37] 47: PUSH -4
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.1:3.37] SP => 65496: -4 ... var: m
[3.1:3.37] 52: POPN
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.1:3.37] SP => 65496: 0 ... var: m
53: REGN.FP
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.1:3.37] 65496: 0 ... var: m
SP => 65492: 65508
54: PUSH -12
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.1:3.37] 65496: 0 ... var: m
65492: 65508
SP => 65488: -12
59: OPER.ADD
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.1:3.37] 65496: 0 ... var: m
SP => 65492: 65496
60: NAME :0
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.1:3.37] 65496: 0 ... var: m
65492: 65496
SP => 65488: 102
65: INIT
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.1:3.37] SP => 65496: 0 ... var: m
[3.29:3.29] 66: REGN.FP
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.1:3.37] 65496: 0 ... var: m
[3.29:3.29] SP => 65492: 65508
[3.29:3.29] 67: PUSH 4
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.1:3.37] 65496: 0 ... var: m
[3.29:3.29] 65492: 65508
[3.29:3.29] SP => 65488: 4
[3.29:3.29] 72: OPER.ADD
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.1:3.37] 65496: 0 ... var: m
[3.29:3.29] SP => 65492: 65512
[3.29:3.29] 73: LOAD
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.1:3.37] 65496: 0 ... var: m
[3.29:3.29] SP => 65492: 5
[3.27:3.27] 74: REGN.FP
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.1:3.37] 65496: 0 ... var: m
[3.29:3.29] 65492: 5
[3.27:3.27] SP => 65488: 65508
[3.27:3.27] 75: PUSH -12
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.1:3.37] 65496: 0 ... var: m
[3.29:3.29] 65492: 5
[3.27:3.27] 65488: 65508
[3.27:3.27] SP => 65484: -12
[3.27:3.27] 80: OPER.ADD
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.1:3.37] 65496: 0 ... var: m
[3.29:3.29] 65492: 5
[3.27:3.27] SP => 65488: 65496
[3.27:3.29] 81: SAVE
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.27:3.29] SP => 65496: 5 ... var: m
[3.31:3.31] 82: REGN.FP
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.27:3.29] 65496: 5 ... var: m
[3.31:3.31] SP => 65492: 65508
[3.31:3.31] 83: PUSH -12
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.27:3.29] 65496: 5 ... var: m
[3.31:3.31] 65492: 65508
[3.31:3.31] SP => 65488: -12
[3.31:3.31] 88: OPER.ADD
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.27:3.29] 65496: 5 ... var: m
[3.31:3.31] SP => 65492: 65496
[3.31:3.31] 89: LOAD
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.27:3.29] 65496: 5 ... var: m
[3.31:3.31] SP => 65492: 5
[3.33:3.33] 90: PUSH 1
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.27:3.29] 65496: 5 ... var: m
[3.31:3.31] 65492: 5
[3.33:3.33] SP => 65488: 1
[3.31:3.33] 95: OPER.ADD
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.27:3.29] 65496: 5 ... var: m
[3.31:3.33] SP => 65492: 6
[3.1:3.37] 96: PUSH 4
65532: -1
65528: -1
65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[1.16:1.16] 65512: 5 ... par: n
[1.12:1.17] FP => 65508: 0 ... SL
[1.12:1.17] 65504: 65524 ... FP *** inc ***
[1.12:1.17] 65500: 41 ... RA
[3.27:3.29] 65496: 5 ... var: m
[3.31:3.33] 65492: 6
[3.1:3.37] SP => 65488: 4
[3.1:3.37] 101: RETN
65532: -1
65528: -1
FP => 65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[3.1:3.37] SP => 65512: 6
[1.1:1.17] 41: PUSH 0
65532: -1
65528: -1
FP => 65524: 0 ... SL
65520: 65532 ... FP *** main ***
65516: 11 ... RA
[3.1:3.37] 65512: 6
[1.1:1.17] SP => 65508: 0
[1.1:1.17] 46: RETN
FP => 65532: -1
65528: -1
[1.1:1.17] SP => 65524: 6
11: PUSH 0
FP => 65532: -1
65528: -1
[1.1:1.17] 65524: 6
SP => 65520: 0
16: NAME exit
FP => 65532: -1
65528: -1
[1.1:1.17] 65524: 6
65520: 0
SP => 65516: -1
21: CALL
EXIT CODE (SP=65536): 6
:-) Done.