diff --git a/.gitmodules b/.gitmodules
index 467761972..3a47222c9 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -43,3 +43,6 @@
 [submodule "third_party/liteiclink"]
 	path = third_party/liteiclink
 	url = https://github.com/enjoy-digital/liteiclink.git
+[submodule "third_party/VexRiscv"]
+	path = third_party/VexRiscv
+	url = https://github.com/SpinalHDL/VexRiscv.git
diff --git a/patches/0001-emulator-Use-external-hw-common.h-from-LiteX.patch b/patches/0001-emulator-Use-external-hw-common.h-from-LiteX.patch
deleted file mode 100644
index 42e7bfdec..000000000
--- a/patches/0001-emulator-Use-external-hw-common.h-from-LiteX.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From f88b259ebacb84624f2df3cfd14db56a5dd2ca4f Mon Sep 17 00:00:00 2001
-From: Mateusz Holenko <mholenko@antmicro.com>
-Date: Mon, 24 Feb 2020 12:43:35 +0100
-Subject: [PATCH] emulator: Use external hw/common.h from LiteX
-
-Remove code copied from `hw/common.h` and use
-the header from the LiteX repository provided
-using `LITEX_BASE` environment variable.
-
-Content of `common.h` is now evolving (new functions
-are added, some are removed) and syncing it
-between repos would be cumbersome.
----
- src/main/c/emulator/makefile  |  7 ++++---
- src/main/c/emulator/src/hal.c | 32 --------------------------------
- 2 files changed, 4 insertions(+), 35 deletions(-)
-
-diff --git a/src/main/c/emulator/makefile b/src/main/c/emulator/makefile
-index 7534d08..6f3c8fc 100755
---- a/src/main/c/emulator/makefile
-+++ b/src/main/c/emulator/makefile
-@@ -18,10 +18,11 @@ sim: all
- qemu: CFLAGS += -DQEMU
- qemu: all
- 
--litex: CFLAGS += -DLITEX -I${LITEX_BASE}/software/include
--litex: | check_litex_base all
--check_litex_base:
-+litex: CFLAGS += -DLITEX -I${LITEX_GENERATED} -I${LITEX_BASE}/litex/soc/software/include
-+litex: | check_litex all
-+check_litex:
- 	@[ "${LITEX_BASE}" ] || ( echo ">> LITEX_BASE is not set"; exit 1 )
-+	@[ "${LITEX_GENERATED}" ] || ( echo ">> LITEX_GENERATED is not set"; exit 1 )
- 
- include ${STANDALONE}/common/riscv64-unknown-elf.mk
- include ${STANDALONE}/common/standalone.mk
-diff --git a/src/main/c/emulator/src/hal.c b/src/main/c/emulator/src/hal.c
-index 5a151bb..aa6745b 100644
---- a/src/main/c/emulator/src/hal.c
-+++ b/src/main/c/emulator/src/hal.c
-@@ -146,38 +146,6 @@ void halInit(){
- 
- #ifdef LITEX
- 
--// this is copied from LiteX <hw/common.h>
--#define CSR_ACCESSORS_DEFINED
--static inline void csr_writeb(uint8_t value, unsigned long addr)
--{
--	*((volatile uint8_t *)addr) = value;
--}
--
--static inline uint8_t csr_readb(unsigned long addr)
--{
--	return *(volatile uint8_t *)addr;
--}
--
--static inline void csr_writew(uint16_t value, unsigned long addr)
--{
--	*((volatile uint16_t *)addr) = value;
--}
--
--static inline uint16_t csr_readw(unsigned long addr)
--{
--	return *(volatile uint16_t *)addr;
--}
--
--static inline void csr_writel(uint32_t value, unsigned long addr)
--{
--	*((volatile uint32_t *)addr) = value;
--}
--
--static inline uint32_t csr_readl(unsigned long addr)
--{
--	return *(volatile uint32_t *)addr;
--}
--
- // this is a file generated by LiteX
- #include <generated/csr.h>
- 
--- 
-2.25.0
-
diff --git a/scripts/build-linux.sh b/scripts/build-linux.sh
index 0ac712769..864c3b9fa 100755
--- a/scripts/build-linux.sh
+++ b/scripts/build-linux.sh
@@ -173,17 +173,10 @@ if [ ${CPU} = vexriscv ]; then
 		# get rid of 'L' suffix
 		RAM_BASE_ADDRESS=${RAM_BASE_ADDRESS::-1}
 
-		# this is a temp fix for building the emulator
-		cd $TOP_DIR/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/ext/VexRiscv
-                if [ ! -e .patched ]; then
-		    git am $TOP_DIR/patches/0001-emulator-Use-external-hw-common.h-from-LiteX.patch
-                    touch .patched
-                fi
-
-		cd $TOP_DIR/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/ext/VexRiscv/src/main/c/emulator
+		cd $TOP_DIR/third_party/VexRiscv/src/main/c/emulator
 
 		# offsets are hardcoded in BIOS
-		export CFLAGS="-DOS_CALL=$((RAM_BASE_ADDRESS + 0x0)) -DDTB=$((RAM_BASE_ADDRESS + 0x01000000)) -Wl,--defsym,__ram_origin=$((RAM_BASE_ADDRESS + 0x01100000))"
+		export CFLAGS="-DOS_CALL=$((RAM_BASE_ADDRESS + 0x0)) -DDTB=$((RAM_BASE_ADDRESS + 0x01000000)) -Wl,--defsym,__ram_origin=$((RAM_BASE_ADDRESS + 0x01100000)) -I$TOP_DIR/third_party/litex/litex/soc/cores/cpu/vexriscv"
 		export LITEX_GENERATED="$TOP_DIR/$TARGET_BUILD_DIR/software/include"
 		export LITEX_BASE="$TOP_DIR/third_party/litex"
 		export RISCV_BIN="${CPU_ARCH}-elf-newlib-"
diff --git a/third_party/VexRiscv b/third_party/VexRiscv
new file mode 160000
index 000000000..2942d0652
--- /dev/null
+++ b/third_party/VexRiscv
@@ -0,0 +1 @@
+Subproject commit 2942d0652a89646c5225bee15dd55cc3b0871766