diff --git a/+adi/+AD3552R/Base.m b/+adi/+AD3552R/Base.m new file mode 100755 index 0000000..2604a01 --- /dev/null +++ b/+adi/+AD3552R/Base.m @@ -0,0 +1,124 @@ +classdef (Abstract) Base < ... + adi.common.RxTx & ... + matlabshared.libiio.base & ... + adi.common.Attribute + % adi.AD3552R.Tx Transmit data to the AD3552R high speed DAC + % The adi.AD3552R.Tx System object is a signal source that can send + % complex data from the AD3552R. + % + % tx = adi.AD3552R.Tx; + % tx = adi.AD3552R.Tx('uri','192.168.2.1'); + % + % AD3552R Datasheet + % + % See also adi.CN0585.Tx + + properties (Nontunable) + % SamplesPerFrame Samples Per Frame + % Number of samples per frame, specified as an even positive + % integer from 2 to 16,777,216. Using values less than 3660 can + % yield poor performance. + SamplesPerFrame = 2 ^ 15; + end + + properties (Nontunable, Hidden) + Timeout = Inf; + kernelBuffersCount = 2; + dataTypeStr = 'uint16'; + end + + properties (Abstract, Hidden, Constant) + Type + end + + properties (Hidden, Constant) + ComplexData = false; + end + + properties + % InputSource + % Lists all the available input sources of the DAC. + % Options are: 'adc_input', 'dma_input', 'ramp_input'. + % Example: InputSource = 'dma_input'; + InputSource = 'dma_input'; + end + + properties + % OutputRange + % Lists all the available voltage ranges of the output signal. + % Options are: '0/2.5V', '0/5V', '0/10V', '-5/+5V', '-10/+10V'. + % Example: OutputRange = '-10/+10V'; + OutputRange = '-10/+10V'; + end + + properties + InputSourceSet = matlab.system.StringSet({... + 'adc_input', 'dma_input', 'ramp_input'}) + OutputRangeSet = matlab.system.StringSet({... + '0/2.5V', '0/5V', '0/10V', '-5/+5V', '-10/+10V'}) + end + + methods + %% Constructor + function obj = Base(varargin) + % Returns the matlabshared.libiio.base object + coder.allowpcode('plain'); + obj = obj@matlabshared.libiio.base(varargin{:}); + end + + % Check SamplesPerFrame + function set.SamplesPerFrame(obj, value) + validateattributes(value, {'double', 'single'}, ... + {'real', 'positive', 'scalar', 'finite', 'nonnan', 'nonempty', 'integer', '>', 0, '<', 2 ^ 20 + 1}, ... + '', 'SamplesPerFrame'); + obj.SamplesPerFrame = value; + end + + % Set/Get Input Source + function result = get.InputSource(obj) + result = obj.InputSource; + end + + function set.InputSource(obj, value) + obj.InputSource = value; + end + + % Set/Get Output Range + function result = get.OutputRange(obj) + result = obj.OutputRange; + end + + function set.OutputRange(obj, value) + obj.OutputRange = value; + end + + end + + %% API Functions + methods (Hidden, Access = protected) + + function icon = getIconImpl(obj) + icon = sprintf(['AD3552R', obj.Type]); + end + + end + + %% External Dependency Methods + methods (Hidden, Static) + + function tf = isSupportedContext(bldCfg) + tf = matlabshared.libiio.ExternalDependency.isSupportedContext(bldCfg); + end + + function updateBuildInfo(buildInfo, bldCfg) + % Call the matlabshared.libiio.method first + matlabshared.libiio.ExternalDependency.updateBuildInfo(buildInfo, bldCfg); + end + + function bName = getDescriptiveName(~) + bName = 'AD3552R'; + end + + end + +end diff --git a/+adi/+AD3552R/Tx.m b/+adi/+AD3552R/Tx.m new file mode 100755 index 0000000..10e62d3 --- /dev/null +++ b/+adi/+AD3552R/Tx.m @@ -0,0 +1,88 @@ +classdef Tx < adi.common.Tx & adi.AD3552R.Base + % adi.AD3552R.Tx Transmit data to the AD3552R high speed DAC + % The adi.AD3552R.Tx System object is a signal source that can send + % complex data from the AD3552R. + % + % tx = adi.AD3552R.Tx; + % tx = adi.AD3552R.Tx('uri','192.168.2.1'); + % + % AD3552R Datasheet + % + % See also adi.CN0585.Tx + + properties (Constant) + % SamplingRate Sampling Rate + % Baseband sampling rate in Hz, specified as a scalar + % in samples per second. This value is constant. + SamplingRate = 15e6; + end + + properties (Hidden, Nontunable, Access = protected) + isOutput = true; + end + + properties (Nontunable, Hidden, Constant) + Type = 'Tx'; + end + + properties (Nontunable, Hidden) + devName = 'axi-ad3552r'; + phyDevName = 'axi-ad3552r'; + channel_names = {'voltage0', 'voltage1'}; + end + + properties + % StreamStatus + % Describes the status of the data streaming. + % Options are: 'start_stream_synced', 'start_stream', 'stop_stream'. + % Example: StreamStatus = 'stop_stream'; + StreamStatus = 'stop_stream'; + end + + properties (Hidden, Constant) + StreamStatusSet = matlab.system.StringSet({ ... + 'start_stream_synced', 'start_stream', 'stop_stream'}) + end + + methods + %% Constructor + function obj = Tx(varargin) + % Returns the matlabshared.libiio.base object + coder.allowpcode('plain'); + obj = obj@adi.AD3552R.Base(varargin{:}); + end + + %% Start or stop stream transfer + function set.StreamStatus(obj, value) + + if obj.ConnectedToDevice + obj.setDeviceAttributeRAW('stream_status', value); + else + error(['StreamStatus cannot be set before initialization, ']); + end + + obj.StreamStatus = value; + + end + + end + + %% External Dependency Methods + methods (Hidden, Static) + + function tf = isSupportedContext(bldCfg) + tf = matlabshared.libiio.ExternalDependency.isSupportedContext(bldCfg); + end + + function updateBuildInfo(buildInfo, bldCfg) + % Call the matlabshared.libiio.method first + matlabshared.libiio.ExternalDependency.updateBuildInfo(buildInfo, bldCfg); + end + + function bName = getDescriptiveName(~) + bName = 'AD3552R'; + end + + end + +end diff --git a/+adi/+CN0585/Base.m b/+adi/+CN0585/Base.m new file mode 100755 index 0000000..3edc2f5 --- /dev/null +++ b/+adi/+CN0585/Base.m @@ -0,0 +1,60 @@ +classdef (Abstract, Hidden = true) Base < ... + adi.common.RxTx & ... + adi.common.Attribute & ... + matlabshared.libiio.base + %adi.CN0585.Base Class + % This class contains shared parameters and methods between TX and RX + % classes + + properties (Hidden) + iioOneBitADCDAC; + HDLSystemID + + end + + methods + %% Constructor + function obj = Base(varargin) + coder.allowpcode('plain'); + obj = obj@matlabshared.libiio.base(varargin{:}); + end + + function result = CheckMathWorksCore(obj) + result = contains(obj.HDLSystemID, "matlab"); + end + + end + + %% API Functions + methods (Hidden, Access = protected) + + function setupInit(obj) + + % GPIO CONTROLLER + + obj.iioOneBitADCDAC = getDev(obj, 'one-bit-adc-dac'); + obj.setAttributeBool('voltage0', 'raw', boolean(1), true, obj.iioOneBitADCDAC); + obj.setAttributeBool('voltage1', 'raw', boolean(1), true, obj.iioOneBitADCDAC); + obj.setAttributeBool('voltage2', 'raw', boolean(1), true, obj.iioOneBitADCDAC); + obj.setAttributeBool('voltage3', 'raw', boolean(1), true, obj.iioOneBitADCDAC); + obj.setAttributeBool('voltage4', 'raw', boolean(1), true, obj.iioOneBitADCDAC); + obj.setAttributeBool('voltage5', 'raw', boolean(1), true, obj.iioOneBitADCDAC); + obj.setAttributeBool('voltage6', 'raw', boolean(1), true, obj.iioOneBitADCDAC); + obj.setAttributeBool('voltage7', 'raw', boolean(1), true, obj.iioOneBitADCDAC); + obj.setAttributeBool('voltage8', 'raw', boolean(1), true, obj.iioOneBitADCDAC); + obj.setAttributeBool('voltage9', 'raw', boolean(1), true, obj.iioOneBitADCDAC); + + % HDLSystemID SYSID STRING VALUE + + obj.HDLSystemID = obj.iio_context_get_attr_value(obj.iioCtx, 'hdl_system_id'); + + % UPDATED PARAMETERS + + obj.setDeviceAttributeRAW('input_source', obj.InputSource); + obj.setDeviceAttributeRAW('output_range', obj.OutputRange); + + end + + end + +end diff --git a/+adi/+CN0585/Rx.m b/+adi/+CN0585/Rx.m new file mode 100755 index 0000000..c9c8449 --- /dev/null +++ b/+adi/+CN0585/Rx.m @@ -0,0 +1,21 @@ +classdef Rx < adi.LTC2387.Rx + % adi.CN0585.Rx Receive data from the LTC2387 evaluation platform + % + % rx = adi.CN0585.Rx; + % rx = adi.CN0585.Rx('uri','192.168.2.1'); + % + % User Guide + % + % See also adi.LTC2387.Rx + + methods + %% Constructor + function obj = Rx(varargin) + % Returns the matlabshared.libiio.base object + coder.allowpcode('plain'); + obj = obj@adi.LTC2387.Rx(varargin{:}); + end + + end + +end diff --git a/+adi/+CN0585/Tx0.m b/+adi/+CN0585/Tx0.m new file mode 100755 index 0000000..50bc2c7 --- /dev/null +++ b/+adi/+CN0585/Tx0.m @@ -0,0 +1,23 @@ +classdef Tx0 < adi.AD3552R.Tx & adi.CN0585.Base + % adi.CN0585.Tx Transmit data from the AD3552R evaluation platform + % + % tx0 = adi.CN0585.Tx0; + % tx0 = adi.CN0585.Tx0('uri','192.168.2.1'); + % + % User Guide + % + % See also adi.AD3552R.Tx0 + + methods + %% Constructor + function obj = Tx0(varargin) + % Returns the matlabshared.libiio.base object + coder.allowpcode('plain'); + obj = obj@adi.AD3552R.Tx(varargin{:}); + obj.devName = 'axi-ad3552r-0'; + obj.phyDevName = 'axi-ad3552r-0'; + end + + end + +end diff --git a/+adi/+CN0585/Tx1.m b/+adi/+CN0585/Tx1.m new file mode 100755 index 0000000..352d5e5 --- /dev/null +++ b/+adi/+CN0585/Tx1.m @@ -0,0 +1,22 @@ +classdef Tx1 < adi.AD3552R.Tx & adi.CN0585.Base + % adi.CN0585.Tx Transmit data from the AD3552R evaluation platform + % + % tx1 = adi.CN0585.Tx1; + % tx1 = adi.CN0585.Tx1('uri','192.168.2.1'); + % + % User Guide + % + % See also adi.AD3552R.Tx1 + + methods + %% Constructor + function obj = Tx1(varargin) + % Returns the matlabshared.libiio.base object + coder.allowpcode('plain'); + obj = obj@adi.AD3552R.Tx(varargin{:}); + obj.devName = 'axi-ad3552r-1'; + obj.phyDevName = 'axi-ad3552r-1'; + end + end + +end diff --git a/+adi/+LTC2387/Base.m b/+adi/+LTC2387/Base.m new file mode 100755 index 0000000..cd1badb --- /dev/null +++ b/+adi/+LTC2387/Base.m @@ -0,0 +1,72 @@ +classdef (Abstract) Base < ... + adi.common.RxTx & ... + adi.common.Attribute & ... + matlabshared.libiio.base + %LTC2387 Base Class + + properties (Nontunable) + %SamplesPerFrame Samples Per Frame + % Number of samples per frame, specified as an even positive + % integer from 2 to 16,777,216. Using values less than 3660 can + % yield poor performance. + SamplesPerFrame = 2^15; + end + + properties(Nontunable, Hidden) + Timeout = Inf; + kernelBuffersCount = 2; + dataTypeStr = 'int64'; + end + + properties (Abstract, Hidden, Constant) + Type + end + + + properties (Hidden, Constant) + ComplexData = false; + end + + methods + %% Constructor + function obj = Base(varargin) + % Returns the matlabshared.libiio.base object + coder.allowpcode('plain'); + obj = obj@matlabshared.libiio.base(varargin{:}); + end + % Check SamplesPerFrame + function set.SamplesPerFrame(obj, value) + validateattributes( value, { 'double','single' }, ... + { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>',0,'<',2^20+1}, ... + '', 'SamplesPerFrame'); + obj.SamplesPerFrame = value; + end + end + + %% API Functions + methods (Hidden, Access = protected) + + function icon = getIconImpl(obj) + icon = sprintf(['LTC2387 ',obj.Type]); + end + + end + + %% External Dependency Methods + methods (Hidden, Static) + + function tf = isSupportedContext(bldCfg) + tf = matlabshared.libiio.ExternalDependency.isSupportedContext(bldCfg); + end + + function updateBuildInfo(buildInfo, bldCfg) + % Call the matlabshared.libiio.method first + matlabshared.libiio.ExternalDependency.updateBuildInfo(buildInfo, bldCfg); + end + + function bName = getDescriptiveName(~) + bName = 'LTC2387'; + end + + end +end diff --git a/+adi/+LTC2387/Rx.m b/+adi/+LTC2387/Rx.m new file mode 100755 index 0000000..0b1c6d6 --- /dev/null +++ b/+adi/+LTC2387/Rx.m @@ -0,0 +1,73 @@ +classdef Rx < adi.common.Rx & adi.LTC2387.Base & adi.common.Attribute + % adi.LTC2387.Rx Receive data from the LTC2387 high speed ADC + % The adi.LTC2387.Rx System object is a signal source that can receive + % complex data from the LTC2387. + % + % rx = adi.LTC2387.Rx; + % rx = adi.LTC2387.Rx('uri','192.168.2.1'); + % + % LTC2387 Datasheet + % + % See also adi.CN0585.Rx + + properties (Dependent) + %SamplingRate Sampling Rate + % Baseband sampling rate in Hz, specified as a scalar + % in samples per second. This value is constant + SamplingRate + end + properties (Hidden, Nontunable, Access = protected) + isOutput = false; + end + + properties(Nontunable, Hidden, Constant) + Type = 'Rx'; + end + + properties (Nontunable, Hidden) + devName = 'ltc2387'; + phyDevName = 'ltc2387'; + channel_names = {'voltage0','voltage1','voltage2','voltage3'}; + end + + methods + %% Constructor + function obj = Rx(varargin) + % Returns the matlabshared.libiio.base object + coder.allowpcode('plain'); + obj = obj@adi.LTC2387.Base(varargin{:}); + end + function value = get.SamplingRate(obj) + if obj.ConnectedToDevice + value= obj.getAttributeLongLong('voltage0','sampling_frequency',false); + else + value = NaN; + end + end + end + + %% API Functions + methods (Hidden, Access = protected) + function setupInit(~) + %unused + end + end + + %% External Dependency Methods + methods (Hidden, Static) + + function tf = isSupportedContext(bldCfg) + tf = matlabshared.libiio.ExternalDependency.isSupportedContext(bldCfg); + end + + function updateBuildInfo(buildInfo, bldCfg) + % Call the matlabshared.libiio.method first + matlabshared.libiio.ExternalDependency.updateBuildInfo(buildInfo, bldCfg); + end + + function bName = getDescriptiveName(~) + bName = 'LTC2387'; + end + + end +end diff --git a/+adi/Contents.m b/+adi/Contents.m index 735aea5..dfdc479 100644 --- a/+adi/Contents.m +++ b/+adi/Contents.m @@ -14,3 +14,10 @@ % AD4858 - ADC % AD2S1210 - Resolver-to-Digital Converter % AD4020 - ADC +% AD43552R - DAC +% LTC2387 - DAC +% +% Boards and Platforms +% ----------------------- +% CN0585 - FMC development board for precision data acquisition + diff --git a/+adi/Version.m b/+adi/Version.m index cffb464..f749edb 100644 --- a/+adi/Version.m +++ b/+adi/Version.m @@ -2,7 +2,8 @@ % Version % BSP Version information properties (Constant) - MATLAB = 'R2021b' + Vivado = '2022.2' + MATLAB = 'R2022a' Release = '21.2.1' AppName = 'Analog Devices, Inc. Precision Toolbox' ToolboxName = 'PrecisionToolbox' diff --git a/.gitmodules b/.gitmodules index 12bf1fc..73fe3bc 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,8 @@ [submodule "+adi/+common"] path = +adi/+common url = https://github.com/analogdevicesinc/ToolboxCommon.git + branch = master +[submodule "CI/scripts"] + path = CI/scripts + url = https://github.com/analogdevicesinc/ToolboxCI.git + branch = master diff --git a/CI/doc/SysObjsProps.m b/CI/doc/SysObjsProps.m index c088b24..6983493 100644 --- a/CI/doc/SysObjsProps.m +++ b/CI/doc/SysObjsProps.m @@ -9,3 +9,4 @@ % * AD7768 % * AD2S1210 % * AD4020 +% * CN0585 and diff --git a/CI/doc/genhtml.m b/CI/doc/genhtml.m index 77043be..cad2ec3 100644 --- a/CI/doc/genhtml.m +++ b/CI/doc/genhtml.m @@ -1,6 +1,6 @@ mfiledir = '..\..\+adi\'; docdir = '..\..\doc\'; -parts = {'AD4630','AD4030','AD463x','AD7768','AD4858','AD2S1210','AD4020'}; +parts = {'AD4630','AD4030','AD463x','AD7768','AD4858','AD2S1210','AD4020','CN0585'}; trx_files = {'Rx','Base','Tx'}; for ii = 1:numel(parts) for jj = 1:numel(trx_files) diff --git a/CI/gen_doc/docs/assets/rd_cn0585.svg b/CI/gen_doc/docs/assets/rd_cn0585.svg new file mode 100644 index 0000000..b00ccdb --- /dev/null +++ b/CI/gen_doc/docs/assets/rd_cn0585.svg @@ -0,0 +1,293 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CI/gen_doc/docs/gen_hdl_refdesigns.py b/CI/gen_doc/docs/gen_hdl_refdesigns.py index 74f8c07..45e991b 100644 --- a/CI/gen_doc/docs/gen_hdl_refdesigns.py +++ b/CI/gen_doc/docs/gen_hdl_refdesigns.py @@ -32,6 +32,8 @@ def update_hdl_refdesigns(): objs[obj]["rd_image"] = "ad9361" elif objs[obj]["name"] in ["adrv9002"]: objs[obj]["rd_image"] = "adrv9001" + elif objs[obj]["name"] in ["cn0585"]: + objs[obj]["rd_image"] = "cn0585" else: objs[obj]["rd_image"] = "jesd" diff --git a/CI/gen_doc/docs/gen_rd_svg.py b/CI/gen_doc/docs/gen_rd_svg.py index 8cb6f6b..3c833be 100644 --- a/CI/gen_doc/docs/gen_rd_svg.py +++ b/CI/gen_doc/docs/gen_rd_svg.py @@ -1,7 +1,7 @@ import os def gen_rd_svg(): - refs = ["rd_ad9361","rd_adrv9001","rd_jesd"] + refs = ["rd_ad9361","rd_adrv9001","rd_cn0585","rd_jesd"] css_out = "" for ref in refs: @@ -10,8 +10,10 @@ def gen_rd_svg(): svg = f.read() selectable_boxes = { + "AXIAD3552RBox": {"link": "https://wiki.analog.com/resources/fpga/docs/axi_ad3552r"}, "AXIAD9361Box": {"link": "https://wiki.analog.com/resources/fpga/docs/axi_ad9361"}, "AXIADRV9002Box": {"link": "https://wiki.analog.com/resources/eval/user-guides/adrv9002/axi_adrv9002"}, + "AXILTC2387Box": {"link": "https://wiki.analog.com/resources/fpga/docs/axi_ltc2387"}, "TxDMAEngineBox": {"link": "https://wiki.analog.com/resources/fpga/docs/axi_dmac"}, "TxUPACKBox": {"link": "https://wiki.analog.com/resources/fpga/docs/util_upack"}, "TxFIFOBox": {"link": "https://wiki.analog.com/resources/fpga/docs/util_rfifo"}, diff --git a/CI/gen_doc/docs/gen_sysobj_doc.m b/CI/gen_doc/docs/gen_sysobj_doc.m index f4e0c29..1256284 100644 --- a/CI/gen_doc/docs/gen_sysobj_doc.m +++ b/CI/gen_doc/docs/gen_sysobj_doc.m @@ -16,6 +16,7 @@ , {'AD4858', {'Rx'}}... , {'AD2S1210', {'Rx'}}... , {'AD4020', {'Rx'}}... + , {'CN0585', {'Rx','Tx'}}... %{'QuadMxFE',{'Rx','Tx'}}... }; @@ -24,9 +25,9 @@ for jj = 1:numel(rootClasses{ii}{2}) part = rootClasses{ii}{1}; tmp = rootClasses{ii}{2}; - trx_file = tmp{jj}; + pcx_file = tmp{jj}; all_props = []; - dotmfilename = strcat(mfiledir, '.', part, '.', trx_file); + dotmfilename = strcat(mfiledir, '.', part, '.', pcx_file); props = unique(properties(dotmfilename)); for prop = 1:length(props) diff --git a/CI/gen_doc/requirements_doc.txt b/CI/gen_doc/requirements_doc.txt new file mode 100644 index 0000000..060c0f8 --- /dev/null +++ b/CI/gen_doc/requirements_doc.txt @@ -0,0 +1,6 @@ +numpy +mkdocs<1.5 +mkdocs-material +mkdocs-awesome-pages-plugin +mkdocs-mermaid2-plugin +mkdocs-plugin-inline-svg diff --git a/CI/scripts b/CI/scripts new file mode 160000 index 0000000..c1489a3 --- /dev/null +++ b/CI/scripts @@ -0,0 +1 @@ +Subproject commit c1489a3cf2781045900cb29e68a7b7c896200366 diff --git a/CI/scripts/Docker b/CI/scripts/Docker deleted file mode 100644 index 6c95c6f..0000000 --- a/CI/scripts/Docker +++ /dev/null @@ -1,10 +0,0 @@ -FROM ubuntu:16.04 - -MAINTAINER Travis Collins -RUN DEBIAN_FRONTEND=noninteractive apt update -RUN DEBIAN_FRONTEND=noninteractive apt-get install -y libpng-dev libfreetype6-dev libblas-dev liblapack-dev gfortran build-essential xorg -RUN DEBIAN_FRONTEND=noninteractive apt-get install -y openjdk-8-jre openjdk-8-jdk libgtk2.0-0 libxss1 libxt6 zip unzip curl wget tar git xvfb -RUN DEBIAN_FRONTEND=noninteractive apt-get install -y fakeroot libncurses5-dev libssl-dev ccache dfu-util u-boot-tools device-tree-compiler -RUN DEBIAN_FRONTEND=noninteractive apt-get install -y libssl-dev mtools bc python cpio zip unzip rsync file wget -RUN DEBIAN_FRONTEND=noninteractive dpkg --add-architecture i386 -RUN DEBIAN_FRONTEND=noninteractive apt-get install -y lib32stdc++6 diff --git a/CI/scripts/Makefile b/CI/scripts/Makefile deleted file mode 100644 index 4e91c39..0000000 --- a/CI/scripts/Makefile +++ /dev/null @@ -1,124 +0,0 @@ -# Usage: -# make MLRELEASE= HDLBRANCH= -# Example -# make build MLRELEASE=R2018b HDLBRANCH=hdl_2018_r1 - -SHELL := /bin/bash - -MLFLAGS := -nodisplay -nodesktop -nosplash - -ifeq ($(MLRELEASE),) -MLRELEASE := R2021b -endif - -ifeq ($(HDLBRANCH),) -HDLBRANCH := hdl_2019_r1 -endif - -ifeq ($(OS),Windows_NT) -MLPATH := /cygdrive/c/Program\ Files/MATLAB -MLFLAGS := $(MLFLAGS) -wait -else -UNAME_S := $(shell uname -s) -ifeq ($(UNAME_S),Linux) -MLPATH := /usr/local/MATLAB -endif -ifeq ($(UNAME_S),Darwin) -MLPATH := /Applications -MLRELEASE := MATLAB_${MLRELEASE}.app -endif -endif - -ifeq ($(BOARD),) -BOARD := -endif - -ifeq ($(INCLUDE_EXAMPLES),) -INCLUDE_EXAMPLES := 1 -endif - -GITTAG := $(shell git describe --tags HEAD) - -.ONESHELL: -build: - # Uses the HDLBRANCH variable - bash build_bsp.sh - -add_libad9361: - cd ../.. ; \ - mkdir deps ; \ - cd deps ; \ - mkdir linux ; \ - cd linux ; \ - wget http://swdownloads.analog.com/cse/travis_builds/master_latest_libad9361-iio-trusty.tar.gz ; \ - tar xvf *.tar.gz ; \ - mv usr/local/lib/* . ; \ - mv usr/local/include ../ ; \ - rm -rf usr ; \ - rm *.tar.gz ; \ - cd .. ; \ - mkdir osx ; \ - cd osx ; \ - wget http://swdownloads.analog.com/cse/travis_builds/master_latest_libad9361-iio-osx_10.12.tar.gz ; \ - tar xvf *.tar.gz ; \ - cd ad9361* ; \ - mv usr/local/lib/ad9361.framework/Versions/Current/ad9361 ../libad9361.dylib ; \ - cd .. ; \ - rm -rf ad9361-*-Darwin ; \ - rm *.tar.gz ; \ - cd .. ; \ - mkdir win ; \ - cd win ; \ - wget "https://github.com/analogdevicesinc/libad9361-iio/releases/download/v0.2/libad9361-0.2-win64.zip" -O lib.zip ; \ - unzip lib.zip ; \ - mv libad9361-win64/* . ; \ - rm -rf libad9361-win64 ; \ - rm *.h ; \ - rm lib.zip - -test_installer: - cd ../.. ; \ - cp *.mltbx test/ ; \ - cp hdl/vendor/AnalogDevices/hdlcoder_board_customization.m test/hdlcoder_board_customization_local.m ; \ - sed -i "s/hdlcoder_board_customization/hdlcoder_board_customization_local/g" test/hdlcoder_board_customization_local.m ; \ - ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "cd('test');runInstallerTests('$(BOARD)');" - -test: - cd ../.. ; \ - ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "cd('test');runTests('$(BOARD)');" - -test_streaming: - cd ../.. ; \ - ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "addpath(genpath('test'));addpath(genpath('deps'));runHWTests;" - -test_evm: - cd ../.. ; \ - ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "addpath(genpath('test'));addpath(genpath('deps'));hwTestRunner;" - -test_modem: - cd ../.. ; \ - ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "addpath(genpath('hdl'));cd('targeting');addpath(genpath('modem-qpsk'))" - -test_synth: - bash synth_designs.sh $(BOARD) - -test_targeting_demos: - bash targeting_designs.sh - -lte_pa_app: - cd ../../trx_examples/streaming/LTE_PA_App/ ; \ - bash genInstaller.sh $(MLPATH) $(MLRELEASE) $(MLFLAGS) - -gen_tlbx: - ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "genTlbx($(INCLUDE_EXAMPLES));exit();" - -linter: - ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "linter;exit();" - -doc: - ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "cd('../doc');genhtml();exit();" - -zip: - cd ../.. ; \ - mkdir zip ; \ - zip -r zip/AnalogDevicesBSP_$(GITTAG).zip deps doc hdl hil_models targeting info.xml LICENSE README.md test/*.log diff --git a/CI/scripts/Makefile2 b/CI/scripts/Makefile2 deleted file mode 100644 index cc2d2d9..0000000 --- a/CI/scripts/Makefile2 +++ /dev/null @@ -1,128 +0,0 @@ -# Usage: -# make MLRELEASE= HDLBRANCH= -# Example -# make build MLRELEASE=R2018b HDLBRANCH=hdl_2018_r1 - -SHELL := /bin/bash - -MLFLAGS := -nodisplay -nodesktop -nosplash - -ifeq ($(MLRELEASE),) -MLRELEASE := R2021a -endif - -ifeq ($(HDLBRANCH),) -HDLBRANCH := hdl_2019_r1 -endif - -ifeq ($(OS),Windows_NT) -MLPATH := /cygdrive/c/Program\ Files/MATLAB -MLFLAGS := $(MLFLAGS) -wait -else -UNAME_S := $(shell uname -s) -ifeq ($(UNAME_S),Linux) -MLPATH := /usr/local/MATLAB -endif -ifeq ($(UNAME_S),Darwin) -MLPATH := /Applications -MLRELEASE := MATLAB_${MLRELEASE}.app -endif -endif - -ifeq ($(BOARD),) -BOARD := -endif - -ifeq ($(INCLUDE_EXAMPLES),) -INCLUDE_EXAMPLES := 1 -endif - -GITTAG := $(shell git describe --tags HEAD) - -.ONESHELL: -build: - # Uses the HDLBRANCH variable - bash build_bsp.sh - -add_libad9361: - cd ../.. ; \ - mkdir deps ; \ - cd deps ; \ - mkdir linux ; \ - cd linux ; \ - wget http://swdownloads.analog.com/cse/travis_builds/master_latest_libad9361-iio-trusty.tar.gz ; \ - tar xvf *.tar.gz ; \ - mv usr/local/lib/* . ; \ - mv usr/local/include ../ ; \ - rm -rf usr ; \ - rm *.tar.gz ; \ - cd .. ; \ - mkdir osx ; \ - cd osx ; \ - wget http://swdownloads.analog.com/cse/travis_builds/master_latest_libad9361-iio-osx_10.12.tar.gz ; \ - tar xvf *.tar.gz ; \ - cd ad9361* ; \ - mv usr/local/lib/ad9361.framework/Versions/Current/ad9361 ../libad9361.dylib ; \ - cd .. ; \ - rm -rf ad9361-*-Darwin ; \ - rm *.tar.gz ; \ - cd .. ; \ - mkdir win ; \ - cd win ; \ - wget "https://github.com/analogdevicesinc/libad9361-iio/releases/download/v0.2/libad9361-0.2-win64.zip" -O lib.zip ; \ - unzip lib.zip ; \ - mv libad9361-win64/* . ; \ - rm -rf libad9361-win64 ; \ - rm *.h ; \ - rm lib.zip - -test_installer: - cd ../.. ; \ - cp *.mltbx test/ ; \ - cp hdl/vendor/AnalogDevices/hdlcoder_board_customization.m test/hdlcoder_board_customization_local.m ; \ - sed -i "s/hdlcoder_board_customization/hdlcoder_board_customization_local/g" test/hdlcoder_board_customization_local.m ; \ - ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "cd('test');runInstallerTests('$(BOARD)');" - -test: - cd ../.. ; \ - ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "cd('test');runTests('$(BOARD)');" - -test_ad4130: - cd ../.. ; \ - ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "cd('test');runAD4130Tests('$(BOARD)');" - -test_streaming: - cd ../.. ; \ - ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "addpath(genpath('test'));addpath(genpath('deps'));runHWTests;" - -test_evm: - cd ../.. ; \ - ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "addpath(genpath('test'));addpath(genpath('deps'));hwTestRunner;" - -test_modem: - cd ../.. ; \ - ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "addpath(genpath('hdl'));cd('targeting');addpath(genpath('modem-qpsk'))" - -test_synth: - bash synth_designs.sh $(BOARD) - -test_targeting_demos: - bash targeting_designs.sh - -lte_pa_app: - cd ../../trx_examples/streaming/LTE_PA_App/ ; \ - bash genInstaller.sh $(MLPATH) $(MLRELEASE) $(MLFLAGS) - -gen_tlbx: - ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "genTlbx($(INCLUDE_EXAMPLES));exit();" - -linter: - ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "linter;exit();" - -doc: - ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "cd('../doc');genhtml();exit();" - -zip: - cd ../.. ; \ - mkdir zip ; \ - zip -r zip/AnalogDevicesBSP_$(GITTAG).zip deps doc hdl hil_models targeting info.xml LICENSE README.md test/*.log \ No newline at end of file diff --git a/CI/scripts/adi_env.tcl b/CI/scripts/adi_env.tcl deleted file mode 100644 index 4e48bd9..0000000 --- a/CI/scripts/adi_env.tcl +++ /dev/null @@ -1,25 +0,0 @@ - -# environment related stuff - -set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] - - -if [info exists ::env(ADI_HDL_DIR)] { - set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)] -} - - -# This helper pocedure retrieves the value of varible from environment if exists, -# other case returns the provided default value -# name - name of the environment variable -# default_value - returned vale in case environment variable does not exists -proc get_env_param {name default_value} { - if [info exists ::env($name)] { - puts "Getting from environment the parameter: $name=$::env($name) " - return $::env($name) - } else { - return $default_value - } -} - - diff --git a/CI/scripts/adi_ip.tcl b/CI/scripts/adi_ip.tcl deleted file mode 100644 index 301af4e..0000000 --- a/CI/scripts/adi_ip.tcl +++ /dev/null @@ -1,660 +0,0 @@ - -source hdl/library/scripts/adi_xilinx_device_info_enc.tcl - -# check tool version - -if {![info exists REQUIRED_VIVADO_VERSION]} { - set REQUIRED_VIVADO_VERSION "2019.1" -} - -if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { - set IGNORE_VERSION_CHECK 1 -} elseif {![info exists IGNORE_VERSION_CHECK]} { - set IGNORE_VERSION_CHECK 0 -} - -## Add a ttcl file to the project. XDC does not support if statements -# in constraint definitions, this file can be used to add parameter dependent -# constraints to the IP. -# -# \param[ip_name] - IP name -# \param[ip_constr_files] - .ttcl file name (full path) -# -proc adi_ip_ttcl {ip_name ip_constr_files} { - - set cdir [pwd] - set m_file "" - set ip_constr_files_clean "" - foreach m_file $ip_constr_files { - file copy -force $m_file $cdir - set m_file [file tail $m_file] - lappend ip_constr_files_clean $m_file - } - set ip_constr_files $ip_constr_files_clean - - set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] - set f [ipx::add_file $ip_constr_files $proj_filegroup] - set_property -dict [list \ - type ttcl \ - ] $f - ipx::reorder_files -front $ip_constr_files $proj_filegroup -} - -## Add ttcl file to generate simulation files for System Verilog environments. -# -# \param[ip_name] - IP name -# \param[ip_constr_files] - .ttcl file name (full path) -# -proc adi_ip_sim_ttcl {ip_name ip_files} { - - set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] - set f [ipx::add_file $ip_files $proj_filegroup] - set_property -dict [list \ - type ttcl \ - ] $f - ipx::reorder_files -front $ip_files $proj_filegroup -} - -## Add a block design, defined by a tcl source, to the IP. -# -# \param[ip_name] - IP name -# \param[ip_bd_files] - Tcl source file -# -proc adi_ip_bd {ip_name ip_bd_files} { - set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] - if {$proj_filegroup == {}} { - set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] - } - - foreach file $ip_bd_files { - set f [ipx::add_file $file $proj_filegroup] - set_property -dict [list \ - type tclSource \ - ] $f - } -} - -## Infers an AXI Streaming interface. Note that the interface has to exist. -# -# \param[ip_name] - IP name -# -proc adi_ip_infer_streaming_interfaces {ip_name} { - - ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] - -} - -## Infers an AXI Memory Mapped interface. Note that the interface has to exist. -# -# \param[ip_name] - IP name -# -proc adi_ip_infer_mm_interfaces {ip_name} { - - ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] - -} - -## Defines a dependency for a port. -# -# \param[port_prefix] - Port prefix, which defines an interface. All ports of an -# interface must have the same prefix. If it's a single port, the whole name -# shall be defined. -# \param[dependency] - Dependency (e.g "PARAMETER_NAME == 1") ??? {spirit:decode(id('MODELPARAM_VALUE.PARAM_NAME')) == CONST} -# \param[driver_value] - Driver value is optional. It defines the default driver -# value of the port. -# -proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { - foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { - set_property ENABLEMENT_DEPENDENCY $dependency $port - if {$driver_value != {}} { - set_property DRIVER_VALUE $driver_value $port - } - } -} - -## Defines a dependency for a bus. -# -# \param[bus] - Name of the bus -# \param[prefix] - Port prefix, in general same as the name of the bus -# \param[dependency] - Dependency (e.g "PARAMETER_NAME == 1") ??? {spirit:decode(id('MODELPARAM_VALUE.PARAM_NAME')) == CONST} -# -proc adi_set_bus_dependency {bus prefix dependency} { - set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] - adi_set_ports_dependency $prefix $dependency 0 -} - -## Add a new port map definition to a bus interface. -# -# \param[bus] - Name of the bus interface -# \param[phys] - Physical name of the port -# \param[logic] - Logic name of the port (defined by the interface) -# -proc adi_add_port_map {bus phys logic} { - set map [ipx::add_port_map $phys $bus] - set_property "PHYSICAL_NAME" $phys $map - set_property "LOGICAL_NAME" $logic $map -} - -## Infers a new bus interface to an IP. -# -# \param[bus_name] - Bus name -# \param[mode] - Interface mode (master/slave) -# \param[abs_type] - Abstraction type, example: "xilinx.com:interface:axis_rtl:1.0" -# \param[bus_type] - Bus type, example: "xilinx.com:interface:axis:1.0" -# \param[port_maps] - Port map -# -# Port map example:\n -# [list \n -# {"m_axis_ready" "TREADY"}\n -# {"m_axis_valid" "TVALID"}\n -# {"m_axis_data" "TDATA"} ]\n - -proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { - set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] - - set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus - set_property "BUS_TYPE_VLNV" $bus_type $bus - set_property "INTERFACE_MODE" $mode $bus - - foreach port_map $port_maps { - adi_add_port_map $bus {*}$port_map - } -} - -## Add multiple bus interfaces of the same type to an IP. -# -# \param[num] - Number of interfaces -# \param[bus_name_prefix] - Prefix of the name of the interface -# \param[mode] - Interface mode (master/slave) -# \param[abs_type] - Abstraction type, example: "xilinx.com:interface:axis_rtl:1.0" -# \param[bus_type] - Bus type, example: "xilinx.com:interface:axis:1.0" -# \param[port_maps] - Port map, example: [list \n -# {"m_axis_ready" "TREADY"}\n -# {"m_axis_valid" "TVALID"}\n: -# {"m_axis_data" "TDATA"} ]\n -# \param[dependency] - Dependency (e.g "PARAMETER_NAME == 1") ??? {spirit:decode(id('MODELPARAM_VALUE.PARAM_NAME')) == CONST} -# -proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { - for {set i 0} {$i < $num} {incr i} { - set bus_name [format "%s%d" $bus_name_prefix $i] - set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] - - set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus - set_property "BUS_TYPE_VLNV" $bus_type $bus - set_property "INTERFACE_MODE" $mode $bus - - if {$dependency ne ""} { - set bus_dependency [string map [list "{i}" $i] $dependency] - set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus - } - - foreach port_map $port_maps { - lassign $port_map phys logic width - set map [ipx::add_port_map $phys $bus] - set_property "PHYSICAL_NAME" $phys $map - set_property "LOGICAL_NAME" $logic $map - set_property "PHYSICAL_RIGHT" [expr $i*$width] $map - set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map - } - } -} - -## Assign clock and reset to an interface bus. -# -# \param[clock_signal_name] - Clock name -# \param[bus_inf_name] - Interface bus name. Note: If multiple interfaces uses -# the same clock, all shall be defined here. (e.g. "s_axis:m_axis") -# \param[reset_signal_name] - Reset signal name -# \param[reset_signal_mode] - Reset mode (master/slave) -# -proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { - set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] - set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] - set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] - set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf - set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf - set_property display_name $clock_inf_name $clock_inf - set clock_map [ipx::add_port_map "CLK" $clock_inf] - set_property physical_name $clock_signal_name $clock_map - - set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] - set_property value $bus_inf_name $assoc_busif - - if { $reset_signal_name != "" } { - set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] - set_property value $reset_signal_name $assoc_reset - - set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] - set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] - set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf - set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf - set_property display_name $reset_inf_name $reset_inf - set_property interface_mode $reset_signal_mode $reset_inf - set reset_map [ipx::add_port_map "RST" $reset_inf] - set_property physical_name $reset_signal_name $reset_map - - set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] - if {[string match {*[Nn]} $reset_signal_name] == 1} { - set_property value "ACTIVE_LOW" $reset_polarity - } else { - set_property value "ACTIVE_HIGH" $reset_polarity - } - } -} - -## Defines an IP as the current IP's dependency. -# -# \param[vlnvs] - VLNVs of the instantiated IPs (e.g. "analog.com:user:util_cdc:1.0") -# -proc adi_ip_add_core_dependencies {vlnvs} { - foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { - foreach vlnv $vlnvs { - ipx::add_subcore $vlnv $file_group - } - } -} - -## List of all constraint files -# -set ip_constr_files "" - -## Create a project which will be packed as an IP. -# -# \param[ip_name] - IP name -# -proc adi_ip_create {ip_name} { - - global ad_hdl_dir - global ad_ghdl_dir - global ip_constr_files - global REQUIRED_VIVADO_VERSION - global IGNORE_VERSION_CHECK - - set VIVADO_VERSION [version -short] - if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { - puts -nonewline "CRITICAL WARNING: vivado version mismatch; " - puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " - puts -nonewline "got $VIVADO_VERSION.\n" - } - - create_project $ip_name . -force - - ## Load custom message severity definitions - source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl - - set ip_constr_files "" - set lib_dirs $ad_hdl_dir/library - if {$ad_hdl_dir ne $ad_ghdl_dir} { - lappend lib_dirs $ad_ghdl_dir/library - } - - set_property ip_repo_paths $lib_dirs [current_fileset] - update_ip_catalog -} - -## Add all source files to the IP's project. -# -# \param[ip_name] - The ip name -# \param[ip_files] - IP files (*.v *.vhd *.xdc) -# -proc adi_ip_files {ip_name ip_files} { - - global ip_constr_files - - set cdir [pwd] - set ip_constr_files "" - set ip_files_clean "" - foreach m_file $ip_files { - file copy -force $m_file $cdir - set m_file [file tail $m_file] - puts $m_file - if {[file extension $m_file] eq ".xdc"} { - lappend ip_constr_files $m_file - } - lappend ip_files_clean $m_file - } - - set ip_files $ip_files_clean - - set proj_fileset [get_filesets sources_1] - add_files -norecurse -scan_for_includes -fileset $proj_fileset $ip_files - add_files -norecurse -copy_to $cdir -force -fileset $proj_fileset $ip_files - set_property "top" "$ip_name" $proj_fileset -} - -## Pack the IP and set its proprieties. -# -# \param[ip_name] - The ip name -# -proc adi_ip_properties_lite {ip_name} { - - global ip_constr_files - - ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices - set_property name $ip_name [ipx::current_core] - set_property vendor_display_name {Analog Devices} [ipx::current_core] - set_property company_url {http://www.analog.com} [ipx::current_core] - - set i_families "" - foreach i_part [get_parts] { - lappend i_families [get_property FAMILY $i_part] - } - set i_families [lsort -unique $i_families] - set s_families [get_property supported_families [ipx::current_core]] - foreach i_family $i_families { - set s_families "$s_families $i_family Production" - set s_families "$s_families $i_family Beta" - } - set_property supported_families $s_families [ipx::current_core] - ipx::save_core - - ipx::remove_all_bus_interface [ipx::current_core] - set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] - foreach map $memory_maps { - ipx::remove_memory_map [lindex $map 2] [ipx::current_core ] - } - ipx::save_core - - set i_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] - foreach i_file $ip_constr_files { - set i_module [file tail $i_file] - regsub {_constr\.xdc} $i_module {} i_module - ipx::add_file $i_file $i_filegroup - ipx::reorder_files -front $i_file $i_filegroup - set_property SCOPED_TO_REF $i_module [ipx::get_files $i_file -of_objects $i_filegroup] - } - ipx::save_core -} - -## Set AXI interface IP proprieties. -# -# \param[ip_name] - The ip name -# -proc adi_ip_properties {ip_name} { - - adi_ip_properties_lite $ip_name - - ipx::infer_bus_interface {\ - s_axi_awvalid \ - s_axi_awaddr \ - s_axi_awprot \ - s_axi_awready \ - s_axi_wvalid \ - s_axi_wdata \ - s_axi_wstrb \ - s_axi_wready \ - s_axi_bvalid \ - s_axi_bresp \ - - s_axi_bready \ - s_axi_arvalid \ - s_axi_araddr \ - s_axi_arprot \ - s_axi_arready \ - s_axi_rvalid \ - s_axi_rdata \ - s_axi_rresp \ - s_axi_rready} \ - xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] - - ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] - ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] - - set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] - set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] - - if {$raddr_width != $waddr_width} { - puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] - set range 65536 - } else { - if {$raddr_width >= 16} { - set range 65536 - } else { - set range [expr 1 << $raddr_width] - } - } - - ipx::add_memory_map {s_axi} [ipx::current_core] - set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] - ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] - set_property range $range [ipx::get_address_blocks axi_lite \ - -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] - ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] - ipx::save_core -} - -## Create/overwrite temporary files containing particular build case dependencies. -# -# DO NOT USE FOR: axi_dmac/jesd204/axi_clkgen -# -proc adi_init_bd_tcl {} { - - global auto_set_param_list - global auto_set_param_list_overwritable - set cc [ipx::current_core] - - if { [file exists bd] } { - file delete -force bd - } - file mkdir bd - - set bd_tcl [open "bd/bd.tcl" w] - - puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" - puts $bd_tcl "proc init {cellpath otherInfo} {" - puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" - puts $bd_tcl "" - set auto_set_param "" - foreach i $auto_set_param_list { - if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { - append auto_set_param " $i \\\n" - } - } - if { $auto_set_param ne "" } { - puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" - regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param - puts $bd_tcl $auto_set_param - } - - set auto_set_overwritable_param "" - foreach i $auto_set_param_list_overwritable { - if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { - append auto_set_overwritable_param " $i \\\n" - } - } - if { $auto_set_overwritable_param ne "" } { - puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" - regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param - puts $bd_tcl $auto_set_overwritable_param - } - puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" - puts $bd_tcl "}" - puts $bd_tcl "" - puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" - puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" - puts $bd_tcl "" - puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" - puts $bd_tcl " set ip_param_list \[list_property \$ip\]" - puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" - puts $bd_tcl "" - puts $bd_tcl " set parent_dir \"../\"" - puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" - puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" - puts $bd_tcl " if { \[file exists \$linkname\] } {" - puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" - puts $bd_tcl " break" - puts $bd_tcl " }" - puts $bd_tcl " append parent_dir \"../\"" - puts $bd_tcl " }" - puts $bd_tcl "" - puts $bd_tcl " # Find predefindes auto assignable parameters" - puts $bd_tcl " foreach i \$auto_set_param_list {" - puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" - puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" - puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" - puts $bd_tcl " }" - puts $bd_tcl " }" - puts $bd_tcl "" - puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" - puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" - puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" - puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" - puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" - puts $bd_tcl " }" - puts $bd_tcl " }" - puts $bd_tcl "}" - puts $bd_tcl "" - close $bd_tcl - - set proj_fileset [get_filesets sources_1] - add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" - - set local_mk [open "temporary_case_dependencies.mk" w] - seek $local_mk 0 start - puts $local_mk "CLEAN_TARGET += bd" - puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" - close $local_mk -} - -## Search after device specific parameters and call the adi_add_device_spec_param -# process with the result. The list of these parameters are defined in -# library/scripts/adi_xilinx_device_info_enc.tcl -# -proc adi_add_auto_fpga_spec_params {} { - - global auto_set_param_list - global auto_set_param_list_overwritable - set cc [ipx::current_core] - - foreach i $auto_set_param_list { - if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { - adi_add_device_spec_param $i - } - } - foreach i $auto_set_param_list_overwritable { - if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { - adi_add_device_spec_param $i - } - } -} - -## Generate validation properties for a parameter, using predefined ranges or -# set of values (the definition of the ranges can be found in -# library/scripts/adi_xilinx_device_info_enc.tcl). -# -# \param[ip_parameter] - name of the HDL parameter -# -proc adi_add_device_spec_param {ip_param} { - - set cc [ipx::current_core] - - set list_pointer [string tolower $ip_param] - set list_pointer [append list_pointer "_list"] - - global $list_pointer - - # set j 1D list from the original list - foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} - - # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) - if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { - set_property -dict [list \ - "value_validation_type" "range" \ - "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ - "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ - [ipx::get_user_parameters $ip_param -of_objects $cc] - } else { - set_property -dict [list \ - "value_validation_type" "pairs" \ - "value_validation_pairs" $j ] \ - [ipx::get_user_parameters $ip_param -of_objects $cc] - } - - # FPGA info grup - set info_group_name "FPGA info" - set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] - if { [string trim $info_group] eq "" } { - set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] - set info_group [ipgui::add_group -name $info_group_name -component $cc \ - -parent $page0 -display_name $info_group_name] - } - - set p [ipgui::get_guiparamspec -name $ip_param -component $cc] - set_property -dict [list "widget" "comboBox" ] $p - ipgui::move_param -component $cc -order 0 $p -parent $info_group -} - -## Define a custom interface bus. -# -# \param[name] - Interface name -# -proc adi_if_define {name} { - - ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 - ipx::create_bus_definition analog.com interface $name 1.0 - - set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] - set_property xml_file_name ${name}.xml [ipx::current_busdef] - set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] - - ipx::save_abstraction_definition [ipx::current_busabs] - ipx::save_bus_definition [ipx::current_busdef] -} - -## Add ports to a custom interface bus. -# -# \param[dir] - Port direction -# \param[width] - Port width -# \param[name] - Port logical name -# \param[type] - Type of the port (default "none") -# -proc adi_if_ports {dir width name {type none}} { - - ipx::add_bus_abstraction_port $name [ipx::current_busabs] - set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] - set_property master_presence required $m_intf - set_property slave_presence required $m_intf - set_property master_width $width $m_intf - set_property slave_width $width $m_intf - - set m_dir "in" - set s_dir "out" - if {$dir eq "output"} { - set m_dir "out" - set s_dir "in" - } - - set_property master_direction $m_dir $m_intf - set_property slave_direction $s_dir $m_intf - - if {$type ne "none"} { - set_property is_${type} true $m_intf - } - - ipx::save_bus_definition [ipx::current_busdef] - ipx::save_abstraction_definition [ipx::current_busabs] -} - -## Infers a new bus interface to an IP. -# -# \param[if_name] - Interface bus name -# \param[mode] - Type of the interface bus (master/slave) -# \param[name] - Interface bus instance name -# \param[maps] - Mapping of the physical ports -# -proc adi_if_infer_bus {if_name mode name maps} { - - ipx::add_bus_interface $name [ipx::current_core] - set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] - set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if - set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if - set_property interface_mode $mode $m_bus_if - - foreach map $maps { - set m_maps [regexp -all -inline {\S+} $map] - lassign $m_maps p_name p_map - ipx::add_port_map $p_name $m_bus_if - set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] - } -} - diff --git a/CI/scripts/adi_ip_xilinx.tcl b/CI/scripts/adi_ip_xilinx.tcl deleted file mode 100644 index 45fdadb..0000000 --- a/CI/scripts/adi_ip_xilinx.tcl +++ /dev/null @@ -1,657 +0,0 @@ - -source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl - -# check tool version - -if {![info exists REQUIRED_VIVADO_VERSION]} { - set REQUIRED_VIVADO_VERSION "2019.1" -} - -if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { - set IGNORE_VERSION_CHECK 1 -} elseif {![info exists IGNORE_VERSION_CHECK]} { - set IGNORE_VERSION_CHECK 0 -} - -## Add a ttcl file to the project. XDC does not support if statements -# in constraint definitions, this file can be used to add parameter dependent -# constraints to the IP. -# -# \param[ip_name] - IP name -# \param[ip_constr_files] - .ttcl file name (full path) -# -proc adi_ip_ttcl {ip_name ip_constr_files} { - - set cdir [pwd] - set m_file "" - set ip_constr_files_clean "" - foreach m_file $ip_constr_files { - file copy -force $m_file $cdir - set m_file [file tail $m_file] - lappend ip_constr_files_clean $m_file - } - set ip_constr_files $ip_constr_files_clean - - set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] - set f [ipx::add_file $ip_constr_files $proj_filegroup] - set_property -dict [list \ - type ttcl \ - ] $f - ipx::reorder_files -front $ip_constr_files $proj_filegroup -} - -## Add ttcl file to generate simulation files for System Verilog environments. -# -# \param[ip_name] - IP name -# \param[ip_constr_files] - .ttcl file name (full path) -# -proc adi_ip_sim_ttcl {ip_name ip_files} { - - set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] - set f [ipx::add_file $ip_files $proj_filegroup] - set_property -dict [list \ - type ttcl \ - ] $f - ipx::reorder_files -front $ip_files $proj_filegroup -} - -## Add a block design, defined by a tcl source, to the IP. -# -# \param[ip_name] - IP name -# \param[ip_bd_files] - Tcl source file -# -proc adi_ip_bd {ip_name ip_bd_files} { - set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] - if {$proj_filegroup == {}} { - set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] - } - - foreach file $ip_bd_files { - set f [ipx::add_file $file $proj_filegroup] - set_property -dict [list \ - type tclSource \ - ] $f - } -} - -## Infers an AXI Streaming interface. Note that the interface has to exist. -# -# \param[ip_name] - IP name -# -proc adi_ip_infer_streaming_interfaces {ip_name} { - - ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] - -} - -## Infers an AXI Memory Mapped interface. Note that the interface has to exist. -# -# \param[ip_name] - IP name -# -proc adi_ip_infer_mm_interfaces {ip_name} { - - ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] - -} - -## Defines a dependency for a port. -# -# \param[port_prefix] - Port prefix, which defines an interface. All ports of an -# interface must have the same prefix. If it's a single port, the whole name -# shall be defined. -# \param[dependency] - Dependency (e.g "PARAMETER_NAME == 1") ??? {spirit:decode(id('MODELPARAM_VALUE.PARAM_NAME')) == CONST} -# \param[driver_value] - Driver value is optional. It defines the default driver -# value of the port. -# -proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { - foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { - set_property ENABLEMENT_DEPENDENCY $dependency $port - if {$driver_value != {}} { - set_property DRIVER_VALUE $driver_value $port - } - } -} - -## Defines a dependency for a bus. -# -# \param[bus] - Name of the bus -# \param[prefix] - Port prefix, in general same as the name of the bus -# \param[dependency] - Dependency (e.g "PARAMETER_NAME == 1") ??? {spirit:decode(id('MODELPARAM_VALUE.PARAM_NAME')) == CONST} -# -proc adi_set_bus_dependency {bus prefix dependency} { - set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] - adi_set_ports_dependency $prefix $dependency 0 -} - -## Add a new port map definition to a bus interface. -# -# \param[bus] - Name of the bus interface -# \param[phys] - Physical name of the port -# \param[logic] - Logic name of the port (defined by the interface) -# -proc adi_add_port_map {bus phys logic} { - set map [ipx::add_port_map $phys $bus] - set_property "PHYSICAL_NAME" $phys $map - set_property "LOGICAL_NAME" $logic $map -} - -## Infers a new bus interface to an IP. -# -# \param[bus_name] - Bus name -# \param[mode] - Interface mode (master/slave) -# \param[abs_type] - Abstraction type, example: "xilinx.com:interface:axis_rtl:1.0" -# \param[bus_type] - Bus type, example: "xilinx.com:interface:axis:1.0" -# \param[port_maps] - Port map -# -# Port map example:\n -# [list \n -# {"m_axis_ready" "TREADY"}\n -# {"m_axis_valid" "TVALID"}\n -# {"m_axis_data" "TDATA"} ]\n - -proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { - set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] - - set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus - set_property "BUS_TYPE_VLNV" $bus_type $bus - set_property "INTERFACE_MODE" $mode $bus - - foreach port_map $port_maps { - adi_add_port_map $bus {*}$port_map - } -} - -## Add multiple bus interfaces of the same type to an IP. -# -# \param[num] - Number of interfaces -# \param[bus_name_prefix] - Prefix of the name of the interface -# \param[mode] - Interface mode (master/slave) -# \param[abs_type] - Abstraction type, example: "xilinx.com:interface:axis_rtl:1.0" -# \param[bus_type] - Bus type, example: "xilinx.com:interface:axis:1.0" -# \param[port_maps] - Port map, example: [list \n -# {"m_axis_ready" "TREADY"}\n -# {"m_axis_valid" "TVALID"}\n: -# {"m_axis_data" "TDATA"} ]\n -# \param[dependency] - Dependency (e.g "PARAMETER_NAME == 1") ??? {spirit:decode(id('MODELPARAM_VALUE.PARAM_NAME')) == CONST} -# -proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { - for {set i 0} {$i < $num} {incr i} { - set bus_name [format "%s%d" $bus_name_prefix $i] - set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] - - set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus - set_property "BUS_TYPE_VLNV" $bus_type $bus - set_property "INTERFACE_MODE" $mode $bus - - if {$dependency ne ""} { - set bus_dependency [string map [list "{i}" $i] $dependency] - set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus - } - - foreach port_map $port_maps { - lassign $port_map phys logic width width_dep - set map [ipx::add_port_map $phys $bus] - set_property "PHYSICAL_NAME" $phys $map - set_property "LOGICAL_NAME" $logic $map - set_property "PHYSICAL_RIGHT" [expr $i*$width] $map - set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map - if {$width_dep ne ""} { - set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map - set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map - set width_dep_r "(($width_dep) * $i)" - set width_dep_l "(($width_dep) * ($i + 1)-1)" - set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map - set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map - } - } - } -} - -## Assign clock and reset to an interface bus. -# -# \param[clock_signal_name] - Clock name -# \param[bus_inf_name] - Interface bus name. Note: If multiple interfaces uses -# the same clock, all shall be defined here. (e.g. "s_axis:m_axis") -# \param[reset_signal_name] - Reset signal name -# \param[reset_signal_mode] - Reset mode (master/slave) -# -proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { - set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] - set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] - set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] - set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf - set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf - set_property display_name $clock_inf_name $clock_inf - set clock_map [ipx::add_port_map "CLK" $clock_inf] - set_property physical_name $clock_signal_name $clock_map - - set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] - set_property value $bus_inf_name $assoc_busif - - if { $reset_signal_name != "" } { - set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] - set_property value $reset_signal_name $assoc_reset - - set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] - set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] - set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf - set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf - set_property display_name $reset_inf_name $reset_inf - set_property interface_mode $reset_signal_mode $reset_inf - set reset_map [ipx::add_port_map "RST" $reset_inf] - set_property physical_name $reset_signal_name $reset_map - - set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] - if {[string match {*[Nn]} $reset_signal_name] == 1} { - set_property value "ACTIVE_LOW" $reset_polarity - } else { - set_property value "ACTIVE_HIGH" $reset_polarity - } - } -} - -## Defines an IP as the current IP's dependency. -# -# \param[vlnvs] - VLNVs of the instantiated IPs (e.g. "analog.com:user:util_cdc:1.0") -# -proc adi_ip_add_core_dependencies {vlnvs} { - foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { - foreach vlnv $vlnvs { - ipx::add_subcore $vlnv $file_group - } - } -} - -## List of all constraint files -# -set ip_constr_files "" - -## Create a project which will be packed as an IP. -# -# \param[ip_name] - IP name -# -proc adi_ip_create {ip_name} { - - global ad_hdl_dir - global ip_constr_files - global REQUIRED_VIVADO_VERSION - global IGNORE_VERSION_CHECK - - set VIVADO_VERSION [version -short] - if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { - puts -nonewline "CRITICAL WARNING: vivado version mismatch; " - puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " - puts -nonewline "got $VIVADO_VERSION.\n" - } - - create_project $ip_name . -force - - ## Load custom message severity definitions - source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl - - set ip_constr_files "" - set lib_dirs $ad_hdl_dir/library - - set_property ip_repo_paths $lib_dirs [current_fileset] - update_ip_catalog -} - -## Add all source files to the IP's project. -# -# \param[ip_name] - The ip name -# \param[ip_files] - IP files (*.v *.vhd *.xdc) -# -proc adi_ip_files {ip_name ip_files} { - - global ip_constr_files - - set cdir [pwd] - set ip_constr_files "" - set ip_files_clean "" - foreach m_file $ip_files { - file copy -force $m_file $cdir - set m_file [file tail $m_file] - puts $m_file - if {[file extension $m_file] eq ".xdc"} { - lappend ip_constr_files $m_file - } - lappend ip_files_clean $m_file - } - - set ip_files $ip_files_clean - - set proj_fileset [get_filesets sources_1] - add_files -norecurse -scan_for_includes -fileset $proj_fileset $ip_files - add_files -norecurse -copy_to $cdir -force -fileset $proj_fileset $ip_files - set_property "top" "$ip_name" $proj_fileset -} - -## Pack the IP and set its proprieties. -# -# \param[ip_name] - The ip name -# -proc adi_ip_properties_lite {ip_name} { - - global ip_constr_files - - ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices - set_property name $ip_name [ipx::current_core] - set_property vendor_display_name {Analog Devices} [ipx::current_core] - set_property company_url {http://www.analog.com} [ipx::current_core] - - set i_families "" - foreach i_part [get_parts] { - lappend i_families [get_property FAMILY $i_part] - } - set i_families [lsort -unique $i_families] - set s_families [get_property supported_families [ipx::current_core]] - foreach i_family $i_families { - set s_families "$s_families $i_family Production" - set s_families "$s_families $i_family Beta" - } - set_property supported_families $s_families [ipx::current_core] - - ipx::save_core [ipx::current_core] - - ipx::remove_all_bus_interface [ipx::current_core] - set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] - foreach map $memory_maps { - ipx::remove_memory_map [lindex $map 2] [ipx::current_core] - } - - ipx::update_checksums [ipx::current_core] - ipx::save_core [ipx::current_core] -} - -## Set AXI interface IP proprieties. -# -# \param[ip_name] - The ip name -# -proc adi_ip_properties {ip_name} { - - adi_ip_properties_lite $ip_name - - ipx::infer_bus_interface {\ - s_axi_awvalid \ - s_axi_awaddr \ - s_axi_awprot \ - s_axi_awready \ - s_axi_wvalid \ - s_axi_wdata \ - s_axi_wstrb \ - s_axi_wready \ - s_axi_bvalid \ - s_axi_bresp \ - - s_axi_bready \ - s_axi_arvalid \ - s_axi_araddr \ - s_axi_arprot \ - s_axi_arready \ - s_axi_rvalid \ - s_axi_rdata \ - s_axi_rresp \ - s_axi_rready} \ - xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] - - ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] - ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] - - set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] - set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] - - if {$raddr_width != $waddr_width} { - puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] - set range 65536 - } else { - if {$raddr_width >= 16} { - set range 65536 - } else { - set range [expr 1 << $raddr_width] - } - } - - ipx::add_memory_map {s_axi} [ipx::current_core] - set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] - ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] - set_property range $range [ipx::get_address_blocks axi_lite \ - -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] - ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] - ipx::save_core -} - -## Create/overwrite temporary files containing particular build case dependencies. -# -# DO NOT USE FOR: axi_dmac/jesd204/axi_clkgen -# -proc adi_init_bd_tcl {} { - - global auto_set_param_list - global auto_set_param_list_overwritable - set cc [ipx::current_core] - - if { [file exists bd] } { - file delete -force bd - } - file mkdir bd - - set bd_tcl [open "bd/bd.tcl" w] - - puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" - puts $bd_tcl "proc init {cellpath otherInfo} {" - puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" - puts $bd_tcl "" - set auto_set_param "" - foreach i $auto_set_param_list { - if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { - append auto_set_param " $i \\\n" - } - } - if { $auto_set_param ne "" } { - puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" - regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param - puts $bd_tcl $auto_set_param - } - - set auto_set_overwritable_param "" - foreach i $auto_set_param_list_overwritable { - if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { - append auto_set_overwritable_param " $i \\\n" - } - } - if { $auto_set_overwritable_param ne "" } { - puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" - regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param - puts $bd_tcl $auto_set_overwritable_param - } - puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" - puts $bd_tcl "}" - puts $bd_tcl "" - puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" - puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" - puts $bd_tcl "" - puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" - puts $bd_tcl " set ip_param_list \[list_property \$ip\]" - puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" - puts $bd_tcl "" - puts $bd_tcl " set parent_dir \"../\"" - puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" - puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" - puts $bd_tcl " if { \[file exists \$linkname\] } {" - puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" - puts $bd_tcl " break" - puts $bd_tcl " }" - puts $bd_tcl " append parent_dir \"../\"" - puts $bd_tcl " }" - puts $bd_tcl "" - puts $bd_tcl " # Find predefindes auto assignable parameters" - puts $bd_tcl " foreach i \$auto_set_param_list {" - puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" - puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" - puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" - puts $bd_tcl " }" - puts $bd_tcl " }" - puts $bd_tcl "" - puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" - puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" - puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" - puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" - puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" - puts $bd_tcl " }" - puts $bd_tcl " }" - puts $bd_tcl "}" - puts $bd_tcl "" - close $bd_tcl - - set proj_fileset [get_filesets sources_1] - add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" - - set local_mk [open "temporary_case_dependencies.mk" w] - seek $local_mk 0 start - puts $local_mk "CLEAN_TARGET += bd" - puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" - close $local_mk -} - -## Search after device specific parameters and call the adi_add_device_spec_param -# process with the result. The list of these parameters are defined in -# library/scripts/adi_xilinx_device_info_enc.tcl -# -proc adi_add_auto_fpga_spec_params {} { - - global auto_set_param_list - global auto_set_param_list_overwritable - set cc [ipx::current_core] - - foreach i $auto_set_param_list { - if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { - adi_add_device_spec_param $i - } - } - foreach i $auto_set_param_list_overwritable { - if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { - adi_add_device_spec_param $i - } - } -} - -## Generate validation properties for a parameter, using predefined ranges or -# set of values (the definition of the ranges can be found in -# library/scripts/adi_xilinx_device_info_enc.tcl). -# -# \param[ip_parameter] - name of the HDL parameter -# -proc adi_add_device_spec_param {ip_param} { - - set cc [ipx::current_core] - - set list_pointer [string tolower $ip_param] - set list_pointer [append list_pointer "_list"] - - global $list_pointer - - # set j 1D list from the original list - foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} - - # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) - if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { - set_property -dict [list \ - "value_validation_type" "range_long" \ - "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ - "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ - [ipx::get_user_parameters $ip_param -of_objects $cc] - } else { - set_property -dict [list \ - "value_validation_type" "pairs" \ - "value_validation_pairs" $j ] \ - [ipx::get_user_parameters $ip_param -of_objects $cc] - } - - # FPGA info grup - set info_group_name "FPGA info" - set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] - if { [string trim $info_group] eq "" } { - set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] - set info_group [ipgui::add_group -name $info_group_name -component $cc \ - -parent $page0 -display_name $info_group_name] - } - - set p [ipgui::get_guiparamspec -name $ip_param -component $cc] - set_property -dict [list "widget" "comboBox" ] $p - ipgui::move_param -component $cc -order 0 $p -parent $info_group -} - -## Define a custom interface bus. -# -# \param[name] - Interface name -# -proc adi_if_define {name} { - - ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 - ipx::create_bus_definition analog.com interface $name 1.0 - - set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] - set_property xml_file_name ${name}.xml [ipx::current_busdef] - set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] - - ipx::save_abstraction_definition [ipx::current_busabs] - ipx::save_bus_definition [ipx::current_busdef] -} - -## Add ports to a custom interface bus. -# -# \param[dir] - Port direction -# \param[width] - Port width -# \param[name] - Port logical name -# \param[type] - Type of the port (default "none") -# -proc adi_if_ports {dir width name {type none}} { - - ipx::add_bus_abstraction_port $name [ipx::current_busabs] - set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] - set_property master_presence required $m_intf - set_property slave_presence required $m_intf - set_property master_width $width $m_intf - set_property slave_width $width $m_intf - - set m_dir "in" - set s_dir "out" - if {$dir eq "output"} { - set m_dir "out" - set s_dir "in" - } - - set_property master_direction $m_dir $m_intf - set_property slave_direction $s_dir $m_intf - - if {$type ne "none"} { - set_property is_${type} true $m_intf - } - - ipx::save_bus_definition [ipx::current_busdef] - ipx::save_abstraction_definition [ipx::current_busabs] -} - -## Infers a new bus interface to an IP. -# -# \param[if_name] - Interface bus name -# \param[mode] - Type of the interface bus (master/slave) -# \param[name] - Interface bus instance name -# \param[maps] - Mapping of the physical ports -# -proc adi_if_infer_bus {if_name mode name maps} { - - ipx::add_bus_interface $name [ipx::current_core] - set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] - set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if - set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if - set_property interface_mode $mode $m_bus_if - - foreach map $maps { - set m_maps [regexp -all -inline {\S+} $map] - lassign $m_maps p_name p_map - ipx::add_port_map $p_name $m_bus_if - set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] - } -} - diff --git a/CI/scripts/adi_project.tcl b/CI/scripts/adi_project.tcl deleted file mode 100644 index 2173764..0000000 --- a/CI/scripts/adi_project.tcl +++ /dev/null @@ -1,215 +0,0 @@ - -variable p_board -variable p_device -variable sys_zynq -variable p_prcfg_init -variable p_prcfg_list -variable p_prcfg_status - -if {![info exists REQUIRED_VIVADO_VERSION]} { - set REQUIRED_VIVADO_VERSION "2019.1" -} - -if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { - set IGNORE_VERSION_CHECK 1 -} elseif {![info exists IGNORE_VERSION_CHECK]} { - set IGNORE_VERSION_CHECK 0 -} - -set p_board "not-applicable" -set p_device "none" -set sys_zynq 1 -set ADI_POWER_OPTIMIZATION 0 - -proc adi_project_xilinx {project_name project_dir update_tcl {mode 0} {parameter_list ""}} { - - global ad_hdl_dir - global ad_phdl_dir - global p_board - global p_device - global sys_zynq - global REQUIRED_VIVADO_VERSION - global IGNORE_VERSION_CHECK - - if [regexp "_ac701$" $project_name] { - set p_device "xc7a200tfbg676-2" - set p_board "xilinx.com:ac701:part0:1.0" - set sys_zynq 0 - } - if [regexp "_kc705$" $project_name] { - set p_device "xc7k325tffg900-2" - set p_board "xilinx.com:kc705:part0:1.1" - set sys_zynq 0 - } - if [regexp "_vc707$" $project_name] { - set p_device "xc7vx485tffg1761-2" - set p_board "xilinx.com:vc707:part0:1.1" - set sys_zynq 0 - } - if [regexp "_kcu105$" $project_name] { - set p_device "xcku040-ffva1156-2-e" - set p_board "xilinx.com:kcu105:part0:1.1" - set sys_zynq 0 - } - if [regexp "_zed$" $project_name] { - set p_device "xc7z020clg484-1" - set p_board "em.avnet.com:zed:part0:1.3" - set sys_zynq 1 - } - if [regexp "_microzed$" $project_name] { - set p_device "xc7z010clg400-1" - set p_board "not-applicable" - set sys_zynq 1 - } - if [regexp "_zc702$" $project_name] { - set p_device "xc7z020clg484-1" - set p_board "xilinx.com:zc702:part0:1.2" - set sys_zynq 1 - } - if [regexp "_zc706$" $project_name] { - set p_device "xc7z045ffg900-2" - set p_board "xilinx.com:zc706:part0:1.2" - set sys_zynq 1 - } - if [regexp "_mitx045$" $project_name] { - set p_device "xc7z045ffg900-2" - set p_board "not-applicable" - set sys_zynq 1 - } - if [regexp "_zcu102$" $project_name] { - set p_device "xczu9eg-ffvb1156-2-e" - set p_board "xilinx.com:zcu102:part0:3.1" - set sys_zynq 2 - } - - #Added - set project_name_org $project_name - set project_name vivado_prj - - set VIVADO_VERSION [version -short] - if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { - puts -nonewline "CRITICAL WARNING: vivado version mismatch; " - puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " - puts -nonewline "got $VIVADO_VERSION.\n" - } - - #Added - adi_setup_libs - - if {$mode == 0} { - set project_system_dir "./$project_name.srcs/sources_1/bd/system" - #Removed - #create_project $project_name . -part $p_device -force - } else { - set project_system_dir ".srcs/sources_1/bd/system" - #Removed - #create_project -in_memory -part $p_device - } - - if {$mode == 1} { - file mkdir $project_name.data - } - - if {$p_board ne "not-applicable"} { - set_property board_part $p_board [current_project] - } - - #Removed - #set lib_dirs $ad_hdl_dir/library - #if {$ad_hdl_dir ne $ad_phdl_dir} { - # lappend lib_dirs $ad_phdl_dir/library - #} - - #set_property ip_repo_paths $lib_dirs [current_fileset] - #update_ip_catalog - - set_msg_config -id {BD 41-1348} -new_severity info - set_msg_config -id {BD 41-1343} -new_severity info - set_msg_config -id {BD 41-1306} -new_severity info - set_msg_config -id {IP_Flow 19-1687} -new_severity info - set_msg_config -id {filemgmt 20-1763} -new_severity info - set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity error - - - #Added from adi_project_xilinx R2021a - # Set parameters of the top level file - # Make the same parameters available to system_bd.tcl - set proj_params [get_property generic [current_fileset]] - foreach {param value} $parameter_list { - lappend proj_params $param=$value - set ad_project_params($param) $value - } - - #Added - create_bd_design "system" - source $project_dir/system_bd.tcl - if {$project_name_org != "adrv9361z7035_ccbox_lvds_modem"} { - source $project_dir/$update_tcl - } - - set_property generic $proj_params [current_fileset] - regenerate_bd_layout - save_bd_design - validate_bd_design - - set_property synth_checkpoint_mode None [get_files $project_system_dir/system.bd] - generate_target {synthesis implementation} [get_files $project_system_dir/system.bd] - make_wrapper -files [get_files $project_system_dir/system.bd] -top - - if {$mode == 0} { - import_files -force -norecurse -fileset sources_1 $project_system_dir/hdl/system_wrapper.v - } else { - write_hwdef -file "$project_name.data/$project_name.hwdef" - } -} - -#Added -proc adi_setup_libs {} { - global ad_hdl_dir - global ad_phdl_dir - - set lib_dirs [get_property ip_repo_paths [current_fileset]] - - lappend lib_dirs $ad_hdl_dir/library - if {$ad_hdl_dir ne $ad_phdl_dir} { - lappend lib_dirs $ad_phdl_dir/library - } - - set_property ip_repo_paths $lib_dirs [current_fileset] - update_ip_catalog - adi_add_archive_ip $lib_dirs -} - -#Added -proc adi_add_archive_ip {lib_dirs} { - global ad_hdl_dir - global ad_phdl_dir - foreach libDir $lib_dirs { - set ipList [glob -nocomplain -directory $libDir *.zip] - foreach ipCore $ipList { - catch {update_ip_catalog -add_ip $ipCore -repo_path $libDir} - file delete -force $ipCore - } - } -} - -proc adi_project_files {project_name project_files} { - - global ad_hdl_dir - global ad_phdl_dir - global proj_dir - - #Added - cd $proj_dir - - add_files -norecurse -fileset sources_1 $project_files - set_property top system_top [current_fileset] - - #Added - cd $ad_hdl_dir -} - -proc adi_project_run {project_name} { - #Removed -} - diff --git a/CI/scripts/adi_project_xilinx.tcl b/CI/scripts/adi_project_xilinx.tcl deleted file mode 100644 index 6f49244..0000000 --- a/CI/scripts/adi_project_xilinx.tcl +++ /dev/null @@ -1,435 +0,0 @@ - -## Define the supported tool version -if {![info exists REQUIRED_VIVADO_VERSION]} { - set REQUIRED_VIVADO_VERSION "2019.1" -} - -## Define the ADI_IGNORE_VERSION_CHECK environment variable to skip version check -if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { - set IGNORE_VERSION_CHECK 1 -} elseif {![info exists IGNORE_VERSION_CHECK]} { - set IGNORE_VERSION_CHECK 0 -} - -## Define the ADI_USE_OOC_SYNTHESIS environment variable to enable out of context -# synthesis -if {[info exists ::env(ADI_USE_OOC_SYNTHESIS)]} { - set ADI_USE_OOC_SYNTHESIS 1 -} elseif {![info exists ADI_USE_OOC_SYNTHESIS]} { - set ADI_USE_OOC_SYNTHESIS 0 -} - -## Set to enable incremental compilation -set ADI_USE_INCR_COMP 1 - -## Set to enable power optimization -set ADI_POWER_OPTIMIZATION 0 - -## Initialize global variables -set p_board "not-applicable" -set p_device "none" -set sys_zynq 1 - -set p_prcfg_init "" -set p_prcfg_list "" -set p_prcfg_status "" - -## Creates a Xilinx project. -# -# \param[project_name] - name of the project -# \param[mode] - if set non-project mode will be used, otherwise project mode -# flow, see UG892 for more information -# \param[parameter_list] - a list of global parameters (parameters of the -# system_top module) -# -# Supported carrier names are: ac701, kc705, vc707, vcu118, kcu105, zed, -# microzed, zc702, zc706, mitx405, zcu102. -# -proc adi_project {project_name {mode 0} {parameter_list {}} } { - - global ad_hdl_dir - global p_board - global p_device - global sys_zynq - global REQUIRED_VIVADO_VERSION - global IGNORE_VERSION_CHECK - global ADI_USE_OOC_SYNTHESIS - global ADI_USE_INCR_COMP - - if [regexp "_ac701$" $project_name] { - set p_device "xc7a200tfbg676-2" - set p_board "xilinx.com:ac701:part0:1.0" - set sys_zynq 0 - } - if [regexp "_kc705$" $project_name] { - set p_device "xc7k325tffg900-2" - set p_board "xilinx.com:kc705:part0:1.1" - set sys_zynq 0 - } - if [regexp "_vc707$" $project_name] { - set p_device "xc7vx485tffg1761-2" - set p_board "xilinx.com:vc707:part0:1.1" - set sys_zynq 0 - } - if [regexp "_vcu118$" $project_name] { - set p_device "xcvu9p-flga2104-2L-e" - set p_board "xilinx.com:vcu118:part0:2.0" - set sys_zynq 0 - } - if [regexp "_kcu105$" $project_name] { - set p_device "xcku040-ffva1156-2-e" - set p_board "xilinx.com:kcu105:part0:1.1" - set sys_zynq 0 - } - if [regexp "_zed$" $project_name] { - set p_device "xc7z020clg484-1" - set p_board "em.avnet.com:zed:part0:1.3" - set sys_zynq 1 - } - if [regexp "_coraz7s$" $project_name] { - set p_device "xc7z007sclg400-1" - set p_board "not-applicable" - set sys_zynq 1 - } - if [regexp "_microzed$" $project_name] { - set p_device "xc7z010clg400-1" - set p_board "not-applicable" - set sys_zynq 1 - } - if [regexp "_zc702$" $project_name] { - set p_device "xc7z020clg484-1" - set p_board "xilinx.com:zc702:part0:1.2" - set sys_zynq 1 - } - if [regexp "_zc706$" $project_name] { - set p_device "xc7z045ffg900-2" - set p_board "xilinx.com:zc706:part0:1.2" - set sys_zynq 1 - } - if [regexp "_mitx045$" $project_name] { - set p_device "xc7z045ffg900-2" - set p_board "not-applicable" - set sys_zynq 1 - } - if [regexp "_zcu102$" $project_name] { - set p_device "xczu9eg-ffvb1156-2-e" - set p_board "xilinx.com:zcu102:part0:3.2" - set sys_zynq 2 - } - - set VIVADO_VERSION [version -short] - if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { - puts -nonewline "CRITICAL WARNING: vivado version mismatch; " - puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " - puts -nonewline "got $VIVADO_VERSION.\n" - } - - if {$mode == 0} { - set project_system_dir "./$project_name.srcs/sources_1/bd/system" - create_project $project_name . -part $p_device -force - } else { - set project_system_dir ".srcs/sources_1/bd/system" - create_project -in_memory -part $p_device - } - - if {$mode == 1} { - file mkdir $project_name.data - } - - if {$p_board ne "not-applicable"} { - set_property board_part $p_board [current_project] - } - - set lib_dirs $ad_hdl_dir/library - - # Set a common IP cache for all projects - if {$ADI_USE_OOC_SYNTHESIS == 1} { - if {[file exists $ad_hdl_dir/ipcache] == 0} { - file mkdir $ad_hdl_dir/ipcache - } - config_ip_cache -import_from_project -use_cache_location $ad_hdl_dir/ipcache - } - - set_property ip_repo_paths $lib_dirs [current_fileset] - update_ip_catalog - - ## Load custom message severity definitions - source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl - - ## In Vivado there is a limit for the number of warnings and errors which are - ## displayed by the tool for a particular error or warning; the default value - ## of this limit is 100. - ## Overrides the default limit to 2000. - set_param messaging.defaultLimit 2000 - - # Set parameters of the top level file - # Make the same parameters available to system_bd.tcl - set proj_params [get_property generic [current_fileset]] - foreach {param value} $parameter_list { - lappend proj_params $param=$value - set ad_project_params($param) $value - } - set_property generic $proj_params [current_fileset] - - create_bd_design "system" - source system_bd.tcl - - save_bd_design - validate_bd_design - - if {$ADI_USE_OOC_SYNTHESIS == 1} { - set_property synth_checkpoint_mode Hierarchical [get_files $project_system_dir/system.bd] - } else { - set_property synth_checkpoint_mode None [get_files $project_system_dir/system.bd] - } - generate_target {synthesis implementation} [get_files $project_system_dir/system.bd] - if {$ADI_USE_OOC_SYNTHESIS == 1} { - export_ip_user_files -of_objects [get_files $project_system_dir/system.bd] -no_script -sync -force -quiet - create_ip_run [get_files $project_system_dir/system.bd] - } - make_wrapper -files [get_files $project_system_dir/system.bd] -top - - if {$mode == 0} { - import_files -force -norecurse -fileset sources_1 $project_system_dir/hdl/system_wrapper.v - } else { - write_hwdef -file "$project_name.data/$project_name.hwdef" - } - - if {$ADI_USE_INCR_COMP == 1} { - if {[file exists ./reference.dcp]} { - set_property incremental_checkpoint ./reference.dcp [get_runs impl_1] - } - } - -} - -## Add source files to an exiting project. -# -# \param[project_name] - name of the project -# \param[project_files] - list of project files -# -proc adi_project_files {project_name project_files} { - - foreach pfile $project_files { - if {[string range $pfile [expr 1 + [string last . $pfile]] end] == "xdc"} { - add_files -norecurse -fileset constrs_1 $pfile - } else { - add_files -norecurse -fileset sources_1 $pfile - } - } - - # NOTE: top file name is always system_top - set_property top system_top [current_fileset] -} - -## Run an existing project (generate bit stream). -# -# \param[project_name] - name of the project -# -proc adi_project_run {project_name} { - - global ADI_POWER_OPTIMIZATION - global ADI_USE_OOC_SYNTHESIS - - if {$ADI_USE_OOC_SYNTHESIS == 1} { - launch_runs -jobs 4 system_*_synth_1 synth_1 - } else { - launch_runs synth_1 - } - wait_on_run synth_1 - open_run synth_1 - report_timing_summary -file timing_synth.log - - if {![info exists ::env(ADI_NO_BITSTREAM_COMPRESSION)] && ![info exists ADI_NO_BITSTREAM_COMPRESSION]} { - set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] - } - - if {$ADI_POWER_OPTIMIZATION == 1} { - set_property STEPS.POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1] - set_property STEPS.POST_PLACE_POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1] - } - - launch_runs impl_1 -to_step write_bitstream - wait_on_run impl_1 - open_run impl_1 - report_timing_summary -file timing_impl.log - - if {[info exists ::env(ADI_GENERATE_UTILIZATION)]} { - set csv_file resource_utilization.csv - if {[ catch { - xilinx::designutils::report_failfast -csv -file $csv_file -transpose -no_header -ignore_pr -quiet - set MMCM [llength [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ *MMCM* }]] - set PLL [llength [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ *PLL* }]] - set worst_slack_setup [get_property SLACK [get_timing_paths -setup]] - set worst_slack_hold [get_property SLACK [get_timing_paths -hold]] - - set fileRead [open $csv_file r] - set lines [split [read $fileRead] "\n"] - set names_line [lindex $lines end-3] - set values_line [lindex $lines end-2] - close $fileRead - - set fileWrite [open $csv_file w] - puts $fileWrite "$names_line,MMCM*,PLL*,Worst_Setup_Slack,Worst_Hold_Slack" - puts $fileWrite "$values_line,$MMCM,$PLL,$worst_slack_setup,$worst_slack_hold" - close $fileWrite - } issue ] != 0 } { - puts "GENERATE_REPORTS: tclapp::xilinx::designutils not installed" - } - } else { - puts "GENERATE_REPORTS: Resource utilization files won't be generated because ADI_GENERATE_UTILIZATION env var is not set" - } - - # Look for undefined clocks which do not show up in the timing summary - set timing_check [check_timing -override_defaults no_clock -no_header -return_string] - if {[regexp { (\d+) register} $timing_check -> num_regs]} { - - if {[info exist num_regs]} { - if {$num_regs > 0} { - puts "CRITICAL WARNING: There are $num_regs registers with no clocks !!! See no_clock.log for details." - check_timing -override_defaults no_clock -verbose -file no_clock.log - } - } - - } else { - puts "CRITICAL WARNING: The search for undefined clocks failed !!!" - } - - file mkdir $project_name.sdk - - if [expr [string match *VIOLATED* $[report_timing_summary -return_string]] == 1] { - file copy -force $project_name.runs/impl_1/system_top.sysdef $project_name.sdk/system_top_bad_timing.hdf - return -code error [format "ERROR: Timing Constraints NOT met!"] - } else { - file copy -force $project_name.runs/impl_1/system_top.sysdef $project_name.sdk/system_top.hdf - } -} - -## Run synthesis on an partial design; use it in Partial Reconfiguration flow. -# -# \param[project_name] - project name -# \param[prcfg_name] - name of the partial design -# \param[hdl_files] - hdl source of the partial design -# \param[xdc_files] - XDC constraint source of the partial design -# -proc adi_project_synth {project_name prcfg_name hdl_files {xdc_files ""}} { - - global p_device - - set p_prefix "$project_name.data/$project_name" - - if {$prcfg_name eq ""} { - - read_verilog .srcs/sources_1/bd/system/hdl/system_wrapper.v - read_verilog $hdl_files - read_xdc $xdc_files - - synth_design -mode default -top system_top -part $p_device > $p_prefix.synth.rds - write_checkpoint -force $p_prefix.synth.dcp - close_project - - } else { - - create_project -in_memory -part $p_device - read_verilog $hdl_files - synth_design -mode out_of_context -top "prcfg" -part $p_device > $p_prefix.${prcfg_name}_synth.rds - write_checkpoint -force $p_prefix.${prcfg_name}_synth.dcp - close_project - } -} - -## Run implementation on an partial design; use it in Partial Reconfiguration -# flow. -# -# \param[project_name] - project name -# \param[prcfg_name] - name of the partial design -# \param[xdc_files] - XDC constraint source of the partial design -# -proc adi_project_impl {project_name prcfg_name {xdc_files ""}} { - - global p_device - global p_prcfg_init - global p_prcfg_list - global p_prcfg_status - - set p_prefix "$project_name.data/$project_name" - - if {$prcfg_name eq "default"} { - set p_prcfg_status 0 - set p_prcfg_list "" - set p_prcfg_init "$p_prefix.${prcfg_name}_impl.dcp" - file mkdir $project_name.sdk - } - - if {$prcfg_name eq "default"} { - - open_checkpoint $p_prefix.synth.dcp -part $p_device - read_xdc $xdc_files - read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp - set_property HD.RECONFIGURABLE 1 [get_cells i_prcfg] - opt_design > $p_prefix.${prcfg_name}_opt.rds - write_debug_probes -force $p_prefix.${prcfg_name}_debug_nets.ltx - place_design > $p_prefix.${prcfg_name}_place.rds - route_design > $p_prefix.${prcfg_name}_route.rds - - } else { - - open_checkpoint $p_prefix.default_impl_bb.dcp -part $p_device - lock_design -level routing - read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp - read_xdc $xdc_files - opt_design > $p_prefix.${prcfg_name}_opt.rds - place_design > $p_prefix.${prcfg_name}_place.rds - route_design > $p_prefix.${prcfg_name}_route.rds - } - - write_checkpoint -force $p_prefix.${prcfg_name}_impl.dcp - report_utilization -pblocks pb_prcfg -file $p_prefix.${prcfg_name}_utilization.rpt - report_timing_summary -file $p_prefix.${prcfg_name}_timing_summary.rpt - - if [expr [get_property SLACK [get_timing_paths]] < 0] { - set p_prcfg_status 1 - puts "CRITICAL WARNING: Timing Constraints NOT met ($prcfg_name)!" - } - - write_checkpoint -force -cell i_prcfg $p_prefix.${prcfg_name}_prcfg_impl.dcp - update_design -cell i_prcfg -black_box - write_checkpoint -force $p_prefix.${prcfg_name}_impl_bb.dcp - open_checkpoint $p_prefix.${prcfg_name}_impl.dcp -part $p_device - write_bitstream -force -bin_file -file $p_prefix.${prcfg_name}.bit - write_sysdef -hwdef $p_prefix.hwdef -bitfile $p_prefix.${prcfg_name}.bit -file $p_prefix.${prcfg_name}.hdf - file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.${prcfg_name}.hdf - - if {$prcfg_name ne "default"} { - lappend p_prcfg_list "$p_prefix.${prcfg_name}_impl.dcp" - } - - if {$prcfg_name eq "default"} { - file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.hdf - } -} - -## Verify an implemented partial reconfiguration design, checks if all the -# partial design are compatible with the base design. -# -# \param[project_name] - project name -# -proc adi_project_verify {project_name} { - - # checkpoint for the default design - global p_prcfg_init - # list of checkpoints with all the PRs integrated into the default design - global p_prcfg_list - global p_prcfg_status - - set p_prefix "$project_name.data/$project_name" - - pr_verify -full_check -initial $p_prcfg_init \ - -additional $p_prcfg_list \ - -file $p_prefix.prcfg_verify.log - - if {$p_prcfg_status == 1} { - return -code error [format "ERROR: Timing Constraints NOT met!"] - } -} - diff --git a/CI/scripts/adi_xilinx_device_info_enc.tcl b/CI/scripts/adi_xilinx_device_info_enc.tcl deleted file mode 100644 index af8b840..0000000 --- a/CI/scripts/adi_xilinx_device_info_enc.tcl +++ /dev/null @@ -1,193 +0,0 @@ -## *************************************************************************** -## *************************************************************************** -## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. -## -## In this HDL repository, there are many different and unique modules, consisting -## of various HDL (Verilog or VHDL) components. The individual modules are -## developed independently, and may be accompanied by separate and unique license -## terms. -## -## The user should read each of these license terms, and understand the -## freedoms and responsibilities that he or she has by using this source/core. -## -## This core is distributed in the hope that it will be useful, but WITHOUT ANY -## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -## A PARTICULAR PURPOSE. -## -## Redistribution and use of source or resulting binaries, with or without modification -## of this file, are permitted under one of the following two license terms: -## -## 1. The GNU General Public License version 2 as published by the -## Free Software Foundation, which can be found in the top level directory -## of this repository (LICENSE_GPL2), and also online at: -## -## -## OR -## -## 2. An ADI specific BSD license, which can be found in the top level directory -## of this repository (LICENSE_ADIBSD), and also on-line at: -## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -## This will allow to generate bit files and not release the source code, -## as long as it attaches to an ADI device. -## -## *************************************************************************** -## *************************************************************************** - -# adi_xilinx_device_info_enc.tcl - -variable auto_set_param_list -variable auto_set_param_list_overwritable -variable fpga_series_list -variable fpga_family_list -variable speed_grade_list -variable dev_package_list -variable xcvr_type_list -variable fpga_voltage_list - -# Parameter list for automatic assignament -set auto_set_param_list { \ - DEV_PACKAGE \ - SPEED_GRADE \ - FPGA_FAMILY \ - FPGA_TECHNOLOGY } - -set auto_set_param_list_overwritable { \ - FPGA_VOLTAGE \ - XCVR_TYPE } - -# List for automatically assigned parameter values and encoded values -# The list name must be the parameter name (lowercase), appending "_list" to it -set fpga_technology_list { \ - { Unknown 0 } \ - { 7series 1 } \ - { ultrascale 2 } \ - { ultrascale+ 3 }} - -set fpga_family_list { \ - { Unknown 0 } \ - { artix 1 } \ - { kintex 2 } \ - { virtex 3 } \ - { zynq 4 }} - -set speed_grade_list { \ - { Unknown 0 } \ - { -1 10 } \ - { -1L 11 } \ - { -1H 12 } \ - { -1HV 13 } \ - { -1LV 14 } \ - { -2 20 } \ - { -2L 21 } \ - { -2LV 22 } \ - { -3 30 }} - -set dev_package_list { \ - { Unknown 0 } \ - { rf 1 } \ - { fl 2 } \ - { ff 3 } \ - { fb 4 } \ - { hc 5 } \ - { fh 6 } \ - { cs 7 } \ - { cp 8 } \ - { ft 9 } \ - { fg 10 } \ - { sb 11 } \ - { rb 12 } \ - { rs 13 } \ - { cl 14 } \ - { sf 15 } \ - { ba 16 } \ - { fa 17 }} - -set xcvr_type_list { \ - { Unknown 0 } \ - { GTPE2_NOT_SUPPORTED 1 } \ - { GTXE2 2 } \ - { GTHE2_NOT_SUPPORTED 3 } \ - { GTZE2_NOT_SUPPORTED 4 } \ - { GTHE3 5 } \ - { GTYE3_NOT_SUPPORTED 6 } \ - { GTRE4_NOT_SUPPORTED 7 } \ - { GTHE4 8 } \ - { GTYE4 9 } \ - { GTME4_NOT_SUPPORTED 10}} - -set fpga_voltage_list {0 5000} ;# 0 to 5000mV - - -## *************************************************************************** - -proc adi_device_spec {cellpath param} { - - set list_pointer [string tolower $param] - set list_pointer [append list_pointer "_list"] - - upvar 1 $list_pointer $list_pointer - - set ip [get_bd_cells $cellpath] - set part [get_property PART [current_project]] - - switch -regexp -- $param { - FPGA_TECHNOLOGY { - switch -regexp -- $part { - ^xc7 {set series_name 7series} - ^xczu {set series_name ultrascale+} - ^xc.u.p {set series_name ultrascale+} - ^xc.u {set series_name ultrascale } - default { - puts "Undefined fpga technology for \"$part\"!" - exit -1 - } - } - return "$series_name" - } - FPGA_FAMILY { - set fpga_family [get_property FAMILY $part] - foreach i $fpga_family_list { - regexp ^[lindex $i 0] $fpga_family matched - } - return "$matched" - } - SPEED_GRADE { - set speed_grade [get_property SPEED $part] - return "$speed_grade" - } - DEV_PACKAGE { - set dev_package [get_property PACKAGE $part] - foreach i $dev_package_list { - regexp ^[lindex $i 0] $dev_package matched - } - return "$matched" - } - XCVR_TYPE { - set matched "" - set dev_transcivers "none" - foreach x [list_property $part] { - regexp ^GT..._TRANSCEIVERS $x dev_transcivers - } - foreach i $xcvr_type_list { - regexp ^[lindex $i 0] $dev_transcivers matched - } - if { $matched eq "" } { - puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" - } - return "$matched" - } - FPGA_VOLTAGE { - set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] - set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) - - return "$fpga_voltage" - } - default { - puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" - } - } -} - - -## *************************************************************************** -## *************************************************************************** diff --git a/CI/scripts/bsp.tmpl b/CI/scripts/bsp.tmpl deleted file mode 100644 index 6dac3cf..0000000 --- a/CI/scripts/bsp.tmpl +++ /dev/null @@ -1,158 +0,0 @@ - - - Analog Devices, Inc. Precision Toolbox - Analog Devices, Inc - - Analog Devices, Inc - Board support package for control and data streaming from Analog Devices Precision products. - Scripts and tools created by ADI to be used with MATLAB and Simulink with ADI Precision products -Documentation: https://wiki.analog.com/resources/tools-software/pcx-toolbox -Support: https://ez.analog.com/ - __REPO-ROOT__/CI/doc/ADI_Logo_AWP_Large.png - __VERSION__ - ${PROJECT_ROOT}/Analog Devices Board Support Packages.mltbx - - MATLAB - Simulink - Communications Toolbox - DSP System Toolbox - Signal Processing Toolbox - - - 1 - 2 - 36 - 24 - 101 - 8 - 14 - - - 9.5 - 9.2 - 7.0 - 9.7 - 3.13 - 8.1 - 9.0 - - - __UUID__ - % -CI/* -hdl_prj/* -slprj/* -.git/* -test/* -itests/* -mltbx/* -*~ -.Xil/* - true - - - - - ${PROJECT_ROOT}/info.xml - - - - false - __ML-RELEASE__ - __ML-RELEASE__ - true - true - false - true - false - - - - - - - - - - - - - - - - - - - - - - - - - - - - - __REPO-ROOT__ - - - ${PROJECT_ROOT}/LICENSE - ${PROJECT_ROOT}/README.md - ${PROJECT_ROOT}/doc - ${PROJECT_ROOT}/info.xml - ${PROJECT_ROOT}/rfm_examples - - - - - - - __REPO-ROOT__/AnalogDevicesPrecision.mltbx - - - - /usr/local/MATLAB/__ML-RELEASE__ - - - - - - - - - true - - - - - true - - - - - true - - - - - true - - - - - true - false - false - false - false - false - true - false - 4.15.0-34-generic - false - true - glnxa64 - true - - - diff --git a/CI/scripts/bsp_noexamples.tmpl b/CI/scripts/bsp_noexamples.tmpl deleted file mode 100644 index 15aac74..0000000 --- a/CI/scripts/bsp_noexamples.tmpl +++ /dev/null @@ -1,162 +0,0 @@ - - - Analog Devices, Inc. Transceiver Toolbox - Travis Collins - travis.collins@analog.com - Analog Devices, Inc - Board support package for HDL targeting and data streaming from Analog Devices transceivers. - Scripts and tools created by ADI to be used with MATLAB and Simulink with ADI transceivers -Documentation: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/matlab_bsp -Support: https://ez.analog.com/ - __REPO-ROOT__/CI/doc/ADI_Logo_AWP_Large.png - __VERSION__ - ${PROJECT_ROOT}/AnalogDevicesTransceiverToolbox.mltbx - - MATLAB - Simulink - Communications Toolbox - DSP System Toolbox - HDL Coder - Signal Processing Toolbox - Simulink Coder - - - 1 - 2 - 36 - 24 - 101 - 8 - 14 - - - 9.5 - 9.2 - 7.0 - 9.7 - 3.13 - 8.1 - 9.0 - - - __UUID__ - % -CI/* -deps/* -hdl_prj/* -slprj/* -.git/* -test/* -itests/* -mltbx/* -trx_examples/* -*~ -.Xil/* - true - - - - - ${PROJECT_ROOT}/info.xml - - - - false - __ML-RELEASE__ - __ML-RELEASE__ - true - true - false - true - false - - - - - - - - - - - - - - - - - - - - - - - - - - - - - __REPO-ROOT__ - - - ${PROJECT_ROOT}/LICENSE - ${PROJECT_ROOT}/README.md - ${PROJECT_ROOT}/doc - ${PROJECT_ROOT}/hdl - ${PROJECT_ROOT}/info.xml - - - - - - - __REPO-ROOT__/AnalogDevicesTransceiverToolbox.mltbx - - - - /usr/local/MATLAB/__ML-RELEASE__ - - - - - - - - - true - - - - - true - - - - - true - - - - - true - - - - - true - false - false - false - false - false - true - false - 4.15.0-34-generic - false - true - glnxa64 - true - - - diff --git a/CI/scripts/build_bsp.m b/CI/scripts/build_bsp.m deleted file mode 100644 index 6acdc33..0000000 --- a/CI/scripts/build_bsp.m +++ /dev/null @@ -1,68 +0,0 @@ -%% Move to correct location -p = mfilename('fullpath'); -p = strsplit(p,'/'); -p = p(1:end-1); -p = strjoin(p,'/'); -cd(p); -cd .. - -%% Setup HDL repo -system('git clone --single-branch -b hdl_2018_r1 https://github.com/analogdevicesinc/hdl.git') -system('source /opt/Xilinx/Vivado/2017.4/settings64.sh'); - -%% Update adi_ip script to make sure archive are built in a portable way -copyfile('scripts/adi_ip.tcl', 'hdl/library/scripts/') - -%% Pack all cores -system('/opt/Xilinx/Vivado/2017.4/bin/vivado -mode batch -source scripts/pack_all_ips.tcl && echo "success" || echo "failed"') - -%% Repack i2s core to include xml files -cd hdl/library/axi_i2s_adi/ -unzip('analog.com_user_axi_i2s_adi_1.0.zip','tmp') -delete('analog.com_user_axi_i2s_adi_1.0.zip') -copyfile('*.xml','tmp') -zip('analog.com_user_axi_i2s_adi_1.0.zip',{'*'},'tmp'); -cd ../../.. - -cd hdl/library/util_i2c_mixer/ -unzip('analog.com_user_util_i2c_mixer_1.0.zip','tmp') -delete('analog.com_user_util_i2c_mixer_1.0.zip') -copyfile('*.xml','tmp') -zip('analog.com_user_util_i2c_mixer_1.0.zip',{'*'},'tmp'); -cd ../../.. - -%% Move all cores -system('/opt/Xilinx/Vivado/2017.4/bin/vivado -mode batch -source scripts/copy_all_packed_ips.tcl && echo "success" || echo "failed"') -!cp -r hdl/library/jesd204/*.zip hdl/library/ -!cp -r hdl/library/xilinx/*.zip hdl/library/ -!rm -rf hdl/projects -!cp -r projects hdl/ - -%% Remove unused projects in BSP -% cd hdl/projects -% whitelist = {'..','.','scripts','fmcomms5','fmcomms2','common','adrv9361z7035','adrv9364z7020','adrv9009'}; -% files = dir('.'); -% files = {files.name}; -% for file = files -% if ~ismember(file{:},whitelist) -% disp(file{:}) -% if isfile(file{:}) -% delete(file{:}); -% elseif isfolder(file{:}) -% rmdir(file{:},'s'); -% end -% end -% end -% cd ../.. - -%% Update tcl scripts and additional IP cores (MUX) -copyfile('scripts/adi_project.tcl', 'hdl/projects/scripts/') -copyfile('scripts/adi_build.tcl', 'hdl/projects/scripts/') -copyfile('ip/*.zip', 'hdl/library/') -movefile('hdl','../../hdl_wa_bsp/vendor/AnalogDevices/vivado') - -%% Cleanup -delete('vivado_*') -delete('vivado.jou') -delete('vivado.log') - diff --git a/CI/scripts/build_bsp.sh b/CI/scripts/build_bsp.sh deleted file mode 100644 index 5a7d1a8..0000000 --- a/CI/scripts/build_bsp.sh +++ /dev/null @@ -1,273 +0,0 @@ -#!/bin/bash -set -x - -if [ -z "${HDLBRANCH}" ]; then -HDLBRANCH='hdl_2019_r2' -fi - - -# Script is designed to run from specific location -scriptdir=`dirname "$BASH_SOURCE"` -cd $scriptdir -cd .. - -# Get HDL -if [ -d "hdl" ]; then - rm -rf "hdl" -fi -for i in {1..5} -do - if git clone --single-branch -b $HDLBRANCH https://github.com/analogdevicesinc/hdl.git - then - break - fi - if [ -d "hdl" ]; then - break - fi -done -if [ ! -d "hdl" ]; then - echo "HDL clone failed" - exit 1 -fi - - -# Get required vivado version needed for HDL -if [ -f "hdl/library/scripts/adi_ip.tcl" ]; then - TARGET="hdl/library/scripts/adi_ip.tcl" -else - TARGET="hdl/library/scripts/adi_ip_xilinx.tcl" -fi -VER=$(awk '/set REQUIRED_VIVADO_VERSION/ {print $3}' $TARGET | sed 's/"//g') -echo "Required Vivado version ${VER}" -VIVADOFULL=${VER} -if [ ${#VER} = 8 ] -then -VER=${VER:0:6} -fi -VIVADO=${VER} - -# Setup -source /opt/Xilinx/Vivado/$VIVADO/settings64.sh - -# Update build scripts and force vivado versions -cp scripts/adi_ip.tcl hdl/library/scripts/ -VERTMP=$(awk '/set REQUIRED_VIVADO_VERSION/ {print $3}' hdl/library/scripts/adi_ip.tcl | sed 's/"//g') -grep -rl ${VERTMP} hdl/library/scripts | xargs sed -i -e "s/${VERTMP}/${VIVADOFULL}/g" - -# Update relative paths -FILES=$(grep -lrnw hdl/projects -e "\.\.\/common" | grep -v Makefile) -for f in $FILES -do - echo "Updating relative paths of: $f" - DEVICE=$(echo "$f"| cut -d "/" -f 3) - STR="\$ad_hdl_dir\/projects\/$DEVICE" - sed -i "s/\.\.\/common/$STR\/common/g" "$f" -done - -# Rename .prj files since MATLAB ignores then during packaging -FILES=$(grep -lrn hdl/projects/common -e '.prj' | grep -v Makefile | grep -v .git) -for f in $FILES -do - echo "Updating prj reference in: $f" - sed -i "s/\.prj/\.mk/g" "$f" -done -FILES=$(find hdl/projects/common -name "*.prj") -for f in $FILES -do - DEST="${f::-3}mk" - echo "Renaming: $f to $DEST" - mv "$f" "$DEST" -done - -# Remove intel -rm -rf hdl/projects/common/intel -rm -rf hdl/library/intel - -# Remove references to GHDL crap -wget https://raw.githubusercontent.com/analogdevicesinc/hdl/hdl_2018_r2/library/scripts/adi_env.tcl -mv adi_env.tcl hdl/library/scripts/ -cp scripts/adi_env.tcl hdl/projects/scripts/ - -cp scripts/adi_project_xilinx.tcl hdl/projects/scripts/ -cp scripts/adi_ip_xilinx.tcl hdl/library/scripts/ - -# Update cores to move relative paths locally -sed -i 's/add_files/add_files\ -copy_to\ \[pwd\]\ -force/g' hdl/library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.tcl - -# Update new folder names -sed -i 's/util_cdc/analog_lib.com_user_util_cdc_1.0/g' hdl/projects/common/xilinx/adi_fir_filter_bd.tcl -sed -i 's/util_fir_int/analog_lib.com_user_util_fir_int_1.0/g' hdl/projects/adrv9009/common/adrv9009_bd.tcl -sed -i 's/util_fir_int/analog_lib.com_user_util_fir_int_1.0/g' hdl/projects/adrv9371x/common/adrv9371x_bd.tcl - -# Pack IP cores -pwd -echo "Starting IP core packaging" -#vivado -verbose -mode batch -source scripts/pack_all_ips.tcl > /dev/null 2>&1 -vivado -verbose -mode batch -source scripts/pack_all_ips.tcl > log.txt - -# Repack i2s and i2c cores to include xml files -cd hdl/library/axi_i2s_adi/ -pwd -ls -#unzip analog.com_user_axi_i2s_adi_1.0.zip -d tmp -unzip analog_lib.com_user_axi_i2s_adi_1.0.zip -d tmp -#rm analog.com_user_axi_i2s_adi_1.0.zip -rm analog_lib.com_user_axi_i2s_adi_1.0.zip -ls -cp *.xml tmp/ -cd tmp -#zip -r analog.com_user_axi_i2s_adi_1.0.zip * -zip -r analog_lib.com_user_axi_i2s_adi_1.0.zip * -#cp analog.com_user_axi_i2s_adi_1.0.zip ../ -cp analog_lib.com_user_axi_i2s_adi_1.0.zip ../ -cd ../../../.. - -pwd - -cd hdl/library/util_i2c_mixer/ -#unzip analog.com_user_util_i2c_mixer_1.0.zip -d tmp/ -unzip analog_lib.com_user_util_i2c_mixer_1.0.zip -d tmp/ -#rm analog.com_user_util_i2c_mixer_1.0.zip -rm analog_lib.com_user_util_i2c_mixer_1.0.zip -cp *.xml tmp/ -cd tmp -#zip -r analog.com_user_util_i2c_mixer_1.0.zip * -zip -r analog_lib.com_user_util_i2c_mixer_1.0.zip * -#cp analog.com_user_util_i2c_mixer_1.0.zip ../ -cp analog_lib.com_user_util_i2c_mixer_1.0.zip ../ -cd ../../../.. - -pwd - -# Rename zips so they do not overwrite one another -cd hdl/library/jesd204 -FILES=$(find . -name "*.zip") -for f in $FILES -do - M=${f:2} - mv -- "$M" . -done -cd ../../.. - -#cd hdl/library/jesd204 -#FILES=$(find . -name "*.zip") -#for f in $FILES -#do -# echo "Renaming $f" -# M=${f:2} -# echo "Repacking $M" -# FN=${M::-4} -# unzip $M -d $FN -# mv -- "$FN" "jesd204_${FN}" -# cd "jesd204_${FN}" -# zip -r "jesd204_${FN}.zip" * -# cd .. -# mv "jesd204_${FN}/jesd204_${FN}.zip" . -# rm -rf "jesd204_${FN}" -# rm $M -#done -#cd ../../.. - -cd hdl/library/xilinx -FILES=$(find . -name "*.zip") -for f in $FILES -do - M=${f:2} - mv -- "$M" . -done -cd ../../.. - -#cd hdl/library/xilinx -#FILES=$(find . -name "*.zip") -#for f in $FILES -#do -# echo "Renaming $f" -# M=${f:2} -# echo "Repacking $M" -# FN=${M::-4} -# unzip $M -d $FN -# mv -- "$FN" "xilinx_${FN}" -# cd "xilinx_${FN}" -# zip -r "xilinx_${FN}.zip" * -# cd .. -# mv "xilinx_${FN}/xilinx_${FN}.zip" . -# rm -rf "xilinx_${FN}" -# rm $M -#done -#cd ../../.. - - -# Move all cores -echo "Moving all cores" -vivado -mode batch -source scripts/copy_all_packed_ips.tcl || true - -cp -r hdl/library/util_pack/*.zip hdl/library/ -cp -r hdl/library/jesd204/*.zip hdl/library/ -cp -r hdl/library/xilinx/*.zip hdl/library/ -cp -r hdl/projects/common common -cp -r hdl/projects/scripts/adi_board.tcl . - -mv hdl/projects projects_premerge -# Remove pluto since its manually updated -rm -rf projects_premerge/pluto -cp -r projects hdl/ -cp -R projects_premerge/* hdl/projects/ -rm -rf projects_premerge - -cp -R common/* hdl/projects/common/ -rm -rf common -mv adi_board.tcl hdl/projects/scripts/ - -# Update tcl scripts and additional IP cores (MUX) -cp scripts/adi_project.tcl hdl/projects/scripts/ -cp scripts/adi_build.tcl hdl/projects/scripts/ -cp ip/*.zip hdl/library/ - -# Update vivado version in MATLAB API and build script -DEFAULT_V_VERSION='2017.4' -cd .. -echo "SED 1" -grep -rl ${DEFAULT_V_VERSION} hdl/vendor/AnalogDevices/+AnalogDevices | grep -v MODEM | xargs sed -i "s/${DEFAULT_V_VERSION}/$VIVADO/g" -cd CI -echo "SED 2" -grep -rl ${DEFAULT_V_VERSION} hdl/projects/scripts | xargs sed -i "s/${DEFAULT_V_VERSION}/$VIVADOFULL/g" - -# Remove extra projects -FILES=$(find hdl/projects) -for f in $FILES -do - if [[ "$f" == 'adrv9009' ]]; then - continue - elif [[ "$f" == 'adrv9371x' ]]; then - continue - elif [[ "$f" == 'fmcomms2' ]]; then - continue - elif [[ "$f" == 'fmcomms5' ]]; then - continue - elif [[ "$f" == 'pluto' ]]; then - continue - elif [[ "$f" == 'adrv9001' ]]; then - continue - elif [[ "$f" == 'adrv9361z7035' ]]; then - continue - elif [[ "$f" == 'adrv9364z7020' ]]; then - continue - fi - rm -rf "hdl/projects/$f" - -done - -# Remove git directory move to bsp folder -rm -fr hdl/.git* -TARGET="../hdl/vendor/AnalogDevices/vivado" -if [ -d "$TARGET" ]; then - rm -rf "$TARGET" -fi -cp -r hdl $TARGET - - -# Cleanup -rm vivado_* -rm vivado.jou -rm vivado.log -rm -rf hdl diff --git a/CI/scripts/copy_all_packed_ips.tcl b/CI/scripts/copy_all_packed_ips.tcl deleted file mode 100644 index b8132f3..0000000 --- a/CI/scripts/copy_all_packed_ips.tcl +++ /dev/null @@ -1,74 +0,0 @@ - - -proc copy_all_packed_ips { DEST_FOLDER } { - - #set WD [pwd] - #set DEST_FOLDER D:/Work/hdlbsp-master/vendor/AnalogDevices/vivado/library - #set DEST_FOLDER $WD - - set folder_list [glob -types d *] - foreach dir $folder_list { - puts "$dir" - cd $dir - - if {[catch {set files_list [glob *]}]} { - cd .. - continue - } - - foreach file $files_list { - set idx [string first .zip $file 1] - if {$idx != -1} { - file copy -force $file $DEST_FOLDER/$file - puts $file - } - } - cd .. - - # Don't remove these folders - if {$dir=="common"} {continue} - if {$dir=="interfaces"} {continue} - if {$dir=="prcfg"} {continue} - if {$dir=="scripts"} {continue} - if {$dir=="xilinx"} {continue} - if {$dir=="jesd204"} {continue} - if {$dir=="spi_engine"} {continue} - if {$dir=="util_pack"} {continue} - file delete -force -- $dir - - - } - -} - -cd hdl - -# Move main library core zips -cd library -set DEST [pwd] -puts $DEST -copy_all_packed_ips $DEST - -# Move Xilinx core zips -cd xilinx -set DEST [pwd] -copy_all_packed_ips $DEST -cd .. - -# Move jesd204 core zips -cd jesd204 -set DEST [pwd] -copy_all_packed_ips $DEST -cd .. - -# Move spi_engine core zips -cd spi_engine -set DEST [pwd] -copy_all_packed_ips $DEST - -# Move util_pack core zips -cd util_pack -set DEST [pwd] -copy_all_packed_ips $DEST - -cd ../../.. diff --git a/CI/scripts/dockermake b/CI/scripts/dockermake deleted file mode 100644 index 06c9322..0000000 --- a/CI/scripts/dockermake +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/bash -docker build . -t matlabci -f CI/scripts/Docker -docker run --rm -e "INCLUDE_EXAMPLES=$INCLUDE_EXAMPLES" -e "BOARD=$BOARD" -e "LM_LICENSE_FILE=$LM_LICENSE_FILE" -e "XILINXD_LICENSE_FILE=$XILINXD_LICENSE_FILE" -e "MLRELEASE=$MLRELEASE" -e "HDLBRANCH=$HDLBRANCH" -v "$(pwd):/work" -v /mlhsp:/mlhspro:ro -v /usr/local/MATLAB:/usr/local/MATLAB -v /root/.matlab:/root/.matlabro:ro -v /root/.Xilinx:/root/.Xilinxro:ro -v /opt/Xilinx:/opt/Xilinx --mac-address="$ADDR" matlabci /bin/bash -c "cd /work && chmod +x CI/scripts/setupDocker.sh && ./CI/scripts/setupDocker.sh && make -C CI/scripts '$@'" diff --git a/CI/scripts/genTlbx.m b/CI/scripts/genTlbx.m deleted file mode 100644 index c95c2fb..0000000 --- a/CI/scripts/genTlbx.m +++ /dev/null @@ -1,96 +0,0 @@ -function genTlbx(examples) - -if nargin==0 - examples = 1; -end - -version = '21.2.1'; -ml = ver('MATLAB'); -ml = ml.Release(2:end-1); -uuid = matlab.lang.internal.uuid; - -%% -cd(fileparts((mfilename('fullpath')))); -cd('../..'); -p = pwd; -cd(fileparts((mfilename('fullpath')))); - -if examples - fid = fopen('bsp.tmpl','r'); -else - fid = fopen('bsp_noexamples.tmpl','r'); -end -f=fread(fid,'*char')'; -fclose(fid); - -f = strrep(f,'__REPO-ROOT__',p); -f = strrep(f,'__VERSION__',version); -f = strrep(f,'__ML-RELEASE__',ml); -f = strrep(f,'__UUID__',uuid); - -fid = fopen('../../bsp.prj','w'); -fprintf(fid,'%s',f); -fclose(fid); - -cd('../..'); -addpath(genpath(matlabshared.supportpkg.getSupportPackageRoot)); -addpath(genpath('.')); -rmpath(genpath('.')); -if examples - ps = {'doc','examples'}; -else - ps = {'doc'}; -end -paths = ''; -for p = ps - pp = genpath(p{:}); - ppF = pp; - pp = pp(1:end-1); - pp = strrep(pp,':',''); - paths = [paths,['',pp,'']]; %#ok - addpath(ppF); -end -rehash -projectFile = 'bsp.prj'; -currentVersion = matlab.addons.toolbox.toolboxVersion(projectFile); -if examples - outputFile = ['AnalogDevicesPrecisionToolbox_v',currentVersion]; -else - outputFile = ['AnalogDevicesPrecisionToolbox_noexamples_v',currentVersion]; -end -matlab.addons.toolbox.packageToolbox(projectFile,outputFile) - -if ~usejava('desktop') - %% Update toolbox paths - mkdir other - movefile([outputFile,'.mltbx'], ['other/',outputFile,'.zip']); - cd other - unzip([outputFile,'.zip'],'out'); - cd('out') - cd('metadata'); - fid = fopen('configuration.xml','r'); - f=fread(fid,'*char')'; - fclose(fid); - - s = ''; - sections = strsplit(f,s); - s1 = sections{1}; - s2 = sections{2}; - newfile = [s1,paths,s,s2]; - - fid = fopen('configuration.xml','w'); - fprintf(fid,'%s',newfile); - fclose(fid); - - %% Repack - cd('..'); - zip([outputFile,'.zip'], '*'); - movefile([outputFile,'.zip'],['../../',outputFile,'.mltbx']); - cd('../..'); - rmdir('other','s'); -end - -delete bsp.prj - - - diff --git a/CI/scripts/genTlbx2.m b/CI/scripts/genTlbx2.m deleted file mode 100644 index 4c83292..0000000 --- a/CI/scripts/genTlbx2.m +++ /dev/null @@ -1,101 +0,0 @@ -function genTlbx2(examples) - -if nargin==0 - examples = 0; -end - -% Lookup versioning info from adi.Version -cwd = pwd; -parts = strsplit(mfilename('fullpath'),filesep); -tbroot = strjoin(parts(1:end-3),filesep); -cd(tbroot); -v = adi.Version; -uuid = matlab.lang.internal.uuid; -cd(cwd); - -%% -cd(fileparts((mfilename('fullpath')))); -cd('../..'); -p = pwd; -cd(fileparts((mfilename('fullpath')))); - -fid = fopen('bsp.tmpl','r'); -f=fread(fid,'*char')'; -fclose(fid); - -f = strrep(f,'__REPO-ROOT__',p); -f = strrep(f,'__VERSION__',v.Release); -f = strrep(f,'__ML-RELEASE__',v.MATLAB); -f = strrep(f,'__APP-NAME__',v.AppName); -f = strrep(f,'__EXAMPLES-DIR__',v.ExamplesDir); -f = strrep(f,'__UUID__',uuid); - -fid = fopen('../../bsp.prj','w'); -fprintf(fid,'%s',f); -fclose(fid); - -cd('../..'); -addpath(genpath(matlabshared.supportpkg.getSupportPackageRoot)); -addpath(genpath('.')); -rmpath(genpath('.')); -if examples - ps = {'doc',v.ExamplesDir}; -else - ps = {'doc'}; -end -if isprop(v,'HasHDL') && v.HasHDL - ps = [ps(:)',{'hdl'}]; -end - -paths = ''; -for p = ps - pp = genpath(p{:}); - ppF = pp; - pp = pp(1:end-1); - pp = strrep(pp,':',''); - paths = [paths,['',pp,'']]; %#ok - addpath(ppF); -end -rehash -projectFile = 'bsp.prj'; -currentVersion = matlab.addons.toolbox.toolboxVersion(projectFile); -if examples - outputFile = sprintf('AnalogDevices%s_v%s',v.ToolboxName,currentVersion); -else - outputFile = sprintf('AnalogDevices%s_noexamples_v%s',v.ToolboxName,currentVersion); -end -matlab.addons.toolbox.packageToolbox(projectFile,outputFile) - -if ~usejava('desktop') - %% Update toolbox paths - mkdir other - movefile([outputFile,'.mltbx'], ['other/',outputFile,'.zip']); - cd other - unzip([outputFile,'.zip'],'out'); - cd('out') - cd('metadata'); - fid = fopen('configuration.xml','r'); - f=fread(fid,'*char')'; - fclose(fid); - - s = ''; - sections = strsplit(f,s); - s1 = sections{1}; - s2 = sections{2}; - newfile = [s1,paths,s,s2]; - - fid = fopen('configuration.xml','w'); - fprintf(fid,'%s',newfile); - fclose(fid); - - %% Repack - cd('..'); - zip([outputFile,'.zip'], '*'); - movefile([outputFile,'.zip'],['../../',outputFile,'.mltbx']); - cd('../..'); - rmdir('other','s'); -end - -% delete bsp.prj - - diff --git a/CI/scripts/linter.m b/CI/scripts/linter.m deleted file mode 100644 index 4a26bff..0000000 --- a/CI/scripts/linter.m +++ /dev/null @@ -1,23 +0,0 @@ -clc; -ignoreFolders = {'CI','doc','test'}; -cd ../.. -d = pwd; -cd .. -addpath(genpath(d)); -cd(d); - -files = dir('**/*.m'); -for file = 1:length(files) - if contains(files(file).folder,ignoreFolders) - continue; - end - mfile = fullfile(files(file).folder,files(file).name); - rpt = mlint(mfile); - if ~isempty(rpt) - disp(mfile); - for l = 1:length(rpt) - disp([num2str(rpt(l).line) ': ' rpt(l).message]); - end - end -end - diff --git a/CI/scripts/pack_all_ips.tcl b/CI/scripts/pack_all_ips.tcl deleted file mode 100644 index 271533c..0000000 --- a/CI/scripts/pack_all_ips.tcl +++ /dev/null @@ -1,58 +0,0 @@ - -# Create zip of IP cores -proc pack_ip_core {sub} { - - set folder_list [glob -types d *] - - foreach dir $folder_list { - puts "$dir" - cd $dir - - if {[catch {set fp [open ${dir}_ip.tcl r]}]} { - cd .. - continue - } - close $fp - - set fp [open ${dir}_ip.tcl a+] - puts -nonewline $fp "ipx::archive_core -verbose {analog_${sub}.com_user_" - puts -nonewline $fp "$dir" - puts -nonewline $fp "_1.0.zip} \[ipx::current_core\]" - close $fp - - source ./${dir}_ip.tcl - - cd .. - } -} - -source hdl/library/scripts/adi_ip.tcl -source hdl/library/scripts/adi_env.tcl - -cd hdl - -# Pack main library cores -cd library -pack_ip_core "lib" - -# Pack Xilinx cores -cd xilinx -pack_ip_core "xilinx" -cd .. - -# Pack JESD cores -cd jesd204 -pack_ip_core "jesd" -cd .. - -# Pack spi_engine cores -cd spi_engine -pack_ip_core "spi_engine" -cd .. - -# Pack pack cores -cd util_pack -pack_ip_core "util_pack" -cd .. - -cd ../../ diff --git a/CI/scripts/read_ports_json.py b/CI/scripts/read_ports_json.py deleted file mode 100644 index 7d6a695..0000000 --- a/CI/scripts/read_ports_json.py +++ /dev/null @@ -1,59 +0,0 @@ -import json - -# open ports.json file and parse -ports_json_file = 'ports.json' -with open(ports_json_file) as json_file: - ports = json.load(json_file) - - tmp_key = "m_name" - for key0 in ports.keys(): - for key1 in ports[key0]['ports'][0].keys(): - if (key1 == "rx"): - for ii in range(0, len(ports[key0]['ports'][0][key1])): - tmp_dict = ports[key0]['ports'][0][key1][ii] - if (tmp_dict['type'].lower() == "data"): - if (tmp_dict['input'] == "true"): - if tmp_key not in tmp_dict: - tmp_list = tmp_dict['name'].split("_") - last_ele = tmp_list[-1] - if (len(last_ele) == 1): - tmp_dict[tmp_key] = f"{ports[key0]['chip']} ADC Data {last_ele} IN" - elif (len(last_ele) == 2): - tmp_dict[tmp_key] = f"{ports[key0]['chip']} ADC Data {last_ele.upper()}" - elif (tmp_dict['input'] == "false"): - if tmp_key not in tmp_dict: - tmp_list = tmp_dict['name'].split("_") - last_ele = tmp_list[-1] - tmp_dict[tmp_key] = f"IP Data {last_ele.upper()} OUT" - elif (tmp_dict['type'].lower() == "valid"): - if (tmp_dict['input'] == "true"): - tmp_dict[tmp_key] = f"IP Valid Rx Data IN" - elif (tmp_dict['input'] == "false"): - tmp_dict[tmp_key] = f"IP Data Valid OUT" - ports[key0]['ports'][0][key1][ii] = tmp_dict - elif (key1 == "tx"): - for ii in range(0, len(ports[key0]['ports'][0][key1])): - tmp_dict = ports[key0]['ports'][0][key1][ii] - if (tmp_dict['type'].lower() == "data"): - if (tmp_dict['input'] == "false"): - if tmp_key not in tmp_dict: - tmp_list = tmp_dict['name'].split("_") - last_ele = tmp_list[-1] - if (len(last_ele) == 1): - tmp_dict[tmp_key] = f"{ports[key0]['chip']} DAC Data {last_ele} OUT" - elif (len(last_ele) == 2): - tmp_dict[tmp_key] = f"{ports[key0]['chip']} DAC Data {last_ele.upper()}" - elif (tmp_dict['input'] == "true"): - if tmp_key not in tmp_dict: - tmp_list = tmp_dict['name'].split("_") - last_ele = tmp_list[-1] - tmp_dict[tmp_key] = f"IP Data {last_ele.upper()} IN" - elif (tmp_dict['type'].lower() == "valid"): - if (tmp_dict['input'] == "true"): - tmp_dict[tmp_key] = f"IP Valid Tx Data IN" - elif (tmp_dict['input'] == "false"): - tmp_dict[tmp_key] = f"IP Load Tx Data OUT" - ports[key0]['ports'][0][key1][ii] = tmp_dict - -with open(ports_json_file, 'w') as json_file: - json.dump(ports, json_file, indent = 4) \ No newline at end of file diff --git a/CI/scripts/rename_common.py b/CI/scripts/rename_common.py deleted file mode 100644 index 46403c6..0000000 --- a/CI/scripts/rename_common.py +++ /dev/null @@ -1,35 +0,0 @@ -import os -import glob -import pathlib - -new_dir = "+commonrf" - -path = pathlib.Path(__file__).parent.resolve() - -path = os.path.split(path) -path = os.path.split(path[0])[0] - -files = glob.glob(os.path.join(path, "+adi", "**/*")) -if len(files) == 0: - print("No files found") - print("Did you clone all the submodules?") - exit(1) - -for file in files: - if os.path.isdir(file): - continue - with open(file, "r") as f: - content = f.read() - if "adi.common." in content: - content = content.replace("adi.common.", f"adi.{new_dir[1:]}.") - print("Updating:", file) - with open(file, "w") as f: - f.write(content) - -src = os.path.join(path, "+adi", "+common") -dst = os.path.join(path, "+adi", new_dir) -if os.path.isdir(src): - print("Renaming:", src, "->", dst) - os.rename(src, dst) -else: - print("No +common folder found. Maybe you already renamed it?") diff --git a/CI/scripts/setupDocker.sh b/CI/scripts/setupDocker.sh deleted file mode 100644 index eca338c..0000000 --- a/CI/scripts/setupDocker.sh +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/bash -# This file is run inside of the docker container -echo "Copying HSP files" -cp -r /mlhspro /mlhsp -echo "Copying .matlab" -cp -r /root/.matlabro /root/.matlab -echo "Copying .Xilinx" -cp -r /root/.Xilinxro /root/.Xilinx diff --git a/CI/scripts/synth_designs.sh b/CI/scripts/synth_designs.sh deleted file mode 100644 index e99496d..0000000 --- a/CI/scripts/synth_designs.sh +++ /dev/null @@ -1,22 +0,0 @@ -#!/bin/bash - -BOARD=$1 -MLFLAGS="-nodisplay -nodesktop -nosplash" - -if [ -z "$MLRELEASE" ] -then - MLRELEASE=R2021a -fi - -MLPATH=/usr/local/MATLAB - -cd ../.. -cp hdl/vendor/AnalogDevices/hdlcoder_board_customization.m test/hdlcoder_board_customization_local.m -sed -i "s/hdlcoder_board_customization/hdlcoder_board_customization_local/g" test/hdlcoder_board_customization_local.m -source /opt/Xilinx/Vivado/2019.1/settings64.sh -Xvfb :77 & -export DISPLAY=:77 -export SWT_GTK3=0 -source /opt/Xilinx/Vivado/2019.1/settings64.sh -$MLPATH/$MLRELEASE/bin/matlab $MLFLAGS -r "cd('test');runSynthTests('$BOARD');" -kill -9 `pidof Xvfb` diff --git a/CI/scripts/targeting_designs.sh b/CI/scripts/targeting_designs.sh deleted file mode 100644 index d284fe6..0000000 --- a/CI/scripts/targeting_designs.sh +++ /dev/null @@ -1,24 +0,0 @@ -#!/bin/bash - -MLFLAGS="-nodisplay -nodesktop -nosplash" - -if [ -z "$MLRELEASE" ] -then - MLRELEASE=R2021a -fi -if [ -z "$DEMO" ] -then - DEMO="" -fi -echo "Testing demo: $DEMO" - -MLPATH=/usr/local/MATLAB - -cd ../.. -source /opt/Xilinx/Vivado/2019.1/settings64.sh -Xvfb :77 & -export DISPLAY=:77 -export SWT_GTK3=0 -source /opt/Xilinx/Vivado/2019.1/settings64.sh -$MLPATH/$MLRELEASE/bin/matlab $MLFLAGS -r "addpath(genpath('test'));addpath(genpath('deps'));runDemoTests('$DEMO');" -kill -9 `pidof Xvfb` diff --git a/CI/scripts_hdl/matlab_processors.tcl b/CI/scripts_hdl/matlab_processors.tcl new file mode 100755 index 0000000..dc47d1f --- /dev/null +++ b/CI/scripts_hdl/matlab_processors.tcl @@ -0,0 +1,57 @@ +proc preprocess_bd {project carrier rxtx} { + + puts "Preprocessing $project $carrier $rxtx" + + switch $project { + cn0585 { + # Disconnect the ADC PACK pins + delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_data] + delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_data] + delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_data] + delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_data] + + set sys_cstring "matlab $rxtx" + sysid_gen_sys_init_file $sys_cstring + + #Disconnect adc_valid + delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_valid] + # Reconnect the adc_valid in the system + connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins axi_ltc2387_dma/fifo_wr_en] + + if {$rxtx == "rx"} { + connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins axi_ad3552r_0/data_in_a] + connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins axi_ad3552r_0/data_in_b] + connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins axi_ad3552r_1/data_in_a] + connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins axi_ad3552r_1/data_in_b] + } + + if {$rxtx == "tx"} { + connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_0] + connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_1] + connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_2] + connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_3] + connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_en] + } + + if {$rxtx == "tx" || $rxtx == "rxtx"} { + + delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_valid] + delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_valid] + delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_valid] + delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_valid] + + # Connect dac valids together + connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_0/valid_in_b] + connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_a] + connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_b] + } + switch $carrier { + zed { + set_property -dict [list CONFIG.NUM_MI {21}] [get_bd_cells axi_cpu_interconnect] + connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ACLK] [get_bd_pins axi_clkgen/clk_0] + connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ARESETN] [get_bd_pins sampling_clk_rstgen/peripheral_aresetn] + } + } + } + } +} diff --git a/CI/scripts/ports.json b/CI/scripts_hdl/ports.json old mode 100644 new mode 100755 similarity index 54% rename from CI/scripts/ports.json rename to CI/scripts_hdl/ports.json index 278ae32..51f6fb1 --- a/CI/scripts/ports.json +++ b/CI/scripts_hdl/ports.json @@ -1,12 +1,14 @@ { - "ad7380": { - "chip": "AD7380", - "complex": "false", + "cn0585": { + "chip": "CN0585", + "complex": "true", "fpga": [ - "zcu102" + "zed" ], "supported_rd": [ - "rx" + "rx", + "tx", + "rx & tx" ], "ports": [ { @@ -14,165 +16,127 @@ { "input": "false", "width": 1, - "name": "axi_ad9680_cpack/fifo_wr_en", - "type": "valid" - }, - { - "input": "true", - "width": 1, - "name": "axi_ad9680_tpl/adc_valid_0", - "type": "valid" - }, - { - "input": "false", - "width": 64, - "name": "axi_ad9680_cpack/fifo_wr_data_0", - "type": "data" - }, - { - "input": "false", - "width": 64, - "name": "axi_ad9680_cpack/fifo_wr_data_1", - "type": "data" - }, - { - "input": "true", - "width": 64, - "name": "axi_ad9680_tpl/adc_data_0", - "type": "data" - }, - { - "input": "true", - "width": 64, - "name": "axi_ad9680_tpl/adc_data_1", - "type": "data" - } - ] - } - ] - }, - "ad7768": { - "chip": "AD7768", - "complex": "false", - "fpga": [ - "zcu102" - ], - "supported_rd": [ - "rx" - ], - "ports": [ - { - "rx": [ - { - "input": "false", - "width": 1, - "name": "util_mxfe_cpack/fifo_wr_en", - "type": "valid" - }, - { - "input": "true", - "width": 1, - "name": "rx_mxfe_tpl_core/adc_valid_0", + "name": "util_ltc2387_adc_pack/fifo_wr_en", "type": "valid" }, { "input": "false", "width": 16, - "name": "util_mxfe_cpack/fifo_wr_data_0", + "name": "util_ltc2387_adc_pack/fifo_wr_data_0", "type": "data" }, { "input": "false", "width": 16, - "name": "util_mxfe_cpack/fifo_wr_data_1", + "name": "util_ltc2387_adc_pack/fifo_wr_data_1", "type": "data" }, { "input": "false", "width": 16, - "name": "util_mxfe_cpack/fifo_wr_data_2", + "name": "util_ltc2387_adc_pack/fifo_wr_data_2", "type": "data" }, { "input": "false", "width": 16, - "name": "util_mxfe_cpack/fifo_wr_data_3", + "name": "util_ltc2387_adc_pack/fifo_wr_data_3", "type": "data" }, { - "input": "false", + "input": "true", + "width": 1, + "name": "axi_ltc2387_0/adc_valid", + "type": "valid" + }, + { + "input": "true", "width": 16, - "name": "util_mxfe_cpack/fifo_wr_data_4", + "name": "axi_ltc2387_0/adc_data", "type": "data" }, { - "input": "false", + "input": "true", "width": 16, - "name": "util_mxfe_cpack/fifo_wr_data_5", + "name": "axi_ltc2387_1/adc_data", "type": "data" }, { - "input": "false", + "input": "true", "width": 16, - "name": "util_mxfe_cpack/fifo_wr_data_6", + "name": "axi_ltc2387_2/adc_data", "type": "data" }, { - "input": "false", + "input": "true", "width": 16, - "name": "util_mxfe_cpack/fifo_wr_data_7", + "name": "axi_ltc2387_3/adc_data", "type": "data" - }, - { + } + ], + "tx": [ + { "input": "true", "width": 16, - "name": "rx_mxfe_tpl_core/adc_data_0", + "name": "axi_ltc2387_0/adc_data", "type": "data" }, { "input": "true", "width": 16, - "name": "rx_mxfe_tpl_core/adc_data_1", + "name": "axi_ltc2387_1/adc_data", "type": "data" }, { "input": "true", "width": 16, - "name": "rx_mxfe_tpl_core/adc_data_2", + "name": "axi_ltc2387_2/adc_data", "type": "data" }, { "input": "true", "width": 16, - "name": "rx_mxfe_tpl_core/adc_data_3", + "name": "axi_ltc2387_3/adc_data", "type": "data" }, - { + { "input": "true", + "width": 1, + "name": "axi_ltc2387_0/adc_valid", + "type": "valid" + }, + { + "input": "false", "width": 16, - "name": "rx_mxfe_tpl_core/adc_data_4", + "name": "axi_ad3552r_0/data_in_a", "type": "data" }, - { - "input": "true", + { + "input": "false", "width": 16, - "name": "rx_mxfe_tpl_core/adc_data_5", + "name": "axi_ad3552r_0/data_in_b", "type": "data" }, { - "input": "true", + "input": "false", + "width": 1, + "name": "axi_ad3552r_0/valid_in_a", + "type": "valid" + }, + { + "input": "false", "width": 16, - "name": "rx_mxfe_tpl_core/adc_data_6", + "name": "axi_ad3552r_1/data_in_a", "type": "data" }, { - "input": "true", + "input": "false", "width": 16, - "name": "rx_mxfe_tpl_core/adc_data_7", + "name": "axi_ad3552r_1/data_in_b", "type": "data" } - ] - } + ] + } ] } } diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585/+zed/hdlcoder_ref_design_customization.m b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585/+zed/hdlcoder_ref_design_customization.m new file mode 100755 index 0000000..a7b638c --- /dev/null +++ b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585/+zed/hdlcoder_ref_design_customization.m @@ -0,0 +1,22 @@ +function [rd, boardName] = hdlcoder_ref_design_customization +% Reference design plugin registration file +% 1. The registration file with this name inside of a board plugin folder +% will be picked up +% 2. Any registration file with this name on MATLAB path will also be picked up +% 3. The registration file returns a cell array pointing to the location of +% the reference design plugins +% 4. The registration file also returns its associated board name +% 5. Reference design plugin must be a package folder accessible from +% MATLAB path, and contains a reference design definition file + +% Copyright 2013-2014 The MathWorks, Inc. + +rd = {... + 'AnalogDevices.cn0585.zed.plugin_rd_rx', ... + 'AnalogDevices.cn0585.zed.plugin_rd_tx', ... + 'AnalogDevices.cn0585.zed.plugin_rd_rxtx', ... + }; + +boardName = 'AnalogDevices CN0585 ZED'; + +end diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585/+zed/plugin_board.m b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585/+zed/plugin_board.m new file mode 100755 index 0000000..22b5cf4 --- /dev/null +++ b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585/+zed/plugin_board.m @@ -0,0 +1,8 @@ +function hP = plugin_board() +% Zynq Platform PCore +% Use Plugin API to create board plugin object + +% Copyright 2015 The MathWorks, Inc. + +% Call the common board definition function +hP = AnalogDevices.plugin_board('CN0585', 'ZED'); diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585/+zed/plugin_rd_rx.m b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585/+zed/plugin_rd_rx.m new file mode 100755 index 0000000..002adf5 --- /dev/null +++ b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585/+zed/plugin_rd_rx.m @@ -0,0 +1,5 @@ +function hRD = plugin_rd_rx +% Reference design definition + +% Call the common reference design definition function +hRD = AnalogDevices.plugin_rd('cn0585','ZED', 'Rx'); diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585/+zed/plugin_rd_rxtx.m b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585/+zed/plugin_rd_rxtx.m new file mode 100755 index 0000000..dc334fc --- /dev/null +++ b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585/+zed/plugin_rd_rxtx.m @@ -0,0 +1,7 @@ +function hRD = plugin_rd_rxtx +% Reference design definition + +% Copyright 2014-2015 The MathWorks, Inc. + +% Call the common reference design definition function +hRD = AnalogDevices.plugin_rd('cn0585','ZED', 'Rx & Tx'); diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585/+zed/plugin_rd_tx.m b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585/+zed/plugin_rd_tx.m new file mode 100755 index 0000000..ae6ae98 --- /dev/null +++ b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585/+zed/plugin_rd_tx.m @@ -0,0 +1,7 @@ +function hRD = plugin_rd_tx +% Reference design definition + +% Copyright 2014-2015 The MathWorks, Inc. + +% Call the common reference design definition function +hRD = AnalogDevices.plugin_rd('cn0585', 'ZED', 'Tx'); diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/+util/ADIZynqSDRAttributeInfo.xml b/hdl/vendor/AnalogDevices/+AnalogDevices/+util/ADIZynqSDRAttributeInfo.xml new file mode 100755 index 0000000..7c9a676 --- /dev/null +++ b/hdl/vendor/AnalogDevices/+AnalogDevices/+util/ADIZynqSDRAttributeInfo.xml @@ -0,0 +1,37 @@ + + + + Analog Devices Zynq SDR + true + + $(MATLAB_ROOT)/rtw/c/src/ext_mode/common/rtiostream_interface.c + + $(ARM_CORTEX_A_ROOT_DIR)/src/rtiostream_tcpip.c + codertarget.zynq.internal.extmodeHooksADI(hObj,'setupfcn'); + + TCP/IP + + + + + + + + + + $(TARGET_ROOT)/src/axi4Lite.c + $(TARGET_ROOT)/include + ARM_PROJECT + ADI_ZYNQ_SDR_IPADDRESS + ZYNQ_USERNAME + ZYNQ_PASSWORD + + codertarget.zynq.internal.onAfterCodeGen + codertarget.zynq.internal.onBuildEntryHook + codertarget.zynq.internal.onHardwareSelect + + diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/+util/ADIZynqSDRParameterInfo.xml b/hdl/vendor/AnalogDevices/+AnalogDevices/+util/ADIZynqSDRParameterInfo.xml new file mode 100755 index 0000000..5965474 --- /dev/null +++ b/hdl/vendor/AnalogDevices/+AnalogDevices/+util/ADIZynqSDRParameterInfo.xml @@ -0,0 +1,13 @@ + + + + Analog Devices Zynq SDR + + Clocking + + + + Build options + + + diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/+util/adizynqsdr.xml b/hdl/vendor/AnalogDevices/+AnalogDevices/+util/adizynqsdr.xml new file mode 100755 index 0000000..3df950a --- /dev/null +++ b/hdl/vendor/AnalogDevices/+AnalogDevices/+util/adizynqsdr.xml @@ -0,0 +1,16 @@ + + + + Analog Devices Zynq SDR + ARM Cortex-A9 + ARM Cortex-A + ARM Compatible->ARM Cortex + + "$(ARM_CORTEX_A_ROOT_DIR)/ssh_download.bat" + "$(MATLAB_ROOT)/toolbox/idelink/foundation/hostapps" root analog $(ADI_ZYNQ_SDR_IPADDRESS) /home/analog/Downloads + + $(TARGET_ROOT)/registry/parameters/ADIZynqSDRParameterInfo.xml + $(TARGET_ROOT)/registry/attributes/ADIZynqSDRAttributeInfo.xml + + + diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/+util/extmodeHooksADI.m b/hdl/vendor/AnalogDevices/+AnalogDevices/+util/extmodeHooksADI.m new file mode 100755 index 0000000..a600f58 --- /dev/null +++ b/hdl/vendor/AnalogDevices/+AnalogDevices/+util/extmodeHooksADI.m @@ -0,0 +1,21 @@ +function extmodeHooksADI(hObj,hookpoint) + +% Copyright 2014-2015 The MathWorks, Inc. + +modelName = get(getModel(hObj),'Name'); +modelName = sprintf('%s.elf', modelName); +data = codertarget.data.getData(hObj); +h__z = zynq(data.RTOS); +h__z.IPAddress = getenv('ADI_ZYNQ_SDR_IPADDRESS'); +h__z.Username = 'root'; +h__z.Password = 'analog'; + +switch (lower(hookpoint)) + case 'preconnectfcn', + waitForAppToStart(h__z, modelName, 60); + case 'setupfcn' + checkConnection(h__z); + otherwise +end + +end diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/add_clocks.m b/hdl/vendor/AnalogDevices/+AnalogDevices/add_clocks.m new file mode 100755 index 0000000..1faebf9 --- /dev/null +++ b/hdl/vendor/AnalogDevices/+AnalogDevices/add_clocks.m @@ -0,0 +1,22 @@ +function add_clocks(hRD,project,design) + +switch lower(project) + case 'cn0585' + switch(upper(design)) + case 'RX' + hRD.addClockInterface( ... + 'ClockConnection', 'axi_clkgen/clk_0', ... + 'ResetConnection', 'sampling_clk_rstgen/peripheral_aresetn'); + + case 'TX' + hRD.addClockInterface( ... + 'ClockConnection', 'axi_clkgen/clk_0', ... + 'ResetConnection', 'sampling_clk_rstgen/peripheral_aresetn'); + case 'RX & TX' + hRD.addClockInterface( ... + 'ClockConnection', 'axi_clkgen/clk_0', ... + 'ResetConnection', 'sampling_clk_rstgen/peripheral_aresetn'); + otherwise + error('Unknown reference design'); + end +end diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/add_io.m b/hdl/vendor/AnalogDevices/+AnalogDevices/add_io.m new file mode 100755 index 0000000..58f6341 --- /dev/null +++ b/hdl/vendor/AnalogDevices/+AnalogDevices/add_io.m @@ -0,0 +1,17 @@ +function add_io(hRD,project,fpga,type) + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% Add AXI4 and AXI4-Lite slave interfaces +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +out = AnalogDevices.get_memory_axi_interface_info(fpga,lower(project)); +hRD.addAXI4SlaveInterface( ... + 'InterfaceConnection', out.InterfaceConnection, ... + 'BaseAddress', out.BaseAddress, ... + 'MasterAddressSpace', out.MasterAddressSpace); + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% Add Reference design interfaces +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +AnalogDevices.add_io_ports(hRD,lower(project),lower(type),lower(fpga)); + +end \ No newline at end of file diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/add_io_ports.m b/hdl/vendor/AnalogDevices/+AnalogDevices/add_io_ports.m new file mode 100755 index 0000000..645e5a4 --- /dev/null +++ b/hdl/vendor/AnalogDevices/+AnalogDevices/add_io_ports.m @@ -0,0 +1,92 @@ +function root = add_io_ports(hRD,project,type,fpga) + +[filepath,~,~] = fileparts(mfilename('fullpath')); +fileName = fullfile(filepath,'ports.json'); +fid = fopen(fileName); +raw = fread(fid,inf); +str = char(raw'); +fclose(fid); +data = jsondecode(str); + +project = erase(project,'-'); +if ~contains(fields(data),project) + error(sprintf('No project found in database for %s',project)); +end + +root = getfield(data, project); + +if ~contains(root.supported_rd,type) + error(sprintf('No project found in database for %s',project)); +end + +if ~contains(root.fpga,fpga) + error(sprintf('No project found in database for %s',fpga)); +end + + +if contains(type,'rx') + process(hRD, root.ports.rx, 'rx'); +end +if contains(type,'tx') + process(hRD, root.ports.tx, 'tx'); +end + + +end + +function process(hRD, rtx, type) +count = [-1 -1]; +for i = 1:length(rtx) + rx = rtx(i); + if strcmpi(rx.type,'valid') + hRD.addInternalIOInterface( ... + 'InterfaceID', rx.m_name, ... + 'InterfaceType', inout(rx.input), ... + 'PortName', inout_pn(rx.input, type), ... + 'PortWidth', rx.width, ... + 'InterfaceConnection', rx.name, ... + 'IsRequired', false); + elseif strcmpi(rx.type,'data') + if strcmp(rx.input, 'true') + count(1)=count(1)+1; + else + count(2)=count(2)+1; + end + hRD.addInternalIOInterface( ... + 'InterfaceID', rx.m_name, ... + 'InterfaceType', inout(rx.input), ... + 'PortName', inout_pn_d(rx.input,count,type), ... + 'PortWidth', rx.width, ... + 'InterfaceConnection', rx.name, ... + 'IsRequired', false); + else + error(sprintf('Unknown port type %s',rx.type)); + end +end +end + +%% +function out = inout_pn_d(in,count,type) +if strcmp(in, 'true') + out = sprintf('dut_data_in_%d_%s',count(1), type); +else + out = sprintf('dut_data_out_%d_%s',count(2), type); +end +end +%% +function out = inout_pn(in, type) + if strcmp(in, 'true') + out = sprintf('dut_data_valid_in_%s', type); + else + out = sprintf('dut_data_valid_out_%s', type); + end +end +%% +function out = inout(in) +if strcmp(in, 'true') + out = 'IN'; +else + out = 'OUT'; +end +end + diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/get_memory_axi_interface_info.m b/hdl/vendor/AnalogDevices/+AnalogDevices/get_memory_axi_interface_info.m new file mode 100755 index 0000000..fb1328e --- /dev/null +++ b/hdl/vendor/AnalogDevices/+AnalogDevices/get_memory_axi_interface_info.m @@ -0,0 +1,21 @@ +function out = get_memory_axi_interface_info(fpga,project) + + +switch project + case 'cn0585' + switch fpga + case{'ZED'} + InterfaceConnection = 'axi_cpu_interconnect/M20_AXI'; + BaseAddress = '0x43C00000'; + MasterAddressSpace = 'sys_ps7/Data'; + otherwise + error(sprintf('Unknown Project FPGA %s/%s',project,fpga)); %#ok<*SPERR> + end + otherwise + error(sprintf('Unknown Project %s',project)); %#ok<*SPERR> +end + +out = struct('InterfaceConnection', InterfaceConnection, ... + 'BaseAddress', BaseAddress, ... + 'MasterAddressSpace', MasterAddressSpace); +end diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/install.m b/hdl/vendor/AnalogDevices/+AnalogDevices/install.m new file mode 100755 index 0000000..9337a51 --- /dev/null +++ b/hdl/vendor/AnalogDevices/+AnalogDevices/install.m @@ -0,0 +1,61 @@ +function install(mode) +% AnalogDevices.install adds/removes AnalogDevices HDL BSPs + +% Copyright 2015 MathWorks, Inc. All Rights Reserved. + + if nargin == 0 + mode = 0; + end + + %% Initialization + % Determine where we're operating out of + vendorRootDir = fileparts(strtok(mfilename('fullpath'), '+')); + + % Add/remove the common contents + commonRootDir = fullfile(fileparts(fileparts(vendorRootDir)), 'common'); + olddir = cd(commonRootDir); + cleanup = onCleanup(@()cd(olddir)); + hdlbsp.install(mode); + + + % Add/remove the vendor contents + paths = {... + fullfile(vendorRootDir),... + }; + + hdlbsp.util.vendorInstall(mode,paths); + + % Copy the Zynq SDR target definition file into the support package + source = []; + destination = []; + zynqRootDir = codertarget.zynq.internal.getSpPkgRootDir; + armRootDir = codertarget.arm_cortex_a.internal.getSpPkgRootDir; + + zynqTargetDir = fullfile(zynqRootDir,'registry/targethardware'); + source = [source {fullfile(vendorRootDir, '/+AnalogDevices/+util/adizynqsdr.xml')}]; + destination = [destination {fullfile(zynqTargetDir, 'adizynqsdr.xml')}]; + + zynqTargetDir = fullfile(zynqRootDir,'registry/attributes'); + source = [source {fullfile(vendorRootDir, '/+AnalogDevices/+util/ADIZynqSDRAttributeInfo.xml')}]; + destination = [destination {fullfile(zynqTargetDir, 'ADIZynqSDRAttributeInfo.xml')}]; + + zynqTargetDir = fullfile(zynqRootDir,'registry/parameters'); + source = [source {fullfile(vendorRootDir, '/+AnalogDevices/+util/ADIZynqSDRParameterInfo.xml')}]; + destination = [destination {fullfile(zynqTargetDir, 'ADIZynqSDRParameterInfo.xml')}]; + + source = [source {fullfile(vendorRootDir, '/+AnalogDevices/+util/extmodeHooksADI.m')}]; + destination = [destination {fullfile(zynqRootDir, '/+codertarget/+zynq/+internal/extmodeHooksADI.m')}]; + + source = [source {fullfile(armRootDir,'ssh_download.bat')}]; + destination = [destination {fullfile(zynqRootDir, 'ssh_download.bat')}]; + + if(mode == 0) + for i = 1:length(source) + copyfile(char(source(:,i)), char(destination(:,i)), 'f'); + end + else + for i = 1:length(destination) + delete(char(destination(:,i))); + end + end +end \ No newline at end of file diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_board.m b/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_board.m new file mode 100755 index 0000000..7fa2607 --- /dev/null +++ b/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_board.m @@ -0,0 +1,42 @@ +function hB = plugin_board(project, board) +% Use Plugin API to create board plugin object + +if nargin < 2 + board = ""; +end +hB = hdlcoder.Board; + +pname = project; + +% Target Board Information +hB.BoardName = sprintf('AnalogDevices %s', upper(pname)); +if nargin > 1 + hB.BoardName = sprintf('%s %s', hB.BoardName, upper(board)); +end + +% FPGA Device +hB.FPGAVendor = 'Xilinx'; + +% Determine the device based on the board +switch lower(project) + + case {'cn0585'} + switch(upper(board)) + case 'ZED' + hB.FPGADevice = sprintf('xc7%s', 'z020'); + hB.FPGAPackage = 'clg484'; + hB.FPGASpeed = '-1'; + hB.FPGAFamily = 'Zynq'; + end + +end + +% Tool Info +hB.SupportedTool = {'Xilinx Vivado'}; + +% FPGA JTAG chain position +hB.JTAGChainPosition = 2; + +%% Add interfaces +% Standard "External Port" interface + diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m b/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m new file mode 100755 index 0000000..b7736a5 --- /dev/null +++ b/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m @@ -0,0 +1,90 @@ +function hRD = plugin_rd(project, board, design) +% Reference design definition + +% Copyright 2014-2015 The MathWorks, Inc. + +pname = upper(project); +ppath = project; +if strcmpi(project, 'cn0585') + ppath = 'cn0585'; +end + +% Construct reference design object +hRD = hdlcoder.ReferenceDesign('SynthesisTool', 'Xilinx Vivado'); + +% Create the reference design for the SOM-only +% This is the base reference design that other RDs can build upon +hRD.ReferenceDesignName = sprintf('%s %s (%s)', pname, upper(board), upper(design)); + +% Determine the board name based on the design +hRD.BoardName = sprintf('AnalogDevices %s %s', pname, upper(board)); + +% Tool information +hRD.SupportedToolVersion = {'2022.2'}; + +% Get the root directory +rootDir = fileparts(strtok(mfilename('fullpath'), '+')); + +% Design files are shared +hRD.SharedRD = true; +hRD.SharedRDFolder = fullfile(rootDir, 'vivado'); + +%% Set top level project pieces +hRD.addParameter( ... + 'ParameterID', 'project', ... + 'DisplayName', 'HDL Project Subfolder', ... + 'DefaultValue', lower(ppath)); + +hRD.addParameter( ... + 'ParameterID', 'carrier', ... + 'DisplayName', 'HDL Project Carrier', ... + 'DefaultValue', lower(board)); + + +%% Add custom design files +% add custom Vivado design +hRD.addCustomVivadoDesign( ... + 'CustomBlockDesignTcl', fullfile('projects', 'scripts', 'system_project_rxtx.tcl'), ... + 'CustomTopLevelHDL', fullfile('projects', lower(ppath), lower(board), 'system_top.v')); + +hRD.BlockDesignName = 'system'; + +% custom constraint files +hRD.CustomConstraints = {... + fullfile('projects', lower(ppath), lower(board), 'system_constr.xdc'), ... + fullfile('projects', 'common', lower(board), sprintf('%s_system_constr.xdc', lower(board))), ... + }; + +% custom source files +hRD.CustomFiles = {... + fullfile('projects')..., + fullfile('library')..., + fullfile('scripts')..., + }; + +hRD.addParameter( ... + 'ParameterID', 'ref_design', ... + 'DisplayName', 'Reference Type', ... + 'DefaultValue', lower(strrep(design, ' & ',''))); + +hRD.addParameter( ... + 'ParameterID', 'fpga_board', ... + 'DisplayName', 'FPGA Boad', ... + 'DefaultValue', upper(board)); + +hRD.addParameter( ... + 'ParameterID', 'preprocess', ... + 'DisplayName', 'Preprocess', ... + 'DefaultValue', 'off'); + +hRD.addParameter( ... + 'ParameterID', 'postprocess', ... + 'DisplayName', 'Postprocess', ... + 'DefaultValue', 'off'); + +%% Add interfaces +% add clock interface +AnalogDevices.add_clocks(hRD,project,design) + +%% Add IO +AnalogDevices.add_io(hRD,project,board,design); diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/uninstall.m b/hdl/vendor/AnalogDevices/+AnalogDevices/uninstall.m new file mode 100755 index 0000000..ce1a433 --- /dev/null +++ b/hdl/vendor/AnalogDevices/+AnalogDevices/uninstall.m @@ -0,0 +1,7 @@ +function uninstall +% AnalogDevices.uninstall removes AnalogDevices HDL BSPs + +% Copyright 2015 MathWorks, Inc. All Rights Reserved. + + AnalogDevices.install(1); +end diff --git a/hdl/vendor/AnalogDevices/Contents.m b/hdl/vendor/AnalogDevices/Contents.m new file mode 100755 index 0000000..9aa4ea5 --- /dev/null +++ b/hdl/vendor/AnalogDevices/Contents.m @@ -0,0 +1,2 @@ +% Precision Toolbox: Analog Devices, Inc +% Version 21.1.1 (R2021a) 3-Dec-2021 \ No newline at end of file diff --git a/hdl/vendor/AnalogDevices/hdlcoder_board_customization.m b/hdl/vendor/AnalogDevices/hdlcoder_board_customization.m new file mode 100755 index 0000000..a83f72a --- /dev/null +++ b/hdl/vendor/AnalogDevices/hdlcoder_board_customization.m @@ -0,0 +1,15 @@ +function r = hdlcoder_board_customization +% Board plugin registration file +% 1. Any registration file with this name on MATLAB path will be picked up +% 2. Registration file returns a cell array pointing to the location of +% the board plugins +% 3. Board plugin must be a package folder accessible from MATLAB path, +% and contains a board definition file + +% Copyright 2012-2013 The MathWorks, Inc. + +r = { ... + 'AnalogDevices.cn0585.zed.plugin_board' ..., + }; +end +% LocalWords: Zynq ZC diff --git a/hdl/vendor/AnalogDevices/vivado/projects/scripts/matlab_processors.tcl b/hdl/vendor/AnalogDevices/vivado/projects/scripts/matlab_processors.tcl new file mode 100755 index 0000000..dc47d1f --- /dev/null +++ b/hdl/vendor/AnalogDevices/vivado/projects/scripts/matlab_processors.tcl @@ -0,0 +1,57 @@ +proc preprocess_bd {project carrier rxtx} { + + puts "Preprocessing $project $carrier $rxtx" + + switch $project { + cn0585 { + # Disconnect the ADC PACK pins + delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_data] + delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_data] + delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_data] + delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_data] + + set sys_cstring "matlab $rxtx" + sysid_gen_sys_init_file $sys_cstring + + #Disconnect adc_valid + delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_valid] + # Reconnect the adc_valid in the system + connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins axi_ltc2387_dma/fifo_wr_en] + + if {$rxtx == "rx"} { + connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins axi_ad3552r_0/data_in_a] + connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins axi_ad3552r_0/data_in_b] + connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins axi_ad3552r_1/data_in_a] + connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins axi_ad3552r_1/data_in_b] + } + + if {$rxtx == "tx"} { + connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_0] + connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_1] + connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_2] + connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_3] + connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_en] + } + + if {$rxtx == "tx" || $rxtx == "rxtx"} { + + delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_valid] + delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_valid] + delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_valid] + delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_valid] + + # Connect dac valids together + connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_0/valid_in_b] + connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_a] + connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_b] + } + switch $carrier { + zed { + set_property -dict [list CONFIG.NUM_MI {21}] [get_bd_cells axi_cpu_interconnect] + connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ACLK] [get_bd_pins axi_clkgen/clk_0] + connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ARESETN] [get_bd_pins sampling_clk_rstgen/peripheral_aresetn] + } + } + } + } +} diff --git a/pcx_examples/streaming/cn0585/CN0585_streaming.m b/pcx_examples/streaming/cn0585/CN0585_streaming.m new file mode 100644 index 0000000..a9d9e81 --- /dev/null +++ b/pcx_examples/streaming/cn0585/CN0585_streaming.m @@ -0,0 +1,74 @@ +% CN0585 Streaming example + +board_ip = 'local_board_ip'; +uri = cat(2, 'ip:', board_ip); + +% Describe the devices + +cn0585_device_rx = adi.CN0585.Rx('uri',uri); +cn0585_device_tx0 = adi.CN0585.Tx0('uri',uri); +cn0585_device_tx1 = adi.CN0585.Tx1('uri',uri); + +cn0585_device_tx0.EnableCyclicBuffers = true; +cn0585_device_tx1.EnableCyclicBuffers = true; + +cn0585_device_rx.BufferTypeConversionEnable = true; + +% Enable the channels to write data to (options are 1, 2 ) + +cn0585_device_tx0.EnabledChannels = [1, 2]; +cn0585_device_tx1.EnabledChannels = [1, 2]; + +% Enable the channels to read data from (options are 1, 2, 3 ,4 ) + +cn0585_device_rx.EnabledChannels = [1, 2, 3, 4]; + +% Generate the sinewave signal + +amplitude = 2 ^ 15; +sampFreq = cn0585_device_tx0.SamplingRate; +toneFreq = 1e3; +N = sampFreq / toneFreq; +x = linspace(-pi, pi, N).'; +sine_wave = amplitude * sin(x); + +% Continuously load data in the buffer and configure the GPIOs state +% (SetupInit Base file) +% DAC1 has to be updated and started first and then DAC0 in order to have syncronized data between devices + +cn0585_device_tx1([sine_wave, sine_wave]); +cn0585_device_tx0([sine_wave, sine_wave]); + +% Stream status available options: "start_stream_synced", "start_stream", "stop_stream" + +cn0585_device_tx1.StreamStatus = 'start_stream'; +cn0585_device_tx0.StreamStatus = 'start_stream'; + +% The data will be stored inside "data" variable + +data = cn0585_device_rx(); + +title('ADAQ23876 Channels'); +subplot(4, 1, 1); +plot(data(:, 1)); +ylabel('Channel A'); +subplot(4, 1, 2); +plot(data(:, 2)); +ylabel('Channel B'); +subplot(4, 1, 3); +plot(data(:, 3)); +ylabel('Channel C'); +subplot(4, 1, 4); +plot(data(:, 4)); +ylabel('Channel D'); +xlabel('Number of samples'); + +% Release the device + +cn0585_device_tx1.StreamStatus = 'stop_stream'; +cn0585_device_tx0.StreamStatus = 'stop_stream'; + +cn0585_device_tx1.release(); +cn0585_device_tx0.release(); + +cn0585_device_rx.release(); diff --git a/pcx_examples/streaming/cn0585/cn0585_axi4_lite_rw_demo/CN0585_streaming_axi4lite_read_write.m b/pcx_examples/streaming/cn0585/cn0585_axi4_lite_rw_demo/CN0585_streaming_axi4lite_read_write.m new file mode 100755 index 0000000..935eaa0 --- /dev/null +++ b/pcx_examples/streaming/cn0585/cn0585_axi4_lite_rw_demo/CN0585_streaming_axi4lite_read_write.m @@ -0,0 +1,96 @@ +% CN0585 Streaming example for AXI4 Lite register read/write + +board_ip = 'local_board_ip'; +uri = cat(2, 'ip:', board_ip); + +% Describe the devices + +cn0585_device_rx = adi.CN0585.Rx('uri',uri); +cn0585_device_tx0 = adi.CN0585.Tx0('uri',uri); +cn0585_device_tx1 = adi.CN0585.Tx1('uri',uri); + +cn0585_device_tx0.EnableCyclicBuffers = true; +cn0585_device_tx1.EnableCyclicBuffers = true; + +cn0585_device_rx.BufferTypeConversionEnable = true; + +% Enable the channels to write data to (options are 1, 2) + +cn0585_device_tx0.EnabledChannels = [1, 2]; +cn0585_device_tx1.EnabledChannels = [1, 2]; + +% Enable the channels to read data from (options are 1, 2, 3 ,4) + +cn0585_device_rx.EnabledChannels = [1, 2, 3, 4]; + +write_reg = soc.libiio.aximm.WriteHost(devName = 'mwipcore0:mmwr-channel0', IPAddress = board_ip); % MathWorks IP Core Write channel +read_reg = soc.libiio.aximm.WriteHost(devName = 'mwipcore0:mmrd-channel1', IPAddress = board_ip); % MathWorks IP Core Read channel + +% Input source available options: 'adc_input', 'dma_input', 'ramp_input' + +cn0585_device_tx0.InputSource = 'dma_input'; +cn0585_device_tx1.InputSource = 'dma_input'; + +% Output range available options: '0/2.5V', '0/5V', '0/10V', '-5/+5V', '-10/+10V' + +cn0585_device_tx0.OutputRange = '-10/+10V'; +cn0585_device_tx1.OutputRange = '-10/+10V'; + +% Generate the sinewave signal + +amplitude = 2 ^ 15; +sampFreq = cn0585_device_tx0.SamplingRate; +toneFreq = 1e3; +N = sampFreq / toneFreq; +x = linspace(-pi, pi, N).'; +sine_wave = amplitude * sin(x); + +% Continuously load data in the buffer and configure the GPIOs state +% (SetupInit Base file) +% DAC1 has to be updated and started first and then DAC0 in order to have syncronized data between devices + +cn0585_device_tx1([sine_wave, sine_wave]); +cn0585_device_tx0([sine_wave, sine_wave]); + +% Stream status available options: "start_stream_synced", "start_stream", "stop_stream" + +cn0585_device_tx1.StreamStatus = 'start_stream'; +cn0585_device_tx0.StreamStatus = 'start_stream'; + +% The data will be stored inside "data" variable + +data = cn0585_device_rx(); + +if cn0585_device_tx0.CheckMathWorksCore() + + write_reg.writeReg(hex2dec('100'), 85); + write_reg.writeReg(hex2dec('104'), 22); + + fprintf('Read value from the 0x108 register is: %d \n', read_reg.readReg(hex2dec('108'))); + fprintf('Read value from the 0x10c register is: %d \n', read_reg.readReg(hex2dec('10c'))); +end + +title('ADAQ23876 Channels'); +subplot(4, 1, 1); +plot(data(:, 1)); +ylabel('Channel A'); +subplot(4, 1, 2); +plot(data(:, 2)); +ylabel('Channel B'); +subplot(4, 1, 3); +plot(data(:, 3)); +ylabel('Channel C'); +subplot(4, 1, 4); +plot(data(:, 4)); +ylabel('Channel D'); +xlabel('Number of samples'); + +% Release the device + +cn0585_device_tx1.StreamStatus = 'stop_stream'; +cn0585_device_tx0.StreamStatus = 'stop_stream'; + +cn0585_device_tx1.release(); +cn0585_device_tx0.release(); + +cn0585_device_rx.release(); diff --git a/pcx_examples/streaming/cn0585/cn0585_axi4_lite_rw_demo/cn0585_host_axi4_lite_read_write_example.slx b/pcx_examples/streaming/cn0585/cn0585_axi4_lite_rw_demo/cn0585_host_axi4_lite_read_write_example.slx new file mode 100755 index 0000000..1b130f7 Binary files /dev/null and b/pcx_examples/streaming/cn0585/cn0585_axi4_lite_rw_demo/cn0585_host_axi4_lite_read_write_example.slx differ diff --git a/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_axi4_lite_demo/zynq-zed-adv7511-cn0585.dts b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_axi4_lite_demo/zynq-zed-adv7511-cn0585.dts new file mode 100644 index 0000000..d2260bb --- /dev/null +++ b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_axi4_lite_demo/zynq-zed-adv7511-cn0585.dts @@ -0,0 +1,269 @@ +/dts-v1/; + +#include "zynq-zed.dtsi" +#include "zynq-zed-adv7511.dtsi" +#include +#include +#include + +/ { + clocks { + ext_clk: clock@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <120000000>; + }; + }; + + one-bit-adc-dac@0 { + compatible = "adi,one-bit-adc-dac"; + #address-cells = <1>; + #size-cells = <0>; + + in-gpios = <&gpio_mux 4 GPIO_ACTIVE_HIGH>, + <&gpio_mux 5 GPIO_ACTIVE_HIGH>; + out-gpios = <&gpio_mux 3 GPIO_ACTIVE_HIGH>, + <&gpio_mux 2 GPIO_ACTIVE_HIGH>, + <&gpio_mux 1 GPIO_ACTIVE_HIGH>, + <&gpio_mux 0 GPIO_ACTIVE_HIGH>, + <&gpio_mux 6 GPIO_ACTIVE_HIGH>, + <&gpio_mux 7 GPIO_ACTIVE_HIGH>, + <&gpio_mux 11 GPIO_ACTIVE_HIGH>, + <&gpio_mux 12 GPIO_ACTIVE_HIGH>, + <&gpio_mux 13 GPIO_ACTIVE_HIGH>, + <&gpio_mux 14 GPIO_ACTIVE_HIGH>; + + channel@0 { + reg = <0>; + label = "GPIO4_VIO"; + }; + channel@1 { + reg = <1>; + label = "GPIO5_VIO"; + }; + channel@2 { + reg = <2>; + label = "GPIO0_VIO"; + }; + channel@3 { + reg = <3>; + label = "GPIO1_VIO"; + }; + channel@4 { + reg = <4>; + label = "GPIO2_VIO"; + }; + channel@5 { + reg = <5>; + label = "GPIO3_VIO"; + }; + channel@6 { + reg = <6>; + label = "GPIO6_VIO"; + }; + channel@7 { + reg = <7>; + label = "GPIO7_VIO"; + }; + channel@8 { + reg = <8>; + label = "PAD_ADC0"; + }; + channel@9 { + reg = <9>; + label = "PAD_ADC1"; + }; + channel@10 { + reg = <10>; + label = "PAD_ADC2"; + }; + channel@11 { + reg = <11>; + label = "PAD_ADC3"; + }; + }; +}; + +&fpga_axi { + axi_pwm_gen: pwm@44B10000 { + compatible = "adi,axi-pwmgen"; + reg = <0x44B10000 0x1000>; + label = "ltc2387_if"; + #pwm-cells = <2>; + clocks = <&ext_clk>; + }; + + ref_clk: clk@44B00000 { + compatible = "adi,axi-clkgen-2.00.a"; + reg = <0x44B00000 0x10000>; + #clock-cells = <0>; + clocks = <&clkc 15>, <&clkc 15>; + clock-names = "s_axi_aclk", "clkin1"; + clock-output-names = "ref_clk"; + }; + + rx_dma: dmac@44A40000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x44A40000 0x1000>; + #dma-cells = <1>; + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc 15>; + + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + + dma-channel@0 { + reg = <0>; + adi,source-bus-width = <64>; + adi,source-bus-type = <2>; + adi,destination-bus-width = <64>; + adi,destination-bus-type = <0>; + }; + }; + }; + + ltc2387@0{ + compatible = "ltc2387-16-x4"; + pwms = <&axi_pwm_gen 0 0 + &axi_pwm_gen 1 0>; + pwm-names = "cnv", "clk_en"; + clocks = <&ref_clk>; + dmas = <&rx_dma 0>; + dma-names = "rx"; + adi,use-two-lanes; + }; + + qspi0: spi@0x44B20000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x44B20000 0x1000>; + num-cs = <0x2>; + compatible = "xlnx,xps-spi-2.00.a"; + bits-per-word = <16>; + fifo-size = <16>; + clock-names = "ext_spi_clk", "s_axi_aclk"; + clocks = <&clkc 15>, <&clkc 15>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&intc>; + interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; + + gpio_mux: max7301@0 { + compatible = "max7301"; + reg = <0>; + spi-max-frequency = <20000000>; + #gpio-cells = <2>; + gpio-controller; + }; + }; + + dac0_tx_dma: tx-dmac@0x44D30000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x44D30000 0x10000>; + #dma-cells = <1>; + interrupt-parent = <&intc>; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc 15>; + + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + + dma-channel@0 { + reg = <0>; + adi,source-bus-width = <32>; + adi,source-bus-type = <0>; + adi,destination-bus-width = <32>; + adi,destination-bus-type = <1>; + }; + }; + }; + + dac1_tx_dma: tx-dmac@0x44E30000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x44E30000 0x10000>; + #dma-cells = <1>; + interrupt-parent = <&intc>; + interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc 15>; + + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + + dma-channel@0 { + reg = <0>; + adi,source-bus-width = <32>; + adi,source-bus-type = <0>; + adi,destination-bus-width = <32>; + adi,destination-bus-type = <1>; + }; + }; + }; + + axi_ad3552r_0: axi-ad3552r-0@44d04000 { + compatible = "adi,axi-ad3552r"; + reg = <0x44d04000 0x1000>; + + reset-gpios = <&gpio0 90 GPIO_ACTIVE_LOW>; + + clocks = <&ref_clk>; + + dmas = <&dac0_tx_dma 0>; + dma-names = "tx"; + }; + + axi_ad3552r_1: axi-ad3552r-1@44e04000 { + compatible = "adi,axi-ad3552r"; + reg = <0x44e04000 0x1000>; + + clocks = <&ref_clk>; + + dmas = <&dac1_tx_dma 0>; + dma-names = "tx"; + }; + + mwipcore@43c00000 { + compatible = "mathworks,mwipcore-v3.00"; + reg = <0x43C00000 0xfffff>; + #address-cells = <1>; + #size-cells = <0>; + mmwr-channel@0{ + reg = <0x0>; + compatible = "mathworks,mm-write-channel-v1.00"; + }; + mmrd-channel@1{ + reg = <0x1>; + compatible = "mathworks,mm-read-channel-v1.00"; + }; + + + }; + + i2c@41620000 { + compatible = "xlnx,axi-iic-1.01.b", "xlnx,xps-iic-2.00.a"; + reg = <0x41620000 0x10000>; + interrupt-parent = <&intc>; + interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc 15>; + clock-names = "pclk"; + + #size-cells = <0>; + #address-cells = <1>; + + eeprom@50 { + compatible = "at24,24c02"; + reg = <0x50>; + }; + eeprom2@54 { + compatible = "at24,24c02"; + reg = <0x54>; + }; + ad7291_1@20 { + label = "ADC_I2C_1"; + compatible = "adi,ad7291"; + reg = <0x20>; + }; + + }; +}; diff --git a/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/add_io.m b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/add_io.m new file mode 100644 index 0000000..6cd8cdc --- /dev/null +++ b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/add_io.m @@ -0,0 +1,17 @@ +% function add_io(hRD,project,fpga,type) +% +% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% % Add AXI4 and AXI4-Lite slave interfaces +% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% out = AnalogDevices.get_memory_axi_interface_info(fpga,lower(project)); +% hRD.addAXI4SlaveInterface( ... +% 'InterfaceConnection', out.InterfaceConnection, ... +% 'BaseAddress', out.BaseAddress, ... +% 'MasterAddressSpace', out.MasterAddressSpace); +% +% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% % Add Reference design interfaces +% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% AnalogDevices.add_io_ports(hRD,lower(project),lower(type),lower(fpga)); +% +% end diff --git a/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/hdlcoder_ref_design_customization.m b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/hdlcoder_ref_design_customization.m new file mode 100644 index 0000000..31e4cea --- /dev/null +++ b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/hdlcoder_ref_design_customization.m @@ -0,0 +1,20 @@ +function [rd,boardName] = hdlcoder_ref_design_customization +% Reference design plugin registration file +% 1. The registration file with this name inside of a board plugin folder +% will be picked up +% 2. Any registration file with this name on MATLAB path will also be picked up +% 3. The registration file returns a cell array pointing to the location of +% the reference design plugins +% 4. The registration file also returns its associated board name +% 5. Reference design plugin must be a package folder accessible from +% MATLAB path, and contains a reference design definition file + +% Copyright 2013-2014 The MathWorks, Inc. + +rd = {... + 'AnalogDevicesDemo.cn0585_led_sw_gpio_control_demo.zed.tx.plugin_rd', ... + }; + +boardName = 'AnalogDevices CN0585 GPIO Control'; + +end diff --git a/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_board.m b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_board.m new file mode 100644 index 0000000..27d0b67 --- /dev/null +++ b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_board.m @@ -0,0 +1,29 @@ +function hB = plugin_board(BoardName) +% Use Plugin API to create board plugin object + +% Copyright 2015 The MathWorks, Inc. + +hB = hdlcoder.Board; + +% Target Board Information +hB.BoardName = sprintf('AnalogDevices CN0585 GPIO Control'); + +% FPGA Device +hB.FPGAVendor = 'Xilinx'; +hB.FPGAFamily = 'Zynq'; + +% Determine the device based on the board + +hB.FPGADevice = sprintf('xc7%s', 'z020'); +hB.FPGAPackage = 'clg484'; +hB.FPGASpeed = '-1'; +hB.FPGAFamily = 'Zynq'; + +% Tool Info +hB.SupportedTool = {'Xilinx Vivado'}; + +% FPGA JTAG chain position +hB.JTAGChainPosition = 2; + +%% Add interfaces +% Standard "External Port" interface diff --git a/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_rd.m b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_rd.m new file mode 100644 index 0000000..d277e32 --- /dev/null +++ b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_rd.m @@ -0,0 +1,110 @@ +function hRD = plugin_rd(board, design) +% Reference design definition + +% Copyright 2014-2015 The MathWorks, Inc. + +% pname = upper(project); +% ppath = project; +% if strcmpi(project, 'cn0585') +% ppath = 'cn0585'; +% end + +board = 'zed'; +design = 'Tx'; + +hRD = hdlcoder.ReferenceDesign('SynthesisTool', 'Xilinx Vivado'); + +% This is the base reference design that other RDs can build upon +hRD.ReferenceDesignName = sprintf('%s (%s)', upper(board), design); + +% Determine the board name based on the design +hRD.BoardName = sprintf('AnalogDevices CN0585 GPIO Control'); + +% Tool information +hRD.SupportedToolVersion = {'2023.2'}; + +% Get the root directories +rootDirExample = fileparts(strtok(mfilename('fullpath'), '+')); +tmp = strsplit(rootDirExample,filesep); + +if isunix + rootDir = fullfile(filesep,tmp{1:end-3}); +else + rootDir = fullfile(tmp{1:end-3}); +end +rootDirBSP = fullfile('hdl','vendor','AnalogDevices','vivado'); + +% Design files are shared +hRD.SharedRD = true; +hRD.SharedRDFolder = rootDir; + +%% Set top level project pieces +hRD.addParameter( ... + 'ParameterID', 'project', ... + 'DisplayName', 'HDL Project Subfolder', ... + 'DefaultValue', 'cn0585'); + +hRD.addParameter( ... + 'ParameterID', 'carrier', ... + 'DisplayName', 'HDL Project Carrier', ... + 'DefaultValue', 'zed'); + +%% Add custom design files +hRD.addCustomVivadoDesign( ... + 'CustomBlockDesignTcl', fullfile('pcx_examples', 'targeting', 'cn0585', 'cn0585_hdl', 'system_project_rxtx.tcl')); + +%% Standard reference design pieces +hRD.BlockDesignName = 'system'; + +% custom source files +hRD.CustomFiles = {... + fullfile('projects')..., + fullfile('library')..., + fullfile('scripts')..., + }; + +% custom source files +hRD.CustomFiles = {... + fullfile(rootDirBSP, 'scripts')..., + fullfile(rootDirBSP, 'library')..., + fullfile(rootDirBSP, 'library','xilinx')..., + fullfile(rootDirBSP, 'projects','common')..., + fullfile(rootDirBSP, 'projects','scripts')..., + fullfile(rootDirBSP, 'projects','cn0585')..., + fullfile(rootDirBSP, 'projects','cn0585', 'common')..., + fullfile(rootDirBSP, 'projects','cn0585', 'zed')..., + fullfile('pcx_examples', 'targeting', 'cn0585', 'cn0585_hdl')..., + }; + +hRD.addParameter( ... + 'ParameterID', 'ref_design', ... + 'DisplayName', 'Reference Type', ... + 'DefaultValue', lower(strrep(design, ' & ',''))); + +hRD.addParameter( ... + 'ParameterID', 'fpga_board', ... + 'DisplayName', 'FPGA Boad', ... + 'DefaultValue', upper(board)); + +hRD.addParameter( ... + 'ParameterID', 'preprocess', ... + 'DisplayName', 'Preprocess', ... + 'DefaultValue', 'on'); +hRD.addParameter( ... + 'ParameterID', 'preprocess_script', ... + 'DisplayName', 'Preprocess Script', ... + 'DefaultValue', fullfile('pcx_examples', 'targeting', 'cn0585','cn0585_hdl','fh_preprocess.tcl')); + +hRD.addParameter( ... + 'ParameterID', 'postprocess', ... + 'DisplayName', 'Postprocess', ... + 'DefaultValue', 'off'); + +%% Add IO +%AnalogDevices.add_io(hRD,'cn0585_led_sw_gpio_control_demo',board,design); + +%% Add interfaces +% add clock interface +hRD.addClockInterface( ... + 'ClockConnection', 'axi_clkgen/clk_0', ... + 'ResetConnection', 'sampling_clk_rstgen/peripheral_aresetn'); diff --git a/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/add_tx_io.m b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/add_tx_io.m new file mode 100644 index 0000000..a5c9ae0 --- /dev/null +++ b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/add_tx_io.m @@ -0,0 +1,107 @@ +function add_tx_io(hRD) + +% add AXI4 and AXI4-Lite slave interfaces +hRD.addAXI4SlaveInterface( ... + 'InterfaceConnection', 'axi_cpu_interconnect/M20_AXI', ... + 'BaseAddress', '0x43C00000', ... + 'MasterAddressSpace', 'sys_ps7/Data'); + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% Tx Reference design interfaces +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 0 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'axi_ltc2387_0_adc_data', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ltc2387_0/adc_data', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 1 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'axi_ltc2387_1_adc_data', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ltc2387_1/adc_data', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 2 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'axi_ltc2387_2_adc_data', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ltc2387_2/adc_data', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 3 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'axi_ltc2387_3_adc_data', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ltc2387_3/adc_data', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Load Tx Data OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad3552r_0_valid_in_a', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'axi_ad3552r_0/valid_in_a', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Valid Tx Data IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'axi_ltc2387_0_adc_valid', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'axi_ltc2387_0/adc_valid', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'CN0585 DAC Data 0 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad3552r_0_data_in_a', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad3552r_0/data_in_a', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'CN0585 DAC Data 1 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad3552r_0_data_in_b', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad3552r_0/data_in_b', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'CN0585 DAC Data 2 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad3552r_1_data_in_a', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad3552r_1/data_in_a', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'CN0585 DAC Data 3 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad3552r_1_data_in_b', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad3552r_1/data_in_b', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'GPIO IN SW', ... + 'InterfaceType', 'IN', ... + 'PortName', 'xlslice_1_Dout', ... + 'PortWidth', 8, ... + 'InterfaceConnection', 'xlslice_1/Dout', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'GPIO OUT LED', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'xlconcat_1_In1', ... + 'PortWidth', 8, ... + 'InterfaceConnection', 'xlconcat_1/In1', ... + 'IsRequired', false); diff --git a/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/hdlcoder_ref_design_customization.m b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/hdlcoder_ref_design_customization.m new file mode 100644 index 0000000..350b2b3 --- /dev/null +++ b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/hdlcoder_ref_design_customization.m @@ -0,0 +1,20 @@ +function [rd, boardName] = hdlcoder_ref_design_customization +% Reference design plugin registration file +% 1. The registration file with this name inside of a board plugin folder +% will be picked up +% 2. Any registration file with this name on MATLAB path will also be picked up +% 3. The registration file returns a cell array pointing to the location of +% the reference design plugins +% 4. The registration file also returns its associated board name +% 5. Reference design plugin must be a package folder accessible from +% MATLAB path, and contains a reference design definition file + +% Copyright 2013-2014 The MathWorks, Inc. + +rd = {... + 'AnalogDevicesDemo.cn0585_led_sw_gpio_control_demo.zed.tx.plugin_rd', ... + }; + +boardName = 'AnalogDevicesDemo cn0585_led_sw_gpio_control AnalogDevies CN0585 GPIO Control (Tx)'; + +end diff --git a/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_board.m b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_board.m new file mode 100644 index 0000000..8e69678 --- /dev/null +++ b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_board.m @@ -0,0 +1,9 @@ +function hP = plugin_board() +% Zynq Platform PCore +% Use Plugin API to create board plugin object + +% Copyright 2015 The MathWorks, Inc. + +% Call the common board definition function +% hP = AnalogDevicesDemo.cn0585_led_sw_gpio_control_demo.common.plugin_board('AnalogDevies CN0585 GPIO Control ', 'Tx'); +hP = AnalogDevicesDemo.cn0585_led_sw_gpio_control_demo.common.plugin_board('AnalogDevies CN0585 GPIO Control'); \ No newline at end of file diff --git a/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_rd.m b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_rd.m new file mode 100644 index 0000000..f381dcf --- /dev/null +++ b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_rd.m @@ -0,0 +1,8 @@ +function hRD = plugin_rd +% Reference design definition + +% Copyright 2014-2015 The MathWorks, Inc. + +% Call the common reference design definition function +hRD = AnalogDevicesDemo.cn0585_led_sw_gpio_control_demo.common.plugin_rd('AnalogDevies CN0585 GPIO Control', 'Tx'); +AnalogDevicesDemo.cn0585_led_sw_gpio_control_demo.zed.tx.add_tx_io(hRD); diff --git a/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/hdlworkflow_cn0585_gpio_zed_tx.m b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/hdlworkflow_cn0585_gpio_zed_tx.m new file mode 100644 index 0000000..bd9e518 --- /dev/null +++ b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/hdlworkflow_cn0585_gpio_zed_tx.m @@ -0,0 +1,38 @@ +function out = hdlworkflow_cn0585_gpio_zed_tx(vivado) + +if nargin < 1 + vivado = '2022.2'; +end + +%-------------------------------------------------------------------------- +% HDL Workflow Script +% Generated with MATLAB 9.8 (R2020a) at 12:56:00 on 24/09/2020 +% This script was generated using the following parameter values: +% Filename : '/tmp/hsx-add-boot-bin-test/test/hdlworkflow_daq2_zcu102_rx.m' +% Overwrite : true +% Comments : true +% Headers : true +% DUT : 'testModel_Rx64Tx64/HDL_DUT' +% To view changes after modifying the workflow, run the following command: +% >> hWC.export('DUT','testModel_Rx64Tx64/HDL_DUT'); +%-------------------------------------------------------------------------- + +%% Load the Model +load_system('testModel_Tx16and8'); + +%% Restore the Model to default HDL parameters +hdlrestoreparams('testModel_Tx16and8/HDL_DUT'); + +%% Model HDL Parameters +%% Set Model 'testModel_Rx64Tx64' HDL parameters +hdlset_param('testModel_Tx16and8', 'HDLSubsystem', 'testModel_Tx16and8/HDL_DUT'); +hdlset_param('testModel_Tx16and8', 'ReferenceDesign', 'AnalogDevies CN0585 GPIO Control (TX)'); +hdlset_param('testModel_Tx16and8', 'SynthesisTool', 'Xilinx Vivado'); +hdlset_param('testModel_Tx16and8', 'SynthesisToolChipFamily', 'Zynq'); +hdlset_param('testModel_Tx16and8', 'SynthesisToolDeviceName', 'xc7z020-clg484-1'); +hdlset_param('testModel_Tx16and8', 'SynthesisToolPackageName', ''); +hdlset_param('testModel_Tx16and8', 'SynthesisToolSpeedValue', ''); +hdlset_param('testModel_Tx16and8', 'TargetDirectory', 'hdl_prj/hdlsrc'); +hdlset_param('testModel_Tx16and8', 'TargetLanguage', 'Verilog'); +hdlset_param('testModel_Tx16and8', 'TargetPlatform', 'AnalogDevices CN0585 GPIO Control'); +hdlset_param('testModel_Tx16and8', 'Workflow', 'IP Core Generation'); diff --git a/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/testModel_Tx16and8.slx b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/testModel_Tx16and8.slx new file mode 100644 index 0000000..55d8cf3 Binary files /dev/null and b/pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/testModel_Tx16and8.slx differ diff --git a/pcx_examples/targeting/cn0585/cn0585_hdl/adi_build.tcl b/pcx_examples/targeting/cn0585/cn0585_hdl/adi_build.tcl new file mode 100644 index 0000000..4609ed6 --- /dev/null +++ b/pcx_examples/targeting/cn0585/cn0585_hdl/adi_build.tcl @@ -0,0 +1,59 @@ +# Define local variables +set cdir [pwd] +set sdk_loc vivado_prj.sdk +set project_system_dir vivado_prj.srcs/sources_1/bd/system +set prj_carrier $project$carrier + +set fpga_board_lc [string tolower $fpga_board] + +puts "FPGA Board: $fpga_board_lc" + +# Verify support files exist +if {![file exists $cdir/projects/common/boot/$fpga_board_lc/u-boot.elf]} { + puts "ERROR: Missing u-boot.elf for $fpga_board_lc" + return +} + +# Build the project +update_compile_order -fileset sources_1 +reset_run impl_1 +reset_run synth_1 +set_property synth_checkpoint_mode Hierarchical [get_files $project_system_dir/system.bd] +export_ip_user_files -of_objects [get_files $project_system_dir/system.bd] -no_script -sync -force -quiet +launch_runs synth_1 +wait_on_run synth_1 +launch_runs impl_1 -to_step write_bitstream +wait_on_run impl_1 + +# Export the hdf +file delete -force $sdk_loc +file mkdir $sdk_loc +write_hw_platform -fixed -force -include_bit -file $sdk_loc/system_top.xsa + +# Close the Vivado project +close_project + +# Create the BOOT.bin +puts "Generating BOOT.BIN" +puts "Please wait, this may take a few minutes." +file mkdir $cdir/boot +file copy -force $cdir/vivado_prj.runs/impl_1/system_top.bit $cdir/boot/system_top.bit +file copy -force $cdir/projects/common/boot/$fpga_board_lc/u-boot.elf $cdir/boot/u-boot.elf +file copy -force $cdir/projects/common/boot/$fpga_board_lc/zynq.bif $cdir/boot/zynq.bif +file copy -force $cdir/projects/common/boot/$fpga_board_lc/fsbl.elf $cdir/boot/fsbl.elf + +if {$fpga_board_lc == "zcu102"} { + file copy -force $cdir/projects/common/boot/$fpga_board_lc/bl31.elf $cdir/boot/bl31.elf + file copy -force $cdir/projects/common/boot/$fpga_board_lc/pmufw.elf $cdir/boot/pmufw.elf + cd $cdir/boot + exec bootgen -arch zynqmp -image zynq.bif -o BOOT.BIN -w +} else { + cd $cdir/boot + exec bootgen -arch zynq -image zynq.bif -o BOOT.BIN -w +} + +puts "------------------------------------" +puts "Embedded system build completed." +puts "You may close this shell." +puts "------------------------------------" +exit diff --git a/pcx_examples/targeting/cn0585/cn0585_hdl/build_bsp.sh b/pcx_examples/targeting/cn0585/cn0585_hdl/build_bsp.sh new file mode 100755 index 0000000..d8ec41d --- /dev/null +++ b/pcx_examples/targeting/cn0585/cn0585_hdl/build_bsp.sh @@ -0,0 +1,88 @@ +#!/bin/bash +set -x +cd "$(dirname "$0")" +if [ -z "${HDLBRANCH}" ]; then +HDLBRANCH='main' +fi + +# Script is designed to run from specific location +scriptdir=`dirname "$BASH_SOURCE"` +cd $scriptdir +#cd .. +# Get HDL +if [ -d "hdl" ]; then + rm -rf "hdl" +fi +for i in {1..5} +do + if git clone --single-branch -b $HDLBRANCH https://github.com/analogdevicesinc/hdl.git + then + break + fi + if [ -d "hdl" ]; then + break + fi +done +if [ ! -d "hdl" ]; then + echo "HDL clone failed" + exit 1 +fi + +# Get required vivado version needed for HDL +if [ -f "hdl/library/scripts/adi_ip.tcl" ]; then + TARGET="hdl/library/scripts/adi_ip.tcl" +else + TARGET="hdl/library/scripts/adi_ip_xilinx.tcl" +fi +VER=$(awk '/set required_vivado_version/ {print $3}' $TARGET | sed 's/"//g') +echo "Required Vivado version ${VER}" +VIVADOFULL=${VER} +if [ ${#VER} = 8 ] +then +VER=${VER:0:6} +fi +VIVADO=${VER} + +# Setup +#source /opt/Xilinx/Vivado/$VIVADO/settings64.sh +source /emea/mediadata/opt/Xilinx/Vivado/$VIVADO/settings64.sh + +# Rename .prj files since MATLAB ignores then during packaging +FILES=$(grep -lrn hdl/projects/common -e '.prj' | grep -v Makefile | grep -v .git) +for f in $FILES +do + echo "Updating prj reference in: $f" + sed -i "s/\.prj/\.mk/g" "$f" +done +FILES=$(find hdl/projects/common -name "*.prj") +for f in $FILES +do + DEST="${f::-3}mk" + echo "Renaming: $f to $DEST" + mv "$f" "$DEST" +done + +# Remove git directory move to bsp folder +rm -fr hdl/.git* +TARGET="../../../../hdl/vendor/AnalogDevices/vivado" +if [ -d "$TARGET" ]; then + rm -rf "$TARGET" +fi + +mv hdl $TARGET + +# Post-process ports.json +cp ./ports.json ../../../../CI/ +python3 ../../../../CI/scripts/read_ports_json.py +cp ../../../../CI/ports.json ../../../../hdl/vendor/AnalogDevices/+AnalogDevices/ + +# Updates +cp ./matlab_processors.tcl ../../../../hdl/vendor/AnalogDevices/vivado/projects/scripts/matlab_processors.tcl +cp ./system_project_rxtx.tcl ../../../../hdl/vendor/AnalogDevices/vivado/projects/scripts/system_project_rxtx.tcl +cp ./adi_build.tcl ../../../../hdl/vendor/AnalogDevices/vivado/projects/scripts/adi_build.tcl + +# Copy boot files +mkdir ../../../../hdl/vendor/AnalogDevices/vivado/projects/common/boot/ +cp -r ../../../../CI/scripts/boot/* ../../../../hdl/vendor/AnalogDevices/vivado/projects/common/boot/ + +echo 'puts "Skipping"' > ../../../../hdl/vendor/AnalogDevices/vivado/library/axi_ad9361/axi_ad9361_delay.tcl diff --git a/pcx_examples/targeting/cn0585/cn0585_hdl/fh_preprocess.tcl b/pcx_examples/targeting/cn0585/cn0585_hdl/fh_preprocess.tcl new file mode 100644 index 0000000..38d8bcb --- /dev/null +++ b/pcx_examples/targeting/cn0585/cn0585_hdl/fh_preprocess.tcl @@ -0,0 +1,6 @@ +set ad_hdl_dir [pwd] + +#### Move files +file rename -force $ad_hdl_dir/hdl/vendor/AnalogDevices/vivado/scripts $ad_hdl_dir/scripts +file rename -force $ad_hdl_dir/hdl/vendor/AnalogDevices/vivado/projects $ad_hdl_dir/projects +file rename -force $ad_hdl_dir/hdl/vendor/AnalogDevices/vivado/library $ad_hdl_dir/library diff --git a/pcx_examples/targeting/cn0585/cn0585_hdl/matlab_processors.tcl b/pcx_examples/targeting/cn0585/cn0585_hdl/matlab_processors.tcl new file mode 100755 index 0000000..ece7ad2 --- /dev/null +++ b/pcx_examples/targeting/cn0585/cn0585_hdl/matlab_processors.tcl @@ -0,0 +1,138 @@ +proc preprocess_bd {project carrier rxtx} { + + puts "Preprocessing $project $carrier $rxtx" + + switch $project { + cn0585 { + # Disconnect the ADC PACK pins + delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_data] + delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_data] + delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_data] + delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_data] + + set sys_cstring "matlab $rxtx" + sysid_gen_sys_init_file $sys_cstring + + # Disconnect adc_valid + delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_valid] + # Reconnect the adc_valid in the system + connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins axi_ltc2387_dma/fifo_wr_en] + + if {$rxtx == "rx"} { + connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins axi_ad3552r_0/data_in_a] + connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins axi_ad3552r_0/data_in_b] + connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins axi_ad3552r_1/data_in_a] + connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins axi_ad3552r_1/data_in_b] + } + + if {$rxtx == "tx"} { + connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_0] + connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_1] + connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_2] + connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_3] + connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_en] + } + + if {$rxtx == "tx" || $rxtx == "rxtx"} { + + delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_valid] + delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_valid] + delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_valid] + delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_valid] + + # Connect dac valids together + connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_0/valid_in_b] + connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_a] + connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_b] + + # Remove the gpio bd connections + delete_bd_objs [get_bd_nets gpio_i_1] + delete_bd_objs [get_bd_nets sys_ps7_GPIO_O] + # Split the input gpios into 3 to separate the switches + create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 + set_property -dict [list \ + CONFIG.DIN_FROM {63} \ + CONFIG.DIN_TO {19} \ + CONFIG.DIN_WIDTH {64} \ + CONFIG.DOUT_WIDTH {45} \ + ] [get_bd_cells xlslice_0] + create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 + set_property -dict [list \ + CONFIG.DIN_FROM {18} \ + CONFIG.DIN_TO {11} \ + CONFIG.DIN_WIDTH {64} \ + CONFIG.DOUT_WIDTH {8} \ + ] [get_bd_cells xlslice_1] + create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 + set_property -dict [list \ + CONFIG.DIN_FROM {10} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {64} \ + CONFIG.DOUT_WIDTH {11} \ + ] [get_bd_cells xlslice_2] + # Reconnect the input gpios + connect_bd_net [get_bd_ports gpio_i] [get_bd_pins xlslice_0/Din] + connect_bd_net [get_bd_ports gpio_i] [get_bd_pins xlslice_1/Din] + connect_bd_net [get_bd_ports gpio_i] [get_bd_pins xlslice_2/Din] + create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 + set_property CONFIG.NUM_PORTS {3} [get_bd_cells xlconcat_0] + set_property -dict [list CONFIG.IN2_WIDTH.VALUE_SRC USER CONFIG.IN1_WIDTH.VALUE_SRC USER CONFIG.IN0_WIDTH.VALUE_SRC USER] [get_bd_cells xlconcat_0] + set_property -dict [list \ + CONFIG.IN0_WIDTH {45} \ + CONFIG.IN1_WIDTH {8} \ + CONFIG.IN2_WIDTH {11} \ + ] [get_bd_cells xlconcat_0] + connect_bd_net [get_bd_pins xlslice_0/Dout] [get_bd_pins xlconcat_0/In0] + connect_bd_net [get_bd_pins xlslice_2/Dout] [get_bd_pins xlconcat_0/In2] + # Reconnect the input gpios to the ps7 + connect_bd_net [get_bd_pins sys_ps7/GPIO_I] [get_bd_pins xlconcat_0/dout] + # Split the output gpios into 3 to separate the leds + create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_3 + set_property -dict [list \ + CONFIG.DIN_FROM {63} \ + CONFIG.DIN_TO {27} \ + CONFIG.DIN_WIDTH {64} \ + CONFIG.DOUT_WIDTH {37} \ + ] [get_bd_cells xlslice_3] + create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_4 + set_property -dict [list \ + CONFIG.DIN_FROM {26} \ + CONFIG.DIN_TO {19} \ + CONFIG.DIN_WIDTH {64} \ + CONFIG.DOUT_WIDTH {8} \ + ] [get_bd_cells xlslice_4] + create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_5 + set_property -dict [list \ + CONFIG.DIN_FROM {18} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {64} \ + CONFIG.DOUT_WIDTH {19} \ + ] [get_bd_cells xlslice_5] + # Reconnect the output gpios + connect_bd_net [get_bd_pins sys_ps7/GPIO_O] [get_bd_pins xlslice_3/Din] + connect_bd_net [get_bd_pins sys_ps7/GPIO_O] [get_bd_pins xlslice_4/Din] + connect_bd_net [get_bd_pins sys_ps7/GPIO_O] [get_bd_pins xlslice_5/Din] + create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 + set_property CONFIG.NUM_PORTS {3} [get_bd_cells xlconcat_1] + set_property -dict [list CONFIG.IN2_WIDTH.VALUE_SRC USER CONFIG.IN1_WIDTH.VALUE_SRC USER CONFIG.IN0_WIDTH.VALUE_SRC USER] [get_bd_cells xlconcat_1] + set_property -dict [list \ + CONFIG.IN0_WIDTH {37} \ + CONFIG.IN1_WIDTH {8} \ + CONFIG.IN2_WIDTH {19} \ + ] [get_bd_cells xlconcat_1] + connect_bd_net [get_bd_pins xlslice_3/Dout] [get_bd_pins xlconcat_1/In0] + connect_bd_net [get_bd_pins xlslice_5/Dout] [get_bd_pins xlconcat_1/In2] + # Reconnect the output gpios to the output port + connect_bd_net [get_bd_ports gpio_o] [get_bd_pins xlconcat_1/Dout] + + } + switch $carrier { + zed { + set_property -dict [list CONFIG.NUM_MI {21}] [get_bd_cells axi_cpu_interconnect] + connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ACLK] [get_bd_pins axi_clkgen/clk_0] + connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ARESETN] [get_bd_pins sampling_clk_rstgen/peripheral_aresetn] + } + } + } + } +} diff --git a/pcx_examples/targeting/cn0585/cn0585_hdl/ports.json b/pcx_examples/targeting/cn0585/cn0585_hdl/ports.json new file mode 100755 index 0000000..f972fc3 --- /dev/null +++ b/pcx_examples/targeting/cn0585/cn0585_hdl/ports.json @@ -0,0 +1,176 @@ +{ + "cn0585": { + "chip": "CN0585", + "complex": "true", + "fpga": [ + "zed" + ], + "supported_rd": [ + "rx", + "tx", + "rx & tx" + ], + "ports": [ + { + "rx": [ + { + "input": "false", + "width": 1, + "name": "util_ltc2387_adc_pack/fifo_wr_en", + "type": "valid", + "m_name": "IP Data Valid OUT" + }, + { + "input": "false", + "width": 16, + "name": "util_ltc2387_adc_pack/fifo_wr_data_0", + "type": "data", + "m_name": "IP Data 0 OUT" + }, + { + "input": "false", + "width": 16, + "name": "util_ltc2387_adc_pack/fifo_wr_data_1", + "type": "data", + "m_name": "IP Data 1 OUT" + }, + { + "input": "false", + "width": 16, + "name": "util_ltc2387_adc_pack/fifo_wr_data_2", + "type": "data", + "m_name": "IP Data 2 OUT" + }, + { + "input": "false", + "width": 16, + "name": "util_ltc2387_adc_pack/fifo_wr_data_3", + "type": "data", + "m_name": "IP Data 3 OUT" + }, + { + "input": "true", + "width": 1, + "name": "axi_ltc2387_0/adc_valid", + "type": "valid", + "m_name": "IP Valid Rx Data IN" + }, + { + "input": "true", + "width": 16, + "name": "axi_ltc2387_0/adc_data", + "type": "data", + "m_name": "CN0585 ADC Data 0 IN" + }, + { + "input": "true", + "width": 16, + "name": "axi_ltc2387_1/adc_data", + "type": "data", + "m_name": "CN0585 ADC Data 1 IN" + }, + { + "input": "true", + "width": 16, + "name": "axi_ltc2387_2/adc_data", + "type": "data", + "m_name": "CN0585 ADC Data 2 IN" + }, + { + "input": "true", + "width": 16, + "name": "axi_ltc2387_3/adc_data", + "type": "data", + "m_name": "CN0585 ADC Data 3 IN" + } + ], + "tx": [ + { + "input": "true", + "width": 16, + "name": "axi_ltc2387_0/adc_data", + "type": "data", + "m_name": "IP Data 0 IN" + }, + { + "input": "true", + "width": 16, + "name": "axi_ltc2387_1/adc_data", + "type": "data", + "m_name": "IP Data 1 IN" + }, + { + "input": "true", + "width": 16, + "name": "axi_ltc2387_2/adc_data", + "type": "data", + "m_name": "IP Data 2 IN" + }, + { + "input": "true", + "width": 16, + "name": "axi_ltc2387_3/adc_data", + "type": "data", + "m_name": "IP Data 3 IN" + }, + { + "input": "true", + "width": 1, + "name": "axi_ltc2387_0/adc_valid", + "type": "valid", + "m_name": "IP Valid Tx Data IN" + }, + { + "input": "false", + "width": 16, + "name": "axi_ad3552r_0/data_in_a", + "type": "data", + "m_name": "CN0585 DAC Data 0 OUT" + }, + { + "input": "false", + "width": 16, + "name": "axi_ad3552r_0/data_in_b", + "type": "data", + "m_name": "CN0585 DAC Data 1 OUT" + }, + { + "input": "false", + "width": 1, + "name": "axi_ad3552r_0/valid_in_a", + "type": "valid", + "m_name": "IP Load Tx Data OUT" + }, + { + "input": "false", + "width": 16, + "name": "axi_ad3552r_1/data_in_a", + "type": "data", + "m_name": "CN0585 DAC Data 2 OUT" + }, + { + "input": "false", + "width": 16, + "name": "axi_ad3552r_1/data_in_b", + "type": "data", + "m_name": "CN0585 DAC Data 3 OUT" + }, + { + "input": "true", + "width": 8, + "name": "xlslice_1/Dout", + "type": "data", + "m_name": "IP Data 4 IN" + }, + { + "input": "false", + "width": 8, + "name": "xlconcat_1/In1", + "type": "data", + "m_name": "CN0585 DAC Data 4 OUT" + } + ] + } + ] + } +} diff --git a/pcx_examples/targeting/cn0585/cn0585_hdl/system_project_rxtx.tcl b/pcx_examples/targeting/cn0585/cn0585_hdl/system_project_rxtx.tcl new file mode 100644 index 0000000..d180513 --- /dev/null +++ b/pcx_examples/targeting/cn0585/cn0585_hdl/system_project_rxtx.tcl @@ -0,0 +1,35 @@ +set start_dir [pwd] +puts "Starting Precision Toolbox HDL build" + +if {$preprocess == "on"} { + source $preprocess_script +} + +cd projects/$project/$carrier +source ../../scripts/adi_make.tcl +adi_make::lib all + +set ::env(ADI_SKIP_SYNTHESIS) 1 +set ::env(SKIP_SYNTHESIS) 1 +set ::env(ADI_MATLAB) 1 +set ::env(MATLAB) 1 +set ::env(ADI_USE_OOC_SYNTHESYS) 1 +set ::env(ADI_IGNORE_VERSION_CHECK) 1 + +source ./system_project.tcl + +# Update block design to make room for new IP +source ../../scripts/matlab_processors.tcl +preprocess_bd $project $carrier $ref_design + +if {$postprocess == "on"} { + cd $start_dir + source $postprocess_script +} + +regenerate_bd_layout +save_bd_design +validate_bd_design + +# Back to root +cd $start_dir diff --git a/pcx_examples/targeting/cn0585/cn0585_led_sw_gpio_control_demo/testModel_Tx16and8.slx b/pcx_examples/targeting/cn0585/cn0585_led_sw_gpio_control_demo/testModel_Tx16and8.slx new file mode 100644 index 0000000..55d8cf3 Binary files /dev/null and b/pcx_examples/targeting/cn0585/cn0585_led_sw_gpio_control_demo/testModel_Tx16and8.slx differ diff --git a/test/BSPTestsBase.m b/test/BSPTestsBase.m index 09b5c6c..6e4f37f 100644 --- a/test/BSPTestsBase.m +++ b/test/BSPTestsBase.m @@ -66,6 +66,11 @@ function CollectLogs(testCase,cfgb) disp('Found workflow_task_CreateProject... copying'); movefile('workflow_task_CreateProject.log',[rdn,'_CreateProject_',cfgb.mode,'.log']); end + system(join(["find '",testCase.Folder,"' -name 'system_top_timing_summary_routed.rpt' | xargs -I '{}' cp {} ."],'')); + if exist('system_top_timing_summary_routed.rpt','file') + disp('Found system_top_timing_summary_routed... copying'); + movefile('system_top_timing_summary_routed.rpt',[rdn,'_timing_summary_',cfgb.mode,'.rpt']); + end system(join(["find '",testCase.Folder,"' -name 'workflow_task_BuildFPGABitstream.log' | xargs -I '{}' cp {} ."],'')); if exist('workflow_task_BuildFPGABitstream.log','file') disp('Found workflow_task_BuildFPGABitstream... copying'); @@ -109,6 +114,15 @@ function CollectLogs(testCase,cfgb) 'vivado_version',vivado_version,'mode',mode); cfg = [cfg(:)',{cfg1},{cfg2},{cfg3}]; + mode = 'tx_rx'; + h2 = str2func([s,'.',variants{k},'.plugin_rd_txrx']);h2 = h2(); + ReferenceDesignName = h2.ReferenceDesignName; + vivado_version = h2.SupportedToolVersion{:}; + cfg4 = struct('Board',h1,... + 'ReferenceDesignName',ReferenceDesignName,... + 'vivado_version',vivado_version,'mode',mode); + cfg = [cfg(:)',{cfg1},{cfg2},{cfg4}]; + end end @@ -124,7 +138,7 @@ function CollectLogs(testCase,cfgb) assert(0); elseif strcmp(s{2},'adrv9361z7035') || ... strcmp(s{2},'adrv9364z7020') - h = str2func([strjoin(s(1:2),'.'),'.common.plugin_board']); + h = str2func([strjoin(s(1:2),'.'),'.plugin_board']); else h = str2func([strjoin(s(1:end-1),'.'),'.plugin_board']); end @@ -138,10 +152,16 @@ function CollectLogs(testCase,cfgb) end function setVivadoPath(~,vivado) - if ispc - pathname = ['C:\Xilinx\Vivado\',vivado,'\bin\vivado.bat']; - elseif isunix - pathname = ['/opt/Xilinx/Vivado/',vivado,'/bin/vivado']; + CUSTOM_VIVADO_PATH = getenv('CUSTOM_VIVADO_PATH'); + if ~isempty(CUSTOM_VIVADO_PATH) + pathname = CUSTOM_VIVADO_PATH; + fprintf('Using custom Vivado path: %s\n',pathname); + else + if ispc + pathname = ['C:\Xilinx\Vivado\',vivado,'\bin\vivado.bat']; + elseif isunix + pathname = ['/emea/mediadata/opt/Xilinx/Vivado/',vivado,'/bin/vivado']; + end end assert(exist(pathname,'file')>0,'Correct version of Vivado is unavailable or in a non-standard location'); hdlsetuptoolpath('ToolName', 'Xilinx Vivado', ... @@ -183,4 +203,4 @@ function testMain(testCase, configs, SynthesizeDesign) end end end -end +end \ No newline at end of file diff --git a/CI/scripts/adi_build.tcl b/test/adi_build.tcl old mode 100644 new mode 100755 similarity index 93% rename from CI/scripts/adi_build.tcl rename to test/adi_build.tcl index f85bf7c..d4d155a --- a/CI/scripts/adi_build.tcl +++ b/test/adi_build.tcl @@ -25,7 +25,7 @@ set sdk_loc vivado_prj.sdk # Export the hdf file delete -force $sdk_loc file mkdir $sdk_loc -file copy -force vivado_prj.runs/impl_1/system_top.sysdef $sdk_loc/system_top.hdf +write_hw_platform -fixed -force -include_bit -file $sdk_loc/system_top.xsa # Close the Vivado project close_project @@ -52,8 +52,9 @@ if {$fpga_board eq "ZCU102"} { } else { puts "pmufw built correctly!" } - - exec xsdk -batch -source $cdir/projects/scripts/fsbl_build_zynqmp.tcl + + set vversion [version -short] + exec xsdk -batch -source $cdir/projects/scripts/fsbl_build_zynqmp.tcl $vversion if {[file exist boot/BOOT.BIN] eq 0} { puts "ERROR: BOOT.BIN not built" return -code error 11 diff --git a/test/board_variants.m b/test/board_variants.m new file mode 100755 index 0000000..dc6e70c --- /dev/null +++ b/test/board_variants.m @@ -0,0 +1,17 @@ +function r = board_variants +% Board plugin registration file +% 1. Any registration file with this name on MATLAB path will be picked up +% 2. Registration file returns a cell array pointing to the location of +% the board plugins +% 3. Board plugin must be a package folder accessible from MATLAB path, +% and contains a board definition file + +% Copyright 2023 The MathWorks, Inc. + +r = { ... + 'AnalogDevices.cn0585.zed.plugin_rd_rx', ... + 'AnalogDevices.cn0585.zed.plugin_rd_tx', ... + 'AnalogDevices.cn0585.zed.plugin_rd_rxtx', ... + }; +end +% LocalWords: Zynq ZC diff --git a/test/build_design.m b/test/build_design.m new file mode 100755 index 0000000..b14c71b --- /dev/null +++ b/test/build_design.m @@ -0,0 +1,82 @@ + +function out = build_design(config,ReferenceDesignName,vivado_version,mode,board_name,SynthesizeDesign,folder) + +%% Restore the Model to default HDL parameters +%hdlrestoreparams('testModel/HDL_DUT'); + +%% Set port mapping based on design configuration +mdl = setportmapping(mode,ReferenceDesignName,board_name); + +%% Model HDL Parameters + +%% Set Model mdl HDL parameters +hdlset_param(mdl, 'HDLSubsystem', [mdl,'/HDL_DUT']); +hdlset_param(mdl, 'ReferenceDesign', ReferenceDesignName); +hdlset_param(mdl, 'SynthesisTool', config.SupportedTool{:}); +hdlset_param(mdl, 'SynthesisToolChipFamily', config.FPGAFamily); +hdlset_param(mdl, 'SynthesisToolDeviceName', config.FPGADevice); +hdlset_param(mdl, 'SynthesisToolPackageName', config.FPGAPackage); +hdlset_param(mdl, 'SynthesisToolSpeedValue', config.FPGASpeed); +hdlset_param(mdl, 'TargetPlatform', config.BoardName); +hdlset_param(mdl, 'TargetLanguage', 'Verilog'); +hdlset_param(mdl, 'TargetDirectory', [folder,'\hdlsrc']); +hdlset_param(mdl, 'Workflow', 'IP Core Generation'); +hdlset_param([mdl,'/HDL_DUT'], 'ProcessorFPGASynchronization', 'Free running'); + +%% Workflow Configuration Settings +% Construct the Workflow Configuration Object with default settings +hWC = hdlcoder.WorkflowConfig('SynthesisTool','Xilinx Vivado','TargetWorkflow','IP Core Generation'); + +% Specify the top level project directory +hWC.ProjectFolder = folder; +hWC.ReferenceDesignToolVersion = '2023.2'; +hWC.IgnoreToolVersionMismatch = true; +hWC.AllowUnsupportedToolVersion = true; + +% Set Workflow tasks to run +hWC.RunTaskGenerateRTLCodeAndIPCore = true; +hWC.RunTaskCreateProject = true; +hWC.RunTaskGenerateSoftwareInterfaceModel = false; +hWC.RunTaskBuildFPGABitstream = SynthesizeDesign; +hWC.RunTaskProgramTargetDevice = false; + +% Set properties related to 'RunTaskGenerateRTLCodeAndIPCore' Task +hWC.IPCoreRepository = ''; +hWC.GenerateIPCoreReport = false; + +% Set properties related to 'RunTaskCreateProject' Task +hWC.Objective = hdlcoder.Objective.None; +hWC.AdditionalProjectCreationTclFiles = ''; +hWC.EnableIPCaching = false; + +% Set properties related to 'RunTaskGenerateSoftwareInterfaceModel' Task +hWC.OperatingSystem = 'Linux'; + +% Set properties related to 'RunTaskBuildFPGABitstream' Task +hWC.RunExternalBuild = false; +%hWC.TclFileForSynthesisBuild = hdlcoder.BuildOption.Default; +%hWC.CustomBuildTclFile = ''; + +hWC.TclFileForSynthesisBuild = hdlcoder.BuildOption.Custom; +hWC.CustomBuildTclFile = '../hdl/vendor/AnalogDevices/vivado/projects/scripts/adi_build.tcl'; + +% Set properties related to 'RunTaskProgramTargetDevice' Task +%hWC.ProgrammingMethod = hdlcoder.ProgrammingMethod.Download; +%hWC.ProgrammingMethod = hdlcoder.ProgrammingMethod.Custom; + +% Validate the Workflow Configuration Object +hWC.validate; + +%% Run the workflow +try + hdlcoder.runWorkflow([mdl,'/HDL_DUT'], hWC, 'Verbosity', 'on'); + close_system(mdl, false); + bdclose('all'); + out = []; +catch ME + if SynthesizeDesign && exist([folder,'/vivado_ip_prj/boot/BOOT.BIN'],'file') + ME = []; + end + out = ME;%.identifier +end + diff --git a/test/runInstallerTests.m b/test/runInstallerTests.m new file mode 100755 index 0000000..14825fa --- /dev/null +++ b/test/runInstallerTests.m @@ -0,0 +1,48 @@ +function runInstallerTests(board) + +import matlab.unittest.TestRunner; +import matlab.unittest.TestSuite; +import matlab.unittest.plugins.TestReportPlugin; +import matlab.unittest.plugins.XMLPlugin +import matlab.unittest.plugins.DiagnosticsValidationPlugin +import matlab.unittest.parameters.Parameter + +SynthesizeDesign = {false}; +param = Parameter.fromData('SynthesizeDesign',SynthesizeDesign); + +if nargin == 0 + suite = testsuite({'BSPInstallerTests'}); +else + boards = ['*',lower(board),'*']; + suite = TestSuite.fromClass(?BSPInstallerTests,'ExternalParameters',param); + suite = suite.selectIf('ParameterProperty','configs', 'ParameterName',boards); +end + +try + + runner = matlab.unittest.TestRunner.withTextOutput('OutputDetail',1); + runner.addPlugin(DiagnosticsValidationPlugin) + + xmlFile = 'BSPTestResults.xml'; + plugin = XMLPlugin.producingJUnitFormat(xmlFile); + runner.addPlugin(plugin); + + results = runner.run(suite); + + t = table(results); + disp(t); + disp(repmat('#',1,80)); + for test = results + if test.Failed + disp(test.Name); + end + end +catch e + disp(getReport(e,'extended')); + bdclose('all'); + exit(1); +end + +save(['BSPInstallerTest_',datestr(now,'dd_mm_yyyy-HH:MM:SS'),'.mat'],'t'); +bdclose('all'); +exit(any([results.Failed])); diff --git a/test/runSynthTests.m b/test/runSynthTests.m new file mode 100644 index 0000000..e0fdc67 --- /dev/null +++ b/test/runSynthTests.m @@ -0,0 +1,68 @@ +function runSynthTests(board) + +import matlab.unittest.TestRunner; +import matlab.unittest.TestSuite; +import matlab.unittest.plugins.TestReportPlugin; +import matlab.unittest.plugins.XMLPlugin +import matlab.unittest.plugins.ToUniqueFile; +import matlab.unittest.plugins.TAPPlugin; +import matlab.unittest.plugins.DiagnosticsValidationPlugin +import matlab.unittest.parameters.Parameter + +runParallel = false; +SynthesizeDesign = {true}; +param = Parameter.fromData('SynthesizeDesign',SynthesizeDesign); + +if nargin == 0 + suite = testsuite({'BSPTests'}); +else + boards = ['*',lower(board),'*']; + suite = TestSuite.fromClass(?BSPTests,'ExternalParameters',param); + suite = suite.selectIf('ParameterProperty','configs', 'ParameterName',boards); +end + +try + + runner = matlab.unittest.TestRunner.withTextOutput('OutputDetail',4); + runner.addPlugin(DiagnosticsValidationPlugin) + + xmlFile = 'BSPTestResults.xml'; + plugin = XMLPlugin.producingJUnitFormat(xmlFile); + runner.addPlugin(plugin); + + if runParallel + try %#ok + parpool(4); + results = runInParallel(runner,suite); + catch ME + disp(ME); + results = runner.run(suite); + end + else + results = runner.run(suite); + end + + t = table(results); + disp(t); + disp(repmat('#',1,80)); + for test = results + if test.Failed + disp(test.Name); + end + end +catch e + disp(getReport(e,'extended')); + bdclose('all'); + exit(1); +end + +try + poolobj = gcp('nocreate'); + delete(poolobj); +catch ME + disp(ME) +end + +save(['BSPTest_',datestr(now,'dd_mm_yyyy-HH:MM:SS'),'.mat'],'t'); +bdclose('all'); +exit(any([results.Failed])); diff --git a/test/setportmapping.m b/test/setportmapping.m new file mode 100644 index 0000000..295644e --- /dev/null +++ b/test/setportmapping.m @@ -0,0 +1,106 @@ +function mdl = setportmapping(mode,ReferenceDesignName,board_name) + +% ! this script will work with test models that have 16 data ports and 4 +% boolean ports + +if contains(lower(ReferenceDesignName),'cn0585') + dev = 'CN0585'; + mdl = 'testModel'; + portWidthRX = 16; + portWidthTX = 16; +else + error('Unknown device'); +end + +load_system(mdl); + +% First set all ports to NIS +for k=1:16 + hdlset_param([mdl,'/HDL_DUT/in',num2str(k)], 'IOInterface', 'No Interface Specified'); + hdlset_param([mdl,'/HDL_DUT/in',num2str(k)], 'IOInterfaceMapping', ''); + hdlset_param([mdl,'/HDL_DUT/out',num2str(k)], 'IOInterface', 'No Interface Specified'); + hdlset_param([mdl,'/HDL_DUT/out',num2str(k)], 'IOInterfaceMapping', ''); +end + +for k = 1:4 + hdlset_param([mdl,'/HDL_DUT/validIn',num2str(k)], 'IOInterface', 'No Interface Specified'); + hdlset_param([mdl,'/HDL_DUT/validIn',num2str(k)], 'IOInterfaceMapping', ''); + hdlset_param([mdl,'/HDL_DUT/validOut',num2str(k)], 'IOInterface', 'No Interface Specified'); + hdlset_param([mdl,'/HDL_DUT/validOut',num2str(k)], 'IOInterfaceMapping', ''); +end + + +filePath = '../CI/ports.json'; +str = fileread(filePath); +val = jsondecode(str); + +fn = fieldnames(val); + +for k = 1:numel(fn) + x = val.(fn{k}); + if (strcmp(x.chip, dev)) + inIndex = 1; + outIndex = 1; + validInIndex = 1; + validOutIndex = 1; + if (mode == "rx") || (mode == "rxtx") + rx = x.ports.rx; + for indexRx = 1:numel(rx) + element = rx(indexRx); + if(element.type == "data") + if(element.input == "true") + hdlset_param([mdl,'/HDL_DUT/in',num2str(inIndex)], 'IOInterface', [element.m_name,' [0:',num2str(portWidthRX-1),']']); + hdlset_param([mdl,'/HDL_DUT/in',num2str(inIndex)], 'IOInterfaceMapping', ['[0:',num2str(portWidthRX-1),']']); + inIndex = inIndex + 1; + else + hdlset_param([mdl,'/HDL_DUT/out',num2str(outIndex)], 'IOInterface', [element.m_name,' [0:',num2str(portWidthRX-1),']']); + hdlset_param([mdl,'/HDL_DUT/out',num2str(outIndex)], 'IOInterfaceMapping', ['[0:',num2str(portWidthRX-1),']']); + outIndex = outIndex + 1; + end + elseif (element.type == "valid") + if(element.input == "true") + hdlset_param([mdl,'/HDL_DUT/validIn',num2str(validInIndex)], 'IOInterface', element.m_name); + hdlset_param([mdl,'/HDL_DUT/validIn',num2str(validInIndex)], 'IOInterfaceMapping', '[0]'); + validInIndex = validInIndex + 1; + else + hdlset_param([mdl,'/HDL_DUT/validOut',num2str(validOutIndex)], 'IOInterface', element.m_name); + hdlset_param([mdl,'/HDL_DUT/validOut',num2str(validOutIndex)], 'IOInterfaceMapping', '[0]'); + validOutIndex = validOutIndex + 1; + end + end + end + + end + if (mode == "tx") || (mode == "rxtx") + tx = x.ports.tx; + if (mode == "tx") + inIndex = 1; + outIndex = 1; + end + for indexTx = 1:numel(tx) + element = tx(indexTx); + if(element.type == "data") + if(element.input == "true") + hdlset_param([mdl,'/HDL_DUT/in',num2str(inIndex)], 'IOInterface', [element.m_name,' [0:',num2str(portWidthTX-1),']']); + hdlset_param([mdl,'/HDL_DUT/in',num2str(inIndex)], 'IOInterfaceMapping', ['[0:',num2str(portWidthTX-1),']']); + inIndex = inIndex + 1; + else + hdlset_param([mdl,'/HDL_DUT/out',num2str(outIndex)], 'IOInterface', [element.m_name,' [0:',num2str(portWidthTX-1),']']); + hdlset_param([mdl,'/HDL_DUT/out',num2str(outIndex)], 'IOInterfaceMapping', ['[0:',num2str(portWidthTX-1),']']); + outIndex = outIndex + 1; + end + elseif (element.type == "valid") + if(element.input == "true") + hdlset_param([mdl,'/HDL_DUT/validIn',num2str(validInIndex)], 'IOInterface', element.m_name); + hdlset_param([mdl,'/HDL_DUT/validIn',num2str(validInIndex)], 'IOInterfaceMapping', '[0]'); + validInIndex = validInIndex + 1; + else + hdlset_param([mdl,'/HDL_DUT/validOut',num2str(validOutIndex)], 'IOInterface', element.m_name); + hdlset_param([mdl,'/HDL_DUT/validOut',num2str(validOutIndex)], 'IOInterfaceMapping', '[0]'); + validOutIndex = validOutIndex + 1; + end + end + end + end + end +end diff --git a/test/testModel.slx b/test/testModel.slx new file mode 100755 index 0000000..7021254 Binary files /dev/null and b/test/testModel.slx differ