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Copy pathLadnerFischer_allbuffered_b.jsim
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LadnerFischer_allbuffered_b.jsim
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.include "50002/nominal.jsim"
.include "50002/stdcell.jsim"
.include "50002/2dcheckoff_3ns.jsim"
* Definition of a black cell
.subckt bc pik gik pkj gkj pij gij
Xinv_gik gik i_gik inverter
Xnand1 pik gkj pg_kj nand2
Xnand2 i_gik pg_kj gij nand2
*2 pij circuits try.
*Xand1 pkj pik pij and2
Xnand_p pkj pik i_pij nand2
Xinv_p i_pij pij inverter
.ends
* Definition of a grey cell
.subckt gc pik gik gkj gij
Xinv_gik gik i_gik inverter
Xnand1 pik gkj pg_kj nand2
Xnand2 i_gik pg_kj gij nand2
.ends
* Definition of a white cell(generates P and G)
.subckt wc i j p g
XgenG i j g and2
XgenP i j p xor2
.ends
* Definition of adder32
.subckt adder32 opi0 a[31:0] b[31:0] s[31:0] z v n
XinvB b[31:0] ib[31:0] inverter_2
Xbuff opi0 op0 buffer_8
XselB op0#32 b[31:0] ib[31:0] xb[31:0] mux2
* generate p and g signals for bit 31:1
Xpandg a[31:1] xb[31:1] p[31:1] g[31:1] wc
* prepare the 2's complement of B by adding in the op0 as carry
Xpng0 a[0] xb[0] p[0] g0pre wc
Xprep p[0] g0pre op0 g[0] gc
* row 1
Xr1c1 p1 g1 p0 g0 r1p1pre r1g1pre bc
Xr1c3 p3 g3 p2 g2 r1p3 r1g3 bc
Xr1c5 p5 g5 p4 g4 r1p5pre r1g5pre bc
Xr1c7 p7 g7 p6 g6 r1p7 r1g7 bc
Xr1c9 p9 g9 p8 g8 r1p9pre r1g9pre bc
Xr1c11 p11 g11 p10 g10 r1p11 r1g11 bc
Xr1c13 p13 g13 p12 g12 r1p13pre r1g13pre bc
Xr1c15 p15 g15 p14 g14 r1p15 r1g15 bc
Xr1c17 p17 g17 p16 g16 r1p17pre r1g17pre bc
Xr1c19 p19 g19 p18 g18 r1p19 r1g19 bc
Xr1c21 p21 g21 p20 g20 r1p21pre r1g21pre bc
Xr1c23 p23 g23 p22 g22 r1p23 r1g23 bc
Xr1c25 p25 g25 p24 g24 r1p25pre r1g25pre bc
Xr1c27 p27 g27 p26 g26 r1p27 r1g27 bc
Xr1c29 p29 g29 p28 g28 r1p29pre r1g29pre bc
Xr1c31 p31 g31 p30 g30 r1p31 r1g31 bc
Xbuff12ap r1p1pre r1p1 buffer
Xbuff12ag r1g1pre r1g1 buffer
Xbuff12bp r1p5pre r1p5 buffer
Xbuff12bg r1g5pre r1g5 buffer
Xbuff12cp r1p9pre r1p9 buffer
Xbuff12cg r1g9pre r1g9 buffer
Xbuff12dp r1p13pre r1p13 buffer
Xbuff12dg r1g13pre r1g13 buffer
Xbuff12ep r1p17pre r1p17 buffer
Xbuff12eg r1g17pre r1g17 buffer
Xbuff12fp r1p21pre r1p21 buffer
Xbuff12fg r1g21pre r1g21 buffer
Xbuff12gp r1p25pre r1p25 buffer
Xbuff12gg r1g25pre r1g25 buffer
Xbuff12hp r1p29pre r1p29 buffer
Xbuff12hg r1g29pre r1g29 buffer
* row 2
Xr2c2 p2 g2 r1p1 r1g1 r2p2 r2g2 bc
Xr2c3 r1p3 r1g3 r1p1 r1g1 r2p3pre r2g3pre bc
Xr2c6 p6 g6 r1p5 r1g5 r2p6 r2g6 bc
Xr2c7 r1p7 r1g7 r1p5 r1g5 r2p7 r2g7 bc
Xr2c10 p10 g10 r1p9 r1g9 r2p10 r2g10 bc
Xr2c11 r1p11 r1g11 r1p9 r1g9 r2p11pre r2g11pre bc
Xr2c14 p14 g14 r1p13 r1g13 r2p14 r2g14 bc
Xr2c15 r1p15 r1g15 r1p13 r1g13 r2p15 r2g15 bc
Xr2c18 p18 g18 r1p17 r1g17 r2p18 r2g18 bc
Xr2c19 r1p19 r1g19 r1p17 r1g17 r2p19pre r2g19pre bc
Xr2c22 p22 g22 r1p21 r1g21 r2p22 r2g22 bc
Xr2c23 r1p23 r1g23 r1p21 r1g21 r2p23 r2g23 bc
Xr2c26 p26 g26 r1p25 r1g25 r2p26 r2g26 bc
Xr2c27 r1p27 r1g27 r1p25 r1g25 r2p27pre r2g27pre bc
Xr2c30 p30 g30 r1p29 r1g29 r2p30 r2g30 bc
Xr2c31 r1p31 r1g31 r1p29 r1g29 r2p31 r2g31 bc
Xbuff23ap r2p3pre r2p3 buffer
Xbuff23ag r2g3pre r2g3 buffer
Xbuff23bp r2p11pre r2p11 buffer
Xbuff23bg r2g11pre r2g11 buffer
Xbuff23cp r2p19pre r2p19 buffer
Xbuff23cg r2g19pre r2g19 buffer
Xbuff23dp r2p27pre r2p27 buffer
Xbuff23dg r2g27pre r2g27 buffer
* row 3
Xr3c4 p4 g4 r2p3 r2g3 r3p4 r3g4 bc
Xr3c5 r1p5 r1g5 r2p3 r2g3 r3p5 r3g5 bc
Xr3c6 r2p6 r2g6 r2p3 r2g3 r3p6 r3g6 bc
Xr3c7 r2p7 r2g7 r2p3 r2g3 r3p7pre r3g7pre bc
Xr3c12 p12 g12 r2p11 r2g11 r3p12 r3g12 bc
Xr3c13 r1p13 r1g13 r2p11 r2g11 r3p13 r3g13 bc
Xr3c14 r2p14 r2g14 r2p11 r2g11 r3p14 r3g14 bc
Xr3c15 r2p15 r2g15 r2p11 r2g11 r3p15 r3g15 bc
Xr3c20 p20 g20 r2p19 r2g19 r3p20 r3g20 bc
Xr3c21 r1p21 r1g21 r2p19 r2g19 r3p21 r3g21 bc
Xr3c22 r2p22 r2g22 r2p19 r2g19 r3p22 r3g22 bc
Xr3c23 r2p23 r2g23 r2p19 r2g19 r3p23pre r3g23pre bc
Xr3c28 p28 g28 r2p27 r2g27 r3p28 r3g28 bc
Xr3c29 r1p29 r1g29 r2p27 r2g27 r3p29 r3g29 bc
Xr3c30 r2p30 r2g30 r2p27 r2g27 r3p30 r3g30 bc
Xr3c31 r2p31 r2g31 r2p27 r2g27 r3p31 r3g31 bc
Xbuff34ap r3p7pre r3p7 buffer
Xbuff34ag r3g7pre r3g7 buffer
Xbuff34bp r3p23pre r3p23 buffer
Xbuff34bg r3g23pre r3g23 buffer
* row 4
Xr4c8 p8 g8 r3p7 r3g7 r4p8 r4g8 bc
Xr4c9 r1p9 r1g9 r3p7 r3g7 r4p9 r4g9 bc
Xr4c10 r2p10 r2g10 r3p7 r3g7 r4p10 r4g10 bc
Xr4c11 r2p11 r2g11 r3p7 r3g7 r4p11 r4g11 bc
Xr4c12 r3p12 r3g12 r3p7 r3g7 r4p12 r4g12 bc
Xr4c13 r3p13 r3g13 r3p7 r3g7 r4p13 r4g13 bc
Xr4c14 r3p14 r3g14 r3p7 r3g7 r4p14 r4g14 bc
Xr4c15 r3p15 r3g15 r3p7 r3g7 r4p15 r4g15pre bc
Xr4c24 p24 g24 r3p23 r3g23 r4p24 r4g24 bc
Xr4c25 r1p25 r1g25 r3p23 r3g23 r4p25 r4g25 bc
Xr4c26 r2p26 r2g26 r3p23 r3g23 r4p26 r4g26 bc
Xr4c27 r2p27 r2g27 r3p23 r3g23 r4p27 r4g27 bc
Xr4c28 r3p28 r3g28 r3p23 r3g23 r4p28 r4g28 bc
Xr4c29 r3p29 r3g29 r3p23 r3g23 r4p29 r4g29 bc
Xr4c30 r3p30 r3g30 r3p23 r3g23 r4p30 r4g30 bc
Xr4c31 r3p31 r3g31 r3p23 r3g23 r4p31 r4g31 bc
Xbuff45 r4g15pre r4g15 buffer
* row 5
Xr5c16 p16 g16 r4g15 r5g16 gc
Xr5c17 r1p17 r1g17 r4g15 r5g17 gc
Xr5c18 r2p18 r2g18 r4g15 r5g18 gc
Xr5c19 r2p19 r2g19 r4g15 r5g19 gc
Xr5c20 r3p20 r3g20 r4g15 r5g20 gc
Xr5c21 r3p21 r3g21 r4g15 r5g21 gc
Xr5c22 r3p22 r3g22 r4g15 r5g22 gc
Xr5c23 r3p23 r3g23 r4g15 r5g23 gc
Xr5c24 r4p24 r4g24 r4g15 r5g24 gc
Xr5c25 r4p25 r4g25 r4g15 r5g25 gc
Xr5c26 r4p26 r4g26 r4g15 r5g26 gc
Xr5c27 r4p27 r4g27 r4g15 r5g27 gc
Xr5c28 r4p28 r4g28 r4g15 r5g28 gc
Xr5c29 r4p29 r4g29 r4g15 r5g29 gc
Xr5c30 r4p30 r4g30 r4g15 r5g30 gc
Xsum0 p0 op0 s0 xor2
Xsum1 p1 g0 s1 xor2
Xsum2 p2 r1g1 s2 xor2
Xsum3 p3 r2g2 s3 xor2
Xsum4 p4 r2g3 s4 xor2
Xsum5 p5 r3g4 s5 xor2
Xsum6 p6 r3g5 s6 xor2
Xsum7 p7 r3g6 s7 xor2
Xsum8 p8 r3g7 s8 xor2
Xsum9 p9 r4g8 s9 xor2
Xsum10 p10 r4g9 s10 xor2
Xsum11 p11 r4g10 s11 xor2
Xsum12 p12 r4g11 s12 xor2
Xsum13 p13 r4g12 s13 xor2
Xsum14 p14 r4g13 s14 xor2
Xsum15 p15 r4g14 s15 xor2
Xsum16 p16 r4g15 s16 xor2
Xsum17 p17 r5g16 s17 xor2
Xsum18 p18 r5g17 s18 xor2
Xsum19 p19 r5g18 s19 xor2
Xsum20 p20 r5g19 s20 xor2
Xsum21 p21 r5g20 s21 xor2
Xsum22 p22 r5g21 s22 xor2
Xsum23 p23 r5g22 s23 xor2
Xsum24 p24 r5g23 s24 xor2
Xsum25 p25 r5g24 s25 xor2
Xsum26 p26 r5g25 s26 xor2
Xsum27 p27 r5g26 s27 xor2
Xsum28 p28 r5g27 s28 xor2
Xsum29 p29 r5g28 s29 xor2
Xsum30 p30 r5g29 s30 xor2
Xsum31 p31 r5g30 s31 xor2
* generate z
XZorCascade s[7:0] s[15:8] s[23:16] s[31:24] w[7:0] nor4
X4AndCascade w[7:6] w[5:4] w[3:2] w[1:0] int[1:0] nand4
XFinalZ int1 int0 z nor2
//Nor nand nor
* generate v
XnotS31 s31 ns31 inverter
XnotA31 a31 na31 inverter
XnotXB31 xb31 nxb31 inverter
XVckt1 a31 xb31 ns31 vp1 nand3
XVckt2 na31 nxb31 s31 vp2 nand3
XVckt vp1 vp2 v nand2
* generate n
.connect s31 n
.ends