diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index 5bbbb278906..7e51b6cb1dd 100644
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -23,6 +23,7 @@
 #include "kernel/celltypes.h"
 #include "passes/techmap/libparse.h"
 #include "kernel/cost.h"
+#include "kernel/gzip.h"
 #include "libs/json11/json11.hpp"
 
 USING_YOSYS_NAMESPACE
@@ -347,13 +348,12 @@ statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTL
 
 void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string liberty_file)
 {
-	std::ifstream f;
-	f.open(liberty_file.c_str());
+	std::istream* f = uncompressed(liberty_file.c_str());
 	yosys_input_files.insert(liberty_file);
-	if (f.fail())
+	if (f->fail())
 		log_cmd_error("Can't open liberty file `%s': %s\n", liberty_file.c_str(), strerror(errno));
-	LibertyParser libparser(f);
-	f.close();
+	LibertyParser libparser(*f);
+	delete f;
 
 	for (auto cell : libparser.ast->children)
 	{
diff --git a/tests/various/stat.ys b/tests/various/stat.ys
new file mode 100644
index 00000000000..ad96fe8d41d
--- /dev/null
+++ b/tests/various/stat.ys
@@ -0,0 +1,14 @@
+read_rtlil << EOF
+module \top
+  wire input 1 \A
+  wire output 2 \Y
+  cell \sg13g2_and2_1 \sub
+    connect \A \A
+    connect \B 1'0
+    connect \Y \Y
+  end
+end
+EOF
+logger -expect log "Chip area for module '\\top': 9.072000" 1
+logger -expect-no-warnings
+stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz