From b00abe4a26ca24d22c822e5400e2f3aede93df48 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Wed, 10 Apr 2024 11:45:12 +0200
Subject: [PATCH 001/499] Extend `log` command with `-push`, `-pop`, `-header`
 options

---
 passes/cmds/logcmd.cc | 38 +++++++++++++++++++++++++++++++++-----
 1 file changed, 33 insertions(+), 5 deletions(-)

diff --git a/passes/cmds/logcmd.cc b/passes/cmds/logcmd.cc
index 20cbd894345..8e51af4b3b7 100644
--- a/passes/cmds/logcmd.cc
+++ b/passes/cmds/logcmd.cc
@@ -31,7 +31,8 @@ struct LogPass : public Pass {
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    log string\n");
+		log("    log [options] string\n");
+		log("    log [ -push | -pop ]\n");
 		log("\n");
 		log("Print the given string to the screen and/or the log file. This is useful for TCL\n");
 		log("scripts, because the TCL command \"puts\" only goes to stdout but not to\n");
@@ -52,14 +53,26 @@ struct LogPass : public Pass {
 		log("    -n\n");
 		log("        do not append a newline\n");
 		log("\n");
+		log("    -header\n");
+		log("        log a pass header\n");
+		log("\n");
+		log("    -push\n");
+		log("        push a new level on the pass counter\n");
+		log("\n");
+		log("    -push\n");
+		log("        pop from the pass counter\n");
+		log("\n");
 	}
-	void execute(std::vector<std::string> args, RTLIL::Design*) override
+	void execute(std::vector<std::string> args, RTLIL::Design* design) override
 	{
 		size_t argidx;
 		bool to_stdout = false;
 		bool to_stderr = false;
 		bool to_log    = true;
 		bool newline   = true;
+		bool header    = false;
+		bool push      = false;
+		bool pop       = false;
 		std::string text;
 
 		for (argidx = 1; argidx < args.size(); argidx++)
@@ -68,15 +81,30 @@ struct LogPass : public Pass {
 			else if (args[argidx] == "-stderr") to_stderr = true;
 			else if (args[argidx] == "-nolog")  to_log    = false;
 			else if (args[argidx] == "-n")      newline   = false;
+			else if (args[argidx] == "-header") header    = true;
+			else if (args[argidx] == "-push")   push      = true;
+			else if (args[argidx] == "-pop")    pop       = true;
 			else break;
 		}
+
+		if ((push || pop) && args.size() != 2)
+			log_cmd_error("Bad usage: 'log -push' or 'log -pop' must be used without other arguments.\n");
+
+		if (push) { log_push(); return; }
+		if (pop)  { log_pop(); return; }
+
 		for (; argidx < args.size(); argidx++)
 			text += args[argidx] + ' ';
 		if (!text.empty()) text.resize(text.size()-1);
 
-		if (to_stdout) fprintf(stdout, (newline ? "%s\n" : "%s"), text.c_str());
-		if (to_stderr) fprintf(stderr, (newline ? "%s\n" : "%s"), text.c_str());
-		if (to_log)    log    (        (newline ? "%s\n" : "%s"), text.c_str());
+		const char *fmtline = newline ? "%s\n" : "%s";
+
+		if (to_stdout) fprintf(stdout, fmtline, text.c_str());
+		if (to_stderr) fprintf(stderr, fmtline, text.c_str());
+		if (to_log) {
+			if (!header) log(fmtline, text.c_str());
+			else log_header(design, fmtline, text.c_str());
+		}
 	}
 } LogPass;
 

From f2ebc3f7b14e1847798fecdf1c12cd3311cb214e Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 25 Apr 2024 09:39:23 +1200
Subject: [PATCH 002/499] github: Add template for documentation issues

---
 .github/ISSUE_TEMPLATE/docs_report.yml | 55 ++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 .github/ISSUE_TEMPLATE/docs_report.yml

diff --git a/.github/ISSUE_TEMPLATE/docs_report.yml b/.github/ISSUE_TEMPLATE/docs_report.yml
new file mode 100644
index 00000000000..aa65c63b9c9
--- /dev/null
+++ b/.github/ISSUE_TEMPLATE/docs_report.yml
@@ -0,0 +1,55 @@
+name: Documentation Report
+description: Report a problem with the Yosys documentation
+labels: ["pending-verification"]
+body:
+  - type: markdown
+    attributes:
+      value: >
+
+        If you have a general question, please ask it in the [Discussions](https://github.com/YosysHQ/yosys/discussions) area
+        or join our [IRC Channel](https://web.libera.chat/#yosys) or [Community Slack](https://join.slack.com/t/yosyshq/shared_invite/zt-1aopkns2q-EiQ97BeQDt_pwvE41sGSuA).
+
+
+        If you have found a bug in Yosys, or in building the documentation,
+        please fill out the Bug Report issue form, this form is for problems
+        with the live documentation on [Read the
+        Docs](https://yosyshq.readthedocs.io/projects/yosys/).  Please only
+        report problems that appear on the latest version of the documentation.
+
+
+        Please contact [YosysHQ GmbH](https://www.yosyshq.com/) if you need
+        commercial support for Yosys.
+
+  - type: input
+    id: docs_url
+    attributes:
+      label: Link to page
+      description: "Please provide a link to the page where the problem was found."
+      placeholder: "e.g. https://yosyshq.readthedocs.io/projects/yosys/"
+    validations:
+      required: true
+
+  - type: input
+    id: build_number
+    attributes:
+      label: Build number
+      description: "If possible, please provide the latest build number from https://readthedocs.org/projects/yosys/builds/."
+      placeholder: "e.g. Build #24078236"
+    validations:
+      required: false
+
+  - type: textarea
+    id: problem
+    attributes:
+      label: Issue
+      description: "Please describe what is incorrect, invalid, or missing."
+    validations:
+      required: true
+
+  - type: textarea
+    id: expected
+    attributes:
+      label: Expected
+      description: "If applicable, please describe what should appear instead."
+    validations:
+      required: false

From 374cd3966d65cf8dda4cdfd2563462211ab3216f Mon Sep 17 00:00:00 2001
From: Jason Wu <wjq_ecust@163.com>
Date: Mon, 29 Apr 2024 10:04:34 +0800
Subject: [PATCH 003/499] export define marco to qtcreator.config

---
 Makefile | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index 22fe373a68a..d77cacd54c6 100644
--- a/Makefile
+++ b/Makefile
@@ -92,7 +92,7 @@ YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST)))
 VPATH := $(YOSYS_SRC)
 
 CXXSTD ?= c++11
-CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include
+CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include 
 LIBS := $(LIBS) -lstdc++ -lm
 PLUGIN_LINKFLAGS :=
 PLUGIN_LIBS :=
@@ -1045,11 +1045,12 @@ coverage:
 	genhtml coverage.info --output-directory coverage_html
 
 qtcreator:
+	echo "$(CXXFLAGS)" | grep -o '\-D[^ ]*' | tr ' ' '\n' | sed 's/-D/#define /' | sed 's/=/ /'> qtcreator.config
 	{ for file in $(basename $(OBJS)); do \
 		for prefix in cc y l; do if [ -f $${file}.$${prefix} ]; then echo $$file.$${prefix}; fi; done \
 	done; find backends frontends kernel libs passes -type f \( -name '*.h' -o -name '*.hh' \); } > qtcreator.files
 	{ echo .; find backends frontends kernel libs passes -type f \( -name '*.h' -o -name '*.hh' \) -printf '%h\n' | sort -u; } > qtcreator.includes
-	touch qtcreator.config qtcreator.creator
+	touch qtcreator.creator
 
 vcxsrc: $(GENFILES) $(EXTRA_TARGETS)
 	rm -rf yosys-win32-vcxsrc-$(YOSYS_VER){,.zip}

From f1672b2f14cbf4aac89bd2e922bbd6919f808c6d Mon Sep 17 00:00:00 2001
From: Jason Wu <41063703+offline3@users.noreply.github.com>
Date: Mon, 29 Apr 2024 10:16:22 +0800
Subject: [PATCH 004/499] Update Makefile

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index d77cacd54c6..296d66d0dad 100644
--- a/Makefile
+++ b/Makefile
@@ -92,7 +92,7 @@ YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST)))
 VPATH := $(YOSYS_SRC)
 
 CXXSTD ?= c++11
-CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include 
+CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include
 LIBS := $(LIBS) -lstdc++ -lm
 PLUGIN_LINKFLAGS :=
 PLUGIN_LIBS :=

From 8cc9aa7fc6a4d9008e68a4e146358a191cb854c4 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Fri, 3 May 2024 11:16:34 +0100
Subject: [PATCH 005/499] intel_alm: drop quartus support

---
 techlibs/intel_alm/Makefile.inc            |   3 -
 techlibs/intel_alm/common/alm_sim.v        | 414 +--------------------
 techlibs/intel_alm/common/bram_m20k.txt    |  33 --
 techlibs/intel_alm/common/bram_m20k_map.v  |  31 --
 techlibs/intel_alm/common/dff_sim.v        |  32 --
 techlibs/intel_alm/common/mem_sim.v        |  56 +--
 techlibs/intel_alm/common/quartus_rename.v | 311 ----------------
 techlibs/intel_alm/synth_intel_alm.cc      |  81 +---
 tests/arch/intel_alm/add_sub.ys            |   9 -
 tests/arch/intel_alm/adffs.ys              |  46 ---
 tests/arch/intel_alm/blockram.ys           |   1 +
 tests/arch/intel_alm/counter.ys            |  14 -
 tests/arch/intel_alm/dffs.ys               |  22 --
 tests/arch/intel_alm/fsm.ys                |  22 --
 tests/arch/intel_alm/logic.ys              |  13 -
 tests/arch/intel_alm/lutram.ys             |   1 +
 tests/arch/intel_alm/mul.ys                |  25 --
 tests/arch/intel_alm/mux.ys                |  43 ---
 tests/arch/intel_alm/quartus_ice.ys        |  26 --
 tests/arch/intel_alm/shifter.ys            |  11 -
 tests/arch/intel_alm/tribuf.ys             |  14 -
 21 files changed, 18 insertions(+), 1190 deletions(-)
 delete mode 100644 techlibs/intel_alm/common/bram_m20k.txt
 delete mode 100644 techlibs/intel_alm/common/bram_m20k_map.v
 delete mode 100644 techlibs/intel_alm/common/quartus_rename.v
 delete mode 100644 tests/arch/intel_alm/quartus_ice.ys

diff --git a/techlibs/intel_alm/Makefile.inc b/techlibs/intel_alm/Makefile.inc
index b5f279a921c..9e24d695e85 100644
--- a/techlibs/intel_alm/Makefile.inc
+++ b/techlibs/intel_alm/Makefile.inc
@@ -20,10 +20,7 @@ $(eval $(call add_share_file,share/intel_alm/cyclonev,techlibs/intel_alm/cyclone
 # RAM
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k.txt))
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k_map.v))
-$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m20k.txt))
-$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m20k_map.v))
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab.txt))
 
 # Miscellaneous
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/megafunction_bb.v))
-$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/quartus_rename.v))
diff --git a/techlibs/intel_alm/common/alm_sim.v b/techlibs/intel_alm/common/alm_sim.v
index d3bd673903f..858e43c76cc 100644
--- a/techlibs/intel_alm/common/alm_sim.v
+++ b/techlibs/intel_alm/common/alm_sim.v
@@ -1,4 +1,4 @@
-// The core logic primitive of the Cyclone V/10GX is the Adaptive Logic Module
+// The core logic primitive of the Cyclone V is the Adaptive Logic Module
 // (ALM). Each ALM is made up of an 8-input, 2-output look-up table, covered
 // in this file, connected to combinational outputs, a carry chain, and four
 // D flip-flops (which are covered as MISTRAL_FF in dff_sim.v).
@@ -77,14 +77,6 @@
 //   SUMOUT  368 1342 1323  887 927   -  785   -
 // CARRYOUT   71 1082 1062  866 813   - 1198   -
 
-// Arria V LUT output timings (picoseconds):
-//
-//          CARRY   A    B    C   D   E    F   G
-//  COMBOUT    -  387  375  316 317   -   76 319 (LUT6)
-//  COMBOUT    -  387  375  316 317 218   76 319 (LUT7)
-//   SUMOUT  249  744  732  562 576   -  511   -
-// CARRYOUT   19  629  623  530 514   -  696   -
-
 (* abc9_lut=2, lib_whitebox *)
 module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
 
@@ -100,26 +92,6 @@ specify
     (F => Q) = 97;
 endspecify
 `endif
-`ifdef arriav
-specify
-    (A => Q) = 387;
-    (B => Q) = 375;
-    (C => Q) = 316;
-    (D => Q) = 317;
-    (E => Q) = 319;
-    (F => Q) = 76;
-endspecify
-`endif
-`ifdef cyclone10gx
-specify
-    (A => Q) = 275;
-    (B => Q) = 272;
-    (C => Q) = 175;
-    (D => Q) = 165;
-    (E => Q) = 162;
-    (F => Q) = 53;
-endspecify
-`endif
 
 assign Q = LUT >> {F, E, D, C, B, A};
 
@@ -140,24 +112,6 @@ specify
     (E => Q) = 97;
 endspecify
 `endif
-`ifdef arriav
-specify
-    (A => Q) = 375;
-    (B => Q) = 316;
-    (C => Q) = 317;
-    (D => Q) = 319;
-    (E => Q) = 76;
-endspecify
-`endif
-`ifdef cyclone10gx
-specify
-    (A => Q) = 272;
-    (B => Q) = 175;
-    (C => Q) = 165;
-    (D => Q) = 162;
-    (E => Q) = 53;
-endspecify
-`endif
 
 assign Q = LUT >> {E, D, C, B, A};
 
@@ -177,22 +131,6 @@ specify
     (D => Q) = 97;
 endspecify
 `endif
-`ifdef arriav
-specify
-    (A => Q) = 316;
-    (B => Q) = 317;
-    (C => Q) = 319;
-    (D => Q) = 76;
-endspecify
-`endif
-`ifdef cyclone10gx
-specify
-    (A => Q) = 175;
-    (B => Q) = 165;
-    (C => Q) = 162;
-    (D => Q) = 53;
-endspecify
-`endif
 
 assign Q = LUT >> {D, C, B, A};
 
@@ -211,20 +149,6 @@ specify
     (C => Q) = 97;
 endspecify
 `endif
-`ifdef arriav
-specify
-    (A => Q) = 316;
-    (B => Q) = 317;
-    (C => Q) = 76;
-endspecify
-`endif
-`ifdef cyclone10gx
-specify
-    (A => Q) = 165;
-    (B => Q) = 162;
-    (C => Q) = 53;
-endspecify
-`endif
 
 assign Q = LUT >> {C, B, A};
 
@@ -242,18 +166,6 @@ specify
     (B => Q) = 97;
 endspecify
 `endif
-`ifdef arriav
-specify
-    (A => Q) = 316;
-    (B => Q) = 76;
-endspecify
-`endif
-`ifdef cyclone10gx
-specify
-    (A => Q) = 162;
-    (B => Q) = 53;
-endspecify
-`endif
 
 assign Q = LUT >> {B, A};
 
@@ -268,16 +180,6 @@ specify
     (A => Q) = 97;
 endspecify
 `endif
-`ifdef arriav
-specify
-    (A => Q) = 76;
-endspecify
-`endif
-`ifdef cyclone10gx
-specify
-    (A => Q) = 53;
-endspecify
-`endif
 
 assign Q = ~A;
 
@@ -306,40 +208,6 @@ specify
     (CI => CO) = 36; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM)
 endspecify
 `endif
-`ifdef arriav
-specify
-    (A  => SO) = 744;
-    (B  => SO) = 732;
-    (C  => SO) = 562;
-    (D0 => SO) = 576;
-    (D1 => SO) = 511;
-    (CI => SO) = 249;
-
-    (A  => CO) = 629;
-    (B  => CO) = 623;
-    (C  => CO) = 530;
-    (D0 => CO) = 514;
-    (D1 => CO) = 696;
-    (CI => CO) = 10; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM)
-endspecify
-`endif
-`ifdef cyclone10gx
-specify
-    (A  => SO) = 644;
-    (B  => SO) = 477;
-    (C  => SO) = 416;
-    (D0 => SO) = 380;
-    (D1 => SO) = 431;
-    (CI => SO) = 276;
-
-    (A  => CO) = 525;
-    (B  => CO) = 433;
-    (C  => CO) = 712;
-    (D0 => CO) = 653;
-    (D1 => CO) = 593;
-    (CI => CO) = 16;
-endspecify
-`endif
 
 wire q0, q1;
 
@@ -349,283 +217,3 @@ assign q1 = LUT1 >> {D1, C, B, A};
 assign {CO, SO} = q0 + !q1 + CI;
 
 endmodule
-
-
-/*
-// A, B, C0, C1, E0, E1, F0, F1: data inputs
-// CARRYIN: carry input
-// SHAREIN: shared-arithmetic input
-// CLK0, CLK1, CLK2: clock inputs
-//
-// COMB0, COMB1: combinational outputs
-// FF0, FF1, FF2, FF3: DFF outputs
-// SUM0, SUM1: adder outputs
-// CARRYOUT: carry output
-// SHAREOUT: shared-arithmetic output
-module MISTRAL_ALM(
-    input A, B, C0, C1, E0, E1, F0, F1, CARRYIN, SHAREIN, // LUT path
-    input CLK0, CLK1, CLK2, AC0, AC1,                     // FF path
-    output COMB0, COMB1, SUM0, SUM1, CARRYOUT, SHAREOUT,
-    output FF0, FF1, FF2, FF3
-);
-
-parameter LUT0 = 16'b0000;
-parameter LUT1 = 16'b0000;
-parameter LUT2 = 16'b0000;
-parameter LUT3 = 16'b0000;
-
-parameter INIT0 = 1'b0;
-parameter INIT1 = 1'b0;
-parameter INIT2 = 1'b0;
-parameter INIT3 = 1'b0;
-
-parameter C0_MUX = "C0";
-parameter C1_MUX = "C1";
-
-parameter F0_MUX = "VCC";
-parameter F1_MUX = "GND";
-
-parameter FEEDBACK0 = "FF0";
-parameter FEEDBACK1 = "FF2";
-
-parameter ADD_MUX = "LUT";
-
-parameter DFF01_DATA_MUX = "COMB";
-parameter DFF23_DATA_MUX = "COMB";
-
-parameter DFF0_CLK = "CLK0";
-parameter DFF1_CLK = "CLK0";
-parameter DFF2_CLK = "CLK0";
-parameter DFF3_CLK = "CLK0";
-
-parameter DFF0_AC  = "AC0";
-parameter DFF1_AC  = "AC0";
-parameter DFF2_AC  = "AC0";
-parameter DFF3_AC  = "AC0";
-
-// Feedback muxes from the flip-flop outputs.
-wire ff_feedback_mux0, ff_feedback_mux1;
-
-// C-input muxes which can be set to also use the F-input.
-wire c0_input_mux, c1_input_mux;
-
-// F-input muxes which can be set to a constant to allow LUT5 use.
-wire f0_input_mux, f1_input_mux;
-
-// Adder input muxes to select between shared-arithmetic mode and arithmetic mode.
-wire add0_input_mux, add1_input_mux;
-
-// Combinational-output muxes for LUT #1 and LUT #3
-wire lut1_comb_mux, lut3_comb_mux;
-
-// Sum-output muxes for LUT #1 and LUT #3
-wire lut1_sum_mux, lut3_sum_mux;
-
-// DFF data-input muxes
-wire dff01_data_mux, dff23_data_mux;
-
-// DFF clock selectors
-wire dff0_clk, dff1_clk, dff2_clk, dff3_clk;
-
-// DFF asynchronous-clear selectors
-wire dff0_ac, dff1_ac, dff2_ac, dff3_ac;
-
-// LUT, DFF and adder output wires for routing.
-wire lut0_out, lut1a_out, lut1b_out, lut2_out, lut3a_out, lut3b_out;
-wire dff0_out, dff1_out, dff2_out, dff3_out;
-wire add0_sum, add1_sum, add0_carry, add1_carry;
-
-generate
-    if (FEEDBACK0 === "FF0")
-        assign ff_feedback_mux0 = dff0_out;
-    else if (FEEDBACK0 === "FF1")
-        assign ff_feedback_mux0 = dff1_out;
-    else
-        $error("Invalid FEEDBACK0 setting!");
-
-    if (FEEDBACK1 == "FF2")
-        assign ff_feedback_mux1 = dff2_out;
-    else if (FEEDBACK1 == "FF3")
-        assign ff_feedback_mux1 = dff3_out;
-    else
-        $error("Invalid FEEDBACK1 setting!");
-
-    if (C0_MUX === "C0")
-        assign c0_input_mux = C0;
-    else if (C0_MUX === "F1")
-        assign c0_input_mux = F1;
-    else if (C0_MUX === "FEEDBACK1")
-        assign c0_input_mux = ff_feedback_mux1;
-    else
-        $error("Invalid C0_MUX setting!");
-
-    if (C1_MUX === "C1")
-        assign c1_input_mux = C1;
-    else if (C1_MUX === "F0")
-        assign c1_input_mux = F0;
-    else if (C1_MUX === "FEEDBACK0")
-        assign c1_input_mux = ff_feedback_mux0;
-    else
-        $error("Invalid C1_MUX setting!");
-
-    // F0 == VCC is LUT5
-    // F0 == F0 is LUT6
-    // F0 == FEEDBACK is unknown
-    if (F0_MUX === "VCC")
-        assign f0_input_mux = 1'b1;
-    else if (F0_MUX === "F0")
-        assign f0_input_mux = F0;
-    else if (F0_MUX === "FEEDBACK0")
-        assign f0_input_mux = ff_feedback_mux0;
-    else
-        $error("Invalid F0_MUX setting!");
-
-    // F1 == GND is LUT5
-    // F1 == F1 is LUT6
-    // F1 == FEEDBACK is unknown
-    if (F1_MUX === "GND")
-        assign f1_input_mux = 1'b0;
-    else if (F1_MUX === "F1")
-        assign f1_input_mux = F1;
-    else if (F1_MUX === "FEEDBACK1")
-        assign f1_input_mux = ff_feedback_mux1;
-    else
-        $error("Invalid F1_MUX setting!");
-
-    if (ADD_MUX === "LUT") begin
-        assign add0_input_mux = ~lut1_sum_mux;
-        assign add1_input_mux = ~lut3_sum_mux;
-    end else if (ADD_MUX === "SHARE") begin
-        assign add0_input_mux = SHAREIN;
-        assign add1_input_mux = lut1_comb_mux;
-    end else
-        $error("Invalid ADD_MUX setting!");
-
-    if (DFF01_DATA_MUX === "COMB")
-        assign dff01_data_mux = COMB0;
-    else if (DFF01_DATA_MUX === "SUM")
-        assign dff01_data_mux = SUM0;
-    else
-        $error("Invalid DFF01_DATA_MUX setting!");
-
-    if (DFF23_DATA_MUX === "COMB")
-        assign dff23_data_mux = COMB0;
-    else if (DFF23_DATA_MUX === "SUM")
-        assign dff23_data_mux = SUM0;
-    else
-        $error("Invalid DFF23_DATA_MUX setting!");
-
-    if (DFF0_CLK === "CLK0")
-        assign dff0_clk = CLK0;
-    else if (DFF0_CLK === "CLK1")
-        assign dff0_clk = CLK1;
-    else if (DFF0_CLK === "CLK2")
-        assign dff0_clk = CLK2;
-    else
-        $error("Invalid DFF0_CLK setting!");
-
-    if (DFF1_CLK === "CLK0")
-        assign dff1_clk = CLK0;
-    else if (DFF1_CLK === "CLK1")
-        assign dff1_clk = CLK1;
-    else if (DFF1_CLK === "CLK2")
-        assign dff1_clk = CLK2;
-    else
-        $error("Invalid DFF1_CLK setting!");
-
-    if (DFF2_CLK === "CLK0")
-        assign dff2_clk = CLK0;
-    else if (DFF2_CLK === "CLK1")
-        assign dff2_clk = CLK1;
-    else if (DFF2_CLK === "CLK2")
-        assign dff2_clk = CLK2;
-    else
-        $error("Invalid DFF2_CLK setting!");
-
-    if (DFF3_CLK === "CLK0")
-        assign dff3_clk = CLK0;
-    else if (DFF3_CLK === "CLK1")
-        assign dff3_clk = CLK1;
-    else if (DFF3_CLK === "CLK2")
-        assign dff3_clk = CLK2;
-    else
-        $error("Invalid DFF3_CLK setting!");
-
-    if (DFF0_AC === "AC0")
-        assign dff0_ac = AC0;
-    else if (DFF0_AC === "AC1")
-        assign dff0_ac = AC1;
-    else
-        $error("Invalid DFF0_AC setting!");
-
-    if (DFF1_AC === "AC0")
-        assign dff1_ac = AC0;
-    else if (DFF1_AC === "AC1")
-        assign dff1_ac = AC1;
-    else
-        $error("Invalid DFF1_AC setting!");
-
-    if (DFF2_AC === "AC0")
-        assign dff2_ac = AC0;
-    else if (DFF2_AC === "AC1")
-        assign dff2_ac = AC1;
-    else
-        $error("Invalid DFF2_AC setting!");
-
-    if (DFF3_AC === "AC0")
-        assign dff3_ac = AC0;
-    else if (DFF3_AC === "AC1")
-        assign dff3_ac = AC1;
-    else
-        $error("Invalid DFF3_AC setting!");
-
-endgenerate
-
-// F0 on the Quartus diagram
-MISTRAL_ALUT4 #(.LUT(LUT0)) lut0 (.A(A), .B(B), .C(C0), .D(c1_input_mux), .Q(lut0_out));
-
-// F2 on the Quartus diagram
-MISTRAL_ALUT4 #(.LUT(LUT1)) lut1_comb (.A(A), .B(B), .C(C0), .D(c1_input_mux), .Q(lut1_comb_mux));
-MISTRAL_ALUT4 #(.LUT(LUT1)) lut1_sum  (.A(A), .B(B), .C(C0), .D(E0), .Q(lut1_sum_mux));
-
-// F1 on the Quartus diagram
-MISTRAL_ALUT4 #(.LUT(LUT2)) lut2 (.A(A), .B(B), .C(C1), .D(c0_input_mux), .Q(lut2_out));
-
-// F3 on the Quartus diagram
-MISTRAL_ALUT4 #(.LUT(LUT3)) lut3_comb (.A(A), .B(B), .C(C1), .D(c0_input_mux), .Q(lut3_comb_mux));
-MISTRAL_ALUT4 #(.LUT(LUT3)) lut3_sum  (.A(A), .B(B), .C(C1), .D(E1), .Q(lut3_sum_mux));
-
-MISTRAL_FF #(.INIT(INIT0)) dff0 (.D(dff01_data_mux), .CLK(dff0_clk), .ACn(dff0_ac), .Q(dff0_out));
-MISTRAL_FF #(.INIT(INIT1)) dff1 (.D(dff01_data_mux), .CLK(dff1_clk), .ACn(dff1_ac), .Q(dff1_out));
-MISTRAL_FF #(.INIT(INIT2)) dff2 (.D(dff23_data_mux), .CLK(dff2_clk), .ACn(dff2_ac), .Q(dff2_out));
-MISTRAL_FF #(.INIT(INIT3)) dff3 (.D(dff23_data_mux), .CLK(dff3_clk), .ACn(dff3_ac), .Q(dff3_out));
-
-// Adders
-assign {add0_carry, add0_sum} = CARRYIN + lut0_out + lut1_sum_mux;
-assign {add1_carry, add1_sum} = add0_carry + lut2_out + lut3_sum_mux;
-
-// COMBOUT outputs on the Quartus diagram
-assign COMB0 = E0 ? (f0_input_mux ? lut3_comb_mux : lut1_comb_mux)
-                    : (f0_input_mux ? lut2_out : lut0_out);
-
-assign COMB1 = E1 ? (f1_input_mux ? lut3_comb_mux : lut1_comb_mux)
-                    : (f1_input_mux ? lut2_out : lut0_out);
-
-// SUMOUT output on the Quartus diagram
-assign SUM0 = add0_sum;
-assign SUM1 = add1_sum;
-
-// COUT output on the Quartus diagram
-assign CARRYOUT = add1_carry;
-
-// SHAREOUT output on the Quartus diagram
-assign SHAREOUT = lut3_comb_mux;
-
-// REGOUT outputs on the Quartus diagram
-assign FF0 = dff0_out;
-assign FF1 = dff1_out;
-assign FF2 = dff2_out;
-assign FF3 = dff3_out;
-
-endmodule
-*/
diff --git a/techlibs/intel_alm/common/bram_m20k.txt b/techlibs/intel_alm/common/bram_m20k.txt
deleted file mode 100644
index b4c5a537287..00000000000
--- a/techlibs/intel_alm/common/bram_m20k.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-bram __MISTRAL_M20K_SDP
-    init   1   # TODO: Re-enable when I figure out how BRAM init works
-    abits 14   @D16384x1
-    dbits  1   @D16384x1
-    abits 13   @D8192x2
-    dbits  2   @D8192x2
-    abits 12   @D4096x4 @D4096x5
-    dbits  4   @D4096x4
-    dbits  5   @D4096x5
-    abits 11   @D2048x8 @D2048x10
-    dbits  8   @D2048x8
-    dbits 10   @D2048x10
-    abits 10   @D1024x16 @D1024x20
-    dbits 16   @D1024x16
-    dbits 20   @D1024x20
-    abits  9   @D512x32 @D512x40
-    dbits 32   @D512x32
-    dbits 40   @D512x40
-    groups 2
-    ports  1 1
-    wrmode 1 0
-    # read enable; write enable + byte enables (only for multiples of 8)
-    enable 1 1
-    transp 0 0
-    clocks 1 1
-    clkpol 1 1
-endbram
-
-
-match __MISTRAL_M20K_SDP
-    min efficiency 5
-    make_transp
-endmatch
diff --git a/techlibs/intel_alm/common/bram_m20k_map.v b/techlibs/intel_alm/common/bram_m20k_map.v
deleted file mode 100644
index 15739d66a2e..00000000000
--- a/techlibs/intel_alm/common/bram_m20k_map.v
+++ /dev/null
@@ -1,31 +0,0 @@
-module __MISTRAL_M20K_SDP(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
-
-parameter CFG_ABITS = 10;
-parameter CFG_DBITS = 20;
-parameter CFG_ENABLE_A = 1;
-parameter CFG_ENABLE_B = 1;
-
-input CLK1;
-input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
-input [CFG_DBITS-1:0] A1DATA;
-output [CFG_DBITS-1:0] B1DATA;
-input [CFG_ENABLE_A-1:0] A1EN, B1EN;
-
-altsyncram #(
-    .operation_mode("dual_port"),
-    .ram_block_type("m20k"),
-    .widthad_a(CFG_ABITS),
-    .width_a(CFG_DBITS),
-    .widthad_b(CFG_ABITS),
-    .width_b(CFG_DBITS),
-) _TECHMAP_REPLACE_ (
-    .address_a(A1ADDR),
-    .data_a(A1DATA),
-    .wren_a(A1EN),
-    .address_b(B1ADDR),
-    .q_b(B1DATA),
-    .clock0(CLK1),
-    .clock1(CLK1)
-);
-
-endmodule
diff --git a/techlibs/intel_alm/common/dff_sim.v b/techlibs/intel_alm/common/dff_sim.v
index 8d58bf61485..a558973f9fd 100644
--- a/techlibs/intel_alm/common/dff_sim.v
+++ b/techlibs/intel_alm/common/dff_sim.v
@@ -77,38 +77,6 @@ specify
     if (ACLR === 1'b0) (ACLR => Q) = 282;
 endspecify
 `endif
-`ifdef arriav
-specify
-    if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 470;
-    if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 633;
-    if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 439;
-
-    $setup(DATAIN, posedge CLK, /* -170 */ 0);
-    $setup(ENA, posedge CLK, /* -170 */ 0);
-    $setup(SCLR, posedge CLK, /* -170 */ 0);
-    $setup(SLOAD, posedge CLK, /* -170 */ 0);
-    $setup(SDATA, posedge CLK, /* -170 */ 0);
-
-    if (ACLR === 1'b0) (ACLR => Q) = 215;
-endspecify
-`endif
-`ifdef cyclone10gx
-specify
-    // TODO (long-term): investigate these numbers.
-    // It seems relying on the Quartus Timing Analyzer was not the best idea; it's too fiddly.
-    if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 219;
-    if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 219;
-    if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 219;
-
-    $setup(DATAIN, posedge CLK, 268);
-    $setup(ENA, posedge CLK, 268);
-    $setup(SCLR, posedge CLK, 268);
-    $setup(SLOAD, posedge CLK, 268);
-    $setup(SDATA, posedge CLK, 268);
-
-    if (ACLR === 1'b0) (ACLR => Q) = 0;
-endspecify
-`endif
 
 initial begin
     // Altera flops initialise to zero.
diff --git a/techlibs/intel_alm/common/mem_sim.v b/techlibs/intel_alm/common/mem_sim.v
index 563f1d2413e..5ab1b73261f 100644
--- a/techlibs/intel_alm/common/mem_sim.v
+++ b/techlibs/intel_alm/common/mem_sim.v
@@ -1,7 +1,7 @@
 // The MLAB
 // --------
 // In addition to Logic Array Blocks (LABs) that contain ten Adaptive Logic
-// Modules (ALMs, see alm_sim.v), the Cyclone V/10GX also contain
+// Modules (ALMs, see alm_sim.v), the Cyclone V also contains
 // Memory/Logic Array Blocks (MLABs) that can act as either ten ALMs, or utilise
 // the memory the ALM uses to store the look-up table data for general usage,
 // producing a 32 address by 20-bit block of memory. MLABs are spread out
@@ -14,11 +14,8 @@
 // or shift registers (by using the output of the Nth bit as input for the N+1th
 // bit).
 //
-// Oddly, instead of providing a block 32 address by 20-bit cell, Quartus asks
-// synthesis tools to build MLABs out of 32 address by 1-bit cells, and tries
-// to put these cells in the same MLAB during cell placement. Because of this
-// a MISTRAL_MLAB cell represents one of these 32 address by 1-bit cells, and
-// 20 of them represent a physical MLAB.
+// For historical reasons a MISTRAL_MLAB cell represents a 32 address by 1-bit cell,
+// and 20 of them represent a physical MLAB.
 //
 // How the MLAB works
 // ------------------
@@ -28,10 +25,7 @@
 // by the Yosys `memory_bram` pass, and it doesn't make sense to me to use
 // `techmap` just for the sake of renaming the cell ports.
 //
-// The MLAB can be initialised to any value, but unfortunately Quartus only
-// allows memory initialisation from a file. Since Yosys doesn't preserve input
-// file information, or write the contents of an `initial` block to a file,
-// Yosys can't currently initialise the MLAB in a way Quartus will accept.
+// The MLAB can be initialised to any value.
 //
 // The MLAB takes in data from A1DATA at the rising edge of CLK1, and if A1EN
 // is high, writes it to the address in A1ADDR. A1EN can therefore be used to
@@ -39,9 +33,7 @@
 //
 // Simultaneously, the MLAB reads data from B1ADDR, and outputs it to B1DATA,
 // asynchronous to CLK1 and ignoring A1EN. If a synchronous read is needed
-// then the output can be fed to embedded flops. Presently, Yosys assumes
-// Quartus will pack external flops into the MLAB, but this is an assumption
-// that needs testing.
+// then the output can be fed to embedded flops.
 
 // The vendor sim model outputs 'x for a very short period (a few
 // combinational delta cycles) after each write. This has been omitted from
@@ -69,33 +61,6 @@ specify
     (B1ADDR[4] => B1DATA) = 96;
 endspecify
 `endif
-`ifdef arriav
-specify
-    $setup(A1ADDR, posedge CLK1, 62);
-    $setup(A1DATA, posedge CLK1, 62);
-    $setup(A1EN, posedge CLK1, 62);
-
-    (B1ADDR[0] => B1DATA) = 370;
-    (B1ADDR[1] => B1DATA) = 292;
-    (B1ADDR[2] => B1DATA) = 218;
-    (B1ADDR[3] => B1DATA) = 74;
-    (B1ADDR[4] => B1DATA) = 177;
-endspecify
-`endif
-`ifdef cyclone10gx
-// TODO: Cyclone 10 GX timings; the below timings are for Cyclone V
-specify
-    $setup(A1ADDR, posedge CLK1, 86);
-    $setup(A1DATA, posedge CLK1, 86);
-    $setup(A1EN, posedge CLK1, 86);
-
-    (B1ADDR[0] => B1DATA) = 487;
-    (B1ADDR[1] => B1DATA) = 475;
-    (B1ADDR[2] => B1DATA) = 382;
-    (B1ADDR[3] => B1DATA) = 284;
-    (B1ADDR[4] => B1DATA) = 96;
-endspecify
-`endif
 
 always @(posedge CLK1)
     if (A1EN) mem[A1ADDR] <= A1DATA;
@@ -134,17 +99,6 @@ specify
     if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 1004;
 endspecify
 `endif
-`ifdef arriav
-specify
-    $setup(A1ADDR, posedge CLK1, 97);
-    $setup(A1DATA, posedge CLK1, 74);
-    $setup(A1EN, posedge CLK1, 109);
-    $setup(B1ADDR, posedge CLK1, 97);
-    $setup(B1EN, posedge CLK1, 126);
-
-    if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 787;
-endspecify
-`endif
 
 always @(posedge CLK1) begin
     if (!A1EN)
diff --git a/techlibs/intel_alm/common/quartus_rename.v b/techlibs/intel_alm/common/quartus_rename.v
deleted file mode 100644
index 217dc5de98b..00000000000
--- a/techlibs/intel_alm/common/quartus_rename.v
+++ /dev/null
@@ -1,311 +0,0 @@
-`ifdef cyclonev
-`define LCELL cyclonev_lcell_comb
-`define MAC cyclonev_mac
-`define MLAB cyclonev_mlab_cell
-`define RAM_BLOCK cyclonev_ram_block
-`define IBUF cyclonev_io_ibuf
-`define OBUF cyclonev_io_obuf
-`define CLKENA cyclonev_clkena
-`endif
-`ifdef arriav
-`define LCELL arriav_lcell_comb
-`define MAC arriav_mac
-`define MLAB arriav_mlab_cell
-`define RAM_BLOCK arriav_ram_block
-`define IBUF arriav_io_ibuf
-`define OBUF arriav_io_obuf
-`define CLKENA arriav_clkena
-`endif
-`ifdef cyclone10gx
-`define LCELL cyclone10gx_lcell_comb
-`define MAC cyclone10gx_mac
-`define MLAB cyclone10gx_mlab_cell
-`define RAM_BLOCK cyclone10gx_ram_block
-`define IBUF cyclone10gx_io_ibuf
-`define OBUF cyclone10gx_io_obuf
-`define CLKENA cyclone10gx_clkena
-`endif
-
-module __MISTRAL_VCC(output Q);
-
-MISTRAL_ALUT2 #(.LUT(4'b1111)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));
-
-endmodule
-
-
-module __MISTRAL_GND(output Q);
-
-MISTRAL_ALUT2 #(.LUT(4'b0000)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));
-
-endmodule
-
-
-module MISTRAL_FF(input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA, output reg Q);
-
-dffeas #(.power_up("low"), .is_wysiwyg("true")) _TECHMAP_REPLACE_ (.d(DATAIN), .clk(CLK), .clrn(ACLR), .ena(ENA), .sclr(SCLR), .sload(SLOAD), .asdata(SDATA), .q(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
-parameter [63:0] LUT = 64'h0000_0000_0000_0000;
-
-`LCELL #(.lut_mask(LUT)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .dataf(F), .combout(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT5(input A, B, C, D, E, output Q);
-parameter [31:0] LUT = 32'h0000_0000;
-
-`LCELL #(.lut_mask({2{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .combout(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT4(input A, B, C, D, output Q);
-parameter [15:0] LUT = 16'h0000;
-
-`LCELL #(.lut_mask({4{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT3(input A, B, C, output Q);
-parameter [7:0] LUT = 8'h00;
-
-`LCELL #(.lut_mask({8{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT2(input A, B, output Q);
-parameter [3:0] LUT = 4'h0;
-
-`LCELL #(.lut_mask({16{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q));
-
-endmodule
-
-
-module MISTRAL_NOT(input A, output Q);
-
-NOT _TECHMAP_REPLACE_ (.IN(A), .OUT(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, CI, output SO, CO);
-parameter LUT0 = 16'h0000;
-parameter LUT1 = 16'h0000;
-
-`LCELL #(.lut_mask({16'h0, LUT1, 16'h0, LUT0})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D0), .dataf(D1), .cin(CI), .sumout(SO), .cout(CO));
-
-endmodule
-
-
-module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA);
-
-parameter _TECHMAP_CELLNAME_ = "";
-
-// Here we get to an unfortunate situation. The cell has a mem_init0 parameter,
-// which takes in a hexadecimal string that could be used to initialise RAM.
-// In the vendor simulation models, this appears to work fine, but Quartus,
-// either intentionally or not, forgets about this parameter and initialises the
-// RAM to zero.
-//
-// Because of this, RAM initialisation is presently disabled, but the source
-// used to generate mem_init0 is kept (commented out) in case this gets fixed
-// or an undocumented way to get Quartus to initialise from mem_init0 is found.
-
-`MLAB #(
-    .logical_ram_name(_TECHMAP_CELLNAME_),
-    .logical_ram_depth(32),
-    .logical_ram_width(1),
-    .mixed_port_feed_through_mode("Dont Care"),
-    .first_bit_number(0),
-    .first_address(0),
-    .last_address(31),
-    .address_width(5),
-    .data_width(1),
-    .byte_enable_mask_width(1),
-    .port_b_data_out_clock("NONE"),
-    // .mem_init0($sformatf("%08x", INIT))
-) _TECHMAP_REPLACE_ (
-    .portaaddr(A1ADDR),
-    .portadatain(A1DATA),
-    .portbaddr(B1ADDR),
-    .portbdataout(B1DATA),
-    .ena0(A1EN),
-    .clk0(CLK1)
-);
-
-endmodule
-
-
-module MISTRAL_M10K(A1ADDR, A1DATA, A1EN, CLK1, B1ADDR, B1DATA, B1EN);
-
-parameter CFG_ABITS = 10;
-parameter CFG_DBITS = 10;
-
-parameter _TECHMAP_CELLNAME_ = "";
-
-input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
-input [CFG_DBITS-1:0] A1DATA;
-input CLK1, A1EN, B1EN;
-output [CFG_DBITS-1:0] B1DATA;
-
-// Much like the MLAB, the M10K has mem_init[01234] parameters which would let
-// you initialise the RAM cell via hex literals. If they were implemented.
-
-// Since the MISTRAL_M10K block has an inverted write-enable (like the real hardware)
-// but the Quartus primitive expects a normal write-enable, we add an inverter.
-wire A1EN_N;
-NOT wren_inv (.IN(A1EN), .OUT(A1EN_N));
-
-`RAM_BLOCK #(
-    .operation_mode("dual_port"),
-    .logical_ram_name(_TECHMAP_CELLNAME_),
-    .port_a_address_width(CFG_ABITS),
-    .port_a_data_width(CFG_DBITS),
-    .port_a_logical_ram_depth(2**CFG_ABITS),
-    .port_a_logical_ram_width(CFG_DBITS),
-    .port_a_first_address(0),
-    .port_a_last_address(2**CFG_ABITS - 1),
-    .port_a_first_bit_number(0),
-    .port_b_address_width(CFG_ABITS),
-    .port_b_data_width(CFG_DBITS),
-    .port_b_logical_ram_depth(2**CFG_ABITS),
-    .port_b_logical_ram_width(CFG_DBITS),
-    .port_b_first_address(0),
-    .port_b_last_address(2**CFG_ABITS - 1),
-    .port_b_first_bit_number(0),
-    .port_b_address_clock("clock0"),
-    .port_b_read_enable_clock("clock0")
-) ram_block (
-    .portaaddr(A1ADDR),
-    .portadatain(A1DATA),
-    .portawe(A1EN_N),
-    .portbaddr(B1ADDR),
-    .portbdataout(B1DATA),
-    .portbre(B1EN),
-    .clk0(CLK1)
-);
-
-endmodule
-
-
-module MISTRAL_MUL27X27(input [26:0] A, B, output [53:0] Y);
-
-parameter A_SIGNED = 1;
-parameter B_SIGNED = 1;
-
-`MAC #(
-    .ax_width(27),
-    .signed_max(A_SIGNED ? "true" : "false"),
-    .ay_scan_in_width(27),
-    .signed_may(B_SIGNED ? "true" : "false"),
-    .result_a_width(54),
-    .operation_mode("M27x27")
-) _TECHMAP_REPLACE_ (
-    .ax(A),
-    .ay(B),
-    .resulta(Y)
-);
-
-endmodule
-
-
-module MISTRAL_MUL18X18(input [17:0] A, B, output [35:0] Y);
-
-parameter A_SIGNED = 1;
-parameter B_SIGNED = 1;
-
-`MAC #(
-    .ax_width(18),
-    .signed_max(A_SIGNED ? "true" : "false"),
-    .ay_scan_in_width(18),
-    .signed_may(B_SIGNED ? "true" : "false"),
-    .result_a_width(36),
-    .operation_mode("M18x18_FULL")
-) _TECHMAP_REPLACE_ (
-    .ax(A),
-    .ay(B),
-    .resulta(Y)
-);
-
-endmodule
-
-
-module MISTRAL_MUL9X9(input [8:0] A, B, output [17:0] Y);
-
-parameter A_SIGNED = 1;
-parameter B_SIGNED = 1;
-
-`MAC #(
-    .ax_width(9),
-    .signed_max(A_SIGNED ? "true" : "false"),
-    .ay_scan_in_width(9),
-    .signed_may(B_SIGNED ? "true" : "false"),
-    .result_a_width(18),
-    .operation_mode("M9x9")
-) _TECHMAP_REPLACE_ (
-    .ax(A),
-    .ay(B),
-    .resulta(Y)
-);
-
-endmodule
-
-module MISTRAL_IB(input PAD, output O);
-`IBUF #(
-    .bus_hold("false"),
-    .differential_mode("false")
-) _TECHMAP_REPLACE_ (
-    .i(PAD),
-    .o(O)
-);
-endmodule
-
-module MISTRAL_OB(output PAD, input I, OE);
-`OBUF #(
-    .bus_hold("false"),
-    .differential_mode("false")
-) _TECHMAP_REPLACE_ (
-    .i(I),
-    .o(PAD),
-    .oe(OE)
-);
-endmodule
-
-module MISTRAL_IO(output PAD, input I, OE, output O);
-`IBUF #(
-    .bus_hold("false"),
-    .differential_mode("false")
-) ibuf (
-    .i(PAD),
-    .o(O)
-);
-
-`OBUF #(
-    .bus_hold("false"),
-    .differential_mode("false")
-) obuf (
-    .i(I),
-    .o(PAD),
-    .oe(OE)
-);
-endmodule
-
-module MISTRAL_CLKBUF (input A, output Q);
-`CLKENA #(
-    .clock_type("auto"),
-    .ena_register_mode("always enabled"),
-    .ena_register_power_up("high"),
-    .disable_mode("low"),
-    .test_syn("high")
-) _TECHMAP_REPLACE_ (
-    .inclk(A),
-    .ena(1'b1),
-    .outclk(Q)
-);
-endmodule
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc
index c33eb43bf35..cdae9586eb0 100644
--- a/techlibs/intel_alm/synth_intel_alm.cc
+++ b/techlibs/intel_alm/synth_intel_alm.cc
@@ -2,7 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
- *  Copyright (C) 2019  Dan Ravensloft <dan.ravensloft@gmail.com>
+ *  Copyright (C) 2019  Hannah Ravensloft <dan.ravensloft@gmail.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -43,21 +43,11 @@ struct SynthIntelALMPass : public ScriptPass {
 		log("    -family <family>\n");
 		log("        target one of:\n");
 		log("        \"cyclonev\"    - Cyclone V (default)\n");
-		log("        \"arriav\"      - Arria V (non-GZ)\n");
-		log("        \"cyclone10gx\" - Cyclone 10GX\n");
-		log("\n");
-		log("    -vqm <file>\n");
-		log("        write the design to the specified Verilog Quartus Mapping File. Writing\n");
-		log("        of an output file is omitted if this parameter is not specified. Implies\n");
-		log("        -quartus.\n");
 		log("\n");
 		log("    -noflatten\n");
 		log("        do not flatten design before synthesis; useful for per-module area\n");
 		log("        statistics\n");
 		log("\n");
-		log("    -quartus\n");
-		log("        output a netlist using Quartus cells instead of MISTRAL_* cells\n");
-		log("\n");
 		log("    -dff\n");
 		log("        pass DFFs to ABC to perform sequential logic optimisations\n");
 		log("        (EXPERIMENTAL)\n");
@@ -87,17 +77,15 @@ struct SynthIntelALMPass : public ScriptPass {
 		log("\n");
 	}
 
-	string top_opt, family_opt, bram_type, vout_file;
-	bool flatten, quartus, nolutram, nobram, dff, nodsp, noiopad, noclkbuf;
+	string top_opt, family_opt, bram_type;
+	bool flatten, nolutram, nobram, dff, nodsp, noiopad, noclkbuf;
 
 	void clear_flags() override
 	{
 		top_opt = "-auto-top";
 		family_opt = "cyclonev";
 		bram_type = "m10k";
-		vout_file = "";
 		flatten = true;
-		quartus = false;
 		nolutram = false;
 		nobram = false;
 		dff = false;
@@ -121,11 +109,6 @@ struct SynthIntelALMPass : public ScriptPass {
 				top_opt = "-top " + args[++argidx];
 				continue;
 			}
-			if (args[argidx] == "-vqm" && argidx + 1 < args.size()) {
-				quartus = true;
-				vout_file = args[++argidx];
-				continue;
-			}
 			if (args[argidx] == "-run" && argidx + 1 < args.size()) {
 				size_t pos = args[argidx + 1].find(':');
 				if (pos == std::string::npos)
@@ -134,10 +117,6 @@ struct SynthIntelALMPass : public ScriptPass {
 				run_to = args[argidx].substr(pos + 1);
 				continue;
 			}
-			if (args[argidx] == "-quartus") {
-				quartus = true;
-				continue;
-			}
 			if (args[argidx] == "-nolutram") {
 				nolutram = true;
 				continue;
@@ -173,18 +152,6 @@ struct SynthIntelALMPass : public ScriptPass {
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
 
-		if (family_opt == "cyclonev" || family_opt == "arriav") {
-			bram_type = "m10k";
-		} else if (family_opt == "cyclone10gx") {
-			bram_type = "m20k";
-		} else if (family_opt == "arriva") {
-			// I have typoed "arriav" as "arriva" (a local bus company)
-			// so many times I thought it would be funny to have an easter egg.
-			log_cmd_error("synth_intel_alm cannot synthesize for bus companies. (did you mean '-family arriav'?)\n");
-		} else {
-			log_cmd_error("Invalid family specified: '%s'\n", family_opt.c_str());
-		}
-
 		log_header(design, "Executing SYNTH_INTEL_ALM pass.\n");
 		log_push();
 
@@ -237,22 +204,16 @@ struct SynthIntelALMPass : public ScriptPass {
 			if (help_mode) {
 				run("techmap -map +/mul2dsp.v [...]", "(unless -nodsp)");
 			} else if (!nodsp) {
-				// Cyclone V/Arria V supports 9x9 multiplication, Cyclone 10 GX does not.
 				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=27 -D DSP_B_MAXWIDTH=27  -D DSP_A_MINWIDTH=19 -D DSP_B_MINWIDTH=4 -D DSP_NAME=__MUL27X27");
 				run("chtype -set $mul t:$__soft_mul");
 				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=27 -D DSP_B_MAXWIDTH=27  -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=19 -D DSP_NAME=__MUL27X27");
 				run("chtype -set $mul t:$__soft_mul");
-				if (family_opt == "cyclonev" || family_opt == "arriav") {
-					run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=10 -D DSP_B_MINWIDTH=4 -D DSP_NAME=__MUL18X18");
-					run("chtype -set $mul t:$__soft_mul");
-					run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=10 -D DSP_NAME=__MUL18X18");
-					run("chtype -set $mul t:$__soft_mul");
-					run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=9 -D DSP_B_MAXWIDTH=9  -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=__MUL9X9");
-					run("chtype -set $mul t:$__soft_mul");
-				} else if (family_opt == "cyclone10gx") {
-					run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=__MUL18X18");
-					run("chtype -set $mul t:$__soft_mul");
-				}
+				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=10 -D DSP_B_MINWIDTH=4 -D DSP_NAME=__MUL18X18");
+				run("chtype -set $mul t:$__soft_mul");
+				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=10 -D DSP_NAME=__MUL18X18");
+				run("chtype -set $mul t:$__soft_mul");
+				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=9 -D DSP_B_MAXWIDTH=9  -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=__MUL9X9");
+				run("chtype -set $mul t:$__soft_mul");
 			}
 			run("alumacc");
 			if (!noiopad)
@@ -269,7 +230,7 @@ struct SynthIntelALMPass : public ScriptPass {
 		}
 
 		if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) {
-			run("memory_bram -rules +/intel_alm/common/lutram_mlab.txt", "(for Cyclone V / Cyclone 10GX)");
+			run("memory_bram -rules +/intel_alm/common/lutram_mlab.txt", "(for Cyclone V)");
 		}
 
 		if (check_label("map_ffram")) {
@@ -303,28 +264,6 @@ struct SynthIntelALMPass : public ScriptPass {
 			run("check");
 			run("blackbox =A:whitebox");
 		}
-
-		if (check_label("quartus")) {
-			if (quartus || help_mode) {
-				// Quartus ICEs if you have a wire which has `[]` in its name,
-				// which Yosys produces when building memories out of flops.
-				run("rename -hide w:*[* w:*]*");
-				// VQM mode does not support 'x, so replace those with zero.
-				run("setundef -zero");
-				// VQM mode does not support multi-bit constant assignments
-				// (e.g. 2'b00 is an error), so as a workaround use references
-				// to constant driver cells, which Quartus accepts.
-				run("hilomap -singleton -hicell __MISTRAL_VCC Q -locell __MISTRAL_GND Q");
-				// Rename from Yosys-internal MISTRAL_* cells to Quartus cells.
-				run(stringf("techmap -D %s -map +/intel_alm/common/quartus_rename.v", family_opt.c_str()));
-			}
-		}
-
-		if (check_label("vqm")) {
-			if (!vout_file.empty() || help_mode) {
-				run(stringf("write_verilog -attr2comment -defparam -nohex -decimal %s", help_mode ? "<file-name>" : vout_file.c_str()));
-			}
-		}
 	}
 } SynthIntelALMPass;
 
diff --git a/tests/arch/intel_alm/add_sub.ys b/tests/arch/intel_alm/add_sub.ys
index 8f87adf2713..6453da116a1 100644
--- a/tests/arch/intel_alm/add_sub.ys
+++ b/tests/arch/intel_alm/add_sub.ys
@@ -7,12 +7,3 @@ stat
 select -assert-count 9 t:MISTRAL_ALUT_ARITH
 select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
 
-design -reset
-read_verilog ../common/add_sub.v
-hierarchy -top top
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-stat
-select -assert-count 9 t:MISTRAL_ALUT_ARITH
-select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
diff --git a/tests/arch/intel_alm/adffs.ys b/tests/arch/intel_alm/adffs.ys
index d7487c40bec..1f81902ec5a 100644
--- a/tests/arch/intel_alm/adffs.ys
+++ b/tests/arch/intel_alm/adffs.ys
@@ -12,18 +12,6 @@ select -assert-count 1 t:MISTRAL_NOT
 select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
 
 
-design -load read
-hierarchy -top adff
-proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd adff # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_FF
-select -assert-count 1 t:MISTRAL_NOT
-
-select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
-
-
 design -load read
 hierarchy -top adffn
 proc
@@ -35,17 +23,6 @@ select -assert-count 1 t:MISTRAL_FF
 select -assert-none t:MISTRAL_FF %% t:* %D
 
 
-design -load read
-hierarchy -top adffn
-proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd adffn # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_FF
-
-select -assert-none t:MISTRAL_FF %% t:* %D
-
-
 design -load read
 hierarchy -top dffs
 proc
@@ -58,18 +35,6 @@ select -assert-count 1 t:MISTRAL_ALUT2
 select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 %% t:* %D
 
 
-design -load read
-hierarchy -top dffs
-proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd dffs # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_FF
-select -assert-count 1 t:MISTRAL_ALUT2
-
-select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 %% t:* %D
-
-
 design -load read
 hierarchy -top ndffnr
 proc
@@ -81,14 +46,3 @@ select -assert-count 2 t:MISTRAL_NOT
 
 select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
 
-
-design -load read
-hierarchy -top ndffnr
-proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd ndffnr # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_FF
-select -assert-count 2 t:MISTRAL_NOT
-
-select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
diff --git a/tests/arch/intel_alm/blockram.ys b/tests/arch/intel_alm/blockram.ys
index 21b5ecbfb60..4af59e7d434 100644
--- a/tests/arch/intel_alm/blockram.ys
+++ b/tests/arch/intel_alm/blockram.ys
@@ -5,3 +5,4 @@ cd sync_ram_sdp
 select -assert-count 1 t:MISTRAL_NOT
 select -assert-count 1 t:MISTRAL_M10K
 select -assert-none t:MISTRAL_NOT t:MISTRAL_M10K %% t:* %D
+
diff --git a/tests/arch/intel_alm/counter.ys b/tests/arch/intel_alm/counter.ys
index 2b428fb3e51..44e00081445 100644
--- a/tests/arch/intel_alm/counter.ys
+++ b/tests/arch/intel_alm/counter.ys
@@ -11,17 +11,3 @@ select -assert-count 8 t:MISTRAL_ALUT_ARITH
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
 
-
-design -reset
-read_verilog ../common/counter.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -assert -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 2 t:MISTRAL_NOT
-select -assert-count 8 t:MISTRAL_ALUT_ARITH
-select -assert-count 8 t:MISTRAL_FF
-select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
diff --git a/tests/arch/intel_alm/dffs.ys b/tests/arch/intel_alm/dffs.ys
index 34b99f04cbf..aeaae4aa3ce 100644
--- a/tests/arch/intel_alm/dffs.ys
+++ b/tests/arch/intel_alm/dffs.ys
@@ -7,17 +7,6 @@ equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
-
-select -assert-none t:MISTRAL_FF %% t:* %D
-
-design -load read
-hierarchy -top dff
-proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd dff # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_FF
-
 select -assert-none t:MISTRAL_FF %% t:* %D
 
 
@@ -28,16 +17,5 @@ equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
-
 select -assert-none t:MISTRAL_FF %% t:* %D
 
-
-design -load read
-hierarchy -top dffe
-proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd dffe # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_FF
-
-select -assert-none t:MISTRAL_FF %% t:* %D
diff --git a/tests/arch/intel_alm/fsm.ys b/tests/arch/intel_alm/fsm.ys
index 0aeea450ac5..f3060684a9f 100644
--- a/tests/arch/intel_alm/fsm.ys
+++ b/tests/arch/intel_alm/fsm.ys
@@ -20,25 +20,3 @@ select -assert-max 6 t:MISTRAL_ALUT5 # Clang returns 5, GCC returns 4
 select -assert-max 2 t:MISTRAL_ALUT6 # Clang returns 1, GCC returns 2
 select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
 
-design -reset
-read_verilog ../common/fsm.v
-hierarchy -top fsm
-proc
-flatten
-
-equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf
-async2sync
-miter -equiv -make_assert -flatten gold gate miter
-sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
-
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd fsm # Constrain all select calls below inside the top module
-
-select -assert-count 6 t:MISTRAL_FF
-select -assert-max 1 t:MISTRAL_NOT
-select -assert-max 2 t:MISTRAL_ALUT2 # Clang returns 2, GCC returns 1
-select -assert-max 2 t:MISTRAL_ALUT3 # Clang returns 2, GCC returns 1
-select -assert-max 2 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1
-select -assert-max 6 t:MISTRAL_ALUT5 # Clang returns 5, GCC returns 4
-select -assert-max 2 t:MISTRAL_ALUT6 # Clang returns 1, GCC returns 2
-select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
diff --git a/tests/arch/intel_alm/logic.ys b/tests/arch/intel_alm/logic.ys
index d34d1bc65de..831f9f1741e 100644
--- a/tests/arch/intel_alm/logic.ys
+++ b/tests/arch/intel_alm/logic.ys
@@ -10,16 +10,3 @@ select -assert-count 6 t:MISTRAL_ALUT2
 select -assert-count 2 t:MISTRAL_ALUT4
 select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D
 
-
-design -reset
-read_verilog ../common/logic.v
-hierarchy -top top
-proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 1 t:MISTRAL_NOT
-select -assert-count 6 t:MISTRAL_ALUT2
-select -assert-count 2 t:MISTRAL_ALUT4
-select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D
\ No newline at end of file
diff --git a/tests/arch/intel_alm/lutram.ys b/tests/arch/intel_alm/lutram.ys
index 9ddb1ec874e..4e77afded78 100644
--- a/tests/arch/intel_alm/lutram.ys
+++ b/tests/arch/intel_alm/lutram.ys
@@ -37,3 +37,4 @@ select -assert-count 2 t:MISTRAL_ALUT2
 select -assert-count 8 t:MISTRAL_ALUT3
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
+
diff --git a/tests/arch/intel_alm/mul.ys b/tests/arch/intel_alm/mul.ys
index e147d93ac1e..75b32846304 100644
--- a/tests/arch/intel_alm/mul.ys
+++ b/tests/arch/intel_alm/mul.ys
@@ -9,8 +9,6 @@ cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_MUL9X9
 select -assert-none t:MISTRAL_MUL9X9 %% t:* %D
 
-# Cyclone 10 GX does not have 9x9 multipliers.
-
 design -reset
 read_verilog ../common/mul.v
 chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
@@ -23,18 +21,6 @@ cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_MUL18X18
 select -assert-none t:MISTRAL_MUL18X18 %% t:* %D
 
-design -reset
-read_verilog ../common/mul.v
-chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
-hierarchy -top top
-proc
-equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 1 t:MISTRAL_MUL18X18
-select -assert-none t:MISTRAL_MUL18X18 %% t:* %D
-
 design -reset
 read_verilog ../common/mul.v
 chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
@@ -47,14 +33,3 @@ cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_MUL27X27
 select -assert-none t:MISTRAL_MUL27X27 %% t:* %D
 
-design -reset
-read_verilog ../common/mul.v
-chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
-hierarchy -top top
-proc
-equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 1 t:MISTRAL_MUL27X27
-select -assert-none t:MISTRAL_MUL27X27 %% t:* %D
diff --git a/tests/arch/intel_alm/mux.ys b/tests/arch/intel_alm/mux.ys
index 20969ead35f..951b0eff6b4 100644
--- a/tests/arch/intel_alm/mux.ys
+++ b/tests/arch/intel_alm/mux.ys
@@ -11,16 +11,6 @@ select -assert-count 1 t:MISTRAL_ALUT3
 select -assert-none t:MISTRAL_ALUT3 %% t:* %D
 
 
-design -load read
-hierarchy -top mux2
-proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux2 # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_ALUT3
-select -assert-none t:MISTRAL_ALUT3 %% t:* %D
-
-
 design -load read
 hierarchy -top mux4
 proc
@@ -31,16 +21,6 @@ select -assert-count 1 t:MISTRAL_ALUT6
 select -assert-none t:MISTRAL_ALUT6 %% t:* %D
 
 
-design -load read
-hierarchy -top mux4
-proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux4 # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_ALUT6
-select -assert-none t:MISTRAL_ALUT6 %% t:* %D
-
-
 design -load read
 hierarchy -top mux8
 proc
@@ -52,17 +32,6 @@ select -assert-count 2 t:MISTRAL_ALUT6
 select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
 
 
-design -load read
-hierarchy -top mux8
-proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_ALUT3
-select -assert-count 2 t:MISTRAL_ALUT6
-select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
-
-
 design -load read
 hierarchy -top mux16
 proc
@@ -74,15 +43,3 @@ select -assert-max 2 t:MISTRAL_ALUT5
 select -assert-max 5 t:MISTRAL_ALUT6
 select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
 
-
-design -load read
-hierarchy -top mux16
-proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux16 # Constrain all select calls below inside the top module
-select -assert-max 1 t:MISTRAL_ALUT3
-select -assert-max 2 t:MISTRAL_ALUT5
-select -assert-max 5 t:MISTRAL_ALUT6
-
-select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
diff --git a/tests/arch/intel_alm/quartus_ice.ys b/tests/arch/intel_alm/quartus_ice.ys
deleted file mode 100644
index 4e1896b82a8..00000000000
--- a/tests/arch/intel_alm/quartus_ice.ys
+++ /dev/null
@@ -1,26 +0,0 @@
-read_verilog <<EOT
-// Verilog has syntax for raw identifiers, where you start it with \ and end it with a space.
-// This test crashes Quartus due to it parsing \a[10] as a wire slice and not a raw identifier.
-module top();
-  (* keep *) wire [31:0] \a[10] ;
-  (* keep *) wire b;
-  assign b = \a[10] [31];
-endmodule
-EOT
-
-synth_intel_alm -family cyclonev -quartus
-select -assert-none w:*[* w:*]*
-
-design -reset
-read_verilog <<EOT
-// Verilog has syntax for raw identifiers, where you start it with \ and end it with a space.
-// This test crashes Quartus due to it parsing \a[10] as a wire slice and not a raw identifier.
-module top();
-  (* keep *) wire [31:0] \a[10] ;
-  (* keep *) wire b;
-  assign b = \a[10] [31];
-endmodule
-EOT
-
-synth_intel_alm -family cyclone10gx -quartus -noiopad -noclkbuf
-select -assert-none w:*[* w:*]*
diff --git a/tests/arch/intel_alm/shifter.ys b/tests/arch/intel_alm/shifter.ys
index 77ff9889658..da10c82d734 100644
--- a/tests/arch/intel_alm/shifter.ys
+++ b/tests/arch/intel_alm/shifter.ys
@@ -8,14 +8,3 @@ cd top # Constrain all select calls below inside the top module
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_FF %% t:* %D
 
-
-design -reset
-read_verilog ../common/shifter.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 8 t:MISTRAL_FF
-select -assert-none t:MISTRAL_FF %% t:* %D
diff --git a/tests/arch/intel_alm/tribuf.ys b/tests/arch/intel_alm/tribuf.ys
index fb5fecb7855..96dde1c9da7 100644
--- a/tests/arch/intel_alm/tribuf.ys
+++ b/tests/arch/intel_alm/tribuf.ys
@@ -11,17 +11,3 @@ cd tristate # Constrain all select calls below inside the top module
 select -assert-count 1 t:$_TBUF_
 select -assert-none t:$_TBUF_ %% t:* %D
 
-
-design -reset
-read_verilog ../common/tribuf.v
-hierarchy -top tristate
-proc
-tribuf
-flatten
-synth
-equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd tristate # Constrain all select calls below inside the top module
-#Internal cell type used. Need support it.
-select -assert-count 1 t:$_TBUF_
-select -assert-none t:$_TBUF_ %% t:* %D

From fc82251105324ea14e10b6738cbaffe5e68c3588 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Wed, 10 Apr 2024 14:17:57 +0200
Subject: [PATCH 006/499] techmap: Support dynamic cell types

---
 kernel/constids.inc       | 2 ++
 passes/techmap/techmap.cc | 7 +++++++
 2 files changed, 9 insertions(+)

diff --git a/kernel/constids.inc b/kernel/constids.inc
index 7db21debb0e..00db94af441 100644
--- a/kernel/constids.inc
+++ b/kernel/constids.inc
@@ -222,6 +222,8 @@ X(_TECHMAP_REPLACE_)
 X(techmap_simplemap)
 X(_techmap_special_)
 X(techmap_wrap)
+X(_TECHMAP_PLACEHOLDER_)
+X(techmap_chtype)
 X(T_FALL_MAX)
 X(T_FALL_MIN)
 X(T_FALL_TYP)
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index db395315ce6..eda7c2f6c3b 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -336,6 +336,9 @@ struct TechmapWorker
 
 			if (c->type.begins_with("\\$"))
 				c->type = c->type.substr(1);
+			
+			if (c->type == ID::_TECHMAP_PLACEHOLDER_ && tpl_cell->has_attribute(ID::techmap_chtype))
+				c->type = RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype));
 
 			vector<IdString> autopurge_ports;
 
@@ -1135,6 +1138,10 @@ struct TechmapPass : public Pass {
 		log("new wire alias to be created and named as above but with the `_TECHMAP_REPLACE_'\n");
 		log("prefix also substituted.\n");
 		log("\n");
+		log("A cell with the type _TECHMAP_PLACEHOLDER_ in the map file will have its type\n");
+		log("changed to the content of the techmap_chtype attribute. This allows for choosing\n");
+		log("the cell type dynamically.\n");
+		log("\n");
 		log("See 'help extract' for a pass that does the opposite thing.\n");
 		log("\n");
 		log("See 'help flatten' for a pass that does flatten the design (which is\n");

From 6ff4ecb2b42b8df40c2c44051159d53bf9eea65b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Wed, 10 Apr 2024 18:32:27 +0200
Subject: [PATCH 007/499] techmap: Remove `techmap_chtype` from the result

---
 passes/techmap/techmap.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index eda7c2f6c3b..64de3a1cac0 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -337,8 +337,10 @@ struct TechmapWorker
 			if (c->type.begins_with("\\$"))
 				c->type = c->type.substr(1);
 			
-			if (c->type == ID::_TECHMAP_PLACEHOLDER_ && tpl_cell->has_attribute(ID::techmap_chtype))
+			if (c->type == ID::_TECHMAP_PLACEHOLDER_ && tpl_cell->has_attribute(ID::techmap_chtype)) {
 				c->type = RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype));
+				c->attributes.erase(ID::techmap_chtype);
+			}
 
 			vector<IdString> autopurge_ports;
 

From a833f050364c959c2eebc039c019a3df8d420825 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Thu, 2 May 2024 23:49:50 +0200
Subject: [PATCH 008/499] techmap: add dynamic cell type test

---
 tests/techmap/techmap_chtype.ys | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 tests/techmap/techmap_chtype.ys

diff --git a/tests/techmap/techmap_chtype.ys b/tests/techmap/techmap_chtype.ys
new file mode 100644
index 00000000000..7c339842013
--- /dev/null
+++ b/tests/techmap/techmap_chtype.ys
@@ -0,0 +1,33 @@
+read_verilog <<EOT
+
+(* techmap_celltype="foo" *)
+module _80_lcu_primitive(P, G, CI, CO);
+	parameter WIDTH = 10;
+
+	(* force_downto *)
+	input wire [WIDTH-1:0] P;
+	(* force_downto *)
+	input wire [WIDTH-1:0] G;
+	input wire CI;
+	(* force_downto *)
+	output wire [WIDTH-1:0] CO;
+
+	(* techmap_chtype=$sformatf("LCU_%0d", WIDTH) *)
+	_TECHMAP_PLACEHOLDER_ #(.WIDTH(WIDTH)) _TECHMAP_REPLACE_(.P(P), .G(G), .CI(CI), .CO(CO));
+endmodule
+
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+module top(input [3:0] pi, input [3:0] gi, input ci, output [3:0] co);
+foo #(.WIDTH(8)) suuuub(pi, gi, ci, co);
+endmodule
+EOT
+
+hierarchy -auto-top
+proc
+opt
+techmap -map %techmap
+
+select -assert-count 1 t:LCU_8

From 86e1080f05d6ab999e7fd393b81ba10aa9231c7f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Wed, 27 Mar 2024 23:54:51 +0100
Subject: [PATCH 009/499] cellmatch: New pass

---
 passes/techmap/Makefile.inc |   1 +
 passes/techmap/cellmatch.cc | 340 ++++++++++++++++++++++++++++++++++++
 2 files changed, 341 insertions(+)
 create mode 100644 passes/techmap/cellmatch.cc

diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index 9d57e3d71af..74813bca93f 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -48,6 +48,7 @@ OBJS += passes/techmap/dfflegalize.o
 OBJS += passes/techmap/dffunmap.o
 OBJS += passes/techmap/flowmap.o
 OBJS += passes/techmap/extractinv.o
+OBJS += passes/techmap/cellmatch.o
 endif
 
 ifeq ($(DISABLE_SPAWN),0)
diff --git a/passes/techmap/cellmatch.cc b/passes/techmap/cellmatch.cc
new file mode 100644
index 00000000000..7c75418e3bc
--- /dev/null
+++ b/passes/techmap/cellmatch.cc
@@ -0,0 +1,340 @@
+#include "kernel/celltypes.h"
+#include "kernel/register.h"
+#include "kernel/rtlil.h"
+#include "kernel/sigtools.h"
+#include "kernel/utils.h"
+
+#include <algorithm>
+
+USING_YOSYS_NAMESPACE
+YOSYS_NAMESPACE_BEGIN
+
+// return module's inputs in canonical order
+SigSpec module_inputs(Module *m)
+{
+	SigSpec ret;
+	for (auto port : m->ports) {
+		Wire *w = m->wire(port);
+		if (!w->port_input)
+			continue;
+		if (w->width != 1)
+			log_error("Unsupported wide port (%s) of non-unit width found in module %s.\n",
+					  log_id(w), log_id(m));
+		ret.append(w);
+	}
+	return ret;
+}
+
+// return module's outputs in canonical order
+SigSpec module_outputs(Module *m)
+{
+	SigSpec ret;
+	for (auto port : m->ports) {
+		Wire *w = m->wire(port);
+		if (!w->port_output)
+			continue;
+		if (w->width != 1)
+			log_error("Unsupported wide port (%s) of non-unit width found in module %s.\n",
+					  log_id(w), log_id(m));
+		ret.append(w);
+	}
+	return ret;
+}
+
+uint64_t permute_lut(uint64_t lut, const std::vector<int> &varmap)
+{
+	int k = varmap.size();
+	uint64_t ret = 0;
+	for (int j = 0; j < 1 << k; j++) {
+		int m = 0;
+		for (int l = 0; l < k; l++)
+		if (j & 1 << l)
+			m |= 1 << varmap[l];
+		if (lut & 1 << m)
+			ret |= 1 << j;
+	}
+	return ret;
+}
+
+uint64_t p_class(int k, uint64_t lut)
+{
+	std::vector<int> map;
+	for (int j = 0; j < k; j++)
+		map.push_back(j);
+
+	uint64_t repr = ~(uint64_t) 0;
+	std::vector<int> repr_vars;
+	while (true) {
+		uint64_t perm = permute_lut(lut, map);
+		if (perm <= repr) {
+			repr = perm;
+			repr_vars = map;
+		}
+		if (!std::next_permutation(map.begin(), map.end()))
+			break;
+	}
+	return repr;
+}
+
+bool derive_module_luts(Module *m, std::vector<uint64_t> &luts)
+{
+	SigMap sigmap(m);
+	CellTypes ff_types;
+	ff_types.setup_stdcells_mem();
+
+	dict<SigBit, Cell*> driver;
+	for (auto cell : m->selected_cells()) {
+		if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
+			continue;
+
+		if (ff_types.cell_known(cell->type)) {
+			log("Ignoring module '%s' which isn't purely combinational.\n", log_id(m));
+			return false;
+		}
+
+		if (!cell->type.in(ID($_NOT_), ID($_AND_)))
+			log_error("Unsupported cell in module '%s': %s of type %s\n",
+					  log_id(m), log_id(cell), log_id(cell->type));
+
+		driver[sigmap(cell->getPort(ID::Y))] = cell;
+	}
+
+	TopoSort<Cell*> sort;
+	for (auto cell : m->cells())
+	if (cell->type.in(ID($_NOT_), ID($_AND_))) {
+		sort.node(cell);
+		SigSpec inputs = cell->type == ID($_AND_)
+				? SigSpec({cell->getPort(ID::B), cell->getPort(ID::A)})
+				: cell->getPort(ID::A);
+		for (auto bit : sigmap(inputs))
+		if (driver.count(bit))
+			sort.edge(driver.at(bit), cell);
+	}
+
+	if (!sort.sort())
+		log_error("Module %s contains combinational loops.\n", log_id(m));
+
+	dict<SigBit, uint64_t> states;
+	states[State::S0] = 0;
+	states[State::S1] = ~(uint64_t) 1;
+
+	{
+		uint64_t sieves[6] = {
+			0xaaaaaaaaaaaaaaaa,
+			0xcccccccccccccccc,
+			0xf0f0f0f0f0f0f0f0,
+			0xff00ff00ff00ff00,
+			0xffff0000ffff0000,
+			0xffffffff00000000,
+		};
+
+		SigSpec inputs = sigmap(module_inputs(m));
+		if (inputs.size() > 6) {
+			log_warning("Skipping module %s with more than 6 inputs bits.\n", log_id(m));
+			return false;
+		}
+
+		for (int i = 0; i < inputs.size(); i++)
+			states[inputs[i]] = sieves[i] & ((((uint64_t) 1) << (1 << inputs.size())) - 1);
+	}
+
+	for (auto cell : sort.sorted) {
+		if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
+			continue;
+
+		if (cell->type == ID($_AND_)) {
+			SigSpec a = sigmap(cell->getPort(ID::A));
+			SigSpec b = sigmap(cell->getPort(ID::B));
+			if (!states.count(a) || !states.count(b))
+				log_error("Cell %s in module %s sources an undriven wire!",
+						  log_id(cell), log_id(m));
+			states[sigmap(cell->getPort(ID::Y))] = \
+				states.at(a) & states.at(b);
+		} else if (cell->type == ID($_NOT_)) {
+			SigSpec a = sigmap(cell->getPort(ID::A));
+			if (!states.count(a))
+				log_error("Cell %s in module %s sources an undriven wire!",
+						  log_id(cell), log_id(m));
+			states[sigmap(cell->getPort(ID::Y))] = ~states.at(a);
+		} else {
+			log_abort();
+		}
+	}
+
+	for (auto bit : module_outputs(m)) {
+		if (!states.count(sigmap(bit)))
+			log_error("Output port %s in module %s is undriven!",
+					  log_signal(bit), log_id(m));
+		luts.push_back(states.at(sigmap(bit)));
+	}
+	return true;
+}
+
+struct CellmatchPass : Pass {
+	CellmatchPass() : Pass("cellmatch", "match cells to their targets in cell library") {}
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    cellmatch -lib <design> [module selection]\n");
+		log("\n");
+		log("This pass identifies functionally equivalent counterparts between each of the\n");
+		log("selected modules and a module from the secondary design <design>. For every such\n");
+		log("correspondence found, a techmap rule is generated for mapping instances of the\n");
+		log("former to instances of the latter. This techmap rule is saved in yet another\n");
+		log("design called '$cellmatch_map', which is created if non-existent.\n");
+		log("\n");
+		log("This pass restricts itself to combinational modules which must be modeled with an\n");
+		log("and-inverter graph. Run 'aigmap' first if necessary. Modules are functionally\n");
+		log("equivalent as long as their truth tables are identical upto a permutation of\n");
+		log("inputs and outputs. The number of inputs is limited to 6.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *d) override
+	{
+		log_header(d, "Executing CELLMATCH pass. (match cells)\n");
+
+		size_t argidx;
+		bool lut_attrs = false;
+		Design *lib = NULL;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-lut_attrs") {
+				// an undocumented debugging option
+				lut_attrs = true;
+			} else if (args[argidx] == "-lib" && argidx + 1 < args.size()) {
+				if (!saved_designs.count(args[++argidx]))
+					log_cmd_error("No design '%s' found!\n", args[argidx].c_str());
+				lib = saved_designs.at(args[argidx]);
+			} else {
+				break;
+			}
+		}
+		extra_args(args, argidx, d);
+
+		if (!lib && !lut_attrs)
+			log_cmd_error("Missing required -lib option.\n");
+
+		struct Target {
+			Module *module;
+			std::vector<uint64_t> luts;
+		};
+
+		dict<pool<uint64_t>, std::vector<Target>> targets;
+
+		if (lib)
+		for (auto m : lib->modules()) {
+			pool<uint64_t> p_classes;
+
+			// produce a fingerprint in p_classes
+			int ninputs = module_inputs(m).size();
+			std::vector<uint64_t> luts;
+			if (!derive_module_luts(m, luts))
+				continue;
+			for (auto lut : luts)
+				p_classes.insert(p_class(ninputs, lut));
+
+			// save as a viable target
+			targets[p_classes].push_back(Target{m, luts});
+		}
+
+		auto r = saved_designs.emplace("$cellmatch_map", nullptr);
+		if (r.second)
+			r.first->second = new Design;
+		Design *map_design = r.first->second;
+
+		for (auto m : d->selected_whole_modules_warn()) {
+			std::vector<uint64_t> luts;
+			if (!derive_module_luts(m, luts))
+				continue;
+
+			SigSpec inputs = module_inputs(m);
+			SigSpec outputs = module_outputs(m);
+
+			if (lut_attrs) {
+				int no = 0;
+				for (auto bit : outputs) {
+					log_assert(bit.is_wire());
+					bit.wire->attributes[ID(p_class)] = p_class(inputs.size(), luts[no]);
+					bit.wire->attributes[ID(lut)] = luts[no++];	
+				}
+			}
+
+			// fingerprint
+			pool<uint64_t> p_classes;
+			for (auto lut : luts)
+				p_classes.insert(p_class(inputs.size(), lut));
+
+			for (auto target : targets[p_classes]) {
+				log_debug("Candidate %s for matching to %s\n", log_id(target.module), log_id(m));
+
+				SigSpec target_inputs = module_inputs(target.module);
+				SigSpec target_outputs = module_outputs(target.module);
+
+				if (target_inputs.size() != inputs.size())
+					continue;
+
+				if (target_outputs.size() != outputs.size())
+					continue;
+
+				std::vector<int> input_map;
+				for (int i = 0; i < inputs.size(); i++)
+					input_map.push_back(i);
+
+				bool found_match = false;
+				while (!found_match) {
+					std::vector<int> output_map;
+					for (int i = 0; i < outputs.size(); i++)
+						output_map.push_back(i);
+
+					while (!found_match) {
+						int out_no = 0;
+						bool match = true;
+						for (auto lut : luts) {
+							if (permute_lut(target.luts[output_map[out_no++]], input_map) != lut) {
+								match = false;
+								break;
+							}
+						}
+
+						if (match) {
+							log("Module %s matches %s\n", log_id(m), log_id(target.module));
+							Module *map = map_design->addModule(stringf("\\_60_%s_%s", log_id(m), log_id(target.module)));
+							Cell *cell = map->addCell(ID::_TECHMAP_REPLACE_, target.module->name);
+
+							map->attributes[ID(techmap_celltype)] = m->name.str();
+
+							for (int i = 0; i < outputs.size(); i++) {
+								log_assert(outputs[i].is_wire());
+								Wire *w = map->addWire(outputs[i].wire->name, 1);
+								w->port_id = outputs[i].wire->port_id;
+								w->port_output = true;
+								log_assert(target_outputs[output_map[i]].is_wire());
+								cell->setPort(target_outputs[output_map[i]].wire->name, w);
+							}
+
+							for (int i = 0; i < inputs.size(); i++) {
+								log_assert(inputs[i].is_wire());
+								Wire *w = map->addWire(inputs[i].wire->name, 1);
+								w->port_id = inputs[i].wire->port_id;
+								w->port_input = true;
+								log_assert(target_inputs[input_map[i]].is_wire());
+								cell->setPort(target_inputs[input_map[i]].wire->name, w);
+							}
+
+							map->fixup_ports();
+							found_match = true;
+						}
+
+						if (!std::next_permutation(output_map.begin(), output_map.end()))
+							break;		
+					}
+
+					if (!std::next_permutation(input_map.begin(), input_map.end()))
+						break;
+				}
+			}
+		}
+	}
+} CellmatchPass;
+
+YOSYS_NAMESPACE_END

From 6a9858cdad96322ddca73d50602ce643c82edc04 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Sat, 13 Apr 2024 16:56:36 +0200
Subject: [PATCH 010/499] cellmatch: Delegate evaluation to `ConstEval`

---
 passes/techmap/cellmatch.cc | 107 ++++++++++--------------------------
 1 file changed, 30 insertions(+), 77 deletions(-)

diff --git a/passes/techmap/cellmatch.cc b/passes/techmap/cellmatch.cc
index 7c75418e3bc..9459c112fe7 100644
--- a/passes/techmap/cellmatch.cc
+++ b/passes/techmap/cellmatch.cc
@@ -2,6 +2,7 @@
 #include "kernel/register.h"
 #include "kernel/rtlil.h"
 #include "kernel/sigtools.h"
+#include "kernel/consteval.h"
 #include "kernel/utils.h"
 
 #include <algorithm>
@@ -78,95 +79,48 @@ uint64_t p_class(int k, uint64_t lut)
 
 bool derive_module_luts(Module *m, std::vector<uint64_t> &luts)
 {
-	SigMap sigmap(m);
 	CellTypes ff_types;
 	ff_types.setup_stdcells_mem();
-
-	dict<SigBit, Cell*> driver;
-	for (auto cell : m->selected_cells()) {
-		if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
-			continue;
-
+	for (auto cell : m->cells()) {
 		if (ff_types.cell_known(cell->type)) {
 			log("Ignoring module '%s' which isn't purely combinational.\n", log_id(m));
 			return false;
 		}
-
-		if (!cell->type.in(ID($_NOT_), ID($_AND_)))
-			log_error("Unsupported cell in module '%s': %s of type %s\n",
-					  log_id(m), log_id(cell), log_id(cell->type));
-
-		driver[sigmap(cell->getPort(ID::Y))] = cell;
 	}
 
-	TopoSort<Cell*> sort;
-	for (auto cell : m->cells())
-	if (cell->type.in(ID($_NOT_), ID($_AND_))) {
-		sort.node(cell);
-		SigSpec inputs = cell->type == ID($_AND_)
-				? SigSpec({cell->getPort(ID::B), cell->getPort(ID::A)})
-				: cell->getPort(ID::A);
-		for (auto bit : sigmap(inputs))
-		if (driver.count(bit))
-			sort.edge(driver.at(bit), cell);
-	}
-
-	if (!sort.sort())
-		log_error("Module %s contains combinational loops.\n", log_id(m));
-
-	dict<SigBit, uint64_t> states;
-	states[State::S0] = 0;
-	states[State::S1] = ~(uint64_t) 1;
-
-	{
-		uint64_t sieves[6] = {
-			0xaaaaaaaaaaaaaaaa,
-			0xcccccccccccccccc,
-			0xf0f0f0f0f0f0f0f0,
-			0xff00ff00ff00ff00,
-			0xffff0000ffff0000,
-			0xffffffff00000000,
-		};
-
-		SigSpec inputs = sigmap(module_inputs(m));
-		if (inputs.size() > 6) {
-			log_warning("Skipping module %s with more than 6 inputs bits.\n", log_id(m));
-			return false;
-		}
+	SigSpec inputs = module_inputs(m);
+	SigSpec outputs = module_outputs(m);
+	int ninputs = inputs.size(), noutputs = outputs.size();
 
-		for (int i = 0; i < inputs.size(); i++)
-			states[inputs[i]] = sieves[i] & ((((uint64_t) 1) << (1 << inputs.size())) - 1);
+	if (ninputs > 6) {
+		log_warning("Skipping module %s with more than 6 inputs bits.\n", log_id(m));
+		return false;
 	}
 
-	for (auto cell : sort.sorted) {
-		if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
-			continue;
+	luts.clear();
+	luts.resize(noutputs);
+
+	ConstEval ceval(m);
+	for (int i = 0; i < 1 << ninputs; i++) {
+		ceval.clear();
+		for (int j = 0; j < ninputs; j++)
+			ceval.set(inputs[j], (i & (1 << j)) ? State::S1 : State::S0);
+		for (int j = 0; j < noutputs; j++) {
+			SigSpec bit = outputs[j];
+
+			if (!ceval.eval(bit)) {
+				log("Failed to evaluate output '%s' in module '%s'.\n",
+					log_signal(outputs[j]), log_id(m));
+				return false;
+			}
 
-		if (cell->type == ID($_AND_)) {
-			SigSpec a = sigmap(cell->getPort(ID::A));
-			SigSpec b = sigmap(cell->getPort(ID::B));
-			if (!states.count(a) || !states.count(b))
-				log_error("Cell %s in module %s sources an undriven wire!",
-						  log_id(cell), log_id(m));
-			states[sigmap(cell->getPort(ID::Y))] = \
-				states.at(a) & states.at(b);
-		} else if (cell->type == ID($_NOT_)) {
-			SigSpec a = sigmap(cell->getPort(ID::A));
-			if (!states.count(a))
-				log_error("Cell %s in module %s sources an undriven wire!",
-						  log_id(cell), log_id(m));
-			states[sigmap(cell->getPort(ID::Y))] = ~states.at(a);
-		} else {
-			log_abort();
+			log_assert(ceval.eval(bit));
+
+			if (bit[0] == State::S1)
+				luts[j] |= 1 << i;
 		}
 	}
 
-	for (auto bit : module_outputs(m)) {
-		if (!states.count(sigmap(bit)))
-			log_error("Output port %s in module %s is undriven!",
-					  log_signal(bit), log_id(m));
-		luts.push_back(states.at(sigmap(bit)));
-	}
 	return true;
 }
 
@@ -184,10 +138,9 @@ struct CellmatchPass : Pass {
 		log("former to instances of the latter. This techmap rule is saved in yet another\n");
 		log("design called '$cellmatch_map', which is created if non-existent.\n");
 		log("\n");
-		log("This pass restricts itself to combinational modules which must be modeled with an\n");
-		log("and-inverter graph. Run 'aigmap' first if necessary. Modules are functionally\n");
+		log("This pass restricts itself to combinational modules. Modules are functionally\n");
 		log("equivalent as long as their truth tables are identical upto a permutation of\n");
-		log("inputs and outputs. The number of inputs is limited to 6.\n");
+		log("inputs and outputs. The supported number of inputs is limited to 6.\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *d) override

From c0e68dcc4d232542272d1ad436767175a6f04481 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Sat, 13 Apr 2024 16:56:44 +0200
Subject: [PATCH 011/499] cellmatch: Add debug print

---
 passes/techmap/cellmatch.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/passes/techmap/cellmatch.cc b/passes/techmap/cellmatch.cc
index 9459c112fe7..5301cc99bfd 100644
--- a/passes/techmap/cellmatch.cc
+++ b/passes/techmap/cellmatch.cc
@@ -185,6 +185,8 @@ struct CellmatchPass : Pass {
 				continue;
 			for (auto lut : luts)
 				p_classes.insert(p_class(ninputs, lut));
+			
+			log_debug("Registered %s\n", log_id(m));
 
 			// save as a viable target
 			targets[p_classes].push_back(Target{m, luts});

From 913bc87c4419303e32f4ca86ed437fe1e8ee015e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Sat, 13 Apr 2024 17:12:53 +0200
Subject: [PATCH 012/499] cellmatch: Add test

---
 tests/techmap/cellmatch.ys | 79 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 79 insertions(+)
 create mode 100644 tests/techmap/cellmatch.ys

diff --git a/tests/techmap/cellmatch.ys b/tests/techmap/cellmatch.ys
new file mode 100644
index 00000000000..46960fc1430
--- /dev/null
+++ b/tests/techmap/cellmatch.ys
@@ -0,0 +1,79 @@
+read_verilog <<EOF
+module bufgate(A, Y);
+	input wire A;
+	output wire Y = A;
+endmodule
+
+module reducegate(A, B, C, X, Y);
+	input wire A;
+	input wire B;
+	input wire C;
+	output wire X = &{A, B, C};
+	output wire Y = |{A, B, C};
+endmodule
+
+module fagate(A, B, C, X, Y);
+	input wire A;
+	input wire B;
+	input wire C;
+	wire t1 = A ^ B;
+	wire t2 = A & B;
+	wire t3 = C & t1;
+	output wire X = t1 ^ C;
+	output wire Y = t2 | t3;
+endmodule
+EOF
+design -stash gatelib
+
+read_verilog <<EOF
+module ripple_carry(A, B, Y);
+	parameter WIDTH = 4;
+
+	input wire [WIDTH-1:0] A;
+	input wire [WIDTH-1:0] B;
+	output wire [WIDTH-1:0] Y;
+
+	wire [WIDTH:0] carry;
+	assign carry[0] = 0;
+
+	generate
+		genvar i;
+
+		for (i = 0; i < WIDTH; i = i + 1) begin
+			FA fa(
+				.A(A[i]),
+				.B(B[i]), .Y(Y[i]),
+				.CI(carry[i]), .CO(carry[i + 1]),
+			);
+		end
+	endgenerate
+endmodule
+
+(* gate *)
+module FA(A, B, CI, CO, Y);
+	input wire A, B, CI;
+	output wire CO, Y;
+	assign {CO, Y} = A + B + CI;
+endmodule
+EOF
+
+prep
+cellmatch -lib gatelib FA A:gate
+
+design -save gold
+techmap -map %$cellmatch_map
+design -save gate
+
+select -assert-none ripple_carry/t:FA
+
+design -reset
+design -copy-from gold -as gold ripple_carry
+design -copy-from gate -as gate ripple_carry
+opt_clean
+equiv_make gold gate equiv
+hierarchy -top equiv
+flatten
+opt_clean
+equiv_induct equiv
+equiv_status -assert
+

From b143e5678fae9d48caa70f6ee4a1f67bb45bf31b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Sat, 13 Apr 2024 17:20:32 +0200
Subject: [PATCH 013/499] cellmatch: Rename the special design to `$cellmatch`

---
 passes/techmap/cellmatch.cc | 4 ++--
 tests/techmap/cellmatch.ys  | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/passes/techmap/cellmatch.cc b/passes/techmap/cellmatch.cc
index 5301cc99bfd..d1da6babd63 100644
--- a/passes/techmap/cellmatch.cc
+++ b/passes/techmap/cellmatch.cc
@@ -136,7 +136,7 @@ struct CellmatchPass : Pass {
 		log("selected modules and a module from the secondary design <design>. For every such\n");
 		log("correspondence found, a techmap rule is generated for mapping instances of the\n");
 		log("former to instances of the latter. This techmap rule is saved in yet another\n");
-		log("design called '$cellmatch_map', which is created if non-existent.\n");
+		log("design called '$cellmatch', which is created if non-existent.\n");
 		log("\n");
 		log("This pass restricts itself to combinational modules. Modules are functionally\n");
 		log("equivalent as long as their truth tables are identical upto a permutation of\n");
@@ -192,7 +192,7 @@ struct CellmatchPass : Pass {
 			targets[p_classes].push_back(Target{m, luts});
 		}
 
-		auto r = saved_designs.emplace("$cellmatch_map", nullptr);
+		auto r = saved_designs.emplace("$cellmatch", nullptr);
 		if (r.second)
 			r.first->second = new Design;
 		Design *map_design = r.first->second;
diff --git a/tests/techmap/cellmatch.ys b/tests/techmap/cellmatch.ys
index 46960fc1430..bea2f598d94 100644
--- a/tests/techmap/cellmatch.ys
+++ b/tests/techmap/cellmatch.ys
@@ -61,7 +61,7 @@ prep
 cellmatch -lib gatelib FA A:gate
 
 design -save gold
-techmap -map %$cellmatch_map
+techmap -map %$cellmatch
 design -save gate
 
 select -assert-none ripple_carry/t:FA

From e939182e68edc26b4267f011f644067e29c7c25a Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 3 May 2024 12:11:55 +0200
Subject: [PATCH 014/499] cellmatch: add comments

---
 passes/techmap/cellmatch.cc | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/passes/techmap/cellmatch.cc b/passes/techmap/cellmatch.cc
index d1da6babd63..a21a4fbadc2 100644
--- a/passes/techmap/cellmatch.cc
+++ b/passes/techmap/cellmatch.cc
@@ -42,10 +42,16 @@ SigSpec module_outputs(Module *m)
 	return ret;
 }
 
+// Permute the inputs of a single-output k-LUT according to varmap
 uint64_t permute_lut(uint64_t lut, const std::vector<int> &varmap)
 {
 	int k = varmap.size();
 	uint64_t ret = 0;
+	// Index j iterates over all bits in lut.
+	// When (j & 1 << n) is true,
+	//  (lut & 1 << j) represents an output value where input var n is set.
+	// We use this fact to permute the LUT such that
+	// every variable n is remapped to varmap[n].
 	for (int j = 0; j < 1 << k; j++) {
 		int m = 0;
 		for (int l = 0; l < k; l++)
@@ -57,6 +63,10 @@ uint64_t permute_lut(uint64_t lut, const std::vector<int> &varmap)
 	return ret;
 }
 
+// Find the LUT with the minimum integer representation
+// such that it is a permutation of the given lut.
+// The resulting LUT becomes the "fingerprint" of the "permutation class".
+// This function checks all possible input permutations.
 uint64_t p_class(int k, uint64_t lut)
 {
 	std::vector<int> map;
@@ -77,6 +87,9 @@ uint64_t p_class(int k, uint64_t lut)
 	return repr;
 }
 
+// Represent module m as N single-output k-LUTs
+// where k is the number of module inputs,
+//   and N is the number of module outputs.
 bool derive_module_luts(Module *m, std::vector<uint64_t> &luts)
 {
 	CellTypes ff_types;
@@ -185,7 +198,7 @@ struct CellmatchPass : Pass {
 				continue;
 			for (auto lut : luts)
 				p_classes.insert(p_class(ninputs, lut));
-			
+
 			log_debug("Registered %s\n", log_id(m));
 
 			// save as a viable target
@@ -210,7 +223,7 @@ struct CellmatchPass : Pass {
 				for (auto bit : outputs) {
 					log_assert(bit.is_wire());
 					bit.wire->attributes[ID(p_class)] = p_class(inputs.size(), luts[no]);
-					bit.wire->attributes[ID(lut)] = luts[no++];	
+					bit.wire->attributes[ID(lut)] = luts[no++];
 				}
 			}
 
@@ -236,11 +249,13 @@ struct CellmatchPass : Pass {
 					input_map.push_back(i);
 
 				bool found_match = false;
+				// For each input_map
 				while (!found_match) {
 					std::vector<int> output_map;
 					for (int i = 0; i < outputs.size(); i++)
 						output_map.push_back(i);
 
+					// For each output_map
 					while (!found_match) {
 						int out_no = 0;
 						bool match = true;
@@ -253,6 +268,8 @@ struct CellmatchPass : Pass {
 
 						if (match) {
 							log("Module %s matches %s\n", log_id(m), log_id(target.module));
+							// Add target.module to map_design ("$cellmatch")
+							// as a techmap rule to match m and replace it with target.module
 							Module *map = map_design->addModule(stringf("\\_60_%s_%s", log_id(m), log_id(target.module)));
 							Cell *cell = map->addCell(ID::_TECHMAP_REPLACE_, target.module->name);
 
@@ -281,7 +298,7 @@ struct CellmatchPass : Pass {
 						}
 
 						if (!std::next_permutation(output_map.begin(), output_map.end()))
-							break;		
+							break;
 					}
 
 					if (!std::next_permutation(input_map.begin(), input_map.end()))

From 4c000d3aba7ab080a95ed0a4b3de5c756f69646b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Wed, 10 Apr 2024 15:20:01 +0200
Subject: [PATCH 015/499] Add new `bbox_derive` command for blackbox derivation

---
 passes/cmds/Makefile.inc   |  1 +
 passes/cmds/bbox_derive.cc | 90 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 91 insertions(+)
 create mode 100644 passes/cmds/bbox_derive.cc

diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index d7e572462b0..b1c9c67f0d0 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -48,3 +48,4 @@ OBJS += passes/cmds/clean_zerowidth.o
 OBJS += passes/cmds/xprop.o
 OBJS += passes/cmds/dft_tag.o
 OBJS += passes/cmds/future.o
+OBJS += passes/cmds/bbox_derive.o
diff --git a/passes/cmds/bbox_derive.cc b/passes/cmds/bbox_derive.cc
new file mode 100644
index 00000000000..de0869cb1eb
--- /dev/null
+++ b/passes/cmds/bbox_derive.cc
@@ -0,0 +1,90 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Martin Povišer <povik@cutebit.org>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+#include "kernel/yosys.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct BboxDerivePass : Pass {
+	BboxDerivePass() : Pass("bbox_derive", "derive blackbox modules") {}
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    bbox_derive [-base <base_module>] [-naming_attr <attr>] [selection]\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *d) override
+	{
+		log_header(d, "Executing BBOX_DERIVE pass. (derive modules for blackboxes)\n");
+
+		size_t argidx;
+		IdString naming_attr;
+		IdString base_name;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-naming_attr" && argidx + 1 < args.size())
+				naming_attr = RTLIL::escape_id(args[++argidx]);
+			else if (args[argidx] == "-base" && argidx + 1 < args.size())
+				base_name = RTLIL::escape_id(args[++argidx]);
+			else
+				break;
+		}
+		extra_args(args, argidx, d);
+
+		Module *base_override;
+		if (!base_name.empty()) {
+			base_override = d->module(base_name);
+			if (!base_override)
+				log_cmd_error("Base module %s not found.\n", log_id(base_name));
+		}
+
+		dict<dict<RTLIL::IdString, RTLIL::Const>, Module*> done;
+
+		for (auto module : d->selected_modules()) {
+			for (auto cell : module->selected_cells()) {
+				Module *inst_module = d->module(cell->type);
+				if (!inst_module || !inst_module->get_blackbox_attribute())
+					continue;
+
+				if (cell->parameters.empty() || done.count(cell->parameters))
+					continue;
+
+				Module *base = inst_module;
+				if (base_override)
+					base = base_override;
+
+				IdString derived_type = base->derive(d, cell->parameters);
+				Module *derived = d->module(derived_type);
+
+				if (!naming_attr.empty() && derived->has_attribute(naming_attr)) {
+					IdString new_name = RTLIL::escape_id(derived->get_string_attribute(naming_attr));
+					if (!new_name.isPublic())
+						log_error("Derived module %s cannot be renamed to private name %s.\n",
+								  log_id(derived), log_id(new_name));
+					derived->attributes.erase(naming_attr);
+					d->rename(derived, new_name);
+				}
+
+				done[cell->parameters] = derived;
+			}
+		}
+	}
+} BboxDerivePass;
+
+PRIVATE_NAMESPACE_END

From e8c58a55280192db2c35006734f42c7983cd9b81 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 3 May 2024 20:41:42 +0200
Subject: [PATCH 016/499] bbox_derive: fix unininitialized memory UB when run
 with no named args

---
 passes/cmds/bbox_derive.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/cmds/bbox_derive.cc b/passes/cmds/bbox_derive.cc
index de0869cb1eb..758f793004a 100644
--- a/passes/cmds/bbox_derive.cc
+++ b/passes/cmds/bbox_derive.cc
@@ -47,7 +47,7 @@ struct BboxDerivePass : Pass {
 		}
 		extra_args(args, argidx, d);
 
-		Module *base_override;
+		Module *base_override = nullptr;
 		if (!base_name.empty()) {
 			base_override = d->module(base_name);
 			if (!base_override)

From 44b0fdc2bf8bac019641f4f5c5f9d29294fc0624 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 3 May 2024 20:43:01 +0200
Subject: [PATCH 017/499] bbox_derive: add assert and debug print

---
 passes/cmds/bbox_derive.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/passes/cmds/bbox_derive.cc b/passes/cmds/bbox_derive.cc
index 758f793004a..a35e9629058 100644
--- a/passes/cmds/bbox_derive.cc
+++ b/passes/cmds/bbox_derive.cc
@@ -71,6 +71,8 @@ struct BboxDerivePass : Pass {
 
 				IdString derived_type = base->derive(d, cell->parameters);
 				Module *derived = d->module(derived_type);
+				log_assert(derived && "Failed to derive module\n");
+				log_debug("derived %s\n", derived_type.c_str());
 
 				if (!naming_attr.empty() && derived->has_attribute(naming_attr)) {
 					IdString new_name = RTLIL::escape_id(derived->get_string_attribute(naming_attr));

From 0f9ee20ea2c9b377f9b28b862f77b197e6485e00 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Sat, 4 May 2024 00:16:00 +0000
Subject: [PATCH 018/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 2dbce272dc6..56efaf5eb0f 100644
--- a/Makefile
+++ b/Makefile
@@ -142,7 +142,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.40+45
+YOSYS_VER := 0.40+50
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From bb0be8c7a20335f8e03597cfcf052609f8a1f4a4 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Sat, 4 May 2024 16:51:29 +1200
Subject: [PATCH 019/499] Docs: Set release to YOSYS_VER

If building from read the docs, and the current build is "latest", add `-dev` to the version string.
Requires `YOSYS_VER` to be exported by .readthedocs.yaml.
---
 docs/source/conf.py | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/docs/source/conf.py b/docs/source/conf.py
index 29d36d9c45f..aed3fddff7c 100644
--- a/docs/source/conf.py
+++ b/docs/source/conf.py
@@ -63,6 +63,14 @@
 extensions.append('sphinx.ext.todo')
 todo_include_todos = False
 
+# attempt to get version
+env_yosys_ver = os.getenv("YOSYS_VER")
+if env_yosys_ver:
+    if os.getenv("READTHEDOCS") and os.getenv("READTHEDOCS_VERSION") == "latest":
+        release = env_yosys_ver + "-dev"
+    else:
+        release = env_yosys_ver
+
 # custom cmd-ref parsing/linking
 sys.path += [os.path.dirname(__file__) + "/../"]
 extensions.append('util.cmdref')

From fe27240b3a9c0be98dd16b3fc27cef61ddb50946 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Sat, 4 May 2024 16:51:38 +1200
Subject: [PATCH 020/499] Makefile: Export YOSYS_VER

---
 Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Makefile b/Makefile
index 56efaf5eb0f..2e93bcc8dc3 100644
--- a/Makefile
+++ b/Makefile
@@ -143,6 +143,7 @@ endif
 endif
 
 YOSYS_VER := 0.40+50
+export YOSYS_VER
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 6eb49ee9e830545e212f9aefe90d5bd130afa7a4 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 7 May 2024 10:23:22 +1200
Subject: [PATCH 021/499] Makefile: Export YOSYS_VER only for make docs

---
 Makefile | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index 2e93bcc8dc3..6711751b62d 100644
--- a/Makefile
+++ b/Makefile
@@ -143,7 +143,6 @@ endif
 endif
 
 YOSYS_VER := 0.40+50
-export YOSYS_VER
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -1013,7 +1012,7 @@ docs/reqs:
 
 DOC_TARGET ?= html
 docs: docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage docs/reqs
-	$(Q) $(MAKE) -C docs $(DOC_TARGET)
+	$(Q) YOSYS_VER=$(YOSYS_VER) $(MAKE) -C docs $(DOC_TARGET)
 
 clean:
 	rm -rf share

From b4034a881e0cf476bbdc19e984a9762bb260ad39 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 7 May 2024 15:35:25 +0200
Subject: [PATCH 022/499] Keep docs version in conf.py

---
 Makefile            |  2 +-
 docs/source/conf.py | 19 +++++++++----------
 2 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/Makefile b/Makefile
index 6711751b62d..56efaf5eb0f 100644
--- a/Makefile
+++ b/Makefile
@@ -1012,7 +1012,7 @@ docs/reqs:
 
 DOC_TARGET ?= html
 docs: docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage docs/reqs
-	$(Q) YOSYS_VER=$(YOSYS_VER) $(MAKE) -C docs $(DOC_TARGET)
+	$(Q) $(MAKE) -C docs $(DOC_TARGET)
 
 clean:
 	rm -rf share
diff --git a/docs/source/conf.py b/docs/source/conf.py
index aed3fddff7c..4e46cfad1b8 100644
--- a/docs/source/conf.py
+++ b/docs/source/conf.py
@@ -4,7 +4,8 @@
 
 project = 'YosysHQ Yosys'
 author = 'YosysHQ GmbH'
-copyright ='2022 YosysHQ GmbH'
+copyright ='2024 YosysHQ GmbH'
+yosys_ver = "0.40"
 
 # select HTML theme
 html_theme = 'furo'
@@ -46,12 +47,18 @@
 autosectionlabel_prefix_document = True
 autosectionlabel_maxdepth = 1
 
+# set version
+if os.getenv("READTHEDOCS") and os.getenv("READTHEDOCS_VERSION") == "latest":
+    release = yosys_ver + "-dev"
+else:
+    release = yosys_ver
+
 # assign figure numbers
 numfig = True
 
 bibtex_bibfiles = ['literature.bib']
-
 latex_elements = {
+        'releasename': ' ',
         'preamble': r'''
 \usepackage{lmodern}
 \usepackage{comment}
@@ -63,14 +70,6 @@
 extensions.append('sphinx.ext.todo')
 todo_include_todos = False
 
-# attempt to get version
-env_yosys_ver = os.getenv("YOSYS_VER")
-if env_yosys_ver:
-    if os.getenv("READTHEDOCS") and os.getenv("READTHEDOCS_VERSION") == "latest":
-        release = env_yosys_ver + "-dev"
-    else:
-        release = env_yosys_ver
-
 # custom cmd-ref parsing/linking
 sys.path += [os.path.dirname(__file__) + "/../"]
 extensions.append('util.cmdref')

From 71f2540cd840046499e1dd84c76ea64c437140d3 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 7 May 2024 15:55:52 +0200
Subject: [PATCH 023/499] docs conf.py change Release -> Version

---
 docs/source/conf.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/source/conf.py b/docs/source/conf.py
index 4e46cfad1b8..182d033f8ce 100644
--- a/docs/source/conf.py
+++ b/docs/source/conf.py
@@ -58,7 +58,7 @@
 
 bibtex_bibfiles = ['literature.bib']
 latex_elements = {
-        'releasename': ' ',
+        'releasename': 'Version',
         'preamble': r'''
 \usepackage{lmodern}
 \usepackage{comment}

From a52088b6af5c4467835de173d83a00645546eddf Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Tue, 7 May 2024 17:57:37 +0200
Subject: [PATCH 024/499] smtbmc: Improvements for --incremental and .yw fixes

This extends the experimental incremental JSON API to allow arbitrary
smtlib subexpressions, defining smtlib constants and to allow access of
signals by their .yw path.

It also fixes a bug during .yw writing where values would be re-emitted
in later cycles if they have no newer defined value and a potential
crash when using --track-assumes.
---
 backends/smt2/smtbmc.py             | 203 +++++++++++++++++-----------
 backends/smt2/smtbmc_incremental.py | 147 ++++++++++++++++++--
 backends/smt2/smtio.py              |  21 ++-
 3 files changed, 279 insertions(+), 92 deletions(-)

diff --git a/backends/smt2/smtbmc.py b/backends/smt2/smtbmc.py
index e6b4088dbd7..995a714c926 100644
--- a/backends/smt2/smtbmc.py
+++ b/backends/smt2/smtbmc.py
@@ -199,7 +199,6 @@ def help():
 
     --minimize-assumes
         when using --track-assumes, solve for a minimal set of sufficient assumptions.
-
 """ + so.helpmsg())
 
 def usage():
@@ -670,18 +669,12 @@ def print_msg(msg):
 
 ywfile_hierwitness_cache = None
 
-def ywfile_constraints(inywfile, constr_assumes, map_steps=None, skip_x=False):
+def ywfile_hierwitness():
     global ywfile_hierwitness_cache
-    if map_steps is None:
-        map_steps = {}
-
-    with open(inywfile, "r") as f:
-        inyw = ReadWitness(f)
-
-        if ywfile_hierwitness_cache is None:
-            ywfile_hierwitness_cache = smt.hierwitness(topmod, allregs=True, blackbox=True)
+    if ywfile_hierwitness_cache is None:
+        ywfile_hierwitness = smt.hierwitness(topmod, allregs=True, blackbox=True)
 
-        inits, seqs, clocks, mems = ywfile_hierwitness_cache
+        inits, seqs, clocks, mems = ywfile_hierwitness
 
         smt_wires = defaultdict(list)
         smt_mems = defaultdict(list)
@@ -692,91 +685,147 @@ def ywfile_constraints(inywfile, constr_assumes, map_steps=None, skip_x=False):
         for mem in mems:
             smt_mems[mem["path"]].append(mem)
 
-        addr_re = re.compile(r'\\\[[0-9]+\]$')
-        bits_re = re.compile(r'[01?]*$')
+        ywfile_hierwitness_cache = inits, seqs, clocks, mems, smt_wires, smt_mems
 
-        max_t = -1
+    return ywfile_hierwitness_cache
 
-        for t, step in inyw.steps():
-            present_signals, missing = step.present_signals(inyw.sigmap)
-            for sig in present_signals:
-                bits = step[sig]
-                if skip_x:
-                    bits = bits.replace('x', '?')
-                if not bits_re.match(bits):
-                    raise ValueError("unsupported bit value in Yosys witness file")
+def_bits_re = re.compile(r'([01]+)')
 
-                sig_end = sig.offset + len(bits)
-                if sig.path in smt_wires:
-                    for wire in smt_wires[sig.path]:
-                        width, offset = wire["width"], wire["offset"]
+def smt_extract_mask(smt_expr, mask):
+    chunks = []
+    def_bits = ''
 
-                        smt_bool = smt.net_width(topmod, wire["smtpath"]) == 1
+    mask_index_order = mask[::-1]
 
-                        offset = max(offset, 0)
+    for matched in def_bits_re.finditer(mask_index_order):
+        chunks.append(matched.span())
+        def_bits += matched[0]
 
-                        end = width + offset
-                        common_offset = max(sig.offset, offset)
-                        common_end = min(sig_end, end)
-                        if common_end <= common_offset:
-                            continue
+    if not chunks:
+        return
 
-                        smt_expr = smt.witness_net_expr(topmod, f"s{map_steps.get(t, t)}", wire)
+    if len(chunks) == 1:
+        start, end = chunks[0]
+        if start == 0 and end == len(mask_index_order):
+            combined_chunks = smt_expr
+        else:
+            combined_chunks = '((_ extract %d %d) %s)' % (end - 1, start, smt_expr)
+    else:
+        combined_chunks = '(let ((x %s)) (concat %s))' % (smt_expr, ' '.join(
+            '((_ extract %d %d) x)' % (end - 1, start)
+            for start, end in reversed(chunks)
+        ))
 
-                        if not smt_bool:
-                            slice_high = common_end - offset - 1
-                            slice_low = common_offset - offset
-                            smt_expr = "((_ extract %d %d) %s)" % (slice_high, slice_low, smt_expr)
+    return combined_chunks, ''.join(mask_index_order[start:end] for start, end in chunks)[::-1]
 
-                        bit_slice = bits[len(bits) - (common_end - sig.offset):len(bits) - (common_offset - sig.offset)]
+def smt_concat(exprs):
+    if not exprs:
+        return ""
+    if len(exprs) == 1:
+        return exprs[1]
+    return "(concat %s)" % ' '.join(exprs)
 
-                        if bit_slice.count("?") == len(bit_slice):
-                            continue
+def ywfile_signal(sig, step, mask=None):
+    assert sig.width > 0
 
-                        if smt_bool:
-                            assert width == 1
-                            smt_constr = "(= %s %s)" % (smt_expr, "true" if bit_slice == "1" else "false")
-                        else:
-                            if "?" in bit_slice:
-                                mask = bit_slice.replace("0", "1").replace("?", "0")
-                                bit_slice = bit_slice.replace("?", "0")
-                                smt_expr = "(bvand %s #b%s)" % (smt_expr, mask)
+    inits, seqs, clocks, mems, smt_wires, smt_mems = ywfile_hierwitness()
+    sig_end = sig.offset + sig.width
 
-                            smt_constr = "(= %s #b%s)" % (smt_expr, bit_slice)
+    output = []
 
-                        constr_assumes[t].append((inywfile, smt_constr))
+    if sig.path in smt_wires:
+        for wire in smt_wires[sig.path]:
+            width, offset = wire["width"], wire["offset"]
 
-                if sig.memory_path:
-                    if sig.memory_path in smt_mems:
-                        for mem in smt_mems[sig.memory_path]:
-                            width, size, bv = mem["width"], mem["size"], mem["statebv"]
+            smt_bool = smt.net_width(topmod, wire["smtpath"]) == 1
 
-                            smt_expr = smt.net_expr(topmod, f"s{map_steps.get(t, t)}", mem["smtpath"])
+            offset = max(offset, 0)
 
-                            if bv:
-                                word_low = sig.memory_addr * width
-                                word_high = word_low + width - 1
-                                smt_expr = "((_ extract %d %d) %s)" % (word_high, word_low, smt_expr)
-                            else:
-                                addr_width = (size - 1).bit_length()
-                                addr_bits = f"{sig.memory_addr:0{addr_width}b}"
-                                smt_expr = "(select %s #b%s )" % (smt_expr, addr_bits)
+            end = width + offset
+            common_offset = max(sig.offset, offset)
+            common_end = min(sig_end, end)
+            if common_end <= common_offset:
+                continue
 
-                            if len(bits) < width:
-                                slice_high = sig.offset + len(bits) - 1
-                                smt_expr = "((_ extract %d %d) %s)" % (slice_high, sig.offset, smt_expr)
+            smt_expr = smt.witness_net_expr(topmod, f"s{step}", wire)
 
-                            bit_slice = bits
+            if not smt_bool:
+                slice_high = common_end - offset - 1
+                slice_low = common_offset - offset
+                smt_expr = "((_ extract %d %d) %s)" % (slice_high, slice_low, smt_expr)
+            else:
+                smt_expr = "(ite %s #b1 #b0)" % smt_expr
 
-                            if "?" in bit_slice:
-                                mask = bit_slice.replace("0", "1").replace("?", "0")
-                                bit_slice = bit_slice.replace("?", "0")
-                                smt_expr = "(bvand %s #b%s)" % (smt_expr, mask)
+            output.append(((common_offset - sig.offset), (common_end - sig.offset), smt_expr))
 
-                            smt_constr = "(= %s #b%s)" % (smt_expr, bit_slice)
-                            constr_assumes[t].append((inywfile, smt_constr))
-            max_t = t
+    if sig.memory_path:
+        if sig.memory_path in smt_mems:
+            for mem in smt_mems[sig.memory_path]:
+                width, size, bv = mem["width"], mem["size"], mem["statebv"]
+
+                smt_expr = smt.net_expr(topmod, f"s{step}", mem["smtpath"])
+
+                if bv:
+                    word_low = sig.memory_addr * width
+                    word_high = word_low + width - 1
+                    smt_expr = "((_ extract %d %d) %s)" % (word_high, word_low, smt_expr)
+                else:
+                    addr_width = (size - 1).bit_length()
+                    addr_bits = f"{sig.memory_addr:0{addr_width}b}"
+                    smt_expr = "(select %s #b%s )" % (smt_expr, addr_bits)
+
+                if sig.width < width:
+                    slice_high = sig.offset + sig.width - 1
+                    smt_expr = "((_ extract %d %d) %s)" % (slice_high, sig.offset, smt_expr)
 
+                output.append((0, sig.width, smt_expr))
+
+    output.sort()
+
+    output = [chunk for chunk in output if chunk[0] != chunk[1]]
+
+    pos = 0
+
+    for start, end, smt_expr in output:
+        assert start == pos
+        pos = end
+
+    assert pos == sig.width
+
+    if len(output) == 1:
+        return output[0][-1]
+    return smt_concat(smt_expr for start, end, smt_expr in reversed(output))
+
+def ywfile_constraints(inywfile, constr_assumes, map_steps=None, skip_x=False):
+    global ywfile_hierwitness_cache
+    if map_steps is None:
+        map_steps = {}
+
+    with open(inywfile, "r") as f:
+        inyw = ReadWitness(f)
+
+        inits, seqs, clocks, mems, smt_wires, smt_mems = ywfile_hierwitness()
+
+        bits_re = re.compile(r'[01?]*$')
+        max_t = -1
+
+        for t, step in inyw.steps():
+            present_signals, missing = step.present_signals(inyw.sigmap)
+            for sig in present_signals:
+                bits = step[sig]
+                if skip_x:
+                    bits = bits.replace('x', '?')
+                if not bits_re.match(bits):
+                    raise ValueError("unsupported bit value in Yosys witness file")
+
+                smt_expr = ywfile_signal(sig, map_steps.get(t, t))
+
+                smt_expr, bits = smt_extract_mask(smt_expr, bits)
+
+                smt_constr = "(= %s #b%s)" % (smt_expr, bits)
+                constr_assumes[t].append((inywfile, smt_constr))
+
+            max_t = t
         return max_t
 
 if inywfile is not None:
@@ -1367,11 +1416,11 @@ def write_yw_trace(steps, index, allregs=False, filename=None):
 
             exprs.extend(smt.witness_net_expr(topmod, f"s{k}", sig) for sig in sigs)
 
-            all_sigs.append(sigs)
+            all_sigs.append((step_values, sigs))
 
         bvs = iter(smt.get_list(exprs))
 
-        for sigs in all_sigs:
+        for (step_values, sigs) in all_sigs:
             for sig in sigs:
                 value = smt.bv2bin(next(bvs))
                 step_values[sig["sig"]] = value
diff --git a/backends/smt2/smtbmc_incremental.py b/backends/smt2/smtbmc_incremental.py
index f43e878f31c..0bd280b4a48 100644
--- a/backends/smt2/smtbmc_incremental.py
+++ b/backends/smt2/smtbmc_incremental.py
@@ -1,7 +1,7 @@
 from collections import defaultdict
 import json
 import typing
-from functools import partial
+import ywio
 
 if typing.TYPE_CHECKING:
     import smtbmc
@@ -34,6 +34,7 @@ def __init__(self):
         self._witness_index = None
 
         self._yw_constraints = {}
+        self._define_sorts = {}
 
     def setup(self):
         generic_assert_map = smtbmc.get_assert_map(
@@ -175,11 +176,7 @@ def expr_andor(self, expr, smt_out):
         if len(expr) == 1:
             smt_out.push({"and": "true", "or": "false"}[expr[0]])
         elif len(expr) == 2:
-            arg_sort = self.expr(expr[1], smt_out)
-            if arg_sort != "Bool":
-                raise InteractiveError(
-                    f"arguments of {json.dumps(expr[0])} must have sort Bool"
-                )
+            self.expr(expr[1], smt_out, required_sort="Bool")
         else:
             sep = f"({expr[0]} "
             for arg in expr[1:]:
@@ -189,7 +186,51 @@ def expr_andor(self, expr, smt_out):
             smt_out.append(")")
         return "Bool"
 
+    def expr_bv_binop(self, expr, smt_out):
+        self.expr_arg_len(expr, 2)
+
+        smt_out.append(f"({expr[0]} ")
+        arg_sort = self.expr(expr[1], smt_out, required_sort=("BitVec", None))
+        smt_out.append(" ")
+        self.expr(expr[2], smt_out, required_sort=arg_sort)
+        smt_out.append(")")
+        return arg_sort
+
+    def expr_extract(self, expr, smt_out):
+        self.expr_arg_len(expr, 3)
+
+        hi = expr[1]
+        lo = expr[2]
+
+        smt_out.append(f"((_ extract {hi} {lo}) ")
+
+        arg_sort = self.expr(expr[3], smt_out, required_sort=("BitVec", None))
+        smt_out.append(")")
+
+        if not (isinstance(hi, int) and 0 <= hi < arg_sort[1]):
+            raise InteractiveError(
+                f"high bit index must be 0 <= index < {arg_sort[1]}, is {hi!r}"
+            )
+        if not (isinstance(lo, int) and 0 <= lo <= hi):
+            raise InteractiveError(
+                f"low bit index must be 0 <= index < {hi}, is {lo!r}"
+            )
+
+        return "BitVec", hi - lo + 1
+
+    def expr_bv(self, expr, smt_out):
+        self.expr_arg_len(expr, 1)
+
+        arg = expr[1]
+        if not isinstance(arg, str) or arg.count("0") + arg.count("1") != len(arg):
+            raise InteractiveError("bv argument must contain only 0 or 1 bits")
+
+        smt_out.append("#b" + arg)
+
+        return "BitVec", len(arg)
+
     def expr_yw(self, expr, smt_out):
+        self.expr_arg_len(expr, 1, 2)
         if len(expr) == 2:
             name = None
             step = expr[1]
@@ -219,6 +260,40 @@ def expr_yw(self, expr, smt_out):
 
         return "Bool"
 
+    def expr_yw_sig(self, expr, smt_out):
+        self.expr_arg_len(expr, 3, 4)
+
+        step = expr[1]
+        path = expr[2]
+        offset = expr[3]
+        width = expr[4] if len(expr) == 5 else 1
+
+        if not isinstance(offset, int) or offset < 0:
+            raise InteractiveError(
+                f"offset must be a non-negative integer, got {json.dumps(offset)}"
+            )
+
+        if not isinstance(width, int) or width <= 0:
+            raise InteractiveError(
+                f"width must be a positive integer, got {json.dumps(width)}"
+            )
+
+        if not isinstance(path, list) or not all(isinstance(s, str) for s in path):
+            raise InteractiveError(
+                f"path must be a string list, got {json.dumps(path)}"
+            )
+
+        if step not in self.state_set:
+            raise InteractiveError(f"step {step} not declared")
+
+        smt_expr = smtbmc.ywfile_signal(
+            ywio.WitnessSig(path=path, offset=offset, width=width), step
+        )
+
+        smt_out.append(smt_expr)
+
+        return "BitVec", width
+
     def expr_smtlib(self, expr, smt_out):
         self.expr_arg_len(expr, 2)
 
@@ -231,10 +306,15 @@ def expr_smtlib(self, expr, smt_out):
                 f"got {json.dumps(smtlib_expr)}"
             )
 
-        if not isinstance(sort, str):
-            raise InteractiveError(
-                f"raw SMT-LIB sort has to be a string, got {json.dumps(sort)}"
-            )
+        if (
+            isinstance(sort, list)
+            and len(sort) == 2
+            and sort[0] == "BitVec"
+            and (sort[1] is None or isinstance(sort[1], int))
+        ):
+            sort = tuple(sort)
+        elif not isinstance(sort, str):
+            raise InteractiveError(f"unsupported raw SMT-LIB sort {json.dumps(sort)}")
 
         smt_out.append(smtlib_expr)
         return sort
@@ -258,6 +338,14 @@ def expr_label(self, expr, smt_out):
 
         return sort
 
+    def expr_def(self, expr, smt_out):
+        self.expr_arg_len(expr, 1)
+        sort = self._define_sorts.get(expr[1])
+        if sort is None:
+            raise InteractiveError(f"unknown definition {json.dumps(expr)}")
+        smt_out.append(expr[1])
+        return sort
+
     expr_handlers = {
         "step": expr_step,
         "cell": expr_cell,
@@ -270,8 +358,15 @@ def expr_label(self, expr, smt_out):
         "not": expr_not,
         "and": expr_andor,
         "or": expr_andor,
+        "bv": expr_bv,
+        "bvand": expr_bv_binop,
+        "bvor": expr_bv_binop,
+        "bvxor": expr_bv_binop,
+        "extract": expr_extract,
+        "def": expr_def,
         "=": expr_eq,
         "yw": expr_yw,
+        "yw_sig": expr_yw_sig,
         "smtlib": expr_smtlib,
         "!": expr_label,
     }
@@ -305,10 +400,13 @@ def expr(self, expr, smt_out, required_sort=None):
         raise InteractiveError(f"unknown expression {json.dumps(expr[0])}")
 
     def expr_smt(self, expr, required_sort):
+        return self.expr_smt_and_sort(expr, required_sort)[0]
+
+    def expr_smt_and_sort(self, expr, required_sort=None):
         smt_out = []
-        self.expr(expr, smt_out, required_sort=required_sort)
+        output_sort = self.expr(expr, smt_out, required_sort=required_sort)
         out = "".join(smt_out)
-        return out
+        return out, output_sort
 
     def cmd_new_step(self, cmd):
         step = self.arg_step(cmd, declare=True)
@@ -338,7 +436,6 @@ def cmd_update_assumptions(self, cmd):
         expr = cmd.get("expr")
         key = cmd.get("key")
 
-
         key = mkkey(key)
 
         result = smtbmc.smt.smt2_assumptions.pop(key, None)
@@ -348,7 +445,7 @@ def cmd_update_assumptions(self, cmd):
         return result
 
     def cmd_get_unsat_assumptions(self, cmd):
-        return smtbmc.smt.get_unsat_assumptions(minimize=bool(cmd.get('minimize')))
+        return smtbmc.smt.get_unsat_assumptions(minimize=bool(cmd.get("minimize")))
 
     def cmd_push(self, cmd):
         smtbmc.smt_push()
@@ -370,6 +467,27 @@ def cmd_smtlib(self, cmd):
         if response:
             return smtbmc.smt.read()
 
+    def cmd_define(self, cmd):
+        expr = cmd.get("expr")
+        if expr is None:
+            raise InteractiveError("'define' copmmand requires 'expr' parameter")
+
+        expr, sort = self.expr_smt_and_sort(expr)
+
+        if isinstance(sort, tuple) and sort[0] == "module":
+            raise InteractiveError("'define' does not support module sorts")
+
+        define_name = f"|inc def {len(self._define_sorts)}|"
+
+        self._define_sorts[define_name] = sort
+
+        if isinstance(sort, tuple):
+            sort = f"(_ {' '.join(map(str, sort))})"
+
+        smtbmc.smt.write(f"(define-const {define_name} {sort} {expr})")
+
+        return {"name": define_name}
+
     def cmd_design_hierwitness(self, cmd=None):
         allregs = (cmd is None) or bool(cmd.get("allreges", False))
         if self._cached_hierwitness[allregs] is not None:
@@ -451,6 +569,7 @@ def cmd_ping(self, cmd):
         "pop": cmd_pop,
         "check": cmd_check,
         "smtlib": cmd_smtlib,
+        "define": cmd_define,
         "design_hierwitness": cmd_design_hierwitness,
         "write_yw_trace": cmd_write_yw_trace,
         "read_yw_trace": cmd_read_yw_trace,
diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py
index e32f43c60a0..5fc3ab5a424 100644
--- a/backends/smt2/smtio.py
+++ b/backends/smt2/smtio.py
@@ -160,6 +160,7 @@ def __init__(self, opts=None):
             self.noincr = opts.noincr
             self.info_stmts = opts.info_stmts
             self.nocomments = opts.nocomments
+            self.smt2_options.update(opts.smt2_options)
 
         else:
             self.solver = "yices"
@@ -959,6 +960,8 @@ def bv2int(self, v):
         return int(self.bv2bin(v), 2)
 
     def get_raw_unsat_assumptions(self):
+        if not self.smt2_assumptions:
+            return []
         self.write("(get-unsat-assumptions)")
         exprs = set(self.unparse(part) for part in self.parse(self.read()))
         unsat_assumptions = []
@@ -973,6 +976,10 @@ def get_raw_unsat_assumptions(self):
     def get_unsat_assumptions(self, minimize=False):
         if not minimize:
             return self.get_raw_unsat_assumptions()
+        orig_assumptions = self.smt2_assumptions
+
+        self.smt2_assumptions = dict(orig_assumptions)
+
         required_assumptions = {}
 
         while True:
@@ -998,6 +1005,7 @@ def get_unsat_assumptions(self, minimize=False):
                     required_assumptions[candidate_key] = candidate_assume
 
             if candidate_assumptions is not None:
+                self.smt2_assumptions = orig_assumptions
                 return list(required_assumptions)
 
     def get(self, expr):
@@ -1146,7 +1154,7 @@ def wait(self):
 class SmtOpts:
     def __init__(self):
         self.shortopts = "s:S:v"
-        self.longopts = ["unroll", "noincr", "noprogress", "timeout=", "dump-smt2=", "logic=", "dummy=", "info=", "nocomments"]
+        self.longopts = ["unroll", "noincr", "noprogress", "timeout=", "dump-smt2=", "logic=", "dummy=", "info=", "nocomments", "smt2-option="]
         self.solver = "yices"
         self.solver_opts = list()
         self.debug_print = False
@@ -1159,6 +1167,7 @@ def __init__(self):
         self.logic = None
         self.info_stmts = list()
         self.nocomments = False
+        self.smt2_options = {}
 
     def handle(self, o, a):
         if o == "-s":
@@ -1185,6 +1194,13 @@ def handle(self, o, a):
             self.info_stmts.append(a)
         elif o == "--nocomments":
             self.nocomments = True
+        elif o == "--smt2-option":
+            args = a.split('=', 1)
+            if len(args) != 2:
+                print("--smt2-option expects an <option>=<value> argument")
+                sys.exit(1)
+            option, value = args
+            self.smt2_options[option] = value
         else:
             return False
         return True
@@ -1208,6 +1224,9 @@ def helpmsg(self):
         if solver is "dummy", read solver output from that file
         otherwise: write solver output to that file
 
+    --smt2-option <option>=<value>
+        enable an SMT-LIBv2 option.
+
     -v
         enable debug output
 

From df95ea824b051e633f7c198c075e55f9e0f726d7 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Sat, 6 Apr 2024 14:24:34 +1300
Subject: [PATCH 025/499] read_verilog: Add missing defaults for flags

Fix for YosysHQ/sby#103
---
 frontends/verilog/verilog_frontend.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 5c59fe3afac..d363d71fb9a 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -270,8 +270,11 @@ struct VerilogFrontend : public Frontend {
 		frontend_verilog_yydebug = false;
 		sv_mode = false;
 		formal_mode = false;
+		noassert_mode = false;
+		noassume_mode = false;
 		norestrict_mode = false;
 		assume_asserts_mode = false;
+		assert_assumes_mode = false;
 		lib_mode = false;
 		specify_mode = false;
 		default_nettype_wire = true;

From 09b9aa83c9ec7c1e7cf64ae267d5947c4b962b9a Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Fri, 12 Apr 2024 07:08:18 +0200
Subject: [PATCH 026/499] Add YosysHQ/abc as a submodule located in abc

---
 .github/workflows/codeql.yml       |  3 +-
 .github/workflows/emcc.yml         |  2 ++
 .github/workflows/test-docs.yml    |  3 +-
 .github/workflows/test-linux.yml   |  3 +-
 .github/workflows/test-macos.yml   |  3 +-
 .github/workflows/test-verific.yml |  2 +-
 .github/workflows/version.yml      |  1 +
 .github/workflows/vs.yml           |  6 ++--
 .github/workflows/wasi.yml         |  2 ++
 .gitignore                         |  2 +-
 .gitmodules                        |  3 ++
 Makefile                           | 56 ++++++------------------------
 abc                                |  1 +
 13 files changed, 33 insertions(+), 54 deletions(-)
 create mode 100644 .gitmodules
 create mode 160000 abc

diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml
index 4a77d223429..24ae7c89883 100644
--- a/.github/workflows/codeql.yml
+++ b/.github/workflows/codeql.yml
@@ -15,7 +15,8 @@ jobs:
 
     - name: Checkout repository
       uses: actions/checkout@v4
-
+      with:
+       submodules: true
     - name: Initialize CodeQL
       uses: github/codeql-action/init@v3
       with:
diff --git a/.github/workflows/emcc.yml b/.github/workflows/emcc.yml
index 7c6409c1be2..b883cfa0a8a 100644
--- a/.github/workflows/emcc.yml
+++ b/.github/workflows/emcc.yml
@@ -8,6 +8,8 @@ jobs:
     steps:
       - uses: mymindstorm/setup-emsdk@v14
       - uses: actions/checkout@v4
+        with:
+         submodules: true
       - name: Build
         run: |
           make config-emcc
diff --git a/.github/workflows/test-docs.yml b/.github/workflows/test-docs.yml
index 00e5309bfbe..f6bcd33eb1b 100644
--- a/.github/workflows/test-docs.yml
+++ b/.github/workflows/test-docs.yml
@@ -29,7 +29,8 @@ jobs:
 
       - name: Checkout Yosys
         uses: actions/checkout@v3
-
+        with:
+         submodules: true
       - name: Build yosys
         shell: bash
         run: |
diff --git a/.github/workflows/test-linux.yml b/.github/workflows/test-linux.yml
index c4441a8843e..a75873d8995 100644
--- a/.github/workflows/test-linux.yml
+++ b/.github/workflows/test-linux.yml
@@ -80,7 +80,8 @@ jobs:
 
       - name: Checkout Yosys
         uses: actions/checkout@v4
-
+        with:
+         submodules: true
       - name: Get iverilog
         shell: bash
         run: |
diff --git a/.github/workflows/test-macos.yml b/.github/workflows/test-macos.yml
index 8ca658c3951..37b66df9bec 100644
--- a/.github/workflows/test-macos.yml
+++ b/.github/workflows/test-macos.yml
@@ -36,7 +36,8 @@ jobs:
 
       - name: Checkout Yosys
         uses: actions/checkout@v4
-
+        with:
+         submodules: true
       - name: Get iverilog
         shell: bash
         run: |
diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml
index b4383eba462..ef7fa3829d8 100644
--- a/.github/workflows/test-verific.yml
+++ b/.github/workflows/test-verific.yml
@@ -10,7 +10,7 @@ jobs:
         uses: actions/checkout@v4
         with:
           persist-credentials: false
-
+          submodules: true
       - name: Runtime environment
         run: |
           echo "procs=$(nproc)" >> $GITHUB_ENV
diff --git a/.github/workflows/version.yml b/.github/workflows/version.yml
index 47a7fe1a39f..f73c68bdf12 100644
--- a/.github/workflows/version.yml
+++ b/.github/workflows/version.yml
@@ -13,6 +13,7 @@ jobs:
         uses: actions/checkout@v4
         with:
           fetch-depth: 0
+          submodules: true
       - name: Take last commit
         id: log
         run: echo "message=$(git log --no-merges -1 --oneline)" >> $GITHUB_OUTPUT
diff --git a/.github/workflows/vs.yml b/.github/workflows/vs.yml
index 799c5f259f4..0647cff1a34 100644
--- a/.github/workflows/vs.yml
+++ b/.github/workflows/vs.yml
@@ -7,17 +7,19 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v4
+        with:
+         submodules: true
       - name: Build
         run: make vcxsrc YOSYS_VER=latest
       - uses: actions/upload-artifact@v4
         with:
           name: vcxsrc
           path: yosys-win32-vcxsrc-latest.zip
-  
+
   build:
     runs-on: windows-2019
     needs: yosys-vcxsrc
-    steps:  
+    steps:
       - uses: actions/download-artifact@v4
         with:
           name: vcxsrc
diff --git a/.github/workflows/wasi.yml b/.github/workflows/wasi.yml
index d6d200d92c2..d65a9622799 100644
--- a/.github/workflows/wasi.yml
+++ b/.github/workflows/wasi.yml
@@ -7,6 +7,8 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v4
+        with:
+         submodules: true
       - name: Build
         run: |
           WASI_SDK=wasi-sdk-19.0
diff --git a/.gitignore b/.gitignore
index 6e4ffea4203..b4797d63884 100644
--- a/.gitignore
+++ b/.gitignore
@@ -18,7 +18,6 @@ __pycache__
 /coverage.info
 /coverage_html
 /Makefile.conf
-/abc
 /viz.js
 /yosys
 /yosys.exe
@@ -46,3 +45,4 @@ __pycache__
 /tests/unit/bintest/
 /tests/unit/objtest/
 /tests/ystests
+/build
diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 00000000000..d88d4b1e5e9
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "abc"]
+	path = abc
+	url = https://github.com/YosysHQ/abc
diff --git a/Makefile b/Makefile
index 55c6a3f02b0..5986539b6b9 100644
--- a/Makefile
+++ b/Makefile
@@ -160,15 +160,6 @@ OBJS = kernel/version_$(GIT_REV).o
 bumpversion:
 	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline c1ad377.. | wc -l`/;" Makefile
 
-# set 'ABCREV = default' to use abc/ as it is
-#
-# Note: If you do ABC development, make sure that 'abc' in this directory
-# is just a symlink to your actual ABC working directory, as 'make mrproper'
-# will remove the 'abc' directory and you do not want to accidentally
-# delete your work on ABC..
-ABCREV = 237d813
-ABCPULL = 1
-ABCURL ?= https://github.com/YosysHQ/abc
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
 
 # set ABCEXTERNAL = <abc-command> to use an external ABC instance
@@ -789,41 +780,17 @@ $(PROGRAM_PREFIX)yosys-config: misc/yosys-config.in
 			-e 's#@BINDIR@#$(strip $(BINDIR))#;' -e 's#@DATDIR@#$(strip $(DATDIR))#;' < $< > $(PROGRAM_PREFIX)yosys-config
 	$(Q) chmod +x $(PROGRAM_PREFIX)yosys-config
 
-abc/abc-$(ABCREV)$(EXE) abc/libabc-$(ABCREV).a:
+ABC_SOURCES := $(wildcard $(YOSYS_SRC)/abc/*)
+
+abc/abc$(EXE) abc/libabc.a: $(ABC_SOURCES)
 	$(P)
-ifneq ($(ABCREV),default)
-	$(Q) if test -d abc/.hg; then \
-		echo 'REEBE: NOP qverpgbel vf n ut jbexvat pbcl! Erzbir nop/ naq er-eha "znxr".' | tr 'A-Za-z' 'N-ZA-Mn-za-m'; false; \
-	fi
-	$(Q) if test -d abc && test -d abc/.git && ! git -C abc diff-index --quiet HEAD; then \
-		echo 'REEBE: NOP pbagnvaf ybpny zbqvsvpngvbaf! Frg NOPERI=qrsnhyg va Lbflf Znxrsvyr!' | tr 'A-Za-z' 'N-ZA-Mn-za-m'; false; \
-	fi
-	$(Q) if test -d abc && ! test -d abc/.git && ! test "`cat abc/.gitcommit | cut -c1-7`" = "$(ABCREV)"; then \
-		echo 'REEBE: Qbjaybnqrq NOP irefvbaf qbrf abg zngpu! Qbjaybnq sebz:' | tr 'A-Za-z' 'N-ZA-Mn-za-m'; echo $(ABCURL)/archive/$(ABCREV).tar.gz; false; \
-	fi
-# set a variable so the test fails if git fails to run - when comparing outputs directly, empty string would match empty string
-	$(Q) if test -d abc && ! test -d abc/.git && test "`cat abc/.gitcommit | cut -c1-7`" = "$(ABCREV)"; then \
-		echo "Compiling local copy of ABC"; \
-	elif ! (cd abc 2> /dev/null && rev="`git rev-parse $(ABCREV)`" && test "`git rev-parse HEAD`" = "$$rev"); then \
-		test $(ABCPULL) -ne 0 || { echo 'REEBE: NOP abg hc gb qngr naq NOPCHYY frg gb 0 va Znxrsvyr!' | tr 'A-Za-z' 'N-ZA-Mn-za-m'; exit 1; }; \
-		echo "Pulling ABC from $(ABCURL):"; set -x; \
-		test -d abc || git clone $(ABCURL) abc; \
-		cd abc && $(MAKE) DEP= clean && git fetch $(ABCURL) && git checkout $(ABCREV); \
-	fi
-endif
-	$(Q) rm -f abc/abc-[0-9a-f]*
-	$(Q) $(MAKE) -C abc $(S) $(ABCMKARGS) $(if $(filter %.a,$@),PROG="abc-$(ABCREV)",PROG="abc-$(ABCREV)$(EXE)") MSG_PREFIX="$(eval P_OFFSET = 5)$(call P_SHOW)$(eval P_OFFSET = 10) ABC: " $(if $(filter %.a,$@),libabc-$(ABCREV).a)
-
-ifeq ($(ABCREV),default)
-.PHONY: abc/abc-$(ABCREV)$(EXE)
-.PHONY: abc/libabc-$(ABCREV).a
-endif
-
-$(PROGRAM_PREFIX)yosys-abc$(EXE): abc/abc-$(ABCREV)$(EXE)
-	$(P) cp abc/abc-$(ABCREV)$(EXE) $(PROGRAM_PREFIX)yosys-abc$(EXE)
-
-$(PROGRAM_PREFIX)yosys-libabc.a: abc/libabc-$(ABCREV).a
-	$(P) cp abc/libabc-$(ABCREV).a $(PROGRAM_PREFIX)yosys-libabc.a
+	$(Q) mkdir -p abc && $(MAKE) -C $(PROGRAM_PREFIX)abc -f "$(realpath $(YOSYS_SRC)/abc/Makefile)" ABCSRC="$(realpath $(YOSYS_SRC)/abc/)" $(S) $(ABCMKARGS) $(if $(filter %.a,$@),PROG="abc",PROG="abc$(EXE)") MSG_PREFIX="$(eval P_OFFSET = 5)$(call P_SHOW)$(eval P_OFFSET = 10) ABC: " $(if $(filter %.a,$@),libabc.a)
+
+$(PROGRAM_PREFIX)yosys-abc$(EXE): abc/abc$(EXE)
+	$(P) cp abc/abc$(EXE) $(PROGRAM_PREFIX)yosys-abc$(EXE)
+
+$(PROGRAM_PREFIX)yosys-libabc.a: abc/libabc.a
+	$(P) cp abc/libabc.a $(PROGRAM_PREFIX)yosys-libabc.a
 
 ifneq ($(SEED),)
 SEEDOPT="-S $(SEED)"
@@ -1141,9 +1108,6 @@ echo-yosys-ver:
 echo-git-rev:
 	@echo "$(GIT_REV)"
 
-echo-abc-rev:
-	@echo "$(ABCREV)"
-
 echo-cxx:
 	@echo "$(CXX)"
 
diff --git a/abc b/abc
new file mode 160000
index 00000000000..237d81397fc
--- /dev/null
+++ b/abc
@@ -0,0 +1 @@
+Subproject commit 237d81397fcc85dd3894bf1a449d2955cd3df02d

From 67d4c8bba664f98b4ada2770c648376d92714f35 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Fri, 12 Apr 2024 07:24:45 +0200
Subject: [PATCH 027/499] Use $< to refer to the first prerequisite listed in
 the rule

---
 Makefile | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index 5986539b6b9..2188c52e112 100644
--- a/Makefile
+++ b/Makefile
@@ -787,10 +787,10 @@ abc/abc$(EXE) abc/libabc.a: $(ABC_SOURCES)
 	$(Q) mkdir -p abc && $(MAKE) -C $(PROGRAM_PREFIX)abc -f "$(realpath $(YOSYS_SRC)/abc/Makefile)" ABCSRC="$(realpath $(YOSYS_SRC)/abc/)" $(S) $(ABCMKARGS) $(if $(filter %.a,$@),PROG="abc",PROG="abc$(EXE)") MSG_PREFIX="$(eval P_OFFSET = 5)$(call P_SHOW)$(eval P_OFFSET = 10) ABC: " $(if $(filter %.a,$@),libabc.a)
 
 $(PROGRAM_PREFIX)yosys-abc$(EXE): abc/abc$(EXE)
-	$(P) cp abc/abc$(EXE) $(PROGRAM_PREFIX)yosys-abc$(EXE)
+	$(P) cp $< $(PROGRAM_PREFIX)yosys-abc$(EXE)
 
 $(PROGRAM_PREFIX)yosys-libabc.a: abc/libabc.a
-	$(P) cp abc/libabc.a $(PROGRAM_PREFIX)yosys-libabc.a
+	$(P) cp $< $(PROGRAM_PREFIX)yosys-libabc.a
 
 ifneq ($(SEED),)
 SEEDOPT="-S $(SEED)"

From fdbe8714c9337e8125470c9d4bc28e9b141e3997 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Fri, 12 Apr 2024 14:29:05 +0200
Subject: [PATCH 028/499] Check that abc is checkout out as a git repo

---
 Makefile | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 2188c52e112..e7a1248c46c 100644
--- a/Makefile
+++ b/Makefile
@@ -780,9 +780,20 @@ $(PROGRAM_PREFIX)yosys-config: misc/yosys-config.in
 			-e 's#@BINDIR@#$(strip $(BINDIR))#;' -e 's#@DATDIR@#$(strip $(DATDIR))#;' < $< > $(PROGRAM_PREFIX)yosys-config
 	$(Q) chmod +x $(PROGRAM_PREFIX)yosys-config
 
+.PHONY: check-git-abc
+
+check-git-abc:
+	@if [ -f "$(YOSYS_SRC)/abc/.git" ]; then \
+	    echo "abc/.git exists"; \
+		  exit 0; \
+	else \
+	    echo "abc/.git does not exist. Please execute git submodule update --init"; \
+	    exit 1; \
+	fi
+
 ABC_SOURCES := $(wildcard $(YOSYS_SRC)/abc/*)
 
-abc/abc$(EXE) abc/libabc.a: $(ABC_SOURCES)
+abc/abc$(EXE) abc/libabc.a: $(ABC_SOURCES) check-git-abc
 	$(P)
 	$(Q) mkdir -p abc && $(MAKE) -C $(PROGRAM_PREFIX)abc -f "$(realpath $(YOSYS_SRC)/abc/Makefile)" ABCSRC="$(realpath $(YOSYS_SRC)/abc/)" $(S) $(ABCMKARGS) $(if $(filter %.a,$@),PROG="abc",PROG="abc$(EXE)") MSG_PREFIX="$(eval P_OFFSET = 5)$(call P_SHOW)$(eval P_OFFSET = 10) ABC: " $(if $(filter %.a,$@),libabc.a)
 

From 6d181c29ce05323fe1515e3dea7cb43ed8167773 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Sun, 14 Apr 2024 19:56:07 +0200
Subject: [PATCH 029/499] Checking different cases for abc

---
 Makefile | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/Makefile b/Makefile
index e7a1248c46c..46778b6d53a 100644
--- a/Makefile
+++ b/Makefile
@@ -783,12 +783,24 @@ $(PROGRAM_PREFIX)yosys-config: misc/yosys-config.in
 .PHONY: check-git-abc
 
 check-git-abc:
-	@if [ -f "$(YOSYS_SRC)/abc/.git" ]; then \
-	    echo "abc/.git exists"; \
-		  exit 0; \
-	else \
-	    echo "abc/.git does not exist. Please execute git submodule update --init"; \
+	@if [ ! -d "$(YOSYS_SRC)/abc" ]; then \
+	    echo "Error: The 'abc' directory does not exist."; \
+			echo "Initialize the submodule: Run 'git submodule update --init' to set up 'abc' as a submodule."; \
+	    exit 1; \
+	elif git -C "$(YOSYS_SRC)" submodule status abc 2>/dev/null | grep -q '^ '; then \
+	    echo "'abc' is a git submodule. Continuing."; \
+	    exit 0; \
+	elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && grep -q '\$$Format:%h\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \
+	    echo "Error: 'abc' is not configured as a git submodule."; \
+	    echo "To resolve this:"; \
+	    echo "1. Back up your changes: Save any modifications from the 'abc' directory to another location."; \
+	    echo "2. Remove the existing 'abc' directory: Delete the 'abc' directory and all its contents."; \
+	    echo "3. Initialize the submodule: Run 'git submodule update --init' to set up 'abc' as a submodule."; \
+	    echo "4. Reapply your changes: Move your saved changes back to the 'abc' directory, if necessary."; \
 	    exit 1; \
+	else \
+	    echo "'abc' comes from a tarball. Continuing."; \
+	    exit 0; \
 	fi
 
 ABC_SOURCES := $(wildcard $(YOSYS_SRC)/abc/*)

From ce450112751aa39801d80af590e9cbccf142078e Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Wed, 8 May 2024 00:13:52 +0000
Subject: [PATCH 030/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 56efaf5eb0f..48594e1a381 100644
--- a/Makefile
+++ b/Makefile
@@ -142,7 +142,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.40+50
+YOSYS_VER := 0.40+68
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 7294d8b5af3d94c919271199edf1285ff335ccb3 Mon Sep 17 00:00:00 2001
From: Catherine <whitequark@whitequark.org>
Date: Wed, 8 May 2024 00:27:28 +0000
Subject: [PATCH 031/499] cxxrtl: fix close of invalid fd in spool destructor.

---
 backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h
index b8233b007c6..9aa3e105d2c 100644
--- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h
+++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h
@@ -512,9 +512,10 @@ class spool {
 	spool &operator=(const spool &) = delete;
 
 	~spool() {
-		if (int fd = writefd.exchange(-1))
+		int fd;
+		if ((fd = writefd.exchange(-1)) != -1)
 			close(fd);
-		if (int fd = readfd.exchange(-1))
+		if ((fd = readfd.exchange(-1)) != -1)
 			close(fd);
 	}
 

From a2c1b268d9fa664fcd08723cdb673ce9ea87e786 Mon Sep 17 00:00:00 2001
From: Ethan Mahintorabi <ethanmoon@google.com>
Date: Wed, 8 May 2024 01:00:06 +0000
Subject: [PATCH 032/499] frontend: Fixes verific import around range order

Test Case
```
module packed_dimensions_range_ordering (
    input  wire [0:4-1] in,
    output wire [4-1:0] out
);
  assign out = in;
endmodule : packed_dimensions_range_ordering

module instanciates_packed_dimensions_range_ordering (
    input  wire [4-1:0] in,
    output wire [4-1:0] out
);
  packed_dimensions_range_ordering U0 (
      .in (in),
      .out(out)
  );
endmodule : instanciates_packed_dimensions_range_ordering
```

```
// with verific, does not pass formal
module instanciates_packed_dimensions_range_ordering(in, out);
  input [3:0] in;
  wire [3:0] in;
  output [3:0] out;
  wire [3:0] out;

  assign out = { in[0], in[1], in[2], in[3] };
endmodule

// with surelog, passes formal
module instanciates_packed_dimensions_range_ordering(in, out);
  input [3:0] in;
  wire [3:0] in;
  output [3:0] out;
  wire [3:0] out;

  assign out = in;
endmodule
```

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
---
 frontends/verific/verific.cc | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 81e79f7497f..6203013bf68 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2156,8 +2156,16 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 			int port_offset = 0;
 			if (pr->GetPort()->Bus()) {
 				port_name = pr->GetPort()->Bus()->Name();
-				port_offset = pr->GetPort()->Bus()->IndexOf(pr->GetPort()) -
-						min(pr->GetPort()->Bus()->LeftIndex(), pr->GetPort()->Bus()->RightIndex());
+				int msb = pr->GetPort()->Bus()->LeftIndex();
+				int lsb = pr->GetPort()->Bus()->RightIndex();
+				int index_of_port = pr->GetPort()->Bus()->IndexOf(pr->GetPort());
+				port_offset =  index_of_port - min(msb, lsb);
+				// In cases where the msb order is flipped we need to make sure
+				// that the indicies match LSB = 0 order to match the std::vector
+				// to SigSpec LSB = 0 precondition.
+				if (lsb > msb) {
+					port_offset = abs(port_offset - lsb);
+				}
 			}
 			IdString port_name_id = RTLIL::escape_id(port_name);
 			auto &sigvec = cell_port_conns[port_name_id];

From c039da2ec167e2ef825357b09e6f7713c4a476df Mon Sep 17 00:00:00 2001
From: Ethan Mahintorabi <ethanmoon@google.com>
Date: Wed, 8 May 2024 01:09:52 +0000
Subject: [PATCH 033/499] renames variables for more code clairty

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
---
 frontends/verific/verific.cc | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 6203013bf68..a18f9fc877b 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2156,15 +2156,15 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 			int port_offset = 0;
 			if (pr->GetPort()->Bus()) {
 				port_name = pr->GetPort()->Bus()->Name();
-				int msb = pr->GetPort()->Bus()->LeftIndex();
-				int lsb = pr->GetPort()->Bus()->RightIndex();
+				int msb_index = pr->GetPort()->Bus()->LeftIndex();
+				int lsb_index = pr->GetPort()->Bus()->RightIndex();
 				int index_of_port = pr->GetPort()->Bus()->IndexOf(pr->GetPort());
-				port_offset =  index_of_port - min(msb, lsb);
+				port_offset =  index_of_port - min(msb_index, lsb_index);
 				// In cases where the msb order is flipped we need to make sure
 				// that the indicies match LSB = 0 order to match the std::vector
 				// to SigSpec LSB = 0 precondition.
-				if (lsb > msb) {
-					port_offset = abs(port_offset - lsb);
+				if (lsb_index > msb_index) {
+					port_offset = abs(port_offset - lsb_index);
 				}
 			}
 			IdString port_name_id = RTLIL::escape_id(port_name);

From 1c89e2ab92d5786dfa2ead8ba1c0f822697c5a24 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Wed, 8 May 2024 03:52:12 +0200
Subject: [PATCH 034/499] Add nix flake and lock file. Add nix build step.
 Pending nix flake update step

---
 .github/workflows/nix-github-actions.yml | 13 +++++
 flake.lock                               | 61 ++++++++++++++++++++++++
 flake.nix                                | 44 +++++++++++++++++
 3 files changed, 118 insertions(+)
 create mode 100644 .github/workflows/nix-github-actions.yml
 create mode 100644 flake.lock
 create mode 100644 flake.nix

diff --git a/.github/workflows/nix-github-actions.yml b/.github/workflows/nix-github-actions.yml
new file mode 100644
index 00000000000..a11584bc641
--- /dev/null
+++ b/.github/workflows/nix-github-actions.yml
@@ -0,0 +1,13 @@
+name: "build nix flake"
+on:
+  pull_request:
+  push:
+jobs:
+  tests:
+    runs-on: ubuntu-latest
+    steps:
+    - uses: actions/checkout@v4
+      with:
+       submodules: true
+    - uses: cachix/install-nix-action@v25
+    - run: nix build '.?submodules=1'
diff --git a/flake.lock b/flake.lock
new file mode 100644
index 00000000000..2545f4ce057
--- /dev/null
+++ b/flake.lock
@@ -0,0 +1,61 @@
+{
+  "nodes": {
+    "flake-utils": {
+      "inputs": {
+        "systems": "systems"
+      },
+      "locked": {
+        "lastModified": 1705309234,
+        "narHash": "sha256-uNRRNRKmJyCRC/8y1RqBkqWBLM034y4qN7EprSdmgyA=",
+        "owner": "numtide",
+        "repo": "flake-utils",
+        "rev": "1ef2e671c3b0c19053962c07dbda38332dcebf26",
+        "type": "github"
+      },
+      "original": {
+        "owner": "numtide",
+        "repo": "flake-utils",
+        "type": "github"
+      }
+    },
+    "nixpkgs": {
+      "locked": {
+        "lastModified": 1708807242,
+        "narHash": "sha256-sRTRkhMD4delO/hPxxi+XwLqPn8BuUq6nnj4JqLwOu0=",
+        "owner": "NixOS",
+        "repo": "nixpkgs",
+        "rev": "73de017ef2d18a04ac4bfd0c02650007ccb31c2a",
+        "type": "github"
+      },
+      "original": {
+        "owner": "NixOS",
+        "ref": "nixos-unstable",
+        "repo": "nixpkgs",
+        "type": "github"
+      }
+    },
+    "root": {
+      "inputs": {
+        "flake-utils": "flake-utils",
+        "nixpkgs": "nixpkgs"
+      }
+    },
+    "systems": {
+      "locked": {
+        "lastModified": 1681028828,
+        "narHash": "sha256-Vy1rq5AaRuLzOxct8nz4T6wlgyUR7zLU309k9mBC768=",
+        "owner": "nix-systems",
+        "repo": "default",
+        "rev": "da67096a3b9bf56a91d16901293e51ba5b49a27e",
+        "type": "github"
+      },
+      "original": {
+        "owner": "nix-systems",
+        "repo": "default",
+        "type": "github"
+      }
+    }
+  },
+  "root": "root",
+  "version": 7
+}
diff --git a/flake.nix b/flake.nix
new file mode 100644
index 00000000000..1143d538c25
--- /dev/null
+++ b/flake.nix
@@ -0,0 +1,44 @@
+{
+  description = "A nix flake for the Yosys synthesis suite";
+
+  inputs = {
+    nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable";
+    flake-utils.url = "github:numtide/flake-utils";
+  };
+
+  outputs = { self, nixpkgs, flake-utils }:
+    flake-utils.lib.eachDefaultSystem (system:
+      let
+        pkgs = import nixpkgs {
+          inherit system;
+        };
+        customYosys = pkgs.clangStdenv.mkDerivation {
+          name = "yosys";
+          src = ./. ;
+          buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git ];
+          checkInputs = with pkgs; [ gtest ];
+          propagatedBuildInputs = with pkgs; [ abc-verifier ];
+          preConfigure = "make config-clang";
+          checkTarget = "test";
+          installPhase = ''
+            make install PREFIX=$out
+          '';
+					buildPhase = ''
+          make -j$(nproc)
+          '';
+          meta = with pkgs.lib; {
+            description = "Yosys Open SYnthesis Suite";
+            homepage = "https://yosyshq.net/yosys/";
+            license = licenses.isc;
+            maintainers = with maintainers; [ ];
+          };
+        };
+      in {
+        packages.default = customYosys;
+        defaultPackage = customYosys;
+        devShell = pkgs.mkShell {
+          buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier ];
+        };
+      }
+    );
+}

From 6f9507a16f3c2a8838827e6695fae2b31eb9fa9b Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Wed, 8 May 2024 04:47:40 +0200
Subject: [PATCH 035/499] Add pkg-config

---
 flake.nix | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/flake.nix b/flake.nix
index 1143d538c25..d97be4ef671 100644
--- a/flake.nix
+++ b/flake.nix
@@ -15,7 +15,7 @@
         customYosys = pkgs.clangStdenv.mkDerivation {
           name = "yosys";
           src = ./. ;
-          buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git ];
+          buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git pkg-configUpstream ];
           checkInputs = with pkgs; [ gtest ];
           propagatedBuildInputs = with pkgs; [ abc-verifier ];
           preConfigure = "make config-clang";

From 43ddd89ba539e41459e3e83bcb088f8e2e575f8f Mon Sep 17 00:00:00 2001
From: Catherine <whitequark@whitequark.org>
Date: Wed, 8 May 2024 02:53:36 +0000
Subject: [PATCH 036/499] cxxrtl: fix `escape_c_string` hex literal fiasco.

In C and C++, a `\x` escape sequence consumes as many hexadecimal digits
as there are available, so it is not composable with arbitrary alnum
characters afterwards. An octal escape sequence like `\000` always has
fixed width, avoiding an issue where `\x01c` and `\x1c` produce the same
string.
---
 backends/cxxrtl/cxxrtl_backend.cc | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index 877a829d37a..86fe9e81b39 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -615,10 +615,11 @@ std::string escape_cxx_string(const std::string &input)
 				output.push_back('\\');
 			output.push_back(c);
 		} else {
-			char l = c & 0xf, h = (c >> 4) & 0xf;
-			output.append("\\x");
-			output.push_back((h < 10 ? '0' + h : 'a' + h - 10));
-			output.push_back((l < 10 ? '0' + l : 'a' + l - 10));
+			char l = c & 0x3, m = (c >> 3) & 0x3, h = (c >> 6) & 0x3;
+			output.append("\\");
+			output.push_back('0' + h);
+			output.push_back('0' + m);
+			output.push_back('0' + l);
 		}
 	}
 	output.push_back('"');

From 9134cd1928a0a043f241fb6e3deef5e0a59d1908 Mon Sep 17 00:00:00 2001
From: Catherine <whitequark@whitequark.org>
Date: Thu, 21 Mar 2024 20:28:32 +0000
Subject: [PATCH 037/499] cxxrtl: reduce stack space consumed by
 `debug_info()`.

Before this commit, the creation of (constant) attribute maps caused
`debug_info()` (which is built with `__attribute__((optnone))`) to
consume large amounts of stack space; up to tens of megabytes. This
caused problems particularly on macOS, where the default stack size
is 512 KiB.

After this commit, `std::map` objects are no longer created inline in
the `debug_info()` function, but are compiled to and then expanded from
a string literal in a subroutine call. This reduces stack space usage
by about 50%.
---
 backends/cxxrtl/cxxrtl_backend.cc       | 81 ++++++++++++++++++++-----
 backends/cxxrtl/runtime/cxxrtl/cxxrtl.h | 49 +++++++++++++++
 2 files changed, 116 insertions(+), 14 deletions(-)

diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index 86fe9e81b39..42b379637c9 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -606,9 +606,10 @@ std::vector<std::string> split_by(const std::string &str, const std::string &sep
 	return result;
 }
 
-std::string escape_cxx_string(const std::string &input)
+std::string escape_c_string(const std::string &input)
 {
-	std::string output = "\"";
+	std::string output;
+	output.push_back('"');
 	for (auto c : input) {
 		if (::isprint(c)) {
 			if (c == '\\')
@@ -623,6 +624,12 @@ std::string escape_cxx_string(const std::string &input)
 		}
 	}
 	output.push_back('"');
+	return output;
+}
+
+std::string escape_cxx_string(const std::string &input)
+{
+	std::string output = escape_c_string(input);
 	if (output.find('\0') != std::string::npos) {
 		output.insert(0, "std::string {");
 		output.append(stringf(", %zu}", input.size()));
@@ -2276,14 +2283,23 @@ struct CxxrtlWorker {
 		dec_indent();
 	}
 
-	void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map)
+	void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map, bool serialize = true)
 	{
 		if (metadata_map.empty()) {
 			f << "metadata_map()";
 			return;
-		}
-		f << "metadata_map({\n";
-		inc_indent();
+		} else if (serialize) {
+			// Creating thousands metadata_map objects using initializer lists in a single function results in one of:
+			// 1. Megabytes of stack usage (with __attribute__((optnone))).
+			// 2. Minutes of compile time (without __attribute__((optnone))).
+			// So, don't create them.
+			std::string data;
+			auto put_u64 = [&](uint64_t value) {
+				for (size_t count = 0; count < 8; count++) {
+					data += (char)(value >> 56);
+					value <<= 8;
+				}
+			};
 			for (auto metadata_item : metadata_map) {
 				if (!metadata_item.first.isPublic())
 					continue;
@@ -2291,21 +2307,58 @@ struct CxxrtlWorker {
 					f << indent << "/* attribute " << metadata_item.first.str().substr(1) << " is over 64 bits wide */\n";
 					continue;
 				}
-				f << indent << "{ " << escape_cxx_string(metadata_item.first.str().substr(1)) << ", ";
+				data += metadata_item.first.str().substr(1) + '\0';
 				// In Yosys, a real is a type of string.
 				if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) {
-					f << std::showpoint << std::stod(metadata_item.second.decode_string()) << std::noshowpoint;
+					double dvalue = std::stod(metadata_item.second.decode_string());
+					uint64_t uvalue;
+					static_assert(sizeof(dvalue) == sizeof(uvalue), "double must be 64 bits in size");
+					memcpy(&uvalue, &dvalue, sizeof(uvalue));
+					data += 'd';
+					put_u64(uvalue);
 				} else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) {
-					f << escape_cxx_string(metadata_item.second.decode_string());
+					data += 's';
+					data += metadata_item.second.decode_string();
+					data += '\0';
 				} else if (metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED) {
-					f << "INT64_C(" << metadata_item.second.as_int(/*is_signed=*/true) << ")";
+					data += 'i';
+					put_u64((uint64_t)metadata_item.second.as_int(/*is_signed=*/true));
 				} else {
-					f << "UINT64_C(" << metadata_item.second.as_int(/*is_signed=*/false) << ")";
+					data += 'u';
+					put_u64(metadata_item.second.as_int(/*is_signed=*/false));
 				}
-				f << " },\n";
 			}
-		dec_indent();
-		f << indent << "})";
+			f << "metadata::deserialize(\n";
+			inc_indent();
+				f << indent << escape_c_string(data) << "\n";
+			dec_indent();
+			f << indent << ")";
+		} else {
+			f << "metadata_map({\n";
+			inc_indent();
+				for (auto metadata_item : metadata_map) {
+					if (!metadata_item.first.isPublic())
+						continue;
+					if (metadata_item.second.size() > 64 && (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) == 0) {
+						f << indent << "/* attribute " << metadata_item.first.str().substr(1) << " is over 64 bits wide */\n";
+						continue;
+					}
+					f << indent << "{ " << escape_cxx_string(metadata_item.first.str().substr(1)) << ", ";
+					// In Yosys, a real is a type of string.
+					if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) {
+						f << std::showpoint << std::stod(metadata_item.second.decode_string()) << std::noshowpoint;
+					} else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) {
+						f << escape_cxx_string(metadata_item.second.decode_string());
+					} else if (metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED) {
+						f << "INT64_C(" << metadata_item.second.as_int(/*is_signed=*/true) << ")";
+					} else {
+						f << "UINT64_C(" << metadata_item.second.as_int(/*is_signed=*/false) << ")";
+					}
+					f << " },\n";
+				}
+			dec_indent();
+			f << indent << "})";
+		}
 	}
 
 	void dump_debug_attrs(const RTLIL::AttrObject *object)
diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
index 8546a841189..068dc350535 100644
--- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
+++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
@@ -941,6 +941,55 @@ struct metadata {
 		assert(value_type == DOUBLE);
 		return double_value;
 	}
+
+	// Internal CXXRTL use only.
+	static std::map<std::string, metadata> deserialize(const char *ptr) {
+		std::map<std::string, metadata> result;
+		std::string name;
+		// Grammar:
+		// string   ::= [^\0]+ \0
+		// metadata ::= [uid] .{8} | s <string>
+		// map      ::= ( <string> <metadata> )* \0
+		for (;;) {
+			if (*ptr) {
+				name += *ptr++;
+			} else if (!name.empty()) {
+				ptr++;
+				auto get_u64 = [&]() {
+					uint64_t result = 0;
+					for (size_t count = 0; count < 8; count++)
+						result = (result << 8) | *ptr++;
+					return result;
+				};
+				char type = *ptr++;
+				if (type == 'u') {
+					uint64_t value = get_u64();
+					result.emplace(name, value);
+				} else if (type == 'i') {
+					int64_t value = (int64_t)get_u64();
+					result.emplace(name, value);
+				} else if (type == 'd') {
+					double dvalue;
+					uint64_t uvalue = get_u64();
+					static_assert(sizeof(dvalue) == sizeof(uvalue), "double must be 64 bits in size");
+					memcpy(&dvalue, &uvalue, sizeof(dvalue));
+					result.emplace(name, dvalue);
+				} else if (type == 's') {
+					std::string value;
+					while (*ptr)
+						value += *ptr++;
+					ptr++;
+					result.emplace(name, value);
+				} else {
+					assert(false && "Unknown type specifier");
+					return result;
+				}
+				name.clear();
+			} else {
+				return result;
+			}
+		}
+	}
 };
 
 typedef std::map<std::string, metadata> metadata_map;

From 80798daf53e74dfc02c49bb31f99bd4b01c6537d Mon Sep 17 00:00:00 2001
From: Catherine <whitequark@whitequark.org>
Date: Wed, 8 May 2024 01:16:56 +0000
Subject: [PATCH 038/499] cxxrtl: reduce stack space consumed by `debug_info()`
 further.

Before this commit, this function would create a temporary `std::string`
per debug item (and scope). After this commit, an additional overload is
used to push that down the call stack. This reduces stack usage by
about 50% more on top of the previous commit.
---
 backends/cxxrtl/cxxrtl_backend.cc       | 120 ++++++++++++------------
 backends/cxxrtl/runtime/cxxrtl/cxxrtl.h |  10 ++
 2 files changed, 70 insertions(+), 60 deletions(-)

diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index 42b379637c9..d839bd86709 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -2283,56 +2283,52 @@ struct CxxrtlWorker {
 		dec_indent();
 	}
 
-	void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map, bool serialize = true)
-	{
+	void dump_serialized_metadata(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map) {
+		// Creating thousands metadata_map objects using initializer lists in a single function results in one of:
+		// 1. Megabytes of stack usage (with __attribute__((optnone))).
+		// 2. Minutes of compile time (without __attribute__((optnone))).
+		// So, don't create them.
+		std::string data;
+		auto put_u64 = [&](uint64_t value) {
+			for (size_t count = 0; count < 8; count++) {
+				data += (char)(value >> 56);
+				value <<= 8;
+			}
+		};
+		for (auto metadata_item : metadata_map) {
+			if (!metadata_item.first.isPublic())
+				continue;
+			if (metadata_item.second.size() > 64 && (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) == 0) {
+				f << indent << "/* attribute " << metadata_item.first.str().substr(1) << " is over 64 bits wide */\n";
+				continue;
+			}
+			data += metadata_item.first.str().substr(1) + '\0';
+			// In Yosys, a real is a type of string.
+			if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) {
+				double dvalue = std::stod(metadata_item.second.decode_string());
+				uint64_t uvalue;
+				static_assert(sizeof(dvalue) == sizeof(uvalue), "double must be 64 bits in size");
+				memcpy(&uvalue, &dvalue, sizeof(uvalue));
+				data += 'd';
+				put_u64(uvalue);
+			} else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) {
+				data += 's';
+				data += metadata_item.second.decode_string();
+				data += '\0';
+			} else if (metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED) {
+				data += 'i';
+				put_u64((uint64_t)metadata_item.second.as_int(/*is_signed=*/true));
+			} else {
+				data += 'u';
+				put_u64(metadata_item.second.as_int(/*is_signed=*/false));
+			}
+		}
+		f << escape_c_string(data);
+	}
+
+	void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map) {
 		if (metadata_map.empty()) {
 			f << "metadata_map()";
-			return;
-		} else if (serialize) {
-			// Creating thousands metadata_map objects using initializer lists in a single function results in one of:
-			// 1. Megabytes of stack usage (with __attribute__((optnone))).
-			// 2. Minutes of compile time (without __attribute__((optnone))).
-			// So, don't create them.
-			std::string data;
-			auto put_u64 = [&](uint64_t value) {
-				for (size_t count = 0; count < 8; count++) {
-					data += (char)(value >> 56);
-					value <<= 8;
-				}
-			};
-			for (auto metadata_item : metadata_map) {
-				if (!metadata_item.first.isPublic())
-					continue;
-				if (metadata_item.second.size() > 64 && (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) == 0) {
-					f << indent << "/* attribute " << metadata_item.first.str().substr(1) << " is over 64 bits wide */\n";
-					continue;
-				}
-				data += metadata_item.first.str().substr(1) + '\0';
-				// In Yosys, a real is a type of string.
-				if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) {
-					double dvalue = std::stod(metadata_item.second.decode_string());
-					uint64_t uvalue;
-					static_assert(sizeof(dvalue) == sizeof(uvalue), "double must be 64 bits in size");
-					memcpy(&uvalue, &dvalue, sizeof(uvalue));
-					data += 'd';
-					put_u64(uvalue);
-				} else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) {
-					data += 's';
-					data += metadata_item.second.decode_string();
-					data += '\0';
-				} else if (metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED) {
-					data += 'i';
-					put_u64((uint64_t)metadata_item.second.as_int(/*is_signed=*/true));
-				} else {
-					data += 'u';
-					put_u64(metadata_item.second.as_int(/*is_signed=*/false));
-				}
-			}
-			f << "metadata::deserialize(\n";
-			inc_indent();
-				f << indent << escape_c_string(data) << "\n";
-			dec_indent();
-			f << indent << ")";
 		} else {
 			f << "metadata_map({\n";
 			inc_indent();
@@ -2361,14 +2357,18 @@ struct CxxrtlWorker {
 		}
 	}
 
-	void dump_debug_attrs(const RTLIL::AttrObject *object)
+	void dump_debug_attrs(const RTLIL::AttrObject *object, bool serialize = true)
 	{
 		dict<RTLIL::IdString, RTLIL::Const> attributes = object->attributes;
 		// Inherently necessary to get access to the object, so a waste of space to emit.
 		attributes.erase(ID::hdlname);
 		// Internal Yosys attribute that should be removed but isn't.
 		attributes.erase(ID::module_not_derived);
-		dump_metadata_map(attributes);
+		if (serialize) {
+			dump_serialized_metadata(attributes);
+		} else {
+			dump_metadata_map(attributes);
+		}
 	}
 
 	void dump_debug_info_method(RTLIL::Module *module)
@@ -2391,7 +2391,7 @@ struct CxxrtlWorker {
 				// The module is responsible for adding its own scope.
 				f << indent << "scopes->add(path.empty() ? path : path.substr(0, path.size() - 1), ";
 				f << escape_cxx_string(get_hdl_name(module)) << ", ";
-				dump_debug_attrs(module);
+				dump_debug_attrs(module, /*serialize=*/false);
 				f << ", std::move(cell_attrs));\n";
 				count_scopes++;
 				// If there were any submodules that were flattened, the module is also responsible for adding them.
@@ -2401,11 +2401,11 @@ struct CxxrtlWorker {
 						auto module_attrs = scopeinfo_attributes(cell, ScopeinfoAttrs::Module);
 						auto cell_attrs = scopeinfo_attributes(cell, ScopeinfoAttrs::Cell);
 						cell_attrs.erase(ID::module_not_derived);
-						f << indent << "scopes->add(path + " << escape_cxx_string(get_hdl_name(cell)) << ", ";
+						f << indent << "scopes->add(path, " << escape_cxx_string(get_hdl_name(cell)) << ", ";
 						f << escape_cxx_string(cell->get_string_attribute(ID(module))) << ", ";
-						dump_metadata_map(module_attrs);
+						dump_serialized_metadata(module_attrs);
 						f << ", ";
-						dump_metadata_map(cell_attrs);
+						dump_serialized_metadata(cell_attrs);
 						f << ");\n";
 					} else log_assert(false && "Unknown $scopeinfo type");
 					count_scopes++;
@@ -2473,7 +2473,7 @@ struct CxxrtlWorker {
 							if (has_driven_sync + has_driven_comb + has_undriven > 1)
 								count_mixed_driver++;
 
-							f << indent << "items->add(path + " << escape_cxx_string(get_hdl_name(wire));
+							f << indent << "items->add(path, " << escape_cxx_string(get_hdl_name(wire));
 							f << ", debug_item(" << mangle(wire) << ", " << wire->start_offset;
 							bool first = true;
 							for (auto flag : flags) {
@@ -2494,7 +2494,7 @@ struct CxxrtlWorker {
 						case WireType::ALIAS: {
 							// Alias of a member wire
 							const RTLIL::Wire *aliasee = debug_wire_type.sig_subst.as_wire();
-							f << indent << "items->add(path + " << escape_cxx_string(get_hdl_name(wire));
+							f << indent << "items->add(path, " << escape_cxx_string(get_hdl_name(wire));
 							f << ", debug_item(";
 							// If the aliasee is an outline, then the alias must be an outline, too; otherwise downstream
 							// tooling has no way to find out about the outline.
@@ -2513,7 +2513,7 @@ struct CxxrtlWorker {
 							f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = ";
 							dump_const(debug_wire_type.sig_subst.as_const());
 							f << ";\n";
-							f << indent << "items->add(path + " << escape_cxx_string(get_hdl_name(wire));
+							f << indent << "items->add(path, " << escape_cxx_string(get_hdl_name(wire));
 							f << ", debug_item(const_" << mangle(wire) << ", " << wire->start_offset << "), ";
 							dump_debug_attrs(wire);
 							f << ");\n";
@@ -2522,7 +2522,7 @@ struct CxxrtlWorker {
 						}
 						case WireType::OUTLINE: {
 							// Localized or inlined, but rematerializable wire
-							f << indent << "items->add(path + " << escape_cxx_string(get_hdl_name(wire));
+							f << indent << "items->add(path, " << escape_cxx_string(get_hdl_name(wire));
 							f << ", debug_item(debug_eval_outline, " << mangle(wire) << ", " << wire->start_offset << "), ";
 							dump_debug_attrs(wire);
 							f << ");\n";
@@ -2540,7 +2540,7 @@ struct CxxrtlWorker {
 					for (auto &mem : mod_memories[module]) {
 						if (!mem.memid.isPublic())
 							continue;
-						f << indent << "items->add(path + " << escape_cxx_string(mem.packed ? get_hdl_name(mem.cell) : get_hdl_name(mem.mem));
+						f << indent << "items->add(path, " << escape_cxx_string(mem.packed ? get_hdl_name(mem.cell) : get_hdl_name(mem.mem));
 						f << ", debug_item(" << mangle(&mem) << ", ";
 						f << mem.start_offset << "), ";
 						if (mem.packed) {
@@ -2560,7 +2560,7 @@ struct CxxrtlWorker {
 					const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
 					f << indent << mangle(cell) << access;
 					f << "debug_info(items, scopes, path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ", ";
-					dump_debug_attrs(cell);
+					dump_debug_attrs(cell, /*serialize=*/false);
 					f << ");\n";
 				}
 			}
diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
index 068dc350535..8f47bc18990 100644
--- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
+++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
@@ -1466,6 +1466,11 @@ struct debug_items {
 			});
 	}
 
+	// This overload exists to reduce excessive stack slot allocation in `CXXRTL_EXTREMELY_COLD void debug_info()`.
+	void add(const std::string &base_path, const char *path, debug_item &&item, const char *serialized_item_attrs) {
+		add(base_path + path, std::move(item), metadata::deserialize(serialized_item_attrs));
+	}
+
 	size_t count(const std::string &path) const {
 		if (table.count(path) == 0)
 			return 0;
@@ -1512,6 +1517,11 @@ struct debug_scopes {
 		scope.cell_attrs = std::unique_ptr<debug_attrs>(new debug_attrs { cell_attrs });
 	}
 
+	// This overload exists to reduce excessive stack slot allocation in `CXXRTL_EXTREMELY_COLD void debug_info()`.
+	void add(const std::string &base_path, const char *path, const char *module_name, const char *serialized_module_attrs, const char *serialized_cell_attrs) {
+		add(base_path + path, module_name, metadata::deserialize(serialized_module_attrs), metadata::deserialize(serialized_cell_attrs));
+	}
+
 	size_t contains(const std::string &path) const {
 		return table.count(path);
 	}

From 6e003e1af67ce4709c63812f6e1d1732ada9ba15 Mon Sep 17 00:00:00 2001
From: Catherine <whitequark@whitequark.org>
Date: Wed, 8 May 2024 03:37:14 +0000
Subject: [PATCH 039/499] cxxrtl: minimize stack space consumed by
 `debug_info()`.

This commit uses parameter packs to sink `debug_item()` construction
into the `debug_info()`-specific `add()` overload. This makes the stack
space use sub-linear in typical case rather than linear (which is still
the worst case). Oddly, the stack slots that get allocated now are all
for the `0` literal for `lsb_offset`. This could be fixed by allocating
numbers statically but the existing reduction in stack use of ~98% for
a representative example (Minerva SoC) should be enough.
---
 backends/cxxrtl/cxxrtl_backend.cc       | 55 ++++++++++++++-----------
 backends/cxxrtl/runtime/cxxrtl/cxxrtl.h |  5 ++-
 2 files changed, 34 insertions(+), 26 deletions(-)

diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index d839bd86709..703494682a8 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -2473,20 +2473,22 @@ struct CxxrtlWorker {
 							if (has_driven_sync + has_driven_comb + has_undriven > 1)
 								count_mixed_driver++;
 
-							f << indent << "items->add(path, " << escape_cxx_string(get_hdl_name(wire));
-							f << ", debug_item(" << mangle(wire) << ", " << wire->start_offset;
-							bool first = true;
-							for (auto flag : flags) {
-								if (first) {
-									first = false;
-									f << ", ";
-								} else {
-									f << "|";
+							f << indent << "items->add(path, " << escape_cxx_string(get_hdl_name(wire)) << ", ";
+							dump_debug_attrs(wire);
+							f << ", " << mangle(wire);
+							if (wire->start_offset != 0 || !flags.empty()) {
+								f << ", " << wire->start_offset;
+								bool first = true;
+								for (auto flag : flags) {
+									if (first) {
+										first = false;
+										f << ", ";
+									} else {
+										f << "|";
+									}
+									f << "debug_item::" << flag;
 								}
-								f << "debug_item::" << flag;
 							}
-							f << "), ";
-							dump_debug_attrs(wire);
 							f << ");\n";
 							count_member_wires++;
 							break;
@@ -2494,16 +2496,18 @@ struct CxxrtlWorker {
 						case WireType::ALIAS: {
 							// Alias of a member wire
 							const RTLIL::Wire *aliasee = debug_wire_type.sig_subst.as_wire();
-							f << indent << "items->add(path, " << escape_cxx_string(get_hdl_name(wire));
-							f << ", debug_item(";
+							f << indent << "items->add(path, " << escape_cxx_string(get_hdl_name(wire)) << ", ";
+							dump_debug_attrs(aliasee);
+							f << ", ";
 							// If the aliasee is an outline, then the alias must be an outline, too; otherwise downstream
 							// tooling has no way to find out about the outline.
 							if (debug_wire_types[aliasee].is_outline())
 								f << "debug_eval_outline";
 							else
 								f << "debug_alias()";
-							f << ", " << mangle(aliasee) << ", " << wire->start_offset << "), ";
-							dump_debug_attrs(aliasee);
+							f << ", " << mangle(aliasee);
+							if (wire->start_offset != 0)
+								f << ", " << wire->start_offset;
 							f << ");\n";
 							count_alias_wires++;
 							break;
@@ -2513,18 +2517,22 @@ struct CxxrtlWorker {
 							f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = ";
 							dump_const(debug_wire_type.sig_subst.as_const());
 							f << ";\n";
-							f << indent << "items->add(path, " << escape_cxx_string(get_hdl_name(wire));
-							f << ", debug_item(const_" << mangle(wire) << ", " << wire->start_offset << "), ";
+							f << indent << "items->add(path, " << escape_cxx_string(get_hdl_name(wire)) << ", ";
 							dump_debug_attrs(wire);
+							f << ", const_" << mangle(wire);
+							if (wire->start_offset != 0)
+								f << ", " << wire->start_offset;
 							f << ");\n";
 							count_const_wires++;
 							break;
 						}
 						case WireType::OUTLINE: {
 							// Localized or inlined, but rematerializable wire
-							f << indent << "items->add(path, " << escape_cxx_string(get_hdl_name(wire));
-							f << ", debug_item(debug_eval_outline, " << mangle(wire) << ", " << wire->start_offset << "), ";
+							f << indent << "items->add(path, " << escape_cxx_string(get_hdl_name(wire)) << ", ";
 							dump_debug_attrs(wire);
+							f << ", debug_eval_outline, " << mangle(wire);
+							if (wire->start_offset != 0)
+								f << ", " << wire->start_offset;
 							f << ");\n";
 							count_inline_wires++;
 							break;
@@ -2540,15 +2548,14 @@ struct CxxrtlWorker {
 					for (auto &mem : mod_memories[module]) {
 						if (!mem.memid.isPublic())
 							continue;
-						f << indent << "items->add(path, " << escape_cxx_string(mem.packed ? get_hdl_name(mem.cell) : get_hdl_name(mem.mem));
-						f << ", debug_item(" << mangle(&mem) << ", ";
-						f << mem.start_offset << "), ";
+						f << indent << "items->add(path, " << escape_cxx_string(mem.packed ? get_hdl_name(mem.cell) : get_hdl_name(mem.mem)) << ", ";
 						if (mem.packed) {
 							dump_debug_attrs(mem.cell);
 						} else {
 							dump_debug_attrs(mem.mem);
 						}
-						f << ");\n";
+						f << ", " << mangle(&mem) << ", ";
+						f << mem.start_offset << ");\n";
 					}
 				}
 			dec_indent();
diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
index 8f47bc18990..057d34cf906 100644
--- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
+++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
@@ -1467,8 +1467,9 @@ struct debug_items {
 	}
 
 	// This overload exists to reduce excessive stack slot allocation in `CXXRTL_EXTREMELY_COLD void debug_info()`.
-	void add(const std::string &base_path, const char *path, debug_item &&item, const char *serialized_item_attrs) {
-		add(base_path + path, std::move(item), metadata::deserialize(serialized_item_attrs));
+	template<class... T>
+	void add(const std::string &base_path, const char *path, const char *serialized_item_attrs, T&&... args) {
+		add(base_path + path, debug_item(std::forward<T>(args)...), metadata::deserialize(serialized_item_attrs));
 	}
 
 	size_t count(const std::string &path) const {

From 7ab43dc1b72109624a575895df26ef36f1b2eb4a Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 8 May 2024 08:30:30 +0200
Subject: [PATCH 040/499] Update ABC with Windows fixes

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 48594e1a381..12d1c31194e 100644
--- a/Makefile
+++ b/Makefile
@@ -166,7 +166,7 @@ bumpversion:
 # is just a symlink to your actual ABC working directory, as 'make mrproper'
 # will remove the 'abc' directory and you do not want to accidentally
 # delete your work on ABC..
-ABCREV = 03da96f
+ABCREV = 237d813
 ABCPULL = 1
 ABCURL ?= https://github.com/YosysHQ/abc
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)

From c1ad37779eea6211866a466026322416fb3a832f Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 8 May 2024 08:52:10 +0200
Subject: [PATCH 041/499] Release version 0.41

---
 CHANGELOG           | 13 ++++++++++++-
 Makefile            |  4 ++--
 docs/source/conf.py |  2 +-
 3 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index f42eaca27e1..e68e0a2a9c9 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,8 +2,19 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.40 .. Yosys 0.41-dev
+Yosys 0.40 .. Yosys 0.41
 --------------------------
+ * New commands and options
+    - Added "cellmatch" pass for picking out standard cells automatically. 
+
+ * Various
+    - Extended the experimental incremental JSON API to allow arbitrary
+      smtlib subexpressions.
+    - Added support for using ABCs library merging when providing multiple
+      liberty files.
+
+ * Verific support
+    - Expose library name as module attribute.
 
 Yosys 0.39 .. Yosys 0.40
 --------------------------
diff --git a/Makefile b/Makefile
index 12d1c31194e..2e33a9503e2 100644
--- a/Makefile
+++ b/Makefile
@@ -142,7 +142,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.40+68
+YOSYS_VER := 0.41
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -158,7 +158,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline a1bb025.. | wc -l`/;" Makefile
+#	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline a1bb025.. | wc -l`/;" Makefile
 
 # set 'ABCREV = default' to use abc/ as it is
 #
diff --git a/docs/source/conf.py b/docs/source/conf.py
index 182d033f8ce..fcd6adce863 100644
--- a/docs/source/conf.py
+++ b/docs/source/conf.py
@@ -5,7 +5,7 @@
 project = 'YosysHQ Yosys'
 author = 'YosysHQ GmbH'
 copyright ='2024 YosysHQ GmbH'
-yosys_ver = "0.40"
+yosys_ver = "0.41"
 
 # select HTML theme
 html_theme = 'furo'

From 561618002ada743b857e15e4f00765ebb016b926 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 8 May 2024 09:02:50 +0200
Subject: [PATCH 042/499] Next dev cycle

---
 CHANGELOG | 3 +++
 Makefile  | 4 ++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index e68e0a2a9c9..7c3ad481e9e 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 List of major changes and improvements between releases
 =======================================================
 
+Yosys 0.41 .. Yosys 0.42-dev
+--------------------------
+
 Yosys 0.40 .. Yosys 0.41
 --------------------------
  * New commands and options
diff --git a/Makefile b/Makefile
index 2e33a9503e2..55c6a3f02b0 100644
--- a/Makefile
+++ b/Makefile
@@ -142,7 +142,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.41
+YOSYS_VER := 0.41+0
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -158,7 +158,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-#	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline a1bb025.. | wc -l`/;" Makefile
+	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline c1ad377.. | wc -l`/;" Makefile
 
 # set 'ABCREV = default' to use abc/ as it is
 #

From f806987d582be36605163d04f107452a4157ee0b Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 8 May 2024 12:00:18 +0200
Subject: [PATCH 043/499] Add PR template

---
 .github/PULL_REQUEST_TEMPLATE.md | 5 +++++
 1 file changed, 5 insertions(+)
 create mode 100644 .github/PULL_REQUEST_TEMPLATE.md

diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md
new file mode 100644
index 00000000000..82daf609d36
--- /dev/null
+++ b/.github/PULL_REQUEST_TEMPLATE.md
@@ -0,0 +1,5 @@
+_What are the reasons/motivation for this change?_
+
+_Explain how this is achieved._
+
+_If applicable, please suggest to reviewers how they can test the change._

From 82a4a87c97e8755e915bade43cf4f8010787ac42 Mon Sep 17 00:00:00 2001
From: Ethan Mahintorabi <ethanmoon@google.com>
Date: Wed, 8 May 2024 20:28:37 +0000
Subject: [PATCH 044/499] Fixes error with vector indicies of the form [2:7]
 [-12:7]

Make sure that we correctly adjust the value to align it to a zero
indexed list with lsb = 0

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
---
 frontends/verific/verific.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index a18f9fc877b..b4b0664d341 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2164,7 +2164,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 				// that the indicies match LSB = 0 order to match the std::vector
 				// to SigSpec LSB = 0 precondition.
 				if (lsb_index > msb_index) {
-					port_offset = abs(port_offset - lsb_index);
+					port_offset = abs(port_offset - (lsb_index - min(msb_index, lsb_index)));
 				}
 			}
 			IdString port_name_id = RTLIL::escape_id(port_name);

From 699049b218e7cb99799ff78b6af4c3363f1e5b4b Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 9 May 2024 09:26:12 +1200
Subject: [PATCH 045/499] ci: Combine extra build flow yml

Currently only vs.yml and wasi.yml since emscripten is on the chopping block.
Use fkirc/skip-duplicate-actions to skip duplicate action runs.
---
 .github/workflows/extra-builds.yml | 79 ++++++++++++++++++++++++++++++
 .github/workflows/vs.yml           | 33 -------------
 .github/workflows/wasi.yml         | 32 ------------
 3 files changed, 79 insertions(+), 65 deletions(-)
 create mode 100644 .github/workflows/extra-builds.yml
 delete mode 100644 .github/workflows/vs.yml
 delete mode 100644 .github/workflows/wasi.yml

diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml
new file mode 100644
index 00000000000..64a4da16778
--- /dev/null
+++ b/.github/workflows/extra-builds.yml
@@ -0,0 +1,79 @@
+name: Test extra build flows
+
+on: [push, pull_request]
+
+jobs:
+  pre_job:
+    runs-on: ubuntu-latest
+    outputs:
+      should_skip: ${{ steps.skip_check.outputs.should_skip }}
+    steps:
+      - id: skip_check
+        uses: fkirc/skip-duplicate-actions@v5
+        with:
+          paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]'
+          # cancel previous builds if a new commit is pushed
+          cancel_others: 'true'
+
+  vs-prep:
+    name: Prepare Visual Studio build
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4
+        with:
+         submodules: true
+      - name: Build
+        run: make vcxsrc YOSYS_VER=latest
+      - uses: actions/upload-artifact@v4
+        with:
+          name: vcxsrc
+          path: yosys-win32-vcxsrc-latest.zip
+  
+  vs-build:
+    name: Visual Studio build
+    runs-on: windows-2019
+    needs: yosys-vcxsrc, pre_job
+    if: needs.pre_job.outputs.should_skip != 'true'
+    steps:  
+      - uses: actions/download-artifact@v4
+        with:
+          name: vcxsrc
+          path: .
+      - name: unzip
+        run: unzip yosys-win32-vcxsrc-latest.zip
+      - name: setup-msbuild
+        uses: microsoft/setup-msbuild@v1
+      - name: MSBuild
+        working-directory: yosys-win32-vcxsrc-latest
+        run: msbuild YosysVS.sln /p:PlatformToolset=v142 /p:Configuration=Release /p:WindowsTargetPlatformVersion=10.0.17763.0
+
+  wasi-build:
+    name: WASI build
+    needs: pre_job
+    if: needs.pre_job.outputs.should_skip != 'true'
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4
+        with:
+         submodules: true
+      - name: Build
+        run: |
+          WASI_SDK=wasi-sdk-19.0
+          WASI_SDK_URL=https://github.com/WebAssembly/wasi-sdk/releases/download/wasi-sdk-19/wasi-sdk-19.0-linux.tar.gz
+          if ! [ -d ${WASI_SDK} ]; then curl -L ${WASI_SDK_URL} | tar xzf -; fi
+
+          mkdir -p build
+          cat > build/Makefile.conf <<END
+          export PATH := $(pwd)/${WASI_SDK}/bin:${PATH}
+          WASI_SYSROOT := $(pwd)/${WASI_SDK}/share/wasi-sysroot
+
+          CONFIG := wasi
+          PREFIX := /
+
+          ENABLE_TCL := 0
+          ENABLE_READLINE := 0
+          ENABLE_PLUGINS := 0
+          ENABLE_ZLIB := 0
+          END
+
+          make -C build -f ../Makefile CXX=clang -j$(nproc)
diff --git a/.github/workflows/vs.yml b/.github/workflows/vs.yml
deleted file mode 100644
index 0647cff1a34..00000000000
--- a/.github/workflows/vs.yml
+++ /dev/null
@@ -1,33 +0,0 @@
-name: Visual Studio Build
-
-on: [push, pull_request]
-
-jobs:
-  yosys-vcxsrc:
-    runs-on: ubuntu-latest
-    steps:
-      - uses: actions/checkout@v4
-        with:
-         submodules: true
-      - name: Build
-        run: make vcxsrc YOSYS_VER=latest
-      - uses: actions/upload-artifact@v4
-        with:
-          name: vcxsrc
-          path: yosys-win32-vcxsrc-latest.zip
-
-  build:
-    runs-on: windows-2019
-    needs: yosys-vcxsrc
-    steps:
-      - uses: actions/download-artifact@v4
-        with:
-          name: vcxsrc
-          path: .
-      - name: unzip
-        run: unzip yosys-win32-vcxsrc-latest.zip
-      - name: setup-msbuild
-        uses: microsoft/setup-msbuild@v1
-      - name: MSBuild
-        working-directory: yosys-win32-vcxsrc-latest
-        run: msbuild YosysVS.sln /p:PlatformToolset=v142 /p:Configuration=Release /p:WindowsTargetPlatformVersion=10.0.17763.0
diff --git a/.github/workflows/wasi.yml b/.github/workflows/wasi.yml
deleted file mode 100644
index d65a9622799..00000000000
--- a/.github/workflows/wasi.yml
+++ /dev/null
@@ -1,32 +0,0 @@
-name: WASI Build
-
-on: [push, pull_request]
-
-jobs:
-  wasi:
-    runs-on: ubuntu-latest
-    steps:
-      - uses: actions/checkout@v4
-        with:
-         submodules: true
-      - name: Build
-        run: |
-          WASI_SDK=wasi-sdk-19.0
-          WASI_SDK_URL=https://github.com/WebAssembly/wasi-sdk/releases/download/wasi-sdk-19/wasi-sdk-19.0-linux.tar.gz
-          if ! [ -d ${WASI_SDK} ]; then curl -L ${WASI_SDK_URL} | tar xzf -; fi
-
-          mkdir -p build
-          cat > build/Makefile.conf <<END
-          export PATH := $(pwd)/${WASI_SDK}/bin:${PATH}
-          WASI_SYSROOT := $(pwd)/${WASI_SDK}/share/wasi-sysroot
-
-          CONFIG := wasi
-          PREFIX := /
-
-          ENABLE_TCL := 0
-          ENABLE_READLINE := 0
-          ENABLE_PLUGINS := 0
-          ENABLE_ZLIB := 0
-          END
-
-          make -C build -f ../Makefile CXX=clang -j$(nproc)

From 7bcef637a45c2254f5aa32d550b94f7ac5253401 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 9 May 2024 09:26:17 +1200
Subject: [PATCH 046/499] extra-builds.yml: Fix prereq list

---
 .github/workflows/extra-builds.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml
index 64a4da16778..3623193130d 100644
--- a/.github/workflows/extra-builds.yml
+++ b/.github/workflows/extra-builds.yml
@@ -32,7 +32,7 @@ jobs:
   vs-build:
     name: Visual Studio build
     runs-on: windows-2019
-    needs: yosys-vcxsrc, pre_job
+    needs: [vs-prep, pre_job]
     if: needs.pre_job.outputs.should_skip != 'true'
     steps:  
       - uses: actions/download-artifact@v4

From 174c7ebf1729cc54c7d57e6ee20eaf6b4eb55fb9 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 9 May 2024 09:26:18 +1200
Subject: [PATCH 047/499] extra-builds.yml: Add concurrent_skipping

---
 .github/workflows/extra-builds.yml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml
index 3623193130d..cc2998e40b1 100644
--- a/.github/workflows/extra-builds.yml
+++ b/.github/workflows/extra-builds.yml
@@ -14,6 +14,8 @@ jobs:
           paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]'
           # cancel previous builds if a new commit is pushed
           cancel_others: 'true'
+          # only run on push *or* pull_request, not both
+          concurrent_skipping: 'same_content_newer'
 
   vs-prep:
     name: Prepare Visual Studio build

From cdce505f82335eeff6a002ee2276ee8771b5d425 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 9 May 2024 09:26:18 +1200
Subject: [PATCH 048/499] ci: Add skip check to other actions

---
 .github/workflows/test-docs.yml  | 15 +++++++++++++++
 .github/workflows/test-linux.yml | 16 ++++++++++++++++
 .github/workflows/test-macos.yml | 16 ++++++++++++++++
 3 files changed, 47 insertions(+)

diff --git a/.github/workflows/test-docs.yml b/.github/workflows/test-docs.yml
index f6bcd33eb1b..16de7735663 100644
--- a/.github/workflows/test-docs.yml
+++ b/.github/workflows/test-docs.yml
@@ -6,7 +6,22 @@ on:
     - main
 
 jobs:
+  pre_job:
+    runs-on: ubuntu-latest
+    outputs:
+      should_skip: ${{ steps.skip_check.outputs.should_skip }}
+    steps:
+      - id: skip_check
+        uses: fkirc/skip-duplicate-actions@v5
+        with:
+          # cancel previous builds if a new commit is pushed
+          cancel_others: 'true'
+          # only run on push *or* pull_request, not both
+          concurrent_skipping: 'same_content_newer'
+
   test-docs:
+    needs: pre_job
+    if: needs.pre_job.outputs.should_skip != 'true'
     runs-on: ubuntu-latest
     steps:
       - name: Install Dependencies
diff --git a/.github/workflows/test-linux.yml b/.github/workflows/test-linux.yml
index a75873d8995..911b3b66e4d 100644
--- a/.github/workflows/test-linux.yml
+++ b/.github/workflows/test-linux.yml
@@ -3,7 +3,23 @@ name: Build and run tests (Linux)
 on: [push, pull_request]
 
 jobs:
+  pre_job:
+    runs-on: ubuntu-latest
+    outputs:
+      should_skip: ${{ steps.skip_check.outputs.should_skip }}
+    steps:
+      - id: skip_check
+        uses: fkirc/skip-duplicate-actions@v5
+        with:
+          paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]'
+          # cancel previous builds if a new commit is pushed
+          cancel_others: 'true'
+          # only run on push *or* pull_request, not both
+          concurrent_skipping: 'same_content_newer'
+
   test-linux:
+    needs: pre_job
+    if: needs.pre_job.outputs.should_skip != 'true'
     runs-on: ${{ matrix.os.id }}
     strategy:
       matrix:
diff --git a/.github/workflows/test-macos.yml b/.github/workflows/test-macos.yml
index 37b66df9bec..cbba8adbd66 100644
--- a/.github/workflows/test-macos.yml
+++ b/.github/workflows/test-macos.yml
@@ -3,7 +3,23 @@ name: Build and run tests (macOS)
 on: [push, pull_request]
 
 jobs:
+  pre_job:
+    runs-on: ubuntu-latest
+    outputs:
+      should_skip: ${{ steps.skip_check.outputs.should_skip }}
+    steps:
+      - id: skip_check
+        uses: fkirc/skip-duplicate-actions@v5
+        with:
+          paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]'
+          # cancel previous builds if a new commit is pushed
+          cancel_others: 'true'
+          # only run on push *or* pull_request, not both
+          concurrent_skipping: 'same_content_newer'
+
   test-macos:
+    needs: pre_job
+    if: needs.pre_job.outputs.should_skip != 'true'
     runs-on: ${{ matrix.os.id }}
     strategy:
       matrix:

From a9eca9072ea4f00a568eaf26817a9e5da1a655f5 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 9 May 2024 09:26:43 +1200
Subject: [PATCH 049/499] ci: Drop emcc

---
 .github/workflows/emcc.yml | 20 --------------------
 1 file changed, 20 deletions(-)
 delete mode 100644 .github/workflows/emcc.yml

diff --git a/.github/workflows/emcc.yml b/.github/workflows/emcc.yml
deleted file mode 100644
index b883cfa0a8a..00000000000
--- a/.github/workflows/emcc.yml
+++ /dev/null
@@ -1,20 +0,0 @@
-name: Emscripten Build
-
-on: [push, pull_request]
-
-jobs:
-  emcc:
-    runs-on: ubuntu-latest
-    steps:
-      - uses: mymindstorm/setup-emsdk@v14
-      - uses: actions/checkout@v4
-        with:
-         submodules: true
-      - name: Build
-        run: |
-          make config-emcc
-          make YOSYS_VER=latest
-      - uses: actions/upload-artifact@v4
-        with:
-          name: yosysjs
-          path: yosysjs-latest.zip

From 878ac021793829e997e8ccdbd09c93e8c89f132a Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 9 May 2024 09:39:27 +1200
Subject: [PATCH 050/499] ci: Add skip check to test-verific

---
 .github/workflows/test-verific.yml | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml
index ef7fa3829d8..54d9487acfb 100644
--- a/.github/workflows/test-verific.yml
+++ b/.github/workflows/test-verific.yml
@@ -3,7 +3,25 @@ name: Build and run tests with Verific (Linux)
 on: [push, pull_request]
 
 jobs:
+  pre_job:
+    runs-on: ubuntu-latest
+    outputs:
+      should_skip: ${{ steps.skip_check.outputs.should_skip }}
+    steps:
+      - id: skip_check
+        uses: fkirc/skip-duplicate-actions@v5
+        with:
+          paths_ignore: '["**/README.md"]'
+          # don't cancel previous builds
+          cancel_others: 'true'
+          # only run on push *or* pull_request, not both
+          concurrent_skipping: 'same_content_newer'
+          # we have special actions when running on main, so this should be off
+          skip_after_successful_duplicate: 'false'
+
   test-verific:
+    needs: pre_job
+    if: needs.pre_job.outputs.should_skip != 'true'
     runs-on: [self-hosted, linux, x64]
     steps:
       - name: Checkout Yosys

From 10686cd2df240002769da2f9d7ce32755b98d119 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Thu, 9 May 2024 00:16:31 +0000
Subject: [PATCH 051/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 46778b6d53a..3f1941c478b 100644
--- a/Makefile
+++ b/Makefile
@@ -142,7 +142,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.41+0
+YOSYS_VER := 0.41+8
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 6df1337d71a7c91f4512777dfdc507a4c3a29a2d Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 9 May 2024 18:16:05 +1200
Subject: [PATCH 052/499] ci: Update to Node.JS 20

---
 .github/workflows/extra-builds.yml | 2 +-
 .github/workflows/test-docs.yml    | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml
index cc2998e40b1..4c4d12dfbe6 100644
--- a/.github/workflows/extra-builds.yml
+++ b/.github/workflows/extra-builds.yml
@@ -44,7 +44,7 @@ jobs:
       - name: unzip
         run: unzip yosys-win32-vcxsrc-latest.zip
       - name: setup-msbuild
-        uses: microsoft/setup-msbuild@v1
+        uses: microsoft/setup-msbuild@v2
       - name: MSBuild
         working-directory: yosys-win32-vcxsrc-latest
         run: msbuild YosysVS.sln /p:PlatformToolset=v142 /p:Configuration=Release /p:WindowsTargetPlatformVersion=10.0.17763.0
diff --git a/.github/workflows/test-docs.yml b/.github/workflows/test-docs.yml
index 16de7735663..7b3906c52ca 100644
--- a/.github/workflows/test-docs.yml
+++ b/.github/workflows/test-docs.yml
@@ -43,7 +43,7 @@ jobs:
           echo "procs=$(nproc)" >> $GITHUB_ENV
 
       - name: Checkout Yosys
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4
         with:
          submodules: true
       - name: Build yosys

From b9b1da826072d0bfe14b538eb7792f312831ddbe Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 9 May 2024 18:17:04 +1200
Subject: [PATCH 053/499] extra-builds.yml: Add skip check to vs-prep

---
 .github/workflows/extra-builds.yml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml
index 4c4d12dfbe6..260394a3ffe 100644
--- a/.github/workflows/extra-builds.yml
+++ b/.github/workflows/extra-builds.yml
@@ -20,6 +20,8 @@ jobs:
   vs-prep:
     name: Prepare Visual Studio build
     runs-on: ubuntu-latest
+    needs: [pre_job]
+    if: needs.pre_job.outputs.should_skip != 'true'
     steps:
       - uses: actions/checkout@v4
         with:

From 93148a87df3f2097a262ffe7c5b2a55b014b0e83 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 9 May 2024 09:22:48 +0200
Subject: [PATCH 054/499] Modify abc directory content check

---
 Makefile | 31 +++++++++++++++++--------------
 1 file changed, 17 insertions(+), 14 deletions(-)

diff --git a/Makefile b/Makefile
index 3f1941c478b..507d46f230d 100644
--- a/Makefile
+++ b/Makefile
@@ -784,23 +784,26 @@ $(PROGRAM_PREFIX)yosys-config: misc/yosys-config.in
 
 check-git-abc:
 	@if [ ! -d "$(YOSYS_SRC)/abc" ]; then \
-	    echo "Error: The 'abc' directory does not exist."; \
-			echo "Initialize the submodule: Run 'git submodule update --init' to set up 'abc' as a submodule."; \
-	    exit 1; \
+		echo "Error: The 'abc' directory does not exist."; \
+		echo "Initialize the submodule: Run 'git submodule update --init' to set up 'abc' as a submodule."; \
+		exit 1; \
 	elif git -C "$(YOSYS_SRC)" submodule status abc 2>/dev/null | grep -q '^ '; then \
-	    echo "'abc' is a git submodule. Continuing."; \
-	    exit 0; \
+		echo "'abc' is a git submodule. Continuing."; \
+		exit 0; \
+	elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && ! grep -q '\$$Format:%h\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \
+		echo "'abc' comes from a tarball. Continuing."; \
+		exit 0; \
 	elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && grep -q '\$$Format:%h\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \
-	    echo "Error: 'abc' is not configured as a git submodule."; \
-	    echo "To resolve this:"; \
-	    echo "1. Back up your changes: Save any modifications from the 'abc' directory to another location."; \
-	    echo "2. Remove the existing 'abc' directory: Delete the 'abc' directory and all its contents."; \
-	    echo "3. Initialize the submodule: Run 'git submodule update --init' to set up 'abc' as a submodule."; \
-	    echo "4. Reapply your changes: Move your saved changes back to the 'abc' directory, if necessary."; \
-	    exit 1; \
+		echo "Error: 'abc' is not configured as a git submodule."; \
+		echo "To resolve this:"; \
+		echo "1. Back up your changes: Save any modifications from the 'abc' directory to another location."; \
+		echo "2. Remove the existing 'abc' directory: Delete the 'abc' directory and all its contents."; \
+		echo "3. Initialize the submodule: Run 'git submodule update --init' to set up 'abc' as a submodule."; \
+		echo "4. Reapply your changes: Move your saved changes back to the 'abc' directory, if necessary."; \
+		exit 1; \
 	else \
-	    echo "'abc' comes from a tarball. Continuing."; \
-	    exit 0; \
+		echo "Initialize the submodule: Run 'git submodule update --init' to set up 'abc' as a submodule."; \
+		exit 1; \
 	fi
 
 ABC_SOURCES := $(wildcard $(YOSYS_SRC)/abc/*)

From fd84a3378eee639663005577c0b180b83cbbbd91 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Thu, 9 May 2024 18:31:18 +0200
Subject: [PATCH 055/499] docs: Document $lut and $sop

---
 .../yosys_internals/formats/cell_library.rst  | 44 ++++++++++++++++++-
 1 file changed, 42 insertions(+), 2 deletions(-)

diff --git a/docs/source/yosys_internals/formats/cell_library.rst b/docs/source/yosys_internals/formats/cell_library.rst
index 2b8dc300154..69e82774c1f 100644
--- a/docs/source/yosys_internals/formats/cell_library.rst
+++ b/docs/source/yosys_internals/formats/cell_library.rst
@@ -661,6 +661,48 @@ The CONFIG parameter carries the following information:
 
 B is an array of concatenated 1-bit-wide unsigned integers to also be summed up.
 
+Arbitrary logic functions
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The ``$lut`` cell type implements a single-output LUT (lookup table).
+It implements an arbitrary logic function with its ``\LUT`` parameter to map
+input port ``\A`` to values of ``\Y`` output port values.
+In psuedocode: ``Y = \LUT[A]``.
+``\A`` has width set by parameter ``\WIDTH`` and ``\Y`` has a width of 1.
+Every logic function with a single bit output has a unique ``$lut``
+representation.
+
+The ``$sop`` cell type implements a sum-of-products expression, also known
+as disjunctive normal form (DNF). It implements an arbitrary logic function.
+Its structure mimics a programmable logic array (PLA).
+Output port ``\Y`` is the sum of products of the bits of the input port ``\A``
+as defined by parameter ``\TABLE``. ``\A`` is ``\WIDTH`` bits wide.
+The number of products in the sum is set by parameter ``\DEPTH``, and each
+product has two bits for each input bit - for the presence of the
+unnegated and negated version of said input bit in the product.
+Therefore the ``\TABLE`` parameter holds ``2 * \WIDTH * \DEPTH`` bits.
+
+For example:
+
+Let ``\WIDTH`` be 3. We would like to represent ``\Y =~\A[0] + \A[1]~\A[2]``.
+There are 2 products to be summed, so ``\DEPTH`` shall be 2.
+
+.. code-block::
+	~A[2]-----┐
+	 A[2]----┐|
+	~A[1]---┐||
+	 A[1]--┐|||
+	~A[0]-┐||||
+	 A[0]┐||||| product formula
+	     010000 ~\A[0]
+	     001001 \A[1]~\A[2]
+
+So the value of ``\TABLE`` will become ``010000001001``.
+
+Any logic function with a single bit output can be represented with
+``$sop`` but may have variously minimized or ordered summands represented
+in the ``\TABLE`` values.
+
 Specify rules
 ~~~~~~~~~~~~~
 
@@ -1192,6 +1234,4 @@ file via ABC using the abc pass.
 
 .. todo:: Add information about ``$slice`` and ``$concat`` cells.
 
-.. todo:: Add information about ``$lut`` and ``$sop`` cells.
-
 .. todo:: Add information about ``$alu``, ``$fa``, and ``$lcu`` cells.

From 69eb39582b36101f005ca6c73eb908ca708f3417 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Mon, 5 Feb 2024 21:48:25 +1300
Subject: [PATCH 056/499] ci: Introduce artifacts

Separates `test-linux` into `build-linux` and `test-linux`, wherein `build-` builds out of tree, and uploading the build for the `test-` job.
Tar compression is done to retain execution permissions when downloading build artifact.
When calling `make test`, override `TARGETS` and `EXTRA_TARGETS` to prevent rebuild.
---
 .github/workflows/test-linux.yml | 66 ++++++++++++++++++++++++++------
 .github/workflows/test-macos.yml |  9 ++++-
 2 files changed, 61 insertions(+), 14 deletions(-)

diff --git a/.github/workflows/test-linux.yml b/.github/workflows/test-linux.yml
index 911b3b66e4d..c4098edbeff 100644
--- a/.github/workflows/test-linux.yml
+++ b/.github/workflows/test-linux.yml
@@ -1,6 +1,12 @@
 name: Build and run tests (Linux)
 
-on: [push, pull_request]
+on:
+  pull_request:
+    branches:
+    - master
+  push:
+    branches:
+    - master
 
 jobs:
   pre_job:
@@ -17,7 +23,7 @@ jobs:
           # only run on push *or* pull_request, not both
           concurrent_skipping: 'same_content_newer'
 
-  test-linux:
+  build-linux:
     needs: pre_job
     if: needs.pre_job.outputs.should_skip != 'true'
     runs-on: ${{ matrix.os.id }}
@@ -123,25 +129,61 @@ jobs:
           make -j${{ env.procs }}
           make install
 
-      - name: Build yosys
+      - name: Build yosys out-of-tree
+        shell: bash
+        run: |
+          mkdir build
+          cd build
+          make -f ../Makefile config-${CC%%-*}
+          make -f ../Makefile -j${{ env.procs }} CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
+
+      - name: Log yosys-config output
+        run: |
+          ./yosys-config || true
+
+      - name: Compress build
         shell: bash
         run: |
-          make config-${CC%%-*}
-          make -j${{ env.procs }} CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
+          cd build
+          tar -cvf ../build.tar Makefile.conf share/ yosys yosys-*
 
       - name: Store build artifact
         if: (matrix.cpp_std == 'c++11') && (matrix.compiler == 'gcc-11')
         uses: actions/upload-artifact@v4
         with:
-          name: compiled-yosys
-          path: yosys
+          name: build-artifact
+          path: build.tar
+          retention-days: 1
 
-      - name: Run tests
-        if: (matrix.cpp_std == 'c++11') && (matrix.compiler == 'gcc-11')
+  test-linux:
+    name: Run tests
+    needs: build-linux
+    runs-on: ubuntu-latest
+    steps:
+      - name: Install Dependencies
+        shell: bash
+        run: |
+          sudo apt-get update
+          sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
+
+      - name: Runtime environment
         shell: bash
+        env:
+          WORKSPACE: ${{ github.workspace }}
         run: |
-          make -j${{ env.procs }} test CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
+          echo "procs=$(nproc)" >> $GITHUB_ENV
 
-      - name: Log yosys-config output
+      - name: Download build artifact
+        uses: actions/download-artifact@v4
+        with:
+          name: build-artifact
+
+      - name: Uncompress build
+        shell: bash
+        run:
+          tar -xvf build.tar
+
+      - name: Run tests
+        shell: bash
         run: |
-          ./yosys-config || true
+          make -j${{ env.procs }} test TARGETS= EXTRA_TARGETS=
diff --git a/.github/workflows/test-macos.yml b/.github/workflows/test-macos.yml
index cbba8adbd66..ed63c8f35b7 100644
--- a/.github/workflows/test-macos.yml
+++ b/.github/workflows/test-macos.yml
@@ -1,6 +1,12 @@
 name: Build and run tests (macOS)
 
-on: [push, pull_request]
+on:
+  pull_request:
+    branches:
+    - master
+  push:
+    branches:
+    - master
 
 jobs:
   pre_job:
@@ -27,7 +33,6 @@ jobs:
           - { id: macos-13, name: 'Ventura' }
         cpp_std:
           - 'c++11'
-          - 'c++17'
       fail-fast: false
     steps:
       - name: Install Dependencies

From 7873fe791eb60436ba48104b6b6443754097459c Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Mon, 5 Feb 2024 21:50:41 +1300
Subject: [PATCH 057/499] Makefile: ignore missing docs

e.g. when calling `make clean` out-of-tree
---
 Makefile | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 507d46f230d..f359ab76749 100644
--- a/Makefile
+++ b/Makefile
@@ -1022,7 +1022,9 @@ clean:
 	rm -rf vloghtb/Makefile vloghtb/refdat vloghtb/rtl vloghtb/scripts vloghtb/spec vloghtb/check_yosys vloghtb/vloghammer_tb.tar.bz2 vloghtb/temp vloghtb/log_test_*
 	rm -f tests/svinterfaces/*.log_stdout tests/svinterfaces/*.log_stderr tests/svinterfaces/dut_result.txt tests/svinterfaces/reference_result.txt tests/svinterfaces/a.out tests/svinterfaces/*_syn.v tests/svinterfaces/*.diff
 	rm -f  tests/tools/cmp_tbdata
-	$(MAKE) -C docs clean
+	-$(MAKE) -C docs clean
+	-$(MAKE) -C docs/images clean
+	rm -rf docs/source/cmd docs/util/__pycache__
 
 clean-abc:
 	$(MAKE) -C abc DEP= clean

From 8e2dae21ad21e5cc87d7ecc8fc07871ce694aa92 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 6 Feb 2024 10:30:37 +1300
Subject: [PATCH 058/499] ci: Checkout Yosys

---
 .github/workflows/test-linux.yml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/.github/workflows/test-linux.yml b/.github/workflows/test-linux.yml
index c4098edbeff..752d69a0694 100644
--- a/.github/workflows/test-linux.yml
+++ b/.github/workflows/test-linux.yml
@@ -173,6 +173,9 @@ jobs:
         run: |
           echo "procs=$(nproc)" >> $GITHUB_ENV
 
+      - name: Checkout Yosys
+        uses: actions/checkout@v4
+
       - name: Download build artifact
         uses: actions/download-artifact@v4
         with:

From 2bec6e3e0af83b0bdc5e4fa31f1bc7980a57e0db Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 6 Feb 2024 10:56:20 +1300
Subject: [PATCH 059/499] ci: Move iverilog from build to test

---
 .github/workflows/test-linux.yml | 58 ++++++++++++++++++--------------
 1 file changed, 33 insertions(+), 25 deletions(-)

diff --git a/.github/workflows/test-linux.yml b/.github/workflows/test-linux.yml
index 752d69a0694..e488c2f6c34 100644
--- a/.github/workflows/test-linux.yml
+++ b/.github/workflows/test-linux.yml
@@ -104,30 +104,6 @@ jobs:
         uses: actions/checkout@v4
         with:
          submodules: true
-      - name: Get iverilog
-        shell: bash
-        run: |
-          git clone https://github.com/steveicarus/iverilog.git
-          cd iverilog
-          echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV
-
-      - name: Cache iverilog
-        id: cache-iverilog
-        uses: actions/cache@v4
-        with:
-          path: .local/
-          key: ${{ matrix.os.id }}-${{ env.IVERILOG_GIT }}
-
-      - name: Build iverilog
-        if: steps.cache-iverilog.outputs.cache-hit != 'true'
-        shell: bash
-        run: |
-          mkdir -p $GITHUB_WORKSPACE/.local/
-          cd iverilog
-          autoconf
-          CC=gcc CXX=g++ ./configure --prefix=$GITHUB_WORKSPACE/.local
-          make -j${{ env.procs }}
-          make install
 
       - name: Build yosys out-of-tree
         shell: bash
@@ -158,7 +134,11 @@ jobs:
   test-linux:
     name: Run tests
     needs: build-linux
-    runs-on: ubuntu-latest
+    runs-on: ${{ matrix.os.id }}
+    strategy:
+      matrix:
+        os:
+          - { id: ubuntu-20.04, name: focal }
     steps:
       - name: Install Dependencies
         shell: bash
@@ -171,11 +151,39 @@ jobs:
         env:
           WORKSPACE: ${{ github.workspace }}
         run: |
+          echo "GITHUB_WORKSPACE=`pwd`" >> $GITHUB_ENV
+          echo "$GITHUB_WORKSPACE/.local/bin" >> $GITHUB_PATH
           echo "procs=$(nproc)" >> $GITHUB_ENV
 
       - name: Checkout Yosys
         uses: actions/checkout@v4
 
+      - name: Get iverilog
+        shell: bash
+        run: |
+          git clone https://github.com/steveicarus/iverilog.git
+          cd iverilog
+          git checkout 192b6aec96fde982e6ddcb28b346d5893aa8e874
+          echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV
+
+      - name: Cache iverilog
+        id: cache-iverilog
+        uses: actions/cache@v4
+        with:
+          path: .local/
+          key: ${{ matrix.os.id }}-${{ env.IVERILOG_GIT }}
+
+      - name: Build iverilog
+        if: steps.cache-iverilog.outputs.cache-hit != 'true'
+        shell: bash
+        run: |
+          mkdir -p $GITHUB_WORKSPACE/.local/
+          cd iverilog
+          autoconf
+          CC=gcc CXX=g++ ./configure --prefix=$GITHUB_WORKSPACE/.local
+          make -j${{ env.procs }}
+          make install
+
       - name: Download build artifact
         uses: actions/download-artifact@v4
         with:

From 1ef21efe3ff2cd6ead409803556c813c3f97d580 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 6 Feb 2024 11:48:38 +1300
Subject: [PATCH 060/499] ci: working on test setup

---
 .github/workflows/test-linux.yml | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/.github/workflows/test-linux.yml b/.github/workflows/test-linux.yml
index e488c2f6c34..fd875d4ae87 100644
--- a/.github/workflows/test-linux.yml
+++ b/.github/workflows/test-linux.yml
@@ -121,7 +121,7 @@ jobs:
         shell: bash
         run: |
           cd build
-          tar -cvf ../build.tar Makefile.conf share/ yosys yosys-*
+          tar -cvf ../build.tar share/ yosys yosys-*
 
       - name: Store build artifact
         if: (matrix.cpp_std == 'c++11') && (matrix.compiler == 'gcc-11')
@@ -134,11 +134,12 @@ jobs:
   test-linux:
     name: Run tests
     needs: build-linux
-    runs-on: ${{ matrix.os.id }}
+    runs-on: ${{ matrix.os }}
+    env:
+      CC: clang
     strategy:
       matrix:
-        os:
-          - { id: ubuntu-20.04, name: focal }
+        os: [ubuntu-20.04]
     steps:
       - name: Install Dependencies
         shell: bash
@@ -171,7 +172,7 @@ jobs:
         uses: actions/cache@v4
         with:
           path: .local/
-          key: ${{ matrix.os.id }}-${{ env.IVERILOG_GIT }}
+          key: ${{ matrix.os }}-${{ env.IVERILOG_GIT }}
 
       - name: Build iverilog
         if: steps.cache-iverilog.outputs.cache-hit != 'true'
@@ -197,4 +198,4 @@ jobs:
       - name: Run tests
         shell: bash
         run: |
-          make -j${{ env.procs }} test TARGETS= EXTRA_TARGETS=
+          make -j$procs test TARGETS= EXTRA_TARGETS= CONFIG=$CC

From 93bee0fc3b89f692a866d4bdf22dc98f6e9f1aba Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 6 Feb 2024 12:18:52 +1300
Subject: [PATCH 061/499] ci: more context var use

Also reduce `${{}}` expansion in `run` blocks.
---
 .github/workflows/test-linux.yml | 27 +++++++++------------------
 1 file changed, 9 insertions(+), 18 deletions(-)

diff --git a/.github/workflows/test-linux.yml b/.github/workflows/test-linux.yml
index fd875d4ae87..17aa050558d 100644
--- a/.github/workflows/test-linux.yml
+++ b/.github/workflows/test-linux.yml
@@ -27,6 +27,9 @@ jobs:
     needs: pre_job
     if: needs.pre_job.outputs.should_skip != 'true'
     runs-on: ${{ matrix.os.id }}
+    env:
+      CC: ${{ matrix.compiler }}
+      CXXSTD: ${{ matrix.cpp_std }}
     strategy:
       matrix:
         os:
@@ -63,11 +66,8 @@ jobs:
           sudo apt-add-repository ppa:ubuntu-toolchain-r/test
           sudo apt-get update
           sudo apt-get install $CC $CXX
-          echo "CC=$CC" >> $GITHUB_ENV
           echo "CXX=$CXX" >> $GITHUB_ENV
           echo "CXXFLAGS=-Wp,-D_GLIBCXX_ASSERTIONS" >> $GITHUB_ENV
-        env:
-          CC: ${{ matrix.compiler }}
 
       - name: Setup Clang
         if: startsWith(matrix.compiler, 'clang')
@@ -80,18 +80,12 @@ jobs:
           sudo apt-get update
           CXX=${CC/#clang/clang++}
           sudo apt-get install $CC $CXX
-          echo "CC=$CC" >> $GITHUB_ENV
           echo "CXX=$CXX" >> $GITHUB_ENV
-        env:
-          CC: ${{ matrix.compiler }}
 
       - name: Runtime environment
         shell: bash
-        env:
-          WORKSPACE: ${{ github.workspace }}
         run: |
-          echo "GITHUB_WORKSPACE=`pwd`" >> $GITHUB_ENV
-          echo "$GITHUB_WORKSPACE/.local/bin" >> $GITHUB_PATH
+          echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
           echo "procs=$(nproc)" >> $GITHUB_ENV
 
       - name: Tool versions
@@ -111,7 +105,7 @@ jobs:
           mkdir build
           cd build
           make -f ../Makefile config-${CC%%-*}
-          make -f ../Makefile -j${{ env.procs }} CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
+          make -f ../Makefile -j$procs CXXSTD=$CXXSTD CC=$CC CXX=$CC LD=$CC
 
       - name: Log yosys-config output
         run: |
@@ -149,11 +143,8 @@ jobs:
 
       - name: Runtime environment
         shell: bash
-        env:
-          WORKSPACE: ${{ github.workspace }}
         run: |
-          echo "GITHUB_WORKSPACE=`pwd`" >> $GITHUB_ENV
-          echo "$GITHUB_WORKSPACE/.local/bin" >> $GITHUB_PATH
+          echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
           echo "procs=$(nproc)" >> $GITHUB_ENV
 
       - name: Checkout Yosys
@@ -178,11 +169,11 @@ jobs:
         if: steps.cache-iverilog.outputs.cache-hit != 'true'
         shell: bash
         run: |
-          mkdir -p $GITHUB_WORKSPACE/.local/
+          mkdir -p ${{ github.workspace }}/.local/
           cd iverilog
           autoconf
-          CC=gcc CXX=g++ ./configure --prefix=$GITHUB_WORKSPACE/.local
-          make -j${{ env.procs }}
+          CC=gcc CXX=g++ ./configure --prefix=${{ github.workspace }}/.local
+          make -j$procs
           make install
 
       - name: Download build artifact

From 5ceafea0eca31301f962f572c757f97674e968fb Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 6 Feb 2024 17:25:25 +1300
Subject: [PATCH 062/499] ci: Default clang build

Switch build artifact to a default clang build.

Testing with the build artifact locally, `make test` is failing with `/lib/x86_64-linux-gnu/libstdc++.so.6: version 'GLIBCXX_3.4.29' not found`.  Using the gcc-11 build (might be?) installing GLIBCXX_3.4.29 but not linking it into the build.  Rather than trying to get it to link, just use the pre-installed `clang` instead.
---
 .github/workflows/test-linux.yml | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/.github/workflows/test-linux.yml b/.github/workflows/test-linux.yml
index 17aa050558d..489995615a3 100644
--- a/.github/workflows/test-linux.yml
+++ b/.github/workflows/test-linux.yml
@@ -29,12 +29,14 @@ jobs:
     runs-on: ${{ matrix.os.id }}
     env:
       CC: ${{ matrix.compiler }}
+      CXX: ${{ matrix.compiler }}
       CXXSTD: ${{ matrix.cpp_std }}
     strategy:
       matrix:
         os:
           - { id: ubuntu-20.04, name: focal }
         compiler:
+          - 'clang'
           - 'clang-12'
           - 'gcc-11'
         cpp_std:
@@ -70,7 +72,7 @@ jobs:
           echo "CXXFLAGS=-Wp,-D_GLIBCXX_ASSERTIONS" >> $GITHUB_ENV
 
       - name: Setup Clang
-        if: startsWith(matrix.compiler, 'clang')
+        if: startsWith(matrix.compiler, 'clang') && (matrix.compiler != 'clang')
         shell: bash
         run: |
           wget https://apt.llvm.org/llvm-snapshot.gpg.key
@@ -105,7 +107,7 @@ jobs:
           mkdir build
           cd build
           make -f ../Makefile config-${CC%%-*}
-          make -f ../Makefile -j$procs CXXSTD=$CXXSTD CC=$CC CXX=$CC LD=$CC
+          make -f ../Makefile -j$procs CXXSTD=$CXXSTD CC=$CC CXX=$CXX LD=$CC
 
       - name: Log yosys-config output
         run: |
@@ -118,7 +120,7 @@ jobs:
           tar -cvf ../build.tar share/ yosys yosys-*
 
       - name: Store build artifact
-        if: (matrix.cpp_std == 'c++11') && (matrix.compiler == 'gcc-11')
+        if: (matrix.cpp_std == 'c++11') && (matrix.compiler == 'clang')
         uses: actions/upload-artifact@v4
         with:
           name: build-artifact

From e3f77ff11fc7b9cee3b9fad081c9312b89cdf4a5 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 6 Feb 2024 17:56:15 +1300
Subject: [PATCH 063/499] ci: Add error reporting

---
 .github/workflows/test-linux.yml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/.github/workflows/test-linux.yml b/.github/workflows/test-linux.yml
index 489995615a3..c6088fd09f8 100644
--- a/.github/workflows/test-linux.yml
+++ b/.github/workflows/test-linux.yml
@@ -192,3 +192,9 @@ jobs:
         shell: bash
         run: |
           make -j$procs test TARGETS= EXTRA_TARGETS= CONFIG=$CC
+
+      - name: Report errors
+        if: ${{ failure() }}
+        shell: bash
+        run: |
+          find tests/**/*.err -print -exec cat {} \;

From aa470ccb4745452e45cb290ff5590f2f09424c5f Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 6 Feb 2024 18:31:53 +1300
Subject: [PATCH 064/499] ci: Unify test-*.yml

Also rename `build-artifact` to use `matrix.os` for compatibility with testing across OS.
---
 .../{test-linux.yml => test-build.yml}        | 53 +++++++---
 .github/workflows/test-macos.yml              | 97 -------------------
 2 files changed, 38 insertions(+), 112 deletions(-)
 rename .github/workflows/{test-linux.yml => test-build.yml} (80%)
 delete mode 100644 .github/workflows/test-macos.yml

diff --git a/.github/workflows/test-linux.yml b/.github/workflows/test-build.yml
similarity index 80%
rename from .github/workflows/test-linux.yml
rename to .github/workflows/test-build.yml
index c6088fd09f8..ec132e7c192 100644
--- a/.github/workflows/test-linux.yml
+++ b/.github/workflows/test-build.yml
@@ -1,4 +1,4 @@
-name: Build and run tests (Linux)
+name: Build and run tests
 
 on:
   pull_request:
@@ -23,10 +23,10 @@ jobs:
           # only run on push *or* pull_request, not both
           concurrent_skipping: 'same_content_newer'
 
-  build-linux:
+  build-yosys:
     needs: pre_job
     if: needs.pre_job.outputs.should_skip != 'true'
-    runs-on: ${{ matrix.os.id }}
+    runs-on: ${{ matrix.os }}
     env:
       CC: ${{ matrix.compiler }}
       CXX: ${{ matrix.compiler }}
@@ -34,9 +34,9 @@ jobs:
     strategy:
       matrix:
         os:
-          - { id: ubuntu-20.04, name: focal }
+          - ubuntu-20.04
+          - macos-13
         compiler:
-          - 'clang'
           - 'clang-12'
           - 'gcc-11'
         cpp_std:
@@ -45,21 +45,34 @@ jobs:
           - 'c++17'
           - 'c++20'
         include:
-          # Limit the older compilers to C++11 mode
-          - os: { id: ubuntu-20.04, name: focal }
+          # Build for testing
+          - os: ubuntu-20.04
+            compiler: 'clang'
+            cpp_std: 'c++11'
+          # Limited testing for older compilers
+          - os: ubuntu-20.04
             compiler: 'clang-11'
             cpp_std: 'c++11'
-          - os: { id: ubuntu-20.04, name: focal }
+          - os: ubuntu-20.04
             compiler: 'gcc-10'
             cpp_std: 'c++11'
+          # Add os_name
+          - os: ubuntu-20.04
+            os_name: focal
       fail-fast: false
     steps:
-      - name: Install Dependencies
+      - name: Install Linux Dependencies
+        if: runner.os == 'Linux'
         shell: bash
         run: |
           sudo apt-get update
           sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
 
+      - name: Install macOS Dependencies
+        if: runner.os == 'macOS'
+        run: |
+          brew install bison flex gawk libffi pkg-config bash
+
       - name: Setup GCC
         if: startsWith(matrix.compiler, 'gcc')
         shell: bash
@@ -78,18 +91,28 @@ jobs:
           wget https://apt.llvm.org/llvm-snapshot.gpg.key
           sudo apt-key add llvm-snapshot.gpg.key
           rm llvm-snapshot.gpg.key
-          sudo apt-add-repository "deb https://apt.llvm.org/${{ matrix.os.name }}/ llvm-toolchain-${{ matrix.os.name }} main"
+          sudo apt-add-repository "deb https://apt.llvm.org/${{ matrix.os_name }}/ llvm-toolchain-${{ matrix.os_name }} main"
           sudo apt-get update
           CXX=${CC/#clang/clang++}
           sudo apt-get install $CC $CXX
           echo "CXX=$CXX" >> $GITHUB_ENV
 
-      - name: Runtime environment
+      - name: Linux runtime environment
+        if: runner.os == 'Linux'
         shell: bash
         run: |
           echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
           echo "procs=$(nproc)" >> $GITHUB_ENV
 
+      - name: macOS runtime environment
+        if: runner.os == 'macOS'
+        shell: bash
+        run: |
+          echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
+          echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH
+          echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
+          echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV
+
       - name: Tool versions
         shell: bash
         run: |
@@ -123,13 +146,13 @@ jobs:
         if: (matrix.cpp_std == 'c++11') && (matrix.compiler == 'clang')
         uses: actions/upload-artifact@v4
         with:
-          name: build-artifact
+          name: build-${{ matrix.os }}
           path: build.tar
           retention-days: 1
 
-  test-linux:
+  test-yosys:
     name: Run tests
-    needs: build-linux
+    needs: build-yosys
     runs-on: ${{ matrix.os }}
     env:
       CC: clang
@@ -181,7 +204,7 @@ jobs:
       - name: Download build artifact
         uses: actions/download-artifact@v4
         with:
-          name: build-artifact
+          name: build-${{ matrix.os }}
 
       - name: Uncompress build
         shell: bash
diff --git a/.github/workflows/test-macos.yml b/.github/workflows/test-macos.yml
deleted file mode 100644
index ed63c8f35b7..00000000000
--- a/.github/workflows/test-macos.yml
+++ /dev/null
@@ -1,97 +0,0 @@
-name: Build and run tests (macOS)
-
-on:
-  pull_request:
-    branches:
-    - master
-  push:
-    branches:
-    - master
-
-jobs:
-  pre_job:
-    runs-on: ubuntu-latest
-    outputs:
-      should_skip: ${{ steps.skip_check.outputs.should_skip }}
-    steps:
-      - id: skip_check
-        uses: fkirc/skip-duplicate-actions@v5
-        with:
-          paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]'
-          # cancel previous builds if a new commit is pushed
-          cancel_others: 'true'
-          # only run on push *or* pull_request, not both
-          concurrent_skipping: 'same_content_newer'
-
-  test-macos:
-    needs: pre_job
-    if: needs.pre_job.outputs.should_skip != 'true'
-    runs-on: ${{ matrix.os.id }}
-    strategy:
-      matrix:
-        os:
-          - { id: macos-13, name: 'Ventura' }
-        cpp_std:
-          - 'c++11'
-      fail-fast: false
-    steps:
-      - name: Install Dependencies
-        run: |
-          HOMEBREW_NO_INSTALLED_DEPENDENTS_CHECK=1 brew install bison flex gawk libffi pkg-config bash
-
-      - name: Runtime environment
-        shell: bash
-        env:
-          WORKSPACE: ${{ github.workspace }}
-        run: |
-          echo "GITHUB_WORKSPACE=`pwd`" >> $GITHUB_ENV
-          echo "$GITHUB_WORKSPACE/.local/bin" >> $GITHUB_PATH
-          echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH
-          echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
-          echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV
-
-      - name: Tool versions
-        shell: bash
-        run: |
-          cc --version
-
-      - name: Checkout Yosys
-        uses: actions/checkout@v4
-        with:
-         submodules: true
-      - name: Get iverilog
-        shell: bash
-        run: |
-          git clone https://github.com/steveicarus/iverilog.git
-          cd iverilog
-          echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV
-
-      - name: Cache iverilog
-        id: cache-iverilog
-        uses: actions/cache@v4
-        with:
-          path: .local/
-          key: ${{ matrix.os.id }}-${{ env.IVERILOG_GIT }}
-
-      - name: Build iverilog
-        if: steps.cache-iverilog.outputs.cache-hit != 'true'
-        shell: bash
-        run: |
-          mkdir -p $GITHUB_WORKSPACE/.local/
-          cd iverilog
-          autoconf
-          CC=gcc CXX=g++ ./configure --prefix=$GITHUB_WORKSPACE/.local/
-          make -j${{ env.procs }}
-          make install
-
-      - name: Build yosys
-        shell: bash
-        run: |
-          make config-clang
-          make -j${{ env.procs }} CXXSTD=${{ matrix.cpp_std }} CC=cc CXX=cc LD=cc
-
-      - name: Run tests
-        if: matrix.cpp_std == 'c++11'
-        shell: bash
-        run: |
-          make -j${{ env.procs }} test CXXSTD=${{ matrix.cpp_std }} CC=cc CXX=cc LD=cc

From f408b4de05775c5735742114641d302f87bcb989 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 6 Feb 2024 18:56:11 +1300
Subject: [PATCH 065/499] ci: fix compiler setup

`os_name` in include section needs to be explicit (putting it at the end doesn't
apply to the extra jobs).

Move macOS test to extra job instead of doing all gcc/clang (which isn't setup
for mac anyway).

Also adds name to build-yosys task.
---
 .github/workflows/test-build.yml | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index ec132e7c192..20417479522 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -24,9 +24,10 @@ jobs:
           concurrent_skipping: 'same_content_newer'
 
   build-yosys:
+    name: Build Yosys
+    runs-on: ${{ matrix.os }}
     needs: pre_job
     if: needs.pre_job.outputs.should_skip != 'true'
-    runs-on: ${{ matrix.os }}
     env:
       CC: ${{ matrix.compiler }}
       CXX: ${{ matrix.compiler }}
@@ -35,7 +36,6 @@ jobs:
       matrix:
         os:
           - ubuntu-20.04
-          - macos-13
         compiler:
           - 'clang-12'
           - 'gcc-11'
@@ -45,20 +45,27 @@ jobs:
           - 'c++17'
           - 'c++20'
         include:
+          # Add os_name
+          - os: ubuntu-20.04
+            os_name: focal
           # Build for testing
           - os: ubuntu-20.04
+            os_name: focal
+            compiler: 'clang'
+            cpp_std: 'c++11'
+          # macOS build
+          - os: macos-13
             compiler: 'clang'
             cpp_std: 'c++11'
           # Limited testing for older compilers
           - os: ubuntu-20.04
+            os_name: focal
             compiler: 'clang-11'
             cpp_std: 'c++11'
           - os: ubuntu-20.04
+            os_name: focal
             compiler: 'gcc-10'
             cpp_std: 'c++11'
-          # Add os_name
-          - os: ubuntu-20.04
-            os_name: focal
       fail-fast: false
     steps:
       - name: Install Linux Dependencies

From 8bc206928f9c1b269de4b0416fb8a0ee14235f37 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 9 Feb 2024 05:43:10 +1300
Subject: [PATCH 066/499] ci: split test build from matrix

Allow test suite to run if, for example, the C++20 builds are failing but C++11 are fine.
---
 .github/workflows/test-build.yml | 75 ++++++++++++++++++++++++++++----
 1 file changed, 67 insertions(+), 8 deletions(-)

diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index 20417479522..853a2b12b46 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -23,8 +23,8 @@ jobs:
           # only run on push *or* pull_request, not both
           concurrent_skipping: 'same_content_newer'
 
-  build-yosys:
-    name: Build Yosys
+  test-builds:
+    name: Compiler testing
     runs-on: ${{ matrix.os }}
     needs: pre_job
     if: needs.pre_job.outputs.should_skip != 'true'
@@ -48,11 +48,6 @@ jobs:
           # Add os_name
           - os: ubuntu-20.04
             os_name: focal
-          # Build for testing
-          - os: ubuntu-20.04
-            os_name: focal
-            compiler: 'clang'
-            cpp_std: 'c++11'
           # macOS build
           - os: macos-13
             compiler: 'clang'
@@ -131,7 +126,71 @@ jobs:
         with:
          submodules: true
 
-      - name: Build yosys out-of-tree
+      - name: Build
+        shell: bash
+        run: |
+          make config-${CC%%-*}
+          make -j$procs CXXSTD=$CXXSTD CC=$CC CXX=$CXX LD=$CC
+
+  build-yosys:
+    name: Reusable Yosys build
+    runs-on: ${{ matrix.os }}
+    env:
+      CC: ${{ matrix.compiler }}
+      CXX: ${{ matrix.compiler }}
+      CXXSTD: ${{ matrix.cpp_std }}
+    strategy:
+      matrix:
+        os:
+          - ubuntu-20.04
+        compiler:
+          - 'clang'
+        cpp_std:
+          - 'c++11'
+        include:
+          # Add os_name
+          - os: ubuntu-20.04
+            os_name: focal
+      fail-fast: false
+    steps:
+      - name: Install Linux Dependencies
+        if: runner.os == 'Linux'
+        shell: bash
+        run: |
+          sudo apt-get update
+          sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
+
+      - name: Install macOS Dependencies
+        if: runner.os == 'macOS'
+        run: |
+          brew install bison flex gawk libffi pkg-config bash
+
+      - name: Linux runtime environment
+        if: runner.os == 'Linux'
+        shell: bash
+        run: |
+          echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
+          echo "procs=$(nproc)" >> $GITHUB_ENV
+
+      - name: macOS runtime environment
+        if: runner.os == 'macOS'
+        shell: bash
+        run: |
+          echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
+          echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH
+          echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
+          echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV
+
+      - name: Tool versions
+        shell: bash
+        run: |
+          $CC --version
+          $CXX --version
+
+      - name: Checkout Yosys
+        uses: actions/checkout@v4
+
+      - name: Build
         shell: bash
         run: |
           mkdir build

From 934822115417c7323c72f9b4b0d992dcd691c354 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Sat, 10 Feb 2024 12:34:07 +1300
Subject: [PATCH 067/499] ci: simplify tests a bit

Remove compiler and cpp_std from `build-yosys` matrix.  Using `config-$CC` will instead fall back to default values.

Drop `Tool versions` step and introduce `yosys-config` output instead.

Rename `test-builds` to `test-compile`.
---
 .github/workflows/test-build.yml | 34 ++++++++++----------------------
 1 file changed, 10 insertions(+), 24 deletions(-)

diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index 853a2b12b46..b27a37a8719 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -23,7 +23,7 @@ jobs:
           # only run on push *or* pull_request, not both
           concurrent_skipping: 'same_content_newer'
 
-  test-builds:
+  test-compile:
     name: Compiler testing
     runs-on: ${{ matrix.os }}
     needs: pre_job
@@ -133,24 +133,13 @@ jobs:
           make -j$procs CXXSTD=$CXXSTD CC=$CC CXX=$CXX LD=$CC
 
   build-yosys:
-    name: Reusable Yosys build
+    name: Reusable build
     runs-on: ${{ matrix.os }}
     env:
-      CC: ${{ matrix.compiler }}
-      CXX: ${{ matrix.compiler }}
-      CXXSTD: ${{ matrix.cpp_std }}
+      CC: clang
     strategy:
       matrix:
-        os:
-          - ubuntu-20.04
-        compiler:
-          - 'clang'
-        cpp_std:
-          - 'c++11'
-        include:
-          # Add os_name
-          - os: ubuntu-20.04
-            os_name: focal
+        os: [ubuntu-20.04]
       fail-fast: false
     steps:
       - name: Install Linux Dependencies
@@ -181,12 +170,6 @@ jobs:
           echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
           echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV
 
-      - name: Tool versions
-        shell: bash
-        run: |
-          $CC --version
-          $CXX --version
-
       - name: Checkout Yosys
         uses: actions/checkout@v4
 
@@ -195,8 +178,12 @@ jobs:
         run: |
           mkdir build
           cd build
-          make -f ../Makefile config-${CC%%-*}
-          make -f ../Makefile -j$procs CXXSTD=$CXXSTD CC=$CC CXX=$CXX LD=$CC
+          make -f ../Makefile config-$CC
+          make -f ../Makefile -j$procs
+
+      - name: Log yosys-config output
+        run: |
+          ./yosys-config || true
 
       - name: Log yosys-config output
         run: |
@@ -209,7 +196,6 @@ jobs:
           tar -cvf ../build.tar share/ yosys yosys-*
 
       - name: Store build artifact
-        if: (matrix.cpp_std == 'c++11') && (matrix.compiler == 'clang')
         uses: actions/upload-artifact@v4
         with:
           name: build-${{ matrix.os }}

From c9c6b96ba92a50ae32515e1ffb76f1f18a7c78fe Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 15 Feb 2024 09:49:02 +1300
Subject: [PATCH 068/499] ci: add missing macOS build

`test-macos.yml` included c++17 which was missing in `test-build.yml`.
---
 .github/workflows/test-build.yml | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index b27a37a8719..7f581af277e 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -48,10 +48,13 @@ jobs:
           # Add os_name
           - os: ubuntu-20.04
             os_name: focal
-          # macOS build
+          # macOS builds
           - os: macos-13
             compiler: 'clang'
             cpp_std: 'c++11'
+          - os: macos-13
+            compiler: 'clang'
+            cpp_std: 'c++17'
           # Limited testing for older compilers
           - os: ubuntu-20.04
             os_name: focal

From 154464e7ce79f46f5647b0e06e7cb226c756fec5 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 15 Feb 2024 10:00:22 +1300
Subject: [PATCH 069/499] ci: add macos test build

---
 .github/workflows/test-build.yml | 26 +++++++++++++++++++++-----
 1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index 7f581af277e..f223bde24d1 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -142,7 +142,7 @@ jobs:
       CC: clang
     strategy:
       matrix:
-        os: [ubuntu-20.04]
+        os: [ubuntu-20.04, macos-13]
       fail-fast: false
     steps:
       - name: Install Linux Dependencies
@@ -213,20 +213,36 @@ jobs:
       CC: clang
     strategy:
       matrix:
-        os: [ubuntu-20.04]
+        os: [ubuntu-20.04, macos-13]
     steps:
-      - name: Install Dependencies
+      - name: Install Linux Dependencies
+        if: runner.os == 'Linux'
         shell: bash
         run: |
           sudo apt-get update
-          sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
+          sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
+
+      - name: Install macOS Dependencies
+        if: runner.os == 'macOS'
+        run: |
+          brew install bison flex gawk libffi pkg-config bash
 
-      - name: Runtime environment
+      - name: Linux runtime environment
+        if: runner.os == 'Linux'
         shell: bash
         run: |
           echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
           echo "procs=$(nproc)" >> $GITHUB_ENV
 
+      - name: macOS runtime environment
+        if: runner.os == 'macOS'
+        shell: bash
+        run: |
+          echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
+          echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH
+          echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
+          echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV
+
       - name: Checkout Yosys
         uses: actions/checkout@v4
 

From 326d802220acaf8102d967b49247d95153396d55 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 15 Feb 2024 10:00:58 +1300
Subject: [PATCH 070/499] ci: split test-compile from test-build

---
 .github/workflows/test-build.yml   | 114 +-----------------------
 .github/workflows/test-compile.yml | 137 +++++++++++++++++++++++++++++
 2 files changed, 139 insertions(+), 112 deletions(-)
 create mode 100644 .github/workflows/test-compile.yml

diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index f223bde24d1..8ad44f0b550 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -23,121 +23,11 @@ jobs:
           # only run on push *or* pull_request, not both
           concurrent_skipping: 'same_content_newer'
 
-  test-compile:
-    name: Compiler testing
-    runs-on: ${{ matrix.os }}
-    needs: pre_job
-    if: needs.pre_job.outputs.should_skip != 'true'
-    env:
-      CC: ${{ matrix.compiler }}
-      CXX: ${{ matrix.compiler }}
-      CXXSTD: ${{ matrix.cpp_std }}
-    strategy:
-      matrix:
-        os:
-          - ubuntu-20.04
-        compiler:
-          - 'clang-12'
-          - 'gcc-11'
-        cpp_std:
-          - 'c++11'
-          - 'c++14'
-          - 'c++17'
-          - 'c++20'
-        include:
-          # Add os_name
-          - os: ubuntu-20.04
-            os_name: focal
-          # macOS builds
-          - os: macos-13
-            compiler: 'clang'
-            cpp_std: 'c++11'
-          - os: macos-13
-            compiler: 'clang'
-            cpp_std: 'c++17'
-          # Limited testing for older compilers
-          - os: ubuntu-20.04
-            os_name: focal
-            compiler: 'clang-11'
-            cpp_std: 'c++11'
-          - os: ubuntu-20.04
-            os_name: focal
-            compiler: 'gcc-10'
-            cpp_std: 'c++11'
-      fail-fast: false
-    steps:
-      - name: Install Linux Dependencies
-        if: runner.os == 'Linux'
-        shell: bash
-        run: |
-          sudo apt-get update
-          sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
-
-      - name: Install macOS Dependencies
-        if: runner.os == 'macOS'
-        run: |
-          brew install bison flex gawk libffi pkg-config bash
-
-      - name: Setup GCC
-        if: startsWith(matrix.compiler, 'gcc')
-        shell: bash
-        run: |
-          CXX=${CC/#gcc/g++}
-          sudo apt-add-repository ppa:ubuntu-toolchain-r/test
-          sudo apt-get update
-          sudo apt-get install $CC $CXX
-          echo "CXX=$CXX" >> $GITHUB_ENV
-          echo "CXXFLAGS=-Wp,-D_GLIBCXX_ASSERTIONS" >> $GITHUB_ENV
-
-      - name: Setup Clang
-        if: startsWith(matrix.compiler, 'clang') && (matrix.compiler != 'clang')
-        shell: bash
-        run: |
-          wget https://apt.llvm.org/llvm-snapshot.gpg.key
-          sudo apt-key add llvm-snapshot.gpg.key
-          rm llvm-snapshot.gpg.key
-          sudo apt-add-repository "deb https://apt.llvm.org/${{ matrix.os_name }}/ llvm-toolchain-${{ matrix.os_name }} main"
-          sudo apt-get update
-          CXX=${CC/#clang/clang++}
-          sudo apt-get install $CC $CXX
-          echo "CXX=$CXX" >> $GITHUB_ENV
-
-      - name: Linux runtime environment
-        if: runner.os == 'Linux'
-        shell: bash
-        run: |
-          echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
-          echo "procs=$(nproc)" >> $GITHUB_ENV
-
-      - name: macOS runtime environment
-        if: runner.os == 'macOS'
-        shell: bash
-        run: |
-          echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
-          echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH
-          echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
-          echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV
-
-      - name: Tool versions
-        shell: bash
-        run: |
-          $CC --version
-          $CXX --version
-
-      - name: Checkout Yosys
-        uses: actions/checkout@v4
-        with:
-         submodules: true
-
-      - name: Build
-        shell: bash
-        run: |
-          make config-${CC%%-*}
-          make -j$procs CXXSTD=$CXXSTD CC=$CC CXX=$CXX LD=$CC
-
   build-yosys:
     name: Reusable build
     runs-on: ${{ matrix.os }}
+    needs: pre_job
+    if: needs.pre_job.outputs.should_skip != 'true'
     env:
       CC: clang
     strategy:
diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml
new file mode 100644
index 00000000000..5d1c0aca94b
--- /dev/null
+++ b/.github/workflows/test-compile.yml
@@ -0,0 +1,137 @@
+name: Compiler testing
+
+on:
+  pull_request:
+    branches:
+    - master
+  push:
+    branches:
+    - master
+
+jobs:
+  pre_job:
+    runs-on: ubuntu-latest
+    outputs:
+      should_skip: ${{ steps.skip_check.outputs.should_skip }}
+    steps:
+      - id: skip_check
+        uses: fkirc/skip-duplicate-actions@v5
+        with:
+          paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]'
+          # cancel previous builds if a new commit is pushed
+          cancel_others: 'true'
+          # only run on push *or* pull_request, not both
+          concurrent_skipping: 'same_content_newer'
+
+  test-compile:
+    runs-on: ${{ matrix.os }}
+    needs: pre_job
+    if: needs.pre_job.outputs.should_skip != 'true'
+    env:
+      CC: ${{ matrix.compiler }}
+      CXX: ${{ matrix.compiler }}
+      CXXSTD: ${{ matrix.cpp_std }}
+    strategy:
+      matrix:
+        os:
+          - ubuntu-20.04
+        compiler:
+          - 'clang-12'
+          - 'gcc-11'
+        cpp_std:
+          - 'c++11'
+          - 'c++14'
+          - 'c++17'
+          - 'c++20'
+        include:
+          # Add os_name
+          - os: ubuntu-20.04
+            os_name: focal
+          # macOS builds
+          - os: macos-13
+            compiler: 'clang'
+            cpp_std: 'c++11'
+          - os: macos-13
+            compiler: 'clang'
+            cpp_std: 'c++17'
+          # Limited testing for older compilers
+          - os: ubuntu-20.04
+            os_name: focal
+            compiler: 'clang-11'
+            cpp_std: 'c++11'
+          - os: ubuntu-20.04
+            os_name: focal
+            compiler: 'gcc-10'
+            cpp_std: 'c++11'
+      fail-fast: false
+    steps:
+      - name: Install Linux Dependencies
+        if: runner.os == 'Linux'
+        shell: bash
+        run: |
+          sudo apt-get update
+          sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
+
+      - name: Install macOS Dependencies
+        if: runner.os == 'macOS'
+        run: |
+          brew install bison flex gawk libffi pkg-config bash
+
+      - name: Setup GCC
+        if: startsWith(matrix.compiler, 'gcc')
+        shell: bash
+        run: |
+          CXX=${CC/#gcc/g++}
+          sudo apt-add-repository ppa:ubuntu-toolchain-r/test
+          sudo apt-get update
+          sudo apt-get install $CC $CXX
+          echo "CXX=$CXX" >> $GITHUB_ENV
+          echo "CXXFLAGS=-Wp,-D_GLIBCXX_ASSERTIONS" >> $GITHUB_ENV
+
+      - name: Setup Clang
+        if: startsWith(matrix.compiler, 'clang') && (matrix.compiler != 'clang')
+        shell: bash
+        run: |
+          wget https://apt.llvm.org/llvm-snapshot.gpg.key
+          sudo apt-key add llvm-snapshot.gpg.key
+          rm llvm-snapshot.gpg.key
+          sudo apt-add-repository "deb https://apt.llvm.org/${{ matrix.os_name }}/ llvm-toolchain-${{ matrix.os_name }} main"
+          sudo apt-get update
+          CXX=${CC/#clang/clang++}
+          sudo apt-get install $CC $CXX
+          echo "CXX=$CXX" >> $GITHUB_ENV
+
+      - name: Linux runtime environment
+        if: runner.os == 'Linux'
+        shell: bash
+        run: |
+          echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
+          echo "procs=$(nproc)" >> $GITHUB_ENV
+
+      - name: macOS runtime environment
+        if: runner.os == 'macOS'
+        shell: bash
+        run: |
+          echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
+          echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH
+          echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
+          echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV
+
+      - name: Tool versions
+        shell: bash
+        run: |
+          $CC --version
+          $CXX --version
+
+      - name: Checkout Yosys
+        uses: actions/checkout@v4
+
+      - name: Build
+        shell: bash
+        run: |
+          make config-${CC%%-*}
+          make -j$procs CXXSTD=$CXXSTD CC=$CC CXX=$CXX LD=$CC
+
+      - name: Log yosys-config output
+        run: |
+          ./yosys-config || true

From 616848b773297ed8c37d94c0a5cf68c84b416284 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Mon, 4 Mar 2024 11:37:25 +1300
Subject: [PATCH 071/499] ci: Use aminya/setup-cpp

---
 .github/workflows/test-compile.yml | 30 +++++-------------------------
 1 file changed, 5 insertions(+), 25 deletions(-)

diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml
index 5d1c0aca94b..b03af924346 100644
--- a/.github/workflows/test-compile.yml
+++ b/.github/workflows/test-compile.yml
@@ -28,9 +28,8 @@ jobs:
     needs: pre_job
     if: needs.pre_job.outputs.should_skip != 'true'
     env:
-      CC: ${{ matrix.compiler }}
-      CXX: ${{ matrix.compiler }}
       CXXSTD: ${{ matrix.cpp_std }}
+      CXXFLAGS: ${{ startsWith(matrix.compiler, 'gcc') && '-Wp,-D_GLIBCXX_ASSERTIONS' || ''}}
     strategy:
       matrix:
         os:
@@ -77,29 +76,10 @@ jobs:
         run: |
           brew install bison flex gawk libffi pkg-config bash
 
-      - name: Setup GCC
-        if: startsWith(matrix.compiler, 'gcc')
-        shell: bash
-        run: |
-          CXX=${CC/#gcc/g++}
-          sudo apt-add-repository ppa:ubuntu-toolchain-r/test
-          sudo apt-get update
-          sudo apt-get install $CC $CXX
-          echo "CXX=$CXX" >> $GITHUB_ENV
-          echo "CXXFLAGS=-Wp,-D_GLIBCXX_ASSERTIONS" >> $GITHUB_ENV
-
-      - name: Setup Clang
-        if: startsWith(matrix.compiler, 'clang') && (matrix.compiler != 'clang')
-        shell: bash
-        run: |
-          wget https://apt.llvm.org/llvm-snapshot.gpg.key
-          sudo apt-key add llvm-snapshot.gpg.key
-          rm llvm-snapshot.gpg.key
-          sudo apt-add-repository "deb https://apt.llvm.org/${{ matrix.os_name }}/ llvm-toolchain-${{ matrix.os_name }} main"
-          sudo apt-get update
-          CXX=${CC/#clang/clang++}
-          sudo apt-get install $CC $CXX
-          echo "CXX=$CXX" >> $GITHUB_ENV
+      - name: Setup Cpp
+        uses: aminya/setup-cpp@v1
+        with:
+          compiler: ${{ matrix.compiler }}
 
       - name: Linux runtime environment
         if: runner.os == 'Linux'

From 62440246ec2d9fdc16d9a9ae535087c3498fc273 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Mon, 4 Mar 2024 12:00:51 +1300
Subject: [PATCH 072/499] ci: Add CC_SHORT env var

New Setup Cpp step uses fully qualified paths for $CC and $CXX so ${CC%%-*} no longer works.
Remove os_name since it's not needed anymore.
---
 .github/workflows/test-compile.yml | 10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml
index b03af924346..9c25874bbcd 100644
--- a/.github/workflows/test-compile.yml
+++ b/.github/workflows/test-compile.yml
@@ -30,6 +30,7 @@ jobs:
     env:
       CXXSTD: ${{ matrix.cpp_std }}
       CXXFLAGS: ${{ startsWith(matrix.compiler, 'gcc') && '-Wp,-D_GLIBCXX_ASSERTIONS' || ''}}
+      CC_SHORT: ${{ startsWith(matrix.compiler, 'gcc') && 'gcc' || 'clang' }}
     strategy:
       matrix:
         os:
@@ -43,9 +44,6 @@ jobs:
           - 'c++17'
           - 'c++20'
         include:
-          # Add os_name
-          - os: ubuntu-20.04
-            os_name: focal
           # macOS builds
           - os: macos-13
             compiler: 'clang'
@@ -55,11 +53,9 @@ jobs:
             cpp_std: 'c++17'
           # Limited testing for older compilers
           - os: ubuntu-20.04
-            os_name: focal
             compiler: 'clang-11'
             cpp_std: 'c++11'
           - os: ubuntu-20.04
-            os_name: focal
             compiler: 'gcc-10'
             cpp_std: 'c++11'
       fail-fast: false
@@ -109,8 +105,8 @@ jobs:
       - name: Build
         shell: bash
         run: |
-          make config-${CC%%-*}
-          make -j$procs CXXSTD=$CXXSTD CC=$CC CXX=$CXX LD=$CC
+          make config-$CC_SHORT
+          make -j$procs CXXSTD=$CXXSTD
 
       - name: Log yosys-config output
         run: |

From d07323e7ddca262727c39750a8c5ec29fcbd59d1 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Mon, 4 Mar 2024 13:10:50 +1300
Subject: [PATCH 073/499] ci: Add action for reusable build env setup

---
 .github/actions/setup-build-env/action.yml | 32 ++++++++++++
 .github/workflows/test-build.yml           | 58 ++--------------------
 .github/workflows/test-compile.yml         | 29 +----------
 3 files changed, 38 insertions(+), 81 deletions(-)
 create mode 100644 .github/actions/setup-build-env/action.yml

diff --git a/.github/actions/setup-build-env/action.yml b/.github/actions/setup-build-env/action.yml
new file mode 100644
index 00000000000..e1b550e5ca8
--- /dev/null
+++ b/.github/actions/setup-build-env/action.yml
@@ -0,0 +1,32 @@
+name: Build environment setup
+description: Configure build env for Yosys builds
+runs:
+  using: composite
+  steps:
+    - name: Install Linux Dependencies
+      if: runner.os == 'Linux'
+      shell: bash
+      run: |
+        sudo apt-get update
+        sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
+
+    - name: Install macOS Dependencies
+      if: runner.os == 'macOS'
+      run: |
+        brew install bison flex gawk libffi pkg-config bash
+
+    - name: Linux runtime environment
+      if: runner.os == 'Linux'
+      shell: bash
+      run: |
+        echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
+        echo "procs=$(nproc)" >> $GITHUB_ENV
+
+    - name: macOS runtime environment
+      if: runner.os == 'macOS'
+      shell: bash
+      run: |
+        echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
+        echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH
+        echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
+        echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV
\ No newline at end of file
diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index 8ad44f0b550..37322883106 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -35,33 +35,8 @@ jobs:
         os: [ubuntu-20.04, macos-13]
       fail-fast: false
     steps:
-      - name: Install Linux Dependencies
-        if: runner.os == 'Linux'
-        shell: bash
-        run: |
-          sudo apt-get update
-          sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
-
-      - name: Install macOS Dependencies
-        if: runner.os == 'macOS'
-        run: |
-          brew install bison flex gawk libffi pkg-config bash
-
-      - name: Linux runtime environment
-        if: runner.os == 'Linux'
-        shell: bash
-        run: |
-          echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
-          echo "procs=$(nproc)" >> $GITHUB_ENV
-
-      - name: macOS runtime environment
-        if: runner.os == 'macOS'
-        shell: bash
-        run: |
-          echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
-          echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH
-          echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
-          echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV
+      - name: Setup environment
+        uses: ./.github/actions/setup-build-env
 
       - name: Checkout Yosys
         uses: actions/checkout@v4
@@ -105,33 +80,8 @@ jobs:
       matrix:
         os: [ubuntu-20.04, macos-13]
     steps:
-      - name: Install Linux Dependencies
-        if: runner.os == 'Linux'
-        shell: bash
-        run: |
-          sudo apt-get update
-          sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
-
-      - name: Install macOS Dependencies
-        if: runner.os == 'macOS'
-        run: |
-          brew install bison flex gawk libffi pkg-config bash
-
-      - name: Linux runtime environment
-        if: runner.os == 'Linux'
-        shell: bash
-        run: |
-          echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
-          echo "procs=$(nproc)" >> $GITHUB_ENV
-
-      - name: macOS runtime environment
-        if: runner.os == 'macOS'
-        shell: bash
-        run: |
-          echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
-          echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH
-          echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
-          echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV
+      - name: Setup environment
+        uses: ./.github/actions/setup-build-env
 
       - name: Checkout Yosys
         uses: actions/checkout@v4
diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml
index 9c25874bbcd..6a0b69c8bb3 100644
--- a/.github/workflows/test-compile.yml
+++ b/.github/workflows/test-compile.yml
@@ -60,39 +60,14 @@ jobs:
             cpp_std: 'c++11'
       fail-fast: false
     steps:
-      - name: Install Linux Dependencies
-        if: runner.os == 'Linux'
-        shell: bash
-        run: |
-          sudo apt-get update
-          sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
-
-      - name: Install macOS Dependencies
-        if: runner.os == 'macOS'
-        run: |
-          brew install bison flex gawk libffi pkg-config bash
+      - name: Setup environment
+        uses: ./.github/actions/setup-build-env
 
       - name: Setup Cpp
         uses: aminya/setup-cpp@v1
         with:
           compiler: ${{ matrix.compiler }}
 
-      - name: Linux runtime environment
-        if: runner.os == 'Linux'
-        shell: bash
-        run: |
-          echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
-          echo "procs=$(nproc)" >> $GITHUB_ENV
-
-      - name: macOS runtime environment
-        if: runner.os == 'macOS'
-        shell: bash
-        run: |
-          echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
-          echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH
-          echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
-          echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV
-
       - name: Tool versions
         shell: bash
         run: |

From 3c65ddbea07a12e6f0d4cbcee4b18e9c6297913c Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Mon, 4 Mar 2024 13:12:45 +1300
Subject: [PATCH 074/499] ci: Checkout goes first

---
 .github/workflows/test-build.yml   | 12 ++++++------
 .github/workflows/test-compile.yml |  6 +++---
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index 37322883106..cdc19b0e35a 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -35,12 +35,12 @@ jobs:
         os: [ubuntu-20.04, macos-13]
       fail-fast: false
     steps:
-      - name: Setup environment
-        uses: ./.github/actions/setup-build-env
-
       - name: Checkout Yosys
         uses: actions/checkout@v4
 
+      - name: Setup environment
+        uses: ./.github/actions/setup-build-env
+
       - name: Build
         shell: bash
         run: |
@@ -80,12 +80,12 @@ jobs:
       matrix:
         os: [ubuntu-20.04, macos-13]
     steps:
-      - name: Setup environment
-        uses: ./.github/actions/setup-build-env
-
       - name: Checkout Yosys
         uses: actions/checkout@v4
 
+      - name: Setup environment
+        uses: ./.github/actions/setup-build-env
+
       - name: Get iverilog
         shell: bash
         run: |
diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml
index 6a0b69c8bb3..c541b68ff30 100644
--- a/.github/workflows/test-compile.yml
+++ b/.github/workflows/test-compile.yml
@@ -60,6 +60,9 @@ jobs:
             cpp_std: 'c++11'
       fail-fast: false
     steps:
+      - name: Checkout Yosys
+        uses: actions/checkout@v4
+
       - name: Setup environment
         uses: ./.github/actions/setup-build-env
 
@@ -74,9 +77,6 @@ jobs:
           $CC --version
           $CXX --version
 
-      - name: Checkout Yosys
-        uses: actions/checkout@v4
-
       - name: Build
         shell: bash
         run: |

From 6451a6a0dc480a67bf681610577a76b4e6d58559 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Mon, 4 Mar 2024 13:13:43 +1300
Subject: [PATCH 075/499] ci: Fix action.yml

---
 .github/actions/setup-build-env/action.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.github/actions/setup-build-env/action.yml b/.github/actions/setup-build-env/action.yml
index e1b550e5ca8..f61d6565e51 100644
--- a/.github/actions/setup-build-env/action.yml
+++ b/.github/actions/setup-build-env/action.yml
@@ -12,6 +12,7 @@ runs:
 
     - name: Install macOS Dependencies
       if: runner.os == 'macOS'
+      shell: bash
       run: |
         brew install bison flex gawk libffi pkg-config bash
 

From 112a5cfc6752c04f5fcec35c750df30b812c56d8 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 21 Mar 2024 10:01:01 +1300
Subject: [PATCH 076/499] ci: Add testing for newer compilers

---
 .github/workflows/test-compile.yml | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml
index c541b68ff30..5b0c716f0be 100644
--- a/.github/workflows/test-compile.yml
+++ b/.github/workflows/test-compile.yml
@@ -58,6 +58,28 @@ jobs:
           - os: ubuntu-20.04
             compiler: 'gcc-10'
             cpp_std: 'c++11'
+          # Limited testing for newer compilers
+          - os: ubuntu-20.04
+            compiler: 'clang-13'
+            cpp_std: 'c++11'
+          - os: ubuntu-20.04
+            compiler: 'clang-14'
+            cpp_std: 'c++11'
+          - os: ubuntu-20.04
+            compiler: 'clang-15'
+            cpp_std: 'c++11'
+          - os: ubuntu-20.04
+            compiler: 'clang-16'
+            cpp_std: 'c++11'
+          - os: ubuntu-20.04
+            compiler: 'clang-17'
+            cpp_std: 'c++11'
+          - os: ubuntu-20.04
+            compiler: 'gcc-12'
+            cpp_std: 'c++11'
+          - os: ubuntu-20.04
+            compiler: 'gcc-13'
+            cpp_std: 'c++11'
       fail-fast: false
     steps:
       - name: Checkout Yosys

From 6f602e79d4abe113eff11d61d9072e18a4bf6733 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 21 Mar 2024 11:02:18 +1300
Subject: [PATCH 077/499] docs: Debugging macro test fail

Call yosys-config post build extraction for sanity check.
Report absolute path for yosys exe if it can't be found.
---
 .github/workflows/test-build.yml | 43 +++++++++++++++++++++++++++++++-
 docs/tests/macro_commands.py     |  7 +++---
 2 files changed, 46 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index cdc19b0e35a..605ce570da4 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -72,8 +72,9 @@ jobs:
 
   test-yosys:
     name: Run tests
-    needs: build-yosys
     runs-on: ${{ matrix.os }}
+    needs: [build-yosys, pre_job]
+    if: needs.pre_job.outputs.should_skip != 'true'
     env:
       CC: clang
     strategy:
@@ -122,6 +123,10 @@ jobs:
         run:
           tar -xvf build.tar
 
+      - name: Log yosys-config output
+        run: |
+          ./yosys-config || true
+
       - name: Run tests
         shell: bash
         run: |
@@ -132,3 +137,39 @@ jobs:
         shell: bash
         run: |
           find tests/**/*.err -print -exec cat {} \;
+
+  test-docs:
+    name: Run docs tests
+    runs-on: ${{ matrix.os }}
+    needs: [build-yosys, pre_job]
+    if: needs.pre_job.outputs.should_skip != 'true'
+    env:
+      CC: clang
+    strategy:
+      matrix:
+        os: [ubuntu-20.04, macos-13]
+    steps:
+      - name: Checkout Yosys
+        uses: actions/checkout@v4
+
+      - name: Setup environment
+        uses: ./.github/actions/setup-build-env
+
+      - name: Download build artifact
+        uses: actions/download-artifact@v4
+        with:
+          name: build-${{ matrix.os }}
+
+      - name: Uncompress build
+        shell: bash
+        run:
+          tar -xvf build.tar
+
+      - name: Log yosys-config output
+        run: |
+          ./yosys-config || true
+
+      - name: Run tests
+        shell: bash
+        run: |
+          make -C docs test -j${{ env.procs }}
diff --git a/docs/tests/macro_commands.py b/docs/tests/macro_commands.py
index faf2baa530b..d879e4365b2 100755
--- a/docs/tests/macro_commands.py
+++ b/docs/tests/macro_commands.py
@@ -12,12 +12,13 @@
 # expects __file__ = yosys/docs/tests/macro_commands.py
 TESTS_DIR = Path(__file__).parent
 ROOT_DIR = TESTS_DIR.parent.parent
+logging.log(logging.INFO, f"Using {ROOT_DIR.absolute()} as root directory")
 THIS_FILE = (TESTS_DIR / "macro_commands.py").relative_to(ROOT_DIR)
 MACRO_SOURCE = TESTS_DIR.parent / "source" / "code_examples" / "macro_commands"
-assert MACRO_SOURCE.exists(), f"can't find macro_commands in {MACRO_SOURCE}"
+assert MACRO_SOURCE.exists(), f"can't find macro_commands in {MACRO_SOURCE.absolute()}"
 
-YOSYS = TESTS_DIR.parent.parent / "yosys"
-assert YOSYS.exists(), f"can't find yosys executable in {YOSYS}"
+YOSYS = ROOT_DIR / "yosys"
+assert YOSYS.exists(), f"can't find yosys executable in {YOSYS.absolute()}"
 
 raise_error = False
 # get all macro commands being used

From 0720020226426838c8f670b8288b71284244ed16 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 21 Mar 2024 11:04:24 +1300
Subject: [PATCH 078/499] ci: Drop gcc-12

Setup script unable to install gcc-12 under ubuntu-20.04.
---
 .github/workflows/test-compile.yml | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml
index 5b0c716f0be..ae48c618081 100644
--- a/.github/workflows/test-compile.yml
+++ b/.github/workflows/test-compile.yml
@@ -74,9 +74,6 @@ jobs:
           - os: ubuntu-20.04
             compiler: 'clang-17'
             cpp_std: 'c++11'
-          - os: ubuntu-20.04
-            compiler: 'gcc-12'
-            cpp_std: 'c++11'
           - os: ubuntu-20.04
             compiler: 'gcc-13'
             cpp_std: 'c++11'

From a4c3dcc5a0cc6a32dd4ac756a66394b41cc060f0 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 22 Mar 2024 09:13:39 +1300
Subject: [PATCH 079/499] docs: Fix macro_commands

Get absolute path for `TESTS_DIR` to work from `docs` directory or from `docs/tests` in addition to `yosys` directory.
---
 docs/tests/macro_commands.py | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/docs/tests/macro_commands.py b/docs/tests/macro_commands.py
index d879e4365b2..7ceb092d867 100755
--- a/docs/tests/macro_commands.py
+++ b/docs/tests/macro_commands.py
@@ -10,15 +10,15 @@
 logging.basicConfig(level=logging.INFO)
 
 # expects __file__ = yosys/docs/tests/macro_commands.py
-TESTS_DIR = Path(__file__).parent
+TESTS_DIR = Path(__file__).parent.absolute()
 ROOT_DIR = TESTS_DIR.parent.parent
-logging.log(logging.INFO, f"Using {ROOT_DIR.absolute()} as root directory")
+logging.log(logging.INFO, f"Using {ROOT_DIR} as root directory")
 THIS_FILE = (TESTS_DIR / "macro_commands.py").relative_to(ROOT_DIR)
 MACRO_SOURCE = TESTS_DIR.parent / "source" / "code_examples" / "macro_commands"
-assert MACRO_SOURCE.exists(), f"can't find macro_commands in {MACRO_SOURCE.absolute()}"
+assert MACRO_SOURCE.exists(), f"can't find macro_commands in {MACRO_SOURCE}"
 
 YOSYS = ROOT_DIR / "yosys"
-assert YOSYS.exists(), f"can't find yosys executable in {YOSYS.absolute()}"
+assert YOSYS.exists(), f"can't find yosys executable in {YOSYS}"
 
 raise_error = False
 # get all macro commands being used

From 7fbf286b3f240fe82ca89a22f07497b5f92c6eaa Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 22 Mar 2024 09:16:43 +1300
Subject: [PATCH 080/499] ci: Update for main branch rename

---
 .github/workflows/test-build.yml   | 4 ++--
 .github/workflows/test-compile.yml | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index 605ce570da4..5a957e5bb70 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -3,10 +3,10 @@ name: Build and run tests
 on:
   pull_request:
     branches:
-    - master
+    - main
   push:
     branches:
-    - master
+    - main
 
 jobs:
   pre_job:
diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml
index ae48c618081..88eaed90c35 100644
--- a/.github/workflows/test-compile.yml
+++ b/.github/workflows/test-compile.yml
@@ -3,10 +3,10 @@ name: Compiler testing
 on:
   pull_request:
     branches:
-    - master
+    - main
   push:
     branches:
-    - master
+    - main
 
 jobs:
   pre_job:

From c89c5c34a0782d5cdcac37ed60c6b40be08921cc Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 22 Mar 2024 10:06:30 +1300
Subject: [PATCH 081/499] ci: Disable fail fast for test runs

---
 .github/workflows/test-build.yml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index 5a957e5bb70..2f078ae6974 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -80,6 +80,7 @@ jobs:
     strategy:
       matrix:
         os: [ubuntu-20.04, macos-13]
+      fail-fast: false
     steps:
       - name: Checkout Yosys
         uses: actions/checkout@v4
@@ -148,6 +149,7 @@ jobs:
     strategy:
       matrix:
         os: [ubuntu-20.04, macos-13]
+      fail-fast: false
     steps:
       - name: Checkout Yosys
         uses: actions/checkout@v4

From 7d8928af4b9488dca402ba90f7d2878c13151bc7 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 22 Mar 2024 10:24:07 +1300
Subject: [PATCH 082/499] ci: Remove macOS from test-docs

macOS fails due to missing gvpack, but trying to install graphviz
triggers a Python update which breaks the macOS runner.
---
 .github/workflows/test-build.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index 2f078ae6974..beb98e60e35 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -148,7 +148,7 @@ jobs:
       CC: clang
     strategy:
       matrix:
-        os: [ubuntu-20.04, macos-13]
+        os: [ubuntu-20.04]
       fail-fast: false
     steps:
       - name: Checkout Yosys

From 144d3c9601341730705920da7e5c73cc20a99d36 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 25 Apr 2024 09:58:07 +1200
Subject: [PATCH 083/499] Add empty line to action.yml

---
 .github/actions/setup-build-env/action.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/actions/setup-build-env/action.yml b/.github/actions/setup-build-env/action.yml
index f61d6565e51..56565ce89fd 100644
--- a/.github/actions/setup-build-env/action.yml
+++ b/.github/actions/setup-build-env/action.yml
@@ -30,4 +30,4 @@ runs:
         echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
         echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH
         echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
-        echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV
\ No newline at end of file
+        echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV

From fc48c3a8719c413dd48aa122695166d506673173 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 25 Apr 2024 10:41:28 +1200
Subject: [PATCH 084/499] ci: Update OS/compiler targets

---
 .github/workflows/test-compile.yml | 32 ++++++++++++++++++------------
 1 file changed, 19 insertions(+), 13 deletions(-)

diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml
index 88eaed90c35..935167b629c 100644
--- a/.github/workflows/test-compile.yml
+++ b/.github/workflows/test-compile.yml
@@ -34,7 +34,7 @@ jobs:
     strategy:
       matrix:
         os:
-          - ubuntu-20.04
+          - ubuntu-22.04
         compiler:
           - 'clang-12'
           - 'gcc-11'
@@ -45,36 +45,42 @@ jobs:
           - 'c++20'
         include:
           # macOS builds
+          - os: macos-latest
+            compiler: 'clang'
+            cpp_std: 'c++11'
           - os: macos-13
             compiler: 'clang'
             cpp_std: 'c++11'
           - os: macos-13
             compiler: 'clang'
             cpp_std: 'c++17'
-          # Limited testing for older compilers
-          - os: ubuntu-20.04
+          # ubuntu-22.04 compilers
+          - os: ubuntu-22.04
             compiler: 'clang-11'
             cpp_std: 'c++11'
-          - os: ubuntu-20.04
-            compiler: 'gcc-10'
-            cpp_std: 'c++11'
-          # Limited testing for newer compilers
-          - os: ubuntu-20.04
+          - os: ubuntu-22.04
             compiler: 'clang-13'
             cpp_std: 'c++11'
-          - os: ubuntu-20.04
+          # ubuntu-latest compilers
+          - os: ubuntu-latest
             compiler: 'clang-14'
             cpp_std: 'c++11'
-          - os: ubuntu-20.04
+          - os: ubuntu-latest
             compiler: 'clang-15'
             cpp_std: 'c++11'
-          - os: ubuntu-20.04
+          - os: ubuntu-latest
             compiler: 'clang-16'
             cpp_std: 'c++11'
-          - os: ubuntu-20.04
+          - os: ubuntu-latest
             compiler: 'clang-17'
             cpp_std: 'c++11'
-          - os: ubuntu-20.04
+          - os: ubuntu-latest
+            compiler: 'gcc-10'
+            cpp_std: 'c++11'
+          - os: ubuntu-latest
+            compiler: 'gcc-12'
+            cpp_std: 'c++11'
+          - os: ubuntu-latest
             compiler: 'gcc-13'
             cpp_std: 'c++11'
       fail-fast: false

From 8fc7dcb5165ccc051fb3f838843fd3f50d076450 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 25 Apr 2024 10:42:50 +1200
Subject: [PATCH 085/499] ci: Drop python2

---
 .github/actions/setup-build-env/action.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/actions/setup-build-env/action.yml b/.github/actions/setup-build-env/action.yml
index 56565ce89fd..d938d6b27ae 100644
--- a/.github/actions/setup-build-env/action.yml
+++ b/.github/actions/setup-build-env/action.yml
@@ -8,7 +8,7 @@ runs:
       shell: bash
       run: |
         sudo apt-get update
-        sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
+        sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
 
     - name: Install macOS Dependencies
       if: runner.os == 'macOS'

From eae7356c701d8419859e378bada12b6550d65262 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 25 Apr 2024 08:37:44 +0200
Subject: [PATCH 086/499] Cleanups and update of VS action

---
 .github/workflows/test-build.yml   | 14 ++++----------
 .github/workflows/test-compile.yml |  8 +-------
 .gitignore                         |  1 -
 3 files changed, 5 insertions(+), 18 deletions(-)

diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index beb98e60e35..703cb6bd70a 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -1,12 +1,6 @@
 name: Build and run tests
 
-on:
-  pull_request:
-    branches:
-    - main
-  push:
-    branches:
-    - main
+on: [push, pull_request]
 
 jobs:
   pre_job:
@@ -32,7 +26,7 @@ jobs:
       CC: clang
     strategy:
       matrix:
-        os: [ubuntu-20.04, macos-13]
+        os: [ubuntu-latest, macos-13]
       fail-fast: false
     steps:
       - name: Checkout Yosys
@@ -79,7 +73,7 @@ jobs:
       CC: clang
     strategy:
       matrix:
-        os: [ubuntu-20.04, macos-13]
+        os: [ubuntu-latest, macos-13]
       fail-fast: false
     steps:
       - name: Checkout Yosys
@@ -148,7 +142,7 @@ jobs:
       CC: clang
     strategy:
       matrix:
-        os: [ubuntu-20.04]
+        os: [ubuntu-latest]
       fail-fast: false
     steps:
       - name: Checkout Yosys
diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml
index 935167b629c..6dd348102b5 100644
--- a/.github/workflows/test-compile.yml
+++ b/.github/workflows/test-compile.yml
@@ -1,12 +1,6 @@
 name: Compiler testing
 
-on:
-  pull_request:
-    branches:
-    - main
-  push:
-    branches:
-    - main
+on: [push, pull_request]
 
 jobs:
   pre_job:
diff --git a/.gitignore b/.gitignore
index b4797d63884..6f3e521d62e 100644
--- a/.gitignore
+++ b/.gitignore
@@ -45,4 +45,3 @@ __pycache__
 /tests/unit/bintest/
 /tests/unit/objtest/
 /tests/ystests
-/build

From 24b3690c255d8e23a0d422daf3c5dad20e645952 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 30 Apr 2024 11:01:30 +1200
Subject: [PATCH 087/499] test-build: Use macos-latest (macOS 14, M1)

---
 .github/workflows/test-build.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index 703cb6bd70a..c73aa995347 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -26,7 +26,7 @@ jobs:
       CC: clang
     strategy:
       matrix:
-        os: [ubuntu-latest, macos-13]
+        os: [ubuntu-latest, macos-latest]
       fail-fast: false
     steps:
       - name: Checkout Yosys
@@ -73,7 +73,7 @@ jobs:
       CC: clang
     strategy:
       matrix:
-        os: [ubuntu-latest, macos-13]
+        os: [ubuntu-latest, macos-latest]
       fail-fast: false
     steps:
       - name: Checkout Yosys

From 6908330005f8e1b08a5367fe25a82b2670c482d0 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 30 Apr 2024 11:11:46 +1200
Subject: [PATCH 088/499] ci: Reduce number of jobs

Limit compilers to oldest and newest.
Oldest compilers test with minimum supported standard.
Newest compilers test with minimum *and* maximum supported standard.
---
 .github/workflows/test-compile.yml | 66 ++++++++----------------------
 Makefile                           |  6 +++
 2 files changed, 24 insertions(+), 48 deletions(-)

diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml
index 6dd348102b5..6a9097ad33a 100644
--- a/.github/workflows/test-compile.yml
+++ b/.github/workflows/test-compile.yml
@@ -22,61 +22,26 @@ jobs:
     needs: pre_job
     if: needs.pre_job.outputs.should_skip != 'true'
     env:
-      CXXSTD: ${{ matrix.cpp_std }}
       CXXFLAGS: ${{ startsWith(matrix.compiler, 'gcc') && '-Wp,-D_GLIBCXX_ASSERTIONS' || ''}}
       CC_SHORT: ${{ startsWith(matrix.compiler, 'gcc') && 'gcc' || 'clang' }}
     strategy:
       matrix:
         os:
-          - ubuntu-22.04
+          - ubuntu-latest
         compiler:
-          - 'clang-12'
-          - 'gcc-11'
-        cpp_std:
-          - 'c++11'
-          - 'c++14'
-          - 'c++17'
-          - 'c++20'
+          # oldest supported
+          - 'clang-14'
+          - 'gcc-10'
+          # newest
+          - 'clang'
+          - 'gcc'
         include:
-          # macOS builds
-          - os: macos-latest
-            compiler: 'clang'
-            cpp_std: 'c++11'
-          - os: macos-13
-            compiler: 'clang'
-            cpp_std: 'c++11'
+          # macOS
           - os: macos-13
             compiler: 'clang'
-            cpp_std: 'c++17'
-          # ubuntu-22.04 compilers
+          # oldest clang not available on ubuntu-latest
           - os: ubuntu-22.04
             compiler: 'clang-11'
-            cpp_std: 'c++11'
-          - os: ubuntu-22.04
-            compiler: 'clang-13'
-            cpp_std: 'c++11'
-          # ubuntu-latest compilers
-          - os: ubuntu-latest
-            compiler: 'clang-14'
-            cpp_std: 'c++11'
-          - os: ubuntu-latest
-            compiler: 'clang-15'
-            cpp_std: 'c++11'
-          - os: ubuntu-latest
-            compiler: 'clang-16'
-            cpp_std: 'c++11'
-          - os: ubuntu-latest
-            compiler: 'clang-17'
-            cpp_std: 'c++11'
-          - os: ubuntu-latest
-            compiler: 'gcc-10'
-            cpp_std: 'c++11'
-          - os: ubuntu-latest
-            compiler: 'gcc-12'
-            cpp_std: 'c++11'
-          - os: ubuntu-latest
-            compiler: 'gcc-13'
-            cpp_std: 'c++11'
       fail-fast: false
     steps:
       - name: Checkout Yosys
@@ -96,12 +61,17 @@ jobs:
           $CC --version
           $CXX --version
 
-      - name: Build
+      # minimum standard
+      - name: Build C++11
         shell: bash
         run: |
           make config-$CC_SHORT
-          make -j$procs CXXSTD=$CXXSTD
+          make -j$procs CXXSTD=c++11 compile-only
 
-      - name: Log yosys-config output
+      # maximum standard, only on newest compilers
+      - name: Build C++20
+        if: ${{ matrix.compiler == 'clang' || matrix.compiler == 'gcc'}}
+        shell: bash
         run: |
-          ./yosys-config || true
+          make config-$CC_SHORT
+          make -j$procs CXXSTD=c++20 compile-only
diff --git a/Makefile b/Makefile
index f359ab76749..85391d47013 100644
--- a/Makefile
+++ b/Makefile
@@ -727,6 +727,12 @@ top-all: $(TARGETS) $(EXTRA_TARGETS)
 	@echo "  Build successful."
 	@echo ""
 
+.PHONY: compile-only
+compile-only: $(OBJS)
+	@echo ""
+	@echo "  Compile successful."
+	@echo ""
+
 ifeq ($(CONFIG),emcc)
 yosys.js: $(filter-out yosysjs-$(YOSYS_VER).zip,$(EXTRA_TARGETS))
 endif

From 4d8ce13aa4d4e347b552b9e365238e83c6a14b3c Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 30 Apr 2024 11:18:42 +1200
Subject: [PATCH 089/499] compile-only: Include genfiles and extra_targets

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 85391d47013..8f427579d92 100644
--- a/Makefile
+++ b/Makefile
@@ -728,7 +728,7 @@ top-all: $(TARGETS) $(EXTRA_TARGETS)
 	@echo ""
 
 .PHONY: compile-only
-compile-only: $(OBJS)
+compile-only: $(OBJS) $(GENFILES) $(EXTRA_TARGETS)
 	@echo ""
 	@echo "  Compile successful."
 	@echo ""

From ff730f486a80d73f6502cb6b39ec7c25571a90e1 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 30 Apr 2024 11:38:05 +1200
Subject: [PATCH 090/499] ci: Add autoconf to macos dependencies

---
 .github/actions/setup-build-env/action.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/actions/setup-build-env/action.yml b/.github/actions/setup-build-env/action.yml
index d938d6b27ae..345b6db8ada 100644
--- a/.github/actions/setup-build-env/action.yml
+++ b/.github/actions/setup-build-env/action.yml
@@ -14,7 +14,7 @@ runs:
       if: runner.os == 'macOS'
       shell: bash
       run: |
-        brew install bison flex gawk libffi pkg-config bash
+        HOMEBREW_NO_INSTALLED_DEPENDENTS_CHECK=1 brew install bison flex gawk libffi pkg-config bash autoconf
 
     - name: Linux runtime environment
       if: runner.os == 'Linux'

From 7905921bd0cdeafb714886aa13021e96b42ffff4 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 10 May 2024 10:00:33 +1200
Subject: [PATCH 091/499] Remove test-docs.yml in favour of test-build

---
 .github/workflows/test-docs.yml | 58 ---------------------------------
 1 file changed, 58 deletions(-)
 delete mode 100644 .github/workflows/test-docs.yml

diff --git a/.github/workflows/test-docs.yml b/.github/workflows/test-docs.yml
deleted file mode 100644
index 7b3906c52ca..00000000000
--- a/.github/workflows/test-docs.yml
+++ /dev/null
@@ -1,58 +0,0 @@
-name: Build and test doc code samples
-
-on:
-  pull_request:
-    branches:
-    - main
-
-jobs:
-  pre_job:
-    runs-on: ubuntu-latest
-    outputs:
-      should_skip: ${{ steps.skip_check.outputs.should_skip }}
-    steps:
-      - id: skip_check
-        uses: fkirc/skip-duplicate-actions@v5
-        with:
-          # cancel previous builds if a new commit is pushed
-          cancel_others: 'true'
-          # only run on push *or* pull_request, not both
-          concurrent_skipping: 'same_content_newer'
-
-  test-docs:
-    needs: pre_job
-    if: needs.pre_job.outputs.should_skip != 'true'
-    runs-on: ubuntu-latest
-    steps:
-      - name: Install Dependencies
-        shell: bash
-        run: |
-          sudo apt-get update
-          sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
-
-      - name: Setup GCC
-        uses: Dup4/actions-setup-gcc@v1
-
-      - name: Runtime environment
-        shell: bash
-        env:
-          WORKSPACE: ${{ github.workspace }}
-        run: |
-          echo "GITHUB_WORKSPACE=`pwd`" >> $GITHUB_ENV
-          echo "$GITHUB_WORKSPACE/.local/bin" >> $GITHUB_PATH
-          echo "procs=$(nproc)" >> $GITHUB_ENV
-
-      - name: Checkout Yosys
-        uses: actions/checkout@v4
-        with:
-         submodules: true
-      - name: Build yosys
-        shell: bash
-        run: |
-          make config-gcc
-          make -j${{ env.procs }}
-
-      - name: Run tests
-        shell: bash
-        run: |
-          make -C docs test -j${{ env.procs }}

From c24a9063b6c5cb6591906ceed497b89b1f4ee36f Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 10 May 2024 10:15:03 +1200
Subject: [PATCH 092/499] Fix submodules

---
 .github/workflows/test-build.yml   | 2 ++
 .github/workflows/test-compile.yml | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index c73aa995347..e13b96816ab 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -31,6 +31,8 @@ jobs:
     steps:
       - name: Checkout Yosys
         uses: actions/checkout@v4
+        with:
+          submodules: true
 
       - name: Setup environment
         uses: ./.github/actions/setup-build-env
diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml
index 6a9097ad33a..375ea7fc54a 100644
--- a/.github/workflows/test-compile.yml
+++ b/.github/workflows/test-compile.yml
@@ -46,6 +46,8 @@ jobs:
     steps:
       - name: Checkout Yosys
         uses: actions/checkout@v4
+        with:
+          submodules: true
 
       - name: Setup environment
         uses: ./.github/actions/setup-build-env

From 16579176936a475428c74a3e540eb70e43e485dd Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Fri, 10 May 2024 00:16:44 +0000
Subject: [PATCH 093/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 507d46f230d..106396d726d 100644
--- a/Makefile
+++ b/Makefile
@@ -142,7 +142,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.41+8
+YOSYS_VER := 0.41+24
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From d73771b0d96f414a48609a27a2a0162031df477b Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 10 May 2024 15:01:39 +0200
Subject: [PATCH 094/499] Make abc Makefile check for dependancies

---
 Makefile | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/Makefile b/Makefile
index 106396d726d..f5bc4072981 100644
--- a/Makefile
+++ b/Makefile
@@ -788,7 +788,6 @@ check-git-abc:
 		echo "Initialize the submodule: Run 'git submodule update --init' to set up 'abc' as a submodule."; \
 		exit 1; \
 	elif git -C "$(YOSYS_SRC)" submodule status abc 2>/dev/null | grep -q '^ '; then \
-		echo "'abc' is a git submodule. Continuing."; \
 		exit 0; \
 	elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && ! grep -q '\$$Format:%h\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \
 		echo "'abc' comes from a tarball. Continuing."; \
@@ -806,9 +805,7 @@ check-git-abc:
 		exit 1; \
 	fi
 
-ABC_SOURCES := $(wildcard $(YOSYS_SRC)/abc/*)
-
-abc/abc$(EXE) abc/libabc.a: $(ABC_SOURCES) check-git-abc
+abc/abc$(EXE) abc/libabc.a: check-git-abc
 	$(P)
 	$(Q) mkdir -p abc && $(MAKE) -C $(PROGRAM_PREFIX)abc -f "$(realpath $(YOSYS_SRC)/abc/Makefile)" ABCSRC="$(realpath $(YOSYS_SRC)/abc/)" $(S) $(ABCMKARGS) $(if $(filter %.a,$@),PROG="abc",PROG="abc$(EXE)") MSG_PREFIX="$(eval P_OFFSET = 5)$(call P_SHOW)$(eval P_OFFSET = 10) ABC: " $(if $(filter %.a,$@),libabc.a)
 

From a31620fda3283cb91d9157b61d699ac4044ba40c Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 10 May 2024 15:02:06 +0200
Subject: [PATCH 095/499] make yosys-abc build before yosys

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index f5bc4072981..7e06deb13d7 100644
--- a/Makefile
+++ b/Makefile
@@ -495,7 +495,7 @@ LIBS += -lpthread
 endif
 else
 ifeq ($(ABCEXTERNAL),)
-TARGETS += $(PROGRAM_PREFIX)yosys-abc$(EXE)
+TARGETS := $(PROGRAM_PREFIX)yosys-abc$(EXE) $(TARGETS)
 endif
 endif
 endif

From cef8bedf63edce900731d7ce296d34d3597efd93 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 10 May 2024 15:03:17 +0200
Subject: [PATCH 096/499] Remove emcc target from Makefile

---
 Makefile | 54 +-----------------------------------------------------
 1 file changed, 1 insertion(+), 53 deletions(-)

diff --git a/Makefile b/Makefile
index 7e06deb13d7..e2354853f17 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,6 @@ CONFIG := none
 # CONFIG := clang
 # CONFIG := gcc
 # CONFIG := afl-gcc
-# CONFIG := emcc
 # CONFIG := wasi
 # CONFIG := mxe
 # CONFIG := msys2-32
@@ -254,45 +253,6 @@ CXX = g++
 CXXFLAGS += -std=gnu++11 -Os
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
 
-else ifeq ($(CONFIG),emcc)
-CXX = emcc
-CXXFLAGS := -std=$(CXXSTD) $(filter-out -fPIC -ggdb,$(CXXFLAGS))
-ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DABC_MEMALIGN=8"
-EMCC_CXXFLAGS := -Os -Wno-warn-absolute-paths
-EMCC_LINKFLAGS := --embed-file share
-EMCC_LINKFLAGS += -s NO_EXIT_RUNTIME=1
-EMCC_LINKFLAGS += -s EXPORTED_FUNCTIONS="['_main','_run','_prompt','_errmsg','_memset']"
-EMCC_LINKFLAGS += -s TOTAL_MEMORY=134217728
-EMCC_LINKFLAGS += -s EXPORTED_RUNTIME_METHODS='["ccall", "cwrap"]'
-# https://github.com/kripken/emscripten/blob/master/src/settings.js
-CXXFLAGS += $(EMCC_CXXFLAGS)
-LINKFLAGS += $(EMCC_LINKFLAGS)
-LIBS =
-EXE = .js
-
-DISABLE_SPAWN := 1
-
-TARGETS := $(filter-out $(PROGRAM_PREFIX)yosys-config,$(TARGETS))
-EXTRA_TARGETS += yosysjs-$(YOSYS_VER).zip
-
-ifeq ($(ENABLE_ABC),1)
-LINK_ABC := 1
-DISABLE_ABC_THREADS := 1
-endif
-
-viz.js:
-	wget -O viz.js.part https://github.com/mdaines/viz.js/releases/download/0.0.3/viz.js
-	mv viz.js.part viz.js
-
-yosysjs-$(YOSYS_VER).zip: yosys.js viz.js misc/yosysjs/*
-	rm -rf yosysjs-$(YOSYS_VER) yosysjs-$(YOSYS_VER).zip
-	mkdir -p yosysjs-$(YOSYS_VER)
-	cp viz.js misc/yosysjs/* yosys.js yosys.wasm yosysjs-$(YOSYS_VER)/
-	zip -r yosysjs-$(YOSYS_VER).zip yosysjs-$(YOSYS_VER)
-
-yosys.html: misc/yosys.html
-	$(P) cp misc/yosys.html yosys.html
-
 else ifeq ($(CONFIG),wasi)
 ifeq ($(WASI_SDK),)
 CXX = clang++
@@ -357,7 +317,7 @@ CXXFLAGS += -std=$(CXXSTD) -Os
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H $(ABC_ARCHFLAGS)"
 
 else
-$(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc, emcc, mxe, msys2-32, msys2-64, none)
+$(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc, mxe, msys2-32, msys2-64, none)
 endif
 
 ifeq ($(ENABLE_LIBYOSYS),1)
@@ -727,10 +687,6 @@ top-all: $(TARGETS) $(EXTRA_TARGETS)
 	@echo "  Build successful."
 	@echo ""
 
-ifeq ($(CONFIG),emcc)
-yosys.js: $(filter-out yosysjs-$(YOSYS_VER).zip,$(EXTRA_TARGETS))
-endif
-
 $(PROGRAM_PREFIX)yosys$(EXE): $(OBJS)
 	$(P) $(CXX) -o $(PROGRAM_PREFIX)yosys$(EXE) $(EXE_LINKFLAGS) $(LINKFLAGS) $(OBJS) $(LIBS) $(LIBS_VERIFIC)
 
@@ -1082,14 +1038,6 @@ config-gcc-static: clean
 config-afl-gcc: clean
 	echo 'CONFIG := afl-gcc' > Makefile.conf
 
-config-emcc: clean
-	echo 'CONFIG := emcc' > Makefile.conf
-	echo 'ENABLE_TCL := 0' >> Makefile.conf
-	echo 'ENABLE_ABC := 0' >> Makefile.conf
-	echo 'ENABLE_PLUGINS := 0' >> Makefile.conf
-	echo 'ENABLE_READLINE := 0' >> Makefile.conf
-	echo 'ENABLE_ZLIB := 0' >> Makefile.conf
-
 config-wasi: clean
 	echo 'CONFIG := wasi' > Makefile.conf
 	echo 'ENABLE_TCL := 0' >> Makefile.conf

From 6dde8107c3214a917eb7f1c1683576fde4922840 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 10 May 2024 15:46:32 +0200
Subject: [PATCH 097/499] Remove checkout for specific iverilog git version

---
 .github/workflows/test-build.yml | 1 -
 1 file changed, 1 deletion(-)

diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index e13b96816ab..5966ec3afdf 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -89,7 +89,6 @@ jobs:
         run: |
           git clone https://github.com/steveicarus/iverilog.git
           cd iverilog
-          git checkout 192b6aec96fde982e6ddcb28b346d5893aa8e874
           echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV
 
       - name: Cache iverilog

From 9be7089f4f90365ff3105824f3867b84d6bca077 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Sat, 11 May 2024 10:40:28 +1200
Subject: [PATCH 098/499] Docs-css: Add invert-helper class for images

Use svg color filter matrix from @jix to invert brightness for images when using dark theme.

Co-authored-by: Jannis Harder <me@jix.one>
---
 docs/source/_static/yosyshq.css | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/docs/source/_static/yosyshq.css b/docs/source/_static/yosyshq.css
index 57ae8f87a5f..447c8536743 100644
--- a/docs/source/_static/yosyshq.css
+++ b/docs/source/_static/yosyshq.css
@@ -24,3 +24,17 @@ a.external {
 th {
     text-align: left;
 }
+
+body[data-theme="dark"] {
+    .invert-helper {
+        filter: url("data:image/svg+xml,<svg xmlns='http%3A//www.w3.org/2000/svg'><filter id='f'><feColorMatrix color-interpolation-filters='sRGB' type='matrix' values='1.47 -1.73 -0.467 0 0.867 -0.733 0.467 -0.467 0 0.867 -0.667 -1.07 1.07 0 0.867 0 0 0 1.0 0'></feColorMatrix></filter></svg>#f");
+    }
+}
+
+@media (prefers-color-scheme: dark) {
+    body:not([data-theme="light"]) {
+        .invert-helper {
+            filter: url("data:image/svg+xml,<svg xmlns='http%3A//www.w3.org/2000/svg'><filter id='f'><feColorMatrix color-interpolation-filters='sRGB' type='matrix' values='1.47 -1.73 -0.467 0 0.867 -0.733 0.467 -0.467 0 0.867 -0.667 -1.07 1.07 0 0.867 0 0 0 1.0 0'></feColorMatrix></filter></svg>#f");
+        }
+    }
+}
\ No newline at end of file

From 3a36612ec7bbf4e445e5dc80a902002f1bd0bfa4 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Sat, 11 May 2024 10:40:54 +1200
Subject: [PATCH 099/499] Docs: Apply invert-helper where needed

---
 docs/source/appendix/primer.rst               |  8 ++--
 docs/source/getting_started/example_synth.rst | 32 +++++++--------
 .../getting_started/scripting_intro.rst       |  6 +--
 docs/source/introduction.rst                  |  2 +-
 .../interactive_investigation.rst             | 24 +++++------
 .../using_yosys/more_scripting/selections.rst | 26 ++++++------
 .../using_yosys/synthesis/cell_libs.rst       |  8 ++--
 docs/source/using_yosys/synthesis/extract.rst | 40 +++++++++----------
 docs/source/using_yosys/synthesis/memory.rst  |  4 +-
 docs/source/using_yosys/synthesis/opt.rst     |  8 ++--
 docs/source/using_yosys/synthesis/proc.rst    |  6 +--
 .../extending_yosys/extensions.rst            |  4 +-
 .../yosys_internals/flow/control_and_data.rst |  2 +-
 docs/source/yosys_internals/flow/overview.rst |  2 +-
 .../yosys_internals/flow/verilog_frontend.rst |  2 +-
 .../yosys_internals/formats/rtlil_rep.rst     |  2 +-
 docs/source/yosys_internals/techmap.rst       | 10 ++---
 17 files changed, 93 insertions(+), 93 deletions(-)

diff --git a/docs/source/appendix/primer.rst b/docs/source/appendix/primer.rst
index 101723e32cb..50656af780e 100644
--- a/docs/source/appendix/primer.rst
+++ b/docs/source/appendix/primer.rst
@@ -24,7 +24,7 @@ circuit to a functionally equivalent low-level representation of a circuit.
 abstraction and how they relate to different kinds of synthesis.
 
 .. figure:: /_images/primer/basics_abstractions.*
-	:class: width-helper
+	:class: width-helper invert-helper
 	:name: fig:Basics_abstractions
 
 	Different levels of abstraction and synthesis.
@@ -499,7 +499,7 @@ using a series of tools and the results are again verified using simulation.
 This process is illustrated in :numref:`Fig. %s <fig:Basics_flow>`.
 
 .. figure:: /_images/primer/basics_flow.*
-	:class: width-helper
+	:class: width-helper invert-helper
 	:name: fig:Basics_flow
 
 	Typical design flow.  Green boxes represent manually created models.
@@ -598,7 +598,7 @@ Let's consider the following BNF (in Bison syntax):
    expr: TOK_IDENTIFIER | TOK_NUMBER | expr TOK_PLUS expr;
 
 .. figure:: /_images/primer/basics_parsetree.*
-	:class: width-helper
+	:class: width-helper invert-helper
 	:name: fig:Basics_parsetree
 
 	Example parse tree for the Verilog expression 
@@ -627,7 +627,7 @@ suitable for further processing. In compilers this is often an assembler-like
 three-address-code intermediate representation. :cite:p:`Dragonbook`
 
 .. figure:: /_images/primer/basics_ast.*
-	:class: width-helper
+	:class: width-helper invert-helper
 	:name: fig:Basics_ast
 
 	Example abstract syntax tree for the Verilog expression 
diff --git a/docs/source/getting_started/example_synth.rst b/docs/source/getting_started/example_synth.rst
index 916bef9fabd..ae0a9a36620 100644
--- a/docs/source/getting_started/example_synth.rst
+++ b/docs/source/getting_started/example_synth.rst
@@ -122,7 +122,7 @@ Since we're just getting started, let's instead begin with :yoscrypt:`hierarchy
 Our ``addr_gen`` circuit now looks like this:
 
 .. figure:: /_images/code_examples/fifo/addr_gen_hier.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: addr_gen_hier
 
    ``addr_gen`` module after :cmd:ref:`hierarchy`
@@ -145,7 +145,7 @@ we run it.  For now, we will call :yoscrypt:`proc -noopt` to prevent some
 automatic optimizations which would normally happen.
 
 .. figure:: /_images/code_examples/fifo/addr_gen_proc.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: addr_gen_proc
 
    ``addr_gen`` module after :yoscrypt:`proc -noopt`
@@ -166,7 +166,7 @@ the same time by separating them with a colon and space: :yoscrypt:`opt_expr;
 clean`.
 
 .. figure:: /_images/code_examples/fifo/addr_gen_clean.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: addr_gen_clean
 
    ``addr_gen`` module after :yoscrypt:`opt_expr; clean`
@@ -252,7 +252,7 @@ command only works with a single module, so you may need to call it with
 :doc:`/getting_started/scripting_intro` has more on how to use :cmd:ref:`show`.
 
 .. figure:: /_images/code_examples/fifo/rdata_proc.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: rdata_proc
 
    ``rdata`` output after :cmd:ref:`proc`
@@ -298,7 +298,7 @@ optimizations between modules which would otherwise be missed.  Let's run
    :caption: output of :yoscrypt:`flatten;;`
 
 .. figure:: /_images/code_examples/fifo/rdata_flat.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: rdata_flat
 
    ``rdata`` output after :yoscrypt:`flatten;;`
@@ -385,7 +385,7 @@ options is able to fold one of the ``$mux`` cells into the ``$adff`` to form an
    :caption: output of :cmd:ref:`opt_dff`
 
 .. figure:: /_images/code_examples/fifo/rdata_adffe.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: rdata_adffe
 
    ``rdata`` output after :cmd:ref:`opt_dff`
@@ -424,7 +424,7 @@ the schematic and see the output of that cell has now changed.
 .. todo:: pending bugfix in :cmd:ref:`wreduce` and/or :cmd:ref:`opt_clean`
 
 .. figure:: /_images/code_examples/fifo/rdata_wreduce.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: rdata_wreduce
 
    ``rdata`` output after :cmd:ref:`wreduce`
@@ -446,7 +446,7 @@ Our next command to run is
    :caption: output of :cmd:ref:`memory_dff`
 
 .. figure:: /_images/code_examples/fifo/rdata_memrdv2.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: rdata_memrdv2
 
    ``rdata`` output after :cmd:ref:`memory_dff`
@@ -535,7 +535,7 @@ example design:
    :caption: output of :cmd:ref:`alumacc`
 
 .. figure:: /_images/code_examples/fifo/rdata_alumacc.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: rdata_alumacc
 
    ``rdata`` output after :cmd:ref:`alumacc`
@@ -553,7 +553,7 @@ operating on the same memory only in the abstract. :cmd:ref:`memory_collect`
 combines all of the reads and writes for a memory block into a single cell.
 
 .. figure:: /_images/code_examples/fifo/rdata_coarse.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: rdata_coarse
 
    ``rdata`` output after :cmd:ref:`memory_collect`
@@ -604,7 +604,7 @@ Mapping to hard memory blocks uses a combination of :cmd:ref:`memory_libmap` and
    :caption: ``map_ram`` section
 
 .. figure:: /_images/code_examples/fifo/rdata_map_ram.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: rdata_map_ram
 
    ``rdata`` output after :ref:`map_ram`
@@ -646,7 +646,7 @@ into flip flops (the ``logic fallback``) with :cmd:ref:`memory_map`.
    :caption: ``map_ffram`` section
 
 .. figure:: /_images/code_examples/fifo/rdata_map_ffram.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: rdata_map_ffram
 
    ``rdata`` output after :ref:`map_ffram`
@@ -682,7 +682,7 @@ replaced with single-bit ``$_MUX_`` and ``$_DFFE_PP0P_`` cells, while the
    :caption: ``map_gates`` section
 
 .. figure:: /_images/code_examples/fifo/rdata_map_gates.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: rdata_map_gates
 
    ``rdata`` output after :ref:`map_gates`
@@ -711,7 +711,7 @@ instead with an ``$_AND_`` cell.
    :caption: ``map_ffs`` section
 
 .. figure:: /_images/code_examples/fifo/rdata_map_ffs.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: rdata_map_ffs
 
    ``rdata`` output after :ref:`map_ffs`
@@ -737,7 +737,7 @@ what the difference between these two commands are, refer to
    :caption: ``map_luts`` section
 
 .. figure:: /_images/code_examples/fifo/rdata_map_luts.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: rdata_map_luts
 
    ``rdata`` output after :ref:`map_luts`
@@ -754,7 +754,7 @@ Finally we use :cmd:ref:`techmap` to map the generic ``$lut`` cells to iCE40
    :caption: ``map_cells`` section
 
 .. figure:: /_images/code_examples/fifo/rdata_map_cells.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: rdata_map_cells
 
    ``rdata`` output after :ref:`map_cells`
diff --git a/docs/source/getting_started/scripting_intro.rst b/docs/source/getting_started/scripting_intro.rst
index 63eca990125..bda76b74e9a 100644
--- a/docs/source/getting_started/scripting_intro.rst
+++ b/docs/source/getting_started/scripting_intro.rst
@@ -108,7 +108,7 @@ what the different symbols represent, see :ref:`interactive_show` and the
 :doc:`/using_yosys/more_scripting/interactive_investigation` page.
 
 .. figure:: /_images/code_examples/fifo/addr_gen_show.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: addr_gen_show
 
    Calling :yoscrypt:`show addr_gen` after :cmd:ref:`hierarchy`
@@ -158,7 +158,7 @@ selection<select_new_cells>` and called it ``new_cells``?  We saw in the
 ``$eq``.  We can call :cmd:ref:`show` on that selection just as easily:
 
 .. figure:: /_images/code_examples/fifo/new_cells_show.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: new_cells_show
 
    Calling :yoscrypt:`show -notitle @new_cells`
@@ -173,7 +173,7 @@ the two ``PROC`` blocks.  To achieve this highlight, we make use of the
 :yoscrypt:`-color` option:
 
 .. figure:: /_images/code_examples/fifo/addr_gen_hier.*
-   :class: width-helper
+   :class: width-helper invert-helper
 
    Calling :yoscrypt:`show -color maroon3 @new_cells -color cornflowerblue p:* -notitle`
 
diff --git a/docs/source/introduction.rst b/docs/source/introduction.rst
index 936784d7411..1d9cd008044 100644
--- a/docs/source/introduction.rst
+++ b/docs/source/introduction.rst
@@ -151,7 +151,7 @@ extensible and therefore is a good basis for implementing custom synthesis tools
 for specialised tasks.
 
 .. figure:: /_images/primer/levels_of_abstraction.*
-    :class: width-helper
+    :class: width-helper invert-helper
     :name: fig:Levels_of_abstraction
 
     Where Yosys exists in the layers of abstraction
diff --git a/docs/source/using_yosys/more_scripting/interactive_investigation.rst b/docs/source/using_yosys/more_scripting/interactive_investigation.rst
index f56543bebbb..db34f041bb9 100644
--- a/docs/source/using_yosys/more_scripting/interactive_investigation.rst
+++ b/docs/source/using_yosys/more_scripting/interactive_investigation.rst
@@ -56,7 +56,7 @@ is shown.
    ``xdot example_first.dot`` etc.
 
 .. figure:: /_images/code_examples/show/example_first.*
-   :class: width-helper
+   :class: width-helper invert-helper
    
    Output of the first :cmd:ref:`show` command in :numref:`example_ys`
 
@@ -88,7 +88,7 @@ The :cmd:ref:`proc` command transforms the process from the first diagram into a
 multiplexer and a d-type flip-flop, which brings us to the second diagram:
 
 .. figure:: /_images/code_examples/show/example_second.*
-   :class: width-helper
+   :class: width-helper invert-helper
    
    Output of the second :cmd:ref:`show` command in :numref:`example_ys`
 
@@ -110,7 +110,7 @@ In this script we directly call :cmd:ref:`opt` as the next step, which finally
 leads us to the third diagram: 
 
 .. figure:: /_images/code_examples/show/example_third.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: example_out
    
    Output of the third :cmd:ref:`show` command in :ref:`example_ys`
@@ -137,7 +137,7 @@ that operate on wide integers, it also introduces some additional complexity
 when the individual bits of of a signal vector are accessed.
 
 .. figure:: /_images/code_examples/show/splice.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: splice_dia
 
    Output of ``yosys -p 'prep -top splice_demo; show' splice.v``
@@ -165,7 +165,7 @@ Gate level netlists
 mapped to a cell library:
 
 .. figure:: /_images/code_examples/show/cmos_00.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: first_pitfall
 
    A half-adder built from simple CMOS gates, demonstrating common pitfalls when 
@@ -185,7 +185,7 @@ column. Secondly the two-bit vector ``y`` requires breakout-boxes for its
 individual bits, resulting in an unnecessary complex diagram.
 
 .. figure:: /_images/code_examples/show/cmos_01.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: second_pitfall
 
    Effects of :cmd:ref:`splitnets` command and of providing a cell library on 
@@ -358,10 +358,10 @@ reorganizing a module in Yosys and checking the resulting circuit.
    :end-before: cd ..
 
 .. figure:: /_images/code_examples/scrambler/scrambler_p01.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. figure:: /_images/code_examples/scrambler/scrambler_p02.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 Analyzing the resulting circuit with :doc:`/cmd/eval`:
 
@@ -442,7 +442,7 @@ if the circuit under investigation is encapsulated in a separate module.
 Recall the ``memdemo`` design from :ref:`advanced_logic_cones`:
 
 .. figure:: /_images/code_examples/selections/memdemo_00.*
-   :class: width-helper
+   :class: width-helper invert-helper
    
    ``memdemo``
 
@@ -463,18 +463,18 @@ name of the new cell in the current module. The resulting circuits are shown
 below.
 
 .. figure:: /_images/code_examples/selections/submod_02.*
-   :class: width-helper
+   :class: width-helper invert-helper
    
    ``outstage``
 
 .. figure:: /_images/code_examples/selections/submod_03.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: selstage
    
    ``selstage``
 
 .. figure:: /_images/code_examples/selections/submod_01.*
-   :class: width-helper
+   :class: width-helper invert-helper
    
    ``scramble``
 
diff --git a/docs/source/using_yosys/more_scripting/selections.rst b/docs/source/using_yosys/more_scripting/selections.rst
index 6aa3465cc99..b0028347499 100644
--- a/docs/source/using_yosys/more_scripting/selections.rst
+++ b/docs/source/using_yosys/more_scripting/selections.rst
@@ -160,7 +160,7 @@ Selecting ``a:sumstuff`` in this module will yield the following circuit
 diagram:
 
 .. figure:: /_images/code_examples/selections/sumprod_00.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: sumprod_00
 
    Output of ``show a:sumstuff`` on :numref:`sumprod`
@@ -177,7 +177,7 @@ selected wire it selects all cells connected to the wire and vice versa. So
 :yoscrypt:`show a:sumstuff %x` yields the diagram shown in :numref:`sumprod_01`:
 
 .. figure:: /_images/code_examples/selections/sumprod_01.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: sumprod_01
 
    Output of ``show a:sumstuff %x`` on :numref:`sumprod`
@@ -200,22 +200,22 @@ input ports.
 The following sequence of diagrams demonstrates this step-wise expansion:
 
 .. figure:: /_images/code_examples/selections/sumprod_02.*
-   :class: width-helper
+   :class: width-helper invert-helper
 
    Output of :yoscrypt:`show prod` on :numref:`sumprod`
 
 .. figure:: /_images/code_examples/selections/sumprod_03.*
-   :class: width-helper
+   :class: width-helper invert-helper
 
    Output of :yoscrypt:`show prod %ci` on :numref:`sumprod`
 
 .. figure:: /_images/code_examples/selections/sumprod_04.*
-   :class: width-helper
+   :class: width-helper invert-helper
 
    Output of :yoscrypt:`show prod %ci %ci` on :numref:`sumprod`
 
 .. figure:: /_images/code_examples/selections/sumprod_05.*
-   :class: width-helper
+   :class: width-helper invert-helper
 
    Output of :yoscrypt:`show prod %ci %ci %ci` on :numref:`sumprod`
 
@@ -280,7 +280,7 @@ provided :file:`memdemo.v` is in the same directory. We can now change to the
 diagram in :numref:`memdemo_00`.
 
 .. figure:: /_images/code_examples/selections/memdemo_00.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: memdemo_00
    
    Complete circuit diagram for the design shown in :numref:`memdemo_src`
@@ -291,7 +291,7 @@ output signal, ``y``, and its immediate predecessors. Remember `Selecting logic
 cones`_ from above, we can use :yoscrypt:`show y %ci2`:
 
 .. figure:: /_images/code_examples/selections/memdemo_01.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: memdemo_01
    
    Output of :yoscrypt:`show y %ci2`
@@ -303,7 +303,7 @@ wire into the input ``D`` of the flip-flop cell (indicated by the ``$`` at the
 start of the name).  Let's go a bit further now and try :yoscrypt:`show y %ci5`:
 
 .. figure:: /_images/code_examples/selections/memdemo_02.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: memdemo_02
    
    Output of :yoscrypt:`show y %ci5`
@@ -317,7 +317,7 @@ brackets.  In this case, we want to exclude the ``S`` port of the ``$mux`` cell
 type with :yoscrypt:`show y %ci5:-$mux[S]`:
 
 .. figure:: /_images/code_examples/selections/memdemo_03.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: memdemo_03
    
    Output of :yoscrypt:`show y %ci5:-$mux[S]`
@@ -328,7 +328,7 @@ flip-flop and the 2nd action selects the entire input cone without going over
 multiplexer select inputs and flip-flop cells:
 
 .. figure:: /_images/code_examples/selections/memdemo_05.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: memdemo_05
    
    Output of ``show y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff``
@@ -340,7 +340,7 @@ ignoring any ports named ``CLK`` or ``S``:
 .. TODO:: pending discussion on whether rule ordering is a bug or a feature
 
 .. figure:: /_images/code_examples/selections/memdemo_04.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: memdemo_04
    
    Output of :yoscrypt:`show y %ci*:-[CLK,S]:+$dff,$mux`
@@ -417,6 +417,6 @@ Example code from |code_examples/selections|_:
    :name: select_ys
 
 .. figure:: /_images/code_examples/selections/select.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
     Circuit diagram produced by :numref:`select_ys`
diff --git a/docs/source/using_yosys/synthesis/cell_libs.rst b/docs/source/using_yosys/synthesis/cell_libs.rst
index 476269abfc9..92b6dab3f58 100644
--- a/docs/source/using_yosys/synthesis/cell_libs.rst
+++ b/docs/source/using_yosys/synthesis/cell_libs.rst
@@ -51,7 +51,7 @@ Loading the design
 Our circuit now looks like this:
 
 .. figure:: /_images/code_examples/intro/counter_00.*
-   :class: width-helper
+   :class: width-helper invert-helper
    :name: counter-hierarchy
 
    ``counter`` after :cmd:ref:`hierarchy`
@@ -66,7 +66,7 @@ Coarse-grain representation
    :caption: :file:`counter.ys` - the high-level stuff
 
 .. figure:: /_images/code_examples/intro/counter_01.*
-   :class: width-helper
+   :class: width-helper invert-helper
 
    Coarse-grain representation of the ``counter`` module
 
@@ -80,7 +80,7 @@ Logic gate mapping
    :caption: :file:`counter.ys` - mapping to internal cell library
 
 .. figure:: /_images/code_examples/intro/counter_02.*
-   :class: width-helper
+   :class: width-helper invert-helper
 
    ``counter`` after :cmd:ref:`techmap`
 
@@ -111,7 +111,7 @@ Recall that the Yosys built-in logic gate types are ``$_NOT_``, ``$_AND_``,
 The final version of our ``counter`` module looks like this:
 
 .. figure:: /_images/code_examples/intro/counter_03.*
-   :class: width-helper
+   :class: width-helper invert-helper
 
    ``counter`` after hardware cell mapping
 
diff --git a/docs/source/using_yosys/synthesis/extract.rst b/docs/source/using_yosys/synthesis/extract.rst
index bbe1870dfb3..c9b76840e3b 100644
--- a/docs/source/using_yosys/synthesis/extract.rst
+++ b/docs/source/using_yosys/synthesis/extract.rst
@@ -23,7 +23,7 @@ Example code can be found in |code_examples/macc|_.
     :lines: 1-2
 
 .. figure:: /_images/code_examples/macc/macc_simple_test_00a.*
-    :class: width-helper
+    :class: width-helper invert-helper
     
     before :cmd:ref:`extract`
 
@@ -32,7 +32,7 @@ Example code can be found in |code_examples/macc|_.
     :lines: 6
 
 .. figure:: /_images/code_examples/macc/macc_simple_test_00b.*
-    :class: width-helper
+    :class: width-helper invert-helper
     
     after :cmd:ref:`extract`
 
@@ -49,20 +49,20 @@ Example code can be found in |code_examples/macc|_.
    :caption: :file:`macc_simple_test_01.v`
 
 .. figure:: /_images/code_examples/macc/macc_simple_test_01a.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. figure:: /_images/code_examples/macc/macc_simple_test_01b.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/macc/macc_simple_test_02.v
    :language: verilog
    :caption: :file:`macc_simple_test_02.v`
 
 .. figure:: /_images/code_examples/macc/macc_simple_test_02a.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. figure:: /_images/code_examples/macc/macc_simple_test_02b.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 The wrap-extract-unwrap method
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -149,10 +149,10 @@ Unwrapping adders: :file:`macc_xilinx_unwrap_map.v`
    :caption: ``test1`` of :file:`macc_xilinx_test.v`
 
 .. figure:: /_images/code_examples/macc/macc_xilinx_test1a.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. figure:: /_images/code_examples/macc/macc_xilinx_test1b.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/macc/macc_xilinx_test.v
    :language: verilog
@@ -160,15 +160,15 @@ Unwrapping adders: :file:`macc_xilinx_unwrap_map.v`
    :caption: ``test2`` of :file:`macc_xilinx_test.v`
 
 .. figure:: /_images/code_examples/macc/macc_xilinx_test2a.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. figure:: /_images/code_examples/macc/macc_xilinx_test2b.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 Wrapping in ``test1``:
 
 .. figure:: /_images/code_examples/macc/macc_xilinx_test1b.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
     :language: yoscrypt
@@ -176,12 +176,12 @@ Wrapping in ``test1``:
     :end-before: end part c
 
 .. figure:: /_images/code_examples/macc/macc_xilinx_test1c.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 Wrapping in ``test2``:
 
 .. figure:: /_images/code_examples/macc/macc_xilinx_test2b.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
     :language: yoscrypt
@@ -189,12 +189,12 @@ Wrapping in ``test2``:
     :end-before: end part c
 
 .. figure:: /_images/code_examples/macc/macc_xilinx_test2c.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 Extract in ``test1``:
 
 .. figure:: /_images/code_examples/macc/macc_xilinx_test1c.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
     :language: yoscrypt
@@ -202,12 +202,12 @@ Extract in ``test1``:
     :end-before: end part d
 
 .. figure:: /_images/code_examples/macc/macc_xilinx_test1d.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 Extract in ``test2``:
 
 .. figure:: /_images/code_examples/macc/macc_xilinx_test2c.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
     :language: yoscrypt
@@ -215,12 +215,12 @@ Extract in ``test2``:
     :end-before: end part d
 
 .. figure:: /_images/code_examples/macc/macc_xilinx_test2d.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 Unwrap in ``test2``:
 
 .. figure:: /_images/code_examples/macc/macc_xilinx_test2d.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
     :language: yoscrypt
@@ -228,4 +228,4 @@ Unwrap in ``test2``:
     :end-before: end part e
 
 .. figure:: /_images/code_examples/macc/macc_xilinx_test2e.*
-    :class: width-helper
\ No newline at end of file
+    :class: width-helper invert-helper
\ No newline at end of file
diff --git a/docs/source/using_yosys/synthesis/memory.rst b/docs/source/using_yosys/synthesis/memory.rst
index 3dbafeaab7e..0f5e1bd3010 100644
--- a/docs/source/using_yosys/synthesis/memory.rst
+++ b/docs/source/using_yosys/synthesis/memory.rst
@@ -39,7 +39,7 @@ Example
 .. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/synth_flow
 
 .. figure:: /_images/code_examples/synth_flow/memory_01.*
-   :class: width-helper
+   :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/synth_flow/memory_01.ys
    :language: yoscrypt
@@ -50,7 +50,7 @@ Example
    :caption: :file:`memory_01.v`
 
 .. figure:: /_images/code_examples/synth_flow/memory_02.*
-   :class: width-helper
+   :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/synth_flow/memory_02.v
    :language: verilog
diff --git a/docs/source/using_yosys/synthesis/opt.rst b/docs/source/using_yosys/synthesis/opt.rst
index 7861f66d4cd..2a06aadd118 100644
--- a/docs/source/using_yosys/synthesis/opt.rst
+++ b/docs/source/using_yosys/synthesis/opt.rst
@@ -88,7 +88,7 @@ trees can interfere with other optimizations.
    :caption: example verilog for demonstrating :cmd:ref:`opt_expr`
 
 .. figure:: /_images/code_examples/opt/opt_expr.*
-   :class: width-helper
+   :class: width-helper invert-helper
 
    Before and after :cmd:ref:`opt_expr`
 
@@ -111,7 +111,7 @@ possible optimizations.
    :caption: example verilog for demonstrating :cmd:ref:`opt_merge`
 
 .. figure:: /_images/code_examples/opt/opt_merge.*
-   :class: width-helper
+   :class: width-helper invert-helper
 
    Before and after :cmd:ref:`opt_merge`
 
@@ -133,7 +133,7 @@ detects this contradiction and replaces the inner multiplexer with a constant 1,
 yielding the logic for ``y = a ? b : d``.
 
 .. figure:: /_images/code_examples/opt/opt_muxtree.*
-   :class: width-helper
+   :class: width-helper invert-helper
 
    Before and after :cmd:ref:`opt_muxtree`
 
@@ -172,7 +172,7 @@ multiplexing its output to multiplexing the non-shared input signals.
    :caption: example verilog for demonstrating :cmd:ref:`opt_share`
 
 .. figure:: /_images/code_examples/opt/opt_share.*
-   :class: width-helper
+   :class: width-helper invert-helper
 
    Before and after :cmd:ref:`opt_share`
 
diff --git a/docs/source/using_yosys/synthesis/proc.rst b/docs/source/using_yosys/synthesis/proc.rst
index b4983438021..d90aa087dc7 100644
--- a/docs/source/using_yosys/synthesis/proc.rst
+++ b/docs/source/using_yosys/synthesis/proc.rst
@@ -42,10 +42,10 @@ Example
    :caption: :file:`proc_01.ys`
 
 .. figure:: /_images/code_examples/synth_flow/proc_01.*
-   :class: width-helper
+   :class: width-helper invert-helper
 
 .. figure:: /_images/code_examples/synth_flow/proc_02.*
-   :class: width-helper
+   :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/synth_flow/proc_02.v
    :language: verilog
@@ -56,7 +56,7 @@ Example
    :caption: :file:`proc_02.ys`
 
 .. figure:: /_images/code_examples/synth_flow/proc_03.*
-   :class: width-helper
+   :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/synth_flow/proc_03.ys
    :language: yoscrypt
diff --git a/docs/source/yosys_internals/extending_yosys/extensions.rst b/docs/source/yosys_internals/extending_yosys/extensions.rst
index 68e1740be4a..f10c634b015 100644
--- a/docs/source/yosys_internals/extending_yosys/extensions.rst
+++ b/docs/source/yosys_internals/extending_yosys/extensions.rst
@@ -38,7 +38,7 @@ This document will focus on the much simpler version of RTLIL left after the
 commands :cmd:ref:`proc` and :cmd:ref:`memory` (or :yoscrypt:`memory -nomap`):
 
 .. figure:: /_images/internals/simplified_rtlil.*
-    :class: width-helper
+    :class: width-helper invert-helper
     :name: fig:Simplified_RTLIL
 
     Simplified RTLIL entity-relationship diagram without memories and processes
@@ -140,7 +140,7 @@ We'll do the same as before and format it as a a ``Yosys::Pass``.
 And if we look at the schematic for this new module we see the following:
 
 .. figure:: /_images/code_examples/extensions/test1.*
-   :class: width-helper
+   :class: width-helper invert-helper
 
    Output of ``yosys -m ./my_cmd.so -p 'test1; show'``
 
diff --git a/docs/source/yosys_internals/flow/control_and_data.rst b/docs/source/yosys_internals/flow/control_and_data.rst
index 5dcbe073025..70a84747f9e 100644
--- a/docs/source/yosys_internals/flow/control_and_data.rst
+++ b/docs/source/yosys_internals/flow/control_and_data.rst
@@ -10,7 +10,7 @@ and generating the data for the next subsystem (see :numref:`Fig. %s
 <fig:approach_flow>`).
 
 .. figure:: /_images/internals/approach_flow.*
-	:class: width-helper
+	:class: width-helper invert-helper
 	:name: fig:approach_flow
 
 	General data- and control-flow of a synthesis tool
diff --git a/docs/source/yosys_internals/flow/overview.rst b/docs/source/yosys_internals/flow/overview.rst
index f7589df031f..b357e5b50ea 100644
--- a/docs/source/yosys_internals/flow/overview.rst
+++ b/docs/source/yosys_internals/flow/overview.rst
@@ -42,7 +42,7 @@ possible it is key that (1) all passes operate on the same data structure
 design in different stages of the synthesis.
 
 .. figure:: /_images/internals/overview_flow.*
-	:class: width-helper
+	:class: width-helper invert-helper
 	:name: fig:Overview_flow
 
 	Yosys simplified data flow (ellipses: data structures, rectangles:
diff --git a/docs/source/yosys_internals/flow/verilog_frontend.rst b/docs/source/yosys_internals/flow/verilog_frontend.rst
index 127fa7be388..f2eaeae97b3 100644
--- a/docs/source/yosys_internals/flow/verilog_frontend.rst
+++ b/docs/source/yosys_internals/flow/verilog_frontend.rst
@@ -10,7 +10,7 @@ is then passed to the AST frontend that converts it to RTLIL data, as
 illustrated in :numref:`Fig. %s <fig:Verilog_flow>`.
 
 .. figure:: /_images/internals/verilog_flow.*
-	:class: width-helper
+	:class: width-helper invert-helper
 	:name: fig:Verilog_flow
 
 	Simplified Verilog to RTLIL data flow
diff --git a/docs/source/yosys_internals/formats/rtlil_rep.rst b/docs/source/yosys_internals/formats/rtlil_rep.rst
index 5de3430f228..2737cd4bd46 100644
--- a/docs/source/yosys_internals/formats/rtlil_rep.rst
+++ b/docs/source/yosys_internals/formats/rtlil_rep.rst
@@ -24,7 +24,7 @@ create an additional ``RTLIL::Design`` object and call the Verilog frontend with
 this other object to parse the cell library.
 
 .. figure:: /_images/internals/overview_rtlil.*
-	:class: width-helper
+	:class: width-helper invert-helper
 	:name: fig:Overview_RTLIL
 
 	Simplified RTLIL Entity-Relationship Diagram
diff --git a/docs/source/yosys_internals/techmap.rst b/docs/source/yosys_internals/techmap.rst
index ab161ed92d3..00fce26bd4f 100644
--- a/docs/source/yosys_internals/techmap.rst
+++ b/docs/source/yosys_internals/techmap.rst
@@ -34,7 +34,7 @@ Mapping OR3X1
    :caption: :file:`red_or3x1_map.v`
 
 .. figure:: /_images/code_examples/techmap/red_or3x1.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/techmap/red_or3x1_test.ys
    :language: yoscrypt
@@ -61,7 +61,7 @@ Conditional techmap
 Example:
 
 .. figure:: /_images/code_examples/techmap/sym_mul.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/techmap/sym_mul_map.v
    :language: verilog
@@ -100,7 +100,7 @@ Scripting in map modules
 Example:
 
 .. figure:: /_images/code_examples/techmap/mymul.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/techmap/mymul_map.v
    :language: verilog
@@ -130,7 +130,7 @@ Handling constant inputs
 Example:
 
 .. figure:: /_images/code_examples/techmap/mulshift.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/techmap/mulshift_map.v
    :language: verilog
@@ -162,7 +162,7 @@ Handling shorted inputs
 Example:
 
 .. figure:: /_images/code_examples/techmap/addshift.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/techmap/addshift_map.v
    :language: verilog

From a8bad3060ca362c07e37734aac55d58fa5e64c9d Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Sat, 11 May 2024 10:51:08 +1200
Subject: [PATCH 100/499] test-build.yml: test-docs should not ignore docs
 changes

---
 .github/workflows/test-build.yml | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index 5966ec3afdf..1cc068c1e5d 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -16,12 +16,23 @@ jobs:
           cancel_others: 'true'
           # only run on push *or* pull_request, not both
           concurrent_skipping: 'same_content_newer'
+  pre_docs_job:
+    runs-on: ubuntu-latest
+    outputs:
+      should_skip: ${{ steps.skip_check.outputs.should_skip }}
+    steps:
+      - id: skip_check
+        uses: fkirc/skip-duplicate-actions@v5
+        with:
+          paths_ignore: '["**/README.md"]'
+          # cancel previous builds if a new commit is pushed
+          cancel_others: 'true'
+          # only run on push *or* pull_request, not both
+          concurrent_skipping: 'same_content_newer'
 
   build-yosys:
     name: Reusable build
     runs-on: ${{ matrix.os }}
-    needs: pre_job
-    if: needs.pre_job.outputs.should_skip != 'true'
     env:
       CC: clang
     strategy:
@@ -137,8 +148,8 @@ jobs:
   test-docs:
     name: Run docs tests
     runs-on: ${{ matrix.os }}
-    needs: [build-yosys, pre_job]
-    if: needs.pre_job.outputs.should_skip != 'true'
+    needs: [build-yosys, pre_docs_job]
+    if: needs.pre_docs_job.outputs.should_skip != 'true'
     env:
       CC: clang
     strategy:

From 95bd7c9b0803f072f2e1b4780b8b7fdbce5042ea Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Sat, 11 May 2024 11:00:58 +1200
Subject: [PATCH 101/499] test-build.yml Use pre_docs_job for build-yosys

pre_job will never skip something that is not skipped by pre_docs_job, so we can gate the build step by pre_docs_job to skip it when the two later jobs are both being skipped.
---
 .github/workflows/test-build.yml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index 1cc068c1e5d..20a00639533 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -33,6 +33,8 @@ jobs:
   build-yosys:
     name: Reusable build
     runs-on: ${{ matrix.os }}
+    needs: pre_docs_job
+    if: needs.pre_docs_job.outputs.should_skip != 'true'
     env:
       CC: clang
     strategy:

From 26b148f455fab2c820402c5f011fb2dab7587091 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Sat, 11 May 2024 11:28:16 +1200
Subject: [PATCH 102/499] test-build.yml: Remove duplicated yosys-config

---
 .github/workflows/test-build.yml | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index 20a00639533..bf95688a15c 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -62,10 +62,6 @@ jobs:
         run: |
           ./yosys-config || true
 
-      - name: Log yosys-config output
-        run: |
-          ./yosys-config || true
-
       - name: Compress build
         shell: bash
         run: |

From 07ac4c2faecb9e72b53988f4a3b87642dfaa0465 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Sat, 11 May 2024 00:16:25 +0000
Subject: [PATCH 103/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 120214ced04..b6e0e91e4dd 100644
--- a/Makefile
+++ b/Makefile
@@ -141,7 +141,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.41+24
+YOSYS_VER := 0.41+69
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 1f9f2518fc51246a1e91975f927b50d171b2c801 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Sat, 11 May 2024 00:42:53 +0200
Subject: [PATCH 104/499] nix: fix abc

---
 flake.nix | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/flake.nix b/flake.nix
index d97be4ef671..26c21cc8996 100644
--- a/flake.nix
+++ b/flake.nix
@@ -12,19 +12,23 @@
         pkgs = import nixpkgs {
           inherit system;
         };
+        # TODO: don't override src when ./abc is empty
+        # which happens when the command used is `nix build` and not `nix build ?submodules=1`
+        abc-verifier = pkgs.abc-verifier.overrideAttrs(x: y: {src = ./abc;});
         customYosys = pkgs.clangStdenv.mkDerivation {
           name = "yosys";
           src = ./. ;
           buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git pkg-configUpstream ];
           checkInputs = with pkgs; [ gtest ];
-          propagatedBuildInputs = with pkgs; [ abc-verifier ];
+          propagatedBuildInputs = [ abc-verifier ];
           preConfigure = "make config-clang";
           checkTarget = "test";
           installPhase = ''
-            make install PREFIX=$out
+            make install PREFIX=$out ABCEXTERNAL=yosys-abc
+            ln -s ${abc-verifier}/bin/abc $out/bin/yosys-abc
           '';
 					buildPhase = ''
-          make -j$(nproc)
+            make -j$(nproc) ABCEXTERNAL=yosys-abc
           '';
           meta = with pkgs.lib; {
             description = "Yosys Open SYnthesis Suite";

From c40d43e3a9f7ac5ca01c26f0471245d69e6028ce Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Mon, 13 May 2024 13:45:06 +0200
Subject: [PATCH 105/499] Ignore result dir, generated by nix

---
 .gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.gitignore b/.gitignore
index 6f3e521d62e..e82343e8947 100644
--- a/.gitignore
+++ b/.gitignore
@@ -45,3 +45,4 @@ __pycache__
 /tests/unit/bintest/
 /tests/unit/objtest/
 /tests/ystests
+/result
\ No newline at end of file

From 8c8fb1399cb45058803a72bdf8e7219b9e3891fb Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Mon, 13 May 2024 13:53:53 +0200
Subject: [PATCH 106/499] Update github action

---
 .github/workflows/nix-github-actions.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/nix-github-actions.yml b/.github/workflows/nix-github-actions.yml
index a11584bc641..256f2043eae 100644
--- a/.github/workflows/nix-github-actions.yml
+++ b/.github/workflows/nix-github-actions.yml
@@ -9,5 +9,5 @@ jobs:
     - uses: actions/checkout@v4
       with:
        submodules: true
-    - uses: cachix/install-nix-action@v25
+    - uses: cachix/install-nix-action@v26
     - run: nix build '.?submodules=1'

From dd6178c74b5b7928f43037808ae60c6fce7e09fe Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Mon, 13 May 2024 14:21:35 +0200
Subject: [PATCH 107/499] Fix nix version to 2.18.1, known working version

---
 .github/workflows/nix-github-actions.yml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/nix-github-actions.yml b/.github/workflows/nix-github-actions.yml
index 256f2043eae..6d5c5b4b2dd 100644
--- a/.github/workflows/nix-github-actions.yml
+++ b/.github/workflows/nix-github-actions.yml
@@ -10,4 +10,6 @@ jobs:
       with:
        submodules: true
     - uses: cachix/install-nix-action@v26
-    - run: nix build '.?submodules=1'
+      with:
+       install_url: https://releases.nixos.org/nix/nix-2.18.1/install
+    - run: nix build .?submodules=1

From 9884bb57a10dd32e9ed73ecae91266c394567c1f Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Mon, 13 May 2024 14:28:32 +0200
Subject: [PATCH 108/499] Add update flake lock github action

---
 .github/workflows/update-flake-lock.yml | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 .github/workflows/update-flake-lock.yml

diff --git a/.github/workflows/update-flake-lock.yml b/.github/workflows/update-flake-lock.yml
new file mode 100644
index 00000000000..1d4741c8c22
--- /dev/null
+++ b/.github/workflows/update-flake-lock.yml
@@ -0,0 +1,21 @@
+name: update-flake-lock
+on:
+  workflow_dispatch: # allows manual triggering
+  schedule:
+    - cron: '0 0 * * 0' # runs weekly on Sunday at 00:00
+
+jobs:
+  lockfile:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout repository
+        uses: actions/checkout@v4
+      - name: Install Nix
+        uses: DeterminateSystems/nix-installer-action@main
+      - name: Update flake.lock
+        uses: DeterminateSystems/update-flake-lock@main
+        with:
+          pr-title: "Update flake.lock" # Title of PR to be created
+          pr-labels: |                  # Labels to be set on the PR
+            dependencies
+            automated
\ No newline at end of file

From fa19abad98c7d57dc958141ff2997eca41fd5746 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 13 May 2024 16:44:42 +0200
Subject: [PATCH 109/499] Fix rst syntax error

---
 docs/source/yosys_internals/formats/cell_library.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/source/yosys_internals/formats/cell_library.rst b/docs/source/yosys_internals/formats/cell_library.rst
index 69e82774c1f..70c36e6e747 100644
--- a/docs/source/yosys_internals/formats/cell_library.rst
+++ b/docs/source/yosys_internals/formats/cell_library.rst
@@ -688,6 +688,7 @@ Let ``\WIDTH`` be 3. We would like to represent ``\Y =~\A[0] + \A[1]~\A[2]``.
 There are 2 products to be summed, so ``\DEPTH`` shall be 2.
 
 .. code-block::
+
 	~A[2]-----┐
 	 A[2]----┐|
 	~A[1]---┐||

From 229300bb4a244fccb110d467045d830af83aec86 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 13 May 2024 17:37:24 +0200
Subject: [PATCH 110/499] replace unicode chars in rst to make pdf work

---
 .../yosys_internals/formats/cell_library.rst    | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/docs/source/yosys_internals/formats/cell_library.rst b/docs/source/yosys_internals/formats/cell_library.rst
index 70c36e6e747..7a19255a3d0 100644
--- a/docs/source/yosys_internals/formats/cell_library.rst
+++ b/docs/source/yosys_internals/formats/cell_library.rst
@@ -689,14 +689,15 @@ There are 2 products to be summed, so ``\DEPTH`` shall be 2.
 
 .. code-block::
 
-	~A[2]-----┐
-	 A[2]----┐|
-	~A[1]---┐||
-	 A[1]--┐|||
-	~A[0]-┐||||
-	 A[0]┐||||| product formula
-	     010000 ~\A[0]
-	     001001 \A[1]~\A[2]
+    ~A[2]-----+
+     A[2]----+|
+    ~A[1]---+||
+     A[1]--+|||
+    ~A[0]-+||||
+     A[0]+||||| 
+         |||||| product formula
+         010000 ~\A[0]
+         001001 \A[1]~\A[2]
 
 So the value of ``\TABLE`` will become ``010000001001``.
 

From 7045cf509e1d95cbc973746674cf2d7c73c02e50 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Tue, 14 May 2024 00:16:31 +0000
Subject: [PATCH 111/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index b6e0e91e4dd..9e3fd1a20ff 100644
--- a/Makefile
+++ b/Makefile
@@ -141,7 +141,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.41+69
+YOSYS_VER := 0.41+83
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 13a6920491a01b492e35c8981a856b14ca83f3e7 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Tue, 21 May 2024 12:50:23 +0200
Subject: [PATCH 112/499] Change customYosys to yosys

---
 flake.nix | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/flake.nix b/flake.nix
index 26c21cc8996..1e202324647 100644
--- a/flake.nix
+++ b/flake.nix
@@ -15,7 +15,7 @@
         # TODO: don't override src when ./abc is empty
         # which happens when the command used is `nix build` and not `nix build ?submodules=1`
         abc-verifier = pkgs.abc-verifier.overrideAttrs(x: y: {src = ./abc;});
-        customYosys = pkgs.clangStdenv.mkDerivation {
+        yosys = pkgs.clangStdenv.mkDerivation {
           name = "yosys";
           src = ./. ;
           buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git pkg-configUpstream ];
@@ -38,8 +38,8 @@
           };
         };
       in {
-        packages.default = customYosys;
-        defaultPackage = customYosys;
+        packages.default = yosys;
+        defaultPackage = yosys;
         devShell = pkgs.mkShell {
           buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier ];
         };

From 88af059fad92631537c94b319ed2123224798351 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Tue, 21 May 2024 14:56:15 +0200
Subject: [PATCH 113/499] bbox_derive: Fix `done` base type confusion

---
 passes/cmds/bbox_derive.cc | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/passes/cmds/bbox_derive.cc b/passes/cmds/bbox_derive.cc
index a35e9629058..e4fcb79637b 100644
--- a/passes/cmds/bbox_derive.cc
+++ b/passes/cmds/bbox_derive.cc
@@ -54,7 +54,7 @@ struct BboxDerivePass : Pass {
 				log_cmd_error("Base module %s not found.\n", log_id(base_name));
 		}
 
-		dict<dict<RTLIL::IdString, RTLIL::Const>, Module*> done;
+		dict<std::pair<RTLIL::IdString, dict<RTLIL::IdString, RTLIL::Const>>, Module*> done;
 
 		for (auto module : d->selected_modules()) {
 			for (auto cell : module->selected_cells()) {
@@ -62,13 +62,15 @@ struct BboxDerivePass : Pass {
 				if (!inst_module || !inst_module->get_blackbox_attribute())
 					continue;
 
-				if (cell->parameters.empty() || done.count(cell->parameters))
-					continue;
-
 				Module *base = inst_module;
 				if (base_override)
 					base = base_override;
 
+				auto index = std::make_pair(base->name, cell->parameters);
+
+				if (cell->parameters.empty() || done.count(index))
+					continue;
+
 				IdString derived_type = base->derive(d, cell->parameters);
 				Module *derived = d->module(derived_type);
 				log_assert(derived && "Failed to derive module\n");
@@ -83,7 +85,7 @@ struct BboxDerivePass : Pass {
 					d->rename(derived, new_name);
 				}
 
-				done[cell->parameters] = derived;
+				done[index] = derived;
 			}
 		}
 	}

From 5c929a91c26920b50d4887e0058c895d1a91b280 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Tue, 21 May 2024 14:57:37 +0200
Subject: [PATCH 114/499] bbox_derive: Write help

---
 passes/cmds/bbox_derive.cc | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/passes/cmds/bbox_derive.cc b/passes/cmds/bbox_derive.cc
index e4fcb79637b..90ce2ac4908 100644
--- a/passes/cmds/bbox_derive.cc
+++ b/passes/cmds/bbox_derive.cc
@@ -29,6 +29,28 @@ struct BboxDerivePass : Pass {
 		log("\n");
 		log("    bbox_derive [-base <base_module>] [-naming_attr <attr>] [selection]\n");
 		log("\n");
+		log("As part of the assembly of the design hierarchy done by the 'hierarchy' command,\n");
+		log("specializations of parametric modules are derived on demand: for each choice of\n");
+		log("parameter values appearing in the design, a copy of the parametric module is\n");
+		log("derived which is specialized to that choice.\n");
+		log("\n");
+		log("This derivation process ignores blackboxes and whiteboxes. To supplement, this\n");
+		log("'bbox_derive' command can be used to request the derivation of modules based on\n");
+		log("blackbox or whitebox instances appearing in the design, which is desirable in\n");
+		log("certain use cases. Only the selected cells are considered as the instances that\n");
+		log("steer the derivation process.\n");
+		log("\n");
+		log("    -base <base_module>\n");
+		log("        instead of deriving the module that directly corresponds to each blackbox\n");
+		log("        instance, derive a specialization of <base_module> (this option applies\n");
+		log("        to all selected blackbox cells)\n");
+		log("\n");
+		log("    -naming_attr <attr>\n");
+		log("        once a specialization is derived, use the value of the module attribute\n");
+		log("        <attr> for a name which should be used for the derived module (this\n");
+		log("        replaces the internal Yosys naming scheme in which the names of derived\n");
+		log("        modules start with '$paramod$')\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *d) override
 	{

From 557db4ea46517658431f4674de41b887413307eb Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Tue, 21 May 2024 14:57:49 +0200
Subject: [PATCH 115/499] bbox_drive: Add an incomplete test

---
 tests/various/bbox_derive.ys | 37 ++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100644 tests/various/bbox_derive.ys

diff --git a/tests/various/bbox_derive.ys b/tests/various/bbox_derive.ys
new file mode 100644
index 00000000000..26312fb53cf
--- /dev/null
+++ b/tests/various/bbox_derive.ys
@@ -0,0 +1,37 @@
+read_verilog <<EOF
+(* whitebox *)
+(* final_name=$sformatf("aa%d", X) *)
+module aa(input wire d, output wire q);
+  parameter [1:0] X = 0;
+  assign q = X[d];
+endmodule
+
+(* whitebox *)
+(* final_name=$sformatf("bb%d", X) *)
+module bb(input wire d, output wire q);
+  parameter [1:0] X = 0;
+  assign q = X[~d];
+endmodule
+
+(* whitebox *)
+(* final_name=$sformatf("cc%d", X) *)
+module cc(input wire d, output wire q);
+  parameter [1:0] X = 0;
+  assign q = ~X[d];
+endmodule
+
+module top;
+	wire d, q1, q2, q3, q3, q4, q5, q6;
+
+	aa #(.X(1)) aa1(.d(d), .q(q1));
+	aa #(.X(2)) aa2(.d(d), .q(q2));
+
+	bb #(.X(1)) bb1(.d(d), .q(q3));
+	bb #(.X(3)) bb2(.d(d), .q(q4));
+
+	cc #(.X(1)) cc1(.d(d), .q(q5));
+	cc #(.X(1)) cc2(.d(d), .q(q6));
+endmodule
+EOF
+
+bbox_derive -naming_attr final_name top

From c0a196173aa92808b567df8bb0d3ce53f0471002 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Tue, 21 May 2024 16:14:34 +0200
Subject: [PATCH 116/499] Rename `bbox_derive` to `box_derive`

---
 passes/cmds/Makefile.inc                      |  2 +-
 passes/cmds/{bbox_derive.cc => box_derive.cc} | 24 +++++++++----------
 .../various/{bbox_derive.ys => box_derive.ys} |  2 +-
 3 files changed, 14 insertions(+), 14 deletions(-)
 rename passes/cmds/{bbox_derive.cc => box_derive.cc} (84%)
 rename tests/various/{bbox_derive.ys => box_derive.ys} (94%)

diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index b1c9c67f0d0..33e3ae1bc5a 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -48,4 +48,4 @@ OBJS += passes/cmds/clean_zerowidth.o
 OBJS += passes/cmds/xprop.o
 OBJS += passes/cmds/dft_tag.o
 OBJS += passes/cmds/future.o
-OBJS += passes/cmds/bbox_derive.o
+OBJS += passes/cmds/box_derive.o
diff --git a/passes/cmds/bbox_derive.cc b/passes/cmds/box_derive.cc
similarity index 84%
rename from passes/cmds/bbox_derive.cc
rename to passes/cmds/box_derive.cc
index 90ce2ac4908..da698b04d37 100644
--- a/passes/cmds/bbox_derive.cc
+++ b/passes/cmds/box_derive.cc
@@ -21,29 +21,29 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-struct BboxDerivePass : Pass {
-	BboxDerivePass() : Pass("bbox_derive", "derive blackbox modules") {}
+struct BoxDerivePass : Pass {
+	BoxDerivePass() : Pass("box_derive", "derive box modules") {}
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    bbox_derive [-base <base_module>] [-naming_attr <attr>] [selection]\n");
+		log("    box_derive [-base <base_module>] [-naming_attr <attr>] [selection]\n");
 		log("\n");
 		log("As part of the assembly of the design hierarchy done by the 'hierarchy' command,\n");
 		log("specializations of parametric modules are derived on demand: for each choice of\n");
 		log("parameter values appearing in the design, a copy of the parametric module is\n");
 		log("derived which is specialized to that choice.\n");
 		log("\n");
-		log("This derivation process ignores blackboxes and whiteboxes. To supplement, this\n");
-		log("'bbox_derive' command can be used to request the derivation of modules based on\n");
-		log("blackbox or whitebox instances appearing in the design, which is desirable in\n");
-		log("certain use cases. Only the selected cells are considered as the instances that\n");
-		log("steer the derivation process.\n");
+		log("This derivation process ignores blackboxes and whiteboxes (boxes). To supplement,\n");
+		log("this 'box_derive' command can be used to request the derivation of modules based\n");
+		log("on box instances appearing in the design, which is desirable in certain use\n");
+		log("cases. Only the selected cells are considered as the instances that steer the\n");
+		log("derivation process.\n");
 		log("\n");
 		log("    -base <base_module>\n");
-		log("        instead of deriving the module that directly corresponds to each blackbox\n");
+		log("        instead of deriving the module that directly corresponds to each box\n");
 		log("        instance, derive a specialization of <base_module> (this option applies\n");
-		log("        to all selected blackbox cells)\n");
+		log("        to all selected box cells)\n");
 		log("\n");
 		log("    -naming_attr <attr>\n");
 		log("        once a specialization is derived, use the value of the module attribute\n");
@@ -54,7 +54,7 @@ struct BboxDerivePass : Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *d) override
 	{
-		log_header(d, "Executing BBOX_DERIVE pass. (derive modules for blackboxes)\n");
+		log_header(d, "Executing BOX_DERIVE pass. (derive modules for boxes)\n");
 
 		size_t argidx;
 		IdString naming_attr;
@@ -111,6 +111,6 @@ struct BboxDerivePass : Pass {
 			}
 		}
 	}
-} BboxDerivePass;
+} BoxDerivePass;
 
 PRIVATE_NAMESPACE_END
diff --git a/tests/various/bbox_derive.ys b/tests/various/box_derive.ys
similarity index 94%
rename from tests/various/bbox_derive.ys
rename to tests/various/box_derive.ys
index 26312fb53cf..a76a79cdc1f 100644
--- a/tests/various/bbox_derive.ys
+++ b/tests/various/box_derive.ys
@@ -34,4 +34,4 @@ module top;
 endmodule
 EOF
 
-bbox_derive -naming_attr final_name top
+box_derive -naming_attr final_name top

From adc1a01490850f294bb6229029799e91e3360d41 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Tue, 21 May 2024 16:28:40 +0200
Subject: [PATCH 117/499] select: Refactor some flag validation

---
 passes/cmds/select.cc | 19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 03d00816e1b..2b68a921d09 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -1385,17 +1385,20 @@ struct SelectPass : public Pass {
 		if (none_mode && args.size() != 2)
 			log_cmd_error("Option -none can not be combined with any other options.\n");
 
-		if (add_mode + del_mode + assert_none + assert_any + (assert_count >= 0) + (assert_max >= 0) + (assert_min >= 0) > 1)
-			log_cmd_error("Options -add, -del, -assert-none, -assert-any, assert-count, -assert-max or -assert-min can not be combined.\n");
+		int common_flagset_tally = add_mode + del_mode + assert_none + assert_any + (assert_count >= 0) + (assert_max >= 0) + (assert_min >= 0);
+		const char *common_flagset = "-add, -del, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min";
 
-		if ((list_mode || !write_file.empty() || count_mode) && (add_mode || del_mode || assert_none || assert_any || assert_count >= 0 || assert_max >= 0 || assert_min >= 0))
-			log_cmd_error("Options -list, -write and -count can not be combined with -add, -del, -assert-none, -assert-any, assert-count, -assert-max, or -assert-min.\n");
+		if (common_flagset_tally > 1)
+			log_cmd_error("Options %s can not be combined.\n", common_flagset);                
 
-		if (!set_name.empty() && (list_mode || !write_file.empty() || count_mode || add_mode || !unset_name.empty() || del_mode || assert_none || assert_any || assert_count >= 0 || assert_max >= 0 || assert_min >= 0))
-			log_cmd_error("Option -set can not be combined with -list, -write, -count, -add, -del, -unset, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min.\n");
+		if ((list_mode || !write_file.empty() || count_mode) && common_flagset_tally)
+			log_cmd_error("Options -list, -write and -count can not be combined with %s.\n", common_flagset);
 
-		if (!unset_name.empty() && (list_mode || !write_file.empty() || count_mode || add_mode || !set_name.empty() || del_mode || assert_none || assert_any || assert_count >= 0 || assert_max >= 0 || assert_min >= 0))
-			log_cmd_error("Option -unset can not be combined with -list, -write, -count, -add, -del, -set, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min.\n");
+		if (!set_name.empty() && (list_mode || !write_file.empty() || count_mode || !unset_name.empty() || common_flagset_tally))
+			log_cmd_error("Option -set can not be combined with -list, -write, -count, -unset, %s.\n", common_flagset);
+
+		if (!unset_name.empty() && (list_mode || !write_file.empty() || count_mode || !set_name.empty() || common_flagset_tally))
+			log_cmd_error("Option -unset can not be combined with -list, -write, -count, -set, %s.\n", common_flagset);
 
 		if (work_stack.size() == 0 && got_module) {
 			RTLIL::Selection sel;

From 49906be776552b62ff2c8c954bd0c80fa215e0f6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Tue, 21 May 2024 16:34:38 +0200
Subject: [PATCH 118/499] select: Introduce `-assert-mod-count`

---
 passes/cmds/select.cc | 26 +++++++++++++++++++++-----
 1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 2b68a921d09..2b7a37013cd 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -1065,6 +1065,10 @@ struct SelectPass : public Pass {
 		log("        selection is non-empty. i.e. produce an error if no object or module\n");
 		log("        matching the selection is found.\n");
 		log("\n");
+		log("    -assert-mod-count N\n");
+		log("        do not modify the current selection. instead assert that the given\n");
+		log("        selection contains exactly N modules.\n");
+		log("\n");
 		log("    -assert-count N\n");
 		log("        do not modify the current selection. instead assert that the given\n");
 		log("        selection contains exactly N objects.\n");
@@ -1263,6 +1267,7 @@ struct SelectPass : public Pass {
 		bool got_module = false;
 		bool assert_none = false;
 		bool assert_any = false;
+		int assert_modcount = -1;
 		int assert_count = -1;
 		int assert_max = -1;
 		int assert_min = -1;
@@ -1291,6 +1296,10 @@ struct SelectPass : public Pass {
 				assert_any = true;
 				continue;
 			}
+			if (arg == "-assert-mod-count" && argidx+1 < args.size()) {
+				assert_modcount = atoi(args[++argidx].c_str());
+				continue;
+			}
 			if (arg == "-assert-count" && argidx+1 < args.size()) {
 				assert_count = atoi(args[++argidx].c_str());
 				continue;
@@ -1345,7 +1354,8 @@ struct SelectPass : public Pass {
 			}
 			if (arg.size() > 0 && arg[0] == '-')
 				log_cmd_error("Unknown option %s.\n", arg.c_str());
-			bool disable_empty_warning = count_mode || assert_none || assert_any || (assert_count != -1) || (assert_max != -1) || (assert_min != -1);
+			bool disable_empty_warning = count_mode || assert_none || assert_any || (assert_modcount != -1) ||
+											(assert_count != -1) || (assert_max != -1) || (assert_min != -1);
 			select_stmt(design, arg, disable_empty_warning);
 			sel_str += " " + arg;
 		}
@@ -1385,8 +1395,8 @@ struct SelectPass : public Pass {
 		if (none_mode && args.size() != 2)
 			log_cmd_error("Option -none can not be combined with any other options.\n");
 
-		int common_flagset_tally = add_mode + del_mode + assert_none + assert_any + (assert_count >= 0) + (assert_max >= 0) + (assert_min >= 0);
-		const char *common_flagset = "-add, -del, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min";
+		int common_flagset_tally = add_mode + del_mode + assert_none + assert_any + (assert_modcount >= 0) + (assert_count >= 0) + (assert_max >= 0) + (assert_min >= 0);
+		const char *common_flagset = "-add, -del, -assert-none, -assert-any, -assert-mod-count, -assert-count, -assert-max, or -assert-min";
 
 		if (common_flagset_tally > 1)
 			log_cmd_error("Options %s can not be combined.\n", common_flagset);                
@@ -1517,15 +1527,16 @@ struct SelectPass : public Pass {
 			return;
 		}
 
-		if (assert_count >= 0 || assert_max >= 0 || assert_min >= 0)
+		if (assert_modcount >= 0 || assert_count >= 0 || assert_max >= 0 || assert_min >= 0)
 		{
-			int total_count = 0;
+			int module_count = 0, total_count = 0;
 			if (work_stack.size() == 0)
 				log_cmd_error("No selection to check.\n");
 			RTLIL::Selection *sel = &work_stack.back();
 			sel->optimize(design);
 			for (auto mod : design->modules())
 				if (sel->selected_module(mod->name)) {
+					module_count++;
 					for (auto wire : mod->wires())
 						if (sel->selected_member(mod->name, wire->name))
 							total_count++;
@@ -1539,6 +1550,11 @@ struct SelectPass : public Pass {
 						if (sel->selected_member(mod->name, it.first))
 							total_count++;
 				}
+			if (assert_modcount >= 0 && assert_modcount != module_count)
+			{
+				log_error("Assertion failed: selection contains %d modules instead of the asserted %d:%s\n",
+						module_count, assert_modcount, sel_str.c_str());
+			}
 			if (assert_count >= 0 && assert_count != total_count)
 			{
 				std::string desc = describe_selection_for_assert(design, sel);

From bff2443af842e41134bbd348dbd6885ab8206e4d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Tue, 21 May 2024 16:34:49 +0200
Subject: [PATCH 119/499] box_derive: Finish the test

---
 tests/various/box_derive.ys | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/tests/various/box_derive.ys b/tests/various/box_derive.ys
index a76a79cdc1f..72db48e4fed 100644
--- a/tests/various/box_derive.ys
+++ b/tests/various/box_derive.ys
@@ -35,3 +35,13 @@ endmodule
 EOF
 
 box_derive -naming_attr final_name top
+select -assert-mod-count 1 =bb1
+select -assert-mod-count 0 =bb2
+select -assert-mod-count 1 =bb3
+
+select -assert-mod-count 1 =cc1
+select -assert-mod-count 0 =cc2
+select -assert-mod-count 0 =cc3
+
+# the original aa, bb, cc, and 5 specializations
+select -assert-mod-count 8 =A:whitebox

From c71262f66b7f428289f6ef0980bb4fc5b9173693 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Wed, 22 May 2024 00:16:29 +0000
Subject: [PATCH 120/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 93f09dee49e..cbf834007fc 100644
--- a/Makefile
+++ b/Makefile
@@ -141,7 +141,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.41+83
+YOSYS_VER := 0.41+101
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From db3f8103044131c0603ec0c05c74dd6f0b06e31b Mon Sep 17 00:00:00 2001
From: Mary Guillemard <mary@mary.zone>
Date: Wed, 22 May 2024 23:40:02 +0200
Subject: [PATCH 121/499] Only build yosys-abc usage docs when ABCEXTERNAL is
 not set

Since 0.41, when building docs with ABCEXTERNAL set, the rule for
yosys-abc docs usage would attempt to build in-tree ABC.

This fix this regression by only including yosys-abc in
DOCS_USAGE_STDERR when ABCEXTERNAL is not set.

Signed-off-by: Mary Guillemard <mary@mary.zone>
---
 Makefile | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index cbf834007fc..55866259c0f 100644
--- a/Makefile
+++ b/Makefile
@@ -946,7 +946,13 @@ define DOC_USAGE_STDERR
 docs/source/generated/$(1): $(PROGRAM_PREFIX)$(1) docs/source/generated
 	-$(Q) ./$$< --help 2> $$@
 endef
-DOCS_USAGE_STDERR := yosys-config yosys-filterlib yosys-abc
+DOCS_USAGE_STDERR := yosys-config yosys-filterlib
+
+# The in-tree ABC (yosys-abc) is only built when ABCEXTERNAL is not set.
+ifeq ($(ABCEXTERNAL),)
+DOCS_USAGE_STDERR += yosys-abc
+endif
+
 $(foreach usage,$(DOCS_USAGE_STDERR),$(eval $(call DOC_USAGE_STDERR,$(usage))))
 
 # others print to stdout

From 1aae0bcd40accc760e30d5c1bab09c1303bca2bf Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 24 May 2024 09:09:48 +1200
Subject: [PATCH 122/499] ci: Move nix build to extra-builds.yml

Skip duplicate actions on nix build.
---
 .github/workflows/extra-builds.yml       | 14 ++++++++++++++
 .github/workflows/nix-github-actions.yml | 15 ---------------
 2 files changed, 14 insertions(+), 15 deletions(-)
 delete mode 100644 .github/workflows/nix-github-actions.yml

diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml
index 260394a3ffe..031f696537a 100644
--- a/.github/workflows/extra-builds.yml
+++ b/.github/workflows/extra-builds.yml
@@ -81,3 +81,17 @@ jobs:
           END
 
           make -C build -f ../Makefile CXX=clang -j$(nproc)
+
+  nix-build:
+    name: "Build nix flake"
+    needs: pre_job
+    if: needs.pre_job.outputs.should_skip != 'true'
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4
+        with:
+        submodules: true
+      - uses: cachix/install-nix-action@v26
+        with:
+        install_url: https://releases.nixos.org/nix/nix-2.18.1/install
+      - run: nix build .?submodules=1
diff --git a/.github/workflows/nix-github-actions.yml b/.github/workflows/nix-github-actions.yml
deleted file mode 100644
index 6d5c5b4b2dd..00000000000
--- a/.github/workflows/nix-github-actions.yml
+++ /dev/null
@@ -1,15 +0,0 @@
-name: "build nix flake"
-on:
-  pull_request:
-  push:
-jobs:
-  tests:
-    runs-on: ubuntu-latest
-    steps:
-    - uses: actions/checkout@v4
-      with:
-       submodules: true
-    - uses: cachix/install-nix-action@v26
-      with:
-       install_url: https://releases.nixos.org/nix/nix-2.18.1/install
-    - run: nix build .?submodules=1

From d135c0bf87b0054cffd77ff6dbc030b194d5ef12 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 24 May 2024 09:41:31 +1200
Subject: [PATCH 123/499] extra-builds.yml: Fix indentation

---
 .github/workflows/extra-builds.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml
index 031f696537a..d7c6e13ff06 100644
--- a/.github/workflows/extra-builds.yml
+++ b/.github/workflows/extra-builds.yml
@@ -90,8 +90,8 @@ jobs:
     steps:
       - uses: actions/checkout@v4
         with:
-        submodules: true
+          submodules: true
       - uses: cachix/install-nix-action@v26
         with:
-        install_url: https://releases.nixos.org/nix/nix-2.18.1/install
+          install_url: https://releases.nixos.org/nix/nix-2.18.1/install
       - run: nix build .?submodules=1

From c7580eb18ed2a8ba313b5120dfc1dba36cef485e Mon Sep 17 00:00:00 2001
From: Amiot Noe <noe.amiot@lip6.fr>
Date: Tue, 21 May 2024 21:47:00 +0200
Subject: [PATCH 124/499] cxxrtl: Prevent wires with input or output ports from
 being aliased

---
 backends/cxxrtl/cxxrtl_backend.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index 703494682a8..9ddbd33b0a3 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -3263,6 +3263,7 @@ struct CxxrtlWorker {
 						debug_wire_type = wire_type; // wire is a member
 
 					if (!debug_alias) continue;
+					if (wire->port_input || wire->port_output) continue; // preserve input/output metadata in flags
 					const RTLIL::Wire *it = wire;
 					while (flow.is_inlinable(it)) {
 						log_assert(flow.wire_comb_defs[it].size() == 1);

From 557968567360026ae8dc75341564209868171296 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Sat, 25 May 2024 00:16:20 +0000
Subject: [PATCH 125/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 55866259c0f..15ab4766c48 100644
--- a/Makefile
+++ b/Makefile
@@ -141,7 +141,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.41+101
+YOSYS_VER := 0.41+108
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 02ad56a132d1faf24ff7efb2178c6bc8c034a9dc Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 27 May 2024 22:39:42 +0200
Subject: [PATCH 126/499] docs: add todo for $demux

---
 docs/source/yosys_internals/formats/cell_library.rst | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/docs/source/yosys_internals/formats/cell_library.rst b/docs/source/yosys_internals/formats/cell_library.rst
index 2b8dc300154..ad2dd93712a 100644
--- a/docs/source/yosys_internals/formats/cell_library.rst
+++ b/docs/source/yosys_internals/formats/cell_library.rst
@@ -1195,3 +1195,5 @@ file via ABC using the abc pass.
 .. todo:: Add information about ``$lut`` and ``$sop`` cells.
 
 .. todo:: Add information about ``$alu``, ``$fa``, and ``$lcu`` cells.
+
+.. todo:: Add information about ``$demux`` cell.
\ No newline at end of file

From b230c95cc4ad14b7024db47f18169045b13230ae Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Wed, 29 May 2024 20:41:56 +0200
Subject: [PATCH 127/499] select: Adjust help

---
 passes/cmds/select.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 2b7a37013cd..e455baf7c7f 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -1067,7 +1067,7 @@ struct SelectPass : public Pass {
 		log("\n");
 		log("    -assert-mod-count N\n");
 		log("        do not modify the current selection. instead assert that the given\n");
-		log("        selection contains exactly N modules.\n");
+		log("        selection contains exactly N modules (partially or fully selected).\n");
 		log("\n");
 		log("    -assert-count N\n");
 		log("        do not modify the current selection. instead assert that the given\n");

From 97fedff383bb253eca5ab9d6827057e1fae9dd1f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Wed, 29 May 2024 20:42:11 +0200
Subject: [PATCH 128/499] box_derive: Tune the test

---
 tests/various/box_derive.ys | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/tests/various/box_derive.ys b/tests/various/box_derive.ys
index 72db48e4fed..f02e133603d 100644
--- a/tests/various/box_derive.ys
+++ b/tests/various/box_derive.ys
@@ -35,6 +35,11 @@ endmodule
 EOF
 
 box_derive -naming_attr final_name top
+
+select -assert-mod-count 1 =aa1
+select -assert-mod-count 1 =aa2
+select -assert-mod-count 0 =aa3
+
 select -assert-mod-count 1 =bb1
 select -assert-mod-count 0 =bb2
 select -assert-mod-count 1 =bb3
@@ -43,5 +48,6 @@ select -assert-mod-count 1 =cc1
 select -assert-mod-count 0 =cc2
 select -assert-mod-count 0 =cc3
 
-# the original aa, bb, cc, and 5 specializations
+# we are expecting the original aa, bb, cc modules
+# and 5 specializations generated by box_derive
 select -assert-mod-count 8 =A:whitebox

From a84e4f44fe5fdd234f80c4b55803f27ec8eb03d6 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Fri, 31 May 2024 00:16:34 +0000
Subject: [PATCH 129/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 15ab4766c48..a15a3971065 100644
--- a/Makefile
+++ b/Makefile
@@ -141,7 +141,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.41+108
+YOSYS_VER := 0.41+111
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 803703a83328ef4535960212f6eb11ca77465f6a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Miodrag=20Milanovi=C4=87?= <mmicko@gmail.com>
Date: Sun, 2 Jun 2024 19:25:05 +0200
Subject: [PATCH 130/499] Update flake lock workflow

Update workflow so it creates trigger as user so  GitHub Action is triggering actual build
---
 .github/workflows/update-flake-lock.yml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/update-flake-lock.yml b/.github/workflows/update-flake-lock.yml
index 1d4741c8c22..c7aa6ecab70 100644
--- a/.github/workflows/update-flake-lock.yml
+++ b/.github/workflows/update-flake-lock.yml
@@ -15,7 +15,8 @@ jobs:
       - name: Update flake.lock
         uses: DeterminateSystems/update-flake-lock@main
         with:
+          token: ${{CI_CREATE_PR_TOKEN}}
           pr-title: "Update flake.lock" # Title of PR to be created
           pr-labels: |                  # Labels to be set on the PR
             dependencies
-            automated
\ No newline at end of file
+            automated

From 855ac285f49277ba9007f5808f5350ec656db852 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Mon, 3 Jun 2024 00:17:36 +0000
Subject: [PATCH 131/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index a15a3971065..9a263c2f2dc 100644
--- a/Makefile
+++ b/Makefile
@@ -141,7 +141,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.41+111
+YOSYS_VER := 0.41+126
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 094fa8cabaafd1cc0ed8e7d485e86cf1651078bf Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Thu, 6 Jun 2024 17:35:31 +0200
Subject: [PATCH 132/499] smtbmc: Fix two .yw handling related crashes

These came up when using the experimental incremental interface and are
also in code that was recently refactored to support that interface.
---
 backends/smt2/smtbmc.py | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/backends/smt2/smtbmc.py b/backends/smt2/smtbmc.py
index 995a714c926..c3bdcebbe96 100644
--- a/backends/smt2/smtbmc.py
+++ b/backends/smt2/smtbmc.py
@@ -719,6 +719,8 @@ def smt_extract_mask(smt_expr, mask):
     return combined_chunks, ''.join(mask_index_order[start:end] for start, end in chunks)[::-1]
 
 def smt_concat(exprs):
+    if not isinstance(exprs, (tuple, list)):
+        exprs = tuple(exprs)
     if not exprs:
         return ""
     if len(exprs) == 1:
@@ -818,6 +820,9 @@ def ywfile_constraints(inywfile, constr_assumes, map_steps=None, skip_x=False):
                 if not bits_re.match(bits):
                     raise ValueError("unsupported bit value in Yosys witness file")
 
+                if bits.count('?') == len(bits):
+                    continue
+
                 smt_expr = ywfile_signal(sig, map_steps.get(t, t))
 
                 smt_expr, bits = smt_extract_mask(smt_expr, bits)

From bd28d26021c4bd2c3bcc9d60b0e6e7e93fbebc86 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Fri, 7 Jun 2024 00:17:23 +0000
Subject: [PATCH 133/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 9a263c2f2dc..594e740a9b3 100644
--- a/Makefile
+++ b/Makefile
@@ -141,7 +141,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.41+126
+YOSYS_VER := 0.41+129
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 9b82a44d254d8db663e7b7b1b9db330faa2118fa Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 7 Jun 2024 08:26:59 +0200
Subject: [PATCH 134/499] Fix help message typo

---
 passes/cmds/logcmd.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/cmds/logcmd.cc b/passes/cmds/logcmd.cc
index 8e51af4b3b7..3b82ac48c0c 100644
--- a/passes/cmds/logcmd.cc
+++ b/passes/cmds/logcmd.cc
@@ -59,7 +59,7 @@ struct LogPass : public Pass {
 		log("    -push\n");
 		log("        push a new level on the pass counter\n");
 		log("\n");
-		log("    -push\n");
+		log("    -pop\n");
 		log("        pop from the pass counter\n");
 		log("\n");
 	}

From 9b6afcf3f83fea413b57c3790c25ba43b9914ce2 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 7 Jun 2024 08:29:48 +0200
Subject: [PATCH 135/499] Release version 0.42

---
 CHANGELOG           | 8 +++++++-
 Makefile            | 4 ++--
 docs/source/conf.py | 2 +-
 3 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index 7c3ad481e9e..0f80a9f5e0e 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,8 +2,14 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.41 .. Yosys 0.42-dev
+Yosys 0.41 .. Yosys 0.42
 --------------------------
+ * New commands and options
+    - Added "box_derive" pass to derive box modules.
+    - Added option "assert-mod-count" to "select" pass. 
+    - Added option "-header","-push" and "-pop" to "log" pass. 
+ * Intel support
+    - Dropped Quartus support in "synth_intel_alm" pass.
 
 Yosys 0.40 .. Yosys 0.41
 --------------------------
diff --git a/Makefile b/Makefile
index 594e740a9b3..7bfd6010cc6 100644
--- a/Makefile
+++ b/Makefile
@@ -141,7 +141,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.41+129
+YOSYS_VER := 0.42
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -157,7 +157,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline c1ad377.. | wc -l`/;" Makefile
+#	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline c1ad377.. | wc -l`/;" Makefile
 
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
 
diff --git a/docs/source/conf.py b/docs/source/conf.py
index fcd6adce863..c9c923e8231 100644
--- a/docs/source/conf.py
+++ b/docs/source/conf.py
@@ -5,7 +5,7 @@
 project = 'YosysHQ Yosys'
 author = 'YosysHQ GmbH'
 copyright ='2024 YosysHQ GmbH'
-yosys_ver = "0.41"
+yosys_ver = "0.42"
 
 # select HTML theme
 html_theme = 'furo'

From b056e8c0ba2b6f7c94d9102a42a03feb66e8d452 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 7 Jun 2024 08:34:06 +0200
Subject: [PATCH 136/499] Next dev cycle

---
 CHANGELOG | 3 +++
 Makefile  | 4 ++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index 0f80a9f5e0e..d8e13b041e5 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 List of major changes and improvements between releases
 =======================================================
 
+Yosys 0.42 .. Yosys 0.43-dev
+--------------------------
+
 Yosys 0.41 .. Yosys 0.42
 --------------------------
  * New commands and options
diff --git a/Makefile b/Makefile
index 7bfd6010cc6..0c2e11953bb 100644
--- a/Makefile
+++ b/Makefile
@@ -141,7 +141,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.42
+YOSYS_VER := 0.42+0
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -157,7 +157,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-#	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline c1ad377.. | wc -l`/;" Makefile
+	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9b6afcf.. | wc -l`/;" Makefile
 
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
 

From dc693652583e83db82cc95c407e4778e640473d7 Mon Sep 17 00:00:00 2001
From: Asherah Connor <ashe@kivikakk.ee>
Date: Sun, 26 May 2024 18:21:45 +0300
Subject: [PATCH 137/499] cxxrtl: failing test: unconnected blackbox outputs
 don't compile.

---
 tests/cxxrtl/run-test.sh               |  4 ++++
 tests/cxxrtl/test_unconnected_output.v | 24 ++++++++++++++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 tests/cxxrtl/test_unconnected_output.v

diff --git a/tests/cxxrtl/run-test.sh b/tests/cxxrtl/run-test.sh
index 89de71c6b26..fd11a378379 100755
--- a/tests/cxxrtl/run-test.sh
+++ b/tests/cxxrtl/run-test.sh
@@ -11,3 +11,7 @@ run_subtest () {
 
 run_subtest value
 run_subtest value_fuzz
+
+# Compile-only test.
+../../yosys -p "read_verilog test_unconnected_output.v; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc"
+${CC:-gcc} -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc
diff --git a/tests/cxxrtl/test_unconnected_output.v b/tests/cxxrtl/test_unconnected_output.v
new file mode 100644
index 00000000000..84d172bdbbf
--- /dev/null
+++ b/tests/cxxrtl/test_unconnected_output.v
@@ -0,0 +1,24 @@
+(* cxxrtl_blackbox *)
+module blackbox(...);
+    (* cxxrtl_edge = "p" *)
+    input clk;
+
+    (* cxxrtl_sync *)
+    output [7:0] out1;
+
+    (* cxxrtl_sync *)
+    output [7:0] out2;
+endmodule
+
+module unconnected_output(
+    input  clk,
+           in,
+    output out
+);
+    blackbox bb (
+        .clock (clock),
+        .in    (in),
+        .out1  (out),
+        .out2  (/* unconnected */),
+    );
+endmodule

From e97c36d4c4189d57eb84e8d6f57de85dfdd551f8 Mon Sep 17 00:00:00 2001
From: Asherah Connor <ashe@kivikakk.ee>
Date: Sun, 26 May 2024 18:31:32 +0300
Subject: [PATCH 138/499] cxxrtl: don't emit syncs for empty lhs.

---
 backends/cxxrtl/cxxrtl_backend.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index 9ddbd33b0a3..8dc14863d60 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -1138,7 +1138,7 @@ struct CxxrtlWorker {
 		f << indent << "// cell " << cell->name.str() << " syncs\n";
 		for (auto conn : cell->connections())
 			if (cell->output(conn.first))
-				if (is_cxxrtl_sync_port(cell, conn.first)) {
+				if (is_cxxrtl_sync_port(cell, conn.first) && !conn.second.empty()) {
 					f << indent;
 					dump_sigspec_lhs(conn.second, for_debug);
 					f << " = " << mangle(cell) << access << mangle_wire_name(conn.first) << ".curr;\n";

From 54d5e567459e6ba39114d5cebf4291705fe2f1fb Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jean-Fran=C3=A7ois=20Nguyen?= <jf@jfng.fr>
Date: Fri, 7 Jun 2024 05:15:38 +0200
Subject: [PATCH 139/499] cxxrtl: fix `debug_info()` deprecation message.

---
 backends/cxxrtl/runtime/cxxrtl/cxxrtl.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
index 057d34cf906..70f30e7f9cb 100644
--- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
+++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
@@ -1582,7 +1582,7 @@ struct module {
 
 	// Compatibility method.
 #if __has_attribute(deprecated)
-	__attribute__((deprecated("Use `debug_info(path, &items, /*scopes=*/nullptr);` instead. (`path` could be \"top \".)")))
+	__attribute__((deprecated("Use `debug_info(&items, /*scopes=*/nullptr, path);` instead. (`path` could be \"top \".)")))
 #endif
 	void debug_info(debug_items &items, std::string path) {
 		debug_info(&items, /*scopes=*/nullptr, path);

From b0ab1cf8c3a2d864b6ce0675a1235e9293e5730e Mon Sep 17 00:00:00 2001
From: Mike Inouye <mikeinouye@google.com>
Date: Fri, 7 Jun 2024 22:51:28 +0000
Subject: [PATCH 140/499] Fix memory leak in verific file parsing.

Signed-off-by: Mike Inouye <mikeinouye@google.com>
---
 frontends/verific/verific.cc | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index b4b0664d341..f7c2cefd288 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -3510,6 +3510,12 @@ struct VerificPass : public Pass {
 					verific_error_msg.clear();
 					log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
 			}
+			char* fn;
+			int i = 0;
+
+			FOREACH_ARRAY_ITEM(&file_names, i, fn) {
+				free(fn);
+			}
 			set_modules_to_blackbox(map, work, flag_lib);
 			verific_import_pending = true;
 			goto check_error;

From 82783646e57264e82ac29ade76dc2bee6c416667 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Sat, 8 Jun 2024 00:17:45 +0000
Subject: [PATCH 141/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 0c2e11953bb..da8aac473f0 100644
--- a/Makefile
+++ b/Makefile
@@ -141,7 +141,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.42+0
+YOSYS_VER := 0.42+2
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From b593f5c01ce993a16fbba8197d85b58993302239 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Mon, 10 Jun 2024 15:51:43 +0200
Subject: [PATCH 142/499] Update the overview comment in `ast.h`

---
 frontends/ast/ast.h | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index f05b568be22..59a393e080e 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -17,12 +17,7 @@
  *
  *  ---
  *
- *  This is the AST frontend library.
- *
- *  The AST frontend library is not a frontend on it's own but provides a
- *  generic abstract syntax tree (AST) abstraction for HDL code and can be
- *  used by HDL frontends. See "ast.h" for an overview of the API and the
- *  Verilog frontend for an usage example.
+ *  This is support code for the Verilog frontend at frontends/verilog
  *
  */
 

From ef90458820461988f389e6b7f069956fd4156673 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Tue, 11 Jun 2024 00:17:10 +0000
Subject: [PATCH 143/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index da8aac473f0..92fce6c7de3 100644
--- a/Makefile
+++ b/Makefile
@@ -141,7 +141,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.42+2
+YOSYS_VER := 0.42+10
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From df4e630ac49274336b3f1ac6a1ad9e1226a41ed6 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 11 Jun 2024 13:17:56 +1200
Subject: [PATCH 144/499] Docs: Add section for script parsing

Document `!` and `:`.
Add warning that semicolons need spaces.
---
 .../getting_started/scripting_intro.rst       | 38 +++++++++++++++++--
 1 file changed, 34 insertions(+), 4 deletions(-)

diff --git a/docs/source/getting_started/scripting_intro.rst b/docs/source/getting_started/scripting_intro.rst
index bda76b74e9a..a6b4cb6bb42 100644
--- a/docs/source/getting_started/scripting_intro.rst
+++ b/docs/source/getting_started/scripting_intro.rst
@@ -8,10 +8,40 @@ file format and how you can make your own synthesis scripts.
 Yosys script files typically use the :file:`.ys` extension and contain a set of
 commands for Yosys to run sequentially.  These commands are the same ones we
 were using on the previous page like :cmd:ref:`read_verilog` and
-:cmd:ref:`hierarchy`.  As with the interactive shell, each command consists of
-the command name, and an optional whitespace separated list of arguments.
-Commands are terminated with the newline character, or by a semicolon (;). Empty
-lines, and lines starting with the hash sign (#), are ignored.
+:cmd:ref:`hierarchy`.
+
+Script parsing
+~~~~~~~~~~~~~~
+
+As with the interactive shell, each command consists of the command name, and an
+optional whitespace separated list of arguments. Commands are terminated with
+the newline character, and anything after a hash sign ``#`` is a comment (i.e.
+it is ignored).
+
+It is also possible to terminate commands with a semicolon ``;``.  This is
+particularly useful in conjunction with the ``-p <command>`` command line
+option, where ``<command>`` can be a string with multiple commands separated by
+semicolon. In-line comments can also be made with the colon ``:``, where the end
+of the comment is a semicolon ``;`` or a new line.
+
+.. code-block::
+   :caption: Using the ``-p`` option
+
+   $ yosys -p "read_verilog fifo.v; :this is a comment; prep"
+
+.. warning::
+
+   The space after the semicolon is required for correct parsing. ``log a;log
+   b;`` for example will display ``a;log b`` instead of ``a`` and ``b`` as might
+   be expected.
+
+Another special character that can be used in Yosys scripts is the bang ``!``.
+Anything after the bang will be executed as a shell command.  This can only be
+terminated with a new line.  Any semicolons, hashes, or other special characters
+will be passed to the shell.  If an error code is returned from the shell it
+will be raised by Yosys.  :cmd:ref:`exec` provides a much more flexible way of
+executing commands, allowing the output to be logged and more control over when
+to generate errors.
 
 The synthesis starter script
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~

From 7f89a45ad724888b111227127b14a48e0b5e48ad Mon Sep 17 00:00:00 2001
From: Marian Buschsieweke <marian.buschsieweke@posteo.net>
Date: Mon, 10 Jun 2024 21:27:19 +0200
Subject: [PATCH 145/499] cxxxrtl: fix use of format specifiers in test

This fix a few instances of incorrect (and non-portable) use of format
specifiers.
---
 tests/cxxrtl/test_value_fuzz.cc | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/tests/cxxrtl/test_value_fuzz.cc b/tests/cxxrtl/test_value_fuzz.cc
index a7bbb293afc..7e8fbb0a926 100644
--- a/tests/cxxrtl/test_value_fuzz.cc
+++ b/tests/cxxrtl/test_value_fuzz.cc
@@ -1,3 +1,4 @@
+#include <cinttypes>
 #include <cstddef>
 #include <cstdint>
 #include <cstdio>
@@ -62,17 +63,17 @@ void test_binary_operation_for_bitsize(Operation &op)
 		for (size_t i = 0; i * chunk_bits < Bits; i++) {
 			if ((chunk_type)(iresult >> (i * chunk_bits)) != vresult.data[i]) {
 				std::printf("Test failure:\n");
-				std::printf("Bits:    %i\n", Bits);
-				std::printf("a:       %016lx\n", ia);
-				std::printf("b:       %016lx\n", ib);
-				std::printf("iresult: %016lx\n", iresult);
-				std::printf("vresult: %016lx\n", vresult.template get<uint64_t>());
+				std::printf("Bits:    %zu\n", Bits);
+				std::printf("a:       %016" PRIx64 "\n", ia);
+				std::printf("b:       %016" PRIx64 "\n", ib);
+				std::printf("iresult: %016" PRIx64 "\n", iresult);
+				std::printf("vresult: %016" PRIx64 "\n", vresult.template get<uint64_t>());
 
 				std::terminate();
 			}
 		}
 	}
-	std::printf("Test passed @ Bits = %i.\n", Bits);
+	std::printf("Test passed @ Bits = %zu.\n", Bits);
 }
 
 template<typename Operation>

From a55e8594b7a70fc84d0bc6dd1e3075b2737daaab Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Wed, 12 Jun 2024 00:17:25 +0000
Subject: [PATCH 146/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 92fce6c7de3..87f8f17f96b 100644
--- a/Makefile
+++ b/Makefile
@@ -141,7 +141,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.42+10
+YOSYS_VER := 0.42+12
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 3ed2865ac5a251e89b6ef3ca86d4cdc50f2256e2 Mon Sep 17 00:00:00 2001
From: Asherah Connor <ashe@kivikakk.ee>
Date: Fri, 7 Jun 2024 14:30:46 +0300
Subject: [PATCH 147/499] cxxrtl: capi: don't use deprecated invocation.

---
 backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc b/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc
index 3c62401ddea..34801c2d118 100644
--- a/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc
+++ b/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc
@@ -47,7 +47,7 @@ cxxrtl_handle cxxrtl_create_at(cxxrtl_toplevel design, const char *top_path_) {
 
 	cxxrtl_handle handle = new _cxxrtl_handle;
 	handle->module = std::move(design->module);
-	handle->module->debug_info(handle->objects, top_path);
+	handle->module->debug_info(&handle->objects, nullptr, top_path);
 	delete design;
 	return handle;
 }

From 62bff3a20436ee547a500e27e6cc6b7f550a6013 Mon Sep 17 00:00:00 2001
From: Asherah Connor <ashe@kivikakk.ee>
Date: Fri, 7 Jun 2024 14:31:13 +0300
Subject: [PATCH 148/499] cxxrtl: don't need to specify a value for "path".

Callers of the deprecated method had a path already.
---
 backends/cxxrtl/runtime/cxxrtl/cxxrtl.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
index 70f30e7f9cb..d1d6bd8dc68 100644
--- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
+++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
@@ -1582,7 +1582,7 @@ struct module {
 
 	// Compatibility method.
 #if __has_attribute(deprecated)
-	__attribute__((deprecated("Use `debug_info(&items, /*scopes=*/nullptr, path);` instead. (`path` could be \"top \".)")))
+	__attribute__((deprecated("Use `debug_info(&items, /*scopes=*/nullptr, path);` instead.")))
 #endif
 	void debug_info(debug_items &items, std::string path) {
 		debug_info(&items, /*scopes=*/nullptr, path);

From 34b5c6d0622f395b569543fa5c166a304253b535 Mon Sep 17 00:00:00 2001
From: phsauter <phsauter@student.ethz.ch>
Date: Thu, 13 Jun 2024 22:40:12 +0200
Subject: [PATCH 149/499] peepopt: avoid shift-amount underflow

---
 passes/pmgen/peepopt_shiftadd.pmg |  5 ++++-
 tests/opt/bug4413.ys              | 15 +++++++++++++++
 2 files changed, 19 insertions(+), 1 deletion(-)
 create mode 100644 tests/opt/bug4413.ys

diff --git a/passes/pmgen/peepopt_shiftadd.pmg b/passes/pmgen/peepopt_shiftadd.pmg
index e690ff65113..87555979076 100644
--- a/passes/pmgen/peepopt_shiftadd.pmg
+++ b/passes/pmgen/peepopt_shiftadd.pmg
@@ -66,7 +66,8 @@ match add
 	define <bool> offset_negative ((port(add, constport).bits().back() == State::S1) ^ (is_sub && varport_A))
 
 	// checking some value boundaries as well:
-	// data[...-c +:W1] is fine for +/-var (pad at LSB, all data still accessible)
+	// data[...-c +:W1] is fine for any signed var (pad at LSB, all data still accessible)
+	// unsigned shift may underflow (eg var-3 with var<3) -> cannot be converted
 	// data[...+c +:W1] is only fine for +var(add) and var unsigned
 	// (+c cuts lower C bits, making them inaccessible, a signed var could try to access them)
 	// either its an add or the variable port is A (it must be positive)
@@ -74,6 +75,8 @@ match add
 
 	// -> data[var+c +:W1] (with var signed) is illegal
 	filter !(!offset_negative && varport_signed)
+	// -> data >> (var-c) (with var unsigned) is illegal
+	filter !(offset_negative && !varport_signed)
 
 	// state-variables are assigned at the end only:
 	// shift the log2scale offset in-front of add to get true value: (var+c)<<N -> (var<<N)+(c<<N)
diff --git a/tests/opt/bug4413.ys b/tests/opt/bug4413.ys
new file mode 100644
index 00000000000..6c415888238
--- /dev/null
+++ b/tests/opt/bug4413.ys
@@ -0,0 +1,15 @@
+read_verilog <<EOT
+module top(
+	input wire shift,
+	input wire [4:0] data,
+	output wire out
+);
+
+	wire [1:0] shift2 = shift - 1'b1;
+
+	assign out = data >> shift2;
+endmodule
+
+EOT
+
+equiv_opt -assert peepopt

From 2fd2b6538df31f345ac1378b3185ff8785f5684e Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Fri, 14 Jun 2024 00:17:13 +0000
Subject: [PATCH 150/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 87f8f17f96b..7760cec43a2 100644
--- a/Makefile
+++ b/Makefile
@@ -141,7 +141,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.42+12
+YOSYS_VER := 0.42+15
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 74e504330a75afe43117d8ef4ee350f9d6000c74 Mon Sep 17 00:00:00 2001
From: Philippe Sauter <phsauter@iis.ee.ethz.ch>
Date: Fri, 14 Jun 2024 13:01:18 +0200
Subject: [PATCH 151/499] peepopt: fix sign check in shiftadd

---
 passes/pmgen/peepopt_shiftadd.pmg | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/passes/pmgen/peepopt_shiftadd.pmg b/passes/pmgen/peepopt_shiftadd.pmg
index 87555979076..161effe4359 100644
--- a/passes/pmgen/peepopt_shiftadd.pmg
+++ b/passes/pmgen/peepopt_shiftadd.pmg
@@ -63,7 +63,8 @@ match add
 
 	define <bool> constport_signed param(add, !varport_A ? \A_SIGNED : \B_SIGNED).as_bool()
 	define <bool> varport_signed param(add, varport_A ? \A_SIGNED : \B_SIGNED).as_bool();
-	define <bool> offset_negative ((port(add, constport).bits().back() == State::S1) ^ (is_sub && varport_A))
+	define <bool> const_negative (constport_signed && (port(add, constport).bits().back() == State::S1))
+	define <bool> offset_negative ((is_sub && varport_A) ^ const_negative)
 
 	// checking some value boundaries as well:
 	// data[...-c +:W1] is fine for any signed var (pad at LSB, all data still accessible)

From 2f0f10cb871228248c8e012a9d6756c1e1b972c1 Mon Sep 17 00:00:00 2001
From: Philippe Sauter <phsauter@iis.ee.ethz.ch>
Date: Fri, 14 Jun 2024 15:30:03 +0200
Subject: [PATCH 152/499] peepopt: limit padding from shiftadd

The input to a shift operation is padded.
This reduced the final number of MUX cells
but during techmap it can create huge
temporary multiplexers in the log shifter.
This significantly increases runtime and resources.

A limit is added with a warning when it is used.
---
 passes/pmgen/peepopt.cc           | 11 +++++++++++
 passes/pmgen/peepopt_shiftadd.pmg | 15 ++++++++++++---
 2 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc
index edd3b18a815..5638ec3c29c 100644
--- a/passes/pmgen/peepopt.cc
+++ b/passes/pmgen/peepopt.cc
@@ -25,6 +25,9 @@ PRIVATE_NAMESPACE_BEGIN
 
 bool did_something;
 
+// scratchpad configurations for pmgen
+int shiftadd_max_ratio;
+
 #include "passes/pmgen/peepopt_pm.h"
 
 struct PeepoptPass : public Pass {
@@ -50,6 +53,9 @@ struct PeepoptPass : public Pass {
 		log("\n");
 		log("   * shiftadd - Replace A>>(B+D) with (A'>>D)>>(B) where D is constant and\n");
 		log("                A' is derived from A by padding or cutting inaccessible bits.\n");
+		log("                Scratchpad: 'peepopt.shiftadd.max_data_multiple' (default: 2)\n");
+		log("                limits the amount of padding to a multiple of the data, \n");
+		log("                to avoid high resource usage from large temporary MUX trees.\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -63,6 +69,11 @@ struct PeepoptPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
+		// limit the padding from shiftadd to a multiple of the input data
+		// during techmap it creates (#data + #padding) * log(shift) $_MUX_ cells
+		// 2x implies there is a constant shift larger than the input-data which should be extremely rare
+		shiftadd_max_ratio = design->scratchpad_get_int("peepopt.shiftadd.max_data_multiple", 2);
+
 		for (auto module : design->selected_modules())
 		{
 			did_something = true;
diff --git a/passes/pmgen/peepopt_shiftadd.pmg b/passes/pmgen/peepopt_shiftadd.pmg
index e690ff65113..62f54efe515 100644
--- a/passes/pmgen/peepopt_shiftadd.pmg
+++ b/passes/pmgen/peepopt_shiftadd.pmg
@@ -91,11 +91,21 @@ code
 	// it should only differ if previous passes create invalid data
 	log_assert(!(offset>0 && var_signed));
 
+	SigSpec old_a = port(shift, \A); // data
+	std::string location = shift->get_src_attribute();
+
+	if(shiftadd_max_ratio>0 && offset<0 && -offset*shiftadd_max_ratio > old_a.size()) {
+		log_warning("at %s: candiate for shiftadd optimization (shifting '%s' by '%s - %d' bits) " 
+					"was ignored to avoid high resource usage, see help peepopt\n", 
+					location.c_str(), log_signal(old_a), log_signal(var_signal), -offset);
+		reject;
+	}
+
 	did_something = true;
 	log("shiftadd pattern in %s: shift=%s, add/sub=%s, offset: %d\n", \
 			log_id(module), log_id(shift), log_id(add), offset);
 
-	SigSpec old_a = port(shift, \A), new_a;
+	SigSpec new_a;
 	if(offset<0) {
 		// data >> (...-c) transformed to {data, c'X} >> (...)
 		SigSpec padding( (shift->type.in($shiftx) ? State::Sx : State::S0), -offset );
@@ -107,14 +117,13 @@ code
 			new_a.append(old_a.extract_end(offset));
 		} else {
 			// warn user in case data is empty (no bits left)
-			std::string location = shift->get_src_attribute();
 			if (location.empty())
 				location = shift->name.str();
 			if(shift->type.in($shiftx))
 				log_warning("at %s: result of indexed part-selection is always constant (selecting from '%s' with index '%s + %d')\n", \
 							location.c_str(), log_signal(old_a), log_signal(var_signal), offset);
 			else
-				log_warning("at %s: result of shift operation is always constant (shifting '%s' by '%s + %d'-bits)\n", \
+				log_warning("at %s: result of shift operation is always constant (shifting '%s' by '%s + %d' bits)\n", \
 							location.c_str(), log_signal(old_a), log_signal(var_signal), offset);
 		}
 	}

From 54bf9ccf0684cb4fcb8811db43a966c99da975e8 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 21 May 2024 17:08:07 +0200
Subject: [PATCH 153/499] Add initial support for Verific without additional
 YosysHQ patch

---
 Makefile                     | 11 +++++-
 frontends/verific/verific.cc | 76 ++++++++++++++++++++++++++++++++++--
 2 files changed, 83 insertions(+), 4 deletions(-)

diff --git a/Makefile b/Makefile
index 7760cec43a2..7091318ca83 100644
--- a/Makefile
+++ b/Makefile
@@ -21,6 +21,7 @@ ENABLE_VERIFIC_EDIF := 0
 ENABLE_VERIFIC_LIBERTY := 0
 DISABLE_VERIFIC_EXTENSIONS := 0
 DISABLE_VERIFIC_VHDL := 0
+DISABLE_VERIFIC_HIER_TREE := 0
 ENABLE_COVER := 1
 ENABLE_LIBYOSYS := 0
 ENABLE_ZLIB := 1
@@ -471,7 +472,15 @@ endif
 LIBS_VERIFIC =
 ifeq ($(ENABLE_VERIFIC),1)
 VERIFIC_DIR ?= /usr/local/src/verific_lib
-VERIFIC_COMPONENTS ?= verilog database util containers hier_tree
+VERIFIC_COMPONENTS ?= verilog database util containers
+ifneq ($(DISABLE_VERIFIC_HIER_TREE),1)
+VERIFIC_COMPONENTS += hier_tree
+CXXFLAGS += -DVERIFIC_HIER_TREE_SUPPORT
+else
+ifneq ($(wildcard $(VERIFIC_DIR)/hier_tree),)
+VERIFIC_COMPONENTS += hier_tree
+endif
+endif
 ifneq ($(DISABLE_VERIFIC_VHDL),1)
 VERIFIC_COMPONENTS += vhdl
 CXXFLAGS += -DVERIFIC_VHDL_SUPPORT
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index f7c2cefd288..5c075956704 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -43,7 +43,9 @@ USING_YOSYS_NAMESPACE
 #endif
 
 #include "veri_file.h"
+#ifdef VERIFIC_HIER_TREE_SUPPORT
 #include "hier_tree.h"
+#endif
 #include "VeriModule.h"
 #include "VeriWrite.h"
 #include "VeriLibrary.h"
@@ -72,12 +74,16 @@ USING_YOSYS_NAMESPACE
 #endif
 
 #ifndef YOSYSHQ_VERIFIC_API_VERSION
-#  error "Only YosysHQ flavored Verific is supported. Please contact office@yosyshq.com for commercial support for Yosys+Verific."
-#endif
-
+#warning "Only YosysHQ flavored Verific is fully supported. Please contact office@yosyshq.com for commercial support for Yosys+Verific."
+#else
 #if YOSYSHQ_VERIFIC_API_VERSION < 20230901
 #  error "Please update your version of YosysHQ flavored Verific."
 #endif
+#endif
+
+#ifndef DB_PRESERVE_INITIAL_VALUE
+#error "Verific must have DB_PRESERVE_INITIAL_VALUE compile flag set on"
+#endif
 
 #ifdef __clang__
 #pragma clang diagnostic pop
@@ -115,9 +121,15 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil
 
 	if (log_verific_callback) {
 		string full_message = stringf("%s%s\n", message_prefix.c_str(), message.c_str());
+#ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS 
 		log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), 
 			linefile ? linefile->GetLeftLine() : 0, linefile ? linefile->GetLeftCol() : 0, 
 			linefile ? linefile->GetRightLine() : 0, linefile ? linefile->GetRightCol() : 0, full_message.c_str());
+#else
+		log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), 
+			linefile ? LineFile::GetLineNo(linefile) : 0, 0, 
+			linefile ? LineFile::GetLineNo(linefile) : 0, 0, full_message.c_str());
+#endif
 	} else {
 		if (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_WARNING || msg_type == VERIFIC_PROGRAM_ERROR)
 			log_warning_noprefix("%s%s\n", message_prefix.c_str(), message.c_str());
@@ -392,6 +404,7 @@ static const RTLIL::Const verific_const(const char* type_name, const char *value
 		return extract_verilog_const(value, allow_string, output_signed);
 }
 
+#ifdef YOSYSHQ_VERIFIC_API_VERSION
 static const std::string verific_unescape(const char *value)
 {
 	std::string val = std::string(value);
@@ -399,6 +412,7 @@ static const std::string verific_unescape(const char *value)
 		return val.substr(1,val.size()-2);
 	return value;
 }
+#endif
 
 void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj, Netlist *nl)
 {
@@ -408,8 +422,13 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
 	MapIter mi;
 	Att *attr;
 
+#ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS 
 	if (obj->Linefile())
 		attributes[ID::src] = stringf("%s:%d.%d-%d.%d", LineFile::GetFileName(obj->Linefile()), obj->Linefile()->GetLeftLine(), obj->Linefile()->GetLeftCol(), obj->Linefile()->GetRightLine(), obj->Linefile()->GetRightCol());
+#else
+	if (obj->Linefile())
+		attributes[ID::src] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile()));
+#endif
 
 	FOREACH_ATTRIBUTE(obj, mi, attr) {
 		if (attr->Key()[0] == ' ' || attr->Value() == nullptr)
@@ -1265,6 +1284,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 		return true;
 	}
 
+#ifdef YOSYSHQ_VERIFIC_API_VERSION
 	if (inst->Type() == OPER_YOSYSHQ_SET_TAG)
 	{
 		RTLIL::SigSpec sig_expr = operatorInport(inst, "expr");
@@ -1301,6 +1321,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 		module->connect(operatorOutput(inst),module->FutureFF(new_verific_id(inst), operatorInput(inst)));
 		return true;
 	}
+#endif
 
 	#undef IN
 	#undef IN1
@@ -2067,6 +2088,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 				continue;
 		}
 
+#ifdef YOSYSHQ_VERIFIC_API_VERSION
 		if (inst->Type() == PRIM_YOSYSHQ_INITSTATE)
 		{
 			if (verific_verbose)
@@ -2078,6 +2100,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 			if (!mode_keep)
 				continue;
 		}
+#endif
 
 		if (!mode_keep && verific_sva_prims.count(inst->Type())) {
 			if (verific_verbose)
@@ -2680,7 +2703,24 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 		VerificExtensions::ElaborateAndRewrite("work", &verific_params);
 		verific_error_msg.clear();
 #endif
+#ifdef VERIFIC_HIER_TREE_SUPPORT
 		netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &verific_params);
+#else
+		if (parameters.size())
+			log_warning("Please note that parameters are not propagated during import.\n");
+		veri_file::ElaborateAll("work");
+		MapIter mi ;
+		Verific::Cell *c ;
+		Library *l = Libset::Global()->GetLibrary("work");
+		FOREACH_CELL_OF_LIBRARY(l,mi,c) {
+			MapIter ni ;
+			Netlist *nl;
+			FOREACH_NETLIST_OF_CELL(c, ni, nl) {
+				if (nl)
+					nl_todo.emplace(nl->CellBaseName(), nl);
+			}
+		}
+#endif
 	}
 	else {
 
@@ -2737,7 +2777,11 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 			}
 #endif
 
+#ifdef VERIFIC_HIER_TREE_SUPPORT
 			netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params);
+#else
+			netlists = veri_file::ElaborateMultipleTop(&veri_modules, &verific_params);
+#endif
 		}
 	}
 
@@ -2781,7 +2825,9 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 #ifdef YOSYSHQ_VERIFIC_EXTENSIONS
 	VerificExtensions::Reset();
 #endif
+#ifdef VERIFIC_HIER_TREE_SUPPORT
 	hier_tree::DeleteHierarchicalTree();
+#endif
 	veri_file::Reset();
 #ifdef VERIFIC_VHDL_SUPPORT
 	vhdl_file::Reset();
@@ -3852,6 +3898,7 @@ struct VerificPass : public Pass {
 #endif
 				if (veri_lib) veri_libs.InsertLast(veri_lib);
 
+#ifdef VERIFIC_HIER_TREE_SUPPORT
 				Array *netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &parameters);
 				Netlist *nl;
 				int i;
@@ -3859,6 +3906,23 @@ struct VerificPass : public Pass {
 				FOREACH_ARRAY_ITEM(netlists, i, nl)
 					nl_todo.emplace(nl->CellBaseName(), nl);
 				delete netlists;
+#else
+				if (parameters.Size())
+					log_warning("Please note that parameters are not propagated during import.\n");
+				veri_file::ElaborateAll(work.c_str());
+
+				MapIter mi ;
+				Verific::Cell *c ;
+				Library *l = Libset::Global()->GetLibrary(work.c_str());
+				FOREACH_CELL_OF_LIBRARY(l,mi,c) {
+					MapIter ni ;
+					Netlist *nl;
+					FOREACH_NETLIST_OF_CELL(c, ni, nl) {
+						if (nl)
+							nl_todo.emplace(nl->CellBaseName(), nl);
+					}
+				}
+#endif
 			}
 			else
 			{
@@ -3949,7 +4013,11 @@ struct VerificPass : public Pass {
 					}
 
 					log("Running hier_tree::Elaborate().\n");
+#ifdef VERIFIC_HIER_TREE_SUPPORT
 					netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &parameters);
+#else
+					netlists = veri_file::ElaborateMultipleTop(&veri_modules, &parameters);
+#endif
 				}
 
 				Netlist *nl;
@@ -4026,7 +4094,9 @@ struct VerificPass : public Pass {
 #ifdef YOSYSHQ_VERIFIC_EXTENSIONS
 			VerificExtensions::Reset();
 #endif
+#ifdef VERIFIC_HIER_TREE_SUPPORT
 			hier_tree::DeleteHierarchicalTree();
+#endif
 			veri_file::Reset();
 #ifdef VERIFIC_VHDL_SUPPORT
 			vhdl_file::Reset();

From 25d50bb2afd8d39409d697946057772545e9c5e3 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 7 Jun 2024 14:58:33 +0200
Subject: [PATCH 154/499] VHDL only build support

---
 Makefile                        |  11 ++-
 frontends/verific/verific.cc    | 156 ++++++++++++++++++++++++++------
 frontends/verific/verificsva.cc |   6 +-
 3 files changed, 144 insertions(+), 29 deletions(-)

diff --git a/Makefile b/Makefile
index 7091318ca83..0712e987bf1 100644
--- a/Makefile
+++ b/Makefile
@@ -20,6 +20,7 @@ ENABLE_VERIFIC := 0
 ENABLE_VERIFIC_EDIF := 0
 ENABLE_VERIFIC_LIBERTY := 0
 DISABLE_VERIFIC_EXTENSIONS := 0
+DISABLE_VERIFIC_SYSTEMVERILOG := 0
 DISABLE_VERIFIC_VHDL := 0
 DISABLE_VERIFIC_HIER_TREE := 0
 ENABLE_COVER := 1
@@ -472,7 +473,7 @@ endif
 LIBS_VERIFIC =
 ifeq ($(ENABLE_VERIFIC),1)
 VERIFIC_DIR ?= /usr/local/src/verific_lib
-VERIFIC_COMPONENTS ?= verilog database util containers
+VERIFIC_COMPONENTS ?= database util containers
 ifneq ($(DISABLE_VERIFIC_HIER_TREE),1)
 VERIFIC_COMPONENTS += hier_tree
 CXXFLAGS += -DVERIFIC_HIER_TREE_SUPPORT
@@ -481,6 +482,14 @@ ifneq ($(wildcard $(VERIFIC_DIR)/hier_tree),)
 VERIFIC_COMPONENTS += hier_tree
 endif
 endif
+ifneq ($(DISABLE_VERIFIC_SYSTEMVERILOG),1)
+VERIFIC_COMPONENTS += verilog
+CXXFLAGS += -DVERIFIC_SYSTEMVERILOG_SUPPORT
+else
+ifneq ($(wildcard $(VERIFIC_DIR)/verilog),)
+VERIFIC_COMPONENTS += verilog
+endif
+endif
 ifneq ($(DISABLE_VERIFIC_VHDL),1)
 VERIFIC_COMPONENTS += vhdl
 CXXFLAGS += -DVERIFIC_VHDL_SUPPORT
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 5c075956704..c76ee14e57f 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -42,14 +42,17 @@ USING_YOSYS_NAMESPACE
 #pragma clang diagnostic ignored "-Woverloaded-virtual"
 #endif
 
-#include "veri_file.h"
 #ifdef VERIFIC_HIER_TREE_SUPPORT
 #include "hier_tree.h"
 #endif
+
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+#include "veri_file.h"
 #include "VeriModule.h"
 #include "VeriWrite.h"
 #include "VeriLibrary.h"
 #include "VeriExpression.h"
+#endif
 
 #ifdef VERIFIC_VHDL_SUPPORT
 #include "vhdl_file.h"
@@ -103,7 +106,9 @@ bool verific_import_pending;
 string verific_error_msg;
 int verific_sva_fsm_limit;
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 vector<string> verific_incdirs, verific_libdirs, verific_libexts;
+#endif
 
 void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefile, const char *msg, va_list args)
 {
@@ -157,6 +162,7 @@ string get_full_netlist_name(Netlist *nl)
 	return nl->CellBaseName();
 }
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 class YosysStreamCallBackHandler : public VerificStreamCallBackHandler
 {
 public:
@@ -186,6 +192,7 @@ class YosysStreamCallBackHandler : public VerificStreamCallBackHandler
 };
 
 YosysStreamCallBackHandler verific_read_cb;
+#endif
 
 // ==================================================================
 
@@ -1825,10 +1832,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 	for (auto net : anyseq_nets)
 		module->connect(net_map_at(net), module->Anyseq(new_verific_id(net)));
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 	pool<Instance*, hash_ptr_ops> sva_asserts;
 	pool<Instance*, hash_ptr_ops> sva_assumes;
 	pool<Instance*, hash_ptr_ops> sva_covers;
 	pool<Instance*, hash_ptr_ops> sva_triggers;
+#endif
 
 	pool<RTLIL::Cell*> past_ffs;
 
@@ -1945,6 +1954,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 				continue;
 		}
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		if (inst->Type() == PRIM_SVA_ASSERT || inst->Type() == PRIM_SVA_IMMEDIATE_ASSERT)
 			sva_asserts.insert(inst);
 
@@ -2087,6 +2097,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 			if (!mode_keep)
 				continue;
 		}
+#endif
 
 #ifdef YOSYSHQ_VERIFIC_API_VERSION
 		if (inst->Type() == PRIM_YOSYSHQ_INITSTATE)
@@ -2210,6 +2221,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		}
 	}
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 	if (!mode_nosva)
 	{
 		for (auto inst : sva_asserts) {
@@ -2229,6 +2241,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 
 		merge_past_ffs(past_ffs);
 	}
+#endif
 
 	if (!mode_fullinit)
 	{
@@ -2280,7 +2293,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 
 // ==================================================================
 
-VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_at_only)
+VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_at_only YS_MAYBE_UNUSED)
 {
 	module = importer->module;
 
@@ -2289,6 +2302,7 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a
 
 	Instance *inst = net->Driver();
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 	// Detect condition expression in sva_at_only mode
 	if (sva_at_only)
 	do {
@@ -2337,7 +2351,7 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a
 		net = inst->GetInput();
 		inst = net->Driver();;
 	}
-
+#endif
 	if (inst != nullptr && inst->Type() == PRIM_INV)
 	{
 		net = inst->GetInput();
@@ -2383,6 +2397,7 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a
 		inst = net->Driver();;
 	} while (0);
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 	// Detect condition expression
 	do {
 		if (body_net == nullptr)
@@ -2407,6 +2422,7 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a
 		cond_net = inst_mux->GetControl();
 		cond_pol = pwr1;
 	} while (0);
+#endif
 
 	clock_net = net;
 	clock_sig = importer->net_map_at(clock_net);
@@ -2683,15 +2699,16 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 	verific_sva_fsm_limit = 16;
 
 	std::map<std::string,Netlist*> nl_todo, nl_done;
-
-	VeriLibrary *veri_lib = veri_file::GetLibrary("work", 1);
 	Array *netlists = NULL;
 	Array veri_libs, vhdl_libs;
 #ifdef VERIFIC_VHDL_SUPPORT
 	VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1);
 	if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);
 #endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+	VeriLibrary *veri_lib = veri_file::GetLibrary("work", 1);
 	if (veri_lib) veri_libs.InsertLast(veri_lib);
+#endif
 
 	Map verific_params(STRING_HASH);
 	for (const auto &i : parameters)
@@ -2708,7 +2725,13 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 #else
 		if (parameters.size())
 			log_warning("Please note that parameters are not propagated during import.\n");
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		veri_file::ElaborateAll("work");
+#endif
+#ifdef VERIFIC_VHDL_SUPPORT
+		vhdl_file::ElaborateAll("work");
+#endif
+		netlists = new Array(1);
 		MapIter mi ;
 		Verific::Cell *c ;
 		Library *l = Libset::Global()->GetLibrary("work");
@@ -2717,7 +2740,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 			Netlist *nl;
 			FOREACH_NETLIST_OF_CELL(c, ni, nl) {
 				if (nl)
-					nl_todo.emplace(nl->CellBaseName(), nl);
+					netlists->InsertLast(nl);
 			}
 		}
 #endif
@@ -2728,7 +2751,8 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 		for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--)
 #endif
 		{
-			Array veri_modules, vhdl_units;
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+			Array veri_modules;
 
 			if (veri_lib) {
 				VeriModule *veri_module = veri_lib->GetModule(top.c_str(), 1);
@@ -2760,8 +2784,10 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 					}
 				}
 			}
+#endif
 
 #ifdef VERIFIC_VHDL_SUPPORT
+			Array vhdl_units;
 			if (vhdl_lib) {
 				VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(top.c_str());
 				if (vhdl_unit)
@@ -2780,7 +2806,17 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 #ifdef VERIFIC_HIER_TREE_SUPPORT
 			netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params);
 #else
+#if defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && !defined(VERIFIC_VHDL_SUPPORT)
+			// SystemVerilog support only
 			netlists = veri_file::ElaborateMultipleTop(&veri_modules, &verific_params);
+#elif defined(VERIFIC_VHDL_SUPPORT) && !defined(VERIFIC_SYSTEMVERILOG_SUPPORT)
+			// VHDL support	only
+			netlists = new Array(1);
+			vhdl_file::Elaborate(top.c_str(), "work", 0, &verific_params);
+			netlists->InsertLast(Netlist::PresentDesign());
+#else
+			// Both SystemVerilog and VHDL support
+#endif
 #endif
 		}
 	}
@@ -2828,7 +2864,9 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 #ifdef VERIFIC_HIER_TREE_SUPPORT
 	hier_tree::DeleteHierarchicalTree();
 #endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 	veri_file::Reset();
+#endif
 #ifdef VERIFIC_VHDL_SUPPORT
 	vhdl_file::Reset();
 #endif
@@ -2842,9 +2880,11 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 	Message::Reset();
 	RuntimeFlags::DeleteAllFlags();
 	LineFile::DeleteAllLineFiles();
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 	verific_incdirs.clear();
 	verific_libdirs.clear();
 	verific_libexts.clear();
+#endif
 	verific_import_pending = false;
 
 	if (!verific_error_msg.empty())
@@ -2875,6 +2915,7 @@ struct VerificPass : public Pass {
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		log("    verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv} <verilog-file>..\n");
 		log("\n");
 		log("Load the specified Verilog/SystemVerilog files into Verific.\n");
@@ -2893,6 +2934,7 @@ struct VerificPass : public Pass {
 		log("Like -sv, but define FORMAL instead of SYNTHESIS.\n");
 		log("\n");
 		log("\n");
+#endif
 #ifdef VERIFIC_VHDL_SUPPORT
 		log("    verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl2019|-vhdl} <vhdl-file>..\n");
 		log("\n");
@@ -2919,6 +2961,7 @@ struct VerificPass : public Pass {
 		log("\n");
 		log("\n");
 #endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		log("    verific {-f|-F} [-vlog95|-vlog2k|-sv2005|-sv2009|\n");
 		log("                     -sv2012|-sv|-formal] <command-file>\n");
 		log("\n");
@@ -2952,6 +2995,7 @@ struct VerificPass : public Pass {
 		log("        -sverilog\n");
 		log("\n");
 		log("\n");
+#endif
 		log("    verific [-work <libname>] {-sv|-vhdl|...} <hdl-file>\n");
 		log("\n");
 		log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n");
@@ -2964,6 +3008,7 @@ struct VerificPass : public Pass {
 		log("(-L may be used more than once)\n");
 		log("\n");
 		log("\n");
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		log("    verific -vlog-incdir <directory>..\n");
 		log("\n");
 		log("Add Verilog include directories.\n");
@@ -2990,6 +3035,7 @@ struct VerificPass : public Pass {
 		log("Remove Verilog defines previously set with -vlog-define.\n");
 		log("\n");
 		log("\n");
+#endif
 		log("    verific -set-error <msg_id>..\n");
 		log("    verific -set-warning <msg_id>..\n");
 		log("    verific -set-info <msg_id>..\n");
@@ -3024,9 +3070,11 @@ struct VerificPass : public Pass {
 		log("  -no-split-complex-ports\n");
 		log("    Complex ports (structs or arrays) are not split and remain packed as a single port.\n");
 		log("\n");
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		log("  -autocover\n");
 		log("    Generate automatic cover statements for all asserts\n");
 		log("\n");
+#endif
 		log("  -fullinit\n");
 		log("    Keep all register initializations, even those for non-FF registers.\n");
 		log("\n");
@@ -3059,12 +3107,14 @@ struct VerificPass : public Pass {
 		log("  -V\n");
 		log("    Import Verific netlist as-is without translating to Yosys cell types. \n");
 		log("\n");
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		log("  -nosva\n");
 		log("    Ignore SVA properties, do not infer checker logic.\n");
 		log("\n");
 		log("  -L <int>\n");
 		log("    Maximum number of ctrl bits for SVA checker FSMs (default=16).\n");
 		log("\n");
+#endif
 		log("  -n\n");
 		log("    Keep all Verific names on instances and nets. By default only\n");
 		log("    user-declared names are preserved.\n");
@@ -3188,7 +3238,7 @@ struct VerificPass : public Pass {
 #endif
 
 	msg_type_t prev_1063;
-
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 	void add_modules_to_map(Map &map, std::string work, bool flag_lib)
 	{
 		MapIter mi ;
@@ -3222,6 +3272,7 @@ struct VerificPass : public Pass {
 		if (Message::GetMessageType("VERI-1063")!=prev_1063)
 			Message::SetMessageType("VERI-1063", prev_1063);
 	}
+#endif
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
@@ -3254,10 +3305,11 @@ struct VerificPass : public Pass {
 			// Properly respect order of read and write for rams
 			RuntimeFlags::SetVar("db_change_inplace_ram_blocking_write_before_read", 1);
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 			RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
 			RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
 			RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1);
-
+#endif
 #ifdef VERIFIC_VHDL_SUPPORT
 			RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);
 			RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1);
@@ -3270,6 +3322,7 @@ struct VerificPass : public Pass {
 			//RuntimeFlags::SetVar("vhdl_preserve_comments", 1);
 			RuntimeFlags::SetVar("vhdl_preserve_drivers", 1);
 #endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 			RuntimeFlags::SetVar("veri_preserve_assignments", 1);
 			RuntimeFlags::SetVar("veri_preserve_comments", 1);
 			RuntimeFlags::SetVar("veri_preserve_drivers", 1);
@@ -3282,7 +3335,7 @@ struct VerificPass : public Pass {
 
 			// https://github.com/YosysHQ/yosys/issues/1055
 			RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ;
-
+#endif
 			RuntimeFlags::SetVar("verific_produce_verbose_syntax_error_message", 1);
 
 #ifndef DB_PRESERVE_INITIAL_VALUE
@@ -3312,8 +3365,9 @@ struct VerificPass : public Pass {
 		std::string work = "work";
 		bool is_work_set = false;
 		(void)is_work_set;
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		veri_file::RegisterCallBackVerificStream(&verific_read_cb);
-
+#endif
 		if (GetSize(args) > argidx && (args[argidx] == "-set-error" || args[argidx] == "-set-warning" ||
 				args[argidx] == "-set-info" || args[argidx] == "-set-ignore"))
 		{
@@ -3347,6 +3401,7 @@ struct VerificPass : public Pass {
 			goto check_error;
 		}
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		if (GetSize(args) > argidx && args[argidx] == "-vlog-incdir") {
 			for (argidx++; argidx < GetSize(args); argidx++)
 				verific_incdirs.push_back(args[argidx]);
@@ -3566,14 +3621,17 @@ struct VerificPass : public Pass {
 			verific_import_pending = true;
 			goto check_error;
 		}
+#endif
 
 #ifdef VERIFIC_VHDL_SUPPORT
 		if (GetSize(args) > argidx && args[argidx] == "-vhdl87") {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str());
 			bool flag_lib = false;
-			for (argidx++; argidx < GetSize(args); argidx++) {
+			argidx++;
+			while (argidx < GetSize(args)) {
 				if (args[argidx] == "-lib") {
 					flag_lib = true;
+					argidx++;
 					continue;
 				}
 				if (args[argidx].compare(0, 1, "-") == 0) {
@@ -3594,9 +3652,11 @@ struct VerificPass : public Pass {
 		if (GetSize(args) > argidx && args[argidx] == "-vhdl93") {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
 			bool flag_lib = false;
-			for (argidx++; argidx < GetSize(args); argidx++) {
+			argidx++;
+			while (argidx < GetSize(args)) {
 				if (args[argidx] == "-lib") {
 					flag_lib = true;
+					argidx++;
 					continue;
 				}
 				if (args[argidx].compare(0, 1, "-") == 0) {
@@ -3617,9 +3677,11 @@ struct VerificPass : public Pass {
 		if (GetSize(args) > argidx && args[argidx] == "-vhdl2k") {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
 			bool flag_lib = false;
-			for (argidx++; argidx < GetSize(args); argidx++) {
+			argidx++;
+			while (argidx < GetSize(args)) {
 				if (args[argidx] == "-lib") {
 					flag_lib = true;
+					argidx++;
 					continue;
 				}
 				if (args[argidx].compare(0, 1, "-") == 0) {
@@ -3640,9 +3702,11 @@ struct VerificPass : public Pass {
 		if (GetSize(args) > argidx && (args[argidx] == "-vhdl2019")) {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2019").c_str());
 			bool flag_lib = false;
-			for (argidx++; argidx < GetSize(args); argidx++) {
+			argidx++;
+			while (argidx < GetSize(args)) {
 				if (args[argidx] == "-lib") {
 					flag_lib = true;
+					argidx++;
 					continue;
 				}
 				if (args[argidx].compare(0, 1, "-") == 0) {
@@ -3663,9 +3727,11 @@ struct VerificPass : public Pass {
 		if (GetSize(args) > argidx && (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl")) {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
 			bool flag_lib = false;
-			for (argidx++; argidx < GetSize(args); argidx++) {
+			argidx++;
+			while (argidx < GetSize(args)) {
 				if (args[argidx] == "-lib") {
 					flag_lib = true;
+					argidx++;
 					continue;
 				}
 				if (args[argidx].compare(0, 1, "-") == 0) {
@@ -3774,8 +3840,10 @@ struct VerificPass : public Pass {
 #else
 				goto check_error;
 #endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 			else
 				veri_file::PrettyPrint(filename, module, work.c_str());
+#endif
 			goto check_error;
 		}
 
@@ -3816,6 +3884,7 @@ struct VerificPass : public Pass {
 					mode_keep = true;
 					continue;
 				}
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 				if (args[argidx] == "-nosva") {
 					mode_nosva = true;
 					continue;
@@ -3824,14 +3893,17 @@ struct VerificPass : public Pass {
 					verific_sva_fsm_limit = atoi(args[++argidx].c_str());
 					continue;
 				}
+#endif
 				if (args[argidx] == "-n") {
 					mode_names = true;
 					continue;
 				}
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 				if (args[argidx] == "-autocover") {
 					mode_autocover = true;
 					continue;
 				}
+#endif
 				if (args[argidx] == "-fullinit") {
 					mode_fullinit = true;
 					continue;
@@ -3884,19 +3956,22 @@ struct VerificPass : public Pass {
 				VerificExtensions::ElaborateAndRewrite(work, &parameters);
 				verific_error_msg.clear();
 #endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 				if (!ppfile.empty())
 					veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str());
-
+#endif
 				log("Running hier_tree::ElaborateAll().\n");
 
-				VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1);
-
-				Array veri_libs, vhdl_libs;
 #ifdef VERIFIC_VHDL_SUPPORT
+				Array vhdl_libs;
 				VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
 				if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);
 #endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+				Array veri_libs;
+				VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1);
 				if (veri_lib) veri_libs.InsertLast(veri_lib);
+#endif
 
 #ifdef VERIFIC_HIER_TREE_SUPPORT
 				Array *netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &parameters);
@@ -3909,8 +3984,12 @@ struct VerificPass : public Pass {
 #else
 				if (parameters.Size())
 					log_warning("Please note that parameters are not propagated during import.\n");
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 				veri_file::ElaborateAll(work.c_str());
-
+#endif
+#ifdef VERIFIC_VHDL_SUPPORT
+				vhdl_file::ElaborateAll(work.c_str());
+#endif
 				MapIter mi ;
 				Verific::Cell *c ;
 				Library *l = Libset::Global()->GetLibrary(work.c_str());
@@ -3936,17 +4015,20 @@ struct VerificPass : public Pass {
 #endif
 				{
 
-					VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1);
 #ifdef VERIFIC_VHDL_SUPPORT
+					Array vhdl_units;
 					VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
 #endif
-
-					Array veri_modules, vhdl_units;
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+					Array veri_modules;
+					VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1);
+#endif
 					for (int i = argidx; i < GetSize(args); i++)
 					{
 						const char *name = args[i].c_str();
 						top_mod_names.insert(name);
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 						VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr;
 						if (veri_module) {
 							if (veri_module->IsConfiguration()) {
@@ -3974,6 +4056,7 @@ struct VerificPass : public Pass {
 							}
 							continue;
 						}
+#endif
 #ifdef VERIFIC_VHDL_SUPPORT
 						VhdlDesignUnit *vhdl_unit = vhdl_lib ? vhdl_lib->GetPrimUnit(name) : nullptr;
 						if (vhdl_unit) {
@@ -3990,13 +4073,15 @@ struct VerificPass : public Pass {
 						VerificExtensions::ElaborateAndRewrite(work, &veri_modules, &vhdl_units, &parameters);
 						verific_error_msg.clear();
 #endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 						if (!ppfile.empty())
 							veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str());
-
+#endif
 #ifdef YOSYSHQ_VERIFIC_EXTENSIONS
 						continue;
 					}
 #endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 					const char *lib_name = nullptr;
 					SetIter si;
 					FOREACH_SET_ITEM(veri_file::GetAllLOptions(), si, &lib_name) {
@@ -4011,12 +4096,24 @@ struct VerificPass : public Pass {
 							}
 						}
 					}
-
+#endif
 					log("Running hier_tree::Elaborate().\n");
 #ifdef VERIFIC_HIER_TREE_SUPPORT
 					netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &parameters);
 #else
+#if defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && !defined(VERIFIC_VHDL_SUPPORT)
+					// SystemVerilog support only
 					netlists = veri_file::ElaborateMultipleTop(&veri_modules, &parameters);
+#elif defined(VERIFIC_VHDL_SUPPORT) && !defined(VERIFIC_SYSTEMVERILOG_SUPPORT)
+					// VHDL support	only
+					netlists = new Array(top_mod_names.size());
+					for (auto &name : top_mod_names) {
+						vhdl_file::Elaborate(name.c_str(), work.c_str(), 0, &parameters);
+						netlists->InsertLast(Netlist::PresentDesign());
+					}
+#else
+					// Both SystemVerilog and VHDL support
+#endif
 #endif
 				}
 
@@ -4074,11 +4171,12 @@ struct VerificPass : public Pass {
 					nl.second->ChangePortBusStructures(1 /* hierarchical */);
 			}
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 			if (!dumpfile.empty()) {
 				VeriWrite veri_writer;
 				veri_writer.WriteFile(dumpfile.c_str(), Netlist::PresentDesign());
 			}
-
+#endif
 			while (!nl_todo.empty()) {
 				auto it = nl_todo.begin();
 				Netlist *nl = it->second;
@@ -4097,7 +4195,9 @@ struct VerificPass : public Pass {
 #ifdef VERIFIC_HIER_TREE_SUPPORT
 			hier_tree::DeleteHierarchicalTree();
 #endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 			veri_file::Reset();
+#endif
 #ifdef VERIFIC_VHDL_SUPPORT
 			vhdl_file::Reset();
 #endif
@@ -4111,9 +4211,11 @@ struct VerificPass : public Pass {
 			Message::Reset();
 			RuntimeFlags::DeleteAllFlags();
 			LineFile::DeleteAllLineFiles();
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 			verific_incdirs.clear();
 			verific_libdirs.clear();
 			verific_libexts.clear();
+#endif
 			verific_import_pending = false;
 			goto check_error;
 		}
diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc
index 222c7d2e917..b219c01652b 100644
--- a/frontends/verific/verificsva.cc
+++ b/frontends/verific/verificsva.cc
@@ -80,6 +80,7 @@ USING_YOSYS_NAMESPACE
 using namespace Verific;
 #endif
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 PRIVATE_NAMESPACE_BEGIN
 
 // Non-deterministic FSM
@@ -1878,5 +1879,8 @@ bool verific_is_sva_net(VerificImporter *importer, Verific::Net *net)
 	worker.importer = importer;
 	return worker.net_to_ast_driver(net) != nullptr;
 }
-
+#else
+YOSYS_NAMESPACE_BEGIN
+pool<int> verific_sva_prims = {};
+#endif
 YOSYS_NAMESPACE_END

From 7bec332b68e2c72457e90ed4dbf0cb56ad350f42 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 10 Jun 2024 09:44:39 +0200
Subject: [PATCH 155/499] SV + VHDL with RTL support

---
 frontends/verific/verific.cc | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index c76ee14e57f..84fc834eae4 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2816,6 +2816,14 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 			netlists->InsertLast(Netlist::PresentDesign());
 #else
 			// Both SystemVerilog and VHDL support
+			if (veri_modules.Size()>0)
+				netlists = veri_file::ElaborateMultipleTop(&veri_modules, &verific_params);
+			else
+				netlists = new Array(1);
+			if (vhdl_units.Size()>0) {
+				vhdl_file::Elaborate(top.c_str(), "work", 0, &verific_params);
+				netlists->InsertLast(Netlist::PresentDesign());
+			}
 #endif
 #endif
 		}
@@ -4113,6 +4121,16 @@ struct VerificPass : public Pass {
 					}
 #else
 					// Both SystemVerilog and VHDL support
+					if (veri_modules.Size()>0)
+						netlists = veri_file::ElaborateMultipleTop(&veri_modules, &parameters);
+					else
+						netlists = new Array(1);
+					if (vhdl_units.Size()>0) {
+						for (auto &name : top_mod_names) {
+							vhdl_file::Elaborate(name.c_str(), work.c_str(), 0, &parameters);
+							netlists->InsertLast(Netlist::PresentDesign());
+						}
+					}
 #endif
 #endif
 				}

From e2e189647f36dd3609711c233d6febebf2a7a8f3 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 10 Jun 2024 10:12:33 +0200
Subject: [PATCH 156/499] Cleanup

---
 frontends/verific/verific.cc | 17 ++++++-----------
 1 file changed, 6 insertions(+), 11 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 84fc834eae4..0c575685f0c 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -84,10 +84,6 @@ USING_YOSYS_NAMESPACE
 #endif
 #endif
 
-#ifndef DB_PRESERVE_INITIAL_VALUE
-#error "Verific must have DB_PRESERVE_INITIAL_VALUE compile flag set on"
-#endif
-
 #ifdef __clang__
 #pragma clang diagnostic pop
 #endif
@@ -2700,12 +2696,13 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 
 	std::map<std::string,Netlist*> nl_todo, nl_done;
 	Array *netlists = NULL;
-	Array veri_libs, vhdl_libs;
 #ifdef VERIFIC_VHDL_SUPPORT
+	Array vhdl_libs;
 	VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1);
 	if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);
 #endif
 #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+	Array veri_libs;
 	VeriLibrary *veri_lib = veri_file::GetLibrary("work", 1);
 	if (veri_lib) veri_libs.InsertLast(veri_lib);
 #endif
@@ -3901,17 +3898,15 @@ struct VerificPass : public Pass {
 					verific_sva_fsm_limit = atoi(args[++argidx].c_str());
 					continue;
 				}
-#endif
-				if (args[argidx] == "-n") {
-					mode_names = true;
-					continue;
-				}
-#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 				if (args[argidx] == "-autocover") {
 					mode_autocover = true;
 					continue;
 				}
 #endif
+				if (args[argidx] == "-n") {
+					mode_names = true;
+					continue;
+				}
 				if (args[argidx] == "-fullinit") {
 					mode_fullinit = true;
 					continue;

From 7c3094633d7f928909984127be875dfa33ba60b5 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 11 Jun 2024 07:48:26 +0200
Subject: [PATCH 157/499] Compile with hier_tree separate SV and VHDL as well

---
 frontends/verific/verific.cc | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 0c575685f0c..39e96883703 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2696,13 +2696,13 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 
 	std::map<std::string,Netlist*> nl_todo, nl_done;
 	Array *netlists = NULL;
-#ifdef VERIFIC_VHDL_SUPPORT
 	Array vhdl_libs;
+#ifdef VERIFIC_VHDL_SUPPORT
 	VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1);
 	if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);
 #endif
-#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 	Array veri_libs;
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 	VeriLibrary *veri_lib = veri_file::GetLibrary("work", 1);
 	if (veri_lib) veri_libs.InsertLast(veri_lib);
 #endif
@@ -2748,9 +2748,8 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 		for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--)
 #endif
 		{
-#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 			Array veri_modules;
-
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 			if (veri_lib) {
 				VeriModule *veri_module = veri_lib->GetModule(top.c_str(), 1);
 				if (veri_module) {
@@ -2783,8 +2782,8 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 			}
 #endif
 
-#ifdef VERIFIC_VHDL_SUPPORT
 			Array vhdl_units;
+#ifdef VERIFIC_VHDL_SUPPORT
 			if (vhdl_lib) {
 				VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(top.c_str());
 				if (vhdl_unit)
@@ -3965,13 +3964,13 @@ struct VerificPass : public Pass {
 #endif
 				log("Running hier_tree::ElaborateAll().\n");
 
-#ifdef VERIFIC_VHDL_SUPPORT
 				Array vhdl_libs;
+#ifdef VERIFIC_VHDL_SUPPORT
 				VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
 				if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);
 #endif
-#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 				Array veri_libs;
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 				VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1);
 				if (veri_lib) veri_libs.InsertLast(veri_lib);
 #endif
@@ -4018,12 +4017,12 @@ struct VerificPass : public Pass {
 #endif
 				{
 
-#ifdef VERIFIC_VHDL_SUPPORT
 					Array vhdl_units;
+#ifdef VERIFIC_VHDL_SUPPORT
 					VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
 #endif
-#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 					Array veri_modules;
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 					VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1);
 #endif
 					for (int i = argidx; i < GetSize(args); i++)

From 0a81c8e161cd6abb36e3ba4eb5edfc745836a9d5 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 11 Jun 2024 08:26:16 +0200
Subject: [PATCH 158/499] Import all modules from all libraries when when
 needed

---
 frontends/verific/verific.cc | 36 ++++++++++++++++++++++--------------
 1 file changed, 22 insertions(+), 14 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 39e96883703..e7bc242194c 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2731,13 +2731,17 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 		netlists = new Array(1);
 		MapIter mi ;
 		Verific::Cell *c ;
-		Library *l = Libset::Global()->GetLibrary("work");
-		FOREACH_CELL_OF_LIBRARY(l,mi,c) {
-			MapIter ni ;
-			Netlist *nl;
-			FOREACH_NETLIST_OF_CELL(c, ni, nl) {
-				if (nl)
-					netlists->InsertLast(nl);
+		MapIter it ;
+		Library *l ;
+		FOREACH_LIBRARY_OF_LIBSET(Libset::Global(),it,l) {
+			if (l == Library::Primitives() || l == Library::Operators()) continue;
+			FOREACH_CELL_OF_LIBRARY(l,mi,c) {
+				MapIter ni ;
+				Netlist *nl;
+				FOREACH_NETLIST_OF_CELL(c, ni, nl) {
+					if (nl)
+						netlists->InsertLast(nl);
+				}
 			}
 		}
 #endif
@@ -3994,13 +3998,17 @@ struct VerificPass : public Pass {
 #endif
 				MapIter mi ;
 				Verific::Cell *c ;
-				Library *l = Libset::Global()->GetLibrary(work.c_str());
-				FOREACH_CELL_OF_LIBRARY(l,mi,c) {
-					MapIter ni ;
-					Netlist *nl;
-					FOREACH_NETLIST_OF_CELL(c, ni, nl) {
-						if (nl)
-							nl_todo.emplace(nl->CellBaseName(), nl);
+				MapIter it ;
+				Library *l ;
+				FOREACH_LIBRARY_OF_LIBSET(Libset::Global(),it,l) {
+					if (l == Library::Primitives() || l == Library::Operators()) continue;
+					FOREACH_CELL_OF_LIBRARY(l,mi,c) {
+						MapIter ni ;
+						Netlist *nl;
+						FOREACH_NETLIST_OF_CELL(c, ni, nl) {
+							if (nl)
+								nl_todo.emplace(nl->CellBaseName(), nl);
+						}
 					}
 				}
 #endif

From 0f3f731254dd92f2b0e20587639ed4883999eeb3 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 11 Jun 2024 08:57:02 +0200
Subject: [PATCH 159/499] Handle -work for vhdl, and clean messages

---
 frontends/verific/verific.cc | 37 +++++++++++++++++++++++++++++-------
 1 file changed, 30 insertions(+), 7 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index e7bc242194c..0a8d432a31d 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -42,6 +42,8 @@ USING_YOSYS_NAMESPACE
 #pragma clang diagnostic ignored "-Woverloaded-virtual"
 #endif
 
+#include "Array.h"
+#include "RuntimeFlags.h"
 #ifdef VERIFIC_HIER_TREE_SUPPORT
 #include "hier_tree.h"
 #endif
@@ -84,6 +86,10 @@ USING_YOSYS_NAMESPACE
 #endif
 #endif
 
+#if !defined(VERIFIC_VHDL_SUPPORT) && !defined(VERIFIC_SYSTEMVERILOG_SUPPORT)
+#error "At least one of HDL languages must be enabled."
+#endif
+
 #ifdef __clang__
 #pragma clang diagnostic pop
 #endif
@@ -2814,7 +2820,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 			netlists = new Array(1);
 			vhdl_file::Elaborate(top.c_str(), "work", 0, &verific_params);
 			netlists->InsertLast(Netlist::PresentDesign());
-#else
+#elif defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && defined(VERIFIC_VHDL_SUPPORT)
 			// Both SystemVerilog and VHDL support
 			if (veri_modules.Size()>0)
 				netlists = veri_file::ElaborateMultipleTop(&veri_modules, &verific_params);
@@ -2824,6 +2830,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 				vhdl_file::Elaborate(top.c_str(), "work", 0, &verific_params);
 				netlists->InsertLast(Netlist::PresentDesign());
 			}
+#else
 #endif
 #endif
 		}
@@ -3452,6 +3459,7 @@ struct VerificPass : public Pass {
 		}
 
 		veri_file::RemoveAllLOptions();
+#endif
 		for (int i = argidx; i < GetSize(args); i++)
 		{
 			if (args[i] == "-work" && i+1 < GetSize(args)) {
@@ -3459,24 +3467,30 @@ struct VerificPass : public Pass {
 				is_work_set = true;
 				continue;
 			}
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 			if (args[i] == "-L" && i+1 < GetSize(args)) {
 				++i;
 				continue;
 			}
+#endif
 			break;
 		}
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		veri_file::AddLOption(work.c_str());
+#endif
 		for (int i = argidx; i < GetSize(args); i++)
 		{
 			if (args[i] == "-work" && i+1 < GetSize(args)) {
 				++i;
 				continue;
 			}
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 			if (args[i] == "-L" && i+1 < GetSize(args)) {
 				if (args[++i] == work)
 					veri_file::RemoveAllLOptions();
 				continue;
 			}
+#endif
 			break;
 		}
 		for (; argidx < GetSize(args); argidx++)
@@ -3486,13 +3500,16 @@ struct VerificPass : public Pass {
 				is_work_set = true;
 				continue;
 			}
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 			if (args[argidx] == "-L" && argidx+1 < GetSize(args)) {
 				veri_file::AddLOption(args[++argidx].c_str());
 				continue;
 			}
+#endif
 			break;
 		}
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F"))
 		{
 			unsigned verilog_mode = veri_file::UNDEFINED;
@@ -3966,8 +3983,6 @@ struct VerificPass : public Pass {
 				if (!ppfile.empty())
 					veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str());
 #endif
-				log("Running hier_tree::ElaborateAll().\n");
-
 				Array vhdl_libs;
 #ifdef VERIFIC_VHDL_SUPPORT
 				VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
@@ -3980,6 +3995,7 @@ struct VerificPass : public Pass {
 #endif
 
 #ifdef VERIFIC_HIER_TREE_SUPPORT
+				log("Running hier_tree::ElaborateAll().\n");
 				Array *netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &parameters);
 				Netlist *nl;
 				int i;
@@ -3991,9 +4007,11 @@ struct VerificPass : public Pass {
 				if (parameters.Size())
 					log_warning("Please note that parameters are not propagated during import.\n");
 #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+				log("Running veri_file::ElaborateAll().\n");
 				veri_file::ElaborateAll(work.c_str());
 #endif
 #ifdef VERIFIC_VHDL_SUPPORT
+				log("Running vhdl_file::ElaborateAll().\n");
 				vhdl_file::ElaborateAll(work.c_str());
 #endif
 				MapIter mi ;
@@ -4107,32 +4125,37 @@ struct VerificPass : public Pass {
 						}
 					}
 #endif
-					log("Running hier_tree::Elaborate().\n");
 #ifdef VERIFIC_HIER_TREE_SUPPORT
+					log("Running hier_tree::Elaborate().\n");
 					netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &parameters);
 #else
 #if defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && !defined(VERIFIC_VHDL_SUPPORT)
+					log("Running veri_file::ElaborateMultipleTop().\n");
 					// SystemVerilog support only
 					netlists = veri_file::ElaborateMultipleTop(&veri_modules, &parameters);
 #elif defined(VERIFIC_VHDL_SUPPORT) && !defined(VERIFIC_SYSTEMVERILOG_SUPPORT)
+					log("Running vhdl_file::Elaborate().\n");
 					// VHDL support	only
 					netlists = new Array(top_mod_names.size());
 					for (auto &name : top_mod_names) {
 						vhdl_file::Elaborate(name.c_str(), work.c_str(), 0, &parameters);
 						netlists->InsertLast(Netlist::PresentDesign());
 					}
-#else
+#elif defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && defined(VERIFIC_VHDL_SUPPORT)
 					// Both SystemVerilog and VHDL support
-					if (veri_modules.Size()>0)
+					if (veri_modules.Size()>0) {
+						log("Running veri_file::ElaborateMultipleTop().\n");
 						netlists = veri_file::ElaborateMultipleTop(&veri_modules, &parameters);
-					else
+					} else
 						netlists = new Array(1);
 					if (vhdl_units.Size()>0) {
+						log("Running vhdl_file::Elaborate().\n");
 						for (auto &name : top_mod_names) {
 							vhdl_file::Elaborate(name.c_str(), work.c_str(), 0, &parameters);
 							netlists->InsertLast(Netlist::PresentDesign());
 						}
 					}
+#else
 #endif
 #endif
 				}

From 19da7f7d59fd3c01f677631652c695815208da86 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 11 Jun 2024 15:32:16 +0200
Subject: [PATCH 160/499] Update makefile to make options uniform

---
 Makefile                       | 20 ++++++++++++--------
 frontends/verific/Makefile.inc |  2 +-
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/Makefile b/Makefile
index 0712e987bf1..b86eb4bfa65 100644
--- a/Makefile
+++ b/Makefile
@@ -17,12 +17,12 @@ ENABLE_READLINE := 1
 ENABLE_EDITLINE := 0
 ENABLE_GHDL := 0
 ENABLE_VERIFIC := 0
+ENABLE_VERIFIC_SYSTEMVERILOG := 1
+ENABLE_VERIFIC_VHDL := 1
+ENABLE_VERIFIC_HIER_TREE := 1
+ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1
 ENABLE_VERIFIC_EDIF := 0
 ENABLE_VERIFIC_LIBERTY := 0
-DISABLE_VERIFIC_EXTENSIONS := 0
-DISABLE_VERIFIC_SYSTEMVERILOG := 0
-DISABLE_VERIFIC_VHDL := 0
-DISABLE_VERIFIC_HIER_TREE := 0
 ENABLE_COVER := 1
 ENABLE_LIBYOSYS := 0
 ENABLE_ZLIB := 1
@@ -474,7 +474,7 @@ LIBS_VERIFIC =
 ifeq ($(ENABLE_VERIFIC),1)
 VERIFIC_DIR ?= /usr/local/src/verific_lib
 VERIFIC_COMPONENTS ?= database util containers
-ifneq ($(DISABLE_VERIFIC_HIER_TREE),1)
+ifeq ($(ENABLE_VERIFIC_HIER_TREE),1)
 VERIFIC_COMPONENTS += hier_tree
 CXXFLAGS += -DVERIFIC_HIER_TREE_SUPPORT
 else
@@ -482,7 +482,7 @@ ifneq ($(wildcard $(VERIFIC_DIR)/hier_tree),)
 VERIFIC_COMPONENTS += hier_tree
 endif
 endif
-ifneq ($(DISABLE_VERIFIC_SYSTEMVERILOG),1)
+ifeq ($(ENABLE_VERIFIC_SYSTEMVERILOG),1)
 VERIFIC_COMPONENTS += verilog
 CXXFLAGS += -DVERIFIC_SYSTEMVERILOG_SUPPORT
 else
@@ -490,7 +490,7 @@ ifneq ($(wildcard $(VERIFIC_DIR)/verilog),)
 VERIFIC_COMPONENTS += verilog
 endif
 endif
-ifneq ($(DISABLE_VERIFIC_VHDL),1)
+ifeq ($(ENABLE_VERIFIC_VHDL),1)
 VERIFIC_COMPONENTS += vhdl
 CXXFLAGS += -DVERIFIC_VHDL_SUPPORT
 else
@@ -506,9 +506,13 @@ ifeq ($(ENABLE_VERIFIC_LIBERTY),1)
 VERIFIC_COMPONENTS += synlib
 CXXFLAGS += -DVERIFIC_LIBERTY_SUPPORT
 endif
-ifneq ($(DISABLE_VERIFIC_EXTENSIONS),1)
+ifeq ($(ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS),1)
 VERIFIC_COMPONENTS += extensions
 CXXFLAGS += -DYOSYSHQ_VERIFIC_EXTENSIONS
+else
+ifneq ($(wildcard $(VERIFIC_DIR)/extensions),)
+VERIFIC_COMPONENTS += extensions
+endif
 endif
 CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC
 ifeq ($(OS), Darwin)
diff --git a/frontends/verific/Makefile.inc b/frontends/verific/Makefile.inc
index df3ac8d2d43..0766240a4a4 100644
--- a/frontends/verific/Makefile.inc
+++ b/frontends/verific/Makefile.inc
@@ -10,7 +10,7 @@ EXTRA_TARGETS += share/verific
 share/verific:
 	$(P) rm -rf share/verific.new
 	$(Q) mkdir -p share/verific.new
-ifneq ($(DISABLE_VERIFIC_VHDL),1)
+ifeq ($(ENABLE_VERIFIC_VHDL),1)
 	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1987/. share/verific.new/vhdl_vdbs_1987
 	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1993/. share/verific.new/vhdl_vdbs_1993
 	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2008/. share/verific.new/vhdl_vdbs_2008

From dfde792288fd9e42bd101c56a81699abc2c450af Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 17 Jun 2024 14:49:58 +0200
Subject: [PATCH 161/499] Refactored import code

---
 frontends/verific/verific.cc | 529 +++++++++++++----------------------
 1 file changed, 198 insertions(+), 331 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 0a8d432a31d..56e94489cba 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2696,183 +2696,217 @@ struct VerificExtNets
 	}
 };
 
-std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top)
+void import_all(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED)
 {
-	verific_sva_fsm_limit = 16;
+#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
+	VerificExtensions::ElaborateAndRewrite(work, parameters);
+	verific_error_msg.clear();
+#endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+	if (!ppfile.empty())
+		veri_file::PrettyPrint(ppfile.c_str(), nullptr, work);
+#endif
 
-	std::map<std::string,Netlist*> nl_todo, nl_done;
-	Array *netlists = NULL;
 	Array vhdl_libs;
 #ifdef VERIFIC_VHDL_SUPPORT
-	VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1);
+	VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work, 1);
 	if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);
 #endif
 	Array veri_libs;
 #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
-	VeriLibrary *veri_lib = veri_file::GetLibrary("work", 1);
+	VeriLibrary *veri_lib = veri_file::GetLibrary(work, 1);
 	if (veri_lib) veri_libs.InsertLast(veri_lib);
 #endif
 
-	Map verific_params(STRING_HASH);
-	for (const auto &i : parameters)
-		verific_params.Insert(i.first.c_str(), i.second.c_str());
-
-	if (top.empty()) {
-
-#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
-		VerificExtensions::ElaborateAndRewrite("work", &verific_params);
-		verific_error_msg.clear();
-#endif
 #ifdef VERIFIC_HIER_TREE_SUPPORT
-		netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &verific_params);
+	if (show_message)
+		log("Running hier_tree::ElaborateAll().\n");
+	Array *netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, parameters);
+	Netlist *nl;
+	int i;
+
+	FOREACH_ARRAY_ITEM(netlists, i, nl)
+		nl_todo->emplace(nl->CellBaseName(), nl);
+	delete netlists;
 #else
-		if (parameters.size())
-			log_warning("Please note that parameters are not propagated during import.\n");
+	if (parameters->Size())
+		log_warning("Please note that parameters are not propagated during import.\n");
 #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
-		veri_file::ElaborateAll("work");
+	if (show_message)
+		log("Running veri_file::ElaborateAll().\n");
+	veri_file::ElaborateAll(work);
 #endif
 #ifdef VERIFIC_VHDL_SUPPORT
-		vhdl_file::ElaborateAll("work");
+	if (show_message)
+		log("Running vhdl_file::ElaborateAll().\n");
+	vhdl_file::ElaborateAll(work);
 #endif
-		netlists = new Array(1);
-		MapIter mi ;
-		Verific::Cell *c ;
-		MapIter it ;
-		Library *l ;
-		FOREACH_LIBRARY_OF_LIBSET(Libset::Global(),it,l) {
-			if (l == Library::Primitives() || l == Library::Operators()) continue;
-			FOREACH_CELL_OF_LIBRARY(l,mi,c) {
-				MapIter ni ;
-				Netlist *nl;
-				FOREACH_NETLIST_OF_CELL(c, ni, nl) {
-					if (nl)
-						netlists->InsertLast(nl);
-				}
+	MapIter mi ;
+	Verific::Cell *c ;
+	MapIter it ;
+	Library *l ;
+	FOREACH_LIBRARY_OF_LIBSET(Libset::Global(),it,l) {
+		if (l == Library::Primitives() || l == Library::Operators()) continue;
+		FOREACH_CELL_OF_LIBRARY(l,mi,c) {
+			MapIter ni ;
+			Netlist *nl;
+			FOREACH_NETLIST_OF_CELL(c, ni, nl) {
+				if (nl)
+					nl_todo->emplace(nl->CellBaseName(), nl);
 			}
 		}
-#endif
 	}
-	else {
+#endif
+}
+
+std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED, std::vector<std::string> &tops)
+{
+	std::set<std::string> top_mod_names;
+	Array *netlists = nullptr;
+
+#ifdef VERIFIC_VHDL_SUPPORT
+	VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work, 1);
+#endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+	VeriLibrary* veri_lib = veri_file::GetLibrary(work, 1);
+#endif
 
 #ifdef YOSYSHQ_VERIFIC_EXTENSIONS
-		for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--)
+	for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--)
 #endif
+	{
+		Array vhdl_units;
+		Array veri_modules;
+		for (std::string n : tops)
 		{
-			Array veri_modules;
+			const char *name = n.c_str();
+			top_mod_names.insert(name);
+
 #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
-			if (veri_lib) {
-				VeriModule *veri_module = veri_lib->GetModule(top.c_str(), 1);
-				if (veri_module) {
+			VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr;
+			if (veri_module) {
+				if (veri_module->IsConfiguration()) {
+					if (show_message)
+						log("Adding Verilog configuration '%s' to elaboration queue.\n", name);
 					veri_modules.InsertLast(veri_module);
-					if (veri_module->IsConfiguration()) {
-						VeriConfiguration *cfg = (VeriConfiguration*)veri_module;
-						VeriName *module_name = (VeriName*)cfg->GetTopModuleNames()->GetLast();
+					top_mod_names.erase(name);
+					VeriConfiguration *cfg = (VeriConfiguration*)veri_module;
+					VeriName *module_name;
+					int i;
+					FOREACH_ARRAY_ITEM(cfg->GetTopModuleNames(), i, module_name) {
 						VeriLibrary *lib = veri_module->GetLibrary() ;
 						if (module_name && module_name->IsHierName()) {
 							VeriName *prefix = module_name->GetPrefix() ;
 							const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
-							if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ;
+							if (work != lib_name) lib = veri_file::GetLibrary(lib_name, 1) ;
 						}
 						if (lib && module_name)
-							top = lib->GetModule(module_name->GetName(), 1)->GetName();
-					}
-				}
-
-#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
-				if (!static_elaborate)
-#endif
-				{
-					// Also elaborate all root modules since they may contain bind statements
-					MapIter mi;
-					FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
-						if (!veri_module->IsRootModule()) continue;
-						veri_modules.InsertLast(veri_module);
+							top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName());
 					}
+				} else {
+					if (show_message)
+						log("Adding Verilog module '%s' to elaboration queue.\n", name);
+					veri_modules.InsertLast(veri_module);
 				}
+			continue;
 			}
 #endif
-
-			Array vhdl_units;
 #ifdef VERIFIC_VHDL_SUPPORT
-			if (vhdl_lib) {
-				VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(top.c_str());
-				if (vhdl_unit)
-					vhdl_units.InsertLast(vhdl_unit);
+			VhdlDesignUnit *vhdl_unit = vhdl_lib ? vhdl_lib->GetPrimUnit(name) : nullptr;
+			if (vhdl_unit) {
+				if (show_message)
+					log("Adding VHDL unit '%s' to elaboration queue.\n", name);
+				vhdl_units.InsertLast(vhdl_unit);
+				continue;
 			}
 #endif
+			log_error("Can't find module/unit '%s'.\n", name);
+		}
 
 #ifdef YOSYSHQ_VERIFIC_EXTENSIONS
-			if (static_elaborate) {
-				VerificExtensions::ElaborateAndRewrite("work", &veri_modules, &vhdl_units, &verific_params);
-				verific_error_msg.clear();
-				continue;
+		if (static_elaborate) {
+			VerificExtensions::ElaborateAndRewrite(work, &veri_modules, &vhdl_units, parameters);
+			verific_error_msg.clear();
+#endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+			if (!ppfile.empty())
+				veri_file::PrettyPrint(ppfile.c_str(), nullptr, work);
+#endif
+#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
+			continue;
+		}
+#endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+		const char *lib_name = nullptr;
+		SetIter si;
+		FOREACH_SET_ITEM(veri_file::GetAllLOptions(), si, &lib_name) {
+			VeriLibrary* veri_lib = veri_file::GetLibrary(lib_name, 0);
+			if (veri_lib) {
+				// Also elaborate all root modules since they may contain bind statements
+				MapIter mi;
+				VeriModule *veri_module;
+				FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
+					if (!veri_module->IsRootModule()) continue;
+					veri_modules.InsertLast(veri_module);
+				}
 			}
+		}
 #endif
-
 #ifdef VERIFIC_HIER_TREE_SUPPORT
-			netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params);
+		if (show_message)
+			log("Running hier_tree::Elaborate().\n");
+		netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, parameters);
 #else
 #if defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && !defined(VERIFIC_VHDL_SUPPORT)
-			// SystemVerilog support only
-			netlists = veri_file::ElaborateMultipleTop(&veri_modules, &verific_params);
+		if (show_message)
+			log("Running veri_file::ElaborateMultipleTop().\n");
+		// SystemVerilog support only
+		netlists = veri_file::ElaborateMultipleTop(&veri_modules, parameters);
 #elif defined(VERIFIC_VHDL_SUPPORT) && !defined(VERIFIC_SYSTEMVERILOG_SUPPORT)
-			// VHDL support	only
-			netlists = new Array(1);
-			vhdl_file::Elaborate(top.c_str(), "work", 0, &verific_params);
+		if (show_message)
+			log("Running vhdl_file::Elaborate().\n");
+		// VHDL support	only
+		netlists = new Array(top_mod_names.size());
+		for (auto &name : top_mod_names) {
+			vhdl_file::Elaborate(name.c_str(), work, 0, parameters);
 			netlists->InsertLast(Netlist::PresentDesign());
+		}
 #elif defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && defined(VERIFIC_VHDL_SUPPORT)
-			// Both SystemVerilog and VHDL support
-			if (veri_modules.Size()>0)
-				netlists = veri_file::ElaborateMultipleTop(&veri_modules, &verific_params);
-			else
-				netlists = new Array(1);
-			if (vhdl_units.Size()>0) {
-				vhdl_file::Elaborate(top.c_str(), "work", 0, &verific_params);
+		// Both SystemVerilog and VHDL support
+		if (veri_modules.Size()>0) {
+			if (show_message)
+				log("Running veri_file::ElaborateMultipleTop().\n");
+			netlists = veri_file::ElaborateMultipleTop(&veri_modules, parameters);
+		} else
+			netlists = new Array(1);
+		if (vhdl_units.Size()>0) {
+			if (show_message)
+				log("Running vhdl_file::Elaborate().\n");
+			for (auto &name : top_mod_names) {
+				vhdl_file::Elaborate(name.c_str(), work, 0, parameters);
 				netlists->InsertLast(Netlist::PresentDesign());
 			}
+		}
 #else
 #endif
 #endif
-		}
 	}
-
 	Netlist *nl;
 	int i;
-	std::string cell_name = top;
 
 	FOREACH_ARRAY_ITEM(netlists, i, nl) {
 		if (!nl) continue;
-		if (!top.empty() && nl->CellBaseName() != top)
+		if (!top_mod_names.count(nl->CellBaseName()))
 			continue;
 		nl->AddAtt(new Att(" \\top", NULL));
-		nl_todo.emplace(nl->CellBaseName(), nl);
-		cell_name = nl->CellBaseName();
+		nl_todo->emplace(nl->CellBaseName(), nl);
 	}
-	if (top.empty()) cell_name = top;
-
 	delete netlists;
+	return top_mod_names;
+}
 
-	if (!verific_error_msg.empty())
-		log_error("%s\n", verific_error_msg.c_str());
-
-	for (auto nl : nl_todo)
-		nl.second->ChangePortBusStructures(1 /* hierarchical */);
-
-	VerificExtNets worker;
-	for (auto nl : nl_todo)
-		worker.run(nl.second);
-
-	while (!nl_todo.empty()) {
-		auto it = nl_todo.begin();
-		Netlist *nl = it->second;
-		if (nl_done.count(it->first) == 0) {
-			VerificImporter importer(false, false, false, false, false, false, false);
-			nl_done[it->first] = it->second;
-			importer.import_netlist(design, nl, nl_todo, nl->CellBaseName() == cell_name);
-		}
-		nl_todo.erase(it);
-	}
-
+void verific_cleanup()
+{
 #ifdef YOSYSHQ_VERIFIC_EXTENSIONS
 	VerificExtensions::Reset();
 #endif
@@ -2901,7 +2935,53 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 	verific_libexts.clear();
 #endif
 	verific_import_pending = false;
+}
+
+std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top)
+{
+	verific_sva_fsm_limit = 16;
+
+	std::map<std::string,Netlist*> nl_todo, nl_done;
+
+	Map verific_params(STRING_HASH);
+	for (const auto &i : parameters)
+		verific_params.Insert(i.first.c_str(), i.second.c_str());
+
+	std::set<std::string> top_mod_names;
+	if (top.empty()) {
+		import_all("work", &nl_todo, &verific_params, false, "");
+	} else {
+		std::vector<std::string> tops;
+		tops.push_back(top);
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+		veri_file::RemoveAllLOptions();
+		veri_file::AddLOption("work");
+#endif
+		top_mod_names = import_tops("work", &nl_todo, &verific_params, false, "", tops) ;
+	}
 
+	if (!verific_error_msg.empty())
+		log_error("%s\n", verific_error_msg.c_str());
+
+	for (auto nl : nl_todo)
+		nl.second->ChangePortBusStructures(1 /* hierarchical */);
+
+	VerificExtNets worker;
+	for (auto nl : nl_todo)
+		worker.run(nl.second);
+
+	while (!nl_todo.empty()) {
+		auto it = nl_todo.begin();
+		Netlist *nl = it->second;
+		if (nl_done.count(it->first) == 0) {
+			VerificImporter importer(false, false, false, false, false, false, false);
+			nl_done[it->first] = it->second;
+			importer.import_netlist(design, nl, nl_todo, top_mod_names.count(nl->CellBaseName()));
+		}
+		nl_todo.erase(it);
+	}
+
+	verific_cleanup();
 	if (!verific_error_msg.empty())
 		log_error("%s\n", verific_error_msg.c_str());
 	return top;
@@ -3974,203 +4054,17 @@ struct VerificPass : public Pass {
 
 			if (mode_all)
 			{
-
-#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
-				VerificExtensions::ElaborateAndRewrite(work, &parameters);
-				verific_error_msg.clear();
-#endif
-#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
-				if (!ppfile.empty())
-					veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str());
-#endif
-				Array vhdl_libs;
-#ifdef VERIFIC_VHDL_SUPPORT
-				VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
-				if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);
-#endif
-				Array veri_libs;
-#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
-				VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1);
-				if (veri_lib) veri_libs.InsertLast(veri_lib);
-#endif
-
-#ifdef VERIFIC_HIER_TREE_SUPPORT
-				log("Running hier_tree::ElaborateAll().\n");
-				Array *netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &parameters);
-				Netlist *nl;
-				int i;
-
-				FOREACH_ARRAY_ITEM(netlists, i, nl)
-					nl_todo.emplace(nl->CellBaseName(), nl);
-				delete netlists;
-#else
-				if (parameters.Size())
-					log_warning("Please note that parameters are not propagated during import.\n");
-#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
-				log("Running veri_file::ElaborateAll().\n");
-				veri_file::ElaborateAll(work.c_str());
-#endif
-#ifdef VERIFIC_VHDL_SUPPORT
-				log("Running vhdl_file::ElaborateAll().\n");
-				vhdl_file::ElaborateAll(work.c_str());
-#endif
-				MapIter mi ;
-				Verific::Cell *c ;
-				MapIter it ;
-				Library *l ;
-				FOREACH_LIBRARY_OF_LIBSET(Libset::Global(),it,l) {
-					if (l == Library::Primitives() || l == Library::Operators()) continue;
-					FOREACH_CELL_OF_LIBRARY(l,mi,c) {
-						MapIter ni ;
-						Netlist *nl;
-						FOREACH_NETLIST_OF_CELL(c, ni, nl) {
-							if (nl)
-								nl_todo.emplace(nl->CellBaseName(), nl);
-						}
-					}
-				}
-#endif
+				import_all(work.c_str(), &nl_todo, &parameters, true, ppfile);
 			}
 			else
 			{
 				if (argidx == GetSize(args))
 					cmd_error(args, argidx, "No top module specified.\n");
 
-				Array *netlists = nullptr;
-
-#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
-				for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--)
-#endif
-				{
-
-					Array vhdl_units;
-#ifdef VERIFIC_VHDL_SUPPORT
-					VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
-#endif
-					Array veri_modules;
-#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
-					VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1);
-#endif
-					for (int i = argidx; i < GetSize(args); i++)
-					{
-						const char *name = args[i].c_str();
-						top_mod_names.insert(name);
-
-#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
-						VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr;
-						if (veri_module) {
-							if (veri_module->IsConfiguration()) {
-								log("Adding Verilog configuration '%s' to elaboration queue.\n", name);
-								veri_modules.InsertLast(veri_module);
-
-								top_mod_names.erase(name);
-
-								VeriConfiguration *cfg = (VeriConfiguration*)veri_module;
-								VeriName *module_name;
-								int i;
-								FOREACH_ARRAY_ITEM(cfg->GetTopModuleNames(), i, module_name) {
-									VeriLibrary *lib = veri_module->GetLibrary() ;
-									if (module_name && module_name->IsHierName()) {
-										VeriName *prefix = module_name->GetPrefix() ;
-										const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
-										if (work != lib_name) lib = veri_file::GetLibrary(lib_name, 1) ;
-									}
-									if (lib && module_name)
-										top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName());
-								}
-							} else {
-								log("Adding Verilog module '%s' to elaboration queue.\n", name);
-								veri_modules.InsertLast(veri_module);
-							}
-							continue;
-						}
-#endif
-#ifdef VERIFIC_VHDL_SUPPORT
-						VhdlDesignUnit *vhdl_unit = vhdl_lib ? vhdl_lib->GetPrimUnit(name) : nullptr;
-						if (vhdl_unit) {
-							log("Adding VHDL unit '%s' to elaboration queue.\n", name);
-							vhdl_units.InsertLast(vhdl_unit);
-							continue;
-						}
-#endif
-						log_error("Can't find module/unit '%s'.\n", name);
-					}
-
-#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
-					if (static_elaborate) {
-						VerificExtensions::ElaborateAndRewrite(work, &veri_modules, &vhdl_units, &parameters);
-						verific_error_msg.clear();
-#endif
-#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
-						if (!ppfile.empty())
-							veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str());
-#endif
-#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
-						continue;
-					}
-#endif
-#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
-					const char *lib_name = nullptr;
-					SetIter si;
-					FOREACH_SET_ITEM(veri_file::GetAllLOptions(), si, &lib_name) {
-						VeriLibrary* veri_lib = veri_file::GetLibrary(lib_name, 0);
-						if (veri_lib) {
-							// Also elaborate all root modules since they may contain bind statements
-							MapIter mi;
-							VeriModule *veri_module;
-							FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
-								if (!veri_module->IsRootModule()) continue;
-								veri_modules.InsertLast(veri_module);
-							}
-						}
-					}
-#endif
-#ifdef VERIFIC_HIER_TREE_SUPPORT
-					log("Running hier_tree::Elaborate().\n");
-					netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &parameters);
-#else
-#if defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && !defined(VERIFIC_VHDL_SUPPORT)
-					log("Running veri_file::ElaborateMultipleTop().\n");
-					// SystemVerilog support only
-					netlists = veri_file::ElaborateMultipleTop(&veri_modules, &parameters);
-#elif defined(VERIFIC_VHDL_SUPPORT) && !defined(VERIFIC_SYSTEMVERILOG_SUPPORT)
-					log("Running vhdl_file::Elaborate().\n");
-					// VHDL support	only
-					netlists = new Array(top_mod_names.size());
-					for (auto &name : top_mod_names) {
-						vhdl_file::Elaborate(name.c_str(), work.c_str(), 0, &parameters);
-						netlists->InsertLast(Netlist::PresentDesign());
-					}
-#elif defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && defined(VERIFIC_VHDL_SUPPORT)
-					// Both SystemVerilog and VHDL support
-					if (veri_modules.Size()>0) {
-						log("Running veri_file::ElaborateMultipleTop().\n");
-						netlists = veri_file::ElaborateMultipleTop(&veri_modules, &parameters);
-					} else
-						netlists = new Array(1);
-					if (vhdl_units.Size()>0) {
-						log("Running vhdl_file::Elaborate().\n");
-						for (auto &name : top_mod_names) {
-							vhdl_file::Elaborate(name.c_str(), work.c_str(), 0, &parameters);
-							netlists->InsertLast(Netlist::PresentDesign());
-						}
-					}
-#else
-#endif
-#endif
-				}
-
-				Netlist *nl;
-				int i;
-
-				FOREACH_ARRAY_ITEM(netlists, i, nl) {
-					if (!nl) continue;
-					if (!top_mod_names.count(nl->CellBaseName()))
-						continue;
-					nl->AddAtt(new Att(" \\top", NULL));
-					nl_todo.emplace(nl->CellBaseName(), nl);
-				}
-				delete netlists;
+				std::vector<std::string> tops;
+				for (int i = argidx; i < GetSize(args); i++)
+					tops.push_back(args[i].c_str());
+				top_mod_names = import_tops(work.c_str(), &nl_todo, &parameters, true, ppfile, tops) ;
 			}
 			if (mode_cells) {
 				log("Importing all cells.\n");
@@ -4232,34 +4126,7 @@ struct VerificPass : public Pass {
 				nl_todo.erase(it);
 			}
 
-#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
-			VerificExtensions::Reset();
-#endif
-#ifdef VERIFIC_HIER_TREE_SUPPORT
-			hier_tree::DeleteHierarchicalTree();
-#endif
-#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
-			veri_file::Reset();
-#endif
-#ifdef VERIFIC_VHDL_SUPPORT
-			vhdl_file::Reset();
-#endif
-#ifdef VERIFIC_EDIF_SUPPORT
-			edif_file::Reset();
-#endif
-#ifdef VERIFIC_LIBERTY_SUPPORT
-			synlib_file::Reset();
-#endif
-			Libset::Reset();
-			Message::Reset();
-			RuntimeFlags::DeleteAllFlags();
-			LineFile::DeleteAllLineFiles();
-#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
-			verific_incdirs.clear();
-			verific_libdirs.clear();
-			verific_libexts.clear();
-#endif
-			verific_import_pending = false;
+			verific_cleanup();
 			goto check_error;
 		}
 

From 141a2e36389795b3e6e9cae82c8639843446c4db Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 17 Jun 2024 16:55:36 +0200
Subject: [PATCH 162/499] Make C++17 compiler required

---
 .github/workflows/test-compile.yml | 4 ++--
 Makefile                           | 4 ++--
 kernel/yosys_common.h              | 6 +-----
 3 files changed, 5 insertions(+), 9 deletions(-)

diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml
index 375ea7fc54a..a892c91ceca 100644
--- a/.github/workflows/test-compile.yml
+++ b/.github/workflows/test-compile.yml
@@ -64,11 +64,11 @@ jobs:
           $CXX --version
 
       # minimum standard
-      - name: Build C++11
+      - name: Build C++17
         shell: bash
         run: |
           make config-$CC_SHORT
-          make -j$procs CXXSTD=c++11 compile-only
+          make -j$procs CXXSTD=c++17 compile-only
 
       # maximum standard, only on newest compilers
       - name: Build C++20
diff --git a/Makefile b/Makefile
index 7760cec43a2..73ea0bcc1fd 100644
--- a/Makefile
+++ b/Makefile
@@ -90,7 +90,7 @@ all: top-all
 YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST)))
 VPATH := $(YOSYS_SRC)
 
-CXXSTD ?= c++11
+CXXSTD ?= c++17
 CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include
 LIBS := $(LIBS) -lstdc++ -lm
 PLUGIN_LINKFLAGS :=
@@ -1015,7 +1015,7 @@ qtcreator:
 vcxsrc: $(GENFILES) $(EXTRA_TARGETS)
 	rm -rf yosys-win32-vcxsrc-$(YOSYS_VER){,.zip}
 	set -e; for f in `ls $(filter %.cc %.cpp,$(GENFILES)) $(addsuffix .cc,$(basename $(OBJS))) $(addsuffix .cpp,$(basename $(OBJS))) 2> /dev/null`; do \
-		echo "Analyse: $$f" >&2; cpp -std=c++11 -MM -I. -D_YOSYS_ $$f; done | sed 's,.*:,,; s,//*,/,g; s,/[^/]*/\.\./,/,g; y, \\,\n\n,;' | grep '^[^/]' | sort -u | grep -v kernel/version_ > srcfiles.txt
+		echo "Analyse: $$f" >&2; cpp -std=c++17 -MM -I. -D_YOSYS_ $$f; done | sed 's,.*:,,; s,//*,/,g; s,/[^/]*/\.\./,/,g; y, \\,\n\n,;' | grep '^[^/]' | sort -u | grep -v kernel/version_ > srcfiles.txt
 	bash misc/create_vcxsrc.sh yosys-win32-vcxsrc $(YOSYS_VER) $(GIT_REV)
 	echo "namespace Yosys { extern const char *yosys_version_str; const char *yosys_version_str=\"Yosys (Version Information Unavailable)\"; }" > kernel/version.cc
 	zip yosys-win32-vcxsrc-$(YOSYS_VER)/genfiles.zip $(GENFILES) kernel/version.cc
diff --git a/kernel/yosys_common.h b/kernel/yosys_common.h
index 9f1bc2f58d7..56d2356b102 100644
--- a/kernel/yosys_common.h
+++ b/kernel/yosys_common.h
@@ -142,12 +142,8 @@ extern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *p
 
 #if __cplusplus >= 201703L
 #  define YS_FALLTHROUGH [[fallthrough]];
-#elif defined(__clang__)
-#  define YS_FALLTHROUGH [[clang::fallthrough]];
-#elif defined(__GNUC__)
-#  define YS_FALLTHROUGH [[gnu::fallthrough]];
 #else
-#  define YS_FALLTHROUGH
+#  error "C++17 or later compatible compiler is required"
 #endif
 
 

From f9b7b8fff0cf72c293a26818734dd41853a1e511 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Mon, 17 Jun 2024 17:08:13 +0200
Subject: [PATCH 163/499] Update documentation for C++17 switch

---
 README.md                                    | 2 +-
 docs/source/getting_started/installation.rst | 2 +-
 docs/source/yosys_internals/index.rst        | 2 +-
 guidelines/CodingStyle                       | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/README.md b/README.md
index 4647efbe9d1..bb1c4d443e4 100644
--- a/README.md
+++ b/README.md
@@ -71,7 +71,7 @@ Many Linux distributions also provide Yosys binaries, some more up to date than
 Building from Source
 ====================
 
-You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
+You need a C++ compiler with C++17 support (up-to-date CLANG or GCC is
 recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
 TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile).
 Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.
diff --git a/docs/source/getting_started/installation.rst b/docs/source/getting_started/installation.rst
index 4dd5244b912..1a89886089b 100644
--- a/docs/source/getting_started/installation.rst
+++ b/docs/source/getting_started/installation.rst
@@ -84,7 +84,7 @@ not regularly tested:
 Build prerequisites
 ^^^^^^^^^^^^^^^^^^^
 
-A C++ compiler with C++11 support is required as well as some standard tools
+A C++ compiler with C++17 support is required as well as some standard tools
 such as GNU Flex, GNU Bison, Make and Python.  Some additional tools: readline,
 libffi, Tcl and zlib; are optional but enabled by default (see
 :makevar:`ENABLE_*` settings in Makefile). Graphviz and Xdot are used by the
diff --git a/docs/source/yosys_internals/index.rst b/docs/source/yosys_internals/index.rst
index b04f136995d..efd865623b0 100644
--- a/docs/source/yosys_internals/index.rst
+++ b/docs/source/yosys_internals/index.rst
@@ -25,7 +25,7 @@ wide range of real-world designs, including the `OpenRISC 1200 CPU`_, the
 
 .. _k68 CPU: http://opencores.org/projects/k68
 
-Yosys is written in C++, targeting C++11 at minimum. This chapter describes some
+Yosys is written in C++, targeting C++17 at minimum. This chapter describes some
 of the fundamental Yosys data structures. For the sake of simplicity the C++
 type names used in the Yosys implementation are used in this chapter, even
 though the chapter only explains the conceptual idea behind it and can be used
diff --git a/guidelines/CodingStyle b/guidelines/CodingStyle
index 8a3df2d62e8..491507cdd48 100644
--- a/guidelines/CodingStyle
+++ b/guidelines/CodingStyle
@@ -25,7 +25,7 @@ Formatting of code
 C++ Language
 -------------
 
-Yosys is written in C++11.
+Yosys is written in C++17.
 
 In general Yosys uses "int" instead of "size_t". To avoid compiler
 warnings for implicit type casts, always use "GetSize(foobar)" instead

From 2bbf3112d998635930584dc7113755a12f1be27e Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 17 Jun 2024 17:29:20 +0200
Subject: [PATCH 164/499] Update VS build to C++17 build

---
 misc/create_vcxsrc.sh | 1 +
 1 file changed, 1 insertion(+)

diff --git a/misc/create_vcxsrc.sh b/misc/create_vcxsrc.sh
index eee215015b5..5f8b35e8075 100644
--- a/misc/create_vcxsrc.sh
+++ b/misc/create_vcxsrc.sh
@@ -30,6 +30,7 @@ popd
 	tail -n +$((n+1)) "$vcxsrc"/YosysVS/YosysVS.vcxproj
 } > "$vcxsrc"/YosysVS/YosysVS.vcxproj.new
 
+sed -i 's,</AdditionalIncludeDirectories>,</AdditionalIncludeDirectories>\n      <LanguageStandard>stdcpp17</LanguageStandard>\n      <AdditionalOptions>/Zc:__cplusplus %(AdditionalOptions)</AdditionalOptions>,g' "$vcxsrc"/YosysVS/YosysVS.vcxproj.new
 mv "$vcxsrc"/YosysVS/YosysVS.vcxproj.new "$vcxsrc"/YosysVS/YosysVS.vcxproj
 
 mkdir -p "$vcxsrc"/yosys

From ede3750a6c8c178cabe8595155cf48e82725f222 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Wed, 19 Jun 2024 00:17:13 +0000
Subject: [PATCH 165/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index b86eb4bfa65..583c0e05e97 100644
--- a/Makefile
+++ b/Makefile
@@ -143,7 +143,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.42+15
+YOSYS_VER := 0.42+28
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 22d8df1e7e08994bef3d67bac144001397b95c2f Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 10 Jun 2024 16:29:11 +0200
Subject: [PATCH 166/499] liberty: Support for IO liberty files for
 verification

Signed-off-by: gatecat <gatecat@ds0.me>
---
 frontends/liberty/liberty.cc | 38 ++++++++++++++++++++++++++----------
 1 file changed, 28 insertions(+), 10 deletions(-)

diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index cadbcaee69f..86bb4c7dcd4 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -214,6 +214,18 @@ static RTLIL::SigSpec parse_func_expr(RTLIL::Module *module, const char *expr)
 	return stack.back().sig;
 }
 
+static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func, const char *three_state_expr)
+{
+	RTLIL::SigSpec three_state = parse_func_expr(module, three_state_expr);
+
+	RTLIL::Cell *cell = module->addCell(NEW_ID, ID($tribuf));
+	cell->setParam(ID::WIDTH, GetSize(func));
+	cell->setPort(ID::A, func);
+	cell->setPort(ID::EN, create_inv_cell(module, three_state));
+	cell->setPort(ID::Y, module->addWire(NEW_ID));
+	return cell->getPort(ID::Y);
+}
+
 static void create_ff(RTLIL::Module *module, LibertyAst *node)
 {
 	RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0))));
@@ -695,18 +707,24 @@ struct LibertyFrontend : public Frontend {
 					LibertyAst *func = node->find("function");
 					if (func == NULL)
 					{
-						if (!flag_ignore_miss_func)
-						{
-							log_error("Missing function on output %s of cell %s.\n", log_id(wire->name), log_id(module->name));
-						} else {
-							log("Ignoring cell %s with missing function on output %s.\n", log_id(module->name), log_id(wire->name));
-							delete module;
-							goto skip_cell;
+						if (dir->value != "inout") { // allow inout with missing function, can be used for power pins
+							if (!flag_ignore_miss_func)
+							{
+								log_error("Missing function on output %s of cell %s.\n", log_id(wire->name), log_id(module->name));
+							} else {
+								log("Ignoring cell %s with missing function on output %s.\n", log_id(module->name), log_id(wire->name));
+								delete module;
+								goto skip_cell;
+							}
+						}
+					} else {
+						RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str());
+						LibertyAst *three_state = node->find("three_state");
+						if (three_state) {
+							out_sig = create_tristate(module, out_sig, three_state->value.c_str());
 						}
+						module->connect(RTLIL::SigSig(wire, out_sig));
 					}
-
-					RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str());
-					module->connect(RTLIL::SigSig(wire, out_sig));
 				}
 			}
 

From 6c8ae44ae7ebe5cbad7cfaf2d0934701e29c9527 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Thu, 20 Jun 2024 00:17:08 +0000
Subject: [PATCH 167/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 583c0e05e97..d2c56e9797b 100644
--- a/Makefile
+++ b/Makefile
@@ -143,7 +143,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.42+28
+YOSYS_VER := 0.42+30
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 89d939334eab09b8dd7baea71b4b23b87345dc7d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Fri, 21 Jun 2024 15:14:08 +0200
Subject: [PATCH 168/499] rtlil: Fix `addShiftx` for signed shifts

Only the `B` input (the shift amount) can be marked as signed on a
`$shiftx` cell. Adapt the helper accordingly and prevent it from
creating invalid RTLIL when called with `is_signed` set. Previously
it would mark both `A` and `B` as signed.
---
 kernel/rtlil.cc | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index a6aebaa4258..d3946a620de 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2517,7 +2517,6 @@ DEF_METHOD(Or,       max(sig_a.size(), sig_b.size()), ID($or))
 DEF_METHOD(Xor,      max(sig_a.size(), sig_b.size()), ID($xor))
 DEF_METHOD(Xnor,     max(sig_a.size(), sig_b.size()), ID($xnor))
 DEF_METHOD(Shift,    sig_a.size(), ID($shift))
-DEF_METHOD(Shiftx,   sig_a.size(), ID($shiftx))
 DEF_METHOD(Lt,       1, ID($lt))
 DEF_METHOD(Le,       1, ID($le))
 DEF_METHOD(Eq,       1, ID($eq))
@@ -2562,6 +2561,28 @@ DEF_METHOD(Sshl,     sig_a.size(), ID($sshl))
 DEF_METHOD(Sshr,     sig_a.size(), ID($sshr))
 #undef DEF_METHOD
 
+#define DEF_METHOD(_func, _y_size, _type) \
+	RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
+		RTLIL::Cell *cell = addCell(name, _type);           \
+		cell->parameters[ID::A_SIGNED] = false;             \
+		cell->parameters[ID::B_SIGNED] = is_signed;         \
+		cell->parameters[ID::A_WIDTH] = sig_a.size();       \
+		cell->parameters[ID::B_WIDTH] = sig_b.size();       \
+		cell->parameters[ID::Y_WIDTH] = sig_y.size();       \
+		cell->setPort(ID::A, sig_a);                        \
+		cell->setPort(ID::B, sig_b);                        \
+		cell->setPort(ID::Y, sig_y);                        \
+		cell->set_src_attribute(src);                       \
+		return cell;                                        \
+	} \
+	RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
+		RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size);         \
+		add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
+		return sig_y;                                            \
+	}
+DEF_METHOD(Shiftx,      sig_a.size(), ID($shiftx))
+#undef DEF_METHOD
+
 #define DEF_METHOD(_func, _type, _pmux) \
 	RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
 		RTLIL::Cell *cell = addCell(name, _type);                 \

From 777624ccf582410dbb510849d9bff9b23dae0e82 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 24 Jun 2024 16:08:08 +0200
Subject: [PATCH 169/499] Make yosys-config dependant of Makefile

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 73ea0bcc1fd..858e15a76fc 100644
--- a/Makefile
+++ b/Makefile
@@ -736,7 +736,7 @@ CXXFLAGS_NOVERIFIC = $(CXXFLAGS)
 LIBS_NOVERIFIC = $(LIBS)
 endif
 
-$(PROGRAM_PREFIX)yosys-config: misc/yosys-config.in
+$(PROGRAM_PREFIX)yosys-config: misc/yosys-config.in $(YOSYS_SRC)/Makefile
 	$(P) $(SED) -e 's#@CXXFLAGS@#$(subst -Ilibs/dlfcn-win32,,$(subst -I. -I"$(YOSYS_SRC)",-I"$(DATDIR)/include",$(strip $(CXXFLAGS_NOVERIFIC))))#;' \
 			-e 's#@CXX@#$(strip $(CXX))#;' -e 's#@LINKFLAGS@#$(strip $(LINKFLAGS) $(PLUGIN_LINKFLAGS))#;' -e 's#@LIBS@#$(strip $(LIBS_NOVERIFIC) $(PLUGIN_LIBS))#;' \
 			-e 's#@BINDIR@#$(strip $(BINDIR))#;' -e 's#@DATDIR@#$(strip $(DATDIR))#;' < $< > $(PROGRAM_PREFIX)yosys-config

From 7a8a69b65c6f4fcfa8cebad50dbc037c926e575a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Wed, 31 Jan 2024 13:21:43 +0100
Subject: [PATCH 170/499] opt_expr: Revisit sorting in `replace_const_cells`

Avoid building a cell-to-inbit map when sorting the cells, add a warning
if we are unable to sort, and move the code treating non-combinational
cells ahead of the rest (this means we don't need to pass
non-combinational cells to the TopoSort object at all).
---
 passes/opt/opt_expr.cc | 173 ++++++++++++++++++++---------------------
 1 file changed, 85 insertions(+), 88 deletions(-)

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 3eadd35c6af..b26ffc54263 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -395,18 +395,10 @@ int get_highest_hot_index(RTLIL::SigSpec signal)
 
 void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc, bool noclkinv)
 {
-	CellTypes ct_combinational;
-	ct_combinational.setup_internals();
-	ct_combinational.setup_stdcells();
-
 	SigMap assign_map(module);
 	dict<RTLIL::SigSpec, RTLIL::SigSpec> invert_map;
 
-	TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
-	dict<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
-	dict<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
-
-	for (auto cell : module->cells())
+	for (auto cell : module->cells()) {
 		if (design->selected(module, cell) && cell->type[0] == '$') {
 			if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) &&
 					GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
@@ -414,110 +406,115 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			if (cell->type.in(ID($mux), ID($_MUX_)) &&
 					cell->getPort(ID::A) == SigSpec(State::S1) && cell->getPort(ID::B) == SigSpec(State::S0))
 				invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::S));
-			if (ct_combinational.cell_known(cell->type))
-				for (auto &conn : cell->connections()) {
-					RTLIL::SigSpec sig = assign_map(conn.second);
-					sig.remove_const();
-					if (ct_combinational.cell_input(cell->type, conn.first))
-						cell_to_inbit[cell].insert(sig.begin(), sig.end());
-					if (ct_combinational.cell_output(cell->type, conn.first))
-						for (auto &bit : sig)
-							outbit_to_cell[bit].insert(cell);
-				}
-                        cells.node(cell);
 		}
+	}
 
-        // Build the graph for the topological sort.
-	for (auto &it_right : cell_to_inbit) {
-          const int r_index = cells.node(it_right.first);
-          for (auto &it_sigbit : it_right.second) {
-            for (auto &it_left : outbit_to_cell[it_sigbit]) {
-              const int l_index = cells.node(it_left);
-              cells.edge(l_index, r_index);
-            }
-          }
-        }
+	if (!noclkinv)
+	for (auto cell : module->cells())
+	if (design->selected(module, cell)) {
+		if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2)))
+			handle_polarity_inv(cell, ID::CLK, ID::CLK_POLARITY, assign_map, invert_map);
 
-	cells.sort();
+		if (cell->type.in(ID($sr), ID($dffsr), ID($dffsre), ID($dlatchsr))) {
+			handle_polarity_inv(cell, ID::SET, ID::SET_POLARITY, assign_map, invert_map);
+			handle_polarity_inv(cell, ID::CLR, ID::CLR_POLARITY, assign_map, invert_map);
+		}
 
-	for (auto cell : cells.sorted)
-	{
-#define ACTION_DO(_p_, _s_) do { cover("opt.opt_expr.action_" S__LINE__); replace_cell(assign_map, module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0)
-#define ACTION_DO_Y(_v_) ACTION_DO(ID::Y, RTLIL::SigSpec(RTLIL::State::S ## _v_))
+		if (cell->type.in(ID($adff), ID($adffe), ID($adlatch)))
+			handle_polarity_inv(cell, ID::ARST, ID::ARST_POLARITY, assign_map, invert_map);
 
-		if (!noclkinv)
-		{
-			if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2)))
-				handle_polarity_inv(cell, ID::CLK, ID::CLK_POLARITY, assign_map, invert_map);
+		if (cell->type.in(ID($aldff), ID($aldffe)))
+			handle_polarity_inv(cell, ID::ALOAD, ID::ALOAD_POLARITY, assign_map, invert_map);
 
-			if (cell->type.in(ID($sr), ID($dffsr), ID($dffsre), ID($dlatchsr))) {
-				handle_polarity_inv(cell, ID::SET, ID::SET_POLARITY, assign_map, invert_map);
-				handle_polarity_inv(cell, ID::CLR, ID::CLR_POLARITY, assign_map, invert_map);
-			}
+		if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce)))
+			handle_polarity_inv(cell, ID::SRST, ID::SRST_POLARITY, assign_map, invert_map);
 
-			if (cell->type.in(ID($adff), ID($adffe), ID($adlatch)))
-				handle_polarity_inv(cell, ID::ARST, ID::ARST_POLARITY, assign_map, invert_map);
+		if (cell->type.in(ID($dffe), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr)))
+			handle_polarity_inv(cell, ID::EN, ID::EN_POLARITY, assign_map, invert_map);
 
-			if (cell->type.in(ID($aldff), ID($aldffe)))
-				handle_polarity_inv(cell, ID::ALOAD, ID::ALOAD_POLARITY, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID::S, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_SR_?N_", "$_SR_?P_", ID::R, assign_map, invert_map);
 
-			if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce)))
-				handle_polarity_inv(cell, ID::SRST, ID::SRST_POLARITY, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DFF_N_", "$_DFF_P_", ID::C, assign_map, invert_map);
 
-			if (cell->type.in(ID($dffe), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr)))
-				handle_polarity_inv(cell, ID::EN, ID::EN_POLARITY, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DFFE_N?_", "$_DFFE_P?_", ID::C, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DFFE_?N_", "$_DFFE_?P_", ID::E, assign_map, invert_map);
 
-			handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID::S, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_SR_?N_", "$_SR_?P_", ID::R, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DFF_N??_", "$_DFF_P??_", ID::C, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DFF_?N?_", "$_DFF_?P?_", ID::R, assign_map, invert_map);
 
-			handle_clkpol_celltype_swap(cell, "$_DFF_N_", "$_DFF_P_", ID::C, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DFFE_N???_", "$_DFFE_P???_", ID::C, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DFFE_?N??_", "$_DFFE_?P??_", ID::R, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DFFE_???N_", "$_DFFE_???P_", ID::E, assign_map, invert_map);
 
-			handle_clkpol_celltype_swap(cell, "$_DFFE_N?_", "$_DFFE_P?_", ID::C, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_DFFE_?N_", "$_DFFE_?P_", ID::E, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_SDFF_N??_", "$_SDFF_P??_", ID::C, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_SDFF_?N?_", "$_SDFF_?P?_", ID::R, assign_map, invert_map);
 
-			handle_clkpol_celltype_swap(cell, "$_DFF_N??_", "$_DFF_P??_", ID::C, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_DFF_?N?_", "$_DFF_?P?_", ID::R, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_SDFFE_N???_", "$_SDFFE_P???_", ID::C, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_SDFFE_?N??_", "$_SDFFE_?P??_", ID::R, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_SDFFE_???N_", "$_SDFFE_???P_", ID::E, assign_map, invert_map);
 
-			handle_clkpol_celltype_swap(cell, "$_DFFE_N???_", "$_DFFE_P???_", ID::C, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_DFFE_?N??_", "$_DFFE_?P??_", ID::R, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_DFFE_???N_", "$_DFFE_???P_", ID::E, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_SDFFCE_N???_", "$_SDFFCE_P???_", ID::C, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_SDFFCE_?N??_", "$_SDFFCE_?P??_", ID::R, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_SDFFCE_???N_", "$_SDFFCE_???P_", ID::E, assign_map, invert_map);
 
-			handle_clkpol_celltype_swap(cell, "$_SDFF_N??_", "$_SDFF_P??_", ID::C, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_SDFF_?N?_", "$_SDFF_?P?_", ID::R, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_ALDFF_N?_", "$_ALDFF_P?_", ID::C, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_ALDFF_?N_", "$_ALDFF_?P_", ID::L, assign_map, invert_map);
 
-			handle_clkpol_celltype_swap(cell, "$_SDFFE_N???_", "$_SDFFE_P???_", ID::C, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_SDFFE_?N??_", "$_SDFFE_?P??_", ID::R, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_SDFFE_???N_", "$_SDFFE_???P_", ID::E, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_ALDFFE_N??_", "$_ALDFFE_P??_", ID::C, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_ALDFFE_?N?_", "$_ALDFFE_?P?_", ID::L, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_ALDFFE_??N_", "$_ALDFFE_??P_", ID::E, assign_map, invert_map);
 
-			handle_clkpol_celltype_swap(cell, "$_SDFFCE_N???_", "$_SDFFCE_P???_", ID::C, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_SDFFCE_?N??_", "$_SDFFCE_?P??_", ID::R, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_SDFFCE_???N_", "$_SDFFCE_???P_", ID::E, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DFFSR_N??_", "$_DFFSR_P??_", ID::C, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DFFSR_?N?_", "$_DFFSR_?P?_", ID::S, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DFFSR_??N_", "$_DFFSR_??P_", ID::R, assign_map, invert_map);
 
-			handle_clkpol_celltype_swap(cell, "$_ALDFF_N?_", "$_ALDFF_P?_", ID::C, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_ALDFF_?N_", "$_ALDFF_?P_", ID::L, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DFFSRE_N???_", "$_DFFSRE_P???_", ID::C, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DFFSRE_?N??_", "$_DFFSRE_?P??_", ID::S, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DFFSRE_??N?_", "$_DFFSRE_??P?_", ID::R, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DFFSRE_???N_", "$_DFFSRE_???P_", ID::E, assign_map, invert_map);
 
-			handle_clkpol_celltype_swap(cell, "$_ALDFFE_N??_", "$_ALDFFE_P??_", ID::C, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_ALDFFE_?N?_", "$_ALDFFE_?P?_", ID::L, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_ALDFFE_??N_", "$_ALDFFE_??P_", ID::E, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DLATCH_N_", "$_DLATCH_P_", ID::E, assign_map, invert_map);
 
-			handle_clkpol_celltype_swap(cell, "$_DFFSR_N??_", "$_DFFSR_P??_", ID::C, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_DFFSR_?N?_", "$_DFFSR_?P?_", ID::S, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_DFFSR_??N_", "$_DFFSR_??P_", ID::R, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DLATCH_N??_", "$_DLATCH_P??_", ID::E, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DLATCH_?N?_", "$_DLATCH_?P?_", ID::R, assign_map, invert_map);
 
-			handle_clkpol_celltype_swap(cell, "$_DFFSRE_N???_", "$_DFFSRE_P???_", ID::C, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_DFFSRE_?N??_", "$_DFFSRE_?P??_", ID::S, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_DFFSRE_??N?_", "$_DFFSRE_??P?_", ID::R, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_DFFSRE_???N_", "$_DFFSRE_???P_", ID::E, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DLATCHSR_N??_", "$_DLATCHSR_P??_", ID::E, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DLATCHSR_?N?_", "$_DLATCHSR_?P?_", ID::S, assign_map, invert_map);
+		handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", ID::R, assign_map, invert_map);	
+	}
 
-			handle_clkpol_celltype_swap(cell, "$_DLATCH_N_", "$_DLATCH_P_", ID::E, assign_map, invert_map);
+	TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
+	dict<RTLIL::SigBit, Cell*> outbit_to_cell;
 
-			handle_clkpol_celltype_swap(cell, "$_DLATCH_N??_", "$_DLATCH_P??_", ID::E, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_DLATCH_?N?_", "$_DLATCH_?P?_", ID::R, assign_map, invert_map);
+	for (auto cell : module->cells())
+	if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type)) {
+		for (auto &conn : cell->connections())
+		if (yosys_celltypes.cell_output(cell->type, conn.first))
+		for (auto bit : assign_map(conn.second))
+			outbit_to_cell[bit] = cell;
+		cells.node(cell);
+	}
 
-			handle_clkpol_celltype_swap(cell, "$_DLATCHSR_N??_", "$_DLATCHSR_P??_", ID::E, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_DLATCHSR_?N?_", "$_DLATCHSR_?P?_", ID::S, assign_map, invert_map);
-			handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", ID::R, assign_map, invert_map);
-		}
+	for (auto cell : module->cells())
+	if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type)) {
+		const int r_index = cells.node(cell);
+		for (auto &conn : cell->connections())
+		if (yosys_celltypes.cell_input(cell->type, conn.first))
+		for (auto bit : assign_map(conn.second))
+		if (outbit_to_cell.count(bit))
+			cells.edge(cells.node(outbit_to_cell.at(bit)), r_index);
+	}
+
+	if (!cells.sort()) {
+		// There might be a combinational loop, or there might be constants on the output of cells. Either way 'check' will find out more.
+		log_warning("Unable to topologically sort combinational cells, there must be an issue with the design. Run 'check' to see what the issue is.\n");
+	}
+
+	for (auto cell : cells.sorted)
+	{
+#define ACTION_DO(_p_, _s_) do { cover("opt.opt_expr.action_" S__LINE__); replace_cell(assign_map, module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0)
+#define ACTION_DO_Y(_v_) ACTION_DO(ID::Y, RTLIL::SigSpec(RTLIL::State::S ## _v_))
 
 		bool detect_const_and = false;
 		bool detect_const_or = false;

From fa4a2b6b0d2424a5bb4dba59448209e43f42618d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Wed, 31 Jan 2024 13:24:12 +0100
Subject: [PATCH 171/499] opt_expr: In clkinv loop ignore irrelevant cells
 early

Each call to `handle_clkpol_celltype_swap` has a conversion of the
cell's type ID to an allocated string. This can sum up to a
non-negligible time being spent in the clkpol code even for a design
which doesn't have any flip-flop gates.
---
 passes/opt/opt_expr.cc | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index b26ffc54263..07c54c9d044 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -409,6 +409,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 		}
 	}
 
+	CellTypes ct_memcells;
+	ct_memcells.setup_stdcells_mem();
+
 	if (!noclkinv)
 	for (auto cell : module->cells())
 	if (design->selected(module, cell)) {
@@ -432,6 +435,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 		if (cell->type.in(ID($dffe), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr)))
 			handle_polarity_inv(cell, ID::EN, ID::EN_POLARITY, assign_map, invert_map);
 
+		if (!ct_memcells.cell_known(cell->type))
+			continue;
+
 		handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID::S, assign_map, invert_map);
 		handle_clkpol_celltype_swap(cell, "$_SR_?N_", "$_SR_?P_", ID::R, assign_map, invert_map);
 

From 1288166f7ac03456b6beb0acff5d4fc84f63f57c Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Tue, 25 Jun 2024 00:17:11 +0000
Subject: [PATCH 172/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 18c39920fb8..f08c6c3bb8c 100644
--- a/Makefile
+++ b/Makefile
@@ -143,7 +143,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.42+30
+YOSYS_VER := 0.42+36
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 01f332e75026457401477d7bdc9fe3978cce4a93 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Tue, 25 Jun 2024 20:18:49 +0200
Subject: [PATCH 173/499] opt_expr: reduce mostly harmless warning to log

---
 passes/opt/opt_expr.cc | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 07c54c9d044..ba7292daf49 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -513,8 +513,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 	}
 
 	if (!cells.sort()) {
-		// There might be a combinational loop, or there might be constants on the output of cells. Either way 'check' will find out more.
-		log_warning("Unable to topologically sort combinational cells, there must be an issue with the design. Run 'check' to see what the issue is.\n");
+		// There might be a combinational loop, or there might be constants on the output of cells. 'check' may find out more.
+		// ...unless this is a coarse-grained cell loop, but not a bit loop, in which case it won't, and all is good.
+		log("Couldn't topologically sort cells, Yosys performance may be degraded.\nRunning 'check' is recommended.\n");
 	}
 
 	for (auto cell : cells.sorted)

From 580aaa362d837559de663ef72cab1384f37481c3 Mon Sep 17 00:00:00 2001
From: Catherine <whitequark@whitequark.org>
Date: Fri, 28 Jun 2024 15:12:36 +0000
Subject: [PATCH 174/499] opt_lut_ins: fix name of global object. NFCI

---
 passes/opt/opt_lut_ins.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/opt/opt_lut_ins.cc b/passes/opt/opt_lut_ins.cc
index 652fce1e2d5..d482f652b91 100644
--- a/passes/opt/opt_lut_ins.cc
+++ b/passes/opt/opt_lut_ins.cc
@@ -278,7 +278,7 @@ struct OptLutInsPass : public Pass {
 				module->remove(cell);
 		}
 	}
-} XilinxDffOptPass;
+} OptLutInsPass;
 
 PRIVATE_NAMESPACE_END
 

From a739e21a5f3b4fdd888d4c62f1578a1300c43f00 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Sat, 29 Jun 2024 00:16:56 +0000
Subject: [PATCH 175/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index f08c6c3bb8c..313de44d56d 100644
--- a/Makefile
+++ b/Makefile
@@ -143,7 +143,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.42+36
+YOSYS_VER := 0.42+40
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 78ae4ed9ac73d9904f69e0247270e73df3045a51 Mon Sep 17 00:00:00 2001
From: George Rennie <georgerennie@gmail.com>
Date: Mon, 1 Jul 2024 12:30:35 +0100
Subject: [PATCH 176/499] hashlib: Add some more primes

* Add some primes as suggested in #4458. This allows larger hashtables
  to be allocated for very big designs
---
 kernel/hashlib.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/kernel/hashlib.h b/kernel/hashlib.h
index e8ddddd3357..05b1528f762 100644
--- a/kernel/hashlib.h
+++ b/kernel/hashlib.h
@@ -188,6 +188,7 @@ inline unsigned int mkhash(const T &v) {
 
 inline int hashtable_size(int min_size)
 {
+	// Primes as generated by https://oeis.org/A175953
 	static std::vector<int> zero_and_some_primes = {
 		0, 23, 29, 37, 47, 59, 79, 101, 127, 163, 211, 269, 337, 431, 541, 677,
 		853, 1069, 1361, 1709, 2137, 2677, 3347, 4201, 5261, 6577, 8231, 10289,
@@ -196,7 +197,8 @@ inline int hashtable_size(int min_size)
 		897133, 1121423, 1401791, 1752239, 2190299, 2737937, 3422429, 4278037,
 		5347553, 6684443, 8355563, 10444457, 13055587, 16319519, 20399411,
 		25499291, 31874149, 39842687, 49803361, 62254207, 77817767, 97272239,
-		121590311, 151987889, 189984863, 237481091, 296851369, 371064217
+		121590311, 151987889, 189984863, 237481091, 296851369, 371064217,
+		463830273, 579787849, 724734817, 905918527, 1132398207, 1415497781
 	};
 
 	for (auto p : zero_and_some_primes)

From 339d4e893222ca510a2976063eed5a436c60c9f4 Mon Sep 17 00:00:00 2001
From: George Rennie <georgerennie@gmail.com>
Date: Tue, 2 Jul 2024 08:10:18 +0100
Subject: [PATCH 177/499] hashlib: Correct prime sequence

---
 kernel/hashlib.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/kernel/hashlib.h b/kernel/hashlib.h
index 05b1528f762..01f7bad140e 100644
--- a/kernel/hashlib.h
+++ b/kernel/hashlib.h
@@ -198,7 +198,8 @@ inline int hashtable_size(int min_size)
 		5347553, 6684443, 8355563, 10444457, 13055587, 16319519, 20399411,
 		25499291, 31874149, 39842687, 49803361, 62254207, 77817767, 97272239,
 		121590311, 151987889, 189984863, 237481091, 296851369, 371064217,
-		463830273, 579787849, 724734817, 905918527, 1132398207, 1415497781
+		463830313, 579787991, 724735009, 905918777, 1132398479, 1415498113,
+		1769372713
 	};
 
 	for (auto p : zero_and_some_primes)

From acddc363896d88ae8cf99879467ad91d618f6215 Mon Sep 17 00:00:00 2001
From: Chun Lin Min <chunlin.min@microchip.com>
Date: Tue, 2 Jul 2024 12:44:30 -0700
Subject: [PATCH 178/499] add PolarFire FPGA support

---
 passes/pmgen/Makefile.inc                     |  11 +
 passes/pmgen/mchp_dsp.cc                      | 373 ++++++++
 passes/pmgen/mchp_dsp.pmg                     | 440 +++++++++
 passes/pmgen/mchp_dsp_CREG.pmg                | 169 ++++
 passes/pmgen/mchp_dsp_cascade.pmg             | 238 +++++
 techlibs/mchp/LSRAM.txt                       | 191 ++++
 techlibs/mchp/LSRAM_map.v                     | 323 +++++++
 techlibs/mchp/Makefile.inc                    |  31 +
 techlibs/mchp/arith_map.v                     | 105 +++
 techlibs/mchp/brams_defs.vh                   |  48 +
 techlibs/mchp/cells_map.v                     | 104 +++
 techlibs/mchp/cells_sim.v                     | 849 ++++++++++++++++++
 techlibs/mchp/mchp_dffopt.cc                  | 340 +++++++
 techlibs/mchp/pf_dsp_map.v                    |  95 ++
 techlibs/mchp/synth_mchp.cc                   | 543 +++++++++++
 techlibs/mchp/tests/Registers/Registers.v     |  38 +
 techlibs/mchp/tests/Registers/Registers.ys    |  23 +
 techlibs/mchp/tests/carryout/carryout.v       |  34 +
 techlibs/mchp/tests/carryout/carryout.ys      |  21 +
 techlibs/mchp/tests/cascade/cascade.v         |  38 +
 techlibs/mchp/tests/cascade/cascade.ys        |  21 +
 techlibs/mchp/tests/dff_opt/dff_opt.v         |  42 +
 techlibs/mchp/tests/dff_opt/dff_opt.ys        |  21 +
 techlibs/mchp/tests/full_dsp/full_dsp.v       |  30 +
 techlibs/mchp/tests/full_dsp/full_dsp.ys      |  21 +
 techlibs/mchp/tests/large_mult/large_mult.v   |  25 +
 techlibs/mchp/tests/large_mult/large_mult.ys  |  21 +
 techlibs/mchp/tests/mac/mac.v                 |  43 +
 techlibs/mchp/tests/mac/mac.ys                |  24 +
 .../mchp/tests/postAdd_mult/postAdd_mult.v    |  30 +
 .../mchp/tests/postAdd_mult/postAdd_mult.ys   |  21 +
 techlibs/mchp/tests/post_adder/post_adder.v   |  32 +
 techlibs/mchp/tests/post_adder/post_adder.ys  |  21 +
 .../mchp/tests/pre_adder_dsp/pre_adder_dsp.v  |  30 +
 .../mchp/tests/pre_adder_dsp/pre_adder_dsp.ys |  21 +
 techlibs/mchp/tests/ram_SDP/ram_SDP.v         |  39 +
 techlibs/mchp/tests/ram_SDP/ram_SDP.ys        |  21 +
 techlibs/mchp/tests/ram_TDP/ram_TDP.v         |  56 ++
 techlibs/mchp/tests/ram_TDP/ram_TDP.ys        |  21 +
 techlibs/mchp/tests/reduce/reduce.v           |  29 +
 techlibs/mchp/tests/reduce/reduce.ys          |  21 +
 techlibs/mchp/tests/reg_c/reg_c.v             | 122 +++
 techlibs/mchp/tests/reg_c/reg_c.ys            |  21 +
 techlibs/mchp/tests/reg_test/reg_test.v       |  97 ++
 techlibs/mchp/tests/reg_test/reg_test.ys      |  21 +
 techlibs/mchp/tests/signed_mult/signed_mult.v |  28 +
 .../mchp/tests/signed_mult/signed_mult.ys     |  21 +
 techlibs/mchp/tests/simple_ram/simple_ram.v   |  37 +
 techlibs/mchp/tests/simple_ram/simple_ram.ys  |  21 +
 .../mchp/tests/unsigned_mult/unsigned_mult.v  |  28 +
 .../mchp/tests/unsigned_mult/unsigned_mult.ys |  21 +
 techlibs/mchp/tests/uram_ar/uram_ar.v         |  38 +
 techlibs/mchp/tests/uram_ar/uram_ar.ys        |  21 +
 techlibs/mchp/tests/uram_sr/uram_sr.v         |  32 +
 techlibs/mchp/tests/uram_sr/uram_sr.ys        |  21 +
 techlibs/mchp/tests/widemux/widemux.v         |  48 +
 techlibs/mchp/tests/widemux/widemux.ys        |  21 +
 techlibs/mchp/uSRAM.txt                       |  69 ++
 techlibs/mchp/uSRAM_map.v                     | 118 +++
 59 files changed, 5389 insertions(+)
 create mode 100644 passes/pmgen/mchp_dsp.cc
 create mode 100644 passes/pmgen/mchp_dsp.pmg
 create mode 100644 passes/pmgen/mchp_dsp_CREG.pmg
 create mode 100644 passes/pmgen/mchp_dsp_cascade.pmg
 create mode 100644 techlibs/mchp/LSRAM.txt
 create mode 100644 techlibs/mchp/LSRAM_map.v
 create mode 100644 techlibs/mchp/Makefile.inc
 create mode 100644 techlibs/mchp/arith_map.v
 create mode 100644 techlibs/mchp/brams_defs.vh
 create mode 100644 techlibs/mchp/cells_map.v
 create mode 100644 techlibs/mchp/cells_sim.v
 create mode 100644 techlibs/mchp/mchp_dffopt.cc
 create mode 100644 techlibs/mchp/pf_dsp_map.v
 create mode 100644 techlibs/mchp/synth_mchp.cc
 create mode 100644 techlibs/mchp/tests/Registers/Registers.v
 create mode 100644 techlibs/mchp/tests/Registers/Registers.ys
 create mode 100644 techlibs/mchp/tests/carryout/carryout.v
 create mode 100644 techlibs/mchp/tests/carryout/carryout.ys
 create mode 100644 techlibs/mchp/tests/cascade/cascade.v
 create mode 100644 techlibs/mchp/tests/cascade/cascade.ys
 create mode 100644 techlibs/mchp/tests/dff_opt/dff_opt.v
 create mode 100644 techlibs/mchp/tests/dff_opt/dff_opt.ys
 create mode 100644 techlibs/mchp/tests/full_dsp/full_dsp.v
 create mode 100644 techlibs/mchp/tests/full_dsp/full_dsp.ys
 create mode 100644 techlibs/mchp/tests/large_mult/large_mult.v
 create mode 100644 techlibs/mchp/tests/large_mult/large_mult.ys
 create mode 100644 techlibs/mchp/tests/mac/mac.v
 create mode 100644 techlibs/mchp/tests/mac/mac.ys
 create mode 100644 techlibs/mchp/tests/postAdd_mult/postAdd_mult.v
 create mode 100644 techlibs/mchp/tests/postAdd_mult/postAdd_mult.ys
 create mode 100644 techlibs/mchp/tests/post_adder/post_adder.v
 create mode 100644 techlibs/mchp/tests/post_adder/post_adder.ys
 create mode 100644 techlibs/mchp/tests/pre_adder_dsp/pre_adder_dsp.v
 create mode 100644 techlibs/mchp/tests/pre_adder_dsp/pre_adder_dsp.ys
 create mode 100644 techlibs/mchp/tests/ram_SDP/ram_SDP.v
 create mode 100644 techlibs/mchp/tests/ram_SDP/ram_SDP.ys
 create mode 100644 techlibs/mchp/tests/ram_TDP/ram_TDP.v
 create mode 100644 techlibs/mchp/tests/ram_TDP/ram_TDP.ys
 create mode 100644 techlibs/mchp/tests/reduce/reduce.v
 create mode 100644 techlibs/mchp/tests/reduce/reduce.ys
 create mode 100644 techlibs/mchp/tests/reg_c/reg_c.v
 create mode 100644 techlibs/mchp/tests/reg_c/reg_c.ys
 create mode 100644 techlibs/mchp/tests/reg_test/reg_test.v
 create mode 100644 techlibs/mchp/tests/reg_test/reg_test.ys
 create mode 100755 techlibs/mchp/tests/signed_mult/signed_mult.v
 create mode 100755 techlibs/mchp/tests/signed_mult/signed_mult.ys
 create mode 100644 techlibs/mchp/tests/simple_ram/simple_ram.v
 create mode 100644 techlibs/mchp/tests/simple_ram/simple_ram.ys
 create mode 100644 techlibs/mchp/tests/unsigned_mult/unsigned_mult.v
 create mode 100644 techlibs/mchp/tests/unsigned_mult/unsigned_mult.ys
 create mode 100644 techlibs/mchp/tests/uram_ar/uram_ar.v
 create mode 100644 techlibs/mchp/tests/uram_ar/uram_ar.ys
 create mode 100644 techlibs/mchp/tests/uram_sr/uram_sr.v
 create mode 100644 techlibs/mchp/tests/uram_sr/uram_sr.ys
 create mode 100644 techlibs/mchp/tests/widemux/widemux.v
 create mode 100644 techlibs/mchp/tests/widemux/widemux.ys
 create mode 100644 techlibs/mchp/uSRAM.txt
 create mode 100644 techlibs/mchp/uSRAM_map.v

diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc
index ed872b7212d..581ce241646 100644
--- a/passes/pmgen/Makefile.inc
+++ b/passes/pmgen/Makefile.inc
@@ -37,6 +37,17 @@ $(eval $(call add_extra_objs,passes/pmgen/xilinx_dsp_cascade_pm.h))
 
 # --------------------------------------
 
+OBJS += passes/pmgen/mchp_dsp.o
+GENFILES += passes/pmgen/mchp_dsp_pm.h
+GENFILES += passes/pmgen/mchp_dsp_CREG_pm.h
+GENFILES += passes/pmgen/mchp_dsp_cascade_pm.h
+passes/pmgen/mchp_dsp.o: passes/pmgen/mchp_dsp_pm.h passes/pmgen/mchp_dsp_CREG_pm.h passes/pmgen/mchp_dsp_cascade_pm.h
+$(eval $(call add_extra_objs,passes/pmgen/mchp_dsp_pm.h))
+$(eval $(call add_extra_objs,passes/pmgen/mchp_dsp_CREG_pm.h))
+$(eval $(call add_extra_objs,passes/pmgen/mchp_dsp_cascade_pm.h))
+
+# --------------------------------------
+
 OBJS += passes/pmgen/peepopt.o
 GENFILES += passes/pmgen/peepopt_pm.h
 passes/pmgen/peepopt.o: passes/pmgen/peepopt_pm.h
diff --git a/passes/pmgen/mchp_dsp.cc b/passes/pmgen/mchp_dsp.cc
new file mode 100644
index 00000000000..8a1bf0b3c41
--- /dev/null
+++ b/passes/pmgen/mchp_dsp.cc
@@ -0,0 +1,373 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+#include <deque>
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+#include "passes/pmgen/mchp_dsp_pm.h"
+#include "passes/pmgen/mchp_dsp_CREG_pm.h"
+#include "passes/pmgen/mchp_dsp_cascade_pm.h"
+
+void mchp_dsp_pack(mchp_dsp_pm &pm)
+{
+	auto &st = pm.st_mchp_dsp_pack;
+
+	log("Analysing %s.%s for MCHP MACC_PA packing.\n", log_id(pm.module), log_id(st.dsp));
+
+	Cell *cell = st.dsp;
+	//pack pre-adder
+	if (st.preAdderStatic) {
+		SigSpec &pasub = cell->connections_.at(ID(PASUB));
+		log("  static PASUB preadder %s (%s)\n", log_id(st.preAdderStatic), log_id(st.preAdderStatic->type));
+		bool D_SIGNED = st.preAdderStatic->getParam(ID::B_SIGNED).as_bool();
+		bool B_SIGNED = st.preAdderStatic->getParam(ID::A_SIGNED).as_bool();
+		st.sigB.extend_u0(18, B_SIGNED);
+		st.sigD.extend_u0(18, D_SIGNED);
+		if (st.moveBtoA)
+		{
+			cell->setPort(ID::A, st.sigA); // if pre-adder feeds into A, original sigB will be moved to port A
+		}
+		cell->setPort(ID::B, st.sigB);
+		cell->setPort(ID::D, st.sigD);
+		// MACC_PA supports both addition and subtraction with the pre-adder.
+		//   Affects the sign of the 'D' port.
+		if (st.preAdderStatic->type == ID($add))
+			pasub[0] = State::S0;
+		else if (st.preAdderStatic->type == ID($sub))
+			pasub[0] = State::S1;
+		else
+			log_assert(!"strange pre-adder type");
+
+		pm.autoremove(st.preAdderStatic);
+	}
+	//pack post-adder
+	if (st.postAdderStatic) {
+		log("  postadder %s (%s)\n", log_id(st.postAdderStatic), log_id(st.postAdderStatic->type));
+		SigSpec &sub = cell->connections_.at(ID(SUB));
+		// Post-adder in MACC_PA also supports subtraction
+		//   Determines the sign of the output from the multiplier.
+		if (st.postAdderStatic->type == ID($add))
+			sub[0] = State::S0;
+		else if (st.postAdderStatic->type == ID($sub))
+			sub[0] = State::S1;
+		else
+			log_assert(!"strange post-adder type");
+
+		if (st.useFeedBack) {
+			cell->setPort(ID(CDIN_FDBK_SEL), {State::S0, State::S1});	
+		} else {
+			st.sigC.extend_u0(48, st.postAdderStatic->getParam(ID::A_SIGNED).as_bool());
+			cell->setPort(ID::C, st.sigC);	
+		}
+
+
+		pm.autoremove(st.postAdderStatic);
+	}
+	
+	// pack registers
+	if (st.clock != SigBit())
+	{
+		cell->setPort(ID::CLK, st.clock);
+
+		// function to absorb a register
+		auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport, IdString bypass) {
+
+			// input/output ports
+			SigSpec D = ff->getPort(ID::D);
+			SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
+			
+			if (!A.empty())
+				A.replace(Q, D);
+			if (rstport != IdString()) {
+				if (ff->type.in(ID($sdff), ID($sdffe))) {
+					SigSpec srst = ff->getPort(ID::SRST);
+					bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool();
+					// active low sync rst
+					cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_ID, srst));
+				} else if (ff->type.in(ID($adff), ID($adffe))) {
+					SigSpec arst = ff->getPort(ID::ARST);
+					bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool();
+					// active low async rst
+					cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_ID, arst));
+				} else {
+					// active low async/sync rst
+					cell->setPort(rstport, State::S1);
+				}
+			}
+			if (ff->type.in(ID($dffe), ID($sdffe), ID($adffe))) {
+				SigSpec ce = ff->getPort(ID::EN);
+				bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
+				// enables are all active high
+				cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
+			}
+			else {
+				// enables are all active high
+				cell->setPort(ceport, State::S1); 
+			}
+
+			// bypass set to 0
+			cell->setPort(bypass, State::S0); 
+			
+
+			for (auto c : Q.chunks()) {
+				auto it = c.wire->attributes.find(ID::init);
+				if (it == c.wire->attributes.end())
+					continue;
+				for (int i = c.offset; i < c.offset+c.width; i++) {
+					log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
+					it->second[i] = State::Sx;
+				}
+			}
+		};
+
+		// NOTE: flops are not autoremoved because it is possible that they
+		//       are only partially absorbed into DSP, or have fanouts.
+		if (st.ffA) {
+			SigSpec A = cell->getPort(ID::A);
+			if (st.ffA) {
+				f(A, st.ffA, ID(A_EN), ID(A_SRST_N), ID(A_BYPASS));
+			}
+			pm.add_siguser(A, cell);
+			cell->setPort(ID::A, A);
+		}
+		if (st.ffB) {
+			SigSpec B = cell->getPort(ID::B);
+			if (st.ffB) {
+				f(B, st.ffB, ID(B_EN), ID(B_SRST_N), ID(B_BYPASS));
+			}
+			pm.add_siguser(B, cell);
+			cell->setPort(ID::B, B);
+		}
+		if (st.ffD) {
+			SigSpec D = cell->getPort(ID::D);
+			if (st.ffD->type.in(ID($adff), ID($adffe))) {
+				f(D, st.ffD, ID(D_EN), ID(D_ARST_N), ID(D_BYPASS));
+			} else {
+				f(D, st.ffD, ID(D_EN), ID(D_SRST_N), ID(D_BYPASS));
+			}
+			
+			pm.add_siguser(D, cell);
+			cell->setPort(ID::D, D);
+		}
+		if (st.ffP) {
+			SigSpec P; // unused
+			f(P, st.ffP, ID(P_EN), ID(P_SRST_N), ID(P_BYPASS));
+			st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
+		}
+
+		log("  clock: %s (%s)\n", log_signal(st.clock), "posedge");
+
+		if (st.ffA)
+			log(" \t ffA:%s\n", log_id(st.ffA));
+		if (st.ffB)
+			log(" \t ffB:%s\n", log_id(st.ffB));
+		if (st.ffD)
+			log(" \t ffD:%s\n", log_id(st.ffD));
+		if (st.ffP)
+			log(" \t ffP:%s\n", log_id(st.ffP));
+	}
+	log("\n");
+
+	SigSpec P = st.sigP;
+	if (GetSize(P) < 48)
+		P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
+	cell->setPort(ID::P, P);
+
+	pm.blacklist(cell);
+}
+
+// For packing cascaded DSPs
+void mchp_dsp_packC(mchp_dsp_CREG_pm &pm)
+{
+	auto &st = pm.st_mchp_dsp_packC;
+
+	log_debug("Analysing %s.%s for MCHP DSP packing (REG_C).\n", log_id(pm.module), log_id(st.dsp));
+	log_debug("ffC:        %s\n", log_id(st.ffC, "--"));
+
+	Cell *cell = st.dsp;
+
+	if (st.clock != SigBit())
+	{
+		cell->setPort(ID::CLK, st.clock);
+
+		// same function as above, used for the last CREG we need to absorb
+		auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport, IdString bypass) {
+
+			// input/output ports
+			SigSpec D = ff->getPort(ID::D);
+			SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
+			if (!A.empty())
+				A.replace(Q, D);
+			if (rstport != IdString()) {
+				if (ff->type.in(ID($sdff), ID($sdffe))) {
+					SigSpec srst = ff->getPort(ID::SRST);
+					bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool();
+					// active low sync rst
+					cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_ID, srst));
+				} else if (ff->type.in(ID($adff), ID($adffe))) {
+					SigSpec arst = ff->getPort(ID::ARST);
+					bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool();
+					// active low async rst
+					cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_ID, arst));
+				} else {
+					// active low async/sync rst
+					cell->setPort(rstport, State::S1);
+				}
+			}
+			if (ff->type.in(ID($dffe), ID($sdffe), ID($adffe))) {
+				SigSpec ce = ff->getPort(ID::EN);
+				bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
+				// enables are all active high
+				cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
+			} else {
+				// enables are all active high
+				cell->setPort(ceport, State::S1); 
+			}
+
+			// bypass set to 0
+			cell->setPort(bypass, State::S0); 
+			
+
+			for (auto c : Q.chunks()) {
+				auto it = c.wire->attributes.find(ID::init);
+				if (it == c.wire->attributes.end())
+					continue;
+				for (int i = c.offset; i < c.offset+c.width; i++) {
+					log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
+					it->second[i] = State::Sx;
+				}
+			}
+		};
+
+		if (st.ffC) {
+			SigSpec C = cell->getPort(ID::C);
+			
+			if (st.ffC->type.in(ID($adff), ID($adffe))) {
+				f(C, st.ffC, ID(C_EN), ID(C_ARST_N), ID(C_BYPASS));
+			} else {
+				f(C, st.ffC, ID(C_EN), ID(C_SRST_N), ID(C_BYPASS));
+			}
+			pm.add_siguser(C, cell);
+			cell->setPort(ID::C, C);
+		}
+
+		log("  clock: %s (%s)", log_signal(st.clock), "posedge");
+
+		if (st.ffC)
+			log(" ffC:%s", log_id(st.ffC));
+		log("\n");
+	}
+
+	pm.blacklist(cell);
+}
+
+struct MchpDspPass : public Pass {
+	MchpDspPass() : Pass("mchp_dsp", "MCHP: pack resources into DSPs") { }
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    mchp_dsp [options] [selection]\n");
+		log("\n");
+		log("Pack input registers 'A', 'B', 'C', and 'D' (with optional enable/reset),\n");
+		log("output register 'P' (with optional enable/reset), pre-adder and/or post-adder into\n");
+		log("MCHP DSP resources.\n");
+		log("\n");
+		log("Multiply-accumulate operations using the post-adder with feedback on the 'C'\n");
+		log("input will be folded into the DSP. In this scenario only, the 'C' input can be\n");
+		log("used to override the current accumulation result with a new value. This will\n");
+		log("be added to the multiplier result to form the next accumulation result.\n");
+		log("\n");
+		log("Use of the dedicated 'PCOUT' -> 'PCIN' cascade path is detected for 'P' -> 'C'\n");
+		log("connections (optionally, where 'P' is right-shifted by 17-bits and used as an\n");
+		log("input to the post-adder. This pattern is common for summing partial products to\n");
+		log("implement wide multipliers). Cascade chains are limited to a mazimum length \n");
+		log("of 24 cells, corresponding to PolarFire (pf) devices.\n");
+		log("\n");
+		log("This pass is a no-op if the scratchpad variable 'mchp_dsp.multonly' is set\n");
+		log("to 1.\n");
+		log("\n");
+		log("\n");
+		log("    -family {pf}\n");
+		log("        select the family to target\n");
+		log("        default: pf\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		log_header(design, "Executing MCHP_DSP pass (pack resources into DSPs).\n");
+
+		std::string family = "pf";
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if ((args[argidx] == "-family") && argidx+1 < args.size()) {
+				family = args[++argidx];
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules()) {
+
+			if (design->scratchpad_get_bool("mchp_dsp.multonly"))
+				continue;
+
+			{
+				// For more details on PolarFire MACC_PA, consult
+				//   the "PolarFire FPGA Macro Library Guide"
+
+				// Main pattern matching step to capture a DSP cell.
+				//   Match for pre-adder, post-adder, as well as 
+				//   registers 'A', 'B', 'D', and 'P'. Additionally,
+				//   check for an accumulator pattern based on whether
+				//   a post-adder and PREG are both present AND
+				//   if PREG feeds into this post-adder.  
+				mchp_dsp_pm pm(module, module->selected_cells());
+				pm.run_mchp_dsp_pack(mchp_dsp_pack);
+			}
+
+			// Separating out CREG packing is necessary since there
+			//   is no guarantee that the cell ordering corresponds
+			//   to the "expected" case (i.e. the order in which
+			//   they appear in the source). There existed the possibility
+			// 	 where a register got packed as a CREG into a
+			//   downstream DSP that should have otherwise been a
+			//   PREG of an upstream DSP that had not been visited
+			//   yet
+			{
+				mchp_dsp_CREG_pm pm(module, module->selected_cells());
+				pm.run_mchp_dsp_packC(mchp_dsp_packC);
+			}
+
+			// Lastly, identify and utilise PCOUT -> PCIN chains
+			{
+				mchp_dsp_cascade_pm pm(module, module->selected_cells());
+				pm.run_mchp_dsp_cascade();
+			}
+			
+		}
+	}
+} MchpDspPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/pmgen/mchp_dsp.pmg b/passes/pmgen/mchp_dsp.pmg
new file mode 100644
index 00000000000..2580d64b49b
--- /dev/null
+++ b/passes/pmgen/mchp_dsp.pmg
@@ -0,0 +1,440 @@
+// ISC License
+// 
+// Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+// 
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+
+// This file describes the main pattern matcher setup (of three total) that
+//   forms the `mchp_dsp` pass described in mchp_dsp.cc - version for
+//   DSP48A/DSP48A1 (Spartan 3A DSP, Spartan 6).
+// At a high level, it works as follows:
+//   ( 1) Starting from a DSP cell. Capture DSP configurations as states
+//   ( 2) Match for pre-adder
+//   ( 3) Match for post-adder
+//   ( 4) Match register 'A', 'B', 'D', 'P' 
+//   ( 5) If post-adder and PREG both present, check if PREG feeds into post-adder.
+//        This indicates an accumulator situation like the ASCII diagram below:
+//             +--------------------------------+
+//             |_________                       |
+//                       | /-------\   +----+   |
+//            +----+     +-| post- |___|PREG|---+ 'P'
+//            |MULT|------ | adder |   +----+
+//            +----+       \-------/
+
+pattern mchp_dsp_pack
+
+state <SigBit> clock
+state <SigSpec> sigA sigB sigC sigD sigP
+state <Cell*> ffA ffB ffD ffP
+state <Cell*> preAdderStatic postAdderStatic
+state <bool> moveBtoA useFeedBack
+
+// static ports, used to detect dsp configuration
+state <SigSpec> bypassA bypassB bypassC bypassD bypassP
+state <SigSpec> bypassPASUB
+
+// Variables used for subpatterns
+state <SigSpec> argQ argD
+udata <bool> allowAsync
+udata <SigSpec> dffD dffQ
+udata <SigBit> dffclock
+udata <Cell*> dff
+udata <Cell*> u_preAdderStatic u_postAdderStatic
+udata <IdString> u_postAddAB
+state <IdString> postAddAB
+
+// (1) Starting from a DSP cell
+match dsp
+	select dsp->type.in(\MACC_PA)
+endmatch
+
+// detect existing signals connected to DSP
+// detect configuration ports
+code sigA sigB sigC sigD clock sigP
+	//helper function to remove unused bits
+	auto unextend = [](const SigSpec &sig) {
+		int i;
+		for (i = GetSize(sig)-1; i > 0; i--)
+			if (sig[i] != sig[i-1])
+				break;
+		// Do not remove non-const sign bit
+		if (sig[i].wire)
+			++i;
+		return sig.extract(0, i);
+	};
+
+	//unextend to remove unused bits
+	sigA = unextend(port(dsp, \A));
+	sigB = unextend(port(dsp, \B));
+
+	//update signals
+	sigC = port(dsp, \C, SigSpec());
+	sigD = port(dsp, \D, SigSpec());
+
+
+	SigSpec P = port(dsp, \P);
+	// Only care about bits that are used
+	int i;
+	for (i = GetSize(P)-1; i >= 0; i--)
+		if (nusers(P[i]) > 1)
+			break;
+	i++;
+	log_assert(nusers(P.extract_end(i)) <= 1);
+	// This sigP could have no users if downstream sinks (e.g. $add) is
+	//   narrower than $mul result, for example
+	if (i == 0)
+		reject;
+	sigP = P.extract(0, i);
+	clock = port(dsp, \CLK, SigBit());
+
+endcode
+
+// capture static configuration ports
+code bypassA bypassB bypassC bypassD bypassPASUB bypassP
+	bypassA = port(dsp, \A_BYPASS, SigSpec());
+	bypassB = port(dsp, \B_BYPASS, SigSpec());
+	bypassC = port(dsp, \C_BYPASS, SigSpec());
+	bypassD = port(dsp, \D_BYPASS, SigSpec());
+	bypassPASUB = port(dsp, \PASUB_BYPASS, SigSpec());
+	bypassP = port(dsp, \P_BYPASS, SigSpec());
+endcode
+
+// (2) Match for pre-adder
+// 
+code sigA sigB sigD preAdderStatic moveBtoA
+	subpattern(preAddMatching);
+	preAdderStatic = u_preAdderStatic;
+	moveBtoA = false;
+
+	if (preAdderStatic) {
+		
+		if (port(preAdderStatic, \Y) == sigA)
+		{
+			//used for packing
+			moveBtoA = true;
+
+			// sigA should be the input to the multiplier without the preAdd. sigB and sigD should be 
+			//the preAdd inputs. If our "A" input into the multiplier is from the preAdd (not sigA), then 
+			// we basically swap it.
+			sigA = port(dsp, \B);
+		}
+
+		// port B of preAdderStatic must be mapped to port D of DSP for subtraction
+		sigD = port(preAdderStatic, \B);
+		sigB = port(preAdderStatic, \A);
+	}
+endcode
+
+//  (3) Match for post-adder
+//
+code postAdderStatic sigP sigC
+	u_postAdderStatic = nullptr;
+	subpattern(postAddMatching);
+	postAdderStatic = u_postAdderStatic;
+
+	if (postAdderStatic) {
+		//sigC will be whichever input to the postAdder that is NOT from the multiplier
+		// u_postAddAB is the input to the postAdder from the multiplier 
+		sigC = port(postAdderStatic, u_postAddAB == \A ? \B : \A);
+		sigP = port(postAdderStatic, \Y);
+	}
+endcode
+
+
+// (4) Matching registers
+//
+// 'A' input for REG_A
+code argQ bypassA sigA clock ffA
+	if (bypassA.is_fully_ones()){
+		argQ = sigA;
+		allowAsync = false;
+		subpattern(in_dffe);
+		if (dff) {
+			ffA = dff;
+			clock = dffclock;
+			sigA = dffD;
+		}
+	}
+endcode
+
+// 'B' input for REG_B
+code argQ bypassB sigB clock ffB
+	if (bypassB.is_fully_ones()){
+		argQ = sigB;
+		allowAsync = false;
+		subpattern(in_dffe);
+		if (dff) {
+			ffB = dff;
+			clock = dffclock;
+			sigB = dffD;
+		}
+	}
+endcode
+
+// 'D' input for REG_D
+code argQ bypassP sigD clock ffD
+	if (bypassD.is_fully_ones()){
+		argQ = sigD;
+		allowAsync = true;
+		subpattern(in_dffe);
+		if (dff) {
+			ffD = dff;
+			clock = dffclock;
+			sigD = dffD;
+		}
+	}
+endcode
+
+// 'P' output for REG_P
+code argD ffP sigP clock bypassP
+	if (bypassP.is_fully_ones() && nusers(sigP) == 2) {
+		argD = sigP;
+		allowAsync = false;
+		subpattern(out_dffe);
+		if (dff) {
+			ffP = dff;
+			clock = dffclock;
+			sigP = dffQ;
+		}
+	}
+endcode
+
+// (5) If post-adder and PREG both present, check if PREG feeds into post-adder via port C.
+//        This indicates an accumulator situation. Port C can be freed
+//             +--------------------------------+
+//             |_________                       |
+//                       | /-------\   +----+   |
+//            +----+     +-| post- |___|PREG|---+ 'P'
+//            |MULT|------ | adder |   +----+
+//            +----+       \-------/
+code useFeedBack
+	useFeedBack = false;
+	if (postAdderStatic && ffP)	{
+		if (sigC == sigP) {
+			useFeedBack = true;
+		}
+	}
+
+endcode
+
+// if any cells are absorbed, invoke the callback function
+code
+	if (preAdderStatic || postAdderStatic)
+		accept;
+	if (ffA || ffB || ffD || ffP)
+		accept;
+endcode
+
+
+// #######################
+// Subpattern for matching against post-adder
+//   Match 'P' output that exclusively drives one of two inputs to an $add
+//   cell (post-adder).
+//   The other input to the adder is assumed to come in from the 'C' input
+
+subpattern postAddMatching
+arg sigP
+
+match postAdd
+
+	select postAdd->type.in($add, $sub)
+	select GetSize(port(postAdd, \Y)) <= 48
+
+	// AB is the port that connects MUL to ADD
+	choice <IdString> AB {\A, \B}
+	select nusers(port(postAdd, AB)) == 2
+
+	// has one input coming from multiplier
+	index <SigBit> port(postAdd, AB)[0] === sigP[0]
+	filter GetSize(port(postAdd, AB)) >= GetSize(sigP)
+	filter port(postAdd, AB).extract(0, GetSize(sigP)) == sigP
+	// Check that remainder of AB is a sign- or zero-extension
+	filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(sigP[GetSize(sigP)-1], GetSize(port(postAdd, AB))-GetSize(sigP)) || port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(State::S0, GetSize(port(postAdd, AB))-GetSize(sigP))
+
+	set postAddAB AB
+	// optional
+endmatch
+
+code
+	if (postAdd)
+	{
+		if (postAdd->type.in(ID($sub)) && postAddAB == \A) {
+			// if $sub, the multiplier output must match to $sub.B, otherwise no match	
+		} else {
+			u_postAddAB = postAddAB;
+			u_postAdderStatic = postAdd;
+		}
+
+	}
+endcode
+
+
+// #######################
+// Subpattern for matching against pre-adder
+//		support static PASUB only
+
+subpattern preAddMatching
+arg sigA sigB sigD bypassB bypassD bypassPASUB
+
+code 
+	u_preAdderStatic = nullptr;
+
+	// Ensure that preAdder not already used
+	// Assume we can inspect port D to see if its all zeros. 
+	if (!(sigD.empty() || sigD.is_fully_zero())) reject;
+	if (!bypassB.is_fully_ones()) reject;
+	if (!bypassD.is_fully_ones()) reject;
+	if (!bypassPASUB.is_fully_ones()) reject;
+endcode
+
+match preAdd
+
+	// can handle add or sub
+	select preAdd->type.in($add, $sub)
+
+	// Output has to be 18 bits or less, and only has single fanout
+	select GetSize(port(preAdd, \Y)) <= 18
+	select nusers(port(preAdd, \Y)) == 2
+
+	// Adder inputs must be 18 bits or less
+	select GetSize(port(preAdd, \A)) <= 18
+	select GetSize(port(preAdd, \B)) <= 18
+
+	// Output feeds into one of multiplier input
+	filter port(preAdd, \Y) == sigB || port(preAdd, \Y) == sigA
+
+	// optional
+endmatch
+
+code
+	if (preAdd)
+	{
+		u_preAdderStatic = preAdd;
+	}
+endcode
+
+// #######################
+// Subpattern for matching against input registers, based on knowledge of the
+//   'Q' input.
+subpattern in_dffe
+arg argQ clock
+
+code
+	dff = nullptr;
+	if (argQ.empty())
+		reject;
+	for (const auto &c : argQ.chunks()) {
+		// Abandon matches when 'Q' is a constant
+		if (!c.wire)
+			reject;
+		// Abandon matches when 'Q' has the keep attribute set
+		if (c.wire->get_bool_attribute(\keep))
+			reject;
+		// Abandon matches when 'Q' has a non-zero init attribute set
+		Const init = c.wire->attributes.at(\init, Const());
+		if (!init.empty())
+			for (auto b : init.extract(c.offset, c.width))
+				if (b != State::Sx && b != State::S0)
+					reject;
+	}
+endcode
+
+match ff
+	// reg D has async rst
+	// reg A, B has sync rst
+	select ff->type.in($dff, $dffe, $sdff, $sdffe, $adff, $adffe)
+	// does not support clock inversion
+	select param(ff, \CLK_POLARITY).as_bool()
+
+	// it is possible that only part of a dff output matches argQ
+	slice offset GetSize(port(ff, \D))
+	index <SigBit> port(ff, \Q)[offset] === argQ[0]
+
+	// Check that the rest of argQ is present
+	filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
+	filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
+
+	// only consider async rst flops when flag is set
+	filter !ff->type.in($adff, $adffe) || allowAsync
+
+	// clock must be consistent
+	filter clock == SigBit() || port(ff, \CLK) == clock
+endmatch
+
+code argQ
+	// Check that reset value, if present, is fully 0.
+	bool noResetFlop = ff->type.in($dff, $dffe);
+	bool srstZero = ff->type.in($sdff, $sdffe) && param(ff, \SRST_VALUE).is_fully_zero();
+	bool arstZero = ff->type.in($adff, $adffe) && param(ff, \ARST_VALUE).is_fully_zero();
+	bool resetLegal = noResetFlop || srstZero || arstZero;
+	if (resetLegal)
+	{
+		SigSpec Q = port(ff, \Q);
+		dff = ff;
+		dffclock = port(ff, \CLK);
+		dffD = argQ;
+		SigSpec D = port(ff, \D);
+		argQ = Q;
+		dffD.replace(argQ, D);
+	}
+
+endcode
+// #######################
+
+
+subpattern out_dffe
+arg argD argQ clock
+
+code
+	dff = nullptr;
+	for (auto c : argD.chunks())
+		// Abandon matches when 'D' has the keep attribute set
+		if (c.wire->get_bool_attribute(\keep))
+			reject;
+endcode
+
+match ff
+	select ff->type.in($dff, $dffe, $sdff, $sdffe)
+	// does not support clock inversion
+	select param(ff, \CLK_POLARITY).as_bool()
+
+	slice offset GetSize(port(ff, \D))
+	index <SigBit> port(ff, \D)[offset] === argD[0]
+
+	// Check that the rest of argD is present
+	filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
+	filter port(ff, \D).extract(offset, GetSize(argD)) == argD
+
+	filter clock == SigBit() || port(ff, \CLK) == clock
+endmatch
+
+code argQ
+	SigSpec D = port(ff, \D);
+	SigSpec Q = port(ff, \Q);
+	argQ = argD;
+	argQ.replace(D, Q);
+
+	// Abandon matches when 'Q' has a non-zero init attribute set
+	for (auto c : argQ.chunks()) {
+		Const init = c.wire->attributes.at(\init, Const());
+		if (!init.empty())
+			for (auto b : init.extract(c.offset, c.width))
+				if (b != State::Sx && b != State::S0)
+					reject;
+	}
+
+	dff = ff;
+	dffQ = argQ;
+	dffclock = port(ff, \CLK);
+endcode
diff --git a/passes/pmgen/mchp_dsp_CREG.pmg b/passes/pmgen/mchp_dsp_CREG.pmg
new file mode 100644
index 00000000000..8647f16a16b
--- /dev/null
+++ b/passes/pmgen/mchp_dsp_CREG.pmg
@@ -0,0 +1,169 @@
+// ISC License
+// 
+// Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+// 
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+
+// This file describes the second of three pattern matcher setups that
+//   forms the `mchp_dsp` pass described in mchp_dsp.cc
+// At a high level, it works as follows:
+//   (1) Starting from a DSP cell that (a) doesn't have a CREG already,
+//       and (b) uses the 'C' port
+//   (2) Match the driver of the 'C' input to a possible $dff cell (CREG)
+//       (attached to at most two $mux cells that implement clock-enable or
+//        reset functionality, using a subpattern discussed below)
+// Notes:
+//   - Running CREG packing after mchp_dsp_pack is necessary since there is no
+//     guarantee that the cell ordering corresponds to the "expected" case (i.e.
+//     the order in which they appear in the source) thus the possiblity existed
+//     where a register got packed as a CREG into a downstream DSP, while it should
+//     have otherwise been a PREG of an upstream DSP that had not been visited.
+//     yet.
+//   - The reason this is separated out from the mchp_dsp.pmg file is
+//     for efficiency --- each *.pmg file creates a class of the same basename,
+//     which when constructed, creates a custom database tailored to the
+//     pattern(s) contained within. Since the pattern in this file must be
+//     executed after the pattern contained in mchp_dsp.pmg, it is necessary
+//     to reconstruct this database. Separating the two patterns into
+//     independent files causes two smaller, more specific, databases.
+
+pattern mchp_dsp_packC
+
+udata <std::function<SigSpec(const SigSpec&)>> unextend
+state <SigBit> clock
+state <SigSpec> sigC sigP
+state <Cell*> ffC
+
+// Variables used for subpatterns
+state <SigSpec> argQ argD
+state <int> ffoffset
+udata <SigSpec> dffD dffQ
+udata <SigBit> dffclock
+udata <Cell*> dff
+
+// (1) Starting from a DSP cell that (a) doesn't have a CREG already,
+//     and (b) uses the 'C' port
+match dsp
+	select dsp->type.in(\MACC_PA)
+    select port(dsp, \C_BYPASS, SigSpec()).is_fully_ones()
+	select nusers(port(dsp, \C, SigSpec())) > 1
+endmatch
+
+code sigC sigP clock
+	//helper function to remove unused bits
+	unextend = [](const SigSpec &sig) {
+		int i;
+		for (i = GetSize(sig)-1; i > 0; i--)
+			if (sig[i] != sig[i-1])
+				break;
+		// Do not remove non-const sign bit
+		if (sig[i].wire)
+			++i;
+		return sig.extract(0, i);
+	};
+	sigC = unextend(port(dsp, \C, SigSpec()));
+
+	SigSpec P = port(dsp, \P);
+
+    // Only care about those bits that are used
+    int i;
+    for (i = GetSize(P)-1; i >= 0; i--)
+        if (nusers(P[i]) > 1)
+            break;
+    i++;
+    log_assert(nusers(P.extract_end(i)) <= 1);
+    sigP = P.extract(0, i);
+
+	clock = port(dsp, \CLK, SigBit());
+endcode
+
+// (2) Match the driver of the 'C' input to a possible $dff cell (CREG)
+//     (attached to at most two $mux cells that implement clock-enable or
+//      reset functionality, using the in_dffe subpattern)
+code argQ ffC sigC clock
+	argQ = sigC;
+	subpattern(in_dffe);
+	if (dff) {
+		ffC = dff;
+		clock = dffclock;
+		sigC = dffD;
+	}
+endcode
+
+code
+	if (ffC)
+		accept;
+endcode
+
+// #######################
+
+// Subpattern for matching against input registers, based on knowledge of the
+//   'Q' input.
+subpattern in_dffe
+arg argQ clock
+
+code
+	dff = nullptr;
+	if (argQ.empty())
+		reject;
+	for (const auto &c : argQ.chunks()) {
+		// Abandon matches when 'Q' is a constant
+		if (!c.wire)
+			reject;
+		// Abandon matches when 'Q' has the keep attribute set
+		if (c.wire->get_bool_attribute(\keep))
+			reject;
+		// Abandon matches when 'Q' has a non-zero init attribute set
+		// (not supported by DSP48E1)
+		Const init = c.wire->attributes.at(\init, Const());
+		if (!init.empty())
+			for (auto b : init.extract(c.offset, c.width))
+				if (b != State::Sx && b != State::S0)
+					reject;
+	}
+endcode
+
+match ff
+	select ff->type.in($dff, $dffe, $sdff, $sdffe, $adff, $adffe)
+	// does not support clock inversion
+	select param(ff, \CLK_POLARITY).as_bool()
+
+	slice offset GetSize(port(ff, \D))
+	index <SigBit> port(ff, \Q)[offset] === argQ[0]
+
+	// Check that the rest of argQ is present
+	filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
+	filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
+
+	filter clock == SigBit() || port(ff, \CLK) == clock
+endmatch
+
+code argQ
+    // Check that reset value, if present, is fully 0.
+	bool noResetFlop = ff->type.in($dff, $dffe);
+	bool srstZero = ff->type.in($sdff, $sdffe) && param(ff, \SRST_VALUE).is_fully_zero();
+	bool arstZero = ff->type.in($adff, $adffe) && param(ff, \ARST_VALUE).is_fully_zero();
+	bool resetLegal = noResetFlop || srstZero || arstZero;
+	if (resetLegal)
+    {
+        SigSpec Q = port(ff, \Q);
+        dff = ff;
+        dffclock = port(ff, \CLK);
+        dffD = argQ;
+        SigSpec D = port(ff, \D);
+        argQ = Q;
+        dffD.replace(argQ, D);
+    }
+	
+endcode
diff --git a/passes/pmgen/mchp_dsp_cascade.pmg b/passes/pmgen/mchp_dsp_cascade.pmg
new file mode 100644
index 00000000000..172dfb807e7
--- /dev/null
+++ b/passes/pmgen/mchp_dsp_cascade.pmg
@@ -0,0 +1,238 @@
+// ISC License
+// 
+// Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+// 
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+
+// This file describes the third of three pattern matcher setups that
+//   forms the `mchp_dsp` pass described in mchp_dsp.cc
+// At a high level, it works as follows:
+//   (1) Starting from a DSP cell that 
+//         (a) CDIN_FDBK_SEL is set to default "00"
+//         (b) doesn't already use the 'PCOUT' port
+//   (2) Match another DSP cell that 
+//         (a) does not have the CREG enabled,
+//         (b) 'C' port is driven by the 'P' output of the previous DSP cell
+//         (c) has its 'PCIN' port unused
+//   (3) Recursively go to (2) until no more matches possible, keeping track
+//       of the longest possible chain found
+//   (4) The longest chain is then divided into chunks of no more than
+//       MAX_DSP_CASCADE in length (to prevent long cascades that exceed the
+//       height of a DSP column) with each DSP in each chunk being rewritten
+//       to use [ABP]COUT -> [ABP]CIN cascading as appropriate
+
+pattern mchp_dsp_cascade
+
+udata <std::function<SigSpec(const SigSpec&)>> unextend
+udata <vector<std::tuple<Cell*,int>>> chain longest_chain
+udata <std::set<Cell*>> visited
+state <Cell*> next
+state <SigSpec> clock
+
+// Variables used for subpatterns
+state <SigSpec> argQ argD
+state <int> ffoffset
+udata <SigSpec> dffD dffQ
+udata <SigBit> dffclock
+udata <Cell*> dff
+
+// Maximum of 24 cascaded blocks
+code
+#define MAX_DSP_CASCADE 24
+endcode
+
+// NOTE: Chain vector
+//  +--------+      +--------+
+//  | first  |----> |  next  | ----> ...
+//  +--------+      +--------+
+//  first.COUT cascades to next.CIN, so on and so forth
+
+// Helper function to remove unused bits
+code
+    unextend = [](const SigSpec &sig) {
+        int i;
+        for (i = GetSize(sig)-1; i > 0; i--)
+            if (sig[i] != sig[i-1])
+                break;
+        // Do not remove non-const sign bit
+        if (sig[i].wire)
+            ++i;
+        return sig.extract(0, i);
+    };
+endcode
+
+// (1) Starting from a DSP cell that 
+//     (a) CDIN_FDBK_SEL is set to default "00"
+//     (b) doesn't already use the 'PCOUT' port
+match first
+	select first->type.in(\MACC_PA) && port(first, \CDIN_FDBK_SEL, Const(0, 2)) == Const::from_string("00")
+	select nusers(port(first, \CDOUT, SigSpec())) <= 1
+endmatch
+
+// (4) The longest chain is then divided into chunks of no more than
+//     MAX_DSP_CASCADE in length (to prevent long cascades that exceed the
+//     height of a DSP column) with each DSP in each chunk being rewritten
+//     to use [ABP]COUT -> [ABP]CIN cascading as appropriate
+code
+    visited.clear();
+    visited.insert(first);
+
+	longest_chain.clear();
+	chain.emplace_back(first, -1);
+	subpattern(tail);
+finally
+
+    // longest cascade chain has been found with DSP "first" being the head of the chain
+    // do some post processing
+
+	chain.pop_back();
+    visited.clear();
+	log_assert(chain.empty());
+
+	if (GetSize(longest_chain) > 1) {
+		Cell *dsp = std::get<0>(longest_chain.front());
+
+		Cell *dsp_pcin;
+        int SHIFT = -1;
+		for (int i = 1; i < GetSize(longest_chain); i++) {
+            log_assert(dsp->type.in(\MACC_PA));
+
+            std::tie(dsp_pcin,SHIFT) = longest_chain[i];
+
+            // Chain length exceeds the maximum cascade length, must split it up
+			if (i % MAX_DSP_CASCADE > 0) {
+                Wire *cascade = module->addWire(NEW_ID, 48);
+
+                // zero port C and move wire to cascade
+                dsp_pcin->setPort(ID(C), Const(0, 48));
+                dsp_pcin->setPort(ID(CDIN), cascade);
+                dsp->setPort(ID(CDOUT), cascade);
+
+                // Configure wire to cascade the dsps
+                add_siguser(cascade, dsp_pcin);
+                add_siguser(cascade, dsp);
+
+                // configure mux to use cascade for signal E
+                SigSpec cdin_fdbk_sel = port(dsp_pcin, \CDIN_FDBK_SEL, Const(0, 2));
+                cdin_fdbk_sel[1] = State::S1;
+                dsp_pcin->setPort(\CDIN_FDBK_SEL, cdin_fdbk_sel);
+
+                // check if shifting is required for wide multiplier implmentation
+                if (SHIFT == 17)
+                {
+                    dsp_pcin->setPort(\ARSHFT17, State::S1);
+                }
+                
+
+                log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
+
+			} else {
+				log_debug("  Blocking %s -> %s cascade (exceeds max: %d)\n", log_id(dsp), log_id(dsp_pcin), MAX_DSP_CASCADE);
+			}
+
+			dsp = dsp_pcin;
+		}
+
+		accept;
+	}
+endcode
+
+// ------------------------------------------------------------------
+
+subpattern tail
+arg first
+arg next
+
+// (2) Match another DSP cell that 
+//          (a) does not have the CREG enabled,
+//          (b) 'C' port is driven by the 'P' output of the previous DSP cell
+//          (c) has its 'PCIN' port unused
+match nextP
+    // find candidates where nextP.C port is driven (maybe partially) by chain's tail DSP.P port
+    //      and with no registers in between (since cascade path cannot be pipelined)
+
+    // reg C must not be used
+    select port(nextP, \C_BYPASS, SigSpec()).is_fully_ones()
+
+    // must be same DSP type
+    select nextP->type.in(\MACC_PA)
+
+    // port C should be driven by something
+	select nusers(port(nextP, \C, SigSpec())) > 1
+
+    // CIN must be unused
+	select nusers(port(nextP, \PCIN, SigSpec())) == 0
+    
+    // should not have internal feedback connection
+    select port(nextP, \CDIN_FDBK_SEL, SigSpec()).is_fully_zero()
+
+    // SHIFT should be unused
+    select port(nextP, \ARSHFT17_BYPASS).is_fully_ones()
+    select port(nextP, \ARSHFT17).is_fully_zero()
+    select nusers(port(nextP, \ARSHFT17, SigSpec())) == 0
+
+    // current DSP cell can be cascaded with the back of the cascade chain
+	// index <SigBit> port(nextP, \C)[0] === port(std::get<0>(chain.back()), \P)[0] || port(nextP, \C)[0] === port(std::get<0>(chain.back()), \P)[17]
+    filter port(nextP, \C)[0] == port(std::get<0>(chain.back()), \P)[0] || port(nextP, \C)[0] == port(std::get<0>(chain.back()), \P)[17]
+
+	// semioptional
+
+    optional
+endmatch
+
+code next
+	next = nextP;
+
+    // keep DSP type consistent in the chain
+    // currently since we only have one type anyways, this line is always false
+	if (next && next->type != first->type) reject;
+
+    // break infinite recursion when there's a combinational loop
+    if (visited.count(next) > 0) reject;
+
+endcode
+
+// (3) Recursively go to (2) until no more matches possible, recording the
+//     longest possible chain
+code
+	if (next) {
+        SigSpec driver_sigP = port(std::get<0>(chain.back()), \P);
+        int shift = 0;
+        if (port(next, \C)[0] == port(std::get<0>(chain.back()), \P)[17]) shift = 17;
+
+		chain.emplace_back(next, shift);
+        visited.insert(next);
+       
+		SigSpec sigC = unextend(port(next, \C));
+
+            //     Make sure driverDSP.P === DSP.C
+            if (GetSize(sigC) + shift <= GetSize(driver_sigP) && driver_sigP.extract(shift, GetSize(sigC)) == sigC)
+            {
+                subpattern(tail);
+            }
+                
+
+	} else {
+		if (GetSize(chain) > GetSize(longest_chain))
+			longest_chain = chain;
+	}
+finally
+	if (next)
+    {
+        visited.erase(next);
+        chain.pop_back();
+    }
+		
+
+endcode
\ No newline at end of file
diff --git a/techlibs/mchp/LSRAM.txt b/techlibs/mchp/LSRAM.txt
new file mode 100644
index 00000000000..abd274eecec
--- /dev/null
+++ b/techlibs/mchp/LSRAM.txt
@@ -0,0 +1,191 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+
+
+
+# LSRAM true dual-port
+ram block $__LSRAM_TDP_ {
+
+	# Cost of a given cell is assumed to be:
+	#   (cost-widthscale) + [widthscale * (used_bits/14)]
+	cost 129;
+
+	# INIT is supported
+	init any;
+
+	# port A and port B are allowed to have different widths, but they MUST have
+	# 	WIDTH values of the same set. 
+	#      Example: Port A has a Data Width of 1. Then Port B's Data Width must be either
+	#      1, 2, 4, 8, or 16 (both values are in the 'WIDTH_1' set).	
+	# 	WIDTH_1 = {1, 2, 4, 8, 16}
+	# 	WIDTH_2 = {5, 10, 20}
+
+	# "byte" specifies how many data bits correspond to one write enable bit.
+	#		"byte" must be larger than width, or width must be a multipler of "byte"
+	#		if "byte" > WIDTH, a single enable wire is inferred
+	#		otherwise, WIDTH/byte number of enable wires are inferred
+	# 		
+	# 		WIDTH = {1, 2, 4, 5, 8, 10} requires 1 enable wire
+	# 		WIDTH = {16, 20} requires 2 enable wire
+
+	option "WIDTH_CONFIG" "REGULAR" {
+
+		# Data-Width | Address bits
+		# 1			 | 14
+		# 2		     | 13
+		# 4	         | 12
+		# 8	         | 11
+		# 16	     | 10
+
+		# 14 address bits
+		abits 14;
+
+		widths 1 2 4 8 16 per_port;
+		byte 8;
+	}
+	option "WIDTH_CONFIG" "ALIGN" {
+		
+		# Data-Width | Address bits
+		# 5			 | 12
+		# 10		 | 11
+		# 20	     | 10
+
+		# Quick "hack" to fix address bit alignment by setting address bits to 12.
+		#	If abits=14, tool will think there are 14 bits for width=5, 13 bits for width=10, 12 bits for width=20
+		#   THe LSRAM_map.v file detects if this option is being used, and adjusts the address port alignments accordingly.
+		abits 12;
+
+		widths 5 10 20 per_port;
+		byte 10;
+	}
+	
+	
+
+	port srsw "A" "B" {
+
+		# read & write width must be same
+		width tied;
+		
+		# clock polarity is rising
+		clock posedge;
+
+		# A/B read-enable
+		rden;
+
+
+		# initial value of read port data (not supported)
+		rdinit none;
+
+		# write modes (<A/B>_WMODE)
+		# 	1. Simple Write: read-data port holds prev value (similar to "NO_CHANGE" for RAMB18E1)
+		# 	2. Feed-through: read-data port takes new write value (similar to "WRITE_FIRST" for RAMB18E1)
+		# 	3. Read-Before-Write: read-data port holds old value while being written (similar to "READ_FIRST" for RAMB18E1)
+
+		portoption "WRITE_MODE" "NO_CHANGE" {
+
+			# Read-write interaction
+			rdwr no_change;
+
+			# Write transparency:
+			#   For write ports, define behaviour when another synchronous read port 
+			#   reads from the same memory cell that said write port is writing to at the same time. 
+			wrtrans all old;
+		}
+		portoption "WRITE_MODE" "WRITE_FIRST" {
+			# bits corresponding to high A/B_WEN are updated
+			rdwr new_only;
+			wrtrans all new;
+		}
+		portoption "WRITE_MODE" "READ_FIRST" {
+			rdwr old;
+
+			wrtrans all old;
+		}
+
+		# generate params to indicate if read or write is used for each port
+		optional_rw;
+	}
+}
+
+# two-port configuration
+ram block $__LSRAM_SDP_ {
+	
+	# since two-port configuration is dedicated for wide-read/write,
+	#	we want to prioritize this configuration over TDP to avoid tool picking multiple TDP RAMs 
+	#	inplace of a single SDP RAM for wide read/write. This means the cost of a single SDP should
+	#	be less than 2 TDP.
+	cost 129;
+	init any;
+
+	option "WIDTH_CONFIG" "REGULAR" {
+
+		# Data-Width | Address bits
+		# 1			 | 14
+		# 2		     | 13
+		# 4	         | 12
+		# 8	         | 11
+		# 16	     | 10
+		# 32	     | 9
+
+		abits 14;
+
+		widths 1 2 4 8 16 32 per_port;
+
+		# width = 32, byte-write size is 8, ignore other widths
+		byte 8;
+		
+	}
+	option "WIDTH_CONFIG" "ALIGN" {
+		
+		# Data-Width | Address bits
+		# 5			 | 12
+		# 10		 | 11
+		# 20	     | 10
+		# 40	     | 9
+
+		# Same trick as TSP RAM for alignment
+		abits 12;
+		widths 5 10 20 40 per_port;
+		byte 10;
+	}
+
+	port sw "W" {
+
+		# only consider wide write
+		
+		option "WIDTH_CONFIG" "REGULAR" width 32;
+		option "WIDTH_CONFIG" "ALIGN" width 40;
+
+		clock posedge;
+
+		# only simple write supported for two-port mode
+		wrtrans all old;
+		
+		optional;
+	}
+	port sr "R" {
+
+		option "WIDTH_CONFIG" "REGULAR" width 32;
+		option "WIDTH_CONFIG" "ALIGN" width 40;
+
+
+		clock posedge;
+		rden;
+		rdinit none;
+		optional;
+	}
+}
diff --git a/techlibs/mchp/LSRAM_map.v b/techlibs/mchp/LSRAM_map.v
new file mode 100644
index 00000000000..6eaf2f4590b
--- /dev/null
+++ b/techlibs/mchp/LSRAM_map.v
@@ -0,0 +1,323 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// See document PolarFire Family Fabric User Guide
+//   section 4.1 for port list.
+
+
+//LSRAM true dual-port
+module $__LSRAM_TDP_ (...);
+
+parameter INIT = 0;
+parameter ADDR_BITS = 14;
+
+parameter OPTION_WIDTH_CONFIG = "A";
+
+parameter PORT_A_WIDTH = 1;
+parameter PORT_A_WR_EN_WIDTH = 1;
+parameter PORT_A_RD_USED = 0;
+parameter PORT_A_WR_USED = 0;
+parameter PORT_A_OPTION_WRITE_MODE = "NO_CHANGE";
+
+parameter PORT_B_WIDTH = 1;
+parameter PORT_B_WR_EN_WIDTH = 1;
+parameter PORT_B_RD_USED = 0;
+parameter PORT_B_WR_USED = 0;
+parameter PORT_B_OPTION_WRITE_MODE = "NO_CHANGE";
+
+
+input PORT_A_CLK;
+input PORT_A_RD_EN;
+input [ADDR_BITS-1:0] PORT_A_ADDR;
+input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
+input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
+output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
+
+
+input PORT_B_CLK;
+input PORT_B_RD_EN;
+input [ADDR_BITS-1:0] PORT_B_ADDR;
+input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
+input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
+output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
+
+
+`include "brams_defs.vh"
+
+// address wires
+wire [ADDR_BITS-1:0] A_address;
+wire [ADDR_BITS-1:0] B_address;
+assign A_address = (OPTION_WIDTH_CONFIG == "REGULAR") ? PORT_A_ADDR : {PORT_A_ADDR, 2'b00};
+assign B_address = (OPTION_WIDTH_CONFIG == "REGULAR") ? PORT_B_ADDR : {PORT_B_ADDR, 2'b00};
+
+// if port is not used, set block sel to 0 to disable it (read-data output is set to 0)
+parameter PORT_A_RD_USED = 0;
+parameter PORT_A_WR_USED = 0;
+wire [2:0] A_BLK_SEL = (PORT_A_RD_USED == 1 || PORT_A_WR_USED == 1) ?  3'b111 : 3'b000;
+wire [2:0] B_BLK_SEL = (PORT_B_RD_USED == 1 || PORT_B_WR_USED == 1) ?  3'b111 : 3'b000;
+
+// wires for write data 
+generate
+    wire [19:0] A_write_data;
+    wire [19:0] B_write_data;
+    if (PORT_A_WIDTH == 16) begin
+        assign A_write_data[7:0] = PORT_A_WR_DATA[7:0];
+        assign A_write_data[17:10] = PORT_A_WR_DATA[15:8];
+        assign A_write_data[9:8] = 2'b0;
+        assign A_write_data[19:18] = 2'b0;
+    end else begin
+        assign A_write_data[PORT_A_WIDTH-1:0] = PORT_A_WR_DATA;
+    end
+
+    if (PORT_B_WIDTH == 16) begin
+        assign B_write_data[7:0] = PORT_B_WR_DATA[7:0];
+        assign B_write_data[17:10] = PORT_B_WR_DATA[15:8];
+        assign B_write_data[9:8] = 2'b0;
+        assign B_write_data[19:18] = 2'b0;
+    end else begin
+        assign B_write_data[PORT_B_WIDTH-1:0] = PORT_B_WR_DATA;
+    end
+endgenerate
+
+// wires for read data
+wire [19:0] A_read_data;
+assign PORT_A_RD_DATA = A_read_data[PORT_A_WIDTH-1:0];
+wire [19:0] B_read_data;
+assign PORT_B_RD_DATA = B_read_data[PORT_B_WIDTH-1:0];
+
+// byte-write enables
+wire [1:0] A_write_EN = (PORT_A_WR_EN_WIDTH == 1) ? {1'b0, PORT_A_WR_EN} : PORT_A_WR_EN;
+wire [1:0] B_write_EN = (PORT_B_WR_EN_WIDTH == 1) ? {1'b0, PORT_B_WR_EN} : PORT_B_WR_EN;
+
+// port width
+wire [2:0] A_width = (PORT_A_WIDTH == 1) ? 3'b000 :
+                     (PORT_A_WIDTH == 2) ? 3'b001 :
+                     (PORT_A_WIDTH == 4 || PORT_A_WIDTH == 5) ? 3'b010 :
+                     (PORT_A_WIDTH == 8 || PORT_A_WIDTH == 10) ? 3'b011 : 3'b100;
+wire [2:0] B_width = (PORT_B_WIDTH == 1) ? 3'b000 :
+                     (PORT_B_WIDTH == 2) ? 3'b001 :
+                     (PORT_B_WIDTH == 4 || PORT_B_WIDTH == 5) ? 3'b010 :
+                     (PORT_B_WIDTH == 8 || PORT_B_WIDTH == 10) ? 3'b011 : 3'b100;
+
+// write modes
+wire [1:0] A_write_mode = PORT_A_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 : 
+                          PORT_A_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10;
+wire [1:0] B_write_mode = PORT_B_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 : 
+                          PORT_B_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10;
+
+RAM1K20 #(
+    `PARAMS_INIT_LSRAM
+) _TECHMAP_REPLACE_ (
+    
+    // port A
+    .A_ADDR(A_address),
+    .A_BLK_EN(A_BLK_SEL),
+    .A_CLK(PORT_A_CLK),
+    .A_DIN(A_write_data),
+    .A_DOUT(A_read_data),
+    .A_WEN(A_write_EN),
+    .A_REN(PORT_A_RD_EN),
+    .A_WIDTH(A_width),
+    .A_WMODE(A_write_mode),
+    .A_BYPASS(1'b1),
+    .A_DOUT_EN(1'b1),
+    .A_DOUT_SRST_N(1'b1),
+    .A_DOUT_ARST_N(1'b1),
+
+    // port B
+    .B_ADDR(B_address),
+    .B_BLK_EN(B_BLK_SEL),
+    .B_CLK(PORT_B_CLK),
+    .B_DIN(B_write_data),
+    .B_DOUT(B_read_data),
+    .B_WEN(B_write_EN),
+    .B_REN(PORT_B_RD_EN),
+    .B_WIDTH(B_width),
+    .B_WMODE(B_write_mode),
+    .B_BYPASS(1'b1),
+    .B_DOUT_EN(1'b1),
+    .B_DOUT_SRST_N(1'b1),
+    .B_DOUT_ARST_N(1'b1),
+    
+    // Disable ECC for TDP
+    .ECC_EN(1'b0), 
+    .ECC_BYPASS(1'b1),
+    .BUSY_FB(1'b0)
+
+);
+
+endmodule
+
+// single dual port configuration
+module $__LSRAM_SDP_ (...);
+
+parameter INIT = 0;
+parameter OPTION_WIDTH_CONFIG = "REGULAR";
+parameter ADDR_BITS = 14;
+
+parameter PORT_W_WIDTH = 1;
+parameter PORT_W_WR_EN_WIDTH = 4;
+parameter PORT_W_USED = 1;
+
+parameter PORT_R_WIDTH = 1;
+parameter PORT_R_USED = 0;
+
+input PORT_W_CLK;
+input [ADDR_BITS-1:0] PORT_W_ADDR;
+input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
+input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
+
+input PORT_R_CLK;
+input PORT_R_RD_EN;
+input [ADDR_BITS-1:0] PORT_R_ADDR;
+output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
+input PORT_R_RD_SRST;
+
+`include "brams_defs.vh"
+
+
+// address wires
+wire [ADDR_BITS-1:0] A_address;
+wire [ADDR_BITS-1:0] B_address;
+assign A_address = (OPTION_WIDTH_CONFIG == "REGULAR") ? PORT_R_ADDR : {PORT_R_ADDR, 2'b00};
+assign B_address = (OPTION_WIDTH_CONFIG == "REGULAR") ? PORT_W_ADDR : {PORT_W_ADDR, 2'b00};
+
+// if port is not used, set block sel to 0 to disable it (read-data output is set to 0)
+// port A is for read, port B for write
+parameter PORT_W_USED = 0;
+parameter PORT_R_USED = 0;
+wire [2:0] A_BLK_SEL = (PORT_R_USED == 1) ?  3'b111 : 3'b000;
+wire [2:0] B_BLK_SEL = (PORT_W_USED == 1) ?  3'b111 : 3'b000;
+
+// read/write data & write enables
+// Currently support only wide write, width = {32, 40}
+generate
+    wire [19:0] A_write_data;
+    wire [19:0] B_write_data;
+    wire [1:0] A_write_EN;
+    wire [1:0] B_write_EN;
+
+    // write port (A provides MSB) 
+    if (PORT_W_WIDTH == 32) begin
+
+        assign B_write_data[3:0] = PORT_W_WR_DATA[3:0];
+        assign B_write_data[8:5] = PORT_W_WR_DATA[7:4];
+        assign B_write_data[13:10] = PORT_W_WR_DATA[11:8];
+        assign B_write_data[18:15] = PORT_W_WR_DATA[15:12];
+        assign B_write_data[4] = 1'b0;
+        assign B_write_data[9] = 1'b0;
+        assign B_write_data[14] = 1'b0;
+        assign B_write_data[19] = 1'b0;
+
+        assign A_write_data[3:0] = PORT_W_WR_DATA[19:16];
+        assign A_write_data[8:5] = PORT_W_WR_DATA[23:20];
+        assign A_write_data[13:10] = PORT_W_WR_DATA[27:24];
+        assign A_write_data[18:15] = PORT_W_WR_DATA[31:28];
+        assign A_write_data[4] = 1'b0;
+        assign A_write_data[9] = 1'b0;
+        assign A_write_data[14] = 1'b0;
+        assign A_write_data[19] = 1'b0;
+        
+    end else if (PORT_W_WIDTH == 40) begin
+        assign B_write_data = PORT_W_WR_DATA[19:0];
+        assign A_write_data = PORT_W_WR_DATA[39:20];         
+    end
+
+    // byte-write enables
+    assign A_write_EN = PORT_W_WR_EN[1:0];
+    assign B_write_EN = PORT_W_WR_EN[3:2];
+
+    // read ports (A provides MSB)
+    wire [19:0] A_read_data;
+    wire [19:0] B_read_data;
+    if (PORT_R_WIDTH == 32) begin
+        assign PORT_R_RD_DATA[3:0] = B_read_data[3:0];
+        assign PORT_R_RD_DATA[8:5] = B_read_data[7:4];
+        assign PORT_R_RD_DATA[13:10] = B_read_data[11:8];
+        assign PORT_R_RD_DATA[18:15] = B_read_data[15:12];
+
+        assign PORT_R_RD_DATA[19:16] = A_read_data[3:0];
+        assign PORT_R_RD_DATA[23:20] = A_read_data[8:5];
+        assign PORT_R_RD_DATA[27:24] = A_read_data[13:10];
+        assign PORT_R_RD_DATA[31:28] = A_read_data[18:15];
+    end else if (PORT_R_WIDTH == 40) begin
+        assign PORT_R_RD_DATA[19:0] = B_read_data[19:0];
+        assign PORT_R_RD_DATA[39:20] = A_read_data[19:0];
+    end
+    
+endgenerate
+
+// port width
+wire [2:0] A_width = (PORT_R_WIDTH == 1) ? 3'b000 :
+                     (PORT_R_WIDTH == 2) ? 3'b001 :
+                     (PORT_R_WIDTH == 4 || PORT_R_WIDTH == 5) ? 3'b010 :
+                     (PORT_R_WIDTH == 8 || PORT_R_WIDTH == 10) ? 3'b011 : 
+                     (PORT_R_WIDTH == 16 || PORT_R_WIDTH == 20) ? 3'b100 : 3'b101;
+wire [2:0] B_width = (PORT_W_WIDTH == 1) ? 3'b000 :
+                     (PORT_W_WIDTH == 2) ? 3'b001 :
+                     (PORT_W_WIDTH == 4 || PORT_W_WIDTH == 5) ? 3'b010 :
+                     (PORT_W_WIDTH == 8 || PORT_W_WIDTH == 10) ? 3'b011 :
+                     (PORT_W_WIDTH == 16 || PORT_W_WIDTH == 20) ? 3'b100 : 3'b101;
+
+// write modes
+wire [1:0] A_write_mode = 2'b00;
+wire [1:0] B_write_mode = 2'b00;
+
+RAM1K20 #(
+    `PARAMS_INIT_LSRAM
+) _TECHMAP_REPLACE_ (
+    // port A - read
+    .A_ADDR(A_address),
+    .A_BLK_EN(A_BLK_SEL),
+    .A_CLK(PORT_R_CLK),
+    .A_DIN(A_write_data),
+    .A_DOUT(A_read_data),
+    .A_WEN(A_write_EN),
+    .A_REN(PORT_R_RD_EN),
+    .A_WIDTH(A_width),
+    .A_WMODE(A_write_mode),
+    .A_BYPASS(1'b1),
+    .A_DOUT_EN(1'b1),
+    .A_DOUT_SRST_N(1'b1),
+    .A_DOUT_ARST_N(1'b1),
+
+    // port B - write
+    .B_ADDR(B_address),
+    .B_BLK_EN(B_BLK_SEL),
+    .B_CLK(PORT_W_CLK),
+    .B_DIN(B_write_data),
+    .B_DOUT(B_read_data),
+    .B_WEN(B_write_EN),
+    .B_REN(PORT_R_RD_EN),
+    .B_WIDTH(B_width),
+    .B_WMODE(B_write_mode),
+    .B_BYPASS(1'b1),
+    .B_DOUT_EN(1'b1),
+    .B_DOUT_SRST_N(1'b1),
+    .B_DOUT_ARST_N(1'b1),
+    
+    // Disable ECC for SDP
+    .ECC_EN(1'b0), 
+    .ECC_BYPASS(1'b1),
+
+    .BUSY_FB(1'b0)
+
+);
+
+
+endmodule
diff --git a/techlibs/mchp/Makefile.inc b/techlibs/mchp/Makefile.inc
new file mode 100644
index 00000000000..a716caa9f16
--- /dev/null
+++ b/techlibs/mchp/Makefile.inc
@@ -0,0 +1,31 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.  
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+
+
+OBJS += techlibs/mchp/synth_mchp.o
+OBJS += techlibs/mchp/mchp_dffopt.o
+
+$(eval $(call add_share_file,share/mchp,techlibs/mchp/arith_map.v))
+$(eval $(call add_share_file,share/mchp,techlibs/mchp/cells_map.v))
+$(eval $(call add_share_file,share/mchp,techlibs/mchp/cells_sim.v))
+$(eval $(call add_share_file,share/mchp,techlibs/mchp/pf_dsp_map.v))
+
+$(eval $(call add_share_file,share/mchp,techlibs/mchp/brams_defs.vh))
+$(eval $(call add_share_file,share/mchp,techlibs/mchp/LSRAM_map.v))
+$(eval $(call add_share_file,share/mchp,techlibs/mchp/LSRAM.txt))
+$(eval $(call add_share_file,share/mchp,techlibs/mchp/uSRAM_map.v))
+$(eval $(call add_share_file,share/mchp,techlibs/mchp/uSRAM.txt))
diff --git a/techlibs/mchp/arith_map.v b/techlibs/mchp/arith_map.v
new file mode 100644
index 00000000000..d6c289c9224
--- /dev/null
+++ b/techlibs/mchp/arith_map.v
@@ -0,0 +1,105 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Based on Macro Library for PolarFire https://coredocs.s3.amazonaws.com/Libero/2021_2/Tool/pf_mlg.pdf
+// NOTE: prefix module names with \$__ so that mapping prioritizes these cells over internal Yosys cells
+
+
+(* techmap_celltype = "$_MUX4_" *)
+module \$__mchp_MUX4_ (A, B, C, D, S, T, Y);
+	input A, B, C, D, S, T;
+	output Y;
+	MX4 _TECHMAP_REPLACE_.MUX4(.D3(D), .D2(C), .D1(B), .D0(A), .S1(T), .S0(S), .Y(Y));
+
+endmodule
+
+
+(* techmap_celltype = "$reduce_xor" *)
+module \$__mchp_XOR8_ (A, Y);
+	parameter A_SIGNED = 0;
+	parameter A_WIDTH = 0;
+	parameter Y_WIDTH = 0;
+
+	input [A_WIDTH-1:0] A;
+	output [Y_WIDTH-1:0] Y;
+
+	// check if mapping should proceed
+	generate
+		if (A_WIDTH != 8 || A_SIGNED || Y_WIDTH != 1) begin
+			wire _TECHMAP_FAIL_ = 1;
+		end
+	endgenerate
+
+
+	XOR8 _TECHMAP_REPLACE_.XOR8 (.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .E(A[4]), .F(A[5]), .G(A[6]), .H(A[7]), .Y(Y));
+
+	
+endmodule
+
+(* techmap_celltype = "$alu" *)
+module \$__SF2_ALU (A, B, CI, BI, X, Y, CO);
+	parameter A_SIGNED = 0;
+	parameter B_SIGNED = 0;
+	parameter A_WIDTH = 1;
+	parameter B_WIDTH = 1;
+	parameter Y_WIDTH = 1;
+
+	(* force_downto *)
+	input [A_WIDTH-1:0] A;
+	(* force_downto *)
+	input [B_WIDTH-1:0] B;
+	(* force_downto *)
+	output [Y_WIDTH-1:0] X, Y;
+
+	input CI, BI;
+	(* force_downto *)
+	output [Y_WIDTH-1:0] CO;
+
+	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+	(* force_downto *)
+	wire [Y_WIDTH-1:0] AA, BB;
+	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(AA));
+	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(BB));
+
+	(* force_downto *)
+	wire [Y_WIDTH-1:0] C = {CO, CI};
+
+	genvar i;
+	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
+		ARI1 #(
+			// See section 1.4 of PolarFire Macro Library
+
+			// G = F1 = A[i] & (B[i]^BI)
+			// Y = F0 = A[i]^B[i]^BI
+			// P = Y
+			//		 ADCB
+			.INIT(20'b 01_11_0010_1000_1001_0110)
+		) carry (
+			.A(1'b0),
+			.B(AA[i]),
+			.C(BB[i]),
+			.D(BI),
+			.FCI(C[i]),
+			.Y(X[i]),
+			.S(Y[i]),
+			.FCO(CO[i])
+		);
+	end endgenerate
+endmodule
+
diff --git a/techlibs/mchp/brams_defs.vh b/techlibs/mchp/brams_defs.vh
new file mode 100644
index 00000000000..157945fdb9d
--- /dev/null
+++ b/techlibs/mchp/brams_defs.vh
@@ -0,0 +1,48 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+`define PARAMS_INIT_LSRAM \
+	.INIT0(slice_init_LSRAM(00)), \
+	.INIT1(slice_init_LSRAM(01)), \
+	.INIT2(slice_init_LSRAM(02)), \
+	.INIT3(slice_init_LSRAM(03)), \
+	.INIT4(slice_init_LSRAM(04)), \
+	.INIT5(slice_init_LSRAM(05)), \
+	.INIT6(slice_init_LSRAM(06)), \
+	.INIT7(slice_init_LSRAM(07)), \
+	.INIT8(slice_init_LSRAM(08)), \
+	.INIT9(slice_init_LSRAM(09)), \
+	.INIT10(slice_init_LSRAM(10)), \
+	.INIT11(slice_init_LSRAM(11)), \
+	.INIT12(slice_init_LSRAM(12)), \
+	.INIT13(slice_init_LSRAM(13)), \
+	.INIT14(slice_init_LSRAM(14)), \
+	.INIT15(slice_init_LSRAM(15)), \
+	.INIT16(slice_init_LSRAM(16)), \
+	.INIT17(slice_init_LSRAM(17)), \
+	.INIT18(slice_init_LSRAM(18)), \
+	.INIT19(slice_init_LSRAM(19))
+
+// Helper function for initializing the LSRAM
+function [1023:0] slice_init_LSRAM;
+	input integer slice_idx;
+	integer i;
+	for (i = 0; i < 1024; i = i + 1)
+		slice_init_LSRAM[i] = INIT[(slice_idx * 1024 + i)];
+endfunction
+
diff --git a/techlibs/mchp/cells_map.v b/techlibs/mchp/cells_map.v
new file mode 100644
index 00000000000..f52018aef96
--- /dev/null
+++ b/techlibs/mchp/cells_map.v
@@ -0,0 +1,104 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// DFFs
+module \$_DFFE_PN0P_ (input D, C, R, E, output Q);
+  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
+endmodule
+
+module \$_DFFE_PN1P_ (input D, C, R, E, output Q);
+  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
+endmodule
+
+// for sync set/reset registers, we can pass them into ABC9. So we need to follow the simplification idiom
+//    and map to intermediate cell types
+module \$_SDFFCE_PN0P_ (input D, C, R, E, output Q);
+  MCHP_SYNC_RESET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Reset(R), .En(E), .Q(Q));
+endmodule
+
+module \$_SDFFCE_PN1P_ (input D, C, R, E, output Q);
+  MCHP_SYNC_SET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Set(R), .En(E), .Q(Q));
+endmodule
+
+
+// LATCHES
+
+module \$_DLATCH_PN0_ (input D, R, E, output Q);
+  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
+endmodule
+
+module \$_DLATCH_PN1_ (input D, R, E, output Q);
+  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
+endmodule
+
+module \$_DLATCH_P_ (input D, E, output Q);
+  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(1'b1), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
+endmodule
+
+// map intermediate flops to SLE
+`ifdef FINAL_MAP
+module MCHP_SYNC_SET_DFF(
+	input D,
+	input CLK,
+	input Set,
+	input En,
+	output Q);
+  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(CLK), .EN(En), .ALn(1'b1), .ADn(1'b0), .SLn(Set), .SD(1'b1), .LAT(1'b0), .Q(Q));
+endmodule
+
+module MCHP_SYNC_RESET_DFF(
+	input D,
+	input CLK,
+	input Reset,
+	input En,
+	output Q);
+  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(CLK), .EN(En), .ALn(1'b1), .ADn(1'b0), .SLn(Reset), .SD(1'b0), .LAT(1'b0), .Q(Q));
+endmodule
+`endif
+
+
+// LUT
+
+`ifndef NO_LUT
+module \$lut (A, Y);
+  parameter WIDTH = 0;
+  parameter LUT = 0;
+
+  (* force_downto *)
+  input [WIDTH-1:0] A;
+  output Y;
+
+  generate
+    if (WIDTH == 1) begin
+      CFG1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]));
+    end else
+    if (WIDTH == 2) begin
+      CFG2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]));
+    end else
+    if (WIDTH == 3) begin
+      CFG3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]));
+    end else
+    if (WIDTH == 4) begin
+      CFG4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+    end else begin
+      wire _TECHMAP_FAIL_ = 1;
+    end
+  endgenerate
+endmodule
+`endif
+
diff --git a/techlibs/mchp/cells_sim.v b/techlibs/mchp/cells_sim.v
new file mode 100644
index 00000000000..a7a96d86ae9
--- /dev/null
+++ b/techlibs/mchp/cells_sim.v
@@ -0,0 +1,849 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Macro Library for PolarFire https://coredocs.s3.amazonaws.com/Libero/2021_2/Tool/pf_mlg.pdf
+
+module AND2 (
+	input A, B,
+	output Y
+);
+	assign Y = A & B;
+endmodule
+
+module AND3 (
+	input A, B, C,
+	output Y
+);
+	assign Y = A & B & C;
+endmodule
+
+module AND4 (
+	input A, B, C, D,
+	output Y
+);
+	assign Y = A & B & C & D;
+endmodule
+
+(* abc9_lut=1 *)
+module CFG1 (
+	output Y,
+	input A
+);
+	parameter [1:0] INIT = 2'h0;
+	assign Y = INIT >> A;
+  specify
+    (A => Y) = 127;
+  endspecify
+endmodule
+
+(* abc9_lut=2 *)
+module CFG2 (
+	output Y,
+	input A,
+	input B
+);
+	parameter [3:0] INIT = 4'h0;
+	assign Y = INIT >> {B, A};
+  specify
+    (A => Y) = 238;
+    (B => Y) = 127;
+  endspecify
+endmodule
+
+(* abc9_lut=3 *)
+module CFG3 (
+	output Y,
+	input A,
+	input B,
+	input C
+);
+	parameter [7:0] INIT = 8'h0;
+	assign Y = INIT >> {C, B, A};
+  specify
+    (A => Y) = 407;
+    (B => Y) = 238;
+    (C => Y) = 127;
+  endspecify
+endmodule
+
+(* abc9_lut=3 *)
+module CFG4 (
+	output Y,
+	input A,
+	input B,
+	input C,
+	input D
+);
+	parameter [15:0] INIT = 16'h0;
+	assign Y = INIT >> {D, C, B, A};
+  specify
+    (A => Y) = 472;
+    (B => Y) = 407;
+    (C => Y) = 238;
+    (D => Y) = 127;
+  endspecify
+endmodule
+
+module BUFF (
+	input A,
+	output Y
+);
+	assign Y = A;
+endmodule
+
+module BUFD (
+	input A,
+	output Y
+);
+	assign Y = A;
+endmodule
+
+module CLKINT (
+	input A,
+	(* clkbuf_driver *)
+	output Y
+);
+	assign Y = A;
+endmodule
+
+module CLKINT_PRESERVE (
+	input A,
+	(* clkbuf_driver *)
+	output Y
+);
+	assign Y = A;
+endmodule
+
+module GCLKINT (
+	input A, EN,
+	(* clkbuf_driver *)
+	output Y
+);
+	assign Y = A & EN;
+endmodule
+
+module RCLKINT (
+	input A,
+	(* clkbuf_driver *)
+	output Y
+);
+	assign Y = A;
+endmodule
+
+module RGCLKINT (
+	input A, EN,
+	(* clkbuf_driver *)
+	output Y
+);
+	assign Y = A & EN;
+endmodule
+
+// sequential elements
+
+// MCHP_SYNC_SET_DFF and MCHP_SYNC_RESET_DFF are intermediate cell types to implement the simplification idiom for abc9 flow 
+//	see: https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/abc_flow.html
+
+(* abc9_flop, lib_whitebox *)
+module MCHP_SYNC_SET_DFF(
+	input D,
+	input CLK,
+	input Set,
+	input En,
+	output Q);
+	parameter [0:0] INIT = 1'b0; // unused
+	always @(posedge CLK) begin
+		if (En == 1) begin
+			if (Set == 0)
+				Q <= 1;
+			else
+				Q <= D;
+		end
+	end
+
+	specify
+		$setup(D , posedge CLK &&& En && Set, 0);  // neg setup not supported?
+		$setup(En, posedge CLK, 109);
+		$setup(Set, posedge CLK &&& En, 404);
+		if (En && !Set) (posedge CLK => (Q : 1'b1)) = 303;
+		if (En && Set)  (posedge CLK => (Q : D)) = 303;
+  	endspecify
+endmodule
+
+(* abc9_flop, lib_whitebox *)
+module MCHP_SYNC_RESET_DFF(
+	input D,
+	input CLK,
+	input Reset,
+	input En,
+	output Q);
+	parameter [0:0] INIT = 1'b0; // unused
+	always @(posedge C) begin
+		if (En == 1) begin
+			if (Reset == 0) 
+				Q <= 0;
+			else
+				Q <= D;
+		end
+	end
+
+	specify
+		$setup(D , posedge CLK &&& En && Reset, 0);  // neg setup not supported?
+		$setup(En, posedge CLK, 109);
+		$setup(Reset, posedge CLK &&& En, 404);
+		if (En && !Reset) (posedge CLK => (Q : 1'b0)) = 303;
+		if (En && Reset)  (posedge CLK => (Q : D)) = 303;
+  	endspecify
+endmodule
+
+module SLE (
+	output Q,
+	input ADn,
+	input ALn,
+	(* clkbuf_sink *)
+	input CLK,
+	input D,
+	input LAT,
+	input SD,
+	input EN,
+	input SLn
+);
+	reg q_latch, q_ff;
+
+	always @(posedge CLK, negedge ALn) begin
+		if (!ALn) begin
+			q_ff <= !ADn;
+		end else if (EN) begin
+			if (!SLn)
+				q_ff <= SD;
+			else
+				q_ff <= D;
+		end
+	end
+
+	always @* begin
+		if (!ALn) begin
+			q_latch <= !ADn;
+		end else if (CLK && EN) begin
+			if (!SLn)
+				q_ff <= SD;
+			else
+				q_ff <= D;
+		end
+	end
+
+	assign Q = LAT ? q_latch : q_ff;
+endmodule
+
+(* abc9_box, lib_whitebox *)
+module ARI1 (
+	(* abc9_carry *)
+	input FCI,
+	(* abc9_carry *)
+	output FCO,
+
+	input A, B, C, D, 
+	output Y, S
+);
+	parameter [19:0] INIT = 20'h0;
+	wire [2:0] Fsel = {D, C, B};
+	wire F0 = INIT[Fsel];
+	wire F1 = INIT[8 + Fsel];
+	wire Yout = A ? F1 : F0;
+	assign Y = Yout;
+	assign S = FCI ^ Yout;
+	wire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17];
+	wire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0);
+	assign FCO = P ? FCI : G;
+	
+	specify
+		//pin to pin path delay 
+		(A => Y )     = 472;
+		(B => Y )     = 407;
+		(C => Y )     = 238;
+		(D => Y )     = 127;
+		(A => S )     = 572;
+		(B => S )     = 507;
+		(C => S )     = 338;
+		(D => S )     = 227;
+		(FCI => S )   = 100;
+		(A => FCO )   = 522;
+		(B => FCO )   = 457;
+		(C => FCO )   = 288;
+		(D => FCO )   = 177;
+		(FCI => FCO ) = 50;
+	endspecify
+endmodule
+
+// module FCEND_BUFF
+// module FCINIT_BUFF
+// module FLASH_FREEZE
+// module OSCILLATOR
+// module SYSCTRL_RESET_STATUS
+// module LIVE_PROBE_FB
+
+(* blackbox *)
+module GCLKBUF (
+	(* iopad_external_pin *)
+	input PAD,
+	input EN,
+	(* clkbuf_driver *)
+	output Y
+);
+endmodule
+
+(* blackbox *)
+module GCLKBUF_DIFF (
+	(* iopad_external_pin *)
+	input PADP,
+	(* iopad_external_pin *)
+	input PADN,
+	input EN,
+	(* clkbuf_driver *)
+	output Y
+);
+endmodule
+
+(* blackbox *)
+module GCLKBIBUF (
+	input D,
+	input E,
+	input EN,
+	(* iopad_external_pin *)
+	inout PAD,
+	(* clkbuf_driver *)
+	output Y
+);
+endmodule
+
+// module DFN1
+// module DFN1C0
+// module DFN1E1
+// module DFN1E1C0
+// module DFN1E1P0
+// module DFN1P0
+// module DLN1
+// module DLN1C0
+// module DLN1P0
+
+module INV (
+	input A,
+	output Y
+);
+	assign Y = !A;
+endmodule
+
+module INVD (
+	input A,
+	output Y
+);
+	assign Y = !A;
+endmodule
+
+module MX2 (
+	input A, B, S,
+	output Y
+);
+	assign Y = S ? B : A;
+endmodule
+
+module MX4 (
+	input D0, D1, D2, D3, S0, S1,
+	output Y
+);
+	assign Y = S1 ? (S0 ? D3 : D2) : (S0 ? D1 : D0);
+endmodule
+
+module NAND2 (
+	input A, B,
+	output Y
+);
+	assign Y = !(A & B);
+endmodule
+
+module NAND3 (
+	input A, B, C,
+	output Y
+);
+	assign Y = !(A & B & C);
+endmodule
+
+module NAND4 (
+	input A, B, C, D,
+	output Y
+);
+	assign Y = !(A & B & C & D);
+endmodule
+
+module NOR2 (
+	input A, B,
+	output Y
+);
+	assign Y = !(A | B);
+endmodule
+
+module NOR3 (
+	input A, B, C,
+	output Y
+);
+	assign Y = !(A | B | C);
+endmodule
+
+module NOR4 (
+	input A, B, C, D,
+	output Y
+);
+	assign Y = !(A | B | C | D);
+endmodule
+
+module OR2 (
+	input A, B,
+	output Y
+);
+	assign Y = A | B;
+endmodule
+
+module OR3 (
+	input A, B, C,
+	output Y
+);
+	assign Y = A | B | C;
+endmodule
+
+module OR4 (
+	input A, B, C, D,
+	output Y
+);
+	assign Y = A | B | C | D;
+endmodule
+
+module XOR2 (
+	input A, B,
+	output Y
+);
+	assign Y = A ^ B;
+endmodule
+
+module XOR3 (
+	input A, B, C,
+	output Y
+);
+	assign Y = A ^ B ^ C;
+endmodule
+
+module XOR4 (
+	input A, B, C, D,
+	output Y
+);
+	assign Y = A ^ B ^ C ^ D;
+endmodule
+
+module XOR8 (
+	input A, B, C, D, E, F, G, H,
+	output Y
+);
+	assign Y = A ^ B ^ C ^ D ^ E ^ F ^ G ^ H;
+endmodule
+
+// module UJTAG
+
+module BIBUF (
+	input D,
+	input E,
+	(* iopad_external_pin *)
+	inout PAD,
+	output Y
+);
+	parameter IOSTD = "";
+	assign PAD = E ? D : 1'bz;
+	assign Y = PAD;
+endmodule
+
+(* blackbox *)
+module BIBUF_DIFF (
+	input D,
+	input E,
+	(* iopad_external_pin *)
+	inout PADP,
+	(* iopad_external_pin *)
+	inout PADN,
+	output Y
+);
+	parameter IOSTD = "";
+endmodule
+
+module CLKBIBUF (
+	input D,
+	input E,
+	(* iopad_external_pin *)
+	inout PAD,
+	(* clkbuf_driver *)
+	output Y
+);
+	parameter IOSTD = "";
+	assign PAD = E ? D : 1'bz;
+	assign Y = PAD;
+endmodule
+
+module CLKBUF (
+	(* iopad_external_pin *)
+	input PAD,
+	(* clkbuf_driver *)
+	output Y
+);
+	parameter IOSTD = "";
+	assign Y = PAD;
+	specify
+    	(PAD => Y) = 50;
+  	endspecify
+endmodule
+
+(* blackbox *)
+module CLKBUF_DIFF (
+	(* iopad_external_pin *)
+	input PADP,
+	(* iopad_external_pin *)
+	input PADN,
+	(* clkbuf_driver *)
+	output Y
+);
+	parameter IOSTD = "";
+endmodule
+
+module INBUF (
+	(* iopad_external_pin *)
+	input PAD,
+	output Y
+);
+	parameter IOSTD = "";
+	assign Y = PAD;
+endmodule
+
+(* blackbox *)
+module INBUF_DIFF (
+	(* iopad_external_pin *)
+	input PADP,
+	(* iopad_external_pin *)
+	input PADN,
+	output Y
+);
+	parameter IOSTD = "";
+endmodule
+
+module OUTBUF (
+	input D,
+	(* iopad_external_pin *)
+	output PAD
+);
+	parameter IOSTD = "";
+	assign PAD = D;
+endmodule
+
+(* blackbox *)
+module OUTBUF_DIFF (
+	input D,
+	(* iopad_external_pin *)
+	output PADP,
+	(* iopad_external_pin *)
+	output PADN
+);
+	parameter IOSTD = "";
+endmodule
+
+module TRIBUFF (
+	input D,
+	input E,
+	(* iopad_external_pin *)
+	output PAD
+);
+	parameter IOSTD = "";
+	assign PAD = E ? D : 1'bz;
+endmodule
+
+(* blackbox *)
+module TRIBUFF_DIFF (
+	input D,
+	input E,
+	(* iopad_external_pin *)
+	output PADP,
+	(* iopad_external_pin *)
+	output PADN
+);
+	parameter IOSTD = "";
+endmodule
+
+// module DDR_IN
+// module DDR_OUT
+// module RAM1K18
+// module RAM64x18
+// module MACC
+
+(* blackbox *)
+module SYSRESET (
+	(* iopad_external_pin *)
+	input  DEVRST_N,
+	output POWER_ON_RESET_N);
+endmodule
+
+
+(* blackbox *)
+module XTLOSC (
+	(* iopad_external_pin *)
+	input  XTL,
+	output CLKOUT);
+	parameter [1:0] MODE = 2'h3;
+	parameter real FREQUENCY = 20.0;
+endmodule
+
+(* blackbox *)
+module RAM1K18 (
+	input [13:0]  A_ADDR,
+	input [2:0]   A_BLK,
+	(* clkbuf_sink *)
+	input	      A_CLK,
+	input [17:0]  A_DIN,
+	output [17:0] A_DOUT,
+	input [1:0]   A_WEN,
+	input [2:0]   A_WIDTH,
+	input	      A_WMODE,
+	input	      A_ARST_N,
+	input	      A_DOUT_LAT,
+	input	      A_DOUT_ARST_N,
+	(* clkbuf_sink *)
+	input	      A_DOUT_CLK,
+	input	      A_DOUT_EN,
+	input	      A_DOUT_SRST_N,
+
+	input [13:0]  B_ADDR,
+	input [2:0]   B_BLK,
+	(* clkbuf_sink *)
+	input	      B_CLK,
+	input [17:0]  B_DIN,
+	output [17:0] B_DOUT,
+	input [1:0]   B_WEN,
+	input [2:0]   B_WIDTH,
+	input	      B_WMODE,
+	input	      B_ARST_N,
+	input	      B_DOUT_LAT,
+	input	      B_DOUT_ARST_N,
+	(* clkbuf_sink *)
+	input	      B_DOUT_CLK,
+	input	      B_DOUT_EN,
+	input	      B_DOUT_SRST_N,
+
+	input	      A_EN,
+	input	      B_EN,
+	input	      SII_LOCK,
+	output	      BUSY);
+endmodule
+
+(* blackbox *)
+module RAM64x18 (
+	input [9:0]   A_ADDR,
+	input [1:0]   A_BLK,
+	input [2:0]   A_WIDTH,
+	output [17:0] A_DOUT,
+	input	      A_DOUT_ARST_N,
+	(* clkbuf_sink *)
+	input	      A_DOUT_CLK,
+	input	      A_DOUT_EN,
+	input	      A_DOUT_LAT,
+	input	      A_DOUT_SRST_N,
+	(* clkbuf_sink *)
+	input	      A_ADDR_CLK,
+	input	      A_ADDR_EN,
+	input	      A_ADDR_LAT,
+	input	      A_ADDR_SRST_N,
+	input	      A_ADDR_ARST_N,
+
+	input [9:0]   B_ADDR,
+	input [1:0]   B_BLK,
+	input [2:0]   B_WIDTH,
+	output [17:0] B_DOUT,
+	input	      B_DOUT_ARST_N,
+	(* clkbuf_sink *)
+	input	      B_DOUT_CLK,
+	input	      B_DOUT_EN,
+	input	      B_DOUT_LAT,
+	input	      B_DOUT_SRST_N,
+	(* clkbuf_sink *)
+	input	      B_ADDR_CLK,
+	input	      B_ADDR_EN,
+	input	      B_ADDR_LAT,
+	input	      B_ADDR_SRST_N,
+	input	      B_ADDR_ARST_N,
+
+	input [9:0]   C_ADDR,
+	(* clkbuf_sink *)
+	input	      C_CLK,
+	input [17:0]  C_DIN,
+	input	      C_WEN,
+	input [1:0]   C_BLK,
+	input [2:0]   C_WIDTH,
+
+	input	      A_EN,
+	input	      B_EN,
+	input	      C_EN,
+	input	      SII_LOCK,
+	output	      BUSY);
+endmodule
+
+(* blackbox *)
+module MACC_PA (
+  input DOTP,
+  input SIMD,
+  input OVFL_CARRYOUT_SEL,
+  input CLK,
+  input AL_N,
+  input [17:0] A,
+  input A_BYPASS,
+  input A_SRST_N,
+  input A_EN,
+  input [17:0] B,
+  input B_BYPASS,
+  input B_SRST_N,
+  input B_EN,
+  input [17:0] D,
+  input D_BYPASS,
+  input D_ARST_N,
+  input D_SRST_N,
+  input D_EN,
+  input CARRYIN,
+  input [47:0] C,
+  input C_BYPASS,
+  input C_ARST_N,
+  input C_SRST_N,
+  input C_EN,
+  input [47:0] CDIN,
+  output [47:0] P,
+  output OVFL_CARRYOUT,
+  input P_BYPASS,
+  input P_SRST_N,
+  input P_EN,
+  output [47:0] CDOUT,
+  input PASUB,
+  input PASUB_BYPASS,
+  input PASUB_AD_N,
+  input PASUB_SL_N,
+  input PASUB_SD_N,
+  input PASUB_EN,
+  input [1:0] CDIN_FDBK_SEL,
+  input CDIN_FDBK_SEL_BYPASS,
+  input [1:0] CDIN_FDBK_SEL_AD_N,
+  input CDIN_FDBK_SEL_SL_N,
+  input [1:0] CDIN_FDBK_SEL_SD_N,
+  input CDIN_FDBK_SEL_EN,
+  input ARSHFT17,
+  input ARSHFT17_BYPASS,
+  input ARSHFT17_AD_N,
+  input ARSHFT17_SL_N,
+  input ARSHFT17_SD_N,
+  input ARSHFT17_EN,
+  input SUB,
+  input SUB_BYPASS,
+  input SUB_AD_N,
+  input SUB_SL_N,
+  input SUB_SD_N,
+  input SUB_EN
+);
+endmodule
+
+(* blackbox *)
+module RAM1K20 (
+    input  [13:0] A_ADDR,
+    input  [2:0]  A_BLK_EN,
+    input         A_CLK,
+    input  [19:0] A_DIN,
+    output [19:0] A_DOUT,
+    input  [1:0]  A_WEN,
+    input         A_REN,
+    input  [2:0]  A_WIDTH,
+    input  [1:0]  A_WMODE,
+    input         A_BYPASS,
+    input         A_DOUT_EN,
+    input         A_DOUT_SRST_N,
+    input         A_DOUT_ARST_N,
+    input  [13:0] B_ADDR,
+    input  [2:0]  B_BLK_EN,
+    input         B_CLK,
+    input  [19:0] B_DIN,
+    output [19:0] B_DOUT,
+    input  [1:0]  B_WEN,
+    input         B_REN,
+    input  [2:0]  B_WIDTH,
+    input  [1:0]  B_WMODE,
+    input         B_BYPASS,
+    input         B_DOUT_EN,
+    input         B_DOUT_SRST_N,
+    input         B_DOUT_ARST_N,
+    input	      ECC_EN, 
+    input 		  ECC_BYPASS,
+    output        SB_CORRECT,
+    output 		  DB_DETECT,
+    input         BUSY_FB,
+    output        ACCESS_BUSY
+);
+parameter INIT0 = 1024'h0;
+parameter INIT1 = 1024'h0;
+parameter INIT2 = 1024'h0;
+parameter INIT3 = 1024'h0;
+parameter INIT4 = 1024'h0;
+parameter INIT5 = 1024'h0;
+parameter INIT6 = 1024'h0;
+parameter INIT7 = 1024'h0;
+parameter INIT8 = 1024'h0;
+parameter INIT9 = 1024'h0;
+parameter INIT10 = 1024'h0;
+parameter INIT11 = 1024'h0;
+parameter INIT12 = 1024'h0;
+parameter INIT13 = 1024'h0;
+parameter INIT14 = 1024'h0;
+parameter INIT15 = 1024'h0;
+parameter INIT16 = 1024'h0;
+parameter INIT17 = 1024'h0;
+parameter INIT18 = 1024'h0;
+parameter INIT19 = 1024'h0;
+endmodule
+
+(* blackbox *)
+module RAM64x12 (
+	input           R_CLK,
+	input  [5:0]    R_ADDR,
+	input           R_ADDR_BYPASS,
+	input			R_ADDR_EN,
+	input 			R_ADDR_SL_N,
+	input			R_ADDR_SD,
+	input			R_ADDR_AL_N, 
+	input			R_ADDR_AD_N,
+	input           BLK_EN,
+	output [11:0]   R_DATA,
+	input           R_DATA_BYPASS,
+	input	 		R_DATA_EN,
+	input	 		R_DATA_SL_N,
+	input	 		R_DATA_SD,
+	input	 		R_DATA_AL_N,
+	input	 		R_DATA_AD_N,
+
+	input           W_CLK,
+	input  [5:0]    W_ADDR,
+	input  [11:0]   W_DATA,
+	input           W_EN,
+
+	input           BUSY_FB,
+	output          ACCESS_BUSY
+);
+endmodule
\ No newline at end of file
diff --git a/techlibs/mchp/mchp_dffopt.cc b/techlibs/mchp/mchp_dffopt.cc
new file mode 100644
index 00000000000..3e73ea6a3b6
--- /dev/null
+++ b/techlibs/mchp/mchp_dffopt.cc
@@ -0,0 +1,340 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+typedef std::pair<Const, std::vector<SigBit>> LutData;
+
+// Compute a LUT implementing (select ^ select_inv) ? alt_data : data.  Returns true if successful.
+bool merge_lut(LutData &result, const LutData &data, const LutData select, bool select_inv, SigBit alt_data, int max_lut_size) {
+	// First, gather input signals -- insert new signals at the beginning
+	// of the vector, so they don't disturb the likely-critical D LUT input
+	// timings.
+	result.second = data.second;
+	// D lut inputs initially start at 0.
+	int idx_data = 0;
+	// Now add the control input LUT inputs.
+	std::vector<int> idx_sel;
+	for (auto bit : select.second) {
+		int idx = -1;
+		for (int i = 0; i < GetSize(result.second); i++)
+			if (result.second[i] == bit)
+				idx = i;
+		if (idx == -1) {
+			idx = 0;
+			// Insert new signal at the beginning and bump all indices.
+			result.second.insert(result.second.begin(), bit);
+			idx_data++;
+			for (int &sidx : idx_sel)
+				sidx++;
+		}
+		idx_sel.push_back(idx);
+	}
+	// Insert the Q signal, if any, to the slowest input -- it will have
+	// no problem meeting timing.
+	// This is to emulate CLK_EN, where output data is retained
+	int idx_alt = -1;
+	if (alt_data.wire) {
+		// Check if we already have it.
+		for (int i = 0; i < GetSize(result.second); i++)
+			if (result.second[i] == alt_data)
+				idx_alt = i;
+		// If not, add it.
+		if (idx_alt == -1) {
+			idx_alt = 0;
+			result.second.insert(result.second.begin(), alt_data);
+			idx_data++;
+			for (int &sidx : idx_sel)
+				sidx++;
+		}
+	}
+
+	// If LUT would be too large, bail.
+	if (GetSize(result.second) > max_lut_size)
+		return false;
+
+	// Okay, we're doing it — compute the LUT mask.
+	result.first = Const(0, 1 << GetSize(result.second));
+	for (int i = 0; i < GetSize(result.first); i++) {
+		int sel_lut_idx = 0;
+		for (int j = 0; j < GetSize(select.second); j++)
+			if (i & 1 << idx_sel[j])
+				sel_lut_idx |= 1 << j;
+		bool select_val = (select.first.bits[sel_lut_idx] == State::S1);
+		bool new_bit;
+		if (select_val ^ select_inv) {
+			// Use alt_data.
+			if (alt_data.wire)
+				new_bit = (i & 1 << idx_alt) != 0;
+			else
+				new_bit = alt_data.data == State::S1;
+		} else {
+			// Use original LUT.
+			int lut_idx = i >> idx_data & ((1 << GetSize(data.second)) - 1);
+			new_bit = data.first.bits[lut_idx] == State::S1;
+		}
+		result.first.bits[i] = new_bit ? State::S1 : State::S0;
+	}
+	return true;
+}
+
+struct MchpDffOptPass : public Pass {
+	MchpDffOptPass() : Pass("mchp_dffopt", "MCHP: optimize FF control signal usage") { }
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    mchp_dffopt [options] [selection]\n");
+		log("\n");
+		log("Converts hardware clock enable and set/reset signals on FFs to emulation\n");
+		log("using LUTs, if doing so would improve area. Operates on post-techmap LUT, DFF\n");
+		log("cells. \n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		log_header(design, "Executing MCHP_DFFOPT pass (optimize FF control signal usage).\n");
+
+		size_t argidx;
+		int max_lut_size = 4;
+		
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+		{
+			log("Optimizing FFs in %s.\n", log_id(module));
+
+			SigMap sigmap(module);
+			dict<SigBit, pair<LutData, Cell *>> bit_to_lut;
+			dict<SigBit, int> bit_uses;
+
+			// Gather LUTs.
+			for (auto cell : module->selected_cells())
+			{
+				for (auto port : cell->connections())
+					for (auto bit : port.second)
+						bit_uses[sigmap(bit)]++;
+				if (cell->get_bool_attribute(ID::keep))
+					continue;
+				if (cell->type == ID(INV)) {
+					SigBit sigout = sigmap(cell->getPort(ID::Y));
+					SigBit sigin = sigmap(cell->getPort(ID::A));
+					bit_to_lut[sigout] = make_pair(LutData(Const(1, 2), {sigin}), cell); // INIT = 01
+				} else if (cell->type.in(ID(CFG1), ID(CFG2), ID(CFG3), ID(CFG4))) {
+					SigBit sigout = sigmap(cell->getPort(ID::Y));
+					const Const &init = cell->getParam(ID::INIT);
+					std::vector<SigBit> sigin;
+					sigin.push_back(sigmap(cell->getPort(ID(A))));
+					if (cell->type == ID(CFG1))
+						goto lut_sigin_done;
+					sigin.push_back(sigmap(cell->getPort(ID(B))));
+					if (cell->type == ID(CFG2))
+						goto lut_sigin_done;
+					sigin.push_back(sigmap(cell->getPort(ID(C))));
+					if (cell->type == ID(CFG3))
+						goto lut_sigin_done;
+					sigin.push_back(sigmap(cell->getPort(ID(D))));
+					
+lut_sigin_done:
+					bit_to_lut[sigout] = make_pair(LutData(init, sigin), cell);
+				}
+			}
+			for (auto wire : module->wires())
+				if (wire->port_output || wire->port_input)
+					for (int i = 0; i < GetSize(wire); i++)
+						bit_uses[sigmap(SigBit(wire, i))]++;
+
+			// Iterate through FFs.
+			for (auto cell : module->selected_cells())
+			{
+				
+				if (!cell->type.in(ID(SLE)))  // not a SLE
+					continue;
+				if (cell->getPort(ID(LAT)).is_fully_ones()) // skip latch
+				  	continue;
+				if (cell->get_bool_attribute(ID::keep)) // keep attribute
+					continue;
+				if (!cell->getPort(ID(ALn)).is_fully_ones()) // async FF
+					continue; 
+
+					
+				const bool hasSyncLoad = cell->getPort(ID(SLn)).is_wire();
+				const bool has_s = hasSyncLoad && cell->getPort(ID(SD)).is_fully_ones();
+				const bool has_r = hasSyncLoad && cell->getPort(ID(SD)).is_fully_zero();
+				
+				// SLE cannot have both synchronous set and reset implemented at the same time
+				log_assert(!(has_s && has_r));
+
+				// Don't bother if D has more than one use.
+				SigBit sig_D = sigmap(cell->getPort(ID::D));
+				if (bit_uses[sig_D] > 2)
+					continue;
+
+				// Find the D LUT.
+				auto it_D = bit_to_lut.find(sig_D);
+				if (it_D == bit_to_lut.end())
+					continue;
+				LutData lut_d = it_D->second.first;
+				Cell *cell_d = it_D->second.second;
+
+
+				LutData lut_d_post_ce;
+				LutData lut_d_post_s;
+				LutData lut_d_post_r;
+				bool worthy_post_ce = false;
+				bool worthy_post_s = false;
+				bool worthy_post_r = false;
+
+				// First, unmap CE.
+				SigBit sig_Q = sigmap(cell->getPort(ID::Q));
+				SigBit sig_CE = sigmap(cell->getPort(ID(EN)));
+				LutData lut_ce = LutData(Const(2, 2), {sig_CE}); // INIT = 10
+				auto it_CE = bit_to_lut.find(sig_CE);
+				if (it_CE != bit_to_lut.end())
+					lut_ce = it_CE->second.first;
+				if (sig_CE.wire) {
+					// Merge CE LUT and D LUT into one.  If it cannot be done, nothing to do about this FF.
+					if (!merge_lut(lut_d_post_ce, lut_d, lut_ce, true, sig_Q, max_lut_size))
+						continue;
+
+					// If this gets rid of a CE LUT, it's worth it.  If not, it still may be worth it, if we can remove set/reset as well.
+					if (it_CE != bit_to_lut.end())
+						worthy_post_ce = true;
+				} else if (sig_CE.data != State::S1) {
+					// Strange.  Should not happen in a reasonable flow, so bail.
+					continue;
+				} else {
+					lut_d_post_ce = lut_d;
+				}
+
+				// Second, unmap S, if any.
+				lut_d_post_s = lut_d_post_ce;
+				if (has_s) {
+					SigBit sig_S = sigmap(cell->getPort(ID(SLn)));
+					LutData lut_s = LutData(Const(2, 2), {sig_S}); // INIT = 10
+					bool inv_s = true; // active low
+					auto it_S = bit_to_lut.find(sig_S);
+					if (it_S != bit_to_lut.end())
+						lut_s = it_S->second.first;
+					if (sig_S.wire) {
+						// Merge S LUT and D LUT into one.  If it cannot be done, try to at least merge CE.
+						if (!merge_lut(lut_d_post_s, lut_d_post_ce, lut_s, inv_s, SigBit(State::S1), max_lut_size))
+							goto unmap;
+						// If this gets rid of an S LUT, it's worth it.
+						if (it_S != bit_to_lut.end())
+							worthy_post_s = true;
+					} else if (sig_S.data != (inv_s ? State::S1 : State::S0)) {
+						// Strange.  Should not happen in a reasonable flow, so bail.
+						continue;
+					}
+				}
+
+				// Third, unmap R, if any.
+				lut_d_post_r = lut_d_post_s;
+				if (has_r) {
+					SigBit sig_R = sigmap(cell->getPort(ID(SLn)));
+					LutData lut_r = LutData(Const(2, 2), {sig_R}); // INIT = 10
+					bool inv_r = true; // active low
+					auto it_R = bit_to_lut.find(sig_R);
+					if (it_R != bit_to_lut.end())
+						lut_r = it_R->second.first;
+					if (sig_R.wire) {
+						// Merge R LUT and D LUT into one.  If it cannot be done, try to at least merge CE/S.
+						if (!merge_lut(lut_d_post_r, lut_d_post_s, lut_r, inv_r, SigBit(State::S0), max_lut_size))
+							goto unmap;
+						// If this gets rid of an S LUT, it's worth it.
+						if (it_R != bit_to_lut.end())
+							worthy_post_r = true;
+					} else if (sig_R.data != (inv_r ? State::S1 : State::S0)) {
+						// Strange.  Should not happen in a reasonable flow, so bail.
+						continue;
+					}
+				}
+
+unmap:
+
+				// SLE cannot have both synchronous set and reset implemented at the same time
+				log_assert(!(worthy_post_r && worthy_post_s));
+
+				LutData final_lut;
+				if (worthy_post_r) {
+					final_lut = lut_d_post_r;
+				} else if (worthy_post_s) {
+					final_lut = lut_d_post_s;
+				} else if (worthy_post_ce) {
+					final_lut = lut_d_post_ce;
+				} else {
+					// Nothing to do here.
+					continue;
+				}
+
+				std::string ports;
+				if (worthy_post_r) ports += " + R";
+				if (worthy_post_s) ports += " + S";
+				if (worthy_post_ce) ports += " + CE";
+				log("  Merging D%s LUTs for %s/%s (%d -> %d)\n", ports.c_str(), log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
+
+				// Okay, we're doing it.  Unmap ports.
+				if ((has_s && worthy_post_s) || worthy_post_r) {
+					cell->setPort(ID(SLn), Const(1, 1));
+				}
+
+				// if we made it this far, clk enable is always merged into D
+				cell->setPort(ID(EN), Const(1, 1));
+
+				// Create the new LUT.
+				Cell *lut_cell = nullptr;
+				switch (GetSize(final_lut.second)) {
+					case 1:
+						lut_cell = module->addCell(NEW_ID, ID(CFG1));
+						break;
+					case 2:
+						lut_cell = module->addCell(NEW_ID, ID(CFG2));
+						break;
+					case 3:
+						lut_cell = module->addCell(NEW_ID, ID(CFG3));
+						break;
+					case 4:
+						lut_cell = module->addCell(NEW_ID, ID(CFG4));
+						break;
+					default:
+						log_assert(!"unknown lut size");
+				}
+				lut_cell->attributes = cell_d->attributes;
+				Wire *lut_out = module->addWire(NEW_ID);
+				lut_cell->setParam(ID::INIT, final_lut.first);
+				cell->setPort(ID::D, lut_out);
+				lut_cell->setPort(ID::Y, lut_out);
+				lut_cell->setPort(ID(A), final_lut.second[0]);
+				if (GetSize(final_lut.second) >= 2)
+					lut_cell->setPort(ID(B), final_lut.second[1]);
+				if (GetSize(final_lut.second) >= 3)
+					lut_cell->setPort(ID(C), final_lut.second[2]);
+				if (GetSize(final_lut.second) >= 4)
+					lut_cell->setPort(ID(D), final_lut.second[3]);
+			}
+		}
+	}
+} MchpDffOptPass;
+
+PRIVATE_NAMESPACE_END
+
diff --git a/techlibs/mchp/pf_dsp_map.v b/techlibs/mchp/pf_dsp_map.v
new file mode 100644
index 00000000000..a6b65a421af
--- /dev/null
+++ b/techlibs/mchp/pf_dsp_map.v
@@ -0,0 +1,95 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
+	parameter A_SIGNED = 0;
+	parameter B_SIGNED = 0;
+	parameter A_WIDTH = 0;
+	parameter B_WIDTH = 0;
+	parameter Y_WIDTH = 0;
+
+	wire [47:0] P_48;
+    // For pin descriptions, see Section 9 of PolarFire FPGA Macro Library Guide:
+    // https://coredocs.s3.amazonaws.com/Libero/2021_2/Tool/pf_mlg.pdf
+	MACC_PA _TECHMAP_REPLACE_ (
+		.DOTP(1'b0), 
+        .SIMD(1'b0), 
+        .OVFL_CARRYOUT_SEL(1'b0), 
+
+        .AL_N(1'b1),
+        .A(A),
+        .A_BYPASS(1'b1),
+        .A_SRST_N(1'b1),
+        .A_EN(1'b1),
+
+        .B(B),
+        .B_BYPASS(1'b1),
+        .B_SRST_N(1'b1),
+        .B_EN(1'b1),
+
+        .D(18'b0),
+        .D_BYPASS(1'b1),
+        .D_ARST_N(1'b1),
+        .D_SRST_N(1'b1),
+        .D_EN(1'b1),
+        
+        .CARRYIN(1'b0),
+        .C(48'b0),
+        .C_BYPASS(1'b1),
+        .C_ARST_N(1'b1),
+        .C_SRST_N(1'b1),
+        .C_EN(1'b1),
+
+        
+        .P(P_48),
+
+        .P_BYPASS(1'b1),
+        .P_SRST_N(1'b1),
+        .P_EN(1'b1),
+
+        .PASUB(1'b0),
+        .PASUB_BYPASS(1'b1),
+        .PASUB_AD_N(1'b0),
+        .PASUB_SL_N(1'b1),
+        .PASUB_SD_N(1'b0),
+        .PASUB_EN(1'b1),
+
+        .CDIN_FDBK_SEL(2'b00),
+        .CDIN_FDBK_SEL_BYPASS(1'b1),
+        .CDIN_FDBK_SEL_AD_N(2'b00),
+        .CDIN_FDBK_SEL_SL_N(1'b1),
+        .CDIN_FDBK_SEL_SD_N(2'b00),
+        .CDIN_FDBK_SEL_EN(1'b1),
+
+        .ARSHFT17(1'b0),
+        .ARSHFT17_BYPASS(1'b1),
+        .ARSHFT17_AD_N(1'b0),
+        .ARSHFT17_SL_N(1'b1),
+        .ARSHFT17_SD_N(1'b0),
+        .ARSHFT17_EN(1'b1),
+
+        .SUB(1'b0),
+        .SUB_BYPASS(1'b1),
+        .SUB_AD_N(1'b0),
+        .SUB_SL_N(1'b1),
+        .SUB_SD_N(1'b0),
+        .SUB_EN(1'b1)
+
+	);
+	assign Y = P_48;
+endmodule
diff --git a/techlibs/mchp/synth_mchp.cc b/techlibs/mchp/synth_mchp.cc
new file mode 100644
index 00000000000..e5fe7d48445
--- /dev/null
+++ b/techlibs/mchp/synth_mchp.cc
@@ -0,0 +1,543 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+#include "kernel/register.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SynthMchpPass : public ScriptPass
+{
+	SynthMchpPass() : ScriptPass("synth_mchp", "synthesis for Microchip FPGAs") { }
+
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    synth_mchp [options]\n");
+		log("\n");
+		log("This command runs synthesis for Microchip FPGAs. Operating on\n");
+		log("partly selected designs is not supported (you must submit a fully-selected \n");
+		log("design). This command creates netlists that are compatible with Microchip \n");
+		log("PolarFire devices.\n");
+		log("\n");
+		log("    -top <module>\n");
+		log("        use the specified module as the top module\n");
+		log("\n");
+		log("    -family <family>\n");
+		log("        Run synthesis for the specified Microchip architecture. \n");
+		log("        Generate the synthesis netlist for the specified family.\n");
+		log("        supported values:\n");
+		log("        - pf: PolarFire\n");
+		log("\n");
+		log("    -edif <file>\n");
+		log("        Write the design to the specified edif file. Writing of an output file\n");
+		log("        is omitted if this parameter is not specified.\n");
+		log("\n");
+		log("    -blif <file>\n");
+		log("        Write the design to the specified BLIF file. Writing of an output file\n");
+		log("        is omitted if this parameter is not specified.\n");		
+		log("\n");
+		log("    -nobram\n");
+		log("        Do not use block RAM cells in output netlist\n");
+		log("\n");
+		log("    -nocarry\n");
+		log("        Do not use ARI1 cells in output netlist\n");
+		log("\n");
+		log("    -nodsp\n");
+		log("        Do not use MATH blocks to implement multipliers and associated logic\n");
+		log("\n");
+		log("    -noiopad\n");
+		log("        Disable I/O buffer insertion (useful for hierarchical or \n");
+		log("        out-of-context flows)\n");
+		log("\n");
+		log("    -noclkbuf\n");
+		log("        Disable automatic clock buffer insertion\n");
+		log("\n");
+		log("    -run <from_label>:<to_label>\n");
+		log("        Only run the commands between the labels (see below). an empty\n");
+		log("        'from_label' is synonymous to 'begin', and empty 'to_label' is\n");
+		log("        synonymous to the end of the command list.\n");
+		log("\n");
+		log("    -flatten\n");
+		log("        Flatten design before synthesis.\n");
+		log("\n");
+		log("    -flatten_before_abc\n");
+		log("        Flatten design before abc tech mapping.\n");
+		log("\n");
+		log("    -dff\n");
+		log("        Run 'abc'/'abc9' with -dff option\n");
+		log("\n");
+		log("    -retime\n");
+		log("        Run 'abc' with '-D 1' option to enable flip-flop retiming.\n");
+		log("        implies -dff.\n");
+		log("\n");
+		log("    -abc9\n");
+		log("        Use new ABC9 flow (EXPERIMENTAL)\n");
+		log("\n");
+		log("\n");
+		log("The following commands are executed by this synthesis command:\n");
+		help_script();
+		log("\n");
+	}
+
+	std::string top_opt, edif_file, blif_file, family;
+	bool flatten, retime, noiopad, noclkbuf, nobram, nocarry, nowidelut, nodsp;
+	bool abc9, dff;
+	bool flatten_before_abc;
+	int lut_size;
+
+	// debug dump switches
+	bool debug_memory, debug_carry;
+
+	void clear_flags() override
+	{
+		top_opt = "-auto-top";
+		edif_file.clear();
+		blif_file.clear();
+		family = "pf";
+		flatten = false;
+		retime = false;
+		noiopad = false;
+		noclkbuf = false;
+		nocarry = false;
+		nobram = false;
+		nowidelut = false;
+		nodsp = false;
+		abc9 = false;
+		dff = false;
+		flatten_before_abc = false;
+		lut_size = 4;
+
+		debug_memory = false;
+		debug_carry = false;
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		std::string run_from, run_to;
+		clear_flags();
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-top" && argidx+1 < args.size()) {
+				top_opt = "-top " + args[++argidx];
+				continue;
+			}
+			if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
+				family = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-edif" && argidx+1 < args.size()) {
+				edif_file = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-blif" && argidx+1 < args.size()) {
+				blif_file = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-run" && argidx+1 < args.size()) {
+				size_t pos = args[argidx+1].find(':');
+				if (pos == std::string::npos)
+					break;
+				run_from = args[++argidx].substr(0, pos);
+				run_to = args[argidx].substr(pos+1);
+				continue;
+			}
+			if (args[argidx] == "-flatten") {
+				flatten = true;
+				continue;
+			}
+			if (args[argidx] == "-flatten_before_abc") {
+				flatten_before_abc = true;
+				continue;
+			}
+			if (args[argidx] == "-retime") {
+				dff = true;
+				retime = true;
+				continue;
+			}
+			if (args[argidx] == "-nocarry") {
+				nocarry = true;
+				continue;
+			}
+			if (args[argidx] == "-nowidelut") {
+				nowidelut = true;
+				continue;
+			}
+			if (args[argidx] == "-iopad") {
+				continue;
+			}
+			if (args[argidx] == "-noiopad") {
+				noiopad = true;
+				continue;
+			}
+			if (args[argidx] == "-noclkbuf") {
+				noclkbuf = true;
+				continue;
+			}
+			if (args[argidx] == "-nocarry") {
+				nocarry = true;
+				continue;
+			}
+			if (args[argidx] == "-nobram") {
+				nobram = true;
+				continue;
+			}
+			if (args[argidx] == "-abc9") {
+				abc9 = true;
+				continue;
+			}
+			if (args[argidx] == "-nodsp") {
+				nodsp = true;
+				continue;
+			}
+			if (args[argidx] == "-dff") {
+				dff = true;
+				continue;
+			}
+			if (args[argidx] == "-debug_memory") {
+				debug_memory = true;
+				continue;
+			}
+			if (args[argidx] == "-debug_carry") {
+				debug_carry = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		if (family == "pf") {
+			lut_size = 4;
+		} else {
+			log_cmd_error("Invalid Microchip -family setting: '%s'.\n", family.c_str());
+        }
+
+		if (!design->full_selection())
+			log_cmd_error("This command only operates on fully selected designs!\n");
+
+		if (abc9 && retime)
+			log_cmd_error("-retime option not currently compatible with -abc9!\n");
+
+
+		log_header(design, "Executing SYNTH_MCHP pass.\n");
+		log_push();
+
+		run_script(design, run_from, run_to);
+
+		log_pop();
+	}
+
+	void script() override
+	{
+		std::string lut_size_s = std::to_string(lut_size);
+		if (help_mode)
+			lut_size_s = "[4]";
+
+		if (check_label("begin")) {
+			std::string read_args;
+			read_args += " -lib -specify +/mchp/cells_sim.v";
+			run("read_verilog" + read_args);
+
+			run(stringf("hierarchy -check %s", top_opt.c_str()));
+		}
+
+		if (check_label("prepare")) {
+			run("proc");
+			if (flatten || help_mode)
+				run("flatten", "(with '-flatten')");
+			if (active_design)
+				active_design->scratchpad_unset("tribuf.added_something");
+			run("tribuf -logic");
+			if (noiopad && active_design && active_design->scratchpad_get_bool("tribuf.added_something"))
+				log_error("Tristate buffers are unsupported without the '-iopad' option.\n");
+			run("deminout");
+			run("opt_expr");
+			run("opt_clean");
+			run("check");
+			run("opt -nodffe -nosdff");
+			run("fsm");
+			run("opt");
+
+			run("wreduce");
+			run("peepopt");
+			run("opt_clean");
+		}
+
+		if (check_label("map_dsp", "(skip if '-nodsp')")) {
+			if (!nodsp || help_mode) {
+				run("memory_dff"); // mchp_dsp will merge registers, reserve memory port registers first
+				if (help_mode)
+					run("techmap -map +/mul2dsp.v -map +/mchp/{family}_dsp_map.v {options}");
+				else if (family == "pf") // Microchip - map multipliers to DSP
+					run("techmap -map +/mul2dsp.v -map +/mchp/pf_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
+						"-D DSP_A_MAXWIDTH_PARTIAL=18 "	// Partial multipliers are intentionally
+										// limited to 18x18 in order to take
+										// advantage of the (PCOUT >> 17) -> PCIN
+										// dedicated cascade chain capability
+						"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
+						"-D DSP_Y_MINWIDTH=9 "
+						"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18");
+				
+				run("select a:mul2dsp");
+				run("setattr -unset mul2dsp");
+				run("opt_expr -fine");
+				run("wreduce");
+				run("select -clear");
+				if (help_mode)
+					run("mchp_dsp -family <family>");
+				else if (family == "pf") // Microchip - absorb cells into DSP
+					run("mchp_dsp -family " + family);
+				
+				run("chtype -set $mul t:$__soft_mul");
+			}
+		}
+
+		if (check_label("coarse")) {
+			run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=" + lut_size_s);
+			run("alumacc");
+			run("share");
+			run("opt");
+			run("memory -nomap");
+			run("opt_clean");
+		}
+
+		if (check_label("map_memory")) {
+			std::string params = "";
+			std::string LSRAM_map = "+/mchp/LSRAM_map.v";
+			std::string uSRAM_map = "+/mchp/uSRAM_map.v";
+			if (debug_memory) run("write_verilog -noexpr memory_map_pre.vm");
+			if (help_mode) {
+				params = " [...]";
+			} else {
+
+				if (family == "pf") {
+					// cost of a single bit for memory lowered to soft logic
+					params += " -logic-cost-rom 0.015625"; 
+
+					params += " -lib +/mchp/LSRAM.txt";
+					params += " -lib +/mchp/uSRAM.txt";
+					LSRAM_map = "+/mchp/LSRAM_map.v";
+					uSRAM_map = "+/mchp/uSRAM_map.v";
+				}
+				if (nobram) params += " -no-auto-block";
+			}
+
+			// transform memories into intermediate cells
+			// Cost based transformation. The cost is assigned by us for each cell.
+			run("memory_libmap" + params);
+			if (debug_memory) run("write_verilog -noexpr memory_map_libmap.vm");
+
+			// map intermediate cells to actual RAM macros
+			// NOTE: order doesnt matter here
+			run("techmap -map " + LSRAM_map);
+			run("techmap -map " + uSRAM_map);
+			if (debug_memory)  run("write_verilog -noexpr memory_map_final.vm");
+		}
+
+		if (check_label("map_ffram")) {
+			run("opt -fast -full");
+
+
+			// blast unmapped RAM to flops or LUTs
+			run("memory_map");
+		}
+
+		if (check_label("fine")) {
+			run("opt -full");
+
+			if (debug_carry) run("write_verilog -noexpr ARI1_cells.vm");
+
+			if (!nocarry) {
+				// converts $mux -> $_MUX_ to allow muxcover to work
+				run("simplemap t:$mux");
+
+				// converts $and/$or/$xor to gate representation for extract_reduce to work
+				run("simplemap t:$xor"); // only mapping reduce_xor
+
+				// mapping based on Yosys internal gates
+				if (debug_carry) run("write_verilog -noexpr ARI1_pre.vm");
+
+				// collapse $_AND_/$_OR_/$_XOR_ chains into reduction cells
+				run("extract_reduce");
+
+				if (debug_carry) run("write_verilog -noexpr ARI1_extract_reduce.vm");
+				
+				// pack mux trees into $_MUX4_
+				run("muxcover -nodecode -mux4=220");
+
+				if (debug_carry) run("write_verilog -noexpr ARI1_muxcover.vm");
+				
+				run("techmap -map +/mchp/arith_map.v");
+				if (debug_carry) run("write_verilog -noexpr ARI1_post.vm");
+				
+			}
+
+			// convert all remaining cells to gates
+			run("techmap -map +/techmap.v");
+
+			run("opt -fast");
+		}
+
+		if (check_label("map_cells")) {
+			// Needs to be done before logic optimization, so that inverters (inserted
+			// 			here because of negative-polarity output enable) are handled.
+			if (help_mode || !noiopad) {
+				run("iopadmap -bits -inpad INBUF Y:PAD -outpad OUTBUF D:PAD -toutpad TRIBUFF E:D:PAD -tinoutpad BIBUF E:Y:D:PAD", "(unless -noiobs)");
+			}
+				
+			std::string techmap_args = "-map +/techmap.v -map +/mchp/cells_map.v";
+			run("techmap " + techmap_args);
+			run("clean");
+		}
+
+		if (check_label("map_ffs")) {
+			// dfflegalize : Converts FFs to types supported by the target
+			// 		this can convert less capable cells into more capable cells (e.g. dff -> dffe)
+
+			// Based on PolarFire® FPGA Macro Library Guide
+			// D-flop:
+			// 		active high enable
+			// 		active low clear or active low set
+			// Latch:
+			//		active low clear or active low set
+			// SLE (can implement D-flop/Latch):
+			//		active high EN
+			//		active low async load (set/reset) with static load configuration via ADn (Q = ~ADn)
+			//		active low sync load (set/reset) with static load configuration via SD
+			//		static latch configuration bit
+			// init not supported
+
+			// Yosys internal cell description
+			// 		see: https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/formats/cell_library.html
+			//		see: common/simcells.v
+			// $_DFF_[NP]_ 						(regular dff)
+			// $_DFFE_[NP][NP]_ 				(enable)
+			// $_DFF_[NP][NP][01]_ 				(async reset to 0/1)
+			// $_DFFE_[NP][NP][01][NP]_ 		(async reset to 0/1 + enable)
+			// $_ALDFF_[NP][NP]_				(async load)
+			// $_ALDFFE_[NP][NP][NP]_			(async load + enable)
+			// $_DFFSR_[NP][NP][NP]_			(async set & reset)
+			// $_DFFSRE_[NP][NP][NP][NP]_		(async set & reset + enable)
+			// $_SDFF_[NP][NP][01]_				(sync reset to 0/1)
+			// $_SDFFE_[NP][NP][01][NP]_		(sync reset to 0/1 + enable, reset prioritize over enable)
+			// $_SDFFCE_[NP][NP][01][NP]_		(sync reset to 0/1 + enable, enable prioritize over reset)
+			// $_SR_[NP][NP]_					(set/reset latch)
+			// $_DLATCH_[NP]_					(D-latch)
+			// $_DLATCH_[NP][NP][01]_			(D-latch + reset to 0/1)
+			// $_DLATCHSR_[NP][NP][NP]_			(D-latch + set + reset)
+
+			
+			if (family == "pf") {
+				std::string params = "";
+				
+
+				// D-flop with async reset and enable
+				// posedge CLK, active low reset to 1 or 0, active high EN
+				params += " -cell $_DFFE_PN?P_ 01"; 
+
+				// D-flop with sync reset and enable, enable takes priority over reset
+				// posedge CLK, active low reset to 1 or 0, active high EN
+				params += " -cell $_SDFFCE_PN?P_ 01";
+
+				// D-latch + reset to 0/1
+				// posedge CLK, active low reset to 1 or 0
+				params += " -cell $_DLATCH_PN?_ 01";
+
+				run("dfflegalize" + params, "(Converts FFs to supported types)");
+			}
+				
+
+			if (abc9 || help_mode) {
+				if (dff || help_mode)
+					run("zinit -all w:* t:$_SDFFCE_*", "('-dff' only)");
+				run("techmap -D NO_LUT -map +/mchp/cells_map.v", "('-abc9' only)");
+			}
+		}
+
+		if (check_label("map_luts")) {
+			run("opt_expr -mux_undef -noclkinv");
+			if (flatten_before_abc)
+				run("flatten");
+			if (help_mode)
+				run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')");
+			else if (abc9) {
+                
+				std::string abc9_opts;
+				// for the if command in abc to specify wire delay between adjects LUTs (default = 0)
+				// NOTE: should not have 0 wire delay between LUTs, 
+				//		 otherwise abc might use LUT2+LUT3 instead of single LUT4
+				abc9_opts += " -W 300";
+				if (nowidelut)
+					abc9_opts += stringf(" -maxlut %d", lut_size);
+				if (dff)
+					abc9_opts += " -dff";
+				run("abc9" + abc9_opts);
+			}
+			else {
+				std::string abc_opts = " -lut " + lut_size_s;
+				if (dff)
+					abc_opts += " -dff";
+				if (retime)
+					abc_opts += " -D 1";
+				run("abc" + abc_opts);
+			}
+			run("clean");
+
+			if (help_mode || !abc9)
+				run("techmap -D NO_LUT -map +/mchp/cells_map.v", "(only if not '-abc9')");
+			std::string techmap_args = "-map +/mchp/cells_map.v -D FINAL_MAP";
+			techmap_args += " -D LUT_WIDTH=" + lut_size_s;
+			run("techmap " + techmap_args);
+            
+			if (help_mode || lut_size == 4)
+				run("mchp_dffopt");
+
+            
+		}
+
+			run("clkbufmap -buf CLKINT Y:A -inpad CLKBUF Y:PAD");
+
+			run("clean -purge");
+
+
+		if (check_label("check")) {
+			run("hierarchy -check");
+			run("stat");
+			run("check -noinit");
+			run("blackbox =A:whitebox");
+		}
+
+		if (check_label("edif")) {
+			if (!edif_file.empty() || help_mode)
+				run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
+		}
+
+		if (check_label("blif")) {
+			if (!blif_file.empty() || help_mode)
+				run(stringf("write_blif %s", blif_file.c_str()));
+		}
+	}
+} SynthMchpPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/mchp/tests/Registers/Registers.v b/techlibs/mchp/tests/Registers/Registers.v
new file mode 100644
index 00000000000..b5bd6f4afea
--- /dev/null
+++ b/techlibs/mchp/tests/Registers/Registers.v
@@ -0,0 +1,38 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module Registers(
+    input clk,
+    input en,
+    input rst,
+    input D,
+    output Q
+);
+parameter LOAD_DATA = 1;
+
+// active low async reset
+always @(posedge clk, negedge rst) begin
+    if (rst == 0) begin
+        Q <= LOAD_DATA;
+    end else if(en) begin
+        Q <= D;
+    end
+end
+
+
+endmodule
\ No newline at end of file
diff --git a/techlibs/mchp/tests/Registers/Registers.ys b/techlibs/mchp/tests/Registers/Registers.ys
new file mode 100644
index 00000000000..c83376fdd30
--- /dev/null
+++ b/techlibs/mchp/tests/Registers/Registers.ys
@@ -0,0 +1,23 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+# read verilog files
+read_verilog Registers.v
+
+synth_mchp -top Registers -abc9 -family pf -noiopad
+
+# write final outputfile
+write_verilog -noexpr Registers.vm
diff --git a/techlibs/mchp/tests/carryout/carryout.v b/techlibs/mchp/tests/carryout/carryout.v
new file mode 100644
index 00000000000..c109435b866
--- /dev/null
+++ b/techlibs/mchp/tests/carryout/carryout.v
@@ -0,0 +1,34 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module carryout (cout,out,a, b,c);
+parameter n = 6;
+parameter k = 2;
+output reg [k*(n+1)-1:0] out;
+output reg cout;
+input [n:0] a;
+input [n:0] b;
+input [n-1:0] c;
+
+    always @(a,b,c) 
+    begin
+        {cout,out} = a * b + c;
+        
+    end
+
+endmodule
diff --git a/techlibs/mchp/tests/carryout/carryout.ys b/techlibs/mchp/tests/carryout/carryout.ys
new file mode 100644
index 00000000000..1697bc8932c
--- /dev/null
+++ b/techlibs/mchp/tests/carryout/carryout.ys
@@ -0,0 +1,21 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+read_verilog carryout.v
+
+synth_mchp -top carryout -abc9 -family pf -noiopad
+
+write_verilog -noexpr carryout.vm
diff --git a/techlibs/mchp/tests/cascade/cascade.v b/techlibs/mchp/tests/cascade/cascade.v
new file mode 100644
index 00000000000..6be738846d2
--- /dev/null
+++ b/techlibs/mchp/tests/cascade/cascade.v
@@ -0,0 +1,38 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module cascade(
+    input signed [5:0] in_A,
+    input signed [4:0] in_B,
+    input signed [4:0] in_D,
+    output signed [11:0] out_P,
+
+    input signed [4:0] casA,
+    input signed [4:0] casB
+
+);
+
+wire signed [9:0] cascade;
+// first dsp
+assign cascade = casA * casB;
+
+// second dsp
+assign out_P = in_A * (in_B + in_D) + cascade;
+
+
+endmodule
diff --git a/techlibs/mchp/tests/cascade/cascade.ys b/techlibs/mchp/tests/cascade/cascade.ys
new file mode 100644
index 00000000000..f7017913d18
--- /dev/null
+++ b/techlibs/mchp/tests/cascade/cascade.ys
@@ -0,0 +1,21 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+read_verilog cascade.v
+
+synth_mchp -top cascade -abc9 -family pf -noiopad
+
+write_verilog -noexpr cascade.vm
diff --git a/techlibs/mchp/tests/dff_opt/dff_opt.v b/techlibs/mchp/tests/dff_opt/dff_opt.v
new file mode 100644
index 00000000000..b14bf4be5c1
--- /dev/null
+++ b/techlibs/mchp/tests/dff_opt/dff_opt.v
@@ -0,0 +1,42 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module dff_opt(
+    input clk,
+    input [1:0] D_comb,
+    input [1:0] EN_comb,
+    input [1:0] RST_comb,
+    output bar
+);
+
+// DFF with enable that can be merged into D
+
+reg foo;
+
+assign bar = foo;
+
+// sync reset
+always@(posedge clk) begin
+    if (&RST_comb) begin
+        foo <= 0;
+    end else begin
+        foo <= &D_comb;
+    end
+end
+
+endmodule
diff --git a/techlibs/mchp/tests/dff_opt/dff_opt.ys b/techlibs/mchp/tests/dff_opt/dff_opt.ys
new file mode 100644
index 00000000000..746444c3422
--- /dev/null
+++ b/techlibs/mchp/tests/dff_opt/dff_opt.ys
@@ -0,0 +1,21 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+read_verilog dff_opt.v 
+
+synth_mchp -top dff_opt -abc9 -family pf -noiopad
+
+# write final outputfile
+write_verilog -noexpr dff_opt.vm
diff --git a/techlibs/mchp/tests/full_dsp/full_dsp.v b/techlibs/mchp/tests/full_dsp/full_dsp.v
new file mode 100644
index 00000000000..a99a4ee1c89
--- /dev/null
+++ b/techlibs/mchp/tests/full_dsp/full_dsp.v
@@ -0,0 +1,30 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+module full_dsp(
+    input signed[5:0] in_A,
+    input signed [4:0] in_B,
+    input signed [11:0] in_C,
+    input signed [4:0] in_D,
+
+    output signed [12:0] out_Y
+);
+
+assign out_Y = ((in_D + in_B)*in_A)+in_C;
+
+
+endmodule
\ No newline at end of file
diff --git a/techlibs/mchp/tests/full_dsp/full_dsp.ys b/techlibs/mchp/tests/full_dsp/full_dsp.ys
new file mode 100644
index 00000000000..01bb95f54d9
--- /dev/null
+++ b/techlibs/mchp/tests/full_dsp/full_dsp.ys
@@ -0,0 +1,21 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+read_verilog full_dsp.v
+
+synth_mchp -top full_dsp -abc9 -family pf -noiopad
+
+write_verilog -noexpr full_dsp.vm
diff --git a/techlibs/mchp/tests/large_mult/large_mult.v b/techlibs/mchp/tests/large_mult/large_mult.v
new file mode 100644
index 00000000000..9f7ad6f92ec
--- /dev/null
+++ b/techlibs/mchp/tests/large_mult/large_mult.v
@@ -0,0 +1,25 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module large_mult(
+    input signed [20:0] in1,
+    input signed [17:0] in2,
+    output signed [38:0] out1
+);
+assign out1 = in1 * in2;
+endmodule
\ No newline at end of file
diff --git a/techlibs/mchp/tests/large_mult/large_mult.ys b/techlibs/mchp/tests/large_mult/large_mult.ys
new file mode 100644
index 00000000000..3779a26d6d4
--- /dev/null
+++ b/techlibs/mchp/tests/large_mult/large_mult.ys
@@ -0,0 +1,21 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+read_verilog large_mult.v
+
+synth_mchp -top large_mult -abc9 -family pf -noiopad
+
+write_verilog -noexpr large_mult.vm
diff --git a/techlibs/mchp/tests/mac/mac.v b/techlibs/mchp/tests/mac/mac.v
new file mode 100644
index 00000000000..e32b21867ad
--- /dev/null
+++ b/techlibs/mchp/tests/mac/mac.v
@@ -0,0 +1,43 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module mac(
+    input clk,
+    input signed [4:0] in_A,
+    input signed [4:0] in_B,
+    input signed [4:0] in_D,
+    output reg signed [11:0] out_P,
+
+    input srst_P,
+
+    input signed [4:0] casA,
+    input signed [4:0] casB
+
+);
+
+
+// sync reset P
+always@(posedge clk) begin
+    if (~srst_P) begin
+        out_P <= 12'h000;
+    end else begin
+        out_P <= in_A * (in_B + in_D) + out_P;
+    end
+end
+
+endmodule
\ No newline at end of file
diff --git a/techlibs/mchp/tests/mac/mac.ys b/techlibs/mchp/tests/mac/mac.ys
new file mode 100644
index 00000000000..59504436803
--- /dev/null
+++ b/techlibs/mchp/tests/mac/mac.ys
@@ -0,0 +1,24 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+# read verilog files
+read_verilog mac.v
+
+# run the synth flow, specifies top module and additional parameters
+synth_mchp -top mac -abc9 -family pf -noiopad
+
+# write final outputfile
+write_verilog -noexpr mac.vm
diff --git a/techlibs/mchp/tests/postAdd_mult/postAdd_mult.v b/techlibs/mchp/tests/postAdd_mult/postAdd_mult.v
new file mode 100644
index 00000000000..90a758dbc8d
--- /dev/null
+++ b/techlibs/mchp/tests/postAdd_mult/postAdd_mult.v
@@ -0,0 +1,30 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module postAdd_mult(
+    input signed[17:0] in_A,
+    input signed [17:0] in_B,
+    input signed [17:0] in_C,
+
+    output signed [35:0] out_Y
+);
+
+assign out_Y = (in_B*in_A)+in_C;
+
+
+endmodule
\ No newline at end of file
diff --git a/techlibs/mchp/tests/postAdd_mult/postAdd_mult.ys b/techlibs/mchp/tests/postAdd_mult/postAdd_mult.ys
new file mode 100644
index 00000000000..3a3586c8859
--- /dev/null
+++ b/techlibs/mchp/tests/postAdd_mult/postAdd_mult.ys
@@ -0,0 +1,21 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+read_verilog postAdd_mult.v
+
+synth_mchp -top postAdd_mult -abc9 -family pf -noiopad
+
+write_verilog -noexpr postAdd_mult.vm
diff --git a/techlibs/mchp/tests/post_adder/post_adder.v b/techlibs/mchp/tests/post_adder/post_adder.v
new file mode 100644
index 00000000000..13d95414164
--- /dev/null
+++ b/techlibs/mchp/tests/post_adder/post_adder.v
@@ -0,0 +1,32 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module post_adder(
+    input signed [5:0] in_A,
+    input signed [4:0] in_B,
+    input signed [4:0] in_D,
+    input signed [11:0] in_C,
+    
+    output [12:0] out_Y
+);
+
+assign out_Y = (in_D + in_B) * in_A + in_C;
+
+
+
+endmodule
\ No newline at end of file
diff --git a/techlibs/mchp/tests/post_adder/post_adder.ys b/techlibs/mchp/tests/post_adder/post_adder.ys
new file mode 100644
index 00000000000..0fa613f6728
--- /dev/null
+++ b/techlibs/mchp/tests/post_adder/post_adder.ys
@@ -0,0 +1,21 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+read_verilog post_adder.v
+
+synth_mchp -top post_adder -abc9 -family pf
+
+write_verilog -noexpr post_adder.vm
diff --git a/techlibs/mchp/tests/pre_adder_dsp/pre_adder_dsp.v b/techlibs/mchp/tests/pre_adder_dsp/pre_adder_dsp.v
new file mode 100644
index 00000000000..2343dd1a482
--- /dev/null
+++ b/techlibs/mchp/tests/pre_adder_dsp/pre_adder_dsp.v
@@ -0,0 +1,30 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module pre_adder_dsp(
+    input signed [5:0] in_A,
+    input signed [4:0] in_B,
+    input signed [4:0] in_D,
+    
+    output [11:0] out_Y
+);
+
+assign out_Y = in_A * (in_B + in_D);
+
+
+endmodule
\ No newline at end of file
diff --git a/techlibs/mchp/tests/pre_adder_dsp/pre_adder_dsp.ys b/techlibs/mchp/tests/pre_adder_dsp/pre_adder_dsp.ys
new file mode 100644
index 00000000000..82bc56bd17c
--- /dev/null
+++ b/techlibs/mchp/tests/pre_adder_dsp/pre_adder_dsp.ys
@@ -0,0 +1,21 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+read_verilog pre_adder_dsp.v
+
+synth_mchp -top pre_adder_dsp -abc9 -family pf -noiopad
+
+write_verilog -noexpr pre_adder_dsp.vm
diff --git a/techlibs/mchp/tests/ram_SDP/ram_SDP.v b/techlibs/mchp/tests/ram_SDP/ram_SDP.v
new file mode 100644
index 00000000000..30c724256c7
--- /dev/null
+++ b/techlibs/mchp/tests/ram_SDP/ram_SDP.v
@@ -0,0 +1,39 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module ram_SDP(data,waddr,we,clk,q);
+parameter d_width = 32;
+parameter addr_width = 8;
+parameter mem_depth = 256;
+input [d_width-1:0] data;
+input [addr_width-1:0] waddr;
+input we, clk;
+output reg [d_width-1:0] q;
+
+reg [d_width-1:0] mem [mem_depth-1:0];
+
+always @(posedge clk) begin
+    if (we) begin 
+        mem[waddr] <= data;
+    end else begin
+        q <= mem[waddr];
+    end
+end
+
+endmodule
+
diff --git a/techlibs/mchp/tests/ram_SDP/ram_SDP.ys b/techlibs/mchp/tests/ram_SDP/ram_SDP.ys
new file mode 100644
index 00000000000..4ab12999021
--- /dev/null
+++ b/techlibs/mchp/tests/ram_SDP/ram_SDP.ys
@@ -0,0 +1,21 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+read_verilog ram_SDP.v
+
+synth_mchp -top ram_SDP -abc9 -family pf -noiopad
+
+write_verilog -noexpr ram_SDP.vm
diff --git a/techlibs/mchp/tests/ram_TDP/ram_TDP.v b/techlibs/mchp/tests/ram_TDP/ram_TDP.v
new file mode 100644
index 00000000000..d223574503a
--- /dev/null
+++ b/techlibs/mchp/tests/ram_TDP/ram_TDP.v
@@ -0,0 +1,56 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module ram_TDP (clka,clkb,wea,addra,dataina,qa,web,addrb,datainb,qb);
+parameter addr_width = 10;
+parameter data_width = 2;
+input clka,clkb,wea,web;
+input [data_width - 1 : 0] dataina,datainb;
+input [addr_width - 1 : 0] addra,addrb;
+output reg [data_width - 1 : 0] qa,qb;
+reg [addr_width - 1 : 0] addra_reg, addrb_reg;
+reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];
+
+always @ (posedge clka)
+    begin
+        addra_reg <= addra;
+        if(wea)
+            mem[addra] <= dataina;
+    end
+
+always @ (posedge clkb)
+begin
+addrb_reg <= addrb;
+if(web)
+mem[addrb] <= datainb;
+end
+
+always @ (posedge clka)
+begin
+if(~wea)
+qa <= mem[addra];
+else qa <= dataina;
+end
+
+always @ (posedge clkb)
+begin
+if(~web)
+qb <= mem[addrb];
+else qb <= datainb;
+end
+endmodule
diff --git a/techlibs/mchp/tests/ram_TDP/ram_TDP.ys b/techlibs/mchp/tests/ram_TDP/ram_TDP.ys
new file mode 100644
index 00000000000..ea98facd59c
--- /dev/null
+++ b/techlibs/mchp/tests/ram_TDP/ram_TDP.ys
@@ -0,0 +1,21 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+read_verilog ram_TDP.v
+
+synth_mchp -top ram_TDP -abc9 -family pf -noiopad -debug_memory
+
+write_verilog -noexpr ram_TDP.vm
diff --git a/techlibs/mchp/tests/reduce/reduce.v b/techlibs/mchp/tests/reduce/reduce.v
new file mode 100644
index 00000000000..603d0317377
--- /dev/null
+++ b/techlibs/mchp/tests/reduce/reduce.v
@@ -0,0 +1,29 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module reduce(
+        input [7:0] data,
+        output Y
+
+    );
+
+
+assign Y = ^data;
+
+endmodule
+
diff --git a/techlibs/mchp/tests/reduce/reduce.ys b/techlibs/mchp/tests/reduce/reduce.ys
new file mode 100644
index 00000000000..693f1cdeb6e
--- /dev/null
+++ b/techlibs/mchp/tests/reduce/reduce.ys
@@ -0,0 +1,21 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+read_verilog reduce.v
+
+synth_mchp -top reduce -abc9 -family pf -noiopad
+
+write_verilog -noexpr reduce.vm
diff --git a/techlibs/mchp/tests/reg_c/reg_c.v b/techlibs/mchp/tests/reg_c/reg_c.v
new file mode 100644
index 00000000000..1d9ee0f3265
--- /dev/null
+++ b/techlibs/mchp/tests/reg_c/reg_c.v
@@ -0,0 +1,122 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module reg_c(
+    input clk,
+
+    // active high
+    input en_A,
+    input en_B,
+    input en_D,
+    input en_P,
+
+    // active low
+    input srst_A,
+    input srst_B,
+    input srst_D,
+    input srst_P,
+
+    // active low
+    input arst_D,
+
+    input srst_C,
+    input arst_C,
+
+
+    input signed [5:0] in_A,
+    input signed [4:0] in_B,
+    input signed [4:0] in_C,
+    input signed [4:0] in_D,
+    
+    
+    output reg [11:0] out_P
+
+);
+
+
+// MACC_PA takes active low resets
+wire srst_A_N;
+wire srst_B_N;
+wire srst_C_N;
+wire srst_D_N;
+wire srst_P_N;
+assign srst_A_N = ~srst_A;
+assign srst_B_N = ~srst_B;
+assign srst_C_N = ~srst_C;
+assign srst_D_N = ~srst_D;
+assign srst_P_N = ~srst_P;
+
+// input reg
+reg signed [5:0] reg_A;
+reg signed [4:0] reg_B;
+reg signed [4:0] reg_C;
+reg signed [4:0] reg_D;
+
+// sync reset A
+always@(posedge clk) begin
+    // if (~srst_A_N) begin
+    if (srst_A_N) begin
+        reg_A = 6'b000000;
+    end else begin
+        reg_A = in_A;
+    end
+end
+
+
+
+// sync reset B
+always@(posedge clk) begin
+    if (srst_B_N) begin
+        reg_B = 5'b00000;
+    end else begin
+        reg_B = in_B;
+    end
+end
+
+
+
+// async reset D
+always@(posedge clk, negedge arst_D) begin
+    if (~arst_D) begin
+        reg_D = 5'b00000;
+    end else begin
+        reg_D = in_D;
+    end
+end
+
+// sync reset C
+always@(posedge clk) begin
+    if (srst_C_N) begin
+        reg_C = 5'b00000;
+    end else begin
+        reg_C = in_C;
+    end
+end
+
+
+
+// sync reset P
+always@(posedge clk) begin
+    if (srst_P_N) begin
+        out_P = 12'h000;
+    end else begin
+        out_P = reg_A * (reg_B + reg_D) + reg_C;
+    end
+end
+
+endmodule
\ No newline at end of file
diff --git a/techlibs/mchp/tests/reg_c/reg_c.ys b/techlibs/mchp/tests/reg_c/reg_c.ys
new file mode 100644
index 00000000000..37c4df18dde
--- /dev/null
+++ b/techlibs/mchp/tests/reg_c/reg_c.ys
@@ -0,0 +1,21 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+read_verilog reg_c.v
+
+synth_mchp -top reg_c -abc9 -family pf -noiopad
+
+write_verilog -noexpr reg_c.vm
diff --git a/techlibs/mchp/tests/reg_test/reg_test.v b/techlibs/mchp/tests/reg_test/reg_test.v
new file mode 100644
index 00000000000..dadec7ae86b
--- /dev/null
+++ b/techlibs/mchp/tests/reg_test/reg_test.v
@@ -0,0 +1,97 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module reg_test(
+    input clk,
+
+    // active high
+    input en_A,
+    input en_B,
+    input en_D,
+    input en_P,
+
+    // active low
+    input srst_A,
+    input srst_B,
+    input srst_D,
+    input srst_P,
+
+    // active low
+    input arst_D,
+
+    input signed [5:0] in_A,
+    input signed [4:0] in_B,
+    input signed [4:0] in_D,
+    
+    output reg [11:0] out_P
+
+);
+
+
+// MACC_PA takes active low resets
+wire srst_A_N;
+wire srst_B_N;
+wire srst_D_N;
+wire srst_P_N;
+assign srst_A_N = ~srst_A;
+assign srst_B_N = ~srst_B;
+assign srst_D_N = ~srst_D;
+assign srst_P_N = ~srst_P;
+
+// input reg
+reg signed [5:0] reg_A;
+reg signed [4:0] reg_B;
+reg signed [4:0] reg_D;
+
+// sync reset A
+always@(posedge clk) begin
+    if (srst_A_N) begin
+        reg_A = 6'b000000;
+    end else begin
+        reg_A = in_A;
+    end
+end
+
+// sync reset B
+always@(posedge clk) begin
+    if (srst_B_N) begin
+        reg_B = 5'b00000;
+    end else begin
+        reg_B = in_B;
+    end
+end
+
+// async reset D
+always@(posedge clk, negedge arst_D) begin
+    if (~arst_D) begin
+        reg_D = 5'b00000;
+    end else begin
+        reg_D = in_D;
+    end
+end
+
+// sync reset P
+always@(posedge clk) begin
+    if (srst_P_N) begin
+        out_P = 12'h000;
+    end else begin
+        out_P = reg_A * (reg_B + reg_D);
+    end
+end
+
+endmodule
\ No newline at end of file
diff --git a/techlibs/mchp/tests/reg_test/reg_test.ys b/techlibs/mchp/tests/reg_test/reg_test.ys
new file mode 100644
index 00000000000..2c1fb87d72c
--- /dev/null
+++ b/techlibs/mchp/tests/reg_test/reg_test.ys
@@ -0,0 +1,21 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+read_verilog reg_test.v
+
+synth_mchp -top reg_test -abc9 -family pf -noiopad
+
+write_verilog -noexpr reg_test.vm
diff --git a/techlibs/mchp/tests/signed_mult/signed_mult.v b/techlibs/mchp/tests/signed_mult/signed_mult.v
new file mode 100755
index 00000000000..09d324af1dc
--- /dev/null
+++ b/techlibs/mchp/tests/signed_mult/signed_mult.v
@@ -0,0 +1,28 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module signed_mult(
+    input signed [17:0] in_A,
+    input signed [17:0] in_B,
+    
+    output signed [35:0] out_Y
+);
+
+assign out_Y = in_A * in_B;
+
+endmodule
\ No newline at end of file
diff --git a/techlibs/mchp/tests/signed_mult/signed_mult.ys b/techlibs/mchp/tests/signed_mult/signed_mult.ys
new file mode 100755
index 00000000000..bba8cbfe20c
--- /dev/null
+++ b/techlibs/mchp/tests/signed_mult/signed_mult.ys
@@ -0,0 +1,21 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+read_verilog signed_mult.v
+
+synth_mchp -top signed_mult -abc9 -family pf -noiopad
+
+write_verilog -noexpr signed_mult.vm
diff --git a/techlibs/mchp/tests/simple_ram/simple_ram.v b/techlibs/mchp/tests/simple_ram/simple_ram.v
new file mode 100644
index 00000000000..5117b1b3557
--- /dev/null
+++ b/techlibs/mchp/tests/simple_ram/simple_ram.v
@@ -0,0 +1,37 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module simple_ram (clk,wr,addr,din,dout);
+input clk;
+input [19:0] din;
+input wr;
+input [9:0] addr;
+output [19:0] dout;
+
+
+reg [9:0] addr_reg;
+reg [19:0] mem [0:1023] ;
+assign dout = mem[addr_reg];
+
+always@(posedge clk) begin
+    addr_reg <= addr;
+    if(wr)
+        mem[addr]<= din;
+end
+endmodule
+
diff --git a/techlibs/mchp/tests/simple_ram/simple_ram.ys b/techlibs/mchp/tests/simple_ram/simple_ram.ys
new file mode 100644
index 00000000000..a315a2bfb80
--- /dev/null
+++ b/techlibs/mchp/tests/simple_ram/simple_ram.ys
@@ -0,0 +1,21 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+read_verilog simple_ram.v
+
+synth_mchp -top simple_ram -abc9 -family pf -noiopad
+
+write_verilog -noexpr simple_ram.vm
diff --git a/techlibs/mchp/tests/unsigned_mult/unsigned_mult.v b/techlibs/mchp/tests/unsigned_mult/unsigned_mult.v
new file mode 100644
index 00000000000..987c77a37b2
--- /dev/null
+++ b/techlibs/mchp/tests/unsigned_mult/unsigned_mult.v
@@ -0,0 +1,28 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module unsigned_mult(
+    input [10:0] in_A,
+    input signed [10:0] in_B,
+    
+    output [21:0] out_Y
+);
+
+assign out_Y = in_A * in_B;
+
+endmodule
\ No newline at end of file
diff --git a/techlibs/mchp/tests/unsigned_mult/unsigned_mult.ys b/techlibs/mchp/tests/unsigned_mult/unsigned_mult.ys
new file mode 100644
index 00000000000..05118e2658e
--- /dev/null
+++ b/techlibs/mchp/tests/unsigned_mult/unsigned_mult.ys
@@ -0,0 +1,21 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+read_verilog unsigned_mult.v
+
+synth_mchp -top unsigned_mult -abc9 -family pf -noiopad
+
+write_verilog -noexpr unsigned_mult.vm
diff --git a/techlibs/mchp/tests/uram_ar/uram_ar.v b/techlibs/mchp/tests/uram_ar/uram_ar.v
new file mode 100644
index 00000000000..524203c9b3c
--- /dev/null
+++ b/techlibs/mchp/tests/uram_ar/uram_ar.v
@@ -0,0 +1,38 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module uram_ar(data,waddr,we,clk,q);
+parameter d_width = 27;
+parameter addr_width = 2;
+parameter mem_depth = 4;
+input [d_width-1:0] data;
+input [addr_width-1:0] waddr;
+input we, clk;
+output [d_width-1:0] q;
+
+reg [d_width-1:0] mem [mem_depth-1:0];
+
+assign q = mem[waddr];
+
+always @(posedge clk) begin
+    if (we) 
+        mem[waddr] <= data;
+
+end
+
+endmodule
diff --git a/techlibs/mchp/tests/uram_ar/uram_ar.ys b/techlibs/mchp/tests/uram_ar/uram_ar.ys
new file mode 100644
index 00000000000..3650cb249c7
--- /dev/null
+++ b/techlibs/mchp/tests/uram_ar/uram_ar.ys
@@ -0,0 +1,21 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+read_verilog uram_ar.v
+
+synth_mchp -top uram_ar -abc9 -family pf -noiopad
+
+write_verilog -noexpr uram_ar.vm
diff --git a/techlibs/mchp/tests/uram_sr/uram_sr.v b/techlibs/mchp/tests/uram_sr/uram_sr.v
new file mode 100644
index 00000000000..2bb5888038d
--- /dev/null
+++ b/techlibs/mchp/tests/uram_sr/uram_sr.v
@@ -0,0 +1,32 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module uram_sr(clk, wr, raddr, din, waddr, dout);
+input clk;
+input [11:0] din;
+input wr;
+input [5:0] waddr, raddr;
+output [11:0] dout;
+reg [5:0] raddr_reg;
+reg [11:0] mem [0:63];
+assign dout = mem[raddr_reg];
+always@(posedge clk) begin
+    raddr_reg <= raddr; if(wr)
+    mem[waddr]<= din;
+end
+endmodule
\ No newline at end of file
diff --git a/techlibs/mchp/tests/uram_sr/uram_sr.ys b/techlibs/mchp/tests/uram_sr/uram_sr.ys
new file mode 100644
index 00000000000..a4c79398a41
--- /dev/null
+++ b/techlibs/mchp/tests/uram_sr/uram_sr.ys
@@ -0,0 +1,21 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+read_verilog uram_sr.v
+
+synth_mchp -top uram_sr -abc9 -family pf -noiopad
+
+write_verilog -noexpr uram_sr.vm
diff --git a/techlibs/mchp/tests/widemux/widemux.v b/techlibs/mchp/tests/widemux/widemux.v
new file mode 100644
index 00000000000..1fe28ba2886
--- /dev/null
+++ b/techlibs/mchp/tests/widemux/widemux.v
@@ -0,0 +1,48 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+module widemux(
+        input [3:0] data,
+        input S0,
+        input S1,
+        output Y
+
+    );
+
+    wire A, B;
+
+    always @ (*) begin 
+         if (S0)begin
+            A = data[1];
+            B = data[3];
+         end else begin 
+            A = data[0];
+            B = data[2];
+        end
+
+        if (S1)begin
+            Y = A;
+        end else begin
+            Y = B;
+        end
+
+    end
+endmodule
+
+
+
diff --git a/techlibs/mchp/tests/widemux/widemux.ys b/techlibs/mchp/tests/widemux/widemux.ys
new file mode 100644
index 00000000000..f8aeaaa5805
--- /dev/null
+++ b/techlibs/mchp/tests/widemux/widemux.ys
@@ -0,0 +1,21 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+read_verilog widemux.v
+
+synth_mchp -top widemux -abc9 -family pf -noiopad
+
+write_verilog -noexpr widemux.vm
diff --git a/techlibs/mchp/uSRAM.txt b/techlibs/mchp/uSRAM.txt
new file mode 100644
index 00000000000..296fc8dd2e5
--- /dev/null
+++ b/techlibs/mchp/uSRAM.txt
@@ -0,0 +1,69 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+# asynchronous read
+ram block $__uSRAM_AR_ {
+
+	#(LSRAM cost)/3
+	cost 43;
+
+	# INIT supported
+	init any;
+
+    abits 6;
+    widths 12 per_port;
+
+    # single write enable wire
+	port sw "W" {
+		clock posedge;
+
+        # collision not supported, but write takes precedence and read data is invalid while writing to 
+        #       the same address
+		wrtrans all new;
+		
+		optional;
+	}
+	port ar "R" {
+        optional;
+	}
+}
+
+# synchronous read
+# NOTE: synchronous read can be realized by the address pipeline register or data pipeline register.
+#       This assumes address is synchronized
+ram block $__uSRAM_SR_ {
+
+	cost 42;
+
+    init any;
+    abits 6;
+    widths 12 per_port;
+
+	port sw "W" {
+		clock posedge;
+
+        # collision not supported
+		wrtrans all new;
+		
+		optional;
+	}
+	port sr "R" {
+		clock posedge;
+		rden;
+		rdinit none;
+		optional;
+	}
+}
diff --git a/techlibs/mchp/uSRAM_map.v b/techlibs/mchp/uSRAM_map.v
new file mode 100644
index 00000000000..9fce7193cad
--- /dev/null
+++ b/techlibs/mchp/uSRAM_map.v
@@ -0,0 +1,118 @@
+/*
+ISC License
+
+Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// See document PolarFire Family Fabric User Guide
+//   section 4.2 for port list.
+
+// Asynchronous read
+module $__uSRAM_AR_ (...);
+
+parameter INIT = 0;
+parameter ADDR_BITS = 6;
+
+parameter PORT_W_WIDTH = 12;
+parameter PORT_R_WIDTH = 12;
+parameter PORT_R_USED = 0;
+parameter PORT_W_USED = 0;
+
+input PORT_W_CLK;
+input [ADDR_BITS-1:0] PORT_W_ADDR;
+input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
+input PORT_W_WR_EN;
+
+input [ADDR_BITS-1:0] PORT_R_ADDR;
+output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
+
+RAM64x12 _TECHMAP_REPLACE_ (
+	.R_ADDR(PORT_R_ADDR),
+	.R_ADDR_BYPASS(1'b1),
+	.R_ADDR_EN(1'b0),
+	.R_ADDR_SL_N(1'b1),
+	.R_ADDR_SD(1'b0),
+	.R_ADDR_AL_N(1'b1), 
+	.R_ADDR_AD_N(1'b0),
+	.BLK_EN(PORT_R_USED ? 1'b1 : 1'b0),
+	.R_DATA(PORT_R_RD_DATA),
+	.R_DATA_BYPASS(1'b1),
+	.R_DATA_EN(1'b0),
+	.R_DATA_SL_N(1'b1),
+	.R_DATA_SD(1'b0),
+	.R_DATA_AL_N(1'b1),
+	.R_DATA_AD_N(1'b0),
+
+	.W_CLK(PORT_W_CLK),
+	.W_ADDR(PORT_W_ADDR),
+	.W_DATA(PORT_W_WR_DATA),
+	.W_EN(PORT_W_WR_EN),
+
+	.BUSY_FB(1'b0)
+);
+
+endmodule
+
+// Synchronous read
+module $__uSRAM_SR_ (...);
+
+parameter INIT = 0;
+parameter ADDR_BITS = 6;
+
+parameter PORT_W_WIDTH = 12;
+parameter PORT_R_WIDTH = 12;
+parameter PORT_R_USED = 0;
+parameter PORT_W_USED = 0;
+
+input PORT_W_CLK;
+input [ADDR_BITS-1:0] PORT_W_ADDR;
+input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
+input PORT_W_WR_EN;
+
+// Read port clock and enable signal
+//   that async read uSRAM doesn't have
+input PORT_R_CLK;
+input PORT_R_RD_EN;
+input [ADDR_BITS-1:0] PORT_R_ADDR;
+output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
+
+RAM64x12 _TECHMAP_REPLACE_ (
+    .R_CLK(PORT_R_CLK),
+    .R_ADDR(PORT_R_ADDR),
+    .R_ADDR_BYPASS(1'b0),
+    .R_ADDR_EN(PORT_R_RD_EN),
+    .R_ADDR_SL_N(1'b1),
+    .R_ADDR_SD(1'b0),
+    .R_ADDR_AL_N(1'b1), 
+    .R_ADDR_AD_N(1'b0),
+    .BLK_EN(PORT_R_USED ? 1'b1 : 1'b0),
+    .R_DATA(PORT_R_RD_DATA),
+    .R_DATA_BYPASS(1'b1),
+    .R_DATA_EN(1'b0),
+    .R_DATA_SL_N(1'b1),
+    .R_DATA_SD(1'b0),
+    .R_DATA_AL_N(1'b1),
+    .R_DATA_AD_N(1'b0),
+
+    .W_CLK(PORT_W_CLK),
+    .W_ADDR(PORT_W_ADDR),
+    .W_DATA(PORT_W_WR_DATA),
+    .W_EN(PORT_W_WR_EN),
+
+    .BUSY_FB(1'b0)
+);
+
+endmodule
+

From 2ced2752e98cc11391d0b638c6c756787f0e1b98 Mon Sep 17 00:00:00 2001
From: Chun Lin Min <chunlin.min@microchip.com>
Date: Tue, 2 Jul 2024 13:47:18 -0700
Subject: [PATCH 179/499] replace space indent with tab indent

---
 passes/pmgen/mchp_dsp_CREG.pmg                |  38 +-
 passes/pmgen/mchp_dsp_cascade.pmg             | 150 +++----
 techlibs/mchp/LSRAM.txt                       |  30 +-
 techlibs/mchp/LSRAM_map.v                     | 323 +++++++------
 techlibs/mchp/cells_map.v                     |  66 +--
 techlibs/mchp/cells_sim.v                     | 425 +++++++++---------
 techlibs/mchp/mchp_dffopt.cc                  |   6 +-
 techlibs/mchp/pf_dsp_map.v                    | 108 ++---
 techlibs/mchp/tests/Registers/Registers.v     |  20 +-
 techlibs/mchp/tests/carryout/carryout.v       |  10 +-
 techlibs/mchp/tests/cascade/cascade.v         |  12 +-
 techlibs/mchp/tests/dff_opt/dff_opt.v         |  20 +-
 techlibs/mchp/tests/full_dsp/full_dsp.v       |  10 +-
 techlibs/mchp/tests/large_mult/large_mult.v   |   6 +-
 techlibs/mchp/tests/mac/mac.v                 |  26 +-
 .../mchp/tests/postAdd_mult/postAdd_mult.v    |   8 +-
 techlibs/mchp/tests/post_adder/post_adder.v   |  12 +-
 .../mchp/tests/pre_adder_dsp/pre_adder_dsp.v  |  10 +-
 techlibs/mchp/tests/ram_SDP/ram_SDP.v         |  10 +-
 techlibs/mchp/tests/ram_TDP/ram_TDP.v         |  10 +-
 techlibs/mchp/tests/reduce/reduce.v           |   6 +-
 techlibs/mchp/tests/reg_c/reg_c.v             |  96 ++--
 techlibs/mchp/tests/reg_test/reg_test.v       |  76 ++--
 techlibs/mchp/tests/signed_mult/signed_mult.v |   8 +-
 techlibs/mchp/tests/simple_ram/simple_ram.v   |   6 +-
 .../mchp/tests/unsigned_mult/unsigned_mult.v  |   8 +-
 techlibs/mchp/tests/uram_ar/uram_ar.v         |   4 +-
 techlibs/mchp/tests/uram_sr/uram_sr.v         |   4 +-
 techlibs/mchp/tests/widemux/widemux.v         |  50 +--
 techlibs/mchp/uSRAM.txt                       |  20 +-
 techlibs/mchp/uSRAM_map.v                     |  50 +--
 31 files changed, 811 insertions(+), 817 deletions(-)

diff --git a/passes/pmgen/mchp_dsp_CREG.pmg b/passes/pmgen/mchp_dsp_CREG.pmg
index 8647f16a16b..043a40617f8 100644
--- a/passes/pmgen/mchp_dsp_CREG.pmg
+++ b/passes/pmgen/mchp_dsp_CREG.pmg
@@ -56,7 +56,7 @@ udata <Cell*> dff
 //     and (b) uses the 'C' port
 match dsp
 	select dsp->type.in(\MACC_PA)
-    select port(dsp, \C_BYPASS, SigSpec()).is_fully_ones()
+	select port(dsp, \C_BYPASS, SigSpec()).is_fully_ones()
 	select nusers(port(dsp, \C, SigSpec())) > 1
 endmatch
 
@@ -76,14 +76,14 @@ code sigC sigP clock
 
 	SigSpec P = port(dsp, \P);
 
-    // Only care about those bits that are used
-    int i;
-    for (i = GetSize(P)-1; i >= 0; i--)
-        if (nusers(P[i]) > 1)
-            break;
-    i++;
-    log_assert(nusers(P.extract_end(i)) <= 1);
-    sigP = P.extract(0, i);
+	// Only care about those bits that are used
+	int i;
+	for (i = GetSize(P)-1; i >= 0; i--)
+		if (nusers(P[i]) > 1)
+			break;
+	i++;
+	log_assert(nusers(P.extract_end(i)) <= 1);
+	sigP = P.extract(0, i);
 
 	clock = port(dsp, \CLK, SigBit());
 endcode
@@ -150,20 +150,20 @@ match ff
 endmatch
 
 code argQ
-    // Check that reset value, if present, is fully 0.
+	// Check that reset value, if present, is fully 0.
 	bool noResetFlop = ff->type.in($dff, $dffe);
 	bool srstZero = ff->type.in($sdff, $sdffe) && param(ff, \SRST_VALUE).is_fully_zero();
 	bool arstZero = ff->type.in($adff, $adffe) && param(ff, \ARST_VALUE).is_fully_zero();
 	bool resetLegal = noResetFlop || srstZero || arstZero;
 	if (resetLegal)
-    {
-        SigSpec Q = port(ff, \Q);
-        dff = ff;
-        dffclock = port(ff, \CLK);
-        dffD = argQ;
-        SigSpec D = port(ff, \D);
-        argQ = Q;
-        dffD.replace(argQ, D);
-    }
+	{
+		SigSpec Q = port(ff, \Q);
+		dff = ff;
+		dffclock = port(ff, \CLK);
+		dffD = argQ;
+		SigSpec D = port(ff, \D);
+		argQ = Q;
+		dffD.replace(argQ, D);
+	}
 	
 endcode
diff --git a/passes/pmgen/mchp_dsp_cascade.pmg b/passes/pmgen/mchp_dsp_cascade.pmg
index 172dfb807e7..4ea9df75802 100644
--- a/passes/pmgen/mchp_dsp_cascade.pmg
+++ b/passes/pmgen/mchp_dsp_cascade.pmg
@@ -60,16 +60,16 @@ endcode
 
 // Helper function to remove unused bits
 code
-    unextend = [](const SigSpec &sig) {
-        int i;
-        for (i = GetSize(sig)-1; i > 0; i--)
-            if (sig[i] != sig[i-1])
-                break;
-        // Do not remove non-const sign bit
-        if (sig[i].wire)
-            ++i;
-        return sig.extract(0, i);
-    };
+	unextend = [](const SigSpec &sig) {
+		int i;
+		for (i = GetSize(sig)-1; i > 0; i--)
+			if (sig[i] != sig[i-1])
+				break;
+		// Do not remove non-const sign bit
+		if (sig[i].wire)
+			++i;
+		return sig.extract(0, i);
+	};
 endcode
 
 // (1) Starting from a DSP cell that 
@@ -85,57 +85,57 @@ endmatch
 //     height of a DSP column) with each DSP in each chunk being rewritten
 //     to use [ABP]COUT -> [ABP]CIN cascading as appropriate
 code
-    visited.clear();
-    visited.insert(first);
+	visited.clear();
+	visited.insert(first);
 
 	longest_chain.clear();
 	chain.emplace_back(first, -1);
 	subpattern(tail);
 finally
 
-    // longest cascade chain has been found with DSP "first" being the head of the chain
-    // do some post processing
+	// longest cascade chain has been found with DSP "first" being the head of the chain
+	// do some post processing
 
 	chain.pop_back();
-    visited.clear();
+	visited.clear();
 	log_assert(chain.empty());
 
 	if (GetSize(longest_chain) > 1) {
 		Cell *dsp = std::get<0>(longest_chain.front());
 
 		Cell *dsp_pcin;
-        int SHIFT = -1;
+		int SHIFT = -1;
 		for (int i = 1; i < GetSize(longest_chain); i++) {
-            log_assert(dsp->type.in(\MACC_PA));
+			log_assert(dsp->type.in(\MACC_PA));
 
-            std::tie(dsp_pcin,SHIFT) = longest_chain[i];
+			std::tie(dsp_pcin,SHIFT) = longest_chain[i];
 
-            // Chain length exceeds the maximum cascade length, must split it up
+			// Chain length exceeds the maximum cascade length, must split it up
 			if (i % MAX_DSP_CASCADE > 0) {
-                Wire *cascade = module->addWire(NEW_ID, 48);
+				Wire *cascade = module->addWire(NEW_ID, 48);
 
-                // zero port C and move wire to cascade
-                dsp_pcin->setPort(ID(C), Const(0, 48));
-                dsp_pcin->setPort(ID(CDIN), cascade);
-                dsp->setPort(ID(CDOUT), cascade);
+				// zero port C and move wire to cascade
+				dsp_pcin->setPort(ID(C), Const(0, 48));
+				dsp_pcin->setPort(ID(CDIN), cascade);
+				dsp->setPort(ID(CDOUT), cascade);
 
-                // Configure wire to cascade the dsps
-                add_siguser(cascade, dsp_pcin);
-                add_siguser(cascade, dsp);
+				// Configure wire to cascade the dsps
+				add_siguser(cascade, dsp_pcin);
+				add_siguser(cascade, dsp);
 
-                // configure mux to use cascade for signal E
-                SigSpec cdin_fdbk_sel = port(dsp_pcin, \CDIN_FDBK_SEL, Const(0, 2));
-                cdin_fdbk_sel[1] = State::S1;
-                dsp_pcin->setPort(\CDIN_FDBK_SEL, cdin_fdbk_sel);
+				// configure mux to use cascade for signal E
+				SigSpec cdin_fdbk_sel = port(dsp_pcin, \CDIN_FDBK_SEL, Const(0, 2));
+				cdin_fdbk_sel[1] = State::S1;
+				dsp_pcin->setPort(\CDIN_FDBK_SEL, cdin_fdbk_sel);
 
-                // check if shifting is required for wide multiplier implmentation
-                if (SHIFT == 17)
-                {
-                    dsp_pcin->setPort(\ARSHFT17, State::S1);
-                }
-                
+				// check if shifting is required for wide multiplier implmentation
+				if (SHIFT == 17)
+				{
+					dsp_pcin->setPort(\ARSHFT17, State::S1);
+				}
+				
 
-                log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
+				log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
 
 			} else {
 				log_debug("  Blocking %s -> %s cascade (exceeds max: %d)\n", log_id(dsp), log_id(dsp_pcin), MAX_DSP_CASCADE);
@@ -159,47 +159,47 @@ arg next
 //          (b) 'C' port is driven by the 'P' output of the previous DSP cell
 //          (c) has its 'PCIN' port unused
 match nextP
-    // find candidates where nextP.C port is driven (maybe partially) by chain's tail DSP.P port
-    //      and with no registers in between (since cascade path cannot be pipelined)
+	// find candidates where nextP.C port is driven (maybe partially) by chain's tail DSP.P port
+	//      and with no registers in between (since cascade path cannot be pipelined)
 
-    // reg C must not be used
-    select port(nextP, \C_BYPASS, SigSpec()).is_fully_ones()
+	// reg C must not be used
+	select port(nextP, \C_BYPASS, SigSpec()).is_fully_ones()
 
-    // must be same DSP type
-    select nextP->type.in(\MACC_PA)
+	// must be same DSP type
+	select nextP->type.in(\MACC_PA)
 
-    // port C should be driven by something
+	// port C should be driven by something
 	select nusers(port(nextP, \C, SigSpec())) > 1
 
-    // CIN must be unused
+	// CIN must be unused
 	select nusers(port(nextP, \PCIN, SigSpec())) == 0
-    
-    // should not have internal feedback connection
-    select port(nextP, \CDIN_FDBK_SEL, SigSpec()).is_fully_zero()
 
-    // SHIFT should be unused
-    select port(nextP, \ARSHFT17_BYPASS).is_fully_ones()
-    select port(nextP, \ARSHFT17).is_fully_zero()
-    select nusers(port(nextP, \ARSHFT17, SigSpec())) == 0
+	// should not have internal feedback connection
+	select port(nextP, \CDIN_FDBK_SEL, SigSpec()).is_fully_zero()
 
-    // current DSP cell can be cascaded with the back of the cascade chain
+	// SHIFT should be unused
+	select port(nextP, \ARSHFT17_BYPASS).is_fully_ones()
+	select port(nextP, \ARSHFT17).is_fully_zero()
+	select nusers(port(nextP, \ARSHFT17, SigSpec())) == 0
+
+	// current DSP cell can be cascaded with the back of the cascade chain
 	// index <SigBit> port(nextP, \C)[0] === port(std::get<0>(chain.back()), \P)[0] || port(nextP, \C)[0] === port(std::get<0>(chain.back()), \P)[17]
-    filter port(nextP, \C)[0] == port(std::get<0>(chain.back()), \P)[0] || port(nextP, \C)[0] == port(std::get<0>(chain.back()), \P)[17]
+	filter port(nextP, \C)[0] == port(std::get<0>(chain.back()), \P)[0] || port(nextP, \C)[0] == port(std::get<0>(chain.back()), \P)[17]
 
 	// semioptional
 
-    optional
+	optional
 endmatch
 
 code next
 	next = nextP;
 
-    // keep DSP type consistent in the chain
-    // currently since we only have one type anyways, this line is always false
+	// keep DSP type consistent in the chain
+	// currently since we only have one type anyways, this line is always false
 	if (next && next->type != first->type) reject;
 
-    // break infinite recursion when there's a combinational loop
-    if (visited.count(next) > 0) reject;
+	// break infinite recursion when there's a combinational loop
+	if (visited.count(next) > 0) reject;
 
 endcode
 
@@ -207,32 +207,30 @@ endcode
 //     longest possible chain
 code
 	if (next) {
-        SigSpec driver_sigP = port(std::get<0>(chain.back()), \P);
-        int shift = 0;
-        if (port(next, \C)[0] == port(std::get<0>(chain.back()), \P)[17]) shift = 17;
+		SigSpec driver_sigP = port(std::get<0>(chain.back()), \P);
+		int shift = 0;
+		if (port(next, \C)[0] == port(std::get<0>(chain.back()), \P)[17]) shift = 17;
 
 		chain.emplace_back(next, shift);
-        visited.insert(next);
-       
+		visited.insert(next);
+		
 		SigSpec sigC = unextend(port(next, \C));
 
-            //     Make sure driverDSP.P === DSP.C
-            if (GetSize(sigC) + shift <= GetSize(driver_sigP) && driver_sigP.extract(shift, GetSize(sigC)) == sigC)
-            {
-                subpattern(tail);
-            }
-                
-
+		// Make sure driverDSP.P === DSP.C
+		if (GetSize(sigC) + shift <= GetSize(driver_sigP) && driver_sigP.extract(shift, GetSize(sigC)) == sigC)
+		{
+			subpattern(tail);
+		}
 	} else {
 		if (GetSize(chain) > GetSize(longest_chain))
 			longest_chain = chain;
 	}
 finally
 	if (next)
-    {
-        visited.erase(next);
-        chain.pop_back();
-    }
+	{
+		visited.erase(next);
+		chain.pop_back();
+	}
 		
 
 endcode
\ No newline at end of file
diff --git a/techlibs/mchp/LSRAM.txt b/techlibs/mchp/LSRAM.txt
index abd274eecec..c6926df2722 100644
--- a/techlibs/mchp/LSRAM.txt
+++ b/techlibs/mchp/LSRAM.txt
@@ -45,11 +45,11 @@ ram block $__LSRAM_TDP_ {
 	option "WIDTH_CONFIG" "REGULAR" {
 
 		# Data-Width | Address bits
-		# 1			 | 14
-		# 2		     | 13
+		# 1	         | 14
+		# 2	         | 13
 		# 4	         | 12
 		# 8	         | 11
-		# 16	     | 10
+		# 16         | 10
 
 		# 14 address bits
 		abits 14;
@@ -60,12 +60,12 @@ ram block $__LSRAM_TDP_ {
 	option "WIDTH_CONFIG" "ALIGN" {
 		
 		# Data-Width | Address bits
-		# 5			 | 12
-		# 10		 | 11
-		# 20	     | 10
+		# 5	         | 12
+		# 10         | 11
+		# 20         | 10
 
 		# Quick "hack" to fix address bit alignment by setting address bits to 12.
-		#	If abits=14, tool will think there are 14 bits for width=5, 13 bits for width=10, 12 bits for width=20
+		#   If abits=14, tool will think there are 14 bits for width=5, 13 bits for width=10, 12 bits for width=20
 		#   THe LSRAM_map.v file detects if this option is being used, and adjusts the address port alignments accordingly.
 		abits 12;
 
@@ -134,12 +134,12 @@ ram block $__LSRAM_SDP_ {
 	option "WIDTH_CONFIG" "REGULAR" {
 
 		# Data-Width | Address bits
-		# 1			 | 14
-		# 2		     | 13
+		# 1	         | 14
+		# 2	         | 13
 		# 4	         | 12
 		# 8	         | 11
-		# 16	     | 10
-		# 32	     | 9
+		# 16         | 10
+		# 32         | 9
 
 		abits 14;
 
@@ -152,10 +152,10 @@ ram block $__LSRAM_SDP_ {
 	option "WIDTH_CONFIG" "ALIGN" {
 		
 		# Data-Width | Address bits
-		# 5			 | 12
-		# 10		 | 11
-		# 20	     | 10
-		# 40	     | 9
+		# 5	         | 12
+		# 10         | 11
+		# 20         | 10
+		# 40         | 9
 
 		# Same trick as TSP RAM for alignment
 		abits 12;
diff --git a/techlibs/mchp/LSRAM_map.v b/techlibs/mchp/LSRAM_map.v
index 6eaf2f4590b..b7cb8486800 100644
--- a/techlibs/mchp/LSRAM_map.v
+++ b/techlibs/mchp/LSRAM_map.v
@@ -73,25 +73,25 @@ wire [2:0] B_BLK_SEL = (PORT_B_RD_USED == 1 || PORT_B_WR_USED == 1) ?  3'b111 :
 
 // wires for write data 
 generate
-    wire [19:0] A_write_data;
-    wire [19:0] B_write_data;
-    if (PORT_A_WIDTH == 16) begin
-        assign A_write_data[7:0] = PORT_A_WR_DATA[7:0];
-        assign A_write_data[17:10] = PORT_A_WR_DATA[15:8];
-        assign A_write_data[9:8] = 2'b0;
-        assign A_write_data[19:18] = 2'b0;
-    end else begin
-        assign A_write_data[PORT_A_WIDTH-1:0] = PORT_A_WR_DATA;
-    end
-
-    if (PORT_B_WIDTH == 16) begin
-        assign B_write_data[7:0] = PORT_B_WR_DATA[7:0];
-        assign B_write_data[17:10] = PORT_B_WR_DATA[15:8];
-        assign B_write_data[9:8] = 2'b0;
-        assign B_write_data[19:18] = 2'b0;
-    end else begin
-        assign B_write_data[PORT_B_WIDTH-1:0] = PORT_B_WR_DATA;
-    end
+	wire [19:0] A_write_data;
+	wire [19:0] B_write_data;
+	if (PORT_A_WIDTH == 16) begin
+		assign A_write_data[7:0] = PORT_A_WR_DATA[7:0];
+		assign A_write_data[17:10] = PORT_A_WR_DATA[15:8];
+		assign A_write_data[9:8] = 2'b0;
+		assign A_write_data[19:18] = 2'b0;
+	end else begin
+		assign A_write_data[PORT_A_WIDTH-1:0] = PORT_A_WR_DATA;
+	end
+
+	if (PORT_B_WIDTH == 16) begin
+		assign B_write_data[7:0] = PORT_B_WR_DATA[7:0];
+		assign B_write_data[17:10] = PORT_B_WR_DATA[15:8];
+		assign B_write_data[9:8] = 2'b0;
+		assign B_write_data[19:18] = 2'b0;
+	end else begin
+		assign B_write_data[PORT_B_WIDTH-1:0] = PORT_B_WR_DATA;
+	end
 endgenerate
 
 // wires for read data
@@ -106,58 +106,58 @@ wire [1:0] B_write_EN = (PORT_B_WR_EN_WIDTH == 1) ? {1'b0, PORT_B_WR_EN} : PORT_
 
 // port width
 wire [2:0] A_width = (PORT_A_WIDTH == 1) ? 3'b000 :
-                     (PORT_A_WIDTH == 2) ? 3'b001 :
-                     (PORT_A_WIDTH == 4 || PORT_A_WIDTH == 5) ? 3'b010 :
-                     (PORT_A_WIDTH == 8 || PORT_A_WIDTH == 10) ? 3'b011 : 3'b100;
+					(PORT_A_WIDTH == 2) ? 3'b001 :
+					(PORT_A_WIDTH == 4 || PORT_A_WIDTH == 5) ? 3'b010 :
+					(PORT_A_WIDTH == 8 || PORT_A_WIDTH == 10) ? 3'b011 : 3'b100;
 wire [2:0] B_width = (PORT_B_WIDTH == 1) ? 3'b000 :
-                     (PORT_B_WIDTH == 2) ? 3'b001 :
-                     (PORT_B_WIDTH == 4 || PORT_B_WIDTH == 5) ? 3'b010 :
-                     (PORT_B_WIDTH == 8 || PORT_B_WIDTH == 10) ? 3'b011 : 3'b100;
+					(PORT_B_WIDTH == 2) ? 3'b001 :
+					(PORT_B_WIDTH == 4 || PORT_B_WIDTH == 5) ? 3'b010 :
+					(PORT_B_WIDTH == 8 || PORT_B_WIDTH == 10) ? 3'b011 : 3'b100;
 
 // write modes
 wire [1:0] A_write_mode = PORT_A_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 : 
-                          PORT_A_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10;
+						PORT_A_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10;
 wire [1:0] B_write_mode = PORT_B_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 : 
-                          PORT_B_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10;
+						PORT_B_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10;
 
 RAM1K20 #(
-    `PARAMS_INIT_LSRAM
+	`PARAMS_INIT_LSRAM
 ) _TECHMAP_REPLACE_ (
-    
-    // port A
-    .A_ADDR(A_address),
-    .A_BLK_EN(A_BLK_SEL),
-    .A_CLK(PORT_A_CLK),
-    .A_DIN(A_write_data),
-    .A_DOUT(A_read_data),
-    .A_WEN(A_write_EN),
-    .A_REN(PORT_A_RD_EN),
-    .A_WIDTH(A_width),
-    .A_WMODE(A_write_mode),
-    .A_BYPASS(1'b1),
-    .A_DOUT_EN(1'b1),
-    .A_DOUT_SRST_N(1'b1),
-    .A_DOUT_ARST_N(1'b1),
-
-    // port B
-    .B_ADDR(B_address),
-    .B_BLK_EN(B_BLK_SEL),
-    .B_CLK(PORT_B_CLK),
-    .B_DIN(B_write_data),
-    .B_DOUT(B_read_data),
-    .B_WEN(B_write_EN),
-    .B_REN(PORT_B_RD_EN),
-    .B_WIDTH(B_width),
-    .B_WMODE(B_write_mode),
-    .B_BYPASS(1'b1),
-    .B_DOUT_EN(1'b1),
-    .B_DOUT_SRST_N(1'b1),
-    .B_DOUT_ARST_N(1'b1),
-    
-    // Disable ECC for TDP
-    .ECC_EN(1'b0), 
-    .ECC_BYPASS(1'b1),
-    .BUSY_FB(1'b0)
+
+	// port A
+	.A_ADDR(A_address),
+	.A_BLK_EN(A_BLK_SEL),
+	.A_CLK(PORT_A_CLK),
+	.A_DIN(A_write_data),
+	.A_DOUT(A_read_data),
+	.A_WEN(A_write_EN),
+	.A_REN(PORT_A_RD_EN),
+	.A_WIDTH(A_width),
+	.A_WMODE(A_write_mode),
+	.A_BYPASS(1'b1),
+	.A_DOUT_EN(1'b1),
+	.A_DOUT_SRST_N(1'b1),
+	.A_DOUT_ARST_N(1'b1),
+
+	// port B
+	.B_ADDR(B_address),
+	.B_BLK_EN(B_BLK_SEL),
+	.B_CLK(PORT_B_CLK),
+	.B_DIN(B_write_data),
+	.B_DOUT(B_read_data),
+	.B_WEN(B_write_EN),
+	.B_REN(PORT_B_RD_EN),
+	.B_WIDTH(B_width),
+	.B_WMODE(B_write_mode),
+	.B_BYPASS(1'b1),
+	.B_DOUT_EN(1'b1),
+	.B_DOUT_SRST_N(1'b1),
+	.B_DOUT_ARST_N(1'b1),
+
+	// Disable ECC for TDP
+	.ECC_EN(1'b0), 
+	.ECC_BYPASS(1'b1),
+	.BUSY_FB(1'b0)
 
 );
 
@@ -201,122 +201,119 @@ assign B_address = (OPTION_WIDTH_CONFIG == "REGULAR") ? PORT_W_ADDR : {PORT_W_AD
 // port A is for read, port B for write
 parameter PORT_W_USED = 0;
 parameter PORT_R_USED = 0;
-wire [2:0] A_BLK_SEL = (PORT_R_USED == 1) ?  3'b111 : 3'b000;
-wire [2:0] B_BLK_SEL = (PORT_W_USED == 1) ?  3'b111 : 3'b000;
+wire [2:0] A_BLK_SEL = (PORT_R_USED == 1) ? 3'b111 : 3'b000;
+wire [2:0] B_BLK_SEL = (PORT_W_USED == 1) ? 3'b111 : 3'b000;
 
 // read/write data & write enables
 // Currently support only wide write, width = {32, 40}
 generate
-    wire [19:0] A_write_data;
-    wire [19:0] B_write_data;
-    wire [1:0] A_write_EN;
-    wire [1:0] B_write_EN;
-
-    // write port (A provides MSB) 
-    if (PORT_W_WIDTH == 32) begin
-
-        assign B_write_data[3:0] = PORT_W_WR_DATA[3:0];
-        assign B_write_data[8:5] = PORT_W_WR_DATA[7:4];
-        assign B_write_data[13:10] = PORT_W_WR_DATA[11:8];
-        assign B_write_data[18:15] = PORT_W_WR_DATA[15:12];
-        assign B_write_data[4] = 1'b0;
-        assign B_write_data[9] = 1'b0;
-        assign B_write_data[14] = 1'b0;
-        assign B_write_data[19] = 1'b0;
-
-        assign A_write_data[3:0] = PORT_W_WR_DATA[19:16];
-        assign A_write_data[8:5] = PORT_W_WR_DATA[23:20];
-        assign A_write_data[13:10] = PORT_W_WR_DATA[27:24];
-        assign A_write_data[18:15] = PORT_W_WR_DATA[31:28];
-        assign A_write_data[4] = 1'b0;
-        assign A_write_data[9] = 1'b0;
-        assign A_write_data[14] = 1'b0;
-        assign A_write_data[19] = 1'b0;
-        
-    end else if (PORT_W_WIDTH == 40) begin
-        assign B_write_data = PORT_W_WR_DATA[19:0];
-        assign A_write_data = PORT_W_WR_DATA[39:20];         
-    end
-
-    // byte-write enables
-    assign A_write_EN = PORT_W_WR_EN[1:0];
-    assign B_write_EN = PORT_W_WR_EN[3:2];
-
-    // read ports (A provides MSB)
-    wire [19:0] A_read_data;
-    wire [19:0] B_read_data;
-    if (PORT_R_WIDTH == 32) begin
-        assign PORT_R_RD_DATA[3:0] = B_read_data[3:0];
-        assign PORT_R_RD_DATA[8:5] = B_read_data[7:4];
-        assign PORT_R_RD_DATA[13:10] = B_read_data[11:8];
-        assign PORT_R_RD_DATA[18:15] = B_read_data[15:12];
-
-        assign PORT_R_RD_DATA[19:16] = A_read_data[3:0];
-        assign PORT_R_RD_DATA[23:20] = A_read_data[8:5];
-        assign PORT_R_RD_DATA[27:24] = A_read_data[13:10];
-        assign PORT_R_RD_DATA[31:28] = A_read_data[18:15];
-    end else if (PORT_R_WIDTH == 40) begin
-        assign PORT_R_RD_DATA[19:0] = B_read_data[19:0];
-        assign PORT_R_RD_DATA[39:20] = A_read_data[19:0];
-    end
-    
+	wire [19:0] A_write_data;
+	wire [19:0] B_write_data;
+	wire [1:0] A_write_EN;
+	wire [1:0] B_write_EN;
+
+	// write port (A provides MSB) 
+	if (PORT_W_WIDTH == 32) begin
+
+		assign B_write_data[3:0] = PORT_W_WR_DATA[3:0];
+		assign B_write_data[8:5] = PORT_W_WR_DATA[7:4];
+		assign B_write_data[13:10] = PORT_W_WR_DATA[11:8];
+		assign B_write_data[18:15] = PORT_W_WR_DATA[15:12];
+		assign B_write_data[4] = 1'b0;
+		assign B_write_data[9] = 1'b0;
+		assign B_write_data[14] = 1'b0;
+		assign B_write_data[19] = 1'b0;
+
+		assign A_write_data[3:0] = PORT_W_WR_DATA[19:16];
+		assign A_write_data[8:5] = PORT_W_WR_DATA[23:20];
+		assign A_write_data[13:10] = PORT_W_WR_DATA[27:24];
+		assign A_write_data[18:15] = PORT_W_WR_DATA[31:28];
+		assign A_write_data[4] = 1'b0;
+		assign A_write_data[9] = 1'b0;
+		assign A_write_data[14] = 1'b0;
+		assign A_write_data[19] = 1'b0;
+		
+	end else if (PORT_W_WIDTH == 40) begin
+		assign B_write_data = PORT_W_WR_DATA[19:0];
+		assign A_write_data = PORT_W_WR_DATA[39:20];
+	end
+
+	// byte-write enables
+	assign A_write_EN = PORT_W_WR_EN[1:0];
+	assign B_write_EN = PORT_W_WR_EN[3:2];
+
+	// read ports (A provides MSB)
+	wire [19:0] A_read_data;
+	wire [19:0] B_read_data;
+	if (PORT_R_WIDTH == 32) begin
+		assign PORT_R_RD_DATA[3:0] = B_read_data[3:0];
+		assign PORT_R_RD_DATA[8:5] = B_read_data[7:4];
+		assign PORT_R_RD_DATA[13:10] = B_read_data[11:8];
+		assign PORT_R_RD_DATA[18:15] = B_read_data[15:12];
+
+		assign PORT_R_RD_DATA[19:16] = A_read_data[3:0];
+		assign PORT_R_RD_DATA[23:20] = A_read_data[8:5];
+		assign PORT_R_RD_DATA[27:24] = A_read_data[13:10];
+		assign PORT_R_RD_DATA[31:28] = A_read_data[18:15];
+	end else if (PORT_R_WIDTH == 40) begin
+		assign PORT_R_RD_DATA[19:0] = B_read_data[19:0];
+		assign PORT_R_RD_DATA[39:20] = A_read_data[19:0];
+	end
 endgenerate
 
 // port width
 wire [2:0] A_width = (PORT_R_WIDTH == 1) ? 3'b000 :
-                     (PORT_R_WIDTH == 2) ? 3'b001 :
-                     (PORT_R_WIDTH == 4 || PORT_R_WIDTH == 5) ? 3'b010 :
-                     (PORT_R_WIDTH == 8 || PORT_R_WIDTH == 10) ? 3'b011 : 
-                     (PORT_R_WIDTH == 16 || PORT_R_WIDTH == 20) ? 3'b100 : 3'b101;
+					(PORT_R_WIDTH == 2) ? 3'b001 :
+					(PORT_R_WIDTH == 4 || PORT_R_WIDTH == 5) ? 3'b010 :
+					(PORT_R_WIDTH == 8 || PORT_R_WIDTH == 10) ? 3'b011 : 
+					(PORT_R_WIDTH == 16 || PORT_R_WIDTH == 20) ? 3'b100 : 3'b101;
 wire [2:0] B_width = (PORT_W_WIDTH == 1) ? 3'b000 :
-                     (PORT_W_WIDTH == 2) ? 3'b001 :
-                     (PORT_W_WIDTH == 4 || PORT_W_WIDTH == 5) ? 3'b010 :
-                     (PORT_W_WIDTH == 8 || PORT_W_WIDTH == 10) ? 3'b011 :
-                     (PORT_W_WIDTH == 16 || PORT_W_WIDTH == 20) ? 3'b100 : 3'b101;
+					(PORT_W_WIDTH == 2) ? 3'b001 :
+					(PORT_W_WIDTH == 4 || PORT_W_WIDTH == 5) ? 3'b010 :
+					(PORT_W_WIDTH == 8 || PORT_W_WIDTH == 10) ? 3'b011 :
+					(PORT_W_WIDTH == 16 || PORT_W_WIDTH == 20) ? 3'b100 : 3'b101;
 
 // write modes
 wire [1:0] A_write_mode = 2'b00;
 wire [1:0] B_write_mode = 2'b00;
 
 RAM1K20 #(
-    `PARAMS_INIT_LSRAM
+	`PARAMS_INIT_LSRAM
 ) _TECHMAP_REPLACE_ (
-    // port A - read
-    .A_ADDR(A_address),
-    .A_BLK_EN(A_BLK_SEL),
-    .A_CLK(PORT_R_CLK),
-    .A_DIN(A_write_data),
-    .A_DOUT(A_read_data),
-    .A_WEN(A_write_EN),
-    .A_REN(PORT_R_RD_EN),
-    .A_WIDTH(A_width),
-    .A_WMODE(A_write_mode),
-    .A_BYPASS(1'b1),
-    .A_DOUT_EN(1'b1),
-    .A_DOUT_SRST_N(1'b1),
-    .A_DOUT_ARST_N(1'b1),
-
-    // port B - write
-    .B_ADDR(B_address),
-    .B_BLK_EN(B_BLK_SEL),
-    .B_CLK(PORT_W_CLK),
-    .B_DIN(B_write_data),
-    .B_DOUT(B_read_data),
-    .B_WEN(B_write_EN),
-    .B_REN(PORT_R_RD_EN),
-    .B_WIDTH(B_width),
-    .B_WMODE(B_write_mode),
-    .B_BYPASS(1'b1),
-    .B_DOUT_EN(1'b1),
-    .B_DOUT_SRST_N(1'b1),
-    .B_DOUT_ARST_N(1'b1),
-    
-    // Disable ECC for SDP
-    .ECC_EN(1'b0), 
-    .ECC_BYPASS(1'b1),
-
-    .BUSY_FB(1'b0)
-
+	// port A - read
+	.A_ADDR(A_address),
+	.A_BLK_EN(A_BLK_SEL),
+	.A_CLK(PORT_R_CLK),
+	.A_DIN(A_write_data),
+	.A_DOUT(A_read_data),
+	.A_WEN(A_write_EN),
+	.A_REN(PORT_R_RD_EN),
+	.A_WIDTH(A_width),
+	.A_WMODE(A_write_mode),
+	.A_BYPASS(1'b1),
+	.A_DOUT_EN(1'b1),
+	.A_DOUT_SRST_N(1'b1),
+	.A_DOUT_ARST_N(1'b1),
+
+	// port B - write
+	.B_ADDR(B_address),
+	.B_BLK_EN(B_BLK_SEL),
+	.B_CLK(PORT_W_CLK),
+	.B_DIN(B_write_data),
+	.B_DOUT(B_read_data),
+	.B_WEN(B_write_EN),
+	.B_REN(PORT_R_RD_EN),
+	.B_WIDTH(B_width),
+	.B_WMODE(B_write_mode),
+	.B_BYPASS(1'b1),
+	.B_DOUT_EN(1'b1),
+	.B_DOUT_SRST_N(1'b1),
+	.B_DOUT_ARST_N(1'b1),
+
+	// Disable ECC for SDP
+	.ECC_EN(1'b0), 
+	.ECC_BYPASS(1'b1),
+	.BUSY_FB(1'b0)
 );
 
 
diff --git a/techlibs/mchp/cells_map.v b/techlibs/mchp/cells_map.v
index f52018aef96..9194b023b51 100644
--- a/techlibs/mchp/cells_map.v
+++ b/techlibs/mchp/cells_map.v
@@ -18,36 +18,36 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
 // DFFs
 module \$_DFFE_PN0P_ (input D, C, R, E, output Q);
-  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
+	SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
 endmodule
 
 module \$_DFFE_PN1P_ (input D, C, R, E, output Q);
-  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
+	SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
 endmodule
 
 // for sync set/reset registers, we can pass them into ABC9. So we need to follow the simplification idiom
-//    and map to intermediate cell types
+// and map to intermediate cell types
 module \$_SDFFCE_PN0P_ (input D, C, R, E, output Q);
-  MCHP_SYNC_RESET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Reset(R), .En(E), .Q(Q));
+	MCHP_SYNC_RESET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Reset(R), .En(E), .Q(Q));
 endmodule
 
 module \$_SDFFCE_PN1P_ (input D, C, R, E, output Q);
-  MCHP_SYNC_SET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Set(R), .En(E), .Q(Q));
+	MCHP_SYNC_SET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Set(R), .En(E), .Q(Q));
 endmodule
 
 
 // LATCHES
 
 module \$_DLATCH_PN0_ (input D, R, E, output Q);
-  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
+	SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
 endmodule
 
 module \$_DLATCH_PN1_ (input D, R, E, output Q);
-  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
+	SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
 endmodule
 
 module \$_DLATCH_P_ (input D, E, output Q);
-  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(1'b1), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
+	SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(1'b1), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
 endmodule
 
 // map intermediate flops to SLE
@@ -58,7 +58,7 @@ module MCHP_SYNC_SET_DFF(
 	input Set,
 	input En,
 	output Q);
-  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(CLK), .EN(En), .ALn(1'b1), .ADn(1'b0), .SLn(Set), .SD(1'b1), .LAT(1'b0), .Q(Q));
+	SLE _TECHMAP_REPLACE_ (.D(D), .CLK(CLK), .EN(En), .ALn(1'b1), .ADn(1'b0), .SLn(Set), .SD(1'b1), .LAT(1'b0), .Q(Q));
 endmodule
 
 module MCHP_SYNC_RESET_DFF(
@@ -67,7 +67,7 @@ module MCHP_SYNC_RESET_DFF(
 	input Reset,
 	input En,
 	output Q);
-  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(CLK), .EN(En), .ALn(1'b1), .ADn(1'b0), .SLn(Reset), .SD(1'b0), .LAT(1'b0), .Q(Q));
+	SLE _TECHMAP_REPLACE_ (.D(D), .CLK(CLK), .EN(En), .ALn(1'b1), .ADn(1'b0), .SLn(Reset), .SD(1'b0), .LAT(1'b0), .Q(Q));
 endmodule
 `endif
 
@@ -76,29 +76,29 @@ endmodule
 
 `ifndef NO_LUT
 module \$lut (A, Y);
-  parameter WIDTH = 0;
-  parameter LUT = 0;
-
-  (* force_downto *)
-  input [WIDTH-1:0] A;
-  output Y;
-
-  generate
-    if (WIDTH == 1) begin
-      CFG1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]));
-    end else
-    if (WIDTH == 2) begin
-      CFG2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]));
-    end else
-    if (WIDTH == 3) begin
-      CFG3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]));
-    end else
-    if (WIDTH == 4) begin
-      CFG4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
-    end else begin
-      wire _TECHMAP_FAIL_ = 1;
-    end
-  endgenerate
+	parameter WIDTH = 0;
+	parameter LUT = 0;
+
+	(* force_downto *)
+	input [WIDTH-1:0] A;
+	output Y;
+
+	generate
+	if (WIDTH == 1) begin
+		CFG1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]));
+	end else
+	if (WIDTH == 2) begin
+		CFG2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]));
+	end else
+	if (WIDTH == 3) begin
+		CFG3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]));
+	end else
+	if (WIDTH == 4) begin
+		CFG4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+	end else begin
+		wire _TECHMAP_FAIL_ = 1;
+	end
+	endgenerate
 endmodule
 `endif
 
diff --git a/techlibs/mchp/cells_sim.v b/techlibs/mchp/cells_sim.v
index a7a96d86ae9..a89f17843be 100644
--- a/techlibs/mchp/cells_sim.v
+++ b/techlibs/mchp/cells_sim.v
@@ -46,9 +46,9 @@ module CFG1 (
 );
 	parameter [1:0] INIT = 2'h0;
 	assign Y = INIT >> A;
-  specify
-    (A => Y) = 127;
-  endspecify
+	specify
+		(A => Y) = 127;
+	endspecify
 endmodule
 
 (* abc9_lut=2 *)
@@ -59,10 +59,10 @@ module CFG2 (
 );
 	parameter [3:0] INIT = 4'h0;
 	assign Y = INIT >> {B, A};
-  specify
-    (A => Y) = 238;
-    (B => Y) = 127;
-  endspecify
+	specify
+		(A => Y) = 238;
+		(B => Y) = 127;
+	endspecify
 endmodule
 
 (* abc9_lut=3 *)
@@ -74,11 +74,11 @@ module CFG3 (
 );
 	parameter [7:0] INIT = 8'h0;
 	assign Y = INIT >> {C, B, A};
-  specify
-    (A => Y) = 407;
-    (B => Y) = 238;
-    (C => Y) = 127;
-  endspecify
+	specify
+		(A => Y) = 407;
+		(B => Y) = 238;
+		(C => Y) = 127;
+	endspecify
 endmodule
 
 (* abc9_lut=3 *)
@@ -91,12 +91,12 @@ module CFG4 (
 );
 	parameter [15:0] INIT = 16'h0;
 	assign Y = INIT >> {D, C, B, A};
-  specify
-    (A => Y) = 472;
-    (B => Y) = 407;
-    (C => Y) = 238;
-    (D => Y) = 127;
-  endspecify
+	specify
+		(A => Y) = 472;
+		(B => Y) = 407;
+		(C => Y) = 238;
+		(D => Y) = 127;
+	endspecify
 endmodule
 
 module BUFF (
@@ -176,12 +176,12 @@ module MCHP_SYNC_SET_DFF(
 	end
 
 	specify
-		$setup(D , posedge CLK &&& En && Set, 0);  // neg setup not supported?
+		$setup(D , posedge CLK &&& En && Set, 0); // neg setup not supported?
 		$setup(En, posedge CLK, 109);
 		$setup(Set, posedge CLK &&& En, 404);
 		if (En && !Set) (posedge CLK => (Q : 1'b1)) = 303;
-		if (En && Set)  (posedge CLK => (Q : D)) = 303;
-  	endspecify
+		if (En && Set) (posedge CLK => (Q : D)) = 303;
+	endspecify
 endmodule
 
 (* abc9_flop, lib_whitebox *)
@@ -202,12 +202,12 @@ module MCHP_SYNC_RESET_DFF(
 	end
 
 	specify
-		$setup(D , posedge CLK &&& En && Reset, 0);  // neg setup not supported?
+		$setup(D , posedge CLK &&& En && Reset, 0); // neg setup not supported?
 		$setup(En, posedge CLK, 109);
 		$setup(Reset, posedge CLK &&& En, 404);
 		if (En && !Reset) (posedge CLK => (Q : 1'b0)) = 303;
-		if (En && Reset)  (posedge CLK => (Q : D)) = 303;
-  	endspecify
+		if (En && Reset) (posedge CLK => (Q : D)) = 303;
+	endspecify
 endmodule
 
 module SLE (
@@ -272,19 +272,19 @@ module ARI1 (
 	
 	specify
 		//pin to pin path delay 
-		(A => Y )     = 472;
-		(B => Y )     = 407;
-		(C => Y )     = 238;
-		(D => Y )     = 127;
-		(A => S )     = 572;
-		(B => S )     = 507;
-		(C => S )     = 338;
-		(D => S )     = 227;
-		(FCI => S )   = 100;
-		(A => FCO )   = 522;
-		(B => FCO )   = 457;
-		(C => FCO )   = 288;
-		(D => FCO )   = 177;
+		(A => Y )	= 472;
+		(B => Y )	= 407;
+		(C => Y )	= 238;
+		(D => Y )	= 127;
+		(A => S )	= 572;
+		(B => S )	= 507;
+		(C => S )	= 338;
+		(D => S )	= 227;
+		(FCI => S ) = 100;
+		(A => FCO ) = 522;
+		(B => FCO ) = 457;
+		(C => FCO ) = 288;
+		(D => FCO ) = 177;
 		(FCI => FCO ) = 50;
 	endspecify
 endmodule
@@ -508,8 +508,8 @@ module CLKBUF (
 	parameter IOSTD = "";
 	assign Y = PAD;
 	specify
-    	(PAD => Y) = 50;
-  	endspecify
+	 	(PAD => Y) = 50;
+	endspecify
 endmodule
 
 (* blackbox *)
@@ -595,7 +595,7 @@ endmodule
 (* blackbox *)
 module SYSRESET (
 	(* iopad_external_pin *)
-	input  DEVRST_N,
+	input DEVRST_N,
 	output POWER_ON_RESET_N);
 endmodule
 
@@ -603,7 +603,7 @@ endmodule
 (* blackbox *)
 module XTLOSC (
 	(* iopad_external_pin *)
-	input  XTL,
+	input XTL,
 	output CLKOUT);
 	parameter [1:0] MODE = 2'h3;
 	parameter real FREQUENCY = 20.0;
@@ -611,191 +611,190 @@ endmodule
 
 (* blackbox *)
 module RAM1K18 (
-	input [13:0]  A_ADDR,
-	input [2:0]   A_BLK,
+	input [13:0] 	A_ADDR,
+	input [2:0] 	A_BLK,
 	(* clkbuf_sink *)
-	input	      A_CLK,
-	input [17:0]  A_DIN,
-	output [17:0] A_DOUT,
-	input [1:0]   A_WEN,
-	input [2:0]   A_WIDTH,
-	input	      A_WMODE,
-	input	      A_ARST_N,
-	input	      A_DOUT_LAT,
-	input	      A_DOUT_ARST_N,
+	input			A_CLK,
+	input [17:0] 	A_DIN,
+	output [17:0]	A_DOUT,
+	input [1:0]		A_WEN,
+	input [2:0]		A_WIDTH,
+	input			A_WMODE,
+	input			A_ARST_N,
+	input			A_DOUT_LAT,
+	input			A_DOUT_ARST_N,
 	(* clkbuf_sink *)
-	input	      A_DOUT_CLK,
-	input	      A_DOUT_EN,
-	input	      A_DOUT_SRST_N,
+	input			A_DOUT_CLK,
+	input			A_DOUT_EN,
+	input			A_DOUT_SRST_N,
 
-	input [13:0]  B_ADDR,
-	input [2:0]   B_BLK,
+	input [13:0]	B_ADDR,
+	input [2:0] 	B_BLK,
 	(* clkbuf_sink *)
-	input	      B_CLK,
-	input [17:0]  B_DIN,
-	output [17:0] B_DOUT,
-	input [1:0]   B_WEN,
-	input [2:0]   B_WIDTH,
-	input	      B_WMODE,
-	input	      B_ARST_N,
-	input	      B_DOUT_LAT,
-	input	      B_DOUT_ARST_N,
+	input			B_CLK,
+	input [17:0] 	B_DIN,
+	output [17:0]	B_DOUT,
+	input [1:0]		B_WEN,
+	input [2:0]		B_WIDTH,
+	input			B_WMODE,
+	input			B_ARST_N,
+	input			B_DOUT_LAT,
+	input			B_DOUT_ARST_N,
 	(* clkbuf_sink *)
-	input	      B_DOUT_CLK,
-	input	      B_DOUT_EN,
-	input	      B_DOUT_SRST_N,
-
-	input	      A_EN,
-	input	      B_EN,
-	input	      SII_LOCK,
-	output	      BUSY);
+	input			B_DOUT_CLK,
+	input			B_DOUT_EN,
+	input			B_DOUT_SRST_N,
+	input			A_EN,
+	input			B_EN,
+	input			SII_LOCK,
+	output			BUSY);
 endmodule
 
 (* blackbox *)
 module RAM64x18 (
-	input [9:0]   A_ADDR,
-	input [1:0]   A_BLK,
-	input [2:0]   A_WIDTH,
-	output [17:0] A_DOUT,
-	input	      A_DOUT_ARST_N,
+	input [9:0] 	A_ADDR,
+	input [1:0] 	A_BLK,
+	input [2:0] 	A_WIDTH,
+	output [17:0] 	A_DOUT,
+	input			A_DOUT_ARST_N,
 	(* clkbuf_sink *)
-	input	      A_DOUT_CLK,
-	input	      A_DOUT_EN,
-	input	      A_DOUT_LAT,
-	input	      A_DOUT_SRST_N,
+	input	 		A_DOUT_CLK,
+	input	 		A_DOUT_EN,
+	input	 		A_DOUT_LAT,
+	input	 		A_DOUT_SRST_N,
 	(* clkbuf_sink *)
-	input	      A_ADDR_CLK,
-	input	      A_ADDR_EN,
-	input	      A_ADDR_LAT,
-	input	      A_ADDR_SRST_N,
-	input	      A_ADDR_ARST_N,
-
-	input [9:0]   B_ADDR,
-	input [1:0]   B_BLK,
-	input [2:0]   B_WIDTH,
-	output [17:0] B_DOUT,
-	input	      B_DOUT_ARST_N,
+	input			A_ADDR_CLK,
+	input	 		A_ADDR_EN,
+	input	 		A_ADDR_LAT,
+	input	 		A_ADDR_SRST_N,
+	input	 		A_ADDR_ARST_N,
+
+	input [9:0]		B_ADDR,
+	input [1:0]		B_BLK,
+	input [2:0]		B_WIDTH,
+	output [17:0] 	B_DOUT,
+	input			B_DOUT_ARST_N,
 	(* clkbuf_sink *)
-	input	      B_DOUT_CLK,
-	input	      B_DOUT_EN,
-	input	      B_DOUT_LAT,
-	input	      B_DOUT_SRST_N,
+	input			B_DOUT_CLK,
+	input			B_DOUT_EN,
+	input			B_DOUT_LAT,
+	input			B_DOUT_SRST_N,
 	(* clkbuf_sink *)
-	input	      B_ADDR_CLK,
-	input	      B_ADDR_EN,
-	input	      B_ADDR_LAT,
-	input	      B_ADDR_SRST_N,
-	input	      B_ADDR_ARST_N,
+	input			B_ADDR_CLK,
+	input			B_ADDR_EN,
+	input			B_ADDR_LAT,
+	input			B_ADDR_SRST_N,
+	input			B_ADDR_ARST_N,
 
-	input [9:0]   C_ADDR,
+	input [9:0]		C_ADDR,
 	(* clkbuf_sink *)
-	input	      C_CLK,
-	input [17:0]  C_DIN,
-	input	      C_WEN,
-	input [1:0]   C_BLK,
-	input [2:0]   C_WIDTH,
+	input			C_CLK,
+	input [17:0]	C_DIN,
+	input			C_WEN,
+	input [1:0]		C_BLK,
+	input [2:0]		C_WIDTH,
 
-	input	      A_EN,
-	input	      B_EN,
-	input	      C_EN,
-	input	      SII_LOCK,
-	output	      BUSY);
+	input			A_EN,
+	input			B_EN,
+	input			C_EN,
+	input			SII_LOCK,
+	output			BUSY);
 endmodule
 
 (* blackbox *)
 module MACC_PA (
-  input DOTP,
-  input SIMD,
-  input OVFL_CARRYOUT_SEL,
-  input CLK,
-  input AL_N,
-  input [17:0] A,
-  input A_BYPASS,
-  input A_SRST_N,
-  input A_EN,
-  input [17:0] B,
-  input B_BYPASS,
-  input B_SRST_N,
-  input B_EN,
-  input [17:0] D,
-  input D_BYPASS,
-  input D_ARST_N,
-  input D_SRST_N,
-  input D_EN,
-  input CARRYIN,
-  input [47:0] C,
-  input C_BYPASS,
-  input C_ARST_N,
-  input C_SRST_N,
-  input C_EN,
-  input [47:0] CDIN,
-  output [47:0] P,
-  output OVFL_CARRYOUT,
-  input P_BYPASS,
-  input P_SRST_N,
-  input P_EN,
-  output [47:0] CDOUT,
-  input PASUB,
-  input PASUB_BYPASS,
-  input PASUB_AD_N,
-  input PASUB_SL_N,
-  input PASUB_SD_N,
-  input PASUB_EN,
-  input [1:0] CDIN_FDBK_SEL,
-  input CDIN_FDBK_SEL_BYPASS,
-  input [1:0] CDIN_FDBK_SEL_AD_N,
-  input CDIN_FDBK_SEL_SL_N,
-  input [1:0] CDIN_FDBK_SEL_SD_N,
-  input CDIN_FDBK_SEL_EN,
-  input ARSHFT17,
-  input ARSHFT17_BYPASS,
-  input ARSHFT17_AD_N,
-  input ARSHFT17_SL_N,
-  input ARSHFT17_SD_N,
-  input ARSHFT17_EN,
-  input SUB,
-  input SUB_BYPASS,
-  input SUB_AD_N,
-  input SUB_SL_N,
-  input SUB_SD_N,
-  input SUB_EN
+	input DOTP,
+	input SIMD,
+	input OVFL_CARRYOUT_SEL,
+	input CLK,
+	input AL_N,
+	input [17:0] A,
+	input A_BYPASS,
+	input A_SRST_N,
+	input A_EN,
+	input [17:0] B,
+	input B_BYPASS,
+	input B_SRST_N,
+	input B_EN,
+	input [17:0] D,
+	input D_BYPASS,
+	input D_ARST_N,
+	input D_SRST_N,
+	input D_EN,
+	input CARRYIN,
+	input [47:0] C,
+	input C_BYPASS,
+	input C_ARST_N,
+	input C_SRST_N,
+	input C_EN,
+	input [47:0] CDIN,
+	output [47:0] P,
+	output OVFL_CARRYOUT,
+	input P_BYPASS,
+	input P_SRST_N,
+	input P_EN,
+	output [47:0] CDOUT,
+	input PASUB,
+	input PASUB_BYPASS,
+	input PASUB_AD_N,
+	input PASUB_SL_N,
+	input PASUB_SD_N,
+	input PASUB_EN,
+	input [1:0] CDIN_FDBK_SEL,
+	input CDIN_FDBK_SEL_BYPASS,
+	input [1:0] CDIN_FDBK_SEL_AD_N,
+	input CDIN_FDBK_SEL_SL_N,
+	input [1:0] CDIN_FDBK_SEL_SD_N,
+	input CDIN_FDBK_SEL_EN,
+	input ARSHFT17,
+	input ARSHFT17_BYPASS,
+	input ARSHFT17_AD_N,
+	input ARSHFT17_SL_N,
+	input ARSHFT17_SD_N,
+	input ARSHFT17_EN,
+	input SUB,
+	input SUB_BYPASS,
+	input SUB_AD_N,
+	input SUB_SL_N,
+	input SUB_SD_N,
+	input SUB_EN
 );
 endmodule
 
 (* blackbox *)
 module RAM1K20 (
-    input  [13:0] A_ADDR,
-    input  [2:0]  A_BLK_EN,
-    input         A_CLK,
-    input  [19:0] A_DIN,
-    output [19:0] A_DOUT,
-    input  [1:0]  A_WEN,
-    input         A_REN,
-    input  [2:0]  A_WIDTH,
-    input  [1:0]  A_WMODE,
-    input         A_BYPASS,
-    input         A_DOUT_EN,
-    input         A_DOUT_SRST_N,
-    input         A_DOUT_ARST_N,
-    input  [13:0] B_ADDR,
-    input  [2:0]  B_BLK_EN,
-    input         B_CLK,
-    input  [19:0] B_DIN,
-    output [19:0] B_DOUT,
-    input  [1:0]  B_WEN,
-    input         B_REN,
-    input  [2:0]  B_WIDTH,
-    input  [1:0]  B_WMODE,
-    input         B_BYPASS,
-    input         B_DOUT_EN,
-    input         B_DOUT_SRST_N,
-    input         B_DOUT_ARST_N,
-    input	      ECC_EN, 
-    input 		  ECC_BYPASS,
-    output        SB_CORRECT,
-    output 		  DB_DETECT,
-    input         BUSY_FB,
-    output        ACCESS_BUSY
+	input 	[13:0] 	A_ADDR,
+	input 	[2:0]	A_BLK_EN,
+	input			A_CLK,
+	input 	[19:0]	A_DIN,
+	output	[19:0]	A_DOUT,
+	input 	[1:0]	A_WEN,
+	input			A_REN,
+	input 	[2:0]	A_WIDTH,
+	input 	[1:0]	A_WMODE,
+	input 			A_BYPASS,
+	input 			A_DOUT_EN,
+	input 			A_DOUT_SRST_N,
+	input 			A_DOUT_ARST_N,
+	input 	[13:0]	B_ADDR,
+	input 	[2:0]	B_BLK_EN,
+	input			B_CLK,
+	input 	[19:0] 	B_DIN,
+	output	[19:0]	B_DOUT,
+	input 	[1:0]	B_WEN,
+	input			B_REN,
+	input 	[2:0]	B_WIDTH,
+	input 	[1:0]	B_WMODE,
+	input			B_BYPASS,
+	input			B_DOUT_EN,
+	input			B_DOUT_SRST_N,
+	input			B_DOUT_ARST_N,
+	input			ECC_EN, 
+	input			ECC_BYPASS,
+	output			SB_CORRECT,
+	output			DB_DETECT,
+	input			BUSY_FB,
+	output			ACCESS_BUSY
 );
 parameter INIT0 = 1024'h0;
 parameter INIT1 = 1024'h0;
@@ -821,29 +820,29 @@ endmodule
 
 (* blackbox *)
 module RAM64x12 (
-	input           R_CLK,
-	input  [5:0]    R_ADDR,
-	input           R_ADDR_BYPASS,
+	input			R_CLK,
+	input [5:0]		R_ADDR,
+	input			R_ADDR_BYPASS,
 	input			R_ADDR_EN,
 	input 			R_ADDR_SL_N,
 	input			R_ADDR_SD,
 	input			R_ADDR_AL_N, 
 	input			R_ADDR_AD_N,
-	input           BLK_EN,
-	output [11:0]   R_DATA,
-	input           R_DATA_BYPASS,
+	input			BLK_EN,
+	output [11:0]	R_DATA,
+	input			R_DATA_BYPASS,
 	input	 		R_DATA_EN,
 	input	 		R_DATA_SL_N,
 	input	 		R_DATA_SD,
 	input	 		R_DATA_AL_N,
 	input	 		R_DATA_AD_N,
 
-	input           W_CLK,
-	input  [5:0]    W_ADDR,
-	input  [11:0]   W_DATA,
-	input           W_EN,
+	input		W_CLK,
+	input [5:0]	W_ADDR,
+	input [11:0]W_DATA,
+	input		W_EN,
 
-	input           BUSY_FB,
-	output          ACCESS_BUSY
+	input		BUSY_FB,
+	output		ACCESS_BUSY
 );
 endmodule
\ No newline at end of file
diff --git a/techlibs/mchp/mchp_dffopt.cc b/techlibs/mchp/mchp_dffopt.cc
index 3e73ea6a3b6..474e9275d16 100644
--- a/techlibs/mchp/mchp_dffopt.cc
+++ b/techlibs/mchp/mchp_dffopt.cc
@@ -166,11 +166,11 @@ struct MchpDffOptPass : public Pass {
 			// Iterate through FFs.
 			for (auto cell : module->selected_cells())
 			{
-				
-				if (!cell->type.in(ID(SLE)))  // not a SLE
+
+				if (!cell->type.in(ID(SLE))) // not a SLE
 					continue;
 				if (cell->getPort(ID(LAT)).is_fully_ones()) // skip latch
-				  	continue;
+					continue;
 				if (cell->get_bool_attribute(ID::keep)) // keep attribute
 					continue;
 				if (!cell->getPort(ID(ALn)).is_fully_ones()) // async FF
diff --git a/techlibs/mchp/pf_dsp_map.v b/techlibs/mchp/pf_dsp_map.v
index a6b65a421af..b416841fb41 100644
--- a/techlibs/mchp/pf_dsp_map.v
+++ b/techlibs/mchp/pf_dsp_map.v
@@ -24,71 +24,71 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
 	parameter Y_WIDTH = 0;
 
 	wire [47:0] P_48;
-    // For pin descriptions, see Section 9 of PolarFire FPGA Macro Library Guide:
-    // https://coredocs.s3.amazonaws.com/Libero/2021_2/Tool/pf_mlg.pdf
+	// For pin descriptions, see Section 9 of PolarFire FPGA Macro Library Guide:
+	// https://coredocs.s3.amazonaws.com/Libero/2021_2/Tool/pf_mlg.pdf
 	MACC_PA _TECHMAP_REPLACE_ (
 		.DOTP(1'b0), 
-        .SIMD(1'b0), 
-        .OVFL_CARRYOUT_SEL(1'b0), 
+		.SIMD(1'b0), 
+		.OVFL_CARRYOUT_SEL(1'b0), 
 
-        .AL_N(1'b1),
-        .A(A),
-        .A_BYPASS(1'b1),
-        .A_SRST_N(1'b1),
-        .A_EN(1'b1),
+		.AL_N(1'b1),
+		.A(A),
+		.A_BYPASS(1'b1),
+		.A_SRST_N(1'b1),
+		.A_EN(1'b1),
 
-        .B(B),
-        .B_BYPASS(1'b1),
-        .B_SRST_N(1'b1),
-        .B_EN(1'b1),
+		.B(B),
+		.B_BYPASS(1'b1),
+		.B_SRST_N(1'b1),
+		.B_EN(1'b1),
 
-        .D(18'b0),
-        .D_BYPASS(1'b1),
-        .D_ARST_N(1'b1),
-        .D_SRST_N(1'b1),
-        .D_EN(1'b1),
-        
-        .CARRYIN(1'b0),
-        .C(48'b0),
-        .C_BYPASS(1'b1),
-        .C_ARST_N(1'b1),
-        .C_SRST_N(1'b1),
-        .C_EN(1'b1),
+		.D(18'b0),
+		.D_BYPASS(1'b1),
+		.D_ARST_N(1'b1),
+		.D_SRST_N(1'b1),
+		.D_EN(1'b1),
+		
+		.CARRYIN(1'b0),
+		.C(48'b0),
+		.C_BYPASS(1'b1),
+		.C_ARST_N(1'b1),
+		.C_SRST_N(1'b1),
+		.C_EN(1'b1),
 
-        
-        .P(P_48),
+		
+		.P(P_48),
 
-        .P_BYPASS(1'b1),
-        .P_SRST_N(1'b1),
-        .P_EN(1'b1),
+		.P_BYPASS(1'b1),
+		.P_SRST_N(1'b1),
+		.P_EN(1'b1),
 
-        .PASUB(1'b0),
-        .PASUB_BYPASS(1'b1),
-        .PASUB_AD_N(1'b0),
-        .PASUB_SL_N(1'b1),
-        .PASUB_SD_N(1'b0),
-        .PASUB_EN(1'b1),
+		.PASUB(1'b0),
+		.PASUB_BYPASS(1'b1),
+		.PASUB_AD_N(1'b0),
+		.PASUB_SL_N(1'b1),
+		.PASUB_SD_N(1'b0),
+		.PASUB_EN(1'b1),
 
-        .CDIN_FDBK_SEL(2'b00),
-        .CDIN_FDBK_SEL_BYPASS(1'b1),
-        .CDIN_FDBK_SEL_AD_N(2'b00),
-        .CDIN_FDBK_SEL_SL_N(1'b1),
-        .CDIN_FDBK_SEL_SD_N(2'b00),
-        .CDIN_FDBK_SEL_EN(1'b1),
+		.CDIN_FDBK_SEL(2'b00),
+		.CDIN_FDBK_SEL_BYPASS(1'b1),
+		.CDIN_FDBK_SEL_AD_N(2'b00),
+		.CDIN_FDBK_SEL_SL_N(1'b1),
+		.CDIN_FDBK_SEL_SD_N(2'b00),
+		.CDIN_FDBK_SEL_EN(1'b1),
 
-        .ARSHFT17(1'b0),
-        .ARSHFT17_BYPASS(1'b1),
-        .ARSHFT17_AD_N(1'b0),
-        .ARSHFT17_SL_N(1'b1),
-        .ARSHFT17_SD_N(1'b0),
-        .ARSHFT17_EN(1'b1),
+		.ARSHFT17(1'b0),
+		.ARSHFT17_BYPASS(1'b1),
+		.ARSHFT17_AD_N(1'b0),
+		.ARSHFT17_SL_N(1'b1),
+		.ARSHFT17_SD_N(1'b0),
+		.ARSHFT17_EN(1'b1),
 
-        .SUB(1'b0),
-        .SUB_BYPASS(1'b1),
-        .SUB_AD_N(1'b0),
-        .SUB_SL_N(1'b1),
-        .SUB_SD_N(1'b0),
-        .SUB_EN(1'b1)
+		.SUB(1'b0),
+		.SUB_BYPASS(1'b1),
+		.SUB_AD_N(1'b0),
+		.SUB_SL_N(1'b1),
+		.SUB_SD_N(1'b0),
+		.SUB_EN(1'b1)
 
 	);
 	assign Y = P_48;
diff --git a/techlibs/mchp/tests/Registers/Registers.v b/techlibs/mchp/tests/Registers/Registers.v
index b5bd6f4afea..b9a86d1d519 100644
--- a/techlibs/mchp/tests/Registers/Registers.v
+++ b/techlibs/mchp/tests/Registers/Registers.v
@@ -17,21 +17,21 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 module Registers(
-    input clk,
-    input en,
-    input rst,
-    input D,
-    output Q
+	input clk,
+	input en,
+	input rst,
+	input D,
+	output Q
 );
 parameter LOAD_DATA = 1;
 
 // active low async reset
 always @(posedge clk, negedge rst) begin
-    if (rst == 0) begin
-        Q <= LOAD_DATA;
-    end else if(en) begin
-        Q <= D;
-    end
+	if (rst == 0) begin
+		Q <= LOAD_DATA;
+	end else if(en) begin
+		Q <= D;
+	end
 end
 
 
diff --git a/techlibs/mchp/tests/carryout/carryout.v b/techlibs/mchp/tests/carryout/carryout.v
index c109435b866..8da139774f3 100644
--- a/techlibs/mchp/tests/carryout/carryout.v
+++ b/techlibs/mchp/tests/carryout/carryout.v
@@ -25,10 +25,10 @@ input [n:0] a;
 input [n:0] b;
 input [n-1:0] c;
 
-    always @(a,b,c) 
-    begin
-        {cout,out} = a * b + c;
-        
-    end
+	always @(a,b,c) 
+	begin
+		{cout,out} = a * b + c;
+		
+	end
 
 endmodule
diff --git a/techlibs/mchp/tests/cascade/cascade.v b/techlibs/mchp/tests/cascade/cascade.v
index 6be738846d2..19dbac9dd8c 100644
--- a/techlibs/mchp/tests/cascade/cascade.v
+++ b/techlibs/mchp/tests/cascade/cascade.v
@@ -17,13 +17,13 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 module cascade(
-    input signed [5:0] in_A,
-    input signed [4:0] in_B,
-    input signed [4:0] in_D,
-    output signed [11:0] out_P,
+	input signed [5:0] in_A,
+	input signed [4:0] in_B,
+	input signed [4:0] in_D,
+	output signed [11:0] out_P,
 
-    input signed [4:0] casA,
-    input signed [4:0] casB
+	input signed [4:0] casA,
+	input signed [4:0] casB
 
 );
 
diff --git a/techlibs/mchp/tests/dff_opt/dff_opt.v b/techlibs/mchp/tests/dff_opt/dff_opt.v
index b14bf4be5c1..67d8c3d51f5 100644
--- a/techlibs/mchp/tests/dff_opt/dff_opt.v
+++ b/techlibs/mchp/tests/dff_opt/dff_opt.v
@@ -17,11 +17,11 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 module dff_opt(
-    input clk,
-    input [1:0] D_comb,
-    input [1:0] EN_comb,
-    input [1:0] RST_comb,
-    output bar
+	input clk,
+	input [1:0] D_comb,
+	input [1:0] EN_comb,
+	input [1:0] RST_comb,
+	output bar
 );
 
 // DFF with enable that can be merged into D
@@ -32,11 +32,11 @@ assign bar = foo;
 
 // sync reset
 always@(posedge clk) begin
-    if (&RST_comb) begin
-        foo <= 0;
-    end else begin
-        foo <= &D_comb;
-    end
+	if (&RST_comb) begin
+		foo <= 0;
+	end else begin
+		foo <= &D_comb;
+	end
 end
 
 endmodule
diff --git a/techlibs/mchp/tests/full_dsp/full_dsp.v b/techlibs/mchp/tests/full_dsp/full_dsp.v
index a99a4ee1c89..ead82b57322 100644
--- a/techlibs/mchp/tests/full_dsp/full_dsp.v
+++ b/techlibs/mchp/tests/full_dsp/full_dsp.v
@@ -16,12 +16,12 @@ ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 module full_dsp(
-    input signed[5:0] in_A,
-    input signed [4:0] in_B,
-    input signed [11:0] in_C,
-    input signed [4:0] in_D,
+	input signed[5:0] in_A,
+	input signed [4:0] in_B,
+	input signed [11:0] in_C,
+	input signed [4:0] in_D,
 
-    output signed [12:0] out_Y
+	output signed [12:0] out_Y
 );
 
 assign out_Y = ((in_D + in_B)*in_A)+in_C;
diff --git a/techlibs/mchp/tests/large_mult/large_mult.v b/techlibs/mchp/tests/large_mult/large_mult.v
index 9f7ad6f92ec..8f861f37fa6 100644
--- a/techlibs/mchp/tests/large_mult/large_mult.v
+++ b/techlibs/mchp/tests/large_mult/large_mult.v
@@ -17,9 +17,9 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 module large_mult(
-    input signed [20:0] in1,
-    input signed [17:0] in2,
-    output signed [38:0] out1
+	input signed [20:0] in1,
+	input signed [17:0] in2,
+	output signed [38:0] out1
 );
 assign out1 = in1 * in2;
 endmodule
\ No newline at end of file
diff --git a/techlibs/mchp/tests/mac/mac.v b/techlibs/mchp/tests/mac/mac.v
index e32b21867ad..855cf97aaa9 100644
--- a/techlibs/mchp/tests/mac/mac.v
+++ b/techlibs/mchp/tests/mac/mac.v
@@ -17,27 +17,27 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 module mac(
-    input clk,
-    input signed [4:0] in_A,
-    input signed [4:0] in_B,
-    input signed [4:0] in_D,
-    output reg signed [11:0] out_P,
+	input clk,
+	input signed [4:0] in_A,
+	input signed [4:0] in_B,
+	input signed [4:0] in_D,
+	output reg signed [11:0] out_P,
 
-    input srst_P,
+	input srst_P,
 
-    input signed [4:0] casA,
-    input signed [4:0] casB
+	input signed [4:0] casA,
+	input signed [4:0] casB
 
 );
 
 
 // sync reset P
 always@(posedge clk) begin
-    if (~srst_P) begin
-        out_P <= 12'h000;
-    end else begin
-        out_P <= in_A * (in_B + in_D) + out_P;
-    end
+	if (~srst_P) begin
+		out_P <= 12'h000;
+	end else begin
+		out_P <= in_A * (in_B + in_D) + out_P;
+	end
 end
 
 endmodule
\ No newline at end of file
diff --git a/techlibs/mchp/tests/postAdd_mult/postAdd_mult.v b/techlibs/mchp/tests/postAdd_mult/postAdd_mult.v
index 90a758dbc8d..666ac8ffcb2 100644
--- a/techlibs/mchp/tests/postAdd_mult/postAdd_mult.v
+++ b/techlibs/mchp/tests/postAdd_mult/postAdd_mult.v
@@ -17,11 +17,11 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 module postAdd_mult(
-    input signed[17:0] in_A,
-    input signed [17:0] in_B,
-    input signed [17:0] in_C,
+	input signed[17:0] in_A,
+	input signed [17:0] in_B,
+	input signed [17:0] in_C,
 
-    output signed [35:0] out_Y
+	output signed [35:0] out_Y
 );
 
 assign out_Y = (in_B*in_A)+in_C;
diff --git a/techlibs/mchp/tests/post_adder/post_adder.v b/techlibs/mchp/tests/post_adder/post_adder.v
index 13d95414164..93c339d7e27 100644
--- a/techlibs/mchp/tests/post_adder/post_adder.v
+++ b/techlibs/mchp/tests/post_adder/post_adder.v
@@ -17,12 +17,12 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 module post_adder(
-    input signed [5:0] in_A,
-    input signed [4:0] in_B,
-    input signed [4:0] in_D,
-    input signed [11:0] in_C,
-    
-    output [12:0] out_Y
+	input signed [5:0] in_A,
+	input signed [4:0] in_B,
+	input signed [4:0] in_D,
+	input signed [11:0] in_C,
+
+	output [12:0] out_Y
 );
 
 assign out_Y = (in_D + in_B) * in_A + in_C;
diff --git a/techlibs/mchp/tests/pre_adder_dsp/pre_adder_dsp.v b/techlibs/mchp/tests/pre_adder_dsp/pre_adder_dsp.v
index 2343dd1a482..7e30278c462 100644
--- a/techlibs/mchp/tests/pre_adder_dsp/pre_adder_dsp.v
+++ b/techlibs/mchp/tests/pre_adder_dsp/pre_adder_dsp.v
@@ -17,11 +17,11 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 module pre_adder_dsp(
-    input signed [5:0] in_A,
-    input signed [4:0] in_B,
-    input signed [4:0] in_D,
-    
-    output [11:0] out_Y
+	input signed [5:0] in_A,
+	input signed [4:0] in_B,
+	input signed [4:0] in_D,
+
+	output [11:0] out_Y
 );
 
 assign out_Y = in_A * (in_B + in_D);
diff --git a/techlibs/mchp/tests/ram_SDP/ram_SDP.v b/techlibs/mchp/tests/ram_SDP/ram_SDP.v
index 30c724256c7..4e83c544a97 100644
--- a/techlibs/mchp/tests/ram_SDP/ram_SDP.v
+++ b/techlibs/mchp/tests/ram_SDP/ram_SDP.v
@@ -28,11 +28,11 @@ output reg [d_width-1:0] q;
 reg [d_width-1:0] mem [mem_depth-1:0];
 
 always @(posedge clk) begin
-    if (we) begin 
-        mem[waddr] <= data;
-    end else begin
-        q <= mem[waddr];
-    end
+	if (we) begin 
+		mem[waddr] <= data;
+	end else begin
+		q <= mem[waddr];
+	end
 end
 
 endmodule
diff --git a/techlibs/mchp/tests/ram_TDP/ram_TDP.v b/techlibs/mchp/tests/ram_TDP/ram_TDP.v
index d223574503a..54b63b7a8fd 100644
--- a/techlibs/mchp/tests/ram_TDP/ram_TDP.v
+++ b/techlibs/mchp/tests/ram_TDP/ram_TDP.v
@@ -27,11 +27,11 @@ reg [addr_width - 1 : 0] addra_reg, addrb_reg;
 reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];
 
 always @ (posedge clka)
-    begin
-        addra_reg <= addra;
-        if(wea)
-            mem[addra] <= dataina;
-    end
+	begin
+		addra_reg <= addra;
+		if(wea)
+			mem[addra] <= dataina;
+	end
 
 always @ (posedge clkb)
 begin
diff --git a/techlibs/mchp/tests/reduce/reduce.v b/techlibs/mchp/tests/reduce/reduce.v
index 603d0317377..b2b01ba92ff 100644
--- a/techlibs/mchp/tests/reduce/reduce.v
+++ b/techlibs/mchp/tests/reduce/reduce.v
@@ -17,10 +17,10 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 module reduce(
-        input [7:0] data,
-        output Y
+	input [7:0] data,
+	output Y
 
-    );
+);
 
 
 assign Y = ^data;
diff --git a/techlibs/mchp/tests/reg_c/reg_c.v b/techlibs/mchp/tests/reg_c/reg_c.v
index 1d9ee0f3265..63d9d8b2e3e 100644
--- a/techlibs/mchp/tests/reg_c/reg_c.v
+++ b/techlibs/mchp/tests/reg_c/reg_c.v
@@ -17,34 +17,34 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 module reg_c(
-    input clk,
+	input clk,
 
-    // active high
-    input en_A,
-    input en_B,
-    input en_D,
-    input en_P,
+	// active high
+	input en_A,
+	input en_B,
+	input en_D,
+	input en_P,
 
-    // active low
-    input srst_A,
-    input srst_B,
-    input srst_D,
-    input srst_P,
+	// active low
+	input srst_A,
+	input srst_B,
+	input srst_D,
+	input srst_P,
 
-    // active low
-    input arst_D,
+	// active low
+	input arst_D,
 
-    input srst_C,
-    input arst_C,
+	input srst_C,
+	input arst_C,
 
 
-    input signed [5:0] in_A,
-    input signed [4:0] in_B,
-    input signed [4:0] in_C,
-    input signed [4:0] in_D,
-    
-    
-    output reg [11:0] out_P
+	input signed [5:0] in_A,
+	input signed [4:0] in_B,
+	input signed [4:0] in_C,
+	input signed [4:0] in_D,
+
+
+	output reg [11:0] out_P
 
 );
 
@@ -69,54 +69,54 @@ reg signed [4:0] reg_D;
 
 // sync reset A
 always@(posedge clk) begin
-    // if (~srst_A_N) begin
-    if (srst_A_N) begin
-        reg_A = 6'b000000;
-    end else begin
-        reg_A = in_A;
-    end
+	// if (~srst_A_N) begin
+	if (srst_A_N) begin
+		reg_A = 6'b000000;
+	end else begin
+		reg_A = in_A;
+	end
 end
 
 
 
 // sync reset B
 always@(posedge clk) begin
-    if (srst_B_N) begin
-        reg_B = 5'b00000;
-    end else begin
-        reg_B = in_B;
-    end
+	if (srst_B_N) begin
+		reg_B = 5'b00000;
+	end else begin
+		reg_B = in_B;
+	end
 end
 
 
 
 // async reset D
 always@(posedge clk, negedge arst_D) begin
-    if (~arst_D) begin
-        reg_D = 5'b00000;
-    end else begin
-        reg_D = in_D;
-    end
+	if (~arst_D) begin
+		reg_D = 5'b00000;
+	end else begin
+		reg_D = in_D;
+	end
 end
 
 // sync reset C
 always@(posedge clk) begin
-    if (srst_C_N) begin
-        reg_C = 5'b00000;
-    end else begin
-        reg_C = in_C;
-    end
+if (srst_C_N) begin
+	reg_C = 5'b00000;
+end else begin
+	reg_C = in_C;
+end
 end
 
 
 
 // sync reset P
 always@(posedge clk) begin
-    if (srst_P_N) begin
-        out_P = 12'h000;
-    end else begin
-        out_P = reg_A * (reg_B + reg_D) + reg_C;
-    end
+if (srst_P_N) begin
+	out_P = 12'h000;
+end else begin
+	out_P = reg_A * (reg_B + reg_D) + reg_C;
+end
 end
 
 endmodule
\ No newline at end of file
diff --git a/techlibs/mchp/tests/reg_test/reg_test.v b/techlibs/mchp/tests/reg_test/reg_test.v
index dadec7ae86b..b10012d026c 100644
--- a/techlibs/mchp/tests/reg_test/reg_test.v
+++ b/techlibs/mchp/tests/reg_test/reg_test.v
@@ -17,28 +17,28 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 module reg_test(
-    input clk,
+	input clk,
 
-    // active high
-    input en_A,
-    input en_B,
-    input en_D,
-    input en_P,
+	// active high
+	input en_A,
+	input en_B,
+	input en_D,
+	input en_P,
 
-    // active low
-    input srst_A,
-    input srst_B,
-    input srst_D,
-    input srst_P,
+	// active low
+	input srst_A,
+	input srst_B,
+	input srst_D,
+	input srst_P,
 
-    // active low
-    input arst_D,
+	// active low
+	input arst_D,
 
-    input signed [5:0] in_A,
-    input signed [4:0] in_B,
-    input signed [4:0] in_D,
-    
-    output reg [11:0] out_P
+	input signed [5:0] in_A,
+	input signed [4:0] in_B,
+	input signed [4:0] in_D,
+
+	output reg [11:0] out_P
 
 );
 
@@ -60,38 +60,38 @@ reg signed [4:0] reg_D;
 
 // sync reset A
 always@(posedge clk) begin
-    if (srst_A_N) begin
-        reg_A = 6'b000000;
-    end else begin
-        reg_A = in_A;
-    end
+	if (srst_A_N) begin
+		reg_A = 6'b000000;
+	end else begin
+		reg_A = in_A;
+	end
 end
 
 // sync reset B
 always@(posedge clk) begin
-    if (srst_B_N) begin
-        reg_B = 5'b00000;
-    end else begin
-        reg_B = in_B;
-    end
+	if (srst_B_N) begin
+		reg_B = 5'b00000;
+	end else begin
+		reg_B = in_B;
+	end
 end
 
 // async reset D
 always@(posedge clk, negedge arst_D) begin
-    if (~arst_D) begin
-        reg_D = 5'b00000;
-    end else begin
-        reg_D = in_D;
-    end
+	if (~arst_D) begin
+		reg_D = 5'b00000;
+	end else begin
+		reg_D = in_D;
+	end
 end
 
 // sync reset P
 always@(posedge clk) begin
-    if (srst_P_N) begin
-        out_P = 12'h000;
-    end else begin
-        out_P = reg_A * (reg_B + reg_D);
-    end
+	if (srst_P_N) begin
+		out_P = 12'h000;
+	end else begin
+		out_P = reg_A * (reg_B + reg_D);
+	end
 end
 
 endmodule
\ No newline at end of file
diff --git a/techlibs/mchp/tests/signed_mult/signed_mult.v b/techlibs/mchp/tests/signed_mult/signed_mult.v
index 09d324af1dc..797d0f5322e 100755
--- a/techlibs/mchp/tests/signed_mult/signed_mult.v
+++ b/techlibs/mchp/tests/signed_mult/signed_mult.v
@@ -17,10 +17,10 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 module signed_mult(
-    input signed [17:0] in_A,
-    input signed [17:0] in_B,
-    
-    output signed [35:0] out_Y
+	input signed [17:0] in_A,
+	input signed [17:0] in_B,
+
+	output signed [35:0] out_Y
 );
 
 assign out_Y = in_A * in_B;
diff --git a/techlibs/mchp/tests/simple_ram/simple_ram.v b/techlibs/mchp/tests/simple_ram/simple_ram.v
index 5117b1b3557..9eeba41cb3a 100644
--- a/techlibs/mchp/tests/simple_ram/simple_ram.v
+++ b/techlibs/mchp/tests/simple_ram/simple_ram.v
@@ -29,9 +29,9 @@ reg [19:0] mem [0:1023] ;
 assign dout = mem[addr_reg];
 
 always@(posedge clk) begin
-    addr_reg <= addr;
-    if(wr)
-        mem[addr]<= din;
+	addr_reg <= addr;
+	if(wr)
+		mem[addr]<= din;
 end
 endmodule
 
diff --git a/techlibs/mchp/tests/unsigned_mult/unsigned_mult.v b/techlibs/mchp/tests/unsigned_mult/unsigned_mult.v
index 987c77a37b2..22d3db2b12c 100644
--- a/techlibs/mchp/tests/unsigned_mult/unsigned_mult.v
+++ b/techlibs/mchp/tests/unsigned_mult/unsigned_mult.v
@@ -17,10 +17,10 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 module unsigned_mult(
-    input [10:0] in_A,
-    input signed [10:0] in_B,
-    
-    output [21:0] out_Y
+	input [10:0] in_A,
+	input signed [10:0] in_B,
+
+	output [21:0] out_Y
 );
 
 assign out_Y = in_A * in_B;
diff --git a/techlibs/mchp/tests/uram_ar/uram_ar.v b/techlibs/mchp/tests/uram_ar/uram_ar.v
index 524203c9b3c..b3b542df634 100644
--- a/techlibs/mchp/tests/uram_ar/uram_ar.v
+++ b/techlibs/mchp/tests/uram_ar/uram_ar.v
@@ -30,8 +30,8 @@ reg [d_width-1:0] mem [mem_depth-1:0];
 assign q = mem[waddr];
 
 always @(posedge clk) begin
-    if (we) 
-        mem[waddr] <= data;
+	if (we) 
+		mem[waddr] <= data;
 
 end
 
diff --git a/techlibs/mchp/tests/uram_sr/uram_sr.v b/techlibs/mchp/tests/uram_sr/uram_sr.v
index 2bb5888038d..1852dfc6890 100644
--- a/techlibs/mchp/tests/uram_sr/uram_sr.v
+++ b/techlibs/mchp/tests/uram_sr/uram_sr.v
@@ -26,7 +26,7 @@ reg [5:0] raddr_reg;
 reg [11:0] mem [0:63];
 assign dout = mem[raddr_reg];
 always@(posedge clk) begin
-    raddr_reg <= raddr; if(wr)
-    mem[waddr]<= din;
+	raddr_reg <= raddr; if(wr)
+	mem[waddr]<= din;
 end
 endmodule
\ No newline at end of file
diff --git a/techlibs/mchp/tests/widemux/widemux.v b/techlibs/mchp/tests/widemux/widemux.v
index 1fe28ba2886..e25c7df16b5 100644
--- a/techlibs/mchp/tests/widemux/widemux.v
+++ b/techlibs/mchp/tests/widemux/widemux.v
@@ -17,31 +17,31 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 module widemux(
-        input [3:0] data,
-        input S0,
-        input S1,
-        output Y
-
-    );
-
-    wire A, B;
-
-    always @ (*) begin 
-         if (S0)begin
-            A = data[1];
-            B = data[3];
-         end else begin 
-            A = data[0];
-            B = data[2];
-        end
-
-        if (S1)begin
-            Y = A;
-        end else begin
-            Y = B;
-        end
-
-    end
+	input [3:0] data,
+	input S0,
+	input S1,
+	output Y
+
+);
+
+wire A, B;
+
+always @ (*) begin 
+		if (S0)begin
+		A = data[1];
+		B = data[3];
+		end else begin 
+		A = data[0];
+		B = data[2];
+	end
+
+	if (S1)begin
+		Y = A;
+	end else begin
+		Y = B;
+	end
+
+end
 endmodule
 
 
diff --git a/techlibs/mchp/uSRAM.txt b/techlibs/mchp/uSRAM.txt
index 296fc8dd2e5..02ed8a4cf99 100644
--- a/techlibs/mchp/uSRAM.txt
+++ b/techlibs/mchp/uSRAM.txt
@@ -23,21 +23,21 @@ ram block $__uSRAM_AR_ {
 	# INIT supported
 	init any;
 
-    abits 6;
-    widths 12 per_port;
+	abits 6;
+	widths 12 per_port;
 
-    # single write enable wire
+	# single write enable wire
 	port sw "W" {
 		clock posedge;
 
-        # collision not supported, but write takes precedence and read data is invalid while writing to 
-        #       the same address
+		# collision not supported, but write takes precedence and read data is invalid while writing to 
+		# the same address
 		wrtrans all new;
 		
 		optional;
 	}
 	port ar "R" {
-        optional;
+		optional;
 	}
 }
 
@@ -48,14 +48,14 @@ ram block $__uSRAM_SR_ {
 
 	cost 42;
 
-    init any;
-    abits 6;
-    widths 12 per_port;
+	init any;
+	abits 6;
+widths 12 per_port;
 
 	port sw "W" {
 		clock posedge;
 
-        # collision not supported
+		# collision not supported
 		wrtrans all new;
 		
 		optional;
diff --git a/techlibs/mchp/uSRAM_map.v b/techlibs/mchp/uSRAM_map.v
index 9fce7193cad..242b027a9c5 100644
--- a/techlibs/mchp/uSRAM_map.v
+++ b/techlibs/mchp/uSRAM_map.v
@@ -17,7 +17,7 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 // See document PolarFire Family Fabric User Guide
-//   section 4.2 for port list.
+// section 4.2 for port list.
 
 // Asynchronous read
 module $__uSRAM_AR_ (...);
@@ -82,36 +82,36 @@ input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
 input PORT_W_WR_EN;
 
 // Read port clock and enable signal
-//   that async read uSRAM doesn't have
+// that async read uSRAM doesn't have
 input PORT_R_CLK;
 input PORT_R_RD_EN;
 input [ADDR_BITS-1:0] PORT_R_ADDR;
 output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
 
 RAM64x12 _TECHMAP_REPLACE_ (
-    .R_CLK(PORT_R_CLK),
-    .R_ADDR(PORT_R_ADDR),
-    .R_ADDR_BYPASS(1'b0),
-    .R_ADDR_EN(PORT_R_RD_EN),
-    .R_ADDR_SL_N(1'b1),
-    .R_ADDR_SD(1'b0),
-    .R_ADDR_AL_N(1'b1), 
-    .R_ADDR_AD_N(1'b0),
-    .BLK_EN(PORT_R_USED ? 1'b1 : 1'b0),
-    .R_DATA(PORT_R_RD_DATA),
-    .R_DATA_BYPASS(1'b1),
-    .R_DATA_EN(1'b0),
-    .R_DATA_SL_N(1'b1),
-    .R_DATA_SD(1'b0),
-    .R_DATA_AL_N(1'b1),
-    .R_DATA_AD_N(1'b0),
-
-    .W_CLK(PORT_W_CLK),
-    .W_ADDR(PORT_W_ADDR),
-    .W_DATA(PORT_W_WR_DATA),
-    .W_EN(PORT_W_WR_EN),
-
-    .BUSY_FB(1'b0)
+	.R_CLK(PORT_R_CLK),
+	.R_ADDR(PORT_R_ADDR),
+	.R_ADDR_BYPASS(1'b0),
+	.R_ADDR_EN(PORT_R_RD_EN),
+	.R_ADDR_SL_N(1'b1),
+	.R_ADDR_SD(1'b0),
+	.R_ADDR_AL_N(1'b1), 
+	.R_ADDR_AD_N(1'b0),
+	.BLK_EN(PORT_R_USED ? 1'b1 : 1'b0),
+	.R_DATA(PORT_R_RD_DATA),
+	.R_DATA_BYPASS(1'b1),
+	.R_DATA_EN(1'b0),
+	.R_DATA_SL_N(1'b1),
+	.R_DATA_SD(1'b0),
+	.R_DATA_AL_N(1'b1),
+	.R_DATA_AD_N(1'b0),
+
+	.W_CLK(PORT_W_CLK),
+	.W_ADDR(PORT_W_ADDR),
+	.W_DATA(PORT_W_WR_DATA),
+	.W_EN(PORT_W_WR_EN),
+
+	.BUSY_FB(1'b0)
 );
 
 endmodule

From 68a11c994146cd0bf1ef6d8813095fb6d3d6e97d Mon Sep 17 00:00:00 2001
From: Chun Lin Min <chunlin.min@microchip.com>
Date: Tue, 2 Jul 2024 13:51:48 -0700
Subject: [PATCH 180/499] more indent fix

---
 techlibs/mchp/LSRAM.txt   | 44 +++++++++++++++++++--------------------
 techlibs/mchp/LSRAM_map.v |  4 ++--
 techlibs/mchp/uSRAM.txt   |  2 +-
 3 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/techlibs/mchp/LSRAM.txt b/techlibs/mchp/LSRAM.txt
index c6926df2722..96dac535c57 100644
--- a/techlibs/mchp/LSRAM.txt
+++ b/techlibs/mchp/LSRAM.txt
@@ -44,12 +44,12 @@ ram block $__LSRAM_TDP_ {
 
 	option "WIDTH_CONFIG" "REGULAR" {
 
-		# Data-Width | Address bits
-		# 1	         | 14
-		# 2	         | 13
-		# 4	         | 12
-		# 8	         | 11
-		# 16         | 10
+		# Data-Width| Address bits
+		# 1			| 14
+		# 2			| 13
+		# 4			| 12
+		# 8			| 11
+		# 16		| 10
 
 		# 14 address bits
 		abits 14;
@@ -59,10 +59,10 @@ ram block $__LSRAM_TDP_ {
 	}
 	option "WIDTH_CONFIG" "ALIGN" {
 		
-		# Data-Width | Address bits
-		# 5	         | 12
-		# 10         | 11
-		# 20         | 10
+		# Data-Width| Address bits
+		# 5			| 12
+		# 10		| 11
+		# 20		| 10
 
 		# Quick "hack" to fix address bit alignment by setting address bits to 12.
 		#   If abits=14, tool will think there are 14 bits for width=5, 13 bits for width=10, 12 bits for width=20
@@ -133,13 +133,13 @@ ram block $__LSRAM_SDP_ {
 
 	option "WIDTH_CONFIG" "REGULAR" {
 
-		# Data-Width | Address bits
-		# 1	         | 14
-		# 2	         | 13
-		# 4	         | 12
-		# 8	         | 11
-		# 16         | 10
-		# 32         | 9
+		# Data-Width| Address bits
+		# 1			| 14
+		# 2			| 13
+		# 4			| 12
+		# 8			| 11
+		# 16		| 10
+		# 32		| 9
 
 		abits 14;
 
@@ -151,11 +151,11 @@ ram block $__LSRAM_SDP_ {
 	}
 	option "WIDTH_CONFIG" "ALIGN" {
 		
-		# Data-Width | Address bits
-		# 5	         | 12
-		# 10         | 11
-		# 20         | 10
-		# 40         | 9
+		# Data-Width| Address bits
+		# 5			| 12
+		# 10		| 11
+		# 20		| 10
+		# 40		| 9
 
 		# Same trick as TSP RAM for alignment
 		abits 12;
diff --git a/techlibs/mchp/LSRAM_map.v b/techlibs/mchp/LSRAM_map.v
index b7cb8486800..c84b5dd1935 100644
--- a/techlibs/mchp/LSRAM_map.v
+++ b/techlibs/mchp/LSRAM_map.v
@@ -68,8 +68,8 @@ assign B_address = (OPTION_WIDTH_CONFIG == "REGULAR") ? PORT_B_ADDR : {PORT_B_AD
 // if port is not used, set block sel to 0 to disable it (read-data output is set to 0)
 parameter PORT_A_RD_USED = 0;
 parameter PORT_A_WR_USED = 0;
-wire [2:0] A_BLK_SEL = (PORT_A_RD_USED == 1 || PORT_A_WR_USED == 1) ?  3'b111 : 3'b000;
-wire [2:0] B_BLK_SEL = (PORT_B_RD_USED == 1 || PORT_B_WR_USED == 1) ?  3'b111 : 3'b000;
+wire [2:0] A_BLK_SEL = (PORT_A_RD_USED == 1 || PORT_A_WR_USED == 1) ? 3'b111 : 3'b000;
+wire [2:0] B_BLK_SEL = (PORT_B_RD_USED == 1 || PORT_B_WR_USED == 1) ? 3'b111 : 3'b000;
 
 // wires for write data 
 generate
diff --git a/techlibs/mchp/uSRAM.txt b/techlibs/mchp/uSRAM.txt
index 02ed8a4cf99..10f9a143530 100644
--- a/techlibs/mchp/uSRAM.txt
+++ b/techlibs/mchp/uSRAM.txt
@@ -43,7 +43,7 @@ ram block $__uSRAM_AR_ {
 
 # synchronous read
 # NOTE: synchronous read can be realized by the address pipeline register or data pipeline register.
-#       This assumes address is synchronized
+#		This assumes address is synchronized
 ram block $__uSRAM_SR_ {
 
 	cost 42;

From f57b624281ff5d0797b8f44eeefa8d9019f18c4b Mon Sep 17 00:00:00 2001
From: Chun Lin Min <chunlin.min@microchip.com>
Date: Tue, 2 Jul 2024 13:54:36 -0700
Subject: [PATCH 181/499] fix indent

---
 techlibs/mchp/LSRAM.txt | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/techlibs/mchp/LSRAM.txt b/techlibs/mchp/LSRAM.txt
index 96dac535c57..9c22e4f302e 100644
--- a/techlibs/mchp/LSRAM.txt
+++ b/techlibs/mchp/LSRAM.txt
@@ -45,10 +45,10 @@ ram block $__LSRAM_TDP_ {
 	option "WIDTH_CONFIG" "REGULAR" {
 
 		# Data-Width| Address bits
-		# 1			| 14
-		# 2			| 13
-		# 4			| 12
-		# 8			| 11
+		# 1 		| 14
+		# 2 		| 13
+		# 4 		| 12
+		# 8 		| 11
 		# 16		| 10
 
 		# 14 address bits
@@ -60,7 +60,7 @@ ram block $__LSRAM_TDP_ {
 	option "WIDTH_CONFIG" "ALIGN" {
 		
 		# Data-Width| Address bits
-		# 5			| 12
+		# 5 		| 12
 		# 10		| 11
 		# 20		| 10
 
@@ -134,10 +134,10 @@ ram block $__LSRAM_SDP_ {
 	option "WIDTH_CONFIG" "REGULAR" {
 
 		# Data-Width| Address bits
-		# 1			| 14
-		# 2			| 13
-		# 4			| 12
-		# 8			| 11
+		# 1 		| 14
+		# 2 		| 13
+		# 4 		| 12
+		# 8 		| 11
 		# 16		| 10
 		# 32		| 9
 
@@ -152,7 +152,7 @@ ram block $__LSRAM_SDP_ {
 	option "WIDTH_CONFIG" "ALIGN" {
 		
 		# Data-Width| Address bits
-		# 5			| 12
+		# 5 		| 12
 		# 10		| 11
 		# 20		| 10
 		# 40		| 9

From e5bdc9b5c9cf4c25050eed2a3aba7f67e1271b5f Mon Sep 17 00:00:00 2001
From: Chun Lin Min <chunlin.min@microchip.com>
Date: Wed, 3 Jul 2024 07:20:29 -0700
Subject: [PATCH 182/499] remove DSP48 references

---
 passes/pmgen/mchp_dsp.pmg      | 3 +--
 passes/pmgen/mchp_dsp_CREG.pmg | 1 -
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/passes/pmgen/mchp_dsp.pmg b/passes/pmgen/mchp_dsp.pmg
index 2580d64b49b..41acf8c4e41 100644
--- a/passes/pmgen/mchp_dsp.pmg
+++ b/passes/pmgen/mchp_dsp.pmg
@@ -16,8 +16,7 @@
 
 
 // This file describes the main pattern matcher setup (of three total) that
-//   forms the `mchp_dsp` pass described in mchp_dsp.cc - version for
-//   DSP48A/DSP48A1 (Spartan 3A DSP, Spartan 6).
+//   forms the `mchp_dsp` pass described in mchp_dsp.cc 
 // At a high level, it works as follows:
 //   ( 1) Starting from a DSP cell. Capture DSP configurations as states
 //   ( 2) Match for pre-adder
diff --git a/passes/pmgen/mchp_dsp_CREG.pmg b/passes/pmgen/mchp_dsp_CREG.pmg
index 043a40617f8..11420107339 100644
--- a/passes/pmgen/mchp_dsp_CREG.pmg
+++ b/passes/pmgen/mchp_dsp_CREG.pmg
@@ -125,7 +125,6 @@ code
 		if (c.wire->get_bool_attribute(\keep))
 			reject;
 		// Abandon matches when 'Q' has a non-zero init attribute set
-		// (not supported by DSP48E1)
 		Const init = c.wire->attributes.at(\init, Const());
 		if (!init.empty())
 			for (auto b : init.extract(c.offset, c.width))

From 7770fa70e1662e92be8f793af28ffde1cb816d81 Mon Sep 17 00:00:00 2001
From: Chun Lin Min <chunlin.min@microchip.com>
Date: Thu, 4 Jul 2024 05:20:22 -0700
Subject: [PATCH 183/499] fix cells_sim.v

---
 techlibs/mchp/cells_sim.v | 20 +++++++++++++++-----
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/techlibs/mchp/cells_sim.v b/techlibs/mchp/cells_sim.v
index a89f17843be..a1f7ae6b8ba 100644
--- a/techlibs/mchp/cells_sim.v
+++ b/techlibs/mchp/cells_sim.v
@@ -166,15 +166,20 @@ module MCHP_SYNC_SET_DFF(
 	input En,
 	output Q);
 	parameter [0:0] INIT = 1'b0; // unused
+
+	reg q_ff;
+
 	always @(posedge CLK) begin
 		if (En == 1) begin
 			if (Set == 0)
-				Q <= 1;
+				q_ff <= 1;
 			else
-				Q <= D;
+				q_ff <= D;
 		end
 	end
 
+	assign Q = q_ff;
+
 	specify
 		$setup(D , posedge CLK &&& En && Set, 0); // neg setup not supported?
 		$setup(En, posedge CLK, 109);
@@ -192,15 +197,20 @@ module MCHP_SYNC_RESET_DFF(
 	input En,
 	output Q);
 	parameter [0:0] INIT = 1'b0; // unused
-	always @(posedge C) begin
+
+	reg q_ff;
+
+	always @(posedge CLK) begin
 		if (En == 1) begin
 			if (Reset == 0) 
-				Q <= 0;
+				q_ff <= 0;
 			else
-				Q <= D;
+				q_ff <= D;
 		end
 	end
 
+	assign Q = q_ff;
+
 	specify
 		$setup(D , posedge CLK &&& En && Reset, 0); // neg setup not supported?
 		$setup(En, posedge CLK, 109);

From 0bb7d1373f33a8db0f6ab8b6a2586102178e3750 Mon Sep 17 00:00:00 2001
From: C77874 <Damon.Ma@Microchip.com>
Date: Thu, 4 Jul 2024 08:53:41 -0700
Subject: [PATCH 184/499] changes made to filenames + references

---
 passes/pmgen/Makefile.inc                     |  16 +-
 .../pmgen/{mchp_dsp.cc => microchip_dsp.cc}   | 115 ++++++-------
 .../pmgen/{mchp_dsp.pmg => microchip_dsp.pmg} |   4 +-
 ...hp_dsp_CREG.pmg => microchip_dsp_CREG.pmg} |  10 +-
 ..._cascade.pmg => microchip_dsp_cascade.pmg} |   4 +-
 techlibs/{mchp => microchip}/LSRAM.txt        |   0
 techlibs/{mchp => microchip}/LSRAM_map.v      |   0
 techlibs/{mchp => microchip}/Makefile.inc     |  22 +--
 techlibs/{mchp => microchip}/arith_map.v      |   4 +-
 techlibs/{mchp => microchip}/brams_defs.vh    |   0
 techlibs/{mchp => microchip}/cells_map.v      |   8 +-
 techlibs/{mchp => microchip}/cells_sim.v      |   6 +-
 .../microchip_dffopt.cc}                      |  86 +++++-----
 .../polarfire_dsp_map.v}                      |   0
 .../synth_microchip.cc}                       | 152 +++++++++---------
 .../tests/Registers/Registers.v               |   0
 .../tests/Registers/Registers.ys              |   2 +-
 .../tests/carryout/carryout.v                 |   0
 .../tests/carryout/carryout.ys                |   2 +-
 .../tests/cascade/cascade.v                   |   0
 .../tests/cascade/cascade.ys                  |   2 +-
 .../tests/dff_opt/dff_opt.v                   |   0
 .../tests/dff_opt/dff_opt.ys                  |   2 +-
 .../tests/full_dsp/full_dsp.v                 |   0
 .../tests/full_dsp/full_dsp.ys                |   2 +-
 .../tests/large_mult/large_mult.v             |   0
 .../tests/large_mult/large_mult.ys            |   2 +-
 techlibs/{mchp => microchip}/tests/mac/mac.v  |   0
 techlibs/{mchp => microchip}/tests/mac/mac.ys |   2 +-
 .../tests/postAdd_mult/postAdd_mult.v         |   0
 .../tests/postAdd_mult/postAdd_mult.ys        |   2 +-
 .../tests/post_adder/post_adder.v             |   0
 .../tests/post_adder/post_adder.ys            |   2 +-
 .../tests/pre_adder_dsp/pre_adder_dsp.v       |   0
 .../tests/pre_adder_dsp/pre_adder_dsp.ys      |   2 +-
 .../tests/ram_SDP/ram_SDP.v                   |   0
 .../tests/ram_SDP/ram_SDP.ys                  |   2 +-
 .../tests/ram_TDP/ram_TDP.v                   |   0
 .../tests/ram_TDP/ram_TDP.ys                  |   2 +-
 .../{mchp => microchip}/tests/reduce/reduce.v |   0
 .../tests/reduce/reduce.ys                    |   2 +-
 .../{mchp => microchip}/tests/reg_c/reg_c.v   |   0
 .../{mchp => microchip}/tests/reg_c/reg_c.ys  |   2 +-
 .../tests/reg_test/reg_test.v                 |   0
 .../tests/reg_test/reg_test.ys                |   2 +-
 .../tests/signed_mult/signed_mult.v           |   0
 .../tests/signed_mult/signed_mult.ys          |   2 +-
 .../tests/simple_ram/simple_ram.v             |   0
 .../tests/simple_ram/simple_ram.ys            |   2 +-
 .../tests/unsigned_mult/unsigned_mult.v       |   0
 .../tests/unsigned_mult/unsigned_mult.ys      |   2 +-
 .../tests/uram_ar/uram_ar.v                   |   0
 .../tests/uram_ar/uram_ar.ys                  |   2 +-
 .../tests/uram_sr/uram_sr.v                   |   0
 .../tests/uram_sr/uram_sr.ys                  |   2 +-
 .../tests/widemux/widemux.v                   |   0
 .../tests/widemux/widemux.ys                  |   2 +-
 techlibs/{mchp => microchip}/uSRAM.txt        |   0
 techlibs/{mchp => microchip}/uSRAM_map.v      |   0
 59 files changed, 228 insertions(+), 241 deletions(-)
 rename passes/pmgen/{mchp_dsp.cc => microchip_dsp.cc} (80%)
 rename passes/pmgen/{mchp_dsp.pmg => microchip_dsp.pmg} (99%)
 rename passes/pmgen/{mchp_dsp_CREG.pmg => microchip_dsp_CREG.pmg} (93%)
 rename passes/pmgen/{mchp_dsp_cascade.pmg => microchip_dsp_cascade.pmg} (98%)
 rename techlibs/{mchp => microchip}/LSRAM.txt (100%)
 rename techlibs/{mchp => microchip}/LSRAM_map.v (100%)
 rename techlibs/{mchp => microchip}/Makefile.inc (50%)
 rename techlibs/{mchp => microchip}/arith_map.v (96%)
 rename techlibs/{mchp => microchip}/brams_defs.vh (100%)
 rename techlibs/{mchp => microchip}/cells_map.v (92%)
 rename techlibs/{mchp => microchip}/cells_sim.v (98%)
 rename techlibs/{mchp/mchp_dffopt.cc => microchip/microchip_dffopt.cc} (88%)
 rename techlibs/{mchp/pf_dsp_map.v => microchip/polarfire_dsp_map.v} (100%)
 rename techlibs/{mchp/synth_mchp.cc => microchip/synth_microchip.cc} (80%)
 rename techlibs/{mchp => microchip}/tests/Registers/Registers.v (100%)
 rename techlibs/{mchp => microchip}/tests/Registers/Registers.ys (93%)
 rename techlibs/{mchp => microchip}/tests/carryout/carryout.v (100%)
 rename techlibs/{mchp => microchip}/tests/carryout/carryout.ys (93%)
 rename techlibs/{mchp => microchip}/tests/cascade/cascade.v (100%)
 rename techlibs/{mchp => microchip}/tests/cascade/cascade.ys (93%)
 rename techlibs/{mchp => microchip}/tests/dff_opt/dff_opt.v (100%)
 rename techlibs/{mchp => microchip}/tests/dff_opt/dff_opt.ys (93%)
 rename techlibs/{mchp => microchip}/tests/full_dsp/full_dsp.v (100%)
 rename techlibs/{mchp => microchip}/tests/full_dsp/full_dsp.ys (93%)
 rename techlibs/{mchp => microchip}/tests/large_mult/large_mult.v (100%)
 rename techlibs/{mchp => microchip}/tests/large_mult/large_mult.ys (93%)
 rename techlibs/{mchp => microchip}/tests/mac/mac.v (100%)
 rename techlibs/{mchp => microchip}/tests/mac/mac.ys (94%)
 rename techlibs/{mchp => microchip}/tests/postAdd_mult/postAdd_mult.v (100%)
 rename techlibs/{mchp => microchip}/tests/postAdd_mult/postAdd_mult.ys (92%)
 rename techlibs/{mchp => microchip}/tests/post_adder/post_adder.v (100%)
 rename techlibs/{mchp => microchip}/tests/post_adder/post_adder.ys (93%)
 rename techlibs/{mchp => microchip}/tests/pre_adder_dsp/pre_adder_dsp.v (100%)
 rename techlibs/{mchp => microchip}/tests/pre_adder_dsp/pre_adder_dsp.ys (92%)
 rename techlibs/{mchp => microchip}/tests/ram_SDP/ram_SDP.v (100%)
 rename techlibs/{mchp => microchip}/tests/ram_SDP/ram_SDP.ys (93%)
 rename techlibs/{mchp => microchip}/tests/ram_TDP/ram_TDP.v (100%)
 rename techlibs/{mchp => microchip}/tests/ram_TDP/ram_TDP.ys (91%)
 rename techlibs/{mchp => microchip}/tests/reduce/reduce.v (100%)
 rename techlibs/{mchp => microchip}/tests/reduce/reduce.ys (93%)
 rename techlibs/{mchp => microchip}/tests/reg_c/reg_c.v (100%)
 rename techlibs/{mchp => microchip}/tests/reg_c/reg_c.ys (93%)
 rename techlibs/{mchp => microchip}/tests/reg_test/reg_test.v (100%)
 rename techlibs/{mchp => microchip}/tests/reg_test/reg_test.ys (93%)
 rename techlibs/{mchp => microchip}/tests/signed_mult/signed_mult.v (100%)
 rename techlibs/{mchp => microchip}/tests/signed_mult/signed_mult.ys (92%)
 rename techlibs/{mchp => microchip}/tests/simple_ram/simple_ram.v (100%)
 rename techlibs/{mchp => microchip}/tests/simple_ram/simple_ram.ys (93%)
 rename techlibs/{mchp => microchip}/tests/unsigned_mult/unsigned_mult.v (100%)
 rename techlibs/{mchp => microchip}/tests/unsigned_mult/unsigned_mult.ys (92%)
 rename techlibs/{mchp => microchip}/tests/uram_ar/uram_ar.v (100%)
 rename techlibs/{mchp => microchip}/tests/uram_ar/uram_ar.ys (93%)
 rename techlibs/{mchp => microchip}/tests/uram_sr/uram_sr.v (100%)
 rename techlibs/{mchp => microchip}/tests/uram_sr/uram_sr.ys (93%)
 rename techlibs/{mchp => microchip}/tests/widemux/widemux.v (100%)
 rename techlibs/{mchp => microchip}/tests/widemux/widemux.ys (93%)
 rename techlibs/{mchp => microchip}/uSRAM.txt (100%)
 rename techlibs/{mchp => microchip}/uSRAM_map.v (100%)

diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc
index 581ce241646..ef6bffb117d 100644
--- a/passes/pmgen/Makefile.inc
+++ b/passes/pmgen/Makefile.inc
@@ -37,14 +37,14 @@ $(eval $(call add_extra_objs,passes/pmgen/xilinx_dsp_cascade_pm.h))
 
 # --------------------------------------
 
-OBJS += passes/pmgen/mchp_dsp.o
-GENFILES += passes/pmgen/mchp_dsp_pm.h
-GENFILES += passes/pmgen/mchp_dsp_CREG_pm.h
-GENFILES += passes/pmgen/mchp_dsp_cascade_pm.h
-passes/pmgen/mchp_dsp.o: passes/pmgen/mchp_dsp_pm.h passes/pmgen/mchp_dsp_CREG_pm.h passes/pmgen/mchp_dsp_cascade_pm.h
-$(eval $(call add_extra_objs,passes/pmgen/mchp_dsp_pm.h))
-$(eval $(call add_extra_objs,passes/pmgen/mchp_dsp_CREG_pm.h))
-$(eval $(call add_extra_objs,passes/pmgen/mchp_dsp_cascade_pm.h))
+OBJS += passes/pmgen/microvhip.o
+GENFILES += passes/pmgen/microchip_dsp_pm.h
+GENFILES += passes/pmgen/microchip_dsp_CREG_pm.h
+GENFILES += passes/pmgen/microchip_dsp_cascade_pm.h
+passes/pmgen/microchip_dsp.o: passes/pmgen/microchip_dsp_pm.h passes/pmgen/microchip_dsp_CREG_pm.h passes/pmgen/microchip_dsp_cascade_pm.h
+$(eval $(call add_extra_objs,passes/pmgen/microchip_dsp_pm.h))
+$(eval $(call add_extra_objs,passes/pmgen/microchip_dsp_CREG_pm.h))
+$(eval $(call add_extra_objs,passes/pmgen/microchip_dsp_cascade_pm.h))
 
 # --------------------------------------
 
diff --git a/passes/pmgen/mchp_dsp.cc b/passes/pmgen/microchip_dsp.cc
similarity index 80%
rename from passes/pmgen/mchp_dsp.cc
rename to passes/pmgen/microchip_dsp.cc
index 8a1bf0b3c41..8207f4be360 100644
--- a/passes/pmgen/mchp_dsp.cc
+++ b/passes/pmgen/microchip_dsp.cc
@@ -16,25 +16,25 @@ ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
-#include "kernel/yosys.h"
 #include "kernel/sigtools.h"
+#include "kernel/yosys.h"
 #include <deque>
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-#include "passes/pmgen/mchp_dsp_pm.h"
-#include "passes/pmgen/mchp_dsp_CREG_pm.h"
-#include "passes/pmgen/mchp_dsp_cascade_pm.h"
+#include "passes/pmgen/microchip_dsp_CREG_pm.h"
+#include "passes/pmgen/microchip_dsp_cascade_pm.h"
+#include "passes/pmgen/microchip_dsp_pm.h"
 
-void mchp_dsp_pack(mchp_dsp_pm &pm)
+void microchip_dsp_pack(microchip_dsp_pm &pm)
 {
-	auto &st = pm.st_mchp_dsp_pack;
+	auto &st = pm.st_microchip_dsp_pack;
 
-	log("Analysing %s.%s for MCHP MACC_PA packing.\n", log_id(pm.module), log_id(st.dsp));
+	log("Analysing %s.%s for Microchip MACC_PA packing.\n", log_id(pm.module), log_id(st.dsp));
 
 	Cell *cell = st.dsp;
-	//pack pre-adder
+	// pack pre-adder
 	if (st.preAdderStatic) {
 		SigSpec &pasub = cell->connections_.at(ID(PASUB));
 		log("  static PASUB preadder %s (%s)\n", log_id(st.preAdderStatic), log_id(st.preAdderStatic->type));
@@ -42,8 +42,7 @@ void mchp_dsp_pack(mchp_dsp_pm &pm)
 		bool B_SIGNED = st.preAdderStatic->getParam(ID::A_SIGNED).as_bool();
 		st.sigB.extend_u0(18, B_SIGNED);
 		st.sigD.extend_u0(18, D_SIGNED);
-		if (st.moveBtoA)
-		{
+		if (st.moveBtoA) {
 			cell->setPort(ID::A, st.sigA); // if pre-adder feeds into A, original sigB will be moved to port A
 		}
 		cell->setPort(ID::B, st.sigB);
@@ -59,7 +58,7 @@ void mchp_dsp_pack(mchp_dsp_pm &pm)
 
 		pm.autoremove(st.preAdderStatic);
 	}
-	//pack post-adder
+	// pack post-adder
 	if (st.postAdderStatic) {
 		log("  postadder %s (%s)\n", log_id(st.postAdderStatic), log_id(st.postAdderStatic->type));
 		SigSpec &sub = cell->connections_.at(ID(SUB));
@@ -73,28 +72,25 @@ void mchp_dsp_pack(mchp_dsp_pm &pm)
 			log_assert(!"strange post-adder type");
 
 		if (st.useFeedBack) {
-			cell->setPort(ID(CDIN_FDBK_SEL), {State::S0, State::S1});	
+			cell->setPort(ID(CDIN_FDBK_SEL), {State::S0, State::S1});
 		} else {
 			st.sigC.extend_u0(48, st.postAdderStatic->getParam(ID::A_SIGNED).as_bool());
-			cell->setPort(ID::C, st.sigC);	
+			cell->setPort(ID::C, st.sigC);
 		}
 
-
 		pm.autoremove(st.postAdderStatic);
 	}
-	
+
 	// pack registers
-	if (st.clock != SigBit())
-	{
+	if (st.clock != SigBit()) {
 		cell->setPort(ID::CLK, st.clock);
 
 		// function to absorb a register
-		auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport, IdString bypass) {
-
+		auto f = [&pm, cell](SigSpec &A, Cell *ff, IdString ceport, IdString rstport, IdString bypass) {
 			// input/output ports
 			SigSpec D = ff->getPort(ID::D);
 			SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
-			
+
 			if (!A.empty())
 				A.replace(Q, D);
 			if (rstport != IdString()) {
@@ -118,21 +114,19 @@ void mchp_dsp_pack(mchp_dsp_pm &pm)
 				bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
 				// enables are all active high
 				cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
-			}
-			else {
+			} else {
 				// enables are all active high
-				cell->setPort(ceport, State::S1); 
+				cell->setPort(ceport, State::S1);
 			}
 
 			// bypass set to 0
-			cell->setPort(bypass, State::S0); 
-			
+			cell->setPort(bypass, State::S0);
 
 			for (auto c : Q.chunks()) {
 				auto it = c.wire->attributes.find(ID::init);
 				if (it == c.wire->attributes.end())
 					continue;
-				for (int i = c.offset; i < c.offset+c.width; i++) {
+				for (int i = c.offset; i < c.offset + c.width; i++) {
 					log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
 					it->second[i] = State::Sx;
 				}
@@ -164,7 +158,7 @@ void mchp_dsp_pack(mchp_dsp_pm &pm)
 			} else {
 				f(D, st.ffD, ID(D_EN), ID(D_SRST_N), ID(D_BYPASS));
 			}
-			
+
 			pm.add_siguser(D, cell);
 			cell->setPort(ID::D, D);
 		}
@@ -189,29 +183,27 @@ void mchp_dsp_pack(mchp_dsp_pm &pm)
 
 	SigSpec P = st.sigP;
 	if (GetSize(P) < 48)
-		P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
+		P.append(pm.module->addWire(NEW_ID, 48 - GetSize(P)));
 	cell->setPort(ID::P, P);
 
 	pm.blacklist(cell);
 }
 
 // For packing cascaded DSPs
-void mchp_dsp_packC(mchp_dsp_CREG_pm &pm)
+void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
 {
-	auto &st = pm.st_mchp_dsp_packC;
+	auto &st = pm.st_microchip_dsp_packC;
 
-	log_debug("Analysing %s.%s for MCHP DSP packing (REG_C).\n", log_id(pm.module), log_id(st.dsp));
+	log_debug("Analysing %s.%s for Microchip DSP packing (REG_C).\n", log_id(pm.module), log_id(st.dsp));
 	log_debug("ffC:        %s\n", log_id(st.ffC, "--"));
 
 	Cell *cell = st.dsp;
 
-	if (st.clock != SigBit())
-	{
+	if (st.clock != SigBit()) {
 		cell->setPort(ID::CLK, st.clock);
 
 		// same function as above, used for the last CREG we need to absorb
-		auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport, IdString bypass) {
-
+		auto f = [&pm, cell](SigSpec &A, Cell *ff, IdString ceport, IdString rstport, IdString bypass) {
 			// input/output ports
 			SigSpec D = ff->getPort(ID::D);
 			SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
@@ -240,18 +232,17 @@ void mchp_dsp_packC(mchp_dsp_CREG_pm &pm)
 				cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
 			} else {
 				// enables are all active high
-				cell->setPort(ceport, State::S1); 
+				cell->setPort(ceport, State::S1);
 			}
 
 			// bypass set to 0
-			cell->setPort(bypass, State::S0); 
-			
+			cell->setPort(bypass, State::S0);
 
 			for (auto c : Q.chunks()) {
 				auto it = c.wire->attributes.find(ID::init);
 				if (it == c.wire->attributes.end())
 					continue;
-				for (int i = c.offset; i < c.offset+c.width; i++) {
+				for (int i = c.offset; i < c.offset + c.width; i++) {
 					log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
 					it->second[i] = State::Sx;
 				}
@@ -260,7 +251,7 @@ void mchp_dsp_packC(mchp_dsp_CREG_pm &pm)
 
 		if (st.ffC) {
 			SigSpec C = cell->getPort(ID::C);
-			
+
 			if (st.ffC->type.in(ID($adff), ID($adffe))) {
 				f(C, st.ffC, ID(C_EN), ID(C_ARST_N), ID(C_BYPASS));
 			} else {
@@ -280,17 +271,17 @@ void mchp_dsp_packC(mchp_dsp_CREG_pm &pm)
 	pm.blacklist(cell);
 }
 
-struct MchpDspPass : public Pass {
-	MchpDspPass() : Pass("mchp_dsp", "MCHP: pack resources into DSPs") { }
+struct MicrochipDspPass : public Pass {
+	MicrochipDspPass() : Pass("microchip_dsp", "MICROCHIP: pack resources into DSPs") {}
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    mchp_dsp [options] [selection]\n");
+		log("    microchip_dsp [options] [selection]\n");
 		log("\n");
 		log("Pack input registers 'A', 'B', 'C', and 'D' (with optional enable/reset),\n");
 		log("output register 'P' (with optional enable/reset), pre-adder and/or post-adder into\n");
-		log("MCHP DSP resources.\n");
+		log("Microchip DSP resources.\n");
 		log("\n");
 		log("Multiply-accumulate operations using the post-adder with feedback on the 'C'\n");
 		log("input will be folded into the DSP. In this scenario only, the 'C' input can be\n");
@@ -303,24 +294,23 @@ struct MchpDspPass : public Pass {
 		log("implement wide multipliers). Cascade chains are limited to a mazimum length \n");
 		log("of 24 cells, corresponding to PolarFire (pf) devices.\n");
 		log("\n");
-		log("This pass is a no-op if the scratchpad variable 'mchp_dsp.multonly' is set\n");
+		log("This pass is a no-op if the scratchpad variable 'microchip_dsp.multonly' is set\n");
 		log("to 1.\n");
 		log("\n");
 		log("\n");
-		log("    -family {pf}\n");
+		log("    -family {polarfire}\n");
 		log("        select the family to target\n");
-		log("        default: pf\n");
+		log("        default: polarfire\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		log_header(design, "Executing MCHP_DSP pass (pack resources into DSPs).\n");
+		log_header(design, "Executing MICROCHIP_DSP pass (pack resources into DSPs).\n");
 
-		std::string family = "pf";
+		std::string family = "polarfire";
 		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++)
-		{
-			if ((args[argidx] == "-family") && argidx+1 < args.size()) {
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if ((args[argidx] == "-family") && argidx + 1 < args.size()) {
 				family = args[++argidx];
 				continue;
 			}
@@ -330,7 +320,7 @@ struct MchpDspPass : public Pass {
 
 		for (auto module : design->selected_modules()) {
 
-			if (design->scratchpad_get_bool("mchp_dsp.multonly"))
+			if (design->scratchpad_get_bool("microchip_dsp.multonly"))
 				continue;
 
 			{
@@ -338,13 +328,13 @@ struct MchpDspPass : public Pass {
 				//   the "PolarFire FPGA Macro Library Guide"
 
 				// Main pattern matching step to capture a DSP cell.
-				//   Match for pre-adder, post-adder, as well as 
+				//   Match for pre-adder, post-adder, as well as
 				//   registers 'A', 'B', 'D', and 'P'. Additionally,
 				//   check for an accumulator pattern based on whether
 				//   a post-adder and PREG are both present AND
-				//   if PREG feeds into this post-adder.  
-				mchp_dsp_pm pm(module, module->selected_cells());
-				pm.run_mchp_dsp_pack(mchp_dsp_pack);
+				//   if PREG feeds into this post-adder.
+				microchip_dsp_pm pm(module, module->selected_cells());
+				pm.run_microchip_dsp_pack(microchip_dsp_pack);
 			}
 
 			// Separating out CREG packing is necessary since there
@@ -356,18 +346,17 @@ struct MchpDspPass : public Pass {
 			//   PREG of an upstream DSP that had not been visited
 			//   yet
 			{
-				mchp_dsp_CREG_pm pm(module, module->selected_cells());
-				pm.run_mchp_dsp_packC(mchp_dsp_packC);
+				microchip_dsp_CREG_pm pm(module, module->selected_cells());
+				pm.run_microchip_dsp_packC(microchip_dsp_packC);
 			}
 
 			// Lastly, identify and utilise PCOUT -> PCIN chains
 			{
-				mchp_dsp_cascade_pm pm(module, module->selected_cells());
-				pm.run_mchp_dsp_cascade();
+				microchip_dsp_cascade_pm pm(module, module->selected_cells());
+				pm.run_microchip_dsp_cascade();
 			}
-			
 		}
 	}
-} MchpDspPass;
+} MicrochipDspPass;
 
 PRIVATE_NAMESPACE_END
diff --git a/passes/pmgen/mchp_dsp.pmg b/passes/pmgen/microchip_dsp.pmg
similarity index 99%
rename from passes/pmgen/mchp_dsp.pmg
rename to passes/pmgen/microchip_dsp.pmg
index 41acf8c4e41..1c22bb317d7 100644
--- a/passes/pmgen/mchp_dsp.pmg
+++ b/passes/pmgen/microchip_dsp.pmg
@@ -16,7 +16,7 @@
 
 
 // This file describes the main pattern matcher setup (of three total) that
-//   forms the `mchp_dsp` pass described in mchp_dsp.cc 
+//   forms the `microchip_dsp` pass described in microchip_dsp.cc 
 // At a high level, it works as follows:
 //   ( 1) Starting from a DSP cell. Capture DSP configurations as states
 //   ( 2) Match for pre-adder
@@ -31,7 +31,7 @@
 //            |MULT|------ | adder |   +----+
 //            +----+       \-------/
 
-pattern mchp_dsp_pack
+pattern microchip_dsp_pack
 
 state <SigBit> clock
 state <SigSpec> sigA sigB sigC sigD sigP
diff --git a/passes/pmgen/mchp_dsp_CREG.pmg b/passes/pmgen/microchip_dsp_CREG.pmg
similarity index 93%
rename from passes/pmgen/mchp_dsp_CREG.pmg
rename to passes/pmgen/microchip_dsp_CREG.pmg
index 11420107339..baa5869620d 100644
--- a/passes/pmgen/mchp_dsp_CREG.pmg
+++ b/passes/pmgen/microchip_dsp_CREG.pmg
@@ -16,7 +16,7 @@
 
 
 // This file describes the second of three pattern matcher setups that
-//   forms the `mchp_dsp` pass described in mchp_dsp.cc
+//   forms the `microchip_dsp` pass described in microchip_dsp.cc
 // At a high level, it works as follows:
 //   (1) Starting from a DSP cell that (a) doesn't have a CREG already,
 //       and (b) uses the 'C' port
@@ -24,21 +24,21 @@
 //       (attached to at most two $mux cells that implement clock-enable or
 //        reset functionality, using a subpattern discussed below)
 // Notes:
-//   - Running CREG packing after mchp_dsp_pack is necessary since there is no
+//   - Running CREG packing after microchip_dsp_pack is necessary since there is no
 //     guarantee that the cell ordering corresponds to the "expected" case (i.e.
 //     the order in which they appear in the source) thus the possiblity existed
 //     where a register got packed as a CREG into a downstream DSP, while it should
 //     have otherwise been a PREG of an upstream DSP that had not been visited.
 //     yet.
-//   - The reason this is separated out from the mchp_dsp.pmg file is
+//   - The reason this is separated out from the microchip_dsp.pmg file is
 //     for efficiency --- each *.pmg file creates a class of the same basename,
 //     which when constructed, creates a custom database tailored to the
 //     pattern(s) contained within. Since the pattern in this file must be
-//     executed after the pattern contained in mchp_dsp.pmg, it is necessary
+//     executed after the pattern contained in microchip_dsp.pmg, it is necessary
 //     to reconstruct this database. Separating the two patterns into
 //     independent files causes two smaller, more specific, databases.
 
-pattern mchp_dsp_packC
+pattern microchip_dsp_packC
 
 udata <std::function<SigSpec(const SigSpec&)>> unextend
 state <SigBit> clock
diff --git a/passes/pmgen/mchp_dsp_cascade.pmg b/passes/pmgen/microchip_dsp_cascade.pmg
similarity index 98%
rename from passes/pmgen/mchp_dsp_cascade.pmg
rename to passes/pmgen/microchip_dsp_cascade.pmg
index 4ea9df75802..d7ea5911e09 100644
--- a/passes/pmgen/mchp_dsp_cascade.pmg
+++ b/passes/pmgen/microchip_dsp_cascade.pmg
@@ -16,7 +16,7 @@
 
 
 // This file describes the third of three pattern matcher setups that
-//   forms the `mchp_dsp` pass described in mchp_dsp.cc
+//   forms the `microchip_dsp` pass described in microchip_dsp.cc
 // At a high level, it works as follows:
 //   (1) Starting from a DSP cell that 
 //         (a) CDIN_FDBK_SEL is set to default "00"
@@ -32,7 +32,7 @@
 //       height of a DSP column) with each DSP in each chunk being rewritten
 //       to use [ABP]COUT -> [ABP]CIN cascading as appropriate
 
-pattern mchp_dsp_cascade
+pattern microchip_dsp_cascade
 
 udata <std::function<SigSpec(const SigSpec&)>> unextend
 udata <vector<std::tuple<Cell*,int>>> chain longest_chain
diff --git a/techlibs/mchp/LSRAM.txt b/techlibs/microchip/LSRAM.txt
similarity index 100%
rename from techlibs/mchp/LSRAM.txt
rename to techlibs/microchip/LSRAM.txt
diff --git a/techlibs/mchp/LSRAM_map.v b/techlibs/microchip/LSRAM_map.v
similarity index 100%
rename from techlibs/mchp/LSRAM_map.v
rename to techlibs/microchip/LSRAM_map.v
diff --git a/techlibs/mchp/Makefile.inc b/techlibs/microchip/Makefile.inc
similarity index 50%
rename from techlibs/mchp/Makefile.inc
rename to techlibs/microchip/Makefile.inc
index a716caa9f16..f6f34ccd304 100644
--- a/techlibs/mchp/Makefile.inc
+++ b/techlibs/microchip/Makefile.inc
@@ -16,16 +16,16 @@
 
 
 
-OBJS += techlibs/mchp/synth_mchp.o
-OBJS += techlibs/mchp/mchp_dffopt.o
+OBJS += techlibs/microchip/synth_microchip.o
+OBJS += techlibs/microchip/microchip_dffopt.o
 
-$(eval $(call add_share_file,share/mchp,techlibs/mchp/arith_map.v))
-$(eval $(call add_share_file,share/mchp,techlibs/mchp/cells_map.v))
-$(eval $(call add_share_file,share/mchp,techlibs/mchp/cells_sim.v))
-$(eval $(call add_share_file,share/mchp,techlibs/mchp/pf_dsp_map.v))
+$(eval $(call add_share_file,share/microchip,techlibs/microchip/arith_map.v))
+$(eval $(call add_share_file,share/microchip,techlibs/microchip/cells_map.v))
+$(eval $(call add_share_file,share/microchip,techlibs/microchip/cells_sim.v))
+$(eval $(call add_share_file,share/microchip,techlibs/microchip/pf_dsp_map.v))
 
-$(eval $(call add_share_file,share/mchp,techlibs/mchp/brams_defs.vh))
-$(eval $(call add_share_file,share/mchp,techlibs/mchp/LSRAM_map.v))
-$(eval $(call add_share_file,share/mchp,techlibs/mchp/LSRAM.txt))
-$(eval $(call add_share_file,share/mchp,techlibs/mchp/uSRAM_map.v))
-$(eval $(call add_share_file,share/mchp,techlibs/mchp/uSRAM.txt))
+$(eval $(call add_share_file,share/microchip,techlibs/microchip/brams_defs.vh))
+$(eval $(call add_share_file,share/microchip,techlibs/microchip/LSRAM_map.v))
+$(eval $(call add_share_file,share/microchip,techlibs/microchip/LSRAM.txt))
+$(eval $(call add_share_file,share/microchip,techlibs/microchip/uSRAM_map.v))
+$(eval $(call add_share_file,share/microchip,techlibs/microchip/uSRAM.txt))
diff --git a/techlibs/mchp/arith_map.v b/techlibs/microchip/arith_map.v
similarity index 96%
rename from techlibs/mchp/arith_map.v
rename to techlibs/microchip/arith_map.v
index d6c289c9224..c21f34f4427 100644
--- a/techlibs/mchp/arith_map.v
+++ b/techlibs/microchip/arith_map.v
@@ -21,7 +21,7 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
 
 (* techmap_celltype = "$_MUX4_" *)
-module \$__mchp_MUX4_ (A, B, C, D, S, T, Y);
+module \$__microchip_MUX4_ (A, B, C, D, S, T, Y);
 	input A, B, C, D, S, T;
 	output Y;
 	MX4 _TECHMAP_REPLACE_.MUX4(.D3(D), .D2(C), .D1(B), .D0(A), .S1(T), .S0(S), .Y(Y));
@@ -30,7 +30,7 @@ endmodule
 
 
 (* techmap_celltype = "$reduce_xor" *)
-module \$__mchp_XOR8_ (A, Y);
+module \$__microchip_XOR8_ (A, Y);
 	parameter A_SIGNED = 0;
 	parameter A_WIDTH = 0;
 	parameter Y_WIDTH = 0;
diff --git a/techlibs/mchp/brams_defs.vh b/techlibs/microchip/brams_defs.vh
similarity index 100%
rename from techlibs/mchp/brams_defs.vh
rename to techlibs/microchip/brams_defs.vh
diff --git a/techlibs/mchp/cells_map.v b/techlibs/microchip/cells_map.v
similarity index 92%
rename from techlibs/mchp/cells_map.v
rename to techlibs/microchip/cells_map.v
index 9194b023b51..6425d594ff8 100644
--- a/techlibs/mchp/cells_map.v
+++ b/techlibs/microchip/cells_map.v
@@ -28,11 +28,11 @@ endmodule
 // for sync set/reset registers, we can pass them into ABC9. So we need to follow the simplification idiom
 // and map to intermediate cell types
 module \$_SDFFCE_PN0P_ (input D, C, R, E, output Q);
-	MCHP_SYNC_RESET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Reset(R), .En(E), .Q(Q));
+	MICROCHIP_SYNC_RESET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Reset(R), .En(E), .Q(Q));
 endmodule
 
 module \$_SDFFCE_PN1P_ (input D, C, R, E, output Q);
-	MCHP_SYNC_SET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Set(R), .En(E), .Q(Q));
+	MICROCHIP_SYNC_SET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Set(R), .En(E), .Q(Q));
 endmodule
 
 
@@ -52,7 +52,7 @@ endmodule
 
 // map intermediate flops to SLE
 `ifdef FINAL_MAP
-module MCHP_SYNC_SET_DFF(
+module MICROCHIP_SYNC_SET_DFF(
 	input D,
 	input CLK,
 	input Set,
@@ -61,7 +61,7 @@ module MCHP_SYNC_SET_DFF(
 	SLE _TECHMAP_REPLACE_ (.D(D), .CLK(CLK), .EN(En), .ALn(1'b1), .ADn(1'b0), .SLn(Set), .SD(1'b1), .LAT(1'b0), .Q(Q));
 endmodule
 
-module MCHP_SYNC_RESET_DFF(
+module MICROCHIP_SYNC_RESET_DFF(
 	input D,
 	input CLK,
 	input Reset,
diff --git a/techlibs/mchp/cells_sim.v b/techlibs/microchip/cells_sim.v
similarity index 98%
rename from techlibs/mchp/cells_sim.v
rename to techlibs/microchip/cells_sim.v
index a89f17843be..47586a8a2d7 100644
--- a/techlibs/mchp/cells_sim.v
+++ b/techlibs/microchip/cells_sim.v
@@ -155,11 +155,11 @@ endmodule
 
 // sequential elements
 
-// MCHP_SYNC_SET_DFF and MCHP_SYNC_RESET_DFF are intermediate cell types to implement the simplification idiom for abc9 flow 
+// MICROCHIP_SYNC_SET_DFF and MICROCHIP_SYNC_RESET_DFF are intermediate cell types to implement the simplification idiom for abc9 flow 
 //	see: https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/abc_flow.html
 
 (* abc9_flop, lib_whitebox *)
-module MCHP_SYNC_SET_DFF(
+module MICROCHIP_SYNC_SET_DFF(
 	input D,
 	input CLK,
 	input Set,
@@ -185,7 +185,7 @@ module MCHP_SYNC_SET_DFF(
 endmodule
 
 (* abc9_flop, lib_whitebox *)
-module MCHP_SYNC_RESET_DFF(
+module MICROCHIP_SYNC_RESET_DFF(
 	input D,
 	input CLK,
 	input Reset,
diff --git a/techlibs/mchp/mchp_dffopt.cc b/techlibs/microchip/microchip_dffopt.cc
similarity index 88%
rename from techlibs/mchp/mchp_dffopt.cc
rename to techlibs/microchip/microchip_dffopt.cc
index 474e9275d16..4193eb469e7 100644
--- a/techlibs/mchp/mchp_dffopt.cc
+++ b/techlibs/microchip/microchip_dffopt.cc
@@ -16,8 +16,8 @@ ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
-#include "kernel/yosys.h"
 #include "kernel/sigtools.h"
+#include "kernel/yosys.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
@@ -25,7 +25,8 @@ PRIVATE_NAMESPACE_BEGIN
 typedef std::pair<Const, std::vector<SigBit>> LutData;
 
 // Compute a LUT implementing (select ^ select_inv) ? alt_data : data.  Returns true if successful.
-bool merge_lut(LutData &result, const LutData &data, const LutData select, bool select_inv, SigBit alt_data, int max_lut_size) {
+bool merge_lut(LutData &result, const LutData &data, const LutData select, bool select_inv, SigBit alt_data, int max_lut_size)
+{
 	// First, gather input signals -- insert new signals at the beginning
 	// of the vector, so they don't disturb the likely-critical D LUT input
 	// timings.
@@ -97,13 +98,13 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool
 	return true;
 }
 
-struct MchpDffOptPass : public Pass {
-	MchpDffOptPass() : Pass("mchp_dffopt", "MCHP: optimize FF control signal usage") { }
+struct MicrochipDffOptPass : public Pass {
+	MicrochipDffOptPass() : Pass("microchip_dffopt", "MICROCHIP: optimize FF control signal usage") {}
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    mchp_dffopt [options] [selection]\n");
+		log("    microchip_dffopt [options] [selection]\n");
 		log("\n");
 		log("Converts hardware clock enable and set/reset signals on FFs to emulation\n");
 		log("using LUTs, if doing so would improve area. Operates on post-techmap LUT, DFF\n");
@@ -112,15 +113,14 @@ struct MchpDffOptPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		log_header(design, "Executing MCHP_DFFOPT pass (optimize FF control signal usage).\n");
+		log_header(design, "Executing MICROCHIP_DFFOPT pass (optimize FF control signal usage).\n");
 
 		size_t argidx;
 		int max_lut_size = 4;
-		
+
 		extra_args(args, argidx, design);
 
-		for (auto module : design->selected_modules())
-		{
+		for (auto module : design->selected_modules()) {
 			log("Optimizing FFs in %s.\n", log_id(module));
 
 			SigMap sigmap(module);
@@ -128,8 +128,7 @@ struct MchpDffOptPass : public Pass {
 			dict<SigBit, int> bit_uses;
 
 			// Gather LUTs.
-			for (auto cell : module->selected_cells())
-			{
+			for (auto cell : module->selected_cells()) {
 				for (auto port : cell->connections())
 					for (auto bit : port.second)
 						bit_uses[sigmap(bit)]++;
@@ -153,8 +152,8 @@ struct MchpDffOptPass : public Pass {
 					if (cell->type == ID(CFG3))
 						goto lut_sigin_done;
 					sigin.push_back(sigmap(cell->getPort(ID(D))));
-					
-lut_sigin_done:
+
+				lut_sigin_done:
 					bit_to_lut[sigout] = make_pair(LutData(init, sigin), cell);
 				}
 			}
@@ -164,8 +163,7 @@ struct MchpDffOptPass : public Pass {
 						bit_uses[sigmap(SigBit(wire, i))]++;
 
 			// Iterate through FFs.
-			for (auto cell : module->selected_cells())
-			{
+			for (auto cell : module->selected_cells()) {
 
 				if (!cell->type.in(ID(SLE))) // not a SLE
 					continue;
@@ -174,13 +172,12 @@ struct MchpDffOptPass : public Pass {
 				if (cell->get_bool_attribute(ID::keep)) // keep attribute
 					continue;
 				if (!cell->getPort(ID(ALn)).is_fully_ones()) // async FF
-					continue; 
+					continue;
 
-					
 				const bool hasSyncLoad = cell->getPort(ID(SLn)).is_wire();
 				const bool has_s = hasSyncLoad && cell->getPort(ID(SD)).is_fully_ones();
 				const bool has_r = hasSyncLoad && cell->getPort(ID(SD)).is_fully_zero();
-				
+
 				// SLE cannot have both synchronous set and reset implemented at the same time
 				log_assert(!(has_s && has_r));
 
@@ -196,7 +193,6 @@ struct MchpDffOptPass : public Pass {
 				LutData lut_d = it_D->second.first;
 				Cell *cell_d = it_D->second.second;
 
-
 				LutData lut_d_post_ce;
 				LutData lut_d_post_s;
 				LutData lut_d_post_r;
@@ -216,7 +212,8 @@ struct MchpDffOptPass : public Pass {
 					if (!merge_lut(lut_d_post_ce, lut_d, lut_ce, true, sig_Q, max_lut_size))
 						continue;
 
-					// If this gets rid of a CE LUT, it's worth it.  If not, it still may be worth it, if we can remove set/reset as well.
+					// If this gets rid of a CE LUT, it's worth it.  If not, it still may be worth it, if we can remove set/reset
+					// as well.
 					if (it_CE != bit_to_lut.end())
 						worthy_post_ce = true;
 				} else if (sig_CE.data != State::S1) {
@@ -231,7 +228,7 @@ struct MchpDffOptPass : public Pass {
 				if (has_s) {
 					SigBit sig_S = sigmap(cell->getPort(ID(SLn)));
 					LutData lut_s = LutData(Const(2, 2), {sig_S}); // INIT = 10
-					bool inv_s = true; // active low
+					bool inv_s = true;			       // active low
 					auto it_S = bit_to_lut.find(sig_S);
 					if (it_S != bit_to_lut.end())
 						lut_s = it_S->second.first;
@@ -253,7 +250,7 @@ struct MchpDffOptPass : public Pass {
 				if (has_r) {
 					SigBit sig_R = sigmap(cell->getPort(ID(SLn)));
 					LutData lut_r = LutData(Const(2, 2), {sig_R}); // INIT = 10
-					bool inv_r = true; // active low
+					bool inv_r = true;			       // active low
 					auto it_R = bit_to_lut.find(sig_R);
 					if (it_R != bit_to_lut.end())
 						lut_r = it_R->second.first;
@@ -270,7 +267,7 @@ struct MchpDffOptPass : public Pass {
 					}
 				}
 
-unmap:
+			unmap:
 
 				// SLE cannot have both synchronous set and reset implemented at the same time
 				log_assert(!(worthy_post_r && worthy_post_s));
@@ -288,10 +285,14 @@ struct MchpDffOptPass : public Pass {
 				}
 
 				std::string ports;
-				if (worthy_post_r) ports += " + R";
-				if (worthy_post_s) ports += " + S";
-				if (worthy_post_ce) ports += " + CE";
-				log("  Merging D%s LUTs for %s/%s (%d -> %d)\n", ports.c_str(), log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
+				if (worthy_post_r)
+					ports += " + R";
+				if (worthy_post_s)
+					ports += " + S";
+				if (worthy_post_ce)
+					ports += " + CE";
+				log("  Merging D%s LUTs for %s/%s (%d -> %d)\n", ports.c_str(), log_id(cell), log_id(sig_Q.wire),
+				    GetSize(lut_d.second), GetSize(final_lut.second));
 
 				// Okay, we're doing it.  Unmap ports.
 				if ((has_s && worthy_post_s) || worthy_post_r) {
@@ -304,20 +305,20 @@ struct MchpDffOptPass : public Pass {
 				// Create the new LUT.
 				Cell *lut_cell = nullptr;
 				switch (GetSize(final_lut.second)) {
-					case 1:
-						lut_cell = module->addCell(NEW_ID, ID(CFG1));
-						break;
-					case 2:
-						lut_cell = module->addCell(NEW_ID, ID(CFG2));
-						break;
-					case 3:
-						lut_cell = module->addCell(NEW_ID, ID(CFG3));
-						break;
-					case 4:
-						lut_cell = module->addCell(NEW_ID, ID(CFG4));
-						break;
-					default:
-						log_assert(!"unknown lut size");
+				case 1:
+					lut_cell = module->addCell(NEW_ID, ID(CFG1));
+					break;
+				case 2:
+					lut_cell = module->addCell(NEW_ID, ID(CFG2));
+					break;
+				case 3:
+					lut_cell = module->addCell(NEW_ID, ID(CFG3));
+					break;
+				case 4:
+					lut_cell = module->addCell(NEW_ID, ID(CFG4));
+					break;
+				default:
+					log_assert(!"unknown lut size");
 				}
 				lut_cell->attributes = cell_d->attributes;
 				Wire *lut_out = module->addWire(NEW_ID);
@@ -334,7 +335,6 @@ struct MchpDffOptPass : public Pass {
 			}
 		}
 	}
-} MchpDffOptPass;
+} MicrochipDffOptPass;
 
 PRIVATE_NAMESPACE_END
-
diff --git a/techlibs/mchp/pf_dsp_map.v b/techlibs/microchip/polarfire_dsp_map.v
similarity index 100%
rename from techlibs/mchp/pf_dsp_map.v
rename to techlibs/microchip/polarfire_dsp_map.v
diff --git a/techlibs/mchp/synth_mchp.cc b/techlibs/microchip/synth_microchip.cc
similarity index 80%
rename from techlibs/mchp/synth_mchp.cc
rename to techlibs/microchip/synth_microchip.cc
index e5fe7d48445..b3764ed7caf 100644
--- a/techlibs/mchp/synth_mchp.cc
+++ b/techlibs/microchip/synth_microchip.cc
@@ -16,23 +16,22 @@ ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
-#include "kernel/register.h"
 #include "kernel/celltypes.h"
-#include "kernel/rtlil.h"
 #include "kernel/log.h"
+#include "kernel/register.h"
+#include "kernel/rtlil.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-struct SynthMchpPass : public ScriptPass
-{
-	SynthMchpPass() : ScriptPass("synth_mchp", "synthesis for Microchip FPGAs") { }
+struct SynthMicrochipPass : public ScriptPass {
+	SynthMicrochipPass() : ScriptPass("synth_microchip", "synthesis for Microchip FPGAs") {}
 
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    synth_mchp [options]\n");
+		log("    synth_microchip [options]\n");
 		log("\n");
 		log("This command runs synthesis for Microchip FPGAs. Operating on\n");
 		log("partly selected designs is not supported (you must submit a fully-selected \n");
@@ -54,7 +53,7 @@ struct SynthMchpPass : public ScriptPass
 		log("\n");
 		log("    -blif <file>\n");
 		log("        Write the design to the specified BLIF file. Writing of an output file\n");
-		log("        is omitted if this parameter is not specified.\n");		
+		log("        is omitted if this parameter is not specified.\n");
 		log("\n");
 		log("    -nobram\n");
 		log("        Do not use block RAM cells in output netlist\n");
@@ -137,30 +136,29 @@ struct SynthMchpPass : public ScriptPass
 		clear_flags();
 
 		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++)
-		{
-			if (args[argidx] == "-top" && argidx+1 < args.size()) {
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-top" && argidx + 1 < args.size()) {
 				top_opt = "-top " + args[++argidx];
 				continue;
 			}
-			if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
+			if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx + 1 < args.size()) {
 				family = args[++argidx];
 				continue;
 			}
-			if (args[argidx] == "-edif" && argidx+1 < args.size()) {
+			if (args[argidx] == "-edif" && argidx + 1 < args.size()) {
 				edif_file = args[++argidx];
 				continue;
 			}
-			if (args[argidx] == "-blif" && argidx+1 < args.size()) {
+			if (args[argidx] == "-blif" && argidx + 1 < args.size()) {
 				blif_file = args[++argidx];
 				continue;
 			}
-			if (args[argidx] == "-run" && argidx+1 < args.size()) {
-				size_t pos = args[argidx+1].find(':');
+			if (args[argidx] == "-run" && argidx + 1 < args.size()) {
+				size_t pos = args[argidx + 1].find(':');
 				if (pos == std::string::npos)
 					break;
 				run_from = args[++argidx].substr(0, pos);
-				run_to = args[argidx].substr(pos+1);
+				run_to = args[argidx].substr(pos + 1);
 				continue;
 			}
 			if (args[argidx] == "-flatten") {
@@ -231,7 +229,7 @@ struct SynthMchpPass : public ScriptPass
 			lut_size = 4;
 		} else {
 			log_cmd_error("Invalid Microchip -family setting: '%s'.\n", family.c_str());
-        }
+		}
 
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
@@ -239,8 +237,7 @@ struct SynthMchpPass : public ScriptPass
 		if (abc9 && retime)
 			log_cmd_error("-retime option not currently compatible with -abc9!\n");
 
-
-		log_header(design, "Executing SYNTH_MCHP pass.\n");
+		log_header(design, "Executing SYNTH_MICROCHIP pass.\n");
 		log_push();
 
 		run_script(design, run_from, run_to);
@@ -256,7 +253,7 @@ struct SynthMchpPass : public ScriptPass
 
 		if (check_label("begin")) {
 			std::string read_args;
-			read_args += " -lib -specify +/mchp/cells_sim.v";
+			read_args += " -lib -specify +/microchip/cells_sim.v";
 			run("read_verilog" + read_args);
 
 			run(stringf("hierarchy -check %s", top_opt.c_str()));
@@ -286,29 +283,29 @@ struct SynthMchpPass : public ScriptPass
 
 		if (check_label("map_dsp", "(skip if '-nodsp')")) {
 			if (!nodsp || help_mode) {
-				run("memory_dff"); // mchp_dsp will merge registers, reserve memory port registers first
+				run("memory_dff"); // microchip_dsp will merge registers, reserve memory port registers first
 				if (help_mode)
-					run("techmap -map +/mul2dsp.v -map +/mchp/{family}_dsp_map.v {options}");
+					run("techmap -map +/mul2dsp.v -map +/microchip/{family}_dsp_map.v {options}");
 				else if (family == "pf") // Microchip - map multipliers to DSP
-					run("techmap -map +/mul2dsp.v -map +/mchp/pf_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
-						"-D DSP_A_MAXWIDTH_PARTIAL=18 "	// Partial multipliers are intentionally
-										// limited to 18x18 in order to take
-										// advantage of the (PCOUT >> 17) -> PCIN
-										// dedicated cascade chain capability
-						"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
-						"-D DSP_Y_MINWIDTH=9 "
-						"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18");
-				
+					run("techmap -map +/mul2dsp.v -map +/microchip/pf_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
+					    "-D DSP_A_MAXWIDTH_PARTIAL=18 " // Partial multipliers are intentionally
+									    // limited to 18x18 in order to take
+									    // advantage of the (PCOUT >> 17) -> PCIN
+									    // dedicated cascade chain capability
+					    "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
+					    "-D DSP_Y_MINWIDTH=9 "
+					    "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18");
+
 				run("select a:mul2dsp");
 				run("setattr -unset mul2dsp");
 				run("opt_expr -fine");
 				run("wreduce");
 				run("select -clear");
 				if (help_mode)
-					run("mchp_dsp -family <family>");
+					run("microchip_dsp -family <family>");
 				else if (family == "pf") // Microchip - absorb cells into DSP
-					run("mchp_dsp -family " + family);
-				
+					run("microchip_dsp -family " + family);
+
 				run("chtype -set $mul t:$__soft_mul");
 			}
 		}
@@ -324,41 +321,44 @@ struct SynthMchpPass : public ScriptPass
 
 		if (check_label("map_memory")) {
 			std::string params = "";
-			std::string LSRAM_map = "+/mchp/LSRAM_map.v";
-			std::string uSRAM_map = "+/mchp/uSRAM_map.v";
-			if (debug_memory) run("write_verilog -noexpr memory_map_pre.vm");
+			std::string LSRAM_map = "+/microchip/LSRAM_map.v";
+			std::string uSRAM_map = "+/microchip/uSRAM_map.v";
+			if (debug_memory)
+				run("write_verilog -noexpr memory_map_pre.vm");
 			if (help_mode) {
 				params = " [...]";
 			} else {
 
 				if (family == "pf") {
 					// cost of a single bit for memory lowered to soft logic
-					params += " -logic-cost-rom 0.015625"; 
+					params += " -logic-cost-rom 0.015625";
 
-					params += " -lib +/mchp/LSRAM.txt";
-					params += " -lib +/mchp/uSRAM.txt";
-					LSRAM_map = "+/mchp/LSRAM_map.v";
-					uSRAM_map = "+/mchp/uSRAM_map.v";
+					params += " -lib +/microchip/LSRAM.txt";
+					params += " -lib +/microchip/uSRAM.txt";
+					LSRAM_map = "+/microchip/LSRAM_map.v";
+					uSRAM_map = "+/microchip/uSRAM_map.v";
 				}
-				if (nobram) params += " -no-auto-block";
+				if (nobram)
+					params += " -no-auto-block";
 			}
 
 			// transform memories into intermediate cells
 			// Cost based transformation. The cost is assigned by us for each cell.
 			run("memory_libmap" + params);
-			if (debug_memory) run("write_verilog -noexpr memory_map_libmap.vm");
+			if (debug_memory)
+				run("write_verilog -noexpr memory_map_libmap.vm");
 
 			// map intermediate cells to actual RAM macros
 			// NOTE: order doesnt matter here
 			run("techmap -map " + LSRAM_map);
 			run("techmap -map " + uSRAM_map);
-			if (debug_memory)  run("write_verilog -noexpr memory_map_final.vm");
+			if (debug_memory)
+				run("write_verilog -noexpr memory_map_final.vm");
 		}
 
 		if (check_label("map_ffram")) {
 			run("opt -fast -full");
 
-
 			// blast unmapped RAM to flops or LUTs
 			run("memory_map");
 		}
@@ -366,7 +366,8 @@ struct SynthMchpPass : public ScriptPass
 		if (check_label("fine")) {
 			run("opt -full");
 
-			if (debug_carry) run("write_verilog -noexpr ARI1_cells.vm");
+			if (debug_carry)
+				run("write_verilog -noexpr ARI1_cells.vm");
 
 			if (!nocarry) {
 				// converts $mux -> $_MUX_ to allow muxcover to work
@@ -376,21 +377,24 @@ struct SynthMchpPass : public ScriptPass
 				run("simplemap t:$xor"); // only mapping reduce_xor
 
 				// mapping based on Yosys internal gates
-				if (debug_carry) run("write_verilog -noexpr ARI1_pre.vm");
+				if (debug_carry)
+					run("write_verilog -noexpr ARI1_pre.vm");
 
 				// collapse $_AND_/$_OR_/$_XOR_ chains into reduction cells
 				run("extract_reduce");
 
-				if (debug_carry) run("write_verilog -noexpr ARI1_extract_reduce.vm");
-				
+				if (debug_carry)
+					run("write_verilog -noexpr ARI1_extract_reduce.vm");
+
 				// pack mux trees into $_MUX4_
 				run("muxcover -nodecode -mux4=220");
 
-				if (debug_carry) run("write_verilog -noexpr ARI1_muxcover.vm");
-				
-				run("techmap -map +/mchp/arith_map.v");
-				if (debug_carry) run("write_verilog -noexpr ARI1_post.vm");
-				
+				if (debug_carry)
+					run("write_verilog -noexpr ARI1_muxcover.vm");
+
+				run("techmap -map +/microchip/arith_map.v");
+				if (debug_carry)
+					run("write_verilog -noexpr ARI1_post.vm");
 			}
 
 			// convert all remaining cells to gates
@@ -403,10 +407,11 @@ struct SynthMchpPass : public ScriptPass
 			// Needs to be done before logic optimization, so that inverters (inserted
 			// 			here because of negative-polarity output enable) are handled.
 			if (help_mode || !noiopad) {
-				run("iopadmap -bits -inpad INBUF Y:PAD -outpad OUTBUF D:PAD -toutpad TRIBUFF E:D:PAD -tinoutpad BIBUF E:Y:D:PAD", "(unless -noiobs)");
+				run("iopadmap -bits -inpad INBUF Y:PAD -outpad OUTBUF D:PAD -toutpad TRIBUFF E:D:PAD -tinoutpad BIBUF E:Y:D:PAD",
+				    "(unless -noiobs)");
 			}
-				
-			std::string techmap_args = "-map +/techmap.v -map +/mchp/cells_map.v";
+
+			std::string techmap_args = "-map +/techmap.v -map +/microchip/cells_map.v";
 			run("techmap " + techmap_args);
 			run("clean");
 		}
@@ -447,14 +452,12 @@ struct SynthMchpPass : public ScriptPass
 			// $_DLATCH_[NP][NP][01]_			(D-latch + reset to 0/1)
 			// $_DLATCHSR_[NP][NP][NP]_			(D-latch + set + reset)
 
-			
 			if (family == "pf") {
 				std::string params = "";
-				
 
 				// D-flop with async reset and enable
 				// posedge CLK, active low reset to 1 or 0, active high EN
-				params += " -cell $_DFFE_PN?P_ 01"; 
+				params += " -cell $_DFFE_PN?P_ 01";
 
 				// D-flop with sync reset and enable, enable takes priority over reset
 				// posedge CLK, active low reset to 1 or 0, active high EN
@@ -466,12 +469,11 @@ struct SynthMchpPass : public ScriptPass
 
 				run("dfflegalize" + params, "(Converts FFs to supported types)");
 			}
-				
 
 			if (abc9 || help_mode) {
 				if (dff || help_mode)
 					run("zinit -all w:* t:$_SDFFCE_*", "('-dff' only)");
-				run("techmap -D NO_LUT -map +/mchp/cells_map.v", "('-abc9' only)");
+				run("techmap -D NO_LUT -map +/microchip/cells_map.v", "('-abc9' only)");
 			}
 		}
 
@@ -482,10 +484,10 @@ struct SynthMchpPass : public ScriptPass
 			if (help_mode)
 				run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')");
 			else if (abc9) {
-                
+
 				std::string abc9_opts;
 				// for the if command in abc to specify wire delay between adjects LUTs (default = 0)
-				// NOTE: should not have 0 wire delay between LUTs, 
+				// NOTE: should not have 0 wire delay between LUTs,
 				//		 otherwise abc might use LUT2+LUT3 instead of single LUT4
 				abc9_opts += " -W 300";
 				if (nowidelut)
@@ -493,8 +495,7 @@ struct SynthMchpPass : public ScriptPass
 				if (dff)
 					abc9_opts += " -dff";
 				run("abc9" + abc9_opts);
-			}
-			else {
+			} else {
 				std::string abc_opts = " -lut " + lut_size_s;
 				if (dff)
 					abc_opts += " -dff";
@@ -505,21 +506,18 @@ struct SynthMchpPass : public ScriptPass
 			run("clean");
 
 			if (help_mode || !abc9)
-				run("techmap -D NO_LUT -map +/mchp/cells_map.v", "(only if not '-abc9')");
-			std::string techmap_args = "-map +/mchp/cells_map.v -D FINAL_MAP";
+				run("techmap -D NO_LUT -map +/microchip/cells_map.v", "(only if not '-abc9')");
+			std::string techmap_args = "-map +/microchip/cells_map.v -D FINAL_MAP";
 			techmap_args += " -D LUT_WIDTH=" + lut_size_s;
 			run("techmap " + techmap_args);
-            
-			if (help_mode || lut_size == 4)
-				run("mchp_dffopt");
 
-            
+			if (help_mode || lut_size == 4)
+				run("microchip_dffopt");
 		}
 
-			run("clkbufmap -buf CLKINT Y:A -inpad CLKBUF Y:PAD");
-
-			run("clean -purge");
+		run("clkbufmap -buf CLKINT Y:A -inpad CLKBUF Y:PAD");
 
+		run("clean -purge");
 
 		if (check_label("check")) {
 			run("hierarchy -check");
@@ -538,6 +536,6 @@ struct SynthMchpPass : public ScriptPass
 				run(stringf("write_blif %s", blif_file.c_str()));
 		}
 	}
-} SynthMchpPass;
+} SynthMicrochipPass;
 
 PRIVATE_NAMESPACE_END
diff --git a/techlibs/mchp/tests/Registers/Registers.v b/techlibs/microchip/tests/Registers/Registers.v
similarity index 100%
rename from techlibs/mchp/tests/Registers/Registers.v
rename to techlibs/microchip/tests/Registers/Registers.v
diff --git a/techlibs/mchp/tests/Registers/Registers.ys b/techlibs/microchip/tests/Registers/Registers.ys
similarity index 93%
rename from techlibs/mchp/tests/Registers/Registers.ys
rename to techlibs/microchip/tests/Registers/Registers.ys
index c83376fdd30..7b1a1ed77a1 100644
--- a/techlibs/mchp/tests/Registers/Registers.ys
+++ b/techlibs/microchip/tests/Registers/Registers.ys
@@ -17,7 +17,7 @@
 # read verilog files
 read_verilog Registers.v
 
-synth_mchp -top Registers -abc9 -family pf -noiopad
+synth_microchip -top Registers -abc9 -family polarfire -noiopad
 
 # write final outputfile
 write_verilog -noexpr Registers.vm
diff --git a/techlibs/mchp/tests/carryout/carryout.v b/techlibs/microchip/tests/carryout/carryout.v
similarity index 100%
rename from techlibs/mchp/tests/carryout/carryout.v
rename to techlibs/microchip/tests/carryout/carryout.v
diff --git a/techlibs/mchp/tests/carryout/carryout.ys b/techlibs/microchip/tests/carryout/carryout.ys
similarity index 93%
rename from techlibs/mchp/tests/carryout/carryout.ys
rename to techlibs/microchip/tests/carryout/carryout.ys
index 1697bc8932c..65d4d6709f2 100644
--- a/techlibs/mchp/tests/carryout/carryout.ys
+++ b/techlibs/microchip/tests/carryout/carryout.ys
@@ -16,6 +16,6 @@
 
 read_verilog carryout.v
 
-synth_mchp -top carryout -abc9 -family pf -noiopad
+synth_microchip -top carryout -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr carryout.vm
diff --git a/techlibs/mchp/tests/cascade/cascade.v b/techlibs/microchip/tests/cascade/cascade.v
similarity index 100%
rename from techlibs/mchp/tests/cascade/cascade.v
rename to techlibs/microchip/tests/cascade/cascade.v
diff --git a/techlibs/mchp/tests/cascade/cascade.ys b/techlibs/microchip/tests/cascade/cascade.ys
similarity index 93%
rename from techlibs/mchp/tests/cascade/cascade.ys
rename to techlibs/microchip/tests/cascade/cascade.ys
index f7017913d18..a817c094553 100644
--- a/techlibs/mchp/tests/cascade/cascade.ys
+++ b/techlibs/microchip/tests/cascade/cascade.ys
@@ -16,6 +16,6 @@
 
 read_verilog cascade.v
 
-synth_mchp -top cascade -abc9 -family pf -noiopad
+synth_microchip -top cascade -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr cascade.vm
diff --git a/techlibs/mchp/tests/dff_opt/dff_opt.v b/techlibs/microchip/tests/dff_opt/dff_opt.v
similarity index 100%
rename from techlibs/mchp/tests/dff_opt/dff_opt.v
rename to techlibs/microchip/tests/dff_opt/dff_opt.v
diff --git a/techlibs/mchp/tests/dff_opt/dff_opt.ys b/techlibs/microchip/tests/dff_opt/dff_opt.ys
similarity index 93%
rename from techlibs/mchp/tests/dff_opt/dff_opt.ys
rename to techlibs/microchip/tests/dff_opt/dff_opt.ys
index 746444c3422..776081639f9 100644
--- a/techlibs/mchp/tests/dff_opt/dff_opt.ys
+++ b/techlibs/microchip/tests/dff_opt/dff_opt.ys
@@ -15,7 +15,7 @@
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 read_verilog dff_opt.v 
 
-synth_mchp -top dff_opt -abc9 -family pf -noiopad
+synth_microchip -top dff_opt -abc9 -family polarfire -noiopad
 
 # write final outputfile
 write_verilog -noexpr dff_opt.vm
diff --git a/techlibs/mchp/tests/full_dsp/full_dsp.v b/techlibs/microchip/tests/full_dsp/full_dsp.v
similarity index 100%
rename from techlibs/mchp/tests/full_dsp/full_dsp.v
rename to techlibs/microchip/tests/full_dsp/full_dsp.v
diff --git a/techlibs/mchp/tests/full_dsp/full_dsp.ys b/techlibs/microchip/tests/full_dsp/full_dsp.ys
similarity index 93%
rename from techlibs/mchp/tests/full_dsp/full_dsp.ys
rename to techlibs/microchip/tests/full_dsp/full_dsp.ys
index 01bb95f54d9..67c66fa1989 100644
--- a/techlibs/mchp/tests/full_dsp/full_dsp.ys
+++ b/techlibs/microchip/tests/full_dsp/full_dsp.ys
@@ -16,6 +16,6 @@
 
 read_verilog full_dsp.v
 
-synth_mchp -top full_dsp -abc9 -family pf -noiopad
+synth_microchip -top full_dsp -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr full_dsp.vm
diff --git a/techlibs/mchp/tests/large_mult/large_mult.v b/techlibs/microchip/tests/large_mult/large_mult.v
similarity index 100%
rename from techlibs/mchp/tests/large_mult/large_mult.v
rename to techlibs/microchip/tests/large_mult/large_mult.v
diff --git a/techlibs/mchp/tests/large_mult/large_mult.ys b/techlibs/microchip/tests/large_mult/large_mult.ys
similarity index 93%
rename from techlibs/mchp/tests/large_mult/large_mult.ys
rename to techlibs/microchip/tests/large_mult/large_mult.ys
index 3779a26d6d4..ea3c80a0ddd 100644
--- a/techlibs/mchp/tests/large_mult/large_mult.ys
+++ b/techlibs/microchip/tests/large_mult/large_mult.ys
@@ -16,6 +16,6 @@
 
 read_verilog large_mult.v
 
-synth_mchp -top large_mult -abc9 -family pf -noiopad
+synth_microchip -top large_mult -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr large_mult.vm
diff --git a/techlibs/mchp/tests/mac/mac.v b/techlibs/microchip/tests/mac/mac.v
similarity index 100%
rename from techlibs/mchp/tests/mac/mac.v
rename to techlibs/microchip/tests/mac/mac.v
diff --git a/techlibs/mchp/tests/mac/mac.ys b/techlibs/microchip/tests/mac/mac.ys
similarity index 94%
rename from techlibs/mchp/tests/mac/mac.ys
rename to techlibs/microchip/tests/mac/mac.ys
index 59504436803..cb22ad49df1 100644
--- a/techlibs/mchp/tests/mac/mac.ys
+++ b/techlibs/microchip/tests/mac/mac.ys
@@ -18,7 +18,7 @@
 read_verilog mac.v
 
 # run the synth flow, specifies top module and additional parameters
-synth_mchp -top mac -abc9 -family pf -noiopad
+synticrochip -top mac -abc9 -family polarfire -noiopad
 
 # write final outputfile
 write_verilog -noexpr mac.vm
diff --git a/techlibs/mchp/tests/postAdd_mult/postAdd_mult.v b/techlibs/microchip/tests/postAdd_mult/postAdd_mult.v
similarity index 100%
rename from techlibs/mchp/tests/postAdd_mult/postAdd_mult.v
rename to techlibs/microchip/tests/postAdd_mult/postAdd_mult.v
diff --git a/techlibs/mchp/tests/postAdd_mult/postAdd_mult.ys b/techlibs/microchip/tests/postAdd_mult/postAdd_mult.ys
similarity index 92%
rename from techlibs/mchp/tests/postAdd_mult/postAdd_mult.ys
rename to techlibs/microchip/tests/postAdd_mult/postAdd_mult.ys
index 3a3586c8859..54754bb7f5a 100644
--- a/techlibs/mchp/tests/postAdd_mult/postAdd_mult.ys
+++ b/techlibs/microchip/tests/postAdd_mult/postAdd_mult.ys
@@ -16,6 +16,6 @@
 
 read_verilog postAdd_mult.v
 
-synth_mchp -top postAdd_mult -abc9 -family pf -noiopad
+synth_microchip -top postAdd_mult -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr postAdd_mult.vm
diff --git a/techlibs/mchp/tests/post_adder/post_adder.v b/techlibs/microchip/tests/post_adder/post_adder.v
similarity index 100%
rename from techlibs/mchp/tests/post_adder/post_adder.v
rename to techlibs/microchip/tests/post_adder/post_adder.v
diff --git a/techlibs/mchp/tests/post_adder/post_adder.ys b/techlibs/microchip/tests/post_adder/post_adder.ys
similarity index 93%
rename from techlibs/mchp/tests/post_adder/post_adder.ys
rename to techlibs/microchip/tests/post_adder/post_adder.ys
index 0fa613f6728..29f0e73f033 100644
--- a/techlibs/mchp/tests/post_adder/post_adder.ys
+++ b/techlibs/microchip/tests/post_adder/post_adder.ys
@@ -16,6 +16,6 @@
 
 read_verilog post_adder.v
 
-synth_mchp -top post_adder -abc9 -family pf
+synth_microchip -top post_adder -abc9 -family polarfire
 
 write_verilog -noexpr post_adder.vm
diff --git a/techlibs/mchp/tests/pre_adder_dsp/pre_adder_dsp.v b/techlibs/microchip/tests/pre_adder_dsp/pre_adder_dsp.v
similarity index 100%
rename from techlibs/mchp/tests/pre_adder_dsp/pre_adder_dsp.v
rename to techlibs/microchip/tests/pre_adder_dsp/pre_adder_dsp.v
diff --git a/techlibs/mchp/tests/pre_adder_dsp/pre_adder_dsp.ys b/techlibs/microchip/tests/pre_adder_dsp/pre_adder_dsp.ys
similarity index 92%
rename from techlibs/mchp/tests/pre_adder_dsp/pre_adder_dsp.ys
rename to techlibs/microchip/tests/pre_adder_dsp/pre_adder_dsp.ys
index 82bc56bd17c..1510f4ed61b 100644
--- a/techlibs/mchp/tests/pre_adder_dsp/pre_adder_dsp.ys
+++ b/techlibs/microchip/tests/pre_adder_dsp/pre_adder_dsp.ys
@@ -16,6 +16,6 @@
 
 read_verilog pre_adder_dsp.v
 
-synth_mchp -top pre_adder_dsp -abc9 -family pf -noiopad
+synth_microchip -top pre_adder_dsp -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr pre_adder_dsp.vm
diff --git a/techlibs/mchp/tests/ram_SDP/ram_SDP.v b/techlibs/microchip/tests/ram_SDP/ram_SDP.v
similarity index 100%
rename from techlibs/mchp/tests/ram_SDP/ram_SDP.v
rename to techlibs/microchip/tests/ram_SDP/ram_SDP.v
diff --git a/techlibs/mchp/tests/ram_SDP/ram_SDP.ys b/techlibs/microchip/tests/ram_SDP/ram_SDP.ys
similarity index 93%
rename from techlibs/mchp/tests/ram_SDP/ram_SDP.ys
rename to techlibs/microchip/tests/ram_SDP/ram_SDP.ys
index 4ab12999021..0060c882db1 100644
--- a/techlibs/mchp/tests/ram_SDP/ram_SDP.ys
+++ b/techlibs/microchip/tests/ram_SDP/ram_SDP.ys
@@ -16,6 +16,6 @@
 
 read_verilog ram_SDP.v
 
-synth_mchp -top ram_SDP -abc9 -family pf -noiopad
+synth_microchip -top ram_SDP -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr ram_SDP.vm
diff --git a/techlibs/mchp/tests/ram_TDP/ram_TDP.v b/techlibs/microchip/tests/ram_TDP/ram_TDP.v
similarity index 100%
rename from techlibs/mchp/tests/ram_TDP/ram_TDP.v
rename to techlibs/microchip/tests/ram_TDP/ram_TDP.v
diff --git a/techlibs/mchp/tests/ram_TDP/ram_TDP.ys b/techlibs/microchip/tests/ram_TDP/ram_TDP.ys
similarity index 91%
rename from techlibs/mchp/tests/ram_TDP/ram_TDP.ys
rename to techlibs/microchip/tests/ram_TDP/ram_TDP.ys
index ea98facd59c..9fe5fdbe76a 100644
--- a/techlibs/mchp/tests/ram_TDP/ram_TDP.ys
+++ b/techlibs/microchip/tests/ram_TDP/ram_TDP.ys
@@ -16,6 +16,6 @@
 
 read_verilog ram_TDP.v
 
-synth_mchp -top ram_TDP -abc9 -family pf -noiopad -debug_memory
+synth_microchip -top ram_TDP -abc9 -family polarfire -noiopad -debug_memory
 
 write_verilog -noexpr ram_TDP.vm
diff --git a/techlibs/mchp/tests/reduce/reduce.v b/techlibs/microchip/tests/reduce/reduce.v
similarity index 100%
rename from techlibs/mchp/tests/reduce/reduce.v
rename to techlibs/microchip/tests/reduce/reduce.v
diff --git a/techlibs/mchp/tests/reduce/reduce.ys b/techlibs/microchip/tests/reduce/reduce.ys
similarity index 93%
rename from techlibs/mchp/tests/reduce/reduce.ys
rename to techlibs/microchip/tests/reduce/reduce.ys
index 693f1cdeb6e..3341f51a23f 100644
--- a/techlibs/mchp/tests/reduce/reduce.ys
+++ b/techlibs/microchip/tests/reduce/reduce.ys
@@ -16,6 +16,6 @@
 
 read_verilog reduce.v
 
-synth_mchp -top reduce -abc9 -family pf -noiopad
+synth_microchip -top reduce -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr reduce.vm
diff --git a/techlibs/mchp/tests/reg_c/reg_c.v b/techlibs/microchip/tests/reg_c/reg_c.v
similarity index 100%
rename from techlibs/mchp/tests/reg_c/reg_c.v
rename to techlibs/microchip/tests/reg_c/reg_c.v
diff --git a/techlibs/mchp/tests/reg_c/reg_c.ys b/techlibs/microchip/tests/reg_c/reg_c.ys
similarity index 93%
rename from techlibs/mchp/tests/reg_c/reg_c.ys
rename to techlibs/microchip/tests/reg_c/reg_c.ys
index 37c4df18dde..0265be56f32 100644
--- a/techlibs/mchp/tests/reg_c/reg_c.ys
+++ b/techlibs/microchip/tests/reg_c/reg_c.ys
@@ -16,6 +16,6 @@
 
 read_verilog reg_c.v
 
-synth_mchp -top reg_c -abc9 -family pf -noiopad
+synth_microchip -top reg_c -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr reg_c.vm
diff --git a/techlibs/mchp/tests/reg_test/reg_test.v b/techlibs/microchip/tests/reg_test/reg_test.v
similarity index 100%
rename from techlibs/mchp/tests/reg_test/reg_test.v
rename to techlibs/microchip/tests/reg_test/reg_test.v
diff --git a/techlibs/mchp/tests/reg_test/reg_test.ys b/techlibs/microchip/tests/reg_test/reg_test.ys
similarity index 93%
rename from techlibs/mchp/tests/reg_test/reg_test.ys
rename to techlibs/microchip/tests/reg_test/reg_test.ys
index 2c1fb87d72c..7bd44a99e7b 100644
--- a/techlibs/mchp/tests/reg_test/reg_test.ys
+++ b/techlibs/microchip/tests/reg_test/reg_test.ys
@@ -16,6 +16,6 @@
 
 read_verilog reg_test.v
 
-synth_mchp -top reg_test -abc9 -family pf -noiopad
+synth_microchip -top reg_test -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr reg_test.vm
diff --git a/techlibs/mchp/tests/signed_mult/signed_mult.v b/techlibs/microchip/tests/signed_mult/signed_mult.v
similarity index 100%
rename from techlibs/mchp/tests/signed_mult/signed_mult.v
rename to techlibs/microchip/tests/signed_mult/signed_mult.v
diff --git a/techlibs/mchp/tests/signed_mult/signed_mult.ys b/techlibs/microchip/tests/signed_mult/signed_mult.ys
similarity index 92%
rename from techlibs/mchp/tests/signed_mult/signed_mult.ys
rename to techlibs/microchip/tests/signed_mult/signed_mult.ys
index bba8cbfe20c..93588a5dd83 100755
--- a/techlibs/mchp/tests/signed_mult/signed_mult.ys
+++ b/techlibs/microchip/tests/signed_mult/signed_mult.ys
@@ -16,6 +16,6 @@
 
 read_verilog signed_mult.v
 
-synth_mchp -top signed_mult -abc9 -family pf -noiopad
+synth_microchip -top signed_mult -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr signed_mult.vm
diff --git a/techlibs/mchp/tests/simple_ram/simple_ram.v b/techlibs/microchip/tests/simple_ram/simple_ram.v
similarity index 100%
rename from techlibs/mchp/tests/simple_ram/simple_ram.v
rename to techlibs/microchip/tests/simple_ram/simple_ram.v
diff --git a/techlibs/mchp/tests/simple_ram/simple_ram.ys b/techlibs/microchip/tests/simple_ram/simple_ram.ys
similarity index 93%
rename from techlibs/mchp/tests/simple_ram/simple_ram.ys
rename to techlibs/microchip/tests/simple_ram/simple_ram.ys
index a315a2bfb80..85975d25093 100644
--- a/techlibs/mchp/tests/simple_ram/simple_ram.ys
+++ b/techlibs/microchip/tests/simple_ram/simple_ram.ys
@@ -16,6 +16,6 @@
 
 read_verilog simple_ram.v
 
-synth_mchp -top simple_ram -abc9 -family pf -noiopad
+synth_microchip -top simple_ram -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr simple_ram.vm
diff --git a/techlibs/mchp/tests/unsigned_mult/unsigned_mult.v b/techlibs/microchip/tests/unsigned_mult/unsigned_mult.v
similarity index 100%
rename from techlibs/mchp/tests/unsigned_mult/unsigned_mult.v
rename to techlibs/microchip/tests/unsigned_mult/unsigned_mult.v
diff --git a/techlibs/mchp/tests/unsigned_mult/unsigned_mult.ys b/techlibs/microchip/tests/unsigned_mult/unsigned_mult.ys
similarity index 92%
rename from techlibs/mchp/tests/unsigned_mult/unsigned_mult.ys
rename to techlibs/microchip/tests/unsigned_mult/unsigned_mult.ys
index 05118e2658e..e588912eaba 100644
--- a/techlibs/mchp/tests/unsigned_mult/unsigned_mult.ys
+++ b/techlibs/microchip/tests/unsigned_mult/unsigned_mult.ys
@@ -16,6 +16,6 @@
 
 read_verilog unsigned_mult.v
 
-synth_mchp -top unsigned_mult -abc9 -family pf -noiopad
+synth_microchip -top unsigned_mult -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr unsigned_mult.vm
diff --git a/techlibs/mchp/tests/uram_ar/uram_ar.v b/techlibs/microchip/tests/uram_ar/uram_ar.v
similarity index 100%
rename from techlibs/mchp/tests/uram_ar/uram_ar.v
rename to techlibs/microchip/tests/uram_ar/uram_ar.v
diff --git a/techlibs/mchp/tests/uram_ar/uram_ar.ys b/techlibs/microchip/tests/uram_ar/uram_ar.ys
similarity index 93%
rename from techlibs/mchp/tests/uram_ar/uram_ar.ys
rename to techlibs/microchip/tests/uram_ar/uram_ar.ys
index 3650cb249c7..cbaea647ff4 100644
--- a/techlibs/mchp/tests/uram_ar/uram_ar.ys
+++ b/techlibs/microchip/tests/uram_ar/uram_ar.ys
@@ -16,6 +16,6 @@
 
 read_verilog uram_ar.v
 
-synth_mchp -top uram_ar -abc9 -family pf -noiopad
+synth_microchip -top uram_ar -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr uram_ar.vm
diff --git a/techlibs/mchp/tests/uram_sr/uram_sr.v b/techlibs/microchip/tests/uram_sr/uram_sr.v
similarity index 100%
rename from techlibs/mchp/tests/uram_sr/uram_sr.v
rename to techlibs/microchip/tests/uram_sr/uram_sr.v
diff --git a/techlibs/mchp/tests/uram_sr/uram_sr.ys b/techlibs/microchip/tests/uram_sr/uram_sr.ys
similarity index 93%
rename from techlibs/mchp/tests/uram_sr/uram_sr.ys
rename to techlibs/microchip/tests/uram_sr/uram_sr.ys
index a4c79398a41..7708fb39ff7 100644
--- a/techlibs/mchp/tests/uram_sr/uram_sr.ys
+++ b/techlibs/microchip/tests/uram_sr/uram_sr.ys
@@ -16,6 +16,6 @@
 
 read_verilog uram_sr.v
 
-synth_mchp -top uram_sr -abc9 -family pf -noiopad
+synth_microchip -top uram_sr -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr uram_sr.vm
diff --git a/techlibs/mchp/tests/widemux/widemux.v b/techlibs/microchip/tests/widemux/widemux.v
similarity index 100%
rename from techlibs/mchp/tests/widemux/widemux.v
rename to techlibs/microchip/tests/widemux/widemux.v
diff --git a/techlibs/mchp/tests/widemux/widemux.ys b/techlibs/microchip/tests/widemux/widemux.ys
similarity index 93%
rename from techlibs/mchp/tests/widemux/widemux.ys
rename to techlibs/microchip/tests/widemux/widemux.ys
index f8aeaaa5805..8ef3a92308f 100644
--- a/techlibs/mchp/tests/widemux/widemux.ys
+++ b/techlibs/microchip/tests/widemux/widemux.ys
@@ -16,6 +16,6 @@
 
 read_verilog widemux.v
 
-synth_mchp -top widemux -abc9 -family pf -noiopad
+synth_microchip -top widemux -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr widemux.vm
diff --git a/techlibs/mchp/uSRAM.txt b/techlibs/microchip/uSRAM.txt
similarity index 100%
rename from techlibs/mchp/uSRAM.txt
rename to techlibs/microchip/uSRAM.txt
diff --git a/techlibs/mchp/uSRAM_map.v b/techlibs/microchip/uSRAM_map.v
similarity index 100%
rename from techlibs/mchp/uSRAM_map.v
rename to techlibs/microchip/uSRAM_map.v

From d0cd01adfe11fd69985785d5888d4a1181c3715c Mon Sep 17 00:00:00 2001
From: C77874 <Damon.Ma@Microchip.com>
Date: Thu, 4 Jul 2024 09:33:58 -0700
Subject: [PATCH 185/499] fixed typos, build with makefile succeeds

---
 passes/pmgen/Makefile.inc       | 2 +-
 techlibs/microchip/Makefile.inc | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc
index ef6bffb117d..84d9ebaf121 100644
--- a/passes/pmgen/Makefile.inc
+++ b/passes/pmgen/Makefile.inc
@@ -37,7 +37,7 @@ $(eval $(call add_extra_objs,passes/pmgen/xilinx_dsp_cascade_pm.h))
 
 # --------------------------------------
 
-OBJS += passes/pmgen/microvhip.o
+OBJS += passes/pmgen/microchip_dsp.o
 GENFILES += passes/pmgen/microchip_dsp_pm.h
 GENFILES += passes/pmgen/microchip_dsp_CREG_pm.h
 GENFILES += passes/pmgen/microchip_dsp_cascade_pm.h
diff --git a/techlibs/microchip/Makefile.inc b/techlibs/microchip/Makefile.inc
index f6f34ccd304..b1905e2cfee 100644
--- a/techlibs/microchip/Makefile.inc
+++ b/techlibs/microchip/Makefile.inc
@@ -22,7 +22,7 @@ OBJS += techlibs/microchip/microchip_dffopt.o
 $(eval $(call add_share_file,share/microchip,techlibs/microchip/arith_map.v))
 $(eval $(call add_share_file,share/microchip,techlibs/microchip/cells_map.v))
 $(eval $(call add_share_file,share/microchip,techlibs/microchip/cells_sim.v))
-$(eval $(call add_share_file,share/microchip,techlibs/microchip/pf_dsp_map.v))
+$(eval $(call add_share_file,share/microchip,techlibs/microchip/polarfire_dsp_map.v))
 
 $(eval $(call add_share_file,share/microchip,techlibs/microchip/brams_defs.vh))
 $(eval $(call add_share_file,share/microchip,techlibs/microchip/LSRAM_map.v))

From c385421c17e7eadf4cace029142db47a53621d72 Mon Sep 17 00:00:00 2001
From: C77874 <Damon.Ma@Microchip.com>
Date: Thu, 4 Jul 2024 09:45:04 -0700
Subject: [PATCH 186/499] rename options

---
 techlibs/microchip/synth_microchip.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/microchip/synth_microchip.cc b/techlibs/microchip/synth_microchip.cc
index b3764ed7caf..f593a4bd05f 100644
--- a/techlibs/microchip/synth_microchip.cc
+++ b/techlibs/microchip/synth_microchip.cc
@@ -225,7 +225,7 @@ struct SynthMicrochipPass : public ScriptPass {
 		}
 		extra_args(args, argidx, design);
 
-		if (family == "pf") {
+		if (family == "polarfire") {
 			lut_size = 4;
 		} else {
 			log_cmd_error("Invalid Microchip -family setting: '%s'.\n", family.c_str());

From 6b80e02d62047b6bd2d5bb5ae46050ca67fd0ed7 Mon Sep 17 00:00:00 2001
From: C77874 <Damon.Ma@Microchip.com>
Date: Thu, 4 Jul 2024 10:25:15 -0700
Subject: [PATCH 187/499] missed a few pf instances

---
 techlibs/microchip/synth_microchip.cc | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/techlibs/microchip/synth_microchip.cc b/techlibs/microchip/synth_microchip.cc
index f593a4bd05f..9b7adae1bfe 100644
--- a/techlibs/microchip/synth_microchip.cc
+++ b/techlibs/microchip/synth_microchip.cc
@@ -45,7 +45,7 @@ struct SynthMicrochipPass : public ScriptPass {
 		log("        Run synthesis for the specified Microchip architecture. \n");
 		log("        Generate the synthesis netlist for the specified family.\n");
 		log("        supported values:\n");
-		log("        - pf: PolarFire\n");
+		log("        - polarfire: PolarFire\n");
 		log("\n");
 		log("    -edif <file>\n");
 		log("        Write the design to the specified edif file. Writing of an output file\n");
@@ -112,7 +112,7 @@ struct SynthMicrochipPass : public ScriptPass {
 		top_opt = "-auto-top";
 		edif_file.clear();
 		blif_file.clear();
-		family = "pf";
+		family = "polarfire";
 		flatten = false;
 		retime = false;
 		noiopad = false;
@@ -286,8 +286,8 @@ struct SynthMicrochipPass : public ScriptPass {
 				run("memory_dff"); // microchip_dsp will merge registers, reserve memory port registers first
 				if (help_mode)
 					run("techmap -map +/mul2dsp.v -map +/microchip/{family}_dsp_map.v {options}");
-				else if (family == "pf") // Microchip - map multipliers to DSP
-					run("techmap -map +/mul2dsp.v -map +/microchip/pf_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
+				else if (family == "polarfire") // Microchip - map multipliers to DSP
+					run("techmap -map +/mul2dsp.v -map +/microchip/polarfire_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
 					    "-D DSP_A_MAXWIDTH_PARTIAL=18 " // Partial multipliers are intentionally
 									    // limited to 18x18 in order to take
 									    // advantage of the (PCOUT >> 17) -> PCIN
@@ -303,7 +303,7 @@ struct SynthMicrochipPass : public ScriptPass {
 				run("select -clear");
 				if (help_mode)
 					run("microchip_dsp -family <family>");
-				else if (family == "pf") // Microchip - absorb cells into DSP
+				else if (family == "polarfire") // Microchip - absorb cells into DSP
 					run("microchip_dsp -family " + family);
 
 				run("chtype -set $mul t:$__soft_mul");
@@ -329,7 +329,7 @@ struct SynthMicrochipPass : public ScriptPass {
 				params = " [...]";
 			} else {
 
-				if (family == "pf") {
+				if (family == "polarfire") {
 					// cost of a single bit for memory lowered to soft logic
 					params += " -logic-cost-rom 0.015625";
 
@@ -452,7 +452,7 @@ struct SynthMicrochipPass : public ScriptPass {
 			// $_DLATCH_[NP][NP][01]_			(D-latch + reset to 0/1)
 			// $_DLATCHSR_[NP][NP][NP]_			(D-latch + set + reset)
 
-			if (family == "pf") {
+			if (family == "polarfire") {
 				std::string params = "";
 
 				// D-flop with async reset and enable

From 5ba06fd947113563e67af012c10cbd15f2bba766 Mon Sep 17 00:00:00 2001
From: C77874 <Damon.Ma@Microchip.com>
Date: Thu, 4 Jul 2024 10:33:59 -0700
Subject: [PATCH 188/499] another typo

---
 techlibs/microchip/tests/mac/mac.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/microchip/tests/mac/mac.ys b/techlibs/microchip/tests/mac/mac.ys
index cb22ad49df1..f8a0c45c5c1 100644
--- a/techlibs/microchip/tests/mac/mac.ys
+++ b/techlibs/microchip/tests/mac/mac.ys
@@ -18,7 +18,7 @@
 read_verilog mac.v
 
 # run the synth flow, specifies top module and additional parameters
-synticrochip -top mac -abc9 -family polarfire -noiopad
+synth_microchip -top mac -abc9 -family polarfire -noiopad
 
 # write final outputfile
 write_verilog -noexpr mac.vm

From 19d32148611707fb71146b8215ca90a469d93b7d Mon Sep 17 00:00:00 2001
From: chunlin min <chunlin.min@microchip.com>
Date: Thu, 4 Jul 2024 14:13:26 -0400
Subject: [PATCH 189/499] use output reg instead of additional reg declaration

---
 techlibs/microchip/cells_sim.v | 20 ++++++--------------
 1 file changed, 6 insertions(+), 14 deletions(-)

diff --git a/techlibs/microchip/cells_sim.v b/techlibs/microchip/cells_sim.v
index de4038e0954..f3b55fe4c70 100644
--- a/techlibs/microchip/cells_sim.v
+++ b/techlibs/microchip/cells_sim.v
@@ -164,22 +164,18 @@ module MICROCHIP_SYNC_SET_DFF(
 	input CLK,
 	input Set,
 	input En,
-	output Q);
+	output reg Q);
 	parameter [0:0] INIT = 1'b0; // unused
 
-	reg q_ff;
-
 	always @(posedge CLK) begin
 		if (En == 1) begin
 			if (Set == 0)
-				q_ff <= 1;
+				Q <= 1;
 			else
-				q_ff <= D;
+				Q <= D;
 		end
 	end
 
-	assign Q = q_ff;
-
 	specify
 		$setup(D , posedge CLK &&& En && Set, 0); // neg setup not supported?
 		$setup(En, posedge CLK, 109);
@@ -195,22 +191,18 @@ module MICROCHIP_SYNC_RESET_DFF(
 	input CLK,
 	input Reset,
 	input En,
-	output Q);
+	output reg Q);
 	parameter [0:0] INIT = 1'b0; // unused
 
-	reg q_ff;
-
 	always @(posedge CLK) begin
 		if (En == 1) begin
 			if (Reset == 0) 
-				q_ff <= 0;
+				Q <= 0;
 			else
-				q_ff <= D;
+				Q <= D;
 		end
 	end
 
-	assign Q = q_ff;
-
 	specify
 		$setup(D , posedge CLK &&& En && Reset, 0); // neg setup not supported?
 		$setup(En, posedge CLK, 109);

From e3c4791e5ba446e484385be7385fca2a4cfa87d6 Mon Sep 17 00:00:00 2001
From: chunlin min <chunlin.min@microchip.com>
Date: Thu, 4 Jul 2024 14:16:52 -0400
Subject: [PATCH 190/499] move microchip tests from techlibs/microchip/tests to
 tests/arch/microchip

---
 .../tests => tests/arch/microchip}/Registers/Registers.v          | 0
 .../tests => tests/arch/microchip}/Registers/Registers.ys         | 0
 .../microchip/tests => tests/arch/microchip}/carryout/carryout.v  | 0
 .../microchip/tests => tests/arch/microchip}/carryout/carryout.ys | 0
 .../microchip/tests => tests/arch/microchip}/cascade/cascade.v    | 0
 .../microchip/tests => tests/arch/microchip}/cascade/cascade.ys   | 0
 .../microchip/tests => tests/arch/microchip}/dff_opt/dff_opt.v    | 0
 .../microchip/tests => tests/arch/microchip}/dff_opt/dff_opt.ys   | 0
 .../microchip/tests => tests/arch/microchip}/full_dsp/full_dsp.v  | 0
 .../microchip/tests => tests/arch/microchip}/full_dsp/full_dsp.ys | 0
 .../tests => tests/arch/microchip}/large_mult/large_mult.v        | 0
 .../tests => tests/arch/microchip}/large_mult/large_mult.ys       | 0
 {techlibs/microchip/tests => tests/arch/microchip}/mac/mac.v      | 0
 {techlibs/microchip/tests => tests/arch/microchip}/mac/mac.ys     | 0
 .../tests => tests/arch/microchip}/postAdd_mult/postAdd_mult.v    | 0
 .../tests => tests/arch/microchip}/postAdd_mult/postAdd_mult.ys   | 0
 .../tests => tests/arch/microchip}/post_adder/post_adder.v        | 0
 .../tests => tests/arch/microchip}/post_adder/post_adder.ys       | 0
 .../tests => tests/arch/microchip}/pre_adder_dsp/pre_adder_dsp.v  | 0
 .../tests => tests/arch/microchip}/pre_adder_dsp/pre_adder_dsp.ys | 0
 .../microchip/tests => tests/arch/microchip}/ram_SDP/ram_SDP.v    | 0
 .../microchip/tests => tests/arch/microchip}/ram_SDP/ram_SDP.ys   | 0
 .../microchip/tests => tests/arch/microchip}/ram_TDP/ram_TDP.v    | 0
 .../microchip/tests => tests/arch/microchip}/ram_TDP/ram_TDP.ys   | 0
 .../microchip/tests => tests/arch/microchip}/reduce/reduce.v      | 0
 .../microchip/tests => tests/arch/microchip}/reduce/reduce.ys     | 0
 {techlibs/microchip/tests => tests/arch/microchip}/reg_c/reg_c.v  | 0
 {techlibs/microchip/tests => tests/arch/microchip}/reg_c/reg_c.ys | 0
 .../microchip/tests => tests/arch/microchip}/reg_test/reg_test.v  | 0
 .../microchip/tests => tests/arch/microchip}/reg_test/reg_test.ys | 0
 .../tests => tests/arch/microchip}/signed_mult/signed_mult.v      | 0
 .../tests => tests/arch/microchip}/signed_mult/signed_mult.ys     | 0
 .../tests => tests/arch/microchip}/simple_ram/simple_ram.v        | 0
 .../tests => tests/arch/microchip}/simple_ram/simple_ram.ys       | 0
 .../tests => tests/arch/microchip}/unsigned_mult/unsigned_mult.v  | 0
 .../tests => tests/arch/microchip}/unsigned_mult/unsigned_mult.ys | 0
 .../microchip/tests => tests/arch/microchip}/uram_ar/uram_ar.v    | 0
 .../microchip/tests => tests/arch/microchip}/uram_ar/uram_ar.ys   | 0
 .../microchip/tests => tests/arch/microchip}/uram_sr/uram_sr.v    | 0
 .../microchip/tests => tests/arch/microchip}/uram_sr/uram_sr.ys   | 0
 .../microchip/tests => tests/arch/microchip}/widemux/widemux.v    | 0
 .../microchip/tests => tests/arch/microchip}/widemux/widemux.ys   | 0
 42 files changed, 0 insertions(+), 0 deletions(-)
 rename {techlibs/microchip/tests => tests/arch/microchip}/Registers/Registers.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/Registers/Registers.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/carryout/carryout.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/carryout/carryout.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/cascade/cascade.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/cascade/cascade.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/dff_opt/dff_opt.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/dff_opt/dff_opt.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/full_dsp/full_dsp.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/full_dsp/full_dsp.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/large_mult/large_mult.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/large_mult/large_mult.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/mac/mac.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/mac/mac.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/postAdd_mult/postAdd_mult.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/postAdd_mult/postAdd_mult.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/post_adder/post_adder.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/post_adder/post_adder.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/pre_adder_dsp/pre_adder_dsp.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/pre_adder_dsp/pre_adder_dsp.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/ram_SDP/ram_SDP.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/ram_SDP/ram_SDP.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/ram_TDP/ram_TDP.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/ram_TDP/ram_TDP.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/reduce/reduce.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/reduce/reduce.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/reg_c/reg_c.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/reg_c/reg_c.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/reg_test/reg_test.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/reg_test/reg_test.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/signed_mult/signed_mult.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/signed_mult/signed_mult.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/simple_ram/simple_ram.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/simple_ram/simple_ram.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/unsigned_mult/unsigned_mult.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/unsigned_mult/unsigned_mult.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/uram_ar/uram_ar.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/uram_ar/uram_ar.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/uram_sr/uram_sr.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/uram_sr/uram_sr.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/widemux/widemux.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/widemux/widemux.ys (100%)

diff --git a/techlibs/microchip/tests/Registers/Registers.v b/tests/arch/microchip/Registers/Registers.v
similarity index 100%
rename from techlibs/microchip/tests/Registers/Registers.v
rename to tests/arch/microchip/Registers/Registers.v
diff --git a/techlibs/microchip/tests/Registers/Registers.ys b/tests/arch/microchip/Registers/Registers.ys
similarity index 100%
rename from techlibs/microchip/tests/Registers/Registers.ys
rename to tests/arch/microchip/Registers/Registers.ys
diff --git a/techlibs/microchip/tests/carryout/carryout.v b/tests/arch/microchip/carryout/carryout.v
similarity index 100%
rename from techlibs/microchip/tests/carryout/carryout.v
rename to tests/arch/microchip/carryout/carryout.v
diff --git a/techlibs/microchip/tests/carryout/carryout.ys b/tests/arch/microchip/carryout/carryout.ys
similarity index 100%
rename from techlibs/microchip/tests/carryout/carryout.ys
rename to tests/arch/microchip/carryout/carryout.ys
diff --git a/techlibs/microchip/tests/cascade/cascade.v b/tests/arch/microchip/cascade/cascade.v
similarity index 100%
rename from techlibs/microchip/tests/cascade/cascade.v
rename to tests/arch/microchip/cascade/cascade.v
diff --git a/techlibs/microchip/tests/cascade/cascade.ys b/tests/arch/microchip/cascade/cascade.ys
similarity index 100%
rename from techlibs/microchip/tests/cascade/cascade.ys
rename to tests/arch/microchip/cascade/cascade.ys
diff --git a/techlibs/microchip/tests/dff_opt/dff_opt.v b/tests/arch/microchip/dff_opt/dff_opt.v
similarity index 100%
rename from techlibs/microchip/tests/dff_opt/dff_opt.v
rename to tests/arch/microchip/dff_opt/dff_opt.v
diff --git a/techlibs/microchip/tests/dff_opt/dff_opt.ys b/tests/arch/microchip/dff_opt/dff_opt.ys
similarity index 100%
rename from techlibs/microchip/tests/dff_opt/dff_opt.ys
rename to tests/arch/microchip/dff_opt/dff_opt.ys
diff --git a/techlibs/microchip/tests/full_dsp/full_dsp.v b/tests/arch/microchip/full_dsp/full_dsp.v
similarity index 100%
rename from techlibs/microchip/tests/full_dsp/full_dsp.v
rename to tests/arch/microchip/full_dsp/full_dsp.v
diff --git a/techlibs/microchip/tests/full_dsp/full_dsp.ys b/tests/arch/microchip/full_dsp/full_dsp.ys
similarity index 100%
rename from techlibs/microchip/tests/full_dsp/full_dsp.ys
rename to tests/arch/microchip/full_dsp/full_dsp.ys
diff --git a/techlibs/microchip/tests/large_mult/large_mult.v b/tests/arch/microchip/large_mult/large_mult.v
similarity index 100%
rename from techlibs/microchip/tests/large_mult/large_mult.v
rename to tests/arch/microchip/large_mult/large_mult.v
diff --git a/techlibs/microchip/tests/large_mult/large_mult.ys b/tests/arch/microchip/large_mult/large_mult.ys
similarity index 100%
rename from techlibs/microchip/tests/large_mult/large_mult.ys
rename to tests/arch/microchip/large_mult/large_mult.ys
diff --git a/techlibs/microchip/tests/mac/mac.v b/tests/arch/microchip/mac/mac.v
similarity index 100%
rename from techlibs/microchip/tests/mac/mac.v
rename to tests/arch/microchip/mac/mac.v
diff --git a/techlibs/microchip/tests/mac/mac.ys b/tests/arch/microchip/mac/mac.ys
similarity index 100%
rename from techlibs/microchip/tests/mac/mac.ys
rename to tests/arch/microchip/mac/mac.ys
diff --git a/techlibs/microchip/tests/postAdd_mult/postAdd_mult.v b/tests/arch/microchip/postAdd_mult/postAdd_mult.v
similarity index 100%
rename from techlibs/microchip/tests/postAdd_mult/postAdd_mult.v
rename to tests/arch/microchip/postAdd_mult/postAdd_mult.v
diff --git a/techlibs/microchip/tests/postAdd_mult/postAdd_mult.ys b/tests/arch/microchip/postAdd_mult/postAdd_mult.ys
similarity index 100%
rename from techlibs/microchip/tests/postAdd_mult/postAdd_mult.ys
rename to tests/arch/microchip/postAdd_mult/postAdd_mult.ys
diff --git a/techlibs/microchip/tests/post_adder/post_adder.v b/tests/arch/microchip/post_adder/post_adder.v
similarity index 100%
rename from techlibs/microchip/tests/post_adder/post_adder.v
rename to tests/arch/microchip/post_adder/post_adder.v
diff --git a/techlibs/microchip/tests/post_adder/post_adder.ys b/tests/arch/microchip/post_adder/post_adder.ys
similarity index 100%
rename from techlibs/microchip/tests/post_adder/post_adder.ys
rename to tests/arch/microchip/post_adder/post_adder.ys
diff --git a/techlibs/microchip/tests/pre_adder_dsp/pre_adder_dsp.v b/tests/arch/microchip/pre_adder_dsp/pre_adder_dsp.v
similarity index 100%
rename from techlibs/microchip/tests/pre_adder_dsp/pre_adder_dsp.v
rename to tests/arch/microchip/pre_adder_dsp/pre_adder_dsp.v
diff --git a/techlibs/microchip/tests/pre_adder_dsp/pre_adder_dsp.ys b/tests/arch/microchip/pre_adder_dsp/pre_adder_dsp.ys
similarity index 100%
rename from techlibs/microchip/tests/pre_adder_dsp/pre_adder_dsp.ys
rename to tests/arch/microchip/pre_adder_dsp/pre_adder_dsp.ys
diff --git a/techlibs/microchip/tests/ram_SDP/ram_SDP.v b/tests/arch/microchip/ram_SDP/ram_SDP.v
similarity index 100%
rename from techlibs/microchip/tests/ram_SDP/ram_SDP.v
rename to tests/arch/microchip/ram_SDP/ram_SDP.v
diff --git a/techlibs/microchip/tests/ram_SDP/ram_SDP.ys b/tests/arch/microchip/ram_SDP/ram_SDP.ys
similarity index 100%
rename from techlibs/microchip/tests/ram_SDP/ram_SDP.ys
rename to tests/arch/microchip/ram_SDP/ram_SDP.ys
diff --git a/techlibs/microchip/tests/ram_TDP/ram_TDP.v b/tests/arch/microchip/ram_TDP/ram_TDP.v
similarity index 100%
rename from techlibs/microchip/tests/ram_TDP/ram_TDP.v
rename to tests/arch/microchip/ram_TDP/ram_TDP.v
diff --git a/techlibs/microchip/tests/ram_TDP/ram_TDP.ys b/tests/arch/microchip/ram_TDP/ram_TDP.ys
similarity index 100%
rename from techlibs/microchip/tests/ram_TDP/ram_TDP.ys
rename to tests/arch/microchip/ram_TDP/ram_TDP.ys
diff --git a/techlibs/microchip/tests/reduce/reduce.v b/tests/arch/microchip/reduce/reduce.v
similarity index 100%
rename from techlibs/microchip/tests/reduce/reduce.v
rename to tests/arch/microchip/reduce/reduce.v
diff --git a/techlibs/microchip/tests/reduce/reduce.ys b/tests/arch/microchip/reduce/reduce.ys
similarity index 100%
rename from techlibs/microchip/tests/reduce/reduce.ys
rename to tests/arch/microchip/reduce/reduce.ys
diff --git a/techlibs/microchip/tests/reg_c/reg_c.v b/tests/arch/microchip/reg_c/reg_c.v
similarity index 100%
rename from techlibs/microchip/tests/reg_c/reg_c.v
rename to tests/arch/microchip/reg_c/reg_c.v
diff --git a/techlibs/microchip/tests/reg_c/reg_c.ys b/tests/arch/microchip/reg_c/reg_c.ys
similarity index 100%
rename from techlibs/microchip/tests/reg_c/reg_c.ys
rename to tests/arch/microchip/reg_c/reg_c.ys
diff --git a/techlibs/microchip/tests/reg_test/reg_test.v b/tests/arch/microchip/reg_test/reg_test.v
similarity index 100%
rename from techlibs/microchip/tests/reg_test/reg_test.v
rename to tests/arch/microchip/reg_test/reg_test.v
diff --git a/techlibs/microchip/tests/reg_test/reg_test.ys b/tests/arch/microchip/reg_test/reg_test.ys
similarity index 100%
rename from techlibs/microchip/tests/reg_test/reg_test.ys
rename to tests/arch/microchip/reg_test/reg_test.ys
diff --git a/techlibs/microchip/tests/signed_mult/signed_mult.v b/tests/arch/microchip/signed_mult/signed_mult.v
similarity index 100%
rename from techlibs/microchip/tests/signed_mult/signed_mult.v
rename to tests/arch/microchip/signed_mult/signed_mult.v
diff --git a/techlibs/microchip/tests/signed_mult/signed_mult.ys b/tests/arch/microchip/signed_mult/signed_mult.ys
similarity index 100%
rename from techlibs/microchip/tests/signed_mult/signed_mult.ys
rename to tests/arch/microchip/signed_mult/signed_mult.ys
diff --git a/techlibs/microchip/tests/simple_ram/simple_ram.v b/tests/arch/microchip/simple_ram/simple_ram.v
similarity index 100%
rename from techlibs/microchip/tests/simple_ram/simple_ram.v
rename to tests/arch/microchip/simple_ram/simple_ram.v
diff --git a/techlibs/microchip/tests/simple_ram/simple_ram.ys b/tests/arch/microchip/simple_ram/simple_ram.ys
similarity index 100%
rename from techlibs/microchip/tests/simple_ram/simple_ram.ys
rename to tests/arch/microchip/simple_ram/simple_ram.ys
diff --git a/techlibs/microchip/tests/unsigned_mult/unsigned_mult.v b/tests/arch/microchip/unsigned_mult/unsigned_mult.v
similarity index 100%
rename from techlibs/microchip/tests/unsigned_mult/unsigned_mult.v
rename to tests/arch/microchip/unsigned_mult/unsigned_mult.v
diff --git a/techlibs/microchip/tests/unsigned_mult/unsigned_mult.ys b/tests/arch/microchip/unsigned_mult/unsigned_mult.ys
similarity index 100%
rename from techlibs/microchip/tests/unsigned_mult/unsigned_mult.ys
rename to tests/arch/microchip/unsigned_mult/unsigned_mult.ys
diff --git a/techlibs/microchip/tests/uram_ar/uram_ar.v b/tests/arch/microchip/uram_ar/uram_ar.v
similarity index 100%
rename from techlibs/microchip/tests/uram_ar/uram_ar.v
rename to tests/arch/microchip/uram_ar/uram_ar.v
diff --git a/techlibs/microchip/tests/uram_ar/uram_ar.ys b/tests/arch/microchip/uram_ar/uram_ar.ys
similarity index 100%
rename from techlibs/microchip/tests/uram_ar/uram_ar.ys
rename to tests/arch/microchip/uram_ar/uram_ar.ys
diff --git a/techlibs/microchip/tests/uram_sr/uram_sr.v b/tests/arch/microchip/uram_sr/uram_sr.v
similarity index 100%
rename from techlibs/microchip/tests/uram_sr/uram_sr.v
rename to tests/arch/microchip/uram_sr/uram_sr.v
diff --git a/techlibs/microchip/tests/uram_sr/uram_sr.ys b/tests/arch/microchip/uram_sr/uram_sr.ys
similarity index 100%
rename from techlibs/microchip/tests/uram_sr/uram_sr.ys
rename to tests/arch/microchip/uram_sr/uram_sr.ys
diff --git a/techlibs/microchip/tests/widemux/widemux.v b/tests/arch/microchip/widemux/widemux.v
similarity index 100%
rename from techlibs/microchip/tests/widemux/widemux.v
rename to tests/arch/microchip/widemux/widemux.v
diff --git a/techlibs/microchip/tests/widemux/widemux.ys b/tests/arch/microchip/widemux/widemux.ys
similarity index 100%
rename from techlibs/microchip/tests/widemux/widemux.ys
rename to tests/arch/microchip/widemux/widemux.ys

From 8e7ec2d66091d3b657e2c58d4c4d113c7fb32067 Mon Sep 17 00:00:00 2001
From: chunlin min <chunlin.min@microchip.com>
Date: Thu, 4 Jul 2024 15:45:44 -0400
Subject: [PATCH 191/499] add assertions for synth_microchip tests

---
 techlibs/microchip/arith_map.v                |  6 +++---
 tests/arch/microchip/.gitignore               |  4 ++++
 .../microchip/{Registers => }/Registers.v     |  2 +-
 .../microchip/{Registers => }/Registers.ys    |  5 +++--
 .../arch/microchip/{carryout => }/carryout.v  |  0
 .../arch/microchip/{carryout => }/carryout.ys |  3 ++-
 tests/arch/microchip/{cascade => }/cascade.v  |  0
 tests/arch/microchip/{cascade => }/cascade.ys |  3 ++-
 tests/arch/microchip/{dff_opt => }/dff_opt.v  |  0
 tests/arch/microchip/{dff_opt => }/dff_opt.ys |  7 +++++--
 .../arch/microchip/{full_dsp => }/full_dsp.v  |  0
 .../arch/microchip/{full_dsp => }/full_dsp.ys |  3 ++-
 .../microchip/{large_mult => }/large_mult.v   |  0
 .../microchip/{large_mult => }/large_mult.ys  |  4 +++-
 tests/arch/microchip/{mac => }/mac.v          |  0
 tests/arch/microchip/{mac => }/mac.ys         |  4 ++--
 .../{postAdd_mult => }/postAdd_mult.v         |  0
 .../{postAdd_mult => }/postAdd_mult.ys        |  3 ++-
 .../microchip/{post_adder => }/post_adder.v   |  0
 .../microchip/{post_adder => }/post_adder.ys  |  6 ++++--
 .../{pre_adder_dsp => }/pre_adder_dsp.v       |  0
 .../{pre_adder_dsp => }/pre_adder_dsp.ys      |  3 ++-
 tests/arch/microchip/{ram_SDP => }/ram_SDP.v  |  0
 tests/arch/microchip/{ram_SDP => }/ram_SDP.ys |  5 ++++-
 tests/arch/microchip/{ram_TDP => }/ram_TDP.v  |  0
 tests/arch/microchip/{ram_TDP => }/ram_TDP.ys |  3 ++-
 tests/arch/microchip/{reduce => }/reduce.v    |  0
 tests/arch/microchip/{reduce => }/reduce.ys   |  4 +++-
 tests/arch/microchip/{reg_c => }/reg_c.v      |  0
 tests/arch/microchip/{reg_c => }/reg_c.ys     |  3 ++-
 .../arch/microchip/{reg_test => }/reg_test.v  |  0
 .../arch/microchip/{reg_test => }/reg_test.ys |  3 ++-
 tests/arch/microchip/run-test.sh              |  4 ++++
 .../microchip/{signed_mult => }/signed_mult.v |  0
 .../{signed_mult => }/signed_mult.ys          |  3 ++-
 .../microchip/{simple_ram => }/simple_ram.v   |  0
 .../microchip/{simple_ram => }/simple_ram.ys  |  3 ++-
 .../{unsigned_mult => }/unsigned_mult.v       |  0
 .../{unsigned_mult => }/unsigned_mult.ys      |  3 ++-
 tests/arch/microchip/{uram_ar => }/uram_ar.v  |  4 ++--
 tests/arch/microchip/{uram_ar => }/uram_ar.ys |  3 ++-
 tests/arch/microchip/{uram_sr => }/uram_sr.v  |  0
 tests/arch/microchip/{uram_sr => }/uram_sr.ys |  3 ++-
 tests/arch/microchip/{widemux => }/widemux.v  | 19 +------------------
 tests/arch/microchip/{widemux => }/widemux.ys |  3 ++-
 45 files changed, 67 insertions(+), 49 deletions(-)
 create mode 100644 tests/arch/microchip/.gitignore
 rename tests/arch/microchip/{Registers => }/Registers.v (98%)
 rename tests/arch/microchip/{Registers => }/Registers.ys (89%)
 rename tests/arch/microchip/{carryout => }/carryout.v (100%)
 rename tests/arch/microchip/{carryout => }/carryout.ys (92%)
 rename tests/arch/microchip/{cascade => }/cascade.v (100%)
 rename tests/arch/microchip/{cascade => }/cascade.ys (92%)
 rename tests/arch/microchip/{dff_opt => }/dff_opt.v (100%)
 rename tests/arch/microchip/{dff_opt => }/dff_opt.ys (86%)
 rename tests/arch/microchip/{full_dsp => }/full_dsp.v (100%)
 rename tests/arch/microchip/{full_dsp => }/full_dsp.ys (92%)
 rename tests/arch/microchip/{large_mult => }/large_mult.v (100%)
 rename tests/arch/microchip/{large_mult => }/large_mult.ys (92%)
 rename tests/arch/microchip/{mac => }/mac.v (100%)
 rename tests/arch/microchip/{mac => }/mac.ys (93%)
 rename tests/arch/microchip/{postAdd_mult => }/postAdd_mult.v (100%)
 rename tests/arch/microchip/{postAdd_mult => }/postAdd_mult.ys (92%)
 rename tests/arch/microchip/{post_adder => }/post_adder.v (100%)
 rename tests/arch/microchip/{post_adder => }/post_adder.ys (85%)
 rename tests/arch/microchip/{pre_adder_dsp => }/pre_adder_dsp.v (100%)
 rename tests/arch/microchip/{pre_adder_dsp => }/pre_adder_dsp.ys (92%)
 rename tests/arch/microchip/{ram_SDP => }/ram_SDP.v (100%)
 rename tests/arch/microchip/{ram_SDP => }/ram_SDP.ys (88%)
 rename tests/arch/microchip/{ram_TDP => }/ram_TDP.v (100%)
 rename tests/arch/microchip/{ram_TDP => }/ram_TDP.ys (92%)
 rename tests/arch/microchip/{reduce => }/reduce.v (100%)
 rename tests/arch/microchip/{reduce => }/reduce.ys (92%)
 rename tests/arch/microchip/{reg_c => }/reg_c.v (100%)
 rename tests/arch/microchip/{reg_c => }/reg_c.ys (92%)
 rename tests/arch/microchip/{reg_test => }/reg_test.v (100%)
 rename tests/arch/microchip/{reg_test => }/reg_test.ys (92%)
 create mode 100755 tests/arch/microchip/run-test.sh
 rename tests/arch/microchip/{signed_mult => }/signed_mult.v (100%)
 rename tests/arch/microchip/{signed_mult => }/signed_mult.ys (92%)
 rename tests/arch/microchip/{simple_ram => }/simple_ram.v (100%)
 rename tests/arch/microchip/{simple_ram => }/simple_ram.ys (92%)
 rename tests/arch/microchip/{unsigned_mult => }/unsigned_mult.v (100%)
 rename tests/arch/microchip/{unsigned_mult => }/unsigned_mult.ys (92%)
 rename tests/arch/microchip/{uram_ar => }/uram_ar.v (95%)
 rename tests/arch/microchip/{uram_ar => }/uram_ar.ys (92%)
 rename tests/arch/microchip/{uram_sr => }/uram_sr.v (100%)
 rename tests/arch/microchip/{uram_sr => }/uram_sr.ys (92%)
 rename tests/arch/microchip/{widemux => }/widemux.v (82%)
 rename tests/arch/microchip/{widemux => }/widemux.ys (93%)

diff --git a/techlibs/microchip/arith_map.v b/techlibs/microchip/arith_map.v
index c21f34f4427..6b105a1f3cc 100644
--- a/techlibs/microchip/arith_map.v
+++ b/techlibs/microchip/arith_map.v
@@ -31,9 +31,9 @@ endmodule
 
 (* techmap_celltype = "$reduce_xor" *)
 module \$__microchip_XOR8_ (A, Y);
-	parameter A_SIGNED = 0;
-	parameter A_WIDTH = 0;
-	parameter Y_WIDTH = 0;
+	parameter A_SIGNED = 1;
+	parameter A_WIDTH = 8;
+	parameter Y_WIDTH = 1;
 
 	input [A_WIDTH-1:0] A;
 	output [Y_WIDTH-1:0] Y;
diff --git a/tests/arch/microchip/.gitignore b/tests/arch/microchip/.gitignore
new file mode 100644
index 00000000000..9c0a77944a9
--- /dev/null
+++ b/tests/arch/microchip/.gitignore
@@ -0,0 +1,4 @@
+*.log
+/run-test.mk
+*.vm
+
diff --git a/tests/arch/microchip/Registers/Registers.v b/tests/arch/microchip/Registers.v
similarity index 98%
rename from tests/arch/microchip/Registers/Registers.v
rename to tests/arch/microchip/Registers.v
index b9a86d1d519..160c09cc736 100644
--- a/tests/arch/microchip/Registers/Registers.v
+++ b/tests/arch/microchip/Registers.v
@@ -21,7 +21,7 @@ module Registers(
 	input en,
 	input rst,
 	input D,
-	output Q
+	output reg Q
 );
 parameter LOAD_DATA = 1;
 
diff --git a/tests/arch/microchip/Registers/Registers.ys b/tests/arch/microchip/Registers.ys
similarity index 89%
rename from tests/arch/microchip/Registers/Registers.ys
rename to tests/arch/microchip/Registers.ys
index 7b1a1ed77a1..bbf7a6c912f 100644
--- a/tests/arch/microchip/Registers/Registers.ys
+++ b/tests/arch/microchip/Registers.ys
@@ -19,5 +19,6 @@ read_verilog Registers.v
 
 synth_microchip -top Registers -abc9 -family polarfire -noiopad
 
-# write final outputfile
-write_verilog -noexpr Registers.vm
+select -assert-count 1 t:SLE
+select -assert-count 1 t:CLKBUF
+select -assert-none t:SLE t:CLKBUF %% t:* %D
diff --git a/tests/arch/microchip/carryout/carryout.v b/tests/arch/microchip/carryout.v
similarity index 100%
rename from tests/arch/microchip/carryout/carryout.v
rename to tests/arch/microchip/carryout.v
diff --git a/tests/arch/microchip/carryout/carryout.ys b/tests/arch/microchip/carryout.ys
similarity index 92%
rename from tests/arch/microchip/carryout/carryout.ys
rename to tests/arch/microchip/carryout.ys
index 65d4d6709f2..7c79dfba38f 100644
--- a/tests/arch/microchip/carryout/carryout.ys
+++ b/tests/arch/microchip/carryout.ys
@@ -18,4 +18,5 @@ read_verilog carryout.v
 
 synth_microchip -top carryout -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr carryout.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/cascade/cascade.v b/tests/arch/microchip/cascade.v
similarity index 100%
rename from tests/arch/microchip/cascade/cascade.v
rename to tests/arch/microchip/cascade.v
diff --git a/tests/arch/microchip/cascade/cascade.ys b/tests/arch/microchip/cascade.ys
similarity index 92%
rename from tests/arch/microchip/cascade/cascade.ys
rename to tests/arch/microchip/cascade.ys
index a817c094553..7248c562594 100644
--- a/tests/arch/microchip/cascade/cascade.ys
+++ b/tests/arch/microchip/cascade.ys
@@ -18,4 +18,5 @@ read_verilog cascade.v
 
 synth_microchip -top cascade -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr cascade.vm
+select -assert-count 2 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/dff_opt/dff_opt.v b/tests/arch/microchip/dff_opt.v
similarity index 100%
rename from tests/arch/microchip/dff_opt/dff_opt.v
rename to tests/arch/microchip/dff_opt.v
diff --git a/tests/arch/microchip/dff_opt/dff_opt.ys b/tests/arch/microchip/dff_opt.ys
similarity index 86%
rename from tests/arch/microchip/dff_opt/dff_opt.ys
rename to tests/arch/microchip/dff_opt.ys
index 776081639f9..f159ad864f4 100644
--- a/tests/arch/microchip/dff_opt/dff_opt.ys
+++ b/tests/arch/microchip/dff_opt.ys
@@ -13,9 +13,12 @@
 # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
 read_verilog dff_opt.v 
 
 synth_microchip -top dff_opt -abc9 -family polarfire -noiopad
 
-# write final outputfile
-write_verilog -noexpr dff_opt.vm
+select -assert-count 1 t:SLE
+select -assert-count 1 t:CFG4
+select -assert-count 1 t:CLKBUF
+select -assert-none t:SLE t:CFG4 t:CLKBUF %% t:* %D
\ No newline at end of file
diff --git a/tests/arch/microchip/full_dsp/full_dsp.v b/tests/arch/microchip/full_dsp.v
similarity index 100%
rename from tests/arch/microchip/full_dsp/full_dsp.v
rename to tests/arch/microchip/full_dsp.v
diff --git a/tests/arch/microchip/full_dsp/full_dsp.ys b/tests/arch/microchip/full_dsp.ys
similarity index 92%
rename from tests/arch/microchip/full_dsp/full_dsp.ys
rename to tests/arch/microchip/full_dsp.ys
index 67c66fa1989..9fce46a38bb 100644
--- a/tests/arch/microchip/full_dsp/full_dsp.ys
+++ b/tests/arch/microchip/full_dsp.ys
@@ -18,4 +18,5 @@ read_verilog full_dsp.v
 
 synth_microchip -top full_dsp -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr full_dsp.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/large_mult/large_mult.v b/tests/arch/microchip/large_mult.v
similarity index 100%
rename from tests/arch/microchip/large_mult/large_mult.v
rename to tests/arch/microchip/large_mult.v
diff --git a/tests/arch/microchip/large_mult/large_mult.ys b/tests/arch/microchip/large_mult.ys
similarity index 92%
rename from tests/arch/microchip/large_mult/large_mult.ys
rename to tests/arch/microchip/large_mult.ys
index ea3c80a0ddd..b76e5576af2 100644
--- a/tests/arch/microchip/large_mult/large_mult.ys
+++ b/tests/arch/microchip/large_mult.ys
@@ -18,4 +18,6 @@ read_verilog large_mult.v
 
 synth_microchip -top large_mult -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr large_mult.vm
+select -assert-count 2 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
+
diff --git a/tests/arch/microchip/mac/mac.v b/tests/arch/microchip/mac.v
similarity index 100%
rename from tests/arch/microchip/mac/mac.v
rename to tests/arch/microchip/mac.v
diff --git a/tests/arch/microchip/mac/mac.ys b/tests/arch/microchip/mac.ys
similarity index 93%
rename from tests/arch/microchip/mac/mac.ys
rename to tests/arch/microchip/mac.ys
index f8a0c45c5c1..69352354743 100644
--- a/tests/arch/microchip/mac/mac.ys
+++ b/tests/arch/microchip/mac.ys
@@ -20,5 +20,5 @@ read_verilog mac.v
 # run the synth flow, specifies top module and additional parameters
 synth_microchip -top mac -abc9 -family polarfire -noiopad
 
-# write final outputfile
-write_verilog -noexpr mac.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
\ No newline at end of file
diff --git a/tests/arch/microchip/postAdd_mult/postAdd_mult.v b/tests/arch/microchip/postAdd_mult.v
similarity index 100%
rename from tests/arch/microchip/postAdd_mult/postAdd_mult.v
rename to tests/arch/microchip/postAdd_mult.v
diff --git a/tests/arch/microchip/postAdd_mult/postAdd_mult.ys b/tests/arch/microchip/postAdd_mult.ys
similarity index 92%
rename from tests/arch/microchip/postAdd_mult/postAdd_mult.ys
rename to tests/arch/microchip/postAdd_mult.ys
index 54754bb7f5a..7d0a4bf0224 100644
--- a/tests/arch/microchip/postAdd_mult/postAdd_mult.ys
+++ b/tests/arch/microchip/postAdd_mult.ys
@@ -18,4 +18,5 @@ read_verilog postAdd_mult.v
 
 synth_microchip -top postAdd_mult -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr postAdd_mult.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/post_adder/post_adder.v b/tests/arch/microchip/post_adder.v
similarity index 100%
rename from tests/arch/microchip/post_adder/post_adder.v
rename to tests/arch/microchip/post_adder.v
diff --git a/tests/arch/microchip/post_adder/post_adder.ys b/tests/arch/microchip/post_adder.ys
similarity index 85%
rename from tests/arch/microchip/post_adder/post_adder.ys
rename to tests/arch/microchip/post_adder.ys
index 29f0e73f033..196215cac3e 100644
--- a/tests/arch/microchip/post_adder/post_adder.ys
+++ b/tests/arch/microchip/post_adder.ys
@@ -16,6 +16,8 @@
 
 read_verilog post_adder.v
 
-synth_microchip -top post_adder -abc9 -family polarfire
+synth_microchip -top post_adder -abc9 -family polarfire -noiopad
+
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
 
-write_verilog -noexpr post_adder.vm
diff --git a/tests/arch/microchip/pre_adder_dsp/pre_adder_dsp.v b/tests/arch/microchip/pre_adder_dsp.v
similarity index 100%
rename from tests/arch/microchip/pre_adder_dsp/pre_adder_dsp.v
rename to tests/arch/microchip/pre_adder_dsp.v
diff --git a/tests/arch/microchip/pre_adder_dsp/pre_adder_dsp.ys b/tests/arch/microchip/pre_adder_dsp.ys
similarity index 92%
rename from tests/arch/microchip/pre_adder_dsp/pre_adder_dsp.ys
rename to tests/arch/microchip/pre_adder_dsp.ys
index 1510f4ed61b..5aa87d432b4 100644
--- a/tests/arch/microchip/pre_adder_dsp/pre_adder_dsp.ys
+++ b/tests/arch/microchip/pre_adder_dsp.ys
@@ -18,4 +18,5 @@ read_verilog pre_adder_dsp.v
 
 synth_microchip -top pre_adder_dsp -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr pre_adder_dsp.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
\ No newline at end of file
diff --git a/tests/arch/microchip/ram_SDP/ram_SDP.v b/tests/arch/microchip/ram_SDP.v
similarity index 100%
rename from tests/arch/microchip/ram_SDP/ram_SDP.v
rename to tests/arch/microchip/ram_SDP.v
diff --git a/tests/arch/microchip/ram_SDP/ram_SDP.ys b/tests/arch/microchip/ram_SDP.ys
similarity index 88%
rename from tests/arch/microchip/ram_SDP/ram_SDP.ys
rename to tests/arch/microchip/ram_SDP.ys
index 0060c882db1..59f08705176 100644
--- a/tests/arch/microchip/ram_SDP/ram_SDP.ys
+++ b/tests/arch/microchip/ram_SDP.ys
@@ -18,4 +18,7 @@ read_verilog ram_SDP.v
 
 synth_microchip -top ram_SDP -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr ram_SDP.vm
+select -assert-count 1 t:RAM1K20
+select -assert-count 1 t:CFG1
+select -assert-none t:RAM1K20 t:CFG1 %% t:* %D
+
diff --git a/tests/arch/microchip/ram_TDP/ram_TDP.v b/tests/arch/microchip/ram_TDP.v
similarity index 100%
rename from tests/arch/microchip/ram_TDP/ram_TDP.v
rename to tests/arch/microchip/ram_TDP.v
diff --git a/tests/arch/microchip/ram_TDP/ram_TDP.ys b/tests/arch/microchip/ram_TDP.ys
similarity index 92%
rename from tests/arch/microchip/ram_TDP/ram_TDP.ys
rename to tests/arch/microchip/ram_TDP.ys
index 9fe5fdbe76a..9dab3cfdc2a 100644
--- a/tests/arch/microchip/ram_TDP/ram_TDP.ys
+++ b/tests/arch/microchip/ram_TDP.ys
@@ -18,4 +18,5 @@ read_verilog ram_TDP.v
 
 synth_microchip -top ram_TDP -abc9 -family polarfire -noiopad -debug_memory
 
-write_verilog -noexpr ram_TDP.vm
+select -assert-count 1 t:RAM1K20
+select -assert-none t:RAM1K20 %% t:* %D
diff --git a/tests/arch/microchip/reduce/reduce.v b/tests/arch/microchip/reduce.v
similarity index 100%
rename from tests/arch/microchip/reduce/reduce.v
rename to tests/arch/microchip/reduce.v
diff --git a/tests/arch/microchip/reduce/reduce.ys b/tests/arch/microchip/reduce.ys
similarity index 92%
rename from tests/arch/microchip/reduce/reduce.ys
rename to tests/arch/microchip/reduce.ys
index 3341f51a23f..789912f3225 100644
--- a/tests/arch/microchip/reduce/reduce.ys
+++ b/tests/arch/microchip/reduce.ys
@@ -18,4 +18,6 @@ read_verilog reduce.v
 
 synth_microchip -top reduce -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr reduce.vm
+select -assert-count 1 t:XOR8
+select -assert-none t:XOR8 %% t:* %D
+
diff --git a/tests/arch/microchip/reg_c/reg_c.v b/tests/arch/microchip/reg_c.v
similarity index 100%
rename from tests/arch/microchip/reg_c/reg_c.v
rename to tests/arch/microchip/reg_c.v
diff --git a/tests/arch/microchip/reg_c/reg_c.ys b/tests/arch/microchip/reg_c.ys
similarity index 92%
rename from tests/arch/microchip/reg_c/reg_c.ys
rename to tests/arch/microchip/reg_c.ys
index 0265be56f32..994e0811137 100644
--- a/tests/arch/microchip/reg_c/reg_c.ys
+++ b/tests/arch/microchip/reg_c.ys
@@ -18,4 +18,5 @@ read_verilog reg_c.v
 
 synth_microchip -top reg_c -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr reg_c.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/reg_test/reg_test.v b/tests/arch/microchip/reg_test.v
similarity index 100%
rename from tests/arch/microchip/reg_test/reg_test.v
rename to tests/arch/microchip/reg_test.v
diff --git a/tests/arch/microchip/reg_test/reg_test.ys b/tests/arch/microchip/reg_test.ys
similarity index 92%
rename from tests/arch/microchip/reg_test/reg_test.ys
rename to tests/arch/microchip/reg_test.ys
index 7bd44a99e7b..1b225b7bf64 100644
--- a/tests/arch/microchip/reg_test/reg_test.ys
+++ b/tests/arch/microchip/reg_test.ys
@@ -18,4 +18,5 @@ read_verilog reg_test.v
 
 synth_microchip -top reg_test -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr reg_test.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/run-test.sh b/tests/arch/microchip/run-test.sh
new file mode 100755
index 00000000000..4be4b70ae17
--- /dev/null
+++ b/tests/arch/microchip/run-test.sh
@@ -0,0 +1,4 @@
+#!/usr/bin/env bash
+set -eu
+source ../../gen-tests-makefile.sh
+run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"
diff --git a/tests/arch/microchip/signed_mult/signed_mult.v b/tests/arch/microchip/signed_mult.v
similarity index 100%
rename from tests/arch/microchip/signed_mult/signed_mult.v
rename to tests/arch/microchip/signed_mult.v
diff --git a/tests/arch/microchip/signed_mult/signed_mult.ys b/tests/arch/microchip/signed_mult.ys
similarity index 92%
rename from tests/arch/microchip/signed_mult/signed_mult.ys
rename to tests/arch/microchip/signed_mult.ys
index 93588a5dd83..931052163c3 100755
--- a/tests/arch/microchip/signed_mult/signed_mult.ys
+++ b/tests/arch/microchip/signed_mult.ys
@@ -18,4 +18,5 @@ read_verilog signed_mult.v
 
 synth_microchip -top signed_mult -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr signed_mult.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/simple_ram/simple_ram.v b/tests/arch/microchip/simple_ram.v
similarity index 100%
rename from tests/arch/microchip/simple_ram/simple_ram.v
rename to tests/arch/microchip/simple_ram.v
diff --git a/tests/arch/microchip/simple_ram/simple_ram.ys b/tests/arch/microchip/simple_ram.ys
similarity index 92%
rename from tests/arch/microchip/simple_ram/simple_ram.ys
rename to tests/arch/microchip/simple_ram.ys
index 85975d25093..5ed8448ee27 100644
--- a/tests/arch/microchip/simple_ram/simple_ram.ys
+++ b/tests/arch/microchip/simple_ram.ys
@@ -18,4 +18,5 @@ read_verilog simple_ram.v
 
 synth_microchip -top simple_ram -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr simple_ram.vm
+select -assert-count 1 t:RAM1K20
+select -assert-none t:RAM1K20 %% t:* %D
diff --git a/tests/arch/microchip/unsigned_mult/unsigned_mult.v b/tests/arch/microchip/unsigned_mult.v
similarity index 100%
rename from tests/arch/microchip/unsigned_mult/unsigned_mult.v
rename to tests/arch/microchip/unsigned_mult.v
diff --git a/tests/arch/microchip/unsigned_mult/unsigned_mult.ys b/tests/arch/microchip/unsigned_mult.ys
similarity index 92%
rename from tests/arch/microchip/unsigned_mult/unsigned_mult.ys
rename to tests/arch/microchip/unsigned_mult.ys
index e588912eaba..9cc96c99811 100644
--- a/tests/arch/microchip/unsigned_mult/unsigned_mult.ys
+++ b/tests/arch/microchip/unsigned_mult.ys
@@ -18,4 +18,5 @@ read_verilog unsigned_mult.v
 
 synth_microchip -top unsigned_mult -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr unsigned_mult.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/uram_ar/uram_ar.v b/tests/arch/microchip/uram_ar.v
similarity index 95%
rename from tests/arch/microchip/uram_ar/uram_ar.v
rename to tests/arch/microchip/uram_ar.v
index b3b542df634..c73ece07e31 100644
--- a/tests/arch/microchip/uram_ar/uram_ar.v
+++ b/tests/arch/microchip/uram_ar.v
@@ -17,9 +17,9 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 module uram_ar(data,waddr,we,clk,q);
-parameter d_width = 27;
+parameter d_width = 12;
 parameter addr_width = 2;
-parameter mem_depth = 4;
+parameter mem_depth = 12;
 input [d_width-1:0] data;
 input [addr_width-1:0] waddr;
 input we, clk;
diff --git a/tests/arch/microchip/uram_ar/uram_ar.ys b/tests/arch/microchip/uram_ar.ys
similarity index 92%
rename from tests/arch/microchip/uram_ar/uram_ar.ys
rename to tests/arch/microchip/uram_ar.ys
index cbaea647ff4..68e76897a31 100644
--- a/tests/arch/microchip/uram_ar/uram_ar.ys
+++ b/tests/arch/microchip/uram_ar.ys
@@ -18,4 +18,5 @@ read_verilog uram_ar.v
 
 synth_microchip -top uram_ar -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr uram_ar.vm
+select -assert-count 1 t:RAM64x12
+select -assert-none t:RAM64x12 %% t:* %D
diff --git a/tests/arch/microchip/uram_sr/uram_sr.v b/tests/arch/microchip/uram_sr.v
similarity index 100%
rename from tests/arch/microchip/uram_sr/uram_sr.v
rename to tests/arch/microchip/uram_sr.v
diff --git a/tests/arch/microchip/uram_sr/uram_sr.ys b/tests/arch/microchip/uram_sr.ys
similarity index 92%
rename from tests/arch/microchip/uram_sr/uram_sr.ys
rename to tests/arch/microchip/uram_sr.ys
index 7708fb39ff7..842d8362773 100644
--- a/tests/arch/microchip/uram_sr/uram_sr.ys
+++ b/tests/arch/microchip/uram_sr.ys
@@ -18,4 +18,5 @@ read_verilog uram_sr.v
 
 synth_microchip -top uram_sr -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr uram_sr.vm
+select -assert-count 1 t:RAM64x12
+select -assert-none t:RAM64x12 %% t:* %D
diff --git a/tests/arch/microchip/widemux/widemux.v b/tests/arch/microchip/widemux.v
similarity index 82%
rename from tests/arch/microchip/widemux/widemux.v
rename to tests/arch/microchip/widemux.v
index e25c7df16b5..74e3fd7fc58 100644
--- a/tests/arch/microchip/widemux/widemux.v
+++ b/tests/arch/microchip/widemux.v
@@ -23,25 +23,8 @@ module widemux(
 	output Y
 
 );
+assign Y = S1 ? (S0 ? data[3] : data[1]) : (S0 ? data[2] : data[0]);
 
-wire A, B;
-
-always @ (*) begin 
-		if (S0)begin
-		A = data[1];
-		B = data[3];
-		end else begin 
-		A = data[0];
-		B = data[2];
-	end
-
-	if (S1)begin
-		Y = A;
-	end else begin
-		Y = B;
-	end
-
-end
 endmodule
 
 
diff --git a/tests/arch/microchip/widemux/widemux.ys b/tests/arch/microchip/widemux.ys
similarity index 93%
rename from tests/arch/microchip/widemux/widemux.ys
rename to tests/arch/microchip/widemux.ys
index 8ef3a92308f..adb7e00bce3 100644
--- a/tests/arch/microchip/widemux/widemux.ys
+++ b/tests/arch/microchip/widemux.ys
@@ -18,4 +18,5 @@ read_verilog widemux.v
 
 synth_microchip -top widemux -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr widemux.vm
+select -assert-count 1 t:MX4
+select -assert-none t:MX4 %% t:* %D
\ No newline at end of file

From 9de5602574cadc7a362134a9444a69646134e29b Mon Sep 17 00:00:00 2001
From: chunlin min <chunlin.min@microchip.com>
Date: Thu, 4 Jul 2024 15:54:59 -0400
Subject: [PATCH 192/499] ininclude microchip tests in makefile

---
 Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Makefile b/Makefile
index 313de44d56d..f40f0d6a515 100644
--- a/Makefile
+++ b/Makefile
@@ -863,6 +863,7 @@ endif
 	+cd tests/arch/quicklogic/pp3 && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/quicklogic/qlf_k6n10f && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/gatemate && bash run-test.sh $(SEEDOPT)
+	+cd tests/arch/microchip && bash run-test.sh $(SEEDOPT)
 	+cd tests/rpc && bash run-test.sh
 	+cd tests/memfile && bash run-test.sh
 	+cd tests/verilog && bash run-test.sh

From 6fe0e00050506db886f32af31539ffd8c09a5ab6 Mon Sep 17 00:00:00 2001
From: Tony Min <170435972+tony-min-1@users.noreply.github.com>
Date: Thu, 4 Jul 2024 16:39:10 -0400
Subject: [PATCH 193/499] Add missing u sram init (#3)

add missing INIT for uSRAM
---
 techlibs/microchip/brams_defs.vh | 21 +++++++++++++++++++++
 techlibs/microchip/cells_sim.v   | 13 +++++++++++++
 techlibs/microchip/uSRAM_map.v   | 12 ++++++++++--
 tests/arch/microchip/uram_sr.v   | 32 ++++++++++++++++++++------------
 4 files changed, 64 insertions(+), 14 deletions(-)

diff --git a/techlibs/microchip/brams_defs.vh b/techlibs/microchip/brams_defs.vh
index 157945fdb9d..e02d2a83db1 100644
--- a/techlibs/microchip/brams_defs.vh
+++ b/techlibs/microchip/brams_defs.vh
@@ -38,6 +38,20 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 	.INIT18(slice_init_LSRAM(18)), \
 	.INIT19(slice_init_LSRAM(19))
 
+`define PARAMS_INIT_uSRAM \
+	.INIT0(slice_init_uSRAM(00)), \
+	.INIT1(slice_init_uSRAM(01)), \
+	.INIT2(slice_init_uSRAM(02)), \
+	.INIT3(slice_init_uSRAM(03)), \
+	.INIT4(slice_init_uSRAM(04)), \
+	.INIT5(slice_init_uSRAM(05)), \
+	.INIT6(slice_init_uSRAM(06)), \
+	.INIT7(slice_init_uSRAM(07)), \
+	.INIT8(slice_init_uSRAM(08)), \
+	.INIT9(slice_init_uSRAM(09)), \
+	.INIT10(slice_init_uSRAM(10)), \
+	.INIT11(slice_init_uSRAM(11)) \
+
 // Helper function for initializing the LSRAM
 function [1023:0] slice_init_LSRAM;
 	input integer slice_idx;
@@ -46,3 +60,10 @@ function [1023:0] slice_init_LSRAM;
 		slice_init_LSRAM[i] = INIT[(slice_idx * 1024 + i)];
 endfunction
 
+// Helper function for initializing the uSRAM
+function [63:0] slice_init_uSRAM;
+	input integer slice_idx;
+	integer i;
+	for (i = 0; i < 64; i = i + 1)
+		slice_init_uSRAM[i] = INIT[(slice_idx * 64 + i)];
+endfunction
\ No newline at end of file
diff --git a/techlibs/microchip/cells_sim.v b/techlibs/microchip/cells_sim.v
index f3b55fe4c70..eb06a0e698c 100644
--- a/techlibs/microchip/cells_sim.v
+++ b/techlibs/microchip/cells_sim.v
@@ -847,4 +847,17 @@ module RAM64x12 (
 	input		BUSY_FB,
 	output		ACCESS_BUSY
 );
+parameter INIT0 = 64'h0;
+parameter INIT1 = 64'h0;
+parameter INIT2 = 64'h0;
+parameter INIT3 = 64'h0;
+parameter INIT4 = 64'h0;
+parameter INIT5 = 64'h0;
+parameter INIT6 = 64'h0;
+parameter INIT7 = 64'h0;
+parameter INIT8 = 64'h0;
+parameter INIT9 = 64'h0;
+parameter INIT10 = 64'h0;
+parameter INIT11 = 64'h0;
+
 endmodule
\ No newline at end of file
diff --git a/techlibs/microchip/uSRAM_map.v b/techlibs/microchip/uSRAM_map.v
index 242b027a9c5..5750a780f33 100644
--- a/techlibs/microchip/uSRAM_map.v
+++ b/techlibs/microchip/uSRAM_map.v
@@ -38,7 +38,11 @@ input PORT_W_WR_EN;
 input [ADDR_BITS-1:0] PORT_R_ADDR;
 output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
 
-RAM64x12 _TECHMAP_REPLACE_ (
+`include "brams_defs.vh"
+
+RAM64x12 #(
+	`PARAMS_INIT_uSRAM
+) _TECHMAP_REPLACE_ (
 	.R_ADDR(PORT_R_ADDR),
 	.R_ADDR_BYPASS(1'b1),
 	.R_ADDR_EN(1'b0),
@@ -88,7 +92,11 @@ input PORT_R_RD_EN;
 input [ADDR_BITS-1:0] PORT_R_ADDR;
 output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
 
-RAM64x12 _TECHMAP_REPLACE_ (
+`include "brams_defs.vh"
+
+RAM64x12 #(
+	`PARAMS_INIT_uSRAM
+) _TECHMAP_REPLACE_ (
 	.R_CLK(PORT_R_CLK),
 	.R_ADDR(PORT_R_ADDR),
 	.R_ADDR_BYPASS(1'b0),
diff --git a/tests/arch/microchip/uram_sr.v b/tests/arch/microchip/uram_sr.v
index 1852dfc6890..7bab189fe48 100644
--- a/tests/arch/microchip/uram_sr.v
+++ b/tests/arch/microchip/uram_sr.v
@@ -17,16 +17,24 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 module uram_sr(clk, wr, raddr, din, waddr, dout);
-input clk;
-input [11:0] din;
-input wr;
-input [5:0] waddr, raddr;
-output [11:0] dout;
-reg [5:0] raddr_reg;
-reg [11:0] mem [0:63];
-assign dout = mem[raddr_reg];
-always@(posedge clk) begin
-	raddr_reg <= raddr; if(wr)
-	mem[waddr]<= din;
-end
+	input clk;
+	input [11:0] din;
+	input wr;
+	input [5:0] waddr, raddr;
+	output [11:0] dout;
+	reg [5:0] raddr_reg;
+	reg [11:0] mem [0:63];
+	assign dout = mem[raddr_reg];
+
+	integer i;
+	initial begin
+		for (i = 0; i < 64; i = i + 1) begin
+			mem[i] = 12'hfff;
+		end
+	end
+
+	always@(posedge clk) begin
+		raddr_reg <= raddr; if(wr)
+		mem[waddr]<= din;
+	end
 endmodule
\ No newline at end of file

From 9d0bca97755c928b803ebfa0d70ec21c4977e631 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 6 Jul 2024 18:58:21 +1000
Subject: [PATCH 194/499] Gowin. Add an energy saving primitive

We add a BANDGAP primitive used to turn off power to OSC, PLL and other
things on some GOWIN chips.

We also mark this primitive and GSR as keep.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 techlibs/gowin/cells_sim.v   | 6 +++++-
 techlibs/gowin/cells_xtra.py | 2 +-
 techlibs/gowin/cells_xtra.v  | 4 ----
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index b268690803f..4c017e2ab04 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -867,8 +867,12 @@ module ODDRC(D0, D1, CLEAR, TX, CLK, Q0, Q1);
 	parameter INIT = 0;
 endmodule
 
+(* blackbox, keep *)
 module GSR (input GSRI);
-	wire GSRO = GSRI;
+endmodule
+
+(* blackbox, keep *)
+module BANDGAP (input BGEN);
 endmodule
 
 (* abc9_box, lib_whitebox *)
diff --git a/techlibs/gowin/cells_xtra.py b/techlibs/gowin/cells_xtra.py
index 4d117e428c3..224ece02f17 100644
--- a/techlibs/gowin/cells_xtra.py
+++ b/techlibs/gowin/cells_xtra.py
@@ -13,7 +13,7 @@ class State(Enum):
     IN_MODULE = auto()
     IN_PARAMETER = auto()
 
-_skip = { 'ALU', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DFFNCE',
+_skip = { 'ALU', 'BANDGAP', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DFFNCE',
           'DFFNE', 'DFFNP', 'DFFNPE', 'DFFNR', 'DFFNRE', 'DFFNS', 'DFFNSE',
           'DFFP', 'DFFPE', 'DFFR', 'DFFRE', 'DFFS', 'DFFSE', 'DP', 'DPX9',
           'ELVDS_OBUF', 'GND', 'GSR', 'IBUF', 'IDDR', 'IDDRC', 'IDES10',
diff --git a/techlibs/gowin/cells_xtra.v b/techlibs/gowin/cells_xtra.v
index 4b89b8098aa..639014dc107 100644
--- a/techlibs/gowin/cells_xtra.v
+++ b/techlibs/gowin/cells_xtra.v
@@ -1687,10 +1687,6 @@ endmodule
 module ADC (...);
 endmodule
 
-module BANDGAP (...);
-input BGEN;
-endmodule
-
 module CLKDIV2 (...);
 parameter GSREN = "false"; 
 input HCLKIN, RESETN;

From d41688f7d72c446c3dc158f52568317e2a56ed4b Mon Sep 17 00:00:00 2001
From: Tony Min <170435972+tony-min-1@users.noreply.github.com>
Date: Mon, 8 Jul 2024 10:57:16 -0400
Subject: [PATCH 195/499] Revisions (#4)

* area should be 1 for all LUTs

* clean up macros

* add log_assert to fail noisily when encountering oddly configured DFF

* clean help msg

* flatten set to true by default

* update

* merge mult tests

* remove redundant test

* move all dsp tests to single file and remove redundant tests

* update ram tests

* add more dff tests

* fix c++20 compile errors

* add option to dump verilog

* default to use abc9

* remove -abc9 option since its the default now

---------

Co-authored-by: tony <minchunlin@gmail.com>
---
 passes/pmgen/microchip_dsp.pmg         |   6 +-
 passes/pmgen/microchip_dsp_CREG.pmg    |   2 +-
 techlibs/microchip/cells_sim.v         | 150 +-----------------
 techlibs/microchip/microchip_dffopt.cc |   3 +
 techlibs/microchip/synth_microchip.cc  |  53 ++++---
 tests/arch/microchip/Registers.v       |  38 -----
 tests/arch/microchip/Registers.ys      |  24 ---
 tests/arch/microchip/carryout.v        |  34 ----
 tests/arch/microchip/carryout.ys       |  22 ---
 tests/arch/microchip/cascade.v         |  38 -----
 tests/arch/microchip/cascade.ys        |  22 ---
 tests/arch/microchip/dff.ys            |  76 +++++++++
 tests/arch/microchip/dff_opt.ys        |   2 +-
 tests/arch/microchip/dsp.ys            | 211 +++++++++++++++++++++++++
 tests/arch/microchip/full_dsp.v        |  30 ----
 tests/arch/microchip/full_dsp.ys       |  22 ---
 tests/arch/microchip/large_mult.v      |  25 ---
 tests/arch/microchip/large_mult.ys     |  23 ---
 tests/arch/microchip/mac.v             |  43 -----
 tests/arch/microchip/mac.ys            |  24 ---
 tests/arch/microchip/mult.ys           |  51 ++++++
 tests/arch/microchip/postAdd_mult.v    |  30 ----
 tests/arch/microchip/postAdd_mult.ys   |  22 ---
 tests/arch/microchip/post_adder.v      |  32 ----
 tests/arch/microchip/post_adder.ys     |  23 ---
 tests/arch/microchip/pre_adder_dsp.v   |  30 ----
 tests/arch/microchip/pre_adder_dsp.ys  |  22 ---
 tests/arch/microchip/ram_SDP.ys        |  12 +-
 tests/arch/microchip/ram_TDP.v         |  36 ++---
 tests/arch/microchip/ram_TDP.ys        |  14 +-
 tests/arch/microchip/reduce.ys         |   2 +-
 tests/arch/microchip/reg_c.v           | 122 --------------
 tests/arch/microchip/reg_c.ys          |  22 ---
 tests/arch/microchip/reg_test.v        |  97 ------------
 tests/arch/microchip/reg_test.ys       |  22 ---
 tests/arch/microchip/signed_mult.v     |  28 ----
 tests/arch/microchip/signed_mult.ys    |  22 ---
 tests/arch/microchip/simple_ram.v      |  37 -----
 tests/arch/microchip/simple_ram.ys     |  10 +-
 tests/arch/microchip/unsigned_mult.v   |  28 ----
 tests/arch/microchip/unsigned_mult.ys  |  22 ---
 tests/arch/microchip/uram_ar.ys        |   2 +-
 tests/arch/microchip/uram_sr.ys        |   2 +-
 tests/arch/microchip/widemux.ys        |  17 +-
 44 files changed, 435 insertions(+), 1118 deletions(-)
 delete mode 100644 tests/arch/microchip/Registers.v
 delete mode 100644 tests/arch/microchip/Registers.ys
 delete mode 100644 tests/arch/microchip/carryout.v
 delete mode 100644 tests/arch/microchip/carryout.ys
 delete mode 100644 tests/arch/microchip/cascade.v
 delete mode 100644 tests/arch/microchip/cascade.ys
 create mode 100644 tests/arch/microchip/dff.ys
 create mode 100644 tests/arch/microchip/dsp.ys
 delete mode 100644 tests/arch/microchip/full_dsp.v
 delete mode 100644 tests/arch/microchip/full_dsp.ys
 delete mode 100644 tests/arch/microchip/large_mult.v
 delete mode 100644 tests/arch/microchip/large_mult.ys
 delete mode 100644 tests/arch/microchip/mac.v
 delete mode 100644 tests/arch/microchip/mac.ys
 create mode 100644 tests/arch/microchip/mult.ys
 delete mode 100644 tests/arch/microchip/postAdd_mult.v
 delete mode 100644 tests/arch/microchip/postAdd_mult.ys
 delete mode 100644 tests/arch/microchip/post_adder.v
 delete mode 100644 tests/arch/microchip/post_adder.ys
 delete mode 100644 tests/arch/microchip/pre_adder_dsp.v
 delete mode 100644 tests/arch/microchip/pre_adder_dsp.ys
 delete mode 100644 tests/arch/microchip/reg_c.v
 delete mode 100644 tests/arch/microchip/reg_c.ys
 delete mode 100644 tests/arch/microchip/reg_test.v
 delete mode 100644 tests/arch/microchip/reg_test.ys
 delete mode 100755 tests/arch/microchip/signed_mult.v
 delete mode 100755 tests/arch/microchip/signed_mult.ys
 delete mode 100644 tests/arch/microchip/simple_ram.v
 delete mode 100644 tests/arch/microchip/unsigned_mult.v
 delete mode 100644 tests/arch/microchip/unsigned_mult.ys

diff --git a/passes/pmgen/microchip_dsp.pmg b/passes/pmgen/microchip_dsp.pmg
index 1c22bb317d7..9a6b9e1fa07 100644
--- a/passes/pmgen/microchip_dsp.pmg
+++ b/passes/pmgen/microchip_dsp.pmg
@@ -126,7 +126,7 @@ code sigA sigB sigD preAdderStatic moveBtoA
 			// sigA should be the input to the multiplier without the preAdd. sigB and sigD should be 
 			//the preAdd inputs. If our "A" input into the multiplier is from the preAdd (not sigA), then 
 			// we basically swap it.
-			sigA = port(dsp, \B);
+			sigA = sigB;
 		}
 
 		// port B of preAdderStatic must be mapped to port D of DSP for subtraction
@@ -368,7 +368,7 @@ match ff
 	filter !ff->type.in($adff, $adffe) || allowAsync
 
 	// clock must be consistent
-	filter clock == SigBit() || port(ff, \CLK) == clock
+	filter clock == SigBit() || port(ff, \CLK)[0] == clock
 endmatch
 
 code argQ
@@ -415,7 +415,7 @@ match ff
 	filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
 	filter port(ff, \D).extract(offset, GetSize(argD)) == argD
 
-	filter clock == SigBit() || port(ff, \CLK) == clock
+	filter clock == SigBit() || port(ff, \CLK)[0] == clock
 endmatch
 
 code argQ
diff --git a/passes/pmgen/microchip_dsp_CREG.pmg b/passes/pmgen/microchip_dsp_CREG.pmg
index baa5869620d..d1b15d460f5 100644
--- a/passes/pmgen/microchip_dsp_CREG.pmg
+++ b/passes/pmgen/microchip_dsp_CREG.pmg
@@ -145,7 +145,7 @@ match ff
 	filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
 	filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
 
-	filter clock == SigBit() || port(ff, \CLK) == clock
+	filter clock == SigBit() || port(ff, \CLK)[0] == clock
 endmatch
 
 code argQ
diff --git a/techlibs/microchip/cells_sim.v b/techlibs/microchip/cells_sim.v
index eb06a0e698c..de4e3607f2a 100644
--- a/techlibs/microchip/cells_sim.v
+++ b/techlibs/microchip/cells_sim.v
@@ -51,7 +51,7 @@ module CFG1 (
 	endspecify
 endmodule
 
-(* abc9_lut=2 *)
+(* abc9_lut=1 *)
 module CFG2 (
 	output Y,
 	input A,
@@ -65,7 +65,7 @@ module CFG2 (
 	endspecify
 endmodule
 
-(* abc9_lut=3 *)
+(* abc9_lut=1 *)
 module CFG3 (
 	output Y,
 	input A,
@@ -81,7 +81,7 @@ module CFG3 (
 	endspecify
 endmodule
 
-(* abc9_lut=3 *)
+(* abc9_lut=1 *)
 module CFG4 (
 	output Y,
 	input A,
@@ -291,13 +291,6 @@ module ARI1 (
 	endspecify
 endmodule
 
-// module FCEND_BUFF
-// module FCINIT_BUFF
-// module FLASH_FREEZE
-// module OSCILLATOR
-// module SYSCTRL_RESET_STATUS
-// module LIVE_PROBE_FB
-
 (* blackbox *)
 module GCLKBUF (
 	(* iopad_external_pin *)
@@ -320,28 +313,6 @@ module GCLKBUF_DIFF (
 );
 endmodule
 
-(* blackbox *)
-module GCLKBIBUF (
-	input D,
-	input E,
-	input EN,
-	(* iopad_external_pin *)
-	inout PAD,
-	(* clkbuf_driver *)
-	output Y
-);
-endmodule
-
-// module DFN1
-// module DFN1C0
-// module DFN1E1
-// module DFN1E1C0
-// module DFN1E1P0
-// module DFN1P0
-// module DLN1
-// module DLN1C0
-// module DLN1P0
-
 module INV (
 	input A,
 	output Y
@@ -588,121 +559,6 @@ module TRIBUFF_DIFF (
 	parameter IOSTD = "";
 endmodule
 
-// module DDR_IN
-// module DDR_OUT
-// module RAM1K18
-// module RAM64x18
-// module MACC
-
-(* blackbox *)
-module SYSRESET (
-	(* iopad_external_pin *)
-	input DEVRST_N,
-	output POWER_ON_RESET_N);
-endmodule
-
-
-(* blackbox *)
-module XTLOSC (
-	(* iopad_external_pin *)
-	input XTL,
-	output CLKOUT);
-	parameter [1:0] MODE = 2'h3;
-	parameter real FREQUENCY = 20.0;
-endmodule
-
-(* blackbox *)
-module RAM1K18 (
-	input [13:0] 	A_ADDR,
-	input [2:0] 	A_BLK,
-	(* clkbuf_sink *)
-	input			A_CLK,
-	input [17:0] 	A_DIN,
-	output [17:0]	A_DOUT,
-	input [1:0]		A_WEN,
-	input [2:0]		A_WIDTH,
-	input			A_WMODE,
-	input			A_ARST_N,
-	input			A_DOUT_LAT,
-	input			A_DOUT_ARST_N,
-	(* clkbuf_sink *)
-	input			A_DOUT_CLK,
-	input			A_DOUT_EN,
-	input			A_DOUT_SRST_N,
-
-	input [13:0]	B_ADDR,
-	input [2:0] 	B_BLK,
-	(* clkbuf_sink *)
-	input			B_CLK,
-	input [17:0] 	B_DIN,
-	output [17:0]	B_DOUT,
-	input [1:0]		B_WEN,
-	input [2:0]		B_WIDTH,
-	input			B_WMODE,
-	input			B_ARST_N,
-	input			B_DOUT_LAT,
-	input			B_DOUT_ARST_N,
-	(* clkbuf_sink *)
-	input			B_DOUT_CLK,
-	input			B_DOUT_EN,
-	input			B_DOUT_SRST_N,
-	input			A_EN,
-	input			B_EN,
-	input			SII_LOCK,
-	output			BUSY);
-endmodule
-
-(* blackbox *)
-module RAM64x18 (
-	input [9:0] 	A_ADDR,
-	input [1:0] 	A_BLK,
-	input [2:0] 	A_WIDTH,
-	output [17:0] 	A_DOUT,
-	input			A_DOUT_ARST_N,
-	(* clkbuf_sink *)
-	input	 		A_DOUT_CLK,
-	input	 		A_DOUT_EN,
-	input	 		A_DOUT_LAT,
-	input	 		A_DOUT_SRST_N,
-	(* clkbuf_sink *)
-	input			A_ADDR_CLK,
-	input	 		A_ADDR_EN,
-	input	 		A_ADDR_LAT,
-	input	 		A_ADDR_SRST_N,
-	input	 		A_ADDR_ARST_N,
-
-	input [9:0]		B_ADDR,
-	input [1:0]		B_BLK,
-	input [2:0]		B_WIDTH,
-	output [17:0] 	B_DOUT,
-	input			B_DOUT_ARST_N,
-	(* clkbuf_sink *)
-	input			B_DOUT_CLK,
-	input			B_DOUT_EN,
-	input			B_DOUT_LAT,
-	input			B_DOUT_SRST_N,
-	(* clkbuf_sink *)
-	input			B_ADDR_CLK,
-	input			B_ADDR_EN,
-	input			B_ADDR_LAT,
-	input			B_ADDR_SRST_N,
-	input			B_ADDR_ARST_N,
-
-	input [9:0]		C_ADDR,
-	(* clkbuf_sink *)
-	input			C_CLK,
-	input [17:0]	C_DIN,
-	input			C_WEN,
-	input [1:0]		C_BLK,
-	input [2:0]		C_WIDTH,
-
-	input			A_EN,
-	input			B_EN,
-	input			C_EN,
-	input			SII_LOCK,
-	output			BUSY);
-endmodule
-
 (* blackbox *)
 module MACC_PA (
 	input DOTP,
diff --git a/techlibs/microchip/microchip_dffopt.cc b/techlibs/microchip/microchip_dffopt.cc
index 4193eb469e7..62450ab6e04 100644
--- a/techlibs/microchip/microchip_dffopt.cc
+++ b/techlibs/microchip/microchip_dffopt.cc
@@ -218,6 +218,7 @@ struct MicrochipDffOptPass : public Pass {
 						worthy_post_ce = true;
 				} else if (sig_CE.data != State::S1) {
 					// Strange.  Should not happen in a reasonable flow, so bail.
+					log_assert(false); // This DFF is always off
 					continue;
 				} else {
 					lut_d_post_ce = lut_d;
@@ -241,6 +242,7 @@ struct MicrochipDffOptPass : public Pass {
 							worthy_post_s = true;
 					} else if (sig_S.data != (inv_s ? State::S1 : State::S0)) {
 						// Strange.  Should not happen in a reasonable flow, so bail.
+						log_assert(false); // DFF is always in set mode
 						continue;
 					}
 				}
@@ -263,6 +265,7 @@ struct MicrochipDffOptPass : public Pass {
 							worthy_post_r = true;
 					} else if (sig_R.data != (inv_r ? State::S1 : State::S0)) {
 						// Strange.  Should not happen in a reasonable flow, so bail.
+						log_assert(false); // DFF is always in reset mode
 						continue;
 					}
 				}
diff --git a/techlibs/microchip/synth_microchip.cc b/techlibs/microchip/synth_microchip.cc
index 9b7adae1bfe..2da4c4000c7 100644
--- a/techlibs/microchip/synth_microchip.cc
+++ b/techlibs/microchip/synth_microchip.cc
@@ -33,10 +33,8 @@ struct SynthMicrochipPass : public ScriptPass {
 		log("\n");
 		log("    synth_microchip [options]\n");
 		log("\n");
-		log("This command runs synthesis for Microchip FPGAs. Operating on\n");
-		log("partly selected designs is not supported (you must submit a fully-selected \n");
-		log("design). This command creates netlists that are compatible with Microchip \n");
-		log("PolarFire devices.\n");
+		log("This command runs synthesis for Microchip FPGAs. This command creates \n");
+		log("netlists that are compatible with Microchip PolarFire devices. \n");
 		log("\n");
 		log("    -top <module>\n");
 		log("        use the specified module as the top module\n");
@@ -55,6 +53,9 @@ struct SynthMicrochipPass : public ScriptPass {
 		log("        Write the design to the specified BLIF file. Writing of an output file\n");
 		log("        is omitted if this parameter is not specified.\n");
 		log("\n");
+		log("    -vlog <file>\n");
+		log("        write the design to the specified Verilog file. writing of an output\n");
+		log("        file is omitted if this parameter is not specified.\n");
 		log("    -nobram\n");
 		log("        Do not use block RAM cells in output netlist\n");
 		log("\n");
@@ -76,11 +77,8 @@ struct SynthMicrochipPass : public ScriptPass {
 		log("        'from_label' is synonymous to 'begin', and empty 'to_label' is\n");
 		log("        synonymous to the end of the command list.\n");
 		log("\n");
-		log("    -flatten\n");
-		log("        Flatten design before synthesis.\n");
-		log("\n");
-		log("    -flatten_before_abc\n");
-		log("        Flatten design before abc tech mapping.\n");
+		log("    -noflatten\n");
+		log("        do not flatten design before synthesis\n");
 		log("\n");
 		log("    -dff\n");
 		log("        Run 'abc'/'abc9' with -dff option\n");
@@ -89,8 +87,8 @@ struct SynthMicrochipPass : public ScriptPass {
 		log("        Run 'abc' with '-D 1' option to enable flip-flop retiming.\n");
 		log("        implies -dff.\n");
 		log("\n");
-		log("    -abc9\n");
-		log("        Use new ABC9 flow (EXPERIMENTAL)\n");
+		log("    -abc\n");
+		log("        Use classic ABC flow instead of ABC9\n");
 		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
@@ -98,10 +96,9 @@ struct SynthMicrochipPass : public ScriptPass {
 		log("\n");
 	}
 
-	std::string top_opt, edif_file, blif_file, family;
+	std::string top_opt, edif_file, blif_file, vlog_file, family;
 	bool flatten, retime, noiopad, noclkbuf, nobram, nocarry, nowidelut, nodsp;
 	bool abc9, dff;
-	bool flatten_before_abc;
 	int lut_size;
 
 	// debug dump switches
@@ -112,8 +109,9 @@ struct SynthMicrochipPass : public ScriptPass {
 		top_opt = "-auto-top";
 		edif_file.clear();
 		blif_file.clear();
+		vlog_file.clear();
 		family = "polarfire";
-		flatten = false;
+		flatten = true;
 		retime = false;
 		noiopad = false;
 		noclkbuf = false;
@@ -121,9 +119,8 @@ struct SynthMicrochipPass : public ScriptPass {
 		nobram = false;
 		nowidelut = false;
 		nodsp = false;
-		abc9 = false;
+		abc9 = true;
 		dff = false;
-		flatten_before_abc = false;
 		lut_size = 4;
 
 		debug_memory = false;
@@ -153,6 +150,10 @@ struct SynthMicrochipPass : public ScriptPass {
 				blif_file = args[++argidx];
 				continue;
 			}
+			if (args[argidx] == "-vlog" && argidx + 1 < args.size()) {
+				vlog_file = args[++argidx];
+				continue;
+			}
 			if (args[argidx] == "-run" && argidx + 1 < args.size()) {
 				size_t pos = args[argidx + 1].find(':');
 				if (pos == std::string::npos)
@@ -161,12 +162,8 @@ struct SynthMicrochipPass : public ScriptPass {
 				run_to = args[argidx].substr(pos + 1);
 				continue;
 			}
-			if (args[argidx] == "-flatten") {
-				flatten = true;
-				continue;
-			}
-			if (args[argidx] == "-flatten_before_abc") {
-				flatten_before_abc = true;
+			if (args[argidx] == "-noflatten") {
+				flatten = false;
 				continue;
 			}
 			if (args[argidx] == "-retime") {
@@ -201,8 +198,8 @@ struct SynthMicrochipPass : public ScriptPass {
 				nobram = true;
 				continue;
 			}
-			if (args[argidx] == "-abc9") {
-				abc9 = true;
+			if (args[argidx] == "-abc") {
+				abc9 = false;
 				continue;
 			}
 			if (args[argidx] == "-nodsp") {
@@ -479,8 +476,6 @@ struct SynthMicrochipPass : public ScriptPass {
 
 		if (check_label("map_luts")) {
 			run("opt_expr -mux_undef -noclkinv");
-			if (flatten_before_abc)
-				run("flatten");
 			if (help_mode)
 				run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')");
 			else if (abc9) {
@@ -535,6 +530,12 @@ struct SynthMicrochipPass : public ScriptPass {
 			if (!blif_file.empty() || help_mode)
 				run(stringf("write_blif %s", blif_file.c_str()));
 		}
+
+		if (check_label("vlog"))
+		{
+			if (!vlog_file.empty() || help_mode)
+				run(stringf("write_verilog %s", help_mode ? "<file-name>" : vlog_file.c_str()));
+		}
 	}
 } SynthMicrochipPass;
 
diff --git a/tests/arch/microchip/Registers.v b/tests/arch/microchip/Registers.v
deleted file mode 100644
index 160c09cc736..00000000000
--- a/tests/arch/microchip/Registers.v
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module Registers(
-	input clk,
-	input en,
-	input rst,
-	input D,
-	output reg Q
-);
-parameter LOAD_DATA = 1;
-
-// active low async reset
-always @(posedge clk, negedge rst) begin
-	if (rst == 0) begin
-		Q <= LOAD_DATA;
-	end else if(en) begin
-		Q <= D;
-	end
-end
-
-
-endmodule
\ No newline at end of file
diff --git a/tests/arch/microchip/Registers.ys b/tests/arch/microchip/Registers.ys
deleted file mode 100644
index bbf7a6c912f..00000000000
--- a/tests/arch/microchip/Registers.ys
+++ /dev/null
@@ -1,24 +0,0 @@
-# ISC License
-# 
-# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
-# Permission to use, copy, modify, and/or distribute this software for any
-# purpose with or without fee is hereby granted, provided that the above
-# copyright notice and this permission notice appear in all copies.
-# 
-# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-
-# read verilog files
-read_verilog Registers.v
-
-synth_microchip -top Registers -abc9 -family polarfire -noiopad
-
-select -assert-count 1 t:SLE
-select -assert-count 1 t:CLKBUF
-select -assert-none t:SLE t:CLKBUF %% t:* %D
diff --git a/tests/arch/microchip/carryout.v b/tests/arch/microchip/carryout.v
deleted file mode 100644
index 8da139774f3..00000000000
--- a/tests/arch/microchip/carryout.v
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module carryout (cout,out,a, b,c);
-parameter n = 6;
-parameter k = 2;
-output reg [k*(n+1)-1:0] out;
-output reg cout;
-input [n:0] a;
-input [n:0] b;
-input [n-1:0] c;
-
-	always @(a,b,c) 
-	begin
-		{cout,out} = a * b + c;
-		
-	end
-
-endmodule
diff --git a/tests/arch/microchip/carryout.ys b/tests/arch/microchip/carryout.ys
deleted file mode 100644
index 7c79dfba38f..00000000000
--- a/tests/arch/microchip/carryout.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-# ISC License
-# 
-# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
-# Permission to use, copy, modify, and/or distribute this software for any
-# purpose with or without fee is hereby granted, provided that the above
-# copyright notice and this permission notice appear in all copies.
-# 
-# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-
-read_verilog carryout.v
-
-synth_microchip -top carryout -abc9 -family polarfire -noiopad
-
-select -assert-count 1 t:MACC_PA
-select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/cascade.v b/tests/arch/microchip/cascade.v
deleted file mode 100644
index 19dbac9dd8c..00000000000
--- a/tests/arch/microchip/cascade.v
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module cascade(
-	input signed [5:0] in_A,
-	input signed [4:0] in_B,
-	input signed [4:0] in_D,
-	output signed [11:0] out_P,
-
-	input signed [4:0] casA,
-	input signed [4:0] casB
-
-);
-
-wire signed [9:0] cascade;
-// first dsp
-assign cascade = casA * casB;
-
-// second dsp
-assign out_P = in_A * (in_B + in_D) + cascade;
-
-
-endmodule
diff --git a/tests/arch/microchip/cascade.ys b/tests/arch/microchip/cascade.ys
deleted file mode 100644
index 7248c562594..00000000000
--- a/tests/arch/microchip/cascade.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-# ISC License
-# 
-# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
-# Permission to use, copy, modify, and/or distribute this software for any
-# purpose with or without fee is hereby granted, provided that the above
-# copyright notice and this permission notice appear in all copies.
-# 
-# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-
-read_verilog cascade.v
-
-synth_microchip -top cascade -abc9 -family polarfire -noiopad
-
-select -assert-count 2 t:MACC_PA
-select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/dff.ys b/tests/arch/microchip/dff.ys
new file mode 100644
index 00000000000..ee377bb4028
--- /dev/null
+++ b/tests/arch/microchip/dff.ys
@@ -0,0 +1,76 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+
+# active low async reset with enable
+read_verilog <<EOT
+module top(
+	input clk,
+	input en,
+	input rst,
+	input D,
+	output reg Q
+);
+always @(posedge clk, negedge rst) begin
+	if (rst == 0) begin
+		Q <= 1;
+	end else if(en) begin
+		Q <= D;
+	end
+end
+endmodule
+EOT
+synth_microchip -top top -family polarfire -noiopad
+select -assert-count 1 t:SLE
+select -assert-count 1 t:CLKBUF
+select -assert-none t:SLE t:CLKBUF %% t:* %D
+
+design -reset
+read_verilog -D NO_INIT ../common/dffs.v
+synth_microchip -top dff -family polarfire -noiopad
+select -assert-count 1 t:SLE
+select -assert-count 1 t:CLKBUF
+select -assert-none t:SLE t:CLKBUF %% t:* %D
+
+design -reset
+read_verilog -D NO_INIT ../common/dffs.v
+synth_microchip -top dffe -family polarfire -noiopad
+select -assert-count 1 t:SLE
+select -assert-count 1 t:CLKBUF
+select -assert-none t:SLE t:CLKBUF %% t:* %D
+
+design -reset
+read_verilog -D NO_INIT ../common/adffs.v
+synth_microchip -top adff -family polarfire -noiopad
+select -assert-count 1 t:SLE
+select -assert-count 1 t:CLKBUF
+select -assert-count 1 t:CFG1
+select -assert-none t:SLE t:CLKBUF t:CFG1 %% t:* %D
+
+design -reset
+read_verilog -D NO_INIT ../common/adffs.v
+synth_microchip -top adffn -family polarfire -noiopad
+select -assert-count 1 t:SLE
+select -assert-count 1 t:CLKBUF
+select -assert-none t:SLE t:CLKBUF %% t:* %D
+
+design -reset
+read_verilog -D NO_INIT ../common/adffs.v
+synth_microchip -top dffs -family polarfire -noiopad
+select -assert-count 1 t:SLE
+select -assert-count 1 t:CLKBUF
+select -assert-count 1 t:CFG1
+select -assert-none t:SLE t:CLKBUF t:CFG1 %% t:* %D
\ No newline at end of file
diff --git a/tests/arch/microchip/dff_opt.ys b/tests/arch/microchip/dff_opt.ys
index f159ad864f4..3c3125d6242 100644
--- a/tests/arch/microchip/dff_opt.ys
+++ b/tests/arch/microchip/dff_opt.ys
@@ -16,7 +16,7 @@
 
 read_verilog dff_opt.v 
 
-synth_microchip -top dff_opt -abc9 -family polarfire -noiopad
+synth_microchip -top dff_opt -family polarfire -noiopad
 
 select -assert-count 1 t:SLE
 select -assert-count 1 t:CFG4
diff --git a/tests/arch/microchip/dsp.ys b/tests/arch/microchip/dsp.ys
new file mode 100644
index 00000000000..b02ad624a4a
--- /dev/null
+++ b/tests/arch/microchip/dsp.ys
@@ -0,0 +1,211 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+# pre-adder
+design -reset
+read_verilog <<EOT
+module pre_adder(
+	input signed [5:0] in_A,
+	input signed [4:0] in_B,
+	input signed [4:0] in_D,
+	output [11:0] out_Y
+);
+    assign out_Y = in_A * (in_B + in_D);
+endmodule
+EOT
+synth_microchip -top pre_adder -family polarfire -noiopad
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
+
+# post-adder
+design -reset
+read_verilog <<EOT
+module post_adder(
+	input signed[17:0] in_A,
+	input signed [17:0] in_B,
+	input signed [17:0] in_C,
+	output signed [35:0] out_Y
+);
+    assign out_Y = (in_B*in_A)+in_C;
+endmodule
+EOT
+synth_microchip -top post_adder -family polarfire -noiopad
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
+
+# pre-adder + post-adder
+design -reset
+read_verilog <<EOT
+module pre_post_adder(
+	input signed[5:0] in_A,
+	input signed [4:0] in_B,
+	input signed [11:0] in_C,
+	input signed [4:0] in_D,
+	output signed [12:0] out_Y
+);
+assign out_Y = ((in_D + in_B)*in_A)+in_C;
+endmodule
+EOT
+synth_microchip -top pre_post_adder -family polarfire -noiopad
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
+
+
+# multiply accumulate
+design -reset
+read_verilog <<EOT
+module mac(
+	input clk,
+	input signed [4:0] in_A,
+	input signed [4:0] in_B,
+	input signed [4:0] in_D,
+	input srst_P,
+	output reg signed [11:0] out_P
+);
+	always@(posedge clk) begin
+		if (~srst_P) begin
+			out_P <= 12'h000;
+		end else begin
+			out_P <= in_A * (in_B + in_D) + out_P;
+		end
+	end
+endmodule
+EOT
+synth_microchip -top mac -family polarfire -noiopad
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
+
+
+# cascade
+design -reset
+read_verilog <<EOT
+module cas(
+	input signed [5:0] in_A,
+	input signed [4:0] in_B,
+	input signed [4:0] in_D,
+	input signed [4:0] casA,
+	input signed [4:0] casB,
+	output signed [11:0] out_P
+);
+	wire signed [9:0] cascade;
+	assign cascade = casA * casB;
+	assign out_P = in_A * (in_B + in_D) + cascade;
+endmodule
+EOT
+synth_microchip -top cas -family polarfire -noiopad
+select -assert-count 2 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
+
+# carryout
+design -reset
+read_verilog <<EOT
+module carryout (cout,out,a, b,c);
+parameter n = 6;
+parameter k = 2;
+output reg [k*(n+1)-1:0] out;
+output reg cout;
+input [n:0] a;
+input [n:0] b;
+input [n-1:0] c;
+	always @(*) 
+	begin
+		{cout,out} = a * b + c;
+	end
+endmodule
+EOT
+synth_microchip -top carryout -family polarfire -noiopad
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
+
+# pipeline registers
+design -reset
+read_verilog <<EOT
+module pipeline(
+	input clk,
+	input srst_A,
+	input srst_B,
+	input srst_D,
+	input srst_P,
+	input arst_D,
+	input srst_C,
+	input signed [5:0] in_A,
+	input signed [4:0] in_B,
+	input signed [4:0] in_C,
+	input signed [4:0] in_D,
+	output reg [11:0] out_P
+);
+wire srst_A_N;
+wire srst_B_N;
+wire srst_C_N;
+wire srst_D_N;
+wire srst_P_N;
+assign srst_A_N = ~srst_A;
+assign srst_B_N = ~srst_B;
+assign srst_C_N = ~srst_C;
+assign srst_D_N = ~srst_D;
+assign srst_P_N = ~srst_P;
+
+reg signed [5:0] reg_A;
+reg signed [4:0] reg_B;
+reg signed [4:0] reg_C;
+reg signed [4:0] reg_D;
+
+always@(posedge clk) begin // sync reset A
+	// if (~srst_A_N) begin
+	if (srst_A_N) begin
+		reg_A = 6'b000000;
+	end else begin
+		reg_A = in_A;
+	end
+end
+
+always@(posedge clk) begin // sync reset B
+	if (srst_B_N) begin
+		reg_B = 5'b00000;
+	end else begin
+		reg_B = in_B;
+	end
+end
+
+always@(posedge clk, negedge arst_D) begin // async reset D
+	if (~arst_D) begin
+		reg_D = 5'b00000;
+	end else begin
+		reg_D = in_D;
+	end
+end
+
+always@(posedge clk) begin // sync reset C
+	if (srst_C_N) begin
+		reg_C = 5'b00000;
+	end else begin
+		reg_C = in_C;
+	end
+end
+
+// sync reset P
+always@(posedge clk) begin
+	if (srst_P_N) begin
+		out_P = 12'h000;
+	end else begin
+		out_P = reg_A * (reg_B + reg_D) + reg_C;
+	end
+end
+endmodule
+EOT
+synth_microchip -top pipeline -family polarfire -noiopad
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/full_dsp.v b/tests/arch/microchip/full_dsp.v
deleted file mode 100644
index ead82b57322..00000000000
--- a/tests/arch/microchip/full_dsp.v
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-module full_dsp(
-	input signed[5:0] in_A,
-	input signed [4:0] in_B,
-	input signed [11:0] in_C,
-	input signed [4:0] in_D,
-
-	output signed [12:0] out_Y
-);
-
-assign out_Y = ((in_D + in_B)*in_A)+in_C;
-
-
-endmodule
\ No newline at end of file
diff --git a/tests/arch/microchip/full_dsp.ys b/tests/arch/microchip/full_dsp.ys
deleted file mode 100644
index 9fce46a38bb..00000000000
--- a/tests/arch/microchip/full_dsp.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-# ISC License
-# 
-# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
-# Permission to use, copy, modify, and/or distribute this software for any
-# purpose with or without fee is hereby granted, provided that the above
-# copyright notice and this permission notice appear in all copies.
-# 
-# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-
-read_verilog full_dsp.v
-
-synth_microchip -top full_dsp -abc9 -family polarfire -noiopad
-
-select -assert-count 1 t:MACC_PA
-select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/large_mult.v b/tests/arch/microchip/large_mult.v
deleted file mode 100644
index 8f861f37fa6..00000000000
--- a/tests/arch/microchip/large_mult.v
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module large_mult(
-	input signed [20:0] in1,
-	input signed [17:0] in2,
-	output signed [38:0] out1
-);
-assign out1 = in1 * in2;
-endmodule
\ No newline at end of file
diff --git a/tests/arch/microchip/large_mult.ys b/tests/arch/microchip/large_mult.ys
deleted file mode 100644
index b76e5576af2..00000000000
--- a/tests/arch/microchip/large_mult.ys
+++ /dev/null
@@ -1,23 +0,0 @@
-# ISC License
-# 
-# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
-# Permission to use, copy, modify, and/or distribute this software for any
-# purpose with or without fee is hereby granted, provided that the above
-# copyright notice and this permission notice appear in all copies.
-# 
-# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-
-read_verilog large_mult.v
-
-synth_microchip -top large_mult -abc9 -family polarfire -noiopad
-
-select -assert-count 2 t:MACC_PA
-select -assert-none t:MACC_PA %% t:* %D
-
diff --git a/tests/arch/microchip/mac.v b/tests/arch/microchip/mac.v
deleted file mode 100644
index 855cf97aaa9..00000000000
--- a/tests/arch/microchip/mac.v
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module mac(
-	input clk,
-	input signed [4:0] in_A,
-	input signed [4:0] in_B,
-	input signed [4:0] in_D,
-	output reg signed [11:0] out_P,
-
-	input srst_P,
-
-	input signed [4:0] casA,
-	input signed [4:0] casB
-
-);
-
-
-// sync reset P
-always@(posedge clk) begin
-	if (~srst_P) begin
-		out_P <= 12'h000;
-	end else begin
-		out_P <= in_A * (in_B + in_D) + out_P;
-	end
-end
-
-endmodule
\ No newline at end of file
diff --git a/tests/arch/microchip/mac.ys b/tests/arch/microchip/mac.ys
deleted file mode 100644
index 69352354743..00000000000
--- a/tests/arch/microchip/mac.ys
+++ /dev/null
@@ -1,24 +0,0 @@
-# ISC License
-# 
-# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
-# Permission to use, copy, modify, and/or distribute this software for any
-# purpose with or without fee is hereby granted, provided that the above
-# copyright notice and this permission notice appear in all copies.
-# 
-# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-
-# read verilog files
-read_verilog mac.v
-
-# run the synth flow, specifies top module and additional parameters
-synth_microchip -top mac -abc9 -family polarfire -noiopad
-
-select -assert-count 1 t:MACC_PA
-select -assert-none t:MACC_PA %% t:* %D
\ No newline at end of file
diff --git a/tests/arch/microchip/mult.ys b/tests/arch/microchip/mult.ys
new file mode 100644
index 00000000000..7a82e52ecb2
--- /dev/null
+++ b/tests/arch/microchip/mult.ys
@@ -0,0 +1,51 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+# regular unsigned multiply
+read_verilog ../common/mul.v
+chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
+hierarchy -top top
+proc
+synth_microchip -family polarfire -noiopad
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
+
+# regular signed multiply
+design -reset
+read_verilog <<EOT
+module signed_mult(
+	input signed [17:0] in_A,
+	input signed [17:0] in_B,
+	output signed [35:0] out_Y
+);
+assign out_Y = in_A * in_B;
+endmodule
+EOT
+synth_microchip -top signed_mult -family polarfire -noiopad
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
+
+# wide multiply
+design -reset
+read_verilog ../common/mul.v
+chparam -set X_WIDTH 30 -set Y_WIDTH 16 -set A_WIDTH 46
+hierarchy -top top
+proc
+synth_microchip -family polarfire -noiopad
+cd top # Constrain all select calls below inside the top module
+select -assert-count 2 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/postAdd_mult.v b/tests/arch/microchip/postAdd_mult.v
deleted file mode 100644
index 666ac8ffcb2..00000000000
--- a/tests/arch/microchip/postAdd_mult.v
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module postAdd_mult(
-	input signed[17:0] in_A,
-	input signed [17:0] in_B,
-	input signed [17:0] in_C,
-
-	output signed [35:0] out_Y
-);
-
-assign out_Y = (in_B*in_A)+in_C;
-
-
-endmodule
\ No newline at end of file
diff --git a/tests/arch/microchip/postAdd_mult.ys b/tests/arch/microchip/postAdd_mult.ys
deleted file mode 100644
index 7d0a4bf0224..00000000000
--- a/tests/arch/microchip/postAdd_mult.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-# ISC License
-# 
-# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
-# Permission to use, copy, modify, and/or distribute this software for any
-# purpose with or without fee is hereby granted, provided that the above
-# copyright notice and this permission notice appear in all copies.
-# 
-# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-
-read_verilog postAdd_mult.v
-
-synth_microchip -top postAdd_mult -abc9 -family polarfire -noiopad
-
-select -assert-count 1 t:MACC_PA
-select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/post_adder.v b/tests/arch/microchip/post_adder.v
deleted file mode 100644
index 93c339d7e27..00000000000
--- a/tests/arch/microchip/post_adder.v
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module post_adder(
-	input signed [5:0] in_A,
-	input signed [4:0] in_B,
-	input signed [4:0] in_D,
-	input signed [11:0] in_C,
-
-	output [12:0] out_Y
-);
-
-assign out_Y = (in_D + in_B) * in_A + in_C;
-
-
-
-endmodule
\ No newline at end of file
diff --git a/tests/arch/microchip/post_adder.ys b/tests/arch/microchip/post_adder.ys
deleted file mode 100644
index 196215cac3e..00000000000
--- a/tests/arch/microchip/post_adder.ys
+++ /dev/null
@@ -1,23 +0,0 @@
-# ISC License
-# 
-# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
-# Permission to use, copy, modify, and/or distribute this software for any
-# purpose with or without fee is hereby granted, provided that the above
-# copyright notice and this permission notice appear in all copies.
-# 
-# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-
-read_verilog post_adder.v
-
-synth_microchip -top post_adder -abc9 -family polarfire -noiopad
-
-select -assert-count 1 t:MACC_PA
-select -assert-none t:MACC_PA %% t:* %D
-
diff --git a/tests/arch/microchip/pre_adder_dsp.v b/tests/arch/microchip/pre_adder_dsp.v
deleted file mode 100644
index 7e30278c462..00000000000
--- a/tests/arch/microchip/pre_adder_dsp.v
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module pre_adder_dsp(
-	input signed [5:0] in_A,
-	input signed [4:0] in_B,
-	input signed [4:0] in_D,
-
-	output [11:0] out_Y
-);
-
-assign out_Y = in_A * (in_B + in_D);
-
-
-endmodule
\ No newline at end of file
diff --git a/tests/arch/microchip/pre_adder_dsp.ys b/tests/arch/microchip/pre_adder_dsp.ys
deleted file mode 100644
index 5aa87d432b4..00000000000
--- a/tests/arch/microchip/pre_adder_dsp.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-# ISC License
-# 
-# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
-# Permission to use, copy, modify, and/or distribute this software for any
-# purpose with or without fee is hereby granted, provided that the above
-# copyright notice and this permission notice appear in all copies.
-# 
-# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-
-read_verilog pre_adder_dsp.v
-
-synth_microchip -top pre_adder_dsp -abc9 -family polarfire -noiopad
-
-select -assert-count 1 t:MACC_PA
-select -assert-none t:MACC_PA %% t:* %D
\ No newline at end of file
diff --git a/tests/arch/microchip/ram_SDP.ys b/tests/arch/microchip/ram_SDP.ys
index 59f08705176..777cefc7e28 100644
--- a/tests/arch/microchip/ram_SDP.ys
+++ b/tests/arch/microchip/ram_SDP.ys
@@ -15,10 +15,16 @@
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
 read_verilog ram_SDP.v
-
-synth_microchip -top ram_SDP -abc9 -family polarfire -noiopad
-
+synth_microchip -top ram_SDP -family polarfire -noiopad
 select -assert-count 1 t:RAM1K20
 select -assert-count 1 t:CFG1
 select -assert-none t:RAM1K20 t:CFG1 %% t:* %D
 
+# very similar to ram_SDP.v, except read enable is always active
+design -reset
+read_verilog ../common/blockram.v
+hierarchy -top sync_ram_sdp
+chparam -set DATA_WIDTH 32 -set ADDRESS_WIDTH 8
+synth_microchip -top sync_ram_sdp -family polarfire -noiopad
+select -assert-count 1 t:RAM1K20
+select -assert-none t:RAM1K20 %% t:* %D
\ No newline at end of file
diff --git a/tests/arch/microchip/ram_TDP.v b/tests/arch/microchip/ram_TDP.v
index 54b63b7a8fd..f3b6f826be7 100644
--- a/tests/arch/microchip/ram_TDP.v
+++ b/tests/arch/microchip/ram_TDP.v
@@ -26,31 +26,27 @@ output reg [data_width - 1 : 0] qa,qb;
 reg [addr_width - 1 : 0] addra_reg, addrb_reg;
 reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];
 
-always @ (posedge clka)
-	begin
-		addra_reg <= addra;
-		if(wea)
-			mem[addra] <= dataina;
-	end
-
-always @ (posedge clkb)
-begin
-addrb_reg <= addrb;
-if(web)
-mem[addrb] <= datainb;
-end
-
 always @ (posedge clka)
 begin
-if(~wea)
-qa <= mem[addra];
-else qa <= dataina;
+	addra_reg <= addra;
+			
+	if(wea) begin
+		mem[addra] <= dataina;
+		qa <= dataina;
+	end else begin
+		qa <= mem[addra];
+	end
 end
 
 always @ (posedge clkb)
 begin
-if(~web)
-qb <= mem[addrb];
-else qb <= datainb;
+	addrb_reg <= addrb;
+	if(web) begin
+		mem[addrb] <= datainb;
+		qb <= datainb;
+	end else begin
+		qb <= mem[addrb];
+	end
 end
+
 endmodule
diff --git a/tests/arch/microchip/ram_TDP.ys b/tests/arch/microchip/ram_TDP.ys
index 9dab3cfdc2a..da140fb3c24 100644
--- a/tests/arch/microchip/ram_TDP.ys
+++ b/tests/arch/microchip/ram_TDP.ys
@@ -15,8 +15,16 @@
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
 read_verilog ram_TDP.v
-
-synth_microchip -top ram_TDP -abc9 -family polarfire -noiopad -debug_memory
-
+synth_microchip -top ram_TDP -family polarfire -noiopad
 select -assert-count 1 t:RAM1K20
 select -assert-none t:RAM1K20 %% t:* %D
+
+# similar to ram_TDP.v, but different write mode and read_enable=~write_enable
+design -reset
+read_verilog ../common/blockram.v
+hierarchy -top sync_ram_tdp
+chparam -set DATA_WIDTH 2 -set ADDRESS_WIDTH 10
+synth_microchip -top sync_ram_tdp -family polarfire -noiopad
+select -assert-count 1 t:RAM1K20
+select -assert-count 2 t:CFG1
+select -assert-none t:RAM1K20 t:CFG1 %% t:* %D
\ No newline at end of file
diff --git a/tests/arch/microchip/reduce.ys b/tests/arch/microchip/reduce.ys
index 789912f3225..9e28cf4da3a 100644
--- a/tests/arch/microchip/reduce.ys
+++ b/tests/arch/microchip/reduce.ys
@@ -16,7 +16,7 @@
 
 read_verilog reduce.v
 
-synth_microchip -top reduce -abc9 -family polarfire -noiopad
+synth_microchip -top reduce -family polarfire -noiopad
 
 select -assert-count 1 t:XOR8
 select -assert-none t:XOR8 %% t:* %D
diff --git a/tests/arch/microchip/reg_c.v b/tests/arch/microchip/reg_c.v
deleted file mode 100644
index 63d9d8b2e3e..00000000000
--- a/tests/arch/microchip/reg_c.v
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module reg_c(
-	input clk,
-
-	// active high
-	input en_A,
-	input en_B,
-	input en_D,
-	input en_P,
-
-	// active low
-	input srst_A,
-	input srst_B,
-	input srst_D,
-	input srst_P,
-
-	// active low
-	input arst_D,
-
-	input srst_C,
-	input arst_C,
-
-
-	input signed [5:0] in_A,
-	input signed [4:0] in_B,
-	input signed [4:0] in_C,
-	input signed [4:0] in_D,
-
-
-	output reg [11:0] out_P
-
-);
-
-
-// MACC_PA takes active low resets
-wire srst_A_N;
-wire srst_B_N;
-wire srst_C_N;
-wire srst_D_N;
-wire srst_P_N;
-assign srst_A_N = ~srst_A;
-assign srst_B_N = ~srst_B;
-assign srst_C_N = ~srst_C;
-assign srst_D_N = ~srst_D;
-assign srst_P_N = ~srst_P;
-
-// input reg
-reg signed [5:0] reg_A;
-reg signed [4:0] reg_B;
-reg signed [4:0] reg_C;
-reg signed [4:0] reg_D;
-
-// sync reset A
-always@(posedge clk) begin
-	// if (~srst_A_N) begin
-	if (srst_A_N) begin
-		reg_A = 6'b000000;
-	end else begin
-		reg_A = in_A;
-	end
-end
-
-
-
-// sync reset B
-always@(posedge clk) begin
-	if (srst_B_N) begin
-		reg_B = 5'b00000;
-	end else begin
-		reg_B = in_B;
-	end
-end
-
-
-
-// async reset D
-always@(posedge clk, negedge arst_D) begin
-	if (~arst_D) begin
-		reg_D = 5'b00000;
-	end else begin
-		reg_D = in_D;
-	end
-end
-
-// sync reset C
-always@(posedge clk) begin
-if (srst_C_N) begin
-	reg_C = 5'b00000;
-end else begin
-	reg_C = in_C;
-end
-end
-
-
-
-// sync reset P
-always@(posedge clk) begin
-if (srst_P_N) begin
-	out_P = 12'h000;
-end else begin
-	out_P = reg_A * (reg_B + reg_D) + reg_C;
-end
-end
-
-endmodule
\ No newline at end of file
diff --git a/tests/arch/microchip/reg_c.ys b/tests/arch/microchip/reg_c.ys
deleted file mode 100644
index 994e0811137..00000000000
--- a/tests/arch/microchip/reg_c.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-# ISC License
-# 
-# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
-# Permission to use, copy, modify, and/or distribute this software for any
-# purpose with or without fee is hereby granted, provided that the above
-# copyright notice and this permission notice appear in all copies.
-# 
-# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-
-read_verilog reg_c.v
-
-synth_microchip -top reg_c -abc9 -family polarfire -noiopad
-
-select -assert-count 1 t:MACC_PA
-select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/reg_test.v b/tests/arch/microchip/reg_test.v
deleted file mode 100644
index b10012d026c..00000000000
--- a/tests/arch/microchip/reg_test.v
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module reg_test(
-	input clk,
-
-	// active high
-	input en_A,
-	input en_B,
-	input en_D,
-	input en_P,
-
-	// active low
-	input srst_A,
-	input srst_B,
-	input srst_D,
-	input srst_P,
-
-	// active low
-	input arst_D,
-
-	input signed [5:0] in_A,
-	input signed [4:0] in_B,
-	input signed [4:0] in_D,
-
-	output reg [11:0] out_P
-
-);
-
-
-// MACC_PA takes active low resets
-wire srst_A_N;
-wire srst_B_N;
-wire srst_D_N;
-wire srst_P_N;
-assign srst_A_N = ~srst_A;
-assign srst_B_N = ~srst_B;
-assign srst_D_N = ~srst_D;
-assign srst_P_N = ~srst_P;
-
-// input reg
-reg signed [5:0] reg_A;
-reg signed [4:0] reg_B;
-reg signed [4:0] reg_D;
-
-// sync reset A
-always@(posedge clk) begin
-	if (srst_A_N) begin
-		reg_A = 6'b000000;
-	end else begin
-		reg_A = in_A;
-	end
-end
-
-// sync reset B
-always@(posedge clk) begin
-	if (srst_B_N) begin
-		reg_B = 5'b00000;
-	end else begin
-		reg_B = in_B;
-	end
-end
-
-// async reset D
-always@(posedge clk, negedge arst_D) begin
-	if (~arst_D) begin
-		reg_D = 5'b00000;
-	end else begin
-		reg_D = in_D;
-	end
-end
-
-// sync reset P
-always@(posedge clk) begin
-	if (srst_P_N) begin
-		out_P = 12'h000;
-	end else begin
-		out_P = reg_A * (reg_B + reg_D);
-	end
-end
-
-endmodule
\ No newline at end of file
diff --git a/tests/arch/microchip/reg_test.ys b/tests/arch/microchip/reg_test.ys
deleted file mode 100644
index 1b225b7bf64..00000000000
--- a/tests/arch/microchip/reg_test.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-# ISC License
-# 
-# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
-# Permission to use, copy, modify, and/or distribute this software for any
-# purpose with or without fee is hereby granted, provided that the above
-# copyright notice and this permission notice appear in all copies.
-# 
-# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-
-read_verilog reg_test.v
-
-synth_microchip -top reg_test -abc9 -family polarfire -noiopad
-
-select -assert-count 1 t:MACC_PA
-select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/signed_mult.v b/tests/arch/microchip/signed_mult.v
deleted file mode 100755
index 797d0f5322e..00000000000
--- a/tests/arch/microchip/signed_mult.v
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module signed_mult(
-	input signed [17:0] in_A,
-	input signed [17:0] in_B,
-
-	output signed [35:0] out_Y
-);
-
-assign out_Y = in_A * in_B;
-
-endmodule
\ No newline at end of file
diff --git a/tests/arch/microchip/signed_mult.ys b/tests/arch/microchip/signed_mult.ys
deleted file mode 100755
index 931052163c3..00000000000
--- a/tests/arch/microchip/signed_mult.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-# ISC License
-# 
-# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
-# Permission to use, copy, modify, and/or distribute this software for any
-# purpose with or without fee is hereby granted, provided that the above
-# copyright notice and this permission notice appear in all copies.
-# 
-# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-
-read_verilog signed_mult.v
-
-synth_microchip -top signed_mult -abc9 -family polarfire -noiopad
-
-select -assert-count 1 t:MACC_PA
-select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/simple_ram.v b/tests/arch/microchip/simple_ram.v
deleted file mode 100644
index 9eeba41cb3a..00000000000
--- a/tests/arch/microchip/simple_ram.v
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module simple_ram (clk,wr,addr,din,dout);
-input clk;
-input [19:0] din;
-input wr;
-input [9:0] addr;
-output [19:0] dout;
-
-
-reg [9:0] addr_reg;
-reg [19:0] mem [0:1023] ;
-assign dout = mem[addr_reg];
-
-always@(posedge clk) begin
-	addr_reg <= addr;
-	if(wr)
-		mem[addr]<= din;
-end
-endmodule
-
diff --git a/tests/arch/microchip/simple_ram.ys b/tests/arch/microchip/simple_ram.ys
index 5ed8448ee27..200780c8e05 100644
--- a/tests/arch/microchip/simple_ram.ys
+++ b/tests/arch/microchip/simple_ram.ys
@@ -14,9 +14,9 @@
 # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
-read_verilog simple_ram.v
-
-synth_microchip -top simple_ram -abc9 -family polarfire -noiopad
-
+read_verilog ../common/blockram.v
+hierarchy -top sync_ram_sp
+chparam -set DATA_WIDTH 20 -set ADDRESS_WIDTH 10
+synth_microchip -top sync_ram_sp -family polarfire -noiopad
 select -assert-count 1 t:RAM1K20
-select -assert-none t:RAM1K20 %% t:* %D
+select -assert-none t:RAM1K20 %% t:* %D
\ No newline at end of file
diff --git a/tests/arch/microchip/unsigned_mult.v b/tests/arch/microchip/unsigned_mult.v
deleted file mode 100644
index 22d3db2b12c..00000000000
--- a/tests/arch/microchip/unsigned_mult.v
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module unsigned_mult(
-	input [10:0] in_A,
-	input signed [10:0] in_B,
-
-	output [21:0] out_Y
-);
-
-assign out_Y = in_A * in_B;
-
-endmodule
\ No newline at end of file
diff --git a/tests/arch/microchip/unsigned_mult.ys b/tests/arch/microchip/unsigned_mult.ys
deleted file mode 100644
index 9cc96c99811..00000000000
--- a/tests/arch/microchip/unsigned_mult.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-# ISC License
-# 
-# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
-# Permission to use, copy, modify, and/or distribute this software for any
-# purpose with or without fee is hereby granted, provided that the above
-# copyright notice and this permission notice appear in all copies.
-# 
-# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-
-read_verilog unsigned_mult.v
-
-synth_microchip -top unsigned_mult -abc9 -family polarfire -noiopad
-
-select -assert-count 1 t:MACC_PA
-select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/uram_ar.ys b/tests/arch/microchip/uram_ar.ys
index 68e76897a31..13647153173 100644
--- a/tests/arch/microchip/uram_ar.ys
+++ b/tests/arch/microchip/uram_ar.ys
@@ -16,7 +16,7 @@
 
 read_verilog uram_ar.v
 
-synth_microchip -top uram_ar -abc9 -family polarfire -noiopad
+synth_microchip -top uram_ar -family polarfire -noiopad
 
 select -assert-count 1 t:RAM64x12
 select -assert-none t:RAM64x12 %% t:* %D
diff --git a/tests/arch/microchip/uram_sr.ys b/tests/arch/microchip/uram_sr.ys
index 842d8362773..bc076480088 100644
--- a/tests/arch/microchip/uram_sr.ys
+++ b/tests/arch/microchip/uram_sr.ys
@@ -16,7 +16,7 @@
 
 read_verilog uram_sr.v
 
-synth_microchip -top uram_sr -abc9 -family polarfire -noiopad
+synth_microchip -top uram_sr -family polarfire -noiopad
 
 select -assert-count 1 t:RAM64x12
 select -assert-none t:RAM64x12 %% t:* %D
diff --git a/tests/arch/microchip/widemux.ys b/tests/arch/microchip/widemux.ys
index adb7e00bce3..87bd2632882 100644
--- a/tests/arch/microchip/widemux.ys
+++ b/tests/arch/microchip/widemux.ys
@@ -16,7 +16,20 @@
 
 read_verilog widemux.v
 
-synth_microchip -top widemux -abc9 -family polarfire -noiopad
+synth_microchip -top widemux -family polarfire -noiopad
 
 select -assert-count 1 t:MX4
-select -assert-none t:MX4 %% t:* %D
\ No newline at end of file
+select -assert-none t:MX4 %% t:* %D
+
+
+# RTL style is different here forming a different structure
+read_verilog ../common/mux.v
+design -save read
+
+hierarchy -top mux4
+proc
+equiv_opt -assert -map +/microchip/cells_sim.v synth_microchip -top mux4 -family polarfire -noiopad
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 3 t:CFG3
+select -assert-none t:CFG3 %% t:* %D
\ No newline at end of file

From 3c95a28dc2b110288952cfd55aa2de8af84839b1 Mon Sep 17 00:00:00 2001
From: chunlin min <chunlin.min@microchip.com>
Date: Mon, 8 Jul 2024 11:13:53 -0400
Subject: [PATCH 196/499] fix compile warning

---
 techlibs/microchip/microchip_dffopt.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/microchip/microchip_dffopt.cc b/techlibs/microchip/microchip_dffopt.cc
index 62450ab6e04..cf059d427cc 100644
--- a/techlibs/microchip/microchip_dffopt.cc
+++ b/techlibs/microchip/microchip_dffopt.cc
@@ -115,7 +115,7 @@ struct MicrochipDffOptPass : public Pass {
 	{
 		log_header(design, "Executing MICROCHIP_DFFOPT pass (optimize FF control signal usage).\n");
 
-		size_t argidx;
+		size_t argidx = 0;
 		int max_lut_size = 4;
 
 		extra_args(args, argidx, design);

From a0c9d10118dfcbe9876b3a19f8ab5c1fd5c6ad7e Mon Sep 17 00:00:00 2001
From: chunlin min <chunlin.min@microchip.com>
Date: Mon, 8 Jul 2024 11:30:52 -0400
Subject: [PATCH 197/499] undo last change, to investigate dff_opt test failure

---
 techlibs/microchip/microchip_dffopt.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/microchip/microchip_dffopt.cc b/techlibs/microchip/microchip_dffopt.cc
index cf059d427cc..62450ab6e04 100644
--- a/techlibs/microchip/microchip_dffopt.cc
+++ b/techlibs/microchip/microchip_dffopt.cc
@@ -115,7 +115,7 @@ struct MicrochipDffOptPass : public Pass {
 	{
 		log_header(design, "Executing MICROCHIP_DFFOPT pass (optimize FF control signal usage).\n");
 
-		size_t argidx = 0;
+		size_t argidx;
 		int max_lut_size = 4;
 
 		extra_args(args, argidx, design);

From af67c745c428e3e92e9201bbed0dc61f9686a23f Mon Sep 17 00:00:00 2001
From: chunlin min <chunlin.min@microchip.com>
Date: Mon, 8 Jul 2024 11:41:41 -0400
Subject: [PATCH 198/499] initialize argidx to 1

---
 techlibs/microchip/microchip_dffopt.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/microchip/microchip_dffopt.cc b/techlibs/microchip/microchip_dffopt.cc
index 62450ab6e04..41a74fdc168 100644
--- a/techlibs/microchip/microchip_dffopt.cc
+++ b/techlibs/microchip/microchip_dffopt.cc
@@ -115,7 +115,7 @@ struct MicrochipDffOptPass : public Pass {
 	{
 		log_header(design, "Executing MICROCHIP_DFFOPT pass (optimize FF control signal usage).\n");
 
-		size_t argidx;
+		size_t argidx = 1;
 		int max_lut_size = 4;
 
 		extra_args(args, argidx, design);

From fee274c76a3d08481c91fa44054c57cbe21f7e60 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 8 Jul 2024 18:16:04 +0200
Subject: [PATCH 199/499] Makefile: let clang use -Og in debug builds

---
 Makefile | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/Makefile b/Makefile
index 313de44d56d..0998b2140c0 100644
--- a/Makefile
+++ b/Makefile
@@ -441,12 +441,8 @@ CXXFLAGS := -O3 -DNDEBUG $(filter-out -Os -ggdb,$(CXXFLAGS))
 endif
 
 ifeq ($(ENABLE_DEBUG),1)
-ifeq ($(CONFIG),clang)
-CXXFLAGS := -O0 -DDEBUG $(filter-out -Os,$(CXXFLAGS))
-else
 CXXFLAGS := -Og -DDEBUG $(filter-out -Os,$(CXXFLAGS))
 endif
-endif
 
 ifeq ($(ENABLE_ABC),1)
 CXXFLAGS += -DYOSYS_ENABLE_ABC

From ad22430b965deaa000928ecc79960c375570f505 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 8 Jul 2024 19:19:10 +0200
Subject: [PATCH 200/499] Makefile: use -O3 instead of -Os

---
 Makefile | 31 ++++++++++++++-----------------
 1 file changed, 14 insertions(+), 17 deletions(-)

diff --git a/Makefile b/Makefile
index 0998b2140c0..dce3562097b 100644
--- a/Makefile
+++ b/Makefile
@@ -34,7 +34,6 @@ ENABLE_PYOSYS := 0
 ENABLE_GCOV := 0
 ENABLE_GPROF := 0
 ENABLE_DEBUG := 0
-ENABLE_NDEBUG := 0
 ENABLE_CCACHE := 0
 # sccache is not always a drop-in replacement for ccache in practice
 ENABLE_SCCACHE := 0
@@ -53,6 +52,8 @@ SANITIZER =
 # SANITIZER = undefined
 # SANITIZER = cfi
 
+# Prefer using ENABLE_DEBUG over setting this
+OPT_LEVEL := -O3
 PROGRAM_PREFIX :=
 
 OS := $(shell uname -s)
@@ -209,7 +210,7 @@ endif
 
 ifeq ($(CONFIG),clang)
 CXX = clang++
-CXXFLAGS += -std=$(CXXSTD) -Os
+CXXFLAGS += -std=$(CXXSTD) $(OPT_LEVEL)
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H $(ABC_ARCHFLAGS)"
 
 ifneq ($(SANITIZER),)
@@ -231,14 +232,14 @@ endif
 
 else ifeq ($(CONFIG),gcc)
 CXX = g++
-CXXFLAGS += -std=$(CXXSTD) -Os
+CXXFLAGS += -std=$(CXXSTD) $(OPT_LEVEL)
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H $(ABC_ARCHFLAGS)"
 
 else ifeq ($(CONFIG),gcc-static)
 LINKFLAGS := $(filter-out -rdynamic,$(LINKFLAGS)) -static
 LIBS := $(filter-out -lrt,$(LIBS))
 CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
-CXXFLAGS += -std=$(CXXSTD) -Os
+CXXFLAGS += -std=$(CXXSTD) $(OPT_LEVEL)
 ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(CXX)" ABC_USE_LIBSTDCXX=1 LIBS="-lm -lpthread -static" OPTFLAGS="-O" \
                        ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable $(ARCHFLAGS)" ABC_USE_NO_READLINE=1
 ifeq ($(DISABLE_ABC_THREADS),1)
@@ -247,12 +248,12 @@ endif
 
 else ifeq ($(CONFIG),afl-gcc)
 CXX = AFL_QUIET=1 AFL_HARDEN=1 afl-gcc
-CXXFLAGS += -std=$(CXXSTD) -Os
+CXXFLAGS += -std=$(CXXSTD) $(OPT_LEVEL)
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
 
 else ifeq ($(CONFIG),cygwin)
 CXX = g++
-CXXFLAGS += -std=gnu++11 -Os
+CXXFLAGS += -std=gnu++11 $(OPT_LEVEL)
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
 
 else ifeq ($(CONFIG),wasi)
@@ -267,12 +268,12 @@ AR = $(WASI_SDK)/bin/ar
 RANLIB = $(WASI_SDK)/bin/ranlib
 WASIFLAGS := --sysroot $(WASI_SDK)/share/wasi-sysroot $(WASIFLAGS)
 endif
-CXXFLAGS := $(WASIFLAGS) -std=$(CXXSTD) -Os -D_WASI_EMULATED_PROCESS_CLOCKS $(filter-out -fPIC,$(CXXFLAGS))
+CXXFLAGS := $(WASIFLAGS) -std=$(CXXSTD) $(OPT_LEVEL) -D_WASI_EMULATED_PROCESS_CLOCKS $(filter-out -fPIC,$(CXXFLAGS))
 LINKFLAGS := $(WASIFLAGS) -Wl,-z,stack-size=1048576 $(filter-out -rdynamic,$(LINKFLAGS))
 LIBS := -lwasi-emulated-process-clocks $(filter-out -lrt,$(LIBS))
 ABCMKARGS += AR="$(AR)" RANLIB="$(RANLIB)"
 ABCMKARGS += ARCHFLAGS="$(WASIFLAGS) -D_WASI_EMULATED_PROCESS_CLOCKS -DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING -DABC_NO_RLIMIT"
-ABCMKARGS += OPTFLAGS="-Os"
+ABCMKARGS += OPTFLAGS="$(OPT_LEVEL)"
 EXE = .wasm
 
 DISABLE_SPAWN := 1
@@ -285,7 +286,7 @@ endif
 else ifeq ($(CONFIG),mxe)
 PKG_CONFIG = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-pkg-config
 CXX = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-g++
-CXXFLAGS += -std=$(CXXSTD) -Os -D_POSIX_SOURCE -DYOSYS_MXE_HACKS -Wno-attributes
+CXXFLAGS += -std=$(CXXSTD) $(OPT_LEVEL) -D_POSIX_SOURCE -DYOSYS_MXE_HACKS -Wno-attributes
 CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
 LINKFLAGS := $(filter-out -rdynamic,$(LINKFLAGS)) -s
 LIBS := $(filter-out -lrt,$(LIBS))
@@ -296,7 +297,7 @@ EXE = .exe
 
 else ifeq ($(CONFIG),msys2-32)
 CXX = i686-w64-mingw32-g++
-CXXFLAGS += -std=$(CXXSTD) -Os -D_POSIX_SOURCE -DYOSYS_WIN32_UNIX_DIR
+CXXFLAGS += -std=$(CXXSTD) $(OPT_LEVEL) -D_POSIX_SOURCE -DYOSYS_WIN32_UNIX_DIR
 CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
 LINKFLAGS := $(filter-out -rdynamic,$(LINKFLAGS)) -s
 LIBS := $(filter-out -lrt,$(LIBS))
@@ -306,7 +307,7 @@ EXE = .exe
 
 else ifeq ($(CONFIG),msys2-64)
 CXX = x86_64-w64-mingw32-g++
-CXXFLAGS += -std=$(CXXSTD) -Os -D_POSIX_SOURCE -DYOSYS_WIN32_UNIX_DIR
+CXXFLAGS += -std=$(CXXSTD) $(OPT_LEVEL) -D_POSIX_SOURCE -DYOSYS_WIN32_UNIX_DIR
 CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
 LINKFLAGS := $(filter-out -rdynamic,$(LINKFLAGS)) -s
 LIBS := $(filter-out -lrt,$(LIBS))
@@ -315,7 +316,7 @@ ABCMKARGS += LIBS="-lpthread -lshlwapi -s" ABC_USE_NO_READLINE=0 CC="x86_64-w64-
 EXE = .exe
 
 else ifeq ($(CONFIG),none)
-CXXFLAGS += -std=$(CXXSTD) -Os
+CXXFLAGS += -std=$(CXXSTD) $(OPT_LEVEL)
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H $(ABC_ARCHFLAGS)"
 
 else
@@ -436,12 +437,8 @@ CXXFLAGS += -pg
 LINKFLAGS += -pg
 endif
 
-ifeq ($(ENABLE_NDEBUG),1)
-CXXFLAGS := -O3 -DNDEBUG $(filter-out -Os -ggdb,$(CXXFLAGS))
-endif
-
 ifeq ($(ENABLE_DEBUG),1)
-CXXFLAGS := -Og -DDEBUG $(filter-out -Os,$(CXXFLAGS))
+CXXFLAGS := -Og -DDEBUG $(filter-out $(OPT_LEVEL),$(CXXFLAGS))
 endif
 
 ifeq ($(ENABLE_ABC),1)

From 0afb5e28fb7dd4c5c866ebcf01d47fa103368ad0 Mon Sep 17 00:00:00 2001
From: chunlin min <chunlin.min@microchip.com>
Date: Mon, 8 Jul 2024 15:10:44 -0400
Subject: [PATCH 201/499] cosmetic changes

---
 techlibs/microchip/synth_microchip.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/techlibs/microchip/synth_microchip.cc b/techlibs/microchip/synth_microchip.cc
index 2da4c4000c7..12dc9e221b7 100644
--- a/techlibs/microchip/synth_microchip.cc
+++ b/techlibs/microchip/synth_microchip.cc
@@ -87,7 +87,7 @@ struct SynthMicrochipPass : public ScriptPass {
 		log("        Run 'abc' with '-D 1' option to enable flip-flop retiming.\n");
 		log("        implies -dff.\n");
 		log("\n");
-		log("    -abc\n");
+		log("    -noabc9\n");
 		log("        Use classic ABC flow instead of ABC9\n");
 		log("\n");
 		log("\n");
@@ -198,7 +198,7 @@ struct SynthMicrochipPass : public ScriptPass {
 				nobram = true;
 				continue;
 			}
-			if (args[argidx] == "-abc") {
+			if (args[argidx] == "-noabc9") {
 				abc9 = false;
 				continue;
 			}
@@ -481,7 +481,7 @@ struct SynthMicrochipPass : public ScriptPass {
 			else if (abc9) {
 
 				std::string abc9_opts;
-				// for the if command in abc to specify wire delay between adjects LUTs (default = 0)
+				// for the if command in abc to specify wire delay between adjacent LUTs (default = 0)
 				// NOTE: should not have 0 wire delay between LUTs,
 				//		 otherwise abc might use LUT2+LUT3 instead of single LUT4
 				abc9_opts += " -W 300";

From 3db69b7a105b2c7497fc00b0dc01602f28c5be67 Mon Sep 17 00:00:00 2001
From: chunlin min <chunlin.min@microchip.com>
Date: Mon, 8 Jul 2024 17:03:03 -0400
Subject: [PATCH 202/499] inline all tests. Add switch to remove init values as
 PolarFire DFFs do not support init

---
 techlibs/microchip/synth_microchip.cc | 17 +++++++--
 tests/arch/microchip/dff_opt.v        | 42 ----------------------
 tests/arch/microchip/dff_opt.ys       | 22 ++++++++++--
 tests/arch/microchip/ram_SDP.v        | 39 --------------------
 tests/arch/microchip/ram_SDP.ys       | 22 +++++++++++-
 tests/arch/microchip/ram_TDP.v        | 52 ---------------------------
 tests/arch/microchip/ram_TDP.ys       | 36 ++++++++++++++++++-
 tests/arch/microchip/reduce.v         | 29 ---------------
 tests/arch/microchip/reduce.ys        | 11 ++++--
 tests/arch/microchip/uram_ar.v        | 38 --------------------
 tests/arch/microchip/uram_ar.ys       | 22 ++++++++++--
 tests/arch/microchip/uram_sr.v        | 40 ---------------------
 tests/arch/microchip/uram_sr.ys       | 25 ++++++++++++-
 tests/arch/microchip/widemux.v        | 31 ----------------
 tests/arch/microchip/widemux.ys       | 14 +++++---
 15 files changed, 152 insertions(+), 288 deletions(-)
 delete mode 100644 tests/arch/microchip/dff_opt.v
 delete mode 100644 tests/arch/microchip/ram_SDP.v
 delete mode 100644 tests/arch/microchip/ram_TDP.v
 delete mode 100644 tests/arch/microchip/reduce.v
 delete mode 100644 tests/arch/microchip/uram_ar.v
 delete mode 100644 tests/arch/microchip/uram_sr.v
 delete mode 100644 tests/arch/microchip/widemux.v

diff --git a/techlibs/microchip/synth_microchip.cc b/techlibs/microchip/synth_microchip.cc
index 12dc9e221b7..727bf9ac65a 100644
--- a/techlibs/microchip/synth_microchip.cc
+++ b/techlibs/microchip/synth_microchip.cc
@@ -90,6 +90,9 @@ struct SynthMicrochipPass : public ScriptPass {
 		log("    -noabc9\n");
 		log("        Use classic ABC flow instead of ABC9\n");
 		log("\n");
+		log("    -discard-ffinit\n");
+		log("        discard FF init value instead of emitting an error\n");
+		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
 		help_script();
@@ -99,6 +102,7 @@ struct SynthMicrochipPass : public ScriptPass {
 	std::string top_opt, edif_file, blif_file, vlog_file, family;
 	bool flatten, retime, noiopad, noclkbuf, nobram, nocarry, nowidelut, nodsp;
 	bool abc9, dff;
+	bool discard_ffinit;
 	int lut_size;
 
 	// debug dump switches
@@ -122,6 +126,7 @@ struct SynthMicrochipPass : public ScriptPass {
 		abc9 = true;
 		dff = false;
 		lut_size = 4;
+		discard_ffinit = false;
 
 		debug_memory = false;
 		debug_carry = false;
@@ -218,6 +223,10 @@ struct SynthMicrochipPass : public ScriptPass {
 				debug_carry = true;
 				continue;
 			}
+			if (args[argidx] == "-discard-ffinit") {
+				discard_ffinit = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -314,6 +323,8 @@ struct SynthMicrochipPass : public ScriptPass {
 			run("opt");
 			run("memory -nomap");
 			run("opt_clean");
+			if (discard_ffinit || help_mode)
+				run("attrmap -remove init", "(only if -discard-ffinit)");
 		}
 
 		if (check_label("map_memory")) {
@@ -454,15 +465,15 @@ struct SynthMicrochipPass : public ScriptPass {
 
 				// D-flop with async reset and enable
 				// posedge CLK, active low reset to 1 or 0, active high EN
-				params += " -cell $_DFFE_PN?P_ 01";
+				params += " -cell $_DFFE_PN?P_ x";
 
 				// D-flop with sync reset and enable, enable takes priority over reset
 				// posedge CLK, active low reset to 1 or 0, active high EN
-				params += " -cell $_SDFFCE_PN?P_ 01";
+				params += " -cell $_SDFFCE_PN?P_ x";
 
 				// D-latch + reset to 0/1
 				// posedge CLK, active low reset to 1 or 0
-				params += " -cell $_DLATCH_PN?_ 01";
+				params += " -cell $_DLATCH_PN?_ x";
 
 				run("dfflegalize" + params, "(Converts FFs to supported types)");
 			}
diff --git a/tests/arch/microchip/dff_opt.v b/tests/arch/microchip/dff_opt.v
deleted file mode 100644
index 67d8c3d51f5..00000000000
--- a/tests/arch/microchip/dff_opt.v
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module dff_opt(
-	input clk,
-	input [1:0] D_comb,
-	input [1:0] EN_comb,
-	input [1:0] RST_comb,
-	output bar
-);
-
-// DFF with enable that can be merged into D
-
-reg foo;
-
-assign bar = foo;
-
-// sync reset
-always@(posedge clk) begin
-	if (&RST_comb) begin
-		foo <= 0;
-	end else begin
-		foo <= &D_comb;
-	end
-end
-
-endmodule
diff --git a/tests/arch/microchip/dff_opt.ys b/tests/arch/microchip/dff_opt.ys
index 3c3125d6242..e4647dc5d5d 100644
--- a/tests/arch/microchip/dff_opt.ys
+++ b/tests/arch/microchip/dff_opt.ys
@@ -14,10 +14,28 @@
 # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
-read_verilog dff_opt.v 
 
+# reset can be merged into D LUT
+read_verilog <<EOT
+module dff_opt(
+	input clk,
+	input [1:0] D_comb,
+	input [1:0] EN_comb,
+	input [1:0] RST_comb,
+	output bar
+);
+reg foo;
+assign bar = foo;
+always@(posedge clk) begin
+	if (&RST_comb) begin
+		foo <= 0;
+	end else begin
+		foo <= &D_comb;
+	end
+end
+endmodule
+EOT
 synth_microchip -top dff_opt -family polarfire -noiopad
-
 select -assert-count 1 t:SLE
 select -assert-count 1 t:CFG4
 select -assert-count 1 t:CLKBUF
diff --git a/tests/arch/microchip/ram_SDP.v b/tests/arch/microchip/ram_SDP.v
deleted file mode 100644
index 4e83c544a97..00000000000
--- a/tests/arch/microchip/ram_SDP.v
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module ram_SDP(data,waddr,we,clk,q);
-parameter d_width = 32;
-parameter addr_width = 8;
-parameter mem_depth = 256;
-input [d_width-1:0] data;
-input [addr_width-1:0] waddr;
-input we, clk;
-output reg [d_width-1:0] q;
-
-reg [d_width-1:0] mem [mem_depth-1:0];
-
-always @(posedge clk) begin
-	if (we) begin 
-		mem[waddr] <= data;
-	end else begin
-		q <= mem[waddr];
-	end
-end
-
-endmodule
-
diff --git a/tests/arch/microchip/ram_SDP.ys b/tests/arch/microchip/ram_SDP.ys
index 777cefc7e28..31b8a874fb0 100644
--- a/tests/arch/microchip/ram_SDP.ys
+++ b/tests/arch/microchip/ram_SDP.ys
@@ -14,7 +14,27 @@
 # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
-read_verilog ram_SDP.v
+read_verilog <<EOT
+module ram_SDP(data,waddr,we,clk,q);
+parameter d_width = 32;
+parameter addr_width = 8;
+parameter mem_depth = 256;
+input [d_width-1:0] data;
+input [addr_width-1:0] waddr;
+input we, clk;
+output reg [d_width-1:0] q;
+
+reg [d_width-1:0] mem [mem_depth-1:0];
+
+always @(posedge clk) begin
+	if (we) begin 
+		mem[waddr] <= data;
+	end else begin
+		q <= mem[waddr];
+	end
+end
+endmodule
+EOT
 synth_microchip -top ram_SDP -family polarfire -noiopad
 select -assert-count 1 t:RAM1K20
 select -assert-count 1 t:CFG1
diff --git a/tests/arch/microchip/ram_TDP.v b/tests/arch/microchip/ram_TDP.v
deleted file mode 100644
index f3b6f826be7..00000000000
--- a/tests/arch/microchip/ram_TDP.v
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module ram_TDP (clka,clkb,wea,addra,dataina,qa,web,addrb,datainb,qb);
-parameter addr_width = 10;
-parameter data_width = 2;
-input clka,clkb,wea,web;
-input [data_width - 1 : 0] dataina,datainb;
-input [addr_width - 1 : 0] addra,addrb;
-output reg [data_width - 1 : 0] qa,qb;
-reg [addr_width - 1 : 0] addra_reg, addrb_reg;
-reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];
-
-always @ (posedge clka)
-begin
-	addra_reg <= addra;
-			
-	if(wea) begin
-		mem[addra] <= dataina;
-		qa <= dataina;
-	end else begin
-		qa <= mem[addra];
-	end
-end
-
-always @ (posedge clkb)
-begin
-	addrb_reg <= addrb;
-	if(web) begin
-		mem[addrb] <= datainb;
-		qb <= datainb;
-	end else begin
-		qb <= mem[addrb];
-	end
-end
-
-endmodule
diff --git a/tests/arch/microchip/ram_TDP.ys b/tests/arch/microchip/ram_TDP.ys
index da140fb3c24..6e7ed43db76 100644
--- a/tests/arch/microchip/ram_TDP.ys
+++ b/tests/arch/microchip/ram_TDP.ys
@@ -14,7 +14,41 @@
 # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
-read_verilog ram_TDP.v
+read_verilog <<EOT
+module ram_TDP (clka,clkb,wea,addra,dataina,qa,web,addrb,datainb,qb);
+parameter addr_width = 10;
+parameter data_width = 2;
+input clka,clkb,wea,web;
+input [data_width - 1 : 0] dataina,datainb;
+input [addr_width - 1 : 0] addra,addrb;
+output reg [data_width - 1 : 0] qa,qb;
+reg [addr_width - 1 : 0] addra_reg, addrb_reg;
+reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];
+
+always @ (posedge clka)
+begin
+	addra_reg <= addra;
+			
+	if(wea) begin
+		mem[addra] <= dataina;
+		qa <= dataina;
+	end else begin
+		qa <= mem[addra];
+	end
+end
+
+always @ (posedge clkb)
+begin
+	addrb_reg <= addrb;
+	if(web) begin
+		mem[addrb] <= datainb;
+		qb <= datainb;
+	end else begin
+		qb <= mem[addrb];
+	end
+end
+endmodule
+EOT
 synth_microchip -top ram_TDP -family polarfire -noiopad
 select -assert-count 1 t:RAM1K20
 select -assert-none t:RAM1K20 %% t:* %D
diff --git a/tests/arch/microchip/reduce.v b/tests/arch/microchip/reduce.v
deleted file mode 100644
index b2b01ba92ff..00000000000
--- a/tests/arch/microchip/reduce.v
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module reduce(
-	input [7:0] data,
-	output Y
-
-);
-
-
-assign Y = ^data;
-
-endmodule
-
diff --git a/tests/arch/microchip/reduce.ys b/tests/arch/microchip/reduce.ys
index 9e28cf4da3a..ab19f5a35c4 100644
--- a/tests/arch/microchip/reduce.ys
+++ b/tests/arch/microchip/reduce.ys
@@ -14,10 +14,15 @@
 # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
-read_verilog reduce.v
-
+read_verilog <<EOT
+module reduce(
+	input [7:0] data,
+	output Y
+);
+	assign Y = ^data;
+endmodule
+EOT
 synth_microchip -top reduce -family polarfire -noiopad
-
 select -assert-count 1 t:XOR8
 select -assert-none t:XOR8 %% t:* %D
 
diff --git a/tests/arch/microchip/uram_ar.v b/tests/arch/microchip/uram_ar.v
deleted file mode 100644
index c73ece07e31..00000000000
--- a/tests/arch/microchip/uram_ar.v
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module uram_ar(data,waddr,we,clk,q);
-parameter d_width = 12;
-parameter addr_width = 2;
-parameter mem_depth = 12;
-input [d_width-1:0] data;
-input [addr_width-1:0] waddr;
-input we, clk;
-output [d_width-1:0] q;
-
-reg [d_width-1:0] mem [mem_depth-1:0];
-
-assign q = mem[waddr];
-
-always @(posedge clk) begin
-	if (we) 
-		mem[waddr] <= data;
-
-end
-
-endmodule
diff --git a/tests/arch/microchip/uram_ar.ys b/tests/arch/microchip/uram_ar.ys
index 13647153173..95c3fbf41b9 100644
--- a/tests/arch/microchip/uram_ar.ys
+++ b/tests/arch/microchip/uram_ar.ys
@@ -14,9 +14,27 @@
 # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
-read_verilog uram_ar.v
+read_verilog <<EOT
+module uram_ar(data,waddr,we,clk,q);
+parameter d_width = 12;
+parameter addr_width = 2;
+parameter mem_depth = 12;
+input [d_width-1:0] data;
+input [addr_width-1:0] waddr;
+input we, clk;
+output [d_width-1:0] q;
 
-synth_microchip -top uram_ar -family polarfire -noiopad
+reg [d_width-1:0] mem [mem_depth-1:0];
+assign q = mem[waddr];
+
+always @(posedge clk) begin
+	if (we) 
+		mem[waddr] <= data;
 
+end
+endmodule
+EOT
+
+synth_microchip -top uram_ar -family polarfire -noiopad
 select -assert-count 1 t:RAM64x12
 select -assert-none t:RAM64x12 %% t:* %D
diff --git a/tests/arch/microchip/uram_sr.v b/tests/arch/microchip/uram_sr.v
deleted file mode 100644
index 7bab189fe48..00000000000
--- a/tests/arch/microchip/uram_sr.v
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module uram_sr(clk, wr, raddr, din, waddr, dout);
-	input clk;
-	input [11:0] din;
-	input wr;
-	input [5:0] waddr, raddr;
-	output [11:0] dout;
-	reg [5:0] raddr_reg;
-	reg [11:0] mem [0:63];
-	assign dout = mem[raddr_reg];
-
-	integer i;
-	initial begin
-		for (i = 0; i < 64; i = i + 1) begin
-			mem[i] = 12'hfff;
-		end
-	end
-
-	always@(posedge clk) begin
-		raddr_reg <= raddr; if(wr)
-		mem[waddr]<= din;
-	end
-endmodule
\ No newline at end of file
diff --git a/tests/arch/microchip/uram_sr.ys b/tests/arch/microchip/uram_sr.ys
index bc076480088..338ce5ecc8d 100644
--- a/tests/arch/microchip/uram_sr.ys
+++ b/tests/arch/microchip/uram_sr.ys
@@ -14,7 +14,30 @@
 # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
-read_verilog uram_sr.v
+read_verilog <<EOT
+module uram_sr(clk, wr, raddr, din, waddr, dout);
+	input clk;
+	input [11:0] din;
+	input wr;
+	input [5:0] waddr, raddr;
+	output [11:0] dout;
+	reg [5:0] raddr_reg;
+	reg [11:0] mem [0:63];
+	assign dout = mem[raddr_reg];
+	integer i;
+	initial begin
+		for (i = 0; i < 64; i = i + 1) begin
+			mem[i] = 12'hfff;
+		end
+	end
+
+	always@(posedge clk) begin
+		raddr_reg <= raddr; 
+		if(wr)
+			mem[waddr]<= din;
+	end
+endmodule
+EOT
 
 synth_microchip -top uram_sr -family polarfire -noiopad
 
diff --git a/tests/arch/microchip/widemux.v b/tests/arch/microchip/widemux.v
deleted file mode 100644
index 74e3fd7fc58..00000000000
--- a/tests/arch/microchip/widemux.v
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module widemux(
-	input [3:0] data,
-	input S0,
-	input S1,
-	output Y
-
-);
-assign Y = S1 ? (S0 ? data[3] : data[1]) : (S0 ? data[2] : data[0]);
-
-endmodule
-
-
-
diff --git a/tests/arch/microchip/widemux.ys b/tests/arch/microchip/widemux.ys
index 87bd2632882..cae24bd0bea 100644
--- a/tests/arch/microchip/widemux.ys
+++ b/tests/arch/microchip/widemux.ys
@@ -14,14 +14,20 @@
 # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
-read_verilog widemux.v
-
+read_verilog <<EOT
+module widemux(
+	input [3:0] data,
+	input S0,
+	input S1,
+	output Y
+);
+	assign Y = S1 ? (S0 ? data[3] : data[1]) : (S0 ? data[2] : data[0]);
+endmodule
+EOT
 synth_microchip -top widemux -family polarfire -noiopad
-
 select -assert-count 1 t:MX4
 select -assert-none t:MX4 %% t:* %D
 
-
 # RTL style is different here forming a different structure
 read_verilog ../common/mux.v
 design -save read

From c6e5e0b26ba2f7fd2ecadb3084c93ef9d1858fab Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 9 Jul 2024 09:11:59 +0200
Subject: [PATCH 203/499] Release version 0.43

---
 CHANGELOG           | 11 ++++++++++-
 Makefile            |  6 +++---
 docs/source/conf.py |  2 +-
 3 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index d8e13b041e5..7148e138aac 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,8 +2,17 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.42 .. Yosys 0.43-dev
+Yosys 0.42 .. Yosys 0.43
 --------------------------
+ * Various
+    - C++ compiler with C++17 support is required.
+    - Support for IO liberty files for verification.
+    - Limit padding from shiftadd for "peepopt" pass.
+
+ * Verific support
+    - Support building Yosys with various Verific library
+      configurations. Can be built now without YosysHQ 
+      specific patch and extension library.
 
 Yosys 0.41 .. Yosys 0.42
 --------------------------
diff --git a/Makefile b/Makefile
index 313de44d56d..1dec716e26b 100644
--- a/Makefile
+++ b/Makefile
@@ -20,7 +20,7 @@ ENABLE_VERIFIC := 0
 ENABLE_VERIFIC_SYSTEMVERILOG := 1
 ENABLE_VERIFIC_VHDL := 1
 ENABLE_VERIFIC_HIER_TREE := 1
-ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1
+ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0
 ENABLE_VERIFIC_EDIF := 0
 ENABLE_VERIFIC_LIBERTY := 0
 ENABLE_COVER := 1
@@ -143,7 +143,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.42+40
+YOSYS_VER := 0.43
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -159,7 +159,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9b6afcf.. | wc -l`/;" Makefile
+#	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9b6afcf.. | wc -l`/;" Makefile
 
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
 
diff --git a/docs/source/conf.py b/docs/source/conf.py
index c9c923e8231..1dd53e95411 100644
--- a/docs/source/conf.py
+++ b/docs/source/conf.py
@@ -5,7 +5,7 @@
 project = 'YosysHQ Yosys'
 author = 'YosysHQ GmbH'
 copyright ='2024 YosysHQ GmbH'
-yosys_ver = "0.42"
+yosys_ver = "0.43"
 
 # select HTML theme
 html_theme = 'furo'

From ead4718e567aed2e552dcfe46294b132aa04c158 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 9 Jul 2024 09:22:37 +0200
Subject: [PATCH 204/499] Enable extensions for CI

---
 .github/workflows/test-verific.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml
index 54d9487acfb..5b6268a2eaf 100644
--- a/.github/workflows/test-verific.yml
+++ b/.github/workflows/test-verific.yml
@@ -39,6 +39,7 @@ jobs:
           echo "ENABLE_VERIFIC := 1" >> Makefile.conf
           echo "ENABLE_VERIFIC_EDIF := 1" >> Makefile.conf
           echo "ENABLE_VERIFIC_LIBERTY := 1" >> Makefile.conf
+          echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1" >> Makefile.conf
           echo "ENABLE_CCACHE := 1" >> Makefile.conf
           make -j${{ env.procs }}
 

From b9181aaad2cbebc11834ec765fd06bf34af2b634 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 9 Jul 2024 09:27:23 +0200
Subject: [PATCH 205/499] Next dev cycle

---
 CHANGELOG | 3 +++
 Makefile  | 4 ++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index 7148e138aac..160f480e7b0 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 List of major changes and improvements between releases
 =======================================================
 
+Yosys 0.43 .. Yosys 0.44-dev
+--------------------------
+
 Yosys 0.42 .. Yosys 0.43
 --------------------------
  * Various
diff --git a/Makefile b/Makefile
index 1dec716e26b..2f1c9a01623 100644
--- a/Makefile
+++ b/Makefile
@@ -143,7 +143,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.43
+YOSYS_VER := 0.43+0
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -159,7 +159,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-#	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9b6afcf.. | wc -l`/;" Makefile
+	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline ead4718.. | wc -l`/;" Makefile
 
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
 

From 725746baa6357a494cc6f3ffb9d149c8b5a29125 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Tue, 9 Jul 2024 11:25:16 +0200
Subject: [PATCH 206/499] Makefile: LTO for all, lld for clang

---
 Makefile  | 19 ++++++++++++++++++-
 flake.nix |  2 +-
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index dce3562097b..310b23dce1c 100644
--- a/Makefile
+++ b/Makefile
@@ -34,6 +34,7 @@ ENABLE_PYOSYS := 0
 ENABLE_GCOV := 0
 ENABLE_GPROF := 0
 ENABLE_DEBUG := 0
+ENABLE_LTO := 1
 ENABLE_CCACHE := 0
 # sccache is not always a drop-in replacement for ccache in practice
 ENABLE_SCCACHE := 0
@@ -52,8 +53,11 @@ SANITIZER =
 # SANITIZER = undefined
 # SANITIZER = cfi
 
-# Prefer using ENABLE_DEBUG over setting this
+# Prefer using ENABLE_DEBUG over setting these
 OPT_LEVEL := -O3
+GCC_LTO := -flto=auto
+CLANG_LTO := -flto=thin
+
 PROGRAM_PREFIX :=
 
 OS := $(shell uname -s)
@@ -208,10 +212,15 @@ ifeq ($(OS), OpenBSD)
 ABC_ARCHFLAGS += "-DABC_NO_RLIMIT"
 endif
 
+# This gets overridden later.
+LTOFLAGS := $(GCC_LTO)
+
 ifeq ($(CONFIG),clang)
 CXX = clang++
 CXXFLAGS += -std=$(CXXSTD) $(OPT_LEVEL)
+LINKFLAGS += -fuse-ld=lld
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H $(ABC_ARCHFLAGS)"
+LTOFLAGS := $(CLANG_LTO)
 
 ifneq ($(SANITIZER),)
 $(info [Clang Sanitizer] $(SANITIZER))
@@ -227,6 +236,7 @@ endif
 ifneq ($(findstring cfi,$(SANITIZER)),)
 CXXFLAGS += -flto
 LINKFLAGS += -flto
+LTOFLAGS =
 endif
 endif
 
@@ -318,11 +328,18 @@ EXE = .exe
 else ifeq ($(CONFIG),none)
 CXXFLAGS += -std=$(CXXSTD) $(OPT_LEVEL)
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H $(ABC_ARCHFLAGS)"
+LTOFLAGS =
 
 else
 $(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc, mxe, msys2-32, msys2-64, none)
 endif
 
+
+ifeq ($(ENABLE_LTO),1)
+CXXFLAGS += $(LTOFLAGS)
+LINKFLAGS += $(LTOFLAGS)
+endif
+
 ifeq ($(ENABLE_LIBYOSYS),1)
 TARGETS += libyosys.so
 endif
diff --git a/flake.nix b/flake.nix
index 1e202324647..bafdc7bc4dc 100644
--- a/flake.nix
+++ b/flake.nix
@@ -41,7 +41,7 @@
         packages.default = yosys;
         defaultPackage = yosys;
         devShell = pkgs.mkShell {
-          buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier ];
+          buildInputs = with pkgs; [ clang llvmPackages.bintools bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier ];
         };
       }
     );

From 130dee6e5695408117d669c89e80b5e687a1471a Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 9 Jul 2024 14:19:33 +0200
Subject: [PATCH 207/499] Use alternate location for VS build required files

---
 misc/create_vcxsrc.sh | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/misc/create_vcxsrc.sh b/misc/create_vcxsrc.sh
index 5f8b35e8075..d7b516fd698 100644
--- a/misc/create_vcxsrc.sh
+++ b/misc/create_vcxsrc.sh
@@ -6,8 +6,8 @@ yosysver="$2"
 gitsha="$3"
 
 rm -rf YosysVS-Tpl-v2.zip YosysVS
-wget https://yosyshq.net/yosys/nogit/YosysVS-Tpl-v2.zip
-wget https://www.zlib.net/fossils/zlib-1.2.11.tar.gz
+wget https://github.com/YosysHQ/yosys/releases/download/resources/YosysVS-Tpl-v2.zip
+wget https://github.com/YosysHQ/yosys/releases/download/resources/zlib-1.2.11.tar.gz
 
 unzip YosysVS-Tpl-v2.zip
 rm -f YosysVS-Tpl-v2.zip

From b08688f71197316cd44859b8ced16136cf1b3957 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Wed, 10 Jul 2024 00:18:13 +0000
Subject: [PATCH 208/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 2f1c9a01623..96c133da96a 100644
--- a/Makefile
+++ b/Makefile
@@ -143,7 +143,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.43+0
+YOSYS_VER := 0.43+3
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 19bbdd8800c45dd06b1572c5dbf9663607335bb1 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 11 Jul 2024 21:39:44 +1000
Subject: [PATCH 209/499] Gowin. Add the DCS primitive

Not so much adding the primitive itself, but only its DCS_MODE
parameter, without which an error occurs.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 techlibs/gowin/cells_sim.v  | 11 +++++++++++
 techlibs/gowin/cells_xtra.v |  6 ------
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index b268690803f..d4e0350510c 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -1901,3 +1901,14 @@ output OSCOUT;
 parameter FREQ_DIV = 100;
 parameter REGULATOR_EN = 1'b0;
 endmodule
+
+(* blackbox *)
+module DCS (CLK0, CLK1, CLK2, CLK3, CLKSEL, SELFORCE, CLKOUT);
+input CLK0, CLK1, CLK2, CLK3, SELFORCE;
+input [3:0] CLKSEL;
+output CLKOUT;
+parameter DCS_MODE = "RISING";
+endmodule
+
+
+
diff --git a/techlibs/gowin/cells_xtra.v b/techlibs/gowin/cells_xtra.v
index 4b89b8098aa..cf914f38e3e 100644
--- a/techlibs/gowin/cells_xtra.v
+++ b/techlibs/gowin/cells_xtra.v
@@ -1564,12 +1564,6 @@ parameter IDLE    =  4'd0,
 		  RD_S2   =  4'd12;
 endmodule
 
-module DCS (...);
-input CLK0, CLK1, CLK2, CLK3, SELFORCE;
-input [3:0] CLKSEL;
-output CLKOUT;
-endmodule
-
 module DQCE (...);
 input CLKIN;
 input CE;

From 9d15f1d6ac4a9ff2e1f87cda8c366659027fb76f Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 12 Jul 2024 10:52:03 +0200
Subject: [PATCH 210/499] Makefile: reproducible .gitcommit

---
 .gitcommit | 2 +-
 Makefile   | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/.gitcommit b/.gitcommit
index 46b7856fbc8..6828f88dcb0 100644
--- a/.gitcommit
+++ b/.gitcommit
@@ -1 +1 @@
-$Format:%h$
+$Format:%H$
diff --git a/Makefile b/Makefile
index 96c133da96a..25a039256ea 100644
--- a/Makefile
+++ b/Makefile
@@ -150,7 +150,7 @@ YOSYS_VER := 0.43+3
 # will have this file in its unexpanded form tough, in which case we fall
 # back to calling git directly.
 TARBALL_GIT_REV := $(shell cat $(YOSYS_SRC)/.gitcommit)
-ifeq ($(TARBALL_GIT_REV),$$Format:%h$$)
+ifneq ($(findstring "Format:",$(TARBALL_GIT_REV)),)
 GIT_REV := $(shell GIT_DIR=$(YOSYS_SRC)/.git git rev-parse --short=9 HEAD || echo UNKNOWN)
 else
 GIT_REV := $(TARBALL_GIT_REV)
@@ -773,10 +773,10 @@ check-git-abc:
 		exit 1; \
 	elif git -C "$(YOSYS_SRC)" submodule status abc 2>/dev/null | grep -q '^ '; then \
 		exit 0; \
-	elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && ! grep -q '\$$Format:%h\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \
+	elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && ! grep -q '\$$Format:%[hH]\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \
 		echo "'abc' comes from a tarball. Continuing."; \
 		exit 0; \
-	elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && grep -q '\$$Format:%h\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \
+	elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && grep -q '\$$Format:%[hH]\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \
 		echo "Error: 'abc' is not configured as a git submodule."; \
 		echo "To resolve this:"; \
 		echo "1. Back up your changes: Save any modifications from the 'abc' directory to another location."; \

From 7d9ba37fa0291b49ec59217dfe1eb43180ad1edd Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 12 Jul 2024 10:52:13 +0200
Subject: [PATCH 211/499] abc: bump for reproducilbe .gitcommit

---
 abc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/abc b/abc
index 237d81397fc..28d955ca97a 160000
--- a/abc
+++ b/abc
@@ -1 +1 @@
-Subproject commit 237d81397fcc85dd3894bf1a449d2955cd3df02d
+Subproject commit 28d955ca97a1c4be3aed4062aec0241a734fac5d

From 0cd55e1d7ccbd08e78a213dba3f8dd0d6479a8b0 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 12 Jul 2024 11:00:36 +0200
Subject: [PATCH 212/499] Makefile: fix

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 25a039256ea..fdb78a98608 100644
--- a/Makefile
+++ b/Makefile
@@ -150,7 +150,7 @@ YOSYS_VER := 0.43+3
 # will have this file in its unexpanded form tough, in which case we fall
 # back to calling git directly.
 TARBALL_GIT_REV := $(shell cat $(YOSYS_SRC)/.gitcommit)
-ifneq ($(findstring "Format:",$(TARBALL_GIT_REV)),)
+ifneq ($(findstring Format:,$(TARBALL_GIT_REV)),)
 GIT_REV := $(shell GIT_DIR=$(YOSYS_SRC)/.git git rev-parse --short=9 HEAD || echo UNKNOWN)
 else
 GIT_REV := $(TARBALL_GIT_REV)

From 532188f23900de787ac21ae641be25493b036d9a Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 15 Jul 2024 11:14:47 +0200
Subject: [PATCH 213/499] opt_expr: change info message

---
 passes/opt/opt_expr.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index ba7292daf49..ae5a980b183 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -515,7 +515,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 	if (!cells.sort()) {
 		// There might be a combinational loop, or there might be constants on the output of cells. 'check' may find out more.
 		// ...unless this is a coarse-grained cell loop, but not a bit loop, in which case it won't, and all is good.
-		log("Couldn't topologically sort cells, Yosys performance may be degraded.\nRunning 'check' is recommended.\n");
+		log("Couldn't topologically sort cells, optimizing module %s may take a longer time.\n", log_id(module));
 	}
 
 	for (auto cell : cells.sorted)

From 2f514487cb297116f51084d41689cba1ced7fc25 Mon Sep 17 00:00:00 2001
From: Alexander von Gluck <alex@terarocket.io>
Date: Tue, 4 Jun 2024 10:14:02 -0500
Subject: [PATCH 214/499] haiku: Basic fixes to build under Haiku

---
 Makefile        | 5 +++++
 kernel/yosys.cc | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 96c133da96a..308b1df3027 100644
--- a/Makefile
+++ b/Makefile
@@ -143,6 +143,11 @@ LIBS += -lrt
 endif
 endif
 
+ifeq ($(OS), Haiku)
+# Allow usage of non-posix vasprintf, mkstemps functions
+CXXFLAGS += -D_DEFAULT_SOURCE
+endif
+
 YOSYS_VER := 0.43+3
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 57433d0d9c1..fca2bca6779 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -967,7 +967,7 @@ std::string proc_self_dirname()
 {
 	return "/";
 }
-#elif defined(__OpenBSD__)
+#elif defined(__OpenBSD__) || defined(__HAIKU__)
 char yosys_path[PATH_MAX];
 char *yosys_argv0;
 

From 49f547782c9f4317df6b70e3f25fe30d18e93cb4 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Tue, 16 Jul 2024 00:18:08 +0000
Subject: [PATCH 215/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 308b1df3027..66e6c91aeac 100644
--- a/Makefile
+++ b/Makefile
@@ -148,7 +148,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.43+3
+YOSYS_VER := 0.43+11
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From ec32c9a0567621b4aadb180588a1faa559c5447e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Wed, 17 Jul 2024 18:26:12 +0200
Subject: [PATCH 216/499] Makefile: do install `bitpattern.h`

---
 Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Makefile b/Makefile
index 66e6c91aeac..3e655556247 100644
--- a/Makefile
+++ b/Makefile
@@ -579,6 +579,7 @@ S =
 endif
 
 $(eval $(call add_include_file,kernel/binding.h))
+$(eval $(call add_include_file,kernel/bitpattern.h))
 $(eval $(call add_include_file,kernel/cellaigs.h))
 $(eval $(call add_include_file,kernel/celledges.h))
 $(eval $(call add_include_file,kernel/celltypes.h))

From 583db7b15edfd04e1030342b6235065d93180b26 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Thu, 18 Jul 2024 16:02:11 +0200
Subject: [PATCH 217/499] sigmap: comments

---
 kernel/hashlib.h  | 16 ++++++++++++++++
 kernel/sigtools.h | 12 ++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/kernel/hashlib.h b/kernel/hashlib.h
index e8ddddd3357..44ba893cf5c 100644
--- a/kernel/hashlib.h
+++ b/kernel/hashlib.h
@@ -1129,6 +1129,11 @@ class idict
 	const_iterator end() const { return const_iterator(*this, offset + size()); }
 };
 
+/**
+ * Union-find data structure with a promotion method
+ * mfp stands for "merge, find, promote"
+ * i-prefixed methods operate on indices in parents
+*/
 template<typename K, typename OPS>
 class mfp
 {
@@ -1142,13 +1147,18 @@ class mfp
 	{
 	}
 
+	// Finds a given element's index. If it isn't in the data structure,
+	// it is added as its own set
 	int operator()(const K &key) const
 	{
 		int i = database(key);
+		// If the lookup caused the database to grow,
+		// also add a corresponding entry in parents initialized to -1 (no parent)
 		parents.resize(database.size(), -1);
 		return i;
 	}
 
+	// Finds an element at given index
 	const K &operator[](int index) const
 	{
 		return database[index];
@@ -1161,6 +1171,11 @@ class mfp
 		while (parents[p] != -1)
 			p = parents[p];
 
+		// p is now the representative of i
+		// Now we traverse from i up to the representative again
+		// and make p the parent of all the nodes along the way.
+		// This is a side effect and doesn't affect the return value.
+		// It speeds up future find operations
 		while (k != p) {
 			int next_k = parents[k];
 			parents[k] = p;
@@ -1170,6 +1185,7 @@ class mfp
 		return p;
 	}
 
+	// Merge sets if the given indices belong to different sets
 	void imerge(int i, int j)
 	{
 		i = ifind(i);
diff --git a/kernel/sigtools.h b/kernel/sigtools.h
index 4ea43d74364..63f1b51ec84 100644
--- a/kernel/sigtools.h
+++ b/kernel/sigtools.h
@@ -229,6 +229,13 @@ using sort_by_name_id_guard = typename std::enable_if<std::is_same<T,RTLIL::Cell
 template<typename T>
 class SigSet<T, sort_by_name_id_guard<T>> : public SigSet<T, RTLIL::sort_by_name_id<typename std::remove_pointer<T>::type>> {};
 
+/**
+ * SigMap wraps a union-find "database"
+ * to map SigBits of a module to canonical representative SigBits.
+ * SigBits that are connected share a set in the underlying database.
+ * If a SigBit has a const state (impl: bit.wire is nullptr),
+ * it's promoted to a representative.
+ */
 struct SigMap
 {
 	mfp<SigBit> database;
@@ -249,6 +256,7 @@ struct SigMap
 		database.clear();
 	}
 
+	// Rebuild SigMap for all connections in module
 	void set(RTLIL::Module *module)
 	{
 		int bitcount = 0;
@@ -262,6 +270,7 @@ struct SigMap
 			add(it.first, it.second);
 	}
 
+	// Add connections from "from" to "to", bit-by-bit
 	void add(const RTLIL::SigSpec& from, const RTLIL::SigSpec& to)
 	{
 		log_assert(GetSize(from) == GetSize(to));
@@ -287,6 +296,7 @@ struct SigMap
 		}
 	}
 
+	// Add sig as disconnected from anything
 	void add(const RTLIL::SigBit &bit)
 	{
 		const auto &b = database.find(bit);
@@ -302,6 +312,7 @@ struct SigMap
 
 	inline void add(Wire *wire) { return add(RTLIL::SigSpec(wire)); }
 
+	// Modify bit to its representative
 	void apply(RTLIL::SigBit &bit) const
 	{
 		bit = database.find(bit);
@@ -332,6 +343,7 @@ struct SigMap
 		return sig;
 	}
 
+	// All non-const bits
 	RTLIL::SigSpec allbits() const
 	{
 		RTLIL::SigSpec sig;

From 72a0380da87bb90ee09724708149c53f99f7df5d Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Thu, 18 Jul 2024 16:37:14 +0200
Subject: [PATCH 218/499] ast: don't suggest use in external projects

---
 frontends/ast/ast.cc | 8 ++++----
 frontends/ast/ast.h  | 4 +++-
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 996f6715d05..d21b8f02d90 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -20,10 +20,10 @@
  *
  *  This is the AST frontend library.
  *
- *  The AST frontend library is not a frontend on it's own but provides a
- *  generic abstract syntax tree (AST) abstraction for HDL code and can be
- *  used by HDL frontends. See "ast.h" for an overview of the API and the
- *  Verilog frontend for an usage example.
+ *  The AST frontend library is not a frontend on its own but provides an
+ *  abstract syntax tree (AST) abstraction for the open source Verilog frontend
+ *  at frontends/verilog.
+ *
  *
  */
 
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 59a393e080e..6c4a1e15a65 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -17,7 +17,9 @@
  *
  *  ---
  *
- *  This is support code for the Verilog frontend at frontends/verilog
+ *  The AST frontend library is not a frontend on its own but provides an
+ *  abstract syntax tree (AST) abstraction for the open source Verilog frontend
+ *  at frontends/verilog.
  *
  */
 

From c94aa719d9c8533fdbfafdfed3df00885320f888 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 18 Jul 2024 16:56:52 +0200
Subject: [PATCH 219/499] VHDL is case insensitive, make sure netlist name is
 proper

---
 frontends/verific/verific.cc | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 56e94489cba..74a36a344ba 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -58,6 +58,7 @@ USING_YOSYS_NAMESPACE
 
 #ifdef VERIFIC_VHDL_SUPPORT
 #include "vhdl_file.h"
+#include "VhdlIdDef.h"
 #include "VhdlUnits.h"
 #include "NameSpace.h"
 #endif
@@ -2817,6 +2818,10 @@ std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist
 				if (show_message)
 					log("Adding VHDL unit '%s' to elaboration queue.\n", name);
 				vhdl_units.InsertLast(vhdl_unit);
+				if (strcmp(name, vhdl_unit->Id()->OrigName()) != 0) {
+					top_mod_names.erase(name);
+					top_mod_names.insert(vhdl_unit->Id()->OrigName());
+				}
 				continue;
 			}
 #endif

From 28ebefda4ac6f534d1e7d3f00224040df0fc5b81 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Fri, 19 Jul 2024 00:17:55 +0000
Subject: [PATCH 220/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 598ce843250..bd95cd1329f 100644
--- a/Makefile
+++ b/Makefile
@@ -148,7 +148,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.43+11
+YOSYS_VER := 0.43+22
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From bf758b909779491c9195c86b76594a5bf9803ef6 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 22 Jul 2024 20:59:56 +0200
Subject: [PATCH 221/499] Makefile: turn off LTO on gcc due to regression

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 310b23dce1c..e3a1a51136d 100644
--- a/Makefile
+++ b/Makefile
@@ -55,7 +55,7 @@ SANITIZER =
 
 # Prefer using ENABLE_DEBUG over setting these
 OPT_LEVEL := -O3
-GCC_LTO := -flto=auto
+GCC_LTO :=
 CLANG_LTO := -flto=thin
 
 PROGRAM_PREFIX :=

From a947572f38bb06c50e4ed22cec7c99a4db40de56 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 22 Jul 2024 21:33:46 +0200
Subject: [PATCH 222/499] Add lld to clang build environments and Dockerfile

---
 Dockerfile                                   | 1 +
 README.md                                    | 2 +-
 docs/source/getting_started/installation.rst | 2 +-
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/Dockerfile b/Dockerfile
index 549c73c9712..9806696e051 100644
--- a/Dockerfile
+++ b/Dockerfile
@@ -8,6 +8,7 @@ RUN apt-get update -qq \
  && DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \
     ca-certificates \
     clang \
+    lld \
     curl \
     libffi-dev \
     libreadline-dev \
diff --git a/README.md b/README.md
index bb1c4d443e4..59637b9bbb1 100644
--- a/README.md
+++ b/README.md
@@ -79,7 +79,7 @@ Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.
 For example on Ubuntu Linux 16.04 LTS the following commands will install all
 prerequisites for building yosys:
 
-	$ sudo apt-get install build-essential clang bison flex \
+	$ sudo apt-get install build-essential clang lld bison flex \
 		libreadline-dev gawk tcl-dev libffi-dev git \
 		graphviz xdot pkg-config python3 libboost-system-dev \
 		libboost-python-dev libboost-filesystem-dev zlib1g-dev
diff --git a/docs/source/getting_started/installation.rst b/docs/source/getting_started/installation.rst
index 1a89886089b..aea8b6a2dd2 100644
--- a/docs/source/getting_started/installation.rst
+++ b/docs/source/getting_started/installation.rst
@@ -94,7 +94,7 @@ Installing all prerequisites for Ubuntu 20.04:
 
 .. code:: console
 
-   sudo sudo apt-get install build-essential clang bison flex \
+   sudo sudo apt-get install build-essential clang lld bison flex \
       libreadline-dev gawk tcl-dev libffi-dev git make \
       graphviz xdot pkg-config python3 libboost-system-dev \
       libboost-python-dev libboost-filesystem-dev zlib1g-dev

From 5d0558932ebfa3212e88602140aebc666ecf5f59 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Mon, 22 Jul 2024 20:11:08 +0200
Subject: [PATCH 223/499] Add llvmPackages.bintools to buildInputs, otherwise
 we get a linkage error

---
 flake.nix | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/flake.nix b/flake.nix
index bafdc7bc4dc..90fa5328c09 100644
--- a/flake.nix
+++ b/flake.nix
@@ -18,7 +18,7 @@
         yosys = pkgs.clangStdenv.mkDerivation {
           name = "yosys";
           src = ./. ;
-          buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git pkg-configUpstream ];
+          buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git pkg-configUpstream llvmPackages.bintools ];
           checkInputs = with pkgs; [ gtest ];
           propagatedBuildInputs = [ abc-verifier ];
           preConfigure = "make config-clang";

From 8c1431f37337b5adb09341981121d140b8abdca7 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Tue, 23 Jul 2024 17:01:57 +0200
Subject: [PATCH 224/499] Guess VHDL frontend for both *.vhd and *vhdl files

---
 kernel/yosys.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index fca2bca6779..5a3e9eb2da6 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -1133,7 +1133,9 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi
 			command = " -vlog2k";
 		else if (filename_trim.size() > 2 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".sv") == 0)
 			command = " -sv";
-		else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".vhd") == 0)
+		else if ((filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".vhd") == 0)
+			 ||
+			 (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-5, std::string::npos, ".vhdl") == 0))
 			command = " -vhdl";
 		else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-5, std::string::npos, ".blif") == 0)
 			command = "blif";

From ce11ddbf219fecc4580619a0f989cde67707895b Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Tue, 23 Jul 2024 17:55:04 +0200
Subject: [PATCH 225/499] Simplified run_frontend by using a lambda function
 for file extension checks and combining blif and eblif into a single
 condition.

---
 kernel/yosys.cc | 61 +++++++++++++++++++++++++++----------------------
 1 file changed, 34 insertions(+), 27 deletions(-)

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 5a3e9eb2da6..efdc54b796c 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -1126,33 +1126,40 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi
 		design = yosys_design;
 
 	if (command == "auto") {
-		std::string filename_trim = filename;
-		if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".gz") == 0)
-			filename_trim.erase(filename_trim.size()-3);
-		if (filename_trim.size() > 2 && filename_trim.compare(filename_trim.size()-2, std::string::npos, ".v") == 0)
-			command = " -vlog2k";
-		else if (filename_trim.size() > 2 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".sv") == 0)
-			command = " -sv";
-		else if ((filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".vhd") == 0)
-			 ||
-			 (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-5, std::string::npos, ".vhdl") == 0))
-			command = " -vhdl";
-		else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-5, std::string::npos, ".blif") == 0)
-			command = "blif";
-		else if (filename_trim.size() > 5 && filename_trim.compare(filename_trim.size()-6, std::string::npos, ".eblif") == 0)
-			command = "blif";
-		else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-5, std::string::npos, ".json") == 0)
-			command = "json";
-		else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".il") == 0)
-			command = "rtlil";
-		else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".ys") == 0)
-			command = "script";
-		else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".tcl") == 0)
-			command = "tcl";
-		else if (filename == "-")
-			command = "script";
-		else
-			log_error("Can't guess frontend for input file `%s' (missing -f option)!\n", filename.c_str());
+	  std::string filename_trim = filename;
+	  
+	  auto has_extension = [](const std::string& filename, const std::string& extension) {
+	    if (filename.size() >= extension.size()) {
+	      return filename.compare(filename.size() - extension.size(), extension.size(), extension) == 0;
+	    }
+	    return false;
+	  };
+
+	  if (has_extension(filename_trim, ".gz")) {
+	    filename_trim.erase(filename_trim.size() - 3);
+	  }
+	  
+	  if (has_extension(filename_trim, ".v")) {
+	    command = " -vlog2k";
+	  } else if (has_extension(filename_trim, ".sv")) {
+	    command = " -sv";
+	  } else if (has_extension(filename_trim, ".vhd") || has_extension(filename_trim, ".vhdl")) {
+	    command = " -vhdl";
+	  } else if (has_extension(filename_trim, ".blif") || has_extension(filename_trim, ".eblif")) {
+	    command = "blif";
+	  } else if (has_extension(filename_trim, ".json")) {
+	    command = "json";
+	  } else if (has_extension(filename_trim, ".il")) {
+	    command = "rtlil";
+	  } else if (has_extension(filename_trim, ".ys")) {
+	    command = "script";
+	  } else if (has_extension(filename_trim, ".tcl")) {
+	    command = "tcl";
+	  } else if (filename == "-") {
+	    command = "script";
+	  } else {
+	    log_error("Can't guess frontend for input file `%s' (missing -f option)!\n", filename.c_str());
+	  }
 	}
 
 	if (command == "script")

From ad47844bbf525340ddea3c179754455a2c2325f9 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Wed, 24 Jul 2024 18:31:21 +0200
Subject: [PATCH 226/499] actions: macos install lld from llvm package

---
 .github/actions/setup-build-env/action.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/actions/setup-build-env/action.yml b/.github/actions/setup-build-env/action.yml
index 345b6db8ada..8f7ff4b426b 100644
--- a/.github/actions/setup-build-env/action.yml
+++ b/.github/actions/setup-build-env/action.yml
@@ -14,7 +14,7 @@ runs:
       if: runner.os == 'macOS'
       shell: bash
       run: |
-        HOMEBREW_NO_INSTALLED_DEPENDENTS_CHECK=1 brew install bison flex gawk libffi pkg-config bash autoconf
+        HOMEBREW_NO_INSTALLED_DEPENDENTS_CHECK=1 brew install bison flex gawk libffi pkg-config bash autoconf llvm
 
     - name: Linux runtime environment
       if: runner.os == 'Linux'

From 29d53bc94a063c202c3f31d2093b9ae3e27a52e0 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Wed, 24 Jul 2024 19:50:34 +0200
Subject: [PATCH 227/499] actions: try fix GITHUB_PATH

---
 .github/actions/setup-build-env/action.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.github/actions/setup-build-env/action.yml b/.github/actions/setup-build-env/action.yml
index 8f7ff4b426b..c5a0d14abdf 100644
--- a/.github/actions/setup-build-env/action.yml
+++ b/.github/actions/setup-build-env/action.yml
@@ -28,6 +28,7 @@ runs:
       shell: bash
       run: |
         echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
+        echo "$(brew --prefix llvm)/bin" >> $GITHUB_PATH
         echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH
         echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
         echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV

From 7cd27e118237b5736b8b80f1765635da65ed1256 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Wed, 24 Jul 2024 21:31:35 +0200
Subject: [PATCH 228/499] Makefile: remove accidental abc opt level override
 for wasi builds

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index e3a1a51136d..789695388ae 100644
--- a/Makefile
+++ b/Makefile
@@ -283,7 +283,7 @@ LINKFLAGS := $(WASIFLAGS) -Wl,-z,stack-size=1048576 $(filter-out -rdynamic,$(LIN
 LIBS := -lwasi-emulated-process-clocks $(filter-out -lrt,$(LIBS))
 ABCMKARGS += AR="$(AR)" RANLIB="$(RANLIB)"
 ABCMKARGS += ARCHFLAGS="$(WASIFLAGS) -D_WASI_EMULATED_PROCESS_CLOCKS -DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING -DABC_NO_RLIMIT"
-ABCMKARGS += OPTFLAGS="$(OPT_LEVEL)"
+ABCMKARGS += OPTFLAGS="-Os"
 EXE = .wasm
 
 DISABLE_SPAWN := 1

From 95667094266e775c5b37b3ea075bdae421ca64ef Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 25 Jul 2024 11:25:17 +0200
Subject: [PATCH 229/499] Initialize extensions when verific pass is registered

---
 frontends/verific/verific.cc | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 56e94489cba..dd6b788d088 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -3006,6 +3006,11 @@ bool check_noverific_env()
 
 struct VerificPass : public Pass {
 	VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }
+
+#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
+	void on_register() override	{ VerificExtensions::Reset(); }
+#endif
+
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|

From e063b96104985aedfc2ce9f518415fec1d2d2d5e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Thu, 25 Jul 2024 11:43:19 +0200
Subject: [PATCH 230/499] synthprop: Reformat the help

---
 passes/sat/synthprop.cc | 26 ++++++++------------------
 1 file changed, 8 insertions(+), 18 deletions(-)

diff --git a/passes/sat/synthprop.cc b/passes/sat/synthprop.cc
index 25416b6c4c3..5553abec2cc 100644
--- a/passes/sat/synthprop.cc
+++ b/passes/sat/synthprop.cc
@@ -185,35 +185,25 @@ struct SyntProperties : public Pass {
 		log("\n");
 		log("    synthprop [options]\n");
 		log("\n");
-		log("This creates synthesizable properties for selected module.\n");
+		log("This creates synthesizable properties for the selected module.\n");
 		log("\n");
 		log("\n");
 		log("    -name <portname>\n");
-		log("\n");
-		log("Name output port for assertions (default: assertions).\n");
-		log("\n");
+		log("        name of the output port for assertions (default: assertions).\n");
 		log("\n");
 		log("    -map <filename>\n");
-		log("\n");
-		log("Write port mapping for synthesizable properties.\n");
-		log("\n");
+		log("        write the port mapping for synthesizable properties into the given file.\n");
 		log("\n");
 		log("    -or_outputs\n");
-		log("\n");
-		log("Or all outputs together to create a single output that goes high when any\n");
-		log("property is violated, instead of generating individual output bits.\n");
-		log("\n");
+		log("        Or all outputs together to create a single output that goes high when\n");
+		log("        any property is violated, instead of generating individual output bits.\n");
 		log("\n");
 		log("    -reset <portname>\n");
-		log("\n");
-		log("Name of top-level reset input. Latch a high state on the generated outputs\n");
-		log("until an asynchronous top-level reset input is activated.\n");
-		log("\n");
+		log("        name of the top-level reset input. Latch a high state on the generated\n");
+		log("        outputs until an asynchronous top-level reset input is activated.\n");
 		log("\n");
 		log("    -resetn <portname>\n");
-		log("\n");
-		log("Name of top-level reset input (inverse polarity). Latch a high state on the\n");
-		log("generated outputs until an asynchronous top-level reset input is activated.\n");
+		log("        like above but with inverse polarity\n");
 		log("\n");
 		log("\n");
 	}

From 7ee685a0b02770f86263802a155955b8d1ebd00a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Thu, 25 Jul 2024 11:35:39 +0200
Subject: [PATCH 231/499] proc_rom: Set `src` on the emitted memory

---
 passes/proc/proc_rom.cc | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/passes/proc/proc_rom.cc b/passes/proc/proc_rom.cc
index ebc2377aafa..ae67745479d 100644
--- a/passes/proc/proc_rom.cc
+++ b/passes/proc/proc_rom.cc
@@ -183,6 +183,12 @@ struct RomWorker
 		mem.rd_ports.push_back(std::move(rd));
 
 		mem.emit();
+
+		if (sw->has_attribute(ID::src)) {
+			mem.inits[0].cell->attributes[ID::src] = sw->attributes[ID::src];
+			mem.rd_ports[0].cell->attributes[ID::src] = sw->attributes[ID::src];
+		}
+
 		for (auto cs: sw->cases)
 			delete cs;
 		sw->cases.clear();

From 610d27dc1c235d2080fc060bc8251a73453920b5 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Fri, 26 Jul 2024 00:17:42 +0000
Subject: [PATCH 232/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index bd95cd1329f..7a77ee4df74 100644
--- a/Makefile
+++ b/Makefile
@@ -148,7 +148,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.43+22
+YOSYS_VER := 0.43+26
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 1c41db69785ed9744b6274cdf30e8470df881257 Mon Sep 17 00:00:00 2001
From: James Meech <43966357+JamesTimothyMeech@users.noreply.github.com>
Date: Fri, 26 Jul 2024 13:53:08 +0100
Subject: [PATCH 233/499] Update interactive_investigation.rst

The text starting at line 118 refers to proc twice but it should refer to opt and then to proc.
---
 .../using_yosys/more_scripting/interactive_investigation.rst    | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/source/using_yosys/more_scripting/interactive_investigation.rst b/docs/source/using_yosys/more_scripting/interactive_investigation.rst
index db34f041bb9..03a1faefa73 100644
--- a/docs/source/using_yosys/more_scripting/interactive_investigation.rst
+++ b/docs/source/using_yosys/more_scripting/interactive_investigation.rst
@@ -115,7 +115,7 @@ leads us to the third diagram:
    
    Output of the third :cmd:ref:`show` command in :ref:`example_ys`
    
-Here we see that the :cmd:ref:`proc` command not only has removed the artifacts
+Here we see that the :cmd:ref:`opt` command not only has removed the artifacts
 left behind by :cmd:ref:`proc`, but also determined correctly that it can remove
 the first ``$mux`` cell without changing the behavior of the circuit.
 

From 960bca019639402df3211ad0687b01522a01ba22 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Sat, 27 Jul 2024 00:17:35 +0000
Subject: [PATCH 234/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 7a77ee4df74..456aa2a40ae 100644
--- a/Makefile
+++ b/Makefile
@@ -148,7 +148,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.43+26
+YOSYS_VER := 0.43+34
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 01fd72520fbde6131ebbc408fe1615b3169830c2 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Thu, 25 Jul 2024 22:09:13 +0200
Subject: [PATCH 235/499] proc_rom: test src attribute on memories

---
 tests/proc/proc_rom.ys | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tests/proc/proc_rom.ys b/tests/proc/proc_rom.ys
index 93fd5002bd8..8b91a9021c2 100644
--- a/tests/proc/proc_rom.ys
+++ b/tests/proc/proc_rom.ys
@@ -33,7 +33,7 @@ hierarchy -auto-top
 
 design -save orig
 proc
-select -assert-count 1 t:$memrd_v2
+select -assert-count 1 t:$memrd_v2 a:src %i
 memory
 opt_dff
 design -stash postopt
@@ -80,7 +80,7 @@ hierarchy -auto-top
 
 design -save orig
 proc
-select -assert-count 1 t:$memrd_v2
+select -assert-count 1 t:$memrd_v2 a:src %i
 memory
 opt_dff
 design -stash postopt
@@ -127,7 +127,7 @@ hierarchy -auto-top
 
 design -save orig
 proc
-select -assert-count 1 t:$memrd_v2
+select -assert-count 1 t:$memrd_v2 a:src %i
 memory
 opt_dff
 design -stash postopt
@@ -175,7 +175,7 @@ hierarchy -auto-top
 
 design -save orig
 proc
-select -assert-count 1 t:$memrd_v2
+select -assert-count 1 t:$memrd_v2 a:src %i
 memory
 opt_dff
 design -stash postopt

From 4b29f64142ea17b894dbdc95d31293d0e66fa612 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 29 Jul 2024 10:26:02 +0200
Subject: [PATCH 236/499] cost: add model for techmapped cell count,
 keep_hierarchy pass with -min_cost parameter

---
 Makefile                           |   2 +-
 kernel/cost.cc                     | 195 +++++++++++++++++++++++++++++
 kernel/cost.h                      |  65 ++++------
 passes/cmds/stat.cc                |   2 -
 passes/hierarchy/Makefile.inc      |   1 +
 passes/hierarchy/keep_hierarchy.cc |  74 +++++++++++
 passes/tests/test_cell.cc          | 108 +++++++++++++---
 7 files changed, 383 insertions(+), 64 deletions(-)
 create mode 100644 kernel/cost.cc
 create mode 100644 passes/hierarchy/keep_hierarchy.cc

diff --git a/Makefile b/Makefile
index 456aa2a40ae..e52c69bf953 100644
--- a/Makefile
+++ b/Makefile
@@ -625,7 +625,7 @@ $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h))
 
 OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o
 OBJS += kernel/binding.o
-OBJS += kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o
+OBJS += kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o
 ifeq ($(ENABLE_ZLIB),1)
 OBJS += kernel/fstdata.o
 endif
diff --git a/kernel/cost.cc b/kernel/cost.cc
new file mode 100644
index 00000000000..5d897ab7a1c
--- /dev/null
+++ b/kernel/cost.cc
@@ -0,0 +1,195 @@
+#include "kernel/cost.h"
+
+USING_YOSYS_NAMESPACE
+
+unsigned int CellCosts::get(RTLIL::Module *mod)
+{
+	if (mod_cost_cache_.count(mod->name))
+		return mod_cost_cache_.at(mod->name);
+
+	unsigned int module_cost = 1;
+	for (auto c : mod->cells()) {
+		unsigned int new_cost = module_cost + get(c);
+		module_cost = new_cost >= module_cost ? new_cost : INT_MAX;
+	}
+
+	mod_cost_cache_[mod->name] = module_cost;
+	return module_cost;
+}
+
+static unsigned int y_coef(RTLIL::IdString type)
+{
+	if (
+	  // equality
+	  type.in(ID($bweqx), ID($nex), ID($eqx)) ||
+	  // basic logic
+	  type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($not)) ||
+	  // mux
+	  type.in(ID($bwmux), ID($mux)) ||
+	  // others
+	  type == ID($tribuf)) {
+		return 1;
+	} else if (type == ID($neg)) {
+		return 4;
+	} else if (type == ID($demux)) {
+		return 2;
+	} else if (type == ID($fa)) {
+		return 5;
+	} else if (type.in(ID($add), ID($sub), ID($alu))) {
+		// multi-bit adders
+		return 8;
+	} else if (type.in(ID($shl), ID($sshl))) {
+		// left shift
+		return 10;
+	}
+	return 0;
+}
+
+static unsigned int max_inp_coef(RTLIL::IdString type)
+{
+	if (
+	  // binop reduce
+	  type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool)) ||
+	  // others
+	  type.in(ID($logic_not), ID($pmux), ID($bmux))) {
+		return 1;
+	} else if (
+	  // equality
+	  type.in(ID($eq), ID($ne)) ||
+	  // logic
+	  type.in(ID($logic_and), ID($logic_or))) {
+		return 2;
+	} else if (type == ID($lcu)) {
+		return 5;
+	} else if (type.in(ID($lt), ID($le), ID($ge), ID($gt))) {
+		// comparison
+		return 7;
+	}
+	return 0;
+}
+
+static unsigned int sum_coef(RTLIL::IdString type)
+{
+	if (type.in(ID($shr), ID($sshr))) {
+		// right shift
+		return 4;
+	} else if (type.in(ID($shift), ID($shiftx))) {
+		// shift
+		return 8;
+	}
+	return 0;
+}
+
+static unsigned int is_div_mod(RTLIL::IdString type)
+{
+	return (type == ID($div) || type == ID($divfloor) || type == ID($mod) || type == ID($modfloor));
+}
+
+static bool is_free(RTLIL::IdString type)
+{
+	return (
+	  // tags
+	  type.in(ID($overwrite_tag), ID($set_tag), ID($original_tag), ID($get_tag)) ||
+	  // formal
+	  type.in(ID($check), ID($equiv), ID($initstate), ID($assert), ID($assume), ID($live), ID($cover), ID($fair)) ||
+	  type.in(ID($allseq), ID($allconst), ID($anyseq), ID($anyconst), ID($anyinit)) ||
+	  // utilities
+	  type.in(ID($scopeinfo), ID($print)) ||
+	  // real but free
+	  type.in(ID($concat), ID($slice), ID($pos)) ||
+	  // specify
+	  type.in(ID($specrule), ID($specify2), ID($specify3)));
+}
+
+unsigned int max_inp_width(RTLIL::Cell *cell)
+{
+	unsigned int max = 0;
+	RTLIL::IdString input_width_params[] = {
+	  ID::WIDTH,
+	  ID::A_WIDTH,
+	  ID::B_WIDTH,
+	  ID::S_WIDTH,
+	};
+
+	if (cell->type == ID($bmux))
+		return cell->getParam(ID::WIDTH).as_int() << cell->getParam(ID::S_WIDTH).as_int();
+
+	for (RTLIL::IdString param : input_width_params)
+		if (cell->hasParam(param))
+			max = std::max(max, (unsigned int)cell->getParam(param).as_int());
+	return max;
+}
+
+unsigned int port_width_sum(RTLIL::Cell *cell)
+{
+	unsigned int sum = 0;
+	RTLIL::IdString port_width_params[] = {
+	  ID::WIDTH, ID::A_WIDTH, ID::B_WIDTH, ID::S_WIDTH, ID::Y_WIDTH,
+	};
+
+	for (auto param : port_width_params)
+		if (cell->hasParam(param))
+			sum += cell->getParam(param).as_int();
+
+	return sum;
+}
+
+unsigned int CellCosts::get(RTLIL::Cell *cell)
+{
+
+	// simple 1-bit cells
+	if (cmos_gate_cost().count(cell->type))
+		return 1;
+
+	if (design_ && design_->module(cell->type) && cell->parameters.empty()) {
+		log_debug("%s is a module, recurse\n", cell->name.c_str());
+		return get(design_->module(cell->type));
+	} else if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
+		log_assert(cell->hasPort(ID::Q) && "Weird flip flop");
+		log_debug("%s is ff\n", cell->name.c_str());
+		return cell->getParam(ID::WIDTH).as_int();
+	} else if (y_coef(cell->type)) {
+		// linear with Y_WIDTH or WIDTH
+		log_assert((cell->hasParam(ID::Y_WIDTH) || cell->hasParam(ID::WIDTH)) && "Unknown width");
+		auto param = cell->hasParam(ID::Y_WIDTH) ? ID::Y_WIDTH : ID::WIDTH;
+		int width = cell->getParam(param).as_int();
+		if (cell->type == ID($demux))
+			width <<= cell->getParam(ID::S_WIDTH).as_int();
+		log_debug("%s Y*coef %d * %d\n", cell->name.c_str(), width, y_coef(cell->type));
+		return width * y_coef(cell->type);
+	} else if (sum_coef(cell->type)) {
+		// linear with sum of port widths
+		unsigned int sum = port_width_sum(cell);
+		log_debug("%s sum*coef %d * %d\n", cell->name.c_str(), sum, sum_coef(cell->type));
+		return sum * sum_coef(cell->type);
+	} else if (max_inp_coef(cell->type)) {
+		// linear with largest input width
+		unsigned int max = max_inp_width(cell);
+		log_debug("%s max*coef %d * %d\n", cell->name.c_str(), max, max_inp_coef(cell->type));
+		return max * max_inp_coef(cell->type);
+	} else if (is_div_mod(cell->type) || cell->type == ID($mul)) {
+		// quadratic with sum of port widths
+		unsigned int sum = port_width_sum(cell);
+		unsigned int coef = cell->type == ID($mul) ? 3 : 5;
+		log_debug("%s coef*(sum**2) %d * %d\n", cell->name.c_str(), coef, sum * sum);
+		return coef * sum * sum;
+	} else if (cell->type == ID($lut)) {
+		int width = cell->getParam(ID::WIDTH).as_int();
+		unsigned int cost = 1U << (unsigned int)width;
+		log_debug("%s is 2**%d\n", cell->name.c_str(), width);
+		return cost;
+	} else if (cell->type == ID($sop)) {
+		int width = cell->getParam(ID::WIDTH).as_int();
+		int depth = cell->getParam(ID::DEPTH).as_int();
+		log_debug("%s is (2*%d + 1)*%d\n", cell->name.c_str(), width, depth);
+		return (2 * width + 1) * depth;
+	} else if (is_free(cell->type)) {
+		log_debug("%s is free\n", cell->name.c_str());
+		return 0;
+	}
+	// TODO: $fsm $mem.* $macc
+	// ignored: $pow
+
+	log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(cell->type), GetSize(cell->parameters));
+	return 1;
+}
diff --git a/kernel/cost.h b/kernel/cost.h
index b81420af756..15d74d7b30e 100644
--- a/kernel/cost.h
+++ b/kernel/cost.h
@@ -26,7 +26,17 @@ YOSYS_NAMESPACE_BEGIN
 
 struct CellCosts
 {
+
+	private:
+	dict<RTLIL::IdString, int> mod_cost_cache_;
+	Design *design_ = nullptr;
+
+	public:
+	CellCosts(RTLIL::Design *design) : design_(design) { }
+
 	static const dict<RTLIL::IdString, int>& default_gate_cost() {
+		// Default size heuristics for several common PDK standard cells
+		// used by abc and stat
 		static const dict<RTLIL::IdString, int> db = {
 			{ ID($_BUF_),    1 },
 			{ ID($_NOT_),    2 },
@@ -43,12 +53,14 @@ struct CellCosts
 			{ ID($_AOI4_),   7 },
 			{ ID($_OAI4_),   7 },
 			{ ID($_MUX_),    4 },
-			{ ID($_NMUX_),   4 }
+			{ ID($_NMUX_),   4 },
 		};
 		return db;
 	}
 
 	static const dict<RTLIL::IdString, int>& cmos_gate_cost() {
+		// Estimated CMOS transistor counts for several common PDK standard cells
+		// used by stat and optionally by abc
 		static const dict<RTLIL::IdString, int> db = {
 			{ ID($_BUF_),     1 },
 			{ ID($_NOT_),     2 },
@@ -65,50 +77,21 @@ struct CellCosts
 			{ ID($_AOI4_),    8 },
 			{ ID($_OAI4_),    8 },
 			{ ID($_MUX_),    12 },
-			{ ID($_NMUX_),   10 }
+			{ ID($_NMUX_),   10 },
+			{ ID($_DFF_P_),  16 },
+			{ ID($_DFF_N_),  16 },
 		};
 		return db;
 	}
 
-	dict<RTLIL::IdString, int> mod_cost_cache;
-	const dict<RTLIL::IdString, int> *gate_cost = nullptr;
-	Design *design = nullptr;
-
-	int get(RTLIL::IdString type) const
-	{
-		if (gate_cost && gate_cost->count(type))
-			return gate_cost->at(type);
-
-		log_warning("Can't determine cost of %s cell.\n", log_id(type));
-		return 1;
-	}
-
-	int get(RTLIL::Cell *cell)
-	{
-		if (gate_cost && gate_cost->count(cell->type))
-			return gate_cost->at(cell->type);
-
-		if (design && design->module(cell->type) && cell->parameters.empty())
-		{
-			RTLIL::Module *mod = design->module(cell->type);
-
-			if (mod->attributes.count(ID(cost)))
-				return mod->attributes.at(ID(cost)).as_int();
-
-			if (mod_cost_cache.count(mod->name))
-				return mod_cost_cache.at(mod->name);
-
-			int module_cost = 1;
-			for (auto c : mod->cells())
-				module_cost += get(c);
-
-			mod_cost_cache[mod->name] = module_cost;
-			return module_cost;
-		}
-
-		log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(cell->type), GetSize(cell->parameters));
-		return 1;
-	}
+	// Get the cell cost for a cell based on its parameters.
+	// This cost is an *approximate* upper bound for the number of gates that
+	// the cell will get mapped to with "opt -fast; techmap"
+	// The intended usage is for flattening heuristics and similar situations
+	unsigned int get(RTLIL::Cell *cell);
+	// Sum up the cell costs of all cells in the module
+	// and all its submodules recursively
+	unsigned int get(RTLIL::Module *mod);
 };
 
 YOSYS_NAMESPACE_END
diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index c2bb72f3bb3..379ce209790 100644
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -230,8 +230,6 @@ struct statdata_t
 
 			if (gate_costs.count(ctype))
 				tran_cnt += cnum * gate_costs.at(ctype);
-			else if (ctype.in(ID($_DFF_P_), ID($_DFF_N_)))
-				tran_cnt += cnum * 16;
 			else
 				*tran_cnt_exact = false;
 		}
diff --git a/passes/hierarchy/Makefile.inc b/passes/hierarchy/Makefile.inc
index b3f139b72e7..3cd1b6180c6 100644
--- a/passes/hierarchy/Makefile.inc
+++ b/passes/hierarchy/Makefile.inc
@@ -2,4 +2,5 @@
 OBJS += passes/hierarchy/hierarchy.o
 OBJS += passes/hierarchy/uniquify.o
 OBJS += passes/hierarchy/submod.o
+OBJS += passes/hierarchy/keep_hierarchy.o
 
diff --git a/passes/hierarchy/keep_hierarchy.cc b/passes/hierarchy/keep_hierarchy.cc
new file mode 100644
index 00000000000..6b947e67370
--- /dev/null
+++ b/passes/hierarchy/keep_hierarchy.cc
@@ -0,0 +1,74 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/cost.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct KeepHierarchyPass : public Pass {
+	KeepHierarchyPass() : Pass("keep_hierarchy", "add the keep_hierarchy attribute") {}
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    keep_hierarchy [options]\n");
+		log("\n");
+		log("Add the keep_hierarchy attribute.\n");
+		log("\n");
+		log("    -min_cost <min_cost>\n");
+		log("        only add the attribute to modules estimated to have more\n");
+		log("        than <min_cost> gates after simple techmapping. Intended\n");
+		log("        for tuning trade-offs between quality and yosys runtime.\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		unsigned int min_cost = 0;
+
+		log_header(design, "Executing KEEP_HIERARCHY pass.\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-min_cost" && argidx+1 < args.size()) {
+				min_cost = std::stoi(args[++argidx].c_str());
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		CellCosts costs(design);
+
+		for (auto module : design->selected_modules()) {
+			if (min_cost) {
+				unsigned int cost = costs.get(module);
+				if (cost > min_cost) {
+					log("Marking %s (module too big: %d > %d).\n", log_id(module), cost, min_cost);
+					module->set_bool_attribute(ID::keep_hierarchy);
+				}
+			} else {
+				log("Marking %s.\n", log_id(module));
+				module->set_bool_attribute(ID::keep_hierarchy);
+			}
+		}
+	}
+} KeepHierarchyPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index e21ec452cc8..fc2aac2f83d 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -23,11 +23,13 @@
 #include "kernel/consteval.h"
 #include "kernel/celledges.h"
 #include "kernel/macc.h"
+#include "kernel/cost.h"
 #include <algorithm>
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+static int bloat_factor = 1;
 static uint32_t xorshift32_state = 123456789;
 
 static uint32_t xorshift32(uint32_t limit) {
@@ -37,7 +39,7 @@ static uint32_t xorshift32(uint32_t limit) {
 	return xorshift32_state % limit;
 }
 
-static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, std::string cell_type_flags, bool constmode, bool muxdiv)
+static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, std::string cell_type_flags, bool constmode, bool muxdiv)
 {
 	RTLIL::Module *module = design->addModule(ID(gold));
 	RTLIL::Cell *cell = module->addCell(ID(UUT), cell_type);
@@ -45,7 +47,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 
 	if (cell_type.in(ID($mux), ID($pmux)))
 	{
-		int width = 1 + xorshift32(8);
+		int width = 1 + xorshift32(8 * bloat_factor);
 		int swidth = cell_type == ID($mux) ? 1 : 1 + xorshift32(8);
 
 		wire = module->addWire(ID::A);
@@ -71,8 +73,8 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 
 	if (cell_type == ID($bmux))
 	{
-		int width = 1 + xorshift32(8);
-		int swidth = 1 + xorshift32(4);
+		int width = 1 + xorshift32(8 * bloat_factor);
+		int swidth = 1 + xorshift32(4 * bloat_factor);
 
 		wire = module->addWire(ID::A);
 		wire->width = width << swidth;
@@ -92,8 +94,8 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 
 	if (cell_type == ID($demux))
 	{
-		int width = 1 + xorshift32(8);
-		int swidth = 1 + xorshift32(6);
+		int width = 1 + xorshift32(8 * bloat_factor);
+		int swidth = 1 + xorshift32(6 * bloat_factor);
 
 		wire = module->addWire(ID::A);
 		wire->width = width;
@@ -113,7 +115,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 
 	if (cell_type == ID($fa))
 	{
-		int width = 1 + xorshift32(8);
+		int width = 1 + xorshift32(8 * bloat_factor);
 
 		wire = module->addWire(ID::A);
 		wire->width = width;
@@ -143,7 +145,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 
 	if (cell_type == ID($lcu))
 	{
-		int width = 1 + xorshift32(8);
+		int width = 1 + xorshift32(8 * bloat_factor);
 
 		wire = module->addWire(ID::P);
 		wire->width = width;
@@ -168,7 +170,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 	if (cell_type == ID($macc))
 	{
 		Macc macc;
-		int width = 1 + xorshift32(8);
+		int width = 1 + xorshift32(8 * bloat_factor);
 		int depth = 1 + xorshift32(6);
 		int mulbits_a = 0, mulbits_b = 0;
 
@@ -215,7 +217,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 
 	if (cell_type == ID($lut))
 	{
-		int width = 1 + xorshift32(6);
+		int width = 1 + xorshift32(6 * bloat_factor);
 
 		wire = module->addWire(ID::A);
 		wire->width = width;
@@ -235,8 +237,8 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 
 	if (cell_type == ID($sop))
 	{
-		int width = 1 + xorshift32(8);
-		int depth = 1 + xorshift32(8);
+		int width = 1 + xorshift32(8 * bloat_factor);
+		int depth = 1 + xorshift32(8 * bloat_factor);
 
 		wire = module->addWire(ID::A);
 		wire->width = width;
@@ -270,7 +272,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 
 	if (cell_type_flags.find('A') != std::string::npos) {
 		wire = module->addWire(ID::A);
-		wire->width = 1 + xorshift32(8);
+		wire->width = 1 + xorshift32(8 * bloat_factor);
 		wire->port_input = true;
 		cell->setPort(ID::A, wire);
 	}
@@ -278,9 +280,9 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 	if (cell_type_flags.find('B') != std::string::npos) {
 		wire = module->addWire(ID::B);
 		if (cell_type_flags.find('h') != std::string::npos)
-			wire->width = 1 + xorshift32(6);
+			wire->width = 1 + xorshift32(6 * bloat_factor);
 		else
-			wire->width = 1 + xorshift32(8);
+			wire->width = 1 + xorshift32(8 * bloat_factor);
 		wire->port_input = true;
 		cell->setPort(ID::B, wire);
 	}
@@ -301,7 +303,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 
 	if (cell_type_flags.find('Y') != std::string::npos) {
 		wire = module->addWire(ID::Y);
-		wire->width = 1 + xorshift32(8);
+		wire->width = 1 + xorshift32(8 * bloat_factor);
 		wire->port_output = true;
 		cell->setPort(ID::Y, wire);
 	}
@@ -380,6 +382,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 	module->fixup_ports();
 	cell->fixup_parameters();
 	cell->check();
+	return cell;
 }
 
 static void run_edges_test(RTLIL::Design *design, bool verbose)
@@ -752,6 +755,9 @@ struct TestCellPass : public Pass {
 		log("    -noeval\n");
 		log("        do not check const-eval models\n");
 		log("\n");
+		log("    -noopt\n");
+		log("        do not opt tecchmapped design\n");
+		log("\n");
 		log("    -edges\n");
 		log("        test cell edges db creator against sat-based implementation\n");
 		log("\n");
@@ -760,6 +766,11 @@ struct TestCellPass : public Pass {
 		log("\n");
 		log("    -vlog {filename}\n");
 		log("        create a Verilog test bench to test simlib and write_verilog\n");
+		log("    -bloat {factor}\n");
+		log("        increase cell size limits b{factor} times where possible\n");
+		log("    -check_cost\n");
+		log("        check if the estimated cell cost is a valid upper bound for\n");
+		log("        the techmapped cell count \n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design*) override
@@ -774,7 +785,9 @@ struct TestCellPass : public Pass {
 		bool constmode = false;
 		bool nosat = false;
 		bool noeval = false;
+		bool noopt = false;
 		bool edges = false;
+		bool check_cost = false;
 
 		int argidx;
 		for (argidx = 1; argidx < GetSize(args); argidx++)
@@ -828,6 +841,10 @@ struct TestCellPass : public Pass {
 				noeval = true;
 				continue;
 			}
+			if (args[argidx] == "-noopt") {
+				noopt = true;
+				continue;
+			}
 			if (args[argidx] == "-edges") {
 				edges = true;
 				continue;
@@ -842,6 +859,14 @@ struct TestCellPass : public Pass {
 					log_cmd_error("Failed to open output file `%s'.\n", args[argidx].c_str());
 				continue;
 			}
+			if (args[argidx] == "-bloat" && argidx+1 < GetSize(args)) {
+				bloat_factor = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-check_cost") {
+				check_cost = true;
+				continue;
+			}
 			break;
 		}
 
@@ -965,21 +990,30 @@ struct TestCellPass : public Pass {
 
 		std::vector<std::string> uut_names;
 
-		for (auto cell_type : selected_cell_types)
+		for (auto cell_type : selected_cell_types) {
+			// Cells that failed cell cost check
+			int failed = 0;
+			// How much bigger is the worst offender than estimated?
+			int worst_abs = 0;
+			// How many times is it bigger than estimated?
+			float worst_rel = 0.0;
 			for (int i = 0; i < num_iter; i++)
 			{
+				Cell* uut = nullptr;
 				RTLIL::Design *design = new RTLIL::Design;
 				if (cell_type == ID(rtlil))
 					Frontend::frontend_call(design, NULL, std::string(), "rtlil " + rtlil_file);
 				else
-					create_gold_module(design, cell_type, cell_types.at(cell_type), constmode, muxdiv);
+					uut = create_gold_module(design, cell_type, cell_types.at(cell_type), constmode, muxdiv);
 				if (!write_prefix.empty()) {
 					Pass::call(design, stringf("write_rtlil %s_%s_%05d.il", write_prefix.c_str(), cell_type.c_str()+1, i));
 				} else if (edges) {
 					Pass::call(design, "dump gold");
 					run_edges_test(design, verbose);
 				} else {
-					Pass::call(design, stringf("copy gold gate; cd gate; %s; cd ..; opt -fast gate", techmap_cmd.c_str()));
+					Pass::call(design, stringf("copy gold gate; cd gate; %s; cd ..", techmap_cmd.c_str()));
+					if (!noopt)
+						Pass::call(design, "opt -fast gate");
 					if (!nosat)
 						Pass::call(design, "miter -equiv -flatten -make_outputs -ignore_gold_x gold gate miter");
 					if (verbose)
@@ -997,10 +1031,44 @@ struct TestCellPass : public Pass {
 					}
 					if (!noeval)
 						run_eval_test(design, verbose, nosat, uut_name, vlog_file);
+					if (check_cost && uut) {
+						Pass::call(design, "select gate");
+						int num_cells = 0;
+						for (auto mod : design->selected_modules()) {
+							// Expected to run once
+							for (auto cell : mod->selected_cells()) {
+								(void) cell;
+								num_cells++;
+							}
+						}
+						CellCosts costs(design);
+						Pass::call(design, "select gold");
+						for (auto mod : design->selected_modules()) {
+							log_assert(mod->name.str() == "\\gold");
+							// Expected to run once
+							int num_cells_estimate = costs.get(uut);
+							if (num_cells <= num_cells_estimate) {
+								log_debug("Correct upper bound for %s: %d <= %d\n", cell_type.c_str(), num_cells, num_cells_estimate);
+							} else {
+								failed++;
+								if (worst_abs < num_cells - num_cells_estimate) {
+									worst_abs = num_cells - num_cells_estimate;
+									worst_rel = (float)(num_cells - num_cells_estimate) / (float)num_cells_estimate;
+								}
+								log_warning("Upper bound violated for %s: %d > %d\n", cell_type.c_str(), num_cells, num_cells_estimate);
+							}
+						}
+					}
 				}
 				delete design;
 			}
-
+			if (check_cost && failed) {
+				log_warning("Cell type %s cost underestimated in %.1f%% cases "
+					    "with worst offender being by %d (%.1f%%)\n",
+					    cell_type.c_str(), 100 * (float)failed / (float)num_iter,
+						worst_abs, 100 * worst_rel);
+			}
+		}
 		if (vlog_file.is_open()) {
 			vlog_file << "\nmodule testbench;\n";
 			for (auto &uut : uut_names)

From af0c2fa659b89764d824b230722b266f92a5a450 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 29 Jul 2024 15:13:24 +0200
Subject: [PATCH 237/499] Brewfile: add llvm for lld

---
 Brewfile | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Brewfile b/Brewfile
index b50c70a4b0e..18e4e2917e9 100644
--- a/Brewfile
+++ b/Brewfile
@@ -9,4 +9,5 @@ brew "python3"
 brew "tcl-tk"
 brew "xdot"
 brew "bash"
-brew 'boost-python3'
+brew "boost-python3"
+brew "llvm"

From 405897a9719cb2409233fc8a310282c0dbe2ae8b Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 29 Jul 2024 15:50:38 +0200
Subject: [PATCH 238/499] Update top value that is returned back to hierarchy
 pass

---
 frontends/verific/verific.cc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 74a36a344ba..5a0e6113fa9 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2760,7 +2760,7 @@ void import_all(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *
 #endif
 }
 
-std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED, std::vector<std::string> &tops)
+std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED, std::vector<std::string> &tops, std::string *top = nullptr)
 {
 	std::set<std::string> top_mod_names;
 	Array *netlists = nullptr;
@@ -2821,6 +2821,8 @@ std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist
 				if (strcmp(name, vhdl_unit->Id()->OrigName()) != 0) {
 					top_mod_names.erase(name);
 					top_mod_names.insert(vhdl_unit->Id()->OrigName());
+					if (top && *top == name)
+						*top = vhdl_unit->Id()->OrigName();
 				}
 				continue;
 			}
@@ -2962,7 +2964,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 		veri_file::RemoveAllLOptions();
 		veri_file::AddLOption("work");
 #endif
-		top_mod_names = import_tops("work", &nl_todo, &verific_params, false, "", tops) ;
+		top_mod_names = import_tops("work", &nl_todo, &verific_params, false, "", tops, &top) ;
 	}
 
 	if (!verific_error_msg.empty())

From c788484679a5d551bf554f8789f86d05338cb0bc Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Tue, 30 Jul 2024 00:18:19 +0000
Subject: [PATCH 239/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index f6186499307..bc9633db5e7 100644
--- a/Makefile
+++ b/Makefile
@@ -153,7 +153,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.43+34
+YOSYS_VER := 0.43+86
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 7e341429651d4efa38d829250631d63cb79840ce Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Tue, 30 Jul 2024 22:47:30 +0200
Subject: [PATCH 240/499] Run nix build also on macos. Build with more logs

---
 .github/workflows/extra-builds.yml | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml
index d7c6e13ff06..1a00d016347 100644
--- a/.github/workflows/extra-builds.yml
+++ b/.github/workflows/extra-builds.yml
@@ -86,7 +86,11 @@ jobs:
     name: "Build nix flake"
     needs: pre_job
     if: needs.pre_job.outputs.should_skip != 'true'
-    runs-on: ubuntu-latest
+    runs-on: ${{ matrix.os }}
+    strategy:
+      matrix:
+        os: [ubuntu-latest, macos-latest]
+      fail-fast: false
     steps:
       - uses: actions/checkout@v4
         with:
@@ -94,4 +98,4 @@ jobs:
       - uses: cachix/install-nix-action@v26
         with:
           install_url: https://releases.nixos.org/nix/nix-2.18.1/install
-      - run: nix build .?submodules=1
+      - run: nix build .?submodules=1 -L

From 6d98418f3d8f15cd7c561622d7a55158ff88c80f Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 2 Aug 2024 15:23:00 +0200
Subject: [PATCH 241/499] Set ranges on exported wires in VCD and FST

---
 passes/sat/sim.cc | 40 ++++++++++++++++++++++++++++------------
 1 file changed, 28 insertions(+), 12 deletions(-)

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index aeed16b9784..dd17a2eba9d 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -2317,6 +2317,23 @@ struct SimWorker : SimShared
 	}
 };
 
+std::string form_vcd_name(const char *name, int size, Wire *w)
+{
+	std::string full_name = name;
+	bool have_bracket = strchr(name, '[');
+	if (w) {
+		if (have_bracket || !(w->start_offset==0 && w->width==1)) {
+			full_name += stringf(" [%d:%d]",
+				w->upto ? w->start_offset : w->start_offset + w->width - 1,
+				w->upto ? w->start_offset + w->width - 1 : w->start_offset);
+		}
+	} else {
+		// Special handling for memories
+		full_name += have_bracket ? stringf(" [%d:0]", size - 1) : std::string();
+	}
+	return full_name;
+}
+
 struct VCDWriter : public OutputWriter
 {
 	VCDWriter(SimWorker *worker, std::string filename) : OutputWriter(worker) {
@@ -2342,16 +2359,14 @@ struct VCDWriter : public OutputWriter
 		worker->top->write_output_header(
 			[this](IdString name) { vcdfile << stringf("$scope module %s $end\n", log_id(name)); },
 			[this]() { vcdfile << stringf("$upscope $end\n");},
-			[this,use_signal](const char *name, int size, Wire *, int id, bool is_reg) {
-				if (use_signal.at(id)) {
-					// Works around gtkwave trying to parse everything past the last [ in a signal
-					// name. While the emitted range doesn't necessarily match the wire's range,
-					// this is consistent with the range gtkwave makes up if it doesn't find a
-					// range
-					std::string range = strchr(name, '[') ? stringf("[%d:0]", size - 1) : std::string();
-					vcdfile << stringf("$var %s %d n%d %s%s%s $end\n", is_reg ? "reg" : "wire", size, id, name[0] == '$' ? "\\" : "", name, range.c_str());
-
-				}
+			[this,use_signal](const char *name, int size, Wire *w, int id, bool is_reg) {
+				if (!use_signal.at(id)) return;
+				// Works around gtkwave trying to parse everything past the last [ in a signal
+				// name. While the emitted range doesn't necessarily match the wire's range,
+				// this is consistent with the range gtkwave makes up if it doesn't find a
+				// range
+				std::string full_name = form_vcd_name(name, size, w);
+				vcdfile << stringf("$var %s %d n%d %s%s $end\n", is_reg ? "reg" : "wire", size, id, name[0] == '$' ? "\\" : "", full_name.c_str());
 			}
 		);
 
@@ -2410,10 +2425,11 @@ struct FSTWriter : public OutputWriter
 	   	worker->top->write_output_header(
 			[this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, stringf("%s",log_id(name)).c_str(), nullptr); },
 			[this]() { fstWriterSetUpscope(fstfile); },
-			[this,use_signal](const char *name, int size, Wire *, int id, bool is_reg) {
+			[this,use_signal](const char *name, int size, Wire *w, int id, bool is_reg) {
 				if (!use_signal.at(id)) return;
+				std::string full_name = form_vcd_name(name, size, w);
 				fstHandle fst_id = fstWriterCreateVar(fstfile, is_reg ? FST_VT_VCD_REG : FST_VT_VCD_WIRE, FST_VD_IMPLICIT, size,
-												name, 0);
+												full_name.c_str(), 0);
 				mapping.emplace(id, fst_id);
 			}
 		);

From eeecb54532291d3e14d2fa943f17aef5e03ce49a Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 5 Aug 2024 19:28:09 +0200
Subject: [PATCH 242/499] Makefile: no LTO and lld by default

---
 .github/workflows/test-build.yml   |  2 +-
 .github/workflows/test-verific.yml |  2 +-
 Makefile                           |  4 +++-
 README.md                          | 11 +++++++++++
 4 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index bf95688a15c..0eb2c65c51c 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -56,7 +56,7 @@ jobs:
           mkdir build
           cd build
           make -f ../Makefile config-$CC
-          make -f ../Makefile -j$procs
+          make -f ../Makefile -j$procs ENABLE_LTO=1
 
       - name: Log yosys-config output
         run: |
diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml
index 5b6268a2eaf..e08f7bd2e0f 100644
--- a/.github/workflows/test-verific.yml
+++ b/.github/workflows/test-verific.yml
@@ -41,7 +41,7 @@ jobs:
           echo "ENABLE_VERIFIC_LIBERTY := 1" >> Makefile.conf
           echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1" >> Makefile.conf
           echo "ENABLE_CCACHE := 1" >> Makefile.conf
-          make -j${{ env.procs }}
+          make -j${{ env.procs }} ENABLE_LTO=1
 
       - name: Install Yosys
         run: |
diff --git a/Makefile b/Makefile
index bc9633db5e7..4b9cd97da10 100644
--- a/Makefile
+++ b/Makefile
@@ -34,7 +34,7 @@ ENABLE_PYOSYS := 0
 ENABLE_GCOV := 0
 ENABLE_GPROF := 0
 ENABLE_DEBUG := 0
-ENABLE_LTO := 1
+ENABLE_LTO := 0
 ENABLE_CCACHE := 0
 # sccache is not always a drop-in replacement for ccache in practice
 ENABLE_SCCACHE := 0
@@ -223,7 +223,9 @@ LTOFLAGS := $(GCC_LTO)
 ifeq ($(CONFIG),clang)
 CXX = clang++
 CXXFLAGS += -std=$(CXXSTD) $(OPT_LEVEL)
+ifeq ($(ENABLE_LTO),1)
 LINKFLAGS += -fuse-ld=lld
+endif
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H $(ABC_ARCHFLAGS)"
 LTOFLAGS := $(CLANG_LTO)
 
diff --git a/README.md b/README.md
index 59637b9bbb1..7437bb2832b 100644
--- a/README.md
+++ b/README.md
@@ -116,6 +116,17 @@ unless `CXX` is assigned in the call to make, e.g.
 
   $ make CXX=$CXX
 
+The Makefile has many variables influencing the build process. These can be
+adjusted by modifying the Makefile.conf file which is created at the
+`make config-...` step (see above), or they can be set by passing an option
+to the make command directly.
+
+For example, if you have clang, and (a compatible version of) `ld.lld`
+available in PATH, it's recommended to speed up incremental builds with
+lld by enabling LTO:
+
+ $ make ENABLE_LTO=1
+
 For other compilers and build configurations it might be
 necessary to make some changes to the config section of the
 Makefile.

From d2b57886745c6d838f0ebbfa38f8f6b47fa31d6e Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Tue, 6 Aug 2024 00:18:14 +0000
Subject: [PATCH 243/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index bc9633db5e7..2aa080acab0 100644
--- a/Makefile
+++ b/Makefile
@@ -153,7 +153,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.43+86
+YOSYS_VER := 0.43+89
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 80ba43d26264738c93900129dc0aab7fab36c53f Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 6 Aug 2024 09:42:28 +0200
Subject: [PATCH 244/499] Release version 0.44

---
 CHANGELOG           | 15 ++++++++++++++-
 Makefile            |  4 ++--
 docs/source/conf.py |  2 +-
 3 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index 160f480e7b0..7f2f14cf200 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,8 +2,21 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.43 .. Yosys 0.44-dev
+Yosys 0.43 .. Yosys 0.44
 --------------------------
+ * Various
+    - Added ENABLE_LTO compile option to enable link time
+      optimizations.
+    - Build support for Haiku OS.
+
+ * New commands and options
+    - Added "keep_hierarchy" pass to add attribute with 
+      same name to modules based on cost.
+    - Added options "-noopt","-bloat" and "-check_cost" to
+      "test_cell" pass. 
+
+ * New back-ends
+    - Added initial PolarFire support. ( synth_microchip )
 
 Yosys 0.42 .. Yosys 0.43
 --------------------------
diff --git a/Makefile b/Makefile
index 617a79c9832..ac0e0507ce4 100644
--- a/Makefile
+++ b/Makefile
@@ -153,7 +153,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.43+89
+YOSYS_VER := 0.44
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -169,7 +169,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline ead4718.. | wc -l`/;" Makefile
+#	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline ead4718.. | wc -l`/;" Makefile
 
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
 
diff --git a/docs/source/conf.py b/docs/source/conf.py
index 1dd53e95411..2fdd43a31a0 100644
--- a/docs/source/conf.py
+++ b/docs/source/conf.py
@@ -5,7 +5,7 @@
 project = 'YosysHQ Yosys'
 author = 'YosysHQ GmbH'
 copyright ='2024 YosysHQ GmbH'
-yosys_ver = "0.43"
+yosys_ver = "0.44"
 
 # select HTML theme
 html_theme = 'furo'

From d08bf671b21f50e8def44955feed09407541b9bd Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 6 Aug 2024 09:48:35 +0200
Subject: [PATCH 245/499] Next dev cycle

---
 CHANGELOG | 3 +++
 Makefile  | 4 ++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index 7f2f14cf200..3d22bfe6008 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 List of major changes and improvements between releases
 =======================================================
 
+Yosys 0.44 .. Yosys 0.45-dev
+--------------------------
+
 Yosys 0.43 .. Yosys 0.44
 --------------------------
  * Various
diff --git a/Makefile b/Makefile
index ac0e0507ce4..9fe5e01185c 100644
--- a/Makefile
+++ b/Makefile
@@ -153,7 +153,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.44
+YOSYS_VER := 0.44+0
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -169,7 +169,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-#	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline ead4718.. | wc -l`/;" Makefile
+	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 80ba43d.. | wc -l`/;" Makefile
 
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
 

From 669f8b18f07ce9b3370eb017ed7f6189704ddad1 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Wed, 7 Aug 2024 00:18:20 +0000
Subject: [PATCH 246/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 9fe5e01185c..bfd65088ebb 100644
--- a/Makefile
+++ b/Makefile
@@ -153,7 +153,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.44+0
+YOSYS_VER := 0.44+1
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 4c3203866f1798c438769aef10609b705ac0b458 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Wed, 7 Aug 2024 13:02:00 +0200
Subject: [PATCH 247/499] exec: Add missing newline

---
 passes/cmds/exec.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/cmds/exec.cc b/passes/cmds/exec.cc
index e5fa4fb41c4..e9cc34b30c0 100644
--- a/passes/cmds/exec.cc
+++ b/passes/cmds/exec.cc
@@ -141,7 +141,7 @@ struct ExecPass : public Pass {
 					}
 
 				} else
-					log_cmd_error("Unknown option \"%s\" or \"--\" doesn\'t precede command.", args[argidx].c_str());
+					log_cmd_error("Unknown option \"%s\" or \"--\" doesn\'t precede command.\n", args[argidx].c_str());
 			}
 		}
 

From ebffe37e4c98bf3eb7ba96a0c096e33e88c5ded6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Wed, 7 Aug 2024 13:03:27 +0200
Subject: [PATCH 248/499] Bump ABC

---
 abc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/abc b/abc
index 28d955ca97a..bf64a922536 160000
--- a/abc
+++ b/abc
@@ -1 +1 @@
-Subproject commit 28d955ca97a1c4be3aed4062aec0241a734fac5d
+Subproject commit bf64a922536d6020f8a521c664826848bb0ecb54

From 4b5beb635f09e0aef115142fe32487fa5fcce643 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Wed, 7 Aug 2024 17:31:34 +0200
Subject: [PATCH 249/499] Pull ABC fix

---
 abc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/abc b/abc
index bf64a922536..1776063db49 160000
--- a/abc
+++ b/abc
@@ -1 +1 @@
-Subproject commit bf64a922536d6020f8a521c664826848bb0ecb54
+Subproject commit 1776063db491b92812f17e7cccf59e0b427f05e0

From 77b2ae2e3906c2aa5a14fbc4e2239ac3ddd08bfc Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Thu, 8 Aug 2024 00:18:08 +0000
Subject: [PATCH 250/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index bfd65088ebb..b2c6db841ee 100644
--- a/Makefile
+++ b/Makefile
@@ -153,7 +153,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.44+1
+YOSYS_VER := 0.44+4
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From bcb995b506a32ec75fbb7f8a1aa571be59c5c484 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Thu, 8 Aug 2024 17:33:54 +0200
Subject: [PATCH 251/499] Sync with yosys-experimental branch

---
 abc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/abc b/abc
index 1776063db49..2188bc71228 160000
--- a/abc
+++ b/abc
@@ -1 +1 @@
-Subproject commit 1776063db491b92812f17e7cccf59e0b427f05e0
+Subproject commit 2188bc71228b0788569d83ad2b7e7b91ca5dcc09

From 4b9f4527352cd433db198c72d4f1efc52f52c0a1 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Tue, 13 Aug 2024 00:19:11 +0000
Subject: [PATCH 252/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index b2c6db841ee..343fa50ef15 100644
--- a/Makefile
+++ b/Makefile
@@ -153,7 +153,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.44+4
+YOSYS_VER := 0.44+9
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 78382eaa6f95ad52a9d4f2a92755c1d2f3f687bc Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Tue, 13 Aug 2024 18:08:21 +0200
Subject: [PATCH 253/499] libparse: Adjust whitespace

---
 passes/techmap/libparse.h | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/passes/techmap/libparse.h b/passes/techmap/libparse.h
index 77e305f0b87..3dcc0535c5f 100644
--- a/passes/techmap/libparse.h
+++ b/passes/techmap/libparse.h
@@ -46,19 +46,18 @@ namespace Yosys
 		LibertyAst *ast;
 		LibertyParser(std::istream &f) : f(f), line(1), ast(parse()) {}
 		~LibertyParser() { if (ast) delete ast; }
-        
-        /* lexer return values:
-           'v': identifier, string, array range [...] -> str holds the token string
-           'n': newline
-           anything else is a single character.
-        */
+		
+		/* lexer return values:
+		   'v': identifier, string, array range [...] -> str holds the token string
+		   'n': newline
+		   anything else is a single character.
+		*/
 		int lexer(std::string &str);
 		
-        LibertyAst *parse();
+		LibertyAst *parse();
 		void error();
-        void error(const std::string &str);
+		void error(const std::string &str);
 	};
 }
 
 #endif
-

From c35f5e379c2542a8df99aca1711cacbe4121dbee Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Tue, 13 Aug 2024 18:36:31 +0200
Subject: [PATCH 254/499] Extend liberty tests

---
 tests/liberty/.gitignore                      |   2 +
 tests/liberty/XNOR2X1.lib.filtered.ok         |  15 ++
 tests/liberty/XNOR2X1.lib.verilogsim.ok       |   6 +
 tests/liberty/busdef.lib.filtered.ok          |   8 +
 tests/liberty/busdef.lib.verilogsim.ok        |   3 +
 tests/liberty/issue3498_bad.lib.filtered.ok   |   4 +
 tests/liberty/issue3498_bad.lib.verilogsim.ok |   2 +
 tests/liberty/normal.lib.filtered.ok          | 211 ++++++++++++++++++
 tests/liberty/normal.lib.verilogsim.ok        | 117 ++++++++++
 tests/liberty/normal.verilogsim.ok            | 117 ++++++++++
 tests/liberty/processdefs.lib.filtered.ok     |   2 +
 tests/liberty/processdefs.lib.verilogsim.ok   |   0
 tests/liberty/run-test.sh                     |  11 +-
 tests/liberty/semicolextra.lib.filtered.ok    |  20 ++
 tests/liberty/semicolextra.lib.verilogsim.ok  |  11 +
 tests/liberty/semicolmissing.lib.filtered.ok  |  22 ++
 .../liberty/semicolmissing.lib.verilogsim.ok  |   9 +
 17 files changed, 556 insertions(+), 4 deletions(-)
 create mode 100644 tests/liberty/XNOR2X1.lib.filtered.ok
 create mode 100644 tests/liberty/XNOR2X1.lib.verilogsim.ok
 create mode 100644 tests/liberty/busdef.lib.filtered.ok
 create mode 100644 tests/liberty/busdef.lib.verilogsim.ok
 create mode 100644 tests/liberty/issue3498_bad.lib.filtered.ok
 create mode 100644 tests/liberty/issue3498_bad.lib.verilogsim.ok
 create mode 100644 tests/liberty/normal.lib.filtered.ok
 create mode 100644 tests/liberty/normal.lib.verilogsim.ok
 create mode 100644 tests/liberty/normal.verilogsim.ok
 create mode 100644 tests/liberty/processdefs.lib.filtered.ok
 create mode 100644 tests/liberty/processdefs.lib.verilogsim.ok
 create mode 100644 tests/liberty/semicolextra.lib.filtered.ok
 create mode 100644 tests/liberty/semicolextra.lib.verilogsim.ok
 create mode 100644 tests/liberty/semicolmissing.lib.filtered.ok
 create mode 100644 tests/liberty/semicolmissing.lib.verilogsim.ok

diff --git a/tests/liberty/.gitignore b/tests/liberty/.gitignore
index e6ec49c4a16..bf5ba57dce0 100644
--- a/tests/liberty/.gitignore
+++ b/tests/liberty/.gitignore
@@ -1,2 +1,4 @@
 *.log
 test.ys
+*.filtered
+*.verilogsim
diff --git a/tests/liberty/XNOR2X1.lib.filtered.ok b/tests/liberty/XNOR2X1.lib.filtered.ok
new file mode 100644
index 00000000000..14e9b625d8d
--- /dev/null
+++ b/tests/liberty/XNOR2X1.lib.filtered.ok
@@ -0,0 +1,15 @@
+library(ls05_stdcells) {
+  cell(XNOR2X1) {
+    area : 206080.0 ;
+    pin(B) {
+      direction : input ;
+    }
+    pin(A) {
+      direction : input ;
+    }
+    pin(Y) {
+      direction : output ;
+      function : !(B&!A|!B&A) ;
+    }
+  }
+}
diff --git a/tests/liberty/XNOR2X1.lib.verilogsim.ok b/tests/liberty/XNOR2X1.lib.verilogsim.ok
new file mode 100644
index 00000000000..62c9f7ffa9f
--- /dev/null
+++ b/tests/liberty/XNOR2X1.lib.verilogsim.ok
@@ -0,0 +1,6 @@
+module XNOR2X1 (B, A, Y);
+  input B;
+  input A;
+  output Y;
+  assign Y = !(B&!A|!B&A); // !(B&!A|!B&A)
+endmodule
diff --git a/tests/liberty/busdef.lib.filtered.ok b/tests/liberty/busdef.lib.filtered.ok
new file mode 100644
index 00000000000..55f5b08a3bf
--- /dev/null
+++ b/tests/liberty/busdef.lib.filtered.ok
@@ -0,0 +1,8 @@
+library(supergate) {
+  cell(SRAM) {
+    area : 1 ;
+    pin(CE1) {
+      direction : input ;
+    }
+  }
+}
diff --git a/tests/liberty/busdef.lib.verilogsim.ok b/tests/liberty/busdef.lib.verilogsim.ok
new file mode 100644
index 00000000000..5d7f47f3712
--- /dev/null
+++ b/tests/liberty/busdef.lib.verilogsim.ok
@@ -0,0 +1,3 @@
+module SRAM (CE1);
+  input CE1;
+endmodule
diff --git a/tests/liberty/issue3498_bad.lib.filtered.ok b/tests/liberty/issue3498_bad.lib.filtered.ok
new file mode 100644
index 00000000000..e121193df71
--- /dev/null
+++ b/tests/liberty/issue3498_bad.lib.filtered.ok
@@ -0,0 +1,4 @@
+library(fake) {
+  cell(bugbad) {
+  }
+}
diff --git a/tests/liberty/issue3498_bad.lib.verilogsim.ok b/tests/liberty/issue3498_bad.lib.verilogsim.ok
new file mode 100644
index 00000000000..2ce41ea6cd2
--- /dev/null
+++ b/tests/liberty/issue3498_bad.lib.verilogsim.ok
@@ -0,0 +1,2 @@
+module bugbad ();
+endmodule
diff --git a/tests/liberty/normal.lib.filtered.ok b/tests/liberty/normal.lib.filtered.ok
new file mode 100644
index 00000000000..757f09cabd5
--- /dev/null
+++ b/tests/liberty/normal.lib.filtered.ok
@@ -0,0 +1,211 @@
+library(supergate) {
+  cell(inv) {
+    area : 1 ;
+    pin(A) {
+      direction : input ;
+    }
+    pin(Y) {
+      direction : output ;
+      function : A' ;
+    }
+  }
+  cell(tri_inv) {
+    area : 4 ;
+    pin(A) {
+      direction : input ;
+    }
+    pin(S) {
+      direction : input ;
+    }
+    pin(Z) {
+      direction : output ;
+      function : A' ;
+    }
+  }
+  cell(buffer) {
+    area : 5 ;
+    pin(A) {
+      direction : input ;
+    }
+    pin(Y) {
+      direction : output ;
+      function : A ;
+    }
+  }
+  cell(nand2) {
+    area : 3 ;
+    pin(A) {
+      direction : input ;
+    }
+    pin(B) {
+      direction : input ;
+    }
+    pin(Y) {
+      direction : output ;
+      function : (A * B)' ;
+    }
+  }
+  cell(nor2) {
+    area : 3 ;
+    pin(A) {
+      direction : input ;
+    }
+    pin(B) {
+      direction : input ;
+    }
+    pin(Y) {
+      direction : output ;
+      function : (A + B)' ;
+    }
+  }
+  cell(xor2) {
+    area : 6 ;
+    pin(A) {
+      direction : input ;
+    }
+    pin(B) {
+      direction : input ;
+    }
+    pin(Y) {
+      direction : output ;
+      function : (A *B') + (A' * B) ;
+    }
+  }
+  cell(imux2) {
+    area : 5 ;
+    pin(A) {
+      direction : input ;
+    }
+    pin(B) {
+      direction : input ;
+    }
+    pin(S) {
+      direction : input ;
+    }
+    pin(Y) {
+      direction : output ;
+      function : ( (A * S) + (B * S') )' ;
+    }
+  }
+  cell(dff) {
+    area : 6 ;
+    ff(IQ, IQN) {
+      next_state : D ;
+      clocked_on : CLK ;
+      clear : RESET ;
+      preset : PRESET ;
+      clear_preset_var1 : L ;
+      clear_preset_var2 : L ;
+    }
+    pin(D) {
+      direction : input ;
+    }
+    pin(CLK) {
+      direction : input ;
+    }
+    pin(RESET) {
+      direction : input ;
+    }
+    pin(PRESET) {
+      direction : input ;
+    }
+    pin(Q) {
+      direction : output ;
+      function : IQ ;
+    }
+    pin(QN) {
+      direction : output ;
+      function : IQN ;
+    }
+  }
+  cell(latch) {
+    area : 5 ;
+    latch(IQ, IQN) {
+      enable : G ;
+      data_in : D ;
+    }
+    pin(D) {
+      direction : input ;
+    }
+    pin(G) {
+      direction : input ;
+    }
+    pin(Q) {
+      direction : output ;
+      function : IQ ;
+    }
+    pin(QN) {
+      direction : output ;
+      function : IQN ;
+    }
+  }
+  cell(aoi211) {
+    area : 3 ;
+    pin(A) {
+      direction : input ;
+    }
+    pin(B) {
+      direction : input ;
+    }
+    pin(C) {
+      direction : input ;
+    }
+    pin(Y) {
+      direction : output ;
+      function : ((A * B) + C)' ;
+    }
+  }
+  cell(oai211) {
+    area : 3 ;
+    pin(A) {
+      direction : input ;
+    }
+    pin(B) {
+      direction : input ;
+    }
+    pin(C) {
+      direction : input ;
+    }
+    pin(Y) {
+      direction : output ;
+      function : ((A + B) * C)' ;
+    }
+  }
+  cell(halfadder) {
+    area : 5 ;
+    pin(A) {
+      direction : input ;
+    }
+    pin(B) {
+      direction : input ;
+    }
+    pin(C) {
+      direction : output ;
+      function : (A * B) ;
+    }
+    pin(Y) {
+      direction : output ;
+      function : (A *B') + (A' * B) ;
+    }
+  }
+  cell(fulladder) {
+    area : 8 ;
+    pin(A) {
+      direction : input ;
+    }
+    pin(B) {
+      direction : input ;
+    }
+    pin(CI) {
+      direction : input ;
+    }
+    pin(CO) {
+      direction : output ;
+      function : (((A * B)+(B * CI))+(CI * A)) ;
+    }
+    pin(Y) {
+      direction : output ;
+      function : ((A^B)^CI) ;
+    }
+  }
+}
diff --git a/tests/liberty/normal.lib.verilogsim.ok b/tests/liberty/normal.lib.verilogsim.ok
new file mode 100644
index 00000000000..30f164a3115
--- /dev/null
+++ b/tests/liberty/normal.lib.verilogsim.ok
@@ -0,0 +1,117 @@
+module inv (A, Y);
+  input A;
+  output Y;
+  assign Y = ~A; // A'
+endmodule
+module tri_inv (A, S, Z);
+  input A;
+  input S;
+  output Z;
+  assign Z = ~A; // A'
+endmodule
+module buffer (A, Y);
+  input A;
+  output Y;
+  assign Y = A; // A
+endmodule
+module nand2 (A, B, Y);
+  input A;
+  input B;
+  output Y;
+  assign Y = ~(A&B); // (A * B)'
+endmodule
+module nor2 (A, B, Y);
+  input A;
+  input B;
+  output Y;
+  assign Y = ~(A|B); // (A + B)'
+endmodule
+module xor2 (A, B, Y);
+  input A;
+  input B;
+  output Y;
+  assign Y = (A&~B)|(~A&B); // (A *B') + (A' * B)
+endmodule
+module imux2 (A, B, S, Y);
+  input A;
+  input B;
+  input S;
+  output Y;
+  assign Y = ~(&(A&S)|(B&~S)&); // ( (A * S) + (B * S') )'
+endmodule
+module dff (D, CLK, RESET, PRESET, Q, QN);
+  reg IQ, IQN;
+  input D;
+  input CLK;
+  input RESET;
+  input PRESET;
+  output Q;
+  assign Q = IQ; // IQ
+  output QN;
+  assign QN = IQN; // IQN
+  always @(posedge CLK, posedge RESET, posedge PRESET) begin
+    if ((RESET) && (PRESET)) begin
+      IQ <= 0;
+      IQN <= 0;
+    end
+    else if (RESET) begin
+      IQ <= 0;
+      IQN <= 1;
+    end
+    else if (PRESET) begin
+      IQ <= 1;
+      IQN <= 0;
+    end
+    else begin
+      // D
+      IQ <= D;
+      IQN <= ~(D);
+    end
+  end
+endmodule
+module latch (D, G, Q, QN);
+  reg IQ, IQN;
+  input D;
+  input G;
+  output Q;
+  assign Q = IQ; // IQ
+  output QN;
+  assign QN = IQN; // IQN
+  always @* begin
+    if (G) begin
+      IQ <= D;
+      IQN <= ~(D);
+    end
+  end
+endmodule
+module aoi211 (A, B, C, Y);
+  input A;
+  input B;
+  input C;
+  output Y;
+  assign Y = ~((A&B)|C); // ((A * B) + C)'
+endmodule
+module oai211 (A, B, C, Y);
+  input A;
+  input B;
+  input C;
+  output Y;
+  assign Y = ~((A|B)&C); // ((A + B) * C)'
+endmodule
+module halfadder (A, B, C, Y);
+  input A;
+  input B;
+  output C;
+  assign C = (A&B); // (A * B)
+  output Y;
+  assign Y = (A&~B)|(~A&B); // (A *B') + (A' * B)
+endmodule
+module fulladder (A, B, CI, CO, Y);
+  input A;
+  input B;
+  input CI;
+  output CO;
+  assign CO = (((A&B)|(B&CI))|(CI&A)); // (((A * B)+(B * CI))+(CI * A))
+  output Y;
+  assign Y = ((A^B)^CI); // ((A^B)^CI)
+endmodule
diff --git a/tests/liberty/normal.verilogsim.ok b/tests/liberty/normal.verilogsim.ok
new file mode 100644
index 00000000000..30f164a3115
--- /dev/null
+++ b/tests/liberty/normal.verilogsim.ok
@@ -0,0 +1,117 @@
+module inv (A, Y);
+  input A;
+  output Y;
+  assign Y = ~A; // A'
+endmodule
+module tri_inv (A, S, Z);
+  input A;
+  input S;
+  output Z;
+  assign Z = ~A; // A'
+endmodule
+module buffer (A, Y);
+  input A;
+  output Y;
+  assign Y = A; // A
+endmodule
+module nand2 (A, B, Y);
+  input A;
+  input B;
+  output Y;
+  assign Y = ~(A&B); // (A * B)'
+endmodule
+module nor2 (A, B, Y);
+  input A;
+  input B;
+  output Y;
+  assign Y = ~(A|B); // (A + B)'
+endmodule
+module xor2 (A, B, Y);
+  input A;
+  input B;
+  output Y;
+  assign Y = (A&~B)|(~A&B); // (A *B') + (A' * B)
+endmodule
+module imux2 (A, B, S, Y);
+  input A;
+  input B;
+  input S;
+  output Y;
+  assign Y = ~(&(A&S)|(B&~S)&); // ( (A * S) + (B * S') )'
+endmodule
+module dff (D, CLK, RESET, PRESET, Q, QN);
+  reg IQ, IQN;
+  input D;
+  input CLK;
+  input RESET;
+  input PRESET;
+  output Q;
+  assign Q = IQ; // IQ
+  output QN;
+  assign QN = IQN; // IQN
+  always @(posedge CLK, posedge RESET, posedge PRESET) begin
+    if ((RESET) && (PRESET)) begin
+      IQ <= 0;
+      IQN <= 0;
+    end
+    else if (RESET) begin
+      IQ <= 0;
+      IQN <= 1;
+    end
+    else if (PRESET) begin
+      IQ <= 1;
+      IQN <= 0;
+    end
+    else begin
+      // D
+      IQ <= D;
+      IQN <= ~(D);
+    end
+  end
+endmodule
+module latch (D, G, Q, QN);
+  reg IQ, IQN;
+  input D;
+  input G;
+  output Q;
+  assign Q = IQ; // IQ
+  output QN;
+  assign QN = IQN; // IQN
+  always @* begin
+    if (G) begin
+      IQ <= D;
+      IQN <= ~(D);
+    end
+  end
+endmodule
+module aoi211 (A, B, C, Y);
+  input A;
+  input B;
+  input C;
+  output Y;
+  assign Y = ~((A&B)|C); // ((A * B) + C)'
+endmodule
+module oai211 (A, B, C, Y);
+  input A;
+  input B;
+  input C;
+  output Y;
+  assign Y = ~((A|B)&C); // ((A + B) * C)'
+endmodule
+module halfadder (A, B, C, Y);
+  input A;
+  input B;
+  output C;
+  assign C = (A&B); // (A * B)
+  output Y;
+  assign Y = (A&~B)|(~A&B); // (A *B') + (A' * B)
+endmodule
+module fulladder (A, B, CI, CO, Y);
+  input A;
+  input B;
+  input CI;
+  output CO;
+  assign CO = (((A&B)|(B&CI))|(CI&A)); // (((A * B)+(B * CI))+(CI * A))
+  output Y;
+  assign Y = ((A^B)^CI); // ((A^B)^CI)
+endmodule
diff --git a/tests/liberty/processdefs.lib.filtered.ok b/tests/liberty/processdefs.lib.filtered.ok
new file mode 100644
index 00000000000..d50f0e17bad
--- /dev/null
+++ b/tests/liberty/processdefs.lib.filtered.ok
@@ -0,0 +1,2 @@
+library(processdefs) {
+}
diff --git a/tests/liberty/processdefs.lib.verilogsim.ok b/tests/liberty/processdefs.lib.verilogsim.ok
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/tests/liberty/run-test.sh b/tests/liberty/run-test.sh
index 19ce0667d51..07d2cce1cd5 100755
--- a/tests/liberty/run-test.sh
+++ b/tests/liberty/run-test.sh
@@ -2,9 +2,12 @@
 set -e
 
 for x in *.lib; do
-	echo "Running $x.."
-    echo "read_verilog small.v" > test.ys
-    echo "synth -top small" >> test.ys
-    echo "dfflibmap -info -liberty ${x}" >> test.ys
+	echo "Testing on $x.."
+	echo "read_verilog small.v" > test.ys
+	echo "synth -top small" >> test.ys
+	echo "dfflibmap -info -liberty ${x}" >> test.ys
 	../../yosys -ql ${x%.lib}.log -s test.ys
+	../../yosys-filterlib - $x 2>/dev/null > $x.filtered
+	../../yosys-filterlib -verilogsim $x > $x.verilogsim
+	diff $x.filtered $x.filtered.ok && diff $x.verilogsim $x.verilogsim.ok
 done
diff --git a/tests/liberty/semicolextra.lib.filtered.ok b/tests/liberty/semicolextra.lib.filtered.ok
new file mode 100644
index 00000000000..791b4508454
--- /dev/null
+++ b/tests/liberty/semicolextra.lib.filtered.ok
@@ -0,0 +1,20 @@
+library(supergate) {
+  cell(DFF) {
+    cell_footprint : dff ;
+    area : 50 ;
+    pin(D) {
+      direction : input ;
+    }
+    pin(CK) {
+      direction : input ;
+      clock : true ;
+    }
+    ff(IQ, IQN) {
+      clocked_on : CK ;
+      next_state : D ;
+    }
+    pin(Q) {
+      direction : output ;
+    }
+  }
+}
diff --git a/tests/liberty/semicolextra.lib.verilogsim.ok b/tests/liberty/semicolextra.lib.verilogsim.ok
new file mode 100644
index 00000000000..c9eebd6ed5a
--- /dev/null
+++ b/tests/liberty/semicolextra.lib.verilogsim.ok
@@ -0,0 +1,11 @@
+module DFF (D, CK, Q);
+  reg IQ, IQN;
+  input D;
+  input CK;
+  output Q;
+  always @(posedge CK) begin
+      // D
+      IQ <= D;
+      IQN <= ~(D);
+  end
+endmodule
diff --git a/tests/liberty/semicolmissing.lib.filtered.ok b/tests/liberty/semicolmissing.lib.filtered.ok
new file mode 100644
index 00000000000..29022cf80c4
--- /dev/null
+++ b/tests/liberty/semicolmissing.lib.filtered.ok
@@ -0,0 +1,22 @@
+library(supergate) {
+  cell(fulladder) {
+    area : 8 ;
+    pin(A) {
+      direction : input ;
+    }
+    pin(B) {
+      direction : input ;
+    }
+    pin(CI) {
+      direction : input ;
+    }
+    pin(CO) {
+      direction : output ;
+      function : (((A * B)+(B * CI))+(CI * A)) ;
+    }
+    pin(Y) {
+      direction : output ;
+      function : ((A^B)^CI) ;
+    }
+  }
+}
diff --git a/tests/liberty/semicolmissing.lib.verilogsim.ok b/tests/liberty/semicolmissing.lib.verilogsim.ok
new file mode 100644
index 00000000000..131ce2fdfe0
--- /dev/null
+++ b/tests/liberty/semicolmissing.lib.verilogsim.ok
@@ -0,0 +1,9 @@
+module fulladder (A, B, CI, CO, Y);
+  input A;
+  input B;
+  input CI;
+  output CO;
+  assign CO = (((A&B)|(B&CI))|(CI&A)); // (((A * B)+(B * CI))+(CI * A))
+  output Y;
+  assign Y = ((A^B)^CI); // ((A^B)^CI)
+endmodule

From 3057c13a665e89852253b3e9aec4897bf7608120 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Tue, 13 Aug 2024 18:43:31 +0200
Subject: [PATCH 255/499] Improve libparse encapsulation

---
 frontends/liberty/liberty.cc | 20 +++++------
 passes/cmds/stat.cc          |  2 +-
 passes/techmap/dfflibmap.cc  | 30 ++++++++--------
 passes/techmap/libparse.cc   | 70 ++++++++++++++++++------------------
 passes/techmap/libparse.h    | 22 +++++++-----
 5 files changed, 73 insertions(+), 71 deletions(-)

diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index 86bb4c7dcd4..c23dbfa531e 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -226,7 +226,7 @@ static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func
 	return cell->getPort(ID::Y);
 }
 
-static void create_ff(RTLIL::Module *module, LibertyAst *node)
+static void create_ff(RTLIL::Module *module, const LibertyAst *node)
 {
 	RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0))));
 	RTLIL::SigSpec iqn_sig(module->addWire(RTLIL::escape_id(node->args.at(1))));
@@ -303,7 +303,7 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
 	log_assert(!cell->type.empty());
 }
 
-static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_ignore_miss_data_latch)
+static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool flag_ignore_miss_data_latch)
 {
 	RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0))));
 	RTLIL::SigSpec iqn_sig(module->addWire(RTLIL::escape_id(node->args.at(1))));
@@ -422,7 +422,7 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
 	return true;
 }
 
-void parse_type_map(std::map<std::string, std::tuple<int, int, bool>> &type_map, LibertyAst *ast)
+void parse_type_map(std::map<std::string, std::tuple<int, int, bool>> &type_map, const LibertyAst *ast)
 {
 	for (auto type_node : ast->children)
 	{
@@ -604,7 +604,7 @@ struct LibertyFrontend : public Frontend {
 			for (auto node : cell->children)
 			{
 				if (node->id == "pin" && node->args.size() == 1) {
-					LibertyAst *dir = node->find("direction");
+					const LibertyAst *dir = node->find("direction");
 					if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "inout" && dir->value != "internal"))
 					{
 						if (!flag_ignore_miss_dir)
@@ -625,10 +625,10 @@ struct LibertyFrontend : public Frontend {
 					if (!flag_lib)
 						log_error("Error in cell %s: bus interfaces are only supported in -lib mode.\n", log_id(cell_name));
 
-					LibertyAst *dir = node->find("direction");
+					const LibertyAst *dir = node->find("direction");
 
 					if (dir == nullptr) {
-						LibertyAst *pin = node->find("pin");
+						const LibertyAst *pin = node->find("pin");
 						if (pin != nullptr)
 							dir = pin->find("direction");
 					}
@@ -639,7 +639,7 @@ struct LibertyFrontend : public Frontend {
 					if (dir->value == "internal")
 						continue;
 
-					LibertyAst *bus_type_node = node->find("bus_type");
+					const LibertyAst *bus_type_node = node->find("bus_type");
 
 					if (!bus_type_node || !type_map.count(bus_type_node->value))
 						log_error("Unknown or unsupported type for bus interface %s on cell %s.\n",
@@ -681,7 +681,7 @@ struct LibertyFrontend : public Frontend {
 			{
 				if (node->id == "pin" && node->args.size() == 1)
 				{
-					LibertyAst *dir = node->find("direction");
+					const LibertyAst *dir = node->find("direction");
 
 					if (flag_lib && dir->value == "internal")
 						continue;
@@ -704,7 +704,7 @@ struct LibertyFrontend : public Frontend {
 					if (flag_lib)
 						continue;
 
-					LibertyAst *func = node->find("function");
+					const LibertyAst *func = node->find("function");
 					if (func == NULL)
 					{
 						if (dir->value != "inout") { // allow inout with missing function, can be used for power pins
@@ -719,7 +719,7 @@ struct LibertyFrontend : public Frontend {
 						}
 					} else {
 						RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str());
-						LibertyAst *three_state = node->find("three_state");
+						const LibertyAst *three_state = node->find("three_state");
 						if (three_state) {
 							out_sig = create_tristate(module, out_sig, three_state->value.c_str());
 						}
diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index 379ce209790..951a321e8a0 100644
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -361,7 +361,7 @@ void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string libert
 		if (cell->id != "cell" || cell->args.size() != 1)
 			continue;
 
-		LibertyAst *ar = cell->find("area");
+		const LibertyAst *ar = cell->find("area");
 		bool is_flip_flop = cell->find("ff") != nullptr;
 		if (ar != nullptr && !ar->value.empty())
 			cell_area["\\" + cell->args[0]] = {/*area=*/atof(ar->value.c_str()), is_flip_flop};
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 78bfe1586ff..43eef1ac04a 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -76,7 +76,7 @@ static void logmap_all()
 	logmap(ID($_DFFSR_PPP_));
 }
 
-static bool parse_pin(LibertyAst *cell, LibertyAst *attr, std::string &pin_name, bool &pin_pol)
+static bool parse_pin(const LibertyAst *cell, const LibertyAst *attr, std::string &pin_name, bool &pin_pol)
 {
 	if (cell == nullptr || attr == nullptr || attr->value.empty())
 		return false;
@@ -115,9 +115,9 @@ static bool parse_pin(LibertyAst *cell, LibertyAst *attr, std::string &pin_name,
 	return false;
 }
 
-static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval, std::vector<std::string> &dont_use_cells)
+static void find_cell(const LibertyAst *ast, IdString cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval, std::vector<std::string> &dont_use_cells)
 {
-	LibertyAst *best_cell = nullptr;
+	const LibertyAst *best_cell = nullptr;
 	std::map<std::string, char> best_cell_ports;
 	int best_cell_pins = 0;
 	bool best_cell_noninv = false;
@@ -131,7 +131,7 @@ static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has
 		if (cell->id != "cell" || cell->args.size() != 1)
 			continue;
 
-		LibertyAst *dn = cell->find("dont_use");
+		const LibertyAst *dn = cell->find("dont_use");
 		if (dn != nullptr && dn->value == "true")
 			continue;
 
@@ -147,7 +147,7 @@ static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has
 		if (dont_use)
 			continue;
 
-		LibertyAst *ff = cell->find("ff");
+		const LibertyAst *ff = cell->find("ff");
 		if (ff == nullptr)
 			continue;
 
@@ -174,7 +174,7 @@ static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has
 		this_cell_ports[cell_next_pin] = 'D';
 
 		double area = 0;
-		LibertyAst *ar = cell->find("area");
+		const LibertyAst *ar = cell->find("area");
 		if (ar != nullptr && !ar->value.empty())
 			area = atof(ar->value.c_str());
 
@@ -186,7 +186,7 @@ static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has
 			if (pin->id != "pin" || pin->args.size() != 1)
 				continue;
 
-			LibertyAst *dir = pin->find("direction");
+			const LibertyAst *dir = pin->find("direction");
 			if (dir == nullptr || dir->value == "internal")
 				continue;
 			num_pins++;
@@ -194,7 +194,7 @@ static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has
 			if (dir->value == "input" && this_cell_ports.count(pin->args[0]) == 0)
 				goto continue_cell_loop;
 
-			LibertyAst *func = pin->find("function");
+			const LibertyAst *func = pin->find("function");
 			if (dir->value == "output" && func != nullptr) {
 				std::string value = func->value;
 				for (size_t pos = value.find_first_of("\" \t"); pos != std::string::npos; pos = value.find_first_of("\" \t"))
@@ -239,9 +239,9 @@ static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has
 	}
 }
 
-static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool setpol, bool clrpol, std::vector<std::string> &dont_use_cells)
+static void find_cell_sr(const LibertyAst *ast, IdString cell_type, bool clkpol, bool setpol, bool clrpol, std::vector<std::string> &dont_use_cells)
 {
-	LibertyAst *best_cell = nullptr;
+	const LibertyAst *best_cell = nullptr;
 	std::map<std::string, char> best_cell_ports;
 	int best_cell_pins = 0;
 	bool best_cell_noninv = false;
@@ -255,7 +255,7 @@ static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool
 		if (cell->id != "cell" || cell->args.size() != 1)
 			continue;
 
-		LibertyAst *dn = cell->find("dont_use");
+		const LibertyAst *dn = cell->find("dont_use");
 		if (dn != nullptr && dn->value == "true")
 			continue;
 
@@ -271,7 +271,7 @@ static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool
 		if (dont_use)
 			continue;
 
-		LibertyAst *ff = cell->find("ff");
+		const LibertyAst *ff = cell->find("ff");
 		if (ff == nullptr)
 			continue;
 
@@ -294,7 +294,7 @@ static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool
 		this_cell_ports[cell_next_pin] = 'D';
 
 		double area = 0;
-		LibertyAst *ar = cell->find("area");
+		const LibertyAst *ar = cell->find("area");
 		if (ar != nullptr && !ar->value.empty())
 			area = atof(ar->value.c_str());
 
@@ -306,7 +306,7 @@ static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool
 			if (pin->id != "pin" || pin->args.size() != 1)
 				continue;
 
-			LibertyAst *dir = pin->find("direction");
+			const LibertyAst *dir = pin->find("direction");
 			if (dir == nullptr || dir->value == "internal")
 				continue;
 			num_pins++;
@@ -314,7 +314,7 @@ static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool
 			if (dir->value == "input" && this_cell_ports.count(pin->args[0]) == 0)
 				goto continue_cell_loop;
 
-			LibertyAst *func = pin->find("function");
+			const LibertyAst *func = pin->find("function");
 			if (dir->value == "output" && func != nullptr) {
 				std::string value = func->value;
 				for (size_t pos = value.find_first_of("\" \t"); pos != std::string::npos; pos = value.find_first_of("\" \t"))
diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc
index efe00c105e4..ebfb325fcd5 100644
--- a/passes/techmap/libparse.cc
+++ b/passes/techmap/libparse.cc
@@ -32,9 +32,6 @@
 
 using namespace Yosys;
 
-std::set<std::string> LibertyAst::blacklist;
-std::set<std::string> LibertyAst::whitelist;
-
 LibertyAst::~LibertyAst()
 {
 	for (auto child : children)
@@ -42,7 +39,7 @@ LibertyAst::~LibertyAst()
 	children.clear();
 }
 
-LibertyAst *LibertyAst::find(std::string name)
+const LibertyAst *LibertyAst::find(std::string name) const
 {
 	for (auto child : children)
 		if (child->id == name)
@@ -50,7 +47,7 @@ LibertyAst *LibertyAst::find(std::string name)
 	return NULL;
 }
 
-void LibertyAst::dump(FILE *f, std::string indent, std::string path, bool path_ok)
+void LibertyAst::dump(FILE *f, sieve &blacklist, sieve &whitelist, std::string indent, std::string path, bool path_ok) const
 {
 	if (whitelist.count(path + "/*") > 0)
 		path_ok = true;
@@ -77,7 +74,7 @@ void LibertyAst::dump(FILE *f, std::string indent, std::string path, bool path_o
 	if (!children.empty()) {
 		fprintf(f, " {\n");
 		for (size_t i = 0; i < children.size(); i++)
-			children[i]->dump(f, indent + "  ", path, path_ok);
+			children[i]->dump(f, blacklist, whitelist, indent + "  ", path, path_ok);
 		fprintf(f, "%s}\n", indent.c_str());
 	} else
 		fprintf(f, " ;\n");
@@ -406,9 +403,9 @@ void LibertyParser::error(const std::string &str)
 
 /**** END: http://svn.clairexen.net/tools/trunk/examples/check.h ****/
 
-LibertyAst *find_non_null(LibertyAst *node, const char *name)
+const LibertyAst *find_non_null(const LibertyAst *node, const char *name)
 {
-	LibertyAst *ret = node->find(name);
+	const LibertyAst *ret = node->find(name);
 	if (ret == NULL)
 		fprintf(stderr, "Error: expected to find `%s' node.\n", name);
 	return ret;
@@ -455,7 +452,7 @@ std::string func2vl(std::string str)
 	return str;
 }
 
-void event2vl(LibertyAst *ast, std::string &edge, std::string &expr)
+void event2vl(const LibertyAst *ast, std::string &edge, std::string &expr)
 {
 	edge.clear();
 	expr.clear();
@@ -489,7 +486,7 @@ void clear_preset_var(std::string var, std::string type)
 	}
 }
 
-void gen_verilogsim_cell(LibertyAst *ast)
+void gen_verilogsim_cell(const LibertyAst *ast)
 {
 	if (ast->find("statetable") != NULL)
 		return;
@@ -522,8 +519,8 @@ void gen_verilogsim_cell(LibertyAst *ast)
 		if (child->id != "pin")
 			continue;
 		CHECK_NV(child->args.size(), == 1);
-		LibertyAst *dir = find_non_null(child, "direction");
-		LibertyAst *func = child->find("function");
+		const LibertyAst *dir = find_non_null(child, "direction");
+		const LibertyAst *func = child->find("function");
 		printf("  %s %s;\n", dir->value.c_str(), child->args[0].c_str());
 		if (func != NULL)
 			printf("  assign %s = %s; // %s\n", child->args[0].c_str(), func2vl(func->value).c_str(), func->value.c_str());
@@ -649,7 +646,7 @@ void gen_verilogsim_cell(LibertyAst *ast)
 	printf("endmodule\n");
 }
 
-void gen_verilogsim(LibertyAst *ast)
+void gen_verilogsim(const LibertyAst *ast)
 {
 	CHECK_COND(ast->id == "library");
 
@@ -668,6 +665,7 @@ void usage()
 int main(int argc, char **argv)
 {
 	bool flag_verilogsim = false;
+	std::set<std::string> whitelist, blacklist;
 
 	if (argc > 3)
 		usage();
@@ -678,26 +676,26 @@ int main(int argc, char **argv)
 			flag_verilogsim = true;
 		if (!strcmp(argv[1], "-") || !strcmp(argv[1], "-verilogsim"))
 		{
-			LibertyAst::whitelist.insert("/library");
-			LibertyAst::whitelist.insert("/library/cell");
-			LibertyAst::whitelist.insert("/library/cell/area");
-			LibertyAst::whitelist.insert("/library/cell/cell_footprint");
-			LibertyAst::whitelist.insert("/library/cell/dont_touch");
-			LibertyAst::whitelist.insert("/library/cell/dont_use");
-			LibertyAst::whitelist.insert("/library/cell/ff");
-			LibertyAst::whitelist.insert("/library/cell/ff/*");
-			LibertyAst::whitelist.insert("/library/cell/latch");
-			LibertyAst::whitelist.insert("/library/cell/latch/*");
-			LibertyAst::whitelist.insert("/library/cell/pin");
-			LibertyAst::whitelist.insert("/library/cell/pin/clock");
-			LibertyAst::whitelist.insert("/library/cell/pin/direction");
-			LibertyAst::whitelist.insert("/library/cell/pin/driver_type");
-			LibertyAst::whitelist.insert("/library/cell/pin/function");
-			LibertyAst::whitelist.insert("/library/cell/pin_opposite");
-			LibertyAst::whitelist.insert("/library/cell/pin/state_function");
-			LibertyAst::whitelist.insert("/library/cell/pin/three_state");
-			LibertyAst::whitelist.insert("/library/cell/statetable");
-			LibertyAst::whitelist.insert("/library/cell/statetable/*");
+			whitelist.insert("/library");
+			whitelist.insert("/library/cell");
+			whitelist.insert("/library/cell/area");
+			whitelist.insert("/library/cell/cell_footprint");
+			whitelist.insert("/library/cell/dont_touch");
+			whitelist.insert("/library/cell/dont_use");
+			whitelist.insert("/library/cell/ff");
+			whitelist.insert("/library/cell/ff/*");
+			whitelist.insert("/library/cell/latch");
+			whitelist.insert("/library/cell/latch/*");
+			whitelist.insert("/library/cell/pin");
+			whitelist.insert("/library/cell/pin/clock");
+			whitelist.insert("/library/cell/pin/direction");
+			whitelist.insert("/library/cell/pin/driver_type");
+			whitelist.insert("/library/cell/pin/function");
+			whitelist.insert("/library/cell/pin_opposite");
+			whitelist.insert("/library/cell/pin/state_function");
+			whitelist.insert("/library/cell/pin/three_state");
+			whitelist.insert("/library/cell/statetable");
+			whitelist.insert("/library/cell/statetable/*");
 		}
 		else
 		{
@@ -723,10 +721,10 @@ int main(int argc, char **argv)
 					if (*p == ' ' || *p == '\t' || *p == '\r' || *p == '\n' || *p == '#') {
 						if (!id.empty()) {
 							if (mode == '-')
-								LibertyAst::blacklist.insert(id);
+								blacklist.insert(id);
 							else
 							if (mode == '+')
-								LibertyAst::whitelist.insert(id);
+								whitelist.insert(id);
 							else
 								goto syntax_error;
 						}
@@ -764,7 +762,7 @@ int main(int argc, char **argv)
 		if (flag_verilogsim)
 			gen_verilogsim(parser.ast);
 		else
-			parser.ast->dump(stdout);
+			parser.ast->dump(stdout, blacklist, whitelist);
 	}
 
 	if (argc == 3)
diff --git a/passes/techmap/libparse.h b/passes/techmap/libparse.h
index 3dcc0535c5f..ad38ae5f8e0 100644
--- a/passes/techmap/libparse.h
+++ b/passes/techmap/libparse.h
@@ -33,20 +33,18 @@ namespace Yosys
 		std::vector<std::string> args;
 		std::vector<LibertyAst*> children;
 		~LibertyAst();
-		LibertyAst *find(std::string name);
-		void dump(FILE *f, std::string indent = "", std::string path = "", bool path_ok = false);
-		static std::set<std::string> blacklist;
-		static std::set<std::string> whitelist;
+		const LibertyAst *find(std::string name) const;
+
+		typedef std::set<std::string> sieve;
+		void dump(FILE *f, sieve &blacklist, sieve &whitelist, std::string indent = "", std::string path = "", bool path_ok = false) const;
 	};
 
-	struct LibertyParser
+	class LibertyParser
 	{
+	private:
 		std::istream &f;
 		int line;
-		LibertyAst *ast;
-		LibertyParser(std::istream &f) : f(f), line(1), ast(parse()) {}
-		~LibertyParser() { if (ast) delete ast; }
-		
+
 		/* lexer return values:
 		   'v': identifier, string, array range [...] -> str holds the token string
 		   'n': newline
@@ -57,6 +55,12 @@ namespace Yosys
 		LibertyAst *parse();
 		void error();
 		void error(const std::string &str);
+
+	public:
+		const LibertyAst *ast;
+
+		LibertyParser(std::istream &f) : f(f), line(1), ast(parse()) {}
+		~LibertyParser() { if (ast) delete ast; }
 	};
 }
 

From 309d80885bc8171116ea4f76f184fa24573f9545 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Tue, 13 Aug 2024 18:44:40 +0200
Subject: [PATCH 256/499] read_liberty: Use available gate creation helpers

---
 frontends/liberty/liberty.cc | 47 +++++-------------------------------
 1 file changed, 6 insertions(+), 41 deletions(-)

diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index c23dbfa531e..83a6297fe56 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -53,47 +53,12 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
 	return module->wires_.at(id);
 }
 
-static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A)
-{
-	RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
-	cell->setPort(ID::A, A);
-	cell->setPort(ID::Y, module->addWire(NEW_ID));
-	return cell->getPort(ID::Y);
-}
-
-static RTLIL::SigSpec create_xor_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
-{
-	RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_XOR_));
-	cell->setPort(ID::A, A);
-	cell->setPort(ID::B, B);
-	cell->setPort(ID::Y, module->addWire(NEW_ID));
-	return cell->getPort(ID::Y);
-}
-
-static RTLIL::SigSpec create_and_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
-{
-	RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_AND_));
-	cell->setPort(ID::A, A);
-	cell->setPort(ID::B, B);
-	cell->setPort(ID::Y, module->addWire(NEW_ID));
-	return cell->getPort(ID::Y);
-}
-
-static RTLIL::SigSpec create_or_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
-{
-	RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_OR_));
-	cell->setPort(ID::A, A);
-	cell->setPort(ID::B, B);
-	cell->setPort(ID::Y, module->addWire(NEW_ID));
-	return cell->getPort(ID::Y);
-}
-
 static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack, token_t next_token)
 {
 	int top = int(stack.size())-1;
 
 	if (0 <= top-1 && stack[top].type == 0 && stack[top-1].type == '!') {
-		token_t t = token_t(0, create_inv_cell(module, stack[top].sig));
+		token_t t = token_t(0, module->NotGate(NEW_ID, stack[top].sig));
 		stack.pop_back();
 		stack.pop_back();
 		stack.push_back(t);
@@ -101,7 +66,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack
 	}
 
 	if (0 <= top-1 && stack[top].type == '\'' && stack[top-1].type == 0) {
-		token_t t = token_t(0, create_inv_cell(module, stack[top-1].sig));
+		token_t t = token_t(0, module->NotGate(NEW_ID, stack[top-1].sig));
 		stack.pop_back();
 		stack.pop_back();
 		stack.push_back(t);
@@ -116,7 +81,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack
 	}
 
 	if (0 <= top-2 && stack[top-2].type == 1 && stack[top-1].type == '^' && stack[top].type == 1) {
-		token_t t = token_t(1, create_xor_cell(module, stack[top-2].sig, stack[top].sig));
+		token_t t = token_t(1, module->XorGate(NEW_ID, stack[top-2].sig, stack[top].sig));
 		stack.pop_back();
 		stack.pop_back();
 		stack.pop_back();
@@ -132,7 +97,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack
 	}
 
 	if (0 <= top-1 && stack[top-1].type == 2 && stack[top].type == 2) {
-		token_t t = token_t(2, create_and_cell(module, stack[top-1].sig, stack[top].sig));
+		token_t t = token_t(2, module->AndGate(NEW_ID, stack[top-1].sig, stack[top].sig));
 		stack.pop_back();
 		stack.pop_back();
 		stack.push_back(t);
@@ -140,7 +105,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack
 	}
 
 	if (0 <= top-2 && stack[top-2].type == 2 && (stack[top-1].type == '*' || stack[top-1].type == '&') && stack[top].type == 2) {
-		token_t t = token_t(2, create_and_cell(module, stack[top-2].sig, stack[top].sig));
+		token_t t = token_t(2, module->AndGate(NEW_ID, stack[top-2].sig, stack[top].sig));
 		stack.pop_back();
 		stack.pop_back();
 		stack.pop_back();
@@ -156,7 +121,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack
 	}
 
 	if (0 <= top-2 && stack[top-2].type == 3 && (stack[top-1].type == '+' || stack[top-1].type == '|') && stack[top].type == 3) {
-		token_t t = token_t(3, create_or_cell(module, stack[top-2].sig, stack[top].sig));
+		token_t t = token_t(3, module->OrGate(NEW_ID, stack[top-2].sig, stack[top].sig));
 		stack.pop_back();
 		stack.pop_back();
 		stack.pop_back();

From ab5d6b06b4fab48c227269c3f2cf2a8de0bbbbf2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Tue, 13 Aug 2024 20:12:38 +0200
Subject: [PATCH 257/499] read_liberty: Fix omitted helper change

---
 frontends/liberty/liberty.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index 83a6297fe56..16fed54f203 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -186,7 +186,7 @@ static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func
 	RTLIL::Cell *cell = module->addCell(NEW_ID, ID($tribuf));
 	cell->setParam(ID::WIDTH, GetSize(func));
 	cell->setPort(ID::A, func);
-	cell->setPort(ID::EN, create_inv_cell(module, three_state));
+	cell->setPort(ID::EN, module->NotGate(NEW_ID, three_state));
 	cell->setPort(ID::Y, module->addWire(NEW_ID));
 	return cell->getPort(ID::Y);
 }

From d7091777704b725f9072b84651a3d5c6c79843b2 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 15 Aug 2024 09:34:23 +1200
Subject: [PATCH 258/499] test-compile: Downgrade to focal

---
 .github/workflows/test-compile.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml
index a892c91ceca..089e65ca757 100644
--- a/.github/workflows/test-compile.yml
+++ b/.github/workflows/test-compile.yml
@@ -40,8 +40,8 @@ jobs:
           - os: macos-13
             compiler: 'clang'
           # oldest clang not available on ubuntu-latest
-          - os: ubuntu-22.04
-            compiler: 'clang-11'
+          - os: ubuntu-20.04
+            compiler: 'clang-10'
       fail-fast: false
     steps:
       - name: Checkout Yosys

From 1eaf4e0790d0336e0c30bfd3341629c68c86d544 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Thu, 15 Aug 2024 00:17:57 +0000
Subject: [PATCH 259/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 343fa50ef15..a2803ed5934 100644
--- a/Makefile
+++ b/Makefile
@@ -153,7 +153,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.44+9
+YOSYS_VER := 0.44+16
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 3b48e9df61126f5f4b6514f9208aa7b2c170ba84 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Fri, 1 Mar 2024 10:43:34 +0100
Subject: [PATCH 260/499] Add initial NanoXplore pass

---
 techlibs/nanoxplore/Makefile.inc        |   6 +
 techlibs/nanoxplore/cells_map.v         |  34 ++++
 techlibs/nanoxplore/cells_sim.v         |  10 ++
 techlibs/nanoxplore/synth_nanoxplore.cc | 228 ++++++++++++++++++++++++
 4 files changed, 278 insertions(+)
 create mode 100644 techlibs/nanoxplore/Makefile.inc
 create mode 100644 techlibs/nanoxplore/cells_map.v
 create mode 100644 techlibs/nanoxplore/cells_sim.v
 create mode 100644 techlibs/nanoxplore/synth_nanoxplore.cc

diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc
new file mode 100644
index 00000000000..7e2923c4018
--- /dev/null
+++ b/techlibs/nanoxplore/Makefile.inc
@@ -0,0 +1,6 @@
+
+OBJS += techlibs/nanoxplore/synth_nanoxplore.o
+
+# Techmap
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v))
diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v
new file mode 100644
index 00000000000..4a83fafc208
--- /dev/null
+++ b/techlibs/nanoxplore/cells_map.v
@@ -0,0 +1,34 @@
+`default_nettype none
+
+module \$lut (A, Y);
+  parameter WIDTH = 0;
+  parameter LUT = 0;
+
+  (* force_downto *)
+  input [WIDTH-1:0] A;
+  output Y;
+
+  generate
+    if (WIDTH == 1) begin
+      localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}};
+      NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+        .I1(1'b0), .I2(1'b0), .I3(1'b0), .I4(A[0]));
+    end else
+    if (WIDTH == 2) begin
+      localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}};
+      NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+        .I1(1'b0), .I2(1'b0), .I3(A[0]), .I4(A[1]));
+    end else
+    if (WIDTH == 3) begin
+      localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}};
+      NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+        .I1(1'b0), .I2(A[0]), .I3(A[1]), .I4(A[2]));
+    end else
+    if (WIDTH == 4) begin
+      NX_LUT #(.lut_table(LUT)) _TECHMAP_REPLACE_ (.O(Y),
+        .I1(A[0]), .I2(A[1]), .I3(A[2]), .I4(A[3]));
+    end else begin
+      wire _TECHMAP_FAIL_ = 1;
+    end
+  endgenerate
+endmodule
diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v
new file mode 100644
index 00000000000..d665e0f89e3
--- /dev/null
+++ b/techlibs/nanoxplore/cells_sim.v
@@ -0,0 +1,10 @@
+module NX_LUT(input I1, I2, I3, I4, output O);
+
+parameter lut_table = 16'h0000;
+
+wire [7:0] s1 = I4 ? lut_table[15:8] : lut_table[7:0];
+wire [3:0] s2 = I3 ? s1[7:4] : s1[3:0];
+wire [1:0] s3 = I2 ? s2[3:2] : s2[1:0];
+assign O = I1 ? s3[1] : s3[0];
+
+endmodule
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
new file mode 100644
index 00000000000..3d8a34c0609
--- /dev/null
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -0,0 +1,228 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024 Hannah Ravensloft <lofty@yosyshq.com> 
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SynthNanoXplorePass : public ScriptPass
+{
+	SynthNanoXplorePass() : ScriptPass("synth_nanoxplore", "synthesis for NanoXplore FPGAs") { }
+
+	void on_register() override
+	{
+		RTLIL::constpad["synth_nanoxplore.abc9.W"] = "300";
+	}
+
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    synth_nanoxplore [options]\n");
+		log("\n");
+		log("This command runs synthesis for NanoXplore FPGAs.\n");
+		log("\n");
+		log("    -top <module>\n");
+		log("        use the specified module as top module\n");
+		log("\n");
+		log("    -json <file>\n");
+		log("        write the design to the specified JSON file. writing of an output file\n");
+		log("        is omitted if this parameter is not specified.\n");
+		log("\n");
+		log("    -run <from_label>:<to_label>\n");
+		log("        only run the commands between the labels (see below). an empty\n");
+		log("        from label is synonymous to 'begin', and empty to label is\n");
+		log("        synonymous to the end of the command list.\n");
+		log("\n");
+		log("    -noflatten\n");
+		log("        do not flatten design before synthesis\n");
+		log("\n");
+		log("    -abc9\n");
+		log("        use new ABC9 flow (EXPERIMENTAL)\n");
+		log("\n");
+		log("\n");
+		log("The following commands are executed by this synthesis command:\n");
+		help_script();
+		log("\n");
+	}
+
+	string top_opt, json_file;
+	bool flatten, abc9;
+
+	void clear_flags() override
+	{
+		top_opt = "-auto-top";
+		json_file = "";
+		flatten = true;
+		abc9 = false;
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		string run_from, run_to;
+		clear_flags();
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-top" && argidx+1 < args.size()) {
+				top_opt = "-top " + args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-json" && argidx+1 < args.size()) {
+				json_file = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-run" && argidx+1 < args.size()) {
+				size_t pos = args[argidx+1].find(':');
+				if (pos == std::string::npos)
+					break;
+				run_from = args[++argidx].substr(0, pos);
+				run_to = args[argidx].substr(pos+1);
+				continue;
+			}
+			if (args[argidx] == "-flatten") {
+				flatten = true;
+				continue;
+			}
+			if (args[argidx] == "-noflatten") {
+				flatten = false;
+				continue;
+			}
+			if (args[argidx] == "-abc9") {
+				abc9 = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		if (!design->full_selection())
+			log_cmd_error("This command only operates on fully selected designs!\n");
+
+		log_header(design, "Executing SYNTH_NANOXPLORE pass.\n");
+		log_push();
+
+		run_script(design, run_from, run_to);
+
+		log_pop();
+	}
+
+	void script() override
+	{
+		if (check_label("begin"))
+		{
+			run("read_verilog -lib -specify +/nanoxplore/cells_sim.v");
+			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
+		}
+
+		if (check_label("coarse"))
+		{
+			run("proc");
+			if (flatten || help_mode)
+				run("flatten", "(skip if -noflatten)");
+			run("tribuf -logic");
+			run("deminout");
+			run("opt_expr");
+			run("opt_clean");
+			run("check");
+			run("opt -nodffe -nosdff");
+			run("fsm");
+			run("opt");
+			run("wreduce");
+			run("peepopt");
+			run("opt_clean");
+			run("share");
+			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
+			run("opt_expr");
+			run("opt_clean");
+			run("alumacc");
+			run("opt");
+			run("memory -nomap");
+			run("opt_clean");
+		}
+
+		if (check_label("map_ram"))
+		{
+		}
+
+		if (check_label("map_ffram"))
+		{
+			run("opt -fast -mux_undef -undriven -fine");
+			run("memory_map");
+			run("opt -undriven -fine -mux_undef");
+		}
+
+		if (check_label("map_gates"))
+		{
+			run("techmap");
+			run("opt -fast");
+		}
+
+		if (check_label("map_ffs"))
+		{
+			run("techmap");
+			run("dfflegalize -cell $_DFF_?P?_ 0 -cell $_ALDFF_?P_ 0 -cell $_SDFF_?P?_ 0");
+			run("techmap -map +/nanoxplore/cells_map.v");
+			run("opt_expr -undriven -mux_undef");
+			run("clean -purge");
+		}
+
+		if (check_label("map_luts"))
+		{
+			if (abc9) {
+				std::string abc9_opts = " -maxlut 4";
+				std::string k = "synth_nanoxplore.abc9.W";
+				if (active_design && active_design->scratchpad.count(k))
+					abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
+				else
+					abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
+				run("abc9" + abc9_opts);
+			} else {
+				std::string abc_args = " -dress";
+				abc_args += " -lut 4";
+				run("abc" + abc_args);
+			}
+			run("techmap -map +/nanoxplore/cells_map.v t:$lut");
+			run("opt -fast");
+			run("clean");
+		}
+
+		if (check_label("check"))
+		{
+			run("autoname");
+			run("hierarchy -check");
+			run("stat");
+			run("check -noinit");
+			run("blackbox =A:whitebox");
+		}
+
+		if (check_label("json"))
+		{
+			if (!json_file.empty() || help_mode)
+				run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
+		}
+	}
+} SynthNanoXplorePass;
+
+PRIVATE_NAMESPACE_END

From 94b6f19cf0a1cc5077c84d31528a34b26a0d1bae Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 1 Mar 2024 10:44:42 +0100
Subject: [PATCH 261/499] Make lut init match vendor tools

---
 techlibs/nanoxplore/cells_map.v | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v
index 4a83fafc208..a0d0e6957d2 100644
--- a/techlibs/nanoxplore/cells_map.v
+++ b/techlibs/nanoxplore/cells_map.v
@@ -10,19 +10,20 @@ module \$lut (A, Y);
 
   generate
     if (WIDTH == 1) begin
-      localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}};
+      localparam [15:0] INIT = {{2{LUT[1:0]}}, {2{LUT[1:0]}}, {2{LUT[1:0]}}, {2{LUT[1:0]}},
+                                {2{LUT[1:0]}}, {2{LUT[1:0]}}, {2{LUT[1:0]}}, {2{LUT[1:0]}}};
       NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I1(1'b0), .I2(1'b0), .I3(1'b0), .I4(A[0]));
+        .I1(A[0]), .I2(1'b0), .I3(1'b0), .I4(1'b0));
     end else
     if (WIDTH == 2) begin
-      localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}};
+      localparam [15:0] INIT = {{4{LUT[3:0]}}, {4{LUT[3:0]}}, {4{LUT[3:0]}}, {4{LUT[3:0]}}};
       NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I1(1'b0), .I2(1'b0), .I3(A[0]), .I4(A[1]));
+        .I1(A[0]), .I2(A[1]), .I3(1'b0), .I4(1'b0), );
     end else
     if (WIDTH == 3) begin
-      localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}};
+      localparam [15:0] INIT = {{8{LUT[7:0]}}, {8{LUT[7:0]}}};
       NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I1(1'b0), .I2(A[0]), .I3(A[1]), .I4(A[2]));
+        .I1(A[0]), .I2(A[1]), .I3(A[2]), .I4(1'b0));
     end else
     if (WIDTH == 4) begin
       NX_LUT #(.lut_table(LUT)) _TECHMAP_REPLACE_ (.O(Y),

From 93543bd87476351af0aee3f45eb6717e79610d64 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 1 Mar 2024 10:45:15 +0100
Subject: [PATCH 262/499] add lut tests

---
 tests/arch/nanoxplore/.gitignore  | 2 ++
 tests/arch/nanoxplore/logic.ys    | 9 +++++++++
 tests/arch/nanoxplore/run-test.sh | 4 ++++
 3 files changed, 15 insertions(+)
 create mode 100644 tests/arch/nanoxplore/.gitignore
 create mode 100644 tests/arch/nanoxplore/logic.ys
 create mode 100755 tests/arch/nanoxplore/run-test.sh

diff --git a/tests/arch/nanoxplore/.gitignore b/tests/arch/nanoxplore/.gitignore
new file mode 100644
index 00000000000..1d329c9331d
--- /dev/null
+++ b/tests/arch/nanoxplore/.gitignore
@@ -0,0 +1,2 @@
+*.log
+/run-test.mk
diff --git a/tests/arch/nanoxplore/logic.ys b/tests/arch/nanoxplore/logic.ys
new file mode 100644
index 00000000000..2edcbfebd79
--- /dev/null
+++ b/tests/arch/nanoxplore/logic.ys
@@ -0,0 +1,9 @@
+read_verilog ../common/logic.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 9 t:NX_LUT
+select -assert-none t:NX_LUT %% t:* %D
diff --git a/tests/arch/nanoxplore/run-test.sh b/tests/arch/nanoxplore/run-test.sh
new file mode 100755
index 00000000000..4be4b70ae17
--- /dev/null
+++ b/tests/arch/nanoxplore/run-test.sh
@@ -0,0 +1,4 @@
+#!/usr/bin/env bash
+set -eu
+source ../../gen-tests-makefile.sh
+run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"

From b4a17cccc30c9bf2ea2a4c212882eaca4be73ce6 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 1 Mar 2024 10:49:48 +0100
Subject: [PATCH 263/499] add few more tests

---
 tests/arch/nanoxplore/mux.ys    | 41 +++++++++++++++++++++++++++++++++
 tests/arch/nanoxplore/tribuf.ys | 12 ++++++++++
 2 files changed, 53 insertions(+)
 create mode 100644 tests/arch/nanoxplore/mux.ys
 create mode 100644 tests/arch/nanoxplore/tribuf.ys

diff --git a/tests/arch/nanoxplore/mux.ys b/tests/arch/nanoxplore/mux.ys
new file mode 100644
index 00000000000..8c92ab15609
--- /dev/null
+++ b/tests/arch/nanoxplore/mux.ys
@@ -0,0 +1,41 @@
+read_verilog ../common/mux.v
+design -save read
+
+hierarchy -top mux2
+proc
+equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:NX_LUT
+
+select -assert-none t:NX_LUT %% t:* %D
+
+design -load read
+hierarchy -top mux4
+proc
+equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+#select -assert-count 2 t:NX_LUT
+
+select -assert-none t:NX_LUT %% t:* %D
+
+design -load read
+hierarchy -top mux8
+proc
+equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+#select -assert-count 5 t:NX_LUT
+
+select -assert-none t:NX_LUT %% t:* %D
+
+design -load read
+hierarchy -top mux16
+proc
+equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux16 # Constrain all select calls below inside the top module
+select -assert-max 13 t:NX_LUT
+
+select -assert-none t:NX_LUT %% t:* %D
diff --git a/tests/arch/nanoxplore/tribuf.ys b/tests/arch/nanoxplore/tribuf.ys
new file mode 100644
index 00000000000..c72e2e1ad5e
--- /dev/null
+++ b/tests/arch/nanoxplore/tribuf.ys
@@ -0,0 +1,12 @@
+read_verilog ../common/tribuf.v
+hierarchy -top tristate
+proc
+tribuf
+flatten
+synth
+equiv_opt -assert -map +/nanoxplore/cells_sim.v -map +/simcells.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd tristate # Constrain all select calls below inside the top module
+#Internal cell type used. Need support it.
+select -assert-count 1 t:$_TBUF_
+select -assert-none t:$_TBUF_ %% t:* %D

From b4e9bb0d85f38ce81fd3eb7733e8ea35a269dc82 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Fri, 1 Mar 2024 10:55:54 +0100
Subject: [PATCH 264/499] Add FFs and related tests

---
 techlibs/nanoxplore/cells_map.v  | 33 +++++++++++++++++++++++
 techlibs/nanoxplore/cells_sim.v  | 25 +++++++++++++++++
 tests/arch/nanoxplore/adffs.ys   | 46 ++++++++++++++++++++++++++++++++
 tests/arch/nanoxplore/dffs.ys    | 22 +++++++++++++++
 tests/arch/nanoxplore/fsm.ys     | 16 +++++++++++
 tests/arch/nanoxplore/latches.ys | 35 ++++++++++++++++++++++++
 tests/arch/nanoxplore/shifter.ys | 10 +++++++
 7 files changed, 187 insertions(+)
 create mode 100644 tests/arch/nanoxplore/adffs.ys
 create mode 100644 tests/arch/nanoxplore/dffs.ys
 create mode 100644 tests/arch/nanoxplore/fsm.ys
 create mode 100644 tests/arch/nanoxplore/latches.ys
 create mode 100644 tests/arch/nanoxplore/shifter.ys

diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v
index a0d0e6957d2..efa2a2af541 100644
--- a/techlibs/nanoxplore/cells_map.v
+++ b/techlibs/nanoxplore/cells_map.v
@@ -33,3 +33,36 @@ module \$lut (A, Y);
     end
   endgenerate
 endmodule
+
+(* techmap_celltype = "$_DFF_[NP]P[01]_" *)
+module dff(input D, C, R, output Q);
+	parameter _TECHMAP_CELLTYPE = "$_DFF_PP1_";
+  localparam dff_edge = _TECHMAP_CELLTYPE[6*8 +: 8] == "N";
+  localparam dff_type = _TECHMAP_CELLTYPE[8*8 +: 8] == "1";
+  wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
+  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
+endmodule
+
+(* techmap_celltype = "$_ALDFF_[NP]P_" *)
+module aldff(input D, C, L, AD, output Q);
+	parameter _TECHMAP_CELLTYPE = "$_ALDFF_PP_";
+  localparam dff_edge = _TECHMAP_CELLTYPE[8*8 +: 8] == "N";
+  wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
+  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(2)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(AD), .R(L), .O(Q));
+endmodule
+
+module \$_SDFF_PP0_ (input D, C, R, output Q);
+  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
+endmodule
+
+module \$_SDFF_PP1_ (input D, C, R, output Q);
+  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
+endmodule
+
+module \$_SDFF_NP0_ (input D, C, R, output Q);
+  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
+endmodule
+
+module \$_SDFF_NP1_ (input D, C, R, output Q);
+  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
+endmodule
diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v
index d665e0f89e3..0a69a8a6ae8 100644
--- a/techlibs/nanoxplore/cells_sim.v
+++ b/techlibs/nanoxplore/cells_sim.v
@@ -8,3 +8,28 @@ wire [1:0] s3 = I2 ? s2[3:2] : s2[1:0];
 assign O = I1 ? s3[1] : s3[0];
 
 endmodule
+
+module NX_DFF(input I, CK, L, R, output reg O);
+
+parameter dff_ctxt = 1'bx;
+parameter dff_edge = 1'b0;
+parameter dff_init = 1'b0;
+parameter dff_load = 1'b0;
+parameter dff_sync = 1'b0;
+parameter dff_type = 1'b0;
+
+initial begin
+	O = dff_ctxt;
+end
+
+wire clock = CK ^ dff_edge;
+wire load = (dff_type == 2) ? (dff_load ? L : 1'bx) : dff_type;
+wire async_reset = !dff_sync && dff_init && R;
+wire sync_reset = dff_sync && dff_init && R;
+
+always @(posedge clock, posedge async_reset)
+	if (async_reset) O <= load;
+	else if (sync_reset) O <= load;
+	else O <= I;
+
+endmodule
diff --git a/tests/arch/nanoxplore/adffs.ys b/tests/arch/nanoxplore/adffs.ys
new file mode 100644
index 00000000000..6a4f63ad7c7
--- /dev/null
+++ b/tests/arch/nanoxplore/adffs.ys
@@ -0,0 +1,46 @@
+read_verilog ../common/adffs.v
+design -save read
+
+hierarchy -top adff
+proc
+equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adff # Constrain all select calls below inside the top module
+select -assert-count 1 t:NX_DFF
+
+select -assert-none t:NX_DFF %% t:* %D
+
+
+design -load read
+hierarchy -top adffn
+proc
+equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:NX_DFF
+select -assert-count 1 t:NX_LUT
+
+select -assert-none t:NX_DFF t:NX_LUT %% t:* %D
+
+
+design -load read
+hierarchy -top dffs
+proc
+equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:NX_DFF
+
+select -assert-none t:NX_DFF %% t:* %D
+
+
+design -load read
+hierarchy -top ndffnr
+proc
+equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:NX_DFF
+select -assert-count 1 t:NX_LUT
+
+select -assert-none t:NX_DFF t:NX_LUT %% t:* %D
diff --git a/tests/arch/nanoxplore/dffs.ys b/tests/arch/nanoxplore/dffs.ys
new file mode 100644
index 00000000000..ba7dff41c46
--- /dev/null
+++ b/tests/arch/nanoxplore/dffs.ys
@@ -0,0 +1,22 @@
+read_verilog ../common/dffs.v
+design -save read
+
+hierarchy -top dff
+proc
+equiv_opt -assert -async2sync -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dff # Constrain all select calls below inside the top module
+select -assert-count 1 t:NX_DFF
+
+select -assert-none t:NX_DFF %% t:* %D
+
+design -load read
+hierarchy -top dffe
+proc
+equiv_opt -assert -async2sync -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:NX_DFF
+select -assert-count 1 t:NX_LUT
+
+select -assert-none t:NX_DFF t:NX_LUT %% t:* %D
diff --git a/tests/arch/nanoxplore/fsm.ys b/tests/arch/nanoxplore/fsm.ys
new file mode 100644
index 00000000000..ee00be4e1bd
--- /dev/null
+++ b/tests/arch/nanoxplore/fsm.ys
@@ -0,0 +1,16 @@
+read_verilog ../common/fsm.v
+hierarchy -top fsm
+proc
+flatten
+
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v synth_nanoxplore
+async2sync
+miter -equiv -make_assert -flatten gold gate miter
+sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
+
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd fsm # Constrain all select calls below inside the top module
+
+select -assert-count 6 t:NX_DFF
+select -assert-count 13 t:NX_LUT
+select -assert-none t:NX_DFF t:NX_LUT %% t:* %D
diff --git a/tests/arch/nanoxplore/latches.ys b/tests/arch/nanoxplore/latches.ys
new file mode 100644
index 00000000000..32609dbce40
--- /dev/null
+++ b/tests/arch/nanoxplore/latches.ys
@@ -0,0 +1,35 @@
+read_verilog ../common/latches.v
+design -save read
+
+hierarchy -top latchp
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_nanoxplore
+cd latchp # Constrain all select calls below inside the top module
+select -assert-count 1 t:NX_DFF
+
+select -assert-none t:NX_DFF %% t:* %D
+
+
+design -load read
+hierarchy -top latchn
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_nanoxplore
+cd latchn # Constrain all select calls below inside the top module
+select -assert-count 1 t:NX_LUT
+select -assert-count 1 t:NX_DFF
+
+select -assert-none t:NX_LUT t:NX_DFF %% t:* %D
+
+
+design -load read
+hierarchy -top latchsr
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_nanoxplore
+cd latchsr # Constrain all select calls below inside the top module
+select -assert-count 2 t:NX_LUT
+select -assert-count 1 t:NX_DFF
+
+select -assert-none t:NX_LUT t:NX_DFF %% t:* %D
diff --git a/tests/arch/nanoxplore/shifter.ys b/tests/arch/nanoxplore/shifter.ys
new file mode 100644
index 00000000000..a3502df2a3e
--- /dev/null
+++ b/tests/arch/nanoxplore/shifter.ys
@@ -0,0 +1,10 @@
+read_verilog ../common/shifter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 8  t:NX_DFF
+select -assert-none t:NX_DFF %% t:* %D

From b3f59c98209e43029afea0a44ce3bd5b94cea38d Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Fri, 1 Mar 2024 11:10:52 +0100
Subject: [PATCH 265/499] Add NX_CY

---
 techlibs/nanoxplore/Makefile.inc |  1 +
 techlibs/nanoxplore/arith_map.v  | 71 ++++++++++++++++++++++++++++++++
 techlibs/nanoxplore/cells_sim.v  |  6 +++
 tests/arch/nanoxplore/add_sub.ys | 10 +++++
 4 files changed, 88 insertions(+)
 create mode 100644 techlibs/nanoxplore/arith_map.v
 create mode 100644 tests/arch/nanoxplore/add_sub.ys

diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc
index 7e2923c4018..bd8bd228e6d 100644
--- a/techlibs/nanoxplore/Makefile.inc
+++ b/techlibs/nanoxplore/Makefile.inc
@@ -2,5 +2,6 @@
 OBJS += techlibs/nanoxplore/synth_nanoxplore.o
 
 # Techmap
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v))
diff --git a/techlibs/nanoxplore/arith_map.v b/techlibs/nanoxplore/arith_map.v
new file mode 100644
index 00000000000..69e83b68ccd
--- /dev/null
+++ b/techlibs/nanoxplore/arith_map.v
@@ -0,0 +1,71 @@
+`default_nettype none
+
+(* techmap_celltype = "$alu" *)
+module _80_nx_cy_alu (A, B, CI, BI, X, Y, CO);
+	parameter A_SIGNED = 0;
+	parameter B_SIGNED = 0;
+	parameter A_WIDTH = 1;
+	parameter B_WIDTH = 1;
+	parameter Y_WIDTH = 1;
+
+	(* force_downto *)
+	input [A_WIDTH-1:0] A;
+	(* force_downto *)
+	input [B_WIDTH-1:0] B;
+	(* force_downto *)
+	output [Y_WIDTH-1:0] X, Y;
+
+	input CI, BI;
+	(* force_downto *)
+	output [Y_WIDTH-1:0] CO;
+
+	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+	(* force_downto *)
+	wire [Y_WIDTH-1:0] A_buf, B_buf;
+	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+	function integer round_up4;
+		input integer N;
+		begin
+			round_up4 = ((N + 3) / 4) * 4;
+		end
+	endfunction
+
+	localparam Y_WIDTH4 = round_up4(Y_WIDTH);
+
+	(* force_downto *)
+	wire [Y_WIDTH4-1:0] AA = A_buf;
+	(* force_downto *)
+	wire [Y_WIDTH4-1:0] BB = BI ? ~B_buf : B_buf;
+	(* force_downto *)
+	wire [Y_WIDTH4-1:0] BX = B_buf;
+	(* force_downto *)
+	wire [Y_WIDTH4:0] C = {CO, CI};
+	(* force_downto *)
+	wire [Y_WIDTH4-1:0] FCO, Y1;
+
+	genvar i;
+	generate for (i = 0; i < Y_WIDTH4; i = i + 4) begin:slice
+        NX_CY cy_i (
+            .CI(C[i]),
+            .A1(AA[i]), .A2(AA[i+1]), .A3(AA[i+2]), .A4(AA[i+3]),
+            .B1(BB[i]), .B2(BB[i+1]), .B3(BB[i+2]), .B4(BB[i+3]),
+            .S1(Y1[i]), .S2(Y1[i+1]), .S3(Y1[i+2]), .S4(Y1[i+3]),
+            .CO(FCO[i])
+        );
+
+		assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
+        if (i+1 < Y_WIDTH)
+		    assign CO[i+1] = (AA[i+1] && BB[i+1]) || (C[i+1] && (AA[i+1] || BB[i+1]));
+		if (i+2 < Y_WIDTH)
+            assign CO[i+2] = (AA[i+2] && BB[i+2]) || (C[i+2] && (AA[i+2] || BB[i+2]));
+        if (i+3 < Y_WIDTH)
+            assign CO[i+3] = FCO[i];
+
+	end endgenerate
+
+	assign X = AA ^ BB;
+    assign Y = Y1[Y_WIDTH-1:0];
+endmodule
diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v
index 0a69a8a6ae8..1f04b216ee0 100644
--- a/techlibs/nanoxplore/cells_sim.v
+++ b/techlibs/nanoxplore/cells_sim.v
@@ -33,3 +33,9 @@ always @(posedge clock, posedge async_reset)
 	else O <= I;
 
 endmodule
+
+module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO);
+parameter add_carry = 0;
+
+assign {CO, S4, S3, S2, S1} = {A4, A3, A2, A1} + {B4, B3, B2, B1} + CI;
+endmodule
diff --git a/tests/arch/nanoxplore/add_sub.ys b/tests/arch/nanoxplore/add_sub.ys
new file mode 100644
index 00000000000..0cfc201f502
--- /dev/null
+++ b/tests/arch/nanoxplore/add_sub.ys
@@ -0,0 +1,10 @@
+read_verilog ../common/add_sub.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 2 t:NX_CY
+select -assert-count 4 t:NX_LUT
+select -assert-none t:NX_CY t:NX_LUT %% t:* %D
+

From 8374f0336de9f031ea8dac5c13df4eb56c6fc440 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 1 Mar 2024 11:11:23 +0100
Subject: [PATCH 266/499] add family and ability to disable carry chains

---
 techlibs/nanoxplore/synth_nanoxplore.cc | 38 ++++++++++++++++++++++---
 1 file changed, 34 insertions(+), 4 deletions(-)

diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index 3d8a34c0609..eda65b66b40 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -2,6 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2024 Hannah Ravensloft <lofty@yosyshq.com> 
+ *  Copyright (C) 2024 Miodrag Milanovic <micko@yosyshq.com> 
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -45,6 +46,15 @@ struct SynthNanoXplorePass : public ScriptPass
 		log("    -top <module>\n");
 		log("        use the specified module as top module\n");
 		log("\n");
+		log("    -family <family>\n");
+		log("        run synthesis for the specified NanoXplore architecture\n");
+		log("        generate the synthesis netlist for the specified family.\n");
+		log("        supported values:\n");
+		log("        - medium: NG-Medium\n");
+		log("        - large: NG-Large\n");
+		log("        - ultra: NG-Ultra\n");
+		log("        - u300: NG-Ultra300\n");
+		log("\n");
 		log("    -json <file>\n");
 		log("        write the design to the specified JSON file. writing of an output file\n");
 		log("        is omitted if this parameter is not specified.\n");
@@ -60,21 +70,26 @@ struct SynthNanoXplorePass : public ScriptPass
 		log("    -abc9\n");
 		log("        use new ABC9 flow (EXPERIMENTAL)\n");
 		log("\n");
+		log("    -nocy\n");
+		log("        do not map adders to CY cells\n");
+		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
 		help_script();
 		log("\n");
 	}
 
-	string top_opt, json_file;
-	bool flatten, abc9;
+	string top_opt, json_file, family;
+	bool flatten, abc9, nocy;
 
 	void clear_flags() override
 	{
 		top_opt = "-auto-top";
 		json_file = "";
+		family = "";
 		flatten = true;
 		abc9 = false;
+		nocy = false;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -89,6 +104,10 @@ struct SynthNanoXplorePass : public ScriptPass
 				top_opt = "-top " + args[++argidx];
 				continue;
 			}
+			if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
+				family = args[++argidx];
+				continue;
+			}
 			if (args[argidx] == "-json" && argidx+1 < args.size()) {
 				json_file = args[++argidx];
 				continue;
@@ -113,10 +132,19 @@ struct SynthNanoXplorePass : public ScriptPass
 				abc9 = true;
 				continue;
 			}
+			if (args[argidx] == "-nocy") {
+				nocy = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
 
+		if (family.empty()) {
+			log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n");
+			family = "ultra";
+		}
+
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
 
@@ -175,13 +203,15 @@ struct SynthNanoXplorePass : public ScriptPass
 
 		if (check_label("map_gates"))
 		{
-			run("techmap");
+			if (nocy)
+				run("techmap");
+			else
+				run("techmap -map +/techmap.v -map +/nanoxplore/arith_map.v");
 			run("opt -fast");
 		}
 
 		if (check_label("map_ffs"))
 		{
-			run("techmap");
 			run("dfflegalize -cell $_DFF_?P?_ 0 -cell $_ALDFF_?P_ 0 -cell $_SDFF_?P?_ 0");
 			run("techmap -map +/nanoxplore/cells_map.v");
 			run("opt_expr -undriven -mux_undef");

From 5d898ab22392335d019c85fdd1b71e3986091a39 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 1 Mar 2024 12:07:20 +0100
Subject: [PATCH 267/499] Add blackboxes

---
 techlibs/nanoxplore/Makefile.inc        |     1 +
 techlibs/nanoxplore/cells_bb.v          | 33105 ++++++++++++++++++++++
 techlibs/nanoxplore/synth_nanoxplore.cc |     2 +-
 3 files changed, 33107 insertions(+), 1 deletion(-)
 create mode 100644 techlibs/nanoxplore/cells_bb.v

diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc
index bd8bd228e6d..0f7bcdbeda8 100644
--- a/techlibs/nanoxplore/Makefile.inc
+++ b/techlibs/nanoxplore/Makefile.inc
@@ -3,5 +3,6 @@ OBJS += techlibs/nanoxplore/synth_nanoxplore.o
 
 # Techmap
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v))
diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
new file mode 100644
index 00000000000..7ebad4ae8fd
--- /dev/null
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -0,0 +1,33105 @@
+(* blackbox *)
+module ACC84_2DSP(clk, rst, X, Z);
+    input [83:0] X;
+    output [84:0] Z;
+    input clk;
+    input rst;
+    parameter g_pipe = 2;
+endmodule
+
+(* blackbox *)
+module ACC92_2DSP(clk, rst, X, Z);
+    input [55:0] X;
+    output [91:0] Z;
+    input clk;
+    input rst;
+    parameter g_pipe = 2;
+endmodule
+
+(* blackbox *)
+module ACC98_2DSP(clk, rst, X, Z);
+    input [55:0] X;
+    output [97:0] Z;
+    input clk;
+    input rst;
+    parameter g_pipe = 2;
+endmodule
+
+(* blackbox *)
+module ADD84_1DSP_2CYCLES(clk, rst, X, Y, Z);
+    input [41:0] X;
+    input [41:0] Y;
+    output [84:0] Z;
+    input clk;
+    input rst;
+    parameter piped = "true";
+endmodule
+
+(* blackbox *)
+module ADD84_2DSP(clk, rst, X, Y, Z);
+    input [83:0] X;
+    input [83:0] Y;
+    output [84:0] Z;
+    input clk;
+    input rst;
+    parameter piped = "true";
+endmodule
+
+(* blackbox *)
+module NX_BD(I, O);
+    input I;
+    output O;
+    parameter mode = "global_lowskew";
+endmodule
+
+(* blackbox *)
+module NX_BFF(I, O);
+    input I;
+    output O;
+endmodule
+
+(* blackbox *)
+module NX_BFR(I, O);
+    input I;
+    output O;
+    parameter data_inv = 1'b0;
+    parameter iobname = "";
+    parameter location = "";
+    parameter mode = 0;
+    parameter path = 0;
+    parameter ring = 0;
+endmodule
+
+(* blackbox *)
+module NX_CDC_L(CK1, CK2, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BI1, BI2, BI3, BI4, BI5, BI6, BO1
+, BO2, BO3, BO4, BO5, BO6, CI1, CI2, CI3, CI4, CI5, CI6, CO1, CO2, CO3, CO4, CO5, CO6, DI1, DI2, DI3, DI4
+, DI5, DI6, DO1, DO2, DO3, DO4, DO5, DO6);
+    input AI1;
+    input AI2;
+    input AI3;
+    input AI4;
+    input AI5;
+    input AI6;
+    output AO1;
+    output AO2;
+    output AO3;
+    output AO4;
+    output AO5;
+    output AO6;
+    input BI1;
+    input BI2;
+    input BI3;
+    input BI4;
+    input BI5;
+    input BI6;
+    output BO1;
+    output BO2;
+    output BO3;
+    output BO4;
+    output BO5;
+    output BO6;
+    input CI1;
+    input CI2;
+    input CI3;
+    input CI4;
+    input CI5;
+    input CI6;
+    input CK1;
+    input CK2;
+    output CO1;
+    output CO2;
+    output CO3;
+    output CO4;
+    output CO5;
+    output CO6;
+    input DI1;
+    input DI2;
+    input DI3;
+    input DI4;
+    input DI5;
+    input DI6;
+    output DO1;
+    output DO2;
+    output DO3;
+    output DO4;
+    output DO5;
+    output DO6;
+    parameter ack_sel = 1'b0;
+    parameter bck_sel = 1'b0;
+    parameter cck_sel = 1'b0;
+    parameter ck0_edge = 1'b0;
+    parameter ck1_edge = 1'b0;
+    parameter dck_sel = 1'b0;
+    parameter gt0_bypass_reg1 = 1'b0;
+    parameter gt0_bypass_reg2 = 1'b0;
+    parameter gt1_bypass_reg1 = 1'b0;
+    parameter gt1_bypass_reg2 = 1'b0;
+    parameter link_BA = 1'b0;
+    parameter link_CB = 1'b0;
+    parameter link_DC = 1'b0;
+    parameter mode = 0;
+    parameter use_adest_arst = 2'b00;
+    parameter use_asrc_arst = 2'b00;
+    parameter use_bdest_arst = 2'b00;
+    parameter use_bsrc_arst = 2'b00;
+    parameter use_cdest_arst = 2'b00;
+    parameter use_csrc_arst = 2'b00;
+    parameter use_ddest_arst = 2'b00;
+    parameter use_dsrc_arst = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_CDC_L_2DFF(CK1, CK2, ADRSTI, BDRSTI, BI, AO, BO, AI);
+    input ADRSTI;
+    input [5:0] AI;
+    output [5:0] AO;
+    input BDRSTI;
+    input [5:0] BI;
+    output [5:0] BO;
+    input CK1;
+    input CK2;
+    parameter ack_sel = 1'b0;
+    parameter bck_sel = 1'b0;
+    parameter ck0_edge = 1'b0;
+    parameter ck1_edge = 1'b0;
+    parameter gt0_bypass_reg1 = 1'b0;
+    parameter gt0_bypass_reg2 = 1'b0;
+    parameter gt1_bypass_reg1 = 1'b0;
+    parameter gt1_bypass_reg2 = 1'b0;
+    parameter use_adest_arst = 2'b00;
+    parameter use_bdest_arst = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_CDC_L_3DFF(CK1, CK2, ASRSTI, ADRSTI, BDRSTI, BSRSTI, BI, AO, BO, AI);
+    input ADRSTI;
+    input [5:0] AI;
+    output [5:0] AO;
+    input ASRSTI;
+    input BDRSTI;
+    input [5:0] BI;
+    output [5:0] BO;
+    input BSRSTI;
+    input CK1;
+    input CK2;
+    parameter ack_sel = 1'b0;
+    parameter bck_sel = 1'b0;
+    parameter ck0_edge = 1'b0;
+    parameter ck1_edge = 1'b0;
+    parameter gt0_bypass_reg1 = 1'b0;
+    parameter gt0_bypass_reg2 = 1'b0;
+    parameter gt1_bypass_reg1 = 1'b0;
+    parameter gt1_bypass_reg2 = 1'b0;
+    parameter use_adest_arst = 2'b00;
+    parameter use_asrc_arst = 2'b00;
+    parameter use_bdest_arst = 2'b00;
+    parameter use_bsrc_arst = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_CDC_L_BIN2GRAY(CK1, CK2, BI, AO, BO, AI);
+    input [5:0] AI;
+    output [5:0] AO;
+    input [5:0] BI;
+    output [5:0] BO;
+    input CK1;
+    input CK2;
+endmodule
+
+(* blackbox *)
+module NX_CDC_L_FULL(CK1, CK2, ASRSTI, ADRSTI, BDRSTI, BSRSTI, BI, AO, BO, AI);
+    input ADRSTI;
+    input [5:0] AI;
+    output [5:0] AO;
+    input ASRSTI;
+    input BDRSTI;
+    input [5:0] BI;
+    output [5:0] BO;
+    input BSRSTI;
+    input CK1;
+    input CK2;
+    parameter ack_sel = 1'b0;
+    parameter bck_sel = 1'b0;
+    parameter ck0_edge = 1'b0;
+    parameter ck1_edge = 1'b0;
+    parameter gt0_bypass_reg1 = 1'b0;
+    parameter gt0_bypass_reg2 = 1'b0;
+    parameter gt1_bypass_reg1 = 1'b0;
+    parameter gt1_bypass_reg2 = 1'b0;
+    parameter use_adest_arst = 2'b00;
+    parameter use_asrc_arst = 2'b00;
+    parameter use_bdest_arst = 2'b00;
+    parameter use_bsrc_arst = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_CDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BSRSTI, BDRSTI, BSRSTO
+, BDRSTO, BI1, BI2, BI3, BI4, BI5, BI6, BO1, BO2, BO3, BO4, BO5, BO6, CSRSTI, CDRSTI, CSRSTO, CDRSTO, CI1, CI2, CI3, CI4
+, CI5, CI6, CO1, CO2, CO3, CO4, CO5, CO6, DSRSTI, DDRSTI, DSRSTO, DDRSTO, DI1, DI2, DI3, DI4, DI5, DI6, DO1, DO2, DO3
+, DO4, DO5, DO6);
+    input ADRSTI;
+    output ADRSTO;
+    input AI1;
+    input AI2;
+    input AI3;
+    input AI4;
+    input AI5;
+    input AI6;
+    output AO1;
+    output AO2;
+    output AO3;
+    output AO4;
+    output AO5;
+    output AO6;
+    input ASRSTI;
+    output ASRSTO;
+    input BDRSTI;
+    output BDRSTO;
+    input BI1;
+    input BI2;
+    input BI3;
+    input BI4;
+    input BI5;
+    input BI6;
+    output BO1;
+    output BO2;
+    output BO3;
+    output BO4;
+    output BO5;
+    output BO6;
+    input BSRSTI;
+    output BSRSTO;
+    input CDRSTI;
+    output CDRSTO;
+    input CI1;
+    input CI2;
+    input CI3;
+    input CI4;
+    input CI5;
+    input CI6;
+    input CK1;
+    input CK2;
+    output CO1;
+    output CO2;
+    output CO3;
+    output CO4;
+    output CO5;
+    output CO6;
+    input CSRSTI;
+    output CSRSTO;
+    input DDRSTI;
+    output DDRSTO;
+    input DI1;
+    input DI2;
+    input DI3;
+    input DI4;
+    input DI5;
+    input DI6;
+    output DO1;
+    output DO2;
+    output DO3;
+    output DO4;
+    output DO5;
+    output DO6;
+    input DSRSTI;
+    output DSRSTO;
+    parameter ack_sel = 1'b0;
+    parameter bck_sel = 1'b0;
+    parameter cck_sel = 1'b0;
+    parameter ck0_edge = 1'b0;
+    parameter ck1_edge = 1'b0;
+    parameter dck_sel = 1'b0;
+    parameter link_BA = 1'b0;
+    parameter link_CB = 1'b0;
+    parameter link_DC = 1'b0;
+    parameter mode = 0;
+    parameter use_adest_arst = 1'b0;
+    parameter use_asrc_arst = 1'b0;
+    parameter use_bdest_arst = 1'b0;
+    parameter use_bsrc_arst = 1'b0;
+    parameter use_cdest_arst = 1'b0;
+    parameter use_csrc_arst = 1'b0;
+    parameter use_ddest_arst = 1'b0;
+    parameter use_dsrc_arst = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_CDC_U_2DFF(CK1, CK2, ADRSTI, ADRSTO, BDRSTI, BDRSTO, BI, AO, BO, AI);
+    input ADRSTI;
+    output ADRSTO;
+    input [5:0] AI;
+    output [5:0] AO;
+    input BDRSTI;
+    output BDRSTO;
+    input [5:0] BI;
+    output [5:0] BO;
+    input CK1;
+    input CK2;
+    parameter ack_sel = 1'b0;
+    parameter bck_sel = 1'b0;
+    parameter ck0_edge = 1'b0;
+    parameter ck1_edge = 1'b0;
+    parameter use_adest_arst = 1'b0;
+    parameter use_bdest_arst = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_CDC_U_3DFF(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, BI, AO, BO, AI);
+    input ADRSTI;
+    output ADRSTO;
+    input [5:0] AI;
+    output [5:0] AO;
+    input ASRSTI;
+    output ASRSTO;
+    input BDRSTI;
+    output BDRSTO;
+    input [5:0] BI;
+    output [5:0] BO;
+    input BSRSTI;
+    output BSRSTO;
+    input CK1;
+    input CK2;
+    parameter ack_sel = 1'b0;
+    parameter bck_sel = 1'b0;
+    parameter ck0_edge = 1'b0;
+    parameter ck1_edge = 1'b0;
+    parameter use_adest_arst = 1'b0;
+    parameter use_asrc_arst = 1'b0;
+    parameter use_bdest_arst = 1'b0;
+    parameter use_bsrc_arst = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_CDC_U_BIN2GRAY(BI, AO, BO, AI);
+    input [5:0] AI;
+    output [5:0] AO;
+    input [5:0] BI;
+    output [5:0] BO;
+endmodule
+
+(* blackbox *)
+module NX_CDC_U_FULL(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, BI, AO, BO, AI);
+    input ADRSTI;
+    output ADRSTO;
+    input [5:0] AI;
+    output [5:0] AO;
+    input ASRSTI;
+    output ASRSTO;
+    input BDRSTI;
+    output BDRSTO;
+    input [5:0] BI;
+    output [5:0] BO;
+    input BSRSTI;
+    output BSRSTO;
+    input CK1;
+    input CK2;
+    parameter ack_sel = 1'b0;
+    parameter bck_sel = 1'b0;
+    parameter ck0_edge = 1'b0;
+    parameter ck1_edge = 1'b0;
+    parameter use_adest_arst = 1'b0;
+    parameter use_asrc_arst = 1'b0;
+    parameter use_bdest_arst = 1'b0;
+    parameter use_bsrc_arst = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_CDC_U_GRAY2BIN(BI, AO, BO, AI);
+    input [5:0] AI;
+    output [5:0] AO;
+    input [5:0] BI;
+    output [5:0] BO;
+endmodule
+
+(* blackbox *)
+module NX_CKS(CKI, CMD, CKO);
+    input CKI;
+    output CKO;
+    input CMD;
+    parameter ck_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_CKS_U(CKI, CMD, CKO);
+    input CKI;
+    output CKO;
+    input CMD;
+endmodule
+
+(* blackbox *)
+module NX_CMUX_U(CKI0, CKI1, SEL, CKO);
+    input CKI0;
+    input CKI1;
+    output CKO;
+    input SEL;
+endmodule
+
+(* blackbox *)
+module NX_CRX_L(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, BUF_FE_I, RST_N_I, CDR_R_I, CKG_RN_I, PLL_RN_I, TST_I1, TST_I2, TST_I3, TST_I4, LOS_O, DATA_O1, DATA_O2, DATA_O3
+, DATA_O4, DATA_O5, DATA_O6, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24
+, DATA_O25, DATA_O26, DATA_O27, DATA_O28, DATA_O29, DATA_O30, DATA_O31, DATA_O32, DATA_O33, DATA_O34, DATA_O35, DATA_O36, DATA_O37, DATA_O38, DATA_O39, DATA_O40, DATA_O41, DATA_O42, DATA_O43, DATA_O44, DATA_O45
+, DATA_O46, DATA_O47, DATA_O48, DATA_O49, DATA_O50, DATA_O51, DATA_O52, DATA_O53, DATA_O54, DATA_O55, DATA_O56, DATA_O57, DATA_O58, DATA_O59, DATA_O60, DATA_O61, DATA_O62, DATA_O63, DATA_O64, CH_COM_O1, CH_COM_O2
+, CH_COM_O3, CH_COM_O4, CH_COM_O5, CH_COM_O6, CH_COM_O7, CH_COM_O8, CH_K_O1, CH_K_O2, CH_K_O3, CH_K_O4, CH_K_O5, CH_K_O6, CH_K_O7, CH_K_O8, NIT_O1, NIT_O2, NIT_O3, NIT_O4, NIT_O5, NIT_O6, NIT_O7
+, NIT_O8, D_ERR_O1, D_ERR_O2, D_ERR_O3, D_ERR_O4, D_ERR_O5, D_ERR_O6, D_ERR_O7, D_ERR_O8, CH_A_O1, CH_A_O2, CH_A_O3, CH_A_O4, CH_A_O5, CH_A_O6, CH_A_O7, CH_A_O8, CH_F_O1, CH_F_O2, CH_F_O3, CH_F_O4
+, CH_F_O5, CH_F_O6, CH_F_O7, CH_F_O8, ALIGN_O, BUSY_O, TST_O1, TST_O2, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, LOCK_O, RX_I, LINK);
+    input ALIGN_E_I;
+    output ALIGN_O;
+    input ALIGN_S_I;
+    input BUF_FE_I;
+    input BUF_R_I;
+    output BUSY_O;
+    input CDR_R_I;
+    output CH_A_O1;
+    output CH_A_O2;
+    output CH_A_O3;
+    output CH_A_O4;
+    output CH_A_O5;
+    output CH_A_O6;
+    output CH_A_O7;
+    output CH_A_O8;
+    output CH_COM_O1;
+    output CH_COM_O2;
+    output CH_COM_O3;
+    output CH_COM_O4;
+    output CH_COM_O5;
+    output CH_COM_O6;
+    output CH_COM_O7;
+    output CH_COM_O8;
+    output CH_F_O1;
+    output CH_F_O2;
+    output CH_F_O3;
+    output CH_F_O4;
+    output CH_F_O5;
+    output CH_F_O6;
+    output CH_F_O7;
+    output CH_F_O8;
+    output CH_K_O1;
+    output CH_K_O2;
+    output CH_K_O3;
+    output CH_K_O4;
+    output CH_K_O5;
+    output CH_K_O6;
+    output CH_K_O7;
+    output CH_K_O8;
+    input CKG_RN_I;
+    output DATA_O1;
+    output DATA_O10;
+    output DATA_O11;
+    output DATA_O12;
+    output DATA_O13;
+    output DATA_O14;
+    output DATA_O15;
+    output DATA_O16;
+    output DATA_O17;
+    output DATA_O18;
+    output DATA_O19;
+    output DATA_O2;
+    output DATA_O20;
+    output DATA_O21;
+    output DATA_O22;
+    output DATA_O23;
+    output DATA_O24;
+    output DATA_O25;
+    output DATA_O26;
+    output DATA_O27;
+    output DATA_O28;
+    output DATA_O29;
+    output DATA_O3;
+    output DATA_O30;
+    output DATA_O31;
+    output DATA_O32;
+    output DATA_O33;
+    output DATA_O34;
+    output DATA_O35;
+    output DATA_O36;
+    output DATA_O37;
+    output DATA_O38;
+    output DATA_O39;
+    output DATA_O4;
+    output DATA_O40;
+    output DATA_O41;
+    output DATA_O42;
+    output DATA_O43;
+    output DATA_O44;
+    output DATA_O45;
+    output DATA_O46;
+    output DATA_O47;
+    output DATA_O48;
+    output DATA_O49;
+    output DATA_O5;
+    output DATA_O50;
+    output DATA_O51;
+    output DATA_O52;
+    output DATA_O53;
+    output DATA_O54;
+    output DATA_O55;
+    output DATA_O56;
+    output DATA_O57;
+    output DATA_O58;
+    output DATA_O59;
+    output DATA_O6;
+    output DATA_O60;
+    output DATA_O61;
+    output DATA_O62;
+    output DATA_O63;
+    output DATA_O64;
+    output DATA_O7;
+    output DATA_O8;
+    output DATA_O9;
+    input DEC_E_I;
+    input DSCR_E_I;
+    output D_ERR_O1;
+    output D_ERR_O2;
+    output D_ERR_O3;
+    output D_ERR_O4;
+    output D_ERR_O5;
+    output D_ERR_O6;
+    output D_ERR_O7;
+    output D_ERR_O8;
+    inout [9:0] LINK;
+    output LOCK_O;
+    output LOS_O;
+    output NIT_O1;
+    output NIT_O2;
+    output NIT_O3;
+    output NIT_O4;
+    output NIT_O5;
+    output NIT_O6;
+    output NIT_O7;
+    output NIT_O8;
+    input OVS_BS_I1;
+    input OVS_BS_I2;
+    input PLL_RN_I;
+    input REP_E_I;
+    input RST_N_I;
+    input RX_I;
+    input TST_I1;
+    input TST_I2;
+    input TST_I3;
+    input TST_I4;
+    output TST_O1;
+    output TST_O2;
+    output TST_O3;
+    output TST_O4;
+    output TST_O5;
+    output TST_O6;
+    output TST_O7;
+    output TST_O8;
+    parameter location = "";
+    parameter pcs_8b_dscr_sel = 1'b0;
+    parameter pcs_align_bypass = 1'b0;
+    parameter pcs_buffers_bypass = 1'b0;
+    parameter pcs_buffers_use_cdc = 1'b0;
+    parameter pcs_bypass_pma_cdc = 1'b0;
+    parameter pcs_bypass_usr_cdc = 1'b0;
+    parameter pcs_comma_mask = 10'b0000000000;
+    parameter pcs_debug_en = 1'b0;
+    parameter pcs_dec_bypass = 1'b0;
+    parameter pcs_dscr_bypass = 1'b0;
+    parameter pcs_el_buff_diff_bef_comp = 3'b000;
+    parameter pcs_el_buff_max_comp = 3'b000;
+    parameter pcs_el_buff_only_one_skp = 1'b0;
+    parameter pcs_el_buff_skp_char_0 = 9'b000000000;
+    parameter pcs_el_buff_skp_char_1 = 9'b000000000;
+    parameter pcs_el_buff_skp_char_2 = 9'b000000000;
+    parameter pcs_el_buff_skp_char_3 = 9'b000000000;
+    parameter pcs_el_buff_skp_header_0 = 9'b000000000;
+    parameter pcs_el_buff_skp_header_1 = 9'b000000000;
+    parameter pcs_el_buff_skp_header_2 = 9'b000000000;
+    parameter pcs_el_buff_skp_header_3 = 9'b000000000;
+    parameter pcs_el_buff_skp_header_size = 2'b00;
+    parameter pcs_el_buff_skp_seq_size = 2'b00;
+    parameter pcs_el_buff_underflow_handle = 1'b0;
+    parameter pcs_fsm_sel = 2'b00;
+    parameter pcs_fsm_watchdog_en = 1'b0;
+    parameter pcs_loopback = 1'b0;
+    parameter pcs_m_comma_en = 1'b0;
+    parameter pcs_m_comma_val = 10'b0000000000;
+    parameter pcs_nb_comma_bef_realign = 2'b00;
+    parameter pcs_p_comma_en = 1'b0;
+    parameter pcs_p_comma_val = 10'b0000000000;
+    parameter pcs_polarity = 1'b0;
+    parameter pcs_protocol_size = 1'b0;
+    parameter pcs_replace_bypass = 1'b0;
+    parameter pcs_sync_supported = 1'b0;
+    parameter pma_cdr_cp = 4'b0000;
+    parameter pma_clk_pos = 1'b0;
+    parameter pma_ctrl_term = 6'b000000;
+    parameter pma_loopback = 1'b0;
+    parameter pma_pll_cpump_n = 3'b000;
+    parameter pma_pll_divf = 2'b00;
+    parameter pma_pll_divf_en_n = 1'b0;
+    parameter pma_pll_divm = 2'b00;
+    parameter pma_pll_divm_en_n = 1'b0;
+    parameter pma_pll_divn = 1'b0;
+    parameter pma_pll_divn_en_n = 1'b0;
+    parameter test = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_CRX_U(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, RST_N_I, PMA_RSTN_I, MEYE_RST_I, PWDN_N_I, DBG_S_I1, DBG_S_I2, DBG_S_I3, DATA_O1, DATA_O2, DATA_O3, DATA_O4, DATA_O5, DATA_O6
+, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24, DATA_O25, DATA_O26, DATA_O27
+, DATA_O28, DATA_O29, DATA_O30, DATA_O31, DATA_O32, DATA_O33, DATA_O34, DATA_O35, DATA_O36, DATA_O37, DATA_O38, DATA_O39, DATA_O40, DATA_O41, DATA_O42, DATA_O43, DATA_O44, DATA_O45, DATA_O46, DATA_O47, DATA_O48
+, DATA_O49, DATA_O50, DATA_O51, DATA_O52, DATA_O53, DATA_O54, DATA_O55, DATA_O56, DATA_O57, DATA_O58, DATA_O59, DATA_O60, DATA_O61, DATA_O62, DATA_O63, DATA_O64, CH_COM_O1, CH_COM_O2, CH_COM_O3, CH_COM_O4, CH_COM_O5
+, CH_COM_O6, CH_COM_O7, CH_COM_O8, CH_K_O1, CH_K_O2, CH_K_O3, CH_K_O4, CH_K_O5, CH_K_O6, CH_K_O7, CH_K_O8, NIT_O1, NIT_O2, NIT_O3, NIT_O4, NIT_O5, NIT_O6, NIT_O7, NIT_O8, D_ERR_O1, D_ERR_O2
+, D_ERR_O3, D_ERR_O4, D_ERR_O5, D_ERR_O6, D_ERR_O7, D_ERR_O8, CH_A_O1, CH_A_O2, CH_A_O3, CH_A_O4, CH_A_O5, CH_A_O6, CH_A_O7, CH_A_O8, CH_F_O1, CH_F_O2, CH_F_O3, CH_F_O4, CH_F_O5, CH_F_O6, CH_F_O7
+, CH_F_O8, ALIGN_O, VREALIGN_O, BUSY_O, TST_O1, TST_O2, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, LOS_O, LL_FLOCK_O, LL_SLOCK_O, PLL_LOCK_O, PLL_LOCKT_O, LINK);
+    input ALIGN_E_I;
+    output ALIGN_O;
+    input ALIGN_S_I;
+    input BUF_R_I;
+    output BUSY_O;
+    output CH_A_O1;
+    output CH_A_O2;
+    output CH_A_O3;
+    output CH_A_O4;
+    output CH_A_O5;
+    output CH_A_O6;
+    output CH_A_O7;
+    output CH_A_O8;
+    output CH_COM_O1;
+    output CH_COM_O2;
+    output CH_COM_O3;
+    output CH_COM_O4;
+    output CH_COM_O5;
+    output CH_COM_O6;
+    output CH_COM_O7;
+    output CH_COM_O8;
+    output CH_F_O1;
+    output CH_F_O2;
+    output CH_F_O3;
+    output CH_F_O4;
+    output CH_F_O5;
+    output CH_F_O6;
+    output CH_F_O7;
+    output CH_F_O8;
+    output CH_K_O1;
+    output CH_K_O2;
+    output CH_K_O3;
+    output CH_K_O4;
+    output CH_K_O5;
+    output CH_K_O6;
+    output CH_K_O7;
+    output CH_K_O8;
+    output DATA_O1;
+    output DATA_O10;
+    output DATA_O11;
+    output DATA_O12;
+    output DATA_O13;
+    output DATA_O14;
+    output DATA_O15;
+    output DATA_O16;
+    output DATA_O17;
+    output DATA_O18;
+    output DATA_O19;
+    output DATA_O2;
+    output DATA_O20;
+    output DATA_O21;
+    output DATA_O22;
+    output DATA_O23;
+    output DATA_O24;
+    output DATA_O25;
+    output DATA_O26;
+    output DATA_O27;
+    output DATA_O28;
+    output DATA_O29;
+    output DATA_O3;
+    output DATA_O30;
+    output DATA_O31;
+    output DATA_O32;
+    output DATA_O33;
+    output DATA_O34;
+    output DATA_O35;
+    output DATA_O36;
+    output DATA_O37;
+    output DATA_O38;
+    output DATA_O39;
+    output DATA_O4;
+    output DATA_O40;
+    output DATA_O41;
+    output DATA_O42;
+    output DATA_O43;
+    output DATA_O44;
+    output DATA_O45;
+    output DATA_O46;
+    output DATA_O47;
+    output DATA_O48;
+    output DATA_O49;
+    output DATA_O5;
+    output DATA_O50;
+    output DATA_O51;
+    output DATA_O52;
+    output DATA_O53;
+    output DATA_O54;
+    output DATA_O55;
+    output DATA_O56;
+    output DATA_O57;
+    output DATA_O58;
+    output DATA_O59;
+    output DATA_O6;
+    output DATA_O60;
+    output DATA_O61;
+    output DATA_O62;
+    output DATA_O63;
+    output DATA_O64;
+    output DATA_O7;
+    output DATA_O8;
+    output DATA_O9;
+    input DBG_S_I1;
+    input DBG_S_I2;
+    input DBG_S_I3;
+    input DEC_E_I;
+    input DSCR_E_I;
+    output D_ERR_O1;
+    output D_ERR_O2;
+    output D_ERR_O3;
+    output D_ERR_O4;
+    output D_ERR_O5;
+    output D_ERR_O6;
+    output D_ERR_O7;
+    output D_ERR_O8;
+    inout [9:0] LINK;
+    output LL_FLOCK_O;
+    output LL_SLOCK_O;
+    output LOS_O;
+    input MEYE_RST_I;
+    output NIT_O1;
+    output NIT_O2;
+    output NIT_O3;
+    output NIT_O4;
+    output NIT_O5;
+    output NIT_O6;
+    output NIT_O7;
+    output NIT_O8;
+    input OVS_BS_I1;
+    input OVS_BS_I2;
+    output PLL_LOCKT_O;
+    output PLL_LOCK_O;
+    input PMA_RSTN_I;
+    input PWDN_N_I;
+    input REP_E_I;
+    input RST_N_I;
+    output TST_O1;
+    output TST_O2;
+    output TST_O3;
+    output TST_O4;
+    output TST_O5;
+    output TST_O6;
+    output TST_O7;
+    output TST_O8;
+    output VREALIGN_O;
+    parameter gearbox_en = 1'b0;
+    parameter gearbox_mode = 1'b0;
+    parameter location = "";
+    parameter pcs_8b_dscr_sel = 1'b0;
+    parameter pcs_align_bypass = 1'b0;
+    parameter pcs_buffers_bypass = 1'b0;
+    parameter pcs_buffers_use_cdc = 1'b0;
+    parameter pcs_bypass_pma_cdc = 1'b0;
+    parameter pcs_bypass_usr_cdc = 1'b0;
+    parameter pcs_comma_mask = 10'b0000000000;
+    parameter pcs_debug_en = 1'b0;
+    parameter pcs_dec_bypass = 1'b0;
+    parameter pcs_dscr_bypass = 1'b0;
+    parameter pcs_el_buff_diff_bef_comp = 4'b0000;
+    parameter pcs_el_buff_max_comp = 4'b0000;
+    parameter pcs_el_buff_only_one_skp = 1'b0;
+    parameter pcs_el_buff_skp_char_0 = 9'b000000000;
+    parameter pcs_el_buff_skp_char_1 = 9'b000000000;
+    parameter pcs_el_buff_skp_char_2 = 9'b000000000;
+    parameter pcs_el_buff_skp_char_3 = 9'b000000000;
+    parameter pcs_el_buff_skp_header_0 = 9'b000000000;
+    parameter pcs_el_buff_skp_header_1 = 9'b000000000;
+    parameter pcs_el_buff_skp_header_2 = 9'b000000000;
+    parameter pcs_el_buff_skp_header_3 = 9'b000000000;
+    parameter pcs_el_buff_skp_header_size = 2'b00;
+    parameter pcs_el_buff_skp_seq_size = 2'b00;
+    parameter pcs_fsm_sel = 2'b00;
+    parameter pcs_fsm_watchdog_en = 1'b0;
+    parameter pcs_loopback = 1'b0;
+    parameter pcs_m_comma_en = 1'b0;
+    parameter pcs_m_comma_val = 10'b0000000000;
+    parameter pcs_nb_comma_bef_realign = 2'b00;
+    parameter pcs_p_comma_en = 1'b0;
+    parameter pcs_p_comma_val = 10'b0000000000;
+    parameter pcs_polarity = 1'b0;
+    parameter pcs_protocol_size = 1'b0;
+    parameter pcs_replace_bypass = 1'b0;
+    parameter pcs_sync_supported = 1'b0;
+    parameter pma_cdr_cp = 4'b0000;
+    parameter pma_clk_pos = 1'b0;
+    parameter pma_coarse_ppm = 3'b000;
+    parameter pma_ctrl_term = 6'b000000;
+    parameter pma_dco_divl = 2'b00;
+    parameter pma_dco_divm = 1'b0;
+    parameter pma_dco_divn = 2'b00;
+    parameter pma_dco_reg_res = 2'b00;
+    parameter pma_dco_vref_sel = 1'b0;
+    parameter pma_fine_ppm = 3'b000;
+    parameter pma_loopback = 1'b0;
+    parameter pma_m_eye_ppm = 3'b000;
+    parameter pma_peak_detect_cmd = 2'b00;
+    parameter pma_peak_detect_on = 1'b0;
+    parameter pma_pll_cpump_n = 3'b000;
+    parameter pma_pll_divf = 2'b00;
+    parameter pma_pll_divf_en_n = 1'b0;
+    parameter pma_pll_divm = 2'b00;
+    parameter pma_pll_divm_en_n = 1'b0;
+    parameter pma_pll_divn = 1'b0;
+    parameter pma_pll_divn_en_n = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_CTX_L(ENC_E_I1, ENC_E_I2, ENC_E_I3, ENC_E_I4, ENC_E_I5, ENC_E_I6, ENC_E_I7, ENC_E_I8, CH_K_I1, CH_K_I2, CH_K_I3, CH_K_I4, CH_K_I5, CH_K_I6, CH_K_I7, CH_K_I8, SCR_E_I1, SCR_E_I2, SCR_E_I3, SCR_E_I4, SCR_E_I5
+, SCR_E_I6, SCR_E_I7, SCR_E_I8, EOMF_I1, EOMF_I2, EOMF_I3, EOMF_I4, EOMF_I5, EOMF_I6, EOMF_I7, EOMF_I8, EOF_I1, EOF_I2, EOF_I3, EOF_I4, EOF_I5, EOF_I6, EOF_I7, EOF_I8, REP_E_I, RST_N_I
+, TST_I1, TST_I2, TST_I3, TST_I4, DATA_I1, DATA_I2, DATA_I3, DATA_I4, DATA_I5, DATA_I6, DATA_I7, DATA_I8, DATA_I9, DATA_I10, DATA_I11, DATA_I12, DATA_I13, DATA_I14, DATA_I15, DATA_I16, DATA_I17
+, DATA_I18, DATA_I19, DATA_I20, DATA_I21, DATA_I22, DATA_I23, DATA_I24, DATA_I25, DATA_I26, DATA_I27, DATA_I28, DATA_I29, DATA_I30, DATA_I31, DATA_I32, DATA_I33, DATA_I34, DATA_I35, DATA_I36, DATA_I37, DATA_I38
+, DATA_I39, DATA_I40, DATA_I41, DATA_I42, DATA_I43, DATA_I44, DATA_I45, DATA_I46, DATA_I47, DATA_I48, DATA_I49, DATA_I50, DATA_I51, DATA_I52, DATA_I53, DATA_I54, DATA_I55, DATA_I56, DATA_I57, DATA_I58, DATA_I59
+, DATA_I60, DATA_I61, DATA_I62, DATA_I63, DATA_I64, TST_O1, TST_O2, TST_O3, TST_O4, BUSY_O, CLK_E_I, TX_O, LINK);
+    output BUSY_O;
+    input CH_K_I1;
+    input CH_K_I2;
+    input CH_K_I3;
+    input CH_K_I4;
+    input CH_K_I5;
+    input CH_K_I6;
+    input CH_K_I7;
+    input CH_K_I8;
+    input CLK_E_I;
+    input DATA_I1;
+    input DATA_I10;
+    input DATA_I11;
+    input DATA_I12;
+    input DATA_I13;
+    input DATA_I14;
+    input DATA_I15;
+    input DATA_I16;
+    input DATA_I17;
+    input DATA_I18;
+    input DATA_I19;
+    input DATA_I2;
+    input DATA_I20;
+    input DATA_I21;
+    input DATA_I22;
+    input DATA_I23;
+    input DATA_I24;
+    input DATA_I25;
+    input DATA_I26;
+    input DATA_I27;
+    input DATA_I28;
+    input DATA_I29;
+    input DATA_I3;
+    input DATA_I30;
+    input DATA_I31;
+    input DATA_I32;
+    input DATA_I33;
+    input DATA_I34;
+    input DATA_I35;
+    input DATA_I36;
+    input DATA_I37;
+    input DATA_I38;
+    input DATA_I39;
+    input DATA_I4;
+    input DATA_I40;
+    input DATA_I41;
+    input DATA_I42;
+    input DATA_I43;
+    input DATA_I44;
+    input DATA_I45;
+    input DATA_I46;
+    input DATA_I47;
+    input DATA_I48;
+    input DATA_I49;
+    input DATA_I5;
+    input DATA_I50;
+    input DATA_I51;
+    input DATA_I52;
+    input DATA_I53;
+    input DATA_I54;
+    input DATA_I55;
+    input DATA_I56;
+    input DATA_I57;
+    input DATA_I58;
+    input DATA_I59;
+    input DATA_I6;
+    input DATA_I60;
+    input DATA_I61;
+    input DATA_I62;
+    input DATA_I63;
+    input DATA_I64;
+    input DATA_I7;
+    input DATA_I8;
+    input DATA_I9;
+    input ENC_E_I1;
+    input ENC_E_I2;
+    input ENC_E_I3;
+    input ENC_E_I4;
+    input ENC_E_I5;
+    input ENC_E_I6;
+    input ENC_E_I7;
+    input ENC_E_I8;
+    input EOF_I1;
+    input EOF_I2;
+    input EOF_I3;
+    input EOF_I4;
+    input EOF_I5;
+    input EOF_I6;
+    input EOF_I7;
+    input EOF_I8;
+    input EOMF_I1;
+    input EOMF_I2;
+    input EOMF_I3;
+    input EOMF_I4;
+    input EOMF_I5;
+    input EOMF_I6;
+    input EOMF_I7;
+    input EOMF_I8;
+    inout [19:0] LINK;
+    input REP_E_I;
+    input RST_N_I;
+    input SCR_E_I1;
+    input SCR_E_I2;
+    input SCR_E_I3;
+    input SCR_E_I4;
+    input SCR_E_I5;
+    input SCR_E_I6;
+    input SCR_E_I7;
+    input SCR_E_I8;
+    input TST_I1;
+    input TST_I2;
+    input TST_I3;
+    input TST_I4;
+    output TST_O1;
+    output TST_O2;
+    output TST_O3;
+    output TST_O4;
+    output TX_O;
+    parameter location = "";
+    parameter pcs_8b_scr_sel = 1'b0;
+    parameter pcs_bypass_pma_cdc = 1'b0;
+    parameter pcs_bypass_usr_cdc = 1'b0;
+    parameter pcs_enc_bypass = 1'b0;
+    parameter pcs_esistream_fsm_en = 1'b0;
+    parameter pcs_loopback = 1'b0;
+    parameter pcs_polarity = 1'b0;
+    parameter pcs_protocol_size = 1'b0;
+    parameter pcs_replace_bypass = 1'b0;
+    parameter pcs_scr_bypass = 1'b0;
+    parameter pcs_scr_init = 17'b00000000000000000;
+    parameter pcs_sync_supported = 1'b0;
+    parameter pma_clk_pos = 1'b0;
+    parameter pma_loopback = 1'b0;
+    parameter test = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_CTX_U(ENC_E_I1, ENC_E_I2, ENC_E_I3, ENC_E_I4, ENC_E_I5, ENC_E_I6, ENC_E_I7, ENC_E_I8, CH_K_I1, CH_K_I2, CH_K_I3, CH_K_I4, CH_K_I5, CH_K_I6, CH_K_I7, CH_K_I8, SCR_E_I1, SCR_E_I2, SCR_E_I3, SCR_E_I4, SCR_E_I5
+, SCR_E_I6, SCR_E_I7, SCR_E_I8, EOMF_I1, EOMF_I2, EOMF_I3, EOMF_I4, EOMF_I5, EOMF_I6, EOMF_I7, EOMF_I8, EOF_I1, EOF_I2, EOF_I3, EOF_I4, EOF_I5, EOF_I6, EOF_I7, EOF_I8, REP_E_I, RST_N_I
+, DATA_I1, DATA_I2, DATA_I3, DATA_I4, DATA_I5, DATA_I6, DATA_I7, DATA_I8, DATA_I9, DATA_I10, DATA_I11, DATA_I12, DATA_I13, DATA_I14, DATA_I15, DATA_I16, DATA_I17, DATA_I18, DATA_I19, DATA_I20, DATA_I21
+, DATA_I22, DATA_I23, DATA_I24, DATA_I25, DATA_I26, DATA_I27, DATA_I28, DATA_I29, DATA_I30, DATA_I31, DATA_I32, DATA_I33, DATA_I34, DATA_I35, DATA_I36, DATA_I37, DATA_I38, DATA_I39, DATA_I40, DATA_I41, DATA_I42
+, DATA_I43, DATA_I44, DATA_I45, DATA_I46, DATA_I47, DATA_I48, DATA_I49, DATA_I50, DATA_I51, DATA_I52, DATA_I53, DATA_I54, DATA_I55, DATA_I56, DATA_I57, DATA_I58, DATA_I59, DATA_I60, DATA_I61, DATA_I62, DATA_I63
+, DATA_I64, BUSY_O, INV_K_O, PWDN_N_I, CLK_E_I, CLK_O, LINK);
+    output BUSY_O;
+    input CH_K_I1;
+    input CH_K_I2;
+    input CH_K_I3;
+    input CH_K_I4;
+    input CH_K_I5;
+    input CH_K_I6;
+    input CH_K_I7;
+    input CH_K_I8;
+    input CLK_E_I;
+    output CLK_O;
+    input DATA_I1;
+    input DATA_I10;
+    input DATA_I11;
+    input DATA_I12;
+    input DATA_I13;
+    input DATA_I14;
+    input DATA_I15;
+    input DATA_I16;
+    input DATA_I17;
+    input DATA_I18;
+    input DATA_I19;
+    input DATA_I2;
+    input DATA_I20;
+    input DATA_I21;
+    input DATA_I22;
+    input DATA_I23;
+    input DATA_I24;
+    input DATA_I25;
+    input DATA_I26;
+    input DATA_I27;
+    input DATA_I28;
+    input DATA_I29;
+    input DATA_I3;
+    input DATA_I30;
+    input DATA_I31;
+    input DATA_I32;
+    input DATA_I33;
+    input DATA_I34;
+    input DATA_I35;
+    input DATA_I36;
+    input DATA_I37;
+    input DATA_I38;
+    input DATA_I39;
+    input DATA_I4;
+    input DATA_I40;
+    input DATA_I41;
+    input DATA_I42;
+    input DATA_I43;
+    input DATA_I44;
+    input DATA_I45;
+    input DATA_I46;
+    input DATA_I47;
+    input DATA_I48;
+    input DATA_I49;
+    input DATA_I5;
+    input DATA_I50;
+    input DATA_I51;
+    input DATA_I52;
+    input DATA_I53;
+    input DATA_I54;
+    input DATA_I55;
+    input DATA_I56;
+    input DATA_I57;
+    input DATA_I58;
+    input DATA_I59;
+    input DATA_I6;
+    input DATA_I60;
+    input DATA_I61;
+    input DATA_I62;
+    input DATA_I63;
+    input DATA_I64;
+    input DATA_I7;
+    input DATA_I8;
+    input DATA_I9;
+    input ENC_E_I1;
+    input ENC_E_I2;
+    input ENC_E_I3;
+    input ENC_E_I4;
+    input ENC_E_I5;
+    input ENC_E_I6;
+    input ENC_E_I7;
+    input ENC_E_I8;
+    input EOF_I1;
+    input EOF_I2;
+    input EOF_I3;
+    input EOF_I4;
+    input EOF_I5;
+    input EOF_I6;
+    input EOF_I7;
+    input EOF_I8;
+    input EOMF_I1;
+    input EOMF_I2;
+    input EOMF_I3;
+    input EOMF_I4;
+    input EOMF_I5;
+    input EOMF_I6;
+    input EOMF_I7;
+    input EOMF_I8;
+    output INV_K_O;
+    inout [19:0] LINK;
+    input PWDN_N_I;
+    input REP_E_I;
+    input RST_N_I;
+    input SCR_E_I1;
+    input SCR_E_I2;
+    input SCR_E_I3;
+    input SCR_E_I4;
+    input SCR_E_I5;
+    input SCR_E_I6;
+    input SCR_E_I7;
+    input SCR_E_I8;
+    parameter gearbox_en = 1'b0;
+    parameter gearbox_mode = 1'b0;
+    parameter location = "";
+    parameter pcs_8b_scr_sel = 1'b0;
+    parameter pcs_bypass_pma_cdc = 1'b0;
+    parameter pcs_bypass_usr_cdc = 1'b0;
+    parameter pcs_enc_bypass = 1'b0;
+    parameter pcs_esistream_fsm_en = 1'b0;
+    parameter pcs_loopback = 1'b0;
+    parameter pcs_polarity = 1'b0;
+    parameter pcs_protocol_size = 1'b0;
+    parameter pcs_replace_bypass = 1'b0;
+    parameter pcs_scr_bypass = 1'b0;
+    parameter pcs_scr_init = 17'b00000000000000000;
+    parameter pcs_sync_supported = 1'b0;
+    parameter pma_clk_pos = 1'b0;
+    parameter pma_loopback = 1'b0;
+endmodule
+
+//(* blackbox *)
+//module NX_CY(A1, A2, A3, A4, B1, B2, B3, B4, CI, CO, S1, S2, S3, S4);
+//    input A1;
+//    input A2;
+//    input A3;
+//    input A4;
+//    input B1;
+//    input B2;
+//    input B3;
+//    input B4;
+//    input CI;
+//    output CO;
+//    output S1;
+//    output S2;
+//    output S3;
+//    output S4;
+//    parameter add_carry = 0;
+//endmodule
+
+(* blackbox *)
+module NX_DES(FCK, SCK, R, IO, DCK, DRL, DIG, FZ, FLD, FLG, O, DS, DRA, DRI, DRO, DID);
+    input DCK;
+    output [5:0] DID;
+    input DIG;
+    input [5:0] DRA;
+    input [5:0] DRI;
+    input DRL;
+    output [5:0] DRO;
+    input [1:0] DS;
+    input FCK;
+    output FLD;
+    output FLG;
+    input FZ;
+    input IO;
+    output [4:0] O;
+    input R;
+    input SCK;
+    parameter data_size = 5;
+    parameter differential = "";
+    parameter dpath_dynamic = 1'b0;
+    parameter drive = "";
+    parameter inputDelayLine = "";
+    parameter inputSignalSlope = "";
+    parameter location = "";
+    parameter locked = 1'b0;
+    parameter standard = "";
+    parameter termination = "";
+    parameter terminationReference = "";
+    parameter turbo = "";
+    parameter weakTermination = "";
+endmodule
+
+//(* blackbox *)
+//module NX_DFF(I, CK, L, R, O);
+//    input CK;
+//    input I;
+//    input L;
+//    output O;
+//    input R;
+//    parameter dff_ctxt = 1'b0;
+//    parameter dff_edge = 1'b0;
+//    parameter dff_init = 1'b0;
+//    parameter dff_load = 1'b0;
+//    parameter dff_sync = 1'b0;
+//    parameter dff_type = 1'b0;
+//endmodule
+
+(* blackbox *)
+module NX_DFR(I, CK, L, R, O);
+    input CK;
+    input I;
+    input L;
+    output O;
+    input R;
+    parameter data_inv = 1'b0;
+    parameter dff_edge = 1'b0;
+    parameter dff_init = 1'b0;
+    parameter dff_load = 1'b0;
+    parameter dff_sync = 1'b0;
+    parameter dff_type = 1'b0;
+    parameter iobname = "";
+    parameter location = "";
+    parameter mode = 0;
+    parameter path = 0;
+    parameter ring = 0;
+endmodule
+
+(* blackbox *)
+module NX_DSP(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21
+, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18
+, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21
+, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6
+, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAO1, CAO2, CAO3, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9
+, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12
+, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15
+, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO, CO37, CO49, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11
+, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32
+, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53
+, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18
+, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39
+, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4
+, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, OVF, R, RZ, WE, Z1, Z2, Z3
+, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24
+, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45
+, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53, Z54, Z55, Z56);
+    input A1;
+    input A10;
+    input A11;
+    input A12;
+    input A13;
+    input A14;
+    input A15;
+    input A16;
+    input A17;
+    input A18;
+    input A19;
+    input A2;
+    input A20;
+    input A21;
+    input A22;
+    input A23;
+    input A24;
+    input A3;
+    input A4;
+    input A5;
+    input A6;
+    input A7;
+    input A8;
+    input A9;
+    input B1;
+    input B10;
+    input B11;
+    input B12;
+    input B13;
+    input B14;
+    input B15;
+    input B16;
+    input B17;
+    input B18;
+    input B2;
+    input B3;
+    input B4;
+    input B5;
+    input B6;
+    input B7;
+    input B8;
+    input B9;
+    input C1;
+    input C10;
+    input C11;
+    input C12;
+    input C13;
+    input C14;
+    input C15;
+    input C16;
+    input C17;
+    input C18;
+    input C19;
+    input C2;
+    input C20;
+    input C21;
+    input C22;
+    input C23;
+    input C24;
+    input C25;
+    input C26;
+    input C27;
+    input C28;
+    input C29;
+    input C3;
+    input C30;
+    input C31;
+    input C32;
+    input C33;
+    input C34;
+    input C35;
+    input C36;
+    input C4;
+    input C5;
+    input C6;
+    input C7;
+    input C8;
+    input C9;
+    input CAI1;
+    input CAI10;
+    input CAI11;
+    input CAI12;
+    input CAI13;
+    input CAI14;
+    input CAI15;
+    input CAI16;
+    input CAI17;
+    input CAI18;
+    input CAI2;
+    input CAI3;
+    input CAI4;
+    input CAI5;
+    input CAI6;
+    input CAI7;
+    input CAI8;
+    input CAI9;
+    output CAO1;
+    output CAO10;
+    output CAO11;
+    output CAO12;
+    output CAO13;
+    output CAO14;
+    output CAO15;
+    output CAO16;
+    output CAO17;
+    output CAO18;
+    output CAO2;
+    output CAO3;
+    output CAO4;
+    output CAO5;
+    output CAO6;
+    output CAO7;
+    output CAO8;
+    output CAO9;
+    input CBI1;
+    input CBI10;
+    input CBI11;
+    input CBI12;
+    input CBI13;
+    input CBI14;
+    input CBI15;
+    input CBI16;
+    input CBI17;
+    input CBI18;
+    input CBI2;
+    input CBI3;
+    input CBI4;
+    input CBI5;
+    input CBI6;
+    input CBI7;
+    input CBI8;
+    input CBI9;
+    output CBO1;
+    output CBO10;
+    output CBO11;
+    output CBO12;
+    output CBO13;
+    output CBO14;
+    output CBO15;
+    output CBO16;
+    output CBO17;
+    output CBO18;
+    output CBO2;
+    output CBO3;
+    output CBO4;
+    output CBO5;
+    output CBO6;
+    output CBO7;
+    output CBO8;
+    output CBO9;
+    input CCI;
+    output CCO;
+    input CI;
+    input CK;
+    output CO;
+    output CO37;
+    output CO49;
+    input CZI1;
+    input CZI10;
+    input CZI11;
+    input CZI12;
+    input CZI13;
+    input CZI14;
+    input CZI15;
+    input CZI16;
+    input CZI17;
+    input CZI18;
+    input CZI19;
+    input CZI2;
+    input CZI20;
+    input CZI21;
+    input CZI22;
+    input CZI23;
+    input CZI24;
+    input CZI25;
+    input CZI26;
+    input CZI27;
+    input CZI28;
+    input CZI29;
+    input CZI3;
+    input CZI30;
+    input CZI31;
+    input CZI32;
+    input CZI33;
+    input CZI34;
+    input CZI35;
+    input CZI36;
+    input CZI37;
+    input CZI38;
+    input CZI39;
+    input CZI4;
+    input CZI40;
+    input CZI41;
+    input CZI42;
+    input CZI43;
+    input CZI44;
+    input CZI45;
+    input CZI46;
+    input CZI47;
+    input CZI48;
+    input CZI49;
+    input CZI5;
+    input CZI50;
+    input CZI51;
+    input CZI52;
+    input CZI53;
+    input CZI54;
+    input CZI55;
+    input CZI56;
+    input CZI6;
+    input CZI7;
+    input CZI8;
+    input CZI9;
+    output CZO1;
+    output CZO10;
+    output CZO11;
+    output CZO12;
+    output CZO13;
+    output CZO14;
+    output CZO15;
+    output CZO16;
+    output CZO17;
+    output CZO18;
+    output CZO19;
+    output CZO2;
+    output CZO20;
+    output CZO21;
+    output CZO22;
+    output CZO23;
+    output CZO24;
+    output CZO25;
+    output CZO26;
+    output CZO27;
+    output CZO28;
+    output CZO29;
+    output CZO3;
+    output CZO30;
+    output CZO31;
+    output CZO32;
+    output CZO33;
+    output CZO34;
+    output CZO35;
+    output CZO36;
+    output CZO37;
+    output CZO38;
+    output CZO39;
+    output CZO4;
+    output CZO40;
+    output CZO41;
+    output CZO42;
+    output CZO43;
+    output CZO44;
+    output CZO45;
+    output CZO46;
+    output CZO47;
+    output CZO48;
+    output CZO49;
+    output CZO5;
+    output CZO50;
+    output CZO51;
+    output CZO52;
+    output CZO53;
+    output CZO54;
+    output CZO55;
+    output CZO56;
+    output CZO6;
+    output CZO7;
+    output CZO8;
+    output CZO9;
+    input D1;
+    input D10;
+    input D11;
+    input D12;
+    input D13;
+    input D14;
+    input D15;
+    input D16;
+    input D17;
+    input D18;
+    input D2;
+    input D3;
+    input D4;
+    input D5;
+    input D6;
+    input D7;
+    input D8;
+    input D9;
+    output OVF;
+    input R;
+    input RZ;
+    input WE;
+    output Z1;
+    output Z10;
+    output Z11;
+    output Z12;
+    output Z13;
+    output Z14;
+    output Z15;
+    output Z16;
+    output Z17;
+    output Z18;
+    output Z19;
+    output Z2;
+    output Z20;
+    output Z21;
+    output Z22;
+    output Z23;
+    output Z24;
+    output Z25;
+    output Z26;
+    output Z27;
+    output Z28;
+    output Z29;
+    output Z3;
+    output Z30;
+    output Z31;
+    output Z32;
+    output Z33;
+    output Z34;
+    output Z35;
+    output Z36;
+    output Z37;
+    output Z38;
+    output Z39;
+    output Z4;
+    output Z40;
+    output Z41;
+    output Z42;
+    output Z43;
+    output Z44;
+    output Z45;
+    output Z46;
+    output Z47;
+    output Z48;
+    output Z49;
+    output Z5;
+    output Z50;
+    output Z51;
+    output Z52;
+    output Z53;
+    output Z54;
+    output Z55;
+    output Z56;
+    output Z6;
+    output Z7;
+    output Z8;
+    output Z9;
+    parameter raw_config0 = 20'b00000000000000000000;
+    parameter raw_config1 = 19'b0000000000000000000;
+    parameter raw_config2 = 13'b0000000000000;
+    parameter raw_config3 = 7'b0000000;
+    parameter std_mode = "";
+endmodule
+
+(* blackbox *)
+module NX_DSP_L(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21
+, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18
+, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21
+, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6
+, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAI19, CAI20, CAI21, CAI22, CAI23, CAI24, CAO1, CAO2, CAO3
+, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CAO19, CAO20, CAO21, CAO22, CAO23, CAO24
+, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3
+, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO, CO37
+, CO57, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20
+, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41
+, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6
+, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27
+, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48
+, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13
+, D14, D15, D16, D17, D18, OVF, R, RZ, WE, Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11, Z12
+, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32, Z33
+, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53, Z54
+, Z55, Z56);
+    input A1;
+    input A10;
+    input A11;
+    input A12;
+    input A13;
+    input A14;
+    input A15;
+    input A16;
+    input A17;
+    input A18;
+    input A19;
+    input A2;
+    input A20;
+    input A21;
+    input A22;
+    input A23;
+    input A24;
+    input A3;
+    input A4;
+    input A5;
+    input A6;
+    input A7;
+    input A8;
+    input A9;
+    input B1;
+    input B10;
+    input B11;
+    input B12;
+    input B13;
+    input B14;
+    input B15;
+    input B16;
+    input B17;
+    input B18;
+    input B2;
+    input B3;
+    input B4;
+    input B5;
+    input B6;
+    input B7;
+    input B8;
+    input B9;
+    input C1;
+    input C10;
+    input C11;
+    input C12;
+    input C13;
+    input C14;
+    input C15;
+    input C16;
+    input C17;
+    input C18;
+    input C19;
+    input C2;
+    input C20;
+    input C21;
+    input C22;
+    input C23;
+    input C24;
+    input C25;
+    input C26;
+    input C27;
+    input C28;
+    input C29;
+    input C3;
+    input C30;
+    input C31;
+    input C32;
+    input C33;
+    input C34;
+    input C35;
+    input C36;
+    input C4;
+    input C5;
+    input C6;
+    input C7;
+    input C8;
+    input C9;
+    input CAI1;
+    input CAI10;
+    input CAI11;
+    input CAI12;
+    input CAI13;
+    input CAI14;
+    input CAI15;
+    input CAI16;
+    input CAI17;
+    input CAI18;
+    input CAI19;
+    input CAI2;
+    input CAI20;
+    input CAI21;
+    input CAI22;
+    input CAI23;
+    input CAI24;
+    input CAI3;
+    input CAI4;
+    input CAI5;
+    input CAI6;
+    input CAI7;
+    input CAI8;
+    input CAI9;
+    output CAO1;
+    output CAO10;
+    output CAO11;
+    output CAO12;
+    output CAO13;
+    output CAO14;
+    output CAO15;
+    output CAO16;
+    output CAO17;
+    output CAO18;
+    output CAO19;
+    output CAO2;
+    output CAO20;
+    output CAO21;
+    output CAO22;
+    output CAO23;
+    output CAO24;
+    output CAO3;
+    output CAO4;
+    output CAO5;
+    output CAO6;
+    output CAO7;
+    output CAO8;
+    output CAO9;
+    input CBI1;
+    input CBI10;
+    input CBI11;
+    input CBI12;
+    input CBI13;
+    input CBI14;
+    input CBI15;
+    input CBI16;
+    input CBI17;
+    input CBI18;
+    input CBI2;
+    input CBI3;
+    input CBI4;
+    input CBI5;
+    input CBI6;
+    input CBI7;
+    input CBI8;
+    input CBI9;
+    output CBO1;
+    output CBO10;
+    output CBO11;
+    output CBO12;
+    output CBO13;
+    output CBO14;
+    output CBO15;
+    output CBO16;
+    output CBO17;
+    output CBO18;
+    output CBO2;
+    output CBO3;
+    output CBO4;
+    output CBO5;
+    output CBO6;
+    output CBO7;
+    output CBO8;
+    output CBO9;
+    input CCI;
+    output CCO;
+    input CI;
+    input CK;
+    output CO;
+    output CO37;
+    output CO57;
+    input CZI1;
+    input CZI10;
+    input CZI11;
+    input CZI12;
+    input CZI13;
+    input CZI14;
+    input CZI15;
+    input CZI16;
+    input CZI17;
+    input CZI18;
+    input CZI19;
+    input CZI2;
+    input CZI20;
+    input CZI21;
+    input CZI22;
+    input CZI23;
+    input CZI24;
+    input CZI25;
+    input CZI26;
+    input CZI27;
+    input CZI28;
+    input CZI29;
+    input CZI3;
+    input CZI30;
+    input CZI31;
+    input CZI32;
+    input CZI33;
+    input CZI34;
+    input CZI35;
+    input CZI36;
+    input CZI37;
+    input CZI38;
+    input CZI39;
+    input CZI4;
+    input CZI40;
+    input CZI41;
+    input CZI42;
+    input CZI43;
+    input CZI44;
+    input CZI45;
+    input CZI46;
+    input CZI47;
+    input CZI48;
+    input CZI49;
+    input CZI5;
+    input CZI50;
+    input CZI51;
+    input CZI52;
+    input CZI53;
+    input CZI54;
+    input CZI55;
+    input CZI56;
+    input CZI6;
+    input CZI7;
+    input CZI8;
+    input CZI9;
+    output CZO1;
+    output CZO10;
+    output CZO11;
+    output CZO12;
+    output CZO13;
+    output CZO14;
+    output CZO15;
+    output CZO16;
+    output CZO17;
+    output CZO18;
+    output CZO19;
+    output CZO2;
+    output CZO20;
+    output CZO21;
+    output CZO22;
+    output CZO23;
+    output CZO24;
+    output CZO25;
+    output CZO26;
+    output CZO27;
+    output CZO28;
+    output CZO29;
+    output CZO3;
+    output CZO30;
+    output CZO31;
+    output CZO32;
+    output CZO33;
+    output CZO34;
+    output CZO35;
+    output CZO36;
+    output CZO37;
+    output CZO38;
+    output CZO39;
+    output CZO4;
+    output CZO40;
+    output CZO41;
+    output CZO42;
+    output CZO43;
+    output CZO44;
+    output CZO45;
+    output CZO46;
+    output CZO47;
+    output CZO48;
+    output CZO49;
+    output CZO5;
+    output CZO50;
+    output CZO51;
+    output CZO52;
+    output CZO53;
+    output CZO54;
+    output CZO55;
+    output CZO56;
+    output CZO6;
+    output CZO7;
+    output CZO8;
+    output CZO9;
+    input D1;
+    input D10;
+    input D11;
+    input D12;
+    input D13;
+    input D14;
+    input D15;
+    input D16;
+    input D17;
+    input D18;
+    input D2;
+    input D3;
+    input D4;
+    input D5;
+    input D6;
+    input D7;
+    input D8;
+    input D9;
+    output OVF;
+    input R;
+    input RZ;
+    input WE;
+    output Z1;
+    output Z10;
+    output Z11;
+    output Z12;
+    output Z13;
+    output Z14;
+    output Z15;
+    output Z16;
+    output Z17;
+    output Z18;
+    output Z19;
+    output Z2;
+    output Z20;
+    output Z21;
+    output Z22;
+    output Z23;
+    output Z24;
+    output Z25;
+    output Z26;
+    output Z27;
+    output Z28;
+    output Z29;
+    output Z3;
+    output Z30;
+    output Z31;
+    output Z32;
+    output Z33;
+    output Z34;
+    output Z35;
+    output Z36;
+    output Z37;
+    output Z38;
+    output Z39;
+    output Z4;
+    output Z40;
+    output Z41;
+    output Z42;
+    output Z43;
+    output Z44;
+    output Z45;
+    output Z46;
+    output Z47;
+    output Z48;
+    output Z49;
+    output Z5;
+    output Z50;
+    output Z51;
+    output Z52;
+    output Z53;
+    output Z54;
+    output Z55;
+    output Z56;
+    output Z6;
+    output Z7;
+    output Z8;
+    output Z9;
+    parameter raw_config0 = 20'b00000000000000000000;
+    parameter raw_config1 = 19'b0000000000000000000;
+    parameter raw_config2 = 13'b0000000000000;
+    parameter raw_config3 = 7'b0000000;
+    parameter std_mode = "";
+endmodule
+
+(* blackbox *)
+module NX_DSP_L_SPLIT(CK, R, RZ, WE, CI, CCI, CO, CO36, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
+, CZO);
+    input [23:0] A;
+    input [17:0] B;
+    input [35:0] C;
+    input [23:0] CAI;
+    output [23:0] CAO;
+    input [17:0] CBI;
+    output [17:0] CBO;
+    input CCI;
+    output CCO;
+    input CI;
+    input CK;
+    output CO;
+    output CO36;
+    output CO56;
+    input [55:0] CZI;
+    output [55:0] CZO;
+    input [17:0] D;
+    output OVF;
+    input R;
+    input RZ;
+    input WE;
+    output [55:0] Z;
+    parameter ALU_DYNAMIC_OP = 1'b0;
+    parameter ALU_MUX = 1'b0;
+    parameter ALU_OP = 6'b000000;
+    parameter CO_SEL = 1'b0;
+    parameter ENABLE_PR_ALU_RST = 1'b0;
+    parameter ENABLE_PR_A_RST = 1'b0;
+    parameter ENABLE_PR_B_RST = 1'b0;
+    parameter ENABLE_PR_CI_RST = 1'b0;
+    parameter ENABLE_PR_CO_RST = 1'b0;
+    parameter ENABLE_PR_C_RST = 1'b0;
+    parameter ENABLE_PR_D_RST = 1'b0;
+    parameter ENABLE_PR_MULT_RST = 1'b0;
+    parameter ENABLE_PR_OV_RST = 1'b0;
+    parameter ENABLE_PR_P_RST = 1'b0;
+    parameter ENABLE_PR_X_RST = 1'b0;
+    parameter ENABLE_PR_Y_RST = 1'b0;
+    parameter ENABLE_PR_Z_RST = 1'b0;
+    parameter ENABLE_SATURATION = 1'b0;
+    parameter MUX_A = 1'b0;
+    parameter MUX_B = 1'b0;
+    parameter MUX_CI = 1'b0;
+    parameter MUX_P = 1'b0;
+    parameter MUX_X = 2'b00;
+    parameter MUX_Y = 1'b0;
+    parameter MUX_Z = 1'b0;
+    parameter PRE_ADDER_OP = 1'b0;
+    parameter PR_ALU_MUX = 1'b0;
+    parameter PR_A_CASCADE_MUX = 2'b00;
+    parameter PR_A_MUX = 2'b00;
+    parameter PR_B_CASCADE_MUX = 2'b00;
+    parameter PR_B_MUX = 2'b00;
+    parameter PR_CI_MUX = 1'b0;
+    parameter PR_CO_MUX = 1'b0;
+    parameter PR_C_MUX = 1'b0;
+    parameter PR_D_MUX = 1'b0;
+    parameter PR_MULT_MUX = 1'b0;
+    parameter PR_OV_MUX = 1'b0;
+    parameter PR_P_MUX = 1'b0;
+    parameter PR_X_MUX = 1'b0;
+    parameter PR_Y_MUX = 1'b0;
+    parameter PR_Z_MUX = 1'b0;
+    parameter SATURATION_RANK = 6'b000000;
+    parameter SIGNED_MODE = 1'b0;
+    parameter Z_FEEDBACK_SHL12 = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_DSP_L_WRAP(CCI, CCO, CI, CK, CO, CO37, CO57, OVF, R, RZ, WE, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
+, CZO);
+    input [23:0] A;
+    input [17:0] B;
+    input [35:0] C;
+    input [23:0] CAI;
+    output [23:0] CAO;
+    input [17:0] CBI;
+    output [17:0] CBO;
+    input CCI;
+    output CCO;
+    input CI;
+    input CK;
+    output CO;
+    output CO37;
+    output CO57;
+    input [55:0] CZI;
+    output [55:0] CZO;
+    input [17:0] D;
+    output OVF;
+    input R;
+    input RZ;
+    input WE;
+    output [55:0] Z;
+    parameter raw_config0 = 20'b00000000000000000000;
+    parameter raw_config1 = 19'b0000000000000000000;
+    parameter raw_config2 = 13'b0000000000000;
+    parameter raw_config3 = 7'b0000000;
+    parameter std_mode = "";
+endmodule
+
+(* blackbox *)
+module NX_DSP_SPLIT(CK, R, RZ, WE, CI, CCI, CO, CO36, CO48, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
+, CZO);
+    input [23:0] A;
+    input [17:0] B;
+    input [35:0] C;
+    input [17:0] CAI;
+    output [17:0] CAO;
+    input [17:0] CBI;
+    output [17:0] CBO;
+    input CCI;
+    output CCO;
+    input CI;
+    input CK;
+    output CO;
+    output CO36;
+    output CO48;
+    input [55:0] CZI;
+    output [55:0] CZO;
+    input [17:0] D;
+    output OVF;
+    input R;
+    input RZ;
+    input WE;
+    output [55:0] Z;
+    parameter ALU_DYNAMIC_OP = 1'b0;
+    parameter ALU_MUX = 1'b0;
+    parameter ALU_OP = 6'b000000;
+    parameter CO_SEL = 1'b0;
+    parameter ENABLE_PR_ALU_RST = 1'b0;
+    parameter ENABLE_PR_A_RST = 1'b0;
+    parameter ENABLE_PR_B_RST = 1'b0;
+    parameter ENABLE_PR_CI_RST = 1'b0;
+    parameter ENABLE_PR_CO_RST = 1'b0;
+    parameter ENABLE_PR_C_RST = 1'b0;
+    parameter ENABLE_PR_D_RST = 1'b0;
+    parameter ENABLE_PR_MULT_RST = 1'b0;
+    parameter ENABLE_PR_OV_RST = 1'b0;
+    parameter ENABLE_PR_P_RST = 1'b0;
+    parameter ENABLE_PR_X_RST = 1'b0;
+    parameter ENABLE_PR_Y_RST = 1'b0;
+    parameter ENABLE_PR_Z_RST = 1'b0;
+    parameter ENABLE_SATURATION = 1'b0;
+    parameter MUX_A = 1'b0;
+    parameter MUX_B = 1'b0;
+    parameter MUX_CI = 1'b0;
+    parameter MUX_P = 1'b0;
+    parameter MUX_X = 2'b00;
+    parameter MUX_Y = 1'b0;
+    parameter MUX_Z = 1'b0;
+    parameter PRE_ADDER_OP = 1'b0;
+    parameter PR_ALU_MUX = 1'b0;
+    parameter PR_A_CASCADE_MUX = 2'b00;
+    parameter PR_A_MUX = 2'b00;
+    parameter PR_B_CASCADE_MUX = 2'b00;
+    parameter PR_B_MUX = 2'b00;
+    parameter PR_CI_MUX = 1'b0;
+    parameter PR_CO_MUX = 1'b0;
+    parameter PR_C_MUX = 1'b0;
+    parameter PR_D_MUX = 1'b0;
+    parameter PR_MULT_MUX = 1'b0;
+    parameter PR_OV_MUX = 1'b0;
+    parameter PR_P_MUX = 1'b0;
+    parameter PR_X_MUX = 1'b0;
+    parameter PR_Y_MUX = 1'b0;
+    parameter PR_Z_MUX = 1'b0;
+    parameter SATURATION_RANK = 6'b000000;
+    parameter SIGNED_MODE = 1'b0;
+    parameter Z_FEEDBACK_SHL12 = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_DSP_U(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21
+, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18
+, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21
+, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6
+, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAI19, CAI20, CAI21, CAI22, CAI23, CAI24, CAO1, CAO2, CAO3
+, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CAO19, CAO20, CAO21, CAO22, CAO23, CAO24
+, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3
+, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO43, CO57
+, RESERVED, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20
+, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41
+, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6
+, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27
+, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48
+, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13
+, D14, D15, D16, D17, D18, OVF, R, RZ, WE, WEZ, Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11
+, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32
+, Z33, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53
+, Z54, Z55, Z56);
+    input A1;
+    input A10;
+    input A11;
+    input A12;
+    input A13;
+    input A14;
+    input A15;
+    input A16;
+    input A17;
+    input A18;
+    input A19;
+    input A2;
+    input A20;
+    input A21;
+    input A22;
+    input A23;
+    input A24;
+    input A3;
+    input A4;
+    input A5;
+    input A6;
+    input A7;
+    input A8;
+    input A9;
+    input B1;
+    input B10;
+    input B11;
+    input B12;
+    input B13;
+    input B14;
+    input B15;
+    input B16;
+    input B17;
+    input B18;
+    input B2;
+    input B3;
+    input B4;
+    input B5;
+    input B6;
+    input B7;
+    input B8;
+    input B9;
+    input C1;
+    input C10;
+    input C11;
+    input C12;
+    input C13;
+    input C14;
+    input C15;
+    input C16;
+    input C17;
+    input C18;
+    input C19;
+    input C2;
+    input C20;
+    input C21;
+    input C22;
+    input C23;
+    input C24;
+    input C25;
+    input C26;
+    input C27;
+    input C28;
+    input C29;
+    input C3;
+    input C30;
+    input C31;
+    input C32;
+    input C33;
+    input C34;
+    input C35;
+    input C36;
+    input C4;
+    input C5;
+    input C6;
+    input C7;
+    input C8;
+    input C9;
+    input CAI1;
+    input CAI10;
+    input CAI11;
+    input CAI12;
+    input CAI13;
+    input CAI14;
+    input CAI15;
+    input CAI16;
+    input CAI17;
+    input CAI18;
+    input CAI19;
+    input CAI2;
+    input CAI20;
+    input CAI21;
+    input CAI22;
+    input CAI23;
+    input CAI24;
+    input CAI3;
+    input CAI4;
+    input CAI5;
+    input CAI6;
+    input CAI7;
+    input CAI8;
+    input CAI9;
+    output CAO1;
+    output CAO10;
+    output CAO11;
+    output CAO12;
+    output CAO13;
+    output CAO14;
+    output CAO15;
+    output CAO16;
+    output CAO17;
+    output CAO18;
+    output CAO19;
+    output CAO2;
+    output CAO20;
+    output CAO21;
+    output CAO22;
+    output CAO23;
+    output CAO24;
+    output CAO3;
+    output CAO4;
+    output CAO5;
+    output CAO6;
+    output CAO7;
+    output CAO8;
+    output CAO9;
+    input CBI1;
+    input CBI10;
+    input CBI11;
+    input CBI12;
+    input CBI13;
+    input CBI14;
+    input CBI15;
+    input CBI16;
+    input CBI17;
+    input CBI18;
+    input CBI2;
+    input CBI3;
+    input CBI4;
+    input CBI5;
+    input CBI6;
+    input CBI7;
+    input CBI8;
+    input CBI9;
+    output CBO1;
+    output CBO10;
+    output CBO11;
+    output CBO12;
+    output CBO13;
+    output CBO14;
+    output CBO15;
+    output CBO16;
+    output CBO17;
+    output CBO18;
+    output CBO2;
+    output CBO3;
+    output CBO4;
+    output CBO5;
+    output CBO6;
+    output CBO7;
+    output CBO8;
+    output CBO9;
+    input CCI;
+    output CCO;
+    input CI;
+    input CK;
+    output CO43;
+    output CO57;
+    input CZI1;
+    input CZI10;
+    input CZI11;
+    input CZI12;
+    input CZI13;
+    input CZI14;
+    input CZI15;
+    input CZI16;
+    input CZI17;
+    input CZI18;
+    input CZI19;
+    input CZI2;
+    input CZI20;
+    input CZI21;
+    input CZI22;
+    input CZI23;
+    input CZI24;
+    input CZI25;
+    input CZI26;
+    input CZI27;
+    input CZI28;
+    input CZI29;
+    input CZI3;
+    input CZI30;
+    input CZI31;
+    input CZI32;
+    input CZI33;
+    input CZI34;
+    input CZI35;
+    input CZI36;
+    input CZI37;
+    input CZI38;
+    input CZI39;
+    input CZI4;
+    input CZI40;
+    input CZI41;
+    input CZI42;
+    input CZI43;
+    input CZI44;
+    input CZI45;
+    input CZI46;
+    input CZI47;
+    input CZI48;
+    input CZI49;
+    input CZI5;
+    input CZI50;
+    input CZI51;
+    input CZI52;
+    input CZI53;
+    input CZI54;
+    input CZI55;
+    input CZI56;
+    input CZI6;
+    input CZI7;
+    input CZI8;
+    input CZI9;
+    output CZO1;
+    output CZO10;
+    output CZO11;
+    output CZO12;
+    output CZO13;
+    output CZO14;
+    output CZO15;
+    output CZO16;
+    output CZO17;
+    output CZO18;
+    output CZO19;
+    output CZO2;
+    output CZO20;
+    output CZO21;
+    output CZO22;
+    output CZO23;
+    output CZO24;
+    output CZO25;
+    output CZO26;
+    output CZO27;
+    output CZO28;
+    output CZO29;
+    output CZO3;
+    output CZO30;
+    output CZO31;
+    output CZO32;
+    output CZO33;
+    output CZO34;
+    output CZO35;
+    output CZO36;
+    output CZO37;
+    output CZO38;
+    output CZO39;
+    output CZO4;
+    output CZO40;
+    output CZO41;
+    output CZO42;
+    output CZO43;
+    output CZO44;
+    output CZO45;
+    output CZO46;
+    output CZO47;
+    output CZO48;
+    output CZO49;
+    output CZO5;
+    output CZO50;
+    output CZO51;
+    output CZO52;
+    output CZO53;
+    output CZO54;
+    output CZO55;
+    output CZO56;
+    output CZO6;
+    output CZO7;
+    output CZO8;
+    output CZO9;
+    input D1;
+    input D10;
+    input D11;
+    input D12;
+    input D13;
+    input D14;
+    input D15;
+    input D16;
+    input D17;
+    input D18;
+    input D2;
+    input D3;
+    input D4;
+    input D5;
+    input D6;
+    input D7;
+    input D8;
+    input D9;
+    output OVF;
+    input R;
+    output RESERVED;
+    input RZ;
+    input WE;
+    input WEZ;
+    output Z1;
+    output Z10;
+    output Z11;
+    output Z12;
+    output Z13;
+    output Z14;
+    output Z15;
+    output Z16;
+    output Z17;
+    output Z18;
+    output Z19;
+    output Z2;
+    output Z20;
+    output Z21;
+    output Z22;
+    output Z23;
+    output Z24;
+    output Z25;
+    output Z26;
+    output Z27;
+    output Z28;
+    output Z29;
+    output Z3;
+    output Z30;
+    output Z31;
+    output Z32;
+    output Z33;
+    output Z34;
+    output Z35;
+    output Z36;
+    output Z37;
+    output Z38;
+    output Z39;
+    output Z4;
+    output Z40;
+    output Z41;
+    output Z42;
+    output Z43;
+    output Z44;
+    output Z45;
+    output Z46;
+    output Z47;
+    output Z48;
+    output Z49;
+    output Z5;
+    output Z50;
+    output Z51;
+    output Z52;
+    output Z53;
+    output Z54;
+    output Z55;
+    output Z56;
+    output Z6;
+    output Z7;
+    output Z8;
+    output Z9;
+    parameter raw_config0 = 27'b000000000000000000000000000;
+    parameter raw_config1 = 24'b000000000000000000000000;
+    parameter raw_config2 = 14'b00000000000000;
+    parameter raw_config3 = 3'b000;
+    parameter std_mode = "";
+endmodule
+
+(* blackbox *)
+module NX_DSP_U_SPLIT(CK, R, RZ, WE, WEZ, CI, CCI, CO42, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
+, CZO);
+    input [23:0] A;
+    input [17:0] B;
+    input [35:0] C;
+    input [23:0] CAI;
+    output [23:0] CAO;
+    input [17:0] CBI;
+    output [17:0] CBO;
+    input CCI;
+    output CCO;
+    input CI;
+    input CK;
+    output CO42;
+    output CO56;
+    input [55:0] CZI;
+    output [55:0] CZO;
+    input [17:0] D;
+    output OVF;
+    input R;
+    input RZ;
+    input WE;
+    input WEZ;
+    output [55:0] Z;
+    parameter ALU_DYNAMIC_OP = 2'b00;
+    parameter ALU_OP = 3'b000;
+    parameter ENABLE_PR_A_RST = 1'b0;
+    parameter ENABLE_PR_B_RST = 1'b0;
+    parameter ENABLE_PR_CCO_RST = 1'b0;
+    parameter ENABLE_PR_CI_RST = 1'b0;
+    parameter ENABLE_PR_CO_RST = 1'b0;
+    parameter ENABLE_PR_CZ_RST = 1'b0;
+    parameter ENABLE_PR_C_RST = 1'b0;
+    parameter ENABLE_PR_D_RST = 1'b0;
+    parameter ENABLE_PR_MULT_RST = 1'b0;
+    parameter ENABLE_PR_OV_RST = 1'b0;
+    parameter ENABLE_PR_P_RST = 1'b0;
+    parameter ENABLE_PR_X_RST = 1'b0;
+    parameter ENABLE_PR_Y_RST = 1'b0;
+    parameter ENABLE_PR_Z_RST = 1'b0;
+    parameter ENABLE_SATURATION = 1'b0;
+    parameter INV_RST = 1'b0;
+    parameter INV_RSTZ = 1'b0;
+    parameter INV_WE = 1'b0;
+    parameter INV_WEZ = 1'b0;
+    parameter MUX_A = 1'b0;
+    parameter MUX_B = 1'b0;
+    parameter MUX_CCI = 1'b0;
+    parameter MUX_CCO = 1'b0;
+    parameter MUX_CI = 1'b0;
+    parameter MUX_CZ = 1'b0;
+    parameter MUX_P = 1'b0;
+    parameter MUX_X = 3'b000;
+    parameter MUX_Y = 1'b0;
+    parameter MUX_Z = 1'b0;
+    parameter PRE_ADDER_OP = 1'b0;
+    parameter PR_A_CASCADE_MUX = 2'b00;
+    parameter PR_A_MUX = 2'b00;
+    parameter PR_B_CASCADE_MUX = 2'b00;
+    parameter PR_B_MUX = 2'b00;
+    parameter PR_CCO_MUX = 1'b0;
+    parameter PR_CI_MUX = 1'b0;
+    parameter PR_CO_MUX = 1'b0;
+    parameter PR_CZ_MUX = 1'b0;
+    parameter PR_C_MUX = 1'b0;
+    parameter PR_D_MUX = 1'b0;
+    parameter PR_MULT_MUX = 1'b0;
+    parameter PR_OV_MUX = 1'b0;
+    parameter PR_P_MUX = 1'b0;
+    parameter PR_RSTZ_MUX = 1'b0;
+    parameter PR_RST_MUX = 1'b0;
+    parameter PR_WEZ_MUX = 1'b0;
+    parameter PR_WE_MUX = 1'b0;
+    parameter PR_X_MUX = 1'b0;
+    parameter PR_Y_MUX = 1'b0;
+    parameter PR_Z_MUX = 1'b0;
+    parameter SATURATION_RANK = 6'b000000;
+    parameter SIGNED_MODE = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_DSP_U_WRAP(CCI, CCO, CI, CK, CO43, CO57, OVF, R, RZ, WE, WEZ, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
+, CZO);
+    input [23:0] A;
+    input [17:0] B;
+    input [35:0] C;
+    input [23:0] CAI;
+    output [23:0] CAO;
+    input [17:0] CBI;
+    output [17:0] CBO;
+    input CCI;
+    output CCO;
+    input CI;
+    input CK;
+    output CO43;
+    output CO57;
+    input [55:0] CZI;
+    output [55:0] CZO;
+    input [17:0] D;
+    output OVF;
+    input R;
+    input RZ;
+    input WE;
+    input WEZ;
+    output [55:0] Z;
+    parameter raw_config0 = 27'b000000000000000000000000000;
+    parameter raw_config1 = 24'b000000000000000000000000;
+    parameter raw_config2 = 14'b00000000000000;
+    parameter raw_config3 = 3'b000;
+    parameter std_mode = "";
+endmodule
+
+(* blackbox *)
+module NX_DSP_WRAP(CCI, CCO, CI, CK, CO, CO37, CO49, OVF, R, RZ, WE, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
+, CZO);
+    input [23:0] A;
+    input [17:0] B;
+    input [35:0] C;
+    input [17:0] CAI;
+    output [17:0] CAO;
+    input [17:0] CBI;
+    output [17:0] CBO;
+    input CCI;
+    output CCO;
+    input CI;
+    input CK;
+    output CO;
+    output CO37;
+    output CO49;
+    input [55:0] CZI;
+    output [55:0] CZO;
+    input [17:0] D;
+    output OVF;
+    input R;
+    input RZ;
+    input WE;
+    output [55:0] Z;
+    parameter raw_config0 = 20'b00000000000000000000;
+    parameter raw_config1 = 19'b0000000000000000000;
+    parameter raw_config2 = 13'b0000000000000;
+    parameter raw_config3 = 7'b0000000;
+    parameter std_mode = "";
+endmodule
+
+(* blackbox *)
+module NX_ECC(CKD, CHK, COR, ERR);
+    input CHK;
+    input CKD;
+    output COR;
+    output ERR;
+endmodule
+
+(* blackbox *)
+module NX_FIFO_DPREG(RCK, WCK, WE, WEA, WRSTI, WRSTO, WEQ, RRSTI, RRSTO, REQ, I, O, WAI, WAO, RAI, RAO);
+    input [17:0] I;
+    output [17:0] O;
+    input [5:0] RAI;
+    output [5:0] RAO;
+    input RCK;
+    output REQ;
+    input RRSTI;
+    output RRSTO;
+    input [5:0] WAI;
+    output [5:0] WAO;
+    input WCK;
+    input WE;
+    input WEA;
+    output WEQ;
+    input WRSTI;
+    output WRSTO;
+    parameter rck_edge = 1'b0;
+    parameter read_addr_inv = 6'b000000;
+    parameter use_read_arst = 1'b0;
+    parameter use_write_arst = 1'b0;
+    parameter wck_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_FIFO_U(RCK, WCK, WE, WEA, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17
+, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2
+, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23
+, O24, O25, O26, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, WRSTI, WAI1, WAI2, WAI3, WAI4, WAI5, WAI6, WAI7
+, WRSTO, WAO1, WAO2, WAO3, WAO4, WAO5, WAO6, WAO7, WEQ1, WEQ2, RRSTI, RAI1, RAI2, RAI3, RAI4, RAI5, RAI6, RAI7, RRSTO, RAO1, RAO2
+, RAO3, RAO4, RAO5, RAO6, RAO7, REQ1, REQ2);
+    input I1;
+    input I10;
+    input I11;
+    input I12;
+    input I13;
+    input I14;
+    input I15;
+    input I16;
+    input I17;
+    input I18;
+    input I19;
+    input I2;
+    input I20;
+    input I21;
+    input I22;
+    input I23;
+    input I24;
+    input I25;
+    input I26;
+    input I27;
+    input I28;
+    input I29;
+    input I3;
+    input I30;
+    input I31;
+    input I32;
+    input I33;
+    input I34;
+    input I35;
+    input I36;
+    input I4;
+    input I5;
+    input I6;
+    input I7;
+    input I8;
+    input I9;
+    output O1;
+    output O10;
+    output O11;
+    output O12;
+    output O13;
+    output O14;
+    output O15;
+    output O16;
+    output O17;
+    output O18;
+    output O19;
+    output O2;
+    output O20;
+    output O21;
+    output O22;
+    output O23;
+    output O24;
+    output O25;
+    output O26;
+    output O27;
+    output O28;
+    output O29;
+    output O3;
+    output O30;
+    output O31;
+    output O32;
+    output O33;
+    output O34;
+    output O35;
+    output O36;
+    output O4;
+    output O5;
+    output O6;
+    output O7;
+    output O8;
+    output O9;
+    input RAI1;
+    input RAI2;
+    input RAI3;
+    input RAI4;
+    input RAI5;
+    input RAI6;
+    input RAI7;
+    output RAO1;
+    output RAO2;
+    output RAO3;
+    output RAO4;
+    output RAO5;
+    output RAO6;
+    output RAO7;
+    input RCK;
+    output REQ1;
+    output REQ2;
+    input RRSTI;
+    output RRSTO;
+    input WAI1;
+    input WAI2;
+    input WAI3;
+    input WAI4;
+    input WAI5;
+    input WAI6;
+    input WAI7;
+    output WAO1;
+    output WAO2;
+    output WAO3;
+    output WAO4;
+    output WAO5;
+    output WAO6;
+    output WAO7;
+    input WCK;
+    input WE;
+    input WEA;
+    output WEQ1;
+    output WEQ2;
+    input WRSTI;
+    output WRSTO;
+    parameter mode = 0;
+    parameter rck_edge = 1'b0;
+    parameter read_addr_inv = 7'b0000000;
+    parameter use_read_arst = 1'b0;
+    parameter use_write_arst = 1'b0;
+    parameter wck_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_GCK_U(SI1, SI2, CMD, SO);
+    input CMD;
+    input SI1;
+    input SI2;
+    output SO;
+    parameter inv_in = 1'b0;
+    parameter inv_out = 1'b0;
+    parameter std_mode = "BYPASS";
+endmodule
+
+(* blackbox *)
+module NX_HSSL_L_FULL(hssl_clk_user_i, hssl_clk_ref_i, hssl_clock_o, usr_com_tx_pma_pre_sign_i, usr_com_tx_pma_pre_en_i, usr_com_tx_pma_main_sign_i, usr_com_rx_pma_m_eye_i, usr_com_tx_pma_post_sign_i, usr_pll_pma_rst_n_i, usr_main_rst_n_i, usr_calibrate_pma_en_i, usr_pcs_ctrl_pll_lock_en_i, usr_pcs_ctrl_ovs_en_i, usr_pll_lock_o, usr_calibrate_pma_out_o, pma_clk_ext_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i, usr_tx0_pma_clk_en_i, usr_tx0_busy_o, pma_tx0_o
+, usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_ctrl_el_buff_fifo_en_i, usr_rx0_rst_n_i, usr_rx0_pma_cdr_rst_i, usr_rx0_pma_ckgen_rst_n_i, usr_rx0_pma_pll_rst_n_i, usr_rx0_pma_loss_of_signal_o, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_busy_o, usr_rx0_pll_lock_o, pma_rx0_i, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_pma_clk_en_i, usr_tx1_busy_o, pma_tx1_o
+, usr_rx1_ctrl_dscr_en_i, usr_rx1_ctrl_dec_en_i, usr_rx1_ctrl_align_en_i, usr_rx1_ctrl_align_sync_i, usr_rx1_ctrl_replace_en_i, usr_rx1_ctrl_el_buff_rst_i, usr_rx1_ctrl_el_buff_fifo_en_i, usr_rx1_rst_n_i, usr_rx1_pma_cdr_rst_i, usr_rx1_pma_ckgen_rst_n_i, usr_rx1_pma_pll_rst_n_i, usr_rx1_pma_loss_of_signal_o, usr_rx1_ctrl_char_is_aligned_o, usr_rx1_busy_o, usr_rx1_pll_lock_o, pma_rx1_i, usr_tx2_ctrl_replace_en_i, usr_tx2_rst_n_i, usr_tx2_pma_clk_en_i, usr_tx2_busy_o, pma_tx2_o
+, usr_rx2_ctrl_dscr_en_i, usr_rx2_ctrl_dec_en_i, usr_rx2_ctrl_align_en_i, usr_rx2_ctrl_align_sync_i, usr_rx2_ctrl_replace_en_i, usr_rx2_ctrl_el_buff_rst_i, usr_rx2_ctrl_el_buff_fifo_en_i, usr_rx2_rst_n_i, usr_rx2_pma_cdr_rst_i, usr_rx2_pma_ckgen_rst_n_i, usr_rx2_pma_pll_rst_n_i, usr_rx2_pma_loss_of_signal_o, usr_rx2_ctrl_char_is_aligned_o, usr_rx2_busy_o, usr_rx2_pll_lock_o, pma_rx2_i, usr_tx3_ctrl_replace_en_i, usr_tx3_rst_n_i, usr_tx3_pma_clk_en_i, usr_tx3_busy_o, pma_tx3_o
+, usr_rx3_ctrl_dscr_en_i, usr_rx3_ctrl_dec_en_i, usr_rx3_ctrl_align_en_i, usr_rx3_ctrl_align_sync_i, usr_rx3_ctrl_replace_en_i, usr_rx3_ctrl_el_buff_rst_i, usr_rx3_ctrl_el_buff_fifo_en_i, usr_rx3_rst_n_i, usr_rx3_pma_cdr_rst_i, usr_rx3_pma_ckgen_rst_n_i, usr_rx3_pma_pll_rst_n_i, usr_rx3_pma_loss_of_signal_o, usr_rx3_ctrl_char_is_aligned_o, usr_rx3_busy_o, usr_rx3_pll_lock_o, pma_rx3_i, usr_tx4_ctrl_replace_en_i, usr_tx4_rst_n_i, usr_tx4_pma_clk_en_i, usr_tx4_busy_o, pma_tx4_o
+, usr_rx4_ctrl_dscr_en_i, usr_rx4_ctrl_dec_en_i, usr_rx4_ctrl_align_en_i, usr_rx4_ctrl_align_sync_i, usr_rx4_ctrl_replace_en_i, usr_rx4_ctrl_el_buff_rst_i, usr_rx4_ctrl_el_buff_fifo_en_i, usr_rx4_rst_n_i, usr_rx4_pma_cdr_rst_i, usr_rx4_pma_ckgen_rst_n_i, usr_rx4_pma_pll_rst_n_i, usr_rx4_pma_loss_of_signal_o, usr_rx4_ctrl_char_is_aligned_o, usr_rx4_busy_o, usr_rx4_pll_lock_o, pma_rx4_i, usr_tx5_ctrl_replace_en_i, usr_tx5_rst_n_i, usr_tx5_pma_clk_en_i, usr_tx5_busy_o, pma_tx5_o
+, usr_rx5_ctrl_dscr_en_i, usr_rx5_ctrl_dec_en_i, usr_rx5_ctrl_align_en_i, usr_rx5_ctrl_align_sync_i, usr_rx5_ctrl_replace_en_i, usr_rx5_ctrl_el_buff_rst_i, usr_rx5_ctrl_el_buff_fifo_en_i, usr_rx5_rst_n_i, usr_rx5_pma_cdr_rst_i, usr_rx5_pma_ckgen_rst_n_i, usr_rx5_pma_pll_rst_n_i, usr_rx5_pma_loss_of_signal_o, usr_rx5_ctrl_char_is_aligned_o, usr_rx5_busy_o, usr_rx5_pll_lock_o, pma_rx5_i, usr_com_tx_pma_main_en_i, usr_com_tx_pma_margin_sel_i, usr_com_tx_pma_margin_input_sel_i, usr_com_tx_pma_margin_sel_var_i, usr_com_tx_pma_margin_input_sel_var_i
+, usr_com_tx_pma_post_en_i, usr_com_tx_pma_post_input_sel_i, usr_com_tx_pma_post_input_sel_var_i, usr_com_rx_pma_ctle_cap_i, usr_com_rx_pma_ctle_resp_i, usr_com_rx_pma_ctle_resn_i, usr_com_ctrl_tx_sel_i, usr_com_ctrl_rx_sel_i, usr_calibrate_pma_res_p1_i, usr_calibrate_pma_res_n2_i, usr_calibrate_pma_res_n3_i, usr_calibrate_pma_res_p4_i, usr_calibrate_pma_sel_i, usr_main_test_i, usr_main_test_o, usr_tx0_ctrl_enc_en_i, usr_tx0_ctrl_char_is_k_i, usr_tx0_ctrl_scr_en_i, usr_tx0_ctrl_end_of_multiframe_i, usr_tx0_ctrl_end_of_frame_i, usr_tx0_test_i
+, usr_tx0_data_i, usr_tx0_test_o, usr_rx0_data_o, usr_rx0_ctrl_ovs_bit_sel_i, usr_rx0_test_i, usr_rx0_ctrl_char_is_comma_o, usr_rx0_ctrl_char_is_k_o, usr_rx0_ctrl_not_in_table_o, usr_rx0_ctrl_disp_err_o, usr_rx0_ctrl_char_is_a_o, usr_rx0_ctrl_char_is_f_o, usr_rx0_test_o, usr_tx1_ctrl_enc_en_i, usr_tx1_ctrl_char_is_k_i, usr_tx1_ctrl_scr_en_i, usr_tx1_ctrl_end_of_multiframe_i, usr_tx1_ctrl_end_of_frame_i, usr_tx1_test_i, usr_tx1_data_i, usr_tx1_test_o, usr_rx1_data_o
+, usr_rx1_ctrl_ovs_bit_sel_i, usr_rx1_test_i, usr_rx1_ctrl_char_is_comma_o, usr_rx1_ctrl_char_is_k_o, usr_rx1_ctrl_not_in_table_o, usr_rx1_ctrl_disp_err_o, usr_rx1_ctrl_char_is_a_o, usr_rx1_ctrl_char_is_f_o, usr_rx1_test_o, usr_tx2_ctrl_enc_en_i, usr_tx2_ctrl_char_is_k_i, usr_tx2_ctrl_scr_en_i, usr_tx2_ctrl_end_of_multiframe_i, usr_tx2_ctrl_end_of_frame_i, usr_tx2_test_i, usr_tx2_data_i, usr_tx2_test_o, usr_rx2_data_o, usr_rx2_ctrl_ovs_bit_sel_i, usr_rx2_test_i, usr_rx2_ctrl_char_is_comma_o
+, usr_rx2_ctrl_char_is_k_o, usr_rx2_ctrl_not_in_table_o, usr_rx2_ctrl_disp_err_o, usr_rx2_ctrl_char_is_a_o, usr_rx2_ctrl_char_is_f_o, usr_rx2_test_o, usr_tx3_ctrl_enc_en_i, usr_tx3_ctrl_char_is_k_i, usr_tx3_ctrl_scr_en_i, usr_tx3_ctrl_end_of_multiframe_i, usr_tx3_ctrl_end_of_frame_i, usr_tx3_test_i, usr_tx3_data_i, usr_tx3_test_o, usr_rx3_data_o, usr_rx3_ctrl_ovs_bit_sel_i, usr_rx3_test_i, usr_rx3_ctrl_char_is_comma_o, usr_rx3_ctrl_char_is_k_o, usr_rx3_ctrl_not_in_table_o, usr_rx3_ctrl_disp_err_o
+, usr_rx3_ctrl_char_is_a_o, usr_rx3_ctrl_char_is_f_o, usr_rx3_test_o, usr_tx4_ctrl_enc_en_i, usr_tx4_ctrl_char_is_k_i, usr_tx4_ctrl_scr_en_i, usr_tx4_ctrl_end_of_multiframe_i, usr_tx4_ctrl_end_of_frame_i, usr_tx4_test_i, usr_tx4_data_i, usr_tx4_test_o, usr_rx4_data_o, usr_rx4_ctrl_ovs_bit_sel_i, usr_rx4_test_i, usr_rx4_ctrl_char_is_comma_o, usr_rx4_ctrl_char_is_k_o, usr_rx4_ctrl_not_in_table_o, usr_rx4_ctrl_disp_err_o, usr_rx4_ctrl_char_is_a_o, usr_rx4_ctrl_char_is_f_o, usr_rx4_test_o
+, usr_tx5_ctrl_enc_en_i, usr_tx5_ctrl_char_is_k_i, usr_tx5_ctrl_scr_en_i, usr_tx5_ctrl_end_of_multiframe_i, usr_tx5_ctrl_end_of_frame_i, usr_tx5_test_i, usr_tx5_data_i, usr_tx5_test_o, usr_rx5_data_o, usr_rx5_ctrl_ovs_bit_sel_i, usr_rx5_test_i, usr_rx5_ctrl_char_is_comma_o, usr_rx5_ctrl_char_is_k_o, usr_rx5_ctrl_not_in_table_o, usr_rx5_ctrl_disp_err_o, usr_rx5_ctrl_char_is_a_o, usr_rx5_ctrl_char_is_f_o, usr_rx5_test_o, usr_com_tx_pma_pre_input_sel_i);
+    input hssl_clk_ref_i;
+    input hssl_clk_user_i;
+    output hssl_clock_o;
+    input pma_clk_ext_i;
+    input pma_rx0_i;
+    input pma_rx1_i;
+    input pma_rx2_i;
+    input pma_rx3_i;
+    input pma_rx4_i;
+    input pma_rx5_i;
+    output pma_tx0_o;
+    output pma_tx1_o;
+    output pma_tx2_o;
+    output pma_tx3_o;
+    output pma_tx4_o;
+    output pma_tx5_o;
+    input usr_calibrate_pma_en_i;
+    output usr_calibrate_pma_out_o;
+    input [7:0] usr_calibrate_pma_res_n2_i;
+    input [7:0] usr_calibrate_pma_res_n3_i;
+    input [7:0] usr_calibrate_pma_res_p1_i;
+    input [7:0] usr_calibrate_pma_res_p4_i;
+    input [3:0] usr_calibrate_pma_sel_i;
+    input [5:0] usr_com_ctrl_rx_sel_i;
+    input [5:0] usr_com_ctrl_tx_sel_i;
+    input [3:0] usr_com_rx_pma_ctle_cap_i;
+    input [3:0] usr_com_rx_pma_ctle_resn_i;
+    input [3:0] usr_com_rx_pma_ctle_resp_i;
+    input usr_com_rx_pma_m_eye_i;
+    input [5:0] usr_com_tx_pma_main_en_i;
+    input usr_com_tx_pma_main_sign_i;
+    input [3:0] usr_com_tx_pma_margin_input_sel_i;
+    input [4:0] usr_com_tx_pma_margin_input_sel_var_i;
+    input [3:0] usr_com_tx_pma_margin_sel_i;
+    input [4:0] usr_com_tx_pma_margin_sel_var_i;
+    input [4:0] usr_com_tx_pma_post_en_i;
+    input [3:0] usr_com_tx_pma_post_input_sel_i;
+    input [3:0] usr_com_tx_pma_post_input_sel_var_i;
+    input usr_com_tx_pma_post_sign_i;
+    input usr_com_tx_pma_pre_en_i;
+    input [3:0] usr_com_tx_pma_pre_input_sel_i;
+    input usr_com_tx_pma_pre_sign_i;
+    input usr_main_rst_n_i;
+    input [7:0] usr_main_test_i;
+    output [7:0] usr_main_test_o;
+    input usr_pcs_ctrl_ovs_en_i;
+    input usr_pcs_ctrl_pll_lock_en_i;
+    output usr_pll_lock_o;
+    input usr_pll_pma_rst_n_i;
+    output usr_rx0_busy_o;
+    input usr_rx0_ctrl_align_en_i;
+    input usr_rx0_ctrl_align_sync_i;
+    output [7:0] usr_rx0_ctrl_char_is_a_o;
+    output usr_rx0_ctrl_char_is_aligned_o;
+    output [7:0] usr_rx0_ctrl_char_is_comma_o;
+    output [7:0] usr_rx0_ctrl_char_is_f_o;
+    output [7:0] usr_rx0_ctrl_char_is_k_o;
+    input usr_rx0_ctrl_dec_en_i;
+    output [7:0] usr_rx0_ctrl_disp_err_o;
+    input usr_rx0_ctrl_dscr_en_i;
+    input usr_rx0_ctrl_el_buff_fifo_en_i;
+    input usr_rx0_ctrl_el_buff_rst_i;
+    output [7:0] usr_rx0_ctrl_not_in_table_o;
+    input [1:0] usr_rx0_ctrl_ovs_bit_sel_i;
+    input usr_rx0_ctrl_replace_en_i;
+    output [63:0] usr_rx0_data_o;
+    output usr_rx0_pll_lock_o;
+    input usr_rx0_pma_cdr_rst_i;
+    input usr_rx0_pma_ckgen_rst_n_i;
+    output usr_rx0_pma_loss_of_signal_o;
+    input usr_rx0_pma_pll_rst_n_i;
+    input usr_rx0_rst_n_i;
+    input [3:0] usr_rx0_test_i;
+    output [7:0] usr_rx0_test_o;
+    output usr_rx1_busy_o;
+    input usr_rx1_ctrl_align_en_i;
+    input usr_rx1_ctrl_align_sync_i;
+    output [7:0] usr_rx1_ctrl_char_is_a_o;
+    output usr_rx1_ctrl_char_is_aligned_o;
+    output [7:0] usr_rx1_ctrl_char_is_comma_o;
+    output [7:0] usr_rx1_ctrl_char_is_f_o;
+    output [7:0] usr_rx1_ctrl_char_is_k_o;
+    input usr_rx1_ctrl_dec_en_i;
+    output [7:0] usr_rx1_ctrl_disp_err_o;
+    input usr_rx1_ctrl_dscr_en_i;
+    input usr_rx1_ctrl_el_buff_fifo_en_i;
+    input usr_rx1_ctrl_el_buff_rst_i;
+    output [7:0] usr_rx1_ctrl_not_in_table_o;
+    input [1:0] usr_rx1_ctrl_ovs_bit_sel_i;
+    input usr_rx1_ctrl_replace_en_i;
+    output [63:0] usr_rx1_data_o;
+    output usr_rx1_pll_lock_o;
+    input usr_rx1_pma_cdr_rst_i;
+    input usr_rx1_pma_ckgen_rst_n_i;
+    output usr_rx1_pma_loss_of_signal_o;
+    input usr_rx1_pma_pll_rst_n_i;
+    input usr_rx1_rst_n_i;
+    input [3:0] usr_rx1_test_i;
+    output [7:0] usr_rx1_test_o;
+    output usr_rx2_busy_o;
+    input usr_rx2_ctrl_align_en_i;
+    input usr_rx2_ctrl_align_sync_i;
+    output [7:0] usr_rx2_ctrl_char_is_a_o;
+    output usr_rx2_ctrl_char_is_aligned_o;
+    output [7:0] usr_rx2_ctrl_char_is_comma_o;
+    output [7:0] usr_rx2_ctrl_char_is_f_o;
+    output [7:0] usr_rx2_ctrl_char_is_k_o;
+    input usr_rx2_ctrl_dec_en_i;
+    output [7:0] usr_rx2_ctrl_disp_err_o;
+    input usr_rx2_ctrl_dscr_en_i;
+    input usr_rx2_ctrl_el_buff_fifo_en_i;
+    input usr_rx2_ctrl_el_buff_rst_i;
+    output [7:0] usr_rx2_ctrl_not_in_table_o;
+    input [1:0] usr_rx2_ctrl_ovs_bit_sel_i;
+    input usr_rx2_ctrl_replace_en_i;
+    output [63:0] usr_rx2_data_o;
+    output usr_rx2_pll_lock_o;
+    input usr_rx2_pma_cdr_rst_i;
+    input usr_rx2_pma_ckgen_rst_n_i;
+    output usr_rx2_pma_loss_of_signal_o;
+    input usr_rx2_pma_pll_rst_n_i;
+    input usr_rx2_rst_n_i;
+    input [3:0] usr_rx2_test_i;
+    output [7:0] usr_rx2_test_o;
+    output usr_rx3_busy_o;
+    input usr_rx3_ctrl_align_en_i;
+    input usr_rx3_ctrl_align_sync_i;
+    output [7:0] usr_rx3_ctrl_char_is_a_o;
+    output usr_rx3_ctrl_char_is_aligned_o;
+    output [7:0] usr_rx3_ctrl_char_is_comma_o;
+    output [7:0] usr_rx3_ctrl_char_is_f_o;
+    output [7:0] usr_rx3_ctrl_char_is_k_o;
+    input usr_rx3_ctrl_dec_en_i;
+    output [7:0] usr_rx3_ctrl_disp_err_o;
+    input usr_rx3_ctrl_dscr_en_i;
+    input usr_rx3_ctrl_el_buff_fifo_en_i;
+    input usr_rx3_ctrl_el_buff_rst_i;
+    output [7:0] usr_rx3_ctrl_not_in_table_o;
+    input [1:0] usr_rx3_ctrl_ovs_bit_sel_i;
+    input usr_rx3_ctrl_replace_en_i;
+    output [63:0] usr_rx3_data_o;
+    output usr_rx3_pll_lock_o;
+    input usr_rx3_pma_cdr_rst_i;
+    input usr_rx3_pma_ckgen_rst_n_i;
+    output usr_rx3_pma_loss_of_signal_o;
+    input usr_rx3_pma_pll_rst_n_i;
+    input usr_rx3_rst_n_i;
+    input [3:0] usr_rx3_test_i;
+    output [7:0] usr_rx3_test_o;
+    output usr_rx4_busy_o;
+    input usr_rx4_ctrl_align_en_i;
+    input usr_rx4_ctrl_align_sync_i;
+    output [7:0] usr_rx4_ctrl_char_is_a_o;
+    output usr_rx4_ctrl_char_is_aligned_o;
+    output [7:0] usr_rx4_ctrl_char_is_comma_o;
+    output [7:0] usr_rx4_ctrl_char_is_f_o;
+    output [7:0] usr_rx4_ctrl_char_is_k_o;
+    input usr_rx4_ctrl_dec_en_i;
+    output [7:0] usr_rx4_ctrl_disp_err_o;
+    input usr_rx4_ctrl_dscr_en_i;
+    input usr_rx4_ctrl_el_buff_fifo_en_i;
+    input usr_rx4_ctrl_el_buff_rst_i;
+    output [7:0] usr_rx4_ctrl_not_in_table_o;
+    input [1:0] usr_rx4_ctrl_ovs_bit_sel_i;
+    input usr_rx4_ctrl_replace_en_i;
+    output [63:0] usr_rx4_data_o;
+    output usr_rx4_pll_lock_o;
+    input usr_rx4_pma_cdr_rst_i;
+    input usr_rx4_pma_ckgen_rst_n_i;
+    output usr_rx4_pma_loss_of_signal_o;
+    input usr_rx4_pma_pll_rst_n_i;
+    input usr_rx4_rst_n_i;
+    input [3:0] usr_rx4_test_i;
+    output [7:0] usr_rx4_test_o;
+    output usr_rx5_busy_o;
+    input usr_rx5_ctrl_align_en_i;
+    input usr_rx5_ctrl_align_sync_i;
+    output [7:0] usr_rx5_ctrl_char_is_a_o;
+    output usr_rx5_ctrl_char_is_aligned_o;
+    output [7:0] usr_rx5_ctrl_char_is_comma_o;
+    output [7:0] usr_rx5_ctrl_char_is_f_o;
+    output [7:0] usr_rx5_ctrl_char_is_k_o;
+    input usr_rx5_ctrl_dec_en_i;
+    output [7:0] usr_rx5_ctrl_disp_err_o;
+    input usr_rx5_ctrl_dscr_en_i;
+    input usr_rx5_ctrl_el_buff_fifo_en_i;
+    input usr_rx5_ctrl_el_buff_rst_i;
+    output [7:0] usr_rx5_ctrl_not_in_table_o;
+    input [1:0] usr_rx5_ctrl_ovs_bit_sel_i;
+    input usr_rx5_ctrl_replace_en_i;
+    output [63:0] usr_rx5_data_o;
+    output usr_rx5_pll_lock_o;
+    input usr_rx5_pma_cdr_rst_i;
+    input usr_rx5_pma_ckgen_rst_n_i;
+    output usr_rx5_pma_loss_of_signal_o;
+    input usr_rx5_pma_pll_rst_n_i;
+    input usr_rx5_rst_n_i;
+    input [3:0] usr_rx5_test_i;
+    output [7:0] usr_rx5_test_o;
+    output usr_tx0_busy_o;
+    input [7:0] usr_tx0_ctrl_char_is_k_i;
+    input [7:0] usr_tx0_ctrl_enc_en_i;
+    input [7:0] usr_tx0_ctrl_end_of_frame_i;
+    input [7:0] usr_tx0_ctrl_end_of_multiframe_i;
+    input usr_tx0_ctrl_replace_en_i;
+    input [7:0] usr_tx0_ctrl_scr_en_i;
+    input [63:0] usr_tx0_data_i;
+    input usr_tx0_pma_clk_en_i;
+    input usr_tx0_rst_n_i;
+    input [3:0] usr_tx0_test_i;
+    output [3:0] usr_tx0_test_o;
+    output usr_tx1_busy_o;
+    input [7:0] usr_tx1_ctrl_char_is_k_i;
+    input [7:0] usr_tx1_ctrl_enc_en_i;
+    input [7:0] usr_tx1_ctrl_end_of_frame_i;
+    input [7:0] usr_tx1_ctrl_end_of_multiframe_i;
+    input usr_tx1_ctrl_replace_en_i;
+    input [7:0] usr_tx1_ctrl_scr_en_i;
+    input [63:0] usr_tx1_data_i;
+    input usr_tx1_pma_clk_en_i;
+    input usr_tx1_rst_n_i;
+    input [3:0] usr_tx1_test_i;
+    output [3:0] usr_tx1_test_o;
+    output usr_tx2_busy_o;
+    input [7:0] usr_tx2_ctrl_char_is_k_i;
+    input [7:0] usr_tx2_ctrl_enc_en_i;
+    input [7:0] usr_tx2_ctrl_end_of_frame_i;
+    input [7:0] usr_tx2_ctrl_end_of_multiframe_i;
+    input usr_tx2_ctrl_replace_en_i;
+    input [7:0] usr_tx2_ctrl_scr_en_i;
+    input [63:0] usr_tx2_data_i;
+    input usr_tx2_pma_clk_en_i;
+    input usr_tx2_rst_n_i;
+    input [3:0] usr_tx2_test_i;
+    output [3:0] usr_tx2_test_o;
+    output usr_tx3_busy_o;
+    input [7:0] usr_tx3_ctrl_char_is_k_i;
+    input [7:0] usr_tx3_ctrl_enc_en_i;
+    input [7:0] usr_tx3_ctrl_end_of_frame_i;
+    input [7:0] usr_tx3_ctrl_end_of_multiframe_i;
+    input usr_tx3_ctrl_replace_en_i;
+    input [7:0] usr_tx3_ctrl_scr_en_i;
+    input [63:0] usr_tx3_data_i;
+    input usr_tx3_pma_clk_en_i;
+    input usr_tx3_rst_n_i;
+    input [3:0] usr_tx3_test_i;
+    output [3:0] usr_tx3_test_o;
+    output usr_tx4_busy_o;
+    input [7:0] usr_tx4_ctrl_char_is_k_i;
+    input [7:0] usr_tx4_ctrl_enc_en_i;
+    input [7:0] usr_tx4_ctrl_end_of_frame_i;
+    input [7:0] usr_tx4_ctrl_end_of_multiframe_i;
+    input usr_tx4_ctrl_replace_en_i;
+    input [7:0] usr_tx4_ctrl_scr_en_i;
+    input [63:0] usr_tx4_data_i;
+    input usr_tx4_pma_clk_en_i;
+    input usr_tx4_rst_n_i;
+    input [3:0] usr_tx4_test_i;
+    output [3:0] usr_tx4_test_o;
+    output usr_tx5_busy_o;
+    input [7:0] usr_tx5_ctrl_char_is_k_i;
+    input [7:0] usr_tx5_ctrl_enc_en_i;
+    input [7:0] usr_tx5_ctrl_end_of_frame_i;
+    input [7:0] usr_tx5_ctrl_end_of_multiframe_i;
+    input usr_tx5_ctrl_replace_en_i;
+    input [7:0] usr_tx5_ctrl_scr_en_i;
+    input [63:0] usr_tx5_data_i;
+    input usr_tx5_pma_clk_en_i;
+    input usr_tx5_rst_n_i;
+    input [3:0] usr_tx5_test_i;
+    output [3:0] usr_tx5_test_o;
+    parameter cfg_main_i = 34'b0000000000000000000000000000000000;
+    parameter cfg_rx0_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter cfg_rx1_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter cfg_rx2_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter cfg_rx3_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter cfg_rx4_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter cfg_rx5_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter cfg_tx0_i = 0;
+    parameter cfg_tx1_i = 0;
+    parameter cfg_tx2_i = 0;
+    parameter cfg_tx3_i = 0;
+    parameter cfg_tx4_i = 0;
+    parameter cfg_tx5_i = 0;
+    parameter location = "";
+endmodule
+
+(* blackbox *)
+module NX_HSSL_U_FULL(hssl_clk_user_tx_i, hssl_clk_user_rx_i, hssl_clk_ref_i, hssl_clock_o, hssl_rclock_o, usr_dyn_cfg_en_i, usr_dyn_cfg_calibration_cs_n_i, usr_dyn_cfg_we_n_i, usr_dyn_cfg_wdata_sel_i, usr_pll_pma_rst_n_i, usr_pll_pma_pwr_down_n_i, usr_main_rst_n_i, usr_pll_lock_o, usr_pll_pma_lock_analog_o, usr_pll_ckfb_lock_o, usr_calibrate_pma_out_o, usr_main_async_debug_ack_i, usr_main_async_debug_req_o, scan_en_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i
+, usr_tx0_busy_o, usr_tx0_ctrl_invalid_k_o, usr_tx0_ctrl_driver_pwrdwn_n_i, usr_tx0_pma_clk_en_i, usr_tx0_pma_tx_clk_o, usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_rst_n_i, usr_rx0_pma_rst_n_i, usr_rx0_pma_m_eye_rst_i, usr_rx0_pma_pwr_down_n_i, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_ctrl_valid_realign_o, usr_rx0_busy_o, usr_rx0_pma_loss_of_signal_o, usr_rx0_pma_ll_fast_locked_o, usr_rx0_pma_ll_slow_locked_o
+, usr_rx0_pma_pll_lock_o, usr_rx0_pma_pll_lock_track_o, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_busy_o, usr_tx1_ctrl_invalid_k_o, usr_tx1_ctrl_driver_pwrdwn_n_i, usr_tx1_pma_clk_en_i, usr_tx1_pma_tx_clk_o, usr_rx1_ctrl_dscr_en_i, usr_rx1_ctrl_dec_en_i, usr_rx1_ctrl_align_en_i, usr_rx1_ctrl_align_sync_i, usr_rx1_ctrl_replace_en_i, usr_rx1_ctrl_el_buff_rst_i, usr_rx1_rst_n_i, usr_rx1_pma_rst_n_i, usr_rx1_pma_m_eye_rst_i, usr_rx1_pma_pwr_down_n_i, usr_rx1_ctrl_char_is_aligned_o, usr_rx1_ctrl_valid_realign_o
+, usr_rx1_busy_o, usr_rx1_pma_loss_of_signal_o, usr_rx1_pma_ll_fast_locked_o, usr_rx1_pma_ll_slow_locked_o, usr_rx1_pma_pll_lock_o, usr_rx1_pma_pll_lock_track_o, usr_tx2_ctrl_replace_en_i, usr_tx2_rst_n_i, usr_tx2_busy_o, usr_tx2_ctrl_invalid_k_o, usr_tx2_ctrl_driver_pwrdwn_n_i, usr_tx2_pma_clk_en_i, usr_tx2_pma_tx_clk_o, usr_rx2_ctrl_dscr_en_i, usr_rx2_ctrl_dec_en_i, usr_rx2_ctrl_align_en_i, usr_rx2_ctrl_align_sync_i, usr_rx2_ctrl_replace_en_i, usr_rx2_ctrl_el_buff_rst_i, usr_rx2_rst_n_i, usr_rx2_pma_rst_n_i
+, usr_rx2_pma_m_eye_rst_i, usr_rx2_pma_pwr_down_n_i, usr_rx2_ctrl_char_is_aligned_o, usr_rx2_ctrl_valid_realign_o, usr_rx2_busy_o, usr_rx2_pma_loss_of_signal_o, usr_rx2_pma_ll_fast_locked_o, usr_rx2_pma_ll_slow_locked_o, usr_rx2_pma_pll_lock_o, usr_rx2_pma_pll_lock_track_o, usr_tx3_ctrl_replace_en_i, usr_tx3_rst_n_i, usr_tx3_busy_o, usr_tx3_ctrl_invalid_k_o, usr_tx3_ctrl_driver_pwrdwn_n_i, usr_tx3_pma_clk_en_i, usr_tx3_pma_tx_clk_o, usr_rx3_ctrl_dscr_en_i, usr_rx3_ctrl_dec_en_i, usr_rx3_ctrl_align_en_i, usr_rx3_ctrl_align_sync_i
+, usr_rx3_ctrl_replace_en_i, usr_rx3_ctrl_el_buff_rst_i, usr_rx3_rst_n_i, usr_rx3_pma_rst_n_i, usr_rx3_pma_m_eye_rst_i, usr_rx3_pma_pwr_down_n_i, usr_rx3_ctrl_char_is_aligned_o, usr_rx3_ctrl_valid_realign_o, usr_rx3_busy_o, usr_rx3_pma_loss_of_signal_o, usr_rx3_pma_ll_fast_locked_o, usr_rx3_pma_ll_slow_locked_o, usr_rx3_pma_pll_lock_o, usr_rx3_pma_pll_lock_track_o, usr_tx0_ctrl_enc_en_i, usr_tx0_ctrl_char_is_k_i, usr_tx0_ctrl_scr_en_i, usr_tx0_ctrl_end_of_multiframe_i, usr_tx0_ctrl_end_of_frame_i, usr_tx0_data_i, usr_rx0_data_o
+, usr_rx0_ctrl_ovs_bit_sel_i, usr_rx0_ctrl_char_is_comma_o, usr_rx0_ctrl_char_is_k_o, usr_rx0_ctrl_not_in_table_o, usr_rx0_ctrl_disp_err_o, usr_rx0_ctrl_char_is_a_o, usr_rx0_ctrl_char_is_f_o, usr_rx0_test_o, usr_tx1_ctrl_enc_en_i, usr_tx1_ctrl_char_is_k_i, usr_tx1_ctrl_scr_en_i, usr_tx1_ctrl_end_of_multiframe_i, usr_tx1_ctrl_end_of_frame_i, usr_tx1_data_i, usr_rx1_data_o, usr_rx1_ctrl_ovs_bit_sel_i, usr_rx1_ctrl_char_is_comma_o, usr_rx1_ctrl_char_is_k_o, usr_rx1_ctrl_not_in_table_o, usr_rx1_ctrl_disp_err_o, usr_rx1_ctrl_char_is_a_o
+, usr_rx1_ctrl_char_is_f_o, usr_rx1_test_o, usr_tx2_ctrl_enc_en_i, usr_tx2_ctrl_char_is_k_i, usr_tx2_ctrl_scr_en_i, usr_tx2_ctrl_end_of_multiframe_i, usr_tx2_ctrl_end_of_frame_i, usr_tx2_data_i, usr_rx2_data_o, usr_rx2_ctrl_ovs_bit_sel_i, usr_rx2_ctrl_char_is_comma_o, usr_rx2_ctrl_char_is_k_o, usr_rx2_ctrl_not_in_table_o, usr_rx2_ctrl_disp_err_o, usr_rx2_ctrl_char_is_a_o, usr_rx2_ctrl_char_is_f_o, usr_rx2_test_o, usr_tx3_ctrl_enc_en_i, usr_tx3_ctrl_char_is_k_i, usr_tx3_ctrl_scr_en_i, usr_tx3_ctrl_end_of_multiframe_i
+, usr_tx3_ctrl_end_of_frame_i, usr_tx3_data_i, usr_rx3_data_o, usr_rx3_ctrl_ovs_bit_sel_i, usr_rx3_ctrl_char_is_comma_o, usr_rx3_ctrl_char_is_k_o, usr_rx3_ctrl_not_in_table_o, usr_rx3_ctrl_disp_err_o, usr_rx3_ctrl_char_is_a_o, usr_rx3_ctrl_char_is_f_o, usr_rx3_test_o, usr_dyn_cfg_addr_i, usr_dyn_cfg_wdata_i, usr_main_async_debug_lane_sel_i, usr_main_rx_pma_ll_out_o, scan_in_i, scan_out_o, usr_rx0_ctrl_debug_sel_i, usr_rx1_ctrl_debug_sel_i, usr_rx2_ctrl_debug_sel_i, usr_rx3_ctrl_debug_sel_i
+, usr_dyn_cfg_lane_cs_n_i);
+    input hssl_clk_ref_i;
+    input hssl_clk_user_rx_i;
+    input hssl_clk_user_tx_i;
+    output hssl_clock_o;
+    output hssl_rclock_o;
+    input scan_en_i;
+    input [7:0] scan_in_i;
+    output [7:0] scan_out_o;
+    output usr_calibrate_pma_out_o;
+    input [3:0] usr_dyn_cfg_addr_i;
+    input usr_dyn_cfg_calibration_cs_n_i;
+    input usr_dyn_cfg_en_i;
+    input [3:0] usr_dyn_cfg_lane_cs_n_i;
+    input [11:0] usr_dyn_cfg_wdata_i;
+    input usr_dyn_cfg_wdata_sel_i;
+    input usr_dyn_cfg_we_n_i;
+    input usr_main_async_debug_ack_i;
+    input [1:0] usr_main_async_debug_lane_sel_i;
+    output usr_main_async_debug_req_o;
+    input usr_main_rst_n_i;
+    output [19:0] usr_main_rx_pma_ll_out_o;
+    output usr_pll_ckfb_lock_o;
+    output usr_pll_lock_o;
+    output usr_pll_pma_lock_analog_o;
+    input usr_pll_pma_pwr_down_n_i;
+    input usr_pll_pma_rst_n_i;
+    output usr_rx0_busy_o;
+    input usr_rx0_ctrl_align_en_i;
+    input usr_rx0_ctrl_align_sync_i;
+    output [7:0] usr_rx0_ctrl_char_is_a_o;
+    output usr_rx0_ctrl_char_is_aligned_o;
+    output [7:0] usr_rx0_ctrl_char_is_comma_o;
+    output [7:0] usr_rx0_ctrl_char_is_f_o;
+    output [7:0] usr_rx0_ctrl_char_is_k_o;
+    input [2:0] usr_rx0_ctrl_debug_sel_i;
+    input usr_rx0_ctrl_dec_en_i;
+    output [7:0] usr_rx0_ctrl_disp_err_o;
+    input usr_rx0_ctrl_dscr_en_i;
+    input usr_rx0_ctrl_el_buff_rst_i;
+    output [7:0] usr_rx0_ctrl_not_in_table_o;
+    input [1:0] usr_rx0_ctrl_ovs_bit_sel_i;
+    input usr_rx0_ctrl_replace_en_i;
+    output usr_rx0_ctrl_valid_realign_o;
+    output [63:0] usr_rx0_data_o;
+    output usr_rx0_pma_ll_fast_locked_o;
+    output usr_rx0_pma_ll_slow_locked_o;
+    output usr_rx0_pma_loss_of_signal_o;
+    input usr_rx0_pma_m_eye_rst_i;
+    output usr_rx0_pma_pll_lock_o;
+    output usr_rx0_pma_pll_lock_track_o;
+    input usr_rx0_pma_pwr_down_n_i;
+    input usr_rx0_pma_rst_n_i;
+    input usr_rx0_rst_n_i;
+    output [7:0] usr_rx0_test_o;
+    output usr_rx1_busy_o;
+    input usr_rx1_ctrl_align_en_i;
+    input usr_rx1_ctrl_align_sync_i;
+    output [7:0] usr_rx1_ctrl_char_is_a_o;
+    output usr_rx1_ctrl_char_is_aligned_o;
+    output [7:0] usr_rx1_ctrl_char_is_comma_o;
+    output [7:0] usr_rx1_ctrl_char_is_f_o;
+    output [7:0] usr_rx1_ctrl_char_is_k_o;
+    input [2:0] usr_rx1_ctrl_debug_sel_i;
+    input usr_rx1_ctrl_dec_en_i;
+    output [7:0] usr_rx1_ctrl_disp_err_o;
+    input usr_rx1_ctrl_dscr_en_i;
+    input usr_rx1_ctrl_el_buff_rst_i;
+    output [7:0] usr_rx1_ctrl_not_in_table_o;
+    input [1:0] usr_rx1_ctrl_ovs_bit_sel_i;
+    input usr_rx1_ctrl_replace_en_i;
+    output usr_rx1_ctrl_valid_realign_o;
+    output [63:0] usr_rx1_data_o;
+    output usr_rx1_pma_ll_fast_locked_o;
+    output usr_rx1_pma_ll_slow_locked_o;
+    output usr_rx1_pma_loss_of_signal_o;
+    input usr_rx1_pma_m_eye_rst_i;
+    output usr_rx1_pma_pll_lock_o;
+    output usr_rx1_pma_pll_lock_track_o;
+    input usr_rx1_pma_pwr_down_n_i;
+    input usr_rx1_pma_rst_n_i;
+    input usr_rx1_rst_n_i;
+    output [7:0] usr_rx1_test_o;
+    output usr_rx2_busy_o;
+    input usr_rx2_ctrl_align_en_i;
+    input usr_rx2_ctrl_align_sync_i;
+    output [7:0] usr_rx2_ctrl_char_is_a_o;
+    output usr_rx2_ctrl_char_is_aligned_o;
+    output [7:0] usr_rx2_ctrl_char_is_comma_o;
+    output [7:0] usr_rx2_ctrl_char_is_f_o;
+    output [7:0] usr_rx2_ctrl_char_is_k_o;
+    input [2:0] usr_rx2_ctrl_debug_sel_i;
+    input usr_rx2_ctrl_dec_en_i;
+    output [7:0] usr_rx2_ctrl_disp_err_o;
+    input usr_rx2_ctrl_dscr_en_i;
+    input usr_rx2_ctrl_el_buff_rst_i;
+    output [7:0] usr_rx2_ctrl_not_in_table_o;
+    input [1:0] usr_rx2_ctrl_ovs_bit_sel_i;
+    input usr_rx2_ctrl_replace_en_i;
+    output usr_rx2_ctrl_valid_realign_o;
+    output [63:0] usr_rx2_data_o;
+    output usr_rx2_pma_ll_fast_locked_o;
+    output usr_rx2_pma_ll_slow_locked_o;
+    output usr_rx2_pma_loss_of_signal_o;
+    input usr_rx2_pma_m_eye_rst_i;
+    output usr_rx2_pma_pll_lock_o;
+    output usr_rx2_pma_pll_lock_track_o;
+    input usr_rx2_pma_pwr_down_n_i;
+    input usr_rx2_pma_rst_n_i;
+    input usr_rx2_rst_n_i;
+    output [7:0] usr_rx2_test_o;
+    output usr_rx3_busy_o;
+    input usr_rx3_ctrl_align_en_i;
+    input usr_rx3_ctrl_align_sync_i;
+    output [7:0] usr_rx3_ctrl_char_is_a_o;
+    output usr_rx3_ctrl_char_is_aligned_o;
+    output [7:0] usr_rx3_ctrl_char_is_comma_o;
+    output [7:0] usr_rx3_ctrl_char_is_f_o;
+    output [7:0] usr_rx3_ctrl_char_is_k_o;
+    input [2:0] usr_rx3_ctrl_debug_sel_i;
+    input usr_rx3_ctrl_dec_en_i;
+    output [7:0] usr_rx3_ctrl_disp_err_o;
+    input usr_rx3_ctrl_dscr_en_i;
+    input usr_rx3_ctrl_el_buff_rst_i;
+    output [7:0] usr_rx3_ctrl_not_in_table_o;
+    input [1:0] usr_rx3_ctrl_ovs_bit_sel_i;
+    input usr_rx3_ctrl_replace_en_i;
+    output usr_rx3_ctrl_valid_realign_o;
+    output [63:0] usr_rx3_data_o;
+    output usr_rx3_pma_ll_fast_locked_o;
+    output usr_rx3_pma_ll_slow_locked_o;
+    output usr_rx3_pma_loss_of_signal_o;
+    input usr_rx3_pma_m_eye_rst_i;
+    output usr_rx3_pma_pll_lock_o;
+    output usr_rx3_pma_pll_lock_track_o;
+    input usr_rx3_pma_pwr_down_n_i;
+    input usr_rx3_pma_rst_n_i;
+    input usr_rx3_rst_n_i;
+    output [7:0] usr_rx3_test_o;
+    output usr_tx0_busy_o;
+    input [7:0] usr_tx0_ctrl_char_is_k_i;
+    input usr_tx0_ctrl_driver_pwrdwn_n_i;
+    input [7:0] usr_tx0_ctrl_enc_en_i;
+    input [7:0] usr_tx0_ctrl_end_of_frame_i;
+    input [7:0] usr_tx0_ctrl_end_of_multiframe_i;
+    output usr_tx0_ctrl_invalid_k_o;
+    input usr_tx0_ctrl_replace_en_i;
+    input [7:0] usr_tx0_ctrl_scr_en_i;
+    input [63:0] usr_tx0_data_i;
+    input usr_tx0_pma_clk_en_i;
+    output usr_tx0_pma_tx_clk_o;
+    input usr_tx0_rst_n_i;
+    output usr_tx1_busy_o;
+    input [7:0] usr_tx1_ctrl_char_is_k_i;
+    input usr_tx1_ctrl_driver_pwrdwn_n_i;
+    input [7:0] usr_tx1_ctrl_enc_en_i;
+    input [7:0] usr_tx1_ctrl_end_of_frame_i;
+    input [7:0] usr_tx1_ctrl_end_of_multiframe_i;
+    output usr_tx1_ctrl_invalid_k_o;
+    input usr_tx1_ctrl_replace_en_i;
+    input [7:0] usr_tx1_ctrl_scr_en_i;
+    input [63:0] usr_tx1_data_i;
+    input usr_tx1_pma_clk_en_i;
+    output usr_tx1_pma_tx_clk_o;
+    input usr_tx1_rst_n_i;
+    output usr_tx2_busy_o;
+    input [7:0] usr_tx2_ctrl_char_is_k_i;
+    input usr_tx2_ctrl_driver_pwrdwn_n_i;
+    input [7:0] usr_tx2_ctrl_enc_en_i;
+    input [7:0] usr_tx2_ctrl_end_of_frame_i;
+    input [7:0] usr_tx2_ctrl_end_of_multiframe_i;
+    output usr_tx2_ctrl_invalid_k_o;
+    input usr_tx2_ctrl_replace_en_i;
+    input [7:0] usr_tx2_ctrl_scr_en_i;
+    input [63:0] usr_tx2_data_i;
+    input usr_tx2_pma_clk_en_i;
+    output usr_tx2_pma_tx_clk_o;
+    input usr_tx2_rst_n_i;
+    output usr_tx3_busy_o;
+    input [7:0] usr_tx3_ctrl_char_is_k_i;
+    input usr_tx3_ctrl_driver_pwrdwn_n_i;
+    input [7:0] usr_tx3_ctrl_enc_en_i;
+    input [7:0] usr_tx3_ctrl_end_of_frame_i;
+    input [7:0] usr_tx3_ctrl_end_of_multiframe_i;
+    output usr_tx3_ctrl_invalid_k_o;
+    input usr_tx3_ctrl_replace_en_i;
+    input [7:0] usr_tx3_ctrl_scr_en_i;
+    input [63:0] usr_tx3_data_i;
+    input usr_tx3_pma_clk_en_i;
+    output usr_tx3_pma_tx_clk_o;
+    input usr_tx3_rst_n_i;
+    parameter cfg_dyn_all_rx_pma_m_eye_coarse_ena_i = 1'b0;
+    parameter cfg_dyn_all_rx_pma_m_eye_dn_i = 1'b0;
+    parameter cfg_dyn_all_rx_pma_m_eye_fine_ena_i = 1'b0;
+    parameter cfg_dyn_all_rx_pma_m_eye_i = 1'b0;
+    parameter cfg_dyn_all_rx_pma_m_eye_step_i = 4'b0000;
+    parameter cfg_dyn_all_rx_pma_m_eye_up_i = 1'b0;
+    parameter cfg_dyn_all_rx_pma_threshold_1 = 5'b00000;
+    parameter cfg_dyn_all_rx_pma_threshold_2 = 5'b00000;
+    parameter cfg_dyn_all_rx_pma_trim_locked_i = 3'b000;
+    parameter cfg_dyn_all_rx_pma_trim_mode_i = 2'b00;
+    parameter cfg_dyn_all_rx_pma_trim_unlocked_i = 3'b000;
+    parameter cfg_dyn_rx0_pma_ctle_cap_p_i = 4'b0000;
+    parameter cfg_dyn_rx0_pma_ctle_res_p_i = 4'b0000;
+    parameter cfg_dyn_rx0_pma_dfe_idac_tap1_n_i = 6'b000000;
+    parameter cfg_dyn_rx0_pma_dfe_idac_tap2_n_i = 6'b000000;
+    parameter cfg_dyn_rx0_pma_dfe_idac_tap3_n_i = 6'b000000;
+    parameter cfg_dyn_rx0_pma_dfe_idac_tap4_n_i = 6'b000000;
+    parameter cfg_dyn_rx0_pma_termination_cmd_i = 6'b000000;
+    parameter cfg_dyn_rx1_pma_ctle_cap_p_i = 4'b0000;
+    parameter cfg_dyn_rx1_pma_ctle_res_p_i = 4'b0000;
+    parameter cfg_dyn_rx1_pma_dfe_idac_tap1_n_i = 6'b000000;
+    parameter cfg_dyn_rx1_pma_dfe_idac_tap2_n_i = 6'b000000;
+    parameter cfg_dyn_rx1_pma_dfe_idac_tap3_n_i = 6'b000000;
+    parameter cfg_dyn_rx1_pma_dfe_idac_tap4_n_i = 6'b000000;
+    parameter cfg_dyn_rx1_pma_termination_cmd_i = 6'b000000;
+    parameter cfg_dyn_rx2_pma_ctle_cap_p_i = 4'b0000;
+    parameter cfg_dyn_rx2_pma_ctle_res_p_i = 4'b0000;
+    parameter cfg_dyn_rx2_pma_dfe_idac_tap1_n_i = 6'b000000;
+    parameter cfg_dyn_rx2_pma_dfe_idac_tap2_n_i = 6'b000000;
+    parameter cfg_dyn_rx2_pma_dfe_idac_tap3_n_i = 6'b000000;
+    parameter cfg_dyn_rx2_pma_dfe_idac_tap4_n_i = 6'b000000;
+    parameter cfg_dyn_rx2_pma_termination_cmd_i = 6'b000000;
+    parameter cfg_dyn_rx3_pma_ctle_cap_p_i = 4'b0000;
+    parameter cfg_dyn_rx3_pma_ctle_res_p_i = 4'b0000;
+    parameter cfg_dyn_rx3_pma_dfe_idac_tap1_n_i = 6'b000000;
+    parameter cfg_dyn_rx3_pma_dfe_idac_tap2_n_i = 6'b000000;
+    parameter cfg_dyn_rx3_pma_dfe_idac_tap3_n_i = 6'b000000;
+    parameter cfg_dyn_rx3_pma_dfe_idac_tap4_n_i = 6'b000000;
+    parameter cfg_dyn_rx3_pma_termination_cmd_i = 6'b000000;
+    parameter cfg_dyn_tx0_pma_main_en_i = 6'b000000;
+    parameter cfg_dyn_tx0_pma_main_sign_i = 1'b0;
+    parameter cfg_dyn_tx0_pma_margin_input_i = 9'b000000000;
+    parameter cfg_dyn_tx0_pma_margin_sel_i = 9'b000000000;
+    parameter cfg_dyn_tx0_pma_post_en_i = 5'b00000;
+    parameter cfg_dyn_tx0_pma_post_sel_i = 8'b00000000;
+    parameter cfg_dyn_tx0_pma_post_sign_i = 1'b0;
+    parameter cfg_dyn_tx0_pma_pre_en_i = 1'b0;
+    parameter cfg_dyn_tx0_pma_pre_sel_i = 4'b0000;
+    parameter cfg_dyn_tx0_pma_pre_sign_i = 1'b0;
+    parameter cfg_dyn_tx1_pma_main_en_i = 6'b000000;
+    parameter cfg_dyn_tx1_pma_main_sign_i = 1'b0;
+    parameter cfg_dyn_tx1_pma_margin_input_i = 9'b000000000;
+    parameter cfg_dyn_tx1_pma_margin_sel_i = 9'b000000000;
+    parameter cfg_dyn_tx1_pma_post_en_i = 5'b00000;
+    parameter cfg_dyn_tx1_pma_post_sel_i = 8'b00000000;
+    parameter cfg_dyn_tx1_pma_post_sign_i = 1'b0;
+    parameter cfg_dyn_tx1_pma_pre_en_i = 1'b0;
+    parameter cfg_dyn_tx1_pma_pre_sel_i = 4'b0000;
+    parameter cfg_dyn_tx1_pma_pre_sign_i = 1'b0;
+    parameter cfg_dyn_tx2_pma_main_en_i = 6'b000000;
+    parameter cfg_dyn_tx2_pma_main_sign_i = 1'b0;
+    parameter cfg_dyn_tx2_pma_margin_input_i = 9'b000000000;
+    parameter cfg_dyn_tx2_pma_margin_sel_i = 9'b000000000;
+    parameter cfg_dyn_tx2_pma_post_en_i = 5'b00000;
+    parameter cfg_dyn_tx2_pma_post_sel_i = 8'b00000000;
+    parameter cfg_dyn_tx2_pma_post_sign_i = 1'b0;
+    parameter cfg_dyn_tx2_pma_pre_en_i = 1'b0;
+    parameter cfg_dyn_tx2_pma_pre_sel_i = 4'b0000;
+    parameter cfg_dyn_tx2_pma_pre_sign_i = 1'b0;
+    parameter cfg_dyn_tx3_pma_main_en_i = 6'b000000;
+    parameter cfg_dyn_tx3_pma_main_sign_i = 1'b0;
+    parameter cfg_dyn_tx3_pma_margin_input_i = 9'b000000000;
+    parameter cfg_dyn_tx3_pma_margin_sel_i = 9'b000000000;
+    parameter cfg_dyn_tx3_pma_post_en_i = 5'b00000;
+    parameter cfg_dyn_tx3_pma_post_sel_i = 8'b00000000;
+    parameter cfg_dyn_tx3_pma_post_sign_i = 1'b0;
+    parameter cfg_dyn_tx3_pma_pre_en_i = 1'b0;
+    parameter cfg_dyn_tx3_pma_pre_sel_i = 4'b0000;
+    parameter cfg_dyn_tx3_pma_pre_sign_i = 1'b0;
+    parameter cfg_main_clk_to_fabric_div_en_i = 1'b0;
+    parameter cfg_main_clk_to_fabric_div_mode_i = 1'b0;
+    parameter cfg_main_clk_to_fabric_sel_i = 1'b0;
+    parameter cfg_main_rclk_to_fabric_sel_i = 2'b00;
+    parameter cfg_main_use_only_usr_clock_i = 1'b0;
+    parameter cfg_pcs_ovs_en_i = 1'b0;
+    parameter cfg_pcs_ovs_mode_i = 1'b0;
+    parameter cfg_pcs_pll_lock_ppm_i = 3'b000;
+    parameter cfg_pcs_word_len_i = 2'b00;
+    parameter cfg_pll_pma_ckref_ext_i = 1'b0;
+    parameter cfg_pll_pma_cpump_i = 4'b0000;
+    parameter cfg_pll_pma_divl_i = 2'b00;
+    parameter cfg_pll_pma_divm_i = 1'b0;
+    parameter cfg_pll_pma_divn_i = 2'b00;
+    parameter cfg_pll_pma_gbx_en_i = 1'b0;
+    parameter cfg_pll_pma_int_data_len_i = 1'b0;
+    parameter cfg_pll_pma_lvds_en_i = 1'b0;
+    parameter cfg_pll_pma_lvds_mux_i = 1'b0;
+    parameter cfg_pll_pma_mux_ckref_i = 1'b0;
+    parameter cfg_rx0_gearbox_en_i = 1'b0;
+    parameter cfg_rx0_gearbox_mode_i = 1'b0;
+    parameter cfg_rx0_pcs_8b_dscr_sel_i = 1'b0;
+    parameter cfg_rx0_pcs_align_bypass_i = 1'b0;
+    parameter cfg_rx0_pcs_buffers_bypass_i = 1'b0;
+    parameter cfg_rx0_pcs_buffers_use_cdc_i = 1'b0;
+    parameter cfg_rx0_pcs_bypass_pma_cdc_i = 1'b0;
+    parameter cfg_rx0_pcs_bypass_usr_cdc_i = 1'b0;
+    parameter cfg_rx0_pcs_comma_mask_i = 10'b0000000000;
+    parameter cfg_rx0_pcs_debug_en_i = 1'b0;
+    parameter cfg_rx0_pcs_dec_bypass_i = 1'b0;
+    parameter cfg_rx0_pcs_dscr_bypass_i = 1'b0;
+    parameter cfg_rx0_pcs_el_buff_diff_bef_comp_i = 4'b0000;
+    parameter cfg_rx0_pcs_el_buff_max_comp_i = 4'b0000;
+    parameter cfg_rx0_pcs_el_buff_only_one_skp_i = 1'b0;
+    parameter cfg_rx0_pcs_el_buff_skp_char_0_i = 9'b000000000;
+    parameter cfg_rx0_pcs_el_buff_skp_char_1_i = 9'b000000000;
+    parameter cfg_rx0_pcs_el_buff_skp_char_2_i = 9'b000000000;
+    parameter cfg_rx0_pcs_el_buff_skp_char_3_i = 9'b000000000;
+    parameter cfg_rx0_pcs_el_buff_skp_header_0_i = 9'b000000000;
+    parameter cfg_rx0_pcs_el_buff_skp_header_1_i = 9'b000000000;
+    parameter cfg_rx0_pcs_el_buff_skp_header_2_i = 9'b000000000;
+    parameter cfg_rx0_pcs_el_buff_skp_header_3_i = 9'b000000000;
+    parameter cfg_rx0_pcs_el_buff_skp_header_size_i = 2'b00;
+    parameter cfg_rx0_pcs_el_buff_skp_seq_size_i = 2'b00;
+    parameter cfg_rx0_pcs_fsm_sel_i = 2'b00;
+    parameter cfg_rx0_pcs_fsm_watchdog_en_i = 1'b0;
+    parameter cfg_rx0_pcs_loopback_i = 1'b0;
+    parameter cfg_rx0_pcs_m_comma_en_i = 1'b0;
+    parameter cfg_rx0_pcs_m_comma_val_i = 10'b0000000000;
+    parameter cfg_rx0_pcs_nb_comma_bef_realign_i = 2'b00;
+    parameter cfg_rx0_pcs_p_comma_en_i = 1'b0;
+    parameter cfg_rx0_pcs_p_comma_val_i = 10'b0000000000;
+    parameter cfg_rx0_pcs_polarity_i = 1'b0;
+    parameter cfg_rx0_pcs_protocol_size_i = 1'b0;
+    parameter cfg_rx0_pcs_replace_bypass_i = 1'b0;
+    parameter cfg_rx0_pcs_sync_supported_i = 1'b0;
+    parameter cfg_rx0_pma_cdr_cp_i = 4'b0000;
+    parameter cfg_rx0_pma_clk_pos_i = 1'b0;
+    parameter cfg_rx0_pma_coarse_ppm_i = 3'b000;
+    parameter cfg_rx0_pma_ctrl_term_i = 6'b000000;
+    parameter cfg_rx0_pma_dco_divl_i = 2'b00;
+    parameter cfg_rx0_pma_dco_divm_i = 1'b0;
+    parameter cfg_rx0_pma_dco_divn_i = 2'b00;
+    parameter cfg_rx0_pma_dco_reg_res_i = 2'b00;
+    parameter cfg_rx0_pma_dco_vref_sel_i = 1'b0;
+    parameter cfg_rx0_pma_fine_ppm_i = 3'b000;
+    parameter cfg_rx0_pma_loopback_i = 1'b0;
+    parameter cfg_rx0_pma_m_eye_ppm_i = 3'b000;
+    parameter cfg_rx0_pma_peak_detect_cmd_i = 2'b00;
+    parameter cfg_rx0_pma_peak_detect_on_i = 1'b0;
+    parameter cfg_rx0_pma_pll_cpump_n_i = 3'b000;
+    parameter cfg_rx0_pma_pll_divf_en_n_i = 1'b0;
+    parameter cfg_rx0_pma_pll_divf_i = 2'b00;
+    parameter cfg_rx0_pma_pll_divm_en_n_i = 1'b0;
+    parameter cfg_rx0_pma_pll_divm_i = 2'b00;
+    parameter cfg_rx0_pma_pll_divn_en_n_i = 1'b0;
+    parameter cfg_rx0_pma_pll_divn_i = 1'b0;
+    parameter cfg_rx1_gearbox_en_i = 1'b0;
+    parameter cfg_rx1_gearbox_mode_i = 1'b0;
+    parameter cfg_rx1_pcs_8b_dscr_sel_i = 1'b0;
+    parameter cfg_rx1_pcs_align_bypass_i = 1'b0;
+    parameter cfg_rx1_pcs_buffers_bypass_i = 1'b0;
+    parameter cfg_rx1_pcs_buffers_use_cdc_i = 1'b0;
+    parameter cfg_rx1_pcs_bypass_pma_cdc_i = 1'b0;
+    parameter cfg_rx1_pcs_bypass_usr_cdc_i = 1'b0;
+    parameter cfg_rx1_pcs_comma_mask_i = 10'b0000000000;
+    parameter cfg_rx1_pcs_debug_en_i = 1'b0;
+    parameter cfg_rx1_pcs_dec_bypass_i = 1'b0;
+    parameter cfg_rx1_pcs_dscr_bypass_i = 1'b0;
+    parameter cfg_rx1_pcs_el_buff_diff_bef_comp_i = 4'b0000;
+    parameter cfg_rx1_pcs_el_buff_max_comp_i = 4'b0000;
+    parameter cfg_rx1_pcs_el_buff_only_one_skp_i = 1'b0;
+    parameter cfg_rx1_pcs_el_buff_skp_char_0_i = 9'b000000000;
+    parameter cfg_rx1_pcs_el_buff_skp_char_1_i = 9'b000000000;
+    parameter cfg_rx1_pcs_el_buff_skp_char_2_i = 9'b000000000;
+    parameter cfg_rx1_pcs_el_buff_skp_char_3_i = 9'b000000000;
+    parameter cfg_rx1_pcs_el_buff_skp_header_0_i = 9'b000000000;
+    parameter cfg_rx1_pcs_el_buff_skp_header_1_i = 9'b000000000;
+    parameter cfg_rx1_pcs_el_buff_skp_header_2_i = 9'b000000000;
+    parameter cfg_rx1_pcs_el_buff_skp_header_3_i = 9'b000000000;
+    parameter cfg_rx1_pcs_el_buff_skp_header_size_i = 2'b00;
+    parameter cfg_rx1_pcs_el_buff_skp_seq_size_i = 2'b00;
+    parameter cfg_rx1_pcs_fsm_sel_i = 2'b00;
+    parameter cfg_rx1_pcs_fsm_watchdog_en_i = 1'b0;
+    parameter cfg_rx1_pcs_loopback_i = 1'b0;
+    parameter cfg_rx1_pcs_m_comma_en_i = 1'b0;
+    parameter cfg_rx1_pcs_m_comma_val_i = 10'b0000000000;
+    parameter cfg_rx1_pcs_nb_comma_bef_realign_i = 2'b00;
+    parameter cfg_rx1_pcs_p_comma_en_i = 1'b0;
+    parameter cfg_rx1_pcs_p_comma_val_i = 10'b0000000000;
+    parameter cfg_rx1_pcs_polarity_i = 1'b0;
+    parameter cfg_rx1_pcs_protocol_size_i = 1'b0;
+    parameter cfg_rx1_pcs_replace_bypass_i = 1'b0;
+    parameter cfg_rx1_pcs_sync_supported_i = 1'b0;
+    parameter cfg_rx1_pma_cdr_cp_i = 4'b0000;
+    parameter cfg_rx1_pma_clk_pos_i = 1'b0;
+    parameter cfg_rx1_pma_coarse_ppm_i = 3'b000;
+    parameter cfg_rx1_pma_ctrl_term_i = 6'b000000;
+    parameter cfg_rx1_pma_dco_divl_i = 2'b00;
+    parameter cfg_rx1_pma_dco_divm_i = 1'b0;
+    parameter cfg_rx1_pma_dco_divn_i = 2'b00;
+    parameter cfg_rx1_pma_dco_reg_res_i = 2'b00;
+    parameter cfg_rx1_pma_dco_vref_sel_i = 1'b0;
+    parameter cfg_rx1_pma_fine_ppm_i = 3'b000;
+    parameter cfg_rx1_pma_loopback_i = 1'b0;
+    parameter cfg_rx1_pma_m_eye_ppm_i = 3'b000;
+    parameter cfg_rx1_pma_peak_detect_cmd_i = 2'b00;
+    parameter cfg_rx1_pma_peak_detect_on_i = 1'b0;
+    parameter cfg_rx1_pma_pll_cpump_n_i = 3'b000;
+    parameter cfg_rx1_pma_pll_divf_en_n_i = 1'b0;
+    parameter cfg_rx1_pma_pll_divf_i = 2'b00;
+    parameter cfg_rx1_pma_pll_divm_en_n_i = 1'b0;
+    parameter cfg_rx1_pma_pll_divm_i = 2'b00;
+    parameter cfg_rx1_pma_pll_divn_en_n_i = 1'b0;
+    parameter cfg_rx1_pma_pll_divn_i = 1'b0;
+    parameter cfg_rx2_gearbox_en_i = 1'b0;
+    parameter cfg_rx2_gearbox_mode_i = 1'b0;
+    parameter cfg_rx2_pcs_8b_dscr_sel_i = 1'b0;
+    parameter cfg_rx2_pcs_align_bypass_i = 1'b0;
+    parameter cfg_rx2_pcs_buffers_bypass_i = 1'b0;
+    parameter cfg_rx2_pcs_buffers_use_cdc_i = 1'b0;
+    parameter cfg_rx2_pcs_bypass_pma_cdc_i = 1'b0;
+    parameter cfg_rx2_pcs_bypass_usr_cdc_i = 1'b0;
+    parameter cfg_rx2_pcs_comma_mask_i = 10'b0000000000;
+    parameter cfg_rx2_pcs_debug_en_i = 1'b0;
+    parameter cfg_rx2_pcs_dec_bypass_i = 1'b0;
+    parameter cfg_rx2_pcs_dscr_bypass_i = 1'b0;
+    parameter cfg_rx2_pcs_el_buff_diff_bef_comp_i = 4'b0000;
+    parameter cfg_rx2_pcs_el_buff_max_comp_i = 4'b0000;
+    parameter cfg_rx2_pcs_el_buff_only_one_skp_i = 1'b0;
+    parameter cfg_rx2_pcs_el_buff_skp_char_0_i = 9'b000000000;
+    parameter cfg_rx2_pcs_el_buff_skp_char_1_i = 9'b000000000;
+    parameter cfg_rx2_pcs_el_buff_skp_char_2_i = 9'b000000000;
+    parameter cfg_rx2_pcs_el_buff_skp_char_3_i = 9'b000000000;
+    parameter cfg_rx2_pcs_el_buff_skp_header_0_i = 9'b000000000;
+    parameter cfg_rx2_pcs_el_buff_skp_header_1_i = 9'b000000000;
+    parameter cfg_rx2_pcs_el_buff_skp_header_2_i = 9'b000000000;
+    parameter cfg_rx2_pcs_el_buff_skp_header_3_i = 9'b000000000;
+    parameter cfg_rx2_pcs_el_buff_skp_header_size_i = 2'b00;
+    parameter cfg_rx2_pcs_el_buff_skp_seq_size_i = 2'b00;
+    parameter cfg_rx2_pcs_fsm_sel_i = 2'b00;
+    parameter cfg_rx2_pcs_fsm_watchdog_en_i = 1'b0;
+    parameter cfg_rx2_pcs_loopback_i = 1'b0;
+    parameter cfg_rx2_pcs_m_comma_en_i = 1'b0;
+    parameter cfg_rx2_pcs_m_comma_val_i = 10'b0000000000;
+    parameter cfg_rx2_pcs_nb_comma_bef_realign_i = 2'b00;
+    parameter cfg_rx2_pcs_p_comma_en_i = 1'b0;
+    parameter cfg_rx2_pcs_p_comma_val_i = 10'b0000000000;
+    parameter cfg_rx2_pcs_polarity_i = 1'b0;
+    parameter cfg_rx2_pcs_protocol_size_i = 1'b0;
+    parameter cfg_rx2_pcs_replace_bypass_i = 1'b0;
+    parameter cfg_rx2_pcs_sync_supported_i = 1'b0;
+    parameter cfg_rx2_pma_cdr_cp_i = 4'b0000;
+    parameter cfg_rx2_pma_clk_pos_i = 1'b0;
+    parameter cfg_rx2_pma_coarse_ppm_i = 3'b000;
+    parameter cfg_rx2_pma_ctrl_term_i = 6'b000000;
+    parameter cfg_rx2_pma_dco_divl_i = 2'b00;
+    parameter cfg_rx2_pma_dco_divm_i = 1'b0;
+    parameter cfg_rx2_pma_dco_divn_i = 2'b00;
+    parameter cfg_rx2_pma_dco_reg_res_i = 2'b00;
+    parameter cfg_rx2_pma_dco_vref_sel_i = 1'b0;
+    parameter cfg_rx2_pma_fine_ppm_i = 3'b000;
+    parameter cfg_rx2_pma_loopback_i = 1'b0;
+    parameter cfg_rx2_pma_m_eye_ppm_i = 3'b000;
+    parameter cfg_rx2_pma_peak_detect_cmd_i = 2'b00;
+    parameter cfg_rx2_pma_peak_detect_on_i = 1'b0;
+    parameter cfg_rx2_pma_pll_cpump_n_i = 3'b000;
+    parameter cfg_rx2_pma_pll_divf_en_n_i = 1'b0;
+    parameter cfg_rx2_pma_pll_divf_i = 2'b00;
+    parameter cfg_rx2_pma_pll_divm_en_n_i = 1'b0;
+    parameter cfg_rx2_pma_pll_divm_i = 2'b00;
+    parameter cfg_rx2_pma_pll_divn_en_n_i = 1'b0;
+    parameter cfg_rx2_pma_pll_divn_i = 1'b0;
+    parameter cfg_rx3_gearbox_en_i = 1'b0;
+    parameter cfg_rx3_gearbox_mode_i = 1'b0;
+    parameter cfg_rx3_pcs_8b_dscr_sel_i = 1'b0;
+    parameter cfg_rx3_pcs_align_bypass_i = 1'b0;
+    parameter cfg_rx3_pcs_buffers_bypass_i = 1'b0;
+    parameter cfg_rx3_pcs_buffers_use_cdc_i = 1'b0;
+    parameter cfg_rx3_pcs_bypass_pma_cdc_i = 1'b0;
+    parameter cfg_rx3_pcs_bypass_usr_cdc_i = 1'b0;
+    parameter cfg_rx3_pcs_comma_mask_i = 10'b0000000000;
+    parameter cfg_rx3_pcs_debug_en_i = 1'b0;
+    parameter cfg_rx3_pcs_dec_bypass_i = 1'b0;
+    parameter cfg_rx3_pcs_dscr_bypass_i = 1'b0;
+    parameter cfg_rx3_pcs_el_buff_diff_bef_comp_i = 4'b0000;
+    parameter cfg_rx3_pcs_el_buff_max_comp_i = 4'b0000;
+    parameter cfg_rx3_pcs_el_buff_only_one_skp_i = 1'b0;
+    parameter cfg_rx3_pcs_el_buff_skp_char_0_i = 9'b000000000;
+    parameter cfg_rx3_pcs_el_buff_skp_char_1_i = 9'b000000000;
+    parameter cfg_rx3_pcs_el_buff_skp_char_2_i = 9'b000000000;
+    parameter cfg_rx3_pcs_el_buff_skp_char_3_i = 9'b000000000;
+    parameter cfg_rx3_pcs_el_buff_skp_header_0_i = 9'b000000000;
+    parameter cfg_rx3_pcs_el_buff_skp_header_1_i = 9'b000000000;
+    parameter cfg_rx3_pcs_el_buff_skp_header_2_i = 9'b000000000;
+    parameter cfg_rx3_pcs_el_buff_skp_header_3_i = 9'b000000000;
+    parameter cfg_rx3_pcs_el_buff_skp_header_size_i = 2'b00;
+    parameter cfg_rx3_pcs_el_buff_skp_seq_size_i = 2'b00;
+    parameter cfg_rx3_pcs_fsm_sel_i = 2'b00;
+    parameter cfg_rx3_pcs_fsm_watchdog_en_i = 1'b0;
+    parameter cfg_rx3_pcs_loopback_i = 1'b0;
+    parameter cfg_rx3_pcs_m_comma_en_i = 1'b0;
+    parameter cfg_rx3_pcs_m_comma_val_i = 10'b0000000000;
+    parameter cfg_rx3_pcs_nb_comma_bef_realign_i = 2'b00;
+    parameter cfg_rx3_pcs_p_comma_en_i = 1'b0;
+    parameter cfg_rx3_pcs_p_comma_val_i = 10'b0000000000;
+    parameter cfg_rx3_pcs_polarity_i = 1'b0;
+    parameter cfg_rx3_pcs_protocol_size_i = 1'b0;
+    parameter cfg_rx3_pcs_replace_bypass_i = 1'b0;
+    parameter cfg_rx3_pcs_sync_supported_i = 1'b0;
+    parameter cfg_rx3_pma_cdr_cp_i = 4'b0000;
+    parameter cfg_rx3_pma_clk_pos_i = 1'b0;
+    parameter cfg_rx3_pma_coarse_ppm_i = 3'b000;
+    parameter cfg_rx3_pma_ctrl_term_i = 6'b000000;
+    parameter cfg_rx3_pma_dco_divl_i = 2'b00;
+    parameter cfg_rx3_pma_dco_divm_i = 1'b0;
+    parameter cfg_rx3_pma_dco_divn_i = 2'b00;
+    parameter cfg_rx3_pma_dco_reg_res_i = 2'b00;
+    parameter cfg_rx3_pma_dco_vref_sel_i = 1'b0;
+    parameter cfg_rx3_pma_fine_ppm_i = 3'b000;
+    parameter cfg_rx3_pma_loopback_i = 1'b0;
+    parameter cfg_rx3_pma_m_eye_ppm_i = 3'b000;
+    parameter cfg_rx3_pma_peak_detect_cmd_i = 2'b00;
+    parameter cfg_rx3_pma_peak_detect_on_i = 1'b0;
+    parameter cfg_rx3_pma_pll_cpump_n_i = 3'b000;
+    parameter cfg_rx3_pma_pll_divf_en_n_i = 1'b0;
+    parameter cfg_rx3_pma_pll_divf_i = 2'b00;
+    parameter cfg_rx3_pma_pll_divm_en_n_i = 1'b0;
+    parameter cfg_rx3_pma_pll_divm_i = 2'b00;
+    parameter cfg_rx3_pma_pll_divn_en_n_i = 1'b0;
+    parameter cfg_rx3_pma_pll_divn_i = 1'b0;
+    parameter cfg_test_mode_i = 2'b00;
+    parameter cfg_tx0_gearbox_en_i = 1'b0;
+    parameter cfg_tx0_gearbox_mode_i = 1'b0;
+    parameter cfg_tx0_pcs_8b_scr_sel_i = 1'b0;
+    parameter cfg_tx0_pcs_bypass_pma_cdc_i = 1'b0;
+    parameter cfg_tx0_pcs_bypass_usr_cdc_i = 1'b0;
+    parameter cfg_tx0_pcs_enc_bypass_i = 1'b0;
+    parameter cfg_tx0_pcs_esistream_fsm_en_i = 1'b0;
+    parameter cfg_tx0_pcs_loopback_i = 1'b0;
+    parameter cfg_tx0_pcs_polarity_i = 1'b0;
+    parameter cfg_tx0_pcs_protocol_size_i = 1'b0;
+    parameter cfg_tx0_pcs_replace_bypass_i = 1'b0;
+    parameter cfg_tx0_pcs_scr_bypass_i = 1'b0;
+    parameter cfg_tx0_pcs_scr_init_i = 17'b00000000000000000;
+    parameter cfg_tx0_pcs_sync_supported_i = 1'b0;
+    parameter cfg_tx0_pma_clk_pos_i = 1'b0;
+    parameter cfg_tx0_pma_loopback_i = 1'b0;
+    parameter cfg_tx1_gearbox_en_i = 1'b0;
+    parameter cfg_tx1_gearbox_mode_i = 1'b0;
+    parameter cfg_tx1_pcs_8b_scr_sel_i = 1'b0;
+    parameter cfg_tx1_pcs_bypass_pma_cdc_i = 1'b0;
+    parameter cfg_tx1_pcs_bypass_usr_cdc_i = 1'b0;
+    parameter cfg_tx1_pcs_enc_bypass_i = 1'b0;
+    parameter cfg_tx1_pcs_esistream_fsm_en_i = 1'b0;
+    parameter cfg_tx1_pcs_loopback_i = 1'b0;
+    parameter cfg_tx1_pcs_polarity_i = 1'b0;
+    parameter cfg_tx1_pcs_protocol_size_i = 1'b0;
+    parameter cfg_tx1_pcs_replace_bypass_i = 1'b0;
+    parameter cfg_tx1_pcs_scr_bypass_i = 1'b0;
+    parameter cfg_tx1_pcs_scr_init_i = 17'b00000000000000000;
+    parameter cfg_tx1_pcs_sync_supported_i = 1'b0;
+    parameter cfg_tx1_pma_clk_pos_i = 1'b0;
+    parameter cfg_tx1_pma_loopback_i = 1'b0;
+    parameter cfg_tx2_gearbox_en_i = 1'b0;
+    parameter cfg_tx2_gearbox_mode_i = 1'b0;
+    parameter cfg_tx2_pcs_8b_scr_sel_i = 1'b0;
+    parameter cfg_tx2_pcs_bypass_pma_cdc_i = 1'b0;
+    parameter cfg_tx2_pcs_bypass_usr_cdc_i = 1'b0;
+    parameter cfg_tx2_pcs_enc_bypass_i = 1'b0;
+    parameter cfg_tx2_pcs_esistream_fsm_en_i = 1'b0;
+    parameter cfg_tx2_pcs_loopback_i = 1'b0;
+    parameter cfg_tx2_pcs_polarity_i = 1'b0;
+    parameter cfg_tx2_pcs_protocol_size_i = 1'b0;
+    parameter cfg_tx2_pcs_replace_bypass_i = 1'b0;
+    parameter cfg_tx2_pcs_scr_bypass_i = 1'b0;
+    parameter cfg_tx2_pcs_scr_init_i = 17'b00000000000000000;
+    parameter cfg_tx2_pcs_sync_supported_i = 1'b0;
+    parameter cfg_tx2_pma_clk_pos_i = 1'b0;
+    parameter cfg_tx2_pma_loopback_i = 1'b0;
+    parameter cfg_tx3_gearbox_en_i = 1'b0;
+    parameter cfg_tx3_gearbox_mode_i = 1'b0;
+    parameter cfg_tx3_pcs_8b_scr_sel_i = 1'b0;
+    parameter cfg_tx3_pcs_bypass_pma_cdc_i = 1'b0;
+    parameter cfg_tx3_pcs_bypass_usr_cdc_i = 1'b0;
+    parameter cfg_tx3_pcs_enc_bypass_i = 1'b0;
+    parameter cfg_tx3_pcs_esistream_fsm_en_i = 1'b0;
+    parameter cfg_tx3_pcs_loopback_i = 1'b0;
+    parameter cfg_tx3_pcs_polarity_i = 1'b0;
+    parameter cfg_tx3_pcs_protocol_size_i = 1'b0;
+    parameter cfg_tx3_pcs_replace_bypass_i = 1'b0;
+    parameter cfg_tx3_pcs_scr_bypass_i = 1'b0;
+    parameter cfg_tx3_pcs_scr_init_i = 17'b00000000000000000;
+    parameter cfg_tx3_pcs_sync_supported_i = 1'b0;
+    parameter cfg_tx3_pma_clk_pos_i = 1'b0;
+    parameter cfg_tx3_pma_loopback_i = 1'b0;
+    parameter location = "";
+    parameter rx_usrclk_use_pcs_clk_2 = 1'b0;
+    parameter tx_usrclk_use_pcs_clk_2 = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_IOB(I, C, T, O, IO);
+    input C;
+    input I;
+    inout IO;
+    output O;
+    input T;
+    parameter differential = "";
+    parameter drive = "";
+    parameter dynDrive = "";
+    parameter dynInput = "";
+    parameter dynTerm = "";
+    parameter extra = 3;
+    parameter inputDelayLine = "";
+    parameter inputDelayOn = "";
+    parameter inputSignalSlope = "";
+    parameter location = "";
+    parameter locked = 1'b0;
+    parameter outputCapacity = "";
+    parameter outputDelayLine = "";
+    parameter outputDelayOn = "";
+    parameter slewRate = "";
+    parameter standard = "";
+    parameter termination = "";
+    parameter terminationReference = "";
+    parameter turbo = "";
+    parameter weakTermination = "";
+endmodule
+
+(* blackbox *)
+module NX_IOB_I(C, T, IO, O);
+    input C;
+    input IO;
+    output O;
+    input T;
+    parameter differential = "";
+    parameter drive = "";
+    parameter dynDrive = "";
+    parameter dynInput = "";
+    parameter dynTerm = "";
+    parameter extra = 1;
+    parameter inputDelayLine = "";
+    parameter inputDelayOn = "";
+    parameter inputSignalSlope = "";
+    parameter location = "";
+    parameter locked = 1'b0;
+    parameter outputCapacity = "";
+    parameter outputDelayLine = "";
+    parameter outputDelayOn = "";
+    parameter slewRate = "";
+    parameter standard = "";
+    parameter termination = "";
+    parameter terminationReference = "";
+    parameter turbo = "";
+    parameter weakTermination = "";
+endmodule
+
+(* blackbox *)
+module NX_IOB_O(I, C, T, IO);
+    input C;
+    input I;
+    output IO;
+    input T;
+    parameter differential = "";
+    parameter drive = "";
+    parameter dynDrive = "";
+    parameter dynInput = "";
+    parameter dynTerm = "";
+    parameter extra = 2;
+    parameter inputDelayLine = "";
+    parameter inputDelayOn = "";
+    parameter inputSignalSlope = "";
+    parameter location = "";
+    parameter locked = 1'b0;
+    parameter outputCapacity = "";
+    parameter outputDelayLine = "";
+    parameter outputDelayOn = "";
+    parameter slewRate = "";
+    parameter standard = "";
+    parameter termination = "";
+    parameter terminationReference = "";
+    parameter turbo = "";
+    parameter weakTermination = "";
+endmodule
+
+(* blackbox *)
+module NX_IOM(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, CCK, DCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1
+, C2RW2, C2RW3, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FZ, DC, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4
+, DRA5, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1, CAP2, CAP3
+, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3
+, DRO4, DRO5, DRO6, CAL, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EL, P1ER, P1EO, P1RI, P1RL, P1RR
+, P1RO1, P1RO2, P1RO3, P1RO4, P1RO5, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EL, P2ER, P2EO, P2RI, P2RL
+, P2RR, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P3CI1, P3CL, P3CR, P3CO, P3CTI, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EL, P3ER, P3EO, P3RI
+, P3RL, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EL, P4ER, P4EO
+, P4RI, P4RL, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P5CI1, P5CI2, P5CI3, P5CI4, P5CI5, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3
+, P5EI4, P5EI5, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P6CI1, P6CL, P6CR, P6CO, P6CTI, P6CTO, P6EI1, P6EI2
+, P6EI3, P6EI4, P6EI5, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1
+, P7EI2, P7EI3, P7EI4, P7EI5, P7EL, P7ER, P7EO, P7RI, P7RL, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO
+, P8EI1, P8EI2, P8EI3, P8EI4, P8EI5, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P9CI1, P9CL, P9CR, P9CO, P9CTI
+, P9CTO, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P10CI1, P10CL, P10CR, P10CO
+, P10CTI, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EL, P10ER, P10EO, P10RI, P10RL, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P11CI1, P11CL, P11CR
+, P11CO, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P12CI1, P12CL
+, P12CR, P12CO, P12CTI, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P13CI1
+, P13CL, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EL, P13ER, P13EO, P13RI, P13RL, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5
+, P14CI1, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4
+, P14RO5, P15CI1, P15CL, P15CR, P15CO, P15CTI, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3
+, P15RO4, P15RO5, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EL, P16ER, P16EO, P16RI, P16RL, P16RR, P16RO1, P16RO2
+, P16RO3, P16RO4, P16RO5, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1
+, P17RO2, P17RO3, P17RO4, P17RO5, P18CI1, P18CL, P18CR, P18CO, P18CTI, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR
+, P18RO1, P18RO2, P18RO3, P18RO4, P18RO5, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EL, P19ER, P19EO, P19RI, P19RL
+, P19RR, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EL, P20ER, P20EO, P20RI
+, P20RL, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P21CI1, P21CL, P21CR, P21CO, P21CTI, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EL, P21ER, P21EO
+, P21RI, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EL, P22ER
+, P22EO, P22RI, P22RL, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EL
+, P23ER, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P24CI1, P24CL, P24CR, P24CO, P24CTI, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5
+, P24EL, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P25CI1, P25CI2, P25CI3, P25CI4, P25CI5, P25CL, P25CR, P25CO, P25CTI, P25CTO
+, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5, P25EL, P25ER, P25EO, P25RI, P25RL, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P26CI1, P26CL, P26CR, P26CO, P26CTI
+, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4, P26EI5, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P27CI1, P27CL, P27CR, P27CO
+, P27CTI, P27CTO, P27EI1, P27EI2, P27EI3, P27EI4, P27EI5, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P28CI1, P28CL, P28CR
+, P28CO, P28CTI, P28CTO, P28EI1, P28EI2, P28EI3, P28EI4, P28EI5, P28EL, P28ER, P28EO, P28RI, P28RL, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P29CI1, P29CL
+, P29CR, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P30CI1
+, P30CL, P30CR, P30CO, P30CTI, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5
+);
+    output C1RED;
+    input C1RNE;
+    input C1RS;
+    input C1RW1;
+    input C1RW2;
+    input C1RW3;
+    input C1TS;
+    input C1TW;
+    output C2RED;
+    input C2RNE;
+    input C2RS;
+    input C2RW1;
+    input C2RW2;
+    input C2RW3;
+    input C2TS;
+    input C2TW;
+    input CAD1;
+    input CAD2;
+    input CAD3;
+    input CAD4;
+    input CAD5;
+    input CAD6;
+    output CAL;
+    input CAN1;
+    input CAN2;
+    input CAN3;
+    input CAN4;
+    input CAP1;
+    input CAP2;
+    input CAP3;
+    input CAP4;
+    input CAT1;
+    input CAT2;
+    input CAT3;
+    input CAT4;
+    input CCK;
+    output CKO1;
+    output CKO2;
+    input CTCK;
+    input DC;
+    input DCK;
+    input DIG;
+    input DIS;
+    input DOG;
+    input DOS;
+    input DPAG;
+    input DPAS;
+    input DQSG;
+    input DQSS;
+    input DRA1;
+    input DRA2;
+    input DRA3;
+    input DRA4;
+    input DRA5;
+    input DRI1;
+    input DRI2;
+    input DRI3;
+    input DRI4;
+    input DRI5;
+    input DRI6;
+    input DRL;
+    output DRO1;
+    output DRO2;
+    output DRO3;
+    output DRO4;
+    output DRO5;
+    output DRO6;
+    input DS1;
+    input DS2;
+    input FA1;
+    input FA2;
+    input FA3;
+    input FA4;
+    input FA5;
+    output FLD;
+    output FLG;
+    input FZ;
+    input P10CI1;
+    input P10CL;
+    output P10CO;
+    input P10CR;
+    input P10CTI;
+    output P10CTO;
+    input P10EI1;
+    input P10EI2;
+    input P10EI3;
+    input P10EI4;
+    input P10EI5;
+    input P10EL;
+    output P10EO;
+    input P10ER;
+    input P10RI;
+    input P10RL;
+    output P10RO1;
+    output P10RO2;
+    output P10RO3;
+    output P10RO4;
+    output P10RO5;
+    input P10RR;
+    input P11CI1;
+    input P11CL;
+    output P11CO;
+    input P11CR;
+    input P11CTI;
+    output P11CTO;
+    input P11EI1;
+    input P11EI2;
+    input P11EI3;
+    input P11EI4;
+    input P11EI5;
+    input P11EL;
+    output P11EO;
+    input P11ER;
+    input P11RI;
+    input P11RL;
+    output P11RO1;
+    output P11RO2;
+    output P11RO3;
+    output P11RO4;
+    output P11RO5;
+    input P11RR;
+    input P12CI1;
+    input P12CL;
+    output P12CO;
+    input P12CR;
+    input P12CTI;
+    output P12CTO;
+    input P12EI1;
+    input P12EI2;
+    input P12EI3;
+    input P12EI4;
+    input P12EI5;
+    input P12EL;
+    output P12EO;
+    input P12ER;
+    input P12RI;
+    input P12RL;
+    output P12RO1;
+    output P12RO2;
+    output P12RO3;
+    output P12RO4;
+    output P12RO5;
+    input P12RR;
+    input P13CI1;
+    input P13CL;
+    output P13CO;
+    input P13CR;
+    input P13CTI;
+    output P13CTO;
+    input P13EI1;
+    input P13EI2;
+    input P13EI3;
+    input P13EI4;
+    input P13EI5;
+    input P13EL;
+    output P13EO;
+    input P13ER;
+    input P13RI;
+    input P13RL;
+    output P13RO1;
+    output P13RO2;
+    output P13RO3;
+    output P13RO4;
+    output P13RO5;
+    input P13RR;
+    input P14CI1;
+    input P14CL;
+    output P14CO;
+    input P14CR;
+    input P14CTI;
+    output P14CTO;
+    input P14EI1;
+    input P14EI2;
+    input P14EI3;
+    input P14EI4;
+    input P14EI5;
+    input P14EL;
+    output P14EO;
+    input P14ER;
+    input P14RI;
+    input P14RL;
+    output P14RO1;
+    output P14RO2;
+    output P14RO3;
+    output P14RO4;
+    output P14RO5;
+    input P14RR;
+    input P15CI1;
+    input P15CL;
+    output P15CO;
+    input P15CR;
+    input P15CTI;
+    output P15CTO;
+    input P15EI1;
+    input P15EI2;
+    input P15EI3;
+    input P15EI4;
+    input P15EI5;
+    input P15EL;
+    output P15EO;
+    input P15ER;
+    input P15RI;
+    input P15RL;
+    output P15RO1;
+    output P15RO2;
+    output P15RO3;
+    output P15RO4;
+    output P15RO5;
+    input P15RR;
+    input P16CI1;
+    input P16CL;
+    output P16CO;
+    input P16CR;
+    input P16CTI;
+    output P16CTO;
+    input P16EI1;
+    input P16EI2;
+    input P16EI3;
+    input P16EI4;
+    input P16EI5;
+    input P16EL;
+    output P16EO;
+    input P16ER;
+    input P16RI;
+    input P16RL;
+    output P16RO1;
+    output P16RO2;
+    output P16RO3;
+    output P16RO4;
+    output P16RO5;
+    input P16RR;
+    input P17CI1;
+    input P17CL;
+    output P17CO;
+    input P17CR;
+    input P17CTI;
+    output P17CTO;
+    input P17EI1;
+    input P17EI2;
+    input P17EI3;
+    input P17EI4;
+    input P17EI5;
+    input P17EL;
+    output P17EO;
+    input P17ER;
+    input P17RI;
+    input P17RL;
+    output P17RO1;
+    output P17RO2;
+    output P17RO3;
+    output P17RO4;
+    output P17RO5;
+    input P17RR;
+    input P18CI1;
+    input P18CL;
+    output P18CO;
+    input P18CR;
+    input P18CTI;
+    output P18CTO;
+    input P18EI1;
+    input P18EI2;
+    input P18EI3;
+    input P18EI4;
+    input P18EI5;
+    input P18EL;
+    output P18EO;
+    input P18ER;
+    input P18RI;
+    input P18RL;
+    output P18RO1;
+    output P18RO2;
+    output P18RO3;
+    output P18RO4;
+    output P18RO5;
+    input P18RR;
+    input P19CI1;
+    input P19CL;
+    output P19CO;
+    input P19CR;
+    input P19CTI;
+    output P19CTO;
+    input P19EI1;
+    input P19EI2;
+    input P19EI3;
+    input P19EI4;
+    input P19EI5;
+    input P19EL;
+    output P19EO;
+    input P19ER;
+    input P19RI;
+    input P19RL;
+    output P19RO1;
+    output P19RO2;
+    output P19RO3;
+    output P19RO4;
+    output P19RO5;
+    input P19RR;
+    input P1CI1;
+    input P1CL;
+    output P1CO;
+    input P1CR;
+    input P1CTI;
+    output P1CTO;
+    input P1EI1;
+    input P1EI2;
+    input P1EI3;
+    input P1EI4;
+    input P1EI5;
+    input P1EL;
+    output P1EO;
+    input P1ER;
+    input P1RI;
+    input P1RL;
+    output P1RO1;
+    output P1RO2;
+    output P1RO3;
+    output P1RO4;
+    output P1RO5;
+    input P1RR;
+    input P20CI1;
+    input P20CL;
+    output P20CO;
+    input P20CR;
+    input P20CTI;
+    output P20CTO;
+    input P20EI1;
+    input P20EI2;
+    input P20EI3;
+    input P20EI4;
+    input P20EI5;
+    input P20EL;
+    output P20EO;
+    input P20ER;
+    input P20RI;
+    input P20RL;
+    output P20RO1;
+    output P20RO2;
+    output P20RO3;
+    output P20RO4;
+    output P20RO5;
+    input P20RR;
+    input P21CI1;
+    input P21CL;
+    output P21CO;
+    input P21CR;
+    input P21CTI;
+    output P21CTO;
+    input P21EI1;
+    input P21EI2;
+    input P21EI3;
+    input P21EI4;
+    input P21EI5;
+    input P21EL;
+    output P21EO;
+    input P21ER;
+    input P21RI;
+    input P21RL;
+    output P21RO1;
+    output P21RO2;
+    output P21RO3;
+    output P21RO4;
+    output P21RO5;
+    input P21RR;
+    input P22CI1;
+    input P22CL;
+    output P22CO;
+    input P22CR;
+    input P22CTI;
+    output P22CTO;
+    input P22EI1;
+    input P22EI2;
+    input P22EI3;
+    input P22EI4;
+    input P22EI5;
+    input P22EL;
+    output P22EO;
+    input P22ER;
+    input P22RI;
+    input P22RL;
+    output P22RO1;
+    output P22RO2;
+    output P22RO3;
+    output P22RO4;
+    output P22RO5;
+    input P22RR;
+    input P23CI1;
+    input P23CL;
+    output P23CO;
+    input P23CR;
+    input P23CTI;
+    output P23CTO;
+    input P23EI1;
+    input P23EI2;
+    input P23EI3;
+    input P23EI4;
+    input P23EI5;
+    input P23EL;
+    output P23EO;
+    input P23ER;
+    input P23RI;
+    input P23RL;
+    output P23RO1;
+    output P23RO2;
+    output P23RO3;
+    output P23RO4;
+    output P23RO5;
+    input P23RR;
+    input P24CI1;
+    input P24CL;
+    output P24CO;
+    input P24CR;
+    input P24CTI;
+    output P24CTO;
+    input P24EI1;
+    input P24EI2;
+    input P24EI3;
+    input P24EI4;
+    input P24EI5;
+    input P24EL;
+    output P24EO;
+    input P24ER;
+    input P24RI;
+    input P24RL;
+    output P24RO1;
+    output P24RO2;
+    output P24RO3;
+    output P24RO4;
+    output P24RO5;
+    input P24RR;
+    input P25CI1;
+    input P25CI2;
+    input P25CI3;
+    input P25CI4;
+    input P25CI5;
+    input P25CL;
+    output P25CO;
+    input P25CR;
+    input P25CTI;
+    output P25CTO;
+    input P25EI1;
+    input P25EI2;
+    input P25EI3;
+    input P25EI4;
+    input P25EI5;
+    input P25EL;
+    output P25EO;
+    input P25ER;
+    input P25RI;
+    input P25RL;
+    output P25RO1;
+    output P25RO2;
+    output P25RO3;
+    output P25RO4;
+    output P25RO5;
+    input P25RR;
+    input P26CI1;
+    input P26CL;
+    output P26CO;
+    input P26CR;
+    input P26CTI;
+    output P26CTO;
+    input P26EI1;
+    input P26EI2;
+    input P26EI3;
+    input P26EI4;
+    input P26EI5;
+    input P26EL;
+    output P26EO;
+    input P26ER;
+    input P26RI;
+    input P26RL;
+    output P26RO1;
+    output P26RO2;
+    output P26RO3;
+    output P26RO4;
+    output P26RO5;
+    input P26RR;
+    input P27CI1;
+    input P27CL;
+    output P27CO;
+    input P27CR;
+    input P27CTI;
+    output P27CTO;
+    input P27EI1;
+    input P27EI2;
+    input P27EI3;
+    input P27EI4;
+    input P27EI5;
+    input P27EL;
+    output P27EO;
+    input P27ER;
+    input P27RI;
+    input P27RL;
+    output P27RO1;
+    output P27RO2;
+    output P27RO3;
+    output P27RO4;
+    output P27RO5;
+    input P27RR;
+    input P28CI1;
+    input P28CL;
+    output P28CO;
+    input P28CR;
+    input P28CTI;
+    output P28CTO;
+    input P28EI1;
+    input P28EI2;
+    input P28EI3;
+    input P28EI4;
+    input P28EI5;
+    input P28EL;
+    output P28EO;
+    input P28ER;
+    input P28RI;
+    input P28RL;
+    output P28RO1;
+    output P28RO2;
+    output P28RO3;
+    output P28RO4;
+    output P28RO5;
+    input P28RR;
+    input P29CI1;
+    input P29CL;
+    output P29CO;
+    input P29CR;
+    input P29CTI;
+    output P29CTO;
+    input P29EI1;
+    input P29EI2;
+    input P29EI3;
+    input P29EI4;
+    input P29EI5;
+    input P29EL;
+    output P29EO;
+    input P29ER;
+    input P29RI;
+    input P29RL;
+    output P29RO1;
+    output P29RO2;
+    output P29RO3;
+    output P29RO4;
+    output P29RO5;
+    input P29RR;
+    input P2CI1;
+    input P2CL;
+    output P2CO;
+    input P2CR;
+    input P2CTI;
+    output P2CTO;
+    input P2EI1;
+    input P2EI2;
+    input P2EI3;
+    input P2EI4;
+    input P2EI5;
+    input P2EL;
+    output P2EO;
+    input P2ER;
+    input P2RI;
+    input P2RL;
+    output P2RO1;
+    output P2RO2;
+    output P2RO3;
+    output P2RO4;
+    output P2RO5;
+    input P2RR;
+    input P30CI1;
+    input P30CL;
+    output P30CO;
+    input P30CR;
+    input P30CTI;
+    output P30CTO;
+    input P30EI1;
+    input P30EI2;
+    input P30EI3;
+    input P30EI4;
+    input P30EI5;
+    input P30EL;
+    output P30EO;
+    input P30ER;
+    input P30RI;
+    input P30RL;
+    output P30RO1;
+    output P30RO2;
+    output P30RO3;
+    output P30RO4;
+    output P30RO5;
+    input P30RR;
+    input P3CI1;
+    input P3CL;
+    output P3CO;
+    input P3CR;
+    input P3CTI;
+    output P3CTO;
+    input P3EI1;
+    input P3EI2;
+    input P3EI3;
+    input P3EI4;
+    input P3EI5;
+    input P3EL;
+    output P3EO;
+    input P3ER;
+    input P3RI;
+    input P3RL;
+    output P3RO1;
+    output P3RO2;
+    output P3RO3;
+    output P3RO4;
+    output P3RO5;
+    input P3RR;
+    input P4CI1;
+    input P4CL;
+    output P4CO;
+    input P4CR;
+    input P4CTI;
+    output P4CTO;
+    input P4EI1;
+    input P4EI2;
+    input P4EI3;
+    input P4EI4;
+    input P4EI5;
+    input P4EL;
+    output P4EO;
+    input P4ER;
+    input P4RI;
+    input P4RL;
+    output P4RO1;
+    output P4RO2;
+    output P4RO3;
+    output P4RO4;
+    output P4RO5;
+    input P4RR;
+    input P5CI1;
+    input P5CI2;
+    input P5CI3;
+    input P5CI4;
+    input P5CI5;
+    input P5CL;
+    output P5CO;
+    input P5CR;
+    input P5CTI;
+    output P5CTO;
+    input P5EI1;
+    input P5EI2;
+    input P5EI3;
+    input P5EI4;
+    input P5EI5;
+    input P5EL;
+    output P5EO;
+    input P5ER;
+    input P5RI;
+    input P5RL;
+    output P5RO1;
+    output P5RO2;
+    output P5RO3;
+    output P5RO4;
+    output P5RO5;
+    input P5RR;
+    input P6CI1;
+    input P6CL;
+    output P6CO;
+    input P6CR;
+    input P6CTI;
+    output P6CTO;
+    input P6EI1;
+    input P6EI2;
+    input P6EI3;
+    input P6EI4;
+    input P6EI5;
+    input P6EL;
+    output P6EO;
+    input P6ER;
+    input P6RI;
+    input P6RL;
+    output P6RO1;
+    output P6RO2;
+    output P6RO3;
+    output P6RO4;
+    output P6RO5;
+    input P6RR;
+    input P7CI1;
+    input P7CL;
+    output P7CO;
+    input P7CR;
+    input P7CTI;
+    output P7CTO;
+    input P7EI1;
+    input P7EI2;
+    input P7EI3;
+    input P7EI4;
+    input P7EI5;
+    input P7EL;
+    output P7EO;
+    input P7ER;
+    input P7RI;
+    input P7RL;
+    output P7RO1;
+    output P7RO2;
+    output P7RO3;
+    output P7RO4;
+    output P7RO5;
+    input P7RR;
+    input P8CI1;
+    input P8CL;
+    output P8CO;
+    input P8CR;
+    input P8CTI;
+    output P8CTO;
+    input P8EI1;
+    input P8EI2;
+    input P8EI3;
+    input P8EI4;
+    input P8EI5;
+    input P8EL;
+    output P8EO;
+    input P8ER;
+    input P8RI;
+    input P8RL;
+    output P8RO1;
+    output P8RO2;
+    output P8RO3;
+    output P8RO4;
+    output P8RO5;
+    input P8RR;
+    input P9CI1;
+    input P9CL;
+    output P9CO;
+    input P9CR;
+    input P9CTI;
+    output P9CTO;
+    input P9EI1;
+    input P9EI2;
+    input P9EI3;
+    input P9EI4;
+    input P9EI5;
+    input P9EL;
+    output P9EO;
+    input P9ER;
+    input P9RI;
+    input P9RL;
+    output P9RO1;
+    output P9RO2;
+    output P9RO3;
+    output P9RO4;
+    output P9RO5;
+    input P9RR;
+    input RRCK1;
+    input RRCK2;
+    input RTCK1;
+    input RTCK2;
+    input SPI1;
+    input SPI2;
+    input SPI3;
+    input WRCK1;
+    input WRCK2;
+    input WTCK1;
+    input WTCK2;
+    parameter div_rx1 = 4'b0000;
+    parameter div_rx2 = 4'b0000;
+    parameter div_tx1 = 4'b0000;
+    parameter div_tx2 = 4'b0000;
+    parameter mode_io_cal = 1'b0;
+    parameter mode_side1 = 0;
+    parameter mode_side2 = 0;
+    parameter pads_dict = "";
+    parameter pads_path = "";
+    parameter sel_clk_out1 = 1'b0;
+    parameter sel_clk_out2 = 1'b0;
+    parameter sel_clkr_rx1 = 1'b0;
+    parameter sel_clkr_rx2 = 1'b0;
+    parameter sel_clkw_rx1 = 2'b00;
+    parameter sel_clkw_rx2 = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_IOM_BIN2GRP(GS, DS, GVON, GVIN, GVDN, PA, LA);
+    input [1:0] DS;
+    input GS;
+    output [2:0] GVDN;
+    output [2:0] GVIN;
+    output [2:0] GVON;
+    input [5:0] LA;
+    output [3:0] PA;
+endmodule
+
+(* blackbox *)
+module NX_IOM_CONTROL(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3
+, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3
+, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1
+, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1
+, DRO2, DRO3, DRO4, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16
+, LINK17, LINK18, LINK19, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);
+    output C1RED;
+    input C1RNE;
+    input C1RS;
+    input C1RW1;
+    input C1RW2;
+    input C1RW3;
+    input C1TS;
+    input C1TW;
+    output C2RED;
+    input C2RNE;
+    input C2RS;
+    input C2RW1;
+    input C2RW2;
+    input C2RW3;
+    input C2TS;
+    input C2TW;
+    input CAD1;
+    input CAD2;
+    input CAD3;
+    input CAD4;
+    input CAD5;
+    input CAD6;
+    output CAL;
+    input CAN1;
+    input CAN2;
+    input CAN3;
+    input CAN4;
+    input CAP1;
+    input CAP2;
+    input CAP3;
+    input CAP4;
+    input CAT1;
+    input CAT2;
+    input CAT3;
+    input CAT4;
+    input CCK;
+    output CKO1;
+    output CKO2;
+    input CTCK;
+    input DC;
+    input DCK;
+    input DIG;
+    input DIS;
+    input DOG;
+    input DOS;
+    input DPAG;
+    input DPAS;
+    input DQSG;
+    input DQSS;
+    input DRA1;
+    input DRA2;
+    input DRA3;
+    input DRA4;
+    input DRA5;
+    input DRA6;
+    input DRI1;
+    input DRI2;
+    input DRI3;
+    input DRI4;
+    input DRI5;
+    input DRI6;
+    input DRL;
+    output DRO1;
+    output DRO2;
+    output DRO3;
+    output DRO4;
+    output DRO5;
+    output DRO6;
+    input DS1;
+    input DS2;
+    input FA1;
+    input FA2;
+    input FA3;
+    input FA4;
+    input FA5;
+    input FA6;
+    output FLD;
+    output FLG;
+    input FZ;
+    inout [41:0] LINK1;
+    inout [41:0] LINK10;
+    inout [41:0] LINK11;
+    inout [41:0] LINK12;
+    inout [41:0] LINK13;
+    inout [41:0] LINK14;
+    inout [41:0] LINK15;
+    inout [41:0] LINK16;
+    inout [41:0] LINK17;
+    inout [41:0] LINK18;
+    inout [41:0] LINK19;
+    inout [41:0] LINK2;
+    inout [41:0] LINK20;
+    inout [41:0] LINK21;
+    inout [41:0] LINK22;
+    inout [41:0] LINK23;
+    inout [41:0] LINK24;
+    inout [41:0] LINK25;
+    inout [41:0] LINK26;
+    inout [41:0] LINK27;
+    inout [41:0] LINK28;
+    inout [41:0] LINK29;
+    inout [41:0] LINK3;
+    inout [41:0] LINK30;
+    inout [41:0] LINK31;
+    inout [41:0] LINK32;
+    inout [41:0] LINK33;
+    inout [41:0] LINK34;
+    inout [41:0] LINK4;
+    inout [41:0] LINK5;
+    inout [41:0] LINK6;
+    inout [41:0] LINK7;
+    inout [41:0] LINK8;
+    inout [41:0] LINK9;
+    input RRCK1;
+    input RRCK2;
+    input RTCK1;
+    input RTCK2;
+    input SPI1;
+    input SPI2;
+    input SPI3;
+    input WRCK1;
+    input WRCK2;
+    input WTCK1;
+    input WTCK2;
+    parameter div_rx1 = 4'b0000;
+    parameter div_rx2 = 4'b0000;
+    parameter div_tx1 = 4'b0000;
+    parameter div_tx2 = 4'b0000;
+    parameter inv_di_fclk1 = 1'b0;
+    parameter inv_di_fclk2 = 1'b0;
+    parameter latency1 = 1'b0;
+    parameter latency2 = 1'b0;
+    parameter location = "";
+    parameter mode_cpath = "";
+    parameter mode_epath = "";
+    parameter mode_io_cal = 1'b0;
+    parameter mode_rpath = "";
+    parameter mode_side1 = 0;
+    parameter mode_side2 = 0;
+    parameter mode_tpath = "";
+    parameter sel_clk_out1 = 1'b0;
+    parameter sel_clk_out2 = 1'b0;
+    parameter sel_clkr_rx1 = 1'b0;
+    parameter sel_clkr_rx2 = 1'b0;
+    parameter sel_clkw_rx1 = 2'b00;
+    parameter sel_clkw_rx2 = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_IOM_CONTROL_L(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3
+, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3
+, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1
+, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3, DRO4
+, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16, LINK17, LINK18, LINK19
+, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);
+    output C1RED;
+    input C1RNE;
+    input C1RS;
+    input C1RW1;
+    input C1RW2;
+    input C1RW3;
+    input C1TS;
+    input C1TW;
+    output C2RED;
+    input C2RNE;
+    input C2RS;
+    input C2RW1;
+    input C2RW2;
+    input C2RW3;
+    input C2TS;
+    input C2TW;
+    input CAD1;
+    input CAD2;
+    input CAD3;
+    input CAD4;
+    input CAD5;
+    input CAD6;
+    output CAL;
+    input CAN1;
+    input CAN2;
+    input CAN3;
+    input CAN4;
+    input CAP1;
+    input CAP2;
+    input CAP3;
+    input CAP4;
+    input CAT1;
+    input CAT2;
+    input CAT3;
+    input CAT4;
+    input CCK;
+    output CKO1;
+    output CKO2;
+    input CTCK;
+    input DC;
+    input DCK;
+    input DIG;
+    input DIS;
+    input DOG;
+    input DOS;
+    input DPAG;
+    input DPAS;
+    input DQSG;
+    input DQSS;
+    input DRA1;
+    input DRA2;
+    input DRA3;
+    input DRA4;
+    input DRA5;
+    input DRA6;
+    input DRI1;
+    input DRI2;
+    input DRI3;
+    input DRI4;
+    input DRI5;
+    input DRI6;
+    input DRL;
+    output DRO1;
+    output DRO2;
+    output DRO3;
+    output DRO4;
+    output DRO5;
+    output DRO6;
+    input DS1;
+    input DS2;
+    input FA1;
+    input FA2;
+    input FA3;
+    input FA4;
+    input FA5;
+    input FA6;
+    output FLD;
+    output FLG;
+    input FZ;
+    inout [41:0] LINK1;
+    inout [41:0] LINK10;
+    inout [41:0] LINK11;
+    inout [41:0] LINK12;
+    inout [41:0] LINK13;
+    inout [41:0] LINK14;
+    inout [41:0] LINK15;
+    inout [41:0] LINK16;
+    inout [41:0] LINK17;
+    inout [41:0] LINK18;
+    inout [41:0] LINK19;
+    inout [41:0] LINK2;
+    inout [41:0] LINK20;
+    inout [41:0] LINK21;
+    inout [41:0] LINK22;
+    inout [41:0] LINK23;
+    inout [41:0] LINK24;
+    inout [41:0] LINK25;
+    inout [41:0] LINK26;
+    inout [41:0] LINK27;
+    inout [41:0] LINK28;
+    inout [41:0] LINK29;
+    inout [41:0] LINK3;
+    inout [41:0] LINK30;
+    inout [41:0] LINK31;
+    inout [41:0] LINK32;
+    inout [41:0] LINK33;
+    inout [41:0] LINK34;
+    inout [41:0] LINK4;
+    inout [41:0] LINK5;
+    inout [41:0] LINK6;
+    inout [41:0] LINK7;
+    inout [41:0] LINK8;
+    inout [41:0] LINK9;
+    input RRCK1;
+    input RRCK2;
+    input RTCK1;
+    input RTCK2;
+    input WRCK1;
+    input WRCK2;
+    input WTCK1;
+    input WTCK2;
+    parameter div_rx1 = 4'b0000;
+    parameter div_rx2 = 4'b0000;
+    parameter div_tx1 = 4'b0000;
+    parameter div_tx2 = 4'b0000;
+    parameter inv_di_fclk1 = 1'b0;
+    parameter inv_di_fclk2 = 1'b0;
+    parameter latency1 = 1'b0;
+    parameter latency2 = 1'b0;
+    parameter location = "";
+    parameter mode_cpath = "";
+    parameter mode_epath = "";
+    parameter mode_io_cal = 1'b0;
+    parameter mode_rpath = "";
+    parameter mode_side1 = 0;
+    parameter mode_side2 = 0;
+    parameter mode_tpath = "";
+    parameter sel_clk_out1 = 1'b0;
+    parameter sel_clk_out2 = 1'b0;
+    parameter sel_clkr_rx1 = 1'b0;
+    parameter sel_clkr_rx2 = 1'b0;
+    parameter sel_clkw_rx1 = 2'b00;
+    parameter sel_clkw_rx2 = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_IOM_CONTROL_M(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3
+, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3
+, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1
+, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1
+, DRO2, DRO3, DRO4, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16
+, LINK17, LINK18, LINK19, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);
+    output C1RED;
+    input C1RNE;
+    input C1RS;
+    input C1RW1;
+    input C1RW2;
+    input C1RW3;
+    input C1TS;
+    input C1TW;
+    output C2RED;
+    input C2RNE;
+    input C2RS;
+    input C2RW1;
+    input C2RW2;
+    input C2RW3;
+    input C2TS;
+    input C2TW;
+    input CAD1;
+    input CAD2;
+    input CAD3;
+    input CAD4;
+    input CAD5;
+    input CAD6;
+    output CAL;
+    input CAN1;
+    input CAN2;
+    input CAN3;
+    input CAN4;
+    input CAP1;
+    input CAP2;
+    input CAP3;
+    input CAP4;
+    input CAT1;
+    input CAT2;
+    input CAT3;
+    input CAT4;
+    input CCK;
+    output CKO1;
+    output CKO2;
+    input CTCK;
+    input DC;
+    input DCK;
+    input DIG;
+    input DIS;
+    input DOG;
+    input DOS;
+    input DPAG;
+    input DPAS;
+    input DQSG;
+    input DQSS;
+    input DRA1;
+    input DRA2;
+    input DRA3;
+    input DRA4;
+    input DRA5;
+    input DRA6;
+    input DRI1;
+    input DRI2;
+    input DRI3;
+    input DRI4;
+    input DRI5;
+    input DRI6;
+    input DRL;
+    output DRO1;
+    output DRO2;
+    output DRO3;
+    output DRO4;
+    output DRO5;
+    output DRO6;
+    input DS1;
+    input DS2;
+    input FA1;
+    input FA2;
+    input FA3;
+    input FA4;
+    input FA5;
+    input FA6;
+    output FLD;
+    output FLG;
+    input FZ;
+    inout [41:0] LINK1;
+    inout [41:0] LINK10;
+    inout [41:0] LINK11;
+    inout [41:0] LINK12;
+    inout [41:0] LINK13;
+    inout [41:0] LINK14;
+    inout [41:0] LINK15;
+    inout [41:0] LINK16;
+    inout [41:0] LINK17;
+    inout [41:0] LINK18;
+    inout [41:0] LINK19;
+    inout [41:0] LINK2;
+    inout [41:0] LINK20;
+    inout [41:0] LINK21;
+    inout [41:0] LINK22;
+    inout [41:0] LINK23;
+    inout [41:0] LINK24;
+    inout [41:0] LINK25;
+    inout [41:0] LINK26;
+    inout [41:0] LINK27;
+    inout [41:0] LINK28;
+    inout [41:0] LINK29;
+    inout [41:0] LINK3;
+    inout [41:0] LINK30;
+    inout [41:0] LINK31;
+    inout [41:0] LINK32;
+    inout [41:0] LINK33;
+    inout [41:0] LINK34;
+    inout [41:0] LINK4;
+    inout [41:0] LINK5;
+    inout [41:0] LINK6;
+    inout [41:0] LINK7;
+    inout [41:0] LINK8;
+    inout [41:0] LINK9;
+    input RRCK1;
+    input RRCK2;
+    input RTCK1;
+    input RTCK2;
+    input SPI1;
+    input SPI2;
+    input SPI3;
+    input WRCK1;
+    input WRCK2;
+    input WTCK1;
+    input WTCK2;
+    parameter div_rx1 = 4'b0000;
+    parameter div_rx2 = 4'b0000;
+    parameter div_tx1 = 4'b0000;
+    parameter div_tx2 = 4'b0000;
+    parameter inv_di_fclk1 = 1'b0;
+    parameter inv_di_fclk2 = 1'b0;
+    parameter latency1 = 1'b0;
+    parameter latency2 = 1'b0;
+    parameter location = "";
+    parameter mode_cpath = "";
+    parameter mode_epath = "";
+    parameter mode_io_cal = 1'b0;
+    parameter mode_rpath = "";
+    parameter mode_side1 = 0;
+    parameter mode_side2 = 0;
+    parameter mode_tpath = "";
+    parameter sel_clk_out1 = 1'b0;
+    parameter sel_clk_out2 = 1'b0;
+    parameter sel_clkr_rx1 = 1'b0;
+    parameter sel_clkr_rx2 = 1'b0;
+    parameter sel_clkw_rx1 = 2'b00;
+    parameter sel_clkw_rx2 = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_IOM_CONTROL_U(ALCK1, ALCK2, ALCK3, LDSCK1, LDSCK2, LDSCK3, SWRX1CK, SWRX2CK, FCK1, FCK2, FDCK, CCK, DQ1CI1, DQ1CI2, DQ1CI3, DQ1CI4, DQ1CI5, DQ1CI6, DQ1CI7, DQ1CI8, DQ2CI1
+, DQ2CI2, DQ2CI3, DQ2CI4, DQ2CI5, DQ2CI6, DQ2CI7, DQ2CI8, DQ3CI1, DQ3CI2, DQ3CI3, DQ3CI4, DQ3CI5, DQ3CI6, DQ3CI7, DQ3CI8, DQS1CI1, DQS1CI2, DQS1CI3, DQS1CI4, DQS1CI5, DQS1CI6
+, DQS1CI7, DQS1CI8, DQS2CI1, DQS2CI2, DQS2CI3, DQS2CI4, DQS2CI5, DQS2CI6, DQS2CI7, DQS2CI8, DQS3CI1, DQS3CI2, DQS3CI3, DQS3CI4, DQS3CI5, DQS3CI6, DQS3CI7, DQS3CI8, LD1RN, LD2RN, LD3RN
+, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DCRN, LE, SE, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4, DRO1CSN
+, DRO2CSN, DRO3CSN, DRI1CSN, DRI2CSN, DRI3CSN, DRDPA1CSN, DRDPA2CSN, DRDPA3CSN, DRCCSN, DRWDS, DRWEN, DRE, CA1P1, CA1P2, CA1P3, CA1P4, CA2P1, CA2P2, CA2P3, CA2P4, CA1N1
+, CA1N2, CA1N3, CA1N4, CA2N1, CA2N2, CA2N3, CA2N4, CA1T1, CA1T2, CA1T3, CA1T4, CA2T1, CA2T2, CA2T3, CA2T4, CA1D1, CA1D2, CA1D3, CA1D4, CA1D5, CA1D6
+, CA2D1, CA2D2, CA2D3, CA2D4, CA2D5, CA2D6, CKO1, CKO2, FLD, FLG, AL1D, AL2D, AL3D, AL1T, AL2T, AL3T, DCL, DRO1, DRO2, DRO3, DRO4
+, DRO5, DRO6, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16, LINK17, LINK18, LINK19, LINK20
+, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);
+    output AL1D;
+    output AL1T;
+    output AL2D;
+    output AL2T;
+    output AL3D;
+    output AL3T;
+    input ALCK1;
+    input ALCK2;
+    input ALCK3;
+    input CA1D1;
+    input CA1D2;
+    input CA1D3;
+    input CA1D4;
+    input CA1D5;
+    input CA1D6;
+    input CA1N1;
+    input CA1N2;
+    input CA1N3;
+    input CA1N4;
+    input CA1P1;
+    input CA1P2;
+    input CA1P3;
+    input CA1P4;
+    input CA1T1;
+    input CA1T2;
+    input CA1T3;
+    input CA1T4;
+    input CA2D1;
+    input CA2D2;
+    input CA2D3;
+    input CA2D4;
+    input CA2D5;
+    input CA2D6;
+    input CA2N1;
+    input CA2N2;
+    input CA2N3;
+    input CA2N4;
+    input CA2P1;
+    input CA2P2;
+    input CA2P3;
+    input CA2P4;
+    input CA2T1;
+    input CA2T2;
+    input CA2T3;
+    input CA2T4;
+    input CCK;
+    output CKO1;
+    output CKO2;
+    output DCL;
+    input DCRN;
+    input DQ1CI1;
+    input DQ1CI2;
+    input DQ1CI3;
+    input DQ1CI4;
+    input DQ1CI5;
+    input DQ1CI6;
+    input DQ1CI7;
+    input DQ1CI8;
+    input DQ2CI1;
+    input DQ2CI2;
+    input DQ2CI3;
+    input DQ2CI4;
+    input DQ2CI5;
+    input DQ2CI6;
+    input DQ2CI7;
+    input DQ2CI8;
+    input DQ3CI1;
+    input DQ3CI2;
+    input DQ3CI3;
+    input DQ3CI4;
+    input DQ3CI5;
+    input DQ3CI6;
+    input DQ3CI7;
+    input DQ3CI8;
+    input DQS1CI1;
+    input DQS1CI2;
+    input DQS1CI3;
+    input DQS1CI4;
+    input DQS1CI5;
+    input DQS1CI6;
+    input DQS1CI7;
+    input DQS1CI8;
+    input DQS2CI1;
+    input DQS2CI2;
+    input DQS2CI3;
+    input DQS2CI4;
+    input DQS2CI5;
+    input DQS2CI6;
+    input DQS2CI7;
+    input DQS2CI8;
+    input DQS3CI1;
+    input DQS3CI2;
+    input DQS3CI3;
+    input DQS3CI4;
+    input DQS3CI5;
+    input DQS3CI6;
+    input DQS3CI7;
+    input DQS3CI8;
+    input DRA1;
+    input DRA2;
+    input DRA3;
+    input DRA4;
+    input DRCCSN;
+    input DRDPA1CSN;
+    input DRDPA2CSN;
+    input DRDPA3CSN;
+    input DRE;
+    input DRI1;
+    input DRI1CSN;
+    input DRI2;
+    input DRI2CSN;
+    input DRI3;
+    input DRI3CSN;
+    input DRI4;
+    input DRI5;
+    input DRI6;
+    output DRO1;
+    input DRO1CSN;
+    output DRO2;
+    input DRO2CSN;
+    output DRO3;
+    input DRO3CSN;
+    output DRO4;
+    output DRO5;
+    output DRO6;
+    input DRWDS;
+    input DRWEN;
+    input FA1;
+    input FA2;
+    input FA3;
+    input FA4;
+    input FA5;
+    input FA6;
+    input FCK1;
+    input FCK2;
+    input FDCK;
+    output FLD;
+    output FLG;
+    input FZ;
+    input LD1RN;
+    input LD2RN;
+    input LD3RN;
+    input LDSCK1;
+    input LDSCK2;
+    input LDSCK3;
+    input LE;
+    inout [41:0] LINK1;
+    inout [41:0] LINK10;
+    inout [41:0] LINK11;
+    inout [41:0] LINK12;
+    inout [41:0] LINK13;
+    inout [41:0] LINK14;
+    inout [41:0] LINK15;
+    inout [41:0] LINK16;
+    inout [41:0] LINK17;
+    inout [41:0] LINK18;
+    inout [41:0] LINK19;
+    inout [41:0] LINK2;
+    inout [41:0] LINK20;
+    inout [41:0] LINK21;
+    inout [41:0] LINK22;
+    inout [41:0] LINK23;
+    inout [41:0] LINK24;
+    inout [41:0] LINK25;
+    inout [41:0] LINK26;
+    inout [41:0] LINK27;
+    inout [41:0] LINK28;
+    inout [41:0] LINK29;
+    inout [41:0] LINK3;
+    inout [41:0] LINK30;
+    inout [41:0] LINK31;
+    inout [41:0] LINK32;
+    inout [41:0] LINK33;
+    inout [41:0] LINK34;
+    inout [41:0] LINK4;
+    inout [41:0] LINK5;
+    inout [41:0] LINK6;
+    inout [41:0] LINK7;
+    inout [41:0] LINK8;
+    inout [41:0] LINK9;
+    input SE;
+    input SWRX1CK;
+    input SWRX2CK;
+    parameter cal_delay1 = "";
+    parameter cal_delay2 = "";
+    parameter div1 = 3'b000;
+    parameter div2 = 3'b000;
+    parameter div3 = 3'b000;
+    parameter div_swrx1 = 3'b000;
+    parameter div_swrx2 = 3'b000;
+    parameter inv_ld_sck1 = 1'b0;
+    parameter inv_ld_sck2 = 1'b0;
+    parameter inv_ld_sck3 = 1'b0;
+    parameter link_ld_12 = 1'b0;
+    parameter link_ld_23 = 1'b0;
+    parameter location = "";
+    parameter mode_side1 = 0;
+    parameter mode_side2 = 0;
+    parameter mode_side3 = 0;
+    parameter sel_clk_out1 = 1'b0;
+    parameter sel_clk_out2 = 1'b0;
+    parameter sel_dc_clk = 2'b00;
+    parameter sel_ld_fck1 = 2'b00;
+    parameter sel_ld_fck2 = 2'b00;
+    parameter sel_ld_fck3 = 2'b00;
+    parameter sel_sw_fck1 = 2'b00;
+    parameter sel_sw_fck2 = 2'b00;
+    parameter use_dc = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_IOM_DRIVER(EI1, EI2, EI3, EI4, EI5, EL, ER, CI1, CI2, CI3, CI4, CI5, CL, CR, CTI, RI, RL, RR, CO, EO, RO1
+, RO2, RO3, RO4, RO5, CTO, LINK);
+    input CI1;
+    input CI2;
+    input CI3;
+    input CI4;
+    input CI5;
+    input CL;
+    output CO;
+    input CR;
+    input CTI;
+    output CTO;
+    input EI1;
+    input EI2;
+    input EI3;
+    input EI4;
+    input EI5;
+    input EL;
+    output EO;
+    input ER;
+    inout [41:0] LINK;
+    input RI;
+    input RL;
+    output RO1;
+    output RO2;
+    output RO3;
+    output RO4;
+    output RO5;
+    input RR;
+    parameter chained = 1'b0;
+    parameter cpath_edge = 1'b0;
+    parameter cpath_init = 1'b0;
+    parameter cpath_inv = 1'b0;
+    parameter cpath_load = 1'b0;
+    parameter cpath_mode = 4'b0000;
+    parameter cpath_sync = 1'b0;
+    parameter epath_dynamic = 1'b0;
+    parameter epath_edge = 1'b0;
+    parameter epath_init = 1'b0;
+    parameter epath_load = 1'b0;
+    parameter epath_mode = 4'b0000;
+    parameter epath_sync = 1'b0;
+    parameter location = "";
+    parameter rpath_dynamic = 1'b0;
+    parameter rpath_edge = 1'b0;
+    parameter rpath_init = 1'b0;
+    parameter rpath_load = 1'b0;
+    parameter rpath_mode = 4'b0000;
+    parameter rpath_sync = 1'b0;
+    parameter symbol = "";
+    parameter tpath_mode = 2'b00;
+    parameter variant = "";
+endmodule
+
+(* blackbox *)
+module NX_IOM_DRIVER_M(EI1, EI2, EI3, EI4, EI5, EL, ER, CI1, CI2, CI3, CI4, CI5, CL, CR, CTI, RI, RL, RR, CO, EO, RO1
+, RO2, RO3, RO4, RO5, CTO, LINK);
+    input CI1;
+    input CI2;
+    input CI3;
+    input CI4;
+    input CI5;
+    input CL;
+    output CO;
+    input CR;
+    input CTI;
+    output CTO;
+    input EI1;
+    input EI2;
+    input EI3;
+    input EI4;
+    input EI5;
+    input EL;
+    output EO;
+    input ER;
+    inout [41:0] LINK;
+    input RI;
+    input RL;
+    output RO1;
+    output RO2;
+    output RO3;
+    output RO4;
+    output RO5;
+    input RR;
+    parameter chained = 1'b0;
+    parameter cpath_edge = 1'b0;
+    parameter cpath_init = 1'b0;
+    parameter cpath_inv = 1'b0;
+    parameter cpath_load = 1'b0;
+    parameter cpath_mode = 4'b0000;
+    parameter cpath_sync = 1'b0;
+    parameter epath_dynamic = 1'b0;
+    parameter epath_edge = 1'b0;
+    parameter epath_init = 1'b0;
+    parameter epath_load = 1'b0;
+    parameter epath_mode = 4'b0000;
+    parameter epath_sync = 1'b0;
+    parameter location = "";
+    parameter rpath_dynamic = 1'b0;
+    parameter rpath_edge = 1'b0;
+    parameter rpath_init = 1'b0;
+    parameter rpath_load = 1'b0;
+    parameter rpath_mode = 4'b0000;
+    parameter rpath_sync = 1'b0;
+    parameter symbol = "";
+    parameter tpath_mode = 2'b00;
+    parameter variant = "";
+endmodule
+
+(* blackbox *)
+module NX_IOM_DRIVER_U(EI1, EI2, EI3, EI4, EI5, EI6, EI7, EI8, EL, ER, CI1, CL, CR, RI, RL, RR, CO, CTI, CTO, EO, RO1
+, RO2, RO3, RO4, RO5, RO6, RO7, RO8, LINK);
+    input CI1;
+    input CL;
+    output CO;
+    input CR;
+    input CTI;
+    output CTO;
+    input EI1;
+    input EI2;
+    input EI3;
+    input EI4;
+    input EI5;
+    input EI6;
+    input EI7;
+    input EI8;
+    input EL;
+    output EO;
+    input ER;
+    inout [41:0] LINK;
+    input RI;
+    input RL;
+    output RO1;
+    output RO2;
+    output RO3;
+    output RO4;
+    output RO5;
+    output RO6;
+    output RO7;
+    output RO8;
+    input RR;
+    parameter chained = 1'b0;
+    parameter cpath_edge = 1'b0;
+    parameter cpath_init = 1'b0;
+    parameter cpath_inv = 1'b0;
+    parameter cpath_load = 1'b0;
+    parameter cpath_mode = 4'b0000;
+    parameter cpath_sync = 1'b0;
+    parameter cpath_type = 1'b0;
+    parameter epath_dynamic = 1'b0;
+    parameter epath_edge = 1'b0;
+    parameter epath_init = 1'b0;
+    parameter epath_load = 1'b0;
+    parameter epath_mode = 4'b0000;
+    parameter epath_sync = 1'b0;
+    parameter epath_type = 1'b0;
+    parameter location = "";
+    parameter rpath_dynamic = 1'b0;
+    parameter rpath_edge = 1'b0;
+    parameter rpath_init = 1'b0;
+    parameter rpath_load = 1'b0;
+    parameter rpath_mode = 4'b0000;
+    parameter rpath_sync = 1'b0;
+    parameter rpath_type = 1'b0;
+    parameter symbol = "";
+    parameter tpath_mode = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_IOM_L(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, CCK, DCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1
+, C2RW2, C2RW3, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3
+, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1
+, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3, DRO4
+, DRO5, DRO6, CAL, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EL, P1ER, P1EO, P1RI, P1RL, P1RR, P1RO1
+, P1RO2, P1RO3, P1RO4, P1RO5, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EL, P2ER, P2EO, P2RI, P2RL, P2RR
+, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P3CI1, P3CL, P3CR, P3CO, P3CTI, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EL, P3ER, P3EO, P3RI, P3RL
+, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EL, P4ER, P4EO, P4RI
+, P4RL, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P5CI1, P5CI2, P5CI3, P5CI4, P5CI5, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3, P5EI4
+, P5EI5, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P6CI1, P6CL, P6CR, P6CO, P6CTI, P6CTO, P6EI1, P6EI2, P6EI3
+, P6EI4, P6EI5, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1, P7EI2
+, P7EI3, P7EI4, P7EI5, P7EL, P7ER, P7EO, P7RI, P7RL, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO, P8EI1
+, P8EI2, P8EI3, P8EI4, P8EI5, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P9CI1, P9CL, P9CR, P9CO, P9CTI, P9CTO
+, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P10CI1, P10CL, P10CR, P10CO, P10CTI
+, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EL, P10ER, P10EO, P10RI, P10RL, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P11CI1, P11CL, P11CR, P11CO
+, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P12CI1, P12CL, P12CR
+, P12CO, P12CTI, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P13CI1, P13CL
+, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EL, P13ER, P13EO, P13RI, P13RL, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5, P14CI1
+, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4, P14RO5
+, P15CI1, P15CL, P15CR, P15CO, P15CTI, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3, P15RO4
+, P15RO5, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EL, P16ER, P16EO, P16RI, P16RL, P16RR, P16RO1, P16RO2, P16RO3
+, P16RO4, P16RO5, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1, P17RO2
+, P17RO3, P17RO4, P17RO5, P18CI1, P18CL, P18CR, P18CO, P18CTI, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR, P18RO1
+, P18RO2, P18RO3, P18RO4, P18RO5, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EL, P19ER, P19EO, P19RI, P19RL, P19RR
+, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EL, P20ER, P20EO, P20RI, P20RL
+, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P21CI1, P21CL, P21CR, P21CO, P21CTI, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EL, P21ER, P21EO, P21RI
+, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EL, P22ER, P22EO
+, P22RI, P22RL, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EL, P23ER
+, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P24CI1, P24CL, P24CR, P24CO, P24CTI, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5, P24EL
+, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P25CI1, P25CL, P25CR, P25CO, P25CTI, P25CTO, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5
+, P25EL, P25ER, P25EO, P25RI, P25RL, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P26CI1, P26CL, P26CR, P26CO, P26CTI, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4
+, P26EI5, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P27CI1, P27CL, P27CR, P27CO, P27CTI, P27CTO, P27EI1, P27EI2, P27EI3
+, P27EI4, P27EI5, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P28CI1, P28CL, P28CR, P28CO, P28CTI, P28CTO, P28EI1, P28EI2
+, P28EI3, P28EI4, P28EI5, P28EL, P28ER, P28EO, P28RI, P28RL, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P29CI1, P29CI2, P29CI3, P29CI4, P29CI5, P29CL, P29CR
+, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P30CI1, P30CL
+, P30CR, P30CO, P30CTI, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5, P31CI1
+, P31CL, P31CR, P31CO, P31CTI, P31CTO, P31EI1, P31EI2, P31EI3, P31EI4, P31EI5, P31EL, P31ER, P31EO, P31RI, P31RL, P31RR, P31RO1, P31RO2, P31RO3, P31RO4, P31RO5
+, P32CI1, P32CL, P32CR, P32CO, P32CTI, P32CTO, P32EI1, P32EI2, P32EI3, P32EI4, P32EI5, P32EL, P32ER, P32EO, P32RI, P32RL, P32RR, P32RO1, P32RO2, P32RO3, P32RO4
+, P32RO5, P33CI1, P33CL, P33CR, P33CO, P33CTI, P33CTO, P33EI1, P33EI2, P33EI3, P33EI4, P33EI5, P33EL, P33ER, P33EO, P33RI, P33RL, P33RR, P33RO1, P33RO2, P33RO3
+, P33RO4, P33RO5, P34CI1, P34CL, P34CR, P34CO, P34CTI, P34CTO, P34EI1, P34EI2, P34EI3, P34EI4, P34EI5, P34EL, P34ER, P34EO, P34RI, P34RL, P34RR, P34RO1, P34RO2
+, P34RO3, P34RO4, P34RO5);
+    output C1RED;
+    input C1RNE;
+    input C1RS;
+    input C1RW1;
+    input C1RW2;
+    input C1RW3;
+    input C1TS;
+    input C1TW;
+    output C2RED;
+    input C2RNE;
+    input C2RS;
+    input C2RW1;
+    input C2RW2;
+    input C2RW3;
+    input C2TS;
+    input C2TW;
+    input CAD1;
+    input CAD2;
+    input CAD3;
+    input CAD4;
+    input CAD5;
+    input CAD6;
+    output CAL;
+    input CAN1;
+    input CAN2;
+    input CAN3;
+    input CAN4;
+    input CAP1;
+    input CAP2;
+    input CAP3;
+    input CAP4;
+    input CAT1;
+    input CAT2;
+    input CAT3;
+    input CAT4;
+    input CCK;
+    output CKO1;
+    output CKO2;
+    input CTCK;
+    input DC;
+    input DCK;
+    input DIG;
+    input DIS;
+    input DOG;
+    input DOS;
+    input DPAG;
+    input DPAS;
+    input DQSG;
+    input DQSS;
+    input DRA1;
+    input DRA2;
+    input DRA3;
+    input DRA4;
+    input DRA5;
+    input DRA6;
+    input DRI1;
+    input DRI2;
+    input DRI3;
+    input DRI4;
+    input DRI5;
+    input DRI6;
+    input DRL;
+    output DRO1;
+    output DRO2;
+    output DRO3;
+    output DRO4;
+    output DRO5;
+    output DRO6;
+    input DS1;
+    input DS2;
+    input FA1;
+    input FA2;
+    input FA3;
+    input FA4;
+    input FA5;
+    input FA6;
+    output FLD;
+    output FLG;
+    input FZ;
+    input P10CI1;
+    input P10CL;
+    output P10CO;
+    input P10CR;
+    input P10CTI;
+    output P10CTO;
+    input P10EI1;
+    input P10EI2;
+    input P10EI3;
+    input P10EI4;
+    input P10EI5;
+    input P10EL;
+    output P10EO;
+    input P10ER;
+    input P10RI;
+    input P10RL;
+    output P10RO1;
+    output P10RO2;
+    output P10RO3;
+    output P10RO4;
+    output P10RO5;
+    input P10RR;
+    input P11CI1;
+    input P11CL;
+    output P11CO;
+    input P11CR;
+    input P11CTI;
+    output P11CTO;
+    input P11EI1;
+    input P11EI2;
+    input P11EI3;
+    input P11EI4;
+    input P11EI5;
+    input P11EL;
+    output P11EO;
+    input P11ER;
+    input P11RI;
+    input P11RL;
+    output P11RO1;
+    output P11RO2;
+    output P11RO3;
+    output P11RO4;
+    output P11RO5;
+    input P11RR;
+    input P12CI1;
+    input P12CL;
+    output P12CO;
+    input P12CR;
+    input P12CTI;
+    output P12CTO;
+    input P12EI1;
+    input P12EI2;
+    input P12EI3;
+    input P12EI4;
+    input P12EI5;
+    input P12EL;
+    output P12EO;
+    input P12ER;
+    input P12RI;
+    input P12RL;
+    output P12RO1;
+    output P12RO2;
+    output P12RO3;
+    output P12RO4;
+    output P12RO5;
+    input P12RR;
+    input P13CI1;
+    input P13CL;
+    output P13CO;
+    input P13CR;
+    input P13CTI;
+    output P13CTO;
+    input P13EI1;
+    input P13EI2;
+    input P13EI3;
+    input P13EI4;
+    input P13EI5;
+    input P13EL;
+    output P13EO;
+    input P13ER;
+    input P13RI;
+    input P13RL;
+    output P13RO1;
+    output P13RO2;
+    output P13RO3;
+    output P13RO4;
+    output P13RO5;
+    input P13RR;
+    input P14CI1;
+    input P14CL;
+    output P14CO;
+    input P14CR;
+    input P14CTI;
+    output P14CTO;
+    input P14EI1;
+    input P14EI2;
+    input P14EI3;
+    input P14EI4;
+    input P14EI5;
+    input P14EL;
+    output P14EO;
+    input P14ER;
+    input P14RI;
+    input P14RL;
+    output P14RO1;
+    output P14RO2;
+    output P14RO3;
+    output P14RO4;
+    output P14RO5;
+    input P14RR;
+    input P15CI1;
+    input P15CL;
+    output P15CO;
+    input P15CR;
+    input P15CTI;
+    output P15CTO;
+    input P15EI1;
+    input P15EI2;
+    input P15EI3;
+    input P15EI4;
+    input P15EI5;
+    input P15EL;
+    output P15EO;
+    input P15ER;
+    input P15RI;
+    input P15RL;
+    output P15RO1;
+    output P15RO2;
+    output P15RO3;
+    output P15RO4;
+    output P15RO5;
+    input P15RR;
+    input P16CI1;
+    input P16CL;
+    output P16CO;
+    input P16CR;
+    input P16CTI;
+    output P16CTO;
+    input P16EI1;
+    input P16EI2;
+    input P16EI3;
+    input P16EI4;
+    input P16EI5;
+    input P16EL;
+    output P16EO;
+    input P16ER;
+    input P16RI;
+    input P16RL;
+    output P16RO1;
+    output P16RO2;
+    output P16RO3;
+    output P16RO4;
+    output P16RO5;
+    input P16RR;
+    input P17CI1;
+    input P17CL;
+    output P17CO;
+    input P17CR;
+    input P17CTI;
+    output P17CTO;
+    input P17EI1;
+    input P17EI2;
+    input P17EI3;
+    input P17EI4;
+    input P17EI5;
+    input P17EL;
+    output P17EO;
+    input P17ER;
+    input P17RI;
+    input P17RL;
+    output P17RO1;
+    output P17RO2;
+    output P17RO3;
+    output P17RO4;
+    output P17RO5;
+    input P17RR;
+    input P18CI1;
+    input P18CL;
+    output P18CO;
+    input P18CR;
+    input P18CTI;
+    output P18CTO;
+    input P18EI1;
+    input P18EI2;
+    input P18EI3;
+    input P18EI4;
+    input P18EI5;
+    input P18EL;
+    output P18EO;
+    input P18ER;
+    input P18RI;
+    input P18RL;
+    output P18RO1;
+    output P18RO2;
+    output P18RO3;
+    output P18RO4;
+    output P18RO5;
+    input P18RR;
+    input P19CI1;
+    input P19CL;
+    output P19CO;
+    input P19CR;
+    input P19CTI;
+    output P19CTO;
+    input P19EI1;
+    input P19EI2;
+    input P19EI3;
+    input P19EI4;
+    input P19EI5;
+    input P19EL;
+    output P19EO;
+    input P19ER;
+    input P19RI;
+    input P19RL;
+    output P19RO1;
+    output P19RO2;
+    output P19RO3;
+    output P19RO4;
+    output P19RO5;
+    input P19RR;
+    input P1CI1;
+    input P1CL;
+    output P1CO;
+    input P1CR;
+    input P1CTI;
+    output P1CTO;
+    input P1EI1;
+    input P1EI2;
+    input P1EI3;
+    input P1EI4;
+    input P1EI5;
+    input P1EL;
+    output P1EO;
+    input P1ER;
+    input P1RI;
+    input P1RL;
+    output P1RO1;
+    output P1RO2;
+    output P1RO3;
+    output P1RO4;
+    output P1RO5;
+    input P1RR;
+    input P20CI1;
+    input P20CL;
+    output P20CO;
+    input P20CR;
+    input P20CTI;
+    output P20CTO;
+    input P20EI1;
+    input P20EI2;
+    input P20EI3;
+    input P20EI4;
+    input P20EI5;
+    input P20EL;
+    output P20EO;
+    input P20ER;
+    input P20RI;
+    input P20RL;
+    output P20RO1;
+    output P20RO2;
+    output P20RO3;
+    output P20RO4;
+    output P20RO5;
+    input P20RR;
+    input P21CI1;
+    input P21CL;
+    output P21CO;
+    input P21CR;
+    input P21CTI;
+    output P21CTO;
+    input P21EI1;
+    input P21EI2;
+    input P21EI3;
+    input P21EI4;
+    input P21EI5;
+    input P21EL;
+    output P21EO;
+    input P21ER;
+    input P21RI;
+    input P21RL;
+    output P21RO1;
+    output P21RO2;
+    output P21RO3;
+    output P21RO4;
+    output P21RO5;
+    input P21RR;
+    input P22CI1;
+    input P22CL;
+    output P22CO;
+    input P22CR;
+    input P22CTI;
+    output P22CTO;
+    input P22EI1;
+    input P22EI2;
+    input P22EI3;
+    input P22EI4;
+    input P22EI5;
+    input P22EL;
+    output P22EO;
+    input P22ER;
+    input P22RI;
+    input P22RL;
+    output P22RO1;
+    output P22RO2;
+    output P22RO3;
+    output P22RO4;
+    output P22RO5;
+    input P22RR;
+    input P23CI1;
+    input P23CL;
+    output P23CO;
+    input P23CR;
+    input P23CTI;
+    output P23CTO;
+    input P23EI1;
+    input P23EI2;
+    input P23EI3;
+    input P23EI4;
+    input P23EI5;
+    input P23EL;
+    output P23EO;
+    input P23ER;
+    input P23RI;
+    input P23RL;
+    output P23RO1;
+    output P23RO2;
+    output P23RO3;
+    output P23RO4;
+    output P23RO5;
+    input P23RR;
+    input P24CI1;
+    input P24CL;
+    output P24CO;
+    input P24CR;
+    input P24CTI;
+    output P24CTO;
+    input P24EI1;
+    input P24EI2;
+    input P24EI3;
+    input P24EI4;
+    input P24EI5;
+    input P24EL;
+    output P24EO;
+    input P24ER;
+    input P24RI;
+    input P24RL;
+    output P24RO1;
+    output P24RO2;
+    output P24RO3;
+    output P24RO4;
+    output P24RO5;
+    input P24RR;
+    input P25CI1;
+    input P25CL;
+    output P25CO;
+    input P25CR;
+    input P25CTI;
+    output P25CTO;
+    input P25EI1;
+    input P25EI2;
+    input P25EI3;
+    input P25EI4;
+    input P25EI5;
+    input P25EL;
+    output P25EO;
+    input P25ER;
+    input P25RI;
+    input P25RL;
+    output P25RO1;
+    output P25RO2;
+    output P25RO3;
+    output P25RO4;
+    output P25RO5;
+    input P25RR;
+    input P26CI1;
+    input P26CL;
+    output P26CO;
+    input P26CR;
+    input P26CTI;
+    output P26CTO;
+    input P26EI1;
+    input P26EI2;
+    input P26EI3;
+    input P26EI4;
+    input P26EI5;
+    input P26EL;
+    output P26EO;
+    input P26ER;
+    input P26RI;
+    input P26RL;
+    output P26RO1;
+    output P26RO2;
+    output P26RO3;
+    output P26RO4;
+    output P26RO5;
+    input P26RR;
+    input P27CI1;
+    input P27CL;
+    output P27CO;
+    input P27CR;
+    input P27CTI;
+    output P27CTO;
+    input P27EI1;
+    input P27EI2;
+    input P27EI3;
+    input P27EI4;
+    input P27EI5;
+    input P27EL;
+    output P27EO;
+    input P27ER;
+    input P27RI;
+    input P27RL;
+    output P27RO1;
+    output P27RO2;
+    output P27RO3;
+    output P27RO4;
+    output P27RO5;
+    input P27RR;
+    input P28CI1;
+    input P28CL;
+    output P28CO;
+    input P28CR;
+    input P28CTI;
+    output P28CTO;
+    input P28EI1;
+    input P28EI2;
+    input P28EI3;
+    input P28EI4;
+    input P28EI5;
+    input P28EL;
+    output P28EO;
+    input P28ER;
+    input P28RI;
+    input P28RL;
+    output P28RO1;
+    output P28RO2;
+    output P28RO3;
+    output P28RO4;
+    output P28RO5;
+    input P28RR;
+    input P29CI1;
+    input P29CI2;
+    input P29CI3;
+    input P29CI4;
+    input P29CI5;
+    input P29CL;
+    output P29CO;
+    input P29CR;
+    input P29CTI;
+    output P29CTO;
+    input P29EI1;
+    input P29EI2;
+    input P29EI3;
+    input P29EI4;
+    input P29EI5;
+    input P29EL;
+    output P29EO;
+    input P29ER;
+    input P29RI;
+    input P29RL;
+    output P29RO1;
+    output P29RO2;
+    output P29RO3;
+    output P29RO4;
+    output P29RO5;
+    input P29RR;
+    input P2CI1;
+    input P2CL;
+    output P2CO;
+    input P2CR;
+    input P2CTI;
+    output P2CTO;
+    input P2EI1;
+    input P2EI2;
+    input P2EI3;
+    input P2EI4;
+    input P2EI5;
+    input P2EL;
+    output P2EO;
+    input P2ER;
+    input P2RI;
+    input P2RL;
+    output P2RO1;
+    output P2RO2;
+    output P2RO3;
+    output P2RO4;
+    output P2RO5;
+    input P2RR;
+    input P30CI1;
+    input P30CL;
+    output P30CO;
+    input P30CR;
+    input P30CTI;
+    output P30CTO;
+    input P30EI1;
+    input P30EI2;
+    input P30EI3;
+    input P30EI4;
+    input P30EI5;
+    input P30EL;
+    output P30EO;
+    input P30ER;
+    input P30RI;
+    input P30RL;
+    output P30RO1;
+    output P30RO2;
+    output P30RO3;
+    output P30RO4;
+    output P30RO5;
+    input P30RR;
+    input P31CI1;
+    input P31CL;
+    output P31CO;
+    input P31CR;
+    input P31CTI;
+    output P31CTO;
+    input P31EI1;
+    input P31EI2;
+    input P31EI3;
+    input P31EI4;
+    input P31EI5;
+    input P31EL;
+    output P31EO;
+    input P31ER;
+    input P31RI;
+    input P31RL;
+    output P31RO1;
+    output P31RO2;
+    output P31RO3;
+    output P31RO4;
+    output P31RO5;
+    input P31RR;
+    input P32CI1;
+    input P32CL;
+    output P32CO;
+    input P32CR;
+    input P32CTI;
+    output P32CTO;
+    input P32EI1;
+    input P32EI2;
+    input P32EI3;
+    input P32EI4;
+    input P32EI5;
+    input P32EL;
+    output P32EO;
+    input P32ER;
+    input P32RI;
+    input P32RL;
+    output P32RO1;
+    output P32RO2;
+    output P32RO3;
+    output P32RO4;
+    output P32RO5;
+    input P32RR;
+    input P33CI1;
+    input P33CL;
+    output P33CO;
+    input P33CR;
+    input P33CTI;
+    output P33CTO;
+    input P33EI1;
+    input P33EI2;
+    input P33EI3;
+    input P33EI4;
+    input P33EI5;
+    input P33EL;
+    output P33EO;
+    input P33ER;
+    input P33RI;
+    input P33RL;
+    output P33RO1;
+    output P33RO2;
+    output P33RO3;
+    output P33RO4;
+    output P33RO5;
+    input P33RR;
+    input P34CI1;
+    input P34CL;
+    output P34CO;
+    input P34CR;
+    input P34CTI;
+    output P34CTO;
+    input P34EI1;
+    input P34EI2;
+    input P34EI3;
+    input P34EI4;
+    input P34EI5;
+    input P34EL;
+    output P34EO;
+    input P34ER;
+    input P34RI;
+    input P34RL;
+    output P34RO1;
+    output P34RO2;
+    output P34RO3;
+    output P34RO4;
+    output P34RO5;
+    input P34RR;
+    input P3CI1;
+    input P3CL;
+    output P3CO;
+    input P3CR;
+    input P3CTI;
+    output P3CTO;
+    input P3EI1;
+    input P3EI2;
+    input P3EI3;
+    input P3EI4;
+    input P3EI5;
+    input P3EL;
+    output P3EO;
+    input P3ER;
+    input P3RI;
+    input P3RL;
+    output P3RO1;
+    output P3RO2;
+    output P3RO3;
+    output P3RO4;
+    output P3RO5;
+    input P3RR;
+    input P4CI1;
+    input P4CL;
+    output P4CO;
+    input P4CR;
+    input P4CTI;
+    output P4CTO;
+    input P4EI1;
+    input P4EI2;
+    input P4EI3;
+    input P4EI4;
+    input P4EI5;
+    input P4EL;
+    output P4EO;
+    input P4ER;
+    input P4RI;
+    input P4RL;
+    output P4RO1;
+    output P4RO2;
+    output P4RO3;
+    output P4RO4;
+    output P4RO5;
+    input P4RR;
+    input P5CI1;
+    input P5CI2;
+    input P5CI3;
+    input P5CI4;
+    input P5CI5;
+    input P5CL;
+    output P5CO;
+    input P5CR;
+    input P5CTI;
+    output P5CTO;
+    input P5EI1;
+    input P5EI2;
+    input P5EI3;
+    input P5EI4;
+    input P5EI5;
+    input P5EL;
+    output P5EO;
+    input P5ER;
+    input P5RI;
+    input P5RL;
+    output P5RO1;
+    output P5RO2;
+    output P5RO3;
+    output P5RO4;
+    output P5RO5;
+    input P5RR;
+    input P6CI1;
+    input P6CL;
+    output P6CO;
+    input P6CR;
+    input P6CTI;
+    output P6CTO;
+    input P6EI1;
+    input P6EI2;
+    input P6EI3;
+    input P6EI4;
+    input P6EI5;
+    input P6EL;
+    output P6EO;
+    input P6ER;
+    input P6RI;
+    input P6RL;
+    output P6RO1;
+    output P6RO2;
+    output P6RO3;
+    output P6RO4;
+    output P6RO5;
+    input P6RR;
+    input P7CI1;
+    input P7CL;
+    output P7CO;
+    input P7CR;
+    input P7CTI;
+    output P7CTO;
+    input P7EI1;
+    input P7EI2;
+    input P7EI3;
+    input P7EI4;
+    input P7EI5;
+    input P7EL;
+    output P7EO;
+    input P7ER;
+    input P7RI;
+    input P7RL;
+    output P7RO1;
+    output P7RO2;
+    output P7RO3;
+    output P7RO4;
+    output P7RO5;
+    input P7RR;
+    input P8CI1;
+    input P8CL;
+    output P8CO;
+    input P8CR;
+    input P8CTI;
+    output P8CTO;
+    input P8EI1;
+    input P8EI2;
+    input P8EI3;
+    input P8EI4;
+    input P8EI5;
+    input P8EL;
+    output P8EO;
+    input P8ER;
+    input P8RI;
+    input P8RL;
+    output P8RO1;
+    output P8RO2;
+    output P8RO3;
+    output P8RO4;
+    output P8RO5;
+    input P8RR;
+    input P9CI1;
+    input P9CL;
+    output P9CO;
+    input P9CR;
+    input P9CTI;
+    output P9CTO;
+    input P9EI1;
+    input P9EI2;
+    input P9EI3;
+    input P9EI4;
+    input P9EI5;
+    input P9EL;
+    output P9EO;
+    input P9ER;
+    input P9RI;
+    input P9RL;
+    output P9RO1;
+    output P9RO2;
+    output P9RO3;
+    output P9RO4;
+    output P9RO5;
+    input P9RR;
+    input RRCK1;
+    input RRCK2;
+    input RTCK1;
+    input RTCK2;
+    input WRCK1;
+    input WRCK2;
+    input WTCK1;
+    input WTCK2;
+    parameter div_rx1 = 4'b0000;
+    parameter div_rx2 = 4'b0000;
+    parameter div_tx1 = 4'b0000;
+    parameter div_tx2 = 4'b0000;
+    parameter mode_io_cal = 1'b0;
+    parameter mode_side1 = 0;
+    parameter mode_side2 = 0;
+    parameter pads_dict = "";
+    parameter pads_path = "";
+    parameter sel_clk_out1 = 1'b0;
+    parameter sel_clk_out2 = 1'b0;
+    parameter sel_clkr_rx1 = 1'b0;
+    parameter sel_clkr_rx2 = 1'b0;
+    parameter sel_clkw_rx1 = 2'b00;
+    parameter sel_clkw_rx2 = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_IOM_SERDES(RTCK, WRCK, WTCK, RRCK, TRST, RRST, CTCK, DCK, DRL, DIG, FZ, FLD, FLG, DS, DRA, DRI, DRO, DID, LINKN, LINKP);
+    input CTCK;
+    input DCK;
+    output [5:0] DID;
+    input DIG;
+    input [5:0] DRA;
+    input [5:0] DRI;
+    input DRL;
+    output [5:0] DRO;
+    input [1:0] DS;
+    output FLD;
+    output FLG;
+    input FZ;
+    inout [41:0] LINKN;
+    inout [41:0] LINKP;
+    input RRCK;
+    input RRST;
+    input RTCK;
+    input TRST;
+    input WRCK;
+    input WTCK;
+    parameter data_size = 5;
+    parameter location = "";
+endmodule
+
+(* blackbox *)
+module NX_IOM_SERDES_M(RTCK, WRCK, WTCK, RRCK, TRST, RRST, CTCK, DCK, DRL, DIG, FZ, FLD, FLG, DS, DRA, DRI, DRO, DID, LINKN, LINKP);
+    input CTCK;
+    input DCK;
+    output [5:0] DID;
+    input DIG;
+    input [5:0] DRA;
+    input [5:0] DRI;
+    input DRL;
+    output [5:0] DRO;
+    input [1:0] DS;
+    output FLD;
+    output FLG;
+    input FZ;
+    inout [41:0] LINKN;
+    inout [41:0] LINKP;
+    input RRCK;
+    input RRST;
+    input RTCK;
+    input TRST;
+    input WRCK;
+    input WTCK;
+    parameter data_size = 5;
+    parameter location = "";
+endmodule
+
+(* blackbox *)
+module NX_IOM_SERDES_U(FCK, SCK, LDRN, DRWDS, DRWEN, DRE, FZ, ALD, ALT, FLD, FLG, LINK, DRA, DRI, DRO, DID, DRIN, DRDN, FA, DRON);
+    output ALD;
+    output ALT;
+    output [5:0] DID;
+    input [3:0] DRA;
+    input [2:0] DRDN;
+    input DRE;
+    input [5:0] DRI;
+    input [2:0] DRIN;
+    output [5:0] DRO;
+    input [2:0] DRON;
+    input DRWDS;
+    input DRWEN;
+    input [5:0] FA;
+    input FCK;
+    output FLD;
+    output FLG;
+    input FZ;
+    input LDRN;
+    inout [41:0] LINK;
+    input SCK;
+    parameter data_size = 5;
+    parameter location = "";
+endmodule
+
+(* blackbox *)
+module NX_IOM_U(ALCK1, ALCK2, ALCK3, LDSCK1, LDSCK2, LDSCK3, SWRX1CK, SWRX2CK, FCK1, FCK2, FDCK, CCK, DQ1CI1, DQ1CI2, DQ1CI3, DQ1CI4, DQ1CI5, DQ1CI6, DQ1CI7, DQ1CI8, DQ2CI1
+, DQ2CI2, DQ2CI3, DQ2CI4, DQ2CI5, DQ2CI6, DQ2CI7, DQ2CI8, DQ3CI1, DQ3CI2, DQ3CI3, DQ3CI4, DQ3CI5, DQ3CI6, DQ3CI7, DQ3CI8, DQS1CI1, DQS1CI2, DQS1CI3, DQS1CI4, DQS1CI5, DQS1CI6
+, DQS1CI7, DQS1CI8, DQS2CI1, DQS2CI2, DQS2CI3, DQS2CI4, DQS2CI5, DQS2CI6, DQS2CI7, DQS2CI8, DQS3CI1, DQS3CI2, DQS3CI3, DQS3CI4, DQS3CI5, DQS3CI6, DQS3CI7, DQS3CI8, LD1RN, LD2RN, LD3RN
+, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DCRN, LE, SE, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4, DRO1CSN
+, DRO2CSN, DRO3CSN, DRI1CSN, DRI2CSN, DRI3CSN, DRDPA1CSN, DRDPA2CSN, DRDPA3CSN, DRCCSN, DRWDS, DRWEN, DRE, CA1P1, CA1P2, CA1P3, CA1P4, CA2P1, CA2P2, CA2P3, CA2P4, CA1N1
+, CA1N2, CA1N3, CA1N4, CA2N1, CA2N2, CA2N3, CA2N4, CA1T1, CA1T2, CA1T3, CA1T4, CA2T1, CA2T2, CA2T3, CA2T4, CA1D1, CA1D2, CA1D3, CA1D4, CA1D5, CA1D6
+, CA2D1, CA2D2, CA2D3, CA2D4, CA2D5, CA2D6, CKO1, CKO2, FLD, FLG, AL1D, AL2D, AL3D, AL1T, AL2T, AL3T, DCL, DRO1, DRO2, DRO3, DRO4
+, DRO5, DRO6, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EI6, P1EI7, P1EI8, P1EL, P1ER, P1EO, P1RI, P1RL
+, P1RR, P1RO1, P1RO2, P1RO3, P1RO4, P1RO5, P1RO6, P1RO7, P1RO8, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EI6
+, P2EI7, P2EI8, P2EL, P2ER, P2EO, P2RI, P2RL, P2RR, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P2RO6, P2RO7, P2RO8, P3CI1, P3CL, P3CR, P3CO, P3CTI
+, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EI6, P3EI7, P3EI8, P3EL, P3ER, P3EO, P3RI, P3RL, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P3RO6
+, P3RO7, P3RO8, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EI6, P4EI7, P4EI8, P4EL, P4ER, P4EO, P4RI, P4RL
+, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P4RO6, P4RO7, P4RO8, P5CI1, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3, P5EI4, P5EI5, P5EI6
+, P5EI7, P5EI8, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P5RO6, P5RO7, P5RO8, P6CI1, P6CL, P6CR, P6CO, P6CTI
+, P6CTO, P6EI1, P6EI2, P6EI3, P6EI4, P6EI5, P6EI6, P6EI7, P6EI8, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P6RO6
+, P6RO7, P6RO8, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1, P7EI2, P7EI3, P7EI4, P7EI5, P7EI6, P7EI7, P7EI8, P7EL, P7ER, P7EO, P7RI, P7RL
+, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P7RO6, P7RO7, P7RO8, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO, P8EI1, P8EI2, P8EI3, P8EI4, P8EI5, P8EI6
+, P8EI7, P8EI8, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P8RO6, P8RO7, P8RO8, P9CI1, P9CL, P9CR, P9CO, P9CTI
+, P9CTO, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EI6, P9EI7, P9EI8, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P9RO6
+, P9RO7, P9RO8, P10CI1, P10CL, P10CR, P10CO, P10CTI, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EI6, P10EI7, P10EI8, P10EL, P10ER, P10EO, P10RI, P10RL
+, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P10RO6, P10RO7, P10RO8, P11CI1, P11CL, P11CR, P11CO, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EI6
+, P11EI7, P11EI8, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P11RO6, P11RO7, P11RO8, P12CI1, P12CL, P12CR, P12CO, P12CTI
+, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EI6, P12EI7, P12EI8, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P12RO6
+, P12RO7, P12RO8, P13CI1, P13CL, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EI6, P13EI7, P13EI8, P13EL, P13ER, P13EO, P13RI, P13RL
+, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5, P13RO6, P13RO7, P13RO8, P14CI1, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EI6
+, P14EI7, P14EI8, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4, P14RO5, P14RO6, P14RO7, P14RO8, P15CI1, P15CL, P15CR, P15CO, P15CTI
+, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EI6, P15EI7, P15EI8, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3, P15RO4, P15RO5, P15RO6
+, P15RO7, P15RO8, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EI6, P16EI7, P16EI8, P16EL, P16ER, P16EO, P16RI, P16RL
+, P16RR, P16RO1, P16RO2, P16RO3, P16RO4, P16RO5, P16RO6, P16RO7, P16RO8, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EI6
+, P17EI7, P17EI8, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1, P17RO2, P17RO3, P17RO4, P17RO5, P17RO6, P17RO7, P17RO8, P18CI1, P18CL, P18CR, P18CO, P18CTI
+, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EI6, P18EI7, P18EI8, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR, P18RO1, P18RO2, P18RO3, P18RO4, P18RO5, P18RO6
+, P18RO7, P18RO8, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EI6, P19EI7, P19EI8, P19EL, P19ER, P19EO, P19RI, P19RL
+, P19RR, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P19RO6, P19RO7, P19RO8, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EI6
+, P20EI7, P20EI8, P20EL, P20ER, P20EO, P20RI, P20RL, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P20RO6, P20RO7, P20RO8, P21CI1, P21CL, P21CR, P21CO, P21CTI
+, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EI6, P21EI7, P21EI8, P21EL, P21ER, P21EO, P21RI, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P21RO6
+, P21RO7, P21RO8, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EI6, P22EI7, P22EI8, P22EL, P22ER, P22EO, P22RI, P22RL
+, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P22RO6, P22RO7, P22RO8, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EI6
+, P23EI7, P23EI8, P23EL, P23ER, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P23RO6, P23RO7, P23RO8, P24CI1, P24CL, P24CR, P24CO, P24CTI
+, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5, P24EI6, P24EI7, P24EI8, P24EL, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P24RO6
+, P24RO7, P24RO8, P25CI1, P25CL, P25CR, P25CO, P25CTI, P25CTO, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5, P25EI6, P25EI7, P25EI8, P25EL, P25ER, P25EO, P25RI, P25RL
+, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P25RO6, P25RO7, P25RO8, P26CI1, P26CL, P26CR, P26CO, P26CTI, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4, P26EI5, P26EI6
+, P26EI7, P26EI8, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P26RO6, P26RO7, P26RO8, P27CI1, P27CL, P27CR, P27CO, P27CTI
+, P27CTO, P27EI1, P27EI2, P27EI3, P27EI4, P27EI5, P27EI6, P27EI7, P27EI8, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P27RO6
+, P27RO7, P27RO8, P28CI1, P28CL, P28CR, P28CO, P28CTI, P28CTO, P28EI1, P28EI2, P28EI3, P28EI4, P28EI5, P28EI6, P28EI7, P28EI8, P28EL, P28ER, P28EO, P28RI, P28RL
+, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P28RO6, P28RO7, P28RO8, P29CI1, P29CL, P29CR, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EI6
+, P29EI7, P29EI8, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P29RO6, P29RO7, P29RO8, P30CI1, P30CL, P30CR, P30CO, P30CTI
+, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EI6, P30EI7, P30EI8, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5, P30RO6
+, P30RO7, P30RO8, P31CI1, P31CL, P31CR, P31CO, P31CTI, P31CTO, P31EI1, P31EI2, P31EI3, P31EI4, P31EI5, P31EI6, P31EI7, P31EI8, P31EL, P31ER, P31EO, P31RI, P31RL
+, P31RR, P31RO1, P31RO2, P31RO3, P31RO4, P31RO5, P31RO6, P31RO7, P31RO8, P32CI1, P32CL, P32CR, P32CO, P32CTI, P32CTO, P32EI1, P32EI2, P32EI3, P32EI4, P32EI5, P32EI6
+, P32EI7, P32EI8, P32EL, P32ER, P32EO, P32RI, P32RL, P32RR, P32RO1, P32RO2, P32RO3, P32RO4, P32RO5, P32RO6, P32RO7, P32RO8, P33CI1, P33CL, P33CR, P33CO, P33CTI
+, P33CTO, P33EI1, P33EI2, P33EI3, P33EI4, P33EI5, P33EI6, P33EI7, P33EI8, P33EL, P33ER, P33EO, P33RI, P33RL, P33RR, P33RO1, P33RO2, P33RO3, P33RO4, P33RO5, P33RO6
+, P33RO7, P33RO8, P34CI1, P34CL, P34CR, P34CO, P34CTI, P34CTO, P34EI1, P34EI2, P34EI3, P34EI4, P34EI5, P34EI6, P34EI7, P34EI8, P34EL, P34ER, P34EO, P34RI, P34RL
+, P34RR, P34RO1, P34RO2, P34RO3, P34RO4, P34RO5, P34RO6, P34RO7, P34RO8);
+    output AL1D;
+    output AL1T;
+    output AL2D;
+    output AL2T;
+    output AL3D;
+    output AL3T;
+    input ALCK1;
+    input ALCK2;
+    input ALCK3;
+    input CA1D1;
+    input CA1D2;
+    input CA1D3;
+    input CA1D4;
+    input CA1D5;
+    input CA1D6;
+    input CA1N1;
+    input CA1N2;
+    input CA1N3;
+    input CA1N4;
+    input CA1P1;
+    input CA1P2;
+    input CA1P3;
+    input CA1P4;
+    input CA1T1;
+    input CA1T2;
+    input CA1T3;
+    input CA1T4;
+    input CA2D1;
+    input CA2D2;
+    input CA2D3;
+    input CA2D4;
+    input CA2D5;
+    input CA2D6;
+    input CA2N1;
+    input CA2N2;
+    input CA2N3;
+    input CA2N4;
+    input CA2P1;
+    input CA2P2;
+    input CA2P3;
+    input CA2P4;
+    input CA2T1;
+    input CA2T2;
+    input CA2T3;
+    input CA2T4;
+    input CCK;
+    output CKO1;
+    output CKO2;
+    output DCL;
+    input DCRN;
+    input DQ1CI1;
+    input DQ1CI2;
+    input DQ1CI3;
+    input DQ1CI4;
+    input DQ1CI5;
+    input DQ1CI6;
+    input DQ1CI7;
+    input DQ1CI8;
+    input DQ2CI1;
+    input DQ2CI2;
+    input DQ2CI3;
+    input DQ2CI4;
+    input DQ2CI5;
+    input DQ2CI6;
+    input DQ2CI7;
+    input DQ2CI8;
+    input DQ3CI1;
+    input DQ3CI2;
+    input DQ3CI3;
+    input DQ3CI4;
+    input DQ3CI5;
+    input DQ3CI6;
+    input DQ3CI7;
+    input DQ3CI8;
+    input DQS1CI1;
+    input DQS1CI2;
+    input DQS1CI3;
+    input DQS1CI4;
+    input DQS1CI5;
+    input DQS1CI6;
+    input DQS1CI7;
+    input DQS1CI8;
+    input DQS2CI1;
+    input DQS2CI2;
+    input DQS2CI3;
+    input DQS2CI4;
+    input DQS2CI5;
+    input DQS2CI6;
+    input DQS2CI7;
+    input DQS2CI8;
+    input DQS3CI1;
+    input DQS3CI2;
+    input DQS3CI3;
+    input DQS3CI4;
+    input DQS3CI5;
+    input DQS3CI6;
+    input DQS3CI7;
+    input DQS3CI8;
+    input DRA1;
+    input DRA2;
+    input DRA3;
+    input DRA4;
+    input DRCCSN;
+    input DRDPA1CSN;
+    input DRDPA2CSN;
+    input DRDPA3CSN;
+    input DRE;
+    input DRI1;
+    input DRI1CSN;
+    input DRI2;
+    input DRI2CSN;
+    input DRI3;
+    input DRI3CSN;
+    input DRI4;
+    input DRI5;
+    input DRI6;
+    output DRO1;
+    input DRO1CSN;
+    output DRO2;
+    input DRO2CSN;
+    output DRO3;
+    input DRO3CSN;
+    output DRO4;
+    output DRO5;
+    output DRO6;
+    input DRWDS;
+    input DRWEN;
+    input FA1;
+    input FA2;
+    input FA3;
+    input FA4;
+    input FA5;
+    input FA6;
+    input FCK1;
+    input FCK2;
+    input FDCK;
+    output FLD;
+    output FLG;
+    input FZ;
+    input LD1RN;
+    input LD2RN;
+    input LD3RN;
+    input LDSCK1;
+    input LDSCK2;
+    input LDSCK3;
+    input LE;
+    input P10CI1;
+    input P10CL;
+    output P10CO;
+    input P10CR;
+    input P10CTI;
+    output P10CTO;
+    input P10EI1;
+    input P10EI2;
+    input P10EI3;
+    input P10EI4;
+    input P10EI5;
+    input P10EI6;
+    input P10EI7;
+    input P10EI8;
+    input P10EL;
+    output P10EO;
+    input P10ER;
+    input P10RI;
+    input P10RL;
+    output P10RO1;
+    output P10RO2;
+    output P10RO3;
+    output P10RO4;
+    output P10RO5;
+    output P10RO6;
+    output P10RO7;
+    output P10RO8;
+    input P10RR;
+    input P11CI1;
+    input P11CL;
+    output P11CO;
+    input P11CR;
+    input P11CTI;
+    output P11CTO;
+    input P11EI1;
+    input P11EI2;
+    input P11EI3;
+    input P11EI4;
+    input P11EI5;
+    input P11EI6;
+    input P11EI7;
+    input P11EI8;
+    input P11EL;
+    output P11EO;
+    input P11ER;
+    input P11RI;
+    input P11RL;
+    output P11RO1;
+    output P11RO2;
+    output P11RO3;
+    output P11RO4;
+    output P11RO5;
+    output P11RO6;
+    output P11RO7;
+    output P11RO8;
+    input P11RR;
+    input P12CI1;
+    input P12CL;
+    output P12CO;
+    input P12CR;
+    input P12CTI;
+    output P12CTO;
+    input P12EI1;
+    input P12EI2;
+    input P12EI3;
+    input P12EI4;
+    input P12EI5;
+    input P12EI6;
+    input P12EI7;
+    input P12EI8;
+    input P12EL;
+    output P12EO;
+    input P12ER;
+    input P12RI;
+    input P12RL;
+    output P12RO1;
+    output P12RO2;
+    output P12RO3;
+    output P12RO4;
+    output P12RO5;
+    output P12RO6;
+    output P12RO7;
+    output P12RO8;
+    input P12RR;
+    input P13CI1;
+    input P13CL;
+    output P13CO;
+    input P13CR;
+    input P13CTI;
+    output P13CTO;
+    input P13EI1;
+    input P13EI2;
+    input P13EI3;
+    input P13EI4;
+    input P13EI5;
+    input P13EI6;
+    input P13EI7;
+    input P13EI8;
+    input P13EL;
+    output P13EO;
+    input P13ER;
+    input P13RI;
+    input P13RL;
+    output P13RO1;
+    output P13RO2;
+    output P13RO3;
+    output P13RO4;
+    output P13RO5;
+    output P13RO6;
+    output P13RO7;
+    output P13RO8;
+    input P13RR;
+    input P14CI1;
+    input P14CL;
+    output P14CO;
+    input P14CR;
+    input P14CTI;
+    output P14CTO;
+    input P14EI1;
+    input P14EI2;
+    input P14EI3;
+    input P14EI4;
+    input P14EI5;
+    input P14EI6;
+    input P14EI7;
+    input P14EI8;
+    input P14EL;
+    output P14EO;
+    input P14ER;
+    input P14RI;
+    input P14RL;
+    output P14RO1;
+    output P14RO2;
+    output P14RO3;
+    output P14RO4;
+    output P14RO5;
+    output P14RO6;
+    output P14RO7;
+    output P14RO8;
+    input P14RR;
+    input P15CI1;
+    input P15CL;
+    output P15CO;
+    input P15CR;
+    input P15CTI;
+    output P15CTO;
+    input P15EI1;
+    input P15EI2;
+    input P15EI3;
+    input P15EI4;
+    input P15EI5;
+    input P15EI6;
+    input P15EI7;
+    input P15EI8;
+    input P15EL;
+    output P15EO;
+    input P15ER;
+    input P15RI;
+    input P15RL;
+    output P15RO1;
+    output P15RO2;
+    output P15RO3;
+    output P15RO4;
+    output P15RO5;
+    output P15RO6;
+    output P15RO7;
+    output P15RO8;
+    input P15RR;
+    input P16CI1;
+    input P16CL;
+    output P16CO;
+    input P16CR;
+    input P16CTI;
+    output P16CTO;
+    input P16EI1;
+    input P16EI2;
+    input P16EI3;
+    input P16EI4;
+    input P16EI5;
+    input P16EI6;
+    input P16EI7;
+    input P16EI8;
+    input P16EL;
+    output P16EO;
+    input P16ER;
+    input P16RI;
+    input P16RL;
+    output P16RO1;
+    output P16RO2;
+    output P16RO3;
+    output P16RO4;
+    output P16RO5;
+    output P16RO6;
+    output P16RO7;
+    output P16RO8;
+    input P16RR;
+    input P17CI1;
+    input P17CL;
+    output P17CO;
+    input P17CR;
+    input P17CTI;
+    output P17CTO;
+    input P17EI1;
+    input P17EI2;
+    input P17EI3;
+    input P17EI4;
+    input P17EI5;
+    input P17EI6;
+    input P17EI7;
+    input P17EI8;
+    input P17EL;
+    output P17EO;
+    input P17ER;
+    input P17RI;
+    input P17RL;
+    output P17RO1;
+    output P17RO2;
+    output P17RO3;
+    output P17RO4;
+    output P17RO5;
+    output P17RO6;
+    output P17RO7;
+    output P17RO8;
+    input P17RR;
+    input P18CI1;
+    input P18CL;
+    output P18CO;
+    input P18CR;
+    input P18CTI;
+    output P18CTO;
+    input P18EI1;
+    input P18EI2;
+    input P18EI3;
+    input P18EI4;
+    input P18EI5;
+    input P18EI6;
+    input P18EI7;
+    input P18EI8;
+    input P18EL;
+    output P18EO;
+    input P18ER;
+    input P18RI;
+    input P18RL;
+    output P18RO1;
+    output P18RO2;
+    output P18RO3;
+    output P18RO4;
+    output P18RO5;
+    output P18RO6;
+    output P18RO7;
+    output P18RO8;
+    input P18RR;
+    input P19CI1;
+    input P19CL;
+    output P19CO;
+    input P19CR;
+    input P19CTI;
+    output P19CTO;
+    input P19EI1;
+    input P19EI2;
+    input P19EI3;
+    input P19EI4;
+    input P19EI5;
+    input P19EI6;
+    input P19EI7;
+    input P19EI8;
+    input P19EL;
+    output P19EO;
+    input P19ER;
+    input P19RI;
+    input P19RL;
+    output P19RO1;
+    output P19RO2;
+    output P19RO3;
+    output P19RO4;
+    output P19RO5;
+    output P19RO6;
+    output P19RO7;
+    output P19RO8;
+    input P19RR;
+    input P1CI1;
+    input P1CL;
+    output P1CO;
+    input P1CR;
+    input P1CTI;
+    output P1CTO;
+    input P1EI1;
+    input P1EI2;
+    input P1EI3;
+    input P1EI4;
+    input P1EI5;
+    input P1EI6;
+    input P1EI7;
+    input P1EI8;
+    input P1EL;
+    output P1EO;
+    input P1ER;
+    input P1RI;
+    input P1RL;
+    output P1RO1;
+    output P1RO2;
+    output P1RO3;
+    output P1RO4;
+    output P1RO5;
+    output P1RO6;
+    output P1RO7;
+    output P1RO8;
+    input P1RR;
+    input P20CI1;
+    input P20CL;
+    output P20CO;
+    input P20CR;
+    input P20CTI;
+    output P20CTO;
+    input P20EI1;
+    input P20EI2;
+    input P20EI3;
+    input P20EI4;
+    input P20EI5;
+    input P20EI6;
+    input P20EI7;
+    input P20EI8;
+    input P20EL;
+    output P20EO;
+    input P20ER;
+    input P20RI;
+    input P20RL;
+    output P20RO1;
+    output P20RO2;
+    output P20RO3;
+    output P20RO4;
+    output P20RO5;
+    output P20RO6;
+    output P20RO7;
+    output P20RO8;
+    input P20RR;
+    input P21CI1;
+    input P21CL;
+    output P21CO;
+    input P21CR;
+    input P21CTI;
+    output P21CTO;
+    input P21EI1;
+    input P21EI2;
+    input P21EI3;
+    input P21EI4;
+    input P21EI5;
+    input P21EI6;
+    input P21EI7;
+    input P21EI8;
+    input P21EL;
+    output P21EO;
+    input P21ER;
+    input P21RI;
+    input P21RL;
+    output P21RO1;
+    output P21RO2;
+    output P21RO3;
+    output P21RO4;
+    output P21RO5;
+    output P21RO6;
+    output P21RO7;
+    output P21RO8;
+    input P21RR;
+    input P22CI1;
+    input P22CL;
+    output P22CO;
+    input P22CR;
+    input P22CTI;
+    output P22CTO;
+    input P22EI1;
+    input P22EI2;
+    input P22EI3;
+    input P22EI4;
+    input P22EI5;
+    input P22EI6;
+    input P22EI7;
+    input P22EI8;
+    input P22EL;
+    output P22EO;
+    input P22ER;
+    input P22RI;
+    input P22RL;
+    output P22RO1;
+    output P22RO2;
+    output P22RO3;
+    output P22RO4;
+    output P22RO5;
+    output P22RO6;
+    output P22RO7;
+    output P22RO8;
+    input P22RR;
+    input P23CI1;
+    input P23CL;
+    output P23CO;
+    input P23CR;
+    input P23CTI;
+    output P23CTO;
+    input P23EI1;
+    input P23EI2;
+    input P23EI3;
+    input P23EI4;
+    input P23EI5;
+    input P23EI6;
+    input P23EI7;
+    input P23EI8;
+    input P23EL;
+    output P23EO;
+    input P23ER;
+    input P23RI;
+    input P23RL;
+    output P23RO1;
+    output P23RO2;
+    output P23RO3;
+    output P23RO4;
+    output P23RO5;
+    output P23RO6;
+    output P23RO7;
+    output P23RO8;
+    input P23RR;
+    input P24CI1;
+    input P24CL;
+    output P24CO;
+    input P24CR;
+    input P24CTI;
+    output P24CTO;
+    input P24EI1;
+    input P24EI2;
+    input P24EI3;
+    input P24EI4;
+    input P24EI5;
+    input P24EI6;
+    input P24EI7;
+    input P24EI8;
+    input P24EL;
+    output P24EO;
+    input P24ER;
+    input P24RI;
+    input P24RL;
+    output P24RO1;
+    output P24RO2;
+    output P24RO3;
+    output P24RO4;
+    output P24RO5;
+    output P24RO6;
+    output P24RO7;
+    output P24RO8;
+    input P24RR;
+    input P25CI1;
+    input P25CL;
+    output P25CO;
+    input P25CR;
+    input P25CTI;
+    output P25CTO;
+    input P25EI1;
+    input P25EI2;
+    input P25EI3;
+    input P25EI4;
+    input P25EI5;
+    input P25EI6;
+    input P25EI7;
+    input P25EI8;
+    input P25EL;
+    output P25EO;
+    input P25ER;
+    input P25RI;
+    input P25RL;
+    output P25RO1;
+    output P25RO2;
+    output P25RO3;
+    output P25RO4;
+    output P25RO5;
+    output P25RO6;
+    output P25RO7;
+    output P25RO8;
+    input P25RR;
+    input P26CI1;
+    input P26CL;
+    output P26CO;
+    input P26CR;
+    input P26CTI;
+    output P26CTO;
+    input P26EI1;
+    input P26EI2;
+    input P26EI3;
+    input P26EI4;
+    input P26EI5;
+    input P26EI6;
+    input P26EI7;
+    input P26EI8;
+    input P26EL;
+    output P26EO;
+    input P26ER;
+    input P26RI;
+    input P26RL;
+    output P26RO1;
+    output P26RO2;
+    output P26RO3;
+    output P26RO4;
+    output P26RO5;
+    output P26RO6;
+    output P26RO7;
+    output P26RO8;
+    input P26RR;
+    input P27CI1;
+    input P27CL;
+    output P27CO;
+    input P27CR;
+    input P27CTI;
+    output P27CTO;
+    input P27EI1;
+    input P27EI2;
+    input P27EI3;
+    input P27EI4;
+    input P27EI5;
+    input P27EI6;
+    input P27EI7;
+    input P27EI8;
+    input P27EL;
+    output P27EO;
+    input P27ER;
+    input P27RI;
+    input P27RL;
+    output P27RO1;
+    output P27RO2;
+    output P27RO3;
+    output P27RO4;
+    output P27RO5;
+    output P27RO6;
+    output P27RO7;
+    output P27RO8;
+    input P27RR;
+    input P28CI1;
+    input P28CL;
+    output P28CO;
+    input P28CR;
+    input P28CTI;
+    output P28CTO;
+    input P28EI1;
+    input P28EI2;
+    input P28EI3;
+    input P28EI4;
+    input P28EI5;
+    input P28EI6;
+    input P28EI7;
+    input P28EI8;
+    input P28EL;
+    output P28EO;
+    input P28ER;
+    input P28RI;
+    input P28RL;
+    output P28RO1;
+    output P28RO2;
+    output P28RO3;
+    output P28RO4;
+    output P28RO5;
+    output P28RO6;
+    output P28RO7;
+    output P28RO8;
+    input P28RR;
+    input P29CI1;
+    input P29CL;
+    output P29CO;
+    input P29CR;
+    input P29CTI;
+    output P29CTO;
+    input P29EI1;
+    input P29EI2;
+    input P29EI3;
+    input P29EI4;
+    input P29EI5;
+    input P29EI6;
+    input P29EI7;
+    input P29EI8;
+    input P29EL;
+    output P29EO;
+    input P29ER;
+    input P29RI;
+    input P29RL;
+    output P29RO1;
+    output P29RO2;
+    output P29RO3;
+    output P29RO4;
+    output P29RO5;
+    output P29RO6;
+    output P29RO7;
+    output P29RO8;
+    input P29RR;
+    input P2CI1;
+    input P2CL;
+    output P2CO;
+    input P2CR;
+    input P2CTI;
+    output P2CTO;
+    input P2EI1;
+    input P2EI2;
+    input P2EI3;
+    input P2EI4;
+    input P2EI5;
+    input P2EI6;
+    input P2EI7;
+    input P2EI8;
+    input P2EL;
+    output P2EO;
+    input P2ER;
+    input P2RI;
+    input P2RL;
+    output P2RO1;
+    output P2RO2;
+    output P2RO3;
+    output P2RO4;
+    output P2RO5;
+    output P2RO6;
+    output P2RO7;
+    output P2RO8;
+    input P2RR;
+    input P30CI1;
+    input P30CL;
+    output P30CO;
+    input P30CR;
+    input P30CTI;
+    output P30CTO;
+    input P30EI1;
+    input P30EI2;
+    input P30EI3;
+    input P30EI4;
+    input P30EI5;
+    input P30EI6;
+    input P30EI7;
+    input P30EI8;
+    input P30EL;
+    output P30EO;
+    input P30ER;
+    input P30RI;
+    input P30RL;
+    output P30RO1;
+    output P30RO2;
+    output P30RO3;
+    output P30RO4;
+    output P30RO5;
+    output P30RO6;
+    output P30RO7;
+    output P30RO8;
+    input P30RR;
+    input P31CI1;
+    input P31CL;
+    output P31CO;
+    input P31CR;
+    input P31CTI;
+    output P31CTO;
+    input P31EI1;
+    input P31EI2;
+    input P31EI3;
+    input P31EI4;
+    input P31EI5;
+    input P31EI6;
+    input P31EI7;
+    input P31EI8;
+    input P31EL;
+    output P31EO;
+    input P31ER;
+    input P31RI;
+    input P31RL;
+    output P31RO1;
+    output P31RO2;
+    output P31RO3;
+    output P31RO4;
+    output P31RO5;
+    output P31RO6;
+    output P31RO7;
+    output P31RO8;
+    input P31RR;
+    input P32CI1;
+    input P32CL;
+    output P32CO;
+    input P32CR;
+    input P32CTI;
+    output P32CTO;
+    input P32EI1;
+    input P32EI2;
+    input P32EI3;
+    input P32EI4;
+    input P32EI5;
+    input P32EI6;
+    input P32EI7;
+    input P32EI8;
+    input P32EL;
+    output P32EO;
+    input P32ER;
+    input P32RI;
+    input P32RL;
+    output P32RO1;
+    output P32RO2;
+    output P32RO3;
+    output P32RO4;
+    output P32RO5;
+    output P32RO6;
+    output P32RO7;
+    output P32RO8;
+    input P32RR;
+    input P33CI1;
+    input P33CL;
+    output P33CO;
+    input P33CR;
+    input P33CTI;
+    output P33CTO;
+    input P33EI1;
+    input P33EI2;
+    input P33EI3;
+    input P33EI4;
+    input P33EI5;
+    input P33EI6;
+    input P33EI7;
+    input P33EI8;
+    input P33EL;
+    output P33EO;
+    input P33ER;
+    input P33RI;
+    input P33RL;
+    output P33RO1;
+    output P33RO2;
+    output P33RO3;
+    output P33RO4;
+    output P33RO5;
+    output P33RO6;
+    output P33RO7;
+    output P33RO8;
+    input P33RR;
+    input P34CI1;
+    input P34CL;
+    output P34CO;
+    input P34CR;
+    input P34CTI;
+    output P34CTO;
+    input P34EI1;
+    input P34EI2;
+    input P34EI3;
+    input P34EI4;
+    input P34EI5;
+    input P34EI6;
+    input P34EI7;
+    input P34EI8;
+    input P34EL;
+    output P34EO;
+    input P34ER;
+    input P34RI;
+    input P34RL;
+    output P34RO1;
+    output P34RO2;
+    output P34RO3;
+    output P34RO4;
+    output P34RO5;
+    output P34RO6;
+    output P34RO7;
+    output P34RO8;
+    input P34RR;
+    input P3CI1;
+    input P3CL;
+    output P3CO;
+    input P3CR;
+    input P3CTI;
+    output P3CTO;
+    input P3EI1;
+    input P3EI2;
+    input P3EI3;
+    input P3EI4;
+    input P3EI5;
+    input P3EI6;
+    input P3EI7;
+    input P3EI8;
+    input P3EL;
+    output P3EO;
+    input P3ER;
+    input P3RI;
+    input P3RL;
+    output P3RO1;
+    output P3RO2;
+    output P3RO3;
+    output P3RO4;
+    output P3RO5;
+    output P3RO6;
+    output P3RO7;
+    output P3RO8;
+    input P3RR;
+    input P4CI1;
+    input P4CL;
+    output P4CO;
+    input P4CR;
+    input P4CTI;
+    output P4CTO;
+    input P4EI1;
+    input P4EI2;
+    input P4EI3;
+    input P4EI4;
+    input P4EI5;
+    input P4EI6;
+    input P4EI7;
+    input P4EI8;
+    input P4EL;
+    output P4EO;
+    input P4ER;
+    input P4RI;
+    input P4RL;
+    output P4RO1;
+    output P4RO2;
+    output P4RO3;
+    output P4RO4;
+    output P4RO5;
+    output P4RO6;
+    output P4RO7;
+    output P4RO8;
+    input P4RR;
+    input P5CI1;
+    input P5CL;
+    output P5CO;
+    input P5CR;
+    input P5CTI;
+    output P5CTO;
+    input P5EI1;
+    input P5EI2;
+    input P5EI3;
+    input P5EI4;
+    input P5EI5;
+    input P5EI6;
+    input P5EI7;
+    input P5EI8;
+    input P5EL;
+    output P5EO;
+    input P5ER;
+    input P5RI;
+    input P5RL;
+    output P5RO1;
+    output P5RO2;
+    output P5RO3;
+    output P5RO4;
+    output P5RO5;
+    output P5RO6;
+    output P5RO7;
+    output P5RO8;
+    input P5RR;
+    input P6CI1;
+    input P6CL;
+    output P6CO;
+    input P6CR;
+    input P6CTI;
+    output P6CTO;
+    input P6EI1;
+    input P6EI2;
+    input P6EI3;
+    input P6EI4;
+    input P6EI5;
+    input P6EI6;
+    input P6EI7;
+    input P6EI8;
+    input P6EL;
+    output P6EO;
+    input P6ER;
+    input P6RI;
+    input P6RL;
+    output P6RO1;
+    output P6RO2;
+    output P6RO3;
+    output P6RO4;
+    output P6RO5;
+    output P6RO6;
+    output P6RO7;
+    output P6RO8;
+    input P6RR;
+    input P7CI1;
+    input P7CL;
+    output P7CO;
+    input P7CR;
+    input P7CTI;
+    output P7CTO;
+    input P7EI1;
+    input P7EI2;
+    input P7EI3;
+    input P7EI4;
+    input P7EI5;
+    input P7EI6;
+    input P7EI7;
+    input P7EI8;
+    input P7EL;
+    output P7EO;
+    input P7ER;
+    input P7RI;
+    input P7RL;
+    output P7RO1;
+    output P7RO2;
+    output P7RO3;
+    output P7RO4;
+    output P7RO5;
+    output P7RO6;
+    output P7RO7;
+    output P7RO8;
+    input P7RR;
+    input P8CI1;
+    input P8CL;
+    output P8CO;
+    input P8CR;
+    input P8CTI;
+    output P8CTO;
+    input P8EI1;
+    input P8EI2;
+    input P8EI3;
+    input P8EI4;
+    input P8EI5;
+    input P8EI6;
+    input P8EI7;
+    input P8EI8;
+    input P8EL;
+    output P8EO;
+    input P8ER;
+    input P8RI;
+    input P8RL;
+    output P8RO1;
+    output P8RO2;
+    output P8RO3;
+    output P8RO4;
+    output P8RO5;
+    output P8RO6;
+    output P8RO7;
+    output P8RO8;
+    input P8RR;
+    input P9CI1;
+    input P9CL;
+    output P9CO;
+    input P9CR;
+    input P9CTI;
+    output P9CTO;
+    input P9EI1;
+    input P9EI2;
+    input P9EI3;
+    input P9EI4;
+    input P9EI5;
+    input P9EI6;
+    input P9EI7;
+    input P9EI8;
+    input P9EL;
+    output P9EO;
+    input P9ER;
+    input P9RI;
+    input P9RL;
+    output P9RO1;
+    output P9RO2;
+    output P9RO3;
+    output P9RO4;
+    output P9RO5;
+    output P9RO6;
+    output P9RO7;
+    output P9RO8;
+    input P9RR;
+    input SE;
+    input SWRX1CK;
+    input SWRX2CK;
+    parameter cal_delay1 = "";
+    parameter cal_delay2 = "";
+    parameter div1 = 3'b000;
+    parameter div2 = 3'b000;
+    parameter div3 = 3'b000;
+    parameter div_swrx1 = 3'b000;
+    parameter div_swrx2 = 3'b000;
+    parameter inv_ld_sck1 = 1'b0;
+    parameter inv_ld_sck2 = 1'b0;
+    parameter inv_ld_sck3 = 1'b0;
+    parameter link_ld_12 = 1'b0;
+    parameter link_ld_23 = 1'b0;
+    parameter mode_side1 = 0;
+    parameter mode_side2 = 0;
+    parameter mode_side3 = 0;
+    parameter pads_dict = "";
+    parameter pads_path = "";
+    parameter sel_clk_out1 = 1'b0;
+    parameter sel_clk_out2 = 1'b0;
+    parameter sel_dc_clk = 2'b00;
+    parameter sel_ld_fck1 = 2'b00;
+    parameter sel_ld_fck2 = 2'b00;
+    parameter sel_ld_fck3 = 2'b00;
+    parameter sel_sw_fck1 = 2'b00;
+    parameter sel_sw_fck2 = 2'b00;
+    parameter use_dc = 1'b0;
+endmodule
+
+//(* blackbox *)
+//module NX_LUT(I1, I2, I3, I4, O);
+//    input I1;
+//    input I2;
+//    input I3;
+//    input I4;
+//    output O;
+//    parameter lut_table = 16'b0000000000000000;
+//endmodule
+
+(* blackbox *)
+module NX_PLL(REF, FBK, VCO, D1, D2, D3, OSC, RDY);
+    output D1;
+    output D2;
+    output D3;
+    input FBK;
+    output OSC;
+    output RDY;
+    input REF;
+    output VCO;
+    parameter clk_outdiv1 = 0;
+    parameter clk_outdiv2 = 0;
+    parameter clk_outdiv3 = 0;
+    parameter ext_fbk_on = 1'b0;
+    parameter fbk_delay = 0;
+    parameter fbk_delay_on = 1'b0;
+    parameter fbk_div_on = 1'b0;
+    parameter fbk_intdiv = 2;
+    parameter location = "";
+    parameter ref_div_on = 1'b0;
+    parameter vco_range = 0;
+endmodule
+
+(* blackbox *)
+module NX_PLL_L(REF, FBK, R, VCO, LDFO, REFO, DIVO1, DIVO2, DIVP1, DIVP2, DIVP3, OSC, PLL_LOCKED, CAL_LOCKED);
+    output CAL_LOCKED;
+    output DIVO1;
+    output DIVO2;
+    output DIVP1;
+    output DIVP2;
+    output DIVP3;
+    input FBK;
+    output LDFO;
+    output OSC;
+    output PLL_LOCKED;
+    input R;
+    input REF;
+    output REFO;
+    output VCO;
+    parameter cfg_use_pll = 1'b1;
+    parameter clk_outdivo1 = 0;
+    parameter clk_outdivp1 = 0;
+    parameter clk_outdivp2 = 0;
+    parameter clk_outdivp3o2 = 0;
+    parameter ext_fbk_on = 1'b0;
+    parameter fbk_delay = 0;
+    parameter fbk_delay_on = 1'b0;
+    parameter fbk_intdiv = 2;
+    parameter location = "";
+    parameter pll_cpump = 3'b010;
+    parameter ref_intdiv = 0;
+    parameter ref_osc_on = 1'b0;
+    parameter wfg_sync_cal_lock = 1'b0;
+    parameter wfg_sync_pll_lock = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_PLL_U(R, REF, FBK, OSC, VCO, LDFO, REFO, CLK_DIV1, CLK_DIV2, CLK_DIV3, CLK_DIV4, CLK_DIVD1, CLK_DIVD2, CLK_DIVD3, CLK_DIVD4, CLK_DIVD5, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV
+, CAL_LOCKED, EXT_CAL_LOCKED, CAL1, CAL2, CAL3, CAL4, CAL5, EXT_CAL1, EXT_CAL2, EXT_CAL3, EXT_CAL4, EXT_CAL5);
+    input ARST_CAL;
+    output CAL1;
+    output CAL2;
+    output CAL3;
+    output CAL4;
+    output CAL5;
+    output CAL_LOCKED;
+    input CLK_CAL;
+    output CLK_CAL_DIV;
+    output CLK_DIV1;
+    output CLK_DIV2;
+    output CLK_DIV3;
+    output CLK_DIV4;
+    output CLK_DIVD1;
+    output CLK_DIVD2;
+    output CLK_DIVD3;
+    output CLK_DIVD4;
+    output CLK_DIVD5;
+    input EXT_CAL1;
+    input EXT_CAL2;
+    input EXT_CAL3;
+    input EXT_CAL4;
+    input EXT_CAL5;
+    input EXT_CAL_LOCKED;
+    input FBK;
+    output LDFO;
+    output OSC;
+    output PLL_LOCKED;
+    output PLL_LOCKEDA;
+    input R;
+    input REF;
+    output REFO;
+    output VCO;
+    parameter cal_delay = 6'b011011;
+    parameter cal_div = 4'b0111;
+    parameter clk_cal_sel = 2'b01;
+    parameter clk_outdiv1 = 3'b000;
+    parameter clk_outdiv2 = 3'b000;
+    parameter clk_outdiv3 = 3'b000;
+    parameter clk_outdiv4 = 3'b000;
+    parameter clk_outdivd1 = 4'b0000;
+    parameter clk_outdivd2 = 4'b0000;
+    parameter clk_outdivd3 = 4'b0000;
+    parameter clk_outdivd4 = 4'b0000;
+    parameter clk_outdivd5 = 4'b0000;
+    parameter ext_fbk_on = 1'b0;
+    parameter fbk_delay = 6'b000000;
+    parameter fbk_delay_on = 1'b0;
+    parameter fbk_intdiv = 7'b0000000;
+    parameter location = "";
+    parameter pll_cpump = 4'b0000;
+    parameter pll_lock = 4'b0000;
+    parameter pll_lpf_cap = 4'b0000;
+    parameter pll_lpf_res = 4'b0000;
+    parameter pll_odf = 2'b00;
+    parameter ref_intdiv = 5'b00000;
+    parameter ref_osc_on = 1'b0;
+    parameter use_cal = 1'b0;
+    parameter use_pll = 1'b1;
+endmodule
+
+(* blackbox *)
+module NX_PLL_U_WRAP(R, REF, FBK, OSC, VCO, LDFO, REFO, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV, CAL_LOCKED, EXT_CAL_LOCKED, CAL, CLK_DIVD, EXT_CAL, CLK_DIV);
+    input ARST_CAL;
+    output [4:0] CAL;
+    output CAL_LOCKED;
+    input CLK_CAL;
+    output CLK_CAL_DIV;
+    output [3:0] CLK_DIV;
+    output [4:0] CLK_DIVD;
+    input [4:0] EXT_CAL;
+    input EXT_CAL_LOCKED;
+    input FBK;
+    output LDFO;
+    output OSC;
+    output PLL_LOCKED;
+    output PLL_LOCKEDA;
+    input R;
+    input REF;
+    output REFO;
+    output VCO;
+    parameter cal_delay = 6'b011011;
+    parameter cal_div = 4'b0111;
+    parameter clk_cal_sel = 2'b01;
+    parameter clk_outdiv1 = 3'b000;
+    parameter clk_outdiv2 = 3'b000;
+    parameter clk_outdiv3 = 3'b000;
+    parameter clk_outdiv4 = 3'b000;
+    parameter clk_outdivd1 = 4'b0000;
+    parameter clk_outdivd2 = 4'b0000;
+    parameter clk_outdivd3 = 4'b0000;
+    parameter clk_outdivd4 = 4'b0000;
+    parameter clk_outdivd5 = 4'b0000;
+    parameter ext_fbk_on = 1'b0;
+    parameter fbk_delay = 6'b000000;
+    parameter fbk_delay_on = 1'b0;
+    parameter fbk_intdiv = 7'b0000000;
+    parameter location = "";
+    parameter pll_cpump = 4'b0000;
+    parameter pll_lock = 4'b0000;
+    parameter pll_lpf_cap = 4'b0000;
+    parameter pll_lpf_res = 4'b0000;
+    parameter pll_odf = 2'b00;
+    parameter ref_intdiv = 5'b00000;
+    parameter ref_osc_on = 1'b0;
+    parameter use_cal = 1'b0;
+    parameter use_pll = 1'b1;
+endmodule
+
+(* blackbox *)
+module NX_PMA_L(CLK_USER_I, CLK_REF_I, PRE_SG_I, PRE_EN_I, PRE_IS_I1, PRE_IS_I2, PRE_IS_I3, PRE_IS_I4, MAIN_SG_I, MAIN_EN_I1, MAIN_EN_I2, MAIN_EN_I3, MAIN_EN_I4, MAIN_EN_I5, MAIN_EN_I6, MARG_S_I1, MARG_S_I2, MARG_S_I3, MARG_S_I4, MARG_IS_I1, MARG_IS_I2
+, MARG_IS_I3, MARG_IS_I4, MARG_SV_I1, MARG_SV_I2, MARG_SV_I3, MARG_SV_I4, MARG_SV_I5, MARG_ISV_I1, MARG_ISV_I2, MARG_ISV_I3, MARG_ISV_I4, MARG_ISV_I5, POST_EN_I1, POST_EN_I2, POST_EN_I3, POST_EN_I4, POST_EN_I5, POST_SG_I, POST_IS_I1, POST_IS_I2, POST_IS_I3
+, POST_IS_I4, POST_ISV_I1, POST_ISV_I2, POST_ISV_I3, POST_ISV_I4, TX_SEL_I1, TX_SEL_I2, TX_SEL_I3, TX_SEL_I4, TX_SEL_I5, TX_SEL_I6, CT_CAP_I1, CT_CAP_I2, CT_CAP_I3, CT_CAP_I4, CT_RESP_I1, CT_RESP_I2, CT_RESP_I3, CT_RESP_I4, CT_RESN_I1, CT_RESN_I2
+, CT_RESN_I3, CT_RESN_I4, M_EYE_I, RX_SEL_I1, RX_SEL_I2, RX_SEL_I3, RX_SEL_I4, RX_SEL_I5, RX_SEL_I6, PLL_RN_I, RST_N_I, CAL_1P_I1, CAL_1P_I2, CAL_1P_I3, CAL_1P_I4, CAL_1P_I5, CAL_1P_I6, CAL_1P_I7, CAL_1P_I8, CAL_2N_I1, CAL_2N_I2
+, CAL_2N_I3, CAL_2N_I4, CAL_2N_I5, CAL_2N_I6, CAL_2N_I7, CAL_2N_I8, CAL_3N_I1, CAL_3N_I2, CAL_3N_I3, CAL_3N_I4, CAL_3N_I5, CAL_3N_I6, CAL_3N_I7, CAL_3N_I8, CAL_4P_I1, CAL_4P_I2, CAL_4P_I3, CAL_4P_I4, CAL_4P_I5, CAL_4P_I6, CAL_4P_I7
+, CAL_4P_I8, CAL_SEL_I1, CAL_SEL_I2, CAL_SEL_I3, CAL_SEL_I4, CAL_E_I, LOCK_E_I, OVS_E_I, TST_I1, TST_I2, TST_I3, TST_I4, TST_I5, TST_I6, TST_I7, TST_I8, CLK_O, LOCK_O, CAL_O, TST_O1, TST_O2
+, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, CLK_EXT_I, LINK_TX1, LINK_TX2, LINK_TX3, LINK_TX4, LINK_TX5, LINK_RX0, LINK_RX1, LINK_RX2, LINK_RX3, LINK_RX4, LINK_RX5, LINK_TX0);
+    input CAL_1P_I1;
+    input CAL_1P_I2;
+    input CAL_1P_I3;
+    input CAL_1P_I4;
+    input CAL_1P_I5;
+    input CAL_1P_I6;
+    input CAL_1P_I7;
+    input CAL_1P_I8;
+    input CAL_2N_I1;
+    input CAL_2N_I2;
+    input CAL_2N_I3;
+    input CAL_2N_I4;
+    input CAL_2N_I5;
+    input CAL_2N_I6;
+    input CAL_2N_I7;
+    input CAL_2N_I8;
+    input CAL_3N_I1;
+    input CAL_3N_I2;
+    input CAL_3N_I3;
+    input CAL_3N_I4;
+    input CAL_3N_I5;
+    input CAL_3N_I6;
+    input CAL_3N_I7;
+    input CAL_3N_I8;
+    input CAL_4P_I1;
+    input CAL_4P_I2;
+    input CAL_4P_I3;
+    input CAL_4P_I4;
+    input CAL_4P_I5;
+    input CAL_4P_I6;
+    input CAL_4P_I7;
+    input CAL_4P_I8;
+    input CAL_E_I;
+    output CAL_O;
+    input CAL_SEL_I1;
+    input CAL_SEL_I2;
+    input CAL_SEL_I3;
+    input CAL_SEL_I4;
+    input CLK_EXT_I;
+    output CLK_O;
+    input CLK_REF_I;
+    input CLK_USER_I;
+    input CT_CAP_I1;
+    input CT_CAP_I2;
+    input CT_CAP_I3;
+    input CT_CAP_I4;
+    input CT_RESN_I1;
+    input CT_RESN_I2;
+    input CT_RESN_I3;
+    input CT_RESN_I4;
+    input CT_RESP_I1;
+    input CT_RESP_I2;
+    input CT_RESP_I3;
+    input CT_RESP_I4;
+    inout [9:0] LINK_RX0;
+    inout [9:0] LINK_RX1;
+    inout [9:0] LINK_RX2;
+    inout [9:0] LINK_RX3;
+    inout [9:0] LINK_RX4;
+    inout [9:0] LINK_RX5;
+    inout [19:0] LINK_TX0;
+    inout [19:0] LINK_TX1;
+    inout [19:0] LINK_TX2;
+    inout [19:0] LINK_TX3;
+    inout [19:0] LINK_TX4;
+    inout [19:0] LINK_TX5;
+    input LOCK_E_I;
+    output LOCK_O;
+    input MAIN_EN_I1;
+    input MAIN_EN_I2;
+    input MAIN_EN_I3;
+    input MAIN_EN_I4;
+    input MAIN_EN_I5;
+    input MAIN_EN_I6;
+    input MAIN_SG_I;
+    input MARG_ISV_I1;
+    input MARG_ISV_I2;
+    input MARG_ISV_I3;
+    input MARG_ISV_I4;
+    input MARG_ISV_I5;
+    input MARG_IS_I1;
+    input MARG_IS_I2;
+    input MARG_IS_I3;
+    input MARG_IS_I4;
+    input MARG_SV_I1;
+    input MARG_SV_I2;
+    input MARG_SV_I3;
+    input MARG_SV_I4;
+    input MARG_SV_I5;
+    input MARG_S_I1;
+    input MARG_S_I2;
+    input MARG_S_I3;
+    input MARG_S_I4;
+    input M_EYE_I;
+    input OVS_E_I;
+    input PLL_RN_I;
+    input POST_EN_I1;
+    input POST_EN_I2;
+    input POST_EN_I3;
+    input POST_EN_I4;
+    input POST_EN_I5;
+    input POST_ISV_I1;
+    input POST_ISV_I2;
+    input POST_ISV_I3;
+    input POST_ISV_I4;
+    input POST_IS_I1;
+    input POST_IS_I2;
+    input POST_IS_I3;
+    input POST_IS_I4;
+    input POST_SG_I;
+    input PRE_EN_I;
+    input PRE_IS_I1;
+    input PRE_IS_I2;
+    input PRE_IS_I3;
+    input PRE_IS_I4;
+    input PRE_SG_I;
+    input RST_N_I;
+    input RX_SEL_I1;
+    input RX_SEL_I2;
+    input RX_SEL_I3;
+    input RX_SEL_I4;
+    input RX_SEL_I5;
+    input RX_SEL_I6;
+    input TST_I1;
+    input TST_I2;
+    input TST_I3;
+    input TST_I4;
+    input TST_I5;
+    input TST_I6;
+    input TST_I7;
+    input TST_I8;
+    output TST_O1;
+    output TST_O2;
+    output TST_O3;
+    output TST_O4;
+    output TST_O5;
+    output TST_O6;
+    output TST_O7;
+    output TST_O8;
+    input TX_SEL_I1;
+    input TX_SEL_I2;
+    input TX_SEL_I3;
+    input TX_SEL_I4;
+    input TX_SEL_I5;
+    input TX_SEL_I6;
+    parameter location = "";
+    parameter main_clk_to_fabric_div_en = 1'b0;
+    parameter main_clk_to_fabric_div_mode = 1'b0;
+    parameter main_clk_to_fabric_sel = 1'b0;
+    parameter main_test = 8'b00000000;
+    parameter main_use_only_usr_clock = 1'b0;
+    parameter main_use_pcs_clk_2 = 1'b0;
+    parameter pcs_ovs_mode = 1'b0;
+    parameter pcs_pll_lock_count = 3'b000;
+    parameter pcs_word_len = 2'b00;
+    parameter pll_pma_cpump_n = 3'b000;
+    parameter pll_pma_divf = 2'b00;
+    parameter pll_pma_divf_en_n = 1'b0;
+    parameter pll_pma_divm = 2'b00;
+    parameter pll_pma_divm_en_n = 1'b0;
+    parameter pll_pma_divn = 1'b0;
+    parameter pll_pma_divn_en_n = 1'b0;
+    parameter pll_pma_int_data_len = 1'b0;
+    parameter pll_pma_lvds_mux = 1'b0;
+    parameter pll_pma_mux_ckref = 1'b0;
+    parameter rx_pma_half_step = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_PMA_U(CLK_TX_I, CLK_RX_I, CLK_REF_I, DC_E_I, DC_LCSN_I1, DC_LCSN_I2, DC_LCSN_I3, DC_LCSN_I4, DC_CCSN_I, DC_WE_N_I, DC_ADD_I1, DC_ADD_I2, DC_ADD_I3, DC_ADD_I4, DC_WDATAS_I, DC_WDATA_I1, DC_WDATA_I2, DC_WDATA_I3, DC_WDATA_I4, DC_WDATA_I5, DC_WDATA_I6
+, DC_WDATA_I7, DC_WDATA_I8, DC_WDATA_I9, DC_WDATA_I10, DC_WDATA_I11, DC_WDATA_I12, PLL_RN_I, PWDN_N_I, RST_N_I, DBG_S_I1, DBG_S_I2, DBG_A_I, SE_I, SCAN_I1, SCAN_I2, SCAN_I3, SCAN_I4, SCAN_I5, SCAN_I6, SCAN_I7, SCAN_I8
+, CLK_O, CLK_RX_O, LOCK_O, LOCKA_O, FB_LOCK_O, CAL_OUT_O, DBG_R_O, LL_O1, LL_O2, LL_O3, LL_O4, LL_O5, LL_O6, LL_O7, LL_O8, LL_O9, LL_O10, LL_O11, LL_O12, LL_O13, LL_O14
+, LL_O15, LL_O16, LL_O17, LL_O18, LL_O19, LL_O20, SCAN_O1, SCAN_O2, SCAN_O3, SCAN_O4, SCAN_O5, SCAN_O6, SCAN_O7, SCAN_O8, LINK_TX1, LINK_TX2, LINK_TX3, LINK_RX0, LINK_RX1, LINK_RX2, LINK_RX3
+, LINK_TX0);
+    output CAL_OUT_O;
+    output CLK_O;
+    input CLK_REF_I;
+    input CLK_RX_I;
+    output CLK_RX_O;
+    input CLK_TX_I;
+    input DBG_A_I;
+    output DBG_R_O;
+    input DBG_S_I1;
+    input DBG_S_I2;
+    input DC_ADD_I1;
+    input DC_ADD_I2;
+    input DC_ADD_I3;
+    input DC_ADD_I4;
+    input DC_CCSN_I;
+    input DC_E_I;
+    input DC_LCSN_I1;
+    input DC_LCSN_I2;
+    input DC_LCSN_I3;
+    input DC_LCSN_I4;
+    input DC_WDATAS_I;
+    input DC_WDATA_I1;
+    input DC_WDATA_I10;
+    input DC_WDATA_I11;
+    input DC_WDATA_I12;
+    input DC_WDATA_I2;
+    input DC_WDATA_I3;
+    input DC_WDATA_I4;
+    input DC_WDATA_I5;
+    input DC_WDATA_I6;
+    input DC_WDATA_I7;
+    input DC_WDATA_I8;
+    input DC_WDATA_I9;
+    input DC_WE_N_I;
+    output FB_LOCK_O;
+    inout [9:0] LINK_RX0;
+    inout [9:0] LINK_RX1;
+    inout [9:0] LINK_RX2;
+    inout [9:0] LINK_RX3;
+    inout [19:0] LINK_TX0;
+    inout [19:0] LINK_TX1;
+    inout [19:0] LINK_TX2;
+    inout [19:0] LINK_TX3;
+    output LL_O1;
+    output LL_O10;
+    output LL_O11;
+    output LL_O12;
+    output LL_O13;
+    output LL_O14;
+    output LL_O15;
+    output LL_O16;
+    output LL_O17;
+    output LL_O18;
+    output LL_O19;
+    output LL_O2;
+    output LL_O20;
+    output LL_O3;
+    output LL_O4;
+    output LL_O5;
+    output LL_O6;
+    output LL_O7;
+    output LL_O8;
+    output LL_O9;
+    output LOCKA_O;
+    output LOCK_O;
+    input PLL_RN_I;
+    input PWDN_N_I;
+    input RST_N_I;
+    input SCAN_I1;
+    input SCAN_I2;
+    input SCAN_I3;
+    input SCAN_I4;
+    input SCAN_I5;
+    input SCAN_I6;
+    input SCAN_I7;
+    input SCAN_I8;
+    output SCAN_O1;
+    output SCAN_O2;
+    output SCAN_O3;
+    output SCAN_O4;
+    output SCAN_O5;
+    output SCAN_O6;
+    output SCAN_O7;
+    output SCAN_O8;
+    input SE_I;
+    parameter dyn_all_rx_pma_m_eye = 1'b0;
+    parameter dyn_all_rx_pma_m_eye_coarse_ena = 1'b0;
+    parameter dyn_all_rx_pma_m_eye_dn = 1'b0;
+    parameter dyn_all_rx_pma_m_eye_fine_ena = 1'b0;
+    parameter dyn_all_rx_pma_m_eye_step = 4'b0000;
+    parameter dyn_all_rx_pma_m_eye_up = 1'b0;
+    parameter dyn_all_rx_pma_threshold_1 = 5'b00000;
+    parameter dyn_all_rx_pma_threshold_2 = 5'b00000;
+    parameter dyn_all_rx_pma_trim_locked = 3'b000;
+    parameter dyn_all_rx_pma_trim_mode = 2'b00;
+    parameter dyn_all_rx_pma_trim_unlocked = 3'b000;
+    parameter dyn_rx0_pma_ctle_cap_p = 4'b0000;
+    parameter dyn_rx0_pma_ctle_res_p = 4'b0000;
+    parameter dyn_rx0_pma_dfe_idac_tap1_n = 6'b000000;
+    parameter dyn_rx0_pma_dfe_idac_tap2_n = 6'b000000;
+    parameter dyn_rx0_pma_dfe_idac_tap3_n = 6'b000000;
+    parameter dyn_rx0_pma_dfe_idac_tap4_n = 6'b000000;
+    parameter dyn_rx0_pma_termination_cmd = 6'b000000;
+    parameter dyn_rx1_pma_ctle_cap_p = 4'b0000;
+    parameter dyn_rx1_pma_ctle_res_p = 4'b0000;
+    parameter dyn_rx1_pma_dfe_idac_tap1_n = 6'b000000;
+    parameter dyn_rx1_pma_dfe_idac_tap2_n = 6'b000000;
+    parameter dyn_rx1_pma_dfe_idac_tap3_n = 6'b000000;
+    parameter dyn_rx1_pma_dfe_idac_tap4_n = 6'b000000;
+    parameter dyn_rx1_pma_termination_cmd = 6'b000000;
+    parameter dyn_rx2_pma_ctle_cap_p = 4'b0000;
+    parameter dyn_rx2_pma_ctle_res_p = 4'b0000;
+    parameter dyn_rx2_pma_dfe_idac_tap1_n = 6'b000000;
+    parameter dyn_rx2_pma_dfe_idac_tap2_n = 6'b000000;
+    parameter dyn_rx2_pma_dfe_idac_tap3_n = 6'b000000;
+    parameter dyn_rx2_pma_dfe_idac_tap4_n = 6'b000000;
+    parameter dyn_rx2_pma_termination_cmd = 6'b000000;
+    parameter dyn_rx3_pma_ctle_cap_p = 4'b0000;
+    parameter dyn_rx3_pma_ctle_res_p = 4'b0000;
+    parameter dyn_rx3_pma_dfe_idac_tap1_n = 6'b000000;
+    parameter dyn_rx3_pma_dfe_idac_tap2_n = 6'b000000;
+    parameter dyn_rx3_pma_dfe_idac_tap3_n = 6'b000000;
+    parameter dyn_rx3_pma_dfe_idac_tap4_n = 6'b000000;
+    parameter dyn_rx3_pma_termination_cmd = 6'b000000;
+    parameter dyn_tx0_pma_main_en = 6'b000000;
+    parameter dyn_tx0_pma_main_sign = 1'b0;
+    parameter dyn_tx0_pma_margin_input = 9'b000000000;
+    parameter dyn_tx0_pma_margin_sel = 9'b000000000;
+    parameter dyn_tx0_pma_post_en = 5'b00000;
+    parameter dyn_tx0_pma_post_sel = 8'b00000000;
+    parameter dyn_tx0_pma_post_sign = 1'b0;
+    parameter dyn_tx0_pma_pre_en = 1'b0;
+    parameter dyn_tx0_pma_pre_sel = 4'b0000;
+    parameter dyn_tx0_pma_pre_sign = 1'b0;
+    parameter dyn_tx1_pma_main_en = 6'b000000;
+    parameter dyn_tx1_pma_main_sign = 1'b0;
+    parameter dyn_tx1_pma_margin_input = 9'b000000000;
+    parameter dyn_tx1_pma_margin_sel = 9'b000000000;
+    parameter dyn_tx1_pma_post_en = 5'b00000;
+    parameter dyn_tx1_pma_post_sel = 8'b00000000;
+    parameter dyn_tx1_pma_post_sign = 1'b0;
+    parameter dyn_tx1_pma_pre_en = 1'b0;
+    parameter dyn_tx1_pma_pre_sel = 4'b0000;
+    parameter dyn_tx1_pma_pre_sign = 1'b0;
+    parameter dyn_tx2_pma_main_en = 6'b000000;
+    parameter dyn_tx2_pma_main_sign = 1'b0;
+    parameter dyn_tx2_pma_margin_input = 9'b000000000;
+    parameter dyn_tx2_pma_margin_sel = 9'b000000000;
+    parameter dyn_tx2_pma_post_en = 5'b00000;
+    parameter dyn_tx2_pma_post_sel = 8'b00000000;
+    parameter dyn_tx2_pma_post_sign = 1'b0;
+    parameter dyn_tx2_pma_pre_en = 1'b0;
+    parameter dyn_tx2_pma_pre_sel = 4'b0000;
+    parameter dyn_tx2_pma_pre_sign = 1'b0;
+    parameter dyn_tx3_pma_main_en = 6'b000000;
+    parameter dyn_tx3_pma_main_sign = 1'b0;
+    parameter dyn_tx3_pma_margin_input = 9'b000000000;
+    parameter dyn_tx3_pma_margin_sel = 9'b000000000;
+    parameter dyn_tx3_pma_post_en = 5'b00000;
+    parameter dyn_tx3_pma_post_sel = 8'b00000000;
+    parameter dyn_tx3_pma_post_sign = 1'b0;
+    parameter dyn_tx3_pma_pre_en = 1'b0;
+    parameter dyn_tx3_pma_pre_sel = 4'b0000;
+    parameter dyn_tx3_pma_pre_sign = 1'b0;
+    parameter location = "";
+    parameter main_clk_to_fabric_div_en = 1'b0;
+    parameter main_clk_to_fabric_div_mode = 1'b0;
+    parameter main_clk_to_fabric_sel = 1'b0;
+    parameter main_rclk_to_fabric_sel = 2'b00;
+    parameter main_use_only_usr_clock = 1'b0;
+    parameter pcs_ovs_en = 1'b0;
+    parameter pcs_ovs_mode = 1'b0;
+    parameter pcs_pll_lock_ppm = 3'b000;
+    parameter pcs_word_len = 2'b00;
+    parameter pll_pma_ckref_ext = 1'b0;
+    parameter pll_pma_cpump = 4'b0000;
+    parameter pll_pma_divl = 2'b00;
+    parameter pll_pma_divm = 1'b0;
+    parameter pll_pma_divn = 2'b00;
+    parameter pll_pma_gbx_en = 1'b0;
+    parameter pll_pma_int_data_len = 1'b0;
+    parameter pll_pma_lvds_en = 1'b0;
+    parameter pll_pma_lvds_mux = 1'b0;
+    parameter pll_pma_mux_ckref = 1'b0;
+    parameter rx_usrclk_use_pcs_clk_2 = 1'b0;
+    parameter test_mode = 2'b00;
+    parameter tx_usrclk_use_pcs_clk_2 = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_R5_L(A_CKEM_I, A_CKEP_I, A_CKES_I, AR_A_I32, AR_A_I31, AR_A_I30, AR_A_I29, AR_A_I28, AR_A_I27, AR_A_I26, AR_A_I25, AR_A_I24, AR_A_I23, AR_A_I22, AR_A_I21, AR_A_I20, AR_A_I19, AR_A_I18, AR_A_I17, AR_A_I16, AR_A_I15
+, AR_A_I14, AR_A_I13, AR_A_I12, AR_A_I11, AR_A_I10, AR_A_I9, AR_A_I8, AR_A_I7, AR_A_I6, AR_A_I5, AR_A_I4, AR_A_I3, AR_A_I2, AR_A_I1, AR_BU_I2, AR_BU_I1, AR_CH_I4, AR_CH_I3, AR_CH_I2, AR_CH_I1, AR_IDS_I8
+, AR_IDS_I7, AR_IDS_I6, AR_IDS_I5, AR_IDS_I4, AR_IDS_I3, AR_IDS_I2, AR_IDS_I1, AR_LE_I4, AR_LE_I3, AR_LE_I2, AR_LE_I1, AR_LK_I2, AR_LK_I1, AR_PR_I3, AR_PR_I2, AR_PR_I1, AR_RYM_I, AR_RYP_I, AR_SZ_I3, AR_SZ_I2, AR_SZ_I1
+, AR_VD_I, AT_RS_I, AW_A_I32, AW_A_I31, AW_A_I30, AW_A_I29, AW_A_I28, AW_A_I27, AW_A_I26, AW_A_I25, AW_A_I24, AW_A_I23, AW_A_I22, AW_A_I21, AW_A_I20, AW_A_I19, AW_A_I18, AW_A_I17, AW_A_I16, AW_A_I15, AW_A_I14
+, AW_A_I13, AW_A_I12, AW_A_I11, AW_A_I10, AW_A_I9, AW_A_I8, AW_A_I7, AW_A_I6, AW_A_I5, AW_A_I4, AW_A_I3, AW_A_I2, AW_A_I1, AW_BU_I2, AW_BU_I1, AW_CH_I4, AW_CH_I3, AW_CH_I2, AW_CH_I1, AW_IDS_I8, AW_IDS_I7
+, AW_IDS_I6, AW_IDS_I5, AW_IDS_I4, AW_IDS_I3, AW_IDS_I2, AW_IDS_I1, AW_LE_I4, AW_LE_I3, AW_LE_I2, AW_LE_I1, AW_LK_I2, AW_LK_I1, AW_PR_I3, AW_PR_I2, AW_PR_I1, AW_RYM_I, AW_RYP_I, AW_SZ_I3, AW_SZ_I2, AW_SZ_I1, AW_VD_I
+, B_IDM_I4, B_IDM_I3, B_IDM_I2, B_IDM_I1, B_IDP_I4, B_IDP_I3, B_IDP_I2, B_IDP_I1, B_RDY_I, B_RSPM_I2, B_RSPM_I1, B_RSPP_I2, B_RSPP_I1, B_VDM_I, B_VDP_I, CDB_PW_I, CDB_RS_I, CFG_EE_I, CFG_IE_I, CFG_NM_I, CK_I
+, CS_PW_I, DB_E_I, DB_NCK_I, DB_RA_I20, DB_RA_I19, DB_RA_I18, DB_RA_I17, DB_RA_I16, DB_RA_I15, DB_RA_I14, DB_RA_I13, DB_RA_I12, DB_RA_I11, DB_RA_I10, DB_RA_I9, DB_RA_I8, DB_RA_I7, DB_RA_I6, DB_RA_I5, DB_RA_I4, DB_RA_I3
+, DB_RA_I2, DB_RA_I1, DB_RAV_I, DB_SA_I20, DB_SA_I19, DB_SA_I18, DB_SA_I17, DB_SA_I16, DB_SA_I15, DB_SA_I14, DB_SA_I13, DB_SA_I12, DB_SA_I11, DB_SA_I10, DB_SA_I9, DB_SA_I8, DB_SA_I7, DB_SA_I6, DB_SA_I5, DB_SA_I4, DB_SA_I3
+, DB_SA_I2, DB_SA_I1, DB_SAV_I, DEV_E_I, DFTS_I8, DFTS_I7, DFTS_I6, DFTS_I5, DFTS_I4, DFTS_I3, DFTS_I2, DFTS_I1, E_DB_I, ERR_R_I, EVENT_I, GID_I4, GID_I3, GID_I2, GID_I1, INIT_P_I, INIT_R_I
+, LOC_R_I, NCPUH_I, NET_RS_I, N_FIQ_I, N_IDE_I, N_IRQ_I, N_PRS_I, N_RS_I, N_SPRS_I, N_TRS_I, P_A_I29, P_A_I28, P_A_I27, P_A_I26, P_A_I25, P_A_I24, P_A_I23, P_A_I22, P_A_I21, P_A_I20, P_A_I19
+, P_A_I18, P_A_I17, P_A_I16, P_A_I15, P_A_I14, P_A_I13, P_A_I12, P_A_I11, P_A_I10, P_A_I9, P_A_I8, P_A_I7, P_A_I6, P_A_I5, P_A_I4, P_A_I3, P_A_I2, P_A_I1, P_ECC_I, PLVL_I, P_CK_E_I
+, P_CK_I, P_E_I, PPV_BS_I20, PPV_BS_I19, PPV_BS_I18, PPV_BS_I17, PPV_BS_I16, PPV_BS_I15, PPV_BS_I14, PPV_BS_I13, PPV_BS_I12, PPV_BS_I11, PPV_BS_I10, PPV_BS_I9, PPV_BS_I8, PPV_BS_I7, PPV_BS_I6, PPV_BS_I5, PPV_BS_I4, PPV_BS_I3, PPV_BS_I2
+, PPV_BS_I1, PPV_SZ_I5, PPV_SZ_I4, PPV_SZ_I3, PPV_SZ_I2, PPV_SZ_I1, PPX_BS_I20, PPX_BS_I19, PPX_BS_I18, PPX_BS_I17, PPX_BS_I16, PPX_BS_I15, PPX_BS_I14, PPX_BS_I13, PPX_BS_I12, PPX_BS_I11, PPX_BS_I10, PPX_BS_I9, PPX_BS_I8, PPX_BS_I7, PPX_BS_I6
+, PPX_BS_I5, PPX_BS_I4, PPX_BS_I3, PPX_BS_I2, PPX_BS_I1, PPX_SZ_I5, PPX_SZ_I4, PPX_SZ_I3, PPX_SZ_I2, PPX_SZ_I1, P_RS_I, P_SEL_I, PW_D_I32, PW_D_I31, PW_D_I30, PW_D_I29, PW_D_I28, PW_D_I27, PW_D_I26, PW_D_I25, PW_D_I24
+, PW_D_I23, PW_D_I22, PW_D_I21, PW_D_I20, PW_D_I19, PW_D_I18, PW_D_I17, PW_D_I16, PW_D_I15, PW_D_I14, PW_D_I13, PW_D_I12, PW_D_I11, PW_D_I10, PW_D_I9, PW_D_I8, PW_D_I7, PW_D_I6, PW_D_I5, PW_D_I4, PW_D_I3
+, PW_D_I2, PW_D_I1, PW_I, RAMCTL_I8, RAMCTL_I7, RAMCTL_I6, RAMCTL_I5, RAMCTL_I4, RAMCTL_I3, RAMCTL_I2, RAMCTL_I1, R_DM_I64, R_DM_I63, R_DM_I62, R_DM_I61, R_DM_I60, R_DM_I59, R_DM_I58, R_DM_I57, R_DM_I56, R_DM_I55
+, R_DM_I54, R_DM_I53, R_DM_I52, R_DM_I51, R_DM_I50, R_DM_I49, R_DM_I48, R_DM_I47, R_DM_I46, R_DM_I45, R_DM_I44, R_DM_I43, R_DM_I42, R_DM_I41, R_DM_I40, R_DM_I39, R_DM_I38, R_DM_I37, R_DM_I36, R_DM_I35, R_DM_I34
+, R_DM_I33, R_DM_I32, R_DM_I31, R_DM_I30, R_DM_I29, R_DM_I28, R_DM_I27, R_DM_I26, R_DM_I25, R_DM_I24, R_DM_I23, R_DM_I22, R_DM_I21, R_DM_I20, R_DM_I19, R_DM_I18, R_DM_I17, R_DM_I16, R_DM_I15, R_DM_I14, R_DM_I13
+, R_DM_I12, R_DM_I11, R_DM_I10, R_DM_I9, R_DM_I8, R_DM_I7, R_DM_I6, R_DM_I5, R_DM_I4, R_DM_I3, R_DM_I2, R_DM_I1, R_DP_I32, R_DP_I31, R_DP_I30, R_DP_I29, R_DP_I28, R_DP_I27, R_DP_I26, R_DP_I25, R_DP_I24
+, R_DP_I23, R_DP_I22, R_DP_I21, R_DP_I20, R_DP_I19, R_DP_I18, R_DP_I17, R_DP_I16, R_DP_I15, R_DP_I14, R_DP_I13, R_DP_I12, R_DP_I11, R_DP_I10, R_DP_I9, R_DP_I8, R_DP_I7, R_DP_I6, R_DP_I5, R_DP_I4, R_DP_I3
+, R_DP_I2, R_DP_I1, R_IDM_I4, R_IDM_I3, R_IDM_I2, R_IDM_I1, R_IDP_I4, R_IDP_I3, R_IDP_I2, R_IDP_I1, R_LSTM_I, R_LSTP_I, R_RDY_I, R_RSPM_I2, R_RSPM_I1, R_RSPP_I2, R_RSPP_I1, RS_BYP_I, R_VDM_I, R_VDP_I, SE_I
+, SW_CK_I, SW_DI_I, T_DI_I, TE_INI_I, VINI_I, W_D_I64, W_D_I63, W_D_I62, W_D_I61, W_D_I60, W_D_I59, W_D_I58, W_D_I57, W_D_I56, W_D_I55, W_D_I54, W_D_I53, W_D_I52, W_D_I51, W_D_I50, W_D_I49
+, W_D_I48, W_D_I47, W_D_I46, W_D_I45, W_D_I44, W_D_I43, W_D_I42, W_D_I41, W_D_I40, W_D_I39, W_D_I38, W_D_I37, W_D_I36, W_D_I35, W_D_I34, W_D_I33, W_D_I32, W_D_I31, W_D_I30, W_D_I29, W_D_I28
+, W_D_I27, W_D_I26, W_D_I25, W_D_I24, W_D_I23, W_D_I22, W_D_I21, W_D_I20, W_D_I19, W_D_I18, W_D_I17, W_D_I16, W_D_I15, W_D_I14, W_D_I13, W_D_I12, W_D_I11, W_D_I10, W_D_I9, W_D_I8, W_D_I7
+, W_D_I6, W_D_I5, W_D_I4, W_D_I3, W_D_I2, W_D_I1, W_IDS_I8, W_IDS_I7, W_IDS_I6, W_IDS_I5, W_IDS_I4, W_IDS_I3, W_IDS_I2, W_IDS_I1, W_LST_I, W_RYM_I, W_RYP_I, W_SBS_I8, W_SBS_I7, W_SBS_I6, W_SBS_I5
+, W_SBS_I4, W_SBS_I3, W_SBS_I2, W_SBS_I1, W_VD_I, AR_AM_O32, AR_AM_O31, AR_AM_O30, AR_AM_O29, AR_AM_O28, AR_AM_O27, AR_AM_O26, AR_AM_O25, AR_AM_O24, AR_AM_O23, AR_AM_O22, AR_AM_O21, AR_AM_O20, AR_AM_O19, AR_AM_O18, AR_AM_O17
+, AR_AM_O16, AR_AM_O15, AR_AM_O14, AR_AM_O13, AR_AM_O12, AR_AM_O11, AR_AM_O10, AR_AM_O9, AR_AM_O8, AR_AM_O7, AR_AM_O6, AR_AM_O5, AR_AM_O4, AR_AM_O3, AR_AM_O2, AR_AM_O1, AR_AP_O32, AR_AP_O31, AR_AP_O30, AR_AP_O29, AR_AP_O28
+, AR_AP_O27, AR_AP_O26, AR_AP_O25, AR_AP_O24, AR_AP_O23, AR_AP_O22, AR_AP_O21, AR_AP_O20, AR_AP_O19, AR_AP_O18, AR_AP_O17, AR_AP_O16, AR_AP_O15, AR_AP_O14, AR_AP_O13, AR_AP_O12, AR_AP_O11, AR_AP_O10, AR_AP_O9, AR_AP_O8, AR_AP_O7
+, AR_AP_O6, AR_AP_O5, AR_AP_O4, AR_AP_O3, AR_AP_O2, AR_AP_O1, AR_BUM_O2, AR_BUM_O1, AR_BUP_O2, AR_BUP_O1, AR_CHM_O4, AR_CHM_O3, AR_CHM_O2, AR_CHM_O1, AR_CHP_O4, AR_CHP_O3, AR_CHP_O2, AR_CHP_O1, AR_IDM_O4, AR_IDM_O3, AR_IDM_O2
+, AR_IDM_O1, AR_IDP_O4, AR_IDP_O3, AR_IDP_O2, AR_IDP_O1, AR_INM_O4, AR_INM_O3, AR_INM_O2, AR_INM_O1, AR_LEM_O4, AR_LEM_O3, AR_LEM_O2, AR_LEM_O1, AR_LEP_O4, AR_LEP_O3, AR_LEP_O2, AR_LEP_O1, AR_LKM_O2, AR_LKM_O1, AR_LKP_O2, AR_LKP_O1
+, AR_PRM_O3, AR_PRM_O2, AR_PRM_O1, AR_PRP_O3, AR_PRP_O2, AR_PRP_O1, AR_RDY_O, AR_SHM_O, AR_SZM_O3, AR_SZM_O2, AR_SZM_O1, AR_SZP_O3, AR_SZP_O2, AR_SZP_O1, AR_VDM_O, AR_VDP_O, AW_AM_O32, AW_AM_O31, AW_AM_O30, AW_AM_O29, AW_AM_O28
+, AW_AM_O27, AW_AM_O26, AW_AM_O25, AW_AM_O24, AW_AM_O23, AW_AM_O22, AW_AM_O21, AW_AM_O20, AW_AM_O19, AW_AM_O18, AW_AM_O17, AW_AM_O16, AW_AM_O15, AW_AM_O14, AW_AM_O13, AW_AM_O12, AW_AM_O11, AW_AM_O10, AW_AM_O9, AW_AM_O8, AW_AM_O7
+, AW_AM_O6, AW_AM_O5, AW_AM_O4, AW_AM_O3, AW_AM_O2, AW_AM_O1, AW_AP_O32, AW_AP_O31, AW_AP_O30, AW_AP_O29, AW_AP_O28, AW_AP_O27, AW_AP_O26, AW_AP_O25, AW_AP_O24, AW_AP_O23, AW_AP_O22, AW_AP_O21, AW_AP_O20, AW_AP_O19, AW_AP_O18
+, AW_AP_O17, AW_AP_O16, AW_AP_O15, AW_AP_O14, AW_AP_O13, AW_AP_O12, AW_AP_O11, AW_AP_O10, AW_AP_O9, AW_AP_O8, AW_AP_O7, AW_AP_O6, AW_AP_O5, AW_AP_O4, AW_AP_O3, AW_AP_O2, AW_AP_O1, AW_BUM_O2, AW_BUM_O1, AW_BUP_O2, AW_BUP_O1
+, AW_CHM_O4, AW_CHM_O3, AW_CHM_O2, AW_CHM_O1, AW_CHP_O4, AW_CHP_O3, AW_CHP_O2, AW_CHP_O1, AW_IDM_O4, AW_IDM_O3, AW_IDM_O2, AW_IDM_O1, AW_IDP_O4, AW_IDP_O3, AW_IDP_O2, AW_IDP_O1, AW_INM_O4, AW_INM_O3, AW_INM_O2, AW_INM_O1, AW_LEM_O4
+, AW_LEM_O3, AW_LEM_O2, AW_LEM_O1, AW_LEP_O4, AW_LEP_O3, AW_LEP_O2, AW_LEP_O1, AW_LKM_O2, AW_LKM_O1, AW_LKP_O2, AW_LKP_O1, AW_PRM_O3, AW_PRM_O2, AW_PRM_O1, AW_PRP_O3, AW_PRP_O2, AW_PRP_O1, AW_RDY_O, AW_SHM_O, AW_SZM_O3, AW_SZM_O2
+, AW_SZM_O1, AW_SZP_O3, AW_SZP_O2, AW_SZP_O1, AW_VDM_O, AW_VDP_O, B_IDS_O8, B_IDS_O7, B_IDS_O6, B_IDS_O5, B_IDS_O4, B_IDS_O3, B_IDS_O2, B_IDS_O1, B_RDYM_O, B_RDYP_O, B_RSP_O2, B_RSP_O1, B_VD_O, CDB_PW_O, CDB_RS_O
+, COM_RX_O, COM_TX_O, CS_PW_O, DB_ACK_O, DB_NPD_O, DB_RS_O, DFTS_O8, DFTS_O7, DFTS_O6, DFTS_O5, DFTS_O4, DFTS_O3, DFTS_O2, DFTS_O1, ET_ASC_O8, ET_ASC_O7, ET_ASC_O6, ET_ASC_O5, ET_ASC_O4, ET_ASC_O3, ET_ASC_O2
+, ET_ASC_O1, ET_E_O, ET_EXT_O2, ET_EXT_O1, EVENT_O, FP_DZC_O, FP_IDC_O, FP_IOC_O, FP_IXC_O, FP_OFC_O, FP_UFC_O, JTAG_O, N_CKST_O, N_PMU_O, N_TDO_O, N_VFIQ_O, N_VIRQ_O, N_VRST_O, N_EPST_O, N_IPST_O, P_RD_O32
+, P_RD_O31, P_RD_O30, P_RD_O29, P_RD_O28, P_RD_O27, P_RD_O26, P_RD_O25, P_RD_O24, P_RD_O23, P_RD_O22, P_RD_O21, P_RD_O20, P_RD_O19, P_RD_O18, P_RD_O17, P_RD_O16, P_RD_O15, P_RD_O14, P_RD_O13, P_RD_O12, P_RD_O11
+, P_RD_O10, P_RD_O9, P_RD_O8, P_RD_O7, P_RD_O6, P_RD_O5, P_RD_O4, P_RD_O3, P_RD_O2, P_RD_O1, P_RDY_O, P_VER_O, RD_O64, RD_O63, RD_O62, RD_O61, RD_O60, RD_O59, RD_O58, RD_O57, RD_O56
+, RD_O55, RD_O54, RD_O53, RD_O52, RD_O51, RD_O50, RD_O49, RD_O48, RD_O47, RD_O46, RD_O45, RD_O44, RD_O43, RD_O42, RD_O41, RD_O40, RD_O39, RD_O38, RD_O37, RD_O36, RD_O35
+, RD_O34, RD_O33, RD_O32, RD_O31, RD_O30, RD_O29, RD_O28, RD_O27, RD_O26, RD_O25, RD_O24, RD_O23, RD_O22, RD_O21, RD_O20, RD_O19, RD_O18, RD_O17, RD_O16, RD_O15, RD_O14
+, RD_O13, RD_O12, RD_O11, RD_O10, RD_O9, RD_O8, RD_O7, RD_O6, RD_O5, RD_O4, RD_O3, RD_O2, RD_O1, R_IDS_O8, R_IDS_O7, R_IDS_O6, R_IDS_O5, R_IDS_O4, R_IDS_O3, R_IDS_O2, R_IDS_O1
+, R_LST_O, R_RDYM_O, R_RDYP_O, R_RSP_O2, R_RSP_O1, R_VD_O, SWDO_O, SWDO_E_O, TDO_O, T_CK_O, T_CTL_O, T_DATA_O32, T_DATA_O31, T_DATA_O30, T_DATA_O29, T_DATA_O28, T_DATA_O27, T_DATA_O26, T_DATA_O25, T_DATA_O24, T_DATA_O23
+, T_DATA_O22, T_DATA_O21, T_DATA_O20, T_DATA_O19, T_DATA_O18, T_DATA_O17, T_DATA_O16, T_DATA_O15, T_DATA_O14, T_DATA_O13, T_DATA_O12, T_DATA_O11, T_DATA_O10, T_DATA_O9, T_DATA_O8, T_DATA_O7, T_DATA_O6, T_DATA_O5, T_DATA_O4, T_DATA_O3, T_DATA_O2
+, T_DATA_O1, W_DM_O64, W_DM_O63, W_DM_O62, W_DM_O61, W_DM_O60, W_DM_O59, W_DM_O58, W_DM_O57, W_DM_O56, W_DM_O55, W_DM_O54, W_DM_O53, W_DM_O52, W_DM_O51, W_DM_O50, W_DM_O49, W_DM_O48, W_DM_O47, W_DM_O46, W_DM_O45
+, W_DM_O44, W_DM_O43, W_DM_O42, W_DM_O41, W_DM_O40, W_DM_O39, W_DM_O38, W_DM_O37, W_DM_O36, W_DM_O35, W_DM_O34, W_DM_O33, W_DM_O32, W_DM_O31, W_DM_O30, W_DM_O29, W_DM_O28, W_DM_O27, W_DM_O26, W_DM_O25, W_DM_O24
+, W_DM_O23, W_DM_O22, W_DM_O21, W_DM_O20, W_DM_O19, W_DM_O18, W_DM_O17, W_DM_O16, W_DM_O15, W_DM_O14, W_DM_O13, W_DM_O12, W_DM_O11, W_DM_O10, W_DM_O9, W_DM_O8, W_DM_O7, W_DM_O6, W_DM_O5, W_DM_O4, W_DM_O3
+, W_DM_O2, W_DM_O1, W_DP_O32, W_DP_O31, W_DP_O30, W_DP_O29, W_DP_O28, W_DP_O27, W_DP_O26, W_DP_O25, W_DP_O24, W_DP_O23, W_DP_O22, W_DP_O21, W_DP_O20, W_DP_O19, W_DP_O18, W_DP_O17, W_DP_O16, W_DP_O15, W_DP_O14
+, W_DP_O13, W_DP_O12, W_DP_O11, W_DP_O10, W_DP_O9, W_DP_O8, W_DP_O7, W_DP_O6, W_DP_O5, W_DP_O4, W_DP_O3, W_DP_O2, W_DP_O1, W_IDM_O4, W_IDM_O3, W_IDM_O2, W_IDM_O1, W_IDP_O4, W_IDP_O3, W_IDP_O2, W_IDP_O1
+, W_LSTM_O, W_LSTP_O, W_RDY_O, W_SBM_O8, W_SBM_O7, W_SBM_O6, W_SBM_O5, W_SBM_O4, W_SBM_O3, W_SBM_O2, W_SBM_O1, W_SBP_O4, W_SBP_O3, W_SBP_O2, W_SBP_O1, W_VDM_O, W_VDP_O);
+    output AR_AM_O1;
+    output AR_AM_O10;
+    output AR_AM_O11;
+    output AR_AM_O12;
+    output AR_AM_O13;
+    output AR_AM_O14;
+    output AR_AM_O15;
+    output AR_AM_O16;
+    output AR_AM_O17;
+    output AR_AM_O18;
+    output AR_AM_O19;
+    output AR_AM_O2;
+    output AR_AM_O20;
+    output AR_AM_O21;
+    output AR_AM_O22;
+    output AR_AM_O23;
+    output AR_AM_O24;
+    output AR_AM_O25;
+    output AR_AM_O26;
+    output AR_AM_O27;
+    output AR_AM_O28;
+    output AR_AM_O29;
+    output AR_AM_O3;
+    output AR_AM_O30;
+    output AR_AM_O31;
+    output AR_AM_O32;
+    output AR_AM_O4;
+    output AR_AM_O5;
+    output AR_AM_O6;
+    output AR_AM_O7;
+    output AR_AM_O8;
+    output AR_AM_O9;
+    output AR_AP_O1;
+    output AR_AP_O10;
+    output AR_AP_O11;
+    output AR_AP_O12;
+    output AR_AP_O13;
+    output AR_AP_O14;
+    output AR_AP_O15;
+    output AR_AP_O16;
+    output AR_AP_O17;
+    output AR_AP_O18;
+    output AR_AP_O19;
+    output AR_AP_O2;
+    output AR_AP_O20;
+    output AR_AP_O21;
+    output AR_AP_O22;
+    output AR_AP_O23;
+    output AR_AP_O24;
+    output AR_AP_O25;
+    output AR_AP_O26;
+    output AR_AP_O27;
+    output AR_AP_O28;
+    output AR_AP_O29;
+    output AR_AP_O3;
+    output AR_AP_O30;
+    output AR_AP_O31;
+    output AR_AP_O32;
+    output AR_AP_O4;
+    output AR_AP_O5;
+    output AR_AP_O6;
+    output AR_AP_O7;
+    output AR_AP_O8;
+    output AR_AP_O9;
+    input AR_A_I1;
+    input AR_A_I10;
+    input AR_A_I11;
+    input AR_A_I12;
+    input AR_A_I13;
+    input AR_A_I14;
+    input AR_A_I15;
+    input AR_A_I16;
+    input AR_A_I17;
+    input AR_A_I18;
+    input AR_A_I19;
+    input AR_A_I2;
+    input AR_A_I20;
+    input AR_A_I21;
+    input AR_A_I22;
+    input AR_A_I23;
+    input AR_A_I24;
+    input AR_A_I25;
+    input AR_A_I26;
+    input AR_A_I27;
+    input AR_A_I28;
+    input AR_A_I29;
+    input AR_A_I3;
+    input AR_A_I30;
+    input AR_A_I31;
+    input AR_A_I32;
+    input AR_A_I4;
+    input AR_A_I5;
+    input AR_A_I6;
+    input AR_A_I7;
+    input AR_A_I8;
+    input AR_A_I9;
+    output AR_BUM_O1;
+    output AR_BUM_O2;
+    output AR_BUP_O1;
+    output AR_BUP_O2;
+    input AR_BU_I1;
+    input AR_BU_I2;
+    output AR_CHM_O1;
+    output AR_CHM_O2;
+    output AR_CHM_O3;
+    output AR_CHM_O4;
+    output AR_CHP_O1;
+    output AR_CHP_O2;
+    output AR_CHP_O3;
+    output AR_CHP_O4;
+    input AR_CH_I1;
+    input AR_CH_I2;
+    input AR_CH_I3;
+    input AR_CH_I4;
+    output AR_IDM_O1;
+    output AR_IDM_O2;
+    output AR_IDM_O3;
+    output AR_IDM_O4;
+    output AR_IDP_O1;
+    output AR_IDP_O2;
+    output AR_IDP_O3;
+    output AR_IDP_O4;
+    input AR_IDS_I1;
+    input AR_IDS_I2;
+    input AR_IDS_I3;
+    input AR_IDS_I4;
+    input AR_IDS_I5;
+    input AR_IDS_I6;
+    input AR_IDS_I7;
+    input AR_IDS_I8;
+    output AR_INM_O1;
+    output AR_INM_O2;
+    output AR_INM_O3;
+    output AR_INM_O4;
+    output AR_LEM_O1;
+    output AR_LEM_O2;
+    output AR_LEM_O3;
+    output AR_LEM_O4;
+    output AR_LEP_O1;
+    output AR_LEP_O2;
+    output AR_LEP_O3;
+    output AR_LEP_O4;
+    input AR_LE_I1;
+    input AR_LE_I2;
+    input AR_LE_I3;
+    input AR_LE_I4;
+    output AR_LKM_O1;
+    output AR_LKM_O2;
+    output AR_LKP_O1;
+    output AR_LKP_O2;
+    input AR_LK_I1;
+    input AR_LK_I2;
+    output AR_PRM_O1;
+    output AR_PRM_O2;
+    output AR_PRM_O3;
+    output AR_PRP_O1;
+    output AR_PRP_O2;
+    output AR_PRP_O3;
+    input AR_PR_I1;
+    input AR_PR_I2;
+    input AR_PR_I3;
+    output AR_RDY_O;
+    input AR_RYM_I;
+    input AR_RYP_I;
+    output AR_SHM_O;
+    output AR_SZM_O1;
+    output AR_SZM_O2;
+    output AR_SZM_O3;
+    output AR_SZP_O1;
+    output AR_SZP_O2;
+    output AR_SZP_O3;
+    input AR_SZ_I1;
+    input AR_SZ_I2;
+    input AR_SZ_I3;
+    output AR_VDM_O;
+    output AR_VDP_O;
+    input AR_VD_I;
+    input AT_RS_I;
+    output AW_AM_O1;
+    output AW_AM_O10;
+    output AW_AM_O11;
+    output AW_AM_O12;
+    output AW_AM_O13;
+    output AW_AM_O14;
+    output AW_AM_O15;
+    output AW_AM_O16;
+    output AW_AM_O17;
+    output AW_AM_O18;
+    output AW_AM_O19;
+    output AW_AM_O2;
+    output AW_AM_O20;
+    output AW_AM_O21;
+    output AW_AM_O22;
+    output AW_AM_O23;
+    output AW_AM_O24;
+    output AW_AM_O25;
+    output AW_AM_O26;
+    output AW_AM_O27;
+    output AW_AM_O28;
+    output AW_AM_O29;
+    output AW_AM_O3;
+    output AW_AM_O30;
+    output AW_AM_O31;
+    output AW_AM_O32;
+    output AW_AM_O4;
+    output AW_AM_O5;
+    output AW_AM_O6;
+    output AW_AM_O7;
+    output AW_AM_O8;
+    output AW_AM_O9;
+    output AW_AP_O1;
+    output AW_AP_O10;
+    output AW_AP_O11;
+    output AW_AP_O12;
+    output AW_AP_O13;
+    output AW_AP_O14;
+    output AW_AP_O15;
+    output AW_AP_O16;
+    output AW_AP_O17;
+    output AW_AP_O18;
+    output AW_AP_O19;
+    output AW_AP_O2;
+    output AW_AP_O20;
+    output AW_AP_O21;
+    output AW_AP_O22;
+    output AW_AP_O23;
+    output AW_AP_O24;
+    output AW_AP_O25;
+    output AW_AP_O26;
+    output AW_AP_O27;
+    output AW_AP_O28;
+    output AW_AP_O29;
+    output AW_AP_O3;
+    output AW_AP_O30;
+    output AW_AP_O31;
+    output AW_AP_O32;
+    output AW_AP_O4;
+    output AW_AP_O5;
+    output AW_AP_O6;
+    output AW_AP_O7;
+    output AW_AP_O8;
+    output AW_AP_O9;
+    input AW_A_I1;
+    input AW_A_I10;
+    input AW_A_I11;
+    input AW_A_I12;
+    input AW_A_I13;
+    input AW_A_I14;
+    input AW_A_I15;
+    input AW_A_I16;
+    input AW_A_I17;
+    input AW_A_I18;
+    input AW_A_I19;
+    input AW_A_I2;
+    input AW_A_I20;
+    input AW_A_I21;
+    input AW_A_I22;
+    input AW_A_I23;
+    input AW_A_I24;
+    input AW_A_I25;
+    input AW_A_I26;
+    input AW_A_I27;
+    input AW_A_I28;
+    input AW_A_I29;
+    input AW_A_I3;
+    input AW_A_I30;
+    input AW_A_I31;
+    input AW_A_I32;
+    input AW_A_I4;
+    input AW_A_I5;
+    input AW_A_I6;
+    input AW_A_I7;
+    input AW_A_I8;
+    input AW_A_I9;
+    output AW_BUM_O1;
+    output AW_BUM_O2;
+    output AW_BUP_O1;
+    output AW_BUP_O2;
+    input AW_BU_I1;
+    input AW_BU_I2;
+    output AW_CHM_O1;
+    output AW_CHM_O2;
+    output AW_CHM_O3;
+    output AW_CHM_O4;
+    output AW_CHP_O1;
+    output AW_CHP_O2;
+    output AW_CHP_O3;
+    output AW_CHP_O4;
+    input AW_CH_I1;
+    input AW_CH_I2;
+    input AW_CH_I3;
+    input AW_CH_I4;
+    output AW_IDM_O1;
+    output AW_IDM_O2;
+    output AW_IDM_O3;
+    output AW_IDM_O4;
+    output AW_IDP_O1;
+    output AW_IDP_O2;
+    output AW_IDP_O3;
+    output AW_IDP_O4;
+    input AW_IDS_I1;
+    input AW_IDS_I2;
+    input AW_IDS_I3;
+    input AW_IDS_I4;
+    input AW_IDS_I5;
+    input AW_IDS_I6;
+    input AW_IDS_I7;
+    input AW_IDS_I8;
+    output AW_INM_O1;
+    output AW_INM_O2;
+    output AW_INM_O3;
+    output AW_INM_O4;
+    output AW_LEM_O1;
+    output AW_LEM_O2;
+    output AW_LEM_O3;
+    output AW_LEM_O4;
+    output AW_LEP_O1;
+    output AW_LEP_O2;
+    output AW_LEP_O3;
+    output AW_LEP_O4;
+    input AW_LE_I1;
+    input AW_LE_I2;
+    input AW_LE_I3;
+    input AW_LE_I4;
+    output AW_LKM_O1;
+    output AW_LKM_O2;
+    output AW_LKP_O1;
+    output AW_LKP_O2;
+    input AW_LK_I1;
+    input AW_LK_I2;
+    output AW_PRM_O1;
+    output AW_PRM_O2;
+    output AW_PRM_O3;
+    output AW_PRP_O1;
+    output AW_PRP_O2;
+    output AW_PRP_O3;
+    input AW_PR_I1;
+    input AW_PR_I2;
+    input AW_PR_I3;
+    output AW_RDY_O;
+    input AW_RYM_I;
+    input AW_RYP_I;
+    output AW_SHM_O;
+    output AW_SZM_O1;
+    output AW_SZM_O2;
+    output AW_SZM_O3;
+    output AW_SZP_O1;
+    output AW_SZP_O2;
+    output AW_SZP_O3;
+    input AW_SZ_I1;
+    input AW_SZ_I2;
+    input AW_SZ_I3;
+    output AW_VDM_O;
+    output AW_VDP_O;
+    input AW_VD_I;
+    input A_CKEM_I;
+    input A_CKEP_I;
+    input A_CKES_I;
+    input B_IDM_I1;
+    input B_IDM_I2;
+    input B_IDM_I3;
+    input B_IDM_I4;
+    input B_IDP_I1;
+    input B_IDP_I2;
+    input B_IDP_I3;
+    input B_IDP_I4;
+    output B_IDS_O1;
+    output B_IDS_O2;
+    output B_IDS_O3;
+    output B_IDS_O4;
+    output B_IDS_O5;
+    output B_IDS_O6;
+    output B_IDS_O7;
+    output B_IDS_O8;
+    output B_RDYM_O;
+    output B_RDYP_O;
+    input B_RDY_I;
+    input B_RSPM_I1;
+    input B_RSPM_I2;
+    input B_RSPP_I1;
+    input B_RSPP_I2;
+    output B_RSP_O1;
+    output B_RSP_O2;
+    input B_VDM_I;
+    input B_VDP_I;
+    output B_VD_O;
+    input CDB_PW_I;
+    output CDB_PW_O;
+    input CDB_RS_I;
+    output CDB_RS_O;
+    input CFG_EE_I;
+    input CFG_IE_I;
+    input CFG_NM_I;
+    input CK_I;
+    output COM_RX_O;
+    output COM_TX_O;
+    input CS_PW_I;
+    output CS_PW_O;
+    output DB_ACK_O;
+    input DB_E_I;
+    input DB_NCK_I;
+    output DB_NPD_O;
+    input DB_RAV_I;
+    input DB_RA_I1;
+    input DB_RA_I10;
+    input DB_RA_I11;
+    input DB_RA_I12;
+    input DB_RA_I13;
+    input DB_RA_I14;
+    input DB_RA_I15;
+    input DB_RA_I16;
+    input DB_RA_I17;
+    input DB_RA_I18;
+    input DB_RA_I19;
+    input DB_RA_I2;
+    input DB_RA_I20;
+    input DB_RA_I3;
+    input DB_RA_I4;
+    input DB_RA_I5;
+    input DB_RA_I6;
+    input DB_RA_I7;
+    input DB_RA_I8;
+    input DB_RA_I9;
+    output DB_RS_O;
+    input DB_SAV_I;
+    input DB_SA_I1;
+    input DB_SA_I10;
+    input DB_SA_I11;
+    input DB_SA_I12;
+    input DB_SA_I13;
+    input DB_SA_I14;
+    input DB_SA_I15;
+    input DB_SA_I16;
+    input DB_SA_I17;
+    input DB_SA_I18;
+    input DB_SA_I19;
+    input DB_SA_I2;
+    input DB_SA_I20;
+    input DB_SA_I3;
+    input DB_SA_I4;
+    input DB_SA_I5;
+    input DB_SA_I6;
+    input DB_SA_I7;
+    input DB_SA_I8;
+    input DB_SA_I9;
+    input DEV_E_I;
+    input DFTS_I1;
+    input DFTS_I2;
+    input DFTS_I3;
+    input DFTS_I4;
+    input DFTS_I5;
+    input DFTS_I6;
+    input DFTS_I7;
+    input DFTS_I8;
+    output DFTS_O1;
+    output DFTS_O2;
+    output DFTS_O3;
+    output DFTS_O4;
+    output DFTS_O5;
+    output DFTS_O6;
+    output DFTS_O7;
+    output DFTS_O8;
+    input ERR_R_I;
+    output ET_ASC_O1;
+    output ET_ASC_O2;
+    output ET_ASC_O3;
+    output ET_ASC_O4;
+    output ET_ASC_O5;
+    output ET_ASC_O6;
+    output ET_ASC_O7;
+    output ET_ASC_O8;
+    output ET_EXT_O1;
+    output ET_EXT_O2;
+    output ET_E_O;
+    input EVENT_I;
+    output EVENT_O;
+    input E_DB_I;
+    output FP_DZC_O;
+    output FP_IDC_O;
+    output FP_IOC_O;
+    output FP_IXC_O;
+    output FP_OFC_O;
+    output FP_UFC_O;
+    input GID_I1;
+    input GID_I2;
+    input GID_I3;
+    input GID_I4;
+    input INIT_P_I;
+    input INIT_R_I;
+    output JTAG_O;
+    input LOC_R_I;
+    input NCPUH_I;
+    input NET_RS_I;
+    output N_CKST_O;
+    output N_EPST_O;
+    input N_FIQ_I;
+    input N_IDE_I;
+    output N_IPST_O;
+    input N_IRQ_I;
+    output N_PMU_O;
+    input N_PRS_I;
+    input N_RS_I;
+    input N_SPRS_I;
+    output N_TDO_O;
+    input N_TRS_I;
+    output N_VFIQ_O;
+    output N_VIRQ_O;
+    output N_VRST_O;
+    input PLVL_I;
+    input PPV_BS_I1;
+    input PPV_BS_I10;
+    input PPV_BS_I11;
+    input PPV_BS_I12;
+    input PPV_BS_I13;
+    input PPV_BS_I14;
+    input PPV_BS_I15;
+    input PPV_BS_I16;
+    input PPV_BS_I17;
+    input PPV_BS_I18;
+    input PPV_BS_I19;
+    input PPV_BS_I2;
+    input PPV_BS_I20;
+    input PPV_BS_I3;
+    input PPV_BS_I4;
+    input PPV_BS_I5;
+    input PPV_BS_I6;
+    input PPV_BS_I7;
+    input PPV_BS_I8;
+    input PPV_BS_I9;
+    input PPV_SZ_I1;
+    input PPV_SZ_I2;
+    input PPV_SZ_I3;
+    input PPV_SZ_I4;
+    input PPV_SZ_I5;
+    input PPX_BS_I1;
+    input PPX_BS_I10;
+    input PPX_BS_I11;
+    input PPX_BS_I12;
+    input PPX_BS_I13;
+    input PPX_BS_I14;
+    input PPX_BS_I15;
+    input PPX_BS_I16;
+    input PPX_BS_I17;
+    input PPX_BS_I18;
+    input PPX_BS_I19;
+    input PPX_BS_I2;
+    input PPX_BS_I20;
+    input PPX_BS_I3;
+    input PPX_BS_I4;
+    input PPX_BS_I5;
+    input PPX_BS_I6;
+    input PPX_BS_I7;
+    input PPX_BS_I8;
+    input PPX_BS_I9;
+    input PPX_SZ_I1;
+    input PPX_SZ_I2;
+    input PPX_SZ_I3;
+    input PPX_SZ_I4;
+    input PPX_SZ_I5;
+    input PW_D_I1;
+    input PW_D_I10;
+    input PW_D_I11;
+    input PW_D_I12;
+    input PW_D_I13;
+    input PW_D_I14;
+    input PW_D_I15;
+    input PW_D_I16;
+    input PW_D_I17;
+    input PW_D_I18;
+    input PW_D_I19;
+    input PW_D_I2;
+    input PW_D_I20;
+    input PW_D_I21;
+    input PW_D_I22;
+    input PW_D_I23;
+    input PW_D_I24;
+    input PW_D_I25;
+    input PW_D_I26;
+    input PW_D_I27;
+    input PW_D_I28;
+    input PW_D_I29;
+    input PW_D_I3;
+    input PW_D_I30;
+    input PW_D_I31;
+    input PW_D_I32;
+    input PW_D_I4;
+    input PW_D_I5;
+    input PW_D_I6;
+    input PW_D_I7;
+    input PW_D_I8;
+    input PW_D_I9;
+    input PW_I;
+    input P_A_I1;
+    input P_A_I10;
+    input P_A_I11;
+    input P_A_I12;
+    input P_A_I13;
+    input P_A_I14;
+    input P_A_I15;
+    input P_A_I16;
+    input P_A_I17;
+    input P_A_I18;
+    input P_A_I19;
+    input P_A_I2;
+    input P_A_I20;
+    input P_A_I21;
+    input P_A_I22;
+    input P_A_I23;
+    input P_A_I24;
+    input P_A_I25;
+    input P_A_I26;
+    input P_A_I27;
+    input P_A_I28;
+    input P_A_I29;
+    input P_A_I3;
+    input P_A_I4;
+    input P_A_I5;
+    input P_A_I6;
+    input P_A_I7;
+    input P_A_I8;
+    input P_A_I9;
+    input P_CK_E_I;
+    input P_CK_I;
+    input P_ECC_I;
+    input P_E_I;
+    output P_RDY_O;
+    output P_RD_O1;
+    output P_RD_O10;
+    output P_RD_O11;
+    output P_RD_O12;
+    output P_RD_O13;
+    output P_RD_O14;
+    output P_RD_O15;
+    output P_RD_O16;
+    output P_RD_O17;
+    output P_RD_O18;
+    output P_RD_O19;
+    output P_RD_O2;
+    output P_RD_O20;
+    output P_RD_O21;
+    output P_RD_O22;
+    output P_RD_O23;
+    output P_RD_O24;
+    output P_RD_O25;
+    output P_RD_O26;
+    output P_RD_O27;
+    output P_RD_O28;
+    output P_RD_O29;
+    output P_RD_O3;
+    output P_RD_O30;
+    output P_RD_O31;
+    output P_RD_O32;
+    output P_RD_O4;
+    output P_RD_O5;
+    output P_RD_O6;
+    output P_RD_O7;
+    output P_RD_O8;
+    output P_RD_O9;
+    input P_RS_I;
+    input P_SEL_I;
+    output P_VER_O;
+    input RAMCTL_I1;
+    input RAMCTL_I2;
+    input RAMCTL_I3;
+    input RAMCTL_I4;
+    input RAMCTL_I5;
+    input RAMCTL_I6;
+    input RAMCTL_I7;
+    input RAMCTL_I8;
+    output RD_O1;
+    output RD_O10;
+    output RD_O11;
+    output RD_O12;
+    output RD_O13;
+    output RD_O14;
+    output RD_O15;
+    output RD_O16;
+    output RD_O17;
+    output RD_O18;
+    output RD_O19;
+    output RD_O2;
+    output RD_O20;
+    output RD_O21;
+    output RD_O22;
+    output RD_O23;
+    output RD_O24;
+    output RD_O25;
+    output RD_O26;
+    output RD_O27;
+    output RD_O28;
+    output RD_O29;
+    output RD_O3;
+    output RD_O30;
+    output RD_O31;
+    output RD_O32;
+    output RD_O33;
+    output RD_O34;
+    output RD_O35;
+    output RD_O36;
+    output RD_O37;
+    output RD_O38;
+    output RD_O39;
+    output RD_O4;
+    output RD_O40;
+    output RD_O41;
+    output RD_O42;
+    output RD_O43;
+    output RD_O44;
+    output RD_O45;
+    output RD_O46;
+    output RD_O47;
+    output RD_O48;
+    output RD_O49;
+    output RD_O5;
+    output RD_O50;
+    output RD_O51;
+    output RD_O52;
+    output RD_O53;
+    output RD_O54;
+    output RD_O55;
+    output RD_O56;
+    output RD_O57;
+    output RD_O58;
+    output RD_O59;
+    output RD_O6;
+    output RD_O60;
+    output RD_O61;
+    output RD_O62;
+    output RD_O63;
+    output RD_O64;
+    output RD_O7;
+    output RD_O8;
+    output RD_O9;
+    input RS_BYP_I;
+    input R_DM_I1;
+    input R_DM_I10;
+    input R_DM_I11;
+    input R_DM_I12;
+    input R_DM_I13;
+    input R_DM_I14;
+    input R_DM_I15;
+    input R_DM_I16;
+    input R_DM_I17;
+    input R_DM_I18;
+    input R_DM_I19;
+    input R_DM_I2;
+    input R_DM_I20;
+    input R_DM_I21;
+    input R_DM_I22;
+    input R_DM_I23;
+    input R_DM_I24;
+    input R_DM_I25;
+    input R_DM_I26;
+    input R_DM_I27;
+    input R_DM_I28;
+    input R_DM_I29;
+    input R_DM_I3;
+    input R_DM_I30;
+    input R_DM_I31;
+    input R_DM_I32;
+    input R_DM_I33;
+    input R_DM_I34;
+    input R_DM_I35;
+    input R_DM_I36;
+    input R_DM_I37;
+    input R_DM_I38;
+    input R_DM_I39;
+    input R_DM_I4;
+    input R_DM_I40;
+    input R_DM_I41;
+    input R_DM_I42;
+    input R_DM_I43;
+    input R_DM_I44;
+    input R_DM_I45;
+    input R_DM_I46;
+    input R_DM_I47;
+    input R_DM_I48;
+    input R_DM_I49;
+    input R_DM_I5;
+    input R_DM_I50;
+    input R_DM_I51;
+    input R_DM_I52;
+    input R_DM_I53;
+    input R_DM_I54;
+    input R_DM_I55;
+    input R_DM_I56;
+    input R_DM_I57;
+    input R_DM_I58;
+    input R_DM_I59;
+    input R_DM_I6;
+    input R_DM_I60;
+    input R_DM_I61;
+    input R_DM_I62;
+    input R_DM_I63;
+    input R_DM_I64;
+    input R_DM_I7;
+    input R_DM_I8;
+    input R_DM_I9;
+    input R_DP_I1;
+    input R_DP_I10;
+    input R_DP_I11;
+    input R_DP_I12;
+    input R_DP_I13;
+    input R_DP_I14;
+    input R_DP_I15;
+    input R_DP_I16;
+    input R_DP_I17;
+    input R_DP_I18;
+    input R_DP_I19;
+    input R_DP_I2;
+    input R_DP_I20;
+    input R_DP_I21;
+    input R_DP_I22;
+    input R_DP_I23;
+    input R_DP_I24;
+    input R_DP_I25;
+    input R_DP_I26;
+    input R_DP_I27;
+    input R_DP_I28;
+    input R_DP_I29;
+    input R_DP_I3;
+    input R_DP_I30;
+    input R_DP_I31;
+    input R_DP_I32;
+    input R_DP_I4;
+    input R_DP_I5;
+    input R_DP_I6;
+    input R_DP_I7;
+    input R_DP_I8;
+    input R_DP_I9;
+    input R_IDM_I1;
+    input R_IDM_I2;
+    input R_IDM_I3;
+    input R_IDM_I4;
+    input R_IDP_I1;
+    input R_IDP_I2;
+    input R_IDP_I3;
+    input R_IDP_I4;
+    output R_IDS_O1;
+    output R_IDS_O2;
+    output R_IDS_O3;
+    output R_IDS_O4;
+    output R_IDS_O5;
+    output R_IDS_O6;
+    output R_IDS_O7;
+    output R_IDS_O8;
+    input R_LSTM_I;
+    input R_LSTP_I;
+    output R_LST_O;
+    output R_RDYM_O;
+    output R_RDYP_O;
+    input R_RDY_I;
+    input R_RSPM_I1;
+    input R_RSPM_I2;
+    input R_RSPP_I1;
+    input R_RSPP_I2;
+    output R_RSP_O1;
+    output R_RSP_O2;
+    input R_VDM_I;
+    input R_VDP_I;
+    output R_VD_O;
+    input SE_I;
+    output SWDO_E_O;
+    output SWDO_O;
+    input SW_CK_I;
+    input SW_DI_I;
+    output TDO_O;
+    input TE_INI_I;
+    output T_CK_O;
+    output T_CTL_O;
+    output T_DATA_O1;
+    output T_DATA_O10;
+    output T_DATA_O11;
+    output T_DATA_O12;
+    output T_DATA_O13;
+    output T_DATA_O14;
+    output T_DATA_O15;
+    output T_DATA_O16;
+    output T_DATA_O17;
+    output T_DATA_O18;
+    output T_DATA_O19;
+    output T_DATA_O2;
+    output T_DATA_O20;
+    output T_DATA_O21;
+    output T_DATA_O22;
+    output T_DATA_O23;
+    output T_DATA_O24;
+    output T_DATA_O25;
+    output T_DATA_O26;
+    output T_DATA_O27;
+    output T_DATA_O28;
+    output T_DATA_O29;
+    output T_DATA_O3;
+    output T_DATA_O30;
+    output T_DATA_O31;
+    output T_DATA_O32;
+    output T_DATA_O4;
+    output T_DATA_O5;
+    output T_DATA_O6;
+    output T_DATA_O7;
+    output T_DATA_O8;
+    output T_DATA_O9;
+    input T_DI_I;
+    input VINI_I;
+    output W_DM_O1;
+    output W_DM_O10;
+    output W_DM_O11;
+    output W_DM_O12;
+    output W_DM_O13;
+    output W_DM_O14;
+    output W_DM_O15;
+    output W_DM_O16;
+    output W_DM_O17;
+    output W_DM_O18;
+    output W_DM_O19;
+    output W_DM_O2;
+    output W_DM_O20;
+    output W_DM_O21;
+    output W_DM_O22;
+    output W_DM_O23;
+    output W_DM_O24;
+    output W_DM_O25;
+    output W_DM_O26;
+    output W_DM_O27;
+    output W_DM_O28;
+    output W_DM_O29;
+    output W_DM_O3;
+    output W_DM_O30;
+    output W_DM_O31;
+    output W_DM_O32;
+    output W_DM_O33;
+    output W_DM_O34;
+    output W_DM_O35;
+    output W_DM_O36;
+    output W_DM_O37;
+    output W_DM_O38;
+    output W_DM_O39;
+    output W_DM_O4;
+    output W_DM_O40;
+    output W_DM_O41;
+    output W_DM_O42;
+    output W_DM_O43;
+    output W_DM_O44;
+    output W_DM_O45;
+    output W_DM_O46;
+    output W_DM_O47;
+    output W_DM_O48;
+    output W_DM_O49;
+    output W_DM_O5;
+    output W_DM_O50;
+    output W_DM_O51;
+    output W_DM_O52;
+    output W_DM_O53;
+    output W_DM_O54;
+    output W_DM_O55;
+    output W_DM_O56;
+    output W_DM_O57;
+    output W_DM_O58;
+    output W_DM_O59;
+    output W_DM_O6;
+    output W_DM_O60;
+    output W_DM_O61;
+    output W_DM_O62;
+    output W_DM_O63;
+    output W_DM_O64;
+    output W_DM_O7;
+    output W_DM_O8;
+    output W_DM_O9;
+    output W_DP_O1;
+    output W_DP_O10;
+    output W_DP_O11;
+    output W_DP_O12;
+    output W_DP_O13;
+    output W_DP_O14;
+    output W_DP_O15;
+    output W_DP_O16;
+    output W_DP_O17;
+    output W_DP_O18;
+    output W_DP_O19;
+    output W_DP_O2;
+    output W_DP_O20;
+    output W_DP_O21;
+    output W_DP_O22;
+    output W_DP_O23;
+    output W_DP_O24;
+    output W_DP_O25;
+    output W_DP_O26;
+    output W_DP_O27;
+    output W_DP_O28;
+    output W_DP_O29;
+    output W_DP_O3;
+    output W_DP_O30;
+    output W_DP_O31;
+    output W_DP_O32;
+    output W_DP_O4;
+    output W_DP_O5;
+    output W_DP_O6;
+    output W_DP_O7;
+    output W_DP_O8;
+    output W_DP_O9;
+    input W_D_I1;
+    input W_D_I10;
+    input W_D_I11;
+    input W_D_I12;
+    input W_D_I13;
+    input W_D_I14;
+    input W_D_I15;
+    input W_D_I16;
+    input W_D_I17;
+    input W_D_I18;
+    input W_D_I19;
+    input W_D_I2;
+    input W_D_I20;
+    input W_D_I21;
+    input W_D_I22;
+    input W_D_I23;
+    input W_D_I24;
+    input W_D_I25;
+    input W_D_I26;
+    input W_D_I27;
+    input W_D_I28;
+    input W_D_I29;
+    input W_D_I3;
+    input W_D_I30;
+    input W_D_I31;
+    input W_D_I32;
+    input W_D_I33;
+    input W_D_I34;
+    input W_D_I35;
+    input W_D_I36;
+    input W_D_I37;
+    input W_D_I38;
+    input W_D_I39;
+    input W_D_I4;
+    input W_D_I40;
+    input W_D_I41;
+    input W_D_I42;
+    input W_D_I43;
+    input W_D_I44;
+    input W_D_I45;
+    input W_D_I46;
+    input W_D_I47;
+    input W_D_I48;
+    input W_D_I49;
+    input W_D_I5;
+    input W_D_I50;
+    input W_D_I51;
+    input W_D_I52;
+    input W_D_I53;
+    input W_D_I54;
+    input W_D_I55;
+    input W_D_I56;
+    input W_D_I57;
+    input W_D_I58;
+    input W_D_I59;
+    input W_D_I6;
+    input W_D_I60;
+    input W_D_I61;
+    input W_D_I62;
+    input W_D_I63;
+    input W_D_I64;
+    input W_D_I7;
+    input W_D_I8;
+    input W_D_I9;
+    output W_IDM_O1;
+    output W_IDM_O2;
+    output W_IDM_O3;
+    output W_IDM_O4;
+    output W_IDP_O1;
+    output W_IDP_O2;
+    output W_IDP_O3;
+    output W_IDP_O4;
+    input W_IDS_I1;
+    input W_IDS_I2;
+    input W_IDS_I3;
+    input W_IDS_I4;
+    input W_IDS_I5;
+    input W_IDS_I6;
+    input W_IDS_I7;
+    input W_IDS_I8;
+    output W_LSTM_O;
+    output W_LSTP_O;
+    input W_LST_I;
+    output W_RDY_O;
+    input W_RYM_I;
+    input W_RYP_I;
+    output W_SBM_O1;
+    output W_SBM_O2;
+    output W_SBM_O3;
+    output W_SBM_O4;
+    output W_SBM_O5;
+    output W_SBM_O6;
+    output W_SBM_O7;
+    output W_SBM_O8;
+    output W_SBP_O1;
+    output W_SBP_O2;
+    output W_SBP_O3;
+    output W_SBP_O4;
+    input W_SBS_I1;
+    input W_SBS_I2;
+    input W_SBS_I3;
+    input W_SBS_I4;
+    input W_SBS_I5;
+    input W_SBS_I6;
+    input W_SBS_I7;
+    input W_SBS_I8;
+    output W_VDM_O;
+    output W_VDP_O;
+    input W_VD_I;
+endmodule
+
+(* blackbox *)
+module NX_R5_L_WRAP(CLKIN, nRESET0, nSYSPORESET, nCPUHALT0, DBGNOCLKSTOP, nCLKSTOPPED0, nWFEPIPESTOPPED0, nWFIPIPESTOPPED0, EVENTI0, EVENTO0, VINITHI0, CFGEE, CFGIE, INITRAMA0, LOCZRAMA0, TEINIT, CFGNMFI0, PARECCENRAM0, PARITYLEVEL, ERRENRAM0, INITPPX0
+, nFIQ0, nIRQ0, nPMUIRQ0, ACLKENM0, AWREADYM0, AWSHAREM0, AWVALIDM0, WLASTM0, WREADYM0, WVALIDM0, BREADYM0, BVALIDM0, ARREADYM0, ARSHAREM0, ARVALIDM0, RLASTM0, RREADYM0, RVALIDM0, ACLKENS0, AWREADYS0, AWVALIDS0
+, WLASTS0, WREADYS0, WVALIDS0, BREADYS0, BVALIDS0, ARREADYS0, ARVALIDS0, RLASTS0, RREADYS0, RVALIDS0, ACLKENP0, AWVALIDP0, AWREADYP0, WLASTP0, WVALIDP0, WREADYP0, BVALIDP0, BREADYP0, ARVALIDP0, ARREADYP0, RLASTP0
+, RVALIDP0, RREADYP0, DBGEN0, NIDEN0, EDBGRQ0, DBGACK0, DBGRSTREQ0, COMMRX0, COMMTX0, DBGNOPWRDWN, DBGROMADDRV, DBGSELFADDRV0, nETMPORESET, ETMEN0, nVALIRQ0, nVALFIQ0, nVALRESET0, FPIXC0, FPOFC0, FPUFC0, FPIOC0
+, FPDZC0, FPIDC0, ATRESETn, TRACECLK, TRACECTL, PCLKSYS, PCLKENSYS, PRESETSYSn, PENABLESYS, PREADYSYS, PSELSYS, PSLVERRSYS, PWRITESYS, CDBGPWRUPACK, CDBGPWRUPREQ, CDBGRSTACK, CDBGRSTREQ, CSYSPWRUPACK, CSYSPWRUPREQ, DEVICEEN, JTAGNSW
+, nPOTRST, nTDOEN, nTRST, SWCLKTCK, SWDITMS, SWDO, SWDOEN, TDI, TDO, PPXBASE0, PPXSIZE0, PPVBASE0, PPVSIZE0, AWADDRM0, AWBURSTM0, AWCACHEM0, AWIDM0, AWLENM0, AWLOCKM0, AWPROTM0, AWSIZEM0
+, AWINNERM0, WDATAM0, WIDM0, WSTRBM0, BIDM0, BRESPM0, ARADDRM0, ARBURSTM0, ARCACHEM0, ARIDM0, ARLENM0, ARLOCKM0, ARPROTM0, ARSIZEM0, ARINNERM0, RDATAM0, RIDM0, RRESPM0, AWADDRS0, AWBURSTS0, AWCACHES0
+, AWIDS0, AWLENS0, AWLOCKS0, AWPROTS0, AWSIZES0, WDATAS0, WIDS0, WSTRBS0, BIDS0, BRESPS0, ARADDRS0, ARBURSTS0, ARCACHES0, ARIDS0, ARLENS0, ARLOCKS0, ARPROTS0, ARSIZES0, RDATAS0, RIDS0, RRESPS0
+, AWIDP0, AWADDRP0, AWLENP0, AWSIZEP0, AWBURSTP0, AWLOCKP0, AWCACHEP0, AWPROTP0, WIDP0, WDATAP0, WSTRBP0, BIDP0, BRESPP0, ARIDP0, ARADDRP0, ARLENP0, ARSIZEP0, ARBURSTP0, ARLOCKP0, ARCACHEP0, ARPROTP0
+, RIDP0, RDATAP0, RRESPP0, DBGROMADDR, DBGSELFADDR0, ETMASICCTL0, ETMEXTOUT0, TRACEDATA, PADDRSYS, PRDATASYS, PWDATASYS, GROUPID);
+    input ACLKENM0;
+    input ACLKENP0;
+    input ACLKENS0;
+    output [31:0] ARADDRM0;
+    output [31:0] ARADDRP0;
+    input [31:0] ARADDRS0;
+    output [1:0] ARBURSTM0;
+    output [1:0] ARBURSTP0;
+    input [1:0] ARBURSTS0;
+    output [3:0] ARCACHEM0;
+    output [3:0] ARCACHEP0;
+    input [3:0] ARCACHES0;
+    output [3:0] ARIDM0;
+    output [3:0] ARIDP0;
+    input [7:0] ARIDS0;
+    output [3:0] ARINNERM0;
+    output [3:0] ARLENM0;
+    output [3:0] ARLENP0;
+    input [3:0] ARLENS0;
+    output [1:0] ARLOCKM0;
+    output [1:0] ARLOCKP0;
+    input [1:0] ARLOCKS0;
+    output [2:0] ARPROTM0;
+    output [2:0] ARPROTP0;
+    input [2:0] ARPROTS0;
+    input ARREADYM0;
+    input ARREADYP0;
+    output ARREADYS0;
+    output ARSHAREM0;
+    output [2:0] ARSIZEM0;
+    output [2:0] ARSIZEP0;
+    input [2:0] ARSIZES0;
+    output ARVALIDM0;
+    output ARVALIDP0;
+    input ARVALIDS0;
+    input ATRESETn;
+    output [31:0] AWADDRM0;
+    output [31:0] AWADDRP0;
+    input [31:0] AWADDRS0;
+    output [1:0] AWBURSTM0;
+    output [1:0] AWBURSTP0;
+    input [1:0] AWBURSTS0;
+    output [3:0] AWCACHEM0;
+    output [3:0] AWCACHEP0;
+    input [3:0] AWCACHES0;
+    output [3:0] AWIDM0;
+    output [3:0] AWIDP0;
+    input [7:0] AWIDS0;
+    output [3:0] AWINNERM0;
+    output [3:0] AWLENM0;
+    output [3:0] AWLENP0;
+    input [3:0] AWLENS0;
+    output [1:0] AWLOCKM0;
+    output [1:0] AWLOCKP0;
+    input [1:0] AWLOCKS0;
+    output [2:0] AWPROTM0;
+    output [2:0] AWPROTP0;
+    input [2:0] AWPROTS0;
+    input AWREADYM0;
+    input AWREADYP0;
+    output AWREADYS0;
+    output AWSHAREM0;
+    output [2:0] AWSIZEM0;
+    output [2:0] AWSIZEP0;
+    input [2:0] AWSIZES0;
+    output AWVALIDM0;
+    output AWVALIDP0;
+    input AWVALIDS0;
+    input [3:0] BIDM0;
+    input [3:0] BIDP0;
+    output [7:0] BIDS0;
+    output BREADYM0;
+    output BREADYP0;
+    input BREADYS0;
+    input [1:0] BRESPM0;
+    input [1:0] BRESPP0;
+    output [1:0] BRESPS0;
+    input BVALIDM0;
+    input BVALIDP0;
+    output BVALIDS0;
+    input CDBGPWRUPACK;
+    output CDBGPWRUPREQ;
+    input CDBGRSTACK;
+    output CDBGRSTREQ;
+    input CFGEE;
+    input CFGIE;
+    input CFGNMFI0;
+    input CLKIN;
+    output COMMRX0;
+    output COMMTX0;
+    input CSYSPWRUPACK;
+    output CSYSPWRUPREQ;
+    output DBGACK0;
+    input DBGEN0;
+    input DBGNOCLKSTOP;
+    output DBGNOPWRDWN;
+    input [19:0] DBGROMADDR;
+    input DBGROMADDRV;
+    output DBGRSTREQ0;
+    input [19:0] DBGSELFADDR0;
+    input DBGSELFADDRV0;
+    input DEVICEEN;
+    input EDBGRQ0;
+    input ERRENRAM0;
+    output [7:0] ETMASICCTL0;
+    output ETMEN0;
+    output [1:0] ETMEXTOUT0;
+    input EVENTI0;
+    output EVENTO0;
+    output FPDZC0;
+    output FPIDC0;
+    output FPIOC0;
+    output FPIXC0;
+    output FPOFC0;
+    output FPUFC0;
+    input [3:0] GROUPID;
+    input INITPPX0;
+    input INITRAMA0;
+    output JTAGNSW;
+    input LOCZRAMA0;
+    input NIDEN0;
+    input [28:0] PADDRSYS;
+    input PARECCENRAM0;
+    input PARITYLEVEL;
+    input PCLKENSYS;
+    input PCLKSYS;
+    input PENABLESYS;
+    input [19:0] PPVBASE0;
+    input [4:0] PPVSIZE0;
+    input [19:0] PPXBASE0;
+    input [4:0] PPXSIZE0;
+    output [31:0] PRDATASYS;
+    output PREADYSYS;
+    input PRESETSYSn;
+    input PSELSYS;
+    output PSLVERRSYS;
+    input [31:0] PWDATASYS;
+    input PWRITESYS;
+    input [63:0] RDATAM0;
+    input [31:0] RDATAP0;
+    output [63:0] RDATAS0;
+    input [3:0] RIDM0;
+    input [3:0] RIDP0;
+    output [7:0] RIDS0;
+    input RLASTM0;
+    input RLASTP0;
+    output RLASTS0;
+    output RREADYM0;
+    output RREADYP0;
+    input RREADYS0;
+    input [1:0] RRESPM0;
+    input [1:0] RRESPP0;
+    output [1:0] RRESPS0;
+    input RVALIDM0;
+    input RVALIDP0;
+    output RVALIDS0;
+    input SWCLKTCK;
+    input SWDITMS;
+    output SWDO;
+    output SWDOEN;
+    input TDI;
+    output TDO;
+    input TEINIT;
+    output TRACECLK;
+    output TRACECTL;
+    output [31:0] TRACEDATA;
+    input VINITHI0;
+    output [63:0] WDATAM0;
+    output [31:0] WDATAP0;
+    input [63:0] WDATAS0;
+    output [3:0] WIDM0;
+    output [3:0] WIDP0;
+    input [7:0] WIDS0;
+    output WLASTM0;
+    output WLASTP0;
+    input WLASTS0;
+    input WREADYM0;
+    input WREADYP0;
+    output WREADYS0;
+    output [7:0] WSTRBM0;
+    output [3:0] WSTRBP0;
+    input [7:0] WSTRBS0;
+    output WVALIDM0;
+    output WVALIDP0;
+    input WVALIDS0;
+    output nCLKSTOPPED0;
+    input nCPUHALT0;
+    input nETMPORESET;
+    input nFIQ0;
+    input nIRQ0;
+    output nPMUIRQ0;
+    input nPOTRST;
+    input nRESET0;
+    input nSYSPORESET;
+    output nTDOEN;
+    input nTRST;
+    output nVALFIQ0;
+    output nVALIRQ0;
+    output nVALRESET0;
+    output nWFEPIPESTOPPED0;
+    output nWFIPIPESTOPPED0;
+endmodule
+
+(* blackbox *)
+module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13
+, AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10
+, BI11, BI12, BI13, BI14, BI15, BI16, BI17, BI18, BI19, BI20, BI21, BI22, BI23, BI24, ACOR, AERR, BCOR, BERR, AO1, AO2, AO3
+, AO4, AO5, AO6, AO7, AO8, AO9, AO10, AO11, AO12, AO13, AO14, AO15, AO16, AO17, AO18, AO19, AO20, AO21, AO22, AO23, AO24
+, BO1, BO2, BO3, BO4, BO5, BO6, BO7, BO8, BO9, BO10, BO11, BO12, BO13, BO14, BO15, BO16, BO17, BO18, BO19, BO20, BO21
+, BO22, BO23, BO24, AA1, AA2, AA3, AA4, AA5, AA6, AA7, AA8, AA9, AA10, AA11, AA12, AA13, AA14, AA15, AA16, ACS, AWE
+, AR, BA1, BA2, BA3, BA4, BA5, BA6, BA7, BA8, BA9, BA10, BA11, BA12, BA13, BA14, BA15, BA16, BCS, BWE, BR);
+    input AA1;
+    input AA10;
+    input AA11;
+    input AA12;
+    input AA13;
+    input AA14;
+    input AA15;
+    input AA16;
+    input AA2;
+    input AA3;
+    input AA4;
+    input AA5;
+    input AA6;
+    input AA7;
+    input AA8;
+    input AA9;
+    input ACK;
+    input ACKC;
+    input ACKD;
+    input ACKR;
+    output ACOR;
+    input ACS;
+    output AERR;
+    input AI1;
+    input AI10;
+    input AI11;
+    input AI12;
+    input AI13;
+    input AI14;
+    input AI15;
+    input AI16;
+    input AI17;
+    input AI18;
+    input AI19;
+    input AI2;
+    input AI20;
+    input AI21;
+    input AI22;
+    input AI23;
+    input AI24;
+    input AI3;
+    input AI4;
+    input AI5;
+    input AI6;
+    input AI7;
+    input AI8;
+    input AI9;
+    output AO1;
+    output AO10;
+    output AO11;
+    output AO12;
+    output AO13;
+    output AO14;
+    output AO15;
+    output AO16;
+    output AO17;
+    output AO18;
+    output AO19;
+    output AO2;
+    output AO20;
+    output AO21;
+    output AO22;
+    output AO23;
+    output AO24;
+    output AO3;
+    output AO4;
+    output AO5;
+    output AO6;
+    output AO7;
+    output AO8;
+    output AO9;
+    input AR;
+    input AWE;
+    input BA1;
+    input BA10;
+    input BA11;
+    input BA12;
+    input BA13;
+    input BA14;
+    input BA15;
+    input BA16;
+    input BA2;
+    input BA3;
+    input BA4;
+    input BA5;
+    input BA6;
+    input BA7;
+    input BA8;
+    input BA9;
+    input BCK;
+    input BCKC;
+    input BCKD;
+    input BCKR;
+    output BCOR;
+    input BCS;
+    output BERR;
+    input BI1;
+    input BI10;
+    input BI11;
+    input BI12;
+    input BI13;
+    input BI14;
+    input BI15;
+    input BI16;
+    input BI17;
+    input BI18;
+    input BI19;
+    input BI2;
+    input BI20;
+    input BI21;
+    input BI22;
+    input BI23;
+    input BI24;
+    input BI3;
+    input BI4;
+    input BI5;
+    input BI6;
+    input BI7;
+    input BI8;
+    input BI9;
+    output BO1;
+    output BO10;
+    output BO11;
+    output BO12;
+    output BO13;
+    output BO14;
+    output BO15;
+    output BO16;
+    output BO17;
+    output BO18;
+    output BO19;
+    output BO2;
+    output BO20;
+    output BO21;
+    output BO22;
+    output BO23;
+    output BO24;
+    output BO3;
+    output BO4;
+    output BO5;
+    output BO6;
+    output BO7;
+    output BO8;
+    output BO9;
+    input BR;
+    input BWE;
+    parameter mcka_edge = 1'b0;
+    parameter mckb_edge = 1'b0;
+    parameter mem_ctxt = "";
+    parameter pcka_edge = 1'b0;
+    parameter pckb_edge = 1'b0;
+    parameter pipe_ia = 1'b0;
+    parameter pipe_ib = 1'b0;
+    parameter pipe_oa = 1'b0;
+    parameter pipe_ob = 1'b0;
+    parameter raw_config0 = 4'b0000;
+    parameter raw_config1 = 16'b0000000000000000;
+    parameter raw_l_enable = 1'b0;
+    parameter raw_l_extend = 4'b0000;
+    parameter raw_u_enable = 1'b0;
+    parameter raw_u_extend = 8'b00000000;
+    parameter std_mode = "";
+endmodule
+
+(* blackbox *)
+module NX_RAM_SLOWECC_1K_36_1r1w(ACK, BCK, ACOR, AERR, ACS, AWE, AR, BCS, BWE, BR, AO, AI, AA);
+    input [9:0] AA;
+    input ACK;
+    output ACOR;
+    input ACS;
+    output AERR;
+    input [35:0] AI;
+    output [35:0] AO;
+    input AR;
+    input AWE;
+    input BCK;
+    input BCS;
+    input BR;
+    input BWE;
+    parameter mem_ctxt = "";
+endmodule
+
+(* blackbox *)
+module NX_RAM_WRAP(ACK, ACKD, ACKR, BCK, BCKD, BCKR, ACOR, AERR, BCOR, BERR, ACS, AWE, AR, BCS, BWE, BR, BI, AO, BO, AI, AA
+, BA);
+    input [15:0] AA;
+    input ACK;
+    input ACKD;
+    input ACKR;
+    output ACOR;
+    input ACS;
+    output AERR;
+    input [23:0] AI;
+    output [23:0] AO;
+    input AR;
+    input AWE;
+    input [15:0] BA;
+    input BCK;
+    input BCKD;
+    input BCKR;
+    output BCOR;
+    input BCS;
+    output BERR;
+    input [23:0] BI;
+    output [23:0] BO;
+    input BR;
+    input BWE;
+    parameter mcka_edge = 1'b0;
+    parameter mckb_edge = 1'b0;
+    parameter mem_ctxt = "";
+    parameter pcka_edge = 1'b0;
+    parameter pckb_edge = 1'b0;
+    parameter pipe_ia = 1'b0;
+    parameter pipe_ib = 1'b0;
+    parameter pipe_oa = 1'b0;
+    parameter pipe_ob = 1'b0;
+    parameter raw_config0 = 4'b0000;
+    parameter raw_config1 = 16'b0000000000000000;
+    parameter raw_l_enable = 1'b0;
+    parameter raw_l_extend = 4'b0000;
+    parameter raw_u_enable = 1'b0;
+    parameter raw_u_extend = 8'b00000000;
+    parameter std_mode = "";
+endmodule
+
+(* blackbox *)
+module NX_RB(CK1, CK2, CK3, CK4, EI1, EI2, EI3, EI4, EI5, EI6, EI7, EI8, EI9, EI10, EI11, EI12, EI13, EI14, EI15, EI16, EI17
+, EI18, EI19, EI20, EI21, EI22, EI23, EI24, EI25, EI26, EI27, EI28, EI29, EI30, EI31, EI32, EI33, EI34, EI35, EI36, EI37, EI38
+, EI39, EI40, EI41, EI42, EI43, EI44, EI45, EI46, EI47, EI48, EI49, EI50, EI51, EI52, EI53, EI54, EI55, EI56, EI57, EI58, EI59
+, EI60, EI61, EI62, EI63, EI64, EI65, EI66, EI67, EI68, EI69, EI70, EI71, EI72, EI73, EI74, EI75, EI76, EI77, EI78, EI79, EI80
+, EI81, EI82, EI83, EI84, EI85, EI86, EI87, EI88, EI89, EI90, EI91, EI92, EI93, EI94, EI95, EI96, EI97, EI98, EI99, EI100, EI101
+, EI102, EI103, EI104, EI105, EI106, EI107, EI108, EI109, EI110, EI111, EI112, EI113, EI114, EI115, EI116, EI117, EI118, EI119, EI120, EI121, EI122
+, EI123, EI124, EI125, EI126, EI127, EI128, EI129, EI130, EI131, EI132, EI133, EI134, EI135, EI136, EI137, EI138, EI139, EI140, EI141, EI142, EI143
+, EI144, EI145, EI146, EI147, EI148, EI149, EI150, EI151, EI152, EI153, EI154, EI155, EI156, EI157, EI158, EI159, EI160, EI161, EI162, EI163, EI164
+, EI165, EI166, EI167, EI168, EI169, EI170, EI171, EI172, EI173, EI174, EI175, EI176, EI177, EI178, EI179, EI180, EI181, EI182, EI183, EI184, EI185
+, EI186, EI187, EI188, EI189, EI190, EI191, EI192, EI_CK, EO_CK, EO1, EO2, EO3, EO4, EO5, EO6, EO7, EO8, EO9, EO10, EO11, EO12
+, EO13, EO14, EO15, EO16, EO17, EO18, EO19, EO20, EO21, EO22, EO23, EO24, EO25, EO26, EO27, EO28, EO29, EO30, EO31, EO32, EO33
+, EO34, EO35, EO36, EO37, EO38, EO39, EO40, EO41, EO42, EO43, EO44, EO45, EO46, EO47, EO48, EO49, EO50, EO51, EO52, EO53, EO54
+, EO55, EO56, EO57, EO58, EO59, EO60, EO61, EO62, EO63, EO64, EO65, EO66, EO67, EO68, EO69, EO70, EO71, EO72, EO73, EO74, EO75
+, EO76, EO77, EO78, EO79, EO80, EO81, EO82, EO83, EO84, EO85, EO86, EO87, EO88, EO89, EO90, EO91, EO92, EO93, EO94, EO95, EO96
+, EO97, EO98, EO99, EO100, EO101, EO102, EO103, EO104, EO105, EO106, EO107, EO108, EO109, EO110, EO111, EO112, EO113, EO114, EO115, EO116, EO117
+, EO118, EO119, EO120, EO121, EO122, EO123, EO124, EO125, EO126, EO127, EO128, EO129, EO130, EO131, EO132, EO133, EO134, EO135, EO136, EO137, EO138
+, EO139, EO140, EO141, EO142, EO143, EO144, EO145, EO146, EO147, EO148, EO149, EO150, EO151, EO152, EO153, EO154, EO155, EO156, EO157, EO158, EO159
+, EO160, EO161, EO162, EO163, EO164, EO165, EO166, EO167, EO168, EO169, EO170, EO171, EO172, EO173, EO174, EO175, EO176, EO177, EO178, EO179, EO180
+, EO181, EO182, EO183, EO184, EO185, EO186, EO187, EO188, EO189, EO190, EO191, EO192, FI1, FI2, FI3, FI4, FI5, FI6, FI7, FI8, FI9
+, FI10, FI11, FI12, FI13, FI14, FI15, FI16, FI17, FI18, FI19, FI20, FI21, FI22, FI23, FI24, FI25, FI26, FI27, FI28, FI29, FI30
+, FI31, FI32, FI33, FI34, FI35, FI36, FI37, FI38, FI39, FI40, FI41, FI42, FI43, FI44, FI45, FI46, FI47, FI48, FI49, FI50, FI51
+, FI52, FI53, FI54, FI55, FI56, FI57, FI58, FI59, FI60, FI61, FI62, FI63, FI64, FI65, FI66, FI67, FI68, FI69, FI70, FI71, FI72
+, FI73, FI74, FI75, FI76, FI77, FI78, FI79, FI80, FI81, FI82, FI83, FI84, FI85, FI86, FI87, FI88, FI89, FI90, FI91, FI92, FI93
+, FI94, FI95, FI96, FI97, FI98, FI99, FI100, FI101, FI102, FI103, FI104, FI105, FI106, FI107, FI108, FI109, FI110, FI111, FI112, FI113, FI114
+, FI115, FI116, FI117, FI118, FI119, FI120, FI121, FI122, FI123, FI124, FI125, FI126, FI127, FI128, FI129, FI130, FI131, FI132, FI133, FI134, FI135
+, FI136, FI137, FI138, FI139, FI140, FI141, FI142, FI143, FI144, FI145, FI146, FI147, FI148, FI149, FI150, FI151, FI152, FI153, FI154, FI155, FI156
+, FI157, FI158, FI159, FI160, FI161, FI162, FI163, FI164, FI165, FI166, FI167, FI168, FI169, FI170, FI171, FI172, FI173, FI174, FI175, FI176, FI177
+, FI178, FI179, FI180, FI181, FI182, FI183, FI184, FI185, FI186, FI187, FI188, FI189, FI190, FI191, FI192, FO1, FO2, FO3, FO4, FO5, FO6
+, FO7, FO8, FO9, FO10, FO11, FO12, FO13, FO14, FO15, FO16, FO17, FO18, FO19, FO20, FO21, FO22, FO23, FO24, FO25, FO26, FO27
+, FO28, FO29, FO30, FO31, FO32, FO33, FO34, FO35, FO36, FO37, FO38, FO39, FO40, FO41, FO42, FO43, FO44, FO45, FO46, FO47, FO48
+, FO49, FO50, FO51, FO52, FO53, FO54, FO55, FO56, FO57, FO58, FO59, FO60, FO61, FO62, FO63, FO64, FO65, FO66, FO67, FO68, FO69
+, FO70, FO71, FO72, FO73, FO74, FO75, FO76, FO77, FO78, FO79, FO80, FO81, FO82, FO83, FO84, FO85, FO86, FO87, FO88, FO89, FO90
+, FO91, FO92, FO93, FO94, FO95, FO96, FO97, FO98, FO99, FO100, FO101, FO102, FO103, FO104, FO105, FO106, FO107, FO108, FO109, FO110, FO111
+, FO112, FO113, FO114, FO115, FO116, FO117, FO118, FO119, FO120, FO121, FO122, FO123, FO124, FO125, FO126, FO127, FO128, FO129, FO130, FO131, FO132
+, FO133, FO134, FO135, FO136, FO137, FO138, FO139, FO140, FO141, FO142, FO143, FO144, FO145, FO146, FO147, FO148, FO149, FO150, FO151, FO152, FO153
+, FO154, FO155, FO156, FO157, FO158, FO159, FO160, FO161, FO162, FO163, FO164, FO165, FO166, FO167, FO168, FO169, FO170, FO171, FO172, FO173, FO174
+, FO175, FO176, FO177, FO178, FO179, FO180, FO181, FO182, FO183, FO184, FO185, FO186, FO187, FO188, FO189, FO190, FO191, FO192);
+    input CK1;
+    input CK2;
+    input CK3;
+    input CK4;
+    input EI1;
+    input EI10;
+    input EI100;
+    input EI101;
+    input EI102;
+    input EI103;
+    input EI104;
+    input EI105;
+    input EI106;
+    input EI107;
+    input EI108;
+    input EI109;
+    input EI11;
+    input EI110;
+    input EI111;
+    input EI112;
+    input EI113;
+    input EI114;
+    input EI115;
+    input EI116;
+    input EI117;
+    input EI118;
+    input EI119;
+    input EI12;
+    input EI120;
+    input EI121;
+    input EI122;
+    input EI123;
+    input EI124;
+    input EI125;
+    input EI126;
+    input EI127;
+    input EI128;
+    input EI129;
+    input EI13;
+    input EI130;
+    input EI131;
+    input EI132;
+    input EI133;
+    input EI134;
+    input EI135;
+    input EI136;
+    input EI137;
+    input EI138;
+    input EI139;
+    input EI14;
+    input EI140;
+    input EI141;
+    input EI142;
+    input EI143;
+    input EI144;
+    input EI145;
+    input EI146;
+    input EI147;
+    input EI148;
+    input EI149;
+    input EI15;
+    input EI150;
+    input EI151;
+    input EI152;
+    input EI153;
+    input EI154;
+    input EI155;
+    input EI156;
+    input EI157;
+    input EI158;
+    input EI159;
+    input EI16;
+    input EI160;
+    input EI161;
+    input EI162;
+    input EI163;
+    input EI164;
+    input EI165;
+    input EI166;
+    input EI167;
+    input EI168;
+    input EI169;
+    input EI17;
+    input EI170;
+    input EI171;
+    input EI172;
+    input EI173;
+    input EI174;
+    input EI175;
+    input EI176;
+    input EI177;
+    input EI178;
+    input EI179;
+    input EI18;
+    input EI180;
+    input EI181;
+    input EI182;
+    input EI183;
+    input EI184;
+    input EI185;
+    input EI186;
+    input EI187;
+    input EI188;
+    input EI189;
+    input EI19;
+    input EI190;
+    input EI191;
+    input EI192;
+    input EI2;
+    input EI20;
+    input EI21;
+    input EI22;
+    input EI23;
+    input EI24;
+    input EI25;
+    input EI26;
+    input EI27;
+    input EI28;
+    input EI29;
+    input EI3;
+    input EI30;
+    input EI31;
+    input EI32;
+    input EI33;
+    input EI34;
+    input EI35;
+    input EI36;
+    input EI37;
+    input EI38;
+    input EI39;
+    input EI4;
+    input EI40;
+    input EI41;
+    input EI42;
+    input EI43;
+    input EI44;
+    input EI45;
+    input EI46;
+    input EI47;
+    input EI48;
+    input EI49;
+    input EI5;
+    input EI50;
+    input EI51;
+    input EI52;
+    input EI53;
+    input EI54;
+    input EI55;
+    input EI56;
+    input EI57;
+    input EI58;
+    input EI59;
+    input EI6;
+    input EI60;
+    input EI61;
+    input EI62;
+    input EI63;
+    input EI64;
+    input EI65;
+    input EI66;
+    input EI67;
+    input EI68;
+    input EI69;
+    input EI7;
+    input EI70;
+    input EI71;
+    input EI72;
+    input EI73;
+    input EI74;
+    input EI75;
+    input EI76;
+    input EI77;
+    input EI78;
+    input EI79;
+    input EI8;
+    input EI80;
+    input EI81;
+    input EI82;
+    input EI83;
+    input EI84;
+    input EI85;
+    input EI86;
+    input EI87;
+    input EI88;
+    input EI89;
+    input EI9;
+    input EI90;
+    input EI91;
+    input EI92;
+    input EI93;
+    input EI94;
+    input EI95;
+    input EI96;
+    input EI97;
+    input EI98;
+    input EI99;
+    output EI_CK;
+    output EO1;
+    output EO10;
+    output EO100;
+    output EO101;
+    output EO102;
+    output EO103;
+    output EO104;
+    output EO105;
+    output EO106;
+    output EO107;
+    output EO108;
+    output EO109;
+    output EO11;
+    output EO110;
+    output EO111;
+    output EO112;
+    output EO113;
+    output EO114;
+    output EO115;
+    output EO116;
+    output EO117;
+    output EO118;
+    output EO119;
+    output EO12;
+    output EO120;
+    output EO121;
+    output EO122;
+    output EO123;
+    output EO124;
+    output EO125;
+    output EO126;
+    output EO127;
+    output EO128;
+    output EO129;
+    output EO13;
+    output EO130;
+    output EO131;
+    output EO132;
+    output EO133;
+    output EO134;
+    output EO135;
+    output EO136;
+    output EO137;
+    output EO138;
+    output EO139;
+    output EO14;
+    output EO140;
+    output EO141;
+    output EO142;
+    output EO143;
+    output EO144;
+    output EO145;
+    output EO146;
+    output EO147;
+    output EO148;
+    output EO149;
+    output EO15;
+    output EO150;
+    output EO151;
+    output EO152;
+    output EO153;
+    output EO154;
+    output EO155;
+    output EO156;
+    output EO157;
+    output EO158;
+    output EO159;
+    output EO16;
+    output EO160;
+    output EO161;
+    output EO162;
+    output EO163;
+    output EO164;
+    output EO165;
+    output EO166;
+    output EO167;
+    output EO168;
+    output EO169;
+    output EO17;
+    output EO170;
+    output EO171;
+    output EO172;
+    output EO173;
+    output EO174;
+    output EO175;
+    output EO176;
+    output EO177;
+    output EO178;
+    output EO179;
+    output EO18;
+    output EO180;
+    output EO181;
+    output EO182;
+    output EO183;
+    output EO184;
+    output EO185;
+    output EO186;
+    output EO187;
+    output EO188;
+    output EO189;
+    output EO19;
+    output EO190;
+    output EO191;
+    output EO192;
+    output EO2;
+    output EO20;
+    output EO21;
+    output EO22;
+    output EO23;
+    output EO24;
+    output EO25;
+    output EO26;
+    output EO27;
+    output EO28;
+    output EO29;
+    output EO3;
+    output EO30;
+    output EO31;
+    output EO32;
+    output EO33;
+    output EO34;
+    output EO35;
+    output EO36;
+    output EO37;
+    output EO38;
+    output EO39;
+    output EO4;
+    output EO40;
+    output EO41;
+    output EO42;
+    output EO43;
+    output EO44;
+    output EO45;
+    output EO46;
+    output EO47;
+    output EO48;
+    output EO49;
+    output EO5;
+    output EO50;
+    output EO51;
+    output EO52;
+    output EO53;
+    output EO54;
+    output EO55;
+    output EO56;
+    output EO57;
+    output EO58;
+    output EO59;
+    output EO6;
+    output EO60;
+    output EO61;
+    output EO62;
+    output EO63;
+    output EO64;
+    output EO65;
+    output EO66;
+    output EO67;
+    output EO68;
+    output EO69;
+    output EO7;
+    output EO70;
+    output EO71;
+    output EO72;
+    output EO73;
+    output EO74;
+    output EO75;
+    output EO76;
+    output EO77;
+    output EO78;
+    output EO79;
+    output EO8;
+    output EO80;
+    output EO81;
+    output EO82;
+    output EO83;
+    output EO84;
+    output EO85;
+    output EO86;
+    output EO87;
+    output EO88;
+    output EO89;
+    output EO9;
+    output EO90;
+    output EO91;
+    output EO92;
+    output EO93;
+    output EO94;
+    output EO95;
+    output EO96;
+    output EO97;
+    output EO98;
+    output EO99;
+    output EO_CK;
+    input FI1;
+    input FI10;
+    input FI100;
+    input FI101;
+    input FI102;
+    input FI103;
+    input FI104;
+    input FI105;
+    input FI106;
+    input FI107;
+    input FI108;
+    input FI109;
+    input FI11;
+    input FI110;
+    input FI111;
+    input FI112;
+    input FI113;
+    input FI114;
+    input FI115;
+    input FI116;
+    input FI117;
+    input FI118;
+    input FI119;
+    input FI12;
+    input FI120;
+    input FI121;
+    input FI122;
+    input FI123;
+    input FI124;
+    input FI125;
+    input FI126;
+    input FI127;
+    input FI128;
+    input FI129;
+    input FI13;
+    input FI130;
+    input FI131;
+    input FI132;
+    input FI133;
+    input FI134;
+    input FI135;
+    input FI136;
+    input FI137;
+    input FI138;
+    input FI139;
+    input FI14;
+    input FI140;
+    input FI141;
+    input FI142;
+    input FI143;
+    input FI144;
+    input FI145;
+    input FI146;
+    input FI147;
+    input FI148;
+    input FI149;
+    input FI15;
+    input FI150;
+    input FI151;
+    input FI152;
+    input FI153;
+    input FI154;
+    input FI155;
+    input FI156;
+    input FI157;
+    input FI158;
+    input FI159;
+    input FI16;
+    input FI160;
+    input FI161;
+    input FI162;
+    input FI163;
+    input FI164;
+    input FI165;
+    input FI166;
+    input FI167;
+    input FI168;
+    input FI169;
+    input FI17;
+    input FI170;
+    input FI171;
+    input FI172;
+    input FI173;
+    input FI174;
+    input FI175;
+    input FI176;
+    input FI177;
+    input FI178;
+    input FI179;
+    input FI18;
+    input FI180;
+    input FI181;
+    input FI182;
+    input FI183;
+    input FI184;
+    input FI185;
+    input FI186;
+    input FI187;
+    input FI188;
+    input FI189;
+    input FI19;
+    input FI190;
+    input FI191;
+    input FI192;
+    input FI2;
+    input FI20;
+    input FI21;
+    input FI22;
+    input FI23;
+    input FI24;
+    input FI25;
+    input FI26;
+    input FI27;
+    input FI28;
+    input FI29;
+    input FI3;
+    input FI30;
+    input FI31;
+    input FI32;
+    input FI33;
+    input FI34;
+    input FI35;
+    input FI36;
+    input FI37;
+    input FI38;
+    input FI39;
+    input FI4;
+    input FI40;
+    input FI41;
+    input FI42;
+    input FI43;
+    input FI44;
+    input FI45;
+    input FI46;
+    input FI47;
+    input FI48;
+    input FI49;
+    input FI5;
+    input FI50;
+    input FI51;
+    input FI52;
+    input FI53;
+    input FI54;
+    input FI55;
+    input FI56;
+    input FI57;
+    input FI58;
+    input FI59;
+    input FI6;
+    input FI60;
+    input FI61;
+    input FI62;
+    input FI63;
+    input FI64;
+    input FI65;
+    input FI66;
+    input FI67;
+    input FI68;
+    input FI69;
+    input FI7;
+    input FI70;
+    input FI71;
+    input FI72;
+    input FI73;
+    input FI74;
+    input FI75;
+    input FI76;
+    input FI77;
+    input FI78;
+    input FI79;
+    input FI8;
+    input FI80;
+    input FI81;
+    input FI82;
+    input FI83;
+    input FI84;
+    input FI85;
+    input FI86;
+    input FI87;
+    input FI88;
+    input FI89;
+    input FI9;
+    input FI90;
+    input FI91;
+    input FI92;
+    input FI93;
+    input FI94;
+    input FI95;
+    input FI96;
+    input FI97;
+    input FI98;
+    input FI99;
+    output FO1;
+    output FO10;
+    output FO100;
+    output FO101;
+    output FO102;
+    output FO103;
+    output FO104;
+    output FO105;
+    output FO106;
+    output FO107;
+    output FO108;
+    output FO109;
+    output FO11;
+    output FO110;
+    output FO111;
+    output FO112;
+    output FO113;
+    output FO114;
+    output FO115;
+    output FO116;
+    output FO117;
+    output FO118;
+    output FO119;
+    output FO12;
+    output FO120;
+    output FO121;
+    output FO122;
+    output FO123;
+    output FO124;
+    output FO125;
+    output FO126;
+    output FO127;
+    output FO128;
+    output FO129;
+    output FO13;
+    output FO130;
+    output FO131;
+    output FO132;
+    output FO133;
+    output FO134;
+    output FO135;
+    output FO136;
+    output FO137;
+    output FO138;
+    output FO139;
+    output FO14;
+    output FO140;
+    output FO141;
+    output FO142;
+    output FO143;
+    output FO144;
+    output FO145;
+    output FO146;
+    output FO147;
+    output FO148;
+    output FO149;
+    output FO15;
+    output FO150;
+    output FO151;
+    output FO152;
+    output FO153;
+    output FO154;
+    output FO155;
+    output FO156;
+    output FO157;
+    output FO158;
+    output FO159;
+    output FO16;
+    output FO160;
+    output FO161;
+    output FO162;
+    output FO163;
+    output FO164;
+    output FO165;
+    output FO166;
+    output FO167;
+    output FO168;
+    output FO169;
+    output FO17;
+    output FO170;
+    output FO171;
+    output FO172;
+    output FO173;
+    output FO174;
+    output FO175;
+    output FO176;
+    output FO177;
+    output FO178;
+    output FO179;
+    output FO18;
+    output FO180;
+    output FO181;
+    output FO182;
+    output FO183;
+    output FO184;
+    output FO185;
+    output FO186;
+    output FO187;
+    output FO188;
+    output FO189;
+    output FO19;
+    output FO190;
+    output FO191;
+    output FO192;
+    output FO2;
+    output FO20;
+    output FO21;
+    output FO22;
+    output FO23;
+    output FO24;
+    output FO25;
+    output FO26;
+    output FO27;
+    output FO28;
+    output FO29;
+    output FO3;
+    output FO30;
+    output FO31;
+    output FO32;
+    output FO33;
+    output FO34;
+    output FO35;
+    output FO36;
+    output FO37;
+    output FO38;
+    output FO39;
+    output FO4;
+    output FO40;
+    output FO41;
+    output FO42;
+    output FO43;
+    output FO44;
+    output FO45;
+    output FO46;
+    output FO47;
+    output FO48;
+    output FO49;
+    output FO5;
+    output FO50;
+    output FO51;
+    output FO52;
+    output FO53;
+    output FO54;
+    output FO55;
+    output FO56;
+    output FO57;
+    output FO58;
+    output FO59;
+    output FO6;
+    output FO60;
+    output FO61;
+    output FO62;
+    output FO63;
+    output FO64;
+    output FO65;
+    output FO66;
+    output FO67;
+    output FO68;
+    output FO69;
+    output FO7;
+    output FO70;
+    output FO71;
+    output FO72;
+    output FO73;
+    output FO74;
+    output FO75;
+    output FO76;
+    output FO77;
+    output FO78;
+    output FO79;
+    output FO8;
+    output FO80;
+    output FO81;
+    output FO82;
+    output FO83;
+    output FO84;
+    output FO85;
+    output FO86;
+    output FO87;
+    output FO88;
+    output FO89;
+    output FO9;
+    output FO90;
+    output FO91;
+    output FO92;
+    output FO93;
+    output FO94;
+    output FO95;
+    output FO96;
+    output FO97;
+    output FO98;
+    output FO99;
+    parameter inputBypass = 24'b000000000000000000000000;
+    parameter inputClk = 2'b00;
+    parameter inputContext = "";
+    parameter outputBypass = 24'b000000000000000000000000;
+    parameter outputClk = 2'b00;
+    parameter outputContext = "";
+endmodule
+
+(* blackbox *)
+module NX_RB_WRAP(EI_CK, EO_CK, CK, EO, EI, FI, FO);
+    input [3:0] CK;
+    input [191:0] EI;
+    output EI_CK;
+    output [191:0] EO;
+    output EO_CK;
+    input [191:0] FI;
+    output [191:0] FO;
+    parameter inputBypass = 24'b000000000000000000000000;
+    parameter inputClk = 2'b00;
+    parameter inputContext = "";
+    parameter outputBypass = 24'b000000000000000000000000;
+    parameter outputClk = 2'b00;
+    parameter outputContext = "";
+endmodule
+
+(* blackbox *)
+module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1
+, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6
+, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);
+    output COR;
+    output ERR;
+    input I1;
+    input I10;
+    input I11;
+    input I12;
+    input I13;
+    input I14;
+    input I15;
+    input I16;
+    input I2;
+    input I3;
+    input I4;
+    input I5;
+    input I6;
+    input I7;
+    input I8;
+    input I9;
+    output O1;
+    output O10;
+    output O11;
+    output O12;
+    output O13;
+    output O14;
+    output O15;
+    output O16;
+    output O2;
+    output O3;
+    output O4;
+    output O5;
+    output O6;
+    output O7;
+    output O8;
+    output O9;
+    input RA1;
+    input RA2;
+    input RA3;
+    input RA4;
+    input RA5;
+    input RA6;
+    input RCK;
+    input RE;
+    input WA1;
+    input WA2;
+    input WA3;
+    input WA4;
+    input WA5;
+    input WA6;
+    input WCK;
+    input WE;
+    parameter addr_mask = 5'b00000;
+    parameter mem_ctxt = "";
+    parameter rck_edge = 1'b0;
+    parameter wck_edge = 1'b0;
+    parameter we_mask = 1'b0;
+    parameter wea_mask = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_RFBDP_U_WRAP(WCK, WE, WEA, I, O, RA, WA);
+    input [17:0] I;
+    output [17:0] O;
+    input [4:0] RA;
+    input [4:0] WA;
+    input WCK;
+    input WE;
+    input WEA;
+    parameter mem_ctxt = "";
+    parameter wck_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_RFBSP_U_WRAP(WCK, WE, WEA, I, O, WA);
+    input [17:0] I;
+    output [17:0] O;
+    input [4:0] WA;
+    input WCK;
+    input WE;
+    input WEA;
+    parameter mem_ctxt = "";
+    parameter wck_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_RFB_L(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1
+, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6
+, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);
+    output COR;
+    output ERR;
+    input I1;
+    input I10;
+    input I11;
+    input I12;
+    input I13;
+    input I14;
+    input I15;
+    input I16;
+    input I2;
+    input I3;
+    input I4;
+    input I5;
+    input I6;
+    input I7;
+    input I8;
+    input I9;
+    output O1;
+    output O10;
+    output O11;
+    output O12;
+    output O13;
+    output O14;
+    output O15;
+    output O16;
+    output O2;
+    output O3;
+    output O4;
+    output O5;
+    output O6;
+    output O7;
+    output O8;
+    output O9;
+    input RA1;
+    input RA2;
+    input RA3;
+    input RA4;
+    input RA5;
+    input RA6;
+    input RCK;
+    input RE;
+    input WA1;
+    input WA2;
+    input WA3;
+    input WA4;
+    input WA5;
+    input WA6;
+    input WCK;
+    input WE;
+    parameter mem_ctxt = "";
+    parameter mode = 0;
+    parameter rck_edge = 1'b0;
+    parameter wck_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_RFB_L_WRAP(RCK, WCK, COR, ERR, RE, WE, I, O, RA, WA);
+    output COR;
+    output ERR;
+    input [15:0] I;
+    output [15:0] O;
+    input [5:0] RA;
+    input RCK;
+    input RE;
+    input [5:0] WA;
+    input WCK;
+    input WE;
+    parameter mem_ctxt = "";
+    parameter mode = 0;
+    parameter rck_edge = 1'b0;
+    parameter wck_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_RFB_M(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1
+, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6
+, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);
+    output COR;
+    output ERR;
+    input I1;
+    input I10;
+    input I11;
+    input I12;
+    input I13;
+    input I14;
+    input I15;
+    input I16;
+    input I2;
+    input I3;
+    input I4;
+    input I5;
+    input I6;
+    input I7;
+    input I8;
+    input I9;
+    output O1;
+    output O10;
+    output O11;
+    output O12;
+    output O13;
+    output O14;
+    output O15;
+    output O16;
+    output O2;
+    output O3;
+    output O4;
+    output O5;
+    output O6;
+    output O7;
+    output O8;
+    output O9;
+    input RA1;
+    input RA2;
+    input RA3;
+    input RA4;
+    input RA5;
+    input RA6;
+    input RCK;
+    input RE;
+    input WA1;
+    input WA2;
+    input WA3;
+    input WA4;
+    input WA5;
+    input WA6;
+    input WCK;
+    input WE;
+    parameter mem_ctxt = "";
+    parameter rck_edge = 1'b0;
+    parameter wck_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20
+, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2, O3, O4, O5
+, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23, O24, O25, O26
+, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, WA1
+, WA2, WA3, WA4, WA5, WA6, WE, WEA);
+    input I1;
+    input I10;
+    input I11;
+    input I12;
+    input I13;
+    input I14;
+    input I15;
+    input I16;
+    input I17;
+    input I18;
+    input I19;
+    input I2;
+    input I20;
+    input I21;
+    input I22;
+    input I23;
+    input I24;
+    input I25;
+    input I26;
+    input I27;
+    input I28;
+    input I29;
+    input I3;
+    input I30;
+    input I31;
+    input I32;
+    input I33;
+    input I34;
+    input I35;
+    input I36;
+    input I4;
+    input I5;
+    input I6;
+    input I7;
+    input I8;
+    input I9;
+    output O1;
+    output O10;
+    output O11;
+    output O12;
+    output O13;
+    output O14;
+    output O15;
+    output O16;
+    output O17;
+    output O18;
+    output O19;
+    output O2;
+    output O20;
+    output O21;
+    output O22;
+    output O23;
+    output O24;
+    output O25;
+    output O26;
+    output O27;
+    output O28;
+    output O29;
+    output O3;
+    output O30;
+    output O31;
+    output O32;
+    output O33;
+    output O34;
+    output O35;
+    output O36;
+    output O4;
+    output O5;
+    output O6;
+    output O7;
+    output O8;
+    output O9;
+    input RA1;
+    input RA10;
+    input RA2;
+    input RA3;
+    input RA4;
+    input RA5;
+    input RA6;
+    input RA7;
+    input RA8;
+    input RA9;
+    input WA1;
+    input WA2;
+    input WA3;
+    input WA4;
+    input WA5;
+    input WA6;
+    input WCK;
+    input WE;
+    input WEA;
+    parameter mem_ctxt = "";
+    parameter mode = 0;
+    parameter wck_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_RFB_WRAP(RCK, WCK, COR, ERR, RE, WE, I, O, RA, WA);
+    output COR;
+    output ERR;
+    input [15:0] I;
+    output [15:0] O;
+    input [5:0] RA;
+    input RCK;
+    input RE;
+    input [5:0] WA;
+    input WCK;
+    input WE;
+    parameter mem_ctxt = "";
+    parameter rck_edge = 1'b0;
+    parameter wck_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_SER(FCK, SCK, R, IO, DCK, DRL, I, DS, DRA, DRI, DRO, DID);
+    input DCK;
+    output [5:0] DID;
+    input [5:0] DRA;
+    input [5:0] DRI;
+    input DRL;
+    output [5:0] DRO;
+    input [1:0] DS;
+    input FCK;
+    input [4:0] I;
+    output IO;
+    input R;
+    input SCK;
+    parameter data_size = 5;
+    parameter differential = "";
+    parameter drive = "";
+    parameter location = "";
+    parameter locked = 1'b0;
+    parameter outputCapacity = "";
+    parameter outputDelayLine = "";
+    parameter slewRate = "";
+    parameter spath_dynamic = 1'b0;
+    parameter standard = "";
+endmodule
+
+(* blackbox *)
+module NX_SERDES(FCK, SCK, RTX, RRX, CI, CCK, CL, CR, IO, DCK, DRL, DIG, FZ, FLD, FLG, I, O, DS, DRA, DRI, DRO
+, DID);
+    input CCK;
+    input CI;
+    input CL;
+    input CR;
+    input DCK;
+    output [5:0] DID;
+    input DIG;
+    input [5:0] DRA;
+    input [5:0] DRI;
+    input DRL;
+    output [5:0] DRO;
+    input [1:0] DS;
+    input FCK;
+    output FLD;
+    output FLG;
+    input FZ;
+    input [4:0] I;
+    inout IO;
+    output [4:0] O;
+    input RRX;
+    input RTX;
+    input SCK;
+    parameter cpath_registered = 1'b0;
+    parameter data_size = 5;
+    parameter differential = "";
+    parameter dpath_dynamic = 1'b0;
+    parameter drive = "";
+    parameter inputDelayLine = "";
+    parameter inputSignalSlope = "";
+    parameter location = "";
+    parameter locked = 1'b0;
+    parameter outputCapacity = "";
+    parameter outputDelayLine = "";
+    parameter slewRate = "";
+    parameter spath_dynamic = 1'b0;
+    parameter standard = "";
+    parameter termination = "";
+    parameter terminationReference = "";
+    parameter turbo = "";
+    parameter weakTermination = "";
+endmodule
+
+(* blackbox *)
+module NX_SERVICE_IF_U(fabric_otp_user_clk_i, fabric_otp_user_bistmode_i, fabric_otp_user_disturbcheck_i, fabric_otp_user_eccbypass_i, fabric_otp_user_pdn_i, fabric_otp_user_prog_i, fabric_otp_user_rbact1_i, fabric_otp_user_rbact2_i, fabric_otp_user_read_i, fabric_otp_user_redbypass_i, fabric_otp_user_suppadd_i, fabric_otp_user_tm_i, fabric_otp_user_tst_scanenable_i, fabric_otp_user_wordlock_i, fabric_otp_user_add_i1, fabric_otp_user_add_i2, fabric_otp_user_add_i3, fabric_otp_user_add_i4, fabric_otp_user_add_i5, fabric_otp_user_add_i6, fabric_otp_user_add_i7
+, fabric_otp_user_clock_frequency_range_i, fabric_otp_user_din_i1, fabric_otp_user_din_i2, fabric_otp_user_din_i3, fabric_otp_user_din_i4, fabric_otp_user_din_i5, fabric_otp_user_din_i6, fabric_otp_user_din_i7, fabric_otp_user_din_i8, fabric_otp_user_din_i9, fabric_otp_user_din_i10, fabric_otp_user_din_i11, fabric_otp_user_din_i12, fabric_otp_user_din_i13, fabric_otp_user_din_i14, fabric_otp_user_din_i15, fabric_otp_user_din_i16, fabric_otp_user_din_i17, fabric_otp_user_din_i18, fabric_otp_user_din_i19, fabric_otp_user_din_i20
+, fabric_otp_user_din_i21, fabric_otp_user_din_i22, fabric_otp_user_din_i23, fabric_otp_user_din_i24, fabric_otp_user_din_i25, fabric_otp_user_din_i26, fabric_otp_user_din_i27, fabric_otp_user_din_i28, fabric_otp_user_din_i29, fabric_otp_user_din_i30, fabric_otp_user_din_i31, fabric_otp_user_din_i32, fabric_otp_user_din_i33, fabric_otp_user_din_i34, fabric_otp_user_din_i35, fabric_otp_user_din_i36, fabric_otp_user_din_i37, fabric_otp_user_din_i38, fabric_otp_user_din_i39, fabric_otp_user_prgwidth_i1, fabric_otp_user_prgwidth_i2
+, fabric_otp_user_prgwidth_i3, fabric_otp_user_tst_scanin_i1, fabric_otp_user_tst_scanin_i2, fabric_otp_user_tst_scanin_i3, fabric_otp_user_tst_scanin_i4, fabric_otp_user_tst_scanin_i5, fabric_otp_user_ack_o, fabric_otp_user_bbad_o, fabric_otp_user_bend1_o, fabric_otp_user_bend2_o, fabric_otp_user_calibrated_o, fabric_otp_user_ded_o, fabric_otp_user_disturbed_o, fabric_otp_user_locked_o, fabric_otp_user_progfail_o, fabric_otp_user_pwok_o, fabric_otp_user_sec_o, fabric_otp_user_bist1fail_o1, fabric_otp_user_bist1fail_o2, fabric_otp_user_bist1fail_o3, fabric_otp_user_bist1fail_o4
+, fabric_otp_user_bist1fail_o5, fabric_otp_user_bist1fail_o6, fabric_otp_user_bist1fail_o7, fabric_otp_user_bist1fail_o8, fabric_otp_user_bist2fail_o1, fabric_otp_user_bist2fail_o2, fabric_otp_user_bist2fail_o3, fabric_otp_user_bist2fail_o4, fabric_otp_user_bist2fail_o5, fabric_otp_user_bist2fail_o6, fabric_otp_user_bist2fail_o7, fabric_otp_user_dout_o1, fabric_otp_user_dout_o2, fabric_otp_user_dout_o3, fabric_otp_user_dout_o4, fabric_otp_user_dout_o5, fabric_otp_user_dout_o6, fabric_otp_user_dout_o7, fabric_otp_user_dout_o8, fabric_otp_user_dout_o9, fabric_otp_user_dout_o10
+, fabric_otp_user_dout_o11, fabric_otp_user_dout_o12, fabric_otp_user_dout_o13, fabric_otp_user_dout_o14, fabric_otp_user_dout_o15, fabric_otp_user_dout_o16, fabric_otp_user_dout_o17, fabric_otp_user_dout_o18, fabric_otp_user_dout_o19, fabric_otp_user_dout_o20, fabric_otp_user_dout_o21, fabric_otp_user_dout_o22, fabric_otp_user_dout_o23, fabric_otp_user_dout_o24, fabric_otp_user_dout_o25, fabric_otp_user_dout_o26, fabric_otp_user_dout_o27, fabric_otp_user_dout_o28, fabric_otp_user_dout_o29, fabric_otp_user_dout_o30, fabric_otp_user_dout_o31
+, fabric_otp_user_dout_o32, fabric_otp_user_dout_o33, fabric_otp_user_dout_o34, fabric_otp_user_dout_o35, fabric_otp_user_dout_o36, fabric_otp_user_dout_o37, fabric_otp_user_dout_o38, fabric_otp_user_dout_o39, fabric_otp_user_dout_o40, fabric_otp_user_dout_o41, fabric_otp_user_flagstate_o1, fabric_otp_user_flagstate_o2, fabric_otp_user_flagstate_o3, fabric_otp_user_flagstate_o4, fabric_otp_user_startword_o1, fabric_otp_user_startword_o2, fabric_otp_user_startword_o3, fabric_otp_user_startword_o4, fabric_otp_user_startword_o5, fabric_otp_user_startword_o6, fabric_otp_user_startword_o7
+, fabric_otp_user_startword_o8, fabric_otp_user_startword_o9, fabric_otp_user_startword_o10, fabric_otp_user_startword_o11, fabric_otp_user_startword_o12, fabric_otp_user_startword_o13, fabric_otp_user_startword_o14, fabric_otp_user_startword_o15, fabric_otp_user_startword_o16, fabric_otp_user_tst_scanout_o1, fabric_otp_user_tst_scanout_o2, fabric_otp_user_tst_scanout_o3, fabric_otp_user_tst_scanout_o4, fabric_otp_user_tst_scanout_o5, fabric_otp_user_wlromout_o1, fabric_otp_user_wlromout_o2, fabric_otp_user_wlromout_o3, fabric_otp_user_wlromout_o4, fabric_otp_user_wlromout_o5, fabric_otp_user_wlromout_o6, fabric_otp_user_wlromout_o7
+, fabric_otp_user_wlromout_o8, fabric_otp_user_wlromout_o9, fabric_otp_user_wlromout_o10, fabric_clk_bsm_o, fabric_clk_otp_mux_i, fabric_clk_otp_o, fabric_clk_user0_o, fabric_clk_user1_o, fabric_io_in_i1, fabric_io_in_i2, fabric_io_in_i3, fabric_io_in_i4, fabric_io_in_i5, fabric_io_in_i6, fabric_io_in_i7, fabric_io_in_i8, fabric_io_in_i9, fabric_io_in_i10, fabric_io_in_i11, fabric_io_in_i12, fabric_io_in_i13
+, fabric_io_in_i14, fabric_io_in_i15, fabric_io_in_i16, fabric_io_in_i17, fabric_io_in_i18, fabric_io_in_i19, fabric_io_in_i20, fabric_io_in_i21, fabric_io_in_i22, fabric_io_in_i23, fabric_io_in_i24, fabric_io_in_i25, fabric_io_in_i26, fabric_io_in_i27, fabric_io_in_i28, fabric_io_in_i29, fabric_io_in_i30, fabric_io_in_i31, fabric_io_in_i32, fabric_io_in_i33, fabric_io_in_i34
+, fabric_io_in_i35, fabric_io_oe_i1, fabric_io_oe_i2, fabric_io_oe_i3, fabric_io_oe_i4, fabric_io_oe_i5, fabric_io_oe_i6, fabric_io_oe_i7, fabric_io_oe_i8, fabric_io_oe_i9, fabric_io_oe_i10, fabric_io_oe_i11, fabric_io_oe_i12, fabric_io_oe_i13, fabric_io_oe_i14, fabric_io_oe_i15, fabric_io_oe_i16, fabric_io_oe_i17, fabric_io_oe_i18, fabric_io_oe_i19, fabric_io_oe_i20
+, fabric_io_oe_i21, fabric_io_oe_i22, fabric_io_oe_i23, fabric_io_oe_i24, fabric_io_oe_i25, fabric_io_oe_i26, fabric_io_oe_i27, fabric_io_oe_i28, fabric_io_oe_i29, fabric_io_oe_i30, fabric_io_oe_i31, fabric_io_oe_i32, fabric_io_oe_i33, fabric_io_oe_i34, fabric_io_oe_i35, fabric_io_out_o1, fabric_io_out_o2, fabric_io_out_o3, fabric_io_out_o4, fabric_io_out_o5, fabric_io_out_o6
+, fabric_io_out_o7, fabric_io_out_o8, fabric_io_out_o9, fabric_io_out_o10, fabric_io_out_o11, fabric_io_out_o12, fabric_io_out_o13, fabric_io_out_o14, fabric_io_out_o15, fabric_io_out_o16, fabric_io_out_o17, fabric_io_out_o18, fabric_io_out_o19, fabric_io_out_o20, fabric_io_out_o21, fabric_io_out_o22, fabric_io_out_o23, fabric_io_out_o24, fabric_io_out_o25, fabric_io_out_o26, fabric_io_out_o27
+, fabric_io_out_o28, fabric_io_out_o29, fabric_io_out_o30, fabric_io_out_o31, fabric_io_out_o32, fabric_io_out_o33, fabric_io_out_o34, fabric_io_out_o35, fabric_user_clk_i, fabric_user_data_i1, fabric_user_data_i2, fabric_user_data_i3, fabric_user_data_i4, fabric_user_data_i5, fabric_user_data_i6, fabric_user_data_i7, fabric_user_data_i8, fabric_user_data_i9, fabric_user_data_i10, fabric_user_data_i11, fabric_user_data_i12
+, fabric_user_data_i13, fabric_user_data_i14, fabric_user_data_i15, fabric_user_data_i16, fabric_user_data_i17, fabric_user_data_i18, fabric_user_data_i19, fabric_user_data_i20, fabric_user_data_i21, fabric_user_data_i22, fabric_user_data_i23, fabric_user_data_i24, fabric_user_data_i25, fabric_user_data_i26, fabric_user_data_i27, fabric_user_data_i28, fabric_user_data_i29, fabric_user_data_i30, fabric_user_data_i31, fabric_user_data_i32, fabric_user_data_o1
+, fabric_user_data_o2, fabric_user_data_o3, fabric_user_data_o4, fabric_user_data_o5, fabric_user_data_o6, fabric_user_data_o7, fabric_user_data_o8, fabric_user_data_o9, fabric_user_data_o10, fabric_user_data_o11, fabric_user_data_o12, fabric_user_data_o13, fabric_user_data_o14, fabric_user_data_o15, fabric_user_data_o16, fabric_user_data_o17, fabric_user_data_o18, fabric_user_data_o19, fabric_user_data_o20, fabric_user_data_o21, fabric_user_data_o22
+, fabric_user_data_o23, fabric_user_data_o24, fabric_user_data_o25, fabric_user_data_o26, fabric_user_data_o27, fabric_user_data_o28, fabric_user_data_o29, fabric_user_data_o30, fabric_user_data_o31, fabric_user_data_o32, fabric_user_write_cycle_o, fabric_user_read_cycle_o, fabric_cfg_fabric_user_flag_o, fabric_cfg_fabric_user_enable_o, fabric_parusr_clk_i, fabric_parusr_enable_i, fabric_parusr_cs_i, fabric_parusr_type_i1, fabric_parusr_type_i2, fabric_parusr_data_i1, fabric_parusr_data_i2
+, fabric_parusr_data_i3, fabric_parusr_data_i4, fabric_parusr_data_i5, fabric_parusr_data_i6, fabric_parusr_data_i7, fabric_parusr_data_i8, fabric_parusr_data_i9, fabric_parusr_data_i10, fabric_parusr_data_i11, fabric_parusr_data_i12, fabric_parusr_data_i13, fabric_parusr_data_i14, fabric_parusr_data_i15, fabric_parusr_data_i16, fabric_parusr_data_o1, fabric_parusr_data_o2, fabric_parusr_data_o3, fabric_parusr_data_o4, fabric_parusr_data_o5, fabric_parusr_data_o6, fabric_parusr_data_o7
+, fabric_parusr_data_o8, fabric_parusr_data_o9, fabric_parusr_data_o10, fabric_parusr_data_o11, fabric_parusr_data_o12, fabric_parusr_data_o13, fabric_parusr_data_o14, fabric_parusr_data_o15, fabric_parusr_data_o16, fabric_parusr_data_val_o, fabric_jtag_tck_o, fabric_jtag_trst_n_o, fabric_jtag_tms_o, fabric_jtag_tdi_o, fabric_jtag_usr1_o, fabric_jtag_usr2_o, fabric_jtag_tdo_usr1_i, fabric_jtag_tdo_usr2_i, fabric_status_cold_start_o, fabric_flag_trigger0_o, fabric_flag_trigger1_o
+, fabric_flag_ready_TMR_o1, fabric_flag_ready_TMR_o2, fabric_flag_ready_TMR_o3, fabric_enable_TMR_i1, fabric_enable_TMR_i2, fabric_enable_TMR_i3, fabric_lowskew_i1, fabric_lowskew_i2, fabric_lowskew_i3, fabric_lowskew_i4, fabric_lowskew_i5, fabric_lowskew_i6, fabric_lowskew_i7, fabric_lowskew_i8, fabric_lowskew_i9, fabric_lowskew_i10, fabric_lowskew_i11, fabric_lowskew_i12, fabric_lowskew_i13, fabric_lowskew_i14, fabric_lowskew_i15
+, fabric_lowskew_i16, fabric_lowskew_i17, fabric_lowskew_i18, fabric_lowskew_i19, fabric_lowskew_i20, fabric_lowskew_i21, fabric_lowskew_i22, fabric_lowskew_i23, fabric_lowskew_i24, fabric_lowskew_i25, fabric_lowskew_i26, fabric_lowskew_i27, fabric_lowskew_i28, fabric_lowskew_i29, fabric_lowskew_i30, fabric_lowskew_i31, fabric_lowskew_i32, fabric_lowskew_i33, fabric_lowskew_i34, fabric_lowskew_i35, fabric_lowskew_i36
+, fabric_lowskew_i37, fabric_lowskew_i38, fabric_lowskew_i39, fabric_lowskew_i40, fabric_lowskew_o1, fabric_lowskew_o2, fabric_lowskew_o3, fabric_lowskew_o4, fabric_lowskew_o5, fabric_lowskew_o6, fabric_spare_i1, fabric_spare_i2, fabric_spare_i3, fabric_spare_i4, fabric_spare_i5, fabric_spare_i6, fabric_spare_i7, fabric_spare_i8, fabric_spare_i9, fabric_spare_i10, fabric_spare_i11
+, fabric_spare_i12, fabric_spare_i13, fabric_spare_i14, fabric_spare_i15, fabric_spare_i16, fabric_spare_i17, fabric_spare_i18, fabric_spare_i19, fabric_spare_i20, fabric_spare_i21, fabric_spare_i22, fabric_spare_i23, fabric_spare_i24, fabric_spare_i25, fabric_spare_i26, fabric_spare_i27, fabric_spare_i28, fabric_spare_i29, fabric_spare_i30, fabric_spare_i31, fabric_spare_i32
+, fabric_spare_i33, fabric_spare_i34, fabric_spare_i35, fabric_spare_i36, fabric_spare_i37, fabric_spare_i38, fabric_spare_i39, fabric_spare_i40, fabric_spare_i41, fabric_spare_i42, fabric_spare_i43, fabric_spare_i44, fabric_spare_i45, fabric_spare_i46, fabric_spare_i47, fabric_spare_i48, fabric_spare_i49, fabric_spare_i50, fabric_spare_i51, fabric_spare_i52, fabric_spare_i53
+, fabric_spare_i54, fabric_spare_i55, fabric_spare_i56, fabric_spare_i57, fabric_spare_i58, fabric_spare_i59, fabric_spare_i60, fabric_spare_i61, fabric_spare_i62, fabric_spare_i63, fabric_spare_i64, fabric_spare_i65, fabric_spare_i66, fabric_spare_i67, fabric_spare_i68, fabric_spare_i69, fabric_spare_i70, fabric_spare_i71, fabric_spare_i72, fabric_spare_i73, fabric_spare_i74
+, fabric_spare_i75, fabric_spare_i76, fabric_spare_i77, fabric_spare_i78, fabric_spare_i79, fabric_spare_i80, fabric_spare_i81, fabric_spare_i82, fabric_spare_i83, fabric_spare_i84, fabric_spare_i85, fabric_spare_i86, fabric_spare_i87, fabric_spare_i88, fabric_spare_i89, fabric_spare_i90, fabric_spare_i91, fabric_spare_i92, fabric_spare_i93, fabric_spare_i94, fabric_spare_i95
+, fabric_spare_i96, fabric_spare_i97, fabric_spare_i98, fabric_spare_i99, fabric_spare_i100, fabric_spare_i101, fabric_spare_i102, fabric_spare_i103, fabric_spare_i104, fabric_spare_i105, fabric_spare_i106, fabric_spare_i107, fabric_spare_i108, fabric_spare_i109, fabric_spare_i110, fabric_spare_i111, fabric_spare_i112, fabric_spare_i113, fabric_spare_i114, fabric_spare_i115, fabric_spare_i116
+, fabric_spare_i117, fabric_spare_i118, fabric_spare_i119, fabric_spare_i120, fabric_spare_i121, fabric_spare_i122, fabric_spare_i123, fabric_spare_i124, fabric_spare_i125, fabric_spare_i126, fabric_spare_i127, fabric_spare_i128, fabric_spare_o1, fabric_spare_o2, fabric_spare_o3, fabric_spare_o4, fabric_spare_o5, fabric_spare_o6, fabric_spare_o7, fabric_spare_o8, fabric_spare_o9
+, fabric_spare_o10, fabric_spare_o11, fabric_spare_o12, fabric_spare_o13, fabric_spare_o14, fabric_spare_o15, fabric_spare_o16, fabric_spare_o17, fabric_spare_o18, fabric_spare_o19, fabric_spare_o20, fabric_spare_o21, fabric_spare_o22, fabric_spare_o23, fabric_spare_o24, fabric_spare_o25, fabric_spare_o26, fabric_spare_o27, fabric_spare_o28, fabric_spare_o29, fabric_spare_o30
+, fabric_spare_o31, fabric_spare_o32, fabric_spare_o33, fabric_spare_o34, fabric_spare_o35, fabric_spare_o36, fabric_spare_o37, fabric_spare_o38, fabric_spare_o39, fabric_spare_o40, fabric_spare_o41, fabric_spare_o42, fabric_spare_o43, fabric_spare_o44, fabric_spare_o45, fabric_spare_o46, fabric_spare_o47, fabric_spare_o48, fabric_spare_o49, fabric_spare_o50, fabric_spare_o51
+, fabric_spare_o52, fabric_spare_o53, fabric_spare_o54, fabric_spare_o55, fabric_spare_o56, fabric_spare_o57, fabric_spare_o58, fabric_spare_o59, fabric_spare_o60, fabric_spare_o61, fabric_spare_o62, fabric_spare_o63, fabric_spare_o64, fabric_spare_o65, fabric_spare_o66, fabric_spare_o67, fabric_spare_o68, fabric_spare_o69, fabric_spare_o70, fabric_spare_o71, fabric_spare_o72
+, fabric_spare_o73, fabric_spare_o74, fabric_spare_o75, fabric_spare_o76, fabric_spare_o77, fabric_spare_o78, fabric_spare_o79, fabric_spare_o80, fabric_spare_o81, fabric_spare_o82, fabric_spare_o83, fabric_spare_o84, fabric_spare_o85, fabric_spare_o86, fabric_spare_o87, fabric_spare_o88, fabric_spare_o89, fabric_spare_o90, fabric_spare_o91, fabric_spare_o92, fabric_spare_o93
+, fabric_spare_o94, fabric_spare_o95, fabric_spare_o96, fabric_spare_o97, fabric_spare_o98, fabric_spare_o99, fabric_spare_o100, fabric_spare_o101, fabric_spare_o102, fabric_spare_o103, fabric_spare_o104, fabric_spare_o105, fabric_spare_o106, fabric_spare_o107, fabric_spare_o108, fabric_spare_o109, fabric_spare_o110, fabric_spare_o111, fabric_spare_o112, fabric_spare_o113, fabric_spare_o114
+, fabric_spare_o115, fabric_spare_o116, fabric_spare_o117, fabric_spare_o118, fabric_spare_o119, fabric_spare_o120, fabric_spare_o121, fabric_spare_o122, fabric_spare_o123, fabric_spare_o124, fabric_spare_o125, fabric_spare_o126, fabric_spare_o127, fabric_spare_o128, fabric_thsens_clk_i, fabric_thsens_arst_tmr_n_i1, fabric_thsens_arst_tmr_n_i2, fabric_thsens_arst_tmr_n_i3, fabric_thsens_fm_enable_i, fabric_thsens_fm_mode_w_i1, fabric_thsens_fm_mode_w_i2
+, fabric_thsens_fm_mode_w_i3, fabric_thsens_fm_mode_w_i4, fabric_thsens_fm_mode_w_i5, fabric_thsens_fm_mode_w_i6, fabric_thsens_fm_mode_w_i7, fabric_thsens_fm_mode_w_i8, fabric_thsens_fm_mode_w_i9, fabric_thsens_fm_mode_w_i10, fabric_thsens_fm_mode_w_i11, fabric_thsens_fm_mode_w_i12, fabric_thsens_fm_mode_w_i13, fabric_thsens_fm_mode_w_i14, fabric_thsens_fm_mode_w_i15, fabric_thsens_fm_mode_w_i16, fabric_thsens_fm_mode_w_i17, fabric_thsens_fm_mode_w_i18, fabric_thsens_fm_mode_w_i19, fabric_thsens_fm_mode_w_i20, fabric_thsens_fm_mode_w_i21, fabric_thsens_fm_mode_w_i22, fabric_thsens_fm_mode_w_i23
+, fabric_thsens_fm_mode_w_i24, fabric_thsens_fm_mode_w_i25, fabric_thsens_fm_mode_w_i26, fabric_thsens_fm_mode_w_i27, fabric_thsens_fm_mode_w_i28, fabric_thsens_fm_mode_w_i29, fabric_thsens_fm_mode_w_i30, fabric_thsens_fm_mode_w_i31, fabric_thsens_fm_mode_w_i32, fabric_thsens_fm_mode_wen_i, fabric_thsens_fm_config_w_i1, fabric_thsens_fm_config_w_i2, fabric_thsens_fm_config_w_i3, fabric_thsens_fm_config_w_i4, fabric_thsens_fm_config_w_i5, fabric_thsens_fm_config_w_i6, fabric_thsens_fm_config_w_i7, fabric_thsens_fm_config_w_i8, fabric_thsens_fm_config_w_i9, fabric_thsens_fm_config_w_i10, fabric_thsens_fm_config_w_i11
+, fabric_thsens_fm_config_w_i12, fabric_thsens_fm_config_w_i13, fabric_thsens_fm_config_w_i14, fabric_thsens_fm_config_w_i15, fabric_thsens_fm_config_w_i16, fabric_thsens_fm_config_w_i17, fabric_thsens_fm_config_w_i18, fabric_thsens_fm_config_w_i19, fabric_thsens_fm_config_w_i20, fabric_thsens_fm_config_w_i21, fabric_thsens_fm_config_w_i22, fabric_thsens_fm_config_w_i23, fabric_thsens_fm_config_w_i24, fabric_thsens_fm_config_w_i25, fabric_thsens_fm_config_w_i26, fabric_thsens_fm_config_w_i27, fabric_thsens_fm_config_wen_i, fabric_thsens_fm_data_o1, fabric_thsens_fm_data_o2, fabric_thsens_fm_data_o3, fabric_thsens_fm_data_o4
+, fabric_thsens_fm_data_o5, fabric_thsens_fm_data_o6, fabric_thsens_fm_data_o7, fabric_thsens_fm_data_o8, fabric_thsens_fm_data_o9, fabric_thsens_fm_data_o10, fabric_thsens_fm_data_o11, fabric_thsens_fm_data_o12, fabric_thsens_fm_data_o13, fabric_thsens_fm_data_o14, fabric_thsens_fm_valid_o, fabric_thsens_fm_overflow_o, fabric_thsens_fm_mode_r_o1, fabric_thsens_fm_mode_r_o2, fabric_thsens_fm_mode_r_o3, fabric_thsens_fm_mode_r_o4, fabric_thsens_fm_mode_r_o5, fabric_thsens_fm_mode_r_o6, fabric_thsens_fm_mode_r_o7, fabric_thsens_fm_mode_r_o8, fabric_thsens_fm_mode_r_o9
+, fabric_thsens_fm_mode_r_o10, fabric_thsens_fm_mode_r_o11, fabric_thsens_fm_mode_r_o12, fabric_thsens_fm_mode_r_o13, fabric_thsens_fm_mode_r_o14, fabric_thsens_fm_mode_r_o15, fabric_thsens_fm_mode_r_o16, fabric_thsens_fm_mode_r_o17, fabric_thsens_fm_mode_r_o18, fabric_thsens_fm_mode_r_o19, fabric_thsens_fm_mode_r_o20, fabric_thsens_fm_mode_r_o21, fabric_thsens_fm_mode_r_o22, fabric_thsens_fm_mode_r_o23, fabric_thsens_fm_mode_r_o24, fabric_thsens_fm_mode_r_o25, fabric_thsens_fm_mode_r_o26, fabric_thsens_fm_mode_r_o27, fabric_thsens_fm_mode_r_o28, fabric_thsens_fm_mode_r_o29, fabric_thsens_fm_mode_r_o30
+, fabric_thsens_fm_mode_r_o31, fabric_thsens_fm_mode_r_o32, fabric_thsens_fm_config_r_o1, fabric_thsens_fm_config_r_o2, fabric_thsens_fm_config_r_o3, fabric_thsens_fm_config_r_o4, fabric_thsens_fm_config_r_o5, fabric_thsens_fm_config_r_o6, fabric_thsens_fm_config_r_o7, fabric_thsens_fm_config_r_o8, fabric_thsens_fm_config_r_o9, fabric_thsens_fm_config_r_o10, fabric_thsens_fm_config_r_o11, fabric_thsens_fm_config_r_o12, fabric_thsens_fm_config_r_o13, fabric_thsens_fm_config_r_o14, fabric_thsens_fm_config_r_o15, fabric_thsens_fm_config_r_o16, fabric_thsens_fm_config_r_o17, fabric_thsens_fm_config_r_o18, fabric_thsens_fm_config_r_o19
+, fabric_thsens_fm_config_r_o20, fabric_thsens_fm_config_r_o21, fabric_thsens_fm_config_r_o22, fabric_thsens_fm_config_r_o23, fabric_thsens_fm_config_r_o24, fabric_thsens_fm_config_r_o25, fabric_thsens_fm_config_r_o26, fabric_thsens_fm_config_r_o27, fabric_thsens_clk_div_ratio_i1, fabric_thsens_clk_div_ratio_i2, fabric_thsens_clk_div_ratio_i3, fabric_thsens_clk_div_ratio_i4, fabric_thsens_clk_div_ratio_i5, fabric_thsens_clk_div_ratio_i6, fabric_thsens_clk_div_ratio_i7, fabric_thsens_clk_div_ratio_i8, fabric_thsens_otp_config_o1, fabric_thsens_otp_config_o2, fabric_thsens_otp_config_o3, fabric_thsens_otp_config_o4, fabric_thsens_otp_config_o5
+, fabric_thsens_otp_config_o6, fabric_thsens_otp_config_o7, fabric_thsens_otp_config_o8, fabric_thsens_otp_config_o9, fabric_thsens_otp_config_o10, fabric_thsens_otp_config_o11, fabric_thsens_otp_config_o12, fabric_thsens_otp_config_o13, fabric_thsens_otp_config_o14, fabric_thsens_otp_config_o15, fabric_thsens_otp_config_o16, fabric_thsens_otp_config_o17, fabric_thsens_otp_config_o18, fabric_thsens_otp_config_o19, fabric_thsens_otp_config_o20, fabric_thsens_otp_config_o21, fabric_thsens_otp_config_o22, fabric_thsens_otp_config_o23, fabric_thsens_otp_config_o24, fabric_thsens_otp_config_o25, fabric_thsens_otp_config_o26
+, fabric_thsens_otp_config_o27, fabric_spi_clk_i2, fabric_spi_sck_i2, fabric_spi_clk_i0, fabric_spi_sck_i0, fabric_spi_clk_i1, fabric_spi_sck_i1, fabric_spi_needed_i1, fabric_spi_needed_i2, fabric_spi_needed_i3, fabric_spi_bsm_release_o1, fabric_spi_bsm_release_o2, fabric_spi_bsm_release_o3, fabric_spi_arst_tmr_n_i1, fabric_spi_arst_tmr_n_i2, fabric_spi_arst_tmr_n_i3, fabric_spi_arst_tmr_n_i4, fabric_spi_arst_tmr_n_i5, fabric_spi_arst_tmr_n_i6, fabric_spi_arst_tmr_n_i7, fabric_spi_arst_tmr_n_i8
+, fabric_spi_arst_tmr_n_i9, fabric_spi_fifo_arst_tmr_n_i1, fabric_spi_fifo_arst_tmr_n_i2, fabric_spi_fifo_arst_tmr_n_i3, fabric_spi_fifo_arst_tmr_n_i4, fabric_spi_fifo_arst_tmr_n_i5, fabric_spi_fifo_arst_tmr_n_i6, fabric_spi_fifo_arst_tmr_n_i7, fabric_spi_fifo_arst_tmr_n_i8, fabric_spi_fifo_arst_tmr_n_i9, fabric_spi_cpol_i1, fabric_spi_cpol_i2, fabric_spi_cpol_i3, fabric_spi_cpha_i1, fabric_spi_cpha_i2, fabric_spi_cpha_i3, fabric_spi_loopback_i1, fabric_spi_loopback_i2, fabric_spi_loopback_i3, fabric_spi_lsb_first_i1, fabric_spi_lsb_first_i2
+, fabric_spi_lsb_first_i3, fabric_spi_cs_setuptime_i1, fabric_spi_cs_setuptime_i2, fabric_spi_cs_setuptime_i3, fabric_spi_cs_setuptime_i4, fabric_spi_cs_setuptime_i5, fabric_spi_cs_setuptime_i6, fabric_spi_cs_setuptime_i7, fabric_spi_cs_setuptime_i8, fabric_spi_cs_setuptime_i9, fabric_spi_cs_setuptime_i10, fabric_spi_cs_setuptime_i11, fabric_spi_cs_setuptime_i12, fabric_spi_cs_holdtime_i1, fabric_spi_cs_holdtime_i2, fabric_spi_cs_holdtime_i3, fabric_spi_cs_holdtime_i4, fabric_spi_cs_holdtime_i5, fabric_spi_cs_holdtime_i6, fabric_spi_cs_holdtime_i7, fabric_spi_cs_holdtime_i8
+, fabric_spi_cs_holdtime_i9, fabric_spi_cs_holdtime_i10, fabric_spi_cs_holdtime_i11, fabric_spi_cs_holdtime_i12, fabric_spi_cs_offtime_i1, fabric_spi_cs_offtime_i2, fabric_spi_cs_offtime_i3, fabric_spi_cs_offtime_i4, fabric_spi_cs_offtime_i5, fabric_spi_cs_offtime_i6, fabric_spi_cs_offtime_i7, fabric_spi_cs_offtime_i8, fabric_spi_cs_offtime_i9, fabric_spi_cs_offtime_i10, fabric_spi_cs_offtime_i11, fabric_spi_cs_offtime_i12, fabric_spi_vcc_enable_i1, fabric_spi_vcc_enable_i2, fabric_spi_vcc_enable_i3, fabric_spi_powerdown_cycle_i1, fabric_spi_powerdown_cycle_i2
+, fabric_spi_powerdown_cycle_i3, fabric_spi_powerdown_cycle_i4, fabric_spi_powerdown_cycle_i5, fabric_spi_powerdown_cycle_i6, fabric_spi_powerdown_cycle_i7, fabric_spi_powerdown_cycle_i8, fabric_spi_powerdown_cycle_i9, fabric_spi_powerdown_cycle_i10, fabric_spi_powerdown_cycle_i11, fabric_spi_powerdown_cycle_i12, fabric_spi_powerdown_cycle_i13, fabric_spi_powerdown_cycle_i14, fabric_spi_powerdown_cycle_i15, fabric_spi_powerdown_cycle_i16, fabric_spi_powerdown_cycle_i17, fabric_spi_powerdown_cycle_i18, fabric_spi_powerdown_cycle_i19, fabric_spi_powerdown_cycle_i20, fabric_spi_powerdown_cycle_i21, fabric_spi_powerdown_cycle_i22, fabric_spi_powerdown_cycle_i23
+, fabric_spi_powerdown_cycle_i24, fabric_spi_powerdown_cycle_i25, fabric_spi_powerdown_cycle_i26, fabric_spi_powerdown_cycle_i27, fabric_spi_powerdown_cycle_i28, fabric_spi_powerdown_cycle_i29, fabric_spi_powerdown_cycle_i30, fabric_spi_powerdown_cycle_i31, fabric_spi_powerdown_cycle_i32, fabric_spi_powerdown_cycle_i33, fabric_spi_powerdown_cycle_i34, fabric_spi_powerdown_cycle_i35, fabric_spi_powerdown_cycle_i36, fabric_spi_powerdown_cycle_i37, fabric_spi_powerdown_cycle_i38, fabric_spi_powerdown_cycle_i39, fabric_spi_powerdown_cycle_i40, fabric_spi_powerdown_cycle_i41, fabric_spi_powerdown_cycle_i42, fabric_spi_powerdown_cycle_i43, fabric_spi_powerdown_cycle_i44
+, fabric_spi_powerdown_cycle_i45, fabric_spi_powerdown_cycle_i46, fabric_spi_powerdown_cycle_i47, fabric_spi_powerdown_cycle_i48, fabric_spi_powerup_cycle_i1, fabric_spi_powerup_cycle_i2, fabric_spi_powerup_cycle_i3, fabric_spi_powerup_cycle_i4, fabric_spi_powerup_cycle_i5, fabric_spi_powerup_cycle_i6, fabric_spi_powerup_cycle_i7, fabric_spi_powerup_cycle_i8, fabric_spi_powerup_cycle_i9, fabric_spi_powerup_cycle_i10, fabric_spi_powerup_cycle_i11, fabric_spi_powerup_cycle_i12, fabric_spi_powerup_cycle_i13, fabric_spi_powerup_cycle_i14, fabric_spi_powerup_cycle_i15, fabric_spi_powerup_cycle_i16, fabric_spi_powerup_cycle_i17
+, fabric_spi_powerup_cycle_i18, fabric_spi_powerup_cycle_i19, fabric_spi_powerup_cycle_i20, fabric_spi_powerup_cycle_i21, fabric_spi_powerup_cycle_i22, fabric_spi_powerup_cycle_i23, fabric_spi_powerup_cycle_i24, fabric_spi_powerup_cycle_i25, fabric_spi_powerup_cycle_i26, fabric_spi_powerup_cycle_i27, fabric_spi_powerup_cycle_i28, fabric_spi_powerup_cycle_i29, fabric_spi_powerup_cycle_i30, fabric_spi_powerup_cycle_i31, fabric_spi_powerup_cycle_i32, fabric_spi_powerup_cycle_i33, fabric_spi_powerup_cycle_i34, fabric_spi_powerup_cycle_i35, fabric_spi_powerup_cycle_i36, fabric_spi_powerup_cycle_i37, fabric_spi_powerup_cycle_i38
+, fabric_spi_powerup_cycle_i39, fabric_spi_powerup_cycle_i40, fabric_spi_powerup_cycle_i41, fabric_spi_powerup_cycle_i42, fabric_spi_powerup_cycle_i43, fabric_spi_powerup_cycle_i44, fabric_spi_powerup_cycle_i45, fabric_spi_powerup_cycle_i46, fabric_spi_powerup_cycle_i47, fabric_spi_powerup_cycle_i48, fabric_spi_legacy_enable_i1, fabric_spi_legacy_enable_i2, fabric_spi_legacy_enable_i3, fabric_spi_legacy_master_i1, fabric_spi_legacy_master_i2, fabric_spi_legacy_master_i3, fabric_spi_data_in_unlimited_i1, fabric_spi_data_in_unlimited_i2, fabric_spi_data_in_unlimited_i3, fabric_spi_enable_i1, fabric_spi_enable_i2
+, fabric_spi_enable_i3, fabric_spi_rst_n_i1, fabric_spi_rst_n_i2, fabric_spi_rst_n_i3, fabric_spi_init_done_o1, fabric_spi_init_done_o2, fabric_spi_init_done_o3, fabric_spi_busy_o1, fabric_spi_busy_o2, fabric_spi_busy_o3, fabric_spi_vcc_used_o1, fabric_spi_vcc_used_o2, fabric_spi_vcc_used_o3, fabric_spi_error_sel_o1, fabric_spi_error_sel_o2, fabric_spi_error_sel_o3, fabric_spi_error_loopback_o1, fabric_spi_error_loopback_o2, fabric_spi_error_loopback_o3, fabric_spi_error_mode_o1, fabric_spi_error_mode_o2
+, fabric_spi_error_mode_o3, fabric_spi_error_endianness_o1, fabric_spi_error_endianness_o2, fabric_spi_error_endianness_o3, fabric_spi_cmd_push_i1, fabric_spi_cmd_push_i2, fabric_spi_cmd_push_i3, fabric_spi_cmd_full_o1, fabric_spi_cmd_full_o2, fabric_spi_cmd_full_o3, fabric_spi_cmd_type_i1, fabric_spi_cmd_type_i2, fabric_spi_cmd_type_i3, fabric_spi_cmd_type_i4, fabric_spi_cmd_type_i5, fabric_spi_cmd_type_i6, fabric_spi_cmd_mode_i1, fabric_spi_cmd_mode_i2, fabric_spi_cmd_mode_i3, fabric_spi_cmd_mode_i4, fabric_spi_cmd_mode_i5
+, fabric_spi_cmd_mode_i6, fabric_spi_cmd_bytes_i1, fabric_spi_cmd_bytes_i2, fabric_spi_cmd_bytes_i3, fabric_spi_cmd_bytes_i4, fabric_spi_cmd_bytes_i5, fabric_spi_cmd_bytes_i6, fabric_spi_mosi_push_i1, fabric_spi_mosi_push_i2, fabric_spi_mosi_push_i3, fabric_spi_mosi_full_o1, fabric_spi_mosi_full_o2, fabric_spi_mosi_full_o3, fabric_spi_mosi_data_i1, fabric_spi_mosi_data_i2, fabric_spi_mosi_data_i3, fabric_spi_mosi_data_i4, fabric_spi_mosi_data_i5, fabric_spi_mosi_data_i6, fabric_spi_mosi_data_i7, fabric_spi_mosi_data_i8
+, fabric_spi_mosi_data_i9, fabric_spi_mosi_data_i10, fabric_spi_mosi_data_i11, fabric_spi_mosi_data_i12, fabric_spi_mosi_data_i13, fabric_spi_mosi_data_i14, fabric_spi_mosi_data_i15, fabric_spi_mosi_data_i16, fabric_spi_mosi_data_i17, fabric_spi_mosi_data_i18, fabric_spi_mosi_data_i19, fabric_spi_mosi_data_i20, fabric_spi_mosi_data_i21, fabric_spi_mosi_data_i22, fabric_spi_mosi_data_i23, fabric_spi_mosi_data_i24, fabric_spi_mosi_data_inv_i1, fabric_spi_mosi_data_inv_i2, fabric_spi_mosi_data_inv_i3, fabric_spi_miso_pop_i1, fabric_spi_miso_pop_i2
+, fabric_spi_miso_pop_i3, fabric_spi_miso_empty_o1, fabric_spi_miso_empty_o2, fabric_spi_miso_empty_o3, fabric_spi_miso_data_o1, fabric_spi_miso_data_o2, fabric_spi_miso_data_o3, fabric_spi_miso_data_o4, fabric_spi_miso_data_o5, fabric_spi_miso_data_o6, fabric_spi_miso_data_o7, fabric_spi_miso_data_o8, fabric_spi_miso_data_o9, fabric_spi_miso_data_o10, fabric_spi_miso_data_o11, fabric_spi_miso_data_o12, fabric_spi_miso_data_o13, fabric_spi_miso_data_o14, fabric_spi_miso_data_o15, fabric_spi_miso_data_o16, fabric_spi_miso_data_o17
+, fabric_spi_miso_data_o18, fabric_spi_miso_data_o19, fabric_spi_miso_data_o20, fabric_spi_miso_data_o21, fabric_spi_miso_data_o22, fabric_spi_miso_data_o23, fabric_spi_miso_data_o24, fabric_spi_miso_data_inv_o1, fabric_spi_miso_data_inv_o2, fabric_spi_miso_data_inv_o3, fabric_spw0_clk_i, fabric_spw0_clk_tx_i, fabric_spw0_rst_n_i, fabric_spw0_user_shared_o, fabric_spw0_tx_fifo_write_i, fabric_spw0_tx_fifo_data_i1, fabric_spw0_tx_fifo_data_i2, fabric_spw0_tx_fifo_data_i3, fabric_spw0_tx_fifo_data_i4, fabric_spw0_tx_fifo_data_i5, fabric_spw0_tx_fifo_data_i6
+, fabric_spw0_tx_fifo_data_i7, fabric_spw0_tx_fifo_data_i8, fabric_spw0_tx_fifo_data_i9, fabric_spw0_tx_fifo_full_o, fabric_spw0_rx_fifo_read_i, fabric_spw0_rx_fifo_empty_o, fabric_spw0_rx_fifo_data_o1, fabric_spw0_rx_fifo_data_o2, fabric_spw0_rx_fifo_data_o3, fabric_spw0_rx_fifo_data_o4, fabric_spw0_rx_fifo_data_o5, fabric_spw0_rx_fifo_data_o6, fabric_spw0_rx_fifo_data_o7, fabric_spw0_rx_fifo_data_o8, fabric_spw0_rx_fifo_data_o9, fabric_spw0_tick_ctm_i, fabric_spw0_tick_ctm_o, fabric_spw0_apb_slv_psel_i, fabric_spw0_apb_slv_penable_i, fabric_spw0_apb_slv_paddr_i1, fabric_spw0_apb_slv_paddr_i2
+, fabric_spw0_apb_slv_paddr_i3, fabric_spw0_apb_slv_paddr_i4, fabric_spw0_apb_slv_paddr_i5, fabric_spw0_apb_slv_pwrite_i, fabric_spw0_apb_slv_pwdata_i1, fabric_spw0_apb_slv_pwdata_i2, fabric_spw0_apb_slv_pwdata_i3, fabric_spw0_apb_slv_pwdata_i4, fabric_spw0_apb_slv_pwdata_i5, fabric_spw0_apb_slv_pwdata_i6, fabric_spw0_apb_slv_pwdata_i7, fabric_spw0_apb_slv_pwdata_i8, fabric_spw0_apb_slv_pwdata_i9, fabric_spw0_apb_slv_pwdata_i10, fabric_spw0_apb_slv_pwdata_i11, fabric_spw0_apb_slv_pwdata_i12, fabric_spw0_apb_slv_pwdata_i13, fabric_spw0_apb_slv_pwdata_i14, fabric_spw0_apb_slv_pwdata_i15, fabric_spw0_apb_slv_pwdata_i16, fabric_spw0_apb_slv_pwdata_i17
+, fabric_spw0_apb_slv_pwdata_i18, fabric_spw0_apb_slv_pwdata_i19, fabric_spw0_apb_slv_pwdata_i20, fabric_spw0_apb_slv_pwdata_i21, fabric_spw0_apb_slv_pwdata_i22, fabric_spw0_apb_slv_pwdata_i23, fabric_spw0_apb_slv_pwdata_i24, fabric_spw0_apb_slv_pwdata_i25, fabric_spw0_apb_slv_pwdata_i26, fabric_spw0_apb_slv_pwdata_i27, fabric_spw0_apb_slv_pwdata_i28, fabric_spw0_apb_slv_pwdata_i29, fabric_spw0_apb_slv_pwdata_i30, fabric_spw0_apb_slv_pwdata_i31, fabric_spw0_apb_slv_prdata_o1, fabric_spw0_apb_slv_prdata_o2, fabric_spw0_apb_slv_prdata_o3, fabric_spw0_apb_slv_prdata_o4, fabric_spw0_apb_slv_prdata_o5, fabric_spw0_apb_slv_prdata_o6, fabric_spw0_apb_slv_prdata_o7
+, fabric_spw0_apb_slv_prdata_o8, fabric_spw0_apb_slv_prdata_o9, fabric_spw0_apb_slv_prdata_o10, fabric_spw0_apb_slv_prdata_o11, fabric_spw0_apb_slv_prdata_o12, fabric_spw0_apb_slv_prdata_o13, fabric_spw0_apb_slv_prdata_o14, fabric_spw0_apb_slv_prdata_o15, fabric_spw0_apb_slv_prdata_o16, fabric_spw0_apb_slv_prdata_o17, fabric_spw0_apb_slv_prdata_o18, fabric_spw0_apb_slv_prdata_o19, fabric_spw0_apb_slv_prdata_o20, fabric_spw0_apb_slv_prdata_o21, fabric_spw0_apb_slv_prdata_o22, fabric_spw0_apb_slv_prdata_o23, fabric_spw0_apb_slv_prdata_o24, fabric_spw0_apb_slv_prdata_o25, fabric_spw0_apb_slv_prdata_o26, fabric_spw0_apb_slv_prdata_o27, fabric_spw0_apb_slv_prdata_o28
+, fabric_spw0_apb_slv_prdata_o29, fabric_spw0_apb_slv_prdata_o30, fabric_spw0_apb_slv_prdata_o31, fabric_spw0_apb_slv_pready_o, fabric_spw0_apb_slv_pslverr_o, fabric_spw1_clk_i, fabric_spw1_clk_tx_i, fabric_spw1_rst_n_i, fabric_spw1_user_shared_o, fabric_spw1_tx_fifo_write_i, fabric_spw1_tx_fifo_data_i1, fabric_spw1_tx_fifo_data_i2, fabric_spw1_tx_fifo_data_i3, fabric_spw1_tx_fifo_data_i4, fabric_spw1_tx_fifo_data_i5, fabric_spw1_tx_fifo_data_i6, fabric_spw1_tx_fifo_data_i7, fabric_spw1_tx_fifo_data_i8, fabric_spw1_tx_fifo_data_i9, fabric_spw1_tx_fifo_full_o, fabric_spw1_rx_fifo_read_i
+, fabric_spw1_rx_fifo_empty_o, fabric_spw1_rx_fifo_data_o1, fabric_spw1_rx_fifo_data_o2, fabric_spw1_rx_fifo_data_o3, fabric_spw1_rx_fifo_data_o4, fabric_spw1_rx_fifo_data_o5, fabric_spw1_rx_fifo_data_o6, fabric_spw1_rx_fifo_data_o7, fabric_spw1_rx_fifo_data_o8, fabric_spw1_rx_fifo_data_o9, fabric_spw1_tick_ctm_i, fabric_spw1_tick_ctm_o, fabric_spw1_apb_slv_psel_i, fabric_spw1_apb_slv_penable_i, fabric_spw1_apb_slv_paddr_i1, fabric_spw1_apb_slv_paddr_i2, fabric_spw1_apb_slv_paddr_i3, fabric_spw1_apb_slv_paddr_i4, fabric_spw1_apb_slv_paddr_i5, fabric_spw1_apb_slv_pwrite_i, fabric_spw1_apb_slv_pwdata_i1
+, fabric_spw1_apb_slv_pwdata_i2, fabric_spw1_apb_slv_pwdata_i3, fabric_spw1_apb_slv_pwdata_i4, fabric_spw1_apb_slv_pwdata_i5, fabric_spw1_apb_slv_pwdata_i6, fabric_spw1_apb_slv_pwdata_i7, fabric_spw1_apb_slv_pwdata_i8, fabric_spw1_apb_slv_pwdata_i9, fabric_spw1_apb_slv_pwdata_i10, fabric_spw1_apb_slv_pwdata_i11, fabric_spw1_apb_slv_pwdata_i12, fabric_spw1_apb_slv_pwdata_i13, fabric_spw1_apb_slv_pwdata_i14, fabric_spw1_apb_slv_pwdata_i15, fabric_spw1_apb_slv_pwdata_i16, fabric_spw1_apb_slv_pwdata_i17, fabric_spw1_apb_slv_pwdata_i18, fabric_spw1_apb_slv_pwdata_i19, fabric_spw1_apb_slv_pwdata_i20, fabric_spw1_apb_slv_pwdata_i21, fabric_spw1_apb_slv_pwdata_i22
+, fabric_spw1_apb_slv_pwdata_i23, fabric_spw1_apb_slv_pwdata_i24, fabric_spw1_apb_slv_pwdata_i25, fabric_spw1_apb_slv_pwdata_i26, fabric_spw1_apb_slv_pwdata_i27, fabric_spw1_apb_slv_pwdata_i28, fabric_spw1_apb_slv_pwdata_i29, fabric_spw1_apb_slv_pwdata_i30, fabric_spw1_apb_slv_pwdata_i31, fabric_spw1_apb_slv_prdata_o1, fabric_spw1_apb_slv_prdata_o2, fabric_spw1_apb_slv_prdata_o3, fabric_spw1_apb_slv_prdata_o4, fabric_spw1_apb_slv_prdata_o5, fabric_spw1_apb_slv_prdata_o6, fabric_spw1_apb_slv_prdata_o7, fabric_spw1_apb_slv_prdata_o8, fabric_spw1_apb_slv_prdata_o9, fabric_spw1_apb_slv_prdata_o10, fabric_spw1_apb_slv_prdata_o11, fabric_spw1_apb_slv_prdata_o12
+, fabric_spw1_apb_slv_prdata_o13, fabric_spw1_apb_slv_prdata_o14, fabric_spw1_apb_slv_prdata_o15, fabric_spw1_apb_slv_prdata_o16, fabric_spw1_apb_slv_prdata_o17, fabric_spw1_apb_slv_prdata_o18, fabric_spw1_apb_slv_prdata_o19, fabric_spw1_apb_slv_prdata_o20, fabric_spw1_apb_slv_prdata_o21, fabric_spw1_apb_slv_prdata_o22, fabric_spw1_apb_slv_prdata_o23, fabric_spw1_apb_slv_prdata_o24, fabric_spw1_apb_slv_prdata_o25, fabric_spw1_apb_slv_prdata_o26, fabric_spw1_apb_slv_prdata_o27, fabric_spw1_apb_slv_prdata_o28, fabric_spw1_apb_slv_prdata_o29, fabric_spw1_apb_slv_prdata_o30, fabric_spw1_apb_slv_prdata_o31, fabric_spw1_apb_slv_pready_o, fabric_spw1_apb_slv_pslverr_o
+);
+    output fabric_cfg_fabric_user_enable_o;
+    output fabric_cfg_fabric_user_flag_o;
+    output fabric_clk_bsm_o;
+    input fabric_clk_otp_mux_i;
+    output fabric_clk_otp_o;
+    output fabric_clk_user0_o;
+    output fabric_clk_user1_o;
+    input fabric_enable_TMR_i1;
+    input fabric_enable_TMR_i2;
+    input fabric_enable_TMR_i3;
+    output fabric_flag_ready_TMR_o1;
+    output fabric_flag_ready_TMR_o2;
+    output fabric_flag_ready_TMR_o3;
+    output fabric_flag_trigger0_o;
+    output fabric_flag_trigger1_o;
+    input fabric_io_in_i1;
+    input fabric_io_in_i10;
+    input fabric_io_in_i11;
+    input fabric_io_in_i12;
+    input fabric_io_in_i13;
+    input fabric_io_in_i14;
+    input fabric_io_in_i15;
+    input fabric_io_in_i16;
+    input fabric_io_in_i17;
+    input fabric_io_in_i18;
+    input fabric_io_in_i19;
+    input fabric_io_in_i2;
+    input fabric_io_in_i20;
+    input fabric_io_in_i21;
+    input fabric_io_in_i22;
+    input fabric_io_in_i23;
+    input fabric_io_in_i24;
+    input fabric_io_in_i25;
+    input fabric_io_in_i26;
+    input fabric_io_in_i27;
+    input fabric_io_in_i28;
+    input fabric_io_in_i29;
+    input fabric_io_in_i3;
+    input fabric_io_in_i30;
+    input fabric_io_in_i31;
+    input fabric_io_in_i32;
+    input fabric_io_in_i33;
+    input fabric_io_in_i34;
+    input fabric_io_in_i35;
+    input fabric_io_in_i4;
+    input fabric_io_in_i5;
+    input fabric_io_in_i6;
+    input fabric_io_in_i7;
+    input fabric_io_in_i8;
+    input fabric_io_in_i9;
+    input fabric_io_oe_i1;
+    input fabric_io_oe_i10;
+    input fabric_io_oe_i11;
+    input fabric_io_oe_i12;
+    input fabric_io_oe_i13;
+    input fabric_io_oe_i14;
+    input fabric_io_oe_i15;
+    input fabric_io_oe_i16;
+    input fabric_io_oe_i17;
+    input fabric_io_oe_i18;
+    input fabric_io_oe_i19;
+    input fabric_io_oe_i2;
+    input fabric_io_oe_i20;
+    input fabric_io_oe_i21;
+    input fabric_io_oe_i22;
+    input fabric_io_oe_i23;
+    input fabric_io_oe_i24;
+    input fabric_io_oe_i25;
+    input fabric_io_oe_i26;
+    input fabric_io_oe_i27;
+    input fabric_io_oe_i28;
+    input fabric_io_oe_i29;
+    input fabric_io_oe_i3;
+    input fabric_io_oe_i30;
+    input fabric_io_oe_i31;
+    input fabric_io_oe_i32;
+    input fabric_io_oe_i33;
+    input fabric_io_oe_i34;
+    input fabric_io_oe_i35;
+    input fabric_io_oe_i4;
+    input fabric_io_oe_i5;
+    input fabric_io_oe_i6;
+    input fabric_io_oe_i7;
+    input fabric_io_oe_i8;
+    input fabric_io_oe_i9;
+    output fabric_io_out_o1;
+    output fabric_io_out_o10;
+    output fabric_io_out_o11;
+    output fabric_io_out_o12;
+    output fabric_io_out_o13;
+    output fabric_io_out_o14;
+    output fabric_io_out_o15;
+    output fabric_io_out_o16;
+    output fabric_io_out_o17;
+    output fabric_io_out_o18;
+    output fabric_io_out_o19;
+    output fabric_io_out_o2;
+    output fabric_io_out_o20;
+    output fabric_io_out_o21;
+    output fabric_io_out_o22;
+    output fabric_io_out_o23;
+    output fabric_io_out_o24;
+    output fabric_io_out_o25;
+    output fabric_io_out_o26;
+    output fabric_io_out_o27;
+    output fabric_io_out_o28;
+    output fabric_io_out_o29;
+    output fabric_io_out_o3;
+    output fabric_io_out_o30;
+    output fabric_io_out_o31;
+    output fabric_io_out_o32;
+    output fabric_io_out_o33;
+    output fabric_io_out_o34;
+    output fabric_io_out_o35;
+    output fabric_io_out_o4;
+    output fabric_io_out_o5;
+    output fabric_io_out_o6;
+    output fabric_io_out_o7;
+    output fabric_io_out_o8;
+    output fabric_io_out_o9;
+    output fabric_jtag_tck_o;
+    output fabric_jtag_tdi_o;
+    input fabric_jtag_tdo_usr1_i;
+    input fabric_jtag_tdo_usr2_i;
+    output fabric_jtag_tms_o;
+    output fabric_jtag_trst_n_o;
+    output fabric_jtag_usr1_o;
+    output fabric_jtag_usr2_o;
+    input fabric_lowskew_i1;
+    input fabric_lowskew_i10;
+    input fabric_lowskew_i11;
+    input fabric_lowskew_i12;
+    input fabric_lowskew_i13;
+    input fabric_lowskew_i14;
+    input fabric_lowskew_i15;
+    input fabric_lowskew_i16;
+    input fabric_lowskew_i17;
+    input fabric_lowskew_i18;
+    input fabric_lowskew_i19;
+    input fabric_lowskew_i2;
+    input fabric_lowskew_i20;
+    input fabric_lowskew_i21;
+    input fabric_lowskew_i22;
+    input fabric_lowskew_i23;
+    input fabric_lowskew_i24;
+    input fabric_lowskew_i25;
+    input fabric_lowskew_i26;
+    input fabric_lowskew_i27;
+    input fabric_lowskew_i28;
+    input fabric_lowskew_i29;
+    input fabric_lowskew_i3;
+    input fabric_lowskew_i30;
+    input fabric_lowskew_i31;
+    input fabric_lowskew_i32;
+    input fabric_lowskew_i33;
+    input fabric_lowskew_i34;
+    input fabric_lowskew_i35;
+    input fabric_lowskew_i36;
+    input fabric_lowskew_i37;
+    input fabric_lowskew_i38;
+    input fabric_lowskew_i39;
+    input fabric_lowskew_i4;
+    input fabric_lowskew_i40;
+    input fabric_lowskew_i5;
+    input fabric_lowskew_i6;
+    input fabric_lowskew_i7;
+    input fabric_lowskew_i8;
+    input fabric_lowskew_i9;
+    output fabric_lowskew_o1;
+    output fabric_lowskew_o2;
+    output fabric_lowskew_o3;
+    output fabric_lowskew_o4;
+    output fabric_lowskew_o5;
+    output fabric_lowskew_o6;
+    output fabric_otp_user_ack_o;
+    input fabric_otp_user_add_i1;
+    input fabric_otp_user_add_i2;
+    input fabric_otp_user_add_i3;
+    input fabric_otp_user_add_i4;
+    input fabric_otp_user_add_i5;
+    input fabric_otp_user_add_i6;
+    input fabric_otp_user_add_i7;
+    output fabric_otp_user_bbad_o;
+    output fabric_otp_user_bend1_o;
+    output fabric_otp_user_bend2_o;
+    output fabric_otp_user_bist1fail_o1;
+    output fabric_otp_user_bist1fail_o2;
+    output fabric_otp_user_bist1fail_o3;
+    output fabric_otp_user_bist1fail_o4;
+    output fabric_otp_user_bist1fail_o5;
+    output fabric_otp_user_bist1fail_o6;
+    output fabric_otp_user_bist1fail_o7;
+    output fabric_otp_user_bist1fail_o8;
+    output fabric_otp_user_bist2fail_o1;
+    output fabric_otp_user_bist2fail_o2;
+    output fabric_otp_user_bist2fail_o3;
+    output fabric_otp_user_bist2fail_o4;
+    output fabric_otp_user_bist2fail_o5;
+    output fabric_otp_user_bist2fail_o6;
+    output fabric_otp_user_bist2fail_o7;
+    input fabric_otp_user_bistmode_i;
+    output fabric_otp_user_calibrated_o;
+    input fabric_otp_user_clk_i;
+    input fabric_otp_user_clock_frequency_range_i;
+    output fabric_otp_user_ded_o;
+    input fabric_otp_user_din_i1;
+    input fabric_otp_user_din_i10;
+    input fabric_otp_user_din_i11;
+    input fabric_otp_user_din_i12;
+    input fabric_otp_user_din_i13;
+    input fabric_otp_user_din_i14;
+    input fabric_otp_user_din_i15;
+    input fabric_otp_user_din_i16;
+    input fabric_otp_user_din_i17;
+    input fabric_otp_user_din_i18;
+    input fabric_otp_user_din_i19;
+    input fabric_otp_user_din_i2;
+    input fabric_otp_user_din_i20;
+    input fabric_otp_user_din_i21;
+    input fabric_otp_user_din_i22;
+    input fabric_otp_user_din_i23;
+    input fabric_otp_user_din_i24;
+    input fabric_otp_user_din_i25;
+    input fabric_otp_user_din_i26;
+    input fabric_otp_user_din_i27;
+    input fabric_otp_user_din_i28;
+    input fabric_otp_user_din_i29;
+    input fabric_otp_user_din_i3;
+    input fabric_otp_user_din_i30;
+    input fabric_otp_user_din_i31;
+    input fabric_otp_user_din_i32;
+    input fabric_otp_user_din_i33;
+    input fabric_otp_user_din_i34;
+    input fabric_otp_user_din_i35;
+    input fabric_otp_user_din_i36;
+    input fabric_otp_user_din_i37;
+    input fabric_otp_user_din_i38;
+    input fabric_otp_user_din_i39;
+    input fabric_otp_user_din_i4;
+    input fabric_otp_user_din_i5;
+    input fabric_otp_user_din_i6;
+    input fabric_otp_user_din_i7;
+    input fabric_otp_user_din_i8;
+    input fabric_otp_user_din_i9;
+    input fabric_otp_user_disturbcheck_i;
+    output fabric_otp_user_disturbed_o;
+    output fabric_otp_user_dout_o1;
+    output fabric_otp_user_dout_o10;
+    output fabric_otp_user_dout_o11;
+    output fabric_otp_user_dout_o12;
+    output fabric_otp_user_dout_o13;
+    output fabric_otp_user_dout_o14;
+    output fabric_otp_user_dout_o15;
+    output fabric_otp_user_dout_o16;
+    output fabric_otp_user_dout_o17;
+    output fabric_otp_user_dout_o18;
+    output fabric_otp_user_dout_o19;
+    output fabric_otp_user_dout_o2;
+    output fabric_otp_user_dout_o20;
+    output fabric_otp_user_dout_o21;
+    output fabric_otp_user_dout_o22;
+    output fabric_otp_user_dout_o23;
+    output fabric_otp_user_dout_o24;
+    output fabric_otp_user_dout_o25;
+    output fabric_otp_user_dout_o26;
+    output fabric_otp_user_dout_o27;
+    output fabric_otp_user_dout_o28;
+    output fabric_otp_user_dout_o29;
+    output fabric_otp_user_dout_o3;
+    output fabric_otp_user_dout_o30;
+    output fabric_otp_user_dout_o31;
+    output fabric_otp_user_dout_o32;
+    output fabric_otp_user_dout_o33;
+    output fabric_otp_user_dout_o34;
+    output fabric_otp_user_dout_o35;
+    output fabric_otp_user_dout_o36;
+    output fabric_otp_user_dout_o37;
+    output fabric_otp_user_dout_o38;
+    output fabric_otp_user_dout_o39;
+    output fabric_otp_user_dout_o4;
+    output fabric_otp_user_dout_o40;
+    output fabric_otp_user_dout_o41;
+    output fabric_otp_user_dout_o5;
+    output fabric_otp_user_dout_o6;
+    output fabric_otp_user_dout_o7;
+    output fabric_otp_user_dout_o8;
+    output fabric_otp_user_dout_o9;
+    input fabric_otp_user_eccbypass_i;
+    output fabric_otp_user_flagstate_o1;
+    output fabric_otp_user_flagstate_o2;
+    output fabric_otp_user_flagstate_o3;
+    output fabric_otp_user_flagstate_o4;
+    output fabric_otp_user_locked_o;
+    input fabric_otp_user_pdn_i;
+    input fabric_otp_user_prgwidth_i1;
+    input fabric_otp_user_prgwidth_i2;
+    input fabric_otp_user_prgwidth_i3;
+    input fabric_otp_user_prog_i;
+    output fabric_otp_user_progfail_o;
+    output fabric_otp_user_pwok_o;
+    input fabric_otp_user_rbact1_i;
+    input fabric_otp_user_rbact2_i;
+    input fabric_otp_user_read_i;
+    input fabric_otp_user_redbypass_i;
+    output fabric_otp_user_sec_o;
+    output fabric_otp_user_startword_o1;
+    output fabric_otp_user_startword_o10;
+    output fabric_otp_user_startword_o11;
+    output fabric_otp_user_startword_o12;
+    output fabric_otp_user_startword_o13;
+    output fabric_otp_user_startword_o14;
+    output fabric_otp_user_startword_o15;
+    output fabric_otp_user_startword_o16;
+    output fabric_otp_user_startword_o2;
+    output fabric_otp_user_startword_o3;
+    output fabric_otp_user_startword_o4;
+    output fabric_otp_user_startword_o5;
+    output fabric_otp_user_startword_o6;
+    output fabric_otp_user_startword_o7;
+    output fabric_otp_user_startword_o8;
+    output fabric_otp_user_startword_o9;
+    input fabric_otp_user_suppadd_i;
+    input fabric_otp_user_tm_i;
+    input fabric_otp_user_tst_scanenable_i;
+    input fabric_otp_user_tst_scanin_i1;
+    input fabric_otp_user_tst_scanin_i2;
+    input fabric_otp_user_tst_scanin_i3;
+    input fabric_otp_user_tst_scanin_i4;
+    input fabric_otp_user_tst_scanin_i5;
+    output fabric_otp_user_tst_scanout_o1;
+    output fabric_otp_user_tst_scanout_o2;
+    output fabric_otp_user_tst_scanout_o3;
+    output fabric_otp_user_tst_scanout_o4;
+    output fabric_otp_user_tst_scanout_o5;
+    output fabric_otp_user_wlromout_o1;
+    output fabric_otp_user_wlromout_o10;
+    output fabric_otp_user_wlromout_o2;
+    output fabric_otp_user_wlromout_o3;
+    output fabric_otp_user_wlromout_o4;
+    output fabric_otp_user_wlromout_o5;
+    output fabric_otp_user_wlromout_o6;
+    output fabric_otp_user_wlromout_o7;
+    output fabric_otp_user_wlromout_o8;
+    output fabric_otp_user_wlromout_o9;
+    input fabric_otp_user_wordlock_i;
+    input fabric_parusr_clk_i;
+    input fabric_parusr_cs_i;
+    input fabric_parusr_data_i1;
+    input fabric_parusr_data_i10;
+    input fabric_parusr_data_i11;
+    input fabric_parusr_data_i12;
+    input fabric_parusr_data_i13;
+    input fabric_parusr_data_i14;
+    input fabric_parusr_data_i15;
+    input fabric_parusr_data_i16;
+    input fabric_parusr_data_i2;
+    input fabric_parusr_data_i3;
+    input fabric_parusr_data_i4;
+    input fabric_parusr_data_i5;
+    input fabric_parusr_data_i6;
+    input fabric_parusr_data_i7;
+    input fabric_parusr_data_i8;
+    input fabric_parusr_data_i9;
+    output fabric_parusr_data_o1;
+    output fabric_parusr_data_o10;
+    output fabric_parusr_data_o11;
+    output fabric_parusr_data_o12;
+    output fabric_parusr_data_o13;
+    output fabric_parusr_data_o14;
+    output fabric_parusr_data_o15;
+    output fabric_parusr_data_o16;
+    output fabric_parusr_data_o2;
+    output fabric_parusr_data_o3;
+    output fabric_parusr_data_o4;
+    output fabric_parusr_data_o5;
+    output fabric_parusr_data_o6;
+    output fabric_parusr_data_o7;
+    output fabric_parusr_data_o8;
+    output fabric_parusr_data_o9;
+    output fabric_parusr_data_val_o;
+    input fabric_parusr_enable_i;
+    input fabric_parusr_type_i1;
+    input fabric_parusr_type_i2;
+    input fabric_spare_i1;
+    input fabric_spare_i10;
+    input fabric_spare_i100;
+    input fabric_spare_i101;
+    input fabric_spare_i102;
+    input fabric_spare_i103;
+    input fabric_spare_i104;
+    input fabric_spare_i105;
+    input fabric_spare_i106;
+    input fabric_spare_i107;
+    input fabric_spare_i108;
+    input fabric_spare_i109;
+    input fabric_spare_i11;
+    input fabric_spare_i110;
+    input fabric_spare_i111;
+    input fabric_spare_i112;
+    input fabric_spare_i113;
+    input fabric_spare_i114;
+    input fabric_spare_i115;
+    input fabric_spare_i116;
+    input fabric_spare_i117;
+    input fabric_spare_i118;
+    input fabric_spare_i119;
+    input fabric_spare_i12;
+    input fabric_spare_i120;
+    input fabric_spare_i121;
+    input fabric_spare_i122;
+    input fabric_spare_i123;
+    input fabric_spare_i124;
+    input fabric_spare_i125;
+    input fabric_spare_i126;
+    input fabric_spare_i127;
+    input fabric_spare_i128;
+    input fabric_spare_i13;
+    input fabric_spare_i14;
+    input fabric_spare_i15;
+    input fabric_spare_i16;
+    input fabric_spare_i17;
+    input fabric_spare_i18;
+    input fabric_spare_i19;
+    input fabric_spare_i2;
+    input fabric_spare_i20;
+    input fabric_spare_i21;
+    input fabric_spare_i22;
+    input fabric_spare_i23;
+    input fabric_spare_i24;
+    input fabric_spare_i25;
+    input fabric_spare_i26;
+    input fabric_spare_i27;
+    input fabric_spare_i28;
+    input fabric_spare_i29;
+    input fabric_spare_i3;
+    input fabric_spare_i30;
+    input fabric_spare_i31;
+    input fabric_spare_i32;
+    input fabric_spare_i33;
+    input fabric_spare_i34;
+    input fabric_spare_i35;
+    input fabric_spare_i36;
+    input fabric_spare_i37;
+    input fabric_spare_i38;
+    input fabric_spare_i39;
+    input fabric_spare_i4;
+    input fabric_spare_i40;
+    input fabric_spare_i41;
+    input fabric_spare_i42;
+    input fabric_spare_i43;
+    input fabric_spare_i44;
+    input fabric_spare_i45;
+    input fabric_spare_i46;
+    input fabric_spare_i47;
+    input fabric_spare_i48;
+    input fabric_spare_i49;
+    input fabric_spare_i5;
+    input fabric_spare_i50;
+    input fabric_spare_i51;
+    input fabric_spare_i52;
+    input fabric_spare_i53;
+    input fabric_spare_i54;
+    input fabric_spare_i55;
+    input fabric_spare_i56;
+    input fabric_spare_i57;
+    input fabric_spare_i58;
+    input fabric_spare_i59;
+    input fabric_spare_i6;
+    input fabric_spare_i60;
+    input fabric_spare_i61;
+    input fabric_spare_i62;
+    input fabric_spare_i63;
+    input fabric_spare_i64;
+    input fabric_spare_i65;
+    input fabric_spare_i66;
+    input fabric_spare_i67;
+    input fabric_spare_i68;
+    input fabric_spare_i69;
+    input fabric_spare_i7;
+    input fabric_spare_i70;
+    input fabric_spare_i71;
+    input fabric_spare_i72;
+    input fabric_spare_i73;
+    input fabric_spare_i74;
+    input fabric_spare_i75;
+    input fabric_spare_i76;
+    input fabric_spare_i77;
+    input fabric_spare_i78;
+    input fabric_spare_i79;
+    input fabric_spare_i8;
+    input fabric_spare_i80;
+    input fabric_spare_i81;
+    input fabric_spare_i82;
+    input fabric_spare_i83;
+    input fabric_spare_i84;
+    input fabric_spare_i85;
+    input fabric_spare_i86;
+    input fabric_spare_i87;
+    input fabric_spare_i88;
+    input fabric_spare_i89;
+    input fabric_spare_i9;
+    input fabric_spare_i90;
+    input fabric_spare_i91;
+    input fabric_spare_i92;
+    input fabric_spare_i93;
+    input fabric_spare_i94;
+    input fabric_spare_i95;
+    input fabric_spare_i96;
+    input fabric_spare_i97;
+    input fabric_spare_i98;
+    input fabric_spare_i99;
+    output fabric_spare_o1;
+    output fabric_spare_o10;
+    output fabric_spare_o100;
+    output fabric_spare_o101;
+    output fabric_spare_o102;
+    output fabric_spare_o103;
+    output fabric_spare_o104;
+    output fabric_spare_o105;
+    output fabric_spare_o106;
+    output fabric_spare_o107;
+    output fabric_spare_o108;
+    output fabric_spare_o109;
+    output fabric_spare_o11;
+    output fabric_spare_o110;
+    output fabric_spare_o111;
+    output fabric_spare_o112;
+    output fabric_spare_o113;
+    output fabric_spare_o114;
+    output fabric_spare_o115;
+    output fabric_spare_o116;
+    output fabric_spare_o117;
+    output fabric_spare_o118;
+    output fabric_spare_o119;
+    output fabric_spare_o12;
+    output fabric_spare_o120;
+    output fabric_spare_o121;
+    output fabric_spare_o122;
+    output fabric_spare_o123;
+    output fabric_spare_o124;
+    output fabric_spare_o125;
+    output fabric_spare_o126;
+    output fabric_spare_o127;
+    output fabric_spare_o128;
+    output fabric_spare_o13;
+    output fabric_spare_o14;
+    output fabric_spare_o15;
+    output fabric_spare_o16;
+    output fabric_spare_o17;
+    output fabric_spare_o18;
+    output fabric_spare_o19;
+    output fabric_spare_o2;
+    output fabric_spare_o20;
+    output fabric_spare_o21;
+    output fabric_spare_o22;
+    output fabric_spare_o23;
+    output fabric_spare_o24;
+    output fabric_spare_o25;
+    output fabric_spare_o26;
+    output fabric_spare_o27;
+    output fabric_spare_o28;
+    output fabric_spare_o29;
+    output fabric_spare_o3;
+    output fabric_spare_o30;
+    output fabric_spare_o31;
+    output fabric_spare_o32;
+    output fabric_spare_o33;
+    output fabric_spare_o34;
+    output fabric_spare_o35;
+    output fabric_spare_o36;
+    output fabric_spare_o37;
+    output fabric_spare_o38;
+    output fabric_spare_o39;
+    output fabric_spare_o4;
+    output fabric_spare_o40;
+    output fabric_spare_o41;
+    output fabric_spare_o42;
+    output fabric_spare_o43;
+    output fabric_spare_o44;
+    output fabric_spare_o45;
+    output fabric_spare_o46;
+    output fabric_spare_o47;
+    output fabric_spare_o48;
+    output fabric_spare_o49;
+    output fabric_spare_o5;
+    output fabric_spare_o50;
+    output fabric_spare_o51;
+    output fabric_spare_o52;
+    output fabric_spare_o53;
+    output fabric_spare_o54;
+    output fabric_spare_o55;
+    output fabric_spare_o56;
+    output fabric_spare_o57;
+    output fabric_spare_o58;
+    output fabric_spare_o59;
+    output fabric_spare_o6;
+    output fabric_spare_o60;
+    output fabric_spare_o61;
+    output fabric_spare_o62;
+    output fabric_spare_o63;
+    output fabric_spare_o64;
+    output fabric_spare_o65;
+    output fabric_spare_o66;
+    output fabric_spare_o67;
+    output fabric_spare_o68;
+    output fabric_spare_o69;
+    output fabric_spare_o7;
+    output fabric_spare_o70;
+    output fabric_spare_o71;
+    output fabric_spare_o72;
+    output fabric_spare_o73;
+    output fabric_spare_o74;
+    output fabric_spare_o75;
+    output fabric_spare_o76;
+    output fabric_spare_o77;
+    output fabric_spare_o78;
+    output fabric_spare_o79;
+    output fabric_spare_o8;
+    output fabric_spare_o80;
+    output fabric_spare_o81;
+    output fabric_spare_o82;
+    output fabric_spare_o83;
+    output fabric_spare_o84;
+    output fabric_spare_o85;
+    output fabric_spare_o86;
+    output fabric_spare_o87;
+    output fabric_spare_o88;
+    output fabric_spare_o89;
+    output fabric_spare_o9;
+    output fabric_spare_o90;
+    output fabric_spare_o91;
+    output fabric_spare_o92;
+    output fabric_spare_o93;
+    output fabric_spare_o94;
+    output fabric_spare_o95;
+    output fabric_spare_o96;
+    output fabric_spare_o97;
+    output fabric_spare_o98;
+    output fabric_spare_o99;
+    input fabric_spi_arst_tmr_n_i1;
+    input fabric_spi_arst_tmr_n_i2;
+    input fabric_spi_arst_tmr_n_i3;
+    input fabric_spi_arst_tmr_n_i4;
+    input fabric_spi_arst_tmr_n_i5;
+    input fabric_spi_arst_tmr_n_i6;
+    input fabric_spi_arst_tmr_n_i7;
+    input fabric_spi_arst_tmr_n_i8;
+    input fabric_spi_arst_tmr_n_i9;
+    output fabric_spi_bsm_release_o1;
+    output fabric_spi_bsm_release_o2;
+    output fabric_spi_bsm_release_o3;
+    output fabric_spi_busy_o1;
+    output fabric_spi_busy_o2;
+    output fabric_spi_busy_o3;
+    input fabric_spi_clk_i0;
+    input fabric_spi_clk_i1;
+    input fabric_spi_clk_i2;
+    input fabric_spi_cmd_bytes_i1;
+    input fabric_spi_cmd_bytes_i2;
+    input fabric_spi_cmd_bytes_i3;
+    input fabric_spi_cmd_bytes_i4;
+    input fabric_spi_cmd_bytes_i5;
+    input fabric_spi_cmd_bytes_i6;
+    output fabric_spi_cmd_full_o1;
+    output fabric_spi_cmd_full_o2;
+    output fabric_spi_cmd_full_o3;
+    input fabric_spi_cmd_mode_i1;
+    input fabric_spi_cmd_mode_i2;
+    input fabric_spi_cmd_mode_i3;
+    input fabric_spi_cmd_mode_i4;
+    input fabric_spi_cmd_mode_i5;
+    input fabric_spi_cmd_mode_i6;
+    input fabric_spi_cmd_push_i1;
+    input fabric_spi_cmd_push_i2;
+    input fabric_spi_cmd_push_i3;
+    input fabric_spi_cmd_type_i1;
+    input fabric_spi_cmd_type_i2;
+    input fabric_spi_cmd_type_i3;
+    input fabric_spi_cmd_type_i4;
+    input fabric_spi_cmd_type_i5;
+    input fabric_spi_cmd_type_i6;
+    input fabric_spi_cpha_i1;
+    input fabric_spi_cpha_i2;
+    input fabric_spi_cpha_i3;
+    input fabric_spi_cpol_i1;
+    input fabric_spi_cpol_i2;
+    input fabric_spi_cpol_i3;
+    input fabric_spi_cs_holdtime_i1;
+    input fabric_spi_cs_holdtime_i10;
+    input fabric_spi_cs_holdtime_i11;
+    input fabric_spi_cs_holdtime_i12;
+    input fabric_spi_cs_holdtime_i2;
+    input fabric_spi_cs_holdtime_i3;
+    input fabric_spi_cs_holdtime_i4;
+    input fabric_spi_cs_holdtime_i5;
+    input fabric_spi_cs_holdtime_i6;
+    input fabric_spi_cs_holdtime_i7;
+    input fabric_spi_cs_holdtime_i8;
+    input fabric_spi_cs_holdtime_i9;
+    input fabric_spi_cs_offtime_i1;
+    input fabric_spi_cs_offtime_i10;
+    input fabric_spi_cs_offtime_i11;
+    input fabric_spi_cs_offtime_i12;
+    input fabric_spi_cs_offtime_i2;
+    input fabric_spi_cs_offtime_i3;
+    input fabric_spi_cs_offtime_i4;
+    input fabric_spi_cs_offtime_i5;
+    input fabric_spi_cs_offtime_i6;
+    input fabric_spi_cs_offtime_i7;
+    input fabric_spi_cs_offtime_i8;
+    input fabric_spi_cs_offtime_i9;
+    input fabric_spi_cs_setuptime_i1;
+    input fabric_spi_cs_setuptime_i10;
+    input fabric_spi_cs_setuptime_i11;
+    input fabric_spi_cs_setuptime_i12;
+    input fabric_spi_cs_setuptime_i2;
+    input fabric_spi_cs_setuptime_i3;
+    input fabric_spi_cs_setuptime_i4;
+    input fabric_spi_cs_setuptime_i5;
+    input fabric_spi_cs_setuptime_i6;
+    input fabric_spi_cs_setuptime_i7;
+    input fabric_spi_cs_setuptime_i8;
+    input fabric_spi_cs_setuptime_i9;
+    input fabric_spi_data_in_unlimited_i1;
+    input fabric_spi_data_in_unlimited_i2;
+    input fabric_spi_data_in_unlimited_i3;
+    input fabric_spi_enable_i1;
+    input fabric_spi_enable_i2;
+    input fabric_spi_enable_i3;
+    output fabric_spi_error_endianness_o1;
+    output fabric_spi_error_endianness_o2;
+    output fabric_spi_error_endianness_o3;
+    output fabric_spi_error_loopback_o1;
+    output fabric_spi_error_loopback_o2;
+    output fabric_spi_error_loopback_o3;
+    output fabric_spi_error_mode_o1;
+    output fabric_spi_error_mode_o2;
+    output fabric_spi_error_mode_o3;
+    output fabric_spi_error_sel_o1;
+    output fabric_spi_error_sel_o2;
+    output fabric_spi_error_sel_o3;
+    input fabric_spi_fifo_arst_tmr_n_i1;
+    input fabric_spi_fifo_arst_tmr_n_i2;
+    input fabric_spi_fifo_arst_tmr_n_i3;
+    input fabric_spi_fifo_arst_tmr_n_i4;
+    input fabric_spi_fifo_arst_tmr_n_i5;
+    input fabric_spi_fifo_arst_tmr_n_i6;
+    input fabric_spi_fifo_arst_tmr_n_i7;
+    input fabric_spi_fifo_arst_tmr_n_i8;
+    input fabric_spi_fifo_arst_tmr_n_i9;
+    output fabric_spi_init_done_o1;
+    output fabric_spi_init_done_o2;
+    output fabric_spi_init_done_o3;
+    input fabric_spi_legacy_enable_i1;
+    input fabric_spi_legacy_enable_i2;
+    input fabric_spi_legacy_enable_i3;
+    input fabric_spi_legacy_master_i1;
+    input fabric_spi_legacy_master_i2;
+    input fabric_spi_legacy_master_i3;
+    input fabric_spi_loopback_i1;
+    input fabric_spi_loopback_i2;
+    input fabric_spi_loopback_i3;
+    input fabric_spi_lsb_first_i1;
+    input fabric_spi_lsb_first_i2;
+    input fabric_spi_lsb_first_i3;
+    output fabric_spi_miso_data_inv_o1;
+    output fabric_spi_miso_data_inv_o2;
+    output fabric_spi_miso_data_inv_o3;
+    output fabric_spi_miso_data_o1;
+    output fabric_spi_miso_data_o10;
+    output fabric_spi_miso_data_o11;
+    output fabric_spi_miso_data_o12;
+    output fabric_spi_miso_data_o13;
+    output fabric_spi_miso_data_o14;
+    output fabric_spi_miso_data_o15;
+    output fabric_spi_miso_data_o16;
+    output fabric_spi_miso_data_o17;
+    output fabric_spi_miso_data_o18;
+    output fabric_spi_miso_data_o19;
+    output fabric_spi_miso_data_o2;
+    output fabric_spi_miso_data_o20;
+    output fabric_spi_miso_data_o21;
+    output fabric_spi_miso_data_o22;
+    output fabric_spi_miso_data_o23;
+    output fabric_spi_miso_data_o24;
+    output fabric_spi_miso_data_o3;
+    output fabric_spi_miso_data_o4;
+    output fabric_spi_miso_data_o5;
+    output fabric_spi_miso_data_o6;
+    output fabric_spi_miso_data_o7;
+    output fabric_spi_miso_data_o8;
+    output fabric_spi_miso_data_o9;
+    output fabric_spi_miso_empty_o1;
+    output fabric_spi_miso_empty_o2;
+    output fabric_spi_miso_empty_o3;
+    input fabric_spi_miso_pop_i1;
+    input fabric_spi_miso_pop_i2;
+    input fabric_spi_miso_pop_i3;
+    input fabric_spi_mosi_data_i1;
+    input fabric_spi_mosi_data_i10;
+    input fabric_spi_mosi_data_i11;
+    input fabric_spi_mosi_data_i12;
+    input fabric_spi_mosi_data_i13;
+    input fabric_spi_mosi_data_i14;
+    input fabric_spi_mosi_data_i15;
+    input fabric_spi_mosi_data_i16;
+    input fabric_spi_mosi_data_i17;
+    input fabric_spi_mosi_data_i18;
+    input fabric_spi_mosi_data_i19;
+    input fabric_spi_mosi_data_i2;
+    input fabric_spi_mosi_data_i20;
+    input fabric_spi_mosi_data_i21;
+    input fabric_spi_mosi_data_i22;
+    input fabric_spi_mosi_data_i23;
+    input fabric_spi_mosi_data_i24;
+    input fabric_spi_mosi_data_i3;
+    input fabric_spi_mosi_data_i4;
+    input fabric_spi_mosi_data_i5;
+    input fabric_spi_mosi_data_i6;
+    input fabric_spi_mosi_data_i7;
+    input fabric_spi_mosi_data_i8;
+    input fabric_spi_mosi_data_i9;
+    input fabric_spi_mosi_data_inv_i1;
+    input fabric_spi_mosi_data_inv_i2;
+    input fabric_spi_mosi_data_inv_i3;
+    output fabric_spi_mosi_full_o1;
+    output fabric_spi_mosi_full_o2;
+    output fabric_spi_mosi_full_o3;
+    input fabric_spi_mosi_push_i1;
+    input fabric_spi_mosi_push_i2;
+    input fabric_spi_mosi_push_i3;
+    input fabric_spi_needed_i1;
+    input fabric_spi_needed_i2;
+    input fabric_spi_needed_i3;
+    input fabric_spi_powerdown_cycle_i1;
+    input fabric_spi_powerdown_cycle_i10;
+    input fabric_spi_powerdown_cycle_i11;
+    input fabric_spi_powerdown_cycle_i12;
+    input fabric_spi_powerdown_cycle_i13;
+    input fabric_spi_powerdown_cycle_i14;
+    input fabric_spi_powerdown_cycle_i15;
+    input fabric_spi_powerdown_cycle_i16;
+    input fabric_spi_powerdown_cycle_i17;
+    input fabric_spi_powerdown_cycle_i18;
+    input fabric_spi_powerdown_cycle_i19;
+    input fabric_spi_powerdown_cycle_i2;
+    input fabric_spi_powerdown_cycle_i20;
+    input fabric_spi_powerdown_cycle_i21;
+    input fabric_spi_powerdown_cycle_i22;
+    input fabric_spi_powerdown_cycle_i23;
+    input fabric_spi_powerdown_cycle_i24;
+    input fabric_spi_powerdown_cycle_i25;
+    input fabric_spi_powerdown_cycle_i26;
+    input fabric_spi_powerdown_cycle_i27;
+    input fabric_spi_powerdown_cycle_i28;
+    input fabric_spi_powerdown_cycle_i29;
+    input fabric_spi_powerdown_cycle_i3;
+    input fabric_spi_powerdown_cycle_i30;
+    input fabric_spi_powerdown_cycle_i31;
+    input fabric_spi_powerdown_cycle_i32;
+    input fabric_spi_powerdown_cycle_i33;
+    input fabric_spi_powerdown_cycle_i34;
+    input fabric_spi_powerdown_cycle_i35;
+    input fabric_spi_powerdown_cycle_i36;
+    input fabric_spi_powerdown_cycle_i37;
+    input fabric_spi_powerdown_cycle_i38;
+    input fabric_spi_powerdown_cycle_i39;
+    input fabric_spi_powerdown_cycle_i4;
+    input fabric_spi_powerdown_cycle_i40;
+    input fabric_spi_powerdown_cycle_i41;
+    input fabric_spi_powerdown_cycle_i42;
+    input fabric_spi_powerdown_cycle_i43;
+    input fabric_spi_powerdown_cycle_i44;
+    input fabric_spi_powerdown_cycle_i45;
+    input fabric_spi_powerdown_cycle_i46;
+    input fabric_spi_powerdown_cycle_i47;
+    input fabric_spi_powerdown_cycle_i48;
+    input fabric_spi_powerdown_cycle_i5;
+    input fabric_spi_powerdown_cycle_i6;
+    input fabric_spi_powerdown_cycle_i7;
+    input fabric_spi_powerdown_cycle_i8;
+    input fabric_spi_powerdown_cycle_i9;
+    input fabric_spi_powerup_cycle_i1;
+    input fabric_spi_powerup_cycle_i10;
+    input fabric_spi_powerup_cycle_i11;
+    input fabric_spi_powerup_cycle_i12;
+    input fabric_spi_powerup_cycle_i13;
+    input fabric_spi_powerup_cycle_i14;
+    input fabric_spi_powerup_cycle_i15;
+    input fabric_spi_powerup_cycle_i16;
+    input fabric_spi_powerup_cycle_i17;
+    input fabric_spi_powerup_cycle_i18;
+    input fabric_spi_powerup_cycle_i19;
+    input fabric_spi_powerup_cycle_i2;
+    input fabric_spi_powerup_cycle_i20;
+    input fabric_spi_powerup_cycle_i21;
+    input fabric_spi_powerup_cycle_i22;
+    input fabric_spi_powerup_cycle_i23;
+    input fabric_spi_powerup_cycle_i24;
+    input fabric_spi_powerup_cycle_i25;
+    input fabric_spi_powerup_cycle_i26;
+    input fabric_spi_powerup_cycle_i27;
+    input fabric_spi_powerup_cycle_i28;
+    input fabric_spi_powerup_cycle_i29;
+    input fabric_spi_powerup_cycle_i3;
+    input fabric_spi_powerup_cycle_i30;
+    input fabric_spi_powerup_cycle_i31;
+    input fabric_spi_powerup_cycle_i32;
+    input fabric_spi_powerup_cycle_i33;
+    input fabric_spi_powerup_cycle_i34;
+    input fabric_spi_powerup_cycle_i35;
+    input fabric_spi_powerup_cycle_i36;
+    input fabric_spi_powerup_cycle_i37;
+    input fabric_spi_powerup_cycle_i38;
+    input fabric_spi_powerup_cycle_i39;
+    input fabric_spi_powerup_cycle_i4;
+    input fabric_spi_powerup_cycle_i40;
+    input fabric_spi_powerup_cycle_i41;
+    input fabric_spi_powerup_cycle_i42;
+    input fabric_spi_powerup_cycle_i43;
+    input fabric_spi_powerup_cycle_i44;
+    input fabric_spi_powerup_cycle_i45;
+    input fabric_spi_powerup_cycle_i46;
+    input fabric_spi_powerup_cycle_i47;
+    input fabric_spi_powerup_cycle_i48;
+    input fabric_spi_powerup_cycle_i5;
+    input fabric_spi_powerup_cycle_i6;
+    input fabric_spi_powerup_cycle_i7;
+    input fabric_spi_powerup_cycle_i8;
+    input fabric_spi_powerup_cycle_i9;
+    input fabric_spi_rst_n_i1;
+    input fabric_spi_rst_n_i2;
+    input fabric_spi_rst_n_i3;
+    input fabric_spi_sck_i0;
+    input fabric_spi_sck_i1;
+    input fabric_spi_sck_i2;
+    input fabric_spi_vcc_enable_i1;
+    input fabric_spi_vcc_enable_i2;
+    input fabric_spi_vcc_enable_i3;
+    output fabric_spi_vcc_used_o1;
+    output fabric_spi_vcc_used_o2;
+    output fabric_spi_vcc_used_o3;
+    input fabric_spw0_apb_slv_paddr_i1;
+    input fabric_spw0_apb_slv_paddr_i2;
+    input fabric_spw0_apb_slv_paddr_i3;
+    input fabric_spw0_apb_slv_paddr_i4;
+    input fabric_spw0_apb_slv_paddr_i5;
+    input fabric_spw0_apb_slv_penable_i;
+    output fabric_spw0_apb_slv_prdata_o1;
+    output fabric_spw0_apb_slv_prdata_o10;
+    output fabric_spw0_apb_slv_prdata_o11;
+    output fabric_spw0_apb_slv_prdata_o12;
+    output fabric_spw0_apb_slv_prdata_o13;
+    output fabric_spw0_apb_slv_prdata_o14;
+    output fabric_spw0_apb_slv_prdata_o15;
+    output fabric_spw0_apb_slv_prdata_o16;
+    output fabric_spw0_apb_slv_prdata_o17;
+    output fabric_spw0_apb_slv_prdata_o18;
+    output fabric_spw0_apb_slv_prdata_o19;
+    output fabric_spw0_apb_slv_prdata_o2;
+    output fabric_spw0_apb_slv_prdata_o20;
+    output fabric_spw0_apb_slv_prdata_o21;
+    output fabric_spw0_apb_slv_prdata_o22;
+    output fabric_spw0_apb_slv_prdata_o23;
+    output fabric_spw0_apb_slv_prdata_o24;
+    output fabric_spw0_apb_slv_prdata_o25;
+    output fabric_spw0_apb_slv_prdata_o26;
+    output fabric_spw0_apb_slv_prdata_o27;
+    output fabric_spw0_apb_slv_prdata_o28;
+    output fabric_spw0_apb_slv_prdata_o29;
+    output fabric_spw0_apb_slv_prdata_o3;
+    output fabric_spw0_apb_slv_prdata_o30;
+    output fabric_spw0_apb_slv_prdata_o31;
+    output fabric_spw0_apb_slv_prdata_o4;
+    output fabric_spw0_apb_slv_prdata_o5;
+    output fabric_spw0_apb_slv_prdata_o6;
+    output fabric_spw0_apb_slv_prdata_o7;
+    output fabric_spw0_apb_slv_prdata_o8;
+    output fabric_spw0_apb_slv_prdata_o9;
+    output fabric_spw0_apb_slv_pready_o;
+    input fabric_spw0_apb_slv_psel_i;
+    output fabric_spw0_apb_slv_pslverr_o;
+    input fabric_spw0_apb_slv_pwdata_i1;
+    input fabric_spw0_apb_slv_pwdata_i10;
+    input fabric_spw0_apb_slv_pwdata_i11;
+    input fabric_spw0_apb_slv_pwdata_i12;
+    input fabric_spw0_apb_slv_pwdata_i13;
+    input fabric_spw0_apb_slv_pwdata_i14;
+    input fabric_spw0_apb_slv_pwdata_i15;
+    input fabric_spw0_apb_slv_pwdata_i16;
+    input fabric_spw0_apb_slv_pwdata_i17;
+    input fabric_spw0_apb_slv_pwdata_i18;
+    input fabric_spw0_apb_slv_pwdata_i19;
+    input fabric_spw0_apb_slv_pwdata_i2;
+    input fabric_spw0_apb_slv_pwdata_i20;
+    input fabric_spw0_apb_slv_pwdata_i21;
+    input fabric_spw0_apb_slv_pwdata_i22;
+    input fabric_spw0_apb_slv_pwdata_i23;
+    input fabric_spw0_apb_slv_pwdata_i24;
+    input fabric_spw0_apb_slv_pwdata_i25;
+    input fabric_spw0_apb_slv_pwdata_i26;
+    input fabric_spw0_apb_slv_pwdata_i27;
+    input fabric_spw0_apb_slv_pwdata_i28;
+    input fabric_spw0_apb_slv_pwdata_i29;
+    input fabric_spw0_apb_slv_pwdata_i3;
+    input fabric_spw0_apb_slv_pwdata_i30;
+    input fabric_spw0_apb_slv_pwdata_i31;
+    input fabric_spw0_apb_slv_pwdata_i4;
+    input fabric_spw0_apb_slv_pwdata_i5;
+    input fabric_spw0_apb_slv_pwdata_i6;
+    input fabric_spw0_apb_slv_pwdata_i7;
+    input fabric_spw0_apb_slv_pwdata_i8;
+    input fabric_spw0_apb_slv_pwdata_i9;
+    input fabric_spw0_apb_slv_pwrite_i;
+    input fabric_spw0_clk_i;
+    input fabric_spw0_clk_tx_i;
+    input fabric_spw0_rst_n_i;
+    output fabric_spw0_rx_fifo_data_o1;
+    output fabric_spw0_rx_fifo_data_o2;
+    output fabric_spw0_rx_fifo_data_o3;
+    output fabric_spw0_rx_fifo_data_o4;
+    output fabric_spw0_rx_fifo_data_o5;
+    output fabric_spw0_rx_fifo_data_o6;
+    output fabric_spw0_rx_fifo_data_o7;
+    output fabric_spw0_rx_fifo_data_o8;
+    output fabric_spw0_rx_fifo_data_o9;
+    output fabric_spw0_rx_fifo_empty_o;
+    input fabric_spw0_rx_fifo_read_i;
+    input fabric_spw0_tick_ctm_i;
+    output fabric_spw0_tick_ctm_o;
+    input fabric_spw0_tx_fifo_data_i1;
+    input fabric_spw0_tx_fifo_data_i2;
+    input fabric_spw0_tx_fifo_data_i3;
+    input fabric_spw0_tx_fifo_data_i4;
+    input fabric_spw0_tx_fifo_data_i5;
+    input fabric_spw0_tx_fifo_data_i6;
+    input fabric_spw0_tx_fifo_data_i7;
+    input fabric_spw0_tx_fifo_data_i8;
+    input fabric_spw0_tx_fifo_data_i9;
+    output fabric_spw0_tx_fifo_full_o;
+    input fabric_spw0_tx_fifo_write_i;
+    output fabric_spw0_user_shared_o;
+    input fabric_spw1_apb_slv_paddr_i1;
+    input fabric_spw1_apb_slv_paddr_i2;
+    input fabric_spw1_apb_slv_paddr_i3;
+    input fabric_spw1_apb_slv_paddr_i4;
+    input fabric_spw1_apb_slv_paddr_i5;
+    input fabric_spw1_apb_slv_penable_i;
+    output fabric_spw1_apb_slv_prdata_o1;
+    output fabric_spw1_apb_slv_prdata_o10;
+    output fabric_spw1_apb_slv_prdata_o11;
+    output fabric_spw1_apb_slv_prdata_o12;
+    output fabric_spw1_apb_slv_prdata_o13;
+    output fabric_spw1_apb_slv_prdata_o14;
+    output fabric_spw1_apb_slv_prdata_o15;
+    output fabric_spw1_apb_slv_prdata_o16;
+    output fabric_spw1_apb_slv_prdata_o17;
+    output fabric_spw1_apb_slv_prdata_o18;
+    output fabric_spw1_apb_slv_prdata_o19;
+    output fabric_spw1_apb_slv_prdata_o2;
+    output fabric_spw1_apb_slv_prdata_o20;
+    output fabric_spw1_apb_slv_prdata_o21;
+    output fabric_spw1_apb_slv_prdata_o22;
+    output fabric_spw1_apb_slv_prdata_o23;
+    output fabric_spw1_apb_slv_prdata_o24;
+    output fabric_spw1_apb_slv_prdata_o25;
+    output fabric_spw1_apb_slv_prdata_o26;
+    output fabric_spw1_apb_slv_prdata_o27;
+    output fabric_spw1_apb_slv_prdata_o28;
+    output fabric_spw1_apb_slv_prdata_o29;
+    output fabric_spw1_apb_slv_prdata_o3;
+    output fabric_spw1_apb_slv_prdata_o30;
+    output fabric_spw1_apb_slv_prdata_o31;
+    output fabric_spw1_apb_slv_prdata_o4;
+    output fabric_spw1_apb_slv_prdata_o5;
+    output fabric_spw1_apb_slv_prdata_o6;
+    output fabric_spw1_apb_slv_prdata_o7;
+    output fabric_spw1_apb_slv_prdata_o8;
+    output fabric_spw1_apb_slv_prdata_o9;
+    output fabric_spw1_apb_slv_pready_o;
+    input fabric_spw1_apb_slv_psel_i;
+    output fabric_spw1_apb_slv_pslverr_o;
+    input fabric_spw1_apb_slv_pwdata_i1;
+    input fabric_spw1_apb_slv_pwdata_i10;
+    input fabric_spw1_apb_slv_pwdata_i11;
+    input fabric_spw1_apb_slv_pwdata_i12;
+    input fabric_spw1_apb_slv_pwdata_i13;
+    input fabric_spw1_apb_slv_pwdata_i14;
+    input fabric_spw1_apb_slv_pwdata_i15;
+    input fabric_spw1_apb_slv_pwdata_i16;
+    input fabric_spw1_apb_slv_pwdata_i17;
+    input fabric_spw1_apb_slv_pwdata_i18;
+    input fabric_spw1_apb_slv_pwdata_i19;
+    input fabric_spw1_apb_slv_pwdata_i2;
+    input fabric_spw1_apb_slv_pwdata_i20;
+    input fabric_spw1_apb_slv_pwdata_i21;
+    input fabric_spw1_apb_slv_pwdata_i22;
+    input fabric_spw1_apb_slv_pwdata_i23;
+    input fabric_spw1_apb_slv_pwdata_i24;
+    input fabric_spw1_apb_slv_pwdata_i25;
+    input fabric_spw1_apb_slv_pwdata_i26;
+    input fabric_spw1_apb_slv_pwdata_i27;
+    input fabric_spw1_apb_slv_pwdata_i28;
+    input fabric_spw1_apb_slv_pwdata_i29;
+    input fabric_spw1_apb_slv_pwdata_i3;
+    input fabric_spw1_apb_slv_pwdata_i30;
+    input fabric_spw1_apb_slv_pwdata_i31;
+    input fabric_spw1_apb_slv_pwdata_i4;
+    input fabric_spw1_apb_slv_pwdata_i5;
+    input fabric_spw1_apb_slv_pwdata_i6;
+    input fabric_spw1_apb_slv_pwdata_i7;
+    input fabric_spw1_apb_slv_pwdata_i8;
+    input fabric_spw1_apb_slv_pwdata_i9;
+    input fabric_spw1_apb_slv_pwrite_i;
+    input fabric_spw1_clk_i;
+    input fabric_spw1_clk_tx_i;
+    input fabric_spw1_rst_n_i;
+    output fabric_spw1_rx_fifo_data_o1;
+    output fabric_spw1_rx_fifo_data_o2;
+    output fabric_spw1_rx_fifo_data_o3;
+    output fabric_spw1_rx_fifo_data_o4;
+    output fabric_spw1_rx_fifo_data_o5;
+    output fabric_spw1_rx_fifo_data_o6;
+    output fabric_spw1_rx_fifo_data_o7;
+    output fabric_spw1_rx_fifo_data_o8;
+    output fabric_spw1_rx_fifo_data_o9;
+    output fabric_spw1_rx_fifo_empty_o;
+    input fabric_spw1_rx_fifo_read_i;
+    input fabric_spw1_tick_ctm_i;
+    output fabric_spw1_tick_ctm_o;
+    input fabric_spw1_tx_fifo_data_i1;
+    input fabric_spw1_tx_fifo_data_i2;
+    input fabric_spw1_tx_fifo_data_i3;
+    input fabric_spw1_tx_fifo_data_i4;
+    input fabric_spw1_tx_fifo_data_i5;
+    input fabric_spw1_tx_fifo_data_i6;
+    input fabric_spw1_tx_fifo_data_i7;
+    input fabric_spw1_tx_fifo_data_i8;
+    input fabric_spw1_tx_fifo_data_i9;
+    output fabric_spw1_tx_fifo_full_o;
+    input fabric_spw1_tx_fifo_write_i;
+    output fabric_spw1_user_shared_o;
+    output fabric_status_cold_start_o;
+    input fabric_thsens_arst_tmr_n_i1;
+    input fabric_thsens_arst_tmr_n_i2;
+    input fabric_thsens_arst_tmr_n_i3;
+    input fabric_thsens_clk_div_ratio_i1;
+    input fabric_thsens_clk_div_ratio_i2;
+    input fabric_thsens_clk_div_ratio_i3;
+    input fabric_thsens_clk_div_ratio_i4;
+    input fabric_thsens_clk_div_ratio_i5;
+    input fabric_thsens_clk_div_ratio_i6;
+    input fabric_thsens_clk_div_ratio_i7;
+    input fabric_thsens_clk_div_ratio_i8;
+    input fabric_thsens_clk_i;
+    output fabric_thsens_fm_config_r_o1;
+    output fabric_thsens_fm_config_r_o10;
+    output fabric_thsens_fm_config_r_o11;
+    output fabric_thsens_fm_config_r_o12;
+    output fabric_thsens_fm_config_r_o13;
+    output fabric_thsens_fm_config_r_o14;
+    output fabric_thsens_fm_config_r_o15;
+    output fabric_thsens_fm_config_r_o16;
+    output fabric_thsens_fm_config_r_o17;
+    output fabric_thsens_fm_config_r_o18;
+    output fabric_thsens_fm_config_r_o19;
+    output fabric_thsens_fm_config_r_o2;
+    output fabric_thsens_fm_config_r_o20;
+    output fabric_thsens_fm_config_r_o21;
+    output fabric_thsens_fm_config_r_o22;
+    output fabric_thsens_fm_config_r_o23;
+    output fabric_thsens_fm_config_r_o24;
+    output fabric_thsens_fm_config_r_o25;
+    output fabric_thsens_fm_config_r_o26;
+    output fabric_thsens_fm_config_r_o27;
+    output fabric_thsens_fm_config_r_o3;
+    output fabric_thsens_fm_config_r_o4;
+    output fabric_thsens_fm_config_r_o5;
+    output fabric_thsens_fm_config_r_o6;
+    output fabric_thsens_fm_config_r_o7;
+    output fabric_thsens_fm_config_r_o8;
+    output fabric_thsens_fm_config_r_o9;
+    input fabric_thsens_fm_config_w_i1;
+    input fabric_thsens_fm_config_w_i10;
+    input fabric_thsens_fm_config_w_i11;
+    input fabric_thsens_fm_config_w_i12;
+    input fabric_thsens_fm_config_w_i13;
+    input fabric_thsens_fm_config_w_i14;
+    input fabric_thsens_fm_config_w_i15;
+    input fabric_thsens_fm_config_w_i16;
+    input fabric_thsens_fm_config_w_i17;
+    input fabric_thsens_fm_config_w_i18;
+    input fabric_thsens_fm_config_w_i19;
+    input fabric_thsens_fm_config_w_i2;
+    input fabric_thsens_fm_config_w_i20;
+    input fabric_thsens_fm_config_w_i21;
+    input fabric_thsens_fm_config_w_i22;
+    input fabric_thsens_fm_config_w_i23;
+    input fabric_thsens_fm_config_w_i24;
+    input fabric_thsens_fm_config_w_i25;
+    input fabric_thsens_fm_config_w_i26;
+    input fabric_thsens_fm_config_w_i27;
+    input fabric_thsens_fm_config_w_i3;
+    input fabric_thsens_fm_config_w_i4;
+    input fabric_thsens_fm_config_w_i5;
+    input fabric_thsens_fm_config_w_i6;
+    input fabric_thsens_fm_config_w_i7;
+    input fabric_thsens_fm_config_w_i8;
+    input fabric_thsens_fm_config_w_i9;
+    input fabric_thsens_fm_config_wen_i;
+    output fabric_thsens_fm_data_o1;
+    output fabric_thsens_fm_data_o10;
+    output fabric_thsens_fm_data_o11;
+    output fabric_thsens_fm_data_o12;
+    output fabric_thsens_fm_data_o13;
+    output fabric_thsens_fm_data_o14;
+    output fabric_thsens_fm_data_o2;
+    output fabric_thsens_fm_data_o3;
+    output fabric_thsens_fm_data_o4;
+    output fabric_thsens_fm_data_o5;
+    output fabric_thsens_fm_data_o6;
+    output fabric_thsens_fm_data_o7;
+    output fabric_thsens_fm_data_o8;
+    output fabric_thsens_fm_data_o9;
+    input fabric_thsens_fm_enable_i;
+    output fabric_thsens_fm_mode_r_o1;
+    output fabric_thsens_fm_mode_r_o10;
+    output fabric_thsens_fm_mode_r_o11;
+    output fabric_thsens_fm_mode_r_o12;
+    output fabric_thsens_fm_mode_r_o13;
+    output fabric_thsens_fm_mode_r_o14;
+    output fabric_thsens_fm_mode_r_o15;
+    output fabric_thsens_fm_mode_r_o16;
+    output fabric_thsens_fm_mode_r_o17;
+    output fabric_thsens_fm_mode_r_o18;
+    output fabric_thsens_fm_mode_r_o19;
+    output fabric_thsens_fm_mode_r_o2;
+    output fabric_thsens_fm_mode_r_o20;
+    output fabric_thsens_fm_mode_r_o21;
+    output fabric_thsens_fm_mode_r_o22;
+    output fabric_thsens_fm_mode_r_o23;
+    output fabric_thsens_fm_mode_r_o24;
+    output fabric_thsens_fm_mode_r_o25;
+    output fabric_thsens_fm_mode_r_o26;
+    output fabric_thsens_fm_mode_r_o27;
+    output fabric_thsens_fm_mode_r_o28;
+    output fabric_thsens_fm_mode_r_o29;
+    output fabric_thsens_fm_mode_r_o3;
+    output fabric_thsens_fm_mode_r_o30;
+    output fabric_thsens_fm_mode_r_o31;
+    output fabric_thsens_fm_mode_r_o32;
+    output fabric_thsens_fm_mode_r_o4;
+    output fabric_thsens_fm_mode_r_o5;
+    output fabric_thsens_fm_mode_r_o6;
+    output fabric_thsens_fm_mode_r_o7;
+    output fabric_thsens_fm_mode_r_o8;
+    output fabric_thsens_fm_mode_r_o9;
+    input fabric_thsens_fm_mode_w_i1;
+    input fabric_thsens_fm_mode_w_i10;
+    input fabric_thsens_fm_mode_w_i11;
+    input fabric_thsens_fm_mode_w_i12;
+    input fabric_thsens_fm_mode_w_i13;
+    input fabric_thsens_fm_mode_w_i14;
+    input fabric_thsens_fm_mode_w_i15;
+    input fabric_thsens_fm_mode_w_i16;
+    input fabric_thsens_fm_mode_w_i17;
+    input fabric_thsens_fm_mode_w_i18;
+    input fabric_thsens_fm_mode_w_i19;
+    input fabric_thsens_fm_mode_w_i2;
+    input fabric_thsens_fm_mode_w_i20;
+    input fabric_thsens_fm_mode_w_i21;
+    input fabric_thsens_fm_mode_w_i22;
+    input fabric_thsens_fm_mode_w_i23;
+    input fabric_thsens_fm_mode_w_i24;
+    input fabric_thsens_fm_mode_w_i25;
+    input fabric_thsens_fm_mode_w_i26;
+    input fabric_thsens_fm_mode_w_i27;
+    input fabric_thsens_fm_mode_w_i28;
+    input fabric_thsens_fm_mode_w_i29;
+    input fabric_thsens_fm_mode_w_i3;
+    input fabric_thsens_fm_mode_w_i30;
+    input fabric_thsens_fm_mode_w_i31;
+    input fabric_thsens_fm_mode_w_i32;
+    input fabric_thsens_fm_mode_w_i4;
+    input fabric_thsens_fm_mode_w_i5;
+    input fabric_thsens_fm_mode_w_i6;
+    input fabric_thsens_fm_mode_w_i7;
+    input fabric_thsens_fm_mode_w_i8;
+    input fabric_thsens_fm_mode_w_i9;
+    input fabric_thsens_fm_mode_wen_i;
+    output fabric_thsens_fm_overflow_o;
+    output fabric_thsens_fm_valid_o;
+    output fabric_thsens_otp_config_o1;
+    output fabric_thsens_otp_config_o10;
+    output fabric_thsens_otp_config_o11;
+    output fabric_thsens_otp_config_o12;
+    output fabric_thsens_otp_config_o13;
+    output fabric_thsens_otp_config_o14;
+    output fabric_thsens_otp_config_o15;
+    output fabric_thsens_otp_config_o16;
+    output fabric_thsens_otp_config_o17;
+    output fabric_thsens_otp_config_o18;
+    output fabric_thsens_otp_config_o19;
+    output fabric_thsens_otp_config_o2;
+    output fabric_thsens_otp_config_o20;
+    output fabric_thsens_otp_config_o21;
+    output fabric_thsens_otp_config_o22;
+    output fabric_thsens_otp_config_o23;
+    output fabric_thsens_otp_config_o24;
+    output fabric_thsens_otp_config_o25;
+    output fabric_thsens_otp_config_o26;
+    output fabric_thsens_otp_config_o27;
+    output fabric_thsens_otp_config_o3;
+    output fabric_thsens_otp_config_o4;
+    output fabric_thsens_otp_config_o5;
+    output fabric_thsens_otp_config_o6;
+    output fabric_thsens_otp_config_o7;
+    output fabric_thsens_otp_config_o8;
+    output fabric_thsens_otp_config_o9;
+    input fabric_user_clk_i;
+    input fabric_user_data_i1;
+    input fabric_user_data_i10;
+    input fabric_user_data_i11;
+    input fabric_user_data_i12;
+    input fabric_user_data_i13;
+    input fabric_user_data_i14;
+    input fabric_user_data_i15;
+    input fabric_user_data_i16;
+    input fabric_user_data_i17;
+    input fabric_user_data_i18;
+    input fabric_user_data_i19;
+    input fabric_user_data_i2;
+    input fabric_user_data_i20;
+    input fabric_user_data_i21;
+    input fabric_user_data_i22;
+    input fabric_user_data_i23;
+    input fabric_user_data_i24;
+    input fabric_user_data_i25;
+    input fabric_user_data_i26;
+    input fabric_user_data_i27;
+    input fabric_user_data_i28;
+    input fabric_user_data_i29;
+    input fabric_user_data_i3;
+    input fabric_user_data_i30;
+    input fabric_user_data_i31;
+    input fabric_user_data_i32;
+    input fabric_user_data_i4;
+    input fabric_user_data_i5;
+    input fabric_user_data_i6;
+    input fabric_user_data_i7;
+    input fabric_user_data_i8;
+    input fabric_user_data_i9;
+    output fabric_user_data_o1;
+    output fabric_user_data_o10;
+    output fabric_user_data_o11;
+    output fabric_user_data_o12;
+    output fabric_user_data_o13;
+    output fabric_user_data_o14;
+    output fabric_user_data_o15;
+    output fabric_user_data_o16;
+    output fabric_user_data_o17;
+    output fabric_user_data_o18;
+    output fabric_user_data_o19;
+    output fabric_user_data_o2;
+    output fabric_user_data_o20;
+    output fabric_user_data_o21;
+    output fabric_user_data_o22;
+    output fabric_user_data_o23;
+    output fabric_user_data_o24;
+    output fabric_user_data_o25;
+    output fabric_user_data_o26;
+    output fabric_user_data_o27;
+    output fabric_user_data_o28;
+    output fabric_user_data_o29;
+    output fabric_user_data_o3;
+    output fabric_user_data_o30;
+    output fabric_user_data_o31;
+    output fabric_user_data_o32;
+    output fabric_user_data_o4;
+    output fabric_user_data_o5;
+    output fabric_user_data_o6;
+    output fabric_user_data_o7;
+    output fabric_user_data_o8;
+    output fabric_user_data_o9;
+    output fabric_user_read_cycle_o;
+    output fabric_user_write_cycle_o;
+    parameter bsm_config = 0;
+endmodule
+
+(* blackbox *)
+module NX_SERVICE_IF_U_FULL(fabric_mrepair_clk_i, fabric_clk_otp_mrepair_o, fabric_mrepair_cke_i, fabric_mrepair_por_i, fabric_mrepair_cke_force_i, fabric_mrepair_rst_n_i, fabric_mrepair_initn_i, fabric_mrepair_data_from_bist_i1, fabric_mrepair_data_from_bist_i2, fabric_mrepair_data_from_bist_i3, fabric_mrepair_data_from_bist_i4, fabric_mrepair_data_from_bist_i5, fabric_mrepair_data_from_bist_i6, fabric_mrepair_data_from_bist_i7, fabric_mrepair_data_from_bist_i8, fabric_mrepair_data_from_bist_i9, fabric_mrepair_data_from_bist_i10, fabric_mrepair_data_from_bist_i11, fabric_mrepair_data_from_bist_i12, fabric_mrepair_data_from_bist_i13, fabric_mrepair_data_from_bist_i14
+, fabric_mrepair_data_from_bist_i15, fabric_mrepair_data_from_bist_i16, fabric_mrepair_data_from_bist_i17, fabric_mrepair_data_from_bist_i18, fabric_mrepair_data_from_bist_i19, fabric_mrepair_data_from_bist_i20, fabric_mrepair_data_from_bist_i21, fabric_mrepair_data_from_bist_i22, fabric_mrepair_data_from_bist_i23, fabric_mrepair_data_from_bist_i24, fabric_mrepair_data_from_bist_i25, fabric_mrepair_data_from_bist_i26, fabric_mrepair_data_to_bist_o1, fabric_mrepair_data_to_bist_o2, fabric_mrepair_data_to_bist_o3, fabric_mrepair_data_to_bist_o4, fabric_mrepair_data_to_bist_o5, fabric_mrepair_data_to_bist_o6, fabric_mrepair_data_to_bist_o7, fabric_mrepair_data_to_bist_o8, fabric_mrepair_data_to_bist_o9
+, fabric_mrepair_data_to_bist_o10, fabric_mrepair_data_to_bist_o11, fabric_mrepair_data_to_bist_o12, fabric_mrepair_data_to_bist_o13, fabric_mrepair_data_to_bist_o14, fabric_mrepair_data_to_bist_o15, fabric_mrepair_data_to_bist_o16, fabric_mrepair_data_to_bist_o17, fabric_mrepair_data_to_bist_o18, fabric_mrepair_data_to_bist_o19, fabric_mrepair_data_to_bist_o20, fabric_mrepair_data_to_bist_o21, fabric_mrepair_data_to_bist_o22, fabric_mrepair_data_to_bist_o23, fabric_mrepair_data_to_bist_o24, fabric_mrepair_data_to_bist_o25, fabric_mrepair_data_to_bist_o26, fabric_mrepair_shift_en_to_bist_o1, fabric_mrepair_shift_en_to_bist_o2, fabric_mrepair_shift_en_to_bist_o3, fabric_mrepair_shift_en_to_bist_o4
+, fabric_mrepair_shift_en_to_bist_o5, fabric_mrepair_shift_en_to_bist_o6, fabric_mrepair_shift_en_to_bist_o7, fabric_mrepair_shift_en_to_bist_o8, fabric_mrepair_shift_en_to_bist_o9, fabric_mrepair_shift_en_to_bist_o10, fabric_mrepair_shift_en_to_bist_o11, fabric_mrepair_shift_en_to_bist_o12, fabric_mrepair_shift_en_to_bist_o13, fabric_mrepair_shift_en_to_bist_o14, fabric_mrepair_shift_en_to_bist_o15, fabric_mrepair_shift_en_to_bist_o16, fabric_mrepair_shift_en_to_bist_o17, fabric_mrepair_shift_en_to_bist_o18, fabric_mrepair_shift_en_to_bist_o19, fabric_mrepair_shift_en_to_bist_o20, fabric_mrepair_shift_en_to_bist_o21, fabric_mrepair_shift_en_to_bist_o22, fabric_mrepair_shift_en_to_bist_o23, fabric_mrepair_shift_en_to_bist_o24, fabric_mrepair_shift_en_to_bist_o25
+, fabric_mrepair_shift_en_to_bist_o26, fabric_mrepair_sif_load_en_to_bist_o1, fabric_mrepair_sif_load_en_to_bist_o2, fabric_mrepair_sif_load_en_to_bist_o3, fabric_mrepair_sif_load_en_to_bist_o4, fabric_mrepair_sif_load_en_to_bist_o5, fabric_mrepair_sif_load_en_to_bist_o6, fabric_mrepair_sif_load_en_to_bist_o7, fabric_mrepair_sif_load_en_to_bist_o8, fabric_mrepair_sif_load_en_to_bist_o9, fabric_mrepair_sif_load_en_to_bist_o10, fabric_mrepair_sif_load_en_to_bist_o11, fabric_mrepair_sif_load_en_to_bist_o12, fabric_mrepair_sif_load_en_to_bist_o13, fabric_mrepair_sif_load_en_to_bist_o14, fabric_mrepair_sif_load_en_to_bist_o15, fabric_mrepair_sif_load_en_to_bist_o16, fabric_mrepair_sif_load_en_to_bist_o17, fabric_mrepair_sif_load_en_to_bist_o18, fabric_mrepair_sif_load_en_to_bist_o19, fabric_mrepair_sif_load_en_to_bist_o20
+, fabric_mrepair_sif_load_en_to_bist_o21, fabric_mrepair_sif_load_en_to_bist_o22, fabric_mrepair_sif_load_en_to_bist_o23, fabric_mrepair_sif_load_en_to_bist_o24, fabric_mrepair_sif_load_en_to_bist_o25, fabric_mrepair_sif_load_en_to_bist_o26, fabric_mrepair_sif_update_en_to_bist_o1, fabric_mrepair_sif_update_en_to_bist_o2, fabric_mrepair_sif_update_en_to_bist_o3, fabric_mrepair_sif_update_en_to_bist_o4, fabric_mrepair_sif_update_en_to_bist_o5, fabric_mrepair_sif_update_en_to_bist_o6, fabric_mrepair_sif_update_en_to_bist_o7, fabric_mrepair_sif_update_en_to_bist_o8, fabric_mrepair_sif_update_en_to_bist_o9, fabric_mrepair_sif_update_en_to_bist_o10, fabric_mrepair_sif_update_en_to_bist_o11, fabric_mrepair_sif_update_en_to_bist_o12, fabric_mrepair_sif_update_en_to_bist_o13, fabric_mrepair_sif_update_en_to_bist_o14, fabric_mrepair_sif_update_en_to_bist_o15
+, fabric_mrepair_sif_update_en_to_bist_o16, fabric_mrepair_sif_update_en_to_bist_o17, fabric_mrepair_sif_update_en_to_bist_o18, fabric_mrepair_sif_update_en_to_bist_o19, fabric_mrepair_sif_update_en_to_bist_o20, fabric_mrepair_sif_update_en_to_bist_o21, fabric_mrepair_sif_update_en_to_bist_o22, fabric_mrepair_sif_update_en_to_bist_o23, fabric_mrepair_sif_update_en_to_bist_o24, fabric_mrepair_sif_update_en_to_bist_o25, fabric_mrepair_sif_update_en_to_bist_o26, fabric_mrepair_sif_reg_en_to_bist_o1, fabric_mrepair_sif_reg_en_to_bist_o2, fabric_mrepair_sif_reg_en_to_bist_o3, fabric_mrepair_sif_reg_en_to_bist_o4, fabric_mrepair_sif_reg_en_to_bist_o5, fabric_mrepair_sif_reg_en_to_bist_o6, fabric_mrepair_sif_reg_en_to_bist_o7, fabric_mrepair_sif_reg_en_to_bist_o8, fabric_mrepair_sif_reg_en_to_bist_o9, fabric_mrepair_sif_reg_en_to_bist_o10
+, fabric_mrepair_sif_reg_en_to_bist_o11, fabric_mrepair_sif_reg_en_to_bist_o12, fabric_mrepair_sif_reg_en_to_bist_o13, fabric_mrepair_sif_reg_en_to_bist_o14, fabric_mrepair_sif_reg_en_to_bist_o15, fabric_mrepair_sif_reg_en_to_bist_o16, fabric_mrepair_sif_reg_en_to_bist_o17, fabric_mrepair_sif_reg_en_to_bist_o18, fabric_mrepair_sif_reg_en_to_bist_o19, fabric_mrepair_sif_reg_en_to_bist_o20, fabric_mrepair_sif_reg_en_to_bist_o21, fabric_mrepair_sif_reg_en_to_bist_o22, fabric_mrepair_sif_reg_en_to_bist_o23, fabric_mrepair_sif_reg_en_to_bist_o24, fabric_mrepair_sif_reg_en_to_bist_o25, fabric_mrepair_sif_reg_en_to_bist_o26, fabric_mrepair_system_data_to_mem_bist_i1, fabric_mrepair_system_data_to_mem_bist_i2, fabric_mrepair_system_data_to_mem_bist_i3, fabric_mrepair_system_data_to_mem_bist_i4, fabric_mrepair_system_data_to_mem_bist_i5
+, fabric_mrepair_system_data_to_mem_bist_i6, fabric_mrepair_system_data_to_mem_bist_i7, fabric_mrepair_system_data_to_mem_bist_i8, fabric_mrepair_system_data_to_mem_bist_i9, fabric_mrepair_system_data_to_mem_bist_i10, fabric_mrepair_system_data_to_mem_bist_i11, fabric_mrepair_system_data_to_mem_bist_i12, fabric_mrepair_system_data_to_mem_bist_i13, fabric_mrepair_system_data_to_mem_bist_i14, fabric_mrepair_system_data_to_mem_bist_i15, fabric_mrepair_system_data_to_mem_bist_i16, fabric_mrepair_system_data_to_mem_bist_i17, fabric_mrepair_system_data_to_mem_bist_i18, fabric_mrepair_system_data_to_mem_bist_i19, fabric_mrepair_system_data_to_mem_bist_i20, fabric_mrepair_system_data_to_mem_bist_i21, fabric_mrepair_system_data_to_mem_bist_i22, fabric_mrepair_system_data_to_mem_bist_i23, fabric_mrepair_system_data_to_mem_bist_i24, fabric_mrepair_system_data_to_mem_bist_i25, fabric_mrepair_system_data_to_mem_bist_i26
+, fabric_mrepair_shift_en_i1, fabric_mrepair_shift_en_i2, fabric_mrepair_shift_en_i3, fabric_mrepair_shift_en_i4, fabric_mrepair_shift_en_i5, fabric_mrepair_shift_en_i6, fabric_mrepair_shift_en_i7, fabric_mrepair_shift_en_i8, fabric_mrepair_shift_en_i9, fabric_mrepair_shift_en_i10, fabric_mrepair_shift_en_i11, fabric_mrepair_shift_en_i12, fabric_mrepair_shift_en_i13, fabric_mrepair_shift_en_i14, fabric_mrepair_shift_en_i15, fabric_mrepair_shift_en_i16, fabric_mrepair_shift_en_i17, fabric_mrepair_shift_en_i18, fabric_mrepair_shift_en_i19, fabric_mrepair_shift_en_i20, fabric_mrepair_shift_en_i21
+, fabric_mrepair_shift_en_i22, fabric_mrepair_shift_en_i23, fabric_mrepair_shift_en_i24, fabric_mrepair_shift_en_i25, fabric_mrepair_shift_en_i26, fabric_mrepair_sif_load_en_i1, fabric_mrepair_sif_load_en_i2, fabric_mrepair_sif_load_en_i3, fabric_mrepair_sif_load_en_i4, fabric_mrepair_sif_load_en_i5, fabric_mrepair_sif_load_en_i6, fabric_mrepair_sif_load_en_i7, fabric_mrepair_sif_load_en_i8, fabric_mrepair_sif_load_en_i9, fabric_mrepair_sif_load_en_i10, fabric_mrepair_sif_load_en_i11, fabric_mrepair_sif_load_en_i12, fabric_mrepair_sif_load_en_i13, fabric_mrepair_sif_load_en_i14, fabric_mrepair_sif_load_en_i15, fabric_mrepair_sif_load_en_i16
+, fabric_mrepair_sif_load_en_i17, fabric_mrepair_sif_load_en_i18, fabric_mrepair_sif_load_en_i19, fabric_mrepair_sif_load_en_i20, fabric_mrepair_sif_load_en_i21, fabric_mrepair_sif_load_en_i22, fabric_mrepair_sif_load_en_i23, fabric_mrepair_sif_load_en_i24, fabric_mrepair_sif_load_en_i25, fabric_mrepair_sif_load_en_i26, fabric_mrepair_sif_update_en_i1, fabric_mrepair_sif_update_en_i2, fabric_mrepair_sif_update_en_i3, fabric_mrepair_sif_update_en_i4, fabric_mrepair_sif_update_en_i5, fabric_mrepair_sif_update_en_i6, fabric_mrepair_sif_update_en_i7, fabric_mrepair_sif_update_en_i8, fabric_mrepair_sif_update_en_i9, fabric_mrepair_sif_update_en_i10, fabric_mrepair_sif_update_en_i11
+, fabric_mrepair_sif_update_en_i12, fabric_mrepair_sif_update_en_i13, fabric_mrepair_sif_update_en_i14, fabric_mrepair_sif_update_en_i15, fabric_mrepair_sif_update_en_i16, fabric_mrepair_sif_update_en_i17, fabric_mrepair_sif_update_en_i18, fabric_mrepair_sif_update_en_i19, fabric_mrepair_sif_update_en_i20, fabric_mrepair_sif_update_en_i21, fabric_mrepair_sif_update_en_i22, fabric_mrepair_sif_update_en_i23, fabric_mrepair_sif_update_en_i24, fabric_mrepair_sif_update_en_i25, fabric_mrepair_sif_update_en_i26, fabric_mrepair_sif_reg_en_i1, fabric_mrepair_sif_reg_en_i2, fabric_mrepair_sif_reg_en_i3, fabric_mrepair_sif_reg_en_i4, fabric_mrepair_sif_reg_en_i5, fabric_mrepair_sif_reg_en_i6
+, fabric_mrepair_sif_reg_en_i7, fabric_mrepair_sif_reg_en_i8, fabric_mrepair_sif_reg_en_i9, fabric_mrepair_sif_reg_en_i10, fabric_mrepair_sif_reg_en_i11, fabric_mrepair_sif_reg_en_i12, fabric_mrepair_sif_reg_en_i13, fabric_mrepair_sif_reg_en_i14, fabric_mrepair_sif_reg_en_i15, fabric_mrepair_sif_reg_en_i16, fabric_mrepair_sif_reg_en_i17, fabric_mrepair_sif_reg_en_i18, fabric_mrepair_sif_reg_en_i19, fabric_mrepair_sif_reg_en_i20, fabric_mrepair_sif_reg_en_i21, fabric_mrepair_sif_reg_en_i22, fabric_mrepair_sif_reg_en_i23, fabric_mrepair_sif_reg_en_i24, fabric_mrepair_sif_reg_en_i25, fabric_mrepair_sif_reg_en_i26, fabric_mrepair_system_data_from_mem_bist_o1
+, fabric_mrepair_system_data_from_mem_bist_o2, fabric_mrepair_system_data_from_mem_bist_o3, fabric_mrepair_system_data_from_mem_bist_o4, fabric_mrepair_system_data_from_mem_bist_o5, fabric_mrepair_system_data_from_mem_bist_o6, fabric_mrepair_system_data_from_mem_bist_o7, fabric_mrepair_system_data_from_mem_bist_o8, fabric_mrepair_system_data_from_mem_bist_o9, fabric_mrepair_system_data_from_mem_bist_o10, fabric_mrepair_system_data_from_mem_bist_o11, fabric_mrepair_system_data_from_mem_bist_o12, fabric_mrepair_system_data_from_mem_bist_o13, fabric_mrepair_system_data_from_mem_bist_o14, fabric_mrepair_system_data_from_mem_bist_o15, fabric_mrepair_system_data_from_mem_bist_o16, fabric_mrepair_system_data_from_mem_bist_o17, fabric_mrepair_system_data_from_mem_bist_o18, fabric_mrepair_system_data_from_mem_bist_o19, fabric_mrepair_system_data_from_mem_bist_o20, fabric_mrepair_system_data_from_mem_bist_o21, fabric_mrepair_system_data_from_mem_bist_o22
+, fabric_mrepair_system_data_from_mem_bist_o23, fabric_mrepair_system_data_from_mem_bist_o24, fabric_mrepair_system_data_from_mem_bist_o25, fabric_mrepair_system_data_from_mem_bist_o26, fabric_mrepair_bist_mode_o, fabric_mrepair_mem_type_sel_o1, fabric_mrepair_mem_type_sel_o2, fabric_mrepair_mem_type_sel_o3, fabric_mrepair_mem_type_sel_o4, fabric_mrepair_mem_type_sel_o5, fabric_mrepair_mode_sel_o1, fabric_mrepair_mode_sel_o2, fabric_mrepair_mode_sel_o3, fabric_mrepair_mode_sel_o4, fabric_mrepair_bend_i, fabric_mrepair_global_bbad_i, fabric_mrepair_global_repairable_i, fabric_mrepair_bypass_o, fabric_mrepair_memsafe_o, fabric_mrepair_mem_atpg_mode_o, fabric_mrepair_tst_gatedclock_o
+, fabric_mrepair_test_se_o, fabric_mrepair_data_to_system_o, fabric_mrepair_tst_atpg_mrepair_i, fabric_mrepair_data_from_system_i, fabric_mrepair_end_encoding_i, fabric_mrepair_mode_i1, fabric_mrepair_mode_i2, fabric_mrepair_mode_i3, fabric_mrepair_mode_i4, fabric_mrepair_pd_active_i1, fabric_mrepair_pd_active_i2, fabric_mrepair_pd_active_i3, fabric_mrepair_pd_active_i4, fabric_mrepair_pd_active_i5, fabric_mrepair_pd_active_i6, fabric_mrepair_pd_active_i7, fabric_mrepair_pd_active_i8, fabric_mrepair_pd_active_i9, fabric_mrepair_pd_active_i10, fabric_mrepair_pd_active_i11, fabric_mrepair_pd_active_i12
+, fabric_mrepair_pd_active_i13, fabric_mrepair_pd_active_i14, fabric_mrepair_pd_active_i15, fabric_mrepair_pd_active_i16, fabric_mrepair_pd_active_i17, fabric_mrepair_pd_active_i18, fabric_mrepair_pd_active_i19, fabric_mrepair_pd_active_i20, fabric_mrepair_pd_active_i21, fabric_mrepair_pd_active_i22, fabric_mrepair_pd_active_i23, fabric_mrepair_pd_active_i24, fabric_mrepair_pd_active_i25, fabric_mrepair_pd_active_i26, fabric_mrepair_chip_status_o1, fabric_mrepair_chip_status_o2, fabric_mrepair_chip_status_o3, fabric_mrepair_chip_status_o4, fabric_mrepair_chip_status_o5, fabric_mrepair_chip_status_o6, fabric_mrepair_chip_status_o7
+, fabric_mrepair_chip_status_o8, fabric_mrepair_chip_status_o9, fabric_mrepair_chip_status_o10, fabric_mrepair_chip_status_o11, fabric_mrepair_chip_status_o12, fabric_mrepair_chip_status_o13, fabric_mrepair_chip_status_o14, fabric_mrepair_chip_status_o15, fabric_mrepair_chip_status_o16, fabric_mrepair_chip_status_o17, fabric_mrepair_chip_status_o18, fabric_mrepair_chip_status_o19, fabric_mrepair_chip_status_o20, fabric_mrepair_chip_status_o21, fabric_mrepair_chip_status_o22, fabric_mrepair_chip_status_o23, fabric_mrepair_chip_status_o24, fabric_mrepair_chip_status_o25, fabric_mrepair_chip_status_o26, fabric_mrepair_chip_status_o27, fabric_mrepair_chip_status_o28
+, fabric_mrepair_chip_status_o29, fabric_mrepair_chip_status_o30, fabric_mrepair_chip_status_o31, fabric_mrepair_chip_status_o32, fabric_mrepair_chip_status_o33, fabric_mrepair_chip_status_o34, fabric_mrepair_chip_status_o35, fabric_mrepair_chip_status_o36, fabric_mrepair_chip_status_o37, fabric_mrepair_chip_status_o38, fabric_mrepair_chip_status_o39, fabric_mrepair_chip_status_o40, fabric_mrepair_chip_status_o41, fabric_mrepair_chip_status_o42, fabric_mrepair_chip_status_o43, fabric_mrepair_chip_status_o44, fabric_mrepair_chip_status_o45, fabric_mrepair_chip_status_o46, fabric_mrepair_chip_status_o47, fabric_mrepair_chip_status_o48, fabric_mrepair_chip_status_o49
+, fabric_mrepair_chip_status_o50, fabric_mrepair_chip_status_o51, fabric_mrepair_chip_status_o52, fabric_mrepair_chip_status_o53, fabric_mrepair_chip_status_o54, fabric_mrepair_chip_status_o55, fabric_mrepair_chip_status_o56, fabric_mrepair_chip_status_o57, fabric_mrepair_chip_status_o58, fabric_mrepair_chip_status_o59, fabric_mrepair_chip_status_o60, fabric_mrepair_chip_status_o61, fabric_mrepair_chip_status_o62, fabric_mrepair_chip_status_o63, fabric_mrepair_chip_status_o64, fabric_mrepair_chip_status_o65, fabric_mrepair_chip_status_o66, fabric_mrepair_chip_status_o67, fabric_mrepair_chip_status_o68, fabric_mrepair_chip_status_o69, fabric_mrepair_chip_status_o70
+, fabric_mrepair_chip_status_o71, fabric_mrepair_chip_status_o72, fabric_mrepair_chip_status_o73, fabric_mrepair_chip_status_o74, fabric_mrepair_chip_status_o75, fabric_mrepair_chip_status_o76, fabric_mrepair_chip_status_o77, fabric_mrepair_chip_status_o78, fabric_mrepair_global_chip_status_o1, fabric_mrepair_global_chip_status_o2, fabric_mrepair_global_chip_status_o3, fabric_mrepair_pd_ready_o1, fabric_mrepair_pd_ready_o2, fabric_mrepair_pd_ready_o3, fabric_mrepair_pd_ready_o4, fabric_mrepair_pd_ready_o5, fabric_mrepair_pd_ready_o6, fabric_mrepair_pd_ready_o7, fabric_mrepair_pd_ready_o8, fabric_mrepair_pd_ready_o9, fabric_mrepair_pd_ready_o10
+, fabric_mrepair_pd_ready_o11, fabric_mrepair_pd_ready_o12, fabric_mrepair_pd_ready_o13, fabric_mrepair_pd_ready_o14, fabric_mrepair_pd_ready_o15, fabric_mrepair_pd_ready_o16, fabric_mrepair_pd_ready_o17, fabric_mrepair_pd_ready_o18, fabric_mrepair_pd_ready_o19, fabric_mrepair_pd_ready_o20, fabric_mrepair_pd_ready_o21, fabric_mrepair_pd_ready_o22, fabric_mrepair_pd_ready_o23, fabric_mrepair_pd_ready_o24, fabric_mrepair_pd_ready_o25, fabric_mrepair_pd_ready_o26, fabric_mrepair_system_dataready_o, fabric_mrepair_decoder_init_ready_o, fabric_mrepair_fuse_pdn_i, fabric_mrepair_fuse_bistmode_i, fabric_mrepair_fuse_tm_i
+, fabric_mrepair_fuse_add_i1, fabric_mrepair_fuse_add_i2, fabric_mrepair_fuse_add_i3, fabric_mrepair_fuse_add_i4, fabric_mrepair_fuse_add_i5, fabric_mrepair_fuse_add_i6, fabric_mrepair_fuse_add_i7, fabric_mrepair_fuse_din_i1, fabric_mrepair_fuse_din_i2, fabric_mrepair_fuse_din_i3, fabric_mrepair_fuse_din_i4, fabric_mrepair_fuse_din_i5, fabric_mrepair_fuse_din_i6, fabric_mrepair_fuse_din_i7, fabric_mrepair_fuse_din_i8, fabric_mrepair_fuse_din_i9, fabric_mrepair_fuse_din_i10, fabric_mrepair_fuse_din_i11, fabric_mrepair_fuse_din_i12, fabric_mrepair_fuse_din_i13, fabric_mrepair_fuse_din_i14
+, fabric_mrepair_fuse_din_i15, fabric_mrepair_fuse_din_i16, fabric_mrepair_fuse_din_i17, fabric_mrepair_fuse_din_i18, fabric_mrepair_fuse_din_i19, fabric_mrepair_fuse_din_i20, fabric_mrepair_fuse_din_i21, fabric_mrepair_fuse_din_i22, fabric_mrepair_fuse_din_i23, fabric_mrepair_fuse_din_i24, fabric_mrepair_fuse_din_i25, fabric_mrepair_fuse_din_i26, fabric_mrepair_fuse_din_i27, fabric_mrepair_fuse_din_i28, fabric_mrepair_fuse_din_i29, fabric_mrepair_fuse_din_i30, fabric_mrepair_fuse_din_i31, fabric_mrepair_fuse_din_i32, fabric_mrepair_fuse_din_i33, fabric_mrepair_fuse_din_i34, fabric_mrepair_fuse_din_i35
+, fabric_mrepair_fuse_din_i36, fabric_mrepair_fuse_din_i37, fabric_mrepair_fuse_din_i38, fabric_mrepair_fuse_din_i39, fabric_mrepair_fuse_read_i, fabric_mrepair_fuse_prog_i, fabric_mrepair_fuse_rbact1_i, fabric_mrepair_fuse_rbact2_i, fabric_mrepair_fuse_tstscanenable_i, fabric_mrepair_fuse_tst_scanin_i1, fabric_mrepair_fuse_tst_scanin_i2, fabric_mrepair_fuse_tst_scanin_i3, fabric_mrepair_fuse_tst_scanin_i4, fabric_mrepair_fuse_tst_scanin_i5, fabric_mrepair_fuse_eccbypass_i, fabric_mrepair_fuse_wordlock_i, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_redbypass_i, fabric_mrepair_fuse_disturbchecked_i, fabric_mrepair_fuse_prgwidth_i1, fabric_mrepair_fuse_prgwidth_i2
+, fabric_mrepair_fuse_prgwidth_i3, fabric_mrepair_data_shift_en_i, fabric_mrepair_fuse_pwok_o, fabric_mrepair_fuse_dout_o1, fabric_mrepair_fuse_dout_o2, fabric_mrepair_fuse_dout_o3, fabric_mrepair_fuse_dout_o4, fabric_mrepair_fuse_dout_o5, fabric_mrepair_fuse_dout_o6, fabric_mrepair_fuse_dout_o7, fabric_mrepair_fuse_dout_o8, fabric_mrepair_fuse_dout_o9, fabric_mrepair_fuse_dout_o10, fabric_mrepair_fuse_dout_o11, fabric_mrepair_fuse_dout_o12, fabric_mrepair_fuse_dout_o13, fabric_mrepair_fuse_dout_o14, fabric_mrepair_fuse_dout_o15, fabric_mrepair_fuse_dout_o16, fabric_mrepair_fuse_dout_o17, fabric_mrepair_fuse_dout_o18
+, fabric_mrepair_fuse_dout_o19, fabric_mrepair_fuse_dout_o20, fabric_mrepair_fuse_dout_o21, fabric_mrepair_fuse_dout_o22, fabric_mrepair_fuse_dout_o23, fabric_mrepair_fuse_dout_o24, fabric_mrepair_fuse_dout_o25, fabric_mrepair_fuse_dout_o26, fabric_mrepair_fuse_dout_o27, fabric_mrepair_fuse_dout_o28, fabric_mrepair_fuse_dout_o29, fabric_mrepair_fuse_dout_o30, fabric_mrepair_fuse_dout_o31, fabric_mrepair_fuse_dout_o32, fabric_mrepair_fuse_dout_o33, fabric_mrepair_fuse_dout_o34, fabric_mrepair_fuse_dout_o35, fabric_mrepair_fuse_dout_o36, fabric_mrepair_fuse_dout_o37, fabric_mrepair_fuse_dout_o38, fabric_mrepair_fuse_dout_o39
+, fabric_mrepair_fuse_dout_o40, fabric_mrepair_fuse_dout_o41, fabric_mrepair_fuse_startword_o1, fabric_mrepair_fuse_startword_o2, fabric_mrepair_fuse_startword_o3, fabric_mrepair_fuse_startword_o4, fabric_mrepair_fuse_startword_o5, fabric_mrepair_fuse_startword_o6, fabric_mrepair_fuse_startword_o7, fabric_mrepair_fuse_startword_o8, fabric_mrepair_fuse_startword_o9, fabric_mrepair_fuse_startword_o10, fabric_mrepair_fuse_startword_o11, fabric_mrepair_fuse_startword_o12, fabric_mrepair_fuse_startword_o13, fabric_mrepair_fuse_startword_o14, fabric_mrepair_fuse_startword_o15, fabric_mrepair_fuse_startword_o16, fabric_mrepair_fuse_ack_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_ded_o
+, fabric_mrepair_fuse_progfail_o, fabric_mrepair_fuse_locked_o, fabric_mrepair_fuse_disturbed_o, fabric_mrepair_fuse_wlromout_o1, fabric_mrepair_fuse_wlromout_o2, fabric_mrepair_fuse_wlromout_o3, fabric_mrepair_fuse_wlromout_o4, fabric_mrepair_fuse_wlromout_o5, fabric_mrepair_fuse_wlromout_o6, fabric_mrepair_fuse_wlromout_o7, fabric_mrepair_fuse_wlromout_o8, fabric_mrepair_fuse_wlromout_o9, fabric_mrepair_fuse_wlromout_o10, fabric_mrepair_fuse_bist1fail_o1, fabric_mrepair_fuse_bist1fail_o2, fabric_mrepair_fuse_bist1fail_o3, fabric_mrepair_fuse_bist1fail_o4, fabric_mrepair_fuse_bist1fail_o5, fabric_mrepair_fuse_bist1fail_o6, fabric_mrepair_fuse_bist1fail_o7, fabric_mrepair_fuse_bist1fail_o8
+, fabric_mrepair_fuse_bist2fail_o1, fabric_mrepair_fuse_bist2fail_o2, fabric_mrepair_fuse_bist2fail_o3, fabric_mrepair_fuse_bist2fail_o4, fabric_mrepair_fuse_bist2fail_o5, fabric_mrepair_fuse_bist2fail_o6, fabric_mrepair_fuse_bist2fail_o7, fabric_mrepair_fuse_bend1_o, fabric_mrepair_fuse_bend2_o, fabric_mrepair_fuse_bbad_o, fabric_mrepair_fuse_tstscanout_o1, fabric_mrepair_fuse_tstscanout_o2, fabric_mrepair_fuse_tstscanout_o3, fabric_mrepair_fuse_tstscanout_o4, fabric_mrepair_fuse_tstscanout_o5, fabric_mrepair_fuse_flagstate_o1, fabric_mrepair_fuse_flagstate_o2, fabric_mrepair_fuse_flagstate_o3, fabric_mrepair_fuse_flagstate_o4, fabric_mrepair_fuse_calibrated_o, fabric_mrepair_fuse_ready_o
+, fabric_mrepair_fuse_status_o1, fabric_mrepair_fuse_status_o2, fabric_mrepair_fuse_status_o3, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_otp_user_clk_i, fabric_otp_user_bistmode_i, fabric_otp_user_disturbcheck_i, fabric_otp_user_eccbypass_i, fabric_otp_user_pdn_i, fabric_otp_user_prog_i, fabric_otp_user_rbact1_i, fabric_otp_user_rbact2_i, fabric_otp_user_read_i, fabric_otp_user_redbypass_i, fabric_otp_user_suppadd_i, fabric_otp_user_tm_i, fabric_otp_user_tst_scanenable_i, fabric_otp_user_wordlock_i, fabric_otp_user_add_i1, fabric_otp_user_add_i2, fabric_otp_user_add_i3
+, fabric_otp_user_add_i4, fabric_otp_user_add_i5, fabric_otp_user_add_i6, fabric_otp_user_add_i7, fabric_otp_user_clock_frequency_range_i, fabric_otp_user_din_i1, fabric_otp_user_din_i2, fabric_otp_user_din_i3, fabric_otp_user_din_i4, fabric_otp_user_din_i5, fabric_otp_user_din_i6, fabric_otp_user_din_i7, fabric_otp_user_din_i8, fabric_otp_user_din_i9, fabric_otp_user_din_i10, fabric_otp_user_din_i11, fabric_otp_user_din_i12, fabric_otp_user_din_i13, fabric_otp_user_din_i14, fabric_otp_user_din_i15, fabric_otp_user_din_i16
+, fabric_otp_user_din_i17, fabric_otp_user_din_i18, fabric_otp_user_din_i19, fabric_otp_user_din_i20, fabric_otp_user_din_i21, fabric_otp_user_din_i22, fabric_otp_user_din_i23, fabric_otp_user_din_i24, fabric_otp_user_din_i25, fabric_otp_user_din_i26, fabric_otp_user_din_i27, fabric_otp_user_din_i28, fabric_otp_user_din_i29, fabric_otp_user_din_i30, fabric_otp_user_din_i31, fabric_otp_user_din_i32, fabric_otp_user_din_i33, fabric_otp_user_din_i34, fabric_otp_user_din_i35, fabric_otp_user_din_i36, fabric_otp_user_din_i37
+, fabric_otp_user_din_i38, fabric_otp_user_din_i39, fabric_otp_user_prgwidth_i1, fabric_otp_user_prgwidth_i2, fabric_otp_user_prgwidth_i3, fabric_otp_user_tst_scanin_i1, fabric_otp_user_tst_scanin_i2, fabric_otp_user_tst_scanin_i3, fabric_otp_user_tst_scanin_i4, fabric_otp_user_tst_scanin_i5, fabric_otp_user_ack_o, fabric_otp_user_bbad_o, fabric_otp_user_bend1_o, fabric_otp_user_bend2_o, fabric_otp_user_calibrated_o, fabric_otp_user_ded_o, fabric_otp_user_disturbed_o, fabric_otp_user_locked_o, fabric_otp_user_progfail_o, fabric_otp_user_pwok_o, fabric_otp_user_sec_o
+, fabric_otp_user_bist1fail_o1, fabric_otp_user_bist1fail_o2, fabric_otp_user_bist1fail_o3, fabric_otp_user_bist1fail_o4, fabric_otp_user_bist1fail_o5, fabric_otp_user_bist1fail_o6, fabric_otp_user_bist1fail_o7, fabric_otp_user_bist1fail_o8, fabric_otp_user_bist2fail_o1, fabric_otp_user_bist2fail_o2, fabric_otp_user_bist2fail_o3, fabric_otp_user_bist2fail_o4, fabric_otp_user_bist2fail_o5, fabric_otp_user_bist2fail_o6, fabric_otp_user_bist2fail_o7, fabric_otp_user_dout_o1, fabric_otp_user_dout_o2, fabric_otp_user_dout_o3, fabric_otp_user_dout_o4, fabric_otp_user_dout_o5, fabric_otp_user_dout_o6
+, fabric_otp_user_dout_o7, fabric_otp_user_dout_o8, fabric_otp_user_dout_o9, fabric_otp_user_dout_o10, fabric_otp_user_dout_o11, fabric_otp_user_dout_o12, fabric_otp_user_dout_o13, fabric_otp_user_dout_o14, fabric_otp_user_dout_o15, fabric_otp_user_dout_o16, fabric_otp_user_dout_o17, fabric_otp_user_dout_o18, fabric_otp_user_dout_o19, fabric_otp_user_dout_o20, fabric_otp_user_dout_o21, fabric_otp_user_dout_o22, fabric_otp_user_dout_o23, fabric_otp_user_dout_o24, fabric_otp_user_dout_o25, fabric_otp_user_dout_o26, fabric_otp_user_dout_o27
+, fabric_otp_user_dout_o28, fabric_otp_user_dout_o29, fabric_otp_user_dout_o30, fabric_otp_user_dout_o31, fabric_otp_user_dout_o32, fabric_otp_user_dout_o33, fabric_otp_user_dout_o34, fabric_otp_user_dout_o35, fabric_otp_user_dout_o36, fabric_otp_user_dout_o37, fabric_otp_user_dout_o38, fabric_otp_user_dout_o39, fabric_otp_user_dout_o40, fabric_otp_user_dout_o41, fabric_otp_user_flagstate_o1, fabric_otp_user_flagstate_o2, fabric_otp_user_flagstate_o3, fabric_otp_user_flagstate_o4, fabric_otp_user_startword_o1, fabric_otp_user_startword_o2, fabric_otp_user_startword_o3
+, fabric_otp_user_startword_o4, fabric_otp_user_startword_o5, fabric_otp_user_startword_o6, fabric_otp_user_startword_o7, fabric_otp_user_startword_o8, fabric_otp_user_startword_o9, fabric_otp_user_startword_o10, fabric_otp_user_startword_o11, fabric_otp_user_startword_o12, fabric_otp_user_startword_o13, fabric_otp_user_startword_o14, fabric_otp_user_startword_o15, fabric_otp_user_startword_o16, fabric_otp_user_tst_scanout_o1, fabric_otp_user_tst_scanout_o2, fabric_otp_user_tst_scanout_o3, fabric_otp_user_tst_scanout_o4, fabric_otp_user_tst_scanout_o5, fabric_otp_user_wlromout_o1, fabric_otp_user_wlromout_o2, fabric_otp_user_wlromout_o3
+, fabric_otp_user_wlromout_o4, fabric_otp_user_wlromout_o5, fabric_otp_user_wlromout_o6, fabric_otp_user_wlromout_o7, fabric_otp_user_wlromout_o8, fabric_otp_user_wlromout_o9, fabric_otp_user_wlromout_o10, fabric_clk_bsm_o, fabric_clk_otp_mux_i, fabric_clk_otp_o, fabric_clk_user0_o, fabric_clk_user1_o, fabric_io_in_i1, fabric_io_in_i2, fabric_io_in_i3, fabric_io_in_i4, fabric_io_in_i5, fabric_io_in_i6, fabric_io_in_i7, fabric_io_in_i8, fabric_io_in_i9
+, fabric_io_in_i10, fabric_io_in_i11, fabric_io_in_i12, fabric_io_in_i13, fabric_io_in_i14, fabric_io_in_i15, fabric_io_in_i16, fabric_io_in_i17, fabric_io_in_i18, fabric_io_in_i19, fabric_io_in_i20, fabric_io_in_i21, fabric_io_in_i22, fabric_io_in_i23, fabric_io_in_i24, fabric_io_in_i25, fabric_io_in_i26, fabric_io_in_i27, fabric_io_in_i28, fabric_io_in_i29, fabric_io_in_i30
+, fabric_io_in_i31, fabric_io_in_i32, fabric_io_in_i33, fabric_io_in_i34, fabric_io_in_i35, fabric_io_oe_i1, fabric_io_oe_i2, fabric_io_oe_i3, fabric_io_oe_i4, fabric_io_oe_i5, fabric_io_oe_i6, fabric_io_oe_i7, fabric_io_oe_i8, fabric_io_oe_i9, fabric_io_oe_i10, fabric_io_oe_i11, fabric_io_oe_i12, fabric_io_oe_i13, fabric_io_oe_i14, fabric_io_oe_i15, fabric_io_oe_i16
+, fabric_io_oe_i17, fabric_io_oe_i18, fabric_io_oe_i19, fabric_io_oe_i20, fabric_io_oe_i21, fabric_io_oe_i22, fabric_io_oe_i23, fabric_io_oe_i24, fabric_io_oe_i25, fabric_io_oe_i26, fabric_io_oe_i27, fabric_io_oe_i28, fabric_io_oe_i29, fabric_io_oe_i30, fabric_io_oe_i31, fabric_io_oe_i32, fabric_io_oe_i33, fabric_io_oe_i34, fabric_io_oe_i35, fabric_io_out_o1, fabric_io_out_o2
+, fabric_io_out_o3, fabric_io_out_o4, fabric_io_out_o5, fabric_io_out_o6, fabric_io_out_o7, fabric_io_out_o8, fabric_io_out_o9, fabric_io_out_o10, fabric_io_out_o11, fabric_io_out_o12, fabric_io_out_o13, fabric_io_out_o14, fabric_io_out_o15, fabric_io_out_o16, fabric_io_out_o17, fabric_io_out_o18, fabric_io_out_o19, fabric_io_out_o20, fabric_io_out_o21, fabric_io_out_o22, fabric_io_out_o23
+, fabric_io_out_o24, fabric_io_out_o25, fabric_io_out_o26, fabric_io_out_o27, fabric_io_out_o28, fabric_io_out_o29, fabric_io_out_o30, fabric_io_out_o31, fabric_io_out_o32, fabric_io_out_o33, fabric_io_out_o34, fabric_io_out_o35, fabric_user_clk_i, fabric_user_data_i1, fabric_user_data_i2, fabric_user_data_i3, fabric_user_data_i4, fabric_user_data_i5, fabric_user_data_i6, fabric_user_data_i7, fabric_user_data_i8
+, fabric_user_data_i9, fabric_user_data_i10, fabric_user_data_i11, fabric_user_data_i12, fabric_user_data_i13, fabric_user_data_i14, fabric_user_data_i15, fabric_user_data_i16, fabric_user_data_i17, fabric_user_data_i18, fabric_user_data_i19, fabric_user_data_i20, fabric_user_data_i21, fabric_user_data_i22, fabric_user_data_i23, fabric_user_data_i24, fabric_user_data_i25, fabric_user_data_i26, fabric_user_data_i27, fabric_user_data_i28, fabric_user_data_i29
+, fabric_user_data_i30, fabric_user_data_i31, fabric_user_data_i32, fabric_user_data_o1, fabric_user_data_o2, fabric_user_data_o3, fabric_user_data_o4, fabric_user_data_o5, fabric_user_data_o6, fabric_user_data_o7, fabric_user_data_o8, fabric_user_data_o9, fabric_user_data_o10, fabric_user_data_o11, fabric_user_data_o12, fabric_user_data_o13, fabric_user_data_o14, fabric_user_data_o15, fabric_user_data_o16, fabric_user_data_o17, fabric_user_data_o18
+, fabric_user_data_o19, fabric_user_data_o20, fabric_user_data_o21, fabric_user_data_o22, fabric_user_data_o23, fabric_user_data_o24, fabric_user_data_o25, fabric_user_data_o26, fabric_user_data_o27, fabric_user_data_o28, fabric_user_data_o29, fabric_user_data_o30, fabric_user_data_o31, fabric_user_data_o32, fabric_user_write_cycle_o, fabric_user_read_cycle_o, fabric_cfg_fabric_user_flag_o, fabric_cfg_fabric_user_enable_o, fabric_parusr_clk_i, fabric_parusr_enable_i, fabric_parusr_cs_i
+, fabric_parusr_type_i1, fabric_parusr_type_i2, fabric_parusr_data_i1, fabric_parusr_data_i2, fabric_parusr_data_i3, fabric_parusr_data_i4, fabric_parusr_data_i5, fabric_parusr_data_i6, fabric_parusr_data_i7, fabric_parusr_data_i8, fabric_parusr_data_i9, fabric_parusr_data_i10, fabric_parusr_data_i11, fabric_parusr_data_i12, fabric_parusr_data_i13, fabric_parusr_data_i14, fabric_parusr_data_i15, fabric_parusr_data_i16, fabric_parusr_data_o1, fabric_parusr_data_o2, fabric_parusr_data_o3
+, fabric_parusr_data_o4, fabric_parusr_data_o5, fabric_parusr_data_o6, fabric_parusr_data_o7, fabric_parusr_data_o8, fabric_parusr_data_o9, fabric_parusr_data_o10, fabric_parusr_data_o11, fabric_parusr_data_o12, fabric_parusr_data_o13, fabric_parusr_data_o14, fabric_parusr_data_o15, fabric_parusr_data_o16, fabric_parusr_data_val_o, fabric_jtag_tck_o, fabric_jtag_trst_n_o, fabric_jtag_tms_o, fabric_jtag_tdi_o, fabric_jtag_usr1_o, fabric_jtag_usr2_o, fabric_jtag_tdo_usr1_i
+, fabric_jtag_tdo_usr2_i, fabric_direct_data_i1, fabric_direct_data_i2, fabric_direct_data_i3, fabric_direct_data_i4, fabric_direct_data_i5, fabric_direct_data_i6, fabric_direct_data_i7, fabric_direct_data_i8, fabric_direct_data_i9, fabric_direct_data_i10, fabric_direct_data_i11, fabric_direct_data_i12, fabric_direct_data_i13, fabric_direct_data_i14, fabric_direct_data_i15, fabric_direct_data_i16, fabric_direct_data_i17, fabric_direct_data_i18, fabric_direct_data_i19, fabric_direct_data_i20
+, fabric_direct_data_i21, fabric_direct_data_i22, fabric_direct_data_i23, fabric_direct_data_i24, fabric_direct_data_i25, fabric_direct_data_i26, fabric_direct_data_i27, fabric_direct_data_i28, fabric_direct_data_i29, fabric_direct_data_i30, fabric_direct_data_i31, fabric_direct_data_i32, fabric_direct_data_o1, fabric_direct_data_o2, fabric_direct_data_o3, fabric_direct_data_o4, fabric_direct_data_o5, fabric_direct_data_o6, fabric_direct_data_o7, fabric_direct_data_o8, fabric_direct_data_o9
+, fabric_direct_data_o10, fabric_direct_data_o11, fabric_direct_data_o12, fabric_direct_data_o13, fabric_direct_data_o14, fabric_direct_data_o15, fabric_direct_data_o16, fabric_direct_data_o17, fabric_direct_data_o18, fabric_direct_data_o19, fabric_direct_data_o20, fabric_direct_data_o21, fabric_direct_data_o22, fabric_direct_data_o23, fabric_direct_data_o24, fabric_direct_data_o25, fabric_direct_data_o26, fabric_direct_data_o27, fabric_direct_data_o28, fabric_direct_data_o29, fabric_direct_data_o30
+, fabric_direct_data_o31, fabric_direct_data_o32, fabric_otp_clk_i, fabric_otp_rst_i, fabric_otp_apb_addr_i1, fabric_otp_apb_addr_i2, fabric_otp_apb_addr_i3, fabric_otp_apb_addr_i4, fabric_otp_apb_addr_i5, fabric_otp_apb_addr_i6, fabric_otp_apb_addr_i7, fabric_otp_apb_addr_i8, fabric_otp_apb_addr_i9, fabric_otp_apb_addr_i10, fabric_otp_apb_addr_i11, fabric_otp_apb_addr_i12, fabric_otp_apb_addr_i13, fabric_otp_apb_addr_i14, fabric_otp_apb_addr_i15, fabric_otp_apb_addr_i16, fabric_otp_apb_addr_i17
+, fabric_otp_apb_addr_i18, fabric_otp_apb_addr_i19, fabric_otp_apb_addr_i20, fabric_otp_apb_addr_i21, fabric_otp_apb_addr_i22, fabric_otp_apb_addr_i23, fabric_otp_apb_addr_i24, fabric_otp_apb_addr_i25, fabric_otp_apb_addr_i26, fabric_otp_apb_addr_i27, fabric_otp_apb_addr_i28, fabric_otp_apb_addr_i29, fabric_otp_apb_addr_i30, fabric_otp_apb_addr_i31, fabric_otp_apb_addr_i32, fabric_otp_apb_write_i, fabric_otp_apb_sel_i, fabric_otp_apb_enable_i, fabric_otp_apb_wdata_i1, fabric_otp_apb_wdata_i2, fabric_otp_apb_wdata_i3
+, fabric_otp_apb_wdata_i4, fabric_otp_apb_wdata_i5, fabric_otp_apb_wdata_i6, fabric_otp_apb_wdata_i7, fabric_otp_apb_wdata_i8, fabric_otp_apb_wdata_i9, fabric_otp_apb_wdata_i10, fabric_otp_apb_wdata_i11, fabric_otp_apb_wdata_i12, fabric_otp_apb_wdata_i13, fabric_otp_apb_wdata_i14, fabric_otp_apb_wdata_i15, fabric_otp_apb_wdata_i16, fabric_otp_apb_wdata_i17, fabric_otp_apb_wdata_i18, fabric_otp_apb_wdata_i19, fabric_otp_apb_wdata_i20, fabric_otp_apb_wdata_i21, fabric_otp_apb_wdata_i22, fabric_otp_apb_wdata_i23, fabric_otp_apb_wdata_i24
+, fabric_otp_apb_wdata_i25, fabric_otp_apb_wdata_i26, fabric_otp_apb_wdata_i27, fabric_otp_apb_wdata_i28, fabric_otp_apb_wdata_i29, fabric_otp_apb_wdata_i30, fabric_otp_apb_wdata_i31, fabric_otp_apb_wdata_i32, fabric_otp_apb_ready_o, fabric_otp_apb_rdata_o1, fabric_otp_apb_rdata_o2, fabric_otp_apb_rdata_o3, fabric_otp_apb_rdata_o4, fabric_otp_apb_rdata_o5, fabric_otp_apb_rdata_o6, fabric_otp_apb_rdata_o7, fabric_otp_apb_rdata_o8, fabric_otp_apb_rdata_o9, fabric_otp_apb_rdata_o10, fabric_otp_apb_rdata_o11, fabric_otp_apb_rdata_o12
+, fabric_otp_apb_rdata_o13, fabric_otp_apb_rdata_o14, fabric_otp_apb_rdata_o15, fabric_otp_apb_rdata_o16, fabric_otp_apb_rdata_o17, fabric_otp_apb_rdata_o18, fabric_otp_apb_rdata_o19, fabric_otp_apb_rdata_o20, fabric_otp_apb_rdata_o21, fabric_otp_apb_rdata_o22, fabric_otp_apb_rdata_o23, fabric_otp_apb_rdata_o24, fabric_otp_apb_rdata_o25, fabric_otp_apb_rdata_o26, fabric_otp_apb_rdata_o27, fabric_otp_apb_rdata_o28, fabric_otp_apb_rdata_o29, fabric_otp_apb_rdata_o30, fabric_otp_apb_rdata_o31, fabric_otp_apb_rdata_o32, fabric_otp_cfg_fabric_apb_en_i
+, fabric_otp_cfg_loader_read_en_i, fabric_otp_cfg_loader_write_en_i, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_cfg_clk_fab_en_i, fabric_otp_security_ack_o, fabric_otp_security_rbact1_i, fabric_otp_security_rbact2_i, fabric_otp_security_bistmode_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_bist_end1_o, fabric_otp_security_bist_end2_o, fabric_otp_security_bist_bad_o, fabric_otp_security_bist_fail1_o1, fabric_otp_security_bist_fail1_o2, fabric_otp_security_bist_fail1_o3, fabric_otp_security_bist_fail1_o4, fabric_otp_security_bist_fail1_o5, fabric_otp_security_bist_fail1_o6, fabric_otp_security_bist_fail1_o7, fabric_otp_security_bist_fail2_o1, fabric_otp_security_bist_fail2_o2
+, fabric_otp_security_bist_fail2_o3, fabric_otp_security_bist_fail2_o4, fabric_otp_security_bist_fail2_o5, fabric_otp_security_bist_fail2_o6, fabric_otp_security_scanin_i1, fabric_otp_security_scanin_i2, fabric_otp_security_scanin_i3, fabric_otp_security_scanin_i4, fabric_otp_security_scanout_o1, fabric_otp_security_scanout_o2, fabric_otp_security_scanout_o3, fabric_otp_security_scanout_o4, fabric_otp_security_testmode_i, fabric_otp_security_scanenable_i, fabric_status_cold_start_o, fabric_flag_trigger0_o, fabric_flag_trigger1_o, fabric_flag_ready_TMR_o1, fabric_flag_ready_TMR_o2, fabric_flag_ready_TMR_o3, fabric_debug_lifecycle_o1
+, fabric_debug_lifecycle_o2, fabric_debug_lifecycle_o3, fabric_debug_lifecycle_o4, fabric_debug_fsm_state_o1, fabric_debug_fsm_state_o2, fabric_debug_fsm_state_o3, fabric_debug_rst_soft_o, fabric_debug_error_o, fabric_debug_otp_manager_read_otp_o, fabric_debug_otp_manager_read_done_o, fabric_debug_direct_permission_write_o1, fabric_debug_direct_permission_write_o2, fabric_debug_direct_permission_write_o3, fabric_debug_direct_permission_write_o4, fabric_debug_direct_permission_read_o1, fabric_debug_direct_permission_read_o2, fabric_debug_direct_permission_read_o3, fabric_debug_direct_permission_read_o4, fabric_debug_frame_use_encryption_o, fabric_debug_frame_permission_frame_o1, fabric_debug_frame_permission_frame_o2
+, fabric_debug_frame_permission_frame_o3, fabric_debug_frame_permission_frame_o4, fabric_debug_key_correct_o, fabric_debug_otpmgmt_state_o1, fabric_debug_otpmgmt_state_o2, fabric_debug_otpmgmt_state_o3, fabric_debug_otpapb_state_o1, fabric_debug_otpapb_state_o2, fabric_debug_otpapb_state_o3, fabric_debug_otpboot_state_o1, fabric_debug_otpboot_state_o2, fabric_debug_otpboot_state_o3, fabric_debug_otp_reload_err_o, fabric_debug_cpt_retry_o1, fabric_debug_cpt_retry_o2, fabric_debug_cpt_retry_o3, fabric_debug_cpt_retry_o4, fabric_debug_bsec_core_status_o1, fabric_debug_bsec_core_status_o2, fabric_debug_bsec_core_status_o3, fabric_debug_bsec_core_status_o4
+, fabric_debug_bsec_core_status_o5, fabric_debug_bsec_core_status_o6, fabric_debug_bsec_core_status_o7, fabric_debug_bsec_core_status_o8, fabric_debug_bsec_core_status_o9, fabric_debug_bsec_core_status_o10, fabric_debug_bsec_core_status_o11, fabric_debug_bsec_core_status_o12, fabric_debug_bsec_core_status_o13, fabric_debug_bsec_core_status_o14, fabric_debug_bsec_core_status_o15, fabric_debug_bsec_core_status_o16, fabric_debug_bsec_core_status_o17, fabric_debug_bsec_core_status_o18, fabric_debug_bsec_core_status_o19, fabric_debug_bsec_core_status_o20, fabric_debug_bsec_core_status_o21, fabric_debug_bsec_core_status_o22, fabric_debug_bsec_core_status_o23, fabric_debug_bsec_core_status_o24, fabric_debug_bsec_core_status_o25
+, fabric_debug_bsec_core_status_o26, fabric_debug_bsec_core_status_o27, fabric_debug_bsec_core_status_o28, fabric_debug_bsec_core_status_o29, fabric_debug_bsec_core_status_o30, fabric_debug_bsec_core_status_o31, fabric_debug_bsec_core_status_o32, fabric_debug_otpboot_curr_addr_o1, fabric_debug_otpboot_curr_addr_o2, fabric_debug_otpboot_curr_addr_o3, fabric_debug_otpboot_curr_addr_o4, fabric_debug_otpboot_curr_addr_o5, fabric_debug_otpboot_curr_addr_o6, fabric_debug_otpboot_curr_addr_o7, fabric_debug_otpboot_curr_addr_o8, fabric_debug_access_reg_data_ready_o, fabric_debug_security_error_read_o, fabric_debug_security_boot_done_o, fabric_debug_lock_reg_o, fabric_enable_TMR_i1, fabric_enable_TMR_i2
+, fabric_enable_TMR_i3, fabric_lowskew_i1, fabric_lowskew_i2, fabric_lowskew_i3, fabric_lowskew_i4, fabric_lowskew_i5, fabric_lowskew_i6, fabric_lowskew_i7, fabric_lowskew_i8, fabric_lowskew_i9, fabric_lowskew_i10, fabric_lowskew_i11, fabric_lowskew_i12, fabric_lowskew_i13, fabric_lowskew_i14, fabric_lowskew_i15, fabric_lowskew_i16, fabric_lowskew_i17, fabric_lowskew_i18, fabric_lowskew_i19, fabric_lowskew_i20
+, fabric_lowskew_i21, fabric_lowskew_i22, fabric_lowskew_i23, fabric_lowskew_i24, fabric_lowskew_i25, fabric_lowskew_i26, fabric_lowskew_i27, fabric_lowskew_i28, fabric_lowskew_i29, fabric_lowskew_i30, fabric_lowskew_i31, fabric_lowskew_i32, fabric_lowskew_i33, fabric_lowskew_i34, fabric_lowskew_i35, fabric_lowskew_i36, fabric_lowskew_i37, fabric_lowskew_i38, fabric_lowskew_i39, fabric_lowskew_i40, fabric_lowskew_o1
+, fabric_lowskew_o2, fabric_lowskew_o3, fabric_lowskew_o4, fabric_lowskew_o5, fabric_lowskew_o6, fabric_spare_i1, fabric_spare_i2, fabric_spare_i3, fabric_spare_i4, fabric_spare_i5, fabric_spare_i6, fabric_spare_i7, fabric_spare_i8, fabric_spare_i9, fabric_spare_i10, fabric_spare_i11, fabric_spare_i12, fabric_spare_i13, fabric_spare_i14, fabric_spare_i15, fabric_spare_i16
+, fabric_spare_i17, fabric_spare_i18, fabric_spare_i19, fabric_spare_i20, fabric_spare_i21, fabric_spare_i22, fabric_spare_i23, fabric_spare_i24, fabric_spare_i25, fabric_spare_i26, fabric_spare_i27, fabric_spare_i28, fabric_spare_i29, fabric_spare_i30, fabric_spare_i31, fabric_spare_i32, fabric_spare_i33, fabric_spare_i34, fabric_spare_i35, fabric_spare_i36, fabric_spare_i37
+, fabric_spare_i38, fabric_spare_i39, fabric_spare_i40, fabric_spare_i41, fabric_spare_i42, fabric_spare_i43, fabric_spare_i44, fabric_spare_i45, fabric_spare_i46, fabric_spare_i47, fabric_spare_i48, fabric_spare_i49, fabric_spare_i50, fabric_spare_i51, fabric_spare_i52, fabric_spare_i53, fabric_spare_i54, fabric_spare_i55, fabric_spare_i56, fabric_spare_i57, fabric_spare_i58
+, fabric_spare_i59, fabric_spare_i60, fabric_spare_i61, fabric_spare_i62, fabric_spare_i63, fabric_spare_i64, fabric_spare_i65, fabric_spare_i66, fabric_spare_i67, fabric_spare_i68, fabric_spare_i69, fabric_spare_i70, fabric_spare_i71, fabric_spare_i72, fabric_spare_i73, fabric_spare_i74, fabric_spare_i75, fabric_spare_i76, fabric_spare_i77, fabric_spare_i78, fabric_spare_i79
+, fabric_spare_i80, fabric_spare_i81, fabric_spare_i82, fabric_spare_i83, fabric_spare_i84, fabric_spare_i85, fabric_spare_i86, fabric_spare_i87, fabric_spare_i88, fabric_spare_i89, fabric_spare_i90, fabric_spare_i91, fabric_spare_i92, fabric_spare_i93, fabric_spare_i94, fabric_spare_i95, fabric_spare_i96, fabric_spare_i97, fabric_spare_i98, fabric_spare_i99, fabric_spare_i100
+, fabric_spare_i101, fabric_spare_i102, fabric_spare_i103, fabric_spare_i104, fabric_spare_i105, fabric_spare_i106, fabric_spare_i107, fabric_spare_i108, fabric_spare_i109, fabric_spare_i110, fabric_spare_i111, fabric_spare_i112, fabric_spare_i113, fabric_spare_i114, fabric_spare_i115, fabric_spare_i116, fabric_spare_i117, fabric_spare_i118, fabric_spare_i119, fabric_spare_i120, fabric_spare_i121
+, fabric_spare_i122, fabric_spare_i123, fabric_spare_i124, fabric_spare_i125, fabric_spare_i126, fabric_spare_i127, fabric_spare_i128, fabric_spare_o1, fabric_spare_o2, fabric_spare_o3, fabric_spare_o4, fabric_spare_o5, fabric_spare_o6, fabric_spare_o7, fabric_spare_o8, fabric_spare_o9, fabric_spare_o10, fabric_spare_o11, fabric_spare_o12, fabric_spare_o13, fabric_spare_o14
+, fabric_spare_o15, fabric_spare_o16, fabric_spare_o17, fabric_spare_o18, fabric_spare_o19, fabric_spare_o20, fabric_spare_o21, fabric_spare_o22, fabric_spare_o23, fabric_spare_o24, fabric_spare_o25, fabric_spare_o26, fabric_spare_o27, fabric_spare_o28, fabric_spare_o29, fabric_spare_o30, fabric_spare_o31, fabric_spare_o32, fabric_spare_o33, fabric_spare_o34, fabric_spare_o35
+, fabric_spare_o36, fabric_spare_o37, fabric_spare_o38, fabric_spare_o39, fabric_spare_o40, fabric_spare_o41, fabric_spare_o42, fabric_spare_o43, fabric_spare_o44, fabric_spare_o45, fabric_spare_o46, fabric_spare_o47, fabric_spare_o48, fabric_spare_o49, fabric_spare_o50, fabric_spare_o51, fabric_spare_o52, fabric_spare_o53, fabric_spare_o54, fabric_spare_o55, fabric_spare_o56
+, fabric_spare_o57, fabric_spare_o58, fabric_spare_o59, fabric_spare_o60, fabric_spare_o61, fabric_spare_o62, fabric_spare_o63, fabric_spare_o64, fabric_spare_o65, fabric_spare_o66, fabric_spare_o67, fabric_spare_o68, fabric_spare_o69, fabric_spare_o70, fabric_spare_o71, fabric_spare_o72, fabric_spare_o73, fabric_spare_o74, fabric_spare_o75, fabric_spare_o76, fabric_spare_o77
+, fabric_spare_o78, fabric_spare_o79, fabric_spare_o80, fabric_spare_o81, fabric_spare_o82, fabric_spare_o83, fabric_spare_o84, fabric_spare_o85, fabric_spare_o86, fabric_spare_o87, fabric_spare_o88, fabric_spare_o89, fabric_spare_o90, fabric_spare_o91, fabric_spare_o92, fabric_spare_o93, fabric_spare_o94, fabric_spare_o95, fabric_spare_o96, fabric_spare_o97, fabric_spare_o98
+, fabric_spare_o99, fabric_spare_o100, fabric_spare_o101, fabric_spare_o102, fabric_spare_o103, fabric_spare_o104, fabric_spare_o105, fabric_spare_o106, fabric_spare_o107, fabric_spare_o108, fabric_spare_o109, fabric_spare_o110, fabric_spare_o111, fabric_spare_o112, fabric_spare_o113, fabric_spare_o114, fabric_spare_o115, fabric_spare_o116, fabric_spare_o117, fabric_spare_o118, fabric_spare_o119
+, fabric_spare_o120, fabric_spare_o121, fabric_spare_o122, fabric_spare_o123, fabric_spare_o124, fabric_spare_o125, fabric_spare_o126, fabric_spare_o127, fabric_spare_o128, fabric_dac0_clk_i, fabric_dac0_clk_en_i, fabric_dac0_din_i1, fabric_dac0_din_i2, fabric_dac0_din_i3, fabric_dac0_din_i4, fabric_dac0_din_i5, fabric_dac0_din_i6, fabric_dac0_din_i7, fabric_dac0_din_i8, fabric_dac0_din_i9, fabric_dac0_din_i10
+, fabric_dac0_din_i11, fabric_dac0_din_i12, fabric_dac0_din_i13, fabric_dac0_reg_pwr_down_n_i, fabric_dac0_rstn_i, fabric_dac0_op_en_i, fabric_dac0_filt_en_i, fabric_dac0_comp_en_i, fabric_dac0_comp_ref_sel_i, fabric_dac0_comp_hyst_en_i, fabric_dac0_comp_in_sel_i1, fabric_dac0_comp_in_sel_i2, fabric_dac0_comp_in_sel_i3, fabric_dac0_comp_in_sel_i4, fabric_dac0_comp_out_o, fabric_cfg_dac0_reg_res_i1, fabric_cfg_dac0_reg_res_i2, fabric_cfg_dac0_reg_vref_select_i, fabric_cfg_dac0_reg_cm_select_i, fabric_cfg_dac0_sync_i, fabric_dac1_clk_i
+, fabric_dac1_clk_en_i, fabric_dac1_din_i1, fabric_dac1_din_i2, fabric_dac1_din_i3, fabric_dac1_din_i4, fabric_dac1_din_i5, fabric_dac1_din_i6, fabric_dac1_din_i7, fabric_dac1_din_i8, fabric_dac1_din_i9, fabric_dac1_din_i10, fabric_dac1_din_i11, fabric_dac1_din_i12, fabric_dac1_din_i13, fabric_dac1_reg_pwr_down_n_i, fabric_dac1_rstn_i, fabric_dac1_op_en_i, fabric_dac1_filt_en_i, fabric_dac1_comp_en_i, fabric_dac1_comp_ref_sel_i, fabric_dac1_comp_hyst_en_i
+, fabric_dac1_comp_in_sel_i1, fabric_dac1_comp_in_sel_i2, fabric_dac1_comp_in_sel_i3, fabric_dac1_comp_in_sel_i4, fabric_dac1_comp_out_o, fabric_cfg_dac1_reg_res_i1, fabric_cfg_dac1_reg_res_i2, fabric_cfg_dac1_reg_vref_select_i, fabric_cfg_dac1_reg_cm_select_i, fabric_cfg_dac1_sync_i, fabric_dac2_clk_i, fabric_dac2_clk_en_i, fabric_dac2_din_i1, fabric_dac2_din_i2, fabric_dac2_din_i3, fabric_dac2_din_i4, fabric_dac2_din_i5, fabric_dac2_din_i6, fabric_dac2_din_i7, fabric_dac2_din_i8, fabric_dac2_din_i9
+, fabric_dac2_din_i10, fabric_dac2_din_i11, fabric_dac2_din_i12, fabric_dac2_din_i13, fabric_dac2_reg_pwr_down_n_i, fabric_dac2_rstn_i, fabric_dac2_op_en_i, fabric_dac2_filt_en_i, fabric_dac2_comp_en_i, fabric_dac2_comp_ref_sel_i, fabric_dac2_comp_hyst_en_i, fabric_dac2_comp_in_sel_i1, fabric_dac2_comp_in_sel_i2, fabric_dac2_comp_in_sel_i3, fabric_dac2_comp_in_sel_i4, fabric_dac2_comp_in_sel_i5, fabric_dac2_comp_in_sel_i6, fabric_dac2_comp_in_sel_i7, fabric_dac2_comp_in_sel_i8, fabric_dac2_comp_in_sel_i9, fabric_dac2_comp_in_sel_i10
+, fabric_dac2_comp_in_sel_i11, fabric_dac2_comp_in_sel_i12, fabric_dac2_comp_in_sel_i13, fabric_dac2_comp_out_o, fabric_cfg_dac2_reg_res_i1, fabric_cfg_dac2_reg_res_i2, fabric_cfg_dac2_reg_vref_select_i, fabric_cfg_dac2_reg_cm_select_i, fabric_cfg_dac2_sync_i, fabric_dac3_clk_i, fabric_dac3_clk_en_i, fabric_dac3_din_i1, fabric_dac3_din_i2, fabric_dac3_din_i3, fabric_dac3_din_i4, fabric_dac3_din_i5, fabric_dac3_din_i6, fabric_dac3_din_i7, fabric_dac3_din_i8, fabric_dac3_din_i9, fabric_dac3_din_i10
+, fabric_dac3_din_i11, fabric_dac3_din_i12, fabric_dac3_din_i13, fabric_dac3_reg_pwr_down_n_i, fabric_dac3_rstn_i, fabric_dac3_op_en_i, fabric_dac3_filt_en_i, fabric_dac3_comp_en_i, fabric_dac3_comp_ref_sel_i, fabric_dac3_comp_hyst_en_i, fabric_dac3_comp_in_sel_i1, fabric_dac3_comp_in_sel_i2, fabric_dac3_comp_in_sel_i3, fabric_dac3_comp_in_sel_i4, fabric_dac3_comp_out_o, fabric_cfg_dac3_reg_res_i1, fabric_cfg_dac3_reg_res_i2, fabric_cfg_dac3_reg_vref_select_i, fabric_cfg_dac3_reg_cm_select_i, fabric_cfg_dac3_sync_i, fabric_adc0_clk_i
+, fabric_adc0_arst_b_tmr_i1, fabric_adc0_arst_b_tmr_i2, fabric_adc0_arst_b_tmr_i3, fabric_adc0_pwr_down_b_tmr_i1, fabric_adc0_pwr_down_b_tmr_i2, fabric_adc0_pwr_down_b_tmr_i3, fabric_adc0_cal_start_i, fabric_adc0_cal_done_o, fabric_adc0_cal_p_overflow_o, fabric_adc0_cal_p_underflow_o, fabric_adc0_cal_n_overflow_o, fabric_adc0_cal_n_underflow_o, fabric_adc0_spare_i1, fabric_adc0_spare_i2, fabric_adc0_spare_i3, fabric_adc0_spare_i4, fabric_adc0_spare_i5, fabric_adc0_spare_i6, fabric_adc0_spare_i7, fabric_adc0_spare_i8, fabric_adc0_spare_i9
+, fabric_adc0_spare_i10, fabric_adc0_spare_i11, fabric_adc0_spare_i12, fabric_adc0_spare_i13, fabric_adc0_spare_i14, fabric_adc0_spare_i15, fabric_adc0_spare_i16, fabric_adc0_dft_test_mode_i1, fabric_adc0_dft_test_mode_i2, fabric_adc0_dft_scan_en_i, fabric_adc0_dft_si_i1, fabric_adc0_dft_si_i2, fabric_adc0_dft_si_i3, fabric_adc0_dft_si_i4, fabric_adc0_dft_si_i5, fabric_adc0_dft_si_i6, fabric_adc0_dft_si_i7, fabric_adc0_dft_si_i8, fabric_adc0_dft_si_i9, fabric_adc0_dft_si_i10, fabric_adc0_dft_si_i11
+, fabric_adc0_dft_si_i12, fabric_adc0_usr_cke_i, fabric_adc0_usr_arst_b_tmr_i1, fabric_adc0_usr_arst_b_tmr_i2, fabric_adc0_usr_arst_b_tmr_i3, fabric_adc0_usr_channel_i1, fabric_adc0_usr_channel_i2, fabric_adc0_usr_channel_i3, fabric_adc0_usr_conv_start_i, fabric_adc0_usr_conv_done_o, fabric_adc0_usr_sample_o1, fabric_adc0_usr_sample_o2, fabric_adc0_usr_sample_o3, fabric_adc0_usr_sample_o4, fabric_adc0_usr_sample_o5, fabric_adc0_usr_sample_o6, fabric_adc0_usr_sample_o7, fabric_adc0_usr_sample_o8, fabric_adc0_usr_sample_o9, fabric_adc0_usr_sample_o10, fabric_adc0_usr_sample_o11
+, fabric_adc0_usr_sample_o12, fabric_adc0_usr_sample_lsb_i1, fabric_adc0_usr_sample_lsb_i2, fabric_adc0_usr_sample_lsb_i3, fabric_adc0_usr_sample_lsb_i4, fabric_adc0_dbg_addr_i1, fabric_adc0_dbg_addr_i2, fabric_adc0_dbg_addr_i3, fabric_adc0_dbg_addr_i4, fabric_adc0_dbg_data_o1, fabric_adc0_dbg_data_o2, fabric_adc0_dbg_data_o3, fabric_adc0_dbg_data_o4, fabric_adc0_dbg_data_o5, fabric_adc0_dbg_data_o6, fabric_adc0_dbg_data_o7, fabric_adc0_dbg_data_o8, fabric_adc0_dbg_data_o9, fabric_adc0_dbg_data_o10, fabric_adc0_dbg_data_o11, fabric_adc0_dbg_data_o12
+, fabric_adc0_dbg_data_o13, fabric_adc0_dbg_data_o14, fabric_adc0_dbg_data_o15, fabric_adc0_dbg_data_o16, fabric_adc0_dbg_data_o17, fabric_adc0_dbg_data_o18, fabric_adc0_dbg_data_o19, fabric_adc0_dbg_data_o20, fabric_adc0_dbg_data_o21, fabric_adc0_dbg_data_o22, fabric_adc0_dbg_data_o23, fabric_adc0_dbg_data_o24, fabric_adc0_dbg_data_o25, fabric_adc0_dbg_data_o26, fabric_adc0_dbg_data_o27, fabric_adc0_dbg_data_o28, fabric_adc0_dbg_data_o29, fabric_adc0_dbg_data_o30, fabric_adc0_dbg_data_o31, fabric_adc0_dbg_data_o32, fabric_cfg_adc0_clk_cal_div_ratio_i1
+, fabric_cfg_adc0_clk_cal_div_ratio_i2, fabric_cfg_adc0_clk_cal_div_ratio_i3, fabric_cfg_adc0_clk_cal_div_ratio_i4, fabric_cfg_adc0_clk_cal_div_ratio_i5, fabric_cfg_adc0_conv_done_delayed_i, fabric_cfg_adc0_use_cdc_i, fabric_adc1_clk_i, fabric_adc1_arst_b_tmr_i1, fabric_adc1_arst_b_tmr_i2, fabric_adc1_arst_b_tmr_i3, fabric_adc1_pwr_down_b_tmr_i1, fabric_adc1_pwr_down_b_tmr_i2, fabric_adc1_pwr_down_b_tmr_i3, fabric_adc1_cal_start_i, fabric_adc1_cal_done_o, fabric_adc1_cal_p_overflow_o, fabric_adc1_cal_p_underflow_o, fabric_adc1_cal_n_overflow_o, fabric_adc1_cal_n_underflow_o, fabric_adc1_spare_i1, fabric_adc1_spare_i2
+, fabric_adc1_spare_i3, fabric_adc1_spare_i4, fabric_adc1_spare_i5, fabric_adc1_spare_i6, fabric_adc1_spare_i7, fabric_adc1_spare_i8, fabric_adc1_spare_i9, fabric_adc1_spare_i10, fabric_adc1_spare_i11, fabric_adc1_spare_i12, fabric_adc1_spare_i13, fabric_adc1_spare_i14, fabric_adc1_spare_i15, fabric_adc1_spare_i16, fabric_adc1_dft_test_mode_i1, fabric_adc1_dft_test_mode_i2, fabric_adc1_dft_scan_en_i, fabric_adc1_dft_si_i1, fabric_adc1_dft_si_i2, fabric_adc1_dft_si_i3, fabric_adc1_dft_si_i4
+, fabric_adc1_dft_si_i5, fabric_adc1_dft_si_i6, fabric_adc1_dft_si_i7, fabric_adc1_dft_si_i8, fabric_adc1_dft_si_i9, fabric_adc1_dft_si_i10, fabric_adc1_dft_si_i11, fabric_adc1_dft_si_i12, fabric_adc1_usr_cke_i, fabric_adc1_usr_arst_b_tmr_i1, fabric_adc1_usr_arst_b_tmr_i2, fabric_adc1_usr_arst_b_tmr_i3, fabric_adc1_usr_channel_i1, fabric_adc1_usr_channel_i2, fabric_adc1_usr_channel_i3, fabric_adc1_usr_conv_start_i, fabric_adc1_usr_conv_done_o, fabric_adc1_usr_sample_o1, fabric_adc1_usr_sample_o2, fabric_adc1_usr_sample_o3, fabric_adc1_usr_sample_o4
+, fabric_adc1_usr_sample_o5, fabric_adc1_usr_sample_o6, fabric_adc1_usr_sample_o7, fabric_adc1_usr_sample_o8, fabric_adc1_usr_sample_o9, fabric_adc1_usr_sample_o10, fabric_adc1_usr_sample_o11, fabric_adc1_usr_sample_o12, fabric_adc1_usr_sample_lsb_i1, fabric_adc1_usr_sample_lsb_i2, fabric_adc1_usr_sample_lsb_i3, fabric_adc1_usr_sample_lsb_i4, fabric_adc1_dbg_addr_i1, fabric_adc1_dbg_addr_i2, fabric_adc1_dbg_addr_i3, fabric_adc1_dbg_addr_i4, fabric_adc1_dbg_data_o1, fabric_adc1_dbg_data_o2, fabric_adc1_dbg_data_o3, fabric_adc1_dbg_data_o4, fabric_adc1_dbg_data_o5
+, fabric_adc1_dbg_data_o6, fabric_adc1_dbg_data_o7, fabric_adc1_dbg_data_o8, fabric_adc1_dbg_data_o9, fabric_adc1_dbg_data_o10, fabric_adc1_dbg_data_o11, fabric_adc1_dbg_data_o12, fabric_adc1_dbg_data_o13, fabric_adc1_dbg_data_o14, fabric_adc1_dbg_data_o15, fabric_adc1_dbg_data_o16, fabric_adc1_dbg_data_o17, fabric_adc1_dbg_data_o18, fabric_adc1_dbg_data_o19, fabric_adc1_dbg_data_o20, fabric_adc1_dbg_data_o21, fabric_adc1_dbg_data_o22, fabric_adc1_dbg_data_o23, fabric_adc1_dbg_data_o24, fabric_adc1_dbg_data_o25, fabric_adc1_dbg_data_o26
+, fabric_adc1_dbg_data_o27, fabric_adc1_dbg_data_o28, fabric_adc1_dbg_data_o29, fabric_adc1_dbg_data_o30, fabric_adc1_dbg_data_o31, fabric_adc1_dbg_data_o32, fabric_cfg_adc1_clk_cal_div_ratio_i1, fabric_cfg_adc1_clk_cal_div_ratio_i2, fabric_cfg_adc1_clk_cal_div_ratio_i3, fabric_cfg_adc1_clk_cal_div_ratio_i4, fabric_cfg_adc1_clk_cal_div_ratio_i5, fabric_cfg_adc1_conv_done_delayed_i, fabric_cfg_adc1_use_cdc_i, fabric_adc2_clk_i, fabric_adc2_arst_b_tmr_i1, fabric_adc2_arst_b_tmr_i2, fabric_adc2_arst_b_tmr_i3, fabric_adc2_pwr_down_b_tmr_i1, fabric_adc2_pwr_down_b_tmr_i2, fabric_adc2_pwr_down_b_tmr_i3, fabric_adc2_cal_start_i
+, fabric_adc2_cal_done_o, fabric_adc2_cal_p_overflow_o, fabric_adc2_cal_p_underflow_o, fabric_adc2_cal_n_overflow_o, fabric_adc2_cal_n_underflow_o, fabric_adc2_spare_i1, fabric_adc2_spare_i2, fabric_adc2_spare_i3, fabric_adc2_spare_i4, fabric_adc2_spare_i5, fabric_adc2_spare_i6, fabric_adc2_spare_i7, fabric_adc2_spare_i8, fabric_adc2_spare_i9, fabric_adc2_spare_i10, fabric_adc2_spare_i11, fabric_adc2_spare_i12, fabric_adc2_spare_i13, fabric_adc2_spare_i14, fabric_adc2_spare_i15, fabric_adc2_spare_i16
+, fabric_adc2_dft_test_mode_i1, fabric_adc2_dft_test_mode_i2, fabric_adc2_dft_scan_en_i, fabric_adc2_dft_si_i1, fabric_adc2_dft_si_i2, fabric_adc2_dft_si_i3, fabric_adc2_dft_si_i4, fabric_adc2_dft_si_i5, fabric_adc2_dft_si_i6, fabric_adc2_dft_si_i7, fabric_adc2_dft_si_i8, fabric_adc2_dft_si_i9, fabric_adc2_dft_si_i10, fabric_adc2_dft_si_i11, fabric_adc2_dft_si_i12, fabric_adc2_usr_cke_i, fabric_adc2_usr_arst_b_tmr_i1, fabric_adc2_usr_arst_b_tmr_i2, fabric_adc2_usr_arst_b_tmr_i3, fabric_adc2_usr_channel_i1, fabric_adc2_usr_channel_i2
+, fabric_adc2_usr_channel_i3, fabric_adc2_usr_conv_start_i, fabric_adc2_usr_conv_done_o, fabric_adc2_usr_sample_o1, fabric_adc2_usr_sample_o2, fabric_adc2_usr_sample_o3, fabric_adc2_usr_sample_o4, fabric_adc2_usr_sample_o5, fabric_adc2_usr_sample_o6, fabric_adc2_usr_sample_o7, fabric_adc2_usr_sample_o8, fabric_adc2_usr_sample_o9, fabric_adc2_usr_sample_o10, fabric_adc2_usr_sample_o11, fabric_adc2_usr_sample_o12, fabric_adc2_usr_sample_lsb_i1, fabric_adc2_usr_sample_lsb_i2, fabric_adc2_usr_sample_lsb_i3, fabric_adc2_usr_sample_lsb_i4, fabric_adc2_dbg_addr_i1, fabric_adc2_dbg_addr_i2
+, fabric_adc2_dbg_addr_i3, fabric_adc2_dbg_addr_i4, fabric_adc2_dbg_data_o1, fabric_adc2_dbg_data_o2, fabric_adc2_dbg_data_o3, fabric_adc2_dbg_data_o4, fabric_adc2_dbg_data_o5, fabric_adc2_dbg_data_o6, fabric_adc2_dbg_data_o7, fabric_adc2_dbg_data_o8, fabric_adc2_dbg_data_o9, fabric_adc2_dbg_data_o10, fabric_adc2_dbg_data_o11, fabric_adc2_dbg_data_o12, fabric_adc2_dbg_data_o13, fabric_adc2_dbg_data_o14, fabric_adc2_dbg_data_o15, fabric_adc2_dbg_data_o16, fabric_adc2_dbg_data_o17, fabric_adc2_dbg_data_o18, fabric_adc2_dbg_data_o19
+, fabric_adc2_dbg_data_o20, fabric_adc2_dbg_data_o21, fabric_adc2_dbg_data_o22, fabric_adc2_dbg_data_o23, fabric_adc2_dbg_data_o24, fabric_adc2_dbg_data_o25, fabric_adc2_dbg_data_o26, fabric_adc2_dbg_data_o27, fabric_adc2_dbg_data_o28, fabric_adc2_dbg_data_o29, fabric_adc2_dbg_data_o30, fabric_adc2_dbg_data_o31, fabric_adc2_dbg_data_o32, fabric_cfg_adc2_clk_cal_div_ratio_i1, fabric_cfg_adc2_clk_cal_div_ratio_i2, fabric_cfg_adc2_clk_cal_div_ratio_i3, fabric_cfg_adc2_clk_cal_div_ratio_i4, fabric_cfg_adc2_clk_cal_div_ratio_i5, fabric_cfg_adc2_conv_done_delayed_i, fabric_cfg_adc2_use_cdc_i, fabric_adc3_clk_i
+, fabric_adc3_arst_b_tmr_i1, fabric_adc3_arst_b_tmr_i2, fabric_adc3_arst_b_tmr_i3, fabric_adc3_pwr_down_b_tmr_i1, fabric_adc3_pwr_down_b_tmr_i2, fabric_adc3_pwr_down_b_tmr_i3, fabric_adc3_cal_start_i, fabric_adc3_cal_done_o, fabric_adc3_cal_p_overflow_o, fabric_adc3_cal_p_underflow_o, fabric_adc3_cal_n_overflow_o, fabric_adc3_cal_n_underflow_o, fabric_adc3_spare_i1, fabric_adc3_spare_i2, fabric_adc3_spare_i3, fabric_adc3_spare_i4, fabric_adc3_spare_i5, fabric_adc3_spare_i6, fabric_adc3_spare_i7, fabric_adc3_spare_i8, fabric_adc3_spare_i9
+, fabric_adc3_spare_i10, fabric_adc3_spare_i11, fabric_adc3_spare_i12, fabric_adc3_spare_i13, fabric_adc3_spare_i14, fabric_adc3_spare_i15, fabric_adc3_spare_i16, fabric_adc3_dft_test_mode_i1, fabric_adc3_dft_test_mode_i2, fabric_adc3_dft_scan_en_i, fabric_adc3_dft_si_i1, fabric_adc3_dft_si_i2, fabric_adc3_dft_si_i3, fabric_adc3_dft_si_i4, fabric_adc3_dft_si_i5, fabric_adc3_dft_si_i6, fabric_adc3_dft_si_i7, fabric_adc3_dft_si_i8, fabric_adc3_dft_si_i9, fabric_adc3_dft_si_i10, fabric_adc3_dft_si_i11
+, fabric_adc3_dft_si_i12, fabric_adc3_usr_cke_i, fabric_adc3_usr_arst_b_tmr_i1, fabric_adc3_usr_arst_b_tmr_i2, fabric_adc3_usr_arst_b_tmr_i3, fabric_adc3_usr_channel_i1, fabric_adc3_usr_channel_i2, fabric_adc3_usr_channel_i3, fabric_adc3_usr_conv_start_i, fabric_adc3_usr_conv_done_o, fabric_adc3_usr_sample_o1, fabric_adc3_usr_sample_o2, fabric_adc3_usr_sample_o3, fabric_adc3_usr_sample_o4, fabric_adc3_usr_sample_o5, fabric_adc3_usr_sample_o6, fabric_adc3_usr_sample_o7, fabric_adc3_usr_sample_o8, fabric_adc3_usr_sample_o9, fabric_adc3_usr_sample_o10, fabric_adc3_usr_sample_o11
+, fabric_adc3_usr_sample_o12, fabric_adc3_usr_sample_lsb_i1, fabric_adc3_usr_sample_lsb_i2, fabric_adc3_usr_sample_lsb_i3, fabric_adc3_usr_sample_lsb_i4, fabric_adc3_dbg_addr_i1, fabric_adc3_dbg_addr_i2, fabric_adc3_dbg_addr_i3, fabric_adc3_dbg_addr_i4, fabric_adc3_dbg_data_o1, fabric_adc3_dbg_data_o2, fabric_adc3_dbg_data_o3, fabric_adc3_dbg_data_o4, fabric_adc3_dbg_data_o5, fabric_adc3_dbg_data_o6, fabric_adc3_dbg_data_o7, fabric_adc3_dbg_data_o8, fabric_adc3_dbg_data_o9, fabric_adc3_dbg_data_o10, fabric_adc3_dbg_data_o11, fabric_adc3_dbg_data_o12
+, fabric_adc3_dbg_data_o13, fabric_adc3_dbg_data_o14, fabric_adc3_dbg_data_o15, fabric_adc3_dbg_data_o16, fabric_adc3_dbg_data_o17, fabric_adc3_dbg_data_o18, fabric_adc3_dbg_data_o19, fabric_adc3_dbg_data_o20, fabric_adc3_dbg_data_o21, fabric_adc3_dbg_data_o22, fabric_adc3_dbg_data_o23, fabric_adc3_dbg_data_o24, fabric_adc3_dbg_data_o25, fabric_adc3_dbg_data_o26, fabric_adc3_dbg_data_o27, fabric_adc3_dbg_data_o28, fabric_adc3_dbg_data_o29, fabric_adc3_dbg_data_o30, fabric_adc3_dbg_data_o31, fabric_adc3_dbg_data_o32, fabric_cfg_adc3_clk_cal_div_ratio_i1
+, fabric_cfg_adc3_clk_cal_div_ratio_i2, fabric_cfg_adc3_clk_cal_div_ratio_i3, fabric_cfg_adc3_clk_cal_div_ratio_i4, fabric_cfg_adc3_clk_cal_div_ratio_i5, fabric_cfg_adc3_conv_done_delayed_i, fabric_cfg_adc3_use_cdc_i, fabric_direct0_clock_fabric_i1, fabric_direct0_clock_fabric_i2, fabric_direct0_clock_fabric_i3, fabric_direct0_clock_fabric_i4, fabric_direct0_oe_i1, fabric_direct0_oe_i2, fabric_direct0_oe_i3, fabric_direct0_oe_i4, fabric_direct0_oe_i5, fabric_direct0_oe_i6, fabric_direct0_oe_i7, fabric_direct0_oe_i8, fabric_direct0_oe_i9, fabric_direct0_oe_i10, fabric_direct0_oe_i11
+, fabric_direct0_oe_i12, fabric_direct0_oe_i13, fabric_direct0_oe_i14, fabric_direct0_oe_i15, fabric_direct0_oe_i16, fabric_direct0_oe_i17, fabric_direct0_oe_i18, fabric_direct0_oe_i19, fabric_direct0_oe_i20, fabric_direct0_oe_i21, fabric_direct0_oe_i22, fabric_direct0_oe_i23, fabric_direct0_oe_i24, fabric_direct0_oe_ena_i1, fabric_direct0_oe_ena_i2, fabric_direct0_oe_ena_i3, fabric_direct0_oe_ena_i4, fabric_direct0_oe_ena_i5, fabric_direct0_oe_ena_i6, fabric_direct0_oe_ena_i7, fabric_direct0_oe_ena_i8
+, fabric_direct0_oe_ena_i9, fabric_direct0_oe_ena_i10, fabric_direct0_oe_ena_i11, fabric_direct0_oe_ena_i12, fabric_direct0_oe_ena_i13, fabric_direct0_oe_ena_i14, fabric_direct0_oe_ena_i15, fabric_direct0_oe_ena_i16, fabric_direct0_oe_ena_i17, fabric_direct0_oe_ena_i18, fabric_direct0_oe_ena_i19, fabric_direct0_oe_ena_i20, fabric_direct0_oe_ena_i21, fabric_direct0_oe_ena_i22, fabric_direct0_oe_ena_i23, fabric_direct0_oe_ena_i24, fabric_direct0_oe_rs_i1, fabric_direct0_oe_rs_i2, fabric_direct0_oe_rs_i3, fabric_direct0_oe_rs_i4, fabric_direct0_oe_rs_i5
+, fabric_direct0_oe_rs_i6, fabric_direct0_oe_rs_i7, fabric_direct0_oe_rs_i8, fabric_direct0_oe_rs_i9, fabric_direct0_oe_rs_i10, fabric_direct0_oe_rs_i11, fabric_direct0_oe_rs_i12, fabric_direct0_oe_rs_i13, fabric_direct0_oe_rs_i14, fabric_direct0_oe_rs_i15, fabric_direct0_oe_rs_i16, fabric_direct0_oe_rs_i17, fabric_direct0_oe_rs_i18, fabric_direct0_oe_rs_i19, fabric_direct0_oe_rs_i20, fabric_direct0_oe_rs_i21, fabric_direct0_oe_rs_i22, fabric_direct0_oe_rs_i23, fabric_direct0_oe_rs_i24, fabric_direct0_do_i1, fabric_direct0_do_i2
+, fabric_direct0_do_i3, fabric_direct0_do_i4, fabric_direct0_do_i5, fabric_direct0_do_i6, fabric_direct0_do_i7, fabric_direct0_do_i8, fabric_direct0_do_i9, fabric_direct0_do_i10, fabric_direct0_do_i11, fabric_direct0_do_i12, fabric_direct0_do_i13, fabric_direct0_do_i14, fabric_direct0_do_i15, fabric_direct0_do_i16, fabric_direct0_do_i17, fabric_direct0_do_i18, fabric_direct0_do_i19, fabric_direct0_do_i20, fabric_direct0_do_i21, fabric_direct0_do_i22, fabric_direct0_do_i23
+, fabric_direct0_do_i24, fabric_direct0_do_ena_i1, fabric_direct0_do_ena_i2, fabric_direct0_do_ena_i3, fabric_direct0_do_ena_i4, fabric_direct0_do_ena_i5, fabric_direct0_do_ena_i6, fabric_direct0_do_ena_i7, fabric_direct0_do_ena_i8, fabric_direct0_do_ena_i9, fabric_direct0_do_ena_i10, fabric_direct0_do_ena_i11, fabric_direct0_do_ena_i12, fabric_direct0_do_ena_i13, fabric_direct0_do_ena_i14, fabric_direct0_do_ena_i15, fabric_direct0_do_ena_i16, fabric_direct0_do_ena_i17, fabric_direct0_do_ena_i18, fabric_direct0_do_ena_i19, fabric_direct0_do_ena_i20
+, fabric_direct0_do_ena_i21, fabric_direct0_do_ena_i22, fabric_direct0_do_ena_i23, fabric_direct0_do_ena_i24, fabric_direct0_do_rs_i1, fabric_direct0_do_rs_i2, fabric_direct0_do_rs_i3, fabric_direct0_do_rs_i4, fabric_direct0_do_rs_i5, fabric_direct0_do_rs_i6, fabric_direct0_do_rs_i7, fabric_direct0_do_rs_i8, fabric_direct0_do_rs_i9, fabric_direct0_do_rs_i10, fabric_direct0_do_rs_i11, fabric_direct0_do_rs_i12, fabric_direct0_do_rs_i13, fabric_direct0_do_rs_i14, fabric_direct0_do_rs_i15, fabric_direct0_do_rs_i16, fabric_direct0_do_rs_i17
+, fabric_direct0_do_rs_i18, fabric_direct0_do_rs_i19, fabric_direct0_do_rs_i20, fabric_direct0_do_rs_i21, fabric_direct0_do_rs_i22, fabric_direct0_do_rs_i23, fabric_direct0_do_rs_i24, fabric_direct0_di_o1, fabric_direct0_di_o2, fabric_direct0_di_o3, fabric_direct0_di_o4, fabric_direct0_di_o5, fabric_direct0_di_o6, fabric_direct0_di_o7, fabric_direct0_di_o8, fabric_direct0_di_o9, fabric_direct0_di_o10, fabric_direct0_di_o11, fabric_direct0_di_o12, fabric_direct0_di_o13, fabric_direct0_di_o14
+, fabric_direct0_di_o15, fabric_direct0_di_o16, fabric_direct0_di_o17, fabric_direct0_di_o18, fabric_direct0_di_o19, fabric_direct0_di_o20, fabric_direct0_di_o21, fabric_direct0_di_o22, fabric_direct0_di_o23, fabric_direct0_di_o24, fabric_direct0_di_ena_i1, fabric_direct0_di_ena_i2, fabric_direct0_di_ena_i3, fabric_direct0_di_ena_i4, fabric_direct0_di_ena_i5, fabric_direct0_di_ena_i6, fabric_direct0_di_ena_i7, fabric_direct0_di_ena_i8, fabric_direct0_di_ena_i9, fabric_direct0_di_ena_i10, fabric_direct0_di_ena_i11
+, fabric_direct0_di_ena_i12, fabric_direct0_di_ena_i13, fabric_direct0_di_ena_i14, fabric_direct0_di_ena_i15, fabric_direct0_di_ena_i16, fabric_direct0_di_ena_i17, fabric_direct0_di_ena_i18, fabric_direct0_di_ena_i19, fabric_direct0_di_ena_i20, fabric_direct0_di_ena_i21, fabric_direct0_di_ena_i22, fabric_direct0_di_ena_i23, fabric_direct0_di_ena_i24, fabric_direct0_di_rs_i1, fabric_direct0_di_rs_i2, fabric_direct0_di_rs_i3, fabric_direct0_di_rs_i4, fabric_direct0_di_rs_i5, fabric_direct0_di_rs_i6, fabric_direct0_di_rs_i7, fabric_direct0_di_rs_i8
+, fabric_direct0_di_rs_i9, fabric_direct0_di_rs_i10, fabric_direct0_di_rs_i11, fabric_direct0_di_rs_i12, fabric_direct0_di_rs_i13, fabric_direct0_di_rs_i14, fabric_direct0_di_rs_i15, fabric_direct0_di_rs_i16, fabric_direct0_di_rs_i17, fabric_direct0_di_rs_i18, fabric_direct0_di_rs_i19, fabric_direct0_di_rs_i20, fabric_direct0_di_rs_i21, fabric_direct0_di_rs_i22, fabric_direct0_di_rs_i23, fabric_direct0_di_rs_i24, fabric_direct0_cfg_bank_i1, fabric_direct0_cfg_bank_i2, fabric_direct0_cfg_bank_i3, fabric_direct0_cfg_bank_i4, fabric_direct0_cfg_pad_i1
+, fabric_direct0_cfg_pad_i2, fabric_direct0_cfg_pad_i3, fabric_direct0_cfg_pad_i4, fabric_direct0_cfg_pad_i5, fabric_direct0_cfg_pad_i6, fabric_direct0_cfg_pad_i7, fabric_direct0_cfg_pad_i8, fabric_direct0_cfg_pad_i9, fabric_direct0_cfg_pad_i10, fabric_direct0_cfg_pad_i11, fabric_direct0_cfg_pad_i12, fabric_direct0_cfg_pad_i13, fabric_direct0_cfg_pad_i14, fabric_direct0_cfg_pad_i15, fabric_direct0_cfg_pad_i16, fabric_direct0_cfg_pad_i17, fabric_direct0_cfg_pad_i18, fabric_direct0_cfg_pad_i19, fabric_direct0_cfg_pad_i20, fabric_direct0_cfg_pad_i21, fabric_direct0_cfg_pad_i22
+, fabric_direct0_cfg_pad_i23, fabric_direct0_cfg_pad_i24, fabric_direct0_cfg_pad_i25, fabric_direct0_cfg_pad_i26, fabric_direct0_cfg_pad_i27, fabric_direct0_cfg_pad_i28, fabric_direct0_cfg_pad_i29, fabric_direct0_cfg_pad_i30, fabric_direct0_cfg_pad_i31, fabric_direct0_cfg_pad_i32, fabric_direct0_cfg_pad_i33, fabric_direct0_cfg_pad_i34, fabric_direct0_cfg_pad_i35, fabric_direct0_cfg_pad_i36, fabric_direct0_cfg_pad_i37, fabric_direct0_cfg_pad_i38, fabric_direct0_cfg_pad_i39, fabric_direct0_cfg_pad_i40, fabric_direct0_cfg_pad_i41, fabric_direct0_cfg_pad_i42, fabric_direct0_cfg_pad_i43
+, fabric_direct0_cfg_pad_i44, fabric_direct0_cfg_pad_i45, fabric_direct0_cfg_pad_i46, fabric_direct0_cfg_pad_i47, fabric_direct0_cfg_pad_i48, fabric_direct0_cfg_pad_i49, fabric_direct0_cfg_pad_i50, fabric_direct0_cfg_pad_i51, fabric_direct0_cfg_pad_i52, fabric_direct0_cfg_pad_i53, fabric_direct0_cfg_pad_i54, fabric_direct0_cfg_pad_i55, fabric_direct0_cfg_pad_i56, fabric_direct0_cfg_pad_i57, fabric_direct0_cfg_pad_i58, fabric_direct0_cfg_pad_i59, fabric_direct0_cfg_pad_i60, fabric_direct0_cfg_pad_i61, fabric_direct0_cfg_pad_i62, fabric_direct0_cfg_pad_i63, fabric_direct0_cfg_pad_i64
+, fabric_direct0_cfg_pad_i65, fabric_direct0_cfg_pad_i66, fabric_direct0_cfg_pad_i67, fabric_direct0_cfg_pad_i68, fabric_direct0_cfg_pad_i69, fabric_direct0_cfg_pad_i70, fabric_direct0_cfg_pad_i71, fabric_direct0_cfg_pad_i72, fabric_direct0_cfg_pad_i73, fabric_direct0_cfg_pad_i74, fabric_direct0_cfg_pad_i75, fabric_direct0_cfg_pad_i76, fabric_direct0_cfg_pad_i77, fabric_direct0_cfg_pad_i78, fabric_direct0_cfg_pad_i79, fabric_direct0_cfg_pad_i80, fabric_direct0_cfg_pad_i81, fabric_direct0_cfg_pad_i82, fabric_direct0_cfg_pad_i83, fabric_direct0_cfg_pad_i84, fabric_direct0_cfg_pad_i85
+, fabric_direct0_cfg_pad_i86, fabric_direct0_cfg_pad_i87, fabric_direct0_cfg_pad_i88, fabric_direct0_cfg_pad_i89, fabric_direct0_cfg_pad_i90, fabric_direct0_cfg_pad_i91, fabric_direct0_cfg_pad_i92, fabric_direct0_cfg_pad_i93, fabric_direct0_cfg_pad_i94, fabric_direct0_cfg_pad_i95, fabric_direct0_cfg_pad_i96, fabric_direct0_cfg_pad_i97, fabric_direct0_cfg_pad_i98, fabric_direct0_cfg_pad_i99, fabric_direct0_cfg_pad_i100, fabric_direct0_cfg_pad_i101, fabric_direct0_cfg_pad_i102, fabric_direct0_cfg_pad_i103, fabric_direct0_cfg_pad_i104, fabric_direct0_cfg_pad_i105, fabric_direct0_cfg_pad_i106
+, fabric_direct0_cfg_pad_i107, fabric_direct0_cfg_pad_i108, fabric_direct0_cfg_pad_i109, fabric_direct0_cfg_pad_i110, fabric_direct0_cfg_pad_i111, fabric_direct0_cfg_pad_i112, fabric_direct0_cfg_pad_i113, fabric_direct0_cfg_pad_i114, fabric_direct0_cfg_pad_i115, fabric_direct0_cfg_pad_i116, fabric_direct0_cfg_pad_i117, fabric_direct0_cfg_pad_i118, fabric_direct0_cfg_pad_i119, fabric_direct0_cfg_pad_i120, fabric_direct0_cfg_pad_i121, fabric_direct0_cfg_pad_i122, fabric_direct0_cfg_pad_i123, fabric_direct0_cfg_pad_i124, fabric_direct0_cfg_pad_i125, fabric_direct0_cfg_pad_i126, fabric_direct0_cfg_pad_i127
+, fabric_direct0_cfg_pad_i128, fabric_direct0_cfg_pad_i129, fabric_direct0_cfg_pad_i130, fabric_direct0_cfg_pad_i131, fabric_direct0_cfg_pad_i132, fabric_direct0_cfg_pad_i133, fabric_direct0_cfg_pad_i134, fabric_direct0_cfg_pad_i135, fabric_direct0_cfg_pad_i136, fabric_direct0_cfg_pad_i137, fabric_direct0_cfg_pad_i138, fabric_direct0_cfg_pad_i139, fabric_direct0_cfg_pad_i140, fabric_direct0_cfg_pad_i141, fabric_direct0_cfg_pad_i142, fabric_direct0_cfg_pad_i143, fabric_direct0_cfg_pad_i144, fabric_direct0_cfg_pad_i145, fabric_direct0_cfg_pad_i146, fabric_direct0_cfg_pad_i147, fabric_direct0_cfg_pad_i148
+, fabric_direct0_cfg_pad_i149, fabric_direct0_cfg_pad_i150, fabric_direct0_cfg_pad_i151, fabric_direct0_cfg_pad_i152, fabric_direct0_cfg_pad_i153, fabric_direct0_cfg_pad_i154, fabric_direct0_cfg_pad_i155, fabric_direct0_cfg_pad_i156, fabric_direct0_cfg_pad_i157, fabric_direct0_cfg_pad_i158, fabric_direct0_cfg_pad_i159, fabric_direct0_cfg_pad_i160, fabric_direct0_cfg_pad_i161, fabric_direct0_cfg_pad_i162, fabric_direct0_cfg_pad_i163, fabric_direct0_cfg_pad_i164, fabric_direct0_cfg_pad_i165, fabric_direct0_cfg_pad_i166, fabric_direct0_cfg_pad_i167, fabric_direct0_cfg_pad_i168, fabric_direct0_cfg_pad_i169
+, fabric_direct0_cfg_pad_i170, fabric_direct0_cfg_pad_i171, fabric_direct0_cfg_pad_i172, fabric_direct0_cfg_pad_i173, fabric_direct0_cfg_pad_i174, fabric_direct0_cfg_pad_i175, fabric_direct0_cfg_pad_i176, fabric_direct0_cfg_pad_i177, fabric_direct0_cfg_pad_i178, fabric_direct0_cfg_pad_i179, fabric_direct0_cfg_pad_i180, fabric_direct0_cfg_pad_i181, fabric_direct0_cfg_pad_i182, fabric_direct0_cfg_pad_i183, fabric_direct0_cfg_pad_i184, fabric_direct0_cfg_pad_i185, fabric_direct0_cfg_pad_i186, fabric_direct0_cfg_pad_i187, fabric_direct0_cfg_pad_i188, fabric_direct0_cfg_pad_i189, fabric_direct0_cfg_pad_i190
+, fabric_direct0_cfg_pad_i191, fabric_direct0_cfg_pad_i192, fabric_direct0_cfg_pad_i193, fabric_direct0_cfg_pad_i194, fabric_direct0_cfg_pad_i195, fabric_direct0_cfg_pad_i196, fabric_direct0_cfg_pad_i197, fabric_direct0_cfg_pad_i198, fabric_direct0_cfg_pad_i199, fabric_direct0_cfg_pad_i200, fabric_direct0_cfg_pad_i201, fabric_direct0_cfg_pad_i202, fabric_direct0_cfg_pad_i203, fabric_direct0_cfg_pad_i204, fabric_direct0_cfg_pad_i205, fabric_direct0_cfg_pad_i206, fabric_direct0_cfg_pad_i207, fabric_direct0_cfg_pad_i208, fabric_direct0_cfg_pad_i209, fabric_direct0_cfg_pad_i210, fabric_direct0_cfg_pad_i211
+, fabric_direct0_cfg_pad_i212, fabric_direct0_cfg_pad_i213, fabric_direct0_cfg_pad_i214, fabric_direct0_cfg_pad_i215, fabric_direct0_cfg_pad_i216, fabric_direct0_cfg_pad_i217, fabric_direct0_cfg_pad_i218, fabric_direct0_cfg_pad_i219, fabric_direct0_cfg_pad_i220, fabric_direct0_cfg_pad_i221, fabric_direct0_cfg_pad_i222, fabric_direct0_cfg_pad_i223, fabric_direct0_cfg_pad_i224, fabric_direct0_cfg_pad_i225, fabric_direct0_cfg_pad_i226, fabric_direct0_cfg_pad_i227, fabric_direct0_cfg_pad_i228, fabric_direct0_cfg_pad_i229, fabric_direct0_cfg_pad_i230, fabric_direct0_cfg_pad_i231, fabric_direct0_cfg_pad_i232
+, fabric_direct0_cfg_pad_i233, fabric_direct0_cfg_pad_i234, fabric_direct0_cfg_pad_i235, fabric_direct0_cfg_pad_i236, fabric_direct0_cfg_pad_i237, fabric_direct0_cfg_pad_i238, fabric_direct0_cfg_pad_i239, fabric_direct0_cfg_pad_i240, fabric_direct0_cfg_pad_i241, fabric_direct0_cfg_pad_i242, fabric_direct0_cfg_pad_i243, fabric_direct0_cfg_pad_i244, fabric_direct0_cfg_pad_i245, fabric_direct0_cfg_pad_i246, fabric_direct0_cfg_pad_i247, fabric_direct0_cfg_pad_i248, fabric_direct0_cfg_pad_i249, fabric_direct0_cfg_pad_i250, fabric_direct0_cfg_pad_i251, fabric_direct0_cfg_pad_i252, fabric_direct0_cfg_pad_i253
+, fabric_direct0_cfg_pad_i254, fabric_direct0_cfg_pad_i255, fabric_direct0_cfg_pad_i256, fabric_direct0_cfg_pad_i257, fabric_direct0_cfg_pad_i258, fabric_direct0_cfg_pad_i259, fabric_direct0_cfg_pad_i260, fabric_direct0_cfg_pad_i261, fabric_direct0_cfg_pad_i262, fabric_direct0_cfg_pad_i263, fabric_direct0_cfg_pad_i264, fabric_direct0_cfg_pad_i265, fabric_direct0_cfg_pad_i266, fabric_direct0_cfg_pad_i267, fabric_direct0_cfg_pad_i268, fabric_direct0_cfg_pad_i269, fabric_direct0_cfg_pad_i270, fabric_direct0_cfg_pad_i271, fabric_direct0_cfg_pad_i272, fabric_direct0_cfg_pad_i273, fabric_direct0_cfg_pad_i274
+, fabric_direct0_cfg_pad_i275, fabric_direct0_cfg_pad_i276, fabric_direct0_cfg_pad_i277, fabric_direct0_cfg_pad_i278, fabric_direct0_cfg_pad_i279, fabric_direct0_cfg_pad_i280, fabric_direct0_cfg_pad_i281, fabric_direct0_cfg_pad_i282, fabric_direct0_cfg_pad_i283, fabric_direct0_cfg_pad_i284, fabric_direct0_cfg_pad_i285, fabric_direct0_cfg_pad_i286, fabric_direct0_cfg_pad_i287, fabric_direct0_cfg_pad_i288, fabric_direct0_cfg_pad_i289, fabric_direct0_cfg_pad_i290, fabric_direct0_cfg_pad_i291, fabric_direct0_cfg_pad_i292, fabric_direct0_cfg_pad_i293, fabric_direct0_cfg_pad_i294, fabric_direct0_cfg_pad_i295
+, fabric_direct0_cfg_pad_i296, fabric_direct0_cfg_pad_i297, fabric_direct0_cfg_pad_i298, fabric_direct0_cfg_pad_i299, fabric_direct0_cfg_pad_i300, fabric_direct0_cfg_pad_i301, fabric_direct0_cfg_pad_i302, fabric_direct0_cfg_pad_i303, fabric_direct0_cfg_pad_i304, fabric_direct0_cfg_pad_i305, fabric_direct0_cfg_pad_i306, fabric_direct0_cfg_pad_i307, fabric_direct0_cfg_pad_i308, fabric_direct0_cfg_pad_i309, fabric_direct0_cfg_pad_i310, fabric_direct0_cfg_pad_i311, fabric_direct0_cfg_pad_i312, fabric_direct0_cfg_pad_i313, fabric_direct0_cfg_pad_i314, fabric_direct0_cfg_pad_i315, fabric_direct0_cfg_pad_i316
+, fabric_direct0_cfg_pad_i317, fabric_direct0_cfg_pad_i318, fabric_direct0_cfg_pad_i319, fabric_direct0_cfg_pad_i320, fabric_direct0_cfg_pad_i321, fabric_direct0_cfg_pad_i322, fabric_direct0_cfg_pad_i323, fabric_direct0_cfg_pad_i324, fabric_direct0_cfg_pad_i325, fabric_direct0_cfg_pad_i326, fabric_direct0_cfg_pad_i327, fabric_direct0_cfg_pad_i328, fabric_direct0_cfg_pad_i329, fabric_direct0_cfg_pad_i330, fabric_direct0_cfg_pad_i331, fabric_direct0_cfg_pad_i332, fabric_direct0_cfg_pad_i333, fabric_direct0_cfg_pad_i334, fabric_direct0_cfg_pad_i335, fabric_direct0_cfg_pad_i336, fabric_direct0_cfg_pad_i337
+, fabric_direct0_cfg_pad_i338, fabric_direct0_cfg_pad_i339, fabric_direct0_cfg_pad_i340, fabric_direct0_cfg_pad_i341, fabric_direct0_cfg_pad_i342, fabric_direct0_cfg_pad_i343, fabric_direct0_cfg_pad_i344, fabric_direct0_cfg_pad_i345, fabric_direct0_cfg_pad_i346, fabric_direct0_cfg_pad_i347, fabric_direct0_cfg_pad_i348, fabric_direct0_cfg_pad_i349, fabric_direct0_cfg_pad_i350, fabric_direct0_cfg_pad_i351, fabric_direct0_cfg_pad_i352, fabric_direct0_cfg_pad_i353, fabric_direct0_cfg_pad_i354, fabric_direct0_cfg_pad_i355, fabric_direct0_cfg_pad_i356, fabric_direct0_cfg_pad_i357, fabric_direct0_cfg_pad_i358
+, fabric_direct0_cfg_pad_i359, fabric_direct0_cfg_pad_i360, fabric_direct0_cfg_pad_i361, fabric_direct0_cfg_pad_i362, fabric_direct0_cfg_pad_i363, fabric_direct0_cfg_pad_i364, fabric_direct0_cfg_pad_i365, fabric_direct0_cfg_pad_i366, fabric_direct0_cfg_pad_i367, fabric_direct0_cfg_pad_i368, fabric_direct0_cfg_pad_i369, fabric_direct0_cfg_pad_i370, fabric_direct0_cfg_pad_i371, fabric_direct0_cfg_pad_i372, fabric_direct0_cfg_pad_i373, fabric_direct0_cfg_pad_i374, fabric_direct0_cfg_pad_i375, fabric_direct0_cfg_pad_i376, fabric_direct0_cfg_pad_i377, fabric_direct0_cfg_pad_i378, fabric_direct0_cfg_pad_i379
+, fabric_direct0_cfg_pad_i380, fabric_direct0_cfg_pad_i381, fabric_direct0_cfg_pad_i382, fabric_direct0_cfg_pad_i383, fabric_direct0_cfg_pad_i384, fabric_direct0_cfg_pad_i385, fabric_direct0_cfg_pad_i386, fabric_direct0_cfg_pad_i387, fabric_direct0_cfg_pad_i388, fabric_direct0_cfg_pad_i389, fabric_direct0_cfg_pad_i390, fabric_direct0_cfg_pad_i391, fabric_direct0_cfg_pad_i392, fabric_direct0_cfg_pad_i393, fabric_direct0_cfg_pad_i394, fabric_direct0_cfg_pad_i395, fabric_direct0_cfg_pad_i396, fabric_direct0_cfg_pad_i397, fabric_direct0_cfg_pad_i398, fabric_direct0_cfg_pad_i399, fabric_direct0_cfg_pad_i400
+, fabric_direct0_cfg_pad_i401, fabric_direct0_cfg_pad_i402, fabric_direct0_cfg_pad_i403, fabric_direct0_cfg_pad_i404, fabric_direct0_cfg_pad_i405, fabric_direct0_cfg_pad_i406, fabric_direct0_cfg_pad_i407, fabric_direct0_cfg_pad_i408, fabric_direct0_cfg_pad_i409, fabric_direct0_cfg_pad_i410, fabric_direct0_cfg_pad_i411, fabric_direct0_cfg_pad_i412, fabric_direct0_cfg_pad_i413, fabric_direct0_cfg_pad_i414, fabric_direct0_cfg_pad_i415, fabric_direct0_cfg_pad_i416, fabric_direct0_cfg_pad_i417, fabric_direct0_cfg_pad_i418, fabric_direct0_cfg_pad_i419, fabric_direct0_cfg_pad_i420, fabric_direct0_cfg_pad_i421
+, fabric_direct0_cfg_pad_i422, fabric_direct0_cfg_pad_i423, fabric_direct0_cfg_pad_i424, fabric_direct0_cfg_pad_i425, fabric_direct0_cfg_pad_i426, fabric_direct0_cfg_pad_i427, fabric_direct0_cfg_pad_i428, fabric_direct0_cfg_pad_i429, fabric_direct0_cfg_pad_i430, fabric_direct0_cfg_pad_i431, fabric_direct0_cfg_pad_i432, fabric_direct0_cfg_pad_i433, fabric_direct0_cfg_pad_i434, fabric_direct0_cfg_pad_i435, fabric_direct0_cfg_pad_i436, fabric_direct0_cfg_pad_i437, fabric_direct0_cfg_pad_i438, fabric_direct0_cfg_pad_i439, fabric_direct0_cfg_pad_i440, fabric_direct0_cfg_pad_i441, fabric_direct0_cfg_pad_i442
+, fabric_direct0_cfg_pad_i443, fabric_direct0_cfg_pad_i444, fabric_direct0_cfg_pad_i445, fabric_direct0_cfg_pad_i446, fabric_direct0_cfg_pad_i447, fabric_direct0_cfg_pad_i448, fabric_direct0_cfg_pad_i449, fabric_direct0_cfg_pad_i450, fabric_direct0_cfg_pad_i451, fabric_direct0_cfg_pad_i452, fabric_direct0_cfg_pad_i453, fabric_direct0_cfg_pad_i454, fabric_direct0_cfg_pad_i455, fabric_direct0_cfg_pad_i456, fabric_direct0_cfg_pad_i457, fabric_direct0_cfg_pad_i458, fabric_direct0_cfg_pad_i459, fabric_direct0_cfg_pad_i460, fabric_direct0_cfg_pad_i461, fabric_direct0_cfg_pad_i462, fabric_direct0_cfg_pad_i463
+, fabric_direct0_cfg_pad_i464, fabric_direct0_cfg_pad_i465, fabric_direct0_cfg_pad_i466, fabric_direct0_cfg_pad_i467, fabric_direct0_cfg_pad_i468, fabric_direct0_cfg_pad_i469, fabric_direct0_cfg_pad_i470, fabric_direct0_cfg_pad_i471, fabric_direct0_cfg_pad_i472, fabric_direct0_cfg_pad_i473, fabric_direct0_cfg_pad_i474, fabric_direct0_cfg_pad_i475, fabric_direct0_cfg_pad_i476, fabric_direct0_cfg_pad_i477, fabric_direct0_cfg_pad_i478, fabric_direct0_cfg_pad_i479, fabric_direct0_cfg_pad_i480, fabric_direct0_cfg_pad_i481, fabric_direct0_cfg_pad_i482, fabric_direct0_cfg_pad_i483, fabric_direct0_cfg_pad_i484
+, fabric_direct0_cfg_pad_i485, fabric_direct0_cfg_pad_i486, fabric_direct0_cfg_pad_i487, fabric_direct0_cfg_pad_i488, fabric_direct0_cfg_pad_i489, fabric_direct0_cfg_pad_i490, fabric_direct0_cfg_pad_i491, fabric_direct0_cfg_pad_i492, fabric_direct0_cfg_pad_i493, fabric_direct0_cfg_pad_i494, fabric_direct0_cfg_pad_i495, fabric_direct0_cfg_pad_i496, fabric_direct0_cfg_pad_i497, fabric_direct0_cfg_pad_i498, fabric_direct0_cfg_pad_i499, fabric_direct0_cfg_pad_i500, fabric_direct0_cfg_pad_i501, fabric_direct0_cfg_pad_i502, fabric_direct0_cfg_pad_i503, fabric_direct0_cfg_pad_i504, fabric_direct0_cfg_pad_i505
+, fabric_direct0_cfg_pad_i506, fabric_direct0_cfg_pad_i507, fabric_direct0_cfg_pad_i508, fabric_direct0_cfg_pad_i509, fabric_direct0_cfg_pad_i510, fabric_direct0_cfg_pad_i511, fabric_direct0_cfg_pad_i512, fabric_direct0_cfg_pad_i513, fabric_direct0_cfg_pad_i514, fabric_direct0_cfg_pad_i515, fabric_direct0_cfg_pad_i516, fabric_direct0_cfg_pad_i517, fabric_direct0_cfg_pad_i518, fabric_direct0_cfg_pad_i519, fabric_direct0_cfg_pad_i520, fabric_direct0_cfg_pad_i521, fabric_direct0_cfg_pad_i522, fabric_direct0_cfg_pad_i523, fabric_direct0_cfg_pad_i524, fabric_direct0_cfg_pad_i525, fabric_direct0_cfg_pad_i526
+, fabric_direct0_cfg_pad_i527, fabric_direct0_cfg_pad_i528, fabric_direct0_cfg_pad_i529, fabric_direct0_cfg_pad_i530, fabric_direct0_cfg_pad_i531, fabric_direct0_cfg_pad_i532, fabric_direct0_cfg_pad_i533, fabric_direct0_cfg_pad_i534, fabric_direct0_cfg_pad_i535, fabric_direct0_cfg_pad_i536, fabric_direct0_cfg_pad_i537, fabric_direct0_cfg_pad_i538, fabric_direct0_cfg_pad_i539, fabric_direct0_cfg_pad_i540, fabric_direct0_cfg_pad_i541, fabric_direct0_cfg_pad_i542, fabric_direct0_cfg_pad_i543, fabric_direct0_cfg_pad_i544, fabric_direct0_cfg_pad_i545, fabric_direct0_cfg_pad_i546, fabric_direct0_cfg_pad_i547
+, fabric_direct0_cfg_pad_i548, fabric_direct0_cfg_pad_i549, fabric_direct0_cfg_pad_i550, fabric_direct0_cfg_pad_i551, fabric_direct0_cfg_pad_i552, fabric_direct0_cfg_pad_i553, fabric_direct0_cfg_pad_i554, fabric_direct0_cfg_pad_i555, fabric_direct0_cfg_pad_i556, fabric_direct0_cfg_pad_i557, fabric_direct0_cfg_pad_i558, fabric_direct0_cfg_pad_i559, fabric_direct0_cfg_pad_i560, fabric_direct0_cfg_pad_i561, fabric_direct0_cfg_pad_i562, fabric_direct0_cfg_pad_i563, fabric_direct0_cfg_pad_i564, fabric_direct0_cfg_pad_i565, fabric_direct0_cfg_pad_i566, fabric_direct0_cfg_pad_i567, fabric_direct0_cfg_pad_i568
+, fabric_direct0_cfg_pad_i569, fabric_direct0_cfg_pad_i570, fabric_direct0_cfg_pad_i571, fabric_direct0_cfg_pad_i572, fabric_direct0_cfg_pad_i573, fabric_direct0_cfg_pad_i574, fabric_direct0_cfg_pad_i575, fabric_direct0_cfg_pad_i576, fabric_direct0_cfg_pad_i577, fabric_direct0_cfg_pad_i578, fabric_direct0_cfg_pad_i579, fabric_direct0_cfg_pad_i580, fabric_direct0_cfg_pad_i581, fabric_direct0_cfg_pad_i582, fabric_direct0_cfg_pad_i583, fabric_direct0_cfg_pad_i584, fabric_direct0_cfg_pad_i585, fabric_direct0_cfg_pad_i586, fabric_direct0_cfg_pad_i587, fabric_direct0_cfg_pad_i588, fabric_direct0_cfg_pad_i589
+, fabric_direct0_cfg_pad_i590, fabric_direct0_cfg_pad_i591, fabric_direct0_cfg_pad_i592, fabric_direct0_cfg_pad_i593, fabric_direct0_cfg_pad_i594, fabric_direct0_cfg_pad_i595, fabric_direct0_cfg_pad_i596, fabric_direct0_cfg_pad_i597, fabric_direct0_cfg_pad_i598, fabric_direct0_cfg_pad_i599, fabric_direct0_cfg_pad_i600, fabric_direct0_cfg_pad_i601, fabric_direct0_cfg_pad_i602, fabric_direct0_cfg_pad_i603, fabric_direct0_cfg_pad_i604, fabric_direct0_cfg_pad_i605, fabric_direct0_cfg_pad_i606, fabric_direct0_cfg_pad_i607, fabric_direct0_cfg_pad_i608, fabric_direct0_cfg_pad_i609, fabric_direct0_cfg_pad_i610
+, fabric_direct0_cfg_pad_i611, fabric_direct0_cfg_pad_i612, fabric_direct0_cfg_pad_i613, fabric_direct0_cfg_pad_i614, fabric_direct0_cfg_pad_i615, fabric_direct0_cfg_pad_i616, fabric_direct0_cfg_pad_i617, fabric_direct0_cfg_pad_i618, fabric_direct0_cfg_pad_i619, fabric_direct0_cfg_pad_i620, fabric_direct0_cfg_pad_i621, fabric_direct0_cfg_pad_i622, fabric_direct0_cfg_pad_i623, fabric_direct0_cfg_pad_i624, fabric_direct0_cfg_pad_i625, fabric_direct0_cfg_pad_i626, fabric_direct0_cfg_pad_i627, fabric_direct0_cfg_pad_i628, fabric_direct0_cfg_pad_i629, fabric_direct0_cfg_pad_i630, fabric_direct0_cfg_pad_i631
+, fabric_direct0_cfg_pad_i632, fabric_direct0_cfg_pad_i633, fabric_direct0_cfg_pad_i634, fabric_direct0_cfg_pad_i635, fabric_direct0_cfg_pad_i636, fabric_direct0_cfg_pad_i637, fabric_direct0_cfg_pad_i638, fabric_direct0_cfg_pad_i639, fabric_direct0_cfg_pad_i640, fabric_direct0_cfg_pad_i641, fabric_direct0_cfg_pad_i642, fabric_direct0_cfg_pad_i643, fabric_direct0_cfg_pad_i644, fabric_direct0_cfg_pad_i645, fabric_direct0_cfg_pad_i646, fabric_direct0_cfg_pad_i647, fabric_direct0_cfg_pad_i648, fabric_direct0_cfg_pad_i649, fabric_direct0_cfg_pad_i650, fabric_direct0_cfg_pad_i651, fabric_direct0_cfg_pad_i652
+, fabric_direct0_cfg_pad_i653, fabric_direct0_cfg_pad_i654, fabric_direct0_cfg_pad_i655, fabric_direct0_cfg_pad_i656, fabric_direct0_cfg_pad_i657, fabric_direct0_cfg_pad_i658, fabric_direct0_cfg_pad_i659, fabric_direct0_cfg_pad_i660, fabric_direct0_cfg_pad_i661, fabric_direct0_cfg_pad_i662, fabric_direct0_cfg_pad_i663, fabric_direct0_cfg_pad_i664, fabric_direct0_cfg_pad_i665, fabric_direct0_cfg_pad_i666, fabric_direct0_cfg_pad_i667, fabric_direct0_cfg_pad_i668, fabric_direct0_cfg_pad_i669, fabric_direct0_cfg_pad_i670, fabric_direct0_cfg_pad_i671, fabric_direct0_cfg_pad_i672, fabric_direct0_cfg_pad_i673
+, fabric_direct0_cfg_pad_i674, fabric_direct0_cfg_pad_i675, fabric_direct0_cfg_pad_i676, fabric_direct0_cfg_pad_i677, fabric_direct0_cfg_pad_i678, fabric_direct0_cfg_pad_i679, fabric_direct0_cfg_pad_i680, fabric_direct0_cfg_pad_i681, fabric_direct0_cfg_pad_i682, fabric_direct0_cfg_pad_i683, fabric_direct0_cfg_pad_i684, fabric_direct0_cfg_pad_i685, fabric_direct0_cfg_pad_i686, fabric_direct0_cfg_pad_i687, fabric_direct0_cfg_pad_i688, fabric_direct0_cfg_pad_i689, fabric_direct0_cfg_pad_i690, fabric_direct0_cfg_pad_i691, fabric_direct0_cfg_pad_i692, fabric_direct0_cfg_pad_i693, fabric_direct0_cfg_pad_i694
+, fabric_direct0_cfg_pad_i695, fabric_direct0_cfg_pad_i696, fabric_direct0_cfg_pad_i697, fabric_direct0_cfg_pad_i698, fabric_direct0_cfg_pad_i699, fabric_direct0_cfg_pad_i700, fabric_direct0_cfg_pad_i701, fabric_direct0_cfg_pad_i702, fabric_direct0_cfg_pad_i703, fabric_direct0_cfg_pad_i704, fabric_direct0_cfg_pad_i705, fabric_direct0_cfg_pad_i706, fabric_direct0_cfg_pad_i707, fabric_direct0_cfg_pad_i708, fabric_direct0_cfg_pad_i709, fabric_direct0_cfg_pad_i710, fabric_direct0_cfg_pad_i711, fabric_direct0_cfg_pad_i712, fabric_direct0_cfg_pad_i713, fabric_direct0_cfg_pad_i714, fabric_direct0_cfg_pad_i715
+, fabric_direct0_cfg_pad_i716, fabric_direct0_cfg_pad_i717, fabric_direct0_cfg_pad_i718, fabric_direct0_cfg_pad_i719, fabric_direct0_cfg_pad_i720, fabric_direct0_scan_en_i, fabric_direct0_loopback_en_i, fabric_direct0_loopback_mux_i, fabric_direct2_clock_fabric_i1, fabric_direct2_clock_fabric_i2, fabric_direct2_clock_fabric_i3, fabric_direct2_clock_fabric_i4, fabric_direct2_oe_i1, fabric_direct2_oe_i2, fabric_direct2_oe_i3, fabric_direct2_oe_i4, fabric_direct2_oe_i5, fabric_direct2_oe_i6, fabric_direct2_oe_i7, fabric_direct2_oe_i8, fabric_direct2_oe_i9
+, fabric_direct2_oe_i10, fabric_direct2_oe_i11, fabric_direct2_oe_i12, fabric_direct2_oe_i13, fabric_direct2_oe_i14, fabric_direct2_oe_i15, fabric_direct2_oe_i16, fabric_direct2_oe_i17, fabric_direct2_oe_i18, fabric_direct2_oe_i19, fabric_direct2_oe_i20, fabric_direct2_oe_i21, fabric_direct2_oe_i22, fabric_direct2_oe_i23, fabric_direct2_oe_i24, fabric_direct2_oe_ena_i1, fabric_direct2_oe_ena_i2, fabric_direct2_oe_ena_i3, fabric_direct2_oe_ena_i4, fabric_direct2_oe_ena_i5, fabric_direct2_oe_ena_i6
+, fabric_direct2_oe_ena_i7, fabric_direct2_oe_ena_i8, fabric_direct2_oe_ena_i9, fabric_direct2_oe_ena_i10, fabric_direct2_oe_ena_i11, fabric_direct2_oe_ena_i12, fabric_direct2_oe_ena_i13, fabric_direct2_oe_ena_i14, fabric_direct2_oe_ena_i15, fabric_direct2_oe_ena_i16, fabric_direct2_oe_ena_i17, fabric_direct2_oe_ena_i18, fabric_direct2_oe_ena_i19, fabric_direct2_oe_ena_i20, fabric_direct2_oe_ena_i21, fabric_direct2_oe_ena_i22, fabric_direct2_oe_ena_i23, fabric_direct2_oe_ena_i24, fabric_direct2_oe_rs_i1, fabric_direct2_oe_rs_i2, fabric_direct2_oe_rs_i3
+, fabric_direct2_oe_rs_i4, fabric_direct2_oe_rs_i5, fabric_direct2_oe_rs_i6, fabric_direct2_oe_rs_i7, fabric_direct2_oe_rs_i8, fabric_direct2_oe_rs_i9, fabric_direct2_oe_rs_i10, fabric_direct2_oe_rs_i11, fabric_direct2_oe_rs_i12, fabric_direct2_oe_rs_i13, fabric_direct2_oe_rs_i14, fabric_direct2_oe_rs_i15, fabric_direct2_oe_rs_i16, fabric_direct2_oe_rs_i17, fabric_direct2_oe_rs_i18, fabric_direct2_oe_rs_i19, fabric_direct2_oe_rs_i20, fabric_direct2_oe_rs_i21, fabric_direct2_oe_rs_i22, fabric_direct2_oe_rs_i23, fabric_direct2_oe_rs_i24
+, fabric_direct2_do_i1, fabric_direct2_do_i2, fabric_direct2_do_i3, fabric_direct2_do_i4, fabric_direct2_do_i5, fabric_direct2_do_i6, fabric_direct2_do_i7, fabric_direct2_do_i8, fabric_direct2_do_i9, fabric_direct2_do_i10, fabric_direct2_do_i11, fabric_direct2_do_i12, fabric_direct2_do_i13, fabric_direct2_do_i14, fabric_direct2_do_i15, fabric_direct2_do_i16, fabric_direct2_do_i17, fabric_direct2_do_i18, fabric_direct2_do_i19, fabric_direct2_do_i20, fabric_direct2_do_i21
+, fabric_direct2_do_i22, fabric_direct2_do_i23, fabric_direct2_do_i24, fabric_direct2_do_ena_i1, fabric_direct2_do_ena_i2, fabric_direct2_do_ena_i3, fabric_direct2_do_ena_i4, fabric_direct2_do_ena_i5, fabric_direct2_do_ena_i6, fabric_direct2_do_ena_i7, fabric_direct2_do_ena_i8, fabric_direct2_do_ena_i9, fabric_direct2_do_ena_i10, fabric_direct2_do_ena_i11, fabric_direct2_do_ena_i12, fabric_direct2_do_ena_i13, fabric_direct2_do_ena_i14, fabric_direct2_do_ena_i15, fabric_direct2_do_ena_i16, fabric_direct2_do_ena_i17, fabric_direct2_do_ena_i18
+, fabric_direct2_do_ena_i19, fabric_direct2_do_ena_i20, fabric_direct2_do_ena_i21, fabric_direct2_do_ena_i22, fabric_direct2_do_ena_i23, fabric_direct2_do_ena_i24, fabric_direct2_do_rs_i1, fabric_direct2_do_rs_i2, fabric_direct2_do_rs_i3, fabric_direct2_do_rs_i4, fabric_direct2_do_rs_i5, fabric_direct2_do_rs_i6, fabric_direct2_do_rs_i7, fabric_direct2_do_rs_i8, fabric_direct2_do_rs_i9, fabric_direct2_do_rs_i10, fabric_direct2_do_rs_i11, fabric_direct2_do_rs_i12, fabric_direct2_do_rs_i13, fabric_direct2_do_rs_i14, fabric_direct2_do_rs_i15
+, fabric_direct2_do_rs_i16, fabric_direct2_do_rs_i17, fabric_direct2_do_rs_i18, fabric_direct2_do_rs_i19, fabric_direct2_do_rs_i20, fabric_direct2_do_rs_i21, fabric_direct2_do_rs_i22, fabric_direct2_do_rs_i23, fabric_direct2_do_rs_i24, fabric_direct2_di_o1, fabric_direct2_di_o2, fabric_direct2_di_o3, fabric_direct2_di_o4, fabric_direct2_di_o5, fabric_direct2_di_o6, fabric_direct2_di_o7, fabric_direct2_di_o8, fabric_direct2_di_o9, fabric_direct2_di_o10, fabric_direct2_di_o11, fabric_direct2_di_o12
+, fabric_direct2_di_o13, fabric_direct2_di_o14, fabric_direct2_di_o15, fabric_direct2_di_o16, fabric_direct2_di_o17, fabric_direct2_di_o18, fabric_direct2_di_o19, fabric_direct2_di_o20, fabric_direct2_di_o21, fabric_direct2_di_o22, fabric_direct2_di_o23, fabric_direct2_di_o24, fabric_direct2_di_ena_i1, fabric_direct2_di_ena_i2, fabric_direct2_di_ena_i3, fabric_direct2_di_ena_i4, fabric_direct2_di_ena_i5, fabric_direct2_di_ena_i6, fabric_direct2_di_ena_i7, fabric_direct2_di_ena_i8, fabric_direct2_di_ena_i9
+, fabric_direct2_di_ena_i10, fabric_direct2_di_ena_i11, fabric_direct2_di_ena_i12, fabric_direct2_di_ena_i13, fabric_direct2_di_ena_i14, fabric_direct2_di_ena_i15, fabric_direct2_di_ena_i16, fabric_direct2_di_ena_i17, fabric_direct2_di_ena_i18, fabric_direct2_di_ena_i19, fabric_direct2_di_ena_i20, fabric_direct2_di_ena_i21, fabric_direct2_di_ena_i22, fabric_direct2_di_ena_i23, fabric_direct2_di_ena_i24, fabric_direct2_di_rs_i1, fabric_direct2_di_rs_i2, fabric_direct2_di_rs_i3, fabric_direct2_di_rs_i4, fabric_direct2_di_rs_i5, fabric_direct2_di_rs_i6
+, fabric_direct2_di_rs_i7, fabric_direct2_di_rs_i8, fabric_direct2_di_rs_i9, fabric_direct2_di_rs_i10, fabric_direct2_di_rs_i11, fabric_direct2_di_rs_i12, fabric_direct2_di_rs_i13, fabric_direct2_di_rs_i14, fabric_direct2_di_rs_i15, fabric_direct2_di_rs_i16, fabric_direct2_di_rs_i17, fabric_direct2_di_rs_i18, fabric_direct2_di_rs_i19, fabric_direct2_di_rs_i20, fabric_direct2_di_rs_i21, fabric_direct2_di_rs_i22, fabric_direct2_di_rs_i23, fabric_direct2_di_rs_i24, fabric_direct2_cfg_bank_i1, fabric_direct2_cfg_bank_i2, fabric_direct2_cfg_bank_i3
+, fabric_direct2_cfg_bank_i4, fabric_direct2_cfg_pad_i1, fabric_direct2_cfg_pad_i2, fabric_direct2_cfg_pad_i3, fabric_direct2_cfg_pad_i4, fabric_direct2_cfg_pad_i5, fabric_direct2_cfg_pad_i6, fabric_direct2_cfg_pad_i7, fabric_direct2_cfg_pad_i8, fabric_direct2_cfg_pad_i9, fabric_direct2_cfg_pad_i10, fabric_direct2_cfg_pad_i11, fabric_direct2_cfg_pad_i12, fabric_direct2_cfg_pad_i13, fabric_direct2_cfg_pad_i14, fabric_direct2_cfg_pad_i15, fabric_direct2_cfg_pad_i16, fabric_direct2_cfg_pad_i17, fabric_direct2_cfg_pad_i18, fabric_direct2_cfg_pad_i19, fabric_direct2_cfg_pad_i20
+, fabric_direct2_cfg_pad_i21, fabric_direct2_cfg_pad_i22, fabric_direct2_cfg_pad_i23, fabric_direct2_cfg_pad_i24, fabric_direct2_cfg_pad_i25, fabric_direct2_cfg_pad_i26, fabric_direct2_cfg_pad_i27, fabric_direct2_cfg_pad_i28, fabric_direct2_cfg_pad_i29, fabric_direct2_cfg_pad_i30, fabric_direct2_cfg_pad_i31, fabric_direct2_cfg_pad_i32, fabric_direct2_cfg_pad_i33, fabric_direct2_cfg_pad_i34, fabric_direct2_cfg_pad_i35, fabric_direct2_cfg_pad_i36, fabric_direct2_cfg_pad_i37, fabric_direct2_cfg_pad_i38, fabric_direct2_cfg_pad_i39, fabric_direct2_cfg_pad_i40, fabric_direct2_cfg_pad_i41
+, fabric_direct2_cfg_pad_i42, fabric_direct2_cfg_pad_i43, fabric_direct2_cfg_pad_i44, fabric_direct2_cfg_pad_i45, fabric_direct2_cfg_pad_i46, fabric_direct2_cfg_pad_i47, fabric_direct2_cfg_pad_i48, fabric_direct2_cfg_pad_i49, fabric_direct2_cfg_pad_i50, fabric_direct2_cfg_pad_i51, fabric_direct2_cfg_pad_i52, fabric_direct2_cfg_pad_i53, fabric_direct2_cfg_pad_i54, fabric_direct2_cfg_pad_i55, fabric_direct2_cfg_pad_i56, fabric_direct2_cfg_pad_i57, fabric_direct2_cfg_pad_i58, fabric_direct2_cfg_pad_i59, fabric_direct2_cfg_pad_i60, fabric_direct2_cfg_pad_i61, fabric_direct2_cfg_pad_i62
+, fabric_direct2_cfg_pad_i63, fabric_direct2_cfg_pad_i64, fabric_direct2_cfg_pad_i65, fabric_direct2_cfg_pad_i66, fabric_direct2_cfg_pad_i67, fabric_direct2_cfg_pad_i68, fabric_direct2_cfg_pad_i69, fabric_direct2_cfg_pad_i70, fabric_direct2_cfg_pad_i71, fabric_direct2_cfg_pad_i72, fabric_direct2_cfg_pad_i73, fabric_direct2_cfg_pad_i74, fabric_direct2_cfg_pad_i75, fabric_direct2_cfg_pad_i76, fabric_direct2_cfg_pad_i77, fabric_direct2_cfg_pad_i78, fabric_direct2_cfg_pad_i79, fabric_direct2_cfg_pad_i80, fabric_direct2_cfg_pad_i81, fabric_direct2_cfg_pad_i82, fabric_direct2_cfg_pad_i83
+, fabric_direct2_cfg_pad_i84, fabric_direct2_cfg_pad_i85, fabric_direct2_cfg_pad_i86, fabric_direct2_cfg_pad_i87, fabric_direct2_cfg_pad_i88, fabric_direct2_cfg_pad_i89, fabric_direct2_cfg_pad_i90, fabric_direct2_cfg_pad_i91, fabric_direct2_cfg_pad_i92, fabric_direct2_cfg_pad_i93, fabric_direct2_cfg_pad_i94, fabric_direct2_cfg_pad_i95, fabric_direct2_cfg_pad_i96, fabric_direct2_cfg_pad_i97, fabric_direct2_cfg_pad_i98, fabric_direct2_cfg_pad_i99, fabric_direct2_cfg_pad_i100, fabric_direct2_cfg_pad_i101, fabric_direct2_cfg_pad_i102, fabric_direct2_cfg_pad_i103, fabric_direct2_cfg_pad_i104
+, fabric_direct2_cfg_pad_i105, fabric_direct2_cfg_pad_i106, fabric_direct2_cfg_pad_i107, fabric_direct2_cfg_pad_i108, fabric_direct2_cfg_pad_i109, fabric_direct2_cfg_pad_i110, fabric_direct2_cfg_pad_i111, fabric_direct2_cfg_pad_i112, fabric_direct2_cfg_pad_i113, fabric_direct2_cfg_pad_i114, fabric_direct2_cfg_pad_i115, fabric_direct2_cfg_pad_i116, fabric_direct2_cfg_pad_i117, fabric_direct2_cfg_pad_i118, fabric_direct2_cfg_pad_i119, fabric_direct2_cfg_pad_i120, fabric_direct2_cfg_pad_i121, fabric_direct2_cfg_pad_i122, fabric_direct2_cfg_pad_i123, fabric_direct2_cfg_pad_i124, fabric_direct2_cfg_pad_i125
+, fabric_direct2_cfg_pad_i126, fabric_direct2_cfg_pad_i127, fabric_direct2_cfg_pad_i128, fabric_direct2_cfg_pad_i129, fabric_direct2_cfg_pad_i130, fabric_direct2_cfg_pad_i131, fabric_direct2_cfg_pad_i132, fabric_direct2_cfg_pad_i133, fabric_direct2_cfg_pad_i134, fabric_direct2_cfg_pad_i135, fabric_direct2_cfg_pad_i136, fabric_direct2_cfg_pad_i137, fabric_direct2_cfg_pad_i138, fabric_direct2_cfg_pad_i139, fabric_direct2_cfg_pad_i140, fabric_direct2_cfg_pad_i141, fabric_direct2_cfg_pad_i142, fabric_direct2_cfg_pad_i143, fabric_direct2_cfg_pad_i144, fabric_direct2_cfg_pad_i145, fabric_direct2_cfg_pad_i146
+, fabric_direct2_cfg_pad_i147, fabric_direct2_cfg_pad_i148, fabric_direct2_cfg_pad_i149, fabric_direct2_cfg_pad_i150, fabric_direct2_cfg_pad_i151, fabric_direct2_cfg_pad_i152, fabric_direct2_cfg_pad_i153, fabric_direct2_cfg_pad_i154, fabric_direct2_cfg_pad_i155, fabric_direct2_cfg_pad_i156, fabric_direct2_cfg_pad_i157, fabric_direct2_cfg_pad_i158, fabric_direct2_cfg_pad_i159, fabric_direct2_cfg_pad_i160, fabric_direct2_cfg_pad_i161, fabric_direct2_cfg_pad_i162, fabric_direct2_cfg_pad_i163, fabric_direct2_cfg_pad_i164, fabric_direct2_cfg_pad_i165, fabric_direct2_cfg_pad_i166, fabric_direct2_cfg_pad_i167
+, fabric_direct2_cfg_pad_i168, fabric_direct2_cfg_pad_i169, fabric_direct2_cfg_pad_i170, fabric_direct2_cfg_pad_i171, fabric_direct2_cfg_pad_i172, fabric_direct2_cfg_pad_i173, fabric_direct2_cfg_pad_i174, fabric_direct2_cfg_pad_i175, fabric_direct2_cfg_pad_i176, fabric_direct2_cfg_pad_i177, fabric_direct2_cfg_pad_i178, fabric_direct2_cfg_pad_i179, fabric_direct2_cfg_pad_i180, fabric_direct2_cfg_pad_i181, fabric_direct2_cfg_pad_i182, fabric_direct2_cfg_pad_i183, fabric_direct2_cfg_pad_i184, fabric_direct2_cfg_pad_i185, fabric_direct2_cfg_pad_i186, fabric_direct2_cfg_pad_i187, fabric_direct2_cfg_pad_i188
+, fabric_direct2_cfg_pad_i189, fabric_direct2_cfg_pad_i190, fabric_direct2_cfg_pad_i191, fabric_direct2_cfg_pad_i192, fabric_direct2_cfg_pad_i193, fabric_direct2_cfg_pad_i194, fabric_direct2_cfg_pad_i195, fabric_direct2_cfg_pad_i196, fabric_direct2_cfg_pad_i197, fabric_direct2_cfg_pad_i198, fabric_direct2_cfg_pad_i199, fabric_direct2_cfg_pad_i200, fabric_direct2_cfg_pad_i201, fabric_direct2_cfg_pad_i202, fabric_direct2_cfg_pad_i203, fabric_direct2_cfg_pad_i204, fabric_direct2_cfg_pad_i205, fabric_direct2_cfg_pad_i206, fabric_direct2_cfg_pad_i207, fabric_direct2_cfg_pad_i208, fabric_direct2_cfg_pad_i209
+, fabric_direct2_cfg_pad_i210, fabric_direct2_cfg_pad_i211, fabric_direct2_cfg_pad_i212, fabric_direct2_cfg_pad_i213, fabric_direct2_cfg_pad_i214, fabric_direct2_cfg_pad_i215, fabric_direct2_cfg_pad_i216, fabric_direct2_cfg_pad_i217, fabric_direct2_cfg_pad_i218, fabric_direct2_cfg_pad_i219, fabric_direct2_cfg_pad_i220, fabric_direct2_cfg_pad_i221, fabric_direct2_cfg_pad_i222, fabric_direct2_cfg_pad_i223, fabric_direct2_cfg_pad_i224, fabric_direct2_cfg_pad_i225, fabric_direct2_cfg_pad_i226, fabric_direct2_cfg_pad_i227, fabric_direct2_cfg_pad_i228, fabric_direct2_cfg_pad_i229, fabric_direct2_cfg_pad_i230
+, fabric_direct2_cfg_pad_i231, fabric_direct2_cfg_pad_i232, fabric_direct2_cfg_pad_i233, fabric_direct2_cfg_pad_i234, fabric_direct2_cfg_pad_i235, fabric_direct2_cfg_pad_i236, fabric_direct2_cfg_pad_i237, fabric_direct2_cfg_pad_i238, fabric_direct2_cfg_pad_i239, fabric_direct2_cfg_pad_i240, fabric_direct2_cfg_pad_i241, fabric_direct2_cfg_pad_i242, fabric_direct2_cfg_pad_i243, fabric_direct2_cfg_pad_i244, fabric_direct2_cfg_pad_i245, fabric_direct2_cfg_pad_i246, fabric_direct2_cfg_pad_i247, fabric_direct2_cfg_pad_i248, fabric_direct2_cfg_pad_i249, fabric_direct2_cfg_pad_i250, fabric_direct2_cfg_pad_i251
+, fabric_direct2_cfg_pad_i252, fabric_direct2_cfg_pad_i253, fabric_direct2_cfg_pad_i254, fabric_direct2_cfg_pad_i255, fabric_direct2_cfg_pad_i256, fabric_direct2_cfg_pad_i257, fabric_direct2_cfg_pad_i258, fabric_direct2_cfg_pad_i259, fabric_direct2_cfg_pad_i260, fabric_direct2_cfg_pad_i261, fabric_direct2_cfg_pad_i262, fabric_direct2_cfg_pad_i263, fabric_direct2_cfg_pad_i264, fabric_direct2_cfg_pad_i265, fabric_direct2_cfg_pad_i266, fabric_direct2_cfg_pad_i267, fabric_direct2_cfg_pad_i268, fabric_direct2_cfg_pad_i269, fabric_direct2_cfg_pad_i270, fabric_direct2_cfg_pad_i271, fabric_direct2_cfg_pad_i272
+, fabric_direct2_cfg_pad_i273, fabric_direct2_cfg_pad_i274, fabric_direct2_cfg_pad_i275, fabric_direct2_cfg_pad_i276, fabric_direct2_cfg_pad_i277, fabric_direct2_cfg_pad_i278, fabric_direct2_cfg_pad_i279, fabric_direct2_cfg_pad_i280, fabric_direct2_cfg_pad_i281, fabric_direct2_cfg_pad_i282, fabric_direct2_cfg_pad_i283, fabric_direct2_cfg_pad_i284, fabric_direct2_cfg_pad_i285, fabric_direct2_cfg_pad_i286, fabric_direct2_cfg_pad_i287, fabric_direct2_cfg_pad_i288, fabric_direct2_cfg_pad_i289, fabric_direct2_cfg_pad_i290, fabric_direct2_cfg_pad_i291, fabric_direct2_cfg_pad_i292, fabric_direct2_cfg_pad_i293
+, fabric_direct2_cfg_pad_i294, fabric_direct2_cfg_pad_i295, fabric_direct2_cfg_pad_i296, fabric_direct2_cfg_pad_i297, fabric_direct2_cfg_pad_i298, fabric_direct2_cfg_pad_i299, fabric_direct2_cfg_pad_i300, fabric_direct2_cfg_pad_i301, fabric_direct2_cfg_pad_i302, fabric_direct2_cfg_pad_i303, fabric_direct2_cfg_pad_i304, fabric_direct2_cfg_pad_i305, fabric_direct2_cfg_pad_i306, fabric_direct2_cfg_pad_i307, fabric_direct2_cfg_pad_i308, fabric_direct2_cfg_pad_i309, fabric_direct2_cfg_pad_i310, fabric_direct2_cfg_pad_i311, fabric_direct2_cfg_pad_i312, fabric_direct2_cfg_pad_i313, fabric_direct2_cfg_pad_i314
+, fabric_direct2_cfg_pad_i315, fabric_direct2_cfg_pad_i316, fabric_direct2_cfg_pad_i317, fabric_direct2_cfg_pad_i318, fabric_direct2_cfg_pad_i319, fabric_direct2_cfg_pad_i320, fabric_direct2_cfg_pad_i321, fabric_direct2_cfg_pad_i322, fabric_direct2_cfg_pad_i323, fabric_direct2_cfg_pad_i324, fabric_direct2_cfg_pad_i325, fabric_direct2_cfg_pad_i326, fabric_direct2_cfg_pad_i327, fabric_direct2_cfg_pad_i328, fabric_direct2_cfg_pad_i329, fabric_direct2_cfg_pad_i330, fabric_direct2_cfg_pad_i331, fabric_direct2_cfg_pad_i332, fabric_direct2_cfg_pad_i333, fabric_direct2_cfg_pad_i334, fabric_direct2_cfg_pad_i335
+, fabric_direct2_cfg_pad_i336, fabric_direct2_cfg_pad_i337, fabric_direct2_cfg_pad_i338, fabric_direct2_cfg_pad_i339, fabric_direct2_cfg_pad_i340, fabric_direct2_cfg_pad_i341, fabric_direct2_cfg_pad_i342, fabric_direct2_cfg_pad_i343, fabric_direct2_cfg_pad_i344, fabric_direct2_cfg_pad_i345, fabric_direct2_cfg_pad_i346, fabric_direct2_cfg_pad_i347, fabric_direct2_cfg_pad_i348, fabric_direct2_cfg_pad_i349, fabric_direct2_cfg_pad_i350, fabric_direct2_cfg_pad_i351, fabric_direct2_cfg_pad_i352, fabric_direct2_cfg_pad_i353, fabric_direct2_cfg_pad_i354, fabric_direct2_cfg_pad_i355, fabric_direct2_cfg_pad_i356
+, fabric_direct2_cfg_pad_i357, fabric_direct2_cfg_pad_i358, fabric_direct2_cfg_pad_i359, fabric_direct2_cfg_pad_i360, fabric_direct2_cfg_pad_i361, fabric_direct2_cfg_pad_i362, fabric_direct2_cfg_pad_i363, fabric_direct2_cfg_pad_i364, fabric_direct2_cfg_pad_i365, fabric_direct2_cfg_pad_i366, fabric_direct2_cfg_pad_i367, fabric_direct2_cfg_pad_i368, fabric_direct2_cfg_pad_i369, fabric_direct2_cfg_pad_i370, fabric_direct2_cfg_pad_i371, fabric_direct2_cfg_pad_i372, fabric_direct2_cfg_pad_i373, fabric_direct2_cfg_pad_i374, fabric_direct2_cfg_pad_i375, fabric_direct2_cfg_pad_i376, fabric_direct2_cfg_pad_i377
+, fabric_direct2_cfg_pad_i378, fabric_direct2_cfg_pad_i379, fabric_direct2_cfg_pad_i380, fabric_direct2_cfg_pad_i381, fabric_direct2_cfg_pad_i382, fabric_direct2_cfg_pad_i383, fabric_direct2_cfg_pad_i384, fabric_direct2_cfg_pad_i385, fabric_direct2_cfg_pad_i386, fabric_direct2_cfg_pad_i387, fabric_direct2_cfg_pad_i388, fabric_direct2_cfg_pad_i389, fabric_direct2_cfg_pad_i390, fabric_direct2_cfg_pad_i391, fabric_direct2_cfg_pad_i392, fabric_direct2_cfg_pad_i393, fabric_direct2_cfg_pad_i394, fabric_direct2_cfg_pad_i395, fabric_direct2_cfg_pad_i396, fabric_direct2_cfg_pad_i397, fabric_direct2_cfg_pad_i398
+, fabric_direct2_cfg_pad_i399, fabric_direct2_cfg_pad_i400, fabric_direct2_cfg_pad_i401, fabric_direct2_cfg_pad_i402, fabric_direct2_cfg_pad_i403, fabric_direct2_cfg_pad_i404, fabric_direct2_cfg_pad_i405, fabric_direct2_cfg_pad_i406, fabric_direct2_cfg_pad_i407, fabric_direct2_cfg_pad_i408, fabric_direct2_cfg_pad_i409, fabric_direct2_cfg_pad_i410, fabric_direct2_cfg_pad_i411, fabric_direct2_cfg_pad_i412, fabric_direct2_cfg_pad_i413, fabric_direct2_cfg_pad_i414, fabric_direct2_cfg_pad_i415, fabric_direct2_cfg_pad_i416, fabric_direct2_cfg_pad_i417, fabric_direct2_cfg_pad_i418, fabric_direct2_cfg_pad_i419
+, fabric_direct2_cfg_pad_i420, fabric_direct2_cfg_pad_i421, fabric_direct2_cfg_pad_i422, fabric_direct2_cfg_pad_i423, fabric_direct2_cfg_pad_i424, fabric_direct2_cfg_pad_i425, fabric_direct2_cfg_pad_i426, fabric_direct2_cfg_pad_i427, fabric_direct2_cfg_pad_i428, fabric_direct2_cfg_pad_i429, fabric_direct2_cfg_pad_i430, fabric_direct2_cfg_pad_i431, fabric_direct2_cfg_pad_i432, fabric_direct2_cfg_pad_i433, fabric_direct2_cfg_pad_i434, fabric_direct2_cfg_pad_i435, fabric_direct2_cfg_pad_i436, fabric_direct2_cfg_pad_i437, fabric_direct2_cfg_pad_i438, fabric_direct2_cfg_pad_i439, fabric_direct2_cfg_pad_i440
+, fabric_direct2_cfg_pad_i441, fabric_direct2_cfg_pad_i442, fabric_direct2_cfg_pad_i443, fabric_direct2_cfg_pad_i444, fabric_direct2_cfg_pad_i445, fabric_direct2_cfg_pad_i446, fabric_direct2_cfg_pad_i447, fabric_direct2_cfg_pad_i448, fabric_direct2_cfg_pad_i449, fabric_direct2_cfg_pad_i450, fabric_direct2_cfg_pad_i451, fabric_direct2_cfg_pad_i452, fabric_direct2_cfg_pad_i453, fabric_direct2_cfg_pad_i454, fabric_direct2_cfg_pad_i455, fabric_direct2_cfg_pad_i456, fabric_direct2_cfg_pad_i457, fabric_direct2_cfg_pad_i458, fabric_direct2_cfg_pad_i459, fabric_direct2_cfg_pad_i460, fabric_direct2_cfg_pad_i461
+, fabric_direct2_cfg_pad_i462, fabric_direct2_cfg_pad_i463, fabric_direct2_cfg_pad_i464, fabric_direct2_cfg_pad_i465, fabric_direct2_cfg_pad_i466, fabric_direct2_cfg_pad_i467, fabric_direct2_cfg_pad_i468, fabric_direct2_cfg_pad_i469, fabric_direct2_cfg_pad_i470, fabric_direct2_cfg_pad_i471, fabric_direct2_cfg_pad_i472, fabric_direct2_cfg_pad_i473, fabric_direct2_cfg_pad_i474, fabric_direct2_cfg_pad_i475, fabric_direct2_cfg_pad_i476, fabric_direct2_cfg_pad_i477, fabric_direct2_cfg_pad_i478, fabric_direct2_cfg_pad_i479, fabric_direct2_cfg_pad_i480, fabric_direct2_cfg_pad_i481, fabric_direct2_cfg_pad_i482
+, fabric_direct2_cfg_pad_i483, fabric_direct2_cfg_pad_i484, fabric_direct2_cfg_pad_i485, fabric_direct2_cfg_pad_i486, fabric_direct2_cfg_pad_i487, fabric_direct2_cfg_pad_i488, fabric_direct2_cfg_pad_i489, fabric_direct2_cfg_pad_i490, fabric_direct2_cfg_pad_i491, fabric_direct2_cfg_pad_i492, fabric_direct2_cfg_pad_i493, fabric_direct2_cfg_pad_i494, fabric_direct2_cfg_pad_i495, fabric_direct2_cfg_pad_i496, fabric_direct2_cfg_pad_i497, fabric_direct2_cfg_pad_i498, fabric_direct2_cfg_pad_i499, fabric_direct2_cfg_pad_i500, fabric_direct2_cfg_pad_i501, fabric_direct2_cfg_pad_i502, fabric_direct2_cfg_pad_i503
+, fabric_direct2_cfg_pad_i504, fabric_direct2_cfg_pad_i505, fabric_direct2_cfg_pad_i506, fabric_direct2_cfg_pad_i507, fabric_direct2_cfg_pad_i508, fabric_direct2_cfg_pad_i509, fabric_direct2_cfg_pad_i510, fabric_direct2_cfg_pad_i511, fabric_direct2_cfg_pad_i512, fabric_direct2_cfg_pad_i513, fabric_direct2_cfg_pad_i514, fabric_direct2_cfg_pad_i515, fabric_direct2_cfg_pad_i516, fabric_direct2_cfg_pad_i517, fabric_direct2_cfg_pad_i518, fabric_direct2_cfg_pad_i519, fabric_direct2_cfg_pad_i520, fabric_direct2_cfg_pad_i521, fabric_direct2_cfg_pad_i522, fabric_direct2_cfg_pad_i523, fabric_direct2_cfg_pad_i524
+, fabric_direct2_cfg_pad_i525, fabric_direct2_cfg_pad_i526, fabric_direct2_cfg_pad_i527, fabric_direct2_cfg_pad_i528, fabric_direct2_cfg_pad_i529, fabric_direct2_cfg_pad_i530, fabric_direct2_cfg_pad_i531, fabric_direct2_cfg_pad_i532, fabric_direct2_cfg_pad_i533, fabric_direct2_cfg_pad_i534, fabric_direct2_cfg_pad_i535, fabric_direct2_cfg_pad_i536, fabric_direct2_cfg_pad_i537, fabric_direct2_cfg_pad_i538, fabric_direct2_cfg_pad_i539, fabric_direct2_cfg_pad_i540, fabric_direct2_cfg_pad_i541, fabric_direct2_cfg_pad_i542, fabric_direct2_cfg_pad_i543, fabric_direct2_cfg_pad_i544, fabric_direct2_cfg_pad_i545
+, fabric_direct2_cfg_pad_i546, fabric_direct2_cfg_pad_i547, fabric_direct2_cfg_pad_i548, fabric_direct2_cfg_pad_i549, fabric_direct2_cfg_pad_i550, fabric_direct2_cfg_pad_i551, fabric_direct2_cfg_pad_i552, fabric_direct2_cfg_pad_i553, fabric_direct2_cfg_pad_i554, fabric_direct2_cfg_pad_i555, fabric_direct2_cfg_pad_i556, fabric_direct2_cfg_pad_i557, fabric_direct2_cfg_pad_i558, fabric_direct2_cfg_pad_i559, fabric_direct2_cfg_pad_i560, fabric_direct2_cfg_pad_i561, fabric_direct2_cfg_pad_i562, fabric_direct2_cfg_pad_i563, fabric_direct2_cfg_pad_i564, fabric_direct2_cfg_pad_i565, fabric_direct2_cfg_pad_i566
+, fabric_direct2_cfg_pad_i567, fabric_direct2_cfg_pad_i568, fabric_direct2_cfg_pad_i569, fabric_direct2_cfg_pad_i570, fabric_direct2_cfg_pad_i571, fabric_direct2_cfg_pad_i572, fabric_direct2_cfg_pad_i573, fabric_direct2_cfg_pad_i574, fabric_direct2_cfg_pad_i575, fabric_direct2_cfg_pad_i576, fabric_direct2_cfg_pad_i577, fabric_direct2_cfg_pad_i578, fabric_direct2_cfg_pad_i579, fabric_direct2_cfg_pad_i580, fabric_direct2_cfg_pad_i581, fabric_direct2_cfg_pad_i582, fabric_direct2_cfg_pad_i583, fabric_direct2_cfg_pad_i584, fabric_direct2_cfg_pad_i585, fabric_direct2_cfg_pad_i586, fabric_direct2_cfg_pad_i587
+, fabric_direct2_cfg_pad_i588, fabric_direct2_cfg_pad_i589, fabric_direct2_cfg_pad_i590, fabric_direct2_cfg_pad_i591, fabric_direct2_cfg_pad_i592, fabric_direct2_cfg_pad_i593, fabric_direct2_cfg_pad_i594, fabric_direct2_cfg_pad_i595, fabric_direct2_cfg_pad_i596, fabric_direct2_cfg_pad_i597, fabric_direct2_cfg_pad_i598, fabric_direct2_cfg_pad_i599, fabric_direct2_cfg_pad_i600, fabric_direct2_cfg_pad_i601, fabric_direct2_cfg_pad_i602, fabric_direct2_cfg_pad_i603, fabric_direct2_cfg_pad_i604, fabric_direct2_cfg_pad_i605, fabric_direct2_cfg_pad_i606, fabric_direct2_cfg_pad_i607, fabric_direct2_cfg_pad_i608
+, fabric_direct2_cfg_pad_i609, fabric_direct2_cfg_pad_i610, fabric_direct2_cfg_pad_i611, fabric_direct2_cfg_pad_i612, fabric_direct2_cfg_pad_i613, fabric_direct2_cfg_pad_i614, fabric_direct2_cfg_pad_i615, fabric_direct2_cfg_pad_i616, fabric_direct2_cfg_pad_i617, fabric_direct2_cfg_pad_i618, fabric_direct2_cfg_pad_i619, fabric_direct2_cfg_pad_i620, fabric_direct2_cfg_pad_i621, fabric_direct2_cfg_pad_i622, fabric_direct2_cfg_pad_i623, fabric_direct2_cfg_pad_i624, fabric_direct2_cfg_pad_i625, fabric_direct2_cfg_pad_i626, fabric_direct2_cfg_pad_i627, fabric_direct2_cfg_pad_i628, fabric_direct2_cfg_pad_i629
+, fabric_direct2_cfg_pad_i630, fabric_direct2_cfg_pad_i631, fabric_direct2_cfg_pad_i632, fabric_direct2_cfg_pad_i633, fabric_direct2_cfg_pad_i634, fabric_direct2_cfg_pad_i635, fabric_direct2_cfg_pad_i636, fabric_direct2_cfg_pad_i637, fabric_direct2_cfg_pad_i638, fabric_direct2_cfg_pad_i639, fabric_direct2_cfg_pad_i640, fabric_direct2_cfg_pad_i641, fabric_direct2_cfg_pad_i642, fabric_direct2_cfg_pad_i643, fabric_direct2_cfg_pad_i644, fabric_direct2_cfg_pad_i645, fabric_direct2_cfg_pad_i646, fabric_direct2_cfg_pad_i647, fabric_direct2_cfg_pad_i648, fabric_direct2_cfg_pad_i649, fabric_direct2_cfg_pad_i650
+, fabric_direct2_cfg_pad_i651, fabric_direct2_cfg_pad_i652, fabric_direct2_cfg_pad_i653, fabric_direct2_cfg_pad_i654, fabric_direct2_cfg_pad_i655, fabric_direct2_cfg_pad_i656, fabric_direct2_cfg_pad_i657, fabric_direct2_cfg_pad_i658, fabric_direct2_cfg_pad_i659, fabric_direct2_cfg_pad_i660, fabric_direct2_cfg_pad_i661, fabric_direct2_cfg_pad_i662, fabric_direct2_cfg_pad_i663, fabric_direct2_cfg_pad_i664, fabric_direct2_cfg_pad_i665, fabric_direct2_cfg_pad_i666, fabric_direct2_cfg_pad_i667, fabric_direct2_cfg_pad_i668, fabric_direct2_cfg_pad_i669, fabric_direct2_cfg_pad_i670, fabric_direct2_cfg_pad_i671
+, fabric_direct2_cfg_pad_i672, fabric_direct2_cfg_pad_i673, fabric_direct2_cfg_pad_i674, fabric_direct2_cfg_pad_i675, fabric_direct2_cfg_pad_i676, fabric_direct2_cfg_pad_i677, fabric_direct2_cfg_pad_i678, fabric_direct2_cfg_pad_i679, fabric_direct2_cfg_pad_i680, fabric_direct2_cfg_pad_i681, fabric_direct2_cfg_pad_i682, fabric_direct2_cfg_pad_i683, fabric_direct2_cfg_pad_i684, fabric_direct2_cfg_pad_i685, fabric_direct2_cfg_pad_i686, fabric_direct2_cfg_pad_i687, fabric_direct2_cfg_pad_i688, fabric_direct2_cfg_pad_i689, fabric_direct2_cfg_pad_i690, fabric_direct2_cfg_pad_i691, fabric_direct2_cfg_pad_i692
+, fabric_direct2_cfg_pad_i693, fabric_direct2_cfg_pad_i694, fabric_direct2_cfg_pad_i695, fabric_direct2_cfg_pad_i696, fabric_direct2_cfg_pad_i697, fabric_direct2_cfg_pad_i698, fabric_direct2_cfg_pad_i699, fabric_direct2_cfg_pad_i700, fabric_direct2_cfg_pad_i701, fabric_direct2_cfg_pad_i702, fabric_direct2_cfg_pad_i703, fabric_direct2_cfg_pad_i704, fabric_direct2_cfg_pad_i705, fabric_direct2_cfg_pad_i706, fabric_direct2_cfg_pad_i707, fabric_direct2_cfg_pad_i708, fabric_direct2_cfg_pad_i709, fabric_direct2_cfg_pad_i710, fabric_direct2_cfg_pad_i711, fabric_direct2_cfg_pad_i712, fabric_direct2_cfg_pad_i713
+, fabric_direct2_cfg_pad_i714, fabric_direct2_cfg_pad_i715, fabric_direct2_cfg_pad_i716, fabric_direct2_cfg_pad_i717, fabric_direct2_cfg_pad_i718, fabric_direct2_cfg_pad_i719, fabric_direct2_cfg_pad_i720, fabric_direct2_scan_en_i, fabric_direct2_loopback_en_i, fabric_direct2_loopback_mux_i, fabric_direct1_clock_fabric_i1, fabric_direct1_clock_fabric_i2, fabric_direct1_clock_fabric_i3, fabric_direct1_clock_fabric_i4, fabric_direct1_oe_i1, fabric_direct1_oe_i2, fabric_direct1_oe_i3, fabric_direct1_oe_i4, fabric_direct1_oe_i5, fabric_direct1_oe_i6, fabric_direct1_oe_i7
+, fabric_direct1_oe_i8, fabric_direct1_oe_i9, fabric_direct1_oe_i10, fabric_direct1_oe_i11, fabric_direct1_oe_i12, fabric_direct1_oe_i13, fabric_direct1_oe_i14, fabric_direct1_oe_i15, fabric_direct1_oe_i16, fabric_direct1_oe_ena_i1, fabric_direct1_oe_ena_i2, fabric_direct1_oe_ena_i3, fabric_direct1_oe_ena_i4, fabric_direct1_oe_ena_i5, fabric_direct1_oe_ena_i6, fabric_direct1_oe_ena_i7, fabric_direct1_oe_ena_i8, fabric_direct1_oe_ena_i9, fabric_direct1_oe_ena_i10, fabric_direct1_oe_ena_i11, fabric_direct1_oe_ena_i12
+, fabric_direct1_oe_ena_i13, fabric_direct1_oe_ena_i14, fabric_direct1_oe_ena_i15, fabric_direct1_oe_ena_i16, fabric_direct1_oe_rs_i1, fabric_direct1_oe_rs_i2, fabric_direct1_oe_rs_i3, fabric_direct1_oe_rs_i4, fabric_direct1_oe_rs_i5, fabric_direct1_oe_rs_i6, fabric_direct1_oe_rs_i7, fabric_direct1_oe_rs_i8, fabric_direct1_oe_rs_i9, fabric_direct1_oe_rs_i10, fabric_direct1_oe_rs_i11, fabric_direct1_oe_rs_i12, fabric_direct1_oe_rs_i13, fabric_direct1_oe_rs_i14, fabric_direct1_oe_rs_i15, fabric_direct1_oe_rs_i16, fabric_direct1_do_i1
+, fabric_direct1_do_i2, fabric_direct1_do_i3, fabric_direct1_do_i4, fabric_direct1_do_i5, fabric_direct1_do_i6, fabric_direct1_do_i7, fabric_direct1_do_i8, fabric_direct1_do_i9, fabric_direct1_do_i10, fabric_direct1_do_i11, fabric_direct1_do_i12, fabric_direct1_do_i13, fabric_direct1_do_i14, fabric_direct1_do_i15, fabric_direct1_do_i16, fabric_direct1_do_ena_i1, fabric_direct1_do_ena_i2, fabric_direct1_do_ena_i3, fabric_direct1_do_ena_i4, fabric_direct1_do_ena_i5, fabric_direct1_do_ena_i6
+, fabric_direct1_do_ena_i7, fabric_direct1_do_ena_i8, fabric_direct1_do_ena_i9, fabric_direct1_do_ena_i10, fabric_direct1_do_ena_i11, fabric_direct1_do_ena_i12, fabric_direct1_do_ena_i13, fabric_direct1_do_ena_i14, fabric_direct1_do_ena_i15, fabric_direct1_do_ena_i16, fabric_direct1_do_rs_i1, fabric_direct1_do_rs_i2, fabric_direct1_do_rs_i3, fabric_direct1_do_rs_i4, fabric_direct1_do_rs_i5, fabric_direct1_do_rs_i6, fabric_direct1_do_rs_i7, fabric_direct1_do_rs_i8, fabric_direct1_do_rs_i9, fabric_direct1_do_rs_i10, fabric_direct1_do_rs_i11
+, fabric_direct1_do_rs_i12, fabric_direct1_do_rs_i13, fabric_direct1_do_rs_i14, fabric_direct1_do_rs_i15, fabric_direct1_do_rs_i16, fabric_direct1_di_o1, fabric_direct1_di_o2, fabric_direct1_di_o3, fabric_direct1_di_o4, fabric_direct1_di_o5, fabric_direct1_di_o6, fabric_direct1_di_o7, fabric_direct1_di_o8, fabric_direct1_di_o9, fabric_direct1_di_o10, fabric_direct1_di_o11, fabric_direct1_di_o12, fabric_direct1_di_o13, fabric_direct1_di_o14, fabric_direct1_di_o15, fabric_direct1_di_o16
+, fabric_direct1_di_ena_i1, fabric_direct1_di_ena_i2, fabric_direct1_di_ena_i3, fabric_direct1_di_ena_i4, fabric_direct1_di_ena_i5, fabric_direct1_di_ena_i6, fabric_direct1_di_ena_i7, fabric_direct1_di_ena_i8, fabric_direct1_di_ena_i9, fabric_direct1_di_ena_i10, fabric_direct1_di_ena_i11, fabric_direct1_di_ena_i12, fabric_direct1_di_ena_i13, fabric_direct1_di_ena_i14, fabric_direct1_di_ena_i15, fabric_direct1_di_ena_i16, fabric_direct1_di_rs_i1, fabric_direct1_di_rs_i2, fabric_direct1_di_rs_i3, fabric_direct1_di_rs_i4, fabric_direct1_di_rs_i5
+, fabric_direct1_di_rs_i6, fabric_direct1_di_rs_i7, fabric_direct1_di_rs_i8, fabric_direct1_di_rs_i9, fabric_direct1_di_rs_i10, fabric_direct1_di_rs_i11, fabric_direct1_di_rs_i12, fabric_direct1_di_rs_i13, fabric_direct1_di_rs_i14, fabric_direct1_di_rs_i15, fabric_direct1_di_rs_i16, fabric_direct1_cfg_bank_i1, fabric_direct1_cfg_bank_i2, fabric_direct1_cfg_bank_i3, fabric_direct1_cfg_bank_i4, fabric_direct1_cfg_pad_i1, fabric_direct1_cfg_pad_i2, fabric_direct1_cfg_pad_i3, fabric_direct1_cfg_pad_i4, fabric_direct1_cfg_pad_i5, fabric_direct1_cfg_pad_i6
+, fabric_direct1_cfg_pad_i7, fabric_direct1_cfg_pad_i8, fabric_direct1_cfg_pad_i9, fabric_direct1_cfg_pad_i10, fabric_direct1_cfg_pad_i11, fabric_direct1_cfg_pad_i12, fabric_direct1_cfg_pad_i13, fabric_direct1_cfg_pad_i14, fabric_direct1_cfg_pad_i15, fabric_direct1_cfg_pad_i16, fabric_direct1_cfg_pad_i17, fabric_direct1_cfg_pad_i18, fabric_direct1_cfg_pad_i19, fabric_direct1_cfg_pad_i20, fabric_direct1_cfg_pad_i21, fabric_direct1_cfg_pad_i22, fabric_direct1_cfg_pad_i23, fabric_direct1_cfg_pad_i24, fabric_direct1_cfg_pad_i25, fabric_direct1_cfg_pad_i26, fabric_direct1_cfg_pad_i27
+, fabric_direct1_cfg_pad_i28, fabric_direct1_cfg_pad_i29, fabric_direct1_cfg_pad_i30, fabric_direct1_cfg_pad_i31, fabric_direct1_cfg_pad_i32, fabric_direct1_cfg_pad_i33, fabric_direct1_cfg_pad_i34, fabric_direct1_cfg_pad_i35, fabric_direct1_cfg_pad_i36, fabric_direct1_cfg_pad_i37, fabric_direct1_cfg_pad_i38, fabric_direct1_cfg_pad_i39, fabric_direct1_cfg_pad_i40, fabric_direct1_cfg_pad_i41, fabric_direct1_cfg_pad_i42, fabric_direct1_cfg_pad_i43, fabric_direct1_cfg_pad_i44, fabric_direct1_cfg_pad_i45, fabric_direct1_cfg_pad_i46, fabric_direct1_cfg_pad_i47, fabric_direct1_cfg_pad_i48
+, fabric_direct1_cfg_pad_i49, fabric_direct1_cfg_pad_i50, fabric_direct1_cfg_pad_i51, fabric_direct1_cfg_pad_i52, fabric_direct1_cfg_pad_i53, fabric_direct1_cfg_pad_i54, fabric_direct1_cfg_pad_i55, fabric_direct1_cfg_pad_i56, fabric_direct1_cfg_pad_i57, fabric_direct1_cfg_pad_i58, fabric_direct1_cfg_pad_i59, fabric_direct1_cfg_pad_i60, fabric_direct1_cfg_pad_i61, fabric_direct1_cfg_pad_i62, fabric_direct1_cfg_pad_i63, fabric_direct1_cfg_pad_i64, fabric_direct1_cfg_pad_i65, fabric_direct1_cfg_pad_i66, fabric_direct1_cfg_pad_i67, fabric_direct1_cfg_pad_i68, fabric_direct1_cfg_pad_i69
+, fabric_direct1_cfg_pad_i70, fabric_direct1_cfg_pad_i71, fabric_direct1_cfg_pad_i72, fabric_direct1_cfg_pad_i73, fabric_direct1_cfg_pad_i74, fabric_direct1_cfg_pad_i75, fabric_direct1_cfg_pad_i76, fabric_direct1_cfg_pad_i77, fabric_direct1_cfg_pad_i78, fabric_direct1_cfg_pad_i79, fabric_direct1_cfg_pad_i80, fabric_direct1_cfg_pad_i81, fabric_direct1_cfg_pad_i82, fabric_direct1_cfg_pad_i83, fabric_direct1_cfg_pad_i84, fabric_direct1_cfg_pad_i85, fabric_direct1_cfg_pad_i86, fabric_direct1_cfg_pad_i87, fabric_direct1_cfg_pad_i88, fabric_direct1_cfg_pad_i89, fabric_direct1_cfg_pad_i90
+, fabric_direct1_cfg_pad_i91, fabric_direct1_cfg_pad_i92, fabric_direct1_cfg_pad_i93, fabric_direct1_cfg_pad_i94, fabric_direct1_cfg_pad_i95, fabric_direct1_cfg_pad_i96, fabric_direct1_cfg_pad_i97, fabric_direct1_cfg_pad_i98, fabric_direct1_cfg_pad_i99, fabric_direct1_cfg_pad_i100, fabric_direct1_cfg_pad_i101, fabric_direct1_cfg_pad_i102, fabric_direct1_cfg_pad_i103, fabric_direct1_cfg_pad_i104, fabric_direct1_cfg_pad_i105, fabric_direct1_cfg_pad_i106, fabric_direct1_cfg_pad_i107, fabric_direct1_cfg_pad_i108, fabric_direct1_cfg_pad_i109, fabric_direct1_cfg_pad_i110, fabric_direct1_cfg_pad_i111
+, fabric_direct1_cfg_pad_i112, fabric_direct1_cfg_pad_i113, fabric_direct1_cfg_pad_i114, fabric_direct1_cfg_pad_i115, fabric_direct1_cfg_pad_i116, fabric_direct1_cfg_pad_i117, fabric_direct1_cfg_pad_i118, fabric_direct1_cfg_pad_i119, fabric_direct1_cfg_pad_i120, fabric_direct1_cfg_pad_i121, fabric_direct1_cfg_pad_i122, fabric_direct1_cfg_pad_i123, fabric_direct1_cfg_pad_i124, fabric_direct1_cfg_pad_i125, fabric_direct1_cfg_pad_i126, fabric_direct1_cfg_pad_i127, fabric_direct1_cfg_pad_i128, fabric_direct1_cfg_pad_i129, fabric_direct1_cfg_pad_i130, fabric_direct1_cfg_pad_i131, fabric_direct1_cfg_pad_i132
+, fabric_direct1_cfg_pad_i133, fabric_direct1_cfg_pad_i134, fabric_direct1_cfg_pad_i135, fabric_direct1_cfg_pad_i136, fabric_direct1_cfg_pad_i137, fabric_direct1_cfg_pad_i138, fabric_direct1_cfg_pad_i139, fabric_direct1_cfg_pad_i140, fabric_direct1_cfg_pad_i141, fabric_direct1_cfg_pad_i142, fabric_direct1_cfg_pad_i143, fabric_direct1_cfg_pad_i144, fabric_direct1_cfg_pad_i145, fabric_direct1_cfg_pad_i146, fabric_direct1_cfg_pad_i147, fabric_direct1_cfg_pad_i148, fabric_direct1_cfg_pad_i149, fabric_direct1_cfg_pad_i150, fabric_direct1_cfg_pad_i151, fabric_direct1_cfg_pad_i152, fabric_direct1_cfg_pad_i153
+, fabric_direct1_cfg_pad_i154, fabric_direct1_cfg_pad_i155, fabric_direct1_cfg_pad_i156, fabric_direct1_cfg_pad_i157, fabric_direct1_cfg_pad_i158, fabric_direct1_cfg_pad_i159, fabric_direct1_cfg_pad_i160, fabric_direct1_cfg_pad_i161, fabric_direct1_cfg_pad_i162, fabric_direct1_cfg_pad_i163, fabric_direct1_cfg_pad_i164, fabric_direct1_cfg_pad_i165, fabric_direct1_cfg_pad_i166, fabric_direct1_cfg_pad_i167, fabric_direct1_cfg_pad_i168, fabric_direct1_cfg_pad_i169, fabric_direct1_cfg_pad_i170, fabric_direct1_cfg_pad_i171, fabric_direct1_cfg_pad_i172, fabric_direct1_cfg_pad_i173, fabric_direct1_cfg_pad_i174
+, fabric_direct1_cfg_pad_i175, fabric_direct1_cfg_pad_i176, fabric_direct1_cfg_pad_i177, fabric_direct1_cfg_pad_i178, fabric_direct1_cfg_pad_i179, fabric_direct1_cfg_pad_i180, fabric_direct1_cfg_pad_i181, fabric_direct1_cfg_pad_i182, fabric_direct1_cfg_pad_i183, fabric_direct1_cfg_pad_i184, fabric_direct1_cfg_pad_i185, fabric_direct1_cfg_pad_i186, fabric_direct1_cfg_pad_i187, fabric_direct1_cfg_pad_i188, fabric_direct1_cfg_pad_i189, fabric_direct1_cfg_pad_i190, fabric_direct1_cfg_pad_i191, fabric_direct1_cfg_pad_i192, fabric_direct1_cfg_pad_i193, fabric_direct1_cfg_pad_i194, fabric_direct1_cfg_pad_i195
+, fabric_direct1_cfg_pad_i196, fabric_direct1_cfg_pad_i197, fabric_direct1_cfg_pad_i198, fabric_direct1_cfg_pad_i199, fabric_direct1_cfg_pad_i200, fabric_direct1_cfg_pad_i201, fabric_direct1_cfg_pad_i202, fabric_direct1_cfg_pad_i203, fabric_direct1_cfg_pad_i204, fabric_direct1_cfg_pad_i205, fabric_direct1_cfg_pad_i206, fabric_direct1_cfg_pad_i207, fabric_direct1_cfg_pad_i208, fabric_direct1_cfg_pad_i209, fabric_direct1_cfg_pad_i210, fabric_direct1_cfg_pad_i211, fabric_direct1_cfg_pad_i212, fabric_direct1_cfg_pad_i213, fabric_direct1_cfg_pad_i214, fabric_direct1_cfg_pad_i215, fabric_direct1_cfg_pad_i216
+, fabric_direct1_cfg_pad_i217, fabric_direct1_cfg_pad_i218, fabric_direct1_cfg_pad_i219, fabric_direct1_cfg_pad_i220, fabric_direct1_cfg_pad_i221, fabric_direct1_cfg_pad_i222, fabric_direct1_cfg_pad_i223, fabric_direct1_cfg_pad_i224, fabric_direct1_cfg_pad_i225, fabric_direct1_cfg_pad_i226, fabric_direct1_cfg_pad_i227, fabric_direct1_cfg_pad_i228, fabric_direct1_cfg_pad_i229, fabric_direct1_cfg_pad_i230, fabric_direct1_cfg_pad_i231, fabric_direct1_cfg_pad_i232, fabric_direct1_cfg_pad_i233, fabric_direct1_cfg_pad_i234, fabric_direct1_cfg_pad_i235, fabric_direct1_cfg_pad_i236, fabric_direct1_cfg_pad_i237
+, fabric_direct1_cfg_pad_i238, fabric_direct1_cfg_pad_i239, fabric_direct1_cfg_pad_i240, fabric_direct1_cfg_pad_i241, fabric_direct1_cfg_pad_i242, fabric_direct1_cfg_pad_i243, fabric_direct1_cfg_pad_i244, fabric_direct1_cfg_pad_i245, fabric_direct1_cfg_pad_i246, fabric_direct1_cfg_pad_i247, fabric_direct1_cfg_pad_i248, fabric_direct1_cfg_pad_i249, fabric_direct1_cfg_pad_i250, fabric_direct1_cfg_pad_i251, fabric_direct1_cfg_pad_i252, fabric_direct1_cfg_pad_i253, fabric_direct1_cfg_pad_i254, fabric_direct1_cfg_pad_i255, fabric_direct1_cfg_pad_i256, fabric_direct1_cfg_pad_i257, fabric_direct1_cfg_pad_i258
+, fabric_direct1_cfg_pad_i259, fabric_direct1_cfg_pad_i260, fabric_direct1_cfg_pad_i261, fabric_direct1_cfg_pad_i262, fabric_direct1_cfg_pad_i263, fabric_direct1_cfg_pad_i264, fabric_direct1_cfg_pad_i265, fabric_direct1_cfg_pad_i266, fabric_direct1_cfg_pad_i267, fabric_direct1_cfg_pad_i268, fabric_direct1_cfg_pad_i269, fabric_direct1_cfg_pad_i270, fabric_direct1_cfg_pad_i271, fabric_direct1_cfg_pad_i272, fabric_direct1_cfg_pad_i273, fabric_direct1_cfg_pad_i274, fabric_direct1_cfg_pad_i275, fabric_direct1_cfg_pad_i276, fabric_direct1_cfg_pad_i277, fabric_direct1_cfg_pad_i278, fabric_direct1_cfg_pad_i279
+, fabric_direct1_cfg_pad_i280, fabric_direct1_cfg_pad_i281, fabric_direct1_cfg_pad_i282, fabric_direct1_cfg_pad_i283, fabric_direct1_cfg_pad_i284, fabric_direct1_cfg_pad_i285, fabric_direct1_cfg_pad_i286, fabric_direct1_cfg_pad_i287, fabric_direct1_cfg_pad_i288, fabric_direct1_cfg_pad_i289, fabric_direct1_cfg_pad_i290, fabric_direct1_cfg_pad_i291, fabric_direct1_cfg_pad_i292, fabric_direct1_cfg_pad_i293, fabric_direct1_cfg_pad_i294, fabric_direct1_cfg_pad_i295, fabric_direct1_cfg_pad_i296, fabric_direct1_cfg_pad_i297, fabric_direct1_cfg_pad_i298, fabric_direct1_cfg_pad_i299, fabric_direct1_cfg_pad_i300
+, fabric_direct1_cfg_pad_i301, fabric_direct1_cfg_pad_i302, fabric_direct1_cfg_pad_i303, fabric_direct1_cfg_pad_i304, fabric_direct1_cfg_pad_i305, fabric_direct1_cfg_pad_i306, fabric_direct1_cfg_pad_i307, fabric_direct1_cfg_pad_i308, fabric_direct1_cfg_pad_i309, fabric_direct1_cfg_pad_i310, fabric_direct1_cfg_pad_i311, fabric_direct1_cfg_pad_i312, fabric_direct1_cfg_pad_i313, fabric_direct1_cfg_pad_i314, fabric_direct1_cfg_pad_i315, fabric_direct1_cfg_pad_i316, fabric_direct1_cfg_pad_i317, fabric_direct1_cfg_pad_i318, fabric_direct1_cfg_pad_i319, fabric_direct1_cfg_pad_i320, fabric_direct1_cfg_pad_i321
+, fabric_direct1_cfg_pad_i322, fabric_direct1_cfg_pad_i323, fabric_direct1_cfg_pad_i324, fabric_direct1_cfg_pad_i325, fabric_direct1_cfg_pad_i326, fabric_direct1_cfg_pad_i327, fabric_direct1_cfg_pad_i328, fabric_direct1_cfg_pad_i329, fabric_direct1_cfg_pad_i330, fabric_direct1_cfg_pad_i331, fabric_direct1_cfg_pad_i332, fabric_direct1_cfg_pad_i333, fabric_direct1_cfg_pad_i334, fabric_direct1_cfg_pad_i335, fabric_direct1_cfg_pad_i336, fabric_direct1_cfg_pad_i337, fabric_direct1_cfg_pad_i338, fabric_direct1_cfg_pad_i339, fabric_direct1_cfg_pad_i340, fabric_direct1_cfg_pad_i341, fabric_direct1_cfg_pad_i342
+, fabric_direct1_cfg_pad_i343, fabric_direct1_cfg_pad_i344, fabric_direct1_cfg_pad_i345, fabric_direct1_cfg_pad_i346, fabric_direct1_cfg_pad_i347, fabric_direct1_cfg_pad_i348, fabric_direct1_cfg_pad_i349, fabric_direct1_cfg_pad_i350, fabric_direct1_cfg_pad_i351, fabric_direct1_cfg_pad_i352, fabric_direct1_cfg_pad_i353, fabric_direct1_cfg_pad_i354, fabric_direct1_cfg_pad_i355, fabric_direct1_cfg_pad_i356, fabric_direct1_cfg_pad_i357, fabric_direct1_cfg_pad_i358, fabric_direct1_cfg_pad_i359, fabric_direct1_cfg_pad_i360, fabric_direct1_cfg_pad_i361, fabric_direct1_cfg_pad_i362, fabric_direct1_cfg_pad_i363
+, fabric_direct1_cfg_pad_i364, fabric_direct1_cfg_pad_i365, fabric_direct1_cfg_pad_i366, fabric_direct1_cfg_pad_i367, fabric_direct1_cfg_pad_i368, fabric_direct1_cfg_pad_i369, fabric_direct1_cfg_pad_i370, fabric_direct1_cfg_pad_i371, fabric_direct1_cfg_pad_i372, fabric_direct1_cfg_pad_i373, fabric_direct1_cfg_pad_i374, fabric_direct1_cfg_pad_i375, fabric_direct1_cfg_pad_i376, fabric_direct1_cfg_pad_i377, fabric_direct1_cfg_pad_i378, fabric_direct1_cfg_pad_i379, fabric_direct1_cfg_pad_i380, fabric_direct1_cfg_pad_i381, fabric_direct1_cfg_pad_i382, fabric_direct1_cfg_pad_i383, fabric_direct1_cfg_pad_i384
+, fabric_direct1_cfg_pad_i385, fabric_direct1_cfg_pad_i386, fabric_direct1_cfg_pad_i387, fabric_direct1_cfg_pad_i388, fabric_direct1_cfg_pad_i389, fabric_direct1_cfg_pad_i390, fabric_direct1_cfg_pad_i391, fabric_direct1_cfg_pad_i392, fabric_direct1_cfg_pad_i393, fabric_direct1_cfg_pad_i394, fabric_direct1_cfg_pad_i395, fabric_direct1_cfg_pad_i396, fabric_direct1_cfg_pad_i397, fabric_direct1_cfg_pad_i398, fabric_direct1_cfg_pad_i399, fabric_direct1_cfg_pad_i400, fabric_direct1_cfg_pad_i401, fabric_direct1_cfg_pad_i402, fabric_direct1_cfg_pad_i403, fabric_direct1_cfg_pad_i404, fabric_direct1_cfg_pad_i405
+, fabric_direct1_cfg_pad_i406, fabric_direct1_cfg_pad_i407, fabric_direct1_cfg_pad_i408, fabric_direct1_cfg_pad_i409, fabric_direct1_cfg_pad_i410, fabric_direct1_cfg_pad_i411, fabric_direct1_cfg_pad_i412, fabric_direct1_cfg_pad_i413, fabric_direct1_cfg_pad_i414, fabric_direct1_cfg_pad_i415, fabric_direct1_cfg_pad_i416, fabric_direct1_cfg_pad_i417, fabric_direct1_cfg_pad_i418, fabric_direct1_cfg_pad_i419, fabric_direct1_cfg_pad_i420, fabric_direct1_cfg_pad_i421, fabric_direct1_cfg_pad_i422, fabric_direct1_cfg_pad_i423, fabric_direct1_cfg_pad_i424, fabric_direct1_cfg_pad_i425, fabric_direct1_cfg_pad_i426
+, fabric_direct1_cfg_pad_i427, fabric_direct1_cfg_pad_i428, fabric_direct1_cfg_pad_i429, fabric_direct1_cfg_pad_i430, fabric_direct1_cfg_pad_i431, fabric_direct1_cfg_pad_i432, fabric_direct1_cfg_pad_i433, fabric_direct1_cfg_pad_i434, fabric_direct1_cfg_pad_i435, fabric_direct1_cfg_pad_i436, fabric_direct1_cfg_pad_i437, fabric_direct1_cfg_pad_i438, fabric_direct1_cfg_pad_i439, fabric_direct1_cfg_pad_i440, fabric_direct1_cfg_pad_i441, fabric_direct1_cfg_pad_i442, fabric_direct1_cfg_pad_i443, fabric_direct1_cfg_pad_i444, fabric_direct1_cfg_pad_i445, fabric_direct1_cfg_pad_i446, fabric_direct1_cfg_pad_i447
+, fabric_direct1_cfg_pad_i448, fabric_direct1_cfg_pad_i449, fabric_direct1_cfg_pad_i450, fabric_direct1_cfg_pad_i451, fabric_direct1_cfg_pad_i452, fabric_direct1_cfg_pad_i453, fabric_direct1_cfg_pad_i454, fabric_direct1_cfg_pad_i455, fabric_direct1_cfg_pad_i456, fabric_direct1_cfg_pad_i457, fabric_direct1_cfg_pad_i458, fabric_direct1_cfg_pad_i459, fabric_direct1_cfg_pad_i460, fabric_direct1_cfg_pad_i461, fabric_direct1_cfg_pad_i462, fabric_direct1_cfg_pad_i463, fabric_direct1_cfg_pad_i464, fabric_direct1_cfg_pad_i465, fabric_direct1_cfg_pad_i466, fabric_direct1_cfg_pad_i467, fabric_direct1_cfg_pad_i468
+, fabric_direct1_cfg_pad_i469, fabric_direct1_cfg_pad_i470, fabric_direct1_cfg_pad_i471, fabric_direct1_cfg_pad_i472, fabric_direct1_cfg_pad_i473, fabric_direct1_cfg_pad_i474, fabric_direct1_cfg_pad_i475, fabric_direct1_cfg_pad_i476, fabric_direct1_cfg_pad_i477, fabric_direct1_cfg_pad_i478, fabric_direct1_cfg_pad_i479, fabric_direct1_cfg_pad_i480, fabric_direct1_scan_en_i, fabric_direct1_loopback_en_i, fabric_direct1_loopback_mux_i, fabric_thsens_clk_i, fabric_thsens_arst_tmr_n_i1, fabric_thsens_arst_tmr_n_i2, fabric_thsens_arst_tmr_n_i3, fabric_thsens_fm_enable_i, fabric_thsens_fm_mode_w_i1
+, fabric_thsens_fm_mode_w_i2, fabric_thsens_fm_mode_w_i3, fabric_thsens_fm_mode_w_i4, fabric_thsens_fm_mode_w_i5, fabric_thsens_fm_mode_w_i6, fabric_thsens_fm_mode_w_i7, fabric_thsens_fm_mode_w_i8, fabric_thsens_fm_mode_w_i9, fabric_thsens_fm_mode_w_i10, fabric_thsens_fm_mode_w_i11, fabric_thsens_fm_mode_w_i12, fabric_thsens_fm_mode_w_i13, fabric_thsens_fm_mode_w_i14, fabric_thsens_fm_mode_w_i15, fabric_thsens_fm_mode_w_i16, fabric_thsens_fm_mode_w_i17, fabric_thsens_fm_mode_w_i18, fabric_thsens_fm_mode_w_i19, fabric_thsens_fm_mode_w_i20, fabric_thsens_fm_mode_w_i21, fabric_thsens_fm_mode_w_i22
+, fabric_thsens_fm_mode_w_i23, fabric_thsens_fm_mode_w_i24, fabric_thsens_fm_mode_w_i25, fabric_thsens_fm_mode_w_i26, fabric_thsens_fm_mode_w_i27, fabric_thsens_fm_mode_w_i28, fabric_thsens_fm_mode_w_i29, fabric_thsens_fm_mode_w_i30, fabric_thsens_fm_mode_w_i31, fabric_thsens_fm_mode_w_i32, fabric_thsens_fm_mode_wen_i, fabric_thsens_fm_config_w_i1, fabric_thsens_fm_config_w_i2, fabric_thsens_fm_config_w_i3, fabric_thsens_fm_config_w_i4, fabric_thsens_fm_config_w_i5, fabric_thsens_fm_config_w_i6, fabric_thsens_fm_config_w_i7, fabric_thsens_fm_config_w_i8, fabric_thsens_fm_config_w_i9, fabric_thsens_fm_config_w_i10
+, fabric_thsens_fm_config_w_i11, fabric_thsens_fm_config_w_i12, fabric_thsens_fm_config_w_i13, fabric_thsens_fm_config_w_i14, fabric_thsens_fm_config_w_i15, fabric_thsens_fm_config_w_i16, fabric_thsens_fm_config_w_i17, fabric_thsens_fm_config_w_i18, fabric_thsens_fm_config_w_i19, fabric_thsens_fm_config_w_i20, fabric_thsens_fm_config_w_i21, fabric_thsens_fm_config_w_i22, fabric_thsens_fm_config_w_i23, fabric_thsens_fm_config_w_i24, fabric_thsens_fm_config_w_i25, fabric_thsens_fm_config_w_i26, fabric_thsens_fm_config_w_i27, fabric_thsens_fm_config_wen_i, fabric_thsens_fm_data_o1, fabric_thsens_fm_data_o2, fabric_thsens_fm_data_o3
+, fabric_thsens_fm_data_o4, fabric_thsens_fm_data_o5, fabric_thsens_fm_data_o6, fabric_thsens_fm_data_o7, fabric_thsens_fm_data_o8, fabric_thsens_fm_data_o9, fabric_thsens_fm_data_o10, fabric_thsens_fm_data_o11, fabric_thsens_fm_data_o12, fabric_thsens_fm_data_o13, fabric_thsens_fm_data_o14, fabric_thsens_fm_valid_o, fabric_thsens_fm_overflow_o, fabric_thsens_fm_mode_r_o1, fabric_thsens_fm_mode_r_o2, fabric_thsens_fm_mode_r_o3, fabric_thsens_fm_mode_r_o4, fabric_thsens_fm_mode_r_o5, fabric_thsens_fm_mode_r_o6, fabric_thsens_fm_mode_r_o7, fabric_thsens_fm_mode_r_o8
+, fabric_thsens_fm_mode_r_o9, fabric_thsens_fm_mode_r_o10, fabric_thsens_fm_mode_r_o11, fabric_thsens_fm_mode_r_o12, fabric_thsens_fm_mode_r_o13, fabric_thsens_fm_mode_r_o14, fabric_thsens_fm_mode_r_o15, fabric_thsens_fm_mode_r_o16, fabric_thsens_fm_mode_r_o17, fabric_thsens_fm_mode_r_o18, fabric_thsens_fm_mode_r_o19, fabric_thsens_fm_mode_r_o20, fabric_thsens_fm_mode_r_o21, fabric_thsens_fm_mode_r_o22, fabric_thsens_fm_mode_r_o23, fabric_thsens_fm_mode_r_o24, fabric_thsens_fm_mode_r_o25, fabric_thsens_fm_mode_r_o26, fabric_thsens_fm_mode_r_o27, fabric_thsens_fm_mode_r_o28, fabric_thsens_fm_mode_r_o29
+, fabric_thsens_fm_mode_r_o30, fabric_thsens_fm_mode_r_o31, fabric_thsens_fm_mode_r_o32, fabric_thsens_fm_config_r_o1, fabric_thsens_fm_config_r_o2, fabric_thsens_fm_config_r_o3, fabric_thsens_fm_config_r_o4, fabric_thsens_fm_config_r_o5, fabric_thsens_fm_config_r_o6, fabric_thsens_fm_config_r_o7, fabric_thsens_fm_config_r_o8, fabric_thsens_fm_config_r_o9, fabric_thsens_fm_config_r_o10, fabric_thsens_fm_config_r_o11, fabric_thsens_fm_config_r_o12, fabric_thsens_fm_config_r_o13, fabric_thsens_fm_config_r_o14, fabric_thsens_fm_config_r_o15, fabric_thsens_fm_config_r_o16, fabric_thsens_fm_config_r_o17, fabric_thsens_fm_config_r_o18
+, fabric_thsens_fm_config_r_o19, fabric_thsens_fm_config_r_o20, fabric_thsens_fm_config_r_o21, fabric_thsens_fm_config_r_o22, fabric_thsens_fm_config_r_o23, fabric_thsens_fm_config_r_o24, fabric_thsens_fm_config_r_o25, fabric_thsens_fm_config_r_o26, fabric_thsens_fm_config_r_o27, fabric_thsens_clk_div_ratio_i1, fabric_thsens_clk_div_ratio_i2, fabric_thsens_clk_div_ratio_i3, fabric_thsens_clk_div_ratio_i4, fabric_thsens_clk_div_ratio_i5, fabric_thsens_clk_div_ratio_i6, fabric_thsens_clk_div_ratio_i7, fabric_thsens_clk_div_ratio_i8, fabric_thsens_tst_scanenable_i, fabric_thsens_tst_scanin1_i, fabric_thsens_tst_scanin2_i, fabric_thsens_tst_scanout1_o
+, fabric_thsens_tst_scanout2_o, fabric_thsens_otp_config_o1, fabric_thsens_otp_config_o2, fabric_thsens_otp_config_o3, fabric_thsens_otp_config_o4, fabric_thsens_otp_config_o5, fabric_thsens_otp_config_o6, fabric_thsens_otp_config_o7, fabric_thsens_otp_config_o8, fabric_thsens_otp_config_o9, fabric_thsens_otp_config_o10, fabric_thsens_otp_config_o11, fabric_thsens_otp_config_o12, fabric_thsens_otp_config_o13, fabric_thsens_otp_config_o14, fabric_thsens_otp_config_o15, fabric_thsens_otp_config_o16, fabric_thsens_otp_config_o17, fabric_thsens_otp_config_o18, fabric_thsens_otp_config_o19, fabric_thsens_otp_config_o20
+, fabric_thsens_otp_config_o21, fabric_thsens_otp_config_o22, fabric_thsens_otp_config_o23, fabric_thsens_otp_config_o24, fabric_thsens_otp_config_o25, fabric_thsens_otp_config_o26, fabric_thsens_otp_config_o27, fabric_spi_clk_i2, fabric_spi_sck_i2, fabric_spi_clk_i0, fabric_spi_sck_i0, fabric_spi_clk_i1, fabric_spi_sck_i1, fabric_spi_needed_i1, fabric_spi_needed_i2, fabric_spi_needed_i3, fabric_spi_bsm_release_o1, fabric_spi_bsm_release_o2, fabric_spi_bsm_release_o3, fabric_spi_arst_tmr_n_i1, fabric_spi_arst_tmr_n_i2
+, fabric_spi_arst_tmr_n_i3, fabric_spi_arst_tmr_n_i4, fabric_spi_arst_tmr_n_i5, fabric_spi_arst_tmr_n_i6, fabric_spi_arst_tmr_n_i7, fabric_spi_arst_tmr_n_i8, fabric_spi_arst_tmr_n_i9, fabric_spi_fifo_arst_tmr_n_i1, fabric_spi_fifo_arst_tmr_n_i2, fabric_spi_fifo_arst_tmr_n_i3, fabric_spi_fifo_arst_tmr_n_i4, fabric_spi_fifo_arst_tmr_n_i5, fabric_spi_fifo_arst_tmr_n_i6, fabric_spi_fifo_arst_tmr_n_i7, fabric_spi_fifo_arst_tmr_n_i8, fabric_spi_fifo_arst_tmr_n_i9, fabric_spi_cpol_i1, fabric_spi_cpol_i2, fabric_spi_cpol_i3, fabric_spi_cpha_i1, fabric_spi_cpha_i2
+, fabric_spi_cpha_i3, fabric_spi_loopback_i1, fabric_spi_loopback_i2, fabric_spi_loopback_i3, fabric_spi_lsb_first_i1, fabric_spi_lsb_first_i2, fabric_spi_lsb_first_i3, fabric_spi_cs_setuptime_i1, fabric_spi_cs_setuptime_i2, fabric_spi_cs_setuptime_i3, fabric_spi_cs_setuptime_i4, fabric_spi_cs_setuptime_i5, fabric_spi_cs_setuptime_i6, fabric_spi_cs_setuptime_i7, fabric_spi_cs_setuptime_i8, fabric_spi_cs_setuptime_i9, fabric_spi_cs_setuptime_i10, fabric_spi_cs_setuptime_i11, fabric_spi_cs_setuptime_i12, fabric_spi_cs_holdtime_i1, fabric_spi_cs_holdtime_i2
+, fabric_spi_cs_holdtime_i3, fabric_spi_cs_holdtime_i4, fabric_spi_cs_holdtime_i5, fabric_spi_cs_holdtime_i6, fabric_spi_cs_holdtime_i7, fabric_spi_cs_holdtime_i8, fabric_spi_cs_holdtime_i9, fabric_spi_cs_holdtime_i10, fabric_spi_cs_holdtime_i11, fabric_spi_cs_holdtime_i12, fabric_spi_cs_offtime_i1, fabric_spi_cs_offtime_i2, fabric_spi_cs_offtime_i3, fabric_spi_cs_offtime_i4, fabric_spi_cs_offtime_i5, fabric_spi_cs_offtime_i6, fabric_spi_cs_offtime_i7, fabric_spi_cs_offtime_i8, fabric_spi_cs_offtime_i9, fabric_spi_cs_offtime_i10, fabric_spi_cs_offtime_i11
+, fabric_spi_cs_offtime_i12, fabric_spi_vcc_enable_i1, fabric_spi_vcc_enable_i2, fabric_spi_vcc_enable_i3, fabric_spi_powerdown_cycle_i1, fabric_spi_powerdown_cycle_i2, fabric_spi_powerdown_cycle_i3, fabric_spi_powerdown_cycle_i4, fabric_spi_powerdown_cycle_i5, fabric_spi_powerdown_cycle_i6, fabric_spi_powerdown_cycle_i7, fabric_spi_powerdown_cycle_i8, fabric_spi_powerdown_cycle_i9, fabric_spi_powerdown_cycle_i10, fabric_spi_powerdown_cycle_i11, fabric_spi_powerdown_cycle_i12, fabric_spi_powerdown_cycle_i13, fabric_spi_powerdown_cycle_i14, fabric_spi_powerdown_cycle_i15, fabric_spi_powerdown_cycle_i16, fabric_spi_powerdown_cycle_i17
+, fabric_spi_powerdown_cycle_i18, fabric_spi_powerdown_cycle_i19, fabric_spi_powerdown_cycle_i20, fabric_spi_powerdown_cycle_i21, fabric_spi_powerdown_cycle_i22, fabric_spi_powerdown_cycle_i23, fabric_spi_powerdown_cycle_i24, fabric_spi_powerdown_cycle_i25, fabric_spi_powerdown_cycle_i26, fabric_spi_powerdown_cycle_i27, fabric_spi_powerdown_cycle_i28, fabric_spi_powerdown_cycle_i29, fabric_spi_powerdown_cycle_i30, fabric_spi_powerdown_cycle_i31, fabric_spi_powerdown_cycle_i32, fabric_spi_powerdown_cycle_i33, fabric_spi_powerdown_cycle_i34, fabric_spi_powerdown_cycle_i35, fabric_spi_powerdown_cycle_i36, fabric_spi_powerdown_cycle_i37, fabric_spi_powerdown_cycle_i38
+, fabric_spi_powerdown_cycle_i39, fabric_spi_powerdown_cycle_i40, fabric_spi_powerdown_cycle_i41, fabric_spi_powerdown_cycle_i42, fabric_spi_powerdown_cycle_i43, fabric_spi_powerdown_cycle_i44, fabric_spi_powerdown_cycle_i45, fabric_spi_powerdown_cycle_i46, fabric_spi_powerdown_cycle_i47, fabric_spi_powerdown_cycle_i48, fabric_spi_powerup_cycle_i1, fabric_spi_powerup_cycle_i2, fabric_spi_powerup_cycle_i3, fabric_spi_powerup_cycle_i4, fabric_spi_powerup_cycle_i5, fabric_spi_powerup_cycle_i6, fabric_spi_powerup_cycle_i7, fabric_spi_powerup_cycle_i8, fabric_spi_powerup_cycle_i9, fabric_spi_powerup_cycle_i10, fabric_spi_powerup_cycle_i11
+, fabric_spi_powerup_cycle_i12, fabric_spi_powerup_cycle_i13, fabric_spi_powerup_cycle_i14, fabric_spi_powerup_cycle_i15, fabric_spi_powerup_cycle_i16, fabric_spi_powerup_cycle_i17, fabric_spi_powerup_cycle_i18, fabric_spi_powerup_cycle_i19, fabric_spi_powerup_cycle_i20, fabric_spi_powerup_cycle_i21, fabric_spi_powerup_cycle_i22, fabric_spi_powerup_cycle_i23, fabric_spi_powerup_cycle_i24, fabric_spi_powerup_cycle_i25, fabric_spi_powerup_cycle_i26, fabric_spi_powerup_cycle_i27, fabric_spi_powerup_cycle_i28, fabric_spi_powerup_cycle_i29, fabric_spi_powerup_cycle_i30, fabric_spi_powerup_cycle_i31, fabric_spi_powerup_cycle_i32
+, fabric_spi_powerup_cycle_i33, fabric_spi_powerup_cycle_i34, fabric_spi_powerup_cycle_i35, fabric_spi_powerup_cycle_i36, fabric_spi_powerup_cycle_i37, fabric_spi_powerup_cycle_i38, fabric_spi_powerup_cycle_i39, fabric_spi_powerup_cycle_i40, fabric_spi_powerup_cycle_i41, fabric_spi_powerup_cycle_i42, fabric_spi_powerup_cycle_i43, fabric_spi_powerup_cycle_i44, fabric_spi_powerup_cycle_i45, fabric_spi_powerup_cycle_i46, fabric_spi_powerup_cycle_i47, fabric_spi_powerup_cycle_i48, fabric_spi_legacy_enable_i1, fabric_spi_legacy_enable_i2, fabric_spi_legacy_enable_i3, fabric_spi_legacy_master_i1, fabric_spi_legacy_master_i2
+, fabric_spi_legacy_master_i3, fabric_spi_data_in_unlimited_i1, fabric_spi_data_in_unlimited_i2, fabric_spi_data_in_unlimited_i3, fabric_spi_enable_i1, fabric_spi_enable_i2, fabric_spi_enable_i3, fabric_spi_rst_n_i1, fabric_spi_rst_n_i2, fabric_spi_rst_n_i3, fabric_spi_init_done_o1, fabric_spi_init_done_o2, fabric_spi_init_done_o3, fabric_spi_busy_o1, fabric_spi_busy_o2, fabric_spi_busy_o3, fabric_spi_vcc_used_o1, fabric_spi_vcc_used_o2, fabric_spi_vcc_used_o3, fabric_spi_error_sel_o1, fabric_spi_error_sel_o2
+, fabric_spi_error_sel_o3, fabric_spi_error_loopback_o1, fabric_spi_error_loopback_o2, fabric_spi_error_loopback_o3, fabric_spi_error_mode_o1, fabric_spi_error_mode_o2, fabric_spi_error_mode_o3, fabric_spi_error_endianness_o1, fabric_spi_error_endianness_o2, fabric_spi_error_endianness_o3, fabric_spi_cmd_push_i1, fabric_spi_cmd_push_i2, fabric_spi_cmd_push_i3, fabric_spi_cmd_full_o1, fabric_spi_cmd_full_o2, fabric_spi_cmd_full_o3, fabric_spi_cmd_type_i1, fabric_spi_cmd_type_i2, fabric_spi_cmd_type_i3, fabric_spi_cmd_type_i4, fabric_spi_cmd_type_i5
+, fabric_spi_cmd_type_i6, fabric_spi_cmd_mode_i1, fabric_spi_cmd_mode_i2, fabric_spi_cmd_mode_i3, fabric_spi_cmd_mode_i4, fabric_spi_cmd_mode_i5, fabric_spi_cmd_mode_i6, fabric_spi_cmd_bytes_i1, fabric_spi_cmd_bytes_i2, fabric_spi_cmd_bytes_i3, fabric_spi_cmd_bytes_i4, fabric_spi_cmd_bytes_i5, fabric_spi_cmd_bytes_i6, fabric_spi_mosi_push_i1, fabric_spi_mosi_push_i2, fabric_spi_mosi_push_i3, fabric_spi_mosi_full_o1, fabric_spi_mosi_full_o2, fabric_spi_mosi_full_o3, fabric_spi_mosi_data_i1, fabric_spi_mosi_data_i2
+, fabric_spi_mosi_data_i3, fabric_spi_mosi_data_i4, fabric_spi_mosi_data_i5, fabric_spi_mosi_data_i6, fabric_spi_mosi_data_i7, fabric_spi_mosi_data_i8, fabric_spi_mosi_data_i9, fabric_spi_mosi_data_i10, fabric_spi_mosi_data_i11, fabric_spi_mosi_data_i12, fabric_spi_mosi_data_i13, fabric_spi_mosi_data_i14, fabric_spi_mosi_data_i15, fabric_spi_mosi_data_i16, fabric_spi_mosi_data_i17, fabric_spi_mosi_data_i18, fabric_spi_mosi_data_i19, fabric_spi_mosi_data_i20, fabric_spi_mosi_data_i21, fabric_spi_mosi_data_i22, fabric_spi_mosi_data_i23
+, fabric_spi_mosi_data_i24, fabric_spi_mosi_data_inv_i1, fabric_spi_mosi_data_inv_i2, fabric_spi_mosi_data_inv_i3, fabric_spi_miso_pop_i1, fabric_spi_miso_pop_i2, fabric_spi_miso_pop_i3, fabric_spi_miso_empty_o1, fabric_spi_miso_empty_o2, fabric_spi_miso_empty_o3, fabric_spi_miso_data_o1, fabric_spi_miso_data_o2, fabric_spi_miso_data_o3, fabric_spi_miso_data_o4, fabric_spi_miso_data_o5, fabric_spi_miso_data_o6, fabric_spi_miso_data_o7, fabric_spi_miso_data_o8, fabric_spi_miso_data_o9, fabric_spi_miso_data_o10, fabric_spi_miso_data_o11
+, fabric_spi_miso_data_o12, fabric_spi_miso_data_o13, fabric_spi_miso_data_o14, fabric_spi_miso_data_o15, fabric_spi_miso_data_o16, fabric_spi_miso_data_o17, fabric_spi_miso_data_o18, fabric_spi_miso_data_o19, fabric_spi_miso_data_o20, fabric_spi_miso_data_o21, fabric_spi_miso_data_o22, fabric_spi_miso_data_o23, fabric_spi_miso_data_o24, fabric_spi_miso_data_inv_o1, fabric_spi_miso_data_inv_o2, fabric_spi_miso_data_inv_o3, fabric_spw0_clk_i, fabric_spw0_clk_tx_i, fabric_spw0_rst_n_i, fabric_spw0_user_shared_o, fabric_spw0_tx_fifo_write_i
+, fabric_spw0_tx_fifo_data_i1, fabric_spw0_tx_fifo_data_i2, fabric_spw0_tx_fifo_data_i3, fabric_spw0_tx_fifo_data_i4, fabric_spw0_tx_fifo_data_i5, fabric_spw0_tx_fifo_data_i6, fabric_spw0_tx_fifo_data_i7, fabric_spw0_tx_fifo_data_i8, fabric_spw0_tx_fifo_data_i9, fabric_spw0_tx_fifo_full_o, fabric_spw0_rx_fifo_read_i, fabric_spw0_rx_fifo_empty_o, fabric_spw0_rx_fifo_data_o1, fabric_spw0_rx_fifo_data_o2, fabric_spw0_rx_fifo_data_o3, fabric_spw0_rx_fifo_data_o4, fabric_spw0_rx_fifo_data_o5, fabric_spw0_rx_fifo_data_o6, fabric_spw0_rx_fifo_data_o7, fabric_spw0_rx_fifo_data_o8, fabric_spw0_rx_fifo_data_o9
+, fabric_spw0_tick_ctm_i, fabric_spw0_tick_ctm_o, fabric_spw0_apb_slv_psel_i, fabric_spw0_apb_slv_penable_i, fabric_spw0_apb_slv_paddr_i1, fabric_spw0_apb_slv_paddr_i2, fabric_spw0_apb_slv_paddr_i3, fabric_spw0_apb_slv_paddr_i4, fabric_spw0_apb_slv_paddr_i5, fabric_spw0_apb_slv_pwrite_i, fabric_spw0_apb_slv_pwdata_i1, fabric_spw0_apb_slv_pwdata_i2, fabric_spw0_apb_slv_pwdata_i3, fabric_spw0_apb_slv_pwdata_i4, fabric_spw0_apb_slv_pwdata_i5, fabric_spw0_apb_slv_pwdata_i6, fabric_spw0_apb_slv_pwdata_i7, fabric_spw0_apb_slv_pwdata_i8, fabric_spw0_apb_slv_pwdata_i9, fabric_spw0_apb_slv_pwdata_i10, fabric_spw0_apb_slv_pwdata_i11
+, fabric_spw0_apb_slv_pwdata_i12, fabric_spw0_apb_slv_pwdata_i13, fabric_spw0_apb_slv_pwdata_i14, fabric_spw0_apb_slv_pwdata_i15, fabric_spw0_apb_slv_pwdata_i16, fabric_spw0_apb_slv_pwdata_i17, fabric_spw0_apb_slv_pwdata_i18, fabric_spw0_apb_slv_pwdata_i19, fabric_spw0_apb_slv_pwdata_i20, fabric_spw0_apb_slv_pwdata_i21, fabric_spw0_apb_slv_pwdata_i22, fabric_spw0_apb_slv_pwdata_i23, fabric_spw0_apb_slv_pwdata_i24, fabric_spw0_apb_slv_pwdata_i25, fabric_spw0_apb_slv_pwdata_i26, fabric_spw0_apb_slv_pwdata_i27, fabric_spw0_apb_slv_pwdata_i28, fabric_spw0_apb_slv_pwdata_i29, fabric_spw0_apb_slv_pwdata_i30, fabric_spw0_apb_slv_pwdata_i31, fabric_spw0_apb_slv_prdata_o1
+, fabric_spw0_apb_slv_prdata_o2, fabric_spw0_apb_slv_prdata_o3, fabric_spw0_apb_slv_prdata_o4, fabric_spw0_apb_slv_prdata_o5, fabric_spw0_apb_slv_prdata_o6, fabric_spw0_apb_slv_prdata_o7, fabric_spw0_apb_slv_prdata_o8, fabric_spw0_apb_slv_prdata_o9, fabric_spw0_apb_slv_prdata_o10, fabric_spw0_apb_slv_prdata_o11, fabric_spw0_apb_slv_prdata_o12, fabric_spw0_apb_slv_prdata_o13, fabric_spw0_apb_slv_prdata_o14, fabric_spw0_apb_slv_prdata_o15, fabric_spw0_apb_slv_prdata_o16, fabric_spw0_apb_slv_prdata_o17, fabric_spw0_apb_slv_prdata_o18, fabric_spw0_apb_slv_prdata_o19, fabric_spw0_apb_slv_prdata_o20, fabric_spw0_apb_slv_prdata_o21, fabric_spw0_apb_slv_prdata_o22
+, fabric_spw0_apb_slv_prdata_o23, fabric_spw0_apb_slv_prdata_o24, fabric_spw0_apb_slv_prdata_o25, fabric_spw0_apb_slv_prdata_o26, fabric_spw0_apb_slv_prdata_o27, fabric_spw0_apb_slv_prdata_o28, fabric_spw0_apb_slv_prdata_o29, fabric_spw0_apb_slv_prdata_o30, fabric_spw0_apb_slv_prdata_o31, fabric_spw0_apb_slv_pready_o, fabric_spw0_apb_slv_pslverr_o, fabric_spw1_clk_i, fabric_spw1_clk_tx_i, fabric_spw1_rst_n_i, fabric_spw1_user_shared_o, fabric_spw1_tx_fifo_write_i, fabric_spw1_tx_fifo_data_i1, fabric_spw1_tx_fifo_data_i2, fabric_spw1_tx_fifo_data_i3, fabric_spw1_tx_fifo_data_i4, fabric_spw1_tx_fifo_data_i5
+, fabric_spw1_tx_fifo_data_i6, fabric_spw1_tx_fifo_data_i7, fabric_spw1_tx_fifo_data_i8, fabric_spw1_tx_fifo_data_i9, fabric_spw1_tx_fifo_full_o, fabric_spw1_rx_fifo_read_i, fabric_spw1_rx_fifo_empty_o, fabric_spw1_rx_fifo_data_o1, fabric_spw1_rx_fifo_data_o2, fabric_spw1_rx_fifo_data_o3, fabric_spw1_rx_fifo_data_o4, fabric_spw1_rx_fifo_data_o5, fabric_spw1_rx_fifo_data_o6, fabric_spw1_rx_fifo_data_o7, fabric_spw1_rx_fifo_data_o8, fabric_spw1_rx_fifo_data_o9, fabric_spw1_tick_ctm_i, fabric_spw1_tick_ctm_o, fabric_spw1_apb_slv_psel_i, fabric_spw1_apb_slv_penable_i, fabric_spw1_apb_slv_paddr_i1
+, fabric_spw1_apb_slv_paddr_i2, fabric_spw1_apb_slv_paddr_i3, fabric_spw1_apb_slv_paddr_i4, fabric_spw1_apb_slv_paddr_i5, fabric_spw1_apb_slv_pwrite_i, fabric_spw1_apb_slv_pwdata_i1, fabric_spw1_apb_slv_pwdata_i2, fabric_spw1_apb_slv_pwdata_i3, fabric_spw1_apb_slv_pwdata_i4, fabric_spw1_apb_slv_pwdata_i5, fabric_spw1_apb_slv_pwdata_i6, fabric_spw1_apb_slv_pwdata_i7, fabric_spw1_apb_slv_pwdata_i8, fabric_spw1_apb_slv_pwdata_i9, fabric_spw1_apb_slv_pwdata_i10, fabric_spw1_apb_slv_pwdata_i11, fabric_spw1_apb_slv_pwdata_i12, fabric_spw1_apb_slv_pwdata_i13, fabric_spw1_apb_slv_pwdata_i14, fabric_spw1_apb_slv_pwdata_i15, fabric_spw1_apb_slv_pwdata_i16
+, fabric_spw1_apb_slv_pwdata_i17, fabric_spw1_apb_slv_pwdata_i18, fabric_spw1_apb_slv_pwdata_i19, fabric_spw1_apb_slv_pwdata_i20, fabric_spw1_apb_slv_pwdata_i21, fabric_spw1_apb_slv_pwdata_i22, fabric_spw1_apb_slv_pwdata_i23, fabric_spw1_apb_slv_pwdata_i24, fabric_spw1_apb_slv_pwdata_i25, fabric_spw1_apb_slv_pwdata_i26, fabric_spw1_apb_slv_pwdata_i27, fabric_spw1_apb_slv_pwdata_i28, fabric_spw1_apb_slv_pwdata_i29, fabric_spw1_apb_slv_pwdata_i30, fabric_spw1_apb_slv_pwdata_i31, fabric_spw1_apb_slv_prdata_o1, fabric_spw1_apb_slv_prdata_o2, fabric_spw1_apb_slv_prdata_o3, fabric_spw1_apb_slv_prdata_o4, fabric_spw1_apb_slv_prdata_o5, fabric_spw1_apb_slv_prdata_o6
+, fabric_spw1_apb_slv_prdata_o7, fabric_spw1_apb_slv_prdata_o8, fabric_spw1_apb_slv_prdata_o9, fabric_spw1_apb_slv_prdata_o10, fabric_spw1_apb_slv_prdata_o11, fabric_spw1_apb_slv_prdata_o12, fabric_spw1_apb_slv_prdata_o13, fabric_spw1_apb_slv_prdata_o14, fabric_spw1_apb_slv_prdata_o15, fabric_spw1_apb_slv_prdata_o16, fabric_spw1_apb_slv_prdata_o17, fabric_spw1_apb_slv_prdata_o18, fabric_spw1_apb_slv_prdata_o19, fabric_spw1_apb_slv_prdata_o20, fabric_spw1_apb_slv_prdata_o21, fabric_spw1_apb_slv_prdata_o22, fabric_spw1_apb_slv_prdata_o23, fabric_spw1_apb_slv_prdata_o24, fabric_spw1_apb_slv_prdata_o25, fabric_spw1_apb_slv_prdata_o26, fabric_spw1_apb_slv_prdata_o27
+, fabric_spw1_apb_slv_prdata_o28, fabric_spw1_apb_slv_prdata_o29, fabric_spw1_apb_slv_prdata_o30, fabric_spw1_apb_slv_prdata_o31, fabric_spw1_apb_slv_pready_o, fabric_spw1_apb_slv_pslverr_o);
+    input fabric_adc0_arst_b_tmr_i1;
+    input fabric_adc0_arst_b_tmr_i2;
+    input fabric_adc0_arst_b_tmr_i3;
+    output fabric_adc0_cal_done_o;
+    output fabric_adc0_cal_n_overflow_o;
+    output fabric_adc0_cal_n_underflow_o;
+    output fabric_adc0_cal_p_overflow_o;
+    output fabric_adc0_cal_p_underflow_o;
+    input fabric_adc0_cal_start_i;
+    input fabric_adc0_clk_i;
+    input fabric_adc0_dbg_addr_i1;
+    input fabric_adc0_dbg_addr_i2;
+    input fabric_adc0_dbg_addr_i3;
+    input fabric_adc0_dbg_addr_i4;
+    output fabric_adc0_dbg_data_o1;
+    output fabric_adc0_dbg_data_o10;
+    output fabric_adc0_dbg_data_o11;
+    output fabric_adc0_dbg_data_o12;
+    output fabric_adc0_dbg_data_o13;
+    output fabric_adc0_dbg_data_o14;
+    output fabric_adc0_dbg_data_o15;
+    output fabric_adc0_dbg_data_o16;
+    output fabric_adc0_dbg_data_o17;
+    output fabric_adc0_dbg_data_o18;
+    output fabric_adc0_dbg_data_o19;
+    output fabric_adc0_dbg_data_o2;
+    output fabric_adc0_dbg_data_o20;
+    output fabric_adc0_dbg_data_o21;
+    output fabric_adc0_dbg_data_o22;
+    output fabric_adc0_dbg_data_o23;
+    output fabric_adc0_dbg_data_o24;
+    output fabric_adc0_dbg_data_o25;
+    output fabric_adc0_dbg_data_o26;
+    output fabric_adc0_dbg_data_o27;
+    output fabric_adc0_dbg_data_o28;
+    output fabric_adc0_dbg_data_o29;
+    output fabric_adc0_dbg_data_o3;
+    output fabric_adc0_dbg_data_o30;
+    output fabric_adc0_dbg_data_o31;
+    output fabric_adc0_dbg_data_o32;
+    output fabric_adc0_dbg_data_o4;
+    output fabric_adc0_dbg_data_o5;
+    output fabric_adc0_dbg_data_o6;
+    output fabric_adc0_dbg_data_o7;
+    output fabric_adc0_dbg_data_o8;
+    output fabric_adc0_dbg_data_o9;
+    input fabric_adc0_dft_scan_en_i;
+    input fabric_adc0_dft_si_i1;
+    input fabric_adc0_dft_si_i10;
+    input fabric_adc0_dft_si_i11;
+    input fabric_adc0_dft_si_i12;
+    input fabric_adc0_dft_si_i2;
+    input fabric_adc0_dft_si_i3;
+    input fabric_adc0_dft_si_i4;
+    input fabric_adc0_dft_si_i5;
+    input fabric_adc0_dft_si_i6;
+    input fabric_adc0_dft_si_i7;
+    input fabric_adc0_dft_si_i8;
+    input fabric_adc0_dft_si_i9;
+    input fabric_adc0_dft_test_mode_i1;
+    input fabric_adc0_dft_test_mode_i2;
+    input fabric_adc0_pwr_down_b_tmr_i1;
+    input fabric_adc0_pwr_down_b_tmr_i2;
+    input fabric_adc0_pwr_down_b_tmr_i3;
+    input fabric_adc0_spare_i1;
+    input fabric_adc0_spare_i10;
+    input fabric_adc0_spare_i11;
+    input fabric_adc0_spare_i12;
+    input fabric_adc0_spare_i13;
+    input fabric_adc0_spare_i14;
+    input fabric_adc0_spare_i15;
+    input fabric_adc0_spare_i16;
+    input fabric_adc0_spare_i2;
+    input fabric_adc0_spare_i3;
+    input fabric_adc0_spare_i4;
+    input fabric_adc0_spare_i5;
+    input fabric_adc0_spare_i6;
+    input fabric_adc0_spare_i7;
+    input fabric_adc0_spare_i8;
+    input fabric_adc0_spare_i9;
+    input fabric_adc0_usr_arst_b_tmr_i1;
+    input fabric_adc0_usr_arst_b_tmr_i2;
+    input fabric_adc0_usr_arst_b_tmr_i3;
+    input fabric_adc0_usr_channel_i1;
+    input fabric_adc0_usr_channel_i2;
+    input fabric_adc0_usr_channel_i3;
+    input fabric_adc0_usr_cke_i;
+    output fabric_adc0_usr_conv_done_o;
+    input fabric_adc0_usr_conv_start_i;
+    input fabric_adc0_usr_sample_lsb_i1;
+    input fabric_adc0_usr_sample_lsb_i2;
+    input fabric_adc0_usr_sample_lsb_i3;
+    input fabric_adc0_usr_sample_lsb_i4;
+    output fabric_adc0_usr_sample_o1;
+    output fabric_adc0_usr_sample_o10;
+    output fabric_adc0_usr_sample_o11;
+    output fabric_adc0_usr_sample_o12;
+    output fabric_adc0_usr_sample_o2;
+    output fabric_adc0_usr_sample_o3;
+    output fabric_adc0_usr_sample_o4;
+    output fabric_adc0_usr_sample_o5;
+    output fabric_adc0_usr_sample_o6;
+    output fabric_adc0_usr_sample_o7;
+    output fabric_adc0_usr_sample_o8;
+    output fabric_adc0_usr_sample_o9;
+    input fabric_adc1_arst_b_tmr_i1;
+    input fabric_adc1_arst_b_tmr_i2;
+    input fabric_adc1_arst_b_tmr_i3;
+    output fabric_adc1_cal_done_o;
+    output fabric_adc1_cal_n_overflow_o;
+    output fabric_adc1_cal_n_underflow_o;
+    output fabric_adc1_cal_p_overflow_o;
+    output fabric_adc1_cal_p_underflow_o;
+    input fabric_adc1_cal_start_i;
+    input fabric_adc1_clk_i;
+    input fabric_adc1_dbg_addr_i1;
+    input fabric_adc1_dbg_addr_i2;
+    input fabric_adc1_dbg_addr_i3;
+    input fabric_adc1_dbg_addr_i4;
+    output fabric_adc1_dbg_data_o1;
+    output fabric_adc1_dbg_data_o10;
+    output fabric_adc1_dbg_data_o11;
+    output fabric_adc1_dbg_data_o12;
+    output fabric_adc1_dbg_data_o13;
+    output fabric_adc1_dbg_data_o14;
+    output fabric_adc1_dbg_data_o15;
+    output fabric_adc1_dbg_data_o16;
+    output fabric_adc1_dbg_data_o17;
+    output fabric_adc1_dbg_data_o18;
+    output fabric_adc1_dbg_data_o19;
+    output fabric_adc1_dbg_data_o2;
+    output fabric_adc1_dbg_data_o20;
+    output fabric_adc1_dbg_data_o21;
+    output fabric_adc1_dbg_data_o22;
+    output fabric_adc1_dbg_data_o23;
+    output fabric_adc1_dbg_data_o24;
+    output fabric_adc1_dbg_data_o25;
+    output fabric_adc1_dbg_data_o26;
+    output fabric_adc1_dbg_data_o27;
+    output fabric_adc1_dbg_data_o28;
+    output fabric_adc1_dbg_data_o29;
+    output fabric_adc1_dbg_data_o3;
+    output fabric_adc1_dbg_data_o30;
+    output fabric_adc1_dbg_data_o31;
+    output fabric_adc1_dbg_data_o32;
+    output fabric_adc1_dbg_data_o4;
+    output fabric_adc1_dbg_data_o5;
+    output fabric_adc1_dbg_data_o6;
+    output fabric_adc1_dbg_data_o7;
+    output fabric_adc1_dbg_data_o8;
+    output fabric_adc1_dbg_data_o9;
+    input fabric_adc1_dft_scan_en_i;
+    input fabric_adc1_dft_si_i1;
+    input fabric_adc1_dft_si_i10;
+    input fabric_adc1_dft_si_i11;
+    input fabric_adc1_dft_si_i12;
+    input fabric_adc1_dft_si_i2;
+    input fabric_adc1_dft_si_i3;
+    input fabric_adc1_dft_si_i4;
+    input fabric_adc1_dft_si_i5;
+    input fabric_adc1_dft_si_i6;
+    input fabric_adc1_dft_si_i7;
+    input fabric_adc1_dft_si_i8;
+    input fabric_adc1_dft_si_i9;
+    input fabric_adc1_dft_test_mode_i1;
+    input fabric_adc1_dft_test_mode_i2;
+    input fabric_adc1_pwr_down_b_tmr_i1;
+    input fabric_adc1_pwr_down_b_tmr_i2;
+    input fabric_adc1_pwr_down_b_tmr_i3;
+    input fabric_adc1_spare_i1;
+    input fabric_adc1_spare_i10;
+    input fabric_adc1_spare_i11;
+    input fabric_adc1_spare_i12;
+    input fabric_adc1_spare_i13;
+    input fabric_adc1_spare_i14;
+    input fabric_adc1_spare_i15;
+    input fabric_adc1_spare_i16;
+    input fabric_adc1_spare_i2;
+    input fabric_adc1_spare_i3;
+    input fabric_adc1_spare_i4;
+    input fabric_adc1_spare_i5;
+    input fabric_adc1_spare_i6;
+    input fabric_adc1_spare_i7;
+    input fabric_adc1_spare_i8;
+    input fabric_adc1_spare_i9;
+    input fabric_adc1_usr_arst_b_tmr_i1;
+    input fabric_adc1_usr_arst_b_tmr_i2;
+    input fabric_adc1_usr_arst_b_tmr_i3;
+    input fabric_adc1_usr_channel_i1;
+    input fabric_adc1_usr_channel_i2;
+    input fabric_adc1_usr_channel_i3;
+    input fabric_adc1_usr_cke_i;
+    output fabric_adc1_usr_conv_done_o;
+    input fabric_adc1_usr_conv_start_i;
+    input fabric_adc1_usr_sample_lsb_i1;
+    input fabric_adc1_usr_sample_lsb_i2;
+    input fabric_adc1_usr_sample_lsb_i3;
+    input fabric_adc1_usr_sample_lsb_i4;
+    output fabric_adc1_usr_sample_o1;
+    output fabric_adc1_usr_sample_o10;
+    output fabric_adc1_usr_sample_o11;
+    output fabric_adc1_usr_sample_o12;
+    output fabric_adc1_usr_sample_o2;
+    output fabric_adc1_usr_sample_o3;
+    output fabric_adc1_usr_sample_o4;
+    output fabric_adc1_usr_sample_o5;
+    output fabric_adc1_usr_sample_o6;
+    output fabric_adc1_usr_sample_o7;
+    output fabric_adc1_usr_sample_o8;
+    output fabric_adc1_usr_sample_o9;
+    input fabric_adc2_arst_b_tmr_i1;
+    input fabric_adc2_arst_b_tmr_i2;
+    input fabric_adc2_arst_b_tmr_i3;
+    output fabric_adc2_cal_done_o;
+    output fabric_adc2_cal_n_overflow_o;
+    output fabric_adc2_cal_n_underflow_o;
+    output fabric_adc2_cal_p_overflow_o;
+    output fabric_adc2_cal_p_underflow_o;
+    input fabric_adc2_cal_start_i;
+    input fabric_adc2_clk_i;
+    input fabric_adc2_dbg_addr_i1;
+    input fabric_adc2_dbg_addr_i2;
+    input fabric_adc2_dbg_addr_i3;
+    input fabric_adc2_dbg_addr_i4;
+    output fabric_adc2_dbg_data_o1;
+    output fabric_adc2_dbg_data_o10;
+    output fabric_adc2_dbg_data_o11;
+    output fabric_adc2_dbg_data_o12;
+    output fabric_adc2_dbg_data_o13;
+    output fabric_adc2_dbg_data_o14;
+    output fabric_adc2_dbg_data_o15;
+    output fabric_adc2_dbg_data_o16;
+    output fabric_adc2_dbg_data_o17;
+    output fabric_adc2_dbg_data_o18;
+    output fabric_adc2_dbg_data_o19;
+    output fabric_adc2_dbg_data_o2;
+    output fabric_adc2_dbg_data_o20;
+    output fabric_adc2_dbg_data_o21;
+    output fabric_adc2_dbg_data_o22;
+    output fabric_adc2_dbg_data_o23;
+    output fabric_adc2_dbg_data_o24;
+    output fabric_adc2_dbg_data_o25;
+    output fabric_adc2_dbg_data_o26;
+    output fabric_adc2_dbg_data_o27;
+    output fabric_adc2_dbg_data_o28;
+    output fabric_adc2_dbg_data_o29;
+    output fabric_adc2_dbg_data_o3;
+    output fabric_adc2_dbg_data_o30;
+    output fabric_adc2_dbg_data_o31;
+    output fabric_adc2_dbg_data_o32;
+    output fabric_adc2_dbg_data_o4;
+    output fabric_adc2_dbg_data_o5;
+    output fabric_adc2_dbg_data_o6;
+    output fabric_adc2_dbg_data_o7;
+    output fabric_adc2_dbg_data_o8;
+    output fabric_adc2_dbg_data_o9;
+    input fabric_adc2_dft_scan_en_i;
+    input fabric_adc2_dft_si_i1;
+    input fabric_adc2_dft_si_i10;
+    input fabric_adc2_dft_si_i11;
+    input fabric_adc2_dft_si_i12;
+    input fabric_adc2_dft_si_i2;
+    input fabric_adc2_dft_si_i3;
+    input fabric_adc2_dft_si_i4;
+    input fabric_adc2_dft_si_i5;
+    input fabric_adc2_dft_si_i6;
+    input fabric_adc2_dft_si_i7;
+    input fabric_adc2_dft_si_i8;
+    input fabric_adc2_dft_si_i9;
+    input fabric_adc2_dft_test_mode_i1;
+    input fabric_adc2_dft_test_mode_i2;
+    input fabric_adc2_pwr_down_b_tmr_i1;
+    input fabric_adc2_pwr_down_b_tmr_i2;
+    input fabric_adc2_pwr_down_b_tmr_i3;
+    input fabric_adc2_spare_i1;
+    input fabric_adc2_spare_i10;
+    input fabric_adc2_spare_i11;
+    input fabric_adc2_spare_i12;
+    input fabric_adc2_spare_i13;
+    input fabric_adc2_spare_i14;
+    input fabric_adc2_spare_i15;
+    input fabric_adc2_spare_i16;
+    input fabric_adc2_spare_i2;
+    input fabric_adc2_spare_i3;
+    input fabric_adc2_spare_i4;
+    input fabric_adc2_spare_i5;
+    input fabric_adc2_spare_i6;
+    input fabric_adc2_spare_i7;
+    input fabric_adc2_spare_i8;
+    input fabric_adc2_spare_i9;
+    input fabric_adc2_usr_arst_b_tmr_i1;
+    input fabric_adc2_usr_arst_b_tmr_i2;
+    input fabric_adc2_usr_arst_b_tmr_i3;
+    input fabric_adc2_usr_channel_i1;
+    input fabric_adc2_usr_channel_i2;
+    input fabric_adc2_usr_channel_i3;
+    input fabric_adc2_usr_cke_i;
+    output fabric_adc2_usr_conv_done_o;
+    input fabric_adc2_usr_conv_start_i;
+    input fabric_adc2_usr_sample_lsb_i1;
+    input fabric_adc2_usr_sample_lsb_i2;
+    input fabric_adc2_usr_sample_lsb_i3;
+    input fabric_adc2_usr_sample_lsb_i4;
+    output fabric_adc2_usr_sample_o1;
+    output fabric_adc2_usr_sample_o10;
+    output fabric_adc2_usr_sample_o11;
+    output fabric_adc2_usr_sample_o12;
+    output fabric_adc2_usr_sample_o2;
+    output fabric_adc2_usr_sample_o3;
+    output fabric_adc2_usr_sample_o4;
+    output fabric_adc2_usr_sample_o5;
+    output fabric_adc2_usr_sample_o6;
+    output fabric_adc2_usr_sample_o7;
+    output fabric_adc2_usr_sample_o8;
+    output fabric_adc2_usr_sample_o9;
+    input fabric_adc3_arst_b_tmr_i1;
+    input fabric_adc3_arst_b_tmr_i2;
+    input fabric_adc3_arst_b_tmr_i3;
+    output fabric_adc3_cal_done_o;
+    output fabric_adc3_cal_n_overflow_o;
+    output fabric_adc3_cal_n_underflow_o;
+    output fabric_adc3_cal_p_overflow_o;
+    output fabric_adc3_cal_p_underflow_o;
+    input fabric_adc3_cal_start_i;
+    input fabric_adc3_clk_i;
+    input fabric_adc3_dbg_addr_i1;
+    input fabric_adc3_dbg_addr_i2;
+    input fabric_adc3_dbg_addr_i3;
+    input fabric_adc3_dbg_addr_i4;
+    output fabric_adc3_dbg_data_o1;
+    output fabric_adc3_dbg_data_o10;
+    output fabric_adc3_dbg_data_o11;
+    output fabric_adc3_dbg_data_o12;
+    output fabric_adc3_dbg_data_o13;
+    output fabric_adc3_dbg_data_o14;
+    output fabric_adc3_dbg_data_o15;
+    output fabric_adc3_dbg_data_o16;
+    output fabric_adc3_dbg_data_o17;
+    output fabric_adc3_dbg_data_o18;
+    output fabric_adc3_dbg_data_o19;
+    output fabric_adc3_dbg_data_o2;
+    output fabric_adc3_dbg_data_o20;
+    output fabric_adc3_dbg_data_o21;
+    output fabric_adc3_dbg_data_o22;
+    output fabric_adc3_dbg_data_o23;
+    output fabric_adc3_dbg_data_o24;
+    output fabric_adc3_dbg_data_o25;
+    output fabric_adc3_dbg_data_o26;
+    output fabric_adc3_dbg_data_o27;
+    output fabric_adc3_dbg_data_o28;
+    output fabric_adc3_dbg_data_o29;
+    output fabric_adc3_dbg_data_o3;
+    output fabric_adc3_dbg_data_o30;
+    output fabric_adc3_dbg_data_o31;
+    output fabric_adc3_dbg_data_o32;
+    output fabric_adc3_dbg_data_o4;
+    output fabric_adc3_dbg_data_o5;
+    output fabric_adc3_dbg_data_o6;
+    output fabric_adc3_dbg_data_o7;
+    output fabric_adc3_dbg_data_o8;
+    output fabric_adc3_dbg_data_o9;
+    input fabric_adc3_dft_scan_en_i;
+    input fabric_adc3_dft_si_i1;
+    input fabric_adc3_dft_si_i10;
+    input fabric_adc3_dft_si_i11;
+    input fabric_adc3_dft_si_i12;
+    input fabric_adc3_dft_si_i2;
+    input fabric_adc3_dft_si_i3;
+    input fabric_adc3_dft_si_i4;
+    input fabric_adc3_dft_si_i5;
+    input fabric_adc3_dft_si_i6;
+    input fabric_adc3_dft_si_i7;
+    input fabric_adc3_dft_si_i8;
+    input fabric_adc3_dft_si_i9;
+    input fabric_adc3_dft_test_mode_i1;
+    input fabric_adc3_dft_test_mode_i2;
+    input fabric_adc3_pwr_down_b_tmr_i1;
+    input fabric_adc3_pwr_down_b_tmr_i2;
+    input fabric_adc3_pwr_down_b_tmr_i3;
+    input fabric_adc3_spare_i1;
+    input fabric_adc3_spare_i10;
+    input fabric_adc3_spare_i11;
+    input fabric_adc3_spare_i12;
+    input fabric_adc3_spare_i13;
+    input fabric_adc3_spare_i14;
+    input fabric_adc3_spare_i15;
+    input fabric_adc3_spare_i16;
+    input fabric_adc3_spare_i2;
+    input fabric_adc3_spare_i3;
+    input fabric_adc3_spare_i4;
+    input fabric_adc3_spare_i5;
+    input fabric_adc3_spare_i6;
+    input fabric_adc3_spare_i7;
+    input fabric_adc3_spare_i8;
+    input fabric_adc3_spare_i9;
+    input fabric_adc3_usr_arst_b_tmr_i1;
+    input fabric_adc3_usr_arst_b_tmr_i2;
+    input fabric_adc3_usr_arst_b_tmr_i3;
+    input fabric_adc3_usr_channel_i1;
+    input fabric_adc3_usr_channel_i2;
+    input fabric_adc3_usr_channel_i3;
+    input fabric_adc3_usr_cke_i;
+    output fabric_adc3_usr_conv_done_o;
+    input fabric_adc3_usr_conv_start_i;
+    input fabric_adc3_usr_sample_lsb_i1;
+    input fabric_adc3_usr_sample_lsb_i2;
+    input fabric_adc3_usr_sample_lsb_i3;
+    input fabric_adc3_usr_sample_lsb_i4;
+    output fabric_adc3_usr_sample_o1;
+    output fabric_adc3_usr_sample_o10;
+    output fabric_adc3_usr_sample_o11;
+    output fabric_adc3_usr_sample_o12;
+    output fabric_adc3_usr_sample_o2;
+    output fabric_adc3_usr_sample_o3;
+    output fabric_adc3_usr_sample_o4;
+    output fabric_adc3_usr_sample_o5;
+    output fabric_adc3_usr_sample_o6;
+    output fabric_adc3_usr_sample_o7;
+    output fabric_adc3_usr_sample_o8;
+    output fabric_adc3_usr_sample_o9;
+    input fabric_cfg_adc0_clk_cal_div_ratio_i1;
+    input fabric_cfg_adc0_clk_cal_div_ratio_i2;
+    input fabric_cfg_adc0_clk_cal_div_ratio_i3;
+    input fabric_cfg_adc0_clk_cal_div_ratio_i4;
+    input fabric_cfg_adc0_clk_cal_div_ratio_i5;
+    input fabric_cfg_adc0_conv_done_delayed_i;
+    input fabric_cfg_adc0_use_cdc_i;
+    input fabric_cfg_adc1_clk_cal_div_ratio_i1;
+    input fabric_cfg_adc1_clk_cal_div_ratio_i2;
+    input fabric_cfg_adc1_clk_cal_div_ratio_i3;
+    input fabric_cfg_adc1_clk_cal_div_ratio_i4;
+    input fabric_cfg_adc1_clk_cal_div_ratio_i5;
+    input fabric_cfg_adc1_conv_done_delayed_i;
+    input fabric_cfg_adc1_use_cdc_i;
+    input fabric_cfg_adc2_clk_cal_div_ratio_i1;
+    input fabric_cfg_adc2_clk_cal_div_ratio_i2;
+    input fabric_cfg_adc2_clk_cal_div_ratio_i3;
+    input fabric_cfg_adc2_clk_cal_div_ratio_i4;
+    input fabric_cfg_adc2_clk_cal_div_ratio_i5;
+    input fabric_cfg_adc2_conv_done_delayed_i;
+    input fabric_cfg_adc2_use_cdc_i;
+    input fabric_cfg_adc3_clk_cal_div_ratio_i1;
+    input fabric_cfg_adc3_clk_cal_div_ratio_i2;
+    input fabric_cfg_adc3_clk_cal_div_ratio_i3;
+    input fabric_cfg_adc3_clk_cal_div_ratio_i4;
+    input fabric_cfg_adc3_clk_cal_div_ratio_i5;
+    input fabric_cfg_adc3_conv_done_delayed_i;
+    input fabric_cfg_adc3_use_cdc_i;
+    input fabric_cfg_dac0_reg_cm_select_i;
+    input fabric_cfg_dac0_reg_res_i1;
+    input fabric_cfg_dac0_reg_res_i2;
+    input fabric_cfg_dac0_reg_vref_select_i;
+    input fabric_cfg_dac0_sync_i;
+    input fabric_cfg_dac1_reg_cm_select_i;
+    input fabric_cfg_dac1_reg_res_i1;
+    input fabric_cfg_dac1_reg_res_i2;
+    input fabric_cfg_dac1_reg_vref_select_i;
+    input fabric_cfg_dac1_sync_i;
+    input fabric_cfg_dac2_reg_cm_select_i;
+    input fabric_cfg_dac2_reg_res_i1;
+    input fabric_cfg_dac2_reg_res_i2;
+    input fabric_cfg_dac2_reg_vref_select_i;
+    input fabric_cfg_dac2_sync_i;
+    input fabric_cfg_dac3_reg_cm_select_i;
+    input fabric_cfg_dac3_reg_res_i1;
+    input fabric_cfg_dac3_reg_res_i2;
+    input fabric_cfg_dac3_reg_vref_select_i;
+    input fabric_cfg_dac3_sync_i;
+    output fabric_cfg_fabric_user_enable_o;
+    output fabric_cfg_fabric_user_flag_o;
+    output fabric_clk_bsm_o;
+    output fabric_clk_otp_mrepair_o;
+    input fabric_clk_otp_mux_i;
+    output fabric_clk_otp_o;
+    output fabric_clk_user0_o;
+    output fabric_clk_user1_o;
+    input fabric_dac0_clk_en_i;
+    input fabric_dac0_clk_i;
+    input fabric_dac0_comp_en_i;
+    input fabric_dac0_comp_hyst_en_i;
+    input fabric_dac0_comp_in_sel_i1;
+    input fabric_dac0_comp_in_sel_i2;
+    input fabric_dac0_comp_in_sel_i3;
+    input fabric_dac0_comp_in_sel_i4;
+    output fabric_dac0_comp_out_o;
+    input fabric_dac0_comp_ref_sel_i;
+    input fabric_dac0_din_i1;
+    input fabric_dac0_din_i10;
+    input fabric_dac0_din_i11;
+    input fabric_dac0_din_i12;
+    input fabric_dac0_din_i13;
+    input fabric_dac0_din_i2;
+    input fabric_dac0_din_i3;
+    input fabric_dac0_din_i4;
+    input fabric_dac0_din_i5;
+    input fabric_dac0_din_i6;
+    input fabric_dac0_din_i7;
+    input fabric_dac0_din_i8;
+    input fabric_dac0_din_i9;
+    input fabric_dac0_filt_en_i;
+    input fabric_dac0_op_en_i;
+    input fabric_dac0_reg_pwr_down_n_i;
+    input fabric_dac0_rstn_i;
+    input fabric_dac1_clk_en_i;
+    input fabric_dac1_clk_i;
+    input fabric_dac1_comp_en_i;
+    input fabric_dac1_comp_hyst_en_i;
+    input fabric_dac1_comp_in_sel_i1;
+    input fabric_dac1_comp_in_sel_i2;
+    input fabric_dac1_comp_in_sel_i3;
+    input fabric_dac1_comp_in_sel_i4;
+    output fabric_dac1_comp_out_o;
+    input fabric_dac1_comp_ref_sel_i;
+    input fabric_dac1_din_i1;
+    input fabric_dac1_din_i10;
+    input fabric_dac1_din_i11;
+    input fabric_dac1_din_i12;
+    input fabric_dac1_din_i13;
+    input fabric_dac1_din_i2;
+    input fabric_dac1_din_i3;
+    input fabric_dac1_din_i4;
+    input fabric_dac1_din_i5;
+    input fabric_dac1_din_i6;
+    input fabric_dac1_din_i7;
+    input fabric_dac1_din_i8;
+    input fabric_dac1_din_i9;
+    input fabric_dac1_filt_en_i;
+    input fabric_dac1_op_en_i;
+    input fabric_dac1_reg_pwr_down_n_i;
+    input fabric_dac1_rstn_i;
+    input fabric_dac2_clk_en_i;
+    input fabric_dac2_clk_i;
+    input fabric_dac2_comp_en_i;
+    input fabric_dac2_comp_hyst_en_i;
+    input fabric_dac2_comp_in_sel_i1;
+    input fabric_dac2_comp_in_sel_i10;
+    input fabric_dac2_comp_in_sel_i11;
+    input fabric_dac2_comp_in_sel_i12;
+    input fabric_dac2_comp_in_sel_i13;
+    input fabric_dac2_comp_in_sel_i2;
+    input fabric_dac2_comp_in_sel_i3;
+    input fabric_dac2_comp_in_sel_i4;
+    input fabric_dac2_comp_in_sel_i5;
+    input fabric_dac2_comp_in_sel_i6;
+    input fabric_dac2_comp_in_sel_i7;
+    input fabric_dac2_comp_in_sel_i8;
+    input fabric_dac2_comp_in_sel_i9;
+    output fabric_dac2_comp_out_o;
+    input fabric_dac2_comp_ref_sel_i;
+    input fabric_dac2_din_i1;
+    input fabric_dac2_din_i10;
+    input fabric_dac2_din_i11;
+    input fabric_dac2_din_i12;
+    input fabric_dac2_din_i13;
+    input fabric_dac2_din_i2;
+    input fabric_dac2_din_i3;
+    input fabric_dac2_din_i4;
+    input fabric_dac2_din_i5;
+    input fabric_dac2_din_i6;
+    input fabric_dac2_din_i7;
+    input fabric_dac2_din_i8;
+    input fabric_dac2_din_i9;
+    input fabric_dac2_filt_en_i;
+    input fabric_dac2_op_en_i;
+    input fabric_dac2_reg_pwr_down_n_i;
+    input fabric_dac2_rstn_i;
+    input fabric_dac3_clk_en_i;
+    input fabric_dac3_clk_i;
+    input fabric_dac3_comp_en_i;
+    input fabric_dac3_comp_hyst_en_i;
+    input fabric_dac3_comp_in_sel_i1;
+    input fabric_dac3_comp_in_sel_i2;
+    input fabric_dac3_comp_in_sel_i3;
+    input fabric_dac3_comp_in_sel_i4;
+    output fabric_dac3_comp_out_o;
+    input fabric_dac3_comp_ref_sel_i;
+    input fabric_dac3_din_i1;
+    input fabric_dac3_din_i10;
+    input fabric_dac3_din_i11;
+    input fabric_dac3_din_i12;
+    input fabric_dac3_din_i13;
+    input fabric_dac3_din_i2;
+    input fabric_dac3_din_i3;
+    input fabric_dac3_din_i4;
+    input fabric_dac3_din_i5;
+    input fabric_dac3_din_i6;
+    input fabric_dac3_din_i7;
+    input fabric_dac3_din_i8;
+    input fabric_dac3_din_i9;
+    input fabric_dac3_filt_en_i;
+    input fabric_dac3_op_en_i;
+    input fabric_dac3_reg_pwr_down_n_i;
+    input fabric_dac3_rstn_i;
+    output fabric_debug_access_reg_data_ready_o;
+    output fabric_debug_bsec_core_status_o1;
+    output fabric_debug_bsec_core_status_o10;
+    output fabric_debug_bsec_core_status_o11;
+    output fabric_debug_bsec_core_status_o12;
+    output fabric_debug_bsec_core_status_o13;
+    output fabric_debug_bsec_core_status_o14;
+    output fabric_debug_bsec_core_status_o15;
+    output fabric_debug_bsec_core_status_o16;
+    output fabric_debug_bsec_core_status_o17;
+    output fabric_debug_bsec_core_status_o18;
+    output fabric_debug_bsec_core_status_o19;
+    output fabric_debug_bsec_core_status_o2;
+    output fabric_debug_bsec_core_status_o20;
+    output fabric_debug_bsec_core_status_o21;
+    output fabric_debug_bsec_core_status_o22;
+    output fabric_debug_bsec_core_status_o23;
+    output fabric_debug_bsec_core_status_o24;
+    output fabric_debug_bsec_core_status_o25;
+    output fabric_debug_bsec_core_status_o26;
+    output fabric_debug_bsec_core_status_o27;
+    output fabric_debug_bsec_core_status_o28;
+    output fabric_debug_bsec_core_status_o29;
+    output fabric_debug_bsec_core_status_o3;
+    output fabric_debug_bsec_core_status_o30;
+    output fabric_debug_bsec_core_status_o31;
+    output fabric_debug_bsec_core_status_o32;
+    output fabric_debug_bsec_core_status_o4;
+    output fabric_debug_bsec_core_status_o5;
+    output fabric_debug_bsec_core_status_o6;
+    output fabric_debug_bsec_core_status_o7;
+    output fabric_debug_bsec_core_status_o8;
+    output fabric_debug_bsec_core_status_o9;
+    output fabric_debug_cpt_retry_o1;
+    output fabric_debug_cpt_retry_o2;
+    output fabric_debug_cpt_retry_o3;
+    output fabric_debug_cpt_retry_o4;
+    output fabric_debug_direct_permission_read_o1;
+    output fabric_debug_direct_permission_read_o2;
+    output fabric_debug_direct_permission_read_o3;
+    output fabric_debug_direct_permission_read_o4;
+    output fabric_debug_direct_permission_write_o1;
+    output fabric_debug_direct_permission_write_o2;
+    output fabric_debug_direct_permission_write_o3;
+    output fabric_debug_direct_permission_write_o4;
+    output fabric_debug_error_o;
+    output fabric_debug_frame_permission_frame_o1;
+    output fabric_debug_frame_permission_frame_o2;
+    output fabric_debug_frame_permission_frame_o3;
+    output fabric_debug_frame_permission_frame_o4;
+    output fabric_debug_frame_use_encryption_o;
+    output fabric_debug_fsm_state_o1;
+    output fabric_debug_fsm_state_o2;
+    output fabric_debug_fsm_state_o3;
+    output fabric_debug_key_correct_o;
+    output fabric_debug_lifecycle_o1;
+    output fabric_debug_lifecycle_o2;
+    output fabric_debug_lifecycle_o3;
+    output fabric_debug_lifecycle_o4;
+    output fabric_debug_lock_reg_o;
+    output fabric_debug_otp_manager_read_done_o;
+    output fabric_debug_otp_manager_read_otp_o;
+    output fabric_debug_otp_reload_err_o;
+    output fabric_debug_otpapb_state_o1;
+    output fabric_debug_otpapb_state_o2;
+    output fabric_debug_otpapb_state_o3;
+    output fabric_debug_otpboot_curr_addr_o1;
+    output fabric_debug_otpboot_curr_addr_o2;
+    output fabric_debug_otpboot_curr_addr_o3;
+    output fabric_debug_otpboot_curr_addr_o4;
+    output fabric_debug_otpboot_curr_addr_o5;
+    output fabric_debug_otpboot_curr_addr_o6;
+    output fabric_debug_otpboot_curr_addr_o7;
+    output fabric_debug_otpboot_curr_addr_o8;
+    output fabric_debug_otpboot_state_o1;
+    output fabric_debug_otpboot_state_o2;
+    output fabric_debug_otpboot_state_o3;
+    output fabric_debug_otpmgmt_state_o1;
+    output fabric_debug_otpmgmt_state_o2;
+    output fabric_debug_otpmgmt_state_o3;
+    output fabric_debug_rst_soft_o;
+    output fabric_debug_security_boot_done_o;
+    output fabric_debug_security_error_read_o;
+    input fabric_direct0_cfg_bank_i1;
+    input fabric_direct0_cfg_bank_i2;
+    input fabric_direct0_cfg_bank_i3;
+    input fabric_direct0_cfg_bank_i4;
+    input fabric_direct0_cfg_pad_i1;
+    input fabric_direct0_cfg_pad_i10;
+    input fabric_direct0_cfg_pad_i100;
+    input fabric_direct0_cfg_pad_i101;
+    input fabric_direct0_cfg_pad_i102;
+    input fabric_direct0_cfg_pad_i103;
+    input fabric_direct0_cfg_pad_i104;
+    input fabric_direct0_cfg_pad_i105;
+    input fabric_direct0_cfg_pad_i106;
+    input fabric_direct0_cfg_pad_i107;
+    input fabric_direct0_cfg_pad_i108;
+    input fabric_direct0_cfg_pad_i109;
+    input fabric_direct0_cfg_pad_i11;
+    input fabric_direct0_cfg_pad_i110;
+    input fabric_direct0_cfg_pad_i111;
+    input fabric_direct0_cfg_pad_i112;
+    input fabric_direct0_cfg_pad_i113;
+    input fabric_direct0_cfg_pad_i114;
+    input fabric_direct0_cfg_pad_i115;
+    input fabric_direct0_cfg_pad_i116;
+    input fabric_direct0_cfg_pad_i117;
+    input fabric_direct0_cfg_pad_i118;
+    input fabric_direct0_cfg_pad_i119;
+    input fabric_direct0_cfg_pad_i12;
+    input fabric_direct0_cfg_pad_i120;
+    input fabric_direct0_cfg_pad_i121;
+    input fabric_direct0_cfg_pad_i122;
+    input fabric_direct0_cfg_pad_i123;
+    input fabric_direct0_cfg_pad_i124;
+    input fabric_direct0_cfg_pad_i125;
+    input fabric_direct0_cfg_pad_i126;
+    input fabric_direct0_cfg_pad_i127;
+    input fabric_direct0_cfg_pad_i128;
+    input fabric_direct0_cfg_pad_i129;
+    input fabric_direct0_cfg_pad_i13;
+    input fabric_direct0_cfg_pad_i130;
+    input fabric_direct0_cfg_pad_i131;
+    input fabric_direct0_cfg_pad_i132;
+    input fabric_direct0_cfg_pad_i133;
+    input fabric_direct0_cfg_pad_i134;
+    input fabric_direct0_cfg_pad_i135;
+    input fabric_direct0_cfg_pad_i136;
+    input fabric_direct0_cfg_pad_i137;
+    input fabric_direct0_cfg_pad_i138;
+    input fabric_direct0_cfg_pad_i139;
+    input fabric_direct0_cfg_pad_i14;
+    input fabric_direct0_cfg_pad_i140;
+    input fabric_direct0_cfg_pad_i141;
+    input fabric_direct0_cfg_pad_i142;
+    input fabric_direct0_cfg_pad_i143;
+    input fabric_direct0_cfg_pad_i144;
+    input fabric_direct0_cfg_pad_i145;
+    input fabric_direct0_cfg_pad_i146;
+    input fabric_direct0_cfg_pad_i147;
+    input fabric_direct0_cfg_pad_i148;
+    input fabric_direct0_cfg_pad_i149;
+    input fabric_direct0_cfg_pad_i15;
+    input fabric_direct0_cfg_pad_i150;
+    input fabric_direct0_cfg_pad_i151;
+    input fabric_direct0_cfg_pad_i152;
+    input fabric_direct0_cfg_pad_i153;
+    input fabric_direct0_cfg_pad_i154;
+    input fabric_direct0_cfg_pad_i155;
+    input fabric_direct0_cfg_pad_i156;
+    input fabric_direct0_cfg_pad_i157;
+    input fabric_direct0_cfg_pad_i158;
+    input fabric_direct0_cfg_pad_i159;
+    input fabric_direct0_cfg_pad_i16;
+    input fabric_direct0_cfg_pad_i160;
+    input fabric_direct0_cfg_pad_i161;
+    input fabric_direct0_cfg_pad_i162;
+    input fabric_direct0_cfg_pad_i163;
+    input fabric_direct0_cfg_pad_i164;
+    input fabric_direct0_cfg_pad_i165;
+    input fabric_direct0_cfg_pad_i166;
+    input fabric_direct0_cfg_pad_i167;
+    input fabric_direct0_cfg_pad_i168;
+    input fabric_direct0_cfg_pad_i169;
+    input fabric_direct0_cfg_pad_i17;
+    input fabric_direct0_cfg_pad_i170;
+    input fabric_direct0_cfg_pad_i171;
+    input fabric_direct0_cfg_pad_i172;
+    input fabric_direct0_cfg_pad_i173;
+    input fabric_direct0_cfg_pad_i174;
+    input fabric_direct0_cfg_pad_i175;
+    input fabric_direct0_cfg_pad_i176;
+    input fabric_direct0_cfg_pad_i177;
+    input fabric_direct0_cfg_pad_i178;
+    input fabric_direct0_cfg_pad_i179;
+    input fabric_direct0_cfg_pad_i18;
+    input fabric_direct0_cfg_pad_i180;
+    input fabric_direct0_cfg_pad_i181;
+    input fabric_direct0_cfg_pad_i182;
+    input fabric_direct0_cfg_pad_i183;
+    input fabric_direct0_cfg_pad_i184;
+    input fabric_direct0_cfg_pad_i185;
+    input fabric_direct0_cfg_pad_i186;
+    input fabric_direct0_cfg_pad_i187;
+    input fabric_direct0_cfg_pad_i188;
+    input fabric_direct0_cfg_pad_i189;
+    input fabric_direct0_cfg_pad_i19;
+    input fabric_direct0_cfg_pad_i190;
+    input fabric_direct0_cfg_pad_i191;
+    input fabric_direct0_cfg_pad_i192;
+    input fabric_direct0_cfg_pad_i193;
+    input fabric_direct0_cfg_pad_i194;
+    input fabric_direct0_cfg_pad_i195;
+    input fabric_direct0_cfg_pad_i196;
+    input fabric_direct0_cfg_pad_i197;
+    input fabric_direct0_cfg_pad_i198;
+    input fabric_direct0_cfg_pad_i199;
+    input fabric_direct0_cfg_pad_i2;
+    input fabric_direct0_cfg_pad_i20;
+    input fabric_direct0_cfg_pad_i200;
+    input fabric_direct0_cfg_pad_i201;
+    input fabric_direct0_cfg_pad_i202;
+    input fabric_direct0_cfg_pad_i203;
+    input fabric_direct0_cfg_pad_i204;
+    input fabric_direct0_cfg_pad_i205;
+    input fabric_direct0_cfg_pad_i206;
+    input fabric_direct0_cfg_pad_i207;
+    input fabric_direct0_cfg_pad_i208;
+    input fabric_direct0_cfg_pad_i209;
+    input fabric_direct0_cfg_pad_i21;
+    input fabric_direct0_cfg_pad_i210;
+    input fabric_direct0_cfg_pad_i211;
+    input fabric_direct0_cfg_pad_i212;
+    input fabric_direct0_cfg_pad_i213;
+    input fabric_direct0_cfg_pad_i214;
+    input fabric_direct0_cfg_pad_i215;
+    input fabric_direct0_cfg_pad_i216;
+    input fabric_direct0_cfg_pad_i217;
+    input fabric_direct0_cfg_pad_i218;
+    input fabric_direct0_cfg_pad_i219;
+    input fabric_direct0_cfg_pad_i22;
+    input fabric_direct0_cfg_pad_i220;
+    input fabric_direct0_cfg_pad_i221;
+    input fabric_direct0_cfg_pad_i222;
+    input fabric_direct0_cfg_pad_i223;
+    input fabric_direct0_cfg_pad_i224;
+    input fabric_direct0_cfg_pad_i225;
+    input fabric_direct0_cfg_pad_i226;
+    input fabric_direct0_cfg_pad_i227;
+    input fabric_direct0_cfg_pad_i228;
+    input fabric_direct0_cfg_pad_i229;
+    input fabric_direct0_cfg_pad_i23;
+    input fabric_direct0_cfg_pad_i230;
+    input fabric_direct0_cfg_pad_i231;
+    input fabric_direct0_cfg_pad_i232;
+    input fabric_direct0_cfg_pad_i233;
+    input fabric_direct0_cfg_pad_i234;
+    input fabric_direct0_cfg_pad_i235;
+    input fabric_direct0_cfg_pad_i236;
+    input fabric_direct0_cfg_pad_i237;
+    input fabric_direct0_cfg_pad_i238;
+    input fabric_direct0_cfg_pad_i239;
+    input fabric_direct0_cfg_pad_i24;
+    input fabric_direct0_cfg_pad_i240;
+    input fabric_direct0_cfg_pad_i241;
+    input fabric_direct0_cfg_pad_i242;
+    input fabric_direct0_cfg_pad_i243;
+    input fabric_direct0_cfg_pad_i244;
+    input fabric_direct0_cfg_pad_i245;
+    input fabric_direct0_cfg_pad_i246;
+    input fabric_direct0_cfg_pad_i247;
+    input fabric_direct0_cfg_pad_i248;
+    input fabric_direct0_cfg_pad_i249;
+    input fabric_direct0_cfg_pad_i25;
+    input fabric_direct0_cfg_pad_i250;
+    input fabric_direct0_cfg_pad_i251;
+    input fabric_direct0_cfg_pad_i252;
+    input fabric_direct0_cfg_pad_i253;
+    input fabric_direct0_cfg_pad_i254;
+    input fabric_direct0_cfg_pad_i255;
+    input fabric_direct0_cfg_pad_i256;
+    input fabric_direct0_cfg_pad_i257;
+    input fabric_direct0_cfg_pad_i258;
+    input fabric_direct0_cfg_pad_i259;
+    input fabric_direct0_cfg_pad_i26;
+    input fabric_direct0_cfg_pad_i260;
+    input fabric_direct0_cfg_pad_i261;
+    input fabric_direct0_cfg_pad_i262;
+    input fabric_direct0_cfg_pad_i263;
+    input fabric_direct0_cfg_pad_i264;
+    input fabric_direct0_cfg_pad_i265;
+    input fabric_direct0_cfg_pad_i266;
+    input fabric_direct0_cfg_pad_i267;
+    input fabric_direct0_cfg_pad_i268;
+    input fabric_direct0_cfg_pad_i269;
+    input fabric_direct0_cfg_pad_i27;
+    input fabric_direct0_cfg_pad_i270;
+    input fabric_direct0_cfg_pad_i271;
+    input fabric_direct0_cfg_pad_i272;
+    input fabric_direct0_cfg_pad_i273;
+    input fabric_direct0_cfg_pad_i274;
+    input fabric_direct0_cfg_pad_i275;
+    input fabric_direct0_cfg_pad_i276;
+    input fabric_direct0_cfg_pad_i277;
+    input fabric_direct0_cfg_pad_i278;
+    input fabric_direct0_cfg_pad_i279;
+    input fabric_direct0_cfg_pad_i28;
+    input fabric_direct0_cfg_pad_i280;
+    input fabric_direct0_cfg_pad_i281;
+    input fabric_direct0_cfg_pad_i282;
+    input fabric_direct0_cfg_pad_i283;
+    input fabric_direct0_cfg_pad_i284;
+    input fabric_direct0_cfg_pad_i285;
+    input fabric_direct0_cfg_pad_i286;
+    input fabric_direct0_cfg_pad_i287;
+    input fabric_direct0_cfg_pad_i288;
+    input fabric_direct0_cfg_pad_i289;
+    input fabric_direct0_cfg_pad_i29;
+    input fabric_direct0_cfg_pad_i290;
+    input fabric_direct0_cfg_pad_i291;
+    input fabric_direct0_cfg_pad_i292;
+    input fabric_direct0_cfg_pad_i293;
+    input fabric_direct0_cfg_pad_i294;
+    input fabric_direct0_cfg_pad_i295;
+    input fabric_direct0_cfg_pad_i296;
+    input fabric_direct0_cfg_pad_i297;
+    input fabric_direct0_cfg_pad_i298;
+    input fabric_direct0_cfg_pad_i299;
+    input fabric_direct0_cfg_pad_i3;
+    input fabric_direct0_cfg_pad_i30;
+    input fabric_direct0_cfg_pad_i300;
+    input fabric_direct0_cfg_pad_i301;
+    input fabric_direct0_cfg_pad_i302;
+    input fabric_direct0_cfg_pad_i303;
+    input fabric_direct0_cfg_pad_i304;
+    input fabric_direct0_cfg_pad_i305;
+    input fabric_direct0_cfg_pad_i306;
+    input fabric_direct0_cfg_pad_i307;
+    input fabric_direct0_cfg_pad_i308;
+    input fabric_direct0_cfg_pad_i309;
+    input fabric_direct0_cfg_pad_i31;
+    input fabric_direct0_cfg_pad_i310;
+    input fabric_direct0_cfg_pad_i311;
+    input fabric_direct0_cfg_pad_i312;
+    input fabric_direct0_cfg_pad_i313;
+    input fabric_direct0_cfg_pad_i314;
+    input fabric_direct0_cfg_pad_i315;
+    input fabric_direct0_cfg_pad_i316;
+    input fabric_direct0_cfg_pad_i317;
+    input fabric_direct0_cfg_pad_i318;
+    input fabric_direct0_cfg_pad_i319;
+    input fabric_direct0_cfg_pad_i32;
+    input fabric_direct0_cfg_pad_i320;
+    input fabric_direct0_cfg_pad_i321;
+    input fabric_direct0_cfg_pad_i322;
+    input fabric_direct0_cfg_pad_i323;
+    input fabric_direct0_cfg_pad_i324;
+    input fabric_direct0_cfg_pad_i325;
+    input fabric_direct0_cfg_pad_i326;
+    input fabric_direct0_cfg_pad_i327;
+    input fabric_direct0_cfg_pad_i328;
+    input fabric_direct0_cfg_pad_i329;
+    input fabric_direct0_cfg_pad_i33;
+    input fabric_direct0_cfg_pad_i330;
+    input fabric_direct0_cfg_pad_i331;
+    input fabric_direct0_cfg_pad_i332;
+    input fabric_direct0_cfg_pad_i333;
+    input fabric_direct0_cfg_pad_i334;
+    input fabric_direct0_cfg_pad_i335;
+    input fabric_direct0_cfg_pad_i336;
+    input fabric_direct0_cfg_pad_i337;
+    input fabric_direct0_cfg_pad_i338;
+    input fabric_direct0_cfg_pad_i339;
+    input fabric_direct0_cfg_pad_i34;
+    input fabric_direct0_cfg_pad_i340;
+    input fabric_direct0_cfg_pad_i341;
+    input fabric_direct0_cfg_pad_i342;
+    input fabric_direct0_cfg_pad_i343;
+    input fabric_direct0_cfg_pad_i344;
+    input fabric_direct0_cfg_pad_i345;
+    input fabric_direct0_cfg_pad_i346;
+    input fabric_direct0_cfg_pad_i347;
+    input fabric_direct0_cfg_pad_i348;
+    input fabric_direct0_cfg_pad_i349;
+    input fabric_direct0_cfg_pad_i35;
+    input fabric_direct0_cfg_pad_i350;
+    input fabric_direct0_cfg_pad_i351;
+    input fabric_direct0_cfg_pad_i352;
+    input fabric_direct0_cfg_pad_i353;
+    input fabric_direct0_cfg_pad_i354;
+    input fabric_direct0_cfg_pad_i355;
+    input fabric_direct0_cfg_pad_i356;
+    input fabric_direct0_cfg_pad_i357;
+    input fabric_direct0_cfg_pad_i358;
+    input fabric_direct0_cfg_pad_i359;
+    input fabric_direct0_cfg_pad_i36;
+    input fabric_direct0_cfg_pad_i360;
+    input fabric_direct0_cfg_pad_i361;
+    input fabric_direct0_cfg_pad_i362;
+    input fabric_direct0_cfg_pad_i363;
+    input fabric_direct0_cfg_pad_i364;
+    input fabric_direct0_cfg_pad_i365;
+    input fabric_direct0_cfg_pad_i366;
+    input fabric_direct0_cfg_pad_i367;
+    input fabric_direct0_cfg_pad_i368;
+    input fabric_direct0_cfg_pad_i369;
+    input fabric_direct0_cfg_pad_i37;
+    input fabric_direct0_cfg_pad_i370;
+    input fabric_direct0_cfg_pad_i371;
+    input fabric_direct0_cfg_pad_i372;
+    input fabric_direct0_cfg_pad_i373;
+    input fabric_direct0_cfg_pad_i374;
+    input fabric_direct0_cfg_pad_i375;
+    input fabric_direct0_cfg_pad_i376;
+    input fabric_direct0_cfg_pad_i377;
+    input fabric_direct0_cfg_pad_i378;
+    input fabric_direct0_cfg_pad_i379;
+    input fabric_direct0_cfg_pad_i38;
+    input fabric_direct0_cfg_pad_i380;
+    input fabric_direct0_cfg_pad_i381;
+    input fabric_direct0_cfg_pad_i382;
+    input fabric_direct0_cfg_pad_i383;
+    input fabric_direct0_cfg_pad_i384;
+    input fabric_direct0_cfg_pad_i385;
+    input fabric_direct0_cfg_pad_i386;
+    input fabric_direct0_cfg_pad_i387;
+    input fabric_direct0_cfg_pad_i388;
+    input fabric_direct0_cfg_pad_i389;
+    input fabric_direct0_cfg_pad_i39;
+    input fabric_direct0_cfg_pad_i390;
+    input fabric_direct0_cfg_pad_i391;
+    input fabric_direct0_cfg_pad_i392;
+    input fabric_direct0_cfg_pad_i393;
+    input fabric_direct0_cfg_pad_i394;
+    input fabric_direct0_cfg_pad_i395;
+    input fabric_direct0_cfg_pad_i396;
+    input fabric_direct0_cfg_pad_i397;
+    input fabric_direct0_cfg_pad_i398;
+    input fabric_direct0_cfg_pad_i399;
+    input fabric_direct0_cfg_pad_i4;
+    input fabric_direct0_cfg_pad_i40;
+    input fabric_direct0_cfg_pad_i400;
+    input fabric_direct0_cfg_pad_i401;
+    input fabric_direct0_cfg_pad_i402;
+    input fabric_direct0_cfg_pad_i403;
+    input fabric_direct0_cfg_pad_i404;
+    input fabric_direct0_cfg_pad_i405;
+    input fabric_direct0_cfg_pad_i406;
+    input fabric_direct0_cfg_pad_i407;
+    input fabric_direct0_cfg_pad_i408;
+    input fabric_direct0_cfg_pad_i409;
+    input fabric_direct0_cfg_pad_i41;
+    input fabric_direct0_cfg_pad_i410;
+    input fabric_direct0_cfg_pad_i411;
+    input fabric_direct0_cfg_pad_i412;
+    input fabric_direct0_cfg_pad_i413;
+    input fabric_direct0_cfg_pad_i414;
+    input fabric_direct0_cfg_pad_i415;
+    input fabric_direct0_cfg_pad_i416;
+    input fabric_direct0_cfg_pad_i417;
+    input fabric_direct0_cfg_pad_i418;
+    input fabric_direct0_cfg_pad_i419;
+    input fabric_direct0_cfg_pad_i42;
+    input fabric_direct0_cfg_pad_i420;
+    input fabric_direct0_cfg_pad_i421;
+    input fabric_direct0_cfg_pad_i422;
+    input fabric_direct0_cfg_pad_i423;
+    input fabric_direct0_cfg_pad_i424;
+    input fabric_direct0_cfg_pad_i425;
+    input fabric_direct0_cfg_pad_i426;
+    input fabric_direct0_cfg_pad_i427;
+    input fabric_direct0_cfg_pad_i428;
+    input fabric_direct0_cfg_pad_i429;
+    input fabric_direct0_cfg_pad_i43;
+    input fabric_direct0_cfg_pad_i430;
+    input fabric_direct0_cfg_pad_i431;
+    input fabric_direct0_cfg_pad_i432;
+    input fabric_direct0_cfg_pad_i433;
+    input fabric_direct0_cfg_pad_i434;
+    input fabric_direct0_cfg_pad_i435;
+    input fabric_direct0_cfg_pad_i436;
+    input fabric_direct0_cfg_pad_i437;
+    input fabric_direct0_cfg_pad_i438;
+    input fabric_direct0_cfg_pad_i439;
+    input fabric_direct0_cfg_pad_i44;
+    input fabric_direct0_cfg_pad_i440;
+    input fabric_direct0_cfg_pad_i441;
+    input fabric_direct0_cfg_pad_i442;
+    input fabric_direct0_cfg_pad_i443;
+    input fabric_direct0_cfg_pad_i444;
+    input fabric_direct0_cfg_pad_i445;
+    input fabric_direct0_cfg_pad_i446;
+    input fabric_direct0_cfg_pad_i447;
+    input fabric_direct0_cfg_pad_i448;
+    input fabric_direct0_cfg_pad_i449;
+    input fabric_direct0_cfg_pad_i45;
+    input fabric_direct0_cfg_pad_i450;
+    input fabric_direct0_cfg_pad_i451;
+    input fabric_direct0_cfg_pad_i452;
+    input fabric_direct0_cfg_pad_i453;
+    input fabric_direct0_cfg_pad_i454;
+    input fabric_direct0_cfg_pad_i455;
+    input fabric_direct0_cfg_pad_i456;
+    input fabric_direct0_cfg_pad_i457;
+    input fabric_direct0_cfg_pad_i458;
+    input fabric_direct0_cfg_pad_i459;
+    input fabric_direct0_cfg_pad_i46;
+    input fabric_direct0_cfg_pad_i460;
+    input fabric_direct0_cfg_pad_i461;
+    input fabric_direct0_cfg_pad_i462;
+    input fabric_direct0_cfg_pad_i463;
+    input fabric_direct0_cfg_pad_i464;
+    input fabric_direct0_cfg_pad_i465;
+    input fabric_direct0_cfg_pad_i466;
+    input fabric_direct0_cfg_pad_i467;
+    input fabric_direct0_cfg_pad_i468;
+    input fabric_direct0_cfg_pad_i469;
+    input fabric_direct0_cfg_pad_i47;
+    input fabric_direct0_cfg_pad_i470;
+    input fabric_direct0_cfg_pad_i471;
+    input fabric_direct0_cfg_pad_i472;
+    input fabric_direct0_cfg_pad_i473;
+    input fabric_direct0_cfg_pad_i474;
+    input fabric_direct0_cfg_pad_i475;
+    input fabric_direct0_cfg_pad_i476;
+    input fabric_direct0_cfg_pad_i477;
+    input fabric_direct0_cfg_pad_i478;
+    input fabric_direct0_cfg_pad_i479;
+    input fabric_direct0_cfg_pad_i48;
+    input fabric_direct0_cfg_pad_i480;
+    input fabric_direct0_cfg_pad_i481;
+    input fabric_direct0_cfg_pad_i482;
+    input fabric_direct0_cfg_pad_i483;
+    input fabric_direct0_cfg_pad_i484;
+    input fabric_direct0_cfg_pad_i485;
+    input fabric_direct0_cfg_pad_i486;
+    input fabric_direct0_cfg_pad_i487;
+    input fabric_direct0_cfg_pad_i488;
+    input fabric_direct0_cfg_pad_i489;
+    input fabric_direct0_cfg_pad_i49;
+    input fabric_direct0_cfg_pad_i490;
+    input fabric_direct0_cfg_pad_i491;
+    input fabric_direct0_cfg_pad_i492;
+    input fabric_direct0_cfg_pad_i493;
+    input fabric_direct0_cfg_pad_i494;
+    input fabric_direct0_cfg_pad_i495;
+    input fabric_direct0_cfg_pad_i496;
+    input fabric_direct0_cfg_pad_i497;
+    input fabric_direct0_cfg_pad_i498;
+    input fabric_direct0_cfg_pad_i499;
+    input fabric_direct0_cfg_pad_i5;
+    input fabric_direct0_cfg_pad_i50;
+    input fabric_direct0_cfg_pad_i500;
+    input fabric_direct0_cfg_pad_i501;
+    input fabric_direct0_cfg_pad_i502;
+    input fabric_direct0_cfg_pad_i503;
+    input fabric_direct0_cfg_pad_i504;
+    input fabric_direct0_cfg_pad_i505;
+    input fabric_direct0_cfg_pad_i506;
+    input fabric_direct0_cfg_pad_i507;
+    input fabric_direct0_cfg_pad_i508;
+    input fabric_direct0_cfg_pad_i509;
+    input fabric_direct0_cfg_pad_i51;
+    input fabric_direct0_cfg_pad_i510;
+    input fabric_direct0_cfg_pad_i511;
+    input fabric_direct0_cfg_pad_i512;
+    input fabric_direct0_cfg_pad_i513;
+    input fabric_direct0_cfg_pad_i514;
+    input fabric_direct0_cfg_pad_i515;
+    input fabric_direct0_cfg_pad_i516;
+    input fabric_direct0_cfg_pad_i517;
+    input fabric_direct0_cfg_pad_i518;
+    input fabric_direct0_cfg_pad_i519;
+    input fabric_direct0_cfg_pad_i52;
+    input fabric_direct0_cfg_pad_i520;
+    input fabric_direct0_cfg_pad_i521;
+    input fabric_direct0_cfg_pad_i522;
+    input fabric_direct0_cfg_pad_i523;
+    input fabric_direct0_cfg_pad_i524;
+    input fabric_direct0_cfg_pad_i525;
+    input fabric_direct0_cfg_pad_i526;
+    input fabric_direct0_cfg_pad_i527;
+    input fabric_direct0_cfg_pad_i528;
+    input fabric_direct0_cfg_pad_i529;
+    input fabric_direct0_cfg_pad_i53;
+    input fabric_direct0_cfg_pad_i530;
+    input fabric_direct0_cfg_pad_i531;
+    input fabric_direct0_cfg_pad_i532;
+    input fabric_direct0_cfg_pad_i533;
+    input fabric_direct0_cfg_pad_i534;
+    input fabric_direct0_cfg_pad_i535;
+    input fabric_direct0_cfg_pad_i536;
+    input fabric_direct0_cfg_pad_i537;
+    input fabric_direct0_cfg_pad_i538;
+    input fabric_direct0_cfg_pad_i539;
+    input fabric_direct0_cfg_pad_i54;
+    input fabric_direct0_cfg_pad_i540;
+    input fabric_direct0_cfg_pad_i541;
+    input fabric_direct0_cfg_pad_i542;
+    input fabric_direct0_cfg_pad_i543;
+    input fabric_direct0_cfg_pad_i544;
+    input fabric_direct0_cfg_pad_i545;
+    input fabric_direct0_cfg_pad_i546;
+    input fabric_direct0_cfg_pad_i547;
+    input fabric_direct0_cfg_pad_i548;
+    input fabric_direct0_cfg_pad_i549;
+    input fabric_direct0_cfg_pad_i55;
+    input fabric_direct0_cfg_pad_i550;
+    input fabric_direct0_cfg_pad_i551;
+    input fabric_direct0_cfg_pad_i552;
+    input fabric_direct0_cfg_pad_i553;
+    input fabric_direct0_cfg_pad_i554;
+    input fabric_direct0_cfg_pad_i555;
+    input fabric_direct0_cfg_pad_i556;
+    input fabric_direct0_cfg_pad_i557;
+    input fabric_direct0_cfg_pad_i558;
+    input fabric_direct0_cfg_pad_i559;
+    input fabric_direct0_cfg_pad_i56;
+    input fabric_direct0_cfg_pad_i560;
+    input fabric_direct0_cfg_pad_i561;
+    input fabric_direct0_cfg_pad_i562;
+    input fabric_direct0_cfg_pad_i563;
+    input fabric_direct0_cfg_pad_i564;
+    input fabric_direct0_cfg_pad_i565;
+    input fabric_direct0_cfg_pad_i566;
+    input fabric_direct0_cfg_pad_i567;
+    input fabric_direct0_cfg_pad_i568;
+    input fabric_direct0_cfg_pad_i569;
+    input fabric_direct0_cfg_pad_i57;
+    input fabric_direct0_cfg_pad_i570;
+    input fabric_direct0_cfg_pad_i571;
+    input fabric_direct0_cfg_pad_i572;
+    input fabric_direct0_cfg_pad_i573;
+    input fabric_direct0_cfg_pad_i574;
+    input fabric_direct0_cfg_pad_i575;
+    input fabric_direct0_cfg_pad_i576;
+    input fabric_direct0_cfg_pad_i577;
+    input fabric_direct0_cfg_pad_i578;
+    input fabric_direct0_cfg_pad_i579;
+    input fabric_direct0_cfg_pad_i58;
+    input fabric_direct0_cfg_pad_i580;
+    input fabric_direct0_cfg_pad_i581;
+    input fabric_direct0_cfg_pad_i582;
+    input fabric_direct0_cfg_pad_i583;
+    input fabric_direct0_cfg_pad_i584;
+    input fabric_direct0_cfg_pad_i585;
+    input fabric_direct0_cfg_pad_i586;
+    input fabric_direct0_cfg_pad_i587;
+    input fabric_direct0_cfg_pad_i588;
+    input fabric_direct0_cfg_pad_i589;
+    input fabric_direct0_cfg_pad_i59;
+    input fabric_direct0_cfg_pad_i590;
+    input fabric_direct0_cfg_pad_i591;
+    input fabric_direct0_cfg_pad_i592;
+    input fabric_direct0_cfg_pad_i593;
+    input fabric_direct0_cfg_pad_i594;
+    input fabric_direct0_cfg_pad_i595;
+    input fabric_direct0_cfg_pad_i596;
+    input fabric_direct0_cfg_pad_i597;
+    input fabric_direct0_cfg_pad_i598;
+    input fabric_direct0_cfg_pad_i599;
+    input fabric_direct0_cfg_pad_i6;
+    input fabric_direct0_cfg_pad_i60;
+    input fabric_direct0_cfg_pad_i600;
+    input fabric_direct0_cfg_pad_i601;
+    input fabric_direct0_cfg_pad_i602;
+    input fabric_direct0_cfg_pad_i603;
+    input fabric_direct0_cfg_pad_i604;
+    input fabric_direct0_cfg_pad_i605;
+    input fabric_direct0_cfg_pad_i606;
+    input fabric_direct0_cfg_pad_i607;
+    input fabric_direct0_cfg_pad_i608;
+    input fabric_direct0_cfg_pad_i609;
+    input fabric_direct0_cfg_pad_i61;
+    input fabric_direct0_cfg_pad_i610;
+    input fabric_direct0_cfg_pad_i611;
+    input fabric_direct0_cfg_pad_i612;
+    input fabric_direct0_cfg_pad_i613;
+    input fabric_direct0_cfg_pad_i614;
+    input fabric_direct0_cfg_pad_i615;
+    input fabric_direct0_cfg_pad_i616;
+    input fabric_direct0_cfg_pad_i617;
+    input fabric_direct0_cfg_pad_i618;
+    input fabric_direct0_cfg_pad_i619;
+    input fabric_direct0_cfg_pad_i62;
+    input fabric_direct0_cfg_pad_i620;
+    input fabric_direct0_cfg_pad_i621;
+    input fabric_direct0_cfg_pad_i622;
+    input fabric_direct0_cfg_pad_i623;
+    input fabric_direct0_cfg_pad_i624;
+    input fabric_direct0_cfg_pad_i625;
+    input fabric_direct0_cfg_pad_i626;
+    input fabric_direct0_cfg_pad_i627;
+    input fabric_direct0_cfg_pad_i628;
+    input fabric_direct0_cfg_pad_i629;
+    input fabric_direct0_cfg_pad_i63;
+    input fabric_direct0_cfg_pad_i630;
+    input fabric_direct0_cfg_pad_i631;
+    input fabric_direct0_cfg_pad_i632;
+    input fabric_direct0_cfg_pad_i633;
+    input fabric_direct0_cfg_pad_i634;
+    input fabric_direct0_cfg_pad_i635;
+    input fabric_direct0_cfg_pad_i636;
+    input fabric_direct0_cfg_pad_i637;
+    input fabric_direct0_cfg_pad_i638;
+    input fabric_direct0_cfg_pad_i639;
+    input fabric_direct0_cfg_pad_i64;
+    input fabric_direct0_cfg_pad_i640;
+    input fabric_direct0_cfg_pad_i641;
+    input fabric_direct0_cfg_pad_i642;
+    input fabric_direct0_cfg_pad_i643;
+    input fabric_direct0_cfg_pad_i644;
+    input fabric_direct0_cfg_pad_i645;
+    input fabric_direct0_cfg_pad_i646;
+    input fabric_direct0_cfg_pad_i647;
+    input fabric_direct0_cfg_pad_i648;
+    input fabric_direct0_cfg_pad_i649;
+    input fabric_direct0_cfg_pad_i65;
+    input fabric_direct0_cfg_pad_i650;
+    input fabric_direct0_cfg_pad_i651;
+    input fabric_direct0_cfg_pad_i652;
+    input fabric_direct0_cfg_pad_i653;
+    input fabric_direct0_cfg_pad_i654;
+    input fabric_direct0_cfg_pad_i655;
+    input fabric_direct0_cfg_pad_i656;
+    input fabric_direct0_cfg_pad_i657;
+    input fabric_direct0_cfg_pad_i658;
+    input fabric_direct0_cfg_pad_i659;
+    input fabric_direct0_cfg_pad_i66;
+    input fabric_direct0_cfg_pad_i660;
+    input fabric_direct0_cfg_pad_i661;
+    input fabric_direct0_cfg_pad_i662;
+    input fabric_direct0_cfg_pad_i663;
+    input fabric_direct0_cfg_pad_i664;
+    input fabric_direct0_cfg_pad_i665;
+    input fabric_direct0_cfg_pad_i666;
+    input fabric_direct0_cfg_pad_i667;
+    input fabric_direct0_cfg_pad_i668;
+    input fabric_direct0_cfg_pad_i669;
+    input fabric_direct0_cfg_pad_i67;
+    input fabric_direct0_cfg_pad_i670;
+    input fabric_direct0_cfg_pad_i671;
+    input fabric_direct0_cfg_pad_i672;
+    input fabric_direct0_cfg_pad_i673;
+    input fabric_direct0_cfg_pad_i674;
+    input fabric_direct0_cfg_pad_i675;
+    input fabric_direct0_cfg_pad_i676;
+    input fabric_direct0_cfg_pad_i677;
+    input fabric_direct0_cfg_pad_i678;
+    input fabric_direct0_cfg_pad_i679;
+    input fabric_direct0_cfg_pad_i68;
+    input fabric_direct0_cfg_pad_i680;
+    input fabric_direct0_cfg_pad_i681;
+    input fabric_direct0_cfg_pad_i682;
+    input fabric_direct0_cfg_pad_i683;
+    input fabric_direct0_cfg_pad_i684;
+    input fabric_direct0_cfg_pad_i685;
+    input fabric_direct0_cfg_pad_i686;
+    input fabric_direct0_cfg_pad_i687;
+    input fabric_direct0_cfg_pad_i688;
+    input fabric_direct0_cfg_pad_i689;
+    input fabric_direct0_cfg_pad_i69;
+    input fabric_direct0_cfg_pad_i690;
+    input fabric_direct0_cfg_pad_i691;
+    input fabric_direct0_cfg_pad_i692;
+    input fabric_direct0_cfg_pad_i693;
+    input fabric_direct0_cfg_pad_i694;
+    input fabric_direct0_cfg_pad_i695;
+    input fabric_direct0_cfg_pad_i696;
+    input fabric_direct0_cfg_pad_i697;
+    input fabric_direct0_cfg_pad_i698;
+    input fabric_direct0_cfg_pad_i699;
+    input fabric_direct0_cfg_pad_i7;
+    input fabric_direct0_cfg_pad_i70;
+    input fabric_direct0_cfg_pad_i700;
+    input fabric_direct0_cfg_pad_i701;
+    input fabric_direct0_cfg_pad_i702;
+    input fabric_direct0_cfg_pad_i703;
+    input fabric_direct0_cfg_pad_i704;
+    input fabric_direct0_cfg_pad_i705;
+    input fabric_direct0_cfg_pad_i706;
+    input fabric_direct0_cfg_pad_i707;
+    input fabric_direct0_cfg_pad_i708;
+    input fabric_direct0_cfg_pad_i709;
+    input fabric_direct0_cfg_pad_i71;
+    input fabric_direct0_cfg_pad_i710;
+    input fabric_direct0_cfg_pad_i711;
+    input fabric_direct0_cfg_pad_i712;
+    input fabric_direct0_cfg_pad_i713;
+    input fabric_direct0_cfg_pad_i714;
+    input fabric_direct0_cfg_pad_i715;
+    input fabric_direct0_cfg_pad_i716;
+    input fabric_direct0_cfg_pad_i717;
+    input fabric_direct0_cfg_pad_i718;
+    input fabric_direct0_cfg_pad_i719;
+    input fabric_direct0_cfg_pad_i72;
+    input fabric_direct0_cfg_pad_i720;
+    input fabric_direct0_cfg_pad_i73;
+    input fabric_direct0_cfg_pad_i74;
+    input fabric_direct0_cfg_pad_i75;
+    input fabric_direct0_cfg_pad_i76;
+    input fabric_direct0_cfg_pad_i77;
+    input fabric_direct0_cfg_pad_i78;
+    input fabric_direct0_cfg_pad_i79;
+    input fabric_direct0_cfg_pad_i8;
+    input fabric_direct0_cfg_pad_i80;
+    input fabric_direct0_cfg_pad_i81;
+    input fabric_direct0_cfg_pad_i82;
+    input fabric_direct0_cfg_pad_i83;
+    input fabric_direct0_cfg_pad_i84;
+    input fabric_direct0_cfg_pad_i85;
+    input fabric_direct0_cfg_pad_i86;
+    input fabric_direct0_cfg_pad_i87;
+    input fabric_direct0_cfg_pad_i88;
+    input fabric_direct0_cfg_pad_i89;
+    input fabric_direct0_cfg_pad_i9;
+    input fabric_direct0_cfg_pad_i90;
+    input fabric_direct0_cfg_pad_i91;
+    input fabric_direct0_cfg_pad_i92;
+    input fabric_direct0_cfg_pad_i93;
+    input fabric_direct0_cfg_pad_i94;
+    input fabric_direct0_cfg_pad_i95;
+    input fabric_direct0_cfg_pad_i96;
+    input fabric_direct0_cfg_pad_i97;
+    input fabric_direct0_cfg_pad_i98;
+    input fabric_direct0_cfg_pad_i99;
+    input fabric_direct0_clock_fabric_i1;
+    input fabric_direct0_clock_fabric_i2;
+    input fabric_direct0_clock_fabric_i3;
+    input fabric_direct0_clock_fabric_i4;
+    input fabric_direct0_di_ena_i1;
+    input fabric_direct0_di_ena_i10;
+    input fabric_direct0_di_ena_i11;
+    input fabric_direct0_di_ena_i12;
+    input fabric_direct0_di_ena_i13;
+    input fabric_direct0_di_ena_i14;
+    input fabric_direct0_di_ena_i15;
+    input fabric_direct0_di_ena_i16;
+    input fabric_direct0_di_ena_i17;
+    input fabric_direct0_di_ena_i18;
+    input fabric_direct0_di_ena_i19;
+    input fabric_direct0_di_ena_i2;
+    input fabric_direct0_di_ena_i20;
+    input fabric_direct0_di_ena_i21;
+    input fabric_direct0_di_ena_i22;
+    input fabric_direct0_di_ena_i23;
+    input fabric_direct0_di_ena_i24;
+    input fabric_direct0_di_ena_i3;
+    input fabric_direct0_di_ena_i4;
+    input fabric_direct0_di_ena_i5;
+    input fabric_direct0_di_ena_i6;
+    input fabric_direct0_di_ena_i7;
+    input fabric_direct0_di_ena_i8;
+    input fabric_direct0_di_ena_i9;
+    output fabric_direct0_di_o1;
+    output fabric_direct0_di_o10;
+    output fabric_direct0_di_o11;
+    output fabric_direct0_di_o12;
+    output fabric_direct0_di_o13;
+    output fabric_direct0_di_o14;
+    output fabric_direct0_di_o15;
+    output fabric_direct0_di_o16;
+    output fabric_direct0_di_o17;
+    output fabric_direct0_di_o18;
+    output fabric_direct0_di_o19;
+    output fabric_direct0_di_o2;
+    output fabric_direct0_di_o20;
+    output fabric_direct0_di_o21;
+    output fabric_direct0_di_o22;
+    output fabric_direct0_di_o23;
+    output fabric_direct0_di_o24;
+    output fabric_direct0_di_o3;
+    output fabric_direct0_di_o4;
+    output fabric_direct0_di_o5;
+    output fabric_direct0_di_o6;
+    output fabric_direct0_di_o7;
+    output fabric_direct0_di_o8;
+    output fabric_direct0_di_o9;
+    input fabric_direct0_di_rs_i1;
+    input fabric_direct0_di_rs_i10;
+    input fabric_direct0_di_rs_i11;
+    input fabric_direct0_di_rs_i12;
+    input fabric_direct0_di_rs_i13;
+    input fabric_direct0_di_rs_i14;
+    input fabric_direct0_di_rs_i15;
+    input fabric_direct0_di_rs_i16;
+    input fabric_direct0_di_rs_i17;
+    input fabric_direct0_di_rs_i18;
+    input fabric_direct0_di_rs_i19;
+    input fabric_direct0_di_rs_i2;
+    input fabric_direct0_di_rs_i20;
+    input fabric_direct0_di_rs_i21;
+    input fabric_direct0_di_rs_i22;
+    input fabric_direct0_di_rs_i23;
+    input fabric_direct0_di_rs_i24;
+    input fabric_direct0_di_rs_i3;
+    input fabric_direct0_di_rs_i4;
+    input fabric_direct0_di_rs_i5;
+    input fabric_direct0_di_rs_i6;
+    input fabric_direct0_di_rs_i7;
+    input fabric_direct0_di_rs_i8;
+    input fabric_direct0_di_rs_i9;
+    input fabric_direct0_do_ena_i1;
+    input fabric_direct0_do_ena_i10;
+    input fabric_direct0_do_ena_i11;
+    input fabric_direct0_do_ena_i12;
+    input fabric_direct0_do_ena_i13;
+    input fabric_direct0_do_ena_i14;
+    input fabric_direct0_do_ena_i15;
+    input fabric_direct0_do_ena_i16;
+    input fabric_direct0_do_ena_i17;
+    input fabric_direct0_do_ena_i18;
+    input fabric_direct0_do_ena_i19;
+    input fabric_direct0_do_ena_i2;
+    input fabric_direct0_do_ena_i20;
+    input fabric_direct0_do_ena_i21;
+    input fabric_direct0_do_ena_i22;
+    input fabric_direct0_do_ena_i23;
+    input fabric_direct0_do_ena_i24;
+    input fabric_direct0_do_ena_i3;
+    input fabric_direct0_do_ena_i4;
+    input fabric_direct0_do_ena_i5;
+    input fabric_direct0_do_ena_i6;
+    input fabric_direct0_do_ena_i7;
+    input fabric_direct0_do_ena_i8;
+    input fabric_direct0_do_ena_i9;
+    input fabric_direct0_do_i1;
+    input fabric_direct0_do_i10;
+    input fabric_direct0_do_i11;
+    input fabric_direct0_do_i12;
+    input fabric_direct0_do_i13;
+    input fabric_direct0_do_i14;
+    input fabric_direct0_do_i15;
+    input fabric_direct0_do_i16;
+    input fabric_direct0_do_i17;
+    input fabric_direct0_do_i18;
+    input fabric_direct0_do_i19;
+    input fabric_direct0_do_i2;
+    input fabric_direct0_do_i20;
+    input fabric_direct0_do_i21;
+    input fabric_direct0_do_i22;
+    input fabric_direct0_do_i23;
+    input fabric_direct0_do_i24;
+    input fabric_direct0_do_i3;
+    input fabric_direct0_do_i4;
+    input fabric_direct0_do_i5;
+    input fabric_direct0_do_i6;
+    input fabric_direct0_do_i7;
+    input fabric_direct0_do_i8;
+    input fabric_direct0_do_i9;
+    input fabric_direct0_do_rs_i1;
+    input fabric_direct0_do_rs_i10;
+    input fabric_direct0_do_rs_i11;
+    input fabric_direct0_do_rs_i12;
+    input fabric_direct0_do_rs_i13;
+    input fabric_direct0_do_rs_i14;
+    input fabric_direct0_do_rs_i15;
+    input fabric_direct0_do_rs_i16;
+    input fabric_direct0_do_rs_i17;
+    input fabric_direct0_do_rs_i18;
+    input fabric_direct0_do_rs_i19;
+    input fabric_direct0_do_rs_i2;
+    input fabric_direct0_do_rs_i20;
+    input fabric_direct0_do_rs_i21;
+    input fabric_direct0_do_rs_i22;
+    input fabric_direct0_do_rs_i23;
+    input fabric_direct0_do_rs_i24;
+    input fabric_direct0_do_rs_i3;
+    input fabric_direct0_do_rs_i4;
+    input fabric_direct0_do_rs_i5;
+    input fabric_direct0_do_rs_i6;
+    input fabric_direct0_do_rs_i7;
+    input fabric_direct0_do_rs_i8;
+    input fabric_direct0_do_rs_i9;
+    input fabric_direct0_loopback_en_i;
+    input fabric_direct0_loopback_mux_i;
+    input fabric_direct0_oe_ena_i1;
+    input fabric_direct0_oe_ena_i10;
+    input fabric_direct0_oe_ena_i11;
+    input fabric_direct0_oe_ena_i12;
+    input fabric_direct0_oe_ena_i13;
+    input fabric_direct0_oe_ena_i14;
+    input fabric_direct0_oe_ena_i15;
+    input fabric_direct0_oe_ena_i16;
+    input fabric_direct0_oe_ena_i17;
+    input fabric_direct0_oe_ena_i18;
+    input fabric_direct0_oe_ena_i19;
+    input fabric_direct0_oe_ena_i2;
+    input fabric_direct0_oe_ena_i20;
+    input fabric_direct0_oe_ena_i21;
+    input fabric_direct0_oe_ena_i22;
+    input fabric_direct0_oe_ena_i23;
+    input fabric_direct0_oe_ena_i24;
+    input fabric_direct0_oe_ena_i3;
+    input fabric_direct0_oe_ena_i4;
+    input fabric_direct0_oe_ena_i5;
+    input fabric_direct0_oe_ena_i6;
+    input fabric_direct0_oe_ena_i7;
+    input fabric_direct0_oe_ena_i8;
+    input fabric_direct0_oe_ena_i9;
+    input fabric_direct0_oe_i1;
+    input fabric_direct0_oe_i10;
+    input fabric_direct0_oe_i11;
+    input fabric_direct0_oe_i12;
+    input fabric_direct0_oe_i13;
+    input fabric_direct0_oe_i14;
+    input fabric_direct0_oe_i15;
+    input fabric_direct0_oe_i16;
+    input fabric_direct0_oe_i17;
+    input fabric_direct0_oe_i18;
+    input fabric_direct0_oe_i19;
+    input fabric_direct0_oe_i2;
+    input fabric_direct0_oe_i20;
+    input fabric_direct0_oe_i21;
+    input fabric_direct0_oe_i22;
+    input fabric_direct0_oe_i23;
+    input fabric_direct0_oe_i24;
+    input fabric_direct0_oe_i3;
+    input fabric_direct0_oe_i4;
+    input fabric_direct0_oe_i5;
+    input fabric_direct0_oe_i6;
+    input fabric_direct0_oe_i7;
+    input fabric_direct0_oe_i8;
+    input fabric_direct0_oe_i9;
+    input fabric_direct0_oe_rs_i1;
+    input fabric_direct0_oe_rs_i10;
+    input fabric_direct0_oe_rs_i11;
+    input fabric_direct0_oe_rs_i12;
+    input fabric_direct0_oe_rs_i13;
+    input fabric_direct0_oe_rs_i14;
+    input fabric_direct0_oe_rs_i15;
+    input fabric_direct0_oe_rs_i16;
+    input fabric_direct0_oe_rs_i17;
+    input fabric_direct0_oe_rs_i18;
+    input fabric_direct0_oe_rs_i19;
+    input fabric_direct0_oe_rs_i2;
+    input fabric_direct0_oe_rs_i20;
+    input fabric_direct0_oe_rs_i21;
+    input fabric_direct0_oe_rs_i22;
+    input fabric_direct0_oe_rs_i23;
+    input fabric_direct0_oe_rs_i24;
+    input fabric_direct0_oe_rs_i3;
+    input fabric_direct0_oe_rs_i4;
+    input fabric_direct0_oe_rs_i5;
+    input fabric_direct0_oe_rs_i6;
+    input fabric_direct0_oe_rs_i7;
+    input fabric_direct0_oe_rs_i8;
+    input fabric_direct0_oe_rs_i9;
+    input fabric_direct0_scan_en_i;
+    input fabric_direct1_cfg_bank_i1;
+    input fabric_direct1_cfg_bank_i2;
+    input fabric_direct1_cfg_bank_i3;
+    input fabric_direct1_cfg_bank_i4;
+    input fabric_direct1_cfg_pad_i1;
+    input fabric_direct1_cfg_pad_i10;
+    input fabric_direct1_cfg_pad_i100;
+    input fabric_direct1_cfg_pad_i101;
+    input fabric_direct1_cfg_pad_i102;
+    input fabric_direct1_cfg_pad_i103;
+    input fabric_direct1_cfg_pad_i104;
+    input fabric_direct1_cfg_pad_i105;
+    input fabric_direct1_cfg_pad_i106;
+    input fabric_direct1_cfg_pad_i107;
+    input fabric_direct1_cfg_pad_i108;
+    input fabric_direct1_cfg_pad_i109;
+    input fabric_direct1_cfg_pad_i11;
+    input fabric_direct1_cfg_pad_i110;
+    input fabric_direct1_cfg_pad_i111;
+    input fabric_direct1_cfg_pad_i112;
+    input fabric_direct1_cfg_pad_i113;
+    input fabric_direct1_cfg_pad_i114;
+    input fabric_direct1_cfg_pad_i115;
+    input fabric_direct1_cfg_pad_i116;
+    input fabric_direct1_cfg_pad_i117;
+    input fabric_direct1_cfg_pad_i118;
+    input fabric_direct1_cfg_pad_i119;
+    input fabric_direct1_cfg_pad_i12;
+    input fabric_direct1_cfg_pad_i120;
+    input fabric_direct1_cfg_pad_i121;
+    input fabric_direct1_cfg_pad_i122;
+    input fabric_direct1_cfg_pad_i123;
+    input fabric_direct1_cfg_pad_i124;
+    input fabric_direct1_cfg_pad_i125;
+    input fabric_direct1_cfg_pad_i126;
+    input fabric_direct1_cfg_pad_i127;
+    input fabric_direct1_cfg_pad_i128;
+    input fabric_direct1_cfg_pad_i129;
+    input fabric_direct1_cfg_pad_i13;
+    input fabric_direct1_cfg_pad_i130;
+    input fabric_direct1_cfg_pad_i131;
+    input fabric_direct1_cfg_pad_i132;
+    input fabric_direct1_cfg_pad_i133;
+    input fabric_direct1_cfg_pad_i134;
+    input fabric_direct1_cfg_pad_i135;
+    input fabric_direct1_cfg_pad_i136;
+    input fabric_direct1_cfg_pad_i137;
+    input fabric_direct1_cfg_pad_i138;
+    input fabric_direct1_cfg_pad_i139;
+    input fabric_direct1_cfg_pad_i14;
+    input fabric_direct1_cfg_pad_i140;
+    input fabric_direct1_cfg_pad_i141;
+    input fabric_direct1_cfg_pad_i142;
+    input fabric_direct1_cfg_pad_i143;
+    input fabric_direct1_cfg_pad_i144;
+    input fabric_direct1_cfg_pad_i145;
+    input fabric_direct1_cfg_pad_i146;
+    input fabric_direct1_cfg_pad_i147;
+    input fabric_direct1_cfg_pad_i148;
+    input fabric_direct1_cfg_pad_i149;
+    input fabric_direct1_cfg_pad_i15;
+    input fabric_direct1_cfg_pad_i150;
+    input fabric_direct1_cfg_pad_i151;
+    input fabric_direct1_cfg_pad_i152;
+    input fabric_direct1_cfg_pad_i153;
+    input fabric_direct1_cfg_pad_i154;
+    input fabric_direct1_cfg_pad_i155;
+    input fabric_direct1_cfg_pad_i156;
+    input fabric_direct1_cfg_pad_i157;
+    input fabric_direct1_cfg_pad_i158;
+    input fabric_direct1_cfg_pad_i159;
+    input fabric_direct1_cfg_pad_i16;
+    input fabric_direct1_cfg_pad_i160;
+    input fabric_direct1_cfg_pad_i161;
+    input fabric_direct1_cfg_pad_i162;
+    input fabric_direct1_cfg_pad_i163;
+    input fabric_direct1_cfg_pad_i164;
+    input fabric_direct1_cfg_pad_i165;
+    input fabric_direct1_cfg_pad_i166;
+    input fabric_direct1_cfg_pad_i167;
+    input fabric_direct1_cfg_pad_i168;
+    input fabric_direct1_cfg_pad_i169;
+    input fabric_direct1_cfg_pad_i17;
+    input fabric_direct1_cfg_pad_i170;
+    input fabric_direct1_cfg_pad_i171;
+    input fabric_direct1_cfg_pad_i172;
+    input fabric_direct1_cfg_pad_i173;
+    input fabric_direct1_cfg_pad_i174;
+    input fabric_direct1_cfg_pad_i175;
+    input fabric_direct1_cfg_pad_i176;
+    input fabric_direct1_cfg_pad_i177;
+    input fabric_direct1_cfg_pad_i178;
+    input fabric_direct1_cfg_pad_i179;
+    input fabric_direct1_cfg_pad_i18;
+    input fabric_direct1_cfg_pad_i180;
+    input fabric_direct1_cfg_pad_i181;
+    input fabric_direct1_cfg_pad_i182;
+    input fabric_direct1_cfg_pad_i183;
+    input fabric_direct1_cfg_pad_i184;
+    input fabric_direct1_cfg_pad_i185;
+    input fabric_direct1_cfg_pad_i186;
+    input fabric_direct1_cfg_pad_i187;
+    input fabric_direct1_cfg_pad_i188;
+    input fabric_direct1_cfg_pad_i189;
+    input fabric_direct1_cfg_pad_i19;
+    input fabric_direct1_cfg_pad_i190;
+    input fabric_direct1_cfg_pad_i191;
+    input fabric_direct1_cfg_pad_i192;
+    input fabric_direct1_cfg_pad_i193;
+    input fabric_direct1_cfg_pad_i194;
+    input fabric_direct1_cfg_pad_i195;
+    input fabric_direct1_cfg_pad_i196;
+    input fabric_direct1_cfg_pad_i197;
+    input fabric_direct1_cfg_pad_i198;
+    input fabric_direct1_cfg_pad_i199;
+    input fabric_direct1_cfg_pad_i2;
+    input fabric_direct1_cfg_pad_i20;
+    input fabric_direct1_cfg_pad_i200;
+    input fabric_direct1_cfg_pad_i201;
+    input fabric_direct1_cfg_pad_i202;
+    input fabric_direct1_cfg_pad_i203;
+    input fabric_direct1_cfg_pad_i204;
+    input fabric_direct1_cfg_pad_i205;
+    input fabric_direct1_cfg_pad_i206;
+    input fabric_direct1_cfg_pad_i207;
+    input fabric_direct1_cfg_pad_i208;
+    input fabric_direct1_cfg_pad_i209;
+    input fabric_direct1_cfg_pad_i21;
+    input fabric_direct1_cfg_pad_i210;
+    input fabric_direct1_cfg_pad_i211;
+    input fabric_direct1_cfg_pad_i212;
+    input fabric_direct1_cfg_pad_i213;
+    input fabric_direct1_cfg_pad_i214;
+    input fabric_direct1_cfg_pad_i215;
+    input fabric_direct1_cfg_pad_i216;
+    input fabric_direct1_cfg_pad_i217;
+    input fabric_direct1_cfg_pad_i218;
+    input fabric_direct1_cfg_pad_i219;
+    input fabric_direct1_cfg_pad_i22;
+    input fabric_direct1_cfg_pad_i220;
+    input fabric_direct1_cfg_pad_i221;
+    input fabric_direct1_cfg_pad_i222;
+    input fabric_direct1_cfg_pad_i223;
+    input fabric_direct1_cfg_pad_i224;
+    input fabric_direct1_cfg_pad_i225;
+    input fabric_direct1_cfg_pad_i226;
+    input fabric_direct1_cfg_pad_i227;
+    input fabric_direct1_cfg_pad_i228;
+    input fabric_direct1_cfg_pad_i229;
+    input fabric_direct1_cfg_pad_i23;
+    input fabric_direct1_cfg_pad_i230;
+    input fabric_direct1_cfg_pad_i231;
+    input fabric_direct1_cfg_pad_i232;
+    input fabric_direct1_cfg_pad_i233;
+    input fabric_direct1_cfg_pad_i234;
+    input fabric_direct1_cfg_pad_i235;
+    input fabric_direct1_cfg_pad_i236;
+    input fabric_direct1_cfg_pad_i237;
+    input fabric_direct1_cfg_pad_i238;
+    input fabric_direct1_cfg_pad_i239;
+    input fabric_direct1_cfg_pad_i24;
+    input fabric_direct1_cfg_pad_i240;
+    input fabric_direct1_cfg_pad_i241;
+    input fabric_direct1_cfg_pad_i242;
+    input fabric_direct1_cfg_pad_i243;
+    input fabric_direct1_cfg_pad_i244;
+    input fabric_direct1_cfg_pad_i245;
+    input fabric_direct1_cfg_pad_i246;
+    input fabric_direct1_cfg_pad_i247;
+    input fabric_direct1_cfg_pad_i248;
+    input fabric_direct1_cfg_pad_i249;
+    input fabric_direct1_cfg_pad_i25;
+    input fabric_direct1_cfg_pad_i250;
+    input fabric_direct1_cfg_pad_i251;
+    input fabric_direct1_cfg_pad_i252;
+    input fabric_direct1_cfg_pad_i253;
+    input fabric_direct1_cfg_pad_i254;
+    input fabric_direct1_cfg_pad_i255;
+    input fabric_direct1_cfg_pad_i256;
+    input fabric_direct1_cfg_pad_i257;
+    input fabric_direct1_cfg_pad_i258;
+    input fabric_direct1_cfg_pad_i259;
+    input fabric_direct1_cfg_pad_i26;
+    input fabric_direct1_cfg_pad_i260;
+    input fabric_direct1_cfg_pad_i261;
+    input fabric_direct1_cfg_pad_i262;
+    input fabric_direct1_cfg_pad_i263;
+    input fabric_direct1_cfg_pad_i264;
+    input fabric_direct1_cfg_pad_i265;
+    input fabric_direct1_cfg_pad_i266;
+    input fabric_direct1_cfg_pad_i267;
+    input fabric_direct1_cfg_pad_i268;
+    input fabric_direct1_cfg_pad_i269;
+    input fabric_direct1_cfg_pad_i27;
+    input fabric_direct1_cfg_pad_i270;
+    input fabric_direct1_cfg_pad_i271;
+    input fabric_direct1_cfg_pad_i272;
+    input fabric_direct1_cfg_pad_i273;
+    input fabric_direct1_cfg_pad_i274;
+    input fabric_direct1_cfg_pad_i275;
+    input fabric_direct1_cfg_pad_i276;
+    input fabric_direct1_cfg_pad_i277;
+    input fabric_direct1_cfg_pad_i278;
+    input fabric_direct1_cfg_pad_i279;
+    input fabric_direct1_cfg_pad_i28;
+    input fabric_direct1_cfg_pad_i280;
+    input fabric_direct1_cfg_pad_i281;
+    input fabric_direct1_cfg_pad_i282;
+    input fabric_direct1_cfg_pad_i283;
+    input fabric_direct1_cfg_pad_i284;
+    input fabric_direct1_cfg_pad_i285;
+    input fabric_direct1_cfg_pad_i286;
+    input fabric_direct1_cfg_pad_i287;
+    input fabric_direct1_cfg_pad_i288;
+    input fabric_direct1_cfg_pad_i289;
+    input fabric_direct1_cfg_pad_i29;
+    input fabric_direct1_cfg_pad_i290;
+    input fabric_direct1_cfg_pad_i291;
+    input fabric_direct1_cfg_pad_i292;
+    input fabric_direct1_cfg_pad_i293;
+    input fabric_direct1_cfg_pad_i294;
+    input fabric_direct1_cfg_pad_i295;
+    input fabric_direct1_cfg_pad_i296;
+    input fabric_direct1_cfg_pad_i297;
+    input fabric_direct1_cfg_pad_i298;
+    input fabric_direct1_cfg_pad_i299;
+    input fabric_direct1_cfg_pad_i3;
+    input fabric_direct1_cfg_pad_i30;
+    input fabric_direct1_cfg_pad_i300;
+    input fabric_direct1_cfg_pad_i301;
+    input fabric_direct1_cfg_pad_i302;
+    input fabric_direct1_cfg_pad_i303;
+    input fabric_direct1_cfg_pad_i304;
+    input fabric_direct1_cfg_pad_i305;
+    input fabric_direct1_cfg_pad_i306;
+    input fabric_direct1_cfg_pad_i307;
+    input fabric_direct1_cfg_pad_i308;
+    input fabric_direct1_cfg_pad_i309;
+    input fabric_direct1_cfg_pad_i31;
+    input fabric_direct1_cfg_pad_i310;
+    input fabric_direct1_cfg_pad_i311;
+    input fabric_direct1_cfg_pad_i312;
+    input fabric_direct1_cfg_pad_i313;
+    input fabric_direct1_cfg_pad_i314;
+    input fabric_direct1_cfg_pad_i315;
+    input fabric_direct1_cfg_pad_i316;
+    input fabric_direct1_cfg_pad_i317;
+    input fabric_direct1_cfg_pad_i318;
+    input fabric_direct1_cfg_pad_i319;
+    input fabric_direct1_cfg_pad_i32;
+    input fabric_direct1_cfg_pad_i320;
+    input fabric_direct1_cfg_pad_i321;
+    input fabric_direct1_cfg_pad_i322;
+    input fabric_direct1_cfg_pad_i323;
+    input fabric_direct1_cfg_pad_i324;
+    input fabric_direct1_cfg_pad_i325;
+    input fabric_direct1_cfg_pad_i326;
+    input fabric_direct1_cfg_pad_i327;
+    input fabric_direct1_cfg_pad_i328;
+    input fabric_direct1_cfg_pad_i329;
+    input fabric_direct1_cfg_pad_i33;
+    input fabric_direct1_cfg_pad_i330;
+    input fabric_direct1_cfg_pad_i331;
+    input fabric_direct1_cfg_pad_i332;
+    input fabric_direct1_cfg_pad_i333;
+    input fabric_direct1_cfg_pad_i334;
+    input fabric_direct1_cfg_pad_i335;
+    input fabric_direct1_cfg_pad_i336;
+    input fabric_direct1_cfg_pad_i337;
+    input fabric_direct1_cfg_pad_i338;
+    input fabric_direct1_cfg_pad_i339;
+    input fabric_direct1_cfg_pad_i34;
+    input fabric_direct1_cfg_pad_i340;
+    input fabric_direct1_cfg_pad_i341;
+    input fabric_direct1_cfg_pad_i342;
+    input fabric_direct1_cfg_pad_i343;
+    input fabric_direct1_cfg_pad_i344;
+    input fabric_direct1_cfg_pad_i345;
+    input fabric_direct1_cfg_pad_i346;
+    input fabric_direct1_cfg_pad_i347;
+    input fabric_direct1_cfg_pad_i348;
+    input fabric_direct1_cfg_pad_i349;
+    input fabric_direct1_cfg_pad_i35;
+    input fabric_direct1_cfg_pad_i350;
+    input fabric_direct1_cfg_pad_i351;
+    input fabric_direct1_cfg_pad_i352;
+    input fabric_direct1_cfg_pad_i353;
+    input fabric_direct1_cfg_pad_i354;
+    input fabric_direct1_cfg_pad_i355;
+    input fabric_direct1_cfg_pad_i356;
+    input fabric_direct1_cfg_pad_i357;
+    input fabric_direct1_cfg_pad_i358;
+    input fabric_direct1_cfg_pad_i359;
+    input fabric_direct1_cfg_pad_i36;
+    input fabric_direct1_cfg_pad_i360;
+    input fabric_direct1_cfg_pad_i361;
+    input fabric_direct1_cfg_pad_i362;
+    input fabric_direct1_cfg_pad_i363;
+    input fabric_direct1_cfg_pad_i364;
+    input fabric_direct1_cfg_pad_i365;
+    input fabric_direct1_cfg_pad_i366;
+    input fabric_direct1_cfg_pad_i367;
+    input fabric_direct1_cfg_pad_i368;
+    input fabric_direct1_cfg_pad_i369;
+    input fabric_direct1_cfg_pad_i37;
+    input fabric_direct1_cfg_pad_i370;
+    input fabric_direct1_cfg_pad_i371;
+    input fabric_direct1_cfg_pad_i372;
+    input fabric_direct1_cfg_pad_i373;
+    input fabric_direct1_cfg_pad_i374;
+    input fabric_direct1_cfg_pad_i375;
+    input fabric_direct1_cfg_pad_i376;
+    input fabric_direct1_cfg_pad_i377;
+    input fabric_direct1_cfg_pad_i378;
+    input fabric_direct1_cfg_pad_i379;
+    input fabric_direct1_cfg_pad_i38;
+    input fabric_direct1_cfg_pad_i380;
+    input fabric_direct1_cfg_pad_i381;
+    input fabric_direct1_cfg_pad_i382;
+    input fabric_direct1_cfg_pad_i383;
+    input fabric_direct1_cfg_pad_i384;
+    input fabric_direct1_cfg_pad_i385;
+    input fabric_direct1_cfg_pad_i386;
+    input fabric_direct1_cfg_pad_i387;
+    input fabric_direct1_cfg_pad_i388;
+    input fabric_direct1_cfg_pad_i389;
+    input fabric_direct1_cfg_pad_i39;
+    input fabric_direct1_cfg_pad_i390;
+    input fabric_direct1_cfg_pad_i391;
+    input fabric_direct1_cfg_pad_i392;
+    input fabric_direct1_cfg_pad_i393;
+    input fabric_direct1_cfg_pad_i394;
+    input fabric_direct1_cfg_pad_i395;
+    input fabric_direct1_cfg_pad_i396;
+    input fabric_direct1_cfg_pad_i397;
+    input fabric_direct1_cfg_pad_i398;
+    input fabric_direct1_cfg_pad_i399;
+    input fabric_direct1_cfg_pad_i4;
+    input fabric_direct1_cfg_pad_i40;
+    input fabric_direct1_cfg_pad_i400;
+    input fabric_direct1_cfg_pad_i401;
+    input fabric_direct1_cfg_pad_i402;
+    input fabric_direct1_cfg_pad_i403;
+    input fabric_direct1_cfg_pad_i404;
+    input fabric_direct1_cfg_pad_i405;
+    input fabric_direct1_cfg_pad_i406;
+    input fabric_direct1_cfg_pad_i407;
+    input fabric_direct1_cfg_pad_i408;
+    input fabric_direct1_cfg_pad_i409;
+    input fabric_direct1_cfg_pad_i41;
+    input fabric_direct1_cfg_pad_i410;
+    input fabric_direct1_cfg_pad_i411;
+    input fabric_direct1_cfg_pad_i412;
+    input fabric_direct1_cfg_pad_i413;
+    input fabric_direct1_cfg_pad_i414;
+    input fabric_direct1_cfg_pad_i415;
+    input fabric_direct1_cfg_pad_i416;
+    input fabric_direct1_cfg_pad_i417;
+    input fabric_direct1_cfg_pad_i418;
+    input fabric_direct1_cfg_pad_i419;
+    input fabric_direct1_cfg_pad_i42;
+    input fabric_direct1_cfg_pad_i420;
+    input fabric_direct1_cfg_pad_i421;
+    input fabric_direct1_cfg_pad_i422;
+    input fabric_direct1_cfg_pad_i423;
+    input fabric_direct1_cfg_pad_i424;
+    input fabric_direct1_cfg_pad_i425;
+    input fabric_direct1_cfg_pad_i426;
+    input fabric_direct1_cfg_pad_i427;
+    input fabric_direct1_cfg_pad_i428;
+    input fabric_direct1_cfg_pad_i429;
+    input fabric_direct1_cfg_pad_i43;
+    input fabric_direct1_cfg_pad_i430;
+    input fabric_direct1_cfg_pad_i431;
+    input fabric_direct1_cfg_pad_i432;
+    input fabric_direct1_cfg_pad_i433;
+    input fabric_direct1_cfg_pad_i434;
+    input fabric_direct1_cfg_pad_i435;
+    input fabric_direct1_cfg_pad_i436;
+    input fabric_direct1_cfg_pad_i437;
+    input fabric_direct1_cfg_pad_i438;
+    input fabric_direct1_cfg_pad_i439;
+    input fabric_direct1_cfg_pad_i44;
+    input fabric_direct1_cfg_pad_i440;
+    input fabric_direct1_cfg_pad_i441;
+    input fabric_direct1_cfg_pad_i442;
+    input fabric_direct1_cfg_pad_i443;
+    input fabric_direct1_cfg_pad_i444;
+    input fabric_direct1_cfg_pad_i445;
+    input fabric_direct1_cfg_pad_i446;
+    input fabric_direct1_cfg_pad_i447;
+    input fabric_direct1_cfg_pad_i448;
+    input fabric_direct1_cfg_pad_i449;
+    input fabric_direct1_cfg_pad_i45;
+    input fabric_direct1_cfg_pad_i450;
+    input fabric_direct1_cfg_pad_i451;
+    input fabric_direct1_cfg_pad_i452;
+    input fabric_direct1_cfg_pad_i453;
+    input fabric_direct1_cfg_pad_i454;
+    input fabric_direct1_cfg_pad_i455;
+    input fabric_direct1_cfg_pad_i456;
+    input fabric_direct1_cfg_pad_i457;
+    input fabric_direct1_cfg_pad_i458;
+    input fabric_direct1_cfg_pad_i459;
+    input fabric_direct1_cfg_pad_i46;
+    input fabric_direct1_cfg_pad_i460;
+    input fabric_direct1_cfg_pad_i461;
+    input fabric_direct1_cfg_pad_i462;
+    input fabric_direct1_cfg_pad_i463;
+    input fabric_direct1_cfg_pad_i464;
+    input fabric_direct1_cfg_pad_i465;
+    input fabric_direct1_cfg_pad_i466;
+    input fabric_direct1_cfg_pad_i467;
+    input fabric_direct1_cfg_pad_i468;
+    input fabric_direct1_cfg_pad_i469;
+    input fabric_direct1_cfg_pad_i47;
+    input fabric_direct1_cfg_pad_i470;
+    input fabric_direct1_cfg_pad_i471;
+    input fabric_direct1_cfg_pad_i472;
+    input fabric_direct1_cfg_pad_i473;
+    input fabric_direct1_cfg_pad_i474;
+    input fabric_direct1_cfg_pad_i475;
+    input fabric_direct1_cfg_pad_i476;
+    input fabric_direct1_cfg_pad_i477;
+    input fabric_direct1_cfg_pad_i478;
+    input fabric_direct1_cfg_pad_i479;
+    input fabric_direct1_cfg_pad_i48;
+    input fabric_direct1_cfg_pad_i480;
+    input fabric_direct1_cfg_pad_i49;
+    input fabric_direct1_cfg_pad_i5;
+    input fabric_direct1_cfg_pad_i50;
+    input fabric_direct1_cfg_pad_i51;
+    input fabric_direct1_cfg_pad_i52;
+    input fabric_direct1_cfg_pad_i53;
+    input fabric_direct1_cfg_pad_i54;
+    input fabric_direct1_cfg_pad_i55;
+    input fabric_direct1_cfg_pad_i56;
+    input fabric_direct1_cfg_pad_i57;
+    input fabric_direct1_cfg_pad_i58;
+    input fabric_direct1_cfg_pad_i59;
+    input fabric_direct1_cfg_pad_i6;
+    input fabric_direct1_cfg_pad_i60;
+    input fabric_direct1_cfg_pad_i61;
+    input fabric_direct1_cfg_pad_i62;
+    input fabric_direct1_cfg_pad_i63;
+    input fabric_direct1_cfg_pad_i64;
+    input fabric_direct1_cfg_pad_i65;
+    input fabric_direct1_cfg_pad_i66;
+    input fabric_direct1_cfg_pad_i67;
+    input fabric_direct1_cfg_pad_i68;
+    input fabric_direct1_cfg_pad_i69;
+    input fabric_direct1_cfg_pad_i7;
+    input fabric_direct1_cfg_pad_i70;
+    input fabric_direct1_cfg_pad_i71;
+    input fabric_direct1_cfg_pad_i72;
+    input fabric_direct1_cfg_pad_i73;
+    input fabric_direct1_cfg_pad_i74;
+    input fabric_direct1_cfg_pad_i75;
+    input fabric_direct1_cfg_pad_i76;
+    input fabric_direct1_cfg_pad_i77;
+    input fabric_direct1_cfg_pad_i78;
+    input fabric_direct1_cfg_pad_i79;
+    input fabric_direct1_cfg_pad_i8;
+    input fabric_direct1_cfg_pad_i80;
+    input fabric_direct1_cfg_pad_i81;
+    input fabric_direct1_cfg_pad_i82;
+    input fabric_direct1_cfg_pad_i83;
+    input fabric_direct1_cfg_pad_i84;
+    input fabric_direct1_cfg_pad_i85;
+    input fabric_direct1_cfg_pad_i86;
+    input fabric_direct1_cfg_pad_i87;
+    input fabric_direct1_cfg_pad_i88;
+    input fabric_direct1_cfg_pad_i89;
+    input fabric_direct1_cfg_pad_i9;
+    input fabric_direct1_cfg_pad_i90;
+    input fabric_direct1_cfg_pad_i91;
+    input fabric_direct1_cfg_pad_i92;
+    input fabric_direct1_cfg_pad_i93;
+    input fabric_direct1_cfg_pad_i94;
+    input fabric_direct1_cfg_pad_i95;
+    input fabric_direct1_cfg_pad_i96;
+    input fabric_direct1_cfg_pad_i97;
+    input fabric_direct1_cfg_pad_i98;
+    input fabric_direct1_cfg_pad_i99;
+    input fabric_direct1_clock_fabric_i1;
+    input fabric_direct1_clock_fabric_i2;
+    input fabric_direct1_clock_fabric_i3;
+    input fabric_direct1_clock_fabric_i4;
+    input fabric_direct1_di_ena_i1;
+    input fabric_direct1_di_ena_i10;
+    input fabric_direct1_di_ena_i11;
+    input fabric_direct1_di_ena_i12;
+    input fabric_direct1_di_ena_i13;
+    input fabric_direct1_di_ena_i14;
+    input fabric_direct1_di_ena_i15;
+    input fabric_direct1_di_ena_i16;
+    input fabric_direct1_di_ena_i2;
+    input fabric_direct1_di_ena_i3;
+    input fabric_direct1_di_ena_i4;
+    input fabric_direct1_di_ena_i5;
+    input fabric_direct1_di_ena_i6;
+    input fabric_direct1_di_ena_i7;
+    input fabric_direct1_di_ena_i8;
+    input fabric_direct1_di_ena_i9;
+    output fabric_direct1_di_o1;
+    output fabric_direct1_di_o10;
+    output fabric_direct1_di_o11;
+    output fabric_direct1_di_o12;
+    output fabric_direct1_di_o13;
+    output fabric_direct1_di_o14;
+    output fabric_direct1_di_o15;
+    output fabric_direct1_di_o16;
+    output fabric_direct1_di_o2;
+    output fabric_direct1_di_o3;
+    output fabric_direct1_di_o4;
+    output fabric_direct1_di_o5;
+    output fabric_direct1_di_o6;
+    output fabric_direct1_di_o7;
+    output fabric_direct1_di_o8;
+    output fabric_direct1_di_o9;
+    input fabric_direct1_di_rs_i1;
+    input fabric_direct1_di_rs_i10;
+    input fabric_direct1_di_rs_i11;
+    input fabric_direct1_di_rs_i12;
+    input fabric_direct1_di_rs_i13;
+    input fabric_direct1_di_rs_i14;
+    input fabric_direct1_di_rs_i15;
+    input fabric_direct1_di_rs_i16;
+    input fabric_direct1_di_rs_i2;
+    input fabric_direct1_di_rs_i3;
+    input fabric_direct1_di_rs_i4;
+    input fabric_direct1_di_rs_i5;
+    input fabric_direct1_di_rs_i6;
+    input fabric_direct1_di_rs_i7;
+    input fabric_direct1_di_rs_i8;
+    input fabric_direct1_di_rs_i9;
+    input fabric_direct1_do_ena_i1;
+    input fabric_direct1_do_ena_i10;
+    input fabric_direct1_do_ena_i11;
+    input fabric_direct1_do_ena_i12;
+    input fabric_direct1_do_ena_i13;
+    input fabric_direct1_do_ena_i14;
+    input fabric_direct1_do_ena_i15;
+    input fabric_direct1_do_ena_i16;
+    input fabric_direct1_do_ena_i2;
+    input fabric_direct1_do_ena_i3;
+    input fabric_direct1_do_ena_i4;
+    input fabric_direct1_do_ena_i5;
+    input fabric_direct1_do_ena_i6;
+    input fabric_direct1_do_ena_i7;
+    input fabric_direct1_do_ena_i8;
+    input fabric_direct1_do_ena_i9;
+    input fabric_direct1_do_i1;
+    input fabric_direct1_do_i10;
+    input fabric_direct1_do_i11;
+    input fabric_direct1_do_i12;
+    input fabric_direct1_do_i13;
+    input fabric_direct1_do_i14;
+    input fabric_direct1_do_i15;
+    input fabric_direct1_do_i16;
+    input fabric_direct1_do_i2;
+    input fabric_direct1_do_i3;
+    input fabric_direct1_do_i4;
+    input fabric_direct1_do_i5;
+    input fabric_direct1_do_i6;
+    input fabric_direct1_do_i7;
+    input fabric_direct1_do_i8;
+    input fabric_direct1_do_i9;
+    input fabric_direct1_do_rs_i1;
+    input fabric_direct1_do_rs_i10;
+    input fabric_direct1_do_rs_i11;
+    input fabric_direct1_do_rs_i12;
+    input fabric_direct1_do_rs_i13;
+    input fabric_direct1_do_rs_i14;
+    input fabric_direct1_do_rs_i15;
+    input fabric_direct1_do_rs_i16;
+    input fabric_direct1_do_rs_i2;
+    input fabric_direct1_do_rs_i3;
+    input fabric_direct1_do_rs_i4;
+    input fabric_direct1_do_rs_i5;
+    input fabric_direct1_do_rs_i6;
+    input fabric_direct1_do_rs_i7;
+    input fabric_direct1_do_rs_i8;
+    input fabric_direct1_do_rs_i9;
+    input fabric_direct1_loopback_en_i;
+    input fabric_direct1_loopback_mux_i;
+    input fabric_direct1_oe_ena_i1;
+    input fabric_direct1_oe_ena_i10;
+    input fabric_direct1_oe_ena_i11;
+    input fabric_direct1_oe_ena_i12;
+    input fabric_direct1_oe_ena_i13;
+    input fabric_direct1_oe_ena_i14;
+    input fabric_direct1_oe_ena_i15;
+    input fabric_direct1_oe_ena_i16;
+    input fabric_direct1_oe_ena_i2;
+    input fabric_direct1_oe_ena_i3;
+    input fabric_direct1_oe_ena_i4;
+    input fabric_direct1_oe_ena_i5;
+    input fabric_direct1_oe_ena_i6;
+    input fabric_direct1_oe_ena_i7;
+    input fabric_direct1_oe_ena_i8;
+    input fabric_direct1_oe_ena_i9;
+    input fabric_direct1_oe_i1;
+    input fabric_direct1_oe_i10;
+    input fabric_direct1_oe_i11;
+    input fabric_direct1_oe_i12;
+    input fabric_direct1_oe_i13;
+    input fabric_direct1_oe_i14;
+    input fabric_direct1_oe_i15;
+    input fabric_direct1_oe_i16;
+    input fabric_direct1_oe_i2;
+    input fabric_direct1_oe_i3;
+    input fabric_direct1_oe_i4;
+    input fabric_direct1_oe_i5;
+    input fabric_direct1_oe_i6;
+    input fabric_direct1_oe_i7;
+    input fabric_direct1_oe_i8;
+    input fabric_direct1_oe_i9;
+    input fabric_direct1_oe_rs_i1;
+    input fabric_direct1_oe_rs_i10;
+    input fabric_direct1_oe_rs_i11;
+    input fabric_direct1_oe_rs_i12;
+    input fabric_direct1_oe_rs_i13;
+    input fabric_direct1_oe_rs_i14;
+    input fabric_direct1_oe_rs_i15;
+    input fabric_direct1_oe_rs_i16;
+    input fabric_direct1_oe_rs_i2;
+    input fabric_direct1_oe_rs_i3;
+    input fabric_direct1_oe_rs_i4;
+    input fabric_direct1_oe_rs_i5;
+    input fabric_direct1_oe_rs_i6;
+    input fabric_direct1_oe_rs_i7;
+    input fabric_direct1_oe_rs_i8;
+    input fabric_direct1_oe_rs_i9;
+    input fabric_direct1_scan_en_i;
+    input fabric_direct2_cfg_bank_i1;
+    input fabric_direct2_cfg_bank_i2;
+    input fabric_direct2_cfg_bank_i3;
+    input fabric_direct2_cfg_bank_i4;
+    input fabric_direct2_cfg_pad_i1;
+    input fabric_direct2_cfg_pad_i10;
+    input fabric_direct2_cfg_pad_i100;
+    input fabric_direct2_cfg_pad_i101;
+    input fabric_direct2_cfg_pad_i102;
+    input fabric_direct2_cfg_pad_i103;
+    input fabric_direct2_cfg_pad_i104;
+    input fabric_direct2_cfg_pad_i105;
+    input fabric_direct2_cfg_pad_i106;
+    input fabric_direct2_cfg_pad_i107;
+    input fabric_direct2_cfg_pad_i108;
+    input fabric_direct2_cfg_pad_i109;
+    input fabric_direct2_cfg_pad_i11;
+    input fabric_direct2_cfg_pad_i110;
+    input fabric_direct2_cfg_pad_i111;
+    input fabric_direct2_cfg_pad_i112;
+    input fabric_direct2_cfg_pad_i113;
+    input fabric_direct2_cfg_pad_i114;
+    input fabric_direct2_cfg_pad_i115;
+    input fabric_direct2_cfg_pad_i116;
+    input fabric_direct2_cfg_pad_i117;
+    input fabric_direct2_cfg_pad_i118;
+    input fabric_direct2_cfg_pad_i119;
+    input fabric_direct2_cfg_pad_i12;
+    input fabric_direct2_cfg_pad_i120;
+    input fabric_direct2_cfg_pad_i121;
+    input fabric_direct2_cfg_pad_i122;
+    input fabric_direct2_cfg_pad_i123;
+    input fabric_direct2_cfg_pad_i124;
+    input fabric_direct2_cfg_pad_i125;
+    input fabric_direct2_cfg_pad_i126;
+    input fabric_direct2_cfg_pad_i127;
+    input fabric_direct2_cfg_pad_i128;
+    input fabric_direct2_cfg_pad_i129;
+    input fabric_direct2_cfg_pad_i13;
+    input fabric_direct2_cfg_pad_i130;
+    input fabric_direct2_cfg_pad_i131;
+    input fabric_direct2_cfg_pad_i132;
+    input fabric_direct2_cfg_pad_i133;
+    input fabric_direct2_cfg_pad_i134;
+    input fabric_direct2_cfg_pad_i135;
+    input fabric_direct2_cfg_pad_i136;
+    input fabric_direct2_cfg_pad_i137;
+    input fabric_direct2_cfg_pad_i138;
+    input fabric_direct2_cfg_pad_i139;
+    input fabric_direct2_cfg_pad_i14;
+    input fabric_direct2_cfg_pad_i140;
+    input fabric_direct2_cfg_pad_i141;
+    input fabric_direct2_cfg_pad_i142;
+    input fabric_direct2_cfg_pad_i143;
+    input fabric_direct2_cfg_pad_i144;
+    input fabric_direct2_cfg_pad_i145;
+    input fabric_direct2_cfg_pad_i146;
+    input fabric_direct2_cfg_pad_i147;
+    input fabric_direct2_cfg_pad_i148;
+    input fabric_direct2_cfg_pad_i149;
+    input fabric_direct2_cfg_pad_i15;
+    input fabric_direct2_cfg_pad_i150;
+    input fabric_direct2_cfg_pad_i151;
+    input fabric_direct2_cfg_pad_i152;
+    input fabric_direct2_cfg_pad_i153;
+    input fabric_direct2_cfg_pad_i154;
+    input fabric_direct2_cfg_pad_i155;
+    input fabric_direct2_cfg_pad_i156;
+    input fabric_direct2_cfg_pad_i157;
+    input fabric_direct2_cfg_pad_i158;
+    input fabric_direct2_cfg_pad_i159;
+    input fabric_direct2_cfg_pad_i16;
+    input fabric_direct2_cfg_pad_i160;
+    input fabric_direct2_cfg_pad_i161;
+    input fabric_direct2_cfg_pad_i162;
+    input fabric_direct2_cfg_pad_i163;
+    input fabric_direct2_cfg_pad_i164;
+    input fabric_direct2_cfg_pad_i165;
+    input fabric_direct2_cfg_pad_i166;
+    input fabric_direct2_cfg_pad_i167;
+    input fabric_direct2_cfg_pad_i168;
+    input fabric_direct2_cfg_pad_i169;
+    input fabric_direct2_cfg_pad_i17;
+    input fabric_direct2_cfg_pad_i170;
+    input fabric_direct2_cfg_pad_i171;
+    input fabric_direct2_cfg_pad_i172;
+    input fabric_direct2_cfg_pad_i173;
+    input fabric_direct2_cfg_pad_i174;
+    input fabric_direct2_cfg_pad_i175;
+    input fabric_direct2_cfg_pad_i176;
+    input fabric_direct2_cfg_pad_i177;
+    input fabric_direct2_cfg_pad_i178;
+    input fabric_direct2_cfg_pad_i179;
+    input fabric_direct2_cfg_pad_i18;
+    input fabric_direct2_cfg_pad_i180;
+    input fabric_direct2_cfg_pad_i181;
+    input fabric_direct2_cfg_pad_i182;
+    input fabric_direct2_cfg_pad_i183;
+    input fabric_direct2_cfg_pad_i184;
+    input fabric_direct2_cfg_pad_i185;
+    input fabric_direct2_cfg_pad_i186;
+    input fabric_direct2_cfg_pad_i187;
+    input fabric_direct2_cfg_pad_i188;
+    input fabric_direct2_cfg_pad_i189;
+    input fabric_direct2_cfg_pad_i19;
+    input fabric_direct2_cfg_pad_i190;
+    input fabric_direct2_cfg_pad_i191;
+    input fabric_direct2_cfg_pad_i192;
+    input fabric_direct2_cfg_pad_i193;
+    input fabric_direct2_cfg_pad_i194;
+    input fabric_direct2_cfg_pad_i195;
+    input fabric_direct2_cfg_pad_i196;
+    input fabric_direct2_cfg_pad_i197;
+    input fabric_direct2_cfg_pad_i198;
+    input fabric_direct2_cfg_pad_i199;
+    input fabric_direct2_cfg_pad_i2;
+    input fabric_direct2_cfg_pad_i20;
+    input fabric_direct2_cfg_pad_i200;
+    input fabric_direct2_cfg_pad_i201;
+    input fabric_direct2_cfg_pad_i202;
+    input fabric_direct2_cfg_pad_i203;
+    input fabric_direct2_cfg_pad_i204;
+    input fabric_direct2_cfg_pad_i205;
+    input fabric_direct2_cfg_pad_i206;
+    input fabric_direct2_cfg_pad_i207;
+    input fabric_direct2_cfg_pad_i208;
+    input fabric_direct2_cfg_pad_i209;
+    input fabric_direct2_cfg_pad_i21;
+    input fabric_direct2_cfg_pad_i210;
+    input fabric_direct2_cfg_pad_i211;
+    input fabric_direct2_cfg_pad_i212;
+    input fabric_direct2_cfg_pad_i213;
+    input fabric_direct2_cfg_pad_i214;
+    input fabric_direct2_cfg_pad_i215;
+    input fabric_direct2_cfg_pad_i216;
+    input fabric_direct2_cfg_pad_i217;
+    input fabric_direct2_cfg_pad_i218;
+    input fabric_direct2_cfg_pad_i219;
+    input fabric_direct2_cfg_pad_i22;
+    input fabric_direct2_cfg_pad_i220;
+    input fabric_direct2_cfg_pad_i221;
+    input fabric_direct2_cfg_pad_i222;
+    input fabric_direct2_cfg_pad_i223;
+    input fabric_direct2_cfg_pad_i224;
+    input fabric_direct2_cfg_pad_i225;
+    input fabric_direct2_cfg_pad_i226;
+    input fabric_direct2_cfg_pad_i227;
+    input fabric_direct2_cfg_pad_i228;
+    input fabric_direct2_cfg_pad_i229;
+    input fabric_direct2_cfg_pad_i23;
+    input fabric_direct2_cfg_pad_i230;
+    input fabric_direct2_cfg_pad_i231;
+    input fabric_direct2_cfg_pad_i232;
+    input fabric_direct2_cfg_pad_i233;
+    input fabric_direct2_cfg_pad_i234;
+    input fabric_direct2_cfg_pad_i235;
+    input fabric_direct2_cfg_pad_i236;
+    input fabric_direct2_cfg_pad_i237;
+    input fabric_direct2_cfg_pad_i238;
+    input fabric_direct2_cfg_pad_i239;
+    input fabric_direct2_cfg_pad_i24;
+    input fabric_direct2_cfg_pad_i240;
+    input fabric_direct2_cfg_pad_i241;
+    input fabric_direct2_cfg_pad_i242;
+    input fabric_direct2_cfg_pad_i243;
+    input fabric_direct2_cfg_pad_i244;
+    input fabric_direct2_cfg_pad_i245;
+    input fabric_direct2_cfg_pad_i246;
+    input fabric_direct2_cfg_pad_i247;
+    input fabric_direct2_cfg_pad_i248;
+    input fabric_direct2_cfg_pad_i249;
+    input fabric_direct2_cfg_pad_i25;
+    input fabric_direct2_cfg_pad_i250;
+    input fabric_direct2_cfg_pad_i251;
+    input fabric_direct2_cfg_pad_i252;
+    input fabric_direct2_cfg_pad_i253;
+    input fabric_direct2_cfg_pad_i254;
+    input fabric_direct2_cfg_pad_i255;
+    input fabric_direct2_cfg_pad_i256;
+    input fabric_direct2_cfg_pad_i257;
+    input fabric_direct2_cfg_pad_i258;
+    input fabric_direct2_cfg_pad_i259;
+    input fabric_direct2_cfg_pad_i26;
+    input fabric_direct2_cfg_pad_i260;
+    input fabric_direct2_cfg_pad_i261;
+    input fabric_direct2_cfg_pad_i262;
+    input fabric_direct2_cfg_pad_i263;
+    input fabric_direct2_cfg_pad_i264;
+    input fabric_direct2_cfg_pad_i265;
+    input fabric_direct2_cfg_pad_i266;
+    input fabric_direct2_cfg_pad_i267;
+    input fabric_direct2_cfg_pad_i268;
+    input fabric_direct2_cfg_pad_i269;
+    input fabric_direct2_cfg_pad_i27;
+    input fabric_direct2_cfg_pad_i270;
+    input fabric_direct2_cfg_pad_i271;
+    input fabric_direct2_cfg_pad_i272;
+    input fabric_direct2_cfg_pad_i273;
+    input fabric_direct2_cfg_pad_i274;
+    input fabric_direct2_cfg_pad_i275;
+    input fabric_direct2_cfg_pad_i276;
+    input fabric_direct2_cfg_pad_i277;
+    input fabric_direct2_cfg_pad_i278;
+    input fabric_direct2_cfg_pad_i279;
+    input fabric_direct2_cfg_pad_i28;
+    input fabric_direct2_cfg_pad_i280;
+    input fabric_direct2_cfg_pad_i281;
+    input fabric_direct2_cfg_pad_i282;
+    input fabric_direct2_cfg_pad_i283;
+    input fabric_direct2_cfg_pad_i284;
+    input fabric_direct2_cfg_pad_i285;
+    input fabric_direct2_cfg_pad_i286;
+    input fabric_direct2_cfg_pad_i287;
+    input fabric_direct2_cfg_pad_i288;
+    input fabric_direct2_cfg_pad_i289;
+    input fabric_direct2_cfg_pad_i29;
+    input fabric_direct2_cfg_pad_i290;
+    input fabric_direct2_cfg_pad_i291;
+    input fabric_direct2_cfg_pad_i292;
+    input fabric_direct2_cfg_pad_i293;
+    input fabric_direct2_cfg_pad_i294;
+    input fabric_direct2_cfg_pad_i295;
+    input fabric_direct2_cfg_pad_i296;
+    input fabric_direct2_cfg_pad_i297;
+    input fabric_direct2_cfg_pad_i298;
+    input fabric_direct2_cfg_pad_i299;
+    input fabric_direct2_cfg_pad_i3;
+    input fabric_direct2_cfg_pad_i30;
+    input fabric_direct2_cfg_pad_i300;
+    input fabric_direct2_cfg_pad_i301;
+    input fabric_direct2_cfg_pad_i302;
+    input fabric_direct2_cfg_pad_i303;
+    input fabric_direct2_cfg_pad_i304;
+    input fabric_direct2_cfg_pad_i305;
+    input fabric_direct2_cfg_pad_i306;
+    input fabric_direct2_cfg_pad_i307;
+    input fabric_direct2_cfg_pad_i308;
+    input fabric_direct2_cfg_pad_i309;
+    input fabric_direct2_cfg_pad_i31;
+    input fabric_direct2_cfg_pad_i310;
+    input fabric_direct2_cfg_pad_i311;
+    input fabric_direct2_cfg_pad_i312;
+    input fabric_direct2_cfg_pad_i313;
+    input fabric_direct2_cfg_pad_i314;
+    input fabric_direct2_cfg_pad_i315;
+    input fabric_direct2_cfg_pad_i316;
+    input fabric_direct2_cfg_pad_i317;
+    input fabric_direct2_cfg_pad_i318;
+    input fabric_direct2_cfg_pad_i319;
+    input fabric_direct2_cfg_pad_i32;
+    input fabric_direct2_cfg_pad_i320;
+    input fabric_direct2_cfg_pad_i321;
+    input fabric_direct2_cfg_pad_i322;
+    input fabric_direct2_cfg_pad_i323;
+    input fabric_direct2_cfg_pad_i324;
+    input fabric_direct2_cfg_pad_i325;
+    input fabric_direct2_cfg_pad_i326;
+    input fabric_direct2_cfg_pad_i327;
+    input fabric_direct2_cfg_pad_i328;
+    input fabric_direct2_cfg_pad_i329;
+    input fabric_direct2_cfg_pad_i33;
+    input fabric_direct2_cfg_pad_i330;
+    input fabric_direct2_cfg_pad_i331;
+    input fabric_direct2_cfg_pad_i332;
+    input fabric_direct2_cfg_pad_i333;
+    input fabric_direct2_cfg_pad_i334;
+    input fabric_direct2_cfg_pad_i335;
+    input fabric_direct2_cfg_pad_i336;
+    input fabric_direct2_cfg_pad_i337;
+    input fabric_direct2_cfg_pad_i338;
+    input fabric_direct2_cfg_pad_i339;
+    input fabric_direct2_cfg_pad_i34;
+    input fabric_direct2_cfg_pad_i340;
+    input fabric_direct2_cfg_pad_i341;
+    input fabric_direct2_cfg_pad_i342;
+    input fabric_direct2_cfg_pad_i343;
+    input fabric_direct2_cfg_pad_i344;
+    input fabric_direct2_cfg_pad_i345;
+    input fabric_direct2_cfg_pad_i346;
+    input fabric_direct2_cfg_pad_i347;
+    input fabric_direct2_cfg_pad_i348;
+    input fabric_direct2_cfg_pad_i349;
+    input fabric_direct2_cfg_pad_i35;
+    input fabric_direct2_cfg_pad_i350;
+    input fabric_direct2_cfg_pad_i351;
+    input fabric_direct2_cfg_pad_i352;
+    input fabric_direct2_cfg_pad_i353;
+    input fabric_direct2_cfg_pad_i354;
+    input fabric_direct2_cfg_pad_i355;
+    input fabric_direct2_cfg_pad_i356;
+    input fabric_direct2_cfg_pad_i357;
+    input fabric_direct2_cfg_pad_i358;
+    input fabric_direct2_cfg_pad_i359;
+    input fabric_direct2_cfg_pad_i36;
+    input fabric_direct2_cfg_pad_i360;
+    input fabric_direct2_cfg_pad_i361;
+    input fabric_direct2_cfg_pad_i362;
+    input fabric_direct2_cfg_pad_i363;
+    input fabric_direct2_cfg_pad_i364;
+    input fabric_direct2_cfg_pad_i365;
+    input fabric_direct2_cfg_pad_i366;
+    input fabric_direct2_cfg_pad_i367;
+    input fabric_direct2_cfg_pad_i368;
+    input fabric_direct2_cfg_pad_i369;
+    input fabric_direct2_cfg_pad_i37;
+    input fabric_direct2_cfg_pad_i370;
+    input fabric_direct2_cfg_pad_i371;
+    input fabric_direct2_cfg_pad_i372;
+    input fabric_direct2_cfg_pad_i373;
+    input fabric_direct2_cfg_pad_i374;
+    input fabric_direct2_cfg_pad_i375;
+    input fabric_direct2_cfg_pad_i376;
+    input fabric_direct2_cfg_pad_i377;
+    input fabric_direct2_cfg_pad_i378;
+    input fabric_direct2_cfg_pad_i379;
+    input fabric_direct2_cfg_pad_i38;
+    input fabric_direct2_cfg_pad_i380;
+    input fabric_direct2_cfg_pad_i381;
+    input fabric_direct2_cfg_pad_i382;
+    input fabric_direct2_cfg_pad_i383;
+    input fabric_direct2_cfg_pad_i384;
+    input fabric_direct2_cfg_pad_i385;
+    input fabric_direct2_cfg_pad_i386;
+    input fabric_direct2_cfg_pad_i387;
+    input fabric_direct2_cfg_pad_i388;
+    input fabric_direct2_cfg_pad_i389;
+    input fabric_direct2_cfg_pad_i39;
+    input fabric_direct2_cfg_pad_i390;
+    input fabric_direct2_cfg_pad_i391;
+    input fabric_direct2_cfg_pad_i392;
+    input fabric_direct2_cfg_pad_i393;
+    input fabric_direct2_cfg_pad_i394;
+    input fabric_direct2_cfg_pad_i395;
+    input fabric_direct2_cfg_pad_i396;
+    input fabric_direct2_cfg_pad_i397;
+    input fabric_direct2_cfg_pad_i398;
+    input fabric_direct2_cfg_pad_i399;
+    input fabric_direct2_cfg_pad_i4;
+    input fabric_direct2_cfg_pad_i40;
+    input fabric_direct2_cfg_pad_i400;
+    input fabric_direct2_cfg_pad_i401;
+    input fabric_direct2_cfg_pad_i402;
+    input fabric_direct2_cfg_pad_i403;
+    input fabric_direct2_cfg_pad_i404;
+    input fabric_direct2_cfg_pad_i405;
+    input fabric_direct2_cfg_pad_i406;
+    input fabric_direct2_cfg_pad_i407;
+    input fabric_direct2_cfg_pad_i408;
+    input fabric_direct2_cfg_pad_i409;
+    input fabric_direct2_cfg_pad_i41;
+    input fabric_direct2_cfg_pad_i410;
+    input fabric_direct2_cfg_pad_i411;
+    input fabric_direct2_cfg_pad_i412;
+    input fabric_direct2_cfg_pad_i413;
+    input fabric_direct2_cfg_pad_i414;
+    input fabric_direct2_cfg_pad_i415;
+    input fabric_direct2_cfg_pad_i416;
+    input fabric_direct2_cfg_pad_i417;
+    input fabric_direct2_cfg_pad_i418;
+    input fabric_direct2_cfg_pad_i419;
+    input fabric_direct2_cfg_pad_i42;
+    input fabric_direct2_cfg_pad_i420;
+    input fabric_direct2_cfg_pad_i421;
+    input fabric_direct2_cfg_pad_i422;
+    input fabric_direct2_cfg_pad_i423;
+    input fabric_direct2_cfg_pad_i424;
+    input fabric_direct2_cfg_pad_i425;
+    input fabric_direct2_cfg_pad_i426;
+    input fabric_direct2_cfg_pad_i427;
+    input fabric_direct2_cfg_pad_i428;
+    input fabric_direct2_cfg_pad_i429;
+    input fabric_direct2_cfg_pad_i43;
+    input fabric_direct2_cfg_pad_i430;
+    input fabric_direct2_cfg_pad_i431;
+    input fabric_direct2_cfg_pad_i432;
+    input fabric_direct2_cfg_pad_i433;
+    input fabric_direct2_cfg_pad_i434;
+    input fabric_direct2_cfg_pad_i435;
+    input fabric_direct2_cfg_pad_i436;
+    input fabric_direct2_cfg_pad_i437;
+    input fabric_direct2_cfg_pad_i438;
+    input fabric_direct2_cfg_pad_i439;
+    input fabric_direct2_cfg_pad_i44;
+    input fabric_direct2_cfg_pad_i440;
+    input fabric_direct2_cfg_pad_i441;
+    input fabric_direct2_cfg_pad_i442;
+    input fabric_direct2_cfg_pad_i443;
+    input fabric_direct2_cfg_pad_i444;
+    input fabric_direct2_cfg_pad_i445;
+    input fabric_direct2_cfg_pad_i446;
+    input fabric_direct2_cfg_pad_i447;
+    input fabric_direct2_cfg_pad_i448;
+    input fabric_direct2_cfg_pad_i449;
+    input fabric_direct2_cfg_pad_i45;
+    input fabric_direct2_cfg_pad_i450;
+    input fabric_direct2_cfg_pad_i451;
+    input fabric_direct2_cfg_pad_i452;
+    input fabric_direct2_cfg_pad_i453;
+    input fabric_direct2_cfg_pad_i454;
+    input fabric_direct2_cfg_pad_i455;
+    input fabric_direct2_cfg_pad_i456;
+    input fabric_direct2_cfg_pad_i457;
+    input fabric_direct2_cfg_pad_i458;
+    input fabric_direct2_cfg_pad_i459;
+    input fabric_direct2_cfg_pad_i46;
+    input fabric_direct2_cfg_pad_i460;
+    input fabric_direct2_cfg_pad_i461;
+    input fabric_direct2_cfg_pad_i462;
+    input fabric_direct2_cfg_pad_i463;
+    input fabric_direct2_cfg_pad_i464;
+    input fabric_direct2_cfg_pad_i465;
+    input fabric_direct2_cfg_pad_i466;
+    input fabric_direct2_cfg_pad_i467;
+    input fabric_direct2_cfg_pad_i468;
+    input fabric_direct2_cfg_pad_i469;
+    input fabric_direct2_cfg_pad_i47;
+    input fabric_direct2_cfg_pad_i470;
+    input fabric_direct2_cfg_pad_i471;
+    input fabric_direct2_cfg_pad_i472;
+    input fabric_direct2_cfg_pad_i473;
+    input fabric_direct2_cfg_pad_i474;
+    input fabric_direct2_cfg_pad_i475;
+    input fabric_direct2_cfg_pad_i476;
+    input fabric_direct2_cfg_pad_i477;
+    input fabric_direct2_cfg_pad_i478;
+    input fabric_direct2_cfg_pad_i479;
+    input fabric_direct2_cfg_pad_i48;
+    input fabric_direct2_cfg_pad_i480;
+    input fabric_direct2_cfg_pad_i481;
+    input fabric_direct2_cfg_pad_i482;
+    input fabric_direct2_cfg_pad_i483;
+    input fabric_direct2_cfg_pad_i484;
+    input fabric_direct2_cfg_pad_i485;
+    input fabric_direct2_cfg_pad_i486;
+    input fabric_direct2_cfg_pad_i487;
+    input fabric_direct2_cfg_pad_i488;
+    input fabric_direct2_cfg_pad_i489;
+    input fabric_direct2_cfg_pad_i49;
+    input fabric_direct2_cfg_pad_i490;
+    input fabric_direct2_cfg_pad_i491;
+    input fabric_direct2_cfg_pad_i492;
+    input fabric_direct2_cfg_pad_i493;
+    input fabric_direct2_cfg_pad_i494;
+    input fabric_direct2_cfg_pad_i495;
+    input fabric_direct2_cfg_pad_i496;
+    input fabric_direct2_cfg_pad_i497;
+    input fabric_direct2_cfg_pad_i498;
+    input fabric_direct2_cfg_pad_i499;
+    input fabric_direct2_cfg_pad_i5;
+    input fabric_direct2_cfg_pad_i50;
+    input fabric_direct2_cfg_pad_i500;
+    input fabric_direct2_cfg_pad_i501;
+    input fabric_direct2_cfg_pad_i502;
+    input fabric_direct2_cfg_pad_i503;
+    input fabric_direct2_cfg_pad_i504;
+    input fabric_direct2_cfg_pad_i505;
+    input fabric_direct2_cfg_pad_i506;
+    input fabric_direct2_cfg_pad_i507;
+    input fabric_direct2_cfg_pad_i508;
+    input fabric_direct2_cfg_pad_i509;
+    input fabric_direct2_cfg_pad_i51;
+    input fabric_direct2_cfg_pad_i510;
+    input fabric_direct2_cfg_pad_i511;
+    input fabric_direct2_cfg_pad_i512;
+    input fabric_direct2_cfg_pad_i513;
+    input fabric_direct2_cfg_pad_i514;
+    input fabric_direct2_cfg_pad_i515;
+    input fabric_direct2_cfg_pad_i516;
+    input fabric_direct2_cfg_pad_i517;
+    input fabric_direct2_cfg_pad_i518;
+    input fabric_direct2_cfg_pad_i519;
+    input fabric_direct2_cfg_pad_i52;
+    input fabric_direct2_cfg_pad_i520;
+    input fabric_direct2_cfg_pad_i521;
+    input fabric_direct2_cfg_pad_i522;
+    input fabric_direct2_cfg_pad_i523;
+    input fabric_direct2_cfg_pad_i524;
+    input fabric_direct2_cfg_pad_i525;
+    input fabric_direct2_cfg_pad_i526;
+    input fabric_direct2_cfg_pad_i527;
+    input fabric_direct2_cfg_pad_i528;
+    input fabric_direct2_cfg_pad_i529;
+    input fabric_direct2_cfg_pad_i53;
+    input fabric_direct2_cfg_pad_i530;
+    input fabric_direct2_cfg_pad_i531;
+    input fabric_direct2_cfg_pad_i532;
+    input fabric_direct2_cfg_pad_i533;
+    input fabric_direct2_cfg_pad_i534;
+    input fabric_direct2_cfg_pad_i535;
+    input fabric_direct2_cfg_pad_i536;
+    input fabric_direct2_cfg_pad_i537;
+    input fabric_direct2_cfg_pad_i538;
+    input fabric_direct2_cfg_pad_i539;
+    input fabric_direct2_cfg_pad_i54;
+    input fabric_direct2_cfg_pad_i540;
+    input fabric_direct2_cfg_pad_i541;
+    input fabric_direct2_cfg_pad_i542;
+    input fabric_direct2_cfg_pad_i543;
+    input fabric_direct2_cfg_pad_i544;
+    input fabric_direct2_cfg_pad_i545;
+    input fabric_direct2_cfg_pad_i546;
+    input fabric_direct2_cfg_pad_i547;
+    input fabric_direct2_cfg_pad_i548;
+    input fabric_direct2_cfg_pad_i549;
+    input fabric_direct2_cfg_pad_i55;
+    input fabric_direct2_cfg_pad_i550;
+    input fabric_direct2_cfg_pad_i551;
+    input fabric_direct2_cfg_pad_i552;
+    input fabric_direct2_cfg_pad_i553;
+    input fabric_direct2_cfg_pad_i554;
+    input fabric_direct2_cfg_pad_i555;
+    input fabric_direct2_cfg_pad_i556;
+    input fabric_direct2_cfg_pad_i557;
+    input fabric_direct2_cfg_pad_i558;
+    input fabric_direct2_cfg_pad_i559;
+    input fabric_direct2_cfg_pad_i56;
+    input fabric_direct2_cfg_pad_i560;
+    input fabric_direct2_cfg_pad_i561;
+    input fabric_direct2_cfg_pad_i562;
+    input fabric_direct2_cfg_pad_i563;
+    input fabric_direct2_cfg_pad_i564;
+    input fabric_direct2_cfg_pad_i565;
+    input fabric_direct2_cfg_pad_i566;
+    input fabric_direct2_cfg_pad_i567;
+    input fabric_direct2_cfg_pad_i568;
+    input fabric_direct2_cfg_pad_i569;
+    input fabric_direct2_cfg_pad_i57;
+    input fabric_direct2_cfg_pad_i570;
+    input fabric_direct2_cfg_pad_i571;
+    input fabric_direct2_cfg_pad_i572;
+    input fabric_direct2_cfg_pad_i573;
+    input fabric_direct2_cfg_pad_i574;
+    input fabric_direct2_cfg_pad_i575;
+    input fabric_direct2_cfg_pad_i576;
+    input fabric_direct2_cfg_pad_i577;
+    input fabric_direct2_cfg_pad_i578;
+    input fabric_direct2_cfg_pad_i579;
+    input fabric_direct2_cfg_pad_i58;
+    input fabric_direct2_cfg_pad_i580;
+    input fabric_direct2_cfg_pad_i581;
+    input fabric_direct2_cfg_pad_i582;
+    input fabric_direct2_cfg_pad_i583;
+    input fabric_direct2_cfg_pad_i584;
+    input fabric_direct2_cfg_pad_i585;
+    input fabric_direct2_cfg_pad_i586;
+    input fabric_direct2_cfg_pad_i587;
+    input fabric_direct2_cfg_pad_i588;
+    input fabric_direct2_cfg_pad_i589;
+    input fabric_direct2_cfg_pad_i59;
+    input fabric_direct2_cfg_pad_i590;
+    input fabric_direct2_cfg_pad_i591;
+    input fabric_direct2_cfg_pad_i592;
+    input fabric_direct2_cfg_pad_i593;
+    input fabric_direct2_cfg_pad_i594;
+    input fabric_direct2_cfg_pad_i595;
+    input fabric_direct2_cfg_pad_i596;
+    input fabric_direct2_cfg_pad_i597;
+    input fabric_direct2_cfg_pad_i598;
+    input fabric_direct2_cfg_pad_i599;
+    input fabric_direct2_cfg_pad_i6;
+    input fabric_direct2_cfg_pad_i60;
+    input fabric_direct2_cfg_pad_i600;
+    input fabric_direct2_cfg_pad_i601;
+    input fabric_direct2_cfg_pad_i602;
+    input fabric_direct2_cfg_pad_i603;
+    input fabric_direct2_cfg_pad_i604;
+    input fabric_direct2_cfg_pad_i605;
+    input fabric_direct2_cfg_pad_i606;
+    input fabric_direct2_cfg_pad_i607;
+    input fabric_direct2_cfg_pad_i608;
+    input fabric_direct2_cfg_pad_i609;
+    input fabric_direct2_cfg_pad_i61;
+    input fabric_direct2_cfg_pad_i610;
+    input fabric_direct2_cfg_pad_i611;
+    input fabric_direct2_cfg_pad_i612;
+    input fabric_direct2_cfg_pad_i613;
+    input fabric_direct2_cfg_pad_i614;
+    input fabric_direct2_cfg_pad_i615;
+    input fabric_direct2_cfg_pad_i616;
+    input fabric_direct2_cfg_pad_i617;
+    input fabric_direct2_cfg_pad_i618;
+    input fabric_direct2_cfg_pad_i619;
+    input fabric_direct2_cfg_pad_i62;
+    input fabric_direct2_cfg_pad_i620;
+    input fabric_direct2_cfg_pad_i621;
+    input fabric_direct2_cfg_pad_i622;
+    input fabric_direct2_cfg_pad_i623;
+    input fabric_direct2_cfg_pad_i624;
+    input fabric_direct2_cfg_pad_i625;
+    input fabric_direct2_cfg_pad_i626;
+    input fabric_direct2_cfg_pad_i627;
+    input fabric_direct2_cfg_pad_i628;
+    input fabric_direct2_cfg_pad_i629;
+    input fabric_direct2_cfg_pad_i63;
+    input fabric_direct2_cfg_pad_i630;
+    input fabric_direct2_cfg_pad_i631;
+    input fabric_direct2_cfg_pad_i632;
+    input fabric_direct2_cfg_pad_i633;
+    input fabric_direct2_cfg_pad_i634;
+    input fabric_direct2_cfg_pad_i635;
+    input fabric_direct2_cfg_pad_i636;
+    input fabric_direct2_cfg_pad_i637;
+    input fabric_direct2_cfg_pad_i638;
+    input fabric_direct2_cfg_pad_i639;
+    input fabric_direct2_cfg_pad_i64;
+    input fabric_direct2_cfg_pad_i640;
+    input fabric_direct2_cfg_pad_i641;
+    input fabric_direct2_cfg_pad_i642;
+    input fabric_direct2_cfg_pad_i643;
+    input fabric_direct2_cfg_pad_i644;
+    input fabric_direct2_cfg_pad_i645;
+    input fabric_direct2_cfg_pad_i646;
+    input fabric_direct2_cfg_pad_i647;
+    input fabric_direct2_cfg_pad_i648;
+    input fabric_direct2_cfg_pad_i649;
+    input fabric_direct2_cfg_pad_i65;
+    input fabric_direct2_cfg_pad_i650;
+    input fabric_direct2_cfg_pad_i651;
+    input fabric_direct2_cfg_pad_i652;
+    input fabric_direct2_cfg_pad_i653;
+    input fabric_direct2_cfg_pad_i654;
+    input fabric_direct2_cfg_pad_i655;
+    input fabric_direct2_cfg_pad_i656;
+    input fabric_direct2_cfg_pad_i657;
+    input fabric_direct2_cfg_pad_i658;
+    input fabric_direct2_cfg_pad_i659;
+    input fabric_direct2_cfg_pad_i66;
+    input fabric_direct2_cfg_pad_i660;
+    input fabric_direct2_cfg_pad_i661;
+    input fabric_direct2_cfg_pad_i662;
+    input fabric_direct2_cfg_pad_i663;
+    input fabric_direct2_cfg_pad_i664;
+    input fabric_direct2_cfg_pad_i665;
+    input fabric_direct2_cfg_pad_i666;
+    input fabric_direct2_cfg_pad_i667;
+    input fabric_direct2_cfg_pad_i668;
+    input fabric_direct2_cfg_pad_i669;
+    input fabric_direct2_cfg_pad_i67;
+    input fabric_direct2_cfg_pad_i670;
+    input fabric_direct2_cfg_pad_i671;
+    input fabric_direct2_cfg_pad_i672;
+    input fabric_direct2_cfg_pad_i673;
+    input fabric_direct2_cfg_pad_i674;
+    input fabric_direct2_cfg_pad_i675;
+    input fabric_direct2_cfg_pad_i676;
+    input fabric_direct2_cfg_pad_i677;
+    input fabric_direct2_cfg_pad_i678;
+    input fabric_direct2_cfg_pad_i679;
+    input fabric_direct2_cfg_pad_i68;
+    input fabric_direct2_cfg_pad_i680;
+    input fabric_direct2_cfg_pad_i681;
+    input fabric_direct2_cfg_pad_i682;
+    input fabric_direct2_cfg_pad_i683;
+    input fabric_direct2_cfg_pad_i684;
+    input fabric_direct2_cfg_pad_i685;
+    input fabric_direct2_cfg_pad_i686;
+    input fabric_direct2_cfg_pad_i687;
+    input fabric_direct2_cfg_pad_i688;
+    input fabric_direct2_cfg_pad_i689;
+    input fabric_direct2_cfg_pad_i69;
+    input fabric_direct2_cfg_pad_i690;
+    input fabric_direct2_cfg_pad_i691;
+    input fabric_direct2_cfg_pad_i692;
+    input fabric_direct2_cfg_pad_i693;
+    input fabric_direct2_cfg_pad_i694;
+    input fabric_direct2_cfg_pad_i695;
+    input fabric_direct2_cfg_pad_i696;
+    input fabric_direct2_cfg_pad_i697;
+    input fabric_direct2_cfg_pad_i698;
+    input fabric_direct2_cfg_pad_i699;
+    input fabric_direct2_cfg_pad_i7;
+    input fabric_direct2_cfg_pad_i70;
+    input fabric_direct2_cfg_pad_i700;
+    input fabric_direct2_cfg_pad_i701;
+    input fabric_direct2_cfg_pad_i702;
+    input fabric_direct2_cfg_pad_i703;
+    input fabric_direct2_cfg_pad_i704;
+    input fabric_direct2_cfg_pad_i705;
+    input fabric_direct2_cfg_pad_i706;
+    input fabric_direct2_cfg_pad_i707;
+    input fabric_direct2_cfg_pad_i708;
+    input fabric_direct2_cfg_pad_i709;
+    input fabric_direct2_cfg_pad_i71;
+    input fabric_direct2_cfg_pad_i710;
+    input fabric_direct2_cfg_pad_i711;
+    input fabric_direct2_cfg_pad_i712;
+    input fabric_direct2_cfg_pad_i713;
+    input fabric_direct2_cfg_pad_i714;
+    input fabric_direct2_cfg_pad_i715;
+    input fabric_direct2_cfg_pad_i716;
+    input fabric_direct2_cfg_pad_i717;
+    input fabric_direct2_cfg_pad_i718;
+    input fabric_direct2_cfg_pad_i719;
+    input fabric_direct2_cfg_pad_i72;
+    input fabric_direct2_cfg_pad_i720;
+    input fabric_direct2_cfg_pad_i73;
+    input fabric_direct2_cfg_pad_i74;
+    input fabric_direct2_cfg_pad_i75;
+    input fabric_direct2_cfg_pad_i76;
+    input fabric_direct2_cfg_pad_i77;
+    input fabric_direct2_cfg_pad_i78;
+    input fabric_direct2_cfg_pad_i79;
+    input fabric_direct2_cfg_pad_i8;
+    input fabric_direct2_cfg_pad_i80;
+    input fabric_direct2_cfg_pad_i81;
+    input fabric_direct2_cfg_pad_i82;
+    input fabric_direct2_cfg_pad_i83;
+    input fabric_direct2_cfg_pad_i84;
+    input fabric_direct2_cfg_pad_i85;
+    input fabric_direct2_cfg_pad_i86;
+    input fabric_direct2_cfg_pad_i87;
+    input fabric_direct2_cfg_pad_i88;
+    input fabric_direct2_cfg_pad_i89;
+    input fabric_direct2_cfg_pad_i9;
+    input fabric_direct2_cfg_pad_i90;
+    input fabric_direct2_cfg_pad_i91;
+    input fabric_direct2_cfg_pad_i92;
+    input fabric_direct2_cfg_pad_i93;
+    input fabric_direct2_cfg_pad_i94;
+    input fabric_direct2_cfg_pad_i95;
+    input fabric_direct2_cfg_pad_i96;
+    input fabric_direct2_cfg_pad_i97;
+    input fabric_direct2_cfg_pad_i98;
+    input fabric_direct2_cfg_pad_i99;
+    input fabric_direct2_clock_fabric_i1;
+    input fabric_direct2_clock_fabric_i2;
+    input fabric_direct2_clock_fabric_i3;
+    input fabric_direct2_clock_fabric_i4;
+    input fabric_direct2_di_ena_i1;
+    input fabric_direct2_di_ena_i10;
+    input fabric_direct2_di_ena_i11;
+    input fabric_direct2_di_ena_i12;
+    input fabric_direct2_di_ena_i13;
+    input fabric_direct2_di_ena_i14;
+    input fabric_direct2_di_ena_i15;
+    input fabric_direct2_di_ena_i16;
+    input fabric_direct2_di_ena_i17;
+    input fabric_direct2_di_ena_i18;
+    input fabric_direct2_di_ena_i19;
+    input fabric_direct2_di_ena_i2;
+    input fabric_direct2_di_ena_i20;
+    input fabric_direct2_di_ena_i21;
+    input fabric_direct2_di_ena_i22;
+    input fabric_direct2_di_ena_i23;
+    input fabric_direct2_di_ena_i24;
+    input fabric_direct2_di_ena_i3;
+    input fabric_direct2_di_ena_i4;
+    input fabric_direct2_di_ena_i5;
+    input fabric_direct2_di_ena_i6;
+    input fabric_direct2_di_ena_i7;
+    input fabric_direct2_di_ena_i8;
+    input fabric_direct2_di_ena_i9;
+    output fabric_direct2_di_o1;
+    output fabric_direct2_di_o10;
+    output fabric_direct2_di_o11;
+    output fabric_direct2_di_o12;
+    output fabric_direct2_di_o13;
+    output fabric_direct2_di_o14;
+    output fabric_direct2_di_o15;
+    output fabric_direct2_di_o16;
+    output fabric_direct2_di_o17;
+    output fabric_direct2_di_o18;
+    output fabric_direct2_di_o19;
+    output fabric_direct2_di_o2;
+    output fabric_direct2_di_o20;
+    output fabric_direct2_di_o21;
+    output fabric_direct2_di_o22;
+    output fabric_direct2_di_o23;
+    output fabric_direct2_di_o24;
+    output fabric_direct2_di_o3;
+    output fabric_direct2_di_o4;
+    output fabric_direct2_di_o5;
+    output fabric_direct2_di_o6;
+    output fabric_direct2_di_o7;
+    output fabric_direct2_di_o8;
+    output fabric_direct2_di_o9;
+    input fabric_direct2_di_rs_i1;
+    input fabric_direct2_di_rs_i10;
+    input fabric_direct2_di_rs_i11;
+    input fabric_direct2_di_rs_i12;
+    input fabric_direct2_di_rs_i13;
+    input fabric_direct2_di_rs_i14;
+    input fabric_direct2_di_rs_i15;
+    input fabric_direct2_di_rs_i16;
+    input fabric_direct2_di_rs_i17;
+    input fabric_direct2_di_rs_i18;
+    input fabric_direct2_di_rs_i19;
+    input fabric_direct2_di_rs_i2;
+    input fabric_direct2_di_rs_i20;
+    input fabric_direct2_di_rs_i21;
+    input fabric_direct2_di_rs_i22;
+    input fabric_direct2_di_rs_i23;
+    input fabric_direct2_di_rs_i24;
+    input fabric_direct2_di_rs_i3;
+    input fabric_direct2_di_rs_i4;
+    input fabric_direct2_di_rs_i5;
+    input fabric_direct2_di_rs_i6;
+    input fabric_direct2_di_rs_i7;
+    input fabric_direct2_di_rs_i8;
+    input fabric_direct2_di_rs_i9;
+    input fabric_direct2_do_ena_i1;
+    input fabric_direct2_do_ena_i10;
+    input fabric_direct2_do_ena_i11;
+    input fabric_direct2_do_ena_i12;
+    input fabric_direct2_do_ena_i13;
+    input fabric_direct2_do_ena_i14;
+    input fabric_direct2_do_ena_i15;
+    input fabric_direct2_do_ena_i16;
+    input fabric_direct2_do_ena_i17;
+    input fabric_direct2_do_ena_i18;
+    input fabric_direct2_do_ena_i19;
+    input fabric_direct2_do_ena_i2;
+    input fabric_direct2_do_ena_i20;
+    input fabric_direct2_do_ena_i21;
+    input fabric_direct2_do_ena_i22;
+    input fabric_direct2_do_ena_i23;
+    input fabric_direct2_do_ena_i24;
+    input fabric_direct2_do_ena_i3;
+    input fabric_direct2_do_ena_i4;
+    input fabric_direct2_do_ena_i5;
+    input fabric_direct2_do_ena_i6;
+    input fabric_direct2_do_ena_i7;
+    input fabric_direct2_do_ena_i8;
+    input fabric_direct2_do_ena_i9;
+    input fabric_direct2_do_i1;
+    input fabric_direct2_do_i10;
+    input fabric_direct2_do_i11;
+    input fabric_direct2_do_i12;
+    input fabric_direct2_do_i13;
+    input fabric_direct2_do_i14;
+    input fabric_direct2_do_i15;
+    input fabric_direct2_do_i16;
+    input fabric_direct2_do_i17;
+    input fabric_direct2_do_i18;
+    input fabric_direct2_do_i19;
+    input fabric_direct2_do_i2;
+    input fabric_direct2_do_i20;
+    input fabric_direct2_do_i21;
+    input fabric_direct2_do_i22;
+    input fabric_direct2_do_i23;
+    input fabric_direct2_do_i24;
+    input fabric_direct2_do_i3;
+    input fabric_direct2_do_i4;
+    input fabric_direct2_do_i5;
+    input fabric_direct2_do_i6;
+    input fabric_direct2_do_i7;
+    input fabric_direct2_do_i8;
+    input fabric_direct2_do_i9;
+    input fabric_direct2_do_rs_i1;
+    input fabric_direct2_do_rs_i10;
+    input fabric_direct2_do_rs_i11;
+    input fabric_direct2_do_rs_i12;
+    input fabric_direct2_do_rs_i13;
+    input fabric_direct2_do_rs_i14;
+    input fabric_direct2_do_rs_i15;
+    input fabric_direct2_do_rs_i16;
+    input fabric_direct2_do_rs_i17;
+    input fabric_direct2_do_rs_i18;
+    input fabric_direct2_do_rs_i19;
+    input fabric_direct2_do_rs_i2;
+    input fabric_direct2_do_rs_i20;
+    input fabric_direct2_do_rs_i21;
+    input fabric_direct2_do_rs_i22;
+    input fabric_direct2_do_rs_i23;
+    input fabric_direct2_do_rs_i24;
+    input fabric_direct2_do_rs_i3;
+    input fabric_direct2_do_rs_i4;
+    input fabric_direct2_do_rs_i5;
+    input fabric_direct2_do_rs_i6;
+    input fabric_direct2_do_rs_i7;
+    input fabric_direct2_do_rs_i8;
+    input fabric_direct2_do_rs_i9;
+    input fabric_direct2_loopback_en_i;
+    input fabric_direct2_loopback_mux_i;
+    input fabric_direct2_oe_ena_i1;
+    input fabric_direct2_oe_ena_i10;
+    input fabric_direct2_oe_ena_i11;
+    input fabric_direct2_oe_ena_i12;
+    input fabric_direct2_oe_ena_i13;
+    input fabric_direct2_oe_ena_i14;
+    input fabric_direct2_oe_ena_i15;
+    input fabric_direct2_oe_ena_i16;
+    input fabric_direct2_oe_ena_i17;
+    input fabric_direct2_oe_ena_i18;
+    input fabric_direct2_oe_ena_i19;
+    input fabric_direct2_oe_ena_i2;
+    input fabric_direct2_oe_ena_i20;
+    input fabric_direct2_oe_ena_i21;
+    input fabric_direct2_oe_ena_i22;
+    input fabric_direct2_oe_ena_i23;
+    input fabric_direct2_oe_ena_i24;
+    input fabric_direct2_oe_ena_i3;
+    input fabric_direct2_oe_ena_i4;
+    input fabric_direct2_oe_ena_i5;
+    input fabric_direct2_oe_ena_i6;
+    input fabric_direct2_oe_ena_i7;
+    input fabric_direct2_oe_ena_i8;
+    input fabric_direct2_oe_ena_i9;
+    input fabric_direct2_oe_i1;
+    input fabric_direct2_oe_i10;
+    input fabric_direct2_oe_i11;
+    input fabric_direct2_oe_i12;
+    input fabric_direct2_oe_i13;
+    input fabric_direct2_oe_i14;
+    input fabric_direct2_oe_i15;
+    input fabric_direct2_oe_i16;
+    input fabric_direct2_oe_i17;
+    input fabric_direct2_oe_i18;
+    input fabric_direct2_oe_i19;
+    input fabric_direct2_oe_i2;
+    input fabric_direct2_oe_i20;
+    input fabric_direct2_oe_i21;
+    input fabric_direct2_oe_i22;
+    input fabric_direct2_oe_i23;
+    input fabric_direct2_oe_i24;
+    input fabric_direct2_oe_i3;
+    input fabric_direct2_oe_i4;
+    input fabric_direct2_oe_i5;
+    input fabric_direct2_oe_i6;
+    input fabric_direct2_oe_i7;
+    input fabric_direct2_oe_i8;
+    input fabric_direct2_oe_i9;
+    input fabric_direct2_oe_rs_i1;
+    input fabric_direct2_oe_rs_i10;
+    input fabric_direct2_oe_rs_i11;
+    input fabric_direct2_oe_rs_i12;
+    input fabric_direct2_oe_rs_i13;
+    input fabric_direct2_oe_rs_i14;
+    input fabric_direct2_oe_rs_i15;
+    input fabric_direct2_oe_rs_i16;
+    input fabric_direct2_oe_rs_i17;
+    input fabric_direct2_oe_rs_i18;
+    input fabric_direct2_oe_rs_i19;
+    input fabric_direct2_oe_rs_i2;
+    input fabric_direct2_oe_rs_i20;
+    input fabric_direct2_oe_rs_i21;
+    input fabric_direct2_oe_rs_i22;
+    input fabric_direct2_oe_rs_i23;
+    input fabric_direct2_oe_rs_i24;
+    input fabric_direct2_oe_rs_i3;
+    input fabric_direct2_oe_rs_i4;
+    input fabric_direct2_oe_rs_i5;
+    input fabric_direct2_oe_rs_i6;
+    input fabric_direct2_oe_rs_i7;
+    input fabric_direct2_oe_rs_i8;
+    input fabric_direct2_oe_rs_i9;
+    input fabric_direct2_scan_en_i;
+    input fabric_direct_data_i1;
+    input fabric_direct_data_i10;
+    input fabric_direct_data_i11;
+    input fabric_direct_data_i12;
+    input fabric_direct_data_i13;
+    input fabric_direct_data_i14;
+    input fabric_direct_data_i15;
+    input fabric_direct_data_i16;
+    input fabric_direct_data_i17;
+    input fabric_direct_data_i18;
+    input fabric_direct_data_i19;
+    input fabric_direct_data_i2;
+    input fabric_direct_data_i20;
+    input fabric_direct_data_i21;
+    input fabric_direct_data_i22;
+    input fabric_direct_data_i23;
+    input fabric_direct_data_i24;
+    input fabric_direct_data_i25;
+    input fabric_direct_data_i26;
+    input fabric_direct_data_i27;
+    input fabric_direct_data_i28;
+    input fabric_direct_data_i29;
+    input fabric_direct_data_i3;
+    input fabric_direct_data_i30;
+    input fabric_direct_data_i31;
+    input fabric_direct_data_i32;
+    input fabric_direct_data_i4;
+    input fabric_direct_data_i5;
+    input fabric_direct_data_i6;
+    input fabric_direct_data_i7;
+    input fabric_direct_data_i8;
+    input fabric_direct_data_i9;
+    output fabric_direct_data_o1;
+    output fabric_direct_data_o10;
+    output fabric_direct_data_o11;
+    output fabric_direct_data_o12;
+    output fabric_direct_data_o13;
+    output fabric_direct_data_o14;
+    output fabric_direct_data_o15;
+    output fabric_direct_data_o16;
+    output fabric_direct_data_o17;
+    output fabric_direct_data_o18;
+    output fabric_direct_data_o19;
+    output fabric_direct_data_o2;
+    output fabric_direct_data_o20;
+    output fabric_direct_data_o21;
+    output fabric_direct_data_o22;
+    output fabric_direct_data_o23;
+    output fabric_direct_data_o24;
+    output fabric_direct_data_o25;
+    output fabric_direct_data_o26;
+    output fabric_direct_data_o27;
+    output fabric_direct_data_o28;
+    output fabric_direct_data_o29;
+    output fabric_direct_data_o3;
+    output fabric_direct_data_o30;
+    output fabric_direct_data_o31;
+    output fabric_direct_data_o32;
+    output fabric_direct_data_o4;
+    output fabric_direct_data_o5;
+    output fabric_direct_data_o6;
+    output fabric_direct_data_o7;
+    output fabric_direct_data_o8;
+    output fabric_direct_data_o9;
+    input fabric_enable_TMR_i1;
+    input fabric_enable_TMR_i2;
+    input fabric_enable_TMR_i3;
+    output fabric_flag_ready_TMR_o1;
+    output fabric_flag_ready_TMR_o2;
+    output fabric_flag_ready_TMR_o3;
+    output fabric_flag_trigger0_o;
+    output fabric_flag_trigger1_o;
+    input fabric_io_in_i1;
+    input fabric_io_in_i10;
+    input fabric_io_in_i11;
+    input fabric_io_in_i12;
+    input fabric_io_in_i13;
+    input fabric_io_in_i14;
+    input fabric_io_in_i15;
+    input fabric_io_in_i16;
+    input fabric_io_in_i17;
+    input fabric_io_in_i18;
+    input fabric_io_in_i19;
+    input fabric_io_in_i2;
+    input fabric_io_in_i20;
+    input fabric_io_in_i21;
+    input fabric_io_in_i22;
+    input fabric_io_in_i23;
+    input fabric_io_in_i24;
+    input fabric_io_in_i25;
+    input fabric_io_in_i26;
+    input fabric_io_in_i27;
+    input fabric_io_in_i28;
+    input fabric_io_in_i29;
+    input fabric_io_in_i3;
+    input fabric_io_in_i30;
+    input fabric_io_in_i31;
+    input fabric_io_in_i32;
+    input fabric_io_in_i33;
+    input fabric_io_in_i34;
+    input fabric_io_in_i35;
+    input fabric_io_in_i4;
+    input fabric_io_in_i5;
+    input fabric_io_in_i6;
+    input fabric_io_in_i7;
+    input fabric_io_in_i8;
+    input fabric_io_in_i9;
+    input fabric_io_oe_i1;
+    input fabric_io_oe_i10;
+    input fabric_io_oe_i11;
+    input fabric_io_oe_i12;
+    input fabric_io_oe_i13;
+    input fabric_io_oe_i14;
+    input fabric_io_oe_i15;
+    input fabric_io_oe_i16;
+    input fabric_io_oe_i17;
+    input fabric_io_oe_i18;
+    input fabric_io_oe_i19;
+    input fabric_io_oe_i2;
+    input fabric_io_oe_i20;
+    input fabric_io_oe_i21;
+    input fabric_io_oe_i22;
+    input fabric_io_oe_i23;
+    input fabric_io_oe_i24;
+    input fabric_io_oe_i25;
+    input fabric_io_oe_i26;
+    input fabric_io_oe_i27;
+    input fabric_io_oe_i28;
+    input fabric_io_oe_i29;
+    input fabric_io_oe_i3;
+    input fabric_io_oe_i30;
+    input fabric_io_oe_i31;
+    input fabric_io_oe_i32;
+    input fabric_io_oe_i33;
+    input fabric_io_oe_i34;
+    input fabric_io_oe_i35;
+    input fabric_io_oe_i4;
+    input fabric_io_oe_i5;
+    input fabric_io_oe_i6;
+    input fabric_io_oe_i7;
+    input fabric_io_oe_i8;
+    input fabric_io_oe_i9;
+    output fabric_io_out_o1;
+    output fabric_io_out_o10;
+    output fabric_io_out_o11;
+    output fabric_io_out_o12;
+    output fabric_io_out_o13;
+    output fabric_io_out_o14;
+    output fabric_io_out_o15;
+    output fabric_io_out_o16;
+    output fabric_io_out_o17;
+    output fabric_io_out_o18;
+    output fabric_io_out_o19;
+    output fabric_io_out_o2;
+    output fabric_io_out_o20;
+    output fabric_io_out_o21;
+    output fabric_io_out_o22;
+    output fabric_io_out_o23;
+    output fabric_io_out_o24;
+    output fabric_io_out_o25;
+    output fabric_io_out_o26;
+    output fabric_io_out_o27;
+    output fabric_io_out_o28;
+    output fabric_io_out_o29;
+    output fabric_io_out_o3;
+    output fabric_io_out_o30;
+    output fabric_io_out_o31;
+    output fabric_io_out_o32;
+    output fabric_io_out_o33;
+    output fabric_io_out_o34;
+    output fabric_io_out_o35;
+    output fabric_io_out_o4;
+    output fabric_io_out_o5;
+    output fabric_io_out_o6;
+    output fabric_io_out_o7;
+    output fabric_io_out_o8;
+    output fabric_io_out_o9;
+    output fabric_jtag_tck_o;
+    output fabric_jtag_tdi_o;
+    input fabric_jtag_tdo_usr1_i;
+    input fabric_jtag_tdo_usr2_i;
+    output fabric_jtag_tms_o;
+    output fabric_jtag_trst_n_o;
+    output fabric_jtag_usr1_o;
+    output fabric_jtag_usr2_o;
+    input fabric_lowskew_i1;
+    input fabric_lowskew_i10;
+    input fabric_lowskew_i11;
+    input fabric_lowskew_i12;
+    input fabric_lowskew_i13;
+    input fabric_lowskew_i14;
+    input fabric_lowskew_i15;
+    input fabric_lowskew_i16;
+    input fabric_lowskew_i17;
+    input fabric_lowskew_i18;
+    input fabric_lowskew_i19;
+    input fabric_lowskew_i2;
+    input fabric_lowskew_i20;
+    input fabric_lowskew_i21;
+    input fabric_lowskew_i22;
+    input fabric_lowskew_i23;
+    input fabric_lowskew_i24;
+    input fabric_lowskew_i25;
+    input fabric_lowskew_i26;
+    input fabric_lowskew_i27;
+    input fabric_lowskew_i28;
+    input fabric_lowskew_i29;
+    input fabric_lowskew_i3;
+    input fabric_lowskew_i30;
+    input fabric_lowskew_i31;
+    input fabric_lowskew_i32;
+    input fabric_lowskew_i33;
+    input fabric_lowskew_i34;
+    input fabric_lowskew_i35;
+    input fabric_lowskew_i36;
+    input fabric_lowskew_i37;
+    input fabric_lowskew_i38;
+    input fabric_lowskew_i39;
+    input fabric_lowskew_i4;
+    input fabric_lowskew_i40;
+    input fabric_lowskew_i5;
+    input fabric_lowskew_i6;
+    input fabric_lowskew_i7;
+    input fabric_lowskew_i8;
+    input fabric_lowskew_i9;
+    output fabric_lowskew_o1;
+    output fabric_lowskew_o2;
+    output fabric_lowskew_o3;
+    output fabric_lowskew_o4;
+    output fabric_lowskew_o5;
+    output fabric_lowskew_o6;
+    input fabric_mrepair_bend_i;
+    output fabric_mrepair_bist_mode_o;
+    output fabric_mrepair_bypass_o;
+    output fabric_mrepair_chip_status_o1;
+    output fabric_mrepair_chip_status_o10;
+    output fabric_mrepair_chip_status_o11;
+    output fabric_mrepair_chip_status_o12;
+    output fabric_mrepair_chip_status_o13;
+    output fabric_mrepair_chip_status_o14;
+    output fabric_mrepair_chip_status_o15;
+    output fabric_mrepair_chip_status_o16;
+    output fabric_mrepair_chip_status_o17;
+    output fabric_mrepair_chip_status_o18;
+    output fabric_mrepair_chip_status_o19;
+    output fabric_mrepair_chip_status_o2;
+    output fabric_mrepair_chip_status_o20;
+    output fabric_mrepair_chip_status_o21;
+    output fabric_mrepair_chip_status_o22;
+    output fabric_mrepair_chip_status_o23;
+    output fabric_mrepair_chip_status_o24;
+    output fabric_mrepair_chip_status_o25;
+    output fabric_mrepair_chip_status_o26;
+    output fabric_mrepair_chip_status_o27;
+    output fabric_mrepair_chip_status_o28;
+    output fabric_mrepair_chip_status_o29;
+    output fabric_mrepair_chip_status_o3;
+    output fabric_mrepair_chip_status_o30;
+    output fabric_mrepair_chip_status_o31;
+    output fabric_mrepair_chip_status_o32;
+    output fabric_mrepair_chip_status_o33;
+    output fabric_mrepair_chip_status_o34;
+    output fabric_mrepair_chip_status_o35;
+    output fabric_mrepair_chip_status_o36;
+    output fabric_mrepair_chip_status_o37;
+    output fabric_mrepair_chip_status_o38;
+    output fabric_mrepair_chip_status_o39;
+    output fabric_mrepair_chip_status_o4;
+    output fabric_mrepair_chip_status_o40;
+    output fabric_mrepair_chip_status_o41;
+    output fabric_mrepair_chip_status_o42;
+    output fabric_mrepair_chip_status_o43;
+    output fabric_mrepair_chip_status_o44;
+    output fabric_mrepair_chip_status_o45;
+    output fabric_mrepair_chip_status_o46;
+    output fabric_mrepair_chip_status_o47;
+    output fabric_mrepair_chip_status_o48;
+    output fabric_mrepair_chip_status_o49;
+    output fabric_mrepair_chip_status_o5;
+    output fabric_mrepair_chip_status_o50;
+    output fabric_mrepair_chip_status_o51;
+    output fabric_mrepair_chip_status_o52;
+    output fabric_mrepair_chip_status_o53;
+    output fabric_mrepair_chip_status_o54;
+    output fabric_mrepair_chip_status_o55;
+    output fabric_mrepair_chip_status_o56;
+    output fabric_mrepair_chip_status_o57;
+    output fabric_mrepair_chip_status_o58;
+    output fabric_mrepair_chip_status_o59;
+    output fabric_mrepair_chip_status_o6;
+    output fabric_mrepair_chip_status_o60;
+    output fabric_mrepair_chip_status_o61;
+    output fabric_mrepair_chip_status_o62;
+    output fabric_mrepair_chip_status_o63;
+    output fabric_mrepair_chip_status_o64;
+    output fabric_mrepair_chip_status_o65;
+    output fabric_mrepair_chip_status_o66;
+    output fabric_mrepair_chip_status_o67;
+    output fabric_mrepair_chip_status_o68;
+    output fabric_mrepair_chip_status_o69;
+    output fabric_mrepair_chip_status_o7;
+    output fabric_mrepair_chip_status_o70;
+    output fabric_mrepair_chip_status_o71;
+    output fabric_mrepair_chip_status_o72;
+    output fabric_mrepair_chip_status_o73;
+    output fabric_mrepair_chip_status_o74;
+    output fabric_mrepair_chip_status_o75;
+    output fabric_mrepair_chip_status_o76;
+    output fabric_mrepair_chip_status_o77;
+    output fabric_mrepair_chip_status_o78;
+    output fabric_mrepair_chip_status_o8;
+    output fabric_mrepair_chip_status_o9;
+    input fabric_mrepair_cke_force_i;
+    input fabric_mrepair_cke_i;
+    input fabric_mrepair_clk_i;
+    input fabric_mrepair_data_from_bist_i1;
+    input fabric_mrepair_data_from_bist_i10;
+    input fabric_mrepair_data_from_bist_i11;
+    input fabric_mrepair_data_from_bist_i12;
+    input fabric_mrepair_data_from_bist_i13;
+    input fabric_mrepair_data_from_bist_i14;
+    input fabric_mrepair_data_from_bist_i15;
+    input fabric_mrepair_data_from_bist_i16;
+    input fabric_mrepair_data_from_bist_i17;
+    input fabric_mrepair_data_from_bist_i18;
+    input fabric_mrepair_data_from_bist_i19;
+    input fabric_mrepair_data_from_bist_i2;
+    input fabric_mrepair_data_from_bist_i20;
+    input fabric_mrepair_data_from_bist_i21;
+    input fabric_mrepair_data_from_bist_i22;
+    input fabric_mrepair_data_from_bist_i23;
+    input fabric_mrepair_data_from_bist_i24;
+    input fabric_mrepair_data_from_bist_i25;
+    input fabric_mrepair_data_from_bist_i26;
+    input fabric_mrepair_data_from_bist_i3;
+    input fabric_mrepair_data_from_bist_i4;
+    input fabric_mrepair_data_from_bist_i5;
+    input fabric_mrepair_data_from_bist_i6;
+    input fabric_mrepair_data_from_bist_i7;
+    input fabric_mrepair_data_from_bist_i8;
+    input fabric_mrepair_data_from_bist_i9;
+    input fabric_mrepair_data_from_system_i;
+    input fabric_mrepair_data_shift_en_i;
+    output fabric_mrepair_data_to_bist_o1;
+    output fabric_mrepair_data_to_bist_o10;
+    output fabric_mrepair_data_to_bist_o11;
+    output fabric_mrepair_data_to_bist_o12;
+    output fabric_mrepair_data_to_bist_o13;
+    output fabric_mrepair_data_to_bist_o14;
+    output fabric_mrepair_data_to_bist_o15;
+    output fabric_mrepair_data_to_bist_o16;
+    output fabric_mrepair_data_to_bist_o17;
+    output fabric_mrepair_data_to_bist_o18;
+    output fabric_mrepair_data_to_bist_o19;
+    output fabric_mrepair_data_to_bist_o2;
+    output fabric_mrepair_data_to_bist_o20;
+    output fabric_mrepair_data_to_bist_o21;
+    output fabric_mrepair_data_to_bist_o22;
+    output fabric_mrepair_data_to_bist_o23;
+    output fabric_mrepair_data_to_bist_o24;
+    output fabric_mrepair_data_to_bist_o25;
+    output fabric_mrepair_data_to_bist_o26;
+    output fabric_mrepair_data_to_bist_o3;
+    output fabric_mrepair_data_to_bist_o4;
+    output fabric_mrepair_data_to_bist_o5;
+    output fabric_mrepair_data_to_bist_o6;
+    output fabric_mrepair_data_to_bist_o7;
+    output fabric_mrepair_data_to_bist_o8;
+    output fabric_mrepair_data_to_bist_o9;
+    output fabric_mrepair_data_to_system_o;
+    output fabric_mrepair_decoder_init_ready_o;
+    input fabric_mrepair_end_encoding_i;
+    output fabric_mrepair_fuse_ack_o;
+    input fabric_mrepair_fuse_add_i1;
+    input fabric_mrepair_fuse_add_i2;
+    input fabric_mrepair_fuse_add_i3;
+    input fabric_mrepair_fuse_add_i4;
+    input fabric_mrepair_fuse_add_i5;
+    input fabric_mrepair_fuse_add_i6;
+    input fabric_mrepair_fuse_add_i7;
+    output fabric_mrepair_fuse_bbad_o;
+    output fabric_mrepair_fuse_bend1_o;
+    output fabric_mrepair_fuse_bend2_o;
+    output fabric_mrepair_fuse_bist1fail_o1;
+    output fabric_mrepair_fuse_bist1fail_o2;
+    output fabric_mrepair_fuse_bist1fail_o3;
+    output fabric_mrepair_fuse_bist1fail_o4;
+    output fabric_mrepair_fuse_bist1fail_o5;
+    output fabric_mrepair_fuse_bist1fail_o6;
+    output fabric_mrepair_fuse_bist1fail_o7;
+    output fabric_mrepair_fuse_bist1fail_o8;
+    output fabric_mrepair_fuse_bist2fail_o1;
+    output fabric_mrepair_fuse_bist2fail_o2;
+    output fabric_mrepair_fuse_bist2fail_o3;
+    output fabric_mrepair_fuse_bist2fail_o4;
+    output fabric_mrepair_fuse_bist2fail_o5;
+    output fabric_mrepair_fuse_bist2fail_o6;
+    output fabric_mrepair_fuse_bist2fail_o7;
+    input fabric_mrepair_fuse_bistmode_i;
+    output fabric_mrepair_fuse_calibrated_o;
+    output fabric_mrepair_fuse_ded_o;
+    input fabric_mrepair_fuse_din_i1;
+    input fabric_mrepair_fuse_din_i10;
+    input fabric_mrepair_fuse_din_i11;
+    input fabric_mrepair_fuse_din_i12;
+    input fabric_mrepair_fuse_din_i13;
+    input fabric_mrepair_fuse_din_i14;
+    input fabric_mrepair_fuse_din_i15;
+    input fabric_mrepair_fuse_din_i16;
+    input fabric_mrepair_fuse_din_i17;
+    input fabric_mrepair_fuse_din_i18;
+    input fabric_mrepair_fuse_din_i19;
+    input fabric_mrepair_fuse_din_i2;
+    input fabric_mrepair_fuse_din_i20;
+    input fabric_mrepair_fuse_din_i21;
+    input fabric_mrepair_fuse_din_i22;
+    input fabric_mrepair_fuse_din_i23;
+    input fabric_mrepair_fuse_din_i24;
+    input fabric_mrepair_fuse_din_i25;
+    input fabric_mrepair_fuse_din_i26;
+    input fabric_mrepair_fuse_din_i27;
+    input fabric_mrepair_fuse_din_i28;
+    input fabric_mrepair_fuse_din_i29;
+    input fabric_mrepair_fuse_din_i3;
+    input fabric_mrepair_fuse_din_i30;
+    input fabric_mrepair_fuse_din_i31;
+    input fabric_mrepair_fuse_din_i32;
+    input fabric_mrepair_fuse_din_i33;
+    input fabric_mrepair_fuse_din_i34;
+    input fabric_mrepair_fuse_din_i35;
+    input fabric_mrepair_fuse_din_i36;
+    input fabric_mrepair_fuse_din_i37;
+    input fabric_mrepair_fuse_din_i38;
+    input fabric_mrepair_fuse_din_i39;
+    input fabric_mrepair_fuse_din_i4;
+    input fabric_mrepair_fuse_din_i5;
+    input fabric_mrepair_fuse_din_i6;
+    input fabric_mrepair_fuse_din_i7;
+    input fabric_mrepair_fuse_din_i8;
+    input fabric_mrepair_fuse_din_i9;
+    input fabric_mrepair_fuse_disturbchecked_i;
+    output fabric_mrepair_fuse_disturbed_o;
+    output fabric_mrepair_fuse_dout_o1;
+    output fabric_mrepair_fuse_dout_o10;
+    output fabric_mrepair_fuse_dout_o11;
+    output fabric_mrepair_fuse_dout_o12;
+    output fabric_mrepair_fuse_dout_o13;
+    output fabric_mrepair_fuse_dout_o14;
+    output fabric_mrepair_fuse_dout_o15;
+    output fabric_mrepair_fuse_dout_o16;
+    output fabric_mrepair_fuse_dout_o17;
+    output fabric_mrepair_fuse_dout_o18;
+    output fabric_mrepair_fuse_dout_o19;
+    output fabric_mrepair_fuse_dout_o2;
+    output fabric_mrepair_fuse_dout_o20;
+    output fabric_mrepair_fuse_dout_o21;
+    output fabric_mrepair_fuse_dout_o22;
+    output fabric_mrepair_fuse_dout_o23;
+    output fabric_mrepair_fuse_dout_o24;
+    output fabric_mrepair_fuse_dout_o25;
+    output fabric_mrepair_fuse_dout_o26;
+    output fabric_mrepair_fuse_dout_o27;
+    output fabric_mrepair_fuse_dout_o28;
+    output fabric_mrepair_fuse_dout_o29;
+    output fabric_mrepair_fuse_dout_o3;
+    output fabric_mrepair_fuse_dout_o30;
+    output fabric_mrepair_fuse_dout_o31;
+    output fabric_mrepair_fuse_dout_o32;
+    output fabric_mrepair_fuse_dout_o33;
+    output fabric_mrepair_fuse_dout_o34;
+    output fabric_mrepair_fuse_dout_o35;
+    output fabric_mrepair_fuse_dout_o36;
+    output fabric_mrepair_fuse_dout_o37;
+    output fabric_mrepair_fuse_dout_o38;
+    output fabric_mrepair_fuse_dout_o39;
+    output fabric_mrepair_fuse_dout_o4;
+    output fabric_mrepair_fuse_dout_o40;
+    output fabric_mrepair_fuse_dout_o41;
+    output fabric_mrepair_fuse_dout_o5;
+    output fabric_mrepair_fuse_dout_o6;
+    output fabric_mrepair_fuse_dout_o7;
+    output fabric_mrepair_fuse_dout_o8;
+    output fabric_mrepair_fuse_dout_o9;
+    input fabric_mrepair_fuse_eccbypass_i;
+    output fabric_mrepair_fuse_flagstate_o1;
+    output fabric_mrepair_fuse_flagstate_o2;
+    output fabric_mrepair_fuse_flagstate_o3;
+    output fabric_mrepair_fuse_flagstate_o4;
+    output fabric_mrepair_fuse_locked_o;
+    input fabric_mrepair_fuse_pdn_i;
+    output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o;
+    input fabric_mrepair_fuse_prgwidth_i1;
+    input fabric_mrepair_fuse_prgwidth_i2;
+    input fabric_mrepair_fuse_prgwidth_i3;
+    input fabric_mrepair_fuse_prog_i;
+    output fabric_mrepair_fuse_progfail_o;
+    output fabric_mrepair_fuse_pwok_o;
+    input fabric_mrepair_fuse_rbact1_i;
+    input fabric_mrepair_fuse_rbact2_i;
+    input fabric_mrepair_fuse_read_i;
+    output fabric_mrepair_fuse_ready_o;
+    input fabric_mrepair_fuse_redbypass_i;
+    output fabric_mrepair_fuse_sec_o;
+    output fabric_mrepair_fuse_startword_o1;
+    output fabric_mrepair_fuse_startword_o10;
+    output fabric_mrepair_fuse_startword_o11;
+    output fabric_mrepair_fuse_startword_o12;
+    output fabric_mrepair_fuse_startword_o13;
+    output fabric_mrepair_fuse_startword_o14;
+    output fabric_mrepair_fuse_startword_o15;
+    output fabric_mrepair_fuse_startword_o16;
+    output fabric_mrepair_fuse_startword_o2;
+    output fabric_mrepair_fuse_startword_o3;
+    output fabric_mrepair_fuse_startword_o4;
+    output fabric_mrepair_fuse_startword_o5;
+    output fabric_mrepair_fuse_startword_o6;
+    output fabric_mrepair_fuse_startword_o7;
+    output fabric_mrepair_fuse_startword_o8;
+    output fabric_mrepair_fuse_startword_o9;
+    output fabric_mrepair_fuse_status_o1;
+    output fabric_mrepair_fuse_status_o2;
+    output fabric_mrepair_fuse_status_o3;
+    input fabric_mrepair_fuse_suppadd_i;
+    input fabric_mrepair_fuse_tm_i;
+    input fabric_mrepair_fuse_tst_scanin_i1;
+    input fabric_mrepair_fuse_tst_scanin_i2;
+    input fabric_mrepair_fuse_tst_scanin_i3;
+    input fabric_mrepair_fuse_tst_scanin_i4;
+    input fabric_mrepair_fuse_tst_scanin_i5;
+    input fabric_mrepair_fuse_tstscanenable_i;
+    output fabric_mrepair_fuse_tstscanout_o1;
+    output fabric_mrepair_fuse_tstscanout_o2;
+    output fabric_mrepair_fuse_tstscanout_o3;
+    output fabric_mrepair_fuse_tstscanout_o4;
+    output fabric_mrepair_fuse_tstscanout_o5;
+    output fabric_mrepair_fuse_wlromout_o1;
+    output fabric_mrepair_fuse_wlromout_o10;
+    output fabric_mrepair_fuse_wlromout_o2;
+    output fabric_mrepair_fuse_wlromout_o3;
+    output fabric_mrepair_fuse_wlromout_o4;
+    output fabric_mrepair_fuse_wlromout_o5;
+    output fabric_mrepair_fuse_wlromout_o6;
+    output fabric_mrepair_fuse_wlromout_o7;
+    output fabric_mrepair_fuse_wlromout_o8;
+    output fabric_mrepair_fuse_wlromout_o9;
+    input fabric_mrepair_fuse_wordlock_i;
+    input fabric_mrepair_global_bbad_i;
+    output fabric_mrepair_global_chip_status_o1;
+    output fabric_mrepair_global_chip_status_o2;
+    output fabric_mrepair_global_chip_status_o3;
+    input fabric_mrepair_global_repairable_i;
+    input fabric_mrepair_initn_i;
+    output fabric_mrepair_mem_atpg_mode_o;
+    output fabric_mrepair_mem_type_sel_o1;
+    output fabric_mrepair_mem_type_sel_o2;
+    output fabric_mrepair_mem_type_sel_o3;
+    output fabric_mrepair_mem_type_sel_o4;
+    output fabric_mrepair_mem_type_sel_o5;
+    output fabric_mrepair_memsafe_o;
+    input fabric_mrepair_mode_i1;
+    input fabric_mrepair_mode_i2;
+    input fabric_mrepair_mode_i3;
+    input fabric_mrepair_mode_i4;
+    output fabric_mrepair_mode_sel_o1;
+    output fabric_mrepair_mode_sel_o2;
+    output fabric_mrepair_mode_sel_o3;
+    output fabric_mrepair_mode_sel_o4;
+    input fabric_mrepair_pd_active_i1;
+    input fabric_mrepair_pd_active_i10;
+    input fabric_mrepair_pd_active_i11;
+    input fabric_mrepair_pd_active_i12;
+    input fabric_mrepair_pd_active_i13;
+    input fabric_mrepair_pd_active_i14;
+    input fabric_mrepair_pd_active_i15;
+    input fabric_mrepair_pd_active_i16;
+    input fabric_mrepair_pd_active_i17;
+    input fabric_mrepair_pd_active_i18;
+    input fabric_mrepair_pd_active_i19;
+    input fabric_mrepair_pd_active_i2;
+    input fabric_mrepair_pd_active_i20;
+    input fabric_mrepair_pd_active_i21;
+    input fabric_mrepair_pd_active_i22;
+    input fabric_mrepair_pd_active_i23;
+    input fabric_mrepair_pd_active_i24;
+    input fabric_mrepair_pd_active_i25;
+    input fabric_mrepair_pd_active_i26;
+    input fabric_mrepair_pd_active_i3;
+    input fabric_mrepair_pd_active_i4;
+    input fabric_mrepair_pd_active_i5;
+    input fabric_mrepair_pd_active_i6;
+    input fabric_mrepair_pd_active_i7;
+    input fabric_mrepair_pd_active_i8;
+    input fabric_mrepair_pd_active_i9;
+    output fabric_mrepair_pd_ready_o1;
+    output fabric_mrepair_pd_ready_o10;
+    output fabric_mrepair_pd_ready_o11;
+    output fabric_mrepair_pd_ready_o12;
+    output fabric_mrepair_pd_ready_o13;
+    output fabric_mrepair_pd_ready_o14;
+    output fabric_mrepair_pd_ready_o15;
+    output fabric_mrepair_pd_ready_o16;
+    output fabric_mrepair_pd_ready_o17;
+    output fabric_mrepair_pd_ready_o18;
+    output fabric_mrepair_pd_ready_o19;
+    output fabric_mrepair_pd_ready_o2;
+    output fabric_mrepair_pd_ready_o20;
+    output fabric_mrepair_pd_ready_o21;
+    output fabric_mrepair_pd_ready_o22;
+    output fabric_mrepair_pd_ready_o23;
+    output fabric_mrepair_pd_ready_o24;
+    output fabric_mrepair_pd_ready_o25;
+    output fabric_mrepair_pd_ready_o26;
+    output fabric_mrepair_pd_ready_o3;
+    output fabric_mrepair_pd_ready_o4;
+    output fabric_mrepair_pd_ready_o5;
+    output fabric_mrepair_pd_ready_o6;
+    output fabric_mrepair_pd_ready_o7;
+    output fabric_mrepair_pd_ready_o8;
+    output fabric_mrepair_pd_ready_o9;
+    input fabric_mrepair_por_i;
+    input fabric_mrepair_rst_n_i;
+    input fabric_mrepair_shift_en_i1;
+    input fabric_mrepair_shift_en_i10;
+    input fabric_mrepair_shift_en_i11;
+    input fabric_mrepair_shift_en_i12;
+    input fabric_mrepair_shift_en_i13;
+    input fabric_mrepair_shift_en_i14;
+    input fabric_mrepair_shift_en_i15;
+    input fabric_mrepair_shift_en_i16;
+    input fabric_mrepair_shift_en_i17;
+    input fabric_mrepair_shift_en_i18;
+    input fabric_mrepair_shift_en_i19;
+    input fabric_mrepair_shift_en_i2;
+    input fabric_mrepair_shift_en_i20;
+    input fabric_mrepair_shift_en_i21;
+    input fabric_mrepair_shift_en_i22;
+    input fabric_mrepair_shift_en_i23;
+    input fabric_mrepair_shift_en_i24;
+    input fabric_mrepair_shift_en_i25;
+    input fabric_mrepair_shift_en_i26;
+    input fabric_mrepair_shift_en_i3;
+    input fabric_mrepair_shift_en_i4;
+    input fabric_mrepair_shift_en_i5;
+    input fabric_mrepair_shift_en_i6;
+    input fabric_mrepair_shift_en_i7;
+    input fabric_mrepair_shift_en_i8;
+    input fabric_mrepair_shift_en_i9;
+    output fabric_mrepair_shift_en_to_bist_o1;
+    output fabric_mrepair_shift_en_to_bist_o10;
+    output fabric_mrepair_shift_en_to_bist_o11;
+    output fabric_mrepair_shift_en_to_bist_o12;
+    output fabric_mrepair_shift_en_to_bist_o13;
+    output fabric_mrepair_shift_en_to_bist_o14;
+    output fabric_mrepair_shift_en_to_bist_o15;
+    output fabric_mrepair_shift_en_to_bist_o16;
+    output fabric_mrepair_shift_en_to_bist_o17;
+    output fabric_mrepair_shift_en_to_bist_o18;
+    output fabric_mrepair_shift_en_to_bist_o19;
+    output fabric_mrepair_shift_en_to_bist_o2;
+    output fabric_mrepair_shift_en_to_bist_o20;
+    output fabric_mrepair_shift_en_to_bist_o21;
+    output fabric_mrepair_shift_en_to_bist_o22;
+    output fabric_mrepair_shift_en_to_bist_o23;
+    output fabric_mrepair_shift_en_to_bist_o24;
+    output fabric_mrepair_shift_en_to_bist_o25;
+    output fabric_mrepair_shift_en_to_bist_o26;
+    output fabric_mrepair_shift_en_to_bist_o3;
+    output fabric_mrepair_shift_en_to_bist_o4;
+    output fabric_mrepair_shift_en_to_bist_o5;
+    output fabric_mrepair_shift_en_to_bist_o6;
+    output fabric_mrepair_shift_en_to_bist_o7;
+    output fabric_mrepair_shift_en_to_bist_o8;
+    output fabric_mrepair_shift_en_to_bist_o9;
+    input fabric_mrepair_sif_load_en_i1;
+    input fabric_mrepair_sif_load_en_i10;
+    input fabric_mrepair_sif_load_en_i11;
+    input fabric_mrepair_sif_load_en_i12;
+    input fabric_mrepair_sif_load_en_i13;
+    input fabric_mrepair_sif_load_en_i14;
+    input fabric_mrepair_sif_load_en_i15;
+    input fabric_mrepair_sif_load_en_i16;
+    input fabric_mrepair_sif_load_en_i17;
+    input fabric_mrepair_sif_load_en_i18;
+    input fabric_mrepair_sif_load_en_i19;
+    input fabric_mrepair_sif_load_en_i2;
+    input fabric_mrepair_sif_load_en_i20;
+    input fabric_mrepair_sif_load_en_i21;
+    input fabric_mrepair_sif_load_en_i22;
+    input fabric_mrepair_sif_load_en_i23;
+    input fabric_mrepair_sif_load_en_i24;
+    input fabric_mrepair_sif_load_en_i25;
+    input fabric_mrepair_sif_load_en_i26;
+    input fabric_mrepair_sif_load_en_i3;
+    input fabric_mrepair_sif_load_en_i4;
+    input fabric_mrepair_sif_load_en_i5;
+    input fabric_mrepair_sif_load_en_i6;
+    input fabric_mrepair_sif_load_en_i7;
+    input fabric_mrepair_sif_load_en_i8;
+    input fabric_mrepair_sif_load_en_i9;
+    output fabric_mrepair_sif_load_en_to_bist_o1;
+    output fabric_mrepair_sif_load_en_to_bist_o10;
+    output fabric_mrepair_sif_load_en_to_bist_o11;
+    output fabric_mrepair_sif_load_en_to_bist_o12;
+    output fabric_mrepair_sif_load_en_to_bist_o13;
+    output fabric_mrepair_sif_load_en_to_bist_o14;
+    output fabric_mrepair_sif_load_en_to_bist_o15;
+    output fabric_mrepair_sif_load_en_to_bist_o16;
+    output fabric_mrepair_sif_load_en_to_bist_o17;
+    output fabric_mrepair_sif_load_en_to_bist_o18;
+    output fabric_mrepair_sif_load_en_to_bist_o19;
+    output fabric_mrepair_sif_load_en_to_bist_o2;
+    output fabric_mrepair_sif_load_en_to_bist_o20;
+    output fabric_mrepair_sif_load_en_to_bist_o21;
+    output fabric_mrepair_sif_load_en_to_bist_o22;
+    output fabric_mrepair_sif_load_en_to_bist_o23;
+    output fabric_mrepair_sif_load_en_to_bist_o24;
+    output fabric_mrepair_sif_load_en_to_bist_o25;
+    output fabric_mrepair_sif_load_en_to_bist_o26;
+    output fabric_mrepair_sif_load_en_to_bist_o3;
+    output fabric_mrepair_sif_load_en_to_bist_o4;
+    output fabric_mrepair_sif_load_en_to_bist_o5;
+    output fabric_mrepair_sif_load_en_to_bist_o6;
+    output fabric_mrepair_sif_load_en_to_bist_o7;
+    output fabric_mrepair_sif_load_en_to_bist_o8;
+    output fabric_mrepair_sif_load_en_to_bist_o9;
+    input fabric_mrepair_sif_reg_en_i1;
+    input fabric_mrepair_sif_reg_en_i10;
+    input fabric_mrepair_sif_reg_en_i11;
+    input fabric_mrepair_sif_reg_en_i12;
+    input fabric_mrepair_sif_reg_en_i13;
+    input fabric_mrepair_sif_reg_en_i14;
+    input fabric_mrepair_sif_reg_en_i15;
+    input fabric_mrepair_sif_reg_en_i16;
+    input fabric_mrepair_sif_reg_en_i17;
+    input fabric_mrepair_sif_reg_en_i18;
+    input fabric_mrepair_sif_reg_en_i19;
+    input fabric_mrepair_sif_reg_en_i2;
+    input fabric_mrepair_sif_reg_en_i20;
+    input fabric_mrepair_sif_reg_en_i21;
+    input fabric_mrepair_sif_reg_en_i22;
+    input fabric_mrepair_sif_reg_en_i23;
+    input fabric_mrepair_sif_reg_en_i24;
+    input fabric_mrepair_sif_reg_en_i25;
+    input fabric_mrepair_sif_reg_en_i26;
+    input fabric_mrepair_sif_reg_en_i3;
+    input fabric_mrepair_sif_reg_en_i4;
+    input fabric_mrepair_sif_reg_en_i5;
+    input fabric_mrepair_sif_reg_en_i6;
+    input fabric_mrepair_sif_reg_en_i7;
+    input fabric_mrepair_sif_reg_en_i8;
+    input fabric_mrepair_sif_reg_en_i9;
+    output fabric_mrepair_sif_reg_en_to_bist_o1;
+    output fabric_mrepair_sif_reg_en_to_bist_o10;
+    output fabric_mrepair_sif_reg_en_to_bist_o11;
+    output fabric_mrepair_sif_reg_en_to_bist_o12;
+    output fabric_mrepair_sif_reg_en_to_bist_o13;
+    output fabric_mrepair_sif_reg_en_to_bist_o14;
+    output fabric_mrepair_sif_reg_en_to_bist_o15;
+    output fabric_mrepair_sif_reg_en_to_bist_o16;
+    output fabric_mrepair_sif_reg_en_to_bist_o17;
+    output fabric_mrepair_sif_reg_en_to_bist_o18;
+    output fabric_mrepair_sif_reg_en_to_bist_o19;
+    output fabric_mrepair_sif_reg_en_to_bist_o2;
+    output fabric_mrepair_sif_reg_en_to_bist_o20;
+    output fabric_mrepair_sif_reg_en_to_bist_o21;
+    output fabric_mrepair_sif_reg_en_to_bist_o22;
+    output fabric_mrepair_sif_reg_en_to_bist_o23;
+    output fabric_mrepair_sif_reg_en_to_bist_o24;
+    output fabric_mrepair_sif_reg_en_to_bist_o25;
+    output fabric_mrepair_sif_reg_en_to_bist_o26;
+    output fabric_mrepair_sif_reg_en_to_bist_o3;
+    output fabric_mrepair_sif_reg_en_to_bist_o4;
+    output fabric_mrepair_sif_reg_en_to_bist_o5;
+    output fabric_mrepair_sif_reg_en_to_bist_o6;
+    output fabric_mrepair_sif_reg_en_to_bist_o7;
+    output fabric_mrepair_sif_reg_en_to_bist_o8;
+    output fabric_mrepair_sif_reg_en_to_bist_o9;
+    input fabric_mrepair_sif_update_en_i1;
+    input fabric_mrepair_sif_update_en_i10;
+    input fabric_mrepair_sif_update_en_i11;
+    input fabric_mrepair_sif_update_en_i12;
+    input fabric_mrepair_sif_update_en_i13;
+    input fabric_mrepair_sif_update_en_i14;
+    input fabric_mrepair_sif_update_en_i15;
+    input fabric_mrepair_sif_update_en_i16;
+    input fabric_mrepair_sif_update_en_i17;
+    input fabric_mrepair_sif_update_en_i18;
+    input fabric_mrepair_sif_update_en_i19;
+    input fabric_mrepair_sif_update_en_i2;
+    input fabric_mrepair_sif_update_en_i20;
+    input fabric_mrepair_sif_update_en_i21;
+    input fabric_mrepair_sif_update_en_i22;
+    input fabric_mrepair_sif_update_en_i23;
+    input fabric_mrepair_sif_update_en_i24;
+    input fabric_mrepair_sif_update_en_i25;
+    input fabric_mrepair_sif_update_en_i26;
+    input fabric_mrepair_sif_update_en_i3;
+    input fabric_mrepair_sif_update_en_i4;
+    input fabric_mrepair_sif_update_en_i5;
+    input fabric_mrepair_sif_update_en_i6;
+    input fabric_mrepair_sif_update_en_i7;
+    input fabric_mrepair_sif_update_en_i8;
+    input fabric_mrepair_sif_update_en_i9;
+    output fabric_mrepair_sif_update_en_to_bist_o1;
+    output fabric_mrepair_sif_update_en_to_bist_o10;
+    output fabric_mrepair_sif_update_en_to_bist_o11;
+    output fabric_mrepair_sif_update_en_to_bist_o12;
+    output fabric_mrepair_sif_update_en_to_bist_o13;
+    output fabric_mrepair_sif_update_en_to_bist_o14;
+    output fabric_mrepair_sif_update_en_to_bist_o15;
+    output fabric_mrepair_sif_update_en_to_bist_o16;
+    output fabric_mrepair_sif_update_en_to_bist_o17;
+    output fabric_mrepair_sif_update_en_to_bist_o18;
+    output fabric_mrepair_sif_update_en_to_bist_o19;
+    output fabric_mrepair_sif_update_en_to_bist_o2;
+    output fabric_mrepair_sif_update_en_to_bist_o20;
+    output fabric_mrepair_sif_update_en_to_bist_o21;
+    output fabric_mrepair_sif_update_en_to_bist_o22;
+    output fabric_mrepair_sif_update_en_to_bist_o23;
+    output fabric_mrepair_sif_update_en_to_bist_o24;
+    output fabric_mrepair_sif_update_en_to_bist_o25;
+    output fabric_mrepair_sif_update_en_to_bist_o26;
+    output fabric_mrepair_sif_update_en_to_bist_o3;
+    output fabric_mrepair_sif_update_en_to_bist_o4;
+    output fabric_mrepair_sif_update_en_to_bist_o5;
+    output fabric_mrepair_sif_update_en_to_bist_o6;
+    output fabric_mrepair_sif_update_en_to_bist_o7;
+    output fabric_mrepair_sif_update_en_to_bist_o8;
+    output fabric_mrepair_sif_update_en_to_bist_o9;
+    output fabric_mrepair_system_data_from_mem_bist_o1;
+    output fabric_mrepair_system_data_from_mem_bist_o10;
+    output fabric_mrepair_system_data_from_mem_bist_o11;
+    output fabric_mrepair_system_data_from_mem_bist_o12;
+    output fabric_mrepair_system_data_from_mem_bist_o13;
+    output fabric_mrepair_system_data_from_mem_bist_o14;
+    output fabric_mrepair_system_data_from_mem_bist_o15;
+    output fabric_mrepair_system_data_from_mem_bist_o16;
+    output fabric_mrepair_system_data_from_mem_bist_o17;
+    output fabric_mrepair_system_data_from_mem_bist_o18;
+    output fabric_mrepair_system_data_from_mem_bist_o19;
+    output fabric_mrepair_system_data_from_mem_bist_o2;
+    output fabric_mrepair_system_data_from_mem_bist_o20;
+    output fabric_mrepair_system_data_from_mem_bist_o21;
+    output fabric_mrepair_system_data_from_mem_bist_o22;
+    output fabric_mrepair_system_data_from_mem_bist_o23;
+    output fabric_mrepair_system_data_from_mem_bist_o24;
+    output fabric_mrepair_system_data_from_mem_bist_o25;
+    output fabric_mrepair_system_data_from_mem_bist_o26;
+    output fabric_mrepair_system_data_from_mem_bist_o3;
+    output fabric_mrepair_system_data_from_mem_bist_o4;
+    output fabric_mrepair_system_data_from_mem_bist_o5;
+    output fabric_mrepair_system_data_from_mem_bist_o6;
+    output fabric_mrepair_system_data_from_mem_bist_o7;
+    output fabric_mrepair_system_data_from_mem_bist_o8;
+    output fabric_mrepair_system_data_from_mem_bist_o9;
+    input fabric_mrepair_system_data_to_mem_bist_i1;
+    input fabric_mrepair_system_data_to_mem_bist_i10;
+    input fabric_mrepair_system_data_to_mem_bist_i11;
+    input fabric_mrepair_system_data_to_mem_bist_i12;
+    input fabric_mrepair_system_data_to_mem_bist_i13;
+    input fabric_mrepair_system_data_to_mem_bist_i14;
+    input fabric_mrepair_system_data_to_mem_bist_i15;
+    input fabric_mrepair_system_data_to_mem_bist_i16;
+    input fabric_mrepair_system_data_to_mem_bist_i17;
+    input fabric_mrepair_system_data_to_mem_bist_i18;
+    input fabric_mrepair_system_data_to_mem_bist_i19;
+    input fabric_mrepair_system_data_to_mem_bist_i2;
+    input fabric_mrepair_system_data_to_mem_bist_i20;
+    input fabric_mrepair_system_data_to_mem_bist_i21;
+    input fabric_mrepair_system_data_to_mem_bist_i22;
+    input fabric_mrepair_system_data_to_mem_bist_i23;
+    input fabric_mrepair_system_data_to_mem_bist_i24;
+    input fabric_mrepair_system_data_to_mem_bist_i25;
+    input fabric_mrepair_system_data_to_mem_bist_i26;
+    input fabric_mrepair_system_data_to_mem_bist_i3;
+    input fabric_mrepair_system_data_to_mem_bist_i4;
+    input fabric_mrepair_system_data_to_mem_bist_i5;
+    input fabric_mrepair_system_data_to_mem_bist_i6;
+    input fabric_mrepair_system_data_to_mem_bist_i7;
+    input fabric_mrepair_system_data_to_mem_bist_i8;
+    input fabric_mrepair_system_data_to_mem_bist_i9;
+    output fabric_mrepair_system_dataready_o;
+    output fabric_mrepair_test_se_o;
+    input fabric_mrepair_tst_atpg_mrepair_i;
+    output fabric_mrepair_tst_gatedclock_o;
+    input fabric_otp_apb_addr_i1;
+    input fabric_otp_apb_addr_i10;
+    input fabric_otp_apb_addr_i11;
+    input fabric_otp_apb_addr_i12;
+    input fabric_otp_apb_addr_i13;
+    input fabric_otp_apb_addr_i14;
+    input fabric_otp_apb_addr_i15;
+    input fabric_otp_apb_addr_i16;
+    input fabric_otp_apb_addr_i17;
+    input fabric_otp_apb_addr_i18;
+    input fabric_otp_apb_addr_i19;
+    input fabric_otp_apb_addr_i2;
+    input fabric_otp_apb_addr_i20;
+    input fabric_otp_apb_addr_i21;
+    input fabric_otp_apb_addr_i22;
+    input fabric_otp_apb_addr_i23;
+    input fabric_otp_apb_addr_i24;
+    input fabric_otp_apb_addr_i25;
+    input fabric_otp_apb_addr_i26;
+    input fabric_otp_apb_addr_i27;
+    input fabric_otp_apb_addr_i28;
+    input fabric_otp_apb_addr_i29;
+    input fabric_otp_apb_addr_i3;
+    input fabric_otp_apb_addr_i30;
+    input fabric_otp_apb_addr_i31;
+    input fabric_otp_apb_addr_i32;
+    input fabric_otp_apb_addr_i4;
+    input fabric_otp_apb_addr_i5;
+    input fabric_otp_apb_addr_i6;
+    input fabric_otp_apb_addr_i7;
+    input fabric_otp_apb_addr_i8;
+    input fabric_otp_apb_addr_i9;
+    input fabric_otp_apb_enable_i;
+    output fabric_otp_apb_rdata_o1;
+    output fabric_otp_apb_rdata_o10;
+    output fabric_otp_apb_rdata_o11;
+    output fabric_otp_apb_rdata_o12;
+    output fabric_otp_apb_rdata_o13;
+    output fabric_otp_apb_rdata_o14;
+    output fabric_otp_apb_rdata_o15;
+    output fabric_otp_apb_rdata_o16;
+    output fabric_otp_apb_rdata_o17;
+    output fabric_otp_apb_rdata_o18;
+    output fabric_otp_apb_rdata_o19;
+    output fabric_otp_apb_rdata_o2;
+    output fabric_otp_apb_rdata_o20;
+    output fabric_otp_apb_rdata_o21;
+    output fabric_otp_apb_rdata_o22;
+    output fabric_otp_apb_rdata_o23;
+    output fabric_otp_apb_rdata_o24;
+    output fabric_otp_apb_rdata_o25;
+    output fabric_otp_apb_rdata_o26;
+    output fabric_otp_apb_rdata_o27;
+    output fabric_otp_apb_rdata_o28;
+    output fabric_otp_apb_rdata_o29;
+    output fabric_otp_apb_rdata_o3;
+    output fabric_otp_apb_rdata_o30;
+    output fabric_otp_apb_rdata_o31;
+    output fabric_otp_apb_rdata_o32;
+    output fabric_otp_apb_rdata_o4;
+    output fabric_otp_apb_rdata_o5;
+    output fabric_otp_apb_rdata_o6;
+    output fabric_otp_apb_rdata_o7;
+    output fabric_otp_apb_rdata_o8;
+    output fabric_otp_apb_rdata_o9;
+    output fabric_otp_apb_ready_o;
+    input fabric_otp_apb_sel_i;
+    input fabric_otp_apb_wdata_i1;
+    input fabric_otp_apb_wdata_i10;
+    input fabric_otp_apb_wdata_i11;
+    input fabric_otp_apb_wdata_i12;
+    input fabric_otp_apb_wdata_i13;
+    input fabric_otp_apb_wdata_i14;
+    input fabric_otp_apb_wdata_i15;
+    input fabric_otp_apb_wdata_i16;
+    input fabric_otp_apb_wdata_i17;
+    input fabric_otp_apb_wdata_i18;
+    input fabric_otp_apb_wdata_i19;
+    input fabric_otp_apb_wdata_i2;
+    input fabric_otp_apb_wdata_i20;
+    input fabric_otp_apb_wdata_i21;
+    input fabric_otp_apb_wdata_i22;
+    input fabric_otp_apb_wdata_i23;
+    input fabric_otp_apb_wdata_i24;
+    input fabric_otp_apb_wdata_i25;
+    input fabric_otp_apb_wdata_i26;
+    input fabric_otp_apb_wdata_i27;
+    input fabric_otp_apb_wdata_i28;
+    input fabric_otp_apb_wdata_i29;
+    input fabric_otp_apb_wdata_i3;
+    input fabric_otp_apb_wdata_i30;
+    input fabric_otp_apb_wdata_i31;
+    input fabric_otp_apb_wdata_i32;
+    input fabric_otp_apb_wdata_i4;
+    input fabric_otp_apb_wdata_i5;
+    input fabric_otp_apb_wdata_i6;
+    input fabric_otp_apb_wdata_i7;
+    input fabric_otp_apb_wdata_i8;
+    input fabric_otp_apb_wdata_i9;
+    input fabric_otp_apb_write_i;
+    input fabric_otp_cfg_clk_fab_en_i;
+    input fabric_otp_cfg_clk_otpm_disable_i;
+    input fabric_otp_cfg_fabric_apb_en_i;
+    input fabric_otp_cfg_loader_read_en_i;
+    input fabric_otp_cfg_loader_write_en_i;
+    input fabric_otp_clk_i;
+    input fabric_otp_rst_i;
+    output fabric_otp_security_ack_o;
+    output fabric_otp_security_bist_bad_o;
+    output fabric_otp_security_bist_end1_o;
+    output fabric_otp_security_bist_end2_o;
+    output fabric_otp_security_bist_fail1_o1;
+    output fabric_otp_security_bist_fail1_o2;
+    output fabric_otp_security_bist_fail1_o3;
+    output fabric_otp_security_bist_fail1_o4;
+    output fabric_otp_security_bist_fail1_o5;
+    output fabric_otp_security_bist_fail1_o6;
+    output fabric_otp_security_bist_fail1_o7;
+    output fabric_otp_security_bist_fail2_o1;
+    output fabric_otp_security_bist_fail2_o2;
+    output fabric_otp_security_bist_fail2_o3;
+    output fabric_otp_security_bist_fail2_o4;
+    output fabric_otp_security_bist_fail2_o5;
+    output fabric_otp_security_bist_fail2_o6;
+    input fabric_otp_security_bistmode_i;
+    input fabric_otp_security_force_pdn1_i;
+    input fabric_otp_security_rbact1_i;
+    input fabric_otp_security_rbact2_i;
+    input fabric_otp_security_scanenable_i;
+    input fabric_otp_security_scanin_i1;
+    input fabric_otp_security_scanin_i2;
+    input fabric_otp_security_scanin_i3;
+    input fabric_otp_security_scanin_i4;
+    output fabric_otp_security_scanout_o1;
+    output fabric_otp_security_scanout_o2;
+    output fabric_otp_security_scanout_o3;
+    output fabric_otp_security_scanout_o4;
+    input fabric_otp_security_testmode_i;
+    output fabric_otp_user_ack_o;
+    input fabric_otp_user_add_i1;
+    input fabric_otp_user_add_i2;
+    input fabric_otp_user_add_i3;
+    input fabric_otp_user_add_i4;
+    input fabric_otp_user_add_i5;
+    input fabric_otp_user_add_i6;
+    input fabric_otp_user_add_i7;
+    output fabric_otp_user_bbad_o;
+    output fabric_otp_user_bend1_o;
+    output fabric_otp_user_bend2_o;
+    output fabric_otp_user_bist1fail_o1;
+    output fabric_otp_user_bist1fail_o2;
+    output fabric_otp_user_bist1fail_o3;
+    output fabric_otp_user_bist1fail_o4;
+    output fabric_otp_user_bist1fail_o5;
+    output fabric_otp_user_bist1fail_o6;
+    output fabric_otp_user_bist1fail_o7;
+    output fabric_otp_user_bist1fail_o8;
+    output fabric_otp_user_bist2fail_o1;
+    output fabric_otp_user_bist2fail_o2;
+    output fabric_otp_user_bist2fail_o3;
+    output fabric_otp_user_bist2fail_o4;
+    output fabric_otp_user_bist2fail_o5;
+    output fabric_otp_user_bist2fail_o6;
+    output fabric_otp_user_bist2fail_o7;
+    input fabric_otp_user_bistmode_i;
+    output fabric_otp_user_calibrated_o;
+    input fabric_otp_user_clk_i;
+    input fabric_otp_user_clock_frequency_range_i;
+    output fabric_otp_user_ded_o;
+    input fabric_otp_user_din_i1;
+    input fabric_otp_user_din_i10;
+    input fabric_otp_user_din_i11;
+    input fabric_otp_user_din_i12;
+    input fabric_otp_user_din_i13;
+    input fabric_otp_user_din_i14;
+    input fabric_otp_user_din_i15;
+    input fabric_otp_user_din_i16;
+    input fabric_otp_user_din_i17;
+    input fabric_otp_user_din_i18;
+    input fabric_otp_user_din_i19;
+    input fabric_otp_user_din_i2;
+    input fabric_otp_user_din_i20;
+    input fabric_otp_user_din_i21;
+    input fabric_otp_user_din_i22;
+    input fabric_otp_user_din_i23;
+    input fabric_otp_user_din_i24;
+    input fabric_otp_user_din_i25;
+    input fabric_otp_user_din_i26;
+    input fabric_otp_user_din_i27;
+    input fabric_otp_user_din_i28;
+    input fabric_otp_user_din_i29;
+    input fabric_otp_user_din_i3;
+    input fabric_otp_user_din_i30;
+    input fabric_otp_user_din_i31;
+    input fabric_otp_user_din_i32;
+    input fabric_otp_user_din_i33;
+    input fabric_otp_user_din_i34;
+    input fabric_otp_user_din_i35;
+    input fabric_otp_user_din_i36;
+    input fabric_otp_user_din_i37;
+    input fabric_otp_user_din_i38;
+    input fabric_otp_user_din_i39;
+    input fabric_otp_user_din_i4;
+    input fabric_otp_user_din_i5;
+    input fabric_otp_user_din_i6;
+    input fabric_otp_user_din_i7;
+    input fabric_otp_user_din_i8;
+    input fabric_otp_user_din_i9;
+    input fabric_otp_user_disturbcheck_i;
+    output fabric_otp_user_disturbed_o;
+    output fabric_otp_user_dout_o1;
+    output fabric_otp_user_dout_o10;
+    output fabric_otp_user_dout_o11;
+    output fabric_otp_user_dout_o12;
+    output fabric_otp_user_dout_o13;
+    output fabric_otp_user_dout_o14;
+    output fabric_otp_user_dout_o15;
+    output fabric_otp_user_dout_o16;
+    output fabric_otp_user_dout_o17;
+    output fabric_otp_user_dout_o18;
+    output fabric_otp_user_dout_o19;
+    output fabric_otp_user_dout_o2;
+    output fabric_otp_user_dout_o20;
+    output fabric_otp_user_dout_o21;
+    output fabric_otp_user_dout_o22;
+    output fabric_otp_user_dout_o23;
+    output fabric_otp_user_dout_o24;
+    output fabric_otp_user_dout_o25;
+    output fabric_otp_user_dout_o26;
+    output fabric_otp_user_dout_o27;
+    output fabric_otp_user_dout_o28;
+    output fabric_otp_user_dout_o29;
+    output fabric_otp_user_dout_o3;
+    output fabric_otp_user_dout_o30;
+    output fabric_otp_user_dout_o31;
+    output fabric_otp_user_dout_o32;
+    output fabric_otp_user_dout_o33;
+    output fabric_otp_user_dout_o34;
+    output fabric_otp_user_dout_o35;
+    output fabric_otp_user_dout_o36;
+    output fabric_otp_user_dout_o37;
+    output fabric_otp_user_dout_o38;
+    output fabric_otp_user_dout_o39;
+    output fabric_otp_user_dout_o4;
+    output fabric_otp_user_dout_o40;
+    output fabric_otp_user_dout_o41;
+    output fabric_otp_user_dout_o5;
+    output fabric_otp_user_dout_o6;
+    output fabric_otp_user_dout_o7;
+    output fabric_otp_user_dout_o8;
+    output fabric_otp_user_dout_o9;
+    input fabric_otp_user_eccbypass_i;
+    output fabric_otp_user_flagstate_o1;
+    output fabric_otp_user_flagstate_o2;
+    output fabric_otp_user_flagstate_o3;
+    output fabric_otp_user_flagstate_o4;
+    output fabric_otp_user_locked_o;
+    input fabric_otp_user_pdn_i;
+    input fabric_otp_user_prgwidth_i1;
+    input fabric_otp_user_prgwidth_i2;
+    input fabric_otp_user_prgwidth_i3;
+    input fabric_otp_user_prog_i;
+    output fabric_otp_user_progfail_o;
+    output fabric_otp_user_pwok_o;
+    input fabric_otp_user_rbact1_i;
+    input fabric_otp_user_rbact2_i;
+    input fabric_otp_user_read_i;
+    input fabric_otp_user_redbypass_i;
+    output fabric_otp_user_sec_o;
+    output fabric_otp_user_startword_o1;
+    output fabric_otp_user_startword_o10;
+    output fabric_otp_user_startword_o11;
+    output fabric_otp_user_startword_o12;
+    output fabric_otp_user_startword_o13;
+    output fabric_otp_user_startword_o14;
+    output fabric_otp_user_startword_o15;
+    output fabric_otp_user_startword_o16;
+    output fabric_otp_user_startword_o2;
+    output fabric_otp_user_startword_o3;
+    output fabric_otp_user_startword_o4;
+    output fabric_otp_user_startword_o5;
+    output fabric_otp_user_startword_o6;
+    output fabric_otp_user_startword_o7;
+    output fabric_otp_user_startword_o8;
+    output fabric_otp_user_startword_o9;
+    input fabric_otp_user_suppadd_i;
+    input fabric_otp_user_tm_i;
+    input fabric_otp_user_tst_scanenable_i;
+    input fabric_otp_user_tst_scanin_i1;
+    input fabric_otp_user_tst_scanin_i2;
+    input fabric_otp_user_tst_scanin_i3;
+    input fabric_otp_user_tst_scanin_i4;
+    input fabric_otp_user_tst_scanin_i5;
+    output fabric_otp_user_tst_scanout_o1;
+    output fabric_otp_user_tst_scanout_o2;
+    output fabric_otp_user_tst_scanout_o3;
+    output fabric_otp_user_tst_scanout_o4;
+    output fabric_otp_user_tst_scanout_o5;
+    output fabric_otp_user_wlromout_o1;
+    output fabric_otp_user_wlromout_o10;
+    output fabric_otp_user_wlromout_o2;
+    output fabric_otp_user_wlromout_o3;
+    output fabric_otp_user_wlromout_o4;
+    output fabric_otp_user_wlromout_o5;
+    output fabric_otp_user_wlromout_o6;
+    output fabric_otp_user_wlromout_o7;
+    output fabric_otp_user_wlromout_o8;
+    output fabric_otp_user_wlromout_o9;
+    input fabric_otp_user_wordlock_i;
+    input fabric_parusr_clk_i;
+    input fabric_parusr_cs_i;
+    input fabric_parusr_data_i1;
+    input fabric_parusr_data_i10;
+    input fabric_parusr_data_i11;
+    input fabric_parusr_data_i12;
+    input fabric_parusr_data_i13;
+    input fabric_parusr_data_i14;
+    input fabric_parusr_data_i15;
+    input fabric_parusr_data_i16;
+    input fabric_parusr_data_i2;
+    input fabric_parusr_data_i3;
+    input fabric_parusr_data_i4;
+    input fabric_parusr_data_i5;
+    input fabric_parusr_data_i6;
+    input fabric_parusr_data_i7;
+    input fabric_parusr_data_i8;
+    input fabric_parusr_data_i9;
+    output fabric_parusr_data_o1;
+    output fabric_parusr_data_o10;
+    output fabric_parusr_data_o11;
+    output fabric_parusr_data_o12;
+    output fabric_parusr_data_o13;
+    output fabric_parusr_data_o14;
+    output fabric_parusr_data_o15;
+    output fabric_parusr_data_o16;
+    output fabric_parusr_data_o2;
+    output fabric_parusr_data_o3;
+    output fabric_parusr_data_o4;
+    output fabric_parusr_data_o5;
+    output fabric_parusr_data_o6;
+    output fabric_parusr_data_o7;
+    output fabric_parusr_data_o8;
+    output fabric_parusr_data_o9;
+    output fabric_parusr_data_val_o;
+    input fabric_parusr_enable_i;
+    input fabric_parusr_type_i1;
+    input fabric_parusr_type_i2;
+    input fabric_spare_i1;
+    input fabric_spare_i10;
+    input fabric_spare_i100;
+    input fabric_spare_i101;
+    input fabric_spare_i102;
+    input fabric_spare_i103;
+    input fabric_spare_i104;
+    input fabric_spare_i105;
+    input fabric_spare_i106;
+    input fabric_spare_i107;
+    input fabric_spare_i108;
+    input fabric_spare_i109;
+    input fabric_spare_i11;
+    input fabric_spare_i110;
+    input fabric_spare_i111;
+    input fabric_spare_i112;
+    input fabric_spare_i113;
+    input fabric_spare_i114;
+    input fabric_spare_i115;
+    input fabric_spare_i116;
+    input fabric_spare_i117;
+    input fabric_spare_i118;
+    input fabric_spare_i119;
+    input fabric_spare_i12;
+    input fabric_spare_i120;
+    input fabric_spare_i121;
+    input fabric_spare_i122;
+    input fabric_spare_i123;
+    input fabric_spare_i124;
+    input fabric_spare_i125;
+    input fabric_spare_i126;
+    input fabric_spare_i127;
+    input fabric_spare_i128;
+    input fabric_spare_i13;
+    input fabric_spare_i14;
+    input fabric_spare_i15;
+    input fabric_spare_i16;
+    input fabric_spare_i17;
+    input fabric_spare_i18;
+    input fabric_spare_i19;
+    input fabric_spare_i2;
+    input fabric_spare_i20;
+    input fabric_spare_i21;
+    input fabric_spare_i22;
+    input fabric_spare_i23;
+    input fabric_spare_i24;
+    input fabric_spare_i25;
+    input fabric_spare_i26;
+    input fabric_spare_i27;
+    input fabric_spare_i28;
+    input fabric_spare_i29;
+    input fabric_spare_i3;
+    input fabric_spare_i30;
+    input fabric_spare_i31;
+    input fabric_spare_i32;
+    input fabric_spare_i33;
+    input fabric_spare_i34;
+    input fabric_spare_i35;
+    input fabric_spare_i36;
+    input fabric_spare_i37;
+    input fabric_spare_i38;
+    input fabric_spare_i39;
+    input fabric_spare_i4;
+    input fabric_spare_i40;
+    input fabric_spare_i41;
+    input fabric_spare_i42;
+    input fabric_spare_i43;
+    input fabric_spare_i44;
+    input fabric_spare_i45;
+    input fabric_spare_i46;
+    input fabric_spare_i47;
+    input fabric_spare_i48;
+    input fabric_spare_i49;
+    input fabric_spare_i5;
+    input fabric_spare_i50;
+    input fabric_spare_i51;
+    input fabric_spare_i52;
+    input fabric_spare_i53;
+    input fabric_spare_i54;
+    input fabric_spare_i55;
+    input fabric_spare_i56;
+    input fabric_spare_i57;
+    input fabric_spare_i58;
+    input fabric_spare_i59;
+    input fabric_spare_i6;
+    input fabric_spare_i60;
+    input fabric_spare_i61;
+    input fabric_spare_i62;
+    input fabric_spare_i63;
+    input fabric_spare_i64;
+    input fabric_spare_i65;
+    input fabric_spare_i66;
+    input fabric_spare_i67;
+    input fabric_spare_i68;
+    input fabric_spare_i69;
+    input fabric_spare_i7;
+    input fabric_spare_i70;
+    input fabric_spare_i71;
+    input fabric_spare_i72;
+    input fabric_spare_i73;
+    input fabric_spare_i74;
+    input fabric_spare_i75;
+    input fabric_spare_i76;
+    input fabric_spare_i77;
+    input fabric_spare_i78;
+    input fabric_spare_i79;
+    input fabric_spare_i8;
+    input fabric_spare_i80;
+    input fabric_spare_i81;
+    input fabric_spare_i82;
+    input fabric_spare_i83;
+    input fabric_spare_i84;
+    input fabric_spare_i85;
+    input fabric_spare_i86;
+    input fabric_spare_i87;
+    input fabric_spare_i88;
+    input fabric_spare_i89;
+    input fabric_spare_i9;
+    input fabric_spare_i90;
+    input fabric_spare_i91;
+    input fabric_spare_i92;
+    input fabric_spare_i93;
+    input fabric_spare_i94;
+    input fabric_spare_i95;
+    input fabric_spare_i96;
+    input fabric_spare_i97;
+    input fabric_spare_i98;
+    input fabric_spare_i99;
+    output fabric_spare_o1;
+    output fabric_spare_o10;
+    output fabric_spare_o100;
+    output fabric_spare_o101;
+    output fabric_spare_o102;
+    output fabric_spare_o103;
+    output fabric_spare_o104;
+    output fabric_spare_o105;
+    output fabric_spare_o106;
+    output fabric_spare_o107;
+    output fabric_spare_o108;
+    output fabric_spare_o109;
+    output fabric_spare_o11;
+    output fabric_spare_o110;
+    output fabric_spare_o111;
+    output fabric_spare_o112;
+    output fabric_spare_o113;
+    output fabric_spare_o114;
+    output fabric_spare_o115;
+    output fabric_spare_o116;
+    output fabric_spare_o117;
+    output fabric_spare_o118;
+    output fabric_spare_o119;
+    output fabric_spare_o12;
+    output fabric_spare_o120;
+    output fabric_spare_o121;
+    output fabric_spare_o122;
+    output fabric_spare_o123;
+    output fabric_spare_o124;
+    output fabric_spare_o125;
+    output fabric_spare_o126;
+    output fabric_spare_o127;
+    output fabric_spare_o128;
+    output fabric_spare_o13;
+    output fabric_spare_o14;
+    output fabric_spare_o15;
+    output fabric_spare_o16;
+    output fabric_spare_o17;
+    output fabric_spare_o18;
+    output fabric_spare_o19;
+    output fabric_spare_o2;
+    output fabric_spare_o20;
+    output fabric_spare_o21;
+    output fabric_spare_o22;
+    output fabric_spare_o23;
+    output fabric_spare_o24;
+    output fabric_spare_o25;
+    output fabric_spare_o26;
+    output fabric_spare_o27;
+    output fabric_spare_o28;
+    output fabric_spare_o29;
+    output fabric_spare_o3;
+    output fabric_spare_o30;
+    output fabric_spare_o31;
+    output fabric_spare_o32;
+    output fabric_spare_o33;
+    output fabric_spare_o34;
+    output fabric_spare_o35;
+    output fabric_spare_o36;
+    output fabric_spare_o37;
+    output fabric_spare_o38;
+    output fabric_spare_o39;
+    output fabric_spare_o4;
+    output fabric_spare_o40;
+    output fabric_spare_o41;
+    output fabric_spare_o42;
+    output fabric_spare_o43;
+    output fabric_spare_o44;
+    output fabric_spare_o45;
+    output fabric_spare_o46;
+    output fabric_spare_o47;
+    output fabric_spare_o48;
+    output fabric_spare_o49;
+    output fabric_spare_o5;
+    output fabric_spare_o50;
+    output fabric_spare_o51;
+    output fabric_spare_o52;
+    output fabric_spare_o53;
+    output fabric_spare_o54;
+    output fabric_spare_o55;
+    output fabric_spare_o56;
+    output fabric_spare_o57;
+    output fabric_spare_o58;
+    output fabric_spare_o59;
+    output fabric_spare_o6;
+    output fabric_spare_o60;
+    output fabric_spare_o61;
+    output fabric_spare_o62;
+    output fabric_spare_o63;
+    output fabric_spare_o64;
+    output fabric_spare_o65;
+    output fabric_spare_o66;
+    output fabric_spare_o67;
+    output fabric_spare_o68;
+    output fabric_spare_o69;
+    output fabric_spare_o7;
+    output fabric_spare_o70;
+    output fabric_spare_o71;
+    output fabric_spare_o72;
+    output fabric_spare_o73;
+    output fabric_spare_o74;
+    output fabric_spare_o75;
+    output fabric_spare_o76;
+    output fabric_spare_o77;
+    output fabric_spare_o78;
+    output fabric_spare_o79;
+    output fabric_spare_o8;
+    output fabric_spare_o80;
+    output fabric_spare_o81;
+    output fabric_spare_o82;
+    output fabric_spare_o83;
+    output fabric_spare_o84;
+    output fabric_spare_o85;
+    output fabric_spare_o86;
+    output fabric_spare_o87;
+    output fabric_spare_o88;
+    output fabric_spare_o89;
+    output fabric_spare_o9;
+    output fabric_spare_o90;
+    output fabric_spare_o91;
+    output fabric_spare_o92;
+    output fabric_spare_o93;
+    output fabric_spare_o94;
+    output fabric_spare_o95;
+    output fabric_spare_o96;
+    output fabric_spare_o97;
+    output fabric_spare_o98;
+    output fabric_spare_o99;
+    input fabric_spi_arst_tmr_n_i1;
+    input fabric_spi_arst_tmr_n_i2;
+    input fabric_spi_arst_tmr_n_i3;
+    input fabric_spi_arst_tmr_n_i4;
+    input fabric_spi_arst_tmr_n_i5;
+    input fabric_spi_arst_tmr_n_i6;
+    input fabric_spi_arst_tmr_n_i7;
+    input fabric_spi_arst_tmr_n_i8;
+    input fabric_spi_arst_tmr_n_i9;
+    output fabric_spi_bsm_release_o1;
+    output fabric_spi_bsm_release_o2;
+    output fabric_spi_bsm_release_o3;
+    output fabric_spi_busy_o1;
+    output fabric_spi_busy_o2;
+    output fabric_spi_busy_o3;
+    input fabric_spi_clk_i0;
+    input fabric_spi_clk_i1;
+    input fabric_spi_clk_i2;
+    input fabric_spi_cmd_bytes_i1;
+    input fabric_spi_cmd_bytes_i2;
+    input fabric_spi_cmd_bytes_i3;
+    input fabric_spi_cmd_bytes_i4;
+    input fabric_spi_cmd_bytes_i5;
+    input fabric_spi_cmd_bytes_i6;
+    output fabric_spi_cmd_full_o1;
+    output fabric_spi_cmd_full_o2;
+    output fabric_spi_cmd_full_o3;
+    input fabric_spi_cmd_mode_i1;
+    input fabric_spi_cmd_mode_i2;
+    input fabric_spi_cmd_mode_i3;
+    input fabric_spi_cmd_mode_i4;
+    input fabric_spi_cmd_mode_i5;
+    input fabric_spi_cmd_mode_i6;
+    input fabric_spi_cmd_push_i1;
+    input fabric_spi_cmd_push_i2;
+    input fabric_spi_cmd_push_i3;
+    input fabric_spi_cmd_type_i1;
+    input fabric_spi_cmd_type_i2;
+    input fabric_spi_cmd_type_i3;
+    input fabric_spi_cmd_type_i4;
+    input fabric_spi_cmd_type_i5;
+    input fabric_spi_cmd_type_i6;
+    input fabric_spi_cpha_i1;
+    input fabric_spi_cpha_i2;
+    input fabric_spi_cpha_i3;
+    input fabric_spi_cpol_i1;
+    input fabric_spi_cpol_i2;
+    input fabric_spi_cpol_i3;
+    input fabric_spi_cs_holdtime_i1;
+    input fabric_spi_cs_holdtime_i10;
+    input fabric_spi_cs_holdtime_i11;
+    input fabric_spi_cs_holdtime_i12;
+    input fabric_spi_cs_holdtime_i2;
+    input fabric_spi_cs_holdtime_i3;
+    input fabric_spi_cs_holdtime_i4;
+    input fabric_spi_cs_holdtime_i5;
+    input fabric_spi_cs_holdtime_i6;
+    input fabric_spi_cs_holdtime_i7;
+    input fabric_spi_cs_holdtime_i8;
+    input fabric_spi_cs_holdtime_i9;
+    input fabric_spi_cs_offtime_i1;
+    input fabric_spi_cs_offtime_i10;
+    input fabric_spi_cs_offtime_i11;
+    input fabric_spi_cs_offtime_i12;
+    input fabric_spi_cs_offtime_i2;
+    input fabric_spi_cs_offtime_i3;
+    input fabric_spi_cs_offtime_i4;
+    input fabric_spi_cs_offtime_i5;
+    input fabric_spi_cs_offtime_i6;
+    input fabric_spi_cs_offtime_i7;
+    input fabric_spi_cs_offtime_i8;
+    input fabric_spi_cs_offtime_i9;
+    input fabric_spi_cs_setuptime_i1;
+    input fabric_spi_cs_setuptime_i10;
+    input fabric_spi_cs_setuptime_i11;
+    input fabric_spi_cs_setuptime_i12;
+    input fabric_spi_cs_setuptime_i2;
+    input fabric_spi_cs_setuptime_i3;
+    input fabric_spi_cs_setuptime_i4;
+    input fabric_spi_cs_setuptime_i5;
+    input fabric_spi_cs_setuptime_i6;
+    input fabric_spi_cs_setuptime_i7;
+    input fabric_spi_cs_setuptime_i8;
+    input fabric_spi_cs_setuptime_i9;
+    input fabric_spi_data_in_unlimited_i1;
+    input fabric_spi_data_in_unlimited_i2;
+    input fabric_spi_data_in_unlimited_i3;
+    input fabric_spi_enable_i1;
+    input fabric_spi_enable_i2;
+    input fabric_spi_enable_i3;
+    output fabric_spi_error_endianness_o1;
+    output fabric_spi_error_endianness_o2;
+    output fabric_spi_error_endianness_o3;
+    output fabric_spi_error_loopback_o1;
+    output fabric_spi_error_loopback_o2;
+    output fabric_spi_error_loopback_o3;
+    output fabric_spi_error_mode_o1;
+    output fabric_spi_error_mode_o2;
+    output fabric_spi_error_mode_o3;
+    output fabric_spi_error_sel_o1;
+    output fabric_spi_error_sel_o2;
+    output fabric_spi_error_sel_o3;
+    input fabric_spi_fifo_arst_tmr_n_i1;
+    input fabric_spi_fifo_arst_tmr_n_i2;
+    input fabric_spi_fifo_arst_tmr_n_i3;
+    input fabric_spi_fifo_arst_tmr_n_i4;
+    input fabric_spi_fifo_arst_tmr_n_i5;
+    input fabric_spi_fifo_arst_tmr_n_i6;
+    input fabric_spi_fifo_arst_tmr_n_i7;
+    input fabric_spi_fifo_arst_tmr_n_i8;
+    input fabric_spi_fifo_arst_tmr_n_i9;
+    output fabric_spi_init_done_o1;
+    output fabric_spi_init_done_o2;
+    output fabric_spi_init_done_o3;
+    input fabric_spi_legacy_enable_i1;
+    input fabric_spi_legacy_enable_i2;
+    input fabric_spi_legacy_enable_i3;
+    input fabric_spi_legacy_master_i1;
+    input fabric_spi_legacy_master_i2;
+    input fabric_spi_legacy_master_i3;
+    input fabric_spi_loopback_i1;
+    input fabric_spi_loopback_i2;
+    input fabric_spi_loopback_i3;
+    input fabric_spi_lsb_first_i1;
+    input fabric_spi_lsb_first_i2;
+    input fabric_spi_lsb_first_i3;
+    output fabric_spi_miso_data_inv_o1;
+    output fabric_spi_miso_data_inv_o2;
+    output fabric_spi_miso_data_inv_o3;
+    output fabric_spi_miso_data_o1;
+    output fabric_spi_miso_data_o10;
+    output fabric_spi_miso_data_o11;
+    output fabric_spi_miso_data_o12;
+    output fabric_spi_miso_data_o13;
+    output fabric_spi_miso_data_o14;
+    output fabric_spi_miso_data_o15;
+    output fabric_spi_miso_data_o16;
+    output fabric_spi_miso_data_o17;
+    output fabric_spi_miso_data_o18;
+    output fabric_spi_miso_data_o19;
+    output fabric_spi_miso_data_o2;
+    output fabric_spi_miso_data_o20;
+    output fabric_spi_miso_data_o21;
+    output fabric_spi_miso_data_o22;
+    output fabric_spi_miso_data_o23;
+    output fabric_spi_miso_data_o24;
+    output fabric_spi_miso_data_o3;
+    output fabric_spi_miso_data_o4;
+    output fabric_spi_miso_data_o5;
+    output fabric_spi_miso_data_o6;
+    output fabric_spi_miso_data_o7;
+    output fabric_spi_miso_data_o8;
+    output fabric_spi_miso_data_o9;
+    output fabric_spi_miso_empty_o1;
+    output fabric_spi_miso_empty_o2;
+    output fabric_spi_miso_empty_o3;
+    input fabric_spi_miso_pop_i1;
+    input fabric_spi_miso_pop_i2;
+    input fabric_spi_miso_pop_i3;
+    input fabric_spi_mosi_data_i1;
+    input fabric_spi_mosi_data_i10;
+    input fabric_spi_mosi_data_i11;
+    input fabric_spi_mosi_data_i12;
+    input fabric_spi_mosi_data_i13;
+    input fabric_spi_mosi_data_i14;
+    input fabric_spi_mosi_data_i15;
+    input fabric_spi_mosi_data_i16;
+    input fabric_spi_mosi_data_i17;
+    input fabric_spi_mosi_data_i18;
+    input fabric_spi_mosi_data_i19;
+    input fabric_spi_mosi_data_i2;
+    input fabric_spi_mosi_data_i20;
+    input fabric_spi_mosi_data_i21;
+    input fabric_spi_mosi_data_i22;
+    input fabric_spi_mosi_data_i23;
+    input fabric_spi_mosi_data_i24;
+    input fabric_spi_mosi_data_i3;
+    input fabric_spi_mosi_data_i4;
+    input fabric_spi_mosi_data_i5;
+    input fabric_spi_mosi_data_i6;
+    input fabric_spi_mosi_data_i7;
+    input fabric_spi_mosi_data_i8;
+    input fabric_spi_mosi_data_i9;
+    input fabric_spi_mosi_data_inv_i1;
+    input fabric_spi_mosi_data_inv_i2;
+    input fabric_spi_mosi_data_inv_i3;
+    output fabric_spi_mosi_full_o1;
+    output fabric_spi_mosi_full_o2;
+    output fabric_spi_mosi_full_o3;
+    input fabric_spi_mosi_push_i1;
+    input fabric_spi_mosi_push_i2;
+    input fabric_spi_mosi_push_i3;
+    input fabric_spi_needed_i1;
+    input fabric_spi_needed_i2;
+    input fabric_spi_needed_i3;
+    input fabric_spi_powerdown_cycle_i1;
+    input fabric_spi_powerdown_cycle_i10;
+    input fabric_spi_powerdown_cycle_i11;
+    input fabric_spi_powerdown_cycle_i12;
+    input fabric_spi_powerdown_cycle_i13;
+    input fabric_spi_powerdown_cycle_i14;
+    input fabric_spi_powerdown_cycle_i15;
+    input fabric_spi_powerdown_cycle_i16;
+    input fabric_spi_powerdown_cycle_i17;
+    input fabric_spi_powerdown_cycle_i18;
+    input fabric_spi_powerdown_cycle_i19;
+    input fabric_spi_powerdown_cycle_i2;
+    input fabric_spi_powerdown_cycle_i20;
+    input fabric_spi_powerdown_cycle_i21;
+    input fabric_spi_powerdown_cycle_i22;
+    input fabric_spi_powerdown_cycle_i23;
+    input fabric_spi_powerdown_cycle_i24;
+    input fabric_spi_powerdown_cycle_i25;
+    input fabric_spi_powerdown_cycle_i26;
+    input fabric_spi_powerdown_cycle_i27;
+    input fabric_spi_powerdown_cycle_i28;
+    input fabric_spi_powerdown_cycle_i29;
+    input fabric_spi_powerdown_cycle_i3;
+    input fabric_spi_powerdown_cycle_i30;
+    input fabric_spi_powerdown_cycle_i31;
+    input fabric_spi_powerdown_cycle_i32;
+    input fabric_spi_powerdown_cycle_i33;
+    input fabric_spi_powerdown_cycle_i34;
+    input fabric_spi_powerdown_cycle_i35;
+    input fabric_spi_powerdown_cycle_i36;
+    input fabric_spi_powerdown_cycle_i37;
+    input fabric_spi_powerdown_cycle_i38;
+    input fabric_spi_powerdown_cycle_i39;
+    input fabric_spi_powerdown_cycle_i4;
+    input fabric_spi_powerdown_cycle_i40;
+    input fabric_spi_powerdown_cycle_i41;
+    input fabric_spi_powerdown_cycle_i42;
+    input fabric_spi_powerdown_cycle_i43;
+    input fabric_spi_powerdown_cycle_i44;
+    input fabric_spi_powerdown_cycle_i45;
+    input fabric_spi_powerdown_cycle_i46;
+    input fabric_spi_powerdown_cycle_i47;
+    input fabric_spi_powerdown_cycle_i48;
+    input fabric_spi_powerdown_cycle_i5;
+    input fabric_spi_powerdown_cycle_i6;
+    input fabric_spi_powerdown_cycle_i7;
+    input fabric_spi_powerdown_cycle_i8;
+    input fabric_spi_powerdown_cycle_i9;
+    input fabric_spi_powerup_cycle_i1;
+    input fabric_spi_powerup_cycle_i10;
+    input fabric_spi_powerup_cycle_i11;
+    input fabric_spi_powerup_cycle_i12;
+    input fabric_spi_powerup_cycle_i13;
+    input fabric_spi_powerup_cycle_i14;
+    input fabric_spi_powerup_cycle_i15;
+    input fabric_spi_powerup_cycle_i16;
+    input fabric_spi_powerup_cycle_i17;
+    input fabric_spi_powerup_cycle_i18;
+    input fabric_spi_powerup_cycle_i19;
+    input fabric_spi_powerup_cycle_i2;
+    input fabric_spi_powerup_cycle_i20;
+    input fabric_spi_powerup_cycle_i21;
+    input fabric_spi_powerup_cycle_i22;
+    input fabric_spi_powerup_cycle_i23;
+    input fabric_spi_powerup_cycle_i24;
+    input fabric_spi_powerup_cycle_i25;
+    input fabric_spi_powerup_cycle_i26;
+    input fabric_spi_powerup_cycle_i27;
+    input fabric_spi_powerup_cycle_i28;
+    input fabric_spi_powerup_cycle_i29;
+    input fabric_spi_powerup_cycle_i3;
+    input fabric_spi_powerup_cycle_i30;
+    input fabric_spi_powerup_cycle_i31;
+    input fabric_spi_powerup_cycle_i32;
+    input fabric_spi_powerup_cycle_i33;
+    input fabric_spi_powerup_cycle_i34;
+    input fabric_spi_powerup_cycle_i35;
+    input fabric_spi_powerup_cycle_i36;
+    input fabric_spi_powerup_cycle_i37;
+    input fabric_spi_powerup_cycle_i38;
+    input fabric_spi_powerup_cycle_i39;
+    input fabric_spi_powerup_cycle_i4;
+    input fabric_spi_powerup_cycle_i40;
+    input fabric_spi_powerup_cycle_i41;
+    input fabric_spi_powerup_cycle_i42;
+    input fabric_spi_powerup_cycle_i43;
+    input fabric_spi_powerup_cycle_i44;
+    input fabric_spi_powerup_cycle_i45;
+    input fabric_spi_powerup_cycle_i46;
+    input fabric_spi_powerup_cycle_i47;
+    input fabric_spi_powerup_cycle_i48;
+    input fabric_spi_powerup_cycle_i5;
+    input fabric_spi_powerup_cycle_i6;
+    input fabric_spi_powerup_cycle_i7;
+    input fabric_spi_powerup_cycle_i8;
+    input fabric_spi_powerup_cycle_i9;
+    input fabric_spi_rst_n_i1;
+    input fabric_spi_rst_n_i2;
+    input fabric_spi_rst_n_i3;
+    input fabric_spi_sck_i0;
+    input fabric_spi_sck_i1;
+    input fabric_spi_sck_i2;
+    input fabric_spi_vcc_enable_i1;
+    input fabric_spi_vcc_enable_i2;
+    input fabric_spi_vcc_enable_i3;
+    output fabric_spi_vcc_used_o1;
+    output fabric_spi_vcc_used_o2;
+    output fabric_spi_vcc_used_o3;
+    input fabric_spw0_apb_slv_paddr_i1;
+    input fabric_spw0_apb_slv_paddr_i2;
+    input fabric_spw0_apb_slv_paddr_i3;
+    input fabric_spw0_apb_slv_paddr_i4;
+    input fabric_spw0_apb_slv_paddr_i5;
+    input fabric_spw0_apb_slv_penable_i;
+    output fabric_spw0_apb_slv_prdata_o1;
+    output fabric_spw0_apb_slv_prdata_o10;
+    output fabric_spw0_apb_slv_prdata_o11;
+    output fabric_spw0_apb_slv_prdata_o12;
+    output fabric_spw0_apb_slv_prdata_o13;
+    output fabric_spw0_apb_slv_prdata_o14;
+    output fabric_spw0_apb_slv_prdata_o15;
+    output fabric_spw0_apb_slv_prdata_o16;
+    output fabric_spw0_apb_slv_prdata_o17;
+    output fabric_spw0_apb_slv_prdata_o18;
+    output fabric_spw0_apb_slv_prdata_o19;
+    output fabric_spw0_apb_slv_prdata_o2;
+    output fabric_spw0_apb_slv_prdata_o20;
+    output fabric_spw0_apb_slv_prdata_o21;
+    output fabric_spw0_apb_slv_prdata_o22;
+    output fabric_spw0_apb_slv_prdata_o23;
+    output fabric_spw0_apb_slv_prdata_o24;
+    output fabric_spw0_apb_slv_prdata_o25;
+    output fabric_spw0_apb_slv_prdata_o26;
+    output fabric_spw0_apb_slv_prdata_o27;
+    output fabric_spw0_apb_slv_prdata_o28;
+    output fabric_spw0_apb_slv_prdata_o29;
+    output fabric_spw0_apb_slv_prdata_o3;
+    output fabric_spw0_apb_slv_prdata_o30;
+    output fabric_spw0_apb_slv_prdata_o31;
+    output fabric_spw0_apb_slv_prdata_o4;
+    output fabric_spw0_apb_slv_prdata_o5;
+    output fabric_spw0_apb_slv_prdata_o6;
+    output fabric_spw0_apb_slv_prdata_o7;
+    output fabric_spw0_apb_slv_prdata_o8;
+    output fabric_spw0_apb_slv_prdata_o9;
+    output fabric_spw0_apb_slv_pready_o;
+    input fabric_spw0_apb_slv_psel_i;
+    output fabric_spw0_apb_slv_pslverr_o;
+    input fabric_spw0_apb_slv_pwdata_i1;
+    input fabric_spw0_apb_slv_pwdata_i10;
+    input fabric_spw0_apb_slv_pwdata_i11;
+    input fabric_spw0_apb_slv_pwdata_i12;
+    input fabric_spw0_apb_slv_pwdata_i13;
+    input fabric_spw0_apb_slv_pwdata_i14;
+    input fabric_spw0_apb_slv_pwdata_i15;
+    input fabric_spw0_apb_slv_pwdata_i16;
+    input fabric_spw0_apb_slv_pwdata_i17;
+    input fabric_spw0_apb_slv_pwdata_i18;
+    input fabric_spw0_apb_slv_pwdata_i19;
+    input fabric_spw0_apb_slv_pwdata_i2;
+    input fabric_spw0_apb_slv_pwdata_i20;
+    input fabric_spw0_apb_slv_pwdata_i21;
+    input fabric_spw0_apb_slv_pwdata_i22;
+    input fabric_spw0_apb_slv_pwdata_i23;
+    input fabric_spw0_apb_slv_pwdata_i24;
+    input fabric_spw0_apb_slv_pwdata_i25;
+    input fabric_spw0_apb_slv_pwdata_i26;
+    input fabric_spw0_apb_slv_pwdata_i27;
+    input fabric_spw0_apb_slv_pwdata_i28;
+    input fabric_spw0_apb_slv_pwdata_i29;
+    input fabric_spw0_apb_slv_pwdata_i3;
+    input fabric_spw0_apb_slv_pwdata_i30;
+    input fabric_spw0_apb_slv_pwdata_i31;
+    input fabric_spw0_apb_slv_pwdata_i4;
+    input fabric_spw0_apb_slv_pwdata_i5;
+    input fabric_spw0_apb_slv_pwdata_i6;
+    input fabric_spw0_apb_slv_pwdata_i7;
+    input fabric_spw0_apb_slv_pwdata_i8;
+    input fabric_spw0_apb_slv_pwdata_i9;
+    input fabric_spw0_apb_slv_pwrite_i;
+    input fabric_spw0_clk_i;
+    input fabric_spw0_clk_tx_i;
+    input fabric_spw0_rst_n_i;
+    output fabric_spw0_rx_fifo_data_o1;
+    output fabric_spw0_rx_fifo_data_o2;
+    output fabric_spw0_rx_fifo_data_o3;
+    output fabric_spw0_rx_fifo_data_o4;
+    output fabric_spw0_rx_fifo_data_o5;
+    output fabric_spw0_rx_fifo_data_o6;
+    output fabric_spw0_rx_fifo_data_o7;
+    output fabric_spw0_rx_fifo_data_o8;
+    output fabric_spw0_rx_fifo_data_o9;
+    output fabric_spw0_rx_fifo_empty_o;
+    input fabric_spw0_rx_fifo_read_i;
+    input fabric_spw0_tick_ctm_i;
+    output fabric_spw0_tick_ctm_o;
+    input fabric_spw0_tx_fifo_data_i1;
+    input fabric_spw0_tx_fifo_data_i2;
+    input fabric_spw0_tx_fifo_data_i3;
+    input fabric_spw0_tx_fifo_data_i4;
+    input fabric_spw0_tx_fifo_data_i5;
+    input fabric_spw0_tx_fifo_data_i6;
+    input fabric_spw0_tx_fifo_data_i7;
+    input fabric_spw0_tx_fifo_data_i8;
+    input fabric_spw0_tx_fifo_data_i9;
+    output fabric_spw0_tx_fifo_full_o;
+    input fabric_spw0_tx_fifo_write_i;
+    output fabric_spw0_user_shared_o;
+    input fabric_spw1_apb_slv_paddr_i1;
+    input fabric_spw1_apb_slv_paddr_i2;
+    input fabric_spw1_apb_slv_paddr_i3;
+    input fabric_spw1_apb_slv_paddr_i4;
+    input fabric_spw1_apb_slv_paddr_i5;
+    input fabric_spw1_apb_slv_penable_i;
+    output fabric_spw1_apb_slv_prdata_o1;
+    output fabric_spw1_apb_slv_prdata_o10;
+    output fabric_spw1_apb_slv_prdata_o11;
+    output fabric_spw1_apb_slv_prdata_o12;
+    output fabric_spw1_apb_slv_prdata_o13;
+    output fabric_spw1_apb_slv_prdata_o14;
+    output fabric_spw1_apb_slv_prdata_o15;
+    output fabric_spw1_apb_slv_prdata_o16;
+    output fabric_spw1_apb_slv_prdata_o17;
+    output fabric_spw1_apb_slv_prdata_o18;
+    output fabric_spw1_apb_slv_prdata_o19;
+    output fabric_spw1_apb_slv_prdata_o2;
+    output fabric_spw1_apb_slv_prdata_o20;
+    output fabric_spw1_apb_slv_prdata_o21;
+    output fabric_spw1_apb_slv_prdata_o22;
+    output fabric_spw1_apb_slv_prdata_o23;
+    output fabric_spw1_apb_slv_prdata_o24;
+    output fabric_spw1_apb_slv_prdata_o25;
+    output fabric_spw1_apb_slv_prdata_o26;
+    output fabric_spw1_apb_slv_prdata_o27;
+    output fabric_spw1_apb_slv_prdata_o28;
+    output fabric_spw1_apb_slv_prdata_o29;
+    output fabric_spw1_apb_slv_prdata_o3;
+    output fabric_spw1_apb_slv_prdata_o30;
+    output fabric_spw1_apb_slv_prdata_o31;
+    output fabric_spw1_apb_slv_prdata_o4;
+    output fabric_spw1_apb_slv_prdata_o5;
+    output fabric_spw1_apb_slv_prdata_o6;
+    output fabric_spw1_apb_slv_prdata_o7;
+    output fabric_spw1_apb_slv_prdata_o8;
+    output fabric_spw1_apb_slv_prdata_o9;
+    output fabric_spw1_apb_slv_pready_o;
+    input fabric_spw1_apb_slv_psel_i;
+    output fabric_spw1_apb_slv_pslverr_o;
+    input fabric_spw1_apb_slv_pwdata_i1;
+    input fabric_spw1_apb_slv_pwdata_i10;
+    input fabric_spw1_apb_slv_pwdata_i11;
+    input fabric_spw1_apb_slv_pwdata_i12;
+    input fabric_spw1_apb_slv_pwdata_i13;
+    input fabric_spw1_apb_slv_pwdata_i14;
+    input fabric_spw1_apb_slv_pwdata_i15;
+    input fabric_spw1_apb_slv_pwdata_i16;
+    input fabric_spw1_apb_slv_pwdata_i17;
+    input fabric_spw1_apb_slv_pwdata_i18;
+    input fabric_spw1_apb_slv_pwdata_i19;
+    input fabric_spw1_apb_slv_pwdata_i2;
+    input fabric_spw1_apb_slv_pwdata_i20;
+    input fabric_spw1_apb_slv_pwdata_i21;
+    input fabric_spw1_apb_slv_pwdata_i22;
+    input fabric_spw1_apb_slv_pwdata_i23;
+    input fabric_spw1_apb_slv_pwdata_i24;
+    input fabric_spw1_apb_slv_pwdata_i25;
+    input fabric_spw1_apb_slv_pwdata_i26;
+    input fabric_spw1_apb_slv_pwdata_i27;
+    input fabric_spw1_apb_slv_pwdata_i28;
+    input fabric_spw1_apb_slv_pwdata_i29;
+    input fabric_spw1_apb_slv_pwdata_i3;
+    input fabric_spw1_apb_slv_pwdata_i30;
+    input fabric_spw1_apb_slv_pwdata_i31;
+    input fabric_spw1_apb_slv_pwdata_i4;
+    input fabric_spw1_apb_slv_pwdata_i5;
+    input fabric_spw1_apb_slv_pwdata_i6;
+    input fabric_spw1_apb_slv_pwdata_i7;
+    input fabric_spw1_apb_slv_pwdata_i8;
+    input fabric_spw1_apb_slv_pwdata_i9;
+    input fabric_spw1_apb_slv_pwrite_i;
+    input fabric_spw1_clk_i;
+    input fabric_spw1_clk_tx_i;
+    input fabric_spw1_rst_n_i;
+    output fabric_spw1_rx_fifo_data_o1;
+    output fabric_spw1_rx_fifo_data_o2;
+    output fabric_spw1_rx_fifo_data_o3;
+    output fabric_spw1_rx_fifo_data_o4;
+    output fabric_spw1_rx_fifo_data_o5;
+    output fabric_spw1_rx_fifo_data_o6;
+    output fabric_spw1_rx_fifo_data_o7;
+    output fabric_spw1_rx_fifo_data_o8;
+    output fabric_spw1_rx_fifo_data_o9;
+    output fabric_spw1_rx_fifo_empty_o;
+    input fabric_spw1_rx_fifo_read_i;
+    input fabric_spw1_tick_ctm_i;
+    output fabric_spw1_tick_ctm_o;
+    input fabric_spw1_tx_fifo_data_i1;
+    input fabric_spw1_tx_fifo_data_i2;
+    input fabric_spw1_tx_fifo_data_i3;
+    input fabric_spw1_tx_fifo_data_i4;
+    input fabric_spw1_tx_fifo_data_i5;
+    input fabric_spw1_tx_fifo_data_i6;
+    input fabric_spw1_tx_fifo_data_i7;
+    input fabric_spw1_tx_fifo_data_i8;
+    input fabric_spw1_tx_fifo_data_i9;
+    output fabric_spw1_tx_fifo_full_o;
+    input fabric_spw1_tx_fifo_write_i;
+    output fabric_spw1_user_shared_o;
+    output fabric_status_cold_start_o;
+    input fabric_thsens_arst_tmr_n_i1;
+    input fabric_thsens_arst_tmr_n_i2;
+    input fabric_thsens_arst_tmr_n_i3;
+    input fabric_thsens_clk_div_ratio_i1;
+    input fabric_thsens_clk_div_ratio_i2;
+    input fabric_thsens_clk_div_ratio_i3;
+    input fabric_thsens_clk_div_ratio_i4;
+    input fabric_thsens_clk_div_ratio_i5;
+    input fabric_thsens_clk_div_ratio_i6;
+    input fabric_thsens_clk_div_ratio_i7;
+    input fabric_thsens_clk_div_ratio_i8;
+    input fabric_thsens_clk_i;
+    output fabric_thsens_fm_config_r_o1;
+    output fabric_thsens_fm_config_r_o10;
+    output fabric_thsens_fm_config_r_o11;
+    output fabric_thsens_fm_config_r_o12;
+    output fabric_thsens_fm_config_r_o13;
+    output fabric_thsens_fm_config_r_o14;
+    output fabric_thsens_fm_config_r_o15;
+    output fabric_thsens_fm_config_r_o16;
+    output fabric_thsens_fm_config_r_o17;
+    output fabric_thsens_fm_config_r_o18;
+    output fabric_thsens_fm_config_r_o19;
+    output fabric_thsens_fm_config_r_o2;
+    output fabric_thsens_fm_config_r_o20;
+    output fabric_thsens_fm_config_r_o21;
+    output fabric_thsens_fm_config_r_o22;
+    output fabric_thsens_fm_config_r_o23;
+    output fabric_thsens_fm_config_r_o24;
+    output fabric_thsens_fm_config_r_o25;
+    output fabric_thsens_fm_config_r_o26;
+    output fabric_thsens_fm_config_r_o27;
+    output fabric_thsens_fm_config_r_o3;
+    output fabric_thsens_fm_config_r_o4;
+    output fabric_thsens_fm_config_r_o5;
+    output fabric_thsens_fm_config_r_o6;
+    output fabric_thsens_fm_config_r_o7;
+    output fabric_thsens_fm_config_r_o8;
+    output fabric_thsens_fm_config_r_o9;
+    input fabric_thsens_fm_config_w_i1;
+    input fabric_thsens_fm_config_w_i10;
+    input fabric_thsens_fm_config_w_i11;
+    input fabric_thsens_fm_config_w_i12;
+    input fabric_thsens_fm_config_w_i13;
+    input fabric_thsens_fm_config_w_i14;
+    input fabric_thsens_fm_config_w_i15;
+    input fabric_thsens_fm_config_w_i16;
+    input fabric_thsens_fm_config_w_i17;
+    input fabric_thsens_fm_config_w_i18;
+    input fabric_thsens_fm_config_w_i19;
+    input fabric_thsens_fm_config_w_i2;
+    input fabric_thsens_fm_config_w_i20;
+    input fabric_thsens_fm_config_w_i21;
+    input fabric_thsens_fm_config_w_i22;
+    input fabric_thsens_fm_config_w_i23;
+    input fabric_thsens_fm_config_w_i24;
+    input fabric_thsens_fm_config_w_i25;
+    input fabric_thsens_fm_config_w_i26;
+    input fabric_thsens_fm_config_w_i27;
+    input fabric_thsens_fm_config_w_i3;
+    input fabric_thsens_fm_config_w_i4;
+    input fabric_thsens_fm_config_w_i5;
+    input fabric_thsens_fm_config_w_i6;
+    input fabric_thsens_fm_config_w_i7;
+    input fabric_thsens_fm_config_w_i8;
+    input fabric_thsens_fm_config_w_i9;
+    input fabric_thsens_fm_config_wen_i;
+    output fabric_thsens_fm_data_o1;
+    output fabric_thsens_fm_data_o10;
+    output fabric_thsens_fm_data_o11;
+    output fabric_thsens_fm_data_o12;
+    output fabric_thsens_fm_data_o13;
+    output fabric_thsens_fm_data_o14;
+    output fabric_thsens_fm_data_o2;
+    output fabric_thsens_fm_data_o3;
+    output fabric_thsens_fm_data_o4;
+    output fabric_thsens_fm_data_o5;
+    output fabric_thsens_fm_data_o6;
+    output fabric_thsens_fm_data_o7;
+    output fabric_thsens_fm_data_o8;
+    output fabric_thsens_fm_data_o9;
+    input fabric_thsens_fm_enable_i;
+    output fabric_thsens_fm_mode_r_o1;
+    output fabric_thsens_fm_mode_r_o10;
+    output fabric_thsens_fm_mode_r_o11;
+    output fabric_thsens_fm_mode_r_o12;
+    output fabric_thsens_fm_mode_r_o13;
+    output fabric_thsens_fm_mode_r_o14;
+    output fabric_thsens_fm_mode_r_o15;
+    output fabric_thsens_fm_mode_r_o16;
+    output fabric_thsens_fm_mode_r_o17;
+    output fabric_thsens_fm_mode_r_o18;
+    output fabric_thsens_fm_mode_r_o19;
+    output fabric_thsens_fm_mode_r_o2;
+    output fabric_thsens_fm_mode_r_o20;
+    output fabric_thsens_fm_mode_r_o21;
+    output fabric_thsens_fm_mode_r_o22;
+    output fabric_thsens_fm_mode_r_o23;
+    output fabric_thsens_fm_mode_r_o24;
+    output fabric_thsens_fm_mode_r_o25;
+    output fabric_thsens_fm_mode_r_o26;
+    output fabric_thsens_fm_mode_r_o27;
+    output fabric_thsens_fm_mode_r_o28;
+    output fabric_thsens_fm_mode_r_o29;
+    output fabric_thsens_fm_mode_r_o3;
+    output fabric_thsens_fm_mode_r_o30;
+    output fabric_thsens_fm_mode_r_o31;
+    output fabric_thsens_fm_mode_r_o32;
+    output fabric_thsens_fm_mode_r_o4;
+    output fabric_thsens_fm_mode_r_o5;
+    output fabric_thsens_fm_mode_r_o6;
+    output fabric_thsens_fm_mode_r_o7;
+    output fabric_thsens_fm_mode_r_o8;
+    output fabric_thsens_fm_mode_r_o9;
+    input fabric_thsens_fm_mode_w_i1;
+    input fabric_thsens_fm_mode_w_i10;
+    input fabric_thsens_fm_mode_w_i11;
+    input fabric_thsens_fm_mode_w_i12;
+    input fabric_thsens_fm_mode_w_i13;
+    input fabric_thsens_fm_mode_w_i14;
+    input fabric_thsens_fm_mode_w_i15;
+    input fabric_thsens_fm_mode_w_i16;
+    input fabric_thsens_fm_mode_w_i17;
+    input fabric_thsens_fm_mode_w_i18;
+    input fabric_thsens_fm_mode_w_i19;
+    input fabric_thsens_fm_mode_w_i2;
+    input fabric_thsens_fm_mode_w_i20;
+    input fabric_thsens_fm_mode_w_i21;
+    input fabric_thsens_fm_mode_w_i22;
+    input fabric_thsens_fm_mode_w_i23;
+    input fabric_thsens_fm_mode_w_i24;
+    input fabric_thsens_fm_mode_w_i25;
+    input fabric_thsens_fm_mode_w_i26;
+    input fabric_thsens_fm_mode_w_i27;
+    input fabric_thsens_fm_mode_w_i28;
+    input fabric_thsens_fm_mode_w_i29;
+    input fabric_thsens_fm_mode_w_i3;
+    input fabric_thsens_fm_mode_w_i30;
+    input fabric_thsens_fm_mode_w_i31;
+    input fabric_thsens_fm_mode_w_i32;
+    input fabric_thsens_fm_mode_w_i4;
+    input fabric_thsens_fm_mode_w_i5;
+    input fabric_thsens_fm_mode_w_i6;
+    input fabric_thsens_fm_mode_w_i7;
+    input fabric_thsens_fm_mode_w_i8;
+    input fabric_thsens_fm_mode_w_i9;
+    input fabric_thsens_fm_mode_wen_i;
+    output fabric_thsens_fm_overflow_o;
+    output fabric_thsens_fm_valid_o;
+    output fabric_thsens_otp_config_o1;
+    output fabric_thsens_otp_config_o10;
+    output fabric_thsens_otp_config_o11;
+    output fabric_thsens_otp_config_o12;
+    output fabric_thsens_otp_config_o13;
+    output fabric_thsens_otp_config_o14;
+    output fabric_thsens_otp_config_o15;
+    output fabric_thsens_otp_config_o16;
+    output fabric_thsens_otp_config_o17;
+    output fabric_thsens_otp_config_o18;
+    output fabric_thsens_otp_config_o19;
+    output fabric_thsens_otp_config_o2;
+    output fabric_thsens_otp_config_o20;
+    output fabric_thsens_otp_config_o21;
+    output fabric_thsens_otp_config_o22;
+    output fabric_thsens_otp_config_o23;
+    output fabric_thsens_otp_config_o24;
+    output fabric_thsens_otp_config_o25;
+    output fabric_thsens_otp_config_o26;
+    output fabric_thsens_otp_config_o27;
+    output fabric_thsens_otp_config_o3;
+    output fabric_thsens_otp_config_o4;
+    output fabric_thsens_otp_config_o5;
+    output fabric_thsens_otp_config_o6;
+    output fabric_thsens_otp_config_o7;
+    output fabric_thsens_otp_config_o8;
+    output fabric_thsens_otp_config_o9;
+    input fabric_thsens_tst_scanenable_i;
+    input fabric_thsens_tst_scanin1_i;
+    input fabric_thsens_tst_scanin2_i;
+    output fabric_thsens_tst_scanout1_o;
+    output fabric_thsens_tst_scanout2_o;
+    input fabric_user_clk_i;
+    input fabric_user_data_i1;
+    input fabric_user_data_i10;
+    input fabric_user_data_i11;
+    input fabric_user_data_i12;
+    input fabric_user_data_i13;
+    input fabric_user_data_i14;
+    input fabric_user_data_i15;
+    input fabric_user_data_i16;
+    input fabric_user_data_i17;
+    input fabric_user_data_i18;
+    input fabric_user_data_i19;
+    input fabric_user_data_i2;
+    input fabric_user_data_i20;
+    input fabric_user_data_i21;
+    input fabric_user_data_i22;
+    input fabric_user_data_i23;
+    input fabric_user_data_i24;
+    input fabric_user_data_i25;
+    input fabric_user_data_i26;
+    input fabric_user_data_i27;
+    input fabric_user_data_i28;
+    input fabric_user_data_i29;
+    input fabric_user_data_i3;
+    input fabric_user_data_i30;
+    input fabric_user_data_i31;
+    input fabric_user_data_i32;
+    input fabric_user_data_i4;
+    input fabric_user_data_i5;
+    input fabric_user_data_i6;
+    input fabric_user_data_i7;
+    input fabric_user_data_i8;
+    input fabric_user_data_i9;
+    output fabric_user_data_o1;
+    output fabric_user_data_o10;
+    output fabric_user_data_o11;
+    output fabric_user_data_o12;
+    output fabric_user_data_o13;
+    output fabric_user_data_o14;
+    output fabric_user_data_o15;
+    output fabric_user_data_o16;
+    output fabric_user_data_o17;
+    output fabric_user_data_o18;
+    output fabric_user_data_o19;
+    output fabric_user_data_o2;
+    output fabric_user_data_o20;
+    output fabric_user_data_o21;
+    output fabric_user_data_o22;
+    output fabric_user_data_o23;
+    output fabric_user_data_o24;
+    output fabric_user_data_o25;
+    output fabric_user_data_o26;
+    output fabric_user_data_o27;
+    output fabric_user_data_o28;
+    output fabric_user_data_o29;
+    output fabric_user_data_o3;
+    output fabric_user_data_o30;
+    output fabric_user_data_o31;
+    output fabric_user_data_o32;
+    output fabric_user_data_o4;
+    output fabric_user_data_o5;
+    output fabric_user_data_o6;
+    output fabric_user_data_o7;
+    output fabric_user_data_o8;
+    output fabric_user_data_o9;
+    output fabric_user_read_cycle_o;
+    output fabric_user_write_cycle_o;
+    parameter bsm_config = 0;
+endmodule
+
+(* blackbox *)
+module NX_SERVICE_IF_U_FULL_WRAP(fabric_mrepair_clk_i, fabric_clk_otp_mrepair_o, fabric_mrepair_cke_i, fabric_mrepair_por_i, fabric_mrepair_cke_force_i, fabric_mrepair_rst_n_i, fabric_mrepair_initn_i, fabric_mrepair_bist_mode_o, fabric_mrepair_bend_i, fabric_mrepair_global_bbad_i, fabric_mrepair_global_repairable_i, fabric_mrepair_bypass_o, fabric_mrepair_memsafe_o, fabric_mrepair_mem_atpg_mode_o, fabric_mrepair_tst_gatedclock_o, fabric_mrepair_test_se_o, fabric_mrepair_data_to_system_o, fabric_mrepair_tst_atpg_mrepair_i, fabric_mrepair_data_from_system_i, fabric_mrepair_end_encoding_i, fabric_mrepair_system_dataready_o
+, fabric_mrepair_decoder_init_ready_o, fabric_mrepair_fuse_pdn_i, fabric_mrepair_fuse_bistmode_i, fabric_mrepair_fuse_tm_i, fabric_mrepair_fuse_read_i, fabric_mrepair_fuse_prog_i, fabric_mrepair_fuse_rbact1_i, fabric_mrepair_fuse_rbact2_i, fabric_mrepair_fuse_tstscanenable_i, fabric_mrepair_fuse_eccbypass_i, fabric_mrepair_fuse_wordlock_i, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_redbypass_i, fabric_mrepair_fuse_disturbchecked_i, fabric_mrepair_data_shift_en_i, fabric_mrepair_fuse_pwok_o, fabric_mrepair_fuse_ack_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_ded_o, fabric_mrepair_fuse_progfail_o, fabric_mrepair_fuse_locked_o
+, fabric_mrepair_fuse_disturbed_o, fabric_mrepair_fuse_bend1_o, fabric_mrepair_fuse_bend2_o, fabric_mrepair_fuse_bbad_o, fabric_mrepair_fuse_calibrated_o, fabric_mrepair_fuse_ready_o, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_otp_user_clk_i, fabric_otp_user_bistmode_i, fabric_otp_user_disturbcheck_i, fabric_otp_user_eccbypass_i, fabric_otp_user_pdn_i, fabric_otp_user_prog_i, fabric_otp_user_rbact1_i, fabric_otp_user_rbact2_i, fabric_otp_user_read_i, fabric_otp_user_redbypass_i, fabric_otp_user_suppadd_i, fabric_otp_user_tm_i, fabric_otp_user_tst_scanenable_i, fabric_otp_user_wordlock_i
+, fabric_otp_user_clock_frequency_range_i, fabric_otp_user_ack_o, fabric_otp_user_bbad_o, fabric_otp_user_bend1_o, fabric_otp_user_bend2_o, fabric_otp_user_calibrated_o, fabric_otp_user_ded_o, fabric_otp_user_disturbed_o, fabric_otp_user_locked_o, fabric_otp_user_progfail_o, fabric_otp_user_pwok_o, fabric_otp_user_sec_o, fabric_clk_bsm_o, fabric_clk_otp_mux_i, fabric_clk_otp_o, fabric_clk_user0_o, fabric_clk_user1_o, fabric_user_clk_i, fabric_user_write_cycle_o, fabric_user_read_cycle_o, fabric_cfg_fabric_user_flag_o
+, fabric_cfg_fabric_user_enable_o, fabric_parusr_clk_i, fabric_parusr_enable_i, fabric_parusr_cs_i, fabric_parusr_data_val_o, fabric_jtag_tck_o, fabric_jtag_trst_n_o, fabric_jtag_tms_o, fabric_jtag_tdi_o, fabric_jtag_usr1_o, fabric_jtag_usr2_o, fabric_jtag_tdo_usr1_i, fabric_jtag_tdo_usr2_i, fabric_otp_clk_i, fabric_otp_rst_i, fabric_otp_apb_write_i, fabric_otp_apb_sel_i, fabric_otp_apb_enable_i, fabric_otp_apb_ready_o, fabric_otp_cfg_fabric_apb_en_i, fabric_otp_cfg_loader_read_en_i
+, fabric_otp_cfg_loader_write_en_i, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_cfg_clk_fab_en_i, fabric_otp_security_ack_o, fabric_otp_security_rbact1_i, fabric_otp_security_rbact2_i, fabric_otp_security_bistmode_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_bist_end1_o, fabric_otp_security_bist_end2_o, fabric_otp_security_bist_bad_o, fabric_otp_security_testmode_i, fabric_otp_security_scanenable_i, fabric_status_cold_start_o, fabric_flag_trigger0_o, fabric_flag_trigger1_o, fabric_debug_rst_soft_o, fabric_debug_error_o, fabric_debug_otp_manager_read_otp_o, fabric_debug_otp_manager_read_done_o, fabric_debug_frame_use_encryption_o
+, fabric_debug_key_correct_o, fabric_debug_otp_reload_err_o, fabric_debug_access_reg_data_ready_o, fabric_debug_security_error_read_o, fabric_debug_security_boot_done_o, fabric_debug_lock_reg_o, fabric_dac0_clk_i, fabric_dac0_clk_en_i, fabric_dac0_reg_pwr_down_n_i, fabric_dac0_rstn_i, fabric_dac0_op_en_i, fabric_dac0_filt_en_i, fabric_dac0_comp_en_i, fabric_dac0_comp_ref_sel_i, fabric_dac0_comp_hyst_en_i, fabric_dac0_comp_out_o, fabric_cfg_dac0_reg_vref_select_i, fabric_cfg_dac0_reg_cm_select_i, fabric_cfg_dac0_sync_i, fabric_dac1_clk_i, fabric_dac1_clk_en_i
+, fabric_dac1_reg_pwr_down_n_i, fabric_dac1_rstn_i, fabric_dac1_op_en_i, fabric_dac1_filt_en_i, fabric_dac1_comp_en_i, fabric_dac1_comp_ref_sel_i, fabric_dac1_comp_hyst_en_i, fabric_dac1_comp_out_o, fabric_cfg_dac1_reg_vref_select_i, fabric_cfg_dac1_reg_cm_select_i, fabric_cfg_dac1_sync_i, fabric_dac2_clk_i, fabric_dac2_clk_en_i, fabric_dac2_reg_pwr_down_n_i, fabric_dac2_rstn_i, fabric_dac2_op_en_i, fabric_dac2_filt_en_i, fabric_dac2_comp_en_i, fabric_dac2_comp_ref_sel_i, fabric_dac2_comp_hyst_en_i, fabric_dac2_comp_out_o
+, fabric_cfg_dac2_reg_vref_select_i, fabric_cfg_dac2_reg_cm_select_i, fabric_cfg_dac2_sync_i, fabric_dac3_clk_i, fabric_dac3_clk_en_i, fabric_dac3_reg_pwr_down_n_i, fabric_dac3_rstn_i, fabric_dac3_op_en_i, fabric_dac3_filt_en_i, fabric_dac3_comp_en_i, fabric_dac3_comp_ref_sel_i, fabric_dac3_comp_hyst_en_i, fabric_dac3_comp_out_o, fabric_cfg_dac3_reg_vref_select_i, fabric_cfg_dac3_reg_cm_select_i, fabric_cfg_dac3_sync_i, fabric_adc0_clk_i, fabric_adc0_cal_start_i, fabric_adc0_cal_done_o, fabric_adc0_cal_p_overflow_o, fabric_adc0_cal_p_underflow_o
+, fabric_adc0_cal_n_overflow_o, fabric_adc0_cal_n_underflow_o, fabric_adc0_dft_scan_en_i, fabric_adc0_usr_cke_i, fabric_adc0_usr_conv_start_i, fabric_adc0_usr_conv_done_o, fabric_cfg_adc0_conv_done_delayed_i, fabric_cfg_adc0_use_cdc_i, fabric_adc1_clk_i, fabric_adc1_cal_start_i, fabric_adc1_cal_done_o, fabric_adc1_cal_p_overflow_o, fabric_adc1_cal_p_underflow_o, fabric_adc1_cal_n_overflow_o, fabric_adc1_cal_n_underflow_o, fabric_adc1_dft_scan_en_i, fabric_adc1_usr_cke_i, fabric_adc1_usr_conv_start_i, fabric_adc1_usr_conv_done_o, fabric_cfg_adc1_conv_done_delayed_i, fabric_cfg_adc1_use_cdc_i
+, fabric_adc2_clk_i, fabric_adc2_cal_start_i, fabric_adc2_cal_done_o, fabric_adc2_cal_p_overflow_o, fabric_adc2_cal_p_underflow_o, fabric_adc2_cal_n_overflow_o, fabric_adc2_cal_n_underflow_o, fabric_adc2_dft_scan_en_i, fabric_adc2_usr_cke_i, fabric_adc2_usr_conv_start_i, fabric_adc2_usr_conv_done_o, fabric_cfg_adc2_conv_done_delayed_i, fabric_cfg_adc2_use_cdc_i, fabric_adc3_clk_i, fabric_adc3_cal_start_i, fabric_adc3_cal_done_o, fabric_adc3_cal_p_overflow_o, fabric_adc3_cal_p_underflow_o, fabric_adc3_cal_n_overflow_o, fabric_adc3_cal_n_underflow_o, fabric_adc3_dft_scan_en_i
+, fabric_adc3_usr_cke_i, fabric_adc3_usr_conv_start_i, fabric_adc3_usr_conv_done_o, fabric_cfg_adc3_conv_done_delayed_i, fabric_cfg_adc3_use_cdc_i, fabric_direct0_scan_en_i, fabric_direct0_loopback_en_i, fabric_direct0_loopback_mux_i, fabric_direct2_scan_en_i, fabric_direct2_loopback_en_i, fabric_direct2_loopback_mux_i, fabric_direct1_scan_en_i, fabric_direct1_loopback_en_i, fabric_direct1_loopback_mux_i, fabric_thsens_clk_i, fabric_thsens_fm_enable_i, fabric_thsens_fm_mode_wen_i, fabric_thsens_fm_config_wen_i, fabric_thsens_fm_valid_o, fabric_thsens_fm_overflow_o, fabric_thsens_tst_scanenable_i
+, fabric_thsens_tst_scanin1_i, fabric_thsens_tst_scanin2_i, fabric_thsens_tst_scanout1_o, fabric_thsens_tst_scanout2_o, fabric_spi_clk_i2, fabric_spi_sck_i2, fabric_spi_clk_i0, fabric_spi_sck_i0, fabric_spi_clk_i1, fabric_spi_sck_i1, fabric_spw0_clk_i, fabric_spw0_clk_tx_i, fabric_spw0_rst_n_i, fabric_spw0_user_shared_o, fabric_spw0_tx_fifo_write_i, fabric_spw0_tx_fifo_full_o, fabric_spw0_rx_fifo_read_i, fabric_spw0_rx_fifo_empty_o, fabric_spw0_tick_ctm_i, fabric_spw0_tick_ctm_o, fabric_spw0_apb_slv_psel_i
+, fabric_spw0_apb_slv_penable_i, fabric_spw0_apb_slv_pwrite_i, fabric_spw0_apb_slv_pready_o, fabric_spw0_apb_slv_pslverr_o, fabric_spw1_clk_i, fabric_spw1_clk_tx_i, fabric_spw1_rst_n_i, fabric_spw1_user_shared_o, fabric_spw1_tx_fifo_write_i, fabric_spw1_tx_fifo_full_o, fabric_spw1_rx_fifo_read_i, fabric_spw1_rx_fifo_empty_o, fabric_spw1_tick_ctm_i, fabric_spw1_tick_ctm_o, fabric_spw1_apb_slv_psel_i, fabric_spw1_apb_slv_penable_i, fabric_spw1_apb_slv_pwrite_i, fabric_spw1_apb_slv_pready_o, fabric_spw1_apb_slv_pslverr_o, fabric_mrepair_data_to_bist_o, fabric_mrepair_shift_en_to_bist_o
+, fabric_mrepair_sif_load_en_to_bist_o, fabric_mrepair_sif_update_en_to_bist_o, fabric_mrepair_sif_reg_en_to_bist_o, fabric_mrepair_system_data_to_mem_bist_i, fabric_mrepair_shift_en_i, fabric_mrepair_sif_load_en_i, fabric_mrepair_sif_update_en_i, fabric_mrepair_sif_reg_en_i, fabric_mrepair_system_data_from_mem_bist_o, fabric_mrepair_mem_type_sel_o, fabric_mrepair_mode_sel_o, fabric_mrepair_mode_i, fabric_mrepair_pd_active_i, fabric_mrepair_chip_status_o, fabric_mrepair_global_chip_status_o, fabric_mrepair_pd_ready_o, fabric_mrepair_fuse_add_i, fabric_mrepair_fuse_din_i, fabric_mrepair_fuse_tst_scanin_i, fabric_mrepair_fuse_prgwidth_i, fabric_mrepair_fuse_dout_o
+, fabric_mrepair_fuse_startword_o, fabric_mrepair_fuse_wlromout_o, fabric_mrepair_fuse_bist1fail_o, fabric_mrepair_fuse_bist2fail_o, fabric_mrepair_fuse_tstscanout_o, fabric_mrepair_fuse_flagstate_o, fabric_mrepair_fuse_status_o, fabric_otp_user_add_i, fabric_otp_user_din_i, fabric_otp_user_prgwidth_i, fabric_otp_user_tst_scanin_i, fabric_otp_user_bist1fail_o, fabric_otp_user_bist2fail_o, fabric_otp_user_dout_o, fabric_otp_user_flagstate_o, fabric_otp_user_startword_o, fabric_otp_user_tst_scanout_o, fabric_otp_user_wlromout_o, fabric_io_in_i, fabric_io_oe_i, fabric_io_out_o
+, fabric_user_data_i, fabric_user_data_o, fabric_parusr_type_i, fabric_parusr_data_i, fabric_parusr_data_o, fabric_direct_data_i, fabric_direct_data_o, fabric_otp_apb_addr_i, fabric_otp_apb_wdata_i, fabric_otp_apb_rdata_o, fabric_otp_security_bist_fail1_o, fabric_otp_security_bist_fail2_o, fabric_otp_security_scanin_i, fabric_otp_security_scanout_o, fabric_flag_ready_TMR_o, fabric_debug_lifecycle_o, fabric_debug_fsm_state_o, fabric_debug_direct_permission_write_o, fabric_debug_direct_permission_read_o, fabric_debug_frame_permission_frame_o, fabric_debug_otpmgmt_state_o
+, fabric_debug_otpapb_state_o, fabric_debug_otpboot_state_o, fabric_debug_cpt_retry_o, fabric_debug_bsec_core_status_o, fabric_debug_otpboot_curr_addr_o, fabric_enable_TMR_i, fabric_lowskew_i, fabric_lowskew_o, fabric_spare_i, fabric_spare_o, fabric_dac0_din_i, fabric_dac0_comp_in_sel_i, fabric_cfg_dac0_reg_res_i, fabric_dac1_din_i, fabric_dac1_comp_in_sel_i, fabric_cfg_dac1_reg_res_i, fabric_dac2_din_i, fabric_dac2_comp_in_sel_i, fabric_cfg_dac2_reg_res_i, fabric_dac3_din_i, fabric_dac3_comp_in_sel_i
+, fabric_cfg_dac3_reg_res_i, fabric_adc0_arst_b_tmr_i, fabric_adc0_pwr_down_b_tmr_i, fabric_adc0_spare_i, fabric_adc0_dft_test_mode_i, fabric_adc0_dft_si_i, fabric_adc0_usr_arst_b_tmr_i, fabric_adc0_usr_channel_i, fabric_adc0_usr_sample_o, fabric_adc0_usr_sample_lsb_i, fabric_adc0_dbg_addr_i, fabric_adc0_dbg_data_o, fabric_cfg_adc0_clk_cal_div_ratio_i, fabric_adc1_arst_b_tmr_i, fabric_adc1_pwr_down_b_tmr_i, fabric_adc1_spare_i, fabric_adc1_dft_test_mode_i, fabric_adc1_dft_si_i, fabric_adc1_usr_arst_b_tmr_i, fabric_adc1_usr_channel_i, fabric_adc1_usr_sample_o
+, fabric_adc1_usr_sample_lsb_i, fabric_adc1_dbg_addr_i, fabric_adc1_dbg_data_o, fabric_cfg_adc1_clk_cal_div_ratio_i, fabric_adc2_arst_b_tmr_i, fabric_adc2_pwr_down_b_tmr_i, fabric_adc2_spare_i, fabric_adc2_dft_test_mode_i, fabric_adc2_dft_si_i, fabric_adc2_usr_arst_b_tmr_i, fabric_adc2_usr_channel_i, fabric_adc2_usr_sample_o, fabric_adc2_usr_sample_lsb_i, fabric_adc2_dbg_addr_i, fabric_adc2_dbg_data_o, fabric_cfg_adc2_clk_cal_div_ratio_i, fabric_adc3_arst_b_tmr_i, fabric_adc3_pwr_down_b_tmr_i, fabric_adc3_spare_i, fabric_adc3_dft_test_mode_i, fabric_adc3_dft_si_i
+, fabric_adc3_usr_arst_b_tmr_i, fabric_adc3_usr_channel_i, fabric_adc3_usr_sample_o, fabric_adc3_usr_sample_lsb_i, fabric_adc3_dbg_addr_i, fabric_adc3_dbg_data_o, fabric_cfg_adc3_clk_cal_div_ratio_i, fabric_direct0_clock_fabric_i, fabric_direct0_oe_i, fabric_direct0_oe_ena_i, fabric_direct0_oe_rs_i, fabric_direct0_do_i, fabric_direct0_do_ena_i, fabric_direct0_do_rs_i, fabric_direct0_di_o, fabric_direct0_di_ena_i, fabric_direct0_di_rs_i, fabric_direct0_cfg_bank_i, fabric_direct0_cfg_pad_i, fabric_direct2_clock_fabric_i, fabric_direct2_oe_i
+, fabric_direct2_oe_ena_i, fabric_direct2_oe_rs_i, fabric_direct2_do_i, fabric_direct2_do_ena_i, fabric_direct2_do_rs_i, fabric_direct2_di_o, fabric_direct2_di_ena_i, fabric_direct2_di_rs_i, fabric_direct2_cfg_bank_i, fabric_direct2_cfg_pad_i, fabric_direct1_clock_fabric_i, fabric_direct1_oe_i, fabric_direct1_oe_ena_i, fabric_direct1_oe_rs_i, fabric_direct1_do_i, fabric_direct1_do_ena_i, fabric_direct1_do_rs_i, fabric_direct1_di_o, fabric_direct1_di_ena_i, fabric_direct1_di_rs_i, fabric_direct1_cfg_bank_i
+, fabric_direct1_cfg_pad_i, fabric_thsens_arst_tmr_n_i, fabric_thsens_fm_mode_w_i, fabric_thsens_fm_config_w_i, fabric_thsens_fm_data_o, fabric_thsens_fm_mode_r_o, fabric_thsens_fm_config_r_o, fabric_thsens_clk_div_ratio_i, fabric_thsens_otp_config_o, fabric_spi_needed_i, fabric_spi_bsm_release_o, fabric_spi_arst_tmr_n_i, fabric_spi_fifo_arst_tmr_n_i, fabric_spi_cpol_i, fabric_spi_cpha_i, fabric_spi_loopback_i, fabric_spi_lsb_first_i, fabric_spi_cs_setuptime_i, fabric_spi_cs_holdtime_i, fabric_spi_cs_offtime_i, fabric_spi_vcc_enable_i
+, fabric_spi_powerdown_cycle_i, fabric_spi_powerup_cycle_i, fabric_spi_legacy_enable_i, fabric_spi_legacy_master_i, fabric_spi_data_in_unlimited_i, fabric_spi_enable_i, fabric_spi_rst_n_i, fabric_spi_init_done_o, fabric_spi_busy_o, fabric_spi_vcc_used_o, fabric_spi_error_sel_o, fabric_spi_error_loopback_o, fabric_spi_error_mode_o, fabric_spi_error_endianness_o, fabric_spi_cmd_push_i, fabric_spi_cmd_full_o, fabric_spi_cmd_type_i, fabric_spi_cmd_mode_i, fabric_spi_cmd_bytes_i, fabric_spi_mosi_push_i, fabric_spi_mosi_full_o
+, fabric_spi_mosi_data_i, fabric_spi_mosi_data_inv_i, fabric_spi_miso_pop_i, fabric_spi_miso_empty_o, fabric_spi_miso_data_o, fabric_spi_miso_data_inv_o, fabric_spw0_tx_fifo_data_i, fabric_spw0_rx_fifo_data_o, fabric_spw0_apb_slv_paddr_i, fabric_spw0_apb_slv_pwdata_i, fabric_spw0_apb_slv_prdata_o, fabric_spw1_tx_fifo_data_i, fabric_spw1_rx_fifo_data_o, fabric_spw1_apb_slv_paddr_i, fabric_spw1_apb_slv_pwdata_i, fabric_spw1_apb_slv_prdata_o, fabric_mrepair_data_from_bist_i);
+    input [2:0] fabric_adc0_arst_b_tmr_i;
+    output fabric_adc0_cal_done_o;
+    output fabric_adc0_cal_n_overflow_o;
+    output fabric_adc0_cal_n_underflow_o;
+    output fabric_adc0_cal_p_overflow_o;
+    output fabric_adc0_cal_p_underflow_o;
+    input fabric_adc0_cal_start_i;
+    input fabric_adc0_clk_i;
+    input [3:0] fabric_adc0_dbg_addr_i;
+    output [31:0] fabric_adc0_dbg_data_o;
+    input fabric_adc0_dft_scan_en_i;
+    input [11:0] fabric_adc0_dft_si_i;
+    input [1:0] fabric_adc0_dft_test_mode_i;
+    input [2:0] fabric_adc0_pwr_down_b_tmr_i;
+    input [15:0] fabric_adc0_spare_i;
+    input [2:0] fabric_adc0_usr_arst_b_tmr_i;
+    input [2:0] fabric_adc0_usr_channel_i;
+    input fabric_adc0_usr_cke_i;
+    output fabric_adc0_usr_conv_done_o;
+    input fabric_adc0_usr_conv_start_i;
+    input [3:0] fabric_adc0_usr_sample_lsb_i;
+    output [11:0] fabric_adc0_usr_sample_o;
+    input [2:0] fabric_adc1_arst_b_tmr_i;
+    output fabric_adc1_cal_done_o;
+    output fabric_adc1_cal_n_overflow_o;
+    output fabric_adc1_cal_n_underflow_o;
+    output fabric_adc1_cal_p_overflow_o;
+    output fabric_adc1_cal_p_underflow_o;
+    input fabric_adc1_cal_start_i;
+    input fabric_adc1_clk_i;
+    input [3:0] fabric_adc1_dbg_addr_i;
+    output [31:0] fabric_adc1_dbg_data_o;
+    input fabric_adc1_dft_scan_en_i;
+    input [11:0] fabric_adc1_dft_si_i;
+    input [1:0] fabric_adc1_dft_test_mode_i;
+    input [2:0] fabric_adc1_pwr_down_b_tmr_i;
+    input [15:0] fabric_adc1_spare_i;
+    input [2:0] fabric_adc1_usr_arst_b_tmr_i;
+    input [2:0] fabric_adc1_usr_channel_i;
+    input fabric_adc1_usr_cke_i;
+    output fabric_adc1_usr_conv_done_o;
+    input fabric_adc1_usr_conv_start_i;
+    input [3:0] fabric_adc1_usr_sample_lsb_i;
+    output [11:0] fabric_adc1_usr_sample_o;
+    input [2:0] fabric_adc2_arst_b_tmr_i;
+    output fabric_adc2_cal_done_o;
+    output fabric_adc2_cal_n_overflow_o;
+    output fabric_adc2_cal_n_underflow_o;
+    output fabric_adc2_cal_p_overflow_o;
+    output fabric_adc2_cal_p_underflow_o;
+    input fabric_adc2_cal_start_i;
+    input fabric_adc2_clk_i;
+    input [3:0] fabric_adc2_dbg_addr_i;
+    output [31:0] fabric_adc2_dbg_data_o;
+    input fabric_adc2_dft_scan_en_i;
+    input [11:0] fabric_adc2_dft_si_i;
+    input [1:0] fabric_adc2_dft_test_mode_i;
+    input [2:0] fabric_adc2_pwr_down_b_tmr_i;
+    input [15:0] fabric_adc2_spare_i;
+    input [2:0] fabric_adc2_usr_arst_b_tmr_i;
+    input [2:0] fabric_adc2_usr_channel_i;
+    input fabric_adc2_usr_cke_i;
+    output fabric_adc2_usr_conv_done_o;
+    input fabric_adc2_usr_conv_start_i;
+    input [3:0] fabric_adc2_usr_sample_lsb_i;
+    output [11:0] fabric_adc2_usr_sample_o;
+    input [2:0] fabric_adc3_arst_b_tmr_i;
+    output fabric_adc3_cal_done_o;
+    output fabric_adc3_cal_n_overflow_o;
+    output fabric_adc3_cal_n_underflow_o;
+    output fabric_adc3_cal_p_overflow_o;
+    output fabric_adc3_cal_p_underflow_o;
+    input fabric_adc3_cal_start_i;
+    input fabric_adc3_clk_i;
+    input [3:0] fabric_adc3_dbg_addr_i;
+    output [31:0] fabric_adc3_dbg_data_o;
+    input fabric_adc3_dft_scan_en_i;
+    input [11:0] fabric_adc3_dft_si_i;
+    input [1:0] fabric_adc3_dft_test_mode_i;
+    input [2:0] fabric_adc3_pwr_down_b_tmr_i;
+    input [15:0] fabric_adc3_spare_i;
+    input [2:0] fabric_adc3_usr_arst_b_tmr_i;
+    input [2:0] fabric_adc3_usr_channel_i;
+    input fabric_adc3_usr_cke_i;
+    output fabric_adc3_usr_conv_done_o;
+    input fabric_adc3_usr_conv_start_i;
+    input [3:0] fabric_adc3_usr_sample_lsb_i;
+    output [11:0] fabric_adc3_usr_sample_o;
+    input [4:0] fabric_cfg_adc0_clk_cal_div_ratio_i;
+    input fabric_cfg_adc0_conv_done_delayed_i;
+    input fabric_cfg_adc0_use_cdc_i;
+    input [4:0] fabric_cfg_adc1_clk_cal_div_ratio_i;
+    input fabric_cfg_adc1_conv_done_delayed_i;
+    input fabric_cfg_adc1_use_cdc_i;
+    input [4:0] fabric_cfg_adc2_clk_cal_div_ratio_i;
+    input fabric_cfg_adc2_conv_done_delayed_i;
+    input fabric_cfg_adc2_use_cdc_i;
+    input [4:0] fabric_cfg_adc3_clk_cal_div_ratio_i;
+    input fabric_cfg_adc3_conv_done_delayed_i;
+    input fabric_cfg_adc3_use_cdc_i;
+    input fabric_cfg_dac0_reg_cm_select_i;
+    input [1:0] fabric_cfg_dac0_reg_res_i;
+    input fabric_cfg_dac0_reg_vref_select_i;
+    input fabric_cfg_dac0_sync_i;
+    input fabric_cfg_dac1_reg_cm_select_i;
+    input [1:0] fabric_cfg_dac1_reg_res_i;
+    input fabric_cfg_dac1_reg_vref_select_i;
+    input fabric_cfg_dac1_sync_i;
+    input fabric_cfg_dac2_reg_cm_select_i;
+    input [1:0] fabric_cfg_dac2_reg_res_i;
+    input fabric_cfg_dac2_reg_vref_select_i;
+    input fabric_cfg_dac2_sync_i;
+    input fabric_cfg_dac3_reg_cm_select_i;
+    input [1:0] fabric_cfg_dac3_reg_res_i;
+    input fabric_cfg_dac3_reg_vref_select_i;
+    input fabric_cfg_dac3_sync_i;
+    output fabric_cfg_fabric_user_enable_o;
+    output fabric_cfg_fabric_user_flag_o;
+    output fabric_clk_bsm_o;
+    output fabric_clk_otp_mrepair_o;
+    input fabric_clk_otp_mux_i;
+    output fabric_clk_otp_o;
+    output fabric_clk_user0_o;
+    output fabric_clk_user1_o;
+    input fabric_dac0_clk_en_i;
+    input fabric_dac0_clk_i;
+    input fabric_dac0_comp_en_i;
+    input fabric_dac0_comp_hyst_en_i;
+    input [3:0] fabric_dac0_comp_in_sel_i;
+    output fabric_dac0_comp_out_o;
+    input fabric_dac0_comp_ref_sel_i;
+    input [12:0] fabric_dac0_din_i;
+    input fabric_dac0_filt_en_i;
+    input fabric_dac0_op_en_i;
+    input fabric_dac0_reg_pwr_down_n_i;
+    input fabric_dac0_rstn_i;
+    input fabric_dac1_clk_en_i;
+    input fabric_dac1_clk_i;
+    input fabric_dac1_comp_en_i;
+    input fabric_dac1_comp_hyst_en_i;
+    input [3:0] fabric_dac1_comp_in_sel_i;
+    output fabric_dac1_comp_out_o;
+    input fabric_dac1_comp_ref_sel_i;
+    input [12:0] fabric_dac1_din_i;
+    input fabric_dac1_filt_en_i;
+    input fabric_dac1_op_en_i;
+    input fabric_dac1_reg_pwr_down_n_i;
+    input fabric_dac1_rstn_i;
+    input fabric_dac2_clk_en_i;
+    input fabric_dac2_clk_i;
+    input fabric_dac2_comp_en_i;
+    input fabric_dac2_comp_hyst_en_i;
+    input [12:0] fabric_dac2_comp_in_sel_i;
+    output fabric_dac2_comp_out_o;
+    input fabric_dac2_comp_ref_sel_i;
+    input [12:0] fabric_dac2_din_i;
+    input fabric_dac2_filt_en_i;
+    input fabric_dac2_op_en_i;
+    input fabric_dac2_reg_pwr_down_n_i;
+    input fabric_dac2_rstn_i;
+    input fabric_dac3_clk_en_i;
+    input fabric_dac3_clk_i;
+    input fabric_dac3_comp_en_i;
+    input fabric_dac3_comp_hyst_en_i;
+    input [3:0] fabric_dac3_comp_in_sel_i;
+    output fabric_dac3_comp_out_o;
+    input fabric_dac3_comp_ref_sel_i;
+    input [12:0] fabric_dac3_din_i;
+    input fabric_dac3_filt_en_i;
+    input fabric_dac3_op_en_i;
+    input fabric_dac3_reg_pwr_down_n_i;
+    input fabric_dac3_rstn_i;
+    output fabric_debug_access_reg_data_ready_o;
+    output [31:0] fabric_debug_bsec_core_status_o;
+    output [3:0] fabric_debug_cpt_retry_o;
+    output [3:0] fabric_debug_direct_permission_read_o;
+    output [3:0] fabric_debug_direct_permission_write_o;
+    output fabric_debug_error_o;
+    output [3:0] fabric_debug_frame_permission_frame_o;
+    output fabric_debug_frame_use_encryption_o;
+    output [2:0] fabric_debug_fsm_state_o;
+    output fabric_debug_key_correct_o;
+    output [3:0] fabric_debug_lifecycle_o;
+    output fabric_debug_lock_reg_o;
+    output fabric_debug_otp_manager_read_done_o;
+    output fabric_debug_otp_manager_read_otp_o;
+    output fabric_debug_otp_reload_err_o;
+    output [2:0] fabric_debug_otpapb_state_o;
+    output [7:0] fabric_debug_otpboot_curr_addr_o;
+    output [2:0] fabric_debug_otpboot_state_o;
+    output [2:0] fabric_debug_otpmgmt_state_o;
+    output fabric_debug_rst_soft_o;
+    output fabric_debug_security_boot_done_o;
+    output fabric_debug_security_error_read_o;
+    input [3:0] fabric_direct0_cfg_bank_i;
+    input [719:0] fabric_direct0_cfg_pad_i;
+    input [3:0] fabric_direct0_clock_fabric_i;
+    input [23:0] fabric_direct0_di_ena_i;
+    output [23:0] fabric_direct0_di_o;
+    input [23:0] fabric_direct0_di_rs_i;
+    input [23:0] fabric_direct0_do_ena_i;
+    input [23:0] fabric_direct0_do_i;
+    input [23:0] fabric_direct0_do_rs_i;
+    input fabric_direct0_loopback_en_i;
+    input fabric_direct0_loopback_mux_i;
+    input [23:0] fabric_direct0_oe_ena_i;
+    input [23:0] fabric_direct0_oe_i;
+    input [23:0] fabric_direct0_oe_rs_i;
+    input fabric_direct0_scan_en_i;
+    input [3:0] fabric_direct1_cfg_bank_i;
+    input [479:0] fabric_direct1_cfg_pad_i;
+    input [3:0] fabric_direct1_clock_fabric_i;
+    input [15:0] fabric_direct1_di_ena_i;
+    output [15:0] fabric_direct1_di_o;
+    input [15:0] fabric_direct1_di_rs_i;
+    input [15:0] fabric_direct1_do_ena_i;
+    input [15:0] fabric_direct1_do_i;
+    input [15:0] fabric_direct1_do_rs_i;
+    input fabric_direct1_loopback_en_i;
+    input fabric_direct1_loopback_mux_i;
+    input [15:0] fabric_direct1_oe_ena_i;
+    input [15:0] fabric_direct1_oe_i;
+    input [15:0] fabric_direct1_oe_rs_i;
+    input fabric_direct1_scan_en_i;
+    input [3:0] fabric_direct2_cfg_bank_i;
+    input [719:0] fabric_direct2_cfg_pad_i;
+    input [3:0] fabric_direct2_clock_fabric_i;
+    input [23:0] fabric_direct2_di_ena_i;
+    output [23:0] fabric_direct2_di_o;
+    input [23:0] fabric_direct2_di_rs_i;
+    input [23:0] fabric_direct2_do_ena_i;
+    input [23:0] fabric_direct2_do_i;
+    input [23:0] fabric_direct2_do_rs_i;
+    input fabric_direct2_loopback_en_i;
+    input fabric_direct2_loopback_mux_i;
+    input [23:0] fabric_direct2_oe_ena_i;
+    input [23:0] fabric_direct2_oe_i;
+    input [23:0] fabric_direct2_oe_rs_i;
+    input fabric_direct2_scan_en_i;
+    input [31:0] fabric_direct_data_i;
+    output [31:0] fabric_direct_data_o;
+    input [2:0] fabric_enable_TMR_i;
+    output [2:0] fabric_flag_ready_TMR_o;
+    output fabric_flag_trigger0_o;
+    output fabric_flag_trigger1_o;
+    input [34:0] fabric_io_in_i;
+    input [34:0] fabric_io_oe_i;
+    output [34:0] fabric_io_out_o;
+    output fabric_jtag_tck_o;
+    output fabric_jtag_tdi_o;
+    input fabric_jtag_tdo_usr1_i;
+    input fabric_jtag_tdo_usr2_i;
+    output fabric_jtag_tms_o;
+    output fabric_jtag_trst_n_o;
+    output fabric_jtag_usr1_o;
+    output fabric_jtag_usr2_o;
+    input [39:0] fabric_lowskew_i;
+    output [5:0] fabric_lowskew_o;
+    input fabric_mrepair_bend_i;
+    output fabric_mrepair_bist_mode_o;
+    output fabric_mrepair_bypass_o;
+    output [77:0] fabric_mrepair_chip_status_o;
+    input fabric_mrepair_cke_force_i;
+    input fabric_mrepair_cke_i;
+    input fabric_mrepair_clk_i;
+    input [25:0] fabric_mrepair_data_from_bist_i;
+    input fabric_mrepair_data_from_system_i;
+    input fabric_mrepair_data_shift_en_i;
+    output [25:0] fabric_mrepair_data_to_bist_o;
+    output fabric_mrepair_data_to_system_o;
+    output fabric_mrepair_decoder_init_ready_o;
+    input fabric_mrepair_end_encoding_i;
+    output fabric_mrepair_fuse_ack_o;
+    input [6:0] fabric_mrepair_fuse_add_i;
+    output fabric_mrepair_fuse_bbad_o;
+    output fabric_mrepair_fuse_bend1_o;
+    output fabric_mrepair_fuse_bend2_o;
+    output [7:0] fabric_mrepair_fuse_bist1fail_o;
+    output [6:0] fabric_mrepair_fuse_bist2fail_o;
+    input fabric_mrepair_fuse_bistmode_i;
+    output fabric_mrepair_fuse_calibrated_o;
+    output fabric_mrepair_fuse_ded_o;
+    input [38:0] fabric_mrepair_fuse_din_i;
+    input fabric_mrepair_fuse_disturbchecked_i;
+    output fabric_mrepair_fuse_disturbed_o;
+    output [40:0] fabric_mrepair_fuse_dout_o;
+    input fabric_mrepair_fuse_eccbypass_i;
+    output [3:0] fabric_mrepair_fuse_flagstate_o;
+    output fabric_mrepair_fuse_locked_o;
+    input fabric_mrepair_fuse_pdn_i;
+    output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o;
+    input [2:0] fabric_mrepair_fuse_prgwidth_i;
+    input fabric_mrepair_fuse_prog_i;
+    output fabric_mrepair_fuse_progfail_o;
+    output fabric_mrepair_fuse_pwok_o;
+    input fabric_mrepair_fuse_rbact1_i;
+    input fabric_mrepair_fuse_rbact2_i;
+    input fabric_mrepair_fuse_read_i;
+    output fabric_mrepair_fuse_ready_o;
+    input fabric_mrepair_fuse_redbypass_i;
+    output fabric_mrepair_fuse_sec_o;
+    output [15:0] fabric_mrepair_fuse_startword_o;
+    output [2:0] fabric_mrepair_fuse_status_o;
+    input fabric_mrepair_fuse_suppadd_i;
+    input fabric_mrepair_fuse_tm_i;
+    input [4:0] fabric_mrepair_fuse_tst_scanin_i;
+    input fabric_mrepair_fuse_tstscanenable_i;
+    output [4:0] fabric_mrepair_fuse_tstscanout_o;
+    output [9:0] fabric_mrepair_fuse_wlromout_o;
+    input fabric_mrepair_fuse_wordlock_i;
+    input fabric_mrepair_global_bbad_i;
+    output [2:0] fabric_mrepair_global_chip_status_o;
+    input fabric_mrepair_global_repairable_i;
+    input fabric_mrepair_initn_i;
+    output fabric_mrepair_mem_atpg_mode_o;
+    output [4:0] fabric_mrepair_mem_type_sel_o;
+    output fabric_mrepair_memsafe_o;
+    input [3:0] fabric_mrepair_mode_i;
+    output [3:0] fabric_mrepair_mode_sel_o;
+    input [25:0] fabric_mrepair_pd_active_i;
+    output [25:0] fabric_mrepair_pd_ready_o;
+    input fabric_mrepair_por_i;
+    input fabric_mrepair_rst_n_i;
+    input [25:0] fabric_mrepair_shift_en_i;
+    output [25:0] fabric_mrepair_shift_en_to_bist_o;
+    input [25:0] fabric_mrepair_sif_load_en_i;
+    output [25:0] fabric_mrepair_sif_load_en_to_bist_o;
+    input [25:0] fabric_mrepair_sif_reg_en_i;
+    output [25:0] fabric_mrepair_sif_reg_en_to_bist_o;
+    input [25:0] fabric_mrepair_sif_update_en_i;
+    output [25:0] fabric_mrepair_sif_update_en_to_bist_o;
+    output [25:0] fabric_mrepair_system_data_from_mem_bist_o;
+    input [25:0] fabric_mrepair_system_data_to_mem_bist_i;
+    output fabric_mrepair_system_dataready_o;
+    output fabric_mrepair_test_se_o;
+    input fabric_mrepair_tst_atpg_mrepair_i;
+    output fabric_mrepair_tst_gatedclock_o;
+    input [31:0] fabric_otp_apb_addr_i;
+    input fabric_otp_apb_enable_i;
+    output [31:0] fabric_otp_apb_rdata_o;
+    output fabric_otp_apb_ready_o;
+    input fabric_otp_apb_sel_i;
+    input [31:0] fabric_otp_apb_wdata_i;
+    input fabric_otp_apb_write_i;
+    input fabric_otp_cfg_clk_fab_en_i;
+    input fabric_otp_cfg_clk_otpm_disable_i;
+    input fabric_otp_cfg_fabric_apb_en_i;
+    input fabric_otp_cfg_loader_read_en_i;
+    input fabric_otp_cfg_loader_write_en_i;
+    input fabric_otp_clk_i;
+    input fabric_otp_rst_i;
+    output fabric_otp_security_ack_o;
+    output fabric_otp_security_bist_bad_o;
+    output fabric_otp_security_bist_end1_o;
+    output fabric_otp_security_bist_end2_o;
+    output [6:0] fabric_otp_security_bist_fail1_o;
+    output [5:0] fabric_otp_security_bist_fail2_o;
+    input fabric_otp_security_bistmode_i;
+    input fabric_otp_security_force_pdn1_i;
+    input fabric_otp_security_rbact1_i;
+    input fabric_otp_security_rbact2_i;
+    input fabric_otp_security_scanenable_i;
+    input [3:0] fabric_otp_security_scanin_i;
+    output [3:0] fabric_otp_security_scanout_o;
+    input fabric_otp_security_testmode_i;
+    output fabric_otp_user_ack_o;
+    input [6:0] fabric_otp_user_add_i;
+    output fabric_otp_user_bbad_o;
+    output fabric_otp_user_bend1_o;
+    output fabric_otp_user_bend2_o;
+    output [7:0] fabric_otp_user_bist1fail_o;
+    output [6:0] fabric_otp_user_bist2fail_o;
+    input fabric_otp_user_bistmode_i;
+    output fabric_otp_user_calibrated_o;
+    input fabric_otp_user_clk_i;
+    input fabric_otp_user_clock_frequency_range_i;
+    output fabric_otp_user_ded_o;
+    input [38:0] fabric_otp_user_din_i;
+    input fabric_otp_user_disturbcheck_i;
+    output fabric_otp_user_disturbed_o;
+    output [40:0] fabric_otp_user_dout_o;
+    input fabric_otp_user_eccbypass_i;
+    output [3:0] fabric_otp_user_flagstate_o;
+    output fabric_otp_user_locked_o;
+    input fabric_otp_user_pdn_i;
+    input [2:0] fabric_otp_user_prgwidth_i;
+    input fabric_otp_user_prog_i;
+    output fabric_otp_user_progfail_o;
+    output fabric_otp_user_pwok_o;
+    input fabric_otp_user_rbact1_i;
+    input fabric_otp_user_rbact2_i;
+    input fabric_otp_user_read_i;
+    input fabric_otp_user_redbypass_i;
+    output fabric_otp_user_sec_o;
+    output [15:0] fabric_otp_user_startword_o;
+    input fabric_otp_user_suppadd_i;
+    input fabric_otp_user_tm_i;
+    input fabric_otp_user_tst_scanenable_i;
+    input [4:0] fabric_otp_user_tst_scanin_i;
+    output [4:0] fabric_otp_user_tst_scanout_o;
+    output [9:0] fabric_otp_user_wlromout_o;
+    input fabric_otp_user_wordlock_i;
+    input fabric_parusr_clk_i;
+    input fabric_parusr_cs_i;
+    input [15:0] fabric_parusr_data_i;
+    output [15:0] fabric_parusr_data_o;
+    output fabric_parusr_data_val_o;
+    input fabric_parusr_enable_i;
+    input [1:0] fabric_parusr_type_i;
+    input [127:0] fabric_spare_i;
+    output [127:0] fabric_spare_o;
+    input [8:0] fabric_spi_arst_tmr_n_i;
+    output [2:0] fabric_spi_bsm_release_o;
+    output [2:0] fabric_spi_busy_o;
+    input fabric_spi_clk_i0;
+    input fabric_spi_clk_i1;
+    input fabric_spi_clk_i2;
+    input [5:0] fabric_spi_cmd_bytes_i;
+    output [2:0] fabric_spi_cmd_full_o;
+    input [5:0] fabric_spi_cmd_mode_i;
+    input [2:0] fabric_spi_cmd_push_i;
+    input [5:0] fabric_spi_cmd_type_i;
+    input [2:0] fabric_spi_cpha_i;
+    input [2:0] fabric_spi_cpol_i;
+    input [11:0] fabric_spi_cs_holdtime_i;
+    input [11:0] fabric_spi_cs_offtime_i;
+    input [11:0] fabric_spi_cs_setuptime_i;
+    input [2:0] fabric_spi_data_in_unlimited_i;
+    input [2:0] fabric_spi_enable_i;
+    output [2:0] fabric_spi_error_endianness_o;
+    output [2:0] fabric_spi_error_loopback_o;
+    output [2:0] fabric_spi_error_mode_o;
+    output [2:0] fabric_spi_error_sel_o;
+    input [8:0] fabric_spi_fifo_arst_tmr_n_i;
+    output [2:0] fabric_spi_init_done_o;
+    input [2:0] fabric_spi_legacy_enable_i;
+    input [2:0] fabric_spi_legacy_master_i;
+    input [2:0] fabric_spi_loopback_i;
+    input [2:0] fabric_spi_lsb_first_i;
+    output [2:0] fabric_spi_miso_data_inv_o;
+    output [23:0] fabric_spi_miso_data_o;
+    output [2:0] fabric_spi_miso_empty_o;
+    input [2:0] fabric_spi_miso_pop_i;
+    input [23:0] fabric_spi_mosi_data_i;
+    input [2:0] fabric_spi_mosi_data_inv_i;
+    output [2:0] fabric_spi_mosi_full_o;
+    input [2:0] fabric_spi_mosi_push_i;
+    input [2:0] fabric_spi_needed_i;
+    input [47:0] fabric_spi_powerdown_cycle_i;
+    input [47:0] fabric_spi_powerup_cycle_i;
+    input [2:0] fabric_spi_rst_n_i;
+    input fabric_spi_sck_i0;
+    input fabric_spi_sck_i1;
+    input fabric_spi_sck_i2;
+    input [2:0] fabric_spi_vcc_enable_i;
+    output [2:0] fabric_spi_vcc_used_o;
+    input [6:2] fabric_spw0_apb_slv_paddr_i;
+    input fabric_spw0_apb_slv_penable_i;
+    output [30:0] fabric_spw0_apb_slv_prdata_o;
+    output fabric_spw0_apb_slv_pready_o;
+    input fabric_spw0_apb_slv_psel_i;
+    output fabric_spw0_apb_slv_pslverr_o;
+    input [30:0] fabric_spw0_apb_slv_pwdata_i;
+    input fabric_spw0_apb_slv_pwrite_i;
+    input fabric_spw0_clk_i;
+    input fabric_spw0_clk_tx_i;
+    input fabric_spw0_rst_n_i;
+    output [8:0] fabric_spw0_rx_fifo_data_o;
+    output fabric_spw0_rx_fifo_empty_o;
+    input fabric_spw0_rx_fifo_read_i;
+    input fabric_spw0_tick_ctm_i;
+    output fabric_spw0_tick_ctm_o;
+    input [8:0] fabric_spw0_tx_fifo_data_i;
+    output fabric_spw0_tx_fifo_full_o;
+    input fabric_spw0_tx_fifo_write_i;
+    output fabric_spw0_user_shared_o;
+    input [6:2] fabric_spw1_apb_slv_paddr_i;
+    input fabric_spw1_apb_slv_penable_i;
+    output [30:0] fabric_spw1_apb_slv_prdata_o;
+    output fabric_spw1_apb_slv_pready_o;
+    input fabric_spw1_apb_slv_psel_i;
+    output fabric_spw1_apb_slv_pslverr_o;
+    input [30:0] fabric_spw1_apb_slv_pwdata_i;
+    input fabric_spw1_apb_slv_pwrite_i;
+    input fabric_spw1_clk_i;
+    input fabric_spw1_clk_tx_i;
+    input fabric_spw1_rst_n_i;
+    output [8:0] fabric_spw1_rx_fifo_data_o;
+    output fabric_spw1_rx_fifo_empty_o;
+    input fabric_spw1_rx_fifo_read_i;
+    input fabric_spw1_tick_ctm_i;
+    output fabric_spw1_tick_ctm_o;
+    input [8:0] fabric_spw1_tx_fifo_data_i;
+    output fabric_spw1_tx_fifo_full_o;
+    input fabric_spw1_tx_fifo_write_i;
+    output fabric_spw1_user_shared_o;
+    output fabric_status_cold_start_o;
+    input [2:0] fabric_thsens_arst_tmr_n_i;
+    input [7:0] fabric_thsens_clk_div_ratio_i;
+    input fabric_thsens_clk_i;
+    output [26:0] fabric_thsens_fm_config_r_o;
+    input [26:0] fabric_thsens_fm_config_w_i;
+    input fabric_thsens_fm_config_wen_i;
+    output [13:0] fabric_thsens_fm_data_o;
+    input fabric_thsens_fm_enable_i;
+    output [31:0] fabric_thsens_fm_mode_r_o;
+    input [31:0] fabric_thsens_fm_mode_w_i;
+    input fabric_thsens_fm_mode_wen_i;
+    output fabric_thsens_fm_overflow_o;
+    output fabric_thsens_fm_valid_o;
+    output [26:0] fabric_thsens_otp_config_o;
+    input fabric_thsens_tst_scanenable_i;
+    input fabric_thsens_tst_scanin1_i;
+    input fabric_thsens_tst_scanin2_i;
+    output fabric_thsens_tst_scanout1_o;
+    output fabric_thsens_tst_scanout2_o;
+    input fabric_user_clk_i;
+    input [31:0] fabric_user_data_i;
+    output [31:0] fabric_user_data_o;
+    output fabric_user_read_cycle_o;
+    output fabric_user_write_cycle_o;
+    parameter bsm_config = 0;
+endmodule
+
+(* blackbox *)
+module NX_SERVICE_IF_U_WRAP(fabric_otp_user_clk_i, fabric_otp_user_bistmode_i, fabric_otp_user_disturbcheck_i, fabric_otp_user_eccbypass_i, fabric_otp_user_pdn_i, fabric_otp_user_prog_i, fabric_otp_user_rbact1_i, fabric_otp_user_rbact2_i, fabric_otp_user_read_i, fabric_otp_user_redbypass_i, fabric_otp_user_suppadd_i, fabric_otp_user_tm_i, fabric_otp_user_tst_scanenable_i, fabric_otp_user_wordlock_i, fabric_otp_user_clock_frequency_range_i, fabric_otp_user_ack_o, fabric_otp_user_bbad_o, fabric_otp_user_bend1_o, fabric_otp_user_bend2_o, fabric_otp_user_calibrated_o, fabric_otp_user_ded_o
+, fabric_otp_user_disturbed_o, fabric_otp_user_locked_o, fabric_otp_user_progfail_o, fabric_otp_user_pwok_o, fabric_otp_user_sec_o, fabric_clk_bsm_o, fabric_clk_otp_mux_i, fabric_clk_otp_o, fabric_clk_user0_o, fabric_clk_user1_o, fabric_user_clk_i, fabric_user_write_cycle_o, fabric_user_read_cycle_o, fabric_cfg_fabric_user_flag_o, fabric_cfg_fabric_user_enable_o, fabric_parusr_clk_i, fabric_parusr_enable_i, fabric_parusr_cs_i, fabric_parusr_data_val_o, fabric_jtag_tck_o, fabric_jtag_trst_n_o
+, fabric_jtag_tms_o, fabric_jtag_tdi_o, fabric_jtag_usr1_o, fabric_jtag_usr2_o, fabric_jtag_tdo_usr1_i, fabric_jtag_tdo_usr2_i, fabric_status_cold_start_o, fabric_flag_trigger0_o, fabric_flag_trigger1_o, fabric_thsens_clk_i, fabric_thsens_fm_enable_i, fabric_thsens_fm_mode_wen_i, fabric_thsens_fm_config_wen_i, fabric_thsens_fm_valid_o, fabric_thsens_fm_overflow_o, fabric_spi_clk_i2, fabric_spi_sck_i2, fabric_spi_clk_i0, fabric_spi_sck_i0, fabric_spi_clk_i1, fabric_spi_sck_i1
+, fabric_spw0_clk_i, fabric_spw0_clk_tx_i, fabric_spw0_rst_n_i, fabric_spw0_user_shared_o, fabric_spw0_tx_fifo_write_i, fabric_spw0_tx_fifo_full_o, fabric_spw0_rx_fifo_read_i, fabric_spw0_rx_fifo_empty_o, fabric_spw0_tick_ctm_i, fabric_spw0_tick_ctm_o, fabric_spw0_apb_slv_psel_i, fabric_spw0_apb_slv_penable_i, fabric_spw0_apb_slv_pwrite_i, fabric_spw0_apb_slv_pready_o, fabric_spw0_apb_slv_pslverr_o, fabric_spw1_clk_i, fabric_spw1_clk_tx_i, fabric_spw1_rst_n_i, fabric_spw1_user_shared_o, fabric_spw1_tx_fifo_write_i, fabric_spw1_tx_fifo_full_o
+, fabric_spw1_rx_fifo_read_i, fabric_spw1_rx_fifo_empty_o, fabric_spw1_tick_ctm_i, fabric_spw1_tick_ctm_o, fabric_spw1_apb_slv_psel_i, fabric_spw1_apb_slv_penable_i, fabric_spw1_apb_slv_pwrite_i, fabric_spw1_apb_slv_pready_o, fabric_spw1_apb_slv_pslverr_o, fabric_otp_user_add_i, fabric_otp_user_din_i, fabric_otp_user_prgwidth_i, fabric_otp_user_tst_scanin_i, fabric_otp_user_bist1fail_o, fabric_otp_user_bist2fail_o, fabric_otp_user_dout_o, fabric_otp_user_flagstate_o, fabric_otp_user_startword_o, fabric_otp_user_tst_scanout_o, fabric_otp_user_wlromout_o, fabric_io_in_i
+, fabric_io_oe_i, fabric_io_out_o, fabric_user_data_i, fabric_user_data_o, fabric_parusr_type_i, fabric_parusr_data_i, fabric_parusr_data_o, fabric_flag_ready_TMR_o, fabric_enable_TMR_i, fabric_lowskew_i, fabric_lowskew_o, fabric_spare_i, fabric_spare_o, fabric_thsens_arst_tmr_n_i, fabric_thsens_fm_mode_w_i, fabric_thsens_fm_config_w_i, fabric_thsens_fm_data_o, fabric_thsens_fm_mode_r_o, fabric_thsens_fm_config_r_o, fabric_thsens_clk_div_ratio_i, fabric_thsens_otp_config_o
+, fabric_spi_needed_i, fabric_spi_bsm_release_o, fabric_spi_arst_tmr_n_i, fabric_spi_fifo_arst_tmr_n_i, fabric_spi_cpol_i, fabric_spi_cpha_i, fabric_spi_loopback_i, fabric_spi_lsb_first_i, fabric_spi_cs_setuptime_i, fabric_spi_cs_holdtime_i, fabric_spi_cs_offtime_i, fabric_spi_vcc_enable_i, fabric_spi_powerdown_cycle_i, fabric_spi_powerup_cycle_i, fabric_spi_legacy_enable_i, fabric_spi_legacy_master_i, fabric_spi_data_in_unlimited_i, fabric_spi_enable_i, fabric_spi_rst_n_i, fabric_spi_init_done_o, fabric_spi_busy_o
+, fabric_spi_vcc_used_o, fabric_spi_error_sel_o, fabric_spi_error_loopback_o, fabric_spi_error_mode_o, fabric_spi_error_endianness_o, fabric_spi_cmd_push_i, fabric_spi_cmd_full_o, fabric_spi_cmd_type_i, fabric_spi_cmd_mode_i, fabric_spi_cmd_bytes_i, fabric_spi_mosi_push_i, fabric_spi_mosi_full_o, fabric_spi_mosi_data_i, fabric_spi_mosi_data_inv_i, fabric_spi_miso_pop_i, fabric_spi_miso_empty_o, fabric_spi_miso_data_o, fabric_spi_miso_data_inv_o, fabric_spw0_tx_fifo_data_i, fabric_spw0_rx_fifo_data_o, fabric_spw0_apb_slv_paddr_i
+, fabric_spw0_apb_slv_pwdata_i, fabric_spw0_apb_slv_prdata_o, fabric_spw1_tx_fifo_data_i, fabric_spw1_rx_fifo_data_o, fabric_spw1_apb_slv_paddr_i, fabric_spw1_apb_slv_pwdata_i, fabric_spw1_apb_slv_prdata_o);
+    output fabric_cfg_fabric_user_enable_o;
+    output fabric_cfg_fabric_user_flag_o;
+    output fabric_clk_bsm_o;
+    input fabric_clk_otp_mux_i;
+    output fabric_clk_otp_o;
+    output fabric_clk_user0_o;
+    output fabric_clk_user1_o;
+    input [2:0] fabric_enable_TMR_i;
+    output [2:0] fabric_flag_ready_TMR_o;
+    output fabric_flag_trigger0_o;
+    output fabric_flag_trigger1_o;
+    input [34:0] fabric_io_in_i;
+    input [34:0] fabric_io_oe_i;
+    output [34:0] fabric_io_out_o;
+    output fabric_jtag_tck_o;
+    output fabric_jtag_tdi_o;
+    input fabric_jtag_tdo_usr1_i;
+    input fabric_jtag_tdo_usr2_i;
+    output fabric_jtag_tms_o;
+    output fabric_jtag_trst_n_o;
+    output fabric_jtag_usr1_o;
+    output fabric_jtag_usr2_o;
+    input [39:0] fabric_lowskew_i;
+    output [5:0] fabric_lowskew_o;
+    output fabric_otp_user_ack_o;
+    input [6:0] fabric_otp_user_add_i;
+    output fabric_otp_user_bbad_o;
+    output fabric_otp_user_bend1_o;
+    output fabric_otp_user_bend2_o;
+    output [7:0] fabric_otp_user_bist1fail_o;
+    output [6:0] fabric_otp_user_bist2fail_o;
+    input fabric_otp_user_bistmode_i;
+    output fabric_otp_user_calibrated_o;
+    input fabric_otp_user_clk_i;
+    input fabric_otp_user_clock_frequency_range_i;
+    output fabric_otp_user_ded_o;
+    input [38:0] fabric_otp_user_din_i;
+    input fabric_otp_user_disturbcheck_i;
+    output fabric_otp_user_disturbed_o;
+    output [40:0] fabric_otp_user_dout_o;
+    input fabric_otp_user_eccbypass_i;
+    output [3:0] fabric_otp_user_flagstate_o;
+    output fabric_otp_user_locked_o;
+    input fabric_otp_user_pdn_i;
+    input [2:0] fabric_otp_user_prgwidth_i;
+    input fabric_otp_user_prog_i;
+    output fabric_otp_user_progfail_o;
+    output fabric_otp_user_pwok_o;
+    input fabric_otp_user_rbact1_i;
+    input fabric_otp_user_rbact2_i;
+    input fabric_otp_user_read_i;
+    input fabric_otp_user_redbypass_i;
+    output fabric_otp_user_sec_o;
+    output [15:0] fabric_otp_user_startword_o;
+    input fabric_otp_user_suppadd_i;
+    input fabric_otp_user_tm_i;
+    input fabric_otp_user_tst_scanenable_i;
+    input [4:0] fabric_otp_user_tst_scanin_i;
+    output [4:0] fabric_otp_user_tst_scanout_o;
+    output [9:0] fabric_otp_user_wlromout_o;
+    input fabric_otp_user_wordlock_i;
+    input fabric_parusr_clk_i;
+    input fabric_parusr_cs_i;
+    input [15:0] fabric_parusr_data_i;
+    output [15:0] fabric_parusr_data_o;
+    output fabric_parusr_data_val_o;
+    input fabric_parusr_enable_i;
+    input [1:0] fabric_parusr_type_i;
+    input [127:0] fabric_spare_i;
+    output [127:0] fabric_spare_o;
+    input [8:0] fabric_spi_arst_tmr_n_i;
+    output [2:0] fabric_spi_bsm_release_o;
+    output [2:0] fabric_spi_busy_o;
+    input fabric_spi_clk_i0;
+    input fabric_spi_clk_i1;
+    input fabric_spi_clk_i2;
+    input [5:0] fabric_spi_cmd_bytes_i;
+    output [2:0] fabric_spi_cmd_full_o;
+    input [5:0] fabric_spi_cmd_mode_i;
+    input [2:0] fabric_spi_cmd_push_i;
+    input [5:0] fabric_spi_cmd_type_i;
+    input [2:0] fabric_spi_cpha_i;
+    input [2:0] fabric_spi_cpol_i;
+    input [11:0] fabric_spi_cs_holdtime_i;
+    input [11:0] fabric_spi_cs_offtime_i;
+    input [11:0] fabric_spi_cs_setuptime_i;
+    input [2:0] fabric_spi_data_in_unlimited_i;
+    input [2:0] fabric_spi_enable_i;
+    output [2:0] fabric_spi_error_endianness_o;
+    output [2:0] fabric_spi_error_loopback_o;
+    output [2:0] fabric_spi_error_mode_o;
+    output [2:0] fabric_spi_error_sel_o;
+    input [8:0] fabric_spi_fifo_arst_tmr_n_i;
+    output [2:0] fabric_spi_init_done_o;
+    input [2:0] fabric_spi_legacy_enable_i;
+    input [2:0] fabric_spi_legacy_master_i;
+    input [2:0] fabric_spi_loopback_i;
+    input [2:0] fabric_spi_lsb_first_i;
+    output [2:0] fabric_spi_miso_data_inv_o;
+    output [23:0] fabric_spi_miso_data_o;
+    output [2:0] fabric_spi_miso_empty_o;
+    input [2:0] fabric_spi_miso_pop_i;
+    input [23:0] fabric_spi_mosi_data_i;
+    input [2:0] fabric_spi_mosi_data_inv_i;
+    output [2:0] fabric_spi_mosi_full_o;
+    input [2:0] fabric_spi_mosi_push_i;
+    input [2:0] fabric_spi_needed_i;
+    input [47:0] fabric_spi_powerdown_cycle_i;
+    input [47:0] fabric_spi_powerup_cycle_i;
+    input [2:0] fabric_spi_rst_n_i;
+    input fabric_spi_sck_i0;
+    input fabric_spi_sck_i1;
+    input fabric_spi_sck_i2;
+    input [2:0] fabric_spi_vcc_enable_i;
+    output [2:0] fabric_spi_vcc_used_o;
+    input [6:2] fabric_spw0_apb_slv_paddr_i;
+    input fabric_spw0_apb_slv_penable_i;
+    output [30:0] fabric_spw0_apb_slv_prdata_o;
+    output fabric_spw0_apb_slv_pready_o;
+    input fabric_spw0_apb_slv_psel_i;
+    output fabric_spw0_apb_slv_pslverr_o;
+    input [30:0] fabric_spw0_apb_slv_pwdata_i;
+    input fabric_spw0_apb_slv_pwrite_i;
+    input fabric_spw0_clk_i;
+    input fabric_spw0_clk_tx_i;
+    input fabric_spw0_rst_n_i;
+    output [8:0] fabric_spw0_rx_fifo_data_o;
+    output fabric_spw0_rx_fifo_empty_o;
+    input fabric_spw0_rx_fifo_read_i;
+    input fabric_spw0_tick_ctm_i;
+    output fabric_spw0_tick_ctm_o;
+    input [8:0] fabric_spw0_tx_fifo_data_i;
+    output fabric_spw0_tx_fifo_full_o;
+    input fabric_spw0_tx_fifo_write_i;
+    output fabric_spw0_user_shared_o;
+    input [6:2] fabric_spw1_apb_slv_paddr_i;
+    input fabric_spw1_apb_slv_penable_i;
+    output [30:0] fabric_spw1_apb_slv_prdata_o;
+    output fabric_spw1_apb_slv_pready_o;
+    input fabric_spw1_apb_slv_psel_i;
+    output fabric_spw1_apb_slv_pslverr_o;
+    input [30:0] fabric_spw1_apb_slv_pwdata_i;
+    input fabric_spw1_apb_slv_pwrite_i;
+    input fabric_spw1_clk_i;
+    input fabric_spw1_clk_tx_i;
+    input fabric_spw1_rst_n_i;
+    output [8:0] fabric_spw1_rx_fifo_data_o;
+    output fabric_spw1_rx_fifo_empty_o;
+    input fabric_spw1_rx_fifo_read_i;
+    input fabric_spw1_tick_ctm_i;
+    output fabric_spw1_tick_ctm_o;
+    input [8:0] fabric_spw1_tx_fifo_data_i;
+    output fabric_spw1_tx_fifo_full_o;
+    input fabric_spw1_tx_fifo_write_i;
+    output fabric_spw1_user_shared_o;
+    output fabric_status_cold_start_o;
+    input [2:0] fabric_thsens_arst_tmr_n_i;
+    input [7:0] fabric_thsens_clk_div_ratio_i;
+    input fabric_thsens_clk_i;
+    output [26:0] fabric_thsens_fm_config_r_o;
+    input [26:0] fabric_thsens_fm_config_w_i;
+    input fabric_thsens_fm_config_wen_i;
+    output [13:0] fabric_thsens_fm_data_o;
+    input fabric_thsens_fm_enable_i;
+    output [31:0] fabric_thsens_fm_mode_r_o;
+    input [31:0] fabric_thsens_fm_mode_w_i;
+    input fabric_thsens_fm_mode_wen_i;
+    output fabric_thsens_fm_overflow_o;
+    output fabric_thsens_fm_valid_o;
+    output [26:0] fabric_thsens_otp_config_o;
+    input fabric_user_clk_i;
+    input [31:0] fabric_user_data_i;
+    output [31:0] fabric_user_data_o;
+    output fabric_user_read_cycle_o;
+    output fabric_user_write_cycle_o;
+    parameter bsm_config = 0;
+endmodule
+
+(* blackbox *)
+module NX_SERVICE_U(fabric_otp_user_tst_scanenable_i, fabric_otp_cfg_loader_read_en_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_scanenable_i, fabric_otp_user_din_i1, fabric_otp_user_din_i2, fabric_otp_user_din_i3, fabric_otp_user_din_i4, fabric_otp_user_din_i5, fabric_otp_user_din_i6, fabric_otp_user_din_i7, fabric_otp_user_din_i8, fabric_otp_user_din_i9, fabric_otp_user_din_i10, fabric_otp_user_din_i11, fabric_otp_user_din_i12, fabric_otp_user_din_i13, fabric_otp_user_din_i14, fabric_otp_user_din_i15, fabric_otp_user_din_i16, fabric_otp_user_din_i17
+, fabric_otp_user_din_i18, fabric_otp_user_din_i19, fabric_otp_user_din_i20, fabric_otp_user_din_i21, fabric_otp_user_din_i22, fabric_otp_user_din_i23, fabric_otp_user_din_i24, fabric_otp_user_din_i25, fabric_otp_user_din_i26, fabric_otp_user_din_i27, fabric_otp_user_din_i28, fabric_otp_user_din_i29, fabric_otp_user_din_i30, fabric_otp_user_din_i31, fabric_otp_user_din_i32, fabric_otp_user_din_i33, fabric_otp_user_din_i34, fabric_otp_user_din_i35, fabric_otp_user_din_i36, fabric_otp_user_din_i37, fabric_otp_user_din_i38
+, fabric_otp_user_din_i39, fabric_mrepair_fuse_prgwidth_i1, fabric_mrepair_fuse_prgwidth_i2, fabric_mrepair_fuse_prgwidth_i3, fabric_otp_apb_wdata_i1, fabric_otp_apb_wdata_i2, fabric_otp_apb_wdata_i3, fabric_otp_apb_wdata_i4, fabric_otp_apb_wdata_i5, fabric_otp_apb_wdata_i6, fabric_otp_apb_wdata_i7, fabric_otp_apb_wdata_i8, fabric_otp_apb_wdata_i9, fabric_otp_apb_wdata_i10, fabric_otp_apb_wdata_i11, fabric_otp_apb_wdata_i12, fabric_otp_apb_wdata_i13, fabric_otp_apb_wdata_i14, fabric_otp_apb_wdata_i15, fabric_otp_apb_wdata_i16, fabric_otp_apb_wdata_i17
+, fabric_otp_apb_wdata_i18, fabric_otp_apb_wdata_i19, fabric_otp_apb_wdata_i20, fabric_otp_apb_wdata_i21, fabric_otp_apb_wdata_i22, fabric_otp_apb_wdata_i23, fabric_otp_apb_wdata_i24, fabric_otp_apb_wdata_i25, fabric_otp_apb_wdata_i26, fabric_otp_apb_wdata_i27, fabric_otp_apb_wdata_i28, fabric_otp_apb_wdata_i29, fabric_otp_apb_wdata_i30, fabric_otp_apb_wdata_i31, fabric_otp_apb_wdata_i32, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_user_disturbcheck_i, fabric_mrepair_fuse_read_i, fabric_otp_user_rbact2_i, fabric_mrepair_fuse_eccbypass_i, fabric_otp_user_bistmode_i
+, fabric_otp_user_add_i1, fabric_otp_user_add_i2, fabric_otp_user_add_i3, fabric_otp_user_add_i4, fabric_otp_user_add_i5, fabric_otp_user_add_i6, fabric_otp_user_add_i7, fabric_otp_user_tm_i, fabric_otp_rst_i, fabric_mrepair_fuse_disturbchecked_i, fabric_otp_user_rbact1_i, fabric_mrepair_fuse_tst_scanin_i1, fabric_mrepair_fuse_tst_scanin_i2, fabric_mrepair_fuse_tst_scanin_i3, fabric_mrepair_fuse_tst_scanin_i4, fabric_mrepair_fuse_tst_scanin_i5, fabric_parusr_type_i1, fabric_parusr_type_i2, fabric_mrepair_fuse_redbypass_i, fabric_otp_user_eccbypass_i, fabric_otp_user_redbypass_i
+, fabric_mrepair_mode_i1, fabric_mrepair_mode_i2, fabric_mrepair_mode_i3, fabric_mrepair_mode_i4, fabric_parusr_cs_i, fabric_sif_reg_en_i1, fabric_sif_reg_en_i2, fabric_sif_reg_en_i3, fabric_sif_reg_en_i4, fabric_sif_reg_en_i5, fabric_sif_reg_en_i6, fabric_sif_reg_en_i7, fabric_sif_reg_en_i8, fabric_sif_reg_en_i9, fabric_sif_reg_en_i10, fabric_sif_reg_en_i11, fabric_sif_reg_en_i12, fabric_sif_reg_en_i13, fabric_sif_reg_en_i14, fabric_sif_reg_en_i15, fabric_sif_reg_en_i16
+, fabric_sif_reg_en_i17, fabric_sif_reg_en_i18, fabric_sif_reg_en_i19, fabric_sif_reg_en_i20, fabric_sif_reg_en_i21, fabric_sif_reg_en_i22, fabric_sif_reg_en_i23, fabric_sif_reg_en_i24, fabric_sif_reg_en_i25, fabric_sif_reg_en_i26, fabric_sif_reg_en_i27, fabric_sif_reg_en_i28, fabric_sif_reg_en_i29, fabric_sif_reg_en_i30, fabric_sif_reg_en_i31, fabric_sif_reg_en_i32, fabric_sif_reg_en_i33, fabric_sif_reg_en_i34, fabric_sif_reg_en_i35, fabric_sif_reg_en_i36, fabric_sif_reg_en_i37
+, fabric_sif_reg_en_i38, fabric_sif_reg_en_i39, fabric_sif_reg_en_i40, fabric_sif_reg_en_i41, fabric_sif_reg_en_i42, fabric_sif_reg_en_i43, fabric_sif_reg_en_i44, fabric_sif_reg_en_i45, fabric_sif_reg_en_i46, fabric_sif_reg_en_i47, fabric_sif_reg_en_i48, fabric_sif_reg_en_i49, fabric_sif_reg_en_i50, fabric_sif_reg_en_i51, fabric_sif_reg_en_i52, fabric_sif_reg_en_i53, fabric_sif_reg_en_i54, fabric_sif_reg_en_i55, fabric_sif_reg_en_i56, fabric_sif_reg_en_i57, fabric_sif_reg_en_i58
+, fabric_sif_reg_en_i59, fabric_sif_reg_en_i60, fabric_sif_reg_en_i61, fabric_sif_reg_en_i62, fabric_sif_reg_en_i63, fabric_sif_reg_en_i64, fabric_sif_reg_en_i65, fabric_sif_reg_en_i66, fabric_sif_reg_en_i67, fabric_sif_reg_en_i68, fabric_sif_reg_en_i69, fabric_sif_reg_en_i70, fabric_sif_reg_en_i71, fabric_sif_reg_en_i72, fabric_sif_reg_en_i73, fabric_sif_reg_en_i74, fabric_sif_reg_en_i75, fabric_sif_reg_en_i76, fabric_sif_reg_en_i77, fabric_sif_reg_en_i78, fabric_sif_reg_en_i79
+, fabric_sif_reg_en_i80, fabric_sif_reg_en_i81, fabric_sif_reg_en_i82, fabric_sif_reg_en_i83, fabric_sif_reg_en_i84, fabric_sif_reg_en_i85, fabric_sif_reg_en_i86, fabric_sif_reg_en_i87, fabric_sif_reg_en_i88, fabric_sif_reg_en_i89, fabric_sif_reg_en_i90, fabric_sif_reg_en_i91, fabric_sif_reg_en_i92, fabric_sif_reg_en_i93, fabric_sif_reg_en_i94, fabric_sif_reg_en_i95, fabric_sif_reg_en_i96, fabric_sif_reg_en_i97, fabric_sif_reg_en_i98, fabric_sif_reg_en_i99, fabric_sif_reg_en_i100
+, fabric_sif_reg_en_i101, fabric_sif_reg_en_i102, fabric_sif_reg_en_i103, fabric_sif_reg_en_i104, fabric_sif_reg_en_i105, fabric_sif_reg_en_i106, fabric_sif_reg_en_i107, fabric_sif_reg_en_i108, fabric_sif_reg_en_i109, fabric_sif_reg_en_i110, fabric_sif_reg_en_i111, fabric_sif_reg_en_i112, fabric_sif_reg_en_i113, fabric_sif_reg_en_i114, fabric_sif_reg_en_i115, fabric_sif_reg_en_i116, fabric_sif_reg_en_i117, fabric_sif_reg_en_i118, fabric_sif_reg_en_i119, fabric_sif_reg_en_i120, fabric_mrepair_fuse_rbact2_i
+, fabric_data_from_system_i, fabric_data_from_bist_i1, fabric_data_from_bist_i2, fabric_data_from_bist_i3, fabric_data_from_bist_i4, fabric_data_from_bist_i5, fabric_data_from_bist_i6, fabric_data_from_bist_i7, fabric_data_from_bist_i8, fabric_data_from_bist_i9, fabric_data_from_bist_i10, fabric_data_from_bist_i11, fabric_data_from_bist_i12, fabric_data_from_bist_i13, fabric_data_from_bist_i14, fabric_data_from_bist_i15, fabric_data_from_bist_i16, fabric_data_from_bist_i17, fabric_data_from_bist_i18, fabric_data_from_bist_i19, fabric_data_from_bist_i20
+, fabric_data_from_bist_i21, fabric_data_from_bist_i22, fabric_data_from_bist_i23, fabric_data_from_bist_i24, fabric_otp_apb_enable_i, fabric_mrepair_fuse_tm_i, fabric_otp_security_rbact2_i, fabric_otp_security_rbact1_i, fabric_shift_en_i1, fabric_shift_en_i2, fabric_shift_en_i3, fabric_shift_en_i4, fabric_shift_en_i5, fabric_shift_en_i6, fabric_shift_en_i7, fabric_shift_en_i8, fabric_shift_en_i9, fabric_shift_en_i10, fabric_shift_en_i11, fabric_shift_en_i12, fabric_shift_en_i13
+, fabric_shift_en_i14, fabric_shift_en_i15, fabric_shift_en_i16, fabric_shift_en_i17, fabric_shift_en_i18, fabric_shift_en_i19, fabric_shift_en_i20, fabric_shift_en_i21, fabric_shift_en_i22, fabric_shift_en_i23, fabric_shift_en_i24, fabric_otp_cfg_loader_write_en_i, fabric_user_data_i1, fabric_user_data_i2, fabric_user_data_i3, fabric_user_data_i4, fabric_user_data_i5, fabric_user_data_i6, fabric_user_data_i7, fabric_user_data_i8, fabric_user_data_i9
+, fabric_user_data_i10, fabric_user_data_i11, fabric_user_data_i12, fabric_user_data_i13, fabric_user_data_i14, fabric_user_data_i15, fabric_user_data_i16, fabric_user_data_i17, fabric_user_data_i18, fabric_user_data_i19, fabric_user_data_i20, fabric_user_data_i21, fabric_user_data_i22, fabric_user_data_i23, fabric_user_data_i24, fabric_user_data_i25, fabric_user_data_i26, fabric_user_data_i27, fabric_user_data_i28, fabric_user_data_i29, fabric_user_data_i30
+, fabric_user_data_i31, fabric_user_data_i32, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_prog_i, fabric_otp_user_wordlock_i, fabric_ahb_direct_data_i1, fabric_ahb_direct_data_i2, fabric_ahb_direct_data_i3, fabric_ahb_direct_data_i4, fabric_ahb_direct_data_i5, fabric_ahb_direct_data_i6, fabric_ahb_direct_data_i7, fabric_ahb_direct_data_i8, fabric_ahb_direct_data_i9, fabric_ahb_direct_data_i10, fabric_ahb_direct_data_i11, fabric_ahb_direct_data_i12, fabric_ahb_direct_data_i13, fabric_ahb_direct_data_i14, fabric_ahb_direct_data_i15, fabric_ahb_direct_data_i16
+, fabric_ahb_direct_data_i17, fabric_ahb_direct_data_i18, fabric_ahb_direct_data_i19, fabric_ahb_direct_data_i20, fabric_ahb_direct_data_i21, fabric_ahb_direct_data_i22, fabric_ahb_direct_data_i23, fabric_ahb_direct_data_i24, fabric_ahb_direct_data_i25, fabric_ahb_direct_data_i26, fabric_ahb_direct_data_i27, fabric_ahb_direct_data_i28, fabric_ahb_direct_data_i29, fabric_ahb_direct_data_i30, fabric_ahb_direct_data_i31, fabric_ahb_direct_data_i32, fabric_otp_user_prog_i, fabric_pd_active_i1, fabric_pd_active_i2, fabric_pd_active_i3, fabric_pd_active_i4
+, fabric_pd_active_i5, fabric_pd_active_i6, fabric_pd_active_i7, fabric_pd_active_i8, fabric_pd_active_i9, fabric_pd_active_i10, fabric_pd_active_i11, fabric_pd_active_i12, fabric_pd_active_i13, fabric_pd_active_i14, fabric_pd_active_i15, fabric_pd_active_i16, fabric_pd_active_i17, fabric_pd_active_i18, fabric_pd_active_i19, fabric_pd_active_i20, fabric_pd_active_i21, fabric_pd_active_i22, fabric_pd_active_i23, fabric_pd_active_i24, fabric_otp_user_suppadd_i
+, fabric_mrepair_fuse_pdn_i, fabric_otp_security_scanin_i1, fabric_otp_security_scanin_i2, fabric_otp_security_scanin_i3, fabric_otp_security_scanin_i4, fabric_otp_security_scanin_i5, fabric_end_encoding_i, fabric_jtag_tdo_usr2_i, fabric_mrepair_fuse_wordlock_i, fabric_otp_user_prgwidth_i1, fabric_otp_user_prgwidth_i2, fabric_otp_user_prgwidth_i3, fabric_otp_user_read_i, fabric_mrepair_fuse_add_i1, fabric_mrepair_fuse_add_i2, fabric_mrepair_fuse_add_i3, fabric_mrepair_fuse_add_i4, fabric_mrepair_fuse_add_i5, fabric_mrepair_fuse_add_i6, fabric_mrepair_fuse_add_i7, fabric_mrepair_fuse_bistmode_i
+, fabric_jtag_tdo_usr1_i, fabric_otp_cfg_clk_fab_en_i, fabric_io_in_i1, fabric_io_in_i2, fabric_io_in_i3, fabric_io_in_i4, fabric_io_in_i5, fabric_io_in_i6, fabric_io_in_i7, fabric_io_in_i8, fabric_io_in_i9, fabric_io_in_i10, fabric_io_in_i11, fabric_io_in_i12, fabric_io_in_i13, fabric_io_in_i14, fabric_io_in_i15, fabric_io_in_i16, fabric_io_in_i17, fabric_io_in_i18, fabric_io_in_i19
+, fabric_io_in_i20, fabric_io_in_i21, fabric_io_in_i22, fabric_io_in_i23, fabric_io_in_i24, fabric_io_in_i25, fabric_sif_load_en_i1, fabric_sif_load_en_i2, fabric_sif_load_en_i3, fabric_sif_load_en_i4, fabric_sif_load_en_i5, fabric_sif_load_en_i6, fabric_sif_load_en_i7, fabric_sif_load_en_i8, fabric_sif_load_en_i9, fabric_sif_load_en_i10, fabric_sif_load_en_i11, fabric_sif_load_en_i12, fabric_sif_load_en_i13, fabric_sif_load_en_i14, fabric_sif_load_en_i15
+, fabric_sif_load_en_i16, fabric_sif_load_en_i17, fabric_sif_load_en_i18, fabric_sif_load_en_i19, fabric_sif_load_en_i20, fabric_sif_load_en_i21, fabric_sif_load_en_i22, fabric_sif_load_en_i23, fabric_sif_load_en_i24, fabric_mrepair_fuse_din_i1, fabric_mrepair_fuse_din_i2, fabric_mrepair_fuse_din_i3, fabric_mrepair_fuse_din_i4, fabric_mrepair_fuse_din_i5, fabric_mrepair_fuse_din_i6, fabric_mrepair_fuse_din_i7, fabric_mrepair_fuse_din_i8, fabric_mrepair_fuse_din_i9, fabric_mrepair_fuse_din_i10, fabric_mrepair_fuse_din_i11, fabric_mrepair_fuse_din_i12
+, fabric_mrepair_fuse_din_i13, fabric_mrepair_fuse_din_i14, fabric_mrepair_fuse_din_i15, fabric_mrepair_fuse_din_i16, fabric_mrepair_fuse_din_i17, fabric_mrepair_fuse_din_i18, fabric_mrepair_fuse_din_i19, fabric_mrepair_fuse_din_i20, fabric_mrepair_fuse_din_i21, fabric_mrepair_fuse_din_i22, fabric_mrepair_fuse_din_i23, fabric_mrepair_fuse_din_i24, fabric_mrepair_fuse_din_i25, fabric_mrepair_fuse_din_i26, fabric_mrepair_fuse_din_i27, fabric_mrepair_fuse_din_i28, fabric_mrepair_fuse_din_i29, fabric_mrepair_fuse_din_i30, fabric_mrepair_fuse_din_i31, fabric_mrepair_fuse_din_i32, fabric_mrepair_fuse_din_i33
+, fabric_mrepair_fuse_din_i34, fabric_mrepair_fuse_din_i35, fabric_mrepair_fuse_din_i36, fabric_mrepair_fuse_din_i37, fabric_mrepair_fuse_din_i38, fabric_mrepair_fuse_din_i39, fabric_otp_apb_addr_i1, fabric_otp_apb_addr_i2, fabric_otp_apb_addr_i3, fabric_otp_apb_addr_i4, fabric_otp_apb_addr_i5, fabric_otp_apb_addr_i6, fabric_otp_apb_addr_i7, fabric_otp_apb_addr_i8, fabric_otp_apb_addr_i9, fabric_otp_apb_addr_i10, fabric_otp_apb_addr_i11, fabric_otp_apb_addr_i12, fabric_otp_apb_addr_i13, fabric_otp_apb_addr_i14, fabric_otp_apb_addr_i15
+, fabric_otp_apb_addr_i16, fabric_otp_apb_addr_i17, fabric_otp_apb_addr_i18, fabric_otp_apb_addr_i19, fabric_otp_apb_addr_i20, fabric_otp_apb_addr_i21, fabric_otp_apb_addr_i22, fabric_otp_apb_addr_i23, fabric_otp_apb_addr_i24, fabric_otp_apb_addr_i25, fabric_otp_apb_addr_i26, fabric_otp_apb_addr_i27, fabric_otp_apb_addr_i28, fabric_otp_apb_addr_i29, fabric_otp_apb_addr_i30, fabric_otp_apb_addr_i31, fabric_otp_apb_addr_i32, fabric_otp_apb_sel_i, fabric_mrepair_fuse_rbact1_i, fabric_otp_cfg_fabric_apb_en_i, fabric_data_shift_en_i
+, fabric_lowskew_i21, fabric_direct_data_i1, fabric_direct_data_i2, fabric_direct_data_i3, fabric_direct_data_i4, fabric_direct_data_i5, fabric_direct_data_i6, fabric_direct_data_i7, fabric_direct_data_i8, fabric_direct_data_i9, fabric_direct_data_i10, fabric_direct_data_i11, fabric_direct_data_i12, fabric_direct_data_i13, fabric_direct_data_i14, fabric_direct_data_i15, fabric_direct_data_i16, fabric_direct_data_i17, fabric_direct_data_i18, fabric_direct_data_i19, fabric_direct_data_i20
+, fabric_direct_data_i21, fabric_direct_data_i22, fabric_direct_data_i23, fabric_direct_data_i24, fabric_direct_data_i25, fabric_direct_data_i26, fabric_direct_data_i27, fabric_direct_data_i28, fabric_direct_data_i29, fabric_direct_data_i30, fabric_direct_data_i31, fabric_direct_data_i32, fabric_otp_user_pdn_i, fabric_io_oe_i1, fabric_io_oe_i2, fabric_io_oe_i3, fabric_io_oe_i4, fabric_io_oe_i5, fabric_io_oe_i6, fabric_io_oe_i7, fabric_io_oe_i8
+, fabric_io_oe_i9, fabric_io_oe_i10, fabric_io_oe_i11, fabric_io_oe_i12, fabric_io_oe_i13, fabric_io_oe_i14, fabric_io_oe_i15, fabric_io_oe_i16, fabric_io_oe_i17, fabric_io_oe_i18, fabric_io_oe_i19, fabric_io_oe_i20, fabric_io_oe_i21, fabric_io_oe_i22, fabric_io_oe_i23, fabric_io_oe_i24, fabric_io_oe_i25, fabric_parusr_data_i1, fabric_parusr_data_i2, fabric_parusr_data_i3, fabric_parusr_data_i4
+, fabric_parusr_data_i5, fabric_parusr_data_i6, fabric_parusr_data_i7, fabric_parusr_data_i8, fabric_parusr_data_i9, fabric_parusr_data_i10, fabric_parusr_data_i11, fabric_parusr_data_i12, fabric_parusr_data_i13, fabric_parusr_data_i14, fabric_parusr_data_i15, fabric_parusr_data_i16, fabric_otp_apb_write_i, fabric_otp_security_testmode_i, fabric_system_data_to_mem_bist_i1, fabric_system_data_to_mem_bist_i2, fabric_system_data_to_mem_bist_i3, fabric_system_data_to_mem_bist_i4, fabric_system_data_to_mem_bist_i5, fabric_system_data_to_mem_bist_i6, fabric_system_data_to_mem_bist_i7
+, fabric_system_data_to_mem_bist_i8, fabric_system_data_to_mem_bist_i9, fabric_system_data_to_mem_bist_i10, fabric_system_data_to_mem_bist_i11, fabric_system_data_to_mem_bist_i12, fabric_system_data_to_mem_bist_i13, fabric_system_data_to_mem_bist_i14, fabric_system_data_to_mem_bist_i15, fabric_system_data_to_mem_bist_i16, fabric_system_data_to_mem_bist_i17, fabric_system_data_to_mem_bist_i18, fabric_system_data_to_mem_bist_i19, fabric_system_data_to_mem_bist_i20, fabric_system_data_to_mem_bist_i21, fabric_system_data_to_mem_bist_i22, fabric_system_data_to_mem_bist_i23, fabric_system_data_to_mem_bist_i24, fabric_tst_atpg_mrepair_i, fabric_mrepair_fuse_tstscanenable_i, fabric_otp_security_bistmode_i, fabric_lowskew_i22
+, fabric_lowskew_i23, fabric_lowskew_i20, fabric_otp_user_tst_scanin_i1, fabric_otp_user_tst_scanin_i2, fabric_otp_user_tst_scanin_i3, fabric_otp_user_tst_scanin_i4, fabric_otp_user_tst_scanin_i5, fabric_sif_update_en_i1, fabric_sif_update_en_i2, fabric_sif_update_en_i3, fabric_sif_update_en_i4, fabric_sif_update_en_i5, fabric_sif_update_en_i6, fabric_sif_update_en_i7, fabric_sif_update_en_i8, fabric_sif_update_en_i9, fabric_sif_update_en_i10, fabric_sif_update_en_i11, fabric_sif_update_en_i12, fabric_sif_update_en_i13, fabric_sif_update_en_i14
+, fabric_sif_update_en_i15, fabric_sif_update_en_i16, fabric_sif_update_en_i17, fabric_sif_update_en_i18, fabric_sif_update_en_i19, fabric_sif_update_en_i20, fabric_sif_update_en_i21, fabric_sif_update_en_i22, fabric_sif_update_en_i23, fabric_sif_update_en_i24, fabric_mrepair_por_i, fabric_mrepair_rst_n_i, fabric_mrepair_initn_i, fabric_mrepair_cke_i, fabric_clk_otp_mux_i, fabric_mrepair_cke_force_i, fabric_mrepair_fuse_bbad_o, fabric_jtag_trst_n_o, fabric_debug_direct_permission_write_o1, fabric_debug_direct_permission_write_o2, fabric_debug_direct_permission_write_o3
+, fabric_debug_direct_permission_write_o4, fabric_otp_security_bist_end1_o, fabric_parusr_data_val_o, fabric_debug_lock_reg_o, fabric_debug_security_error_read_o, fabric_mrepair_fuse_tstscanout_o1, fabric_mrepair_fuse_tstscanout_o2, fabric_mrepair_fuse_tstscanout_o3, fabric_mrepair_fuse_tstscanout_o4, fabric_mrepair_fuse_tstscanout_o5, fabric_otp_user_tst_scanout_o1, fabric_otp_user_tst_scanout_o2, fabric_otp_user_tst_scanout_o3, fabric_otp_user_tst_scanout_o4, fabric_otp_user_tst_scanout_o5, fabric_sif_update_en_to_bist_o1, fabric_sif_update_en_to_bist_o2, fabric_sif_update_en_to_bist_o3, fabric_sif_update_en_to_bist_o4, fabric_sif_update_en_to_bist_o5, fabric_sif_update_en_to_bist_o6
+, fabric_sif_update_en_to_bist_o7, fabric_sif_update_en_to_bist_o8, fabric_sif_update_en_to_bist_o9, fabric_sif_update_en_to_bist_o10, fabric_sif_update_en_to_bist_o11, fabric_sif_update_en_to_bist_o12, fabric_sif_update_en_to_bist_o13, fabric_sif_update_en_to_bist_o14, fabric_sif_update_en_to_bist_o15, fabric_sif_update_en_to_bist_o16, fabric_sif_update_en_to_bist_o17, fabric_sif_update_en_to_bist_o18, fabric_sif_update_en_to_bist_o19, fabric_sif_update_en_to_bist_o20, fabric_sif_update_en_to_bist_o21, fabric_sif_update_en_to_bist_o22, fabric_sif_update_en_to_bist_o23, fabric_sif_update_en_to_bist_o24, fabric_otp_user_locked_o, fabric_otp_security_bist_bad_o, fabric_debug_frame_permission_frame_o1
+, fabric_debug_frame_permission_frame_o2, fabric_debug_frame_permission_frame_o3, fabric_debug_frame_permission_frame_o4, fabric_otp_user_pwok_o, fabric_otp_user_bend2_o, fabric_mrepair_fuse_ded_o, fabric_debug_access_reg_data_ready_o, fabric_data_to_bist_o1, fabric_data_to_bist_o2, fabric_data_to_bist_o3, fabric_data_to_bist_o4, fabric_data_to_bist_o5, fabric_data_to_bist_o6, fabric_data_to_bist_o7, fabric_data_to_bist_o8, fabric_data_to_bist_o9, fabric_data_to_bist_o10, fabric_data_to_bist_o11, fabric_data_to_bist_o12, fabric_data_to_bist_o13, fabric_data_to_bist_o14
+, fabric_data_to_bist_o15, fabric_data_to_bist_o16, fabric_data_to_bist_o17, fabric_data_to_bist_o18, fabric_data_to_bist_o19, fabric_data_to_bist_o20, fabric_data_to_bist_o21, fabric_data_to_bist_o22, fabric_data_to_bist_o23, fabric_data_to_bist_o24, fabric_otp_user_startword_o1, fabric_otp_user_startword_o2, fabric_otp_user_startword_o3, fabric_otp_user_startword_o4, fabric_otp_user_startword_o5, fabric_otp_user_startword_o6, fabric_otp_user_startword_o7, fabric_otp_user_startword_o8, fabric_otp_user_startword_o9, fabric_otp_user_startword_o10, fabric_otp_user_startword_o11
+, fabric_otp_user_startword_o12, fabric_otp_user_startword_o13, fabric_otp_user_startword_o14, fabric_otp_user_startword_o15, fabric_otp_user_startword_o16, fabric_ahb_direct_data_o1, fabric_ahb_direct_data_o2, fabric_ahb_direct_data_o3, fabric_ahb_direct_data_o4, fabric_ahb_direct_data_o5, fabric_ahb_direct_data_o6, fabric_ahb_direct_data_o7, fabric_ahb_direct_data_o8, fabric_ahb_direct_data_o9, fabric_ahb_direct_data_o10, fabric_ahb_direct_data_o11, fabric_ahb_direct_data_o12, fabric_ahb_direct_data_o13, fabric_ahb_direct_data_o14, fabric_ahb_direct_data_o15, fabric_ahb_direct_data_o16
+, fabric_ahb_direct_data_o17, fabric_ahb_direct_data_o18, fabric_ahb_direct_data_o19, fabric_ahb_direct_data_o20, fabric_ahb_direct_data_o21, fabric_ahb_direct_data_o22, fabric_ahb_direct_data_o23, fabric_ahb_direct_data_o24, fabric_ahb_direct_data_o25, fabric_ahb_direct_data_o26, fabric_ahb_direct_data_o27, fabric_ahb_direct_data_o28, fabric_ahb_direct_data_o29, fabric_ahb_direct_data_o30, fabric_ahb_direct_data_o31, fabric_ahb_direct_data_o32, fabric_parusr_data_o1, fabric_parusr_data_o2, fabric_parusr_data_o3, fabric_parusr_data_o4, fabric_parusr_data_o5
+, fabric_parusr_data_o6, fabric_parusr_data_o7, fabric_parusr_data_o8, fabric_parusr_data_o9, fabric_parusr_data_o10, fabric_parusr_data_o11, fabric_parusr_data_o12, fabric_parusr_data_o13, fabric_parusr_data_o14, fabric_parusr_data_o15, fabric_parusr_data_o16, fabric_debug_otp_reload_err_o, fabric_cfg_fabric_user_enable_o, fabric_decoder_init_ready_o, fabric_global_chip_status_o1, fabric_global_chip_status_o2, fabric_global_chip_status_o3, fabric_debug_security_boot_done_o, fabric_otp_user_calibrated_o, fabric_fuse_status_o1, fabric_fuse_status_o2
+, fabric_fuse_status_o3, fabric_otp_apb_rdata_o1, fabric_otp_apb_rdata_o2, fabric_otp_apb_rdata_o3, fabric_otp_apb_rdata_o4, fabric_otp_apb_rdata_o5, fabric_otp_apb_rdata_o6, fabric_otp_apb_rdata_o7, fabric_otp_apb_rdata_o8, fabric_otp_apb_rdata_o9, fabric_otp_apb_rdata_o10, fabric_otp_apb_rdata_o11, fabric_otp_apb_rdata_o12, fabric_otp_apb_rdata_o13, fabric_otp_apb_rdata_o14, fabric_otp_apb_rdata_o15, fabric_otp_apb_rdata_o16, fabric_otp_apb_rdata_o17, fabric_otp_apb_rdata_o18, fabric_otp_apb_rdata_o19, fabric_otp_apb_rdata_o20
+, fabric_otp_apb_rdata_o21, fabric_otp_apb_rdata_o22, fabric_otp_apb_rdata_o23, fabric_otp_apb_rdata_o24, fabric_otp_apb_rdata_o25, fabric_otp_apb_rdata_o26, fabric_otp_apb_rdata_o27, fabric_otp_apb_rdata_o28, fabric_otp_apb_rdata_o29, fabric_otp_apb_rdata_o30, fabric_otp_apb_rdata_o31, fabric_otp_apb_rdata_o32, fabric_jtag_tms_o, fabric_debug_bsec_core_status_o1, fabric_debug_bsec_core_status_o2, fabric_debug_bsec_core_status_o3, fabric_debug_bsec_core_status_o4, fabric_debug_bsec_core_status_o5, fabric_debug_bsec_core_status_o6, fabric_debug_bsec_core_status_o7, fabric_debug_bsec_core_status_o8
+, fabric_debug_bsec_core_status_o9, fabric_debug_bsec_core_status_o10, fabric_debug_bsec_core_status_o11, fabric_debug_bsec_core_status_o12, fabric_debug_bsec_core_status_o13, fabric_debug_bsec_core_status_o14, fabric_debug_bsec_core_status_o15, fabric_debug_bsec_core_status_o16, fabric_debug_bsec_core_status_o17, fabric_debug_bsec_core_status_o18, fabric_debug_bsec_core_status_o19, fabric_debug_bsec_core_status_o20, fabric_debug_bsec_core_status_o21, fabric_debug_bsec_core_status_o22, fabric_debug_bsec_core_status_o23, fabric_debug_bsec_core_status_o24, fabric_debug_bsec_core_status_o25, fabric_debug_bsec_core_status_o26, fabric_debug_bsec_core_status_o27, fabric_debug_bsec_core_status_o28, fabric_debug_bsec_core_status_o29
+, fabric_debug_bsec_core_status_o30, fabric_debug_bsec_core_status_o31, fabric_debug_bsec_core_status_o32, fabric_mrepair_fuse_bist1fail_o1, fabric_mrepair_fuse_bist1fail_o2, fabric_mrepair_fuse_bist1fail_o3, fabric_mrepair_fuse_bist1fail_o4, fabric_mrepair_fuse_bist1fail_o5, fabric_mrepair_fuse_bist1fail_o6, fabric_mrepair_fuse_bist1fail_o7, fabric_mrepair_fuse_bist1fail_o8, fabric_flag_ready_TMR_o1, fabric_flag_ready_TMR_o2, fabric_flag_ready_TMR_o3, fabric_mrepair_fuse_dout_o1, fabric_mrepair_fuse_dout_o2, fabric_mrepair_fuse_dout_o3, fabric_mrepair_fuse_dout_o4, fabric_mrepair_fuse_dout_o5, fabric_mrepair_fuse_dout_o6, fabric_mrepair_fuse_dout_o7
+, fabric_mrepair_fuse_dout_o8, fabric_mrepair_fuse_dout_o9, fabric_mrepair_fuse_dout_o10, fabric_mrepair_fuse_dout_o11, fabric_mrepair_fuse_dout_o12, fabric_mrepair_fuse_dout_o13, fabric_mrepair_fuse_dout_o14, fabric_mrepair_fuse_dout_o15, fabric_mrepair_fuse_dout_o16, fabric_mrepair_fuse_dout_o17, fabric_mrepair_fuse_dout_o18, fabric_mrepair_fuse_dout_o19, fabric_mrepair_fuse_dout_o20, fabric_mrepair_fuse_dout_o21, fabric_mrepair_fuse_dout_o22, fabric_mrepair_fuse_dout_o23, fabric_mrepair_fuse_dout_o24, fabric_mrepair_fuse_dout_o25, fabric_mrepair_fuse_dout_o26, fabric_mrepair_fuse_dout_o27, fabric_mrepair_fuse_dout_o28
+, fabric_mrepair_fuse_dout_o29, fabric_mrepair_fuse_dout_o30, fabric_mrepair_fuse_dout_o31, fabric_mrepair_fuse_dout_o32, fabric_mrepair_fuse_dout_o33, fabric_mrepair_fuse_dout_o34, fabric_mrepair_fuse_dout_o35, fabric_mrepair_fuse_dout_o36, fabric_mrepair_fuse_dout_o37, fabric_mrepair_fuse_dout_o38, fabric_mrepair_fuse_dout_o39, fabric_mrepair_fuse_dout_o40, fabric_mrepair_fuse_dout_o41, fabric_debug_rst_soft_o, fabric_otp_user_ack_o, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_shift_en_to_bist_o1, fabric_shift_en_to_bist_o2, fabric_shift_en_to_bist_o3, fabric_shift_en_to_bist_o4, fabric_shift_en_to_bist_o5
+, fabric_shift_en_to_bist_o6, fabric_shift_en_to_bist_o7, fabric_shift_en_to_bist_o8, fabric_shift_en_to_bist_o9, fabric_shift_en_to_bist_o10, fabric_shift_en_to_bist_o11, fabric_shift_en_to_bist_o12, fabric_shift_en_to_bist_o13, fabric_shift_en_to_bist_o14, fabric_shift_en_to_bist_o15, fabric_shift_en_to_bist_o16, fabric_shift_en_to_bist_o17, fabric_shift_en_to_bist_o18, fabric_shift_en_to_bist_o19, fabric_shift_en_to_bist_o20, fabric_shift_en_to_bist_o21, fabric_shift_en_to_bist_o22, fabric_shift_en_to_bist_o23, fabric_shift_en_to_bist_o24, fabric_sif_reg_en_to_bist_o1, fabric_sif_reg_en_to_bist_o2
+, fabric_sif_reg_en_to_bist_o3, fabric_sif_reg_en_to_bist_o4, fabric_sif_reg_en_to_bist_o5, fabric_sif_reg_en_to_bist_o6, fabric_sif_reg_en_to_bist_o7, fabric_sif_reg_en_to_bist_o8, fabric_sif_reg_en_to_bist_o9, fabric_sif_reg_en_to_bist_o10, fabric_sif_reg_en_to_bist_o11, fabric_sif_reg_en_to_bist_o12, fabric_sif_reg_en_to_bist_o13, fabric_sif_reg_en_to_bist_o14, fabric_sif_reg_en_to_bist_o15, fabric_sif_reg_en_to_bist_o16, fabric_sif_reg_en_to_bist_o17, fabric_sif_reg_en_to_bist_o18, fabric_sif_reg_en_to_bist_o19, fabric_sif_reg_en_to_bist_o20, fabric_sif_reg_en_to_bist_o21, fabric_sif_reg_en_to_bist_o22, fabric_sif_reg_en_to_bist_o23
+, fabric_sif_reg_en_to_bist_o24, fabric_sif_reg_en_to_bist_o25, fabric_sif_reg_en_to_bist_o26, fabric_sif_reg_en_to_bist_o27, fabric_sif_reg_en_to_bist_o28, fabric_sif_reg_en_to_bist_o29, fabric_sif_reg_en_to_bist_o30, fabric_sif_reg_en_to_bist_o31, fabric_sif_reg_en_to_bist_o32, fabric_sif_reg_en_to_bist_o33, fabric_sif_reg_en_to_bist_o34, fabric_sif_reg_en_to_bist_o35, fabric_sif_reg_en_to_bist_o36, fabric_sif_reg_en_to_bist_o37, fabric_sif_reg_en_to_bist_o38, fabric_sif_reg_en_to_bist_o39, fabric_sif_reg_en_to_bist_o40, fabric_sif_reg_en_to_bist_o41, fabric_sif_reg_en_to_bist_o42, fabric_sif_reg_en_to_bist_o43, fabric_sif_reg_en_to_bist_o44
+, fabric_sif_reg_en_to_bist_o45, fabric_sif_reg_en_to_bist_o46, fabric_sif_reg_en_to_bist_o47, fabric_sif_reg_en_to_bist_o48, fabric_sif_reg_en_to_bist_o49, fabric_sif_reg_en_to_bist_o50, fabric_sif_reg_en_to_bist_o51, fabric_sif_reg_en_to_bist_o52, fabric_sif_reg_en_to_bist_o53, fabric_sif_reg_en_to_bist_o54, fabric_sif_reg_en_to_bist_o55, fabric_sif_reg_en_to_bist_o56, fabric_sif_reg_en_to_bist_o57, fabric_sif_reg_en_to_bist_o58, fabric_sif_reg_en_to_bist_o59, fabric_sif_reg_en_to_bist_o60, fabric_sif_reg_en_to_bist_o61, fabric_sif_reg_en_to_bist_o62, fabric_sif_reg_en_to_bist_o63, fabric_sif_reg_en_to_bist_o64, fabric_sif_reg_en_to_bist_o65
+, fabric_sif_reg_en_to_bist_o66, fabric_sif_reg_en_to_bist_o67, fabric_sif_reg_en_to_bist_o68, fabric_sif_reg_en_to_bist_o69, fabric_sif_reg_en_to_bist_o70, fabric_sif_reg_en_to_bist_o71, fabric_sif_reg_en_to_bist_o72, fabric_sif_reg_en_to_bist_o73, fabric_sif_reg_en_to_bist_o74, fabric_sif_reg_en_to_bist_o75, fabric_sif_reg_en_to_bist_o76, fabric_sif_reg_en_to_bist_o77, fabric_sif_reg_en_to_bist_o78, fabric_sif_reg_en_to_bist_o79, fabric_sif_reg_en_to_bist_o80, fabric_sif_reg_en_to_bist_o81, fabric_sif_reg_en_to_bist_o82, fabric_sif_reg_en_to_bist_o83, fabric_sif_reg_en_to_bist_o84, fabric_sif_reg_en_to_bist_o85, fabric_sif_reg_en_to_bist_o86
+, fabric_sif_reg_en_to_bist_o87, fabric_sif_reg_en_to_bist_o88, fabric_sif_reg_en_to_bist_o89, fabric_sif_reg_en_to_bist_o90, fabric_sif_reg_en_to_bist_o91, fabric_sif_reg_en_to_bist_o92, fabric_sif_reg_en_to_bist_o93, fabric_sif_reg_en_to_bist_o94, fabric_sif_reg_en_to_bist_o95, fabric_sif_reg_en_to_bist_o96, fabric_sif_reg_en_to_bist_o97, fabric_sif_reg_en_to_bist_o98, fabric_sif_reg_en_to_bist_o99, fabric_sif_reg_en_to_bist_o100, fabric_sif_reg_en_to_bist_o101, fabric_sif_reg_en_to_bist_o102, fabric_sif_reg_en_to_bist_o103, fabric_sif_reg_en_to_bist_o104, fabric_sif_reg_en_to_bist_o105, fabric_sif_reg_en_to_bist_o106, fabric_sif_reg_en_to_bist_o107
+, fabric_sif_reg_en_to_bist_o108, fabric_sif_reg_en_to_bist_o109, fabric_sif_reg_en_to_bist_o110, fabric_sif_reg_en_to_bist_o111, fabric_sif_reg_en_to_bist_o112, fabric_sif_reg_en_to_bist_o113, fabric_sif_reg_en_to_bist_o114, fabric_sif_reg_en_to_bist_o115, fabric_sif_reg_en_to_bist_o116, fabric_sif_reg_en_to_bist_o117, fabric_sif_reg_en_to_bist_o118, fabric_sif_reg_en_to_bist_o119, fabric_sif_reg_en_to_bist_o120, fabric_debug_otp_manager_read_otp_o, fabric_otp_user_sec_o, fabric_otp_user_wlromout_o1, fabric_otp_user_wlromout_o2, fabric_otp_user_wlromout_o3, fabric_otp_user_wlromout_o4, fabric_otp_user_wlromout_o5, fabric_otp_user_wlromout_o6
+, fabric_otp_user_wlromout_o7, fabric_otp_user_wlromout_o8, fabric_otp_user_wlromout_o9, fabric_otp_user_wlromout_o10, fabric_mrepair_fuse_bend1_o, fabric_mrepair_fuse_flagstate_o1, fabric_mrepair_fuse_flagstate_o2, fabric_mrepair_fuse_flagstate_o3, fabric_mrepair_fuse_flagstate_o4, fabric_system_data_from_mem_bist_o1, fabric_system_data_from_mem_bist_o2, fabric_system_data_from_mem_bist_o3, fabric_system_data_from_mem_bist_o4, fabric_system_data_from_mem_bist_o5, fabric_system_data_from_mem_bist_o6, fabric_system_data_from_mem_bist_o7, fabric_system_data_from_mem_bist_o8, fabric_system_data_from_mem_bist_o9, fabric_system_data_from_mem_bist_o10, fabric_system_data_from_mem_bist_o11, fabric_system_data_from_mem_bist_o12
+, fabric_system_data_from_mem_bist_o13, fabric_system_data_from_mem_bist_o14, fabric_system_data_from_mem_bist_o15, fabric_system_data_from_mem_bist_o16, fabric_system_data_from_mem_bist_o17, fabric_system_data_from_mem_bist_o18, fabric_system_data_from_mem_bist_o19, fabric_system_data_from_mem_bist_o20, fabric_system_data_from_mem_bist_o21, fabric_system_data_from_mem_bist_o22, fabric_system_data_from_mem_bist_o23, fabric_system_data_from_mem_bist_o24, fabric_direct_data_o1, fabric_direct_data_o2, fabric_direct_data_o3, fabric_direct_data_o4, fabric_direct_data_o5, fabric_direct_data_o6, fabric_direct_data_o7, fabric_direct_data_o8, fabric_direct_data_o9
+, fabric_direct_data_o10, fabric_direct_data_o11, fabric_direct_data_o12, fabric_direct_data_o13, fabric_direct_data_o14, fabric_direct_data_o15, fabric_direct_data_o16, fabric_direct_data_o17, fabric_direct_data_o18, fabric_direct_data_o19, fabric_direct_data_o20, fabric_direct_data_o21, fabric_direct_data_o22, fabric_direct_data_o23, fabric_direct_data_o24, fabric_direct_data_o25, fabric_direct_data_o26, fabric_direct_data_o27, fabric_direct_data_o28, fabric_direct_data_o29, fabric_direct_data_o30
+, fabric_direct_data_o31, fabric_direct_data_o32, fabric_otp_user_bbad_o, fabric_user_read_cycle_o, fabric_chip_status_o1, fabric_chip_status_o2, fabric_chip_status_o3, fabric_chip_status_o4, fabric_chip_status_o5, fabric_chip_status_o6, fabric_chip_status_o7, fabric_chip_status_o8, fabric_chip_status_o9, fabric_chip_status_o10, fabric_chip_status_o11, fabric_chip_status_o12, fabric_chip_status_o13, fabric_chip_status_o14, fabric_chip_status_o15, fabric_chip_status_o16, fabric_chip_status_o17
+, fabric_chip_status_o18, fabric_chip_status_o19, fabric_chip_status_o20, fabric_chip_status_o21, fabric_chip_status_o22, fabric_chip_status_o23, fabric_chip_status_o24, fabric_chip_status_o25, fabric_chip_status_o26, fabric_chip_status_o27, fabric_chip_status_o28, fabric_chip_status_o29, fabric_chip_status_o30, fabric_chip_status_o31, fabric_chip_status_o32, fabric_chip_status_o33, fabric_chip_status_o34, fabric_chip_status_o35, fabric_chip_status_o36, fabric_chip_status_o37, fabric_chip_status_o38
+, fabric_chip_status_o39, fabric_chip_status_o40, fabric_chip_status_o41, fabric_chip_status_o42, fabric_chip_status_o43, fabric_chip_status_o44, fabric_chip_status_o45, fabric_chip_status_o46, fabric_chip_status_o47, fabric_chip_status_o48, fabric_chip_status_o49, fabric_chip_status_o50, fabric_chip_status_o51, fabric_chip_status_o52, fabric_chip_status_o53, fabric_chip_status_o54, fabric_chip_status_o55, fabric_chip_status_o56, fabric_chip_status_o57, fabric_chip_status_o58, fabric_chip_status_o59
+, fabric_chip_status_o60, fabric_chip_status_o61, fabric_chip_status_o62, fabric_chip_status_o63, fabric_chip_status_o64, fabric_chip_status_o65, fabric_chip_status_o66, fabric_chip_status_o67, fabric_chip_status_o68, fabric_chip_status_o69, fabric_chip_status_o70, fabric_chip_status_o71, fabric_chip_status_o72, fabric_mrepair_fuse_disturbed_o, fabric_debug_otpboot_state_o1, fabric_debug_otpboot_state_o2, fabric_debug_otpboot_state_o3, fabric_pd_ready_o1, fabric_pd_ready_o2, fabric_pd_ready_o3, fabric_pd_ready_o4
+, fabric_pd_ready_o5, fabric_pd_ready_o6, fabric_pd_ready_o7, fabric_pd_ready_o8, fabric_pd_ready_o9, fabric_pd_ready_o10, fabric_pd_ready_o11, fabric_pd_ready_o12, fabric_pd_ready_o13, fabric_pd_ready_o14, fabric_pd_ready_o15, fabric_pd_ready_o16, fabric_pd_ready_o17, fabric_pd_ready_o18, fabric_pd_ready_o19, fabric_pd_ready_o20, fabric_pd_ready_o21, fabric_pd_ready_o22, fabric_pd_ready_o23, fabric_pd_ready_o24, fabric_debug_key_correct_o
+, fabric_otp_apb_ready_o, fabric_otp_user_progfail_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_bend2_o, fabric_debug_lifecycle_o1, fabric_debug_lifecycle_o2, fabric_debug_lifecycle_o3, fabric_debug_lifecycle_o4, fabric_mrepair_fuse_ack_o, fabric_debug_cpt_retry_o1, fabric_debug_cpt_retry_o2, fabric_debug_cpt_retry_o3, fabric_debug_cpt_retry_o4, fabric_otp_security_ack_o, fabric_debug_otpmgmt_state_o1, fabric_debug_otpmgmt_state_o2, fabric_debug_otpmgmt_state_o3, fabric_mrepair_fuse_progfail_o, fabric_otp_user_bist2fail_o1, fabric_otp_user_bist2fail_o2, fabric_otp_user_bist2fail_o3
+, fabric_otp_user_bist2fail_o4, fabric_otp_user_bist2fail_o5, fabric_otp_user_bist2fail_o6, fabric_otp_user_bist2fail_o7, fabric_user_data_o1, fabric_user_data_o2, fabric_user_data_o3, fabric_user_data_o4, fabric_user_data_o5, fabric_user_data_o6, fabric_user_data_o7, fabric_user_data_o8, fabric_user_data_o9, fabric_user_data_o10, fabric_user_data_o11, fabric_user_data_o12, fabric_user_data_o13, fabric_user_data_o14, fabric_user_data_o15, fabric_user_data_o16, fabric_user_data_o17
+, fabric_user_data_o18, fabric_user_data_o19, fabric_user_data_o20, fabric_user_data_o21, fabric_user_data_o22, fabric_user_data_o23, fabric_user_data_o24, fabric_user_data_o25, fabric_user_data_o26, fabric_user_data_o27, fabric_user_data_o28, fabric_user_data_o29, fabric_user_data_o30, fabric_user_data_o31, fabric_user_data_o32, fabric_jtag_tdi_o, fabric_lowskew_o3, fabric_lowskew_o5, fabric_lowskew_o4, fabric_debug_error_o, fabric_jtag_usr2_o
+, fabric_mrepair_fuse_wlromout_o1, fabric_mrepair_fuse_wlromout_o2, fabric_mrepair_fuse_wlromout_o3, fabric_mrepair_fuse_wlromout_o4, fabric_mrepair_fuse_wlromout_o5, fabric_mrepair_fuse_wlromout_o6, fabric_mrepair_fuse_wlromout_o7, fabric_mrepair_fuse_wlromout_o8, fabric_mrepair_fuse_wlromout_o9, fabric_mrepair_fuse_wlromout_o10, fabric_debug_otpapb_state_o1, fabric_debug_otpapb_state_o2, fabric_debug_otpapb_state_o3, fabric_otp_user_bist1fail_o1, fabric_otp_user_bist1fail_o2, fabric_otp_user_bist1fail_o3, fabric_otp_user_bist1fail_o4, fabric_otp_user_bist1fail_o5, fabric_otp_user_bist1fail_o6, fabric_otp_user_bist1fail_o7, fabric_otp_user_bist1fail_o8
+, fabric_otp_security_bist_fail2_o1, fabric_otp_security_bist_fail2_o2, fabric_otp_security_bist_fail2_o3, fabric_otp_security_bist_fail2_o4, fabric_otp_security_bist_fail2_o5, fabric_otp_security_bist_fail2_o6, fabric_otp_security_bist_fail2_o7, fabric_otp_user_disturbed_o, fabric_flag_trigger_o, fabric_otp_security_bist_end2_o, fabric_otp_security_bist_fail1_o1, fabric_otp_security_bist_fail1_o2, fabric_otp_security_bist_fail1_o3, fabric_otp_security_bist_fail1_o4, fabric_otp_security_bist_fail1_o5, fabric_otp_security_bist_fail1_o6, fabric_otp_security_bist_fail1_o7, fabric_otp_security_bist_fail1_o8, fabric_mrepair_fuse_locked_o, fabric_otp_user_flagstate_o1, fabric_otp_user_flagstate_o2
+, fabric_otp_user_flagstate_o3, fabric_otp_user_flagstate_o4, fabric_otp_security_scanout_o1, fabric_otp_security_scanout_o2, fabric_otp_security_scanout_o3, fabric_otp_security_scanout_o4, fabric_otp_security_scanout_o5, fabric_user_write_cycle_o, fabric_debug_fsm_state_o1, fabric_debug_fsm_state_o2, fabric_debug_fsm_state_o3, fabric_otp_user_ded_o, fabric_debug_otp_manager_read_done_o, fabric_debug_frame_use_encryption_o, fabric_data_to_system_o, fabric_jtag_usr1_o, fabric_otp_user_bend1_o, fabric_debug_otpboot_curr_addr_o1, fabric_debug_otpboot_curr_addr_o2, fabric_debug_otpboot_curr_addr_o3, fabric_debug_otpboot_curr_addr_o4
+, fabric_debug_otpboot_curr_addr_o5, fabric_debug_otpboot_curr_addr_o6, fabric_debug_otpboot_curr_addr_o7, fabric_debug_otpboot_curr_addr_o8, fabric_mrepair_fuse_ready_o, fabric_mrepair_fuse_calibrated_o, fabric_sif_load_en_to_bist_o1, fabric_sif_load_en_to_bist_o2, fabric_sif_load_en_to_bist_o3, fabric_sif_load_en_to_bist_o4, fabric_sif_load_en_to_bist_o5, fabric_sif_load_en_to_bist_o6, fabric_sif_load_en_to_bist_o7, fabric_sif_load_en_to_bist_o8, fabric_sif_load_en_to_bist_o9, fabric_sif_load_en_to_bist_o10, fabric_sif_load_en_to_bist_o11, fabric_sif_load_en_to_bist_o12, fabric_sif_load_en_to_bist_o13, fabric_sif_load_en_to_bist_o14, fabric_sif_load_en_to_bist_o15
+, fabric_sif_load_en_to_bist_o16, fabric_sif_load_en_to_bist_o17, fabric_sif_load_en_to_bist_o18, fabric_sif_load_en_to_bist_o19, fabric_sif_load_en_to_bist_o20, fabric_sif_load_en_to_bist_o21, fabric_sif_load_en_to_bist_o22, fabric_sif_load_en_to_bist_o23, fabric_sif_load_en_to_bist_o24, fabric_io_out_o1, fabric_io_out_o2, fabric_io_out_o3, fabric_io_out_o4, fabric_io_out_o5, fabric_io_out_o6, fabric_io_out_o7, fabric_io_out_o8, fabric_io_out_o9, fabric_io_out_o10, fabric_io_out_o11, fabric_io_out_o12
+, fabric_io_out_o13, fabric_io_out_o14, fabric_io_out_o15, fabric_io_out_o16, fabric_io_out_o17, fabric_io_out_o18, fabric_io_out_o19, fabric_io_out_o20, fabric_io_out_o21, fabric_io_out_o22, fabric_io_out_o23, fabric_io_out_o24, fabric_io_out_o25, fabric_mrepair_fuse_startword_o1, fabric_mrepair_fuse_startword_o2, fabric_mrepair_fuse_startword_o3, fabric_mrepair_fuse_startword_o4, fabric_mrepair_fuse_startword_o5, fabric_mrepair_fuse_startword_o6, fabric_mrepair_fuse_startword_o7, fabric_mrepair_fuse_startword_o8
+, fabric_mrepair_fuse_startword_o9, fabric_mrepair_fuse_startword_o10, fabric_mrepair_fuse_startword_o11, fabric_mrepair_fuse_startword_o12, fabric_mrepair_fuse_startword_o13, fabric_mrepair_fuse_startword_o14, fabric_mrepair_fuse_startword_o15, fabric_mrepair_fuse_startword_o16, fabric_system_dataready_o, fabric_mrepair_fuse_pwok_o, fabric_lowskew_o6, fabric_cfg_fabric_user_flag_o, fabric_otp_user_dout_o1, fabric_otp_user_dout_o2, fabric_otp_user_dout_o3, fabric_otp_user_dout_o4, fabric_otp_user_dout_o5, fabric_otp_user_dout_o6, fabric_otp_user_dout_o7, fabric_otp_user_dout_o8, fabric_otp_user_dout_o9
+, fabric_otp_user_dout_o10, fabric_otp_user_dout_o11, fabric_otp_user_dout_o12, fabric_otp_user_dout_o13, fabric_otp_user_dout_o14, fabric_otp_user_dout_o15, fabric_otp_user_dout_o16, fabric_otp_user_dout_o17, fabric_otp_user_dout_o18, fabric_otp_user_dout_o19, fabric_otp_user_dout_o20, fabric_otp_user_dout_o21, fabric_otp_user_dout_o22, fabric_otp_user_dout_o23, fabric_otp_user_dout_o24, fabric_otp_user_dout_o25, fabric_otp_user_dout_o26, fabric_otp_user_dout_o27, fabric_otp_user_dout_o28, fabric_otp_user_dout_o29, fabric_otp_user_dout_o30
+, fabric_otp_user_dout_o31, fabric_otp_user_dout_o32, fabric_otp_user_dout_o33, fabric_otp_user_dout_o34, fabric_otp_user_dout_o35, fabric_otp_user_dout_o36, fabric_otp_user_dout_o37, fabric_otp_user_dout_o38, fabric_otp_user_dout_o39, fabric_otp_user_dout_o40, fabric_otp_user_dout_o41, fabric_mrepair_fuse_bist2fail_o1, fabric_mrepair_fuse_bist2fail_o2, fabric_mrepair_fuse_bist2fail_o3, fabric_mrepair_fuse_bist2fail_o4, fabric_mrepair_fuse_bist2fail_o5, fabric_mrepair_fuse_bist2fail_o6, fabric_mrepair_fuse_bist2fail_o7, fabric_status_cold_start_o, fabric_flag_error_o, fabric_debug_direct_permission_read_o1
+, fabric_debug_direct_permission_read_o2, fabric_debug_direct_permission_read_o3, fabric_debug_direct_permission_read_o4, fabric_otp_user_clock_frequency_range_i, fabric_parusr_enable_i);
+    input fabric_ahb_direct_data_i1;
+    input fabric_ahb_direct_data_i10;
+    input fabric_ahb_direct_data_i11;
+    input fabric_ahb_direct_data_i12;
+    input fabric_ahb_direct_data_i13;
+    input fabric_ahb_direct_data_i14;
+    input fabric_ahb_direct_data_i15;
+    input fabric_ahb_direct_data_i16;
+    input fabric_ahb_direct_data_i17;
+    input fabric_ahb_direct_data_i18;
+    input fabric_ahb_direct_data_i19;
+    input fabric_ahb_direct_data_i2;
+    input fabric_ahb_direct_data_i20;
+    input fabric_ahb_direct_data_i21;
+    input fabric_ahb_direct_data_i22;
+    input fabric_ahb_direct_data_i23;
+    input fabric_ahb_direct_data_i24;
+    input fabric_ahb_direct_data_i25;
+    input fabric_ahb_direct_data_i26;
+    input fabric_ahb_direct_data_i27;
+    input fabric_ahb_direct_data_i28;
+    input fabric_ahb_direct_data_i29;
+    input fabric_ahb_direct_data_i3;
+    input fabric_ahb_direct_data_i30;
+    input fabric_ahb_direct_data_i31;
+    input fabric_ahb_direct_data_i32;
+    input fabric_ahb_direct_data_i4;
+    input fabric_ahb_direct_data_i5;
+    input fabric_ahb_direct_data_i6;
+    input fabric_ahb_direct_data_i7;
+    input fabric_ahb_direct_data_i8;
+    input fabric_ahb_direct_data_i9;
+    output fabric_ahb_direct_data_o1;
+    output fabric_ahb_direct_data_o10;
+    output fabric_ahb_direct_data_o11;
+    output fabric_ahb_direct_data_o12;
+    output fabric_ahb_direct_data_o13;
+    output fabric_ahb_direct_data_o14;
+    output fabric_ahb_direct_data_o15;
+    output fabric_ahb_direct_data_o16;
+    output fabric_ahb_direct_data_o17;
+    output fabric_ahb_direct_data_o18;
+    output fabric_ahb_direct_data_o19;
+    output fabric_ahb_direct_data_o2;
+    output fabric_ahb_direct_data_o20;
+    output fabric_ahb_direct_data_o21;
+    output fabric_ahb_direct_data_o22;
+    output fabric_ahb_direct_data_o23;
+    output fabric_ahb_direct_data_o24;
+    output fabric_ahb_direct_data_o25;
+    output fabric_ahb_direct_data_o26;
+    output fabric_ahb_direct_data_o27;
+    output fabric_ahb_direct_data_o28;
+    output fabric_ahb_direct_data_o29;
+    output fabric_ahb_direct_data_o3;
+    output fabric_ahb_direct_data_o30;
+    output fabric_ahb_direct_data_o31;
+    output fabric_ahb_direct_data_o32;
+    output fabric_ahb_direct_data_o4;
+    output fabric_ahb_direct_data_o5;
+    output fabric_ahb_direct_data_o6;
+    output fabric_ahb_direct_data_o7;
+    output fabric_ahb_direct_data_o8;
+    output fabric_ahb_direct_data_o9;
+    output fabric_cfg_fabric_user_enable_o;
+    output fabric_cfg_fabric_user_flag_o;
+    output fabric_chip_status_o1;
+    output fabric_chip_status_o10;
+    output fabric_chip_status_o11;
+    output fabric_chip_status_o12;
+    output fabric_chip_status_o13;
+    output fabric_chip_status_o14;
+    output fabric_chip_status_o15;
+    output fabric_chip_status_o16;
+    output fabric_chip_status_o17;
+    output fabric_chip_status_o18;
+    output fabric_chip_status_o19;
+    output fabric_chip_status_o2;
+    output fabric_chip_status_o20;
+    output fabric_chip_status_o21;
+    output fabric_chip_status_o22;
+    output fabric_chip_status_o23;
+    output fabric_chip_status_o24;
+    output fabric_chip_status_o25;
+    output fabric_chip_status_o26;
+    output fabric_chip_status_o27;
+    output fabric_chip_status_o28;
+    output fabric_chip_status_o29;
+    output fabric_chip_status_o3;
+    output fabric_chip_status_o30;
+    output fabric_chip_status_o31;
+    output fabric_chip_status_o32;
+    output fabric_chip_status_o33;
+    output fabric_chip_status_o34;
+    output fabric_chip_status_o35;
+    output fabric_chip_status_o36;
+    output fabric_chip_status_o37;
+    output fabric_chip_status_o38;
+    output fabric_chip_status_o39;
+    output fabric_chip_status_o4;
+    output fabric_chip_status_o40;
+    output fabric_chip_status_o41;
+    output fabric_chip_status_o42;
+    output fabric_chip_status_o43;
+    output fabric_chip_status_o44;
+    output fabric_chip_status_o45;
+    output fabric_chip_status_o46;
+    output fabric_chip_status_o47;
+    output fabric_chip_status_o48;
+    output fabric_chip_status_o49;
+    output fabric_chip_status_o5;
+    output fabric_chip_status_o50;
+    output fabric_chip_status_o51;
+    output fabric_chip_status_o52;
+    output fabric_chip_status_o53;
+    output fabric_chip_status_o54;
+    output fabric_chip_status_o55;
+    output fabric_chip_status_o56;
+    output fabric_chip_status_o57;
+    output fabric_chip_status_o58;
+    output fabric_chip_status_o59;
+    output fabric_chip_status_o6;
+    output fabric_chip_status_o60;
+    output fabric_chip_status_o61;
+    output fabric_chip_status_o62;
+    output fabric_chip_status_o63;
+    output fabric_chip_status_o64;
+    output fabric_chip_status_o65;
+    output fabric_chip_status_o66;
+    output fabric_chip_status_o67;
+    output fabric_chip_status_o68;
+    output fabric_chip_status_o69;
+    output fabric_chip_status_o7;
+    output fabric_chip_status_o70;
+    output fabric_chip_status_o71;
+    output fabric_chip_status_o72;
+    output fabric_chip_status_o8;
+    output fabric_chip_status_o9;
+    input fabric_clk_otp_mux_i;
+    input fabric_data_from_bist_i1;
+    input fabric_data_from_bist_i10;
+    input fabric_data_from_bist_i11;
+    input fabric_data_from_bist_i12;
+    input fabric_data_from_bist_i13;
+    input fabric_data_from_bist_i14;
+    input fabric_data_from_bist_i15;
+    input fabric_data_from_bist_i16;
+    input fabric_data_from_bist_i17;
+    input fabric_data_from_bist_i18;
+    input fabric_data_from_bist_i19;
+    input fabric_data_from_bist_i2;
+    input fabric_data_from_bist_i20;
+    input fabric_data_from_bist_i21;
+    input fabric_data_from_bist_i22;
+    input fabric_data_from_bist_i23;
+    input fabric_data_from_bist_i24;
+    input fabric_data_from_bist_i3;
+    input fabric_data_from_bist_i4;
+    input fabric_data_from_bist_i5;
+    input fabric_data_from_bist_i6;
+    input fabric_data_from_bist_i7;
+    input fabric_data_from_bist_i8;
+    input fabric_data_from_bist_i9;
+    input fabric_data_from_system_i;
+    input fabric_data_shift_en_i;
+    output fabric_data_to_bist_o1;
+    output fabric_data_to_bist_o10;
+    output fabric_data_to_bist_o11;
+    output fabric_data_to_bist_o12;
+    output fabric_data_to_bist_o13;
+    output fabric_data_to_bist_o14;
+    output fabric_data_to_bist_o15;
+    output fabric_data_to_bist_o16;
+    output fabric_data_to_bist_o17;
+    output fabric_data_to_bist_o18;
+    output fabric_data_to_bist_o19;
+    output fabric_data_to_bist_o2;
+    output fabric_data_to_bist_o20;
+    output fabric_data_to_bist_o21;
+    output fabric_data_to_bist_o22;
+    output fabric_data_to_bist_o23;
+    output fabric_data_to_bist_o24;
+    output fabric_data_to_bist_o3;
+    output fabric_data_to_bist_o4;
+    output fabric_data_to_bist_o5;
+    output fabric_data_to_bist_o6;
+    output fabric_data_to_bist_o7;
+    output fabric_data_to_bist_o8;
+    output fabric_data_to_bist_o9;
+    output fabric_data_to_system_o;
+    output fabric_debug_access_reg_data_ready_o;
+    output fabric_debug_bsec_core_status_o1;
+    output fabric_debug_bsec_core_status_o10;
+    output fabric_debug_bsec_core_status_o11;
+    output fabric_debug_bsec_core_status_o12;
+    output fabric_debug_bsec_core_status_o13;
+    output fabric_debug_bsec_core_status_o14;
+    output fabric_debug_bsec_core_status_o15;
+    output fabric_debug_bsec_core_status_o16;
+    output fabric_debug_bsec_core_status_o17;
+    output fabric_debug_bsec_core_status_o18;
+    output fabric_debug_bsec_core_status_o19;
+    output fabric_debug_bsec_core_status_o2;
+    output fabric_debug_bsec_core_status_o20;
+    output fabric_debug_bsec_core_status_o21;
+    output fabric_debug_bsec_core_status_o22;
+    output fabric_debug_bsec_core_status_o23;
+    output fabric_debug_bsec_core_status_o24;
+    output fabric_debug_bsec_core_status_o25;
+    output fabric_debug_bsec_core_status_o26;
+    output fabric_debug_bsec_core_status_o27;
+    output fabric_debug_bsec_core_status_o28;
+    output fabric_debug_bsec_core_status_o29;
+    output fabric_debug_bsec_core_status_o3;
+    output fabric_debug_bsec_core_status_o30;
+    output fabric_debug_bsec_core_status_o31;
+    output fabric_debug_bsec_core_status_o32;
+    output fabric_debug_bsec_core_status_o4;
+    output fabric_debug_bsec_core_status_o5;
+    output fabric_debug_bsec_core_status_o6;
+    output fabric_debug_bsec_core_status_o7;
+    output fabric_debug_bsec_core_status_o8;
+    output fabric_debug_bsec_core_status_o9;
+    output fabric_debug_cpt_retry_o1;
+    output fabric_debug_cpt_retry_o2;
+    output fabric_debug_cpt_retry_o3;
+    output fabric_debug_cpt_retry_o4;
+    output fabric_debug_direct_permission_read_o1;
+    output fabric_debug_direct_permission_read_o2;
+    output fabric_debug_direct_permission_read_o3;
+    output fabric_debug_direct_permission_read_o4;
+    output fabric_debug_direct_permission_write_o1;
+    output fabric_debug_direct_permission_write_o2;
+    output fabric_debug_direct_permission_write_o3;
+    output fabric_debug_direct_permission_write_o4;
+    output fabric_debug_error_o;
+    output fabric_debug_frame_permission_frame_o1;
+    output fabric_debug_frame_permission_frame_o2;
+    output fabric_debug_frame_permission_frame_o3;
+    output fabric_debug_frame_permission_frame_o4;
+    output fabric_debug_frame_use_encryption_o;
+    output fabric_debug_fsm_state_o1;
+    output fabric_debug_fsm_state_o2;
+    output fabric_debug_fsm_state_o3;
+    output fabric_debug_key_correct_o;
+    output fabric_debug_lifecycle_o1;
+    output fabric_debug_lifecycle_o2;
+    output fabric_debug_lifecycle_o3;
+    output fabric_debug_lifecycle_o4;
+    output fabric_debug_lock_reg_o;
+    output fabric_debug_otp_manager_read_done_o;
+    output fabric_debug_otp_manager_read_otp_o;
+    output fabric_debug_otp_reload_err_o;
+    output fabric_debug_otpapb_state_o1;
+    output fabric_debug_otpapb_state_o2;
+    output fabric_debug_otpapb_state_o3;
+    output fabric_debug_otpboot_curr_addr_o1;
+    output fabric_debug_otpboot_curr_addr_o2;
+    output fabric_debug_otpboot_curr_addr_o3;
+    output fabric_debug_otpboot_curr_addr_o4;
+    output fabric_debug_otpboot_curr_addr_o5;
+    output fabric_debug_otpboot_curr_addr_o6;
+    output fabric_debug_otpboot_curr_addr_o7;
+    output fabric_debug_otpboot_curr_addr_o8;
+    output fabric_debug_otpboot_state_o1;
+    output fabric_debug_otpboot_state_o2;
+    output fabric_debug_otpboot_state_o3;
+    output fabric_debug_otpmgmt_state_o1;
+    output fabric_debug_otpmgmt_state_o2;
+    output fabric_debug_otpmgmt_state_o3;
+    output fabric_debug_rst_soft_o;
+    output fabric_debug_security_boot_done_o;
+    output fabric_debug_security_error_read_o;
+    output fabric_decoder_init_ready_o;
+    input fabric_direct_data_i1;
+    input fabric_direct_data_i10;
+    input fabric_direct_data_i11;
+    input fabric_direct_data_i12;
+    input fabric_direct_data_i13;
+    input fabric_direct_data_i14;
+    input fabric_direct_data_i15;
+    input fabric_direct_data_i16;
+    input fabric_direct_data_i17;
+    input fabric_direct_data_i18;
+    input fabric_direct_data_i19;
+    input fabric_direct_data_i2;
+    input fabric_direct_data_i20;
+    input fabric_direct_data_i21;
+    input fabric_direct_data_i22;
+    input fabric_direct_data_i23;
+    input fabric_direct_data_i24;
+    input fabric_direct_data_i25;
+    input fabric_direct_data_i26;
+    input fabric_direct_data_i27;
+    input fabric_direct_data_i28;
+    input fabric_direct_data_i29;
+    input fabric_direct_data_i3;
+    input fabric_direct_data_i30;
+    input fabric_direct_data_i31;
+    input fabric_direct_data_i32;
+    input fabric_direct_data_i4;
+    input fabric_direct_data_i5;
+    input fabric_direct_data_i6;
+    input fabric_direct_data_i7;
+    input fabric_direct_data_i8;
+    input fabric_direct_data_i9;
+    output fabric_direct_data_o1;
+    output fabric_direct_data_o10;
+    output fabric_direct_data_o11;
+    output fabric_direct_data_o12;
+    output fabric_direct_data_o13;
+    output fabric_direct_data_o14;
+    output fabric_direct_data_o15;
+    output fabric_direct_data_o16;
+    output fabric_direct_data_o17;
+    output fabric_direct_data_o18;
+    output fabric_direct_data_o19;
+    output fabric_direct_data_o2;
+    output fabric_direct_data_o20;
+    output fabric_direct_data_o21;
+    output fabric_direct_data_o22;
+    output fabric_direct_data_o23;
+    output fabric_direct_data_o24;
+    output fabric_direct_data_o25;
+    output fabric_direct_data_o26;
+    output fabric_direct_data_o27;
+    output fabric_direct_data_o28;
+    output fabric_direct_data_o29;
+    output fabric_direct_data_o3;
+    output fabric_direct_data_o30;
+    output fabric_direct_data_o31;
+    output fabric_direct_data_o32;
+    output fabric_direct_data_o4;
+    output fabric_direct_data_o5;
+    output fabric_direct_data_o6;
+    output fabric_direct_data_o7;
+    output fabric_direct_data_o8;
+    output fabric_direct_data_o9;
+    input fabric_end_encoding_i;
+    output fabric_flag_error_o;
+    output fabric_flag_ready_TMR_o1;
+    output fabric_flag_ready_TMR_o2;
+    output fabric_flag_ready_TMR_o3;
+    output fabric_flag_trigger_o;
+    output fabric_fuse_status_o1;
+    output fabric_fuse_status_o2;
+    output fabric_fuse_status_o3;
+    output fabric_global_chip_status_o1;
+    output fabric_global_chip_status_o2;
+    output fabric_global_chip_status_o3;
+    input fabric_io_in_i1;
+    input fabric_io_in_i10;
+    input fabric_io_in_i11;
+    input fabric_io_in_i12;
+    input fabric_io_in_i13;
+    input fabric_io_in_i14;
+    input fabric_io_in_i15;
+    input fabric_io_in_i16;
+    input fabric_io_in_i17;
+    input fabric_io_in_i18;
+    input fabric_io_in_i19;
+    input fabric_io_in_i2;
+    input fabric_io_in_i20;
+    input fabric_io_in_i21;
+    input fabric_io_in_i22;
+    input fabric_io_in_i23;
+    input fabric_io_in_i24;
+    input fabric_io_in_i25;
+    input fabric_io_in_i3;
+    input fabric_io_in_i4;
+    input fabric_io_in_i5;
+    input fabric_io_in_i6;
+    input fabric_io_in_i7;
+    input fabric_io_in_i8;
+    input fabric_io_in_i9;
+    input fabric_io_oe_i1;
+    input fabric_io_oe_i10;
+    input fabric_io_oe_i11;
+    input fabric_io_oe_i12;
+    input fabric_io_oe_i13;
+    input fabric_io_oe_i14;
+    input fabric_io_oe_i15;
+    input fabric_io_oe_i16;
+    input fabric_io_oe_i17;
+    input fabric_io_oe_i18;
+    input fabric_io_oe_i19;
+    input fabric_io_oe_i2;
+    input fabric_io_oe_i20;
+    input fabric_io_oe_i21;
+    input fabric_io_oe_i22;
+    input fabric_io_oe_i23;
+    input fabric_io_oe_i24;
+    input fabric_io_oe_i25;
+    input fabric_io_oe_i3;
+    input fabric_io_oe_i4;
+    input fabric_io_oe_i5;
+    input fabric_io_oe_i6;
+    input fabric_io_oe_i7;
+    input fabric_io_oe_i8;
+    input fabric_io_oe_i9;
+    output fabric_io_out_o1;
+    output fabric_io_out_o10;
+    output fabric_io_out_o11;
+    output fabric_io_out_o12;
+    output fabric_io_out_o13;
+    output fabric_io_out_o14;
+    output fabric_io_out_o15;
+    output fabric_io_out_o16;
+    output fabric_io_out_o17;
+    output fabric_io_out_o18;
+    output fabric_io_out_o19;
+    output fabric_io_out_o2;
+    output fabric_io_out_o20;
+    output fabric_io_out_o21;
+    output fabric_io_out_o22;
+    output fabric_io_out_o23;
+    output fabric_io_out_o24;
+    output fabric_io_out_o25;
+    output fabric_io_out_o3;
+    output fabric_io_out_o4;
+    output fabric_io_out_o5;
+    output fabric_io_out_o6;
+    output fabric_io_out_o7;
+    output fabric_io_out_o8;
+    output fabric_io_out_o9;
+    output fabric_jtag_tdi_o;
+    input fabric_jtag_tdo_usr1_i;
+    input fabric_jtag_tdo_usr2_i;
+    output fabric_jtag_tms_o;
+    output fabric_jtag_trst_n_o;
+    output fabric_jtag_usr1_o;
+    output fabric_jtag_usr2_o;
+    input fabric_lowskew_i20;
+    input fabric_lowskew_i21;
+    input fabric_lowskew_i22;
+    input fabric_lowskew_i23;
+    output fabric_lowskew_o3;
+    output fabric_lowskew_o4;
+    output fabric_lowskew_o5;
+    output fabric_lowskew_o6;
+    input fabric_mrepair_cke_force_i;
+    input fabric_mrepair_cke_i;
+    output fabric_mrepair_fuse_ack_o;
+    input fabric_mrepair_fuse_add_i1;
+    input fabric_mrepair_fuse_add_i2;
+    input fabric_mrepair_fuse_add_i3;
+    input fabric_mrepair_fuse_add_i4;
+    input fabric_mrepair_fuse_add_i5;
+    input fabric_mrepair_fuse_add_i6;
+    input fabric_mrepair_fuse_add_i7;
+    output fabric_mrepair_fuse_bbad_o;
+    output fabric_mrepair_fuse_bend1_o;
+    output fabric_mrepair_fuse_bend2_o;
+    output fabric_mrepair_fuse_bist1fail_o1;
+    output fabric_mrepair_fuse_bist1fail_o2;
+    output fabric_mrepair_fuse_bist1fail_o3;
+    output fabric_mrepair_fuse_bist1fail_o4;
+    output fabric_mrepair_fuse_bist1fail_o5;
+    output fabric_mrepair_fuse_bist1fail_o6;
+    output fabric_mrepair_fuse_bist1fail_o7;
+    output fabric_mrepair_fuse_bist1fail_o8;
+    output fabric_mrepair_fuse_bist2fail_o1;
+    output fabric_mrepair_fuse_bist2fail_o2;
+    output fabric_mrepair_fuse_bist2fail_o3;
+    output fabric_mrepair_fuse_bist2fail_o4;
+    output fabric_mrepair_fuse_bist2fail_o5;
+    output fabric_mrepair_fuse_bist2fail_o6;
+    output fabric_mrepair_fuse_bist2fail_o7;
+    input fabric_mrepair_fuse_bistmode_i;
+    output fabric_mrepair_fuse_calibrated_o;
+    output fabric_mrepair_fuse_ded_o;
+    input fabric_mrepair_fuse_din_i1;
+    input fabric_mrepair_fuse_din_i10;
+    input fabric_mrepair_fuse_din_i11;
+    input fabric_mrepair_fuse_din_i12;
+    input fabric_mrepair_fuse_din_i13;
+    input fabric_mrepair_fuse_din_i14;
+    input fabric_mrepair_fuse_din_i15;
+    input fabric_mrepair_fuse_din_i16;
+    input fabric_mrepair_fuse_din_i17;
+    input fabric_mrepair_fuse_din_i18;
+    input fabric_mrepair_fuse_din_i19;
+    input fabric_mrepair_fuse_din_i2;
+    input fabric_mrepair_fuse_din_i20;
+    input fabric_mrepair_fuse_din_i21;
+    input fabric_mrepair_fuse_din_i22;
+    input fabric_mrepair_fuse_din_i23;
+    input fabric_mrepair_fuse_din_i24;
+    input fabric_mrepair_fuse_din_i25;
+    input fabric_mrepair_fuse_din_i26;
+    input fabric_mrepair_fuse_din_i27;
+    input fabric_mrepair_fuse_din_i28;
+    input fabric_mrepair_fuse_din_i29;
+    input fabric_mrepair_fuse_din_i3;
+    input fabric_mrepair_fuse_din_i30;
+    input fabric_mrepair_fuse_din_i31;
+    input fabric_mrepair_fuse_din_i32;
+    input fabric_mrepair_fuse_din_i33;
+    input fabric_mrepair_fuse_din_i34;
+    input fabric_mrepair_fuse_din_i35;
+    input fabric_mrepair_fuse_din_i36;
+    input fabric_mrepair_fuse_din_i37;
+    input fabric_mrepair_fuse_din_i38;
+    input fabric_mrepair_fuse_din_i39;
+    input fabric_mrepair_fuse_din_i4;
+    input fabric_mrepair_fuse_din_i5;
+    input fabric_mrepair_fuse_din_i6;
+    input fabric_mrepair_fuse_din_i7;
+    input fabric_mrepair_fuse_din_i8;
+    input fabric_mrepair_fuse_din_i9;
+    input fabric_mrepair_fuse_disturbchecked_i;
+    output fabric_mrepair_fuse_disturbed_o;
+    output fabric_mrepair_fuse_dout_o1;
+    output fabric_mrepair_fuse_dout_o10;
+    output fabric_mrepair_fuse_dout_o11;
+    output fabric_mrepair_fuse_dout_o12;
+    output fabric_mrepair_fuse_dout_o13;
+    output fabric_mrepair_fuse_dout_o14;
+    output fabric_mrepair_fuse_dout_o15;
+    output fabric_mrepair_fuse_dout_o16;
+    output fabric_mrepair_fuse_dout_o17;
+    output fabric_mrepair_fuse_dout_o18;
+    output fabric_mrepair_fuse_dout_o19;
+    output fabric_mrepair_fuse_dout_o2;
+    output fabric_mrepair_fuse_dout_o20;
+    output fabric_mrepair_fuse_dout_o21;
+    output fabric_mrepair_fuse_dout_o22;
+    output fabric_mrepair_fuse_dout_o23;
+    output fabric_mrepair_fuse_dout_o24;
+    output fabric_mrepair_fuse_dout_o25;
+    output fabric_mrepair_fuse_dout_o26;
+    output fabric_mrepair_fuse_dout_o27;
+    output fabric_mrepair_fuse_dout_o28;
+    output fabric_mrepair_fuse_dout_o29;
+    output fabric_mrepair_fuse_dout_o3;
+    output fabric_mrepair_fuse_dout_o30;
+    output fabric_mrepair_fuse_dout_o31;
+    output fabric_mrepair_fuse_dout_o32;
+    output fabric_mrepair_fuse_dout_o33;
+    output fabric_mrepair_fuse_dout_o34;
+    output fabric_mrepair_fuse_dout_o35;
+    output fabric_mrepair_fuse_dout_o36;
+    output fabric_mrepair_fuse_dout_o37;
+    output fabric_mrepair_fuse_dout_o38;
+    output fabric_mrepair_fuse_dout_o39;
+    output fabric_mrepair_fuse_dout_o4;
+    output fabric_mrepair_fuse_dout_o40;
+    output fabric_mrepair_fuse_dout_o41;
+    output fabric_mrepair_fuse_dout_o5;
+    output fabric_mrepair_fuse_dout_o6;
+    output fabric_mrepair_fuse_dout_o7;
+    output fabric_mrepair_fuse_dout_o8;
+    output fabric_mrepair_fuse_dout_o9;
+    input fabric_mrepair_fuse_eccbypass_i;
+    output fabric_mrepair_fuse_flagstate_o1;
+    output fabric_mrepair_fuse_flagstate_o2;
+    output fabric_mrepair_fuse_flagstate_o3;
+    output fabric_mrepair_fuse_flagstate_o4;
+    output fabric_mrepair_fuse_locked_o;
+    input fabric_mrepair_fuse_pdn_i;
+    output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o;
+    input fabric_mrepair_fuse_prgwidth_i1;
+    input fabric_mrepair_fuse_prgwidth_i2;
+    input fabric_mrepair_fuse_prgwidth_i3;
+    input fabric_mrepair_fuse_prog_i;
+    output fabric_mrepair_fuse_progfail_o;
+    output fabric_mrepair_fuse_pwok_o;
+    input fabric_mrepair_fuse_rbact1_i;
+    input fabric_mrepair_fuse_rbact2_i;
+    input fabric_mrepair_fuse_read_i;
+    output fabric_mrepair_fuse_ready_o;
+    input fabric_mrepair_fuse_redbypass_i;
+    output fabric_mrepair_fuse_sec_o;
+    output fabric_mrepair_fuse_startword_o1;
+    output fabric_mrepair_fuse_startword_o10;
+    output fabric_mrepair_fuse_startword_o11;
+    output fabric_mrepair_fuse_startword_o12;
+    output fabric_mrepair_fuse_startword_o13;
+    output fabric_mrepair_fuse_startword_o14;
+    output fabric_mrepair_fuse_startword_o15;
+    output fabric_mrepair_fuse_startword_o16;
+    output fabric_mrepair_fuse_startword_o2;
+    output fabric_mrepair_fuse_startword_o3;
+    output fabric_mrepair_fuse_startword_o4;
+    output fabric_mrepair_fuse_startword_o5;
+    output fabric_mrepair_fuse_startword_o6;
+    output fabric_mrepair_fuse_startword_o7;
+    output fabric_mrepair_fuse_startword_o8;
+    output fabric_mrepair_fuse_startword_o9;
+    input fabric_mrepair_fuse_suppadd_i;
+    input fabric_mrepair_fuse_tm_i;
+    input fabric_mrepair_fuse_tst_scanin_i1;
+    input fabric_mrepair_fuse_tst_scanin_i2;
+    input fabric_mrepair_fuse_tst_scanin_i3;
+    input fabric_mrepair_fuse_tst_scanin_i4;
+    input fabric_mrepair_fuse_tst_scanin_i5;
+    input fabric_mrepair_fuse_tstscanenable_i;
+    output fabric_mrepair_fuse_tstscanout_o1;
+    output fabric_mrepair_fuse_tstscanout_o2;
+    output fabric_mrepair_fuse_tstscanout_o3;
+    output fabric_mrepair_fuse_tstscanout_o4;
+    output fabric_mrepair_fuse_tstscanout_o5;
+    output fabric_mrepair_fuse_wlromout_o1;
+    output fabric_mrepair_fuse_wlromout_o10;
+    output fabric_mrepair_fuse_wlromout_o2;
+    output fabric_mrepair_fuse_wlromout_o3;
+    output fabric_mrepair_fuse_wlromout_o4;
+    output fabric_mrepair_fuse_wlromout_o5;
+    output fabric_mrepair_fuse_wlromout_o6;
+    output fabric_mrepair_fuse_wlromout_o7;
+    output fabric_mrepair_fuse_wlromout_o8;
+    output fabric_mrepair_fuse_wlromout_o9;
+    input fabric_mrepair_fuse_wordlock_i;
+    input fabric_mrepair_initn_i;
+    input fabric_mrepair_mode_i1;
+    input fabric_mrepair_mode_i2;
+    input fabric_mrepair_mode_i3;
+    input fabric_mrepair_mode_i4;
+    input fabric_mrepair_por_i;
+    input fabric_mrepair_rst_n_i;
+    input fabric_otp_apb_addr_i1;
+    input fabric_otp_apb_addr_i10;
+    input fabric_otp_apb_addr_i11;
+    input fabric_otp_apb_addr_i12;
+    input fabric_otp_apb_addr_i13;
+    input fabric_otp_apb_addr_i14;
+    input fabric_otp_apb_addr_i15;
+    input fabric_otp_apb_addr_i16;
+    input fabric_otp_apb_addr_i17;
+    input fabric_otp_apb_addr_i18;
+    input fabric_otp_apb_addr_i19;
+    input fabric_otp_apb_addr_i2;
+    input fabric_otp_apb_addr_i20;
+    input fabric_otp_apb_addr_i21;
+    input fabric_otp_apb_addr_i22;
+    input fabric_otp_apb_addr_i23;
+    input fabric_otp_apb_addr_i24;
+    input fabric_otp_apb_addr_i25;
+    input fabric_otp_apb_addr_i26;
+    input fabric_otp_apb_addr_i27;
+    input fabric_otp_apb_addr_i28;
+    input fabric_otp_apb_addr_i29;
+    input fabric_otp_apb_addr_i3;
+    input fabric_otp_apb_addr_i30;
+    input fabric_otp_apb_addr_i31;
+    input fabric_otp_apb_addr_i32;
+    input fabric_otp_apb_addr_i4;
+    input fabric_otp_apb_addr_i5;
+    input fabric_otp_apb_addr_i6;
+    input fabric_otp_apb_addr_i7;
+    input fabric_otp_apb_addr_i8;
+    input fabric_otp_apb_addr_i9;
+    input fabric_otp_apb_enable_i;
+    output fabric_otp_apb_rdata_o1;
+    output fabric_otp_apb_rdata_o10;
+    output fabric_otp_apb_rdata_o11;
+    output fabric_otp_apb_rdata_o12;
+    output fabric_otp_apb_rdata_o13;
+    output fabric_otp_apb_rdata_o14;
+    output fabric_otp_apb_rdata_o15;
+    output fabric_otp_apb_rdata_o16;
+    output fabric_otp_apb_rdata_o17;
+    output fabric_otp_apb_rdata_o18;
+    output fabric_otp_apb_rdata_o19;
+    output fabric_otp_apb_rdata_o2;
+    output fabric_otp_apb_rdata_o20;
+    output fabric_otp_apb_rdata_o21;
+    output fabric_otp_apb_rdata_o22;
+    output fabric_otp_apb_rdata_o23;
+    output fabric_otp_apb_rdata_o24;
+    output fabric_otp_apb_rdata_o25;
+    output fabric_otp_apb_rdata_o26;
+    output fabric_otp_apb_rdata_o27;
+    output fabric_otp_apb_rdata_o28;
+    output fabric_otp_apb_rdata_o29;
+    output fabric_otp_apb_rdata_o3;
+    output fabric_otp_apb_rdata_o30;
+    output fabric_otp_apb_rdata_o31;
+    output fabric_otp_apb_rdata_o32;
+    output fabric_otp_apb_rdata_o4;
+    output fabric_otp_apb_rdata_o5;
+    output fabric_otp_apb_rdata_o6;
+    output fabric_otp_apb_rdata_o7;
+    output fabric_otp_apb_rdata_o8;
+    output fabric_otp_apb_rdata_o9;
+    output fabric_otp_apb_ready_o;
+    input fabric_otp_apb_sel_i;
+    input fabric_otp_apb_wdata_i1;
+    input fabric_otp_apb_wdata_i10;
+    input fabric_otp_apb_wdata_i11;
+    input fabric_otp_apb_wdata_i12;
+    input fabric_otp_apb_wdata_i13;
+    input fabric_otp_apb_wdata_i14;
+    input fabric_otp_apb_wdata_i15;
+    input fabric_otp_apb_wdata_i16;
+    input fabric_otp_apb_wdata_i17;
+    input fabric_otp_apb_wdata_i18;
+    input fabric_otp_apb_wdata_i19;
+    input fabric_otp_apb_wdata_i2;
+    input fabric_otp_apb_wdata_i20;
+    input fabric_otp_apb_wdata_i21;
+    input fabric_otp_apb_wdata_i22;
+    input fabric_otp_apb_wdata_i23;
+    input fabric_otp_apb_wdata_i24;
+    input fabric_otp_apb_wdata_i25;
+    input fabric_otp_apb_wdata_i26;
+    input fabric_otp_apb_wdata_i27;
+    input fabric_otp_apb_wdata_i28;
+    input fabric_otp_apb_wdata_i29;
+    input fabric_otp_apb_wdata_i3;
+    input fabric_otp_apb_wdata_i30;
+    input fabric_otp_apb_wdata_i31;
+    input fabric_otp_apb_wdata_i32;
+    input fabric_otp_apb_wdata_i4;
+    input fabric_otp_apb_wdata_i5;
+    input fabric_otp_apb_wdata_i6;
+    input fabric_otp_apb_wdata_i7;
+    input fabric_otp_apb_wdata_i8;
+    input fabric_otp_apb_wdata_i9;
+    input fabric_otp_apb_write_i;
+    input fabric_otp_cfg_clk_fab_en_i;
+    input fabric_otp_cfg_clk_otpm_disable_i;
+    input fabric_otp_cfg_fabric_apb_en_i;
+    input fabric_otp_cfg_loader_read_en_i;
+    input fabric_otp_cfg_loader_write_en_i;
+    input fabric_otp_rst_i;
+    output fabric_otp_security_ack_o;
+    output fabric_otp_security_bist_bad_o;
+    output fabric_otp_security_bist_end1_o;
+    output fabric_otp_security_bist_end2_o;
+    output fabric_otp_security_bist_fail1_o1;
+    output fabric_otp_security_bist_fail1_o2;
+    output fabric_otp_security_bist_fail1_o3;
+    output fabric_otp_security_bist_fail1_o4;
+    output fabric_otp_security_bist_fail1_o5;
+    output fabric_otp_security_bist_fail1_o6;
+    output fabric_otp_security_bist_fail1_o7;
+    output fabric_otp_security_bist_fail1_o8;
+    output fabric_otp_security_bist_fail2_o1;
+    output fabric_otp_security_bist_fail2_o2;
+    output fabric_otp_security_bist_fail2_o3;
+    output fabric_otp_security_bist_fail2_o4;
+    output fabric_otp_security_bist_fail2_o5;
+    output fabric_otp_security_bist_fail2_o6;
+    output fabric_otp_security_bist_fail2_o7;
+    input fabric_otp_security_bistmode_i;
+    input fabric_otp_security_force_pdn1_i;
+    input fabric_otp_security_rbact1_i;
+    input fabric_otp_security_rbact2_i;
+    input fabric_otp_security_scanenable_i;
+    input fabric_otp_security_scanin_i1;
+    input fabric_otp_security_scanin_i2;
+    input fabric_otp_security_scanin_i3;
+    input fabric_otp_security_scanin_i4;
+    input fabric_otp_security_scanin_i5;
+    output fabric_otp_security_scanout_o1;
+    output fabric_otp_security_scanout_o2;
+    output fabric_otp_security_scanout_o3;
+    output fabric_otp_security_scanout_o4;
+    output fabric_otp_security_scanout_o5;
+    input fabric_otp_security_testmode_i;
+    output fabric_otp_user_ack_o;
+    input fabric_otp_user_add_i1;
+    input fabric_otp_user_add_i2;
+    input fabric_otp_user_add_i3;
+    input fabric_otp_user_add_i4;
+    input fabric_otp_user_add_i5;
+    input fabric_otp_user_add_i6;
+    input fabric_otp_user_add_i7;
+    output fabric_otp_user_bbad_o;
+    output fabric_otp_user_bend1_o;
+    output fabric_otp_user_bend2_o;
+    output fabric_otp_user_bist1fail_o1;
+    output fabric_otp_user_bist1fail_o2;
+    output fabric_otp_user_bist1fail_o3;
+    output fabric_otp_user_bist1fail_o4;
+    output fabric_otp_user_bist1fail_o5;
+    output fabric_otp_user_bist1fail_o6;
+    output fabric_otp_user_bist1fail_o7;
+    output fabric_otp_user_bist1fail_o8;
+    output fabric_otp_user_bist2fail_o1;
+    output fabric_otp_user_bist2fail_o2;
+    output fabric_otp_user_bist2fail_o3;
+    output fabric_otp_user_bist2fail_o4;
+    output fabric_otp_user_bist2fail_o5;
+    output fabric_otp_user_bist2fail_o6;
+    output fabric_otp_user_bist2fail_o7;
+    input fabric_otp_user_bistmode_i;
+    output fabric_otp_user_calibrated_o;
+    input fabric_otp_user_clock_frequency_range_i;
+    output fabric_otp_user_ded_o;
+    input fabric_otp_user_din_i1;
+    input fabric_otp_user_din_i10;
+    input fabric_otp_user_din_i11;
+    input fabric_otp_user_din_i12;
+    input fabric_otp_user_din_i13;
+    input fabric_otp_user_din_i14;
+    input fabric_otp_user_din_i15;
+    input fabric_otp_user_din_i16;
+    input fabric_otp_user_din_i17;
+    input fabric_otp_user_din_i18;
+    input fabric_otp_user_din_i19;
+    input fabric_otp_user_din_i2;
+    input fabric_otp_user_din_i20;
+    input fabric_otp_user_din_i21;
+    input fabric_otp_user_din_i22;
+    input fabric_otp_user_din_i23;
+    input fabric_otp_user_din_i24;
+    input fabric_otp_user_din_i25;
+    input fabric_otp_user_din_i26;
+    input fabric_otp_user_din_i27;
+    input fabric_otp_user_din_i28;
+    input fabric_otp_user_din_i29;
+    input fabric_otp_user_din_i3;
+    input fabric_otp_user_din_i30;
+    input fabric_otp_user_din_i31;
+    input fabric_otp_user_din_i32;
+    input fabric_otp_user_din_i33;
+    input fabric_otp_user_din_i34;
+    input fabric_otp_user_din_i35;
+    input fabric_otp_user_din_i36;
+    input fabric_otp_user_din_i37;
+    input fabric_otp_user_din_i38;
+    input fabric_otp_user_din_i39;
+    input fabric_otp_user_din_i4;
+    input fabric_otp_user_din_i5;
+    input fabric_otp_user_din_i6;
+    input fabric_otp_user_din_i7;
+    input fabric_otp_user_din_i8;
+    input fabric_otp_user_din_i9;
+    input fabric_otp_user_disturbcheck_i;
+    output fabric_otp_user_disturbed_o;
+    output fabric_otp_user_dout_o1;
+    output fabric_otp_user_dout_o10;
+    output fabric_otp_user_dout_o11;
+    output fabric_otp_user_dout_o12;
+    output fabric_otp_user_dout_o13;
+    output fabric_otp_user_dout_o14;
+    output fabric_otp_user_dout_o15;
+    output fabric_otp_user_dout_o16;
+    output fabric_otp_user_dout_o17;
+    output fabric_otp_user_dout_o18;
+    output fabric_otp_user_dout_o19;
+    output fabric_otp_user_dout_o2;
+    output fabric_otp_user_dout_o20;
+    output fabric_otp_user_dout_o21;
+    output fabric_otp_user_dout_o22;
+    output fabric_otp_user_dout_o23;
+    output fabric_otp_user_dout_o24;
+    output fabric_otp_user_dout_o25;
+    output fabric_otp_user_dout_o26;
+    output fabric_otp_user_dout_o27;
+    output fabric_otp_user_dout_o28;
+    output fabric_otp_user_dout_o29;
+    output fabric_otp_user_dout_o3;
+    output fabric_otp_user_dout_o30;
+    output fabric_otp_user_dout_o31;
+    output fabric_otp_user_dout_o32;
+    output fabric_otp_user_dout_o33;
+    output fabric_otp_user_dout_o34;
+    output fabric_otp_user_dout_o35;
+    output fabric_otp_user_dout_o36;
+    output fabric_otp_user_dout_o37;
+    output fabric_otp_user_dout_o38;
+    output fabric_otp_user_dout_o39;
+    output fabric_otp_user_dout_o4;
+    output fabric_otp_user_dout_o40;
+    output fabric_otp_user_dout_o41;
+    output fabric_otp_user_dout_o5;
+    output fabric_otp_user_dout_o6;
+    output fabric_otp_user_dout_o7;
+    output fabric_otp_user_dout_o8;
+    output fabric_otp_user_dout_o9;
+    input fabric_otp_user_eccbypass_i;
+    output fabric_otp_user_flagstate_o1;
+    output fabric_otp_user_flagstate_o2;
+    output fabric_otp_user_flagstate_o3;
+    output fabric_otp_user_flagstate_o4;
+    output fabric_otp_user_locked_o;
+    input fabric_otp_user_pdn_i;
+    input fabric_otp_user_prgwidth_i1;
+    input fabric_otp_user_prgwidth_i2;
+    input fabric_otp_user_prgwidth_i3;
+    input fabric_otp_user_prog_i;
+    output fabric_otp_user_progfail_o;
+    output fabric_otp_user_pwok_o;
+    input fabric_otp_user_rbact1_i;
+    input fabric_otp_user_rbact2_i;
+    input fabric_otp_user_read_i;
+    input fabric_otp_user_redbypass_i;
+    output fabric_otp_user_sec_o;
+    output fabric_otp_user_startword_o1;
+    output fabric_otp_user_startword_o10;
+    output fabric_otp_user_startword_o11;
+    output fabric_otp_user_startword_o12;
+    output fabric_otp_user_startword_o13;
+    output fabric_otp_user_startword_o14;
+    output fabric_otp_user_startword_o15;
+    output fabric_otp_user_startword_o16;
+    output fabric_otp_user_startword_o2;
+    output fabric_otp_user_startword_o3;
+    output fabric_otp_user_startword_o4;
+    output fabric_otp_user_startword_o5;
+    output fabric_otp_user_startword_o6;
+    output fabric_otp_user_startword_o7;
+    output fabric_otp_user_startword_o8;
+    output fabric_otp_user_startword_o9;
+    input fabric_otp_user_suppadd_i;
+    input fabric_otp_user_tm_i;
+    input fabric_otp_user_tst_scanenable_i;
+    input fabric_otp_user_tst_scanin_i1;
+    input fabric_otp_user_tst_scanin_i2;
+    input fabric_otp_user_tst_scanin_i3;
+    input fabric_otp_user_tst_scanin_i4;
+    input fabric_otp_user_tst_scanin_i5;
+    output fabric_otp_user_tst_scanout_o1;
+    output fabric_otp_user_tst_scanout_o2;
+    output fabric_otp_user_tst_scanout_o3;
+    output fabric_otp_user_tst_scanout_o4;
+    output fabric_otp_user_tst_scanout_o5;
+    output fabric_otp_user_wlromout_o1;
+    output fabric_otp_user_wlromout_o10;
+    output fabric_otp_user_wlromout_o2;
+    output fabric_otp_user_wlromout_o3;
+    output fabric_otp_user_wlromout_o4;
+    output fabric_otp_user_wlromout_o5;
+    output fabric_otp_user_wlromout_o6;
+    output fabric_otp_user_wlromout_o7;
+    output fabric_otp_user_wlromout_o8;
+    output fabric_otp_user_wlromout_o9;
+    input fabric_otp_user_wordlock_i;
+    input fabric_parusr_cs_i;
+    input fabric_parusr_data_i1;
+    input fabric_parusr_data_i10;
+    input fabric_parusr_data_i11;
+    input fabric_parusr_data_i12;
+    input fabric_parusr_data_i13;
+    input fabric_parusr_data_i14;
+    input fabric_parusr_data_i15;
+    input fabric_parusr_data_i16;
+    input fabric_parusr_data_i2;
+    input fabric_parusr_data_i3;
+    input fabric_parusr_data_i4;
+    input fabric_parusr_data_i5;
+    input fabric_parusr_data_i6;
+    input fabric_parusr_data_i7;
+    input fabric_parusr_data_i8;
+    input fabric_parusr_data_i9;
+    output fabric_parusr_data_o1;
+    output fabric_parusr_data_o10;
+    output fabric_parusr_data_o11;
+    output fabric_parusr_data_o12;
+    output fabric_parusr_data_o13;
+    output fabric_parusr_data_o14;
+    output fabric_parusr_data_o15;
+    output fabric_parusr_data_o16;
+    output fabric_parusr_data_o2;
+    output fabric_parusr_data_o3;
+    output fabric_parusr_data_o4;
+    output fabric_parusr_data_o5;
+    output fabric_parusr_data_o6;
+    output fabric_parusr_data_o7;
+    output fabric_parusr_data_o8;
+    output fabric_parusr_data_o9;
+    output fabric_parusr_data_val_o;
+    input fabric_parusr_enable_i;
+    input fabric_parusr_type_i1;
+    input fabric_parusr_type_i2;
+    input fabric_pd_active_i1;
+    input fabric_pd_active_i10;
+    input fabric_pd_active_i11;
+    input fabric_pd_active_i12;
+    input fabric_pd_active_i13;
+    input fabric_pd_active_i14;
+    input fabric_pd_active_i15;
+    input fabric_pd_active_i16;
+    input fabric_pd_active_i17;
+    input fabric_pd_active_i18;
+    input fabric_pd_active_i19;
+    input fabric_pd_active_i2;
+    input fabric_pd_active_i20;
+    input fabric_pd_active_i21;
+    input fabric_pd_active_i22;
+    input fabric_pd_active_i23;
+    input fabric_pd_active_i24;
+    input fabric_pd_active_i3;
+    input fabric_pd_active_i4;
+    input fabric_pd_active_i5;
+    input fabric_pd_active_i6;
+    input fabric_pd_active_i7;
+    input fabric_pd_active_i8;
+    input fabric_pd_active_i9;
+    output fabric_pd_ready_o1;
+    output fabric_pd_ready_o10;
+    output fabric_pd_ready_o11;
+    output fabric_pd_ready_o12;
+    output fabric_pd_ready_o13;
+    output fabric_pd_ready_o14;
+    output fabric_pd_ready_o15;
+    output fabric_pd_ready_o16;
+    output fabric_pd_ready_o17;
+    output fabric_pd_ready_o18;
+    output fabric_pd_ready_o19;
+    output fabric_pd_ready_o2;
+    output fabric_pd_ready_o20;
+    output fabric_pd_ready_o21;
+    output fabric_pd_ready_o22;
+    output fabric_pd_ready_o23;
+    output fabric_pd_ready_o24;
+    output fabric_pd_ready_o3;
+    output fabric_pd_ready_o4;
+    output fabric_pd_ready_o5;
+    output fabric_pd_ready_o6;
+    output fabric_pd_ready_o7;
+    output fabric_pd_ready_o8;
+    output fabric_pd_ready_o9;
+    input fabric_shift_en_i1;
+    input fabric_shift_en_i10;
+    input fabric_shift_en_i11;
+    input fabric_shift_en_i12;
+    input fabric_shift_en_i13;
+    input fabric_shift_en_i14;
+    input fabric_shift_en_i15;
+    input fabric_shift_en_i16;
+    input fabric_shift_en_i17;
+    input fabric_shift_en_i18;
+    input fabric_shift_en_i19;
+    input fabric_shift_en_i2;
+    input fabric_shift_en_i20;
+    input fabric_shift_en_i21;
+    input fabric_shift_en_i22;
+    input fabric_shift_en_i23;
+    input fabric_shift_en_i24;
+    input fabric_shift_en_i3;
+    input fabric_shift_en_i4;
+    input fabric_shift_en_i5;
+    input fabric_shift_en_i6;
+    input fabric_shift_en_i7;
+    input fabric_shift_en_i8;
+    input fabric_shift_en_i9;
+    output fabric_shift_en_to_bist_o1;
+    output fabric_shift_en_to_bist_o10;
+    output fabric_shift_en_to_bist_o11;
+    output fabric_shift_en_to_bist_o12;
+    output fabric_shift_en_to_bist_o13;
+    output fabric_shift_en_to_bist_o14;
+    output fabric_shift_en_to_bist_o15;
+    output fabric_shift_en_to_bist_o16;
+    output fabric_shift_en_to_bist_o17;
+    output fabric_shift_en_to_bist_o18;
+    output fabric_shift_en_to_bist_o19;
+    output fabric_shift_en_to_bist_o2;
+    output fabric_shift_en_to_bist_o20;
+    output fabric_shift_en_to_bist_o21;
+    output fabric_shift_en_to_bist_o22;
+    output fabric_shift_en_to_bist_o23;
+    output fabric_shift_en_to_bist_o24;
+    output fabric_shift_en_to_bist_o3;
+    output fabric_shift_en_to_bist_o4;
+    output fabric_shift_en_to_bist_o5;
+    output fabric_shift_en_to_bist_o6;
+    output fabric_shift_en_to_bist_o7;
+    output fabric_shift_en_to_bist_o8;
+    output fabric_shift_en_to_bist_o9;
+    input fabric_sif_load_en_i1;
+    input fabric_sif_load_en_i10;
+    input fabric_sif_load_en_i11;
+    input fabric_sif_load_en_i12;
+    input fabric_sif_load_en_i13;
+    input fabric_sif_load_en_i14;
+    input fabric_sif_load_en_i15;
+    input fabric_sif_load_en_i16;
+    input fabric_sif_load_en_i17;
+    input fabric_sif_load_en_i18;
+    input fabric_sif_load_en_i19;
+    input fabric_sif_load_en_i2;
+    input fabric_sif_load_en_i20;
+    input fabric_sif_load_en_i21;
+    input fabric_sif_load_en_i22;
+    input fabric_sif_load_en_i23;
+    input fabric_sif_load_en_i24;
+    input fabric_sif_load_en_i3;
+    input fabric_sif_load_en_i4;
+    input fabric_sif_load_en_i5;
+    input fabric_sif_load_en_i6;
+    input fabric_sif_load_en_i7;
+    input fabric_sif_load_en_i8;
+    input fabric_sif_load_en_i9;
+    output fabric_sif_load_en_to_bist_o1;
+    output fabric_sif_load_en_to_bist_o10;
+    output fabric_sif_load_en_to_bist_o11;
+    output fabric_sif_load_en_to_bist_o12;
+    output fabric_sif_load_en_to_bist_o13;
+    output fabric_sif_load_en_to_bist_o14;
+    output fabric_sif_load_en_to_bist_o15;
+    output fabric_sif_load_en_to_bist_o16;
+    output fabric_sif_load_en_to_bist_o17;
+    output fabric_sif_load_en_to_bist_o18;
+    output fabric_sif_load_en_to_bist_o19;
+    output fabric_sif_load_en_to_bist_o2;
+    output fabric_sif_load_en_to_bist_o20;
+    output fabric_sif_load_en_to_bist_o21;
+    output fabric_sif_load_en_to_bist_o22;
+    output fabric_sif_load_en_to_bist_o23;
+    output fabric_sif_load_en_to_bist_o24;
+    output fabric_sif_load_en_to_bist_o3;
+    output fabric_sif_load_en_to_bist_o4;
+    output fabric_sif_load_en_to_bist_o5;
+    output fabric_sif_load_en_to_bist_o6;
+    output fabric_sif_load_en_to_bist_o7;
+    output fabric_sif_load_en_to_bist_o8;
+    output fabric_sif_load_en_to_bist_o9;
+    input fabric_sif_reg_en_i1;
+    input fabric_sif_reg_en_i10;
+    input fabric_sif_reg_en_i100;
+    input fabric_sif_reg_en_i101;
+    input fabric_sif_reg_en_i102;
+    input fabric_sif_reg_en_i103;
+    input fabric_sif_reg_en_i104;
+    input fabric_sif_reg_en_i105;
+    input fabric_sif_reg_en_i106;
+    input fabric_sif_reg_en_i107;
+    input fabric_sif_reg_en_i108;
+    input fabric_sif_reg_en_i109;
+    input fabric_sif_reg_en_i11;
+    input fabric_sif_reg_en_i110;
+    input fabric_sif_reg_en_i111;
+    input fabric_sif_reg_en_i112;
+    input fabric_sif_reg_en_i113;
+    input fabric_sif_reg_en_i114;
+    input fabric_sif_reg_en_i115;
+    input fabric_sif_reg_en_i116;
+    input fabric_sif_reg_en_i117;
+    input fabric_sif_reg_en_i118;
+    input fabric_sif_reg_en_i119;
+    input fabric_sif_reg_en_i12;
+    input fabric_sif_reg_en_i120;
+    input fabric_sif_reg_en_i13;
+    input fabric_sif_reg_en_i14;
+    input fabric_sif_reg_en_i15;
+    input fabric_sif_reg_en_i16;
+    input fabric_sif_reg_en_i17;
+    input fabric_sif_reg_en_i18;
+    input fabric_sif_reg_en_i19;
+    input fabric_sif_reg_en_i2;
+    input fabric_sif_reg_en_i20;
+    input fabric_sif_reg_en_i21;
+    input fabric_sif_reg_en_i22;
+    input fabric_sif_reg_en_i23;
+    input fabric_sif_reg_en_i24;
+    input fabric_sif_reg_en_i25;
+    input fabric_sif_reg_en_i26;
+    input fabric_sif_reg_en_i27;
+    input fabric_sif_reg_en_i28;
+    input fabric_sif_reg_en_i29;
+    input fabric_sif_reg_en_i3;
+    input fabric_sif_reg_en_i30;
+    input fabric_sif_reg_en_i31;
+    input fabric_sif_reg_en_i32;
+    input fabric_sif_reg_en_i33;
+    input fabric_sif_reg_en_i34;
+    input fabric_sif_reg_en_i35;
+    input fabric_sif_reg_en_i36;
+    input fabric_sif_reg_en_i37;
+    input fabric_sif_reg_en_i38;
+    input fabric_sif_reg_en_i39;
+    input fabric_sif_reg_en_i4;
+    input fabric_sif_reg_en_i40;
+    input fabric_sif_reg_en_i41;
+    input fabric_sif_reg_en_i42;
+    input fabric_sif_reg_en_i43;
+    input fabric_sif_reg_en_i44;
+    input fabric_sif_reg_en_i45;
+    input fabric_sif_reg_en_i46;
+    input fabric_sif_reg_en_i47;
+    input fabric_sif_reg_en_i48;
+    input fabric_sif_reg_en_i49;
+    input fabric_sif_reg_en_i5;
+    input fabric_sif_reg_en_i50;
+    input fabric_sif_reg_en_i51;
+    input fabric_sif_reg_en_i52;
+    input fabric_sif_reg_en_i53;
+    input fabric_sif_reg_en_i54;
+    input fabric_sif_reg_en_i55;
+    input fabric_sif_reg_en_i56;
+    input fabric_sif_reg_en_i57;
+    input fabric_sif_reg_en_i58;
+    input fabric_sif_reg_en_i59;
+    input fabric_sif_reg_en_i6;
+    input fabric_sif_reg_en_i60;
+    input fabric_sif_reg_en_i61;
+    input fabric_sif_reg_en_i62;
+    input fabric_sif_reg_en_i63;
+    input fabric_sif_reg_en_i64;
+    input fabric_sif_reg_en_i65;
+    input fabric_sif_reg_en_i66;
+    input fabric_sif_reg_en_i67;
+    input fabric_sif_reg_en_i68;
+    input fabric_sif_reg_en_i69;
+    input fabric_sif_reg_en_i7;
+    input fabric_sif_reg_en_i70;
+    input fabric_sif_reg_en_i71;
+    input fabric_sif_reg_en_i72;
+    input fabric_sif_reg_en_i73;
+    input fabric_sif_reg_en_i74;
+    input fabric_sif_reg_en_i75;
+    input fabric_sif_reg_en_i76;
+    input fabric_sif_reg_en_i77;
+    input fabric_sif_reg_en_i78;
+    input fabric_sif_reg_en_i79;
+    input fabric_sif_reg_en_i8;
+    input fabric_sif_reg_en_i80;
+    input fabric_sif_reg_en_i81;
+    input fabric_sif_reg_en_i82;
+    input fabric_sif_reg_en_i83;
+    input fabric_sif_reg_en_i84;
+    input fabric_sif_reg_en_i85;
+    input fabric_sif_reg_en_i86;
+    input fabric_sif_reg_en_i87;
+    input fabric_sif_reg_en_i88;
+    input fabric_sif_reg_en_i89;
+    input fabric_sif_reg_en_i9;
+    input fabric_sif_reg_en_i90;
+    input fabric_sif_reg_en_i91;
+    input fabric_sif_reg_en_i92;
+    input fabric_sif_reg_en_i93;
+    input fabric_sif_reg_en_i94;
+    input fabric_sif_reg_en_i95;
+    input fabric_sif_reg_en_i96;
+    input fabric_sif_reg_en_i97;
+    input fabric_sif_reg_en_i98;
+    input fabric_sif_reg_en_i99;
+    output fabric_sif_reg_en_to_bist_o1;
+    output fabric_sif_reg_en_to_bist_o10;
+    output fabric_sif_reg_en_to_bist_o100;
+    output fabric_sif_reg_en_to_bist_o101;
+    output fabric_sif_reg_en_to_bist_o102;
+    output fabric_sif_reg_en_to_bist_o103;
+    output fabric_sif_reg_en_to_bist_o104;
+    output fabric_sif_reg_en_to_bist_o105;
+    output fabric_sif_reg_en_to_bist_o106;
+    output fabric_sif_reg_en_to_bist_o107;
+    output fabric_sif_reg_en_to_bist_o108;
+    output fabric_sif_reg_en_to_bist_o109;
+    output fabric_sif_reg_en_to_bist_o11;
+    output fabric_sif_reg_en_to_bist_o110;
+    output fabric_sif_reg_en_to_bist_o111;
+    output fabric_sif_reg_en_to_bist_o112;
+    output fabric_sif_reg_en_to_bist_o113;
+    output fabric_sif_reg_en_to_bist_o114;
+    output fabric_sif_reg_en_to_bist_o115;
+    output fabric_sif_reg_en_to_bist_o116;
+    output fabric_sif_reg_en_to_bist_o117;
+    output fabric_sif_reg_en_to_bist_o118;
+    output fabric_sif_reg_en_to_bist_o119;
+    output fabric_sif_reg_en_to_bist_o12;
+    output fabric_sif_reg_en_to_bist_o120;
+    output fabric_sif_reg_en_to_bist_o13;
+    output fabric_sif_reg_en_to_bist_o14;
+    output fabric_sif_reg_en_to_bist_o15;
+    output fabric_sif_reg_en_to_bist_o16;
+    output fabric_sif_reg_en_to_bist_o17;
+    output fabric_sif_reg_en_to_bist_o18;
+    output fabric_sif_reg_en_to_bist_o19;
+    output fabric_sif_reg_en_to_bist_o2;
+    output fabric_sif_reg_en_to_bist_o20;
+    output fabric_sif_reg_en_to_bist_o21;
+    output fabric_sif_reg_en_to_bist_o22;
+    output fabric_sif_reg_en_to_bist_o23;
+    output fabric_sif_reg_en_to_bist_o24;
+    output fabric_sif_reg_en_to_bist_o25;
+    output fabric_sif_reg_en_to_bist_o26;
+    output fabric_sif_reg_en_to_bist_o27;
+    output fabric_sif_reg_en_to_bist_o28;
+    output fabric_sif_reg_en_to_bist_o29;
+    output fabric_sif_reg_en_to_bist_o3;
+    output fabric_sif_reg_en_to_bist_o30;
+    output fabric_sif_reg_en_to_bist_o31;
+    output fabric_sif_reg_en_to_bist_o32;
+    output fabric_sif_reg_en_to_bist_o33;
+    output fabric_sif_reg_en_to_bist_o34;
+    output fabric_sif_reg_en_to_bist_o35;
+    output fabric_sif_reg_en_to_bist_o36;
+    output fabric_sif_reg_en_to_bist_o37;
+    output fabric_sif_reg_en_to_bist_o38;
+    output fabric_sif_reg_en_to_bist_o39;
+    output fabric_sif_reg_en_to_bist_o4;
+    output fabric_sif_reg_en_to_bist_o40;
+    output fabric_sif_reg_en_to_bist_o41;
+    output fabric_sif_reg_en_to_bist_o42;
+    output fabric_sif_reg_en_to_bist_o43;
+    output fabric_sif_reg_en_to_bist_o44;
+    output fabric_sif_reg_en_to_bist_o45;
+    output fabric_sif_reg_en_to_bist_o46;
+    output fabric_sif_reg_en_to_bist_o47;
+    output fabric_sif_reg_en_to_bist_o48;
+    output fabric_sif_reg_en_to_bist_o49;
+    output fabric_sif_reg_en_to_bist_o5;
+    output fabric_sif_reg_en_to_bist_o50;
+    output fabric_sif_reg_en_to_bist_o51;
+    output fabric_sif_reg_en_to_bist_o52;
+    output fabric_sif_reg_en_to_bist_o53;
+    output fabric_sif_reg_en_to_bist_o54;
+    output fabric_sif_reg_en_to_bist_o55;
+    output fabric_sif_reg_en_to_bist_o56;
+    output fabric_sif_reg_en_to_bist_o57;
+    output fabric_sif_reg_en_to_bist_o58;
+    output fabric_sif_reg_en_to_bist_o59;
+    output fabric_sif_reg_en_to_bist_o6;
+    output fabric_sif_reg_en_to_bist_o60;
+    output fabric_sif_reg_en_to_bist_o61;
+    output fabric_sif_reg_en_to_bist_o62;
+    output fabric_sif_reg_en_to_bist_o63;
+    output fabric_sif_reg_en_to_bist_o64;
+    output fabric_sif_reg_en_to_bist_o65;
+    output fabric_sif_reg_en_to_bist_o66;
+    output fabric_sif_reg_en_to_bist_o67;
+    output fabric_sif_reg_en_to_bist_o68;
+    output fabric_sif_reg_en_to_bist_o69;
+    output fabric_sif_reg_en_to_bist_o7;
+    output fabric_sif_reg_en_to_bist_o70;
+    output fabric_sif_reg_en_to_bist_o71;
+    output fabric_sif_reg_en_to_bist_o72;
+    output fabric_sif_reg_en_to_bist_o73;
+    output fabric_sif_reg_en_to_bist_o74;
+    output fabric_sif_reg_en_to_bist_o75;
+    output fabric_sif_reg_en_to_bist_o76;
+    output fabric_sif_reg_en_to_bist_o77;
+    output fabric_sif_reg_en_to_bist_o78;
+    output fabric_sif_reg_en_to_bist_o79;
+    output fabric_sif_reg_en_to_bist_o8;
+    output fabric_sif_reg_en_to_bist_o80;
+    output fabric_sif_reg_en_to_bist_o81;
+    output fabric_sif_reg_en_to_bist_o82;
+    output fabric_sif_reg_en_to_bist_o83;
+    output fabric_sif_reg_en_to_bist_o84;
+    output fabric_sif_reg_en_to_bist_o85;
+    output fabric_sif_reg_en_to_bist_o86;
+    output fabric_sif_reg_en_to_bist_o87;
+    output fabric_sif_reg_en_to_bist_o88;
+    output fabric_sif_reg_en_to_bist_o89;
+    output fabric_sif_reg_en_to_bist_o9;
+    output fabric_sif_reg_en_to_bist_o90;
+    output fabric_sif_reg_en_to_bist_o91;
+    output fabric_sif_reg_en_to_bist_o92;
+    output fabric_sif_reg_en_to_bist_o93;
+    output fabric_sif_reg_en_to_bist_o94;
+    output fabric_sif_reg_en_to_bist_o95;
+    output fabric_sif_reg_en_to_bist_o96;
+    output fabric_sif_reg_en_to_bist_o97;
+    output fabric_sif_reg_en_to_bist_o98;
+    output fabric_sif_reg_en_to_bist_o99;
+    input fabric_sif_update_en_i1;
+    input fabric_sif_update_en_i10;
+    input fabric_sif_update_en_i11;
+    input fabric_sif_update_en_i12;
+    input fabric_sif_update_en_i13;
+    input fabric_sif_update_en_i14;
+    input fabric_sif_update_en_i15;
+    input fabric_sif_update_en_i16;
+    input fabric_sif_update_en_i17;
+    input fabric_sif_update_en_i18;
+    input fabric_sif_update_en_i19;
+    input fabric_sif_update_en_i2;
+    input fabric_sif_update_en_i20;
+    input fabric_sif_update_en_i21;
+    input fabric_sif_update_en_i22;
+    input fabric_sif_update_en_i23;
+    input fabric_sif_update_en_i24;
+    input fabric_sif_update_en_i3;
+    input fabric_sif_update_en_i4;
+    input fabric_sif_update_en_i5;
+    input fabric_sif_update_en_i6;
+    input fabric_sif_update_en_i7;
+    input fabric_sif_update_en_i8;
+    input fabric_sif_update_en_i9;
+    output fabric_sif_update_en_to_bist_o1;
+    output fabric_sif_update_en_to_bist_o10;
+    output fabric_sif_update_en_to_bist_o11;
+    output fabric_sif_update_en_to_bist_o12;
+    output fabric_sif_update_en_to_bist_o13;
+    output fabric_sif_update_en_to_bist_o14;
+    output fabric_sif_update_en_to_bist_o15;
+    output fabric_sif_update_en_to_bist_o16;
+    output fabric_sif_update_en_to_bist_o17;
+    output fabric_sif_update_en_to_bist_o18;
+    output fabric_sif_update_en_to_bist_o19;
+    output fabric_sif_update_en_to_bist_o2;
+    output fabric_sif_update_en_to_bist_o20;
+    output fabric_sif_update_en_to_bist_o21;
+    output fabric_sif_update_en_to_bist_o22;
+    output fabric_sif_update_en_to_bist_o23;
+    output fabric_sif_update_en_to_bist_o24;
+    output fabric_sif_update_en_to_bist_o3;
+    output fabric_sif_update_en_to_bist_o4;
+    output fabric_sif_update_en_to_bist_o5;
+    output fabric_sif_update_en_to_bist_o6;
+    output fabric_sif_update_en_to_bist_o7;
+    output fabric_sif_update_en_to_bist_o8;
+    output fabric_sif_update_en_to_bist_o9;
+    output fabric_status_cold_start_o;
+    output fabric_system_data_from_mem_bist_o1;
+    output fabric_system_data_from_mem_bist_o10;
+    output fabric_system_data_from_mem_bist_o11;
+    output fabric_system_data_from_mem_bist_o12;
+    output fabric_system_data_from_mem_bist_o13;
+    output fabric_system_data_from_mem_bist_o14;
+    output fabric_system_data_from_mem_bist_o15;
+    output fabric_system_data_from_mem_bist_o16;
+    output fabric_system_data_from_mem_bist_o17;
+    output fabric_system_data_from_mem_bist_o18;
+    output fabric_system_data_from_mem_bist_o19;
+    output fabric_system_data_from_mem_bist_o2;
+    output fabric_system_data_from_mem_bist_o20;
+    output fabric_system_data_from_mem_bist_o21;
+    output fabric_system_data_from_mem_bist_o22;
+    output fabric_system_data_from_mem_bist_o23;
+    output fabric_system_data_from_mem_bist_o24;
+    output fabric_system_data_from_mem_bist_o3;
+    output fabric_system_data_from_mem_bist_o4;
+    output fabric_system_data_from_mem_bist_o5;
+    output fabric_system_data_from_mem_bist_o6;
+    output fabric_system_data_from_mem_bist_o7;
+    output fabric_system_data_from_mem_bist_o8;
+    output fabric_system_data_from_mem_bist_o9;
+    input fabric_system_data_to_mem_bist_i1;
+    input fabric_system_data_to_mem_bist_i10;
+    input fabric_system_data_to_mem_bist_i11;
+    input fabric_system_data_to_mem_bist_i12;
+    input fabric_system_data_to_mem_bist_i13;
+    input fabric_system_data_to_mem_bist_i14;
+    input fabric_system_data_to_mem_bist_i15;
+    input fabric_system_data_to_mem_bist_i16;
+    input fabric_system_data_to_mem_bist_i17;
+    input fabric_system_data_to_mem_bist_i18;
+    input fabric_system_data_to_mem_bist_i19;
+    input fabric_system_data_to_mem_bist_i2;
+    input fabric_system_data_to_mem_bist_i20;
+    input fabric_system_data_to_mem_bist_i21;
+    input fabric_system_data_to_mem_bist_i22;
+    input fabric_system_data_to_mem_bist_i23;
+    input fabric_system_data_to_mem_bist_i24;
+    input fabric_system_data_to_mem_bist_i3;
+    input fabric_system_data_to_mem_bist_i4;
+    input fabric_system_data_to_mem_bist_i5;
+    input fabric_system_data_to_mem_bist_i6;
+    input fabric_system_data_to_mem_bist_i7;
+    input fabric_system_data_to_mem_bist_i8;
+    input fabric_system_data_to_mem_bist_i9;
+    output fabric_system_dataready_o;
+    input fabric_tst_atpg_mrepair_i;
+    input fabric_user_data_i1;
+    input fabric_user_data_i10;
+    input fabric_user_data_i11;
+    input fabric_user_data_i12;
+    input fabric_user_data_i13;
+    input fabric_user_data_i14;
+    input fabric_user_data_i15;
+    input fabric_user_data_i16;
+    input fabric_user_data_i17;
+    input fabric_user_data_i18;
+    input fabric_user_data_i19;
+    input fabric_user_data_i2;
+    input fabric_user_data_i20;
+    input fabric_user_data_i21;
+    input fabric_user_data_i22;
+    input fabric_user_data_i23;
+    input fabric_user_data_i24;
+    input fabric_user_data_i25;
+    input fabric_user_data_i26;
+    input fabric_user_data_i27;
+    input fabric_user_data_i28;
+    input fabric_user_data_i29;
+    input fabric_user_data_i3;
+    input fabric_user_data_i30;
+    input fabric_user_data_i31;
+    input fabric_user_data_i32;
+    input fabric_user_data_i4;
+    input fabric_user_data_i5;
+    input fabric_user_data_i6;
+    input fabric_user_data_i7;
+    input fabric_user_data_i8;
+    input fabric_user_data_i9;
+    output fabric_user_data_o1;
+    output fabric_user_data_o10;
+    output fabric_user_data_o11;
+    output fabric_user_data_o12;
+    output fabric_user_data_o13;
+    output fabric_user_data_o14;
+    output fabric_user_data_o15;
+    output fabric_user_data_o16;
+    output fabric_user_data_o17;
+    output fabric_user_data_o18;
+    output fabric_user_data_o19;
+    output fabric_user_data_o2;
+    output fabric_user_data_o20;
+    output fabric_user_data_o21;
+    output fabric_user_data_o22;
+    output fabric_user_data_o23;
+    output fabric_user_data_o24;
+    output fabric_user_data_o25;
+    output fabric_user_data_o26;
+    output fabric_user_data_o27;
+    output fabric_user_data_o28;
+    output fabric_user_data_o29;
+    output fabric_user_data_o3;
+    output fabric_user_data_o30;
+    output fabric_user_data_o31;
+    output fabric_user_data_o32;
+    output fabric_user_data_o4;
+    output fabric_user_data_o5;
+    output fabric_user_data_o6;
+    output fabric_user_data_o7;
+    output fabric_user_data_o8;
+    output fabric_user_data_o9;
+    output fabric_user_read_cycle_o;
+    output fabric_user_write_cycle_o;
+    parameter ahb_config = 0;
+    parameter bsm_config = 0;
+endmodule
+
+(* blackbox *)
+module NX_SERVICE_U_V1(fabric_otp_user_tst_scanenable_i, fabric_otp_cfg_loader_read_en_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_scanenable_i, fabric_otp_user_din_i1, fabric_otp_user_din_i2, fabric_otp_user_din_i3, fabric_otp_user_din_i4, fabric_otp_user_din_i5, fabric_otp_user_din_i6, fabric_otp_user_din_i7, fabric_otp_user_din_i8, fabric_otp_user_din_i9, fabric_otp_user_din_i10, fabric_otp_user_din_i11, fabric_otp_user_din_i12, fabric_otp_user_din_i13, fabric_otp_user_din_i14, fabric_otp_user_din_i15, fabric_otp_user_din_i16, fabric_otp_user_din_i17
+, fabric_otp_user_din_i18, fabric_otp_user_din_i19, fabric_otp_user_din_i20, fabric_otp_user_din_i21, fabric_otp_user_din_i22, fabric_otp_user_din_i23, fabric_otp_user_din_i24, fabric_otp_user_din_i25, fabric_otp_user_din_i26, fabric_otp_user_din_i27, fabric_otp_user_din_i28, fabric_otp_user_din_i29, fabric_otp_user_din_i30, fabric_otp_user_din_i31, fabric_otp_user_din_i32, fabric_otp_user_din_i33, fabric_otp_user_din_i34, fabric_otp_user_din_i35, fabric_otp_user_din_i36, fabric_otp_user_din_i37, fabric_otp_user_din_i38
+, fabric_otp_user_din_i39, fabric_mrepair_fuse_prgwidth_i1, fabric_mrepair_fuse_prgwidth_i2, fabric_mrepair_fuse_prgwidth_i3, fabric_otp_apb_wdata_i1, fabric_otp_apb_wdata_i2, fabric_otp_apb_wdata_i3, fabric_otp_apb_wdata_i4, fabric_otp_apb_wdata_i5, fabric_otp_apb_wdata_i6, fabric_otp_apb_wdata_i7, fabric_otp_apb_wdata_i8, fabric_otp_apb_wdata_i9, fabric_otp_apb_wdata_i10, fabric_otp_apb_wdata_i11, fabric_otp_apb_wdata_i12, fabric_otp_apb_wdata_i13, fabric_otp_apb_wdata_i14, fabric_otp_apb_wdata_i15, fabric_otp_apb_wdata_i16, fabric_otp_apb_wdata_i17
+, fabric_otp_apb_wdata_i18, fabric_otp_apb_wdata_i19, fabric_otp_apb_wdata_i20, fabric_otp_apb_wdata_i21, fabric_otp_apb_wdata_i22, fabric_otp_apb_wdata_i23, fabric_otp_apb_wdata_i24, fabric_otp_apb_wdata_i25, fabric_otp_apb_wdata_i26, fabric_otp_apb_wdata_i27, fabric_otp_apb_wdata_i28, fabric_otp_apb_wdata_i29, fabric_otp_apb_wdata_i30, fabric_otp_apb_wdata_i31, fabric_otp_apb_wdata_i32, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_user_disturbcheck_i, fabric_mrepair_fuse_read_i, fabric_otp_user_rbact2_i, fabric_mrepair_fuse_eccbypass_i, fabric_otp_user_bistmode_i
+, fabric_otp_user_add_i1, fabric_otp_user_add_i2, fabric_otp_user_add_i3, fabric_otp_user_add_i4, fabric_otp_user_add_i5, fabric_otp_user_add_i6, fabric_otp_user_add_i7, fabric_otp_user_tm_i, fabric_otp_rstn_i, fabric_mrepair_fuse_disturbchecked_i, fabric_otp_user_rbact1_i, fabric_mrepair_fuse_tst_scanin_i1, fabric_mrepair_fuse_tst_scanin_i2, fabric_mrepair_fuse_tst_scanin_i3, fabric_mrepair_fuse_tst_scanin_i4, fabric_mrepair_fuse_tst_scanin_i5, fabric_parusr_type_i1, fabric_parusr_type_i2, fabric_mrepair_fuse_redbypass_i, fabric_otp_user_eccbypass_i, fabric_otp_user_redbypass_i
+, fabric_mrepair_mode_i1, fabric_mrepair_mode_i2, fabric_mrepair_mode_i3, fabric_mrepair_mode_i4, fabric_parusr_cs_i, fabric_sif_reg_en_i1, fabric_sif_reg_en_i2, fabric_sif_reg_en_i3, fabric_sif_reg_en_i4, fabric_sif_reg_en_i5, fabric_sif_reg_en_i6, fabric_sif_reg_en_i7, fabric_sif_reg_en_i8, fabric_sif_reg_en_i9, fabric_sif_reg_en_i10, fabric_sif_reg_en_i11, fabric_sif_reg_en_i12, fabric_sif_reg_en_i13, fabric_sif_reg_en_i14, fabric_sif_reg_en_i15, fabric_sif_reg_en_i16
+, fabric_sif_reg_en_i17, fabric_sif_reg_en_i18, fabric_sif_reg_en_i19, fabric_sif_reg_en_i20, fabric_sif_reg_en_i21, fabric_sif_reg_en_i22, fabric_sif_reg_en_i23, fabric_sif_reg_en_i24, fabric_sif_reg_en_i25, fabric_sif_reg_en_i26, fabric_sif_reg_en_i27, fabric_sif_reg_en_i28, fabric_sif_reg_en_i29, fabric_sif_reg_en_i30, fabric_sif_reg_en_i31, fabric_sif_reg_en_i32, fabric_sif_reg_en_i33, fabric_sif_reg_en_i34, fabric_sif_reg_en_i35, fabric_sif_reg_en_i36, fabric_sif_reg_en_i37
+, fabric_sif_reg_en_i38, fabric_sif_reg_en_i39, fabric_sif_reg_en_i40, fabric_sif_reg_en_i41, fabric_sif_reg_en_i42, fabric_sif_reg_en_i43, fabric_sif_reg_en_i44, fabric_sif_reg_en_i45, fabric_sif_reg_en_i46, fabric_sif_reg_en_i47, fabric_sif_reg_en_i48, fabric_sif_reg_en_i49, fabric_sif_reg_en_i50, fabric_sif_reg_en_i51, fabric_sif_reg_en_i52, fabric_sif_reg_en_i53, fabric_sif_reg_en_i54, fabric_sif_reg_en_i55, fabric_sif_reg_en_i56, fabric_sif_reg_en_i57, fabric_sif_reg_en_i58
+, fabric_sif_reg_en_i59, fabric_sif_reg_en_i60, fabric_sif_reg_en_i61, fabric_sif_reg_en_i62, fabric_sif_reg_en_i63, fabric_sif_reg_en_i64, fabric_sif_reg_en_i65, fabric_sif_reg_en_i66, fabric_sif_reg_en_i67, fabric_sif_reg_en_i68, fabric_sif_reg_en_i69, fabric_sif_reg_en_i70, fabric_sif_reg_en_i71, fabric_sif_reg_en_i72, fabric_sif_reg_en_i73, fabric_sif_reg_en_i74, fabric_sif_reg_en_i75, fabric_sif_reg_en_i76, fabric_sif_reg_en_i77, fabric_sif_reg_en_i78, fabric_sif_reg_en_i79
+, fabric_sif_reg_en_i80, fabric_sif_reg_en_i81, fabric_sif_reg_en_i82, fabric_sif_reg_en_i83, fabric_sif_reg_en_i84, fabric_sif_reg_en_i85, fabric_sif_reg_en_i86, fabric_sif_reg_en_i87, fabric_sif_reg_en_i88, fabric_sif_reg_en_i89, fabric_sif_reg_en_i90, fabric_sif_reg_en_i91, fabric_sif_reg_en_i92, fabric_sif_reg_en_i93, fabric_sif_reg_en_i94, fabric_sif_reg_en_i95, fabric_sif_reg_en_i96, fabric_sif_reg_en_i97, fabric_sif_reg_en_i98, fabric_sif_reg_en_i99, fabric_sif_reg_en_i100
+, fabric_sif_reg_en_i101, fabric_sif_reg_en_i102, fabric_sif_reg_en_i103, fabric_sif_reg_en_i104, fabric_sif_reg_en_i105, fabric_sif_reg_en_i106, fabric_sif_reg_en_i107, fabric_sif_reg_en_i108, fabric_sif_reg_en_i109, fabric_sif_reg_en_i110, fabric_sif_reg_en_i111, fabric_sif_reg_en_i112, fabric_sif_reg_en_i113, fabric_sif_reg_en_i114, fabric_sif_reg_en_i115, fabric_sif_reg_en_i116, fabric_sif_reg_en_i117, fabric_sif_reg_en_i118, fabric_sif_reg_en_i119, fabric_sif_reg_en_i120, fabric_mrepair_fuse_rbact2_i
+, fabric_data_from_system_i, fabric_data_from_bist_i1, fabric_data_from_bist_i2, fabric_data_from_bist_i3, fabric_data_from_bist_i4, fabric_data_from_bist_i5, fabric_data_from_bist_i6, fabric_data_from_bist_i7, fabric_data_from_bist_i8, fabric_data_from_bist_i9, fabric_data_from_bist_i10, fabric_data_from_bist_i11, fabric_data_from_bist_i12, fabric_data_from_bist_i13, fabric_data_from_bist_i14, fabric_data_from_bist_i15, fabric_data_from_bist_i16, fabric_data_from_bist_i17, fabric_data_from_bist_i18, fabric_data_from_bist_i19, fabric_data_from_bist_i20
+, fabric_data_from_bist_i21, fabric_data_from_bist_i22, fabric_data_from_bist_i23, fabric_data_from_bist_i24, fabric_otp_apb_enable_i, fabric_mrepair_fuse_tm_i, fabric_otp_security_rbact2_i, fabric_otp_security_rbact1_i, fabric_shift_en_i1, fabric_shift_en_i2, fabric_shift_en_i3, fabric_shift_en_i4, fabric_shift_en_i5, fabric_shift_en_i6, fabric_shift_en_i7, fabric_shift_en_i8, fabric_shift_en_i9, fabric_shift_en_i10, fabric_shift_en_i11, fabric_shift_en_i12, fabric_shift_en_i13
+, fabric_shift_en_i14, fabric_shift_en_i15, fabric_shift_en_i16, fabric_shift_en_i17, fabric_shift_en_i18, fabric_shift_en_i19, fabric_shift_en_i20, fabric_shift_en_i21, fabric_shift_en_i22, fabric_shift_en_i23, fabric_shift_en_i24, fabric_otp_cfg_loader_write_en_i, fabric_user_data_i1, fabric_user_data_i2, fabric_user_data_i3, fabric_user_data_i4, fabric_user_data_i5, fabric_user_data_i6, fabric_user_data_i7, fabric_user_data_i8, fabric_user_data_i9
+, fabric_user_data_i10, fabric_user_data_i11, fabric_user_data_i12, fabric_user_data_i13, fabric_user_data_i14, fabric_user_data_i15, fabric_user_data_i16, fabric_user_data_i17, fabric_user_data_i18, fabric_user_data_i19, fabric_user_data_i20, fabric_user_data_i21, fabric_user_data_i22, fabric_user_data_i23, fabric_user_data_i24, fabric_user_data_i25, fabric_user_data_i26, fabric_user_data_i27, fabric_user_data_i28, fabric_user_data_i29, fabric_user_data_i30
+, fabric_user_data_i31, fabric_user_data_i32, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_prog_i, fabric_otp_user_wordlock_i, fabric_ahb_direct_data_i1, fabric_ahb_direct_data_i2, fabric_ahb_direct_data_i3, fabric_ahb_direct_data_i4, fabric_ahb_direct_data_i5, fabric_ahb_direct_data_i6, fabric_ahb_direct_data_i7, fabric_ahb_direct_data_i8, fabric_ahb_direct_data_i9, fabric_ahb_direct_data_i10, fabric_ahb_direct_data_i11, fabric_ahb_direct_data_i12, fabric_ahb_direct_data_i13, fabric_ahb_direct_data_i14, fabric_ahb_direct_data_i15, fabric_ahb_direct_data_i16
+, fabric_ahb_direct_data_i17, fabric_ahb_direct_data_i18, fabric_ahb_direct_data_i19, fabric_ahb_direct_data_i20, fabric_ahb_direct_data_i21, fabric_ahb_direct_data_i22, fabric_ahb_direct_data_i23, fabric_ahb_direct_data_i24, fabric_ahb_direct_data_i25, fabric_ahb_direct_data_i26, fabric_ahb_direct_data_i27, fabric_ahb_direct_data_i28, fabric_ahb_direct_data_i29, fabric_ahb_direct_data_i30, fabric_ahb_direct_data_i31, fabric_ahb_direct_data_i32, fabric_otp_user_prog_i, fabric_pd_active_i1, fabric_pd_active_i2, fabric_pd_active_i3, fabric_pd_active_i4
+, fabric_pd_active_i5, fabric_pd_active_i6, fabric_pd_active_i7, fabric_pd_active_i8, fabric_pd_active_i9, fabric_pd_active_i10, fabric_pd_active_i11, fabric_pd_active_i12, fabric_pd_active_i13, fabric_pd_active_i14, fabric_pd_active_i15, fabric_pd_active_i16, fabric_pd_active_i17, fabric_pd_active_i18, fabric_pd_active_i19, fabric_pd_active_i20, fabric_pd_active_i21, fabric_pd_active_i22, fabric_pd_active_i23, fabric_pd_active_i24, fabric_otp_user_suppadd_i
+, fabric_mrepair_fuse_pdn_i, fabric_otp_security_scanin_i1, fabric_otp_security_scanin_i2, fabric_otp_security_scanin_i3, fabric_otp_security_scanin_i4, fabric_otp_security_scanin_i5, fabric_end_encoding_i, fabric_jtag_tdo_usr2_i, fabric_mrepair_fuse_wordlock_i, fabric_otp_user_prgwidth_i1, fabric_otp_user_prgwidth_i2, fabric_otp_user_prgwidth_i3, fabric_otp_user_read_i, fabric_mrepair_fuse_add_i1, fabric_mrepair_fuse_add_i2, fabric_mrepair_fuse_add_i3, fabric_mrepair_fuse_add_i4, fabric_mrepair_fuse_add_i5, fabric_mrepair_fuse_add_i6, fabric_mrepair_fuse_add_i7, fabric_mrepair_fuse_bistmode_i
+, fabric_jtag_tdo_usr1_i, fabric_otp_cfg_clk_fab_en_i, fabric_io_in_i1, fabric_io_in_i2, fabric_io_in_i3, fabric_io_in_i4, fabric_io_in_i5, fabric_io_in_i6, fabric_io_in_i7, fabric_io_in_i8, fabric_io_in_i9, fabric_io_in_i10, fabric_io_in_i11, fabric_io_in_i12, fabric_io_in_i13, fabric_io_in_i14, fabric_io_in_i15, fabric_io_in_i16, fabric_io_in_i17, fabric_io_in_i18, fabric_io_in_i19
+, fabric_io_in_i20, fabric_io_in_i21, fabric_io_in_i22, fabric_io_in_i23, fabric_io_in_i24, fabric_io_in_i25, fabric_sif_load_en_i1, fabric_sif_load_en_i2, fabric_sif_load_en_i3, fabric_sif_load_en_i4, fabric_sif_load_en_i5, fabric_sif_load_en_i6, fabric_sif_load_en_i7, fabric_sif_load_en_i8, fabric_sif_load_en_i9, fabric_sif_load_en_i10, fabric_sif_load_en_i11, fabric_sif_load_en_i12, fabric_sif_load_en_i13, fabric_sif_load_en_i14, fabric_sif_load_en_i15
+, fabric_sif_load_en_i16, fabric_sif_load_en_i17, fabric_sif_load_en_i18, fabric_sif_load_en_i19, fabric_sif_load_en_i20, fabric_sif_load_en_i21, fabric_sif_load_en_i22, fabric_sif_load_en_i23, fabric_sif_load_en_i24, fabric_mrepair_fuse_din_i1, fabric_mrepair_fuse_din_i2, fabric_mrepair_fuse_din_i3, fabric_mrepair_fuse_din_i4, fabric_mrepair_fuse_din_i5, fabric_mrepair_fuse_din_i6, fabric_mrepair_fuse_din_i7, fabric_mrepair_fuse_din_i8, fabric_mrepair_fuse_din_i9, fabric_mrepair_fuse_din_i10, fabric_mrepair_fuse_din_i11, fabric_mrepair_fuse_din_i12
+, fabric_mrepair_fuse_din_i13, fabric_mrepair_fuse_din_i14, fabric_mrepair_fuse_din_i15, fabric_mrepair_fuse_din_i16, fabric_mrepair_fuse_din_i17, fabric_mrepair_fuse_din_i18, fabric_mrepair_fuse_din_i19, fabric_mrepair_fuse_din_i20, fabric_mrepair_fuse_din_i21, fabric_mrepair_fuse_din_i22, fabric_mrepair_fuse_din_i23, fabric_mrepair_fuse_din_i24, fabric_mrepair_fuse_din_i25, fabric_mrepair_fuse_din_i26, fabric_mrepair_fuse_din_i27, fabric_mrepair_fuse_din_i28, fabric_mrepair_fuse_din_i29, fabric_mrepair_fuse_din_i30, fabric_mrepair_fuse_din_i31, fabric_mrepair_fuse_din_i32, fabric_mrepair_fuse_din_i33
+, fabric_mrepair_fuse_din_i34, fabric_mrepair_fuse_din_i35, fabric_mrepair_fuse_din_i36, fabric_mrepair_fuse_din_i37, fabric_mrepair_fuse_din_i38, fabric_mrepair_fuse_din_i39, fabric_otp_apb_addr_i1, fabric_otp_apb_addr_i2, fabric_otp_apb_addr_i3, fabric_otp_apb_addr_i4, fabric_otp_apb_addr_i5, fabric_otp_apb_addr_i6, fabric_otp_apb_addr_i7, fabric_otp_apb_addr_i8, fabric_otp_apb_addr_i9, fabric_otp_apb_addr_i10, fabric_otp_apb_addr_i11, fabric_otp_apb_addr_i12, fabric_otp_apb_addr_i13, fabric_otp_apb_addr_i14, fabric_otp_apb_addr_i15
+, fabric_otp_apb_addr_i16, fabric_otp_apb_addr_i17, fabric_otp_apb_addr_i18, fabric_otp_apb_addr_i19, fabric_otp_apb_addr_i20, fabric_otp_apb_addr_i21, fabric_otp_apb_addr_i22, fabric_otp_apb_addr_i23, fabric_otp_apb_addr_i24, fabric_otp_apb_addr_i25, fabric_otp_apb_addr_i26, fabric_otp_apb_addr_i27, fabric_otp_apb_addr_i28, fabric_otp_apb_addr_i29, fabric_otp_apb_addr_i30, fabric_otp_apb_addr_i31, fabric_otp_apb_addr_i32, fabric_otp_apb_sel_i, fabric_mrepair_fuse_rbact1_i, fabric_mrepair_fuse_configreg_i1, fabric_mrepair_fuse_configreg_i2
+, fabric_mrepair_fuse_configreg_i3, fabric_mrepair_fuse_configreg_i4, fabric_mrepair_fuse_configreg_i5, fabric_mrepair_fuse_configreg_i6, fabric_mrepair_fuse_configreg_i7, fabric_mrepair_fuse_configreg_i8, fabric_mrepair_fuse_configreg_i9, fabric_mrepair_fuse_configreg_i10, fabric_mrepair_fuse_configreg_i11, fabric_mrepair_fuse_configreg_i12, fabric_mrepair_fuse_configreg_i13, fabric_mrepair_fuse_configreg_i14, fabric_mrepair_fuse_configreg_i15, fabric_mrepair_fuse_configreg_i16, fabric_mrepair_fuse_configreg_i17, fabric_mrepair_fuse_configreg_i18, fabric_mrepair_fuse_configreg_i19, fabric_mrepair_fuse_configreg_i20, fabric_mrepair_fuse_configreg_i21, fabric_mrepair_fuse_configreg_i22, fabric_mrepair_fuse_configreg_i23
+, fabric_mrepair_fuse_configreg_i24, fabric_mrepair_fuse_configreg_i25, fabric_mrepair_fuse_configreg_i26, fabric_mrepair_fuse_configreg_i27, fabric_mrepair_fuse_configreg_i28, fabric_mrepair_fuse_configreg_i29, fabric_mrepair_fuse_configreg_i30, fabric_mrepair_fuse_configreg_i31, fabric_mrepair_fuse_configreg_i32, fabric_otp_cfg_fabric_apb_en_i, fabric_data_shift_en_i, fabric_lowskew_i21, fabric_direct_data_i1, fabric_direct_data_i2, fabric_direct_data_i3, fabric_direct_data_i4, fabric_direct_data_i5, fabric_direct_data_i6, fabric_direct_data_i7, fabric_direct_data_i8, fabric_direct_data_i9
+, fabric_direct_data_i10, fabric_direct_data_i11, fabric_direct_data_i12, fabric_direct_data_i13, fabric_direct_data_i14, fabric_direct_data_i15, fabric_direct_data_i16, fabric_direct_data_i17, fabric_direct_data_i18, fabric_direct_data_i19, fabric_direct_data_i20, fabric_direct_data_i21, fabric_direct_data_i22, fabric_direct_data_i23, fabric_direct_data_i24, fabric_direct_data_i25, fabric_direct_data_i26, fabric_direct_data_i27, fabric_direct_data_i28, fabric_direct_data_i29, fabric_direct_data_i30
+, fabric_direct_data_i31, fabric_direct_data_i32, fabric_otp_user_pdn_i, fabric_io_oe_i1, fabric_io_oe_i2, fabric_io_oe_i3, fabric_io_oe_i4, fabric_io_oe_i5, fabric_io_oe_i6, fabric_io_oe_i7, fabric_io_oe_i8, fabric_io_oe_i9, fabric_io_oe_i10, fabric_io_oe_i11, fabric_io_oe_i12, fabric_io_oe_i13, fabric_io_oe_i14, fabric_io_oe_i15, fabric_io_oe_i16, fabric_io_oe_i17, fabric_io_oe_i18
+, fabric_io_oe_i19, fabric_io_oe_i20, fabric_io_oe_i21, fabric_io_oe_i22, fabric_io_oe_i23, fabric_io_oe_i24, fabric_io_oe_i25, fabric_parusr_data_i1, fabric_parusr_data_i2, fabric_parusr_data_i3, fabric_parusr_data_i4, fabric_parusr_data_i5, fabric_parusr_data_i6, fabric_parusr_data_i7, fabric_parusr_data_i8, fabric_parusr_data_i9, fabric_parusr_data_i10, fabric_parusr_data_i11, fabric_parusr_data_i12, fabric_parusr_data_i13, fabric_parusr_data_i14
+, fabric_parusr_data_i15, fabric_parusr_data_i16, fabric_otp_apb_write_i, fabric_otp_security_testmode_i, fabric_system_data_to_mem_bist_i1, fabric_system_data_to_mem_bist_i2, fabric_system_data_to_mem_bist_i3, fabric_system_data_to_mem_bist_i4, fabric_system_data_to_mem_bist_i5, fabric_system_data_to_mem_bist_i6, fabric_system_data_to_mem_bist_i7, fabric_system_data_to_mem_bist_i8, fabric_system_data_to_mem_bist_i9, fabric_system_data_to_mem_bist_i10, fabric_system_data_to_mem_bist_i11, fabric_system_data_to_mem_bist_i12, fabric_system_data_to_mem_bist_i13, fabric_system_data_to_mem_bist_i14, fabric_system_data_to_mem_bist_i15, fabric_system_data_to_mem_bist_i16, fabric_system_data_to_mem_bist_i17
+, fabric_system_data_to_mem_bist_i18, fabric_system_data_to_mem_bist_i19, fabric_system_data_to_mem_bist_i20, fabric_system_data_to_mem_bist_i21, fabric_system_data_to_mem_bist_i22, fabric_system_data_to_mem_bist_i23, fabric_system_data_to_mem_bist_i24, fabric_tst_atpg_mrepair_i, fabric_mrepair_fuse_tstscanenable_i, fabric_otp_security_bistmode_i, fabric_lowskew_i22, fabric_lowskew_i23, fabric_lowskew_i20, fabric_otp_user_configreg_i1, fabric_otp_user_configreg_i2, fabric_otp_user_configreg_i3, fabric_otp_user_configreg_i4, fabric_otp_user_configreg_i5, fabric_otp_user_configreg_i6, fabric_otp_user_configreg_i7, fabric_otp_user_configreg_i8
+, fabric_otp_user_configreg_i9, fabric_otp_user_configreg_i10, fabric_otp_user_configreg_i11, fabric_otp_user_configreg_i12, fabric_otp_user_configreg_i13, fabric_otp_user_configreg_i14, fabric_otp_user_configreg_i15, fabric_otp_user_configreg_i16, fabric_otp_user_configreg_i17, fabric_otp_user_configreg_i18, fabric_otp_user_configreg_i19, fabric_otp_user_configreg_i20, fabric_otp_user_configreg_i21, fabric_otp_user_configreg_i22, fabric_otp_user_configreg_i23, fabric_otp_user_configreg_i24, fabric_otp_user_configreg_i25, fabric_otp_user_configreg_i26, fabric_otp_user_configreg_i27, fabric_otp_user_configreg_i28, fabric_otp_user_configreg_i29
+, fabric_otp_user_configreg_i30, fabric_otp_user_configreg_i31, fabric_otp_user_configreg_i32, fabric_otp_user_tst_scanin_i1, fabric_otp_user_tst_scanin_i2, fabric_otp_user_tst_scanin_i3, fabric_otp_user_tst_scanin_i4, fabric_otp_user_tst_scanin_i5, fabric_sif_update_en_i1, fabric_sif_update_en_i2, fabric_sif_update_en_i3, fabric_sif_update_en_i4, fabric_sif_update_en_i5, fabric_sif_update_en_i6, fabric_sif_update_en_i7, fabric_sif_update_en_i8, fabric_sif_update_en_i9, fabric_sif_update_en_i10, fabric_sif_update_en_i11, fabric_sif_update_en_i12, fabric_sif_update_en_i13
+, fabric_sif_update_en_i14, fabric_sif_update_en_i15, fabric_sif_update_en_i16, fabric_sif_update_en_i17, fabric_sif_update_en_i18, fabric_sif_update_en_i19, fabric_sif_update_en_i20, fabric_sif_update_en_i21, fabric_sif_update_en_i22, fabric_sif_update_en_i23, fabric_sif_update_en_i24, fabric_mrepair_por_i, fabric_mrepair_rst_n_i, fabric_mrepair_initn_i, fabric_spare_i1, fabric_spare_i2, fabric_spare_i3, fabric_mrepair_fuse_bbad_o, fabric_jtag_trst_n_o, fabric_debug_direct_permission_write_o1, fabric_debug_direct_permission_write_o2
+, fabric_debug_direct_permission_write_o3, fabric_debug_direct_permission_write_o4, fabric_otp_security_bist_end1_o, fabric_parusr_data_val_o, fabric_debug_lock_reg_o, fabric_debug_security_error_read_o, fabric_mrepair_fuse_tstscanout_o1, fabric_mrepair_fuse_tstscanout_o2, fabric_mrepair_fuse_tstscanout_o3, fabric_mrepair_fuse_tstscanout_o4, fabric_mrepair_fuse_tstscanout_o5, fabric_otp_user_tst_scanout_o1, fabric_otp_user_tst_scanout_o2, fabric_otp_user_tst_scanout_o3, fabric_otp_user_tst_scanout_o4, fabric_otp_user_tst_scanout_o5, fabric_sif_update_en_to_bist_o1, fabric_sif_update_en_to_bist_o2, fabric_sif_update_en_to_bist_o3, fabric_sif_update_en_to_bist_o4, fabric_sif_update_en_to_bist_o5
+, fabric_sif_update_en_to_bist_o6, fabric_sif_update_en_to_bist_o7, fabric_sif_update_en_to_bist_o8, fabric_sif_update_en_to_bist_o9, fabric_sif_update_en_to_bist_o10, fabric_sif_update_en_to_bist_o11, fabric_sif_update_en_to_bist_o12, fabric_sif_update_en_to_bist_o13, fabric_sif_update_en_to_bist_o14, fabric_sif_update_en_to_bist_o15, fabric_sif_update_en_to_bist_o16, fabric_sif_update_en_to_bist_o17, fabric_sif_update_en_to_bist_o18, fabric_sif_update_en_to_bist_o19, fabric_sif_update_en_to_bist_o20, fabric_sif_update_en_to_bist_o21, fabric_sif_update_en_to_bist_o22, fabric_sif_update_en_to_bist_o23, fabric_sif_update_en_to_bist_o24, fabric_otp_user_locked_o, fabric_otp_security_bist_bad_o
+, fabric_debug_frame_permission_frame_o1, fabric_debug_frame_permission_frame_o2, fabric_debug_frame_permission_frame_o3, fabric_debug_frame_permission_frame_o4, fabric_otp_user_pwok_o, fabric_otp_user_bend2_o, fabric_mrepair_fuse_ded_o, fabric_debug_access_reg_data_ready_o, fabric_data_to_bist_o1, fabric_data_to_bist_o2, fabric_data_to_bist_o3, fabric_data_to_bist_o4, fabric_data_to_bist_o5, fabric_data_to_bist_o6, fabric_data_to_bist_o7, fabric_data_to_bist_o8, fabric_data_to_bist_o9, fabric_data_to_bist_o10, fabric_data_to_bist_o11, fabric_data_to_bist_o12, fabric_data_to_bist_o13
+, fabric_data_to_bist_o14, fabric_data_to_bist_o15, fabric_data_to_bist_o16, fabric_data_to_bist_o17, fabric_data_to_bist_o18, fabric_data_to_bist_o19, fabric_data_to_bist_o20, fabric_data_to_bist_o21, fabric_data_to_bist_o22, fabric_data_to_bist_o23, fabric_data_to_bist_o24, fabric_otp_user_startword_o1, fabric_otp_user_startword_o2, fabric_otp_user_startword_o3, fabric_otp_user_startword_o4, fabric_otp_user_startword_o5, fabric_otp_user_startword_o6, fabric_otp_user_startword_o7, fabric_otp_user_startword_o8, fabric_otp_user_startword_o9, fabric_otp_user_startword_o10
+, fabric_otp_user_startword_o11, fabric_otp_user_startword_o12, fabric_otp_user_startword_o13, fabric_otp_user_startword_o14, fabric_otp_user_startword_o15, fabric_otp_user_startword_o16, fabric_ahb_direct_data_o1, fabric_ahb_direct_data_o2, fabric_ahb_direct_data_o3, fabric_ahb_direct_data_o4, fabric_ahb_direct_data_o5, fabric_ahb_direct_data_o6, fabric_ahb_direct_data_o7, fabric_ahb_direct_data_o8, fabric_ahb_direct_data_o9, fabric_ahb_direct_data_o10, fabric_ahb_direct_data_o11, fabric_ahb_direct_data_o12, fabric_ahb_direct_data_o13, fabric_ahb_direct_data_o14, fabric_ahb_direct_data_o15
+, fabric_ahb_direct_data_o16, fabric_ahb_direct_data_o17, fabric_ahb_direct_data_o18, fabric_ahb_direct_data_o19, fabric_ahb_direct_data_o20, fabric_ahb_direct_data_o21, fabric_ahb_direct_data_o22, fabric_ahb_direct_data_o23, fabric_ahb_direct_data_o24, fabric_ahb_direct_data_o25, fabric_ahb_direct_data_o26, fabric_ahb_direct_data_o27, fabric_ahb_direct_data_o28, fabric_ahb_direct_data_o29, fabric_ahb_direct_data_o30, fabric_ahb_direct_data_o31, fabric_ahb_direct_data_o32, fabric_parusr_data_o1, fabric_parusr_data_o2, fabric_parusr_data_o3, fabric_parusr_data_o4
+, fabric_parusr_data_o5, fabric_parusr_data_o6, fabric_parusr_data_o7, fabric_parusr_data_o8, fabric_parusr_data_o9, fabric_parusr_data_o10, fabric_parusr_data_o11, fabric_parusr_data_o12, fabric_parusr_data_o13, fabric_parusr_data_o14, fabric_parusr_data_o15, fabric_parusr_data_o16, fabric_debug_otp_reload_err_o, fabric_cfg_fabric_user_unmask_o, fabric_decoder_init_ready_o, fabric_global_chip_status_o1, fabric_global_chip_status_o2, fabric_global_chip_status_o3, fabric_debug_security_boot_done_o, fabric_otp_user_calibrated_o, fabric_fuse_status_o1
+, fabric_fuse_status_o2, fabric_fuse_status_o3, fabric_otp_apb_rdata_o1, fabric_otp_apb_rdata_o2, fabric_otp_apb_rdata_o3, fabric_otp_apb_rdata_o4, fabric_otp_apb_rdata_o5, fabric_otp_apb_rdata_o6, fabric_otp_apb_rdata_o7, fabric_otp_apb_rdata_o8, fabric_otp_apb_rdata_o9, fabric_otp_apb_rdata_o10, fabric_otp_apb_rdata_o11, fabric_otp_apb_rdata_o12, fabric_otp_apb_rdata_o13, fabric_otp_apb_rdata_o14, fabric_otp_apb_rdata_o15, fabric_otp_apb_rdata_o16, fabric_otp_apb_rdata_o17, fabric_otp_apb_rdata_o18, fabric_otp_apb_rdata_o19
+, fabric_otp_apb_rdata_o20, fabric_otp_apb_rdata_o21, fabric_otp_apb_rdata_o22, fabric_otp_apb_rdata_o23, fabric_otp_apb_rdata_o24, fabric_otp_apb_rdata_o25, fabric_otp_apb_rdata_o26, fabric_otp_apb_rdata_o27, fabric_otp_apb_rdata_o28, fabric_otp_apb_rdata_o29, fabric_otp_apb_rdata_o30, fabric_otp_apb_rdata_o31, fabric_otp_apb_rdata_o32, fabric_jtag_tms_o, fabric_debug_bsec_core_status_o1, fabric_debug_bsec_core_status_o2, fabric_debug_bsec_core_status_o3, fabric_debug_bsec_core_status_o4, fabric_debug_bsec_core_status_o5, fabric_debug_bsec_core_status_o6, fabric_debug_bsec_core_status_o7
+, fabric_debug_bsec_core_status_o8, fabric_debug_bsec_core_status_o9, fabric_debug_bsec_core_status_o10, fabric_debug_bsec_core_status_o11, fabric_debug_bsec_core_status_o12, fabric_debug_bsec_core_status_o13, fabric_debug_bsec_core_status_o14, fabric_debug_bsec_core_status_o15, fabric_debug_bsec_core_status_o16, fabric_debug_bsec_core_status_o17, fabric_debug_bsec_core_status_o18, fabric_debug_bsec_core_status_o19, fabric_debug_bsec_core_status_o20, fabric_debug_bsec_core_status_o21, fabric_debug_bsec_core_status_o22, fabric_debug_bsec_core_status_o23, fabric_debug_bsec_core_status_o24, fabric_debug_bsec_core_status_o25, fabric_debug_bsec_core_status_o26, fabric_debug_bsec_core_status_o27, fabric_debug_bsec_core_status_o28
+, fabric_debug_bsec_core_status_o29, fabric_debug_bsec_core_status_o30, fabric_debug_bsec_core_status_o31, fabric_debug_bsec_core_status_o32, fabric_mrepair_fuse_bist1fail_o1, fabric_mrepair_fuse_bist1fail_o2, fabric_mrepair_fuse_bist1fail_o3, fabric_mrepair_fuse_bist1fail_o4, fabric_mrepair_fuse_bist1fail_o5, fabric_mrepair_fuse_bist1fail_o6, fabric_mrepair_fuse_bist1fail_o7, fabric_mrepair_fuse_bist1fail_o8, fabric_flag_ready_o, fabric_mrepair_fuse_dout_o1, fabric_mrepair_fuse_dout_o2, fabric_mrepair_fuse_dout_o3, fabric_mrepair_fuse_dout_o4, fabric_mrepair_fuse_dout_o5, fabric_mrepair_fuse_dout_o6, fabric_mrepair_fuse_dout_o7, fabric_mrepair_fuse_dout_o8
+, fabric_mrepair_fuse_dout_o9, fabric_mrepair_fuse_dout_o10, fabric_mrepair_fuse_dout_o11, fabric_mrepair_fuse_dout_o12, fabric_mrepair_fuse_dout_o13, fabric_mrepair_fuse_dout_o14, fabric_mrepair_fuse_dout_o15, fabric_mrepair_fuse_dout_o16, fabric_mrepair_fuse_dout_o17, fabric_mrepair_fuse_dout_o18, fabric_mrepair_fuse_dout_o19, fabric_mrepair_fuse_dout_o20, fabric_mrepair_fuse_dout_o21, fabric_mrepair_fuse_dout_o22, fabric_mrepair_fuse_dout_o23, fabric_mrepair_fuse_dout_o24, fabric_mrepair_fuse_dout_o25, fabric_mrepair_fuse_dout_o26, fabric_mrepair_fuse_dout_o27, fabric_mrepair_fuse_dout_o28, fabric_mrepair_fuse_dout_o29
+, fabric_mrepair_fuse_dout_o30, fabric_mrepair_fuse_dout_o31, fabric_mrepair_fuse_dout_o32, fabric_mrepair_fuse_dout_o33, fabric_mrepair_fuse_dout_o34, fabric_mrepair_fuse_dout_o35, fabric_mrepair_fuse_dout_o36, fabric_mrepair_fuse_dout_o37, fabric_mrepair_fuse_dout_o38, fabric_mrepair_fuse_dout_o39, fabric_mrepair_fuse_dout_o40, fabric_mrepair_fuse_dout_o41, fabric_debug_rst_soft_o, fabric_otp_user_ack_o, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_shift_en_to_bist_o1, fabric_shift_en_to_bist_o2, fabric_shift_en_to_bist_o3, fabric_shift_en_to_bist_o4, fabric_shift_en_to_bist_o5, fabric_shift_en_to_bist_o6
+, fabric_shift_en_to_bist_o7, fabric_shift_en_to_bist_o8, fabric_shift_en_to_bist_o9, fabric_shift_en_to_bist_o10, fabric_shift_en_to_bist_o11, fabric_shift_en_to_bist_o12, fabric_shift_en_to_bist_o13, fabric_shift_en_to_bist_o14, fabric_shift_en_to_bist_o15, fabric_shift_en_to_bist_o16, fabric_shift_en_to_bist_o17, fabric_shift_en_to_bist_o18, fabric_shift_en_to_bist_o19, fabric_shift_en_to_bist_o20, fabric_shift_en_to_bist_o21, fabric_shift_en_to_bist_o22, fabric_shift_en_to_bist_o23, fabric_shift_en_to_bist_o24, fabric_sif_reg_en_to_bist_o1, fabric_sif_reg_en_to_bist_o2, fabric_sif_reg_en_to_bist_o3
+, fabric_sif_reg_en_to_bist_o4, fabric_sif_reg_en_to_bist_o5, fabric_sif_reg_en_to_bist_o6, fabric_sif_reg_en_to_bist_o7, fabric_sif_reg_en_to_bist_o8, fabric_sif_reg_en_to_bist_o9, fabric_sif_reg_en_to_bist_o10, fabric_sif_reg_en_to_bist_o11, fabric_sif_reg_en_to_bist_o12, fabric_sif_reg_en_to_bist_o13, fabric_sif_reg_en_to_bist_o14, fabric_sif_reg_en_to_bist_o15, fabric_sif_reg_en_to_bist_o16, fabric_sif_reg_en_to_bist_o17, fabric_sif_reg_en_to_bist_o18, fabric_sif_reg_en_to_bist_o19, fabric_sif_reg_en_to_bist_o20, fabric_sif_reg_en_to_bist_o21, fabric_sif_reg_en_to_bist_o22, fabric_sif_reg_en_to_bist_o23, fabric_sif_reg_en_to_bist_o24
+, fabric_sif_reg_en_to_bist_o25, fabric_sif_reg_en_to_bist_o26, fabric_sif_reg_en_to_bist_o27, fabric_sif_reg_en_to_bist_o28, fabric_sif_reg_en_to_bist_o29, fabric_sif_reg_en_to_bist_o30, fabric_sif_reg_en_to_bist_o31, fabric_sif_reg_en_to_bist_o32, fabric_sif_reg_en_to_bist_o33, fabric_sif_reg_en_to_bist_o34, fabric_sif_reg_en_to_bist_o35, fabric_sif_reg_en_to_bist_o36, fabric_sif_reg_en_to_bist_o37, fabric_sif_reg_en_to_bist_o38, fabric_sif_reg_en_to_bist_o39, fabric_sif_reg_en_to_bist_o40, fabric_sif_reg_en_to_bist_o41, fabric_sif_reg_en_to_bist_o42, fabric_sif_reg_en_to_bist_o43, fabric_sif_reg_en_to_bist_o44, fabric_sif_reg_en_to_bist_o45
+, fabric_sif_reg_en_to_bist_o46, fabric_sif_reg_en_to_bist_o47, fabric_sif_reg_en_to_bist_o48, fabric_sif_reg_en_to_bist_o49, fabric_sif_reg_en_to_bist_o50, fabric_sif_reg_en_to_bist_o51, fabric_sif_reg_en_to_bist_o52, fabric_sif_reg_en_to_bist_o53, fabric_sif_reg_en_to_bist_o54, fabric_sif_reg_en_to_bist_o55, fabric_sif_reg_en_to_bist_o56, fabric_sif_reg_en_to_bist_o57, fabric_sif_reg_en_to_bist_o58, fabric_sif_reg_en_to_bist_o59, fabric_sif_reg_en_to_bist_o60, fabric_sif_reg_en_to_bist_o61, fabric_sif_reg_en_to_bist_o62, fabric_sif_reg_en_to_bist_o63, fabric_sif_reg_en_to_bist_o64, fabric_sif_reg_en_to_bist_o65, fabric_sif_reg_en_to_bist_o66
+, fabric_sif_reg_en_to_bist_o67, fabric_sif_reg_en_to_bist_o68, fabric_sif_reg_en_to_bist_o69, fabric_sif_reg_en_to_bist_o70, fabric_sif_reg_en_to_bist_o71, fabric_sif_reg_en_to_bist_o72, fabric_sif_reg_en_to_bist_o73, fabric_sif_reg_en_to_bist_o74, fabric_sif_reg_en_to_bist_o75, fabric_sif_reg_en_to_bist_o76, fabric_sif_reg_en_to_bist_o77, fabric_sif_reg_en_to_bist_o78, fabric_sif_reg_en_to_bist_o79, fabric_sif_reg_en_to_bist_o80, fabric_sif_reg_en_to_bist_o81, fabric_sif_reg_en_to_bist_o82, fabric_sif_reg_en_to_bist_o83, fabric_sif_reg_en_to_bist_o84, fabric_sif_reg_en_to_bist_o85, fabric_sif_reg_en_to_bist_o86, fabric_sif_reg_en_to_bist_o87
+, fabric_sif_reg_en_to_bist_o88, fabric_sif_reg_en_to_bist_o89, fabric_sif_reg_en_to_bist_o90, fabric_sif_reg_en_to_bist_o91, fabric_sif_reg_en_to_bist_o92, fabric_sif_reg_en_to_bist_o93, fabric_sif_reg_en_to_bist_o94, fabric_sif_reg_en_to_bist_o95, fabric_sif_reg_en_to_bist_o96, fabric_sif_reg_en_to_bist_o97, fabric_sif_reg_en_to_bist_o98, fabric_sif_reg_en_to_bist_o99, fabric_sif_reg_en_to_bist_o100, fabric_sif_reg_en_to_bist_o101, fabric_sif_reg_en_to_bist_o102, fabric_sif_reg_en_to_bist_o103, fabric_sif_reg_en_to_bist_o104, fabric_sif_reg_en_to_bist_o105, fabric_sif_reg_en_to_bist_o106, fabric_sif_reg_en_to_bist_o107, fabric_sif_reg_en_to_bist_o108
+, fabric_sif_reg_en_to_bist_o109, fabric_sif_reg_en_to_bist_o110, fabric_sif_reg_en_to_bist_o111, fabric_sif_reg_en_to_bist_o112, fabric_sif_reg_en_to_bist_o113, fabric_sif_reg_en_to_bist_o114, fabric_sif_reg_en_to_bist_o115, fabric_sif_reg_en_to_bist_o116, fabric_sif_reg_en_to_bist_o117, fabric_sif_reg_en_to_bist_o118, fabric_sif_reg_en_to_bist_o119, fabric_sif_reg_en_to_bist_o120, fabric_debug_otp_manager_read_otp_o, fabric_otp_user_sec_o, fabric_otp_user_wlromout_o1, fabric_otp_user_wlromout_o2, fabric_otp_user_wlromout_o3, fabric_otp_user_wlromout_o4, fabric_otp_user_wlromout_o5, fabric_otp_user_wlromout_o6, fabric_otp_user_wlromout_o7
+, fabric_otp_user_wlromout_o8, fabric_otp_user_wlromout_o9, fabric_otp_user_wlromout_o10, fabric_mrepair_fuse_bend1_o, fabric_mrepair_fuse_flagstate_o1, fabric_mrepair_fuse_flagstate_o2, fabric_mrepair_fuse_flagstate_o3, fabric_mrepair_fuse_flagstate_o4, fabric_system_data_from_mem_bist_o1, fabric_system_data_from_mem_bist_o2, fabric_system_data_from_mem_bist_o3, fabric_system_data_from_mem_bist_o4, fabric_system_data_from_mem_bist_o5, fabric_system_data_from_mem_bist_o6, fabric_system_data_from_mem_bist_o7, fabric_system_data_from_mem_bist_o8, fabric_system_data_from_mem_bist_o9, fabric_system_data_from_mem_bist_o10, fabric_system_data_from_mem_bist_o11, fabric_system_data_from_mem_bist_o12, fabric_system_data_from_mem_bist_o13
+, fabric_system_data_from_mem_bist_o14, fabric_system_data_from_mem_bist_o15, fabric_system_data_from_mem_bist_o16, fabric_system_data_from_mem_bist_o17, fabric_system_data_from_mem_bist_o18, fabric_system_data_from_mem_bist_o19, fabric_system_data_from_mem_bist_o20, fabric_system_data_from_mem_bist_o21, fabric_system_data_from_mem_bist_o22, fabric_system_data_from_mem_bist_o23, fabric_system_data_from_mem_bist_o24, fabric_direct_data_o1, fabric_direct_data_o2, fabric_direct_data_o3, fabric_direct_data_o4, fabric_direct_data_o5, fabric_direct_data_o6, fabric_direct_data_o7, fabric_direct_data_o8, fabric_direct_data_o9, fabric_direct_data_o10
+, fabric_direct_data_o11, fabric_direct_data_o12, fabric_direct_data_o13, fabric_direct_data_o14, fabric_direct_data_o15, fabric_direct_data_o16, fabric_direct_data_o17, fabric_direct_data_o18, fabric_direct_data_o19, fabric_direct_data_o20, fabric_direct_data_o21, fabric_direct_data_o22, fabric_direct_data_o23, fabric_direct_data_o24, fabric_direct_data_o25, fabric_direct_data_o26, fabric_direct_data_o27, fabric_direct_data_o28, fabric_direct_data_o29, fabric_direct_data_o30, fabric_direct_data_o31
+, fabric_direct_data_o32, fabric_otp_user_bbad_o, fabric_user_read_cycle_o, fabric_chip_status_o1, fabric_chip_status_o2, fabric_chip_status_o3, fabric_chip_status_o4, fabric_chip_status_o5, fabric_chip_status_o6, fabric_chip_status_o7, fabric_chip_status_o8, fabric_chip_status_o9, fabric_chip_status_o10, fabric_chip_status_o11, fabric_chip_status_o12, fabric_chip_status_o13, fabric_chip_status_o14, fabric_chip_status_o15, fabric_chip_status_o16, fabric_chip_status_o17, fabric_chip_status_o18
+, fabric_chip_status_o19, fabric_chip_status_o20, fabric_chip_status_o21, fabric_chip_status_o22, fabric_chip_status_o23, fabric_chip_status_o24, fabric_chip_status_o25, fabric_chip_status_o26, fabric_chip_status_o27, fabric_chip_status_o28, fabric_chip_status_o29, fabric_chip_status_o30, fabric_chip_status_o31, fabric_chip_status_o32, fabric_chip_status_o33, fabric_chip_status_o34, fabric_chip_status_o35, fabric_chip_status_o36, fabric_chip_status_o37, fabric_chip_status_o38, fabric_chip_status_o39
+, fabric_chip_status_o40, fabric_chip_status_o41, fabric_chip_status_o42, fabric_chip_status_o43, fabric_chip_status_o44, fabric_chip_status_o45, fabric_chip_status_o46, fabric_chip_status_o47, fabric_chip_status_o48, fabric_chip_status_o49, fabric_chip_status_o50, fabric_chip_status_o51, fabric_chip_status_o52, fabric_chip_status_o53, fabric_chip_status_o54, fabric_chip_status_o55, fabric_chip_status_o56, fabric_chip_status_o57, fabric_chip_status_o58, fabric_chip_status_o59, fabric_chip_status_o60
+, fabric_chip_status_o61, fabric_chip_status_o62, fabric_chip_status_o63, fabric_chip_status_o64, fabric_chip_status_o65, fabric_chip_status_o66, fabric_chip_status_o67, fabric_chip_status_o68, fabric_chip_status_o69, fabric_chip_status_o70, fabric_chip_status_o71, fabric_chip_status_o72, fabric_mrepair_fuse_disturbed_o, fabric_debug_otpboot_state_o1, fabric_debug_otpboot_state_o2, fabric_debug_otpboot_state_o3, fabric_pd_ready_o1, fabric_pd_ready_o2, fabric_pd_ready_o3, fabric_pd_ready_o4, fabric_pd_ready_o5
+, fabric_pd_ready_o6, fabric_pd_ready_o7, fabric_pd_ready_o8, fabric_pd_ready_o9, fabric_pd_ready_o10, fabric_pd_ready_o11, fabric_pd_ready_o12, fabric_pd_ready_o13, fabric_pd_ready_o14, fabric_pd_ready_o15, fabric_pd_ready_o16, fabric_pd_ready_o17, fabric_pd_ready_o18, fabric_pd_ready_o19, fabric_pd_ready_o20, fabric_pd_ready_o21, fabric_pd_ready_o22, fabric_pd_ready_o23, fabric_pd_ready_o24, fabric_debug_key_correct_o, fabric_otp_apb_ready_o
+, fabric_otp_user_progfail_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_bend2_o, fabric_debug_lifecycle_o1, fabric_debug_lifecycle_o2, fabric_debug_lifecycle_o3, fabric_debug_lifecycle_o4, fabric_mrepair_fuse_ack_o, fabric_debug_cpt_retry_o1, fabric_debug_cpt_retry_o2, fabric_debug_cpt_retry_o3, fabric_debug_cpt_retry_o4, fabric_otp_security_ack_o, fabric_debug_otpmgmt_state_o1, fabric_debug_otpmgmt_state_o2, fabric_debug_otpmgmt_state_o3, fabric_mrepair_fuse_progfail_o, fabric_otp_user_bist2fail_o1, fabric_otp_user_bist2fail_o2, fabric_otp_user_bist2fail_o3, fabric_otp_user_bist2fail_o4
+, fabric_otp_user_bist2fail_o5, fabric_otp_user_bist2fail_o6, fabric_otp_user_bist2fail_o7, fabric_user_data_o1, fabric_user_data_o2, fabric_user_data_o3, fabric_user_data_o4, fabric_user_data_o5, fabric_user_data_o6, fabric_user_data_o7, fabric_user_data_o8, fabric_user_data_o9, fabric_user_data_o10, fabric_user_data_o11, fabric_user_data_o12, fabric_user_data_o13, fabric_user_data_o14, fabric_user_data_o15, fabric_user_data_o16, fabric_user_data_o17, fabric_user_data_o18
+, fabric_user_data_o19, fabric_user_data_o20, fabric_user_data_o21, fabric_user_data_o22, fabric_user_data_o23, fabric_user_data_o24, fabric_user_data_o25, fabric_user_data_o26, fabric_user_data_o27, fabric_user_data_o28, fabric_user_data_o29, fabric_user_data_o30, fabric_user_data_o31, fabric_user_data_o32, fabric_jtag_tdi_o, fabric_lowskew_o3, fabric_lowskew_o5, fabric_lowskew_o4, fabric_debug_error_o, fabric_jtag_usr2_o, fabric_mrepair_fuse_wlromout_o1
+, fabric_mrepair_fuse_wlromout_o2, fabric_mrepair_fuse_wlromout_o3, fabric_mrepair_fuse_wlromout_o4, fabric_mrepair_fuse_wlromout_o5, fabric_mrepair_fuse_wlromout_o6, fabric_mrepair_fuse_wlromout_o7, fabric_mrepair_fuse_wlromout_o8, fabric_mrepair_fuse_wlromout_o9, fabric_mrepair_fuse_wlromout_o10, fabric_debug_otpapb_state_o1, fabric_debug_otpapb_state_o2, fabric_debug_otpapb_state_o3, fabric_otp_user_bist1fail_o1, fabric_otp_user_bist1fail_o2, fabric_otp_user_bist1fail_o3, fabric_otp_user_bist1fail_o4, fabric_otp_user_bist1fail_o5, fabric_otp_user_bist1fail_o6, fabric_otp_user_bist1fail_o7, fabric_otp_user_bist1fail_o8, fabric_otp_security_bist_fail2_o1
+, fabric_otp_security_bist_fail2_o2, fabric_otp_security_bist_fail2_o3, fabric_otp_security_bist_fail2_o4, fabric_otp_security_bist_fail2_o5, fabric_otp_security_bist_fail2_o6, fabric_otp_security_bist_fail2_o7, fabric_otp_user_disturbed_o, fabric_flag_trigger_o, fabric_otp_security_bist_end2_o, fabric_otp_security_bist_fail1_o1, fabric_otp_security_bist_fail1_o2, fabric_otp_security_bist_fail1_o3, fabric_otp_security_bist_fail1_o4, fabric_otp_security_bist_fail1_o5, fabric_otp_security_bist_fail1_o6, fabric_otp_security_bist_fail1_o7, fabric_otp_security_bist_fail1_o8, fabric_mrepair_fuse_locked_o, fabric_otp_user_flagstate_o1, fabric_otp_user_flagstate_o2, fabric_otp_user_flagstate_o3
+, fabric_otp_user_flagstate_o4, fabric_otp_security_scanout_o1, fabric_otp_security_scanout_o2, fabric_otp_security_scanout_o3, fabric_otp_security_scanout_o4, fabric_otp_security_scanout_o5, fabric_user_write_cycle_o, fabric_debug_fsm_state_o1, fabric_debug_fsm_state_o2, fabric_debug_fsm_state_o3, fabric_otp_user_ded_o, fabric_debug_otp_manager_read_done_o, fabric_debug_frame_use_encryption_o, fabric_data_to_system_o, fabric_jtag_usr1_o, fabric_otp_user_bend1_o, fabric_debug_otpboot_curr_addr_o1, fabric_debug_otpboot_curr_addr_o2, fabric_debug_otpboot_curr_addr_o3, fabric_debug_otpboot_curr_addr_o4, fabric_debug_otpboot_curr_addr_o5
+, fabric_debug_otpboot_curr_addr_o6, fabric_debug_otpboot_curr_addr_o7, fabric_debug_otpboot_curr_addr_o8, fabric_mrepair_fuse_ready_o, fabric_mrepair_fuse_calibrated_o, fabric_sif_load_en_to_bist_o1, fabric_sif_load_en_to_bist_o2, fabric_sif_load_en_to_bist_o3, fabric_sif_load_en_to_bist_o4, fabric_sif_load_en_to_bist_o5, fabric_sif_load_en_to_bist_o6, fabric_sif_load_en_to_bist_o7, fabric_sif_load_en_to_bist_o8, fabric_sif_load_en_to_bist_o9, fabric_sif_load_en_to_bist_o10, fabric_sif_load_en_to_bist_o11, fabric_sif_load_en_to_bist_o12, fabric_sif_load_en_to_bist_o13, fabric_sif_load_en_to_bist_o14, fabric_sif_load_en_to_bist_o15, fabric_sif_load_en_to_bist_o16
+, fabric_sif_load_en_to_bist_o17, fabric_sif_load_en_to_bist_o18, fabric_sif_load_en_to_bist_o19, fabric_sif_load_en_to_bist_o20, fabric_sif_load_en_to_bist_o21, fabric_sif_load_en_to_bist_o22, fabric_sif_load_en_to_bist_o23, fabric_sif_load_en_to_bist_o24, fabric_io_out_o1, fabric_io_out_o2, fabric_io_out_o3, fabric_io_out_o4, fabric_io_out_o5, fabric_io_out_o6, fabric_io_out_o7, fabric_io_out_o8, fabric_io_out_o9, fabric_io_out_o10, fabric_io_out_o11, fabric_io_out_o12, fabric_io_out_o13
+, fabric_io_out_o14, fabric_io_out_o15, fabric_io_out_o16, fabric_io_out_o17, fabric_io_out_o18, fabric_io_out_o19, fabric_io_out_o20, fabric_io_out_o21, fabric_io_out_o22, fabric_io_out_o23, fabric_io_out_o24, fabric_io_out_o25, fabric_mrepair_fuse_startword_o1, fabric_mrepair_fuse_startword_o2, fabric_mrepair_fuse_startword_o3, fabric_mrepair_fuse_startword_o4, fabric_mrepair_fuse_startword_o5, fabric_mrepair_fuse_startword_o6, fabric_mrepair_fuse_startword_o7, fabric_mrepair_fuse_startword_o8, fabric_mrepair_fuse_startword_o9
+, fabric_mrepair_fuse_startword_o10, fabric_mrepair_fuse_startword_o11, fabric_mrepair_fuse_startword_o12, fabric_mrepair_fuse_startword_o13, fabric_mrepair_fuse_startword_o14, fabric_mrepair_fuse_startword_o15, fabric_mrepair_fuse_startword_o16, fabric_system_dataready_o, fabric_mrepair_fuse_pwok_o, fabric_lowskew_o6, fabric_cfg_fabric_user_flag_o, fabric_otp_user_dout_o1, fabric_otp_user_dout_o2, fabric_otp_user_dout_o3, fabric_otp_user_dout_o4, fabric_otp_user_dout_o5, fabric_otp_user_dout_o6, fabric_otp_user_dout_o7, fabric_otp_user_dout_o8, fabric_otp_user_dout_o9, fabric_otp_user_dout_o10
+, fabric_otp_user_dout_o11, fabric_otp_user_dout_o12, fabric_otp_user_dout_o13, fabric_otp_user_dout_o14, fabric_otp_user_dout_o15, fabric_otp_user_dout_o16, fabric_otp_user_dout_o17, fabric_otp_user_dout_o18, fabric_otp_user_dout_o19, fabric_otp_user_dout_o20, fabric_otp_user_dout_o21, fabric_otp_user_dout_o22, fabric_otp_user_dout_o23, fabric_otp_user_dout_o24, fabric_otp_user_dout_o25, fabric_otp_user_dout_o26, fabric_otp_user_dout_o27, fabric_otp_user_dout_o28, fabric_otp_user_dout_o29, fabric_otp_user_dout_o30, fabric_otp_user_dout_o31
+, fabric_otp_user_dout_o32, fabric_otp_user_dout_o33, fabric_otp_user_dout_o34, fabric_otp_user_dout_o35, fabric_otp_user_dout_o36, fabric_otp_user_dout_o37, fabric_otp_user_dout_o38, fabric_otp_user_dout_o39, fabric_otp_user_dout_o40, fabric_otp_user_dout_o41, fabric_mrepair_fuse_bist2fail_o1, fabric_mrepair_fuse_bist2fail_o2, fabric_mrepair_fuse_bist2fail_o3, fabric_mrepair_fuse_bist2fail_o4, fabric_mrepair_fuse_bist2fail_o5, fabric_mrepair_fuse_bist2fail_o6, fabric_mrepair_fuse_bist2fail_o7, fabric_status_cold_start_o, fabric_flag_error_o, fabric_debug_direct_permission_read_o1, fabric_debug_direct_permission_read_o2
+, fabric_debug_direct_permission_read_o3, fabric_debug_direct_permission_read_o4);
+    input fabric_ahb_direct_data_i1;
+    input fabric_ahb_direct_data_i10;
+    input fabric_ahb_direct_data_i11;
+    input fabric_ahb_direct_data_i12;
+    input fabric_ahb_direct_data_i13;
+    input fabric_ahb_direct_data_i14;
+    input fabric_ahb_direct_data_i15;
+    input fabric_ahb_direct_data_i16;
+    input fabric_ahb_direct_data_i17;
+    input fabric_ahb_direct_data_i18;
+    input fabric_ahb_direct_data_i19;
+    input fabric_ahb_direct_data_i2;
+    input fabric_ahb_direct_data_i20;
+    input fabric_ahb_direct_data_i21;
+    input fabric_ahb_direct_data_i22;
+    input fabric_ahb_direct_data_i23;
+    input fabric_ahb_direct_data_i24;
+    input fabric_ahb_direct_data_i25;
+    input fabric_ahb_direct_data_i26;
+    input fabric_ahb_direct_data_i27;
+    input fabric_ahb_direct_data_i28;
+    input fabric_ahb_direct_data_i29;
+    input fabric_ahb_direct_data_i3;
+    input fabric_ahb_direct_data_i30;
+    input fabric_ahb_direct_data_i31;
+    input fabric_ahb_direct_data_i32;
+    input fabric_ahb_direct_data_i4;
+    input fabric_ahb_direct_data_i5;
+    input fabric_ahb_direct_data_i6;
+    input fabric_ahb_direct_data_i7;
+    input fabric_ahb_direct_data_i8;
+    input fabric_ahb_direct_data_i9;
+    output fabric_ahb_direct_data_o1;
+    output fabric_ahb_direct_data_o10;
+    output fabric_ahb_direct_data_o11;
+    output fabric_ahb_direct_data_o12;
+    output fabric_ahb_direct_data_o13;
+    output fabric_ahb_direct_data_o14;
+    output fabric_ahb_direct_data_o15;
+    output fabric_ahb_direct_data_o16;
+    output fabric_ahb_direct_data_o17;
+    output fabric_ahb_direct_data_o18;
+    output fabric_ahb_direct_data_o19;
+    output fabric_ahb_direct_data_o2;
+    output fabric_ahb_direct_data_o20;
+    output fabric_ahb_direct_data_o21;
+    output fabric_ahb_direct_data_o22;
+    output fabric_ahb_direct_data_o23;
+    output fabric_ahb_direct_data_o24;
+    output fabric_ahb_direct_data_o25;
+    output fabric_ahb_direct_data_o26;
+    output fabric_ahb_direct_data_o27;
+    output fabric_ahb_direct_data_o28;
+    output fabric_ahb_direct_data_o29;
+    output fabric_ahb_direct_data_o3;
+    output fabric_ahb_direct_data_o30;
+    output fabric_ahb_direct_data_o31;
+    output fabric_ahb_direct_data_o32;
+    output fabric_ahb_direct_data_o4;
+    output fabric_ahb_direct_data_o5;
+    output fabric_ahb_direct_data_o6;
+    output fabric_ahb_direct_data_o7;
+    output fabric_ahb_direct_data_o8;
+    output fabric_ahb_direct_data_o9;
+    output fabric_cfg_fabric_user_flag_o;
+    output fabric_cfg_fabric_user_unmask_o;
+    output fabric_chip_status_o1;
+    output fabric_chip_status_o10;
+    output fabric_chip_status_o11;
+    output fabric_chip_status_o12;
+    output fabric_chip_status_o13;
+    output fabric_chip_status_o14;
+    output fabric_chip_status_o15;
+    output fabric_chip_status_o16;
+    output fabric_chip_status_o17;
+    output fabric_chip_status_o18;
+    output fabric_chip_status_o19;
+    output fabric_chip_status_o2;
+    output fabric_chip_status_o20;
+    output fabric_chip_status_o21;
+    output fabric_chip_status_o22;
+    output fabric_chip_status_o23;
+    output fabric_chip_status_o24;
+    output fabric_chip_status_o25;
+    output fabric_chip_status_o26;
+    output fabric_chip_status_o27;
+    output fabric_chip_status_o28;
+    output fabric_chip_status_o29;
+    output fabric_chip_status_o3;
+    output fabric_chip_status_o30;
+    output fabric_chip_status_o31;
+    output fabric_chip_status_o32;
+    output fabric_chip_status_o33;
+    output fabric_chip_status_o34;
+    output fabric_chip_status_o35;
+    output fabric_chip_status_o36;
+    output fabric_chip_status_o37;
+    output fabric_chip_status_o38;
+    output fabric_chip_status_o39;
+    output fabric_chip_status_o4;
+    output fabric_chip_status_o40;
+    output fabric_chip_status_o41;
+    output fabric_chip_status_o42;
+    output fabric_chip_status_o43;
+    output fabric_chip_status_o44;
+    output fabric_chip_status_o45;
+    output fabric_chip_status_o46;
+    output fabric_chip_status_o47;
+    output fabric_chip_status_o48;
+    output fabric_chip_status_o49;
+    output fabric_chip_status_o5;
+    output fabric_chip_status_o50;
+    output fabric_chip_status_o51;
+    output fabric_chip_status_o52;
+    output fabric_chip_status_o53;
+    output fabric_chip_status_o54;
+    output fabric_chip_status_o55;
+    output fabric_chip_status_o56;
+    output fabric_chip_status_o57;
+    output fabric_chip_status_o58;
+    output fabric_chip_status_o59;
+    output fabric_chip_status_o6;
+    output fabric_chip_status_o60;
+    output fabric_chip_status_o61;
+    output fabric_chip_status_o62;
+    output fabric_chip_status_o63;
+    output fabric_chip_status_o64;
+    output fabric_chip_status_o65;
+    output fabric_chip_status_o66;
+    output fabric_chip_status_o67;
+    output fabric_chip_status_o68;
+    output fabric_chip_status_o69;
+    output fabric_chip_status_o7;
+    output fabric_chip_status_o70;
+    output fabric_chip_status_o71;
+    output fabric_chip_status_o72;
+    output fabric_chip_status_o8;
+    output fabric_chip_status_o9;
+    input fabric_data_from_bist_i1;
+    input fabric_data_from_bist_i10;
+    input fabric_data_from_bist_i11;
+    input fabric_data_from_bist_i12;
+    input fabric_data_from_bist_i13;
+    input fabric_data_from_bist_i14;
+    input fabric_data_from_bist_i15;
+    input fabric_data_from_bist_i16;
+    input fabric_data_from_bist_i17;
+    input fabric_data_from_bist_i18;
+    input fabric_data_from_bist_i19;
+    input fabric_data_from_bist_i2;
+    input fabric_data_from_bist_i20;
+    input fabric_data_from_bist_i21;
+    input fabric_data_from_bist_i22;
+    input fabric_data_from_bist_i23;
+    input fabric_data_from_bist_i24;
+    input fabric_data_from_bist_i3;
+    input fabric_data_from_bist_i4;
+    input fabric_data_from_bist_i5;
+    input fabric_data_from_bist_i6;
+    input fabric_data_from_bist_i7;
+    input fabric_data_from_bist_i8;
+    input fabric_data_from_bist_i9;
+    input fabric_data_from_system_i;
+    input fabric_data_shift_en_i;
+    output fabric_data_to_bist_o1;
+    output fabric_data_to_bist_o10;
+    output fabric_data_to_bist_o11;
+    output fabric_data_to_bist_o12;
+    output fabric_data_to_bist_o13;
+    output fabric_data_to_bist_o14;
+    output fabric_data_to_bist_o15;
+    output fabric_data_to_bist_o16;
+    output fabric_data_to_bist_o17;
+    output fabric_data_to_bist_o18;
+    output fabric_data_to_bist_o19;
+    output fabric_data_to_bist_o2;
+    output fabric_data_to_bist_o20;
+    output fabric_data_to_bist_o21;
+    output fabric_data_to_bist_o22;
+    output fabric_data_to_bist_o23;
+    output fabric_data_to_bist_o24;
+    output fabric_data_to_bist_o3;
+    output fabric_data_to_bist_o4;
+    output fabric_data_to_bist_o5;
+    output fabric_data_to_bist_o6;
+    output fabric_data_to_bist_o7;
+    output fabric_data_to_bist_o8;
+    output fabric_data_to_bist_o9;
+    output fabric_data_to_system_o;
+    output fabric_debug_access_reg_data_ready_o;
+    output fabric_debug_bsec_core_status_o1;
+    output fabric_debug_bsec_core_status_o10;
+    output fabric_debug_bsec_core_status_o11;
+    output fabric_debug_bsec_core_status_o12;
+    output fabric_debug_bsec_core_status_o13;
+    output fabric_debug_bsec_core_status_o14;
+    output fabric_debug_bsec_core_status_o15;
+    output fabric_debug_bsec_core_status_o16;
+    output fabric_debug_bsec_core_status_o17;
+    output fabric_debug_bsec_core_status_o18;
+    output fabric_debug_bsec_core_status_o19;
+    output fabric_debug_bsec_core_status_o2;
+    output fabric_debug_bsec_core_status_o20;
+    output fabric_debug_bsec_core_status_o21;
+    output fabric_debug_bsec_core_status_o22;
+    output fabric_debug_bsec_core_status_o23;
+    output fabric_debug_bsec_core_status_o24;
+    output fabric_debug_bsec_core_status_o25;
+    output fabric_debug_bsec_core_status_o26;
+    output fabric_debug_bsec_core_status_o27;
+    output fabric_debug_bsec_core_status_o28;
+    output fabric_debug_bsec_core_status_o29;
+    output fabric_debug_bsec_core_status_o3;
+    output fabric_debug_bsec_core_status_o30;
+    output fabric_debug_bsec_core_status_o31;
+    output fabric_debug_bsec_core_status_o32;
+    output fabric_debug_bsec_core_status_o4;
+    output fabric_debug_bsec_core_status_o5;
+    output fabric_debug_bsec_core_status_o6;
+    output fabric_debug_bsec_core_status_o7;
+    output fabric_debug_bsec_core_status_o8;
+    output fabric_debug_bsec_core_status_o9;
+    output fabric_debug_cpt_retry_o1;
+    output fabric_debug_cpt_retry_o2;
+    output fabric_debug_cpt_retry_o3;
+    output fabric_debug_cpt_retry_o4;
+    output fabric_debug_direct_permission_read_o1;
+    output fabric_debug_direct_permission_read_o2;
+    output fabric_debug_direct_permission_read_o3;
+    output fabric_debug_direct_permission_read_o4;
+    output fabric_debug_direct_permission_write_o1;
+    output fabric_debug_direct_permission_write_o2;
+    output fabric_debug_direct_permission_write_o3;
+    output fabric_debug_direct_permission_write_o4;
+    output fabric_debug_error_o;
+    output fabric_debug_frame_permission_frame_o1;
+    output fabric_debug_frame_permission_frame_o2;
+    output fabric_debug_frame_permission_frame_o3;
+    output fabric_debug_frame_permission_frame_o4;
+    output fabric_debug_frame_use_encryption_o;
+    output fabric_debug_fsm_state_o1;
+    output fabric_debug_fsm_state_o2;
+    output fabric_debug_fsm_state_o3;
+    output fabric_debug_key_correct_o;
+    output fabric_debug_lifecycle_o1;
+    output fabric_debug_lifecycle_o2;
+    output fabric_debug_lifecycle_o3;
+    output fabric_debug_lifecycle_o4;
+    output fabric_debug_lock_reg_o;
+    output fabric_debug_otp_manager_read_done_o;
+    output fabric_debug_otp_manager_read_otp_o;
+    output fabric_debug_otp_reload_err_o;
+    output fabric_debug_otpapb_state_o1;
+    output fabric_debug_otpapb_state_o2;
+    output fabric_debug_otpapb_state_o3;
+    output fabric_debug_otpboot_curr_addr_o1;
+    output fabric_debug_otpboot_curr_addr_o2;
+    output fabric_debug_otpboot_curr_addr_o3;
+    output fabric_debug_otpboot_curr_addr_o4;
+    output fabric_debug_otpboot_curr_addr_o5;
+    output fabric_debug_otpboot_curr_addr_o6;
+    output fabric_debug_otpboot_curr_addr_o7;
+    output fabric_debug_otpboot_curr_addr_o8;
+    output fabric_debug_otpboot_state_o1;
+    output fabric_debug_otpboot_state_o2;
+    output fabric_debug_otpboot_state_o3;
+    output fabric_debug_otpmgmt_state_o1;
+    output fabric_debug_otpmgmt_state_o2;
+    output fabric_debug_otpmgmt_state_o3;
+    output fabric_debug_rst_soft_o;
+    output fabric_debug_security_boot_done_o;
+    output fabric_debug_security_error_read_o;
+    output fabric_decoder_init_ready_o;
+    input fabric_direct_data_i1;
+    input fabric_direct_data_i10;
+    input fabric_direct_data_i11;
+    input fabric_direct_data_i12;
+    input fabric_direct_data_i13;
+    input fabric_direct_data_i14;
+    input fabric_direct_data_i15;
+    input fabric_direct_data_i16;
+    input fabric_direct_data_i17;
+    input fabric_direct_data_i18;
+    input fabric_direct_data_i19;
+    input fabric_direct_data_i2;
+    input fabric_direct_data_i20;
+    input fabric_direct_data_i21;
+    input fabric_direct_data_i22;
+    input fabric_direct_data_i23;
+    input fabric_direct_data_i24;
+    input fabric_direct_data_i25;
+    input fabric_direct_data_i26;
+    input fabric_direct_data_i27;
+    input fabric_direct_data_i28;
+    input fabric_direct_data_i29;
+    input fabric_direct_data_i3;
+    input fabric_direct_data_i30;
+    input fabric_direct_data_i31;
+    input fabric_direct_data_i32;
+    input fabric_direct_data_i4;
+    input fabric_direct_data_i5;
+    input fabric_direct_data_i6;
+    input fabric_direct_data_i7;
+    input fabric_direct_data_i8;
+    input fabric_direct_data_i9;
+    output fabric_direct_data_o1;
+    output fabric_direct_data_o10;
+    output fabric_direct_data_o11;
+    output fabric_direct_data_o12;
+    output fabric_direct_data_o13;
+    output fabric_direct_data_o14;
+    output fabric_direct_data_o15;
+    output fabric_direct_data_o16;
+    output fabric_direct_data_o17;
+    output fabric_direct_data_o18;
+    output fabric_direct_data_o19;
+    output fabric_direct_data_o2;
+    output fabric_direct_data_o20;
+    output fabric_direct_data_o21;
+    output fabric_direct_data_o22;
+    output fabric_direct_data_o23;
+    output fabric_direct_data_o24;
+    output fabric_direct_data_o25;
+    output fabric_direct_data_o26;
+    output fabric_direct_data_o27;
+    output fabric_direct_data_o28;
+    output fabric_direct_data_o29;
+    output fabric_direct_data_o3;
+    output fabric_direct_data_o30;
+    output fabric_direct_data_o31;
+    output fabric_direct_data_o32;
+    output fabric_direct_data_o4;
+    output fabric_direct_data_o5;
+    output fabric_direct_data_o6;
+    output fabric_direct_data_o7;
+    output fabric_direct_data_o8;
+    output fabric_direct_data_o9;
+    input fabric_end_encoding_i;
+    output fabric_flag_error_o;
+    output fabric_flag_ready_o;
+    output fabric_flag_trigger_o;
+    output fabric_fuse_status_o1;
+    output fabric_fuse_status_o2;
+    output fabric_fuse_status_o3;
+    output fabric_global_chip_status_o1;
+    output fabric_global_chip_status_o2;
+    output fabric_global_chip_status_o3;
+    input fabric_io_in_i1;
+    input fabric_io_in_i10;
+    input fabric_io_in_i11;
+    input fabric_io_in_i12;
+    input fabric_io_in_i13;
+    input fabric_io_in_i14;
+    input fabric_io_in_i15;
+    input fabric_io_in_i16;
+    input fabric_io_in_i17;
+    input fabric_io_in_i18;
+    input fabric_io_in_i19;
+    input fabric_io_in_i2;
+    input fabric_io_in_i20;
+    input fabric_io_in_i21;
+    input fabric_io_in_i22;
+    input fabric_io_in_i23;
+    input fabric_io_in_i24;
+    input fabric_io_in_i25;
+    input fabric_io_in_i3;
+    input fabric_io_in_i4;
+    input fabric_io_in_i5;
+    input fabric_io_in_i6;
+    input fabric_io_in_i7;
+    input fabric_io_in_i8;
+    input fabric_io_in_i9;
+    input fabric_io_oe_i1;
+    input fabric_io_oe_i10;
+    input fabric_io_oe_i11;
+    input fabric_io_oe_i12;
+    input fabric_io_oe_i13;
+    input fabric_io_oe_i14;
+    input fabric_io_oe_i15;
+    input fabric_io_oe_i16;
+    input fabric_io_oe_i17;
+    input fabric_io_oe_i18;
+    input fabric_io_oe_i19;
+    input fabric_io_oe_i2;
+    input fabric_io_oe_i20;
+    input fabric_io_oe_i21;
+    input fabric_io_oe_i22;
+    input fabric_io_oe_i23;
+    input fabric_io_oe_i24;
+    input fabric_io_oe_i25;
+    input fabric_io_oe_i3;
+    input fabric_io_oe_i4;
+    input fabric_io_oe_i5;
+    input fabric_io_oe_i6;
+    input fabric_io_oe_i7;
+    input fabric_io_oe_i8;
+    input fabric_io_oe_i9;
+    output fabric_io_out_o1;
+    output fabric_io_out_o10;
+    output fabric_io_out_o11;
+    output fabric_io_out_o12;
+    output fabric_io_out_o13;
+    output fabric_io_out_o14;
+    output fabric_io_out_o15;
+    output fabric_io_out_o16;
+    output fabric_io_out_o17;
+    output fabric_io_out_o18;
+    output fabric_io_out_o19;
+    output fabric_io_out_o2;
+    output fabric_io_out_o20;
+    output fabric_io_out_o21;
+    output fabric_io_out_o22;
+    output fabric_io_out_o23;
+    output fabric_io_out_o24;
+    output fabric_io_out_o25;
+    output fabric_io_out_o3;
+    output fabric_io_out_o4;
+    output fabric_io_out_o5;
+    output fabric_io_out_o6;
+    output fabric_io_out_o7;
+    output fabric_io_out_o8;
+    output fabric_io_out_o9;
+    output fabric_jtag_tdi_o;
+    input fabric_jtag_tdo_usr1_i;
+    input fabric_jtag_tdo_usr2_i;
+    output fabric_jtag_tms_o;
+    output fabric_jtag_trst_n_o;
+    output fabric_jtag_usr1_o;
+    output fabric_jtag_usr2_o;
+    input fabric_lowskew_i20;
+    input fabric_lowskew_i21;
+    input fabric_lowskew_i22;
+    input fabric_lowskew_i23;
+    output fabric_lowskew_o3;
+    output fabric_lowskew_o4;
+    output fabric_lowskew_o5;
+    output fabric_lowskew_o6;
+    output fabric_mrepair_fuse_ack_o;
+    input fabric_mrepair_fuse_add_i1;
+    input fabric_mrepair_fuse_add_i2;
+    input fabric_mrepair_fuse_add_i3;
+    input fabric_mrepair_fuse_add_i4;
+    input fabric_mrepair_fuse_add_i5;
+    input fabric_mrepair_fuse_add_i6;
+    input fabric_mrepair_fuse_add_i7;
+    output fabric_mrepair_fuse_bbad_o;
+    output fabric_mrepair_fuse_bend1_o;
+    output fabric_mrepair_fuse_bend2_o;
+    output fabric_mrepair_fuse_bist1fail_o1;
+    output fabric_mrepair_fuse_bist1fail_o2;
+    output fabric_mrepair_fuse_bist1fail_o3;
+    output fabric_mrepair_fuse_bist1fail_o4;
+    output fabric_mrepair_fuse_bist1fail_o5;
+    output fabric_mrepair_fuse_bist1fail_o6;
+    output fabric_mrepair_fuse_bist1fail_o7;
+    output fabric_mrepair_fuse_bist1fail_o8;
+    output fabric_mrepair_fuse_bist2fail_o1;
+    output fabric_mrepair_fuse_bist2fail_o2;
+    output fabric_mrepair_fuse_bist2fail_o3;
+    output fabric_mrepair_fuse_bist2fail_o4;
+    output fabric_mrepair_fuse_bist2fail_o5;
+    output fabric_mrepair_fuse_bist2fail_o6;
+    output fabric_mrepair_fuse_bist2fail_o7;
+    input fabric_mrepair_fuse_bistmode_i;
+    output fabric_mrepair_fuse_calibrated_o;
+    input fabric_mrepair_fuse_configreg_i1;
+    input fabric_mrepair_fuse_configreg_i10;
+    input fabric_mrepair_fuse_configreg_i11;
+    input fabric_mrepair_fuse_configreg_i12;
+    input fabric_mrepair_fuse_configreg_i13;
+    input fabric_mrepair_fuse_configreg_i14;
+    input fabric_mrepair_fuse_configreg_i15;
+    input fabric_mrepair_fuse_configreg_i16;
+    input fabric_mrepair_fuse_configreg_i17;
+    input fabric_mrepair_fuse_configreg_i18;
+    input fabric_mrepair_fuse_configreg_i19;
+    input fabric_mrepair_fuse_configreg_i2;
+    input fabric_mrepair_fuse_configreg_i20;
+    input fabric_mrepair_fuse_configreg_i21;
+    input fabric_mrepair_fuse_configreg_i22;
+    input fabric_mrepair_fuse_configreg_i23;
+    input fabric_mrepair_fuse_configreg_i24;
+    input fabric_mrepair_fuse_configreg_i25;
+    input fabric_mrepair_fuse_configreg_i26;
+    input fabric_mrepair_fuse_configreg_i27;
+    input fabric_mrepair_fuse_configreg_i28;
+    input fabric_mrepair_fuse_configreg_i29;
+    input fabric_mrepair_fuse_configreg_i3;
+    input fabric_mrepair_fuse_configreg_i30;
+    input fabric_mrepair_fuse_configreg_i31;
+    input fabric_mrepair_fuse_configreg_i32;
+    input fabric_mrepair_fuse_configreg_i4;
+    input fabric_mrepair_fuse_configreg_i5;
+    input fabric_mrepair_fuse_configreg_i6;
+    input fabric_mrepair_fuse_configreg_i7;
+    input fabric_mrepair_fuse_configreg_i8;
+    input fabric_mrepair_fuse_configreg_i9;
+    output fabric_mrepair_fuse_ded_o;
+    input fabric_mrepair_fuse_din_i1;
+    input fabric_mrepair_fuse_din_i10;
+    input fabric_mrepair_fuse_din_i11;
+    input fabric_mrepair_fuse_din_i12;
+    input fabric_mrepair_fuse_din_i13;
+    input fabric_mrepair_fuse_din_i14;
+    input fabric_mrepair_fuse_din_i15;
+    input fabric_mrepair_fuse_din_i16;
+    input fabric_mrepair_fuse_din_i17;
+    input fabric_mrepair_fuse_din_i18;
+    input fabric_mrepair_fuse_din_i19;
+    input fabric_mrepair_fuse_din_i2;
+    input fabric_mrepair_fuse_din_i20;
+    input fabric_mrepair_fuse_din_i21;
+    input fabric_mrepair_fuse_din_i22;
+    input fabric_mrepair_fuse_din_i23;
+    input fabric_mrepair_fuse_din_i24;
+    input fabric_mrepair_fuse_din_i25;
+    input fabric_mrepair_fuse_din_i26;
+    input fabric_mrepair_fuse_din_i27;
+    input fabric_mrepair_fuse_din_i28;
+    input fabric_mrepair_fuse_din_i29;
+    input fabric_mrepair_fuse_din_i3;
+    input fabric_mrepair_fuse_din_i30;
+    input fabric_mrepair_fuse_din_i31;
+    input fabric_mrepair_fuse_din_i32;
+    input fabric_mrepair_fuse_din_i33;
+    input fabric_mrepair_fuse_din_i34;
+    input fabric_mrepair_fuse_din_i35;
+    input fabric_mrepair_fuse_din_i36;
+    input fabric_mrepair_fuse_din_i37;
+    input fabric_mrepair_fuse_din_i38;
+    input fabric_mrepair_fuse_din_i39;
+    input fabric_mrepair_fuse_din_i4;
+    input fabric_mrepair_fuse_din_i5;
+    input fabric_mrepair_fuse_din_i6;
+    input fabric_mrepair_fuse_din_i7;
+    input fabric_mrepair_fuse_din_i8;
+    input fabric_mrepair_fuse_din_i9;
+    input fabric_mrepair_fuse_disturbchecked_i;
+    output fabric_mrepair_fuse_disturbed_o;
+    output fabric_mrepair_fuse_dout_o1;
+    output fabric_mrepair_fuse_dout_o10;
+    output fabric_mrepair_fuse_dout_o11;
+    output fabric_mrepair_fuse_dout_o12;
+    output fabric_mrepair_fuse_dout_o13;
+    output fabric_mrepair_fuse_dout_o14;
+    output fabric_mrepair_fuse_dout_o15;
+    output fabric_mrepair_fuse_dout_o16;
+    output fabric_mrepair_fuse_dout_o17;
+    output fabric_mrepair_fuse_dout_o18;
+    output fabric_mrepair_fuse_dout_o19;
+    output fabric_mrepair_fuse_dout_o2;
+    output fabric_mrepair_fuse_dout_o20;
+    output fabric_mrepair_fuse_dout_o21;
+    output fabric_mrepair_fuse_dout_o22;
+    output fabric_mrepair_fuse_dout_o23;
+    output fabric_mrepair_fuse_dout_o24;
+    output fabric_mrepair_fuse_dout_o25;
+    output fabric_mrepair_fuse_dout_o26;
+    output fabric_mrepair_fuse_dout_o27;
+    output fabric_mrepair_fuse_dout_o28;
+    output fabric_mrepair_fuse_dout_o29;
+    output fabric_mrepair_fuse_dout_o3;
+    output fabric_mrepair_fuse_dout_o30;
+    output fabric_mrepair_fuse_dout_o31;
+    output fabric_mrepair_fuse_dout_o32;
+    output fabric_mrepair_fuse_dout_o33;
+    output fabric_mrepair_fuse_dout_o34;
+    output fabric_mrepair_fuse_dout_o35;
+    output fabric_mrepair_fuse_dout_o36;
+    output fabric_mrepair_fuse_dout_o37;
+    output fabric_mrepair_fuse_dout_o38;
+    output fabric_mrepair_fuse_dout_o39;
+    output fabric_mrepair_fuse_dout_o4;
+    output fabric_mrepair_fuse_dout_o40;
+    output fabric_mrepair_fuse_dout_o41;
+    output fabric_mrepair_fuse_dout_o5;
+    output fabric_mrepair_fuse_dout_o6;
+    output fabric_mrepair_fuse_dout_o7;
+    output fabric_mrepair_fuse_dout_o8;
+    output fabric_mrepair_fuse_dout_o9;
+    input fabric_mrepair_fuse_eccbypass_i;
+    output fabric_mrepair_fuse_flagstate_o1;
+    output fabric_mrepair_fuse_flagstate_o2;
+    output fabric_mrepair_fuse_flagstate_o3;
+    output fabric_mrepair_fuse_flagstate_o4;
+    output fabric_mrepair_fuse_locked_o;
+    input fabric_mrepair_fuse_pdn_i;
+    output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o;
+    input fabric_mrepair_fuse_prgwidth_i1;
+    input fabric_mrepair_fuse_prgwidth_i2;
+    input fabric_mrepair_fuse_prgwidth_i3;
+    input fabric_mrepair_fuse_prog_i;
+    output fabric_mrepair_fuse_progfail_o;
+    output fabric_mrepair_fuse_pwok_o;
+    input fabric_mrepair_fuse_rbact1_i;
+    input fabric_mrepair_fuse_rbact2_i;
+    input fabric_mrepair_fuse_read_i;
+    output fabric_mrepair_fuse_ready_o;
+    input fabric_mrepair_fuse_redbypass_i;
+    output fabric_mrepair_fuse_sec_o;
+    output fabric_mrepair_fuse_startword_o1;
+    output fabric_mrepair_fuse_startword_o10;
+    output fabric_mrepair_fuse_startword_o11;
+    output fabric_mrepair_fuse_startword_o12;
+    output fabric_mrepair_fuse_startword_o13;
+    output fabric_mrepair_fuse_startword_o14;
+    output fabric_mrepair_fuse_startword_o15;
+    output fabric_mrepair_fuse_startword_o16;
+    output fabric_mrepair_fuse_startword_o2;
+    output fabric_mrepair_fuse_startword_o3;
+    output fabric_mrepair_fuse_startword_o4;
+    output fabric_mrepair_fuse_startword_o5;
+    output fabric_mrepair_fuse_startword_o6;
+    output fabric_mrepair_fuse_startword_o7;
+    output fabric_mrepair_fuse_startword_o8;
+    output fabric_mrepair_fuse_startword_o9;
+    input fabric_mrepair_fuse_suppadd_i;
+    input fabric_mrepair_fuse_tm_i;
+    input fabric_mrepair_fuse_tst_scanin_i1;
+    input fabric_mrepair_fuse_tst_scanin_i2;
+    input fabric_mrepair_fuse_tst_scanin_i3;
+    input fabric_mrepair_fuse_tst_scanin_i4;
+    input fabric_mrepair_fuse_tst_scanin_i5;
+    input fabric_mrepair_fuse_tstscanenable_i;
+    output fabric_mrepair_fuse_tstscanout_o1;
+    output fabric_mrepair_fuse_tstscanout_o2;
+    output fabric_mrepair_fuse_tstscanout_o3;
+    output fabric_mrepair_fuse_tstscanout_o4;
+    output fabric_mrepair_fuse_tstscanout_o5;
+    output fabric_mrepair_fuse_wlromout_o1;
+    output fabric_mrepair_fuse_wlromout_o10;
+    output fabric_mrepair_fuse_wlromout_o2;
+    output fabric_mrepair_fuse_wlromout_o3;
+    output fabric_mrepair_fuse_wlromout_o4;
+    output fabric_mrepair_fuse_wlromout_o5;
+    output fabric_mrepair_fuse_wlromout_o6;
+    output fabric_mrepair_fuse_wlromout_o7;
+    output fabric_mrepair_fuse_wlromout_o8;
+    output fabric_mrepair_fuse_wlromout_o9;
+    input fabric_mrepair_fuse_wordlock_i;
+    input fabric_mrepair_initn_i;
+    input fabric_mrepair_mode_i1;
+    input fabric_mrepair_mode_i2;
+    input fabric_mrepair_mode_i3;
+    input fabric_mrepair_mode_i4;
+    input fabric_mrepair_por_i;
+    input fabric_mrepair_rst_n_i;
+    input fabric_otp_apb_addr_i1;
+    input fabric_otp_apb_addr_i10;
+    input fabric_otp_apb_addr_i11;
+    input fabric_otp_apb_addr_i12;
+    input fabric_otp_apb_addr_i13;
+    input fabric_otp_apb_addr_i14;
+    input fabric_otp_apb_addr_i15;
+    input fabric_otp_apb_addr_i16;
+    input fabric_otp_apb_addr_i17;
+    input fabric_otp_apb_addr_i18;
+    input fabric_otp_apb_addr_i19;
+    input fabric_otp_apb_addr_i2;
+    input fabric_otp_apb_addr_i20;
+    input fabric_otp_apb_addr_i21;
+    input fabric_otp_apb_addr_i22;
+    input fabric_otp_apb_addr_i23;
+    input fabric_otp_apb_addr_i24;
+    input fabric_otp_apb_addr_i25;
+    input fabric_otp_apb_addr_i26;
+    input fabric_otp_apb_addr_i27;
+    input fabric_otp_apb_addr_i28;
+    input fabric_otp_apb_addr_i29;
+    input fabric_otp_apb_addr_i3;
+    input fabric_otp_apb_addr_i30;
+    input fabric_otp_apb_addr_i31;
+    input fabric_otp_apb_addr_i32;
+    input fabric_otp_apb_addr_i4;
+    input fabric_otp_apb_addr_i5;
+    input fabric_otp_apb_addr_i6;
+    input fabric_otp_apb_addr_i7;
+    input fabric_otp_apb_addr_i8;
+    input fabric_otp_apb_addr_i9;
+    input fabric_otp_apb_enable_i;
+    output fabric_otp_apb_rdata_o1;
+    output fabric_otp_apb_rdata_o10;
+    output fabric_otp_apb_rdata_o11;
+    output fabric_otp_apb_rdata_o12;
+    output fabric_otp_apb_rdata_o13;
+    output fabric_otp_apb_rdata_o14;
+    output fabric_otp_apb_rdata_o15;
+    output fabric_otp_apb_rdata_o16;
+    output fabric_otp_apb_rdata_o17;
+    output fabric_otp_apb_rdata_o18;
+    output fabric_otp_apb_rdata_o19;
+    output fabric_otp_apb_rdata_o2;
+    output fabric_otp_apb_rdata_o20;
+    output fabric_otp_apb_rdata_o21;
+    output fabric_otp_apb_rdata_o22;
+    output fabric_otp_apb_rdata_o23;
+    output fabric_otp_apb_rdata_o24;
+    output fabric_otp_apb_rdata_o25;
+    output fabric_otp_apb_rdata_o26;
+    output fabric_otp_apb_rdata_o27;
+    output fabric_otp_apb_rdata_o28;
+    output fabric_otp_apb_rdata_o29;
+    output fabric_otp_apb_rdata_o3;
+    output fabric_otp_apb_rdata_o30;
+    output fabric_otp_apb_rdata_o31;
+    output fabric_otp_apb_rdata_o32;
+    output fabric_otp_apb_rdata_o4;
+    output fabric_otp_apb_rdata_o5;
+    output fabric_otp_apb_rdata_o6;
+    output fabric_otp_apb_rdata_o7;
+    output fabric_otp_apb_rdata_o8;
+    output fabric_otp_apb_rdata_o9;
+    output fabric_otp_apb_ready_o;
+    input fabric_otp_apb_sel_i;
+    input fabric_otp_apb_wdata_i1;
+    input fabric_otp_apb_wdata_i10;
+    input fabric_otp_apb_wdata_i11;
+    input fabric_otp_apb_wdata_i12;
+    input fabric_otp_apb_wdata_i13;
+    input fabric_otp_apb_wdata_i14;
+    input fabric_otp_apb_wdata_i15;
+    input fabric_otp_apb_wdata_i16;
+    input fabric_otp_apb_wdata_i17;
+    input fabric_otp_apb_wdata_i18;
+    input fabric_otp_apb_wdata_i19;
+    input fabric_otp_apb_wdata_i2;
+    input fabric_otp_apb_wdata_i20;
+    input fabric_otp_apb_wdata_i21;
+    input fabric_otp_apb_wdata_i22;
+    input fabric_otp_apb_wdata_i23;
+    input fabric_otp_apb_wdata_i24;
+    input fabric_otp_apb_wdata_i25;
+    input fabric_otp_apb_wdata_i26;
+    input fabric_otp_apb_wdata_i27;
+    input fabric_otp_apb_wdata_i28;
+    input fabric_otp_apb_wdata_i29;
+    input fabric_otp_apb_wdata_i3;
+    input fabric_otp_apb_wdata_i30;
+    input fabric_otp_apb_wdata_i31;
+    input fabric_otp_apb_wdata_i32;
+    input fabric_otp_apb_wdata_i4;
+    input fabric_otp_apb_wdata_i5;
+    input fabric_otp_apb_wdata_i6;
+    input fabric_otp_apb_wdata_i7;
+    input fabric_otp_apb_wdata_i8;
+    input fabric_otp_apb_wdata_i9;
+    input fabric_otp_apb_write_i;
+    input fabric_otp_cfg_clk_fab_en_i;
+    input fabric_otp_cfg_clk_otpm_disable_i;
+    input fabric_otp_cfg_fabric_apb_en_i;
+    input fabric_otp_cfg_loader_read_en_i;
+    input fabric_otp_cfg_loader_write_en_i;
+    input fabric_otp_rstn_i;
+    output fabric_otp_security_ack_o;
+    output fabric_otp_security_bist_bad_o;
+    output fabric_otp_security_bist_end1_o;
+    output fabric_otp_security_bist_end2_o;
+    output fabric_otp_security_bist_fail1_o1;
+    output fabric_otp_security_bist_fail1_o2;
+    output fabric_otp_security_bist_fail1_o3;
+    output fabric_otp_security_bist_fail1_o4;
+    output fabric_otp_security_bist_fail1_o5;
+    output fabric_otp_security_bist_fail1_o6;
+    output fabric_otp_security_bist_fail1_o7;
+    output fabric_otp_security_bist_fail1_o8;
+    output fabric_otp_security_bist_fail2_o1;
+    output fabric_otp_security_bist_fail2_o2;
+    output fabric_otp_security_bist_fail2_o3;
+    output fabric_otp_security_bist_fail2_o4;
+    output fabric_otp_security_bist_fail2_o5;
+    output fabric_otp_security_bist_fail2_o6;
+    output fabric_otp_security_bist_fail2_o7;
+    input fabric_otp_security_bistmode_i;
+    input fabric_otp_security_force_pdn1_i;
+    input fabric_otp_security_rbact1_i;
+    input fabric_otp_security_rbact2_i;
+    input fabric_otp_security_scanenable_i;
+    input fabric_otp_security_scanin_i1;
+    input fabric_otp_security_scanin_i2;
+    input fabric_otp_security_scanin_i3;
+    input fabric_otp_security_scanin_i4;
+    input fabric_otp_security_scanin_i5;
+    output fabric_otp_security_scanout_o1;
+    output fabric_otp_security_scanout_o2;
+    output fabric_otp_security_scanout_o3;
+    output fabric_otp_security_scanout_o4;
+    output fabric_otp_security_scanout_o5;
+    input fabric_otp_security_testmode_i;
+    output fabric_otp_user_ack_o;
+    input fabric_otp_user_add_i1;
+    input fabric_otp_user_add_i2;
+    input fabric_otp_user_add_i3;
+    input fabric_otp_user_add_i4;
+    input fabric_otp_user_add_i5;
+    input fabric_otp_user_add_i6;
+    input fabric_otp_user_add_i7;
+    output fabric_otp_user_bbad_o;
+    output fabric_otp_user_bend1_o;
+    output fabric_otp_user_bend2_o;
+    output fabric_otp_user_bist1fail_o1;
+    output fabric_otp_user_bist1fail_o2;
+    output fabric_otp_user_bist1fail_o3;
+    output fabric_otp_user_bist1fail_o4;
+    output fabric_otp_user_bist1fail_o5;
+    output fabric_otp_user_bist1fail_o6;
+    output fabric_otp_user_bist1fail_o7;
+    output fabric_otp_user_bist1fail_o8;
+    output fabric_otp_user_bist2fail_o1;
+    output fabric_otp_user_bist2fail_o2;
+    output fabric_otp_user_bist2fail_o3;
+    output fabric_otp_user_bist2fail_o4;
+    output fabric_otp_user_bist2fail_o5;
+    output fabric_otp_user_bist2fail_o6;
+    output fabric_otp_user_bist2fail_o7;
+    input fabric_otp_user_bistmode_i;
+    output fabric_otp_user_calibrated_o;
+    input fabric_otp_user_configreg_i1;
+    input fabric_otp_user_configreg_i10;
+    input fabric_otp_user_configreg_i11;
+    input fabric_otp_user_configreg_i12;
+    input fabric_otp_user_configreg_i13;
+    input fabric_otp_user_configreg_i14;
+    input fabric_otp_user_configreg_i15;
+    input fabric_otp_user_configreg_i16;
+    input fabric_otp_user_configreg_i17;
+    input fabric_otp_user_configreg_i18;
+    input fabric_otp_user_configreg_i19;
+    input fabric_otp_user_configreg_i2;
+    input fabric_otp_user_configreg_i20;
+    input fabric_otp_user_configreg_i21;
+    input fabric_otp_user_configreg_i22;
+    input fabric_otp_user_configreg_i23;
+    input fabric_otp_user_configreg_i24;
+    input fabric_otp_user_configreg_i25;
+    input fabric_otp_user_configreg_i26;
+    input fabric_otp_user_configreg_i27;
+    input fabric_otp_user_configreg_i28;
+    input fabric_otp_user_configreg_i29;
+    input fabric_otp_user_configreg_i3;
+    input fabric_otp_user_configreg_i30;
+    input fabric_otp_user_configreg_i31;
+    input fabric_otp_user_configreg_i32;
+    input fabric_otp_user_configreg_i4;
+    input fabric_otp_user_configreg_i5;
+    input fabric_otp_user_configreg_i6;
+    input fabric_otp_user_configreg_i7;
+    input fabric_otp_user_configreg_i8;
+    input fabric_otp_user_configreg_i9;
+    output fabric_otp_user_ded_o;
+    input fabric_otp_user_din_i1;
+    input fabric_otp_user_din_i10;
+    input fabric_otp_user_din_i11;
+    input fabric_otp_user_din_i12;
+    input fabric_otp_user_din_i13;
+    input fabric_otp_user_din_i14;
+    input fabric_otp_user_din_i15;
+    input fabric_otp_user_din_i16;
+    input fabric_otp_user_din_i17;
+    input fabric_otp_user_din_i18;
+    input fabric_otp_user_din_i19;
+    input fabric_otp_user_din_i2;
+    input fabric_otp_user_din_i20;
+    input fabric_otp_user_din_i21;
+    input fabric_otp_user_din_i22;
+    input fabric_otp_user_din_i23;
+    input fabric_otp_user_din_i24;
+    input fabric_otp_user_din_i25;
+    input fabric_otp_user_din_i26;
+    input fabric_otp_user_din_i27;
+    input fabric_otp_user_din_i28;
+    input fabric_otp_user_din_i29;
+    input fabric_otp_user_din_i3;
+    input fabric_otp_user_din_i30;
+    input fabric_otp_user_din_i31;
+    input fabric_otp_user_din_i32;
+    input fabric_otp_user_din_i33;
+    input fabric_otp_user_din_i34;
+    input fabric_otp_user_din_i35;
+    input fabric_otp_user_din_i36;
+    input fabric_otp_user_din_i37;
+    input fabric_otp_user_din_i38;
+    input fabric_otp_user_din_i39;
+    input fabric_otp_user_din_i4;
+    input fabric_otp_user_din_i5;
+    input fabric_otp_user_din_i6;
+    input fabric_otp_user_din_i7;
+    input fabric_otp_user_din_i8;
+    input fabric_otp_user_din_i9;
+    input fabric_otp_user_disturbcheck_i;
+    output fabric_otp_user_disturbed_o;
+    output fabric_otp_user_dout_o1;
+    output fabric_otp_user_dout_o10;
+    output fabric_otp_user_dout_o11;
+    output fabric_otp_user_dout_o12;
+    output fabric_otp_user_dout_o13;
+    output fabric_otp_user_dout_o14;
+    output fabric_otp_user_dout_o15;
+    output fabric_otp_user_dout_o16;
+    output fabric_otp_user_dout_o17;
+    output fabric_otp_user_dout_o18;
+    output fabric_otp_user_dout_o19;
+    output fabric_otp_user_dout_o2;
+    output fabric_otp_user_dout_o20;
+    output fabric_otp_user_dout_o21;
+    output fabric_otp_user_dout_o22;
+    output fabric_otp_user_dout_o23;
+    output fabric_otp_user_dout_o24;
+    output fabric_otp_user_dout_o25;
+    output fabric_otp_user_dout_o26;
+    output fabric_otp_user_dout_o27;
+    output fabric_otp_user_dout_o28;
+    output fabric_otp_user_dout_o29;
+    output fabric_otp_user_dout_o3;
+    output fabric_otp_user_dout_o30;
+    output fabric_otp_user_dout_o31;
+    output fabric_otp_user_dout_o32;
+    output fabric_otp_user_dout_o33;
+    output fabric_otp_user_dout_o34;
+    output fabric_otp_user_dout_o35;
+    output fabric_otp_user_dout_o36;
+    output fabric_otp_user_dout_o37;
+    output fabric_otp_user_dout_o38;
+    output fabric_otp_user_dout_o39;
+    output fabric_otp_user_dout_o4;
+    output fabric_otp_user_dout_o40;
+    output fabric_otp_user_dout_o41;
+    output fabric_otp_user_dout_o5;
+    output fabric_otp_user_dout_o6;
+    output fabric_otp_user_dout_o7;
+    output fabric_otp_user_dout_o8;
+    output fabric_otp_user_dout_o9;
+    input fabric_otp_user_eccbypass_i;
+    output fabric_otp_user_flagstate_o1;
+    output fabric_otp_user_flagstate_o2;
+    output fabric_otp_user_flagstate_o3;
+    output fabric_otp_user_flagstate_o4;
+    output fabric_otp_user_locked_o;
+    input fabric_otp_user_pdn_i;
+    input fabric_otp_user_prgwidth_i1;
+    input fabric_otp_user_prgwidth_i2;
+    input fabric_otp_user_prgwidth_i3;
+    input fabric_otp_user_prog_i;
+    output fabric_otp_user_progfail_o;
+    output fabric_otp_user_pwok_o;
+    input fabric_otp_user_rbact1_i;
+    input fabric_otp_user_rbact2_i;
+    input fabric_otp_user_read_i;
+    input fabric_otp_user_redbypass_i;
+    output fabric_otp_user_sec_o;
+    output fabric_otp_user_startword_o1;
+    output fabric_otp_user_startword_o10;
+    output fabric_otp_user_startword_o11;
+    output fabric_otp_user_startword_o12;
+    output fabric_otp_user_startword_o13;
+    output fabric_otp_user_startword_o14;
+    output fabric_otp_user_startword_o15;
+    output fabric_otp_user_startword_o16;
+    output fabric_otp_user_startword_o2;
+    output fabric_otp_user_startword_o3;
+    output fabric_otp_user_startword_o4;
+    output fabric_otp_user_startword_o5;
+    output fabric_otp_user_startword_o6;
+    output fabric_otp_user_startword_o7;
+    output fabric_otp_user_startword_o8;
+    output fabric_otp_user_startword_o9;
+    input fabric_otp_user_suppadd_i;
+    input fabric_otp_user_tm_i;
+    input fabric_otp_user_tst_scanenable_i;
+    input fabric_otp_user_tst_scanin_i1;
+    input fabric_otp_user_tst_scanin_i2;
+    input fabric_otp_user_tst_scanin_i3;
+    input fabric_otp_user_tst_scanin_i4;
+    input fabric_otp_user_tst_scanin_i5;
+    output fabric_otp_user_tst_scanout_o1;
+    output fabric_otp_user_tst_scanout_o2;
+    output fabric_otp_user_tst_scanout_o3;
+    output fabric_otp_user_tst_scanout_o4;
+    output fabric_otp_user_tst_scanout_o5;
+    output fabric_otp_user_wlromout_o1;
+    output fabric_otp_user_wlromout_o10;
+    output fabric_otp_user_wlromout_o2;
+    output fabric_otp_user_wlromout_o3;
+    output fabric_otp_user_wlromout_o4;
+    output fabric_otp_user_wlromout_o5;
+    output fabric_otp_user_wlromout_o6;
+    output fabric_otp_user_wlromout_o7;
+    output fabric_otp_user_wlromout_o8;
+    output fabric_otp_user_wlromout_o9;
+    input fabric_otp_user_wordlock_i;
+    input fabric_parusr_cs_i;
+    input fabric_parusr_data_i1;
+    input fabric_parusr_data_i10;
+    input fabric_parusr_data_i11;
+    input fabric_parusr_data_i12;
+    input fabric_parusr_data_i13;
+    input fabric_parusr_data_i14;
+    input fabric_parusr_data_i15;
+    input fabric_parusr_data_i16;
+    input fabric_parusr_data_i2;
+    input fabric_parusr_data_i3;
+    input fabric_parusr_data_i4;
+    input fabric_parusr_data_i5;
+    input fabric_parusr_data_i6;
+    input fabric_parusr_data_i7;
+    input fabric_parusr_data_i8;
+    input fabric_parusr_data_i9;
+    output fabric_parusr_data_o1;
+    output fabric_parusr_data_o10;
+    output fabric_parusr_data_o11;
+    output fabric_parusr_data_o12;
+    output fabric_parusr_data_o13;
+    output fabric_parusr_data_o14;
+    output fabric_parusr_data_o15;
+    output fabric_parusr_data_o16;
+    output fabric_parusr_data_o2;
+    output fabric_parusr_data_o3;
+    output fabric_parusr_data_o4;
+    output fabric_parusr_data_o5;
+    output fabric_parusr_data_o6;
+    output fabric_parusr_data_o7;
+    output fabric_parusr_data_o8;
+    output fabric_parusr_data_o9;
+    output fabric_parusr_data_val_o;
+    input fabric_parusr_type_i1;
+    input fabric_parusr_type_i2;
+    input fabric_pd_active_i1;
+    input fabric_pd_active_i10;
+    input fabric_pd_active_i11;
+    input fabric_pd_active_i12;
+    input fabric_pd_active_i13;
+    input fabric_pd_active_i14;
+    input fabric_pd_active_i15;
+    input fabric_pd_active_i16;
+    input fabric_pd_active_i17;
+    input fabric_pd_active_i18;
+    input fabric_pd_active_i19;
+    input fabric_pd_active_i2;
+    input fabric_pd_active_i20;
+    input fabric_pd_active_i21;
+    input fabric_pd_active_i22;
+    input fabric_pd_active_i23;
+    input fabric_pd_active_i24;
+    input fabric_pd_active_i3;
+    input fabric_pd_active_i4;
+    input fabric_pd_active_i5;
+    input fabric_pd_active_i6;
+    input fabric_pd_active_i7;
+    input fabric_pd_active_i8;
+    input fabric_pd_active_i9;
+    output fabric_pd_ready_o1;
+    output fabric_pd_ready_o10;
+    output fabric_pd_ready_o11;
+    output fabric_pd_ready_o12;
+    output fabric_pd_ready_o13;
+    output fabric_pd_ready_o14;
+    output fabric_pd_ready_o15;
+    output fabric_pd_ready_o16;
+    output fabric_pd_ready_o17;
+    output fabric_pd_ready_o18;
+    output fabric_pd_ready_o19;
+    output fabric_pd_ready_o2;
+    output fabric_pd_ready_o20;
+    output fabric_pd_ready_o21;
+    output fabric_pd_ready_o22;
+    output fabric_pd_ready_o23;
+    output fabric_pd_ready_o24;
+    output fabric_pd_ready_o3;
+    output fabric_pd_ready_o4;
+    output fabric_pd_ready_o5;
+    output fabric_pd_ready_o6;
+    output fabric_pd_ready_o7;
+    output fabric_pd_ready_o8;
+    output fabric_pd_ready_o9;
+    input fabric_shift_en_i1;
+    input fabric_shift_en_i10;
+    input fabric_shift_en_i11;
+    input fabric_shift_en_i12;
+    input fabric_shift_en_i13;
+    input fabric_shift_en_i14;
+    input fabric_shift_en_i15;
+    input fabric_shift_en_i16;
+    input fabric_shift_en_i17;
+    input fabric_shift_en_i18;
+    input fabric_shift_en_i19;
+    input fabric_shift_en_i2;
+    input fabric_shift_en_i20;
+    input fabric_shift_en_i21;
+    input fabric_shift_en_i22;
+    input fabric_shift_en_i23;
+    input fabric_shift_en_i24;
+    input fabric_shift_en_i3;
+    input fabric_shift_en_i4;
+    input fabric_shift_en_i5;
+    input fabric_shift_en_i6;
+    input fabric_shift_en_i7;
+    input fabric_shift_en_i8;
+    input fabric_shift_en_i9;
+    output fabric_shift_en_to_bist_o1;
+    output fabric_shift_en_to_bist_o10;
+    output fabric_shift_en_to_bist_o11;
+    output fabric_shift_en_to_bist_o12;
+    output fabric_shift_en_to_bist_o13;
+    output fabric_shift_en_to_bist_o14;
+    output fabric_shift_en_to_bist_o15;
+    output fabric_shift_en_to_bist_o16;
+    output fabric_shift_en_to_bist_o17;
+    output fabric_shift_en_to_bist_o18;
+    output fabric_shift_en_to_bist_o19;
+    output fabric_shift_en_to_bist_o2;
+    output fabric_shift_en_to_bist_o20;
+    output fabric_shift_en_to_bist_o21;
+    output fabric_shift_en_to_bist_o22;
+    output fabric_shift_en_to_bist_o23;
+    output fabric_shift_en_to_bist_o24;
+    output fabric_shift_en_to_bist_o3;
+    output fabric_shift_en_to_bist_o4;
+    output fabric_shift_en_to_bist_o5;
+    output fabric_shift_en_to_bist_o6;
+    output fabric_shift_en_to_bist_o7;
+    output fabric_shift_en_to_bist_o8;
+    output fabric_shift_en_to_bist_o9;
+    input fabric_sif_load_en_i1;
+    input fabric_sif_load_en_i10;
+    input fabric_sif_load_en_i11;
+    input fabric_sif_load_en_i12;
+    input fabric_sif_load_en_i13;
+    input fabric_sif_load_en_i14;
+    input fabric_sif_load_en_i15;
+    input fabric_sif_load_en_i16;
+    input fabric_sif_load_en_i17;
+    input fabric_sif_load_en_i18;
+    input fabric_sif_load_en_i19;
+    input fabric_sif_load_en_i2;
+    input fabric_sif_load_en_i20;
+    input fabric_sif_load_en_i21;
+    input fabric_sif_load_en_i22;
+    input fabric_sif_load_en_i23;
+    input fabric_sif_load_en_i24;
+    input fabric_sif_load_en_i3;
+    input fabric_sif_load_en_i4;
+    input fabric_sif_load_en_i5;
+    input fabric_sif_load_en_i6;
+    input fabric_sif_load_en_i7;
+    input fabric_sif_load_en_i8;
+    input fabric_sif_load_en_i9;
+    output fabric_sif_load_en_to_bist_o1;
+    output fabric_sif_load_en_to_bist_o10;
+    output fabric_sif_load_en_to_bist_o11;
+    output fabric_sif_load_en_to_bist_o12;
+    output fabric_sif_load_en_to_bist_o13;
+    output fabric_sif_load_en_to_bist_o14;
+    output fabric_sif_load_en_to_bist_o15;
+    output fabric_sif_load_en_to_bist_o16;
+    output fabric_sif_load_en_to_bist_o17;
+    output fabric_sif_load_en_to_bist_o18;
+    output fabric_sif_load_en_to_bist_o19;
+    output fabric_sif_load_en_to_bist_o2;
+    output fabric_sif_load_en_to_bist_o20;
+    output fabric_sif_load_en_to_bist_o21;
+    output fabric_sif_load_en_to_bist_o22;
+    output fabric_sif_load_en_to_bist_o23;
+    output fabric_sif_load_en_to_bist_o24;
+    output fabric_sif_load_en_to_bist_o3;
+    output fabric_sif_load_en_to_bist_o4;
+    output fabric_sif_load_en_to_bist_o5;
+    output fabric_sif_load_en_to_bist_o6;
+    output fabric_sif_load_en_to_bist_o7;
+    output fabric_sif_load_en_to_bist_o8;
+    output fabric_sif_load_en_to_bist_o9;
+    input fabric_sif_reg_en_i1;
+    input fabric_sif_reg_en_i10;
+    input fabric_sif_reg_en_i100;
+    input fabric_sif_reg_en_i101;
+    input fabric_sif_reg_en_i102;
+    input fabric_sif_reg_en_i103;
+    input fabric_sif_reg_en_i104;
+    input fabric_sif_reg_en_i105;
+    input fabric_sif_reg_en_i106;
+    input fabric_sif_reg_en_i107;
+    input fabric_sif_reg_en_i108;
+    input fabric_sif_reg_en_i109;
+    input fabric_sif_reg_en_i11;
+    input fabric_sif_reg_en_i110;
+    input fabric_sif_reg_en_i111;
+    input fabric_sif_reg_en_i112;
+    input fabric_sif_reg_en_i113;
+    input fabric_sif_reg_en_i114;
+    input fabric_sif_reg_en_i115;
+    input fabric_sif_reg_en_i116;
+    input fabric_sif_reg_en_i117;
+    input fabric_sif_reg_en_i118;
+    input fabric_sif_reg_en_i119;
+    input fabric_sif_reg_en_i12;
+    input fabric_sif_reg_en_i120;
+    input fabric_sif_reg_en_i13;
+    input fabric_sif_reg_en_i14;
+    input fabric_sif_reg_en_i15;
+    input fabric_sif_reg_en_i16;
+    input fabric_sif_reg_en_i17;
+    input fabric_sif_reg_en_i18;
+    input fabric_sif_reg_en_i19;
+    input fabric_sif_reg_en_i2;
+    input fabric_sif_reg_en_i20;
+    input fabric_sif_reg_en_i21;
+    input fabric_sif_reg_en_i22;
+    input fabric_sif_reg_en_i23;
+    input fabric_sif_reg_en_i24;
+    input fabric_sif_reg_en_i25;
+    input fabric_sif_reg_en_i26;
+    input fabric_sif_reg_en_i27;
+    input fabric_sif_reg_en_i28;
+    input fabric_sif_reg_en_i29;
+    input fabric_sif_reg_en_i3;
+    input fabric_sif_reg_en_i30;
+    input fabric_sif_reg_en_i31;
+    input fabric_sif_reg_en_i32;
+    input fabric_sif_reg_en_i33;
+    input fabric_sif_reg_en_i34;
+    input fabric_sif_reg_en_i35;
+    input fabric_sif_reg_en_i36;
+    input fabric_sif_reg_en_i37;
+    input fabric_sif_reg_en_i38;
+    input fabric_sif_reg_en_i39;
+    input fabric_sif_reg_en_i4;
+    input fabric_sif_reg_en_i40;
+    input fabric_sif_reg_en_i41;
+    input fabric_sif_reg_en_i42;
+    input fabric_sif_reg_en_i43;
+    input fabric_sif_reg_en_i44;
+    input fabric_sif_reg_en_i45;
+    input fabric_sif_reg_en_i46;
+    input fabric_sif_reg_en_i47;
+    input fabric_sif_reg_en_i48;
+    input fabric_sif_reg_en_i49;
+    input fabric_sif_reg_en_i5;
+    input fabric_sif_reg_en_i50;
+    input fabric_sif_reg_en_i51;
+    input fabric_sif_reg_en_i52;
+    input fabric_sif_reg_en_i53;
+    input fabric_sif_reg_en_i54;
+    input fabric_sif_reg_en_i55;
+    input fabric_sif_reg_en_i56;
+    input fabric_sif_reg_en_i57;
+    input fabric_sif_reg_en_i58;
+    input fabric_sif_reg_en_i59;
+    input fabric_sif_reg_en_i6;
+    input fabric_sif_reg_en_i60;
+    input fabric_sif_reg_en_i61;
+    input fabric_sif_reg_en_i62;
+    input fabric_sif_reg_en_i63;
+    input fabric_sif_reg_en_i64;
+    input fabric_sif_reg_en_i65;
+    input fabric_sif_reg_en_i66;
+    input fabric_sif_reg_en_i67;
+    input fabric_sif_reg_en_i68;
+    input fabric_sif_reg_en_i69;
+    input fabric_sif_reg_en_i7;
+    input fabric_sif_reg_en_i70;
+    input fabric_sif_reg_en_i71;
+    input fabric_sif_reg_en_i72;
+    input fabric_sif_reg_en_i73;
+    input fabric_sif_reg_en_i74;
+    input fabric_sif_reg_en_i75;
+    input fabric_sif_reg_en_i76;
+    input fabric_sif_reg_en_i77;
+    input fabric_sif_reg_en_i78;
+    input fabric_sif_reg_en_i79;
+    input fabric_sif_reg_en_i8;
+    input fabric_sif_reg_en_i80;
+    input fabric_sif_reg_en_i81;
+    input fabric_sif_reg_en_i82;
+    input fabric_sif_reg_en_i83;
+    input fabric_sif_reg_en_i84;
+    input fabric_sif_reg_en_i85;
+    input fabric_sif_reg_en_i86;
+    input fabric_sif_reg_en_i87;
+    input fabric_sif_reg_en_i88;
+    input fabric_sif_reg_en_i89;
+    input fabric_sif_reg_en_i9;
+    input fabric_sif_reg_en_i90;
+    input fabric_sif_reg_en_i91;
+    input fabric_sif_reg_en_i92;
+    input fabric_sif_reg_en_i93;
+    input fabric_sif_reg_en_i94;
+    input fabric_sif_reg_en_i95;
+    input fabric_sif_reg_en_i96;
+    input fabric_sif_reg_en_i97;
+    input fabric_sif_reg_en_i98;
+    input fabric_sif_reg_en_i99;
+    output fabric_sif_reg_en_to_bist_o1;
+    output fabric_sif_reg_en_to_bist_o10;
+    output fabric_sif_reg_en_to_bist_o100;
+    output fabric_sif_reg_en_to_bist_o101;
+    output fabric_sif_reg_en_to_bist_o102;
+    output fabric_sif_reg_en_to_bist_o103;
+    output fabric_sif_reg_en_to_bist_o104;
+    output fabric_sif_reg_en_to_bist_o105;
+    output fabric_sif_reg_en_to_bist_o106;
+    output fabric_sif_reg_en_to_bist_o107;
+    output fabric_sif_reg_en_to_bist_o108;
+    output fabric_sif_reg_en_to_bist_o109;
+    output fabric_sif_reg_en_to_bist_o11;
+    output fabric_sif_reg_en_to_bist_o110;
+    output fabric_sif_reg_en_to_bist_o111;
+    output fabric_sif_reg_en_to_bist_o112;
+    output fabric_sif_reg_en_to_bist_o113;
+    output fabric_sif_reg_en_to_bist_o114;
+    output fabric_sif_reg_en_to_bist_o115;
+    output fabric_sif_reg_en_to_bist_o116;
+    output fabric_sif_reg_en_to_bist_o117;
+    output fabric_sif_reg_en_to_bist_o118;
+    output fabric_sif_reg_en_to_bist_o119;
+    output fabric_sif_reg_en_to_bist_o12;
+    output fabric_sif_reg_en_to_bist_o120;
+    output fabric_sif_reg_en_to_bist_o13;
+    output fabric_sif_reg_en_to_bist_o14;
+    output fabric_sif_reg_en_to_bist_o15;
+    output fabric_sif_reg_en_to_bist_o16;
+    output fabric_sif_reg_en_to_bist_o17;
+    output fabric_sif_reg_en_to_bist_o18;
+    output fabric_sif_reg_en_to_bist_o19;
+    output fabric_sif_reg_en_to_bist_o2;
+    output fabric_sif_reg_en_to_bist_o20;
+    output fabric_sif_reg_en_to_bist_o21;
+    output fabric_sif_reg_en_to_bist_o22;
+    output fabric_sif_reg_en_to_bist_o23;
+    output fabric_sif_reg_en_to_bist_o24;
+    output fabric_sif_reg_en_to_bist_o25;
+    output fabric_sif_reg_en_to_bist_o26;
+    output fabric_sif_reg_en_to_bist_o27;
+    output fabric_sif_reg_en_to_bist_o28;
+    output fabric_sif_reg_en_to_bist_o29;
+    output fabric_sif_reg_en_to_bist_o3;
+    output fabric_sif_reg_en_to_bist_o30;
+    output fabric_sif_reg_en_to_bist_o31;
+    output fabric_sif_reg_en_to_bist_o32;
+    output fabric_sif_reg_en_to_bist_o33;
+    output fabric_sif_reg_en_to_bist_o34;
+    output fabric_sif_reg_en_to_bist_o35;
+    output fabric_sif_reg_en_to_bist_o36;
+    output fabric_sif_reg_en_to_bist_o37;
+    output fabric_sif_reg_en_to_bist_o38;
+    output fabric_sif_reg_en_to_bist_o39;
+    output fabric_sif_reg_en_to_bist_o4;
+    output fabric_sif_reg_en_to_bist_o40;
+    output fabric_sif_reg_en_to_bist_o41;
+    output fabric_sif_reg_en_to_bist_o42;
+    output fabric_sif_reg_en_to_bist_o43;
+    output fabric_sif_reg_en_to_bist_o44;
+    output fabric_sif_reg_en_to_bist_o45;
+    output fabric_sif_reg_en_to_bist_o46;
+    output fabric_sif_reg_en_to_bist_o47;
+    output fabric_sif_reg_en_to_bist_o48;
+    output fabric_sif_reg_en_to_bist_o49;
+    output fabric_sif_reg_en_to_bist_o5;
+    output fabric_sif_reg_en_to_bist_o50;
+    output fabric_sif_reg_en_to_bist_o51;
+    output fabric_sif_reg_en_to_bist_o52;
+    output fabric_sif_reg_en_to_bist_o53;
+    output fabric_sif_reg_en_to_bist_o54;
+    output fabric_sif_reg_en_to_bist_o55;
+    output fabric_sif_reg_en_to_bist_o56;
+    output fabric_sif_reg_en_to_bist_o57;
+    output fabric_sif_reg_en_to_bist_o58;
+    output fabric_sif_reg_en_to_bist_o59;
+    output fabric_sif_reg_en_to_bist_o6;
+    output fabric_sif_reg_en_to_bist_o60;
+    output fabric_sif_reg_en_to_bist_o61;
+    output fabric_sif_reg_en_to_bist_o62;
+    output fabric_sif_reg_en_to_bist_o63;
+    output fabric_sif_reg_en_to_bist_o64;
+    output fabric_sif_reg_en_to_bist_o65;
+    output fabric_sif_reg_en_to_bist_o66;
+    output fabric_sif_reg_en_to_bist_o67;
+    output fabric_sif_reg_en_to_bist_o68;
+    output fabric_sif_reg_en_to_bist_o69;
+    output fabric_sif_reg_en_to_bist_o7;
+    output fabric_sif_reg_en_to_bist_o70;
+    output fabric_sif_reg_en_to_bist_o71;
+    output fabric_sif_reg_en_to_bist_o72;
+    output fabric_sif_reg_en_to_bist_o73;
+    output fabric_sif_reg_en_to_bist_o74;
+    output fabric_sif_reg_en_to_bist_o75;
+    output fabric_sif_reg_en_to_bist_o76;
+    output fabric_sif_reg_en_to_bist_o77;
+    output fabric_sif_reg_en_to_bist_o78;
+    output fabric_sif_reg_en_to_bist_o79;
+    output fabric_sif_reg_en_to_bist_o8;
+    output fabric_sif_reg_en_to_bist_o80;
+    output fabric_sif_reg_en_to_bist_o81;
+    output fabric_sif_reg_en_to_bist_o82;
+    output fabric_sif_reg_en_to_bist_o83;
+    output fabric_sif_reg_en_to_bist_o84;
+    output fabric_sif_reg_en_to_bist_o85;
+    output fabric_sif_reg_en_to_bist_o86;
+    output fabric_sif_reg_en_to_bist_o87;
+    output fabric_sif_reg_en_to_bist_o88;
+    output fabric_sif_reg_en_to_bist_o89;
+    output fabric_sif_reg_en_to_bist_o9;
+    output fabric_sif_reg_en_to_bist_o90;
+    output fabric_sif_reg_en_to_bist_o91;
+    output fabric_sif_reg_en_to_bist_o92;
+    output fabric_sif_reg_en_to_bist_o93;
+    output fabric_sif_reg_en_to_bist_o94;
+    output fabric_sif_reg_en_to_bist_o95;
+    output fabric_sif_reg_en_to_bist_o96;
+    output fabric_sif_reg_en_to_bist_o97;
+    output fabric_sif_reg_en_to_bist_o98;
+    output fabric_sif_reg_en_to_bist_o99;
+    input fabric_sif_update_en_i1;
+    input fabric_sif_update_en_i10;
+    input fabric_sif_update_en_i11;
+    input fabric_sif_update_en_i12;
+    input fabric_sif_update_en_i13;
+    input fabric_sif_update_en_i14;
+    input fabric_sif_update_en_i15;
+    input fabric_sif_update_en_i16;
+    input fabric_sif_update_en_i17;
+    input fabric_sif_update_en_i18;
+    input fabric_sif_update_en_i19;
+    input fabric_sif_update_en_i2;
+    input fabric_sif_update_en_i20;
+    input fabric_sif_update_en_i21;
+    input fabric_sif_update_en_i22;
+    input fabric_sif_update_en_i23;
+    input fabric_sif_update_en_i24;
+    input fabric_sif_update_en_i3;
+    input fabric_sif_update_en_i4;
+    input fabric_sif_update_en_i5;
+    input fabric_sif_update_en_i6;
+    input fabric_sif_update_en_i7;
+    input fabric_sif_update_en_i8;
+    input fabric_sif_update_en_i9;
+    output fabric_sif_update_en_to_bist_o1;
+    output fabric_sif_update_en_to_bist_o10;
+    output fabric_sif_update_en_to_bist_o11;
+    output fabric_sif_update_en_to_bist_o12;
+    output fabric_sif_update_en_to_bist_o13;
+    output fabric_sif_update_en_to_bist_o14;
+    output fabric_sif_update_en_to_bist_o15;
+    output fabric_sif_update_en_to_bist_o16;
+    output fabric_sif_update_en_to_bist_o17;
+    output fabric_sif_update_en_to_bist_o18;
+    output fabric_sif_update_en_to_bist_o19;
+    output fabric_sif_update_en_to_bist_o2;
+    output fabric_sif_update_en_to_bist_o20;
+    output fabric_sif_update_en_to_bist_o21;
+    output fabric_sif_update_en_to_bist_o22;
+    output fabric_sif_update_en_to_bist_o23;
+    output fabric_sif_update_en_to_bist_o24;
+    output fabric_sif_update_en_to_bist_o3;
+    output fabric_sif_update_en_to_bist_o4;
+    output fabric_sif_update_en_to_bist_o5;
+    output fabric_sif_update_en_to_bist_o6;
+    output fabric_sif_update_en_to_bist_o7;
+    output fabric_sif_update_en_to_bist_o8;
+    output fabric_sif_update_en_to_bist_o9;
+    input fabric_spare_i1;
+    input fabric_spare_i2;
+    input fabric_spare_i3;
+    output fabric_status_cold_start_o;
+    output fabric_system_data_from_mem_bist_o1;
+    output fabric_system_data_from_mem_bist_o10;
+    output fabric_system_data_from_mem_bist_o11;
+    output fabric_system_data_from_mem_bist_o12;
+    output fabric_system_data_from_mem_bist_o13;
+    output fabric_system_data_from_mem_bist_o14;
+    output fabric_system_data_from_mem_bist_o15;
+    output fabric_system_data_from_mem_bist_o16;
+    output fabric_system_data_from_mem_bist_o17;
+    output fabric_system_data_from_mem_bist_o18;
+    output fabric_system_data_from_mem_bist_o19;
+    output fabric_system_data_from_mem_bist_o2;
+    output fabric_system_data_from_mem_bist_o20;
+    output fabric_system_data_from_mem_bist_o21;
+    output fabric_system_data_from_mem_bist_o22;
+    output fabric_system_data_from_mem_bist_o23;
+    output fabric_system_data_from_mem_bist_o24;
+    output fabric_system_data_from_mem_bist_o3;
+    output fabric_system_data_from_mem_bist_o4;
+    output fabric_system_data_from_mem_bist_o5;
+    output fabric_system_data_from_mem_bist_o6;
+    output fabric_system_data_from_mem_bist_o7;
+    output fabric_system_data_from_mem_bist_o8;
+    output fabric_system_data_from_mem_bist_o9;
+    input fabric_system_data_to_mem_bist_i1;
+    input fabric_system_data_to_mem_bist_i10;
+    input fabric_system_data_to_mem_bist_i11;
+    input fabric_system_data_to_mem_bist_i12;
+    input fabric_system_data_to_mem_bist_i13;
+    input fabric_system_data_to_mem_bist_i14;
+    input fabric_system_data_to_mem_bist_i15;
+    input fabric_system_data_to_mem_bist_i16;
+    input fabric_system_data_to_mem_bist_i17;
+    input fabric_system_data_to_mem_bist_i18;
+    input fabric_system_data_to_mem_bist_i19;
+    input fabric_system_data_to_mem_bist_i2;
+    input fabric_system_data_to_mem_bist_i20;
+    input fabric_system_data_to_mem_bist_i21;
+    input fabric_system_data_to_mem_bist_i22;
+    input fabric_system_data_to_mem_bist_i23;
+    input fabric_system_data_to_mem_bist_i24;
+    input fabric_system_data_to_mem_bist_i3;
+    input fabric_system_data_to_mem_bist_i4;
+    input fabric_system_data_to_mem_bist_i5;
+    input fabric_system_data_to_mem_bist_i6;
+    input fabric_system_data_to_mem_bist_i7;
+    input fabric_system_data_to_mem_bist_i8;
+    input fabric_system_data_to_mem_bist_i9;
+    output fabric_system_dataready_o;
+    input fabric_tst_atpg_mrepair_i;
+    input fabric_user_data_i1;
+    input fabric_user_data_i10;
+    input fabric_user_data_i11;
+    input fabric_user_data_i12;
+    input fabric_user_data_i13;
+    input fabric_user_data_i14;
+    input fabric_user_data_i15;
+    input fabric_user_data_i16;
+    input fabric_user_data_i17;
+    input fabric_user_data_i18;
+    input fabric_user_data_i19;
+    input fabric_user_data_i2;
+    input fabric_user_data_i20;
+    input fabric_user_data_i21;
+    input fabric_user_data_i22;
+    input fabric_user_data_i23;
+    input fabric_user_data_i24;
+    input fabric_user_data_i25;
+    input fabric_user_data_i26;
+    input fabric_user_data_i27;
+    input fabric_user_data_i28;
+    input fabric_user_data_i29;
+    input fabric_user_data_i3;
+    input fabric_user_data_i30;
+    input fabric_user_data_i31;
+    input fabric_user_data_i32;
+    input fabric_user_data_i4;
+    input fabric_user_data_i5;
+    input fabric_user_data_i6;
+    input fabric_user_data_i7;
+    input fabric_user_data_i8;
+    input fabric_user_data_i9;
+    output fabric_user_data_o1;
+    output fabric_user_data_o10;
+    output fabric_user_data_o11;
+    output fabric_user_data_o12;
+    output fabric_user_data_o13;
+    output fabric_user_data_o14;
+    output fabric_user_data_o15;
+    output fabric_user_data_o16;
+    output fabric_user_data_o17;
+    output fabric_user_data_o18;
+    output fabric_user_data_o19;
+    output fabric_user_data_o2;
+    output fabric_user_data_o20;
+    output fabric_user_data_o21;
+    output fabric_user_data_o22;
+    output fabric_user_data_o23;
+    output fabric_user_data_o24;
+    output fabric_user_data_o25;
+    output fabric_user_data_o26;
+    output fabric_user_data_o27;
+    output fabric_user_data_o28;
+    output fabric_user_data_o29;
+    output fabric_user_data_o3;
+    output fabric_user_data_o30;
+    output fabric_user_data_o31;
+    output fabric_user_data_o32;
+    output fabric_user_data_o4;
+    output fabric_user_data_o5;
+    output fabric_user_data_o6;
+    output fabric_user_data_o7;
+    output fabric_user_data_o8;
+    output fabric_user_data_o9;
+    output fabric_user_read_cycle_o;
+    output fabric_user_write_cycle_o;
+    parameter ahb_config = 0;
+    parameter bsm_config = 0;
+endmodule
+
+(* blackbox *)
+module NX_SERVICE_U_V1_WRAP(fabric_otp_user_tst_scanenable_i, fabric_otp_cfg_loader_read_en_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_scanenable_i, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_user_disturbcheck_i, fabric_mrepair_fuse_read_i, fabric_otp_user_rbact2_i, fabric_mrepair_fuse_eccbypass_i, fabric_otp_user_bistmode_i, fabric_otp_user_tm_i, fabric_otp_rstn_i, fabric_mrepair_fuse_disturbchecked_i, fabric_otp_user_rbact1_i, fabric_mrepair_fuse_redbypass_i, fabric_otp_user_eccbypass_i, fabric_otp_user_redbypass_i, fabric_parusr_cs_i, fabric_mrepair_fuse_rbact2_i, fabric_data_from_system_i, fabric_otp_apb_enable_i
+, fabric_mrepair_fuse_tm_i, fabric_otp_security_rbact2_i, fabric_otp_security_rbact1_i, fabric_otp_cfg_loader_write_en_i, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_prog_i, fabric_otp_user_wordlock_i, fabric_otp_user_prog_i, fabric_otp_user_suppadd_i, fabric_mrepair_fuse_pdn_i, fabric_end_encoding_i, fabric_jtag_tdo_usr2_i, fabric_mrepair_fuse_wordlock_i, fabric_otp_user_read_i, fabric_mrepair_fuse_bistmode_i, fabric_jtag_tdo_usr1_i, fabric_otp_cfg_clk_fab_en_i, fabric_otp_apb_sel_i, fabric_mrepair_fuse_rbact1_i, fabric_otp_cfg_fabric_apb_en_i, fabric_data_shift_en_i
+, fabric_lowskew_i21, fabric_otp_user_pdn_i, fabric_otp_apb_write_i, fabric_otp_security_testmode_i, fabric_tst_atpg_mrepair_i, fabric_mrepair_fuse_tstscanenable_i, fabric_otp_security_bistmode_i, fabric_lowskew_i22, fabric_lowskew_i23, fabric_lowskew_i20, fabric_mrepair_por_i, fabric_mrepair_rst_n_i, fabric_mrepair_initn_i, fabric_mrepair_fuse_bbad_o, fabric_jtag_trst_n_o, fabric_otp_security_bist_end1_o, fabric_parusr_data_val_o, fabric_debug_lock_reg_o, fabric_debug_security_error_read_o, fabric_otp_user_locked_o, fabric_otp_security_bist_bad_o
+, fabric_otp_user_pwok_o, fabric_otp_user_bend2_o, fabric_mrepair_fuse_ded_o, fabric_debug_access_reg_data_ready_o, fabric_debug_otp_reload_err_o, fabric_cfg_fabric_user_unmask_o, fabric_decoder_init_ready_o, fabric_debug_security_boot_done_o, fabric_otp_user_calibrated_o, fabric_jtag_tms_o, fabric_flag_ready_o, fabric_debug_rst_soft_o, fabric_otp_user_ack_o, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_debug_otp_manager_read_otp_o, fabric_otp_user_sec_o, fabric_mrepair_fuse_bend1_o, fabric_otp_user_bbad_o, fabric_user_read_cycle_o, fabric_mrepair_fuse_disturbed_o, fabric_debug_key_correct_o
+, fabric_otp_apb_ready_o, fabric_otp_user_progfail_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_bend2_o, fabric_mrepair_fuse_ack_o, fabric_otp_security_ack_o, fabric_mrepair_fuse_progfail_o, fabric_jtag_tdi_o, fabric_lowskew_o3, fabric_lowskew_o5, fabric_lowskew_o4, fabric_debug_error_o, fabric_jtag_usr2_o, fabric_otp_user_disturbed_o, fabric_flag_trigger_o, fabric_otp_security_bist_end2_o, fabric_mrepair_fuse_locked_o, fabric_user_write_cycle_o, fabric_otp_user_ded_o, fabric_debug_otp_manager_read_done_o, fabric_debug_frame_use_encryption_o
+, fabric_data_to_system_o, fabric_jtag_usr1_o, fabric_otp_user_bend1_o, fabric_mrepair_fuse_ready_o, fabric_mrepair_fuse_calibrated_o, fabric_system_dataready_o, fabric_mrepair_fuse_pwok_o, fabric_lowskew_o6, fabric_cfg_fabric_user_flag_o, fabric_status_cold_start_o, fabric_flag_error_o, fabric_mrepair_mode_i, fabric_mrepair_fuse_add_i, fabric_mrepair_fuse_din_i, fabric_mrepair_fuse_tst_scanin_i, fabric_mrepair_fuse_prgwidth_i, fabric_mrepair_fuse_dout_o, fabric_mrepair_fuse_startword_o, fabric_mrepair_fuse_wlromout_o, fabric_mrepair_fuse_bist1fail_o, fabric_mrepair_fuse_bist2fail_o
+, fabric_mrepair_fuse_tstscanout_o, fabric_mrepair_fuse_flagstate_o, fabric_otp_user_add_i, fabric_otp_user_din_i, fabric_otp_user_prgwidth_i, fabric_otp_user_tst_scanin_i, fabric_otp_user_bist1fail_o, fabric_otp_user_bist2fail_o, fabric_otp_user_dout_o, fabric_otp_user_flagstate_o, fabric_otp_user_startword_o, fabric_otp_user_tst_scanout_o, fabric_otp_user_wlromout_o, fabric_io_in_i, fabric_io_oe_i, fabric_io_out_o, fabric_user_data_i, fabric_user_data_o, fabric_parusr_type_i, fabric_parusr_data_i, fabric_parusr_data_o
+, fabric_direct_data_i, fabric_direct_data_o, fabric_otp_apb_addr_i, fabric_otp_apb_wdata_i, fabric_otp_apb_rdata_o, fabric_otp_security_bist_fail1_o, fabric_otp_security_bist_fail2_o, fabric_otp_security_scanin_i, fabric_otp_security_scanout_o, fabric_debug_lifecycle_o, fabric_debug_fsm_state_o, fabric_debug_direct_permission_write_o, fabric_debug_direct_permission_read_o, fabric_debug_frame_permission_frame_o, fabric_debug_otpmgmt_state_o, fabric_debug_otpapb_state_o, fabric_debug_otpboot_state_o, fabric_debug_cpt_retry_o, fabric_debug_bsec_core_status_o, fabric_debug_otpboot_curr_addr_o, fabric_spare_i
+, fabric_sif_reg_en_i, fabric_data_from_bist_i, fabric_shift_en_i, fabric_ahb_direct_data_i, fabric_pd_active_i, fabric_sif_load_en_i, fabric_mrepair_fuse_configreg_i, fabric_system_data_to_mem_bist_i, fabric_otp_user_configreg_i, fabric_sif_update_en_i, fabric_sif_update_en_to_bist_o, fabric_data_to_bist_o, fabric_ahb_direct_data_o, fabric_global_chip_status_o, fabric_fuse_status_o, fabric_shift_en_to_bist_o, fabric_sif_reg_en_to_bist_o, fabric_system_data_from_mem_bist_o, fabric_chip_status_o, fabric_pd_ready_o, fabric_sif_load_en_to_bist_o
+);
+    input [31:0] fabric_ahb_direct_data_i;
+    output [31:0] fabric_ahb_direct_data_o;
+    output fabric_cfg_fabric_user_flag_o;
+    output fabric_cfg_fabric_user_unmask_o;
+    output [71:0] fabric_chip_status_o;
+    input [23:0] fabric_data_from_bist_i;
+    input fabric_data_from_system_i;
+    input fabric_data_shift_en_i;
+    output [23:0] fabric_data_to_bist_o;
+    output fabric_data_to_system_o;
+    output fabric_debug_access_reg_data_ready_o;
+    output [31:0] fabric_debug_bsec_core_status_o;
+    output [3:0] fabric_debug_cpt_retry_o;
+    output [3:0] fabric_debug_direct_permission_read_o;
+    output [3:0] fabric_debug_direct_permission_write_o;
+    output fabric_debug_error_o;
+    output [3:0] fabric_debug_frame_permission_frame_o;
+    output fabric_debug_frame_use_encryption_o;
+    output [2:0] fabric_debug_fsm_state_o;
+    output fabric_debug_key_correct_o;
+    output [3:0] fabric_debug_lifecycle_o;
+    output fabric_debug_lock_reg_o;
+    output fabric_debug_otp_manager_read_done_o;
+    output fabric_debug_otp_manager_read_otp_o;
+    output fabric_debug_otp_reload_err_o;
+    output [2:0] fabric_debug_otpapb_state_o;
+    output [7:0] fabric_debug_otpboot_curr_addr_o;
+    output [2:0] fabric_debug_otpboot_state_o;
+    output [2:0] fabric_debug_otpmgmt_state_o;
+    output fabric_debug_rst_soft_o;
+    output fabric_debug_security_boot_done_o;
+    output fabric_debug_security_error_read_o;
+    output fabric_decoder_init_ready_o;
+    input [31:0] fabric_direct_data_i;
+    output [31:0] fabric_direct_data_o;
+    input fabric_end_encoding_i;
+    output fabric_flag_error_o;
+    output fabric_flag_ready_o;
+    output fabric_flag_trigger_o;
+    output [2:0] fabric_fuse_status_o;
+    output [2:0] fabric_global_chip_status_o;
+    input [24:0] fabric_io_in_i;
+    input [24:0] fabric_io_oe_i;
+    output [24:0] fabric_io_out_o;
+    output fabric_jtag_tdi_o;
+    input fabric_jtag_tdo_usr1_i;
+    input fabric_jtag_tdo_usr2_i;
+    output fabric_jtag_tms_o;
+    output fabric_jtag_trst_n_o;
+    output fabric_jtag_usr1_o;
+    output fabric_jtag_usr2_o;
+    input fabric_lowskew_i20;
+    input fabric_lowskew_i21;
+    input fabric_lowskew_i22;
+    input fabric_lowskew_i23;
+    output fabric_lowskew_o3;
+    output fabric_lowskew_o4;
+    output fabric_lowskew_o5;
+    output fabric_lowskew_o6;
+    output fabric_mrepair_fuse_ack_o;
+    input [6:0] fabric_mrepair_fuse_add_i;
+    output fabric_mrepair_fuse_bbad_o;
+    output fabric_mrepair_fuse_bend1_o;
+    output fabric_mrepair_fuse_bend2_o;
+    output [7:0] fabric_mrepair_fuse_bist1fail_o;
+    output [6:0] fabric_mrepair_fuse_bist2fail_o;
+    input fabric_mrepair_fuse_bistmode_i;
+    output fabric_mrepair_fuse_calibrated_o;
+    input [31:0] fabric_mrepair_fuse_configreg_i;
+    output fabric_mrepair_fuse_ded_o;
+    input [38:0] fabric_mrepair_fuse_din_i;
+    input fabric_mrepair_fuse_disturbchecked_i;
+    output fabric_mrepair_fuse_disturbed_o;
+    output [40:0] fabric_mrepair_fuse_dout_o;
+    input fabric_mrepair_fuse_eccbypass_i;
+    output [3:0] fabric_mrepair_fuse_flagstate_o;
+    output fabric_mrepair_fuse_locked_o;
+    input fabric_mrepair_fuse_pdn_i;
+    output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o;
+    input [2:0] fabric_mrepair_fuse_prgwidth_i;
+    input fabric_mrepair_fuse_prog_i;
+    output fabric_mrepair_fuse_progfail_o;
+    output fabric_mrepair_fuse_pwok_o;
+    input fabric_mrepair_fuse_rbact1_i;
+    input fabric_mrepair_fuse_rbact2_i;
+    input fabric_mrepair_fuse_read_i;
+    output fabric_mrepair_fuse_ready_o;
+    input fabric_mrepair_fuse_redbypass_i;
+    output fabric_mrepair_fuse_sec_o;
+    output [15:0] fabric_mrepair_fuse_startword_o;
+    input fabric_mrepair_fuse_suppadd_i;
+    input fabric_mrepair_fuse_tm_i;
+    input [4:0] fabric_mrepair_fuse_tst_scanin_i;
+    input fabric_mrepair_fuse_tstscanenable_i;
+    output [4:0] fabric_mrepair_fuse_tstscanout_o;
+    output [9:0] fabric_mrepair_fuse_wlromout_o;
+    input fabric_mrepair_fuse_wordlock_i;
+    input fabric_mrepair_initn_i;
+    input [3:0] fabric_mrepair_mode_i;
+    input fabric_mrepair_por_i;
+    input fabric_mrepair_rst_n_i;
+    input [31:0] fabric_otp_apb_addr_i;
+    input fabric_otp_apb_enable_i;
+    output [31:0] fabric_otp_apb_rdata_o;
+    output fabric_otp_apb_ready_o;
+    input fabric_otp_apb_sel_i;
+    input [31:0] fabric_otp_apb_wdata_i;
+    input fabric_otp_apb_write_i;
+    input fabric_otp_cfg_clk_fab_en_i;
+    input fabric_otp_cfg_clk_otpm_disable_i;
+    input fabric_otp_cfg_fabric_apb_en_i;
+    input fabric_otp_cfg_loader_read_en_i;
+    input fabric_otp_cfg_loader_write_en_i;
+    input fabric_otp_rstn_i;
+    output fabric_otp_security_ack_o;
+    output fabric_otp_security_bist_bad_o;
+    output fabric_otp_security_bist_end1_o;
+    output fabric_otp_security_bist_end2_o;
+    output [7:0] fabric_otp_security_bist_fail1_o;
+    output [6:0] fabric_otp_security_bist_fail2_o;
+    input fabric_otp_security_bistmode_i;
+    input fabric_otp_security_force_pdn1_i;
+    input fabric_otp_security_rbact1_i;
+    input fabric_otp_security_rbact2_i;
+    input fabric_otp_security_scanenable_i;
+    input [4:0] fabric_otp_security_scanin_i;
+    output [4:0] fabric_otp_security_scanout_o;
+    input fabric_otp_security_testmode_i;
+    output fabric_otp_user_ack_o;
+    input [6:0] fabric_otp_user_add_i;
+    output fabric_otp_user_bbad_o;
+    output fabric_otp_user_bend1_o;
+    output fabric_otp_user_bend2_o;
+    output [7:0] fabric_otp_user_bist1fail_o;
+    output [6:0] fabric_otp_user_bist2fail_o;
+    input fabric_otp_user_bistmode_i;
+    output fabric_otp_user_calibrated_o;
+    input [31:0] fabric_otp_user_configreg_i;
+    output fabric_otp_user_ded_o;
+    input [38:0] fabric_otp_user_din_i;
+    input fabric_otp_user_disturbcheck_i;
+    output fabric_otp_user_disturbed_o;
+    output [40:0] fabric_otp_user_dout_o;
+    input fabric_otp_user_eccbypass_i;
+    output [3:0] fabric_otp_user_flagstate_o;
+    output fabric_otp_user_locked_o;
+    input fabric_otp_user_pdn_i;
+    input [2:0] fabric_otp_user_prgwidth_i;
+    input fabric_otp_user_prog_i;
+    output fabric_otp_user_progfail_o;
+    output fabric_otp_user_pwok_o;
+    input fabric_otp_user_rbact1_i;
+    input fabric_otp_user_rbact2_i;
+    input fabric_otp_user_read_i;
+    input fabric_otp_user_redbypass_i;
+    output fabric_otp_user_sec_o;
+    output [15:0] fabric_otp_user_startword_o;
+    input fabric_otp_user_suppadd_i;
+    input fabric_otp_user_tm_i;
+    input fabric_otp_user_tst_scanenable_i;
+    input [4:0] fabric_otp_user_tst_scanin_i;
+    output [4:0] fabric_otp_user_tst_scanout_o;
+    output [9:0] fabric_otp_user_wlromout_o;
+    input fabric_otp_user_wordlock_i;
+    input fabric_parusr_cs_i;
+    input [15:0] fabric_parusr_data_i;
+    output [15:0] fabric_parusr_data_o;
+    output fabric_parusr_data_val_o;
+    input [1:0] fabric_parusr_type_i;
+    input [23:0] fabric_pd_active_i;
+    output [23:0] fabric_pd_ready_o;
+    input [23:0] fabric_shift_en_i;
+    output [23:0] fabric_shift_en_to_bist_o;
+    input [23:0] fabric_sif_load_en_i;
+    output [23:0] fabric_sif_load_en_to_bist_o;
+    input [119:0] fabric_sif_reg_en_i;
+    output [119:0] fabric_sif_reg_en_to_bist_o;
+    input [23:0] fabric_sif_update_en_i;
+    output [23:0] fabric_sif_update_en_to_bist_o;
+    input [2:0] fabric_spare_i;
+    output fabric_status_cold_start_o;
+    output [23:0] fabric_system_data_from_mem_bist_o;
+    input [23:0] fabric_system_data_to_mem_bist_i;
+    output fabric_system_dataready_o;
+    input fabric_tst_atpg_mrepair_i;
+    input [31:0] fabric_user_data_i;
+    output [31:0] fabric_user_data_o;
+    output fabric_user_read_cycle_o;
+    output fabric_user_write_cycle_o;
+    parameter ahb_config = 0;
+    parameter bsm_config = 0;
+endmodule
+
+(* blackbox *)
+module NX_SERVICE_U_WRAP(fabric_otp_user_tst_scanenable_i, fabric_otp_cfg_loader_read_en_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_scanenable_i, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_user_disturbcheck_i, fabric_mrepair_fuse_read_i, fabric_otp_user_rbact2_i, fabric_mrepair_fuse_eccbypass_i, fabric_otp_user_bistmode_i, fabric_otp_user_tm_i, fabric_otp_rst_i, fabric_mrepair_fuse_disturbchecked_i, fabric_otp_user_rbact1_i, fabric_mrepair_fuse_redbypass_i, fabric_otp_user_eccbypass_i, fabric_otp_user_redbypass_i, fabric_parusr_cs_i, fabric_mrepair_fuse_rbact2_i, fabric_data_from_system_i, fabric_otp_apb_enable_i
+, fabric_mrepair_fuse_tm_i, fabric_otp_security_rbact2_i, fabric_otp_security_rbact1_i, fabric_otp_cfg_loader_write_en_i, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_prog_i, fabric_otp_user_wordlock_i, fabric_otp_user_prog_i, fabric_otp_user_suppadd_i, fabric_mrepair_fuse_pdn_i, fabric_end_encoding_i, fabric_jtag_tdo_usr2_i, fabric_mrepair_fuse_wordlock_i, fabric_otp_user_read_i, fabric_mrepair_fuse_bistmode_i, fabric_jtag_tdo_usr1_i, fabric_otp_cfg_clk_fab_en_i, fabric_otp_apb_sel_i, fabric_mrepair_fuse_rbact1_i, fabric_otp_cfg_fabric_apb_en_i, fabric_data_shift_en_i
+, fabric_lowskew_i21, fabric_otp_user_pdn_i, fabric_otp_apb_write_i, fabric_otp_security_testmode_i, fabric_tst_atpg_mrepair_i, fabric_mrepair_fuse_tstscanenable_i, fabric_otp_security_bistmode_i, fabric_lowskew_i22, fabric_lowskew_i23, fabric_lowskew_i20, fabric_mrepair_por_i, fabric_mrepair_cke_i, fabric_clk_otp_mux_i, fabric_mrepair_cke_force_i, fabric_mrepair_fuse_bbad_o, fabric_jtag_trst_n_o, fabric_otp_security_bist_end1_o, fabric_parusr_data_val_o, fabric_debug_lock_reg_o, fabric_debug_security_error_read_o, fabric_otp_user_locked_o
+, fabric_otp_security_bist_bad_o, fabric_otp_user_pwok_o, fabric_otp_user_bend2_o, fabric_mrepair_fuse_ded_o, fabric_debug_access_reg_data_ready_o, fabric_debug_otp_reload_err_o, fabric_cfg_fabric_user_enable_o, fabric_decoder_init_ready_o, fabric_debug_security_boot_done_o, fabric_otp_user_calibrated_o, fabric_jtag_tms_o, fabric_debug_rst_soft_o, fabric_otp_user_ack_o, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_debug_otp_manager_read_otp_o, fabric_otp_user_sec_o, fabric_mrepair_fuse_bend1_o, fabric_otp_user_bbad_o, fabric_user_read_cycle_o, fabric_mrepair_fuse_disturbed_o, fabric_debug_key_correct_o
+, fabric_otp_apb_ready_o, fabric_otp_user_progfail_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_bend2_o, fabric_mrepair_fuse_ack_o, fabric_otp_security_ack_o, fabric_mrepair_fuse_progfail_o, fabric_jtag_tdi_o, fabric_lowskew_o3, fabric_lowskew_o5, fabric_lowskew_o4, fabric_debug_error_o, fabric_jtag_usr2_o, fabric_otp_user_disturbed_o, fabric_flag_trigger_o, fabric_otp_security_bist_end2_o, fabric_mrepair_fuse_locked_o, fabric_user_write_cycle_o, fabric_otp_user_ded_o, fabric_debug_otp_manager_read_done_o, fabric_debug_frame_use_encryption_o
+, fabric_data_to_system_o, fabric_jtag_usr1_o, fabric_otp_user_bend1_o, fabric_mrepair_fuse_ready_o, fabric_mrepair_fuse_calibrated_o, fabric_system_dataready_o, fabric_mrepair_fuse_pwok_o, fabric_lowskew_o6, fabric_cfg_fabric_user_flag_o, fabric_status_cold_start_o, fabric_flag_error_o, fabric_otp_user_clock_frequency_range_i, fabric_parusr_enable_i, fabric_mrepair_mode_i, fabric_mrepair_fuse_add_i, fabric_mrepair_fuse_din_i, fabric_mrepair_fuse_tst_scanin_i, fabric_mrepair_fuse_prgwidth_i, fabric_mrepair_fuse_dout_o, fabric_mrepair_fuse_startword_o, fabric_mrepair_fuse_wlromout_o
+, fabric_mrepair_fuse_bist1fail_o, fabric_mrepair_fuse_bist2fail_o, fabric_mrepair_fuse_tstscanout_o, fabric_mrepair_fuse_flagstate_o, fabric_otp_user_add_i, fabric_otp_user_din_i, fabric_otp_user_prgwidth_i, fabric_otp_user_tst_scanin_i, fabric_otp_user_bist1fail_o, fabric_otp_user_bist2fail_o, fabric_otp_user_dout_o, fabric_otp_user_flagstate_o, fabric_otp_user_startword_o, fabric_otp_user_tst_scanout_o, fabric_otp_user_wlromout_o, fabric_io_in_i, fabric_io_oe_i, fabric_io_out_o, fabric_user_data_i, fabric_user_data_o, fabric_parusr_type_i
+, fabric_parusr_data_i, fabric_parusr_data_o, fabric_direct_data_i, fabric_direct_data_o, fabric_otp_apb_addr_i, fabric_otp_apb_wdata_i, fabric_otp_apb_rdata_o, fabric_otp_security_bist_fail1_o, fabric_otp_security_bist_fail2_o, fabric_otp_security_scanin_i, fabric_otp_security_scanout_o, fabric_flag_ready_TMR_o, fabric_debug_lifecycle_o, fabric_debug_fsm_state_o, fabric_debug_direct_permission_write_o, fabric_debug_direct_permission_read_o, fabric_debug_frame_permission_frame_o, fabric_debug_otpmgmt_state_o, fabric_debug_otpapb_state_o, fabric_debug_otpboot_state_o, fabric_debug_cpt_retry_o
+, fabric_debug_bsec_core_status_o, fabric_debug_otpboot_curr_addr_o, fabric_sif_reg_en_i, fabric_data_from_bist_i, fabric_shift_en_i, fabric_ahb_direct_data_i, fabric_pd_active_i, fabric_sif_load_en_i, fabric_system_data_to_mem_bist_i, fabric_sif_update_en_i, fabric_sif_update_en_to_bist_o, fabric_data_to_bist_o, fabric_ahb_direct_data_o, fabric_global_chip_status_o, fabric_fuse_status_o, fabric_shift_en_to_bist_o, fabric_sif_reg_en_to_bist_o, fabric_system_data_from_mem_bist_o, fabric_chip_status_o, fabric_pd_ready_o, fabric_sif_load_en_to_bist_o
+);
+    input [31:0] fabric_ahb_direct_data_i;
+    output [31:0] fabric_ahb_direct_data_o;
+    output fabric_cfg_fabric_user_enable_o;
+    output fabric_cfg_fabric_user_flag_o;
+    output [71:0] fabric_chip_status_o;
+    input fabric_clk_otp_mux_i;
+    input [23:0] fabric_data_from_bist_i;
+    input fabric_data_from_system_i;
+    input fabric_data_shift_en_i;
+    output [23:0] fabric_data_to_bist_o;
+    output fabric_data_to_system_o;
+    output fabric_debug_access_reg_data_ready_o;
+    output [31:0] fabric_debug_bsec_core_status_o;
+    output [3:0] fabric_debug_cpt_retry_o;
+    output [3:0] fabric_debug_direct_permission_read_o;
+    output [3:0] fabric_debug_direct_permission_write_o;
+    output fabric_debug_error_o;
+    output [3:0] fabric_debug_frame_permission_frame_o;
+    output fabric_debug_frame_use_encryption_o;
+    output [2:0] fabric_debug_fsm_state_o;
+    output fabric_debug_key_correct_o;
+    output [3:0] fabric_debug_lifecycle_o;
+    output fabric_debug_lock_reg_o;
+    output fabric_debug_otp_manager_read_done_o;
+    output fabric_debug_otp_manager_read_otp_o;
+    output fabric_debug_otp_reload_err_o;
+    output [2:0] fabric_debug_otpapb_state_o;
+    output [7:0] fabric_debug_otpboot_curr_addr_o;
+    output [2:0] fabric_debug_otpboot_state_o;
+    output [2:0] fabric_debug_otpmgmt_state_o;
+    output fabric_debug_rst_soft_o;
+    output fabric_debug_security_boot_done_o;
+    output fabric_debug_security_error_read_o;
+    output fabric_decoder_init_ready_o;
+    input [31:0] fabric_direct_data_i;
+    output [31:0] fabric_direct_data_o;
+    input fabric_end_encoding_i;
+    output fabric_flag_error_o;
+    output [2:0] fabric_flag_ready_TMR_o;
+    output fabric_flag_trigger_o;
+    output [2:0] fabric_fuse_status_o;
+    output [2:0] fabric_global_chip_status_o;
+    input [24:0] fabric_io_in_i;
+    input [24:0] fabric_io_oe_i;
+    output [24:0] fabric_io_out_o;
+    output fabric_jtag_tdi_o;
+    input fabric_jtag_tdo_usr1_i;
+    input fabric_jtag_tdo_usr2_i;
+    output fabric_jtag_tms_o;
+    output fabric_jtag_trst_n_o;
+    output fabric_jtag_usr1_o;
+    output fabric_jtag_usr2_o;
+    input fabric_lowskew_i20;
+    input fabric_lowskew_i21;
+    input fabric_lowskew_i22;
+    input fabric_lowskew_i23;
+    output fabric_lowskew_o3;
+    output fabric_lowskew_o4;
+    output fabric_lowskew_o5;
+    output fabric_lowskew_o6;
+    input fabric_mrepair_cke_force_i;
+    input fabric_mrepair_cke_i;
+    output fabric_mrepair_fuse_ack_o;
+    input [6:0] fabric_mrepair_fuse_add_i;
+    output fabric_mrepair_fuse_bbad_o;
+    output fabric_mrepair_fuse_bend1_o;
+    output fabric_mrepair_fuse_bend2_o;
+    output [7:0] fabric_mrepair_fuse_bist1fail_o;
+    output [6:0] fabric_mrepair_fuse_bist2fail_o;
+    input fabric_mrepair_fuse_bistmode_i;
+    output fabric_mrepair_fuse_calibrated_o;
+    output fabric_mrepair_fuse_ded_o;
+    input [38:0] fabric_mrepair_fuse_din_i;
+    input fabric_mrepair_fuse_disturbchecked_i;
+    output fabric_mrepair_fuse_disturbed_o;
+    output [40:0] fabric_mrepair_fuse_dout_o;
+    input fabric_mrepair_fuse_eccbypass_i;
+    output [3:0] fabric_mrepair_fuse_flagstate_o;
+    output fabric_mrepair_fuse_locked_o;
+    input fabric_mrepair_fuse_pdn_i;
+    output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o;
+    input [2:0] fabric_mrepair_fuse_prgwidth_i;
+    input fabric_mrepair_fuse_prog_i;
+    output fabric_mrepair_fuse_progfail_o;
+    output fabric_mrepair_fuse_pwok_o;
+    input fabric_mrepair_fuse_rbact1_i;
+    input fabric_mrepair_fuse_rbact2_i;
+    input fabric_mrepair_fuse_read_i;
+    output fabric_mrepair_fuse_ready_o;
+    input fabric_mrepair_fuse_redbypass_i;
+    output fabric_mrepair_fuse_sec_o;
+    output [15:0] fabric_mrepair_fuse_startword_o;
+    input fabric_mrepair_fuse_suppadd_i;
+    input fabric_mrepair_fuse_tm_i;
+    input [4:0] fabric_mrepair_fuse_tst_scanin_i;
+    input fabric_mrepair_fuse_tstscanenable_i;
+    output [4:0] fabric_mrepair_fuse_tstscanout_o;
+    output [9:0] fabric_mrepair_fuse_wlromout_o;
+    input fabric_mrepair_fuse_wordlock_i;
+    input [3:0] fabric_mrepair_mode_i;
+    input fabric_mrepair_por_i;
+    input [31:0] fabric_otp_apb_addr_i;
+    input fabric_otp_apb_enable_i;
+    output [31:0] fabric_otp_apb_rdata_o;
+    output fabric_otp_apb_ready_o;
+    input fabric_otp_apb_sel_i;
+    input [31:0] fabric_otp_apb_wdata_i;
+    input fabric_otp_apb_write_i;
+    input fabric_otp_cfg_clk_fab_en_i;
+    input fabric_otp_cfg_clk_otpm_disable_i;
+    input fabric_otp_cfg_fabric_apb_en_i;
+    input fabric_otp_cfg_loader_read_en_i;
+    input fabric_otp_cfg_loader_write_en_i;
+    input fabric_otp_rst_i;
+    output fabric_otp_security_ack_o;
+    output fabric_otp_security_bist_bad_o;
+    output fabric_otp_security_bist_end1_o;
+    output fabric_otp_security_bist_end2_o;
+    output [7:0] fabric_otp_security_bist_fail1_o;
+    output [6:0] fabric_otp_security_bist_fail2_o;
+    input fabric_otp_security_bistmode_i;
+    input fabric_otp_security_force_pdn1_i;
+    input fabric_otp_security_rbact1_i;
+    input fabric_otp_security_rbact2_i;
+    input fabric_otp_security_scanenable_i;
+    input [4:0] fabric_otp_security_scanin_i;
+    output [4:0] fabric_otp_security_scanout_o;
+    input fabric_otp_security_testmode_i;
+    output fabric_otp_user_ack_o;
+    input [6:0] fabric_otp_user_add_i;
+    output fabric_otp_user_bbad_o;
+    output fabric_otp_user_bend1_o;
+    output fabric_otp_user_bend2_o;
+    output [7:0] fabric_otp_user_bist1fail_o;
+    output [6:0] fabric_otp_user_bist2fail_o;
+    input fabric_otp_user_bistmode_i;
+    output fabric_otp_user_calibrated_o;
+    input fabric_otp_user_clock_frequency_range_i;
+    output fabric_otp_user_ded_o;
+    input [38:0] fabric_otp_user_din_i;
+    input fabric_otp_user_disturbcheck_i;
+    output fabric_otp_user_disturbed_o;
+    output [40:0] fabric_otp_user_dout_o;
+    input fabric_otp_user_eccbypass_i;
+    output [3:0] fabric_otp_user_flagstate_o;
+    output fabric_otp_user_locked_o;
+    input fabric_otp_user_pdn_i;
+    input [2:0] fabric_otp_user_prgwidth_i;
+    input fabric_otp_user_prog_i;
+    output fabric_otp_user_progfail_o;
+    output fabric_otp_user_pwok_o;
+    input fabric_otp_user_rbact1_i;
+    input fabric_otp_user_rbact2_i;
+    input fabric_otp_user_read_i;
+    input fabric_otp_user_redbypass_i;
+    output fabric_otp_user_sec_o;
+    output [15:0] fabric_otp_user_startword_o;
+    input fabric_otp_user_suppadd_i;
+    input fabric_otp_user_tm_i;
+    input fabric_otp_user_tst_scanenable_i;
+    input [4:0] fabric_otp_user_tst_scanin_i;
+    output [4:0] fabric_otp_user_tst_scanout_o;
+    output [9:0] fabric_otp_user_wlromout_o;
+    input fabric_otp_user_wordlock_i;
+    input fabric_parusr_cs_i;
+    input [15:0] fabric_parusr_data_i;
+    output [15:0] fabric_parusr_data_o;
+    output fabric_parusr_data_val_o;
+    input fabric_parusr_enable_i;
+    input [1:0] fabric_parusr_type_i;
+    input [23:0] fabric_pd_active_i;
+    output [23:0] fabric_pd_ready_o;
+    input [23:0] fabric_shift_en_i;
+    output [23:0] fabric_shift_en_to_bist_o;
+    input [23:0] fabric_sif_load_en_i;
+    output [23:0] fabric_sif_load_en_to_bist_o;
+    input [119:0] fabric_sif_reg_en_i;
+    output [119:0] fabric_sif_reg_en_to_bist_o;
+    input [23:0] fabric_sif_update_en_i;
+    output [23:0] fabric_sif_update_en_to_bist_o;
+    output fabric_status_cold_start_o;
+    output [23:0] fabric_system_data_from_mem_bist_o;
+    input [23:0] fabric_system_data_to_mem_bist_i;
+    output fabric_system_dataready_o;
+    input fabric_tst_atpg_mrepair_i;
+    input [31:0] fabric_user_data_i;
+    output [31:0] fabric_user_data_o;
+    output fabric_user_read_cycle_o;
+    output fabric_user_write_cycle_o;
+    parameter ahb_config = 0;
+    parameter bsm_config = 0;
+endmodule
+
+(* blackbox *)
+module NX_SOC_INTERFACE(fabric_lowskew_o1, fabric_lowskew_o2, fabric_lowskew_i3, fabric_lowskew_i4, fabric_lowskew_i5, fabric_lowskew_i6, fabric_lowskew_i7, fabric_lowskew_i8, fabric_lowskew_i9, fabric_lowskew_i10, fabric_lowskew_i11, fabric_lowskew_i12, fabric_lowskew_i13, fabric_lowskew_i14, fabric_lowskew_i15, fabric_lowskew_i16, fabric_lowskew_i17, fabric_lowskew_i18, fabric_lowskew_i19, fabric_fpga_nic_rstn_i1, fabric_fpga_nic_rstn_i2
+, fabric_fpga_nic_rstn_i3, fabric_fpga_nic_rstn_i4, fabric_fpga_nic_rstn_i5, fabric_fpga_nic_rstn_i6, fabric_fpga_nic_rstn_i7, fabric_fpga_nic_rstn_i8, fabric_fpga_nic_rstn_i9, fabric_fpga_nic_rstn_i10, fabric_fpga_pmrstn_i, fabric_fpga_sysrstn_i, fabric_fpga_trigger_in_o1, fabric_fpga_trigger_in_o2, fabric_fpga_trigger_in_o3, fabric_fpga_trigger_in_o4, fabric_fpga_trigger_in_o5, fabric_fpga_trigger_in_o6, fabric_fpga_trigger_in_o7, fabric_fpga_trigger_in_o8, fabric_fpga_trigger_out_i1, fabric_fpga_trigger_out_i2, fabric_fpga_trigger_out_i3
+, fabric_fpga_trigger_out_i4, fabric_fpga_trigger_out_i5, fabric_fpga_trigger_out_i6, fabric_fpga_trigger_out_i7, fabric_fpga_trigger_out_i8, fabric_fpga_interrupt_in_i1, fabric_fpga_interrupt_in_i2, fabric_fpga_interrupt_in_i3, fabric_fpga_interrupt_in_i4, fabric_fpga_interrupt_in_i5, fabric_fpga_interrupt_in_i6, fabric_fpga_interrupt_in_i7, fabric_fpga_interrupt_in_i8, fabric_fpga_interrupt_in_i9, fabric_fpga_interrupt_in_i10, fabric_fpga_interrupt_in_i11, fabric_fpga_interrupt_in_i12, fabric_fpga_interrupt_in_i13, fabric_fpga_interrupt_in_i14, fabric_fpga_interrupt_in_i15, fabric_fpga_interrupt_in_i16
+, fabric_fpga_interrupt_in_i17, fabric_fpga_interrupt_in_i18, fabric_fpga_interrupt_in_i19, fabric_fpga_interrupt_in_i20, fabric_fpga_interrupt_in_i21, fabric_fpga_interrupt_in_i22, fabric_fpga_interrupt_in_i23, fabric_fpga_interrupt_in_i24, fabric_fpga_interrupt_in_i25, fabric_fpga_interrupt_in_i26, fabric_fpga_interrupt_in_i27, fabric_fpga_interrupt_in_i28, fabric_fpga_interrupt_in_i29, fabric_fpga_interrupt_in_i30, fabric_fpga_interrupt_in_i31, fabric_fpga_interrupt_in_i32, fabric_fpga_interrupt_in_i33, fabric_fpga_interrupt_in_i34, fabric_fpga_interrupt_in_i35, fabric_fpga_interrupt_in_i36, fabric_fpga_interrupt_in_i37
+, fabric_fpga_interrupt_in_i38, fabric_fpga_interrupt_in_i39, fabric_fpga_interrupt_in_i40, fabric_fpga_interrupt_in_i41, fabric_fpga_interrupt_in_i42, fabric_fpga_interrupt_in_i43, fabric_fpga_interrupt_in_i44, fabric_fpga_interrupt_in_i45, fabric_fpga_interrupt_in_i46, fabric_fpga_interrupt_in_i47, fabric_fpga_interrupt_in_i48, fabric_fpga_interrupt_in_i49, fabric_fpga_interrupt_in_i50, fabric_fpga_interrupt_in_i51, fabric_fpga_interrupt_in_i52, fabric_fpga_interrupt_in_i53, fabric_fpga_interrupt_in_i54, fabric_fpga_interrupt_in_i55, fabric_fpga_interrupt_in_i56, fabric_fpga_interrupt_in_i57, fabric_fpga_interrupt_in_i58
+, fabric_fpga_interrupt_in_i59, fabric_fpga_interrupt_in_i60, fabric_fpga_interrupt_in_i61, fabric_fpga_interrupt_in_i62, fabric_fpga_interrupt_in_i63, fabric_fpga_interrupt_in_i64, fabric_fpga_interrupt_in_i65, fabric_fpga_interrupt_in_i66, fabric_fpga_interrupt_in_i67, fabric_fpga_interrupt_in_i68, fabric_fpga_interrupt_in_i69, fabric_fpga_interrupt_in_i70, fabric_fpga_interrupt_in_i71, fabric_fpga_interrupt_in_i72, fabric_fpga_interrupt_in_i73, fabric_fpga_interrupt_in_i74, fabric_fpga_interrupt_in_i75, fabric_fpga_interrupt_in_i76, fabric_fpga_interrupt_in_i77, fabric_fpga_interrupt_in_i78, fabric_fpga_interrupt_in_i79
+, fabric_fpga_interrupt_in_i80, fabric_fpga_interrupt_in_i81, fabric_fpga_interrupt_in_i82, fabric_fpga_interrupt_in_i83, fabric_fpga_interrupt_in_i84, fabric_fpga_interrupt_in_i85, fabric_fpga_interrupt_in_i86, fabric_fpga_interrupt_in_i87, fabric_fpga_interrupt_in_i88, fabric_fpga_interrupt_in_i89, fabric_fpga_interrupt_in_i90, fabric_fpga_interrupt_in_i91, fabric_fpga_interrupt_in_i92, fabric_fpga_interrupt_in_i93, fabric_fpga_interrupt_in_i94, fabric_fpga_interrupt_in_i95, fabric_fpga_interrupt_in_i96, fabric_fpga_interrupt_in_i97, fabric_fpga_interrupt_in_i98, fabric_fpga_interrupt_in_i99, fabric_fpga_interrupt_in_i100
+, fabric_fpga_interrupt_in_i101, fabric_fpga_interrupt_in_i102, fabric_fpga_interrupt_in_i103, fabric_fpga_interrupt_in_i104, fabric_fpga_interrupt_in_i105, fabric_fpga_interrupt_in_i106, fabric_fpga_interrupt_in_i107, fabric_fpga_interrupt_in_i108, fabric_fpga_interrupt_in_i109, fabric_fpga_interrupt_in_i110, fabric_fpga_interrupt_in_i111, fabric_fpga_interrupt_in_i112, fabric_fpga_interrupt_in_i113, fabric_fpga_interrupt_in_i114, fabric_fpga_interrupt_in_i115, fabric_fpga_interrupt_in_i116, fabric_fpga_interrupt_in_i117, fabric_fpga_interrupt_in_i118, fabric_fpga_interrupt_in_i119, fabric_fpga_interrupt_in_i120, fabric_sysc_hold_on_debug_i
+, fabric_fpga_events60_i1, fabric_fpga_events60_i2, fabric_fpga_events60_i3, fabric_fpga_events60_i4, fabric_fpga_events60_i5, fabric_fpga_events60_i6, fabric_fpga_events60_i7, fabric_fpga_events60_i8, fabric_fpga_events60_i9, fabric_fpga_events60_i10, fabric_fpga_events60_i11, fabric_fpga_events60_i12, fabric_fpga_events60_i13, fabric_fpga_events60_i14, fabric_fpga_events60_i15, fabric_fpga_events60_i16, fabric_fpga_events60_i17, fabric_fpga_events60_i18, fabric_fpga_events60_i19, fabric_fpga_events60_i20, fabric_fpga_events60_i21
+, fabric_fpga_events60_i22, fabric_fpga_events60_i23, fabric_fpga_events60_i24, fabric_fpga_events60_i25, fabric_fpga_events60_i26, fabric_fpga_events60_i27, fabric_fpga_events60_i28, fabric_fpga_events60_i29, fabric_fpga_events60_i30, fabric_fpga_events60_i31, fabric_fpga_events60_i32, fabric_fpga_events60_i33, fabric_fpga_events60_i34, fabric_fpga_events60_i35, fabric_fpga_events60_i36, fabric_fpga_events60_i37, fabric_fpga_events60_i38, fabric_fpga_events60_i39, fabric_fpga_events60_i40, fabric_fpga_events60_i41, fabric_fpga_events60_i42
+, fabric_fpga_events60_i43, fabric_fpga_events60_i44, fabric_fpga_events60_i45, fabric_fpga_events60_i46, fabric_fpga_events60_i47, fabric_fpga_events60_i48, fabric_fpga_events60_i49, fabric_fpga_events60_i50, fabric_fpga_events60_i51, fabric_fpga_events60_i52, fabric_fpga_events60_i53, fabric_fpga_events60_i54, fabric_fpga_events60_i55, fabric_fpga_events60_i56, fabric_fpga_events60_i57, fabric_fpga_events60_i58, fabric_fpga_events60_i59, fabric_fpga_events60_i60, fabric_fpga_araddr_axi_s1_o1, fabric_fpga_araddr_axi_s1_o2, fabric_fpga_araddr_axi_s1_o3
+, fabric_fpga_araddr_axi_s1_o4, fabric_fpga_araddr_axi_s1_o5, fabric_fpga_araddr_axi_s1_o6, fabric_fpga_araddr_axi_s1_o7, fabric_fpga_araddr_axi_s1_o8, fabric_fpga_araddr_axi_s1_o9, fabric_fpga_araddr_axi_s1_o10, fabric_fpga_araddr_axi_s1_o11, fabric_fpga_araddr_axi_s1_o12, fabric_fpga_araddr_axi_s1_o13, fabric_fpga_araddr_axi_s1_o14, fabric_fpga_araddr_axi_s1_o15, fabric_fpga_araddr_axi_s1_o16, fabric_fpga_araddr_axi_s1_o17, fabric_fpga_araddr_axi_s1_o18, fabric_fpga_araddr_axi_s1_o19, fabric_fpga_araddr_axi_s1_o20, fabric_fpga_araddr_axi_s1_o21, fabric_fpga_araddr_axi_s1_o22, fabric_fpga_araddr_axi_s1_o23, fabric_fpga_araddr_axi_s1_o24
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+, fabric_fpga_rdata_axi_s2_i125, fabric_fpga_rdata_axi_s2_i126, fabric_fpga_rdata_axi_s2_i127, fabric_fpga_rdata_axi_s2_i128, fabric_fpga_rid_axi_s2_i1, fabric_fpga_rid_axi_s2_i2, fabric_fpga_rid_axi_s2_i3, fabric_fpga_rid_axi_s2_i4, fabric_fpga_rid_axi_s2_i5, fabric_fpga_rid_axi_s2_i6, fabric_fpga_rid_axi_s2_i7, fabric_fpga_rid_axi_s2_i8, fabric_fpga_rid_axi_s2_i9, fabric_fpga_rid_axi_s2_i10, fabric_fpga_rid_axi_s2_i11, fabric_fpga_rid_axi_s2_i12, fabric_fpga_rlast_axi_s2_i, fabric_fpga_rresp_axi_s2_i1, fabric_fpga_rresp_axi_s2_i2, fabric_fpga_rvalid_axi_s2_i, fabric_fpga_wready_axi_s2_i
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+, fabric_fpga_dma_finish_m1_o6, fabric_fpga_rdata_axi_m1_o1, fabric_fpga_rdata_axi_m1_o2, fabric_fpga_rdata_axi_m1_o3, fabric_fpga_rdata_axi_m1_o4, fabric_fpga_rdata_axi_m1_o5, fabric_fpga_rdata_axi_m1_o6, fabric_fpga_rdata_axi_m1_o7, fabric_fpga_rdata_axi_m1_o8, fabric_fpga_rdata_axi_m1_o9, fabric_fpga_rdata_axi_m1_o10, fabric_fpga_rdata_axi_m1_o11, fabric_fpga_rdata_axi_m1_o12, fabric_fpga_rdata_axi_m1_o13, fabric_fpga_rdata_axi_m1_o14, fabric_fpga_rdata_axi_m1_o15, fabric_fpga_rdata_axi_m1_o16, fabric_fpga_rdata_axi_m1_o17, fabric_fpga_rdata_axi_m1_o18, fabric_fpga_rdata_axi_m1_o19, fabric_fpga_rdata_axi_m1_o20
+, fabric_fpga_rdata_axi_m1_o21, fabric_fpga_rdata_axi_m1_o22, fabric_fpga_rdata_axi_m1_o23, fabric_fpga_rdata_axi_m1_o24, fabric_fpga_rdata_axi_m1_o25, fabric_fpga_rdata_axi_m1_o26, fabric_fpga_rdata_axi_m1_o27, fabric_fpga_rdata_axi_m1_o28, fabric_fpga_rdata_axi_m1_o29, fabric_fpga_rdata_axi_m1_o30, fabric_fpga_rdata_axi_m1_o31, fabric_fpga_rdata_axi_m1_o32, fabric_fpga_rdata_axi_m1_o33, fabric_fpga_rdata_axi_m1_o34, fabric_fpga_rdata_axi_m1_o35, fabric_fpga_rdata_axi_m1_o36, fabric_fpga_rdata_axi_m1_o37, fabric_fpga_rdata_axi_m1_o38, fabric_fpga_rdata_axi_m1_o39, fabric_fpga_rdata_axi_m1_o40, fabric_fpga_rdata_axi_m1_o41
+, fabric_fpga_rdata_axi_m1_o42, fabric_fpga_rdata_axi_m1_o43, fabric_fpga_rdata_axi_m1_o44, fabric_fpga_rdata_axi_m1_o45, fabric_fpga_rdata_axi_m1_o46, fabric_fpga_rdata_axi_m1_o47, fabric_fpga_rdata_axi_m1_o48, fabric_fpga_rdata_axi_m1_o49, fabric_fpga_rdata_axi_m1_o50, fabric_fpga_rdata_axi_m1_o51, fabric_fpga_rdata_axi_m1_o52, fabric_fpga_rdata_axi_m1_o53, fabric_fpga_rdata_axi_m1_o54, fabric_fpga_rdata_axi_m1_o55, fabric_fpga_rdata_axi_m1_o56, fabric_fpga_rdata_axi_m1_o57, fabric_fpga_rdata_axi_m1_o58, fabric_fpga_rdata_axi_m1_o59, fabric_fpga_rdata_axi_m1_o60, fabric_fpga_rdata_axi_m1_o61, fabric_fpga_rdata_axi_m1_o62
+, fabric_fpga_rdata_axi_m1_o63, fabric_fpga_rdata_axi_m1_o64, fabric_fpga_rdata_axi_m1_o65, fabric_fpga_rdata_axi_m1_o66, fabric_fpga_rdata_axi_m1_o67, fabric_fpga_rdata_axi_m1_o68, fabric_fpga_rdata_axi_m1_o69, fabric_fpga_rdata_axi_m1_o70, fabric_fpga_rdata_axi_m1_o71, fabric_fpga_rdata_axi_m1_o72, fabric_fpga_rdata_axi_m1_o73, fabric_fpga_rdata_axi_m1_o74, fabric_fpga_rdata_axi_m1_o75, fabric_fpga_rdata_axi_m1_o76, fabric_fpga_rdata_axi_m1_o77, fabric_fpga_rdata_axi_m1_o78, fabric_fpga_rdata_axi_m1_o79, fabric_fpga_rdata_axi_m1_o80, fabric_fpga_rdata_axi_m1_o81, fabric_fpga_rdata_axi_m1_o82, fabric_fpga_rdata_axi_m1_o83
+, fabric_fpga_rdata_axi_m1_o84, fabric_fpga_rdata_axi_m1_o85, fabric_fpga_rdata_axi_m1_o86, fabric_fpga_rdata_axi_m1_o87, fabric_fpga_rdata_axi_m1_o88, fabric_fpga_rdata_axi_m1_o89, fabric_fpga_rdata_axi_m1_o90, fabric_fpga_rdata_axi_m1_o91, fabric_fpga_rdata_axi_m1_o92, fabric_fpga_rdata_axi_m1_o93, fabric_fpga_rdata_axi_m1_o94, fabric_fpga_rdata_axi_m1_o95, fabric_fpga_rdata_axi_m1_o96, fabric_fpga_rdata_axi_m1_o97, fabric_fpga_rdata_axi_m1_o98, fabric_fpga_rdata_axi_m1_o99, fabric_fpga_rdata_axi_m1_o100, fabric_fpga_rdata_axi_m1_o101, fabric_fpga_rdata_axi_m1_o102, fabric_fpga_rdata_axi_m1_o103, fabric_fpga_rdata_axi_m1_o104
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+, fabric_fpga_awaddr_axi_m1_i1, fabric_fpga_awaddr_axi_m1_i2, fabric_fpga_awaddr_axi_m1_i3, fabric_fpga_awaddr_axi_m1_i4, fabric_fpga_awaddr_axi_m1_i5, fabric_fpga_awaddr_axi_m1_i6, fabric_fpga_awaddr_axi_m1_i7, fabric_fpga_awaddr_axi_m1_i8, fabric_fpga_awaddr_axi_m1_i9, fabric_fpga_awaddr_axi_m1_i10, fabric_fpga_awaddr_axi_m1_i11, fabric_fpga_awaddr_axi_m1_i12, fabric_fpga_awaddr_axi_m1_i13, fabric_fpga_awaddr_axi_m1_i14, fabric_fpga_awaddr_axi_m1_i15, fabric_fpga_awaddr_axi_m1_i16, fabric_fpga_awaddr_axi_m1_i17, fabric_fpga_awaddr_axi_m1_i18, fabric_fpga_awaddr_axi_m1_i19, fabric_fpga_awaddr_axi_m1_i20, fabric_fpga_awaddr_axi_m1_i21
+, fabric_fpga_awaddr_axi_m1_i22, fabric_fpga_awaddr_axi_m1_i23, fabric_fpga_awaddr_axi_m1_i24, fabric_fpga_awaddr_axi_m1_i25, fabric_fpga_awaddr_axi_m1_i26, fabric_fpga_awaddr_axi_m1_i27, fabric_fpga_awaddr_axi_m1_i28, fabric_fpga_awaddr_axi_m1_i29, fabric_fpga_awaddr_axi_m1_i30, fabric_fpga_awaddr_axi_m1_i31, fabric_fpga_awaddr_axi_m1_i32, fabric_fpga_awaddr_axi_m1_i33, fabric_fpga_awaddr_axi_m1_i34, fabric_fpga_awaddr_axi_m1_i35, fabric_fpga_awaddr_axi_m1_i36, fabric_fpga_awaddr_axi_m1_i37, fabric_fpga_awaddr_axi_m1_i38, fabric_fpga_awaddr_axi_m1_i39, fabric_fpga_awaddr_axi_m1_i40, fabric_fpga_awburst_axi_m1_i1, fabric_fpga_awburst_axi_m1_i2
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+, fabric_fpga_awqos_axi_m1_i1, fabric_fpga_awqos_axi_m1_i2, fabric_fpga_awqos_axi_m1_i3, fabric_fpga_awqos_axi_m1_i4, fabric_fpga_awsize_axi_m1_i1, fabric_fpga_awsize_axi_m1_i2, fabric_fpga_awsize_axi_m1_i3, fabric_fpga_awvalid_axi_m1_i, fabric_fpga_bready_axi_m1_i, fabric_fpga_dma_last_m1_i1, fabric_fpga_dma_last_m1_i2, fabric_fpga_dma_last_m1_i3, fabric_fpga_dma_last_m1_i4, fabric_fpga_dma_last_m1_i5, fabric_fpga_dma_last_m1_i6, fabric_fpga_dma_req_m1_i1, fabric_fpga_dma_req_m1_i2, fabric_fpga_dma_req_m1_i3, fabric_fpga_dma_req_m1_i4, fabric_fpga_dma_req_m1_i5, fabric_fpga_dma_req_m1_i6
+, fabric_fpga_dma_single_m1_i1, fabric_fpga_dma_single_m1_i2, fabric_fpga_dma_single_m1_i3, fabric_fpga_dma_single_m1_i4, fabric_fpga_dma_single_m1_i5, fabric_fpga_dma_single_m1_i6, fabric_fpga_rready_axi_m1_i, fabric_fpga_wdata_axi_m1_i1, fabric_fpga_wdata_axi_m1_i2, fabric_fpga_wdata_axi_m1_i3, fabric_fpga_wdata_axi_m1_i4, fabric_fpga_wdata_axi_m1_i5, fabric_fpga_wdata_axi_m1_i6, fabric_fpga_wdata_axi_m1_i7, fabric_fpga_wdata_axi_m1_i8, fabric_fpga_wdata_axi_m1_i9, fabric_fpga_wdata_axi_m1_i10, fabric_fpga_wdata_axi_m1_i11, fabric_fpga_wdata_axi_m1_i12, fabric_fpga_wdata_axi_m1_i13, fabric_fpga_wdata_axi_m1_i14
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+, fabric_fpga_wdata_axi_m1_i36, fabric_fpga_wdata_axi_m1_i37, fabric_fpga_wdata_axi_m1_i38, fabric_fpga_wdata_axi_m1_i39, fabric_fpga_wdata_axi_m1_i40, fabric_fpga_wdata_axi_m1_i41, fabric_fpga_wdata_axi_m1_i42, fabric_fpga_wdata_axi_m1_i43, fabric_fpga_wdata_axi_m1_i44, fabric_fpga_wdata_axi_m1_i45, fabric_fpga_wdata_axi_m1_i46, fabric_fpga_wdata_axi_m1_i47, fabric_fpga_wdata_axi_m1_i48, fabric_fpga_wdata_axi_m1_i49, fabric_fpga_wdata_axi_m1_i50, fabric_fpga_wdata_axi_m1_i51, fabric_fpga_wdata_axi_m1_i52, fabric_fpga_wdata_axi_m1_i53, fabric_fpga_wdata_axi_m1_i54, fabric_fpga_wdata_axi_m1_i55, fabric_fpga_wdata_axi_m1_i56
+, fabric_fpga_wdata_axi_m1_i57, fabric_fpga_wdata_axi_m1_i58, fabric_fpga_wdata_axi_m1_i59, fabric_fpga_wdata_axi_m1_i60, fabric_fpga_wdata_axi_m1_i61, fabric_fpga_wdata_axi_m1_i62, fabric_fpga_wdata_axi_m1_i63, fabric_fpga_wdata_axi_m1_i64, fabric_fpga_wdata_axi_m1_i65, fabric_fpga_wdata_axi_m1_i66, fabric_fpga_wdata_axi_m1_i67, fabric_fpga_wdata_axi_m1_i68, fabric_fpga_wdata_axi_m1_i69, fabric_fpga_wdata_axi_m1_i70, fabric_fpga_wdata_axi_m1_i71, fabric_fpga_wdata_axi_m1_i72, fabric_fpga_wdata_axi_m1_i73, fabric_fpga_wdata_axi_m1_i74, fabric_fpga_wdata_axi_m1_i75, fabric_fpga_wdata_axi_m1_i76, fabric_fpga_wdata_axi_m1_i77
+, fabric_fpga_wdata_axi_m1_i78, fabric_fpga_wdata_axi_m1_i79, fabric_fpga_wdata_axi_m1_i80, fabric_fpga_wdata_axi_m1_i81, fabric_fpga_wdata_axi_m1_i82, fabric_fpga_wdata_axi_m1_i83, fabric_fpga_wdata_axi_m1_i84, fabric_fpga_wdata_axi_m1_i85, fabric_fpga_wdata_axi_m1_i86, fabric_fpga_wdata_axi_m1_i87, fabric_fpga_wdata_axi_m1_i88, fabric_fpga_wdata_axi_m1_i89, fabric_fpga_wdata_axi_m1_i90, fabric_fpga_wdata_axi_m1_i91, fabric_fpga_wdata_axi_m1_i92, fabric_fpga_wdata_axi_m1_i93, fabric_fpga_wdata_axi_m1_i94, fabric_fpga_wdata_axi_m1_i95, fabric_fpga_wdata_axi_m1_i96, fabric_fpga_wdata_axi_m1_i97, fabric_fpga_wdata_axi_m1_i98
+, fabric_fpga_wdata_axi_m1_i99, fabric_fpga_wdata_axi_m1_i100, fabric_fpga_wdata_axi_m1_i101, fabric_fpga_wdata_axi_m1_i102, fabric_fpga_wdata_axi_m1_i103, fabric_fpga_wdata_axi_m1_i104, fabric_fpga_wdata_axi_m1_i105, fabric_fpga_wdata_axi_m1_i106, fabric_fpga_wdata_axi_m1_i107, fabric_fpga_wdata_axi_m1_i108, fabric_fpga_wdata_axi_m1_i109, fabric_fpga_wdata_axi_m1_i110, fabric_fpga_wdata_axi_m1_i111, fabric_fpga_wdata_axi_m1_i112, fabric_fpga_wdata_axi_m1_i113, fabric_fpga_wdata_axi_m1_i114, fabric_fpga_wdata_axi_m1_i115, fabric_fpga_wdata_axi_m1_i116, fabric_fpga_wdata_axi_m1_i117, fabric_fpga_wdata_axi_m1_i118, fabric_fpga_wdata_axi_m1_i119
+, fabric_fpga_wdata_axi_m1_i120, fabric_fpga_wdata_axi_m1_i121, fabric_fpga_wdata_axi_m1_i122, fabric_fpga_wdata_axi_m1_i123, fabric_fpga_wdata_axi_m1_i124, fabric_fpga_wdata_axi_m1_i125, fabric_fpga_wdata_axi_m1_i126, fabric_fpga_wdata_axi_m1_i127, fabric_fpga_wdata_axi_m1_i128, fabric_fpga_wlast_axi_m1_i, fabric_fpga_wstrb_axi_m1_i1, fabric_fpga_wstrb_axi_m1_i2, fabric_fpga_wstrb_axi_m1_i3, fabric_fpga_wstrb_axi_m1_i4, fabric_fpga_wstrb_axi_m1_i5, fabric_fpga_wstrb_axi_m1_i6, fabric_fpga_wstrb_axi_m1_i7, fabric_fpga_wstrb_axi_m1_i8, fabric_fpga_wstrb_axi_m1_i9, fabric_fpga_wstrb_axi_m1_i10, fabric_fpga_wstrb_axi_m1_i11
+, fabric_fpga_wstrb_axi_m1_i12, fabric_fpga_wstrb_axi_m1_i13, fabric_fpga_wstrb_axi_m1_i14, fabric_fpga_wstrb_axi_m1_i15, fabric_fpga_wstrb_axi_m1_i16, fabric_fpga_wvalid_axi_m1_i, fabric_fpga_arready_axi_m2_o, fabric_fpga_awready_axi_m2_o, fabric_fpga_bid_axi_m2_o1, fabric_fpga_bid_axi_m2_o2, fabric_fpga_bid_axi_m2_o3, fabric_fpga_bid_axi_m2_o4, fabric_fpga_bid_axi_m2_o5, fabric_fpga_bresp_axi_m2_o1, fabric_fpga_bresp_axi_m2_o2, fabric_fpga_bvalid_axi_m2_o, fabric_fpga_dma_ack_m2_o1, fabric_fpga_dma_ack_m2_o2, fabric_fpga_dma_ack_m2_o3, fabric_fpga_dma_ack_m2_o4, fabric_fpga_dma_ack_m2_o5
+, fabric_fpga_dma_ack_m2_o6, fabric_fpga_dma_finish_m2_o1, fabric_fpga_dma_finish_m2_o2, fabric_fpga_dma_finish_m2_o3, fabric_fpga_dma_finish_m2_o4, fabric_fpga_dma_finish_m2_o5, fabric_fpga_dma_finish_m2_o6, fabric_fpga_rdata_axi_m2_o1, fabric_fpga_rdata_axi_m2_o2, fabric_fpga_rdata_axi_m2_o3, fabric_fpga_rdata_axi_m2_o4, fabric_fpga_rdata_axi_m2_o5, fabric_fpga_rdata_axi_m2_o6, fabric_fpga_rdata_axi_m2_o7, fabric_fpga_rdata_axi_m2_o8, fabric_fpga_rdata_axi_m2_o9, fabric_fpga_rdata_axi_m2_o10, fabric_fpga_rdata_axi_m2_o11, fabric_fpga_rdata_axi_m2_o12, fabric_fpga_rdata_axi_m2_o13, fabric_fpga_rdata_axi_m2_o14
+, fabric_fpga_rdata_axi_m2_o15, fabric_fpga_rdata_axi_m2_o16, fabric_fpga_rdata_axi_m2_o17, fabric_fpga_rdata_axi_m2_o18, fabric_fpga_rdata_axi_m2_o19, fabric_fpga_rdata_axi_m2_o20, fabric_fpga_rdata_axi_m2_o21, fabric_fpga_rdata_axi_m2_o22, fabric_fpga_rdata_axi_m2_o23, fabric_fpga_rdata_axi_m2_o24, fabric_fpga_rdata_axi_m2_o25, fabric_fpga_rdata_axi_m2_o26, fabric_fpga_rdata_axi_m2_o27, fabric_fpga_rdata_axi_m2_o28, fabric_fpga_rdata_axi_m2_o29, fabric_fpga_rdata_axi_m2_o30, fabric_fpga_rdata_axi_m2_o31, fabric_fpga_rdata_axi_m2_o32, fabric_fpga_rdata_axi_m2_o33, fabric_fpga_rdata_axi_m2_o34, fabric_fpga_rdata_axi_m2_o35
+, fabric_fpga_rdata_axi_m2_o36, fabric_fpga_rdata_axi_m2_o37, fabric_fpga_rdata_axi_m2_o38, fabric_fpga_rdata_axi_m2_o39, fabric_fpga_rdata_axi_m2_o40, fabric_fpga_rdata_axi_m2_o41, fabric_fpga_rdata_axi_m2_o42, fabric_fpga_rdata_axi_m2_o43, fabric_fpga_rdata_axi_m2_o44, fabric_fpga_rdata_axi_m2_o45, fabric_fpga_rdata_axi_m2_o46, fabric_fpga_rdata_axi_m2_o47, fabric_fpga_rdata_axi_m2_o48, fabric_fpga_rdata_axi_m2_o49, fabric_fpga_rdata_axi_m2_o50, fabric_fpga_rdata_axi_m2_o51, fabric_fpga_rdata_axi_m2_o52, fabric_fpga_rdata_axi_m2_o53, fabric_fpga_rdata_axi_m2_o54, fabric_fpga_rdata_axi_m2_o55, fabric_fpga_rdata_axi_m2_o56
+, fabric_fpga_rdata_axi_m2_o57, fabric_fpga_rdata_axi_m2_o58, fabric_fpga_rdata_axi_m2_o59, fabric_fpga_rdata_axi_m2_o60, fabric_fpga_rdata_axi_m2_o61, fabric_fpga_rdata_axi_m2_o62, fabric_fpga_rdata_axi_m2_o63, fabric_fpga_rdata_axi_m2_o64, fabric_fpga_rdata_axi_m2_o65, fabric_fpga_rdata_axi_m2_o66, fabric_fpga_rdata_axi_m2_o67, fabric_fpga_rdata_axi_m2_o68, fabric_fpga_rdata_axi_m2_o69, fabric_fpga_rdata_axi_m2_o70, fabric_fpga_rdata_axi_m2_o71, fabric_fpga_rdata_axi_m2_o72, fabric_fpga_rdata_axi_m2_o73, fabric_fpga_rdata_axi_m2_o74, fabric_fpga_rdata_axi_m2_o75, fabric_fpga_rdata_axi_m2_o76, fabric_fpga_rdata_axi_m2_o77
+, fabric_fpga_rdata_axi_m2_o78, fabric_fpga_rdata_axi_m2_o79, fabric_fpga_rdata_axi_m2_o80, fabric_fpga_rdata_axi_m2_o81, fabric_fpga_rdata_axi_m2_o82, fabric_fpga_rdata_axi_m2_o83, fabric_fpga_rdata_axi_m2_o84, fabric_fpga_rdata_axi_m2_o85, fabric_fpga_rdata_axi_m2_o86, fabric_fpga_rdata_axi_m2_o87, fabric_fpga_rdata_axi_m2_o88, fabric_fpga_rdata_axi_m2_o89, fabric_fpga_rdata_axi_m2_o90, fabric_fpga_rdata_axi_m2_o91, fabric_fpga_rdata_axi_m2_o92, fabric_fpga_rdata_axi_m2_o93, fabric_fpga_rdata_axi_m2_o94, fabric_fpga_rdata_axi_m2_o95, fabric_fpga_rdata_axi_m2_o96, fabric_fpga_rdata_axi_m2_o97, fabric_fpga_rdata_axi_m2_o98
+, fabric_fpga_rdata_axi_m2_o99, fabric_fpga_rdata_axi_m2_o100, fabric_fpga_rdata_axi_m2_o101, fabric_fpga_rdata_axi_m2_o102, fabric_fpga_rdata_axi_m2_o103, fabric_fpga_rdata_axi_m2_o104, fabric_fpga_rdata_axi_m2_o105, fabric_fpga_rdata_axi_m2_o106, fabric_fpga_rdata_axi_m2_o107, fabric_fpga_rdata_axi_m2_o108, fabric_fpga_rdata_axi_m2_o109, fabric_fpga_rdata_axi_m2_o110, fabric_fpga_rdata_axi_m2_o111, fabric_fpga_rdata_axi_m2_o112, fabric_fpga_rdata_axi_m2_o113, fabric_fpga_rdata_axi_m2_o114, fabric_fpga_rdata_axi_m2_o115, fabric_fpga_rdata_axi_m2_o116, fabric_fpga_rdata_axi_m2_o117, fabric_fpga_rdata_axi_m2_o118, fabric_fpga_rdata_axi_m2_o119
+, fabric_fpga_rdata_axi_m2_o120, fabric_fpga_rdata_axi_m2_o121, fabric_fpga_rdata_axi_m2_o122, fabric_fpga_rdata_axi_m2_o123, fabric_fpga_rdata_axi_m2_o124, fabric_fpga_rdata_axi_m2_o125, fabric_fpga_rdata_axi_m2_o126, fabric_fpga_rdata_axi_m2_o127, fabric_fpga_rdata_axi_m2_o128, fabric_fpga_rid_axi_m2_o1, fabric_fpga_rid_axi_m2_o2, fabric_fpga_rid_axi_m2_o3, fabric_fpga_rid_axi_m2_o4, fabric_fpga_rid_axi_m2_o5, fabric_fpga_rlast_axi_m2_o, fabric_fpga_rresp_axi_m2_o1, fabric_fpga_rresp_axi_m2_o2, fabric_fpga_rvalid_axi_m2_o, fabric_fpga_wready_axi_m2_o, fabric_fpga_araddr_axi_m2_i1, fabric_fpga_araddr_axi_m2_i2
+, fabric_fpga_araddr_axi_m2_i3, fabric_fpga_araddr_axi_m2_i4, fabric_fpga_araddr_axi_m2_i5, fabric_fpga_araddr_axi_m2_i6, fabric_fpga_araddr_axi_m2_i7, fabric_fpga_araddr_axi_m2_i8, fabric_fpga_araddr_axi_m2_i9, fabric_fpga_araddr_axi_m2_i10, fabric_fpga_araddr_axi_m2_i11, fabric_fpga_araddr_axi_m2_i12, fabric_fpga_araddr_axi_m2_i13, fabric_fpga_araddr_axi_m2_i14, fabric_fpga_araddr_axi_m2_i15, fabric_fpga_araddr_axi_m2_i16, fabric_fpga_araddr_axi_m2_i17, fabric_fpga_araddr_axi_m2_i18, fabric_fpga_araddr_axi_m2_i19, fabric_fpga_araddr_axi_m2_i20, fabric_fpga_araddr_axi_m2_i21, fabric_fpga_araddr_axi_m2_i22, fabric_fpga_araddr_axi_m2_i23
+, fabric_fpga_araddr_axi_m2_i24, fabric_fpga_araddr_axi_m2_i25, fabric_fpga_araddr_axi_m2_i26, fabric_fpga_araddr_axi_m2_i27, fabric_fpga_araddr_axi_m2_i28, fabric_fpga_araddr_axi_m2_i29, fabric_fpga_araddr_axi_m2_i30, fabric_fpga_araddr_axi_m2_i31, fabric_fpga_araddr_axi_m2_i32, fabric_fpga_araddr_axi_m2_i33, fabric_fpga_araddr_axi_m2_i34, fabric_fpga_araddr_axi_m2_i35, fabric_fpga_araddr_axi_m2_i36, fabric_fpga_araddr_axi_m2_i37, fabric_fpga_araddr_axi_m2_i38, fabric_fpga_araddr_axi_m2_i39, fabric_fpga_araddr_axi_m2_i40, fabric_fpga_arburst_axi_m2_i1, fabric_fpga_arburst_axi_m2_i2, fabric_fpga_arcache_axi_m2_i1, fabric_fpga_arcache_axi_m2_i2
+, fabric_fpga_arcache_axi_m2_i3, fabric_fpga_arcache_axi_m2_i4, fabric_fpga_arid_axi_m2_i1, fabric_fpga_arid_axi_m2_i2, fabric_fpga_arid_axi_m2_i3, fabric_fpga_arid_axi_m2_i4, fabric_fpga_arid_axi_m2_i5, fabric_fpga_arlen_axi_m2_i1, fabric_fpga_arlen_axi_m2_i2, fabric_fpga_arlen_axi_m2_i3, fabric_fpga_arlen_axi_m2_i4, fabric_fpga_arlen_axi_m2_i5, fabric_fpga_arlen_axi_m2_i6, fabric_fpga_arlen_axi_m2_i7, fabric_fpga_arlen_axi_m2_i8, fabric_fpga_arlock_axi_m2_i, fabric_fpga_arprot_axi_m2_i1, fabric_fpga_arprot_axi_m2_i2, fabric_fpga_arprot_axi_m2_i3, fabric_fpga_arqos_axi_m2_i1, fabric_fpga_arqos_axi_m2_i2
+, fabric_fpga_arqos_axi_m2_i3, fabric_fpga_arqos_axi_m2_i4, fabric_fpga_arsize_axi_m2_i1, fabric_fpga_arsize_axi_m2_i2, fabric_fpga_arsize_axi_m2_i3, fabric_fpga_arvalid_axi_m2_i, fabric_fpga_awaddr_axi_m2_i1, fabric_fpga_awaddr_axi_m2_i2, fabric_fpga_awaddr_axi_m2_i3, fabric_fpga_awaddr_axi_m2_i4, fabric_fpga_awaddr_axi_m2_i5, fabric_fpga_awaddr_axi_m2_i6, fabric_fpga_awaddr_axi_m2_i7, fabric_fpga_awaddr_axi_m2_i8, fabric_fpga_awaddr_axi_m2_i9, fabric_fpga_awaddr_axi_m2_i10, fabric_fpga_awaddr_axi_m2_i11, fabric_fpga_awaddr_axi_m2_i12, fabric_fpga_awaddr_axi_m2_i13, fabric_fpga_awaddr_axi_m2_i14, fabric_fpga_awaddr_axi_m2_i15
+, fabric_fpga_awaddr_axi_m2_i16, fabric_fpga_awaddr_axi_m2_i17, fabric_fpga_awaddr_axi_m2_i18, fabric_fpga_awaddr_axi_m2_i19, fabric_fpga_awaddr_axi_m2_i20, fabric_fpga_awaddr_axi_m2_i21, fabric_fpga_awaddr_axi_m2_i22, fabric_fpga_awaddr_axi_m2_i23, fabric_fpga_awaddr_axi_m2_i24, fabric_fpga_awaddr_axi_m2_i25, fabric_fpga_awaddr_axi_m2_i26, fabric_fpga_awaddr_axi_m2_i27, fabric_fpga_awaddr_axi_m2_i28, fabric_fpga_awaddr_axi_m2_i29, fabric_fpga_awaddr_axi_m2_i30, fabric_fpga_awaddr_axi_m2_i31, fabric_fpga_awaddr_axi_m2_i32, fabric_fpga_awaddr_axi_m2_i33, fabric_fpga_awaddr_axi_m2_i34, fabric_fpga_awaddr_axi_m2_i35, fabric_fpga_awaddr_axi_m2_i36
+, fabric_fpga_awaddr_axi_m2_i37, fabric_fpga_awaddr_axi_m2_i38, fabric_fpga_awaddr_axi_m2_i39, fabric_fpga_awaddr_axi_m2_i40, fabric_fpga_awburst_axi_m2_i1, fabric_fpga_awburst_axi_m2_i2, fabric_fpga_awcache_axi_m2_i1, fabric_fpga_awcache_axi_m2_i2, fabric_fpga_awcache_axi_m2_i3, fabric_fpga_awcache_axi_m2_i4, fabric_fpga_awid_axi_m2_i1, fabric_fpga_awid_axi_m2_i2, fabric_fpga_awid_axi_m2_i3, fabric_fpga_awid_axi_m2_i4, fabric_fpga_awid_axi_m2_i5, fabric_fpga_awlen_axi_m2_i1, fabric_fpga_awlen_axi_m2_i2, fabric_fpga_awlen_axi_m2_i3, fabric_fpga_awlen_axi_m2_i4, fabric_fpga_awlen_axi_m2_i5, fabric_fpga_awlen_axi_m2_i6
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+, fabric_llpp1_arqos_s_o3, fabric_llpp1_arqos_s_o4, fabric_llpp1_arsize_s_o1, fabric_llpp1_arsize_s_o2, fabric_llpp1_arsize_s_o3, fabric_llpp1_arvalid_s_o, fabric_llpp1_awaddr_s_o1, fabric_llpp1_awaddr_s_o2, fabric_llpp1_awaddr_s_o3, fabric_llpp1_awaddr_s_o4, fabric_llpp1_awaddr_s_o5, fabric_llpp1_awaddr_s_o6, fabric_llpp1_awaddr_s_o7, fabric_llpp1_awaddr_s_o8, fabric_llpp1_awaddr_s_o9, fabric_llpp1_awaddr_s_o10, fabric_llpp1_awaddr_s_o11, fabric_llpp1_awaddr_s_o12, fabric_llpp1_awaddr_s_o13, fabric_llpp1_awaddr_s_o14, fabric_llpp1_awaddr_s_o15
+, fabric_llpp1_awaddr_s_o16, fabric_llpp1_awaddr_s_o17, fabric_llpp1_awaddr_s_o18, fabric_llpp1_awaddr_s_o19, fabric_llpp1_awaddr_s_o20, fabric_llpp1_awaddr_s_o21, fabric_llpp1_awaddr_s_o22, fabric_llpp1_awaddr_s_o23, fabric_llpp1_awaddr_s_o24, fabric_llpp1_awaddr_s_o25, fabric_llpp1_awaddr_s_o26, fabric_llpp1_awaddr_s_o27, fabric_llpp1_awaddr_s_o28, fabric_llpp1_awaddr_s_o29, fabric_llpp1_awaddr_s_o30, fabric_llpp1_awaddr_s_o31, fabric_llpp1_awaddr_s_o32, fabric_llpp1_awburst_s_o1, fabric_llpp1_awburst_s_o2, fabric_llpp1_awcache_s_o1, fabric_llpp1_awcache_s_o2
+, fabric_llpp1_awcache_s_o3, fabric_llpp1_awcache_s_o4, fabric_llpp1_awid_s_o1, fabric_llpp1_awid_s_o2, fabric_llpp1_awid_s_o3, fabric_llpp1_awid_s_o4, fabric_llpp1_awid_s_o5, fabric_llpp1_awid_s_o6, fabric_llpp1_awid_s_o7, fabric_llpp1_awid_s_o8, fabric_llpp1_awid_s_o9, fabric_llpp1_awid_s_o10, fabric_llpp1_awid_s_o11, fabric_llpp1_awid_s_o12, fabric_llpp1_awlen_s_o1, fabric_llpp1_awlen_s_o2, fabric_llpp1_awlen_s_o3, fabric_llpp1_awlen_s_o4, fabric_llpp1_awlen_s_o5, fabric_llpp1_awlen_s_o6, fabric_llpp1_awlen_s_o7
+, fabric_llpp1_awlen_s_o8, fabric_llpp1_awlock_s_o, fabric_llpp1_awprot_s_o1, fabric_llpp1_awprot_s_o2, fabric_llpp1_awprot_s_o3, fabric_llpp1_awqos_s_o1, fabric_llpp1_awqos_s_o2, fabric_llpp1_awqos_s_o3, fabric_llpp1_awqos_s_o4, fabric_llpp1_awsize_s_o1, fabric_llpp1_awsize_s_o2, fabric_llpp1_awsize_s_o3, fabric_llpp1_awvalid_s_o, fabric_llpp1_bready_s_o, fabric_llpp1_rready_s_o, fabric_llpp1_wdata_s_o1, fabric_llpp1_wdata_s_o2, fabric_llpp1_wdata_s_o3, fabric_llpp1_wdata_s_o4, fabric_llpp1_wdata_s_o5, fabric_llpp1_wdata_s_o6
+, fabric_llpp1_wdata_s_o7, fabric_llpp1_wdata_s_o8, fabric_llpp1_wdata_s_o9, fabric_llpp1_wdata_s_o10, fabric_llpp1_wdata_s_o11, fabric_llpp1_wdata_s_o12, fabric_llpp1_wdata_s_o13, fabric_llpp1_wdata_s_o14, fabric_llpp1_wdata_s_o15, fabric_llpp1_wdata_s_o16, fabric_llpp1_wdata_s_o17, fabric_llpp1_wdata_s_o18, fabric_llpp1_wdata_s_o19, fabric_llpp1_wdata_s_o20, fabric_llpp1_wdata_s_o21, fabric_llpp1_wdata_s_o22, fabric_llpp1_wdata_s_o23, fabric_llpp1_wdata_s_o24, fabric_llpp1_wdata_s_o25, fabric_llpp1_wdata_s_o26, fabric_llpp1_wdata_s_o27
+, fabric_llpp1_wdata_s_o28, fabric_llpp1_wdata_s_o29, fabric_llpp1_wdata_s_o30, fabric_llpp1_wdata_s_o31, fabric_llpp1_wdata_s_o32, fabric_llpp1_wlast_s_o, fabric_llpp1_wstrb_s_o1, fabric_llpp1_wstrb_s_o2, fabric_llpp1_wstrb_s_o3, fabric_llpp1_wstrb_s_o4, fabric_llpp1_wvalid_s_o, fabric_llpp1_arready_s_i, fabric_llpp1_awready_s_i, fabric_llpp1_bid_s_i1, fabric_llpp1_bid_s_i2, fabric_llpp1_bid_s_i3, fabric_llpp1_bid_s_i4, fabric_llpp1_bid_s_i5, fabric_llpp1_bid_s_i6, fabric_llpp1_bid_s_i7, fabric_llpp1_bid_s_i8
+, fabric_llpp1_bid_s_i9, fabric_llpp1_bid_s_i10, fabric_llpp1_bid_s_i11, fabric_llpp1_bid_s_i12, fabric_llpp1_bresp_s_i1, fabric_llpp1_bresp_s_i2, fabric_llpp1_bvalid_s_i, fabric_llpp1_rdata_s_i1, fabric_llpp1_rdata_s_i2, fabric_llpp1_rdata_s_i3, fabric_llpp1_rdata_s_i4, fabric_llpp1_rdata_s_i5, fabric_llpp1_rdata_s_i6, fabric_llpp1_rdata_s_i7, fabric_llpp1_rdata_s_i8, fabric_llpp1_rdata_s_i9, fabric_llpp1_rdata_s_i10, fabric_llpp1_rdata_s_i11, fabric_llpp1_rdata_s_i12, fabric_llpp1_rdata_s_i13, fabric_llpp1_rdata_s_i14
+, fabric_llpp1_rdata_s_i15, fabric_llpp1_rdata_s_i16, fabric_llpp1_rdata_s_i17, fabric_llpp1_rdata_s_i18, fabric_llpp1_rdata_s_i19, fabric_llpp1_rdata_s_i20, fabric_llpp1_rdata_s_i21, fabric_llpp1_rdata_s_i22, fabric_llpp1_rdata_s_i23, fabric_llpp1_rdata_s_i24, fabric_llpp1_rdata_s_i25, fabric_llpp1_rdata_s_i26, fabric_llpp1_rdata_s_i27, fabric_llpp1_rdata_s_i28, fabric_llpp1_rdata_s_i29, fabric_llpp1_rdata_s_i30, fabric_llpp1_rdata_s_i31, fabric_llpp1_rdata_s_i32, fabric_llpp1_rid_s_i1, fabric_llpp1_rid_s_i2, fabric_llpp1_rid_s_i3
+, fabric_llpp1_rid_s_i4, fabric_llpp1_rid_s_i5, fabric_llpp1_rid_s_i6, fabric_llpp1_rid_s_i7, fabric_llpp1_rid_s_i8, fabric_llpp1_rid_s_i9, fabric_llpp1_rid_s_i10, fabric_llpp1_rid_s_i11, fabric_llpp1_rid_s_i12, fabric_llpp1_rlast_s_i, fabric_llpp1_rresp_s_i1, fabric_llpp1_rresp_s_i2, fabric_llpp1_rvalid_s_i, fabric_llpp1_wready_s_i, fabric_llpp2_araddr_s_o1, fabric_llpp2_araddr_s_o2, fabric_llpp2_araddr_s_o3, fabric_llpp2_araddr_s_o4, fabric_llpp2_araddr_s_o5, fabric_llpp2_araddr_s_o6, fabric_llpp2_araddr_s_o7
+, fabric_llpp2_araddr_s_o8, fabric_llpp2_araddr_s_o9, fabric_llpp2_araddr_s_o10, fabric_llpp2_araddr_s_o11, fabric_llpp2_araddr_s_o12, fabric_llpp2_araddr_s_o13, fabric_llpp2_araddr_s_o14, fabric_llpp2_araddr_s_o15, fabric_llpp2_araddr_s_o16, fabric_llpp2_araddr_s_o17, fabric_llpp2_araddr_s_o18, fabric_llpp2_araddr_s_o19, fabric_llpp2_araddr_s_o20, fabric_llpp2_araddr_s_o21, fabric_llpp2_araddr_s_o22, fabric_llpp2_araddr_s_o23, fabric_llpp2_araddr_s_o24, fabric_llpp2_araddr_s_o25, fabric_llpp2_araddr_s_o26, fabric_llpp2_araddr_s_o27, fabric_llpp2_araddr_s_o28
+, fabric_llpp2_araddr_s_o29, fabric_llpp2_araddr_s_o30, fabric_llpp2_araddr_s_o31, fabric_llpp2_araddr_s_o32, fabric_llpp2_arburst_s_o1, fabric_llpp2_arburst_s_o2, fabric_llpp2_arcache_s_o1, fabric_llpp2_arcache_s_o2, fabric_llpp2_arcache_s_o3, fabric_llpp2_arcache_s_o4, fabric_llpp2_arid_s_o1, fabric_llpp2_arid_s_o2, fabric_llpp2_arid_s_o3, fabric_llpp2_arid_s_o4, fabric_llpp2_arid_s_o5, fabric_llpp2_arid_s_o6, fabric_llpp2_arid_s_o7, fabric_llpp2_arid_s_o8, fabric_llpp2_arid_s_o9, fabric_llpp2_arid_s_o10, fabric_llpp2_arid_s_o11
+, fabric_llpp2_arid_s_o12, fabric_llpp2_arlen_s_o1, fabric_llpp2_arlen_s_o2, fabric_llpp2_arlen_s_o3, fabric_llpp2_arlen_s_o4, fabric_llpp2_arlen_s_o5, fabric_llpp2_arlen_s_o6, fabric_llpp2_arlen_s_o7, fabric_llpp2_arlen_s_o8, fabric_llpp2_arlock_s_o, fabric_llpp2_arprot_s_o1, fabric_llpp2_arprot_s_o2, fabric_llpp2_arprot_s_o3, fabric_llpp2_arqos_s_o1, fabric_llpp2_arqos_s_o2, fabric_llpp2_arqos_s_o3, fabric_llpp2_arqos_s_o4, fabric_llpp2_arsize_s_o1, fabric_llpp2_arsize_s_o2, fabric_llpp2_arsize_s_o3, fabric_llpp2_arvalid_s_o
+, fabric_llpp2_awaddr_s_o1, fabric_llpp2_awaddr_s_o2, fabric_llpp2_awaddr_s_o3, fabric_llpp2_awaddr_s_o4, fabric_llpp2_awaddr_s_o5, fabric_llpp2_awaddr_s_o6, fabric_llpp2_awaddr_s_o7, fabric_llpp2_awaddr_s_o8, fabric_llpp2_awaddr_s_o9, fabric_llpp2_awaddr_s_o10, fabric_llpp2_awaddr_s_o11, fabric_llpp2_awaddr_s_o12, fabric_llpp2_awaddr_s_o13, fabric_llpp2_awaddr_s_o14, fabric_llpp2_awaddr_s_o15, fabric_llpp2_awaddr_s_o16, fabric_llpp2_awaddr_s_o17, fabric_llpp2_awaddr_s_o18, fabric_llpp2_awaddr_s_o19, fabric_llpp2_awaddr_s_o20, fabric_llpp2_awaddr_s_o21
+, fabric_llpp2_awaddr_s_o22, fabric_llpp2_awaddr_s_o23, fabric_llpp2_awaddr_s_o24, fabric_llpp2_awaddr_s_o25, fabric_llpp2_awaddr_s_o26, fabric_llpp2_awaddr_s_o27, fabric_llpp2_awaddr_s_o28, fabric_llpp2_awaddr_s_o29, fabric_llpp2_awaddr_s_o30, fabric_llpp2_awaddr_s_o31, fabric_llpp2_awaddr_s_o32, fabric_llpp2_awburst_s_o1, fabric_llpp2_awburst_s_o2, fabric_llpp2_awcache_s_o1, fabric_llpp2_awcache_s_o2, fabric_llpp2_awcache_s_o3, fabric_llpp2_awcache_s_o4, fabric_llpp2_awid_s_o1, fabric_llpp2_awid_s_o2, fabric_llpp2_awid_s_o3, fabric_llpp2_awid_s_o4
+, fabric_llpp2_awid_s_o5, fabric_llpp2_awid_s_o6, fabric_llpp2_awid_s_o7, fabric_llpp2_awid_s_o8, fabric_llpp2_awid_s_o9, fabric_llpp2_awid_s_o10, fabric_llpp2_awid_s_o11, fabric_llpp2_awid_s_o12, fabric_llpp2_awlen_s_o1, fabric_llpp2_awlen_s_o2, fabric_llpp2_awlen_s_o3, fabric_llpp2_awlen_s_o4, fabric_llpp2_awlen_s_o5, fabric_llpp2_awlen_s_o6, fabric_llpp2_awlen_s_o7, fabric_llpp2_awlen_s_o8, fabric_llpp2_awlock_s_o, fabric_llpp2_awprot_s_o1, fabric_llpp2_awprot_s_o2, fabric_llpp2_awprot_s_o3, fabric_llpp2_awqos_s_o1
+, fabric_llpp2_awqos_s_o2, fabric_llpp2_awqos_s_o3, fabric_llpp2_awqos_s_o4, fabric_llpp2_awsize_s_o1, fabric_llpp2_awsize_s_o2, fabric_llpp2_awsize_s_o3, fabric_llpp2_awvalid_s_o, fabric_llpp2_bready_s_o, fabric_llpp2_rready_s_o, fabric_llpp2_wdata_s_o1, fabric_llpp2_wdata_s_o2, fabric_llpp2_wdata_s_o3, fabric_llpp2_wdata_s_o4, fabric_llpp2_wdata_s_o5, fabric_llpp2_wdata_s_o6, fabric_llpp2_wdata_s_o7, fabric_llpp2_wdata_s_o8, fabric_llpp2_wdata_s_o9, fabric_llpp2_wdata_s_o10, fabric_llpp2_wdata_s_o11, fabric_llpp2_wdata_s_o12
+, fabric_llpp2_wdata_s_o13, fabric_llpp2_wdata_s_o14, fabric_llpp2_wdata_s_o15, fabric_llpp2_wdata_s_o16, fabric_llpp2_wdata_s_o17, fabric_llpp2_wdata_s_o18, fabric_llpp2_wdata_s_o19, fabric_llpp2_wdata_s_o20, fabric_llpp2_wdata_s_o21, fabric_llpp2_wdata_s_o22, fabric_llpp2_wdata_s_o23, fabric_llpp2_wdata_s_o24, fabric_llpp2_wdata_s_o25, fabric_llpp2_wdata_s_o26, fabric_llpp2_wdata_s_o27, fabric_llpp2_wdata_s_o28, fabric_llpp2_wdata_s_o29, fabric_llpp2_wdata_s_o30, fabric_llpp2_wdata_s_o31, fabric_llpp2_wdata_s_o32, fabric_llpp2_wlast_s_o
+, fabric_llpp2_wstrb_s_o1, fabric_llpp2_wstrb_s_o2, fabric_llpp2_wstrb_s_o3, fabric_llpp2_wstrb_s_o4, fabric_llpp2_wvalid_s_o, fabric_llpp2_arready_s_i, fabric_llpp2_awready_s_i, fabric_llpp2_bid_s_i1, fabric_llpp2_bid_s_i2, fabric_llpp2_bid_s_i3, fabric_llpp2_bid_s_i4, fabric_llpp2_bid_s_i5, fabric_llpp2_bid_s_i6, fabric_llpp2_bid_s_i7, fabric_llpp2_bid_s_i8, fabric_llpp2_bid_s_i9, fabric_llpp2_bid_s_i10, fabric_llpp2_bid_s_i11, fabric_llpp2_bid_s_i12, fabric_llpp2_bresp_s_i1, fabric_llpp2_bresp_s_i2
+, fabric_llpp2_bvalid_s_i, fabric_llpp2_rdata_s_i1, fabric_llpp2_rdata_s_i2, fabric_llpp2_rdata_s_i3, fabric_llpp2_rdata_s_i4, fabric_llpp2_rdata_s_i5, fabric_llpp2_rdata_s_i6, fabric_llpp2_rdata_s_i7, fabric_llpp2_rdata_s_i8, fabric_llpp2_rdata_s_i9, fabric_llpp2_rdata_s_i10, fabric_llpp2_rdata_s_i11, fabric_llpp2_rdata_s_i12, fabric_llpp2_rdata_s_i13, fabric_llpp2_rdata_s_i14, fabric_llpp2_rdata_s_i15, fabric_llpp2_rdata_s_i16, fabric_llpp2_rdata_s_i17, fabric_llpp2_rdata_s_i18, fabric_llpp2_rdata_s_i19, fabric_llpp2_rdata_s_i20
+, fabric_llpp2_rdata_s_i21, fabric_llpp2_rdata_s_i22, fabric_llpp2_rdata_s_i23, fabric_llpp2_rdata_s_i24, fabric_llpp2_rdata_s_i25, fabric_llpp2_rdata_s_i26, fabric_llpp2_rdata_s_i27, fabric_llpp2_rdata_s_i28, fabric_llpp2_rdata_s_i29, fabric_llpp2_rdata_s_i30, fabric_llpp2_rdata_s_i31, fabric_llpp2_rdata_s_i32, fabric_llpp2_rid_s_i1, fabric_llpp2_rid_s_i2, fabric_llpp2_rid_s_i3, fabric_llpp2_rid_s_i4, fabric_llpp2_rid_s_i5, fabric_llpp2_rid_s_i6, fabric_llpp2_rid_s_i7, fabric_llpp2_rid_s_i8, fabric_llpp2_rid_s_i9
+, fabric_llpp2_rid_s_i10, fabric_llpp2_rid_s_i11, fabric_llpp2_rid_s_i12, fabric_llpp2_rlast_s_i, fabric_llpp2_rresp_s_i1, fabric_llpp2_rresp_s_i2, fabric_llpp2_rvalid_s_i, fabric_llpp2_wready_s_i, fabric_llpp3_araddr_s_o1, fabric_llpp3_araddr_s_o2, fabric_llpp3_araddr_s_o3, fabric_llpp3_araddr_s_o4, fabric_llpp3_araddr_s_o5, fabric_llpp3_araddr_s_o6, fabric_llpp3_araddr_s_o7, fabric_llpp3_araddr_s_o8, fabric_llpp3_araddr_s_o9, fabric_llpp3_araddr_s_o10, fabric_llpp3_araddr_s_o11, fabric_llpp3_araddr_s_o12, fabric_llpp3_araddr_s_o13
+, fabric_llpp3_araddr_s_o14, fabric_llpp3_araddr_s_o15, fabric_llpp3_araddr_s_o16, fabric_llpp3_araddr_s_o17, fabric_llpp3_araddr_s_o18, fabric_llpp3_araddr_s_o19, fabric_llpp3_araddr_s_o20, fabric_llpp3_araddr_s_o21, fabric_llpp3_araddr_s_o22, fabric_llpp3_araddr_s_o23, fabric_llpp3_araddr_s_o24, fabric_llpp3_araddr_s_o25, fabric_llpp3_araddr_s_o26, fabric_llpp3_araddr_s_o27, fabric_llpp3_araddr_s_o28, fabric_llpp3_araddr_s_o29, fabric_llpp3_araddr_s_o30, fabric_llpp3_araddr_s_o31, fabric_llpp3_araddr_s_o32, fabric_llpp3_arburst_s_o1, fabric_llpp3_arburst_s_o2
+, fabric_llpp3_arcache_s_o1, fabric_llpp3_arcache_s_o2, fabric_llpp3_arcache_s_o3, fabric_llpp3_arcache_s_o4, fabric_llpp3_arid_s_o1, fabric_llpp3_arid_s_o2, fabric_llpp3_arid_s_o3, fabric_llpp3_arid_s_o4, fabric_llpp3_arid_s_o5, fabric_llpp3_arid_s_o6, fabric_llpp3_arid_s_o7, fabric_llpp3_arid_s_o8, fabric_llpp3_arid_s_o9, fabric_llpp3_arid_s_o10, fabric_llpp3_arid_s_o11, fabric_llpp3_arid_s_o12, fabric_llpp3_arlen_s_o1, fabric_llpp3_arlen_s_o2, fabric_llpp3_arlen_s_o3, fabric_llpp3_arlen_s_o4, fabric_llpp3_arlen_s_o5
+, fabric_llpp3_arlen_s_o6, fabric_llpp3_arlen_s_o7, fabric_llpp3_arlen_s_o8, fabric_llpp3_arlock_s_o, fabric_llpp3_arprot_s_o1, fabric_llpp3_arprot_s_o2, fabric_llpp3_arprot_s_o3, fabric_llpp3_arqos_s_o1, fabric_llpp3_arqos_s_o2, fabric_llpp3_arqos_s_o3, fabric_llpp3_arqos_s_o4, fabric_llpp3_arsize_s_o1, fabric_llpp3_arsize_s_o2, fabric_llpp3_arsize_s_o3, fabric_llpp3_arvalid_s_o, fabric_llpp3_awaddr_s_o1, fabric_llpp3_awaddr_s_o2, fabric_llpp3_awaddr_s_o3, fabric_llpp3_awaddr_s_o4, fabric_llpp3_awaddr_s_o5, fabric_llpp3_awaddr_s_o6
+, fabric_llpp3_awaddr_s_o7, fabric_llpp3_awaddr_s_o8, fabric_llpp3_awaddr_s_o9, fabric_llpp3_awaddr_s_o10, fabric_llpp3_awaddr_s_o11, fabric_llpp3_awaddr_s_o12, fabric_llpp3_awaddr_s_o13, fabric_llpp3_awaddr_s_o14, fabric_llpp3_awaddr_s_o15, fabric_llpp3_awaddr_s_o16, fabric_llpp3_awaddr_s_o17, fabric_llpp3_awaddr_s_o18, fabric_llpp3_awaddr_s_o19, fabric_llpp3_awaddr_s_o20, fabric_llpp3_awaddr_s_o21, fabric_llpp3_awaddr_s_o22, fabric_llpp3_awaddr_s_o23, fabric_llpp3_awaddr_s_o24, fabric_llpp3_awaddr_s_o25, fabric_llpp3_awaddr_s_o26, fabric_llpp3_awaddr_s_o27
+, fabric_llpp3_awaddr_s_o28, fabric_llpp3_awaddr_s_o29, fabric_llpp3_awaddr_s_o30, fabric_llpp3_awaddr_s_o31, fabric_llpp3_awaddr_s_o32, fabric_llpp3_awburst_s_o1, fabric_llpp3_awburst_s_o2, fabric_llpp3_awcache_s_o1, fabric_llpp3_awcache_s_o2, fabric_llpp3_awcache_s_o3, fabric_llpp3_awcache_s_o4, fabric_llpp3_awid_s_o1, fabric_llpp3_awid_s_o2, fabric_llpp3_awid_s_o3, fabric_llpp3_awid_s_o4, fabric_llpp3_awid_s_o5, fabric_llpp3_awid_s_o6, fabric_llpp3_awid_s_o7, fabric_llpp3_awid_s_o8, fabric_llpp3_awid_s_o9, fabric_llpp3_awid_s_o10
+, fabric_llpp3_awid_s_o11, fabric_llpp3_awid_s_o12, fabric_llpp3_awlen_s_o1, fabric_llpp3_awlen_s_o2, fabric_llpp3_awlen_s_o3, fabric_llpp3_awlen_s_o4, fabric_llpp3_awlen_s_o5, fabric_llpp3_awlen_s_o6, fabric_llpp3_awlen_s_o7, fabric_llpp3_awlen_s_o8, fabric_llpp3_awlock_s_o, fabric_llpp3_awprot_s_o1, fabric_llpp3_awprot_s_o2, fabric_llpp3_awprot_s_o3, fabric_llpp3_awqos_s_o1, fabric_llpp3_awqos_s_o2, fabric_llpp3_awqos_s_o3, fabric_llpp3_awqos_s_o4, fabric_llpp3_awsize_s_o1, fabric_llpp3_awsize_s_o2, fabric_llpp3_awsize_s_o3
+, fabric_llpp3_awvalid_s_o, fabric_llpp3_bready_s_o, fabric_llpp3_rready_s_o, fabric_llpp3_wdata_s_o1, fabric_llpp3_wdata_s_o2, fabric_llpp3_wdata_s_o3, fabric_llpp3_wdata_s_o4, fabric_llpp3_wdata_s_o5, fabric_llpp3_wdata_s_o6, fabric_llpp3_wdata_s_o7, fabric_llpp3_wdata_s_o8, fabric_llpp3_wdata_s_o9, fabric_llpp3_wdata_s_o10, fabric_llpp3_wdata_s_o11, fabric_llpp3_wdata_s_o12, fabric_llpp3_wdata_s_o13, fabric_llpp3_wdata_s_o14, fabric_llpp3_wdata_s_o15, fabric_llpp3_wdata_s_o16, fabric_llpp3_wdata_s_o17, fabric_llpp3_wdata_s_o18
+, fabric_llpp3_wdata_s_o19, fabric_llpp3_wdata_s_o20, fabric_llpp3_wdata_s_o21, fabric_llpp3_wdata_s_o22, fabric_llpp3_wdata_s_o23, fabric_llpp3_wdata_s_o24, fabric_llpp3_wdata_s_o25, fabric_llpp3_wdata_s_o26, fabric_llpp3_wdata_s_o27, fabric_llpp3_wdata_s_o28, fabric_llpp3_wdata_s_o29, fabric_llpp3_wdata_s_o30, fabric_llpp3_wdata_s_o31, fabric_llpp3_wdata_s_o32, fabric_llpp3_wlast_s_o, fabric_llpp3_wstrb_s_o1, fabric_llpp3_wstrb_s_o2, fabric_llpp3_wstrb_s_o3, fabric_llpp3_wstrb_s_o4, fabric_llpp3_wvalid_s_o, fabric_llpp3_arready_s_i
+, fabric_llpp3_awready_s_i, fabric_llpp3_bid_s_i1, fabric_llpp3_bid_s_i2, fabric_llpp3_bid_s_i3, fabric_llpp3_bid_s_i4, fabric_llpp3_bid_s_i5, fabric_llpp3_bid_s_i6, fabric_llpp3_bid_s_i7, fabric_llpp3_bid_s_i8, fabric_llpp3_bid_s_i9, fabric_llpp3_bid_s_i10, fabric_llpp3_bid_s_i11, fabric_llpp3_bid_s_i12, fabric_llpp3_bresp_s_i1, fabric_llpp3_bresp_s_i2, fabric_llpp3_bvalid_s_i, fabric_llpp3_rdata_s_i1, fabric_llpp3_rdata_s_i2, fabric_llpp3_rdata_s_i3, fabric_llpp3_rdata_s_i4, fabric_llpp3_rdata_s_i5
+, fabric_llpp3_rdata_s_i6, fabric_llpp3_rdata_s_i7, fabric_llpp3_rdata_s_i8, fabric_llpp3_rdata_s_i9, fabric_llpp3_rdata_s_i10, fabric_llpp3_rdata_s_i11, fabric_llpp3_rdata_s_i12, fabric_llpp3_rdata_s_i13, fabric_llpp3_rdata_s_i14, fabric_llpp3_rdata_s_i15, fabric_llpp3_rdata_s_i16, fabric_llpp3_rdata_s_i17, fabric_llpp3_rdata_s_i18, fabric_llpp3_rdata_s_i19, fabric_llpp3_rdata_s_i20, fabric_llpp3_rdata_s_i21, fabric_llpp3_rdata_s_i22, fabric_llpp3_rdata_s_i23, fabric_llpp3_rdata_s_i24, fabric_llpp3_rdata_s_i25, fabric_llpp3_rdata_s_i26
+, fabric_llpp3_rdata_s_i27, fabric_llpp3_rdata_s_i28, fabric_llpp3_rdata_s_i29, fabric_llpp3_rdata_s_i30, fabric_llpp3_rdata_s_i31, fabric_llpp3_rdata_s_i32, fabric_llpp3_rid_s_i1, fabric_llpp3_rid_s_i2, fabric_llpp3_rid_s_i3, fabric_llpp3_rid_s_i4, fabric_llpp3_rid_s_i5, fabric_llpp3_rid_s_i6, fabric_llpp3_rid_s_i7, fabric_llpp3_rid_s_i8, fabric_llpp3_rid_s_i9, fabric_llpp3_rid_s_i10, fabric_llpp3_rid_s_i11, fabric_llpp3_rid_s_i12, fabric_llpp3_rlast_s_i, fabric_llpp3_rresp_s_i1, fabric_llpp3_rresp_s_i2
+, fabric_llpp3_rvalid_s_i, fabric_llpp3_wready_s_i, fabric_qos_pprdata_o1, fabric_qos_pprdata_o2, fabric_qos_pprdata_o3, fabric_qos_pprdata_o4, fabric_qos_pprdata_o5, fabric_qos_pprdata_o6, fabric_qos_pprdata_o7, fabric_qos_pprdata_o8, fabric_qos_pprdata_o9, fabric_qos_pprdata_o10, fabric_qos_pprdata_o11, fabric_qos_pprdata_o12, fabric_qos_pprdata_o13, fabric_qos_pprdata_o14, fabric_qos_pprdata_o15, fabric_qos_pprdata_o16, fabric_qos_pprdata_o17, fabric_qos_pprdata_o18, fabric_qos_pprdata_o19
+, fabric_qos_pprdata_o20, fabric_qos_pprdata_o21, fabric_qos_pprdata_o22, fabric_qos_pprdata_o23, fabric_qos_pprdata_o24, fabric_qos_pprdata_o25, fabric_qos_pprdata_o26, fabric_qos_pprdata_o27, fabric_qos_pprdata_o28, fabric_qos_pprdata_o29, fabric_qos_pprdata_o30, fabric_qos_pprdata_o31, fabric_qos_pprdata_o32, fabric_qos_ppready_o, fabric_qos_ppslverr_o, fabric_qos_ppaddr_i1, fabric_qos_ppaddr_i2, fabric_qos_ppaddr_i3, fabric_qos_ppaddr_i4, fabric_qos_ppaddr_i5, fabric_qos_ppaddr_i6
+, fabric_qos_ppaddr_i7, fabric_qos_ppaddr_i8, fabric_qos_ppaddr_i9, fabric_qos_ppaddr_i10, fabric_qos_ppaddr_i11, fabric_qos_ppaddr_i12, fabric_qos_ppaddr_i13, fabric_qos_ppaddr_i14, fabric_qos_ppaddr_i15, fabric_qos_ppaddr_i16, fabric_qos_ppaddr_i17, fabric_qos_ppaddr_i18, fabric_qos_ppaddr_i19, fabric_qos_ppaddr_i20, fabric_qos_ppaddr_i21, fabric_qos_ppaddr_i22, fabric_qos_ppaddr_i23, fabric_qos_ppaddr_i24, fabric_qos_ppaddr_i25, fabric_qos_ppaddr_i26, fabric_qos_ppaddr_i27
+, fabric_qos_ppaddr_i28, fabric_qos_ppaddr_i29, fabric_qos_ppaddr_i30, fabric_qos_ppaddr_i31, fabric_qos_ppaddr_i32, fabric_qos_ppenable_i, fabric_qos_ppwdata_i1, fabric_qos_ppwdata_i2, fabric_qos_ppwdata_i3, fabric_qos_ppwdata_i4, fabric_qos_ppwdata_i5, fabric_qos_ppwdata_i6, fabric_qos_ppwdata_i7, fabric_qos_ppwdata_i8, fabric_qos_ppwdata_i9, fabric_qos_ppwdata_i10, fabric_qos_ppwdata_i11, fabric_qos_ppwdata_i12, fabric_qos_ppwdata_i13, fabric_qos_ppwdata_i14, fabric_qos_ppwdata_i15
+, fabric_qos_ppwdata_i16, fabric_qos_ppwdata_i17, fabric_qos_ppwdata_i18, fabric_qos_ppwdata_i19, fabric_qos_ppwdata_i20, fabric_qos_ppwdata_i21, fabric_qos_ppwdata_i22, fabric_qos_ppwdata_i23, fabric_qos_ppwdata_i24, fabric_qos_ppwdata_i25, fabric_qos_ppwdata_i26, fabric_qos_ppwdata_i27, fabric_qos_ppwdata_i28, fabric_qos_ppwdata_i29, fabric_qos_ppwdata_i30, fabric_qos_ppwdata_i31, fabric_qos_ppwdata_i32, fabric_qos_ppwrite_i, fabric_qos_presetn_i, fabric_qos_psel_i, fabric_tnd_hssl_flushin_o
+, fabric_tnd_hssl_trigin_o, fabric_tnd_fpga_apb_master_paddr_o1, fabric_tnd_fpga_apb_master_paddr_o2, fabric_tnd_fpga_apb_master_paddr_o3, fabric_tnd_fpga_apb_master_paddr_o4, fabric_tnd_fpga_apb_master_paddr_o5, fabric_tnd_fpga_apb_master_paddr_o6, fabric_tnd_fpga_apb_master_paddr_o7, fabric_tnd_fpga_apb_master_paddr_o8, fabric_tnd_fpga_apb_master_paddr_o9, fabric_tnd_fpga_apb_master_paddr_o10, fabric_tnd_fpga_apb_master_paddr_o11, fabric_tnd_fpga_apb_master_paddr_o12, fabric_tnd_fpga_apb_master_paddr_o13, fabric_tnd_fpga_apb_master_paddr_o14, fabric_tnd_fpga_apb_master_paddr_o15, fabric_tnd_fpga_apb_master_paddr_o16, fabric_tnd_fpga_apb_master_paddr_o17, fabric_tnd_fpga_apb_master_paddr_o18, fabric_tnd_fpga_apb_master_paddr_o19, fabric_tnd_fpga_apb_master_paddr_o20
+, fabric_tnd_fpga_apb_master_paddr_o21, fabric_tnd_fpga_apb_master_paddr_o22, fabric_tnd_fpga_apb_master_paddr_o23, fabric_tnd_fpga_apb_master_paddr_o24, fabric_tnd_fpga_apb_master_paddr_o25, fabric_tnd_fpga_apb_master_paddr_o26, fabric_tnd_fpga_apb_master_paddr_o27, fabric_tnd_fpga_apb_master_paddr_o28, fabric_tnd_fpga_apb_master_paddr_o29, fabric_tnd_fpga_apb_master_paddr_o30, fabric_tnd_fpga_apb_master_paddr_o31, fabric_tnd_fpga_apb_master_paddr_o32, fabric_tnd_fpga_apb_master_penable_o, fabric_tnd_fpga_apb_master_psel_o, fabric_tnd_fpga_apb_master_pwdata_o1, fabric_tnd_fpga_apb_master_pwdata_o2, fabric_tnd_fpga_apb_master_pwdata_o3, fabric_tnd_fpga_apb_master_pwdata_o4, fabric_tnd_fpga_apb_master_pwdata_o5, fabric_tnd_fpga_apb_master_pwdata_o6, fabric_tnd_fpga_apb_master_pwdata_o7
+, fabric_tnd_fpga_apb_master_pwdata_o8, fabric_tnd_fpga_apb_master_pwdata_o9, fabric_tnd_fpga_apb_master_pwdata_o10, fabric_tnd_fpga_apb_master_pwdata_o11, fabric_tnd_fpga_apb_master_pwdata_o12, fabric_tnd_fpga_apb_master_pwdata_o13, fabric_tnd_fpga_apb_master_pwdata_o14, fabric_tnd_fpga_apb_master_pwdata_o15, fabric_tnd_fpga_apb_master_pwdata_o16, fabric_tnd_fpga_apb_master_pwdata_o17, fabric_tnd_fpga_apb_master_pwdata_o18, fabric_tnd_fpga_apb_master_pwdata_o19, fabric_tnd_fpga_apb_master_pwdata_o20, fabric_tnd_fpga_apb_master_pwdata_o21, fabric_tnd_fpga_apb_master_pwdata_o22, fabric_tnd_fpga_apb_master_pwdata_o23, fabric_tnd_fpga_apb_master_pwdata_o24, fabric_tnd_fpga_apb_master_pwdata_o25, fabric_tnd_fpga_apb_master_pwdata_o26, fabric_tnd_fpga_apb_master_pwdata_o27, fabric_tnd_fpga_apb_master_pwdata_o28
+, fabric_tnd_fpga_apb_master_pwdata_o29, fabric_tnd_fpga_apb_master_pwdata_o30, fabric_tnd_fpga_apb_master_pwdata_o31, fabric_tnd_fpga_apb_master_pwdata_o32, fabric_tnd_fpga_apb_master_pwrite_o, fabric_tnd_fpga_atb_master_afvalid_o, fabric_tnd_fpga_atb_master_atready_o, fabric_tnd_fpga_atb_master_syncreq_o, fabric_tnd_hssl_apb_master_paddr_o1, fabric_tnd_hssl_apb_master_paddr_o2, fabric_tnd_hssl_apb_master_paddr_o3, fabric_tnd_hssl_apb_master_paddr_o4, fabric_tnd_hssl_apb_master_paddr_o5, fabric_tnd_hssl_apb_master_paddr_o6, fabric_tnd_hssl_apb_master_paddr_o7, fabric_tnd_hssl_apb_master_paddr_o8, fabric_tnd_hssl_apb_master_paddr_o9, fabric_tnd_hssl_apb_master_paddr_o10, fabric_tnd_hssl_apb_master_paddr_o11, fabric_tnd_hssl_apb_master_paddr_o12, fabric_tnd_hssl_apb_master_paddr_o13
+, fabric_tnd_hssl_apb_master_paddr_o14, fabric_tnd_hssl_apb_master_paddr_o15, fabric_tnd_hssl_apb_master_paddr_o16, fabric_tnd_hssl_apb_master_paddr_o17, fabric_tnd_hssl_apb_master_paddr_o18, fabric_tnd_hssl_apb_master_paddr_o19, fabric_tnd_hssl_apb_master_paddr_o20, fabric_tnd_hssl_apb_master_paddr_o21, fabric_tnd_hssl_apb_master_paddr_o22, fabric_tnd_hssl_apb_master_paddr_o23, fabric_tnd_hssl_apb_master_paddr_o24, fabric_tnd_hssl_apb_master_paddr_o25, fabric_tnd_hssl_apb_master_paddr_o26, fabric_tnd_hssl_apb_master_paddr_o27, fabric_tnd_hssl_apb_master_paddr_o28, fabric_tnd_hssl_apb_master_paddr_o29, fabric_tnd_hssl_apb_master_paddr_o30, fabric_tnd_hssl_apb_master_paddr_o31, fabric_tnd_hssl_apb_master_paddr_o32, fabric_tnd_hssl_apb_master_penable_o, fabric_tnd_hssl_apb_master_psel_o
+, fabric_tnd_hssl_apb_master_pwdata_o1, fabric_tnd_hssl_apb_master_pwdata_o2, fabric_tnd_hssl_apb_master_pwdata_o3, fabric_tnd_hssl_apb_master_pwdata_o4, fabric_tnd_hssl_apb_master_pwdata_o5, fabric_tnd_hssl_apb_master_pwdata_o6, fabric_tnd_hssl_apb_master_pwdata_o7, fabric_tnd_hssl_apb_master_pwdata_o8, fabric_tnd_hssl_apb_master_pwdata_o9, fabric_tnd_hssl_apb_master_pwdata_o10, fabric_tnd_hssl_apb_master_pwdata_o11, fabric_tnd_hssl_apb_master_pwdata_o12, fabric_tnd_hssl_apb_master_pwdata_o13, fabric_tnd_hssl_apb_master_pwdata_o14, fabric_tnd_hssl_apb_master_pwdata_o15, fabric_tnd_hssl_apb_master_pwdata_o16, fabric_tnd_hssl_apb_master_pwdata_o17, fabric_tnd_hssl_apb_master_pwdata_o18, fabric_tnd_hssl_apb_master_pwdata_o19, fabric_tnd_hssl_apb_master_pwdata_o20, fabric_tnd_hssl_apb_master_pwdata_o21
+, fabric_tnd_hssl_apb_master_pwdata_o22, fabric_tnd_hssl_apb_master_pwdata_o23, fabric_tnd_hssl_apb_master_pwdata_o24, fabric_tnd_hssl_apb_master_pwdata_o25, fabric_tnd_hssl_apb_master_pwdata_o26, fabric_tnd_hssl_apb_master_pwdata_o27, fabric_tnd_hssl_apb_master_pwdata_o28, fabric_tnd_hssl_apb_master_pwdata_o29, fabric_tnd_hssl_apb_master_pwdata_o30, fabric_tnd_hssl_apb_master_pwdata_o31, fabric_tnd_hssl_apb_master_pwdata_o32, fabric_tnd_hssl_apb_master_pwrite_o, fabric_tnd_hssl_atb_master_afready_o, fabric_tnd_hssl_atb_master_atbytes_o1, fabric_tnd_hssl_atb_master_atbytes_o2, fabric_tnd_hssl_atb_master_atbytes_o3, fabric_tnd_hssl_atb_master_atbytes_o4, fabric_tnd_hssl_atb_master_atdata_o1, fabric_tnd_hssl_atb_master_atdata_o2, fabric_tnd_hssl_atb_master_atdata_o3, fabric_tnd_hssl_atb_master_atdata_o4
+, fabric_tnd_hssl_atb_master_atdata_o5, fabric_tnd_hssl_atb_master_atdata_o6, fabric_tnd_hssl_atb_master_atdata_o7, fabric_tnd_hssl_atb_master_atdata_o8, fabric_tnd_hssl_atb_master_atdata_o9, fabric_tnd_hssl_atb_master_atdata_o10, fabric_tnd_hssl_atb_master_atdata_o11, fabric_tnd_hssl_atb_master_atdata_o12, fabric_tnd_hssl_atb_master_atdata_o13, fabric_tnd_hssl_atb_master_atdata_o14, fabric_tnd_hssl_atb_master_atdata_o15, fabric_tnd_hssl_atb_master_atdata_o16, fabric_tnd_hssl_atb_master_atdata_o17, fabric_tnd_hssl_atb_master_atdata_o18, fabric_tnd_hssl_atb_master_atdata_o19, fabric_tnd_hssl_atb_master_atdata_o20, fabric_tnd_hssl_atb_master_atdata_o21, fabric_tnd_hssl_atb_master_atdata_o22, fabric_tnd_hssl_atb_master_atdata_o23, fabric_tnd_hssl_atb_master_atdata_o24, fabric_tnd_hssl_atb_master_atdata_o25
+, fabric_tnd_hssl_atb_master_atdata_o26, fabric_tnd_hssl_atb_master_atdata_o27, fabric_tnd_hssl_atb_master_atdata_o28, fabric_tnd_hssl_atb_master_atdata_o29, fabric_tnd_hssl_atb_master_atdata_o30, fabric_tnd_hssl_atb_master_atdata_o31, fabric_tnd_hssl_atb_master_atdata_o32, fabric_tnd_hssl_atb_master_atdata_o33, fabric_tnd_hssl_atb_master_atdata_o34, fabric_tnd_hssl_atb_master_atdata_o35, fabric_tnd_hssl_atb_master_atdata_o36, fabric_tnd_hssl_atb_master_atdata_o37, fabric_tnd_hssl_atb_master_atdata_o38, fabric_tnd_hssl_atb_master_atdata_o39, fabric_tnd_hssl_atb_master_atdata_o40, fabric_tnd_hssl_atb_master_atdata_o41, fabric_tnd_hssl_atb_master_atdata_o42, fabric_tnd_hssl_atb_master_atdata_o43, fabric_tnd_hssl_atb_master_atdata_o44, fabric_tnd_hssl_atb_master_atdata_o45, fabric_tnd_hssl_atb_master_atdata_o46
+, fabric_tnd_hssl_atb_master_atdata_o47, fabric_tnd_hssl_atb_master_atdata_o48, fabric_tnd_hssl_atb_master_atdata_o49, fabric_tnd_hssl_atb_master_atdata_o50, fabric_tnd_hssl_atb_master_atdata_o51, fabric_tnd_hssl_atb_master_atdata_o52, fabric_tnd_hssl_atb_master_atdata_o53, fabric_tnd_hssl_atb_master_atdata_o54, fabric_tnd_hssl_atb_master_atdata_o55, fabric_tnd_hssl_atb_master_atdata_o56, fabric_tnd_hssl_atb_master_atdata_o57, fabric_tnd_hssl_atb_master_atdata_o58, fabric_tnd_hssl_atb_master_atdata_o59, fabric_tnd_hssl_atb_master_atdata_o60, fabric_tnd_hssl_atb_master_atdata_o61, fabric_tnd_hssl_atb_master_atdata_o62, fabric_tnd_hssl_atb_master_atdata_o63, fabric_tnd_hssl_atb_master_atdata_o64, fabric_tnd_hssl_atb_master_atdata_o65, fabric_tnd_hssl_atb_master_atdata_o66, fabric_tnd_hssl_atb_master_atdata_o67
+, fabric_tnd_hssl_atb_master_atdata_o68, fabric_tnd_hssl_atb_master_atdata_o69, fabric_tnd_hssl_atb_master_atdata_o70, fabric_tnd_hssl_atb_master_atdata_o71, fabric_tnd_hssl_atb_master_atdata_o72, fabric_tnd_hssl_atb_master_atdata_o73, fabric_tnd_hssl_atb_master_atdata_o74, fabric_tnd_hssl_atb_master_atdata_o75, fabric_tnd_hssl_atb_master_atdata_o76, fabric_tnd_hssl_atb_master_atdata_o77, fabric_tnd_hssl_atb_master_atdata_o78, fabric_tnd_hssl_atb_master_atdata_o79, fabric_tnd_hssl_atb_master_atdata_o80, fabric_tnd_hssl_atb_master_atdata_o81, fabric_tnd_hssl_atb_master_atdata_o82, fabric_tnd_hssl_atb_master_atdata_o83, fabric_tnd_hssl_atb_master_atdata_o84, fabric_tnd_hssl_atb_master_atdata_o85, fabric_tnd_hssl_atb_master_atdata_o86, fabric_tnd_hssl_atb_master_atdata_o87, fabric_tnd_hssl_atb_master_atdata_o88
+, fabric_tnd_hssl_atb_master_atdata_o89, fabric_tnd_hssl_atb_master_atdata_o90, fabric_tnd_hssl_atb_master_atdata_o91, fabric_tnd_hssl_atb_master_atdata_o92, fabric_tnd_hssl_atb_master_atdata_o93, fabric_tnd_hssl_atb_master_atdata_o94, fabric_tnd_hssl_atb_master_atdata_o95, fabric_tnd_hssl_atb_master_atdata_o96, fabric_tnd_hssl_atb_master_atdata_o97, fabric_tnd_hssl_atb_master_atdata_o98, fabric_tnd_hssl_atb_master_atdata_o99, fabric_tnd_hssl_atb_master_atdata_o100, fabric_tnd_hssl_atb_master_atdata_o101, fabric_tnd_hssl_atb_master_atdata_o102, fabric_tnd_hssl_atb_master_atdata_o103, fabric_tnd_hssl_atb_master_atdata_o104, fabric_tnd_hssl_atb_master_atdata_o105, fabric_tnd_hssl_atb_master_atdata_o106, fabric_tnd_hssl_atb_master_atdata_o107, fabric_tnd_hssl_atb_master_atdata_o108, fabric_tnd_hssl_atb_master_atdata_o109
+, fabric_tnd_hssl_atb_master_atdata_o110, fabric_tnd_hssl_atb_master_atdata_o111, fabric_tnd_hssl_atb_master_atdata_o112, fabric_tnd_hssl_atb_master_atdata_o113, fabric_tnd_hssl_atb_master_atdata_o114, fabric_tnd_hssl_atb_master_atdata_o115, fabric_tnd_hssl_atb_master_atdata_o116, fabric_tnd_hssl_atb_master_atdata_o117, fabric_tnd_hssl_atb_master_atdata_o118, fabric_tnd_hssl_atb_master_atdata_o119, fabric_tnd_hssl_atb_master_atdata_o120, fabric_tnd_hssl_atb_master_atdata_o121, fabric_tnd_hssl_atb_master_atdata_o122, fabric_tnd_hssl_atb_master_atdata_o123, fabric_tnd_hssl_atb_master_atdata_o124, fabric_tnd_hssl_atb_master_atdata_o125, fabric_tnd_hssl_atb_master_atdata_o126, fabric_tnd_hssl_atb_master_atdata_o127, fabric_tnd_hssl_atb_master_atdata_o128, fabric_tnd_hssl_atb_master_atid_o1, fabric_tnd_hssl_atb_master_atid_o2
+, fabric_tnd_hssl_atb_master_atid_o3, fabric_tnd_hssl_atb_master_atid_o4, fabric_tnd_hssl_atb_master_atid_o5, fabric_tnd_hssl_atb_master_atid_o6, fabric_tnd_hssl_atb_master_atid_o7, fabric_tnd_hssl_atb_master_atvalid_o, fabric_tnd_trace_clk_traceoutportintf_o, fabric_tnd_trace_ctl_traceoutportintf_o, fabric_tnd_trace_data_traceoutportintf_o1, fabric_tnd_trace_data_traceoutportintf_o2, fabric_tnd_trace_data_traceoutportintf_o3, fabric_tnd_trace_data_traceoutportintf_o4, fabric_tnd_trace_data_traceoutportintf_o5, fabric_tnd_trace_data_traceoutportintf_o6, fabric_tnd_trace_data_traceoutportintf_o7, fabric_tnd_trace_data_traceoutportintf_o8, fabric_tnd_trace_data_traceoutportintf_o9, fabric_tnd_trace_data_traceoutportintf_o10, fabric_tnd_trace_data_traceoutportintf_o11, fabric_tnd_trace_data_traceoutportintf_o12, fabric_tnd_trace_data_traceoutportintf_o13
+, fabric_tnd_trace_data_traceoutportintf_o14, fabric_tnd_trace_data_traceoutportintf_o15, fabric_tnd_trace_data_traceoutportintf_o16, fabric_tnd_trace_data_traceoutportintf_o17, fabric_tnd_trace_data_traceoutportintf_o18, fabric_tnd_trace_data_traceoutportintf_o19, fabric_tnd_trace_data_traceoutportintf_o20, fabric_tnd_trace_data_traceoutportintf_o21, fabric_tnd_trace_data_traceoutportintf_o22, fabric_tnd_trace_data_traceoutportintf_o23, fabric_tnd_trace_data_traceoutportintf_o24, fabric_tnd_trace_data_traceoutportintf_o25, fabric_tnd_trace_data_traceoutportintf_o26, fabric_tnd_trace_data_traceoutportintf_o27, fabric_tnd_trace_data_traceoutportintf_o28, fabric_tnd_trace_data_traceoutportintf_o29, fabric_tnd_trace_data_traceoutportintf_o30, fabric_tnd_trace_data_traceoutportintf_o31, fabric_tnd_trace_data_traceoutportintf_o32, fabric_tsvalue_tsgen_fpga_o1, fabric_tsvalue_tsgen_fpga_o2
+, fabric_tsvalue_tsgen_fpga_o3, fabric_tsvalue_tsgen_fpga_o4, fabric_tsvalue_tsgen_fpga_o5, fabric_tsvalue_tsgen_fpga_o6, fabric_tsvalue_tsgen_fpga_o7, fabric_tsvalue_tsgen_fpga_o8, fabric_tsvalue_tsgen_fpga_o9, fabric_tsvalue_tsgen_fpga_o10, fabric_tsvalue_tsgen_fpga_o11, fabric_tsvalue_tsgen_fpga_o12, fabric_tsvalue_tsgen_fpga_o13, fabric_tsvalue_tsgen_fpga_o14, fabric_tsvalue_tsgen_fpga_o15, fabric_tsvalue_tsgen_fpga_o16, fabric_tsvalue_tsgen_fpga_o17, fabric_tsvalue_tsgen_fpga_o18, fabric_tsvalue_tsgen_fpga_o19, fabric_tsvalue_tsgen_fpga_o20, fabric_tsvalue_tsgen_fpga_o21, fabric_tsvalue_tsgen_fpga_o22, fabric_tsvalue_tsgen_fpga_o23
+, fabric_tsvalue_tsgen_fpga_o24, fabric_tsvalue_tsgen_fpga_o25, fabric_tsvalue_tsgen_fpga_o26, fabric_tsvalue_tsgen_fpga_o27, fabric_tsvalue_tsgen_fpga_o28, fabric_tsvalue_tsgen_fpga_o29, fabric_tsvalue_tsgen_fpga_o30, fabric_tsvalue_tsgen_fpga_o31, fabric_tsvalue_tsgen_fpga_o32, fabric_tsvalue_tsgen_fpga_o33, fabric_tsvalue_tsgen_fpga_o34, fabric_tsvalue_tsgen_fpga_o35, fabric_tsvalue_tsgen_fpga_o36, fabric_tsvalue_tsgen_fpga_o37, fabric_tsvalue_tsgen_fpga_o38, fabric_tsvalue_tsgen_fpga_o39, fabric_tsvalue_tsgen_fpga_o40, fabric_tsvalue_tsgen_fpga_o41, fabric_tsvalue_tsgen_fpga_o42, fabric_tsvalue_tsgen_fpga_o43, fabric_tsvalue_tsgen_fpga_o44
+, fabric_tsvalue_tsgen_fpga_o45, fabric_tsvalue_tsgen_fpga_o46, fabric_tsvalue_tsgen_fpga_o47, fabric_tsvalue_tsgen_fpga_o48, fabric_tsvalue_tsgen_fpga_o49, fabric_tsvalue_tsgen_fpga_o50, fabric_tsvalue_tsgen_fpga_o51, fabric_tsvalue_tsgen_fpga_o52, fabric_tsvalue_tsgen_fpga_o53, fabric_tsvalue_tsgen_fpga_o54, fabric_tsvalue_tsgen_fpga_o55, fabric_tsvalue_tsgen_fpga_o56, fabric_tsvalue_tsgen_fpga_o57, fabric_tsvalue_tsgen_fpga_o58, fabric_tsvalue_tsgen_fpga_o59, fabric_tsvalue_tsgen_fpga_o60, fabric_tsvalue_tsgen_fpga_o61, fabric_tsvalue_tsgen_fpga_o62, fabric_tsvalue_tsgen_fpga_o63, fabric_tsvalue_tsgen_fpga_o64, fabric_tnd_fpga_apb_master_prdata_i1
+, fabric_tnd_fpga_apb_master_prdata_i2, fabric_tnd_fpga_apb_master_prdata_i3, fabric_tnd_fpga_apb_master_prdata_i4, fabric_tnd_fpga_apb_master_prdata_i5, fabric_tnd_fpga_apb_master_prdata_i6, fabric_tnd_fpga_apb_master_prdata_i7, fabric_tnd_fpga_apb_master_prdata_i8, fabric_tnd_fpga_apb_master_prdata_i9, fabric_tnd_fpga_apb_master_prdata_i10, fabric_tnd_fpga_apb_master_prdata_i11, fabric_tnd_fpga_apb_master_prdata_i12, fabric_tnd_fpga_apb_master_prdata_i13, fabric_tnd_fpga_apb_master_prdata_i14, fabric_tnd_fpga_apb_master_prdata_i15, fabric_tnd_fpga_apb_master_prdata_i16, fabric_tnd_fpga_apb_master_prdata_i17, fabric_tnd_fpga_apb_master_prdata_i18, fabric_tnd_fpga_apb_master_prdata_i19, fabric_tnd_fpga_apb_master_prdata_i20, fabric_tnd_fpga_apb_master_prdata_i21, fabric_tnd_fpga_apb_master_prdata_i22
+, fabric_tnd_fpga_apb_master_prdata_i23, fabric_tnd_fpga_apb_master_prdata_i24, fabric_tnd_fpga_apb_master_prdata_i25, fabric_tnd_fpga_apb_master_prdata_i26, fabric_tnd_fpga_apb_master_prdata_i27, fabric_tnd_fpga_apb_master_prdata_i28, fabric_tnd_fpga_apb_master_prdata_i29, fabric_tnd_fpga_apb_master_prdata_i30, fabric_tnd_fpga_apb_master_prdata_i31, fabric_tnd_fpga_apb_master_prdata_i32, fabric_tnd_fpga_apb_master_pready_i, fabric_tnd_fpga_apb_master_pslverr_i, fabric_tnd_fpga_atb_master_afready_i, fabric_tnd_fpga_atb_master_atbytes_i1, fabric_tnd_fpga_atb_master_atbytes_i2, fabric_tnd_fpga_atb_master_atbytes_i3, fabric_tnd_fpga_atb_master_atbytes_i4, fabric_tnd_fpga_atb_master_atdata_i1, fabric_tnd_fpga_atb_master_atdata_i2, fabric_tnd_fpga_atb_master_atdata_i3, fabric_tnd_fpga_atb_master_atdata_i4
+, fabric_tnd_fpga_atb_master_atdata_i5, fabric_tnd_fpga_atb_master_atdata_i6, fabric_tnd_fpga_atb_master_atdata_i7, fabric_tnd_fpga_atb_master_atdata_i8, fabric_tnd_fpga_atb_master_atdata_i9, fabric_tnd_fpga_atb_master_atdata_i10, fabric_tnd_fpga_atb_master_atdata_i11, fabric_tnd_fpga_atb_master_atdata_i12, fabric_tnd_fpga_atb_master_atdata_i13, fabric_tnd_fpga_atb_master_atdata_i14, fabric_tnd_fpga_atb_master_atdata_i15, fabric_tnd_fpga_atb_master_atdata_i16, fabric_tnd_fpga_atb_master_atdata_i17, fabric_tnd_fpga_atb_master_atdata_i18, fabric_tnd_fpga_atb_master_atdata_i19, fabric_tnd_fpga_atb_master_atdata_i20, fabric_tnd_fpga_atb_master_atdata_i21, fabric_tnd_fpga_atb_master_atdata_i22, fabric_tnd_fpga_atb_master_atdata_i23, fabric_tnd_fpga_atb_master_atdata_i24, fabric_tnd_fpga_atb_master_atdata_i25
+, fabric_tnd_fpga_atb_master_atdata_i26, fabric_tnd_fpga_atb_master_atdata_i27, fabric_tnd_fpga_atb_master_atdata_i28, fabric_tnd_fpga_atb_master_atdata_i29, fabric_tnd_fpga_atb_master_atdata_i30, fabric_tnd_fpga_atb_master_atdata_i31, fabric_tnd_fpga_atb_master_atdata_i32, fabric_tnd_fpga_atb_master_atdata_i33, fabric_tnd_fpga_atb_master_atdata_i34, fabric_tnd_fpga_atb_master_atdata_i35, fabric_tnd_fpga_atb_master_atdata_i36, fabric_tnd_fpga_atb_master_atdata_i37, fabric_tnd_fpga_atb_master_atdata_i38, fabric_tnd_fpga_atb_master_atdata_i39, fabric_tnd_fpga_atb_master_atdata_i40, fabric_tnd_fpga_atb_master_atdata_i41, fabric_tnd_fpga_atb_master_atdata_i42, fabric_tnd_fpga_atb_master_atdata_i43, fabric_tnd_fpga_atb_master_atdata_i44, fabric_tnd_fpga_atb_master_atdata_i45, fabric_tnd_fpga_atb_master_atdata_i46
+, fabric_tnd_fpga_atb_master_atdata_i47, fabric_tnd_fpga_atb_master_atdata_i48, fabric_tnd_fpga_atb_master_atdata_i49, fabric_tnd_fpga_atb_master_atdata_i50, fabric_tnd_fpga_atb_master_atdata_i51, fabric_tnd_fpga_atb_master_atdata_i52, fabric_tnd_fpga_atb_master_atdata_i53, fabric_tnd_fpga_atb_master_atdata_i54, fabric_tnd_fpga_atb_master_atdata_i55, fabric_tnd_fpga_atb_master_atdata_i56, fabric_tnd_fpga_atb_master_atdata_i57, fabric_tnd_fpga_atb_master_atdata_i58, fabric_tnd_fpga_atb_master_atdata_i59, fabric_tnd_fpga_atb_master_atdata_i60, fabric_tnd_fpga_atb_master_atdata_i61, fabric_tnd_fpga_atb_master_atdata_i62, fabric_tnd_fpga_atb_master_atdata_i63, fabric_tnd_fpga_atb_master_atdata_i64, fabric_tnd_fpga_atb_master_atdata_i65, fabric_tnd_fpga_atb_master_atdata_i66, fabric_tnd_fpga_atb_master_atdata_i67
+, fabric_tnd_fpga_atb_master_atdata_i68, fabric_tnd_fpga_atb_master_atdata_i69, fabric_tnd_fpga_atb_master_atdata_i70, fabric_tnd_fpga_atb_master_atdata_i71, fabric_tnd_fpga_atb_master_atdata_i72, fabric_tnd_fpga_atb_master_atdata_i73, fabric_tnd_fpga_atb_master_atdata_i74, fabric_tnd_fpga_atb_master_atdata_i75, fabric_tnd_fpga_atb_master_atdata_i76, fabric_tnd_fpga_atb_master_atdata_i77, fabric_tnd_fpga_atb_master_atdata_i78, fabric_tnd_fpga_atb_master_atdata_i79, fabric_tnd_fpga_atb_master_atdata_i80, fabric_tnd_fpga_atb_master_atdata_i81, fabric_tnd_fpga_atb_master_atdata_i82, fabric_tnd_fpga_atb_master_atdata_i83, fabric_tnd_fpga_atb_master_atdata_i84, fabric_tnd_fpga_atb_master_atdata_i85, fabric_tnd_fpga_atb_master_atdata_i86, fabric_tnd_fpga_atb_master_atdata_i87, fabric_tnd_fpga_atb_master_atdata_i88
+, fabric_tnd_fpga_atb_master_atdata_i89, fabric_tnd_fpga_atb_master_atdata_i90, fabric_tnd_fpga_atb_master_atdata_i91, fabric_tnd_fpga_atb_master_atdata_i92, fabric_tnd_fpga_atb_master_atdata_i93, fabric_tnd_fpga_atb_master_atdata_i94, fabric_tnd_fpga_atb_master_atdata_i95, fabric_tnd_fpga_atb_master_atdata_i96, fabric_tnd_fpga_atb_master_atdata_i97, fabric_tnd_fpga_atb_master_atdata_i98, fabric_tnd_fpga_atb_master_atdata_i99, fabric_tnd_fpga_atb_master_atdata_i100, fabric_tnd_fpga_atb_master_atdata_i101, fabric_tnd_fpga_atb_master_atdata_i102, fabric_tnd_fpga_atb_master_atdata_i103, fabric_tnd_fpga_atb_master_atdata_i104, fabric_tnd_fpga_atb_master_atdata_i105, fabric_tnd_fpga_atb_master_atdata_i106, fabric_tnd_fpga_atb_master_atdata_i107, fabric_tnd_fpga_atb_master_atdata_i108, fabric_tnd_fpga_atb_master_atdata_i109
+, fabric_tnd_fpga_atb_master_atdata_i110, fabric_tnd_fpga_atb_master_atdata_i111, fabric_tnd_fpga_atb_master_atdata_i112, fabric_tnd_fpga_atb_master_atdata_i113, fabric_tnd_fpga_atb_master_atdata_i114, fabric_tnd_fpga_atb_master_atdata_i115, fabric_tnd_fpga_atb_master_atdata_i116, fabric_tnd_fpga_atb_master_atdata_i117, fabric_tnd_fpga_atb_master_atdata_i118, fabric_tnd_fpga_atb_master_atdata_i119, fabric_tnd_fpga_atb_master_atdata_i120, fabric_tnd_fpga_atb_master_atdata_i121, fabric_tnd_fpga_atb_master_atdata_i122, fabric_tnd_fpga_atb_master_atdata_i123, fabric_tnd_fpga_atb_master_atdata_i124, fabric_tnd_fpga_atb_master_atdata_i125, fabric_tnd_fpga_atb_master_atdata_i126, fabric_tnd_fpga_atb_master_atdata_i127, fabric_tnd_fpga_atb_master_atdata_i128, fabric_tnd_fpga_atb_master_atid_i1, fabric_tnd_fpga_atb_master_atid_i2
+, fabric_tnd_fpga_atb_master_atid_i3, fabric_tnd_fpga_atb_master_atid_i4, fabric_tnd_fpga_atb_master_atid_i5, fabric_tnd_fpga_atb_master_atid_i6, fabric_tnd_fpga_atb_master_atid_i7, fabric_tnd_fpga_atb_master_atvalid_i, fabric_tnd_hssl_apb_master_prdata_i1, fabric_tnd_hssl_apb_master_prdata_i2, fabric_tnd_hssl_apb_master_prdata_i3, fabric_tnd_hssl_apb_master_prdata_i4, fabric_tnd_hssl_apb_master_prdata_i5, fabric_tnd_hssl_apb_master_prdata_i6, fabric_tnd_hssl_apb_master_prdata_i7, fabric_tnd_hssl_apb_master_prdata_i8, fabric_tnd_hssl_apb_master_prdata_i9, fabric_tnd_hssl_apb_master_prdata_i10, fabric_tnd_hssl_apb_master_prdata_i11, fabric_tnd_hssl_apb_master_prdata_i12, fabric_tnd_hssl_apb_master_prdata_i13, fabric_tnd_hssl_apb_master_prdata_i14, fabric_tnd_hssl_apb_master_prdata_i15
+, fabric_tnd_hssl_apb_master_prdata_i16, fabric_tnd_hssl_apb_master_prdata_i17, fabric_tnd_hssl_apb_master_prdata_i18, fabric_tnd_hssl_apb_master_prdata_i19, fabric_tnd_hssl_apb_master_prdata_i20, fabric_tnd_hssl_apb_master_prdata_i21, fabric_tnd_hssl_apb_master_prdata_i22, fabric_tnd_hssl_apb_master_prdata_i23, fabric_tnd_hssl_apb_master_prdata_i24, fabric_tnd_hssl_apb_master_prdata_i25, fabric_tnd_hssl_apb_master_prdata_i26, fabric_tnd_hssl_apb_master_prdata_i27, fabric_tnd_hssl_apb_master_prdata_i28, fabric_tnd_hssl_apb_master_prdata_i29, fabric_tnd_hssl_apb_master_prdata_i30, fabric_tnd_hssl_apb_master_prdata_i31, fabric_tnd_hssl_apb_master_prdata_i32, fabric_tnd_hssl_apb_master_pready_i, fabric_tnd_hssl_apb_master_pslverr_i, fabric_tnd_hssl_atb_master_afvalid_i, fabric_tnd_hssl_atb_master_atready_i
+, fabric_tnd_hssl_atb_master_syncreq_i, fabric_watchdog0_signal_0_o, fabric_watchdog0_signal_1_o, fabric_watchdog1_signal_0_o, fabric_watchdog1_signal_1_o, fabric_watchdog2_signal_0_o, fabric_watchdog2_signal_1_o, fabric_watchdog3_signal_0_o, fabric_watchdog3_signal_1_o, fabric_tst_pll_lock_o1, fabric_tst_pll_lock_o2, fabric_tst_pll_lock_o3, fabric_tst_pll_lock_o4, fabric_tst_pll_lock_o5, fabric_tst_pll_lock_o6, fabric_tst_pll_lock_o7, fabric_soc_mon_sensor_alarm_o, fabric_erom_fpga_cpu0_dbgen_i, fabric_erom_fpga_cpu0_hiden_i, fabric_erom_fpga_cpu0_hniden_i, fabric_erom_fpga_cpu0_niden_i
+, fabric_erom_fpga_cpu1_dbgen_i, fabric_erom_fpga_cpu1_hiden_i, fabric_erom_fpga_cpu1_hniden_i, fabric_erom_fpga_cpu1_niden_i, fabric_erom_fpga_cpu2_dbgen_i, fabric_erom_fpga_cpu2_hiden_i, fabric_erom_fpga_cpu2_hniden_i, fabric_erom_fpga_cpu2_niden_i, fabric_erom_fpga_cpu3_dbgen_i, fabric_erom_fpga_cpu3_hiden_i, fabric_erom_fpga_cpu3_hniden_i, fabric_erom_fpga_cpu3_niden_i, fabric_erom_fpga_cs_dbgen_i, fabric_erom_fpga_cs_niden_i, fabric_erom_fpga_cs_deviceen_i, fabric_erom_fpga_cs_rst_n_i, fabric_erom_fpga_debug_en_i, fabric_enable_TMR_i1, fabric_enable_TMR_i2, fabric_enable_TMR_i3, fabric_spw_interrupts_toggle_o1
+, fabric_spw_interrupts_toggle_o2, fabric_spw_interrupts_toggle_o3, fabric_spw_interrupts_o1, fabric_spw_interrupts_o2, fabric_spw_interrupts_o3, fabric_flash_irq_toggle_o, fabric_flash_irq_o, fabric_fpga_dma_hs_rstn_i1, fabric_fpga_dma_hs_rstn_i2, fabric_fpga_dma_hs_rstn_i3, fabric_fpga_dma_hs_rstn_i4, fabric_fpga_dma_hs_rstn_i5, fabric_fpga_dma_hs_rstn_i6);
+    input fabric_enable_TMR_i1;
+    input fabric_enable_TMR_i2;
+    input fabric_enable_TMR_i3;
+    input fabric_erom_fpga_cpu0_dbgen_i;
+    input fabric_erom_fpga_cpu0_hiden_i;
+    input fabric_erom_fpga_cpu0_hniden_i;
+    input fabric_erom_fpga_cpu0_niden_i;
+    input fabric_erom_fpga_cpu1_dbgen_i;
+    input fabric_erom_fpga_cpu1_hiden_i;
+    input fabric_erom_fpga_cpu1_hniden_i;
+    input fabric_erom_fpga_cpu1_niden_i;
+    input fabric_erom_fpga_cpu2_dbgen_i;
+    input fabric_erom_fpga_cpu2_hiden_i;
+    input fabric_erom_fpga_cpu2_hniden_i;
+    input fabric_erom_fpga_cpu2_niden_i;
+    input fabric_erom_fpga_cpu3_dbgen_i;
+    input fabric_erom_fpga_cpu3_hiden_i;
+    input fabric_erom_fpga_cpu3_hniden_i;
+    input fabric_erom_fpga_cpu3_niden_i;
+    input fabric_erom_fpga_cs_dbgen_i;
+    input fabric_erom_fpga_cs_deviceen_i;
+    input fabric_erom_fpga_cs_niden_i;
+    input fabric_erom_fpga_cs_rst_n_i;
+    input fabric_erom_fpga_debug_en_i;
+    output fabric_flash_irq_o;
+    output fabric_flash_irq_toggle_o;
+    input fabric_fpga_araddr_axi_m1_i1;
+    input fabric_fpga_araddr_axi_m1_i10;
+    input fabric_fpga_araddr_axi_m1_i11;
+    input fabric_fpga_araddr_axi_m1_i12;
+    input fabric_fpga_araddr_axi_m1_i13;
+    input fabric_fpga_araddr_axi_m1_i14;
+    input fabric_fpga_araddr_axi_m1_i15;
+    input fabric_fpga_araddr_axi_m1_i16;
+    input fabric_fpga_araddr_axi_m1_i17;
+    input fabric_fpga_araddr_axi_m1_i18;
+    input fabric_fpga_araddr_axi_m1_i19;
+    input fabric_fpga_araddr_axi_m1_i2;
+    input fabric_fpga_araddr_axi_m1_i20;
+    input fabric_fpga_araddr_axi_m1_i21;
+    input fabric_fpga_araddr_axi_m1_i22;
+    input fabric_fpga_araddr_axi_m1_i23;
+    input fabric_fpga_araddr_axi_m1_i24;
+    input fabric_fpga_araddr_axi_m1_i25;
+    input fabric_fpga_araddr_axi_m1_i26;
+    input fabric_fpga_araddr_axi_m1_i27;
+    input fabric_fpga_araddr_axi_m1_i28;
+    input fabric_fpga_araddr_axi_m1_i29;
+    input fabric_fpga_araddr_axi_m1_i3;
+    input fabric_fpga_araddr_axi_m1_i30;
+    input fabric_fpga_araddr_axi_m1_i31;
+    input fabric_fpga_araddr_axi_m1_i32;
+    input fabric_fpga_araddr_axi_m1_i33;
+    input fabric_fpga_araddr_axi_m1_i34;
+    input fabric_fpga_araddr_axi_m1_i35;
+    input fabric_fpga_araddr_axi_m1_i36;
+    input fabric_fpga_araddr_axi_m1_i37;
+    input fabric_fpga_araddr_axi_m1_i38;
+    input fabric_fpga_araddr_axi_m1_i39;
+    input fabric_fpga_araddr_axi_m1_i4;
+    input fabric_fpga_araddr_axi_m1_i40;
+    input fabric_fpga_araddr_axi_m1_i5;
+    input fabric_fpga_araddr_axi_m1_i6;
+    input fabric_fpga_araddr_axi_m1_i7;
+    input fabric_fpga_araddr_axi_m1_i8;
+    input fabric_fpga_araddr_axi_m1_i9;
+    input fabric_fpga_araddr_axi_m2_i1;
+    input fabric_fpga_araddr_axi_m2_i10;
+    input fabric_fpga_araddr_axi_m2_i11;
+    input fabric_fpga_araddr_axi_m2_i12;
+    input fabric_fpga_araddr_axi_m2_i13;
+    input fabric_fpga_araddr_axi_m2_i14;
+    input fabric_fpga_araddr_axi_m2_i15;
+    input fabric_fpga_araddr_axi_m2_i16;
+    input fabric_fpga_araddr_axi_m2_i17;
+    input fabric_fpga_araddr_axi_m2_i18;
+    input fabric_fpga_araddr_axi_m2_i19;
+    input fabric_fpga_araddr_axi_m2_i2;
+    input fabric_fpga_araddr_axi_m2_i20;
+    input fabric_fpga_araddr_axi_m2_i21;
+    input fabric_fpga_araddr_axi_m2_i22;
+    input fabric_fpga_araddr_axi_m2_i23;
+    input fabric_fpga_araddr_axi_m2_i24;
+    input fabric_fpga_araddr_axi_m2_i25;
+    input fabric_fpga_araddr_axi_m2_i26;
+    input fabric_fpga_araddr_axi_m2_i27;
+    input fabric_fpga_araddr_axi_m2_i28;
+    input fabric_fpga_araddr_axi_m2_i29;
+    input fabric_fpga_araddr_axi_m2_i3;
+    input fabric_fpga_araddr_axi_m2_i30;
+    input fabric_fpga_araddr_axi_m2_i31;
+    input fabric_fpga_araddr_axi_m2_i32;
+    input fabric_fpga_araddr_axi_m2_i33;
+    input fabric_fpga_araddr_axi_m2_i34;
+    input fabric_fpga_araddr_axi_m2_i35;
+    input fabric_fpga_araddr_axi_m2_i36;
+    input fabric_fpga_araddr_axi_m2_i37;
+    input fabric_fpga_araddr_axi_m2_i38;
+    input fabric_fpga_araddr_axi_m2_i39;
+    input fabric_fpga_araddr_axi_m2_i4;
+    input fabric_fpga_araddr_axi_m2_i40;
+    input fabric_fpga_araddr_axi_m2_i5;
+    input fabric_fpga_araddr_axi_m2_i6;
+    input fabric_fpga_araddr_axi_m2_i7;
+    input fabric_fpga_araddr_axi_m2_i8;
+    input fabric_fpga_araddr_axi_m2_i9;
+    output fabric_fpga_araddr_axi_s1_o1;
+    output fabric_fpga_araddr_axi_s1_o10;
+    output fabric_fpga_araddr_axi_s1_o11;
+    output fabric_fpga_araddr_axi_s1_o12;
+    output fabric_fpga_araddr_axi_s1_o13;
+    output fabric_fpga_araddr_axi_s1_o14;
+    output fabric_fpga_araddr_axi_s1_o15;
+    output fabric_fpga_araddr_axi_s1_o16;
+    output fabric_fpga_araddr_axi_s1_o17;
+    output fabric_fpga_araddr_axi_s1_o18;
+    output fabric_fpga_araddr_axi_s1_o19;
+    output fabric_fpga_araddr_axi_s1_o2;
+    output fabric_fpga_araddr_axi_s1_o20;
+    output fabric_fpga_araddr_axi_s1_o21;
+    output fabric_fpga_araddr_axi_s1_o22;
+    output fabric_fpga_araddr_axi_s1_o23;
+    output fabric_fpga_araddr_axi_s1_o24;
+    output fabric_fpga_araddr_axi_s1_o25;
+    output fabric_fpga_araddr_axi_s1_o26;
+    output fabric_fpga_araddr_axi_s1_o27;
+    output fabric_fpga_araddr_axi_s1_o28;
+    output fabric_fpga_araddr_axi_s1_o29;
+    output fabric_fpga_araddr_axi_s1_o3;
+    output fabric_fpga_araddr_axi_s1_o30;
+    output fabric_fpga_araddr_axi_s1_o31;
+    output fabric_fpga_araddr_axi_s1_o32;
+    output fabric_fpga_araddr_axi_s1_o33;
+    output fabric_fpga_araddr_axi_s1_o34;
+    output fabric_fpga_araddr_axi_s1_o35;
+    output fabric_fpga_araddr_axi_s1_o36;
+    output fabric_fpga_araddr_axi_s1_o37;
+    output fabric_fpga_araddr_axi_s1_o38;
+    output fabric_fpga_araddr_axi_s1_o39;
+    output fabric_fpga_araddr_axi_s1_o4;
+    output fabric_fpga_araddr_axi_s1_o40;
+    output fabric_fpga_araddr_axi_s1_o5;
+    output fabric_fpga_araddr_axi_s1_o6;
+    output fabric_fpga_araddr_axi_s1_o7;
+    output fabric_fpga_araddr_axi_s1_o8;
+    output fabric_fpga_araddr_axi_s1_o9;
+    output fabric_fpga_araddr_axi_s2_o1;
+    output fabric_fpga_araddr_axi_s2_o10;
+    output fabric_fpga_araddr_axi_s2_o11;
+    output fabric_fpga_araddr_axi_s2_o12;
+    output fabric_fpga_araddr_axi_s2_o13;
+    output fabric_fpga_araddr_axi_s2_o14;
+    output fabric_fpga_araddr_axi_s2_o15;
+    output fabric_fpga_araddr_axi_s2_o16;
+    output fabric_fpga_araddr_axi_s2_o17;
+    output fabric_fpga_araddr_axi_s2_o18;
+    output fabric_fpga_araddr_axi_s2_o19;
+    output fabric_fpga_araddr_axi_s2_o2;
+    output fabric_fpga_araddr_axi_s2_o20;
+    output fabric_fpga_araddr_axi_s2_o21;
+    output fabric_fpga_araddr_axi_s2_o22;
+    output fabric_fpga_araddr_axi_s2_o23;
+    output fabric_fpga_araddr_axi_s2_o24;
+    output fabric_fpga_araddr_axi_s2_o25;
+    output fabric_fpga_araddr_axi_s2_o26;
+    output fabric_fpga_araddr_axi_s2_o27;
+    output fabric_fpga_araddr_axi_s2_o28;
+    output fabric_fpga_araddr_axi_s2_o29;
+    output fabric_fpga_araddr_axi_s2_o3;
+    output fabric_fpga_araddr_axi_s2_o30;
+    output fabric_fpga_araddr_axi_s2_o31;
+    output fabric_fpga_araddr_axi_s2_o32;
+    output fabric_fpga_araddr_axi_s2_o33;
+    output fabric_fpga_araddr_axi_s2_o34;
+    output fabric_fpga_araddr_axi_s2_o35;
+    output fabric_fpga_araddr_axi_s2_o36;
+    output fabric_fpga_araddr_axi_s2_o37;
+    output fabric_fpga_araddr_axi_s2_o38;
+    output fabric_fpga_araddr_axi_s2_o39;
+    output fabric_fpga_araddr_axi_s2_o4;
+    output fabric_fpga_araddr_axi_s2_o40;
+    output fabric_fpga_araddr_axi_s2_o5;
+    output fabric_fpga_araddr_axi_s2_o6;
+    output fabric_fpga_araddr_axi_s2_o7;
+    output fabric_fpga_araddr_axi_s2_o8;
+    output fabric_fpga_araddr_axi_s2_o9;
+    input fabric_fpga_arburst_axi_m1_i1;
+    input fabric_fpga_arburst_axi_m1_i2;
+    input fabric_fpga_arburst_axi_m2_i1;
+    input fabric_fpga_arburst_axi_m2_i2;
+    output fabric_fpga_arburst_axi_s1_o1;
+    output fabric_fpga_arburst_axi_s1_o2;
+    output fabric_fpga_arburst_axi_s2_o1;
+    output fabric_fpga_arburst_axi_s2_o2;
+    input fabric_fpga_arcache_axi_m1_i1;
+    input fabric_fpga_arcache_axi_m1_i2;
+    input fabric_fpga_arcache_axi_m1_i3;
+    input fabric_fpga_arcache_axi_m1_i4;
+    input fabric_fpga_arcache_axi_m2_i1;
+    input fabric_fpga_arcache_axi_m2_i2;
+    input fabric_fpga_arcache_axi_m2_i3;
+    input fabric_fpga_arcache_axi_m2_i4;
+    output fabric_fpga_arcache_axi_s1_o1;
+    output fabric_fpga_arcache_axi_s1_o2;
+    output fabric_fpga_arcache_axi_s1_o3;
+    output fabric_fpga_arcache_axi_s1_o4;
+    output fabric_fpga_arcache_axi_s2_o1;
+    output fabric_fpga_arcache_axi_s2_o2;
+    output fabric_fpga_arcache_axi_s2_o3;
+    output fabric_fpga_arcache_axi_s2_o4;
+    input fabric_fpga_arid_axi_m1_i1;
+    input fabric_fpga_arid_axi_m1_i2;
+    input fabric_fpga_arid_axi_m1_i3;
+    input fabric_fpga_arid_axi_m1_i4;
+    input fabric_fpga_arid_axi_m1_i5;
+    input fabric_fpga_arid_axi_m2_i1;
+    input fabric_fpga_arid_axi_m2_i2;
+    input fabric_fpga_arid_axi_m2_i3;
+    input fabric_fpga_arid_axi_m2_i4;
+    input fabric_fpga_arid_axi_m2_i5;
+    output fabric_fpga_arid_axi_s1_o1;
+    output fabric_fpga_arid_axi_s1_o10;
+    output fabric_fpga_arid_axi_s1_o11;
+    output fabric_fpga_arid_axi_s1_o12;
+    output fabric_fpga_arid_axi_s1_o2;
+    output fabric_fpga_arid_axi_s1_o3;
+    output fabric_fpga_arid_axi_s1_o4;
+    output fabric_fpga_arid_axi_s1_o5;
+    output fabric_fpga_arid_axi_s1_o6;
+    output fabric_fpga_arid_axi_s1_o7;
+    output fabric_fpga_arid_axi_s1_o8;
+    output fabric_fpga_arid_axi_s1_o9;
+    output fabric_fpga_arid_axi_s2_o1;
+    output fabric_fpga_arid_axi_s2_o10;
+    output fabric_fpga_arid_axi_s2_o11;
+    output fabric_fpga_arid_axi_s2_o12;
+    output fabric_fpga_arid_axi_s2_o2;
+    output fabric_fpga_arid_axi_s2_o3;
+    output fabric_fpga_arid_axi_s2_o4;
+    output fabric_fpga_arid_axi_s2_o5;
+    output fabric_fpga_arid_axi_s2_o6;
+    output fabric_fpga_arid_axi_s2_o7;
+    output fabric_fpga_arid_axi_s2_o8;
+    output fabric_fpga_arid_axi_s2_o9;
+    input fabric_fpga_arlen_axi_m1_i1;
+    input fabric_fpga_arlen_axi_m1_i2;
+    input fabric_fpga_arlen_axi_m1_i3;
+    input fabric_fpga_arlen_axi_m1_i4;
+    input fabric_fpga_arlen_axi_m1_i5;
+    input fabric_fpga_arlen_axi_m1_i6;
+    input fabric_fpga_arlen_axi_m1_i7;
+    input fabric_fpga_arlen_axi_m1_i8;
+    input fabric_fpga_arlen_axi_m2_i1;
+    input fabric_fpga_arlen_axi_m2_i2;
+    input fabric_fpga_arlen_axi_m2_i3;
+    input fabric_fpga_arlen_axi_m2_i4;
+    input fabric_fpga_arlen_axi_m2_i5;
+    input fabric_fpga_arlen_axi_m2_i6;
+    input fabric_fpga_arlen_axi_m2_i7;
+    input fabric_fpga_arlen_axi_m2_i8;
+    output fabric_fpga_arlen_axi_s1_o1;
+    output fabric_fpga_arlen_axi_s1_o2;
+    output fabric_fpga_arlen_axi_s1_o3;
+    output fabric_fpga_arlen_axi_s1_o4;
+    output fabric_fpga_arlen_axi_s1_o5;
+    output fabric_fpga_arlen_axi_s1_o6;
+    output fabric_fpga_arlen_axi_s1_o7;
+    output fabric_fpga_arlen_axi_s1_o8;
+    output fabric_fpga_arlen_axi_s2_o1;
+    output fabric_fpga_arlen_axi_s2_o2;
+    output fabric_fpga_arlen_axi_s2_o3;
+    output fabric_fpga_arlen_axi_s2_o4;
+    output fabric_fpga_arlen_axi_s2_o5;
+    output fabric_fpga_arlen_axi_s2_o6;
+    output fabric_fpga_arlen_axi_s2_o7;
+    output fabric_fpga_arlen_axi_s2_o8;
+    input fabric_fpga_arlock_axi_m1_i;
+    input fabric_fpga_arlock_axi_m2_i;
+    output fabric_fpga_arlock_axi_s1_o;
+    output fabric_fpga_arlock_axi_s2_o;
+    input fabric_fpga_arprot_axi_m1_i1;
+    input fabric_fpga_arprot_axi_m1_i2;
+    input fabric_fpga_arprot_axi_m1_i3;
+    input fabric_fpga_arprot_axi_m2_i1;
+    input fabric_fpga_arprot_axi_m2_i2;
+    input fabric_fpga_arprot_axi_m2_i3;
+    output fabric_fpga_arprot_axi_s1_o1;
+    output fabric_fpga_arprot_axi_s1_o2;
+    output fabric_fpga_arprot_axi_s1_o3;
+    output fabric_fpga_arprot_axi_s2_o1;
+    output fabric_fpga_arprot_axi_s2_o2;
+    output fabric_fpga_arprot_axi_s2_o3;
+    input fabric_fpga_arqos_axi_m1_i1;
+    input fabric_fpga_arqos_axi_m1_i2;
+    input fabric_fpga_arqos_axi_m1_i3;
+    input fabric_fpga_arqos_axi_m1_i4;
+    input fabric_fpga_arqos_axi_m2_i1;
+    input fabric_fpga_arqos_axi_m2_i2;
+    input fabric_fpga_arqos_axi_m2_i3;
+    input fabric_fpga_arqos_axi_m2_i4;
+    output fabric_fpga_arqos_axi_s1_o1;
+    output fabric_fpga_arqos_axi_s1_o2;
+    output fabric_fpga_arqos_axi_s1_o3;
+    output fabric_fpga_arqos_axi_s1_o4;
+    output fabric_fpga_arqos_axi_s2_o1;
+    output fabric_fpga_arqos_axi_s2_o2;
+    output fabric_fpga_arqos_axi_s2_o3;
+    output fabric_fpga_arqos_axi_s2_o4;
+    output fabric_fpga_arready_axi_m1_o;
+    output fabric_fpga_arready_axi_m2_o;
+    input fabric_fpga_arready_axi_s1_i;
+    input fabric_fpga_arready_axi_s2_i;
+    output fabric_fpga_arregion_axi_s1_o1;
+    output fabric_fpga_arregion_axi_s1_o2;
+    output fabric_fpga_arregion_axi_s1_o3;
+    output fabric_fpga_arregion_axi_s1_o4;
+    output fabric_fpga_arregion_axi_s2_o1;
+    output fabric_fpga_arregion_axi_s2_o2;
+    output fabric_fpga_arregion_axi_s2_o3;
+    output fabric_fpga_arregion_axi_s2_o4;
+    input fabric_fpga_arsize_axi_m1_i1;
+    input fabric_fpga_arsize_axi_m1_i2;
+    input fabric_fpga_arsize_axi_m1_i3;
+    input fabric_fpga_arsize_axi_m2_i1;
+    input fabric_fpga_arsize_axi_m2_i2;
+    input fabric_fpga_arsize_axi_m2_i3;
+    output fabric_fpga_arsize_axi_s1_o1;
+    output fabric_fpga_arsize_axi_s1_o2;
+    output fabric_fpga_arsize_axi_s1_o3;
+    output fabric_fpga_arsize_axi_s2_o1;
+    output fabric_fpga_arsize_axi_s2_o2;
+    output fabric_fpga_arsize_axi_s2_o3;
+    input fabric_fpga_arvalid_axi_m1_i;
+    input fabric_fpga_arvalid_axi_m2_i;
+    output fabric_fpga_arvalid_axi_s1_o;
+    output fabric_fpga_arvalid_axi_s2_o;
+    input fabric_fpga_awaddr_axi_m1_i1;
+    input fabric_fpga_awaddr_axi_m1_i10;
+    input fabric_fpga_awaddr_axi_m1_i11;
+    input fabric_fpga_awaddr_axi_m1_i12;
+    input fabric_fpga_awaddr_axi_m1_i13;
+    input fabric_fpga_awaddr_axi_m1_i14;
+    input fabric_fpga_awaddr_axi_m1_i15;
+    input fabric_fpga_awaddr_axi_m1_i16;
+    input fabric_fpga_awaddr_axi_m1_i17;
+    input fabric_fpga_awaddr_axi_m1_i18;
+    input fabric_fpga_awaddr_axi_m1_i19;
+    input fabric_fpga_awaddr_axi_m1_i2;
+    input fabric_fpga_awaddr_axi_m1_i20;
+    input fabric_fpga_awaddr_axi_m1_i21;
+    input fabric_fpga_awaddr_axi_m1_i22;
+    input fabric_fpga_awaddr_axi_m1_i23;
+    input fabric_fpga_awaddr_axi_m1_i24;
+    input fabric_fpga_awaddr_axi_m1_i25;
+    input fabric_fpga_awaddr_axi_m1_i26;
+    input fabric_fpga_awaddr_axi_m1_i27;
+    input fabric_fpga_awaddr_axi_m1_i28;
+    input fabric_fpga_awaddr_axi_m1_i29;
+    input fabric_fpga_awaddr_axi_m1_i3;
+    input fabric_fpga_awaddr_axi_m1_i30;
+    input fabric_fpga_awaddr_axi_m1_i31;
+    input fabric_fpga_awaddr_axi_m1_i32;
+    input fabric_fpga_awaddr_axi_m1_i33;
+    input fabric_fpga_awaddr_axi_m1_i34;
+    input fabric_fpga_awaddr_axi_m1_i35;
+    input fabric_fpga_awaddr_axi_m1_i36;
+    input fabric_fpga_awaddr_axi_m1_i37;
+    input fabric_fpga_awaddr_axi_m1_i38;
+    input fabric_fpga_awaddr_axi_m1_i39;
+    input fabric_fpga_awaddr_axi_m1_i4;
+    input fabric_fpga_awaddr_axi_m1_i40;
+    input fabric_fpga_awaddr_axi_m1_i5;
+    input fabric_fpga_awaddr_axi_m1_i6;
+    input fabric_fpga_awaddr_axi_m1_i7;
+    input fabric_fpga_awaddr_axi_m1_i8;
+    input fabric_fpga_awaddr_axi_m1_i9;
+    input fabric_fpga_awaddr_axi_m2_i1;
+    input fabric_fpga_awaddr_axi_m2_i10;
+    input fabric_fpga_awaddr_axi_m2_i11;
+    input fabric_fpga_awaddr_axi_m2_i12;
+    input fabric_fpga_awaddr_axi_m2_i13;
+    input fabric_fpga_awaddr_axi_m2_i14;
+    input fabric_fpga_awaddr_axi_m2_i15;
+    input fabric_fpga_awaddr_axi_m2_i16;
+    input fabric_fpga_awaddr_axi_m2_i17;
+    input fabric_fpga_awaddr_axi_m2_i18;
+    input fabric_fpga_awaddr_axi_m2_i19;
+    input fabric_fpga_awaddr_axi_m2_i2;
+    input fabric_fpga_awaddr_axi_m2_i20;
+    input fabric_fpga_awaddr_axi_m2_i21;
+    input fabric_fpga_awaddr_axi_m2_i22;
+    input fabric_fpga_awaddr_axi_m2_i23;
+    input fabric_fpga_awaddr_axi_m2_i24;
+    input fabric_fpga_awaddr_axi_m2_i25;
+    input fabric_fpga_awaddr_axi_m2_i26;
+    input fabric_fpga_awaddr_axi_m2_i27;
+    input fabric_fpga_awaddr_axi_m2_i28;
+    input fabric_fpga_awaddr_axi_m2_i29;
+    input fabric_fpga_awaddr_axi_m2_i3;
+    input fabric_fpga_awaddr_axi_m2_i30;
+    input fabric_fpga_awaddr_axi_m2_i31;
+    input fabric_fpga_awaddr_axi_m2_i32;
+    input fabric_fpga_awaddr_axi_m2_i33;
+    input fabric_fpga_awaddr_axi_m2_i34;
+    input fabric_fpga_awaddr_axi_m2_i35;
+    input fabric_fpga_awaddr_axi_m2_i36;
+    input fabric_fpga_awaddr_axi_m2_i37;
+    input fabric_fpga_awaddr_axi_m2_i38;
+    input fabric_fpga_awaddr_axi_m2_i39;
+    input fabric_fpga_awaddr_axi_m2_i4;
+    input fabric_fpga_awaddr_axi_m2_i40;
+    input fabric_fpga_awaddr_axi_m2_i5;
+    input fabric_fpga_awaddr_axi_m2_i6;
+    input fabric_fpga_awaddr_axi_m2_i7;
+    input fabric_fpga_awaddr_axi_m2_i8;
+    input fabric_fpga_awaddr_axi_m2_i9;
+    output fabric_fpga_awaddr_axi_s1_o1;
+    output fabric_fpga_awaddr_axi_s1_o10;
+    output fabric_fpga_awaddr_axi_s1_o11;
+    output fabric_fpga_awaddr_axi_s1_o12;
+    output fabric_fpga_awaddr_axi_s1_o13;
+    output fabric_fpga_awaddr_axi_s1_o14;
+    output fabric_fpga_awaddr_axi_s1_o15;
+    output fabric_fpga_awaddr_axi_s1_o16;
+    output fabric_fpga_awaddr_axi_s1_o17;
+    output fabric_fpga_awaddr_axi_s1_o18;
+    output fabric_fpga_awaddr_axi_s1_o19;
+    output fabric_fpga_awaddr_axi_s1_o2;
+    output fabric_fpga_awaddr_axi_s1_o20;
+    output fabric_fpga_awaddr_axi_s1_o21;
+    output fabric_fpga_awaddr_axi_s1_o22;
+    output fabric_fpga_awaddr_axi_s1_o23;
+    output fabric_fpga_awaddr_axi_s1_o24;
+    output fabric_fpga_awaddr_axi_s1_o25;
+    output fabric_fpga_awaddr_axi_s1_o26;
+    output fabric_fpga_awaddr_axi_s1_o27;
+    output fabric_fpga_awaddr_axi_s1_o28;
+    output fabric_fpga_awaddr_axi_s1_o29;
+    output fabric_fpga_awaddr_axi_s1_o3;
+    output fabric_fpga_awaddr_axi_s1_o30;
+    output fabric_fpga_awaddr_axi_s1_o31;
+    output fabric_fpga_awaddr_axi_s1_o32;
+    output fabric_fpga_awaddr_axi_s1_o33;
+    output fabric_fpga_awaddr_axi_s1_o34;
+    output fabric_fpga_awaddr_axi_s1_o35;
+    output fabric_fpga_awaddr_axi_s1_o36;
+    output fabric_fpga_awaddr_axi_s1_o37;
+    output fabric_fpga_awaddr_axi_s1_o38;
+    output fabric_fpga_awaddr_axi_s1_o39;
+    output fabric_fpga_awaddr_axi_s1_o4;
+    output fabric_fpga_awaddr_axi_s1_o40;
+    output fabric_fpga_awaddr_axi_s1_o5;
+    output fabric_fpga_awaddr_axi_s1_o6;
+    output fabric_fpga_awaddr_axi_s1_o7;
+    output fabric_fpga_awaddr_axi_s1_o8;
+    output fabric_fpga_awaddr_axi_s1_o9;
+    output fabric_fpga_awaddr_axi_s2_o1;
+    output fabric_fpga_awaddr_axi_s2_o10;
+    output fabric_fpga_awaddr_axi_s2_o11;
+    output fabric_fpga_awaddr_axi_s2_o12;
+    output fabric_fpga_awaddr_axi_s2_o13;
+    output fabric_fpga_awaddr_axi_s2_o14;
+    output fabric_fpga_awaddr_axi_s2_o15;
+    output fabric_fpga_awaddr_axi_s2_o16;
+    output fabric_fpga_awaddr_axi_s2_o17;
+    output fabric_fpga_awaddr_axi_s2_o18;
+    output fabric_fpga_awaddr_axi_s2_o19;
+    output fabric_fpga_awaddr_axi_s2_o2;
+    output fabric_fpga_awaddr_axi_s2_o20;
+    output fabric_fpga_awaddr_axi_s2_o21;
+    output fabric_fpga_awaddr_axi_s2_o22;
+    output fabric_fpga_awaddr_axi_s2_o23;
+    output fabric_fpga_awaddr_axi_s2_o24;
+    output fabric_fpga_awaddr_axi_s2_o25;
+    output fabric_fpga_awaddr_axi_s2_o26;
+    output fabric_fpga_awaddr_axi_s2_o27;
+    output fabric_fpga_awaddr_axi_s2_o28;
+    output fabric_fpga_awaddr_axi_s2_o29;
+    output fabric_fpga_awaddr_axi_s2_o3;
+    output fabric_fpga_awaddr_axi_s2_o30;
+    output fabric_fpga_awaddr_axi_s2_o31;
+    output fabric_fpga_awaddr_axi_s2_o32;
+    output fabric_fpga_awaddr_axi_s2_o33;
+    output fabric_fpga_awaddr_axi_s2_o34;
+    output fabric_fpga_awaddr_axi_s2_o35;
+    output fabric_fpga_awaddr_axi_s2_o36;
+    output fabric_fpga_awaddr_axi_s2_o37;
+    output fabric_fpga_awaddr_axi_s2_o38;
+    output fabric_fpga_awaddr_axi_s2_o39;
+    output fabric_fpga_awaddr_axi_s2_o4;
+    output fabric_fpga_awaddr_axi_s2_o40;
+    output fabric_fpga_awaddr_axi_s2_o5;
+    output fabric_fpga_awaddr_axi_s2_o6;
+    output fabric_fpga_awaddr_axi_s2_o7;
+    output fabric_fpga_awaddr_axi_s2_o8;
+    output fabric_fpga_awaddr_axi_s2_o9;
+    input fabric_fpga_awburst_axi_m1_i1;
+    input fabric_fpga_awburst_axi_m1_i2;
+    input fabric_fpga_awburst_axi_m2_i1;
+    input fabric_fpga_awburst_axi_m2_i2;
+    output fabric_fpga_awburst_axi_s1_o1;
+    output fabric_fpga_awburst_axi_s1_o2;
+    output fabric_fpga_awburst_axi_s2_o1;
+    output fabric_fpga_awburst_axi_s2_o2;
+    input fabric_fpga_awcache_axi_m1_i1;
+    input fabric_fpga_awcache_axi_m1_i2;
+    input fabric_fpga_awcache_axi_m1_i3;
+    input fabric_fpga_awcache_axi_m1_i4;
+    input fabric_fpga_awcache_axi_m2_i1;
+    input fabric_fpga_awcache_axi_m2_i2;
+    input fabric_fpga_awcache_axi_m2_i3;
+    input fabric_fpga_awcache_axi_m2_i4;
+    output fabric_fpga_awcache_axi_s1_o1;
+    output fabric_fpga_awcache_axi_s1_o2;
+    output fabric_fpga_awcache_axi_s1_o3;
+    output fabric_fpga_awcache_axi_s1_o4;
+    output fabric_fpga_awcache_axi_s2_o1;
+    output fabric_fpga_awcache_axi_s2_o2;
+    output fabric_fpga_awcache_axi_s2_o3;
+    output fabric_fpga_awcache_axi_s2_o4;
+    input fabric_fpga_awid_axi_m1_i1;
+    input fabric_fpga_awid_axi_m1_i2;
+    input fabric_fpga_awid_axi_m1_i3;
+    input fabric_fpga_awid_axi_m1_i4;
+    input fabric_fpga_awid_axi_m1_i5;
+    input fabric_fpga_awid_axi_m2_i1;
+    input fabric_fpga_awid_axi_m2_i2;
+    input fabric_fpga_awid_axi_m2_i3;
+    input fabric_fpga_awid_axi_m2_i4;
+    input fabric_fpga_awid_axi_m2_i5;
+    output fabric_fpga_awid_axi_s1_o1;
+    output fabric_fpga_awid_axi_s1_o10;
+    output fabric_fpga_awid_axi_s1_o11;
+    output fabric_fpga_awid_axi_s1_o12;
+    output fabric_fpga_awid_axi_s1_o2;
+    output fabric_fpga_awid_axi_s1_o3;
+    output fabric_fpga_awid_axi_s1_o4;
+    output fabric_fpga_awid_axi_s1_o5;
+    output fabric_fpga_awid_axi_s1_o6;
+    output fabric_fpga_awid_axi_s1_o7;
+    output fabric_fpga_awid_axi_s1_o8;
+    output fabric_fpga_awid_axi_s1_o9;
+    output fabric_fpga_awid_axi_s2_o1;
+    output fabric_fpga_awid_axi_s2_o10;
+    output fabric_fpga_awid_axi_s2_o11;
+    output fabric_fpga_awid_axi_s2_o12;
+    output fabric_fpga_awid_axi_s2_o2;
+    output fabric_fpga_awid_axi_s2_o3;
+    output fabric_fpga_awid_axi_s2_o4;
+    output fabric_fpga_awid_axi_s2_o5;
+    output fabric_fpga_awid_axi_s2_o6;
+    output fabric_fpga_awid_axi_s2_o7;
+    output fabric_fpga_awid_axi_s2_o8;
+    output fabric_fpga_awid_axi_s2_o9;
+    input fabric_fpga_awlen_axi_m1_i1;
+    input fabric_fpga_awlen_axi_m1_i2;
+    input fabric_fpga_awlen_axi_m1_i3;
+    input fabric_fpga_awlen_axi_m1_i4;
+    input fabric_fpga_awlen_axi_m1_i5;
+    input fabric_fpga_awlen_axi_m1_i6;
+    input fabric_fpga_awlen_axi_m1_i7;
+    input fabric_fpga_awlen_axi_m1_i8;
+    input fabric_fpga_awlen_axi_m2_i1;
+    input fabric_fpga_awlen_axi_m2_i2;
+    input fabric_fpga_awlen_axi_m2_i3;
+    input fabric_fpga_awlen_axi_m2_i4;
+    input fabric_fpga_awlen_axi_m2_i5;
+    input fabric_fpga_awlen_axi_m2_i6;
+    input fabric_fpga_awlen_axi_m2_i7;
+    input fabric_fpga_awlen_axi_m2_i8;
+    output fabric_fpga_awlen_axi_s1_o1;
+    output fabric_fpga_awlen_axi_s1_o2;
+    output fabric_fpga_awlen_axi_s1_o3;
+    output fabric_fpga_awlen_axi_s1_o4;
+    output fabric_fpga_awlen_axi_s1_o5;
+    output fabric_fpga_awlen_axi_s1_o6;
+    output fabric_fpga_awlen_axi_s1_o7;
+    output fabric_fpga_awlen_axi_s1_o8;
+    output fabric_fpga_awlen_axi_s2_o1;
+    output fabric_fpga_awlen_axi_s2_o2;
+    output fabric_fpga_awlen_axi_s2_o3;
+    output fabric_fpga_awlen_axi_s2_o4;
+    output fabric_fpga_awlen_axi_s2_o5;
+    output fabric_fpga_awlen_axi_s2_o6;
+    output fabric_fpga_awlen_axi_s2_o7;
+    output fabric_fpga_awlen_axi_s2_o8;
+    input fabric_fpga_awlock_axi_m1_i;
+    input fabric_fpga_awlock_axi_m2_i;
+    output fabric_fpga_awlock_axi_s1_o;
+    output fabric_fpga_awlock_axi_s2_o;
+    input fabric_fpga_awprot_axi_m1_i1;
+    input fabric_fpga_awprot_axi_m1_i2;
+    input fabric_fpga_awprot_axi_m1_i3;
+    input fabric_fpga_awprot_axi_m2_i1;
+    input fabric_fpga_awprot_axi_m2_i2;
+    input fabric_fpga_awprot_axi_m2_i3;
+    output fabric_fpga_awprot_axi_s1_o1;
+    output fabric_fpga_awprot_axi_s1_o2;
+    output fabric_fpga_awprot_axi_s1_o3;
+    output fabric_fpga_awprot_axi_s2_o1;
+    output fabric_fpga_awprot_axi_s2_o2;
+    output fabric_fpga_awprot_axi_s2_o3;
+    input fabric_fpga_awqos_axi_m1_i1;
+    input fabric_fpga_awqos_axi_m1_i2;
+    input fabric_fpga_awqos_axi_m1_i3;
+    input fabric_fpga_awqos_axi_m1_i4;
+    input fabric_fpga_awqos_axi_m2_i1;
+    input fabric_fpga_awqos_axi_m2_i2;
+    input fabric_fpga_awqos_axi_m2_i3;
+    input fabric_fpga_awqos_axi_m2_i4;
+    output fabric_fpga_awqos_axi_s1_o1;
+    output fabric_fpga_awqos_axi_s1_o2;
+    output fabric_fpga_awqos_axi_s1_o3;
+    output fabric_fpga_awqos_axi_s1_o4;
+    output fabric_fpga_awqos_axi_s2_o1;
+    output fabric_fpga_awqos_axi_s2_o2;
+    output fabric_fpga_awqos_axi_s2_o3;
+    output fabric_fpga_awqos_axi_s2_o4;
+    output fabric_fpga_awready_axi_m1_o;
+    output fabric_fpga_awready_axi_m2_o;
+    input fabric_fpga_awready_axi_s1_i;
+    input fabric_fpga_awready_axi_s2_i;
+    output fabric_fpga_awregion_axi_s1_o1;
+    output fabric_fpga_awregion_axi_s1_o2;
+    output fabric_fpga_awregion_axi_s1_o3;
+    output fabric_fpga_awregion_axi_s1_o4;
+    output fabric_fpga_awregion_axi_s2_o1;
+    output fabric_fpga_awregion_axi_s2_o2;
+    output fabric_fpga_awregion_axi_s2_o3;
+    output fabric_fpga_awregion_axi_s2_o4;
+    input fabric_fpga_awsize_axi_m1_i1;
+    input fabric_fpga_awsize_axi_m1_i2;
+    input fabric_fpga_awsize_axi_m1_i3;
+    input fabric_fpga_awsize_axi_m2_i1;
+    input fabric_fpga_awsize_axi_m2_i2;
+    input fabric_fpga_awsize_axi_m2_i3;
+    output fabric_fpga_awsize_axi_s1_o1;
+    output fabric_fpga_awsize_axi_s1_o2;
+    output fabric_fpga_awsize_axi_s1_o3;
+    output fabric_fpga_awsize_axi_s2_o1;
+    output fabric_fpga_awsize_axi_s2_o2;
+    output fabric_fpga_awsize_axi_s2_o3;
+    input fabric_fpga_awvalid_axi_m1_i;
+    input fabric_fpga_awvalid_axi_m2_i;
+    output fabric_fpga_awvalid_axi_s1_o;
+    output fabric_fpga_awvalid_axi_s2_o;
+    output fabric_fpga_bid_axi_m1_o1;
+    output fabric_fpga_bid_axi_m1_o2;
+    output fabric_fpga_bid_axi_m1_o3;
+    output fabric_fpga_bid_axi_m1_o4;
+    output fabric_fpga_bid_axi_m1_o5;
+    output fabric_fpga_bid_axi_m2_o1;
+    output fabric_fpga_bid_axi_m2_o2;
+    output fabric_fpga_bid_axi_m2_o3;
+    output fabric_fpga_bid_axi_m2_o4;
+    output fabric_fpga_bid_axi_m2_o5;
+    input fabric_fpga_bid_axi_s1_i1;
+    input fabric_fpga_bid_axi_s1_i10;
+    input fabric_fpga_bid_axi_s1_i11;
+    input fabric_fpga_bid_axi_s1_i12;
+    input fabric_fpga_bid_axi_s1_i2;
+    input fabric_fpga_bid_axi_s1_i3;
+    input fabric_fpga_bid_axi_s1_i4;
+    input fabric_fpga_bid_axi_s1_i5;
+    input fabric_fpga_bid_axi_s1_i6;
+    input fabric_fpga_bid_axi_s1_i7;
+    input fabric_fpga_bid_axi_s1_i8;
+    input fabric_fpga_bid_axi_s1_i9;
+    input fabric_fpga_bid_axi_s2_i1;
+    input fabric_fpga_bid_axi_s2_i10;
+    input fabric_fpga_bid_axi_s2_i11;
+    input fabric_fpga_bid_axi_s2_i12;
+    input fabric_fpga_bid_axi_s2_i2;
+    input fabric_fpga_bid_axi_s2_i3;
+    input fabric_fpga_bid_axi_s2_i4;
+    input fabric_fpga_bid_axi_s2_i5;
+    input fabric_fpga_bid_axi_s2_i6;
+    input fabric_fpga_bid_axi_s2_i7;
+    input fabric_fpga_bid_axi_s2_i8;
+    input fabric_fpga_bid_axi_s2_i9;
+    input fabric_fpga_bready_axi_m1_i;
+    input fabric_fpga_bready_axi_m2_i;
+    output fabric_fpga_bready_axi_s1_o;
+    output fabric_fpga_bready_axi_s2_o;
+    output fabric_fpga_bresp_axi_m1_o1;
+    output fabric_fpga_bresp_axi_m1_o2;
+    output fabric_fpga_bresp_axi_m2_o1;
+    output fabric_fpga_bresp_axi_m2_o2;
+    input fabric_fpga_bresp_axi_s1_i1;
+    input fabric_fpga_bresp_axi_s1_i2;
+    input fabric_fpga_bresp_axi_s2_i1;
+    input fabric_fpga_bresp_axi_s2_i2;
+    output fabric_fpga_bvalid_axi_m1_o;
+    output fabric_fpga_bvalid_axi_m2_o;
+    input fabric_fpga_bvalid_axi_s1_i;
+    input fabric_fpga_bvalid_axi_s2_i;
+    input fabric_fpga_ddr0_araddr_i1;
+    input fabric_fpga_ddr0_araddr_i10;
+    input fabric_fpga_ddr0_araddr_i11;
+    input fabric_fpga_ddr0_araddr_i12;
+    input fabric_fpga_ddr0_araddr_i13;
+    input fabric_fpga_ddr0_araddr_i14;
+    input fabric_fpga_ddr0_araddr_i15;
+    input fabric_fpga_ddr0_araddr_i16;
+    input fabric_fpga_ddr0_araddr_i17;
+    input fabric_fpga_ddr0_araddr_i18;
+    input fabric_fpga_ddr0_araddr_i19;
+    input fabric_fpga_ddr0_araddr_i2;
+    input fabric_fpga_ddr0_araddr_i20;
+    input fabric_fpga_ddr0_araddr_i21;
+    input fabric_fpga_ddr0_araddr_i22;
+    input fabric_fpga_ddr0_araddr_i23;
+    input fabric_fpga_ddr0_araddr_i24;
+    input fabric_fpga_ddr0_araddr_i25;
+    input fabric_fpga_ddr0_araddr_i26;
+    input fabric_fpga_ddr0_araddr_i27;
+    input fabric_fpga_ddr0_araddr_i28;
+    input fabric_fpga_ddr0_araddr_i29;
+    input fabric_fpga_ddr0_araddr_i3;
+    input fabric_fpga_ddr0_araddr_i30;
+    input fabric_fpga_ddr0_araddr_i31;
+    input fabric_fpga_ddr0_araddr_i32;
+    input fabric_fpga_ddr0_araddr_i33;
+    input fabric_fpga_ddr0_araddr_i34;
+    input fabric_fpga_ddr0_araddr_i35;
+    input fabric_fpga_ddr0_araddr_i36;
+    input fabric_fpga_ddr0_araddr_i37;
+    input fabric_fpga_ddr0_araddr_i38;
+    input fabric_fpga_ddr0_araddr_i39;
+    input fabric_fpga_ddr0_araddr_i4;
+    input fabric_fpga_ddr0_araddr_i40;
+    input fabric_fpga_ddr0_araddr_i5;
+    input fabric_fpga_ddr0_araddr_i6;
+    input fabric_fpga_ddr0_araddr_i7;
+    input fabric_fpga_ddr0_araddr_i8;
+    input fabric_fpga_ddr0_araddr_i9;
+    input fabric_fpga_ddr0_arburst_i1;
+    input fabric_fpga_ddr0_arburst_i2;
+    input fabric_fpga_ddr0_arcache_i1;
+    input fabric_fpga_ddr0_arcache_i2;
+    input fabric_fpga_ddr0_arcache_i3;
+    input fabric_fpga_ddr0_arcache_i4;
+    input fabric_fpga_ddr0_arid_i1;
+    input fabric_fpga_ddr0_arid_i2;
+    input fabric_fpga_ddr0_arid_i3;
+    input fabric_fpga_ddr0_arid_i4;
+    input fabric_fpga_ddr0_arid_i5;
+    input fabric_fpga_ddr0_arlen_i1;
+    input fabric_fpga_ddr0_arlen_i2;
+    input fabric_fpga_ddr0_arlen_i3;
+    input fabric_fpga_ddr0_arlen_i4;
+    input fabric_fpga_ddr0_arlen_i5;
+    input fabric_fpga_ddr0_arlen_i6;
+    input fabric_fpga_ddr0_arlen_i7;
+    input fabric_fpga_ddr0_arlen_i8;
+    input fabric_fpga_ddr0_arlock_i;
+    input fabric_fpga_ddr0_arprot_i1;
+    input fabric_fpga_ddr0_arprot_i2;
+    input fabric_fpga_ddr0_arprot_i3;
+    input fabric_fpga_ddr0_arqos_i1;
+    input fabric_fpga_ddr0_arqos_i2;
+    input fabric_fpga_ddr0_arqos_i3;
+    input fabric_fpga_ddr0_arqos_i4;
+    output fabric_fpga_ddr0_arready_o;
+    input fabric_fpga_ddr0_arsize_i1;
+    input fabric_fpga_ddr0_arsize_i2;
+    input fabric_fpga_ddr0_arsize_i3;
+    input fabric_fpga_ddr0_arvalid_i;
+    input fabric_fpga_ddr0_awaddr_i1;
+    input fabric_fpga_ddr0_awaddr_i10;
+    input fabric_fpga_ddr0_awaddr_i11;
+    input fabric_fpga_ddr0_awaddr_i12;
+    input fabric_fpga_ddr0_awaddr_i13;
+    input fabric_fpga_ddr0_awaddr_i14;
+    input fabric_fpga_ddr0_awaddr_i15;
+    input fabric_fpga_ddr0_awaddr_i16;
+    input fabric_fpga_ddr0_awaddr_i17;
+    input fabric_fpga_ddr0_awaddr_i18;
+    input fabric_fpga_ddr0_awaddr_i19;
+    input fabric_fpga_ddr0_awaddr_i2;
+    input fabric_fpga_ddr0_awaddr_i20;
+    input fabric_fpga_ddr0_awaddr_i21;
+    input fabric_fpga_ddr0_awaddr_i22;
+    input fabric_fpga_ddr0_awaddr_i23;
+    input fabric_fpga_ddr0_awaddr_i24;
+    input fabric_fpga_ddr0_awaddr_i25;
+    input fabric_fpga_ddr0_awaddr_i26;
+    input fabric_fpga_ddr0_awaddr_i27;
+    input fabric_fpga_ddr0_awaddr_i28;
+    input fabric_fpga_ddr0_awaddr_i29;
+    input fabric_fpga_ddr0_awaddr_i3;
+    input fabric_fpga_ddr0_awaddr_i30;
+    input fabric_fpga_ddr0_awaddr_i31;
+    input fabric_fpga_ddr0_awaddr_i32;
+    input fabric_fpga_ddr0_awaddr_i33;
+    input fabric_fpga_ddr0_awaddr_i34;
+    input fabric_fpga_ddr0_awaddr_i35;
+    input fabric_fpga_ddr0_awaddr_i36;
+    input fabric_fpga_ddr0_awaddr_i37;
+    input fabric_fpga_ddr0_awaddr_i38;
+    input fabric_fpga_ddr0_awaddr_i39;
+    input fabric_fpga_ddr0_awaddr_i4;
+    input fabric_fpga_ddr0_awaddr_i40;
+    input fabric_fpga_ddr0_awaddr_i5;
+    input fabric_fpga_ddr0_awaddr_i6;
+    input fabric_fpga_ddr0_awaddr_i7;
+    input fabric_fpga_ddr0_awaddr_i8;
+    input fabric_fpga_ddr0_awaddr_i9;
+    input fabric_fpga_ddr0_awburst_i1;
+    input fabric_fpga_ddr0_awburst_i2;
+    input fabric_fpga_ddr0_awcache_i1;
+    input fabric_fpga_ddr0_awcache_i2;
+    input fabric_fpga_ddr0_awcache_i3;
+    input fabric_fpga_ddr0_awcache_i4;
+    input fabric_fpga_ddr0_awid_i1;
+    input fabric_fpga_ddr0_awid_i2;
+    input fabric_fpga_ddr0_awid_i3;
+    input fabric_fpga_ddr0_awid_i4;
+    input fabric_fpga_ddr0_awid_i5;
+    input fabric_fpga_ddr0_awlen_i1;
+    input fabric_fpga_ddr0_awlen_i2;
+    input fabric_fpga_ddr0_awlen_i3;
+    input fabric_fpga_ddr0_awlen_i4;
+    input fabric_fpga_ddr0_awlen_i5;
+    input fabric_fpga_ddr0_awlen_i6;
+    input fabric_fpga_ddr0_awlen_i7;
+    input fabric_fpga_ddr0_awlen_i8;
+    input fabric_fpga_ddr0_awlock_i;
+    input fabric_fpga_ddr0_awprot_i1;
+    input fabric_fpga_ddr0_awprot_i2;
+    input fabric_fpga_ddr0_awprot_i3;
+    input fabric_fpga_ddr0_awqos_i1;
+    input fabric_fpga_ddr0_awqos_i2;
+    input fabric_fpga_ddr0_awqos_i3;
+    input fabric_fpga_ddr0_awqos_i4;
+    output fabric_fpga_ddr0_awready_o;
+    input fabric_fpga_ddr0_awsize_i1;
+    input fabric_fpga_ddr0_awsize_i2;
+    input fabric_fpga_ddr0_awsize_i3;
+    input fabric_fpga_ddr0_awvalid_i;
+    output fabric_fpga_ddr0_bid_o1;
+    output fabric_fpga_ddr0_bid_o2;
+    output fabric_fpga_ddr0_bid_o3;
+    output fabric_fpga_ddr0_bid_o4;
+    output fabric_fpga_ddr0_bid_o5;
+    input fabric_fpga_ddr0_bready_i;
+    output fabric_fpga_ddr0_bresp_o1;
+    output fabric_fpga_ddr0_bresp_o2;
+    output fabric_fpga_ddr0_bvalid_o;
+    output fabric_fpga_ddr0_rdata_o1;
+    output fabric_fpga_ddr0_rdata_o10;
+    output fabric_fpga_ddr0_rdata_o100;
+    output fabric_fpga_ddr0_rdata_o101;
+    output fabric_fpga_ddr0_rdata_o102;
+    output fabric_fpga_ddr0_rdata_o103;
+    output fabric_fpga_ddr0_rdata_o104;
+    output fabric_fpga_ddr0_rdata_o105;
+    output fabric_fpga_ddr0_rdata_o106;
+    output fabric_fpga_ddr0_rdata_o107;
+    output fabric_fpga_ddr0_rdata_o108;
+    output fabric_fpga_ddr0_rdata_o109;
+    output fabric_fpga_ddr0_rdata_o11;
+    output fabric_fpga_ddr0_rdata_o110;
+    output fabric_fpga_ddr0_rdata_o111;
+    output fabric_fpga_ddr0_rdata_o112;
+    output fabric_fpga_ddr0_rdata_o113;
+    output fabric_fpga_ddr0_rdata_o114;
+    output fabric_fpga_ddr0_rdata_o115;
+    output fabric_fpga_ddr0_rdata_o116;
+    output fabric_fpga_ddr0_rdata_o117;
+    output fabric_fpga_ddr0_rdata_o118;
+    output fabric_fpga_ddr0_rdata_o119;
+    output fabric_fpga_ddr0_rdata_o12;
+    output fabric_fpga_ddr0_rdata_o120;
+    output fabric_fpga_ddr0_rdata_o121;
+    output fabric_fpga_ddr0_rdata_o122;
+    output fabric_fpga_ddr0_rdata_o123;
+    output fabric_fpga_ddr0_rdata_o124;
+    output fabric_fpga_ddr0_rdata_o125;
+    output fabric_fpga_ddr0_rdata_o126;
+    output fabric_fpga_ddr0_rdata_o127;
+    output fabric_fpga_ddr0_rdata_o128;
+    output fabric_fpga_ddr0_rdata_o13;
+    output fabric_fpga_ddr0_rdata_o14;
+    output fabric_fpga_ddr0_rdata_o15;
+    output fabric_fpga_ddr0_rdata_o16;
+    output fabric_fpga_ddr0_rdata_o17;
+    output fabric_fpga_ddr0_rdata_o18;
+    output fabric_fpga_ddr0_rdata_o19;
+    output fabric_fpga_ddr0_rdata_o2;
+    output fabric_fpga_ddr0_rdata_o20;
+    output fabric_fpga_ddr0_rdata_o21;
+    output fabric_fpga_ddr0_rdata_o22;
+    output fabric_fpga_ddr0_rdata_o23;
+    output fabric_fpga_ddr0_rdata_o24;
+    output fabric_fpga_ddr0_rdata_o25;
+    output fabric_fpga_ddr0_rdata_o26;
+    output fabric_fpga_ddr0_rdata_o27;
+    output fabric_fpga_ddr0_rdata_o28;
+    output fabric_fpga_ddr0_rdata_o29;
+    output fabric_fpga_ddr0_rdata_o3;
+    output fabric_fpga_ddr0_rdata_o30;
+    output fabric_fpga_ddr0_rdata_o31;
+    output fabric_fpga_ddr0_rdata_o32;
+    output fabric_fpga_ddr0_rdata_o33;
+    output fabric_fpga_ddr0_rdata_o34;
+    output fabric_fpga_ddr0_rdata_o35;
+    output fabric_fpga_ddr0_rdata_o36;
+    output fabric_fpga_ddr0_rdata_o37;
+    output fabric_fpga_ddr0_rdata_o38;
+    output fabric_fpga_ddr0_rdata_o39;
+    output fabric_fpga_ddr0_rdata_o4;
+    output fabric_fpga_ddr0_rdata_o40;
+    output fabric_fpga_ddr0_rdata_o41;
+    output fabric_fpga_ddr0_rdata_o42;
+    output fabric_fpga_ddr0_rdata_o43;
+    output fabric_fpga_ddr0_rdata_o44;
+    output fabric_fpga_ddr0_rdata_o45;
+    output fabric_fpga_ddr0_rdata_o46;
+    output fabric_fpga_ddr0_rdata_o47;
+    output fabric_fpga_ddr0_rdata_o48;
+    output fabric_fpga_ddr0_rdata_o49;
+    output fabric_fpga_ddr0_rdata_o5;
+    output fabric_fpga_ddr0_rdata_o50;
+    output fabric_fpga_ddr0_rdata_o51;
+    output fabric_fpga_ddr0_rdata_o52;
+    output fabric_fpga_ddr0_rdata_o53;
+    output fabric_fpga_ddr0_rdata_o54;
+    output fabric_fpga_ddr0_rdata_o55;
+    output fabric_fpga_ddr0_rdata_o56;
+    output fabric_fpga_ddr0_rdata_o57;
+    output fabric_fpga_ddr0_rdata_o58;
+    output fabric_fpga_ddr0_rdata_o59;
+    output fabric_fpga_ddr0_rdata_o6;
+    output fabric_fpga_ddr0_rdata_o60;
+    output fabric_fpga_ddr0_rdata_o61;
+    output fabric_fpga_ddr0_rdata_o62;
+    output fabric_fpga_ddr0_rdata_o63;
+    output fabric_fpga_ddr0_rdata_o64;
+    output fabric_fpga_ddr0_rdata_o65;
+    output fabric_fpga_ddr0_rdata_o66;
+    output fabric_fpga_ddr0_rdata_o67;
+    output fabric_fpga_ddr0_rdata_o68;
+    output fabric_fpga_ddr0_rdata_o69;
+    output fabric_fpga_ddr0_rdata_o7;
+    output fabric_fpga_ddr0_rdata_o70;
+    output fabric_fpga_ddr0_rdata_o71;
+    output fabric_fpga_ddr0_rdata_o72;
+    output fabric_fpga_ddr0_rdata_o73;
+    output fabric_fpga_ddr0_rdata_o74;
+    output fabric_fpga_ddr0_rdata_o75;
+    output fabric_fpga_ddr0_rdata_o76;
+    output fabric_fpga_ddr0_rdata_o77;
+    output fabric_fpga_ddr0_rdata_o78;
+    output fabric_fpga_ddr0_rdata_o79;
+    output fabric_fpga_ddr0_rdata_o8;
+    output fabric_fpga_ddr0_rdata_o80;
+    output fabric_fpga_ddr0_rdata_o81;
+    output fabric_fpga_ddr0_rdata_o82;
+    output fabric_fpga_ddr0_rdata_o83;
+    output fabric_fpga_ddr0_rdata_o84;
+    output fabric_fpga_ddr0_rdata_o85;
+    output fabric_fpga_ddr0_rdata_o86;
+    output fabric_fpga_ddr0_rdata_o87;
+    output fabric_fpga_ddr0_rdata_o88;
+    output fabric_fpga_ddr0_rdata_o89;
+    output fabric_fpga_ddr0_rdata_o9;
+    output fabric_fpga_ddr0_rdata_o90;
+    output fabric_fpga_ddr0_rdata_o91;
+    output fabric_fpga_ddr0_rdata_o92;
+    output fabric_fpga_ddr0_rdata_o93;
+    output fabric_fpga_ddr0_rdata_o94;
+    output fabric_fpga_ddr0_rdata_o95;
+    output fabric_fpga_ddr0_rdata_o96;
+    output fabric_fpga_ddr0_rdata_o97;
+    output fabric_fpga_ddr0_rdata_o98;
+    output fabric_fpga_ddr0_rdata_o99;
+    output fabric_fpga_ddr0_rid_o1;
+    output fabric_fpga_ddr0_rid_o2;
+    output fabric_fpga_ddr0_rid_o3;
+    output fabric_fpga_ddr0_rid_o4;
+    output fabric_fpga_ddr0_rid_o5;
+    output fabric_fpga_ddr0_rlast_o;
+    input fabric_fpga_ddr0_rready_i;
+    output fabric_fpga_ddr0_rresp_o1;
+    output fabric_fpga_ddr0_rresp_o2;
+    output fabric_fpga_ddr0_rvalid_o;
+    input fabric_fpga_ddr0_wdata_i1;
+    input fabric_fpga_ddr0_wdata_i10;
+    input fabric_fpga_ddr0_wdata_i100;
+    input fabric_fpga_ddr0_wdata_i101;
+    input fabric_fpga_ddr0_wdata_i102;
+    input fabric_fpga_ddr0_wdata_i103;
+    input fabric_fpga_ddr0_wdata_i104;
+    input fabric_fpga_ddr0_wdata_i105;
+    input fabric_fpga_ddr0_wdata_i106;
+    input fabric_fpga_ddr0_wdata_i107;
+    input fabric_fpga_ddr0_wdata_i108;
+    input fabric_fpga_ddr0_wdata_i109;
+    input fabric_fpga_ddr0_wdata_i11;
+    input fabric_fpga_ddr0_wdata_i110;
+    input fabric_fpga_ddr0_wdata_i111;
+    input fabric_fpga_ddr0_wdata_i112;
+    input fabric_fpga_ddr0_wdata_i113;
+    input fabric_fpga_ddr0_wdata_i114;
+    input fabric_fpga_ddr0_wdata_i115;
+    input fabric_fpga_ddr0_wdata_i116;
+    input fabric_fpga_ddr0_wdata_i117;
+    input fabric_fpga_ddr0_wdata_i118;
+    input fabric_fpga_ddr0_wdata_i119;
+    input fabric_fpga_ddr0_wdata_i12;
+    input fabric_fpga_ddr0_wdata_i120;
+    input fabric_fpga_ddr0_wdata_i121;
+    input fabric_fpga_ddr0_wdata_i122;
+    input fabric_fpga_ddr0_wdata_i123;
+    input fabric_fpga_ddr0_wdata_i124;
+    input fabric_fpga_ddr0_wdata_i125;
+    input fabric_fpga_ddr0_wdata_i126;
+    input fabric_fpga_ddr0_wdata_i127;
+    input fabric_fpga_ddr0_wdata_i128;
+    input fabric_fpga_ddr0_wdata_i13;
+    input fabric_fpga_ddr0_wdata_i14;
+    input fabric_fpga_ddr0_wdata_i15;
+    input fabric_fpga_ddr0_wdata_i16;
+    input fabric_fpga_ddr0_wdata_i17;
+    input fabric_fpga_ddr0_wdata_i18;
+    input fabric_fpga_ddr0_wdata_i19;
+    input fabric_fpga_ddr0_wdata_i2;
+    input fabric_fpga_ddr0_wdata_i20;
+    input fabric_fpga_ddr0_wdata_i21;
+    input fabric_fpga_ddr0_wdata_i22;
+    input fabric_fpga_ddr0_wdata_i23;
+    input fabric_fpga_ddr0_wdata_i24;
+    input fabric_fpga_ddr0_wdata_i25;
+    input fabric_fpga_ddr0_wdata_i26;
+    input fabric_fpga_ddr0_wdata_i27;
+    input fabric_fpga_ddr0_wdata_i28;
+    input fabric_fpga_ddr0_wdata_i29;
+    input fabric_fpga_ddr0_wdata_i3;
+    input fabric_fpga_ddr0_wdata_i30;
+    input fabric_fpga_ddr0_wdata_i31;
+    input fabric_fpga_ddr0_wdata_i32;
+    input fabric_fpga_ddr0_wdata_i33;
+    input fabric_fpga_ddr0_wdata_i34;
+    input fabric_fpga_ddr0_wdata_i35;
+    input fabric_fpga_ddr0_wdata_i36;
+    input fabric_fpga_ddr0_wdata_i37;
+    input fabric_fpga_ddr0_wdata_i38;
+    input fabric_fpga_ddr0_wdata_i39;
+    input fabric_fpga_ddr0_wdata_i4;
+    input fabric_fpga_ddr0_wdata_i40;
+    input fabric_fpga_ddr0_wdata_i41;
+    input fabric_fpga_ddr0_wdata_i42;
+    input fabric_fpga_ddr0_wdata_i43;
+    input fabric_fpga_ddr0_wdata_i44;
+    input fabric_fpga_ddr0_wdata_i45;
+    input fabric_fpga_ddr0_wdata_i46;
+    input fabric_fpga_ddr0_wdata_i47;
+    input fabric_fpga_ddr0_wdata_i48;
+    input fabric_fpga_ddr0_wdata_i49;
+    input fabric_fpga_ddr0_wdata_i5;
+    input fabric_fpga_ddr0_wdata_i50;
+    input fabric_fpga_ddr0_wdata_i51;
+    input fabric_fpga_ddr0_wdata_i52;
+    input fabric_fpga_ddr0_wdata_i53;
+    input fabric_fpga_ddr0_wdata_i54;
+    input fabric_fpga_ddr0_wdata_i55;
+    input fabric_fpga_ddr0_wdata_i56;
+    input fabric_fpga_ddr0_wdata_i57;
+    input fabric_fpga_ddr0_wdata_i58;
+    input fabric_fpga_ddr0_wdata_i59;
+    input fabric_fpga_ddr0_wdata_i6;
+    input fabric_fpga_ddr0_wdata_i60;
+    input fabric_fpga_ddr0_wdata_i61;
+    input fabric_fpga_ddr0_wdata_i62;
+    input fabric_fpga_ddr0_wdata_i63;
+    input fabric_fpga_ddr0_wdata_i64;
+    input fabric_fpga_ddr0_wdata_i65;
+    input fabric_fpga_ddr0_wdata_i66;
+    input fabric_fpga_ddr0_wdata_i67;
+    input fabric_fpga_ddr0_wdata_i68;
+    input fabric_fpga_ddr0_wdata_i69;
+    input fabric_fpga_ddr0_wdata_i7;
+    input fabric_fpga_ddr0_wdata_i70;
+    input fabric_fpga_ddr0_wdata_i71;
+    input fabric_fpga_ddr0_wdata_i72;
+    input fabric_fpga_ddr0_wdata_i73;
+    input fabric_fpga_ddr0_wdata_i74;
+    input fabric_fpga_ddr0_wdata_i75;
+    input fabric_fpga_ddr0_wdata_i76;
+    input fabric_fpga_ddr0_wdata_i77;
+    input fabric_fpga_ddr0_wdata_i78;
+    input fabric_fpga_ddr0_wdata_i79;
+    input fabric_fpga_ddr0_wdata_i8;
+    input fabric_fpga_ddr0_wdata_i80;
+    input fabric_fpga_ddr0_wdata_i81;
+    input fabric_fpga_ddr0_wdata_i82;
+    input fabric_fpga_ddr0_wdata_i83;
+    input fabric_fpga_ddr0_wdata_i84;
+    input fabric_fpga_ddr0_wdata_i85;
+    input fabric_fpga_ddr0_wdata_i86;
+    input fabric_fpga_ddr0_wdata_i87;
+    input fabric_fpga_ddr0_wdata_i88;
+    input fabric_fpga_ddr0_wdata_i89;
+    input fabric_fpga_ddr0_wdata_i9;
+    input fabric_fpga_ddr0_wdata_i90;
+    input fabric_fpga_ddr0_wdata_i91;
+    input fabric_fpga_ddr0_wdata_i92;
+    input fabric_fpga_ddr0_wdata_i93;
+    input fabric_fpga_ddr0_wdata_i94;
+    input fabric_fpga_ddr0_wdata_i95;
+    input fabric_fpga_ddr0_wdata_i96;
+    input fabric_fpga_ddr0_wdata_i97;
+    input fabric_fpga_ddr0_wdata_i98;
+    input fabric_fpga_ddr0_wdata_i99;
+    input fabric_fpga_ddr0_wlast_i;
+    output fabric_fpga_ddr0_wready_o;
+    input fabric_fpga_ddr0_wstrb_i1;
+    input fabric_fpga_ddr0_wstrb_i10;
+    input fabric_fpga_ddr0_wstrb_i11;
+    input fabric_fpga_ddr0_wstrb_i12;
+    input fabric_fpga_ddr0_wstrb_i13;
+    input fabric_fpga_ddr0_wstrb_i14;
+    input fabric_fpga_ddr0_wstrb_i15;
+    input fabric_fpga_ddr0_wstrb_i16;
+    input fabric_fpga_ddr0_wstrb_i2;
+    input fabric_fpga_ddr0_wstrb_i3;
+    input fabric_fpga_ddr0_wstrb_i4;
+    input fabric_fpga_ddr0_wstrb_i5;
+    input fabric_fpga_ddr0_wstrb_i6;
+    input fabric_fpga_ddr0_wstrb_i7;
+    input fabric_fpga_ddr0_wstrb_i8;
+    input fabric_fpga_ddr0_wstrb_i9;
+    input fabric_fpga_ddr0_wvalid_i;
+    output fabric_fpga_dma_ack_m1_o1;
+    output fabric_fpga_dma_ack_m1_o2;
+    output fabric_fpga_dma_ack_m1_o3;
+    output fabric_fpga_dma_ack_m1_o4;
+    output fabric_fpga_dma_ack_m1_o5;
+    output fabric_fpga_dma_ack_m1_o6;
+    output fabric_fpga_dma_ack_m2_o1;
+    output fabric_fpga_dma_ack_m2_o2;
+    output fabric_fpga_dma_ack_m2_o3;
+    output fabric_fpga_dma_ack_m2_o4;
+    output fabric_fpga_dma_ack_m2_o5;
+    output fabric_fpga_dma_ack_m2_o6;
+    output fabric_fpga_dma_finish_m1_o1;
+    output fabric_fpga_dma_finish_m1_o2;
+    output fabric_fpga_dma_finish_m1_o3;
+    output fabric_fpga_dma_finish_m1_o4;
+    output fabric_fpga_dma_finish_m1_o5;
+    output fabric_fpga_dma_finish_m1_o6;
+    output fabric_fpga_dma_finish_m2_o1;
+    output fabric_fpga_dma_finish_m2_o2;
+    output fabric_fpga_dma_finish_m2_o3;
+    output fabric_fpga_dma_finish_m2_o4;
+    output fabric_fpga_dma_finish_m2_o5;
+    output fabric_fpga_dma_finish_m2_o6;
+    input fabric_fpga_dma_hs_rstn_i1;
+    input fabric_fpga_dma_hs_rstn_i2;
+    input fabric_fpga_dma_hs_rstn_i3;
+    input fabric_fpga_dma_hs_rstn_i4;
+    input fabric_fpga_dma_hs_rstn_i5;
+    input fabric_fpga_dma_hs_rstn_i6;
+    input fabric_fpga_dma_last_m1_i1;
+    input fabric_fpga_dma_last_m1_i2;
+    input fabric_fpga_dma_last_m1_i3;
+    input fabric_fpga_dma_last_m1_i4;
+    input fabric_fpga_dma_last_m1_i5;
+    input fabric_fpga_dma_last_m1_i6;
+    input fabric_fpga_dma_last_m2_i1;
+    input fabric_fpga_dma_last_m2_i2;
+    input fabric_fpga_dma_last_m2_i3;
+    input fabric_fpga_dma_last_m2_i4;
+    input fabric_fpga_dma_last_m2_i5;
+    input fabric_fpga_dma_last_m2_i6;
+    input fabric_fpga_dma_req_m1_i1;
+    input fabric_fpga_dma_req_m1_i2;
+    input fabric_fpga_dma_req_m1_i3;
+    input fabric_fpga_dma_req_m1_i4;
+    input fabric_fpga_dma_req_m1_i5;
+    input fabric_fpga_dma_req_m1_i6;
+    input fabric_fpga_dma_req_m2_i1;
+    input fabric_fpga_dma_req_m2_i2;
+    input fabric_fpga_dma_req_m2_i3;
+    input fabric_fpga_dma_req_m2_i4;
+    input fabric_fpga_dma_req_m2_i5;
+    input fabric_fpga_dma_req_m2_i6;
+    input fabric_fpga_dma_single_m1_i1;
+    input fabric_fpga_dma_single_m1_i2;
+    input fabric_fpga_dma_single_m1_i3;
+    input fabric_fpga_dma_single_m1_i4;
+    input fabric_fpga_dma_single_m1_i5;
+    input fabric_fpga_dma_single_m1_i6;
+    input fabric_fpga_dma_single_m2_i1;
+    input fabric_fpga_dma_single_m2_i2;
+    input fabric_fpga_dma_single_m2_i3;
+    input fabric_fpga_dma_single_m2_i4;
+    input fabric_fpga_dma_single_m2_i5;
+    input fabric_fpga_dma_single_m2_i6;
+    input fabric_fpga_events60_i1;
+    input fabric_fpga_events60_i10;
+    input fabric_fpga_events60_i11;
+    input fabric_fpga_events60_i12;
+    input fabric_fpga_events60_i13;
+    input fabric_fpga_events60_i14;
+    input fabric_fpga_events60_i15;
+    input fabric_fpga_events60_i16;
+    input fabric_fpga_events60_i17;
+    input fabric_fpga_events60_i18;
+    input fabric_fpga_events60_i19;
+    input fabric_fpga_events60_i2;
+    input fabric_fpga_events60_i20;
+    input fabric_fpga_events60_i21;
+    input fabric_fpga_events60_i22;
+    input fabric_fpga_events60_i23;
+    input fabric_fpga_events60_i24;
+    input fabric_fpga_events60_i25;
+    input fabric_fpga_events60_i26;
+    input fabric_fpga_events60_i27;
+    input fabric_fpga_events60_i28;
+    input fabric_fpga_events60_i29;
+    input fabric_fpga_events60_i3;
+    input fabric_fpga_events60_i30;
+    input fabric_fpga_events60_i31;
+    input fabric_fpga_events60_i32;
+    input fabric_fpga_events60_i33;
+    input fabric_fpga_events60_i34;
+    input fabric_fpga_events60_i35;
+    input fabric_fpga_events60_i36;
+    input fabric_fpga_events60_i37;
+    input fabric_fpga_events60_i38;
+    input fabric_fpga_events60_i39;
+    input fabric_fpga_events60_i4;
+    input fabric_fpga_events60_i40;
+    input fabric_fpga_events60_i41;
+    input fabric_fpga_events60_i42;
+    input fabric_fpga_events60_i43;
+    input fabric_fpga_events60_i44;
+    input fabric_fpga_events60_i45;
+    input fabric_fpga_events60_i46;
+    input fabric_fpga_events60_i47;
+    input fabric_fpga_events60_i48;
+    input fabric_fpga_events60_i49;
+    input fabric_fpga_events60_i5;
+    input fabric_fpga_events60_i50;
+    input fabric_fpga_events60_i51;
+    input fabric_fpga_events60_i52;
+    input fabric_fpga_events60_i53;
+    input fabric_fpga_events60_i54;
+    input fabric_fpga_events60_i55;
+    input fabric_fpga_events60_i56;
+    input fabric_fpga_events60_i57;
+    input fabric_fpga_events60_i58;
+    input fabric_fpga_events60_i59;
+    input fabric_fpga_events60_i6;
+    input fabric_fpga_events60_i60;
+    input fabric_fpga_events60_i7;
+    input fabric_fpga_events60_i8;
+    input fabric_fpga_events60_i9;
+    input fabric_fpga_interrupt_in_i1;
+    input fabric_fpga_interrupt_in_i10;
+    input fabric_fpga_interrupt_in_i100;
+    input fabric_fpga_interrupt_in_i101;
+    input fabric_fpga_interrupt_in_i102;
+    input fabric_fpga_interrupt_in_i103;
+    input fabric_fpga_interrupt_in_i104;
+    input fabric_fpga_interrupt_in_i105;
+    input fabric_fpga_interrupt_in_i106;
+    input fabric_fpga_interrupt_in_i107;
+    input fabric_fpga_interrupt_in_i108;
+    input fabric_fpga_interrupt_in_i109;
+    input fabric_fpga_interrupt_in_i11;
+    input fabric_fpga_interrupt_in_i110;
+    input fabric_fpga_interrupt_in_i111;
+    input fabric_fpga_interrupt_in_i112;
+    input fabric_fpga_interrupt_in_i113;
+    input fabric_fpga_interrupt_in_i114;
+    input fabric_fpga_interrupt_in_i115;
+    input fabric_fpga_interrupt_in_i116;
+    input fabric_fpga_interrupt_in_i117;
+    input fabric_fpga_interrupt_in_i118;
+    input fabric_fpga_interrupt_in_i119;
+    input fabric_fpga_interrupt_in_i12;
+    input fabric_fpga_interrupt_in_i120;
+    input fabric_fpga_interrupt_in_i13;
+    input fabric_fpga_interrupt_in_i14;
+    input fabric_fpga_interrupt_in_i15;
+    input fabric_fpga_interrupt_in_i16;
+    input fabric_fpga_interrupt_in_i17;
+    input fabric_fpga_interrupt_in_i18;
+    input fabric_fpga_interrupt_in_i19;
+    input fabric_fpga_interrupt_in_i2;
+    input fabric_fpga_interrupt_in_i20;
+    input fabric_fpga_interrupt_in_i21;
+    input fabric_fpga_interrupt_in_i22;
+    input fabric_fpga_interrupt_in_i23;
+    input fabric_fpga_interrupt_in_i24;
+    input fabric_fpga_interrupt_in_i25;
+    input fabric_fpga_interrupt_in_i26;
+    input fabric_fpga_interrupt_in_i27;
+    input fabric_fpga_interrupt_in_i28;
+    input fabric_fpga_interrupt_in_i29;
+    input fabric_fpga_interrupt_in_i3;
+    input fabric_fpga_interrupt_in_i30;
+    input fabric_fpga_interrupt_in_i31;
+    input fabric_fpga_interrupt_in_i32;
+    input fabric_fpga_interrupt_in_i33;
+    input fabric_fpga_interrupt_in_i34;
+    input fabric_fpga_interrupt_in_i35;
+    input fabric_fpga_interrupt_in_i36;
+    input fabric_fpga_interrupt_in_i37;
+    input fabric_fpga_interrupt_in_i38;
+    input fabric_fpga_interrupt_in_i39;
+    input fabric_fpga_interrupt_in_i4;
+    input fabric_fpga_interrupt_in_i40;
+    input fabric_fpga_interrupt_in_i41;
+    input fabric_fpga_interrupt_in_i42;
+    input fabric_fpga_interrupt_in_i43;
+    input fabric_fpga_interrupt_in_i44;
+    input fabric_fpga_interrupt_in_i45;
+    input fabric_fpga_interrupt_in_i46;
+    input fabric_fpga_interrupt_in_i47;
+    input fabric_fpga_interrupt_in_i48;
+    input fabric_fpga_interrupt_in_i49;
+    input fabric_fpga_interrupt_in_i5;
+    input fabric_fpga_interrupt_in_i50;
+    input fabric_fpga_interrupt_in_i51;
+    input fabric_fpga_interrupt_in_i52;
+    input fabric_fpga_interrupt_in_i53;
+    input fabric_fpga_interrupt_in_i54;
+    input fabric_fpga_interrupt_in_i55;
+    input fabric_fpga_interrupt_in_i56;
+    input fabric_fpga_interrupt_in_i57;
+    input fabric_fpga_interrupt_in_i58;
+    input fabric_fpga_interrupt_in_i59;
+    input fabric_fpga_interrupt_in_i6;
+    input fabric_fpga_interrupt_in_i60;
+    input fabric_fpga_interrupt_in_i61;
+    input fabric_fpga_interrupt_in_i62;
+    input fabric_fpga_interrupt_in_i63;
+    input fabric_fpga_interrupt_in_i64;
+    input fabric_fpga_interrupt_in_i65;
+    input fabric_fpga_interrupt_in_i66;
+    input fabric_fpga_interrupt_in_i67;
+    input fabric_fpga_interrupt_in_i68;
+    input fabric_fpga_interrupt_in_i69;
+    input fabric_fpga_interrupt_in_i7;
+    input fabric_fpga_interrupt_in_i70;
+    input fabric_fpga_interrupt_in_i71;
+    input fabric_fpga_interrupt_in_i72;
+    input fabric_fpga_interrupt_in_i73;
+    input fabric_fpga_interrupt_in_i74;
+    input fabric_fpga_interrupt_in_i75;
+    input fabric_fpga_interrupt_in_i76;
+    input fabric_fpga_interrupt_in_i77;
+    input fabric_fpga_interrupt_in_i78;
+    input fabric_fpga_interrupt_in_i79;
+    input fabric_fpga_interrupt_in_i8;
+    input fabric_fpga_interrupt_in_i80;
+    input fabric_fpga_interrupt_in_i81;
+    input fabric_fpga_interrupt_in_i82;
+    input fabric_fpga_interrupt_in_i83;
+    input fabric_fpga_interrupt_in_i84;
+    input fabric_fpga_interrupt_in_i85;
+    input fabric_fpga_interrupt_in_i86;
+    input fabric_fpga_interrupt_in_i87;
+    input fabric_fpga_interrupt_in_i88;
+    input fabric_fpga_interrupt_in_i89;
+    input fabric_fpga_interrupt_in_i9;
+    input fabric_fpga_interrupt_in_i90;
+    input fabric_fpga_interrupt_in_i91;
+    input fabric_fpga_interrupt_in_i92;
+    input fabric_fpga_interrupt_in_i93;
+    input fabric_fpga_interrupt_in_i94;
+    input fabric_fpga_interrupt_in_i95;
+    input fabric_fpga_interrupt_in_i96;
+    input fabric_fpga_interrupt_in_i97;
+    input fabric_fpga_interrupt_in_i98;
+    input fabric_fpga_interrupt_in_i99;
+    input fabric_fpga_nic_rstn_i1;
+    input fabric_fpga_nic_rstn_i10;
+    input fabric_fpga_nic_rstn_i2;
+    input fabric_fpga_nic_rstn_i3;
+    input fabric_fpga_nic_rstn_i4;
+    input fabric_fpga_nic_rstn_i5;
+    input fabric_fpga_nic_rstn_i6;
+    input fabric_fpga_nic_rstn_i7;
+    input fabric_fpga_nic_rstn_i8;
+    input fabric_fpga_nic_rstn_i9;
+    output fabric_fpga_paddr_apb_o1;
+    output fabric_fpga_paddr_apb_o10;
+    output fabric_fpga_paddr_apb_o11;
+    output fabric_fpga_paddr_apb_o12;
+    output fabric_fpga_paddr_apb_o13;
+    output fabric_fpga_paddr_apb_o14;
+    output fabric_fpga_paddr_apb_o15;
+    output fabric_fpga_paddr_apb_o16;
+    output fabric_fpga_paddr_apb_o17;
+    output fabric_fpga_paddr_apb_o18;
+    output fabric_fpga_paddr_apb_o19;
+    output fabric_fpga_paddr_apb_o2;
+    output fabric_fpga_paddr_apb_o20;
+    output fabric_fpga_paddr_apb_o21;
+    output fabric_fpga_paddr_apb_o22;
+    output fabric_fpga_paddr_apb_o23;
+    output fabric_fpga_paddr_apb_o24;
+    output fabric_fpga_paddr_apb_o25;
+    output fabric_fpga_paddr_apb_o26;
+    output fabric_fpga_paddr_apb_o27;
+    output fabric_fpga_paddr_apb_o28;
+    output fabric_fpga_paddr_apb_o29;
+    output fabric_fpga_paddr_apb_o3;
+    output fabric_fpga_paddr_apb_o30;
+    output fabric_fpga_paddr_apb_o31;
+    output fabric_fpga_paddr_apb_o32;
+    output fabric_fpga_paddr_apb_o4;
+    output fabric_fpga_paddr_apb_o5;
+    output fabric_fpga_paddr_apb_o6;
+    output fabric_fpga_paddr_apb_o7;
+    output fabric_fpga_paddr_apb_o8;
+    output fabric_fpga_paddr_apb_o9;
+    output fabric_fpga_penable_apb_o;
+    input fabric_fpga_pmrstn_i;
+    input fabric_fpga_prdata_apb_i1;
+    input fabric_fpga_prdata_apb_i10;
+    input fabric_fpga_prdata_apb_i11;
+    input fabric_fpga_prdata_apb_i12;
+    input fabric_fpga_prdata_apb_i13;
+    input fabric_fpga_prdata_apb_i14;
+    input fabric_fpga_prdata_apb_i15;
+    input fabric_fpga_prdata_apb_i16;
+    input fabric_fpga_prdata_apb_i17;
+    input fabric_fpga_prdata_apb_i18;
+    input fabric_fpga_prdata_apb_i19;
+    input fabric_fpga_prdata_apb_i2;
+    input fabric_fpga_prdata_apb_i20;
+    input fabric_fpga_prdata_apb_i21;
+    input fabric_fpga_prdata_apb_i22;
+    input fabric_fpga_prdata_apb_i23;
+    input fabric_fpga_prdata_apb_i24;
+    input fabric_fpga_prdata_apb_i25;
+    input fabric_fpga_prdata_apb_i26;
+    input fabric_fpga_prdata_apb_i27;
+    input fabric_fpga_prdata_apb_i28;
+    input fabric_fpga_prdata_apb_i29;
+    input fabric_fpga_prdata_apb_i3;
+    input fabric_fpga_prdata_apb_i30;
+    input fabric_fpga_prdata_apb_i31;
+    input fabric_fpga_prdata_apb_i32;
+    input fabric_fpga_prdata_apb_i4;
+    input fabric_fpga_prdata_apb_i5;
+    input fabric_fpga_prdata_apb_i6;
+    input fabric_fpga_prdata_apb_i7;
+    input fabric_fpga_prdata_apb_i8;
+    input fabric_fpga_prdata_apb_i9;
+    input fabric_fpga_pready_apb_i;
+    output fabric_fpga_psel_apb_o;
+    input fabric_fpga_pslverr_apb_i;
+    output fabric_fpga_pwdata_apb_o1;
+    output fabric_fpga_pwdata_apb_o10;
+    output fabric_fpga_pwdata_apb_o11;
+    output fabric_fpga_pwdata_apb_o12;
+    output fabric_fpga_pwdata_apb_o13;
+    output fabric_fpga_pwdata_apb_o14;
+    output fabric_fpga_pwdata_apb_o15;
+    output fabric_fpga_pwdata_apb_o16;
+    output fabric_fpga_pwdata_apb_o17;
+    output fabric_fpga_pwdata_apb_o18;
+    output fabric_fpga_pwdata_apb_o19;
+    output fabric_fpga_pwdata_apb_o2;
+    output fabric_fpga_pwdata_apb_o20;
+    output fabric_fpga_pwdata_apb_o21;
+    output fabric_fpga_pwdata_apb_o22;
+    output fabric_fpga_pwdata_apb_o23;
+    output fabric_fpga_pwdata_apb_o24;
+    output fabric_fpga_pwdata_apb_o25;
+    output fabric_fpga_pwdata_apb_o26;
+    output fabric_fpga_pwdata_apb_o27;
+    output fabric_fpga_pwdata_apb_o28;
+    output fabric_fpga_pwdata_apb_o29;
+    output fabric_fpga_pwdata_apb_o3;
+    output fabric_fpga_pwdata_apb_o30;
+    output fabric_fpga_pwdata_apb_o31;
+    output fabric_fpga_pwdata_apb_o32;
+    output fabric_fpga_pwdata_apb_o4;
+    output fabric_fpga_pwdata_apb_o5;
+    output fabric_fpga_pwdata_apb_o6;
+    output fabric_fpga_pwdata_apb_o7;
+    output fabric_fpga_pwdata_apb_o8;
+    output fabric_fpga_pwdata_apb_o9;
+    output fabric_fpga_pwrite_apb_o;
+    output fabric_fpga_rdata_axi_m1_o1;
+    output fabric_fpga_rdata_axi_m1_o10;
+    output fabric_fpga_rdata_axi_m1_o100;
+    output fabric_fpga_rdata_axi_m1_o101;
+    output fabric_fpga_rdata_axi_m1_o102;
+    output fabric_fpga_rdata_axi_m1_o103;
+    output fabric_fpga_rdata_axi_m1_o104;
+    output fabric_fpga_rdata_axi_m1_o105;
+    output fabric_fpga_rdata_axi_m1_o106;
+    output fabric_fpga_rdata_axi_m1_o107;
+    output fabric_fpga_rdata_axi_m1_o108;
+    output fabric_fpga_rdata_axi_m1_o109;
+    output fabric_fpga_rdata_axi_m1_o11;
+    output fabric_fpga_rdata_axi_m1_o110;
+    output fabric_fpga_rdata_axi_m1_o111;
+    output fabric_fpga_rdata_axi_m1_o112;
+    output fabric_fpga_rdata_axi_m1_o113;
+    output fabric_fpga_rdata_axi_m1_o114;
+    output fabric_fpga_rdata_axi_m1_o115;
+    output fabric_fpga_rdata_axi_m1_o116;
+    output fabric_fpga_rdata_axi_m1_o117;
+    output fabric_fpga_rdata_axi_m1_o118;
+    output fabric_fpga_rdata_axi_m1_o119;
+    output fabric_fpga_rdata_axi_m1_o12;
+    output fabric_fpga_rdata_axi_m1_o120;
+    output fabric_fpga_rdata_axi_m1_o121;
+    output fabric_fpga_rdata_axi_m1_o122;
+    output fabric_fpga_rdata_axi_m1_o123;
+    output fabric_fpga_rdata_axi_m1_o124;
+    output fabric_fpga_rdata_axi_m1_o125;
+    output fabric_fpga_rdata_axi_m1_o126;
+    output fabric_fpga_rdata_axi_m1_o127;
+    output fabric_fpga_rdata_axi_m1_o128;
+    output fabric_fpga_rdata_axi_m1_o13;
+    output fabric_fpga_rdata_axi_m1_o14;
+    output fabric_fpga_rdata_axi_m1_o15;
+    output fabric_fpga_rdata_axi_m1_o16;
+    output fabric_fpga_rdata_axi_m1_o17;
+    output fabric_fpga_rdata_axi_m1_o18;
+    output fabric_fpga_rdata_axi_m1_o19;
+    output fabric_fpga_rdata_axi_m1_o2;
+    output fabric_fpga_rdata_axi_m1_o20;
+    output fabric_fpga_rdata_axi_m1_o21;
+    output fabric_fpga_rdata_axi_m1_o22;
+    output fabric_fpga_rdata_axi_m1_o23;
+    output fabric_fpga_rdata_axi_m1_o24;
+    output fabric_fpga_rdata_axi_m1_o25;
+    output fabric_fpga_rdata_axi_m1_o26;
+    output fabric_fpga_rdata_axi_m1_o27;
+    output fabric_fpga_rdata_axi_m1_o28;
+    output fabric_fpga_rdata_axi_m1_o29;
+    output fabric_fpga_rdata_axi_m1_o3;
+    output fabric_fpga_rdata_axi_m1_o30;
+    output fabric_fpga_rdata_axi_m1_o31;
+    output fabric_fpga_rdata_axi_m1_o32;
+    output fabric_fpga_rdata_axi_m1_o33;
+    output fabric_fpga_rdata_axi_m1_o34;
+    output fabric_fpga_rdata_axi_m1_o35;
+    output fabric_fpga_rdata_axi_m1_o36;
+    output fabric_fpga_rdata_axi_m1_o37;
+    output fabric_fpga_rdata_axi_m1_o38;
+    output fabric_fpga_rdata_axi_m1_o39;
+    output fabric_fpga_rdata_axi_m1_o4;
+    output fabric_fpga_rdata_axi_m1_o40;
+    output fabric_fpga_rdata_axi_m1_o41;
+    output fabric_fpga_rdata_axi_m1_o42;
+    output fabric_fpga_rdata_axi_m1_o43;
+    output fabric_fpga_rdata_axi_m1_o44;
+    output fabric_fpga_rdata_axi_m1_o45;
+    output fabric_fpga_rdata_axi_m1_o46;
+    output fabric_fpga_rdata_axi_m1_o47;
+    output fabric_fpga_rdata_axi_m1_o48;
+    output fabric_fpga_rdata_axi_m1_o49;
+    output fabric_fpga_rdata_axi_m1_o5;
+    output fabric_fpga_rdata_axi_m1_o50;
+    output fabric_fpga_rdata_axi_m1_o51;
+    output fabric_fpga_rdata_axi_m1_o52;
+    output fabric_fpga_rdata_axi_m1_o53;
+    output fabric_fpga_rdata_axi_m1_o54;
+    output fabric_fpga_rdata_axi_m1_o55;
+    output fabric_fpga_rdata_axi_m1_o56;
+    output fabric_fpga_rdata_axi_m1_o57;
+    output fabric_fpga_rdata_axi_m1_o58;
+    output fabric_fpga_rdata_axi_m1_o59;
+    output fabric_fpga_rdata_axi_m1_o6;
+    output fabric_fpga_rdata_axi_m1_o60;
+    output fabric_fpga_rdata_axi_m1_o61;
+    output fabric_fpga_rdata_axi_m1_o62;
+    output fabric_fpga_rdata_axi_m1_o63;
+    output fabric_fpga_rdata_axi_m1_o64;
+    output fabric_fpga_rdata_axi_m1_o65;
+    output fabric_fpga_rdata_axi_m1_o66;
+    output fabric_fpga_rdata_axi_m1_o67;
+    output fabric_fpga_rdata_axi_m1_o68;
+    output fabric_fpga_rdata_axi_m1_o69;
+    output fabric_fpga_rdata_axi_m1_o7;
+    output fabric_fpga_rdata_axi_m1_o70;
+    output fabric_fpga_rdata_axi_m1_o71;
+    output fabric_fpga_rdata_axi_m1_o72;
+    output fabric_fpga_rdata_axi_m1_o73;
+    output fabric_fpga_rdata_axi_m1_o74;
+    output fabric_fpga_rdata_axi_m1_o75;
+    output fabric_fpga_rdata_axi_m1_o76;
+    output fabric_fpga_rdata_axi_m1_o77;
+    output fabric_fpga_rdata_axi_m1_o78;
+    output fabric_fpga_rdata_axi_m1_o79;
+    output fabric_fpga_rdata_axi_m1_o8;
+    output fabric_fpga_rdata_axi_m1_o80;
+    output fabric_fpga_rdata_axi_m1_o81;
+    output fabric_fpga_rdata_axi_m1_o82;
+    output fabric_fpga_rdata_axi_m1_o83;
+    output fabric_fpga_rdata_axi_m1_o84;
+    output fabric_fpga_rdata_axi_m1_o85;
+    output fabric_fpga_rdata_axi_m1_o86;
+    output fabric_fpga_rdata_axi_m1_o87;
+    output fabric_fpga_rdata_axi_m1_o88;
+    output fabric_fpga_rdata_axi_m1_o89;
+    output fabric_fpga_rdata_axi_m1_o9;
+    output fabric_fpga_rdata_axi_m1_o90;
+    output fabric_fpga_rdata_axi_m1_o91;
+    output fabric_fpga_rdata_axi_m1_o92;
+    output fabric_fpga_rdata_axi_m1_o93;
+    output fabric_fpga_rdata_axi_m1_o94;
+    output fabric_fpga_rdata_axi_m1_o95;
+    output fabric_fpga_rdata_axi_m1_o96;
+    output fabric_fpga_rdata_axi_m1_o97;
+    output fabric_fpga_rdata_axi_m1_o98;
+    output fabric_fpga_rdata_axi_m1_o99;
+    output fabric_fpga_rdata_axi_m2_o1;
+    output fabric_fpga_rdata_axi_m2_o10;
+    output fabric_fpga_rdata_axi_m2_o100;
+    output fabric_fpga_rdata_axi_m2_o101;
+    output fabric_fpga_rdata_axi_m2_o102;
+    output fabric_fpga_rdata_axi_m2_o103;
+    output fabric_fpga_rdata_axi_m2_o104;
+    output fabric_fpga_rdata_axi_m2_o105;
+    output fabric_fpga_rdata_axi_m2_o106;
+    output fabric_fpga_rdata_axi_m2_o107;
+    output fabric_fpga_rdata_axi_m2_o108;
+    output fabric_fpga_rdata_axi_m2_o109;
+    output fabric_fpga_rdata_axi_m2_o11;
+    output fabric_fpga_rdata_axi_m2_o110;
+    output fabric_fpga_rdata_axi_m2_o111;
+    output fabric_fpga_rdata_axi_m2_o112;
+    output fabric_fpga_rdata_axi_m2_o113;
+    output fabric_fpga_rdata_axi_m2_o114;
+    output fabric_fpga_rdata_axi_m2_o115;
+    output fabric_fpga_rdata_axi_m2_o116;
+    output fabric_fpga_rdata_axi_m2_o117;
+    output fabric_fpga_rdata_axi_m2_o118;
+    output fabric_fpga_rdata_axi_m2_o119;
+    output fabric_fpga_rdata_axi_m2_o12;
+    output fabric_fpga_rdata_axi_m2_o120;
+    output fabric_fpga_rdata_axi_m2_o121;
+    output fabric_fpga_rdata_axi_m2_o122;
+    output fabric_fpga_rdata_axi_m2_o123;
+    output fabric_fpga_rdata_axi_m2_o124;
+    output fabric_fpga_rdata_axi_m2_o125;
+    output fabric_fpga_rdata_axi_m2_o126;
+    output fabric_fpga_rdata_axi_m2_o127;
+    output fabric_fpga_rdata_axi_m2_o128;
+    output fabric_fpga_rdata_axi_m2_o13;
+    output fabric_fpga_rdata_axi_m2_o14;
+    output fabric_fpga_rdata_axi_m2_o15;
+    output fabric_fpga_rdata_axi_m2_o16;
+    output fabric_fpga_rdata_axi_m2_o17;
+    output fabric_fpga_rdata_axi_m2_o18;
+    output fabric_fpga_rdata_axi_m2_o19;
+    output fabric_fpga_rdata_axi_m2_o2;
+    output fabric_fpga_rdata_axi_m2_o20;
+    output fabric_fpga_rdata_axi_m2_o21;
+    output fabric_fpga_rdata_axi_m2_o22;
+    output fabric_fpga_rdata_axi_m2_o23;
+    output fabric_fpga_rdata_axi_m2_o24;
+    output fabric_fpga_rdata_axi_m2_o25;
+    output fabric_fpga_rdata_axi_m2_o26;
+    output fabric_fpga_rdata_axi_m2_o27;
+    output fabric_fpga_rdata_axi_m2_o28;
+    output fabric_fpga_rdata_axi_m2_o29;
+    output fabric_fpga_rdata_axi_m2_o3;
+    output fabric_fpga_rdata_axi_m2_o30;
+    output fabric_fpga_rdata_axi_m2_o31;
+    output fabric_fpga_rdata_axi_m2_o32;
+    output fabric_fpga_rdata_axi_m2_o33;
+    output fabric_fpga_rdata_axi_m2_o34;
+    output fabric_fpga_rdata_axi_m2_o35;
+    output fabric_fpga_rdata_axi_m2_o36;
+    output fabric_fpga_rdata_axi_m2_o37;
+    output fabric_fpga_rdata_axi_m2_o38;
+    output fabric_fpga_rdata_axi_m2_o39;
+    output fabric_fpga_rdata_axi_m2_o4;
+    output fabric_fpga_rdata_axi_m2_o40;
+    output fabric_fpga_rdata_axi_m2_o41;
+    output fabric_fpga_rdata_axi_m2_o42;
+    output fabric_fpga_rdata_axi_m2_o43;
+    output fabric_fpga_rdata_axi_m2_o44;
+    output fabric_fpga_rdata_axi_m2_o45;
+    output fabric_fpga_rdata_axi_m2_o46;
+    output fabric_fpga_rdata_axi_m2_o47;
+    output fabric_fpga_rdata_axi_m2_o48;
+    output fabric_fpga_rdata_axi_m2_o49;
+    output fabric_fpga_rdata_axi_m2_o5;
+    output fabric_fpga_rdata_axi_m2_o50;
+    output fabric_fpga_rdata_axi_m2_o51;
+    output fabric_fpga_rdata_axi_m2_o52;
+    output fabric_fpga_rdata_axi_m2_o53;
+    output fabric_fpga_rdata_axi_m2_o54;
+    output fabric_fpga_rdata_axi_m2_o55;
+    output fabric_fpga_rdata_axi_m2_o56;
+    output fabric_fpga_rdata_axi_m2_o57;
+    output fabric_fpga_rdata_axi_m2_o58;
+    output fabric_fpga_rdata_axi_m2_o59;
+    output fabric_fpga_rdata_axi_m2_o6;
+    output fabric_fpga_rdata_axi_m2_o60;
+    output fabric_fpga_rdata_axi_m2_o61;
+    output fabric_fpga_rdata_axi_m2_o62;
+    output fabric_fpga_rdata_axi_m2_o63;
+    output fabric_fpga_rdata_axi_m2_o64;
+    output fabric_fpga_rdata_axi_m2_o65;
+    output fabric_fpga_rdata_axi_m2_o66;
+    output fabric_fpga_rdata_axi_m2_o67;
+    output fabric_fpga_rdata_axi_m2_o68;
+    output fabric_fpga_rdata_axi_m2_o69;
+    output fabric_fpga_rdata_axi_m2_o7;
+    output fabric_fpga_rdata_axi_m2_o70;
+    output fabric_fpga_rdata_axi_m2_o71;
+    output fabric_fpga_rdata_axi_m2_o72;
+    output fabric_fpga_rdata_axi_m2_o73;
+    output fabric_fpga_rdata_axi_m2_o74;
+    output fabric_fpga_rdata_axi_m2_o75;
+    output fabric_fpga_rdata_axi_m2_o76;
+    output fabric_fpga_rdata_axi_m2_o77;
+    output fabric_fpga_rdata_axi_m2_o78;
+    output fabric_fpga_rdata_axi_m2_o79;
+    output fabric_fpga_rdata_axi_m2_o8;
+    output fabric_fpga_rdata_axi_m2_o80;
+    output fabric_fpga_rdata_axi_m2_o81;
+    output fabric_fpga_rdata_axi_m2_o82;
+    output fabric_fpga_rdata_axi_m2_o83;
+    output fabric_fpga_rdata_axi_m2_o84;
+    output fabric_fpga_rdata_axi_m2_o85;
+    output fabric_fpga_rdata_axi_m2_o86;
+    output fabric_fpga_rdata_axi_m2_o87;
+    output fabric_fpga_rdata_axi_m2_o88;
+    output fabric_fpga_rdata_axi_m2_o89;
+    output fabric_fpga_rdata_axi_m2_o9;
+    output fabric_fpga_rdata_axi_m2_o90;
+    output fabric_fpga_rdata_axi_m2_o91;
+    output fabric_fpga_rdata_axi_m2_o92;
+    output fabric_fpga_rdata_axi_m2_o93;
+    output fabric_fpga_rdata_axi_m2_o94;
+    output fabric_fpga_rdata_axi_m2_o95;
+    output fabric_fpga_rdata_axi_m2_o96;
+    output fabric_fpga_rdata_axi_m2_o97;
+    output fabric_fpga_rdata_axi_m2_o98;
+    output fabric_fpga_rdata_axi_m2_o99;
+    input fabric_fpga_rdata_axi_s1_i1;
+    input fabric_fpga_rdata_axi_s1_i10;
+    input fabric_fpga_rdata_axi_s1_i100;
+    input fabric_fpga_rdata_axi_s1_i101;
+    input fabric_fpga_rdata_axi_s1_i102;
+    input fabric_fpga_rdata_axi_s1_i103;
+    input fabric_fpga_rdata_axi_s1_i104;
+    input fabric_fpga_rdata_axi_s1_i105;
+    input fabric_fpga_rdata_axi_s1_i106;
+    input fabric_fpga_rdata_axi_s1_i107;
+    input fabric_fpga_rdata_axi_s1_i108;
+    input fabric_fpga_rdata_axi_s1_i109;
+    input fabric_fpga_rdata_axi_s1_i11;
+    input fabric_fpga_rdata_axi_s1_i110;
+    input fabric_fpga_rdata_axi_s1_i111;
+    input fabric_fpga_rdata_axi_s1_i112;
+    input fabric_fpga_rdata_axi_s1_i113;
+    input fabric_fpga_rdata_axi_s1_i114;
+    input fabric_fpga_rdata_axi_s1_i115;
+    input fabric_fpga_rdata_axi_s1_i116;
+    input fabric_fpga_rdata_axi_s1_i117;
+    input fabric_fpga_rdata_axi_s1_i118;
+    input fabric_fpga_rdata_axi_s1_i119;
+    input fabric_fpga_rdata_axi_s1_i12;
+    input fabric_fpga_rdata_axi_s1_i120;
+    input fabric_fpga_rdata_axi_s1_i121;
+    input fabric_fpga_rdata_axi_s1_i122;
+    input fabric_fpga_rdata_axi_s1_i123;
+    input fabric_fpga_rdata_axi_s1_i124;
+    input fabric_fpga_rdata_axi_s1_i125;
+    input fabric_fpga_rdata_axi_s1_i126;
+    input fabric_fpga_rdata_axi_s1_i127;
+    input fabric_fpga_rdata_axi_s1_i128;
+    input fabric_fpga_rdata_axi_s1_i13;
+    input fabric_fpga_rdata_axi_s1_i14;
+    input fabric_fpga_rdata_axi_s1_i15;
+    input fabric_fpga_rdata_axi_s1_i16;
+    input fabric_fpga_rdata_axi_s1_i17;
+    input fabric_fpga_rdata_axi_s1_i18;
+    input fabric_fpga_rdata_axi_s1_i19;
+    input fabric_fpga_rdata_axi_s1_i2;
+    input fabric_fpga_rdata_axi_s1_i20;
+    input fabric_fpga_rdata_axi_s1_i21;
+    input fabric_fpga_rdata_axi_s1_i22;
+    input fabric_fpga_rdata_axi_s1_i23;
+    input fabric_fpga_rdata_axi_s1_i24;
+    input fabric_fpga_rdata_axi_s1_i25;
+    input fabric_fpga_rdata_axi_s1_i26;
+    input fabric_fpga_rdata_axi_s1_i27;
+    input fabric_fpga_rdata_axi_s1_i28;
+    input fabric_fpga_rdata_axi_s1_i29;
+    input fabric_fpga_rdata_axi_s1_i3;
+    input fabric_fpga_rdata_axi_s1_i30;
+    input fabric_fpga_rdata_axi_s1_i31;
+    input fabric_fpga_rdata_axi_s1_i32;
+    input fabric_fpga_rdata_axi_s1_i33;
+    input fabric_fpga_rdata_axi_s1_i34;
+    input fabric_fpga_rdata_axi_s1_i35;
+    input fabric_fpga_rdata_axi_s1_i36;
+    input fabric_fpga_rdata_axi_s1_i37;
+    input fabric_fpga_rdata_axi_s1_i38;
+    input fabric_fpga_rdata_axi_s1_i39;
+    input fabric_fpga_rdata_axi_s1_i4;
+    input fabric_fpga_rdata_axi_s1_i40;
+    input fabric_fpga_rdata_axi_s1_i41;
+    input fabric_fpga_rdata_axi_s1_i42;
+    input fabric_fpga_rdata_axi_s1_i43;
+    input fabric_fpga_rdata_axi_s1_i44;
+    input fabric_fpga_rdata_axi_s1_i45;
+    input fabric_fpga_rdata_axi_s1_i46;
+    input fabric_fpga_rdata_axi_s1_i47;
+    input fabric_fpga_rdata_axi_s1_i48;
+    input fabric_fpga_rdata_axi_s1_i49;
+    input fabric_fpga_rdata_axi_s1_i5;
+    input fabric_fpga_rdata_axi_s1_i50;
+    input fabric_fpga_rdata_axi_s1_i51;
+    input fabric_fpga_rdata_axi_s1_i52;
+    input fabric_fpga_rdata_axi_s1_i53;
+    input fabric_fpga_rdata_axi_s1_i54;
+    input fabric_fpga_rdata_axi_s1_i55;
+    input fabric_fpga_rdata_axi_s1_i56;
+    input fabric_fpga_rdata_axi_s1_i57;
+    input fabric_fpga_rdata_axi_s1_i58;
+    input fabric_fpga_rdata_axi_s1_i59;
+    input fabric_fpga_rdata_axi_s1_i6;
+    input fabric_fpga_rdata_axi_s1_i60;
+    input fabric_fpga_rdata_axi_s1_i61;
+    input fabric_fpga_rdata_axi_s1_i62;
+    input fabric_fpga_rdata_axi_s1_i63;
+    input fabric_fpga_rdata_axi_s1_i64;
+    input fabric_fpga_rdata_axi_s1_i65;
+    input fabric_fpga_rdata_axi_s1_i66;
+    input fabric_fpga_rdata_axi_s1_i67;
+    input fabric_fpga_rdata_axi_s1_i68;
+    input fabric_fpga_rdata_axi_s1_i69;
+    input fabric_fpga_rdata_axi_s1_i7;
+    input fabric_fpga_rdata_axi_s1_i70;
+    input fabric_fpga_rdata_axi_s1_i71;
+    input fabric_fpga_rdata_axi_s1_i72;
+    input fabric_fpga_rdata_axi_s1_i73;
+    input fabric_fpga_rdata_axi_s1_i74;
+    input fabric_fpga_rdata_axi_s1_i75;
+    input fabric_fpga_rdata_axi_s1_i76;
+    input fabric_fpga_rdata_axi_s1_i77;
+    input fabric_fpga_rdata_axi_s1_i78;
+    input fabric_fpga_rdata_axi_s1_i79;
+    input fabric_fpga_rdata_axi_s1_i8;
+    input fabric_fpga_rdata_axi_s1_i80;
+    input fabric_fpga_rdata_axi_s1_i81;
+    input fabric_fpga_rdata_axi_s1_i82;
+    input fabric_fpga_rdata_axi_s1_i83;
+    input fabric_fpga_rdata_axi_s1_i84;
+    input fabric_fpga_rdata_axi_s1_i85;
+    input fabric_fpga_rdata_axi_s1_i86;
+    input fabric_fpga_rdata_axi_s1_i87;
+    input fabric_fpga_rdata_axi_s1_i88;
+    input fabric_fpga_rdata_axi_s1_i89;
+    input fabric_fpga_rdata_axi_s1_i9;
+    input fabric_fpga_rdata_axi_s1_i90;
+    input fabric_fpga_rdata_axi_s1_i91;
+    input fabric_fpga_rdata_axi_s1_i92;
+    input fabric_fpga_rdata_axi_s1_i93;
+    input fabric_fpga_rdata_axi_s1_i94;
+    input fabric_fpga_rdata_axi_s1_i95;
+    input fabric_fpga_rdata_axi_s1_i96;
+    input fabric_fpga_rdata_axi_s1_i97;
+    input fabric_fpga_rdata_axi_s1_i98;
+    input fabric_fpga_rdata_axi_s1_i99;
+    input fabric_fpga_rdata_axi_s2_i1;
+    input fabric_fpga_rdata_axi_s2_i10;
+    input fabric_fpga_rdata_axi_s2_i100;
+    input fabric_fpga_rdata_axi_s2_i101;
+    input fabric_fpga_rdata_axi_s2_i102;
+    input fabric_fpga_rdata_axi_s2_i103;
+    input fabric_fpga_rdata_axi_s2_i104;
+    input fabric_fpga_rdata_axi_s2_i105;
+    input fabric_fpga_rdata_axi_s2_i106;
+    input fabric_fpga_rdata_axi_s2_i107;
+    input fabric_fpga_rdata_axi_s2_i108;
+    input fabric_fpga_rdata_axi_s2_i109;
+    input fabric_fpga_rdata_axi_s2_i11;
+    input fabric_fpga_rdata_axi_s2_i110;
+    input fabric_fpga_rdata_axi_s2_i111;
+    input fabric_fpga_rdata_axi_s2_i112;
+    input fabric_fpga_rdata_axi_s2_i113;
+    input fabric_fpga_rdata_axi_s2_i114;
+    input fabric_fpga_rdata_axi_s2_i115;
+    input fabric_fpga_rdata_axi_s2_i116;
+    input fabric_fpga_rdata_axi_s2_i117;
+    input fabric_fpga_rdata_axi_s2_i118;
+    input fabric_fpga_rdata_axi_s2_i119;
+    input fabric_fpga_rdata_axi_s2_i12;
+    input fabric_fpga_rdata_axi_s2_i120;
+    input fabric_fpga_rdata_axi_s2_i121;
+    input fabric_fpga_rdata_axi_s2_i122;
+    input fabric_fpga_rdata_axi_s2_i123;
+    input fabric_fpga_rdata_axi_s2_i124;
+    input fabric_fpga_rdata_axi_s2_i125;
+    input fabric_fpga_rdata_axi_s2_i126;
+    input fabric_fpga_rdata_axi_s2_i127;
+    input fabric_fpga_rdata_axi_s2_i128;
+    input fabric_fpga_rdata_axi_s2_i13;
+    input fabric_fpga_rdata_axi_s2_i14;
+    input fabric_fpga_rdata_axi_s2_i15;
+    input fabric_fpga_rdata_axi_s2_i16;
+    input fabric_fpga_rdata_axi_s2_i17;
+    input fabric_fpga_rdata_axi_s2_i18;
+    input fabric_fpga_rdata_axi_s2_i19;
+    input fabric_fpga_rdata_axi_s2_i2;
+    input fabric_fpga_rdata_axi_s2_i20;
+    input fabric_fpga_rdata_axi_s2_i21;
+    input fabric_fpga_rdata_axi_s2_i22;
+    input fabric_fpga_rdata_axi_s2_i23;
+    input fabric_fpga_rdata_axi_s2_i24;
+    input fabric_fpga_rdata_axi_s2_i25;
+    input fabric_fpga_rdata_axi_s2_i26;
+    input fabric_fpga_rdata_axi_s2_i27;
+    input fabric_fpga_rdata_axi_s2_i28;
+    input fabric_fpga_rdata_axi_s2_i29;
+    input fabric_fpga_rdata_axi_s2_i3;
+    input fabric_fpga_rdata_axi_s2_i30;
+    input fabric_fpga_rdata_axi_s2_i31;
+    input fabric_fpga_rdata_axi_s2_i32;
+    input fabric_fpga_rdata_axi_s2_i33;
+    input fabric_fpga_rdata_axi_s2_i34;
+    input fabric_fpga_rdata_axi_s2_i35;
+    input fabric_fpga_rdata_axi_s2_i36;
+    input fabric_fpga_rdata_axi_s2_i37;
+    input fabric_fpga_rdata_axi_s2_i38;
+    input fabric_fpga_rdata_axi_s2_i39;
+    input fabric_fpga_rdata_axi_s2_i4;
+    input fabric_fpga_rdata_axi_s2_i40;
+    input fabric_fpga_rdata_axi_s2_i41;
+    input fabric_fpga_rdata_axi_s2_i42;
+    input fabric_fpga_rdata_axi_s2_i43;
+    input fabric_fpga_rdata_axi_s2_i44;
+    input fabric_fpga_rdata_axi_s2_i45;
+    input fabric_fpga_rdata_axi_s2_i46;
+    input fabric_fpga_rdata_axi_s2_i47;
+    input fabric_fpga_rdata_axi_s2_i48;
+    input fabric_fpga_rdata_axi_s2_i49;
+    input fabric_fpga_rdata_axi_s2_i5;
+    input fabric_fpga_rdata_axi_s2_i50;
+    input fabric_fpga_rdata_axi_s2_i51;
+    input fabric_fpga_rdata_axi_s2_i52;
+    input fabric_fpga_rdata_axi_s2_i53;
+    input fabric_fpga_rdata_axi_s2_i54;
+    input fabric_fpga_rdata_axi_s2_i55;
+    input fabric_fpga_rdata_axi_s2_i56;
+    input fabric_fpga_rdata_axi_s2_i57;
+    input fabric_fpga_rdata_axi_s2_i58;
+    input fabric_fpga_rdata_axi_s2_i59;
+    input fabric_fpga_rdata_axi_s2_i6;
+    input fabric_fpga_rdata_axi_s2_i60;
+    input fabric_fpga_rdata_axi_s2_i61;
+    input fabric_fpga_rdata_axi_s2_i62;
+    input fabric_fpga_rdata_axi_s2_i63;
+    input fabric_fpga_rdata_axi_s2_i64;
+    input fabric_fpga_rdata_axi_s2_i65;
+    input fabric_fpga_rdata_axi_s2_i66;
+    input fabric_fpga_rdata_axi_s2_i67;
+    input fabric_fpga_rdata_axi_s2_i68;
+    input fabric_fpga_rdata_axi_s2_i69;
+    input fabric_fpga_rdata_axi_s2_i7;
+    input fabric_fpga_rdata_axi_s2_i70;
+    input fabric_fpga_rdata_axi_s2_i71;
+    input fabric_fpga_rdata_axi_s2_i72;
+    input fabric_fpga_rdata_axi_s2_i73;
+    input fabric_fpga_rdata_axi_s2_i74;
+    input fabric_fpga_rdata_axi_s2_i75;
+    input fabric_fpga_rdata_axi_s2_i76;
+    input fabric_fpga_rdata_axi_s2_i77;
+    input fabric_fpga_rdata_axi_s2_i78;
+    input fabric_fpga_rdata_axi_s2_i79;
+    input fabric_fpga_rdata_axi_s2_i8;
+    input fabric_fpga_rdata_axi_s2_i80;
+    input fabric_fpga_rdata_axi_s2_i81;
+    input fabric_fpga_rdata_axi_s2_i82;
+    input fabric_fpga_rdata_axi_s2_i83;
+    input fabric_fpga_rdata_axi_s2_i84;
+    input fabric_fpga_rdata_axi_s2_i85;
+    input fabric_fpga_rdata_axi_s2_i86;
+    input fabric_fpga_rdata_axi_s2_i87;
+    input fabric_fpga_rdata_axi_s2_i88;
+    input fabric_fpga_rdata_axi_s2_i89;
+    input fabric_fpga_rdata_axi_s2_i9;
+    input fabric_fpga_rdata_axi_s2_i90;
+    input fabric_fpga_rdata_axi_s2_i91;
+    input fabric_fpga_rdata_axi_s2_i92;
+    input fabric_fpga_rdata_axi_s2_i93;
+    input fabric_fpga_rdata_axi_s2_i94;
+    input fabric_fpga_rdata_axi_s2_i95;
+    input fabric_fpga_rdata_axi_s2_i96;
+    input fabric_fpga_rdata_axi_s2_i97;
+    input fabric_fpga_rdata_axi_s2_i98;
+    input fabric_fpga_rdata_axi_s2_i99;
+    output fabric_fpga_rid_axi_m1_o1;
+    output fabric_fpga_rid_axi_m1_o2;
+    output fabric_fpga_rid_axi_m1_o3;
+    output fabric_fpga_rid_axi_m1_o4;
+    output fabric_fpga_rid_axi_m1_o5;
+    output fabric_fpga_rid_axi_m2_o1;
+    output fabric_fpga_rid_axi_m2_o2;
+    output fabric_fpga_rid_axi_m2_o3;
+    output fabric_fpga_rid_axi_m2_o4;
+    output fabric_fpga_rid_axi_m2_o5;
+    input fabric_fpga_rid_axi_s1_i1;
+    input fabric_fpga_rid_axi_s1_i10;
+    input fabric_fpga_rid_axi_s1_i11;
+    input fabric_fpga_rid_axi_s1_i12;
+    input fabric_fpga_rid_axi_s1_i2;
+    input fabric_fpga_rid_axi_s1_i3;
+    input fabric_fpga_rid_axi_s1_i4;
+    input fabric_fpga_rid_axi_s1_i5;
+    input fabric_fpga_rid_axi_s1_i6;
+    input fabric_fpga_rid_axi_s1_i7;
+    input fabric_fpga_rid_axi_s1_i8;
+    input fabric_fpga_rid_axi_s1_i9;
+    input fabric_fpga_rid_axi_s2_i1;
+    input fabric_fpga_rid_axi_s2_i10;
+    input fabric_fpga_rid_axi_s2_i11;
+    input fabric_fpga_rid_axi_s2_i12;
+    input fabric_fpga_rid_axi_s2_i2;
+    input fabric_fpga_rid_axi_s2_i3;
+    input fabric_fpga_rid_axi_s2_i4;
+    input fabric_fpga_rid_axi_s2_i5;
+    input fabric_fpga_rid_axi_s2_i6;
+    input fabric_fpga_rid_axi_s2_i7;
+    input fabric_fpga_rid_axi_s2_i8;
+    input fabric_fpga_rid_axi_s2_i9;
+    output fabric_fpga_rlast_axi_m1_o;
+    output fabric_fpga_rlast_axi_m2_o;
+    input fabric_fpga_rlast_axi_s1_i;
+    input fabric_fpga_rlast_axi_s2_i;
+    input fabric_fpga_rready_axi_m1_i;
+    input fabric_fpga_rready_axi_m2_i;
+    output fabric_fpga_rready_axi_s1_o;
+    output fabric_fpga_rready_axi_s2_o;
+    output fabric_fpga_rresp_axi_m1_o1;
+    output fabric_fpga_rresp_axi_m1_o2;
+    output fabric_fpga_rresp_axi_m2_o1;
+    output fabric_fpga_rresp_axi_m2_o2;
+    input fabric_fpga_rresp_axi_s1_i1;
+    input fabric_fpga_rresp_axi_s1_i2;
+    input fabric_fpga_rresp_axi_s2_i1;
+    input fabric_fpga_rresp_axi_s2_i2;
+    output fabric_fpga_rvalid_axi_m1_o;
+    output fabric_fpga_rvalid_axi_m2_o;
+    input fabric_fpga_rvalid_axi_s1_i;
+    input fabric_fpga_rvalid_axi_s2_i;
+    input fabric_fpga_sysrstn_i;
+    output fabric_fpga_trigger_in_o1;
+    output fabric_fpga_trigger_in_o2;
+    output fabric_fpga_trigger_in_o3;
+    output fabric_fpga_trigger_in_o4;
+    output fabric_fpga_trigger_in_o5;
+    output fabric_fpga_trigger_in_o6;
+    output fabric_fpga_trigger_in_o7;
+    output fabric_fpga_trigger_in_o8;
+    input fabric_fpga_trigger_out_i1;
+    input fabric_fpga_trigger_out_i2;
+    input fabric_fpga_trigger_out_i3;
+    input fabric_fpga_trigger_out_i4;
+    input fabric_fpga_trigger_out_i5;
+    input fabric_fpga_trigger_out_i6;
+    input fabric_fpga_trigger_out_i7;
+    input fabric_fpga_trigger_out_i8;
+    input fabric_fpga_wdata_axi_m1_i1;
+    input fabric_fpga_wdata_axi_m1_i10;
+    input fabric_fpga_wdata_axi_m1_i100;
+    input fabric_fpga_wdata_axi_m1_i101;
+    input fabric_fpga_wdata_axi_m1_i102;
+    input fabric_fpga_wdata_axi_m1_i103;
+    input fabric_fpga_wdata_axi_m1_i104;
+    input fabric_fpga_wdata_axi_m1_i105;
+    input fabric_fpga_wdata_axi_m1_i106;
+    input fabric_fpga_wdata_axi_m1_i107;
+    input fabric_fpga_wdata_axi_m1_i108;
+    input fabric_fpga_wdata_axi_m1_i109;
+    input fabric_fpga_wdata_axi_m1_i11;
+    input fabric_fpga_wdata_axi_m1_i110;
+    input fabric_fpga_wdata_axi_m1_i111;
+    input fabric_fpga_wdata_axi_m1_i112;
+    input fabric_fpga_wdata_axi_m1_i113;
+    input fabric_fpga_wdata_axi_m1_i114;
+    input fabric_fpga_wdata_axi_m1_i115;
+    input fabric_fpga_wdata_axi_m1_i116;
+    input fabric_fpga_wdata_axi_m1_i117;
+    input fabric_fpga_wdata_axi_m1_i118;
+    input fabric_fpga_wdata_axi_m1_i119;
+    input fabric_fpga_wdata_axi_m1_i12;
+    input fabric_fpga_wdata_axi_m1_i120;
+    input fabric_fpga_wdata_axi_m1_i121;
+    input fabric_fpga_wdata_axi_m1_i122;
+    input fabric_fpga_wdata_axi_m1_i123;
+    input fabric_fpga_wdata_axi_m1_i124;
+    input fabric_fpga_wdata_axi_m1_i125;
+    input fabric_fpga_wdata_axi_m1_i126;
+    input fabric_fpga_wdata_axi_m1_i127;
+    input fabric_fpga_wdata_axi_m1_i128;
+    input fabric_fpga_wdata_axi_m1_i13;
+    input fabric_fpga_wdata_axi_m1_i14;
+    input fabric_fpga_wdata_axi_m1_i15;
+    input fabric_fpga_wdata_axi_m1_i16;
+    input fabric_fpga_wdata_axi_m1_i17;
+    input fabric_fpga_wdata_axi_m1_i18;
+    input fabric_fpga_wdata_axi_m1_i19;
+    input fabric_fpga_wdata_axi_m1_i2;
+    input fabric_fpga_wdata_axi_m1_i20;
+    input fabric_fpga_wdata_axi_m1_i21;
+    input fabric_fpga_wdata_axi_m1_i22;
+    input fabric_fpga_wdata_axi_m1_i23;
+    input fabric_fpga_wdata_axi_m1_i24;
+    input fabric_fpga_wdata_axi_m1_i25;
+    input fabric_fpga_wdata_axi_m1_i26;
+    input fabric_fpga_wdata_axi_m1_i27;
+    input fabric_fpga_wdata_axi_m1_i28;
+    input fabric_fpga_wdata_axi_m1_i29;
+    input fabric_fpga_wdata_axi_m1_i3;
+    input fabric_fpga_wdata_axi_m1_i30;
+    input fabric_fpga_wdata_axi_m1_i31;
+    input fabric_fpga_wdata_axi_m1_i32;
+    input fabric_fpga_wdata_axi_m1_i33;
+    input fabric_fpga_wdata_axi_m1_i34;
+    input fabric_fpga_wdata_axi_m1_i35;
+    input fabric_fpga_wdata_axi_m1_i36;
+    input fabric_fpga_wdata_axi_m1_i37;
+    input fabric_fpga_wdata_axi_m1_i38;
+    input fabric_fpga_wdata_axi_m1_i39;
+    input fabric_fpga_wdata_axi_m1_i4;
+    input fabric_fpga_wdata_axi_m1_i40;
+    input fabric_fpga_wdata_axi_m1_i41;
+    input fabric_fpga_wdata_axi_m1_i42;
+    input fabric_fpga_wdata_axi_m1_i43;
+    input fabric_fpga_wdata_axi_m1_i44;
+    input fabric_fpga_wdata_axi_m1_i45;
+    input fabric_fpga_wdata_axi_m1_i46;
+    input fabric_fpga_wdata_axi_m1_i47;
+    input fabric_fpga_wdata_axi_m1_i48;
+    input fabric_fpga_wdata_axi_m1_i49;
+    input fabric_fpga_wdata_axi_m1_i5;
+    input fabric_fpga_wdata_axi_m1_i50;
+    input fabric_fpga_wdata_axi_m1_i51;
+    input fabric_fpga_wdata_axi_m1_i52;
+    input fabric_fpga_wdata_axi_m1_i53;
+    input fabric_fpga_wdata_axi_m1_i54;
+    input fabric_fpga_wdata_axi_m1_i55;
+    input fabric_fpga_wdata_axi_m1_i56;
+    input fabric_fpga_wdata_axi_m1_i57;
+    input fabric_fpga_wdata_axi_m1_i58;
+    input fabric_fpga_wdata_axi_m1_i59;
+    input fabric_fpga_wdata_axi_m1_i6;
+    input fabric_fpga_wdata_axi_m1_i60;
+    input fabric_fpga_wdata_axi_m1_i61;
+    input fabric_fpga_wdata_axi_m1_i62;
+    input fabric_fpga_wdata_axi_m1_i63;
+    input fabric_fpga_wdata_axi_m1_i64;
+    input fabric_fpga_wdata_axi_m1_i65;
+    input fabric_fpga_wdata_axi_m1_i66;
+    input fabric_fpga_wdata_axi_m1_i67;
+    input fabric_fpga_wdata_axi_m1_i68;
+    input fabric_fpga_wdata_axi_m1_i69;
+    input fabric_fpga_wdata_axi_m1_i7;
+    input fabric_fpga_wdata_axi_m1_i70;
+    input fabric_fpga_wdata_axi_m1_i71;
+    input fabric_fpga_wdata_axi_m1_i72;
+    input fabric_fpga_wdata_axi_m1_i73;
+    input fabric_fpga_wdata_axi_m1_i74;
+    input fabric_fpga_wdata_axi_m1_i75;
+    input fabric_fpga_wdata_axi_m1_i76;
+    input fabric_fpga_wdata_axi_m1_i77;
+    input fabric_fpga_wdata_axi_m1_i78;
+    input fabric_fpga_wdata_axi_m1_i79;
+    input fabric_fpga_wdata_axi_m1_i8;
+    input fabric_fpga_wdata_axi_m1_i80;
+    input fabric_fpga_wdata_axi_m1_i81;
+    input fabric_fpga_wdata_axi_m1_i82;
+    input fabric_fpga_wdata_axi_m1_i83;
+    input fabric_fpga_wdata_axi_m1_i84;
+    input fabric_fpga_wdata_axi_m1_i85;
+    input fabric_fpga_wdata_axi_m1_i86;
+    input fabric_fpga_wdata_axi_m1_i87;
+    input fabric_fpga_wdata_axi_m1_i88;
+    input fabric_fpga_wdata_axi_m1_i89;
+    input fabric_fpga_wdata_axi_m1_i9;
+    input fabric_fpga_wdata_axi_m1_i90;
+    input fabric_fpga_wdata_axi_m1_i91;
+    input fabric_fpga_wdata_axi_m1_i92;
+    input fabric_fpga_wdata_axi_m1_i93;
+    input fabric_fpga_wdata_axi_m1_i94;
+    input fabric_fpga_wdata_axi_m1_i95;
+    input fabric_fpga_wdata_axi_m1_i96;
+    input fabric_fpga_wdata_axi_m1_i97;
+    input fabric_fpga_wdata_axi_m1_i98;
+    input fabric_fpga_wdata_axi_m1_i99;
+    input fabric_fpga_wdata_axi_m2_i1;
+    input fabric_fpga_wdata_axi_m2_i10;
+    input fabric_fpga_wdata_axi_m2_i100;
+    input fabric_fpga_wdata_axi_m2_i101;
+    input fabric_fpga_wdata_axi_m2_i102;
+    input fabric_fpga_wdata_axi_m2_i103;
+    input fabric_fpga_wdata_axi_m2_i104;
+    input fabric_fpga_wdata_axi_m2_i105;
+    input fabric_fpga_wdata_axi_m2_i106;
+    input fabric_fpga_wdata_axi_m2_i107;
+    input fabric_fpga_wdata_axi_m2_i108;
+    input fabric_fpga_wdata_axi_m2_i109;
+    input fabric_fpga_wdata_axi_m2_i11;
+    input fabric_fpga_wdata_axi_m2_i110;
+    input fabric_fpga_wdata_axi_m2_i111;
+    input fabric_fpga_wdata_axi_m2_i112;
+    input fabric_fpga_wdata_axi_m2_i113;
+    input fabric_fpga_wdata_axi_m2_i114;
+    input fabric_fpga_wdata_axi_m2_i115;
+    input fabric_fpga_wdata_axi_m2_i116;
+    input fabric_fpga_wdata_axi_m2_i117;
+    input fabric_fpga_wdata_axi_m2_i118;
+    input fabric_fpga_wdata_axi_m2_i119;
+    input fabric_fpga_wdata_axi_m2_i12;
+    input fabric_fpga_wdata_axi_m2_i120;
+    input fabric_fpga_wdata_axi_m2_i121;
+    input fabric_fpga_wdata_axi_m2_i122;
+    input fabric_fpga_wdata_axi_m2_i123;
+    input fabric_fpga_wdata_axi_m2_i124;
+    input fabric_fpga_wdata_axi_m2_i125;
+    input fabric_fpga_wdata_axi_m2_i126;
+    input fabric_fpga_wdata_axi_m2_i127;
+    input fabric_fpga_wdata_axi_m2_i128;
+    input fabric_fpga_wdata_axi_m2_i13;
+    input fabric_fpga_wdata_axi_m2_i14;
+    input fabric_fpga_wdata_axi_m2_i15;
+    input fabric_fpga_wdata_axi_m2_i16;
+    input fabric_fpga_wdata_axi_m2_i17;
+    input fabric_fpga_wdata_axi_m2_i18;
+    input fabric_fpga_wdata_axi_m2_i19;
+    input fabric_fpga_wdata_axi_m2_i2;
+    input fabric_fpga_wdata_axi_m2_i20;
+    input fabric_fpga_wdata_axi_m2_i21;
+    input fabric_fpga_wdata_axi_m2_i22;
+    input fabric_fpga_wdata_axi_m2_i23;
+    input fabric_fpga_wdata_axi_m2_i24;
+    input fabric_fpga_wdata_axi_m2_i25;
+    input fabric_fpga_wdata_axi_m2_i26;
+    input fabric_fpga_wdata_axi_m2_i27;
+    input fabric_fpga_wdata_axi_m2_i28;
+    input fabric_fpga_wdata_axi_m2_i29;
+    input fabric_fpga_wdata_axi_m2_i3;
+    input fabric_fpga_wdata_axi_m2_i30;
+    input fabric_fpga_wdata_axi_m2_i31;
+    input fabric_fpga_wdata_axi_m2_i32;
+    input fabric_fpga_wdata_axi_m2_i33;
+    input fabric_fpga_wdata_axi_m2_i34;
+    input fabric_fpga_wdata_axi_m2_i35;
+    input fabric_fpga_wdata_axi_m2_i36;
+    input fabric_fpga_wdata_axi_m2_i37;
+    input fabric_fpga_wdata_axi_m2_i38;
+    input fabric_fpga_wdata_axi_m2_i39;
+    input fabric_fpga_wdata_axi_m2_i4;
+    input fabric_fpga_wdata_axi_m2_i40;
+    input fabric_fpga_wdata_axi_m2_i41;
+    input fabric_fpga_wdata_axi_m2_i42;
+    input fabric_fpga_wdata_axi_m2_i43;
+    input fabric_fpga_wdata_axi_m2_i44;
+    input fabric_fpga_wdata_axi_m2_i45;
+    input fabric_fpga_wdata_axi_m2_i46;
+    input fabric_fpga_wdata_axi_m2_i47;
+    input fabric_fpga_wdata_axi_m2_i48;
+    input fabric_fpga_wdata_axi_m2_i49;
+    input fabric_fpga_wdata_axi_m2_i5;
+    input fabric_fpga_wdata_axi_m2_i50;
+    input fabric_fpga_wdata_axi_m2_i51;
+    input fabric_fpga_wdata_axi_m2_i52;
+    input fabric_fpga_wdata_axi_m2_i53;
+    input fabric_fpga_wdata_axi_m2_i54;
+    input fabric_fpga_wdata_axi_m2_i55;
+    input fabric_fpga_wdata_axi_m2_i56;
+    input fabric_fpga_wdata_axi_m2_i57;
+    input fabric_fpga_wdata_axi_m2_i58;
+    input fabric_fpga_wdata_axi_m2_i59;
+    input fabric_fpga_wdata_axi_m2_i6;
+    input fabric_fpga_wdata_axi_m2_i60;
+    input fabric_fpga_wdata_axi_m2_i61;
+    input fabric_fpga_wdata_axi_m2_i62;
+    input fabric_fpga_wdata_axi_m2_i63;
+    input fabric_fpga_wdata_axi_m2_i64;
+    input fabric_fpga_wdata_axi_m2_i65;
+    input fabric_fpga_wdata_axi_m2_i66;
+    input fabric_fpga_wdata_axi_m2_i67;
+    input fabric_fpga_wdata_axi_m2_i68;
+    input fabric_fpga_wdata_axi_m2_i69;
+    input fabric_fpga_wdata_axi_m2_i7;
+    input fabric_fpga_wdata_axi_m2_i70;
+    input fabric_fpga_wdata_axi_m2_i71;
+    input fabric_fpga_wdata_axi_m2_i72;
+    input fabric_fpga_wdata_axi_m2_i73;
+    input fabric_fpga_wdata_axi_m2_i74;
+    input fabric_fpga_wdata_axi_m2_i75;
+    input fabric_fpga_wdata_axi_m2_i76;
+    input fabric_fpga_wdata_axi_m2_i77;
+    input fabric_fpga_wdata_axi_m2_i78;
+    input fabric_fpga_wdata_axi_m2_i79;
+    input fabric_fpga_wdata_axi_m2_i8;
+    input fabric_fpga_wdata_axi_m2_i80;
+    input fabric_fpga_wdata_axi_m2_i81;
+    input fabric_fpga_wdata_axi_m2_i82;
+    input fabric_fpga_wdata_axi_m2_i83;
+    input fabric_fpga_wdata_axi_m2_i84;
+    input fabric_fpga_wdata_axi_m2_i85;
+    input fabric_fpga_wdata_axi_m2_i86;
+    input fabric_fpga_wdata_axi_m2_i87;
+    input fabric_fpga_wdata_axi_m2_i88;
+    input fabric_fpga_wdata_axi_m2_i89;
+    input fabric_fpga_wdata_axi_m2_i9;
+    input fabric_fpga_wdata_axi_m2_i90;
+    input fabric_fpga_wdata_axi_m2_i91;
+    input fabric_fpga_wdata_axi_m2_i92;
+    input fabric_fpga_wdata_axi_m2_i93;
+    input fabric_fpga_wdata_axi_m2_i94;
+    input fabric_fpga_wdata_axi_m2_i95;
+    input fabric_fpga_wdata_axi_m2_i96;
+    input fabric_fpga_wdata_axi_m2_i97;
+    input fabric_fpga_wdata_axi_m2_i98;
+    input fabric_fpga_wdata_axi_m2_i99;
+    output fabric_fpga_wdata_axi_s1_o1;
+    output fabric_fpga_wdata_axi_s1_o10;
+    output fabric_fpga_wdata_axi_s1_o100;
+    output fabric_fpga_wdata_axi_s1_o101;
+    output fabric_fpga_wdata_axi_s1_o102;
+    output fabric_fpga_wdata_axi_s1_o103;
+    output fabric_fpga_wdata_axi_s1_o104;
+    output fabric_fpga_wdata_axi_s1_o105;
+    output fabric_fpga_wdata_axi_s1_o106;
+    output fabric_fpga_wdata_axi_s1_o107;
+    output fabric_fpga_wdata_axi_s1_o108;
+    output fabric_fpga_wdata_axi_s1_o109;
+    output fabric_fpga_wdata_axi_s1_o11;
+    output fabric_fpga_wdata_axi_s1_o110;
+    output fabric_fpga_wdata_axi_s1_o111;
+    output fabric_fpga_wdata_axi_s1_o112;
+    output fabric_fpga_wdata_axi_s1_o113;
+    output fabric_fpga_wdata_axi_s1_o114;
+    output fabric_fpga_wdata_axi_s1_o115;
+    output fabric_fpga_wdata_axi_s1_o116;
+    output fabric_fpga_wdata_axi_s1_o117;
+    output fabric_fpga_wdata_axi_s1_o118;
+    output fabric_fpga_wdata_axi_s1_o119;
+    output fabric_fpga_wdata_axi_s1_o12;
+    output fabric_fpga_wdata_axi_s1_o120;
+    output fabric_fpga_wdata_axi_s1_o121;
+    output fabric_fpga_wdata_axi_s1_o122;
+    output fabric_fpga_wdata_axi_s1_o123;
+    output fabric_fpga_wdata_axi_s1_o124;
+    output fabric_fpga_wdata_axi_s1_o125;
+    output fabric_fpga_wdata_axi_s1_o126;
+    output fabric_fpga_wdata_axi_s1_o127;
+    output fabric_fpga_wdata_axi_s1_o128;
+    output fabric_fpga_wdata_axi_s1_o13;
+    output fabric_fpga_wdata_axi_s1_o14;
+    output fabric_fpga_wdata_axi_s1_o15;
+    output fabric_fpga_wdata_axi_s1_o16;
+    output fabric_fpga_wdata_axi_s1_o17;
+    output fabric_fpga_wdata_axi_s1_o18;
+    output fabric_fpga_wdata_axi_s1_o19;
+    output fabric_fpga_wdata_axi_s1_o2;
+    output fabric_fpga_wdata_axi_s1_o20;
+    output fabric_fpga_wdata_axi_s1_o21;
+    output fabric_fpga_wdata_axi_s1_o22;
+    output fabric_fpga_wdata_axi_s1_o23;
+    output fabric_fpga_wdata_axi_s1_o24;
+    output fabric_fpga_wdata_axi_s1_o25;
+    output fabric_fpga_wdata_axi_s1_o26;
+    output fabric_fpga_wdata_axi_s1_o27;
+    output fabric_fpga_wdata_axi_s1_o28;
+    output fabric_fpga_wdata_axi_s1_o29;
+    output fabric_fpga_wdata_axi_s1_o3;
+    output fabric_fpga_wdata_axi_s1_o30;
+    output fabric_fpga_wdata_axi_s1_o31;
+    output fabric_fpga_wdata_axi_s1_o32;
+    output fabric_fpga_wdata_axi_s1_o33;
+    output fabric_fpga_wdata_axi_s1_o34;
+    output fabric_fpga_wdata_axi_s1_o35;
+    output fabric_fpga_wdata_axi_s1_o36;
+    output fabric_fpga_wdata_axi_s1_o37;
+    output fabric_fpga_wdata_axi_s1_o38;
+    output fabric_fpga_wdata_axi_s1_o39;
+    output fabric_fpga_wdata_axi_s1_o4;
+    output fabric_fpga_wdata_axi_s1_o40;
+    output fabric_fpga_wdata_axi_s1_o41;
+    output fabric_fpga_wdata_axi_s1_o42;
+    output fabric_fpga_wdata_axi_s1_o43;
+    output fabric_fpga_wdata_axi_s1_o44;
+    output fabric_fpga_wdata_axi_s1_o45;
+    output fabric_fpga_wdata_axi_s1_o46;
+    output fabric_fpga_wdata_axi_s1_o47;
+    output fabric_fpga_wdata_axi_s1_o48;
+    output fabric_fpga_wdata_axi_s1_o49;
+    output fabric_fpga_wdata_axi_s1_o5;
+    output fabric_fpga_wdata_axi_s1_o50;
+    output fabric_fpga_wdata_axi_s1_o51;
+    output fabric_fpga_wdata_axi_s1_o52;
+    output fabric_fpga_wdata_axi_s1_o53;
+    output fabric_fpga_wdata_axi_s1_o54;
+    output fabric_fpga_wdata_axi_s1_o55;
+    output fabric_fpga_wdata_axi_s1_o56;
+    output fabric_fpga_wdata_axi_s1_o57;
+    output fabric_fpga_wdata_axi_s1_o58;
+    output fabric_fpga_wdata_axi_s1_o59;
+    output fabric_fpga_wdata_axi_s1_o6;
+    output fabric_fpga_wdata_axi_s1_o60;
+    output fabric_fpga_wdata_axi_s1_o61;
+    output fabric_fpga_wdata_axi_s1_o62;
+    output fabric_fpga_wdata_axi_s1_o63;
+    output fabric_fpga_wdata_axi_s1_o64;
+    output fabric_fpga_wdata_axi_s1_o65;
+    output fabric_fpga_wdata_axi_s1_o66;
+    output fabric_fpga_wdata_axi_s1_o67;
+    output fabric_fpga_wdata_axi_s1_o68;
+    output fabric_fpga_wdata_axi_s1_o69;
+    output fabric_fpga_wdata_axi_s1_o7;
+    output fabric_fpga_wdata_axi_s1_o70;
+    output fabric_fpga_wdata_axi_s1_o71;
+    output fabric_fpga_wdata_axi_s1_o72;
+    output fabric_fpga_wdata_axi_s1_o73;
+    output fabric_fpga_wdata_axi_s1_o74;
+    output fabric_fpga_wdata_axi_s1_o75;
+    output fabric_fpga_wdata_axi_s1_o76;
+    output fabric_fpga_wdata_axi_s1_o77;
+    output fabric_fpga_wdata_axi_s1_o78;
+    output fabric_fpga_wdata_axi_s1_o79;
+    output fabric_fpga_wdata_axi_s1_o8;
+    output fabric_fpga_wdata_axi_s1_o80;
+    output fabric_fpga_wdata_axi_s1_o81;
+    output fabric_fpga_wdata_axi_s1_o82;
+    output fabric_fpga_wdata_axi_s1_o83;
+    output fabric_fpga_wdata_axi_s1_o84;
+    output fabric_fpga_wdata_axi_s1_o85;
+    output fabric_fpga_wdata_axi_s1_o86;
+    output fabric_fpga_wdata_axi_s1_o87;
+    output fabric_fpga_wdata_axi_s1_o88;
+    output fabric_fpga_wdata_axi_s1_o89;
+    output fabric_fpga_wdata_axi_s1_o9;
+    output fabric_fpga_wdata_axi_s1_o90;
+    output fabric_fpga_wdata_axi_s1_o91;
+    output fabric_fpga_wdata_axi_s1_o92;
+    output fabric_fpga_wdata_axi_s1_o93;
+    output fabric_fpga_wdata_axi_s1_o94;
+    output fabric_fpga_wdata_axi_s1_o95;
+    output fabric_fpga_wdata_axi_s1_o96;
+    output fabric_fpga_wdata_axi_s1_o97;
+    output fabric_fpga_wdata_axi_s1_o98;
+    output fabric_fpga_wdata_axi_s1_o99;
+    output fabric_fpga_wdata_axi_s2_o1;
+    output fabric_fpga_wdata_axi_s2_o10;
+    output fabric_fpga_wdata_axi_s2_o100;
+    output fabric_fpga_wdata_axi_s2_o101;
+    output fabric_fpga_wdata_axi_s2_o102;
+    output fabric_fpga_wdata_axi_s2_o103;
+    output fabric_fpga_wdata_axi_s2_o104;
+    output fabric_fpga_wdata_axi_s2_o105;
+    output fabric_fpga_wdata_axi_s2_o106;
+    output fabric_fpga_wdata_axi_s2_o107;
+    output fabric_fpga_wdata_axi_s2_o108;
+    output fabric_fpga_wdata_axi_s2_o109;
+    output fabric_fpga_wdata_axi_s2_o11;
+    output fabric_fpga_wdata_axi_s2_o110;
+    output fabric_fpga_wdata_axi_s2_o111;
+    output fabric_fpga_wdata_axi_s2_o112;
+    output fabric_fpga_wdata_axi_s2_o113;
+    output fabric_fpga_wdata_axi_s2_o114;
+    output fabric_fpga_wdata_axi_s2_o115;
+    output fabric_fpga_wdata_axi_s2_o116;
+    output fabric_fpga_wdata_axi_s2_o117;
+    output fabric_fpga_wdata_axi_s2_o118;
+    output fabric_fpga_wdata_axi_s2_o119;
+    output fabric_fpga_wdata_axi_s2_o12;
+    output fabric_fpga_wdata_axi_s2_o120;
+    output fabric_fpga_wdata_axi_s2_o121;
+    output fabric_fpga_wdata_axi_s2_o122;
+    output fabric_fpga_wdata_axi_s2_o123;
+    output fabric_fpga_wdata_axi_s2_o124;
+    output fabric_fpga_wdata_axi_s2_o125;
+    output fabric_fpga_wdata_axi_s2_o126;
+    output fabric_fpga_wdata_axi_s2_o127;
+    output fabric_fpga_wdata_axi_s2_o128;
+    output fabric_fpga_wdata_axi_s2_o13;
+    output fabric_fpga_wdata_axi_s2_o14;
+    output fabric_fpga_wdata_axi_s2_o15;
+    output fabric_fpga_wdata_axi_s2_o16;
+    output fabric_fpga_wdata_axi_s2_o17;
+    output fabric_fpga_wdata_axi_s2_o18;
+    output fabric_fpga_wdata_axi_s2_o19;
+    output fabric_fpga_wdata_axi_s2_o2;
+    output fabric_fpga_wdata_axi_s2_o20;
+    output fabric_fpga_wdata_axi_s2_o21;
+    output fabric_fpga_wdata_axi_s2_o22;
+    output fabric_fpga_wdata_axi_s2_o23;
+    output fabric_fpga_wdata_axi_s2_o24;
+    output fabric_fpga_wdata_axi_s2_o25;
+    output fabric_fpga_wdata_axi_s2_o26;
+    output fabric_fpga_wdata_axi_s2_o27;
+    output fabric_fpga_wdata_axi_s2_o28;
+    output fabric_fpga_wdata_axi_s2_o29;
+    output fabric_fpga_wdata_axi_s2_o3;
+    output fabric_fpga_wdata_axi_s2_o30;
+    output fabric_fpga_wdata_axi_s2_o31;
+    output fabric_fpga_wdata_axi_s2_o32;
+    output fabric_fpga_wdata_axi_s2_o33;
+    output fabric_fpga_wdata_axi_s2_o34;
+    output fabric_fpga_wdata_axi_s2_o35;
+    output fabric_fpga_wdata_axi_s2_o36;
+    output fabric_fpga_wdata_axi_s2_o37;
+    output fabric_fpga_wdata_axi_s2_o38;
+    output fabric_fpga_wdata_axi_s2_o39;
+    output fabric_fpga_wdata_axi_s2_o4;
+    output fabric_fpga_wdata_axi_s2_o40;
+    output fabric_fpga_wdata_axi_s2_o41;
+    output fabric_fpga_wdata_axi_s2_o42;
+    output fabric_fpga_wdata_axi_s2_o43;
+    output fabric_fpga_wdata_axi_s2_o44;
+    output fabric_fpga_wdata_axi_s2_o45;
+    output fabric_fpga_wdata_axi_s2_o46;
+    output fabric_fpga_wdata_axi_s2_o47;
+    output fabric_fpga_wdata_axi_s2_o48;
+    output fabric_fpga_wdata_axi_s2_o49;
+    output fabric_fpga_wdata_axi_s2_o5;
+    output fabric_fpga_wdata_axi_s2_o50;
+    output fabric_fpga_wdata_axi_s2_o51;
+    output fabric_fpga_wdata_axi_s2_o52;
+    output fabric_fpga_wdata_axi_s2_o53;
+    output fabric_fpga_wdata_axi_s2_o54;
+    output fabric_fpga_wdata_axi_s2_o55;
+    output fabric_fpga_wdata_axi_s2_o56;
+    output fabric_fpga_wdata_axi_s2_o57;
+    output fabric_fpga_wdata_axi_s2_o58;
+    output fabric_fpga_wdata_axi_s2_o59;
+    output fabric_fpga_wdata_axi_s2_o6;
+    output fabric_fpga_wdata_axi_s2_o60;
+    output fabric_fpga_wdata_axi_s2_o61;
+    output fabric_fpga_wdata_axi_s2_o62;
+    output fabric_fpga_wdata_axi_s2_o63;
+    output fabric_fpga_wdata_axi_s2_o64;
+    output fabric_fpga_wdata_axi_s2_o65;
+    output fabric_fpga_wdata_axi_s2_o66;
+    output fabric_fpga_wdata_axi_s2_o67;
+    output fabric_fpga_wdata_axi_s2_o68;
+    output fabric_fpga_wdata_axi_s2_o69;
+    output fabric_fpga_wdata_axi_s2_o7;
+    output fabric_fpga_wdata_axi_s2_o70;
+    output fabric_fpga_wdata_axi_s2_o71;
+    output fabric_fpga_wdata_axi_s2_o72;
+    output fabric_fpga_wdata_axi_s2_o73;
+    output fabric_fpga_wdata_axi_s2_o74;
+    output fabric_fpga_wdata_axi_s2_o75;
+    output fabric_fpga_wdata_axi_s2_o76;
+    output fabric_fpga_wdata_axi_s2_o77;
+    output fabric_fpga_wdata_axi_s2_o78;
+    output fabric_fpga_wdata_axi_s2_o79;
+    output fabric_fpga_wdata_axi_s2_o8;
+    output fabric_fpga_wdata_axi_s2_o80;
+    output fabric_fpga_wdata_axi_s2_o81;
+    output fabric_fpga_wdata_axi_s2_o82;
+    output fabric_fpga_wdata_axi_s2_o83;
+    output fabric_fpga_wdata_axi_s2_o84;
+    output fabric_fpga_wdata_axi_s2_o85;
+    output fabric_fpga_wdata_axi_s2_o86;
+    output fabric_fpga_wdata_axi_s2_o87;
+    output fabric_fpga_wdata_axi_s2_o88;
+    output fabric_fpga_wdata_axi_s2_o89;
+    output fabric_fpga_wdata_axi_s2_o9;
+    output fabric_fpga_wdata_axi_s2_o90;
+    output fabric_fpga_wdata_axi_s2_o91;
+    output fabric_fpga_wdata_axi_s2_o92;
+    output fabric_fpga_wdata_axi_s2_o93;
+    output fabric_fpga_wdata_axi_s2_o94;
+    output fabric_fpga_wdata_axi_s2_o95;
+    output fabric_fpga_wdata_axi_s2_o96;
+    output fabric_fpga_wdata_axi_s2_o97;
+    output fabric_fpga_wdata_axi_s2_o98;
+    output fabric_fpga_wdata_axi_s2_o99;
+    input fabric_fpga_wlast_axi_m1_i;
+    input fabric_fpga_wlast_axi_m2_i;
+    output fabric_fpga_wlast_axi_s1_o;
+    output fabric_fpga_wlast_axi_s2_o;
+    output fabric_fpga_wready_axi_m1_o;
+    output fabric_fpga_wready_axi_m2_o;
+    input fabric_fpga_wready_axi_s1_i;
+    input fabric_fpga_wready_axi_s2_i;
+    input fabric_fpga_wstrb_axi_m1_i1;
+    input fabric_fpga_wstrb_axi_m1_i10;
+    input fabric_fpga_wstrb_axi_m1_i11;
+    input fabric_fpga_wstrb_axi_m1_i12;
+    input fabric_fpga_wstrb_axi_m1_i13;
+    input fabric_fpga_wstrb_axi_m1_i14;
+    input fabric_fpga_wstrb_axi_m1_i15;
+    input fabric_fpga_wstrb_axi_m1_i16;
+    input fabric_fpga_wstrb_axi_m1_i2;
+    input fabric_fpga_wstrb_axi_m1_i3;
+    input fabric_fpga_wstrb_axi_m1_i4;
+    input fabric_fpga_wstrb_axi_m1_i5;
+    input fabric_fpga_wstrb_axi_m1_i6;
+    input fabric_fpga_wstrb_axi_m1_i7;
+    input fabric_fpga_wstrb_axi_m1_i8;
+    input fabric_fpga_wstrb_axi_m1_i9;
+    input fabric_fpga_wstrb_axi_m2_i1;
+    input fabric_fpga_wstrb_axi_m2_i10;
+    input fabric_fpga_wstrb_axi_m2_i11;
+    input fabric_fpga_wstrb_axi_m2_i12;
+    input fabric_fpga_wstrb_axi_m2_i13;
+    input fabric_fpga_wstrb_axi_m2_i14;
+    input fabric_fpga_wstrb_axi_m2_i15;
+    input fabric_fpga_wstrb_axi_m2_i16;
+    input fabric_fpga_wstrb_axi_m2_i2;
+    input fabric_fpga_wstrb_axi_m2_i3;
+    input fabric_fpga_wstrb_axi_m2_i4;
+    input fabric_fpga_wstrb_axi_m2_i5;
+    input fabric_fpga_wstrb_axi_m2_i6;
+    input fabric_fpga_wstrb_axi_m2_i7;
+    input fabric_fpga_wstrb_axi_m2_i8;
+    input fabric_fpga_wstrb_axi_m2_i9;
+    output fabric_fpga_wstrb_axi_s1_o1;
+    output fabric_fpga_wstrb_axi_s1_o10;
+    output fabric_fpga_wstrb_axi_s1_o11;
+    output fabric_fpga_wstrb_axi_s1_o12;
+    output fabric_fpga_wstrb_axi_s1_o13;
+    output fabric_fpga_wstrb_axi_s1_o14;
+    output fabric_fpga_wstrb_axi_s1_o15;
+    output fabric_fpga_wstrb_axi_s1_o16;
+    output fabric_fpga_wstrb_axi_s1_o2;
+    output fabric_fpga_wstrb_axi_s1_o3;
+    output fabric_fpga_wstrb_axi_s1_o4;
+    output fabric_fpga_wstrb_axi_s1_o5;
+    output fabric_fpga_wstrb_axi_s1_o6;
+    output fabric_fpga_wstrb_axi_s1_o7;
+    output fabric_fpga_wstrb_axi_s1_o8;
+    output fabric_fpga_wstrb_axi_s1_o9;
+    output fabric_fpga_wstrb_axi_s2_o1;
+    output fabric_fpga_wstrb_axi_s2_o10;
+    output fabric_fpga_wstrb_axi_s2_o11;
+    output fabric_fpga_wstrb_axi_s2_o12;
+    output fabric_fpga_wstrb_axi_s2_o13;
+    output fabric_fpga_wstrb_axi_s2_o14;
+    output fabric_fpga_wstrb_axi_s2_o15;
+    output fabric_fpga_wstrb_axi_s2_o16;
+    output fabric_fpga_wstrb_axi_s2_o2;
+    output fabric_fpga_wstrb_axi_s2_o3;
+    output fabric_fpga_wstrb_axi_s2_o4;
+    output fabric_fpga_wstrb_axi_s2_o5;
+    output fabric_fpga_wstrb_axi_s2_o6;
+    output fabric_fpga_wstrb_axi_s2_o7;
+    output fabric_fpga_wstrb_axi_s2_o8;
+    output fabric_fpga_wstrb_axi_s2_o9;
+    input fabric_fpga_wvalid_axi_m1_i;
+    input fabric_fpga_wvalid_axi_m2_i;
+    output fabric_fpga_wvalid_axi_s1_o;
+    output fabric_fpga_wvalid_axi_s2_o;
+    output fabric_llpp0_araddr_s_o1;
+    output fabric_llpp0_araddr_s_o10;
+    output fabric_llpp0_araddr_s_o11;
+    output fabric_llpp0_araddr_s_o12;
+    output fabric_llpp0_araddr_s_o13;
+    output fabric_llpp0_araddr_s_o14;
+    output fabric_llpp0_araddr_s_o15;
+    output fabric_llpp0_araddr_s_o16;
+    output fabric_llpp0_araddr_s_o17;
+    output fabric_llpp0_araddr_s_o18;
+    output fabric_llpp0_araddr_s_o19;
+    output fabric_llpp0_araddr_s_o2;
+    output fabric_llpp0_araddr_s_o20;
+    output fabric_llpp0_araddr_s_o21;
+    output fabric_llpp0_araddr_s_o22;
+    output fabric_llpp0_araddr_s_o23;
+    output fabric_llpp0_araddr_s_o24;
+    output fabric_llpp0_araddr_s_o25;
+    output fabric_llpp0_araddr_s_o26;
+    output fabric_llpp0_araddr_s_o27;
+    output fabric_llpp0_araddr_s_o28;
+    output fabric_llpp0_araddr_s_o29;
+    output fabric_llpp0_araddr_s_o3;
+    output fabric_llpp0_araddr_s_o30;
+    output fabric_llpp0_araddr_s_o31;
+    output fabric_llpp0_araddr_s_o32;
+    output fabric_llpp0_araddr_s_o4;
+    output fabric_llpp0_araddr_s_o5;
+    output fabric_llpp0_araddr_s_o6;
+    output fabric_llpp0_araddr_s_o7;
+    output fabric_llpp0_araddr_s_o8;
+    output fabric_llpp0_araddr_s_o9;
+    output fabric_llpp0_arburst_s_o1;
+    output fabric_llpp0_arburst_s_o2;
+    output fabric_llpp0_arcache_s_o1;
+    output fabric_llpp0_arcache_s_o2;
+    output fabric_llpp0_arcache_s_o3;
+    output fabric_llpp0_arcache_s_o4;
+    output fabric_llpp0_arid_s_o1;
+    output fabric_llpp0_arid_s_o10;
+    output fabric_llpp0_arid_s_o11;
+    output fabric_llpp0_arid_s_o12;
+    output fabric_llpp0_arid_s_o2;
+    output fabric_llpp0_arid_s_o3;
+    output fabric_llpp0_arid_s_o4;
+    output fabric_llpp0_arid_s_o5;
+    output fabric_llpp0_arid_s_o6;
+    output fabric_llpp0_arid_s_o7;
+    output fabric_llpp0_arid_s_o8;
+    output fabric_llpp0_arid_s_o9;
+    output fabric_llpp0_arlen_s_o1;
+    output fabric_llpp0_arlen_s_o2;
+    output fabric_llpp0_arlen_s_o3;
+    output fabric_llpp0_arlen_s_o4;
+    output fabric_llpp0_arlen_s_o5;
+    output fabric_llpp0_arlen_s_o6;
+    output fabric_llpp0_arlen_s_o7;
+    output fabric_llpp0_arlen_s_o8;
+    output fabric_llpp0_arlock_s_o;
+    output fabric_llpp0_arprot_s_o1;
+    output fabric_llpp0_arprot_s_o2;
+    output fabric_llpp0_arprot_s_o3;
+    output fabric_llpp0_arqos_s_o1;
+    output fabric_llpp0_arqos_s_o2;
+    output fabric_llpp0_arqos_s_o3;
+    output fabric_llpp0_arqos_s_o4;
+    input fabric_llpp0_arready_s_i;
+    output fabric_llpp0_arsize_s_o1;
+    output fabric_llpp0_arsize_s_o2;
+    output fabric_llpp0_arsize_s_o3;
+    output fabric_llpp0_arvalid_s_o;
+    output fabric_llpp0_awaddr_s_o1;
+    output fabric_llpp0_awaddr_s_o10;
+    output fabric_llpp0_awaddr_s_o11;
+    output fabric_llpp0_awaddr_s_o12;
+    output fabric_llpp0_awaddr_s_o13;
+    output fabric_llpp0_awaddr_s_o14;
+    output fabric_llpp0_awaddr_s_o15;
+    output fabric_llpp0_awaddr_s_o16;
+    output fabric_llpp0_awaddr_s_o17;
+    output fabric_llpp0_awaddr_s_o18;
+    output fabric_llpp0_awaddr_s_o19;
+    output fabric_llpp0_awaddr_s_o2;
+    output fabric_llpp0_awaddr_s_o20;
+    output fabric_llpp0_awaddr_s_o21;
+    output fabric_llpp0_awaddr_s_o22;
+    output fabric_llpp0_awaddr_s_o23;
+    output fabric_llpp0_awaddr_s_o24;
+    output fabric_llpp0_awaddr_s_o25;
+    output fabric_llpp0_awaddr_s_o26;
+    output fabric_llpp0_awaddr_s_o27;
+    output fabric_llpp0_awaddr_s_o28;
+    output fabric_llpp0_awaddr_s_o29;
+    output fabric_llpp0_awaddr_s_o3;
+    output fabric_llpp0_awaddr_s_o30;
+    output fabric_llpp0_awaddr_s_o31;
+    output fabric_llpp0_awaddr_s_o32;
+    output fabric_llpp0_awaddr_s_o4;
+    output fabric_llpp0_awaddr_s_o5;
+    output fabric_llpp0_awaddr_s_o6;
+    output fabric_llpp0_awaddr_s_o7;
+    output fabric_llpp0_awaddr_s_o8;
+    output fabric_llpp0_awaddr_s_o9;
+    output fabric_llpp0_awburst_s_o1;
+    output fabric_llpp0_awburst_s_o2;
+    output fabric_llpp0_awcache_s_o1;
+    output fabric_llpp0_awcache_s_o2;
+    output fabric_llpp0_awcache_s_o3;
+    output fabric_llpp0_awcache_s_o4;
+    output fabric_llpp0_awid_s_o1;
+    output fabric_llpp0_awid_s_o10;
+    output fabric_llpp0_awid_s_o11;
+    output fabric_llpp0_awid_s_o12;
+    output fabric_llpp0_awid_s_o2;
+    output fabric_llpp0_awid_s_o3;
+    output fabric_llpp0_awid_s_o4;
+    output fabric_llpp0_awid_s_o5;
+    output fabric_llpp0_awid_s_o6;
+    output fabric_llpp0_awid_s_o7;
+    output fabric_llpp0_awid_s_o8;
+    output fabric_llpp0_awid_s_o9;
+    output fabric_llpp0_awlen_s_o1;
+    output fabric_llpp0_awlen_s_o2;
+    output fabric_llpp0_awlen_s_o3;
+    output fabric_llpp0_awlen_s_o4;
+    output fabric_llpp0_awlen_s_o5;
+    output fabric_llpp0_awlen_s_o6;
+    output fabric_llpp0_awlen_s_o7;
+    output fabric_llpp0_awlen_s_o8;
+    output fabric_llpp0_awlock_s_o;
+    output fabric_llpp0_awprot_s_o1;
+    output fabric_llpp0_awprot_s_o2;
+    output fabric_llpp0_awprot_s_o3;
+    output fabric_llpp0_awqos_s_o1;
+    output fabric_llpp0_awqos_s_o2;
+    output fabric_llpp0_awqos_s_o3;
+    output fabric_llpp0_awqos_s_o4;
+    input fabric_llpp0_awready_s_i;
+    output fabric_llpp0_awsize_s_o1;
+    output fabric_llpp0_awsize_s_o2;
+    output fabric_llpp0_awsize_s_o3;
+    output fabric_llpp0_awvalid_s_o;
+    input fabric_llpp0_bid_s_i1;
+    input fabric_llpp0_bid_s_i10;
+    input fabric_llpp0_bid_s_i11;
+    input fabric_llpp0_bid_s_i12;
+    input fabric_llpp0_bid_s_i2;
+    input fabric_llpp0_bid_s_i3;
+    input fabric_llpp0_bid_s_i4;
+    input fabric_llpp0_bid_s_i5;
+    input fabric_llpp0_bid_s_i6;
+    input fabric_llpp0_bid_s_i7;
+    input fabric_llpp0_bid_s_i8;
+    input fabric_llpp0_bid_s_i9;
+    output fabric_llpp0_bready_s_o;
+    input fabric_llpp0_bresp_s_i1;
+    input fabric_llpp0_bresp_s_i2;
+    input fabric_llpp0_bvalid_s_i;
+    input fabric_llpp0_rdata_s_i1;
+    input fabric_llpp0_rdata_s_i10;
+    input fabric_llpp0_rdata_s_i11;
+    input fabric_llpp0_rdata_s_i12;
+    input fabric_llpp0_rdata_s_i13;
+    input fabric_llpp0_rdata_s_i14;
+    input fabric_llpp0_rdata_s_i15;
+    input fabric_llpp0_rdata_s_i16;
+    input fabric_llpp0_rdata_s_i17;
+    input fabric_llpp0_rdata_s_i18;
+    input fabric_llpp0_rdata_s_i19;
+    input fabric_llpp0_rdata_s_i2;
+    input fabric_llpp0_rdata_s_i20;
+    input fabric_llpp0_rdata_s_i21;
+    input fabric_llpp0_rdata_s_i22;
+    input fabric_llpp0_rdata_s_i23;
+    input fabric_llpp0_rdata_s_i24;
+    input fabric_llpp0_rdata_s_i25;
+    input fabric_llpp0_rdata_s_i26;
+    input fabric_llpp0_rdata_s_i27;
+    input fabric_llpp0_rdata_s_i28;
+    input fabric_llpp0_rdata_s_i29;
+    input fabric_llpp0_rdata_s_i3;
+    input fabric_llpp0_rdata_s_i30;
+    input fabric_llpp0_rdata_s_i31;
+    input fabric_llpp0_rdata_s_i32;
+    input fabric_llpp0_rdata_s_i4;
+    input fabric_llpp0_rdata_s_i5;
+    input fabric_llpp0_rdata_s_i6;
+    input fabric_llpp0_rdata_s_i7;
+    input fabric_llpp0_rdata_s_i8;
+    input fabric_llpp0_rdata_s_i9;
+    input fabric_llpp0_rid_s_i1;
+    input fabric_llpp0_rid_s_i10;
+    input fabric_llpp0_rid_s_i11;
+    input fabric_llpp0_rid_s_i12;
+    input fabric_llpp0_rid_s_i2;
+    input fabric_llpp0_rid_s_i3;
+    input fabric_llpp0_rid_s_i4;
+    input fabric_llpp0_rid_s_i5;
+    input fabric_llpp0_rid_s_i6;
+    input fabric_llpp0_rid_s_i7;
+    input fabric_llpp0_rid_s_i8;
+    input fabric_llpp0_rid_s_i9;
+    input fabric_llpp0_rlast_s_i;
+    output fabric_llpp0_rready_s_o;
+    input fabric_llpp0_rresp_s_i1;
+    input fabric_llpp0_rresp_s_i2;
+    input fabric_llpp0_rvalid_s_i;
+    output fabric_llpp0_wdata_s_o1;
+    output fabric_llpp0_wdata_s_o10;
+    output fabric_llpp0_wdata_s_o11;
+    output fabric_llpp0_wdata_s_o12;
+    output fabric_llpp0_wdata_s_o13;
+    output fabric_llpp0_wdata_s_o14;
+    output fabric_llpp0_wdata_s_o15;
+    output fabric_llpp0_wdata_s_o16;
+    output fabric_llpp0_wdata_s_o17;
+    output fabric_llpp0_wdata_s_o18;
+    output fabric_llpp0_wdata_s_o19;
+    output fabric_llpp0_wdata_s_o2;
+    output fabric_llpp0_wdata_s_o20;
+    output fabric_llpp0_wdata_s_o21;
+    output fabric_llpp0_wdata_s_o22;
+    output fabric_llpp0_wdata_s_o23;
+    output fabric_llpp0_wdata_s_o24;
+    output fabric_llpp0_wdata_s_o25;
+    output fabric_llpp0_wdata_s_o26;
+    output fabric_llpp0_wdata_s_o27;
+    output fabric_llpp0_wdata_s_o28;
+    output fabric_llpp0_wdata_s_o29;
+    output fabric_llpp0_wdata_s_o3;
+    output fabric_llpp0_wdata_s_o30;
+    output fabric_llpp0_wdata_s_o31;
+    output fabric_llpp0_wdata_s_o32;
+    output fabric_llpp0_wdata_s_o4;
+    output fabric_llpp0_wdata_s_o5;
+    output fabric_llpp0_wdata_s_o6;
+    output fabric_llpp0_wdata_s_o7;
+    output fabric_llpp0_wdata_s_o8;
+    output fabric_llpp0_wdata_s_o9;
+    output fabric_llpp0_wlast_s_o;
+    input fabric_llpp0_wready_s_i;
+    output fabric_llpp0_wstrb_s_o1;
+    output fabric_llpp0_wstrb_s_o2;
+    output fabric_llpp0_wstrb_s_o3;
+    output fabric_llpp0_wstrb_s_o4;
+    output fabric_llpp0_wvalid_s_o;
+    output fabric_llpp1_araddr_s_o1;
+    output fabric_llpp1_araddr_s_o10;
+    output fabric_llpp1_araddr_s_o11;
+    output fabric_llpp1_araddr_s_o12;
+    output fabric_llpp1_araddr_s_o13;
+    output fabric_llpp1_araddr_s_o14;
+    output fabric_llpp1_araddr_s_o15;
+    output fabric_llpp1_araddr_s_o16;
+    output fabric_llpp1_araddr_s_o17;
+    output fabric_llpp1_araddr_s_o18;
+    output fabric_llpp1_araddr_s_o19;
+    output fabric_llpp1_araddr_s_o2;
+    output fabric_llpp1_araddr_s_o20;
+    output fabric_llpp1_araddr_s_o21;
+    output fabric_llpp1_araddr_s_o22;
+    output fabric_llpp1_araddr_s_o23;
+    output fabric_llpp1_araddr_s_o24;
+    output fabric_llpp1_araddr_s_o25;
+    output fabric_llpp1_araddr_s_o26;
+    output fabric_llpp1_araddr_s_o27;
+    output fabric_llpp1_araddr_s_o28;
+    output fabric_llpp1_araddr_s_o29;
+    output fabric_llpp1_araddr_s_o3;
+    output fabric_llpp1_araddr_s_o30;
+    output fabric_llpp1_araddr_s_o31;
+    output fabric_llpp1_araddr_s_o32;
+    output fabric_llpp1_araddr_s_o4;
+    output fabric_llpp1_araddr_s_o5;
+    output fabric_llpp1_araddr_s_o6;
+    output fabric_llpp1_araddr_s_o7;
+    output fabric_llpp1_araddr_s_o8;
+    output fabric_llpp1_araddr_s_o9;
+    output fabric_llpp1_arburst_s_o1;
+    output fabric_llpp1_arburst_s_o2;
+    output fabric_llpp1_arcache_s_o1;
+    output fabric_llpp1_arcache_s_o2;
+    output fabric_llpp1_arcache_s_o3;
+    output fabric_llpp1_arcache_s_o4;
+    output fabric_llpp1_arid_s_o1;
+    output fabric_llpp1_arid_s_o10;
+    output fabric_llpp1_arid_s_o11;
+    output fabric_llpp1_arid_s_o12;
+    output fabric_llpp1_arid_s_o2;
+    output fabric_llpp1_arid_s_o3;
+    output fabric_llpp1_arid_s_o4;
+    output fabric_llpp1_arid_s_o5;
+    output fabric_llpp1_arid_s_o6;
+    output fabric_llpp1_arid_s_o7;
+    output fabric_llpp1_arid_s_o8;
+    output fabric_llpp1_arid_s_o9;
+    output fabric_llpp1_arlen_s_o1;
+    output fabric_llpp1_arlen_s_o2;
+    output fabric_llpp1_arlen_s_o3;
+    output fabric_llpp1_arlen_s_o4;
+    output fabric_llpp1_arlen_s_o5;
+    output fabric_llpp1_arlen_s_o6;
+    output fabric_llpp1_arlen_s_o7;
+    output fabric_llpp1_arlen_s_o8;
+    output fabric_llpp1_arlock_s_o;
+    output fabric_llpp1_arprot_s_o1;
+    output fabric_llpp1_arprot_s_o2;
+    output fabric_llpp1_arprot_s_o3;
+    output fabric_llpp1_arqos_s_o1;
+    output fabric_llpp1_arqos_s_o2;
+    output fabric_llpp1_arqos_s_o3;
+    output fabric_llpp1_arqos_s_o4;
+    input fabric_llpp1_arready_s_i;
+    output fabric_llpp1_arsize_s_o1;
+    output fabric_llpp1_arsize_s_o2;
+    output fabric_llpp1_arsize_s_o3;
+    output fabric_llpp1_arvalid_s_o;
+    output fabric_llpp1_awaddr_s_o1;
+    output fabric_llpp1_awaddr_s_o10;
+    output fabric_llpp1_awaddr_s_o11;
+    output fabric_llpp1_awaddr_s_o12;
+    output fabric_llpp1_awaddr_s_o13;
+    output fabric_llpp1_awaddr_s_o14;
+    output fabric_llpp1_awaddr_s_o15;
+    output fabric_llpp1_awaddr_s_o16;
+    output fabric_llpp1_awaddr_s_o17;
+    output fabric_llpp1_awaddr_s_o18;
+    output fabric_llpp1_awaddr_s_o19;
+    output fabric_llpp1_awaddr_s_o2;
+    output fabric_llpp1_awaddr_s_o20;
+    output fabric_llpp1_awaddr_s_o21;
+    output fabric_llpp1_awaddr_s_o22;
+    output fabric_llpp1_awaddr_s_o23;
+    output fabric_llpp1_awaddr_s_o24;
+    output fabric_llpp1_awaddr_s_o25;
+    output fabric_llpp1_awaddr_s_o26;
+    output fabric_llpp1_awaddr_s_o27;
+    output fabric_llpp1_awaddr_s_o28;
+    output fabric_llpp1_awaddr_s_o29;
+    output fabric_llpp1_awaddr_s_o3;
+    output fabric_llpp1_awaddr_s_o30;
+    output fabric_llpp1_awaddr_s_o31;
+    output fabric_llpp1_awaddr_s_o32;
+    output fabric_llpp1_awaddr_s_o4;
+    output fabric_llpp1_awaddr_s_o5;
+    output fabric_llpp1_awaddr_s_o6;
+    output fabric_llpp1_awaddr_s_o7;
+    output fabric_llpp1_awaddr_s_o8;
+    output fabric_llpp1_awaddr_s_o9;
+    output fabric_llpp1_awburst_s_o1;
+    output fabric_llpp1_awburst_s_o2;
+    output fabric_llpp1_awcache_s_o1;
+    output fabric_llpp1_awcache_s_o2;
+    output fabric_llpp1_awcache_s_o3;
+    output fabric_llpp1_awcache_s_o4;
+    output fabric_llpp1_awid_s_o1;
+    output fabric_llpp1_awid_s_o10;
+    output fabric_llpp1_awid_s_o11;
+    output fabric_llpp1_awid_s_o12;
+    output fabric_llpp1_awid_s_o2;
+    output fabric_llpp1_awid_s_o3;
+    output fabric_llpp1_awid_s_o4;
+    output fabric_llpp1_awid_s_o5;
+    output fabric_llpp1_awid_s_o6;
+    output fabric_llpp1_awid_s_o7;
+    output fabric_llpp1_awid_s_o8;
+    output fabric_llpp1_awid_s_o9;
+    output fabric_llpp1_awlen_s_o1;
+    output fabric_llpp1_awlen_s_o2;
+    output fabric_llpp1_awlen_s_o3;
+    output fabric_llpp1_awlen_s_o4;
+    output fabric_llpp1_awlen_s_o5;
+    output fabric_llpp1_awlen_s_o6;
+    output fabric_llpp1_awlen_s_o7;
+    output fabric_llpp1_awlen_s_o8;
+    output fabric_llpp1_awlock_s_o;
+    output fabric_llpp1_awprot_s_o1;
+    output fabric_llpp1_awprot_s_o2;
+    output fabric_llpp1_awprot_s_o3;
+    output fabric_llpp1_awqos_s_o1;
+    output fabric_llpp1_awqos_s_o2;
+    output fabric_llpp1_awqos_s_o3;
+    output fabric_llpp1_awqos_s_o4;
+    input fabric_llpp1_awready_s_i;
+    output fabric_llpp1_awsize_s_o1;
+    output fabric_llpp1_awsize_s_o2;
+    output fabric_llpp1_awsize_s_o3;
+    output fabric_llpp1_awvalid_s_o;
+    input fabric_llpp1_bid_s_i1;
+    input fabric_llpp1_bid_s_i10;
+    input fabric_llpp1_bid_s_i11;
+    input fabric_llpp1_bid_s_i12;
+    input fabric_llpp1_bid_s_i2;
+    input fabric_llpp1_bid_s_i3;
+    input fabric_llpp1_bid_s_i4;
+    input fabric_llpp1_bid_s_i5;
+    input fabric_llpp1_bid_s_i6;
+    input fabric_llpp1_bid_s_i7;
+    input fabric_llpp1_bid_s_i8;
+    input fabric_llpp1_bid_s_i9;
+    output fabric_llpp1_bready_s_o;
+    input fabric_llpp1_bresp_s_i1;
+    input fabric_llpp1_bresp_s_i2;
+    input fabric_llpp1_bvalid_s_i;
+    input fabric_llpp1_rdata_s_i1;
+    input fabric_llpp1_rdata_s_i10;
+    input fabric_llpp1_rdata_s_i11;
+    input fabric_llpp1_rdata_s_i12;
+    input fabric_llpp1_rdata_s_i13;
+    input fabric_llpp1_rdata_s_i14;
+    input fabric_llpp1_rdata_s_i15;
+    input fabric_llpp1_rdata_s_i16;
+    input fabric_llpp1_rdata_s_i17;
+    input fabric_llpp1_rdata_s_i18;
+    input fabric_llpp1_rdata_s_i19;
+    input fabric_llpp1_rdata_s_i2;
+    input fabric_llpp1_rdata_s_i20;
+    input fabric_llpp1_rdata_s_i21;
+    input fabric_llpp1_rdata_s_i22;
+    input fabric_llpp1_rdata_s_i23;
+    input fabric_llpp1_rdata_s_i24;
+    input fabric_llpp1_rdata_s_i25;
+    input fabric_llpp1_rdata_s_i26;
+    input fabric_llpp1_rdata_s_i27;
+    input fabric_llpp1_rdata_s_i28;
+    input fabric_llpp1_rdata_s_i29;
+    input fabric_llpp1_rdata_s_i3;
+    input fabric_llpp1_rdata_s_i30;
+    input fabric_llpp1_rdata_s_i31;
+    input fabric_llpp1_rdata_s_i32;
+    input fabric_llpp1_rdata_s_i4;
+    input fabric_llpp1_rdata_s_i5;
+    input fabric_llpp1_rdata_s_i6;
+    input fabric_llpp1_rdata_s_i7;
+    input fabric_llpp1_rdata_s_i8;
+    input fabric_llpp1_rdata_s_i9;
+    input fabric_llpp1_rid_s_i1;
+    input fabric_llpp1_rid_s_i10;
+    input fabric_llpp1_rid_s_i11;
+    input fabric_llpp1_rid_s_i12;
+    input fabric_llpp1_rid_s_i2;
+    input fabric_llpp1_rid_s_i3;
+    input fabric_llpp1_rid_s_i4;
+    input fabric_llpp1_rid_s_i5;
+    input fabric_llpp1_rid_s_i6;
+    input fabric_llpp1_rid_s_i7;
+    input fabric_llpp1_rid_s_i8;
+    input fabric_llpp1_rid_s_i9;
+    input fabric_llpp1_rlast_s_i;
+    output fabric_llpp1_rready_s_o;
+    input fabric_llpp1_rresp_s_i1;
+    input fabric_llpp1_rresp_s_i2;
+    input fabric_llpp1_rvalid_s_i;
+    output fabric_llpp1_wdata_s_o1;
+    output fabric_llpp1_wdata_s_o10;
+    output fabric_llpp1_wdata_s_o11;
+    output fabric_llpp1_wdata_s_o12;
+    output fabric_llpp1_wdata_s_o13;
+    output fabric_llpp1_wdata_s_o14;
+    output fabric_llpp1_wdata_s_o15;
+    output fabric_llpp1_wdata_s_o16;
+    output fabric_llpp1_wdata_s_o17;
+    output fabric_llpp1_wdata_s_o18;
+    output fabric_llpp1_wdata_s_o19;
+    output fabric_llpp1_wdata_s_o2;
+    output fabric_llpp1_wdata_s_o20;
+    output fabric_llpp1_wdata_s_o21;
+    output fabric_llpp1_wdata_s_o22;
+    output fabric_llpp1_wdata_s_o23;
+    output fabric_llpp1_wdata_s_o24;
+    output fabric_llpp1_wdata_s_o25;
+    output fabric_llpp1_wdata_s_o26;
+    output fabric_llpp1_wdata_s_o27;
+    output fabric_llpp1_wdata_s_o28;
+    output fabric_llpp1_wdata_s_o29;
+    output fabric_llpp1_wdata_s_o3;
+    output fabric_llpp1_wdata_s_o30;
+    output fabric_llpp1_wdata_s_o31;
+    output fabric_llpp1_wdata_s_o32;
+    output fabric_llpp1_wdata_s_o4;
+    output fabric_llpp1_wdata_s_o5;
+    output fabric_llpp1_wdata_s_o6;
+    output fabric_llpp1_wdata_s_o7;
+    output fabric_llpp1_wdata_s_o8;
+    output fabric_llpp1_wdata_s_o9;
+    output fabric_llpp1_wlast_s_o;
+    input fabric_llpp1_wready_s_i;
+    output fabric_llpp1_wstrb_s_o1;
+    output fabric_llpp1_wstrb_s_o2;
+    output fabric_llpp1_wstrb_s_o3;
+    output fabric_llpp1_wstrb_s_o4;
+    output fabric_llpp1_wvalid_s_o;
+    output fabric_llpp2_araddr_s_o1;
+    output fabric_llpp2_araddr_s_o10;
+    output fabric_llpp2_araddr_s_o11;
+    output fabric_llpp2_araddr_s_o12;
+    output fabric_llpp2_araddr_s_o13;
+    output fabric_llpp2_araddr_s_o14;
+    output fabric_llpp2_araddr_s_o15;
+    output fabric_llpp2_araddr_s_o16;
+    output fabric_llpp2_araddr_s_o17;
+    output fabric_llpp2_araddr_s_o18;
+    output fabric_llpp2_araddr_s_o19;
+    output fabric_llpp2_araddr_s_o2;
+    output fabric_llpp2_araddr_s_o20;
+    output fabric_llpp2_araddr_s_o21;
+    output fabric_llpp2_araddr_s_o22;
+    output fabric_llpp2_araddr_s_o23;
+    output fabric_llpp2_araddr_s_o24;
+    output fabric_llpp2_araddr_s_o25;
+    output fabric_llpp2_araddr_s_o26;
+    output fabric_llpp2_araddr_s_o27;
+    output fabric_llpp2_araddr_s_o28;
+    output fabric_llpp2_araddr_s_o29;
+    output fabric_llpp2_araddr_s_o3;
+    output fabric_llpp2_araddr_s_o30;
+    output fabric_llpp2_araddr_s_o31;
+    output fabric_llpp2_araddr_s_o32;
+    output fabric_llpp2_araddr_s_o4;
+    output fabric_llpp2_araddr_s_o5;
+    output fabric_llpp2_araddr_s_o6;
+    output fabric_llpp2_araddr_s_o7;
+    output fabric_llpp2_araddr_s_o8;
+    output fabric_llpp2_araddr_s_o9;
+    output fabric_llpp2_arburst_s_o1;
+    output fabric_llpp2_arburst_s_o2;
+    output fabric_llpp2_arcache_s_o1;
+    output fabric_llpp2_arcache_s_o2;
+    output fabric_llpp2_arcache_s_o3;
+    output fabric_llpp2_arcache_s_o4;
+    output fabric_llpp2_arid_s_o1;
+    output fabric_llpp2_arid_s_o10;
+    output fabric_llpp2_arid_s_o11;
+    output fabric_llpp2_arid_s_o12;
+    output fabric_llpp2_arid_s_o2;
+    output fabric_llpp2_arid_s_o3;
+    output fabric_llpp2_arid_s_o4;
+    output fabric_llpp2_arid_s_o5;
+    output fabric_llpp2_arid_s_o6;
+    output fabric_llpp2_arid_s_o7;
+    output fabric_llpp2_arid_s_o8;
+    output fabric_llpp2_arid_s_o9;
+    output fabric_llpp2_arlen_s_o1;
+    output fabric_llpp2_arlen_s_o2;
+    output fabric_llpp2_arlen_s_o3;
+    output fabric_llpp2_arlen_s_o4;
+    output fabric_llpp2_arlen_s_o5;
+    output fabric_llpp2_arlen_s_o6;
+    output fabric_llpp2_arlen_s_o7;
+    output fabric_llpp2_arlen_s_o8;
+    output fabric_llpp2_arlock_s_o;
+    output fabric_llpp2_arprot_s_o1;
+    output fabric_llpp2_arprot_s_o2;
+    output fabric_llpp2_arprot_s_o3;
+    output fabric_llpp2_arqos_s_o1;
+    output fabric_llpp2_arqos_s_o2;
+    output fabric_llpp2_arqos_s_o3;
+    output fabric_llpp2_arqos_s_o4;
+    input fabric_llpp2_arready_s_i;
+    output fabric_llpp2_arsize_s_o1;
+    output fabric_llpp2_arsize_s_o2;
+    output fabric_llpp2_arsize_s_o3;
+    output fabric_llpp2_arvalid_s_o;
+    output fabric_llpp2_awaddr_s_o1;
+    output fabric_llpp2_awaddr_s_o10;
+    output fabric_llpp2_awaddr_s_o11;
+    output fabric_llpp2_awaddr_s_o12;
+    output fabric_llpp2_awaddr_s_o13;
+    output fabric_llpp2_awaddr_s_o14;
+    output fabric_llpp2_awaddr_s_o15;
+    output fabric_llpp2_awaddr_s_o16;
+    output fabric_llpp2_awaddr_s_o17;
+    output fabric_llpp2_awaddr_s_o18;
+    output fabric_llpp2_awaddr_s_o19;
+    output fabric_llpp2_awaddr_s_o2;
+    output fabric_llpp2_awaddr_s_o20;
+    output fabric_llpp2_awaddr_s_o21;
+    output fabric_llpp2_awaddr_s_o22;
+    output fabric_llpp2_awaddr_s_o23;
+    output fabric_llpp2_awaddr_s_o24;
+    output fabric_llpp2_awaddr_s_o25;
+    output fabric_llpp2_awaddr_s_o26;
+    output fabric_llpp2_awaddr_s_o27;
+    output fabric_llpp2_awaddr_s_o28;
+    output fabric_llpp2_awaddr_s_o29;
+    output fabric_llpp2_awaddr_s_o3;
+    output fabric_llpp2_awaddr_s_o30;
+    output fabric_llpp2_awaddr_s_o31;
+    output fabric_llpp2_awaddr_s_o32;
+    output fabric_llpp2_awaddr_s_o4;
+    output fabric_llpp2_awaddr_s_o5;
+    output fabric_llpp2_awaddr_s_o6;
+    output fabric_llpp2_awaddr_s_o7;
+    output fabric_llpp2_awaddr_s_o8;
+    output fabric_llpp2_awaddr_s_o9;
+    output fabric_llpp2_awburst_s_o1;
+    output fabric_llpp2_awburst_s_o2;
+    output fabric_llpp2_awcache_s_o1;
+    output fabric_llpp2_awcache_s_o2;
+    output fabric_llpp2_awcache_s_o3;
+    output fabric_llpp2_awcache_s_o4;
+    output fabric_llpp2_awid_s_o1;
+    output fabric_llpp2_awid_s_o10;
+    output fabric_llpp2_awid_s_o11;
+    output fabric_llpp2_awid_s_o12;
+    output fabric_llpp2_awid_s_o2;
+    output fabric_llpp2_awid_s_o3;
+    output fabric_llpp2_awid_s_o4;
+    output fabric_llpp2_awid_s_o5;
+    output fabric_llpp2_awid_s_o6;
+    output fabric_llpp2_awid_s_o7;
+    output fabric_llpp2_awid_s_o8;
+    output fabric_llpp2_awid_s_o9;
+    output fabric_llpp2_awlen_s_o1;
+    output fabric_llpp2_awlen_s_o2;
+    output fabric_llpp2_awlen_s_o3;
+    output fabric_llpp2_awlen_s_o4;
+    output fabric_llpp2_awlen_s_o5;
+    output fabric_llpp2_awlen_s_o6;
+    output fabric_llpp2_awlen_s_o7;
+    output fabric_llpp2_awlen_s_o8;
+    output fabric_llpp2_awlock_s_o;
+    output fabric_llpp2_awprot_s_o1;
+    output fabric_llpp2_awprot_s_o2;
+    output fabric_llpp2_awprot_s_o3;
+    output fabric_llpp2_awqos_s_o1;
+    output fabric_llpp2_awqos_s_o2;
+    output fabric_llpp2_awqos_s_o3;
+    output fabric_llpp2_awqos_s_o4;
+    input fabric_llpp2_awready_s_i;
+    output fabric_llpp2_awsize_s_o1;
+    output fabric_llpp2_awsize_s_o2;
+    output fabric_llpp2_awsize_s_o3;
+    output fabric_llpp2_awvalid_s_o;
+    input fabric_llpp2_bid_s_i1;
+    input fabric_llpp2_bid_s_i10;
+    input fabric_llpp2_bid_s_i11;
+    input fabric_llpp2_bid_s_i12;
+    input fabric_llpp2_bid_s_i2;
+    input fabric_llpp2_bid_s_i3;
+    input fabric_llpp2_bid_s_i4;
+    input fabric_llpp2_bid_s_i5;
+    input fabric_llpp2_bid_s_i6;
+    input fabric_llpp2_bid_s_i7;
+    input fabric_llpp2_bid_s_i8;
+    input fabric_llpp2_bid_s_i9;
+    output fabric_llpp2_bready_s_o;
+    input fabric_llpp2_bresp_s_i1;
+    input fabric_llpp2_bresp_s_i2;
+    input fabric_llpp2_bvalid_s_i;
+    input fabric_llpp2_rdata_s_i1;
+    input fabric_llpp2_rdata_s_i10;
+    input fabric_llpp2_rdata_s_i11;
+    input fabric_llpp2_rdata_s_i12;
+    input fabric_llpp2_rdata_s_i13;
+    input fabric_llpp2_rdata_s_i14;
+    input fabric_llpp2_rdata_s_i15;
+    input fabric_llpp2_rdata_s_i16;
+    input fabric_llpp2_rdata_s_i17;
+    input fabric_llpp2_rdata_s_i18;
+    input fabric_llpp2_rdata_s_i19;
+    input fabric_llpp2_rdata_s_i2;
+    input fabric_llpp2_rdata_s_i20;
+    input fabric_llpp2_rdata_s_i21;
+    input fabric_llpp2_rdata_s_i22;
+    input fabric_llpp2_rdata_s_i23;
+    input fabric_llpp2_rdata_s_i24;
+    input fabric_llpp2_rdata_s_i25;
+    input fabric_llpp2_rdata_s_i26;
+    input fabric_llpp2_rdata_s_i27;
+    input fabric_llpp2_rdata_s_i28;
+    input fabric_llpp2_rdata_s_i29;
+    input fabric_llpp2_rdata_s_i3;
+    input fabric_llpp2_rdata_s_i30;
+    input fabric_llpp2_rdata_s_i31;
+    input fabric_llpp2_rdata_s_i32;
+    input fabric_llpp2_rdata_s_i4;
+    input fabric_llpp2_rdata_s_i5;
+    input fabric_llpp2_rdata_s_i6;
+    input fabric_llpp2_rdata_s_i7;
+    input fabric_llpp2_rdata_s_i8;
+    input fabric_llpp2_rdata_s_i9;
+    input fabric_llpp2_rid_s_i1;
+    input fabric_llpp2_rid_s_i10;
+    input fabric_llpp2_rid_s_i11;
+    input fabric_llpp2_rid_s_i12;
+    input fabric_llpp2_rid_s_i2;
+    input fabric_llpp2_rid_s_i3;
+    input fabric_llpp2_rid_s_i4;
+    input fabric_llpp2_rid_s_i5;
+    input fabric_llpp2_rid_s_i6;
+    input fabric_llpp2_rid_s_i7;
+    input fabric_llpp2_rid_s_i8;
+    input fabric_llpp2_rid_s_i9;
+    input fabric_llpp2_rlast_s_i;
+    output fabric_llpp2_rready_s_o;
+    input fabric_llpp2_rresp_s_i1;
+    input fabric_llpp2_rresp_s_i2;
+    input fabric_llpp2_rvalid_s_i;
+    output fabric_llpp2_wdata_s_o1;
+    output fabric_llpp2_wdata_s_o10;
+    output fabric_llpp2_wdata_s_o11;
+    output fabric_llpp2_wdata_s_o12;
+    output fabric_llpp2_wdata_s_o13;
+    output fabric_llpp2_wdata_s_o14;
+    output fabric_llpp2_wdata_s_o15;
+    output fabric_llpp2_wdata_s_o16;
+    output fabric_llpp2_wdata_s_o17;
+    output fabric_llpp2_wdata_s_o18;
+    output fabric_llpp2_wdata_s_o19;
+    output fabric_llpp2_wdata_s_o2;
+    output fabric_llpp2_wdata_s_o20;
+    output fabric_llpp2_wdata_s_o21;
+    output fabric_llpp2_wdata_s_o22;
+    output fabric_llpp2_wdata_s_o23;
+    output fabric_llpp2_wdata_s_o24;
+    output fabric_llpp2_wdata_s_o25;
+    output fabric_llpp2_wdata_s_o26;
+    output fabric_llpp2_wdata_s_o27;
+    output fabric_llpp2_wdata_s_o28;
+    output fabric_llpp2_wdata_s_o29;
+    output fabric_llpp2_wdata_s_o3;
+    output fabric_llpp2_wdata_s_o30;
+    output fabric_llpp2_wdata_s_o31;
+    output fabric_llpp2_wdata_s_o32;
+    output fabric_llpp2_wdata_s_o4;
+    output fabric_llpp2_wdata_s_o5;
+    output fabric_llpp2_wdata_s_o6;
+    output fabric_llpp2_wdata_s_o7;
+    output fabric_llpp2_wdata_s_o8;
+    output fabric_llpp2_wdata_s_o9;
+    output fabric_llpp2_wlast_s_o;
+    input fabric_llpp2_wready_s_i;
+    output fabric_llpp2_wstrb_s_o1;
+    output fabric_llpp2_wstrb_s_o2;
+    output fabric_llpp2_wstrb_s_o3;
+    output fabric_llpp2_wstrb_s_o4;
+    output fabric_llpp2_wvalid_s_o;
+    output fabric_llpp3_araddr_s_o1;
+    output fabric_llpp3_araddr_s_o10;
+    output fabric_llpp3_araddr_s_o11;
+    output fabric_llpp3_araddr_s_o12;
+    output fabric_llpp3_araddr_s_o13;
+    output fabric_llpp3_araddr_s_o14;
+    output fabric_llpp3_araddr_s_o15;
+    output fabric_llpp3_araddr_s_o16;
+    output fabric_llpp3_araddr_s_o17;
+    output fabric_llpp3_araddr_s_o18;
+    output fabric_llpp3_araddr_s_o19;
+    output fabric_llpp3_araddr_s_o2;
+    output fabric_llpp3_araddr_s_o20;
+    output fabric_llpp3_araddr_s_o21;
+    output fabric_llpp3_araddr_s_o22;
+    output fabric_llpp3_araddr_s_o23;
+    output fabric_llpp3_araddr_s_o24;
+    output fabric_llpp3_araddr_s_o25;
+    output fabric_llpp3_araddr_s_o26;
+    output fabric_llpp3_araddr_s_o27;
+    output fabric_llpp3_araddr_s_o28;
+    output fabric_llpp3_araddr_s_o29;
+    output fabric_llpp3_araddr_s_o3;
+    output fabric_llpp3_araddr_s_o30;
+    output fabric_llpp3_araddr_s_o31;
+    output fabric_llpp3_araddr_s_o32;
+    output fabric_llpp3_araddr_s_o4;
+    output fabric_llpp3_araddr_s_o5;
+    output fabric_llpp3_araddr_s_o6;
+    output fabric_llpp3_araddr_s_o7;
+    output fabric_llpp3_araddr_s_o8;
+    output fabric_llpp3_araddr_s_o9;
+    output fabric_llpp3_arburst_s_o1;
+    output fabric_llpp3_arburst_s_o2;
+    output fabric_llpp3_arcache_s_o1;
+    output fabric_llpp3_arcache_s_o2;
+    output fabric_llpp3_arcache_s_o3;
+    output fabric_llpp3_arcache_s_o4;
+    output fabric_llpp3_arid_s_o1;
+    output fabric_llpp3_arid_s_o10;
+    output fabric_llpp3_arid_s_o11;
+    output fabric_llpp3_arid_s_o12;
+    output fabric_llpp3_arid_s_o2;
+    output fabric_llpp3_arid_s_o3;
+    output fabric_llpp3_arid_s_o4;
+    output fabric_llpp3_arid_s_o5;
+    output fabric_llpp3_arid_s_o6;
+    output fabric_llpp3_arid_s_o7;
+    output fabric_llpp3_arid_s_o8;
+    output fabric_llpp3_arid_s_o9;
+    output fabric_llpp3_arlen_s_o1;
+    output fabric_llpp3_arlen_s_o2;
+    output fabric_llpp3_arlen_s_o3;
+    output fabric_llpp3_arlen_s_o4;
+    output fabric_llpp3_arlen_s_o5;
+    output fabric_llpp3_arlen_s_o6;
+    output fabric_llpp3_arlen_s_o7;
+    output fabric_llpp3_arlen_s_o8;
+    output fabric_llpp3_arlock_s_o;
+    output fabric_llpp3_arprot_s_o1;
+    output fabric_llpp3_arprot_s_o2;
+    output fabric_llpp3_arprot_s_o3;
+    output fabric_llpp3_arqos_s_o1;
+    output fabric_llpp3_arqos_s_o2;
+    output fabric_llpp3_arqos_s_o3;
+    output fabric_llpp3_arqos_s_o4;
+    input fabric_llpp3_arready_s_i;
+    output fabric_llpp3_arsize_s_o1;
+    output fabric_llpp3_arsize_s_o2;
+    output fabric_llpp3_arsize_s_o3;
+    output fabric_llpp3_arvalid_s_o;
+    output fabric_llpp3_awaddr_s_o1;
+    output fabric_llpp3_awaddr_s_o10;
+    output fabric_llpp3_awaddr_s_o11;
+    output fabric_llpp3_awaddr_s_o12;
+    output fabric_llpp3_awaddr_s_o13;
+    output fabric_llpp3_awaddr_s_o14;
+    output fabric_llpp3_awaddr_s_o15;
+    output fabric_llpp3_awaddr_s_o16;
+    output fabric_llpp3_awaddr_s_o17;
+    output fabric_llpp3_awaddr_s_o18;
+    output fabric_llpp3_awaddr_s_o19;
+    output fabric_llpp3_awaddr_s_o2;
+    output fabric_llpp3_awaddr_s_o20;
+    output fabric_llpp3_awaddr_s_o21;
+    output fabric_llpp3_awaddr_s_o22;
+    output fabric_llpp3_awaddr_s_o23;
+    output fabric_llpp3_awaddr_s_o24;
+    output fabric_llpp3_awaddr_s_o25;
+    output fabric_llpp3_awaddr_s_o26;
+    output fabric_llpp3_awaddr_s_o27;
+    output fabric_llpp3_awaddr_s_o28;
+    output fabric_llpp3_awaddr_s_o29;
+    output fabric_llpp3_awaddr_s_o3;
+    output fabric_llpp3_awaddr_s_o30;
+    output fabric_llpp3_awaddr_s_o31;
+    output fabric_llpp3_awaddr_s_o32;
+    output fabric_llpp3_awaddr_s_o4;
+    output fabric_llpp3_awaddr_s_o5;
+    output fabric_llpp3_awaddr_s_o6;
+    output fabric_llpp3_awaddr_s_o7;
+    output fabric_llpp3_awaddr_s_o8;
+    output fabric_llpp3_awaddr_s_o9;
+    output fabric_llpp3_awburst_s_o1;
+    output fabric_llpp3_awburst_s_o2;
+    output fabric_llpp3_awcache_s_o1;
+    output fabric_llpp3_awcache_s_o2;
+    output fabric_llpp3_awcache_s_o3;
+    output fabric_llpp3_awcache_s_o4;
+    output fabric_llpp3_awid_s_o1;
+    output fabric_llpp3_awid_s_o10;
+    output fabric_llpp3_awid_s_o11;
+    output fabric_llpp3_awid_s_o12;
+    output fabric_llpp3_awid_s_o2;
+    output fabric_llpp3_awid_s_o3;
+    output fabric_llpp3_awid_s_o4;
+    output fabric_llpp3_awid_s_o5;
+    output fabric_llpp3_awid_s_o6;
+    output fabric_llpp3_awid_s_o7;
+    output fabric_llpp3_awid_s_o8;
+    output fabric_llpp3_awid_s_o9;
+    output fabric_llpp3_awlen_s_o1;
+    output fabric_llpp3_awlen_s_o2;
+    output fabric_llpp3_awlen_s_o3;
+    output fabric_llpp3_awlen_s_o4;
+    output fabric_llpp3_awlen_s_o5;
+    output fabric_llpp3_awlen_s_o6;
+    output fabric_llpp3_awlen_s_o7;
+    output fabric_llpp3_awlen_s_o8;
+    output fabric_llpp3_awlock_s_o;
+    output fabric_llpp3_awprot_s_o1;
+    output fabric_llpp3_awprot_s_o2;
+    output fabric_llpp3_awprot_s_o3;
+    output fabric_llpp3_awqos_s_o1;
+    output fabric_llpp3_awqos_s_o2;
+    output fabric_llpp3_awqos_s_o3;
+    output fabric_llpp3_awqos_s_o4;
+    input fabric_llpp3_awready_s_i;
+    output fabric_llpp3_awsize_s_o1;
+    output fabric_llpp3_awsize_s_o2;
+    output fabric_llpp3_awsize_s_o3;
+    output fabric_llpp3_awvalid_s_o;
+    input fabric_llpp3_bid_s_i1;
+    input fabric_llpp3_bid_s_i10;
+    input fabric_llpp3_bid_s_i11;
+    input fabric_llpp3_bid_s_i12;
+    input fabric_llpp3_bid_s_i2;
+    input fabric_llpp3_bid_s_i3;
+    input fabric_llpp3_bid_s_i4;
+    input fabric_llpp3_bid_s_i5;
+    input fabric_llpp3_bid_s_i6;
+    input fabric_llpp3_bid_s_i7;
+    input fabric_llpp3_bid_s_i8;
+    input fabric_llpp3_bid_s_i9;
+    output fabric_llpp3_bready_s_o;
+    input fabric_llpp3_bresp_s_i1;
+    input fabric_llpp3_bresp_s_i2;
+    input fabric_llpp3_bvalid_s_i;
+    input fabric_llpp3_rdata_s_i1;
+    input fabric_llpp3_rdata_s_i10;
+    input fabric_llpp3_rdata_s_i11;
+    input fabric_llpp3_rdata_s_i12;
+    input fabric_llpp3_rdata_s_i13;
+    input fabric_llpp3_rdata_s_i14;
+    input fabric_llpp3_rdata_s_i15;
+    input fabric_llpp3_rdata_s_i16;
+    input fabric_llpp3_rdata_s_i17;
+    input fabric_llpp3_rdata_s_i18;
+    input fabric_llpp3_rdata_s_i19;
+    input fabric_llpp3_rdata_s_i2;
+    input fabric_llpp3_rdata_s_i20;
+    input fabric_llpp3_rdata_s_i21;
+    input fabric_llpp3_rdata_s_i22;
+    input fabric_llpp3_rdata_s_i23;
+    input fabric_llpp3_rdata_s_i24;
+    input fabric_llpp3_rdata_s_i25;
+    input fabric_llpp3_rdata_s_i26;
+    input fabric_llpp3_rdata_s_i27;
+    input fabric_llpp3_rdata_s_i28;
+    input fabric_llpp3_rdata_s_i29;
+    input fabric_llpp3_rdata_s_i3;
+    input fabric_llpp3_rdata_s_i30;
+    input fabric_llpp3_rdata_s_i31;
+    input fabric_llpp3_rdata_s_i32;
+    input fabric_llpp3_rdata_s_i4;
+    input fabric_llpp3_rdata_s_i5;
+    input fabric_llpp3_rdata_s_i6;
+    input fabric_llpp3_rdata_s_i7;
+    input fabric_llpp3_rdata_s_i8;
+    input fabric_llpp3_rdata_s_i9;
+    input fabric_llpp3_rid_s_i1;
+    input fabric_llpp3_rid_s_i10;
+    input fabric_llpp3_rid_s_i11;
+    input fabric_llpp3_rid_s_i12;
+    input fabric_llpp3_rid_s_i2;
+    input fabric_llpp3_rid_s_i3;
+    input fabric_llpp3_rid_s_i4;
+    input fabric_llpp3_rid_s_i5;
+    input fabric_llpp3_rid_s_i6;
+    input fabric_llpp3_rid_s_i7;
+    input fabric_llpp3_rid_s_i8;
+    input fabric_llpp3_rid_s_i9;
+    input fabric_llpp3_rlast_s_i;
+    output fabric_llpp3_rready_s_o;
+    input fabric_llpp3_rresp_s_i1;
+    input fabric_llpp3_rresp_s_i2;
+    input fabric_llpp3_rvalid_s_i;
+    output fabric_llpp3_wdata_s_o1;
+    output fabric_llpp3_wdata_s_o10;
+    output fabric_llpp3_wdata_s_o11;
+    output fabric_llpp3_wdata_s_o12;
+    output fabric_llpp3_wdata_s_o13;
+    output fabric_llpp3_wdata_s_o14;
+    output fabric_llpp3_wdata_s_o15;
+    output fabric_llpp3_wdata_s_o16;
+    output fabric_llpp3_wdata_s_o17;
+    output fabric_llpp3_wdata_s_o18;
+    output fabric_llpp3_wdata_s_o19;
+    output fabric_llpp3_wdata_s_o2;
+    output fabric_llpp3_wdata_s_o20;
+    output fabric_llpp3_wdata_s_o21;
+    output fabric_llpp3_wdata_s_o22;
+    output fabric_llpp3_wdata_s_o23;
+    output fabric_llpp3_wdata_s_o24;
+    output fabric_llpp3_wdata_s_o25;
+    output fabric_llpp3_wdata_s_o26;
+    output fabric_llpp3_wdata_s_o27;
+    output fabric_llpp3_wdata_s_o28;
+    output fabric_llpp3_wdata_s_o29;
+    output fabric_llpp3_wdata_s_o3;
+    output fabric_llpp3_wdata_s_o30;
+    output fabric_llpp3_wdata_s_o31;
+    output fabric_llpp3_wdata_s_o32;
+    output fabric_llpp3_wdata_s_o4;
+    output fabric_llpp3_wdata_s_o5;
+    output fabric_llpp3_wdata_s_o6;
+    output fabric_llpp3_wdata_s_o7;
+    output fabric_llpp3_wdata_s_o8;
+    output fabric_llpp3_wdata_s_o9;
+    output fabric_llpp3_wlast_s_o;
+    input fabric_llpp3_wready_s_i;
+    output fabric_llpp3_wstrb_s_o1;
+    output fabric_llpp3_wstrb_s_o2;
+    output fabric_llpp3_wstrb_s_o3;
+    output fabric_llpp3_wstrb_s_o4;
+    output fabric_llpp3_wvalid_s_o;
+    input fabric_lowskew_i10;
+    input fabric_lowskew_i11;
+    input fabric_lowskew_i12;
+    input fabric_lowskew_i13;
+    input fabric_lowskew_i14;
+    input fabric_lowskew_i15;
+    input fabric_lowskew_i16;
+    input fabric_lowskew_i17;
+    input fabric_lowskew_i18;
+    input fabric_lowskew_i19;
+    input fabric_lowskew_i3;
+    input fabric_lowskew_i4;
+    input fabric_lowskew_i5;
+    input fabric_lowskew_i6;
+    input fabric_lowskew_i7;
+    input fabric_lowskew_i8;
+    input fabric_lowskew_i9;
+    output fabric_lowskew_o1;
+    output fabric_lowskew_o2;
+    input fabric_qos_ppaddr_i1;
+    input fabric_qos_ppaddr_i10;
+    input fabric_qos_ppaddr_i11;
+    input fabric_qos_ppaddr_i12;
+    input fabric_qos_ppaddr_i13;
+    input fabric_qos_ppaddr_i14;
+    input fabric_qos_ppaddr_i15;
+    input fabric_qos_ppaddr_i16;
+    input fabric_qos_ppaddr_i17;
+    input fabric_qos_ppaddr_i18;
+    input fabric_qos_ppaddr_i19;
+    input fabric_qos_ppaddr_i2;
+    input fabric_qos_ppaddr_i20;
+    input fabric_qos_ppaddr_i21;
+    input fabric_qos_ppaddr_i22;
+    input fabric_qos_ppaddr_i23;
+    input fabric_qos_ppaddr_i24;
+    input fabric_qos_ppaddr_i25;
+    input fabric_qos_ppaddr_i26;
+    input fabric_qos_ppaddr_i27;
+    input fabric_qos_ppaddr_i28;
+    input fabric_qos_ppaddr_i29;
+    input fabric_qos_ppaddr_i3;
+    input fabric_qos_ppaddr_i30;
+    input fabric_qos_ppaddr_i31;
+    input fabric_qos_ppaddr_i32;
+    input fabric_qos_ppaddr_i4;
+    input fabric_qos_ppaddr_i5;
+    input fabric_qos_ppaddr_i6;
+    input fabric_qos_ppaddr_i7;
+    input fabric_qos_ppaddr_i8;
+    input fabric_qos_ppaddr_i9;
+    input fabric_qos_ppenable_i;
+    output fabric_qos_pprdata_o1;
+    output fabric_qos_pprdata_o10;
+    output fabric_qos_pprdata_o11;
+    output fabric_qos_pprdata_o12;
+    output fabric_qos_pprdata_o13;
+    output fabric_qos_pprdata_o14;
+    output fabric_qos_pprdata_o15;
+    output fabric_qos_pprdata_o16;
+    output fabric_qos_pprdata_o17;
+    output fabric_qos_pprdata_o18;
+    output fabric_qos_pprdata_o19;
+    output fabric_qos_pprdata_o2;
+    output fabric_qos_pprdata_o20;
+    output fabric_qos_pprdata_o21;
+    output fabric_qos_pprdata_o22;
+    output fabric_qos_pprdata_o23;
+    output fabric_qos_pprdata_o24;
+    output fabric_qos_pprdata_o25;
+    output fabric_qos_pprdata_o26;
+    output fabric_qos_pprdata_o27;
+    output fabric_qos_pprdata_o28;
+    output fabric_qos_pprdata_o29;
+    output fabric_qos_pprdata_o3;
+    output fabric_qos_pprdata_o30;
+    output fabric_qos_pprdata_o31;
+    output fabric_qos_pprdata_o32;
+    output fabric_qos_pprdata_o4;
+    output fabric_qos_pprdata_o5;
+    output fabric_qos_pprdata_o6;
+    output fabric_qos_pprdata_o7;
+    output fabric_qos_pprdata_o8;
+    output fabric_qos_pprdata_o9;
+    output fabric_qos_ppready_o;
+    output fabric_qos_ppslverr_o;
+    input fabric_qos_ppwdata_i1;
+    input fabric_qos_ppwdata_i10;
+    input fabric_qos_ppwdata_i11;
+    input fabric_qos_ppwdata_i12;
+    input fabric_qos_ppwdata_i13;
+    input fabric_qos_ppwdata_i14;
+    input fabric_qos_ppwdata_i15;
+    input fabric_qos_ppwdata_i16;
+    input fabric_qos_ppwdata_i17;
+    input fabric_qos_ppwdata_i18;
+    input fabric_qos_ppwdata_i19;
+    input fabric_qos_ppwdata_i2;
+    input fabric_qos_ppwdata_i20;
+    input fabric_qos_ppwdata_i21;
+    input fabric_qos_ppwdata_i22;
+    input fabric_qos_ppwdata_i23;
+    input fabric_qos_ppwdata_i24;
+    input fabric_qos_ppwdata_i25;
+    input fabric_qos_ppwdata_i26;
+    input fabric_qos_ppwdata_i27;
+    input fabric_qos_ppwdata_i28;
+    input fabric_qos_ppwdata_i29;
+    input fabric_qos_ppwdata_i3;
+    input fabric_qos_ppwdata_i30;
+    input fabric_qos_ppwdata_i31;
+    input fabric_qos_ppwdata_i32;
+    input fabric_qos_ppwdata_i4;
+    input fabric_qos_ppwdata_i5;
+    input fabric_qos_ppwdata_i6;
+    input fabric_qos_ppwdata_i7;
+    input fabric_qos_ppwdata_i8;
+    input fabric_qos_ppwdata_i9;
+    input fabric_qos_ppwrite_i;
+    input fabric_qos_presetn_i;
+    input fabric_qos_psel_i;
+    output fabric_soc_mon_sensor_alarm_o;
+    output fabric_spw_interrupts_o1;
+    output fabric_spw_interrupts_o2;
+    output fabric_spw_interrupts_o3;
+    output fabric_spw_interrupts_toggle_o1;
+    output fabric_spw_interrupts_toggle_o2;
+    output fabric_spw_interrupts_toggle_o3;
+    input fabric_sysc_hold_on_debug_i;
+    output fabric_tnd_fpga_apb_master_paddr_o1;
+    output fabric_tnd_fpga_apb_master_paddr_o10;
+    output fabric_tnd_fpga_apb_master_paddr_o11;
+    output fabric_tnd_fpga_apb_master_paddr_o12;
+    output fabric_tnd_fpga_apb_master_paddr_o13;
+    output fabric_tnd_fpga_apb_master_paddr_o14;
+    output fabric_tnd_fpga_apb_master_paddr_o15;
+    output fabric_tnd_fpga_apb_master_paddr_o16;
+    output fabric_tnd_fpga_apb_master_paddr_o17;
+    output fabric_tnd_fpga_apb_master_paddr_o18;
+    output fabric_tnd_fpga_apb_master_paddr_o19;
+    output fabric_tnd_fpga_apb_master_paddr_o2;
+    output fabric_tnd_fpga_apb_master_paddr_o20;
+    output fabric_tnd_fpga_apb_master_paddr_o21;
+    output fabric_tnd_fpga_apb_master_paddr_o22;
+    output fabric_tnd_fpga_apb_master_paddr_o23;
+    output fabric_tnd_fpga_apb_master_paddr_o24;
+    output fabric_tnd_fpga_apb_master_paddr_o25;
+    output fabric_tnd_fpga_apb_master_paddr_o26;
+    output fabric_tnd_fpga_apb_master_paddr_o27;
+    output fabric_tnd_fpga_apb_master_paddr_o28;
+    output fabric_tnd_fpga_apb_master_paddr_o29;
+    output fabric_tnd_fpga_apb_master_paddr_o3;
+    output fabric_tnd_fpga_apb_master_paddr_o30;
+    output fabric_tnd_fpga_apb_master_paddr_o31;
+    output fabric_tnd_fpga_apb_master_paddr_o32;
+    output fabric_tnd_fpga_apb_master_paddr_o4;
+    output fabric_tnd_fpga_apb_master_paddr_o5;
+    output fabric_tnd_fpga_apb_master_paddr_o6;
+    output fabric_tnd_fpga_apb_master_paddr_o7;
+    output fabric_tnd_fpga_apb_master_paddr_o8;
+    output fabric_tnd_fpga_apb_master_paddr_o9;
+    output fabric_tnd_fpga_apb_master_penable_o;
+    input fabric_tnd_fpga_apb_master_prdata_i1;
+    input fabric_tnd_fpga_apb_master_prdata_i10;
+    input fabric_tnd_fpga_apb_master_prdata_i11;
+    input fabric_tnd_fpga_apb_master_prdata_i12;
+    input fabric_tnd_fpga_apb_master_prdata_i13;
+    input fabric_tnd_fpga_apb_master_prdata_i14;
+    input fabric_tnd_fpga_apb_master_prdata_i15;
+    input fabric_tnd_fpga_apb_master_prdata_i16;
+    input fabric_tnd_fpga_apb_master_prdata_i17;
+    input fabric_tnd_fpga_apb_master_prdata_i18;
+    input fabric_tnd_fpga_apb_master_prdata_i19;
+    input fabric_tnd_fpga_apb_master_prdata_i2;
+    input fabric_tnd_fpga_apb_master_prdata_i20;
+    input fabric_tnd_fpga_apb_master_prdata_i21;
+    input fabric_tnd_fpga_apb_master_prdata_i22;
+    input fabric_tnd_fpga_apb_master_prdata_i23;
+    input fabric_tnd_fpga_apb_master_prdata_i24;
+    input fabric_tnd_fpga_apb_master_prdata_i25;
+    input fabric_tnd_fpga_apb_master_prdata_i26;
+    input fabric_tnd_fpga_apb_master_prdata_i27;
+    input fabric_tnd_fpga_apb_master_prdata_i28;
+    input fabric_tnd_fpga_apb_master_prdata_i29;
+    input fabric_tnd_fpga_apb_master_prdata_i3;
+    input fabric_tnd_fpga_apb_master_prdata_i30;
+    input fabric_tnd_fpga_apb_master_prdata_i31;
+    input fabric_tnd_fpga_apb_master_prdata_i32;
+    input fabric_tnd_fpga_apb_master_prdata_i4;
+    input fabric_tnd_fpga_apb_master_prdata_i5;
+    input fabric_tnd_fpga_apb_master_prdata_i6;
+    input fabric_tnd_fpga_apb_master_prdata_i7;
+    input fabric_tnd_fpga_apb_master_prdata_i8;
+    input fabric_tnd_fpga_apb_master_prdata_i9;
+    input fabric_tnd_fpga_apb_master_pready_i;
+    output fabric_tnd_fpga_apb_master_psel_o;
+    input fabric_tnd_fpga_apb_master_pslverr_i;
+    output fabric_tnd_fpga_apb_master_pwdata_o1;
+    output fabric_tnd_fpga_apb_master_pwdata_o10;
+    output fabric_tnd_fpga_apb_master_pwdata_o11;
+    output fabric_tnd_fpga_apb_master_pwdata_o12;
+    output fabric_tnd_fpga_apb_master_pwdata_o13;
+    output fabric_tnd_fpga_apb_master_pwdata_o14;
+    output fabric_tnd_fpga_apb_master_pwdata_o15;
+    output fabric_tnd_fpga_apb_master_pwdata_o16;
+    output fabric_tnd_fpga_apb_master_pwdata_o17;
+    output fabric_tnd_fpga_apb_master_pwdata_o18;
+    output fabric_tnd_fpga_apb_master_pwdata_o19;
+    output fabric_tnd_fpga_apb_master_pwdata_o2;
+    output fabric_tnd_fpga_apb_master_pwdata_o20;
+    output fabric_tnd_fpga_apb_master_pwdata_o21;
+    output fabric_tnd_fpga_apb_master_pwdata_o22;
+    output fabric_tnd_fpga_apb_master_pwdata_o23;
+    output fabric_tnd_fpga_apb_master_pwdata_o24;
+    output fabric_tnd_fpga_apb_master_pwdata_o25;
+    output fabric_tnd_fpga_apb_master_pwdata_o26;
+    output fabric_tnd_fpga_apb_master_pwdata_o27;
+    output fabric_tnd_fpga_apb_master_pwdata_o28;
+    output fabric_tnd_fpga_apb_master_pwdata_o29;
+    output fabric_tnd_fpga_apb_master_pwdata_o3;
+    output fabric_tnd_fpga_apb_master_pwdata_o30;
+    output fabric_tnd_fpga_apb_master_pwdata_o31;
+    output fabric_tnd_fpga_apb_master_pwdata_o32;
+    output fabric_tnd_fpga_apb_master_pwdata_o4;
+    output fabric_tnd_fpga_apb_master_pwdata_o5;
+    output fabric_tnd_fpga_apb_master_pwdata_o6;
+    output fabric_tnd_fpga_apb_master_pwdata_o7;
+    output fabric_tnd_fpga_apb_master_pwdata_o8;
+    output fabric_tnd_fpga_apb_master_pwdata_o9;
+    output fabric_tnd_fpga_apb_master_pwrite_o;
+    input fabric_tnd_fpga_atb_master_afready_i;
+    output fabric_tnd_fpga_atb_master_afvalid_o;
+    input fabric_tnd_fpga_atb_master_atbytes_i1;
+    input fabric_tnd_fpga_atb_master_atbytes_i2;
+    input fabric_tnd_fpga_atb_master_atbytes_i3;
+    input fabric_tnd_fpga_atb_master_atbytes_i4;
+    input fabric_tnd_fpga_atb_master_atdata_i1;
+    input fabric_tnd_fpga_atb_master_atdata_i10;
+    input fabric_tnd_fpga_atb_master_atdata_i100;
+    input fabric_tnd_fpga_atb_master_atdata_i101;
+    input fabric_tnd_fpga_atb_master_atdata_i102;
+    input fabric_tnd_fpga_atb_master_atdata_i103;
+    input fabric_tnd_fpga_atb_master_atdata_i104;
+    input fabric_tnd_fpga_atb_master_atdata_i105;
+    input fabric_tnd_fpga_atb_master_atdata_i106;
+    input fabric_tnd_fpga_atb_master_atdata_i107;
+    input fabric_tnd_fpga_atb_master_atdata_i108;
+    input fabric_tnd_fpga_atb_master_atdata_i109;
+    input fabric_tnd_fpga_atb_master_atdata_i11;
+    input fabric_tnd_fpga_atb_master_atdata_i110;
+    input fabric_tnd_fpga_atb_master_atdata_i111;
+    input fabric_tnd_fpga_atb_master_atdata_i112;
+    input fabric_tnd_fpga_atb_master_atdata_i113;
+    input fabric_tnd_fpga_atb_master_atdata_i114;
+    input fabric_tnd_fpga_atb_master_atdata_i115;
+    input fabric_tnd_fpga_atb_master_atdata_i116;
+    input fabric_tnd_fpga_atb_master_atdata_i117;
+    input fabric_tnd_fpga_atb_master_atdata_i118;
+    input fabric_tnd_fpga_atb_master_atdata_i119;
+    input fabric_tnd_fpga_atb_master_atdata_i12;
+    input fabric_tnd_fpga_atb_master_atdata_i120;
+    input fabric_tnd_fpga_atb_master_atdata_i121;
+    input fabric_tnd_fpga_atb_master_atdata_i122;
+    input fabric_tnd_fpga_atb_master_atdata_i123;
+    input fabric_tnd_fpga_atb_master_atdata_i124;
+    input fabric_tnd_fpga_atb_master_atdata_i125;
+    input fabric_tnd_fpga_atb_master_atdata_i126;
+    input fabric_tnd_fpga_atb_master_atdata_i127;
+    input fabric_tnd_fpga_atb_master_atdata_i128;
+    input fabric_tnd_fpga_atb_master_atdata_i13;
+    input fabric_tnd_fpga_atb_master_atdata_i14;
+    input fabric_tnd_fpga_atb_master_atdata_i15;
+    input fabric_tnd_fpga_atb_master_atdata_i16;
+    input fabric_tnd_fpga_atb_master_atdata_i17;
+    input fabric_tnd_fpga_atb_master_atdata_i18;
+    input fabric_tnd_fpga_atb_master_atdata_i19;
+    input fabric_tnd_fpga_atb_master_atdata_i2;
+    input fabric_tnd_fpga_atb_master_atdata_i20;
+    input fabric_tnd_fpga_atb_master_atdata_i21;
+    input fabric_tnd_fpga_atb_master_atdata_i22;
+    input fabric_tnd_fpga_atb_master_atdata_i23;
+    input fabric_tnd_fpga_atb_master_atdata_i24;
+    input fabric_tnd_fpga_atb_master_atdata_i25;
+    input fabric_tnd_fpga_atb_master_atdata_i26;
+    input fabric_tnd_fpga_atb_master_atdata_i27;
+    input fabric_tnd_fpga_atb_master_atdata_i28;
+    input fabric_tnd_fpga_atb_master_atdata_i29;
+    input fabric_tnd_fpga_atb_master_atdata_i3;
+    input fabric_tnd_fpga_atb_master_atdata_i30;
+    input fabric_tnd_fpga_atb_master_atdata_i31;
+    input fabric_tnd_fpga_atb_master_atdata_i32;
+    input fabric_tnd_fpga_atb_master_atdata_i33;
+    input fabric_tnd_fpga_atb_master_atdata_i34;
+    input fabric_tnd_fpga_atb_master_atdata_i35;
+    input fabric_tnd_fpga_atb_master_atdata_i36;
+    input fabric_tnd_fpga_atb_master_atdata_i37;
+    input fabric_tnd_fpga_atb_master_atdata_i38;
+    input fabric_tnd_fpga_atb_master_atdata_i39;
+    input fabric_tnd_fpga_atb_master_atdata_i4;
+    input fabric_tnd_fpga_atb_master_atdata_i40;
+    input fabric_tnd_fpga_atb_master_atdata_i41;
+    input fabric_tnd_fpga_atb_master_atdata_i42;
+    input fabric_tnd_fpga_atb_master_atdata_i43;
+    input fabric_tnd_fpga_atb_master_atdata_i44;
+    input fabric_tnd_fpga_atb_master_atdata_i45;
+    input fabric_tnd_fpga_atb_master_atdata_i46;
+    input fabric_tnd_fpga_atb_master_atdata_i47;
+    input fabric_tnd_fpga_atb_master_atdata_i48;
+    input fabric_tnd_fpga_atb_master_atdata_i49;
+    input fabric_tnd_fpga_atb_master_atdata_i5;
+    input fabric_tnd_fpga_atb_master_atdata_i50;
+    input fabric_tnd_fpga_atb_master_atdata_i51;
+    input fabric_tnd_fpga_atb_master_atdata_i52;
+    input fabric_tnd_fpga_atb_master_atdata_i53;
+    input fabric_tnd_fpga_atb_master_atdata_i54;
+    input fabric_tnd_fpga_atb_master_atdata_i55;
+    input fabric_tnd_fpga_atb_master_atdata_i56;
+    input fabric_tnd_fpga_atb_master_atdata_i57;
+    input fabric_tnd_fpga_atb_master_atdata_i58;
+    input fabric_tnd_fpga_atb_master_atdata_i59;
+    input fabric_tnd_fpga_atb_master_atdata_i6;
+    input fabric_tnd_fpga_atb_master_atdata_i60;
+    input fabric_tnd_fpga_atb_master_atdata_i61;
+    input fabric_tnd_fpga_atb_master_atdata_i62;
+    input fabric_tnd_fpga_atb_master_atdata_i63;
+    input fabric_tnd_fpga_atb_master_atdata_i64;
+    input fabric_tnd_fpga_atb_master_atdata_i65;
+    input fabric_tnd_fpga_atb_master_atdata_i66;
+    input fabric_tnd_fpga_atb_master_atdata_i67;
+    input fabric_tnd_fpga_atb_master_atdata_i68;
+    input fabric_tnd_fpga_atb_master_atdata_i69;
+    input fabric_tnd_fpga_atb_master_atdata_i7;
+    input fabric_tnd_fpga_atb_master_atdata_i70;
+    input fabric_tnd_fpga_atb_master_atdata_i71;
+    input fabric_tnd_fpga_atb_master_atdata_i72;
+    input fabric_tnd_fpga_atb_master_atdata_i73;
+    input fabric_tnd_fpga_atb_master_atdata_i74;
+    input fabric_tnd_fpga_atb_master_atdata_i75;
+    input fabric_tnd_fpga_atb_master_atdata_i76;
+    input fabric_tnd_fpga_atb_master_atdata_i77;
+    input fabric_tnd_fpga_atb_master_atdata_i78;
+    input fabric_tnd_fpga_atb_master_atdata_i79;
+    input fabric_tnd_fpga_atb_master_atdata_i8;
+    input fabric_tnd_fpga_atb_master_atdata_i80;
+    input fabric_tnd_fpga_atb_master_atdata_i81;
+    input fabric_tnd_fpga_atb_master_atdata_i82;
+    input fabric_tnd_fpga_atb_master_atdata_i83;
+    input fabric_tnd_fpga_atb_master_atdata_i84;
+    input fabric_tnd_fpga_atb_master_atdata_i85;
+    input fabric_tnd_fpga_atb_master_atdata_i86;
+    input fabric_tnd_fpga_atb_master_atdata_i87;
+    input fabric_tnd_fpga_atb_master_atdata_i88;
+    input fabric_tnd_fpga_atb_master_atdata_i89;
+    input fabric_tnd_fpga_atb_master_atdata_i9;
+    input fabric_tnd_fpga_atb_master_atdata_i90;
+    input fabric_tnd_fpga_atb_master_atdata_i91;
+    input fabric_tnd_fpga_atb_master_atdata_i92;
+    input fabric_tnd_fpga_atb_master_atdata_i93;
+    input fabric_tnd_fpga_atb_master_atdata_i94;
+    input fabric_tnd_fpga_atb_master_atdata_i95;
+    input fabric_tnd_fpga_atb_master_atdata_i96;
+    input fabric_tnd_fpga_atb_master_atdata_i97;
+    input fabric_tnd_fpga_atb_master_atdata_i98;
+    input fabric_tnd_fpga_atb_master_atdata_i99;
+    input fabric_tnd_fpga_atb_master_atid_i1;
+    input fabric_tnd_fpga_atb_master_atid_i2;
+    input fabric_tnd_fpga_atb_master_atid_i3;
+    input fabric_tnd_fpga_atb_master_atid_i4;
+    input fabric_tnd_fpga_atb_master_atid_i5;
+    input fabric_tnd_fpga_atb_master_atid_i6;
+    input fabric_tnd_fpga_atb_master_atid_i7;
+    output fabric_tnd_fpga_atb_master_atready_o;
+    input fabric_tnd_fpga_atb_master_atvalid_i;
+    output fabric_tnd_fpga_atb_master_syncreq_o;
+    output fabric_tnd_hssl_apb_master_paddr_o1;
+    output fabric_tnd_hssl_apb_master_paddr_o10;
+    output fabric_tnd_hssl_apb_master_paddr_o11;
+    output fabric_tnd_hssl_apb_master_paddr_o12;
+    output fabric_tnd_hssl_apb_master_paddr_o13;
+    output fabric_tnd_hssl_apb_master_paddr_o14;
+    output fabric_tnd_hssl_apb_master_paddr_o15;
+    output fabric_tnd_hssl_apb_master_paddr_o16;
+    output fabric_tnd_hssl_apb_master_paddr_o17;
+    output fabric_tnd_hssl_apb_master_paddr_o18;
+    output fabric_tnd_hssl_apb_master_paddr_o19;
+    output fabric_tnd_hssl_apb_master_paddr_o2;
+    output fabric_tnd_hssl_apb_master_paddr_o20;
+    output fabric_tnd_hssl_apb_master_paddr_o21;
+    output fabric_tnd_hssl_apb_master_paddr_o22;
+    output fabric_tnd_hssl_apb_master_paddr_o23;
+    output fabric_tnd_hssl_apb_master_paddr_o24;
+    output fabric_tnd_hssl_apb_master_paddr_o25;
+    output fabric_tnd_hssl_apb_master_paddr_o26;
+    output fabric_tnd_hssl_apb_master_paddr_o27;
+    output fabric_tnd_hssl_apb_master_paddr_o28;
+    output fabric_tnd_hssl_apb_master_paddr_o29;
+    output fabric_tnd_hssl_apb_master_paddr_o3;
+    output fabric_tnd_hssl_apb_master_paddr_o30;
+    output fabric_tnd_hssl_apb_master_paddr_o31;
+    output fabric_tnd_hssl_apb_master_paddr_o32;
+    output fabric_tnd_hssl_apb_master_paddr_o4;
+    output fabric_tnd_hssl_apb_master_paddr_o5;
+    output fabric_tnd_hssl_apb_master_paddr_o6;
+    output fabric_tnd_hssl_apb_master_paddr_o7;
+    output fabric_tnd_hssl_apb_master_paddr_o8;
+    output fabric_tnd_hssl_apb_master_paddr_o9;
+    output fabric_tnd_hssl_apb_master_penable_o;
+    input fabric_tnd_hssl_apb_master_prdata_i1;
+    input fabric_tnd_hssl_apb_master_prdata_i10;
+    input fabric_tnd_hssl_apb_master_prdata_i11;
+    input fabric_tnd_hssl_apb_master_prdata_i12;
+    input fabric_tnd_hssl_apb_master_prdata_i13;
+    input fabric_tnd_hssl_apb_master_prdata_i14;
+    input fabric_tnd_hssl_apb_master_prdata_i15;
+    input fabric_tnd_hssl_apb_master_prdata_i16;
+    input fabric_tnd_hssl_apb_master_prdata_i17;
+    input fabric_tnd_hssl_apb_master_prdata_i18;
+    input fabric_tnd_hssl_apb_master_prdata_i19;
+    input fabric_tnd_hssl_apb_master_prdata_i2;
+    input fabric_tnd_hssl_apb_master_prdata_i20;
+    input fabric_tnd_hssl_apb_master_prdata_i21;
+    input fabric_tnd_hssl_apb_master_prdata_i22;
+    input fabric_tnd_hssl_apb_master_prdata_i23;
+    input fabric_tnd_hssl_apb_master_prdata_i24;
+    input fabric_tnd_hssl_apb_master_prdata_i25;
+    input fabric_tnd_hssl_apb_master_prdata_i26;
+    input fabric_tnd_hssl_apb_master_prdata_i27;
+    input fabric_tnd_hssl_apb_master_prdata_i28;
+    input fabric_tnd_hssl_apb_master_prdata_i29;
+    input fabric_tnd_hssl_apb_master_prdata_i3;
+    input fabric_tnd_hssl_apb_master_prdata_i30;
+    input fabric_tnd_hssl_apb_master_prdata_i31;
+    input fabric_tnd_hssl_apb_master_prdata_i32;
+    input fabric_tnd_hssl_apb_master_prdata_i4;
+    input fabric_tnd_hssl_apb_master_prdata_i5;
+    input fabric_tnd_hssl_apb_master_prdata_i6;
+    input fabric_tnd_hssl_apb_master_prdata_i7;
+    input fabric_tnd_hssl_apb_master_prdata_i8;
+    input fabric_tnd_hssl_apb_master_prdata_i9;
+    input fabric_tnd_hssl_apb_master_pready_i;
+    output fabric_tnd_hssl_apb_master_psel_o;
+    input fabric_tnd_hssl_apb_master_pslverr_i;
+    output fabric_tnd_hssl_apb_master_pwdata_o1;
+    output fabric_tnd_hssl_apb_master_pwdata_o10;
+    output fabric_tnd_hssl_apb_master_pwdata_o11;
+    output fabric_tnd_hssl_apb_master_pwdata_o12;
+    output fabric_tnd_hssl_apb_master_pwdata_o13;
+    output fabric_tnd_hssl_apb_master_pwdata_o14;
+    output fabric_tnd_hssl_apb_master_pwdata_o15;
+    output fabric_tnd_hssl_apb_master_pwdata_o16;
+    output fabric_tnd_hssl_apb_master_pwdata_o17;
+    output fabric_tnd_hssl_apb_master_pwdata_o18;
+    output fabric_tnd_hssl_apb_master_pwdata_o19;
+    output fabric_tnd_hssl_apb_master_pwdata_o2;
+    output fabric_tnd_hssl_apb_master_pwdata_o20;
+    output fabric_tnd_hssl_apb_master_pwdata_o21;
+    output fabric_tnd_hssl_apb_master_pwdata_o22;
+    output fabric_tnd_hssl_apb_master_pwdata_o23;
+    output fabric_tnd_hssl_apb_master_pwdata_o24;
+    output fabric_tnd_hssl_apb_master_pwdata_o25;
+    output fabric_tnd_hssl_apb_master_pwdata_o26;
+    output fabric_tnd_hssl_apb_master_pwdata_o27;
+    output fabric_tnd_hssl_apb_master_pwdata_o28;
+    output fabric_tnd_hssl_apb_master_pwdata_o29;
+    output fabric_tnd_hssl_apb_master_pwdata_o3;
+    output fabric_tnd_hssl_apb_master_pwdata_o30;
+    output fabric_tnd_hssl_apb_master_pwdata_o31;
+    output fabric_tnd_hssl_apb_master_pwdata_o32;
+    output fabric_tnd_hssl_apb_master_pwdata_o4;
+    output fabric_tnd_hssl_apb_master_pwdata_o5;
+    output fabric_tnd_hssl_apb_master_pwdata_o6;
+    output fabric_tnd_hssl_apb_master_pwdata_o7;
+    output fabric_tnd_hssl_apb_master_pwdata_o8;
+    output fabric_tnd_hssl_apb_master_pwdata_o9;
+    output fabric_tnd_hssl_apb_master_pwrite_o;
+    output fabric_tnd_hssl_atb_master_afready_o;
+    input fabric_tnd_hssl_atb_master_afvalid_i;
+    output fabric_tnd_hssl_atb_master_atbytes_o1;
+    output fabric_tnd_hssl_atb_master_atbytes_o2;
+    output fabric_tnd_hssl_atb_master_atbytes_o3;
+    output fabric_tnd_hssl_atb_master_atbytes_o4;
+    output fabric_tnd_hssl_atb_master_atdata_o1;
+    output fabric_tnd_hssl_atb_master_atdata_o10;
+    output fabric_tnd_hssl_atb_master_atdata_o100;
+    output fabric_tnd_hssl_atb_master_atdata_o101;
+    output fabric_tnd_hssl_atb_master_atdata_o102;
+    output fabric_tnd_hssl_atb_master_atdata_o103;
+    output fabric_tnd_hssl_atb_master_atdata_o104;
+    output fabric_tnd_hssl_atb_master_atdata_o105;
+    output fabric_tnd_hssl_atb_master_atdata_o106;
+    output fabric_tnd_hssl_atb_master_atdata_o107;
+    output fabric_tnd_hssl_atb_master_atdata_o108;
+    output fabric_tnd_hssl_atb_master_atdata_o109;
+    output fabric_tnd_hssl_atb_master_atdata_o11;
+    output fabric_tnd_hssl_atb_master_atdata_o110;
+    output fabric_tnd_hssl_atb_master_atdata_o111;
+    output fabric_tnd_hssl_atb_master_atdata_o112;
+    output fabric_tnd_hssl_atb_master_atdata_o113;
+    output fabric_tnd_hssl_atb_master_atdata_o114;
+    output fabric_tnd_hssl_atb_master_atdata_o115;
+    output fabric_tnd_hssl_atb_master_atdata_o116;
+    output fabric_tnd_hssl_atb_master_atdata_o117;
+    output fabric_tnd_hssl_atb_master_atdata_o118;
+    output fabric_tnd_hssl_atb_master_atdata_o119;
+    output fabric_tnd_hssl_atb_master_atdata_o12;
+    output fabric_tnd_hssl_atb_master_atdata_o120;
+    output fabric_tnd_hssl_atb_master_atdata_o121;
+    output fabric_tnd_hssl_atb_master_atdata_o122;
+    output fabric_tnd_hssl_atb_master_atdata_o123;
+    output fabric_tnd_hssl_atb_master_atdata_o124;
+    output fabric_tnd_hssl_atb_master_atdata_o125;
+    output fabric_tnd_hssl_atb_master_atdata_o126;
+    output fabric_tnd_hssl_atb_master_atdata_o127;
+    output fabric_tnd_hssl_atb_master_atdata_o128;
+    output fabric_tnd_hssl_atb_master_atdata_o13;
+    output fabric_tnd_hssl_atb_master_atdata_o14;
+    output fabric_tnd_hssl_atb_master_atdata_o15;
+    output fabric_tnd_hssl_atb_master_atdata_o16;
+    output fabric_tnd_hssl_atb_master_atdata_o17;
+    output fabric_tnd_hssl_atb_master_atdata_o18;
+    output fabric_tnd_hssl_atb_master_atdata_o19;
+    output fabric_tnd_hssl_atb_master_atdata_o2;
+    output fabric_tnd_hssl_atb_master_atdata_o20;
+    output fabric_tnd_hssl_atb_master_atdata_o21;
+    output fabric_tnd_hssl_atb_master_atdata_o22;
+    output fabric_tnd_hssl_atb_master_atdata_o23;
+    output fabric_tnd_hssl_atb_master_atdata_o24;
+    output fabric_tnd_hssl_atb_master_atdata_o25;
+    output fabric_tnd_hssl_atb_master_atdata_o26;
+    output fabric_tnd_hssl_atb_master_atdata_o27;
+    output fabric_tnd_hssl_atb_master_atdata_o28;
+    output fabric_tnd_hssl_atb_master_atdata_o29;
+    output fabric_tnd_hssl_atb_master_atdata_o3;
+    output fabric_tnd_hssl_atb_master_atdata_o30;
+    output fabric_tnd_hssl_atb_master_atdata_o31;
+    output fabric_tnd_hssl_atb_master_atdata_o32;
+    output fabric_tnd_hssl_atb_master_atdata_o33;
+    output fabric_tnd_hssl_atb_master_atdata_o34;
+    output fabric_tnd_hssl_atb_master_atdata_o35;
+    output fabric_tnd_hssl_atb_master_atdata_o36;
+    output fabric_tnd_hssl_atb_master_atdata_o37;
+    output fabric_tnd_hssl_atb_master_atdata_o38;
+    output fabric_tnd_hssl_atb_master_atdata_o39;
+    output fabric_tnd_hssl_atb_master_atdata_o4;
+    output fabric_tnd_hssl_atb_master_atdata_o40;
+    output fabric_tnd_hssl_atb_master_atdata_o41;
+    output fabric_tnd_hssl_atb_master_atdata_o42;
+    output fabric_tnd_hssl_atb_master_atdata_o43;
+    output fabric_tnd_hssl_atb_master_atdata_o44;
+    output fabric_tnd_hssl_atb_master_atdata_o45;
+    output fabric_tnd_hssl_atb_master_atdata_o46;
+    output fabric_tnd_hssl_atb_master_atdata_o47;
+    output fabric_tnd_hssl_atb_master_atdata_o48;
+    output fabric_tnd_hssl_atb_master_atdata_o49;
+    output fabric_tnd_hssl_atb_master_atdata_o5;
+    output fabric_tnd_hssl_atb_master_atdata_o50;
+    output fabric_tnd_hssl_atb_master_atdata_o51;
+    output fabric_tnd_hssl_atb_master_atdata_o52;
+    output fabric_tnd_hssl_atb_master_atdata_o53;
+    output fabric_tnd_hssl_atb_master_atdata_o54;
+    output fabric_tnd_hssl_atb_master_atdata_o55;
+    output fabric_tnd_hssl_atb_master_atdata_o56;
+    output fabric_tnd_hssl_atb_master_atdata_o57;
+    output fabric_tnd_hssl_atb_master_atdata_o58;
+    output fabric_tnd_hssl_atb_master_atdata_o59;
+    output fabric_tnd_hssl_atb_master_atdata_o6;
+    output fabric_tnd_hssl_atb_master_atdata_o60;
+    output fabric_tnd_hssl_atb_master_atdata_o61;
+    output fabric_tnd_hssl_atb_master_atdata_o62;
+    output fabric_tnd_hssl_atb_master_atdata_o63;
+    output fabric_tnd_hssl_atb_master_atdata_o64;
+    output fabric_tnd_hssl_atb_master_atdata_o65;
+    output fabric_tnd_hssl_atb_master_atdata_o66;
+    output fabric_tnd_hssl_atb_master_atdata_o67;
+    output fabric_tnd_hssl_atb_master_atdata_o68;
+    output fabric_tnd_hssl_atb_master_atdata_o69;
+    output fabric_tnd_hssl_atb_master_atdata_o7;
+    output fabric_tnd_hssl_atb_master_atdata_o70;
+    output fabric_tnd_hssl_atb_master_atdata_o71;
+    output fabric_tnd_hssl_atb_master_atdata_o72;
+    output fabric_tnd_hssl_atb_master_atdata_o73;
+    output fabric_tnd_hssl_atb_master_atdata_o74;
+    output fabric_tnd_hssl_atb_master_atdata_o75;
+    output fabric_tnd_hssl_atb_master_atdata_o76;
+    output fabric_tnd_hssl_atb_master_atdata_o77;
+    output fabric_tnd_hssl_atb_master_atdata_o78;
+    output fabric_tnd_hssl_atb_master_atdata_o79;
+    output fabric_tnd_hssl_atb_master_atdata_o8;
+    output fabric_tnd_hssl_atb_master_atdata_o80;
+    output fabric_tnd_hssl_atb_master_atdata_o81;
+    output fabric_tnd_hssl_atb_master_atdata_o82;
+    output fabric_tnd_hssl_atb_master_atdata_o83;
+    output fabric_tnd_hssl_atb_master_atdata_o84;
+    output fabric_tnd_hssl_atb_master_atdata_o85;
+    output fabric_tnd_hssl_atb_master_atdata_o86;
+    output fabric_tnd_hssl_atb_master_atdata_o87;
+    output fabric_tnd_hssl_atb_master_atdata_o88;
+    output fabric_tnd_hssl_atb_master_atdata_o89;
+    output fabric_tnd_hssl_atb_master_atdata_o9;
+    output fabric_tnd_hssl_atb_master_atdata_o90;
+    output fabric_tnd_hssl_atb_master_atdata_o91;
+    output fabric_tnd_hssl_atb_master_atdata_o92;
+    output fabric_tnd_hssl_atb_master_atdata_o93;
+    output fabric_tnd_hssl_atb_master_atdata_o94;
+    output fabric_tnd_hssl_atb_master_atdata_o95;
+    output fabric_tnd_hssl_atb_master_atdata_o96;
+    output fabric_tnd_hssl_atb_master_atdata_o97;
+    output fabric_tnd_hssl_atb_master_atdata_o98;
+    output fabric_tnd_hssl_atb_master_atdata_o99;
+    output fabric_tnd_hssl_atb_master_atid_o1;
+    output fabric_tnd_hssl_atb_master_atid_o2;
+    output fabric_tnd_hssl_atb_master_atid_o3;
+    output fabric_tnd_hssl_atb_master_atid_o4;
+    output fabric_tnd_hssl_atb_master_atid_o5;
+    output fabric_tnd_hssl_atb_master_atid_o6;
+    output fabric_tnd_hssl_atb_master_atid_o7;
+    input fabric_tnd_hssl_atb_master_atready_i;
+    output fabric_tnd_hssl_atb_master_atvalid_o;
+    input fabric_tnd_hssl_atb_master_syncreq_i;
+    output fabric_tnd_hssl_flushin_o;
+    output fabric_tnd_hssl_trigin_o;
+    output fabric_tnd_trace_clk_traceoutportintf_o;
+    output fabric_tnd_trace_ctl_traceoutportintf_o;
+    output fabric_tnd_trace_data_traceoutportintf_o1;
+    output fabric_tnd_trace_data_traceoutportintf_o10;
+    output fabric_tnd_trace_data_traceoutportintf_o11;
+    output fabric_tnd_trace_data_traceoutportintf_o12;
+    output fabric_tnd_trace_data_traceoutportintf_o13;
+    output fabric_tnd_trace_data_traceoutportintf_o14;
+    output fabric_tnd_trace_data_traceoutportintf_o15;
+    output fabric_tnd_trace_data_traceoutportintf_o16;
+    output fabric_tnd_trace_data_traceoutportintf_o17;
+    output fabric_tnd_trace_data_traceoutportintf_o18;
+    output fabric_tnd_trace_data_traceoutportintf_o19;
+    output fabric_tnd_trace_data_traceoutportintf_o2;
+    output fabric_tnd_trace_data_traceoutportintf_o20;
+    output fabric_tnd_trace_data_traceoutportintf_o21;
+    output fabric_tnd_trace_data_traceoutportintf_o22;
+    output fabric_tnd_trace_data_traceoutportintf_o23;
+    output fabric_tnd_trace_data_traceoutportintf_o24;
+    output fabric_tnd_trace_data_traceoutportintf_o25;
+    output fabric_tnd_trace_data_traceoutportintf_o26;
+    output fabric_tnd_trace_data_traceoutportintf_o27;
+    output fabric_tnd_trace_data_traceoutportintf_o28;
+    output fabric_tnd_trace_data_traceoutportintf_o29;
+    output fabric_tnd_trace_data_traceoutportintf_o3;
+    output fabric_tnd_trace_data_traceoutportintf_o30;
+    output fabric_tnd_trace_data_traceoutportintf_o31;
+    output fabric_tnd_trace_data_traceoutportintf_o32;
+    output fabric_tnd_trace_data_traceoutportintf_o4;
+    output fabric_tnd_trace_data_traceoutportintf_o5;
+    output fabric_tnd_trace_data_traceoutportintf_o6;
+    output fabric_tnd_trace_data_traceoutportintf_o7;
+    output fabric_tnd_trace_data_traceoutportintf_o8;
+    output fabric_tnd_trace_data_traceoutportintf_o9;
+    output fabric_tst_pll_lock_o1;
+    output fabric_tst_pll_lock_o2;
+    output fabric_tst_pll_lock_o3;
+    output fabric_tst_pll_lock_o4;
+    output fabric_tst_pll_lock_o5;
+    output fabric_tst_pll_lock_o6;
+    output fabric_tst_pll_lock_o7;
+    output fabric_tsvalue_tsgen_fpga_o1;
+    output fabric_tsvalue_tsgen_fpga_o10;
+    output fabric_tsvalue_tsgen_fpga_o11;
+    output fabric_tsvalue_tsgen_fpga_o12;
+    output fabric_tsvalue_tsgen_fpga_o13;
+    output fabric_tsvalue_tsgen_fpga_o14;
+    output fabric_tsvalue_tsgen_fpga_o15;
+    output fabric_tsvalue_tsgen_fpga_o16;
+    output fabric_tsvalue_tsgen_fpga_o17;
+    output fabric_tsvalue_tsgen_fpga_o18;
+    output fabric_tsvalue_tsgen_fpga_o19;
+    output fabric_tsvalue_tsgen_fpga_o2;
+    output fabric_tsvalue_tsgen_fpga_o20;
+    output fabric_tsvalue_tsgen_fpga_o21;
+    output fabric_tsvalue_tsgen_fpga_o22;
+    output fabric_tsvalue_tsgen_fpga_o23;
+    output fabric_tsvalue_tsgen_fpga_o24;
+    output fabric_tsvalue_tsgen_fpga_o25;
+    output fabric_tsvalue_tsgen_fpga_o26;
+    output fabric_tsvalue_tsgen_fpga_o27;
+    output fabric_tsvalue_tsgen_fpga_o28;
+    output fabric_tsvalue_tsgen_fpga_o29;
+    output fabric_tsvalue_tsgen_fpga_o3;
+    output fabric_tsvalue_tsgen_fpga_o30;
+    output fabric_tsvalue_tsgen_fpga_o31;
+    output fabric_tsvalue_tsgen_fpga_o32;
+    output fabric_tsvalue_tsgen_fpga_o33;
+    output fabric_tsvalue_tsgen_fpga_o34;
+    output fabric_tsvalue_tsgen_fpga_o35;
+    output fabric_tsvalue_tsgen_fpga_o36;
+    output fabric_tsvalue_tsgen_fpga_o37;
+    output fabric_tsvalue_tsgen_fpga_o38;
+    output fabric_tsvalue_tsgen_fpga_o39;
+    output fabric_tsvalue_tsgen_fpga_o4;
+    output fabric_tsvalue_tsgen_fpga_o40;
+    output fabric_tsvalue_tsgen_fpga_o41;
+    output fabric_tsvalue_tsgen_fpga_o42;
+    output fabric_tsvalue_tsgen_fpga_o43;
+    output fabric_tsvalue_tsgen_fpga_o44;
+    output fabric_tsvalue_tsgen_fpga_o45;
+    output fabric_tsvalue_tsgen_fpga_o46;
+    output fabric_tsvalue_tsgen_fpga_o47;
+    output fabric_tsvalue_tsgen_fpga_o48;
+    output fabric_tsvalue_tsgen_fpga_o49;
+    output fabric_tsvalue_tsgen_fpga_o5;
+    output fabric_tsvalue_tsgen_fpga_o50;
+    output fabric_tsvalue_tsgen_fpga_o51;
+    output fabric_tsvalue_tsgen_fpga_o52;
+    output fabric_tsvalue_tsgen_fpga_o53;
+    output fabric_tsvalue_tsgen_fpga_o54;
+    output fabric_tsvalue_tsgen_fpga_o55;
+    output fabric_tsvalue_tsgen_fpga_o56;
+    output fabric_tsvalue_tsgen_fpga_o57;
+    output fabric_tsvalue_tsgen_fpga_o58;
+    output fabric_tsvalue_tsgen_fpga_o59;
+    output fabric_tsvalue_tsgen_fpga_o6;
+    output fabric_tsvalue_tsgen_fpga_o60;
+    output fabric_tsvalue_tsgen_fpga_o61;
+    output fabric_tsvalue_tsgen_fpga_o62;
+    output fabric_tsvalue_tsgen_fpga_o63;
+    output fabric_tsvalue_tsgen_fpga_o64;
+    output fabric_tsvalue_tsgen_fpga_o7;
+    output fabric_tsvalue_tsgen_fpga_o8;
+    output fabric_tsvalue_tsgen_fpga_o9;
+    output fabric_watchdog0_signal_0_o;
+    output fabric_watchdog0_signal_1_o;
+    output fabric_watchdog1_signal_0_o;
+    output fabric_watchdog1_signal_1_o;
+    output fabric_watchdog2_signal_0_o;
+    output fabric_watchdog2_signal_1_o;
+    output fabric_watchdog3_signal_0_o;
+    output fabric_watchdog3_signal_1_o;
+    parameter ahb_config = 0;
+    parameter bsm_config = 0;
+endmodule
+
+(* blackbox *)
+module NX_SOC_INTERFACE_V1(fabric_lowskew_o1, fabric_lowskew_i1, fabric_lowskew_i2, fabric_lowskew_i3, fabric_lowskew_i4, fabric_lowskew_i5, fabric_lowskew_i6, fabric_lowskew_i7, fabric_lowskew_i8, fabric_lowskew_i9, fabric_lowskew_i10, fabric_lowskew_o2, fabric_fpga_nic_rstn_i1, fabric_fpga_nic_rstn_i2, fabric_fpga_nic_rstn_i3, fabric_fpga_nic_rstn_i4, fabric_fpga_nic_rstn_i5, fabric_fpga_nic_rstn_i6, fabric_fpga_nic_rstn_i7, fabric_fpga_nic_rstn_i8, fabric_fpga_nic_rstn_i9
+, fabric_fpga_nic_rstn_i10, fabric_fpga_pmrstn_i, fabric_fpga_sysrstn_i, fabric_fpga_trigger_in_o1, fabric_fpga_trigger_in_o2, fabric_fpga_trigger_in_o3, fabric_fpga_trigger_in_o4, fabric_fpga_trigger_in_o5, fabric_fpga_trigger_in_o6, fabric_fpga_trigger_in_o7, fabric_fpga_trigger_in_o8, fabric_fpga_trigger_out_i1, fabric_fpga_trigger_out_i2, fabric_fpga_trigger_out_i3, fabric_fpga_trigger_out_i4, fabric_fpga_trigger_out_i5, fabric_fpga_trigger_out_i6, fabric_fpga_trigger_out_i7, fabric_fpga_trigger_out_i8, fabric_fpga_interrupt_in_i1, fabric_fpga_interrupt_in_i2
+, fabric_fpga_interrupt_in_i3, fabric_fpga_interrupt_in_i4, fabric_fpga_interrupt_in_i5, fabric_fpga_interrupt_in_i6, fabric_fpga_interrupt_in_i7, fabric_fpga_interrupt_in_i8, fabric_fpga_interrupt_in_i9, fabric_fpga_interrupt_in_i10, fabric_fpga_interrupt_in_i11, fabric_fpga_interrupt_in_i12, fabric_fpga_interrupt_in_i13, fabric_fpga_interrupt_in_i14, fabric_fpga_interrupt_in_i15, fabric_fpga_interrupt_in_i16, fabric_fpga_interrupt_in_i17, fabric_fpga_interrupt_in_i18, fabric_fpga_interrupt_in_i19, fabric_fpga_interrupt_in_i20, fabric_fpga_interrupt_in_i21, fabric_fpga_interrupt_in_i22, fabric_fpga_interrupt_in_i23
+, fabric_fpga_interrupt_in_i24, fabric_fpga_interrupt_in_i25, fabric_fpga_interrupt_in_i26, fabric_fpga_interrupt_in_i27, fabric_fpga_interrupt_in_i28, fabric_fpga_interrupt_in_i29, fabric_fpga_interrupt_in_i30, fabric_fpga_interrupt_in_i31, fabric_fpga_interrupt_in_i32, fabric_fpga_interrupt_in_i33, fabric_fpga_interrupt_in_i34, fabric_fpga_interrupt_in_i35, fabric_fpga_interrupt_in_i36, fabric_fpga_interrupt_in_i37, fabric_fpga_interrupt_in_i38, fabric_fpga_interrupt_in_i39, fabric_fpga_interrupt_in_i40, fabric_fpga_interrupt_in_i41, fabric_fpga_interrupt_in_i42, fabric_fpga_interrupt_in_i43, fabric_fpga_interrupt_in_i44
+, fabric_fpga_interrupt_in_i45, fabric_fpga_interrupt_in_i46, fabric_fpga_interrupt_in_i47, fabric_fpga_interrupt_in_i48, fabric_fpga_interrupt_in_i49, fabric_fpga_interrupt_in_i50, fabric_fpga_interrupt_in_i51, fabric_fpga_interrupt_in_i52, fabric_fpga_interrupt_in_i53, fabric_fpga_interrupt_in_i54, fabric_fpga_interrupt_in_i55, fabric_fpga_interrupt_in_i56, fabric_fpga_interrupt_in_i57, fabric_fpga_interrupt_in_i58, fabric_fpga_interrupt_in_i59, fabric_fpga_interrupt_in_i60, fabric_fpga_interrupt_in_i61, fabric_fpga_interrupt_in_i62, fabric_fpga_interrupt_in_i63, fabric_fpga_interrupt_in_i64, fabric_fpga_interrupt_in_i65
+, fabric_fpga_interrupt_in_i66, fabric_fpga_interrupt_in_i67, fabric_fpga_interrupt_in_i68, fabric_fpga_interrupt_in_i69, fabric_fpga_interrupt_in_i70, fabric_fpga_interrupt_in_i71, fabric_fpga_interrupt_in_i72, fabric_fpga_interrupt_in_i73, fabric_fpga_interrupt_in_i74, fabric_fpga_interrupt_in_i75, fabric_fpga_interrupt_in_i76, fabric_fpga_interrupt_in_i77, fabric_fpga_interrupt_in_i78, fabric_fpga_interrupt_in_i79, fabric_fpga_interrupt_in_i80, fabric_fpga_interrupt_in_i81, fabric_fpga_interrupt_in_i82, fabric_fpga_interrupt_in_i83, fabric_fpga_interrupt_in_i84, fabric_fpga_interrupt_in_i85, fabric_fpga_interrupt_in_i86
+, fabric_fpga_interrupt_in_i87, fabric_fpga_interrupt_in_i88, fabric_fpga_interrupt_in_i89, fabric_fpga_interrupt_in_i90, fabric_fpga_interrupt_in_i91, fabric_fpga_interrupt_in_i92, fabric_fpga_interrupt_in_i93, fabric_fpga_interrupt_in_i94, fabric_fpga_interrupt_in_i95, fabric_fpga_interrupt_in_i96, fabric_fpga_interrupt_in_i97, fabric_fpga_interrupt_in_i98, fabric_fpga_interrupt_in_i99, fabric_fpga_interrupt_in_i100, fabric_fpga_interrupt_in_i101, fabric_fpga_interrupt_in_i102, fabric_fpga_interrupt_in_i103, fabric_fpga_interrupt_in_i104, fabric_fpga_interrupt_in_i105, fabric_fpga_interrupt_in_i106, fabric_fpga_interrupt_in_i107
+, fabric_fpga_interrupt_in_i108, fabric_fpga_interrupt_in_i109, fabric_fpga_interrupt_in_i110, fabric_fpga_interrupt_in_i111, fabric_fpga_interrupt_in_i112, fabric_fpga_interrupt_in_i113, fabric_fpga_interrupt_in_i114, fabric_fpga_interrupt_in_i115, fabric_fpga_interrupt_in_i116, fabric_fpga_interrupt_in_i117, fabric_fpga_interrupt_in_i118, fabric_fpga_interrupt_in_i119, fabric_fpga_interrupt_in_i120, fabric_sysc_hold_on_debug_i, fabric_fpga_events60_i1, fabric_fpga_events60_i2, fabric_fpga_events60_i3, fabric_fpga_events60_i4, fabric_fpga_events60_i5, fabric_fpga_events60_i6, fabric_fpga_events60_i7
+, fabric_fpga_events60_i8, fabric_fpga_events60_i9, fabric_fpga_events60_i10, fabric_fpga_events60_i11, fabric_fpga_events60_i12, fabric_fpga_events60_i13, fabric_fpga_events60_i14, fabric_fpga_events60_i15, fabric_fpga_events60_i16, fabric_fpga_events60_i17, fabric_fpga_events60_i18, fabric_fpga_events60_i19, fabric_fpga_events60_i20, fabric_fpga_events60_i21, fabric_fpga_events60_i22, fabric_fpga_events60_i23, fabric_fpga_events60_i24, fabric_fpga_events60_i25, fabric_fpga_events60_i26, fabric_fpga_events60_i27, fabric_fpga_events60_i28
+, fabric_fpga_events60_i29, fabric_fpga_events60_i30, fabric_fpga_events60_i31, fabric_fpga_events60_i32, fabric_fpga_events60_i33, fabric_fpga_events60_i34, fabric_fpga_events60_i35, fabric_fpga_events60_i36, fabric_fpga_events60_i37, fabric_fpga_events60_i38, fabric_fpga_events60_i39, fabric_fpga_events60_i40, fabric_fpga_events60_i41, fabric_fpga_events60_i42, fabric_fpga_events60_i43, fabric_fpga_events60_i44, fabric_fpga_events60_i45, fabric_fpga_events60_i46, fabric_fpga_events60_i47, fabric_fpga_events60_i48, fabric_fpga_events60_i49
+, fabric_fpga_events60_i50, fabric_fpga_events60_i51, fabric_fpga_events60_i52, fabric_fpga_events60_i53, fabric_fpga_events60_i54, fabric_fpga_events60_i55, fabric_fpga_events60_i56, fabric_fpga_events60_i57, fabric_fpga_events60_i58, fabric_fpga_events60_i59, fabric_fpga_events60_i60, fabric_fpga_araddr_axi_s1_o1, fabric_fpga_araddr_axi_s1_o2, fabric_fpga_araddr_axi_s1_o3, fabric_fpga_araddr_axi_s1_o4, fabric_fpga_araddr_axi_s1_o5, fabric_fpga_araddr_axi_s1_o6, fabric_fpga_araddr_axi_s1_o7, fabric_fpga_araddr_axi_s1_o8, fabric_fpga_araddr_axi_s1_o9, fabric_fpga_araddr_axi_s1_o10
+, fabric_fpga_araddr_axi_s1_o11, fabric_fpga_araddr_axi_s1_o12, fabric_fpga_araddr_axi_s1_o13, fabric_fpga_araddr_axi_s1_o14, fabric_fpga_araddr_axi_s1_o15, fabric_fpga_araddr_axi_s1_o16, fabric_fpga_araddr_axi_s1_o17, fabric_fpga_araddr_axi_s1_o18, fabric_fpga_araddr_axi_s1_o19, fabric_fpga_araddr_axi_s1_o20, fabric_fpga_araddr_axi_s1_o21, fabric_fpga_araddr_axi_s1_o22, fabric_fpga_araddr_axi_s1_o23, fabric_fpga_araddr_axi_s1_o24, fabric_fpga_araddr_axi_s1_o25, fabric_fpga_araddr_axi_s1_o26, fabric_fpga_araddr_axi_s1_o27, fabric_fpga_araddr_axi_s1_o28, fabric_fpga_araddr_axi_s1_o29, fabric_fpga_araddr_axi_s1_o30, fabric_fpga_araddr_axi_s1_o31
+, fabric_fpga_araddr_axi_s1_o32, fabric_fpga_araddr_axi_s1_o33, fabric_fpga_araddr_axi_s1_o34, fabric_fpga_araddr_axi_s1_o35, fabric_fpga_araddr_axi_s1_o36, fabric_fpga_araddr_axi_s1_o37, fabric_fpga_araddr_axi_s1_o38, fabric_fpga_araddr_axi_s1_o39, fabric_fpga_araddr_axi_s1_o40, fabric_fpga_arburst_axi_s1_o1, fabric_fpga_arburst_axi_s1_o2, fabric_fpga_arcache_axi_s1_o1, fabric_fpga_arcache_axi_s1_o2, fabric_fpga_arcache_axi_s1_o3, fabric_fpga_arcache_axi_s1_o4, fabric_fpga_arid_axi_s1_o1, fabric_fpga_arid_axi_s1_o2, fabric_fpga_arid_axi_s1_o3, fabric_fpga_arid_axi_s1_o4, fabric_fpga_arid_axi_s1_o5, fabric_fpga_arid_axi_s1_o6
+, fabric_fpga_arid_axi_s1_o7, fabric_fpga_arid_axi_s1_o8, fabric_fpga_arid_axi_s1_o9, fabric_fpga_arid_axi_s1_o10, fabric_fpga_arid_axi_s1_o11, fabric_fpga_arid_axi_s1_o12, fabric_fpga_arlen_axi_s1_o1, fabric_fpga_arlen_axi_s1_o2, fabric_fpga_arlen_axi_s1_o3, fabric_fpga_arlen_axi_s1_o4, fabric_fpga_arlen_axi_s1_o5, fabric_fpga_arlen_axi_s1_o6, fabric_fpga_arlen_axi_s1_o7, fabric_fpga_arlen_axi_s1_o8, fabric_fpga_arlock_axi_s1_o, fabric_fpga_arprot_axi_s1_o1, fabric_fpga_arprot_axi_s1_o2, fabric_fpga_arprot_axi_s1_o3, fabric_fpga_arqos_axi_s1_o1, fabric_fpga_arqos_axi_s1_o2, fabric_fpga_arqos_axi_s1_o3
+, fabric_fpga_arqos_axi_s1_o4, fabric_fpga_arregion_axi_s1_o1, fabric_fpga_arregion_axi_s1_o2, fabric_fpga_arregion_axi_s1_o3, fabric_fpga_arregion_axi_s1_o4, fabric_fpga_arsize_axi_s1_o1, fabric_fpga_arsize_axi_s1_o2, fabric_fpga_arsize_axi_s1_o3, fabric_fpga_arvalid_axi_s1_o, fabric_fpga_awaddr_axi_s1_o1, fabric_fpga_awaddr_axi_s1_o2, fabric_fpga_awaddr_axi_s1_o3, fabric_fpga_awaddr_axi_s1_o4, fabric_fpga_awaddr_axi_s1_o5, fabric_fpga_awaddr_axi_s1_o6, fabric_fpga_awaddr_axi_s1_o7, fabric_fpga_awaddr_axi_s1_o8, fabric_fpga_awaddr_axi_s1_o9, fabric_fpga_awaddr_axi_s1_o10, fabric_fpga_awaddr_axi_s1_o11, fabric_fpga_awaddr_axi_s1_o12
+, fabric_fpga_awaddr_axi_s1_o13, fabric_fpga_awaddr_axi_s1_o14, fabric_fpga_awaddr_axi_s1_o15, fabric_fpga_awaddr_axi_s1_o16, fabric_fpga_awaddr_axi_s1_o17, fabric_fpga_awaddr_axi_s1_o18, fabric_fpga_awaddr_axi_s1_o19, fabric_fpga_awaddr_axi_s1_o20, fabric_fpga_awaddr_axi_s1_o21, fabric_fpga_awaddr_axi_s1_o22, fabric_fpga_awaddr_axi_s1_o23, fabric_fpga_awaddr_axi_s1_o24, fabric_fpga_awaddr_axi_s1_o25, fabric_fpga_awaddr_axi_s1_o26, fabric_fpga_awaddr_axi_s1_o27, fabric_fpga_awaddr_axi_s1_o28, fabric_fpga_awaddr_axi_s1_o29, fabric_fpga_awaddr_axi_s1_o30, fabric_fpga_awaddr_axi_s1_o31, fabric_fpga_awaddr_axi_s1_o32, fabric_fpga_awaddr_axi_s1_o33
+, fabric_fpga_awaddr_axi_s1_o34, fabric_fpga_awaddr_axi_s1_o35, fabric_fpga_awaddr_axi_s1_o36, fabric_fpga_awaddr_axi_s1_o37, fabric_fpga_awaddr_axi_s1_o38, fabric_fpga_awaddr_axi_s1_o39, fabric_fpga_awaddr_axi_s1_o40, fabric_fpga_awburst_axi_s1_o1, fabric_fpga_awburst_axi_s1_o2, fabric_fpga_awcache_axi_s1_o1, fabric_fpga_awcache_axi_s1_o2, fabric_fpga_awcache_axi_s1_o3, fabric_fpga_awcache_axi_s1_o4, fabric_fpga_awid_axi_s1_o1, fabric_fpga_awid_axi_s1_o2, fabric_fpga_awid_axi_s1_o3, fabric_fpga_awid_axi_s1_o4, fabric_fpga_awid_axi_s1_o5, fabric_fpga_awid_axi_s1_o6, fabric_fpga_awid_axi_s1_o7, fabric_fpga_awid_axi_s1_o8
+, fabric_fpga_awid_axi_s1_o9, fabric_fpga_awid_axi_s1_o10, fabric_fpga_awid_axi_s1_o11, fabric_fpga_awid_axi_s1_o12, fabric_fpga_awlen_axi_s1_o1, fabric_fpga_awlen_axi_s1_o2, fabric_fpga_awlen_axi_s1_o3, fabric_fpga_awlen_axi_s1_o4, fabric_fpga_awlen_axi_s1_o5, fabric_fpga_awlen_axi_s1_o6, fabric_fpga_awlen_axi_s1_o7, fabric_fpga_awlen_axi_s1_o8, fabric_fpga_awlock_axi_s1_o, fabric_fpga_awprot_axi_s1_o1, fabric_fpga_awprot_axi_s1_o2, fabric_fpga_awprot_axi_s1_o3, fabric_fpga_awqos_axi_s1_o1, fabric_fpga_awqos_axi_s1_o2, fabric_fpga_awqos_axi_s1_o3, fabric_fpga_awqos_axi_s1_o4, fabric_fpga_awregion_axi_s1_o1
+, fabric_fpga_awregion_axi_s1_o2, fabric_fpga_awregion_axi_s1_o3, fabric_fpga_awregion_axi_s1_o4, fabric_fpga_awsize_axi_s1_o1, fabric_fpga_awsize_axi_s1_o2, fabric_fpga_awsize_axi_s1_o3, fabric_fpga_bready_axi_s1_o, fabric_fpga_rready_axi_s1_o, fabric_fpga_wdata_axi_s1_o1, fabric_fpga_wdata_axi_s1_o2, fabric_fpga_wdata_axi_s1_o3, fabric_fpga_wdata_axi_s1_o4, fabric_fpga_wdata_axi_s1_o5, fabric_fpga_wdata_axi_s1_o6, fabric_fpga_wdata_axi_s1_o7, fabric_fpga_wdata_axi_s1_o8, fabric_fpga_wdata_axi_s1_o9, fabric_fpga_wdata_axi_s1_o10, fabric_fpga_wdata_axi_s1_o11, fabric_fpga_wdata_axi_s1_o12, fabric_fpga_wdata_axi_s1_o13
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+, fabric_fpga_rdata_axi_m1_o49, fabric_fpga_rdata_axi_m1_o50, fabric_fpga_rdata_axi_m1_o51, fabric_fpga_rdata_axi_m1_o52, fabric_fpga_rdata_axi_m1_o53, fabric_fpga_rdata_axi_m1_o54, fabric_fpga_rdata_axi_m1_o55, fabric_fpga_rdata_axi_m1_o56, fabric_fpga_rdata_axi_m1_o57, fabric_fpga_rdata_axi_m1_o58, fabric_fpga_rdata_axi_m1_o59, fabric_fpga_rdata_axi_m1_o60, fabric_fpga_rdata_axi_m1_o61, fabric_fpga_rdata_axi_m1_o62, fabric_fpga_rdata_axi_m1_o63, fabric_fpga_rdata_axi_m1_o64, fabric_fpga_rdata_axi_m1_o65, fabric_fpga_rdata_axi_m1_o66, fabric_fpga_rdata_axi_m1_o67, fabric_fpga_rdata_axi_m1_o68, fabric_fpga_rdata_axi_m1_o69
+, fabric_fpga_rdata_axi_m1_o70, fabric_fpga_rdata_axi_m1_o71, fabric_fpga_rdata_axi_m1_o72, fabric_fpga_rdata_axi_m1_o73, fabric_fpga_rdata_axi_m1_o74, fabric_fpga_rdata_axi_m1_o75, fabric_fpga_rdata_axi_m1_o76, fabric_fpga_rdata_axi_m1_o77, fabric_fpga_rdata_axi_m1_o78, fabric_fpga_rdata_axi_m1_o79, fabric_fpga_rdata_axi_m1_o80, fabric_fpga_rdata_axi_m1_o81, fabric_fpga_rdata_axi_m1_o82, fabric_fpga_rdata_axi_m1_o83, fabric_fpga_rdata_axi_m1_o84, fabric_fpga_rdata_axi_m1_o85, fabric_fpga_rdata_axi_m1_o86, fabric_fpga_rdata_axi_m1_o87, fabric_fpga_rdata_axi_m1_o88, fabric_fpga_rdata_axi_m1_o89, fabric_fpga_rdata_axi_m1_o90
+, fabric_fpga_rdata_axi_m1_o91, fabric_fpga_rdata_axi_m1_o92, fabric_fpga_rdata_axi_m1_o93, fabric_fpga_rdata_axi_m1_o94, fabric_fpga_rdata_axi_m1_o95, fabric_fpga_rdata_axi_m1_o96, fabric_fpga_rdata_axi_m1_o97, fabric_fpga_rdata_axi_m1_o98, fabric_fpga_rdata_axi_m1_o99, fabric_fpga_rdata_axi_m1_o100, fabric_fpga_rdata_axi_m1_o101, fabric_fpga_rdata_axi_m1_o102, fabric_fpga_rdata_axi_m1_o103, fabric_fpga_rdata_axi_m1_o104, fabric_fpga_rdata_axi_m1_o105, fabric_fpga_rdata_axi_m1_o106, fabric_fpga_rdata_axi_m1_o107, fabric_fpga_rdata_axi_m1_o108, fabric_fpga_rdata_axi_m1_o109, fabric_fpga_rdata_axi_m1_o110, fabric_fpga_rdata_axi_m1_o111
+, fabric_fpga_rdata_axi_m1_o112, fabric_fpga_rdata_axi_m1_o113, fabric_fpga_rdata_axi_m1_o114, fabric_fpga_rdata_axi_m1_o115, fabric_fpga_rdata_axi_m1_o116, fabric_fpga_rdata_axi_m1_o117, fabric_fpga_rdata_axi_m1_o118, fabric_fpga_rdata_axi_m1_o119, fabric_fpga_rdata_axi_m1_o120, fabric_fpga_rdata_axi_m1_o121, fabric_fpga_rdata_axi_m1_o122, fabric_fpga_rdata_axi_m1_o123, fabric_fpga_rdata_axi_m1_o124, fabric_fpga_rdata_axi_m1_o125, fabric_fpga_rdata_axi_m1_o126, fabric_fpga_rdata_axi_m1_o127, fabric_fpga_rdata_axi_m1_o128, fabric_fpga_rid_axi_m1_o1, fabric_fpga_rid_axi_m1_o2, fabric_fpga_rid_axi_m1_o3, fabric_fpga_rid_axi_m1_o4
+, fabric_fpga_rid_axi_m1_o5, fabric_fpga_rlast_axi_m1_o, fabric_fpga_rresp_axi_m1_o1, fabric_fpga_rresp_axi_m1_o2, fabric_fpga_rvalid_axi_m1_o, fabric_fpga_wready_axi_m1_o, fabric_fpga_araddr_axi_m1_i1, fabric_fpga_araddr_axi_m1_i2, fabric_fpga_araddr_axi_m1_i3, fabric_fpga_araddr_axi_m1_i4, fabric_fpga_araddr_axi_m1_i5, fabric_fpga_araddr_axi_m1_i6, fabric_fpga_araddr_axi_m1_i7, fabric_fpga_araddr_axi_m1_i8, fabric_fpga_araddr_axi_m1_i9, fabric_fpga_araddr_axi_m1_i10, fabric_fpga_araddr_axi_m1_i11, fabric_fpga_araddr_axi_m1_i12, fabric_fpga_araddr_axi_m1_i13, fabric_fpga_araddr_axi_m1_i14, fabric_fpga_araddr_axi_m1_i15
+, fabric_fpga_araddr_axi_m1_i16, fabric_fpga_araddr_axi_m1_i17, fabric_fpga_araddr_axi_m1_i18, fabric_fpga_araddr_axi_m1_i19, fabric_fpga_araddr_axi_m1_i20, fabric_fpga_araddr_axi_m1_i21, fabric_fpga_araddr_axi_m1_i22, fabric_fpga_araddr_axi_m1_i23, fabric_fpga_araddr_axi_m1_i24, fabric_fpga_araddr_axi_m1_i25, fabric_fpga_araddr_axi_m1_i26, fabric_fpga_araddr_axi_m1_i27, fabric_fpga_araddr_axi_m1_i28, fabric_fpga_araddr_axi_m1_i29, fabric_fpga_araddr_axi_m1_i30, fabric_fpga_araddr_axi_m1_i31, fabric_fpga_araddr_axi_m1_i32, fabric_fpga_araddr_axi_m1_i33, fabric_fpga_araddr_axi_m1_i34, fabric_fpga_araddr_axi_m1_i35, fabric_fpga_araddr_axi_m1_i36
+, fabric_fpga_araddr_axi_m1_i37, fabric_fpga_araddr_axi_m1_i38, fabric_fpga_araddr_axi_m1_i39, fabric_fpga_araddr_axi_m1_i40, fabric_fpga_arburst_axi_m1_i1, fabric_fpga_arburst_axi_m1_i2, fabric_fpga_arcache_axi_m1_i1, fabric_fpga_arcache_axi_m1_i2, fabric_fpga_arcache_axi_m1_i3, fabric_fpga_arcache_axi_m1_i4, fabric_fpga_arid_axi_m1_i1, fabric_fpga_arid_axi_m1_i2, fabric_fpga_arid_axi_m1_i3, fabric_fpga_arid_axi_m1_i4, fabric_fpga_arid_axi_m1_i5, fabric_fpga_arlen_axi_m1_i1, fabric_fpga_arlen_axi_m1_i2, fabric_fpga_arlen_axi_m1_i3, fabric_fpga_arlen_axi_m1_i4, fabric_fpga_arlen_axi_m1_i5, fabric_fpga_arlen_axi_m1_i6
+, fabric_fpga_arlen_axi_m1_i7, fabric_fpga_arlen_axi_m1_i8, fabric_fpga_arlock_axi_m1_i, fabric_fpga_arprot_axi_m1_i1, fabric_fpga_arprot_axi_m1_i2, fabric_fpga_arprot_axi_m1_i3, fabric_fpga_arqos_axi_m1_i1, fabric_fpga_arqos_axi_m1_i2, fabric_fpga_arqos_axi_m1_i3, fabric_fpga_arqos_axi_m1_i4, fabric_fpga_arsize_axi_m1_i1, fabric_fpga_arsize_axi_m1_i2, fabric_fpga_arsize_axi_m1_i3, fabric_fpga_arvalid_axi_m1_i, fabric_fpga_awaddr_axi_m1_i1, fabric_fpga_awaddr_axi_m1_i2, fabric_fpga_awaddr_axi_m1_i3, fabric_fpga_awaddr_axi_m1_i4, fabric_fpga_awaddr_axi_m1_i5, fabric_fpga_awaddr_axi_m1_i6, fabric_fpga_awaddr_axi_m1_i7
+, fabric_fpga_awaddr_axi_m1_i8, fabric_fpga_awaddr_axi_m1_i9, fabric_fpga_awaddr_axi_m1_i10, fabric_fpga_awaddr_axi_m1_i11, fabric_fpga_awaddr_axi_m1_i12, fabric_fpga_awaddr_axi_m1_i13, fabric_fpga_awaddr_axi_m1_i14, fabric_fpga_awaddr_axi_m1_i15, fabric_fpga_awaddr_axi_m1_i16, fabric_fpga_awaddr_axi_m1_i17, fabric_fpga_awaddr_axi_m1_i18, fabric_fpga_awaddr_axi_m1_i19, fabric_fpga_awaddr_axi_m1_i20, fabric_fpga_awaddr_axi_m1_i21, fabric_fpga_awaddr_axi_m1_i22, fabric_fpga_awaddr_axi_m1_i23, fabric_fpga_awaddr_axi_m1_i24, fabric_fpga_awaddr_axi_m1_i25, fabric_fpga_awaddr_axi_m1_i26, fabric_fpga_awaddr_axi_m1_i27, fabric_fpga_awaddr_axi_m1_i28
+, fabric_fpga_awaddr_axi_m1_i29, fabric_fpga_awaddr_axi_m1_i30, fabric_fpga_awaddr_axi_m1_i31, fabric_fpga_awaddr_axi_m1_i32, fabric_fpga_awaddr_axi_m1_i33, fabric_fpga_awaddr_axi_m1_i34, fabric_fpga_awaddr_axi_m1_i35, fabric_fpga_awaddr_axi_m1_i36, fabric_fpga_awaddr_axi_m1_i37, fabric_fpga_awaddr_axi_m1_i38, fabric_fpga_awaddr_axi_m1_i39, fabric_fpga_awaddr_axi_m1_i40, fabric_fpga_awburst_axi_m1_i1, fabric_fpga_awburst_axi_m1_i2, fabric_fpga_awcache_axi_m1_i1, fabric_fpga_awcache_axi_m1_i2, fabric_fpga_awcache_axi_m1_i3, fabric_fpga_awcache_axi_m1_i4, fabric_fpga_awid_axi_m1_i1, fabric_fpga_awid_axi_m1_i2, fabric_fpga_awid_axi_m1_i3
+, fabric_fpga_awid_axi_m1_i4, fabric_fpga_awid_axi_m1_i5, fabric_fpga_awlen_axi_m1_i1, fabric_fpga_awlen_axi_m1_i2, fabric_fpga_awlen_axi_m1_i3, fabric_fpga_awlen_axi_m1_i4, fabric_fpga_awlen_axi_m1_i5, fabric_fpga_awlen_axi_m1_i6, fabric_fpga_awlen_axi_m1_i7, fabric_fpga_awlen_axi_m1_i8, fabric_fpga_awlock_axi_m1_i, fabric_fpga_awprot_axi_m1_i1, fabric_fpga_awprot_axi_m1_i2, fabric_fpga_awprot_axi_m1_i3, fabric_fpga_awqos_axi_m1_i1, fabric_fpga_awqos_axi_m1_i2, fabric_fpga_awqos_axi_m1_i3, fabric_fpga_awqos_axi_m1_i4, fabric_fpga_awsize_axi_m1_i1, fabric_fpga_awsize_axi_m1_i2, fabric_fpga_awsize_axi_m1_i3
+, fabric_fpga_awvalid_axi_m1_i, fabric_fpga_bready_axi_m1_i, fabric_fpga_dma_last_m1_i1, fabric_fpga_dma_last_m1_i2, fabric_fpga_dma_last_m1_i3, fabric_fpga_dma_last_m1_i4, fabric_fpga_dma_last_m1_i5, fabric_fpga_dma_last_m1_i6, fabric_fpga_dma_req_m1_i1, fabric_fpga_dma_req_m1_i2, fabric_fpga_dma_req_m1_i3, fabric_fpga_dma_req_m1_i4, fabric_fpga_dma_req_m1_i5, fabric_fpga_dma_req_m1_i6, fabric_fpga_dma_single_m1_i1, fabric_fpga_dma_single_m1_i2, fabric_fpga_dma_single_m1_i3, fabric_fpga_dma_single_m1_i4, fabric_fpga_dma_single_m1_i5, fabric_fpga_dma_single_m1_i6, fabric_fpga_rready_axi_m1_i
+, fabric_fpga_wdata_axi_m1_i1, fabric_fpga_wdata_axi_m1_i2, fabric_fpga_wdata_axi_m1_i3, fabric_fpga_wdata_axi_m1_i4, fabric_fpga_wdata_axi_m1_i5, fabric_fpga_wdata_axi_m1_i6, fabric_fpga_wdata_axi_m1_i7, fabric_fpga_wdata_axi_m1_i8, fabric_fpga_wdata_axi_m1_i9, fabric_fpga_wdata_axi_m1_i10, fabric_fpga_wdata_axi_m1_i11, fabric_fpga_wdata_axi_m1_i12, fabric_fpga_wdata_axi_m1_i13, fabric_fpga_wdata_axi_m1_i14, fabric_fpga_wdata_axi_m1_i15, fabric_fpga_wdata_axi_m1_i16, fabric_fpga_wdata_axi_m1_i17, fabric_fpga_wdata_axi_m1_i18, fabric_fpga_wdata_axi_m1_i19, fabric_fpga_wdata_axi_m1_i20, fabric_fpga_wdata_axi_m1_i21
+, fabric_fpga_wdata_axi_m1_i22, fabric_fpga_wdata_axi_m1_i23, fabric_fpga_wdata_axi_m1_i24, fabric_fpga_wdata_axi_m1_i25, fabric_fpga_wdata_axi_m1_i26, fabric_fpga_wdata_axi_m1_i27, fabric_fpga_wdata_axi_m1_i28, fabric_fpga_wdata_axi_m1_i29, fabric_fpga_wdata_axi_m1_i30, fabric_fpga_wdata_axi_m1_i31, fabric_fpga_wdata_axi_m1_i32, fabric_fpga_wdata_axi_m1_i33, fabric_fpga_wdata_axi_m1_i34, fabric_fpga_wdata_axi_m1_i35, fabric_fpga_wdata_axi_m1_i36, fabric_fpga_wdata_axi_m1_i37, fabric_fpga_wdata_axi_m1_i38, fabric_fpga_wdata_axi_m1_i39, fabric_fpga_wdata_axi_m1_i40, fabric_fpga_wdata_axi_m1_i41, fabric_fpga_wdata_axi_m1_i42
+, fabric_fpga_wdata_axi_m1_i43, fabric_fpga_wdata_axi_m1_i44, fabric_fpga_wdata_axi_m1_i45, fabric_fpga_wdata_axi_m1_i46, fabric_fpga_wdata_axi_m1_i47, fabric_fpga_wdata_axi_m1_i48, fabric_fpga_wdata_axi_m1_i49, fabric_fpga_wdata_axi_m1_i50, fabric_fpga_wdata_axi_m1_i51, fabric_fpga_wdata_axi_m1_i52, fabric_fpga_wdata_axi_m1_i53, fabric_fpga_wdata_axi_m1_i54, fabric_fpga_wdata_axi_m1_i55, fabric_fpga_wdata_axi_m1_i56, fabric_fpga_wdata_axi_m1_i57, fabric_fpga_wdata_axi_m1_i58, fabric_fpga_wdata_axi_m1_i59, fabric_fpga_wdata_axi_m1_i60, fabric_fpga_wdata_axi_m1_i61, fabric_fpga_wdata_axi_m1_i62, fabric_fpga_wdata_axi_m1_i63
+, fabric_fpga_wdata_axi_m1_i64, fabric_fpga_wdata_axi_m1_i65, fabric_fpga_wdata_axi_m1_i66, fabric_fpga_wdata_axi_m1_i67, fabric_fpga_wdata_axi_m1_i68, fabric_fpga_wdata_axi_m1_i69, fabric_fpga_wdata_axi_m1_i70, fabric_fpga_wdata_axi_m1_i71, fabric_fpga_wdata_axi_m1_i72, fabric_fpga_wdata_axi_m1_i73, fabric_fpga_wdata_axi_m1_i74, fabric_fpga_wdata_axi_m1_i75, fabric_fpga_wdata_axi_m1_i76, fabric_fpga_wdata_axi_m1_i77, fabric_fpga_wdata_axi_m1_i78, fabric_fpga_wdata_axi_m1_i79, fabric_fpga_wdata_axi_m1_i80, fabric_fpga_wdata_axi_m1_i81, fabric_fpga_wdata_axi_m1_i82, fabric_fpga_wdata_axi_m1_i83, fabric_fpga_wdata_axi_m1_i84
+, fabric_fpga_wdata_axi_m1_i85, fabric_fpga_wdata_axi_m1_i86, fabric_fpga_wdata_axi_m1_i87, fabric_fpga_wdata_axi_m1_i88, fabric_fpga_wdata_axi_m1_i89, fabric_fpga_wdata_axi_m1_i90, fabric_fpga_wdata_axi_m1_i91, fabric_fpga_wdata_axi_m1_i92, fabric_fpga_wdata_axi_m1_i93, fabric_fpga_wdata_axi_m1_i94, fabric_fpga_wdata_axi_m1_i95, fabric_fpga_wdata_axi_m1_i96, fabric_fpga_wdata_axi_m1_i97, fabric_fpga_wdata_axi_m1_i98, fabric_fpga_wdata_axi_m1_i99, fabric_fpga_wdata_axi_m1_i100, fabric_fpga_wdata_axi_m1_i101, fabric_fpga_wdata_axi_m1_i102, fabric_fpga_wdata_axi_m1_i103, fabric_fpga_wdata_axi_m1_i104, fabric_fpga_wdata_axi_m1_i105
+, fabric_fpga_wdata_axi_m1_i106, fabric_fpga_wdata_axi_m1_i107, fabric_fpga_wdata_axi_m1_i108, fabric_fpga_wdata_axi_m1_i109, fabric_fpga_wdata_axi_m1_i110, fabric_fpga_wdata_axi_m1_i111, fabric_fpga_wdata_axi_m1_i112, fabric_fpga_wdata_axi_m1_i113, fabric_fpga_wdata_axi_m1_i114, fabric_fpga_wdata_axi_m1_i115, fabric_fpga_wdata_axi_m1_i116, fabric_fpga_wdata_axi_m1_i117, fabric_fpga_wdata_axi_m1_i118, fabric_fpga_wdata_axi_m1_i119, fabric_fpga_wdata_axi_m1_i120, fabric_fpga_wdata_axi_m1_i121, fabric_fpga_wdata_axi_m1_i122, fabric_fpga_wdata_axi_m1_i123, fabric_fpga_wdata_axi_m1_i124, fabric_fpga_wdata_axi_m1_i125, fabric_fpga_wdata_axi_m1_i126
+, fabric_fpga_wdata_axi_m1_i127, fabric_fpga_wdata_axi_m1_i128, fabric_fpga_wlast_axi_m1_i, fabric_fpga_wstrb_axi_m1_i1, fabric_fpga_wstrb_axi_m1_i2, fabric_fpga_wstrb_axi_m1_i3, fabric_fpga_wstrb_axi_m1_i4, fabric_fpga_wstrb_axi_m1_i5, fabric_fpga_wstrb_axi_m1_i6, fabric_fpga_wstrb_axi_m1_i7, fabric_fpga_wstrb_axi_m1_i8, fabric_fpga_wstrb_axi_m1_i9, fabric_fpga_wstrb_axi_m1_i10, fabric_fpga_wstrb_axi_m1_i11, fabric_fpga_wstrb_axi_m1_i12, fabric_fpga_wstrb_axi_m1_i13, fabric_fpga_wstrb_axi_m1_i14, fabric_fpga_wstrb_axi_m1_i15, fabric_fpga_wstrb_axi_m1_i16, fabric_fpga_wvalid_axi_m1_i, fabric_fpga_arready_axi_m2_o
+, fabric_fpga_awready_axi_m2_o, fabric_fpga_bid_axi_m2_o1, fabric_fpga_bid_axi_m2_o2, fabric_fpga_bid_axi_m2_o3, fabric_fpga_bid_axi_m2_o4, fabric_fpga_bid_axi_m2_o5, fabric_fpga_bresp_axi_m2_o1, fabric_fpga_bresp_axi_m2_o2, fabric_fpga_bvalid_axi_m2_o, fabric_fpga_dma_ack_m2_o1, fabric_fpga_dma_ack_m2_o2, fabric_fpga_dma_ack_m2_o3, fabric_fpga_dma_ack_m2_o4, fabric_fpga_dma_ack_m2_o5, fabric_fpga_dma_ack_m2_o6, fabric_fpga_dma_finish_m2_o1, fabric_fpga_dma_finish_m2_o2, fabric_fpga_dma_finish_m2_o3, fabric_fpga_dma_finish_m2_o4, fabric_fpga_dma_finish_m2_o5, fabric_fpga_dma_finish_m2_o6
+, fabric_fpga_rdata_axi_m2_o1, fabric_fpga_rdata_axi_m2_o2, fabric_fpga_rdata_axi_m2_o3, fabric_fpga_rdata_axi_m2_o4, fabric_fpga_rdata_axi_m2_o5, fabric_fpga_rdata_axi_m2_o6, fabric_fpga_rdata_axi_m2_o7, fabric_fpga_rdata_axi_m2_o8, fabric_fpga_rdata_axi_m2_o9, fabric_fpga_rdata_axi_m2_o10, fabric_fpga_rdata_axi_m2_o11, fabric_fpga_rdata_axi_m2_o12, fabric_fpga_rdata_axi_m2_o13, fabric_fpga_rdata_axi_m2_o14, fabric_fpga_rdata_axi_m2_o15, fabric_fpga_rdata_axi_m2_o16, fabric_fpga_rdata_axi_m2_o17, fabric_fpga_rdata_axi_m2_o18, fabric_fpga_rdata_axi_m2_o19, fabric_fpga_rdata_axi_m2_o20, fabric_fpga_rdata_axi_m2_o21
+, fabric_fpga_rdata_axi_m2_o22, fabric_fpga_rdata_axi_m2_o23, fabric_fpga_rdata_axi_m2_o24, fabric_fpga_rdata_axi_m2_o25, fabric_fpga_rdata_axi_m2_o26, fabric_fpga_rdata_axi_m2_o27, fabric_fpga_rdata_axi_m2_o28, fabric_fpga_rdata_axi_m2_o29, fabric_fpga_rdata_axi_m2_o30, fabric_fpga_rdata_axi_m2_o31, fabric_fpga_rdata_axi_m2_o32, fabric_fpga_rdata_axi_m2_o33, fabric_fpga_rdata_axi_m2_o34, fabric_fpga_rdata_axi_m2_o35, fabric_fpga_rdata_axi_m2_o36, fabric_fpga_rdata_axi_m2_o37, fabric_fpga_rdata_axi_m2_o38, fabric_fpga_rdata_axi_m2_o39, fabric_fpga_rdata_axi_m2_o40, fabric_fpga_rdata_axi_m2_o41, fabric_fpga_rdata_axi_m2_o42
+, fabric_fpga_rdata_axi_m2_o43, fabric_fpga_rdata_axi_m2_o44, fabric_fpga_rdata_axi_m2_o45, fabric_fpga_rdata_axi_m2_o46, fabric_fpga_rdata_axi_m2_o47, fabric_fpga_rdata_axi_m2_o48, fabric_fpga_rdata_axi_m2_o49, fabric_fpga_rdata_axi_m2_o50, fabric_fpga_rdata_axi_m2_o51, fabric_fpga_rdata_axi_m2_o52, fabric_fpga_rdata_axi_m2_o53, fabric_fpga_rdata_axi_m2_o54, fabric_fpga_rdata_axi_m2_o55, fabric_fpga_rdata_axi_m2_o56, fabric_fpga_rdata_axi_m2_o57, fabric_fpga_rdata_axi_m2_o58, fabric_fpga_rdata_axi_m2_o59, fabric_fpga_rdata_axi_m2_o60, fabric_fpga_rdata_axi_m2_o61, fabric_fpga_rdata_axi_m2_o62, fabric_fpga_rdata_axi_m2_o63
+, fabric_fpga_rdata_axi_m2_o64, fabric_fpga_rdata_axi_m2_o65, fabric_fpga_rdata_axi_m2_o66, fabric_fpga_rdata_axi_m2_o67, fabric_fpga_rdata_axi_m2_o68, fabric_fpga_rdata_axi_m2_o69, fabric_fpga_rdata_axi_m2_o70, fabric_fpga_rdata_axi_m2_o71, fabric_fpga_rdata_axi_m2_o72, fabric_fpga_rdata_axi_m2_o73, fabric_fpga_rdata_axi_m2_o74, fabric_fpga_rdata_axi_m2_o75, fabric_fpga_rdata_axi_m2_o76, fabric_fpga_rdata_axi_m2_o77, fabric_fpga_rdata_axi_m2_o78, fabric_fpga_rdata_axi_m2_o79, fabric_fpga_rdata_axi_m2_o80, fabric_fpga_rdata_axi_m2_o81, fabric_fpga_rdata_axi_m2_o82, fabric_fpga_rdata_axi_m2_o83, fabric_fpga_rdata_axi_m2_o84
+, fabric_fpga_rdata_axi_m2_o85, fabric_fpga_rdata_axi_m2_o86, fabric_fpga_rdata_axi_m2_o87, fabric_fpga_rdata_axi_m2_o88, fabric_fpga_rdata_axi_m2_o89, fabric_fpga_rdata_axi_m2_o90, fabric_fpga_rdata_axi_m2_o91, fabric_fpga_rdata_axi_m2_o92, fabric_fpga_rdata_axi_m2_o93, fabric_fpga_rdata_axi_m2_o94, fabric_fpga_rdata_axi_m2_o95, fabric_fpga_rdata_axi_m2_o96, fabric_fpga_rdata_axi_m2_o97, fabric_fpga_rdata_axi_m2_o98, fabric_fpga_rdata_axi_m2_o99, fabric_fpga_rdata_axi_m2_o100, fabric_fpga_rdata_axi_m2_o101, fabric_fpga_rdata_axi_m2_o102, fabric_fpga_rdata_axi_m2_o103, fabric_fpga_rdata_axi_m2_o104, fabric_fpga_rdata_axi_m2_o105
+, fabric_fpga_rdata_axi_m2_o106, fabric_fpga_rdata_axi_m2_o107, fabric_fpga_rdata_axi_m2_o108, fabric_fpga_rdata_axi_m2_o109, fabric_fpga_rdata_axi_m2_o110, fabric_fpga_rdata_axi_m2_o111, fabric_fpga_rdata_axi_m2_o112, fabric_fpga_rdata_axi_m2_o113, fabric_fpga_rdata_axi_m2_o114, fabric_fpga_rdata_axi_m2_o115, fabric_fpga_rdata_axi_m2_o116, fabric_fpga_rdata_axi_m2_o117, fabric_fpga_rdata_axi_m2_o118, fabric_fpga_rdata_axi_m2_o119, fabric_fpga_rdata_axi_m2_o120, fabric_fpga_rdata_axi_m2_o121, fabric_fpga_rdata_axi_m2_o122, fabric_fpga_rdata_axi_m2_o123, fabric_fpga_rdata_axi_m2_o124, fabric_fpga_rdata_axi_m2_o125, fabric_fpga_rdata_axi_m2_o126
+, fabric_fpga_rdata_axi_m2_o127, fabric_fpga_rdata_axi_m2_o128, fabric_fpga_rid_axi_m2_o1, fabric_fpga_rid_axi_m2_o2, fabric_fpga_rid_axi_m2_o3, fabric_fpga_rid_axi_m2_o4, fabric_fpga_rid_axi_m2_o5, fabric_fpga_rlast_axi_m2_o, fabric_fpga_rresp_axi_m2_o1, fabric_fpga_rresp_axi_m2_o2, fabric_fpga_rvalid_axi_m2_o, fabric_fpga_wready_axi_m2_o, fabric_fpga_araddr_axi_m2_i1, fabric_fpga_araddr_axi_m2_i2, fabric_fpga_araddr_axi_m2_i3, fabric_fpga_araddr_axi_m2_i4, fabric_fpga_araddr_axi_m2_i5, fabric_fpga_araddr_axi_m2_i6, fabric_fpga_araddr_axi_m2_i7, fabric_fpga_araddr_axi_m2_i8, fabric_fpga_araddr_axi_m2_i9
+, fabric_fpga_araddr_axi_m2_i10, fabric_fpga_araddr_axi_m2_i11, fabric_fpga_araddr_axi_m2_i12, fabric_fpga_araddr_axi_m2_i13, fabric_fpga_araddr_axi_m2_i14, fabric_fpga_araddr_axi_m2_i15, fabric_fpga_araddr_axi_m2_i16, fabric_fpga_araddr_axi_m2_i17, fabric_fpga_araddr_axi_m2_i18, fabric_fpga_araddr_axi_m2_i19, fabric_fpga_araddr_axi_m2_i20, fabric_fpga_araddr_axi_m2_i21, fabric_fpga_araddr_axi_m2_i22, fabric_fpga_araddr_axi_m2_i23, fabric_fpga_araddr_axi_m2_i24, fabric_fpga_araddr_axi_m2_i25, fabric_fpga_araddr_axi_m2_i26, fabric_fpga_araddr_axi_m2_i27, fabric_fpga_araddr_axi_m2_i28, fabric_fpga_araddr_axi_m2_i29, fabric_fpga_araddr_axi_m2_i30
+, fabric_fpga_araddr_axi_m2_i31, fabric_fpga_araddr_axi_m2_i32, fabric_fpga_araddr_axi_m2_i33, fabric_fpga_araddr_axi_m2_i34, fabric_fpga_araddr_axi_m2_i35, fabric_fpga_araddr_axi_m2_i36, fabric_fpga_araddr_axi_m2_i37, fabric_fpga_araddr_axi_m2_i38, fabric_fpga_araddr_axi_m2_i39, fabric_fpga_araddr_axi_m2_i40, fabric_fpga_arburst_axi_m2_i1, fabric_fpga_arburst_axi_m2_i2, fabric_fpga_arcache_axi_m2_i1, fabric_fpga_arcache_axi_m2_i2, fabric_fpga_arcache_axi_m2_i3, fabric_fpga_arcache_axi_m2_i4, fabric_fpga_arid_axi_m2_i1, fabric_fpga_arid_axi_m2_i2, fabric_fpga_arid_axi_m2_i3, fabric_fpga_arid_axi_m2_i4, fabric_fpga_arid_axi_m2_i5
+, fabric_fpga_arlen_axi_m2_i1, fabric_fpga_arlen_axi_m2_i2, fabric_fpga_arlen_axi_m2_i3, fabric_fpga_arlen_axi_m2_i4, fabric_fpga_arlen_axi_m2_i5, fabric_fpga_arlen_axi_m2_i6, fabric_fpga_arlen_axi_m2_i7, fabric_fpga_arlen_axi_m2_i8, fabric_fpga_arlock_axi_m2_i, fabric_fpga_arprot_axi_m2_i1, fabric_fpga_arprot_axi_m2_i2, fabric_fpga_arprot_axi_m2_i3, fabric_fpga_arqos_axi_m2_i1, fabric_fpga_arqos_axi_m2_i2, fabric_fpga_arqos_axi_m2_i3, fabric_fpga_arqos_axi_m2_i4, fabric_fpga_arsize_axi_m2_i1, fabric_fpga_arsize_axi_m2_i2, fabric_fpga_arsize_axi_m2_i3, fabric_fpga_arvalid_axi_m2_i, fabric_fpga_awaddr_axi_m2_i1
+, fabric_fpga_awaddr_axi_m2_i2, fabric_fpga_awaddr_axi_m2_i3, fabric_fpga_awaddr_axi_m2_i4, fabric_fpga_awaddr_axi_m2_i5, fabric_fpga_awaddr_axi_m2_i6, fabric_fpga_awaddr_axi_m2_i7, fabric_fpga_awaddr_axi_m2_i8, fabric_fpga_awaddr_axi_m2_i9, fabric_fpga_awaddr_axi_m2_i10, fabric_fpga_awaddr_axi_m2_i11, fabric_fpga_awaddr_axi_m2_i12, fabric_fpga_awaddr_axi_m2_i13, fabric_fpga_awaddr_axi_m2_i14, fabric_fpga_awaddr_axi_m2_i15, fabric_fpga_awaddr_axi_m2_i16, fabric_fpga_awaddr_axi_m2_i17, fabric_fpga_awaddr_axi_m2_i18, fabric_fpga_awaddr_axi_m2_i19, fabric_fpga_awaddr_axi_m2_i20, fabric_fpga_awaddr_axi_m2_i21, fabric_fpga_awaddr_axi_m2_i22
+, fabric_fpga_awaddr_axi_m2_i23, fabric_fpga_awaddr_axi_m2_i24, fabric_fpga_awaddr_axi_m2_i25, fabric_fpga_awaddr_axi_m2_i26, fabric_fpga_awaddr_axi_m2_i27, fabric_fpga_awaddr_axi_m2_i28, fabric_fpga_awaddr_axi_m2_i29, fabric_fpga_awaddr_axi_m2_i30, fabric_fpga_awaddr_axi_m2_i31, fabric_fpga_awaddr_axi_m2_i32, fabric_fpga_awaddr_axi_m2_i33, fabric_fpga_awaddr_axi_m2_i34, fabric_fpga_awaddr_axi_m2_i35, fabric_fpga_awaddr_axi_m2_i36, fabric_fpga_awaddr_axi_m2_i37, fabric_fpga_awaddr_axi_m2_i38, fabric_fpga_awaddr_axi_m2_i39, fabric_fpga_awaddr_axi_m2_i40, fabric_fpga_awburst_axi_m2_i1, fabric_fpga_awburst_axi_m2_i2, fabric_fpga_awcache_axi_m2_i1
+, fabric_fpga_awcache_axi_m2_i2, fabric_fpga_awcache_axi_m2_i3, fabric_fpga_awcache_axi_m2_i4, fabric_fpga_awid_axi_m2_i1, fabric_fpga_awid_axi_m2_i2, fabric_fpga_awid_axi_m2_i3, fabric_fpga_awid_axi_m2_i4, fabric_fpga_awid_axi_m2_i5, fabric_fpga_awlen_axi_m2_i1, fabric_fpga_awlen_axi_m2_i2, fabric_fpga_awlen_axi_m2_i3, fabric_fpga_awlen_axi_m2_i4, fabric_fpga_awlen_axi_m2_i5, fabric_fpga_awlen_axi_m2_i6, fabric_fpga_awlen_axi_m2_i7, fabric_fpga_awlen_axi_m2_i8, fabric_fpga_awlock_axi_m2_i, fabric_fpga_awprot_axi_m2_i1, fabric_fpga_awprot_axi_m2_i2, fabric_fpga_awprot_axi_m2_i3, fabric_fpga_awqos_axi_m2_i1
+, fabric_fpga_awqos_axi_m2_i2, fabric_fpga_awqos_axi_m2_i3, fabric_fpga_awqos_axi_m2_i4, fabric_fpga_awsize_axi_m2_i1, fabric_fpga_awsize_axi_m2_i2, fabric_fpga_awsize_axi_m2_i3, fabric_fpga_awvalid_axi_m2_i, fabric_fpga_bready_axi_m2_i, fabric_fpga_dma_last_m2_i1, fabric_fpga_dma_last_m2_i2, fabric_fpga_dma_last_m2_i3, fabric_fpga_dma_last_m2_i4, fabric_fpga_dma_last_m2_i5, fabric_fpga_dma_last_m2_i6, fabric_fpga_dma_req_m2_i1, fabric_fpga_dma_req_m2_i2, fabric_fpga_dma_req_m2_i3, fabric_fpga_dma_req_m2_i4, fabric_fpga_dma_req_m2_i5, fabric_fpga_dma_req_m2_i6, fabric_fpga_dma_single_m2_i1
+, fabric_fpga_dma_single_m2_i2, fabric_fpga_dma_single_m2_i3, fabric_fpga_dma_single_m2_i4, fabric_fpga_dma_single_m2_i5, fabric_fpga_dma_single_m2_i6, fabric_fpga_rready_axi_m2_i, fabric_fpga_wdata_axi_m2_i1, fabric_fpga_wdata_axi_m2_i2, fabric_fpga_wdata_axi_m2_i3, fabric_fpga_wdata_axi_m2_i4, fabric_fpga_wdata_axi_m2_i5, fabric_fpga_wdata_axi_m2_i6, fabric_fpga_wdata_axi_m2_i7, fabric_fpga_wdata_axi_m2_i8, fabric_fpga_wdata_axi_m2_i9, fabric_fpga_wdata_axi_m2_i10, fabric_fpga_wdata_axi_m2_i11, fabric_fpga_wdata_axi_m2_i12, fabric_fpga_wdata_axi_m2_i13, fabric_fpga_wdata_axi_m2_i14, fabric_fpga_wdata_axi_m2_i15
+, fabric_fpga_wdata_axi_m2_i16, fabric_fpga_wdata_axi_m2_i17, fabric_fpga_wdata_axi_m2_i18, fabric_fpga_wdata_axi_m2_i19, fabric_fpga_wdata_axi_m2_i20, fabric_fpga_wdata_axi_m2_i21, fabric_fpga_wdata_axi_m2_i22, fabric_fpga_wdata_axi_m2_i23, fabric_fpga_wdata_axi_m2_i24, fabric_fpga_wdata_axi_m2_i25, fabric_fpga_wdata_axi_m2_i26, fabric_fpga_wdata_axi_m2_i27, fabric_fpga_wdata_axi_m2_i28, fabric_fpga_wdata_axi_m2_i29, fabric_fpga_wdata_axi_m2_i30, fabric_fpga_wdata_axi_m2_i31, fabric_fpga_wdata_axi_m2_i32, fabric_fpga_wdata_axi_m2_i33, fabric_fpga_wdata_axi_m2_i34, fabric_fpga_wdata_axi_m2_i35, fabric_fpga_wdata_axi_m2_i36
+, fabric_fpga_wdata_axi_m2_i37, fabric_fpga_wdata_axi_m2_i38, fabric_fpga_wdata_axi_m2_i39, fabric_fpga_wdata_axi_m2_i40, fabric_fpga_wdata_axi_m2_i41, fabric_fpga_wdata_axi_m2_i42, fabric_fpga_wdata_axi_m2_i43, fabric_fpga_wdata_axi_m2_i44, fabric_fpga_wdata_axi_m2_i45, fabric_fpga_wdata_axi_m2_i46, fabric_fpga_wdata_axi_m2_i47, fabric_fpga_wdata_axi_m2_i48, fabric_fpga_wdata_axi_m2_i49, fabric_fpga_wdata_axi_m2_i50, fabric_fpga_wdata_axi_m2_i51, fabric_fpga_wdata_axi_m2_i52, fabric_fpga_wdata_axi_m2_i53, fabric_fpga_wdata_axi_m2_i54, fabric_fpga_wdata_axi_m2_i55, fabric_fpga_wdata_axi_m2_i56, fabric_fpga_wdata_axi_m2_i57
+, fabric_fpga_wdata_axi_m2_i58, fabric_fpga_wdata_axi_m2_i59, fabric_fpga_wdata_axi_m2_i60, fabric_fpga_wdata_axi_m2_i61, fabric_fpga_wdata_axi_m2_i62, fabric_fpga_wdata_axi_m2_i63, fabric_fpga_wdata_axi_m2_i64, fabric_fpga_wdata_axi_m2_i65, fabric_fpga_wdata_axi_m2_i66, fabric_fpga_wdata_axi_m2_i67, fabric_fpga_wdata_axi_m2_i68, fabric_fpga_wdata_axi_m2_i69, fabric_fpga_wdata_axi_m2_i70, fabric_fpga_wdata_axi_m2_i71, fabric_fpga_wdata_axi_m2_i72, fabric_fpga_wdata_axi_m2_i73, fabric_fpga_wdata_axi_m2_i74, fabric_fpga_wdata_axi_m2_i75, fabric_fpga_wdata_axi_m2_i76, fabric_fpga_wdata_axi_m2_i77, fabric_fpga_wdata_axi_m2_i78
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+, fabric_fpga_paddr_apb_o20, fabric_fpga_paddr_apb_o21, fabric_fpga_paddr_apb_o22, fabric_fpga_paddr_apb_o23, fabric_fpga_paddr_apb_o24, fabric_fpga_paddr_apb_o25, fabric_fpga_paddr_apb_o26, fabric_fpga_paddr_apb_o27, fabric_fpga_paddr_apb_o28, fabric_fpga_paddr_apb_o29, fabric_fpga_paddr_apb_o30, fabric_fpga_paddr_apb_o31, fabric_fpga_paddr_apb_o32, fabric_fpga_penable_apb_o, fabric_fpga_psel_apb_o, fabric_fpga_pwdata_apb_o1, fabric_fpga_pwdata_apb_o2, fabric_fpga_pwdata_apb_o3, fabric_fpga_pwdata_apb_o4, fabric_fpga_pwdata_apb_o5, fabric_fpga_pwdata_apb_o6
+, fabric_fpga_pwdata_apb_o7, fabric_fpga_pwdata_apb_o8, fabric_fpga_pwdata_apb_o9, fabric_fpga_pwdata_apb_o10, fabric_fpga_pwdata_apb_o11, fabric_fpga_pwdata_apb_o12, fabric_fpga_pwdata_apb_o13, fabric_fpga_pwdata_apb_o14, fabric_fpga_pwdata_apb_o15, fabric_fpga_pwdata_apb_o16, fabric_fpga_pwdata_apb_o17, fabric_fpga_pwdata_apb_o18, fabric_fpga_pwdata_apb_o19, fabric_fpga_pwdata_apb_o20, fabric_fpga_pwdata_apb_o21, fabric_fpga_pwdata_apb_o22, fabric_fpga_pwdata_apb_o23, fabric_fpga_pwdata_apb_o24, fabric_fpga_pwdata_apb_o25, fabric_fpga_pwdata_apb_o26, fabric_fpga_pwdata_apb_o27
+, fabric_fpga_pwdata_apb_o28, fabric_fpga_pwdata_apb_o29, fabric_fpga_pwdata_apb_o30, fabric_fpga_pwdata_apb_o31, fabric_fpga_pwdata_apb_o32, fabric_fpga_pwrite_apb_o, fabric_fpga_prdata_apb_i1, fabric_fpga_prdata_apb_i2, fabric_fpga_prdata_apb_i3, fabric_fpga_prdata_apb_i4, fabric_fpga_prdata_apb_i5, fabric_fpga_prdata_apb_i6, fabric_fpga_prdata_apb_i7, fabric_fpga_prdata_apb_i8, fabric_fpga_prdata_apb_i9, fabric_fpga_prdata_apb_i10, fabric_fpga_prdata_apb_i11, fabric_fpga_prdata_apb_i12, fabric_fpga_prdata_apb_i13, fabric_fpga_prdata_apb_i14, fabric_fpga_prdata_apb_i15
+, fabric_fpga_prdata_apb_i16, fabric_fpga_prdata_apb_i17, fabric_fpga_prdata_apb_i18, fabric_fpga_prdata_apb_i19, fabric_fpga_prdata_apb_i20, fabric_fpga_prdata_apb_i21, fabric_fpga_prdata_apb_i22, fabric_fpga_prdata_apb_i23, fabric_fpga_prdata_apb_i24, fabric_fpga_prdata_apb_i25, fabric_fpga_prdata_apb_i26, fabric_fpga_prdata_apb_i27, fabric_fpga_prdata_apb_i28, fabric_fpga_prdata_apb_i29, fabric_fpga_prdata_apb_i30, fabric_fpga_prdata_apb_i31, fabric_fpga_prdata_apb_i32, fabric_fpga_pready_apb_i, fabric_fpga_pslverr_apb_i, fabric_llpp0_araddr_s_o1, fabric_llpp0_araddr_s_o2
+, fabric_llpp0_araddr_s_o3, fabric_llpp0_araddr_s_o4, fabric_llpp0_araddr_s_o5, fabric_llpp0_araddr_s_o6, fabric_llpp0_araddr_s_o7, fabric_llpp0_araddr_s_o8, fabric_llpp0_araddr_s_o9, fabric_llpp0_araddr_s_o10, fabric_llpp0_araddr_s_o11, fabric_llpp0_araddr_s_o12, fabric_llpp0_araddr_s_o13, fabric_llpp0_araddr_s_o14, fabric_llpp0_araddr_s_o15, fabric_llpp0_araddr_s_o16, fabric_llpp0_araddr_s_o17, fabric_llpp0_araddr_s_o18, fabric_llpp0_araddr_s_o19, fabric_llpp0_araddr_s_o20, fabric_llpp0_araddr_s_o21, fabric_llpp0_araddr_s_o22, fabric_llpp0_araddr_s_o23
+, fabric_llpp0_araddr_s_o24, fabric_llpp0_araddr_s_o25, fabric_llpp0_araddr_s_o26, fabric_llpp0_araddr_s_o27, fabric_llpp0_araddr_s_o28, fabric_llpp0_araddr_s_o29, fabric_llpp0_araddr_s_o30, fabric_llpp0_araddr_s_o31, fabric_llpp0_araddr_s_o32, fabric_llpp0_arburst_s_o1, fabric_llpp0_arburst_s_o2, fabric_llpp0_arcache_s_o1, fabric_llpp0_arcache_s_o2, fabric_llpp0_arcache_s_o3, fabric_llpp0_arcache_s_o4, fabric_llpp0_arid_s_o1, fabric_llpp0_arid_s_o2, fabric_llpp0_arid_s_o3, fabric_llpp0_arid_s_o4, fabric_llpp0_arid_s_o5, fabric_llpp0_arid_s_o6
+, fabric_llpp0_arid_s_o7, fabric_llpp0_arid_s_o8, fabric_llpp0_arid_s_o9, fabric_llpp0_arid_s_o10, fabric_llpp0_arid_s_o11, fabric_llpp0_arid_s_o12, fabric_llpp0_arlen_s_o1, fabric_llpp0_arlen_s_o2, fabric_llpp0_arlen_s_o3, fabric_llpp0_arlen_s_o4, fabric_llpp0_arlen_s_o5, fabric_llpp0_arlen_s_o6, fabric_llpp0_arlen_s_o7, fabric_llpp0_arlen_s_o8, fabric_llpp0_arlock_s_o, fabric_llpp0_arprot_s_o1, fabric_llpp0_arprot_s_o2, fabric_llpp0_arprot_s_o3, fabric_llpp0_arqos_s_o1, fabric_llpp0_arqos_s_o2, fabric_llpp0_arqos_s_o3
+, fabric_llpp0_arqos_s_o4, fabric_llpp0_arsize_s_o1, fabric_llpp0_arsize_s_o2, fabric_llpp0_arsize_s_o3, fabric_llpp0_arvalid_s_o, fabric_llpp0_awaddr_s_o1, fabric_llpp0_awaddr_s_o2, fabric_llpp0_awaddr_s_o3, fabric_llpp0_awaddr_s_o4, fabric_llpp0_awaddr_s_o5, fabric_llpp0_awaddr_s_o6, fabric_llpp0_awaddr_s_o7, fabric_llpp0_awaddr_s_o8, fabric_llpp0_awaddr_s_o9, fabric_llpp0_awaddr_s_o10, fabric_llpp0_awaddr_s_o11, fabric_llpp0_awaddr_s_o12, fabric_llpp0_awaddr_s_o13, fabric_llpp0_awaddr_s_o14, fabric_llpp0_awaddr_s_o15, fabric_llpp0_awaddr_s_o16
+, fabric_llpp0_awaddr_s_o17, fabric_llpp0_awaddr_s_o18, fabric_llpp0_awaddr_s_o19, fabric_llpp0_awaddr_s_o20, fabric_llpp0_awaddr_s_o21, fabric_llpp0_awaddr_s_o22, fabric_llpp0_awaddr_s_o23, fabric_llpp0_awaddr_s_o24, fabric_llpp0_awaddr_s_o25, fabric_llpp0_awaddr_s_o26, fabric_llpp0_awaddr_s_o27, fabric_llpp0_awaddr_s_o28, fabric_llpp0_awaddr_s_o29, fabric_llpp0_awaddr_s_o30, fabric_llpp0_awaddr_s_o31, fabric_llpp0_awaddr_s_o32, fabric_llpp0_awburst_s_o1, fabric_llpp0_awburst_s_o2, fabric_llpp0_awcache_s_o1, fabric_llpp0_awcache_s_o2, fabric_llpp0_awcache_s_o3
+, fabric_llpp0_awcache_s_o4, fabric_llpp0_awid_s_o1, fabric_llpp0_awid_s_o2, fabric_llpp0_awid_s_o3, fabric_llpp0_awid_s_o4, fabric_llpp0_awid_s_o5, fabric_llpp0_awid_s_o6, fabric_llpp0_awid_s_o7, fabric_llpp0_awid_s_o8, fabric_llpp0_awid_s_o9, fabric_llpp0_awid_s_o10, fabric_llpp0_awid_s_o11, fabric_llpp0_awid_s_o12, fabric_llpp0_awlen_s_o1, fabric_llpp0_awlen_s_o2, fabric_llpp0_awlen_s_o3, fabric_llpp0_awlen_s_o4, fabric_llpp0_awlen_s_o5, fabric_llpp0_awlen_s_o6, fabric_llpp0_awlen_s_o7, fabric_llpp0_awlen_s_o8
+, fabric_llpp0_awlock_s_o, fabric_llpp0_awprot_s_o1, fabric_llpp0_awprot_s_o2, fabric_llpp0_awprot_s_o3, fabric_llpp0_awqos_s_o1, fabric_llpp0_awqos_s_o2, fabric_llpp0_awqos_s_o3, fabric_llpp0_awqos_s_o4, fabric_llpp0_awsize_s_o1, fabric_llpp0_awsize_s_o2, fabric_llpp0_awsize_s_o3, fabric_llpp0_awvalid_s_o, fabric_llpp0_bready_s_o, fabric_llpp0_rready_s_o, fabric_llpp0_wdata_s_o1, fabric_llpp0_wdata_s_o2, fabric_llpp0_wdata_s_o3, fabric_llpp0_wdata_s_o4, fabric_llpp0_wdata_s_o5, fabric_llpp0_wdata_s_o6, fabric_llpp0_wdata_s_o7
+, fabric_llpp0_wdata_s_o8, fabric_llpp0_wdata_s_o9, fabric_llpp0_wdata_s_o10, fabric_llpp0_wdata_s_o11, fabric_llpp0_wdata_s_o12, fabric_llpp0_wdata_s_o13, fabric_llpp0_wdata_s_o14, fabric_llpp0_wdata_s_o15, fabric_llpp0_wdata_s_o16, fabric_llpp0_wdata_s_o17, fabric_llpp0_wdata_s_o18, fabric_llpp0_wdata_s_o19, fabric_llpp0_wdata_s_o20, fabric_llpp0_wdata_s_o21, fabric_llpp0_wdata_s_o22, fabric_llpp0_wdata_s_o23, fabric_llpp0_wdata_s_o24, fabric_llpp0_wdata_s_o25, fabric_llpp0_wdata_s_o26, fabric_llpp0_wdata_s_o27, fabric_llpp0_wdata_s_o28
+, fabric_llpp0_wdata_s_o29, fabric_llpp0_wdata_s_o30, fabric_llpp0_wdata_s_o31, fabric_llpp0_wdata_s_o32, fabric_llpp0_wlast_s_o, fabric_llpp0_wstrb_s_o1, fabric_llpp0_wstrb_s_o2, fabric_llpp0_wstrb_s_o3, fabric_llpp0_wstrb_s_o4, fabric_llpp0_wvalid_s_o, fabric_llpp0_arready_s_i, fabric_llpp0_awready_s_i, fabric_llpp0_bid_s_i1, fabric_llpp0_bid_s_i2, fabric_llpp0_bid_s_i3, fabric_llpp0_bid_s_i4, fabric_llpp0_bid_s_i5, fabric_llpp0_bid_s_i6, fabric_llpp0_bid_s_i7, fabric_llpp0_bid_s_i8, fabric_llpp0_bid_s_i9
+, fabric_llpp0_bid_s_i10, fabric_llpp0_bid_s_i11, fabric_llpp0_bid_s_i12, fabric_llpp0_bresp_s_i1, fabric_llpp0_bresp_s_i2, fabric_llpp0_bvalid_s_i, fabric_llpp0_rdata_s_i1, fabric_llpp0_rdata_s_i2, fabric_llpp0_rdata_s_i3, fabric_llpp0_rdata_s_i4, fabric_llpp0_rdata_s_i5, fabric_llpp0_rdata_s_i6, fabric_llpp0_rdata_s_i7, fabric_llpp0_rdata_s_i8, fabric_llpp0_rdata_s_i9, fabric_llpp0_rdata_s_i10, fabric_llpp0_rdata_s_i11, fabric_llpp0_rdata_s_i12, fabric_llpp0_rdata_s_i13, fabric_llpp0_rdata_s_i14, fabric_llpp0_rdata_s_i15
+, fabric_llpp0_rdata_s_i16, fabric_llpp0_rdata_s_i17, fabric_llpp0_rdata_s_i18, fabric_llpp0_rdata_s_i19, fabric_llpp0_rdata_s_i20, fabric_llpp0_rdata_s_i21, fabric_llpp0_rdata_s_i22, fabric_llpp0_rdata_s_i23, fabric_llpp0_rdata_s_i24, fabric_llpp0_rdata_s_i25, fabric_llpp0_rdata_s_i26, fabric_llpp0_rdata_s_i27, fabric_llpp0_rdata_s_i28, fabric_llpp0_rdata_s_i29, fabric_llpp0_rdata_s_i30, fabric_llpp0_rdata_s_i31, fabric_llpp0_rdata_s_i32, fabric_llpp0_rid_s_i1, fabric_llpp0_rid_s_i2, fabric_llpp0_rid_s_i3, fabric_llpp0_rid_s_i4
+, fabric_llpp0_rid_s_i5, fabric_llpp0_rid_s_i6, fabric_llpp0_rid_s_i7, fabric_llpp0_rid_s_i8, fabric_llpp0_rid_s_i9, fabric_llpp0_rid_s_i10, fabric_llpp0_rid_s_i11, fabric_llpp0_rid_s_i12, fabric_llpp0_rlast_s_i, fabric_llpp0_rresp_s_i1, fabric_llpp0_rresp_s_i2, fabric_llpp0_rvalid_s_i, fabric_llpp0_wready_s_i, fabric_llpp1_araddr_s_o1, fabric_llpp1_araddr_s_o2, fabric_llpp1_araddr_s_o3, fabric_llpp1_araddr_s_o4, fabric_llpp1_araddr_s_o5, fabric_llpp1_araddr_s_o6, fabric_llpp1_araddr_s_o7, fabric_llpp1_araddr_s_o8
+, fabric_llpp1_araddr_s_o9, fabric_llpp1_araddr_s_o10, fabric_llpp1_araddr_s_o11, fabric_llpp1_araddr_s_o12, fabric_llpp1_araddr_s_o13, fabric_llpp1_araddr_s_o14, fabric_llpp1_araddr_s_o15, fabric_llpp1_araddr_s_o16, fabric_llpp1_araddr_s_o17, fabric_llpp1_araddr_s_o18, fabric_llpp1_araddr_s_o19, fabric_llpp1_araddr_s_o20, fabric_llpp1_araddr_s_o21, fabric_llpp1_araddr_s_o22, fabric_llpp1_araddr_s_o23, fabric_llpp1_araddr_s_o24, fabric_llpp1_araddr_s_o25, fabric_llpp1_araddr_s_o26, fabric_llpp1_araddr_s_o27, fabric_llpp1_araddr_s_o28, fabric_llpp1_araddr_s_o29
+, fabric_llpp1_araddr_s_o30, fabric_llpp1_araddr_s_o31, fabric_llpp1_araddr_s_o32, fabric_llpp1_arburst_s_o1, fabric_llpp1_arburst_s_o2, fabric_llpp1_arcache_s_o1, fabric_llpp1_arcache_s_o2, fabric_llpp1_arcache_s_o3, fabric_llpp1_arcache_s_o4, fabric_llpp1_arid_s_o1, fabric_llpp1_arid_s_o2, fabric_llpp1_arid_s_o3, fabric_llpp1_arid_s_o4, fabric_llpp1_arid_s_o5, fabric_llpp1_arid_s_o6, fabric_llpp1_arid_s_o7, fabric_llpp1_arid_s_o8, fabric_llpp1_arid_s_o9, fabric_llpp1_arid_s_o10, fabric_llpp1_arid_s_o11, fabric_llpp1_arid_s_o12
+, fabric_llpp1_arlen_s_o1, fabric_llpp1_arlen_s_o2, fabric_llpp1_arlen_s_o3, fabric_llpp1_arlen_s_o4, fabric_llpp1_arlen_s_o5, fabric_llpp1_arlen_s_o6, fabric_llpp1_arlen_s_o7, fabric_llpp1_arlen_s_o8, fabric_llpp1_arlock_s_o, fabric_llpp1_arprot_s_o1, fabric_llpp1_arprot_s_o2, fabric_llpp1_arprot_s_o3, fabric_llpp1_arqos_s1_o1, fabric_llpp1_arqos_s1_o2, fabric_llpp1_arqos_s1_o3, fabric_llpp1_arqos_s1_o4, fabric_llpp1_arsize_s_o1, fabric_llpp1_arsize_s_o2, fabric_llpp1_arsize_s_o3, fabric_llpp1_arvalid_s_o, fabric_llpp1_awaddr_s_o1
+, fabric_llpp1_awaddr_s_o2, fabric_llpp1_awaddr_s_o3, fabric_llpp1_awaddr_s_o4, fabric_llpp1_awaddr_s_o5, fabric_llpp1_awaddr_s_o6, fabric_llpp1_awaddr_s_o7, fabric_llpp1_awaddr_s_o8, fabric_llpp1_awaddr_s_o9, fabric_llpp1_awaddr_s_o10, fabric_llpp1_awaddr_s_o11, fabric_llpp1_awaddr_s_o12, fabric_llpp1_awaddr_s_o13, fabric_llpp1_awaddr_s_o14, fabric_llpp1_awaddr_s_o15, fabric_llpp1_awaddr_s_o16, fabric_llpp1_awaddr_s_o17, fabric_llpp1_awaddr_s_o18, fabric_llpp1_awaddr_s_o19, fabric_llpp1_awaddr_s_o20, fabric_llpp1_awaddr_s_o21, fabric_llpp1_awaddr_s_o22
+, fabric_llpp1_awaddr_s_o23, fabric_llpp1_awaddr_s_o24, fabric_llpp1_awaddr_s_o25, fabric_llpp1_awaddr_s_o26, fabric_llpp1_awaddr_s_o27, fabric_llpp1_awaddr_s_o28, fabric_llpp1_awaddr_s_o29, fabric_llpp1_awaddr_s_o30, fabric_llpp1_awaddr_s_o31, fabric_llpp1_awaddr_s_o32, fabric_llpp1_awburst_s_o1, fabric_llpp1_awburst_s_o2, fabric_llpp1_awcache_s_o1, fabric_llpp1_awcache_s_o2, fabric_llpp1_awcache_s_o3, fabric_llpp1_awcache_s_o4, fabric_llpp1_awid_s_o1, fabric_llpp1_awid_s_o2, fabric_llpp1_awid_s_o3, fabric_llpp1_awid_s_o4, fabric_llpp1_awid_s_o5
+, fabric_llpp1_awid_s_o6, fabric_llpp1_awid_s_o7, fabric_llpp1_awid_s_o8, fabric_llpp1_awid_s_o9, fabric_llpp1_awid_s_o10, fabric_llpp1_awid_s_o11, fabric_llpp1_awid_s_o12, fabric_llpp1_awlen_s_o1, fabric_llpp1_awlen_s_o2, fabric_llpp1_awlen_s_o3, fabric_llpp1_awlen_s_o4, fabric_llpp1_awlen_s_o5, fabric_llpp1_awlen_s_o6, fabric_llpp1_awlen_s_o7, fabric_llpp1_awlen_s_o8, fabric_llpp1_awlock_s_o, fabric_llpp1_awprot_s_o1, fabric_llpp1_awprot_s_o2, fabric_llpp1_awprot_s_o3, fabric_llpp1_awqos_s_o1, fabric_llpp1_awqos_s_o2
+, fabric_llpp1_awqos_s_o3, fabric_llpp1_awqos_s_o4, fabric_llpp1_awsize_s_o1, fabric_llpp1_awsize_s_o2, fabric_llpp1_awsize_s_o3, fabric_llpp1_awvalid_s_o, fabric_llpp1_bready_s_o, fabric_llpp1_rready_s_o, fabric_llpp1_wdata_s_o1, fabric_llpp1_wdata_s_o2, fabric_llpp1_wdata_s_o3, fabric_llpp1_wdata_s_o4, fabric_llpp1_wdata_s_o5, fabric_llpp1_wdata_s_o6, fabric_llpp1_wdata_s_o7, fabric_llpp1_wdata_s_o8, fabric_llpp1_wdata_s_o9, fabric_llpp1_wdata_s_o10, fabric_llpp1_wdata_s_o11, fabric_llpp1_wdata_s_o12, fabric_llpp1_wdata_s_o13
+, fabric_llpp1_wdata_s_o14, fabric_llpp1_wdata_s_o15, fabric_llpp1_wdata_s_o16, fabric_llpp1_wdata_s_o17, fabric_llpp1_wdata_s_o18, fabric_llpp1_wdata_s_o19, fabric_llpp1_wdata_s_o20, fabric_llpp1_wdata_s_o21, fabric_llpp1_wdata_s_o22, fabric_llpp1_wdata_s_o23, fabric_llpp1_wdata_s_o24, fabric_llpp1_wdata_s_o25, fabric_llpp1_wdata_s_o26, fabric_llpp1_wdata_s_o27, fabric_llpp1_wdata_s_o28, fabric_llpp1_wdata_s_o29, fabric_llpp1_wdata_s_o30, fabric_llpp1_wdata_s_o31, fabric_llpp1_wdata_s_o32, fabric_llpp1_wlast_s_o, fabric_llpp1_wstrb_s_o1
+, fabric_llpp1_wstrb_s_o2, fabric_llpp1_wstrb_s_o3, fabric_llpp1_wstrb_s_o4, fabric_llpp1_wvalid_s_o, fabric_llpp1_arready_s_i, fabric_llpp1_awready_s_i, fabric_llpp1_bid_s_i1, fabric_llpp1_bid_s_i2, fabric_llpp1_bid_s_i3, fabric_llpp1_bid_s_i4, fabric_llpp1_bid_s_i5, fabric_llpp1_bid_s_i6, fabric_llpp1_bid_s_i7, fabric_llpp1_bid_s_i8, fabric_llpp1_bid_s_i9, fabric_llpp1_bid_s_i10, fabric_llpp1_bid_s_i11, fabric_llpp1_bid_s_i12, fabric_llpp1_bresp_s_i1, fabric_llpp1_bresp_s_i2, fabric_llpp1_bvalid_s_i
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+, fabric_llpp2_rdata_s_i7, fabric_llpp2_rdata_s_i8, fabric_llpp2_rdata_s_i9, fabric_llpp2_rdata_s_i10, fabric_llpp2_rdata_s_i11, fabric_llpp2_rdata_s_i12, fabric_llpp2_rdata_s_i13, fabric_llpp2_rdata_s_i14, fabric_llpp2_rdata_s_i15, fabric_llpp2_rdata_s_i16, fabric_llpp2_rdata_s_i17, fabric_llpp2_rdata_s_i18, fabric_llpp2_rdata_s_i19, fabric_llpp2_rdata_s_i20, fabric_llpp2_rdata_s_i21, fabric_llpp2_rdata_s_i22, fabric_llpp2_rdata_s_i23, fabric_llpp2_rdata_s_i24, fabric_llpp2_rdata_s_i25, fabric_llpp2_rdata_s_i26, fabric_llpp2_rdata_s_i27
+, fabric_llpp2_rdata_s_i28, fabric_llpp2_rdata_s_i29, fabric_llpp2_rdata_s_i30, fabric_llpp2_rdata_s_i31, fabric_llpp2_rdata_s_i32, fabric_llpp2_rid_s_i1, fabric_llpp2_rid_s_i2, fabric_llpp2_rid_s_i3, fabric_llpp2_rid_s_i4, fabric_llpp2_rid_s_i5, fabric_llpp2_rid_s_i6, fabric_llpp2_rid_s_i7, fabric_llpp2_rid_s_i8, fabric_llpp2_rid_s_i9, fabric_llpp2_rid_s_i10, fabric_llpp2_rid_s_i11, fabric_llpp2_rid_s_i12, fabric_llpp2_rlast_s_i, fabric_llpp2_rresp_s_i1, fabric_llpp2_rresp_s_i2, fabric_llpp2_rvalid_s_i
+, fabric_llpp2_wready_s_i, fabric_llpp3_araddr_s_o1, fabric_llpp3_araddr_s_o2, fabric_llpp3_araddr_s_o3, fabric_llpp3_araddr_s_o4, fabric_llpp3_araddr_s_o5, fabric_llpp3_araddr_s_o6, fabric_llpp3_araddr_s_o7, fabric_llpp3_araddr_s_o8, fabric_llpp3_araddr_s_o9, fabric_llpp3_araddr_s_o10, fabric_llpp3_araddr_s_o11, fabric_llpp3_araddr_s_o12, fabric_llpp3_araddr_s_o13, fabric_llpp3_araddr_s_o14, fabric_llpp3_araddr_s_o15, fabric_llpp3_araddr_s_o16, fabric_llpp3_araddr_s_o17, fabric_llpp3_araddr_s_o18, fabric_llpp3_araddr_s_o19, fabric_llpp3_araddr_s_o20
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+, fabric_llpp3_arid_s_o4, fabric_llpp3_arid_s_o5, fabric_llpp3_arid_s_o6, fabric_llpp3_arid_s_o7, fabric_llpp3_arid_s_o8, fabric_llpp3_arid_s_o9, fabric_llpp3_arid_s_o10, fabric_llpp3_arid_s_o11, fabric_llpp3_arid_s_o12, fabric_llpp3_arlen_s_o1, fabric_llpp3_arlen_s_o2, fabric_llpp3_arlen_s_o3, fabric_llpp3_arlen_s_o4, fabric_llpp3_arlen_s_o5, fabric_llpp3_arlen_s_o6, fabric_llpp3_arlen_s_o7, fabric_llpp3_arlen_s_o8, fabric_llpp3_arlock_s_o, fabric_llpp3_arprot_s_o1, fabric_llpp3_arprot_s_o2, fabric_llpp3_arprot_s_o3
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+, fabric_llpp3_awaddr_s_o14, fabric_llpp3_awaddr_s_o15, fabric_llpp3_awaddr_s_o16, fabric_llpp3_awaddr_s_o17, fabric_llpp3_awaddr_s_o18, fabric_llpp3_awaddr_s_o19, fabric_llpp3_awaddr_s_o20, fabric_llpp3_awaddr_s_o21, fabric_llpp3_awaddr_s_o22, fabric_llpp3_awaddr_s_o23, fabric_llpp3_awaddr_s_o24, fabric_llpp3_awaddr_s_o25, fabric_llpp3_awaddr_s_o26, fabric_llpp3_awaddr_s_o27, fabric_llpp3_awaddr_s_o28, fabric_llpp3_awaddr_s_o29, fabric_llpp3_awaddr_s_o30, fabric_llpp3_awaddr_s_o31, fabric_llpp3_awaddr_s_o32, fabric_llpp3_awburst_s_o1, fabric_llpp3_awburst_s_o2
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+, fabric_llpp3_bid_s_i7, fabric_llpp3_bid_s_i8, fabric_llpp3_bid_s_i9, fabric_llpp3_bid_s_i10, fabric_llpp3_bid_s_i11, fabric_llpp3_bid_s_i12, fabric_llpp3_bresp_s_i1, fabric_llpp3_bresp_s_i2, fabric_llpp3_bvalid_s_i, fabric_llpp3_rdata_s_i1, fabric_llpp3_rdata_s_i2, fabric_llpp3_rdata_s_i3, fabric_llpp3_rdata_s_i4, fabric_llpp3_rdata_s_i5, fabric_llpp3_rdata_s_i6, fabric_llpp3_rdata_s_i7, fabric_llpp3_rdata_s_i8, fabric_llpp3_rdata_s_i9, fabric_llpp3_rdata_s_i10, fabric_llpp3_rdata_s_i11, fabric_llpp3_rdata_s_i12
+, fabric_llpp3_rdata_s_i13, fabric_llpp3_rdata_s_i14, fabric_llpp3_rdata_s_i15, fabric_llpp3_rdata_s_i16, fabric_llpp3_rdata_s_i17, fabric_llpp3_rdata_s_i18, fabric_llpp3_rdata_s_i19, fabric_llpp3_rdata_s_i20, fabric_llpp3_rdata_s_i21, fabric_llpp3_rdata_s_i22, fabric_llpp3_rdata_s_i23, fabric_llpp3_rdata_s_i24, fabric_llpp3_rdata_s_i25, fabric_llpp3_rdata_s_i26, fabric_llpp3_rdata_s_i27, fabric_llpp3_rdata_s_i28, fabric_llpp3_rdata_s_i29, fabric_llpp3_rdata_s_i30, fabric_llpp3_rdata_s_i31, fabric_llpp3_rdata_s_i32, fabric_llpp3_rid_s_i1
+, fabric_llpp3_rid_s_i2, fabric_llpp3_rid_s_i3, fabric_llpp3_rid_s_i4, fabric_llpp3_rid_s_i5, fabric_llpp3_rid_s_i6, fabric_llpp3_rid_s_i7, fabric_llpp3_rid_s_i8, fabric_llpp3_rid_s_i9, fabric_llpp3_rid_s_i10, fabric_llpp3_rid_s_i11, fabric_llpp3_rid_s_i12, fabric_llpp3_rlast_s_i, fabric_llpp3_rresp_s_i1, fabric_llpp3_rresp_s_i2, fabric_llpp3_rvalid_s_i, fabric_llpp3_wready_s_i, fabric_qos_pprdata_o1, fabric_qos_pprdata_o2, fabric_qos_pprdata_o3, fabric_qos_pprdata_o4, fabric_qos_pprdata_o5
+, fabric_qos_pprdata_o6, fabric_qos_pprdata_o7, fabric_qos_pprdata_o8, fabric_qos_pprdata_o9, fabric_qos_pprdata_o10, fabric_qos_pprdata_o11, fabric_qos_pprdata_o12, fabric_qos_pprdata_o13, fabric_qos_pprdata_o14, fabric_qos_pprdata_o15, fabric_qos_pprdata_o16, fabric_qos_pprdata_o17, fabric_qos_pprdata_o18, fabric_qos_pprdata_o19, fabric_qos_pprdata_o20, fabric_qos_pprdata_o21, fabric_qos_pprdata_o22, fabric_qos_pprdata_o23, fabric_qos_pprdata_o24, fabric_qos_pprdata_o25, fabric_qos_pprdata_o26
+, fabric_qos_pprdata_o27, fabric_qos_pprdata_o28, fabric_qos_pprdata_o29, fabric_qos_pprdata_o30, fabric_qos_pprdata_o31, fabric_qos_pprdata_o32, fabric_qos_ppready_o, fabric_qos_ppslverr_o, fabric_qos_pclk_i, fabric_qos_ppaddr_i1, fabric_qos_ppaddr_i2, fabric_qos_ppaddr_i3, fabric_qos_ppaddr_i4, fabric_qos_ppaddr_i5, fabric_qos_ppaddr_i6, fabric_qos_ppaddr_i7, fabric_qos_ppaddr_i8, fabric_qos_ppaddr_i9, fabric_qos_ppaddr_i10, fabric_qos_ppaddr_i11, fabric_qos_ppaddr_i12
+, fabric_qos_ppaddr_i13, fabric_qos_ppaddr_i14, fabric_qos_ppaddr_i15, fabric_qos_ppaddr_i16, fabric_qos_ppaddr_i17, fabric_qos_ppaddr_i18, fabric_qos_ppaddr_i19, fabric_qos_ppaddr_i20, fabric_qos_ppaddr_i21, fabric_qos_ppaddr_i22, fabric_qos_ppaddr_i23, fabric_qos_ppaddr_i24, fabric_qos_ppaddr_i25, fabric_qos_ppaddr_i26, fabric_qos_ppaddr_i27, fabric_qos_ppaddr_i28, fabric_qos_ppaddr_i29, fabric_qos_ppaddr_i30, fabric_qos_ppaddr_i31, fabric_qos_ppaddr_i32, fabric_qos_ppenable_i
+, fabric_qos_ppwdata_i1, fabric_qos_ppwdata_i2, fabric_qos_ppwdata_i3, fabric_qos_ppwdata_i4, fabric_qos_ppwdata_i5, fabric_qos_ppwdata_i6, fabric_qos_ppwdata_i7, fabric_qos_ppwdata_i8, fabric_qos_ppwdata_i9, fabric_qos_ppwdata_i10, fabric_qos_ppwdata_i11, fabric_qos_ppwdata_i12, fabric_qos_ppwdata_i13, fabric_qos_ppwdata_i14, fabric_qos_ppwdata_i15, fabric_qos_ppwdata_i16, fabric_qos_ppwdata_i17, fabric_qos_ppwdata_i18, fabric_qos_ppwdata_i19, fabric_qos_ppwdata_i20, fabric_qos_ppwdata_i21
+, fabric_qos_ppwdata_i22, fabric_qos_ppwdata_i23, fabric_qos_ppwdata_i24, fabric_qos_ppwdata_i25, fabric_qos_ppwdata_i26, fabric_qos_ppwdata_i27, fabric_qos_ppwdata_i28, fabric_qos_ppwdata_i29, fabric_qos_ppwdata_i30, fabric_qos_ppwdata_i31, fabric_qos_ppwdata_i32, fabric_qos_ppwrite_i, fabric_qos_presetn_i, fabric_qos_psel_i, fabric_tnd_hssl_flushin_o, fabric_tnd_hssl_trigin_o, fabric_tnd_fpga_apb_master_paddr_o1, fabric_tnd_fpga_apb_master_paddr_o2, fabric_tnd_fpga_apb_master_paddr_o3, fabric_tnd_fpga_apb_master_paddr_o4, fabric_tnd_fpga_apb_master_paddr_o5
+, fabric_tnd_fpga_apb_master_paddr_o6, fabric_tnd_fpga_apb_master_paddr_o7, fabric_tnd_fpga_apb_master_paddr_o8, fabric_tnd_fpga_apb_master_paddr_o9, fabric_tnd_fpga_apb_master_paddr_o10, fabric_tnd_fpga_apb_master_paddr_o11, fabric_tnd_fpga_apb_master_paddr_o12, fabric_tnd_fpga_apb_master_paddr_o13, fabric_tnd_fpga_apb_master_paddr_o14, fabric_tnd_fpga_apb_master_paddr_o15, fabric_tnd_fpga_apb_master_paddr_o16, fabric_tnd_fpga_apb_master_paddr_o17, fabric_tnd_fpga_apb_master_paddr_o18, fabric_tnd_fpga_apb_master_paddr_o19, fabric_tnd_fpga_apb_master_paddr_o20, fabric_tnd_fpga_apb_master_paddr_o21, fabric_tnd_fpga_apb_master_paddr_o22, fabric_tnd_fpga_apb_master_paddr_o23, fabric_tnd_fpga_apb_master_paddr_o24, fabric_tnd_fpga_apb_master_paddr_o25, fabric_tnd_fpga_apb_master_paddr_o26
+, fabric_tnd_fpga_apb_master_paddr_o27, fabric_tnd_fpga_apb_master_paddr_o28, fabric_tnd_fpga_apb_master_paddr_o29, fabric_tnd_fpga_apb_master_paddr_o30, fabric_tnd_fpga_apb_master_paddr_o31, fabric_tnd_fpga_apb_master_paddr_o32, fabric_tnd_fpga_apb_master_penable_o, fabric_tnd_fpga_apb_master_psel_o, fabric_tnd_fpga_apb_master_pwdata_o1, fabric_tnd_fpga_apb_master_pwdata_o2, fabric_tnd_fpga_apb_master_pwdata_o3, fabric_tnd_fpga_apb_master_pwdata_o4, fabric_tnd_fpga_apb_master_pwdata_o5, fabric_tnd_fpga_apb_master_pwdata_o6, fabric_tnd_fpga_apb_master_pwdata_o7, fabric_tnd_fpga_apb_master_pwdata_o8, fabric_tnd_fpga_apb_master_pwdata_o9, fabric_tnd_fpga_apb_master_pwdata_o10, fabric_tnd_fpga_apb_master_pwdata_o11, fabric_tnd_fpga_apb_master_pwdata_o12, fabric_tnd_fpga_apb_master_pwdata_o13
+, fabric_tnd_fpga_apb_master_pwdata_o14, fabric_tnd_fpga_apb_master_pwdata_o15, fabric_tnd_fpga_apb_master_pwdata_o16, fabric_tnd_fpga_apb_master_pwdata_o17, fabric_tnd_fpga_apb_master_pwdata_o18, fabric_tnd_fpga_apb_master_pwdata_o19, fabric_tnd_fpga_apb_master_pwdata_o20, fabric_tnd_fpga_apb_master_pwdata_o21, fabric_tnd_fpga_apb_master_pwdata_o22, fabric_tnd_fpga_apb_master_pwdata_o23, fabric_tnd_fpga_apb_master_pwdata_o24, fabric_tnd_fpga_apb_master_pwdata_o25, fabric_tnd_fpga_apb_master_pwdata_o26, fabric_tnd_fpga_apb_master_pwdata_o27, fabric_tnd_fpga_apb_master_pwdata_o28, fabric_tnd_fpga_apb_master_pwdata_o29, fabric_tnd_fpga_apb_master_pwdata_o30, fabric_tnd_fpga_apb_master_pwdata_o31, fabric_tnd_fpga_apb_master_pwdata_o32, fabric_tnd_fpga_apb_master_pwrite_o, fabric_tnd_fpga_atb_master_afvalid_o
+, fabric_tnd_fpga_atb_master_atready_o, fabric_tnd_fpga_atb_master_syncreq_o, fabric_tnd_hssl_apb_master_paddr_o1, fabric_tnd_hssl_apb_master_paddr_o2, fabric_tnd_hssl_apb_master_paddr_o3, fabric_tnd_hssl_apb_master_paddr_o4, fabric_tnd_hssl_apb_master_paddr_o5, fabric_tnd_hssl_apb_master_paddr_o6, fabric_tnd_hssl_apb_master_paddr_o7, fabric_tnd_hssl_apb_master_paddr_o8, fabric_tnd_hssl_apb_master_paddr_o9, fabric_tnd_hssl_apb_master_paddr_o10, fabric_tnd_hssl_apb_master_paddr_o11, fabric_tnd_hssl_apb_master_paddr_o12, fabric_tnd_hssl_apb_master_paddr_o13, fabric_tnd_hssl_apb_master_paddr_o14, fabric_tnd_hssl_apb_master_paddr_o15, fabric_tnd_hssl_apb_master_paddr_o16, fabric_tnd_hssl_apb_master_paddr_o17, fabric_tnd_hssl_apb_master_paddr_o18, fabric_tnd_hssl_apb_master_paddr_o19
+, fabric_tnd_hssl_apb_master_paddr_o20, fabric_tnd_hssl_apb_master_paddr_o21, fabric_tnd_hssl_apb_master_paddr_o22, fabric_tnd_hssl_apb_master_paddr_o23, fabric_tnd_hssl_apb_master_paddr_o24, fabric_tnd_hssl_apb_master_paddr_o25, fabric_tnd_hssl_apb_master_paddr_o26, fabric_tnd_hssl_apb_master_paddr_o27, fabric_tnd_hssl_apb_master_paddr_o28, fabric_tnd_hssl_apb_master_paddr_o29, fabric_tnd_hssl_apb_master_paddr_o30, fabric_tnd_hssl_apb_master_paddr_o31, fabric_tnd_hssl_apb_master_paddr_o32, fabric_tnd_hssl_apb_master_penable_o, fabric_tnd_hssl_apb_master_psel_o, fabric_tnd_hssl_apb_master_pwdata_o1, fabric_tnd_hssl_apb_master_pwdata_o2, fabric_tnd_hssl_apb_master_pwdata_o3, fabric_tnd_hssl_apb_master_pwdata_o4, fabric_tnd_hssl_apb_master_pwdata_o5, fabric_tnd_hssl_apb_master_pwdata_o6
+, fabric_tnd_hssl_apb_master_pwdata_o7, fabric_tnd_hssl_apb_master_pwdata_o8, fabric_tnd_hssl_apb_master_pwdata_o9, fabric_tnd_hssl_apb_master_pwdata_o10, fabric_tnd_hssl_apb_master_pwdata_o11, fabric_tnd_hssl_apb_master_pwdata_o12, fabric_tnd_hssl_apb_master_pwdata_o13, fabric_tnd_hssl_apb_master_pwdata_o14, fabric_tnd_hssl_apb_master_pwdata_o15, fabric_tnd_hssl_apb_master_pwdata_o16, fabric_tnd_hssl_apb_master_pwdata_o17, fabric_tnd_hssl_apb_master_pwdata_o18, fabric_tnd_hssl_apb_master_pwdata_o19, fabric_tnd_hssl_apb_master_pwdata_o20, fabric_tnd_hssl_apb_master_pwdata_o21, fabric_tnd_hssl_apb_master_pwdata_o22, fabric_tnd_hssl_apb_master_pwdata_o23, fabric_tnd_hssl_apb_master_pwdata_o24, fabric_tnd_hssl_apb_master_pwdata_o25, fabric_tnd_hssl_apb_master_pwdata_o26, fabric_tnd_hssl_apb_master_pwdata_o27
+, fabric_tnd_hssl_apb_master_pwdata_o28, fabric_tnd_hssl_apb_master_pwdata_o29, fabric_tnd_hssl_apb_master_pwdata_o30, fabric_tnd_hssl_apb_master_pwdata_o31, fabric_tnd_hssl_apb_master_pwdata_o32, fabric_tnd_hssl_apb_master_pwrite_o, fabric_tnd_hssl_atb_master_afready_o, fabric_tnd_hssl_atb_master_atbytes_o1, fabric_tnd_hssl_atb_master_atbytes_o2, fabric_tnd_hssl_atb_master_atbytes_o3, fabric_tnd_hssl_atb_master_atbytes_o4, fabric_tnd_hssl_atb_master_atdata_o1, fabric_tnd_hssl_atb_master_atdata_o2, fabric_tnd_hssl_atb_master_atdata_o3, fabric_tnd_hssl_atb_master_atdata_o4, fabric_tnd_hssl_atb_master_atdata_o5, fabric_tnd_hssl_atb_master_atdata_o6, fabric_tnd_hssl_atb_master_atdata_o7, fabric_tnd_hssl_atb_master_atdata_o8, fabric_tnd_hssl_atb_master_atdata_o9, fabric_tnd_hssl_atb_master_atdata_o10
+, fabric_tnd_hssl_atb_master_atdata_o11, fabric_tnd_hssl_atb_master_atdata_o12, fabric_tnd_hssl_atb_master_atdata_o13, fabric_tnd_hssl_atb_master_atdata_o14, fabric_tnd_hssl_atb_master_atdata_o15, fabric_tnd_hssl_atb_master_atdata_o16, fabric_tnd_hssl_atb_master_atdata_o17, fabric_tnd_hssl_atb_master_atdata_o18, fabric_tnd_hssl_atb_master_atdata_o19, fabric_tnd_hssl_atb_master_atdata_o20, fabric_tnd_hssl_atb_master_atdata_o21, fabric_tnd_hssl_atb_master_atdata_o22, fabric_tnd_hssl_atb_master_atdata_o23, fabric_tnd_hssl_atb_master_atdata_o24, fabric_tnd_hssl_atb_master_atdata_o25, fabric_tnd_hssl_atb_master_atdata_o26, fabric_tnd_hssl_atb_master_atdata_o27, fabric_tnd_hssl_atb_master_atdata_o28, fabric_tnd_hssl_atb_master_atdata_o29, fabric_tnd_hssl_atb_master_atdata_o30, fabric_tnd_hssl_atb_master_atdata_o31
+, fabric_tnd_hssl_atb_master_atdata_o32, fabric_tnd_hssl_atb_master_atdata_o33, fabric_tnd_hssl_atb_master_atdata_o34, fabric_tnd_hssl_atb_master_atdata_o35, fabric_tnd_hssl_atb_master_atdata_o36, fabric_tnd_hssl_atb_master_atdata_o37, fabric_tnd_hssl_atb_master_atdata_o38, fabric_tnd_hssl_atb_master_atdata_o39, fabric_tnd_hssl_atb_master_atdata_o40, fabric_tnd_hssl_atb_master_atdata_o41, fabric_tnd_hssl_atb_master_atdata_o42, fabric_tnd_hssl_atb_master_atdata_o43, fabric_tnd_hssl_atb_master_atdata_o44, fabric_tnd_hssl_atb_master_atdata_o45, fabric_tnd_hssl_atb_master_atdata_o46, fabric_tnd_hssl_atb_master_atdata_o47, fabric_tnd_hssl_atb_master_atdata_o48, fabric_tnd_hssl_atb_master_atdata_o49, fabric_tnd_hssl_atb_master_atdata_o50, fabric_tnd_hssl_atb_master_atdata_o51, fabric_tnd_hssl_atb_master_atdata_o52
+, fabric_tnd_hssl_atb_master_atdata_o53, fabric_tnd_hssl_atb_master_atdata_o54, fabric_tnd_hssl_atb_master_atdata_o55, fabric_tnd_hssl_atb_master_atdata_o56, fabric_tnd_hssl_atb_master_atdata_o57, fabric_tnd_hssl_atb_master_atdata_o58, fabric_tnd_hssl_atb_master_atdata_o59, fabric_tnd_hssl_atb_master_atdata_o60, fabric_tnd_hssl_atb_master_atdata_o61, fabric_tnd_hssl_atb_master_atdata_o62, fabric_tnd_hssl_atb_master_atdata_o63, fabric_tnd_hssl_atb_master_atdata_o64, fabric_tnd_hssl_atb_master_atdata_o65, fabric_tnd_hssl_atb_master_atdata_o66, fabric_tnd_hssl_atb_master_atdata_o67, fabric_tnd_hssl_atb_master_atdata_o68, fabric_tnd_hssl_atb_master_atdata_o69, fabric_tnd_hssl_atb_master_atdata_o70, fabric_tnd_hssl_atb_master_atdata_o71, fabric_tnd_hssl_atb_master_atdata_o72, fabric_tnd_hssl_atb_master_atdata_o73
+, fabric_tnd_hssl_atb_master_atdata_o74, fabric_tnd_hssl_atb_master_atdata_o75, fabric_tnd_hssl_atb_master_atdata_o76, fabric_tnd_hssl_atb_master_atdata_o77, fabric_tnd_hssl_atb_master_atdata_o78, fabric_tnd_hssl_atb_master_atdata_o79, fabric_tnd_hssl_atb_master_atdata_o80, fabric_tnd_hssl_atb_master_atdata_o81, fabric_tnd_hssl_atb_master_atdata_o82, fabric_tnd_hssl_atb_master_atdata_o83, fabric_tnd_hssl_atb_master_atdata_o84, fabric_tnd_hssl_atb_master_atdata_o85, fabric_tnd_hssl_atb_master_atdata_o86, fabric_tnd_hssl_atb_master_atdata_o87, fabric_tnd_hssl_atb_master_atdata_o88, fabric_tnd_hssl_atb_master_atdata_o89, fabric_tnd_hssl_atb_master_atdata_o90, fabric_tnd_hssl_atb_master_atdata_o91, fabric_tnd_hssl_atb_master_atdata_o92, fabric_tnd_hssl_atb_master_atdata_o93, fabric_tnd_hssl_atb_master_atdata_o94
+, fabric_tnd_hssl_atb_master_atdata_o95, fabric_tnd_hssl_atb_master_atdata_o96, fabric_tnd_hssl_atb_master_atdata_o97, fabric_tnd_hssl_atb_master_atdata_o98, fabric_tnd_hssl_atb_master_atdata_o99, fabric_tnd_hssl_atb_master_atdata_o100, fabric_tnd_hssl_atb_master_atdata_o101, fabric_tnd_hssl_atb_master_atdata_o102, fabric_tnd_hssl_atb_master_atdata_o103, fabric_tnd_hssl_atb_master_atdata_o104, fabric_tnd_hssl_atb_master_atdata_o105, fabric_tnd_hssl_atb_master_atdata_o106, fabric_tnd_hssl_atb_master_atdata_o107, fabric_tnd_hssl_atb_master_atdata_o108, fabric_tnd_hssl_atb_master_atdata_o109, fabric_tnd_hssl_atb_master_atdata_o110, fabric_tnd_hssl_atb_master_atdata_o111, fabric_tnd_hssl_atb_master_atdata_o112, fabric_tnd_hssl_atb_master_atdata_o113, fabric_tnd_hssl_atb_master_atdata_o114, fabric_tnd_hssl_atb_master_atdata_o115
+, fabric_tnd_hssl_atb_master_atdata_o116, fabric_tnd_hssl_atb_master_atdata_o117, fabric_tnd_hssl_atb_master_atdata_o118, fabric_tnd_hssl_atb_master_atdata_o119, fabric_tnd_hssl_atb_master_atdata_o120, fabric_tnd_hssl_atb_master_atdata_o121, fabric_tnd_hssl_atb_master_atdata_o122, fabric_tnd_hssl_atb_master_atdata_o123, fabric_tnd_hssl_atb_master_atdata_o124, fabric_tnd_hssl_atb_master_atdata_o125, fabric_tnd_hssl_atb_master_atdata_o126, fabric_tnd_hssl_atb_master_atdata_o127, fabric_tnd_hssl_atb_master_atdata_o128, fabric_tnd_hssl_atb_master_atid_o1, fabric_tnd_hssl_atb_master_atid_o2, fabric_tnd_hssl_atb_master_atid_o3, fabric_tnd_hssl_atb_master_atid_o4, fabric_tnd_hssl_atb_master_atid_o5, fabric_tnd_hssl_atb_master_atid_o6, fabric_tnd_hssl_atb_master_atid_o7, fabric_tnd_hssl_atb_master_atvalid_o
+, fabric_tnd_trace_clk_traceoutportintf_o, fabric_tnd_trace_ctl_traceoutportintf_o, fabric_tnd_trace_data_traceoutportintf_o1, fabric_tnd_trace_data_traceoutportintf_o2, fabric_tnd_trace_data_traceoutportintf_o3, fabric_tnd_trace_data_traceoutportintf_o4, fabric_tnd_trace_data_traceoutportintf_o5, fabric_tnd_trace_data_traceoutportintf_o6, fabric_tnd_trace_data_traceoutportintf_o7, fabric_tnd_trace_data_traceoutportintf_o8, fabric_tnd_trace_data_traceoutportintf_o9, fabric_tnd_trace_data_traceoutportintf_o10, fabric_tnd_trace_data_traceoutportintf_o11, fabric_tnd_trace_data_traceoutportintf_o12, fabric_tnd_trace_data_traceoutportintf_o13, fabric_tnd_trace_data_traceoutportintf_o14, fabric_tnd_trace_data_traceoutportintf_o15, fabric_tnd_trace_data_traceoutportintf_o16, fabric_tnd_trace_data_traceoutportintf_o17, fabric_tnd_trace_data_traceoutportintf_o18, fabric_tnd_trace_data_traceoutportintf_o19
+, fabric_tnd_trace_data_traceoutportintf_o20, fabric_tnd_trace_data_traceoutportintf_o21, fabric_tnd_trace_data_traceoutportintf_o22, fabric_tnd_trace_data_traceoutportintf_o23, fabric_tnd_trace_data_traceoutportintf_o24, fabric_tnd_trace_data_traceoutportintf_o25, fabric_tnd_trace_data_traceoutportintf_o26, fabric_tnd_trace_data_traceoutportintf_o27, fabric_tnd_trace_data_traceoutportintf_o28, fabric_tnd_trace_data_traceoutportintf_o29, fabric_tnd_trace_data_traceoutportintf_o30, fabric_tnd_trace_data_traceoutportintf_o31, fabric_tnd_trace_data_traceoutportintf_o32, fabric_tsvalue_tsgen_fpga_o1, fabric_tsvalue_tsgen_fpga_o2, fabric_tsvalue_tsgen_fpga_o3, fabric_tsvalue_tsgen_fpga_o4, fabric_tsvalue_tsgen_fpga_o5, fabric_tsvalue_tsgen_fpga_o6, fabric_tsvalue_tsgen_fpga_o7, fabric_tsvalue_tsgen_fpga_o8
+, fabric_tsvalue_tsgen_fpga_o9, fabric_tsvalue_tsgen_fpga_o10, fabric_tsvalue_tsgen_fpga_o11, fabric_tsvalue_tsgen_fpga_o12, fabric_tsvalue_tsgen_fpga_o13, fabric_tsvalue_tsgen_fpga_o14, fabric_tsvalue_tsgen_fpga_o15, fabric_tsvalue_tsgen_fpga_o16, fabric_tsvalue_tsgen_fpga_o17, fabric_tsvalue_tsgen_fpga_o18, fabric_tsvalue_tsgen_fpga_o19, fabric_tsvalue_tsgen_fpga_o20, fabric_tsvalue_tsgen_fpga_o21, fabric_tsvalue_tsgen_fpga_o22, fabric_tsvalue_tsgen_fpga_o23, fabric_tsvalue_tsgen_fpga_o24, fabric_tsvalue_tsgen_fpga_o25, fabric_tsvalue_tsgen_fpga_o26, fabric_tsvalue_tsgen_fpga_o27, fabric_tsvalue_tsgen_fpga_o28, fabric_tsvalue_tsgen_fpga_o29
+, fabric_tsvalue_tsgen_fpga_o30, fabric_tsvalue_tsgen_fpga_o31, fabric_tsvalue_tsgen_fpga_o32, fabric_tsvalue_tsgen_fpga_o33, fabric_tsvalue_tsgen_fpga_o34, fabric_tsvalue_tsgen_fpga_o35, fabric_tsvalue_tsgen_fpga_o36, fabric_tsvalue_tsgen_fpga_o37, fabric_tsvalue_tsgen_fpga_o38, fabric_tsvalue_tsgen_fpga_o39, fabric_tsvalue_tsgen_fpga_o40, fabric_tsvalue_tsgen_fpga_o41, fabric_tsvalue_tsgen_fpga_o42, fabric_tsvalue_tsgen_fpga_o43, fabric_tsvalue_tsgen_fpga_o44, fabric_tsvalue_tsgen_fpga_o45, fabric_tsvalue_tsgen_fpga_o46, fabric_tsvalue_tsgen_fpga_o47, fabric_tsvalue_tsgen_fpga_o48, fabric_tsvalue_tsgen_fpga_o49, fabric_tsvalue_tsgen_fpga_o50
+, fabric_tsvalue_tsgen_fpga_o51, fabric_tsvalue_tsgen_fpga_o52, fabric_tsvalue_tsgen_fpga_o53, fabric_tsvalue_tsgen_fpga_o54, fabric_tsvalue_tsgen_fpga_o55, fabric_tsvalue_tsgen_fpga_o56, fabric_tsvalue_tsgen_fpga_o57, fabric_tsvalue_tsgen_fpga_o58, fabric_tsvalue_tsgen_fpga_o59, fabric_tsvalue_tsgen_fpga_o60, fabric_tsvalue_tsgen_fpga_o61, fabric_tsvalue_tsgen_fpga_o62, fabric_tsvalue_tsgen_fpga_o63, fabric_tsvalue_tsgen_fpga_o64, fabric_tnd_fpga_apb_master_prdata_i1, fabric_tnd_fpga_apb_master_prdata_i2, fabric_tnd_fpga_apb_master_prdata_i3, fabric_tnd_fpga_apb_master_prdata_i4, fabric_tnd_fpga_apb_master_prdata_i5, fabric_tnd_fpga_apb_master_prdata_i6, fabric_tnd_fpga_apb_master_prdata_i7
+, fabric_tnd_fpga_apb_master_prdata_i8, fabric_tnd_fpga_apb_master_prdata_i9, fabric_tnd_fpga_apb_master_prdata_i10, fabric_tnd_fpga_apb_master_prdata_i11, fabric_tnd_fpga_apb_master_prdata_i12, fabric_tnd_fpga_apb_master_prdata_i13, fabric_tnd_fpga_apb_master_prdata_i14, fabric_tnd_fpga_apb_master_prdata_i15, fabric_tnd_fpga_apb_master_prdata_i16, fabric_tnd_fpga_apb_master_prdata_i17, fabric_tnd_fpga_apb_master_prdata_i18, fabric_tnd_fpga_apb_master_prdata_i19, fabric_tnd_fpga_apb_master_prdata_i20, fabric_tnd_fpga_apb_master_prdata_i21, fabric_tnd_fpga_apb_master_prdata_i22, fabric_tnd_fpga_apb_master_prdata_i23, fabric_tnd_fpga_apb_master_prdata_i24, fabric_tnd_fpga_apb_master_prdata_i25, fabric_tnd_fpga_apb_master_prdata_i26, fabric_tnd_fpga_apb_master_prdata_i27, fabric_tnd_fpga_apb_master_prdata_i28
+, fabric_tnd_fpga_apb_master_prdata_i29, fabric_tnd_fpga_apb_master_prdata_i30, fabric_tnd_fpga_apb_master_prdata_i31, fabric_tnd_fpga_apb_master_prdata_i32, fabric_tnd_fpga_apb_master_pready_i, fabric_tnd_fpga_apb_master_pslverr_i, fabric_tnd_fpga_atb_master_afready_i, fabric_tnd_fpga_atb_master_atbytes_i1, fabric_tnd_fpga_atb_master_atbytes_i2, fabric_tnd_fpga_atb_master_atbytes_i3, fabric_tnd_fpga_atb_master_atbytes_i4, fabric_tnd_fpga_atb_master_atdata_i1, fabric_tnd_fpga_atb_master_atdata_i2, fabric_tnd_fpga_atb_master_atdata_i3, fabric_tnd_fpga_atb_master_atdata_i4, fabric_tnd_fpga_atb_master_atdata_i5, fabric_tnd_fpga_atb_master_atdata_i6, fabric_tnd_fpga_atb_master_atdata_i7, fabric_tnd_fpga_atb_master_atdata_i8, fabric_tnd_fpga_atb_master_atdata_i9, fabric_tnd_fpga_atb_master_atdata_i10
+, fabric_tnd_fpga_atb_master_atdata_i11, fabric_tnd_fpga_atb_master_atdata_i12, fabric_tnd_fpga_atb_master_atdata_i13, fabric_tnd_fpga_atb_master_atdata_i14, fabric_tnd_fpga_atb_master_atdata_i15, fabric_tnd_fpga_atb_master_atdata_i16, fabric_tnd_fpga_atb_master_atdata_i17, fabric_tnd_fpga_atb_master_atdata_i18, fabric_tnd_fpga_atb_master_atdata_i19, fabric_tnd_fpga_atb_master_atdata_i20, fabric_tnd_fpga_atb_master_atdata_i21, fabric_tnd_fpga_atb_master_atdata_i22, fabric_tnd_fpga_atb_master_atdata_i23, fabric_tnd_fpga_atb_master_atdata_i24, fabric_tnd_fpga_atb_master_atdata_i25, fabric_tnd_fpga_atb_master_atdata_i26, fabric_tnd_fpga_atb_master_atdata_i27, fabric_tnd_fpga_atb_master_atdata_i28, fabric_tnd_fpga_atb_master_atdata_i29, fabric_tnd_fpga_atb_master_atdata_i30, fabric_tnd_fpga_atb_master_atdata_i31
+, fabric_tnd_fpga_atb_master_atdata_i32, fabric_tnd_fpga_atb_master_atdata_i33, fabric_tnd_fpga_atb_master_atdata_i34, fabric_tnd_fpga_atb_master_atdata_i35, fabric_tnd_fpga_atb_master_atdata_i36, fabric_tnd_fpga_atb_master_atdata_i37, fabric_tnd_fpga_atb_master_atdata_i38, fabric_tnd_fpga_atb_master_atdata_i39, fabric_tnd_fpga_atb_master_atdata_i40, fabric_tnd_fpga_atb_master_atdata_i41, fabric_tnd_fpga_atb_master_atdata_i42, fabric_tnd_fpga_atb_master_atdata_i43, fabric_tnd_fpga_atb_master_atdata_i44, fabric_tnd_fpga_atb_master_atdata_i45, fabric_tnd_fpga_atb_master_atdata_i46, fabric_tnd_fpga_atb_master_atdata_i47, fabric_tnd_fpga_atb_master_atdata_i48, fabric_tnd_fpga_atb_master_atdata_i49, fabric_tnd_fpga_atb_master_atdata_i50, fabric_tnd_fpga_atb_master_atdata_i51, fabric_tnd_fpga_atb_master_atdata_i52
+, fabric_tnd_fpga_atb_master_atdata_i53, fabric_tnd_fpga_atb_master_atdata_i54, fabric_tnd_fpga_atb_master_atdata_i55, fabric_tnd_fpga_atb_master_atdata_i56, fabric_tnd_fpga_atb_master_atdata_i57, fabric_tnd_fpga_atb_master_atdata_i58, fabric_tnd_fpga_atb_master_atdata_i59, fabric_tnd_fpga_atb_master_atdata_i60, fabric_tnd_fpga_atb_master_atdata_i61, fabric_tnd_fpga_atb_master_atdata_i62, fabric_tnd_fpga_atb_master_atdata_i63, fabric_tnd_fpga_atb_master_atdata_i64, fabric_tnd_fpga_atb_master_atdata_i65, fabric_tnd_fpga_atb_master_atdata_i66, fabric_tnd_fpga_atb_master_atdata_i67, fabric_tnd_fpga_atb_master_atdata_i68, fabric_tnd_fpga_atb_master_atdata_i69, fabric_tnd_fpga_atb_master_atdata_i70, fabric_tnd_fpga_atb_master_atdata_i71, fabric_tnd_fpga_atb_master_atdata_i72, fabric_tnd_fpga_atb_master_atdata_i73
+, fabric_tnd_fpga_atb_master_atdata_i74, fabric_tnd_fpga_atb_master_atdata_i75, fabric_tnd_fpga_atb_master_atdata_i76, fabric_tnd_fpga_atb_master_atdata_i77, fabric_tnd_fpga_atb_master_atdata_i78, fabric_tnd_fpga_atb_master_atdata_i79, fabric_tnd_fpga_atb_master_atdata_i80, fabric_tnd_fpga_atb_master_atdata_i81, fabric_tnd_fpga_atb_master_atdata_i82, fabric_tnd_fpga_atb_master_atdata_i83, fabric_tnd_fpga_atb_master_atdata_i84, fabric_tnd_fpga_atb_master_atdata_i85, fabric_tnd_fpga_atb_master_atdata_i86, fabric_tnd_fpga_atb_master_atdata_i87, fabric_tnd_fpga_atb_master_atdata_i88, fabric_tnd_fpga_atb_master_atdata_i89, fabric_tnd_fpga_atb_master_atdata_i90, fabric_tnd_fpga_atb_master_atdata_i91, fabric_tnd_fpga_atb_master_atdata_i92, fabric_tnd_fpga_atb_master_atdata_i93, fabric_tnd_fpga_atb_master_atdata_i94
+, fabric_tnd_fpga_atb_master_atdata_i95, fabric_tnd_fpga_atb_master_atdata_i96, fabric_tnd_fpga_atb_master_atdata_i97, fabric_tnd_fpga_atb_master_atdata_i98, fabric_tnd_fpga_atb_master_atdata_i99, fabric_tnd_fpga_atb_master_atdata_i100, fabric_tnd_fpga_atb_master_atdata_i101, fabric_tnd_fpga_atb_master_atdata_i102, fabric_tnd_fpga_atb_master_atdata_i103, fabric_tnd_fpga_atb_master_atdata_i104, fabric_tnd_fpga_atb_master_atdata_i105, fabric_tnd_fpga_atb_master_atdata_i106, fabric_tnd_fpga_atb_master_atdata_i107, fabric_tnd_fpga_atb_master_atdata_i108, fabric_tnd_fpga_atb_master_atdata_i109, fabric_tnd_fpga_atb_master_atdata_i110, fabric_tnd_fpga_atb_master_atdata_i111, fabric_tnd_fpga_atb_master_atdata_i112, fabric_tnd_fpga_atb_master_atdata_i113, fabric_tnd_fpga_atb_master_atdata_i114, fabric_tnd_fpga_atb_master_atdata_i115
+, fabric_tnd_fpga_atb_master_atdata_i116, fabric_tnd_fpga_atb_master_atdata_i117, fabric_tnd_fpga_atb_master_atdata_i118, fabric_tnd_fpga_atb_master_atdata_i119, fabric_tnd_fpga_atb_master_atdata_i120, fabric_tnd_fpga_atb_master_atdata_i121, fabric_tnd_fpga_atb_master_atdata_i122, fabric_tnd_fpga_atb_master_atdata_i123, fabric_tnd_fpga_atb_master_atdata_i124, fabric_tnd_fpga_atb_master_atdata_i125, fabric_tnd_fpga_atb_master_atdata_i126, fabric_tnd_fpga_atb_master_atdata_i127, fabric_tnd_fpga_atb_master_atdata_i128, fabric_tnd_fpga_atb_master_atid_i1, fabric_tnd_fpga_atb_master_atid_i2, fabric_tnd_fpga_atb_master_atid_i3, fabric_tnd_fpga_atb_master_atid_i4, fabric_tnd_fpga_atb_master_atid_i5, fabric_tnd_fpga_atb_master_atid_i6, fabric_tnd_fpga_atb_master_atid_i7, fabric_tnd_fpga_atb_master_atvalid_i
+, fabric_tnd_hssl_apb_master_prdata_i1, fabric_tnd_hssl_apb_master_prdata_i2, fabric_tnd_hssl_apb_master_prdata_i3, fabric_tnd_hssl_apb_master_prdata_i4, fabric_tnd_hssl_apb_master_prdata_i5, fabric_tnd_hssl_apb_master_prdata_i6, fabric_tnd_hssl_apb_master_prdata_i7, fabric_tnd_hssl_apb_master_prdata_i8, fabric_tnd_hssl_apb_master_prdata_i9, fabric_tnd_hssl_apb_master_prdata_i10, fabric_tnd_hssl_apb_master_prdata_i11, fabric_tnd_hssl_apb_master_prdata_i12, fabric_tnd_hssl_apb_master_prdata_i13, fabric_tnd_hssl_apb_master_prdata_i14, fabric_tnd_hssl_apb_master_prdata_i15, fabric_tnd_hssl_apb_master_prdata_i16, fabric_tnd_hssl_apb_master_prdata_i17, fabric_tnd_hssl_apb_master_prdata_i18, fabric_tnd_hssl_apb_master_prdata_i19, fabric_tnd_hssl_apb_master_prdata_i20, fabric_tnd_hssl_apb_master_prdata_i21
+, fabric_tnd_hssl_apb_master_prdata_i22, fabric_tnd_hssl_apb_master_prdata_i23, fabric_tnd_hssl_apb_master_prdata_i24, fabric_tnd_hssl_apb_master_prdata_i25, fabric_tnd_hssl_apb_master_prdata_i26, fabric_tnd_hssl_apb_master_prdata_i27, fabric_tnd_hssl_apb_master_prdata_i28, fabric_tnd_hssl_apb_master_prdata_i29, fabric_tnd_hssl_apb_master_prdata_i30, fabric_tnd_hssl_apb_master_prdata_i31, fabric_tnd_hssl_apb_master_prdata_i32, fabric_tnd_hssl_apb_master_pready_i, fabric_tnd_hssl_apb_master_pslverr_i, fabric_tnd_hssl_atb_master_afvalid_i, fabric_tnd_hssl_atb_master_atready_i, fabric_tnd_hssl_atb_master_syncreq_i, fabric_watchdog0_signal_0_o, fabric_watchdog0_signal_1_o, fabric_watchdog1_signal_0_o, fabric_watchdog1_signal_1_o, fabric_watchdog2_signal_0_o
+, fabric_watchdog2_signal_1_o, fabric_watchdog3_signal_0_o, fabric_watchdog3_signal_1_o, fabric_tst_pll_lock_o1, fabric_tst_pll_lock_o2, fabric_tst_pll_lock_o3, fabric_tst_pll_lock_o4, fabric_tst_pll_lock_o5, fabric_tst_pll_lock_o6, fabric_tst_pll_lock_o7, fabric_soc_mon_sensor_alarm_o, fabric_erom_fpga_cpu0_dbgen_i, fabric_erom_fpga_cpu0_hiden_i, fabric_erom_fpga_cpu0_hniden_i, fabric_erom_fpga_cpu0_niden_i, fabric_erom_fpga_cpu1_dbgen_i, fabric_erom_fpga_cpu1_hiden_i, fabric_erom_fpga_cpu1_hniden_i, fabric_erom_fpga_cpu1_niden_i, fabric_erom_fpga_cpu2_dbgen_i, fabric_erom_fpga_cpu2_hiden_i
+, fabric_erom_fpga_cpu2_hniden_i, fabric_erom_fpga_cpu2_niden_i, fabric_erom_fpga_cpu3_dbgen_i, fabric_erom_fpga_cpu3_hiden_i, fabric_erom_fpga_cpu3_hniden_i, fabric_erom_fpga_cpu3_niden_i, fabric_erom_fpga_cs_dbgen_i, fabric_erom_fpga_cs_niden_i, fabric_erom_fpga_cs_deviceen_i, fabric_erom_fpga_cs_rst_n_i, fabric_erom_fpga_debug_en_i, fabric_enable_TMR_i1, fabric_enable_TMR_i2, fabric_enable_TMR_i3);
+    input fabric_enable_TMR_i1;
+    input fabric_enable_TMR_i2;
+    input fabric_enable_TMR_i3;
+    input fabric_erom_fpga_cpu0_dbgen_i;
+    input fabric_erom_fpga_cpu0_hiden_i;
+    input fabric_erom_fpga_cpu0_hniden_i;
+    input fabric_erom_fpga_cpu0_niden_i;
+    input fabric_erom_fpga_cpu1_dbgen_i;
+    input fabric_erom_fpga_cpu1_hiden_i;
+    input fabric_erom_fpga_cpu1_hniden_i;
+    input fabric_erom_fpga_cpu1_niden_i;
+    input fabric_erom_fpga_cpu2_dbgen_i;
+    input fabric_erom_fpga_cpu2_hiden_i;
+    input fabric_erom_fpga_cpu2_hniden_i;
+    input fabric_erom_fpga_cpu2_niden_i;
+    input fabric_erom_fpga_cpu3_dbgen_i;
+    input fabric_erom_fpga_cpu3_hiden_i;
+    input fabric_erom_fpga_cpu3_hniden_i;
+    input fabric_erom_fpga_cpu3_niden_i;
+    input fabric_erom_fpga_cs_dbgen_i;
+    input fabric_erom_fpga_cs_deviceen_i;
+    input fabric_erom_fpga_cs_niden_i;
+    input fabric_erom_fpga_cs_rst_n_i;
+    input fabric_erom_fpga_debug_en_i;
+    input fabric_fpga_araddr_axi_m1_i1;
+    input fabric_fpga_araddr_axi_m1_i10;
+    input fabric_fpga_araddr_axi_m1_i11;
+    input fabric_fpga_araddr_axi_m1_i12;
+    input fabric_fpga_araddr_axi_m1_i13;
+    input fabric_fpga_araddr_axi_m1_i14;
+    input fabric_fpga_araddr_axi_m1_i15;
+    input fabric_fpga_araddr_axi_m1_i16;
+    input fabric_fpga_araddr_axi_m1_i17;
+    input fabric_fpga_araddr_axi_m1_i18;
+    input fabric_fpga_araddr_axi_m1_i19;
+    input fabric_fpga_araddr_axi_m1_i2;
+    input fabric_fpga_araddr_axi_m1_i20;
+    input fabric_fpga_araddr_axi_m1_i21;
+    input fabric_fpga_araddr_axi_m1_i22;
+    input fabric_fpga_araddr_axi_m1_i23;
+    input fabric_fpga_araddr_axi_m1_i24;
+    input fabric_fpga_araddr_axi_m1_i25;
+    input fabric_fpga_araddr_axi_m1_i26;
+    input fabric_fpga_araddr_axi_m1_i27;
+    input fabric_fpga_araddr_axi_m1_i28;
+    input fabric_fpga_araddr_axi_m1_i29;
+    input fabric_fpga_araddr_axi_m1_i3;
+    input fabric_fpga_araddr_axi_m1_i30;
+    input fabric_fpga_araddr_axi_m1_i31;
+    input fabric_fpga_araddr_axi_m1_i32;
+    input fabric_fpga_araddr_axi_m1_i33;
+    input fabric_fpga_araddr_axi_m1_i34;
+    input fabric_fpga_araddr_axi_m1_i35;
+    input fabric_fpga_araddr_axi_m1_i36;
+    input fabric_fpga_araddr_axi_m1_i37;
+    input fabric_fpga_araddr_axi_m1_i38;
+    input fabric_fpga_araddr_axi_m1_i39;
+    input fabric_fpga_araddr_axi_m1_i4;
+    input fabric_fpga_araddr_axi_m1_i40;
+    input fabric_fpga_araddr_axi_m1_i5;
+    input fabric_fpga_araddr_axi_m1_i6;
+    input fabric_fpga_araddr_axi_m1_i7;
+    input fabric_fpga_araddr_axi_m1_i8;
+    input fabric_fpga_araddr_axi_m1_i9;
+    input fabric_fpga_araddr_axi_m2_i1;
+    input fabric_fpga_araddr_axi_m2_i10;
+    input fabric_fpga_araddr_axi_m2_i11;
+    input fabric_fpga_araddr_axi_m2_i12;
+    input fabric_fpga_araddr_axi_m2_i13;
+    input fabric_fpga_araddr_axi_m2_i14;
+    input fabric_fpga_araddr_axi_m2_i15;
+    input fabric_fpga_araddr_axi_m2_i16;
+    input fabric_fpga_araddr_axi_m2_i17;
+    input fabric_fpga_araddr_axi_m2_i18;
+    input fabric_fpga_araddr_axi_m2_i19;
+    input fabric_fpga_araddr_axi_m2_i2;
+    input fabric_fpga_araddr_axi_m2_i20;
+    input fabric_fpga_araddr_axi_m2_i21;
+    input fabric_fpga_araddr_axi_m2_i22;
+    input fabric_fpga_araddr_axi_m2_i23;
+    input fabric_fpga_araddr_axi_m2_i24;
+    input fabric_fpga_araddr_axi_m2_i25;
+    input fabric_fpga_araddr_axi_m2_i26;
+    input fabric_fpga_araddr_axi_m2_i27;
+    input fabric_fpga_araddr_axi_m2_i28;
+    input fabric_fpga_araddr_axi_m2_i29;
+    input fabric_fpga_araddr_axi_m2_i3;
+    input fabric_fpga_araddr_axi_m2_i30;
+    input fabric_fpga_araddr_axi_m2_i31;
+    input fabric_fpga_araddr_axi_m2_i32;
+    input fabric_fpga_araddr_axi_m2_i33;
+    input fabric_fpga_araddr_axi_m2_i34;
+    input fabric_fpga_araddr_axi_m2_i35;
+    input fabric_fpga_araddr_axi_m2_i36;
+    input fabric_fpga_araddr_axi_m2_i37;
+    input fabric_fpga_araddr_axi_m2_i38;
+    input fabric_fpga_araddr_axi_m2_i39;
+    input fabric_fpga_araddr_axi_m2_i4;
+    input fabric_fpga_araddr_axi_m2_i40;
+    input fabric_fpga_araddr_axi_m2_i5;
+    input fabric_fpga_araddr_axi_m2_i6;
+    input fabric_fpga_araddr_axi_m2_i7;
+    input fabric_fpga_araddr_axi_m2_i8;
+    input fabric_fpga_araddr_axi_m2_i9;
+    output fabric_fpga_araddr_axi_s1_o1;
+    output fabric_fpga_araddr_axi_s1_o10;
+    output fabric_fpga_araddr_axi_s1_o11;
+    output fabric_fpga_araddr_axi_s1_o12;
+    output fabric_fpga_araddr_axi_s1_o13;
+    output fabric_fpga_araddr_axi_s1_o14;
+    output fabric_fpga_araddr_axi_s1_o15;
+    output fabric_fpga_araddr_axi_s1_o16;
+    output fabric_fpga_araddr_axi_s1_o17;
+    output fabric_fpga_araddr_axi_s1_o18;
+    output fabric_fpga_araddr_axi_s1_o19;
+    output fabric_fpga_araddr_axi_s1_o2;
+    output fabric_fpga_araddr_axi_s1_o20;
+    output fabric_fpga_araddr_axi_s1_o21;
+    output fabric_fpga_araddr_axi_s1_o22;
+    output fabric_fpga_araddr_axi_s1_o23;
+    output fabric_fpga_araddr_axi_s1_o24;
+    output fabric_fpga_araddr_axi_s1_o25;
+    output fabric_fpga_araddr_axi_s1_o26;
+    output fabric_fpga_araddr_axi_s1_o27;
+    output fabric_fpga_araddr_axi_s1_o28;
+    output fabric_fpga_araddr_axi_s1_o29;
+    output fabric_fpga_araddr_axi_s1_o3;
+    output fabric_fpga_araddr_axi_s1_o30;
+    output fabric_fpga_araddr_axi_s1_o31;
+    output fabric_fpga_araddr_axi_s1_o32;
+    output fabric_fpga_araddr_axi_s1_o33;
+    output fabric_fpga_araddr_axi_s1_o34;
+    output fabric_fpga_araddr_axi_s1_o35;
+    output fabric_fpga_araddr_axi_s1_o36;
+    output fabric_fpga_araddr_axi_s1_o37;
+    output fabric_fpga_araddr_axi_s1_o38;
+    output fabric_fpga_araddr_axi_s1_o39;
+    output fabric_fpga_araddr_axi_s1_o4;
+    output fabric_fpga_araddr_axi_s1_o40;
+    output fabric_fpga_araddr_axi_s1_o5;
+    output fabric_fpga_araddr_axi_s1_o6;
+    output fabric_fpga_araddr_axi_s1_o7;
+    output fabric_fpga_araddr_axi_s1_o8;
+    output fabric_fpga_araddr_axi_s1_o9;
+    output fabric_fpga_araddr_axi_s2_o1;
+    output fabric_fpga_araddr_axi_s2_o10;
+    output fabric_fpga_araddr_axi_s2_o11;
+    output fabric_fpga_araddr_axi_s2_o12;
+    output fabric_fpga_araddr_axi_s2_o13;
+    output fabric_fpga_araddr_axi_s2_o14;
+    output fabric_fpga_araddr_axi_s2_o15;
+    output fabric_fpga_araddr_axi_s2_o16;
+    output fabric_fpga_araddr_axi_s2_o17;
+    output fabric_fpga_araddr_axi_s2_o18;
+    output fabric_fpga_araddr_axi_s2_o19;
+    output fabric_fpga_araddr_axi_s2_o2;
+    output fabric_fpga_araddr_axi_s2_o20;
+    output fabric_fpga_araddr_axi_s2_o21;
+    output fabric_fpga_araddr_axi_s2_o22;
+    output fabric_fpga_araddr_axi_s2_o23;
+    output fabric_fpga_araddr_axi_s2_o24;
+    output fabric_fpga_araddr_axi_s2_o25;
+    output fabric_fpga_araddr_axi_s2_o26;
+    output fabric_fpga_araddr_axi_s2_o27;
+    output fabric_fpga_araddr_axi_s2_o28;
+    output fabric_fpga_araddr_axi_s2_o29;
+    output fabric_fpga_araddr_axi_s2_o3;
+    output fabric_fpga_araddr_axi_s2_o30;
+    output fabric_fpga_araddr_axi_s2_o31;
+    output fabric_fpga_araddr_axi_s2_o32;
+    output fabric_fpga_araddr_axi_s2_o33;
+    output fabric_fpga_araddr_axi_s2_o34;
+    output fabric_fpga_araddr_axi_s2_o35;
+    output fabric_fpga_araddr_axi_s2_o36;
+    output fabric_fpga_araddr_axi_s2_o37;
+    output fabric_fpga_araddr_axi_s2_o38;
+    output fabric_fpga_araddr_axi_s2_o39;
+    output fabric_fpga_araddr_axi_s2_o4;
+    output fabric_fpga_araddr_axi_s2_o40;
+    output fabric_fpga_araddr_axi_s2_o5;
+    output fabric_fpga_araddr_axi_s2_o6;
+    output fabric_fpga_araddr_axi_s2_o7;
+    output fabric_fpga_araddr_axi_s2_o8;
+    output fabric_fpga_araddr_axi_s2_o9;
+    input fabric_fpga_arburst_axi_m1_i1;
+    input fabric_fpga_arburst_axi_m1_i2;
+    input fabric_fpga_arburst_axi_m2_i1;
+    input fabric_fpga_arburst_axi_m2_i2;
+    output fabric_fpga_arburst_axi_s1_o1;
+    output fabric_fpga_arburst_axi_s1_o2;
+    output fabric_fpga_arburst_axi_s2_o1;
+    output fabric_fpga_arburst_axi_s2_o2;
+    input fabric_fpga_arcache_axi_m1_i1;
+    input fabric_fpga_arcache_axi_m1_i2;
+    input fabric_fpga_arcache_axi_m1_i3;
+    input fabric_fpga_arcache_axi_m1_i4;
+    input fabric_fpga_arcache_axi_m2_i1;
+    input fabric_fpga_arcache_axi_m2_i2;
+    input fabric_fpga_arcache_axi_m2_i3;
+    input fabric_fpga_arcache_axi_m2_i4;
+    output fabric_fpga_arcache_axi_s1_o1;
+    output fabric_fpga_arcache_axi_s1_o2;
+    output fabric_fpga_arcache_axi_s1_o3;
+    output fabric_fpga_arcache_axi_s1_o4;
+    output fabric_fpga_arcache_axi_s2_o1;
+    output fabric_fpga_arcache_axi_s2_o2;
+    output fabric_fpga_arcache_axi_s2_o3;
+    output fabric_fpga_arcache_axi_s2_o4;
+    input fabric_fpga_arid_axi_m1_i1;
+    input fabric_fpga_arid_axi_m1_i2;
+    input fabric_fpga_arid_axi_m1_i3;
+    input fabric_fpga_arid_axi_m1_i4;
+    input fabric_fpga_arid_axi_m1_i5;
+    input fabric_fpga_arid_axi_m2_i1;
+    input fabric_fpga_arid_axi_m2_i2;
+    input fabric_fpga_arid_axi_m2_i3;
+    input fabric_fpga_arid_axi_m2_i4;
+    input fabric_fpga_arid_axi_m2_i5;
+    output fabric_fpga_arid_axi_s1_o1;
+    output fabric_fpga_arid_axi_s1_o10;
+    output fabric_fpga_arid_axi_s1_o11;
+    output fabric_fpga_arid_axi_s1_o12;
+    output fabric_fpga_arid_axi_s1_o2;
+    output fabric_fpga_arid_axi_s1_o3;
+    output fabric_fpga_arid_axi_s1_o4;
+    output fabric_fpga_arid_axi_s1_o5;
+    output fabric_fpga_arid_axi_s1_o6;
+    output fabric_fpga_arid_axi_s1_o7;
+    output fabric_fpga_arid_axi_s1_o8;
+    output fabric_fpga_arid_axi_s1_o9;
+    output fabric_fpga_arid_axi_s2_o1;
+    output fabric_fpga_arid_axi_s2_o10;
+    output fabric_fpga_arid_axi_s2_o11;
+    output fabric_fpga_arid_axi_s2_o12;
+    output fabric_fpga_arid_axi_s2_o2;
+    output fabric_fpga_arid_axi_s2_o3;
+    output fabric_fpga_arid_axi_s2_o4;
+    output fabric_fpga_arid_axi_s2_o5;
+    output fabric_fpga_arid_axi_s2_o6;
+    output fabric_fpga_arid_axi_s2_o7;
+    output fabric_fpga_arid_axi_s2_o8;
+    output fabric_fpga_arid_axi_s2_o9;
+    input fabric_fpga_arlen_axi_m1_i1;
+    input fabric_fpga_arlen_axi_m1_i2;
+    input fabric_fpga_arlen_axi_m1_i3;
+    input fabric_fpga_arlen_axi_m1_i4;
+    input fabric_fpga_arlen_axi_m1_i5;
+    input fabric_fpga_arlen_axi_m1_i6;
+    input fabric_fpga_arlen_axi_m1_i7;
+    input fabric_fpga_arlen_axi_m1_i8;
+    input fabric_fpga_arlen_axi_m2_i1;
+    input fabric_fpga_arlen_axi_m2_i2;
+    input fabric_fpga_arlen_axi_m2_i3;
+    input fabric_fpga_arlen_axi_m2_i4;
+    input fabric_fpga_arlen_axi_m2_i5;
+    input fabric_fpga_arlen_axi_m2_i6;
+    input fabric_fpga_arlen_axi_m2_i7;
+    input fabric_fpga_arlen_axi_m2_i8;
+    output fabric_fpga_arlen_axi_s1_o1;
+    output fabric_fpga_arlen_axi_s1_o2;
+    output fabric_fpga_arlen_axi_s1_o3;
+    output fabric_fpga_arlen_axi_s1_o4;
+    output fabric_fpga_arlen_axi_s1_o5;
+    output fabric_fpga_arlen_axi_s1_o6;
+    output fabric_fpga_arlen_axi_s1_o7;
+    output fabric_fpga_arlen_axi_s1_o8;
+    output fabric_fpga_arlen_axi_s2_o1;
+    output fabric_fpga_arlen_axi_s2_o2;
+    output fabric_fpga_arlen_axi_s2_o3;
+    output fabric_fpga_arlen_axi_s2_o4;
+    output fabric_fpga_arlen_axi_s2_o5;
+    output fabric_fpga_arlen_axi_s2_o6;
+    output fabric_fpga_arlen_axi_s2_o7;
+    output fabric_fpga_arlen_axi_s2_o8;
+    input fabric_fpga_arlock_axi_m1_i;
+    input fabric_fpga_arlock_axi_m2_i;
+    output fabric_fpga_arlock_axi_s1_o;
+    output fabric_fpga_arlock_axi_s2_o;
+    input fabric_fpga_arprot_axi_m1_i1;
+    input fabric_fpga_arprot_axi_m1_i2;
+    input fabric_fpga_arprot_axi_m1_i3;
+    input fabric_fpga_arprot_axi_m2_i1;
+    input fabric_fpga_arprot_axi_m2_i2;
+    input fabric_fpga_arprot_axi_m2_i3;
+    output fabric_fpga_arprot_axi_s1_o1;
+    output fabric_fpga_arprot_axi_s1_o2;
+    output fabric_fpga_arprot_axi_s1_o3;
+    output fabric_fpga_arprot_axi_s2_o1;
+    output fabric_fpga_arprot_axi_s2_o2;
+    output fabric_fpga_arprot_axi_s2_o3;
+    input fabric_fpga_arqos_axi_m1_i1;
+    input fabric_fpga_arqos_axi_m1_i2;
+    input fabric_fpga_arqos_axi_m1_i3;
+    input fabric_fpga_arqos_axi_m1_i4;
+    input fabric_fpga_arqos_axi_m2_i1;
+    input fabric_fpga_arqos_axi_m2_i2;
+    input fabric_fpga_arqos_axi_m2_i3;
+    input fabric_fpga_arqos_axi_m2_i4;
+    output fabric_fpga_arqos_axi_s1_o1;
+    output fabric_fpga_arqos_axi_s1_o2;
+    output fabric_fpga_arqos_axi_s1_o3;
+    output fabric_fpga_arqos_axi_s1_o4;
+    output fabric_fpga_arqos_axi_s2_o1;
+    output fabric_fpga_arqos_axi_s2_o2;
+    output fabric_fpga_arqos_axi_s2_o3;
+    output fabric_fpga_arqos_axi_s2_o4;
+    output fabric_fpga_arready_axi_m1_o;
+    output fabric_fpga_arready_axi_m2_o;
+    input fabric_fpga_arready_axi_s1_i;
+    input fabric_fpga_arready_axi_s2_i;
+    output fabric_fpga_arregion_axi_s1_o1;
+    output fabric_fpga_arregion_axi_s1_o2;
+    output fabric_fpga_arregion_axi_s1_o3;
+    output fabric_fpga_arregion_axi_s1_o4;
+    output fabric_fpga_arregion_axi_s2_o1;
+    output fabric_fpga_arregion_axi_s2_o2;
+    output fabric_fpga_arregion_axi_s2_o3;
+    output fabric_fpga_arregion_axi_s2_o4;
+    input fabric_fpga_arsize_axi_m1_i1;
+    input fabric_fpga_arsize_axi_m1_i2;
+    input fabric_fpga_arsize_axi_m1_i3;
+    input fabric_fpga_arsize_axi_m2_i1;
+    input fabric_fpga_arsize_axi_m2_i2;
+    input fabric_fpga_arsize_axi_m2_i3;
+    output fabric_fpga_arsize_axi_s1_o1;
+    output fabric_fpga_arsize_axi_s1_o2;
+    output fabric_fpga_arsize_axi_s1_o3;
+    output fabric_fpga_arsize_axi_s2_o1;
+    output fabric_fpga_arsize_axi_s2_o2;
+    output fabric_fpga_arsize_axi_s2_o3;
+    input fabric_fpga_arvalid_axi_m1_i;
+    input fabric_fpga_arvalid_axi_m2_i;
+    output fabric_fpga_arvalid_axi_s1_o;
+    output fabric_fpga_arvalid_axi_s2_o;
+    input fabric_fpga_awaddr_axi_m1_i1;
+    input fabric_fpga_awaddr_axi_m1_i10;
+    input fabric_fpga_awaddr_axi_m1_i11;
+    input fabric_fpga_awaddr_axi_m1_i12;
+    input fabric_fpga_awaddr_axi_m1_i13;
+    input fabric_fpga_awaddr_axi_m1_i14;
+    input fabric_fpga_awaddr_axi_m1_i15;
+    input fabric_fpga_awaddr_axi_m1_i16;
+    input fabric_fpga_awaddr_axi_m1_i17;
+    input fabric_fpga_awaddr_axi_m1_i18;
+    input fabric_fpga_awaddr_axi_m1_i19;
+    input fabric_fpga_awaddr_axi_m1_i2;
+    input fabric_fpga_awaddr_axi_m1_i20;
+    input fabric_fpga_awaddr_axi_m1_i21;
+    input fabric_fpga_awaddr_axi_m1_i22;
+    input fabric_fpga_awaddr_axi_m1_i23;
+    input fabric_fpga_awaddr_axi_m1_i24;
+    input fabric_fpga_awaddr_axi_m1_i25;
+    input fabric_fpga_awaddr_axi_m1_i26;
+    input fabric_fpga_awaddr_axi_m1_i27;
+    input fabric_fpga_awaddr_axi_m1_i28;
+    input fabric_fpga_awaddr_axi_m1_i29;
+    input fabric_fpga_awaddr_axi_m1_i3;
+    input fabric_fpga_awaddr_axi_m1_i30;
+    input fabric_fpga_awaddr_axi_m1_i31;
+    input fabric_fpga_awaddr_axi_m1_i32;
+    input fabric_fpga_awaddr_axi_m1_i33;
+    input fabric_fpga_awaddr_axi_m1_i34;
+    input fabric_fpga_awaddr_axi_m1_i35;
+    input fabric_fpga_awaddr_axi_m1_i36;
+    input fabric_fpga_awaddr_axi_m1_i37;
+    input fabric_fpga_awaddr_axi_m1_i38;
+    input fabric_fpga_awaddr_axi_m1_i39;
+    input fabric_fpga_awaddr_axi_m1_i4;
+    input fabric_fpga_awaddr_axi_m1_i40;
+    input fabric_fpga_awaddr_axi_m1_i5;
+    input fabric_fpga_awaddr_axi_m1_i6;
+    input fabric_fpga_awaddr_axi_m1_i7;
+    input fabric_fpga_awaddr_axi_m1_i8;
+    input fabric_fpga_awaddr_axi_m1_i9;
+    input fabric_fpga_awaddr_axi_m2_i1;
+    input fabric_fpga_awaddr_axi_m2_i10;
+    input fabric_fpga_awaddr_axi_m2_i11;
+    input fabric_fpga_awaddr_axi_m2_i12;
+    input fabric_fpga_awaddr_axi_m2_i13;
+    input fabric_fpga_awaddr_axi_m2_i14;
+    input fabric_fpga_awaddr_axi_m2_i15;
+    input fabric_fpga_awaddr_axi_m2_i16;
+    input fabric_fpga_awaddr_axi_m2_i17;
+    input fabric_fpga_awaddr_axi_m2_i18;
+    input fabric_fpga_awaddr_axi_m2_i19;
+    input fabric_fpga_awaddr_axi_m2_i2;
+    input fabric_fpga_awaddr_axi_m2_i20;
+    input fabric_fpga_awaddr_axi_m2_i21;
+    input fabric_fpga_awaddr_axi_m2_i22;
+    input fabric_fpga_awaddr_axi_m2_i23;
+    input fabric_fpga_awaddr_axi_m2_i24;
+    input fabric_fpga_awaddr_axi_m2_i25;
+    input fabric_fpga_awaddr_axi_m2_i26;
+    input fabric_fpga_awaddr_axi_m2_i27;
+    input fabric_fpga_awaddr_axi_m2_i28;
+    input fabric_fpga_awaddr_axi_m2_i29;
+    input fabric_fpga_awaddr_axi_m2_i3;
+    input fabric_fpga_awaddr_axi_m2_i30;
+    input fabric_fpga_awaddr_axi_m2_i31;
+    input fabric_fpga_awaddr_axi_m2_i32;
+    input fabric_fpga_awaddr_axi_m2_i33;
+    input fabric_fpga_awaddr_axi_m2_i34;
+    input fabric_fpga_awaddr_axi_m2_i35;
+    input fabric_fpga_awaddr_axi_m2_i36;
+    input fabric_fpga_awaddr_axi_m2_i37;
+    input fabric_fpga_awaddr_axi_m2_i38;
+    input fabric_fpga_awaddr_axi_m2_i39;
+    input fabric_fpga_awaddr_axi_m2_i4;
+    input fabric_fpga_awaddr_axi_m2_i40;
+    input fabric_fpga_awaddr_axi_m2_i5;
+    input fabric_fpga_awaddr_axi_m2_i6;
+    input fabric_fpga_awaddr_axi_m2_i7;
+    input fabric_fpga_awaddr_axi_m2_i8;
+    input fabric_fpga_awaddr_axi_m2_i9;
+    output fabric_fpga_awaddr_axi_s1_o1;
+    output fabric_fpga_awaddr_axi_s1_o10;
+    output fabric_fpga_awaddr_axi_s1_o11;
+    output fabric_fpga_awaddr_axi_s1_o12;
+    output fabric_fpga_awaddr_axi_s1_o13;
+    output fabric_fpga_awaddr_axi_s1_o14;
+    output fabric_fpga_awaddr_axi_s1_o15;
+    output fabric_fpga_awaddr_axi_s1_o16;
+    output fabric_fpga_awaddr_axi_s1_o17;
+    output fabric_fpga_awaddr_axi_s1_o18;
+    output fabric_fpga_awaddr_axi_s1_o19;
+    output fabric_fpga_awaddr_axi_s1_o2;
+    output fabric_fpga_awaddr_axi_s1_o20;
+    output fabric_fpga_awaddr_axi_s1_o21;
+    output fabric_fpga_awaddr_axi_s1_o22;
+    output fabric_fpga_awaddr_axi_s1_o23;
+    output fabric_fpga_awaddr_axi_s1_o24;
+    output fabric_fpga_awaddr_axi_s1_o25;
+    output fabric_fpga_awaddr_axi_s1_o26;
+    output fabric_fpga_awaddr_axi_s1_o27;
+    output fabric_fpga_awaddr_axi_s1_o28;
+    output fabric_fpga_awaddr_axi_s1_o29;
+    output fabric_fpga_awaddr_axi_s1_o3;
+    output fabric_fpga_awaddr_axi_s1_o30;
+    output fabric_fpga_awaddr_axi_s1_o31;
+    output fabric_fpga_awaddr_axi_s1_o32;
+    output fabric_fpga_awaddr_axi_s1_o33;
+    output fabric_fpga_awaddr_axi_s1_o34;
+    output fabric_fpga_awaddr_axi_s1_o35;
+    output fabric_fpga_awaddr_axi_s1_o36;
+    output fabric_fpga_awaddr_axi_s1_o37;
+    output fabric_fpga_awaddr_axi_s1_o38;
+    output fabric_fpga_awaddr_axi_s1_o39;
+    output fabric_fpga_awaddr_axi_s1_o4;
+    output fabric_fpga_awaddr_axi_s1_o40;
+    output fabric_fpga_awaddr_axi_s1_o5;
+    output fabric_fpga_awaddr_axi_s1_o6;
+    output fabric_fpga_awaddr_axi_s1_o7;
+    output fabric_fpga_awaddr_axi_s1_o8;
+    output fabric_fpga_awaddr_axi_s1_o9;
+    output fabric_fpga_awaddr_axi_s2_o1;
+    output fabric_fpga_awaddr_axi_s2_o10;
+    output fabric_fpga_awaddr_axi_s2_o11;
+    output fabric_fpga_awaddr_axi_s2_o12;
+    output fabric_fpga_awaddr_axi_s2_o13;
+    output fabric_fpga_awaddr_axi_s2_o14;
+    output fabric_fpga_awaddr_axi_s2_o15;
+    output fabric_fpga_awaddr_axi_s2_o16;
+    output fabric_fpga_awaddr_axi_s2_o17;
+    output fabric_fpga_awaddr_axi_s2_o18;
+    output fabric_fpga_awaddr_axi_s2_o19;
+    output fabric_fpga_awaddr_axi_s2_o2;
+    output fabric_fpga_awaddr_axi_s2_o20;
+    output fabric_fpga_awaddr_axi_s2_o21;
+    output fabric_fpga_awaddr_axi_s2_o22;
+    output fabric_fpga_awaddr_axi_s2_o23;
+    output fabric_fpga_awaddr_axi_s2_o24;
+    output fabric_fpga_awaddr_axi_s2_o25;
+    output fabric_fpga_awaddr_axi_s2_o26;
+    output fabric_fpga_awaddr_axi_s2_o27;
+    output fabric_fpga_awaddr_axi_s2_o28;
+    output fabric_fpga_awaddr_axi_s2_o29;
+    output fabric_fpga_awaddr_axi_s2_o3;
+    output fabric_fpga_awaddr_axi_s2_o30;
+    output fabric_fpga_awaddr_axi_s2_o31;
+    output fabric_fpga_awaddr_axi_s2_o32;
+    output fabric_fpga_awaddr_axi_s2_o33;
+    output fabric_fpga_awaddr_axi_s2_o34;
+    output fabric_fpga_awaddr_axi_s2_o35;
+    output fabric_fpga_awaddr_axi_s2_o36;
+    output fabric_fpga_awaddr_axi_s2_o37;
+    output fabric_fpga_awaddr_axi_s2_o38;
+    output fabric_fpga_awaddr_axi_s2_o39;
+    output fabric_fpga_awaddr_axi_s2_o4;
+    output fabric_fpga_awaddr_axi_s2_o40;
+    output fabric_fpga_awaddr_axi_s2_o5;
+    output fabric_fpga_awaddr_axi_s2_o6;
+    output fabric_fpga_awaddr_axi_s2_o7;
+    output fabric_fpga_awaddr_axi_s2_o8;
+    output fabric_fpga_awaddr_axi_s2_o9;
+    input fabric_fpga_awburst_axi_m1_i1;
+    input fabric_fpga_awburst_axi_m1_i2;
+    input fabric_fpga_awburst_axi_m2_i1;
+    input fabric_fpga_awburst_axi_m2_i2;
+    output fabric_fpga_awburst_axi_s1_o1;
+    output fabric_fpga_awburst_axi_s1_o2;
+    output fabric_fpga_awburst_axi_s2_o1;
+    output fabric_fpga_awburst_axi_s2_o2;
+    input fabric_fpga_awcache_axi_m1_i1;
+    input fabric_fpga_awcache_axi_m1_i2;
+    input fabric_fpga_awcache_axi_m1_i3;
+    input fabric_fpga_awcache_axi_m1_i4;
+    input fabric_fpga_awcache_axi_m2_i1;
+    input fabric_fpga_awcache_axi_m2_i2;
+    input fabric_fpga_awcache_axi_m2_i3;
+    input fabric_fpga_awcache_axi_m2_i4;
+    output fabric_fpga_awcache_axi_s1_o1;
+    output fabric_fpga_awcache_axi_s1_o2;
+    output fabric_fpga_awcache_axi_s1_o3;
+    output fabric_fpga_awcache_axi_s1_o4;
+    output fabric_fpga_awcache_axi_s2_o1;
+    output fabric_fpga_awcache_axi_s2_o2;
+    output fabric_fpga_awcache_axi_s2_o3;
+    output fabric_fpga_awcache_axi_s2_o4;
+    input fabric_fpga_awid_axi_m1_i1;
+    input fabric_fpga_awid_axi_m1_i2;
+    input fabric_fpga_awid_axi_m1_i3;
+    input fabric_fpga_awid_axi_m1_i4;
+    input fabric_fpga_awid_axi_m1_i5;
+    input fabric_fpga_awid_axi_m2_i1;
+    input fabric_fpga_awid_axi_m2_i2;
+    input fabric_fpga_awid_axi_m2_i3;
+    input fabric_fpga_awid_axi_m2_i4;
+    input fabric_fpga_awid_axi_m2_i5;
+    output fabric_fpga_awid_axi_s1_o1;
+    output fabric_fpga_awid_axi_s1_o10;
+    output fabric_fpga_awid_axi_s1_o11;
+    output fabric_fpga_awid_axi_s1_o12;
+    output fabric_fpga_awid_axi_s1_o2;
+    output fabric_fpga_awid_axi_s1_o3;
+    output fabric_fpga_awid_axi_s1_o4;
+    output fabric_fpga_awid_axi_s1_o5;
+    output fabric_fpga_awid_axi_s1_o6;
+    output fabric_fpga_awid_axi_s1_o7;
+    output fabric_fpga_awid_axi_s1_o8;
+    output fabric_fpga_awid_axi_s1_o9;
+    output fabric_fpga_awid_axi_s2_o1;
+    output fabric_fpga_awid_axi_s2_o10;
+    output fabric_fpga_awid_axi_s2_o11;
+    output fabric_fpga_awid_axi_s2_o12;
+    output fabric_fpga_awid_axi_s2_o2;
+    output fabric_fpga_awid_axi_s2_o3;
+    output fabric_fpga_awid_axi_s2_o4;
+    output fabric_fpga_awid_axi_s2_o5;
+    output fabric_fpga_awid_axi_s2_o6;
+    output fabric_fpga_awid_axi_s2_o7;
+    output fabric_fpga_awid_axi_s2_o8;
+    output fabric_fpga_awid_axi_s2_o9;
+    input fabric_fpga_awlen_axi_m1_i1;
+    input fabric_fpga_awlen_axi_m1_i2;
+    input fabric_fpga_awlen_axi_m1_i3;
+    input fabric_fpga_awlen_axi_m1_i4;
+    input fabric_fpga_awlen_axi_m1_i5;
+    input fabric_fpga_awlen_axi_m1_i6;
+    input fabric_fpga_awlen_axi_m1_i7;
+    input fabric_fpga_awlen_axi_m1_i8;
+    input fabric_fpga_awlen_axi_m2_i1;
+    input fabric_fpga_awlen_axi_m2_i2;
+    input fabric_fpga_awlen_axi_m2_i3;
+    input fabric_fpga_awlen_axi_m2_i4;
+    input fabric_fpga_awlen_axi_m2_i5;
+    input fabric_fpga_awlen_axi_m2_i6;
+    input fabric_fpga_awlen_axi_m2_i7;
+    input fabric_fpga_awlen_axi_m2_i8;
+    output fabric_fpga_awlen_axi_s1_o1;
+    output fabric_fpga_awlen_axi_s1_o2;
+    output fabric_fpga_awlen_axi_s1_o3;
+    output fabric_fpga_awlen_axi_s1_o4;
+    output fabric_fpga_awlen_axi_s1_o5;
+    output fabric_fpga_awlen_axi_s1_o6;
+    output fabric_fpga_awlen_axi_s1_o7;
+    output fabric_fpga_awlen_axi_s1_o8;
+    output fabric_fpga_awlen_axi_s2_o1;
+    output fabric_fpga_awlen_axi_s2_o2;
+    output fabric_fpga_awlen_axi_s2_o3;
+    output fabric_fpga_awlen_axi_s2_o4;
+    output fabric_fpga_awlen_axi_s2_o5;
+    output fabric_fpga_awlen_axi_s2_o6;
+    output fabric_fpga_awlen_axi_s2_o7;
+    output fabric_fpga_awlen_axi_s2_o8;
+    input fabric_fpga_awlock_axi_m1_i;
+    input fabric_fpga_awlock_axi_m2_i;
+    output fabric_fpga_awlock_axi_s1_o;
+    output fabric_fpga_awlock_axi_s2_o;
+    input fabric_fpga_awprot_axi_m1_i1;
+    input fabric_fpga_awprot_axi_m1_i2;
+    input fabric_fpga_awprot_axi_m1_i3;
+    input fabric_fpga_awprot_axi_m2_i1;
+    input fabric_fpga_awprot_axi_m2_i2;
+    input fabric_fpga_awprot_axi_m2_i3;
+    output fabric_fpga_awprot_axi_s1_o1;
+    output fabric_fpga_awprot_axi_s1_o2;
+    output fabric_fpga_awprot_axi_s1_o3;
+    output fabric_fpga_awprot_axi_s2_o1;
+    output fabric_fpga_awprot_axi_s2_o2;
+    output fabric_fpga_awprot_axi_s2_o3;
+    input fabric_fpga_awqos_axi_m1_i1;
+    input fabric_fpga_awqos_axi_m1_i2;
+    input fabric_fpga_awqos_axi_m1_i3;
+    input fabric_fpga_awqos_axi_m1_i4;
+    input fabric_fpga_awqos_axi_m2_i1;
+    input fabric_fpga_awqos_axi_m2_i2;
+    input fabric_fpga_awqos_axi_m2_i3;
+    input fabric_fpga_awqos_axi_m2_i4;
+    output fabric_fpga_awqos_axi_s1_o1;
+    output fabric_fpga_awqos_axi_s1_o2;
+    output fabric_fpga_awqos_axi_s1_o3;
+    output fabric_fpga_awqos_axi_s1_o4;
+    output fabric_fpga_awqos_axi_s2_o1;
+    output fabric_fpga_awqos_axi_s2_o2;
+    output fabric_fpga_awqos_axi_s2_o3;
+    output fabric_fpga_awqos_axi_s2_o4;
+    output fabric_fpga_awready_axi_m1_o;
+    output fabric_fpga_awready_axi_m2_o;
+    input fabric_fpga_awready_axi_s1_i;
+    input fabric_fpga_awready_axi_s2_i;
+    output fabric_fpga_awregion_axi_s1_o1;
+    output fabric_fpga_awregion_axi_s1_o2;
+    output fabric_fpga_awregion_axi_s1_o3;
+    output fabric_fpga_awregion_axi_s1_o4;
+    output fabric_fpga_awregion_axi_s2_o1;
+    output fabric_fpga_awregion_axi_s2_o2;
+    output fabric_fpga_awregion_axi_s2_o3;
+    output fabric_fpga_awregion_axi_s2_o4;
+    input fabric_fpga_awsize_axi_m1_i1;
+    input fabric_fpga_awsize_axi_m1_i2;
+    input fabric_fpga_awsize_axi_m1_i3;
+    input fabric_fpga_awsize_axi_m2_i1;
+    input fabric_fpga_awsize_axi_m2_i2;
+    input fabric_fpga_awsize_axi_m2_i3;
+    output fabric_fpga_awsize_axi_s1_o1;
+    output fabric_fpga_awsize_axi_s1_o2;
+    output fabric_fpga_awsize_axi_s1_o3;
+    output fabric_fpga_awsize_axi_s2_o1;
+    output fabric_fpga_awsize_axi_s2_o2;
+    output fabric_fpga_awsize_axi_s2_o3;
+    input fabric_fpga_awvalid_axi_m1_i;
+    input fabric_fpga_awvalid_axi_m2_i;
+    output fabric_fpga_awvalid_axi_s1_o;
+    output fabric_fpga_awvalid_axi_s2_o;
+    output fabric_fpga_bid_axi_m1_o1;
+    output fabric_fpga_bid_axi_m1_o2;
+    output fabric_fpga_bid_axi_m1_o3;
+    output fabric_fpga_bid_axi_m1_o4;
+    output fabric_fpga_bid_axi_m1_o5;
+    output fabric_fpga_bid_axi_m2_o1;
+    output fabric_fpga_bid_axi_m2_o2;
+    output fabric_fpga_bid_axi_m2_o3;
+    output fabric_fpga_bid_axi_m2_o4;
+    output fabric_fpga_bid_axi_m2_o5;
+    input fabric_fpga_bid_axi_s1_i1;
+    input fabric_fpga_bid_axi_s1_i10;
+    input fabric_fpga_bid_axi_s1_i11;
+    input fabric_fpga_bid_axi_s1_i12;
+    input fabric_fpga_bid_axi_s1_i2;
+    input fabric_fpga_bid_axi_s1_i3;
+    input fabric_fpga_bid_axi_s1_i4;
+    input fabric_fpga_bid_axi_s1_i5;
+    input fabric_fpga_bid_axi_s1_i6;
+    input fabric_fpga_bid_axi_s1_i7;
+    input fabric_fpga_bid_axi_s1_i8;
+    input fabric_fpga_bid_axi_s1_i9;
+    input fabric_fpga_bid_axi_s2_i1;
+    input fabric_fpga_bid_axi_s2_i10;
+    input fabric_fpga_bid_axi_s2_i11;
+    input fabric_fpga_bid_axi_s2_i12;
+    input fabric_fpga_bid_axi_s2_i2;
+    input fabric_fpga_bid_axi_s2_i3;
+    input fabric_fpga_bid_axi_s2_i4;
+    input fabric_fpga_bid_axi_s2_i5;
+    input fabric_fpga_bid_axi_s2_i6;
+    input fabric_fpga_bid_axi_s2_i7;
+    input fabric_fpga_bid_axi_s2_i8;
+    input fabric_fpga_bid_axi_s2_i9;
+    input fabric_fpga_bready_axi_m1_i;
+    input fabric_fpga_bready_axi_m2_i;
+    output fabric_fpga_bready_axi_s1_o;
+    output fabric_fpga_bready_axi_s2_o;
+    output fabric_fpga_bresp_axi_m1_o1;
+    output fabric_fpga_bresp_axi_m1_o2;
+    output fabric_fpga_bresp_axi_m2_o1;
+    output fabric_fpga_bresp_axi_m2_o2;
+    input fabric_fpga_bresp_axi_s1_i1;
+    input fabric_fpga_bresp_axi_s1_i2;
+    input fabric_fpga_bresp_axi_s2_i1;
+    input fabric_fpga_bresp_axi_s2_i2;
+    output fabric_fpga_bvalid_axi_m1_o;
+    output fabric_fpga_bvalid_axi_m2_o;
+    input fabric_fpga_bvalid_axi_s1_i;
+    input fabric_fpga_bvalid_axi_s2_i;
+    input fabric_fpga_ddr0_araddr_i1;
+    input fabric_fpga_ddr0_araddr_i10;
+    input fabric_fpga_ddr0_araddr_i11;
+    input fabric_fpga_ddr0_araddr_i12;
+    input fabric_fpga_ddr0_araddr_i13;
+    input fabric_fpga_ddr0_araddr_i14;
+    input fabric_fpga_ddr0_araddr_i15;
+    input fabric_fpga_ddr0_araddr_i16;
+    input fabric_fpga_ddr0_araddr_i17;
+    input fabric_fpga_ddr0_araddr_i18;
+    input fabric_fpga_ddr0_araddr_i19;
+    input fabric_fpga_ddr0_araddr_i2;
+    input fabric_fpga_ddr0_araddr_i20;
+    input fabric_fpga_ddr0_araddr_i21;
+    input fabric_fpga_ddr0_araddr_i22;
+    input fabric_fpga_ddr0_araddr_i23;
+    input fabric_fpga_ddr0_araddr_i24;
+    input fabric_fpga_ddr0_araddr_i25;
+    input fabric_fpga_ddr0_araddr_i26;
+    input fabric_fpga_ddr0_araddr_i27;
+    input fabric_fpga_ddr0_araddr_i28;
+    input fabric_fpga_ddr0_araddr_i29;
+    input fabric_fpga_ddr0_araddr_i3;
+    input fabric_fpga_ddr0_araddr_i30;
+    input fabric_fpga_ddr0_araddr_i31;
+    input fabric_fpga_ddr0_araddr_i32;
+    input fabric_fpga_ddr0_araddr_i33;
+    input fabric_fpga_ddr0_araddr_i34;
+    input fabric_fpga_ddr0_araddr_i35;
+    input fabric_fpga_ddr0_araddr_i36;
+    input fabric_fpga_ddr0_araddr_i37;
+    input fabric_fpga_ddr0_araddr_i38;
+    input fabric_fpga_ddr0_araddr_i39;
+    input fabric_fpga_ddr0_araddr_i4;
+    input fabric_fpga_ddr0_araddr_i40;
+    input fabric_fpga_ddr0_araddr_i5;
+    input fabric_fpga_ddr0_araddr_i6;
+    input fabric_fpga_ddr0_araddr_i7;
+    input fabric_fpga_ddr0_araddr_i8;
+    input fabric_fpga_ddr0_araddr_i9;
+    input fabric_fpga_ddr0_arburst_i1;
+    input fabric_fpga_ddr0_arburst_i2;
+    input fabric_fpga_ddr0_arcache_i1;
+    input fabric_fpga_ddr0_arcache_i2;
+    input fabric_fpga_ddr0_arcache_i3;
+    input fabric_fpga_ddr0_arcache_i4;
+    input fabric_fpga_ddr0_arid_i1;
+    input fabric_fpga_ddr0_arid_i2;
+    input fabric_fpga_ddr0_arid_i3;
+    input fabric_fpga_ddr0_arid_i4;
+    input fabric_fpga_ddr0_arid_i5;
+    input fabric_fpga_ddr0_arlen_i1;
+    input fabric_fpga_ddr0_arlen_i2;
+    input fabric_fpga_ddr0_arlen_i3;
+    input fabric_fpga_ddr0_arlen_i4;
+    input fabric_fpga_ddr0_arlen_i5;
+    input fabric_fpga_ddr0_arlen_i6;
+    input fabric_fpga_ddr0_arlen_i7;
+    input fabric_fpga_ddr0_arlen_i8;
+    input fabric_fpga_ddr0_arlock_i;
+    input fabric_fpga_ddr0_arprot_i1;
+    input fabric_fpga_ddr0_arprot_i2;
+    input fabric_fpga_ddr0_arprot_i3;
+    input fabric_fpga_ddr0_arqos_i1;
+    input fabric_fpga_ddr0_arqos_i2;
+    input fabric_fpga_ddr0_arqos_i3;
+    input fabric_fpga_ddr0_arqos_i4;
+    output fabric_fpga_ddr0_arready_o;
+    input fabric_fpga_ddr0_arsize_i1;
+    input fabric_fpga_ddr0_arsize_i2;
+    input fabric_fpga_ddr0_arsize_i3;
+    input fabric_fpga_ddr0_arvalid_i;
+    input fabric_fpga_ddr0_awaddr_i1;
+    input fabric_fpga_ddr0_awaddr_i10;
+    input fabric_fpga_ddr0_awaddr_i11;
+    input fabric_fpga_ddr0_awaddr_i12;
+    input fabric_fpga_ddr0_awaddr_i13;
+    input fabric_fpga_ddr0_awaddr_i14;
+    input fabric_fpga_ddr0_awaddr_i15;
+    input fabric_fpga_ddr0_awaddr_i16;
+    input fabric_fpga_ddr0_awaddr_i17;
+    input fabric_fpga_ddr0_awaddr_i18;
+    input fabric_fpga_ddr0_awaddr_i19;
+    input fabric_fpga_ddr0_awaddr_i2;
+    input fabric_fpga_ddr0_awaddr_i20;
+    input fabric_fpga_ddr0_awaddr_i21;
+    input fabric_fpga_ddr0_awaddr_i22;
+    input fabric_fpga_ddr0_awaddr_i23;
+    input fabric_fpga_ddr0_awaddr_i24;
+    input fabric_fpga_ddr0_awaddr_i25;
+    input fabric_fpga_ddr0_awaddr_i26;
+    input fabric_fpga_ddr0_awaddr_i27;
+    input fabric_fpga_ddr0_awaddr_i28;
+    input fabric_fpga_ddr0_awaddr_i29;
+    input fabric_fpga_ddr0_awaddr_i3;
+    input fabric_fpga_ddr0_awaddr_i30;
+    input fabric_fpga_ddr0_awaddr_i31;
+    input fabric_fpga_ddr0_awaddr_i32;
+    input fabric_fpga_ddr0_awaddr_i33;
+    input fabric_fpga_ddr0_awaddr_i34;
+    input fabric_fpga_ddr0_awaddr_i35;
+    input fabric_fpga_ddr0_awaddr_i36;
+    input fabric_fpga_ddr0_awaddr_i37;
+    input fabric_fpga_ddr0_awaddr_i38;
+    input fabric_fpga_ddr0_awaddr_i39;
+    input fabric_fpga_ddr0_awaddr_i4;
+    input fabric_fpga_ddr0_awaddr_i40;
+    input fabric_fpga_ddr0_awaddr_i5;
+    input fabric_fpga_ddr0_awaddr_i6;
+    input fabric_fpga_ddr0_awaddr_i7;
+    input fabric_fpga_ddr0_awaddr_i8;
+    input fabric_fpga_ddr0_awaddr_i9;
+    input fabric_fpga_ddr0_awburst_i1;
+    input fabric_fpga_ddr0_awburst_i2;
+    input fabric_fpga_ddr0_awcache_i1;
+    input fabric_fpga_ddr0_awcache_i2;
+    input fabric_fpga_ddr0_awcache_i3;
+    input fabric_fpga_ddr0_awcache_i4;
+    input fabric_fpga_ddr0_awid_i1;
+    input fabric_fpga_ddr0_awid_i2;
+    input fabric_fpga_ddr0_awid_i3;
+    input fabric_fpga_ddr0_awid_i4;
+    input fabric_fpga_ddr0_awid_i5;
+    input fabric_fpga_ddr0_awlen_i1;
+    input fabric_fpga_ddr0_awlen_i2;
+    input fabric_fpga_ddr0_awlen_i3;
+    input fabric_fpga_ddr0_awlen_i4;
+    input fabric_fpga_ddr0_awlen_i5;
+    input fabric_fpga_ddr0_awlen_i6;
+    input fabric_fpga_ddr0_awlen_i7;
+    input fabric_fpga_ddr0_awlen_i8;
+    input fabric_fpga_ddr0_awlock_i;
+    input fabric_fpga_ddr0_awprot_i1;
+    input fabric_fpga_ddr0_awprot_i2;
+    input fabric_fpga_ddr0_awprot_i3;
+    input fabric_fpga_ddr0_awqos_i1;
+    input fabric_fpga_ddr0_awqos_i2;
+    input fabric_fpga_ddr0_awqos_i3;
+    input fabric_fpga_ddr0_awqos_i4;
+    output fabric_fpga_ddr0_awready_o;
+    input fabric_fpga_ddr0_awsize_i1;
+    input fabric_fpga_ddr0_awsize_i2;
+    input fabric_fpga_ddr0_awsize_i3;
+    input fabric_fpga_ddr0_awvalid_i;
+    output fabric_fpga_ddr0_bid_o1;
+    output fabric_fpga_ddr0_bid_o2;
+    output fabric_fpga_ddr0_bid_o3;
+    output fabric_fpga_ddr0_bid_o4;
+    output fabric_fpga_ddr0_bid_o5;
+    input fabric_fpga_ddr0_bready_i;
+    output fabric_fpga_ddr0_bresp_o1;
+    output fabric_fpga_ddr0_bresp_o2;
+    output fabric_fpga_ddr0_bvalid_o;
+    output fabric_fpga_ddr0_rdata_o1;
+    output fabric_fpga_ddr0_rdata_o10;
+    output fabric_fpga_ddr0_rdata_o100;
+    output fabric_fpga_ddr0_rdata_o101;
+    output fabric_fpga_ddr0_rdata_o102;
+    output fabric_fpga_ddr0_rdata_o103;
+    output fabric_fpga_ddr0_rdata_o104;
+    output fabric_fpga_ddr0_rdata_o105;
+    output fabric_fpga_ddr0_rdata_o106;
+    output fabric_fpga_ddr0_rdata_o107;
+    output fabric_fpga_ddr0_rdata_o108;
+    output fabric_fpga_ddr0_rdata_o109;
+    output fabric_fpga_ddr0_rdata_o11;
+    output fabric_fpga_ddr0_rdata_o110;
+    output fabric_fpga_ddr0_rdata_o111;
+    output fabric_fpga_ddr0_rdata_o112;
+    output fabric_fpga_ddr0_rdata_o113;
+    output fabric_fpga_ddr0_rdata_o114;
+    output fabric_fpga_ddr0_rdata_o115;
+    output fabric_fpga_ddr0_rdata_o116;
+    output fabric_fpga_ddr0_rdata_o117;
+    output fabric_fpga_ddr0_rdata_o118;
+    output fabric_fpga_ddr0_rdata_o119;
+    output fabric_fpga_ddr0_rdata_o12;
+    output fabric_fpga_ddr0_rdata_o120;
+    output fabric_fpga_ddr0_rdata_o121;
+    output fabric_fpga_ddr0_rdata_o122;
+    output fabric_fpga_ddr0_rdata_o123;
+    output fabric_fpga_ddr0_rdata_o124;
+    output fabric_fpga_ddr0_rdata_o125;
+    output fabric_fpga_ddr0_rdata_o126;
+    output fabric_fpga_ddr0_rdata_o127;
+    output fabric_fpga_ddr0_rdata_o128;
+    output fabric_fpga_ddr0_rdata_o13;
+    output fabric_fpga_ddr0_rdata_o14;
+    output fabric_fpga_ddr0_rdata_o15;
+    output fabric_fpga_ddr0_rdata_o16;
+    output fabric_fpga_ddr0_rdata_o17;
+    output fabric_fpga_ddr0_rdata_o18;
+    output fabric_fpga_ddr0_rdata_o19;
+    output fabric_fpga_ddr0_rdata_o2;
+    output fabric_fpga_ddr0_rdata_o20;
+    output fabric_fpga_ddr0_rdata_o21;
+    output fabric_fpga_ddr0_rdata_o22;
+    output fabric_fpga_ddr0_rdata_o23;
+    output fabric_fpga_ddr0_rdata_o24;
+    output fabric_fpga_ddr0_rdata_o25;
+    output fabric_fpga_ddr0_rdata_o26;
+    output fabric_fpga_ddr0_rdata_o27;
+    output fabric_fpga_ddr0_rdata_o28;
+    output fabric_fpga_ddr0_rdata_o29;
+    output fabric_fpga_ddr0_rdata_o3;
+    output fabric_fpga_ddr0_rdata_o30;
+    output fabric_fpga_ddr0_rdata_o31;
+    output fabric_fpga_ddr0_rdata_o32;
+    output fabric_fpga_ddr0_rdata_o33;
+    output fabric_fpga_ddr0_rdata_o34;
+    output fabric_fpga_ddr0_rdata_o35;
+    output fabric_fpga_ddr0_rdata_o36;
+    output fabric_fpga_ddr0_rdata_o37;
+    output fabric_fpga_ddr0_rdata_o38;
+    output fabric_fpga_ddr0_rdata_o39;
+    output fabric_fpga_ddr0_rdata_o4;
+    output fabric_fpga_ddr0_rdata_o40;
+    output fabric_fpga_ddr0_rdata_o41;
+    output fabric_fpga_ddr0_rdata_o42;
+    output fabric_fpga_ddr0_rdata_o43;
+    output fabric_fpga_ddr0_rdata_o44;
+    output fabric_fpga_ddr0_rdata_o45;
+    output fabric_fpga_ddr0_rdata_o46;
+    output fabric_fpga_ddr0_rdata_o47;
+    output fabric_fpga_ddr0_rdata_o48;
+    output fabric_fpga_ddr0_rdata_o49;
+    output fabric_fpga_ddr0_rdata_o5;
+    output fabric_fpga_ddr0_rdata_o50;
+    output fabric_fpga_ddr0_rdata_o51;
+    output fabric_fpga_ddr0_rdata_o52;
+    output fabric_fpga_ddr0_rdata_o53;
+    output fabric_fpga_ddr0_rdata_o54;
+    output fabric_fpga_ddr0_rdata_o55;
+    output fabric_fpga_ddr0_rdata_o56;
+    output fabric_fpga_ddr0_rdata_o57;
+    output fabric_fpga_ddr0_rdata_o58;
+    output fabric_fpga_ddr0_rdata_o59;
+    output fabric_fpga_ddr0_rdata_o6;
+    output fabric_fpga_ddr0_rdata_o60;
+    output fabric_fpga_ddr0_rdata_o61;
+    output fabric_fpga_ddr0_rdata_o62;
+    output fabric_fpga_ddr0_rdata_o63;
+    output fabric_fpga_ddr0_rdata_o64;
+    output fabric_fpga_ddr0_rdata_o65;
+    output fabric_fpga_ddr0_rdata_o66;
+    output fabric_fpga_ddr0_rdata_o67;
+    output fabric_fpga_ddr0_rdata_o68;
+    output fabric_fpga_ddr0_rdata_o69;
+    output fabric_fpga_ddr0_rdata_o7;
+    output fabric_fpga_ddr0_rdata_o70;
+    output fabric_fpga_ddr0_rdata_o71;
+    output fabric_fpga_ddr0_rdata_o72;
+    output fabric_fpga_ddr0_rdata_o73;
+    output fabric_fpga_ddr0_rdata_o74;
+    output fabric_fpga_ddr0_rdata_o75;
+    output fabric_fpga_ddr0_rdata_o76;
+    output fabric_fpga_ddr0_rdata_o77;
+    output fabric_fpga_ddr0_rdata_o78;
+    output fabric_fpga_ddr0_rdata_o79;
+    output fabric_fpga_ddr0_rdata_o8;
+    output fabric_fpga_ddr0_rdata_o80;
+    output fabric_fpga_ddr0_rdata_o81;
+    output fabric_fpga_ddr0_rdata_o82;
+    output fabric_fpga_ddr0_rdata_o83;
+    output fabric_fpga_ddr0_rdata_o84;
+    output fabric_fpga_ddr0_rdata_o85;
+    output fabric_fpga_ddr0_rdata_o86;
+    output fabric_fpga_ddr0_rdata_o87;
+    output fabric_fpga_ddr0_rdata_o88;
+    output fabric_fpga_ddr0_rdata_o89;
+    output fabric_fpga_ddr0_rdata_o9;
+    output fabric_fpga_ddr0_rdata_o90;
+    output fabric_fpga_ddr0_rdata_o91;
+    output fabric_fpga_ddr0_rdata_o92;
+    output fabric_fpga_ddr0_rdata_o93;
+    output fabric_fpga_ddr0_rdata_o94;
+    output fabric_fpga_ddr0_rdata_o95;
+    output fabric_fpga_ddr0_rdata_o96;
+    output fabric_fpga_ddr0_rdata_o97;
+    output fabric_fpga_ddr0_rdata_o98;
+    output fabric_fpga_ddr0_rdata_o99;
+    output fabric_fpga_ddr0_rid_o1;
+    output fabric_fpga_ddr0_rid_o2;
+    output fabric_fpga_ddr0_rid_o3;
+    output fabric_fpga_ddr0_rid_o4;
+    output fabric_fpga_ddr0_rid_o5;
+    output fabric_fpga_ddr0_rlast_o;
+    input fabric_fpga_ddr0_rready_i;
+    output fabric_fpga_ddr0_rresp_o1;
+    output fabric_fpga_ddr0_rresp_o2;
+    output fabric_fpga_ddr0_rvalid_o;
+    input fabric_fpga_ddr0_wdata_i1;
+    input fabric_fpga_ddr0_wdata_i10;
+    input fabric_fpga_ddr0_wdata_i100;
+    input fabric_fpga_ddr0_wdata_i101;
+    input fabric_fpga_ddr0_wdata_i102;
+    input fabric_fpga_ddr0_wdata_i103;
+    input fabric_fpga_ddr0_wdata_i104;
+    input fabric_fpga_ddr0_wdata_i105;
+    input fabric_fpga_ddr0_wdata_i106;
+    input fabric_fpga_ddr0_wdata_i107;
+    input fabric_fpga_ddr0_wdata_i108;
+    input fabric_fpga_ddr0_wdata_i109;
+    input fabric_fpga_ddr0_wdata_i11;
+    input fabric_fpga_ddr0_wdata_i110;
+    input fabric_fpga_ddr0_wdata_i111;
+    input fabric_fpga_ddr0_wdata_i112;
+    input fabric_fpga_ddr0_wdata_i113;
+    input fabric_fpga_ddr0_wdata_i114;
+    input fabric_fpga_ddr0_wdata_i115;
+    input fabric_fpga_ddr0_wdata_i116;
+    input fabric_fpga_ddr0_wdata_i117;
+    input fabric_fpga_ddr0_wdata_i118;
+    input fabric_fpga_ddr0_wdata_i119;
+    input fabric_fpga_ddr0_wdata_i12;
+    input fabric_fpga_ddr0_wdata_i120;
+    input fabric_fpga_ddr0_wdata_i121;
+    input fabric_fpga_ddr0_wdata_i122;
+    input fabric_fpga_ddr0_wdata_i123;
+    input fabric_fpga_ddr0_wdata_i124;
+    input fabric_fpga_ddr0_wdata_i125;
+    input fabric_fpga_ddr0_wdata_i126;
+    input fabric_fpga_ddr0_wdata_i127;
+    input fabric_fpga_ddr0_wdata_i128;
+    input fabric_fpga_ddr0_wdata_i13;
+    input fabric_fpga_ddr0_wdata_i14;
+    input fabric_fpga_ddr0_wdata_i15;
+    input fabric_fpga_ddr0_wdata_i16;
+    input fabric_fpga_ddr0_wdata_i17;
+    input fabric_fpga_ddr0_wdata_i18;
+    input fabric_fpga_ddr0_wdata_i19;
+    input fabric_fpga_ddr0_wdata_i2;
+    input fabric_fpga_ddr0_wdata_i20;
+    input fabric_fpga_ddr0_wdata_i21;
+    input fabric_fpga_ddr0_wdata_i22;
+    input fabric_fpga_ddr0_wdata_i23;
+    input fabric_fpga_ddr0_wdata_i24;
+    input fabric_fpga_ddr0_wdata_i25;
+    input fabric_fpga_ddr0_wdata_i26;
+    input fabric_fpga_ddr0_wdata_i27;
+    input fabric_fpga_ddr0_wdata_i28;
+    input fabric_fpga_ddr0_wdata_i29;
+    input fabric_fpga_ddr0_wdata_i3;
+    input fabric_fpga_ddr0_wdata_i30;
+    input fabric_fpga_ddr0_wdata_i31;
+    input fabric_fpga_ddr0_wdata_i32;
+    input fabric_fpga_ddr0_wdata_i33;
+    input fabric_fpga_ddr0_wdata_i34;
+    input fabric_fpga_ddr0_wdata_i35;
+    input fabric_fpga_ddr0_wdata_i36;
+    input fabric_fpga_ddr0_wdata_i37;
+    input fabric_fpga_ddr0_wdata_i38;
+    input fabric_fpga_ddr0_wdata_i39;
+    input fabric_fpga_ddr0_wdata_i4;
+    input fabric_fpga_ddr0_wdata_i40;
+    input fabric_fpga_ddr0_wdata_i41;
+    input fabric_fpga_ddr0_wdata_i42;
+    input fabric_fpga_ddr0_wdata_i43;
+    input fabric_fpga_ddr0_wdata_i44;
+    input fabric_fpga_ddr0_wdata_i45;
+    input fabric_fpga_ddr0_wdata_i46;
+    input fabric_fpga_ddr0_wdata_i47;
+    input fabric_fpga_ddr0_wdata_i48;
+    input fabric_fpga_ddr0_wdata_i49;
+    input fabric_fpga_ddr0_wdata_i5;
+    input fabric_fpga_ddr0_wdata_i50;
+    input fabric_fpga_ddr0_wdata_i51;
+    input fabric_fpga_ddr0_wdata_i52;
+    input fabric_fpga_ddr0_wdata_i53;
+    input fabric_fpga_ddr0_wdata_i54;
+    input fabric_fpga_ddr0_wdata_i55;
+    input fabric_fpga_ddr0_wdata_i56;
+    input fabric_fpga_ddr0_wdata_i57;
+    input fabric_fpga_ddr0_wdata_i58;
+    input fabric_fpga_ddr0_wdata_i59;
+    input fabric_fpga_ddr0_wdata_i6;
+    input fabric_fpga_ddr0_wdata_i60;
+    input fabric_fpga_ddr0_wdata_i61;
+    input fabric_fpga_ddr0_wdata_i62;
+    input fabric_fpga_ddr0_wdata_i63;
+    input fabric_fpga_ddr0_wdata_i64;
+    input fabric_fpga_ddr0_wdata_i65;
+    input fabric_fpga_ddr0_wdata_i66;
+    input fabric_fpga_ddr0_wdata_i67;
+    input fabric_fpga_ddr0_wdata_i68;
+    input fabric_fpga_ddr0_wdata_i69;
+    input fabric_fpga_ddr0_wdata_i7;
+    input fabric_fpga_ddr0_wdata_i70;
+    input fabric_fpga_ddr0_wdata_i71;
+    input fabric_fpga_ddr0_wdata_i72;
+    input fabric_fpga_ddr0_wdata_i73;
+    input fabric_fpga_ddr0_wdata_i74;
+    input fabric_fpga_ddr0_wdata_i75;
+    input fabric_fpga_ddr0_wdata_i76;
+    input fabric_fpga_ddr0_wdata_i77;
+    input fabric_fpga_ddr0_wdata_i78;
+    input fabric_fpga_ddr0_wdata_i79;
+    input fabric_fpga_ddr0_wdata_i8;
+    input fabric_fpga_ddr0_wdata_i80;
+    input fabric_fpga_ddr0_wdata_i81;
+    input fabric_fpga_ddr0_wdata_i82;
+    input fabric_fpga_ddr0_wdata_i83;
+    input fabric_fpga_ddr0_wdata_i84;
+    input fabric_fpga_ddr0_wdata_i85;
+    input fabric_fpga_ddr0_wdata_i86;
+    input fabric_fpga_ddr0_wdata_i87;
+    input fabric_fpga_ddr0_wdata_i88;
+    input fabric_fpga_ddr0_wdata_i89;
+    input fabric_fpga_ddr0_wdata_i9;
+    input fabric_fpga_ddr0_wdata_i90;
+    input fabric_fpga_ddr0_wdata_i91;
+    input fabric_fpga_ddr0_wdata_i92;
+    input fabric_fpga_ddr0_wdata_i93;
+    input fabric_fpga_ddr0_wdata_i94;
+    input fabric_fpga_ddr0_wdata_i95;
+    input fabric_fpga_ddr0_wdata_i96;
+    input fabric_fpga_ddr0_wdata_i97;
+    input fabric_fpga_ddr0_wdata_i98;
+    input fabric_fpga_ddr0_wdata_i99;
+    input fabric_fpga_ddr0_wlast_i;
+    output fabric_fpga_ddr0_wready_o;
+    input fabric_fpga_ddr0_wstrb_i1;
+    input fabric_fpga_ddr0_wstrb_i10;
+    input fabric_fpga_ddr0_wstrb_i11;
+    input fabric_fpga_ddr0_wstrb_i12;
+    input fabric_fpga_ddr0_wstrb_i13;
+    input fabric_fpga_ddr0_wstrb_i14;
+    input fabric_fpga_ddr0_wstrb_i15;
+    input fabric_fpga_ddr0_wstrb_i16;
+    input fabric_fpga_ddr0_wstrb_i2;
+    input fabric_fpga_ddr0_wstrb_i3;
+    input fabric_fpga_ddr0_wstrb_i4;
+    input fabric_fpga_ddr0_wstrb_i5;
+    input fabric_fpga_ddr0_wstrb_i6;
+    input fabric_fpga_ddr0_wstrb_i7;
+    input fabric_fpga_ddr0_wstrb_i8;
+    input fabric_fpga_ddr0_wstrb_i9;
+    input fabric_fpga_ddr0_wvalid_i;
+    output fabric_fpga_dma_ack_m1_o1;
+    output fabric_fpga_dma_ack_m1_o2;
+    output fabric_fpga_dma_ack_m1_o3;
+    output fabric_fpga_dma_ack_m1_o4;
+    output fabric_fpga_dma_ack_m1_o5;
+    output fabric_fpga_dma_ack_m1_o6;
+    output fabric_fpga_dma_ack_m2_o1;
+    output fabric_fpga_dma_ack_m2_o2;
+    output fabric_fpga_dma_ack_m2_o3;
+    output fabric_fpga_dma_ack_m2_o4;
+    output fabric_fpga_dma_ack_m2_o5;
+    output fabric_fpga_dma_ack_m2_o6;
+    output fabric_fpga_dma_finish_m1_o1;
+    output fabric_fpga_dma_finish_m1_o2;
+    output fabric_fpga_dma_finish_m1_o3;
+    output fabric_fpga_dma_finish_m1_o4;
+    output fabric_fpga_dma_finish_m1_o5;
+    output fabric_fpga_dma_finish_m1_o6;
+    output fabric_fpga_dma_finish_m2_o1;
+    output fabric_fpga_dma_finish_m2_o2;
+    output fabric_fpga_dma_finish_m2_o3;
+    output fabric_fpga_dma_finish_m2_o4;
+    output fabric_fpga_dma_finish_m2_o5;
+    output fabric_fpga_dma_finish_m2_o6;
+    input fabric_fpga_dma_last_m1_i1;
+    input fabric_fpga_dma_last_m1_i2;
+    input fabric_fpga_dma_last_m1_i3;
+    input fabric_fpga_dma_last_m1_i4;
+    input fabric_fpga_dma_last_m1_i5;
+    input fabric_fpga_dma_last_m1_i6;
+    input fabric_fpga_dma_last_m2_i1;
+    input fabric_fpga_dma_last_m2_i2;
+    input fabric_fpga_dma_last_m2_i3;
+    input fabric_fpga_dma_last_m2_i4;
+    input fabric_fpga_dma_last_m2_i5;
+    input fabric_fpga_dma_last_m2_i6;
+    input fabric_fpga_dma_req_m1_i1;
+    input fabric_fpga_dma_req_m1_i2;
+    input fabric_fpga_dma_req_m1_i3;
+    input fabric_fpga_dma_req_m1_i4;
+    input fabric_fpga_dma_req_m1_i5;
+    input fabric_fpga_dma_req_m1_i6;
+    input fabric_fpga_dma_req_m2_i1;
+    input fabric_fpga_dma_req_m2_i2;
+    input fabric_fpga_dma_req_m2_i3;
+    input fabric_fpga_dma_req_m2_i4;
+    input fabric_fpga_dma_req_m2_i5;
+    input fabric_fpga_dma_req_m2_i6;
+    input fabric_fpga_dma_single_m1_i1;
+    input fabric_fpga_dma_single_m1_i2;
+    input fabric_fpga_dma_single_m1_i3;
+    input fabric_fpga_dma_single_m1_i4;
+    input fabric_fpga_dma_single_m1_i5;
+    input fabric_fpga_dma_single_m1_i6;
+    input fabric_fpga_dma_single_m2_i1;
+    input fabric_fpga_dma_single_m2_i2;
+    input fabric_fpga_dma_single_m2_i3;
+    input fabric_fpga_dma_single_m2_i4;
+    input fabric_fpga_dma_single_m2_i5;
+    input fabric_fpga_dma_single_m2_i6;
+    input fabric_fpga_events60_i1;
+    input fabric_fpga_events60_i10;
+    input fabric_fpga_events60_i11;
+    input fabric_fpga_events60_i12;
+    input fabric_fpga_events60_i13;
+    input fabric_fpga_events60_i14;
+    input fabric_fpga_events60_i15;
+    input fabric_fpga_events60_i16;
+    input fabric_fpga_events60_i17;
+    input fabric_fpga_events60_i18;
+    input fabric_fpga_events60_i19;
+    input fabric_fpga_events60_i2;
+    input fabric_fpga_events60_i20;
+    input fabric_fpga_events60_i21;
+    input fabric_fpga_events60_i22;
+    input fabric_fpga_events60_i23;
+    input fabric_fpga_events60_i24;
+    input fabric_fpga_events60_i25;
+    input fabric_fpga_events60_i26;
+    input fabric_fpga_events60_i27;
+    input fabric_fpga_events60_i28;
+    input fabric_fpga_events60_i29;
+    input fabric_fpga_events60_i3;
+    input fabric_fpga_events60_i30;
+    input fabric_fpga_events60_i31;
+    input fabric_fpga_events60_i32;
+    input fabric_fpga_events60_i33;
+    input fabric_fpga_events60_i34;
+    input fabric_fpga_events60_i35;
+    input fabric_fpga_events60_i36;
+    input fabric_fpga_events60_i37;
+    input fabric_fpga_events60_i38;
+    input fabric_fpga_events60_i39;
+    input fabric_fpga_events60_i4;
+    input fabric_fpga_events60_i40;
+    input fabric_fpga_events60_i41;
+    input fabric_fpga_events60_i42;
+    input fabric_fpga_events60_i43;
+    input fabric_fpga_events60_i44;
+    input fabric_fpga_events60_i45;
+    input fabric_fpga_events60_i46;
+    input fabric_fpga_events60_i47;
+    input fabric_fpga_events60_i48;
+    input fabric_fpga_events60_i49;
+    input fabric_fpga_events60_i5;
+    input fabric_fpga_events60_i50;
+    input fabric_fpga_events60_i51;
+    input fabric_fpga_events60_i52;
+    input fabric_fpga_events60_i53;
+    input fabric_fpga_events60_i54;
+    input fabric_fpga_events60_i55;
+    input fabric_fpga_events60_i56;
+    input fabric_fpga_events60_i57;
+    input fabric_fpga_events60_i58;
+    input fabric_fpga_events60_i59;
+    input fabric_fpga_events60_i6;
+    input fabric_fpga_events60_i60;
+    input fabric_fpga_events60_i7;
+    input fabric_fpga_events60_i8;
+    input fabric_fpga_events60_i9;
+    input fabric_fpga_interrupt_in_i1;
+    input fabric_fpga_interrupt_in_i10;
+    input fabric_fpga_interrupt_in_i100;
+    input fabric_fpga_interrupt_in_i101;
+    input fabric_fpga_interrupt_in_i102;
+    input fabric_fpga_interrupt_in_i103;
+    input fabric_fpga_interrupt_in_i104;
+    input fabric_fpga_interrupt_in_i105;
+    input fabric_fpga_interrupt_in_i106;
+    input fabric_fpga_interrupt_in_i107;
+    input fabric_fpga_interrupt_in_i108;
+    input fabric_fpga_interrupt_in_i109;
+    input fabric_fpga_interrupt_in_i11;
+    input fabric_fpga_interrupt_in_i110;
+    input fabric_fpga_interrupt_in_i111;
+    input fabric_fpga_interrupt_in_i112;
+    input fabric_fpga_interrupt_in_i113;
+    input fabric_fpga_interrupt_in_i114;
+    input fabric_fpga_interrupt_in_i115;
+    input fabric_fpga_interrupt_in_i116;
+    input fabric_fpga_interrupt_in_i117;
+    input fabric_fpga_interrupt_in_i118;
+    input fabric_fpga_interrupt_in_i119;
+    input fabric_fpga_interrupt_in_i12;
+    input fabric_fpga_interrupt_in_i120;
+    input fabric_fpga_interrupt_in_i13;
+    input fabric_fpga_interrupt_in_i14;
+    input fabric_fpga_interrupt_in_i15;
+    input fabric_fpga_interrupt_in_i16;
+    input fabric_fpga_interrupt_in_i17;
+    input fabric_fpga_interrupt_in_i18;
+    input fabric_fpga_interrupt_in_i19;
+    input fabric_fpga_interrupt_in_i2;
+    input fabric_fpga_interrupt_in_i20;
+    input fabric_fpga_interrupt_in_i21;
+    input fabric_fpga_interrupt_in_i22;
+    input fabric_fpga_interrupt_in_i23;
+    input fabric_fpga_interrupt_in_i24;
+    input fabric_fpga_interrupt_in_i25;
+    input fabric_fpga_interrupt_in_i26;
+    input fabric_fpga_interrupt_in_i27;
+    input fabric_fpga_interrupt_in_i28;
+    input fabric_fpga_interrupt_in_i29;
+    input fabric_fpga_interrupt_in_i3;
+    input fabric_fpga_interrupt_in_i30;
+    input fabric_fpga_interrupt_in_i31;
+    input fabric_fpga_interrupt_in_i32;
+    input fabric_fpga_interrupt_in_i33;
+    input fabric_fpga_interrupt_in_i34;
+    input fabric_fpga_interrupt_in_i35;
+    input fabric_fpga_interrupt_in_i36;
+    input fabric_fpga_interrupt_in_i37;
+    input fabric_fpga_interrupt_in_i38;
+    input fabric_fpga_interrupt_in_i39;
+    input fabric_fpga_interrupt_in_i4;
+    input fabric_fpga_interrupt_in_i40;
+    input fabric_fpga_interrupt_in_i41;
+    input fabric_fpga_interrupt_in_i42;
+    input fabric_fpga_interrupt_in_i43;
+    input fabric_fpga_interrupt_in_i44;
+    input fabric_fpga_interrupt_in_i45;
+    input fabric_fpga_interrupt_in_i46;
+    input fabric_fpga_interrupt_in_i47;
+    input fabric_fpga_interrupt_in_i48;
+    input fabric_fpga_interrupt_in_i49;
+    input fabric_fpga_interrupt_in_i5;
+    input fabric_fpga_interrupt_in_i50;
+    input fabric_fpga_interrupt_in_i51;
+    input fabric_fpga_interrupt_in_i52;
+    input fabric_fpga_interrupt_in_i53;
+    input fabric_fpga_interrupt_in_i54;
+    input fabric_fpga_interrupt_in_i55;
+    input fabric_fpga_interrupt_in_i56;
+    input fabric_fpga_interrupt_in_i57;
+    input fabric_fpga_interrupt_in_i58;
+    input fabric_fpga_interrupt_in_i59;
+    input fabric_fpga_interrupt_in_i6;
+    input fabric_fpga_interrupt_in_i60;
+    input fabric_fpga_interrupt_in_i61;
+    input fabric_fpga_interrupt_in_i62;
+    input fabric_fpga_interrupt_in_i63;
+    input fabric_fpga_interrupt_in_i64;
+    input fabric_fpga_interrupt_in_i65;
+    input fabric_fpga_interrupt_in_i66;
+    input fabric_fpga_interrupt_in_i67;
+    input fabric_fpga_interrupt_in_i68;
+    input fabric_fpga_interrupt_in_i69;
+    input fabric_fpga_interrupt_in_i7;
+    input fabric_fpga_interrupt_in_i70;
+    input fabric_fpga_interrupt_in_i71;
+    input fabric_fpga_interrupt_in_i72;
+    input fabric_fpga_interrupt_in_i73;
+    input fabric_fpga_interrupt_in_i74;
+    input fabric_fpga_interrupt_in_i75;
+    input fabric_fpga_interrupt_in_i76;
+    input fabric_fpga_interrupt_in_i77;
+    input fabric_fpga_interrupt_in_i78;
+    input fabric_fpga_interrupt_in_i79;
+    input fabric_fpga_interrupt_in_i8;
+    input fabric_fpga_interrupt_in_i80;
+    input fabric_fpga_interrupt_in_i81;
+    input fabric_fpga_interrupt_in_i82;
+    input fabric_fpga_interrupt_in_i83;
+    input fabric_fpga_interrupt_in_i84;
+    input fabric_fpga_interrupt_in_i85;
+    input fabric_fpga_interrupt_in_i86;
+    input fabric_fpga_interrupt_in_i87;
+    input fabric_fpga_interrupt_in_i88;
+    input fabric_fpga_interrupt_in_i89;
+    input fabric_fpga_interrupt_in_i9;
+    input fabric_fpga_interrupt_in_i90;
+    input fabric_fpga_interrupt_in_i91;
+    input fabric_fpga_interrupt_in_i92;
+    input fabric_fpga_interrupt_in_i93;
+    input fabric_fpga_interrupt_in_i94;
+    input fabric_fpga_interrupt_in_i95;
+    input fabric_fpga_interrupt_in_i96;
+    input fabric_fpga_interrupt_in_i97;
+    input fabric_fpga_interrupt_in_i98;
+    input fabric_fpga_interrupt_in_i99;
+    input fabric_fpga_nic_rstn_i1;
+    input fabric_fpga_nic_rstn_i10;
+    input fabric_fpga_nic_rstn_i2;
+    input fabric_fpga_nic_rstn_i3;
+    input fabric_fpga_nic_rstn_i4;
+    input fabric_fpga_nic_rstn_i5;
+    input fabric_fpga_nic_rstn_i6;
+    input fabric_fpga_nic_rstn_i7;
+    input fabric_fpga_nic_rstn_i8;
+    input fabric_fpga_nic_rstn_i9;
+    output fabric_fpga_paddr_apb_o1;
+    output fabric_fpga_paddr_apb_o10;
+    output fabric_fpga_paddr_apb_o11;
+    output fabric_fpga_paddr_apb_o12;
+    output fabric_fpga_paddr_apb_o13;
+    output fabric_fpga_paddr_apb_o14;
+    output fabric_fpga_paddr_apb_o15;
+    output fabric_fpga_paddr_apb_o16;
+    output fabric_fpga_paddr_apb_o17;
+    output fabric_fpga_paddr_apb_o18;
+    output fabric_fpga_paddr_apb_o19;
+    output fabric_fpga_paddr_apb_o2;
+    output fabric_fpga_paddr_apb_o20;
+    output fabric_fpga_paddr_apb_o21;
+    output fabric_fpga_paddr_apb_o22;
+    output fabric_fpga_paddr_apb_o23;
+    output fabric_fpga_paddr_apb_o24;
+    output fabric_fpga_paddr_apb_o25;
+    output fabric_fpga_paddr_apb_o26;
+    output fabric_fpga_paddr_apb_o27;
+    output fabric_fpga_paddr_apb_o28;
+    output fabric_fpga_paddr_apb_o29;
+    output fabric_fpga_paddr_apb_o3;
+    output fabric_fpga_paddr_apb_o30;
+    output fabric_fpga_paddr_apb_o31;
+    output fabric_fpga_paddr_apb_o32;
+    output fabric_fpga_paddr_apb_o4;
+    output fabric_fpga_paddr_apb_o5;
+    output fabric_fpga_paddr_apb_o6;
+    output fabric_fpga_paddr_apb_o7;
+    output fabric_fpga_paddr_apb_o8;
+    output fabric_fpga_paddr_apb_o9;
+    output fabric_fpga_penable_apb_o;
+    input fabric_fpga_pmrstn_i;
+    input fabric_fpga_prdata_apb_i1;
+    input fabric_fpga_prdata_apb_i10;
+    input fabric_fpga_prdata_apb_i11;
+    input fabric_fpga_prdata_apb_i12;
+    input fabric_fpga_prdata_apb_i13;
+    input fabric_fpga_prdata_apb_i14;
+    input fabric_fpga_prdata_apb_i15;
+    input fabric_fpga_prdata_apb_i16;
+    input fabric_fpga_prdata_apb_i17;
+    input fabric_fpga_prdata_apb_i18;
+    input fabric_fpga_prdata_apb_i19;
+    input fabric_fpga_prdata_apb_i2;
+    input fabric_fpga_prdata_apb_i20;
+    input fabric_fpga_prdata_apb_i21;
+    input fabric_fpga_prdata_apb_i22;
+    input fabric_fpga_prdata_apb_i23;
+    input fabric_fpga_prdata_apb_i24;
+    input fabric_fpga_prdata_apb_i25;
+    input fabric_fpga_prdata_apb_i26;
+    input fabric_fpga_prdata_apb_i27;
+    input fabric_fpga_prdata_apb_i28;
+    input fabric_fpga_prdata_apb_i29;
+    input fabric_fpga_prdata_apb_i3;
+    input fabric_fpga_prdata_apb_i30;
+    input fabric_fpga_prdata_apb_i31;
+    input fabric_fpga_prdata_apb_i32;
+    input fabric_fpga_prdata_apb_i4;
+    input fabric_fpga_prdata_apb_i5;
+    input fabric_fpga_prdata_apb_i6;
+    input fabric_fpga_prdata_apb_i7;
+    input fabric_fpga_prdata_apb_i8;
+    input fabric_fpga_prdata_apb_i9;
+    input fabric_fpga_pready_apb_i;
+    output fabric_fpga_psel_apb_o;
+    input fabric_fpga_pslverr_apb_i;
+    output fabric_fpga_pwdata_apb_o1;
+    output fabric_fpga_pwdata_apb_o10;
+    output fabric_fpga_pwdata_apb_o11;
+    output fabric_fpga_pwdata_apb_o12;
+    output fabric_fpga_pwdata_apb_o13;
+    output fabric_fpga_pwdata_apb_o14;
+    output fabric_fpga_pwdata_apb_o15;
+    output fabric_fpga_pwdata_apb_o16;
+    output fabric_fpga_pwdata_apb_o17;
+    output fabric_fpga_pwdata_apb_o18;
+    output fabric_fpga_pwdata_apb_o19;
+    output fabric_fpga_pwdata_apb_o2;
+    output fabric_fpga_pwdata_apb_o20;
+    output fabric_fpga_pwdata_apb_o21;
+    output fabric_fpga_pwdata_apb_o22;
+    output fabric_fpga_pwdata_apb_o23;
+    output fabric_fpga_pwdata_apb_o24;
+    output fabric_fpga_pwdata_apb_o25;
+    output fabric_fpga_pwdata_apb_o26;
+    output fabric_fpga_pwdata_apb_o27;
+    output fabric_fpga_pwdata_apb_o28;
+    output fabric_fpga_pwdata_apb_o29;
+    output fabric_fpga_pwdata_apb_o3;
+    output fabric_fpga_pwdata_apb_o30;
+    output fabric_fpga_pwdata_apb_o31;
+    output fabric_fpga_pwdata_apb_o32;
+    output fabric_fpga_pwdata_apb_o4;
+    output fabric_fpga_pwdata_apb_o5;
+    output fabric_fpga_pwdata_apb_o6;
+    output fabric_fpga_pwdata_apb_o7;
+    output fabric_fpga_pwdata_apb_o8;
+    output fabric_fpga_pwdata_apb_o9;
+    output fabric_fpga_pwrite_apb_o;
+    output fabric_fpga_rdata_axi_m1_o1;
+    output fabric_fpga_rdata_axi_m1_o10;
+    output fabric_fpga_rdata_axi_m1_o100;
+    output fabric_fpga_rdata_axi_m1_o101;
+    output fabric_fpga_rdata_axi_m1_o102;
+    output fabric_fpga_rdata_axi_m1_o103;
+    output fabric_fpga_rdata_axi_m1_o104;
+    output fabric_fpga_rdata_axi_m1_o105;
+    output fabric_fpga_rdata_axi_m1_o106;
+    output fabric_fpga_rdata_axi_m1_o107;
+    output fabric_fpga_rdata_axi_m1_o108;
+    output fabric_fpga_rdata_axi_m1_o109;
+    output fabric_fpga_rdata_axi_m1_o11;
+    output fabric_fpga_rdata_axi_m1_o110;
+    output fabric_fpga_rdata_axi_m1_o111;
+    output fabric_fpga_rdata_axi_m1_o112;
+    output fabric_fpga_rdata_axi_m1_o113;
+    output fabric_fpga_rdata_axi_m1_o114;
+    output fabric_fpga_rdata_axi_m1_o115;
+    output fabric_fpga_rdata_axi_m1_o116;
+    output fabric_fpga_rdata_axi_m1_o117;
+    output fabric_fpga_rdata_axi_m1_o118;
+    output fabric_fpga_rdata_axi_m1_o119;
+    output fabric_fpga_rdata_axi_m1_o12;
+    output fabric_fpga_rdata_axi_m1_o120;
+    output fabric_fpga_rdata_axi_m1_o121;
+    output fabric_fpga_rdata_axi_m1_o122;
+    output fabric_fpga_rdata_axi_m1_o123;
+    output fabric_fpga_rdata_axi_m1_o124;
+    output fabric_fpga_rdata_axi_m1_o125;
+    output fabric_fpga_rdata_axi_m1_o126;
+    output fabric_fpga_rdata_axi_m1_o127;
+    output fabric_fpga_rdata_axi_m1_o128;
+    output fabric_fpga_rdata_axi_m1_o13;
+    output fabric_fpga_rdata_axi_m1_o14;
+    output fabric_fpga_rdata_axi_m1_o15;
+    output fabric_fpga_rdata_axi_m1_o16;
+    output fabric_fpga_rdata_axi_m1_o17;
+    output fabric_fpga_rdata_axi_m1_o18;
+    output fabric_fpga_rdata_axi_m1_o19;
+    output fabric_fpga_rdata_axi_m1_o2;
+    output fabric_fpga_rdata_axi_m1_o20;
+    output fabric_fpga_rdata_axi_m1_o21;
+    output fabric_fpga_rdata_axi_m1_o22;
+    output fabric_fpga_rdata_axi_m1_o23;
+    output fabric_fpga_rdata_axi_m1_o24;
+    output fabric_fpga_rdata_axi_m1_o25;
+    output fabric_fpga_rdata_axi_m1_o26;
+    output fabric_fpga_rdata_axi_m1_o27;
+    output fabric_fpga_rdata_axi_m1_o28;
+    output fabric_fpga_rdata_axi_m1_o29;
+    output fabric_fpga_rdata_axi_m1_o3;
+    output fabric_fpga_rdata_axi_m1_o30;
+    output fabric_fpga_rdata_axi_m1_o31;
+    output fabric_fpga_rdata_axi_m1_o32;
+    output fabric_fpga_rdata_axi_m1_o33;
+    output fabric_fpga_rdata_axi_m1_o34;
+    output fabric_fpga_rdata_axi_m1_o35;
+    output fabric_fpga_rdata_axi_m1_o36;
+    output fabric_fpga_rdata_axi_m1_o37;
+    output fabric_fpga_rdata_axi_m1_o38;
+    output fabric_fpga_rdata_axi_m1_o39;
+    output fabric_fpga_rdata_axi_m1_o4;
+    output fabric_fpga_rdata_axi_m1_o40;
+    output fabric_fpga_rdata_axi_m1_o41;
+    output fabric_fpga_rdata_axi_m1_o42;
+    output fabric_fpga_rdata_axi_m1_o43;
+    output fabric_fpga_rdata_axi_m1_o44;
+    output fabric_fpga_rdata_axi_m1_o45;
+    output fabric_fpga_rdata_axi_m1_o46;
+    output fabric_fpga_rdata_axi_m1_o47;
+    output fabric_fpga_rdata_axi_m1_o48;
+    output fabric_fpga_rdata_axi_m1_o49;
+    output fabric_fpga_rdata_axi_m1_o5;
+    output fabric_fpga_rdata_axi_m1_o50;
+    output fabric_fpga_rdata_axi_m1_o51;
+    output fabric_fpga_rdata_axi_m1_o52;
+    output fabric_fpga_rdata_axi_m1_o53;
+    output fabric_fpga_rdata_axi_m1_o54;
+    output fabric_fpga_rdata_axi_m1_o55;
+    output fabric_fpga_rdata_axi_m1_o56;
+    output fabric_fpga_rdata_axi_m1_o57;
+    output fabric_fpga_rdata_axi_m1_o58;
+    output fabric_fpga_rdata_axi_m1_o59;
+    output fabric_fpga_rdata_axi_m1_o6;
+    output fabric_fpga_rdata_axi_m1_o60;
+    output fabric_fpga_rdata_axi_m1_o61;
+    output fabric_fpga_rdata_axi_m1_o62;
+    output fabric_fpga_rdata_axi_m1_o63;
+    output fabric_fpga_rdata_axi_m1_o64;
+    output fabric_fpga_rdata_axi_m1_o65;
+    output fabric_fpga_rdata_axi_m1_o66;
+    output fabric_fpga_rdata_axi_m1_o67;
+    output fabric_fpga_rdata_axi_m1_o68;
+    output fabric_fpga_rdata_axi_m1_o69;
+    output fabric_fpga_rdata_axi_m1_o7;
+    output fabric_fpga_rdata_axi_m1_o70;
+    output fabric_fpga_rdata_axi_m1_o71;
+    output fabric_fpga_rdata_axi_m1_o72;
+    output fabric_fpga_rdata_axi_m1_o73;
+    output fabric_fpga_rdata_axi_m1_o74;
+    output fabric_fpga_rdata_axi_m1_o75;
+    output fabric_fpga_rdata_axi_m1_o76;
+    output fabric_fpga_rdata_axi_m1_o77;
+    output fabric_fpga_rdata_axi_m1_o78;
+    output fabric_fpga_rdata_axi_m1_o79;
+    output fabric_fpga_rdata_axi_m1_o8;
+    output fabric_fpga_rdata_axi_m1_o80;
+    output fabric_fpga_rdata_axi_m1_o81;
+    output fabric_fpga_rdata_axi_m1_o82;
+    output fabric_fpga_rdata_axi_m1_o83;
+    output fabric_fpga_rdata_axi_m1_o84;
+    output fabric_fpga_rdata_axi_m1_o85;
+    output fabric_fpga_rdata_axi_m1_o86;
+    output fabric_fpga_rdata_axi_m1_o87;
+    output fabric_fpga_rdata_axi_m1_o88;
+    output fabric_fpga_rdata_axi_m1_o89;
+    output fabric_fpga_rdata_axi_m1_o9;
+    output fabric_fpga_rdata_axi_m1_o90;
+    output fabric_fpga_rdata_axi_m1_o91;
+    output fabric_fpga_rdata_axi_m1_o92;
+    output fabric_fpga_rdata_axi_m1_o93;
+    output fabric_fpga_rdata_axi_m1_o94;
+    output fabric_fpga_rdata_axi_m1_o95;
+    output fabric_fpga_rdata_axi_m1_o96;
+    output fabric_fpga_rdata_axi_m1_o97;
+    output fabric_fpga_rdata_axi_m1_o98;
+    output fabric_fpga_rdata_axi_m1_o99;
+    output fabric_fpga_rdata_axi_m2_o1;
+    output fabric_fpga_rdata_axi_m2_o10;
+    output fabric_fpga_rdata_axi_m2_o100;
+    output fabric_fpga_rdata_axi_m2_o101;
+    output fabric_fpga_rdata_axi_m2_o102;
+    output fabric_fpga_rdata_axi_m2_o103;
+    output fabric_fpga_rdata_axi_m2_o104;
+    output fabric_fpga_rdata_axi_m2_o105;
+    output fabric_fpga_rdata_axi_m2_o106;
+    output fabric_fpga_rdata_axi_m2_o107;
+    output fabric_fpga_rdata_axi_m2_o108;
+    output fabric_fpga_rdata_axi_m2_o109;
+    output fabric_fpga_rdata_axi_m2_o11;
+    output fabric_fpga_rdata_axi_m2_o110;
+    output fabric_fpga_rdata_axi_m2_o111;
+    output fabric_fpga_rdata_axi_m2_o112;
+    output fabric_fpga_rdata_axi_m2_o113;
+    output fabric_fpga_rdata_axi_m2_o114;
+    output fabric_fpga_rdata_axi_m2_o115;
+    output fabric_fpga_rdata_axi_m2_o116;
+    output fabric_fpga_rdata_axi_m2_o117;
+    output fabric_fpga_rdata_axi_m2_o118;
+    output fabric_fpga_rdata_axi_m2_o119;
+    output fabric_fpga_rdata_axi_m2_o12;
+    output fabric_fpga_rdata_axi_m2_o120;
+    output fabric_fpga_rdata_axi_m2_o121;
+    output fabric_fpga_rdata_axi_m2_o122;
+    output fabric_fpga_rdata_axi_m2_o123;
+    output fabric_fpga_rdata_axi_m2_o124;
+    output fabric_fpga_rdata_axi_m2_o125;
+    output fabric_fpga_rdata_axi_m2_o126;
+    output fabric_fpga_rdata_axi_m2_o127;
+    output fabric_fpga_rdata_axi_m2_o128;
+    output fabric_fpga_rdata_axi_m2_o13;
+    output fabric_fpga_rdata_axi_m2_o14;
+    output fabric_fpga_rdata_axi_m2_o15;
+    output fabric_fpga_rdata_axi_m2_o16;
+    output fabric_fpga_rdata_axi_m2_o17;
+    output fabric_fpga_rdata_axi_m2_o18;
+    output fabric_fpga_rdata_axi_m2_o19;
+    output fabric_fpga_rdata_axi_m2_o2;
+    output fabric_fpga_rdata_axi_m2_o20;
+    output fabric_fpga_rdata_axi_m2_o21;
+    output fabric_fpga_rdata_axi_m2_o22;
+    output fabric_fpga_rdata_axi_m2_o23;
+    output fabric_fpga_rdata_axi_m2_o24;
+    output fabric_fpga_rdata_axi_m2_o25;
+    output fabric_fpga_rdata_axi_m2_o26;
+    output fabric_fpga_rdata_axi_m2_o27;
+    output fabric_fpga_rdata_axi_m2_o28;
+    output fabric_fpga_rdata_axi_m2_o29;
+    output fabric_fpga_rdata_axi_m2_o3;
+    output fabric_fpga_rdata_axi_m2_o30;
+    output fabric_fpga_rdata_axi_m2_o31;
+    output fabric_fpga_rdata_axi_m2_o32;
+    output fabric_fpga_rdata_axi_m2_o33;
+    output fabric_fpga_rdata_axi_m2_o34;
+    output fabric_fpga_rdata_axi_m2_o35;
+    output fabric_fpga_rdata_axi_m2_o36;
+    output fabric_fpga_rdata_axi_m2_o37;
+    output fabric_fpga_rdata_axi_m2_o38;
+    output fabric_fpga_rdata_axi_m2_o39;
+    output fabric_fpga_rdata_axi_m2_o4;
+    output fabric_fpga_rdata_axi_m2_o40;
+    output fabric_fpga_rdata_axi_m2_o41;
+    output fabric_fpga_rdata_axi_m2_o42;
+    output fabric_fpga_rdata_axi_m2_o43;
+    output fabric_fpga_rdata_axi_m2_o44;
+    output fabric_fpga_rdata_axi_m2_o45;
+    output fabric_fpga_rdata_axi_m2_o46;
+    output fabric_fpga_rdata_axi_m2_o47;
+    output fabric_fpga_rdata_axi_m2_o48;
+    output fabric_fpga_rdata_axi_m2_o49;
+    output fabric_fpga_rdata_axi_m2_o5;
+    output fabric_fpga_rdata_axi_m2_o50;
+    output fabric_fpga_rdata_axi_m2_o51;
+    output fabric_fpga_rdata_axi_m2_o52;
+    output fabric_fpga_rdata_axi_m2_o53;
+    output fabric_fpga_rdata_axi_m2_o54;
+    output fabric_fpga_rdata_axi_m2_o55;
+    output fabric_fpga_rdata_axi_m2_o56;
+    output fabric_fpga_rdata_axi_m2_o57;
+    output fabric_fpga_rdata_axi_m2_o58;
+    output fabric_fpga_rdata_axi_m2_o59;
+    output fabric_fpga_rdata_axi_m2_o6;
+    output fabric_fpga_rdata_axi_m2_o60;
+    output fabric_fpga_rdata_axi_m2_o61;
+    output fabric_fpga_rdata_axi_m2_o62;
+    output fabric_fpga_rdata_axi_m2_o63;
+    output fabric_fpga_rdata_axi_m2_o64;
+    output fabric_fpga_rdata_axi_m2_o65;
+    output fabric_fpga_rdata_axi_m2_o66;
+    output fabric_fpga_rdata_axi_m2_o67;
+    output fabric_fpga_rdata_axi_m2_o68;
+    output fabric_fpga_rdata_axi_m2_o69;
+    output fabric_fpga_rdata_axi_m2_o7;
+    output fabric_fpga_rdata_axi_m2_o70;
+    output fabric_fpga_rdata_axi_m2_o71;
+    output fabric_fpga_rdata_axi_m2_o72;
+    output fabric_fpga_rdata_axi_m2_o73;
+    output fabric_fpga_rdata_axi_m2_o74;
+    output fabric_fpga_rdata_axi_m2_o75;
+    output fabric_fpga_rdata_axi_m2_o76;
+    output fabric_fpga_rdata_axi_m2_o77;
+    output fabric_fpga_rdata_axi_m2_o78;
+    output fabric_fpga_rdata_axi_m2_o79;
+    output fabric_fpga_rdata_axi_m2_o8;
+    output fabric_fpga_rdata_axi_m2_o80;
+    output fabric_fpga_rdata_axi_m2_o81;
+    output fabric_fpga_rdata_axi_m2_o82;
+    output fabric_fpga_rdata_axi_m2_o83;
+    output fabric_fpga_rdata_axi_m2_o84;
+    output fabric_fpga_rdata_axi_m2_o85;
+    output fabric_fpga_rdata_axi_m2_o86;
+    output fabric_fpga_rdata_axi_m2_o87;
+    output fabric_fpga_rdata_axi_m2_o88;
+    output fabric_fpga_rdata_axi_m2_o89;
+    output fabric_fpga_rdata_axi_m2_o9;
+    output fabric_fpga_rdata_axi_m2_o90;
+    output fabric_fpga_rdata_axi_m2_o91;
+    output fabric_fpga_rdata_axi_m2_o92;
+    output fabric_fpga_rdata_axi_m2_o93;
+    output fabric_fpga_rdata_axi_m2_o94;
+    output fabric_fpga_rdata_axi_m2_o95;
+    output fabric_fpga_rdata_axi_m2_o96;
+    output fabric_fpga_rdata_axi_m2_o97;
+    output fabric_fpga_rdata_axi_m2_o98;
+    output fabric_fpga_rdata_axi_m2_o99;
+    input fabric_fpga_rdata_axi_s1_i1;
+    input fabric_fpga_rdata_axi_s1_i10;
+    input fabric_fpga_rdata_axi_s1_i100;
+    input fabric_fpga_rdata_axi_s1_i101;
+    input fabric_fpga_rdata_axi_s1_i102;
+    input fabric_fpga_rdata_axi_s1_i103;
+    input fabric_fpga_rdata_axi_s1_i104;
+    input fabric_fpga_rdata_axi_s1_i105;
+    input fabric_fpga_rdata_axi_s1_i106;
+    input fabric_fpga_rdata_axi_s1_i107;
+    input fabric_fpga_rdata_axi_s1_i108;
+    input fabric_fpga_rdata_axi_s1_i109;
+    input fabric_fpga_rdata_axi_s1_i11;
+    input fabric_fpga_rdata_axi_s1_i110;
+    input fabric_fpga_rdata_axi_s1_i111;
+    input fabric_fpga_rdata_axi_s1_i112;
+    input fabric_fpga_rdata_axi_s1_i113;
+    input fabric_fpga_rdata_axi_s1_i114;
+    input fabric_fpga_rdata_axi_s1_i115;
+    input fabric_fpga_rdata_axi_s1_i116;
+    input fabric_fpga_rdata_axi_s1_i117;
+    input fabric_fpga_rdata_axi_s1_i118;
+    input fabric_fpga_rdata_axi_s1_i119;
+    input fabric_fpga_rdata_axi_s1_i12;
+    input fabric_fpga_rdata_axi_s1_i120;
+    input fabric_fpga_rdata_axi_s1_i121;
+    input fabric_fpga_rdata_axi_s1_i122;
+    input fabric_fpga_rdata_axi_s1_i123;
+    input fabric_fpga_rdata_axi_s1_i124;
+    input fabric_fpga_rdata_axi_s1_i125;
+    input fabric_fpga_rdata_axi_s1_i126;
+    input fabric_fpga_rdata_axi_s1_i127;
+    input fabric_fpga_rdata_axi_s1_i128;
+    input fabric_fpga_rdata_axi_s1_i13;
+    input fabric_fpga_rdata_axi_s1_i14;
+    input fabric_fpga_rdata_axi_s1_i15;
+    input fabric_fpga_rdata_axi_s1_i16;
+    input fabric_fpga_rdata_axi_s1_i17;
+    input fabric_fpga_rdata_axi_s1_i18;
+    input fabric_fpga_rdata_axi_s1_i19;
+    input fabric_fpga_rdata_axi_s1_i2;
+    input fabric_fpga_rdata_axi_s1_i20;
+    input fabric_fpga_rdata_axi_s1_i21;
+    input fabric_fpga_rdata_axi_s1_i22;
+    input fabric_fpga_rdata_axi_s1_i23;
+    input fabric_fpga_rdata_axi_s1_i24;
+    input fabric_fpga_rdata_axi_s1_i25;
+    input fabric_fpga_rdata_axi_s1_i26;
+    input fabric_fpga_rdata_axi_s1_i27;
+    input fabric_fpga_rdata_axi_s1_i28;
+    input fabric_fpga_rdata_axi_s1_i29;
+    input fabric_fpga_rdata_axi_s1_i3;
+    input fabric_fpga_rdata_axi_s1_i30;
+    input fabric_fpga_rdata_axi_s1_i31;
+    input fabric_fpga_rdata_axi_s1_i32;
+    input fabric_fpga_rdata_axi_s1_i33;
+    input fabric_fpga_rdata_axi_s1_i34;
+    input fabric_fpga_rdata_axi_s1_i35;
+    input fabric_fpga_rdata_axi_s1_i36;
+    input fabric_fpga_rdata_axi_s1_i37;
+    input fabric_fpga_rdata_axi_s1_i38;
+    input fabric_fpga_rdata_axi_s1_i39;
+    input fabric_fpga_rdata_axi_s1_i4;
+    input fabric_fpga_rdata_axi_s1_i40;
+    input fabric_fpga_rdata_axi_s1_i41;
+    input fabric_fpga_rdata_axi_s1_i42;
+    input fabric_fpga_rdata_axi_s1_i43;
+    input fabric_fpga_rdata_axi_s1_i44;
+    input fabric_fpga_rdata_axi_s1_i45;
+    input fabric_fpga_rdata_axi_s1_i46;
+    input fabric_fpga_rdata_axi_s1_i47;
+    input fabric_fpga_rdata_axi_s1_i48;
+    input fabric_fpga_rdata_axi_s1_i49;
+    input fabric_fpga_rdata_axi_s1_i5;
+    input fabric_fpga_rdata_axi_s1_i50;
+    input fabric_fpga_rdata_axi_s1_i51;
+    input fabric_fpga_rdata_axi_s1_i52;
+    input fabric_fpga_rdata_axi_s1_i53;
+    input fabric_fpga_rdata_axi_s1_i54;
+    input fabric_fpga_rdata_axi_s1_i55;
+    input fabric_fpga_rdata_axi_s1_i56;
+    input fabric_fpga_rdata_axi_s1_i57;
+    input fabric_fpga_rdata_axi_s1_i58;
+    input fabric_fpga_rdata_axi_s1_i59;
+    input fabric_fpga_rdata_axi_s1_i6;
+    input fabric_fpga_rdata_axi_s1_i60;
+    input fabric_fpga_rdata_axi_s1_i61;
+    input fabric_fpga_rdata_axi_s1_i62;
+    input fabric_fpga_rdata_axi_s1_i63;
+    input fabric_fpga_rdata_axi_s1_i64;
+    input fabric_fpga_rdata_axi_s1_i65;
+    input fabric_fpga_rdata_axi_s1_i66;
+    input fabric_fpga_rdata_axi_s1_i67;
+    input fabric_fpga_rdata_axi_s1_i68;
+    input fabric_fpga_rdata_axi_s1_i69;
+    input fabric_fpga_rdata_axi_s1_i7;
+    input fabric_fpga_rdata_axi_s1_i70;
+    input fabric_fpga_rdata_axi_s1_i71;
+    input fabric_fpga_rdata_axi_s1_i72;
+    input fabric_fpga_rdata_axi_s1_i73;
+    input fabric_fpga_rdata_axi_s1_i74;
+    input fabric_fpga_rdata_axi_s1_i75;
+    input fabric_fpga_rdata_axi_s1_i76;
+    input fabric_fpga_rdata_axi_s1_i77;
+    input fabric_fpga_rdata_axi_s1_i78;
+    input fabric_fpga_rdata_axi_s1_i79;
+    input fabric_fpga_rdata_axi_s1_i8;
+    input fabric_fpga_rdata_axi_s1_i80;
+    input fabric_fpga_rdata_axi_s1_i81;
+    input fabric_fpga_rdata_axi_s1_i82;
+    input fabric_fpga_rdata_axi_s1_i83;
+    input fabric_fpga_rdata_axi_s1_i84;
+    input fabric_fpga_rdata_axi_s1_i85;
+    input fabric_fpga_rdata_axi_s1_i86;
+    input fabric_fpga_rdata_axi_s1_i87;
+    input fabric_fpga_rdata_axi_s1_i88;
+    input fabric_fpga_rdata_axi_s1_i89;
+    input fabric_fpga_rdata_axi_s1_i9;
+    input fabric_fpga_rdata_axi_s1_i90;
+    input fabric_fpga_rdata_axi_s1_i91;
+    input fabric_fpga_rdata_axi_s1_i92;
+    input fabric_fpga_rdata_axi_s1_i93;
+    input fabric_fpga_rdata_axi_s1_i94;
+    input fabric_fpga_rdata_axi_s1_i95;
+    input fabric_fpga_rdata_axi_s1_i96;
+    input fabric_fpga_rdata_axi_s1_i97;
+    input fabric_fpga_rdata_axi_s1_i98;
+    input fabric_fpga_rdata_axi_s1_i99;
+    input fabric_fpga_rdata_axi_s2_i1;
+    input fabric_fpga_rdata_axi_s2_i10;
+    input fabric_fpga_rdata_axi_s2_i100;
+    input fabric_fpga_rdata_axi_s2_i101;
+    input fabric_fpga_rdata_axi_s2_i102;
+    input fabric_fpga_rdata_axi_s2_i103;
+    input fabric_fpga_rdata_axi_s2_i104;
+    input fabric_fpga_rdata_axi_s2_i105;
+    input fabric_fpga_rdata_axi_s2_i106;
+    input fabric_fpga_rdata_axi_s2_i107;
+    input fabric_fpga_rdata_axi_s2_i108;
+    input fabric_fpga_rdata_axi_s2_i109;
+    input fabric_fpga_rdata_axi_s2_i11;
+    input fabric_fpga_rdata_axi_s2_i110;
+    input fabric_fpga_rdata_axi_s2_i111;
+    input fabric_fpga_rdata_axi_s2_i112;
+    input fabric_fpga_rdata_axi_s2_i113;
+    input fabric_fpga_rdata_axi_s2_i114;
+    input fabric_fpga_rdata_axi_s2_i115;
+    input fabric_fpga_rdata_axi_s2_i116;
+    input fabric_fpga_rdata_axi_s2_i117;
+    input fabric_fpga_rdata_axi_s2_i118;
+    input fabric_fpga_rdata_axi_s2_i119;
+    input fabric_fpga_rdata_axi_s2_i12;
+    input fabric_fpga_rdata_axi_s2_i120;
+    input fabric_fpga_rdata_axi_s2_i121;
+    input fabric_fpga_rdata_axi_s2_i122;
+    input fabric_fpga_rdata_axi_s2_i123;
+    input fabric_fpga_rdata_axi_s2_i124;
+    input fabric_fpga_rdata_axi_s2_i125;
+    input fabric_fpga_rdata_axi_s2_i126;
+    input fabric_fpga_rdata_axi_s2_i127;
+    input fabric_fpga_rdata_axi_s2_i128;
+    input fabric_fpga_rdata_axi_s2_i13;
+    input fabric_fpga_rdata_axi_s2_i14;
+    input fabric_fpga_rdata_axi_s2_i15;
+    input fabric_fpga_rdata_axi_s2_i16;
+    input fabric_fpga_rdata_axi_s2_i17;
+    input fabric_fpga_rdata_axi_s2_i18;
+    input fabric_fpga_rdata_axi_s2_i19;
+    input fabric_fpga_rdata_axi_s2_i2;
+    input fabric_fpga_rdata_axi_s2_i20;
+    input fabric_fpga_rdata_axi_s2_i21;
+    input fabric_fpga_rdata_axi_s2_i22;
+    input fabric_fpga_rdata_axi_s2_i23;
+    input fabric_fpga_rdata_axi_s2_i24;
+    input fabric_fpga_rdata_axi_s2_i25;
+    input fabric_fpga_rdata_axi_s2_i26;
+    input fabric_fpga_rdata_axi_s2_i27;
+    input fabric_fpga_rdata_axi_s2_i28;
+    input fabric_fpga_rdata_axi_s2_i29;
+    input fabric_fpga_rdata_axi_s2_i3;
+    input fabric_fpga_rdata_axi_s2_i30;
+    input fabric_fpga_rdata_axi_s2_i31;
+    input fabric_fpga_rdata_axi_s2_i32;
+    input fabric_fpga_rdata_axi_s2_i33;
+    input fabric_fpga_rdata_axi_s2_i34;
+    input fabric_fpga_rdata_axi_s2_i35;
+    input fabric_fpga_rdata_axi_s2_i36;
+    input fabric_fpga_rdata_axi_s2_i37;
+    input fabric_fpga_rdata_axi_s2_i38;
+    input fabric_fpga_rdata_axi_s2_i39;
+    input fabric_fpga_rdata_axi_s2_i4;
+    input fabric_fpga_rdata_axi_s2_i40;
+    input fabric_fpga_rdata_axi_s2_i41;
+    input fabric_fpga_rdata_axi_s2_i42;
+    input fabric_fpga_rdata_axi_s2_i43;
+    input fabric_fpga_rdata_axi_s2_i44;
+    input fabric_fpga_rdata_axi_s2_i45;
+    input fabric_fpga_rdata_axi_s2_i46;
+    input fabric_fpga_rdata_axi_s2_i47;
+    input fabric_fpga_rdata_axi_s2_i48;
+    input fabric_fpga_rdata_axi_s2_i49;
+    input fabric_fpga_rdata_axi_s2_i5;
+    input fabric_fpga_rdata_axi_s2_i50;
+    input fabric_fpga_rdata_axi_s2_i51;
+    input fabric_fpga_rdata_axi_s2_i52;
+    input fabric_fpga_rdata_axi_s2_i53;
+    input fabric_fpga_rdata_axi_s2_i54;
+    input fabric_fpga_rdata_axi_s2_i55;
+    input fabric_fpga_rdata_axi_s2_i56;
+    input fabric_fpga_rdata_axi_s2_i57;
+    input fabric_fpga_rdata_axi_s2_i58;
+    input fabric_fpga_rdata_axi_s2_i59;
+    input fabric_fpga_rdata_axi_s2_i6;
+    input fabric_fpga_rdata_axi_s2_i60;
+    input fabric_fpga_rdata_axi_s2_i61;
+    input fabric_fpga_rdata_axi_s2_i62;
+    input fabric_fpga_rdata_axi_s2_i63;
+    input fabric_fpga_rdata_axi_s2_i64;
+    input fabric_fpga_rdata_axi_s2_i65;
+    input fabric_fpga_rdata_axi_s2_i66;
+    input fabric_fpga_rdata_axi_s2_i67;
+    input fabric_fpga_rdata_axi_s2_i68;
+    input fabric_fpga_rdata_axi_s2_i69;
+    input fabric_fpga_rdata_axi_s2_i7;
+    input fabric_fpga_rdata_axi_s2_i70;
+    input fabric_fpga_rdata_axi_s2_i71;
+    input fabric_fpga_rdata_axi_s2_i72;
+    input fabric_fpga_rdata_axi_s2_i73;
+    input fabric_fpga_rdata_axi_s2_i74;
+    input fabric_fpga_rdata_axi_s2_i75;
+    input fabric_fpga_rdata_axi_s2_i76;
+    input fabric_fpga_rdata_axi_s2_i77;
+    input fabric_fpga_rdata_axi_s2_i78;
+    input fabric_fpga_rdata_axi_s2_i79;
+    input fabric_fpga_rdata_axi_s2_i8;
+    input fabric_fpga_rdata_axi_s2_i80;
+    input fabric_fpga_rdata_axi_s2_i81;
+    input fabric_fpga_rdata_axi_s2_i82;
+    input fabric_fpga_rdata_axi_s2_i83;
+    input fabric_fpga_rdata_axi_s2_i84;
+    input fabric_fpga_rdata_axi_s2_i85;
+    input fabric_fpga_rdata_axi_s2_i86;
+    input fabric_fpga_rdata_axi_s2_i87;
+    input fabric_fpga_rdata_axi_s2_i88;
+    input fabric_fpga_rdata_axi_s2_i89;
+    input fabric_fpga_rdata_axi_s2_i9;
+    input fabric_fpga_rdata_axi_s2_i90;
+    input fabric_fpga_rdata_axi_s2_i91;
+    input fabric_fpga_rdata_axi_s2_i92;
+    input fabric_fpga_rdata_axi_s2_i93;
+    input fabric_fpga_rdata_axi_s2_i94;
+    input fabric_fpga_rdata_axi_s2_i95;
+    input fabric_fpga_rdata_axi_s2_i96;
+    input fabric_fpga_rdata_axi_s2_i97;
+    input fabric_fpga_rdata_axi_s2_i98;
+    input fabric_fpga_rdata_axi_s2_i99;
+    output fabric_fpga_rid_axi_m1_o1;
+    output fabric_fpga_rid_axi_m1_o2;
+    output fabric_fpga_rid_axi_m1_o3;
+    output fabric_fpga_rid_axi_m1_o4;
+    output fabric_fpga_rid_axi_m1_o5;
+    output fabric_fpga_rid_axi_m2_o1;
+    output fabric_fpga_rid_axi_m2_o2;
+    output fabric_fpga_rid_axi_m2_o3;
+    output fabric_fpga_rid_axi_m2_o4;
+    output fabric_fpga_rid_axi_m2_o5;
+    input fabric_fpga_rid_axi_s1_i1;
+    input fabric_fpga_rid_axi_s1_i10;
+    input fabric_fpga_rid_axi_s1_i11;
+    input fabric_fpga_rid_axi_s1_i12;
+    input fabric_fpga_rid_axi_s1_i2;
+    input fabric_fpga_rid_axi_s1_i3;
+    input fabric_fpga_rid_axi_s1_i4;
+    input fabric_fpga_rid_axi_s1_i5;
+    input fabric_fpga_rid_axi_s1_i6;
+    input fabric_fpga_rid_axi_s1_i7;
+    input fabric_fpga_rid_axi_s1_i8;
+    input fabric_fpga_rid_axi_s1_i9;
+    input fabric_fpga_rid_axi_s2_i1;
+    input fabric_fpga_rid_axi_s2_i10;
+    input fabric_fpga_rid_axi_s2_i11;
+    input fabric_fpga_rid_axi_s2_i12;
+    input fabric_fpga_rid_axi_s2_i2;
+    input fabric_fpga_rid_axi_s2_i3;
+    input fabric_fpga_rid_axi_s2_i4;
+    input fabric_fpga_rid_axi_s2_i5;
+    input fabric_fpga_rid_axi_s2_i6;
+    input fabric_fpga_rid_axi_s2_i7;
+    input fabric_fpga_rid_axi_s2_i8;
+    input fabric_fpga_rid_axi_s2_i9;
+    output fabric_fpga_rlast_axi_m1_o;
+    output fabric_fpga_rlast_axi_m2_o;
+    input fabric_fpga_rlast_axi_s1_i;
+    input fabric_fpga_rlast_axi_s2_i;
+    input fabric_fpga_rready_axi_m1_i;
+    input fabric_fpga_rready_axi_m2_i;
+    output fabric_fpga_rready_axi_s1_o;
+    output fabric_fpga_rready_axi_s2_o;
+    output fabric_fpga_rresp_axi_m1_o1;
+    output fabric_fpga_rresp_axi_m1_o2;
+    output fabric_fpga_rresp_axi_m2_o1;
+    output fabric_fpga_rresp_axi_m2_o2;
+    input fabric_fpga_rresp_axi_s1_i1;
+    input fabric_fpga_rresp_axi_s1_i2;
+    input fabric_fpga_rresp_axi_s2_i1;
+    input fabric_fpga_rresp_axi_s2_i2;
+    output fabric_fpga_rvalid_axi_m1_o;
+    output fabric_fpga_rvalid_axi_m2_o;
+    input fabric_fpga_rvalid_axi_s1_i;
+    input fabric_fpga_rvalid_axi_s2_i;
+    input fabric_fpga_sysrstn_i;
+    output fabric_fpga_trigger_in_o1;
+    output fabric_fpga_trigger_in_o2;
+    output fabric_fpga_trigger_in_o3;
+    output fabric_fpga_trigger_in_o4;
+    output fabric_fpga_trigger_in_o5;
+    output fabric_fpga_trigger_in_o6;
+    output fabric_fpga_trigger_in_o7;
+    output fabric_fpga_trigger_in_o8;
+    input fabric_fpga_trigger_out_i1;
+    input fabric_fpga_trigger_out_i2;
+    input fabric_fpga_trigger_out_i3;
+    input fabric_fpga_trigger_out_i4;
+    input fabric_fpga_trigger_out_i5;
+    input fabric_fpga_trigger_out_i6;
+    input fabric_fpga_trigger_out_i7;
+    input fabric_fpga_trigger_out_i8;
+    input fabric_fpga_wdata_axi_m1_i1;
+    input fabric_fpga_wdata_axi_m1_i10;
+    input fabric_fpga_wdata_axi_m1_i100;
+    input fabric_fpga_wdata_axi_m1_i101;
+    input fabric_fpga_wdata_axi_m1_i102;
+    input fabric_fpga_wdata_axi_m1_i103;
+    input fabric_fpga_wdata_axi_m1_i104;
+    input fabric_fpga_wdata_axi_m1_i105;
+    input fabric_fpga_wdata_axi_m1_i106;
+    input fabric_fpga_wdata_axi_m1_i107;
+    input fabric_fpga_wdata_axi_m1_i108;
+    input fabric_fpga_wdata_axi_m1_i109;
+    input fabric_fpga_wdata_axi_m1_i11;
+    input fabric_fpga_wdata_axi_m1_i110;
+    input fabric_fpga_wdata_axi_m1_i111;
+    input fabric_fpga_wdata_axi_m1_i112;
+    input fabric_fpga_wdata_axi_m1_i113;
+    input fabric_fpga_wdata_axi_m1_i114;
+    input fabric_fpga_wdata_axi_m1_i115;
+    input fabric_fpga_wdata_axi_m1_i116;
+    input fabric_fpga_wdata_axi_m1_i117;
+    input fabric_fpga_wdata_axi_m1_i118;
+    input fabric_fpga_wdata_axi_m1_i119;
+    input fabric_fpga_wdata_axi_m1_i12;
+    input fabric_fpga_wdata_axi_m1_i120;
+    input fabric_fpga_wdata_axi_m1_i121;
+    input fabric_fpga_wdata_axi_m1_i122;
+    input fabric_fpga_wdata_axi_m1_i123;
+    input fabric_fpga_wdata_axi_m1_i124;
+    input fabric_fpga_wdata_axi_m1_i125;
+    input fabric_fpga_wdata_axi_m1_i126;
+    input fabric_fpga_wdata_axi_m1_i127;
+    input fabric_fpga_wdata_axi_m1_i128;
+    input fabric_fpga_wdata_axi_m1_i13;
+    input fabric_fpga_wdata_axi_m1_i14;
+    input fabric_fpga_wdata_axi_m1_i15;
+    input fabric_fpga_wdata_axi_m1_i16;
+    input fabric_fpga_wdata_axi_m1_i17;
+    input fabric_fpga_wdata_axi_m1_i18;
+    input fabric_fpga_wdata_axi_m1_i19;
+    input fabric_fpga_wdata_axi_m1_i2;
+    input fabric_fpga_wdata_axi_m1_i20;
+    input fabric_fpga_wdata_axi_m1_i21;
+    input fabric_fpga_wdata_axi_m1_i22;
+    input fabric_fpga_wdata_axi_m1_i23;
+    input fabric_fpga_wdata_axi_m1_i24;
+    input fabric_fpga_wdata_axi_m1_i25;
+    input fabric_fpga_wdata_axi_m1_i26;
+    input fabric_fpga_wdata_axi_m1_i27;
+    input fabric_fpga_wdata_axi_m1_i28;
+    input fabric_fpga_wdata_axi_m1_i29;
+    input fabric_fpga_wdata_axi_m1_i3;
+    input fabric_fpga_wdata_axi_m1_i30;
+    input fabric_fpga_wdata_axi_m1_i31;
+    input fabric_fpga_wdata_axi_m1_i32;
+    input fabric_fpga_wdata_axi_m1_i33;
+    input fabric_fpga_wdata_axi_m1_i34;
+    input fabric_fpga_wdata_axi_m1_i35;
+    input fabric_fpga_wdata_axi_m1_i36;
+    input fabric_fpga_wdata_axi_m1_i37;
+    input fabric_fpga_wdata_axi_m1_i38;
+    input fabric_fpga_wdata_axi_m1_i39;
+    input fabric_fpga_wdata_axi_m1_i4;
+    input fabric_fpga_wdata_axi_m1_i40;
+    input fabric_fpga_wdata_axi_m1_i41;
+    input fabric_fpga_wdata_axi_m1_i42;
+    input fabric_fpga_wdata_axi_m1_i43;
+    input fabric_fpga_wdata_axi_m1_i44;
+    input fabric_fpga_wdata_axi_m1_i45;
+    input fabric_fpga_wdata_axi_m1_i46;
+    input fabric_fpga_wdata_axi_m1_i47;
+    input fabric_fpga_wdata_axi_m1_i48;
+    input fabric_fpga_wdata_axi_m1_i49;
+    input fabric_fpga_wdata_axi_m1_i5;
+    input fabric_fpga_wdata_axi_m1_i50;
+    input fabric_fpga_wdata_axi_m1_i51;
+    input fabric_fpga_wdata_axi_m1_i52;
+    input fabric_fpga_wdata_axi_m1_i53;
+    input fabric_fpga_wdata_axi_m1_i54;
+    input fabric_fpga_wdata_axi_m1_i55;
+    input fabric_fpga_wdata_axi_m1_i56;
+    input fabric_fpga_wdata_axi_m1_i57;
+    input fabric_fpga_wdata_axi_m1_i58;
+    input fabric_fpga_wdata_axi_m1_i59;
+    input fabric_fpga_wdata_axi_m1_i6;
+    input fabric_fpga_wdata_axi_m1_i60;
+    input fabric_fpga_wdata_axi_m1_i61;
+    input fabric_fpga_wdata_axi_m1_i62;
+    input fabric_fpga_wdata_axi_m1_i63;
+    input fabric_fpga_wdata_axi_m1_i64;
+    input fabric_fpga_wdata_axi_m1_i65;
+    input fabric_fpga_wdata_axi_m1_i66;
+    input fabric_fpga_wdata_axi_m1_i67;
+    input fabric_fpga_wdata_axi_m1_i68;
+    input fabric_fpga_wdata_axi_m1_i69;
+    input fabric_fpga_wdata_axi_m1_i7;
+    input fabric_fpga_wdata_axi_m1_i70;
+    input fabric_fpga_wdata_axi_m1_i71;
+    input fabric_fpga_wdata_axi_m1_i72;
+    input fabric_fpga_wdata_axi_m1_i73;
+    input fabric_fpga_wdata_axi_m1_i74;
+    input fabric_fpga_wdata_axi_m1_i75;
+    input fabric_fpga_wdata_axi_m1_i76;
+    input fabric_fpga_wdata_axi_m1_i77;
+    input fabric_fpga_wdata_axi_m1_i78;
+    input fabric_fpga_wdata_axi_m1_i79;
+    input fabric_fpga_wdata_axi_m1_i8;
+    input fabric_fpga_wdata_axi_m1_i80;
+    input fabric_fpga_wdata_axi_m1_i81;
+    input fabric_fpga_wdata_axi_m1_i82;
+    input fabric_fpga_wdata_axi_m1_i83;
+    input fabric_fpga_wdata_axi_m1_i84;
+    input fabric_fpga_wdata_axi_m1_i85;
+    input fabric_fpga_wdata_axi_m1_i86;
+    input fabric_fpga_wdata_axi_m1_i87;
+    input fabric_fpga_wdata_axi_m1_i88;
+    input fabric_fpga_wdata_axi_m1_i89;
+    input fabric_fpga_wdata_axi_m1_i9;
+    input fabric_fpga_wdata_axi_m1_i90;
+    input fabric_fpga_wdata_axi_m1_i91;
+    input fabric_fpga_wdata_axi_m1_i92;
+    input fabric_fpga_wdata_axi_m1_i93;
+    input fabric_fpga_wdata_axi_m1_i94;
+    input fabric_fpga_wdata_axi_m1_i95;
+    input fabric_fpga_wdata_axi_m1_i96;
+    input fabric_fpga_wdata_axi_m1_i97;
+    input fabric_fpga_wdata_axi_m1_i98;
+    input fabric_fpga_wdata_axi_m1_i99;
+    input fabric_fpga_wdata_axi_m2_i1;
+    input fabric_fpga_wdata_axi_m2_i10;
+    input fabric_fpga_wdata_axi_m2_i100;
+    input fabric_fpga_wdata_axi_m2_i101;
+    input fabric_fpga_wdata_axi_m2_i102;
+    input fabric_fpga_wdata_axi_m2_i103;
+    input fabric_fpga_wdata_axi_m2_i104;
+    input fabric_fpga_wdata_axi_m2_i105;
+    input fabric_fpga_wdata_axi_m2_i106;
+    input fabric_fpga_wdata_axi_m2_i107;
+    input fabric_fpga_wdata_axi_m2_i108;
+    input fabric_fpga_wdata_axi_m2_i109;
+    input fabric_fpga_wdata_axi_m2_i11;
+    input fabric_fpga_wdata_axi_m2_i110;
+    input fabric_fpga_wdata_axi_m2_i111;
+    input fabric_fpga_wdata_axi_m2_i112;
+    input fabric_fpga_wdata_axi_m2_i113;
+    input fabric_fpga_wdata_axi_m2_i114;
+    input fabric_fpga_wdata_axi_m2_i115;
+    input fabric_fpga_wdata_axi_m2_i116;
+    input fabric_fpga_wdata_axi_m2_i117;
+    input fabric_fpga_wdata_axi_m2_i118;
+    input fabric_fpga_wdata_axi_m2_i119;
+    input fabric_fpga_wdata_axi_m2_i12;
+    input fabric_fpga_wdata_axi_m2_i120;
+    input fabric_fpga_wdata_axi_m2_i121;
+    input fabric_fpga_wdata_axi_m2_i122;
+    input fabric_fpga_wdata_axi_m2_i123;
+    input fabric_fpga_wdata_axi_m2_i124;
+    input fabric_fpga_wdata_axi_m2_i125;
+    input fabric_fpga_wdata_axi_m2_i126;
+    input fabric_fpga_wdata_axi_m2_i127;
+    input fabric_fpga_wdata_axi_m2_i128;
+    input fabric_fpga_wdata_axi_m2_i13;
+    input fabric_fpga_wdata_axi_m2_i14;
+    input fabric_fpga_wdata_axi_m2_i15;
+    input fabric_fpga_wdata_axi_m2_i16;
+    input fabric_fpga_wdata_axi_m2_i17;
+    input fabric_fpga_wdata_axi_m2_i18;
+    input fabric_fpga_wdata_axi_m2_i19;
+    input fabric_fpga_wdata_axi_m2_i2;
+    input fabric_fpga_wdata_axi_m2_i20;
+    input fabric_fpga_wdata_axi_m2_i21;
+    input fabric_fpga_wdata_axi_m2_i22;
+    input fabric_fpga_wdata_axi_m2_i23;
+    input fabric_fpga_wdata_axi_m2_i24;
+    input fabric_fpga_wdata_axi_m2_i25;
+    input fabric_fpga_wdata_axi_m2_i26;
+    input fabric_fpga_wdata_axi_m2_i27;
+    input fabric_fpga_wdata_axi_m2_i28;
+    input fabric_fpga_wdata_axi_m2_i29;
+    input fabric_fpga_wdata_axi_m2_i3;
+    input fabric_fpga_wdata_axi_m2_i30;
+    input fabric_fpga_wdata_axi_m2_i31;
+    input fabric_fpga_wdata_axi_m2_i32;
+    input fabric_fpga_wdata_axi_m2_i33;
+    input fabric_fpga_wdata_axi_m2_i34;
+    input fabric_fpga_wdata_axi_m2_i35;
+    input fabric_fpga_wdata_axi_m2_i36;
+    input fabric_fpga_wdata_axi_m2_i37;
+    input fabric_fpga_wdata_axi_m2_i38;
+    input fabric_fpga_wdata_axi_m2_i39;
+    input fabric_fpga_wdata_axi_m2_i4;
+    input fabric_fpga_wdata_axi_m2_i40;
+    input fabric_fpga_wdata_axi_m2_i41;
+    input fabric_fpga_wdata_axi_m2_i42;
+    input fabric_fpga_wdata_axi_m2_i43;
+    input fabric_fpga_wdata_axi_m2_i44;
+    input fabric_fpga_wdata_axi_m2_i45;
+    input fabric_fpga_wdata_axi_m2_i46;
+    input fabric_fpga_wdata_axi_m2_i47;
+    input fabric_fpga_wdata_axi_m2_i48;
+    input fabric_fpga_wdata_axi_m2_i49;
+    input fabric_fpga_wdata_axi_m2_i5;
+    input fabric_fpga_wdata_axi_m2_i50;
+    input fabric_fpga_wdata_axi_m2_i51;
+    input fabric_fpga_wdata_axi_m2_i52;
+    input fabric_fpga_wdata_axi_m2_i53;
+    input fabric_fpga_wdata_axi_m2_i54;
+    input fabric_fpga_wdata_axi_m2_i55;
+    input fabric_fpga_wdata_axi_m2_i56;
+    input fabric_fpga_wdata_axi_m2_i57;
+    input fabric_fpga_wdata_axi_m2_i58;
+    input fabric_fpga_wdata_axi_m2_i59;
+    input fabric_fpga_wdata_axi_m2_i6;
+    input fabric_fpga_wdata_axi_m2_i60;
+    input fabric_fpga_wdata_axi_m2_i61;
+    input fabric_fpga_wdata_axi_m2_i62;
+    input fabric_fpga_wdata_axi_m2_i63;
+    input fabric_fpga_wdata_axi_m2_i64;
+    input fabric_fpga_wdata_axi_m2_i65;
+    input fabric_fpga_wdata_axi_m2_i66;
+    input fabric_fpga_wdata_axi_m2_i67;
+    input fabric_fpga_wdata_axi_m2_i68;
+    input fabric_fpga_wdata_axi_m2_i69;
+    input fabric_fpga_wdata_axi_m2_i7;
+    input fabric_fpga_wdata_axi_m2_i70;
+    input fabric_fpga_wdata_axi_m2_i71;
+    input fabric_fpga_wdata_axi_m2_i72;
+    input fabric_fpga_wdata_axi_m2_i73;
+    input fabric_fpga_wdata_axi_m2_i74;
+    input fabric_fpga_wdata_axi_m2_i75;
+    input fabric_fpga_wdata_axi_m2_i76;
+    input fabric_fpga_wdata_axi_m2_i77;
+    input fabric_fpga_wdata_axi_m2_i78;
+    input fabric_fpga_wdata_axi_m2_i79;
+    input fabric_fpga_wdata_axi_m2_i8;
+    input fabric_fpga_wdata_axi_m2_i80;
+    input fabric_fpga_wdata_axi_m2_i81;
+    input fabric_fpga_wdata_axi_m2_i82;
+    input fabric_fpga_wdata_axi_m2_i83;
+    input fabric_fpga_wdata_axi_m2_i84;
+    input fabric_fpga_wdata_axi_m2_i85;
+    input fabric_fpga_wdata_axi_m2_i86;
+    input fabric_fpga_wdata_axi_m2_i87;
+    input fabric_fpga_wdata_axi_m2_i88;
+    input fabric_fpga_wdata_axi_m2_i89;
+    input fabric_fpga_wdata_axi_m2_i9;
+    input fabric_fpga_wdata_axi_m2_i90;
+    input fabric_fpga_wdata_axi_m2_i91;
+    input fabric_fpga_wdata_axi_m2_i92;
+    input fabric_fpga_wdata_axi_m2_i93;
+    input fabric_fpga_wdata_axi_m2_i94;
+    input fabric_fpga_wdata_axi_m2_i95;
+    input fabric_fpga_wdata_axi_m2_i96;
+    input fabric_fpga_wdata_axi_m2_i97;
+    input fabric_fpga_wdata_axi_m2_i98;
+    input fabric_fpga_wdata_axi_m2_i99;
+    output fabric_fpga_wdata_axi_s1_o1;
+    output fabric_fpga_wdata_axi_s1_o10;
+    output fabric_fpga_wdata_axi_s1_o100;
+    output fabric_fpga_wdata_axi_s1_o101;
+    output fabric_fpga_wdata_axi_s1_o102;
+    output fabric_fpga_wdata_axi_s1_o103;
+    output fabric_fpga_wdata_axi_s1_o104;
+    output fabric_fpga_wdata_axi_s1_o105;
+    output fabric_fpga_wdata_axi_s1_o106;
+    output fabric_fpga_wdata_axi_s1_o107;
+    output fabric_fpga_wdata_axi_s1_o108;
+    output fabric_fpga_wdata_axi_s1_o109;
+    output fabric_fpga_wdata_axi_s1_o11;
+    output fabric_fpga_wdata_axi_s1_o110;
+    output fabric_fpga_wdata_axi_s1_o111;
+    output fabric_fpga_wdata_axi_s1_o112;
+    output fabric_fpga_wdata_axi_s1_o113;
+    output fabric_fpga_wdata_axi_s1_o114;
+    output fabric_fpga_wdata_axi_s1_o115;
+    output fabric_fpga_wdata_axi_s1_o116;
+    output fabric_fpga_wdata_axi_s1_o117;
+    output fabric_fpga_wdata_axi_s1_o118;
+    output fabric_fpga_wdata_axi_s1_o119;
+    output fabric_fpga_wdata_axi_s1_o12;
+    output fabric_fpga_wdata_axi_s1_o120;
+    output fabric_fpga_wdata_axi_s1_o121;
+    output fabric_fpga_wdata_axi_s1_o122;
+    output fabric_fpga_wdata_axi_s1_o123;
+    output fabric_fpga_wdata_axi_s1_o124;
+    output fabric_fpga_wdata_axi_s1_o125;
+    output fabric_fpga_wdata_axi_s1_o126;
+    output fabric_fpga_wdata_axi_s1_o127;
+    output fabric_fpga_wdata_axi_s1_o128;
+    output fabric_fpga_wdata_axi_s1_o13;
+    output fabric_fpga_wdata_axi_s1_o14;
+    output fabric_fpga_wdata_axi_s1_o15;
+    output fabric_fpga_wdata_axi_s1_o16;
+    output fabric_fpga_wdata_axi_s1_o17;
+    output fabric_fpga_wdata_axi_s1_o18;
+    output fabric_fpga_wdata_axi_s1_o19;
+    output fabric_fpga_wdata_axi_s1_o2;
+    output fabric_fpga_wdata_axi_s1_o20;
+    output fabric_fpga_wdata_axi_s1_o21;
+    output fabric_fpga_wdata_axi_s1_o22;
+    output fabric_fpga_wdata_axi_s1_o23;
+    output fabric_fpga_wdata_axi_s1_o24;
+    output fabric_fpga_wdata_axi_s1_o25;
+    output fabric_fpga_wdata_axi_s1_o26;
+    output fabric_fpga_wdata_axi_s1_o27;
+    output fabric_fpga_wdata_axi_s1_o28;
+    output fabric_fpga_wdata_axi_s1_o29;
+    output fabric_fpga_wdata_axi_s1_o3;
+    output fabric_fpga_wdata_axi_s1_o30;
+    output fabric_fpga_wdata_axi_s1_o31;
+    output fabric_fpga_wdata_axi_s1_o32;
+    output fabric_fpga_wdata_axi_s1_o33;
+    output fabric_fpga_wdata_axi_s1_o34;
+    output fabric_fpga_wdata_axi_s1_o35;
+    output fabric_fpga_wdata_axi_s1_o36;
+    output fabric_fpga_wdata_axi_s1_o37;
+    output fabric_fpga_wdata_axi_s1_o38;
+    output fabric_fpga_wdata_axi_s1_o39;
+    output fabric_fpga_wdata_axi_s1_o4;
+    output fabric_fpga_wdata_axi_s1_o40;
+    output fabric_fpga_wdata_axi_s1_o41;
+    output fabric_fpga_wdata_axi_s1_o42;
+    output fabric_fpga_wdata_axi_s1_o43;
+    output fabric_fpga_wdata_axi_s1_o44;
+    output fabric_fpga_wdata_axi_s1_o45;
+    output fabric_fpga_wdata_axi_s1_o46;
+    output fabric_fpga_wdata_axi_s1_o47;
+    output fabric_fpga_wdata_axi_s1_o48;
+    output fabric_fpga_wdata_axi_s1_o49;
+    output fabric_fpga_wdata_axi_s1_o5;
+    output fabric_fpga_wdata_axi_s1_o50;
+    output fabric_fpga_wdata_axi_s1_o51;
+    output fabric_fpga_wdata_axi_s1_o52;
+    output fabric_fpga_wdata_axi_s1_o53;
+    output fabric_fpga_wdata_axi_s1_o54;
+    output fabric_fpga_wdata_axi_s1_o55;
+    output fabric_fpga_wdata_axi_s1_o56;
+    output fabric_fpga_wdata_axi_s1_o57;
+    output fabric_fpga_wdata_axi_s1_o58;
+    output fabric_fpga_wdata_axi_s1_o59;
+    output fabric_fpga_wdata_axi_s1_o6;
+    output fabric_fpga_wdata_axi_s1_o60;
+    output fabric_fpga_wdata_axi_s1_o61;
+    output fabric_fpga_wdata_axi_s1_o62;
+    output fabric_fpga_wdata_axi_s1_o63;
+    output fabric_fpga_wdata_axi_s1_o64;
+    output fabric_fpga_wdata_axi_s1_o65;
+    output fabric_fpga_wdata_axi_s1_o66;
+    output fabric_fpga_wdata_axi_s1_o67;
+    output fabric_fpga_wdata_axi_s1_o68;
+    output fabric_fpga_wdata_axi_s1_o69;
+    output fabric_fpga_wdata_axi_s1_o7;
+    output fabric_fpga_wdata_axi_s1_o70;
+    output fabric_fpga_wdata_axi_s1_o71;
+    output fabric_fpga_wdata_axi_s1_o72;
+    output fabric_fpga_wdata_axi_s1_o73;
+    output fabric_fpga_wdata_axi_s1_o74;
+    output fabric_fpga_wdata_axi_s1_o75;
+    output fabric_fpga_wdata_axi_s1_o76;
+    output fabric_fpga_wdata_axi_s1_o77;
+    output fabric_fpga_wdata_axi_s1_o78;
+    output fabric_fpga_wdata_axi_s1_o79;
+    output fabric_fpga_wdata_axi_s1_o8;
+    output fabric_fpga_wdata_axi_s1_o80;
+    output fabric_fpga_wdata_axi_s1_o81;
+    output fabric_fpga_wdata_axi_s1_o82;
+    output fabric_fpga_wdata_axi_s1_o83;
+    output fabric_fpga_wdata_axi_s1_o84;
+    output fabric_fpga_wdata_axi_s1_o85;
+    output fabric_fpga_wdata_axi_s1_o86;
+    output fabric_fpga_wdata_axi_s1_o87;
+    output fabric_fpga_wdata_axi_s1_o88;
+    output fabric_fpga_wdata_axi_s1_o89;
+    output fabric_fpga_wdata_axi_s1_o9;
+    output fabric_fpga_wdata_axi_s1_o90;
+    output fabric_fpga_wdata_axi_s1_o91;
+    output fabric_fpga_wdata_axi_s1_o92;
+    output fabric_fpga_wdata_axi_s1_o93;
+    output fabric_fpga_wdata_axi_s1_o94;
+    output fabric_fpga_wdata_axi_s1_o95;
+    output fabric_fpga_wdata_axi_s1_o96;
+    output fabric_fpga_wdata_axi_s1_o97;
+    output fabric_fpga_wdata_axi_s1_o98;
+    output fabric_fpga_wdata_axi_s1_o99;
+    output fabric_fpga_wdata_axi_s2_o1;
+    output fabric_fpga_wdata_axi_s2_o10;
+    output fabric_fpga_wdata_axi_s2_o100;
+    output fabric_fpga_wdata_axi_s2_o101;
+    output fabric_fpga_wdata_axi_s2_o102;
+    output fabric_fpga_wdata_axi_s2_o103;
+    output fabric_fpga_wdata_axi_s2_o104;
+    output fabric_fpga_wdata_axi_s2_o105;
+    output fabric_fpga_wdata_axi_s2_o106;
+    output fabric_fpga_wdata_axi_s2_o107;
+    output fabric_fpga_wdata_axi_s2_o108;
+    output fabric_fpga_wdata_axi_s2_o109;
+    output fabric_fpga_wdata_axi_s2_o11;
+    output fabric_fpga_wdata_axi_s2_o110;
+    output fabric_fpga_wdata_axi_s2_o111;
+    output fabric_fpga_wdata_axi_s2_o112;
+    output fabric_fpga_wdata_axi_s2_o113;
+    output fabric_fpga_wdata_axi_s2_o114;
+    output fabric_fpga_wdata_axi_s2_o115;
+    output fabric_fpga_wdata_axi_s2_o116;
+    output fabric_fpga_wdata_axi_s2_o117;
+    output fabric_fpga_wdata_axi_s2_o118;
+    output fabric_fpga_wdata_axi_s2_o119;
+    output fabric_fpga_wdata_axi_s2_o12;
+    output fabric_fpga_wdata_axi_s2_o120;
+    output fabric_fpga_wdata_axi_s2_o121;
+    output fabric_fpga_wdata_axi_s2_o122;
+    output fabric_fpga_wdata_axi_s2_o123;
+    output fabric_fpga_wdata_axi_s2_o124;
+    output fabric_fpga_wdata_axi_s2_o125;
+    output fabric_fpga_wdata_axi_s2_o126;
+    output fabric_fpga_wdata_axi_s2_o127;
+    output fabric_fpga_wdata_axi_s2_o128;
+    output fabric_fpga_wdata_axi_s2_o13;
+    output fabric_fpga_wdata_axi_s2_o14;
+    output fabric_fpga_wdata_axi_s2_o15;
+    output fabric_fpga_wdata_axi_s2_o16;
+    output fabric_fpga_wdata_axi_s2_o17;
+    output fabric_fpga_wdata_axi_s2_o18;
+    output fabric_fpga_wdata_axi_s2_o19;
+    output fabric_fpga_wdata_axi_s2_o2;
+    output fabric_fpga_wdata_axi_s2_o20;
+    output fabric_fpga_wdata_axi_s2_o21;
+    output fabric_fpga_wdata_axi_s2_o22;
+    output fabric_fpga_wdata_axi_s2_o23;
+    output fabric_fpga_wdata_axi_s2_o24;
+    output fabric_fpga_wdata_axi_s2_o25;
+    output fabric_fpga_wdata_axi_s2_o26;
+    output fabric_fpga_wdata_axi_s2_o27;
+    output fabric_fpga_wdata_axi_s2_o28;
+    output fabric_fpga_wdata_axi_s2_o29;
+    output fabric_fpga_wdata_axi_s2_o3;
+    output fabric_fpga_wdata_axi_s2_o30;
+    output fabric_fpga_wdata_axi_s2_o31;
+    output fabric_fpga_wdata_axi_s2_o32;
+    output fabric_fpga_wdata_axi_s2_o33;
+    output fabric_fpga_wdata_axi_s2_o34;
+    output fabric_fpga_wdata_axi_s2_o35;
+    output fabric_fpga_wdata_axi_s2_o36;
+    output fabric_fpga_wdata_axi_s2_o37;
+    output fabric_fpga_wdata_axi_s2_o38;
+    output fabric_fpga_wdata_axi_s2_o39;
+    output fabric_fpga_wdata_axi_s2_o4;
+    output fabric_fpga_wdata_axi_s2_o40;
+    output fabric_fpga_wdata_axi_s2_o41;
+    output fabric_fpga_wdata_axi_s2_o42;
+    output fabric_fpga_wdata_axi_s2_o43;
+    output fabric_fpga_wdata_axi_s2_o44;
+    output fabric_fpga_wdata_axi_s2_o45;
+    output fabric_fpga_wdata_axi_s2_o46;
+    output fabric_fpga_wdata_axi_s2_o47;
+    output fabric_fpga_wdata_axi_s2_o48;
+    output fabric_fpga_wdata_axi_s2_o49;
+    output fabric_fpga_wdata_axi_s2_o5;
+    output fabric_fpga_wdata_axi_s2_o50;
+    output fabric_fpga_wdata_axi_s2_o51;
+    output fabric_fpga_wdata_axi_s2_o52;
+    output fabric_fpga_wdata_axi_s2_o53;
+    output fabric_fpga_wdata_axi_s2_o54;
+    output fabric_fpga_wdata_axi_s2_o55;
+    output fabric_fpga_wdata_axi_s2_o56;
+    output fabric_fpga_wdata_axi_s2_o57;
+    output fabric_fpga_wdata_axi_s2_o58;
+    output fabric_fpga_wdata_axi_s2_o59;
+    output fabric_fpga_wdata_axi_s2_o6;
+    output fabric_fpga_wdata_axi_s2_o60;
+    output fabric_fpga_wdata_axi_s2_o61;
+    output fabric_fpga_wdata_axi_s2_o62;
+    output fabric_fpga_wdata_axi_s2_o63;
+    output fabric_fpga_wdata_axi_s2_o64;
+    output fabric_fpga_wdata_axi_s2_o65;
+    output fabric_fpga_wdata_axi_s2_o66;
+    output fabric_fpga_wdata_axi_s2_o67;
+    output fabric_fpga_wdata_axi_s2_o68;
+    output fabric_fpga_wdata_axi_s2_o69;
+    output fabric_fpga_wdata_axi_s2_o7;
+    output fabric_fpga_wdata_axi_s2_o70;
+    output fabric_fpga_wdata_axi_s2_o71;
+    output fabric_fpga_wdata_axi_s2_o72;
+    output fabric_fpga_wdata_axi_s2_o73;
+    output fabric_fpga_wdata_axi_s2_o74;
+    output fabric_fpga_wdata_axi_s2_o75;
+    output fabric_fpga_wdata_axi_s2_o76;
+    output fabric_fpga_wdata_axi_s2_o77;
+    output fabric_fpga_wdata_axi_s2_o78;
+    output fabric_fpga_wdata_axi_s2_o79;
+    output fabric_fpga_wdata_axi_s2_o8;
+    output fabric_fpga_wdata_axi_s2_o80;
+    output fabric_fpga_wdata_axi_s2_o81;
+    output fabric_fpga_wdata_axi_s2_o82;
+    output fabric_fpga_wdata_axi_s2_o83;
+    output fabric_fpga_wdata_axi_s2_o84;
+    output fabric_fpga_wdata_axi_s2_o85;
+    output fabric_fpga_wdata_axi_s2_o86;
+    output fabric_fpga_wdata_axi_s2_o87;
+    output fabric_fpga_wdata_axi_s2_o88;
+    output fabric_fpga_wdata_axi_s2_o89;
+    output fabric_fpga_wdata_axi_s2_o9;
+    output fabric_fpga_wdata_axi_s2_o90;
+    output fabric_fpga_wdata_axi_s2_o91;
+    output fabric_fpga_wdata_axi_s2_o92;
+    output fabric_fpga_wdata_axi_s2_o93;
+    output fabric_fpga_wdata_axi_s2_o94;
+    output fabric_fpga_wdata_axi_s2_o95;
+    output fabric_fpga_wdata_axi_s2_o96;
+    output fabric_fpga_wdata_axi_s2_o97;
+    output fabric_fpga_wdata_axi_s2_o98;
+    output fabric_fpga_wdata_axi_s2_o99;
+    input fabric_fpga_wlast_axi_m1_i;
+    input fabric_fpga_wlast_axi_m2_i;
+    output fabric_fpga_wlast_axi_s1_o;
+    output fabric_fpga_wlast_axi_s2_o;
+    output fabric_fpga_wready_axi_m1_o;
+    output fabric_fpga_wready_axi_m2_o;
+    input fabric_fpga_wready_axi_s1_i;
+    input fabric_fpga_wready_axi_s2_i;
+    input fabric_fpga_wstrb_axi_m1_i1;
+    input fabric_fpga_wstrb_axi_m1_i10;
+    input fabric_fpga_wstrb_axi_m1_i11;
+    input fabric_fpga_wstrb_axi_m1_i12;
+    input fabric_fpga_wstrb_axi_m1_i13;
+    input fabric_fpga_wstrb_axi_m1_i14;
+    input fabric_fpga_wstrb_axi_m1_i15;
+    input fabric_fpga_wstrb_axi_m1_i16;
+    input fabric_fpga_wstrb_axi_m1_i2;
+    input fabric_fpga_wstrb_axi_m1_i3;
+    input fabric_fpga_wstrb_axi_m1_i4;
+    input fabric_fpga_wstrb_axi_m1_i5;
+    input fabric_fpga_wstrb_axi_m1_i6;
+    input fabric_fpga_wstrb_axi_m1_i7;
+    input fabric_fpga_wstrb_axi_m1_i8;
+    input fabric_fpga_wstrb_axi_m1_i9;
+    input fabric_fpga_wstrb_axi_m2_i1;
+    input fabric_fpga_wstrb_axi_m2_i10;
+    input fabric_fpga_wstrb_axi_m2_i11;
+    input fabric_fpga_wstrb_axi_m2_i12;
+    input fabric_fpga_wstrb_axi_m2_i13;
+    input fabric_fpga_wstrb_axi_m2_i14;
+    input fabric_fpga_wstrb_axi_m2_i15;
+    input fabric_fpga_wstrb_axi_m2_i16;
+    input fabric_fpga_wstrb_axi_m2_i2;
+    input fabric_fpga_wstrb_axi_m2_i3;
+    input fabric_fpga_wstrb_axi_m2_i4;
+    input fabric_fpga_wstrb_axi_m2_i5;
+    input fabric_fpga_wstrb_axi_m2_i6;
+    input fabric_fpga_wstrb_axi_m2_i7;
+    input fabric_fpga_wstrb_axi_m2_i8;
+    input fabric_fpga_wstrb_axi_m2_i9;
+    output fabric_fpga_wstrb_axi_s1_o1;
+    output fabric_fpga_wstrb_axi_s1_o10;
+    output fabric_fpga_wstrb_axi_s1_o11;
+    output fabric_fpga_wstrb_axi_s1_o12;
+    output fabric_fpga_wstrb_axi_s1_o13;
+    output fabric_fpga_wstrb_axi_s1_o14;
+    output fabric_fpga_wstrb_axi_s1_o15;
+    output fabric_fpga_wstrb_axi_s1_o16;
+    output fabric_fpga_wstrb_axi_s1_o2;
+    output fabric_fpga_wstrb_axi_s1_o3;
+    output fabric_fpga_wstrb_axi_s1_o4;
+    output fabric_fpga_wstrb_axi_s1_o5;
+    output fabric_fpga_wstrb_axi_s1_o6;
+    output fabric_fpga_wstrb_axi_s1_o7;
+    output fabric_fpga_wstrb_axi_s1_o8;
+    output fabric_fpga_wstrb_axi_s1_o9;
+    output fabric_fpga_wstrb_axi_s2_o1;
+    output fabric_fpga_wstrb_axi_s2_o10;
+    output fabric_fpga_wstrb_axi_s2_o11;
+    output fabric_fpga_wstrb_axi_s2_o12;
+    output fabric_fpga_wstrb_axi_s2_o13;
+    output fabric_fpga_wstrb_axi_s2_o14;
+    output fabric_fpga_wstrb_axi_s2_o15;
+    output fabric_fpga_wstrb_axi_s2_o16;
+    output fabric_fpga_wstrb_axi_s2_o2;
+    output fabric_fpga_wstrb_axi_s2_o3;
+    output fabric_fpga_wstrb_axi_s2_o4;
+    output fabric_fpga_wstrb_axi_s2_o5;
+    output fabric_fpga_wstrb_axi_s2_o6;
+    output fabric_fpga_wstrb_axi_s2_o7;
+    output fabric_fpga_wstrb_axi_s2_o8;
+    output fabric_fpga_wstrb_axi_s2_o9;
+    input fabric_fpga_wvalid_axi_m1_i;
+    input fabric_fpga_wvalid_axi_m2_i;
+    output fabric_fpga_wvalid_axi_s1_o;
+    output fabric_fpga_wvalid_axi_s2_o;
+    output fabric_llpp0_araddr_s_o1;
+    output fabric_llpp0_araddr_s_o10;
+    output fabric_llpp0_araddr_s_o11;
+    output fabric_llpp0_araddr_s_o12;
+    output fabric_llpp0_araddr_s_o13;
+    output fabric_llpp0_araddr_s_o14;
+    output fabric_llpp0_araddr_s_o15;
+    output fabric_llpp0_araddr_s_o16;
+    output fabric_llpp0_araddr_s_o17;
+    output fabric_llpp0_araddr_s_o18;
+    output fabric_llpp0_araddr_s_o19;
+    output fabric_llpp0_araddr_s_o2;
+    output fabric_llpp0_araddr_s_o20;
+    output fabric_llpp0_araddr_s_o21;
+    output fabric_llpp0_araddr_s_o22;
+    output fabric_llpp0_araddr_s_o23;
+    output fabric_llpp0_araddr_s_o24;
+    output fabric_llpp0_araddr_s_o25;
+    output fabric_llpp0_araddr_s_o26;
+    output fabric_llpp0_araddr_s_o27;
+    output fabric_llpp0_araddr_s_o28;
+    output fabric_llpp0_araddr_s_o29;
+    output fabric_llpp0_araddr_s_o3;
+    output fabric_llpp0_araddr_s_o30;
+    output fabric_llpp0_araddr_s_o31;
+    output fabric_llpp0_araddr_s_o32;
+    output fabric_llpp0_araddr_s_o4;
+    output fabric_llpp0_araddr_s_o5;
+    output fabric_llpp0_araddr_s_o6;
+    output fabric_llpp0_araddr_s_o7;
+    output fabric_llpp0_araddr_s_o8;
+    output fabric_llpp0_araddr_s_o9;
+    output fabric_llpp0_arburst_s_o1;
+    output fabric_llpp0_arburst_s_o2;
+    output fabric_llpp0_arcache_s_o1;
+    output fabric_llpp0_arcache_s_o2;
+    output fabric_llpp0_arcache_s_o3;
+    output fabric_llpp0_arcache_s_o4;
+    output fabric_llpp0_arid_s_o1;
+    output fabric_llpp0_arid_s_o10;
+    output fabric_llpp0_arid_s_o11;
+    output fabric_llpp0_arid_s_o12;
+    output fabric_llpp0_arid_s_o2;
+    output fabric_llpp0_arid_s_o3;
+    output fabric_llpp0_arid_s_o4;
+    output fabric_llpp0_arid_s_o5;
+    output fabric_llpp0_arid_s_o6;
+    output fabric_llpp0_arid_s_o7;
+    output fabric_llpp0_arid_s_o8;
+    output fabric_llpp0_arid_s_o9;
+    output fabric_llpp0_arlen_s_o1;
+    output fabric_llpp0_arlen_s_o2;
+    output fabric_llpp0_arlen_s_o3;
+    output fabric_llpp0_arlen_s_o4;
+    output fabric_llpp0_arlen_s_o5;
+    output fabric_llpp0_arlen_s_o6;
+    output fabric_llpp0_arlen_s_o7;
+    output fabric_llpp0_arlen_s_o8;
+    output fabric_llpp0_arlock_s_o;
+    output fabric_llpp0_arprot_s_o1;
+    output fabric_llpp0_arprot_s_o2;
+    output fabric_llpp0_arprot_s_o3;
+    output fabric_llpp0_arqos_s_o1;
+    output fabric_llpp0_arqos_s_o2;
+    output fabric_llpp0_arqos_s_o3;
+    output fabric_llpp0_arqos_s_o4;
+    input fabric_llpp0_arready_s_i;
+    output fabric_llpp0_arsize_s_o1;
+    output fabric_llpp0_arsize_s_o2;
+    output fabric_llpp0_arsize_s_o3;
+    output fabric_llpp0_arvalid_s_o;
+    output fabric_llpp0_awaddr_s_o1;
+    output fabric_llpp0_awaddr_s_o10;
+    output fabric_llpp0_awaddr_s_o11;
+    output fabric_llpp0_awaddr_s_o12;
+    output fabric_llpp0_awaddr_s_o13;
+    output fabric_llpp0_awaddr_s_o14;
+    output fabric_llpp0_awaddr_s_o15;
+    output fabric_llpp0_awaddr_s_o16;
+    output fabric_llpp0_awaddr_s_o17;
+    output fabric_llpp0_awaddr_s_o18;
+    output fabric_llpp0_awaddr_s_o19;
+    output fabric_llpp0_awaddr_s_o2;
+    output fabric_llpp0_awaddr_s_o20;
+    output fabric_llpp0_awaddr_s_o21;
+    output fabric_llpp0_awaddr_s_o22;
+    output fabric_llpp0_awaddr_s_o23;
+    output fabric_llpp0_awaddr_s_o24;
+    output fabric_llpp0_awaddr_s_o25;
+    output fabric_llpp0_awaddr_s_o26;
+    output fabric_llpp0_awaddr_s_o27;
+    output fabric_llpp0_awaddr_s_o28;
+    output fabric_llpp0_awaddr_s_o29;
+    output fabric_llpp0_awaddr_s_o3;
+    output fabric_llpp0_awaddr_s_o30;
+    output fabric_llpp0_awaddr_s_o31;
+    output fabric_llpp0_awaddr_s_o32;
+    output fabric_llpp0_awaddr_s_o4;
+    output fabric_llpp0_awaddr_s_o5;
+    output fabric_llpp0_awaddr_s_o6;
+    output fabric_llpp0_awaddr_s_o7;
+    output fabric_llpp0_awaddr_s_o8;
+    output fabric_llpp0_awaddr_s_o9;
+    output fabric_llpp0_awburst_s_o1;
+    output fabric_llpp0_awburst_s_o2;
+    output fabric_llpp0_awcache_s_o1;
+    output fabric_llpp0_awcache_s_o2;
+    output fabric_llpp0_awcache_s_o3;
+    output fabric_llpp0_awcache_s_o4;
+    output fabric_llpp0_awid_s_o1;
+    output fabric_llpp0_awid_s_o10;
+    output fabric_llpp0_awid_s_o11;
+    output fabric_llpp0_awid_s_o12;
+    output fabric_llpp0_awid_s_o2;
+    output fabric_llpp0_awid_s_o3;
+    output fabric_llpp0_awid_s_o4;
+    output fabric_llpp0_awid_s_o5;
+    output fabric_llpp0_awid_s_o6;
+    output fabric_llpp0_awid_s_o7;
+    output fabric_llpp0_awid_s_o8;
+    output fabric_llpp0_awid_s_o9;
+    output fabric_llpp0_awlen_s_o1;
+    output fabric_llpp0_awlen_s_o2;
+    output fabric_llpp0_awlen_s_o3;
+    output fabric_llpp0_awlen_s_o4;
+    output fabric_llpp0_awlen_s_o5;
+    output fabric_llpp0_awlen_s_o6;
+    output fabric_llpp0_awlen_s_o7;
+    output fabric_llpp0_awlen_s_o8;
+    output fabric_llpp0_awlock_s_o;
+    output fabric_llpp0_awprot_s_o1;
+    output fabric_llpp0_awprot_s_o2;
+    output fabric_llpp0_awprot_s_o3;
+    output fabric_llpp0_awqos_s_o1;
+    output fabric_llpp0_awqos_s_o2;
+    output fabric_llpp0_awqos_s_o3;
+    output fabric_llpp0_awqos_s_o4;
+    input fabric_llpp0_awready_s_i;
+    output fabric_llpp0_awsize_s_o1;
+    output fabric_llpp0_awsize_s_o2;
+    output fabric_llpp0_awsize_s_o3;
+    output fabric_llpp0_awvalid_s_o;
+    input fabric_llpp0_bid_s_i1;
+    input fabric_llpp0_bid_s_i10;
+    input fabric_llpp0_bid_s_i11;
+    input fabric_llpp0_bid_s_i12;
+    input fabric_llpp0_bid_s_i2;
+    input fabric_llpp0_bid_s_i3;
+    input fabric_llpp0_bid_s_i4;
+    input fabric_llpp0_bid_s_i5;
+    input fabric_llpp0_bid_s_i6;
+    input fabric_llpp0_bid_s_i7;
+    input fabric_llpp0_bid_s_i8;
+    input fabric_llpp0_bid_s_i9;
+    output fabric_llpp0_bready_s_o;
+    input fabric_llpp0_bresp_s_i1;
+    input fabric_llpp0_bresp_s_i2;
+    input fabric_llpp0_bvalid_s_i;
+    input fabric_llpp0_rdata_s_i1;
+    input fabric_llpp0_rdata_s_i10;
+    input fabric_llpp0_rdata_s_i11;
+    input fabric_llpp0_rdata_s_i12;
+    input fabric_llpp0_rdata_s_i13;
+    input fabric_llpp0_rdata_s_i14;
+    input fabric_llpp0_rdata_s_i15;
+    input fabric_llpp0_rdata_s_i16;
+    input fabric_llpp0_rdata_s_i17;
+    input fabric_llpp0_rdata_s_i18;
+    input fabric_llpp0_rdata_s_i19;
+    input fabric_llpp0_rdata_s_i2;
+    input fabric_llpp0_rdata_s_i20;
+    input fabric_llpp0_rdata_s_i21;
+    input fabric_llpp0_rdata_s_i22;
+    input fabric_llpp0_rdata_s_i23;
+    input fabric_llpp0_rdata_s_i24;
+    input fabric_llpp0_rdata_s_i25;
+    input fabric_llpp0_rdata_s_i26;
+    input fabric_llpp0_rdata_s_i27;
+    input fabric_llpp0_rdata_s_i28;
+    input fabric_llpp0_rdata_s_i29;
+    input fabric_llpp0_rdata_s_i3;
+    input fabric_llpp0_rdata_s_i30;
+    input fabric_llpp0_rdata_s_i31;
+    input fabric_llpp0_rdata_s_i32;
+    input fabric_llpp0_rdata_s_i4;
+    input fabric_llpp0_rdata_s_i5;
+    input fabric_llpp0_rdata_s_i6;
+    input fabric_llpp0_rdata_s_i7;
+    input fabric_llpp0_rdata_s_i8;
+    input fabric_llpp0_rdata_s_i9;
+    input fabric_llpp0_rid_s_i1;
+    input fabric_llpp0_rid_s_i10;
+    input fabric_llpp0_rid_s_i11;
+    input fabric_llpp0_rid_s_i12;
+    input fabric_llpp0_rid_s_i2;
+    input fabric_llpp0_rid_s_i3;
+    input fabric_llpp0_rid_s_i4;
+    input fabric_llpp0_rid_s_i5;
+    input fabric_llpp0_rid_s_i6;
+    input fabric_llpp0_rid_s_i7;
+    input fabric_llpp0_rid_s_i8;
+    input fabric_llpp0_rid_s_i9;
+    input fabric_llpp0_rlast_s_i;
+    output fabric_llpp0_rready_s_o;
+    input fabric_llpp0_rresp_s_i1;
+    input fabric_llpp0_rresp_s_i2;
+    input fabric_llpp0_rvalid_s_i;
+    output fabric_llpp0_wdata_s_o1;
+    output fabric_llpp0_wdata_s_o10;
+    output fabric_llpp0_wdata_s_o11;
+    output fabric_llpp0_wdata_s_o12;
+    output fabric_llpp0_wdata_s_o13;
+    output fabric_llpp0_wdata_s_o14;
+    output fabric_llpp0_wdata_s_o15;
+    output fabric_llpp0_wdata_s_o16;
+    output fabric_llpp0_wdata_s_o17;
+    output fabric_llpp0_wdata_s_o18;
+    output fabric_llpp0_wdata_s_o19;
+    output fabric_llpp0_wdata_s_o2;
+    output fabric_llpp0_wdata_s_o20;
+    output fabric_llpp0_wdata_s_o21;
+    output fabric_llpp0_wdata_s_o22;
+    output fabric_llpp0_wdata_s_o23;
+    output fabric_llpp0_wdata_s_o24;
+    output fabric_llpp0_wdata_s_o25;
+    output fabric_llpp0_wdata_s_o26;
+    output fabric_llpp0_wdata_s_o27;
+    output fabric_llpp0_wdata_s_o28;
+    output fabric_llpp0_wdata_s_o29;
+    output fabric_llpp0_wdata_s_o3;
+    output fabric_llpp0_wdata_s_o30;
+    output fabric_llpp0_wdata_s_o31;
+    output fabric_llpp0_wdata_s_o32;
+    output fabric_llpp0_wdata_s_o4;
+    output fabric_llpp0_wdata_s_o5;
+    output fabric_llpp0_wdata_s_o6;
+    output fabric_llpp0_wdata_s_o7;
+    output fabric_llpp0_wdata_s_o8;
+    output fabric_llpp0_wdata_s_o9;
+    output fabric_llpp0_wlast_s_o;
+    input fabric_llpp0_wready_s_i;
+    output fabric_llpp0_wstrb_s_o1;
+    output fabric_llpp0_wstrb_s_o2;
+    output fabric_llpp0_wstrb_s_o3;
+    output fabric_llpp0_wstrb_s_o4;
+    output fabric_llpp0_wvalid_s_o;
+    output fabric_llpp1_araddr_s_o1;
+    output fabric_llpp1_araddr_s_o10;
+    output fabric_llpp1_araddr_s_o11;
+    output fabric_llpp1_araddr_s_o12;
+    output fabric_llpp1_araddr_s_o13;
+    output fabric_llpp1_araddr_s_o14;
+    output fabric_llpp1_araddr_s_o15;
+    output fabric_llpp1_araddr_s_o16;
+    output fabric_llpp1_araddr_s_o17;
+    output fabric_llpp1_araddr_s_o18;
+    output fabric_llpp1_araddr_s_o19;
+    output fabric_llpp1_araddr_s_o2;
+    output fabric_llpp1_araddr_s_o20;
+    output fabric_llpp1_araddr_s_o21;
+    output fabric_llpp1_araddr_s_o22;
+    output fabric_llpp1_araddr_s_o23;
+    output fabric_llpp1_araddr_s_o24;
+    output fabric_llpp1_araddr_s_o25;
+    output fabric_llpp1_araddr_s_o26;
+    output fabric_llpp1_araddr_s_o27;
+    output fabric_llpp1_araddr_s_o28;
+    output fabric_llpp1_araddr_s_o29;
+    output fabric_llpp1_araddr_s_o3;
+    output fabric_llpp1_araddr_s_o30;
+    output fabric_llpp1_araddr_s_o31;
+    output fabric_llpp1_araddr_s_o32;
+    output fabric_llpp1_araddr_s_o4;
+    output fabric_llpp1_araddr_s_o5;
+    output fabric_llpp1_araddr_s_o6;
+    output fabric_llpp1_araddr_s_o7;
+    output fabric_llpp1_araddr_s_o8;
+    output fabric_llpp1_araddr_s_o9;
+    output fabric_llpp1_arburst_s_o1;
+    output fabric_llpp1_arburst_s_o2;
+    output fabric_llpp1_arcache_s_o1;
+    output fabric_llpp1_arcache_s_o2;
+    output fabric_llpp1_arcache_s_o3;
+    output fabric_llpp1_arcache_s_o4;
+    output fabric_llpp1_arid_s_o1;
+    output fabric_llpp1_arid_s_o10;
+    output fabric_llpp1_arid_s_o11;
+    output fabric_llpp1_arid_s_o12;
+    output fabric_llpp1_arid_s_o2;
+    output fabric_llpp1_arid_s_o3;
+    output fabric_llpp1_arid_s_o4;
+    output fabric_llpp1_arid_s_o5;
+    output fabric_llpp1_arid_s_o6;
+    output fabric_llpp1_arid_s_o7;
+    output fabric_llpp1_arid_s_o8;
+    output fabric_llpp1_arid_s_o9;
+    output fabric_llpp1_arlen_s_o1;
+    output fabric_llpp1_arlen_s_o2;
+    output fabric_llpp1_arlen_s_o3;
+    output fabric_llpp1_arlen_s_o4;
+    output fabric_llpp1_arlen_s_o5;
+    output fabric_llpp1_arlen_s_o6;
+    output fabric_llpp1_arlen_s_o7;
+    output fabric_llpp1_arlen_s_o8;
+    output fabric_llpp1_arlock_s_o;
+    output fabric_llpp1_arprot_s_o1;
+    output fabric_llpp1_arprot_s_o2;
+    output fabric_llpp1_arprot_s_o3;
+    output fabric_llpp1_arqos_s1_o1;
+    output fabric_llpp1_arqos_s1_o2;
+    output fabric_llpp1_arqos_s1_o3;
+    output fabric_llpp1_arqos_s1_o4;
+    input fabric_llpp1_arready_s_i;
+    output fabric_llpp1_arsize_s_o1;
+    output fabric_llpp1_arsize_s_o2;
+    output fabric_llpp1_arsize_s_o3;
+    output fabric_llpp1_arvalid_s_o;
+    output fabric_llpp1_awaddr_s_o1;
+    output fabric_llpp1_awaddr_s_o10;
+    output fabric_llpp1_awaddr_s_o11;
+    output fabric_llpp1_awaddr_s_o12;
+    output fabric_llpp1_awaddr_s_o13;
+    output fabric_llpp1_awaddr_s_o14;
+    output fabric_llpp1_awaddr_s_o15;
+    output fabric_llpp1_awaddr_s_o16;
+    output fabric_llpp1_awaddr_s_o17;
+    output fabric_llpp1_awaddr_s_o18;
+    output fabric_llpp1_awaddr_s_o19;
+    output fabric_llpp1_awaddr_s_o2;
+    output fabric_llpp1_awaddr_s_o20;
+    output fabric_llpp1_awaddr_s_o21;
+    output fabric_llpp1_awaddr_s_o22;
+    output fabric_llpp1_awaddr_s_o23;
+    output fabric_llpp1_awaddr_s_o24;
+    output fabric_llpp1_awaddr_s_o25;
+    output fabric_llpp1_awaddr_s_o26;
+    output fabric_llpp1_awaddr_s_o27;
+    output fabric_llpp1_awaddr_s_o28;
+    output fabric_llpp1_awaddr_s_o29;
+    output fabric_llpp1_awaddr_s_o3;
+    output fabric_llpp1_awaddr_s_o30;
+    output fabric_llpp1_awaddr_s_o31;
+    output fabric_llpp1_awaddr_s_o32;
+    output fabric_llpp1_awaddr_s_o4;
+    output fabric_llpp1_awaddr_s_o5;
+    output fabric_llpp1_awaddr_s_o6;
+    output fabric_llpp1_awaddr_s_o7;
+    output fabric_llpp1_awaddr_s_o8;
+    output fabric_llpp1_awaddr_s_o9;
+    output fabric_llpp1_awburst_s_o1;
+    output fabric_llpp1_awburst_s_o2;
+    output fabric_llpp1_awcache_s_o1;
+    output fabric_llpp1_awcache_s_o2;
+    output fabric_llpp1_awcache_s_o3;
+    output fabric_llpp1_awcache_s_o4;
+    output fabric_llpp1_awid_s_o1;
+    output fabric_llpp1_awid_s_o10;
+    output fabric_llpp1_awid_s_o11;
+    output fabric_llpp1_awid_s_o12;
+    output fabric_llpp1_awid_s_o2;
+    output fabric_llpp1_awid_s_o3;
+    output fabric_llpp1_awid_s_o4;
+    output fabric_llpp1_awid_s_o5;
+    output fabric_llpp1_awid_s_o6;
+    output fabric_llpp1_awid_s_o7;
+    output fabric_llpp1_awid_s_o8;
+    output fabric_llpp1_awid_s_o9;
+    output fabric_llpp1_awlen_s_o1;
+    output fabric_llpp1_awlen_s_o2;
+    output fabric_llpp1_awlen_s_o3;
+    output fabric_llpp1_awlen_s_o4;
+    output fabric_llpp1_awlen_s_o5;
+    output fabric_llpp1_awlen_s_o6;
+    output fabric_llpp1_awlen_s_o7;
+    output fabric_llpp1_awlen_s_o8;
+    output fabric_llpp1_awlock_s_o;
+    output fabric_llpp1_awprot_s_o1;
+    output fabric_llpp1_awprot_s_o2;
+    output fabric_llpp1_awprot_s_o3;
+    output fabric_llpp1_awqos_s_o1;
+    output fabric_llpp1_awqos_s_o2;
+    output fabric_llpp1_awqos_s_o3;
+    output fabric_llpp1_awqos_s_o4;
+    input fabric_llpp1_awready_s_i;
+    output fabric_llpp1_awsize_s_o1;
+    output fabric_llpp1_awsize_s_o2;
+    output fabric_llpp1_awsize_s_o3;
+    output fabric_llpp1_awvalid_s_o;
+    input fabric_llpp1_bid_s_i1;
+    input fabric_llpp1_bid_s_i10;
+    input fabric_llpp1_bid_s_i11;
+    input fabric_llpp1_bid_s_i12;
+    input fabric_llpp1_bid_s_i2;
+    input fabric_llpp1_bid_s_i3;
+    input fabric_llpp1_bid_s_i4;
+    input fabric_llpp1_bid_s_i5;
+    input fabric_llpp1_bid_s_i6;
+    input fabric_llpp1_bid_s_i7;
+    input fabric_llpp1_bid_s_i8;
+    input fabric_llpp1_bid_s_i9;
+    output fabric_llpp1_bready_s_o;
+    input fabric_llpp1_bresp_s_i1;
+    input fabric_llpp1_bresp_s_i2;
+    input fabric_llpp1_bvalid_s_i;
+    input fabric_llpp1_rdata_s_i1;
+    input fabric_llpp1_rdata_s_i10;
+    input fabric_llpp1_rdata_s_i11;
+    input fabric_llpp1_rdata_s_i12;
+    input fabric_llpp1_rdata_s_i13;
+    input fabric_llpp1_rdata_s_i14;
+    input fabric_llpp1_rdata_s_i15;
+    input fabric_llpp1_rdata_s_i16;
+    input fabric_llpp1_rdata_s_i17;
+    input fabric_llpp1_rdata_s_i18;
+    input fabric_llpp1_rdata_s_i19;
+    input fabric_llpp1_rdata_s_i2;
+    input fabric_llpp1_rdata_s_i20;
+    input fabric_llpp1_rdata_s_i21;
+    input fabric_llpp1_rdata_s_i22;
+    input fabric_llpp1_rdata_s_i23;
+    input fabric_llpp1_rdata_s_i24;
+    input fabric_llpp1_rdata_s_i25;
+    input fabric_llpp1_rdata_s_i26;
+    input fabric_llpp1_rdata_s_i27;
+    input fabric_llpp1_rdata_s_i28;
+    input fabric_llpp1_rdata_s_i29;
+    input fabric_llpp1_rdata_s_i3;
+    input fabric_llpp1_rdata_s_i30;
+    input fabric_llpp1_rdata_s_i31;
+    input fabric_llpp1_rdata_s_i32;
+    input fabric_llpp1_rdata_s_i4;
+    input fabric_llpp1_rdata_s_i5;
+    input fabric_llpp1_rdata_s_i6;
+    input fabric_llpp1_rdata_s_i7;
+    input fabric_llpp1_rdata_s_i8;
+    input fabric_llpp1_rdata_s_i9;
+    input fabric_llpp1_rid_s_i1;
+    input fabric_llpp1_rid_s_i10;
+    input fabric_llpp1_rid_s_i11;
+    input fabric_llpp1_rid_s_i12;
+    input fabric_llpp1_rid_s_i2;
+    input fabric_llpp1_rid_s_i3;
+    input fabric_llpp1_rid_s_i4;
+    input fabric_llpp1_rid_s_i5;
+    input fabric_llpp1_rid_s_i6;
+    input fabric_llpp1_rid_s_i7;
+    input fabric_llpp1_rid_s_i8;
+    input fabric_llpp1_rid_s_i9;
+    input fabric_llpp1_rlast_s_i;
+    output fabric_llpp1_rready_s_o;
+    input fabric_llpp1_rresp_s_i1;
+    input fabric_llpp1_rresp_s_i2;
+    input fabric_llpp1_rvalid_s_i;
+    output fabric_llpp1_wdata_s_o1;
+    output fabric_llpp1_wdata_s_o10;
+    output fabric_llpp1_wdata_s_o11;
+    output fabric_llpp1_wdata_s_o12;
+    output fabric_llpp1_wdata_s_o13;
+    output fabric_llpp1_wdata_s_o14;
+    output fabric_llpp1_wdata_s_o15;
+    output fabric_llpp1_wdata_s_o16;
+    output fabric_llpp1_wdata_s_o17;
+    output fabric_llpp1_wdata_s_o18;
+    output fabric_llpp1_wdata_s_o19;
+    output fabric_llpp1_wdata_s_o2;
+    output fabric_llpp1_wdata_s_o20;
+    output fabric_llpp1_wdata_s_o21;
+    output fabric_llpp1_wdata_s_o22;
+    output fabric_llpp1_wdata_s_o23;
+    output fabric_llpp1_wdata_s_o24;
+    output fabric_llpp1_wdata_s_o25;
+    output fabric_llpp1_wdata_s_o26;
+    output fabric_llpp1_wdata_s_o27;
+    output fabric_llpp1_wdata_s_o28;
+    output fabric_llpp1_wdata_s_o29;
+    output fabric_llpp1_wdata_s_o3;
+    output fabric_llpp1_wdata_s_o30;
+    output fabric_llpp1_wdata_s_o31;
+    output fabric_llpp1_wdata_s_o32;
+    output fabric_llpp1_wdata_s_o4;
+    output fabric_llpp1_wdata_s_o5;
+    output fabric_llpp1_wdata_s_o6;
+    output fabric_llpp1_wdata_s_o7;
+    output fabric_llpp1_wdata_s_o8;
+    output fabric_llpp1_wdata_s_o9;
+    output fabric_llpp1_wlast_s_o;
+    input fabric_llpp1_wready_s_i;
+    output fabric_llpp1_wstrb_s_o1;
+    output fabric_llpp1_wstrb_s_o2;
+    output fabric_llpp1_wstrb_s_o3;
+    output fabric_llpp1_wstrb_s_o4;
+    output fabric_llpp1_wvalid_s_o;
+    output fabric_llpp2_araddr_s_o1;
+    output fabric_llpp2_araddr_s_o10;
+    output fabric_llpp2_araddr_s_o11;
+    output fabric_llpp2_araddr_s_o12;
+    output fabric_llpp2_araddr_s_o13;
+    output fabric_llpp2_araddr_s_o14;
+    output fabric_llpp2_araddr_s_o15;
+    output fabric_llpp2_araddr_s_o16;
+    output fabric_llpp2_araddr_s_o17;
+    output fabric_llpp2_araddr_s_o18;
+    output fabric_llpp2_araddr_s_o19;
+    output fabric_llpp2_araddr_s_o2;
+    output fabric_llpp2_araddr_s_o20;
+    output fabric_llpp2_araddr_s_o21;
+    output fabric_llpp2_araddr_s_o22;
+    output fabric_llpp2_araddr_s_o23;
+    output fabric_llpp2_araddr_s_o24;
+    output fabric_llpp2_araddr_s_o25;
+    output fabric_llpp2_araddr_s_o26;
+    output fabric_llpp2_araddr_s_o27;
+    output fabric_llpp2_araddr_s_o28;
+    output fabric_llpp2_araddr_s_o29;
+    output fabric_llpp2_araddr_s_o3;
+    output fabric_llpp2_araddr_s_o30;
+    output fabric_llpp2_araddr_s_o31;
+    output fabric_llpp2_araddr_s_o32;
+    output fabric_llpp2_araddr_s_o4;
+    output fabric_llpp2_araddr_s_o5;
+    output fabric_llpp2_araddr_s_o6;
+    output fabric_llpp2_araddr_s_o7;
+    output fabric_llpp2_araddr_s_o8;
+    output fabric_llpp2_araddr_s_o9;
+    output fabric_llpp2_arburst_s_o1;
+    output fabric_llpp2_arburst_s_o2;
+    output fabric_llpp2_arcache_s_o1;
+    output fabric_llpp2_arcache_s_o2;
+    output fabric_llpp2_arcache_s_o3;
+    output fabric_llpp2_arcache_s_o4;
+    output fabric_llpp2_arid_s_o1;
+    output fabric_llpp2_arid_s_o10;
+    output fabric_llpp2_arid_s_o11;
+    output fabric_llpp2_arid_s_o12;
+    output fabric_llpp2_arid_s_o2;
+    output fabric_llpp2_arid_s_o3;
+    output fabric_llpp2_arid_s_o4;
+    output fabric_llpp2_arid_s_o5;
+    output fabric_llpp2_arid_s_o6;
+    output fabric_llpp2_arid_s_o7;
+    output fabric_llpp2_arid_s_o8;
+    output fabric_llpp2_arid_s_o9;
+    output fabric_llpp2_arlen_s_o1;
+    output fabric_llpp2_arlen_s_o2;
+    output fabric_llpp2_arlen_s_o3;
+    output fabric_llpp2_arlen_s_o4;
+    output fabric_llpp2_arlen_s_o5;
+    output fabric_llpp2_arlen_s_o6;
+    output fabric_llpp2_arlen_s_o7;
+    output fabric_llpp2_arlen_s_o8;
+    output fabric_llpp2_arlock_s_o;
+    output fabric_llpp2_arprot_s_o1;
+    output fabric_llpp2_arprot_s_o2;
+    output fabric_llpp2_arprot_s_o3;
+    output fabric_llpp2_arqos_s_o1;
+    output fabric_llpp2_arqos_s_o2;
+    output fabric_llpp2_arqos_s_o3;
+    output fabric_llpp2_arqos_s_o4;
+    input fabric_llpp2_arready_s_i;
+    output fabric_llpp2_arsize_s_o1;
+    output fabric_llpp2_arsize_s_o2;
+    output fabric_llpp2_arsize_s_o3;
+    output fabric_llpp2_arvalid_s_o;
+    output fabric_llpp2_awaddr_s_o1;
+    output fabric_llpp2_awaddr_s_o10;
+    output fabric_llpp2_awaddr_s_o11;
+    output fabric_llpp2_awaddr_s_o12;
+    output fabric_llpp2_awaddr_s_o13;
+    output fabric_llpp2_awaddr_s_o14;
+    output fabric_llpp2_awaddr_s_o15;
+    output fabric_llpp2_awaddr_s_o16;
+    output fabric_llpp2_awaddr_s_o17;
+    output fabric_llpp2_awaddr_s_o18;
+    output fabric_llpp2_awaddr_s_o19;
+    output fabric_llpp2_awaddr_s_o2;
+    output fabric_llpp2_awaddr_s_o20;
+    output fabric_llpp2_awaddr_s_o21;
+    output fabric_llpp2_awaddr_s_o22;
+    output fabric_llpp2_awaddr_s_o23;
+    output fabric_llpp2_awaddr_s_o24;
+    output fabric_llpp2_awaddr_s_o25;
+    output fabric_llpp2_awaddr_s_o26;
+    output fabric_llpp2_awaddr_s_o27;
+    output fabric_llpp2_awaddr_s_o28;
+    output fabric_llpp2_awaddr_s_o29;
+    output fabric_llpp2_awaddr_s_o3;
+    output fabric_llpp2_awaddr_s_o30;
+    output fabric_llpp2_awaddr_s_o31;
+    output fabric_llpp2_awaddr_s_o32;
+    output fabric_llpp2_awaddr_s_o4;
+    output fabric_llpp2_awaddr_s_o5;
+    output fabric_llpp2_awaddr_s_o6;
+    output fabric_llpp2_awaddr_s_o7;
+    output fabric_llpp2_awaddr_s_o8;
+    output fabric_llpp2_awaddr_s_o9;
+    output fabric_llpp2_awburst_s_o1;
+    output fabric_llpp2_awburst_s_o2;
+    output fabric_llpp2_awcache_s_o1;
+    output fabric_llpp2_awcache_s_o2;
+    output fabric_llpp2_awcache_s_o3;
+    output fabric_llpp2_awcache_s_o4;
+    output fabric_llpp2_awid_s_o1;
+    output fabric_llpp2_awid_s_o10;
+    output fabric_llpp2_awid_s_o11;
+    output fabric_llpp2_awid_s_o12;
+    output fabric_llpp2_awid_s_o2;
+    output fabric_llpp2_awid_s_o3;
+    output fabric_llpp2_awid_s_o4;
+    output fabric_llpp2_awid_s_o5;
+    output fabric_llpp2_awid_s_o6;
+    output fabric_llpp2_awid_s_o7;
+    output fabric_llpp2_awid_s_o8;
+    output fabric_llpp2_awid_s_o9;
+    output fabric_llpp2_awlen_s_o1;
+    output fabric_llpp2_awlen_s_o2;
+    output fabric_llpp2_awlen_s_o3;
+    output fabric_llpp2_awlen_s_o4;
+    output fabric_llpp2_awlen_s_o5;
+    output fabric_llpp2_awlen_s_o6;
+    output fabric_llpp2_awlen_s_o7;
+    output fabric_llpp2_awlen_s_o8;
+    output fabric_llpp2_awlock_s_o;
+    output fabric_llpp2_awprot_s_o1;
+    output fabric_llpp2_awprot_s_o2;
+    output fabric_llpp2_awprot_s_o3;
+    output fabric_llpp2_awqos_s_o1;
+    output fabric_llpp2_awqos_s_o2;
+    output fabric_llpp2_awqos_s_o3;
+    output fabric_llpp2_awqos_s_o4;
+    input fabric_llpp2_awready_s_i;
+    output fabric_llpp2_awsize_s_o1;
+    output fabric_llpp2_awsize_s_o2;
+    output fabric_llpp2_awsize_s_o3;
+    output fabric_llpp2_awvalid_s_o;
+    input fabric_llpp2_bid_s_i1;
+    input fabric_llpp2_bid_s_i10;
+    input fabric_llpp2_bid_s_i11;
+    input fabric_llpp2_bid_s_i12;
+    input fabric_llpp2_bid_s_i2;
+    input fabric_llpp2_bid_s_i3;
+    input fabric_llpp2_bid_s_i4;
+    input fabric_llpp2_bid_s_i5;
+    input fabric_llpp2_bid_s_i6;
+    input fabric_llpp2_bid_s_i7;
+    input fabric_llpp2_bid_s_i8;
+    input fabric_llpp2_bid_s_i9;
+    output fabric_llpp2_bready_s_o;
+    input fabric_llpp2_bresp_s_i1;
+    input fabric_llpp2_bresp_s_i2;
+    input fabric_llpp2_bvalid_s_i;
+    input fabric_llpp2_rdata_s_i1;
+    input fabric_llpp2_rdata_s_i10;
+    input fabric_llpp2_rdata_s_i11;
+    input fabric_llpp2_rdata_s_i12;
+    input fabric_llpp2_rdata_s_i13;
+    input fabric_llpp2_rdata_s_i14;
+    input fabric_llpp2_rdata_s_i15;
+    input fabric_llpp2_rdata_s_i16;
+    input fabric_llpp2_rdata_s_i17;
+    input fabric_llpp2_rdata_s_i18;
+    input fabric_llpp2_rdata_s_i19;
+    input fabric_llpp2_rdata_s_i2;
+    input fabric_llpp2_rdata_s_i20;
+    input fabric_llpp2_rdata_s_i21;
+    input fabric_llpp2_rdata_s_i22;
+    input fabric_llpp2_rdata_s_i23;
+    input fabric_llpp2_rdata_s_i24;
+    input fabric_llpp2_rdata_s_i25;
+    input fabric_llpp2_rdata_s_i26;
+    input fabric_llpp2_rdata_s_i27;
+    input fabric_llpp2_rdata_s_i28;
+    input fabric_llpp2_rdata_s_i29;
+    input fabric_llpp2_rdata_s_i3;
+    input fabric_llpp2_rdata_s_i30;
+    input fabric_llpp2_rdata_s_i31;
+    input fabric_llpp2_rdata_s_i32;
+    input fabric_llpp2_rdata_s_i4;
+    input fabric_llpp2_rdata_s_i5;
+    input fabric_llpp2_rdata_s_i6;
+    input fabric_llpp2_rdata_s_i7;
+    input fabric_llpp2_rdata_s_i8;
+    input fabric_llpp2_rdata_s_i9;
+    input fabric_llpp2_rid_s_i1;
+    input fabric_llpp2_rid_s_i10;
+    input fabric_llpp2_rid_s_i11;
+    input fabric_llpp2_rid_s_i12;
+    input fabric_llpp2_rid_s_i2;
+    input fabric_llpp2_rid_s_i3;
+    input fabric_llpp2_rid_s_i4;
+    input fabric_llpp2_rid_s_i5;
+    input fabric_llpp2_rid_s_i6;
+    input fabric_llpp2_rid_s_i7;
+    input fabric_llpp2_rid_s_i8;
+    input fabric_llpp2_rid_s_i9;
+    input fabric_llpp2_rlast_s_i;
+    output fabric_llpp2_rready_s_o;
+    input fabric_llpp2_rresp_s_i1;
+    input fabric_llpp2_rresp_s_i2;
+    input fabric_llpp2_rvalid_s_i;
+    output fabric_llpp2_wdata_s_o1;
+    output fabric_llpp2_wdata_s_o10;
+    output fabric_llpp2_wdata_s_o11;
+    output fabric_llpp2_wdata_s_o12;
+    output fabric_llpp2_wdata_s_o13;
+    output fabric_llpp2_wdata_s_o14;
+    output fabric_llpp2_wdata_s_o15;
+    output fabric_llpp2_wdata_s_o16;
+    output fabric_llpp2_wdata_s_o17;
+    output fabric_llpp2_wdata_s_o18;
+    output fabric_llpp2_wdata_s_o19;
+    output fabric_llpp2_wdata_s_o2;
+    output fabric_llpp2_wdata_s_o20;
+    output fabric_llpp2_wdata_s_o21;
+    output fabric_llpp2_wdata_s_o22;
+    output fabric_llpp2_wdata_s_o23;
+    output fabric_llpp2_wdata_s_o24;
+    output fabric_llpp2_wdata_s_o25;
+    output fabric_llpp2_wdata_s_o26;
+    output fabric_llpp2_wdata_s_o27;
+    output fabric_llpp2_wdata_s_o28;
+    output fabric_llpp2_wdata_s_o29;
+    output fabric_llpp2_wdata_s_o3;
+    output fabric_llpp2_wdata_s_o30;
+    output fabric_llpp2_wdata_s_o31;
+    output fabric_llpp2_wdata_s_o32;
+    output fabric_llpp2_wdata_s_o4;
+    output fabric_llpp2_wdata_s_o5;
+    output fabric_llpp2_wdata_s_o6;
+    output fabric_llpp2_wdata_s_o7;
+    output fabric_llpp2_wdata_s_o8;
+    output fabric_llpp2_wdata_s_o9;
+    output fabric_llpp2_wlast_s_o;
+    input fabric_llpp2_wready_s_i;
+    output fabric_llpp2_wstrb_s_o1;
+    output fabric_llpp2_wstrb_s_o2;
+    output fabric_llpp2_wstrb_s_o3;
+    output fabric_llpp2_wstrb_s_o4;
+    output fabric_llpp2_wvalid_s_o;
+    output fabric_llpp3_araddr_s_o1;
+    output fabric_llpp3_araddr_s_o10;
+    output fabric_llpp3_araddr_s_o11;
+    output fabric_llpp3_araddr_s_o12;
+    output fabric_llpp3_araddr_s_o13;
+    output fabric_llpp3_araddr_s_o14;
+    output fabric_llpp3_araddr_s_o15;
+    output fabric_llpp3_araddr_s_o16;
+    output fabric_llpp3_araddr_s_o17;
+    output fabric_llpp3_araddr_s_o18;
+    output fabric_llpp3_araddr_s_o19;
+    output fabric_llpp3_araddr_s_o2;
+    output fabric_llpp3_araddr_s_o20;
+    output fabric_llpp3_araddr_s_o21;
+    output fabric_llpp3_araddr_s_o22;
+    output fabric_llpp3_araddr_s_o23;
+    output fabric_llpp3_araddr_s_o24;
+    output fabric_llpp3_araddr_s_o25;
+    output fabric_llpp3_araddr_s_o26;
+    output fabric_llpp3_araddr_s_o27;
+    output fabric_llpp3_araddr_s_o28;
+    output fabric_llpp3_araddr_s_o29;
+    output fabric_llpp3_araddr_s_o3;
+    output fabric_llpp3_araddr_s_o30;
+    output fabric_llpp3_araddr_s_o31;
+    output fabric_llpp3_araddr_s_o32;
+    output fabric_llpp3_araddr_s_o4;
+    output fabric_llpp3_araddr_s_o5;
+    output fabric_llpp3_araddr_s_o6;
+    output fabric_llpp3_araddr_s_o7;
+    output fabric_llpp3_araddr_s_o8;
+    output fabric_llpp3_araddr_s_o9;
+    output fabric_llpp3_arburst_s_o1;
+    output fabric_llpp3_arburst_s_o2;
+    output fabric_llpp3_arcache_s_o1;
+    output fabric_llpp3_arcache_s_o2;
+    output fabric_llpp3_arcache_s_o3;
+    output fabric_llpp3_arcache_s_o4;
+    output fabric_llpp3_arid_s_o1;
+    output fabric_llpp3_arid_s_o10;
+    output fabric_llpp3_arid_s_o11;
+    output fabric_llpp3_arid_s_o12;
+    output fabric_llpp3_arid_s_o2;
+    output fabric_llpp3_arid_s_o3;
+    output fabric_llpp3_arid_s_o4;
+    output fabric_llpp3_arid_s_o5;
+    output fabric_llpp3_arid_s_o6;
+    output fabric_llpp3_arid_s_o7;
+    output fabric_llpp3_arid_s_o8;
+    output fabric_llpp3_arid_s_o9;
+    output fabric_llpp3_arlen_s_o1;
+    output fabric_llpp3_arlen_s_o2;
+    output fabric_llpp3_arlen_s_o3;
+    output fabric_llpp3_arlen_s_o4;
+    output fabric_llpp3_arlen_s_o5;
+    output fabric_llpp3_arlen_s_o6;
+    output fabric_llpp3_arlen_s_o7;
+    output fabric_llpp3_arlen_s_o8;
+    output fabric_llpp3_arlock_s_o;
+    output fabric_llpp3_arprot_s_o1;
+    output fabric_llpp3_arprot_s_o2;
+    output fabric_llpp3_arprot_s_o3;
+    output fabric_llpp3_arqos_s_o1;
+    output fabric_llpp3_arqos_s_o2;
+    output fabric_llpp3_arqos_s_o3;
+    output fabric_llpp3_arqos_s_o4;
+    input fabric_llpp3_arready_s_i;
+    output fabric_llpp3_arsize_s_o1;
+    output fabric_llpp3_arsize_s_o2;
+    output fabric_llpp3_arsize_s_o3;
+    output fabric_llpp3_arvalid_s_o;
+    output fabric_llpp3_awaddr_s_o1;
+    output fabric_llpp3_awaddr_s_o10;
+    output fabric_llpp3_awaddr_s_o11;
+    output fabric_llpp3_awaddr_s_o12;
+    output fabric_llpp3_awaddr_s_o13;
+    output fabric_llpp3_awaddr_s_o14;
+    output fabric_llpp3_awaddr_s_o15;
+    output fabric_llpp3_awaddr_s_o16;
+    output fabric_llpp3_awaddr_s_o17;
+    output fabric_llpp3_awaddr_s_o18;
+    output fabric_llpp3_awaddr_s_o19;
+    output fabric_llpp3_awaddr_s_o2;
+    output fabric_llpp3_awaddr_s_o20;
+    output fabric_llpp3_awaddr_s_o21;
+    output fabric_llpp3_awaddr_s_o22;
+    output fabric_llpp3_awaddr_s_o23;
+    output fabric_llpp3_awaddr_s_o24;
+    output fabric_llpp3_awaddr_s_o25;
+    output fabric_llpp3_awaddr_s_o26;
+    output fabric_llpp3_awaddr_s_o27;
+    output fabric_llpp3_awaddr_s_o28;
+    output fabric_llpp3_awaddr_s_o29;
+    output fabric_llpp3_awaddr_s_o3;
+    output fabric_llpp3_awaddr_s_o30;
+    output fabric_llpp3_awaddr_s_o31;
+    output fabric_llpp3_awaddr_s_o32;
+    output fabric_llpp3_awaddr_s_o4;
+    output fabric_llpp3_awaddr_s_o5;
+    output fabric_llpp3_awaddr_s_o6;
+    output fabric_llpp3_awaddr_s_o7;
+    output fabric_llpp3_awaddr_s_o8;
+    output fabric_llpp3_awaddr_s_o9;
+    output fabric_llpp3_awburst_s_o1;
+    output fabric_llpp3_awburst_s_o2;
+    output fabric_llpp3_awcache_s_o1;
+    output fabric_llpp3_awcache_s_o2;
+    output fabric_llpp3_awcache_s_o3;
+    output fabric_llpp3_awcache_s_o4;
+    output fabric_llpp3_awid_s_o1;
+    output fabric_llpp3_awid_s_o10;
+    output fabric_llpp3_awid_s_o11;
+    output fabric_llpp3_awid_s_o12;
+    output fabric_llpp3_awid_s_o2;
+    output fabric_llpp3_awid_s_o3;
+    output fabric_llpp3_awid_s_o4;
+    output fabric_llpp3_awid_s_o5;
+    output fabric_llpp3_awid_s_o6;
+    output fabric_llpp3_awid_s_o7;
+    output fabric_llpp3_awid_s_o8;
+    output fabric_llpp3_awid_s_o9;
+    output fabric_llpp3_awlen_s_o1;
+    output fabric_llpp3_awlen_s_o2;
+    output fabric_llpp3_awlen_s_o3;
+    output fabric_llpp3_awlen_s_o4;
+    output fabric_llpp3_awlen_s_o5;
+    output fabric_llpp3_awlen_s_o6;
+    output fabric_llpp3_awlen_s_o7;
+    output fabric_llpp3_awlen_s_o8;
+    output fabric_llpp3_awlock_s_o;
+    output fabric_llpp3_awprot_s_o1;
+    output fabric_llpp3_awprot_s_o2;
+    output fabric_llpp3_awprot_s_o3;
+    output fabric_llpp3_awqos_s_o1;
+    output fabric_llpp3_awqos_s_o2;
+    output fabric_llpp3_awqos_s_o3;
+    output fabric_llpp3_awqos_s_o4;
+    input fabric_llpp3_awready_s_i;
+    output fabric_llpp3_awsize_s_o1;
+    output fabric_llpp3_awsize_s_o2;
+    output fabric_llpp3_awsize_s_o3;
+    output fabric_llpp3_awvalid_s_o;
+    input fabric_llpp3_bid_s_i1;
+    input fabric_llpp3_bid_s_i10;
+    input fabric_llpp3_bid_s_i11;
+    input fabric_llpp3_bid_s_i12;
+    input fabric_llpp3_bid_s_i2;
+    input fabric_llpp3_bid_s_i3;
+    input fabric_llpp3_bid_s_i4;
+    input fabric_llpp3_bid_s_i5;
+    input fabric_llpp3_bid_s_i6;
+    input fabric_llpp3_bid_s_i7;
+    input fabric_llpp3_bid_s_i8;
+    input fabric_llpp3_bid_s_i9;
+    output fabric_llpp3_bready_s_o;
+    input fabric_llpp3_bresp_s_i1;
+    input fabric_llpp3_bresp_s_i2;
+    input fabric_llpp3_bvalid_s_i;
+    input fabric_llpp3_rdata_s_i1;
+    input fabric_llpp3_rdata_s_i10;
+    input fabric_llpp3_rdata_s_i11;
+    input fabric_llpp3_rdata_s_i12;
+    input fabric_llpp3_rdata_s_i13;
+    input fabric_llpp3_rdata_s_i14;
+    input fabric_llpp3_rdata_s_i15;
+    input fabric_llpp3_rdata_s_i16;
+    input fabric_llpp3_rdata_s_i17;
+    input fabric_llpp3_rdata_s_i18;
+    input fabric_llpp3_rdata_s_i19;
+    input fabric_llpp3_rdata_s_i2;
+    input fabric_llpp3_rdata_s_i20;
+    input fabric_llpp3_rdata_s_i21;
+    input fabric_llpp3_rdata_s_i22;
+    input fabric_llpp3_rdata_s_i23;
+    input fabric_llpp3_rdata_s_i24;
+    input fabric_llpp3_rdata_s_i25;
+    input fabric_llpp3_rdata_s_i26;
+    input fabric_llpp3_rdata_s_i27;
+    input fabric_llpp3_rdata_s_i28;
+    input fabric_llpp3_rdata_s_i29;
+    input fabric_llpp3_rdata_s_i3;
+    input fabric_llpp3_rdata_s_i30;
+    input fabric_llpp3_rdata_s_i31;
+    input fabric_llpp3_rdata_s_i32;
+    input fabric_llpp3_rdata_s_i4;
+    input fabric_llpp3_rdata_s_i5;
+    input fabric_llpp3_rdata_s_i6;
+    input fabric_llpp3_rdata_s_i7;
+    input fabric_llpp3_rdata_s_i8;
+    input fabric_llpp3_rdata_s_i9;
+    input fabric_llpp3_rid_s_i1;
+    input fabric_llpp3_rid_s_i10;
+    input fabric_llpp3_rid_s_i11;
+    input fabric_llpp3_rid_s_i12;
+    input fabric_llpp3_rid_s_i2;
+    input fabric_llpp3_rid_s_i3;
+    input fabric_llpp3_rid_s_i4;
+    input fabric_llpp3_rid_s_i5;
+    input fabric_llpp3_rid_s_i6;
+    input fabric_llpp3_rid_s_i7;
+    input fabric_llpp3_rid_s_i8;
+    input fabric_llpp3_rid_s_i9;
+    input fabric_llpp3_rlast_s_i;
+    output fabric_llpp3_rready_s_o;
+    input fabric_llpp3_rresp_s_i1;
+    input fabric_llpp3_rresp_s_i2;
+    input fabric_llpp3_rvalid_s_i;
+    output fabric_llpp3_wdata_s_o1;
+    output fabric_llpp3_wdata_s_o10;
+    output fabric_llpp3_wdata_s_o11;
+    output fabric_llpp3_wdata_s_o12;
+    output fabric_llpp3_wdata_s_o13;
+    output fabric_llpp3_wdata_s_o14;
+    output fabric_llpp3_wdata_s_o15;
+    output fabric_llpp3_wdata_s_o16;
+    output fabric_llpp3_wdata_s_o17;
+    output fabric_llpp3_wdata_s_o18;
+    output fabric_llpp3_wdata_s_o19;
+    output fabric_llpp3_wdata_s_o2;
+    output fabric_llpp3_wdata_s_o20;
+    output fabric_llpp3_wdata_s_o21;
+    output fabric_llpp3_wdata_s_o22;
+    output fabric_llpp3_wdata_s_o23;
+    output fabric_llpp3_wdata_s_o24;
+    output fabric_llpp3_wdata_s_o25;
+    output fabric_llpp3_wdata_s_o26;
+    output fabric_llpp3_wdata_s_o27;
+    output fabric_llpp3_wdata_s_o28;
+    output fabric_llpp3_wdata_s_o29;
+    output fabric_llpp3_wdata_s_o3;
+    output fabric_llpp3_wdata_s_o30;
+    output fabric_llpp3_wdata_s_o31;
+    output fabric_llpp3_wdata_s_o32;
+    output fabric_llpp3_wdata_s_o4;
+    output fabric_llpp3_wdata_s_o5;
+    output fabric_llpp3_wdata_s_o6;
+    output fabric_llpp3_wdata_s_o7;
+    output fabric_llpp3_wdata_s_o8;
+    output fabric_llpp3_wdata_s_o9;
+    output fabric_llpp3_wlast_s_o;
+    input fabric_llpp3_wready_s_i;
+    output fabric_llpp3_wstrb_s_o1;
+    output fabric_llpp3_wstrb_s_o2;
+    output fabric_llpp3_wstrb_s_o3;
+    output fabric_llpp3_wstrb_s_o4;
+    output fabric_llpp3_wvalid_s_o;
+    input fabric_lowskew_i1;
+    input fabric_lowskew_i10;
+    input fabric_lowskew_i2;
+    input fabric_lowskew_i3;
+    input fabric_lowskew_i4;
+    input fabric_lowskew_i5;
+    input fabric_lowskew_i6;
+    input fabric_lowskew_i7;
+    input fabric_lowskew_i8;
+    input fabric_lowskew_i9;
+    output fabric_lowskew_o1;
+    output fabric_lowskew_o2;
+    input fabric_qos_pclk_i;
+    input fabric_qos_ppaddr_i1;
+    input fabric_qos_ppaddr_i10;
+    input fabric_qos_ppaddr_i11;
+    input fabric_qos_ppaddr_i12;
+    input fabric_qos_ppaddr_i13;
+    input fabric_qos_ppaddr_i14;
+    input fabric_qos_ppaddr_i15;
+    input fabric_qos_ppaddr_i16;
+    input fabric_qos_ppaddr_i17;
+    input fabric_qos_ppaddr_i18;
+    input fabric_qos_ppaddr_i19;
+    input fabric_qos_ppaddr_i2;
+    input fabric_qos_ppaddr_i20;
+    input fabric_qos_ppaddr_i21;
+    input fabric_qos_ppaddr_i22;
+    input fabric_qos_ppaddr_i23;
+    input fabric_qos_ppaddr_i24;
+    input fabric_qos_ppaddr_i25;
+    input fabric_qos_ppaddr_i26;
+    input fabric_qos_ppaddr_i27;
+    input fabric_qos_ppaddr_i28;
+    input fabric_qos_ppaddr_i29;
+    input fabric_qos_ppaddr_i3;
+    input fabric_qos_ppaddr_i30;
+    input fabric_qos_ppaddr_i31;
+    input fabric_qos_ppaddr_i32;
+    input fabric_qos_ppaddr_i4;
+    input fabric_qos_ppaddr_i5;
+    input fabric_qos_ppaddr_i6;
+    input fabric_qos_ppaddr_i7;
+    input fabric_qos_ppaddr_i8;
+    input fabric_qos_ppaddr_i9;
+    input fabric_qos_ppenable_i;
+    output fabric_qos_pprdata_o1;
+    output fabric_qos_pprdata_o10;
+    output fabric_qos_pprdata_o11;
+    output fabric_qos_pprdata_o12;
+    output fabric_qos_pprdata_o13;
+    output fabric_qos_pprdata_o14;
+    output fabric_qos_pprdata_o15;
+    output fabric_qos_pprdata_o16;
+    output fabric_qos_pprdata_o17;
+    output fabric_qos_pprdata_o18;
+    output fabric_qos_pprdata_o19;
+    output fabric_qos_pprdata_o2;
+    output fabric_qos_pprdata_o20;
+    output fabric_qos_pprdata_o21;
+    output fabric_qos_pprdata_o22;
+    output fabric_qos_pprdata_o23;
+    output fabric_qos_pprdata_o24;
+    output fabric_qos_pprdata_o25;
+    output fabric_qos_pprdata_o26;
+    output fabric_qos_pprdata_o27;
+    output fabric_qos_pprdata_o28;
+    output fabric_qos_pprdata_o29;
+    output fabric_qos_pprdata_o3;
+    output fabric_qos_pprdata_o30;
+    output fabric_qos_pprdata_o31;
+    output fabric_qos_pprdata_o32;
+    output fabric_qos_pprdata_o4;
+    output fabric_qos_pprdata_o5;
+    output fabric_qos_pprdata_o6;
+    output fabric_qos_pprdata_o7;
+    output fabric_qos_pprdata_o8;
+    output fabric_qos_pprdata_o9;
+    output fabric_qos_ppready_o;
+    output fabric_qos_ppslverr_o;
+    input fabric_qos_ppwdata_i1;
+    input fabric_qos_ppwdata_i10;
+    input fabric_qos_ppwdata_i11;
+    input fabric_qos_ppwdata_i12;
+    input fabric_qos_ppwdata_i13;
+    input fabric_qos_ppwdata_i14;
+    input fabric_qos_ppwdata_i15;
+    input fabric_qos_ppwdata_i16;
+    input fabric_qos_ppwdata_i17;
+    input fabric_qos_ppwdata_i18;
+    input fabric_qos_ppwdata_i19;
+    input fabric_qos_ppwdata_i2;
+    input fabric_qos_ppwdata_i20;
+    input fabric_qos_ppwdata_i21;
+    input fabric_qos_ppwdata_i22;
+    input fabric_qos_ppwdata_i23;
+    input fabric_qos_ppwdata_i24;
+    input fabric_qos_ppwdata_i25;
+    input fabric_qos_ppwdata_i26;
+    input fabric_qos_ppwdata_i27;
+    input fabric_qos_ppwdata_i28;
+    input fabric_qos_ppwdata_i29;
+    input fabric_qos_ppwdata_i3;
+    input fabric_qos_ppwdata_i30;
+    input fabric_qos_ppwdata_i31;
+    input fabric_qos_ppwdata_i32;
+    input fabric_qos_ppwdata_i4;
+    input fabric_qos_ppwdata_i5;
+    input fabric_qos_ppwdata_i6;
+    input fabric_qos_ppwdata_i7;
+    input fabric_qos_ppwdata_i8;
+    input fabric_qos_ppwdata_i9;
+    input fabric_qos_ppwrite_i;
+    input fabric_qos_presetn_i;
+    input fabric_qos_psel_i;
+    output fabric_soc_mon_sensor_alarm_o;
+    input fabric_sysc_hold_on_debug_i;
+    output fabric_tnd_fpga_apb_master_paddr_o1;
+    output fabric_tnd_fpga_apb_master_paddr_o10;
+    output fabric_tnd_fpga_apb_master_paddr_o11;
+    output fabric_tnd_fpga_apb_master_paddr_o12;
+    output fabric_tnd_fpga_apb_master_paddr_o13;
+    output fabric_tnd_fpga_apb_master_paddr_o14;
+    output fabric_tnd_fpga_apb_master_paddr_o15;
+    output fabric_tnd_fpga_apb_master_paddr_o16;
+    output fabric_tnd_fpga_apb_master_paddr_o17;
+    output fabric_tnd_fpga_apb_master_paddr_o18;
+    output fabric_tnd_fpga_apb_master_paddr_o19;
+    output fabric_tnd_fpga_apb_master_paddr_o2;
+    output fabric_tnd_fpga_apb_master_paddr_o20;
+    output fabric_tnd_fpga_apb_master_paddr_o21;
+    output fabric_tnd_fpga_apb_master_paddr_o22;
+    output fabric_tnd_fpga_apb_master_paddr_o23;
+    output fabric_tnd_fpga_apb_master_paddr_o24;
+    output fabric_tnd_fpga_apb_master_paddr_o25;
+    output fabric_tnd_fpga_apb_master_paddr_o26;
+    output fabric_tnd_fpga_apb_master_paddr_o27;
+    output fabric_tnd_fpga_apb_master_paddr_o28;
+    output fabric_tnd_fpga_apb_master_paddr_o29;
+    output fabric_tnd_fpga_apb_master_paddr_o3;
+    output fabric_tnd_fpga_apb_master_paddr_o30;
+    output fabric_tnd_fpga_apb_master_paddr_o31;
+    output fabric_tnd_fpga_apb_master_paddr_o32;
+    output fabric_tnd_fpga_apb_master_paddr_o4;
+    output fabric_tnd_fpga_apb_master_paddr_o5;
+    output fabric_tnd_fpga_apb_master_paddr_o6;
+    output fabric_tnd_fpga_apb_master_paddr_o7;
+    output fabric_tnd_fpga_apb_master_paddr_o8;
+    output fabric_tnd_fpga_apb_master_paddr_o9;
+    output fabric_tnd_fpga_apb_master_penable_o;
+    input fabric_tnd_fpga_apb_master_prdata_i1;
+    input fabric_tnd_fpga_apb_master_prdata_i10;
+    input fabric_tnd_fpga_apb_master_prdata_i11;
+    input fabric_tnd_fpga_apb_master_prdata_i12;
+    input fabric_tnd_fpga_apb_master_prdata_i13;
+    input fabric_tnd_fpga_apb_master_prdata_i14;
+    input fabric_tnd_fpga_apb_master_prdata_i15;
+    input fabric_tnd_fpga_apb_master_prdata_i16;
+    input fabric_tnd_fpga_apb_master_prdata_i17;
+    input fabric_tnd_fpga_apb_master_prdata_i18;
+    input fabric_tnd_fpga_apb_master_prdata_i19;
+    input fabric_tnd_fpga_apb_master_prdata_i2;
+    input fabric_tnd_fpga_apb_master_prdata_i20;
+    input fabric_tnd_fpga_apb_master_prdata_i21;
+    input fabric_tnd_fpga_apb_master_prdata_i22;
+    input fabric_tnd_fpga_apb_master_prdata_i23;
+    input fabric_tnd_fpga_apb_master_prdata_i24;
+    input fabric_tnd_fpga_apb_master_prdata_i25;
+    input fabric_tnd_fpga_apb_master_prdata_i26;
+    input fabric_tnd_fpga_apb_master_prdata_i27;
+    input fabric_tnd_fpga_apb_master_prdata_i28;
+    input fabric_tnd_fpga_apb_master_prdata_i29;
+    input fabric_tnd_fpga_apb_master_prdata_i3;
+    input fabric_tnd_fpga_apb_master_prdata_i30;
+    input fabric_tnd_fpga_apb_master_prdata_i31;
+    input fabric_tnd_fpga_apb_master_prdata_i32;
+    input fabric_tnd_fpga_apb_master_prdata_i4;
+    input fabric_tnd_fpga_apb_master_prdata_i5;
+    input fabric_tnd_fpga_apb_master_prdata_i6;
+    input fabric_tnd_fpga_apb_master_prdata_i7;
+    input fabric_tnd_fpga_apb_master_prdata_i8;
+    input fabric_tnd_fpga_apb_master_prdata_i9;
+    input fabric_tnd_fpga_apb_master_pready_i;
+    output fabric_tnd_fpga_apb_master_psel_o;
+    input fabric_tnd_fpga_apb_master_pslverr_i;
+    output fabric_tnd_fpga_apb_master_pwdata_o1;
+    output fabric_tnd_fpga_apb_master_pwdata_o10;
+    output fabric_tnd_fpga_apb_master_pwdata_o11;
+    output fabric_tnd_fpga_apb_master_pwdata_o12;
+    output fabric_tnd_fpga_apb_master_pwdata_o13;
+    output fabric_tnd_fpga_apb_master_pwdata_o14;
+    output fabric_tnd_fpga_apb_master_pwdata_o15;
+    output fabric_tnd_fpga_apb_master_pwdata_o16;
+    output fabric_tnd_fpga_apb_master_pwdata_o17;
+    output fabric_tnd_fpga_apb_master_pwdata_o18;
+    output fabric_tnd_fpga_apb_master_pwdata_o19;
+    output fabric_tnd_fpga_apb_master_pwdata_o2;
+    output fabric_tnd_fpga_apb_master_pwdata_o20;
+    output fabric_tnd_fpga_apb_master_pwdata_o21;
+    output fabric_tnd_fpga_apb_master_pwdata_o22;
+    output fabric_tnd_fpga_apb_master_pwdata_o23;
+    output fabric_tnd_fpga_apb_master_pwdata_o24;
+    output fabric_tnd_fpga_apb_master_pwdata_o25;
+    output fabric_tnd_fpga_apb_master_pwdata_o26;
+    output fabric_tnd_fpga_apb_master_pwdata_o27;
+    output fabric_tnd_fpga_apb_master_pwdata_o28;
+    output fabric_tnd_fpga_apb_master_pwdata_o29;
+    output fabric_tnd_fpga_apb_master_pwdata_o3;
+    output fabric_tnd_fpga_apb_master_pwdata_o30;
+    output fabric_tnd_fpga_apb_master_pwdata_o31;
+    output fabric_tnd_fpga_apb_master_pwdata_o32;
+    output fabric_tnd_fpga_apb_master_pwdata_o4;
+    output fabric_tnd_fpga_apb_master_pwdata_o5;
+    output fabric_tnd_fpga_apb_master_pwdata_o6;
+    output fabric_tnd_fpga_apb_master_pwdata_o7;
+    output fabric_tnd_fpga_apb_master_pwdata_o8;
+    output fabric_tnd_fpga_apb_master_pwdata_o9;
+    output fabric_tnd_fpga_apb_master_pwrite_o;
+    input fabric_tnd_fpga_atb_master_afready_i;
+    output fabric_tnd_fpga_atb_master_afvalid_o;
+    input fabric_tnd_fpga_atb_master_atbytes_i1;
+    input fabric_tnd_fpga_atb_master_atbytes_i2;
+    input fabric_tnd_fpga_atb_master_atbytes_i3;
+    input fabric_tnd_fpga_atb_master_atbytes_i4;
+    input fabric_tnd_fpga_atb_master_atdata_i1;
+    input fabric_tnd_fpga_atb_master_atdata_i10;
+    input fabric_tnd_fpga_atb_master_atdata_i100;
+    input fabric_tnd_fpga_atb_master_atdata_i101;
+    input fabric_tnd_fpga_atb_master_atdata_i102;
+    input fabric_tnd_fpga_atb_master_atdata_i103;
+    input fabric_tnd_fpga_atb_master_atdata_i104;
+    input fabric_tnd_fpga_atb_master_atdata_i105;
+    input fabric_tnd_fpga_atb_master_atdata_i106;
+    input fabric_tnd_fpga_atb_master_atdata_i107;
+    input fabric_tnd_fpga_atb_master_atdata_i108;
+    input fabric_tnd_fpga_atb_master_atdata_i109;
+    input fabric_tnd_fpga_atb_master_atdata_i11;
+    input fabric_tnd_fpga_atb_master_atdata_i110;
+    input fabric_tnd_fpga_atb_master_atdata_i111;
+    input fabric_tnd_fpga_atb_master_atdata_i112;
+    input fabric_tnd_fpga_atb_master_atdata_i113;
+    input fabric_tnd_fpga_atb_master_atdata_i114;
+    input fabric_tnd_fpga_atb_master_atdata_i115;
+    input fabric_tnd_fpga_atb_master_atdata_i116;
+    input fabric_tnd_fpga_atb_master_atdata_i117;
+    input fabric_tnd_fpga_atb_master_atdata_i118;
+    input fabric_tnd_fpga_atb_master_atdata_i119;
+    input fabric_tnd_fpga_atb_master_atdata_i12;
+    input fabric_tnd_fpga_atb_master_atdata_i120;
+    input fabric_tnd_fpga_atb_master_atdata_i121;
+    input fabric_tnd_fpga_atb_master_atdata_i122;
+    input fabric_tnd_fpga_atb_master_atdata_i123;
+    input fabric_tnd_fpga_atb_master_atdata_i124;
+    input fabric_tnd_fpga_atb_master_atdata_i125;
+    input fabric_tnd_fpga_atb_master_atdata_i126;
+    input fabric_tnd_fpga_atb_master_atdata_i127;
+    input fabric_tnd_fpga_atb_master_atdata_i128;
+    input fabric_tnd_fpga_atb_master_atdata_i13;
+    input fabric_tnd_fpga_atb_master_atdata_i14;
+    input fabric_tnd_fpga_atb_master_atdata_i15;
+    input fabric_tnd_fpga_atb_master_atdata_i16;
+    input fabric_tnd_fpga_atb_master_atdata_i17;
+    input fabric_tnd_fpga_atb_master_atdata_i18;
+    input fabric_tnd_fpga_atb_master_atdata_i19;
+    input fabric_tnd_fpga_atb_master_atdata_i2;
+    input fabric_tnd_fpga_atb_master_atdata_i20;
+    input fabric_tnd_fpga_atb_master_atdata_i21;
+    input fabric_tnd_fpga_atb_master_atdata_i22;
+    input fabric_tnd_fpga_atb_master_atdata_i23;
+    input fabric_tnd_fpga_atb_master_atdata_i24;
+    input fabric_tnd_fpga_atb_master_atdata_i25;
+    input fabric_tnd_fpga_atb_master_atdata_i26;
+    input fabric_tnd_fpga_atb_master_atdata_i27;
+    input fabric_tnd_fpga_atb_master_atdata_i28;
+    input fabric_tnd_fpga_atb_master_atdata_i29;
+    input fabric_tnd_fpga_atb_master_atdata_i3;
+    input fabric_tnd_fpga_atb_master_atdata_i30;
+    input fabric_tnd_fpga_atb_master_atdata_i31;
+    input fabric_tnd_fpga_atb_master_atdata_i32;
+    input fabric_tnd_fpga_atb_master_atdata_i33;
+    input fabric_tnd_fpga_atb_master_atdata_i34;
+    input fabric_tnd_fpga_atb_master_atdata_i35;
+    input fabric_tnd_fpga_atb_master_atdata_i36;
+    input fabric_tnd_fpga_atb_master_atdata_i37;
+    input fabric_tnd_fpga_atb_master_atdata_i38;
+    input fabric_tnd_fpga_atb_master_atdata_i39;
+    input fabric_tnd_fpga_atb_master_atdata_i4;
+    input fabric_tnd_fpga_atb_master_atdata_i40;
+    input fabric_tnd_fpga_atb_master_atdata_i41;
+    input fabric_tnd_fpga_atb_master_atdata_i42;
+    input fabric_tnd_fpga_atb_master_atdata_i43;
+    input fabric_tnd_fpga_atb_master_atdata_i44;
+    input fabric_tnd_fpga_atb_master_atdata_i45;
+    input fabric_tnd_fpga_atb_master_atdata_i46;
+    input fabric_tnd_fpga_atb_master_atdata_i47;
+    input fabric_tnd_fpga_atb_master_atdata_i48;
+    input fabric_tnd_fpga_atb_master_atdata_i49;
+    input fabric_tnd_fpga_atb_master_atdata_i5;
+    input fabric_tnd_fpga_atb_master_atdata_i50;
+    input fabric_tnd_fpga_atb_master_atdata_i51;
+    input fabric_tnd_fpga_atb_master_atdata_i52;
+    input fabric_tnd_fpga_atb_master_atdata_i53;
+    input fabric_tnd_fpga_atb_master_atdata_i54;
+    input fabric_tnd_fpga_atb_master_atdata_i55;
+    input fabric_tnd_fpga_atb_master_atdata_i56;
+    input fabric_tnd_fpga_atb_master_atdata_i57;
+    input fabric_tnd_fpga_atb_master_atdata_i58;
+    input fabric_tnd_fpga_atb_master_atdata_i59;
+    input fabric_tnd_fpga_atb_master_atdata_i6;
+    input fabric_tnd_fpga_atb_master_atdata_i60;
+    input fabric_tnd_fpga_atb_master_atdata_i61;
+    input fabric_tnd_fpga_atb_master_atdata_i62;
+    input fabric_tnd_fpga_atb_master_atdata_i63;
+    input fabric_tnd_fpga_atb_master_atdata_i64;
+    input fabric_tnd_fpga_atb_master_atdata_i65;
+    input fabric_tnd_fpga_atb_master_atdata_i66;
+    input fabric_tnd_fpga_atb_master_atdata_i67;
+    input fabric_tnd_fpga_atb_master_atdata_i68;
+    input fabric_tnd_fpga_atb_master_atdata_i69;
+    input fabric_tnd_fpga_atb_master_atdata_i7;
+    input fabric_tnd_fpga_atb_master_atdata_i70;
+    input fabric_tnd_fpga_atb_master_atdata_i71;
+    input fabric_tnd_fpga_atb_master_atdata_i72;
+    input fabric_tnd_fpga_atb_master_atdata_i73;
+    input fabric_tnd_fpga_atb_master_atdata_i74;
+    input fabric_tnd_fpga_atb_master_atdata_i75;
+    input fabric_tnd_fpga_atb_master_atdata_i76;
+    input fabric_tnd_fpga_atb_master_atdata_i77;
+    input fabric_tnd_fpga_atb_master_atdata_i78;
+    input fabric_tnd_fpga_atb_master_atdata_i79;
+    input fabric_tnd_fpga_atb_master_atdata_i8;
+    input fabric_tnd_fpga_atb_master_atdata_i80;
+    input fabric_tnd_fpga_atb_master_atdata_i81;
+    input fabric_tnd_fpga_atb_master_atdata_i82;
+    input fabric_tnd_fpga_atb_master_atdata_i83;
+    input fabric_tnd_fpga_atb_master_atdata_i84;
+    input fabric_tnd_fpga_atb_master_atdata_i85;
+    input fabric_tnd_fpga_atb_master_atdata_i86;
+    input fabric_tnd_fpga_atb_master_atdata_i87;
+    input fabric_tnd_fpga_atb_master_atdata_i88;
+    input fabric_tnd_fpga_atb_master_atdata_i89;
+    input fabric_tnd_fpga_atb_master_atdata_i9;
+    input fabric_tnd_fpga_atb_master_atdata_i90;
+    input fabric_tnd_fpga_atb_master_atdata_i91;
+    input fabric_tnd_fpga_atb_master_atdata_i92;
+    input fabric_tnd_fpga_atb_master_atdata_i93;
+    input fabric_tnd_fpga_atb_master_atdata_i94;
+    input fabric_tnd_fpga_atb_master_atdata_i95;
+    input fabric_tnd_fpga_atb_master_atdata_i96;
+    input fabric_tnd_fpga_atb_master_atdata_i97;
+    input fabric_tnd_fpga_atb_master_atdata_i98;
+    input fabric_tnd_fpga_atb_master_atdata_i99;
+    input fabric_tnd_fpga_atb_master_atid_i1;
+    input fabric_tnd_fpga_atb_master_atid_i2;
+    input fabric_tnd_fpga_atb_master_atid_i3;
+    input fabric_tnd_fpga_atb_master_atid_i4;
+    input fabric_tnd_fpga_atb_master_atid_i5;
+    input fabric_tnd_fpga_atb_master_atid_i6;
+    input fabric_tnd_fpga_atb_master_atid_i7;
+    output fabric_tnd_fpga_atb_master_atready_o;
+    input fabric_tnd_fpga_atb_master_atvalid_i;
+    output fabric_tnd_fpga_atb_master_syncreq_o;
+    output fabric_tnd_hssl_apb_master_paddr_o1;
+    output fabric_tnd_hssl_apb_master_paddr_o10;
+    output fabric_tnd_hssl_apb_master_paddr_o11;
+    output fabric_tnd_hssl_apb_master_paddr_o12;
+    output fabric_tnd_hssl_apb_master_paddr_o13;
+    output fabric_tnd_hssl_apb_master_paddr_o14;
+    output fabric_tnd_hssl_apb_master_paddr_o15;
+    output fabric_tnd_hssl_apb_master_paddr_o16;
+    output fabric_tnd_hssl_apb_master_paddr_o17;
+    output fabric_tnd_hssl_apb_master_paddr_o18;
+    output fabric_tnd_hssl_apb_master_paddr_o19;
+    output fabric_tnd_hssl_apb_master_paddr_o2;
+    output fabric_tnd_hssl_apb_master_paddr_o20;
+    output fabric_tnd_hssl_apb_master_paddr_o21;
+    output fabric_tnd_hssl_apb_master_paddr_o22;
+    output fabric_tnd_hssl_apb_master_paddr_o23;
+    output fabric_tnd_hssl_apb_master_paddr_o24;
+    output fabric_tnd_hssl_apb_master_paddr_o25;
+    output fabric_tnd_hssl_apb_master_paddr_o26;
+    output fabric_tnd_hssl_apb_master_paddr_o27;
+    output fabric_tnd_hssl_apb_master_paddr_o28;
+    output fabric_tnd_hssl_apb_master_paddr_o29;
+    output fabric_tnd_hssl_apb_master_paddr_o3;
+    output fabric_tnd_hssl_apb_master_paddr_o30;
+    output fabric_tnd_hssl_apb_master_paddr_o31;
+    output fabric_tnd_hssl_apb_master_paddr_o32;
+    output fabric_tnd_hssl_apb_master_paddr_o4;
+    output fabric_tnd_hssl_apb_master_paddr_o5;
+    output fabric_tnd_hssl_apb_master_paddr_o6;
+    output fabric_tnd_hssl_apb_master_paddr_o7;
+    output fabric_tnd_hssl_apb_master_paddr_o8;
+    output fabric_tnd_hssl_apb_master_paddr_o9;
+    output fabric_tnd_hssl_apb_master_penable_o;
+    input fabric_tnd_hssl_apb_master_prdata_i1;
+    input fabric_tnd_hssl_apb_master_prdata_i10;
+    input fabric_tnd_hssl_apb_master_prdata_i11;
+    input fabric_tnd_hssl_apb_master_prdata_i12;
+    input fabric_tnd_hssl_apb_master_prdata_i13;
+    input fabric_tnd_hssl_apb_master_prdata_i14;
+    input fabric_tnd_hssl_apb_master_prdata_i15;
+    input fabric_tnd_hssl_apb_master_prdata_i16;
+    input fabric_tnd_hssl_apb_master_prdata_i17;
+    input fabric_tnd_hssl_apb_master_prdata_i18;
+    input fabric_tnd_hssl_apb_master_prdata_i19;
+    input fabric_tnd_hssl_apb_master_prdata_i2;
+    input fabric_tnd_hssl_apb_master_prdata_i20;
+    input fabric_tnd_hssl_apb_master_prdata_i21;
+    input fabric_tnd_hssl_apb_master_prdata_i22;
+    input fabric_tnd_hssl_apb_master_prdata_i23;
+    input fabric_tnd_hssl_apb_master_prdata_i24;
+    input fabric_tnd_hssl_apb_master_prdata_i25;
+    input fabric_tnd_hssl_apb_master_prdata_i26;
+    input fabric_tnd_hssl_apb_master_prdata_i27;
+    input fabric_tnd_hssl_apb_master_prdata_i28;
+    input fabric_tnd_hssl_apb_master_prdata_i29;
+    input fabric_tnd_hssl_apb_master_prdata_i3;
+    input fabric_tnd_hssl_apb_master_prdata_i30;
+    input fabric_tnd_hssl_apb_master_prdata_i31;
+    input fabric_tnd_hssl_apb_master_prdata_i32;
+    input fabric_tnd_hssl_apb_master_prdata_i4;
+    input fabric_tnd_hssl_apb_master_prdata_i5;
+    input fabric_tnd_hssl_apb_master_prdata_i6;
+    input fabric_tnd_hssl_apb_master_prdata_i7;
+    input fabric_tnd_hssl_apb_master_prdata_i8;
+    input fabric_tnd_hssl_apb_master_prdata_i9;
+    input fabric_tnd_hssl_apb_master_pready_i;
+    output fabric_tnd_hssl_apb_master_psel_o;
+    input fabric_tnd_hssl_apb_master_pslverr_i;
+    output fabric_tnd_hssl_apb_master_pwdata_o1;
+    output fabric_tnd_hssl_apb_master_pwdata_o10;
+    output fabric_tnd_hssl_apb_master_pwdata_o11;
+    output fabric_tnd_hssl_apb_master_pwdata_o12;
+    output fabric_tnd_hssl_apb_master_pwdata_o13;
+    output fabric_tnd_hssl_apb_master_pwdata_o14;
+    output fabric_tnd_hssl_apb_master_pwdata_o15;
+    output fabric_tnd_hssl_apb_master_pwdata_o16;
+    output fabric_tnd_hssl_apb_master_pwdata_o17;
+    output fabric_tnd_hssl_apb_master_pwdata_o18;
+    output fabric_tnd_hssl_apb_master_pwdata_o19;
+    output fabric_tnd_hssl_apb_master_pwdata_o2;
+    output fabric_tnd_hssl_apb_master_pwdata_o20;
+    output fabric_tnd_hssl_apb_master_pwdata_o21;
+    output fabric_tnd_hssl_apb_master_pwdata_o22;
+    output fabric_tnd_hssl_apb_master_pwdata_o23;
+    output fabric_tnd_hssl_apb_master_pwdata_o24;
+    output fabric_tnd_hssl_apb_master_pwdata_o25;
+    output fabric_tnd_hssl_apb_master_pwdata_o26;
+    output fabric_tnd_hssl_apb_master_pwdata_o27;
+    output fabric_tnd_hssl_apb_master_pwdata_o28;
+    output fabric_tnd_hssl_apb_master_pwdata_o29;
+    output fabric_tnd_hssl_apb_master_pwdata_o3;
+    output fabric_tnd_hssl_apb_master_pwdata_o30;
+    output fabric_tnd_hssl_apb_master_pwdata_o31;
+    output fabric_tnd_hssl_apb_master_pwdata_o32;
+    output fabric_tnd_hssl_apb_master_pwdata_o4;
+    output fabric_tnd_hssl_apb_master_pwdata_o5;
+    output fabric_tnd_hssl_apb_master_pwdata_o6;
+    output fabric_tnd_hssl_apb_master_pwdata_o7;
+    output fabric_tnd_hssl_apb_master_pwdata_o8;
+    output fabric_tnd_hssl_apb_master_pwdata_o9;
+    output fabric_tnd_hssl_apb_master_pwrite_o;
+    output fabric_tnd_hssl_atb_master_afready_o;
+    input fabric_tnd_hssl_atb_master_afvalid_i;
+    output fabric_tnd_hssl_atb_master_atbytes_o1;
+    output fabric_tnd_hssl_atb_master_atbytes_o2;
+    output fabric_tnd_hssl_atb_master_atbytes_o3;
+    output fabric_tnd_hssl_atb_master_atbytes_o4;
+    output fabric_tnd_hssl_atb_master_atdata_o1;
+    output fabric_tnd_hssl_atb_master_atdata_o10;
+    output fabric_tnd_hssl_atb_master_atdata_o100;
+    output fabric_tnd_hssl_atb_master_atdata_o101;
+    output fabric_tnd_hssl_atb_master_atdata_o102;
+    output fabric_tnd_hssl_atb_master_atdata_o103;
+    output fabric_tnd_hssl_atb_master_atdata_o104;
+    output fabric_tnd_hssl_atb_master_atdata_o105;
+    output fabric_tnd_hssl_atb_master_atdata_o106;
+    output fabric_tnd_hssl_atb_master_atdata_o107;
+    output fabric_tnd_hssl_atb_master_atdata_o108;
+    output fabric_tnd_hssl_atb_master_atdata_o109;
+    output fabric_tnd_hssl_atb_master_atdata_o11;
+    output fabric_tnd_hssl_atb_master_atdata_o110;
+    output fabric_tnd_hssl_atb_master_atdata_o111;
+    output fabric_tnd_hssl_atb_master_atdata_o112;
+    output fabric_tnd_hssl_atb_master_atdata_o113;
+    output fabric_tnd_hssl_atb_master_atdata_o114;
+    output fabric_tnd_hssl_atb_master_atdata_o115;
+    output fabric_tnd_hssl_atb_master_atdata_o116;
+    output fabric_tnd_hssl_atb_master_atdata_o117;
+    output fabric_tnd_hssl_atb_master_atdata_o118;
+    output fabric_tnd_hssl_atb_master_atdata_o119;
+    output fabric_tnd_hssl_atb_master_atdata_o12;
+    output fabric_tnd_hssl_atb_master_atdata_o120;
+    output fabric_tnd_hssl_atb_master_atdata_o121;
+    output fabric_tnd_hssl_atb_master_atdata_o122;
+    output fabric_tnd_hssl_atb_master_atdata_o123;
+    output fabric_tnd_hssl_atb_master_atdata_o124;
+    output fabric_tnd_hssl_atb_master_atdata_o125;
+    output fabric_tnd_hssl_atb_master_atdata_o126;
+    output fabric_tnd_hssl_atb_master_atdata_o127;
+    output fabric_tnd_hssl_atb_master_atdata_o128;
+    output fabric_tnd_hssl_atb_master_atdata_o13;
+    output fabric_tnd_hssl_atb_master_atdata_o14;
+    output fabric_tnd_hssl_atb_master_atdata_o15;
+    output fabric_tnd_hssl_atb_master_atdata_o16;
+    output fabric_tnd_hssl_atb_master_atdata_o17;
+    output fabric_tnd_hssl_atb_master_atdata_o18;
+    output fabric_tnd_hssl_atb_master_atdata_o19;
+    output fabric_tnd_hssl_atb_master_atdata_o2;
+    output fabric_tnd_hssl_atb_master_atdata_o20;
+    output fabric_tnd_hssl_atb_master_atdata_o21;
+    output fabric_tnd_hssl_atb_master_atdata_o22;
+    output fabric_tnd_hssl_atb_master_atdata_o23;
+    output fabric_tnd_hssl_atb_master_atdata_o24;
+    output fabric_tnd_hssl_atb_master_atdata_o25;
+    output fabric_tnd_hssl_atb_master_atdata_o26;
+    output fabric_tnd_hssl_atb_master_atdata_o27;
+    output fabric_tnd_hssl_atb_master_atdata_o28;
+    output fabric_tnd_hssl_atb_master_atdata_o29;
+    output fabric_tnd_hssl_atb_master_atdata_o3;
+    output fabric_tnd_hssl_atb_master_atdata_o30;
+    output fabric_tnd_hssl_atb_master_atdata_o31;
+    output fabric_tnd_hssl_atb_master_atdata_o32;
+    output fabric_tnd_hssl_atb_master_atdata_o33;
+    output fabric_tnd_hssl_atb_master_atdata_o34;
+    output fabric_tnd_hssl_atb_master_atdata_o35;
+    output fabric_tnd_hssl_atb_master_atdata_o36;
+    output fabric_tnd_hssl_atb_master_atdata_o37;
+    output fabric_tnd_hssl_atb_master_atdata_o38;
+    output fabric_tnd_hssl_atb_master_atdata_o39;
+    output fabric_tnd_hssl_atb_master_atdata_o4;
+    output fabric_tnd_hssl_atb_master_atdata_o40;
+    output fabric_tnd_hssl_atb_master_atdata_o41;
+    output fabric_tnd_hssl_atb_master_atdata_o42;
+    output fabric_tnd_hssl_atb_master_atdata_o43;
+    output fabric_tnd_hssl_atb_master_atdata_o44;
+    output fabric_tnd_hssl_atb_master_atdata_o45;
+    output fabric_tnd_hssl_atb_master_atdata_o46;
+    output fabric_tnd_hssl_atb_master_atdata_o47;
+    output fabric_tnd_hssl_atb_master_atdata_o48;
+    output fabric_tnd_hssl_atb_master_atdata_o49;
+    output fabric_tnd_hssl_atb_master_atdata_o5;
+    output fabric_tnd_hssl_atb_master_atdata_o50;
+    output fabric_tnd_hssl_atb_master_atdata_o51;
+    output fabric_tnd_hssl_atb_master_atdata_o52;
+    output fabric_tnd_hssl_atb_master_atdata_o53;
+    output fabric_tnd_hssl_atb_master_atdata_o54;
+    output fabric_tnd_hssl_atb_master_atdata_o55;
+    output fabric_tnd_hssl_atb_master_atdata_o56;
+    output fabric_tnd_hssl_atb_master_atdata_o57;
+    output fabric_tnd_hssl_atb_master_atdata_o58;
+    output fabric_tnd_hssl_atb_master_atdata_o59;
+    output fabric_tnd_hssl_atb_master_atdata_o6;
+    output fabric_tnd_hssl_atb_master_atdata_o60;
+    output fabric_tnd_hssl_atb_master_atdata_o61;
+    output fabric_tnd_hssl_atb_master_atdata_o62;
+    output fabric_tnd_hssl_atb_master_atdata_o63;
+    output fabric_tnd_hssl_atb_master_atdata_o64;
+    output fabric_tnd_hssl_atb_master_atdata_o65;
+    output fabric_tnd_hssl_atb_master_atdata_o66;
+    output fabric_tnd_hssl_atb_master_atdata_o67;
+    output fabric_tnd_hssl_atb_master_atdata_o68;
+    output fabric_tnd_hssl_atb_master_atdata_o69;
+    output fabric_tnd_hssl_atb_master_atdata_o7;
+    output fabric_tnd_hssl_atb_master_atdata_o70;
+    output fabric_tnd_hssl_atb_master_atdata_o71;
+    output fabric_tnd_hssl_atb_master_atdata_o72;
+    output fabric_tnd_hssl_atb_master_atdata_o73;
+    output fabric_tnd_hssl_atb_master_atdata_o74;
+    output fabric_tnd_hssl_atb_master_atdata_o75;
+    output fabric_tnd_hssl_atb_master_atdata_o76;
+    output fabric_tnd_hssl_atb_master_atdata_o77;
+    output fabric_tnd_hssl_atb_master_atdata_o78;
+    output fabric_tnd_hssl_atb_master_atdata_o79;
+    output fabric_tnd_hssl_atb_master_atdata_o8;
+    output fabric_tnd_hssl_atb_master_atdata_o80;
+    output fabric_tnd_hssl_atb_master_atdata_o81;
+    output fabric_tnd_hssl_atb_master_atdata_o82;
+    output fabric_tnd_hssl_atb_master_atdata_o83;
+    output fabric_tnd_hssl_atb_master_atdata_o84;
+    output fabric_tnd_hssl_atb_master_atdata_o85;
+    output fabric_tnd_hssl_atb_master_atdata_o86;
+    output fabric_tnd_hssl_atb_master_atdata_o87;
+    output fabric_tnd_hssl_atb_master_atdata_o88;
+    output fabric_tnd_hssl_atb_master_atdata_o89;
+    output fabric_tnd_hssl_atb_master_atdata_o9;
+    output fabric_tnd_hssl_atb_master_atdata_o90;
+    output fabric_tnd_hssl_atb_master_atdata_o91;
+    output fabric_tnd_hssl_atb_master_atdata_o92;
+    output fabric_tnd_hssl_atb_master_atdata_o93;
+    output fabric_tnd_hssl_atb_master_atdata_o94;
+    output fabric_tnd_hssl_atb_master_atdata_o95;
+    output fabric_tnd_hssl_atb_master_atdata_o96;
+    output fabric_tnd_hssl_atb_master_atdata_o97;
+    output fabric_tnd_hssl_atb_master_atdata_o98;
+    output fabric_tnd_hssl_atb_master_atdata_o99;
+    output fabric_tnd_hssl_atb_master_atid_o1;
+    output fabric_tnd_hssl_atb_master_atid_o2;
+    output fabric_tnd_hssl_atb_master_atid_o3;
+    output fabric_tnd_hssl_atb_master_atid_o4;
+    output fabric_tnd_hssl_atb_master_atid_o5;
+    output fabric_tnd_hssl_atb_master_atid_o6;
+    output fabric_tnd_hssl_atb_master_atid_o7;
+    input fabric_tnd_hssl_atb_master_atready_i;
+    output fabric_tnd_hssl_atb_master_atvalid_o;
+    input fabric_tnd_hssl_atb_master_syncreq_i;
+    output fabric_tnd_hssl_flushin_o;
+    output fabric_tnd_hssl_trigin_o;
+    output fabric_tnd_trace_clk_traceoutportintf_o;
+    output fabric_tnd_trace_ctl_traceoutportintf_o;
+    output fabric_tnd_trace_data_traceoutportintf_o1;
+    output fabric_tnd_trace_data_traceoutportintf_o10;
+    output fabric_tnd_trace_data_traceoutportintf_o11;
+    output fabric_tnd_trace_data_traceoutportintf_o12;
+    output fabric_tnd_trace_data_traceoutportintf_o13;
+    output fabric_tnd_trace_data_traceoutportintf_o14;
+    output fabric_tnd_trace_data_traceoutportintf_o15;
+    output fabric_tnd_trace_data_traceoutportintf_o16;
+    output fabric_tnd_trace_data_traceoutportintf_o17;
+    output fabric_tnd_trace_data_traceoutportintf_o18;
+    output fabric_tnd_trace_data_traceoutportintf_o19;
+    output fabric_tnd_trace_data_traceoutportintf_o2;
+    output fabric_tnd_trace_data_traceoutportintf_o20;
+    output fabric_tnd_trace_data_traceoutportintf_o21;
+    output fabric_tnd_trace_data_traceoutportintf_o22;
+    output fabric_tnd_trace_data_traceoutportintf_o23;
+    output fabric_tnd_trace_data_traceoutportintf_o24;
+    output fabric_tnd_trace_data_traceoutportintf_o25;
+    output fabric_tnd_trace_data_traceoutportintf_o26;
+    output fabric_tnd_trace_data_traceoutportintf_o27;
+    output fabric_tnd_trace_data_traceoutportintf_o28;
+    output fabric_tnd_trace_data_traceoutportintf_o29;
+    output fabric_tnd_trace_data_traceoutportintf_o3;
+    output fabric_tnd_trace_data_traceoutportintf_o30;
+    output fabric_tnd_trace_data_traceoutportintf_o31;
+    output fabric_tnd_trace_data_traceoutportintf_o32;
+    output fabric_tnd_trace_data_traceoutportintf_o4;
+    output fabric_tnd_trace_data_traceoutportintf_o5;
+    output fabric_tnd_trace_data_traceoutportintf_o6;
+    output fabric_tnd_trace_data_traceoutportintf_o7;
+    output fabric_tnd_trace_data_traceoutportintf_o8;
+    output fabric_tnd_trace_data_traceoutportintf_o9;
+    output fabric_tst_pll_lock_o1;
+    output fabric_tst_pll_lock_o2;
+    output fabric_tst_pll_lock_o3;
+    output fabric_tst_pll_lock_o4;
+    output fabric_tst_pll_lock_o5;
+    output fabric_tst_pll_lock_o6;
+    output fabric_tst_pll_lock_o7;
+    output fabric_tsvalue_tsgen_fpga_o1;
+    output fabric_tsvalue_tsgen_fpga_o10;
+    output fabric_tsvalue_tsgen_fpga_o11;
+    output fabric_tsvalue_tsgen_fpga_o12;
+    output fabric_tsvalue_tsgen_fpga_o13;
+    output fabric_tsvalue_tsgen_fpga_o14;
+    output fabric_tsvalue_tsgen_fpga_o15;
+    output fabric_tsvalue_tsgen_fpga_o16;
+    output fabric_tsvalue_tsgen_fpga_o17;
+    output fabric_tsvalue_tsgen_fpga_o18;
+    output fabric_tsvalue_tsgen_fpga_o19;
+    output fabric_tsvalue_tsgen_fpga_o2;
+    output fabric_tsvalue_tsgen_fpga_o20;
+    output fabric_tsvalue_tsgen_fpga_o21;
+    output fabric_tsvalue_tsgen_fpga_o22;
+    output fabric_tsvalue_tsgen_fpga_o23;
+    output fabric_tsvalue_tsgen_fpga_o24;
+    output fabric_tsvalue_tsgen_fpga_o25;
+    output fabric_tsvalue_tsgen_fpga_o26;
+    output fabric_tsvalue_tsgen_fpga_o27;
+    output fabric_tsvalue_tsgen_fpga_o28;
+    output fabric_tsvalue_tsgen_fpga_o29;
+    output fabric_tsvalue_tsgen_fpga_o3;
+    output fabric_tsvalue_tsgen_fpga_o30;
+    output fabric_tsvalue_tsgen_fpga_o31;
+    output fabric_tsvalue_tsgen_fpga_o32;
+    output fabric_tsvalue_tsgen_fpga_o33;
+    output fabric_tsvalue_tsgen_fpga_o34;
+    output fabric_tsvalue_tsgen_fpga_o35;
+    output fabric_tsvalue_tsgen_fpga_o36;
+    output fabric_tsvalue_tsgen_fpga_o37;
+    output fabric_tsvalue_tsgen_fpga_o38;
+    output fabric_tsvalue_tsgen_fpga_o39;
+    output fabric_tsvalue_tsgen_fpga_o4;
+    output fabric_tsvalue_tsgen_fpga_o40;
+    output fabric_tsvalue_tsgen_fpga_o41;
+    output fabric_tsvalue_tsgen_fpga_o42;
+    output fabric_tsvalue_tsgen_fpga_o43;
+    output fabric_tsvalue_tsgen_fpga_o44;
+    output fabric_tsvalue_tsgen_fpga_o45;
+    output fabric_tsvalue_tsgen_fpga_o46;
+    output fabric_tsvalue_tsgen_fpga_o47;
+    output fabric_tsvalue_tsgen_fpga_o48;
+    output fabric_tsvalue_tsgen_fpga_o49;
+    output fabric_tsvalue_tsgen_fpga_o5;
+    output fabric_tsvalue_tsgen_fpga_o50;
+    output fabric_tsvalue_tsgen_fpga_o51;
+    output fabric_tsvalue_tsgen_fpga_o52;
+    output fabric_tsvalue_tsgen_fpga_o53;
+    output fabric_tsvalue_tsgen_fpga_o54;
+    output fabric_tsvalue_tsgen_fpga_o55;
+    output fabric_tsvalue_tsgen_fpga_o56;
+    output fabric_tsvalue_tsgen_fpga_o57;
+    output fabric_tsvalue_tsgen_fpga_o58;
+    output fabric_tsvalue_tsgen_fpga_o59;
+    output fabric_tsvalue_tsgen_fpga_o6;
+    output fabric_tsvalue_tsgen_fpga_o60;
+    output fabric_tsvalue_tsgen_fpga_o61;
+    output fabric_tsvalue_tsgen_fpga_o62;
+    output fabric_tsvalue_tsgen_fpga_o63;
+    output fabric_tsvalue_tsgen_fpga_o64;
+    output fabric_tsvalue_tsgen_fpga_o7;
+    output fabric_tsvalue_tsgen_fpga_o8;
+    output fabric_tsvalue_tsgen_fpga_o9;
+    output fabric_watchdog0_signal_0_o;
+    output fabric_watchdog0_signal_1_o;
+    output fabric_watchdog1_signal_0_o;
+    output fabric_watchdog1_signal_1_o;
+    output fabric_watchdog2_signal_0_o;
+    output fabric_watchdog2_signal_1_o;
+    output fabric_watchdog3_signal_0_o;
+    output fabric_watchdog3_signal_1_o;
+    parameter ahb_config = 0;
+    parameter bsm_config = 0;
+endmodule
+
+(* blackbox *)
+module NX_SOC_INTERFACE_V1_WRAP(fabric_fpga_pmrstn_i, fabric_fpga_sysrstn_i, fabric_sysc_hold_on_debug_i, fabric_fpga_arlock_axi_s1_o, fabric_fpga_arvalid_axi_s1_o, fabric_fpga_awlock_axi_s1_o, fabric_fpga_bready_axi_s1_o, fabric_fpga_rready_axi_s1_o, fabric_fpga_wlast_axi_s1_o, fabric_fpga_wvalid_axi_s1_o, fabric_fpga_awvalid_axi_s1_o, fabric_fpga_arready_axi_s1_i, fabric_fpga_awready_axi_s1_i, fabric_fpga_bvalid_axi_s1_i, fabric_fpga_rlast_axi_s1_i, fabric_fpga_rvalid_axi_s1_i, fabric_fpga_wready_axi_s1_i, fabric_fpga_arlock_axi_s2_o, fabric_fpga_arvalid_axi_s2_o, fabric_fpga_awlock_axi_s2_o, fabric_fpga_bready_axi_s2_o
+, fabric_fpga_rready_axi_s2_o, fabric_fpga_wlast_axi_s2_o, fabric_fpga_wvalid_axi_s2_o, fabric_fpga_awvalid_axi_s2_o, fabric_fpga_arready_axi_s2_i, fabric_fpga_awready_axi_s2_i, fabric_fpga_bvalid_axi_s2_i, fabric_fpga_rlast_axi_s2_i, fabric_fpga_rvalid_axi_s2_i, fabric_fpga_wready_axi_s2_i, fabric_fpga_arready_axi_m1_o, fabric_fpga_awready_axi_m1_o, fabric_fpga_bvalid_axi_m1_o, fabric_fpga_rlast_axi_m1_o, fabric_fpga_rvalid_axi_m1_o, fabric_fpga_wready_axi_m1_o, fabric_fpga_arlock_axi_m1_i, fabric_fpga_arvalid_axi_m1_i, fabric_fpga_awlock_axi_m1_i, fabric_fpga_awvalid_axi_m1_i, fabric_fpga_bready_axi_m1_i
+, fabric_fpga_rready_axi_m1_i, fabric_fpga_wlast_axi_m1_i, fabric_fpga_wvalid_axi_m1_i, fabric_fpga_arready_axi_m2_o, fabric_fpga_awready_axi_m2_o, fabric_fpga_bvalid_axi_m2_o, fabric_fpga_rlast_axi_m2_o, fabric_fpga_rvalid_axi_m2_o, fabric_fpga_wready_axi_m2_o, fabric_fpga_arlock_axi_m2_i, fabric_fpga_arvalid_axi_m2_i, fabric_fpga_awlock_axi_m2_i, fabric_fpga_awvalid_axi_m2_i, fabric_fpga_bready_axi_m2_i, fabric_fpga_rready_axi_m2_i, fabric_fpga_wlast_axi_m2_i, fabric_fpga_wvalid_axi_m2_i, fabric_fpga_ddr0_arready_o, fabric_fpga_ddr0_awready_o, fabric_fpga_ddr0_bvalid_o, fabric_fpga_ddr0_rlast_o
+, fabric_fpga_ddr0_rvalid_o, fabric_fpga_ddr0_wready_o, fabric_fpga_ddr0_arlock_i, fabric_fpga_ddr0_arvalid_i, fabric_fpga_ddr0_awlock_i, fabric_fpga_ddr0_awvalid_i, fabric_fpga_ddr0_bready_i, fabric_fpga_ddr0_rready_i, fabric_fpga_ddr0_wlast_i, fabric_fpga_ddr0_wvalid_i, fabric_fpga_penable_apb_o, fabric_fpga_psel_apb_o, fabric_fpga_pwrite_apb_o, fabric_fpga_pready_apb_i, fabric_fpga_pslverr_apb_i, fabric_llpp0_arlock_s_o, fabric_llpp0_arvalid_s_o, fabric_llpp0_awlock_s_o, fabric_llpp0_awvalid_s_o, fabric_llpp0_bready_s_o, fabric_llpp0_rready_s_o
+, fabric_llpp0_wlast_s_o, fabric_llpp0_wvalid_s_o, fabric_llpp0_arready_s_i, fabric_llpp0_awready_s_i, fabric_llpp0_bvalid_s_i, fabric_llpp0_rlast_s_i, fabric_llpp0_rvalid_s_i, fabric_llpp0_wready_s_i, fabric_llpp1_arlock_s_o, fabric_llpp1_arvalid_s_o, fabric_llpp1_awlock_s_o, fabric_llpp1_awvalid_s_o, fabric_llpp1_bready_s_o, fabric_llpp1_rready_s_o, fabric_llpp1_wlast_s_o, fabric_llpp1_wvalid_s_o, fabric_llpp1_arready_s_i, fabric_llpp1_awready_s_i, fabric_llpp1_bvalid_s_i, fabric_llpp1_rlast_s_i, fabric_llpp1_rvalid_s_i
+, fabric_llpp1_wready_s_i, fabric_llpp2_arlock_s_o, fabric_llpp2_arvalid_s_o, fabric_llpp2_awlock_s_o, fabric_llpp2_awvalid_s_o, fabric_llpp2_bready_s_o, fabric_llpp2_rready_s_o, fabric_llpp2_wlast_s_o, fabric_llpp2_wvalid_s_o, fabric_llpp2_arready_s_i, fabric_llpp2_awready_s_i, fabric_llpp2_bvalid_s_i, fabric_llpp2_rlast_s_i, fabric_llpp2_rvalid_s_i, fabric_llpp2_wready_s_i, fabric_llpp3_arlock_s_o, fabric_llpp3_arvalid_s_o, fabric_llpp3_awlock_s_o, fabric_llpp3_awvalid_s_o, fabric_llpp3_bready_s_o, fabric_llpp3_rready_s_o
+, fabric_llpp3_wlast_s_o, fabric_llpp3_wvalid_s_o, fabric_llpp3_arready_s_i, fabric_llpp3_awready_s_i, fabric_llpp3_bvalid_s_i, fabric_llpp3_rlast_s_i, fabric_llpp3_rvalid_s_i, fabric_llpp3_wready_s_i, fabric_qos_ppready_o, fabric_qos_ppslverr_o, fabric_qos_pclk_i, fabric_qos_ppenable_i, fabric_qos_ppwrite_i, fabric_qos_presetn_i, fabric_qos_psel_i, fabric_tnd_hssl_flushin_o, fabric_tnd_hssl_trigin_o, fabric_tnd_fpga_apb_master_penable_o, fabric_tnd_fpga_apb_master_psel_o, fabric_tnd_fpga_apb_master_pwrite_o, fabric_tnd_fpga_atb_master_afvalid_o
+, fabric_tnd_fpga_atb_master_atready_o, fabric_tnd_fpga_atb_master_syncreq_o, fabric_tnd_hssl_apb_master_penable_o, fabric_tnd_hssl_apb_master_psel_o, fabric_tnd_hssl_apb_master_pwrite_o, fabric_tnd_hssl_atb_master_afready_o, fabric_tnd_hssl_atb_master_atvalid_o, fabric_tnd_trace_clk_traceoutportintf_o, fabric_tnd_trace_ctl_traceoutportintf_o, fabric_tnd_fpga_apb_master_pready_i, fabric_tnd_fpga_apb_master_pslverr_i, fabric_tnd_fpga_atb_master_afready_i, fabric_tnd_fpga_atb_master_atvalid_i, fabric_tnd_hssl_apb_master_pready_i, fabric_tnd_hssl_apb_master_pslverr_i, fabric_tnd_hssl_atb_master_afvalid_i, fabric_tnd_hssl_atb_master_atready_i, fabric_tnd_hssl_atb_master_syncreq_i, fabric_watchdog0_signal_0_o, fabric_watchdog0_signal_1_o, fabric_watchdog1_signal_0_o
+, fabric_watchdog1_signal_1_o, fabric_watchdog2_signal_0_o, fabric_watchdog2_signal_1_o, fabric_watchdog3_signal_0_o, fabric_watchdog3_signal_1_o, fabric_soc_mon_sensor_alarm_o, fabric_erom_fpga_cpu0_dbgen_i, fabric_erom_fpga_cpu0_hiden_i, fabric_erom_fpga_cpu0_hniden_i, fabric_erom_fpga_cpu0_niden_i, fabric_erom_fpga_cpu1_dbgen_i, fabric_erom_fpga_cpu1_hiden_i, fabric_erom_fpga_cpu1_hniden_i, fabric_erom_fpga_cpu1_niden_i, fabric_erom_fpga_cpu2_dbgen_i, fabric_erom_fpga_cpu2_hiden_i, fabric_erom_fpga_cpu2_hniden_i, fabric_erom_fpga_cpu2_niden_i, fabric_erom_fpga_cpu3_dbgen_i, fabric_erom_fpga_cpu3_hiden_i, fabric_erom_fpga_cpu3_hniden_i
+, fabric_erom_fpga_cpu3_niden_i, fabric_erom_fpga_cs_dbgen_i, fabric_erom_fpga_cs_niden_i, fabric_erom_fpga_cs_deviceen_i, fabric_erom_fpga_cs_rst_n_i, fabric_erom_fpga_debug_en_i, fabric_enable_TMR_i, fabric_lowskew_i, fabric_lowskew_o, fabric_fpga_nic_rstn_i, fabric_fpga_trigger_in_o, fabric_fpga_trigger_out_i, fabric_fpga_interrupt_in_i, fabric_fpga_events60_i, fabric_fpga_araddr_axi_s1_o, fabric_fpga_arburst_axi_s1_o, fabric_fpga_arcache_axi_s1_o, fabric_fpga_arid_axi_s1_o, fabric_fpga_arlen_axi_s1_o, fabric_fpga_arprot_axi_s1_o, fabric_fpga_arqos_axi_s1_o
+, fabric_fpga_arregion_axi_s1_o, fabric_fpga_arsize_axi_s1_o, fabric_fpga_awaddr_axi_s1_o, fabric_fpga_awburst_axi_s1_o, fabric_fpga_awcache_axi_s1_o, fabric_fpga_awid_axi_s1_o, fabric_fpga_awlen_axi_s1_o, fabric_fpga_awprot_axi_s1_o, fabric_fpga_awqos_axi_s1_o, fabric_fpga_awregion_axi_s1_o, fabric_fpga_awsize_axi_s1_o, fabric_fpga_wdata_axi_s1_o, fabric_fpga_wstrb_axi_s1_o, fabric_fpga_bid_axi_s1_i, fabric_fpga_bresp_axi_s1_i, fabric_fpga_rdata_axi_s1_i, fabric_fpga_rid_axi_s1_i, fabric_fpga_rresp_axi_s1_i, fabric_fpga_araddr_axi_s2_o, fabric_fpga_arburst_axi_s2_o, fabric_fpga_arcache_axi_s2_o
+, fabric_fpga_arid_axi_s2_o, fabric_fpga_arlen_axi_s2_o, fabric_fpga_arprot_axi_s2_o, fabric_fpga_arqos_axi_s2_o, fabric_fpga_arregion_axi_s2_o, fabric_fpga_arsize_axi_s2_o, fabric_fpga_awaddr_axi_s2_o, fabric_fpga_awburst_axi_s2_o, fabric_fpga_awcache_axi_s2_o, fabric_fpga_awid_axi_s2_o, fabric_fpga_awlen_axi_s2_o, fabric_fpga_awprot_axi_s2_o, fabric_fpga_awqos_axi_s2_o, fabric_fpga_awregion_axi_s2_o, fabric_fpga_awsize_axi_s2_o, fabric_fpga_wdata_axi_s2_o, fabric_fpga_wstrb_axi_s2_o, fabric_fpga_bid_axi_s2_i, fabric_fpga_bresp_axi_s2_i, fabric_fpga_rdata_axi_s2_i, fabric_fpga_rid_axi_s2_i
+, fabric_fpga_rresp_axi_s2_i, fabric_fpga_bid_axi_m1_o, fabric_fpga_bresp_axi_m1_o, fabric_fpga_dma_ack_m1_o, fabric_fpga_dma_finish_m1_o, fabric_fpga_rdata_axi_m1_o, fabric_fpga_rid_axi_m1_o, fabric_fpga_rresp_axi_m1_o, fabric_fpga_araddr_axi_m1_i, fabric_fpga_arburst_axi_m1_i, fabric_fpga_arcache_axi_m1_i, fabric_fpga_arid_axi_m1_i, fabric_fpga_arlen_axi_m1_i, fabric_fpga_arprot_axi_m1_i, fabric_fpga_arqos_axi_m1_i, fabric_fpga_arsize_axi_m1_i, fabric_fpga_awaddr_axi_m1_i, fabric_fpga_awburst_axi_m1_i, fabric_fpga_awcache_axi_m1_i, fabric_fpga_awid_axi_m1_i, fabric_fpga_awlen_axi_m1_i
+, fabric_fpga_awprot_axi_m1_i, fabric_fpga_awqos_axi_m1_i, fabric_fpga_awsize_axi_m1_i, fabric_fpga_dma_last_m1_i, fabric_fpga_dma_req_m1_i, fabric_fpga_dma_single_m1_i, fabric_fpga_wdata_axi_m1_i, fabric_fpga_wstrb_axi_m1_i, fabric_fpga_bid_axi_m2_o, fabric_fpga_bresp_axi_m2_o, fabric_fpga_dma_ack_m2_o, fabric_fpga_dma_finish_m2_o, fabric_fpga_rdata_axi_m2_o, fabric_fpga_rid_axi_m2_o, fabric_fpga_rresp_axi_m2_o, fabric_fpga_araddr_axi_m2_i, fabric_fpga_arburst_axi_m2_i, fabric_fpga_arcache_axi_m2_i, fabric_fpga_arid_axi_m2_i, fabric_fpga_arlen_axi_m2_i, fabric_fpga_arprot_axi_m2_i
+, fabric_fpga_arqos_axi_m2_i, fabric_fpga_arsize_axi_m2_i, fabric_fpga_awaddr_axi_m2_i, fabric_fpga_awburst_axi_m2_i, fabric_fpga_awcache_axi_m2_i, fabric_fpga_awid_axi_m2_i, fabric_fpga_awlen_axi_m2_i, fabric_fpga_awprot_axi_m2_i, fabric_fpga_awqos_axi_m2_i, fabric_fpga_awsize_axi_m2_i, fabric_fpga_dma_last_m2_i, fabric_fpga_dma_req_m2_i, fabric_fpga_dma_single_m2_i, fabric_fpga_wdata_axi_m2_i, fabric_fpga_wstrb_axi_m2_i, fabric_fpga_ddr0_bid_o, fabric_fpga_ddr0_bresp_o, fabric_fpga_ddr0_rdata_o, fabric_fpga_ddr0_rid_o, fabric_fpga_ddr0_rresp_o, fabric_fpga_ddr0_araddr_i
+, fabric_fpga_ddr0_arburst_i, fabric_fpga_ddr0_arcache_i, fabric_fpga_ddr0_arid_i, fabric_fpga_ddr0_arlen_i, fabric_fpga_ddr0_arprot_i, fabric_fpga_ddr0_arqos_i, fabric_fpga_ddr0_arsize_i, fabric_fpga_ddr0_awaddr_i, fabric_fpga_ddr0_awburst_i, fabric_fpga_ddr0_awcache_i, fabric_fpga_ddr0_awid_i, fabric_fpga_ddr0_awlen_i, fabric_fpga_ddr0_awprot_i, fabric_fpga_ddr0_awqos_i, fabric_fpga_ddr0_awsize_i, fabric_fpga_ddr0_wdata_i, fabric_fpga_ddr0_wstrb_i, fabric_fpga_paddr_apb_o, fabric_fpga_pwdata_apb_o, fabric_fpga_prdata_apb_i, fabric_llpp0_araddr_s_o
+, fabric_llpp0_arburst_s_o, fabric_llpp0_arcache_s_o, fabric_llpp0_arid_s_o, fabric_llpp0_arlen_s_o, fabric_llpp0_arprot_s_o, fabric_llpp0_arqos_s_o, fabric_llpp0_arsize_s_o, fabric_llpp0_awaddr_s_o, fabric_llpp0_awburst_s_o, fabric_llpp0_awcache_s_o, fabric_llpp0_awid_s_o, fabric_llpp0_awlen_s_o, fabric_llpp0_awprot_s_o, fabric_llpp0_awqos_s_o, fabric_llpp0_awsize_s_o, fabric_llpp0_wdata_s_o, fabric_llpp0_wstrb_s_o, fabric_llpp0_bid_s_i, fabric_llpp0_bresp_s_i, fabric_llpp0_rdata_s_i, fabric_llpp0_rid_s_i
+, fabric_llpp0_rresp_s_i, fabric_llpp1_araddr_s_o, fabric_llpp1_arburst_s_o, fabric_llpp1_arcache_s_o, fabric_llpp1_arid_s_o, fabric_llpp1_arlen_s_o, fabric_llpp1_arprot_s_o, fabric_llpp1_arqos_s1_o, fabric_llpp1_arsize_s_o, fabric_llpp1_awaddr_s_o, fabric_llpp1_awburst_s_o, fabric_llpp1_awcache_s_o, fabric_llpp1_awid_s_o, fabric_llpp1_awlen_s_o, fabric_llpp1_awprot_s_o, fabric_llpp1_awqos_s_o, fabric_llpp1_awsize_s_o, fabric_llpp1_wdata_s_o, fabric_llpp1_wstrb_s_o, fabric_llpp1_bid_s_i, fabric_llpp1_bresp_s_i
+, fabric_llpp1_rdata_s_i, fabric_llpp1_rid_s_i, fabric_llpp1_rresp_s_i, fabric_llpp2_araddr_s_o, fabric_llpp2_arburst_s_o, fabric_llpp2_arcache_s_o, fabric_llpp2_arid_s_o, fabric_llpp2_arlen_s_o, fabric_llpp2_arprot_s_o, fabric_llpp2_arqos_s_o, fabric_llpp2_arsize_s_o, fabric_llpp2_awaddr_s_o, fabric_llpp2_awburst_s_o, fabric_llpp2_awcache_s_o, fabric_llpp2_awid_s_o, fabric_llpp2_awlen_s_o, fabric_llpp2_awprot_s_o, fabric_llpp2_awqos_s_o, fabric_llpp2_awsize_s_o, fabric_llpp2_wdata_s_o, fabric_llpp2_wstrb_s_o
+, fabric_llpp2_bid_s_i, fabric_llpp2_bresp_s_i, fabric_llpp2_rdata_s_i, fabric_llpp2_rid_s_i, fabric_llpp2_rresp_s_i, fabric_llpp3_araddr_s_o, fabric_llpp3_arburst_s_o, fabric_llpp3_arcache_s_o, fabric_llpp3_arid_s_o, fabric_llpp3_arlen_s_o, fabric_llpp3_arprot_s_o, fabric_llpp3_arqos_s_o, fabric_llpp3_arsize_s_o, fabric_llpp3_awaddr_s_o, fabric_llpp3_awburst_s_o, fabric_llpp3_awcache_s_o, fabric_llpp3_awid_s_o, fabric_llpp3_awlen_s_o, fabric_llpp3_awprot_s_o, fabric_llpp3_awqos_s_o, fabric_llpp3_awsize_s_o
+, fabric_llpp3_wdata_s_o, fabric_llpp3_wstrb_s_o, fabric_llpp3_bid_s_i, fabric_llpp3_bresp_s_i, fabric_llpp3_rdata_s_i, fabric_llpp3_rid_s_i, fabric_llpp3_rresp_s_i, fabric_qos_pprdata_o, fabric_qos_ppaddr_i, fabric_qos_ppwdata_i, fabric_tnd_fpga_apb_master_paddr_o, fabric_tnd_fpga_apb_master_pwdata_o, fabric_tnd_hssl_apb_master_paddr_o, fabric_tnd_hssl_apb_master_pwdata_o, fabric_tnd_hssl_atb_master_atbytes_o, fabric_tnd_hssl_atb_master_atdata_o, fabric_tnd_hssl_atb_master_atid_o, fabric_tnd_trace_data_traceoutportintf_o, fabric_tsvalue_tsgen_fpga_o, fabric_tnd_fpga_apb_master_prdata_i, fabric_tnd_fpga_atb_master_atbytes_i
+, fabric_tnd_fpga_atb_master_atdata_i, fabric_tnd_fpga_atb_master_atid_i, fabric_tnd_hssl_apb_master_prdata_i, fabric_tst_pll_lock_o);
+    input [2:0] fabric_enable_TMR_i;
+    input fabric_erom_fpga_cpu0_dbgen_i;
+    input fabric_erom_fpga_cpu0_hiden_i;
+    input fabric_erom_fpga_cpu0_hniden_i;
+    input fabric_erom_fpga_cpu0_niden_i;
+    input fabric_erom_fpga_cpu1_dbgen_i;
+    input fabric_erom_fpga_cpu1_hiden_i;
+    input fabric_erom_fpga_cpu1_hniden_i;
+    input fabric_erom_fpga_cpu1_niden_i;
+    input fabric_erom_fpga_cpu2_dbgen_i;
+    input fabric_erom_fpga_cpu2_hiden_i;
+    input fabric_erom_fpga_cpu2_hniden_i;
+    input fabric_erom_fpga_cpu2_niden_i;
+    input fabric_erom_fpga_cpu3_dbgen_i;
+    input fabric_erom_fpga_cpu3_hiden_i;
+    input fabric_erom_fpga_cpu3_hniden_i;
+    input fabric_erom_fpga_cpu3_niden_i;
+    input fabric_erom_fpga_cs_dbgen_i;
+    input fabric_erom_fpga_cs_deviceen_i;
+    input fabric_erom_fpga_cs_niden_i;
+    input fabric_erom_fpga_cs_rst_n_i;
+    input fabric_erom_fpga_debug_en_i;
+    input [39:0] fabric_fpga_araddr_axi_m1_i;
+    input [39:0] fabric_fpga_araddr_axi_m2_i;
+    output [39:0] fabric_fpga_araddr_axi_s1_o;
+    output [39:0] fabric_fpga_araddr_axi_s2_o;
+    input [1:0] fabric_fpga_arburst_axi_m1_i;
+    input [1:0] fabric_fpga_arburst_axi_m2_i;
+    output [1:0] fabric_fpga_arburst_axi_s1_o;
+    output [1:0] fabric_fpga_arburst_axi_s2_o;
+    input [3:0] fabric_fpga_arcache_axi_m1_i;
+    input [3:0] fabric_fpga_arcache_axi_m2_i;
+    output [3:0] fabric_fpga_arcache_axi_s1_o;
+    output [3:0] fabric_fpga_arcache_axi_s2_o;
+    input [4:0] fabric_fpga_arid_axi_m1_i;
+    input [4:0] fabric_fpga_arid_axi_m2_i;
+    output [11:0] fabric_fpga_arid_axi_s1_o;
+    output [11:0] fabric_fpga_arid_axi_s2_o;
+    input [7:0] fabric_fpga_arlen_axi_m1_i;
+    input [7:0] fabric_fpga_arlen_axi_m2_i;
+    output [7:0] fabric_fpga_arlen_axi_s1_o;
+    output [7:0] fabric_fpga_arlen_axi_s2_o;
+    input fabric_fpga_arlock_axi_m1_i;
+    input fabric_fpga_arlock_axi_m2_i;
+    output fabric_fpga_arlock_axi_s1_o;
+    output fabric_fpga_arlock_axi_s2_o;
+    input [2:0] fabric_fpga_arprot_axi_m1_i;
+    input [2:0] fabric_fpga_arprot_axi_m2_i;
+    output [2:0] fabric_fpga_arprot_axi_s1_o;
+    output [2:0] fabric_fpga_arprot_axi_s2_o;
+    input [3:0] fabric_fpga_arqos_axi_m1_i;
+    input [3:0] fabric_fpga_arqos_axi_m2_i;
+    output [3:0] fabric_fpga_arqos_axi_s1_o;
+    output [3:0] fabric_fpga_arqos_axi_s2_o;
+    output fabric_fpga_arready_axi_m1_o;
+    output fabric_fpga_arready_axi_m2_o;
+    input fabric_fpga_arready_axi_s1_i;
+    input fabric_fpga_arready_axi_s2_i;
+    output [3:0] fabric_fpga_arregion_axi_s1_o;
+    output [3:0] fabric_fpga_arregion_axi_s2_o;
+    input [2:0] fabric_fpga_arsize_axi_m1_i;
+    input [2:0] fabric_fpga_arsize_axi_m2_i;
+    output [2:0] fabric_fpga_arsize_axi_s1_o;
+    output [2:0] fabric_fpga_arsize_axi_s2_o;
+    input fabric_fpga_arvalid_axi_m1_i;
+    input fabric_fpga_arvalid_axi_m2_i;
+    output fabric_fpga_arvalid_axi_s1_o;
+    output fabric_fpga_arvalid_axi_s2_o;
+    input [39:0] fabric_fpga_awaddr_axi_m1_i;
+    input [39:0] fabric_fpga_awaddr_axi_m2_i;
+    output [39:0] fabric_fpga_awaddr_axi_s1_o;
+    output [39:0] fabric_fpga_awaddr_axi_s2_o;
+    input [1:0] fabric_fpga_awburst_axi_m1_i;
+    input [1:0] fabric_fpga_awburst_axi_m2_i;
+    output [1:0] fabric_fpga_awburst_axi_s1_o;
+    output [1:0] fabric_fpga_awburst_axi_s2_o;
+    input [3:0] fabric_fpga_awcache_axi_m1_i;
+    input [3:0] fabric_fpga_awcache_axi_m2_i;
+    output [3:0] fabric_fpga_awcache_axi_s1_o;
+    output [3:0] fabric_fpga_awcache_axi_s2_o;
+    input [4:0] fabric_fpga_awid_axi_m1_i;
+    input [4:0] fabric_fpga_awid_axi_m2_i;
+    output [11:0] fabric_fpga_awid_axi_s1_o;
+    output [11:0] fabric_fpga_awid_axi_s2_o;
+    input [7:0] fabric_fpga_awlen_axi_m1_i;
+    input [7:0] fabric_fpga_awlen_axi_m2_i;
+    output [7:0] fabric_fpga_awlen_axi_s1_o;
+    output [7:0] fabric_fpga_awlen_axi_s2_o;
+    input fabric_fpga_awlock_axi_m1_i;
+    input fabric_fpga_awlock_axi_m2_i;
+    output fabric_fpga_awlock_axi_s1_o;
+    output fabric_fpga_awlock_axi_s2_o;
+    input [2:0] fabric_fpga_awprot_axi_m1_i;
+    input [2:0] fabric_fpga_awprot_axi_m2_i;
+    output [2:0] fabric_fpga_awprot_axi_s1_o;
+    output [2:0] fabric_fpga_awprot_axi_s2_o;
+    input [3:0] fabric_fpga_awqos_axi_m1_i;
+    input [3:0] fabric_fpga_awqos_axi_m2_i;
+    output [3:0] fabric_fpga_awqos_axi_s1_o;
+    output [3:0] fabric_fpga_awqos_axi_s2_o;
+    output fabric_fpga_awready_axi_m1_o;
+    output fabric_fpga_awready_axi_m2_o;
+    input fabric_fpga_awready_axi_s1_i;
+    input fabric_fpga_awready_axi_s2_i;
+    output [3:0] fabric_fpga_awregion_axi_s1_o;
+    output [3:0] fabric_fpga_awregion_axi_s2_o;
+    input [2:0] fabric_fpga_awsize_axi_m1_i;
+    input [2:0] fabric_fpga_awsize_axi_m2_i;
+    output [2:0] fabric_fpga_awsize_axi_s1_o;
+    output [2:0] fabric_fpga_awsize_axi_s2_o;
+    input fabric_fpga_awvalid_axi_m1_i;
+    input fabric_fpga_awvalid_axi_m2_i;
+    output fabric_fpga_awvalid_axi_s1_o;
+    output fabric_fpga_awvalid_axi_s2_o;
+    output [4:0] fabric_fpga_bid_axi_m1_o;
+    output [4:0] fabric_fpga_bid_axi_m2_o;
+    input [11:0] fabric_fpga_bid_axi_s1_i;
+    input [11:0] fabric_fpga_bid_axi_s2_i;
+    input fabric_fpga_bready_axi_m1_i;
+    input fabric_fpga_bready_axi_m2_i;
+    output fabric_fpga_bready_axi_s1_o;
+    output fabric_fpga_bready_axi_s2_o;
+    output [1:0] fabric_fpga_bresp_axi_m1_o;
+    output [1:0] fabric_fpga_bresp_axi_m2_o;
+    input [1:0] fabric_fpga_bresp_axi_s1_i;
+    input [1:0] fabric_fpga_bresp_axi_s2_i;
+    output fabric_fpga_bvalid_axi_m1_o;
+    output fabric_fpga_bvalid_axi_m2_o;
+    input fabric_fpga_bvalid_axi_s1_i;
+    input fabric_fpga_bvalid_axi_s2_i;
+    input [39:0] fabric_fpga_ddr0_araddr_i;
+    input [1:0] fabric_fpga_ddr0_arburst_i;
+    input [3:0] fabric_fpga_ddr0_arcache_i;
+    input [4:0] fabric_fpga_ddr0_arid_i;
+    input [7:0] fabric_fpga_ddr0_arlen_i;
+    input fabric_fpga_ddr0_arlock_i;
+    input [2:0] fabric_fpga_ddr0_arprot_i;
+    input [3:0] fabric_fpga_ddr0_arqos_i;
+    output fabric_fpga_ddr0_arready_o;
+    input [2:0] fabric_fpga_ddr0_arsize_i;
+    input fabric_fpga_ddr0_arvalid_i;
+    input [39:0] fabric_fpga_ddr0_awaddr_i;
+    input [1:0] fabric_fpga_ddr0_awburst_i;
+    input [3:0] fabric_fpga_ddr0_awcache_i;
+    input [4:0] fabric_fpga_ddr0_awid_i;
+    input [7:0] fabric_fpga_ddr0_awlen_i;
+    input fabric_fpga_ddr0_awlock_i;
+    input [2:0] fabric_fpga_ddr0_awprot_i;
+    input [3:0] fabric_fpga_ddr0_awqos_i;
+    output fabric_fpga_ddr0_awready_o;
+    input [2:0] fabric_fpga_ddr0_awsize_i;
+    input fabric_fpga_ddr0_awvalid_i;
+    output [4:0] fabric_fpga_ddr0_bid_o;
+    input fabric_fpga_ddr0_bready_i;
+    output [1:0] fabric_fpga_ddr0_bresp_o;
+    output fabric_fpga_ddr0_bvalid_o;
+    output [127:0] fabric_fpga_ddr0_rdata_o;
+    output [4:0] fabric_fpga_ddr0_rid_o;
+    output fabric_fpga_ddr0_rlast_o;
+    input fabric_fpga_ddr0_rready_i;
+    output [1:0] fabric_fpga_ddr0_rresp_o;
+    output fabric_fpga_ddr0_rvalid_o;
+    input [127:0] fabric_fpga_ddr0_wdata_i;
+    input fabric_fpga_ddr0_wlast_i;
+    output fabric_fpga_ddr0_wready_o;
+    input [15:0] fabric_fpga_ddr0_wstrb_i;
+    input fabric_fpga_ddr0_wvalid_i;
+    output [5:0] fabric_fpga_dma_ack_m1_o;
+    output [5:0] fabric_fpga_dma_ack_m2_o;
+    output [5:0] fabric_fpga_dma_finish_m1_o;
+    output [5:0] fabric_fpga_dma_finish_m2_o;
+    input [5:0] fabric_fpga_dma_last_m1_i;
+    input [5:0] fabric_fpga_dma_last_m2_i;
+    input [5:0] fabric_fpga_dma_req_m1_i;
+    input [5:0] fabric_fpga_dma_req_m2_i;
+    input [5:0] fabric_fpga_dma_single_m1_i;
+    input [5:0] fabric_fpga_dma_single_m2_i;
+    input [59:0] fabric_fpga_events60_i;
+    input [119:0] fabric_fpga_interrupt_in_i;
+    input [9:0] fabric_fpga_nic_rstn_i;
+    output [31:0] fabric_fpga_paddr_apb_o;
+    output fabric_fpga_penable_apb_o;
+    input fabric_fpga_pmrstn_i;
+    input [31:0] fabric_fpga_prdata_apb_i;
+    input fabric_fpga_pready_apb_i;
+    output fabric_fpga_psel_apb_o;
+    input fabric_fpga_pslverr_apb_i;
+    output [31:0] fabric_fpga_pwdata_apb_o;
+    output fabric_fpga_pwrite_apb_o;
+    output [127:0] fabric_fpga_rdata_axi_m1_o;
+    output [127:0] fabric_fpga_rdata_axi_m2_o;
+    input [127:0] fabric_fpga_rdata_axi_s1_i;
+    input [127:0] fabric_fpga_rdata_axi_s2_i;
+    output [4:0] fabric_fpga_rid_axi_m1_o;
+    output [4:0] fabric_fpga_rid_axi_m2_o;
+    input [11:0] fabric_fpga_rid_axi_s1_i;
+    input [11:0] fabric_fpga_rid_axi_s2_i;
+    output fabric_fpga_rlast_axi_m1_o;
+    output fabric_fpga_rlast_axi_m2_o;
+    input fabric_fpga_rlast_axi_s1_i;
+    input fabric_fpga_rlast_axi_s2_i;
+    input fabric_fpga_rready_axi_m1_i;
+    input fabric_fpga_rready_axi_m2_i;
+    output fabric_fpga_rready_axi_s1_o;
+    output fabric_fpga_rready_axi_s2_o;
+    output [1:0] fabric_fpga_rresp_axi_m1_o;
+    output [1:0] fabric_fpga_rresp_axi_m2_o;
+    input [1:0] fabric_fpga_rresp_axi_s1_i;
+    input [1:0] fabric_fpga_rresp_axi_s2_i;
+    output fabric_fpga_rvalid_axi_m1_o;
+    output fabric_fpga_rvalid_axi_m2_o;
+    input fabric_fpga_rvalid_axi_s1_i;
+    input fabric_fpga_rvalid_axi_s2_i;
+    input fabric_fpga_sysrstn_i;
+    output [7:0] fabric_fpga_trigger_in_o;
+    input [7:0] fabric_fpga_trigger_out_i;
+    input [127:0] fabric_fpga_wdata_axi_m1_i;
+    input [127:0] fabric_fpga_wdata_axi_m2_i;
+    output [127:0] fabric_fpga_wdata_axi_s1_o;
+    output [127:0] fabric_fpga_wdata_axi_s2_o;
+    input fabric_fpga_wlast_axi_m1_i;
+    input fabric_fpga_wlast_axi_m2_i;
+    output fabric_fpga_wlast_axi_s1_o;
+    output fabric_fpga_wlast_axi_s2_o;
+    output fabric_fpga_wready_axi_m1_o;
+    output fabric_fpga_wready_axi_m2_o;
+    input fabric_fpga_wready_axi_s1_i;
+    input fabric_fpga_wready_axi_s2_i;
+    input [15:0] fabric_fpga_wstrb_axi_m1_i;
+    input [15:0] fabric_fpga_wstrb_axi_m2_i;
+    output [15:0] fabric_fpga_wstrb_axi_s1_o;
+    output [15:0] fabric_fpga_wstrb_axi_s2_o;
+    input fabric_fpga_wvalid_axi_m1_i;
+    input fabric_fpga_wvalid_axi_m2_i;
+    output fabric_fpga_wvalid_axi_s1_o;
+    output fabric_fpga_wvalid_axi_s2_o;
+    output [31:0] fabric_llpp0_araddr_s_o;
+    output [1:0] fabric_llpp0_arburst_s_o;
+    output [3:0] fabric_llpp0_arcache_s_o;
+    output [11:0] fabric_llpp0_arid_s_o;
+    output [7:0] fabric_llpp0_arlen_s_o;
+    output fabric_llpp0_arlock_s_o;
+    output [2:0] fabric_llpp0_arprot_s_o;
+    output [3:0] fabric_llpp0_arqos_s_o;
+    input fabric_llpp0_arready_s_i;
+    output [2:0] fabric_llpp0_arsize_s_o;
+    output fabric_llpp0_arvalid_s_o;
+    output [31:0] fabric_llpp0_awaddr_s_o;
+    output [1:0] fabric_llpp0_awburst_s_o;
+    output [3:0] fabric_llpp0_awcache_s_o;
+    output [11:0] fabric_llpp0_awid_s_o;
+    output [7:0] fabric_llpp0_awlen_s_o;
+    output fabric_llpp0_awlock_s_o;
+    output [2:0] fabric_llpp0_awprot_s_o;
+    output [3:0] fabric_llpp0_awqos_s_o;
+    input fabric_llpp0_awready_s_i;
+    output [2:0] fabric_llpp0_awsize_s_o;
+    output fabric_llpp0_awvalid_s_o;
+    input [11:0] fabric_llpp0_bid_s_i;
+    output fabric_llpp0_bready_s_o;
+    input [1:0] fabric_llpp0_bresp_s_i;
+    input fabric_llpp0_bvalid_s_i;
+    input [31:0] fabric_llpp0_rdata_s_i;
+    input [11:0] fabric_llpp0_rid_s_i;
+    input fabric_llpp0_rlast_s_i;
+    output fabric_llpp0_rready_s_o;
+    input [1:0] fabric_llpp0_rresp_s_i;
+    input fabric_llpp0_rvalid_s_i;
+    output [31:0] fabric_llpp0_wdata_s_o;
+    output fabric_llpp0_wlast_s_o;
+    input fabric_llpp0_wready_s_i;
+    output [3:0] fabric_llpp0_wstrb_s_o;
+    output fabric_llpp0_wvalid_s_o;
+    output [31:0] fabric_llpp1_araddr_s_o;
+    output [1:0] fabric_llpp1_arburst_s_o;
+    output [3:0] fabric_llpp1_arcache_s_o;
+    output [11:0] fabric_llpp1_arid_s_o;
+    output [7:0] fabric_llpp1_arlen_s_o;
+    output fabric_llpp1_arlock_s_o;
+    output [2:0] fabric_llpp1_arprot_s_o;
+    output [3:0] fabric_llpp1_arqos_s1_o;
+    input fabric_llpp1_arready_s_i;
+    output [2:0] fabric_llpp1_arsize_s_o;
+    output fabric_llpp1_arvalid_s_o;
+    output [31:0] fabric_llpp1_awaddr_s_o;
+    output [1:0] fabric_llpp1_awburst_s_o;
+    output [3:0] fabric_llpp1_awcache_s_o;
+    output [11:0] fabric_llpp1_awid_s_o;
+    output [7:0] fabric_llpp1_awlen_s_o;
+    output fabric_llpp1_awlock_s_o;
+    output [2:0] fabric_llpp1_awprot_s_o;
+    output [3:0] fabric_llpp1_awqos_s_o;
+    input fabric_llpp1_awready_s_i;
+    output [2:0] fabric_llpp1_awsize_s_o;
+    output fabric_llpp1_awvalid_s_o;
+    input [11:0] fabric_llpp1_bid_s_i;
+    output fabric_llpp1_bready_s_o;
+    input [1:0] fabric_llpp1_bresp_s_i;
+    input fabric_llpp1_bvalid_s_i;
+    input [31:0] fabric_llpp1_rdata_s_i;
+    input [11:0] fabric_llpp1_rid_s_i;
+    input fabric_llpp1_rlast_s_i;
+    output fabric_llpp1_rready_s_o;
+    input [1:0] fabric_llpp1_rresp_s_i;
+    input fabric_llpp1_rvalid_s_i;
+    output [31:0] fabric_llpp1_wdata_s_o;
+    output fabric_llpp1_wlast_s_o;
+    input fabric_llpp1_wready_s_i;
+    output [3:0] fabric_llpp1_wstrb_s_o;
+    output fabric_llpp1_wvalid_s_o;
+    output [31:0] fabric_llpp2_araddr_s_o;
+    output [1:0] fabric_llpp2_arburst_s_o;
+    output [3:0] fabric_llpp2_arcache_s_o;
+    output [11:0] fabric_llpp2_arid_s_o;
+    output [7:0] fabric_llpp2_arlen_s_o;
+    output fabric_llpp2_arlock_s_o;
+    output [2:0] fabric_llpp2_arprot_s_o;
+    output [3:0] fabric_llpp2_arqos_s_o;
+    input fabric_llpp2_arready_s_i;
+    output [2:0] fabric_llpp2_arsize_s_o;
+    output fabric_llpp2_arvalid_s_o;
+    output [31:0] fabric_llpp2_awaddr_s_o;
+    output [1:0] fabric_llpp2_awburst_s_o;
+    output [3:0] fabric_llpp2_awcache_s_o;
+    output [11:0] fabric_llpp2_awid_s_o;
+    output [7:0] fabric_llpp2_awlen_s_o;
+    output fabric_llpp2_awlock_s_o;
+    output [2:0] fabric_llpp2_awprot_s_o;
+    output [3:0] fabric_llpp2_awqos_s_o;
+    input fabric_llpp2_awready_s_i;
+    output [2:0] fabric_llpp2_awsize_s_o;
+    output fabric_llpp2_awvalid_s_o;
+    input [11:0] fabric_llpp2_bid_s_i;
+    output fabric_llpp2_bready_s_o;
+    input [1:0] fabric_llpp2_bresp_s_i;
+    input fabric_llpp2_bvalid_s_i;
+    input [31:0] fabric_llpp2_rdata_s_i;
+    input [11:0] fabric_llpp2_rid_s_i;
+    input fabric_llpp2_rlast_s_i;
+    output fabric_llpp2_rready_s_o;
+    input [1:0] fabric_llpp2_rresp_s_i;
+    input fabric_llpp2_rvalid_s_i;
+    output [31:0] fabric_llpp2_wdata_s_o;
+    output fabric_llpp2_wlast_s_o;
+    input fabric_llpp2_wready_s_i;
+    output [3:0] fabric_llpp2_wstrb_s_o;
+    output fabric_llpp2_wvalid_s_o;
+    output [31:0] fabric_llpp3_araddr_s_o;
+    output [1:0] fabric_llpp3_arburst_s_o;
+    output [3:0] fabric_llpp3_arcache_s_o;
+    output [11:0] fabric_llpp3_arid_s_o;
+    output [7:0] fabric_llpp3_arlen_s_o;
+    output fabric_llpp3_arlock_s_o;
+    output [2:0] fabric_llpp3_arprot_s_o;
+    output [3:0] fabric_llpp3_arqos_s_o;
+    input fabric_llpp3_arready_s_i;
+    output [2:0] fabric_llpp3_arsize_s_o;
+    output fabric_llpp3_arvalid_s_o;
+    output [31:0] fabric_llpp3_awaddr_s_o;
+    output [1:0] fabric_llpp3_awburst_s_o;
+    output [3:0] fabric_llpp3_awcache_s_o;
+    output [11:0] fabric_llpp3_awid_s_o;
+    output [7:0] fabric_llpp3_awlen_s_o;
+    output fabric_llpp3_awlock_s_o;
+    output [2:0] fabric_llpp3_awprot_s_o;
+    output [3:0] fabric_llpp3_awqos_s_o;
+    input fabric_llpp3_awready_s_i;
+    output [2:0] fabric_llpp3_awsize_s_o;
+    output fabric_llpp3_awvalid_s_o;
+    input [11:0] fabric_llpp3_bid_s_i;
+    output fabric_llpp3_bready_s_o;
+    input [1:0] fabric_llpp3_bresp_s_i;
+    input fabric_llpp3_bvalid_s_i;
+    input [31:0] fabric_llpp3_rdata_s_i;
+    input [11:0] fabric_llpp3_rid_s_i;
+    input fabric_llpp3_rlast_s_i;
+    output fabric_llpp3_rready_s_o;
+    input [1:0] fabric_llpp3_rresp_s_i;
+    input fabric_llpp3_rvalid_s_i;
+    output [31:0] fabric_llpp3_wdata_s_o;
+    output fabric_llpp3_wlast_s_o;
+    input fabric_llpp3_wready_s_i;
+    output [3:0] fabric_llpp3_wstrb_s_o;
+    output fabric_llpp3_wvalid_s_o;
+    input [9:0] fabric_lowskew_i;
+    output [1:0] fabric_lowskew_o;
+    input fabric_qos_pclk_i;
+    input [31:0] fabric_qos_ppaddr_i;
+    input fabric_qos_ppenable_i;
+    output [31:0] fabric_qos_pprdata_o;
+    output fabric_qos_ppready_o;
+    output fabric_qos_ppslverr_o;
+    input [31:0] fabric_qos_ppwdata_i;
+    input fabric_qos_ppwrite_i;
+    input fabric_qos_presetn_i;
+    input fabric_qos_psel_i;
+    output fabric_soc_mon_sensor_alarm_o;
+    input fabric_sysc_hold_on_debug_i;
+    output [31:0] fabric_tnd_fpga_apb_master_paddr_o;
+    output fabric_tnd_fpga_apb_master_penable_o;
+    input [31:0] fabric_tnd_fpga_apb_master_prdata_i;
+    input fabric_tnd_fpga_apb_master_pready_i;
+    output fabric_tnd_fpga_apb_master_psel_o;
+    input fabric_tnd_fpga_apb_master_pslverr_i;
+    output [31:0] fabric_tnd_fpga_apb_master_pwdata_o;
+    output fabric_tnd_fpga_apb_master_pwrite_o;
+    input fabric_tnd_fpga_atb_master_afready_i;
+    output fabric_tnd_fpga_atb_master_afvalid_o;
+    input [3:0] fabric_tnd_fpga_atb_master_atbytes_i;
+    input [127:0] fabric_tnd_fpga_atb_master_atdata_i;
+    input [6:0] fabric_tnd_fpga_atb_master_atid_i;
+    output fabric_tnd_fpga_atb_master_atready_o;
+    input fabric_tnd_fpga_atb_master_atvalid_i;
+    output fabric_tnd_fpga_atb_master_syncreq_o;
+    output [31:0] fabric_tnd_hssl_apb_master_paddr_o;
+    output fabric_tnd_hssl_apb_master_penable_o;
+    input [31:0] fabric_tnd_hssl_apb_master_prdata_i;
+    input fabric_tnd_hssl_apb_master_pready_i;
+    output fabric_tnd_hssl_apb_master_psel_o;
+    input fabric_tnd_hssl_apb_master_pslverr_i;
+    output [31:0] fabric_tnd_hssl_apb_master_pwdata_o;
+    output fabric_tnd_hssl_apb_master_pwrite_o;
+    output fabric_tnd_hssl_atb_master_afready_o;
+    input fabric_tnd_hssl_atb_master_afvalid_i;
+    output [3:0] fabric_tnd_hssl_atb_master_atbytes_o;
+    output [127:0] fabric_tnd_hssl_atb_master_atdata_o;
+    output [6:0] fabric_tnd_hssl_atb_master_atid_o;
+    input fabric_tnd_hssl_atb_master_atready_i;
+    output fabric_tnd_hssl_atb_master_atvalid_o;
+    input fabric_tnd_hssl_atb_master_syncreq_i;
+    output fabric_tnd_hssl_flushin_o;
+    output fabric_tnd_hssl_trigin_o;
+    output fabric_tnd_trace_clk_traceoutportintf_o;
+    output fabric_tnd_trace_ctl_traceoutportintf_o;
+    output [31:0] fabric_tnd_trace_data_traceoutportintf_o;
+    output [6:0] fabric_tst_pll_lock_o;
+    output [63:0] fabric_tsvalue_tsgen_fpga_o;
+    output fabric_watchdog0_signal_0_o;
+    output fabric_watchdog0_signal_1_o;
+    output fabric_watchdog1_signal_0_o;
+    output fabric_watchdog1_signal_1_o;
+    output fabric_watchdog2_signal_0_o;
+    output fabric_watchdog2_signal_1_o;
+    output fabric_watchdog3_signal_0_o;
+    output fabric_watchdog3_signal_1_o;
+    parameter ahb_config = 0;
+    parameter bsm_config = 0;
+endmodule
+
+(* blackbox *)
+module NX_SOC_INTERFACE_WRAP(fabric_fpga_pmrstn_i, fabric_fpga_sysrstn_i, fabric_sysc_hold_on_debug_i, fabric_fpga_arlock_axi_s1_o, fabric_fpga_arvalid_axi_s1_o, fabric_fpga_awlock_axi_s1_o, fabric_fpga_bready_axi_s1_o, fabric_fpga_rready_axi_s1_o, fabric_fpga_wlast_axi_s1_o, fabric_fpga_wvalid_axi_s1_o, fabric_fpga_awvalid_axi_s1_o, fabric_fpga_arready_axi_s1_i, fabric_fpga_awready_axi_s1_i, fabric_fpga_bvalid_axi_s1_i, fabric_fpga_rlast_axi_s1_i, fabric_fpga_rvalid_axi_s1_i, fabric_fpga_wready_axi_s1_i, fabric_fpga_arlock_axi_s2_o, fabric_fpga_arvalid_axi_s2_o, fabric_fpga_awlock_axi_s2_o, fabric_fpga_bready_axi_s2_o
+, fabric_fpga_rready_axi_s2_o, fabric_fpga_wlast_axi_s2_o, fabric_fpga_wvalid_axi_s2_o, fabric_fpga_awvalid_axi_s2_o, fabric_fpga_arready_axi_s2_i, fabric_fpga_awready_axi_s2_i, fabric_fpga_bvalid_axi_s2_i, fabric_fpga_rlast_axi_s2_i, fabric_fpga_rvalid_axi_s2_i, fabric_fpga_wready_axi_s2_i, fabric_fpga_arready_axi_m1_o, fabric_fpga_awready_axi_m1_o, fabric_fpga_bvalid_axi_m1_o, fabric_fpga_rlast_axi_m1_o, fabric_fpga_rvalid_axi_m1_o, fabric_fpga_wready_axi_m1_o, fabric_fpga_arlock_axi_m1_i, fabric_fpga_arvalid_axi_m1_i, fabric_fpga_awlock_axi_m1_i, fabric_fpga_awvalid_axi_m1_i, fabric_fpga_bready_axi_m1_i
+, fabric_fpga_rready_axi_m1_i, fabric_fpga_wlast_axi_m1_i, fabric_fpga_wvalid_axi_m1_i, fabric_fpga_arready_axi_m2_o, fabric_fpga_awready_axi_m2_o, fabric_fpga_bvalid_axi_m2_o, fabric_fpga_rlast_axi_m2_o, fabric_fpga_rvalid_axi_m2_o, fabric_fpga_wready_axi_m2_o, fabric_fpga_arlock_axi_m2_i, fabric_fpga_arvalid_axi_m2_i, fabric_fpga_awlock_axi_m2_i, fabric_fpga_awvalid_axi_m2_i, fabric_fpga_bready_axi_m2_i, fabric_fpga_rready_axi_m2_i, fabric_fpga_wlast_axi_m2_i, fabric_fpga_wvalid_axi_m2_i, fabric_fpga_ddr0_arready_o, fabric_fpga_ddr0_awready_o, fabric_fpga_ddr0_bvalid_o, fabric_fpga_ddr0_rlast_o
+, fabric_fpga_ddr0_rvalid_o, fabric_fpga_ddr0_wready_o, fabric_fpga_ddr0_arlock_i, fabric_fpga_ddr0_arvalid_i, fabric_fpga_ddr0_awlock_i, fabric_fpga_ddr0_awvalid_i, fabric_fpga_ddr0_bready_i, fabric_fpga_ddr0_rready_i, fabric_fpga_ddr0_wlast_i, fabric_fpga_ddr0_wvalid_i, fabric_fpga_penable_apb_o, fabric_fpga_psel_apb_o, fabric_fpga_pwrite_apb_o, fabric_fpga_pready_apb_i, fabric_fpga_pslverr_apb_i, fabric_llpp0_arlock_s_o, fabric_llpp0_arvalid_s_o, fabric_llpp0_awlock_s_o, fabric_llpp0_awvalid_s_o, fabric_llpp0_bready_s_o, fabric_llpp0_rready_s_o
+, fabric_llpp0_wlast_s_o, fabric_llpp0_wvalid_s_o, fabric_llpp0_arready_s_i, fabric_llpp0_awready_s_i, fabric_llpp0_bvalid_s_i, fabric_llpp0_rlast_s_i, fabric_llpp0_rvalid_s_i, fabric_llpp0_wready_s_i, fabric_llpp1_arlock_s_o, fabric_llpp1_arvalid_s_o, fabric_llpp1_awlock_s_o, fabric_llpp1_awvalid_s_o, fabric_llpp1_bready_s_o, fabric_llpp1_rready_s_o, fabric_llpp1_wlast_s_o, fabric_llpp1_wvalid_s_o, fabric_llpp1_arready_s_i, fabric_llpp1_awready_s_i, fabric_llpp1_bvalid_s_i, fabric_llpp1_rlast_s_i, fabric_llpp1_rvalid_s_i
+, fabric_llpp1_wready_s_i, fabric_llpp2_arlock_s_o, fabric_llpp2_arvalid_s_o, fabric_llpp2_awlock_s_o, fabric_llpp2_awvalid_s_o, fabric_llpp2_bready_s_o, fabric_llpp2_rready_s_o, fabric_llpp2_wlast_s_o, fabric_llpp2_wvalid_s_o, fabric_llpp2_arready_s_i, fabric_llpp2_awready_s_i, fabric_llpp2_bvalid_s_i, fabric_llpp2_rlast_s_i, fabric_llpp2_rvalid_s_i, fabric_llpp2_wready_s_i, fabric_llpp3_arlock_s_o, fabric_llpp3_arvalid_s_o, fabric_llpp3_awlock_s_o, fabric_llpp3_awvalid_s_o, fabric_llpp3_bready_s_o, fabric_llpp3_rready_s_o
+, fabric_llpp3_wlast_s_o, fabric_llpp3_wvalid_s_o, fabric_llpp3_arready_s_i, fabric_llpp3_awready_s_i, fabric_llpp3_bvalid_s_i, fabric_llpp3_rlast_s_i, fabric_llpp3_rvalid_s_i, fabric_llpp3_wready_s_i, fabric_qos_ppready_o, fabric_qos_ppslverr_o, fabric_qos_ppenable_i, fabric_qos_ppwrite_i, fabric_qos_presetn_i, fabric_qos_psel_i, fabric_tnd_hssl_flushin_o, fabric_tnd_hssl_trigin_o, fabric_tnd_fpga_apb_master_penable_o, fabric_tnd_fpga_apb_master_psel_o, fabric_tnd_fpga_apb_master_pwrite_o, fabric_tnd_fpga_atb_master_afvalid_o, fabric_tnd_fpga_atb_master_atready_o
+, fabric_tnd_fpga_atb_master_syncreq_o, fabric_tnd_hssl_apb_master_penable_o, fabric_tnd_hssl_apb_master_psel_o, fabric_tnd_hssl_apb_master_pwrite_o, fabric_tnd_hssl_atb_master_afready_o, fabric_tnd_hssl_atb_master_atvalid_o, fabric_tnd_trace_clk_traceoutportintf_o, fabric_tnd_trace_ctl_traceoutportintf_o, fabric_tnd_fpga_apb_master_pready_i, fabric_tnd_fpga_apb_master_pslverr_i, fabric_tnd_fpga_atb_master_afready_i, fabric_tnd_fpga_atb_master_atvalid_i, fabric_tnd_hssl_apb_master_pready_i, fabric_tnd_hssl_apb_master_pslverr_i, fabric_tnd_hssl_atb_master_afvalid_i, fabric_tnd_hssl_atb_master_atready_i, fabric_tnd_hssl_atb_master_syncreq_i, fabric_watchdog0_signal_0_o, fabric_watchdog0_signal_1_o, fabric_watchdog1_signal_0_o, fabric_watchdog1_signal_1_o
+, fabric_watchdog2_signal_0_o, fabric_watchdog2_signal_1_o, fabric_watchdog3_signal_0_o, fabric_watchdog3_signal_1_o, fabric_soc_mon_sensor_alarm_o, fabric_erom_fpga_cpu0_dbgen_i, fabric_erom_fpga_cpu0_hiden_i, fabric_erom_fpga_cpu0_hniden_i, fabric_erom_fpga_cpu0_niden_i, fabric_erom_fpga_cpu1_dbgen_i, fabric_erom_fpga_cpu1_hiden_i, fabric_erom_fpga_cpu1_hniden_i, fabric_erom_fpga_cpu1_niden_i, fabric_erom_fpga_cpu2_dbgen_i, fabric_erom_fpga_cpu2_hiden_i, fabric_erom_fpga_cpu2_hniden_i, fabric_erom_fpga_cpu2_niden_i, fabric_erom_fpga_cpu3_dbgen_i, fabric_erom_fpga_cpu3_hiden_i, fabric_erom_fpga_cpu3_hniden_i, fabric_erom_fpga_cpu3_niden_i
+, fabric_erom_fpga_cs_dbgen_i, fabric_erom_fpga_cs_niden_i, fabric_erom_fpga_cs_deviceen_i, fabric_erom_fpga_cs_rst_n_i, fabric_erom_fpga_debug_en_i, fabric_flash_irq_toggle_o, fabric_flash_irq_o, fabric_enable_TMR_i, fabric_lowskew_i, fabric_lowskew_o, fabric_fpga_nic_rstn_i, fabric_fpga_trigger_in_o, fabric_fpga_trigger_out_i, fabric_fpga_interrupt_in_i, fabric_fpga_events60_i, fabric_fpga_araddr_axi_s1_o, fabric_fpga_arburst_axi_s1_o, fabric_fpga_arcache_axi_s1_o, fabric_fpga_arid_axi_s1_o, fabric_fpga_arlen_axi_s1_o, fabric_fpga_arprot_axi_s1_o
+, fabric_fpga_arqos_axi_s1_o, fabric_fpga_arregion_axi_s1_o, fabric_fpga_arsize_axi_s1_o, fabric_fpga_awaddr_axi_s1_o, fabric_fpga_awburst_axi_s1_o, fabric_fpga_awcache_axi_s1_o, fabric_fpga_awid_axi_s1_o, fabric_fpga_awlen_axi_s1_o, fabric_fpga_awprot_axi_s1_o, fabric_fpga_awqos_axi_s1_o, fabric_fpga_awregion_axi_s1_o, fabric_fpga_awsize_axi_s1_o, fabric_fpga_wdata_axi_s1_o, fabric_fpga_wstrb_axi_s1_o, fabric_fpga_bid_axi_s1_i, fabric_fpga_bresp_axi_s1_i, fabric_fpga_rdata_axi_s1_i, fabric_fpga_rid_axi_s1_i, fabric_fpga_rresp_axi_s1_i, fabric_fpga_araddr_axi_s2_o, fabric_fpga_arburst_axi_s2_o
+, fabric_fpga_arcache_axi_s2_o, fabric_fpga_arid_axi_s2_o, fabric_fpga_arlen_axi_s2_o, fabric_fpga_arprot_axi_s2_o, fabric_fpga_arqos_axi_s2_o, fabric_fpga_arregion_axi_s2_o, fabric_fpga_arsize_axi_s2_o, fabric_fpga_awaddr_axi_s2_o, fabric_fpga_awburst_axi_s2_o, fabric_fpga_awcache_axi_s2_o, fabric_fpga_awid_axi_s2_o, fabric_fpga_awlen_axi_s2_o, fabric_fpga_awprot_axi_s2_o, fabric_fpga_awqos_axi_s2_o, fabric_fpga_awregion_axi_s2_o, fabric_fpga_awsize_axi_s2_o, fabric_fpga_wdata_axi_s2_o, fabric_fpga_wstrb_axi_s2_o, fabric_fpga_bid_axi_s2_i, fabric_fpga_bresp_axi_s2_i, fabric_fpga_rdata_axi_s2_i
+, fabric_fpga_rid_axi_s2_i, fabric_fpga_rresp_axi_s2_i, fabric_fpga_bid_axi_m1_o, fabric_fpga_bresp_axi_m1_o, fabric_fpga_dma_ack_m1_o, fabric_fpga_dma_finish_m1_o, fabric_fpga_rdata_axi_m1_o, fabric_fpga_rid_axi_m1_o, fabric_fpga_rresp_axi_m1_o, fabric_fpga_araddr_axi_m1_i, fabric_fpga_arburst_axi_m1_i, fabric_fpga_arcache_axi_m1_i, fabric_fpga_arid_axi_m1_i, fabric_fpga_arlen_axi_m1_i, fabric_fpga_arprot_axi_m1_i, fabric_fpga_arqos_axi_m1_i, fabric_fpga_arsize_axi_m1_i, fabric_fpga_awaddr_axi_m1_i, fabric_fpga_awburst_axi_m1_i, fabric_fpga_awcache_axi_m1_i, fabric_fpga_awid_axi_m1_i
+, fabric_fpga_awlen_axi_m1_i, fabric_fpga_awprot_axi_m1_i, fabric_fpga_awqos_axi_m1_i, fabric_fpga_awsize_axi_m1_i, fabric_fpga_dma_last_m1_i, fabric_fpga_dma_req_m1_i, fabric_fpga_dma_single_m1_i, fabric_fpga_wdata_axi_m1_i, fabric_fpga_wstrb_axi_m1_i, fabric_fpga_bid_axi_m2_o, fabric_fpga_bresp_axi_m2_o, fabric_fpga_dma_ack_m2_o, fabric_fpga_dma_finish_m2_o, fabric_fpga_rdata_axi_m2_o, fabric_fpga_rid_axi_m2_o, fabric_fpga_rresp_axi_m2_o, fabric_fpga_araddr_axi_m2_i, fabric_fpga_arburst_axi_m2_i, fabric_fpga_arcache_axi_m2_i, fabric_fpga_arid_axi_m2_i, fabric_fpga_arlen_axi_m2_i
+, fabric_fpga_arprot_axi_m2_i, fabric_fpga_arqos_axi_m2_i, fabric_fpga_arsize_axi_m2_i, fabric_fpga_awaddr_axi_m2_i, fabric_fpga_awburst_axi_m2_i, fabric_fpga_awcache_axi_m2_i, fabric_fpga_awid_axi_m2_i, fabric_fpga_awlen_axi_m2_i, fabric_fpga_awprot_axi_m2_i, fabric_fpga_awqos_axi_m2_i, fabric_fpga_awsize_axi_m2_i, fabric_fpga_dma_last_m2_i, fabric_fpga_dma_req_m2_i, fabric_fpga_dma_single_m2_i, fabric_fpga_wdata_axi_m2_i, fabric_fpga_wstrb_axi_m2_i, fabric_fpga_ddr0_bid_o, fabric_fpga_ddr0_bresp_o, fabric_fpga_ddr0_rdata_o, fabric_fpga_ddr0_rid_o, fabric_fpga_ddr0_rresp_o
+, fabric_fpga_ddr0_araddr_i, fabric_fpga_ddr0_arburst_i, fabric_fpga_ddr0_arcache_i, fabric_fpga_ddr0_arid_i, fabric_fpga_ddr0_arlen_i, fabric_fpga_ddr0_arprot_i, fabric_fpga_ddr0_arqos_i, fabric_fpga_ddr0_arsize_i, fabric_fpga_ddr0_awaddr_i, fabric_fpga_ddr0_awburst_i, fabric_fpga_ddr0_awcache_i, fabric_fpga_ddr0_awid_i, fabric_fpga_ddr0_awlen_i, fabric_fpga_ddr0_awprot_i, fabric_fpga_ddr0_awqos_i, fabric_fpga_ddr0_awsize_i, fabric_fpga_ddr0_wdata_i, fabric_fpga_ddr0_wstrb_i, fabric_fpga_paddr_apb_o, fabric_fpga_pwdata_apb_o, fabric_fpga_prdata_apb_i
+, fabric_llpp0_araddr_s_o, fabric_llpp0_arburst_s_o, fabric_llpp0_arcache_s_o, fabric_llpp0_arid_s_o, fabric_llpp0_arlen_s_o, fabric_llpp0_arprot_s_o, fabric_llpp0_arqos_s_o, fabric_llpp0_arsize_s_o, fabric_llpp0_awaddr_s_o, fabric_llpp0_awburst_s_o, fabric_llpp0_awcache_s_o, fabric_llpp0_awid_s_o, fabric_llpp0_awlen_s_o, fabric_llpp0_awprot_s_o, fabric_llpp0_awqos_s_o, fabric_llpp0_awsize_s_o, fabric_llpp0_wdata_s_o, fabric_llpp0_wstrb_s_o, fabric_llpp0_bid_s_i, fabric_llpp0_bresp_s_i, fabric_llpp0_rdata_s_i
+, fabric_llpp0_rid_s_i, fabric_llpp0_rresp_s_i, fabric_llpp1_araddr_s_o, fabric_llpp1_arburst_s_o, fabric_llpp1_arcache_s_o, fabric_llpp1_arid_s_o, fabric_llpp1_arlen_s_o, fabric_llpp1_arprot_s_o, fabric_llpp1_arsize_s_o, fabric_llpp1_awaddr_s_o, fabric_llpp1_awburst_s_o, fabric_llpp1_awcache_s_o, fabric_llpp1_awid_s_o, fabric_llpp1_awlen_s_o, fabric_llpp1_awprot_s_o, fabric_llpp1_awqos_s_o, fabric_llpp1_awsize_s_o, fabric_llpp1_wdata_s_o, fabric_llpp1_wstrb_s_o, fabric_llpp1_bid_s_i, fabric_llpp1_bresp_s_i
+, fabric_llpp1_rdata_s_i, fabric_llpp1_rid_s_i, fabric_llpp1_rresp_s_i, fabric_llpp2_araddr_s_o, fabric_llpp2_arburst_s_o, fabric_llpp2_arcache_s_o, fabric_llpp2_arid_s_o, fabric_llpp2_arlen_s_o, fabric_llpp2_arprot_s_o, fabric_llpp2_arqos_s_o, fabric_llpp2_arsize_s_o, fabric_llpp2_awaddr_s_o, fabric_llpp2_awburst_s_o, fabric_llpp2_awcache_s_o, fabric_llpp2_awid_s_o, fabric_llpp2_awlen_s_o, fabric_llpp2_awprot_s_o, fabric_llpp2_awqos_s_o, fabric_llpp2_awsize_s_o, fabric_llpp2_wdata_s_o, fabric_llpp2_wstrb_s_o
+, fabric_llpp2_bid_s_i, fabric_llpp2_bresp_s_i, fabric_llpp2_rdata_s_i, fabric_llpp2_rid_s_i, fabric_llpp2_rresp_s_i, fabric_llpp3_araddr_s_o, fabric_llpp3_arburst_s_o, fabric_llpp3_arcache_s_o, fabric_llpp3_arid_s_o, fabric_llpp3_arlen_s_o, fabric_llpp3_arprot_s_o, fabric_llpp3_arqos_s_o, fabric_llpp3_arsize_s_o, fabric_llpp3_awaddr_s_o, fabric_llpp3_awburst_s_o, fabric_llpp3_awcache_s_o, fabric_llpp3_awid_s_o, fabric_llpp3_awlen_s_o, fabric_llpp3_awprot_s_o, fabric_llpp3_awqos_s_o, fabric_llpp3_awsize_s_o
+, fabric_llpp3_wdata_s_o, fabric_llpp3_wstrb_s_o, fabric_llpp3_bid_s_i, fabric_llpp3_bresp_s_i, fabric_llpp3_rdata_s_i, fabric_llpp3_rid_s_i, fabric_llpp3_rresp_s_i, fabric_qos_pprdata_o, fabric_qos_ppaddr_i, fabric_qos_ppwdata_i, fabric_tnd_fpga_apb_master_paddr_o, fabric_tnd_fpga_apb_master_pwdata_o, fabric_tnd_hssl_apb_master_paddr_o, fabric_tnd_hssl_apb_master_pwdata_o, fabric_tnd_hssl_atb_master_atbytes_o, fabric_tnd_hssl_atb_master_atdata_o, fabric_tnd_hssl_atb_master_atid_o, fabric_tnd_trace_data_traceoutportintf_o, fabric_tsvalue_tsgen_fpga_o, fabric_tnd_fpga_apb_master_prdata_i, fabric_tnd_fpga_atb_master_atbytes_i
+, fabric_tnd_fpga_atb_master_atdata_i, fabric_tnd_fpga_atb_master_atid_i, fabric_tnd_hssl_apb_master_prdata_i, fabric_tst_pll_lock_o, fabric_llpp1_arqos_s_o, fabric_spw_interrupts_toggle_o, fabric_spw_interrupts_o, fabric_fpga_dma_hs_rstn_i);
+    input [2:0] fabric_enable_TMR_i;
+    input fabric_erom_fpga_cpu0_dbgen_i;
+    input fabric_erom_fpga_cpu0_hiden_i;
+    input fabric_erom_fpga_cpu0_hniden_i;
+    input fabric_erom_fpga_cpu0_niden_i;
+    input fabric_erom_fpga_cpu1_dbgen_i;
+    input fabric_erom_fpga_cpu1_hiden_i;
+    input fabric_erom_fpga_cpu1_hniden_i;
+    input fabric_erom_fpga_cpu1_niden_i;
+    input fabric_erom_fpga_cpu2_dbgen_i;
+    input fabric_erom_fpga_cpu2_hiden_i;
+    input fabric_erom_fpga_cpu2_hniden_i;
+    input fabric_erom_fpga_cpu2_niden_i;
+    input fabric_erom_fpga_cpu3_dbgen_i;
+    input fabric_erom_fpga_cpu3_hiden_i;
+    input fabric_erom_fpga_cpu3_hniden_i;
+    input fabric_erom_fpga_cpu3_niden_i;
+    input fabric_erom_fpga_cs_dbgen_i;
+    input fabric_erom_fpga_cs_deviceen_i;
+    input fabric_erom_fpga_cs_niden_i;
+    input fabric_erom_fpga_cs_rst_n_i;
+    input fabric_erom_fpga_debug_en_i;
+    output fabric_flash_irq_o;
+    output fabric_flash_irq_toggle_o;
+    input [39:0] fabric_fpga_araddr_axi_m1_i;
+    input [39:0] fabric_fpga_araddr_axi_m2_i;
+    output [39:0] fabric_fpga_araddr_axi_s1_o;
+    output [39:0] fabric_fpga_araddr_axi_s2_o;
+    input [1:0] fabric_fpga_arburst_axi_m1_i;
+    input [1:0] fabric_fpga_arburst_axi_m2_i;
+    output [1:0] fabric_fpga_arburst_axi_s1_o;
+    output [1:0] fabric_fpga_arburst_axi_s2_o;
+    input [3:0] fabric_fpga_arcache_axi_m1_i;
+    input [3:0] fabric_fpga_arcache_axi_m2_i;
+    output [3:0] fabric_fpga_arcache_axi_s1_o;
+    output [3:0] fabric_fpga_arcache_axi_s2_o;
+    input [4:0] fabric_fpga_arid_axi_m1_i;
+    input [4:0] fabric_fpga_arid_axi_m2_i;
+    output [11:0] fabric_fpga_arid_axi_s1_o;
+    output [11:0] fabric_fpga_arid_axi_s2_o;
+    input [7:0] fabric_fpga_arlen_axi_m1_i;
+    input [7:0] fabric_fpga_arlen_axi_m2_i;
+    output [7:0] fabric_fpga_arlen_axi_s1_o;
+    output [7:0] fabric_fpga_arlen_axi_s2_o;
+    input fabric_fpga_arlock_axi_m1_i;
+    input fabric_fpga_arlock_axi_m2_i;
+    output fabric_fpga_arlock_axi_s1_o;
+    output fabric_fpga_arlock_axi_s2_o;
+    input [2:0] fabric_fpga_arprot_axi_m1_i;
+    input [2:0] fabric_fpga_arprot_axi_m2_i;
+    output [2:0] fabric_fpga_arprot_axi_s1_o;
+    output [2:0] fabric_fpga_arprot_axi_s2_o;
+    input [3:0] fabric_fpga_arqos_axi_m1_i;
+    input [3:0] fabric_fpga_arqos_axi_m2_i;
+    output [3:0] fabric_fpga_arqos_axi_s1_o;
+    output [3:0] fabric_fpga_arqos_axi_s2_o;
+    output fabric_fpga_arready_axi_m1_o;
+    output fabric_fpga_arready_axi_m2_o;
+    input fabric_fpga_arready_axi_s1_i;
+    input fabric_fpga_arready_axi_s2_i;
+    output [3:0] fabric_fpga_arregion_axi_s1_o;
+    output [3:0] fabric_fpga_arregion_axi_s2_o;
+    input [2:0] fabric_fpga_arsize_axi_m1_i;
+    input [2:0] fabric_fpga_arsize_axi_m2_i;
+    output [2:0] fabric_fpga_arsize_axi_s1_o;
+    output [2:0] fabric_fpga_arsize_axi_s2_o;
+    input fabric_fpga_arvalid_axi_m1_i;
+    input fabric_fpga_arvalid_axi_m2_i;
+    output fabric_fpga_arvalid_axi_s1_o;
+    output fabric_fpga_arvalid_axi_s2_o;
+    input [39:0] fabric_fpga_awaddr_axi_m1_i;
+    input [39:0] fabric_fpga_awaddr_axi_m2_i;
+    output [39:0] fabric_fpga_awaddr_axi_s1_o;
+    output [39:0] fabric_fpga_awaddr_axi_s2_o;
+    input [1:0] fabric_fpga_awburst_axi_m1_i;
+    input [1:0] fabric_fpga_awburst_axi_m2_i;
+    output [1:0] fabric_fpga_awburst_axi_s1_o;
+    output [1:0] fabric_fpga_awburst_axi_s2_o;
+    input [3:0] fabric_fpga_awcache_axi_m1_i;
+    input [3:0] fabric_fpga_awcache_axi_m2_i;
+    output [3:0] fabric_fpga_awcache_axi_s1_o;
+    output [3:0] fabric_fpga_awcache_axi_s2_o;
+    input [4:0] fabric_fpga_awid_axi_m1_i;
+    input [4:0] fabric_fpga_awid_axi_m2_i;
+    output [11:0] fabric_fpga_awid_axi_s1_o;
+    output [11:0] fabric_fpga_awid_axi_s2_o;
+    input [7:0] fabric_fpga_awlen_axi_m1_i;
+    input [7:0] fabric_fpga_awlen_axi_m2_i;
+    output [7:0] fabric_fpga_awlen_axi_s1_o;
+    output [7:0] fabric_fpga_awlen_axi_s2_o;
+    input fabric_fpga_awlock_axi_m1_i;
+    input fabric_fpga_awlock_axi_m2_i;
+    output fabric_fpga_awlock_axi_s1_o;
+    output fabric_fpga_awlock_axi_s2_o;
+    input [2:0] fabric_fpga_awprot_axi_m1_i;
+    input [2:0] fabric_fpga_awprot_axi_m2_i;
+    output [2:0] fabric_fpga_awprot_axi_s1_o;
+    output [2:0] fabric_fpga_awprot_axi_s2_o;
+    input [3:0] fabric_fpga_awqos_axi_m1_i;
+    input [3:0] fabric_fpga_awqos_axi_m2_i;
+    output [3:0] fabric_fpga_awqos_axi_s1_o;
+    output [3:0] fabric_fpga_awqos_axi_s2_o;
+    output fabric_fpga_awready_axi_m1_o;
+    output fabric_fpga_awready_axi_m2_o;
+    input fabric_fpga_awready_axi_s1_i;
+    input fabric_fpga_awready_axi_s2_i;
+    output [3:0] fabric_fpga_awregion_axi_s1_o;
+    output [3:0] fabric_fpga_awregion_axi_s2_o;
+    input [2:0] fabric_fpga_awsize_axi_m1_i;
+    input [2:0] fabric_fpga_awsize_axi_m2_i;
+    output [2:0] fabric_fpga_awsize_axi_s1_o;
+    output [2:0] fabric_fpga_awsize_axi_s2_o;
+    input fabric_fpga_awvalid_axi_m1_i;
+    input fabric_fpga_awvalid_axi_m2_i;
+    output fabric_fpga_awvalid_axi_s1_o;
+    output fabric_fpga_awvalid_axi_s2_o;
+    output [4:0] fabric_fpga_bid_axi_m1_o;
+    output [4:0] fabric_fpga_bid_axi_m2_o;
+    input [11:0] fabric_fpga_bid_axi_s1_i;
+    input [11:0] fabric_fpga_bid_axi_s2_i;
+    input fabric_fpga_bready_axi_m1_i;
+    input fabric_fpga_bready_axi_m2_i;
+    output fabric_fpga_bready_axi_s1_o;
+    output fabric_fpga_bready_axi_s2_o;
+    output [1:0] fabric_fpga_bresp_axi_m1_o;
+    output [1:0] fabric_fpga_bresp_axi_m2_o;
+    input [1:0] fabric_fpga_bresp_axi_s1_i;
+    input [1:0] fabric_fpga_bresp_axi_s2_i;
+    output fabric_fpga_bvalid_axi_m1_o;
+    output fabric_fpga_bvalid_axi_m2_o;
+    input fabric_fpga_bvalid_axi_s1_i;
+    input fabric_fpga_bvalid_axi_s2_i;
+    input [39:0] fabric_fpga_ddr0_araddr_i;
+    input [1:0] fabric_fpga_ddr0_arburst_i;
+    input [3:0] fabric_fpga_ddr0_arcache_i;
+    input [4:0] fabric_fpga_ddr0_arid_i;
+    input [7:0] fabric_fpga_ddr0_arlen_i;
+    input fabric_fpga_ddr0_arlock_i;
+    input [2:0] fabric_fpga_ddr0_arprot_i;
+    input [3:0] fabric_fpga_ddr0_arqos_i;
+    output fabric_fpga_ddr0_arready_o;
+    input [2:0] fabric_fpga_ddr0_arsize_i;
+    input fabric_fpga_ddr0_arvalid_i;
+    input [39:0] fabric_fpga_ddr0_awaddr_i;
+    input [1:0] fabric_fpga_ddr0_awburst_i;
+    input [3:0] fabric_fpga_ddr0_awcache_i;
+    input [4:0] fabric_fpga_ddr0_awid_i;
+    input [7:0] fabric_fpga_ddr0_awlen_i;
+    input fabric_fpga_ddr0_awlock_i;
+    input [2:0] fabric_fpga_ddr0_awprot_i;
+    input [3:0] fabric_fpga_ddr0_awqos_i;
+    output fabric_fpga_ddr0_awready_o;
+    input [2:0] fabric_fpga_ddr0_awsize_i;
+    input fabric_fpga_ddr0_awvalid_i;
+    output [4:0] fabric_fpga_ddr0_bid_o;
+    input fabric_fpga_ddr0_bready_i;
+    output [1:0] fabric_fpga_ddr0_bresp_o;
+    output fabric_fpga_ddr0_bvalid_o;
+    output [127:0] fabric_fpga_ddr0_rdata_o;
+    output [4:0] fabric_fpga_ddr0_rid_o;
+    output fabric_fpga_ddr0_rlast_o;
+    input fabric_fpga_ddr0_rready_i;
+    output [1:0] fabric_fpga_ddr0_rresp_o;
+    output fabric_fpga_ddr0_rvalid_o;
+    input [127:0] fabric_fpga_ddr0_wdata_i;
+    input fabric_fpga_ddr0_wlast_i;
+    output fabric_fpga_ddr0_wready_o;
+    input [15:0] fabric_fpga_ddr0_wstrb_i;
+    input fabric_fpga_ddr0_wvalid_i;
+    output [5:0] fabric_fpga_dma_ack_m1_o;
+    output [5:0] fabric_fpga_dma_ack_m2_o;
+    output [5:0] fabric_fpga_dma_finish_m1_o;
+    output [5:0] fabric_fpga_dma_finish_m2_o;
+    input [5:0] fabric_fpga_dma_hs_rstn_i;
+    input [5:0] fabric_fpga_dma_last_m1_i;
+    input [5:0] fabric_fpga_dma_last_m2_i;
+    input [5:0] fabric_fpga_dma_req_m1_i;
+    input [5:0] fabric_fpga_dma_req_m2_i;
+    input [5:0] fabric_fpga_dma_single_m1_i;
+    input [5:0] fabric_fpga_dma_single_m2_i;
+    input [59:0] fabric_fpga_events60_i;
+    input [119:0] fabric_fpga_interrupt_in_i;
+    input [9:0] fabric_fpga_nic_rstn_i;
+    output [31:0] fabric_fpga_paddr_apb_o;
+    output fabric_fpga_penable_apb_o;
+    input fabric_fpga_pmrstn_i;
+    input [31:0] fabric_fpga_prdata_apb_i;
+    input fabric_fpga_pready_apb_i;
+    output fabric_fpga_psel_apb_o;
+    input fabric_fpga_pslverr_apb_i;
+    output [31:0] fabric_fpga_pwdata_apb_o;
+    output fabric_fpga_pwrite_apb_o;
+    output [127:0] fabric_fpga_rdata_axi_m1_o;
+    output [127:0] fabric_fpga_rdata_axi_m2_o;
+    input [127:0] fabric_fpga_rdata_axi_s1_i;
+    input [127:0] fabric_fpga_rdata_axi_s2_i;
+    output [4:0] fabric_fpga_rid_axi_m1_o;
+    output [4:0] fabric_fpga_rid_axi_m2_o;
+    input [11:0] fabric_fpga_rid_axi_s1_i;
+    input [11:0] fabric_fpga_rid_axi_s2_i;
+    output fabric_fpga_rlast_axi_m1_o;
+    output fabric_fpga_rlast_axi_m2_o;
+    input fabric_fpga_rlast_axi_s1_i;
+    input fabric_fpga_rlast_axi_s2_i;
+    input fabric_fpga_rready_axi_m1_i;
+    input fabric_fpga_rready_axi_m2_i;
+    output fabric_fpga_rready_axi_s1_o;
+    output fabric_fpga_rready_axi_s2_o;
+    output [1:0] fabric_fpga_rresp_axi_m1_o;
+    output [1:0] fabric_fpga_rresp_axi_m2_o;
+    input [1:0] fabric_fpga_rresp_axi_s1_i;
+    input [1:0] fabric_fpga_rresp_axi_s2_i;
+    output fabric_fpga_rvalid_axi_m1_o;
+    output fabric_fpga_rvalid_axi_m2_o;
+    input fabric_fpga_rvalid_axi_s1_i;
+    input fabric_fpga_rvalid_axi_s2_i;
+    input fabric_fpga_sysrstn_i;
+    output [7:0] fabric_fpga_trigger_in_o;
+    input [7:0] fabric_fpga_trigger_out_i;
+    input [127:0] fabric_fpga_wdata_axi_m1_i;
+    input [127:0] fabric_fpga_wdata_axi_m2_i;
+    output [127:0] fabric_fpga_wdata_axi_s1_o;
+    output [127:0] fabric_fpga_wdata_axi_s2_o;
+    input fabric_fpga_wlast_axi_m1_i;
+    input fabric_fpga_wlast_axi_m2_i;
+    output fabric_fpga_wlast_axi_s1_o;
+    output fabric_fpga_wlast_axi_s2_o;
+    output fabric_fpga_wready_axi_m1_o;
+    output fabric_fpga_wready_axi_m2_o;
+    input fabric_fpga_wready_axi_s1_i;
+    input fabric_fpga_wready_axi_s2_i;
+    input [15:0] fabric_fpga_wstrb_axi_m1_i;
+    input [15:0] fabric_fpga_wstrb_axi_m2_i;
+    output [15:0] fabric_fpga_wstrb_axi_s1_o;
+    output [15:0] fabric_fpga_wstrb_axi_s2_o;
+    input fabric_fpga_wvalid_axi_m1_i;
+    input fabric_fpga_wvalid_axi_m2_i;
+    output fabric_fpga_wvalid_axi_s1_o;
+    output fabric_fpga_wvalid_axi_s2_o;
+    output [31:0] fabric_llpp0_araddr_s_o;
+    output [1:0] fabric_llpp0_arburst_s_o;
+    output [3:0] fabric_llpp0_arcache_s_o;
+    output [11:0] fabric_llpp0_arid_s_o;
+    output [7:0] fabric_llpp0_arlen_s_o;
+    output fabric_llpp0_arlock_s_o;
+    output [2:0] fabric_llpp0_arprot_s_o;
+    output [3:0] fabric_llpp0_arqos_s_o;
+    input fabric_llpp0_arready_s_i;
+    output [2:0] fabric_llpp0_arsize_s_o;
+    output fabric_llpp0_arvalid_s_o;
+    output [31:0] fabric_llpp0_awaddr_s_o;
+    output [1:0] fabric_llpp0_awburst_s_o;
+    output [3:0] fabric_llpp0_awcache_s_o;
+    output [11:0] fabric_llpp0_awid_s_o;
+    output [7:0] fabric_llpp0_awlen_s_o;
+    output fabric_llpp0_awlock_s_o;
+    output [2:0] fabric_llpp0_awprot_s_o;
+    output [3:0] fabric_llpp0_awqos_s_o;
+    input fabric_llpp0_awready_s_i;
+    output [2:0] fabric_llpp0_awsize_s_o;
+    output fabric_llpp0_awvalid_s_o;
+    input [11:0] fabric_llpp0_bid_s_i;
+    output fabric_llpp0_bready_s_o;
+    input [1:0] fabric_llpp0_bresp_s_i;
+    input fabric_llpp0_bvalid_s_i;
+    input [31:0] fabric_llpp0_rdata_s_i;
+    input [11:0] fabric_llpp0_rid_s_i;
+    input fabric_llpp0_rlast_s_i;
+    output fabric_llpp0_rready_s_o;
+    input [1:0] fabric_llpp0_rresp_s_i;
+    input fabric_llpp0_rvalid_s_i;
+    output [31:0] fabric_llpp0_wdata_s_o;
+    output fabric_llpp0_wlast_s_o;
+    input fabric_llpp0_wready_s_i;
+    output [3:0] fabric_llpp0_wstrb_s_o;
+    output fabric_llpp0_wvalid_s_o;
+    output [31:0] fabric_llpp1_araddr_s_o;
+    output [1:0] fabric_llpp1_arburst_s_o;
+    output [3:0] fabric_llpp1_arcache_s_o;
+    output [11:0] fabric_llpp1_arid_s_o;
+    output [7:0] fabric_llpp1_arlen_s_o;
+    output fabric_llpp1_arlock_s_o;
+    output [2:0] fabric_llpp1_arprot_s_o;
+    output [3:0] fabric_llpp1_arqos_s_o;
+    input fabric_llpp1_arready_s_i;
+    output [2:0] fabric_llpp1_arsize_s_o;
+    output fabric_llpp1_arvalid_s_o;
+    output [31:0] fabric_llpp1_awaddr_s_o;
+    output [1:0] fabric_llpp1_awburst_s_o;
+    output [3:0] fabric_llpp1_awcache_s_o;
+    output [11:0] fabric_llpp1_awid_s_o;
+    output [7:0] fabric_llpp1_awlen_s_o;
+    output fabric_llpp1_awlock_s_o;
+    output [2:0] fabric_llpp1_awprot_s_o;
+    output [3:0] fabric_llpp1_awqos_s_o;
+    input fabric_llpp1_awready_s_i;
+    output [2:0] fabric_llpp1_awsize_s_o;
+    output fabric_llpp1_awvalid_s_o;
+    input [11:0] fabric_llpp1_bid_s_i;
+    output fabric_llpp1_bready_s_o;
+    input [1:0] fabric_llpp1_bresp_s_i;
+    input fabric_llpp1_bvalid_s_i;
+    input [31:0] fabric_llpp1_rdata_s_i;
+    input [11:0] fabric_llpp1_rid_s_i;
+    input fabric_llpp1_rlast_s_i;
+    output fabric_llpp1_rready_s_o;
+    input [1:0] fabric_llpp1_rresp_s_i;
+    input fabric_llpp1_rvalid_s_i;
+    output [31:0] fabric_llpp1_wdata_s_o;
+    output fabric_llpp1_wlast_s_o;
+    input fabric_llpp1_wready_s_i;
+    output [3:0] fabric_llpp1_wstrb_s_o;
+    output fabric_llpp1_wvalid_s_o;
+    output [31:0] fabric_llpp2_araddr_s_o;
+    output [1:0] fabric_llpp2_arburst_s_o;
+    output [3:0] fabric_llpp2_arcache_s_o;
+    output [11:0] fabric_llpp2_arid_s_o;
+    output [7:0] fabric_llpp2_arlen_s_o;
+    output fabric_llpp2_arlock_s_o;
+    output [2:0] fabric_llpp2_arprot_s_o;
+    output [3:0] fabric_llpp2_arqos_s_o;
+    input fabric_llpp2_arready_s_i;
+    output [2:0] fabric_llpp2_arsize_s_o;
+    output fabric_llpp2_arvalid_s_o;
+    output [31:0] fabric_llpp2_awaddr_s_o;
+    output [1:0] fabric_llpp2_awburst_s_o;
+    output [3:0] fabric_llpp2_awcache_s_o;
+    output [11:0] fabric_llpp2_awid_s_o;
+    output [7:0] fabric_llpp2_awlen_s_o;
+    output fabric_llpp2_awlock_s_o;
+    output [2:0] fabric_llpp2_awprot_s_o;
+    output [3:0] fabric_llpp2_awqos_s_o;
+    input fabric_llpp2_awready_s_i;
+    output [2:0] fabric_llpp2_awsize_s_o;
+    output fabric_llpp2_awvalid_s_o;
+    input [11:0] fabric_llpp2_bid_s_i;
+    output fabric_llpp2_bready_s_o;
+    input [1:0] fabric_llpp2_bresp_s_i;
+    input fabric_llpp2_bvalid_s_i;
+    input [31:0] fabric_llpp2_rdata_s_i;
+    input [11:0] fabric_llpp2_rid_s_i;
+    input fabric_llpp2_rlast_s_i;
+    output fabric_llpp2_rready_s_o;
+    input [1:0] fabric_llpp2_rresp_s_i;
+    input fabric_llpp2_rvalid_s_i;
+    output [31:0] fabric_llpp2_wdata_s_o;
+    output fabric_llpp2_wlast_s_o;
+    input fabric_llpp2_wready_s_i;
+    output [3:0] fabric_llpp2_wstrb_s_o;
+    output fabric_llpp2_wvalid_s_o;
+    output [31:0] fabric_llpp3_araddr_s_o;
+    output [1:0] fabric_llpp3_arburst_s_o;
+    output [3:0] fabric_llpp3_arcache_s_o;
+    output [11:0] fabric_llpp3_arid_s_o;
+    output [7:0] fabric_llpp3_arlen_s_o;
+    output fabric_llpp3_arlock_s_o;
+    output [2:0] fabric_llpp3_arprot_s_o;
+    output [3:0] fabric_llpp3_arqos_s_o;
+    input fabric_llpp3_arready_s_i;
+    output [2:0] fabric_llpp3_arsize_s_o;
+    output fabric_llpp3_arvalid_s_o;
+    output [31:0] fabric_llpp3_awaddr_s_o;
+    output [1:0] fabric_llpp3_awburst_s_o;
+    output [3:0] fabric_llpp3_awcache_s_o;
+    output [11:0] fabric_llpp3_awid_s_o;
+    output [7:0] fabric_llpp3_awlen_s_o;
+    output fabric_llpp3_awlock_s_o;
+    output [2:0] fabric_llpp3_awprot_s_o;
+    output [3:0] fabric_llpp3_awqos_s_o;
+    input fabric_llpp3_awready_s_i;
+    output [2:0] fabric_llpp3_awsize_s_o;
+    output fabric_llpp3_awvalid_s_o;
+    input [11:0] fabric_llpp3_bid_s_i;
+    output fabric_llpp3_bready_s_o;
+    input [1:0] fabric_llpp3_bresp_s_i;
+    input fabric_llpp3_bvalid_s_i;
+    input [31:0] fabric_llpp3_rdata_s_i;
+    input [11:0] fabric_llpp3_rid_s_i;
+    input fabric_llpp3_rlast_s_i;
+    output fabric_llpp3_rready_s_o;
+    input [1:0] fabric_llpp3_rresp_s_i;
+    input fabric_llpp3_rvalid_s_i;
+    output [31:0] fabric_llpp3_wdata_s_o;
+    output fabric_llpp3_wlast_s_o;
+    input fabric_llpp3_wready_s_i;
+    output [3:0] fabric_llpp3_wstrb_s_o;
+    output fabric_llpp3_wvalid_s_o;
+    input [18:2] fabric_lowskew_i;
+    output [1:0] fabric_lowskew_o;
+    input [31:0] fabric_qos_ppaddr_i;
+    input fabric_qos_ppenable_i;
+    output [31:0] fabric_qos_pprdata_o;
+    output fabric_qos_ppready_o;
+    output fabric_qos_ppslverr_o;
+    input [31:0] fabric_qos_ppwdata_i;
+    input fabric_qos_ppwrite_i;
+    input fabric_qos_presetn_i;
+    input fabric_qos_psel_i;
+    output fabric_soc_mon_sensor_alarm_o;
+    output [2:0] fabric_spw_interrupts_o;
+    output [2:0] fabric_spw_interrupts_toggle_o;
+    input fabric_sysc_hold_on_debug_i;
+    output [31:0] fabric_tnd_fpga_apb_master_paddr_o;
+    output fabric_tnd_fpga_apb_master_penable_o;
+    input [31:0] fabric_tnd_fpga_apb_master_prdata_i;
+    input fabric_tnd_fpga_apb_master_pready_i;
+    output fabric_tnd_fpga_apb_master_psel_o;
+    input fabric_tnd_fpga_apb_master_pslverr_i;
+    output [31:0] fabric_tnd_fpga_apb_master_pwdata_o;
+    output fabric_tnd_fpga_apb_master_pwrite_o;
+    input fabric_tnd_fpga_atb_master_afready_i;
+    output fabric_tnd_fpga_atb_master_afvalid_o;
+    input [3:0] fabric_tnd_fpga_atb_master_atbytes_i;
+    input [127:0] fabric_tnd_fpga_atb_master_atdata_i;
+    input [6:0] fabric_tnd_fpga_atb_master_atid_i;
+    output fabric_tnd_fpga_atb_master_atready_o;
+    input fabric_tnd_fpga_atb_master_atvalid_i;
+    output fabric_tnd_fpga_atb_master_syncreq_o;
+    output [31:0] fabric_tnd_hssl_apb_master_paddr_o;
+    output fabric_tnd_hssl_apb_master_penable_o;
+    input [31:0] fabric_tnd_hssl_apb_master_prdata_i;
+    input fabric_tnd_hssl_apb_master_pready_i;
+    output fabric_tnd_hssl_apb_master_psel_o;
+    input fabric_tnd_hssl_apb_master_pslverr_i;
+    output [31:0] fabric_tnd_hssl_apb_master_pwdata_o;
+    output fabric_tnd_hssl_apb_master_pwrite_o;
+    output fabric_tnd_hssl_atb_master_afready_o;
+    input fabric_tnd_hssl_atb_master_afvalid_i;
+    output [3:0] fabric_tnd_hssl_atb_master_atbytes_o;
+    output [127:0] fabric_tnd_hssl_atb_master_atdata_o;
+    output [6:0] fabric_tnd_hssl_atb_master_atid_o;
+    input fabric_tnd_hssl_atb_master_atready_i;
+    output fabric_tnd_hssl_atb_master_atvalid_o;
+    input fabric_tnd_hssl_atb_master_syncreq_i;
+    output fabric_tnd_hssl_flushin_o;
+    output fabric_tnd_hssl_trigin_o;
+    output fabric_tnd_trace_clk_traceoutportintf_o;
+    output fabric_tnd_trace_ctl_traceoutportintf_o;
+    output [31:0] fabric_tnd_trace_data_traceoutportintf_o;
+    output [6:0] fabric_tst_pll_lock_o;
+    output [63:0] fabric_tsvalue_tsgen_fpga_o;
+    output fabric_watchdog0_signal_0_o;
+    output fabric_watchdog0_signal_1_o;
+    output fabric_watchdog1_signal_0_o;
+    output fabric_watchdog1_signal_1_o;
+    output fabric_watchdog2_signal_0_o;
+    output fabric_watchdog2_signal_1_o;
+    output fabric_watchdog3_signal_0_o;
+    output fabric_watchdog3_signal_1_o;
+    parameter ahb_config = 0;
+    parameter bsm_config = 0;
+endmodule
+
+(* blackbox *)
+module NX_WFG(SI, ZI, RDY, SO, ZO);
+    input RDY;
+    input SI;
+    output SO;
+    input ZI;
+    output ZO;
+    parameter delay = 0;
+    parameter delay_on = 1'b0;
+    parameter location = "";
+    parameter mode = 1'b0;
+    parameter pattern = 16'b0000000000000000;
+    parameter pattern_end = 1;
+    parameter wfg_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_WFG_L(R, SI, ZI, RDY, SO, ZO);
+    input R;
+    input RDY;
+    input SI;
+    output SO;
+    input ZI;
+    output ZO;
+    parameter delay = 0;
+    parameter delay_on = 1'b0;
+    parameter location = "";
+    parameter mode = 1'b0;
+    parameter pattern = 16'b0000000000000000;
+    parameter pattern_end = 1;
+    parameter wfg_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_WFG_U(R, SI, ZI, SO, ZO);
+    input R;
+    input SI;
+    output SO;
+    input ZI;
+    output ZO;
+    parameter delay = 0;
+    parameter delay_on = 1'b0;
+    parameter div_phase = 1'b0;
+    parameter div_ratio = 0;
+    parameter location = "";
+    parameter mode = 0;
+    parameter pattern = 16'b0000000000000000;
+    parameter pattern_end = 0;
+    parameter reset_on_cal_lock_n = 1'b0;
+    parameter reset_on_pll_lock_n = 1'b0;
+    parameter reset_on_pll_locka_n = 1'b0;
+    parameter wfg_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_XCDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, CSRSTI, CDRSTI, CSRSTO, CDRSTO, DSRSTI, DDRSTI, DSRSTO, DDRSTO, BI, CI, CO
+, AO, BO, AI, DI, DO);
+    input ADRSTI;
+    output ADRSTO;
+    input [5:0] AI;
+    output [5:0] AO;
+    input ASRSTI;
+    output ASRSTO;
+    input BDRSTI;
+    output BDRSTO;
+    input [5:0] BI;
+    output [5:0] BO;
+    input BSRSTI;
+    output BSRSTO;
+    input CDRSTI;
+    output CDRSTO;
+    input [5:0] CI;
+    input CK1;
+    input CK2;
+    output [5:0] CO;
+    input CSRSTI;
+    output CSRSTO;
+    input DDRSTI;
+    output DDRSTO;
+    input [5:0] DI;
+    output [5:0] DO;
+    input DSRSTI;
+    output DSRSTO;
+    parameter ack_sel = 1'b0;
+    parameter bck_sel = 1'b0;
+    parameter cck_sel = 1'b0;
+    parameter ck0_edge = 1'b0;
+    parameter ck1_edge = 1'b0;
+    parameter dck_sel = 1'b0;
+    parameter link_BA = 1'b0;
+    parameter link_CB = 1'b0;
+    parameter link_DC = 1'b0;
+    parameter use_adest_arst = 1'b0;
+    parameter use_asrc_arst = 1'b0;
+    parameter use_bdest_arst = 1'b0;
+    parameter use_bsrc_arst = 1'b0;
+    parameter use_cdest_arst = 1'b0;
+    parameter use_csrc_arst = 1'b0;
+    parameter use_ddest_arst = 1'b0;
+    parameter use_dsrc_arst = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_XFIFO_32x36(RCK, WCK, WE, WEA, WRSTI, WEQ, RRSTI, REQ, I, O, WAI, WAO, RAI, RAO);
+    input [35:0] I;
+    output [35:0] O;
+    input [5:0] RAI;
+    output [5:0] RAO;
+    input RCK;
+    output REQ;
+    input RRSTI;
+    input [5:0] WAI;
+    output [5:0] WAO;
+    input WCK;
+    input WE;
+    input WEA;
+    output WEQ;
+    input WRSTI;
+    parameter rck_edge = 1'b0;
+    parameter read_addr_inv = 7'b0000000;
+    parameter use_read_arst = 1'b0;
+    parameter use_write_arst = 1'b0;
+    parameter wck_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_XFIFO_64x18(RCK, WCK, WE, WEA, WRSTI, RRSTI, I, O, WEQ, REQ, WAI, WAO, RAI, RAO);
+    input [17:0] I;
+    output [17:0] O;
+    input [6:0] RAI;
+    output [6:0] RAO;
+    input RCK;
+    output [1:0] REQ;
+    input RRSTI;
+    input [6:0] WAI;
+    output [6:0] WAO;
+    input WCK;
+    input WE;
+    input WEA;
+    output [1:0] WEQ;
+    input WRSTI;
+    parameter rck_edge = 1'b0;
+    parameter read_addr_inv = 7'b0000000;
+    parameter use_read_arst = 1'b0;
+    parameter use_write_arst = 1'b0;
+    parameter wck_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_XRFB_2R_1W(WCK, WE, WEA, I, AO, BO, WA, ARA, BRA);
+    output [17:0] AO;
+    input [4:0] ARA;
+    output [17:0] BO;
+    input [4:0] BRA;
+    input [17:0] I;
+    input [4:0] WA;
+    input WCK;
+    input WE;
+    input WEA;
+    parameter mem_ctxt = "";
+    parameter wck_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_XRFB_32x36(WCK, WE, WEA, I, O, RA, WA);
+    input [35:0] I;
+    output [35:0] O;
+    input [4:0] RA;
+    input [4:0] WA;
+    input WCK;
+    input WE;
+    input WEA;
+    parameter mem_ctxt = "";
+    parameter wck_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_XRFB_64x18(WCK, WE, WEA, I, O, RA, WA);
+    input [17:0] I;
+    output [17:0] O;
+    input [5:0] RA;
+    input [5:0] WA;
+    input WCK;
+    input WE;
+    input WEA;
+    parameter mem_ctxt = "";
+    parameter wck_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module SMACC24x18_1DSP(clk, rst, A, B, Z);
+    input [23:0] A;
+    input [17:0] B;
+    output [55:0] Z;
+    input clk;
+    input rst;
+    parameter g_pipe = 1;
+endmodule
+
+(* blackbox *)
+module SMACC24x32_2DSP(clk, rst, A, B, Z);
+    input [23:0] A;
+    input [31:0] B;
+    output [55:0] Z;
+    input clk;
+    input rst;
+    parameter g_pipe = 1;
+endmodule
+
+(* blackbox *)
+module SMACC24x32_enable_2DSP(clk, rst, we, A, B, Z);
+    input [23:0] A;
+    input [31:0] B;
+    output [55:0] Z;
+    input clk;
+    input rst;
+    input we;
+    parameter STAGE_1 = "false";
+    parameter STAGE_2 = "false";
+    parameter STAGE_3 = "false";
+    parameter STAGE_4 = "false";
+endmodule
+
+(* blackbox *)
+module SMUL24x32_2DSP(clk, rst, A, B, Z);
+    input [23:0] A;
+    input [31:0] B;
+    output [54:0] Z;
+    input clk;
+    input rst;
+    parameter g_pipe = 1;
+endmodule
+
+(* blackbox *)
+module SMUL24x32_2DSP_ACC_2DSP(clk, rst, we, A, B, Z);
+    input [23:0] A;
+    input [31:0] B;
+    output [97:0] Z;
+    input clk;
+    input rst;
+    input we;
+    parameter STAGE_1 = "false";
+    parameter STAGE_2 = "false";
+    parameter STAGE_3 = "false";
+endmodule
+
+(* blackbox *)
+module SMUL24x32_2DSP_ACC_2DSP_L(clk, rst, we, A, B, Z);
+    input [23:0] A;
+    input [31:0] B;
+    output [91:0] Z;
+    input clk;
+    input rst;
+    input we;
+endmodule
+
+(* blackbox *)
+module SMUL47x35_4DSP(clk, rst, A, B, Z);
+    input [46:0] A;
+    input [34:0] B;
+    output [80:0] Z;
+    input clk;
+    input rst;
+    parameter piped = "true";
+endmodule
+
+(* blackbox *)
+module UMADD24_2DSP(clk, rst, A, B, C, Z);
+    input [23:0] A;
+    input [31:0] B;
+    input [55:0] C;
+    output [55:0] Z;
+    input clk;
+    input rst;
+    parameter piped = "true";
+endmodule
+
+(* blackbox *)
+module UMUL24x32_1DSP_2CYCLES(clk, rst, A, B, Z);
+    input [23:0] A;
+    input [15:0] B;
+    output [55:0] Z;
+    input clk;
+    input rst;
+    parameter piped = "true";
+endmodule
+
+(* blackbox *)
+module UMUL24x32_2DSP(clk, rst, A, B, Z);
+    input [23:0] A;
+    input [31:0] B;
+    output [55:0] Z;
+    input clk;
+    input rst;
+    parameter piped = "true";
+endmodule
+
+(* blackbox *)
+module UMUL24x36_1DSP_2CYCLES(clk, rst, A, B, Z);
+    input [23:0] A;
+    input [17:0] B;
+    output [59:0] Z;
+    input clk;
+    input rst;
+    parameter piped = "true";
+endmodule
+
+(* blackbox *)
+module UMUL24x36_2DSP(clk, rst, A, B, Z);
+    input [23:0] A;
+    input [35:0] B;
+    output [59:0] Z;
+    input clk;
+    input rst;
+    parameter piped = "true";
+endmodule
+
+(* blackbox *)
+module UMUL48x36_1DSP_4CYCLES(clk, rst, A, B, Z);
+    input [23:0] A;
+    input [17:0] B;
+    output [83:0] Z;
+    input clk;
+    input rst;
+    parameter piped = "true";
+endmodule
+
+(* blackbox *)
+module UMUL48x36_4DSP(clk, rst, A, B, Z);
+    input [47:0] A;
+    input [35:0] B;
+    output [83:0] Z;
+    input clk;
+    input rst;
+    parameter piped = "true";
+endmodule
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index eda65b66b40..b37bed164a3 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -160,7 +160,7 @@ struct SynthNanoXplorePass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib -specify +/nanoxplore/cells_sim.v");
+			run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_bb.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 		}
 

From b0c4add642f23f899f5aac69c5970d9e34e1a921 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Fri, 1 Mar 2024 13:41:25 +0100
Subject: [PATCH 268/499] Added lutram

---
 techlibs/nanoxplore/Makefile.inc        |  1 +
 techlibs/nanoxplore/cells_bb.v          | 50 ++++++++++++------------
 techlibs/nanoxplore/cells_map.v         | 12 ++++++
 techlibs/nanoxplore/cells_sim.v         | 51 +++++++++++++++++++++++++
 techlibs/nanoxplore/drams.txt           | 27 +++++++++++++
 techlibs/nanoxplore/synth_nanoxplore.cc | 41 ++++++++++++++++++--
 tests/arch/nanoxplore/lutram.ys         |  8 ++++
 7 files changed, 161 insertions(+), 29 deletions(-)
 create mode 100644 techlibs/nanoxplore/drams.txt
 create mode 100644 tests/arch/nanoxplore/lutram.ys

diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc
index 0f7bcdbeda8..d7331f5dee4 100644
--- a/techlibs/nanoxplore/Makefile.inc
+++ b/techlibs/nanoxplore/Makefile.inc
@@ -6,3 +6,4 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/drams.txt))
diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index 7ebad4ae8fd..6aa98152992 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -32930,31 +32930,31 @@ module NX_XRFB_2R_1W(WCK, WE, WEA, I, AO, BO, WA, ARA, BRA);
     parameter wck_edge = 1'b0;
 endmodule
 
-(* blackbox *)
-module NX_XRFB_32x36(WCK, WE, WEA, I, O, RA, WA);
-    input [35:0] I;
-    output [35:0] O;
-    input [4:0] RA;
-    input [4:0] WA;
-    input WCK;
-    input WE;
-    input WEA;
-    parameter mem_ctxt = "";
-    parameter wck_edge = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_XRFB_64x18(WCK, WE, WEA, I, O, RA, WA);
-    input [17:0] I;
-    output [17:0] O;
-    input [5:0] RA;
-    input [5:0] WA;
-    input WCK;
-    input WE;
-    input WEA;
-    parameter mem_ctxt = "";
-    parameter wck_edge = 1'b0;
-endmodule
+//(* blackbox *)
+//module NX_XRFB_32x36(WCK, WE, WEA, I, O, RA, WA);
+//    input [35:0] I;
+//    output [35:0] O;
+//    input [4:0] RA;
+//    input [4:0] WA;
+//    input WCK;
+//    input WE;
+//    input WEA;
+//    parameter mem_ctxt = "";
+//    parameter wck_edge = 1'b0;
+//endmodule
+//
+//(* blackbox *)
+//module NX_XRFB_64x18(WCK, WE, WEA, I, O, RA, WA);
+//    input [17:0] I;
+//    output [17:0] O;
+//    input [5:0] RA;
+//    input [5:0] WA;
+//    input WCK;
+//    input WE;
+//    input WEA;
+//    parameter mem_ctxt = "";
+//    parameter wck_edge = 1'b0;
+//endmodule
 
 (* blackbox *)
 module SMACC24x18_1DSP(clk, rst, A, B, Z);
diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v
index efa2a2af541..9728922f373 100644
--- a/techlibs/nanoxplore/cells_map.v
+++ b/techlibs/nanoxplore/cells_map.v
@@ -66,3 +66,15 @@ endmodule
 module \$_SDFF_NP1_ (input D, C, R, output Q);
   NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
 endmodule
+
+module $__NX_XRFB_64x18_ (input PORT_W_CLK, input [5:0] PORT_W_ADDR, PORT_R_ADDR, input [17:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [17:0] PORT_R_RD_DATA);
+  parameter INIT = 1152'bx;
+  parameter PORT_W_CLK_POL = 1'b1;
+  NX_XRFB_64x18 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA));
+endmodule
+
+module $__NX_XRFB_32x36_ (input PORT_W_CLK, input [4:0] PORT_W_ADDR, PORT_R_ADDR, input [35:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [35:0] PORT_R_RD_DATA);
+  parameter INIT = 1152'bx;
+  parameter PORT_W_CLK_POL = 1'b1;
+  NX_XRFB_32x36 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA));
+endmodule
diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v
index 1f04b216ee0..2a4b5b00f3a 100644
--- a/techlibs/nanoxplore/cells_sim.v
+++ b/techlibs/nanoxplore/cells_sim.v
@@ -9,6 +9,7 @@ assign O = I1 ? s3[1] : s3[0];
 
 endmodule
 
+(* abc9_box, lib_whitebox *)
 module NX_DFF(input I, CK, L, R, output reg O);
 
 parameter dff_ctxt = 1'bx;
@@ -34,8 +35,58 @@ always @(posedge clock, posedge async_reset)
 
 endmodule
 
+(* abc9_box, lib_whitebox *)
 module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO);
 parameter add_carry = 0;
 
 assign {CO, S4, S3, S2, S1} = {A4, A3, A2, A1} + {B4, B3, B2, B1} + CI;
+
+endmodule
+
+(* abc9_box, lib_whitebox *)
+module NX_XRFB_64x18(input WCK, input [17:0] I, input [5:0] RA, WA, input WE, WEA, output [17:0] O);
+
+parameter wck_edge = 1'b0;
+parameter mem_ctxt = 1152'b0;
+
+reg [17:0] mem [63:0];
+
+integer i;
+initial begin
+	for (i = 0; i < 64; i = i + 1)
+		mem[i] = mem_ctxt[18*i +: 18];
+end
+
+wire clock = WCK ^ wck_edge;
+
+always @(posedge clock)
+	if (WE && WEA)
+		mem[WA] <= I;
+
+assign O = mem[RA];
+
+endmodule
+
+(* abc9_box, lib_whitebox *)
+module NX_XRFB_32x36(input WCK, input [35:0] I, input [4:0] RA, WA, input WE, WEA, output [35:0] O);
+
+parameter wck_edge = 1'b0;
+parameter mem_ctxt = 1152'b0;
+
+reg [35:0] mem [31:0];
+
+integer i;
+initial begin
+	for (i = 0; i < 32; i = i + 1)
+		mem[i] = mem_ctxt[36*i +: 36];
+end
+
+wire clock = WCK ^ wck_edge;
+
+always @(posedge clock)
+	if (WE && WEA)
+		mem[WA] <= I;
+
+assign O = mem[RA];
+
 endmodule
diff --git a/techlibs/nanoxplore/drams.txt b/techlibs/nanoxplore/drams.txt
new file mode 100644
index 00000000000..370b62b1638
--- /dev/null
+++ b/techlibs/nanoxplore/drams.txt
@@ -0,0 +1,27 @@
+ram distributed $__NX_XRFB_64x18_ {
+    abits 6;
+    width 18;
+    cost 10;
+    init no_undef;
+    prune_rom;
+
+    port sw "W" {
+        clock anyedge;
+    }
+    port ar "R" {
+    }
+}
+
+ram distributed $__NX_XRFB_32x36_ {
+    abits 5;
+    width 36;
+    cost 10;
+    init no_undef;
+    prune_rom;
+
+    port sw "W" {
+        clock anyedge;
+    }
+    port ar "R" {
+    }
+}
\ No newline at end of file
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index b37bed164a3..97c4a21a4ba 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -73,6 +73,18 @@ struct SynthNanoXplorePass : public ScriptPass
 		log("    -nocy\n");
 		log("        do not map adders to CY cells\n");
 		log("\n");
+		log("    -nolutram\n");
+		log("        do not use LUT RAM cells in output netlist\n");
+		log("\n");
+		log("    -nobram\n");
+		log("        do not use block RAM cells in output netlist\n");
+		log("\n");
+		log("    -nodsp\n");
+		log("        do not map multipliers to NX_DSP cells\n");
+		log("\n");
+		log("    -noiopad\n");
+		log("        do not instantiate IO buffers\n");
+		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
 		help_script();
@@ -80,7 +92,7 @@ struct SynthNanoXplorePass : public ScriptPass
 	}
 
 	string top_opt, json_file, family;
-	bool flatten, abc9, nocy;
+	bool flatten, abc9, nocy, nolutram, nobram, nodsp, noiopad;
 
 	void clear_flags() override
 	{
@@ -90,6 +102,10 @@ struct SynthNanoXplorePass : public ScriptPass
 		flatten = true;
 		abc9 = false;
 		nocy = false;
+		nolutram = false;
+		nobram = false;
+		nodsp = false;
+		noiopad = false;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -136,12 +152,28 @@ struct SynthNanoXplorePass : public ScriptPass
 				nocy = true;
 				continue;
 			}
+			if (args[argidx] == "-nolutram") {
+				nolutram = true;
+				continue;
+			}
+			if (args[argidx] == "-nobram") {
+				nobram = true;
+				continue;
+			}
+			if (args[argidx] == "-nodsp") {
+				nodsp = true;
+				continue;
+			}
+			if (args[argidx] == "-noiopad") {
+				noiopad = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
 
 		if (family.empty()) {
-			log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n");
+			//log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n");
 			family = "ultra";
 		}
 
@@ -190,8 +222,9 @@ struct SynthNanoXplorePass : public ScriptPass
 			run("opt_clean");
 		}
 
-		if (check_label("map_ram"))
-		{
+		if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) {
+			run("memory_libmap -lib +/nanoxplore/drams.txt");
+			run("techmap -map +/nanoxplore/cells_map.v t:$__NX_XRFB_32x36_ t:$__NX_XRFB_64x18_");
 		}
 
 		if (check_label("map_ffram"))
diff --git a/tests/arch/nanoxplore/lutram.ys b/tests/arch/nanoxplore/lutram.ys
new file mode 100644
index 00000000000..97035b64cf5
--- /dev/null
+++ b/tests/arch/nanoxplore/lutram.ys
@@ -0,0 +1,8 @@
+read_verilog ../common/lutram.v
+hierarchy -top lutram_1w1r
+synth_nanoxplore -noiopad
+cd lutram_1w1r
+select -assert-count 1 t:NX_XRFB_64x18
+select -assert-count 8 t:NX_DFF
+select -assert-none t:NX_XRFB_64x18 t:NX_DFF %% t:* %D
+

From 65d2ebac9d941b854649aa0c118de629999fb236 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 1 Mar 2024 13:51:56 +0100
Subject: [PATCH 269/499] fix test

---
 tests/arch/nanoxplore/lutram.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/arch/nanoxplore/lutram.ys b/tests/arch/nanoxplore/lutram.ys
index 97035b64cf5..669cb000757 100644
--- a/tests/arch/nanoxplore/lutram.ys
+++ b/tests/arch/nanoxplore/lutram.ys
@@ -1,6 +1,6 @@
 read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r
-synth_nanoxplore -noiopad
+synth_nanoxplore
 cd lutram_1w1r
 select -assert-count 1 t:NX_XRFB_64x18
 select -assert-count 8 t:NX_DFF

From 4c1f84a686ff86fc370690840643ee0470075990 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 1 Mar 2024 13:52:11 +0100
Subject: [PATCH 270/499] add io mapping

---
 techlibs/nanoxplore/Makefile.inc        |  1 +
 techlibs/nanoxplore/io_map.v            |  8 ++++++++
 techlibs/nanoxplore/synth_nanoxplore.cc | 18 ++++++++++++------
 3 files changed, 21 insertions(+), 6 deletions(-)
 create mode 100644 techlibs/nanoxplore/io_map.v

diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc
index d7331f5dee4..030cabd64b7 100644
--- a/techlibs/nanoxplore/Makefile.inc
+++ b/techlibs/nanoxplore/Makefile.inc
@@ -7,3 +7,4 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/drams.txt))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v))
diff --git a/techlibs/nanoxplore/io_map.v b/techlibs/nanoxplore/io_map.v
new file mode 100644
index 00000000000..42fac461903
--- /dev/null
+++ b/techlibs/nanoxplore/io_map.v
@@ -0,0 +1,8 @@
+module \$__BEYOND_IBUF (input PAD, output O);
+	NX_IOB_I _TECHMAP_REPLACE_ (.IO(PAD), .O(O), .C(1'b0));
+endmodule
+
+module \$__BEYOND_OBUF (output PAD, input I);
+	NX_IOB_O _TECHMAP_REPLACE_ (.IO(PAD), .I(I), .C(1'b1));
+endmodule
+
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index 97c4a21a4ba..d5e77daaa5d 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -82,8 +82,8 @@ struct SynthNanoXplorePass : public ScriptPass
 		log("    -nodsp\n");
 		log("        do not map multipliers to NX_DSP cells\n");
 		log("\n");
-		log("    -noiopad\n");
-		log("        do not instantiate IO buffers\n");
+		log("    -iopad\n");
+		log("       insert IO buffers\n");
 		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
@@ -92,7 +92,7 @@ struct SynthNanoXplorePass : public ScriptPass
 	}
 
 	string top_opt, json_file, family;
-	bool flatten, abc9, nocy, nolutram, nobram, nodsp, noiopad;
+	bool flatten, abc9, nocy, nolutram, nobram, nodsp, iopad;
 
 	void clear_flags() override
 	{
@@ -105,7 +105,7 @@ struct SynthNanoXplorePass : public ScriptPass
 		nolutram = false;
 		nobram = false;
 		nodsp = false;
-		noiopad = false;
+		iopad = false;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -164,8 +164,8 @@ struct SynthNanoXplorePass : public ScriptPass
 				nodsp = true;
 				continue;
 			}
-			if (args[argidx] == "-noiopad") {
-				noiopad = true;
+			if (args[argidx] == "-iopad") {
+				iopad = true;
 				continue;
 			}
 			break;
@@ -240,6 +240,12 @@ struct SynthNanoXplorePass : public ScriptPass
 				run("techmap");
 			else
 				run("techmap -map +/techmap.v -map +/nanoxplore/arith_map.v");
+			if (help_mode || iopad) {
+				run("iopadmap -bits -outpad $__BEYOND_OBUF I:PAD -inpad $__BEYOND_IBUF O:PAD A:top", "(only if '-iopad')");
+				run("techmap -map +/nanoxplore/io_map.v");
+				run("attrmvcp -attr src -attr LOC t:NX_IOB_O n:*");
+				run("attrmvcp -attr src -attr LOC -driven t:NX_IOB_I n:*");
+			}
 			run("opt -fast");
 		}
 

From 74289b733968f4f4b41fd6ed31b02114f3a492dc Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 1 Mar 2024 15:25:24 +0100
Subject: [PATCH 271/499] remove init from sdff

---
 techlibs/nanoxplore/cells_map.v | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v
index 9728922f373..54f2414c849 100644
--- a/techlibs/nanoxplore/cells_map.v
+++ b/techlibs/nanoxplore/cells_map.v
@@ -52,18 +52,22 @@ module aldff(input D, C, L, AD, output Q);
 endmodule
 
 module \$_SDFF_PP0_ (input D, C, R, output Q);
+  wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
   NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
 endmodule
 
 module \$_SDFF_PP1_ (input D, C, R, output Q);
+  wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
   NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
 endmodule
 
 module \$_SDFF_NP0_ (input D, C, R, output Q);
+  wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
   NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
 endmodule
 
 module \$_SDFF_NP1_ (input D, C, R, output Q);
+  wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
   NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
 endmodule
 

From 989eef29b2c317c5a9724a848b8f3b64ffb166b7 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 1 Mar 2024 16:19:00 +0100
Subject: [PATCH 272/499] produce less cells

---
 techlibs/nanoxplore/cells_sim.v         | 1 +
 techlibs/nanoxplore/synth_nanoxplore.cc | 5 +++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v
index 2a4b5b00f3a..35b1574ba2a 100644
--- a/techlibs/nanoxplore/cells_sim.v
+++ b/techlibs/nanoxplore/cells_sim.v
@@ -1,3 +1,4 @@
+(* abc9_lut=1 *)
 module NX_LUT(input I1, I2, I3, I4, output O);
 
 parameter lut_table = 16'h0000;
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index d5e77daaa5d..c4c625cb50e 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -229,9 +229,10 @@ struct SynthNanoXplorePass : public ScriptPass
 
 		if (check_label("map_ffram"))
 		{
-			run("opt -fast -mux_undef -undriven -fine");
+			//run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");
-			run("opt -undriven -fine -mux_undef");
+			run("opt -full");
+			//run("opt -undriven -fine -mux_undef");
 		}
 
 		if (check_label("map_gates"))

From 9700971a8ad95031caa6a23e17b9d861db73c1c2 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 6 Mar 2024 14:45:49 +0100
Subject: [PATCH 273/499] just copy LOC

---
 techlibs/nanoxplore/synth_nanoxplore.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index c4c625cb50e..75168adcce2 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -244,8 +244,8 @@ struct SynthNanoXplorePass : public ScriptPass
 			if (help_mode || iopad) {
 				run("iopadmap -bits -outpad $__BEYOND_OBUF I:PAD -inpad $__BEYOND_IBUF O:PAD A:top", "(only if '-iopad')");
 				run("techmap -map +/nanoxplore/io_map.v");
-				run("attrmvcp -attr src -attr LOC t:NX_IOB_O n:*");
-				run("attrmvcp -attr src -attr LOC -driven t:NX_IOB_I n:*");
+				run("attrmvcp -attr LOC t:NX_IOB_O n:*");
+				run("attrmvcp -attr LOC -driven t:NX_IOB_I n:*");
 			}
 			run("opt -fast");
 		}

From cfce7dd2f8b877213731a8abc3ee250c1d66515f Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 11 Mar 2024 10:42:14 +0100
Subject: [PATCH 274/499] remove soc

---
 techlibs/nanoxplore/cells_bb.v | 23061 -------------------------------
 1 file changed, 23061 deletions(-)

diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index 6aa98152992..01fc0e3f3b2 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -8222,1385 +8222,6 @@ module NX_PMA_U(CLK_TX_I, CLK_RX_I, CLK_REF_I, DC_E_I, DC_LCSN_I1, DC_LCSN_I2, D
     parameter tx_usrclk_use_pcs_clk_2 = 1'b0;
 endmodule
 
-(* blackbox *)
-module NX_R5_L(A_CKEM_I, A_CKEP_I, A_CKES_I, AR_A_I32, AR_A_I31, AR_A_I30, AR_A_I29, AR_A_I28, AR_A_I27, AR_A_I26, AR_A_I25, AR_A_I24, AR_A_I23, AR_A_I22, AR_A_I21, AR_A_I20, AR_A_I19, AR_A_I18, AR_A_I17, AR_A_I16, AR_A_I15
-, AR_A_I14, AR_A_I13, AR_A_I12, AR_A_I11, AR_A_I10, AR_A_I9, AR_A_I8, AR_A_I7, AR_A_I6, AR_A_I5, AR_A_I4, AR_A_I3, AR_A_I2, AR_A_I1, AR_BU_I2, AR_BU_I1, AR_CH_I4, AR_CH_I3, AR_CH_I2, AR_CH_I1, AR_IDS_I8
-, AR_IDS_I7, AR_IDS_I6, AR_IDS_I5, AR_IDS_I4, AR_IDS_I3, AR_IDS_I2, AR_IDS_I1, AR_LE_I4, AR_LE_I3, AR_LE_I2, AR_LE_I1, AR_LK_I2, AR_LK_I1, AR_PR_I3, AR_PR_I2, AR_PR_I1, AR_RYM_I, AR_RYP_I, AR_SZ_I3, AR_SZ_I2, AR_SZ_I1
-, AR_VD_I, AT_RS_I, AW_A_I32, AW_A_I31, AW_A_I30, AW_A_I29, AW_A_I28, AW_A_I27, AW_A_I26, AW_A_I25, AW_A_I24, AW_A_I23, AW_A_I22, AW_A_I21, AW_A_I20, AW_A_I19, AW_A_I18, AW_A_I17, AW_A_I16, AW_A_I15, AW_A_I14
-, AW_A_I13, AW_A_I12, AW_A_I11, AW_A_I10, AW_A_I9, AW_A_I8, AW_A_I7, AW_A_I6, AW_A_I5, AW_A_I4, AW_A_I3, AW_A_I2, AW_A_I1, AW_BU_I2, AW_BU_I1, AW_CH_I4, AW_CH_I3, AW_CH_I2, AW_CH_I1, AW_IDS_I8, AW_IDS_I7
-, AW_IDS_I6, AW_IDS_I5, AW_IDS_I4, AW_IDS_I3, AW_IDS_I2, AW_IDS_I1, AW_LE_I4, AW_LE_I3, AW_LE_I2, AW_LE_I1, AW_LK_I2, AW_LK_I1, AW_PR_I3, AW_PR_I2, AW_PR_I1, AW_RYM_I, AW_RYP_I, AW_SZ_I3, AW_SZ_I2, AW_SZ_I1, AW_VD_I
-, B_IDM_I4, B_IDM_I3, B_IDM_I2, B_IDM_I1, B_IDP_I4, B_IDP_I3, B_IDP_I2, B_IDP_I1, B_RDY_I, B_RSPM_I2, B_RSPM_I1, B_RSPP_I2, B_RSPP_I1, B_VDM_I, B_VDP_I, CDB_PW_I, CDB_RS_I, CFG_EE_I, CFG_IE_I, CFG_NM_I, CK_I
-, CS_PW_I, DB_E_I, DB_NCK_I, DB_RA_I20, DB_RA_I19, DB_RA_I18, DB_RA_I17, DB_RA_I16, DB_RA_I15, DB_RA_I14, DB_RA_I13, DB_RA_I12, DB_RA_I11, DB_RA_I10, DB_RA_I9, DB_RA_I8, DB_RA_I7, DB_RA_I6, DB_RA_I5, DB_RA_I4, DB_RA_I3
-, DB_RA_I2, DB_RA_I1, DB_RAV_I, DB_SA_I20, DB_SA_I19, DB_SA_I18, DB_SA_I17, DB_SA_I16, DB_SA_I15, DB_SA_I14, DB_SA_I13, DB_SA_I12, DB_SA_I11, DB_SA_I10, DB_SA_I9, DB_SA_I8, DB_SA_I7, DB_SA_I6, DB_SA_I5, DB_SA_I4, DB_SA_I3
-, DB_SA_I2, DB_SA_I1, DB_SAV_I, DEV_E_I, DFTS_I8, DFTS_I7, DFTS_I6, DFTS_I5, DFTS_I4, DFTS_I3, DFTS_I2, DFTS_I1, E_DB_I, ERR_R_I, EVENT_I, GID_I4, GID_I3, GID_I2, GID_I1, INIT_P_I, INIT_R_I
-, LOC_R_I, NCPUH_I, NET_RS_I, N_FIQ_I, N_IDE_I, N_IRQ_I, N_PRS_I, N_RS_I, N_SPRS_I, N_TRS_I, P_A_I29, P_A_I28, P_A_I27, P_A_I26, P_A_I25, P_A_I24, P_A_I23, P_A_I22, P_A_I21, P_A_I20, P_A_I19
-, P_A_I18, P_A_I17, P_A_I16, P_A_I15, P_A_I14, P_A_I13, P_A_I12, P_A_I11, P_A_I10, P_A_I9, P_A_I8, P_A_I7, P_A_I6, P_A_I5, P_A_I4, P_A_I3, P_A_I2, P_A_I1, P_ECC_I, PLVL_I, P_CK_E_I
-, P_CK_I, P_E_I, PPV_BS_I20, PPV_BS_I19, PPV_BS_I18, PPV_BS_I17, PPV_BS_I16, PPV_BS_I15, PPV_BS_I14, PPV_BS_I13, PPV_BS_I12, PPV_BS_I11, PPV_BS_I10, PPV_BS_I9, PPV_BS_I8, PPV_BS_I7, PPV_BS_I6, PPV_BS_I5, PPV_BS_I4, PPV_BS_I3, PPV_BS_I2
-, PPV_BS_I1, PPV_SZ_I5, PPV_SZ_I4, PPV_SZ_I3, PPV_SZ_I2, PPV_SZ_I1, PPX_BS_I20, PPX_BS_I19, PPX_BS_I18, PPX_BS_I17, PPX_BS_I16, PPX_BS_I15, PPX_BS_I14, PPX_BS_I13, PPX_BS_I12, PPX_BS_I11, PPX_BS_I10, PPX_BS_I9, PPX_BS_I8, PPX_BS_I7, PPX_BS_I6
-, PPX_BS_I5, PPX_BS_I4, PPX_BS_I3, PPX_BS_I2, PPX_BS_I1, PPX_SZ_I5, PPX_SZ_I4, PPX_SZ_I3, PPX_SZ_I2, PPX_SZ_I1, P_RS_I, P_SEL_I, PW_D_I32, PW_D_I31, PW_D_I30, PW_D_I29, PW_D_I28, PW_D_I27, PW_D_I26, PW_D_I25, PW_D_I24
-, PW_D_I23, PW_D_I22, PW_D_I21, PW_D_I20, PW_D_I19, PW_D_I18, PW_D_I17, PW_D_I16, PW_D_I15, PW_D_I14, PW_D_I13, PW_D_I12, PW_D_I11, PW_D_I10, PW_D_I9, PW_D_I8, PW_D_I7, PW_D_I6, PW_D_I5, PW_D_I4, PW_D_I3
-, PW_D_I2, PW_D_I1, PW_I, RAMCTL_I8, RAMCTL_I7, RAMCTL_I6, RAMCTL_I5, RAMCTL_I4, RAMCTL_I3, RAMCTL_I2, RAMCTL_I1, R_DM_I64, R_DM_I63, R_DM_I62, R_DM_I61, R_DM_I60, R_DM_I59, R_DM_I58, R_DM_I57, R_DM_I56, R_DM_I55
-, R_DM_I54, R_DM_I53, R_DM_I52, R_DM_I51, R_DM_I50, R_DM_I49, R_DM_I48, R_DM_I47, R_DM_I46, R_DM_I45, R_DM_I44, R_DM_I43, R_DM_I42, R_DM_I41, R_DM_I40, R_DM_I39, R_DM_I38, R_DM_I37, R_DM_I36, R_DM_I35, R_DM_I34
-, R_DM_I33, R_DM_I32, R_DM_I31, R_DM_I30, R_DM_I29, R_DM_I28, R_DM_I27, R_DM_I26, R_DM_I25, R_DM_I24, R_DM_I23, R_DM_I22, R_DM_I21, R_DM_I20, R_DM_I19, R_DM_I18, R_DM_I17, R_DM_I16, R_DM_I15, R_DM_I14, R_DM_I13
-, R_DM_I12, R_DM_I11, R_DM_I10, R_DM_I9, R_DM_I8, R_DM_I7, R_DM_I6, R_DM_I5, R_DM_I4, R_DM_I3, R_DM_I2, R_DM_I1, R_DP_I32, R_DP_I31, R_DP_I30, R_DP_I29, R_DP_I28, R_DP_I27, R_DP_I26, R_DP_I25, R_DP_I24
-, R_DP_I23, R_DP_I22, R_DP_I21, R_DP_I20, R_DP_I19, R_DP_I18, R_DP_I17, R_DP_I16, R_DP_I15, R_DP_I14, R_DP_I13, R_DP_I12, R_DP_I11, R_DP_I10, R_DP_I9, R_DP_I8, R_DP_I7, R_DP_I6, R_DP_I5, R_DP_I4, R_DP_I3
-, R_DP_I2, R_DP_I1, R_IDM_I4, R_IDM_I3, R_IDM_I2, R_IDM_I1, R_IDP_I4, R_IDP_I3, R_IDP_I2, R_IDP_I1, R_LSTM_I, R_LSTP_I, R_RDY_I, R_RSPM_I2, R_RSPM_I1, R_RSPP_I2, R_RSPP_I1, RS_BYP_I, R_VDM_I, R_VDP_I, SE_I
-, SW_CK_I, SW_DI_I, T_DI_I, TE_INI_I, VINI_I, W_D_I64, W_D_I63, W_D_I62, W_D_I61, W_D_I60, W_D_I59, W_D_I58, W_D_I57, W_D_I56, W_D_I55, W_D_I54, W_D_I53, W_D_I52, W_D_I51, W_D_I50, W_D_I49
-, W_D_I48, W_D_I47, W_D_I46, W_D_I45, W_D_I44, W_D_I43, W_D_I42, W_D_I41, W_D_I40, W_D_I39, W_D_I38, W_D_I37, W_D_I36, W_D_I35, W_D_I34, W_D_I33, W_D_I32, W_D_I31, W_D_I30, W_D_I29, W_D_I28
-, W_D_I27, W_D_I26, W_D_I25, W_D_I24, W_D_I23, W_D_I22, W_D_I21, W_D_I20, W_D_I19, W_D_I18, W_D_I17, W_D_I16, W_D_I15, W_D_I14, W_D_I13, W_D_I12, W_D_I11, W_D_I10, W_D_I9, W_D_I8, W_D_I7
-, W_D_I6, W_D_I5, W_D_I4, W_D_I3, W_D_I2, W_D_I1, W_IDS_I8, W_IDS_I7, W_IDS_I6, W_IDS_I5, W_IDS_I4, W_IDS_I3, W_IDS_I2, W_IDS_I1, W_LST_I, W_RYM_I, W_RYP_I, W_SBS_I8, W_SBS_I7, W_SBS_I6, W_SBS_I5
-, W_SBS_I4, W_SBS_I3, W_SBS_I2, W_SBS_I1, W_VD_I, AR_AM_O32, AR_AM_O31, AR_AM_O30, AR_AM_O29, AR_AM_O28, AR_AM_O27, AR_AM_O26, AR_AM_O25, AR_AM_O24, AR_AM_O23, AR_AM_O22, AR_AM_O21, AR_AM_O20, AR_AM_O19, AR_AM_O18, AR_AM_O17
-, AR_AM_O16, AR_AM_O15, AR_AM_O14, AR_AM_O13, AR_AM_O12, AR_AM_O11, AR_AM_O10, AR_AM_O9, AR_AM_O8, AR_AM_O7, AR_AM_O6, AR_AM_O5, AR_AM_O4, AR_AM_O3, AR_AM_O2, AR_AM_O1, AR_AP_O32, AR_AP_O31, AR_AP_O30, AR_AP_O29, AR_AP_O28
-, AR_AP_O27, AR_AP_O26, AR_AP_O25, AR_AP_O24, AR_AP_O23, AR_AP_O22, AR_AP_O21, AR_AP_O20, AR_AP_O19, AR_AP_O18, AR_AP_O17, AR_AP_O16, AR_AP_O15, AR_AP_O14, AR_AP_O13, AR_AP_O12, AR_AP_O11, AR_AP_O10, AR_AP_O9, AR_AP_O8, AR_AP_O7
-, AR_AP_O6, AR_AP_O5, AR_AP_O4, AR_AP_O3, AR_AP_O2, AR_AP_O1, AR_BUM_O2, AR_BUM_O1, AR_BUP_O2, AR_BUP_O1, AR_CHM_O4, AR_CHM_O3, AR_CHM_O2, AR_CHM_O1, AR_CHP_O4, AR_CHP_O3, AR_CHP_O2, AR_CHP_O1, AR_IDM_O4, AR_IDM_O3, AR_IDM_O2
-, AR_IDM_O1, AR_IDP_O4, AR_IDP_O3, AR_IDP_O2, AR_IDP_O1, AR_INM_O4, AR_INM_O3, AR_INM_O2, AR_INM_O1, AR_LEM_O4, AR_LEM_O3, AR_LEM_O2, AR_LEM_O1, AR_LEP_O4, AR_LEP_O3, AR_LEP_O2, AR_LEP_O1, AR_LKM_O2, AR_LKM_O1, AR_LKP_O2, AR_LKP_O1
-, AR_PRM_O3, AR_PRM_O2, AR_PRM_O1, AR_PRP_O3, AR_PRP_O2, AR_PRP_O1, AR_RDY_O, AR_SHM_O, AR_SZM_O3, AR_SZM_O2, AR_SZM_O1, AR_SZP_O3, AR_SZP_O2, AR_SZP_O1, AR_VDM_O, AR_VDP_O, AW_AM_O32, AW_AM_O31, AW_AM_O30, AW_AM_O29, AW_AM_O28
-, AW_AM_O27, AW_AM_O26, AW_AM_O25, AW_AM_O24, AW_AM_O23, AW_AM_O22, AW_AM_O21, AW_AM_O20, AW_AM_O19, AW_AM_O18, AW_AM_O17, AW_AM_O16, AW_AM_O15, AW_AM_O14, AW_AM_O13, AW_AM_O12, AW_AM_O11, AW_AM_O10, AW_AM_O9, AW_AM_O8, AW_AM_O7
-, AW_AM_O6, AW_AM_O5, AW_AM_O4, AW_AM_O3, AW_AM_O2, AW_AM_O1, AW_AP_O32, AW_AP_O31, AW_AP_O30, AW_AP_O29, AW_AP_O28, AW_AP_O27, AW_AP_O26, AW_AP_O25, AW_AP_O24, AW_AP_O23, AW_AP_O22, AW_AP_O21, AW_AP_O20, AW_AP_O19, AW_AP_O18
-, AW_AP_O17, AW_AP_O16, AW_AP_O15, AW_AP_O14, AW_AP_O13, AW_AP_O12, AW_AP_O11, AW_AP_O10, AW_AP_O9, AW_AP_O8, AW_AP_O7, AW_AP_O6, AW_AP_O5, AW_AP_O4, AW_AP_O3, AW_AP_O2, AW_AP_O1, AW_BUM_O2, AW_BUM_O1, AW_BUP_O2, AW_BUP_O1
-, AW_CHM_O4, AW_CHM_O3, AW_CHM_O2, AW_CHM_O1, AW_CHP_O4, AW_CHP_O3, AW_CHP_O2, AW_CHP_O1, AW_IDM_O4, AW_IDM_O3, AW_IDM_O2, AW_IDM_O1, AW_IDP_O4, AW_IDP_O3, AW_IDP_O2, AW_IDP_O1, AW_INM_O4, AW_INM_O3, AW_INM_O2, AW_INM_O1, AW_LEM_O4
-, AW_LEM_O3, AW_LEM_O2, AW_LEM_O1, AW_LEP_O4, AW_LEP_O3, AW_LEP_O2, AW_LEP_O1, AW_LKM_O2, AW_LKM_O1, AW_LKP_O2, AW_LKP_O1, AW_PRM_O3, AW_PRM_O2, AW_PRM_O1, AW_PRP_O3, AW_PRP_O2, AW_PRP_O1, AW_RDY_O, AW_SHM_O, AW_SZM_O3, AW_SZM_O2
-, AW_SZM_O1, AW_SZP_O3, AW_SZP_O2, AW_SZP_O1, AW_VDM_O, AW_VDP_O, B_IDS_O8, B_IDS_O7, B_IDS_O6, B_IDS_O5, B_IDS_O4, B_IDS_O3, B_IDS_O2, B_IDS_O1, B_RDYM_O, B_RDYP_O, B_RSP_O2, B_RSP_O1, B_VD_O, CDB_PW_O, CDB_RS_O
-, COM_RX_O, COM_TX_O, CS_PW_O, DB_ACK_O, DB_NPD_O, DB_RS_O, DFTS_O8, DFTS_O7, DFTS_O6, DFTS_O5, DFTS_O4, DFTS_O3, DFTS_O2, DFTS_O1, ET_ASC_O8, ET_ASC_O7, ET_ASC_O6, ET_ASC_O5, ET_ASC_O4, ET_ASC_O3, ET_ASC_O2
-, ET_ASC_O1, ET_E_O, ET_EXT_O2, ET_EXT_O1, EVENT_O, FP_DZC_O, FP_IDC_O, FP_IOC_O, FP_IXC_O, FP_OFC_O, FP_UFC_O, JTAG_O, N_CKST_O, N_PMU_O, N_TDO_O, N_VFIQ_O, N_VIRQ_O, N_VRST_O, N_EPST_O, N_IPST_O, P_RD_O32
-, P_RD_O31, P_RD_O30, P_RD_O29, P_RD_O28, P_RD_O27, P_RD_O26, P_RD_O25, P_RD_O24, P_RD_O23, P_RD_O22, P_RD_O21, P_RD_O20, P_RD_O19, P_RD_O18, P_RD_O17, P_RD_O16, P_RD_O15, P_RD_O14, P_RD_O13, P_RD_O12, P_RD_O11
-, P_RD_O10, P_RD_O9, P_RD_O8, P_RD_O7, P_RD_O6, P_RD_O5, P_RD_O4, P_RD_O3, P_RD_O2, P_RD_O1, P_RDY_O, P_VER_O, RD_O64, RD_O63, RD_O62, RD_O61, RD_O60, RD_O59, RD_O58, RD_O57, RD_O56
-, RD_O55, RD_O54, RD_O53, RD_O52, RD_O51, RD_O50, RD_O49, RD_O48, RD_O47, RD_O46, RD_O45, RD_O44, RD_O43, RD_O42, RD_O41, RD_O40, RD_O39, RD_O38, RD_O37, RD_O36, RD_O35
-, RD_O34, RD_O33, RD_O32, RD_O31, RD_O30, RD_O29, RD_O28, RD_O27, RD_O26, RD_O25, RD_O24, RD_O23, RD_O22, RD_O21, RD_O20, RD_O19, RD_O18, RD_O17, RD_O16, RD_O15, RD_O14
-, RD_O13, RD_O12, RD_O11, RD_O10, RD_O9, RD_O8, RD_O7, RD_O6, RD_O5, RD_O4, RD_O3, RD_O2, RD_O1, R_IDS_O8, R_IDS_O7, R_IDS_O6, R_IDS_O5, R_IDS_O4, R_IDS_O3, R_IDS_O2, R_IDS_O1
-, R_LST_O, R_RDYM_O, R_RDYP_O, R_RSP_O2, R_RSP_O1, R_VD_O, SWDO_O, SWDO_E_O, TDO_O, T_CK_O, T_CTL_O, T_DATA_O32, T_DATA_O31, T_DATA_O30, T_DATA_O29, T_DATA_O28, T_DATA_O27, T_DATA_O26, T_DATA_O25, T_DATA_O24, T_DATA_O23
-, T_DATA_O22, T_DATA_O21, T_DATA_O20, T_DATA_O19, T_DATA_O18, T_DATA_O17, T_DATA_O16, T_DATA_O15, T_DATA_O14, T_DATA_O13, T_DATA_O12, T_DATA_O11, T_DATA_O10, T_DATA_O9, T_DATA_O8, T_DATA_O7, T_DATA_O6, T_DATA_O5, T_DATA_O4, T_DATA_O3, T_DATA_O2
-, T_DATA_O1, W_DM_O64, W_DM_O63, W_DM_O62, W_DM_O61, W_DM_O60, W_DM_O59, W_DM_O58, W_DM_O57, W_DM_O56, W_DM_O55, W_DM_O54, W_DM_O53, W_DM_O52, W_DM_O51, W_DM_O50, W_DM_O49, W_DM_O48, W_DM_O47, W_DM_O46, W_DM_O45
-, W_DM_O44, W_DM_O43, W_DM_O42, W_DM_O41, W_DM_O40, W_DM_O39, W_DM_O38, W_DM_O37, W_DM_O36, W_DM_O35, W_DM_O34, W_DM_O33, W_DM_O32, W_DM_O31, W_DM_O30, W_DM_O29, W_DM_O28, W_DM_O27, W_DM_O26, W_DM_O25, W_DM_O24
-, W_DM_O23, W_DM_O22, W_DM_O21, W_DM_O20, W_DM_O19, W_DM_O18, W_DM_O17, W_DM_O16, W_DM_O15, W_DM_O14, W_DM_O13, W_DM_O12, W_DM_O11, W_DM_O10, W_DM_O9, W_DM_O8, W_DM_O7, W_DM_O6, W_DM_O5, W_DM_O4, W_DM_O3
-, W_DM_O2, W_DM_O1, W_DP_O32, W_DP_O31, W_DP_O30, W_DP_O29, W_DP_O28, W_DP_O27, W_DP_O26, W_DP_O25, W_DP_O24, W_DP_O23, W_DP_O22, W_DP_O21, W_DP_O20, W_DP_O19, W_DP_O18, W_DP_O17, W_DP_O16, W_DP_O15, W_DP_O14
-, W_DP_O13, W_DP_O12, W_DP_O11, W_DP_O10, W_DP_O9, W_DP_O8, W_DP_O7, W_DP_O6, W_DP_O5, W_DP_O4, W_DP_O3, W_DP_O2, W_DP_O1, W_IDM_O4, W_IDM_O3, W_IDM_O2, W_IDM_O1, W_IDP_O4, W_IDP_O3, W_IDP_O2, W_IDP_O1
-, W_LSTM_O, W_LSTP_O, W_RDY_O, W_SBM_O8, W_SBM_O7, W_SBM_O6, W_SBM_O5, W_SBM_O4, W_SBM_O3, W_SBM_O2, W_SBM_O1, W_SBP_O4, W_SBP_O3, W_SBP_O2, W_SBP_O1, W_VDM_O, W_VDP_O);
-    output AR_AM_O1;
-    output AR_AM_O10;
-    output AR_AM_O11;
-    output AR_AM_O12;
-    output AR_AM_O13;
-    output AR_AM_O14;
-    output AR_AM_O15;
-    output AR_AM_O16;
-    output AR_AM_O17;
-    output AR_AM_O18;
-    output AR_AM_O19;
-    output AR_AM_O2;
-    output AR_AM_O20;
-    output AR_AM_O21;
-    output AR_AM_O22;
-    output AR_AM_O23;
-    output AR_AM_O24;
-    output AR_AM_O25;
-    output AR_AM_O26;
-    output AR_AM_O27;
-    output AR_AM_O28;
-    output AR_AM_O29;
-    output AR_AM_O3;
-    output AR_AM_O30;
-    output AR_AM_O31;
-    output AR_AM_O32;
-    output AR_AM_O4;
-    output AR_AM_O5;
-    output AR_AM_O6;
-    output AR_AM_O7;
-    output AR_AM_O8;
-    output AR_AM_O9;
-    output AR_AP_O1;
-    output AR_AP_O10;
-    output AR_AP_O11;
-    output AR_AP_O12;
-    output AR_AP_O13;
-    output AR_AP_O14;
-    output AR_AP_O15;
-    output AR_AP_O16;
-    output AR_AP_O17;
-    output AR_AP_O18;
-    output AR_AP_O19;
-    output AR_AP_O2;
-    output AR_AP_O20;
-    output AR_AP_O21;
-    output AR_AP_O22;
-    output AR_AP_O23;
-    output AR_AP_O24;
-    output AR_AP_O25;
-    output AR_AP_O26;
-    output AR_AP_O27;
-    output AR_AP_O28;
-    output AR_AP_O29;
-    output AR_AP_O3;
-    output AR_AP_O30;
-    output AR_AP_O31;
-    output AR_AP_O32;
-    output AR_AP_O4;
-    output AR_AP_O5;
-    output AR_AP_O6;
-    output AR_AP_O7;
-    output AR_AP_O8;
-    output AR_AP_O9;
-    input AR_A_I1;
-    input AR_A_I10;
-    input AR_A_I11;
-    input AR_A_I12;
-    input AR_A_I13;
-    input AR_A_I14;
-    input AR_A_I15;
-    input AR_A_I16;
-    input AR_A_I17;
-    input AR_A_I18;
-    input AR_A_I19;
-    input AR_A_I2;
-    input AR_A_I20;
-    input AR_A_I21;
-    input AR_A_I22;
-    input AR_A_I23;
-    input AR_A_I24;
-    input AR_A_I25;
-    input AR_A_I26;
-    input AR_A_I27;
-    input AR_A_I28;
-    input AR_A_I29;
-    input AR_A_I3;
-    input AR_A_I30;
-    input AR_A_I31;
-    input AR_A_I32;
-    input AR_A_I4;
-    input AR_A_I5;
-    input AR_A_I6;
-    input AR_A_I7;
-    input AR_A_I8;
-    input AR_A_I9;
-    output AR_BUM_O1;
-    output AR_BUM_O2;
-    output AR_BUP_O1;
-    output AR_BUP_O2;
-    input AR_BU_I1;
-    input AR_BU_I2;
-    output AR_CHM_O1;
-    output AR_CHM_O2;
-    output AR_CHM_O3;
-    output AR_CHM_O4;
-    output AR_CHP_O1;
-    output AR_CHP_O2;
-    output AR_CHP_O3;
-    output AR_CHP_O4;
-    input AR_CH_I1;
-    input AR_CH_I2;
-    input AR_CH_I3;
-    input AR_CH_I4;
-    output AR_IDM_O1;
-    output AR_IDM_O2;
-    output AR_IDM_O3;
-    output AR_IDM_O4;
-    output AR_IDP_O1;
-    output AR_IDP_O2;
-    output AR_IDP_O3;
-    output AR_IDP_O4;
-    input AR_IDS_I1;
-    input AR_IDS_I2;
-    input AR_IDS_I3;
-    input AR_IDS_I4;
-    input AR_IDS_I5;
-    input AR_IDS_I6;
-    input AR_IDS_I7;
-    input AR_IDS_I8;
-    output AR_INM_O1;
-    output AR_INM_O2;
-    output AR_INM_O3;
-    output AR_INM_O4;
-    output AR_LEM_O1;
-    output AR_LEM_O2;
-    output AR_LEM_O3;
-    output AR_LEM_O4;
-    output AR_LEP_O1;
-    output AR_LEP_O2;
-    output AR_LEP_O3;
-    output AR_LEP_O4;
-    input AR_LE_I1;
-    input AR_LE_I2;
-    input AR_LE_I3;
-    input AR_LE_I4;
-    output AR_LKM_O1;
-    output AR_LKM_O2;
-    output AR_LKP_O1;
-    output AR_LKP_O2;
-    input AR_LK_I1;
-    input AR_LK_I2;
-    output AR_PRM_O1;
-    output AR_PRM_O2;
-    output AR_PRM_O3;
-    output AR_PRP_O1;
-    output AR_PRP_O2;
-    output AR_PRP_O3;
-    input AR_PR_I1;
-    input AR_PR_I2;
-    input AR_PR_I3;
-    output AR_RDY_O;
-    input AR_RYM_I;
-    input AR_RYP_I;
-    output AR_SHM_O;
-    output AR_SZM_O1;
-    output AR_SZM_O2;
-    output AR_SZM_O3;
-    output AR_SZP_O1;
-    output AR_SZP_O2;
-    output AR_SZP_O3;
-    input AR_SZ_I1;
-    input AR_SZ_I2;
-    input AR_SZ_I3;
-    output AR_VDM_O;
-    output AR_VDP_O;
-    input AR_VD_I;
-    input AT_RS_I;
-    output AW_AM_O1;
-    output AW_AM_O10;
-    output AW_AM_O11;
-    output AW_AM_O12;
-    output AW_AM_O13;
-    output AW_AM_O14;
-    output AW_AM_O15;
-    output AW_AM_O16;
-    output AW_AM_O17;
-    output AW_AM_O18;
-    output AW_AM_O19;
-    output AW_AM_O2;
-    output AW_AM_O20;
-    output AW_AM_O21;
-    output AW_AM_O22;
-    output AW_AM_O23;
-    output AW_AM_O24;
-    output AW_AM_O25;
-    output AW_AM_O26;
-    output AW_AM_O27;
-    output AW_AM_O28;
-    output AW_AM_O29;
-    output AW_AM_O3;
-    output AW_AM_O30;
-    output AW_AM_O31;
-    output AW_AM_O32;
-    output AW_AM_O4;
-    output AW_AM_O5;
-    output AW_AM_O6;
-    output AW_AM_O7;
-    output AW_AM_O8;
-    output AW_AM_O9;
-    output AW_AP_O1;
-    output AW_AP_O10;
-    output AW_AP_O11;
-    output AW_AP_O12;
-    output AW_AP_O13;
-    output AW_AP_O14;
-    output AW_AP_O15;
-    output AW_AP_O16;
-    output AW_AP_O17;
-    output AW_AP_O18;
-    output AW_AP_O19;
-    output AW_AP_O2;
-    output AW_AP_O20;
-    output AW_AP_O21;
-    output AW_AP_O22;
-    output AW_AP_O23;
-    output AW_AP_O24;
-    output AW_AP_O25;
-    output AW_AP_O26;
-    output AW_AP_O27;
-    output AW_AP_O28;
-    output AW_AP_O29;
-    output AW_AP_O3;
-    output AW_AP_O30;
-    output AW_AP_O31;
-    output AW_AP_O32;
-    output AW_AP_O4;
-    output AW_AP_O5;
-    output AW_AP_O6;
-    output AW_AP_O7;
-    output AW_AP_O8;
-    output AW_AP_O9;
-    input AW_A_I1;
-    input AW_A_I10;
-    input AW_A_I11;
-    input AW_A_I12;
-    input AW_A_I13;
-    input AW_A_I14;
-    input AW_A_I15;
-    input AW_A_I16;
-    input AW_A_I17;
-    input AW_A_I18;
-    input AW_A_I19;
-    input AW_A_I2;
-    input AW_A_I20;
-    input AW_A_I21;
-    input AW_A_I22;
-    input AW_A_I23;
-    input AW_A_I24;
-    input AW_A_I25;
-    input AW_A_I26;
-    input AW_A_I27;
-    input AW_A_I28;
-    input AW_A_I29;
-    input AW_A_I3;
-    input AW_A_I30;
-    input AW_A_I31;
-    input AW_A_I32;
-    input AW_A_I4;
-    input AW_A_I5;
-    input AW_A_I6;
-    input AW_A_I7;
-    input AW_A_I8;
-    input AW_A_I9;
-    output AW_BUM_O1;
-    output AW_BUM_O2;
-    output AW_BUP_O1;
-    output AW_BUP_O2;
-    input AW_BU_I1;
-    input AW_BU_I2;
-    output AW_CHM_O1;
-    output AW_CHM_O2;
-    output AW_CHM_O3;
-    output AW_CHM_O4;
-    output AW_CHP_O1;
-    output AW_CHP_O2;
-    output AW_CHP_O3;
-    output AW_CHP_O4;
-    input AW_CH_I1;
-    input AW_CH_I2;
-    input AW_CH_I3;
-    input AW_CH_I4;
-    output AW_IDM_O1;
-    output AW_IDM_O2;
-    output AW_IDM_O3;
-    output AW_IDM_O4;
-    output AW_IDP_O1;
-    output AW_IDP_O2;
-    output AW_IDP_O3;
-    output AW_IDP_O4;
-    input AW_IDS_I1;
-    input AW_IDS_I2;
-    input AW_IDS_I3;
-    input AW_IDS_I4;
-    input AW_IDS_I5;
-    input AW_IDS_I6;
-    input AW_IDS_I7;
-    input AW_IDS_I8;
-    output AW_INM_O1;
-    output AW_INM_O2;
-    output AW_INM_O3;
-    output AW_INM_O4;
-    output AW_LEM_O1;
-    output AW_LEM_O2;
-    output AW_LEM_O3;
-    output AW_LEM_O4;
-    output AW_LEP_O1;
-    output AW_LEP_O2;
-    output AW_LEP_O3;
-    output AW_LEP_O4;
-    input AW_LE_I1;
-    input AW_LE_I2;
-    input AW_LE_I3;
-    input AW_LE_I4;
-    output AW_LKM_O1;
-    output AW_LKM_O2;
-    output AW_LKP_O1;
-    output AW_LKP_O2;
-    input AW_LK_I1;
-    input AW_LK_I2;
-    output AW_PRM_O1;
-    output AW_PRM_O2;
-    output AW_PRM_O3;
-    output AW_PRP_O1;
-    output AW_PRP_O2;
-    output AW_PRP_O3;
-    input AW_PR_I1;
-    input AW_PR_I2;
-    input AW_PR_I3;
-    output AW_RDY_O;
-    input AW_RYM_I;
-    input AW_RYP_I;
-    output AW_SHM_O;
-    output AW_SZM_O1;
-    output AW_SZM_O2;
-    output AW_SZM_O3;
-    output AW_SZP_O1;
-    output AW_SZP_O2;
-    output AW_SZP_O3;
-    input AW_SZ_I1;
-    input AW_SZ_I2;
-    input AW_SZ_I3;
-    output AW_VDM_O;
-    output AW_VDP_O;
-    input AW_VD_I;
-    input A_CKEM_I;
-    input A_CKEP_I;
-    input A_CKES_I;
-    input B_IDM_I1;
-    input B_IDM_I2;
-    input B_IDM_I3;
-    input B_IDM_I4;
-    input B_IDP_I1;
-    input B_IDP_I2;
-    input B_IDP_I3;
-    input B_IDP_I4;
-    output B_IDS_O1;
-    output B_IDS_O2;
-    output B_IDS_O3;
-    output B_IDS_O4;
-    output B_IDS_O5;
-    output B_IDS_O6;
-    output B_IDS_O7;
-    output B_IDS_O8;
-    output B_RDYM_O;
-    output B_RDYP_O;
-    input B_RDY_I;
-    input B_RSPM_I1;
-    input B_RSPM_I2;
-    input B_RSPP_I1;
-    input B_RSPP_I2;
-    output B_RSP_O1;
-    output B_RSP_O2;
-    input B_VDM_I;
-    input B_VDP_I;
-    output B_VD_O;
-    input CDB_PW_I;
-    output CDB_PW_O;
-    input CDB_RS_I;
-    output CDB_RS_O;
-    input CFG_EE_I;
-    input CFG_IE_I;
-    input CFG_NM_I;
-    input CK_I;
-    output COM_RX_O;
-    output COM_TX_O;
-    input CS_PW_I;
-    output CS_PW_O;
-    output DB_ACK_O;
-    input DB_E_I;
-    input DB_NCK_I;
-    output DB_NPD_O;
-    input DB_RAV_I;
-    input DB_RA_I1;
-    input DB_RA_I10;
-    input DB_RA_I11;
-    input DB_RA_I12;
-    input DB_RA_I13;
-    input DB_RA_I14;
-    input DB_RA_I15;
-    input DB_RA_I16;
-    input DB_RA_I17;
-    input DB_RA_I18;
-    input DB_RA_I19;
-    input DB_RA_I2;
-    input DB_RA_I20;
-    input DB_RA_I3;
-    input DB_RA_I4;
-    input DB_RA_I5;
-    input DB_RA_I6;
-    input DB_RA_I7;
-    input DB_RA_I8;
-    input DB_RA_I9;
-    output DB_RS_O;
-    input DB_SAV_I;
-    input DB_SA_I1;
-    input DB_SA_I10;
-    input DB_SA_I11;
-    input DB_SA_I12;
-    input DB_SA_I13;
-    input DB_SA_I14;
-    input DB_SA_I15;
-    input DB_SA_I16;
-    input DB_SA_I17;
-    input DB_SA_I18;
-    input DB_SA_I19;
-    input DB_SA_I2;
-    input DB_SA_I20;
-    input DB_SA_I3;
-    input DB_SA_I4;
-    input DB_SA_I5;
-    input DB_SA_I6;
-    input DB_SA_I7;
-    input DB_SA_I8;
-    input DB_SA_I9;
-    input DEV_E_I;
-    input DFTS_I1;
-    input DFTS_I2;
-    input DFTS_I3;
-    input DFTS_I4;
-    input DFTS_I5;
-    input DFTS_I6;
-    input DFTS_I7;
-    input DFTS_I8;
-    output DFTS_O1;
-    output DFTS_O2;
-    output DFTS_O3;
-    output DFTS_O4;
-    output DFTS_O5;
-    output DFTS_O6;
-    output DFTS_O7;
-    output DFTS_O8;
-    input ERR_R_I;
-    output ET_ASC_O1;
-    output ET_ASC_O2;
-    output ET_ASC_O3;
-    output ET_ASC_O4;
-    output ET_ASC_O5;
-    output ET_ASC_O6;
-    output ET_ASC_O7;
-    output ET_ASC_O8;
-    output ET_EXT_O1;
-    output ET_EXT_O2;
-    output ET_E_O;
-    input EVENT_I;
-    output EVENT_O;
-    input E_DB_I;
-    output FP_DZC_O;
-    output FP_IDC_O;
-    output FP_IOC_O;
-    output FP_IXC_O;
-    output FP_OFC_O;
-    output FP_UFC_O;
-    input GID_I1;
-    input GID_I2;
-    input GID_I3;
-    input GID_I4;
-    input INIT_P_I;
-    input INIT_R_I;
-    output JTAG_O;
-    input LOC_R_I;
-    input NCPUH_I;
-    input NET_RS_I;
-    output N_CKST_O;
-    output N_EPST_O;
-    input N_FIQ_I;
-    input N_IDE_I;
-    output N_IPST_O;
-    input N_IRQ_I;
-    output N_PMU_O;
-    input N_PRS_I;
-    input N_RS_I;
-    input N_SPRS_I;
-    output N_TDO_O;
-    input N_TRS_I;
-    output N_VFIQ_O;
-    output N_VIRQ_O;
-    output N_VRST_O;
-    input PLVL_I;
-    input PPV_BS_I1;
-    input PPV_BS_I10;
-    input PPV_BS_I11;
-    input PPV_BS_I12;
-    input PPV_BS_I13;
-    input PPV_BS_I14;
-    input PPV_BS_I15;
-    input PPV_BS_I16;
-    input PPV_BS_I17;
-    input PPV_BS_I18;
-    input PPV_BS_I19;
-    input PPV_BS_I2;
-    input PPV_BS_I20;
-    input PPV_BS_I3;
-    input PPV_BS_I4;
-    input PPV_BS_I5;
-    input PPV_BS_I6;
-    input PPV_BS_I7;
-    input PPV_BS_I8;
-    input PPV_BS_I9;
-    input PPV_SZ_I1;
-    input PPV_SZ_I2;
-    input PPV_SZ_I3;
-    input PPV_SZ_I4;
-    input PPV_SZ_I5;
-    input PPX_BS_I1;
-    input PPX_BS_I10;
-    input PPX_BS_I11;
-    input PPX_BS_I12;
-    input PPX_BS_I13;
-    input PPX_BS_I14;
-    input PPX_BS_I15;
-    input PPX_BS_I16;
-    input PPX_BS_I17;
-    input PPX_BS_I18;
-    input PPX_BS_I19;
-    input PPX_BS_I2;
-    input PPX_BS_I20;
-    input PPX_BS_I3;
-    input PPX_BS_I4;
-    input PPX_BS_I5;
-    input PPX_BS_I6;
-    input PPX_BS_I7;
-    input PPX_BS_I8;
-    input PPX_BS_I9;
-    input PPX_SZ_I1;
-    input PPX_SZ_I2;
-    input PPX_SZ_I3;
-    input PPX_SZ_I4;
-    input PPX_SZ_I5;
-    input PW_D_I1;
-    input PW_D_I10;
-    input PW_D_I11;
-    input PW_D_I12;
-    input PW_D_I13;
-    input PW_D_I14;
-    input PW_D_I15;
-    input PW_D_I16;
-    input PW_D_I17;
-    input PW_D_I18;
-    input PW_D_I19;
-    input PW_D_I2;
-    input PW_D_I20;
-    input PW_D_I21;
-    input PW_D_I22;
-    input PW_D_I23;
-    input PW_D_I24;
-    input PW_D_I25;
-    input PW_D_I26;
-    input PW_D_I27;
-    input PW_D_I28;
-    input PW_D_I29;
-    input PW_D_I3;
-    input PW_D_I30;
-    input PW_D_I31;
-    input PW_D_I32;
-    input PW_D_I4;
-    input PW_D_I5;
-    input PW_D_I6;
-    input PW_D_I7;
-    input PW_D_I8;
-    input PW_D_I9;
-    input PW_I;
-    input P_A_I1;
-    input P_A_I10;
-    input P_A_I11;
-    input P_A_I12;
-    input P_A_I13;
-    input P_A_I14;
-    input P_A_I15;
-    input P_A_I16;
-    input P_A_I17;
-    input P_A_I18;
-    input P_A_I19;
-    input P_A_I2;
-    input P_A_I20;
-    input P_A_I21;
-    input P_A_I22;
-    input P_A_I23;
-    input P_A_I24;
-    input P_A_I25;
-    input P_A_I26;
-    input P_A_I27;
-    input P_A_I28;
-    input P_A_I29;
-    input P_A_I3;
-    input P_A_I4;
-    input P_A_I5;
-    input P_A_I6;
-    input P_A_I7;
-    input P_A_I8;
-    input P_A_I9;
-    input P_CK_E_I;
-    input P_CK_I;
-    input P_ECC_I;
-    input P_E_I;
-    output P_RDY_O;
-    output P_RD_O1;
-    output P_RD_O10;
-    output P_RD_O11;
-    output P_RD_O12;
-    output P_RD_O13;
-    output P_RD_O14;
-    output P_RD_O15;
-    output P_RD_O16;
-    output P_RD_O17;
-    output P_RD_O18;
-    output P_RD_O19;
-    output P_RD_O2;
-    output P_RD_O20;
-    output P_RD_O21;
-    output P_RD_O22;
-    output P_RD_O23;
-    output P_RD_O24;
-    output P_RD_O25;
-    output P_RD_O26;
-    output P_RD_O27;
-    output P_RD_O28;
-    output P_RD_O29;
-    output P_RD_O3;
-    output P_RD_O30;
-    output P_RD_O31;
-    output P_RD_O32;
-    output P_RD_O4;
-    output P_RD_O5;
-    output P_RD_O6;
-    output P_RD_O7;
-    output P_RD_O8;
-    output P_RD_O9;
-    input P_RS_I;
-    input P_SEL_I;
-    output P_VER_O;
-    input RAMCTL_I1;
-    input RAMCTL_I2;
-    input RAMCTL_I3;
-    input RAMCTL_I4;
-    input RAMCTL_I5;
-    input RAMCTL_I6;
-    input RAMCTL_I7;
-    input RAMCTL_I8;
-    output RD_O1;
-    output RD_O10;
-    output RD_O11;
-    output RD_O12;
-    output RD_O13;
-    output RD_O14;
-    output RD_O15;
-    output RD_O16;
-    output RD_O17;
-    output RD_O18;
-    output RD_O19;
-    output RD_O2;
-    output RD_O20;
-    output RD_O21;
-    output RD_O22;
-    output RD_O23;
-    output RD_O24;
-    output RD_O25;
-    output RD_O26;
-    output RD_O27;
-    output RD_O28;
-    output RD_O29;
-    output RD_O3;
-    output RD_O30;
-    output RD_O31;
-    output RD_O32;
-    output RD_O33;
-    output RD_O34;
-    output RD_O35;
-    output RD_O36;
-    output RD_O37;
-    output RD_O38;
-    output RD_O39;
-    output RD_O4;
-    output RD_O40;
-    output RD_O41;
-    output RD_O42;
-    output RD_O43;
-    output RD_O44;
-    output RD_O45;
-    output RD_O46;
-    output RD_O47;
-    output RD_O48;
-    output RD_O49;
-    output RD_O5;
-    output RD_O50;
-    output RD_O51;
-    output RD_O52;
-    output RD_O53;
-    output RD_O54;
-    output RD_O55;
-    output RD_O56;
-    output RD_O57;
-    output RD_O58;
-    output RD_O59;
-    output RD_O6;
-    output RD_O60;
-    output RD_O61;
-    output RD_O62;
-    output RD_O63;
-    output RD_O64;
-    output RD_O7;
-    output RD_O8;
-    output RD_O9;
-    input RS_BYP_I;
-    input R_DM_I1;
-    input R_DM_I10;
-    input R_DM_I11;
-    input R_DM_I12;
-    input R_DM_I13;
-    input R_DM_I14;
-    input R_DM_I15;
-    input R_DM_I16;
-    input R_DM_I17;
-    input R_DM_I18;
-    input R_DM_I19;
-    input R_DM_I2;
-    input R_DM_I20;
-    input R_DM_I21;
-    input R_DM_I22;
-    input R_DM_I23;
-    input R_DM_I24;
-    input R_DM_I25;
-    input R_DM_I26;
-    input R_DM_I27;
-    input R_DM_I28;
-    input R_DM_I29;
-    input R_DM_I3;
-    input R_DM_I30;
-    input R_DM_I31;
-    input R_DM_I32;
-    input R_DM_I33;
-    input R_DM_I34;
-    input R_DM_I35;
-    input R_DM_I36;
-    input R_DM_I37;
-    input R_DM_I38;
-    input R_DM_I39;
-    input R_DM_I4;
-    input R_DM_I40;
-    input R_DM_I41;
-    input R_DM_I42;
-    input R_DM_I43;
-    input R_DM_I44;
-    input R_DM_I45;
-    input R_DM_I46;
-    input R_DM_I47;
-    input R_DM_I48;
-    input R_DM_I49;
-    input R_DM_I5;
-    input R_DM_I50;
-    input R_DM_I51;
-    input R_DM_I52;
-    input R_DM_I53;
-    input R_DM_I54;
-    input R_DM_I55;
-    input R_DM_I56;
-    input R_DM_I57;
-    input R_DM_I58;
-    input R_DM_I59;
-    input R_DM_I6;
-    input R_DM_I60;
-    input R_DM_I61;
-    input R_DM_I62;
-    input R_DM_I63;
-    input R_DM_I64;
-    input R_DM_I7;
-    input R_DM_I8;
-    input R_DM_I9;
-    input R_DP_I1;
-    input R_DP_I10;
-    input R_DP_I11;
-    input R_DP_I12;
-    input R_DP_I13;
-    input R_DP_I14;
-    input R_DP_I15;
-    input R_DP_I16;
-    input R_DP_I17;
-    input R_DP_I18;
-    input R_DP_I19;
-    input R_DP_I2;
-    input R_DP_I20;
-    input R_DP_I21;
-    input R_DP_I22;
-    input R_DP_I23;
-    input R_DP_I24;
-    input R_DP_I25;
-    input R_DP_I26;
-    input R_DP_I27;
-    input R_DP_I28;
-    input R_DP_I29;
-    input R_DP_I3;
-    input R_DP_I30;
-    input R_DP_I31;
-    input R_DP_I32;
-    input R_DP_I4;
-    input R_DP_I5;
-    input R_DP_I6;
-    input R_DP_I7;
-    input R_DP_I8;
-    input R_DP_I9;
-    input R_IDM_I1;
-    input R_IDM_I2;
-    input R_IDM_I3;
-    input R_IDM_I4;
-    input R_IDP_I1;
-    input R_IDP_I2;
-    input R_IDP_I3;
-    input R_IDP_I4;
-    output R_IDS_O1;
-    output R_IDS_O2;
-    output R_IDS_O3;
-    output R_IDS_O4;
-    output R_IDS_O5;
-    output R_IDS_O6;
-    output R_IDS_O7;
-    output R_IDS_O8;
-    input R_LSTM_I;
-    input R_LSTP_I;
-    output R_LST_O;
-    output R_RDYM_O;
-    output R_RDYP_O;
-    input R_RDY_I;
-    input R_RSPM_I1;
-    input R_RSPM_I2;
-    input R_RSPP_I1;
-    input R_RSPP_I2;
-    output R_RSP_O1;
-    output R_RSP_O2;
-    input R_VDM_I;
-    input R_VDP_I;
-    output R_VD_O;
-    input SE_I;
-    output SWDO_E_O;
-    output SWDO_O;
-    input SW_CK_I;
-    input SW_DI_I;
-    output TDO_O;
-    input TE_INI_I;
-    output T_CK_O;
-    output T_CTL_O;
-    output T_DATA_O1;
-    output T_DATA_O10;
-    output T_DATA_O11;
-    output T_DATA_O12;
-    output T_DATA_O13;
-    output T_DATA_O14;
-    output T_DATA_O15;
-    output T_DATA_O16;
-    output T_DATA_O17;
-    output T_DATA_O18;
-    output T_DATA_O19;
-    output T_DATA_O2;
-    output T_DATA_O20;
-    output T_DATA_O21;
-    output T_DATA_O22;
-    output T_DATA_O23;
-    output T_DATA_O24;
-    output T_DATA_O25;
-    output T_DATA_O26;
-    output T_DATA_O27;
-    output T_DATA_O28;
-    output T_DATA_O29;
-    output T_DATA_O3;
-    output T_DATA_O30;
-    output T_DATA_O31;
-    output T_DATA_O32;
-    output T_DATA_O4;
-    output T_DATA_O5;
-    output T_DATA_O6;
-    output T_DATA_O7;
-    output T_DATA_O8;
-    output T_DATA_O9;
-    input T_DI_I;
-    input VINI_I;
-    output W_DM_O1;
-    output W_DM_O10;
-    output W_DM_O11;
-    output W_DM_O12;
-    output W_DM_O13;
-    output W_DM_O14;
-    output W_DM_O15;
-    output W_DM_O16;
-    output W_DM_O17;
-    output W_DM_O18;
-    output W_DM_O19;
-    output W_DM_O2;
-    output W_DM_O20;
-    output W_DM_O21;
-    output W_DM_O22;
-    output W_DM_O23;
-    output W_DM_O24;
-    output W_DM_O25;
-    output W_DM_O26;
-    output W_DM_O27;
-    output W_DM_O28;
-    output W_DM_O29;
-    output W_DM_O3;
-    output W_DM_O30;
-    output W_DM_O31;
-    output W_DM_O32;
-    output W_DM_O33;
-    output W_DM_O34;
-    output W_DM_O35;
-    output W_DM_O36;
-    output W_DM_O37;
-    output W_DM_O38;
-    output W_DM_O39;
-    output W_DM_O4;
-    output W_DM_O40;
-    output W_DM_O41;
-    output W_DM_O42;
-    output W_DM_O43;
-    output W_DM_O44;
-    output W_DM_O45;
-    output W_DM_O46;
-    output W_DM_O47;
-    output W_DM_O48;
-    output W_DM_O49;
-    output W_DM_O5;
-    output W_DM_O50;
-    output W_DM_O51;
-    output W_DM_O52;
-    output W_DM_O53;
-    output W_DM_O54;
-    output W_DM_O55;
-    output W_DM_O56;
-    output W_DM_O57;
-    output W_DM_O58;
-    output W_DM_O59;
-    output W_DM_O6;
-    output W_DM_O60;
-    output W_DM_O61;
-    output W_DM_O62;
-    output W_DM_O63;
-    output W_DM_O64;
-    output W_DM_O7;
-    output W_DM_O8;
-    output W_DM_O9;
-    output W_DP_O1;
-    output W_DP_O10;
-    output W_DP_O11;
-    output W_DP_O12;
-    output W_DP_O13;
-    output W_DP_O14;
-    output W_DP_O15;
-    output W_DP_O16;
-    output W_DP_O17;
-    output W_DP_O18;
-    output W_DP_O19;
-    output W_DP_O2;
-    output W_DP_O20;
-    output W_DP_O21;
-    output W_DP_O22;
-    output W_DP_O23;
-    output W_DP_O24;
-    output W_DP_O25;
-    output W_DP_O26;
-    output W_DP_O27;
-    output W_DP_O28;
-    output W_DP_O29;
-    output W_DP_O3;
-    output W_DP_O30;
-    output W_DP_O31;
-    output W_DP_O32;
-    output W_DP_O4;
-    output W_DP_O5;
-    output W_DP_O6;
-    output W_DP_O7;
-    output W_DP_O8;
-    output W_DP_O9;
-    input W_D_I1;
-    input W_D_I10;
-    input W_D_I11;
-    input W_D_I12;
-    input W_D_I13;
-    input W_D_I14;
-    input W_D_I15;
-    input W_D_I16;
-    input W_D_I17;
-    input W_D_I18;
-    input W_D_I19;
-    input W_D_I2;
-    input W_D_I20;
-    input W_D_I21;
-    input W_D_I22;
-    input W_D_I23;
-    input W_D_I24;
-    input W_D_I25;
-    input W_D_I26;
-    input W_D_I27;
-    input W_D_I28;
-    input W_D_I29;
-    input W_D_I3;
-    input W_D_I30;
-    input W_D_I31;
-    input W_D_I32;
-    input W_D_I33;
-    input W_D_I34;
-    input W_D_I35;
-    input W_D_I36;
-    input W_D_I37;
-    input W_D_I38;
-    input W_D_I39;
-    input W_D_I4;
-    input W_D_I40;
-    input W_D_I41;
-    input W_D_I42;
-    input W_D_I43;
-    input W_D_I44;
-    input W_D_I45;
-    input W_D_I46;
-    input W_D_I47;
-    input W_D_I48;
-    input W_D_I49;
-    input W_D_I5;
-    input W_D_I50;
-    input W_D_I51;
-    input W_D_I52;
-    input W_D_I53;
-    input W_D_I54;
-    input W_D_I55;
-    input W_D_I56;
-    input W_D_I57;
-    input W_D_I58;
-    input W_D_I59;
-    input W_D_I6;
-    input W_D_I60;
-    input W_D_I61;
-    input W_D_I62;
-    input W_D_I63;
-    input W_D_I64;
-    input W_D_I7;
-    input W_D_I8;
-    input W_D_I9;
-    output W_IDM_O1;
-    output W_IDM_O2;
-    output W_IDM_O3;
-    output W_IDM_O4;
-    output W_IDP_O1;
-    output W_IDP_O2;
-    output W_IDP_O3;
-    output W_IDP_O4;
-    input W_IDS_I1;
-    input W_IDS_I2;
-    input W_IDS_I3;
-    input W_IDS_I4;
-    input W_IDS_I5;
-    input W_IDS_I6;
-    input W_IDS_I7;
-    input W_IDS_I8;
-    output W_LSTM_O;
-    output W_LSTP_O;
-    input W_LST_I;
-    output W_RDY_O;
-    input W_RYM_I;
-    input W_RYP_I;
-    output W_SBM_O1;
-    output W_SBM_O2;
-    output W_SBM_O3;
-    output W_SBM_O4;
-    output W_SBM_O5;
-    output W_SBM_O6;
-    output W_SBM_O7;
-    output W_SBM_O8;
-    output W_SBP_O1;
-    output W_SBP_O2;
-    output W_SBP_O3;
-    output W_SBP_O4;
-    input W_SBS_I1;
-    input W_SBS_I2;
-    input W_SBS_I3;
-    input W_SBS_I4;
-    input W_SBS_I5;
-    input W_SBS_I6;
-    input W_SBS_I7;
-    input W_SBS_I8;
-    output W_VDM_O;
-    output W_VDP_O;
-    input W_VD_I;
-endmodule
-
-(* blackbox *)
-module NX_R5_L_WRAP(CLKIN, nRESET0, nSYSPORESET, nCPUHALT0, DBGNOCLKSTOP, nCLKSTOPPED0, nWFEPIPESTOPPED0, nWFIPIPESTOPPED0, EVENTI0, EVENTO0, VINITHI0, CFGEE, CFGIE, INITRAMA0, LOCZRAMA0, TEINIT, CFGNMFI0, PARECCENRAM0, PARITYLEVEL, ERRENRAM0, INITPPX0
-, nFIQ0, nIRQ0, nPMUIRQ0, ACLKENM0, AWREADYM0, AWSHAREM0, AWVALIDM0, WLASTM0, WREADYM0, WVALIDM0, BREADYM0, BVALIDM0, ARREADYM0, ARSHAREM0, ARVALIDM0, RLASTM0, RREADYM0, RVALIDM0, ACLKENS0, AWREADYS0, AWVALIDS0
-, WLASTS0, WREADYS0, WVALIDS0, BREADYS0, BVALIDS0, ARREADYS0, ARVALIDS0, RLASTS0, RREADYS0, RVALIDS0, ACLKENP0, AWVALIDP0, AWREADYP0, WLASTP0, WVALIDP0, WREADYP0, BVALIDP0, BREADYP0, ARVALIDP0, ARREADYP0, RLASTP0
-, RVALIDP0, RREADYP0, DBGEN0, NIDEN0, EDBGRQ0, DBGACK0, DBGRSTREQ0, COMMRX0, COMMTX0, DBGNOPWRDWN, DBGROMADDRV, DBGSELFADDRV0, nETMPORESET, ETMEN0, nVALIRQ0, nVALFIQ0, nVALRESET0, FPIXC0, FPOFC0, FPUFC0, FPIOC0
-, FPDZC0, FPIDC0, ATRESETn, TRACECLK, TRACECTL, PCLKSYS, PCLKENSYS, PRESETSYSn, PENABLESYS, PREADYSYS, PSELSYS, PSLVERRSYS, PWRITESYS, CDBGPWRUPACK, CDBGPWRUPREQ, CDBGRSTACK, CDBGRSTREQ, CSYSPWRUPACK, CSYSPWRUPREQ, DEVICEEN, JTAGNSW
-, nPOTRST, nTDOEN, nTRST, SWCLKTCK, SWDITMS, SWDO, SWDOEN, TDI, TDO, PPXBASE0, PPXSIZE0, PPVBASE0, PPVSIZE0, AWADDRM0, AWBURSTM0, AWCACHEM0, AWIDM0, AWLENM0, AWLOCKM0, AWPROTM0, AWSIZEM0
-, AWINNERM0, WDATAM0, WIDM0, WSTRBM0, BIDM0, BRESPM0, ARADDRM0, ARBURSTM0, ARCACHEM0, ARIDM0, ARLENM0, ARLOCKM0, ARPROTM0, ARSIZEM0, ARINNERM0, RDATAM0, RIDM0, RRESPM0, AWADDRS0, AWBURSTS0, AWCACHES0
-, AWIDS0, AWLENS0, AWLOCKS0, AWPROTS0, AWSIZES0, WDATAS0, WIDS0, WSTRBS0, BIDS0, BRESPS0, ARADDRS0, ARBURSTS0, ARCACHES0, ARIDS0, ARLENS0, ARLOCKS0, ARPROTS0, ARSIZES0, RDATAS0, RIDS0, RRESPS0
-, AWIDP0, AWADDRP0, AWLENP0, AWSIZEP0, AWBURSTP0, AWLOCKP0, AWCACHEP0, AWPROTP0, WIDP0, WDATAP0, WSTRBP0, BIDP0, BRESPP0, ARIDP0, ARADDRP0, ARLENP0, ARSIZEP0, ARBURSTP0, ARLOCKP0, ARCACHEP0, ARPROTP0
-, RIDP0, RDATAP0, RRESPP0, DBGROMADDR, DBGSELFADDR0, ETMASICCTL0, ETMEXTOUT0, TRACEDATA, PADDRSYS, PRDATASYS, PWDATASYS, GROUPID);
-    input ACLKENM0;
-    input ACLKENP0;
-    input ACLKENS0;
-    output [31:0] ARADDRM0;
-    output [31:0] ARADDRP0;
-    input [31:0] ARADDRS0;
-    output [1:0] ARBURSTM0;
-    output [1:0] ARBURSTP0;
-    input [1:0] ARBURSTS0;
-    output [3:0] ARCACHEM0;
-    output [3:0] ARCACHEP0;
-    input [3:0] ARCACHES0;
-    output [3:0] ARIDM0;
-    output [3:0] ARIDP0;
-    input [7:0] ARIDS0;
-    output [3:0] ARINNERM0;
-    output [3:0] ARLENM0;
-    output [3:0] ARLENP0;
-    input [3:0] ARLENS0;
-    output [1:0] ARLOCKM0;
-    output [1:0] ARLOCKP0;
-    input [1:0] ARLOCKS0;
-    output [2:0] ARPROTM0;
-    output [2:0] ARPROTP0;
-    input [2:0] ARPROTS0;
-    input ARREADYM0;
-    input ARREADYP0;
-    output ARREADYS0;
-    output ARSHAREM0;
-    output [2:0] ARSIZEM0;
-    output [2:0] ARSIZEP0;
-    input [2:0] ARSIZES0;
-    output ARVALIDM0;
-    output ARVALIDP0;
-    input ARVALIDS0;
-    input ATRESETn;
-    output [31:0] AWADDRM0;
-    output [31:0] AWADDRP0;
-    input [31:0] AWADDRS0;
-    output [1:0] AWBURSTM0;
-    output [1:0] AWBURSTP0;
-    input [1:0] AWBURSTS0;
-    output [3:0] AWCACHEM0;
-    output [3:0] AWCACHEP0;
-    input [3:0] AWCACHES0;
-    output [3:0] AWIDM0;
-    output [3:0] AWIDP0;
-    input [7:0] AWIDS0;
-    output [3:0] AWINNERM0;
-    output [3:0] AWLENM0;
-    output [3:0] AWLENP0;
-    input [3:0] AWLENS0;
-    output [1:0] AWLOCKM0;
-    output [1:0] AWLOCKP0;
-    input [1:0] AWLOCKS0;
-    output [2:0] AWPROTM0;
-    output [2:0] AWPROTP0;
-    input [2:0] AWPROTS0;
-    input AWREADYM0;
-    input AWREADYP0;
-    output AWREADYS0;
-    output AWSHAREM0;
-    output [2:0] AWSIZEM0;
-    output [2:0] AWSIZEP0;
-    input [2:0] AWSIZES0;
-    output AWVALIDM0;
-    output AWVALIDP0;
-    input AWVALIDS0;
-    input [3:0] BIDM0;
-    input [3:0] BIDP0;
-    output [7:0] BIDS0;
-    output BREADYM0;
-    output BREADYP0;
-    input BREADYS0;
-    input [1:0] BRESPM0;
-    input [1:0] BRESPP0;
-    output [1:0] BRESPS0;
-    input BVALIDM0;
-    input BVALIDP0;
-    output BVALIDS0;
-    input CDBGPWRUPACK;
-    output CDBGPWRUPREQ;
-    input CDBGRSTACK;
-    output CDBGRSTREQ;
-    input CFGEE;
-    input CFGIE;
-    input CFGNMFI0;
-    input CLKIN;
-    output COMMRX0;
-    output COMMTX0;
-    input CSYSPWRUPACK;
-    output CSYSPWRUPREQ;
-    output DBGACK0;
-    input DBGEN0;
-    input DBGNOCLKSTOP;
-    output DBGNOPWRDWN;
-    input [19:0] DBGROMADDR;
-    input DBGROMADDRV;
-    output DBGRSTREQ0;
-    input [19:0] DBGSELFADDR0;
-    input DBGSELFADDRV0;
-    input DEVICEEN;
-    input EDBGRQ0;
-    input ERRENRAM0;
-    output [7:0] ETMASICCTL0;
-    output ETMEN0;
-    output [1:0] ETMEXTOUT0;
-    input EVENTI0;
-    output EVENTO0;
-    output FPDZC0;
-    output FPIDC0;
-    output FPIOC0;
-    output FPIXC0;
-    output FPOFC0;
-    output FPUFC0;
-    input [3:0] GROUPID;
-    input INITPPX0;
-    input INITRAMA0;
-    output JTAGNSW;
-    input LOCZRAMA0;
-    input NIDEN0;
-    input [28:0] PADDRSYS;
-    input PARECCENRAM0;
-    input PARITYLEVEL;
-    input PCLKENSYS;
-    input PCLKSYS;
-    input PENABLESYS;
-    input [19:0] PPVBASE0;
-    input [4:0] PPVSIZE0;
-    input [19:0] PPXBASE0;
-    input [4:0] PPXSIZE0;
-    output [31:0] PRDATASYS;
-    output PREADYSYS;
-    input PRESETSYSn;
-    input PSELSYS;
-    output PSLVERRSYS;
-    input [31:0] PWDATASYS;
-    input PWRITESYS;
-    input [63:0] RDATAM0;
-    input [31:0] RDATAP0;
-    output [63:0] RDATAS0;
-    input [3:0] RIDM0;
-    input [3:0] RIDP0;
-    output [7:0] RIDS0;
-    input RLASTM0;
-    input RLASTP0;
-    output RLASTS0;
-    output RREADYM0;
-    output RREADYP0;
-    input RREADYS0;
-    input [1:0] RRESPM0;
-    input [1:0] RRESPP0;
-    output [1:0] RRESPS0;
-    input RVALIDM0;
-    input RVALIDP0;
-    output RVALIDS0;
-    input SWCLKTCK;
-    input SWDITMS;
-    output SWDO;
-    output SWDOEN;
-    input TDI;
-    output TDO;
-    input TEINIT;
-    output TRACECLK;
-    output TRACECTL;
-    output [31:0] TRACEDATA;
-    input VINITHI0;
-    output [63:0] WDATAM0;
-    output [31:0] WDATAP0;
-    input [63:0] WDATAS0;
-    output [3:0] WIDM0;
-    output [3:0] WIDP0;
-    input [7:0] WIDS0;
-    output WLASTM0;
-    output WLASTP0;
-    input WLASTS0;
-    input WREADYM0;
-    input WREADYP0;
-    output WREADYS0;
-    output [7:0] WSTRBM0;
-    output [3:0] WSTRBP0;
-    input [7:0] WSTRBS0;
-    output WVALIDM0;
-    output WVALIDP0;
-    input WVALIDS0;
-    output nCLKSTOPPED0;
-    input nCPUHALT0;
-    input nETMPORESET;
-    input nFIQ0;
-    input nIRQ0;
-    output nPMUIRQ0;
-    input nPOTRST;
-    input nRESET0;
-    input nSYSPORESET;
-    output nTDOEN;
-    input nTRST;
-    output nVALFIQ0;
-    output nVALIRQ0;
-    output nVALRESET0;
-    output nWFEPIPESTOPPED0;
-    output nWFIPIPESTOPPED0;
-endmodule
-
 (* blackbox *)
 module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13
 , AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10
@@ -11085,21688 +9706,6 @@ module NX_SERDES(FCK, SCK, RTX, RRX, CI, CCK, CL, CR, IO, DCK, DRL, DIG, FZ, FLD
     parameter weakTermination = "";
 endmodule
 
-(* blackbox *)
-module NX_SERVICE_IF_U(fabric_otp_user_clk_i, fabric_otp_user_bistmode_i, fabric_otp_user_disturbcheck_i, fabric_otp_user_eccbypass_i, fabric_otp_user_pdn_i, fabric_otp_user_prog_i, fabric_otp_user_rbact1_i, fabric_otp_user_rbact2_i, fabric_otp_user_read_i, fabric_otp_user_redbypass_i, fabric_otp_user_suppadd_i, fabric_otp_user_tm_i, fabric_otp_user_tst_scanenable_i, fabric_otp_user_wordlock_i, fabric_otp_user_add_i1, fabric_otp_user_add_i2, fabric_otp_user_add_i3, fabric_otp_user_add_i4, fabric_otp_user_add_i5, fabric_otp_user_add_i6, fabric_otp_user_add_i7
-, fabric_otp_user_clock_frequency_range_i, fabric_otp_user_din_i1, fabric_otp_user_din_i2, fabric_otp_user_din_i3, fabric_otp_user_din_i4, fabric_otp_user_din_i5, fabric_otp_user_din_i6, fabric_otp_user_din_i7, fabric_otp_user_din_i8, fabric_otp_user_din_i9, fabric_otp_user_din_i10, fabric_otp_user_din_i11, fabric_otp_user_din_i12, fabric_otp_user_din_i13, fabric_otp_user_din_i14, fabric_otp_user_din_i15, fabric_otp_user_din_i16, fabric_otp_user_din_i17, fabric_otp_user_din_i18, fabric_otp_user_din_i19, fabric_otp_user_din_i20
-, fabric_otp_user_din_i21, fabric_otp_user_din_i22, fabric_otp_user_din_i23, fabric_otp_user_din_i24, fabric_otp_user_din_i25, fabric_otp_user_din_i26, fabric_otp_user_din_i27, fabric_otp_user_din_i28, fabric_otp_user_din_i29, fabric_otp_user_din_i30, fabric_otp_user_din_i31, fabric_otp_user_din_i32, fabric_otp_user_din_i33, fabric_otp_user_din_i34, fabric_otp_user_din_i35, fabric_otp_user_din_i36, fabric_otp_user_din_i37, fabric_otp_user_din_i38, fabric_otp_user_din_i39, fabric_otp_user_prgwidth_i1, fabric_otp_user_prgwidth_i2
-, fabric_otp_user_prgwidth_i3, fabric_otp_user_tst_scanin_i1, fabric_otp_user_tst_scanin_i2, fabric_otp_user_tst_scanin_i3, fabric_otp_user_tst_scanin_i4, fabric_otp_user_tst_scanin_i5, fabric_otp_user_ack_o, fabric_otp_user_bbad_o, fabric_otp_user_bend1_o, fabric_otp_user_bend2_o, fabric_otp_user_calibrated_o, fabric_otp_user_ded_o, fabric_otp_user_disturbed_o, fabric_otp_user_locked_o, fabric_otp_user_progfail_o, fabric_otp_user_pwok_o, fabric_otp_user_sec_o, fabric_otp_user_bist1fail_o1, fabric_otp_user_bist1fail_o2, fabric_otp_user_bist1fail_o3, fabric_otp_user_bist1fail_o4
-, fabric_otp_user_bist1fail_o5, fabric_otp_user_bist1fail_o6, fabric_otp_user_bist1fail_o7, fabric_otp_user_bist1fail_o8, fabric_otp_user_bist2fail_o1, fabric_otp_user_bist2fail_o2, fabric_otp_user_bist2fail_o3, fabric_otp_user_bist2fail_o4, fabric_otp_user_bist2fail_o5, fabric_otp_user_bist2fail_o6, fabric_otp_user_bist2fail_o7, fabric_otp_user_dout_o1, fabric_otp_user_dout_o2, fabric_otp_user_dout_o3, fabric_otp_user_dout_o4, fabric_otp_user_dout_o5, fabric_otp_user_dout_o6, fabric_otp_user_dout_o7, fabric_otp_user_dout_o8, fabric_otp_user_dout_o9, fabric_otp_user_dout_o10
-, fabric_otp_user_dout_o11, fabric_otp_user_dout_o12, fabric_otp_user_dout_o13, fabric_otp_user_dout_o14, fabric_otp_user_dout_o15, fabric_otp_user_dout_o16, fabric_otp_user_dout_o17, fabric_otp_user_dout_o18, fabric_otp_user_dout_o19, fabric_otp_user_dout_o20, fabric_otp_user_dout_o21, fabric_otp_user_dout_o22, fabric_otp_user_dout_o23, fabric_otp_user_dout_o24, fabric_otp_user_dout_o25, fabric_otp_user_dout_o26, fabric_otp_user_dout_o27, fabric_otp_user_dout_o28, fabric_otp_user_dout_o29, fabric_otp_user_dout_o30, fabric_otp_user_dout_o31
-, fabric_otp_user_dout_o32, fabric_otp_user_dout_o33, fabric_otp_user_dout_o34, fabric_otp_user_dout_o35, fabric_otp_user_dout_o36, fabric_otp_user_dout_o37, fabric_otp_user_dout_o38, fabric_otp_user_dout_o39, fabric_otp_user_dout_o40, fabric_otp_user_dout_o41, fabric_otp_user_flagstate_o1, fabric_otp_user_flagstate_o2, fabric_otp_user_flagstate_o3, fabric_otp_user_flagstate_o4, fabric_otp_user_startword_o1, fabric_otp_user_startword_o2, fabric_otp_user_startword_o3, fabric_otp_user_startword_o4, fabric_otp_user_startword_o5, fabric_otp_user_startword_o6, fabric_otp_user_startword_o7
-, fabric_otp_user_startword_o8, fabric_otp_user_startword_o9, fabric_otp_user_startword_o10, fabric_otp_user_startword_o11, fabric_otp_user_startword_o12, fabric_otp_user_startword_o13, fabric_otp_user_startword_o14, fabric_otp_user_startword_o15, fabric_otp_user_startword_o16, fabric_otp_user_tst_scanout_o1, fabric_otp_user_tst_scanout_o2, fabric_otp_user_tst_scanout_o3, fabric_otp_user_tst_scanout_o4, fabric_otp_user_tst_scanout_o5, fabric_otp_user_wlromout_o1, fabric_otp_user_wlromout_o2, fabric_otp_user_wlromout_o3, fabric_otp_user_wlromout_o4, fabric_otp_user_wlromout_o5, fabric_otp_user_wlromout_o6, fabric_otp_user_wlromout_o7
-, fabric_otp_user_wlromout_o8, fabric_otp_user_wlromout_o9, fabric_otp_user_wlromout_o10, fabric_clk_bsm_o, fabric_clk_otp_mux_i, fabric_clk_otp_o, fabric_clk_user0_o, fabric_clk_user1_o, fabric_io_in_i1, fabric_io_in_i2, fabric_io_in_i3, fabric_io_in_i4, fabric_io_in_i5, fabric_io_in_i6, fabric_io_in_i7, fabric_io_in_i8, fabric_io_in_i9, fabric_io_in_i10, fabric_io_in_i11, fabric_io_in_i12, fabric_io_in_i13
-, fabric_io_in_i14, fabric_io_in_i15, fabric_io_in_i16, fabric_io_in_i17, fabric_io_in_i18, fabric_io_in_i19, fabric_io_in_i20, fabric_io_in_i21, fabric_io_in_i22, fabric_io_in_i23, fabric_io_in_i24, fabric_io_in_i25, fabric_io_in_i26, fabric_io_in_i27, fabric_io_in_i28, fabric_io_in_i29, fabric_io_in_i30, fabric_io_in_i31, fabric_io_in_i32, fabric_io_in_i33, fabric_io_in_i34
-, fabric_io_in_i35, fabric_io_oe_i1, fabric_io_oe_i2, fabric_io_oe_i3, fabric_io_oe_i4, fabric_io_oe_i5, fabric_io_oe_i6, fabric_io_oe_i7, fabric_io_oe_i8, fabric_io_oe_i9, fabric_io_oe_i10, fabric_io_oe_i11, fabric_io_oe_i12, fabric_io_oe_i13, fabric_io_oe_i14, fabric_io_oe_i15, fabric_io_oe_i16, fabric_io_oe_i17, fabric_io_oe_i18, fabric_io_oe_i19, fabric_io_oe_i20
-, fabric_io_oe_i21, fabric_io_oe_i22, fabric_io_oe_i23, fabric_io_oe_i24, fabric_io_oe_i25, fabric_io_oe_i26, fabric_io_oe_i27, fabric_io_oe_i28, fabric_io_oe_i29, fabric_io_oe_i30, fabric_io_oe_i31, fabric_io_oe_i32, fabric_io_oe_i33, fabric_io_oe_i34, fabric_io_oe_i35, fabric_io_out_o1, fabric_io_out_o2, fabric_io_out_o3, fabric_io_out_o4, fabric_io_out_o5, fabric_io_out_o6
-, fabric_io_out_o7, fabric_io_out_o8, fabric_io_out_o9, fabric_io_out_o10, fabric_io_out_o11, fabric_io_out_o12, fabric_io_out_o13, fabric_io_out_o14, fabric_io_out_o15, fabric_io_out_o16, fabric_io_out_o17, fabric_io_out_o18, fabric_io_out_o19, fabric_io_out_o20, fabric_io_out_o21, fabric_io_out_o22, fabric_io_out_o23, fabric_io_out_o24, fabric_io_out_o25, fabric_io_out_o26, fabric_io_out_o27
-, fabric_io_out_o28, fabric_io_out_o29, fabric_io_out_o30, fabric_io_out_o31, fabric_io_out_o32, fabric_io_out_o33, fabric_io_out_o34, fabric_io_out_o35, fabric_user_clk_i, fabric_user_data_i1, fabric_user_data_i2, fabric_user_data_i3, fabric_user_data_i4, fabric_user_data_i5, fabric_user_data_i6, fabric_user_data_i7, fabric_user_data_i8, fabric_user_data_i9, fabric_user_data_i10, fabric_user_data_i11, fabric_user_data_i12
-, fabric_user_data_i13, fabric_user_data_i14, fabric_user_data_i15, fabric_user_data_i16, fabric_user_data_i17, fabric_user_data_i18, fabric_user_data_i19, fabric_user_data_i20, fabric_user_data_i21, fabric_user_data_i22, fabric_user_data_i23, fabric_user_data_i24, fabric_user_data_i25, fabric_user_data_i26, fabric_user_data_i27, fabric_user_data_i28, fabric_user_data_i29, fabric_user_data_i30, fabric_user_data_i31, fabric_user_data_i32, fabric_user_data_o1
-, fabric_user_data_o2, fabric_user_data_o3, fabric_user_data_o4, fabric_user_data_o5, fabric_user_data_o6, fabric_user_data_o7, fabric_user_data_o8, fabric_user_data_o9, fabric_user_data_o10, fabric_user_data_o11, fabric_user_data_o12, fabric_user_data_o13, fabric_user_data_o14, fabric_user_data_o15, fabric_user_data_o16, fabric_user_data_o17, fabric_user_data_o18, fabric_user_data_o19, fabric_user_data_o20, fabric_user_data_o21, fabric_user_data_o22
-, fabric_user_data_o23, fabric_user_data_o24, fabric_user_data_o25, fabric_user_data_o26, fabric_user_data_o27, fabric_user_data_o28, fabric_user_data_o29, fabric_user_data_o30, fabric_user_data_o31, fabric_user_data_o32, fabric_user_write_cycle_o, fabric_user_read_cycle_o, fabric_cfg_fabric_user_flag_o, fabric_cfg_fabric_user_enable_o, fabric_parusr_clk_i, fabric_parusr_enable_i, fabric_parusr_cs_i, fabric_parusr_type_i1, fabric_parusr_type_i2, fabric_parusr_data_i1, fabric_parusr_data_i2
-, fabric_parusr_data_i3, fabric_parusr_data_i4, fabric_parusr_data_i5, fabric_parusr_data_i6, fabric_parusr_data_i7, fabric_parusr_data_i8, fabric_parusr_data_i9, fabric_parusr_data_i10, fabric_parusr_data_i11, fabric_parusr_data_i12, fabric_parusr_data_i13, fabric_parusr_data_i14, fabric_parusr_data_i15, fabric_parusr_data_i16, fabric_parusr_data_o1, fabric_parusr_data_o2, fabric_parusr_data_o3, fabric_parusr_data_o4, fabric_parusr_data_o5, fabric_parusr_data_o6, fabric_parusr_data_o7
-, fabric_parusr_data_o8, fabric_parusr_data_o9, fabric_parusr_data_o10, fabric_parusr_data_o11, fabric_parusr_data_o12, fabric_parusr_data_o13, fabric_parusr_data_o14, fabric_parusr_data_o15, fabric_parusr_data_o16, fabric_parusr_data_val_o, fabric_jtag_tck_o, fabric_jtag_trst_n_o, fabric_jtag_tms_o, fabric_jtag_tdi_o, fabric_jtag_usr1_o, fabric_jtag_usr2_o, fabric_jtag_tdo_usr1_i, fabric_jtag_tdo_usr2_i, fabric_status_cold_start_o, fabric_flag_trigger0_o, fabric_flag_trigger1_o
-, fabric_flag_ready_TMR_o1, fabric_flag_ready_TMR_o2, fabric_flag_ready_TMR_o3, fabric_enable_TMR_i1, fabric_enable_TMR_i2, fabric_enable_TMR_i3, fabric_lowskew_i1, fabric_lowskew_i2, fabric_lowskew_i3, fabric_lowskew_i4, fabric_lowskew_i5, fabric_lowskew_i6, fabric_lowskew_i7, fabric_lowskew_i8, fabric_lowskew_i9, fabric_lowskew_i10, fabric_lowskew_i11, fabric_lowskew_i12, fabric_lowskew_i13, fabric_lowskew_i14, fabric_lowskew_i15
-, fabric_lowskew_i16, fabric_lowskew_i17, fabric_lowskew_i18, fabric_lowskew_i19, fabric_lowskew_i20, fabric_lowskew_i21, fabric_lowskew_i22, fabric_lowskew_i23, fabric_lowskew_i24, fabric_lowskew_i25, fabric_lowskew_i26, fabric_lowskew_i27, fabric_lowskew_i28, fabric_lowskew_i29, fabric_lowskew_i30, fabric_lowskew_i31, fabric_lowskew_i32, fabric_lowskew_i33, fabric_lowskew_i34, fabric_lowskew_i35, fabric_lowskew_i36
-, fabric_lowskew_i37, fabric_lowskew_i38, fabric_lowskew_i39, fabric_lowskew_i40, fabric_lowskew_o1, fabric_lowskew_o2, fabric_lowskew_o3, fabric_lowskew_o4, fabric_lowskew_o5, fabric_lowskew_o6, fabric_spare_i1, fabric_spare_i2, fabric_spare_i3, fabric_spare_i4, fabric_spare_i5, fabric_spare_i6, fabric_spare_i7, fabric_spare_i8, fabric_spare_i9, fabric_spare_i10, fabric_spare_i11
-, fabric_spare_i12, fabric_spare_i13, fabric_spare_i14, fabric_spare_i15, fabric_spare_i16, fabric_spare_i17, fabric_spare_i18, fabric_spare_i19, fabric_spare_i20, fabric_spare_i21, fabric_spare_i22, fabric_spare_i23, fabric_spare_i24, fabric_spare_i25, fabric_spare_i26, fabric_spare_i27, fabric_spare_i28, fabric_spare_i29, fabric_spare_i30, fabric_spare_i31, fabric_spare_i32
-, fabric_spare_i33, fabric_spare_i34, fabric_spare_i35, fabric_spare_i36, fabric_spare_i37, fabric_spare_i38, fabric_spare_i39, fabric_spare_i40, fabric_spare_i41, fabric_spare_i42, fabric_spare_i43, fabric_spare_i44, fabric_spare_i45, fabric_spare_i46, fabric_spare_i47, fabric_spare_i48, fabric_spare_i49, fabric_spare_i50, fabric_spare_i51, fabric_spare_i52, fabric_spare_i53
-, fabric_spare_i54, fabric_spare_i55, fabric_spare_i56, fabric_spare_i57, fabric_spare_i58, fabric_spare_i59, fabric_spare_i60, fabric_spare_i61, fabric_spare_i62, fabric_spare_i63, fabric_spare_i64, fabric_spare_i65, fabric_spare_i66, fabric_spare_i67, fabric_spare_i68, fabric_spare_i69, fabric_spare_i70, fabric_spare_i71, fabric_spare_i72, fabric_spare_i73, fabric_spare_i74
-, fabric_spare_i75, fabric_spare_i76, fabric_spare_i77, fabric_spare_i78, fabric_spare_i79, fabric_spare_i80, fabric_spare_i81, fabric_spare_i82, fabric_spare_i83, fabric_spare_i84, fabric_spare_i85, fabric_spare_i86, fabric_spare_i87, fabric_spare_i88, fabric_spare_i89, fabric_spare_i90, fabric_spare_i91, fabric_spare_i92, fabric_spare_i93, fabric_spare_i94, fabric_spare_i95
-, fabric_spare_i96, fabric_spare_i97, fabric_spare_i98, fabric_spare_i99, fabric_spare_i100, fabric_spare_i101, fabric_spare_i102, fabric_spare_i103, fabric_spare_i104, fabric_spare_i105, fabric_spare_i106, fabric_spare_i107, fabric_spare_i108, fabric_spare_i109, fabric_spare_i110, fabric_spare_i111, fabric_spare_i112, fabric_spare_i113, fabric_spare_i114, fabric_spare_i115, fabric_spare_i116
-, fabric_spare_i117, fabric_spare_i118, fabric_spare_i119, fabric_spare_i120, fabric_spare_i121, fabric_spare_i122, fabric_spare_i123, fabric_spare_i124, fabric_spare_i125, fabric_spare_i126, fabric_spare_i127, fabric_spare_i128, fabric_spare_o1, fabric_spare_o2, fabric_spare_o3, fabric_spare_o4, fabric_spare_o5, fabric_spare_o6, fabric_spare_o7, fabric_spare_o8, fabric_spare_o9
-, fabric_spare_o10, fabric_spare_o11, fabric_spare_o12, fabric_spare_o13, fabric_spare_o14, fabric_spare_o15, fabric_spare_o16, fabric_spare_o17, fabric_spare_o18, fabric_spare_o19, fabric_spare_o20, fabric_spare_o21, fabric_spare_o22, fabric_spare_o23, fabric_spare_o24, fabric_spare_o25, fabric_spare_o26, fabric_spare_o27, fabric_spare_o28, fabric_spare_o29, fabric_spare_o30
-, fabric_spare_o31, fabric_spare_o32, fabric_spare_o33, fabric_spare_o34, fabric_spare_o35, fabric_spare_o36, fabric_spare_o37, fabric_spare_o38, fabric_spare_o39, fabric_spare_o40, fabric_spare_o41, fabric_spare_o42, fabric_spare_o43, fabric_spare_o44, fabric_spare_o45, fabric_spare_o46, fabric_spare_o47, fabric_spare_o48, fabric_spare_o49, fabric_spare_o50, fabric_spare_o51
-, fabric_spare_o52, fabric_spare_o53, fabric_spare_o54, fabric_spare_o55, fabric_spare_o56, fabric_spare_o57, fabric_spare_o58, fabric_spare_o59, fabric_spare_o60, fabric_spare_o61, fabric_spare_o62, fabric_spare_o63, fabric_spare_o64, fabric_spare_o65, fabric_spare_o66, fabric_spare_o67, fabric_spare_o68, fabric_spare_o69, fabric_spare_o70, fabric_spare_o71, fabric_spare_o72
-, fabric_spare_o73, fabric_spare_o74, fabric_spare_o75, fabric_spare_o76, fabric_spare_o77, fabric_spare_o78, fabric_spare_o79, fabric_spare_o80, fabric_spare_o81, fabric_spare_o82, fabric_spare_o83, fabric_spare_o84, fabric_spare_o85, fabric_spare_o86, fabric_spare_o87, fabric_spare_o88, fabric_spare_o89, fabric_spare_o90, fabric_spare_o91, fabric_spare_o92, fabric_spare_o93
-, fabric_spare_o94, fabric_spare_o95, fabric_spare_o96, fabric_spare_o97, fabric_spare_o98, fabric_spare_o99, fabric_spare_o100, fabric_spare_o101, fabric_spare_o102, fabric_spare_o103, fabric_spare_o104, fabric_spare_o105, fabric_spare_o106, fabric_spare_o107, fabric_spare_o108, fabric_spare_o109, fabric_spare_o110, fabric_spare_o111, fabric_spare_o112, fabric_spare_o113, fabric_spare_o114
-, fabric_spare_o115, fabric_spare_o116, fabric_spare_o117, fabric_spare_o118, fabric_spare_o119, fabric_spare_o120, fabric_spare_o121, fabric_spare_o122, fabric_spare_o123, fabric_spare_o124, fabric_spare_o125, fabric_spare_o126, fabric_spare_o127, fabric_spare_o128, fabric_thsens_clk_i, fabric_thsens_arst_tmr_n_i1, fabric_thsens_arst_tmr_n_i2, fabric_thsens_arst_tmr_n_i3, fabric_thsens_fm_enable_i, fabric_thsens_fm_mode_w_i1, fabric_thsens_fm_mode_w_i2
-, fabric_thsens_fm_mode_w_i3, fabric_thsens_fm_mode_w_i4, fabric_thsens_fm_mode_w_i5, fabric_thsens_fm_mode_w_i6, fabric_thsens_fm_mode_w_i7, fabric_thsens_fm_mode_w_i8, fabric_thsens_fm_mode_w_i9, fabric_thsens_fm_mode_w_i10, fabric_thsens_fm_mode_w_i11, fabric_thsens_fm_mode_w_i12, fabric_thsens_fm_mode_w_i13, fabric_thsens_fm_mode_w_i14, fabric_thsens_fm_mode_w_i15, fabric_thsens_fm_mode_w_i16, fabric_thsens_fm_mode_w_i17, fabric_thsens_fm_mode_w_i18, fabric_thsens_fm_mode_w_i19, fabric_thsens_fm_mode_w_i20, fabric_thsens_fm_mode_w_i21, fabric_thsens_fm_mode_w_i22, fabric_thsens_fm_mode_w_i23
-, fabric_thsens_fm_mode_w_i24, fabric_thsens_fm_mode_w_i25, fabric_thsens_fm_mode_w_i26, fabric_thsens_fm_mode_w_i27, fabric_thsens_fm_mode_w_i28, fabric_thsens_fm_mode_w_i29, fabric_thsens_fm_mode_w_i30, fabric_thsens_fm_mode_w_i31, fabric_thsens_fm_mode_w_i32, fabric_thsens_fm_mode_wen_i, fabric_thsens_fm_config_w_i1, fabric_thsens_fm_config_w_i2, fabric_thsens_fm_config_w_i3, fabric_thsens_fm_config_w_i4, fabric_thsens_fm_config_w_i5, fabric_thsens_fm_config_w_i6, fabric_thsens_fm_config_w_i7, fabric_thsens_fm_config_w_i8, fabric_thsens_fm_config_w_i9, fabric_thsens_fm_config_w_i10, fabric_thsens_fm_config_w_i11
-, fabric_thsens_fm_config_w_i12, fabric_thsens_fm_config_w_i13, fabric_thsens_fm_config_w_i14, fabric_thsens_fm_config_w_i15, fabric_thsens_fm_config_w_i16, fabric_thsens_fm_config_w_i17, fabric_thsens_fm_config_w_i18, fabric_thsens_fm_config_w_i19, fabric_thsens_fm_config_w_i20, fabric_thsens_fm_config_w_i21, fabric_thsens_fm_config_w_i22, fabric_thsens_fm_config_w_i23, fabric_thsens_fm_config_w_i24, fabric_thsens_fm_config_w_i25, fabric_thsens_fm_config_w_i26, fabric_thsens_fm_config_w_i27, fabric_thsens_fm_config_wen_i, fabric_thsens_fm_data_o1, fabric_thsens_fm_data_o2, fabric_thsens_fm_data_o3, fabric_thsens_fm_data_o4
-, fabric_thsens_fm_data_o5, fabric_thsens_fm_data_o6, fabric_thsens_fm_data_o7, fabric_thsens_fm_data_o8, fabric_thsens_fm_data_o9, fabric_thsens_fm_data_o10, fabric_thsens_fm_data_o11, fabric_thsens_fm_data_o12, fabric_thsens_fm_data_o13, fabric_thsens_fm_data_o14, fabric_thsens_fm_valid_o, fabric_thsens_fm_overflow_o, fabric_thsens_fm_mode_r_o1, fabric_thsens_fm_mode_r_o2, fabric_thsens_fm_mode_r_o3, fabric_thsens_fm_mode_r_o4, fabric_thsens_fm_mode_r_o5, fabric_thsens_fm_mode_r_o6, fabric_thsens_fm_mode_r_o7, fabric_thsens_fm_mode_r_o8, fabric_thsens_fm_mode_r_o9
-, fabric_thsens_fm_mode_r_o10, fabric_thsens_fm_mode_r_o11, fabric_thsens_fm_mode_r_o12, fabric_thsens_fm_mode_r_o13, fabric_thsens_fm_mode_r_o14, fabric_thsens_fm_mode_r_o15, fabric_thsens_fm_mode_r_o16, fabric_thsens_fm_mode_r_o17, fabric_thsens_fm_mode_r_o18, fabric_thsens_fm_mode_r_o19, fabric_thsens_fm_mode_r_o20, fabric_thsens_fm_mode_r_o21, fabric_thsens_fm_mode_r_o22, fabric_thsens_fm_mode_r_o23, fabric_thsens_fm_mode_r_o24, fabric_thsens_fm_mode_r_o25, fabric_thsens_fm_mode_r_o26, fabric_thsens_fm_mode_r_o27, fabric_thsens_fm_mode_r_o28, fabric_thsens_fm_mode_r_o29, fabric_thsens_fm_mode_r_o30
-, fabric_thsens_fm_mode_r_o31, fabric_thsens_fm_mode_r_o32, fabric_thsens_fm_config_r_o1, fabric_thsens_fm_config_r_o2, fabric_thsens_fm_config_r_o3, fabric_thsens_fm_config_r_o4, fabric_thsens_fm_config_r_o5, fabric_thsens_fm_config_r_o6, fabric_thsens_fm_config_r_o7, fabric_thsens_fm_config_r_o8, fabric_thsens_fm_config_r_o9, fabric_thsens_fm_config_r_o10, fabric_thsens_fm_config_r_o11, fabric_thsens_fm_config_r_o12, fabric_thsens_fm_config_r_o13, fabric_thsens_fm_config_r_o14, fabric_thsens_fm_config_r_o15, fabric_thsens_fm_config_r_o16, fabric_thsens_fm_config_r_o17, fabric_thsens_fm_config_r_o18, fabric_thsens_fm_config_r_o19
-, fabric_thsens_fm_config_r_o20, fabric_thsens_fm_config_r_o21, fabric_thsens_fm_config_r_o22, fabric_thsens_fm_config_r_o23, fabric_thsens_fm_config_r_o24, fabric_thsens_fm_config_r_o25, fabric_thsens_fm_config_r_o26, fabric_thsens_fm_config_r_o27, fabric_thsens_clk_div_ratio_i1, fabric_thsens_clk_div_ratio_i2, fabric_thsens_clk_div_ratio_i3, fabric_thsens_clk_div_ratio_i4, fabric_thsens_clk_div_ratio_i5, fabric_thsens_clk_div_ratio_i6, fabric_thsens_clk_div_ratio_i7, fabric_thsens_clk_div_ratio_i8, fabric_thsens_otp_config_o1, fabric_thsens_otp_config_o2, fabric_thsens_otp_config_o3, fabric_thsens_otp_config_o4, fabric_thsens_otp_config_o5
-, fabric_thsens_otp_config_o6, fabric_thsens_otp_config_o7, fabric_thsens_otp_config_o8, fabric_thsens_otp_config_o9, fabric_thsens_otp_config_o10, fabric_thsens_otp_config_o11, fabric_thsens_otp_config_o12, fabric_thsens_otp_config_o13, fabric_thsens_otp_config_o14, fabric_thsens_otp_config_o15, fabric_thsens_otp_config_o16, fabric_thsens_otp_config_o17, fabric_thsens_otp_config_o18, fabric_thsens_otp_config_o19, fabric_thsens_otp_config_o20, fabric_thsens_otp_config_o21, fabric_thsens_otp_config_o22, fabric_thsens_otp_config_o23, fabric_thsens_otp_config_o24, fabric_thsens_otp_config_o25, fabric_thsens_otp_config_o26
-, fabric_thsens_otp_config_o27, fabric_spi_clk_i2, fabric_spi_sck_i2, fabric_spi_clk_i0, fabric_spi_sck_i0, fabric_spi_clk_i1, fabric_spi_sck_i1, fabric_spi_needed_i1, fabric_spi_needed_i2, fabric_spi_needed_i3, fabric_spi_bsm_release_o1, fabric_spi_bsm_release_o2, fabric_spi_bsm_release_o3, fabric_spi_arst_tmr_n_i1, fabric_spi_arst_tmr_n_i2, fabric_spi_arst_tmr_n_i3, fabric_spi_arst_tmr_n_i4, fabric_spi_arst_tmr_n_i5, fabric_spi_arst_tmr_n_i6, fabric_spi_arst_tmr_n_i7, fabric_spi_arst_tmr_n_i8
-, fabric_spi_arst_tmr_n_i9, fabric_spi_fifo_arst_tmr_n_i1, fabric_spi_fifo_arst_tmr_n_i2, fabric_spi_fifo_arst_tmr_n_i3, fabric_spi_fifo_arst_tmr_n_i4, fabric_spi_fifo_arst_tmr_n_i5, fabric_spi_fifo_arst_tmr_n_i6, fabric_spi_fifo_arst_tmr_n_i7, fabric_spi_fifo_arst_tmr_n_i8, fabric_spi_fifo_arst_tmr_n_i9, fabric_spi_cpol_i1, fabric_spi_cpol_i2, fabric_spi_cpol_i3, fabric_spi_cpha_i1, fabric_spi_cpha_i2, fabric_spi_cpha_i3, fabric_spi_loopback_i1, fabric_spi_loopback_i2, fabric_spi_loopback_i3, fabric_spi_lsb_first_i1, fabric_spi_lsb_first_i2
-, fabric_spi_lsb_first_i3, fabric_spi_cs_setuptime_i1, fabric_spi_cs_setuptime_i2, fabric_spi_cs_setuptime_i3, fabric_spi_cs_setuptime_i4, fabric_spi_cs_setuptime_i5, fabric_spi_cs_setuptime_i6, fabric_spi_cs_setuptime_i7, fabric_spi_cs_setuptime_i8, fabric_spi_cs_setuptime_i9, fabric_spi_cs_setuptime_i10, fabric_spi_cs_setuptime_i11, fabric_spi_cs_setuptime_i12, fabric_spi_cs_holdtime_i1, fabric_spi_cs_holdtime_i2, fabric_spi_cs_holdtime_i3, fabric_spi_cs_holdtime_i4, fabric_spi_cs_holdtime_i5, fabric_spi_cs_holdtime_i6, fabric_spi_cs_holdtime_i7, fabric_spi_cs_holdtime_i8
-, fabric_spi_cs_holdtime_i9, fabric_spi_cs_holdtime_i10, fabric_spi_cs_holdtime_i11, fabric_spi_cs_holdtime_i12, fabric_spi_cs_offtime_i1, fabric_spi_cs_offtime_i2, fabric_spi_cs_offtime_i3, fabric_spi_cs_offtime_i4, fabric_spi_cs_offtime_i5, fabric_spi_cs_offtime_i6, fabric_spi_cs_offtime_i7, fabric_spi_cs_offtime_i8, fabric_spi_cs_offtime_i9, fabric_spi_cs_offtime_i10, fabric_spi_cs_offtime_i11, fabric_spi_cs_offtime_i12, fabric_spi_vcc_enable_i1, fabric_spi_vcc_enable_i2, fabric_spi_vcc_enable_i3, fabric_spi_powerdown_cycle_i1, fabric_spi_powerdown_cycle_i2
-, fabric_spi_powerdown_cycle_i3, fabric_spi_powerdown_cycle_i4, fabric_spi_powerdown_cycle_i5, fabric_spi_powerdown_cycle_i6, fabric_spi_powerdown_cycle_i7, fabric_spi_powerdown_cycle_i8, fabric_spi_powerdown_cycle_i9, fabric_spi_powerdown_cycle_i10, fabric_spi_powerdown_cycle_i11, fabric_spi_powerdown_cycle_i12, fabric_spi_powerdown_cycle_i13, fabric_spi_powerdown_cycle_i14, fabric_spi_powerdown_cycle_i15, fabric_spi_powerdown_cycle_i16, fabric_spi_powerdown_cycle_i17, fabric_spi_powerdown_cycle_i18, fabric_spi_powerdown_cycle_i19, fabric_spi_powerdown_cycle_i20, fabric_spi_powerdown_cycle_i21, fabric_spi_powerdown_cycle_i22, fabric_spi_powerdown_cycle_i23
-, fabric_spi_powerdown_cycle_i24, fabric_spi_powerdown_cycle_i25, fabric_spi_powerdown_cycle_i26, fabric_spi_powerdown_cycle_i27, fabric_spi_powerdown_cycle_i28, fabric_spi_powerdown_cycle_i29, fabric_spi_powerdown_cycle_i30, fabric_spi_powerdown_cycle_i31, fabric_spi_powerdown_cycle_i32, fabric_spi_powerdown_cycle_i33, fabric_spi_powerdown_cycle_i34, fabric_spi_powerdown_cycle_i35, fabric_spi_powerdown_cycle_i36, fabric_spi_powerdown_cycle_i37, fabric_spi_powerdown_cycle_i38, fabric_spi_powerdown_cycle_i39, fabric_spi_powerdown_cycle_i40, fabric_spi_powerdown_cycle_i41, fabric_spi_powerdown_cycle_i42, fabric_spi_powerdown_cycle_i43, fabric_spi_powerdown_cycle_i44
-, fabric_spi_powerdown_cycle_i45, fabric_spi_powerdown_cycle_i46, fabric_spi_powerdown_cycle_i47, fabric_spi_powerdown_cycle_i48, fabric_spi_powerup_cycle_i1, fabric_spi_powerup_cycle_i2, fabric_spi_powerup_cycle_i3, fabric_spi_powerup_cycle_i4, fabric_spi_powerup_cycle_i5, fabric_spi_powerup_cycle_i6, fabric_spi_powerup_cycle_i7, fabric_spi_powerup_cycle_i8, fabric_spi_powerup_cycle_i9, fabric_spi_powerup_cycle_i10, fabric_spi_powerup_cycle_i11, fabric_spi_powerup_cycle_i12, fabric_spi_powerup_cycle_i13, fabric_spi_powerup_cycle_i14, fabric_spi_powerup_cycle_i15, fabric_spi_powerup_cycle_i16, fabric_spi_powerup_cycle_i17
-, fabric_spi_powerup_cycle_i18, fabric_spi_powerup_cycle_i19, fabric_spi_powerup_cycle_i20, fabric_spi_powerup_cycle_i21, fabric_spi_powerup_cycle_i22, fabric_spi_powerup_cycle_i23, fabric_spi_powerup_cycle_i24, fabric_spi_powerup_cycle_i25, fabric_spi_powerup_cycle_i26, fabric_spi_powerup_cycle_i27, fabric_spi_powerup_cycle_i28, fabric_spi_powerup_cycle_i29, fabric_spi_powerup_cycle_i30, fabric_spi_powerup_cycle_i31, fabric_spi_powerup_cycle_i32, fabric_spi_powerup_cycle_i33, fabric_spi_powerup_cycle_i34, fabric_spi_powerup_cycle_i35, fabric_spi_powerup_cycle_i36, fabric_spi_powerup_cycle_i37, fabric_spi_powerup_cycle_i38
-, fabric_spi_powerup_cycle_i39, fabric_spi_powerup_cycle_i40, fabric_spi_powerup_cycle_i41, fabric_spi_powerup_cycle_i42, fabric_spi_powerup_cycle_i43, fabric_spi_powerup_cycle_i44, fabric_spi_powerup_cycle_i45, fabric_spi_powerup_cycle_i46, fabric_spi_powerup_cycle_i47, fabric_spi_powerup_cycle_i48, fabric_spi_legacy_enable_i1, fabric_spi_legacy_enable_i2, fabric_spi_legacy_enable_i3, fabric_spi_legacy_master_i1, fabric_spi_legacy_master_i2, fabric_spi_legacy_master_i3, fabric_spi_data_in_unlimited_i1, fabric_spi_data_in_unlimited_i2, fabric_spi_data_in_unlimited_i3, fabric_spi_enable_i1, fabric_spi_enable_i2
-, fabric_spi_enable_i3, fabric_spi_rst_n_i1, fabric_spi_rst_n_i2, fabric_spi_rst_n_i3, fabric_spi_init_done_o1, fabric_spi_init_done_o2, fabric_spi_init_done_o3, fabric_spi_busy_o1, fabric_spi_busy_o2, fabric_spi_busy_o3, fabric_spi_vcc_used_o1, fabric_spi_vcc_used_o2, fabric_spi_vcc_used_o3, fabric_spi_error_sel_o1, fabric_spi_error_sel_o2, fabric_spi_error_sel_o3, fabric_spi_error_loopback_o1, fabric_spi_error_loopback_o2, fabric_spi_error_loopback_o3, fabric_spi_error_mode_o1, fabric_spi_error_mode_o2
-, fabric_spi_error_mode_o3, fabric_spi_error_endianness_o1, fabric_spi_error_endianness_o2, fabric_spi_error_endianness_o3, fabric_spi_cmd_push_i1, fabric_spi_cmd_push_i2, fabric_spi_cmd_push_i3, fabric_spi_cmd_full_o1, fabric_spi_cmd_full_o2, fabric_spi_cmd_full_o3, fabric_spi_cmd_type_i1, fabric_spi_cmd_type_i2, fabric_spi_cmd_type_i3, fabric_spi_cmd_type_i4, fabric_spi_cmd_type_i5, fabric_spi_cmd_type_i6, fabric_spi_cmd_mode_i1, fabric_spi_cmd_mode_i2, fabric_spi_cmd_mode_i3, fabric_spi_cmd_mode_i4, fabric_spi_cmd_mode_i5
-, fabric_spi_cmd_mode_i6, fabric_spi_cmd_bytes_i1, fabric_spi_cmd_bytes_i2, fabric_spi_cmd_bytes_i3, fabric_spi_cmd_bytes_i4, fabric_spi_cmd_bytes_i5, fabric_spi_cmd_bytes_i6, fabric_spi_mosi_push_i1, fabric_spi_mosi_push_i2, fabric_spi_mosi_push_i3, fabric_spi_mosi_full_o1, fabric_spi_mosi_full_o2, fabric_spi_mosi_full_o3, fabric_spi_mosi_data_i1, fabric_spi_mosi_data_i2, fabric_spi_mosi_data_i3, fabric_spi_mosi_data_i4, fabric_spi_mosi_data_i5, fabric_spi_mosi_data_i6, fabric_spi_mosi_data_i7, fabric_spi_mosi_data_i8
-, fabric_spi_mosi_data_i9, fabric_spi_mosi_data_i10, fabric_spi_mosi_data_i11, fabric_spi_mosi_data_i12, fabric_spi_mosi_data_i13, fabric_spi_mosi_data_i14, fabric_spi_mosi_data_i15, fabric_spi_mosi_data_i16, fabric_spi_mosi_data_i17, fabric_spi_mosi_data_i18, fabric_spi_mosi_data_i19, fabric_spi_mosi_data_i20, fabric_spi_mosi_data_i21, fabric_spi_mosi_data_i22, fabric_spi_mosi_data_i23, fabric_spi_mosi_data_i24, fabric_spi_mosi_data_inv_i1, fabric_spi_mosi_data_inv_i2, fabric_spi_mosi_data_inv_i3, fabric_spi_miso_pop_i1, fabric_spi_miso_pop_i2
-, fabric_spi_miso_pop_i3, fabric_spi_miso_empty_o1, fabric_spi_miso_empty_o2, fabric_spi_miso_empty_o3, fabric_spi_miso_data_o1, fabric_spi_miso_data_o2, fabric_spi_miso_data_o3, fabric_spi_miso_data_o4, fabric_spi_miso_data_o5, fabric_spi_miso_data_o6, fabric_spi_miso_data_o7, fabric_spi_miso_data_o8, fabric_spi_miso_data_o9, fabric_spi_miso_data_o10, fabric_spi_miso_data_o11, fabric_spi_miso_data_o12, fabric_spi_miso_data_o13, fabric_spi_miso_data_o14, fabric_spi_miso_data_o15, fabric_spi_miso_data_o16, fabric_spi_miso_data_o17
-, fabric_spi_miso_data_o18, fabric_spi_miso_data_o19, fabric_spi_miso_data_o20, fabric_spi_miso_data_o21, fabric_spi_miso_data_o22, fabric_spi_miso_data_o23, fabric_spi_miso_data_o24, fabric_spi_miso_data_inv_o1, fabric_spi_miso_data_inv_o2, fabric_spi_miso_data_inv_o3, fabric_spw0_clk_i, fabric_spw0_clk_tx_i, fabric_spw0_rst_n_i, fabric_spw0_user_shared_o, fabric_spw0_tx_fifo_write_i, fabric_spw0_tx_fifo_data_i1, fabric_spw0_tx_fifo_data_i2, fabric_spw0_tx_fifo_data_i3, fabric_spw0_tx_fifo_data_i4, fabric_spw0_tx_fifo_data_i5, fabric_spw0_tx_fifo_data_i6
-, fabric_spw0_tx_fifo_data_i7, fabric_spw0_tx_fifo_data_i8, fabric_spw0_tx_fifo_data_i9, fabric_spw0_tx_fifo_full_o, fabric_spw0_rx_fifo_read_i, fabric_spw0_rx_fifo_empty_o, fabric_spw0_rx_fifo_data_o1, fabric_spw0_rx_fifo_data_o2, fabric_spw0_rx_fifo_data_o3, fabric_spw0_rx_fifo_data_o4, fabric_spw0_rx_fifo_data_o5, fabric_spw0_rx_fifo_data_o6, fabric_spw0_rx_fifo_data_o7, fabric_spw0_rx_fifo_data_o8, fabric_spw0_rx_fifo_data_o9, fabric_spw0_tick_ctm_i, fabric_spw0_tick_ctm_o, fabric_spw0_apb_slv_psel_i, fabric_spw0_apb_slv_penable_i, fabric_spw0_apb_slv_paddr_i1, fabric_spw0_apb_slv_paddr_i2
-, fabric_spw0_apb_slv_paddr_i3, fabric_spw0_apb_slv_paddr_i4, fabric_spw0_apb_slv_paddr_i5, fabric_spw0_apb_slv_pwrite_i, fabric_spw0_apb_slv_pwdata_i1, fabric_spw0_apb_slv_pwdata_i2, fabric_spw0_apb_slv_pwdata_i3, fabric_spw0_apb_slv_pwdata_i4, fabric_spw0_apb_slv_pwdata_i5, fabric_spw0_apb_slv_pwdata_i6, fabric_spw0_apb_slv_pwdata_i7, fabric_spw0_apb_slv_pwdata_i8, fabric_spw0_apb_slv_pwdata_i9, fabric_spw0_apb_slv_pwdata_i10, fabric_spw0_apb_slv_pwdata_i11, fabric_spw0_apb_slv_pwdata_i12, fabric_spw0_apb_slv_pwdata_i13, fabric_spw0_apb_slv_pwdata_i14, fabric_spw0_apb_slv_pwdata_i15, fabric_spw0_apb_slv_pwdata_i16, fabric_spw0_apb_slv_pwdata_i17
-, fabric_spw0_apb_slv_pwdata_i18, fabric_spw0_apb_slv_pwdata_i19, fabric_spw0_apb_slv_pwdata_i20, fabric_spw0_apb_slv_pwdata_i21, fabric_spw0_apb_slv_pwdata_i22, fabric_spw0_apb_slv_pwdata_i23, fabric_spw0_apb_slv_pwdata_i24, fabric_spw0_apb_slv_pwdata_i25, fabric_spw0_apb_slv_pwdata_i26, fabric_spw0_apb_slv_pwdata_i27, fabric_spw0_apb_slv_pwdata_i28, fabric_spw0_apb_slv_pwdata_i29, fabric_spw0_apb_slv_pwdata_i30, fabric_spw0_apb_slv_pwdata_i31, fabric_spw0_apb_slv_prdata_o1, fabric_spw0_apb_slv_prdata_o2, fabric_spw0_apb_slv_prdata_o3, fabric_spw0_apb_slv_prdata_o4, fabric_spw0_apb_slv_prdata_o5, fabric_spw0_apb_slv_prdata_o6, fabric_spw0_apb_slv_prdata_o7
-, fabric_spw0_apb_slv_prdata_o8, fabric_spw0_apb_slv_prdata_o9, fabric_spw0_apb_slv_prdata_o10, fabric_spw0_apb_slv_prdata_o11, fabric_spw0_apb_slv_prdata_o12, fabric_spw0_apb_slv_prdata_o13, fabric_spw0_apb_slv_prdata_o14, fabric_spw0_apb_slv_prdata_o15, fabric_spw0_apb_slv_prdata_o16, fabric_spw0_apb_slv_prdata_o17, fabric_spw0_apb_slv_prdata_o18, fabric_spw0_apb_slv_prdata_o19, fabric_spw0_apb_slv_prdata_o20, fabric_spw0_apb_slv_prdata_o21, fabric_spw0_apb_slv_prdata_o22, fabric_spw0_apb_slv_prdata_o23, fabric_spw0_apb_slv_prdata_o24, fabric_spw0_apb_slv_prdata_o25, fabric_spw0_apb_slv_prdata_o26, fabric_spw0_apb_slv_prdata_o27, fabric_spw0_apb_slv_prdata_o28
-, fabric_spw0_apb_slv_prdata_o29, fabric_spw0_apb_slv_prdata_o30, fabric_spw0_apb_slv_prdata_o31, fabric_spw0_apb_slv_pready_o, fabric_spw0_apb_slv_pslverr_o, fabric_spw1_clk_i, fabric_spw1_clk_tx_i, fabric_spw1_rst_n_i, fabric_spw1_user_shared_o, fabric_spw1_tx_fifo_write_i, fabric_spw1_tx_fifo_data_i1, fabric_spw1_tx_fifo_data_i2, fabric_spw1_tx_fifo_data_i3, fabric_spw1_tx_fifo_data_i4, fabric_spw1_tx_fifo_data_i5, fabric_spw1_tx_fifo_data_i6, fabric_spw1_tx_fifo_data_i7, fabric_spw1_tx_fifo_data_i8, fabric_spw1_tx_fifo_data_i9, fabric_spw1_tx_fifo_full_o, fabric_spw1_rx_fifo_read_i
-, fabric_spw1_rx_fifo_empty_o, fabric_spw1_rx_fifo_data_o1, fabric_spw1_rx_fifo_data_o2, fabric_spw1_rx_fifo_data_o3, fabric_spw1_rx_fifo_data_o4, fabric_spw1_rx_fifo_data_o5, fabric_spw1_rx_fifo_data_o6, fabric_spw1_rx_fifo_data_o7, fabric_spw1_rx_fifo_data_o8, fabric_spw1_rx_fifo_data_o9, fabric_spw1_tick_ctm_i, fabric_spw1_tick_ctm_o, fabric_spw1_apb_slv_psel_i, fabric_spw1_apb_slv_penable_i, fabric_spw1_apb_slv_paddr_i1, fabric_spw1_apb_slv_paddr_i2, fabric_spw1_apb_slv_paddr_i3, fabric_spw1_apb_slv_paddr_i4, fabric_spw1_apb_slv_paddr_i5, fabric_spw1_apb_slv_pwrite_i, fabric_spw1_apb_slv_pwdata_i1
-, fabric_spw1_apb_slv_pwdata_i2, fabric_spw1_apb_slv_pwdata_i3, fabric_spw1_apb_slv_pwdata_i4, fabric_spw1_apb_slv_pwdata_i5, fabric_spw1_apb_slv_pwdata_i6, fabric_spw1_apb_slv_pwdata_i7, fabric_spw1_apb_slv_pwdata_i8, fabric_spw1_apb_slv_pwdata_i9, fabric_spw1_apb_slv_pwdata_i10, fabric_spw1_apb_slv_pwdata_i11, fabric_spw1_apb_slv_pwdata_i12, fabric_spw1_apb_slv_pwdata_i13, fabric_spw1_apb_slv_pwdata_i14, fabric_spw1_apb_slv_pwdata_i15, fabric_spw1_apb_slv_pwdata_i16, fabric_spw1_apb_slv_pwdata_i17, fabric_spw1_apb_slv_pwdata_i18, fabric_spw1_apb_slv_pwdata_i19, fabric_spw1_apb_slv_pwdata_i20, fabric_spw1_apb_slv_pwdata_i21, fabric_spw1_apb_slv_pwdata_i22
-, fabric_spw1_apb_slv_pwdata_i23, fabric_spw1_apb_slv_pwdata_i24, fabric_spw1_apb_slv_pwdata_i25, fabric_spw1_apb_slv_pwdata_i26, fabric_spw1_apb_slv_pwdata_i27, fabric_spw1_apb_slv_pwdata_i28, fabric_spw1_apb_slv_pwdata_i29, fabric_spw1_apb_slv_pwdata_i30, fabric_spw1_apb_slv_pwdata_i31, fabric_spw1_apb_slv_prdata_o1, fabric_spw1_apb_slv_prdata_o2, fabric_spw1_apb_slv_prdata_o3, fabric_spw1_apb_slv_prdata_o4, fabric_spw1_apb_slv_prdata_o5, fabric_spw1_apb_slv_prdata_o6, fabric_spw1_apb_slv_prdata_o7, fabric_spw1_apb_slv_prdata_o8, fabric_spw1_apb_slv_prdata_o9, fabric_spw1_apb_slv_prdata_o10, fabric_spw1_apb_slv_prdata_o11, fabric_spw1_apb_slv_prdata_o12
-, fabric_spw1_apb_slv_prdata_o13, fabric_spw1_apb_slv_prdata_o14, fabric_spw1_apb_slv_prdata_o15, fabric_spw1_apb_slv_prdata_o16, fabric_spw1_apb_slv_prdata_o17, fabric_spw1_apb_slv_prdata_o18, fabric_spw1_apb_slv_prdata_o19, fabric_spw1_apb_slv_prdata_o20, fabric_spw1_apb_slv_prdata_o21, fabric_spw1_apb_slv_prdata_o22, fabric_spw1_apb_slv_prdata_o23, fabric_spw1_apb_slv_prdata_o24, fabric_spw1_apb_slv_prdata_o25, fabric_spw1_apb_slv_prdata_o26, fabric_spw1_apb_slv_prdata_o27, fabric_spw1_apb_slv_prdata_o28, fabric_spw1_apb_slv_prdata_o29, fabric_spw1_apb_slv_prdata_o30, fabric_spw1_apb_slv_prdata_o31, fabric_spw1_apb_slv_pready_o, fabric_spw1_apb_slv_pslverr_o
-);
-    output fabric_cfg_fabric_user_enable_o;
-    output fabric_cfg_fabric_user_flag_o;
-    output fabric_clk_bsm_o;
-    input fabric_clk_otp_mux_i;
-    output fabric_clk_otp_o;
-    output fabric_clk_user0_o;
-    output fabric_clk_user1_o;
-    input fabric_enable_TMR_i1;
-    input fabric_enable_TMR_i2;
-    input fabric_enable_TMR_i3;
-    output fabric_flag_ready_TMR_o1;
-    output fabric_flag_ready_TMR_o2;
-    output fabric_flag_ready_TMR_o3;
-    output fabric_flag_trigger0_o;
-    output fabric_flag_trigger1_o;
-    input fabric_io_in_i1;
-    input fabric_io_in_i10;
-    input fabric_io_in_i11;
-    input fabric_io_in_i12;
-    input fabric_io_in_i13;
-    input fabric_io_in_i14;
-    input fabric_io_in_i15;
-    input fabric_io_in_i16;
-    input fabric_io_in_i17;
-    input fabric_io_in_i18;
-    input fabric_io_in_i19;
-    input fabric_io_in_i2;
-    input fabric_io_in_i20;
-    input fabric_io_in_i21;
-    input fabric_io_in_i22;
-    input fabric_io_in_i23;
-    input fabric_io_in_i24;
-    input fabric_io_in_i25;
-    input fabric_io_in_i26;
-    input fabric_io_in_i27;
-    input fabric_io_in_i28;
-    input fabric_io_in_i29;
-    input fabric_io_in_i3;
-    input fabric_io_in_i30;
-    input fabric_io_in_i31;
-    input fabric_io_in_i32;
-    input fabric_io_in_i33;
-    input fabric_io_in_i34;
-    input fabric_io_in_i35;
-    input fabric_io_in_i4;
-    input fabric_io_in_i5;
-    input fabric_io_in_i6;
-    input fabric_io_in_i7;
-    input fabric_io_in_i8;
-    input fabric_io_in_i9;
-    input fabric_io_oe_i1;
-    input fabric_io_oe_i10;
-    input fabric_io_oe_i11;
-    input fabric_io_oe_i12;
-    input fabric_io_oe_i13;
-    input fabric_io_oe_i14;
-    input fabric_io_oe_i15;
-    input fabric_io_oe_i16;
-    input fabric_io_oe_i17;
-    input fabric_io_oe_i18;
-    input fabric_io_oe_i19;
-    input fabric_io_oe_i2;
-    input fabric_io_oe_i20;
-    input fabric_io_oe_i21;
-    input fabric_io_oe_i22;
-    input fabric_io_oe_i23;
-    input fabric_io_oe_i24;
-    input fabric_io_oe_i25;
-    input fabric_io_oe_i26;
-    input fabric_io_oe_i27;
-    input fabric_io_oe_i28;
-    input fabric_io_oe_i29;
-    input fabric_io_oe_i3;
-    input fabric_io_oe_i30;
-    input fabric_io_oe_i31;
-    input fabric_io_oe_i32;
-    input fabric_io_oe_i33;
-    input fabric_io_oe_i34;
-    input fabric_io_oe_i35;
-    input fabric_io_oe_i4;
-    input fabric_io_oe_i5;
-    input fabric_io_oe_i6;
-    input fabric_io_oe_i7;
-    input fabric_io_oe_i8;
-    input fabric_io_oe_i9;
-    output fabric_io_out_o1;
-    output fabric_io_out_o10;
-    output fabric_io_out_o11;
-    output fabric_io_out_o12;
-    output fabric_io_out_o13;
-    output fabric_io_out_o14;
-    output fabric_io_out_o15;
-    output fabric_io_out_o16;
-    output fabric_io_out_o17;
-    output fabric_io_out_o18;
-    output fabric_io_out_o19;
-    output fabric_io_out_o2;
-    output fabric_io_out_o20;
-    output fabric_io_out_o21;
-    output fabric_io_out_o22;
-    output fabric_io_out_o23;
-    output fabric_io_out_o24;
-    output fabric_io_out_o25;
-    output fabric_io_out_o26;
-    output fabric_io_out_o27;
-    output fabric_io_out_o28;
-    output fabric_io_out_o29;
-    output fabric_io_out_o3;
-    output fabric_io_out_o30;
-    output fabric_io_out_o31;
-    output fabric_io_out_o32;
-    output fabric_io_out_o33;
-    output fabric_io_out_o34;
-    output fabric_io_out_o35;
-    output fabric_io_out_o4;
-    output fabric_io_out_o5;
-    output fabric_io_out_o6;
-    output fabric_io_out_o7;
-    output fabric_io_out_o8;
-    output fabric_io_out_o9;
-    output fabric_jtag_tck_o;
-    output fabric_jtag_tdi_o;
-    input fabric_jtag_tdo_usr1_i;
-    input fabric_jtag_tdo_usr2_i;
-    output fabric_jtag_tms_o;
-    output fabric_jtag_trst_n_o;
-    output fabric_jtag_usr1_o;
-    output fabric_jtag_usr2_o;
-    input fabric_lowskew_i1;
-    input fabric_lowskew_i10;
-    input fabric_lowskew_i11;
-    input fabric_lowskew_i12;
-    input fabric_lowskew_i13;
-    input fabric_lowskew_i14;
-    input fabric_lowskew_i15;
-    input fabric_lowskew_i16;
-    input fabric_lowskew_i17;
-    input fabric_lowskew_i18;
-    input fabric_lowskew_i19;
-    input fabric_lowskew_i2;
-    input fabric_lowskew_i20;
-    input fabric_lowskew_i21;
-    input fabric_lowskew_i22;
-    input fabric_lowskew_i23;
-    input fabric_lowskew_i24;
-    input fabric_lowskew_i25;
-    input fabric_lowskew_i26;
-    input fabric_lowskew_i27;
-    input fabric_lowskew_i28;
-    input fabric_lowskew_i29;
-    input fabric_lowskew_i3;
-    input fabric_lowskew_i30;
-    input fabric_lowskew_i31;
-    input fabric_lowskew_i32;
-    input fabric_lowskew_i33;
-    input fabric_lowskew_i34;
-    input fabric_lowskew_i35;
-    input fabric_lowskew_i36;
-    input fabric_lowskew_i37;
-    input fabric_lowskew_i38;
-    input fabric_lowskew_i39;
-    input fabric_lowskew_i4;
-    input fabric_lowskew_i40;
-    input fabric_lowskew_i5;
-    input fabric_lowskew_i6;
-    input fabric_lowskew_i7;
-    input fabric_lowskew_i8;
-    input fabric_lowskew_i9;
-    output fabric_lowskew_o1;
-    output fabric_lowskew_o2;
-    output fabric_lowskew_o3;
-    output fabric_lowskew_o4;
-    output fabric_lowskew_o5;
-    output fabric_lowskew_o6;
-    output fabric_otp_user_ack_o;
-    input fabric_otp_user_add_i1;
-    input fabric_otp_user_add_i2;
-    input fabric_otp_user_add_i3;
-    input fabric_otp_user_add_i4;
-    input fabric_otp_user_add_i5;
-    input fabric_otp_user_add_i6;
-    input fabric_otp_user_add_i7;
-    output fabric_otp_user_bbad_o;
-    output fabric_otp_user_bend1_o;
-    output fabric_otp_user_bend2_o;
-    output fabric_otp_user_bist1fail_o1;
-    output fabric_otp_user_bist1fail_o2;
-    output fabric_otp_user_bist1fail_o3;
-    output fabric_otp_user_bist1fail_o4;
-    output fabric_otp_user_bist1fail_o5;
-    output fabric_otp_user_bist1fail_o6;
-    output fabric_otp_user_bist1fail_o7;
-    output fabric_otp_user_bist1fail_o8;
-    output fabric_otp_user_bist2fail_o1;
-    output fabric_otp_user_bist2fail_o2;
-    output fabric_otp_user_bist2fail_o3;
-    output fabric_otp_user_bist2fail_o4;
-    output fabric_otp_user_bist2fail_o5;
-    output fabric_otp_user_bist2fail_o6;
-    output fabric_otp_user_bist2fail_o7;
-    input fabric_otp_user_bistmode_i;
-    output fabric_otp_user_calibrated_o;
-    input fabric_otp_user_clk_i;
-    input fabric_otp_user_clock_frequency_range_i;
-    output fabric_otp_user_ded_o;
-    input fabric_otp_user_din_i1;
-    input fabric_otp_user_din_i10;
-    input fabric_otp_user_din_i11;
-    input fabric_otp_user_din_i12;
-    input fabric_otp_user_din_i13;
-    input fabric_otp_user_din_i14;
-    input fabric_otp_user_din_i15;
-    input fabric_otp_user_din_i16;
-    input fabric_otp_user_din_i17;
-    input fabric_otp_user_din_i18;
-    input fabric_otp_user_din_i19;
-    input fabric_otp_user_din_i2;
-    input fabric_otp_user_din_i20;
-    input fabric_otp_user_din_i21;
-    input fabric_otp_user_din_i22;
-    input fabric_otp_user_din_i23;
-    input fabric_otp_user_din_i24;
-    input fabric_otp_user_din_i25;
-    input fabric_otp_user_din_i26;
-    input fabric_otp_user_din_i27;
-    input fabric_otp_user_din_i28;
-    input fabric_otp_user_din_i29;
-    input fabric_otp_user_din_i3;
-    input fabric_otp_user_din_i30;
-    input fabric_otp_user_din_i31;
-    input fabric_otp_user_din_i32;
-    input fabric_otp_user_din_i33;
-    input fabric_otp_user_din_i34;
-    input fabric_otp_user_din_i35;
-    input fabric_otp_user_din_i36;
-    input fabric_otp_user_din_i37;
-    input fabric_otp_user_din_i38;
-    input fabric_otp_user_din_i39;
-    input fabric_otp_user_din_i4;
-    input fabric_otp_user_din_i5;
-    input fabric_otp_user_din_i6;
-    input fabric_otp_user_din_i7;
-    input fabric_otp_user_din_i8;
-    input fabric_otp_user_din_i9;
-    input fabric_otp_user_disturbcheck_i;
-    output fabric_otp_user_disturbed_o;
-    output fabric_otp_user_dout_o1;
-    output fabric_otp_user_dout_o10;
-    output fabric_otp_user_dout_o11;
-    output fabric_otp_user_dout_o12;
-    output fabric_otp_user_dout_o13;
-    output fabric_otp_user_dout_o14;
-    output fabric_otp_user_dout_o15;
-    output fabric_otp_user_dout_o16;
-    output fabric_otp_user_dout_o17;
-    output fabric_otp_user_dout_o18;
-    output fabric_otp_user_dout_o19;
-    output fabric_otp_user_dout_o2;
-    output fabric_otp_user_dout_o20;
-    output fabric_otp_user_dout_o21;
-    output fabric_otp_user_dout_o22;
-    output fabric_otp_user_dout_o23;
-    output fabric_otp_user_dout_o24;
-    output fabric_otp_user_dout_o25;
-    output fabric_otp_user_dout_o26;
-    output fabric_otp_user_dout_o27;
-    output fabric_otp_user_dout_o28;
-    output fabric_otp_user_dout_o29;
-    output fabric_otp_user_dout_o3;
-    output fabric_otp_user_dout_o30;
-    output fabric_otp_user_dout_o31;
-    output fabric_otp_user_dout_o32;
-    output fabric_otp_user_dout_o33;
-    output fabric_otp_user_dout_o34;
-    output fabric_otp_user_dout_o35;
-    output fabric_otp_user_dout_o36;
-    output fabric_otp_user_dout_o37;
-    output fabric_otp_user_dout_o38;
-    output fabric_otp_user_dout_o39;
-    output fabric_otp_user_dout_o4;
-    output fabric_otp_user_dout_o40;
-    output fabric_otp_user_dout_o41;
-    output fabric_otp_user_dout_o5;
-    output fabric_otp_user_dout_o6;
-    output fabric_otp_user_dout_o7;
-    output fabric_otp_user_dout_o8;
-    output fabric_otp_user_dout_o9;
-    input fabric_otp_user_eccbypass_i;
-    output fabric_otp_user_flagstate_o1;
-    output fabric_otp_user_flagstate_o2;
-    output fabric_otp_user_flagstate_o3;
-    output fabric_otp_user_flagstate_o4;
-    output fabric_otp_user_locked_o;
-    input fabric_otp_user_pdn_i;
-    input fabric_otp_user_prgwidth_i1;
-    input fabric_otp_user_prgwidth_i2;
-    input fabric_otp_user_prgwidth_i3;
-    input fabric_otp_user_prog_i;
-    output fabric_otp_user_progfail_o;
-    output fabric_otp_user_pwok_o;
-    input fabric_otp_user_rbact1_i;
-    input fabric_otp_user_rbact2_i;
-    input fabric_otp_user_read_i;
-    input fabric_otp_user_redbypass_i;
-    output fabric_otp_user_sec_o;
-    output fabric_otp_user_startword_o1;
-    output fabric_otp_user_startword_o10;
-    output fabric_otp_user_startword_o11;
-    output fabric_otp_user_startword_o12;
-    output fabric_otp_user_startword_o13;
-    output fabric_otp_user_startword_o14;
-    output fabric_otp_user_startword_o15;
-    output fabric_otp_user_startword_o16;
-    output fabric_otp_user_startword_o2;
-    output fabric_otp_user_startword_o3;
-    output fabric_otp_user_startword_o4;
-    output fabric_otp_user_startword_o5;
-    output fabric_otp_user_startword_o6;
-    output fabric_otp_user_startword_o7;
-    output fabric_otp_user_startword_o8;
-    output fabric_otp_user_startword_o9;
-    input fabric_otp_user_suppadd_i;
-    input fabric_otp_user_tm_i;
-    input fabric_otp_user_tst_scanenable_i;
-    input fabric_otp_user_tst_scanin_i1;
-    input fabric_otp_user_tst_scanin_i2;
-    input fabric_otp_user_tst_scanin_i3;
-    input fabric_otp_user_tst_scanin_i4;
-    input fabric_otp_user_tst_scanin_i5;
-    output fabric_otp_user_tst_scanout_o1;
-    output fabric_otp_user_tst_scanout_o2;
-    output fabric_otp_user_tst_scanout_o3;
-    output fabric_otp_user_tst_scanout_o4;
-    output fabric_otp_user_tst_scanout_o5;
-    output fabric_otp_user_wlromout_o1;
-    output fabric_otp_user_wlromout_o10;
-    output fabric_otp_user_wlromout_o2;
-    output fabric_otp_user_wlromout_o3;
-    output fabric_otp_user_wlromout_o4;
-    output fabric_otp_user_wlromout_o5;
-    output fabric_otp_user_wlromout_o6;
-    output fabric_otp_user_wlromout_o7;
-    output fabric_otp_user_wlromout_o8;
-    output fabric_otp_user_wlromout_o9;
-    input fabric_otp_user_wordlock_i;
-    input fabric_parusr_clk_i;
-    input fabric_parusr_cs_i;
-    input fabric_parusr_data_i1;
-    input fabric_parusr_data_i10;
-    input fabric_parusr_data_i11;
-    input fabric_parusr_data_i12;
-    input fabric_parusr_data_i13;
-    input fabric_parusr_data_i14;
-    input fabric_parusr_data_i15;
-    input fabric_parusr_data_i16;
-    input fabric_parusr_data_i2;
-    input fabric_parusr_data_i3;
-    input fabric_parusr_data_i4;
-    input fabric_parusr_data_i5;
-    input fabric_parusr_data_i6;
-    input fabric_parusr_data_i7;
-    input fabric_parusr_data_i8;
-    input fabric_parusr_data_i9;
-    output fabric_parusr_data_o1;
-    output fabric_parusr_data_o10;
-    output fabric_parusr_data_o11;
-    output fabric_parusr_data_o12;
-    output fabric_parusr_data_o13;
-    output fabric_parusr_data_o14;
-    output fabric_parusr_data_o15;
-    output fabric_parusr_data_o16;
-    output fabric_parusr_data_o2;
-    output fabric_parusr_data_o3;
-    output fabric_parusr_data_o4;
-    output fabric_parusr_data_o5;
-    output fabric_parusr_data_o6;
-    output fabric_parusr_data_o7;
-    output fabric_parusr_data_o8;
-    output fabric_parusr_data_o9;
-    output fabric_parusr_data_val_o;
-    input fabric_parusr_enable_i;
-    input fabric_parusr_type_i1;
-    input fabric_parusr_type_i2;
-    input fabric_spare_i1;
-    input fabric_spare_i10;
-    input fabric_spare_i100;
-    input fabric_spare_i101;
-    input fabric_spare_i102;
-    input fabric_spare_i103;
-    input fabric_spare_i104;
-    input fabric_spare_i105;
-    input fabric_spare_i106;
-    input fabric_spare_i107;
-    input fabric_spare_i108;
-    input fabric_spare_i109;
-    input fabric_spare_i11;
-    input fabric_spare_i110;
-    input fabric_spare_i111;
-    input fabric_spare_i112;
-    input fabric_spare_i113;
-    input fabric_spare_i114;
-    input fabric_spare_i115;
-    input fabric_spare_i116;
-    input fabric_spare_i117;
-    input fabric_spare_i118;
-    input fabric_spare_i119;
-    input fabric_spare_i12;
-    input fabric_spare_i120;
-    input fabric_spare_i121;
-    input fabric_spare_i122;
-    input fabric_spare_i123;
-    input fabric_spare_i124;
-    input fabric_spare_i125;
-    input fabric_spare_i126;
-    input fabric_spare_i127;
-    input fabric_spare_i128;
-    input fabric_spare_i13;
-    input fabric_spare_i14;
-    input fabric_spare_i15;
-    input fabric_spare_i16;
-    input fabric_spare_i17;
-    input fabric_spare_i18;
-    input fabric_spare_i19;
-    input fabric_spare_i2;
-    input fabric_spare_i20;
-    input fabric_spare_i21;
-    input fabric_spare_i22;
-    input fabric_spare_i23;
-    input fabric_spare_i24;
-    input fabric_spare_i25;
-    input fabric_spare_i26;
-    input fabric_spare_i27;
-    input fabric_spare_i28;
-    input fabric_spare_i29;
-    input fabric_spare_i3;
-    input fabric_spare_i30;
-    input fabric_spare_i31;
-    input fabric_spare_i32;
-    input fabric_spare_i33;
-    input fabric_spare_i34;
-    input fabric_spare_i35;
-    input fabric_spare_i36;
-    input fabric_spare_i37;
-    input fabric_spare_i38;
-    input fabric_spare_i39;
-    input fabric_spare_i4;
-    input fabric_spare_i40;
-    input fabric_spare_i41;
-    input fabric_spare_i42;
-    input fabric_spare_i43;
-    input fabric_spare_i44;
-    input fabric_spare_i45;
-    input fabric_spare_i46;
-    input fabric_spare_i47;
-    input fabric_spare_i48;
-    input fabric_spare_i49;
-    input fabric_spare_i5;
-    input fabric_spare_i50;
-    input fabric_spare_i51;
-    input fabric_spare_i52;
-    input fabric_spare_i53;
-    input fabric_spare_i54;
-    input fabric_spare_i55;
-    input fabric_spare_i56;
-    input fabric_spare_i57;
-    input fabric_spare_i58;
-    input fabric_spare_i59;
-    input fabric_spare_i6;
-    input fabric_spare_i60;
-    input fabric_spare_i61;
-    input fabric_spare_i62;
-    input fabric_spare_i63;
-    input fabric_spare_i64;
-    input fabric_spare_i65;
-    input fabric_spare_i66;
-    input fabric_spare_i67;
-    input fabric_spare_i68;
-    input fabric_spare_i69;
-    input fabric_spare_i7;
-    input fabric_spare_i70;
-    input fabric_spare_i71;
-    input fabric_spare_i72;
-    input fabric_spare_i73;
-    input fabric_spare_i74;
-    input fabric_spare_i75;
-    input fabric_spare_i76;
-    input fabric_spare_i77;
-    input fabric_spare_i78;
-    input fabric_spare_i79;
-    input fabric_spare_i8;
-    input fabric_spare_i80;
-    input fabric_spare_i81;
-    input fabric_spare_i82;
-    input fabric_spare_i83;
-    input fabric_spare_i84;
-    input fabric_spare_i85;
-    input fabric_spare_i86;
-    input fabric_spare_i87;
-    input fabric_spare_i88;
-    input fabric_spare_i89;
-    input fabric_spare_i9;
-    input fabric_spare_i90;
-    input fabric_spare_i91;
-    input fabric_spare_i92;
-    input fabric_spare_i93;
-    input fabric_spare_i94;
-    input fabric_spare_i95;
-    input fabric_spare_i96;
-    input fabric_spare_i97;
-    input fabric_spare_i98;
-    input fabric_spare_i99;
-    output fabric_spare_o1;
-    output fabric_spare_o10;
-    output fabric_spare_o100;
-    output fabric_spare_o101;
-    output fabric_spare_o102;
-    output fabric_spare_o103;
-    output fabric_spare_o104;
-    output fabric_spare_o105;
-    output fabric_spare_o106;
-    output fabric_spare_o107;
-    output fabric_spare_o108;
-    output fabric_spare_o109;
-    output fabric_spare_o11;
-    output fabric_spare_o110;
-    output fabric_spare_o111;
-    output fabric_spare_o112;
-    output fabric_spare_o113;
-    output fabric_spare_o114;
-    output fabric_spare_o115;
-    output fabric_spare_o116;
-    output fabric_spare_o117;
-    output fabric_spare_o118;
-    output fabric_spare_o119;
-    output fabric_spare_o12;
-    output fabric_spare_o120;
-    output fabric_spare_o121;
-    output fabric_spare_o122;
-    output fabric_spare_o123;
-    output fabric_spare_o124;
-    output fabric_spare_o125;
-    output fabric_spare_o126;
-    output fabric_spare_o127;
-    output fabric_spare_o128;
-    output fabric_spare_o13;
-    output fabric_spare_o14;
-    output fabric_spare_o15;
-    output fabric_spare_o16;
-    output fabric_spare_o17;
-    output fabric_spare_o18;
-    output fabric_spare_o19;
-    output fabric_spare_o2;
-    output fabric_spare_o20;
-    output fabric_spare_o21;
-    output fabric_spare_o22;
-    output fabric_spare_o23;
-    output fabric_spare_o24;
-    output fabric_spare_o25;
-    output fabric_spare_o26;
-    output fabric_spare_o27;
-    output fabric_spare_o28;
-    output fabric_spare_o29;
-    output fabric_spare_o3;
-    output fabric_spare_o30;
-    output fabric_spare_o31;
-    output fabric_spare_o32;
-    output fabric_spare_o33;
-    output fabric_spare_o34;
-    output fabric_spare_o35;
-    output fabric_spare_o36;
-    output fabric_spare_o37;
-    output fabric_spare_o38;
-    output fabric_spare_o39;
-    output fabric_spare_o4;
-    output fabric_spare_o40;
-    output fabric_spare_o41;
-    output fabric_spare_o42;
-    output fabric_spare_o43;
-    output fabric_spare_o44;
-    output fabric_spare_o45;
-    output fabric_spare_o46;
-    output fabric_spare_o47;
-    output fabric_spare_o48;
-    output fabric_spare_o49;
-    output fabric_spare_o5;
-    output fabric_spare_o50;
-    output fabric_spare_o51;
-    output fabric_spare_o52;
-    output fabric_spare_o53;
-    output fabric_spare_o54;
-    output fabric_spare_o55;
-    output fabric_spare_o56;
-    output fabric_spare_o57;
-    output fabric_spare_o58;
-    output fabric_spare_o59;
-    output fabric_spare_o6;
-    output fabric_spare_o60;
-    output fabric_spare_o61;
-    output fabric_spare_o62;
-    output fabric_spare_o63;
-    output fabric_spare_o64;
-    output fabric_spare_o65;
-    output fabric_spare_o66;
-    output fabric_spare_o67;
-    output fabric_spare_o68;
-    output fabric_spare_o69;
-    output fabric_spare_o7;
-    output fabric_spare_o70;
-    output fabric_spare_o71;
-    output fabric_spare_o72;
-    output fabric_spare_o73;
-    output fabric_spare_o74;
-    output fabric_spare_o75;
-    output fabric_spare_o76;
-    output fabric_spare_o77;
-    output fabric_spare_o78;
-    output fabric_spare_o79;
-    output fabric_spare_o8;
-    output fabric_spare_o80;
-    output fabric_spare_o81;
-    output fabric_spare_o82;
-    output fabric_spare_o83;
-    output fabric_spare_o84;
-    output fabric_spare_o85;
-    output fabric_spare_o86;
-    output fabric_spare_o87;
-    output fabric_spare_o88;
-    output fabric_spare_o89;
-    output fabric_spare_o9;
-    output fabric_spare_o90;
-    output fabric_spare_o91;
-    output fabric_spare_o92;
-    output fabric_spare_o93;
-    output fabric_spare_o94;
-    output fabric_spare_o95;
-    output fabric_spare_o96;
-    output fabric_spare_o97;
-    output fabric_spare_o98;
-    output fabric_spare_o99;
-    input fabric_spi_arst_tmr_n_i1;
-    input fabric_spi_arst_tmr_n_i2;
-    input fabric_spi_arst_tmr_n_i3;
-    input fabric_spi_arst_tmr_n_i4;
-    input fabric_spi_arst_tmr_n_i5;
-    input fabric_spi_arst_tmr_n_i6;
-    input fabric_spi_arst_tmr_n_i7;
-    input fabric_spi_arst_tmr_n_i8;
-    input fabric_spi_arst_tmr_n_i9;
-    output fabric_spi_bsm_release_o1;
-    output fabric_spi_bsm_release_o2;
-    output fabric_spi_bsm_release_o3;
-    output fabric_spi_busy_o1;
-    output fabric_spi_busy_o2;
-    output fabric_spi_busy_o3;
-    input fabric_spi_clk_i0;
-    input fabric_spi_clk_i1;
-    input fabric_spi_clk_i2;
-    input fabric_spi_cmd_bytes_i1;
-    input fabric_spi_cmd_bytes_i2;
-    input fabric_spi_cmd_bytes_i3;
-    input fabric_spi_cmd_bytes_i4;
-    input fabric_spi_cmd_bytes_i5;
-    input fabric_spi_cmd_bytes_i6;
-    output fabric_spi_cmd_full_o1;
-    output fabric_spi_cmd_full_o2;
-    output fabric_spi_cmd_full_o3;
-    input fabric_spi_cmd_mode_i1;
-    input fabric_spi_cmd_mode_i2;
-    input fabric_spi_cmd_mode_i3;
-    input fabric_spi_cmd_mode_i4;
-    input fabric_spi_cmd_mode_i5;
-    input fabric_spi_cmd_mode_i6;
-    input fabric_spi_cmd_push_i1;
-    input fabric_spi_cmd_push_i2;
-    input fabric_spi_cmd_push_i3;
-    input fabric_spi_cmd_type_i1;
-    input fabric_spi_cmd_type_i2;
-    input fabric_spi_cmd_type_i3;
-    input fabric_spi_cmd_type_i4;
-    input fabric_spi_cmd_type_i5;
-    input fabric_spi_cmd_type_i6;
-    input fabric_spi_cpha_i1;
-    input fabric_spi_cpha_i2;
-    input fabric_spi_cpha_i3;
-    input fabric_spi_cpol_i1;
-    input fabric_spi_cpol_i2;
-    input fabric_spi_cpol_i3;
-    input fabric_spi_cs_holdtime_i1;
-    input fabric_spi_cs_holdtime_i10;
-    input fabric_spi_cs_holdtime_i11;
-    input fabric_spi_cs_holdtime_i12;
-    input fabric_spi_cs_holdtime_i2;
-    input fabric_spi_cs_holdtime_i3;
-    input fabric_spi_cs_holdtime_i4;
-    input fabric_spi_cs_holdtime_i5;
-    input fabric_spi_cs_holdtime_i6;
-    input fabric_spi_cs_holdtime_i7;
-    input fabric_spi_cs_holdtime_i8;
-    input fabric_spi_cs_holdtime_i9;
-    input fabric_spi_cs_offtime_i1;
-    input fabric_spi_cs_offtime_i10;
-    input fabric_spi_cs_offtime_i11;
-    input fabric_spi_cs_offtime_i12;
-    input fabric_spi_cs_offtime_i2;
-    input fabric_spi_cs_offtime_i3;
-    input fabric_spi_cs_offtime_i4;
-    input fabric_spi_cs_offtime_i5;
-    input fabric_spi_cs_offtime_i6;
-    input fabric_spi_cs_offtime_i7;
-    input fabric_spi_cs_offtime_i8;
-    input fabric_spi_cs_offtime_i9;
-    input fabric_spi_cs_setuptime_i1;
-    input fabric_spi_cs_setuptime_i10;
-    input fabric_spi_cs_setuptime_i11;
-    input fabric_spi_cs_setuptime_i12;
-    input fabric_spi_cs_setuptime_i2;
-    input fabric_spi_cs_setuptime_i3;
-    input fabric_spi_cs_setuptime_i4;
-    input fabric_spi_cs_setuptime_i5;
-    input fabric_spi_cs_setuptime_i6;
-    input fabric_spi_cs_setuptime_i7;
-    input fabric_spi_cs_setuptime_i8;
-    input fabric_spi_cs_setuptime_i9;
-    input fabric_spi_data_in_unlimited_i1;
-    input fabric_spi_data_in_unlimited_i2;
-    input fabric_spi_data_in_unlimited_i3;
-    input fabric_spi_enable_i1;
-    input fabric_spi_enable_i2;
-    input fabric_spi_enable_i3;
-    output fabric_spi_error_endianness_o1;
-    output fabric_spi_error_endianness_o2;
-    output fabric_spi_error_endianness_o3;
-    output fabric_spi_error_loopback_o1;
-    output fabric_spi_error_loopback_o2;
-    output fabric_spi_error_loopback_o3;
-    output fabric_spi_error_mode_o1;
-    output fabric_spi_error_mode_o2;
-    output fabric_spi_error_mode_o3;
-    output fabric_spi_error_sel_o1;
-    output fabric_spi_error_sel_o2;
-    output fabric_spi_error_sel_o3;
-    input fabric_spi_fifo_arst_tmr_n_i1;
-    input fabric_spi_fifo_arst_tmr_n_i2;
-    input fabric_spi_fifo_arst_tmr_n_i3;
-    input fabric_spi_fifo_arst_tmr_n_i4;
-    input fabric_spi_fifo_arst_tmr_n_i5;
-    input fabric_spi_fifo_arst_tmr_n_i6;
-    input fabric_spi_fifo_arst_tmr_n_i7;
-    input fabric_spi_fifo_arst_tmr_n_i8;
-    input fabric_spi_fifo_arst_tmr_n_i9;
-    output fabric_spi_init_done_o1;
-    output fabric_spi_init_done_o2;
-    output fabric_spi_init_done_o3;
-    input fabric_spi_legacy_enable_i1;
-    input fabric_spi_legacy_enable_i2;
-    input fabric_spi_legacy_enable_i3;
-    input fabric_spi_legacy_master_i1;
-    input fabric_spi_legacy_master_i2;
-    input fabric_spi_legacy_master_i3;
-    input fabric_spi_loopback_i1;
-    input fabric_spi_loopback_i2;
-    input fabric_spi_loopback_i3;
-    input fabric_spi_lsb_first_i1;
-    input fabric_spi_lsb_first_i2;
-    input fabric_spi_lsb_first_i3;
-    output fabric_spi_miso_data_inv_o1;
-    output fabric_spi_miso_data_inv_o2;
-    output fabric_spi_miso_data_inv_o3;
-    output fabric_spi_miso_data_o1;
-    output fabric_spi_miso_data_o10;
-    output fabric_spi_miso_data_o11;
-    output fabric_spi_miso_data_o12;
-    output fabric_spi_miso_data_o13;
-    output fabric_spi_miso_data_o14;
-    output fabric_spi_miso_data_o15;
-    output fabric_spi_miso_data_o16;
-    output fabric_spi_miso_data_o17;
-    output fabric_spi_miso_data_o18;
-    output fabric_spi_miso_data_o19;
-    output fabric_spi_miso_data_o2;
-    output fabric_spi_miso_data_o20;
-    output fabric_spi_miso_data_o21;
-    output fabric_spi_miso_data_o22;
-    output fabric_spi_miso_data_o23;
-    output fabric_spi_miso_data_o24;
-    output fabric_spi_miso_data_o3;
-    output fabric_spi_miso_data_o4;
-    output fabric_spi_miso_data_o5;
-    output fabric_spi_miso_data_o6;
-    output fabric_spi_miso_data_o7;
-    output fabric_spi_miso_data_o8;
-    output fabric_spi_miso_data_o9;
-    output fabric_spi_miso_empty_o1;
-    output fabric_spi_miso_empty_o2;
-    output fabric_spi_miso_empty_o3;
-    input fabric_spi_miso_pop_i1;
-    input fabric_spi_miso_pop_i2;
-    input fabric_spi_miso_pop_i3;
-    input fabric_spi_mosi_data_i1;
-    input fabric_spi_mosi_data_i10;
-    input fabric_spi_mosi_data_i11;
-    input fabric_spi_mosi_data_i12;
-    input fabric_spi_mosi_data_i13;
-    input fabric_spi_mosi_data_i14;
-    input fabric_spi_mosi_data_i15;
-    input fabric_spi_mosi_data_i16;
-    input fabric_spi_mosi_data_i17;
-    input fabric_spi_mosi_data_i18;
-    input fabric_spi_mosi_data_i19;
-    input fabric_spi_mosi_data_i2;
-    input fabric_spi_mosi_data_i20;
-    input fabric_spi_mosi_data_i21;
-    input fabric_spi_mosi_data_i22;
-    input fabric_spi_mosi_data_i23;
-    input fabric_spi_mosi_data_i24;
-    input fabric_spi_mosi_data_i3;
-    input fabric_spi_mosi_data_i4;
-    input fabric_spi_mosi_data_i5;
-    input fabric_spi_mosi_data_i6;
-    input fabric_spi_mosi_data_i7;
-    input fabric_spi_mosi_data_i8;
-    input fabric_spi_mosi_data_i9;
-    input fabric_spi_mosi_data_inv_i1;
-    input fabric_spi_mosi_data_inv_i2;
-    input fabric_spi_mosi_data_inv_i3;
-    output fabric_spi_mosi_full_o1;
-    output fabric_spi_mosi_full_o2;
-    output fabric_spi_mosi_full_o3;
-    input fabric_spi_mosi_push_i1;
-    input fabric_spi_mosi_push_i2;
-    input fabric_spi_mosi_push_i3;
-    input fabric_spi_needed_i1;
-    input fabric_spi_needed_i2;
-    input fabric_spi_needed_i3;
-    input fabric_spi_powerdown_cycle_i1;
-    input fabric_spi_powerdown_cycle_i10;
-    input fabric_spi_powerdown_cycle_i11;
-    input fabric_spi_powerdown_cycle_i12;
-    input fabric_spi_powerdown_cycle_i13;
-    input fabric_spi_powerdown_cycle_i14;
-    input fabric_spi_powerdown_cycle_i15;
-    input fabric_spi_powerdown_cycle_i16;
-    input fabric_spi_powerdown_cycle_i17;
-    input fabric_spi_powerdown_cycle_i18;
-    input fabric_spi_powerdown_cycle_i19;
-    input fabric_spi_powerdown_cycle_i2;
-    input fabric_spi_powerdown_cycle_i20;
-    input fabric_spi_powerdown_cycle_i21;
-    input fabric_spi_powerdown_cycle_i22;
-    input fabric_spi_powerdown_cycle_i23;
-    input fabric_spi_powerdown_cycle_i24;
-    input fabric_spi_powerdown_cycle_i25;
-    input fabric_spi_powerdown_cycle_i26;
-    input fabric_spi_powerdown_cycle_i27;
-    input fabric_spi_powerdown_cycle_i28;
-    input fabric_spi_powerdown_cycle_i29;
-    input fabric_spi_powerdown_cycle_i3;
-    input fabric_spi_powerdown_cycle_i30;
-    input fabric_spi_powerdown_cycle_i31;
-    input fabric_spi_powerdown_cycle_i32;
-    input fabric_spi_powerdown_cycle_i33;
-    input fabric_spi_powerdown_cycle_i34;
-    input fabric_spi_powerdown_cycle_i35;
-    input fabric_spi_powerdown_cycle_i36;
-    input fabric_spi_powerdown_cycle_i37;
-    input fabric_spi_powerdown_cycle_i38;
-    input fabric_spi_powerdown_cycle_i39;
-    input fabric_spi_powerdown_cycle_i4;
-    input fabric_spi_powerdown_cycle_i40;
-    input fabric_spi_powerdown_cycle_i41;
-    input fabric_spi_powerdown_cycle_i42;
-    input fabric_spi_powerdown_cycle_i43;
-    input fabric_spi_powerdown_cycle_i44;
-    input fabric_spi_powerdown_cycle_i45;
-    input fabric_spi_powerdown_cycle_i46;
-    input fabric_spi_powerdown_cycle_i47;
-    input fabric_spi_powerdown_cycle_i48;
-    input fabric_spi_powerdown_cycle_i5;
-    input fabric_spi_powerdown_cycle_i6;
-    input fabric_spi_powerdown_cycle_i7;
-    input fabric_spi_powerdown_cycle_i8;
-    input fabric_spi_powerdown_cycle_i9;
-    input fabric_spi_powerup_cycle_i1;
-    input fabric_spi_powerup_cycle_i10;
-    input fabric_spi_powerup_cycle_i11;
-    input fabric_spi_powerup_cycle_i12;
-    input fabric_spi_powerup_cycle_i13;
-    input fabric_spi_powerup_cycle_i14;
-    input fabric_spi_powerup_cycle_i15;
-    input fabric_spi_powerup_cycle_i16;
-    input fabric_spi_powerup_cycle_i17;
-    input fabric_spi_powerup_cycle_i18;
-    input fabric_spi_powerup_cycle_i19;
-    input fabric_spi_powerup_cycle_i2;
-    input fabric_spi_powerup_cycle_i20;
-    input fabric_spi_powerup_cycle_i21;
-    input fabric_spi_powerup_cycle_i22;
-    input fabric_spi_powerup_cycle_i23;
-    input fabric_spi_powerup_cycle_i24;
-    input fabric_spi_powerup_cycle_i25;
-    input fabric_spi_powerup_cycle_i26;
-    input fabric_spi_powerup_cycle_i27;
-    input fabric_spi_powerup_cycle_i28;
-    input fabric_spi_powerup_cycle_i29;
-    input fabric_spi_powerup_cycle_i3;
-    input fabric_spi_powerup_cycle_i30;
-    input fabric_spi_powerup_cycle_i31;
-    input fabric_spi_powerup_cycle_i32;
-    input fabric_spi_powerup_cycle_i33;
-    input fabric_spi_powerup_cycle_i34;
-    input fabric_spi_powerup_cycle_i35;
-    input fabric_spi_powerup_cycle_i36;
-    input fabric_spi_powerup_cycle_i37;
-    input fabric_spi_powerup_cycle_i38;
-    input fabric_spi_powerup_cycle_i39;
-    input fabric_spi_powerup_cycle_i4;
-    input fabric_spi_powerup_cycle_i40;
-    input fabric_spi_powerup_cycle_i41;
-    input fabric_spi_powerup_cycle_i42;
-    input fabric_spi_powerup_cycle_i43;
-    input fabric_spi_powerup_cycle_i44;
-    input fabric_spi_powerup_cycle_i45;
-    input fabric_spi_powerup_cycle_i46;
-    input fabric_spi_powerup_cycle_i47;
-    input fabric_spi_powerup_cycle_i48;
-    input fabric_spi_powerup_cycle_i5;
-    input fabric_spi_powerup_cycle_i6;
-    input fabric_spi_powerup_cycle_i7;
-    input fabric_spi_powerup_cycle_i8;
-    input fabric_spi_powerup_cycle_i9;
-    input fabric_spi_rst_n_i1;
-    input fabric_spi_rst_n_i2;
-    input fabric_spi_rst_n_i3;
-    input fabric_spi_sck_i0;
-    input fabric_spi_sck_i1;
-    input fabric_spi_sck_i2;
-    input fabric_spi_vcc_enable_i1;
-    input fabric_spi_vcc_enable_i2;
-    input fabric_spi_vcc_enable_i3;
-    output fabric_spi_vcc_used_o1;
-    output fabric_spi_vcc_used_o2;
-    output fabric_spi_vcc_used_o3;
-    input fabric_spw0_apb_slv_paddr_i1;
-    input fabric_spw0_apb_slv_paddr_i2;
-    input fabric_spw0_apb_slv_paddr_i3;
-    input fabric_spw0_apb_slv_paddr_i4;
-    input fabric_spw0_apb_slv_paddr_i5;
-    input fabric_spw0_apb_slv_penable_i;
-    output fabric_spw0_apb_slv_prdata_o1;
-    output fabric_spw0_apb_slv_prdata_o10;
-    output fabric_spw0_apb_slv_prdata_o11;
-    output fabric_spw0_apb_slv_prdata_o12;
-    output fabric_spw0_apb_slv_prdata_o13;
-    output fabric_spw0_apb_slv_prdata_o14;
-    output fabric_spw0_apb_slv_prdata_o15;
-    output fabric_spw0_apb_slv_prdata_o16;
-    output fabric_spw0_apb_slv_prdata_o17;
-    output fabric_spw0_apb_slv_prdata_o18;
-    output fabric_spw0_apb_slv_prdata_o19;
-    output fabric_spw0_apb_slv_prdata_o2;
-    output fabric_spw0_apb_slv_prdata_o20;
-    output fabric_spw0_apb_slv_prdata_o21;
-    output fabric_spw0_apb_slv_prdata_o22;
-    output fabric_spw0_apb_slv_prdata_o23;
-    output fabric_spw0_apb_slv_prdata_o24;
-    output fabric_spw0_apb_slv_prdata_o25;
-    output fabric_spw0_apb_slv_prdata_o26;
-    output fabric_spw0_apb_slv_prdata_o27;
-    output fabric_spw0_apb_slv_prdata_o28;
-    output fabric_spw0_apb_slv_prdata_o29;
-    output fabric_spw0_apb_slv_prdata_o3;
-    output fabric_spw0_apb_slv_prdata_o30;
-    output fabric_spw0_apb_slv_prdata_o31;
-    output fabric_spw0_apb_slv_prdata_o4;
-    output fabric_spw0_apb_slv_prdata_o5;
-    output fabric_spw0_apb_slv_prdata_o6;
-    output fabric_spw0_apb_slv_prdata_o7;
-    output fabric_spw0_apb_slv_prdata_o8;
-    output fabric_spw0_apb_slv_prdata_o9;
-    output fabric_spw0_apb_slv_pready_o;
-    input fabric_spw0_apb_slv_psel_i;
-    output fabric_spw0_apb_slv_pslverr_o;
-    input fabric_spw0_apb_slv_pwdata_i1;
-    input fabric_spw0_apb_slv_pwdata_i10;
-    input fabric_spw0_apb_slv_pwdata_i11;
-    input fabric_spw0_apb_slv_pwdata_i12;
-    input fabric_spw0_apb_slv_pwdata_i13;
-    input fabric_spw0_apb_slv_pwdata_i14;
-    input fabric_spw0_apb_slv_pwdata_i15;
-    input fabric_spw0_apb_slv_pwdata_i16;
-    input fabric_spw0_apb_slv_pwdata_i17;
-    input fabric_spw0_apb_slv_pwdata_i18;
-    input fabric_spw0_apb_slv_pwdata_i19;
-    input fabric_spw0_apb_slv_pwdata_i2;
-    input fabric_spw0_apb_slv_pwdata_i20;
-    input fabric_spw0_apb_slv_pwdata_i21;
-    input fabric_spw0_apb_slv_pwdata_i22;
-    input fabric_spw0_apb_slv_pwdata_i23;
-    input fabric_spw0_apb_slv_pwdata_i24;
-    input fabric_spw0_apb_slv_pwdata_i25;
-    input fabric_spw0_apb_slv_pwdata_i26;
-    input fabric_spw0_apb_slv_pwdata_i27;
-    input fabric_spw0_apb_slv_pwdata_i28;
-    input fabric_spw0_apb_slv_pwdata_i29;
-    input fabric_spw0_apb_slv_pwdata_i3;
-    input fabric_spw0_apb_slv_pwdata_i30;
-    input fabric_spw0_apb_slv_pwdata_i31;
-    input fabric_spw0_apb_slv_pwdata_i4;
-    input fabric_spw0_apb_slv_pwdata_i5;
-    input fabric_spw0_apb_slv_pwdata_i6;
-    input fabric_spw0_apb_slv_pwdata_i7;
-    input fabric_spw0_apb_slv_pwdata_i8;
-    input fabric_spw0_apb_slv_pwdata_i9;
-    input fabric_spw0_apb_slv_pwrite_i;
-    input fabric_spw0_clk_i;
-    input fabric_spw0_clk_tx_i;
-    input fabric_spw0_rst_n_i;
-    output fabric_spw0_rx_fifo_data_o1;
-    output fabric_spw0_rx_fifo_data_o2;
-    output fabric_spw0_rx_fifo_data_o3;
-    output fabric_spw0_rx_fifo_data_o4;
-    output fabric_spw0_rx_fifo_data_o5;
-    output fabric_spw0_rx_fifo_data_o6;
-    output fabric_spw0_rx_fifo_data_o7;
-    output fabric_spw0_rx_fifo_data_o8;
-    output fabric_spw0_rx_fifo_data_o9;
-    output fabric_spw0_rx_fifo_empty_o;
-    input fabric_spw0_rx_fifo_read_i;
-    input fabric_spw0_tick_ctm_i;
-    output fabric_spw0_tick_ctm_o;
-    input fabric_spw0_tx_fifo_data_i1;
-    input fabric_spw0_tx_fifo_data_i2;
-    input fabric_spw0_tx_fifo_data_i3;
-    input fabric_spw0_tx_fifo_data_i4;
-    input fabric_spw0_tx_fifo_data_i5;
-    input fabric_spw0_tx_fifo_data_i6;
-    input fabric_spw0_tx_fifo_data_i7;
-    input fabric_spw0_tx_fifo_data_i8;
-    input fabric_spw0_tx_fifo_data_i9;
-    output fabric_spw0_tx_fifo_full_o;
-    input fabric_spw0_tx_fifo_write_i;
-    output fabric_spw0_user_shared_o;
-    input fabric_spw1_apb_slv_paddr_i1;
-    input fabric_spw1_apb_slv_paddr_i2;
-    input fabric_spw1_apb_slv_paddr_i3;
-    input fabric_spw1_apb_slv_paddr_i4;
-    input fabric_spw1_apb_slv_paddr_i5;
-    input fabric_spw1_apb_slv_penable_i;
-    output fabric_spw1_apb_slv_prdata_o1;
-    output fabric_spw1_apb_slv_prdata_o10;
-    output fabric_spw1_apb_slv_prdata_o11;
-    output fabric_spw1_apb_slv_prdata_o12;
-    output fabric_spw1_apb_slv_prdata_o13;
-    output fabric_spw1_apb_slv_prdata_o14;
-    output fabric_spw1_apb_slv_prdata_o15;
-    output fabric_spw1_apb_slv_prdata_o16;
-    output fabric_spw1_apb_slv_prdata_o17;
-    output fabric_spw1_apb_slv_prdata_o18;
-    output fabric_spw1_apb_slv_prdata_o19;
-    output fabric_spw1_apb_slv_prdata_o2;
-    output fabric_spw1_apb_slv_prdata_o20;
-    output fabric_spw1_apb_slv_prdata_o21;
-    output fabric_spw1_apb_slv_prdata_o22;
-    output fabric_spw1_apb_slv_prdata_o23;
-    output fabric_spw1_apb_slv_prdata_o24;
-    output fabric_spw1_apb_slv_prdata_o25;
-    output fabric_spw1_apb_slv_prdata_o26;
-    output fabric_spw1_apb_slv_prdata_o27;
-    output fabric_spw1_apb_slv_prdata_o28;
-    output fabric_spw1_apb_slv_prdata_o29;
-    output fabric_spw1_apb_slv_prdata_o3;
-    output fabric_spw1_apb_slv_prdata_o30;
-    output fabric_spw1_apb_slv_prdata_o31;
-    output fabric_spw1_apb_slv_prdata_o4;
-    output fabric_spw1_apb_slv_prdata_o5;
-    output fabric_spw1_apb_slv_prdata_o6;
-    output fabric_spw1_apb_slv_prdata_o7;
-    output fabric_spw1_apb_slv_prdata_o8;
-    output fabric_spw1_apb_slv_prdata_o9;
-    output fabric_spw1_apb_slv_pready_o;
-    input fabric_spw1_apb_slv_psel_i;
-    output fabric_spw1_apb_slv_pslverr_o;
-    input fabric_spw1_apb_slv_pwdata_i1;
-    input fabric_spw1_apb_slv_pwdata_i10;
-    input fabric_spw1_apb_slv_pwdata_i11;
-    input fabric_spw1_apb_slv_pwdata_i12;
-    input fabric_spw1_apb_slv_pwdata_i13;
-    input fabric_spw1_apb_slv_pwdata_i14;
-    input fabric_spw1_apb_slv_pwdata_i15;
-    input fabric_spw1_apb_slv_pwdata_i16;
-    input fabric_spw1_apb_slv_pwdata_i17;
-    input fabric_spw1_apb_slv_pwdata_i18;
-    input fabric_spw1_apb_slv_pwdata_i19;
-    input fabric_spw1_apb_slv_pwdata_i2;
-    input fabric_spw1_apb_slv_pwdata_i20;
-    input fabric_spw1_apb_slv_pwdata_i21;
-    input fabric_spw1_apb_slv_pwdata_i22;
-    input fabric_spw1_apb_slv_pwdata_i23;
-    input fabric_spw1_apb_slv_pwdata_i24;
-    input fabric_spw1_apb_slv_pwdata_i25;
-    input fabric_spw1_apb_slv_pwdata_i26;
-    input fabric_spw1_apb_slv_pwdata_i27;
-    input fabric_spw1_apb_slv_pwdata_i28;
-    input fabric_spw1_apb_slv_pwdata_i29;
-    input fabric_spw1_apb_slv_pwdata_i3;
-    input fabric_spw1_apb_slv_pwdata_i30;
-    input fabric_spw1_apb_slv_pwdata_i31;
-    input fabric_spw1_apb_slv_pwdata_i4;
-    input fabric_spw1_apb_slv_pwdata_i5;
-    input fabric_spw1_apb_slv_pwdata_i6;
-    input fabric_spw1_apb_slv_pwdata_i7;
-    input fabric_spw1_apb_slv_pwdata_i8;
-    input fabric_spw1_apb_slv_pwdata_i9;
-    input fabric_spw1_apb_slv_pwrite_i;
-    input fabric_spw1_clk_i;
-    input fabric_spw1_clk_tx_i;
-    input fabric_spw1_rst_n_i;
-    output fabric_spw1_rx_fifo_data_o1;
-    output fabric_spw1_rx_fifo_data_o2;
-    output fabric_spw1_rx_fifo_data_o3;
-    output fabric_spw1_rx_fifo_data_o4;
-    output fabric_spw1_rx_fifo_data_o5;
-    output fabric_spw1_rx_fifo_data_o6;
-    output fabric_spw1_rx_fifo_data_o7;
-    output fabric_spw1_rx_fifo_data_o8;
-    output fabric_spw1_rx_fifo_data_o9;
-    output fabric_spw1_rx_fifo_empty_o;
-    input fabric_spw1_rx_fifo_read_i;
-    input fabric_spw1_tick_ctm_i;
-    output fabric_spw1_tick_ctm_o;
-    input fabric_spw1_tx_fifo_data_i1;
-    input fabric_spw1_tx_fifo_data_i2;
-    input fabric_spw1_tx_fifo_data_i3;
-    input fabric_spw1_tx_fifo_data_i4;
-    input fabric_spw1_tx_fifo_data_i5;
-    input fabric_spw1_tx_fifo_data_i6;
-    input fabric_spw1_tx_fifo_data_i7;
-    input fabric_spw1_tx_fifo_data_i8;
-    input fabric_spw1_tx_fifo_data_i9;
-    output fabric_spw1_tx_fifo_full_o;
-    input fabric_spw1_tx_fifo_write_i;
-    output fabric_spw1_user_shared_o;
-    output fabric_status_cold_start_o;
-    input fabric_thsens_arst_tmr_n_i1;
-    input fabric_thsens_arst_tmr_n_i2;
-    input fabric_thsens_arst_tmr_n_i3;
-    input fabric_thsens_clk_div_ratio_i1;
-    input fabric_thsens_clk_div_ratio_i2;
-    input fabric_thsens_clk_div_ratio_i3;
-    input fabric_thsens_clk_div_ratio_i4;
-    input fabric_thsens_clk_div_ratio_i5;
-    input fabric_thsens_clk_div_ratio_i6;
-    input fabric_thsens_clk_div_ratio_i7;
-    input fabric_thsens_clk_div_ratio_i8;
-    input fabric_thsens_clk_i;
-    output fabric_thsens_fm_config_r_o1;
-    output fabric_thsens_fm_config_r_o10;
-    output fabric_thsens_fm_config_r_o11;
-    output fabric_thsens_fm_config_r_o12;
-    output fabric_thsens_fm_config_r_o13;
-    output fabric_thsens_fm_config_r_o14;
-    output fabric_thsens_fm_config_r_o15;
-    output fabric_thsens_fm_config_r_o16;
-    output fabric_thsens_fm_config_r_o17;
-    output fabric_thsens_fm_config_r_o18;
-    output fabric_thsens_fm_config_r_o19;
-    output fabric_thsens_fm_config_r_o2;
-    output fabric_thsens_fm_config_r_o20;
-    output fabric_thsens_fm_config_r_o21;
-    output fabric_thsens_fm_config_r_o22;
-    output fabric_thsens_fm_config_r_o23;
-    output fabric_thsens_fm_config_r_o24;
-    output fabric_thsens_fm_config_r_o25;
-    output fabric_thsens_fm_config_r_o26;
-    output fabric_thsens_fm_config_r_o27;
-    output fabric_thsens_fm_config_r_o3;
-    output fabric_thsens_fm_config_r_o4;
-    output fabric_thsens_fm_config_r_o5;
-    output fabric_thsens_fm_config_r_o6;
-    output fabric_thsens_fm_config_r_o7;
-    output fabric_thsens_fm_config_r_o8;
-    output fabric_thsens_fm_config_r_o9;
-    input fabric_thsens_fm_config_w_i1;
-    input fabric_thsens_fm_config_w_i10;
-    input fabric_thsens_fm_config_w_i11;
-    input fabric_thsens_fm_config_w_i12;
-    input fabric_thsens_fm_config_w_i13;
-    input fabric_thsens_fm_config_w_i14;
-    input fabric_thsens_fm_config_w_i15;
-    input fabric_thsens_fm_config_w_i16;
-    input fabric_thsens_fm_config_w_i17;
-    input fabric_thsens_fm_config_w_i18;
-    input fabric_thsens_fm_config_w_i19;
-    input fabric_thsens_fm_config_w_i2;
-    input fabric_thsens_fm_config_w_i20;
-    input fabric_thsens_fm_config_w_i21;
-    input fabric_thsens_fm_config_w_i22;
-    input fabric_thsens_fm_config_w_i23;
-    input fabric_thsens_fm_config_w_i24;
-    input fabric_thsens_fm_config_w_i25;
-    input fabric_thsens_fm_config_w_i26;
-    input fabric_thsens_fm_config_w_i27;
-    input fabric_thsens_fm_config_w_i3;
-    input fabric_thsens_fm_config_w_i4;
-    input fabric_thsens_fm_config_w_i5;
-    input fabric_thsens_fm_config_w_i6;
-    input fabric_thsens_fm_config_w_i7;
-    input fabric_thsens_fm_config_w_i8;
-    input fabric_thsens_fm_config_w_i9;
-    input fabric_thsens_fm_config_wen_i;
-    output fabric_thsens_fm_data_o1;
-    output fabric_thsens_fm_data_o10;
-    output fabric_thsens_fm_data_o11;
-    output fabric_thsens_fm_data_o12;
-    output fabric_thsens_fm_data_o13;
-    output fabric_thsens_fm_data_o14;
-    output fabric_thsens_fm_data_o2;
-    output fabric_thsens_fm_data_o3;
-    output fabric_thsens_fm_data_o4;
-    output fabric_thsens_fm_data_o5;
-    output fabric_thsens_fm_data_o6;
-    output fabric_thsens_fm_data_o7;
-    output fabric_thsens_fm_data_o8;
-    output fabric_thsens_fm_data_o9;
-    input fabric_thsens_fm_enable_i;
-    output fabric_thsens_fm_mode_r_o1;
-    output fabric_thsens_fm_mode_r_o10;
-    output fabric_thsens_fm_mode_r_o11;
-    output fabric_thsens_fm_mode_r_o12;
-    output fabric_thsens_fm_mode_r_o13;
-    output fabric_thsens_fm_mode_r_o14;
-    output fabric_thsens_fm_mode_r_o15;
-    output fabric_thsens_fm_mode_r_o16;
-    output fabric_thsens_fm_mode_r_o17;
-    output fabric_thsens_fm_mode_r_o18;
-    output fabric_thsens_fm_mode_r_o19;
-    output fabric_thsens_fm_mode_r_o2;
-    output fabric_thsens_fm_mode_r_o20;
-    output fabric_thsens_fm_mode_r_o21;
-    output fabric_thsens_fm_mode_r_o22;
-    output fabric_thsens_fm_mode_r_o23;
-    output fabric_thsens_fm_mode_r_o24;
-    output fabric_thsens_fm_mode_r_o25;
-    output fabric_thsens_fm_mode_r_o26;
-    output fabric_thsens_fm_mode_r_o27;
-    output fabric_thsens_fm_mode_r_o28;
-    output fabric_thsens_fm_mode_r_o29;
-    output fabric_thsens_fm_mode_r_o3;
-    output fabric_thsens_fm_mode_r_o30;
-    output fabric_thsens_fm_mode_r_o31;
-    output fabric_thsens_fm_mode_r_o32;
-    output fabric_thsens_fm_mode_r_o4;
-    output fabric_thsens_fm_mode_r_o5;
-    output fabric_thsens_fm_mode_r_o6;
-    output fabric_thsens_fm_mode_r_o7;
-    output fabric_thsens_fm_mode_r_o8;
-    output fabric_thsens_fm_mode_r_o9;
-    input fabric_thsens_fm_mode_w_i1;
-    input fabric_thsens_fm_mode_w_i10;
-    input fabric_thsens_fm_mode_w_i11;
-    input fabric_thsens_fm_mode_w_i12;
-    input fabric_thsens_fm_mode_w_i13;
-    input fabric_thsens_fm_mode_w_i14;
-    input fabric_thsens_fm_mode_w_i15;
-    input fabric_thsens_fm_mode_w_i16;
-    input fabric_thsens_fm_mode_w_i17;
-    input fabric_thsens_fm_mode_w_i18;
-    input fabric_thsens_fm_mode_w_i19;
-    input fabric_thsens_fm_mode_w_i2;
-    input fabric_thsens_fm_mode_w_i20;
-    input fabric_thsens_fm_mode_w_i21;
-    input fabric_thsens_fm_mode_w_i22;
-    input fabric_thsens_fm_mode_w_i23;
-    input fabric_thsens_fm_mode_w_i24;
-    input fabric_thsens_fm_mode_w_i25;
-    input fabric_thsens_fm_mode_w_i26;
-    input fabric_thsens_fm_mode_w_i27;
-    input fabric_thsens_fm_mode_w_i28;
-    input fabric_thsens_fm_mode_w_i29;
-    input fabric_thsens_fm_mode_w_i3;
-    input fabric_thsens_fm_mode_w_i30;
-    input fabric_thsens_fm_mode_w_i31;
-    input fabric_thsens_fm_mode_w_i32;
-    input fabric_thsens_fm_mode_w_i4;
-    input fabric_thsens_fm_mode_w_i5;
-    input fabric_thsens_fm_mode_w_i6;
-    input fabric_thsens_fm_mode_w_i7;
-    input fabric_thsens_fm_mode_w_i8;
-    input fabric_thsens_fm_mode_w_i9;
-    input fabric_thsens_fm_mode_wen_i;
-    output fabric_thsens_fm_overflow_o;
-    output fabric_thsens_fm_valid_o;
-    output fabric_thsens_otp_config_o1;
-    output fabric_thsens_otp_config_o10;
-    output fabric_thsens_otp_config_o11;
-    output fabric_thsens_otp_config_o12;
-    output fabric_thsens_otp_config_o13;
-    output fabric_thsens_otp_config_o14;
-    output fabric_thsens_otp_config_o15;
-    output fabric_thsens_otp_config_o16;
-    output fabric_thsens_otp_config_o17;
-    output fabric_thsens_otp_config_o18;
-    output fabric_thsens_otp_config_o19;
-    output fabric_thsens_otp_config_o2;
-    output fabric_thsens_otp_config_o20;
-    output fabric_thsens_otp_config_o21;
-    output fabric_thsens_otp_config_o22;
-    output fabric_thsens_otp_config_o23;
-    output fabric_thsens_otp_config_o24;
-    output fabric_thsens_otp_config_o25;
-    output fabric_thsens_otp_config_o26;
-    output fabric_thsens_otp_config_o27;
-    output fabric_thsens_otp_config_o3;
-    output fabric_thsens_otp_config_o4;
-    output fabric_thsens_otp_config_o5;
-    output fabric_thsens_otp_config_o6;
-    output fabric_thsens_otp_config_o7;
-    output fabric_thsens_otp_config_o8;
-    output fabric_thsens_otp_config_o9;
-    input fabric_user_clk_i;
-    input fabric_user_data_i1;
-    input fabric_user_data_i10;
-    input fabric_user_data_i11;
-    input fabric_user_data_i12;
-    input fabric_user_data_i13;
-    input fabric_user_data_i14;
-    input fabric_user_data_i15;
-    input fabric_user_data_i16;
-    input fabric_user_data_i17;
-    input fabric_user_data_i18;
-    input fabric_user_data_i19;
-    input fabric_user_data_i2;
-    input fabric_user_data_i20;
-    input fabric_user_data_i21;
-    input fabric_user_data_i22;
-    input fabric_user_data_i23;
-    input fabric_user_data_i24;
-    input fabric_user_data_i25;
-    input fabric_user_data_i26;
-    input fabric_user_data_i27;
-    input fabric_user_data_i28;
-    input fabric_user_data_i29;
-    input fabric_user_data_i3;
-    input fabric_user_data_i30;
-    input fabric_user_data_i31;
-    input fabric_user_data_i32;
-    input fabric_user_data_i4;
-    input fabric_user_data_i5;
-    input fabric_user_data_i6;
-    input fabric_user_data_i7;
-    input fabric_user_data_i8;
-    input fabric_user_data_i9;
-    output fabric_user_data_o1;
-    output fabric_user_data_o10;
-    output fabric_user_data_o11;
-    output fabric_user_data_o12;
-    output fabric_user_data_o13;
-    output fabric_user_data_o14;
-    output fabric_user_data_o15;
-    output fabric_user_data_o16;
-    output fabric_user_data_o17;
-    output fabric_user_data_o18;
-    output fabric_user_data_o19;
-    output fabric_user_data_o2;
-    output fabric_user_data_o20;
-    output fabric_user_data_o21;
-    output fabric_user_data_o22;
-    output fabric_user_data_o23;
-    output fabric_user_data_o24;
-    output fabric_user_data_o25;
-    output fabric_user_data_o26;
-    output fabric_user_data_o27;
-    output fabric_user_data_o28;
-    output fabric_user_data_o29;
-    output fabric_user_data_o3;
-    output fabric_user_data_o30;
-    output fabric_user_data_o31;
-    output fabric_user_data_o32;
-    output fabric_user_data_o4;
-    output fabric_user_data_o5;
-    output fabric_user_data_o6;
-    output fabric_user_data_o7;
-    output fabric_user_data_o8;
-    output fabric_user_data_o9;
-    output fabric_user_read_cycle_o;
-    output fabric_user_write_cycle_o;
-    parameter bsm_config = 0;
-endmodule
-
-(* blackbox *)
-module NX_SERVICE_IF_U_FULL(fabric_mrepair_clk_i, fabric_clk_otp_mrepair_o, fabric_mrepair_cke_i, fabric_mrepair_por_i, fabric_mrepair_cke_force_i, fabric_mrepair_rst_n_i, fabric_mrepair_initn_i, fabric_mrepair_data_from_bist_i1, fabric_mrepair_data_from_bist_i2, fabric_mrepair_data_from_bist_i3, fabric_mrepair_data_from_bist_i4, fabric_mrepair_data_from_bist_i5, fabric_mrepair_data_from_bist_i6, fabric_mrepair_data_from_bist_i7, fabric_mrepair_data_from_bist_i8, fabric_mrepair_data_from_bist_i9, fabric_mrepair_data_from_bist_i10, fabric_mrepair_data_from_bist_i11, fabric_mrepair_data_from_bist_i12, fabric_mrepair_data_from_bist_i13, fabric_mrepair_data_from_bist_i14
-, fabric_mrepair_data_from_bist_i15, fabric_mrepair_data_from_bist_i16, fabric_mrepair_data_from_bist_i17, fabric_mrepair_data_from_bist_i18, fabric_mrepair_data_from_bist_i19, fabric_mrepair_data_from_bist_i20, fabric_mrepair_data_from_bist_i21, fabric_mrepair_data_from_bist_i22, fabric_mrepair_data_from_bist_i23, fabric_mrepair_data_from_bist_i24, fabric_mrepair_data_from_bist_i25, fabric_mrepair_data_from_bist_i26, fabric_mrepair_data_to_bist_o1, fabric_mrepair_data_to_bist_o2, fabric_mrepair_data_to_bist_o3, fabric_mrepair_data_to_bist_o4, fabric_mrepair_data_to_bist_o5, fabric_mrepair_data_to_bist_o6, fabric_mrepair_data_to_bist_o7, fabric_mrepair_data_to_bist_o8, fabric_mrepair_data_to_bist_o9
-, fabric_mrepair_data_to_bist_o10, fabric_mrepair_data_to_bist_o11, fabric_mrepair_data_to_bist_o12, fabric_mrepair_data_to_bist_o13, fabric_mrepair_data_to_bist_o14, fabric_mrepair_data_to_bist_o15, fabric_mrepair_data_to_bist_o16, fabric_mrepair_data_to_bist_o17, fabric_mrepair_data_to_bist_o18, fabric_mrepair_data_to_bist_o19, fabric_mrepair_data_to_bist_o20, fabric_mrepair_data_to_bist_o21, fabric_mrepair_data_to_bist_o22, fabric_mrepair_data_to_bist_o23, fabric_mrepair_data_to_bist_o24, fabric_mrepair_data_to_bist_o25, fabric_mrepair_data_to_bist_o26, fabric_mrepair_shift_en_to_bist_o1, fabric_mrepair_shift_en_to_bist_o2, fabric_mrepair_shift_en_to_bist_o3, fabric_mrepair_shift_en_to_bist_o4
-, fabric_mrepair_shift_en_to_bist_o5, fabric_mrepair_shift_en_to_bist_o6, fabric_mrepair_shift_en_to_bist_o7, fabric_mrepair_shift_en_to_bist_o8, fabric_mrepair_shift_en_to_bist_o9, fabric_mrepair_shift_en_to_bist_o10, fabric_mrepair_shift_en_to_bist_o11, fabric_mrepair_shift_en_to_bist_o12, fabric_mrepair_shift_en_to_bist_o13, fabric_mrepair_shift_en_to_bist_o14, fabric_mrepair_shift_en_to_bist_o15, fabric_mrepair_shift_en_to_bist_o16, fabric_mrepair_shift_en_to_bist_o17, fabric_mrepair_shift_en_to_bist_o18, fabric_mrepair_shift_en_to_bist_o19, fabric_mrepair_shift_en_to_bist_o20, fabric_mrepair_shift_en_to_bist_o21, fabric_mrepair_shift_en_to_bist_o22, fabric_mrepair_shift_en_to_bist_o23, fabric_mrepair_shift_en_to_bist_o24, fabric_mrepair_shift_en_to_bist_o25
-, fabric_mrepair_shift_en_to_bist_o26, fabric_mrepair_sif_load_en_to_bist_o1, fabric_mrepair_sif_load_en_to_bist_o2, fabric_mrepair_sif_load_en_to_bist_o3, fabric_mrepair_sif_load_en_to_bist_o4, fabric_mrepair_sif_load_en_to_bist_o5, fabric_mrepair_sif_load_en_to_bist_o6, fabric_mrepair_sif_load_en_to_bist_o7, fabric_mrepair_sif_load_en_to_bist_o8, fabric_mrepair_sif_load_en_to_bist_o9, fabric_mrepair_sif_load_en_to_bist_o10, fabric_mrepair_sif_load_en_to_bist_o11, fabric_mrepair_sif_load_en_to_bist_o12, fabric_mrepair_sif_load_en_to_bist_o13, fabric_mrepair_sif_load_en_to_bist_o14, fabric_mrepair_sif_load_en_to_bist_o15, fabric_mrepair_sif_load_en_to_bist_o16, fabric_mrepair_sif_load_en_to_bist_o17, fabric_mrepair_sif_load_en_to_bist_o18, fabric_mrepair_sif_load_en_to_bist_o19, fabric_mrepair_sif_load_en_to_bist_o20
-, fabric_mrepair_sif_load_en_to_bist_o21, fabric_mrepair_sif_load_en_to_bist_o22, fabric_mrepair_sif_load_en_to_bist_o23, fabric_mrepair_sif_load_en_to_bist_o24, fabric_mrepair_sif_load_en_to_bist_o25, fabric_mrepair_sif_load_en_to_bist_o26, fabric_mrepair_sif_update_en_to_bist_o1, fabric_mrepair_sif_update_en_to_bist_o2, fabric_mrepair_sif_update_en_to_bist_o3, fabric_mrepair_sif_update_en_to_bist_o4, fabric_mrepair_sif_update_en_to_bist_o5, fabric_mrepair_sif_update_en_to_bist_o6, fabric_mrepair_sif_update_en_to_bist_o7, fabric_mrepair_sif_update_en_to_bist_o8, fabric_mrepair_sif_update_en_to_bist_o9, fabric_mrepair_sif_update_en_to_bist_o10, fabric_mrepair_sif_update_en_to_bist_o11, fabric_mrepair_sif_update_en_to_bist_o12, fabric_mrepair_sif_update_en_to_bist_o13, fabric_mrepair_sif_update_en_to_bist_o14, fabric_mrepair_sif_update_en_to_bist_o15
-, fabric_mrepair_sif_update_en_to_bist_o16, fabric_mrepair_sif_update_en_to_bist_o17, fabric_mrepair_sif_update_en_to_bist_o18, fabric_mrepair_sif_update_en_to_bist_o19, fabric_mrepair_sif_update_en_to_bist_o20, fabric_mrepair_sif_update_en_to_bist_o21, fabric_mrepair_sif_update_en_to_bist_o22, fabric_mrepair_sif_update_en_to_bist_o23, fabric_mrepair_sif_update_en_to_bist_o24, fabric_mrepair_sif_update_en_to_bist_o25, fabric_mrepair_sif_update_en_to_bist_o26, fabric_mrepair_sif_reg_en_to_bist_o1, fabric_mrepair_sif_reg_en_to_bist_o2, fabric_mrepair_sif_reg_en_to_bist_o3, fabric_mrepair_sif_reg_en_to_bist_o4, fabric_mrepair_sif_reg_en_to_bist_o5, fabric_mrepair_sif_reg_en_to_bist_o6, fabric_mrepair_sif_reg_en_to_bist_o7, fabric_mrepair_sif_reg_en_to_bist_o8, fabric_mrepair_sif_reg_en_to_bist_o9, fabric_mrepair_sif_reg_en_to_bist_o10
-, fabric_mrepair_sif_reg_en_to_bist_o11, fabric_mrepair_sif_reg_en_to_bist_o12, fabric_mrepair_sif_reg_en_to_bist_o13, fabric_mrepair_sif_reg_en_to_bist_o14, fabric_mrepair_sif_reg_en_to_bist_o15, fabric_mrepair_sif_reg_en_to_bist_o16, fabric_mrepair_sif_reg_en_to_bist_o17, fabric_mrepair_sif_reg_en_to_bist_o18, fabric_mrepair_sif_reg_en_to_bist_o19, fabric_mrepair_sif_reg_en_to_bist_o20, fabric_mrepair_sif_reg_en_to_bist_o21, fabric_mrepair_sif_reg_en_to_bist_o22, fabric_mrepair_sif_reg_en_to_bist_o23, fabric_mrepair_sif_reg_en_to_bist_o24, fabric_mrepair_sif_reg_en_to_bist_o25, fabric_mrepair_sif_reg_en_to_bist_o26, fabric_mrepair_system_data_to_mem_bist_i1, fabric_mrepair_system_data_to_mem_bist_i2, fabric_mrepair_system_data_to_mem_bist_i3, fabric_mrepair_system_data_to_mem_bist_i4, fabric_mrepair_system_data_to_mem_bist_i5
-, fabric_mrepair_system_data_to_mem_bist_i6, fabric_mrepair_system_data_to_mem_bist_i7, fabric_mrepair_system_data_to_mem_bist_i8, fabric_mrepair_system_data_to_mem_bist_i9, fabric_mrepair_system_data_to_mem_bist_i10, fabric_mrepair_system_data_to_mem_bist_i11, fabric_mrepair_system_data_to_mem_bist_i12, fabric_mrepair_system_data_to_mem_bist_i13, fabric_mrepair_system_data_to_mem_bist_i14, fabric_mrepair_system_data_to_mem_bist_i15, fabric_mrepair_system_data_to_mem_bist_i16, fabric_mrepair_system_data_to_mem_bist_i17, fabric_mrepair_system_data_to_mem_bist_i18, fabric_mrepair_system_data_to_mem_bist_i19, fabric_mrepair_system_data_to_mem_bist_i20, fabric_mrepair_system_data_to_mem_bist_i21, fabric_mrepair_system_data_to_mem_bist_i22, fabric_mrepair_system_data_to_mem_bist_i23, fabric_mrepair_system_data_to_mem_bist_i24, fabric_mrepair_system_data_to_mem_bist_i25, fabric_mrepair_system_data_to_mem_bist_i26
-, fabric_mrepair_shift_en_i1, fabric_mrepair_shift_en_i2, fabric_mrepair_shift_en_i3, fabric_mrepair_shift_en_i4, fabric_mrepair_shift_en_i5, fabric_mrepair_shift_en_i6, fabric_mrepair_shift_en_i7, fabric_mrepair_shift_en_i8, fabric_mrepair_shift_en_i9, fabric_mrepair_shift_en_i10, fabric_mrepair_shift_en_i11, fabric_mrepair_shift_en_i12, fabric_mrepair_shift_en_i13, fabric_mrepair_shift_en_i14, fabric_mrepair_shift_en_i15, fabric_mrepair_shift_en_i16, fabric_mrepair_shift_en_i17, fabric_mrepair_shift_en_i18, fabric_mrepair_shift_en_i19, fabric_mrepair_shift_en_i20, fabric_mrepair_shift_en_i21
-, fabric_mrepair_shift_en_i22, fabric_mrepair_shift_en_i23, fabric_mrepair_shift_en_i24, fabric_mrepair_shift_en_i25, fabric_mrepair_shift_en_i26, fabric_mrepair_sif_load_en_i1, fabric_mrepair_sif_load_en_i2, fabric_mrepair_sif_load_en_i3, fabric_mrepair_sif_load_en_i4, fabric_mrepair_sif_load_en_i5, fabric_mrepair_sif_load_en_i6, fabric_mrepair_sif_load_en_i7, fabric_mrepair_sif_load_en_i8, fabric_mrepair_sif_load_en_i9, fabric_mrepair_sif_load_en_i10, fabric_mrepair_sif_load_en_i11, fabric_mrepair_sif_load_en_i12, fabric_mrepair_sif_load_en_i13, fabric_mrepair_sif_load_en_i14, fabric_mrepair_sif_load_en_i15, fabric_mrepair_sif_load_en_i16
-, fabric_mrepair_sif_load_en_i17, fabric_mrepair_sif_load_en_i18, fabric_mrepair_sif_load_en_i19, fabric_mrepair_sif_load_en_i20, fabric_mrepair_sif_load_en_i21, fabric_mrepair_sif_load_en_i22, fabric_mrepair_sif_load_en_i23, fabric_mrepair_sif_load_en_i24, fabric_mrepair_sif_load_en_i25, fabric_mrepair_sif_load_en_i26, fabric_mrepair_sif_update_en_i1, fabric_mrepair_sif_update_en_i2, fabric_mrepair_sif_update_en_i3, fabric_mrepair_sif_update_en_i4, fabric_mrepair_sif_update_en_i5, fabric_mrepair_sif_update_en_i6, fabric_mrepair_sif_update_en_i7, fabric_mrepair_sif_update_en_i8, fabric_mrepair_sif_update_en_i9, fabric_mrepair_sif_update_en_i10, fabric_mrepair_sif_update_en_i11
-, fabric_mrepair_sif_update_en_i12, fabric_mrepair_sif_update_en_i13, fabric_mrepair_sif_update_en_i14, fabric_mrepair_sif_update_en_i15, fabric_mrepair_sif_update_en_i16, fabric_mrepair_sif_update_en_i17, fabric_mrepair_sif_update_en_i18, fabric_mrepair_sif_update_en_i19, fabric_mrepair_sif_update_en_i20, fabric_mrepair_sif_update_en_i21, fabric_mrepair_sif_update_en_i22, fabric_mrepair_sif_update_en_i23, fabric_mrepair_sif_update_en_i24, fabric_mrepair_sif_update_en_i25, fabric_mrepair_sif_update_en_i26, fabric_mrepair_sif_reg_en_i1, fabric_mrepair_sif_reg_en_i2, fabric_mrepair_sif_reg_en_i3, fabric_mrepair_sif_reg_en_i4, fabric_mrepair_sif_reg_en_i5, fabric_mrepair_sif_reg_en_i6
-, fabric_mrepair_sif_reg_en_i7, fabric_mrepair_sif_reg_en_i8, fabric_mrepair_sif_reg_en_i9, fabric_mrepair_sif_reg_en_i10, fabric_mrepair_sif_reg_en_i11, fabric_mrepair_sif_reg_en_i12, fabric_mrepair_sif_reg_en_i13, fabric_mrepair_sif_reg_en_i14, fabric_mrepair_sif_reg_en_i15, fabric_mrepair_sif_reg_en_i16, fabric_mrepair_sif_reg_en_i17, fabric_mrepair_sif_reg_en_i18, fabric_mrepair_sif_reg_en_i19, fabric_mrepair_sif_reg_en_i20, fabric_mrepair_sif_reg_en_i21, fabric_mrepair_sif_reg_en_i22, fabric_mrepair_sif_reg_en_i23, fabric_mrepair_sif_reg_en_i24, fabric_mrepair_sif_reg_en_i25, fabric_mrepair_sif_reg_en_i26, fabric_mrepair_system_data_from_mem_bist_o1
-, fabric_mrepair_system_data_from_mem_bist_o2, fabric_mrepair_system_data_from_mem_bist_o3, fabric_mrepair_system_data_from_mem_bist_o4, fabric_mrepair_system_data_from_mem_bist_o5, fabric_mrepair_system_data_from_mem_bist_o6, fabric_mrepair_system_data_from_mem_bist_o7, fabric_mrepair_system_data_from_mem_bist_o8, fabric_mrepair_system_data_from_mem_bist_o9, fabric_mrepair_system_data_from_mem_bist_o10, fabric_mrepair_system_data_from_mem_bist_o11, fabric_mrepair_system_data_from_mem_bist_o12, fabric_mrepair_system_data_from_mem_bist_o13, fabric_mrepair_system_data_from_mem_bist_o14, fabric_mrepair_system_data_from_mem_bist_o15, fabric_mrepair_system_data_from_mem_bist_o16, fabric_mrepair_system_data_from_mem_bist_o17, fabric_mrepair_system_data_from_mem_bist_o18, fabric_mrepair_system_data_from_mem_bist_o19, fabric_mrepair_system_data_from_mem_bist_o20, fabric_mrepair_system_data_from_mem_bist_o21, fabric_mrepair_system_data_from_mem_bist_o22
-, fabric_mrepair_system_data_from_mem_bist_o23, fabric_mrepair_system_data_from_mem_bist_o24, fabric_mrepair_system_data_from_mem_bist_o25, fabric_mrepair_system_data_from_mem_bist_o26, fabric_mrepair_bist_mode_o, fabric_mrepair_mem_type_sel_o1, fabric_mrepair_mem_type_sel_o2, fabric_mrepair_mem_type_sel_o3, fabric_mrepair_mem_type_sel_o4, fabric_mrepair_mem_type_sel_o5, fabric_mrepair_mode_sel_o1, fabric_mrepair_mode_sel_o2, fabric_mrepair_mode_sel_o3, fabric_mrepair_mode_sel_o4, fabric_mrepair_bend_i, fabric_mrepair_global_bbad_i, fabric_mrepair_global_repairable_i, fabric_mrepair_bypass_o, fabric_mrepair_memsafe_o, fabric_mrepair_mem_atpg_mode_o, fabric_mrepair_tst_gatedclock_o
-, fabric_mrepair_test_se_o, fabric_mrepair_data_to_system_o, fabric_mrepair_tst_atpg_mrepair_i, fabric_mrepair_data_from_system_i, fabric_mrepair_end_encoding_i, fabric_mrepair_mode_i1, fabric_mrepair_mode_i2, fabric_mrepair_mode_i3, fabric_mrepair_mode_i4, fabric_mrepair_pd_active_i1, fabric_mrepair_pd_active_i2, fabric_mrepair_pd_active_i3, fabric_mrepair_pd_active_i4, fabric_mrepair_pd_active_i5, fabric_mrepair_pd_active_i6, fabric_mrepair_pd_active_i7, fabric_mrepair_pd_active_i8, fabric_mrepair_pd_active_i9, fabric_mrepair_pd_active_i10, fabric_mrepair_pd_active_i11, fabric_mrepair_pd_active_i12
-, fabric_mrepair_pd_active_i13, fabric_mrepair_pd_active_i14, fabric_mrepair_pd_active_i15, fabric_mrepair_pd_active_i16, fabric_mrepair_pd_active_i17, fabric_mrepair_pd_active_i18, fabric_mrepair_pd_active_i19, fabric_mrepair_pd_active_i20, fabric_mrepair_pd_active_i21, fabric_mrepair_pd_active_i22, fabric_mrepair_pd_active_i23, fabric_mrepair_pd_active_i24, fabric_mrepair_pd_active_i25, fabric_mrepair_pd_active_i26, fabric_mrepair_chip_status_o1, fabric_mrepair_chip_status_o2, fabric_mrepair_chip_status_o3, fabric_mrepair_chip_status_o4, fabric_mrepair_chip_status_o5, fabric_mrepair_chip_status_o6, fabric_mrepair_chip_status_o7
-, fabric_mrepair_chip_status_o8, fabric_mrepair_chip_status_o9, fabric_mrepair_chip_status_o10, fabric_mrepair_chip_status_o11, fabric_mrepair_chip_status_o12, fabric_mrepair_chip_status_o13, fabric_mrepair_chip_status_o14, fabric_mrepair_chip_status_o15, fabric_mrepair_chip_status_o16, fabric_mrepair_chip_status_o17, fabric_mrepair_chip_status_o18, fabric_mrepair_chip_status_o19, fabric_mrepair_chip_status_o20, fabric_mrepair_chip_status_o21, fabric_mrepair_chip_status_o22, fabric_mrepair_chip_status_o23, fabric_mrepair_chip_status_o24, fabric_mrepair_chip_status_o25, fabric_mrepair_chip_status_o26, fabric_mrepair_chip_status_o27, fabric_mrepair_chip_status_o28
-, fabric_mrepair_chip_status_o29, fabric_mrepair_chip_status_o30, fabric_mrepair_chip_status_o31, fabric_mrepair_chip_status_o32, fabric_mrepair_chip_status_o33, fabric_mrepair_chip_status_o34, fabric_mrepair_chip_status_o35, fabric_mrepair_chip_status_o36, fabric_mrepair_chip_status_o37, fabric_mrepair_chip_status_o38, fabric_mrepair_chip_status_o39, fabric_mrepair_chip_status_o40, fabric_mrepair_chip_status_o41, fabric_mrepair_chip_status_o42, fabric_mrepair_chip_status_o43, fabric_mrepair_chip_status_o44, fabric_mrepair_chip_status_o45, fabric_mrepair_chip_status_o46, fabric_mrepair_chip_status_o47, fabric_mrepair_chip_status_o48, fabric_mrepair_chip_status_o49
-, fabric_mrepair_chip_status_o50, fabric_mrepair_chip_status_o51, fabric_mrepair_chip_status_o52, fabric_mrepair_chip_status_o53, fabric_mrepair_chip_status_o54, fabric_mrepair_chip_status_o55, fabric_mrepair_chip_status_o56, fabric_mrepair_chip_status_o57, fabric_mrepair_chip_status_o58, fabric_mrepair_chip_status_o59, fabric_mrepair_chip_status_o60, fabric_mrepair_chip_status_o61, fabric_mrepair_chip_status_o62, fabric_mrepair_chip_status_o63, fabric_mrepair_chip_status_o64, fabric_mrepair_chip_status_o65, fabric_mrepair_chip_status_o66, fabric_mrepair_chip_status_o67, fabric_mrepair_chip_status_o68, fabric_mrepair_chip_status_o69, fabric_mrepair_chip_status_o70
-, fabric_mrepair_chip_status_o71, fabric_mrepair_chip_status_o72, fabric_mrepair_chip_status_o73, fabric_mrepair_chip_status_o74, fabric_mrepair_chip_status_o75, fabric_mrepair_chip_status_o76, fabric_mrepair_chip_status_o77, fabric_mrepair_chip_status_o78, fabric_mrepair_global_chip_status_o1, fabric_mrepair_global_chip_status_o2, fabric_mrepair_global_chip_status_o3, fabric_mrepair_pd_ready_o1, fabric_mrepair_pd_ready_o2, fabric_mrepair_pd_ready_o3, fabric_mrepair_pd_ready_o4, fabric_mrepair_pd_ready_o5, fabric_mrepair_pd_ready_o6, fabric_mrepair_pd_ready_o7, fabric_mrepair_pd_ready_o8, fabric_mrepair_pd_ready_o9, fabric_mrepair_pd_ready_o10
-, fabric_mrepair_pd_ready_o11, fabric_mrepair_pd_ready_o12, fabric_mrepair_pd_ready_o13, fabric_mrepair_pd_ready_o14, fabric_mrepair_pd_ready_o15, fabric_mrepair_pd_ready_o16, fabric_mrepair_pd_ready_o17, fabric_mrepair_pd_ready_o18, fabric_mrepair_pd_ready_o19, fabric_mrepair_pd_ready_o20, fabric_mrepair_pd_ready_o21, fabric_mrepair_pd_ready_o22, fabric_mrepair_pd_ready_o23, fabric_mrepair_pd_ready_o24, fabric_mrepair_pd_ready_o25, fabric_mrepair_pd_ready_o26, fabric_mrepair_system_dataready_o, fabric_mrepair_decoder_init_ready_o, fabric_mrepair_fuse_pdn_i, fabric_mrepair_fuse_bistmode_i, fabric_mrepair_fuse_tm_i
-, fabric_mrepair_fuse_add_i1, fabric_mrepair_fuse_add_i2, fabric_mrepair_fuse_add_i3, fabric_mrepair_fuse_add_i4, fabric_mrepair_fuse_add_i5, fabric_mrepair_fuse_add_i6, fabric_mrepair_fuse_add_i7, fabric_mrepair_fuse_din_i1, fabric_mrepair_fuse_din_i2, fabric_mrepair_fuse_din_i3, fabric_mrepair_fuse_din_i4, fabric_mrepair_fuse_din_i5, fabric_mrepair_fuse_din_i6, fabric_mrepair_fuse_din_i7, fabric_mrepair_fuse_din_i8, fabric_mrepair_fuse_din_i9, fabric_mrepair_fuse_din_i10, fabric_mrepair_fuse_din_i11, fabric_mrepair_fuse_din_i12, fabric_mrepair_fuse_din_i13, fabric_mrepair_fuse_din_i14
-, fabric_mrepair_fuse_din_i15, fabric_mrepair_fuse_din_i16, fabric_mrepair_fuse_din_i17, fabric_mrepair_fuse_din_i18, fabric_mrepair_fuse_din_i19, fabric_mrepair_fuse_din_i20, fabric_mrepair_fuse_din_i21, fabric_mrepair_fuse_din_i22, fabric_mrepair_fuse_din_i23, fabric_mrepair_fuse_din_i24, fabric_mrepair_fuse_din_i25, fabric_mrepair_fuse_din_i26, fabric_mrepair_fuse_din_i27, fabric_mrepair_fuse_din_i28, fabric_mrepair_fuse_din_i29, fabric_mrepair_fuse_din_i30, fabric_mrepair_fuse_din_i31, fabric_mrepair_fuse_din_i32, fabric_mrepair_fuse_din_i33, fabric_mrepair_fuse_din_i34, fabric_mrepair_fuse_din_i35
-, fabric_mrepair_fuse_din_i36, fabric_mrepair_fuse_din_i37, fabric_mrepair_fuse_din_i38, fabric_mrepair_fuse_din_i39, fabric_mrepair_fuse_read_i, fabric_mrepair_fuse_prog_i, fabric_mrepair_fuse_rbact1_i, fabric_mrepair_fuse_rbact2_i, fabric_mrepair_fuse_tstscanenable_i, fabric_mrepair_fuse_tst_scanin_i1, fabric_mrepair_fuse_tst_scanin_i2, fabric_mrepair_fuse_tst_scanin_i3, fabric_mrepair_fuse_tst_scanin_i4, fabric_mrepair_fuse_tst_scanin_i5, fabric_mrepair_fuse_eccbypass_i, fabric_mrepair_fuse_wordlock_i, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_redbypass_i, fabric_mrepair_fuse_disturbchecked_i, fabric_mrepair_fuse_prgwidth_i1, fabric_mrepair_fuse_prgwidth_i2
-, fabric_mrepair_fuse_prgwidth_i3, fabric_mrepair_data_shift_en_i, fabric_mrepair_fuse_pwok_o, fabric_mrepair_fuse_dout_o1, fabric_mrepair_fuse_dout_o2, fabric_mrepair_fuse_dout_o3, fabric_mrepair_fuse_dout_o4, fabric_mrepair_fuse_dout_o5, fabric_mrepair_fuse_dout_o6, fabric_mrepair_fuse_dout_o7, fabric_mrepair_fuse_dout_o8, fabric_mrepair_fuse_dout_o9, fabric_mrepair_fuse_dout_o10, fabric_mrepair_fuse_dout_o11, fabric_mrepair_fuse_dout_o12, fabric_mrepair_fuse_dout_o13, fabric_mrepair_fuse_dout_o14, fabric_mrepair_fuse_dout_o15, fabric_mrepair_fuse_dout_o16, fabric_mrepair_fuse_dout_o17, fabric_mrepair_fuse_dout_o18
-, fabric_mrepair_fuse_dout_o19, fabric_mrepair_fuse_dout_o20, fabric_mrepair_fuse_dout_o21, fabric_mrepair_fuse_dout_o22, fabric_mrepair_fuse_dout_o23, fabric_mrepair_fuse_dout_o24, fabric_mrepair_fuse_dout_o25, fabric_mrepair_fuse_dout_o26, fabric_mrepair_fuse_dout_o27, fabric_mrepair_fuse_dout_o28, fabric_mrepair_fuse_dout_o29, fabric_mrepair_fuse_dout_o30, fabric_mrepair_fuse_dout_o31, fabric_mrepair_fuse_dout_o32, fabric_mrepair_fuse_dout_o33, fabric_mrepair_fuse_dout_o34, fabric_mrepair_fuse_dout_o35, fabric_mrepair_fuse_dout_o36, fabric_mrepair_fuse_dout_o37, fabric_mrepair_fuse_dout_o38, fabric_mrepair_fuse_dout_o39
-, fabric_mrepair_fuse_dout_o40, fabric_mrepair_fuse_dout_o41, fabric_mrepair_fuse_startword_o1, fabric_mrepair_fuse_startword_o2, fabric_mrepair_fuse_startword_o3, fabric_mrepair_fuse_startword_o4, fabric_mrepair_fuse_startword_o5, fabric_mrepair_fuse_startword_o6, fabric_mrepair_fuse_startword_o7, fabric_mrepair_fuse_startword_o8, fabric_mrepair_fuse_startword_o9, fabric_mrepair_fuse_startword_o10, fabric_mrepair_fuse_startword_o11, fabric_mrepair_fuse_startword_o12, fabric_mrepair_fuse_startword_o13, fabric_mrepair_fuse_startword_o14, fabric_mrepair_fuse_startword_o15, fabric_mrepair_fuse_startword_o16, fabric_mrepair_fuse_ack_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_ded_o
-, fabric_mrepair_fuse_progfail_o, fabric_mrepair_fuse_locked_o, fabric_mrepair_fuse_disturbed_o, fabric_mrepair_fuse_wlromout_o1, fabric_mrepair_fuse_wlromout_o2, fabric_mrepair_fuse_wlromout_o3, fabric_mrepair_fuse_wlromout_o4, fabric_mrepair_fuse_wlromout_o5, fabric_mrepair_fuse_wlromout_o6, fabric_mrepair_fuse_wlromout_o7, fabric_mrepair_fuse_wlromout_o8, fabric_mrepair_fuse_wlromout_o9, fabric_mrepair_fuse_wlromout_o10, fabric_mrepair_fuse_bist1fail_o1, fabric_mrepair_fuse_bist1fail_o2, fabric_mrepair_fuse_bist1fail_o3, fabric_mrepair_fuse_bist1fail_o4, fabric_mrepair_fuse_bist1fail_o5, fabric_mrepair_fuse_bist1fail_o6, fabric_mrepair_fuse_bist1fail_o7, fabric_mrepair_fuse_bist1fail_o8
-, fabric_mrepair_fuse_bist2fail_o1, fabric_mrepair_fuse_bist2fail_o2, fabric_mrepair_fuse_bist2fail_o3, fabric_mrepair_fuse_bist2fail_o4, fabric_mrepair_fuse_bist2fail_o5, fabric_mrepair_fuse_bist2fail_o6, fabric_mrepair_fuse_bist2fail_o7, fabric_mrepair_fuse_bend1_o, fabric_mrepair_fuse_bend2_o, fabric_mrepair_fuse_bbad_o, fabric_mrepair_fuse_tstscanout_o1, fabric_mrepair_fuse_tstscanout_o2, fabric_mrepair_fuse_tstscanout_o3, fabric_mrepair_fuse_tstscanout_o4, fabric_mrepair_fuse_tstscanout_o5, fabric_mrepair_fuse_flagstate_o1, fabric_mrepair_fuse_flagstate_o2, fabric_mrepair_fuse_flagstate_o3, fabric_mrepair_fuse_flagstate_o4, fabric_mrepair_fuse_calibrated_o, fabric_mrepair_fuse_ready_o
-, fabric_mrepair_fuse_status_o1, fabric_mrepair_fuse_status_o2, fabric_mrepair_fuse_status_o3, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_otp_user_clk_i, fabric_otp_user_bistmode_i, fabric_otp_user_disturbcheck_i, fabric_otp_user_eccbypass_i, fabric_otp_user_pdn_i, fabric_otp_user_prog_i, fabric_otp_user_rbact1_i, fabric_otp_user_rbact2_i, fabric_otp_user_read_i, fabric_otp_user_redbypass_i, fabric_otp_user_suppadd_i, fabric_otp_user_tm_i, fabric_otp_user_tst_scanenable_i, fabric_otp_user_wordlock_i, fabric_otp_user_add_i1, fabric_otp_user_add_i2, fabric_otp_user_add_i3
-, fabric_otp_user_add_i4, fabric_otp_user_add_i5, fabric_otp_user_add_i6, fabric_otp_user_add_i7, fabric_otp_user_clock_frequency_range_i, fabric_otp_user_din_i1, fabric_otp_user_din_i2, fabric_otp_user_din_i3, fabric_otp_user_din_i4, fabric_otp_user_din_i5, fabric_otp_user_din_i6, fabric_otp_user_din_i7, fabric_otp_user_din_i8, fabric_otp_user_din_i9, fabric_otp_user_din_i10, fabric_otp_user_din_i11, fabric_otp_user_din_i12, fabric_otp_user_din_i13, fabric_otp_user_din_i14, fabric_otp_user_din_i15, fabric_otp_user_din_i16
-, fabric_otp_user_din_i17, fabric_otp_user_din_i18, fabric_otp_user_din_i19, fabric_otp_user_din_i20, fabric_otp_user_din_i21, fabric_otp_user_din_i22, fabric_otp_user_din_i23, fabric_otp_user_din_i24, fabric_otp_user_din_i25, fabric_otp_user_din_i26, fabric_otp_user_din_i27, fabric_otp_user_din_i28, fabric_otp_user_din_i29, fabric_otp_user_din_i30, fabric_otp_user_din_i31, fabric_otp_user_din_i32, fabric_otp_user_din_i33, fabric_otp_user_din_i34, fabric_otp_user_din_i35, fabric_otp_user_din_i36, fabric_otp_user_din_i37
-, fabric_otp_user_din_i38, fabric_otp_user_din_i39, fabric_otp_user_prgwidth_i1, fabric_otp_user_prgwidth_i2, fabric_otp_user_prgwidth_i3, fabric_otp_user_tst_scanin_i1, fabric_otp_user_tst_scanin_i2, fabric_otp_user_tst_scanin_i3, fabric_otp_user_tst_scanin_i4, fabric_otp_user_tst_scanin_i5, fabric_otp_user_ack_o, fabric_otp_user_bbad_o, fabric_otp_user_bend1_o, fabric_otp_user_bend2_o, fabric_otp_user_calibrated_o, fabric_otp_user_ded_o, fabric_otp_user_disturbed_o, fabric_otp_user_locked_o, fabric_otp_user_progfail_o, fabric_otp_user_pwok_o, fabric_otp_user_sec_o
-, fabric_otp_user_bist1fail_o1, fabric_otp_user_bist1fail_o2, fabric_otp_user_bist1fail_o3, fabric_otp_user_bist1fail_o4, fabric_otp_user_bist1fail_o5, fabric_otp_user_bist1fail_o6, fabric_otp_user_bist1fail_o7, fabric_otp_user_bist1fail_o8, fabric_otp_user_bist2fail_o1, fabric_otp_user_bist2fail_o2, fabric_otp_user_bist2fail_o3, fabric_otp_user_bist2fail_o4, fabric_otp_user_bist2fail_o5, fabric_otp_user_bist2fail_o6, fabric_otp_user_bist2fail_o7, fabric_otp_user_dout_o1, fabric_otp_user_dout_o2, fabric_otp_user_dout_o3, fabric_otp_user_dout_o4, fabric_otp_user_dout_o5, fabric_otp_user_dout_o6
-, fabric_otp_user_dout_o7, fabric_otp_user_dout_o8, fabric_otp_user_dout_o9, fabric_otp_user_dout_o10, fabric_otp_user_dout_o11, fabric_otp_user_dout_o12, fabric_otp_user_dout_o13, fabric_otp_user_dout_o14, fabric_otp_user_dout_o15, fabric_otp_user_dout_o16, fabric_otp_user_dout_o17, fabric_otp_user_dout_o18, fabric_otp_user_dout_o19, fabric_otp_user_dout_o20, fabric_otp_user_dout_o21, fabric_otp_user_dout_o22, fabric_otp_user_dout_o23, fabric_otp_user_dout_o24, fabric_otp_user_dout_o25, fabric_otp_user_dout_o26, fabric_otp_user_dout_o27
-, fabric_otp_user_dout_o28, fabric_otp_user_dout_o29, fabric_otp_user_dout_o30, fabric_otp_user_dout_o31, fabric_otp_user_dout_o32, fabric_otp_user_dout_o33, fabric_otp_user_dout_o34, fabric_otp_user_dout_o35, fabric_otp_user_dout_o36, fabric_otp_user_dout_o37, fabric_otp_user_dout_o38, fabric_otp_user_dout_o39, fabric_otp_user_dout_o40, fabric_otp_user_dout_o41, fabric_otp_user_flagstate_o1, fabric_otp_user_flagstate_o2, fabric_otp_user_flagstate_o3, fabric_otp_user_flagstate_o4, fabric_otp_user_startword_o1, fabric_otp_user_startword_o2, fabric_otp_user_startword_o3
-, fabric_otp_user_startword_o4, fabric_otp_user_startword_o5, fabric_otp_user_startword_o6, fabric_otp_user_startword_o7, fabric_otp_user_startword_o8, fabric_otp_user_startword_o9, fabric_otp_user_startword_o10, fabric_otp_user_startword_o11, fabric_otp_user_startword_o12, fabric_otp_user_startword_o13, fabric_otp_user_startword_o14, fabric_otp_user_startword_o15, fabric_otp_user_startword_o16, fabric_otp_user_tst_scanout_o1, fabric_otp_user_tst_scanout_o2, fabric_otp_user_tst_scanout_o3, fabric_otp_user_tst_scanout_o4, fabric_otp_user_tst_scanout_o5, fabric_otp_user_wlromout_o1, fabric_otp_user_wlromout_o2, fabric_otp_user_wlromout_o3
-, fabric_otp_user_wlromout_o4, fabric_otp_user_wlromout_o5, fabric_otp_user_wlromout_o6, fabric_otp_user_wlromout_o7, fabric_otp_user_wlromout_o8, fabric_otp_user_wlromout_o9, fabric_otp_user_wlromout_o10, fabric_clk_bsm_o, fabric_clk_otp_mux_i, fabric_clk_otp_o, fabric_clk_user0_o, fabric_clk_user1_o, fabric_io_in_i1, fabric_io_in_i2, fabric_io_in_i3, fabric_io_in_i4, fabric_io_in_i5, fabric_io_in_i6, fabric_io_in_i7, fabric_io_in_i8, fabric_io_in_i9
-, fabric_io_in_i10, fabric_io_in_i11, fabric_io_in_i12, fabric_io_in_i13, fabric_io_in_i14, fabric_io_in_i15, fabric_io_in_i16, fabric_io_in_i17, fabric_io_in_i18, fabric_io_in_i19, fabric_io_in_i20, fabric_io_in_i21, fabric_io_in_i22, fabric_io_in_i23, fabric_io_in_i24, fabric_io_in_i25, fabric_io_in_i26, fabric_io_in_i27, fabric_io_in_i28, fabric_io_in_i29, fabric_io_in_i30
-, fabric_io_in_i31, fabric_io_in_i32, fabric_io_in_i33, fabric_io_in_i34, fabric_io_in_i35, fabric_io_oe_i1, fabric_io_oe_i2, fabric_io_oe_i3, fabric_io_oe_i4, fabric_io_oe_i5, fabric_io_oe_i6, fabric_io_oe_i7, fabric_io_oe_i8, fabric_io_oe_i9, fabric_io_oe_i10, fabric_io_oe_i11, fabric_io_oe_i12, fabric_io_oe_i13, fabric_io_oe_i14, fabric_io_oe_i15, fabric_io_oe_i16
-, fabric_io_oe_i17, fabric_io_oe_i18, fabric_io_oe_i19, fabric_io_oe_i20, fabric_io_oe_i21, fabric_io_oe_i22, fabric_io_oe_i23, fabric_io_oe_i24, fabric_io_oe_i25, fabric_io_oe_i26, fabric_io_oe_i27, fabric_io_oe_i28, fabric_io_oe_i29, fabric_io_oe_i30, fabric_io_oe_i31, fabric_io_oe_i32, fabric_io_oe_i33, fabric_io_oe_i34, fabric_io_oe_i35, fabric_io_out_o1, fabric_io_out_o2
-, fabric_io_out_o3, fabric_io_out_o4, fabric_io_out_o5, fabric_io_out_o6, fabric_io_out_o7, fabric_io_out_o8, fabric_io_out_o9, fabric_io_out_o10, fabric_io_out_o11, fabric_io_out_o12, fabric_io_out_o13, fabric_io_out_o14, fabric_io_out_o15, fabric_io_out_o16, fabric_io_out_o17, fabric_io_out_o18, fabric_io_out_o19, fabric_io_out_o20, fabric_io_out_o21, fabric_io_out_o22, fabric_io_out_o23
-, fabric_io_out_o24, fabric_io_out_o25, fabric_io_out_o26, fabric_io_out_o27, fabric_io_out_o28, fabric_io_out_o29, fabric_io_out_o30, fabric_io_out_o31, fabric_io_out_o32, fabric_io_out_o33, fabric_io_out_o34, fabric_io_out_o35, fabric_user_clk_i, fabric_user_data_i1, fabric_user_data_i2, fabric_user_data_i3, fabric_user_data_i4, fabric_user_data_i5, fabric_user_data_i6, fabric_user_data_i7, fabric_user_data_i8
-, fabric_user_data_i9, fabric_user_data_i10, fabric_user_data_i11, fabric_user_data_i12, fabric_user_data_i13, fabric_user_data_i14, fabric_user_data_i15, fabric_user_data_i16, fabric_user_data_i17, fabric_user_data_i18, fabric_user_data_i19, fabric_user_data_i20, fabric_user_data_i21, fabric_user_data_i22, fabric_user_data_i23, fabric_user_data_i24, fabric_user_data_i25, fabric_user_data_i26, fabric_user_data_i27, fabric_user_data_i28, fabric_user_data_i29
-, fabric_user_data_i30, fabric_user_data_i31, fabric_user_data_i32, fabric_user_data_o1, fabric_user_data_o2, fabric_user_data_o3, fabric_user_data_o4, fabric_user_data_o5, fabric_user_data_o6, fabric_user_data_o7, fabric_user_data_o8, fabric_user_data_o9, fabric_user_data_o10, fabric_user_data_o11, fabric_user_data_o12, fabric_user_data_o13, fabric_user_data_o14, fabric_user_data_o15, fabric_user_data_o16, fabric_user_data_o17, fabric_user_data_o18
-, fabric_user_data_o19, fabric_user_data_o20, fabric_user_data_o21, fabric_user_data_o22, fabric_user_data_o23, fabric_user_data_o24, fabric_user_data_o25, fabric_user_data_o26, fabric_user_data_o27, fabric_user_data_o28, fabric_user_data_o29, fabric_user_data_o30, fabric_user_data_o31, fabric_user_data_o32, fabric_user_write_cycle_o, fabric_user_read_cycle_o, fabric_cfg_fabric_user_flag_o, fabric_cfg_fabric_user_enable_o, fabric_parusr_clk_i, fabric_parusr_enable_i, fabric_parusr_cs_i
-, fabric_parusr_type_i1, fabric_parusr_type_i2, fabric_parusr_data_i1, fabric_parusr_data_i2, fabric_parusr_data_i3, fabric_parusr_data_i4, fabric_parusr_data_i5, fabric_parusr_data_i6, fabric_parusr_data_i7, fabric_parusr_data_i8, fabric_parusr_data_i9, fabric_parusr_data_i10, fabric_parusr_data_i11, fabric_parusr_data_i12, fabric_parusr_data_i13, fabric_parusr_data_i14, fabric_parusr_data_i15, fabric_parusr_data_i16, fabric_parusr_data_o1, fabric_parusr_data_o2, fabric_parusr_data_o3
-, fabric_parusr_data_o4, fabric_parusr_data_o5, fabric_parusr_data_o6, fabric_parusr_data_o7, fabric_parusr_data_o8, fabric_parusr_data_o9, fabric_parusr_data_o10, fabric_parusr_data_o11, fabric_parusr_data_o12, fabric_parusr_data_o13, fabric_parusr_data_o14, fabric_parusr_data_o15, fabric_parusr_data_o16, fabric_parusr_data_val_o, fabric_jtag_tck_o, fabric_jtag_trst_n_o, fabric_jtag_tms_o, fabric_jtag_tdi_o, fabric_jtag_usr1_o, fabric_jtag_usr2_o, fabric_jtag_tdo_usr1_i
-, fabric_jtag_tdo_usr2_i, fabric_direct_data_i1, fabric_direct_data_i2, fabric_direct_data_i3, fabric_direct_data_i4, fabric_direct_data_i5, fabric_direct_data_i6, fabric_direct_data_i7, fabric_direct_data_i8, fabric_direct_data_i9, fabric_direct_data_i10, fabric_direct_data_i11, fabric_direct_data_i12, fabric_direct_data_i13, fabric_direct_data_i14, fabric_direct_data_i15, fabric_direct_data_i16, fabric_direct_data_i17, fabric_direct_data_i18, fabric_direct_data_i19, fabric_direct_data_i20
-, fabric_direct_data_i21, fabric_direct_data_i22, fabric_direct_data_i23, fabric_direct_data_i24, fabric_direct_data_i25, fabric_direct_data_i26, fabric_direct_data_i27, fabric_direct_data_i28, fabric_direct_data_i29, fabric_direct_data_i30, fabric_direct_data_i31, fabric_direct_data_i32, fabric_direct_data_o1, fabric_direct_data_o2, fabric_direct_data_o3, fabric_direct_data_o4, fabric_direct_data_o5, fabric_direct_data_o6, fabric_direct_data_o7, fabric_direct_data_o8, fabric_direct_data_o9
-, fabric_direct_data_o10, fabric_direct_data_o11, fabric_direct_data_o12, fabric_direct_data_o13, fabric_direct_data_o14, fabric_direct_data_o15, fabric_direct_data_o16, fabric_direct_data_o17, fabric_direct_data_o18, fabric_direct_data_o19, fabric_direct_data_o20, fabric_direct_data_o21, fabric_direct_data_o22, fabric_direct_data_o23, fabric_direct_data_o24, fabric_direct_data_o25, fabric_direct_data_o26, fabric_direct_data_o27, fabric_direct_data_o28, fabric_direct_data_o29, fabric_direct_data_o30
-, fabric_direct_data_o31, fabric_direct_data_o32, fabric_otp_clk_i, fabric_otp_rst_i, fabric_otp_apb_addr_i1, fabric_otp_apb_addr_i2, fabric_otp_apb_addr_i3, fabric_otp_apb_addr_i4, fabric_otp_apb_addr_i5, fabric_otp_apb_addr_i6, fabric_otp_apb_addr_i7, fabric_otp_apb_addr_i8, fabric_otp_apb_addr_i9, fabric_otp_apb_addr_i10, fabric_otp_apb_addr_i11, fabric_otp_apb_addr_i12, fabric_otp_apb_addr_i13, fabric_otp_apb_addr_i14, fabric_otp_apb_addr_i15, fabric_otp_apb_addr_i16, fabric_otp_apb_addr_i17
-, fabric_otp_apb_addr_i18, fabric_otp_apb_addr_i19, fabric_otp_apb_addr_i20, fabric_otp_apb_addr_i21, fabric_otp_apb_addr_i22, fabric_otp_apb_addr_i23, fabric_otp_apb_addr_i24, fabric_otp_apb_addr_i25, fabric_otp_apb_addr_i26, fabric_otp_apb_addr_i27, fabric_otp_apb_addr_i28, fabric_otp_apb_addr_i29, fabric_otp_apb_addr_i30, fabric_otp_apb_addr_i31, fabric_otp_apb_addr_i32, fabric_otp_apb_write_i, fabric_otp_apb_sel_i, fabric_otp_apb_enable_i, fabric_otp_apb_wdata_i1, fabric_otp_apb_wdata_i2, fabric_otp_apb_wdata_i3
-, fabric_otp_apb_wdata_i4, fabric_otp_apb_wdata_i5, fabric_otp_apb_wdata_i6, fabric_otp_apb_wdata_i7, fabric_otp_apb_wdata_i8, fabric_otp_apb_wdata_i9, fabric_otp_apb_wdata_i10, fabric_otp_apb_wdata_i11, fabric_otp_apb_wdata_i12, fabric_otp_apb_wdata_i13, fabric_otp_apb_wdata_i14, fabric_otp_apb_wdata_i15, fabric_otp_apb_wdata_i16, fabric_otp_apb_wdata_i17, fabric_otp_apb_wdata_i18, fabric_otp_apb_wdata_i19, fabric_otp_apb_wdata_i20, fabric_otp_apb_wdata_i21, fabric_otp_apb_wdata_i22, fabric_otp_apb_wdata_i23, fabric_otp_apb_wdata_i24
-, fabric_otp_apb_wdata_i25, fabric_otp_apb_wdata_i26, fabric_otp_apb_wdata_i27, fabric_otp_apb_wdata_i28, fabric_otp_apb_wdata_i29, fabric_otp_apb_wdata_i30, fabric_otp_apb_wdata_i31, fabric_otp_apb_wdata_i32, fabric_otp_apb_ready_o, fabric_otp_apb_rdata_o1, fabric_otp_apb_rdata_o2, fabric_otp_apb_rdata_o3, fabric_otp_apb_rdata_o4, fabric_otp_apb_rdata_o5, fabric_otp_apb_rdata_o6, fabric_otp_apb_rdata_o7, fabric_otp_apb_rdata_o8, fabric_otp_apb_rdata_o9, fabric_otp_apb_rdata_o10, fabric_otp_apb_rdata_o11, fabric_otp_apb_rdata_o12
-, fabric_otp_apb_rdata_o13, fabric_otp_apb_rdata_o14, fabric_otp_apb_rdata_o15, fabric_otp_apb_rdata_o16, fabric_otp_apb_rdata_o17, fabric_otp_apb_rdata_o18, fabric_otp_apb_rdata_o19, fabric_otp_apb_rdata_o20, fabric_otp_apb_rdata_o21, fabric_otp_apb_rdata_o22, fabric_otp_apb_rdata_o23, fabric_otp_apb_rdata_o24, fabric_otp_apb_rdata_o25, fabric_otp_apb_rdata_o26, fabric_otp_apb_rdata_o27, fabric_otp_apb_rdata_o28, fabric_otp_apb_rdata_o29, fabric_otp_apb_rdata_o30, fabric_otp_apb_rdata_o31, fabric_otp_apb_rdata_o32, fabric_otp_cfg_fabric_apb_en_i
-, fabric_otp_cfg_loader_read_en_i, fabric_otp_cfg_loader_write_en_i, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_cfg_clk_fab_en_i, fabric_otp_security_ack_o, fabric_otp_security_rbact1_i, fabric_otp_security_rbact2_i, fabric_otp_security_bistmode_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_bist_end1_o, fabric_otp_security_bist_end2_o, fabric_otp_security_bist_bad_o, fabric_otp_security_bist_fail1_o1, fabric_otp_security_bist_fail1_o2, fabric_otp_security_bist_fail1_o3, fabric_otp_security_bist_fail1_o4, fabric_otp_security_bist_fail1_o5, fabric_otp_security_bist_fail1_o6, fabric_otp_security_bist_fail1_o7, fabric_otp_security_bist_fail2_o1, fabric_otp_security_bist_fail2_o2
-, fabric_otp_security_bist_fail2_o3, fabric_otp_security_bist_fail2_o4, fabric_otp_security_bist_fail2_o5, fabric_otp_security_bist_fail2_o6, fabric_otp_security_scanin_i1, fabric_otp_security_scanin_i2, fabric_otp_security_scanin_i3, fabric_otp_security_scanin_i4, fabric_otp_security_scanout_o1, fabric_otp_security_scanout_o2, fabric_otp_security_scanout_o3, fabric_otp_security_scanout_o4, fabric_otp_security_testmode_i, fabric_otp_security_scanenable_i, fabric_status_cold_start_o, fabric_flag_trigger0_o, fabric_flag_trigger1_o, fabric_flag_ready_TMR_o1, fabric_flag_ready_TMR_o2, fabric_flag_ready_TMR_o3, fabric_debug_lifecycle_o1
-, fabric_debug_lifecycle_o2, fabric_debug_lifecycle_o3, fabric_debug_lifecycle_o4, fabric_debug_fsm_state_o1, fabric_debug_fsm_state_o2, fabric_debug_fsm_state_o3, fabric_debug_rst_soft_o, fabric_debug_error_o, fabric_debug_otp_manager_read_otp_o, fabric_debug_otp_manager_read_done_o, fabric_debug_direct_permission_write_o1, fabric_debug_direct_permission_write_o2, fabric_debug_direct_permission_write_o3, fabric_debug_direct_permission_write_o4, fabric_debug_direct_permission_read_o1, fabric_debug_direct_permission_read_o2, fabric_debug_direct_permission_read_o3, fabric_debug_direct_permission_read_o4, fabric_debug_frame_use_encryption_o, fabric_debug_frame_permission_frame_o1, fabric_debug_frame_permission_frame_o2
-, fabric_debug_frame_permission_frame_o3, fabric_debug_frame_permission_frame_o4, fabric_debug_key_correct_o, fabric_debug_otpmgmt_state_o1, fabric_debug_otpmgmt_state_o2, fabric_debug_otpmgmt_state_o3, fabric_debug_otpapb_state_o1, fabric_debug_otpapb_state_o2, fabric_debug_otpapb_state_o3, fabric_debug_otpboot_state_o1, fabric_debug_otpboot_state_o2, fabric_debug_otpboot_state_o3, fabric_debug_otp_reload_err_o, fabric_debug_cpt_retry_o1, fabric_debug_cpt_retry_o2, fabric_debug_cpt_retry_o3, fabric_debug_cpt_retry_o4, fabric_debug_bsec_core_status_o1, fabric_debug_bsec_core_status_o2, fabric_debug_bsec_core_status_o3, fabric_debug_bsec_core_status_o4
-, fabric_debug_bsec_core_status_o5, fabric_debug_bsec_core_status_o6, fabric_debug_bsec_core_status_o7, fabric_debug_bsec_core_status_o8, fabric_debug_bsec_core_status_o9, fabric_debug_bsec_core_status_o10, fabric_debug_bsec_core_status_o11, fabric_debug_bsec_core_status_o12, fabric_debug_bsec_core_status_o13, fabric_debug_bsec_core_status_o14, fabric_debug_bsec_core_status_o15, fabric_debug_bsec_core_status_o16, fabric_debug_bsec_core_status_o17, fabric_debug_bsec_core_status_o18, fabric_debug_bsec_core_status_o19, fabric_debug_bsec_core_status_o20, fabric_debug_bsec_core_status_o21, fabric_debug_bsec_core_status_o22, fabric_debug_bsec_core_status_o23, fabric_debug_bsec_core_status_o24, fabric_debug_bsec_core_status_o25
-, fabric_debug_bsec_core_status_o26, fabric_debug_bsec_core_status_o27, fabric_debug_bsec_core_status_o28, fabric_debug_bsec_core_status_o29, fabric_debug_bsec_core_status_o30, fabric_debug_bsec_core_status_o31, fabric_debug_bsec_core_status_o32, fabric_debug_otpboot_curr_addr_o1, fabric_debug_otpboot_curr_addr_o2, fabric_debug_otpboot_curr_addr_o3, fabric_debug_otpboot_curr_addr_o4, fabric_debug_otpboot_curr_addr_o5, fabric_debug_otpboot_curr_addr_o6, fabric_debug_otpboot_curr_addr_o7, fabric_debug_otpboot_curr_addr_o8, fabric_debug_access_reg_data_ready_o, fabric_debug_security_error_read_o, fabric_debug_security_boot_done_o, fabric_debug_lock_reg_o, fabric_enable_TMR_i1, fabric_enable_TMR_i2
-, fabric_enable_TMR_i3, fabric_lowskew_i1, fabric_lowskew_i2, fabric_lowskew_i3, fabric_lowskew_i4, fabric_lowskew_i5, fabric_lowskew_i6, fabric_lowskew_i7, fabric_lowskew_i8, fabric_lowskew_i9, fabric_lowskew_i10, fabric_lowskew_i11, fabric_lowskew_i12, fabric_lowskew_i13, fabric_lowskew_i14, fabric_lowskew_i15, fabric_lowskew_i16, fabric_lowskew_i17, fabric_lowskew_i18, fabric_lowskew_i19, fabric_lowskew_i20
-, fabric_lowskew_i21, fabric_lowskew_i22, fabric_lowskew_i23, fabric_lowskew_i24, fabric_lowskew_i25, fabric_lowskew_i26, fabric_lowskew_i27, fabric_lowskew_i28, fabric_lowskew_i29, fabric_lowskew_i30, fabric_lowskew_i31, fabric_lowskew_i32, fabric_lowskew_i33, fabric_lowskew_i34, fabric_lowskew_i35, fabric_lowskew_i36, fabric_lowskew_i37, fabric_lowskew_i38, fabric_lowskew_i39, fabric_lowskew_i40, fabric_lowskew_o1
-, fabric_lowskew_o2, fabric_lowskew_o3, fabric_lowskew_o4, fabric_lowskew_o5, fabric_lowskew_o6, fabric_spare_i1, fabric_spare_i2, fabric_spare_i3, fabric_spare_i4, fabric_spare_i5, fabric_spare_i6, fabric_spare_i7, fabric_spare_i8, fabric_spare_i9, fabric_spare_i10, fabric_spare_i11, fabric_spare_i12, fabric_spare_i13, fabric_spare_i14, fabric_spare_i15, fabric_spare_i16
-, fabric_spare_i17, fabric_spare_i18, fabric_spare_i19, fabric_spare_i20, fabric_spare_i21, fabric_spare_i22, fabric_spare_i23, fabric_spare_i24, fabric_spare_i25, fabric_spare_i26, fabric_spare_i27, fabric_spare_i28, fabric_spare_i29, fabric_spare_i30, fabric_spare_i31, fabric_spare_i32, fabric_spare_i33, fabric_spare_i34, fabric_spare_i35, fabric_spare_i36, fabric_spare_i37
-, fabric_spare_i38, fabric_spare_i39, fabric_spare_i40, fabric_spare_i41, fabric_spare_i42, fabric_spare_i43, fabric_spare_i44, fabric_spare_i45, fabric_spare_i46, fabric_spare_i47, fabric_spare_i48, fabric_spare_i49, fabric_spare_i50, fabric_spare_i51, fabric_spare_i52, fabric_spare_i53, fabric_spare_i54, fabric_spare_i55, fabric_spare_i56, fabric_spare_i57, fabric_spare_i58
-, fabric_spare_i59, fabric_spare_i60, fabric_spare_i61, fabric_spare_i62, fabric_spare_i63, fabric_spare_i64, fabric_spare_i65, fabric_spare_i66, fabric_spare_i67, fabric_spare_i68, fabric_spare_i69, fabric_spare_i70, fabric_spare_i71, fabric_spare_i72, fabric_spare_i73, fabric_spare_i74, fabric_spare_i75, fabric_spare_i76, fabric_spare_i77, fabric_spare_i78, fabric_spare_i79
-, fabric_spare_i80, fabric_spare_i81, fabric_spare_i82, fabric_spare_i83, fabric_spare_i84, fabric_spare_i85, fabric_spare_i86, fabric_spare_i87, fabric_spare_i88, fabric_spare_i89, fabric_spare_i90, fabric_spare_i91, fabric_spare_i92, fabric_spare_i93, fabric_spare_i94, fabric_spare_i95, fabric_spare_i96, fabric_spare_i97, fabric_spare_i98, fabric_spare_i99, fabric_spare_i100
-, fabric_spare_i101, fabric_spare_i102, fabric_spare_i103, fabric_spare_i104, fabric_spare_i105, fabric_spare_i106, fabric_spare_i107, fabric_spare_i108, fabric_spare_i109, fabric_spare_i110, fabric_spare_i111, fabric_spare_i112, fabric_spare_i113, fabric_spare_i114, fabric_spare_i115, fabric_spare_i116, fabric_spare_i117, fabric_spare_i118, fabric_spare_i119, fabric_spare_i120, fabric_spare_i121
-, fabric_spare_i122, fabric_spare_i123, fabric_spare_i124, fabric_spare_i125, fabric_spare_i126, fabric_spare_i127, fabric_spare_i128, fabric_spare_o1, fabric_spare_o2, fabric_spare_o3, fabric_spare_o4, fabric_spare_o5, fabric_spare_o6, fabric_spare_o7, fabric_spare_o8, fabric_spare_o9, fabric_spare_o10, fabric_spare_o11, fabric_spare_o12, fabric_spare_o13, fabric_spare_o14
-, fabric_spare_o15, fabric_spare_o16, fabric_spare_o17, fabric_spare_o18, fabric_spare_o19, fabric_spare_o20, fabric_spare_o21, fabric_spare_o22, fabric_spare_o23, fabric_spare_o24, fabric_spare_o25, fabric_spare_o26, fabric_spare_o27, fabric_spare_o28, fabric_spare_o29, fabric_spare_o30, fabric_spare_o31, fabric_spare_o32, fabric_spare_o33, fabric_spare_o34, fabric_spare_o35
-, fabric_spare_o36, fabric_spare_o37, fabric_spare_o38, fabric_spare_o39, fabric_spare_o40, fabric_spare_o41, fabric_spare_o42, fabric_spare_o43, fabric_spare_o44, fabric_spare_o45, fabric_spare_o46, fabric_spare_o47, fabric_spare_o48, fabric_spare_o49, fabric_spare_o50, fabric_spare_o51, fabric_spare_o52, fabric_spare_o53, fabric_spare_o54, fabric_spare_o55, fabric_spare_o56
-, fabric_spare_o57, fabric_spare_o58, fabric_spare_o59, fabric_spare_o60, fabric_spare_o61, fabric_spare_o62, fabric_spare_o63, fabric_spare_o64, fabric_spare_o65, fabric_spare_o66, fabric_spare_o67, fabric_spare_o68, fabric_spare_o69, fabric_spare_o70, fabric_spare_o71, fabric_spare_o72, fabric_spare_o73, fabric_spare_o74, fabric_spare_o75, fabric_spare_o76, fabric_spare_o77
-, fabric_spare_o78, fabric_spare_o79, fabric_spare_o80, fabric_spare_o81, fabric_spare_o82, fabric_spare_o83, fabric_spare_o84, fabric_spare_o85, fabric_spare_o86, fabric_spare_o87, fabric_spare_o88, fabric_spare_o89, fabric_spare_o90, fabric_spare_o91, fabric_spare_o92, fabric_spare_o93, fabric_spare_o94, fabric_spare_o95, fabric_spare_o96, fabric_spare_o97, fabric_spare_o98
-, fabric_spare_o99, fabric_spare_o100, fabric_spare_o101, fabric_spare_o102, fabric_spare_o103, fabric_spare_o104, fabric_spare_o105, fabric_spare_o106, fabric_spare_o107, fabric_spare_o108, fabric_spare_o109, fabric_spare_o110, fabric_spare_o111, fabric_spare_o112, fabric_spare_o113, fabric_spare_o114, fabric_spare_o115, fabric_spare_o116, fabric_spare_o117, fabric_spare_o118, fabric_spare_o119
-, fabric_spare_o120, fabric_spare_o121, fabric_spare_o122, fabric_spare_o123, fabric_spare_o124, fabric_spare_o125, fabric_spare_o126, fabric_spare_o127, fabric_spare_o128, fabric_dac0_clk_i, fabric_dac0_clk_en_i, fabric_dac0_din_i1, fabric_dac0_din_i2, fabric_dac0_din_i3, fabric_dac0_din_i4, fabric_dac0_din_i5, fabric_dac0_din_i6, fabric_dac0_din_i7, fabric_dac0_din_i8, fabric_dac0_din_i9, fabric_dac0_din_i10
-, fabric_dac0_din_i11, fabric_dac0_din_i12, fabric_dac0_din_i13, fabric_dac0_reg_pwr_down_n_i, fabric_dac0_rstn_i, fabric_dac0_op_en_i, fabric_dac0_filt_en_i, fabric_dac0_comp_en_i, fabric_dac0_comp_ref_sel_i, fabric_dac0_comp_hyst_en_i, fabric_dac0_comp_in_sel_i1, fabric_dac0_comp_in_sel_i2, fabric_dac0_comp_in_sel_i3, fabric_dac0_comp_in_sel_i4, fabric_dac0_comp_out_o, fabric_cfg_dac0_reg_res_i1, fabric_cfg_dac0_reg_res_i2, fabric_cfg_dac0_reg_vref_select_i, fabric_cfg_dac0_reg_cm_select_i, fabric_cfg_dac0_sync_i, fabric_dac1_clk_i
-, fabric_dac1_clk_en_i, fabric_dac1_din_i1, fabric_dac1_din_i2, fabric_dac1_din_i3, fabric_dac1_din_i4, fabric_dac1_din_i5, fabric_dac1_din_i6, fabric_dac1_din_i7, fabric_dac1_din_i8, fabric_dac1_din_i9, fabric_dac1_din_i10, fabric_dac1_din_i11, fabric_dac1_din_i12, fabric_dac1_din_i13, fabric_dac1_reg_pwr_down_n_i, fabric_dac1_rstn_i, fabric_dac1_op_en_i, fabric_dac1_filt_en_i, fabric_dac1_comp_en_i, fabric_dac1_comp_ref_sel_i, fabric_dac1_comp_hyst_en_i
-, fabric_dac1_comp_in_sel_i1, fabric_dac1_comp_in_sel_i2, fabric_dac1_comp_in_sel_i3, fabric_dac1_comp_in_sel_i4, fabric_dac1_comp_out_o, fabric_cfg_dac1_reg_res_i1, fabric_cfg_dac1_reg_res_i2, fabric_cfg_dac1_reg_vref_select_i, fabric_cfg_dac1_reg_cm_select_i, fabric_cfg_dac1_sync_i, fabric_dac2_clk_i, fabric_dac2_clk_en_i, fabric_dac2_din_i1, fabric_dac2_din_i2, fabric_dac2_din_i3, fabric_dac2_din_i4, fabric_dac2_din_i5, fabric_dac2_din_i6, fabric_dac2_din_i7, fabric_dac2_din_i8, fabric_dac2_din_i9
-, fabric_dac2_din_i10, fabric_dac2_din_i11, fabric_dac2_din_i12, fabric_dac2_din_i13, fabric_dac2_reg_pwr_down_n_i, fabric_dac2_rstn_i, fabric_dac2_op_en_i, fabric_dac2_filt_en_i, fabric_dac2_comp_en_i, fabric_dac2_comp_ref_sel_i, fabric_dac2_comp_hyst_en_i, fabric_dac2_comp_in_sel_i1, fabric_dac2_comp_in_sel_i2, fabric_dac2_comp_in_sel_i3, fabric_dac2_comp_in_sel_i4, fabric_dac2_comp_in_sel_i5, fabric_dac2_comp_in_sel_i6, fabric_dac2_comp_in_sel_i7, fabric_dac2_comp_in_sel_i8, fabric_dac2_comp_in_sel_i9, fabric_dac2_comp_in_sel_i10
-, fabric_dac2_comp_in_sel_i11, fabric_dac2_comp_in_sel_i12, fabric_dac2_comp_in_sel_i13, fabric_dac2_comp_out_o, fabric_cfg_dac2_reg_res_i1, fabric_cfg_dac2_reg_res_i2, fabric_cfg_dac2_reg_vref_select_i, fabric_cfg_dac2_reg_cm_select_i, fabric_cfg_dac2_sync_i, fabric_dac3_clk_i, fabric_dac3_clk_en_i, fabric_dac3_din_i1, fabric_dac3_din_i2, fabric_dac3_din_i3, fabric_dac3_din_i4, fabric_dac3_din_i5, fabric_dac3_din_i6, fabric_dac3_din_i7, fabric_dac3_din_i8, fabric_dac3_din_i9, fabric_dac3_din_i10
-, fabric_dac3_din_i11, fabric_dac3_din_i12, fabric_dac3_din_i13, fabric_dac3_reg_pwr_down_n_i, fabric_dac3_rstn_i, fabric_dac3_op_en_i, fabric_dac3_filt_en_i, fabric_dac3_comp_en_i, fabric_dac3_comp_ref_sel_i, fabric_dac3_comp_hyst_en_i, fabric_dac3_comp_in_sel_i1, fabric_dac3_comp_in_sel_i2, fabric_dac3_comp_in_sel_i3, fabric_dac3_comp_in_sel_i4, fabric_dac3_comp_out_o, fabric_cfg_dac3_reg_res_i1, fabric_cfg_dac3_reg_res_i2, fabric_cfg_dac3_reg_vref_select_i, fabric_cfg_dac3_reg_cm_select_i, fabric_cfg_dac3_sync_i, fabric_adc0_clk_i
-, fabric_adc0_arst_b_tmr_i1, fabric_adc0_arst_b_tmr_i2, fabric_adc0_arst_b_tmr_i3, fabric_adc0_pwr_down_b_tmr_i1, fabric_adc0_pwr_down_b_tmr_i2, fabric_adc0_pwr_down_b_tmr_i3, fabric_adc0_cal_start_i, fabric_adc0_cal_done_o, fabric_adc0_cal_p_overflow_o, fabric_adc0_cal_p_underflow_o, fabric_adc0_cal_n_overflow_o, fabric_adc0_cal_n_underflow_o, fabric_adc0_spare_i1, fabric_adc0_spare_i2, fabric_adc0_spare_i3, fabric_adc0_spare_i4, fabric_adc0_spare_i5, fabric_adc0_spare_i6, fabric_adc0_spare_i7, fabric_adc0_spare_i8, fabric_adc0_spare_i9
-, fabric_adc0_spare_i10, fabric_adc0_spare_i11, fabric_adc0_spare_i12, fabric_adc0_spare_i13, fabric_adc0_spare_i14, fabric_adc0_spare_i15, fabric_adc0_spare_i16, fabric_adc0_dft_test_mode_i1, fabric_adc0_dft_test_mode_i2, fabric_adc0_dft_scan_en_i, fabric_adc0_dft_si_i1, fabric_adc0_dft_si_i2, fabric_adc0_dft_si_i3, fabric_adc0_dft_si_i4, fabric_adc0_dft_si_i5, fabric_adc0_dft_si_i6, fabric_adc0_dft_si_i7, fabric_adc0_dft_si_i8, fabric_adc0_dft_si_i9, fabric_adc0_dft_si_i10, fabric_adc0_dft_si_i11
-, fabric_adc0_dft_si_i12, fabric_adc0_usr_cke_i, fabric_adc0_usr_arst_b_tmr_i1, fabric_adc0_usr_arst_b_tmr_i2, fabric_adc0_usr_arst_b_tmr_i3, fabric_adc0_usr_channel_i1, fabric_adc0_usr_channel_i2, fabric_adc0_usr_channel_i3, fabric_adc0_usr_conv_start_i, fabric_adc0_usr_conv_done_o, fabric_adc0_usr_sample_o1, fabric_adc0_usr_sample_o2, fabric_adc0_usr_sample_o3, fabric_adc0_usr_sample_o4, fabric_adc0_usr_sample_o5, fabric_adc0_usr_sample_o6, fabric_adc0_usr_sample_o7, fabric_adc0_usr_sample_o8, fabric_adc0_usr_sample_o9, fabric_adc0_usr_sample_o10, fabric_adc0_usr_sample_o11
-, fabric_adc0_usr_sample_o12, fabric_adc0_usr_sample_lsb_i1, fabric_adc0_usr_sample_lsb_i2, fabric_adc0_usr_sample_lsb_i3, fabric_adc0_usr_sample_lsb_i4, fabric_adc0_dbg_addr_i1, fabric_adc0_dbg_addr_i2, fabric_adc0_dbg_addr_i3, fabric_adc0_dbg_addr_i4, fabric_adc0_dbg_data_o1, fabric_adc0_dbg_data_o2, fabric_adc0_dbg_data_o3, fabric_adc0_dbg_data_o4, fabric_adc0_dbg_data_o5, fabric_adc0_dbg_data_o6, fabric_adc0_dbg_data_o7, fabric_adc0_dbg_data_o8, fabric_adc0_dbg_data_o9, fabric_adc0_dbg_data_o10, fabric_adc0_dbg_data_o11, fabric_adc0_dbg_data_o12
-, fabric_adc0_dbg_data_o13, fabric_adc0_dbg_data_o14, fabric_adc0_dbg_data_o15, fabric_adc0_dbg_data_o16, fabric_adc0_dbg_data_o17, fabric_adc0_dbg_data_o18, fabric_adc0_dbg_data_o19, fabric_adc0_dbg_data_o20, fabric_adc0_dbg_data_o21, fabric_adc0_dbg_data_o22, fabric_adc0_dbg_data_o23, fabric_adc0_dbg_data_o24, fabric_adc0_dbg_data_o25, fabric_adc0_dbg_data_o26, fabric_adc0_dbg_data_o27, fabric_adc0_dbg_data_o28, fabric_adc0_dbg_data_o29, fabric_adc0_dbg_data_o30, fabric_adc0_dbg_data_o31, fabric_adc0_dbg_data_o32, fabric_cfg_adc0_clk_cal_div_ratio_i1
-, fabric_cfg_adc0_clk_cal_div_ratio_i2, fabric_cfg_adc0_clk_cal_div_ratio_i3, fabric_cfg_adc0_clk_cal_div_ratio_i4, fabric_cfg_adc0_clk_cal_div_ratio_i5, fabric_cfg_adc0_conv_done_delayed_i, fabric_cfg_adc0_use_cdc_i, fabric_adc1_clk_i, fabric_adc1_arst_b_tmr_i1, fabric_adc1_arst_b_tmr_i2, fabric_adc1_arst_b_tmr_i3, fabric_adc1_pwr_down_b_tmr_i1, fabric_adc1_pwr_down_b_tmr_i2, fabric_adc1_pwr_down_b_tmr_i3, fabric_adc1_cal_start_i, fabric_adc1_cal_done_o, fabric_adc1_cal_p_overflow_o, fabric_adc1_cal_p_underflow_o, fabric_adc1_cal_n_overflow_o, fabric_adc1_cal_n_underflow_o, fabric_adc1_spare_i1, fabric_adc1_spare_i2
-, fabric_adc1_spare_i3, fabric_adc1_spare_i4, fabric_adc1_spare_i5, fabric_adc1_spare_i6, fabric_adc1_spare_i7, fabric_adc1_spare_i8, fabric_adc1_spare_i9, fabric_adc1_spare_i10, fabric_adc1_spare_i11, fabric_adc1_spare_i12, fabric_adc1_spare_i13, fabric_adc1_spare_i14, fabric_adc1_spare_i15, fabric_adc1_spare_i16, fabric_adc1_dft_test_mode_i1, fabric_adc1_dft_test_mode_i2, fabric_adc1_dft_scan_en_i, fabric_adc1_dft_si_i1, fabric_adc1_dft_si_i2, fabric_adc1_dft_si_i3, fabric_adc1_dft_si_i4
-, fabric_adc1_dft_si_i5, fabric_adc1_dft_si_i6, fabric_adc1_dft_si_i7, fabric_adc1_dft_si_i8, fabric_adc1_dft_si_i9, fabric_adc1_dft_si_i10, fabric_adc1_dft_si_i11, fabric_adc1_dft_si_i12, fabric_adc1_usr_cke_i, fabric_adc1_usr_arst_b_tmr_i1, fabric_adc1_usr_arst_b_tmr_i2, fabric_adc1_usr_arst_b_tmr_i3, fabric_adc1_usr_channel_i1, fabric_adc1_usr_channel_i2, fabric_adc1_usr_channel_i3, fabric_adc1_usr_conv_start_i, fabric_adc1_usr_conv_done_o, fabric_adc1_usr_sample_o1, fabric_adc1_usr_sample_o2, fabric_adc1_usr_sample_o3, fabric_adc1_usr_sample_o4
-, fabric_adc1_usr_sample_o5, fabric_adc1_usr_sample_o6, fabric_adc1_usr_sample_o7, fabric_adc1_usr_sample_o8, fabric_adc1_usr_sample_o9, fabric_adc1_usr_sample_o10, fabric_adc1_usr_sample_o11, fabric_adc1_usr_sample_o12, fabric_adc1_usr_sample_lsb_i1, fabric_adc1_usr_sample_lsb_i2, fabric_adc1_usr_sample_lsb_i3, fabric_adc1_usr_sample_lsb_i4, fabric_adc1_dbg_addr_i1, fabric_adc1_dbg_addr_i2, fabric_adc1_dbg_addr_i3, fabric_adc1_dbg_addr_i4, fabric_adc1_dbg_data_o1, fabric_adc1_dbg_data_o2, fabric_adc1_dbg_data_o3, fabric_adc1_dbg_data_o4, fabric_adc1_dbg_data_o5
-, fabric_adc1_dbg_data_o6, fabric_adc1_dbg_data_o7, fabric_adc1_dbg_data_o8, fabric_adc1_dbg_data_o9, fabric_adc1_dbg_data_o10, fabric_adc1_dbg_data_o11, fabric_adc1_dbg_data_o12, fabric_adc1_dbg_data_o13, fabric_adc1_dbg_data_o14, fabric_adc1_dbg_data_o15, fabric_adc1_dbg_data_o16, fabric_adc1_dbg_data_o17, fabric_adc1_dbg_data_o18, fabric_adc1_dbg_data_o19, fabric_adc1_dbg_data_o20, fabric_adc1_dbg_data_o21, fabric_adc1_dbg_data_o22, fabric_adc1_dbg_data_o23, fabric_adc1_dbg_data_o24, fabric_adc1_dbg_data_o25, fabric_adc1_dbg_data_o26
-, fabric_adc1_dbg_data_o27, fabric_adc1_dbg_data_o28, fabric_adc1_dbg_data_o29, fabric_adc1_dbg_data_o30, fabric_adc1_dbg_data_o31, fabric_adc1_dbg_data_o32, fabric_cfg_adc1_clk_cal_div_ratio_i1, fabric_cfg_adc1_clk_cal_div_ratio_i2, fabric_cfg_adc1_clk_cal_div_ratio_i3, fabric_cfg_adc1_clk_cal_div_ratio_i4, fabric_cfg_adc1_clk_cal_div_ratio_i5, fabric_cfg_adc1_conv_done_delayed_i, fabric_cfg_adc1_use_cdc_i, fabric_adc2_clk_i, fabric_adc2_arst_b_tmr_i1, fabric_adc2_arst_b_tmr_i2, fabric_adc2_arst_b_tmr_i3, fabric_adc2_pwr_down_b_tmr_i1, fabric_adc2_pwr_down_b_tmr_i2, fabric_adc2_pwr_down_b_tmr_i3, fabric_adc2_cal_start_i
-, fabric_adc2_cal_done_o, fabric_adc2_cal_p_overflow_o, fabric_adc2_cal_p_underflow_o, fabric_adc2_cal_n_overflow_o, fabric_adc2_cal_n_underflow_o, fabric_adc2_spare_i1, fabric_adc2_spare_i2, fabric_adc2_spare_i3, fabric_adc2_spare_i4, fabric_adc2_spare_i5, fabric_adc2_spare_i6, fabric_adc2_spare_i7, fabric_adc2_spare_i8, fabric_adc2_spare_i9, fabric_adc2_spare_i10, fabric_adc2_spare_i11, fabric_adc2_spare_i12, fabric_adc2_spare_i13, fabric_adc2_spare_i14, fabric_adc2_spare_i15, fabric_adc2_spare_i16
-, fabric_adc2_dft_test_mode_i1, fabric_adc2_dft_test_mode_i2, fabric_adc2_dft_scan_en_i, fabric_adc2_dft_si_i1, fabric_adc2_dft_si_i2, fabric_adc2_dft_si_i3, fabric_adc2_dft_si_i4, fabric_adc2_dft_si_i5, fabric_adc2_dft_si_i6, fabric_adc2_dft_si_i7, fabric_adc2_dft_si_i8, fabric_adc2_dft_si_i9, fabric_adc2_dft_si_i10, fabric_adc2_dft_si_i11, fabric_adc2_dft_si_i12, fabric_adc2_usr_cke_i, fabric_adc2_usr_arst_b_tmr_i1, fabric_adc2_usr_arst_b_tmr_i2, fabric_adc2_usr_arst_b_tmr_i3, fabric_adc2_usr_channel_i1, fabric_adc2_usr_channel_i2
-, fabric_adc2_usr_channel_i3, fabric_adc2_usr_conv_start_i, fabric_adc2_usr_conv_done_o, fabric_adc2_usr_sample_o1, fabric_adc2_usr_sample_o2, fabric_adc2_usr_sample_o3, fabric_adc2_usr_sample_o4, fabric_adc2_usr_sample_o5, fabric_adc2_usr_sample_o6, fabric_adc2_usr_sample_o7, fabric_adc2_usr_sample_o8, fabric_adc2_usr_sample_o9, fabric_adc2_usr_sample_o10, fabric_adc2_usr_sample_o11, fabric_adc2_usr_sample_o12, fabric_adc2_usr_sample_lsb_i1, fabric_adc2_usr_sample_lsb_i2, fabric_adc2_usr_sample_lsb_i3, fabric_adc2_usr_sample_lsb_i4, fabric_adc2_dbg_addr_i1, fabric_adc2_dbg_addr_i2
-, fabric_adc2_dbg_addr_i3, fabric_adc2_dbg_addr_i4, fabric_adc2_dbg_data_o1, fabric_adc2_dbg_data_o2, fabric_adc2_dbg_data_o3, fabric_adc2_dbg_data_o4, fabric_adc2_dbg_data_o5, fabric_adc2_dbg_data_o6, fabric_adc2_dbg_data_o7, fabric_adc2_dbg_data_o8, fabric_adc2_dbg_data_o9, fabric_adc2_dbg_data_o10, fabric_adc2_dbg_data_o11, fabric_adc2_dbg_data_o12, fabric_adc2_dbg_data_o13, fabric_adc2_dbg_data_o14, fabric_adc2_dbg_data_o15, fabric_adc2_dbg_data_o16, fabric_adc2_dbg_data_o17, fabric_adc2_dbg_data_o18, fabric_adc2_dbg_data_o19
-, fabric_adc2_dbg_data_o20, fabric_adc2_dbg_data_o21, fabric_adc2_dbg_data_o22, fabric_adc2_dbg_data_o23, fabric_adc2_dbg_data_o24, fabric_adc2_dbg_data_o25, fabric_adc2_dbg_data_o26, fabric_adc2_dbg_data_o27, fabric_adc2_dbg_data_o28, fabric_adc2_dbg_data_o29, fabric_adc2_dbg_data_o30, fabric_adc2_dbg_data_o31, fabric_adc2_dbg_data_o32, fabric_cfg_adc2_clk_cal_div_ratio_i1, fabric_cfg_adc2_clk_cal_div_ratio_i2, fabric_cfg_adc2_clk_cal_div_ratio_i3, fabric_cfg_adc2_clk_cal_div_ratio_i4, fabric_cfg_adc2_clk_cal_div_ratio_i5, fabric_cfg_adc2_conv_done_delayed_i, fabric_cfg_adc2_use_cdc_i, fabric_adc3_clk_i
-, fabric_adc3_arst_b_tmr_i1, fabric_adc3_arst_b_tmr_i2, fabric_adc3_arst_b_tmr_i3, fabric_adc3_pwr_down_b_tmr_i1, fabric_adc3_pwr_down_b_tmr_i2, fabric_adc3_pwr_down_b_tmr_i3, fabric_adc3_cal_start_i, fabric_adc3_cal_done_o, fabric_adc3_cal_p_overflow_o, fabric_adc3_cal_p_underflow_o, fabric_adc3_cal_n_overflow_o, fabric_adc3_cal_n_underflow_o, fabric_adc3_spare_i1, fabric_adc3_spare_i2, fabric_adc3_spare_i3, fabric_adc3_spare_i4, fabric_adc3_spare_i5, fabric_adc3_spare_i6, fabric_adc3_spare_i7, fabric_adc3_spare_i8, fabric_adc3_spare_i9
-, fabric_adc3_spare_i10, fabric_adc3_spare_i11, fabric_adc3_spare_i12, fabric_adc3_spare_i13, fabric_adc3_spare_i14, fabric_adc3_spare_i15, fabric_adc3_spare_i16, fabric_adc3_dft_test_mode_i1, fabric_adc3_dft_test_mode_i2, fabric_adc3_dft_scan_en_i, fabric_adc3_dft_si_i1, fabric_adc3_dft_si_i2, fabric_adc3_dft_si_i3, fabric_adc3_dft_si_i4, fabric_adc3_dft_si_i5, fabric_adc3_dft_si_i6, fabric_adc3_dft_si_i7, fabric_adc3_dft_si_i8, fabric_adc3_dft_si_i9, fabric_adc3_dft_si_i10, fabric_adc3_dft_si_i11
-, fabric_adc3_dft_si_i12, fabric_adc3_usr_cke_i, fabric_adc3_usr_arst_b_tmr_i1, fabric_adc3_usr_arst_b_tmr_i2, fabric_adc3_usr_arst_b_tmr_i3, fabric_adc3_usr_channel_i1, fabric_adc3_usr_channel_i2, fabric_adc3_usr_channel_i3, fabric_adc3_usr_conv_start_i, fabric_adc3_usr_conv_done_o, fabric_adc3_usr_sample_o1, fabric_adc3_usr_sample_o2, fabric_adc3_usr_sample_o3, fabric_adc3_usr_sample_o4, fabric_adc3_usr_sample_o5, fabric_adc3_usr_sample_o6, fabric_adc3_usr_sample_o7, fabric_adc3_usr_sample_o8, fabric_adc3_usr_sample_o9, fabric_adc3_usr_sample_o10, fabric_adc3_usr_sample_o11
-, fabric_adc3_usr_sample_o12, fabric_adc3_usr_sample_lsb_i1, fabric_adc3_usr_sample_lsb_i2, fabric_adc3_usr_sample_lsb_i3, fabric_adc3_usr_sample_lsb_i4, fabric_adc3_dbg_addr_i1, fabric_adc3_dbg_addr_i2, fabric_adc3_dbg_addr_i3, fabric_adc3_dbg_addr_i4, fabric_adc3_dbg_data_o1, fabric_adc3_dbg_data_o2, fabric_adc3_dbg_data_o3, fabric_adc3_dbg_data_o4, fabric_adc3_dbg_data_o5, fabric_adc3_dbg_data_o6, fabric_adc3_dbg_data_o7, fabric_adc3_dbg_data_o8, fabric_adc3_dbg_data_o9, fabric_adc3_dbg_data_o10, fabric_adc3_dbg_data_o11, fabric_adc3_dbg_data_o12
-, fabric_adc3_dbg_data_o13, fabric_adc3_dbg_data_o14, fabric_adc3_dbg_data_o15, fabric_adc3_dbg_data_o16, fabric_adc3_dbg_data_o17, fabric_adc3_dbg_data_o18, fabric_adc3_dbg_data_o19, fabric_adc3_dbg_data_o20, fabric_adc3_dbg_data_o21, fabric_adc3_dbg_data_o22, fabric_adc3_dbg_data_o23, fabric_adc3_dbg_data_o24, fabric_adc3_dbg_data_o25, fabric_adc3_dbg_data_o26, fabric_adc3_dbg_data_o27, fabric_adc3_dbg_data_o28, fabric_adc3_dbg_data_o29, fabric_adc3_dbg_data_o30, fabric_adc3_dbg_data_o31, fabric_adc3_dbg_data_o32, fabric_cfg_adc3_clk_cal_div_ratio_i1
-, fabric_cfg_adc3_clk_cal_div_ratio_i2, fabric_cfg_adc3_clk_cal_div_ratio_i3, fabric_cfg_adc3_clk_cal_div_ratio_i4, fabric_cfg_adc3_clk_cal_div_ratio_i5, fabric_cfg_adc3_conv_done_delayed_i, fabric_cfg_adc3_use_cdc_i, fabric_direct0_clock_fabric_i1, fabric_direct0_clock_fabric_i2, fabric_direct0_clock_fabric_i3, fabric_direct0_clock_fabric_i4, fabric_direct0_oe_i1, fabric_direct0_oe_i2, fabric_direct0_oe_i3, fabric_direct0_oe_i4, fabric_direct0_oe_i5, fabric_direct0_oe_i6, fabric_direct0_oe_i7, fabric_direct0_oe_i8, fabric_direct0_oe_i9, fabric_direct0_oe_i10, fabric_direct0_oe_i11
-, fabric_direct0_oe_i12, fabric_direct0_oe_i13, fabric_direct0_oe_i14, fabric_direct0_oe_i15, fabric_direct0_oe_i16, fabric_direct0_oe_i17, fabric_direct0_oe_i18, fabric_direct0_oe_i19, fabric_direct0_oe_i20, fabric_direct0_oe_i21, fabric_direct0_oe_i22, fabric_direct0_oe_i23, fabric_direct0_oe_i24, fabric_direct0_oe_ena_i1, fabric_direct0_oe_ena_i2, fabric_direct0_oe_ena_i3, fabric_direct0_oe_ena_i4, fabric_direct0_oe_ena_i5, fabric_direct0_oe_ena_i6, fabric_direct0_oe_ena_i7, fabric_direct0_oe_ena_i8
-, fabric_direct0_oe_ena_i9, fabric_direct0_oe_ena_i10, fabric_direct0_oe_ena_i11, fabric_direct0_oe_ena_i12, fabric_direct0_oe_ena_i13, fabric_direct0_oe_ena_i14, fabric_direct0_oe_ena_i15, fabric_direct0_oe_ena_i16, fabric_direct0_oe_ena_i17, fabric_direct0_oe_ena_i18, fabric_direct0_oe_ena_i19, fabric_direct0_oe_ena_i20, fabric_direct0_oe_ena_i21, fabric_direct0_oe_ena_i22, fabric_direct0_oe_ena_i23, fabric_direct0_oe_ena_i24, fabric_direct0_oe_rs_i1, fabric_direct0_oe_rs_i2, fabric_direct0_oe_rs_i3, fabric_direct0_oe_rs_i4, fabric_direct0_oe_rs_i5
-, fabric_direct0_oe_rs_i6, fabric_direct0_oe_rs_i7, fabric_direct0_oe_rs_i8, fabric_direct0_oe_rs_i9, fabric_direct0_oe_rs_i10, fabric_direct0_oe_rs_i11, fabric_direct0_oe_rs_i12, fabric_direct0_oe_rs_i13, fabric_direct0_oe_rs_i14, fabric_direct0_oe_rs_i15, fabric_direct0_oe_rs_i16, fabric_direct0_oe_rs_i17, fabric_direct0_oe_rs_i18, fabric_direct0_oe_rs_i19, fabric_direct0_oe_rs_i20, fabric_direct0_oe_rs_i21, fabric_direct0_oe_rs_i22, fabric_direct0_oe_rs_i23, fabric_direct0_oe_rs_i24, fabric_direct0_do_i1, fabric_direct0_do_i2
-, fabric_direct0_do_i3, fabric_direct0_do_i4, fabric_direct0_do_i5, fabric_direct0_do_i6, fabric_direct0_do_i7, fabric_direct0_do_i8, fabric_direct0_do_i9, fabric_direct0_do_i10, fabric_direct0_do_i11, fabric_direct0_do_i12, fabric_direct0_do_i13, fabric_direct0_do_i14, fabric_direct0_do_i15, fabric_direct0_do_i16, fabric_direct0_do_i17, fabric_direct0_do_i18, fabric_direct0_do_i19, fabric_direct0_do_i20, fabric_direct0_do_i21, fabric_direct0_do_i22, fabric_direct0_do_i23
-, fabric_direct0_do_i24, fabric_direct0_do_ena_i1, fabric_direct0_do_ena_i2, fabric_direct0_do_ena_i3, fabric_direct0_do_ena_i4, fabric_direct0_do_ena_i5, fabric_direct0_do_ena_i6, fabric_direct0_do_ena_i7, fabric_direct0_do_ena_i8, fabric_direct0_do_ena_i9, fabric_direct0_do_ena_i10, fabric_direct0_do_ena_i11, fabric_direct0_do_ena_i12, fabric_direct0_do_ena_i13, fabric_direct0_do_ena_i14, fabric_direct0_do_ena_i15, fabric_direct0_do_ena_i16, fabric_direct0_do_ena_i17, fabric_direct0_do_ena_i18, fabric_direct0_do_ena_i19, fabric_direct0_do_ena_i20
-, fabric_direct0_do_ena_i21, fabric_direct0_do_ena_i22, fabric_direct0_do_ena_i23, fabric_direct0_do_ena_i24, fabric_direct0_do_rs_i1, fabric_direct0_do_rs_i2, fabric_direct0_do_rs_i3, fabric_direct0_do_rs_i4, fabric_direct0_do_rs_i5, fabric_direct0_do_rs_i6, fabric_direct0_do_rs_i7, fabric_direct0_do_rs_i8, fabric_direct0_do_rs_i9, fabric_direct0_do_rs_i10, fabric_direct0_do_rs_i11, fabric_direct0_do_rs_i12, fabric_direct0_do_rs_i13, fabric_direct0_do_rs_i14, fabric_direct0_do_rs_i15, fabric_direct0_do_rs_i16, fabric_direct0_do_rs_i17
-, fabric_direct0_do_rs_i18, fabric_direct0_do_rs_i19, fabric_direct0_do_rs_i20, fabric_direct0_do_rs_i21, fabric_direct0_do_rs_i22, fabric_direct0_do_rs_i23, fabric_direct0_do_rs_i24, fabric_direct0_di_o1, fabric_direct0_di_o2, fabric_direct0_di_o3, fabric_direct0_di_o4, fabric_direct0_di_o5, fabric_direct0_di_o6, fabric_direct0_di_o7, fabric_direct0_di_o8, fabric_direct0_di_o9, fabric_direct0_di_o10, fabric_direct0_di_o11, fabric_direct0_di_o12, fabric_direct0_di_o13, fabric_direct0_di_o14
-, fabric_direct0_di_o15, fabric_direct0_di_o16, fabric_direct0_di_o17, fabric_direct0_di_o18, fabric_direct0_di_o19, fabric_direct0_di_o20, fabric_direct0_di_o21, fabric_direct0_di_o22, fabric_direct0_di_o23, fabric_direct0_di_o24, fabric_direct0_di_ena_i1, fabric_direct0_di_ena_i2, fabric_direct0_di_ena_i3, fabric_direct0_di_ena_i4, fabric_direct0_di_ena_i5, fabric_direct0_di_ena_i6, fabric_direct0_di_ena_i7, fabric_direct0_di_ena_i8, fabric_direct0_di_ena_i9, fabric_direct0_di_ena_i10, fabric_direct0_di_ena_i11
-, fabric_direct0_di_ena_i12, fabric_direct0_di_ena_i13, fabric_direct0_di_ena_i14, fabric_direct0_di_ena_i15, fabric_direct0_di_ena_i16, fabric_direct0_di_ena_i17, fabric_direct0_di_ena_i18, fabric_direct0_di_ena_i19, fabric_direct0_di_ena_i20, fabric_direct0_di_ena_i21, fabric_direct0_di_ena_i22, fabric_direct0_di_ena_i23, fabric_direct0_di_ena_i24, fabric_direct0_di_rs_i1, fabric_direct0_di_rs_i2, fabric_direct0_di_rs_i3, fabric_direct0_di_rs_i4, fabric_direct0_di_rs_i5, fabric_direct0_di_rs_i6, fabric_direct0_di_rs_i7, fabric_direct0_di_rs_i8
-, fabric_direct0_di_rs_i9, fabric_direct0_di_rs_i10, fabric_direct0_di_rs_i11, fabric_direct0_di_rs_i12, fabric_direct0_di_rs_i13, fabric_direct0_di_rs_i14, fabric_direct0_di_rs_i15, fabric_direct0_di_rs_i16, fabric_direct0_di_rs_i17, fabric_direct0_di_rs_i18, fabric_direct0_di_rs_i19, fabric_direct0_di_rs_i20, fabric_direct0_di_rs_i21, fabric_direct0_di_rs_i22, fabric_direct0_di_rs_i23, fabric_direct0_di_rs_i24, fabric_direct0_cfg_bank_i1, fabric_direct0_cfg_bank_i2, fabric_direct0_cfg_bank_i3, fabric_direct0_cfg_bank_i4, fabric_direct0_cfg_pad_i1
-, fabric_direct0_cfg_pad_i2, fabric_direct0_cfg_pad_i3, fabric_direct0_cfg_pad_i4, fabric_direct0_cfg_pad_i5, fabric_direct0_cfg_pad_i6, fabric_direct0_cfg_pad_i7, fabric_direct0_cfg_pad_i8, fabric_direct0_cfg_pad_i9, fabric_direct0_cfg_pad_i10, fabric_direct0_cfg_pad_i11, fabric_direct0_cfg_pad_i12, fabric_direct0_cfg_pad_i13, fabric_direct0_cfg_pad_i14, fabric_direct0_cfg_pad_i15, fabric_direct0_cfg_pad_i16, fabric_direct0_cfg_pad_i17, fabric_direct0_cfg_pad_i18, fabric_direct0_cfg_pad_i19, fabric_direct0_cfg_pad_i20, fabric_direct0_cfg_pad_i21, fabric_direct0_cfg_pad_i22
-, fabric_direct0_cfg_pad_i23, fabric_direct0_cfg_pad_i24, fabric_direct0_cfg_pad_i25, fabric_direct0_cfg_pad_i26, fabric_direct0_cfg_pad_i27, fabric_direct0_cfg_pad_i28, fabric_direct0_cfg_pad_i29, fabric_direct0_cfg_pad_i30, fabric_direct0_cfg_pad_i31, fabric_direct0_cfg_pad_i32, fabric_direct0_cfg_pad_i33, fabric_direct0_cfg_pad_i34, fabric_direct0_cfg_pad_i35, fabric_direct0_cfg_pad_i36, fabric_direct0_cfg_pad_i37, fabric_direct0_cfg_pad_i38, fabric_direct0_cfg_pad_i39, fabric_direct0_cfg_pad_i40, fabric_direct0_cfg_pad_i41, fabric_direct0_cfg_pad_i42, fabric_direct0_cfg_pad_i43
-, fabric_direct0_cfg_pad_i44, fabric_direct0_cfg_pad_i45, fabric_direct0_cfg_pad_i46, fabric_direct0_cfg_pad_i47, fabric_direct0_cfg_pad_i48, fabric_direct0_cfg_pad_i49, fabric_direct0_cfg_pad_i50, fabric_direct0_cfg_pad_i51, fabric_direct0_cfg_pad_i52, fabric_direct0_cfg_pad_i53, fabric_direct0_cfg_pad_i54, fabric_direct0_cfg_pad_i55, fabric_direct0_cfg_pad_i56, fabric_direct0_cfg_pad_i57, fabric_direct0_cfg_pad_i58, fabric_direct0_cfg_pad_i59, fabric_direct0_cfg_pad_i60, fabric_direct0_cfg_pad_i61, fabric_direct0_cfg_pad_i62, fabric_direct0_cfg_pad_i63, fabric_direct0_cfg_pad_i64
-, fabric_direct0_cfg_pad_i65, fabric_direct0_cfg_pad_i66, fabric_direct0_cfg_pad_i67, fabric_direct0_cfg_pad_i68, fabric_direct0_cfg_pad_i69, fabric_direct0_cfg_pad_i70, fabric_direct0_cfg_pad_i71, fabric_direct0_cfg_pad_i72, fabric_direct0_cfg_pad_i73, fabric_direct0_cfg_pad_i74, fabric_direct0_cfg_pad_i75, fabric_direct0_cfg_pad_i76, fabric_direct0_cfg_pad_i77, fabric_direct0_cfg_pad_i78, fabric_direct0_cfg_pad_i79, fabric_direct0_cfg_pad_i80, fabric_direct0_cfg_pad_i81, fabric_direct0_cfg_pad_i82, fabric_direct0_cfg_pad_i83, fabric_direct0_cfg_pad_i84, fabric_direct0_cfg_pad_i85
-, fabric_direct0_cfg_pad_i86, fabric_direct0_cfg_pad_i87, fabric_direct0_cfg_pad_i88, fabric_direct0_cfg_pad_i89, fabric_direct0_cfg_pad_i90, fabric_direct0_cfg_pad_i91, fabric_direct0_cfg_pad_i92, fabric_direct0_cfg_pad_i93, fabric_direct0_cfg_pad_i94, fabric_direct0_cfg_pad_i95, fabric_direct0_cfg_pad_i96, fabric_direct0_cfg_pad_i97, fabric_direct0_cfg_pad_i98, fabric_direct0_cfg_pad_i99, fabric_direct0_cfg_pad_i100, fabric_direct0_cfg_pad_i101, fabric_direct0_cfg_pad_i102, fabric_direct0_cfg_pad_i103, fabric_direct0_cfg_pad_i104, fabric_direct0_cfg_pad_i105, fabric_direct0_cfg_pad_i106
-, fabric_direct0_cfg_pad_i107, fabric_direct0_cfg_pad_i108, fabric_direct0_cfg_pad_i109, fabric_direct0_cfg_pad_i110, fabric_direct0_cfg_pad_i111, fabric_direct0_cfg_pad_i112, fabric_direct0_cfg_pad_i113, fabric_direct0_cfg_pad_i114, fabric_direct0_cfg_pad_i115, fabric_direct0_cfg_pad_i116, fabric_direct0_cfg_pad_i117, fabric_direct0_cfg_pad_i118, fabric_direct0_cfg_pad_i119, fabric_direct0_cfg_pad_i120, fabric_direct0_cfg_pad_i121, fabric_direct0_cfg_pad_i122, fabric_direct0_cfg_pad_i123, fabric_direct0_cfg_pad_i124, fabric_direct0_cfg_pad_i125, fabric_direct0_cfg_pad_i126, fabric_direct0_cfg_pad_i127
-, fabric_direct0_cfg_pad_i128, fabric_direct0_cfg_pad_i129, fabric_direct0_cfg_pad_i130, fabric_direct0_cfg_pad_i131, fabric_direct0_cfg_pad_i132, fabric_direct0_cfg_pad_i133, fabric_direct0_cfg_pad_i134, fabric_direct0_cfg_pad_i135, fabric_direct0_cfg_pad_i136, fabric_direct0_cfg_pad_i137, fabric_direct0_cfg_pad_i138, fabric_direct0_cfg_pad_i139, fabric_direct0_cfg_pad_i140, fabric_direct0_cfg_pad_i141, fabric_direct0_cfg_pad_i142, fabric_direct0_cfg_pad_i143, fabric_direct0_cfg_pad_i144, fabric_direct0_cfg_pad_i145, fabric_direct0_cfg_pad_i146, fabric_direct0_cfg_pad_i147, fabric_direct0_cfg_pad_i148
-, fabric_direct0_cfg_pad_i149, fabric_direct0_cfg_pad_i150, fabric_direct0_cfg_pad_i151, fabric_direct0_cfg_pad_i152, fabric_direct0_cfg_pad_i153, fabric_direct0_cfg_pad_i154, fabric_direct0_cfg_pad_i155, fabric_direct0_cfg_pad_i156, fabric_direct0_cfg_pad_i157, fabric_direct0_cfg_pad_i158, fabric_direct0_cfg_pad_i159, fabric_direct0_cfg_pad_i160, fabric_direct0_cfg_pad_i161, fabric_direct0_cfg_pad_i162, fabric_direct0_cfg_pad_i163, fabric_direct0_cfg_pad_i164, fabric_direct0_cfg_pad_i165, fabric_direct0_cfg_pad_i166, fabric_direct0_cfg_pad_i167, fabric_direct0_cfg_pad_i168, fabric_direct0_cfg_pad_i169
-, fabric_direct0_cfg_pad_i170, fabric_direct0_cfg_pad_i171, fabric_direct0_cfg_pad_i172, fabric_direct0_cfg_pad_i173, fabric_direct0_cfg_pad_i174, fabric_direct0_cfg_pad_i175, fabric_direct0_cfg_pad_i176, fabric_direct0_cfg_pad_i177, fabric_direct0_cfg_pad_i178, fabric_direct0_cfg_pad_i179, fabric_direct0_cfg_pad_i180, fabric_direct0_cfg_pad_i181, fabric_direct0_cfg_pad_i182, fabric_direct0_cfg_pad_i183, fabric_direct0_cfg_pad_i184, fabric_direct0_cfg_pad_i185, fabric_direct0_cfg_pad_i186, fabric_direct0_cfg_pad_i187, fabric_direct0_cfg_pad_i188, fabric_direct0_cfg_pad_i189, fabric_direct0_cfg_pad_i190
-, fabric_direct0_cfg_pad_i191, fabric_direct0_cfg_pad_i192, fabric_direct0_cfg_pad_i193, fabric_direct0_cfg_pad_i194, fabric_direct0_cfg_pad_i195, fabric_direct0_cfg_pad_i196, fabric_direct0_cfg_pad_i197, fabric_direct0_cfg_pad_i198, fabric_direct0_cfg_pad_i199, fabric_direct0_cfg_pad_i200, fabric_direct0_cfg_pad_i201, fabric_direct0_cfg_pad_i202, fabric_direct0_cfg_pad_i203, fabric_direct0_cfg_pad_i204, fabric_direct0_cfg_pad_i205, fabric_direct0_cfg_pad_i206, fabric_direct0_cfg_pad_i207, fabric_direct0_cfg_pad_i208, fabric_direct0_cfg_pad_i209, fabric_direct0_cfg_pad_i210, fabric_direct0_cfg_pad_i211
-, fabric_direct0_cfg_pad_i212, fabric_direct0_cfg_pad_i213, fabric_direct0_cfg_pad_i214, fabric_direct0_cfg_pad_i215, fabric_direct0_cfg_pad_i216, fabric_direct0_cfg_pad_i217, fabric_direct0_cfg_pad_i218, fabric_direct0_cfg_pad_i219, fabric_direct0_cfg_pad_i220, fabric_direct0_cfg_pad_i221, fabric_direct0_cfg_pad_i222, fabric_direct0_cfg_pad_i223, fabric_direct0_cfg_pad_i224, fabric_direct0_cfg_pad_i225, fabric_direct0_cfg_pad_i226, fabric_direct0_cfg_pad_i227, fabric_direct0_cfg_pad_i228, fabric_direct0_cfg_pad_i229, fabric_direct0_cfg_pad_i230, fabric_direct0_cfg_pad_i231, fabric_direct0_cfg_pad_i232
-, fabric_direct0_cfg_pad_i233, fabric_direct0_cfg_pad_i234, fabric_direct0_cfg_pad_i235, fabric_direct0_cfg_pad_i236, fabric_direct0_cfg_pad_i237, fabric_direct0_cfg_pad_i238, fabric_direct0_cfg_pad_i239, fabric_direct0_cfg_pad_i240, fabric_direct0_cfg_pad_i241, fabric_direct0_cfg_pad_i242, fabric_direct0_cfg_pad_i243, fabric_direct0_cfg_pad_i244, fabric_direct0_cfg_pad_i245, fabric_direct0_cfg_pad_i246, fabric_direct0_cfg_pad_i247, fabric_direct0_cfg_pad_i248, fabric_direct0_cfg_pad_i249, fabric_direct0_cfg_pad_i250, fabric_direct0_cfg_pad_i251, fabric_direct0_cfg_pad_i252, fabric_direct0_cfg_pad_i253
-, fabric_direct0_cfg_pad_i254, fabric_direct0_cfg_pad_i255, fabric_direct0_cfg_pad_i256, fabric_direct0_cfg_pad_i257, fabric_direct0_cfg_pad_i258, fabric_direct0_cfg_pad_i259, fabric_direct0_cfg_pad_i260, fabric_direct0_cfg_pad_i261, fabric_direct0_cfg_pad_i262, fabric_direct0_cfg_pad_i263, fabric_direct0_cfg_pad_i264, fabric_direct0_cfg_pad_i265, fabric_direct0_cfg_pad_i266, fabric_direct0_cfg_pad_i267, fabric_direct0_cfg_pad_i268, fabric_direct0_cfg_pad_i269, fabric_direct0_cfg_pad_i270, fabric_direct0_cfg_pad_i271, fabric_direct0_cfg_pad_i272, fabric_direct0_cfg_pad_i273, fabric_direct0_cfg_pad_i274
-, fabric_direct0_cfg_pad_i275, fabric_direct0_cfg_pad_i276, fabric_direct0_cfg_pad_i277, fabric_direct0_cfg_pad_i278, fabric_direct0_cfg_pad_i279, fabric_direct0_cfg_pad_i280, fabric_direct0_cfg_pad_i281, fabric_direct0_cfg_pad_i282, fabric_direct0_cfg_pad_i283, fabric_direct0_cfg_pad_i284, fabric_direct0_cfg_pad_i285, fabric_direct0_cfg_pad_i286, fabric_direct0_cfg_pad_i287, fabric_direct0_cfg_pad_i288, fabric_direct0_cfg_pad_i289, fabric_direct0_cfg_pad_i290, fabric_direct0_cfg_pad_i291, fabric_direct0_cfg_pad_i292, fabric_direct0_cfg_pad_i293, fabric_direct0_cfg_pad_i294, fabric_direct0_cfg_pad_i295
-, fabric_direct0_cfg_pad_i296, fabric_direct0_cfg_pad_i297, fabric_direct0_cfg_pad_i298, fabric_direct0_cfg_pad_i299, fabric_direct0_cfg_pad_i300, fabric_direct0_cfg_pad_i301, fabric_direct0_cfg_pad_i302, fabric_direct0_cfg_pad_i303, fabric_direct0_cfg_pad_i304, fabric_direct0_cfg_pad_i305, fabric_direct0_cfg_pad_i306, fabric_direct0_cfg_pad_i307, fabric_direct0_cfg_pad_i308, fabric_direct0_cfg_pad_i309, fabric_direct0_cfg_pad_i310, fabric_direct0_cfg_pad_i311, fabric_direct0_cfg_pad_i312, fabric_direct0_cfg_pad_i313, fabric_direct0_cfg_pad_i314, fabric_direct0_cfg_pad_i315, fabric_direct0_cfg_pad_i316
-, fabric_direct0_cfg_pad_i317, fabric_direct0_cfg_pad_i318, fabric_direct0_cfg_pad_i319, fabric_direct0_cfg_pad_i320, fabric_direct0_cfg_pad_i321, fabric_direct0_cfg_pad_i322, fabric_direct0_cfg_pad_i323, fabric_direct0_cfg_pad_i324, fabric_direct0_cfg_pad_i325, fabric_direct0_cfg_pad_i326, fabric_direct0_cfg_pad_i327, fabric_direct0_cfg_pad_i328, fabric_direct0_cfg_pad_i329, fabric_direct0_cfg_pad_i330, fabric_direct0_cfg_pad_i331, fabric_direct0_cfg_pad_i332, fabric_direct0_cfg_pad_i333, fabric_direct0_cfg_pad_i334, fabric_direct0_cfg_pad_i335, fabric_direct0_cfg_pad_i336, fabric_direct0_cfg_pad_i337
-, fabric_direct0_cfg_pad_i338, fabric_direct0_cfg_pad_i339, fabric_direct0_cfg_pad_i340, fabric_direct0_cfg_pad_i341, fabric_direct0_cfg_pad_i342, fabric_direct0_cfg_pad_i343, fabric_direct0_cfg_pad_i344, fabric_direct0_cfg_pad_i345, fabric_direct0_cfg_pad_i346, fabric_direct0_cfg_pad_i347, fabric_direct0_cfg_pad_i348, fabric_direct0_cfg_pad_i349, fabric_direct0_cfg_pad_i350, fabric_direct0_cfg_pad_i351, fabric_direct0_cfg_pad_i352, fabric_direct0_cfg_pad_i353, fabric_direct0_cfg_pad_i354, fabric_direct0_cfg_pad_i355, fabric_direct0_cfg_pad_i356, fabric_direct0_cfg_pad_i357, fabric_direct0_cfg_pad_i358
-, fabric_direct0_cfg_pad_i359, fabric_direct0_cfg_pad_i360, fabric_direct0_cfg_pad_i361, fabric_direct0_cfg_pad_i362, fabric_direct0_cfg_pad_i363, fabric_direct0_cfg_pad_i364, fabric_direct0_cfg_pad_i365, fabric_direct0_cfg_pad_i366, fabric_direct0_cfg_pad_i367, fabric_direct0_cfg_pad_i368, fabric_direct0_cfg_pad_i369, fabric_direct0_cfg_pad_i370, fabric_direct0_cfg_pad_i371, fabric_direct0_cfg_pad_i372, fabric_direct0_cfg_pad_i373, fabric_direct0_cfg_pad_i374, fabric_direct0_cfg_pad_i375, fabric_direct0_cfg_pad_i376, fabric_direct0_cfg_pad_i377, fabric_direct0_cfg_pad_i378, fabric_direct0_cfg_pad_i379
-, fabric_direct0_cfg_pad_i380, fabric_direct0_cfg_pad_i381, fabric_direct0_cfg_pad_i382, fabric_direct0_cfg_pad_i383, fabric_direct0_cfg_pad_i384, fabric_direct0_cfg_pad_i385, fabric_direct0_cfg_pad_i386, fabric_direct0_cfg_pad_i387, fabric_direct0_cfg_pad_i388, fabric_direct0_cfg_pad_i389, fabric_direct0_cfg_pad_i390, fabric_direct0_cfg_pad_i391, fabric_direct0_cfg_pad_i392, fabric_direct0_cfg_pad_i393, fabric_direct0_cfg_pad_i394, fabric_direct0_cfg_pad_i395, fabric_direct0_cfg_pad_i396, fabric_direct0_cfg_pad_i397, fabric_direct0_cfg_pad_i398, fabric_direct0_cfg_pad_i399, fabric_direct0_cfg_pad_i400
-, fabric_direct0_cfg_pad_i401, fabric_direct0_cfg_pad_i402, fabric_direct0_cfg_pad_i403, fabric_direct0_cfg_pad_i404, fabric_direct0_cfg_pad_i405, fabric_direct0_cfg_pad_i406, fabric_direct0_cfg_pad_i407, fabric_direct0_cfg_pad_i408, fabric_direct0_cfg_pad_i409, fabric_direct0_cfg_pad_i410, fabric_direct0_cfg_pad_i411, fabric_direct0_cfg_pad_i412, fabric_direct0_cfg_pad_i413, fabric_direct0_cfg_pad_i414, fabric_direct0_cfg_pad_i415, fabric_direct0_cfg_pad_i416, fabric_direct0_cfg_pad_i417, fabric_direct0_cfg_pad_i418, fabric_direct0_cfg_pad_i419, fabric_direct0_cfg_pad_i420, fabric_direct0_cfg_pad_i421
-, fabric_direct0_cfg_pad_i422, fabric_direct0_cfg_pad_i423, fabric_direct0_cfg_pad_i424, fabric_direct0_cfg_pad_i425, fabric_direct0_cfg_pad_i426, fabric_direct0_cfg_pad_i427, fabric_direct0_cfg_pad_i428, fabric_direct0_cfg_pad_i429, fabric_direct0_cfg_pad_i430, fabric_direct0_cfg_pad_i431, fabric_direct0_cfg_pad_i432, fabric_direct0_cfg_pad_i433, fabric_direct0_cfg_pad_i434, fabric_direct0_cfg_pad_i435, fabric_direct0_cfg_pad_i436, fabric_direct0_cfg_pad_i437, fabric_direct0_cfg_pad_i438, fabric_direct0_cfg_pad_i439, fabric_direct0_cfg_pad_i440, fabric_direct0_cfg_pad_i441, fabric_direct0_cfg_pad_i442
-, fabric_direct0_cfg_pad_i443, fabric_direct0_cfg_pad_i444, fabric_direct0_cfg_pad_i445, fabric_direct0_cfg_pad_i446, fabric_direct0_cfg_pad_i447, fabric_direct0_cfg_pad_i448, fabric_direct0_cfg_pad_i449, fabric_direct0_cfg_pad_i450, fabric_direct0_cfg_pad_i451, fabric_direct0_cfg_pad_i452, fabric_direct0_cfg_pad_i453, fabric_direct0_cfg_pad_i454, fabric_direct0_cfg_pad_i455, fabric_direct0_cfg_pad_i456, fabric_direct0_cfg_pad_i457, fabric_direct0_cfg_pad_i458, fabric_direct0_cfg_pad_i459, fabric_direct0_cfg_pad_i460, fabric_direct0_cfg_pad_i461, fabric_direct0_cfg_pad_i462, fabric_direct0_cfg_pad_i463
-, fabric_direct0_cfg_pad_i464, fabric_direct0_cfg_pad_i465, fabric_direct0_cfg_pad_i466, fabric_direct0_cfg_pad_i467, fabric_direct0_cfg_pad_i468, fabric_direct0_cfg_pad_i469, fabric_direct0_cfg_pad_i470, fabric_direct0_cfg_pad_i471, fabric_direct0_cfg_pad_i472, fabric_direct0_cfg_pad_i473, fabric_direct0_cfg_pad_i474, fabric_direct0_cfg_pad_i475, fabric_direct0_cfg_pad_i476, fabric_direct0_cfg_pad_i477, fabric_direct0_cfg_pad_i478, fabric_direct0_cfg_pad_i479, fabric_direct0_cfg_pad_i480, fabric_direct0_cfg_pad_i481, fabric_direct0_cfg_pad_i482, fabric_direct0_cfg_pad_i483, fabric_direct0_cfg_pad_i484
-, fabric_direct0_cfg_pad_i485, fabric_direct0_cfg_pad_i486, fabric_direct0_cfg_pad_i487, fabric_direct0_cfg_pad_i488, fabric_direct0_cfg_pad_i489, fabric_direct0_cfg_pad_i490, fabric_direct0_cfg_pad_i491, fabric_direct0_cfg_pad_i492, fabric_direct0_cfg_pad_i493, fabric_direct0_cfg_pad_i494, fabric_direct0_cfg_pad_i495, fabric_direct0_cfg_pad_i496, fabric_direct0_cfg_pad_i497, fabric_direct0_cfg_pad_i498, fabric_direct0_cfg_pad_i499, fabric_direct0_cfg_pad_i500, fabric_direct0_cfg_pad_i501, fabric_direct0_cfg_pad_i502, fabric_direct0_cfg_pad_i503, fabric_direct0_cfg_pad_i504, fabric_direct0_cfg_pad_i505
-, fabric_direct0_cfg_pad_i506, fabric_direct0_cfg_pad_i507, fabric_direct0_cfg_pad_i508, fabric_direct0_cfg_pad_i509, fabric_direct0_cfg_pad_i510, fabric_direct0_cfg_pad_i511, fabric_direct0_cfg_pad_i512, fabric_direct0_cfg_pad_i513, fabric_direct0_cfg_pad_i514, fabric_direct0_cfg_pad_i515, fabric_direct0_cfg_pad_i516, fabric_direct0_cfg_pad_i517, fabric_direct0_cfg_pad_i518, fabric_direct0_cfg_pad_i519, fabric_direct0_cfg_pad_i520, fabric_direct0_cfg_pad_i521, fabric_direct0_cfg_pad_i522, fabric_direct0_cfg_pad_i523, fabric_direct0_cfg_pad_i524, fabric_direct0_cfg_pad_i525, fabric_direct0_cfg_pad_i526
-, fabric_direct0_cfg_pad_i527, fabric_direct0_cfg_pad_i528, fabric_direct0_cfg_pad_i529, fabric_direct0_cfg_pad_i530, fabric_direct0_cfg_pad_i531, fabric_direct0_cfg_pad_i532, fabric_direct0_cfg_pad_i533, fabric_direct0_cfg_pad_i534, fabric_direct0_cfg_pad_i535, fabric_direct0_cfg_pad_i536, fabric_direct0_cfg_pad_i537, fabric_direct0_cfg_pad_i538, fabric_direct0_cfg_pad_i539, fabric_direct0_cfg_pad_i540, fabric_direct0_cfg_pad_i541, fabric_direct0_cfg_pad_i542, fabric_direct0_cfg_pad_i543, fabric_direct0_cfg_pad_i544, fabric_direct0_cfg_pad_i545, fabric_direct0_cfg_pad_i546, fabric_direct0_cfg_pad_i547
-, fabric_direct0_cfg_pad_i548, fabric_direct0_cfg_pad_i549, fabric_direct0_cfg_pad_i550, fabric_direct0_cfg_pad_i551, fabric_direct0_cfg_pad_i552, fabric_direct0_cfg_pad_i553, fabric_direct0_cfg_pad_i554, fabric_direct0_cfg_pad_i555, fabric_direct0_cfg_pad_i556, fabric_direct0_cfg_pad_i557, fabric_direct0_cfg_pad_i558, fabric_direct0_cfg_pad_i559, fabric_direct0_cfg_pad_i560, fabric_direct0_cfg_pad_i561, fabric_direct0_cfg_pad_i562, fabric_direct0_cfg_pad_i563, fabric_direct0_cfg_pad_i564, fabric_direct0_cfg_pad_i565, fabric_direct0_cfg_pad_i566, fabric_direct0_cfg_pad_i567, fabric_direct0_cfg_pad_i568
-, fabric_direct0_cfg_pad_i569, fabric_direct0_cfg_pad_i570, fabric_direct0_cfg_pad_i571, fabric_direct0_cfg_pad_i572, fabric_direct0_cfg_pad_i573, fabric_direct0_cfg_pad_i574, fabric_direct0_cfg_pad_i575, fabric_direct0_cfg_pad_i576, fabric_direct0_cfg_pad_i577, fabric_direct0_cfg_pad_i578, fabric_direct0_cfg_pad_i579, fabric_direct0_cfg_pad_i580, fabric_direct0_cfg_pad_i581, fabric_direct0_cfg_pad_i582, fabric_direct0_cfg_pad_i583, fabric_direct0_cfg_pad_i584, fabric_direct0_cfg_pad_i585, fabric_direct0_cfg_pad_i586, fabric_direct0_cfg_pad_i587, fabric_direct0_cfg_pad_i588, fabric_direct0_cfg_pad_i589
-, fabric_direct0_cfg_pad_i590, fabric_direct0_cfg_pad_i591, fabric_direct0_cfg_pad_i592, fabric_direct0_cfg_pad_i593, fabric_direct0_cfg_pad_i594, fabric_direct0_cfg_pad_i595, fabric_direct0_cfg_pad_i596, fabric_direct0_cfg_pad_i597, fabric_direct0_cfg_pad_i598, fabric_direct0_cfg_pad_i599, fabric_direct0_cfg_pad_i600, fabric_direct0_cfg_pad_i601, fabric_direct0_cfg_pad_i602, fabric_direct0_cfg_pad_i603, fabric_direct0_cfg_pad_i604, fabric_direct0_cfg_pad_i605, fabric_direct0_cfg_pad_i606, fabric_direct0_cfg_pad_i607, fabric_direct0_cfg_pad_i608, fabric_direct0_cfg_pad_i609, fabric_direct0_cfg_pad_i610
-, fabric_direct0_cfg_pad_i611, fabric_direct0_cfg_pad_i612, fabric_direct0_cfg_pad_i613, fabric_direct0_cfg_pad_i614, fabric_direct0_cfg_pad_i615, fabric_direct0_cfg_pad_i616, fabric_direct0_cfg_pad_i617, fabric_direct0_cfg_pad_i618, fabric_direct0_cfg_pad_i619, fabric_direct0_cfg_pad_i620, fabric_direct0_cfg_pad_i621, fabric_direct0_cfg_pad_i622, fabric_direct0_cfg_pad_i623, fabric_direct0_cfg_pad_i624, fabric_direct0_cfg_pad_i625, fabric_direct0_cfg_pad_i626, fabric_direct0_cfg_pad_i627, fabric_direct0_cfg_pad_i628, fabric_direct0_cfg_pad_i629, fabric_direct0_cfg_pad_i630, fabric_direct0_cfg_pad_i631
-, fabric_direct0_cfg_pad_i632, fabric_direct0_cfg_pad_i633, fabric_direct0_cfg_pad_i634, fabric_direct0_cfg_pad_i635, fabric_direct0_cfg_pad_i636, fabric_direct0_cfg_pad_i637, fabric_direct0_cfg_pad_i638, fabric_direct0_cfg_pad_i639, fabric_direct0_cfg_pad_i640, fabric_direct0_cfg_pad_i641, fabric_direct0_cfg_pad_i642, fabric_direct0_cfg_pad_i643, fabric_direct0_cfg_pad_i644, fabric_direct0_cfg_pad_i645, fabric_direct0_cfg_pad_i646, fabric_direct0_cfg_pad_i647, fabric_direct0_cfg_pad_i648, fabric_direct0_cfg_pad_i649, fabric_direct0_cfg_pad_i650, fabric_direct0_cfg_pad_i651, fabric_direct0_cfg_pad_i652
-, fabric_direct0_cfg_pad_i653, fabric_direct0_cfg_pad_i654, fabric_direct0_cfg_pad_i655, fabric_direct0_cfg_pad_i656, fabric_direct0_cfg_pad_i657, fabric_direct0_cfg_pad_i658, fabric_direct0_cfg_pad_i659, fabric_direct0_cfg_pad_i660, fabric_direct0_cfg_pad_i661, fabric_direct0_cfg_pad_i662, fabric_direct0_cfg_pad_i663, fabric_direct0_cfg_pad_i664, fabric_direct0_cfg_pad_i665, fabric_direct0_cfg_pad_i666, fabric_direct0_cfg_pad_i667, fabric_direct0_cfg_pad_i668, fabric_direct0_cfg_pad_i669, fabric_direct0_cfg_pad_i670, fabric_direct0_cfg_pad_i671, fabric_direct0_cfg_pad_i672, fabric_direct0_cfg_pad_i673
-, fabric_direct0_cfg_pad_i674, fabric_direct0_cfg_pad_i675, fabric_direct0_cfg_pad_i676, fabric_direct0_cfg_pad_i677, fabric_direct0_cfg_pad_i678, fabric_direct0_cfg_pad_i679, fabric_direct0_cfg_pad_i680, fabric_direct0_cfg_pad_i681, fabric_direct0_cfg_pad_i682, fabric_direct0_cfg_pad_i683, fabric_direct0_cfg_pad_i684, fabric_direct0_cfg_pad_i685, fabric_direct0_cfg_pad_i686, fabric_direct0_cfg_pad_i687, fabric_direct0_cfg_pad_i688, fabric_direct0_cfg_pad_i689, fabric_direct0_cfg_pad_i690, fabric_direct0_cfg_pad_i691, fabric_direct0_cfg_pad_i692, fabric_direct0_cfg_pad_i693, fabric_direct0_cfg_pad_i694
-, fabric_direct0_cfg_pad_i695, fabric_direct0_cfg_pad_i696, fabric_direct0_cfg_pad_i697, fabric_direct0_cfg_pad_i698, fabric_direct0_cfg_pad_i699, fabric_direct0_cfg_pad_i700, fabric_direct0_cfg_pad_i701, fabric_direct0_cfg_pad_i702, fabric_direct0_cfg_pad_i703, fabric_direct0_cfg_pad_i704, fabric_direct0_cfg_pad_i705, fabric_direct0_cfg_pad_i706, fabric_direct0_cfg_pad_i707, fabric_direct0_cfg_pad_i708, fabric_direct0_cfg_pad_i709, fabric_direct0_cfg_pad_i710, fabric_direct0_cfg_pad_i711, fabric_direct0_cfg_pad_i712, fabric_direct0_cfg_pad_i713, fabric_direct0_cfg_pad_i714, fabric_direct0_cfg_pad_i715
-, fabric_direct0_cfg_pad_i716, fabric_direct0_cfg_pad_i717, fabric_direct0_cfg_pad_i718, fabric_direct0_cfg_pad_i719, fabric_direct0_cfg_pad_i720, fabric_direct0_scan_en_i, fabric_direct0_loopback_en_i, fabric_direct0_loopback_mux_i, fabric_direct2_clock_fabric_i1, fabric_direct2_clock_fabric_i2, fabric_direct2_clock_fabric_i3, fabric_direct2_clock_fabric_i4, fabric_direct2_oe_i1, fabric_direct2_oe_i2, fabric_direct2_oe_i3, fabric_direct2_oe_i4, fabric_direct2_oe_i5, fabric_direct2_oe_i6, fabric_direct2_oe_i7, fabric_direct2_oe_i8, fabric_direct2_oe_i9
-, fabric_direct2_oe_i10, fabric_direct2_oe_i11, fabric_direct2_oe_i12, fabric_direct2_oe_i13, fabric_direct2_oe_i14, fabric_direct2_oe_i15, fabric_direct2_oe_i16, fabric_direct2_oe_i17, fabric_direct2_oe_i18, fabric_direct2_oe_i19, fabric_direct2_oe_i20, fabric_direct2_oe_i21, fabric_direct2_oe_i22, fabric_direct2_oe_i23, fabric_direct2_oe_i24, fabric_direct2_oe_ena_i1, fabric_direct2_oe_ena_i2, fabric_direct2_oe_ena_i3, fabric_direct2_oe_ena_i4, fabric_direct2_oe_ena_i5, fabric_direct2_oe_ena_i6
-, fabric_direct2_oe_ena_i7, fabric_direct2_oe_ena_i8, fabric_direct2_oe_ena_i9, fabric_direct2_oe_ena_i10, fabric_direct2_oe_ena_i11, fabric_direct2_oe_ena_i12, fabric_direct2_oe_ena_i13, fabric_direct2_oe_ena_i14, fabric_direct2_oe_ena_i15, fabric_direct2_oe_ena_i16, fabric_direct2_oe_ena_i17, fabric_direct2_oe_ena_i18, fabric_direct2_oe_ena_i19, fabric_direct2_oe_ena_i20, fabric_direct2_oe_ena_i21, fabric_direct2_oe_ena_i22, fabric_direct2_oe_ena_i23, fabric_direct2_oe_ena_i24, fabric_direct2_oe_rs_i1, fabric_direct2_oe_rs_i2, fabric_direct2_oe_rs_i3
-, fabric_direct2_oe_rs_i4, fabric_direct2_oe_rs_i5, fabric_direct2_oe_rs_i6, fabric_direct2_oe_rs_i7, fabric_direct2_oe_rs_i8, fabric_direct2_oe_rs_i9, fabric_direct2_oe_rs_i10, fabric_direct2_oe_rs_i11, fabric_direct2_oe_rs_i12, fabric_direct2_oe_rs_i13, fabric_direct2_oe_rs_i14, fabric_direct2_oe_rs_i15, fabric_direct2_oe_rs_i16, fabric_direct2_oe_rs_i17, fabric_direct2_oe_rs_i18, fabric_direct2_oe_rs_i19, fabric_direct2_oe_rs_i20, fabric_direct2_oe_rs_i21, fabric_direct2_oe_rs_i22, fabric_direct2_oe_rs_i23, fabric_direct2_oe_rs_i24
-, fabric_direct2_do_i1, fabric_direct2_do_i2, fabric_direct2_do_i3, fabric_direct2_do_i4, fabric_direct2_do_i5, fabric_direct2_do_i6, fabric_direct2_do_i7, fabric_direct2_do_i8, fabric_direct2_do_i9, fabric_direct2_do_i10, fabric_direct2_do_i11, fabric_direct2_do_i12, fabric_direct2_do_i13, fabric_direct2_do_i14, fabric_direct2_do_i15, fabric_direct2_do_i16, fabric_direct2_do_i17, fabric_direct2_do_i18, fabric_direct2_do_i19, fabric_direct2_do_i20, fabric_direct2_do_i21
-, fabric_direct2_do_i22, fabric_direct2_do_i23, fabric_direct2_do_i24, fabric_direct2_do_ena_i1, fabric_direct2_do_ena_i2, fabric_direct2_do_ena_i3, fabric_direct2_do_ena_i4, fabric_direct2_do_ena_i5, fabric_direct2_do_ena_i6, fabric_direct2_do_ena_i7, fabric_direct2_do_ena_i8, fabric_direct2_do_ena_i9, fabric_direct2_do_ena_i10, fabric_direct2_do_ena_i11, fabric_direct2_do_ena_i12, fabric_direct2_do_ena_i13, fabric_direct2_do_ena_i14, fabric_direct2_do_ena_i15, fabric_direct2_do_ena_i16, fabric_direct2_do_ena_i17, fabric_direct2_do_ena_i18
-, fabric_direct2_do_ena_i19, fabric_direct2_do_ena_i20, fabric_direct2_do_ena_i21, fabric_direct2_do_ena_i22, fabric_direct2_do_ena_i23, fabric_direct2_do_ena_i24, fabric_direct2_do_rs_i1, fabric_direct2_do_rs_i2, fabric_direct2_do_rs_i3, fabric_direct2_do_rs_i4, fabric_direct2_do_rs_i5, fabric_direct2_do_rs_i6, fabric_direct2_do_rs_i7, fabric_direct2_do_rs_i8, fabric_direct2_do_rs_i9, fabric_direct2_do_rs_i10, fabric_direct2_do_rs_i11, fabric_direct2_do_rs_i12, fabric_direct2_do_rs_i13, fabric_direct2_do_rs_i14, fabric_direct2_do_rs_i15
-, fabric_direct2_do_rs_i16, fabric_direct2_do_rs_i17, fabric_direct2_do_rs_i18, fabric_direct2_do_rs_i19, fabric_direct2_do_rs_i20, fabric_direct2_do_rs_i21, fabric_direct2_do_rs_i22, fabric_direct2_do_rs_i23, fabric_direct2_do_rs_i24, fabric_direct2_di_o1, fabric_direct2_di_o2, fabric_direct2_di_o3, fabric_direct2_di_o4, fabric_direct2_di_o5, fabric_direct2_di_o6, fabric_direct2_di_o7, fabric_direct2_di_o8, fabric_direct2_di_o9, fabric_direct2_di_o10, fabric_direct2_di_o11, fabric_direct2_di_o12
-, fabric_direct2_di_o13, fabric_direct2_di_o14, fabric_direct2_di_o15, fabric_direct2_di_o16, fabric_direct2_di_o17, fabric_direct2_di_o18, fabric_direct2_di_o19, fabric_direct2_di_o20, fabric_direct2_di_o21, fabric_direct2_di_o22, fabric_direct2_di_o23, fabric_direct2_di_o24, fabric_direct2_di_ena_i1, fabric_direct2_di_ena_i2, fabric_direct2_di_ena_i3, fabric_direct2_di_ena_i4, fabric_direct2_di_ena_i5, fabric_direct2_di_ena_i6, fabric_direct2_di_ena_i7, fabric_direct2_di_ena_i8, fabric_direct2_di_ena_i9
-, fabric_direct2_di_ena_i10, fabric_direct2_di_ena_i11, fabric_direct2_di_ena_i12, fabric_direct2_di_ena_i13, fabric_direct2_di_ena_i14, fabric_direct2_di_ena_i15, fabric_direct2_di_ena_i16, fabric_direct2_di_ena_i17, fabric_direct2_di_ena_i18, fabric_direct2_di_ena_i19, fabric_direct2_di_ena_i20, fabric_direct2_di_ena_i21, fabric_direct2_di_ena_i22, fabric_direct2_di_ena_i23, fabric_direct2_di_ena_i24, fabric_direct2_di_rs_i1, fabric_direct2_di_rs_i2, fabric_direct2_di_rs_i3, fabric_direct2_di_rs_i4, fabric_direct2_di_rs_i5, fabric_direct2_di_rs_i6
-, fabric_direct2_di_rs_i7, fabric_direct2_di_rs_i8, fabric_direct2_di_rs_i9, fabric_direct2_di_rs_i10, fabric_direct2_di_rs_i11, fabric_direct2_di_rs_i12, fabric_direct2_di_rs_i13, fabric_direct2_di_rs_i14, fabric_direct2_di_rs_i15, fabric_direct2_di_rs_i16, fabric_direct2_di_rs_i17, fabric_direct2_di_rs_i18, fabric_direct2_di_rs_i19, fabric_direct2_di_rs_i20, fabric_direct2_di_rs_i21, fabric_direct2_di_rs_i22, fabric_direct2_di_rs_i23, fabric_direct2_di_rs_i24, fabric_direct2_cfg_bank_i1, fabric_direct2_cfg_bank_i2, fabric_direct2_cfg_bank_i3
-, fabric_direct2_cfg_bank_i4, fabric_direct2_cfg_pad_i1, fabric_direct2_cfg_pad_i2, fabric_direct2_cfg_pad_i3, fabric_direct2_cfg_pad_i4, fabric_direct2_cfg_pad_i5, fabric_direct2_cfg_pad_i6, fabric_direct2_cfg_pad_i7, fabric_direct2_cfg_pad_i8, fabric_direct2_cfg_pad_i9, fabric_direct2_cfg_pad_i10, fabric_direct2_cfg_pad_i11, fabric_direct2_cfg_pad_i12, fabric_direct2_cfg_pad_i13, fabric_direct2_cfg_pad_i14, fabric_direct2_cfg_pad_i15, fabric_direct2_cfg_pad_i16, fabric_direct2_cfg_pad_i17, fabric_direct2_cfg_pad_i18, fabric_direct2_cfg_pad_i19, fabric_direct2_cfg_pad_i20
-, fabric_direct2_cfg_pad_i21, fabric_direct2_cfg_pad_i22, fabric_direct2_cfg_pad_i23, fabric_direct2_cfg_pad_i24, fabric_direct2_cfg_pad_i25, fabric_direct2_cfg_pad_i26, fabric_direct2_cfg_pad_i27, fabric_direct2_cfg_pad_i28, fabric_direct2_cfg_pad_i29, fabric_direct2_cfg_pad_i30, fabric_direct2_cfg_pad_i31, fabric_direct2_cfg_pad_i32, fabric_direct2_cfg_pad_i33, fabric_direct2_cfg_pad_i34, fabric_direct2_cfg_pad_i35, fabric_direct2_cfg_pad_i36, fabric_direct2_cfg_pad_i37, fabric_direct2_cfg_pad_i38, fabric_direct2_cfg_pad_i39, fabric_direct2_cfg_pad_i40, fabric_direct2_cfg_pad_i41
-, fabric_direct2_cfg_pad_i42, fabric_direct2_cfg_pad_i43, fabric_direct2_cfg_pad_i44, fabric_direct2_cfg_pad_i45, fabric_direct2_cfg_pad_i46, fabric_direct2_cfg_pad_i47, fabric_direct2_cfg_pad_i48, fabric_direct2_cfg_pad_i49, fabric_direct2_cfg_pad_i50, fabric_direct2_cfg_pad_i51, fabric_direct2_cfg_pad_i52, fabric_direct2_cfg_pad_i53, fabric_direct2_cfg_pad_i54, fabric_direct2_cfg_pad_i55, fabric_direct2_cfg_pad_i56, fabric_direct2_cfg_pad_i57, fabric_direct2_cfg_pad_i58, fabric_direct2_cfg_pad_i59, fabric_direct2_cfg_pad_i60, fabric_direct2_cfg_pad_i61, fabric_direct2_cfg_pad_i62
-, fabric_direct2_cfg_pad_i63, fabric_direct2_cfg_pad_i64, fabric_direct2_cfg_pad_i65, fabric_direct2_cfg_pad_i66, fabric_direct2_cfg_pad_i67, fabric_direct2_cfg_pad_i68, fabric_direct2_cfg_pad_i69, fabric_direct2_cfg_pad_i70, fabric_direct2_cfg_pad_i71, fabric_direct2_cfg_pad_i72, fabric_direct2_cfg_pad_i73, fabric_direct2_cfg_pad_i74, fabric_direct2_cfg_pad_i75, fabric_direct2_cfg_pad_i76, fabric_direct2_cfg_pad_i77, fabric_direct2_cfg_pad_i78, fabric_direct2_cfg_pad_i79, fabric_direct2_cfg_pad_i80, fabric_direct2_cfg_pad_i81, fabric_direct2_cfg_pad_i82, fabric_direct2_cfg_pad_i83
-, fabric_direct2_cfg_pad_i84, fabric_direct2_cfg_pad_i85, fabric_direct2_cfg_pad_i86, fabric_direct2_cfg_pad_i87, fabric_direct2_cfg_pad_i88, fabric_direct2_cfg_pad_i89, fabric_direct2_cfg_pad_i90, fabric_direct2_cfg_pad_i91, fabric_direct2_cfg_pad_i92, fabric_direct2_cfg_pad_i93, fabric_direct2_cfg_pad_i94, fabric_direct2_cfg_pad_i95, fabric_direct2_cfg_pad_i96, fabric_direct2_cfg_pad_i97, fabric_direct2_cfg_pad_i98, fabric_direct2_cfg_pad_i99, fabric_direct2_cfg_pad_i100, fabric_direct2_cfg_pad_i101, fabric_direct2_cfg_pad_i102, fabric_direct2_cfg_pad_i103, fabric_direct2_cfg_pad_i104
-, fabric_direct2_cfg_pad_i105, fabric_direct2_cfg_pad_i106, fabric_direct2_cfg_pad_i107, fabric_direct2_cfg_pad_i108, fabric_direct2_cfg_pad_i109, fabric_direct2_cfg_pad_i110, fabric_direct2_cfg_pad_i111, fabric_direct2_cfg_pad_i112, fabric_direct2_cfg_pad_i113, fabric_direct2_cfg_pad_i114, fabric_direct2_cfg_pad_i115, fabric_direct2_cfg_pad_i116, fabric_direct2_cfg_pad_i117, fabric_direct2_cfg_pad_i118, fabric_direct2_cfg_pad_i119, fabric_direct2_cfg_pad_i120, fabric_direct2_cfg_pad_i121, fabric_direct2_cfg_pad_i122, fabric_direct2_cfg_pad_i123, fabric_direct2_cfg_pad_i124, fabric_direct2_cfg_pad_i125
-, fabric_direct2_cfg_pad_i126, fabric_direct2_cfg_pad_i127, fabric_direct2_cfg_pad_i128, fabric_direct2_cfg_pad_i129, fabric_direct2_cfg_pad_i130, fabric_direct2_cfg_pad_i131, fabric_direct2_cfg_pad_i132, fabric_direct2_cfg_pad_i133, fabric_direct2_cfg_pad_i134, fabric_direct2_cfg_pad_i135, fabric_direct2_cfg_pad_i136, fabric_direct2_cfg_pad_i137, fabric_direct2_cfg_pad_i138, fabric_direct2_cfg_pad_i139, fabric_direct2_cfg_pad_i140, fabric_direct2_cfg_pad_i141, fabric_direct2_cfg_pad_i142, fabric_direct2_cfg_pad_i143, fabric_direct2_cfg_pad_i144, fabric_direct2_cfg_pad_i145, fabric_direct2_cfg_pad_i146
-, fabric_direct2_cfg_pad_i147, fabric_direct2_cfg_pad_i148, fabric_direct2_cfg_pad_i149, fabric_direct2_cfg_pad_i150, fabric_direct2_cfg_pad_i151, fabric_direct2_cfg_pad_i152, fabric_direct2_cfg_pad_i153, fabric_direct2_cfg_pad_i154, fabric_direct2_cfg_pad_i155, fabric_direct2_cfg_pad_i156, fabric_direct2_cfg_pad_i157, fabric_direct2_cfg_pad_i158, fabric_direct2_cfg_pad_i159, fabric_direct2_cfg_pad_i160, fabric_direct2_cfg_pad_i161, fabric_direct2_cfg_pad_i162, fabric_direct2_cfg_pad_i163, fabric_direct2_cfg_pad_i164, fabric_direct2_cfg_pad_i165, fabric_direct2_cfg_pad_i166, fabric_direct2_cfg_pad_i167
-, fabric_direct2_cfg_pad_i168, fabric_direct2_cfg_pad_i169, fabric_direct2_cfg_pad_i170, fabric_direct2_cfg_pad_i171, fabric_direct2_cfg_pad_i172, fabric_direct2_cfg_pad_i173, fabric_direct2_cfg_pad_i174, fabric_direct2_cfg_pad_i175, fabric_direct2_cfg_pad_i176, fabric_direct2_cfg_pad_i177, fabric_direct2_cfg_pad_i178, fabric_direct2_cfg_pad_i179, fabric_direct2_cfg_pad_i180, fabric_direct2_cfg_pad_i181, fabric_direct2_cfg_pad_i182, fabric_direct2_cfg_pad_i183, fabric_direct2_cfg_pad_i184, fabric_direct2_cfg_pad_i185, fabric_direct2_cfg_pad_i186, fabric_direct2_cfg_pad_i187, fabric_direct2_cfg_pad_i188
-, fabric_direct2_cfg_pad_i189, fabric_direct2_cfg_pad_i190, fabric_direct2_cfg_pad_i191, fabric_direct2_cfg_pad_i192, fabric_direct2_cfg_pad_i193, fabric_direct2_cfg_pad_i194, fabric_direct2_cfg_pad_i195, fabric_direct2_cfg_pad_i196, fabric_direct2_cfg_pad_i197, fabric_direct2_cfg_pad_i198, fabric_direct2_cfg_pad_i199, fabric_direct2_cfg_pad_i200, fabric_direct2_cfg_pad_i201, fabric_direct2_cfg_pad_i202, fabric_direct2_cfg_pad_i203, fabric_direct2_cfg_pad_i204, fabric_direct2_cfg_pad_i205, fabric_direct2_cfg_pad_i206, fabric_direct2_cfg_pad_i207, fabric_direct2_cfg_pad_i208, fabric_direct2_cfg_pad_i209
-, fabric_direct2_cfg_pad_i210, fabric_direct2_cfg_pad_i211, fabric_direct2_cfg_pad_i212, fabric_direct2_cfg_pad_i213, fabric_direct2_cfg_pad_i214, fabric_direct2_cfg_pad_i215, fabric_direct2_cfg_pad_i216, fabric_direct2_cfg_pad_i217, fabric_direct2_cfg_pad_i218, fabric_direct2_cfg_pad_i219, fabric_direct2_cfg_pad_i220, fabric_direct2_cfg_pad_i221, fabric_direct2_cfg_pad_i222, fabric_direct2_cfg_pad_i223, fabric_direct2_cfg_pad_i224, fabric_direct2_cfg_pad_i225, fabric_direct2_cfg_pad_i226, fabric_direct2_cfg_pad_i227, fabric_direct2_cfg_pad_i228, fabric_direct2_cfg_pad_i229, fabric_direct2_cfg_pad_i230
-, fabric_direct2_cfg_pad_i231, fabric_direct2_cfg_pad_i232, fabric_direct2_cfg_pad_i233, fabric_direct2_cfg_pad_i234, fabric_direct2_cfg_pad_i235, fabric_direct2_cfg_pad_i236, fabric_direct2_cfg_pad_i237, fabric_direct2_cfg_pad_i238, fabric_direct2_cfg_pad_i239, fabric_direct2_cfg_pad_i240, fabric_direct2_cfg_pad_i241, fabric_direct2_cfg_pad_i242, fabric_direct2_cfg_pad_i243, fabric_direct2_cfg_pad_i244, fabric_direct2_cfg_pad_i245, fabric_direct2_cfg_pad_i246, fabric_direct2_cfg_pad_i247, fabric_direct2_cfg_pad_i248, fabric_direct2_cfg_pad_i249, fabric_direct2_cfg_pad_i250, fabric_direct2_cfg_pad_i251
-, fabric_direct2_cfg_pad_i252, fabric_direct2_cfg_pad_i253, fabric_direct2_cfg_pad_i254, fabric_direct2_cfg_pad_i255, fabric_direct2_cfg_pad_i256, fabric_direct2_cfg_pad_i257, fabric_direct2_cfg_pad_i258, fabric_direct2_cfg_pad_i259, fabric_direct2_cfg_pad_i260, fabric_direct2_cfg_pad_i261, fabric_direct2_cfg_pad_i262, fabric_direct2_cfg_pad_i263, fabric_direct2_cfg_pad_i264, fabric_direct2_cfg_pad_i265, fabric_direct2_cfg_pad_i266, fabric_direct2_cfg_pad_i267, fabric_direct2_cfg_pad_i268, fabric_direct2_cfg_pad_i269, fabric_direct2_cfg_pad_i270, fabric_direct2_cfg_pad_i271, fabric_direct2_cfg_pad_i272
-, fabric_direct2_cfg_pad_i273, fabric_direct2_cfg_pad_i274, fabric_direct2_cfg_pad_i275, fabric_direct2_cfg_pad_i276, fabric_direct2_cfg_pad_i277, fabric_direct2_cfg_pad_i278, fabric_direct2_cfg_pad_i279, fabric_direct2_cfg_pad_i280, fabric_direct2_cfg_pad_i281, fabric_direct2_cfg_pad_i282, fabric_direct2_cfg_pad_i283, fabric_direct2_cfg_pad_i284, fabric_direct2_cfg_pad_i285, fabric_direct2_cfg_pad_i286, fabric_direct2_cfg_pad_i287, fabric_direct2_cfg_pad_i288, fabric_direct2_cfg_pad_i289, fabric_direct2_cfg_pad_i290, fabric_direct2_cfg_pad_i291, fabric_direct2_cfg_pad_i292, fabric_direct2_cfg_pad_i293
-, fabric_direct2_cfg_pad_i294, fabric_direct2_cfg_pad_i295, fabric_direct2_cfg_pad_i296, fabric_direct2_cfg_pad_i297, fabric_direct2_cfg_pad_i298, fabric_direct2_cfg_pad_i299, fabric_direct2_cfg_pad_i300, fabric_direct2_cfg_pad_i301, fabric_direct2_cfg_pad_i302, fabric_direct2_cfg_pad_i303, fabric_direct2_cfg_pad_i304, fabric_direct2_cfg_pad_i305, fabric_direct2_cfg_pad_i306, fabric_direct2_cfg_pad_i307, fabric_direct2_cfg_pad_i308, fabric_direct2_cfg_pad_i309, fabric_direct2_cfg_pad_i310, fabric_direct2_cfg_pad_i311, fabric_direct2_cfg_pad_i312, fabric_direct2_cfg_pad_i313, fabric_direct2_cfg_pad_i314
-, fabric_direct2_cfg_pad_i315, fabric_direct2_cfg_pad_i316, fabric_direct2_cfg_pad_i317, fabric_direct2_cfg_pad_i318, fabric_direct2_cfg_pad_i319, fabric_direct2_cfg_pad_i320, fabric_direct2_cfg_pad_i321, fabric_direct2_cfg_pad_i322, fabric_direct2_cfg_pad_i323, fabric_direct2_cfg_pad_i324, fabric_direct2_cfg_pad_i325, fabric_direct2_cfg_pad_i326, fabric_direct2_cfg_pad_i327, fabric_direct2_cfg_pad_i328, fabric_direct2_cfg_pad_i329, fabric_direct2_cfg_pad_i330, fabric_direct2_cfg_pad_i331, fabric_direct2_cfg_pad_i332, fabric_direct2_cfg_pad_i333, fabric_direct2_cfg_pad_i334, fabric_direct2_cfg_pad_i335
-, fabric_direct2_cfg_pad_i336, fabric_direct2_cfg_pad_i337, fabric_direct2_cfg_pad_i338, fabric_direct2_cfg_pad_i339, fabric_direct2_cfg_pad_i340, fabric_direct2_cfg_pad_i341, fabric_direct2_cfg_pad_i342, fabric_direct2_cfg_pad_i343, fabric_direct2_cfg_pad_i344, fabric_direct2_cfg_pad_i345, fabric_direct2_cfg_pad_i346, fabric_direct2_cfg_pad_i347, fabric_direct2_cfg_pad_i348, fabric_direct2_cfg_pad_i349, fabric_direct2_cfg_pad_i350, fabric_direct2_cfg_pad_i351, fabric_direct2_cfg_pad_i352, fabric_direct2_cfg_pad_i353, fabric_direct2_cfg_pad_i354, fabric_direct2_cfg_pad_i355, fabric_direct2_cfg_pad_i356
-, fabric_direct2_cfg_pad_i357, fabric_direct2_cfg_pad_i358, fabric_direct2_cfg_pad_i359, fabric_direct2_cfg_pad_i360, fabric_direct2_cfg_pad_i361, fabric_direct2_cfg_pad_i362, fabric_direct2_cfg_pad_i363, fabric_direct2_cfg_pad_i364, fabric_direct2_cfg_pad_i365, fabric_direct2_cfg_pad_i366, fabric_direct2_cfg_pad_i367, fabric_direct2_cfg_pad_i368, fabric_direct2_cfg_pad_i369, fabric_direct2_cfg_pad_i370, fabric_direct2_cfg_pad_i371, fabric_direct2_cfg_pad_i372, fabric_direct2_cfg_pad_i373, fabric_direct2_cfg_pad_i374, fabric_direct2_cfg_pad_i375, fabric_direct2_cfg_pad_i376, fabric_direct2_cfg_pad_i377
-, fabric_direct2_cfg_pad_i378, fabric_direct2_cfg_pad_i379, fabric_direct2_cfg_pad_i380, fabric_direct2_cfg_pad_i381, fabric_direct2_cfg_pad_i382, fabric_direct2_cfg_pad_i383, fabric_direct2_cfg_pad_i384, fabric_direct2_cfg_pad_i385, fabric_direct2_cfg_pad_i386, fabric_direct2_cfg_pad_i387, fabric_direct2_cfg_pad_i388, fabric_direct2_cfg_pad_i389, fabric_direct2_cfg_pad_i390, fabric_direct2_cfg_pad_i391, fabric_direct2_cfg_pad_i392, fabric_direct2_cfg_pad_i393, fabric_direct2_cfg_pad_i394, fabric_direct2_cfg_pad_i395, fabric_direct2_cfg_pad_i396, fabric_direct2_cfg_pad_i397, fabric_direct2_cfg_pad_i398
-, fabric_direct2_cfg_pad_i399, fabric_direct2_cfg_pad_i400, fabric_direct2_cfg_pad_i401, fabric_direct2_cfg_pad_i402, fabric_direct2_cfg_pad_i403, fabric_direct2_cfg_pad_i404, fabric_direct2_cfg_pad_i405, fabric_direct2_cfg_pad_i406, fabric_direct2_cfg_pad_i407, fabric_direct2_cfg_pad_i408, fabric_direct2_cfg_pad_i409, fabric_direct2_cfg_pad_i410, fabric_direct2_cfg_pad_i411, fabric_direct2_cfg_pad_i412, fabric_direct2_cfg_pad_i413, fabric_direct2_cfg_pad_i414, fabric_direct2_cfg_pad_i415, fabric_direct2_cfg_pad_i416, fabric_direct2_cfg_pad_i417, fabric_direct2_cfg_pad_i418, fabric_direct2_cfg_pad_i419
-, fabric_direct2_cfg_pad_i420, fabric_direct2_cfg_pad_i421, fabric_direct2_cfg_pad_i422, fabric_direct2_cfg_pad_i423, fabric_direct2_cfg_pad_i424, fabric_direct2_cfg_pad_i425, fabric_direct2_cfg_pad_i426, fabric_direct2_cfg_pad_i427, fabric_direct2_cfg_pad_i428, fabric_direct2_cfg_pad_i429, fabric_direct2_cfg_pad_i430, fabric_direct2_cfg_pad_i431, fabric_direct2_cfg_pad_i432, fabric_direct2_cfg_pad_i433, fabric_direct2_cfg_pad_i434, fabric_direct2_cfg_pad_i435, fabric_direct2_cfg_pad_i436, fabric_direct2_cfg_pad_i437, fabric_direct2_cfg_pad_i438, fabric_direct2_cfg_pad_i439, fabric_direct2_cfg_pad_i440
-, fabric_direct2_cfg_pad_i441, fabric_direct2_cfg_pad_i442, fabric_direct2_cfg_pad_i443, fabric_direct2_cfg_pad_i444, fabric_direct2_cfg_pad_i445, fabric_direct2_cfg_pad_i446, fabric_direct2_cfg_pad_i447, fabric_direct2_cfg_pad_i448, fabric_direct2_cfg_pad_i449, fabric_direct2_cfg_pad_i450, fabric_direct2_cfg_pad_i451, fabric_direct2_cfg_pad_i452, fabric_direct2_cfg_pad_i453, fabric_direct2_cfg_pad_i454, fabric_direct2_cfg_pad_i455, fabric_direct2_cfg_pad_i456, fabric_direct2_cfg_pad_i457, fabric_direct2_cfg_pad_i458, fabric_direct2_cfg_pad_i459, fabric_direct2_cfg_pad_i460, fabric_direct2_cfg_pad_i461
-, fabric_direct2_cfg_pad_i462, fabric_direct2_cfg_pad_i463, fabric_direct2_cfg_pad_i464, fabric_direct2_cfg_pad_i465, fabric_direct2_cfg_pad_i466, fabric_direct2_cfg_pad_i467, fabric_direct2_cfg_pad_i468, fabric_direct2_cfg_pad_i469, fabric_direct2_cfg_pad_i470, fabric_direct2_cfg_pad_i471, fabric_direct2_cfg_pad_i472, fabric_direct2_cfg_pad_i473, fabric_direct2_cfg_pad_i474, fabric_direct2_cfg_pad_i475, fabric_direct2_cfg_pad_i476, fabric_direct2_cfg_pad_i477, fabric_direct2_cfg_pad_i478, fabric_direct2_cfg_pad_i479, fabric_direct2_cfg_pad_i480, fabric_direct2_cfg_pad_i481, fabric_direct2_cfg_pad_i482
-, fabric_direct2_cfg_pad_i483, fabric_direct2_cfg_pad_i484, fabric_direct2_cfg_pad_i485, fabric_direct2_cfg_pad_i486, fabric_direct2_cfg_pad_i487, fabric_direct2_cfg_pad_i488, fabric_direct2_cfg_pad_i489, fabric_direct2_cfg_pad_i490, fabric_direct2_cfg_pad_i491, fabric_direct2_cfg_pad_i492, fabric_direct2_cfg_pad_i493, fabric_direct2_cfg_pad_i494, fabric_direct2_cfg_pad_i495, fabric_direct2_cfg_pad_i496, fabric_direct2_cfg_pad_i497, fabric_direct2_cfg_pad_i498, fabric_direct2_cfg_pad_i499, fabric_direct2_cfg_pad_i500, fabric_direct2_cfg_pad_i501, fabric_direct2_cfg_pad_i502, fabric_direct2_cfg_pad_i503
-, fabric_direct2_cfg_pad_i504, fabric_direct2_cfg_pad_i505, fabric_direct2_cfg_pad_i506, fabric_direct2_cfg_pad_i507, fabric_direct2_cfg_pad_i508, fabric_direct2_cfg_pad_i509, fabric_direct2_cfg_pad_i510, fabric_direct2_cfg_pad_i511, fabric_direct2_cfg_pad_i512, fabric_direct2_cfg_pad_i513, fabric_direct2_cfg_pad_i514, fabric_direct2_cfg_pad_i515, fabric_direct2_cfg_pad_i516, fabric_direct2_cfg_pad_i517, fabric_direct2_cfg_pad_i518, fabric_direct2_cfg_pad_i519, fabric_direct2_cfg_pad_i520, fabric_direct2_cfg_pad_i521, fabric_direct2_cfg_pad_i522, fabric_direct2_cfg_pad_i523, fabric_direct2_cfg_pad_i524
-, fabric_direct2_cfg_pad_i525, fabric_direct2_cfg_pad_i526, fabric_direct2_cfg_pad_i527, fabric_direct2_cfg_pad_i528, fabric_direct2_cfg_pad_i529, fabric_direct2_cfg_pad_i530, fabric_direct2_cfg_pad_i531, fabric_direct2_cfg_pad_i532, fabric_direct2_cfg_pad_i533, fabric_direct2_cfg_pad_i534, fabric_direct2_cfg_pad_i535, fabric_direct2_cfg_pad_i536, fabric_direct2_cfg_pad_i537, fabric_direct2_cfg_pad_i538, fabric_direct2_cfg_pad_i539, fabric_direct2_cfg_pad_i540, fabric_direct2_cfg_pad_i541, fabric_direct2_cfg_pad_i542, fabric_direct2_cfg_pad_i543, fabric_direct2_cfg_pad_i544, fabric_direct2_cfg_pad_i545
-, fabric_direct2_cfg_pad_i546, fabric_direct2_cfg_pad_i547, fabric_direct2_cfg_pad_i548, fabric_direct2_cfg_pad_i549, fabric_direct2_cfg_pad_i550, fabric_direct2_cfg_pad_i551, fabric_direct2_cfg_pad_i552, fabric_direct2_cfg_pad_i553, fabric_direct2_cfg_pad_i554, fabric_direct2_cfg_pad_i555, fabric_direct2_cfg_pad_i556, fabric_direct2_cfg_pad_i557, fabric_direct2_cfg_pad_i558, fabric_direct2_cfg_pad_i559, fabric_direct2_cfg_pad_i560, fabric_direct2_cfg_pad_i561, fabric_direct2_cfg_pad_i562, fabric_direct2_cfg_pad_i563, fabric_direct2_cfg_pad_i564, fabric_direct2_cfg_pad_i565, fabric_direct2_cfg_pad_i566
-, fabric_direct2_cfg_pad_i567, fabric_direct2_cfg_pad_i568, fabric_direct2_cfg_pad_i569, fabric_direct2_cfg_pad_i570, fabric_direct2_cfg_pad_i571, fabric_direct2_cfg_pad_i572, fabric_direct2_cfg_pad_i573, fabric_direct2_cfg_pad_i574, fabric_direct2_cfg_pad_i575, fabric_direct2_cfg_pad_i576, fabric_direct2_cfg_pad_i577, fabric_direct2_cfg_pad_i578, fabric_direct2_cfg_pad_i579, fabric_direct2_cfg_pad_i580, fabric_direct2_cfg_pad_i581, fabric_direct2_cfg_pad_i582, fabric_direct2_cfg_pad_i583, fabric_direct2_cfg_pad_i584, fabric_direct2_cfg_pad_i585, fabric_direct2_cfg_pad_i586, fabric_direct2_cfg_pad_i587
-, fabric_direct2_cfg_pad_i588, fabric_direct2_cfg_pad_i589, fabric_direct2_cfg_pad_i590, fabric_direct2_cfg_pad_i591, fabric_direct2_cfg_pad_i592, fabric_direct2_cfg_pad_i593, fabric_direct2_cfg_pad_i594, fabric_direct2_cfg_pad_i595, fabric_direct2_cfg_pad_i596, fabric_direct2_cfg_pad_i597, fabric_direct2_cfg_pad_i598, fabric_direct2_cfg_pad_i599, fabric_direct2_cfg_pad_i600, fabric_direct2_cfg_pad_i601, fabric_direct2_cfg_pad_i602, fabric_direct2_cfg_pad_i603, fabric_direct2_cfg_pad_i604, fabric_direct2_cfg_pad_i605, fabric_direct2_cfg_pad_i606, fabric_direct2_cfg_pad_i607, fabric_direct2_cfg_pad_i608
-, fabric_direct2_cfg_pad_i609, fabric_direct2_cfg_pad_i610, fabric_direct2_cfg_pad_i611, fabric_direct2_cfg_pad_i612, fabric_direct2_cfg_pad_i613, fabric_direct2_cfg_pad_i614, fabric_direct2_cfg_pad_i615, fabric_direct2_cfg_pad_i616, fabric_direct2_cfg_pad_i617, fabric_direct2_cfg_pad_i618, fabric_direct2_cfg_pad_i619, fabric_direct2_cfg_pad_i620, fabric_direct2_cfg_pad_i621, fabric_direct2_cfg_pad_i622, fabric_direct2_cfg_pad_i623, fabric_direct2_cfg_pad_i624, fabric_direct2_cfg_pad_i625, fabric_direct2_cfg_pad_i626, fabric_direct2_cfg_pad_i627, fabric_direct2_cfg_pad_i628, fabric_direct2_cfg_pad_i629
-, fabric_direct2_cfg_pad_i630, fabric_direct2_cfg_pad_i631, fabric_direct2_cfg_pad_i632, fabric_direct2_cfg_pad_i633, fabric_direct2_cfg_pad_i634, fabric_direct2_cfg_pad_i635, fabric_direct2_cfg_pad_i636, fabric_direct2_cfg_pad_i637, fabric_direct2_cfg_pad_i638, fabric_direct2_cfg_pad_i639, fabric_direct2_cfg_pad_i640, fabric_direct2_cfg_pad_i641, fabric_direct2_cfg_pad_i642, fabric_direct2_cfg_pad_i643, fabric_direct2_cfg_pad_i644, fabric_direct2_cfg_pad_i645, fabric_direct2_cfg_pad_i646, fabric_direct2_cfg_pad_i647, fabric_direct2_cfg_pad_i648, fabric_direct2_cfg_pad_i649, fabric_direct2_cfg_pad_i650
-, fabric_direct2_cfg_pad_i651, fabric_direct2_cfg_pad_i652, fabric_direct2_cfg_pad_i653, fabric_direct2_cfg_pad_i654, fabric_direct2_cfg_pad_i655, fabric_direct2_cfg_pad_i656, fabric_direct2_cfg_pad_i657, fabric_direct2_cfg_pad_i658, fabric_direct2_cfg_pad_i659, fabric_direct2_cfg_pad_i660, fabric_direct2_cfg_pad_i661, fabric_direct2_cfg_pad_i662, fabric_direct2_cfg_pad_i663, fabric_direct2_cfg_pad_i664, fabric_direct2_cfg_pad_i665, fabric_direct2_cfg_pad_i666, fabric_direct2_cfg_pad_i667, fabric_direct2_cfg_pad_i668, fabric_direct2_cfg_pad_i669, fabric_direct2_cfg_pad_i670, fabric_direct2_cfg_pad_i671
-, fabric_direct2_cfg_pad_i672, fabric_direct2_cfg_pad_i673, fabric_direct2_cfg_pad_i674, fabric_direct2_cfg_pad_i675, fabric_direct2_cfg_pad_i676, fabric_direct2_cfg_pad_i677, fabric_direct2_cfg_pad_i678, fabric_direct2_cfg_pad_i679, fabric_direct2_cfg_pad_i680, fabric_direct2_cfg_pad_i681, fabric_direct2_cfg_pad_i682, fabric_direct2_cfg_pad_i683, fabric_direct2_cfg_pad_i684, fabric_direct2_cfg_pad_i685, fabric_direct2_cfg_pad_i686, fabric_direct2_cfg_pad_i687, fabric_direct2_cfg_pad_i688, fabric_direct2_cfg_pad_i689, fabric_direct2_cfg_pad_i690, fabric_direct2_cfg_pad_i691, fabric_direct2_cfg_pad_i692
-, fabric_direct2_cfg_pad_i693, fabric_direct2_cfg_pad_i694, fabric_direct2_cfg_pad_i695, fabric_direct2_cfg_pad_i696, fabric_direct2_cfg_pad_i697, fabric_direct2_cfg_pad_i698, fabric_direct2_cfg_pad_i699, fabric_direct2_cfg_pad_i700, fabric_direct2_cfg_pad_i701, fabric_direct2_cfg_pad_i702, fabric_direct2_cfg_pad_i703, fabric_direct2_cfg_pad_i704, fabric_direct2_cfg_pad_i705, fabric_direct2_cfg_pad_i706, fabric_direct2_cfg_pad_i707, fabric_direct2_cfg_pad_i708, fabric_direct2_cfg_pad_i709, fabric_direct2_cfg_pad_i710, fabric_direct2_cfg_pad_i711, fabric_direct2_cfg_pad_i712, fabric_direct2_cfg_pad_i713
-, fabric_direct2_cfg_pad_i714, fabric_direct2_cfg_pad_i715, fabric_direct2_cfg_pad_i716, fabric_direct2_cfg_pad_i717, fabric_direct2_cfg_pad_i718, fabric_direct2_cfg_pad_i719, fabric_direct2_cfg_pad_i720, fabric_direct2_scan_en_i, fabric_direct2_loopback_en_i, fabric_direct2_loopback_mux_i, fabric_direct1_clock_fabric_i1, fabric_direct1_clock_fabric_i2, fabric_direct1_clock_fabric_i3, fabric_direct1_clock_fabric_i4, fabric_direct1_oe_i1, fabric_direct1_oe_i2, fabric_direct1_oe_i3, fabric_direct1_oe_i4, fabric_direct1_oe_i5, fabric_direct1_oe_i6, fabric_direct1_oe_i7
-, fabric_direct1_oe_i8, fabric_direct1_oe_i9, fabric_direct1_oe_i10, fabric_direct1_oe_i11, fabric_direct1_oe_i12, fabric_direct1_oe_i13, fabric_direct1_oe_i14, fabric_direct1_oe_i15, fabric_direct1_oe_i16, fabric_direct1_oe_ena_i1, fabric_direct1_oe_ena_i2, fabric_direct1_oe_ena_i3, fabric_direct1_oe_ena_i4, fabric_direct1_oe_ena_i5, fabric_direct1_oe_ena_i6, fabric_direct1_oe_ena_i7, fabric_direct1_oe_ena_i8, fabric_direct1_oe_ena_i9, fabric_direct1_oe_ena_i10, fabric_direct1_oe_ena_i11, fabric_direct1_oe_ena_i12
-, fabric_direct1_oe_ena_i13, fabric_direct1_oe_ena_i14, fabric_direct1_oe_ena_i15, fabric_direct1_oe_ena_i16, fabric_direct1_oe_rs_i1, fabric_direct1_oe_rs_i2, fabric_direct1_oe_rs_i3, fabric_direct1_oe_rs_i4, fabric_direct1_oe_rs_i5, fabric_direct1_oe_rs_i6, fabric_direct1_oe_rs_i7, fabric_direct1_oe_rs_i8, fabric_direct1_oe_rs_i9, fabric_direct1_oe_rs_i10, fabric_direct1_oe_rs_i11, fabric_direct1_oe_rs_i12, fabric_direct1_oe_rs_i13, fabric_direct1_oe_rs_i14, fabric_direct1_oe_rs_i15, fabric_direct1_oe_rs_i16, fabric_direct1_do_i1
-, fabric_direct1_do_i2, fabric_direct1_do_i3, fabric_direct1_do_i4, fabric_direct1_do_i5, fabric_direct1_do_i6, fabric_direct1_do_i7, fabric_direct1_do_i8, fabric_direct1_do_i9, fabric_direct1_do_i10, fabric_direct1_do_i11, fabric_direct1_do_i12, fabric_direct1_do_i13, fabric_direct1_do_i14, fabric_direct1_do_i15, fabric_direct1_do_i16, fabric_direct1_do_ena_i1, fabric_direct1_do_ena_i2, fabric_direct1_do_ena_i3, fabric_direct1_do_ena_i4, fabric_direct1_do_ena_i5, fabric_direct1_do_ena_i6
-, fabric_direct1_do_ena_i7, fabric_direct1_do_ena_i8, fabric_direct1_do_ena_i9, fabric_direct1_do_ena_i10, fabric_direct1_do_ena_i11, fabric_direct1_do_ena_i12, fabric_direct1_do_ena_i13, fabric_direct1_do_ena_i14, fabric_direct1_do_ena_i15, fabric_direct1_do_ena_i16, fabric_direct1_do_rs_i1, fabric_direct1_do_rs_i2, fabric_direct1_do_rs_i3, fabric_direct1_do_rs_i4, fabric_direct1_do_rs_i5, fabric_direct1_do_rs_i6, fabric_direct1_do_rs_i7, fabric_direct1_do_rs_i8, fabric_direct1_do_rs_i9, fabric_direct1_do_rs_i10, fabric_direct1_do_rs_i11
-, fabric_direct1_do_rs_i12, fabric_direct1_do_rs_i13, fabric_direct1_do_rs_i14, fabric_direct1_do_rs_i15, fabric_direct1_do_rs_i16, fabric_direct1_di_o1, fabric_direct1_di_o2, fabric_direct1_di_o3, fabric_direct1_di_o4, fabric_direct1_di_o5, fabric_direct1_di_o6, fabric_direct1_di_o7, fabric_direct1_di_o8, fabric_direct1_di_o9, fabric_direct1_di_o10, fabric_direct1_di_o11, fabric_direct1_di_o12, fabric_direct1_di_o13, fabric_direct1_di_o14, fabric_direct1_di_o15, fabric_direct1_di_o16
-, fabric_direct1_di_ena_i1, fabric_direct1_di_ena_i2, fabric_direct1_di_ena_i3, fabric_direct1_di_ena_i4, fabric_direct1_di_ena_i5, fabric_direct1_di_ena_i6, fabric_direct1_di_ena_i7, fabric_direct1_di_ena_i8, fabric_direct1_di_ena_i9, fabric_direct1_di_ena_i10, fabric_direct1_di_ena_i11, fabric_direct1_di_ena_i12, fabric_direct1_di_ena_i13, fabric_direct1_di_ena_i14, fabric_direct1_di_ena_i15, fabric_direct1_di_ena_i16, fabric_direct1_di_rs_i1, fabric_direct1_di_rs_i2, fabric_direct1_di_rs_i3, fabric_direct1_di_rs_i4, fabric_direct1_di_rs_i5
-, fabric_direct1_di_rs_i6, fabric_direct1_di_rs_i7, fabric_direct1_di_rs_i8, fabric_direct1_di_rs_i9, fabric_direct1_di_rs_i10, fabric_direct1_di_rs_i11, fabric_direct1_di_rs_i12, fabric_direct1_di_rs_i13, fabric_direct1_di_rs_i14, fabric_direct1_di_rs_i15, fabric_direct1_di_rs_i16, fabric_direct1_cfg_bank_i1, fabric_direct1_cfg_bank_i2, fabric_direct1_cfg_bank_i3, fabric_direct1_cfg_bank_i4, fabric_direct1_cfg_pad_i1, fabric_direct1_cfg_pad_i2, fabric_direct1_cfg_pad_i3, fabric_direct1_cfg_pad_i4, fabric_direct1_cfg_pad_i5, fabric_direct1_cfg_pad_i6
-, fabric_direct1_cfg_pad_i7, fabric_direct1_cfg_pad_i8, fabric_direct1_cfg_pad_i9, fabric_direct1_cfg_pad_i10, fabric_direct1_cfg_pad_i11, fabric_direct1_cfg_pad_i12, fabric_direct1_cfg_pad_i13, fabric_direct1_cfg_pad_i14, fabric_direct1_cfg_pad_i15, fabric_direct1_cfg_pad_i16, fabric_direct1_cfg_pad_i17, fabric_direct1_cfg_pad_i18, fabric_direct1_cfg_pad_i19, fabric_direct1_cfg_pad_i20, fabric_direct1_cfg_pad_i21, fabric_direct1_cfg_pad_i22, fabric_direct1_cfg_pad_i23, fabric_direct1_cfg_pad_i24, fabric_direct1_cfg_pad_i25, fabric_direct1_cfg_pad_i26, fabric_direct1_cfg_pad_i27
-, fabric_direct1_cfg_pad_i28, fabric_direct1_cfg_pad_i29, fabric_direct1_cfg_pad_i30, fabric_direct1_cfg_pad_i31, fabric_direct1_cfg_pad_i32, fabric_direct1_cfg_pad_i33, fabric_direct1_cfg_pad_i34, fabric_direct1_cfg_pad_i35, fabric_direct1_cfg_pad_i36, fabric_direct1_cfg_pad_i37, fabric_direct1_cfg_pad_i38, fabric_direct1_cfg_pad_i39, fabric_direct1_cfg_pad_i40, fabric_direct1_cfg_pad_i41, fabric_direct1_cfg_pad_i42, fabric_direct1_cfg_pad_i43, fabric_direct1_cfg_pad_i44, fabric_direct1_cfg_pad_i45, fabric_direct1_cfg_pad_i46, fabric_direct1_cfg_pad_i47, fabric_direct1_cfg_pad_i48
-, fabric_direct1_cfg_pad_i49, fabric_direct1_cfg_pad_i50, fabric_direct1_cfg_pad_i51, fabric_direct1_cfg_pad_i52, fabric_direct1_cfg_pad_i53, fabric_direct1_cfg_pad_i54, fabric_direct1_cfg_pad_i55, fabric_direct1_cfg_pad_i56, fabric_direct1_cfg_pad_i57, fabric_direct1_cfg_pad_i58, fabric_direct1_cfg_pad_i59, fabric_direct1_cfg_pad_i60, fabric_direct1_cfg_pad_i61, fabric_direct1_cfg_pad_i62, fabric_direct1_cfg_pad_i63, fabric_direct1_cfg_pad_i64, fabric_direct1_cfg_pad_i65, fabric_direct1_cfg_pad_i66, fabric_direct1_cfg_pad_i67, fabric_direct1_cfg_pad_i68, fabric_direct1_cfg_pad_i69
-, fabric_direct1_cfg_pad_i70, fabric_direct1_cfg_pad_i71, fabric_direct1_cfg_pad_i72, fabric_direct1_cfg_pad_i73, fabric_direct1_cfg_pad_i74, fabric_direct1_cfg_pad_i75, fabric_direct1_cfg_pad_i76, fabric_direct1_cfg_pad_i77, fabric_direct1_cfg_pad_i78, fabric_direct1_cfg_pad_i79, fabric_direct1_cfg_pad_i80, fabric_direct1_cfg_pad_i81, fabric_direct1_cfg_pad_i82, fabric_direct1_cfg_pad_i83, fabric_direct1_cfg_pad_i84, fabric_direct1_cfg_pad_i85, fabric_direct1_cfg_pad_i86, fabric_direct1_cfg_pad_i87, fabric_direct1_cfg_pad_i88, fabric_direct1_cfg_pad_i89, fabric_direct1_cfg_pad_i90
-, fabric_direct1_cfg_pad_i91, fabric_direct1_cfg_pad_i92, fabric_direct1_cfg_pad_i93, fabric_direct1_cfg_pad_i94, fabric_direct1_cfg_pad_i95, fabric_direct1_cfg_pad_i96, fabric_direct1_cfg_pad_i97, fabric_direct1_cfg_pad_i98, fabric_direct1_cfg_pad_i99, fabric_direct1_cfg_pad_i100, fabric_direct1_cfg_pad_i101, fabric_direct1_cfg_pad_i102, fabric_direct1_cfg_pad_i103, fabric_direct1_cfg_pad_i104, fabric_direct1_cfg_pad_i105, fabric_direct1_cfg_pad_i106, fabric_direct1_cfg_pad_i107, fabric_direct1_cfg_pad_i108, fabric_direct1_cfg_pad_i109, fabric_direct1_cfg_pad_i110, fabric_direct1_cfg_pad_i111
-, fabric_direct1_cfg_pad_i112, fabric_direct1_cfg_pad_i113, fabric_direct1_cfg_pad_i114, fabric_direct1_cfg_pad_i115, fabric_direct1_cfg_pad_i116, fabric_direct1_cfg_pad_i117, fabric_direct1_cfg_pad_i118, fabric_direct1_cfg_pad_i119, fabric_direct1_cfg_pad_i120, fabric_direct1_cfg_pad_i121, fabric_direct1_cfg_pad_i122, fabric_direct1_cfg_pad_i123, fabric_direct1_cfg_pad_i124, fabric_direct1_cfg_pad_i125, fabric_direct1_cfg_pad_i126, fabric_direct1_cfg_pad_i127, fabric_direct1_cfg_pad_i128, fabric_direct1_cfg_pad_i129, fabric_direct1_cfg_pad_i130, fabric_direct1_cfg_pad_i131, fabric_direct1_cfg_pad_i132
-, fabric_direct1_cfg_pad_i133, fabric_direct1_cfg_pad_i134, fabric_direct1_cfg_pad_i135, fabric_direct1_cfg_pad_i136, fabric_direct1_cfg_pad_i137, fabric_direct1_cfg_pad_i138, fabric_direct1_cfg_pad_i139, fabric_direct1_cfg_pad_i140, fabric_direct1_cfg_pad_i141, fabric_direct1_cfg_pad_i142, fabric_direct1_cfg_pad_i143, fabric_direct1_cfg_pad_i144, fabric_direct1_cfg_pad_i145, fabric_direct1_cfg_pad_i146, fabric_direct1_cfg_pad_i147, fabric_direct1_cfg_pad_i148, fabric_direct1_cfg_pad_i149, fabric_direct1_cfg_pad_i150, fabric_direct1_cfg_pad_i151, fabric_direct1_cfg_pad_i152, fabric_direct1_cfg_pad_i153
-, fabric_direct1_cfg_pad_i154, fabric_direct1_cfg_pad_i155, fabric_direct1_cfg_pad_i156, fabric_direct1_cfg_pad_i157, fabric_direct1_cfg_pad_i158, fabric_direct1_cfg_pad_i159, fabric_direct1_cfg_pad_i160, fabric_direct1_cfg_pad_i161, fabric_direct1_cfg_pad_i162, fabric_direct1_cfg_pad_i163, fabric_direct1_cfg_pad_i164, fabric_direct1_cfg_pad_i165, fabric_direct1_cfg_pad_i166, fabric_direct1_cfg_pad_i167, fabric_direct1_cfg_pad_i168, fabric_direct1_cfg_pad_i169, fabric_direct1_cfg_pad_i170, fabric_direct1_cfg_pad_i171, fabric_direct1_cfg_pad_i172, fabric_direct1_cfg_pad_i173, fabric_direct1_cfg_pad_i174
-, fabric_direct1_cfg_pad_i175, fabric_direct1_cfg_pad_i176, fabric_direct1_cfg_pad_i177, fabric_direct1_cfg_pad_i178, fabric_direct1_cfg_pad_i179, fabric_direct1_cfg_pad_i180, fabric_direct1_cfg_pad_i181, fabric_direct1_cfg_pad_i182, fabric_direct1_cfg_pad_i183, fabric_direct1_cfg_pad_i184, fabric_direct1_cfg_pad_i185, fabric_direct1_cfg_pad_i186, fabric_direct1_cfg_pad_i187, fabric_direct1_cfg_pad_i188, fabric_direct1_cfg_pad_i189, fabric_direct1_cfg_pad_i190, fabric_direct1_cfg_pad_i191, fabric_direct1_cfg_pad_i192, fabric_direct1_cfg_pad_i193, fabric_direct1_cfg_pad_i194, fabric_direct1_cfg_pad_i195
-, fabric_direct1_cfg_pad_i196, fabric_direct1_cfg_pad_i197, fabric_direct1_cfg_pad_i198, fabric_direct1_cfg_pad_i199, fabric_direct1_cfg_pad_i200, fabric_direct1_cfg_pad_i201, fabric_direct1_cfg_pad_i202, fabric_direct1_cfg_pad_i203, fabric_direct1_cfg_pad_i204, fabric_direct1_cfg_pad_i205, fabric_direct1_cfg_pad_i206, fabric_direct1_cfg_pad_i207, fabric_direct1_cfg_pad_i208, fabric_direct1_cfg_pad_i209, fabric_direct1_cfg_pad_i210, fabric_direct1_cfg_pad_i211, fabric_direct1_cfg_pad_i212, fabric_direct1_cfg_pad_i213, fabric_direct1_cfg_pad_i214, fabric_direct1_cfg_pad_i215, fabric_direct1_cfg_pad_i216
-, fabric_direct1_cfg_pad_i217, fabric_direct1_cfg_pad_i218, fabric_direct1_cfg_pad_i219, fabric_direct1_cfg_pad_i220, fabric_direct1_cfg_pad_i221, fabric_direct1_cfg_pad_i222, fabric_direct1_cfg_pad_i223, fabric_direct1_cfg_pad_i224, fabric_direct1_cfg_pad_i225, fabric_direct1_cfg_pad_i226, fabric_direct1_cfg_pad_i227, fabric_direct1_cfg_pad_i228, fabric_direct1_cfg_pad_i229, fabric_direct1_cfg_pad_i230, fabric_direct1_cfg_pad_i231, fabric_direct1_cfg_pad_i232, fabric_direct1_cfg_pad_i233, fabric_direct1_cfg_pad_i234, fabric_direct1_cfg_pad_i235, fabric_direct1_cfg_pad_i236, fabric_direct1_cfg_pad_i237
-, fabric_direct1_cfg_pad_i238, fabric_direct1_cfg_pad_i239, fabric_direct1_cfg_pad_i240, fabric_direct1_cfg_pad_i241, fabric_direct1_cfg_pad_i242, fabric_direct1_cfg_pad_i243, fabric_direct1_cfg_pad_i244, fabric_direct1_cfg_pad_i245, fabric_direct1_cfg_pad_i246, fabric_direct1_cfg_pad_i247, fabric_direct1_cfg_pad_i248, fabric_direct1_cfg_pad_i249, fabric_direct1_cfg_pad_i250, fabric_direct1_cfg_pad_i251, fabric_direct1_cfg_pad_i252, fabric_direct1_cfg_pad_i253, fabric_direct1_cfg_pad_i254, fabric_direct1_cfg_pad_i255, fabric_direct1_cfg_pad_i256, fabric_direct1_cfg_pad_i257, fabric_direct1_cfg_pad_i258
-, fabric_direct1_cfg_pad_i259, fabric_direct1_cfg_pad_i260, fabric_direct1_cfg_pad_i261, fabric_direct1_cfg_pad_i262, fabric_direct1_cfg_pad_i263, fabric_direct1_cfg_pad_i264, fabric_direct1_cfg_pad_i265, fabric_direct1_cfg_pad_i266, fabric_direct1_cfg_pad_i267, fabric_direct1_cfg_pad_i268, fabric_direct1_cfg_pad_i269, fabric_direct1_cfg_pad_i270, fabric_direct1_cfg_pad_i271, fabric_direct1_cfg_pad_i272, fabric_direct1_cfg_pad_i273, fabric_direct1_cfg_pad_i274, fabric_direct1_cfg_pad_i275, fabric_direct1_cfg_pad_i276, fabric_direct1_cfg_pad_i277, fabric_direct1_cfg_pad_i278, fabric_direct1_cfg_pad_i279
-, fabric_direct1_cfg_pad_i280, fabric_direct1_cfg_pad_i281, fabric_direct1_cfg_pad_i282, fabric_direct1_cfg_pad_i283, fabric_direct1_cfg_pad_i284, fabric_direct1_cfg_pad_i285, fabric_direct1_cfg_pad_i286, fabric_direct1_cfg_pad_i287, fabric_direct1_cfg_pad_i288, fabric_direct1_cfg_pad_i289, fabric_direct1_cfg_pad_i290, fabric_direct1_cfg_pad_i291, fabric_direct1_cfg_pad_i292, fabric_direct1_cfg_pad_i293, fabric_direct1_cfg_pad_i294, fabric_direct1_cfg_pad_i295, fabric_direct1_cfg_pad_i296, fabric_direct1_cfg_pad_i297, fabric_direct1_cfg_pad_i298, fabric_direct1_cfg_pad_i299, fabric_direct1_cfg_pad_i300
-, fabric_direct1_cfg_pad_i301, fabric_direct1_cfg_pad_i302, fabric_direct1_cfg_pad_i303, fabric_direct1_cfg_pad_i304, fabric_direct1_cfg_pad_i305, fabric_direct1_cfg_pad_i306, fabric_direct1_cfg_pad_i307, fabric_direct1_cfg_pad_i308, fabric_direct1_cfg_pad_i309, fabric_direct1_cfg_pad_i310, fabric_direct1_cfg_pad_i311, fabric_direct1_cfg_pad_i312, fabric_direct1_cfg_pad_i313, fabric_direct1_cfg_pad_i314, fabric_direct1_cfg_pad_i315, fabric_direct1_cfg_pad_i316, fabric_direct1_cfg_pad_i317, fabric_direct1_cfg_pad_i318, fabric_direct1_cfg_pad_i319, fabric_direct1_cfg_pad_i320, fabric_direct1_cfg_pad_i321
-, fabric_direct1_cfg_pad_i322, fabric_direct1_cfg_pad_i323, fabric_direct1_cfg_pad_i324, fabric_direct1_cfg_pad_i325, fabric_direct1_cfg_pad_i326, fabric_direct1_cfg_pad_i327, fabric_direct1_cfg_pad_i328, fabric_direct1_cfg_pad_i329, fabric_direct1_cfg_pad_i330, fabric_direct1_cfg_pad_i331, fabric_direct1_cfg_pad_i332, fabric_direct1_cfg_pad_i333, fabric_direct1_cfg_pad_i334, fabric_direct1_cfg_pad_i335, fabric_direct1_cfg_pad_i336, fabric_direct1_cfg_pad_i337, fabric_direct1_cfg_pad_i338, fabric_direct1_cfg_pad_i339, fabric_direct1_cfg_pad_i340, fabric_direct1_cfg_pad_i341, fabric_direct1_cfg_pad_i342
-, fabric_direct1_cfg_pad_i343, fabric_direct1_cfg_pad_i344, fabric_direct1_cfg_pad_i345, fabric_direct1_cfg_pad_i346, fabric_direct1_cfg_pad_i347, fabric_direct1_cfg_pad_i348, fabric_direct1_cfg_pad_i349, fabric_direct1_cfg_pad_i350, fabric_direct1_cfg_pad_i351, fabric_direct1_cfg_pad_i352, fabric_direct1_cfg_pad_i353, fabric_direct1_cfg_pad_i354, fabric_direct1_cfg_pad_i355, fabric_direct1_cfg_pad_i356, fabric_direct1_cfg_pad_i357, fabric_direct1_cfg_pad_i358, fabric_direct1_cfg_pad_i359, fabric_direct1_cfg_pad_i360, fabric_direct1_cfg_pad_i361, fabric_direct1_cfg_pad_i362, fabric_direct1_cfg_pad_i363
-, fabric_direct1_cfg_pad_i364, fabric_direct1_cfg_pad_i365, fabric_direct1_cfg_pad_i366, fabric_direct1_cfg_pad_i367, fabric_direct1_cfg_pad_i368, fabric_direct1_cfg_pad_i369, fabric_direct1_cfg_pad_i370, fabric_direct1_cfg_pad_i371, fabric_direct1_cfg_pad_i372, fabric_direct1_cfg_pad_i373, fabric_direct1_cfg_pad_i374, fabric_direct1_cfg_pad_i375, fabric_direct1_cfg_pad_i376, fabric_direct1_cfg_pad_i377, fabric_direct1_cfg_pad_i378, fabric_direct1_cfg_pad_i379, fabric_direct1_cfg_pad_i380, fabric_direct1_cfg_pad_i381, fabric_direct1_cfg_pad_i382, fabric_direct1_cfg_pad_i383, fabric_direct1_cfg_pad_i384
-, fabric_direct1_cfg_pad_i385, fabric_direct1_cfg_pad_i386, fabric_direct1_cfg_pad_i387, fabric_direct1_cfg_pad_i388, fabric_direct1_cfg_pad_i389, fabric_direct1_cfg_pad_i390, fabric_direct1_cfg_pad_i391, fabric_direct1_cfg_pad_i392, fabric_direct1_cfg_pad_i393, fabric_direct1_cfg_pad_i394, fabric_direct1_cfg_pad_i395, fabric_direct1_cfg_pad_i396, fabric_direct1_cfg_pad_i397, fabric_direct1_cfg_pad_i398, fabric_direct1_cfg_pad_i399, fabric_direct1_cfg_pad_i400, fabric_direct1_cfg_pad_i401, fabric_direct1_cfg_pad_i402, fabric_direct1_cfg_pad_i403, fabric_direct1_cfg_pad_i404, fabric_direct1_cfg_pad_i405
-, fabric_direct1_cfg_pad_i406, fabric_direct1_cfg_pad_i407, fabric_direct1_cfg_pad_i408, fabric_direct1_cfg_pad_i409, fabric_direct1_cfg_pad_i410, fabric_direct1_cfg_pad_i411, fabric_direct1_cfg_pad_i412, fabric_direct1_cfg_pad_i413, fabric_direct1_cfg_pad_i414, fabric_direct1_cfg_pad_i415, fabric_direct1_cfg_pad_i416, fabric_direct1_cfg_pad_i417, fabric_direct1_cfg_pad_i418, fabric_direct1_cfg_pad_i419, fabric_direct1_cfg_pad_i420, fabric_direct1_cfg_pad_i421, fabric_direct1_cfg_pad_i422, fabric_direct1_cfg_pad_i423, fabric_direct1_cfg_pad_i424, fabric_direct1_cfg_pad_i425, fabric_direct1_cfg_pad_i426
-, fabric_direct1_cfg_pad_i427, fabric_direct1_cfg_pad_i428, fabric_direct1_cfg_pad_i429, fabric_direct1_cfg_pad_i430, fabric_direct1_cfg_pad_i431, fabric_direct1_cfg_pad_i432, fabric_direct1_cfg_pad_i433, fabric_direct1_cfg_pad_i434, fabric_direct1_cfg_pad_i435, fabric_direct1_cfg_pad_i436, fabric_direct1_cfg_pad_i437, fabric_direct1_cfg_pad_i438, fabric_direct1_cfg_pad_i439, fabric_direct1_cfg_pad_i440, fabric_direct1_cfg_pad_i441, fabric_direct1_cfg_pad_i442, fabric_direct1_cfg_pad_i443, fabric_direct1_cfg_pad_i444, fabric_direct1_cfg_pad_i445, fabric_direct1_cfg_pad_i446, fabric_direct1_cfg_pad_i447
-, fabric_direct1_cfg_pad_i448, fabric_direct1_cfg_pad_i449, fabric_direct1_cfg_pad_i450, fabric_direct1_cfg_pad_i451, fabric_direct1_cfg_pad_i452, fabric_direct1_cfg_pad_i453, fabric_direct1_cfg_pad_i454, fabric_direct1_cfg_pad_i455, fabric_direct1_cfg_pad_i456, fabric_direct1_cfg_pad_i457, fabric_direct1_cfg_pad_i458, fabric_direct1_cfg_pad_i459, fabric_direct1_cfg_pad_i460, fabric_direct1_cfg_pad_i461, fabric_direct1_cfg_pad_i462, fabric_direct1_cfg_pad_i463, fabric_direct1_cfg_pad_i464, fabric_direct1_cfg_pad_i465, fabric_direct1_cfg_pad_i466, fabric_direct1_cfg_pad_i467, fabric_direct1_cfg_pad_i468
-, fabric_direct1_cfg_pad_i469, fabric_direct1_cfg_pad_i470, fabric_direct1_cfg_pad_i471, fabric_direct1_cfg_pad_i472, fabric_direct1_cfg_pad_i473, fabric_direct1_cfg_pad_i474, fabric_direct1_cfg_pad_i475, fabric_direct1_cfg_pad_i476, fabric_direct1_cfg_pad_i477, fabric_direct1_cfg_pad_i478, fabric_direct1_cfg_pad_i479, fabric_direct1_cfg_pad_i480, fabric_direct1_scan_en_i, fabric_direct1_loopback_en_i, fabric_direct1_loopback_mux_i, fabric_thsens_clk_i, fabric_thsens_arst_tmr_n_i1, fabric_thsens_arst_tmr_n_i2, fabric_thsens_arst_tmr_n_i3, fabric_thsens_fm_enable_i, fabric_thsens_fm_mode_w_i1
-, fabric_thsens_fm_mode_w_i2, fabric_thsens_fm_mode_w_i3, fabric_thsens_fm_mode_w_i4, fabric_thsens_fm_mode_w_i5, fabric_thsens_fm_mode_w_i6, fabric_thsens_fm_mode_w_i7, fabric_thsens_fm_mode_w_i8, fabric_thsens_fm_mode_w_i9, fabric_thsens_fm_mode_w_i10, fabric_thsens_fm_mode_w_i11, fabric_thsens_fm_mode_w_i12, fabric_thsens_fm_mode_w_i13, fabric_thsens_fm_mode_w_i14, fabric_thsens_fm_mode_w_i15, fabric_thsens_fm_mode_w_i16, fabric_thsens_fm_mode_w_i17, fabric_thsens_fm_mode_w_i18, fabric_thsens_fm_mode_w_i19, fabric_thsens_fm_mode_w_i20, fabric_thsens_fm_mode_w_i21, fabric_thsens_fm_mode_w_i22
-, fabric_thsens_fm_mode_w_i23, fabric_thsens_fm_mode_w_i24, fabric_thsens_fm_mode_w_i25, fabric_thsens_fm_mode_w_i26, fabric_thsens_fm_mode_w_i27, fabric_thsens_fm_mode_w_i28, fabric_thsens_fm_mode_w_i29, fabric_thsens_fm_mode_w_i30, fabric_thsens_fm_mode_w_i31, fabric_thsens_fm_mode_w_i32, fabric_thsens_fm_mode_wen_i, fabric_thsens_fm_config_w_i1, fabric_thsens_fm_config_w_i2, fabric_thsens_fm_config_w_i3, fabric_thsens_fm_config_w_i4, fabric_thsens_fm_config_w_i5, fabric_thsens_fm_config_w_i6, fabric_thsens_fm_config_w_i7, fabric_thsens_fm_config_w_i8, fabric_thsens_fm_config_w_i9, fabric_thsens_fm_config_w_i10
-, fabric_thsens_fm_config_w_i11, fabric_thsens_fm_config_w_i12, fabric_thsens_fm_config_w_i13, fabric_thsens_fm_config_w_i14, fabric_thsens_fm_config_w_i15, fabric_thsens_fm_config_w_i16, fabric_thsens_fm_config_w_i17, fabric_thsens_fm_config_w_i18, fabric_thsens_fm_config_w_i19, fabric_thsens_fm_config_w_i20, fabric_thsens_fm_config_w_i21, fabric_thsens_fm_config_w_i22, fabric_thsens_fm_config_w_i23, fabric_thsens_fm_config_w_i24, fabric_thsens_fm_config_w_i25, fabric_thsens_fm_config_w_i26, fabric_thsens_fm_config_w_i27, fabric_thsens_fm_config_wen_i, fabric_thsens_fm_data_o1, fabric_thsens_fm_data_o2, fabric_thsens_fm_data_o3
-, fabric_thsens_fm_data_o4, fabric_thsens_fm_data_o5, fabric_thsens_fm_data_o6, fabric_thsens_fm_data_o7, fabric_thsens_fm_data_o8, fabric_thsens_fm_data_o9, fabric_thsens_fm_data_o10, fabric_thsens_fm_data_o11, fabric_thsens_fm_data_o12, fabric_thsens_fm_data_o13, fabric_thsens_fm_data_o14, fabric_thsens_fm_valid_o, fabric_thsens_fm_overflow_o, fabric_thsens_fm_mode_r_o1, fabric_thsens_fm_mode_r_o2, fabric_thsens_fm_mode_r_o3, fabric_thsens_fm_mode_r_o4, fabric_thsens_fm_mode_r_o5, fabric_thsens_fm_mode_r_o6, fabric_thsens_fm_mode_r_o7, fabric_thsens_fm_mode_r_o8
-, fabric_thsens_fm_mode_r_o9, fabric_thsens_fm_mode_r_o10, fabric_thsens_fm_mode_r_o11, fabric_thsens_fm_mode_r_o12, fabric_thsens_fm_mode_r_o13, fabric_thsens_fm_mode_r_o14, fabric_thsens_fm_mode_r_o15, fabric_thsens_fm_mode_r_o16, fabric_thsens_fm_mode_r_o17, fabric_thsens_fm_mode_r_o18, fabric_thsens_fm_mode_r_o19, fabric_thsens_fm_mode_r_o20, fabric_thsens_fm_mode_r_o21, fabric_thsens_fm_mode_r_o22, fabric_thsens_fm_mode_r_o23, fabric_thsens_fm_mode_r_o24, fabric_thsens_fm_mode_r_o25, fabric_thsens_fm_mode_r_o26, fabric_thsens_fm_mode_r_o27, fabric_thsens_fm_mode_r_o28, fabric_thsens_fm_mode_r_o29
-, fabric_thsens_fm_mode_r_o30, fabric_thsens_fm_mode_r_o31, fabric_thsens_fm_mode_r_o32, fabric_thsens_fm_config_r_o1, fabric_thsens_fm_config_r_o2, fabric_thsens_fm_config_r_o3, fabric_thsens_fm_config_r_o4, fabric_thsens_fm_config_r_o5, fabric_thsens_fm_config_r_o6, fabric_thsens_fm_config_r_o7, fabric_thsens_fm_config_r_o8, fabric_thsens_fm_config_r_o9, fabric_thsens_fm_config_r_o10, fabric_thsens_fm_config_r_o11, fabric_thsens_fm_config_r_o12, fabric_thsens_fm_config_r_o13, fabric_thsens_fm_config_r_o14, fabric_thsens_fm_config_r_o15, fabric_thsens_fm_config_r_o16, fabric_thsens_fm_config_r_o17, fabric_thsens_fm_config_r_o18
-, fabric_thsens_fm_config_r_o19, fabric_thsens_fm_config_r_o20, fabric_thsens_fm_config_r_o21, fabric_thsens_fm_config_r_o22, fabric_thsens_fm_config_r_o23, fabric_thsens_fm_config_r_o24, fabric_thsens_fm_config_r_o25, fabric_thsens_fm_config_r_o26, fabric_thsens_fm_config_r_o27, fabric_thsens_clk_div_ratio_i1, fabric_thsens_clk_div_ratio_i2, fabric_thsens_clk_div_ratio_i3, fabric_thsens_clk_div_ratio_i4, fabric_thsens_clk_div_ratio_i5, fabric_thsens_clk_div_ratio_i6, fabric_thsens_clk_div_ratio_i7, fabric_thsens_clk_div_ratio_i8, fabric_thsens_tst_scanenable_i, fabric_thsens_tst_scanin1_i, fabric_thsens_tst_scanin2_i, fabric_thsens_tst_scanout1_o
-, fabric_thsens_tst_scanout2_o, fabric_thsens_otp_config_o1, fabric_thsens_otp_config_o2, fabric_thsens_otp_config_o3, fabric_thsens_otp_config_o4, fabric_thsens_otp_config_o5, fabric_thsens_otp_config_o6, fabric_thsens_otp_config_o7, fabric_thsens_otp_config_o8, fabric_thsens_otp_config_o9, fabric_thsens_otp_config_o10, fabric_thsens_otp_config_o11, fabric_thsens_otp_config_o12, fabric_thsens_otp_config_o13, fabric_thsens_otp_config_o14, fabric_thsens_otp_config_o15, fabric_thsens_otp_config_o16, fabric_thsens_otp_config_o17, fabric_thsens_otp_config_o18, fabric_thsens_otp_config_o19, fabric_thsens_otp_config_o20
-, fabric_thsens_otp_config_o21, fabric_thsens_otp_config_o22, fabric_thsens_otp_config_o23, fabric_thsens_otp_config_o24, fabric_thsens_otp_config_o25, fabric_thsens_otp_config_o26, fabric_thsens_otp_config_o27, fabric_spi_clk_i2, fabric_spi_sck_i2, fabric_spi_clk_i0, fabric_spi_sck_i0, fabric_spi_clk_i1, fabric_spi_sck_i1, fabric_spi_needed_i1, fabric_spi_needed_i2, fabric_spi_needed_i3, fabric_spi_bsm_release_o1, fabric_spi_bsm_release_o2, fabric_spi_bsm_release_o3, fabric_spi_arst_tmr_n_i1, fabric_spi_arst_tmr_n_i2
-, fabric_spi_arst_tmr_n_i3, fabric_spi_arst_tmr_n_i4, fabric_spi_arst_tmr_n_i5, fabric_spi_arst_tmr_n_i6, fabric_spi_arst_tmr_n_i7, fabric_spi_arst_tmr_n_i8, fabric_spi_arst_tmr_n_i9, fabric_spi_fifo_arst_tmr_n_i1, fabric_spi_fifo_arst_tmr_n_i2, fabric_spi_fifo_arst_tmr_n_i3, fabric_spi_fifo_arst_tmr_n_i4, fabric_spi_fifo_arst_tmr_n_i5, fabric_spi_fifo_arst_tmr_n_i6, fabric_spi_fifo_arst_tmr_n_i7, fabric_spi_fifo_arst_tmr_n_i8, fabric_spi_fifo_arst_tmr_n_i9, fabric_spi_cpol_i1, fabric_spi_cpol_i2, fabric_spi_cpol_i3, fabric_spi_cpha_i1, fabric_spi_cpha_i2
-, fabric_spi_cpha_i3, fabric_spi_loopback_i1, fabric_spi_loopback_i2, fabric_spi_loopback_i3, fabric_spi_lsb_first_i1, fabric_spi_lsb_first_i2, fabric_spi_lsb_first_i3, fabric_spi_cs_setuptime_i1, fabric_spi_cs_setuptime_i2, fabric_spi_cs_setuptime_i3, fabric_spi_cs_setuptime_i4, fabric_spi_cs_setuptime_i5, fabric_spi_cs_setuptime_i6, fabric_spi_cs_setuptime_i7, fabric_spi_cs_setuptime_i8, fabric_spi_cs_setuptime_i9, fabric_spi_cs_setuptime_i10, fabric_spi_cs_setuptime_i11, fabric_spi_cs_setuptime_i12, fabric_spi_cs_holdtime_i1, fabric_spi_cs_holdtime_i2
-, fabric_spi_cs_holdtime_i3, fabric_spi_cs_holdtime_i4, fabric_spi_cs_holdtime_i5, fabric_spi_cs_holdtime_i6, fabric_spi_cs_holdtime_i7, fabric_spi_cs_holdtime_i8, fabric_spi_cs_holdtime_i9, fabric_spi_cs_holdtime_i10, fabric_spi_cs_holdtime_i11, fabric_spi_cs_holdtime_i12, fabric_spi_cs_offtime_i1, fabric_spi_cs_offtime_i2, fabric_spi_cs_offtime_i3, fabric_spi_cs_offtime_i4, fabric_spi_cs_offtime_i5, fabric_spi_cs_offtime_i6, fabric_spi_cs_offtime_i7, fabric_spi_cs_offtime_i8, fabric_spi_cs_offtime_i9, fabric_spi_cs_offtime_i10, fabric_spi_cs_offtime_i11
-, fabric_spi_cs_offtime_i12, fabric_spi_vcc_enable_i1, fabric_spi_vcc_enable_i2, fabric_spi_vcc_enable_i3, fabric_spi_powerdown_cycle_i1, fabric_spi_powerdown_cycle_i2, fabric_spi_powerdown_cycle_i3, fabric_spi_powerdown_cycle_i4, fabric_spi_powerdown_cycle_i5, fabric_spi_powerdown_cycle_i6, fabric_spi_powerdown_cycle_i7, fabric_spi_powerdown_cycle_i8, fabric_spi_powerdown_cycle_i9, fabric_spi_powerdown_cycle_i10, fabric_spi_powerdown_cycle_i11, fabric_spi_powerdown_cycle_i12, fabric_spi_powerdown_cycle_i13, fabric_spi_powerdown_cycle_i14, fabric_spi_powerdown_cycle_i15, fabric_spi_powerdown_cycle_i16, fabric_spi_powerdown_cycle_i17
-, fabric_spi_powerdown_cycle_i18, fabric_spi_powerdown_cycle_i19, fabric_spi_powerdown_cycle_i20, fabric_spi_powerdown_cycle_i21, fabric_spi_powerdown_cycle_i22, fabric_spi_powerdown_cycle_i23, fabric_spi_powerdown_cycle_i24, fabric_spi_powerdown_cycle_i25, fabric_spi_powerdown_cycle_i26, fabric_spi_powerdown_cycle_i27, fabric_spi_powerdown_cycle_i28, fabric_spi_powerdown_cycle_i29, fabric_spi_powerdown_cycle_i30, fabric_spi_powerdown_cycle_i31, fabric_spi_powerdown_cycle_i32, fabric_spi_powerdown_cycle_i33, fabric_spi_powerdown_cycle_i34, fabric_spi_powerdown_cycle_i35, fabric_spi_powerdown_cycle_i36, fabric_spi_powerdown_cycle_i37, fabric_spi_powerdown_cycle_i38
-, fabric_spi_powerdown_cycle_i39, fabric_spi_powerdown_cycle_i40, fabric_spi_powerdown_cycle_i41, fabric_spi_powerdown_cycle_i42, fabric_spi_powerdown_cycle_i43, fabric_spi_powerdown_cycle_i44, fabric_spi_powerdown_cycle_i45, fabric_spi_powerdown_cycle_i46, fabric_spi_powerdown_cycle_i47, fabric_spi_powerdown_cycle_i48, fabric_spi_powerup_cycle_i1, fabric_spi_powerup_cycle_i2, fabric_spi_powerup_cycle_i3, fabric_spi_powerup_cycle_i4, fabric_spi_powerup_cycle_i5, fabric_spi_powerup_cycle_i6, fabric_spi_powerup_cycle_i7, fabric_spi_powerup_cycle_i8, fabric_spi_powerup_cycle_i9, fabric_spi_powerup_cycle_i10, fabric_spi_powerup_cycle_i11
-, fabric_spi_powerup_cycle_i12, fabric_spi_powerup_cycle_i13, fabric_spi_powerup_cycle_i14, fabric_spi_powerup_cycle_i15, fabric_spi_powerup_cycle_i16, fabric_spi_powerup_cycle_i17, fabric_spi_powerup_cycle_i18, fabric_spi_powerup_cycle_i19, fabric_spi_powerup_cycle_i20, fabric_spi_powerup_cycle_i21, fabric_spi_powerup_cycle_i22, fabric_spi_powerup_cycle_i23, fabric_spi_powerup_cycle_i24, fabric_spi_powerup_cycle_i25, fabric_spi_powerup_cycle_i26, fabric_spi_powerup_cycle_i27, fabric_spi_powerup_cycle_i28, fabric_spi_powerup_cycle_i29, fabric_spi_powerup_cycle_i30, fabric_spi_powerup_cycle_i31, fabric_spi_powerup_cycle_i32
-, fabric_spi_powerup_cycle_i33, fabric_spi_powerup_cycle_i34, fabric_spi_powerup_cycle_i35, fabric_spi_powerup_cycle_i36, fabric_spi_powerup_cycle_i37, fabric_spi_powerup_cycle_i38, fabric_spi_powerup_cycle_i39, fabric_spi_powerup_cycle_i40, fabric_spi_powerup_cycle_i41, fabric_spi_powerup_cycle_i42, fabric_spi_powerup_cycle_i43, fabric_spi_powerup_cycle_i44, fabric_spi_powerup_cycle_i45, fabric_spi_powerup_cycle_i46, fabric_spi_powerup_cycle_i47, fabric_spi_powerup_cycle_i48, fabric_spi_legacy_enable_i1, fabric_spi_legacy_enable_i2, fabric_spi_legacy_enable_i3, fabric_spi_legacy_master_i1, fabric_spi_legacy_master_i2
-, fabric_spi_legacy_master_i3, fabric_spi_data_in_unlimited_i1, fabric_spi_data_in_unlimited_i2, fabric_spi_data_in_unlimited_i3, fabric_spi_enable_i1, fabric_spi_enable_i2, fabric_spi_enable_i3, fabric_spi_rst_n_i1, fabric_spi_rst_n_i2, fabric_spi_rst_n_i3, fabric_spi_init_done_o1, fabric_spi_init_done_o2, fabric_spi_init_done_o3, fabric_spi_busy_o1, fabric_spi_busy_o2, fabric_spi_busy_o3, fabric_spi_vcc_used_o1, fabric_spi_vcc_used_o2, fabric_spi_vcc_used_o3, fabric_spi_error_sel_o1, fabric_spi_error_sel_o2
-, fabric_spi_error_sel_o3, fabric_spi_error_loopback_o1, fabric_spi_error_loopback_o2, fabric_spi_error_loopback_o3, fabric_spi_error_mode_o1, fabric_spi_error_mode_o2, fabric_spi_error_mode_o3, fabric_spi_error_endianness_o1, fabric_spi_error_endianness_o2, fabric_spi_error_endianness_o3, fabric_spi_cmd_push_i1, fabric_spi_cmd_push_i2, fabric_spi_cmd_push_i3, fabric_spi_cmd_full_o1, fabric_spi_cmd_full_o2, fabric_spi_cmd_full_o3, fabric_spi_cmd_type_i1, fabric_spi_cmd_type_i2, fabric_spi_cmd_type_i3, fabric_spi_cmd_type_i4, fabric_spi_cmd_type_i5
-, fabric_spi_cmd_type_i6, fabric_spi_cmd_mode_i1, fabric_spi_cmd_mode_i2, fabric_spi_cmd_mode_i3, fabric_spi_cmd_mode_i4, fabric_spi_cmd_mode_i5, fabric_spi_cmd_mode_i6, fabric_spi_cmd_bytes_i1, fabric_spi_cmd_bytes_i2, fabric_spi_cmd_bytes_i3, fabric_spi_cmd_bytes_i4, fabric_spi_cmd_bytes_i5, fabric_spi_cmd_bytes_i6, fabric_spi_mosi_push_i1, fabric_spi_mosi_push_i2, fabric_spi_mosi_push_i3, fabric_spi_mosi_full_o1, fabric_spi_mosi_full_o2, fabric_spi_mosi_full_o3, fabric_spi_mosi_data_i1, fabric_spi_mosi_data_i2
-, fabric_spi_mosi_data_i3, fabric_spi_mosi_data_i4, fabric_spi_mosi_data_i5, fabric_spi_mosi_data_i6, fabric_spi_mosi_data_i7, fabric_spi_mosi_data_i8, fabric_spi_mosi_data_i9, fabric_spi_mosi_data_i10, fabric_spi_mosi_data_i11, fabric_spi_mosi_data_i12, fabric_spi_mosi_data_i13, fabric_spi_mosi_data_i14, fabric_spi_mosi_data_i15, fabric_spi_mosi_data_i16, fabric_spi_mosi_data_i17, fabric_spi_mosi_data_i18, fabric_spi_mosi_data_i19, fabric_spi_mosi_data_i20, fabric_spi_mosi_data_i21, fabric_spi_mosi_data_i22, fabric_spi_mosi_data_i23
-, fabric_spi_mosi_data_i24, fabric_spi_mosi_data_inv_i1, fabric_spi_mosi_data_inv_i2, fabric_spi_mosi_data_inv_i3, fabric_spi_miso_pop_i1, fabric_spi_miso_pop_i2, fabric_spi_miso_pop_i3, fabric_spi_miso_empty_o1, fabric_spi_miso_empty_o2, fabric_spi_miso_empty_o3, fabric_spi_miso_data_o1, fabric_spi_miso_data_o2, fabric_spi_miso_data_o3, fabric_spi_miso_data_o4, fabric_spi_miso_data_o5, fabric_spi_miso_data_o6, fabric_spi_miso_data_o7, fabric_spi_miso_data_o8, fabric_spi_miso_data_o9, fabric_spi_miso_data_o10, fabric_spi_miso_data_o11
-, fabric_spi_miso_data_o12, fabric_spi_miso_data_o13, fabric_spi_miso_data_o14, fabric_spi_miso_data_o15, fabric_spi_miso_data_o16, fabric_spi_miso_data_o17, fabric_spi_miso_data_o18, fabric_spi_miso_data_o19, fabric_spi_miso_data_o20, fabric_spi_miso_data_o21, fabric_spi_miso_data_o22, fabric_spi_miso_data_o23, fabric_spi_miso_data_o24, fabric_spi_miso_data_inv_o1, fabric_spi_miso_data_inv_o2, fabric_spi_miso_data_inv_o3, fabric_spw0_clk_i, fabric_spw0_clk_tx_i, fabric_spw0_rst_n_i, fabric_spw0_user_shared_o, fabric_spw0_tx_fifo_write_i
-, fabric_spw0_tx_fifo_data_i1, fabric_spw0_tx_fifo_data_i2, fabric_spw0_tx_fifo_data_i3, fabric_spw0_tx_fifo_data_i4, fabric_spw0_tx_fifo_data_i5, fabric_spw0_tx_fifo_data_i6, fabric_spw0_tx_fifo_data_i7, fabric_spw0_tx_fifo_data_i8, fabric_spw0_tx_fifo_data_i9, fabric_spw0_tx_fifo_full_o, fabric_spw0_rx_fifo_read_i, fabric_spw0_rx_fifo_empty_o, fabric_spw0_rx_fifo_data_o1, fabric_spw0_rx_fifo_data_o2, fabric_spw0_rx_fifo_data_o3, fabric_spw0_rx_fifo_data_o4, fabric_spw0_rx_fifo_data_o5, fabric_spw0_rx_fifo_data_o6, fabric_spw0_rx_fifo_data_o7, fabric_spw0_rx_fifo_data_o8, fabric_spw0_rx_fifo_data_o9
-, fabric_spw0_tick_ctm_i, fabric_spw0_tick_ctm_o, fabric_spw0_apb_slv_psel_i, fabric_spw0_apb_slv_penable_i, fabric_spw0_apb_slv_paddr_i1, fabric_spw0_apb_slv_paddr_i2, fabric_spw0_apb_slv_paddr_i3, fabric_spw0_apb_slv_paddr_i4, fabric_spw0_apb_slv_paddr_i5, fabric_spw0_apb_slv_pwrite_i, fabric_spw0_apb_slv_pwdata_i1, fabric_spw0_apb_slv_pwdata_i2, fabric_spw0_apb_slv_pwdata_i3, fabric_spw0_apb_slv_pwdata_i4, fabric_spw0_apb_slv_pwdata_i5, fabric_spw0_apb_slv_pwdata_i6, fabric_spw0_apb_slv_pwdata_i7, fabric_spw0_apb_slv_pwdata_i8, fabric_spw0_apb_slv_pwdata_i9, fabric_spw0_apb_slv_pwdata_i10, fabric_spw0_apb_slv_pwdata_i11
-, fabric_spw0_apb_slv_pwdata_i12, fabric_spw0_apb_slv_pwdata_i13, fabric_spw0_apb_slv_pwdata_i14, fabric_spw0_apb_slv_pwdata_i15, fabric_spw0_apb_slv_pwdata_i16, fabric_spw0_apb_slv_pwdata_i17, fabric_spw0_apb_slv_pwdata_i18, fabric_spw0_apb_slv_pwdata_i19, fabric_spw0_apb_slv_pwdata_i20, fabric_spw0_apb_slv_pwdata_i21, fabric_spw0_apb_slv_pwdata_i22, fabric_spw0_apb_slv_pwdata_i23, fabric_spw0_apb_slv_pwdata_i24, fabric_spw0_apb_slv_pwdata_i25, fabric_spw0_apb_slv_pwdata_i26, fabric_spw0_apb_slv_pwdata_i27, fabric_spw0_apb_slv_pwdata_i28, fabric_spw0_apb_slv_pwdata_i29, fabric_spw0_apb_slv_pwdata_i30, fabric_spw0_apb_slv_pwdata_i31, fabric_spw0_apb_slv_prdata_o1
-, fabric_spw0_apb_slv_prdata_o2, fabric_spw0_apb_slv_prdata_o3, fabric_spw0_apb_slv_prdata_o4, fabric_spw0_apb_slv_prdata_o5, fabric_spw0_apb_slv_prdata_o6, fabric_spw0_apb_slv_prdata_o7, fabric_spw0_apb_slv_prdata_o8, fabric_spw0_apb_slv_prdata_o9, fabric_spw0_apb_slv_prdata_o10, fabric_spw0_apb_slv_prdata_o11, fabric_spw0_apb_slv_prdata_o12, fabric_spw0_apb_slv_prdata_o13, fabric_spw0_apb_slv_prdata_o14, fabric_spw0_apb_slv_prdata_o15, fabric_spw0_apb_slv_prdata_o16, fabric_spw0_apb_slv_prdata_o17, fabric_spw0_apb_slv_prdata_o18, fabric_spw0_apb_slv_prdata_o19, fabric_spw0_apb_slv_prdata_o20, fabric_spw0_apb_slv_prdata_o21, fabric_spw0_apb_slv_prdata_o22
-, fabric_spw0_apb_slv_prdata_o23, fabric_spw0_apb_slv_prdata_o24, fabric_spw0_apb_slv_prdata_o25, fabric_spw0_apb_slv_prdata_o26, fabric_spw0_apb_slv_prdata_o27, fabric_spw0_apb_slv_prdata_o28, fabric_spw0_apb_slv_prdata_o29, fabric_spw0_apb_slv_prdata_o30, fabric_spw0_apb_slv_prdata_o31, fabric_spw0_apb_slv_pready_o, fabric_spw0_apb_slv_pslverr_o, fabric_spw1_clk_i, fabric_spw1_clk_tx_i, fabric_spw1_rst_n_i, fabric_spw1_user_shared_o, fabric_spw1_tx_fifo_write_i, fabric_spw1_tx_fifo_data_i1, fabric_spw1_tx_fifo_data_i2, fabric_spw1_tx_fifo_data_i3, fabric_spw1_tx_fifo_data_i4, fabric_spw1_tx_fifo_data_i5
-, fabric_spw1_tx_fifo_data_i6, fabric_spw1_tx_fifo_data_i7, fabric_spw1_tx_fifo_data_i8, fabric_spw1_tx_fifo_data_i9, fabric_spw1_tx_fifo_full_o, fabric_spw1_rx_fifo_read_i, fabric_spw1_rx_fifo_empty_o, fabric_spw1_rx_fifo_data_o1, fabric_spw1_rx_fifo_data_o2, fabric_spw1_rx_fifo_data_o3, fabric_spw1_rx_fifo_data_o4, fabric_spw1_rx_fifo_data_o5, fabric_spw1_rx_fifo_data_o6, fabric_spw1_rx_fifo_data_o7, fabric_spw1_rx_fifo_data_o8, fabric_spw1_rx_fifo_data_o9, fabric_spw1_tick_ctm_i, fabric_spw1_tick_ctm_o, fabric_spw1_apb_slv_psel_i, fabric_spw1_apb_slv_penable_i, fabric_spw1_apb_slv_paddr_i1
-, fabric_spw1_apb_slv_paddr_i2, fabric_spw1_apb_slv_paddr_i3, fabric_spw1_apb_slv_paddr_i4, fabric_spw1_apb_slv_paddr_i5, fabric_spw1_apb_slv_pwrite_i, fabric_spw1_apb_slv_pwdata_i1, fabric_spw1_apb_slv_pwdata_i2, fabric_spw1_apb_slv_pwdata_i3, fabric_spw1_apb_slv_pwdata_i4, fabric_spw1_apb_slv_pwdata_i5, fabric_spw1_apb_slv_pwdata_i6, fabric_spw1_apb_slv_pwdata_i7, fabric_spw1_apb_slv_pwdata_i8, fabric_spw1_apb_slv_pwdata_i9, fabric_spw1_apb_slv_pwdata_i10, fabric_spw1_apb_slv_pwdata_i11, fabric_spw1_apb_slv_pwdata_i12, fabric_spw1_apb_slv_pwdata_i13, fabric_spw1_apb_slv_pwdata_i14, fabric_spw1_apb_slv_pwdata_i15, fabric_spw1_apb_slv_pwdata_i16
-, fabric_spw1_apb_slv_pwdata_i17, fabric_spw1_apb_slv_pwdata_i18, fabric_spw1_apb_slv_pwdata_i19, fabric_spw1_apb_slv_pwdata_i20, fabric_spw1_apb_slv_pwdata_i21, fabric_spw1_apb_slv_pwdata_i22, fabric_spw1_apb_slv_pwdata_i23, fabric_spw1_apb_slv_pwdata_i24, fabric_spw1_apb_slv_pwdata_i25, fabric_spw1_apb_slv_pwdata_i26, fabric_spw1_apb_slv_pwdata_i27, fabric_spw1_apb_slv_pwdata_i28, fabric_spw1_apb_slv_pwdata_i29, fabric_spw1_apb_slv_pwdata_i30, fabric_spw1_apb_slv_pwdata_i31, fabric_spw1_apb_slv_prdata_o1, fabric_spw1_apb_slv_prdata_o2, fabric_spw1_apb_slv_prdata_o3, fabric_spw1_apb_slv_prdata_o4, fabric_spw1_apb_slv_prdata_o5, fabric_spw1_apb_slv_prdata_o6
-, fabric_spw1_apb_slv_prdata_o7, fabric_spw1_apb_slv_prdata_o8, fabric_spw1_apb_slv_prdata_o9, fabric_spw1_apb_slv_prdata_o10, fabric_spw1_apb_slv_prdata_o11, fabric_spw1_apb_slv_prdata_o12, fabric_spw1_apb_slv_prdata_o13, fabric_spw1_apb_slv_prdata_o14, fabric_spw1_apb_slv_prdata_o15, fabric_spw1_apb_slv_prdata_o16, fabric_spw1_apb_slv_prdata_o17, fabric_spw1_apb_slv_prdata_o18, fabric_spw1_apb_slv_prdata_o19, fabric_spw1_apb_slv_prdata_o20, fabric_spw1_apb_slv_prdata_o21, fabric_spw1_apb_slv_prdata_o22, fabric_spw1_apb_slv_prdata_o23, fabric_spw1_apb_slv_prdata_o24, fabric_spw1_apb_slv_prdata_o25, fabric_spw1_apb_slv_prdata_o26, fabric_spw1_apb_slv_prdata_o27
-, fabric_spw1_apb_slv_prdata_o28, fabric_spw1_apb_slv_prdata_o29, fabric_spw1_apb_slv_prdata_o30, fabric_spw1_apb_slv_prdata_o31, fabric_spw1_apb_slv_pready_o, fabric_spw1_apb_slv_pslverr_o);
-    input fabric_adc0_arst_b_tmr_i1;
-    input fabric_adc0_arst_b_tmr_i2;
-    input fabric_adc0_arst_b_tmr_i3;
-    output fabric_adc0_cal_done_o;
-    output fabric_adc0_cal_n_overflow_o;
-    output fabric_adc0_cal_n_underflow_o;
-    output fabric_adc0_cal_p_overflow_o;
-    output fabric_adc0_cal_p_underflow_o;
-    input fabric_adc0_cal_start_i;
-    input fabric_adc0_clk_i;
-    input fabric_adc0_dbg_addr_i1;
-    input fabric_adc0_dbg_addr_i2;
-    input fabric_adc0_dbg_addr_i3;
-    input fabric_adc0_dbg_addr_i4;
-    output fabric_adc0_dbg_data_o1;
-    output fabric_adc0_dbg_data_o10;
-    output fabric_adc0_dbg_data_o11;
-    output fabric_adc0_dbg_data_o12;
-    output fabric_adc0_dbg_data_o13;
-    output fabric_adc0_dbg_data_o14;
-    output fabric_adc0_dbg_data_o15;
-    output fabric_adc0_dbg_data_o16;
-    output fabric_adc0_dbg_data_o17;
-    output fabric_adc0_dbg_data_o18;
-    output fabric_adc0_dbg_data_o19;
-    output fabric_adc0_dbg_data_o2;
-    output fabric_adc0_dbg_data_o20;
-    output fabric_adc0_dbg_data_o21;
-    output fabric_adc0_dbg_data_o22;
-    output fabric_adc0_dbg_data_o23;
-    output fabric_adc0_dbg_data_o24;
-    output fabric_adc0_dbg_data_o25;
-    output fabric_adc0_dbg_data_o26;
-    output fabric_adc0_dbg_data_o27;
-    output fabric_adc0_dbg_data_o28;
-    output fabric_adc0_dbg_data_o29;
-    output fabric_adc0_dbg_data_o3;
-    output fabric_adc0_dbg_data_o30;
-    output fabric_adc0_dbg_data_o31;
-    output fabric_adc0_dbg_data_o32;
-    output fabric_adc0_dbg_data_o4;
-    output fabric_adc0_dbg_data_o5;
-    output fabric_adc0_dbg_data_o6;
-    output fabric_adc0_dbg_data_o7;
-    output fabric_adc0_dbg_data_o8;
-    output fabric_adc0_dbg_data_o9;
-    input fabric_adc0_dft_scan_en_i;
-    input fabric_adc0_dft_si_i1;
-    input fabric_adc0_dft_si_i10;
-    input fabric_adc0_dft_si_i11;
-    input fabric_adc0_dft_si_i12;
-    input fabric_adc0_dft_si_i2;
-    input fabric_adc0_dft_si_i3;
-    input fabric_adc0_dft_si_i4;
-    input fabric_adc0_dft_si_i5;
-    input fabric_adc0_dft_si_i6;
-    input fabric_adc0_dft_si_i7;
-    input fabric_adc0_dft_si_i8;
-    input fabric_adc0_dft_si_i9;
-    input fabric_adc0_dft_test_mode_i1;
-    input fabric_adc0_dft_test_mode_i2;
-    input fabric_adc0_pwr_down_b_tmr_i1;
-    input fabric_adc0_pwr_down_b_tmr_i2;
-    input fabric_adc0_pwr_down_b_tmr_i3;
-    input fabric_adc0_spare_i1;
-    input fabric_adc0_spare_i10;
-    input fabric_adc0_spare_i11;
-    input fabric_adc0_spare_i12;
-    input fabric_adc0_spare_i13;
-    input fabric_adc0_spare_i14;
-    input fabric_adc0_spare_i15;
-    input fabric_adc0_spare_i16;
-    input fabric_adc0_spare_i2;
-    input fabric_adc0_spare_i3;
-    input fabric_adc0_spare_i4;
-    input fabric_adc0_spare_i5;
-    input fabric_adc0_spare_i6;
-    input fabric_adc0_spare_i7;
-    input fabric_adc0_spare_i8;
-    input fabric_adc0_spare_i9;
-    input fabric_adc0_usr_arst_b_tmr_i1;
-    input fabric_adc0_usr_arst_b_tmr_i2;
-    input fabric_adc0_usr_arst_b_tmr_i3;
-    input fabric_adc0_usr_channel_i1;
-    input fabric_adc0_usr_channel_i2;
-    input fabric_adc0_usr_channel_i3;
-    input fabric_adc0_usr_cke_i;
-    output fabric_adc0_usr_conv_done_o;
-    input fabric_adc0_usr_conv_start_i;
-    input fabric_adc0_usr_sample_lsb_i1;
-    input fabric_adc0_usr_sample_lsb_i2;
-    input fabric_adc0_usr_sample_lsb_i3;
-    input fabric_adc0_usr_sample_lsb_i4;
-    output fabric_adc0_usr_sample_o1;
-    output fabric_adc0_usr_sample_o10;
-    output fabric_adc0_usr_sample_o11;
-    output fabric_adc0_usr_sample_o12;
-    output fabric_adc0_usr_sample_o2;
-    output fabric_adc0_usr_sample_o3;
-    output fabric_adc0_usr_sample_o4;
-    output fabric_adc0_usr_sample_o5;
-    output fabric_adc0_usr_sample_o6;
-    output fabric_adc0_usr_sample_o7;
-    output fabric_adc0_usr_sample_o8;
-    output fabric_adc0_usr_sample_o9;
-    input fabric_adc1_arst_b_tmr_i1;
-    input fabric_adc1_arst_b_tmr_i2;
-    input fabric_adc1_arst_b_tmr_i3;
-    output fabric_adc1_cal_done_o;
-    output fabric_adc1_cal_n_overflow_o;
-    output fabric_adc1_cal_n_underflow_o;
-    output fabric_adc1_cal_p_overflow_o;
-    output fabric_adc1_cal_p_underflow_o;
-    input fabric_adc1_cal_start_i;
-    input fabric_adc1_clk_i;
-    input fabric_adc1_dbg_addr_i1;
-    input fabric_adc1_dbg_addr_i2;
-    input fabric_adc1_dbg_addr_i3;
-    input fabric_adc1_dbg_addr_i4;
-    output fabric_adc1_dbg_data_o1;
-    output fabric_adc1_dbg_data_o10;
-    output fabric_adc1_dbg_data_o11;
-    output fabric_adc1_dbg_data_o12;
-    output fabric_adc1_dbg_data_o13;
-    output fabric_adc1_dbg_data_o14;
-    output fabric_adc1_dbg_data_o15;
-    output fabric_adc1_dbg_data_o16;
-    output fabric_adc1_dbg_data_o17;
-    output fabric_adc1_dbg_data_o18;
-    output fabric_adc1_dbg_data_o19;
-    output fabric_adc1_dbg_data_o2;
-    output fabric_adc1_dbg_data_o20;
-    output fabric_adc1_dbg_data_o21;
-    output fabric_adc1_dbg_data_o22;
-    output fabric_adc1_dbg_data_o23;
-    output fabric_adc1_dbg_data_o24;
-    output fabric_adc1_dbg_data_o25;
-    output fabric_adc1_dbg_data_o26;
-    output fabric_adc1_dbg_data_o27;
-    output fabric_adc1_dbg_data_o28;
-    output fabric_adc1_dbg_data_o29;
-    output fabric_adc1_dbg_data_o3;
-    output fabric_adc1_dbg_data_o30;
-    output fabric_adc1_dbg_data_o31;
-    output fabric_adc1_dbg_data_o32;
-    output fabric_adc1_dbg_data_o4;
-    output fabric_adc1_dbg_data_o5;
-    output fabric_adc1_dbg_data_o6;
-    output fabric_adc1_dbg_data_o7;
-    output fabric_adc1_dbg_data_o8;
-    output fabric_adc1_dbg_data_o9;
-    input fabric_adc1_dft_scan_en_i;
-    input fabric_adc1_dft_si_i1;
-    input fabric_adc1_dft_si_i10;
-    input fabric_adc1_dft_si_i11;
-    input fabric_adc1_dft_si_i12;
-    input fabric_adc1_dft_si_i2;
-    input fabric_adc1_dft_si_i3;
-    input fabric_adc1_dft_si_i4;
-    input fabric_adc1_dft_si_i5;
-    input fabric_adc1_dft_si_i6;
-    input fabric_adc1_dft_si_i7;
-    input fabric_adc1_dft_si_i8;
-    input fabric_adc1_dft_si_i9;
-    input fabric_adc1_dft_test_mode_i1;
-    input fabric_adc1_dft_test_mode_i2;
-    input fabric_adc1_pwr_down_b_tmr_i1;
-    input fabric_adc1_pwr_down_b_tmr_i2;
-    input fabric_adc1_pwr_down_b_tmr_i3;
-    input fabric_adc1_spare_i1;
-    input fabric_adc1_spare_i10;
-    input fabric_adc1_spare_i11;
-    input fabric_adc1_spare_i12;
-    input fabric_adc1_spare_i13;
-    input fabric_adc1_spare_i14;
-    input fabric_adc1_spare_i15;
-    input fabric_adc1_spare_i16;
-    input fabric_adc1_spare_i2;
-    input fabric_adc1_spare_i3;
-    input fabric_adc1_spare_i4;
-    input fabric_adc1_spare_i5;
-    input fabric_adc1_spare_i6;
-    input fabric_adc1_spare_i7;
-    input fabric_adc1_spare_i8;
-    input fabric_adc1_spare_i9;
-    input fabric_adc1_usr_arst_b_tmr_i1;
-    input fabric_adc1_usr_arst_b_tmr_i2;
-    input fabric_adc1_usr_arst_b_tmr_i3;
-    input fabric_adc1_usr_channel_i1;
-    input fabric_adc1_usr_channel_i2;
-    input fabric_adc1_usr_channel_i3;
-    input fabric_adc1_usr_cke_i;
-    output fabric_adc1_usr_conv_done_o;
-    input fabric_adc1_usr_conv_start_i;
-    input fabric_adc1_usr_sample_lsb_i1;
-    input fabric_adc1_usr_sample_lsb_i2;
-    input fabric_adc1_usr_sample_lsb_i3;
-    input fabric_adc1_usr_sample_lsb_i4;
-    output fabric_adc1_usr_sample_o1;
-    output fabric_adc1_usr_sample_o10;
-    output fabric_adc1_usr_sample_o11;
-    output fabric_adc1_usr_sample_o12;
-    output fabric_adc1_usr_sample_o2;
-    output fabric_adc1_usr_sample_o3;
-    output fabric_adc1_usr_sample_o4;
-    output fabric_adc1_usr_sample_o5;
-    output fabric_adc1_usr_sample_o6;
-    output fabric_adc1_usr_sample_o7;
-    output fabric_adc1_usr_sample_o8;
-    output fabric_adc1_usr_sample_o9;
-    input fabric_adc2_arst_b_tmr_i1;
-    input fabric_adc2_arst_b_tmr_i2;
-    input fabric_adc2_arst_b_tmr_i3;
-    output fabric_adc2_cal_done_o;
-    output fabric_adc2_cal_n_overflow_o;
-    output fabric_adc2_cal_n_underflow_o;
-    output fabric_adc2_cal_p_overflow_o;
-    output fabric_adc2_cal_p_underflow_o;
-    input fabric_adc2_cal_start_i;
-    input fabric_adc2_clk_i;
-    input fabric_adc2_dbg_addr_i1;
-    input fabric_adc2_dbg_addr_i2;
-    input fabric_adc2_dbg_addr_i3;
-    input fabric_adc2_dbg_addr_i4;
-    output fabric_adc2_dbg_data_o1;
-    output fabric_adc2_dbg_data_o10;
-    output fabric_adc2_dbg_data_o11;
-    output fabric_adc2_dbg_data_o12;
-    output fabric_adc2_dbg_data_o13;
-    output fabric_adc2_dbg_data_o14;
-    output fabric_adc2_dbg_data_o15;
-    output fabric_adc2_dbg_data_o16;
-    output fabric_adc2_dbg_data_o17;
-    output fabric_adc2_dbg_data_o18;
-    output fabric_adc2_dbg_data_o19;
-    output fabric_adc2_dbg_data_o2;
-    output fabric_adc2_dbg_data_o20;
-    output fabric_adc2_dbg_data_o21;
-    output fabric_adc2_dbg_data_o22;
-    output fabric_adc2_dbg_data_o23;
-    output fabric_adc2_dbg_data_o24;
-    output fabric_adc2_dbg_data_o25;
-    output fabric_adc2_dbg_data_o26;
-    output fabric_adc2_dbg_data_o27;
-    output fabric_adc2_dbg_data_o28;
-    output fabric_adc2_dbg_data_o29;
-    output fabric_adc2_dbg_data_o3;
-    output fabric_adc2_dbg_data_o30;
-    output fabric_adc2_dbg_data_o31;
-    output fabric_adc2_dbg_data_o32;
-    output fabric_adc2_dbg_data_o4;
-    output fabric_adc2_dbg_data_o5;
-    output fabric_adc2_dbg_data_o6;
-    output fabric_adc2_dbg_data_o7;
-    output fabric_adc2_dbg_data_o8;
-    output fabric_adc2_dbg_data_o9;
-    input fabric_adc2_dft_scan_en_i;
-    input fabric_adc2_dft_si_i1;
-    input fabric_adc2_dft_si_i10;
-    input fabric_adc2_dft_si_i11;
-    input fabric_adc2_dft_si_i12;
-    input fabric_adc2_dft_si_i2;
-    input fabric_adc2_dft_si_i3;
-    input fabric_adc2_dft_si_i4;
-    input fabric_adc2_dft_si_i5;
-    input fabric_adc2_dft_si_i6;
-    input fabric_adc2_dft_si_i7;
-    input fabric_adc2_dft_si_i8;
-    input fabric_adc2_dft_si_i9;
-    input fabric_adc2_dft_test_mode_i1;
-    input fabric_adc2_dft_test_mode_i2;
-    input fabric_adc2_pwr_down_b_tmr_i1;
-    input fabric_adc2_pwr_down_b_tmr_i2;
-    input fabric_adc2_pwr_down_b_tmr_i3;
-    input fabric_adc2_spare_i1;
-    input fabric_adc2_spare_i10;
-    input fabric_adc2_spare_i11;
-    input fabric_adc2_spare_i12;
-    input fabric_adc2_spare_i13;
-    input fabric_adc2_spare_i14;
-    input fabric_adc2_spare_i15;
-    input fabric_adc2_spare_i16;
-    input fabric_adc2_spare_i2;
-    input fabric_adc2_spare_i3;
-    input fabric_adc2_spare_i4;
-    input fabric_adc2_spare_i5;
-    input fabric_adc2_spare_i6;
-    input fabric_adc2_spare_i7;
-    input fabric_adc2_spare_i8;
-    input fabric_adc2_spare_i9;
-    input fabric_adc2_usr_arst_b_tmr_i1;
-    input fabric_adc2_usr_arst_b_tmr_i2;
-    input fabric_adc2_usr_arst_b_tmr_i3;
-    input fabric_adc2_usr_channel_i1;
-    input fabric_adc2_usr_channel_i2;
-    input fabric_adc2_usr_channel_i3;
-    input fabric_adc2_usr_cke_i;
-    output fabric_adc2_usr_conv_done_o;
-    input fabric_adc2_usr_conv_start_i;
-    input fabric_adc2_usr_sample_lsb_i1;
-    input fabric_adc2_usr_sample_lsb_i2;
-    input fabric_adc2_usr_sample_lsb_i3;
-    input fabric_adc2_usr_sample_lsb_i4;
-    output fabric_adc2_usr_sample_o1;
-    output fabric_adc2_usr_sample_o10;
-    output fabric_adc2_usr_sample_o11;
-    output fabric_adc2_usr_sample_o12;
-    output fabric_adc2_usr_sample_o2;
-    output fabric_adc2_usr_sample_o3;
-    output fabric_adc2_usr_sample_o4;
-    output fabric_adc2_usr_sample_o5;
-    output fabric_adc2_usr_sample_o6;
-    output fabric_adc2_usr_sample_o7;
-    output fabric_adc2_usr_sample_o8;
-    output fabric_adc2_usr_sample_o9;
-    input fabric_adc3_arst_b_tmr_i1;
-    input fabric_adc3_arst_b_tmr_i2;
-    input fabric_adc3_arst_b_tmr_i3;
-    output fabric_adc3_cal_done_o;
-    output fabric_adc3_cal_n_overflow_o;
-    output fabric_adc3_cal_n_underflow_o;
-    output fabric_adc3_cal_p_overflow_o;
-    output fabric_adc3_cal_p_underflow_o;
-    input fabric_adc3_cal_start_i;
-    input fabric_adc3_clk_i;
-    input fabric_adc3_dbg_addr_i1;
-    input fabric_adc3_dbg_addr_i2;
-    input fabric_adc3_dbg_addr_i3;
-    input fabric_adc3_dbg_addr_i4;
-    output fabric_adc3_dbg_data_o1;
-    output fabric_adc3_dbg_data_o10;
-    output fabric_adc3_dbg_data_o11;
-    output fabric_adc3_dbg_data_o12;
-    output fabric_adc3_dbg_data_o13;
-    output fabric_adc3_dbg_data_o14;
-    output fabric_adc3_dbg_data_o15;
-    output fabric_adc3_dbg_data_o16;
-    output fabric_adc3_dbg_data_o17;
-    output fabric_adc3_dbg_data_o18;
-    output fabric_adc3_dbg_data_o19;
-    output fabric_adc3_dbg_data_o2;
-    output fabric_adc3_dbg_data_o20;
-    output fabric_adc3_dbg_data_o21;
-    output fabric_adc3_dbg_data_o22;
-    output fabric_adc3_dbg_data_o23;
-    output fabric_adc3_dbg_data_o24;
-    output fabric_adc3_dbg_data_o25;
-    output fabric_adc3_dbg_data_o26;
-    output fabric_adc3_dbg_data_o27;
-    output fabric_adc3_dbg_data_o28;
-    output fabric_adc3_dbg_data_o29;
-    output fabric_adc3_dbg_data_o3;
-    output fabric_adc3_dbg_data_o30;
-    output fabric_adc3_dbg_data_o31;
-    output fabric_adc3_dbg_data_o32;
-    output fabric_adc3_dbg_data_o4;
-    output fabric_adc3_dbg_data_o5;
-    output fabric_adc3_dbg_data_o6;
-    output fabric_adc3_dbg_data_o7;
-    output fabric_adc3_dbg_data_o8;
-    output fabric_adc3_dbg_data_o9;
-    input fabric_adc3_dft_scan_en_i;
-    input fabric_adc3_dft_si_i1;
-    input fabric_adc3_dft_si_i10;
-    input fabric_adc3_dft_si_i11;
-    input fabric_adc3_dft_si_i12;
-    input fabric_adc3_dft_si_i2;
-    input fabric_adc3_dft_si_i3;
-    input fabric_adc3_dft_si_i4;
-    input fabric_adc3_dft_si_i5;
-    input fabric_adc3_dft_si_i6;
-    input fabric_adc3_dft_si_i7;
-    input fabric_adc3_dft_si_i8;
-    input fabric_adc3_dft_si_i9;
-    input fabric_adc3_dft_test_mode_i1;
-    input fabric_adc3_dft_test_mode_i2;
-    input fabric_adc3_pwr_down_b_tmr_i1;
-    input fabric_adc3_pwr_down_b_tmr_i2;
-    input fabric_adc3_pwr_down_b_tmr_i3;
-    input fabric_adc3_spare_i1;
-    input fabric_adc3_spare_i10;
-    input fabric_adc3_spare_i11;
-    input fabric_adc3_spare_i12;
-    input fabric_adc3_spare_i13;
-    input fabric_adc3_spare_i14;
-    input fabric_adc3_spare_i15;
-    input fabric_adc3_spare_i16;
-    input fabric_adc3_spare_i2;
-    input fabric_adc3_spare_i3;
-    input fabric_adc3_spare_i4;
-    input fabric_adc3_spare_i5;
-    input fabric_adc3_spare_i6;
-    input fabric_adc3_spare_i7;
-    input fabric_adc3_spare_i8;
-    input fabric_adc3_spare_i9;
-    input fabric_adc3_usr_arst_b_tmr_i1;
-    input fabric_adc3_usr_arst_b_tmr_i2;
-    input fabric_adc3_usr_arst_b_tmr_i3;
-    input fabric_adc3_usr_channel_i1;
-    input fabric_adc3_usr_channel_i2;
-    input fabric_adc3_usr_channel_i3;
-    input fabric_adc3_usr_cke_i;
-    output fabric_adc3_usr_conv_done_o;
-    input fabric_adc3_usr_conv_start_i;
-    input fabric_adc3_usr_sample_lsb_i1;
-    input fabric_adc3_usr_sample_lsb_i2;
-    input fabric_adc3_usr_sample_lsb_i3;
-    input fabric_adc3_usr_sample_lsb_i4;
-    output fabric_adc3_usr_sample_o1;
-    output fabric_adc3_usr_sample_o10;
-    output fabric_adc3_usr_sample_o11;
-    output fabric_adc3_usr_sample_o12;
-    output fabric_adc3_usr_sample_o2;
-    output fabric_adc3_usr_sample_o3;
-    output fabric_adc3_usr_sample_o4;
-    output fabric_adc3_usr_sample_o5;
-    output fabric_adc3_usr_sample_o6;
-    output fabric_adc3_usr_sample_o7;
-    output fabric_adc3_usr_sample_o8;
-    output fabric_adc3_usr_sample_o9;
-    input fabric_cfg_adc0_clk_cal_div_ratio_i1;
-    input fabric_cfg_adc0_clk_cal_div_ratio_i2;
-    input fabric_cfg_adc0_clk_cal_div_ratio_i3;
-    input fabric_cfg_adc0_clk_cal_div_ratio_i4;
-    input fabric_cfg_adc0_clk_cal_div_ratio_i5;
-    input fabric_cfg_adc0_conv_done_delayed_i;
-    input fabric_cfg_adc0_use_cdc_i;
-    input fabric_cfg_adc1_clk_cal_div_ratio_i1;
-    input fabric_cfg_adc1_clk_cal_div_ratio_i2;
-    input fabric_cfg_adc1_clk_cal_div_ratio_i3;
-    input fabric_cfg_adc1_clk_cal_div_ratio_i4;
-    input fabric_cfg_adc1_clk_cal_div_ratio_i5;
-    input fabric_cfg_adc1_conv_done_delayed_i;
-    input fabric_cfg_adc1_use_cdc_i;
-    input fabric_cfg_adc2_clk_cal_div_ratio_i1;
-    input fabric_cfg_adc2_clk_cal_div_ratio_i2;
-    input fabric_cfg_adc2_clk_cal_div_ratio_i3;
-    input fabric_cfg_adc2_clk_cal_div_ratio_i4;
-    input fabric_cfg_adc2_clk_cal_div_ratio_i5;
-    input fabric_cfg_adc2_conv_done_delayed_i;
-    input fabric_cfg_adc2_use_cdc_i;
-    input fabric_cfg_adc3_clk_cal_div_ratio_i1;
-    input fabric_cfg_adc3_clk_cal_div_ratio_i2;
-    input fabric_cfg_adc3_clk_cal_div_ratio_i3;
-    input fabric_cfg_adc3_clk_cal_div_ratio_i4;
-    input fabric_cfg_adc3_clk_cal_div_ratio_i5;
-    input fabric_cfg_adc3_conv_done_delayed_i;
-    input fabric_cfg_adc3_use_cdc_i;
-    input fabric_cfg_dac0_reg_cm_select_i;
-    input fabric_cfg_dac0_reg_res_i1;
-    input fabric_cfg_dac0_reg_res_i2;
-    input fabric_cfg_dac0_reg_vref_select_i;
-    input fabric_cfg_dac0_sync_i;
-    input fabric_cfg_dac1_reg_cm_select_i;
-    input fabric_cfg_dac1_reg_res_i1;
-    input fabric_cfg_dac1_reg_res_i2;
-    input fabric_cfg_dac1_reg_vref_select_i;
-    input fabric_cfg_dac1_sync_i;
-    input fabric_cfg_dac2_reg_cm_select_i;
-    input fabric_cfg_dac2_reg_res_i1;
-    input fabric_cfg_dac2_reg_res_i2;
-    input fabric_cfg_dac2_reg_vref_select_i;
-    input fabric_cfg_dac2_sync_i;
-    input fabric_cfg_dac3_reg_cm_select_i;
-    input fabric_cfg_dac3_reg_res_i1;
-    input fabric_cfg_dac3_reg_res_i2;
-    input fabric_cfg_dac3_reg_vref_select_i;
-    input fabric_cfg_dac3_sync_i;
-    output fabric_cfg_fabric_user_enable_o;
-    output fabric_cfg_fabric_user_flag_o;
-    output fabric_clk_bsm_o;
-    output fabric_clk_otp_mrepair_o;
-    input fabric_clk_otp_mux_i;
-    output fabric_clk_otp_o;
-    output fabric_clk_user0_o;
-    output fabric_clk_user1_o;
-    input fabric_dac0_clk_en_i;
-    input fabric_dac0_clk_i;
-    input fabric_dac0_comp_en_i;
-    input fabric_dac0_comp_hyst_en_i;
-    input fabric_dac0_comp_in_sel_i1;
-    input fabric_dac0_comp_in_sel_i2;
-    input fabric_dac0_comp_in_sel_i3;
-    input fabric_dac0_comp_in_sel_i4;
-    output fabric_dac0_comp_out_o;
-    input fabric_dac0_comp_ref_sel_i;
-    input fabric_dac0_din_i1;
-    input fabric_dac0_din_i10;
-    input fabric_dac0_din_i11;
-    input fabric_dac0_din_i12;
-    input fabric_dac0_din_i13;
-    input fabric_dac0_din_i2;
-    input fabric_dac0_din_i3;
-    input fabric_dac0_din_i4;
-    input fabric_dac0_din_i5;
-    input fabric_dac0_din_i6;
-    input fabric_dac0_din_i7;
-    input fabric_dac0_din_i8;
-    input fabric_dac0_din_i9;
-    input fabric_dac0_filt_en_i;
-    input fabric_dac0_op_en_i;
-    input fabric_dac0_reg_pwr_down_n_i;
-    input fabric_dac0_rstn_i;
-    input fabric_dac1_clk_en_i;
-    input fabric_dac1_clk_i;
-    input fabric_dac1_comp_en_i;
-    input fabric_dac1_comp_hyst_en_i;
-    input fabric_dac1_comp_in_sel_i1;
-    input fabric_dac1_comp_in_sel_i2;
-    input fabric_dac1_comp_in_sel_i3;
-    input fabric_dac1_comp_in_sel_i4;
-    output fabric_dac1_comp_out_o;
-    input fabric_dac1_comp_ref_sel_i;
-    input fabric_dac1_din_i1;
-    input fabric_dac1_din_i10;
-    input fabric_dac1_din_i11;
-    input fabric_dac1_din_i12;
-    input fabric_dac1_din_i13;
-    input fabric_dac1_din_i2;
-    input fabric_dac1_din_i3;
-    input fabric_dac1_din_i4;
-    input fabric_dac1_din_i5;
-    input fabric_dac1_din_i6;
-    input fabric_dac1_din_i7;
-    input fabric_dac1_din_i8;
-    input fabric_dac1_din_i9;
-    input fabric_dac1_filt_en_i;
-    input fabric_dac1_op_en_i;
-    input fabric_dac1_reg_pwr_down_n_i;
-    input fabric_dac1_rstn_i;
-    input fabric_dac2_clk_en_i;
-    input fabric_dac2_clk_i;
-    input fabric_dac2_comp_en_i;
-    input fabric_dac2_comp_hyst_en_i;
-    input fabric_dac2_comp_in_sel_i1;
-    input fabric_dac2_comp_in_sel_i10;
-    input fabric_dac2_comp_in_sel_i11;
-    input fabric_dac2_comp_in_sel_i12;
-    input fabric_dac2_comp_in_sel_i13;
-    input fabric_dac2_comp_in_sel_i2;
-    input fabric_dac2_comp_in_sel_i3;
-    input fabric_dac2_comp_in_sel_i4;
-    input fabric_dac2_comp_in_sel_i5;
-    input fabric_dac2_comp_in_sel_i6;
-    input fabric_dac2_comp_in_sel_i7;
-    input fabric_dac2_comp_in_sel_i8;
-    input fabric_dac2_comp_in_sel_i9;
-    output fabric_dac2_comp_out_o;
-    input fabric_dac2_comp_ref_sel_i;
-    input fabric_dac2_din_i1;
-    input fabric_dac2_din_i10;
-    input fabric_dac2_din_i11;
-    input fabric_dac2_din_i12;
-    input fabric_dac2_din_i13;
-    input fabric_dac2_din_i2;
-    input fabric_dac2_din_i3;
-    input fabric_dac2_din_i4;
-    input fabric_dac2_din_i5;
-    input fabric_dac2_din_i6;
-    input fabric_dac2_din_i7;
-    input fabric_dac2_din_i8;
-    input fabric_dac2_din_i9;
-    input fabric_dac2_filt_en_i;
-    input fabric_dac2_op_en_i;
-    input fabric_dac2_reg_pwr_down_n_i;
-    input fabric_dac2_rstn_i;
-    input fabric_dac3_clk_en_i;
-    input fabric_dac3_clk_i;
-    input fabric_dac3_comp_en_i;
-    input fabric_dac3_comp_hyst_en_i;
-    input fabric_dac3_comp_in_sel_i1;
-    input fabric_dac3_comp_in_sel_i2;
-    input fabric_dac3_comp_in_sel_i3;
-    input fabric_dac3_comp_in_sel_i4;
-    output fabric_dac3_comp_out_o;
-    input fabric_dac3_comp_ref_sel_i;
-    input fabric_dac3_din_i1;
-    input fabric_dac3_din_i10;
-    input fabric_dac3_din_i11;
-    input fabric_dac3_din_i12;
-    input fabric_dac3_din_i13;
-    input fabric_dac3_din_i2;
-    input fabric_dac3_din_i3;
-    input fabric_dac3_din_i4;
-    input fabric_dac3_din_i5;
-    input fabric_dac3_din_i6;
-    input fabric_dac3_din_i7;
-    input fabric_dac3_din_i8;
-    input fabric_dac3_din_i9;
-    input fabric_dac3_filt_en_i;
-    input fabric_dac3_op_en_i;
-    input fabric_dac3_reg_pwr_down_n_i;
-    input fabric_dac3_rstn_i;
-    output fabric_debug_access_reg_data_ready_o;
-    output fabric_debug_bsec_core_status_o1;
-    output fabric_debug_bsec_core_status_o10;
-    output fabric_debug_bsec_core_status_o11;
-    output fabric_debug_bsec_core_status_o12;
-    output fabric_debug_bsec_core_status_o13;
-    output fabric_debug_bsec_core_status_o14;
-    output fabric_debug_bsec_core_status_o15;
-    output fabric_debug_bsec_core_status_o16;
-    output fabric_debug_bsec_core_status_o17;
-    output fabric_debug_bsec_core_status_o18;
-    output fabric_debug_bsec_core_status_o19;
-    output fabric_debug_bsec_core_status_o2;
-    output fabric_debug_bsec_core_status_o20;
-    output fabric_debug_bsec_core_status_o21;
-    output fabric_debug_bsec_core_status_o22;
-    output fabric_debug_bsec_core_status_o23;
-    output fabric_debug_bsec_core_status_o24;
-    output fabric_debug_bsec_core_status_o25;
-    output fabric_debug_bsec_core_status_o26;
-    output fabric_debug_bsec_core_status_o27;
-    output fabric_debug_bsec_core_status_o28;
-    output fabric_debug_bsec_core_status_o29;
-    output fabric_debug_bsec_core_status_o3;
-    output fabric_debug_bsec_core_status_o30;
-    output fabric_debug_bsec_core_status_o31;
-    output fabric_debug_bsec_core_status_o32;
-    output fabric_debug_bsec_core_status_o4;
-    output fabric_debug_bsec_core_status_o5;
-    output fabric_debug_bsec_core_status_o6;
-    output fabric_debug_bsec_core_status_o7;
-    output fabric_debug_bsec_core_status_o8;
-    output fabric_debug_bsec_core_status_o9;
-    output fabric_debug_cpt_retry_o1;
-    output fabric_debug_cpt_retry_o2;
-    output fabric_debug_cpt_retry_o3;
-    output fabric_debug_cpt_retry_o4;
-    output fabric_debug_direct_permission_read_o1;
-    output fabric_debug_direct_permission_read_o2;
-    output fabric_debug_direct_permission_read_o3;
-    output fabric_debug_direct_permission_read_o4;
-    output fabric_debug_direct_permission_write_o1;
-    output fabric_debug_direct_permission_write_o2;
-    output fabric_debug_direct_permission_write_o3;
-    output fabric_debug_direct_permission_write_o4;
-    output fabric_debug_error_o;
-    output fabric_debug_frame_permission_frame_o1;
-    output fabric_debug_frame_permission_frame_o2;
-    output fabric_debug_frame_permission_frame_o3;
-    output fabric_debug_frame_permission_frame_o4;
-    output fabric_debug_frame_use_encryption_o;
-    output fabric_debug_fsm_state_o1;
-    output fabric_debug_fsm_state_o2;
-    output fabric_debug_fsm_state_o3;
-    output fabric_debug_key_correct_o;
-    output fabric_debug_lifecycle_o1;
-    output fabric_debug_lifecycle_o2;
-    output fabric_debug_lifecycle_o3;
-    output fabric_debug_lifecycle_o4;
-    output fabric_debug_lock_reg_o;
-    output fabric_debug_otp_manager_read_done_o;
-    output fabric_debug_otp_manager_read_otp_o;
-    output fabric_debug_otp_reload_err_o;
-    output fabric_debug_otpapb_state_o1;
-    output fabric_debug_otpapb_state_o2;
-    output fabric_debug_otpapb_state_o3;
-    output fabric_debug_otpboot_curr_addr_o1;
-    output fabric_debug_otpboot_curr_addr_o2;
-    output fabric_debug_otpboot_curr_addr_o3;
-    output fabric_debug_otpboot_curr_addr_o4;
-    output fabric_debug_otpboot_curr_addr_o5;
-    output fabric_debug_otpboot_curr_addr_o6;
-    output fabric_debug_otpboot_curr_addr_o7;
-    output fabric_debug_otpboot_curr_addr_o8;
-    output fabric_debug_otpboot_state_o1;
-    output fabric_debug_otpboot_state_o2;
-    output fabric_debug_otpboot_state_o3;
-    output fabric_debug_otpmgmt_state_o1;
-    output fabric_debug_otpmgmt_state_o2;
-    output fabric_debug_otpmgmt_state_o3;
-    output fabric_debug_rst_soft_o;
-    output fabric_debug_security_boot_done_o;
-    output fabric_debug_security_error_read_o;
-    input fabric_direct0_cfg_bank_i1;
-    input fabric_direct0_cfg_bank_i2;
-    input fabric_direct0_cfg_bank_i3;
-    input fabric_direct0_cfg_bank_i4;
-    input fabric_direct0_cfg_pad_i1;
-    input fabric_direct0_cfg_pad_i10;
-    input fabric_direct0_cfg_pad_i100;
-    input fabric_direct0_cfg_pad_i101;
-    input fabric_direct0_cfg_pad_i102;
-    input fabric_direct0_cfg_pad_i103;
-    input fabric_direct0_cfg_pad_i104;
-    input fabric_direct0_cfg_pad_i105;
-    input fabric_direct0_cfg_pad_i106;
-    input fabric_direct0_cfg_pad_i107;
-    input fabric_direct0_cfg_pad_i108;
-    input fabric_direct0_cfg_pad_i109;
-    input fabric_direct0_cfg_pad_i11;
-    input fabric_direct0_cfg_pad_i110;
-    input fabric_direct0_cfg_pad_i111;
-    input fabric_direct0_cfg_pad_i112;
-    input fabric_direct0_cfg_pad_i113;
-    input fabric_direct0_cfg_pad_i114;
-    input fabric_direct0_cfg_pad_i115;
-    input fabric_direct0_cfg_pad_i116;
-    input fabric_direct0_cfg_pad_i117;
-    input fabric_direct0_cfg_pad_i118;
-    input fabric_direct0_cfg_pad_i119;
-    input fabric_direct0_cfg_pad_i12;
-    input fabric_direct0_cfg_pad_i120;
-    input fabric_direct0_cfg_pad_i121;
-    input fabric_direct0_cfg_pad_i122;
-    input fabric_direct0_cfg_pad_i123;
-    input fabric_direct0_cfg_pad_i124;
-    input fabric_direct0_cfg_pad_i125;
-    input fabric_direct0_cfg_pad_i126;
-    input fabric_direct0_cfg_pad_i127;
-    input fabric_direct0_cfg_pad_i128;
-    input fabric_direct0_cfg_pad_i129;
-    input fabric_direct0_cfg_pad_i13;
-    input fabric_direct0_cfg_pad_i130;
-    input fabric_direct0_cfg_pad_i131;
-    input fabric_direct0_cfg_pad_i132;
-    input fabric_direct0_cfg_pad_i133;
-    input fabric_direct0_cfg_pad_i134;
-    input fabric_direct0_cfg_pad_i135;
-    input fabric_direct0_cfg_pad_i136;
-    input fabric_direct0_cfg_pad_i137;
-    input fabric_direct0_cfg_pad_i138;
-    input fabric_direct0_cfg_pad_i139;
-    input fabric_direct0_cfg_pad_i14;
-    input fabric_direct0_cfg_pad_i140;
-    input fabric_direct0_cfg_pad_i141;
-    input fabric_direct0_cfg_pad_i142;
-    input fabric_direct0_cfg_pad_i143;
-    input fabric_direct0_cfg_pad_i144;
-    input fabric_direct0_cfg_pad_i145;
-    input fabric_direct0_cfg_pad_i146;
-    input fabric_direct0_cfg_pad_i147;
-    input fabric_direct0_cfg_pad_i148;
-    input fabric_direct0_cfg_pad_i149;
-    input fabric_direct0_cfg_pad_i15;
-    input fabric_direct0_cfg_pad_i150;
-    input fabric_direct0_cfg_pad_i151;
-    input fabric_direct0_cfg_pad_i152;
-    input fabric_direct0_cfg_pad_i153;
-    input fabric_direct0_cfg_pad_i154;
-    input fabric_direct0_cfg_pad_i155;
-    input fabric_direct0_cfg_pad_i156;
-    input fabric_direct0_cfg_pad_i157;
-    input fabric_direct0_cfg_pad_i158;
-    input fabric_direct0_cfg_pad_i159;
-    input fabric_direct0_cfg_pad_i16;
-    input fabric_direct0_cfg_pad_i160;
-    input fabric_direct0_cfg_pad_i161;
-    input fabric_direct0_cfg_pad_i162;
-    input fabric_direct0_cfg_pad_i163;
-    input fabric_direct0_cfg_pad_i164;
-    input fabric_direct0_cfg_pad_i165;
-    input fabric_direct0_cfg_pad_i166;
-    input fabric_direct0_cfg_pad_i167;
-    input fabric_direct0_cfg_pad_i168;
-    input fabric_direct0_cfg_pad_i169;
-    input fabric_direct0_cfg_pad_i17;
-    input fabric_direct0_cfg_pad_i170;
-    input fabric_direct0_cfg_pad_i171;
-    input fabric_direct0_cfg_pad_i172;
-    input fabric_direct0_cfg_pad_i173;
-    input fabric_direct0_cfg_pad_i174;
-    input fabric_direct0_cfg_pad_i175;
-    input fabric_direct0_cfg_pad_i176;
-    input fabric_direct0_cfg_pad_i177;
-    input fabric_direct0_cfg_pad_i178;
-    input fabric_direct0_cfg_pad_i179;
-    input fabric_direct0_cfg_pad_i18;
-    input fabric_direct0_cfg_pad_i180;
-    input fabric_direct0_cfg_pad_i181;
-    input fabric_direct0_cfg_pad_i182;
-    input fabric_direct0_cfg_pad_i183;
-    input fabric_direct0_cfg_pad_i184;
-    input fabric_direct0_cfg_pad_i185;
-    input fabric_direct0_cfg_pad_i186;
-    input fabric_direct0_cfg_pad_i187;
-    input fabric_direct0_cfg_pad_i188;
-    input fabric_direct0_cfg_pad_i189;
-    input fabric_direct0_cfg_pad_i19;
-    input fabric_direct0_cfg_pad_i190;
-    input fabric_direct0_cfg_pad_i191;
-    input fabric_direct0_cfg_pad_i192;
-    input fabric_direct0_cfg_pad_i193;
-    input fabric_direct0_cfg_pad_i194;
-    input fabric_direct0_cfg_pad_i195;
-    input fabric_direct0_cfg_pad_i196;
-    input fabric_direct0_cfg_pad_i197;
-    input fabric_direct0_cfg_pad_i198;
-    input fabric_direct0_cfg_pad_i199;
-    input fabric_direct0_cfg_pad_i2;
-    input fabric_direct0_cfg_pad_i20;
-    input fabric_direct0_cfg_pad_i200;
-    input fabric_direct0_cfg_pad_i201;
-    input fabric_direct0_cfg_pad_i202;
-    input fabric_direct0_cfg_pad_i203;
-    input fabric_direct0_cfg_pad_i204;
-    input fabric_direct0_cfg_pad_i205;
-    input fabric_direct0_cfg_pad_i206;
-    input fabric_direct0_cfg_pad_i207;
-    input fabric_direct0_cfg_pad_i208;
-    input fabric_direct0_cfg_pad_i209;
-    input fabric_direct0_cfg_pad_i21;
-    input fabric_direct0_cfg_pad_i210;
-    input fabric_direct0_cfg_pad_i211;
-    input fabric_direct0_cfg_pad_i212;
-    input fabric_direct0_cfg_pad_i213;
-    input fabric_direct0_cfg_pad_i214;
-    input fabric_direct0_cfg_pad_i215;
-    input fabric_direct0_cfg_pad_i216;
-    input fabric_direct0_cfg_pad_i217;
-    input fabric_direct0_cfg_pad_i218;
-    input fabric_direct0_cfg_pad_i219;
-    input fabric_direct0_cfg_pad_i22;
-    input fabric_direct0_cfg_pad_i220;
-    input fabric_direct0_cfg_pad_i221;
-    input fabric_direct0_cfg_pad_i222;
-    input fabric_direct0_cfg_pad_i223;
-    input fabric_direct0_cfg_pad_i224;
-    input fabric_direct0_cfg_pad_i225;
-    input fabric_direct0_cfg_pad_i226;
-    input fabric_direct0_cfg_pad_i227;
-    input fabric_direct0_cfg_pad_i228;
-    input fabric_direct0_cfg_pad_i229;
-    input fabric_direct0_cfg_pad_i23;
-    input fabric_direct0_cfg_pad_i230;
-    input fabric_direct0_cfg_pad_i231;
-    input fabric_direct0_cfg_pad_i232;
-    input fabric_direct0_cfg_pad_i233;
-    input fabric_direct0_cfg_pad_i234;
-    input fabric_direct0_cfg_pad_i235;
-    input fabric_direct0_cfg_pad_i236;
-    input fabric_direct0_cfg_pad_i237;
-    input fabric_direct0_cfg_pad_i238;
-    input fabric_direct0_cfg_pad_i239;
-    input fabric_direct0_cfg_pad_i24;
-    input fabric_direct0_cfg_pad_i240;
-    input fabric_direct0_cfg_pad_i241;
-    input fabric_direct0_cfg_pad_i242;
-    input fabric_direct0_cfg_pad_i243;
-    input fabric_direct0_cfg_pad_i244;
-    input fabric_direct0_cfg_pad_i245;
-    input fabric_direct0_cfg_pad_i246;
-    input fabric_direct0_cfg_pad_i247;
-    input fabric_direct0_cfg_pad_i248;
-    input fabric_direct0_cfg_pad_i249;
-    input fabric_direct0_cfg_pad_i25;
-    input fabric_direct0_cfg_pad_i250;
-    input fabric_direct0_cfg_pad_i251;
-    input fabric_direct0_cfg_pad_i252;
-    input fabric_direct0_cfg_pad_i253;
-    input fabric_direct0_cfg_pad_i254;
-    input fabric_direct0_cfg_pad_i255;
-    input fabric_direct0_cfg_pad_i256;
-    input fabric_direct0_cfg_pad_i257;
-    input fabric_direct0_cfg_pad_i258;
-    input fabric_direct0_cfg_pad_i259;
-    input fabric_direct0_cfg_pad_i26;
-    input fabric_direct0_cfg_pad_i260;
-    input fabric_direct0_cfg_pad_i261;
-    input fabric_direct0_cfg_pad_i262;
-    input fabric_direct0_cfg_pad_i263;
-    input fabric_direct0_cfg_pad_i264;
-    input fabric_direct0_cfg_pad_i265;
-    input fabric_direct0_cfg_pad_i266;
-    input fabric_direct0_cfg_pad_i267;
-    input fabric_direct0_cfg_pad_i268;
-    input fabric_direct0_cfg_pad_i269;
-    input fabric_direct0_cfg_pad_i27;
-    input fabric_direct0_cfg_pad_i270;
-    input fabric_direct0_cfg_pad_i271;
-    input fabric_direct0_cfg_pad_i272;
-    input fabric_direct0_cfg_pad_i273;
-    input fabric_direct0_cfg_pad_i274;
-    input fabric_direct0_cfg_pad_i275;
-    input fabric_direct0_cfg_pad_i276;
-    input fabric_direct0_cfg_pad_i277;
-    input fabric_direct0_cfg_pad_i278;
-    input fabric_direct0_cfg_pad_i279;
-    input fabric_direct0_cfg_pad_i28;
-    input fabric_direct0_cfg_pad_i280;
-    input fabric_direct0_cfg_pad_i281;
-    input fabric_direct0_cfg_pad_i282;
-    input fabric_direct0_cfg_pad_i283;
-    input fabric_direct0_cfg_pad_i284;
-    input fabric_direct0_cfg_pad_i285;
-    input fabric_direct0_cfg_pad_i286;
-    input fabric_direct0_cfg_pad_i287;
-    input fabric_direct0_cfg_pad_i288;
-    input fabric_direct0_cfg_pad_i289;
-    input fabric_direct0_cfg_pad_i29;
-    input fabric_direct0_cfg_pad_i290;
-    input fabric_direct0_cfg_pad_i291;
-    input fabric_direct0_cfg_pad_i292;
-    input fabric_direct0_cfg_pad_i293;
-    input fabric_direct0_cfg_pad_i294;
-    input fabric_direct0_cfg_pad_i295;
-    input fabric_direct0_cfg_pad_i296;
-    input fabric_direct0_cfg_pad_i297;
-    input fabric_direct0_cfg_pad_i298;
-    input fabric_direct0_cfg_pad_i299;
-    input fabric_direct0_cfg_pad_i3;
-    input fabric_direct0_cfg_pad_i30;
-    input fabric_direct0_cfg_pad_i300;
-    input fabric_direct0_cfg_pad_i301;
-    input fabric_direct0_cfg_pad_i302;
-    input fabric_direct0_cfg_pad_i303;
-    input fabric_direct0_cfg_pad_i304;
-    input fabric_direct0_cfg_pad_i305;
-    input fabric_direct0_cfg_pad_i306;
-    input fabric_direct0_cfg_pad_i307;
-    input fabric_direct0_cfg_pad_i308;
-    input fabric_direct0_cfg_pad_i309;
-    input fabric_direct0_cfg_pad_i31;
-    input fabric_direct0_cfg_pad_i310;
-    input fabric_direct0_cfg_pad_i311;
-    input fabric_direct0_cfg_pad_i312;
-    input fabric_direct0_cfg_pad_i313;
-    input fabric_direct0_cfg_pad_i314;
-    input fabric_direct0_cfg_pad_i315;
-    input fabric_direct0_cfg_pad_i316;
-    input fabric_direct0_cfg_pad_i317;
-    input fabric_direct0_cfg_pad_i318;
-    input fabric_direct0_cfg_pad_i319;
-    input fabric_direct0_cfg_pad_i32;
-    input fabric_direct0_cfg_pad_i320;
-    input fabric_direct0_cfg_pad_i321;
-    input fabric_direct0_cfg_pad_i322;
-    input fabric_direct0_cfg_pad_i323;
-    input fabric_direct0_cfg_pad_i324;
-    input fabric_direct0_cfg_pad_i325;
-    input fabric_direct0_cfg_pad_i326;
-    input fabric_direct0_cfg_pad_i327;
-    input fabric_direct0_cfg_pad_i328;
-    input fabric_direct0_cfg_pad_i329;
-    input fabric_direct0_cfg_pad_i33;
-    input fabric_direct0_cfg_pad_i330;
-    input fabric_direct0_cfg_pad_i331;
-    input fabric_direct0_cfg_pad_i332;
-    input fabric_direct0_cfg_pad_i333;
-    input fabric_direct0_cfg_pad_i334;
-    input fabric_direct0_cfg_pad_i335;
-    input fabric_direct0_cfg_pad_i336;
-    input fabric_direct0_cfg_pad_i337;
-    input fabric_direct0_cfg_pad_i338;
-    input fabric_direct0_cfg_pad_i339;
-    input fabric_direct0_cfg_pad_i34;
-    input fabric_direct0_cfg_pad_i340;
-    input fabric_direct0_cfg_pad_i341;
-    input fabric_direct0_cfg_pad_i342;
-    input fabric_direct0_cfg_pad_i343;
-    input fabric_direct0_cfg_pad_i344;
-    input fabric_direct0_cfg_pad_i345;
-    input fabric_direct0_cfg_pad_i346;
-    input fabric_direct0_cfg_pad_i347;
-    input fabric_direct0_cfg_pad_i348;
-    input fabric_direct0_cfg_pad_i349;
-    input fabric_direct0_cfg_pad_i35;
-    input fabric_direct0_cfg_pad_i350;
-    input fabric_direct0_cfg_pad_i351;
-    input fabric_direct0_cfg_pad_i352;
-    input fabric_direct0_cfg_pad_i353;
-    input fabric_direct0_cfg_pad_i354;
-    input fabric_direct0_cfg_pad_i355;
-    input fabric_direct0_cfg_pad_i356;
-    input fabric_direct0_cfg_pad_i357;
-    input fabric_direct0_cfg_pad_i358;
-    input fabric_direct0_cfg_pad_i359;
-    input fabric_direct0_cfg_pad_i36;
-    input fabric_direct0_cfg_pad_i360;
-    input fabric_direct0_cfg_pad_i361;
-    input fabric_direct0_cfg_pad_i362;
-    input fabric_direct0_cfg_pad_i363;
-    input fabric_direct0_cfg_pad_i364;
-    input fabric_direct0_cfg_pad_i365;
-    input fabric_direct0_cfg_pad_i366;
-    input fabric_direct0_cfg_pad_i367;
-    input fabric_direct0_cfg_pad_i368;
-    input fabric_direct0_cfg_pad_i369;
-    input fabric_direct0_cfg_pad_i37;
-    input fabric_direct0_cfg_pad_i370;
-    input fabric_direct0_cfg_pad_i371;
-    input fabric_direct0_cfg_pad_i372;
-    input fabric_direct0_cfg_pad_i373;
-    input fabric_direct0_cfg_pad_i374;
-    input fabric_direct0_cfg_pad_i375;
-    input fabric_direct0_cfg_pad_i376;
-    input fabric_direct0_cfg_pad_i377;
-    input fabric_direct0_cfg_pad_i378;
-    input fabric_direct0_cfg_pad_i379;
-    input fabric_direct0_cfg_pad_i38;
-    input fabric_direct0_cfg_pad_i380;
-    input fabric_direct0_cfg_pad_i381;
-    input fabric_direct0_cfg_pad_i382;
-    input fabric_direct0_cfg_pad_i383;
-    input fabric_direct0_cfg_pad_i384;
-    input fabric_direct0_cfg_pad_i385;
-    input fabric_direct0_cfg_pad_i386;
-    input fabric_direct0_cfg_pad_i387;
-    input fabric_direct0_cfg_pad_i388;
-    input fabric_direct0_cfg_pad_i389;
-    input fabric_direct0_cfg_pad_i39;
-    input fabric_direct0_cfg_pad_i390;
-    input fabric_direct0_cfg_pad_i391;
-    input fabric_direct0_cfg_pad_i392;
-    input fabric_direct0_cfg_pad_i393;
-    input fabric_direct0_cfg_pad_i394;
-    input fabric_direct0_cfg_pad_i395;
-    input fabric_direct0_cfg_pad_i396;
-    input fabric_direct0_cfg_pad_i397;
-    input fabric_direct0_cfg_pad_i398;
-    input fabric_direct0_cfg_pad_i399;
-    input fabric_direct0_cfg_pad_i4;
-    input fabric_direct0_cfg_pad_i40;
-    input fabric_direct0_cfg_pad_i400;
-    input fabric_direct0_cfg_pad_i401;
-    input fabric_direct0_cfg_pad_i402;
-    input fabric_direct0_cfg_pad_i403;
-    input fabric_direct0_cfg_pad_i404;
-    input fabric_direct0_cfg_pad_i405;
-    input fabric_direct0_cfg_pad_i406;
-    input fabric_direct0_cfg_pad_i407;
-    input fabric_direct0_cfg_pad_i408;
-    input fabric_direct0_cfg_pad_i409;
-    input fabric_direct0_cfg_pad_i41;
-    input fabric_direct0_cfg_pad_i410;
-    input fabric_direct0_cfg_pad_i411;
-    input fabric_direct0_cfg_pad_i412;
-    input fabric_direct0_cfg_pad_i413;
-    input fabric_direct0_cfg_pad_i414;
-    input fabric_direct0_cfg_pad_i415;
-    input fabric_direct0_cfg_pad_i416;
-    input fabric_direct0_cfg_pad_i417;
-    input fabric_direct0_cfg_pad_i418;
-    input fabric_direct0_cfg_pad_i419;
-    input fabric_direct0_cfg_pad_i42;
-    input fabric_direct0_cfg_pad_i420;
-    input fabric_direct0_cfg_pad_i421;
-    input fabric_direct0_cfg_pad_i422;
-    input fabric_direct0_cfg_pad_i423;
-    input fabric_direct0_cfg_pad_i424;
-    input fabric_direct0_cfg_pad_i425;
-    input fabric_direct0_cfg_pad_i426;
-    input fabric_direct0_cfg_pad_i427;
-    input fabric_direct0_cfg_pad_i428;
-    input fabric_direct0_cfg_pad_i429;
-    input fabric_direct0_cfg_pad_i43;
-    input fabric_direct0_cfg_pad_i430;
-    input fabric_direct0_cfg_pad_i431;
-    input fabric_direct0_cfg_pad_i432;
-    input fabric_direct0_cfg_pad_i433;
-    input fabric_direct0_cfg_pad_i434;
-    input fabric_direct0_cfg_pad_i435;
-    input fabric_direct0_cfg_pad_i436;
-    input fabric_direct0_cfg_pad_i437;
-    input fabric_direct0_cfg_pad_i438;
-    input fabric_direct0_cfg_pad_i439;
-    input fabric_direct0_cfg_pad_i44;
-    input fabric_direct0_cfg_pad_i440;
-    input fabric_direct0_cfg_pad_i441;
-    input fabric_direct0_cfg_pad_i442;
-    input fabric_direct0_cfg_pad_i443;
-    input fabric_direct0_cfg_pad_i444;
-    input fabric_direct0_cfg_pad_i445;
-    input fabric_direct0_cfg_pad_i446;
-    input fabric_direct0_cfg_pad_i447;
-    input fabric_direct0_cfg_pad_i448;
-    input fabric_direct0_cfg_pad_i449;
-    input fabric_direct0_cfg_pad_i45;
-    input fabric_direct0_cfg_pad_i450;
-    input fabric_direct0_cfg_pad_i451;
-    input fabric_direct0_cfg_pad_i452;
-    input fabric_direct0_cfg_pad_i453;
-    input fabric_direct0_cfg_pad_i454;
-    input fabric_direct0_cfg_pad_i455;
-    input fabric_direct0_cfg_pad_i456;
-    input fabric_direct0_cfg_pad_i457;
-    input fabric_direct0_cfg_pad_i458;
-    input fabric_direct0_cfg_pad_i459;
-    input fabric_direct0_cfg_pad_i46;
-    input fabric_direct0_cfg_pad_i460;
-    input fabric_direct0_cfg_pad_i461;
-    input fabric_direct0_cfg_pad_i462;
-    input fabric_direct0_cfg_pad_i463;
-    input fabric_direct0_cfg_pad_i464;
-    input fabric_direct0_cfg_pad_i465;
-    input fabric_direct0_cfg_pad_i466;
-    input fabric_direct0_cfg_pad_i467;
-    input fabric_direct0_cfg_pad_i468;
-    input fabric_direct0_cfg_pad_i469;
-    input fabric_direct0_cfg_pad_i47;
-    input fabric_direct0_cfg_pad_i470;
-    input fabric_direct0_cfg_pad_i471;
-    input fabric_direct0_cfg_pad_i472;
-    input fabric_direct0_cfg_pad_i473;
-    input fabric_direct0_cfg_pad_i474;
-    input fabric_direct0_cfg_pad_i475;
-    input fabric_direct0_cfg_pad_i476;
-    input fabric_direct0_cfg_pad_i477;
-    input fabric_direct0_cfg_pad_i478;
-    input fabric_direct0_cfg_pad_i479;
-    input fabric_direct0_cfg_pad_i48;
-    input fabric_direct0_cfg_pad_i480;
-    input fabric_direct0_cfg_pad_i481;
-    input fabric_direct0_cfg_pad_i482;
-    input fabric_direct0_cfg_pad_i483;
-    input fabric_direct0_cfg_pad_i484;
-    input fabric_direct0_cfg_pad_i485;
-    input fabric_direct0_cfg_pad_i486;
-    input fabric_direct0_cfg_pad_i487;
-    input fabric_direct0_cfg_pad_i488;
-    input fabric_direct0_cfg_pad_i489;
-    input fabric_direct0_cfg_pad_i49;
-    input fabric_direct0_cfg_pad_i490;
-    input fabric_direct0_cfg_pad_i491;
-    input fabric_direct0_cfg_pad_i492;
-    input fabric_direct0_cfg_pad_i493;
-    input fabric_direct0_cfg_pad_i494;
-    input fabric_direct0_cfg_pad_i495;
-    input fabric_direct0_cfg_pad_i496;
-    input fabric_direct0_cfg_pad_i497;
-    input fabric_direct0_cfg_pad_i498;
-    input fabric_direct0_cfg_pad_i499;
-    input fabric_direct0_cfg_pad_i5;
-    input fabric_direct0_cfg_pad_i50;
-    input fabric_direct0_cfg_pad_i500;
-    input fabric_direct0_cfg_pad_i501;
-    input fabric_direct0_cfg_pad_i502;
-    input fabric_direct0_cfg_pad_i503;
-    input fabric_direct0_cfg_pad_i504;
-    input fabric_direct0_cfg_pad_i505;
-    input fabric_direct0_cfg_pad_i506;
-    input fabric_direct0_cfg_pad_i507;
-    input fabric_direct0_cfg_pad_i508;
-    input fabric_direct0_cfg_pad_i509;
-    input fabric_direct0_cfg_pad_i51;
-    input fabric_direct0_cfg_pad_i510;
-    input fabric_direct0_cfg_pad_i511;
-    input fabric_direct0_cfg_pad_i512;
-    input fabric_direct0_cfg_pad_i513;
-    input fabric_direct0_cfg_pad_i514;
-    input fabric_direct0_cfg_pad_i515;
-    input fabric_direct0_cfg_pad_i516;
-    input fabric_direct0_cfg_pad_i517;
-    input fabric_direct0_cfg_pad_i518;
-    input fabric_direct0_cfg_pad_i519;
-    input fabric_direct0_cfg_pad_i52;
-    input fabric_direct0_cfg_pad_i520;
-    input fabric_direct0_cfg_pad_i521;
-    input fabric_direct0_cfg_pad_i522;
-    input fabric_direct0_cfg_pad_i523;
-    input fabric_direct0_cfg_pad_i524;
-    input fabric_direct0_cfg_pad_i525;
-    input fabric_direct0_cfg_pad_i526;
-    input fabric_direct0_cfg_pad_i527;
-    input fabric_direct0_cfg_pad_i528;
-    input fabric_direct0_cfg_pad_i529;
-    input fabric_direct0_cfg_pad_i53;
-    input fabric_direct0_cfg_pad_i530;
-    input fabric_direct0_cfg_pad_i531;
-    input fabric_direct0_cfg_pad_i532;
-    input fabric_direct0_cfg_pad_i533;
-    input fabric_direct0_cfg_pad_i534;
-    input fabric_direct0_cfg_pad_i535;
-    input fabric_direct0_cfg_pad_i536;
-    input fabric_direct0_cfg_pad_i537;
-    input fabric_direct0_cfg_pad_i538;
-    input fabric_direct0_cfg_pad_i539;
-    input fabric_direct0_cfg_pad_i54;
-    input fabric_direct0_cfg_pad_i540;
-    input fabric_direct0_cfg_pad_i541;
-    input fabric_direct0_cfg_pad_i542;
-    input fabric_direct0_cfg_pad_i543;
-    input fabric_direct0_cfg_pad_i544;
-    input fabric_direct0_cfg_pad_i545;
-    input fabric_direct0_cfg_pad_i546;
-    input fabric_direct0_cfg_pad_i547;
-    input fabric_direct0_cfg_pad_i548;
-    input fabric_direct0_cfg_pad_i549;
-    input fabric_direct0_cfg_pad_i55;
-    input fabric_direct0_cfg_pad_i550;
-    input fabric_direct0_cfg_pad_i551;
-    input fabric_direct0_cfg_pad_i552;
-    input fabric_direct0_cfg_pad_i553;
-    input fabric_direct0_cfg_pad_i554;
-    input fabric_direct0_cfg_pad_i555;
-    input fabric_direct0_cfg_pad_i556;
-    input fabric_direct0_cfg_pad_i557;
-    input fabric_direct0_cfg_pad_i558;
-    input fabric_direct0_cfg_pad_i559;
-    input fabric_direct0_cfg_pad_i56;
-    input fabric_direct0_cfg_pad_i560;
-    input fabric_direct0_cfg_pad_i561;
-    input fabric_direct0_cfg_pad_i562;
-    input fabric_direct0_cfg_pad_i563;
-    input fabric_direct0_cfg_pad_i564;
-    input fabric_direct0_cfg_pad_i565;
-    input fabric_direct0_cfg_pad_i566;
-    input fabric_direct0_cfg_pad_i567;
-    input fabric_direct0_cfg_pad_i568;
-    input fabric_direct0_cfg_pad_i569;
-    input fabric_direct0_cfg_pad_i57;
-    input fabric_direct0_cfg_pad_i570;
-    input fabric_direct0_cfg_pad_i571;
-    input fabric_direct0_cfg_pad_i572;
-    input fabric_direct0_cfg_pad_i573;
-    input fabric_direct0_cfg_pad_i574;
-    input fabric_direct0_cfg_pad_i575;
-    input fabric_direct0_cfg_pad_i576;
-    input fabric_direct0_cfg_pad_i577;
-    input fabric_direct0_cfg_pad_i578;
-    input fabric_direct0_cfg_pad_i579;
-    input fabric_direct0_cfg_pad_i58;
-    input fabric_direct0_cfg_pad_i580;
-    input fabric_direct0_cfg_pad_i581;
-    input fabric_direct0_cfg_pad_i582;
-    input fabric_direct0_cfg_pad_i583;
-    input fabric_direct0_cfg_pad_i584;
-    input fabric_direct0_cfg_pad_i585;
-    input fabric_direct0_cfg_pad_i586;
-    input fabric_direct0_cfg_pad_i587;
-    input fabric_direct0_cfg_pad_i588;
-    input fabric_direct0_cfg_pad_i589;
-    input fabric_direct0_cfg_pad_i59;
-    input fabric_direct0_cfg_pad_i590;
-    input fabric_direct0_cfg_pad_i591;
-    input fabric_direct0_cfg_pad_i592;
-    input fabric_direct0_cfg_pad_i593;
-    input fabric_direct0_cfg_pad_i594;
-    input fabric_direct0_cfg_pad_i595;
-    input fabric_direct0_cfg_pad_i596;
-    input fabric_direct0_cfg_pad_i597;
-    input fabric_direct0_cfg_pad_i598;
-    input fabric_direct0_cfg_pad_i599;
-    input fabric_direct0_cfg_pad_i6;
-    input fabric_direct0_cfg_pad_i60;
-    input fabric_direct0_cfg_pad_i600;
-    input fabric_direct0_cfg_pad_i601;
-    input fabric_direct0_cfg_pad_i602;
-    input fabric_direct0_cfg_pad_i603;
-    input fabric_direct0_cfg_pad_i604;
-    input fabric_direct0_cfg_pad_i605;
-    input fabric_direct0_cfg_pad_i606;
-    input fabric_direct0_cfg_pad_i607;
-    input fabric_direct0_cfg_pad_i608;
-    input fabric_direct0_cfg_pad_i609;
-    input fabric_direct0_cfg_pad_i61;
-    input fabric_direct0_cfg_pad_i610;
-    input fabric_direct0_cfg_pad_i611;
-    input fabric_direct0_cfg_pad_i612;
-    input fabric_direct0_cfg_pad_i613;
-    input fabric_direct0_cfg_pad_i614;
-    input fabric_direct0_cfg_pad_i615;
-    input fabric_direct0_cfg_pad_i616;
-    input fabric_direct0_cfg_pad_i617;
-    input fabric_direct0_cfg_pad_i618;
-    input fabric_direct0_cfg_pad_i619;
-    input fabric_direct0_cfg_pad_i62;
-    input fabric_direct0_cfg_pad_i620;
-    input fabric_direct0_cfg_pad_i621;
-    input fabric_direct0_cfg_pad_i622;
-    input fabric_direct0_cfg_pad_i623;
-    input fabric_direct0_cfg_pad_i624;
-    input fabric_direct0_cfg_pad_i625;
-    input fabric_direct0_cfg_pad_i626;
-    input fabric_direct0_cfg_pad_i627;
-    input fabric_direct0_cfg_pad_i628;
-    input fabric_direct0_cfg_pad_i629;
-    input fabric_direct0_cfg_pad_i63;
-    input fabric_direct0_cfg_pad_i630;
-    input fabric_direct0_cfg_pad_i631;
-    input fabric_direct0_cfg_pad_i632;
-    input fabric_direct0_cfg_pad_i633;
-    input fabric_direct0_cfg_pad_i634;
-    input fabric_direct0_cfg_pad_i635;
-    input fabric_direct0_cfg_pad_i636;
-    input fabric_direct0_cfg_pad_i637;
-    input fabric_direct0_cfg_pad_i638;
-    input fabric_direct0_cfg_pad_i639;
-    input fabric_direct0_cfg_pad_i64;
-    input fabric_direct0_cfg_pad_i640;
-    input fabric_direct0_cfg_pad_i641;
-    input fabric_direct0_cfg_pad_i642;
-    input fabric_direct0_cfg_pad_i643;
-    input fabric_direct0_cfg_pad_i644;
-    input fabric_direct0_cfg_pad_i645;
-    input fabric_direct0_cfg_pad_i646;
-    input fabric_direct0_cfg_pad_i647;
-    input fabric_direct0_cfg_pad_i648;
-    input fabric_direct0_cfg_pad_i649;
-    input fabric_direct0_cfg_pad_i65;
-    input fabric_direct0_cfg_pad_i650;
-    input fabric_direct0_cfg_pad_i651;
-    input fabric_direct0_cfg_pad_i652;
-    input fabric_direct0_cfg_pad_i653;
-    input fabric_direct0_cfg_pad_i654;
-    input fabric_direct0_cfg_pad_i655;
-    input fabric_direct0_cfg_pad_i656;
-    input fabric_direct0_cfg_pad_i657;
-    input fabric_direct0_cfg_pad_i658;
-    input fabric_direct0_cfg_pad_i659;
-    input fabric_direct0_cfg_pad_i66;
-    input fabric_direct0_cfg_pad_i660;
-    input fabric_direct0_cfg_pad_i661;
-    input fabric_direct0_cfg_pad_i662;
-    input fabric_direct0_cfg_pad_i663;
-    input fabric_direct0_cfg_pad_i664;
-    input fabric_direct0_cfg_pad_i665;
-    input fabric_direct0_cfg_pad_i666;
-    input fabric_direct0_cfg_pad_i667;
-    input fabric_direct0_cfg_pad_i668;
-    input fabric_direct0_cfg_pad_i669;
-    input fabric_direct0_cfg_pad_i67;
-    input fabric_direct0_cfg_pad_i670;
-    input fabric_direct0_cfg_pad_i671;
-    input fabric_direct0_cfg_pad_i672;
-    input fabric_direct0_cfg_pad_i673;
-    input fabric_direct0_cfg_pad_i674;
-    input fabric_direct0_cfg_pad_i675;
-    input fabric_direct0_cfg_pad_i676;
-    input fabric_direct0_cfg_pad_i677;
-    input fabric_direct0_cfg_pad_i678;
-    input fabric_direct0_cfg_pad_i679;
-    input fabric_direct0_cfg_pad_i68;
-    input fabric_direct0_cfg_pad_i680;
-    input fabric_direct0_cfg_pad_i681;
-    input fabric_direct0_cfg_pad_i682;
-    input fabric_direct0_cfg_pad_i683;
-    input fabric_direct0_cfg_pad_i684;
-    input fabric_direct0_cfg_pad_i685;
-    input fabric_direct0_cfg_pad_i686;
-    input fabric_direct0_cfg_pad_i687;
-    input fabric_direct0_cfg_pad_i688;
-    input fabric_direct0_cfg_pad_i689;
-    input fabric_direct0_cfg_pad_i69;
-    input fabric_direct0_cfg_pad_i690;
-    input fabric_direct0_cfg_pad_i691;
-    input fabric_direct0_cfg_pad_i692;
-    input fabric_direct0_cfg_pad_i693;
-    input fabric_direct0_cfg_pad_i694;
-    input fabric_direct0_cfg_pad_i695;
-    input fabric_direct0_cfg_pad_i696;
-    input fabric_direct0_cfg_pad_i697;
-    input fabric_direct0_cfg_pad_i698;
-    input fabric_direct0_cfg_pad_i699;
-    input fabric_direct0_cfg_pad_i7;
-    input fabric_direct0_cfg_pad_i70;
-    input fabric_direct0_cfg_pad_i700;
-    input fabric_direct0_cfg_pad_i701;
-    input fabric_direct0_cfg_pad_i702;
-    input fabric_direct0_cfg_pad_i703;
-    input fabric_direct0_cfg_pad_i704;
-    input fabric_direct0_cfg_pad_i705;
-    input fabric_direct0_cfg_pad_i706;
-    input fabric_direct0_cfg_pad_i707;
-    input fabric_direct0_cfg_pad_i708;
-    input fabric_direct0_cfg_pad_i709;
-    input fabric_direct0_cfg_pad_i71;
-    input fabric_direct0_cfg_pad_i710;
-    input fabric_direct0_cfg_pad_i711;
-    input fabric_direct0_cfg_pad_i712;
-    input fabric_direct0_cfg_pad_i713;
-    input fabric_direct0_cfg_pad_i714;
-    input fabric_direct0_cfg_pad_i715;
-    input fabric_direct0_cfg_pad_i716;
-    input fabric_direct0_cfg_pad_i717;
-    input fabric_direct0_cfg_pad_i718;
-    input fabric_direct0_cfg_pad_i719;
-    input fabric_direct0_cfg_pad_i72;
-    input fabric_direct0_cfg_pad_i720;
-    input fabric_direct0_cfg_pad_i73;
-    input fabric_direct0_cfg_pad_i74;
-    input fabric_direct0_cfg_pad_i75;
-    input fabric_direct0_cfg_pad_i76;
-    input fabric_direct0_cfg_pad_i77;
-    input fabric_direct0_cfg_pad_i78;
-    input fabric_direct0_cfg_pad_i79;
-    input fabric_direct0_cfg_pad_i8;
-    input fabric_direct0_cfg_pad_i80;
-    input fabric_direct0_cfg_pad_i81;
-    input fabric_direct0_cfg_pad_i82;
-    input fabric_direct0_cfg_pad_i83;
-    input fabric_direct0_cfg_pad_i84;
-    input fabric_direct0_cfg_pad_i85;
-    input fabric_direct0_cfg_pad_i86;
-    input fabric_direct0_cfg_pad_i87;
-    input fabric_direct0_cfg_pad_i88;
-    input fabric_direct0_cfg_pad_i89;
-    input fabric_direct0_cfg_pad_i9;
-    input fabric_direct0_cfg_pad_i90;
-    input fabric_direct0_cfg_pad_i91;
-    input fabric_direct0_cfg_pad_i92;
-    input fabric_direct0_cfg_pad_i93;
-    input fabric_direct0_cfg_pad_i94;
-    input fabric_direct0_cfg_pad_i95;
-    input fabric_direct0_cfg_pad_i96;
-    input fabric_direct0_cfg_pad_i97;
-    input fabric_direct0_cfg_pad_i98;
-    input fabric_direct0_cfg_pad_i99;
-    input fabric_direct0_clock_fabric_i1;
-    input fabric_direct0_clock_fabric_i2;
-    input fabric_direct0_clock_fabric_i3;
-    input fabric_direct0_clock_fabric_i4;
-    input fabric_direct0_di_ena_i1;
-    input fabric_direct0_di_ena_i10;
-    input fabric_direct0_di_ena_i11;
-    input fabric_direct0_di_ena_i12;
-    input fabric_direct0_di_ena_i13;
-    input fabric_direct0_di_ena_i14;
-    input fabric_direct0_di_ena_i15;
-    input fabric_direct0_di_ena_i16;
-    input fabric_direct0_di_ena_i17;
-    input fabric_direct0_di_ena_i18;
-    input fabric_direct0_di_ena_i19;
-    input fabric_direct0_di_ena_i2;
-    input fabric_direct0_di_ena_i20;
-    input fabric_direct0_di_ena_i21;
-    input fabric_direct0_di_ena_i22;
-    input fabric_direct0_di_ena_i23;
-    input fabric_direct0_di_ena_i24;
-    input fabric_direct0_di_ena_i3;
-    input fabric_direct0_di_ena_i4;
-    input fabric_direct0_di_ena_i5;
-    input fabric_direct0_di_ena_i6;
-    input fabric_direct0_di_ena_i7;
-    input fabric_direct0_di_ena_i8;
-    input fabric_direct0_di_ena_i9;
-    output fabric_direct0_di_o1;
-    output fabric_direct0_di_o10;
-    output fabric_direct0_di_o11;
-    output fabric_direct0_di_o12;
-    output fabric_direct0_di_o13;
-    output fabric_direct0_di_o14;
-    output fabric_direct0_di_o15;
-    output fabric_direct0_di_o16;
-    output fabric_direct0_di_o17;
-    output fabric_direct0_di_o18;
-    output fabric_direct0_di_o19;
-    output fabric_direct0_di_o2;
-    output fabric_direct0_di_o20;
-    output fabric_direct0_di_o21;
-    output fabric_direct0_di_o22;
-    output fabric_direct0_di_o23;
-    output fabric_direct0_di_o24;
-    output fabric_direct0_di_o3;
-    output fabric_direct0_di_o4;
-    output fabric_direct0_di_o5;
-    output fabric_direct0_di_o6;
-    output fabric_direct0_di_o7;
-    output fabric_direct0_di_o8;
-    output fabric_direct0_di_o9;
-    input fabric_direct0_di_rs_i1;
-    input fabric_direct0_di_rs_i10;
-    input fabric_direct0_di_rs_i11;
-    input fabric_direct0_di_rs_i12;
-    input fabric_direct0_di_rs_i13;
-    input fabric_direct0_di_rs_i14;
-    input fabric_direct0_di_rs_i15;
-    input fabric_direct0_di_rs_i16;
-    input fabric_direct0_di_rs_i17;
-    input fabric_direct0_di_rs_i18;
-    input fabric_direct0_di_rs_i19;
-    input fabric_direct0_di_rs_i2;
-    input fabric_direct0_di_rs_i20;
-    input fabric_direct0_di_rs_i21;
-    input fabric_direct0_di_rs_i22;
-    input fabric_direct0_di_rs_i23;
-    input fabric_direct0_di_rs_i24;
-    input fabric_direct0_di_rs_i3;
-    input fabric_direct0_di_rs_i4;
-    input fabric_direct0_di_rs_i5;
-    input fabric_direct0_di_rs_i6;
-    input fabric_direct0_di_rs_i7;
-    input fabric_direct0_di_rs_i8;
-    input fabric_direct0_di_rs_i9;
-    input fabric_direct0_do_ena_i1;
-    input fabric_direct0_do_ena_i10;
-    input fabric_direct0_do_ena_i11;
-    input fabric_direct0_do_ena_i12;
-    input fabric_direct0_do_ena_i13;
-    input fabric_direct0_do_ena_i14;
-    input fabric_direct0_do_ena_i15;
-    input fabric_direct0_do_ena_i16;
-    input fabric_direct0_do_ena_i17;
-    input fabric_direct0_do_ena_i18;
-    input fabric_direct0_do_ena_i19;
-    input fabric_direct0_do_ena_i2;
-    input fabric_direct0_do_ena_i20;
-    input fabric_direct0_do_ena_i21;
-    input fabric_direct0_do_ena_i22;
-    input fabric_direct0_do_ena_i23;
-    input fabric_direct0_do_ena_i24;
-    input fabric_direct0_do_ena_i3;
-    input fabric_direct0_do_ena_i4;
-    input fabric_direct0_do_ena_i5;
-    input fabric_direct0_do_ena_i6;
-    input fabric_direct0_do_ena_i7;
-    input fabric_direct0_do_ena_i8;
-    input fabric_direct0_do_ena_i9;
-    input fabric_direct0_do_i1;
-    input fabric_direct0_do_i10;
-    input fabric_direct0_do_i11;
-    input fabric_direct0_do_i12;
-    input fabric_direct0_do_i13;
-    input fabric_direct0_do_i14;
-    input fabric_direct0_do_i15;
-    input fabric_direct0_do_i16;
-    input fabric_direct0_do_i17;
-    input fabric_direct0_do_i18;
-    input fabric_direct0_do_i19;
-    input fabric_direct0_do_i2;
-    input fabric_direct0_do_i20;
-    input fabric_direct0_do_i21;
-    input fabric_direct0_do_i22;
-    input fabric_direct0_do_i23;
-    input fabric_direct0_do_i24;
-    input fabric_direct0_do_i3;
-    input fabric_direct0_do_i4;
-    input fabric_direct0_do_i5;
-    input fabric_direct0_do_i6;
-    input fabric_direct0_do_i7;
-    input fabric_direct0_do_i8;
-    input fabric_direct0_do_i9;
-    input fabric_direct0_do_rs_i1;
-    input fabric_direct0_do_rs_i10;
-    input fabric_direct0_do_rs_i11;
-    input fabric_direct0_do_rs_i12;
-    input fabric_direct0_do_rs_i13;
-    input fabric_direct0_do_rs_i14;
-    input fabric_direct0_do_rs_i15;
-    input fabric_direct0_do_rs_i16;
-    input fabric_direct0_do_rs_i17;
-    input fabric_direct0_do_rs_i18;
-    input fabric_direct0_do_rs_i19;
-    input fabric_direct0_do_rs_i2;
-    input fabric_direct0_do_rs_i20;
-    input fabric_direct0_do_rs_i21;
-    input fabric_direct0_do_rs_i22;
-    input fabric_direct0_do_rs_i23;
-    input fabric_direct0_do_rs_i24;
-    input fabric_direct0_do_rs_i3;
-    input fabric_direct0_do_rs_i4;
-    input fabric_direct0_do_rs_i5;
-    input fabric_direct0_do_rs_i6;
-    input fabric_direct0_do_rs_i7;
-    input fabric_direct0_do_rs_i8;
-    input fabric_direct0_do_rs_i9;
-    input fabric_direct0_loopback_en_i;
-    input fabric_direct0_loopback_mux_i;
-    input fabric_direct0_oe_ena_i1;
-    input fabric_direct0_oe_ena_i10;
-    input fabric_direct0_oe_ena_i11;
-    input fabric_direct0_oe_ena_i12;
-    input fabric_direct0_oe_ena_i13;
-    input fabric_direct0_oe_ena_i14;
-    input fabric_direct0_oe_ena_i15;
-    input fabric_direct0_oe_ena_i16;
-    input fabric_direct0_oe_ena_i17;
-    input fabric_direct0_oe_ena_i18;
-    input fabric_direct0_oe_ena_i19;
-    input fabric_direct0_oe_ena_i2;
-    input fabric_direct0_oe_ena_i20;
-    input fabric_direct0_oe_ena_i21;
-    input fabric_direct0_oe_ena_i22;
-    input fabric_direct0_oe_ena_i23;
-    input fabric_direct0_oe_ena_i24;
-    input fabric_direct0_oe_ena_i3;
-    input fabric_direct0_oe_ena_i4;
-    input fabric_direct0_oe_ena_i5;
-    input fabric_direct0_oe_ena_i6;
-    input fabric_direct0_oe_ena_i7;
-    input fabric_direct0_oe_ena_i8;
-    input fabric_direct0_oe_ena_i9;
-    input fabric_direct0_oe_i1;
-    input fabric_direct0_oe_i10;
-    input fabric_direct0_oe_i11;
-    input fabric_direct0_oe_i12;
-    input fabric_direct0_oe_i13;
-    input fabric_direct0_oe_i14;
-    input fabric_direct0_oe_i15;
-    input fabric_direct0_oe_i16;
-    input fabric_direct0_oe_i17;
-    input fabric_direct0_oe_i18;
-    input fabric_direct0_oe_i19;
-    input fabric_direct0_oe_i2;
-    input fabric_direct0_oe_i20;
-    input fabric_direct0_oe_i21;
-    input fabric_direct0_oe_i22;
-    input fabric_direct0_oe_i23;
-    input fabric_direct0_oe_i24;
-    input fabric_direct0_oe_i3;
-    input fabric_direct0_oe_i4;
-    input fabric_direct0_oe_i5;
-    input fabric_direct0_oe_i6;
-    input fabric_direct0_oe_i7;
-    input fabric_direct0_oe_i8;
-    input fabric_direct0_oe_i9;
-    input fabric_direct0_oe_rs_i1;
-    input fabric_direct0_oe_rs_i10;
-    input fabric_direct0_oe_rs_i11;
-    input fabric_direct0_oe_rs_i12;
-    input fabric_direct0_oe_rs_i13;
-    input fabric_direct0_oe_rs_i14;
-    input fabric_direct0_oe_rs_i15;
-    input fabric_direct0_oe_rs_i16;
-    input fabric_direct0_oe_rs_i17;
-    input fabric_direct0_oe_rs_i18;
-    input fabric_direct0_oe_rs_i19;
-    input fabric_direct0_oe_rs_i2;
-    input fabric_direct0_oe_rs_i20;
-    input fabric_direct0_oe_rs_i21;
-    input fabric_direct0_oe_rs_i22;
-    input fabric_direct0_oe_rs_i23;
-    input fabric_direct0_oe_rs_i24;
-    input fabric_direct0_oe_rs_i3;
-    input fabric_direct0_oe_rs_i4;
-    input fabric_direct0_oe_rs_i5;
-    input fabric_direct0_oe_rs_i6;
-    input fabric_direct0_oe_rs_i7;
-    input fabric_direct0_oe_rs_i8;
-    input fabric_direct0_oe_rs_i9;
-    input fabric_direct0_scan_en_i;
-    input fabric_direct1_cfg_bank_i1;
-    input fabric_direct1_cfg_bank_i2;
-    input fabric_direct1_cfg_bank_i3;
-    input fabric_direct1_cfg_bank_i4;
-    input fabric_direct1_cfg_pad_i1;
-    input fabric_direct1_cfg_pad_i10;
-    input fabric_direct1_cfg_pad_i100;
-    input fabric_direct1_cfg_pad_i101;
-    input fabric_direct1_cfg_pad_i102;
-    input fabric_direct1_cfg_pad_i103;
-    input fabric_direct1_cfg_pad_i104;
-    input fabric_direct1_cfg_pad_i105;
-    input fabric_direct1_cfg_pad_i106;
-    input fabric_direct1_cfg_pad_i107;
-    input fabric_direct1_cfg_pad_i108;
-    input fabric_direct1_cfg_pad_i109;
-    input fabric_direct1_cfg_pad_i11;
-    input fabric_direct1_cfg_pad_i110;
-    input fabric_direct1_cfg_pad_i111;
-    input fabric_direct1_cfg_pad_i112;
-    input fabric_direct1_cfg_pad_i113;
-    input fabric_direct1_cfg_pad_i114;
-    input fabric_direct1_cfg_pad_i115;
-    input fabric_direct1_cfg_pad_i116;
-    input fabric_direct1_cfg_pad_i117;
-    input fabric_direct1_cfg_pad_i118;
-    input fabric_direct1_cfg_pad_i119;
-    input fabric_direct1_cfg_pad_i12;
-    input fabric_direct1_cfg_pad_i120;
-    input fabric_direct1_cfg_pad_i121;
-    input fabric_direct1_cfg_pad_i122;
-    input fabric_direct1_cfg_pad_i123;
-    input fabric_direct1_cfg_pad_i124;
-    input fabric_direct1_cfg_pad_i125;
-    input fabric_direct1_cfg_pad_i126;
-    input fabric_direct1_cfg_pad_i127;
-    input fabric_direct1_cfg_pad_i128;
-    input fabric_direct1_cfg_pad_i129;
-    input fabric_direct1_cfg_pad_i13;
-    input fabric_direct1_cfg_pad_i130;
-    input fabric_direct1_cfg_pad_i131;
-    input fabric_direct1_cfg_pad_i132;
-    input fabric_direct1_cfg_pad_i133;
-    input fabric_direct1_cfg_pad_i134;
-    input fabric_direct1_cfg_pad_i135;
-    input fabric_direct1_cfg_pad_i136;
-    input fabric_direct1_cfg_pad_i137;
-    input fabric_direct1_cfg_pad_i138;
-    input fabric_direct1_cfg_pad_i139;
-    input fabric_direct1_cfg_pad_i14;
-    input fabric_direct1_cfg_pad_i140;
-    input fabric_direct1_cfg_pad_i141;
-    input fabric_direct1_cfg_pad_i142;
-    input fabric_direct1_cfg_pad_i143;
-    input fabric_direct1_cfg_pad_i144;
-    input fabric_direct1_cfg_pad_i145;
-    input fabric_direct1_cfg_pad_i146;
-    input fabric_direct1_cfg_pad_i147;
-    input fabric_direct1_cfg_pad_i148;
-    input fabric_direct1_cfg_pad_i149;
-    input fabric_direct1_cfg_pad_i15;
-    input fabric_direct1_cfg_pad_i150;
-    input fabric_direct1_cfg_pad_i151;
-    input fabric_direct1_cfg_pad_i152;
-    input fabric_direct1_cfg_pad_i153;
-    input fabric_direct1_cfg_pad_i154;
-    input fabric_direct1_cfg_pad_i155;
-    input fabric_direct1_cfg_pad_i156;
-    input fabric_direct1_cfg_pad_i157;
-    input fabric_direct1_cfg_pad_i158;
-    input fabric_direct1_cfg_pad_i159;
-    input fabric_direct1_cfg_pad_i16;
-    input fabric_direct1_cfg_pad_i160;
-    input fabric_direct1_cfg_pad_i161;
-    input fabric_direct1_cfg_pad_i162;
-    input fabric_direct1_cfg_pad_i163;
-    input fabric_direct1_cfg_pad_i164;
-    input fabric_direct1_cfg_pad_i165;
-    input fabric_direct1_cfg_pad_i166;
-    input fabric_direct1_cfg_pad_i167;
-    input fabric_direct1_cfg_pad_i168;
-    input fabric_direct1_cfg_pad_i169;
-    input fabric_direct1_cfg_pad_i17;
-    input fabric_direct1_cfg_pad_i170;
-    input fabric_direct1_cfg_pad_i171;
-    input fabric_direct1_cfg_pad_i172;
-    input fabric_direct1_cfg_pad_i173;
-    input fabric_direct1_cfg_pad_i174;
-    input fabric_direct1_cfg_pad_i175;
-    input fabric_direct1_cfg_pad_i176;
-    input fabric_direct1_cfg_pad_i177;
-    input fabric_direct1_cfg_pad_i178;
-    input fabric_direct1_cfg_pad_i179;
-    input fabric_direct1_cfg_pad_i18;
-    input fabric_direct1_cfg_pad_i180;
-    input fabric_direct1_cfg_pad_i181;
-    input fabric_direct1_cfg_pad_i182;
-    input fabric_direct1_cfg_pad_i183;
-    input fabric_direct1_cfg_pad_i184;
-    input fabric_direct1_cfg_pad_i185;
-    input fabric_direct1_cfg_pad_i186;
-    input fabric_direct1_cfg_pad_i187;
-    input fabric_direct1_cfg_pad_i188;
-    input fabric_direct1_cfg_pad_i189;
-    input fabric_direct1_cfg_pad_i19;
-    input fabric_direct1_cfg_pad_i190;
-    input fabric_direct1_cfg_pad_i191;
-    input fabric_direct1_cfg_pad_i192;
-    input fabric_direct1_cfg_pad_i193;
-    input fabric_direct1_cfg_pad_i194;
-    input fabric_direct1_cfg_pad_i195;
-    input fabric_direct1_cfg_pad_i196;
-    input fabric_direct1_cfg_pad_i197;
-    input fabric_direct1_cfg_pad_i198;
-    input fabric_direct1_cfg_pad_i199;
-    input fabric_direct1_cfg_pad_i2;
-    input fabric_direct1_cfg_pad_i20;
-    input fabric_direct1_cfg_pad_i200;
-    input fabric_direct1_cfg_pad_i201;
-    input fabric_direct1_cfg_pad_i202;
-    input fabric_direct1_cfg_pad_i203;
-    input fabric_direct1_cfg_pad_i204;
-    input fabric_direct1_cfg_pad_i205;
-    input fabric_direct1_cfg_pad_i206;
-    input fabric_direct1_cfg_pad_i207;
-    input fabric_direct1_cfg_pad_i208;
-    input fabric_direct1_cfg_pad_i209;
-    input fabric_direct1_cfg_pad_i21;
-    input fabric_direct1_cfg_pad_i210;
-    input fabric_direct1_cfg_pad_i211;
-    input fabric_direct1_cfg_pad_i212;
-    input fabric_direct1_cfg_pad_i213;
-    input fabric_direct1_cfg_pad_i214;
-    input fabric_direct1_cfg_pad_i215;
-    input fabric_direct1_cfg_pad_i216;
-    input fabric_direct1_cfg_pad_i217;
-    input fabric_direct1_cfg_pad_i218;
-    input fabric_direct1_cfg_pad_i219;
-    input fabric_direct1_cfg_pad_i22;
-    input fabric_direct1_cfg_pad_i220;
-    input fabric_direct1_cfg_pad_i221;
-    input fabric_direct1_cfg_pad_i222;
-    input fabric_direct1_cfg_pad_i223;
-    input fabric_direct1_cfg_pad_i224;
-    input fabric_direct1_cfg_pad_i225;
-    input fabric_direct1_cfg_pad_i226;
-    input fabric_direct1_cfg_pad_i227;
-    input fabric_direct1_cfg_pad_i228;
-    input fabric_direct1_cfg_pad_i229;
-    input fabric_direct1_cfg_pad_i23;
-    input fabric_direct1_cfg_pad_i230;
-    input fabric_direct1_cfg_pad_i231;
-    input fabric_direct1_cfg_pad_i232;
-    input fabric_direct1_cfg_pad_i233;
-    input fabric_direct1_cfg_pad_i234;
-    input fabric_direct1_cfg_pad_i235;
-    input fabric_direct1_cfg_pad_i236;
-    input fabric_direct1_cfg_pad_i237;
-    input fabric_direct1_cfg_pad_i238;
-    input fabric_direct1_cfg_pad_i239;
-    input fabric_direct1_cfg_pad_i24;
-    input fabric_direct1_cfg_pad_i240;
-    input fabric_direct1_cfg_pad_i241;
-    input fabric_direct1_cfg_pad_i242;
-    input fabric_direct1_cfg_pad_i243;
-    input fabric_direct1_cfg_pad_i244;
-    input fabric_direct1_cfg_pad_i245;
-    input fabric_direct1_cfg_pad_i246;
-    input fabric_direct1_cfg_pad_i247;
-    input fabric_direct1_cfg_pad_i248;
-    input fabric_direct1_cfg_pad_i249;
-    input fabric_direct1_cfg_pad_i25;
-    input fabric_direct1_cfg_pad_i250;
-    input fabric_direct1_cfg_pad_i251;
-    input fabric_direct1_cfg_pad_i252;
-    input fabric_direct1_cfg_pad_i253;
-    input fabric_direct1_cfg_pad_i254;
-    input fabric_direct1_cfg_pad_i255;
-    input fabric_direct1_cfg_pad_i256;
-    input fabric_direct1_cfg_pad_i257;
-    input fabric_direct1_cfg_pad_i258;
-    input fabric_direct1_cfg_pad_i259;
-    input fabric_direct1_cfg_pad_i26;
-    input fabric_direct1_cfg_pad_i260;
-    input fabric_direct1_cfg_pad_i261;
-    input fabric_direct1_cfg_pad_i262;
-    input fabric_direct1_cfg_pad_i263;
-    input fabric_direct1_cfg_pad_i264;
-    input fabric_direct1_cfg_pad_i265;
-    input fabric_direct1_cfg_pad_i266;
-    input fabric_direct1_cfg_pad_i267;
-    input fabric_direct1_cfg_pad_i268;
-    input fabric_direct1_cfg_pad_i269;
-    input fabric_direct1_cfg_pad_i27;
-    input fabric_direct1_cfg_pad_i270;
-    input fabric_direct1_cfg_pad_i271;
-    input fabric_direct1_cfg_pad_i272;
-    input fabric_direct1_cfg_pad_i273;
-    input fabric_direct1_cfg_pad_i274;
-    input fabric_direct1_cfg_pad_i275;
-    input fabric_direct1_cfg_pad_i276;
-    input fabric_direct1_cfg_pad_i277;
-    input fabric_direct1_cfg_pad_i278;
-    input fabric_direct1_cfg_pad_i279;
-    input fabric_direct1_cfg_pad_i28;
-    input fabric_direct1_cfg_pad_i280;
-    input fabric_direct1_cfg_pad_i281;
-    input fabric_direct1_cfg_pad_i282;
-    input fabric_direct1_cfg_pad_i283;
-    input fabric_direct1_cfg_pad_i284;
-    input fabric_direct1_cfg_pad_i285;
-    input fabric_direct1_cfg_pad_i286;
-    input fabric_direct1_cfg_pad_i287;
-    input fabric_direct1_cfg_pad_i288;
-    input fabric_direct1_cfg_pad_i289;
-    input fabric_direct1_cfg_pad_i29;
-    input fabric_direct1_cfg_pad_i290;
-    input fabric_direct1_cfg_pad_i291;
-    input fabric_direct1_cfg_pad_i292;
-    input fabric_direct1_cfg_pad_i293;
-    input fabric_direct1_cfg_pad_i294;
-    input fabric_direct1_cfg_pad_i295;
-    input fabric_direct1_cfg_pad_i296;
-    input fabric_direct1_cfg_pad_i297;
-    input fabric_direct1_cfg_pad_i298;
-    input fabric_direct1_cfg_pad_i299;
-    input fabric_direct1_cfg_pad_i3;
-    input fabric_direct1_cfg_pad_i30;
-    input fabric_direct1_cfg_pad_i300;
-    input fabric_direct1_cfg_pad_i301;
-    input fabric_direct1_cfg_pad_i302;
-    input fabric_direct1_cfg_pad_i303;
-    input fabric_direct1_cfg_pad_i304;
-    input fabric_direct1_cfg_pad_i305;
-    input fabric_direct1_cfg_pad_i306;
-    input fabric_direct1_cfg_pad_i307;
-    input fabric_direct1_cfg_pad_i308;
-    input fabric_direct1_cfg_pad_i309;
-    input fabric_direct1_cfg_pad_i31;
-    input fabric_direct1_cfg_pad_i310;
-    input fabric_direct1_cfg_pad_i311;
-    input fabric_direct1_cfg_pad_i312;
-    input fabric_direct1_cfg_pad_i313;
-    input fabric_direct1_cfg_pad_i314;
-    input fabric_direct1_cfg_pad_i315;
-    input fabric_direct1_cfg_pad_i316;
-    input fabric_direct1_cfg_pad_i317;
-    input fabric_direct1_cfg_pad_i318;
-    input fabric_direct1_cfg_pad_i319;
-    input fabric_direct1_cfg_pad_i32;
-    input fabric_direct1_cfg_pad_i320;
-    input fabric_direct1_cfg_pad_i321;
-    input fabric_direct1_cfg_pad_i322;
-    input fabric_direct1_cfg_pad_i323;
-    input fabric_direct1_cfg_pad_i324;
-    input fabric_direct1_cfg_pad_i325;
-    input fabric_direct1_cfg_pad_i326;
-    input fabric_direct1_cfg_pad_i327;
-    input fabric_direct1_cfg_pad_i328;
-    input fabric_direct1_cfg_pad_i329;
-    input fabric_direct1_cfg_pad_i33;
-    input fabric_direct1_cfg_pad_i330;
-    input fabric_direct1_cfg_pad_i331;
-    input fabric_direct1_cfg_pad_i332;
-    input fabric_direct1_cfg_pad_i333;
-    input fabric_direct1_cfg_pad_i334;
-    input fabric_direct1_cfg_pad_i335;
-    input fabric_direct1_cfg_pad_i336;
-    input fabric_direct1_cfg_pad_i337;
-    input fabric_direct1_cfg_pad_i338;
-    input fabric_direct1_cfg_pad_i339;
-    input fabric_direct1_cfg_pad_i34;
-    input fabric_direct1_cfg_pad_i340;
-    input fabric_direct1_cfg_pad_i341;
-    input fabric_direct1_cfg_pad_i342;
-    input fabric_direct1_cfg_pad_i343;
-    input fabric_direct1_cfg_pad_i344;
-    input fabric_direct1_cfg_pad_i345;
-    input fabric_direct1_cfg_pad_i346;
-    input fabric_direct1_cfg_pad_i347;
-    input fabric_direct1_cfg_pad_i348;
-    input fabric_direct1_cfg_pad_i349;
-    input fabric_direct1_cfg_pad_i35;
-    input fabric_direct1_cfg_pad_i350;
-    input fabric_direct1_cfg_pad_i351;
-    input fabric_direct1_cfg_pad_i352;
-    input fabric_direct1_cfg_pad_i353;
-    input fabric_direct1_cfg_pad_i354;
-    input fabric_direct1_cfg_pad_i355;
-    input fabric_direct1_cfg_pad_i356;
-    input fabric_direct1_cfg_pad_i357;
-    input fabric_direct1_cfg_pad_i358;
-    input fabric_direct1_cfg_pad_i359;
-    input fabric_direct1_cfg_pad_i36;
-    input fabric_direct1_cfg_pad_i360;
-    input fabric_direct1_cfg_pad_i361;
-    input fabric_direct1_cfg_pad_i362;
-    input fabric_direct1_cfg_pad_i363;
-    input fabric_direct1_cfg_pad_i364;
-    input fabric_direct1_cfg_pad_i365;
-    input fabric_direct1_cfg_pad_i366;
-    input fabric_direct1_cfg_pad_i367;
-    input fabric_direct1_cfg_pad_i368;
-    input fabric_direct1_cfg_pad_i369;
-    input fabric_direct1_cfg_pad_i37;
-    input fabric_direct1_cfg_pad_i370;
-    input fabric_direct1_cfg_pad_i371;
-    input fabric_direct1_cfg_pad_i372;
-    input fabric_direct1_cfg_pad_i373;
-    input fabric_direct1_cfg_pad_i374;
-    input fabric_direct1_cfg_pad_i375;
-    input fabric_direct1_cfg_pad_i376;
-    input fabric_direct1_cfg_pad_i377;
-    input fabric_direct1_cfg_pad_i378;
-    input fabric_direct1_cfg_pad_i379;
-    input fabric_direct1_cfg_pad_i38;
-    input fabric_direct1_cfg_pad_i380;
-    input fabric_direct1_cfg_pad_i381;
-    input fabric_direct1_cfg_pad_i382;
-    input fabric_direct1_cfg_pad_i383;
-    input fabric_direct1_cfg_pad_i384;
-    input fabric_direct1_cfg_pad_i385;
-    input fabric_direct1_cfg_pad_i386;
-    input fabric_direct1_cfg_pad_i387;
-    input fabric_direct1_cfg_pad_i388;
-    input fabric_direct1_cfg_pad_i389;
-    input fabric_direct1_cfg_pad_i39;
-    input fabric_direct1_cfg_pad_i390;
-    input fabric_direct1_cfg_pad_i391;
-    input fabric_direct1_cfg_pad_i392;
-    input fabric_direct1_cfg_pad_i393;
-    input fabric_direct1_cfg_pad_i394;
-    input fabric_direct1_cfg_pad_i395;
-    input fabric_direct1_cfg_pad_i396;
-    input fabric_direct1_cfg_pad_i397;
-    input fabric_direct1_cfg_pad_i398;
-    input fabric_direct1_cfg_pad_i399;
-    input fabric_direct1_cfg_pad_i4;
-    input fabric_direct1_cfg_pad_i40;
-    input fabric_direct1_cfg_pad_i400;
-    input fabric_direct1_cfg_pad_i401;
-    input fabric_direct1_cfg_pad_i402;
-    input fabric_direct1_cfg_pad_i403;
-    input fabric_direct1_cfg_pad_i404;
-    input fabric_direct1_cfg_pad_i405;
-    input fabric_direct1_cfg_pad_i406;
-    input fabric_direct1_cfg_pad_i407;
-    input fabric_direct1_cfg_pad_i408;
-    input fabric_direct1_cfg_pad_i409;
-    input fabric_direct1_cfg_pad_i41;
-    input fabric_direct1_cfg_pad_i410;
-    input fabric_direct1_cfg_pad_i411;
-    input fabric_direct1_cfg_pad_i412;
-    input fabric_direct1_cfg_pad_i413;
-    input fabric_direct1_cfg_pad_i414;
-    input fabric_direct1_cfg_pad_i415;
-    input fabric_direct1_cfg_pad_i416;
-    input fabric_direct1_cfg_pad_i417;
-    input fabric_direct1_cfg_pad_i418;
-    input fabric_direct1_cfg_pad_i419;
-    input fabric_direct1_cfg_pad_i42;
-    input fabric_direct1_cfg_pad_i420;
-    input fabric_direct1_cfg_pad_i421;
-    input fabric_direct1_cfg_pad_i422;
-    input fabric_direct1_cfg_pad_i423;
-    input fabric_direct1_cfg_pad_i424;
-    input fabric_direct1_cfg_pad_i425;
-    input fabric_direct1_cfg_pad_i426;
-    input fabric_direct1_cfg_pad_i427;
-    input fabric_direct1_cfg_pad_i428;
-    input fabric_direct1_cfg_pad_i429;
-    input fabric_direct1_cfg_pad_i43;
-    input fabric_direct1_cfg_pad_i430;
-    input fabric_direct1_cfg_pad_i431;
-    input fabric_direct1_cfg_pad_i432;
-    input fabric_direct1_cfg_pad_i433;
-    input fabric_direct1_cfg_pad_i434;
-    input fabric_direct1_cfg_pad_i435;
-    input fabric_direct1_cfg_pad_i436;
-    input fabric_direct1_cfg_pad_i437;
-    input fabric_direct1_cfg_pad_i438;
-    input fabric_direct1_cfg_pad_i439;
-    input fabric_direct1_cfg_pad_i44;
-    input fabric_direct1_cfg_pad_i440;
-    input fabric_direct1_cfg_pad_i441;
-    input fabric_direct1_cfg_pad_i442;
-    input fabric_direct1_cfg_pad_i443;
-    input fabric_direct1_cfg_pad_i444;
-    input fabric_direct1_cfg_pad_i445;
-    input fabric_direct1_cfg_pad_i446;
-    input fabric_direct1_cfg_pad_i447;
-    input fabric_direct1_cfg_pad_i448;
-    input fabric_direct1_cfg_pad_i449;
-    input fabric_direct1_cfg_pad_i45;
-    input fabric_direct1_cfg_pad_i450;
-    input fabric_direct1_cfg_pad_i451;
-    input fabric_direct1_cfg_pad_i452;
-    input fabric_direct1_cfg_pad_i453;
-    input fabric_direct1_cfg_pad_i454;
-    input fabric_direct1_cfg_pad_i455;
-    input fabric_direct1_cfg_pad_i456;
-    input fabric_direct1_cfg_pad_i457;
-    input fabric_direct1_cfg_pad_i458;
-    input fabric_direct1_cfg_pad_i459;
-    input fabric_direct1_cfg_pad_i46;
-    input fabric_direct1_cfg_pad_i460;
-    input fabric_direct1_cfg_pad_i461;
-    input fabric_direct1_cfg_pad_i462;
-    input fabric_direct1_cfg_pad_i463;
-    input fabric_direct1_cfg_pad_i464;
-    input fabric_direct1_cfg_pad_i465;
-    input fabric_direct1_cfg_pad_i466;
-    input fabric_direct1_cfg_pad_i467;
-    input fabric_direct1_cfg_pad_i468;
-    input fabric_direct1_cfg_pad_i469;
-    input fabric_direct1_cfg_pad_i47;
-    input fabric_direct1_cfg_pad_i470;
-    input fabric_direct1_cfg_pad_i471;
-    input fabric_direct1_cfg_pad_i472;
-    input fabric_direct1_cfg_pad_i473;
-    input fabric_direct1_cfg_pad_i474;
-    input fabric_direct1_cfg_pad_i475;
-    input fabric_direct1_cfg_pad_i476;
-    input fabric_direct1_cfg_pad_i477;
-    input fabric_direct1_cfg_pad_i478;
-    input fabric_direct1_cfg_pad_i479;
-    input fabric_direct1_cfg_pad_i48;
-    input fabric_direct1_cfg_pad_i480;
-    input fabric_direct1_cfg_pad_i49;
-    input fabric_direct1_cfg_pad_i5;
-    input fabric_direct1_cfg_pad_i50;
-    input fabric_direct1_cfg_pad_i51;
-    input fabric_direct1_cfg_pad_i52;
-    input fabric_direct1_cfg_pad_i53;
-    input fabric_direct1_cfg_pad_i54;
-    input fabric_direct1_cfg_pad_i55;
-    input fabric_direct1_cfg_pad_i56;
-    input fabric_direct1_cfg_pad_i57;
-    input fabric_direct1_cfg_pad_i58;
-    input fabric_direct1_cfg_pad_i59;
-    input fabric_direct1_cfg_pad_i6;
-    input fabric_direct1_cfg_pad_i60;
-    input fabric_direct1_cfg_pad_i61;
-    input fabric_direct1_cfg_pad_i62;
-    input fabric_direct1_cfg_pad_i63;
-    input fabric_direct1_cfg_pad_i64;
-    input fabric_direct1_cfg_pad_i65;
-    input fabric_direct1_cfg_pad_i66;
-    input fabric_direct1_cfg_pad_i67;
-    input fabric_direct1_cfg_pad_i68;
-    input fabric_direct1_cfg_pad_i69;
-    input fabric_direct1_cfg_pad_i7;
-    input fabric_direct1_cfg_pad_i70;
-    input fabric_direct1_cfg_pad_i71;
-    input fabric_direct1_cfg_pad_i72;
-    input fabric_direct1_cfg_pad_i73;
-    input fabric_direct1_cfg_pad_i74;
-    input fabric_direct1_cfg_pad_i75;
-    input fabric_direct1_cfg_pad_i76;
-    input fabric_direct1_cfg_pad_i77;
-    input fabric_direct1_cfg_pad_i78;
-    input fabric_direct1_cfg_pad_i79;
-    input fabric_direct1_cfg_pad_i8;
-    input fabric_direct1_cfg_pad_i80;
-    input fabric_direct1_cfg_pad_i81;
-    input fabric_direct1_cfg_pad_i82;
-    input fabric_direct1_cfg_pad_i83;
-    input fabric_direct1_cfg_pad_i84;
-    input fabric_direct1_cfg_pad_i85;
-    input fabric_direct1_cfg_pad_i86;
-    input fabric_direct1_cfg_pad_i87;
-    input fabric_direct1_cfg_pad_i88;
-    input fabric_direct1_cfg_pad_i89;
-    input fabric_direct1_cfg_pad_i9;
-    input fabric_direct1_cfg_pad_i90;
-    input fabric_direct1_cfg_pad_i91;
-    input fabric_direct1_cfg_pad_i92;
-    input fabric_direct1_cfg_pad_i93;
-    input fabric_direct1_cfg_pad_i94;
-    input fabric_direct1_cfg_pad_i95;
-    input fabric_direct1_cfg_pad_i96;
-    input fabric_direct1_cfg_pad_i97;
-    input fabric_direct1_cfg_pad_i98;
-    input fabric_direct1_cfg_pad_i99;
-    input fabric_direct1_clock_fabric_i1;
-    input fabric_direct1_clock_fabric_i2;
-    input fabric_direct1_clock_fabric_i3;
-    input fabric_direct1_clock_fabric_i4;
-    input fabric_direct1_di_ena_i1;
-    input fabric_direct1_di_ena_i10;
-    input fabric_direct1_di_ena_i11;
-    input fabric_direct1_di_ena_i12;
-    input fabric_direct1_di_ena_i13;
-    input fabric_direct1_di_ena_i14;
-    input fabric_direct1_di_ena_i15;
-    input fabric_direct1_di_ena_i16;
-    input fabric_direct1_di_ena_i2;
-    input fabric_direct1_di_ena_i3;
-    input fabric_direct1_di_ena_i4;
-    input fabric_direct1_di_ena_i5;
-    input fabric_direct1_di_ena_i6;
-    input fabric_direct1_di_ena_i7;
-    input fabric_direct1_di_ena_i8;
-    input fabric_direct1_di_ena_i9;
-    output fabric_direct1_di_o1;
-    output fabric_direct1_di_o10;
-    output fabric_direct1_di_o11;
-    output fabric_direct1_di_o12;
-    output fabric_direct1_di_o13;
-    output fabric_direct1_di_o14;
-    output fabric_direct1_di_o15;
-    output fabric_direct1_di_o16;
-    output fabric_direct1_di_o2;
-    output fabric_direct1_di_o3;
-    output fabric_direct1_di_o4;
-    output fabric_direct1_di_o5;
-    output fabric_direct1_di_o6;
-    output fabric_direct1_di_o7;
-    output fabric_direct1_di_o8;
-    output fabric_direct1_di_o9;
-    input fabric_direct1_di_rs_i1;
-    input fabric_direct1_di_rs_i10;
-    input fabric_direct1_di_rs_i11;
-    input fabric_direct1_di_rs_i12;
-    input fabric_direct1_di_rs_i13;
-    input fabric_direct1_di_rs_i14;
-    input fabric_direct1_di_rs_i15;
-    input fabric_direct1_di_rs_i16;
-    input fabric_direct1_di_rs_i2;
-    input fabric_direct1_di_rs_i3;
-    input fabric_direct1_di_rs_i4;
-    input fabric_direct1_di_rs_i5;
-    input fabric_direct1_di_rs_i6;
-    input fabric_direct1_di_rs_i7;
-    input fabric_direct1_di_rs_i8;
-    input fabric_direct1_di_rs_i9;
-    input fabric_direct1_do_ena_i1;
-    input fabric_direct1_do_ena_i10;
-    input fabric_direct1_do_ena_i11;
-    input fabric_direct1_do_ena_i12;
-    input fabric_direct1_do_ena_i13;
-    input fabric_direct1_do_ena_i14;
-    input fabric_direct1_do_ena_i15;
-    input fabric_direct1_do_ena_i16;
-    input fabric_direct1_do_ena_i2;
-    input fabric_direct1_do_ena_i3;
-    input fabric_direct1_do_ena_i4;
-    input fabric_direct1_do_ena_i5;
-    input fabric_direct1_do_ena_i6;
-    input fabric_direct1_do_ena_i7;
-    input fabric_direct1_do_ena_i8;
-    input fabric_direct1_do_ena_i9;
-    input fabric_direct1_do_i1;
-    input fabric_direct1_do_i10;
-    input fabric_direct1_do_i11;
-    input fabric_direct1_do_i12;
-    input fabric_direct1_do_i13;
-    input fabric_direct1_do_i14;
-    input fabric_direct1_do_i15;
-    input fabric_direct1_do_i16;
-    input fabric_direct1_do_i2;
-    input fabric_direct1_do_i3;
-    input fabric_direct1_do_i4;
-    input fabric_direct1_do_i5;
-    input fabric_direct1_do_i6;
-    input fabric_direct1_do_i7;
-    input fabric_direct1_do_i8;
-    input fabric_direct1_do_i9;
-    input fabric_direct1_do_rs_i1;
-    input fabric_direct1_do_rs_i10;
-    input fabric_direct1_do_rs_i11;
-    input fabric_direct1_do_rs_i12;
-    input fabric_direct1_do_rs_i13;
-    input fabric_direct1_do_rs_i14;
-    input fabric_direct1_do_rs_i15;
-    input fabric_direct1_do_rs_i16;
-    input fabric_direct1_do_rs_i2;
-    input fabric_direct1_do_rs_i3;
-    input fabric_direct1_do_rs_i4;
-    input fabric_direct1_do_rs_i5;
-    input fabric_direct1_do_rs_i6;
-    input fabric_direct1_do_rs_i7;
-    input fabric_direct1_do_rs_i8;
-    input fabric_direct1_do_rs_i9;
-    input fabric_direct1_loopback_en_i;
-    input fabric_direct1_loopback_mux_i;
-    input fabric_direct1_oe_ena_i1;
-    input fabric_direct1_oe_ena_i10;
-    input fabric_direct1_oe_ena_i11;
-    input fabric_direct1_oe_ena_i12;
-    input fabric_direct1_oe_ena_i13;
-    input fabric_direct1_oe_ena_i14;
-    input fabric_direct1_oe_ena_i15;
-    input fabric_direct1_oe_ena_i16;
-    input fabric_direct1_oe_ena_i2;
-    input fabric_direct1_oe_ena_i3;
-    input fabric_direct1_oe_ena_i4;
-    input fabric_direct1_oe_ena_i5;
-    input fabric_direct1_oe_ena_i6;
-    input fabric_direct1_oe_ena_i7;
-    input fabric_direct1_oe_ena_i8;
-    input fabric_direct1_oe_ena_i9;
-    input fabric_direct1_oe_i1;
-    input fabric_direct1_oe_i10;
-    input fabric_direct1_oe_i11;
-    input fabric_direct1_oe_i12;
-    input fabric_direct1_oe_i13;
-    input fabric_direct1_oe_i14;
-    input fabric_direct1_oe_i15;
-    input fabric_direct1_oe_i16;
-    input fabric_direct1_oe_i2;
-    input fabric_direct1_oe_i3;
-    input fabric_direct1_oe_i4;
-    input fabric_direct1_oe_i5;
-    input fabric_direct1_oe_i6;
-    input fabric_direct1_oe_i7;
-    input fabric_direct1_oe_i8;
-    input fabric_direct1_oe_i9;
-    input fabric_direct1_oe_rs_i1;
-    input fabric_direct1_oe_rs_i10;
-    input fabric_direct1_oe_rs_i11;
-    input fabric_direct1_oe_rs_i12;
-    input fabric_direct1_oe_rs_i13;
-    input fabric_direct1_oe_rs_i14;
-    input fabric_direct1_oe_rs_i15;
-    input fabric_direct1_oe_rs_i16;
-    input fabric_direct1_oe_rs_i2;
-    input fabric_direct1_oe_rs_i3;
-    input fabric_direct1_oe_rs_i4;
-    input fabric_direct1_oe_rs_i5;
-    input fabric_direct1_oe_rs_i6;
-    input fabric_direct1_oe_rs_i7;
-    input fabric_direct1_oe_rs_i8;
-    input fabric_direct1_oe_rs_i9;
-    input fabric_direct1_scan_en_i;
-    input fabric_direct2_cfg_bank_i1;
-    input fabric_direct2_cfg_bank_i2;
-    input fabric_direct2_cfg_bank_i3;
-    input fabric_direct2_cfg_bank_i4;
-    input fabric_direct2_cfg_pad_i1;
-    input fabric_direct2_cfg_pad_i10;
-    input fabric_direct2_cfg_pad_i100;
-    input fabric_direct2_cfg_pad_i101;
-    input fabric_direct2_cfg_pad_i102;
-    input fabric_direct2_cfg_pad_i103;
-    input fabric_direct2_cfg_pad_i104;
-    input fabric_direct2_cfg_pad_i105;
-    input fabric_direct2_cfg_pad_i106;
-    input fabric_direct2_cfg_pad_i107;
-    input fabric_direct2_cfg_pad_i108;
-    input fabric_direct2_cfg_pad_i109;
-    input fabric_direct2_cfg_pad_i11;
-    input fabric_direct2_cfg_pad_i110;
-    input fabric_direct2_cfg_pad_i111;
-    input fabric_direct2_cfg_pad_i112;
-    input fabric_direct2_cfg_pad_i113;
-    input fabric_direct2_cfg_pad_i114;
-    input fabric_direct2_cfg_pad_i115;
-    input fabric_direct2_cfg_pad_i116;
-    input fabric_direct2_cfg_pad_i117;
-    input fabric_direct2_cfg_pad_i118;
-    input fabric_direct2_cfg_pad_i119;
-    input fabric_direct2_cfg_pad_i12;
-    input fabric_direct2_cfg_pad_i120;
-    input fabric_direct2_cfg_pad_i121;
-    input fabric_direct2_cfg_pad_i122;
-    input fabric_direct2_cfg_pad_i123;
-    input fabric_direct2_cfg_pad_i124;
-    input fabric_direct2_cfg_pad_i125;
-    input fabric_direct2_cfg_pad_i126;
-    input fabric_direct2_cfg_pad_i127;
-    input fabric_direct2_cfg_pad_i128;
-    input fabric_direct2_cfg_pad_i129;
-    input fabric_direct2_cfg_pad_i13;
-    input fabric_direct2_cfg_pad_i130;
-    input fabric_direct2_cfg_pad_i131;
-    input fabric_direct2_cfg_pad_i132;
-    input fabric_direct2_cfg_pad_i133;
-    input fabric_direct2_cfg_pad_i134;
-    input fabric_direct2_cfg_pad_i135;
-    input fabric_direct2_cfg_pad_i136;
-    input fabric_direct2_cfg_pad_i137;
-    input fabric_direct2_cfg_pad_i138;
-    input fabric_direct2_cfg_pad_i139;
-    input fabric_direct2_cfg_pad_i14;
-    input fabric_direct2_cfg_pad_i140;
-    input fabric_direct2_cfg_pad_i141;
-    input fabric_direct2_cfg_pad_i142;
-    input fabric_direct2_cfg_pad_i143;
-    input fabric_direct2_cfg_pad_i144;
-    input fabric_direct2_cfg_pad_i145;
-    input fabric_direct2_cfg_pad_i146;
-    input fabric_direct2_cfg_pad_i147;
-    input fabric_direct2_cfg_pad_i148;
-    input fabric_direct2_cfg_pad_i149;
-    input fabric_direct2_cfg_pad_i15;
-    input fabric_direct2_cfg_pad_i150;
-    input fabric_direct2_cfg_pad_i151;
-    input fabric_direct2_cfg_pad_i152;
-    input fabric_direct2_cfg_pad_i153;
-    input fabric_direct2_cfg_pad_i154;
-    input fabric_direct2_cfg_pad_i155;
-    input fabric_direct2_cfg_pad_i156;
-    input fabric_direct2_cfg_pad_i157;
-    input fabric_direct2_cfg_pad_i158;
-    input fabric_direct2_cfg_pad_i159;
-    input fabric_direct2_cfg_pad_i16;
-    input fabric_direct2_cfg_pad_i160;
-    input fabric_direct2_cfg_pad_i161;
-    input fabric_direct2_cfg_pad_i162;
-    input fabric_direct2_cfg_pad_i163;
-    input fabric_direct2_cfg_pad_i164;
-    input fabric_direct2_cfg_pad_i165;
-    input fabric_direct2_cfg_pad_i166;
-    input fabric_direct2_cfg_pad_i167;
-    input fabric_direct2_cfg_pad_i168;
-    input fabric_direct2_cfg_pad_i169;
-    input fabric_direct2_cfg_pad_i17;
-    input fabric_direct2_cfg_pad_i170;
-    input fabric_direct2_cfg_pad_i171;
-    input fabric_direct2_cfg_pad_i172;
-    input fabric_direct2_cfg_pad_i173;
-    input fabric_direct2_cfg_pad_i174;
-    input fabric_direct2_cfg_pad_i175;
-    input fabric_direct2_cfg_pad_i176;
-    input fabric_direct2_cfg_pad_i177;
-    input fabric_direct2_cfg_pad_i178;
-    input fabric_direct2_cfg_pad_i179;
-    input fabric_direct2_cfg_pad_i18;
-    input fabric_direct2_cfg_pad_i180;
-    input fabric_direct2_cfg_pad_i181;
-    input fabric_direct2_cfg_pad_i182;
-    input fabric_direct2_cfg_pad_i183;
-    input fabric_direct2_cfg_pad_i184;
-    input fabric_direct2_cfg_pad_i185;
-    input fabric_direct2_cfg_pad_i186;
-    input fabric_direct2_cfg_pad_i187;
-    input fabric_direct2_cfg_pad_i188;
-    input fabric_direct2_cfg_pad_i189;
-    input fabric_direct2_cfg_pad_i19;
-    input fabric_direct2_cfg_pad_i190;
-    input fabric_direct2_cfg_pad_i191;
-    input fabric_direct2_cfg_pad_i192;
-    input fabric_direct2_cfg_pad_i193;
-    input fabric_direct2_cfg_pad_i194;
-    input fabric_direct2_cfg_pad_i195;
-    input fabric_direct2_cfg_pad_i196;
-    input fabric_direct2_cfg_pad_i197;
-    input fabric_direct2_cfg_pad_i198;
-    input fabric_direct2_cfg_pad_i199;
-    input fabric_direct2_cfg_pad_i2;
-    input fabric_direct2_cfg_pad_i20;
-    input fabric_direct2_cfg_pad_i200;
-    input fabric_direct2_cfg_pad_i201;
-    input fabric_direct2_cfg_pad_i202;
-    input fabric_direct2_cfg_pad_i203;
-    input fabric_direct2_cfg_pad_i204;
-    input fabric_direct2_cfg_pad_i205;
-    input fabric_direct2_cfg_pad_i206;
-    input fabric_direct2_cfg_pad_i207;
-    input fabric_direct2_cfg_pad_i208;
-    input fabric_direct2_cfg_pad_i209;
-    input fabric_direct2_cfg_pad_i21;
-    input fabric_direct2_cfg_pad_i210;
-    input fabric_direct2_cfg_pad_i211;
-    input fabric_direct2_cfg_pad_i212;
-    input fabric_direct2_cfg_pad_i213;
-    input fabric_direct2_cfg_pad_i214;
-    input fabric_direct2_cfg_pad_i215;
-    input fabric_direct2_cfg_pad_i216;
-    input fabric_direct2_cfg_pad_i217;
-    input fabric_direct2_cfg_pad_i218;
-    input fabric_direct2_cfg_pad_i219;
-    input fabric_direct2_cfg_pad_i22;
-    input fabric_direct2_cfg_pad_i220;
-    input fabric_direct2_cfg_pad_i221;
-    input fabric_direct2_cfg_pad_i222;
-    input fabric_direct2_cfg_pad_i223;
-    input fabric_direct2_cfg_pad_i224;
-    input fabric_direct2_cfg_pad_i225;
-    input fabric_direct2_cfg_pad_i226;
-    input fabric_direct2_cfg_pad_i227;
-    input fabric_direct2_cfg_pad_i228;
-    input fabric_direct2_cfg_pad_i229;
-    input fabric_direct2_cfg_pad_i23;
-    input fabric_direct2_cfg_pad_i230;
-    input fabric_direct2_cfg_pad_i231;
-    input fabric_direct2_cfg_pad_i232;
-    input fabric_direct2_cfg_pad_i233;
-    input fabric_direct2_cfg_pad_i234;
-    input fabric_direct2_cfg_pad_i235;
-    input fabric_direct2_cfg_pad_i236;
-    input fabric_direct2_cfg_pad_i237;
-    input fabric_direct2_cfg_pad_i238;
-    input fabric_direct2_cfg_pad_i239;
-    input fabric_direct2_cfg_pad_i24;
-    input fabric_direct2_cfg_pad_i240;
-    input fabric_direct2_cfg_pad_i241;
-    input fabric_direct2_cfg_pad_i242;
-    input fabric_direct2_cfg_pad_i243;
-    input fabric_direct2_cfg_pad_i244;
-    input fabric_direct2_cfg_pad_i245;
-    input fabric_direct2_cfg_pad_i246;
-    input fabric_direct2_cfg_pad_i247;
-    input fabric_direct2_cfg_pad_i248;
-    input fabric_direct2_cfg_pad_i249;
-    input fabric_direct2_cfg_pad_i25;
-    input fabric_direct2_cfg_pad_i250;
-    input fabric_direct2_cfg_pad_i251;
-    input fabric_direct2_cfg_pad_i252;
-    input fabric_direct2_cfg_pad_i253;
-    input fabric_direct2_cfg_pad_i254;
-    input fabric_direct2_cfg_pad_i255;
-    input fabric_direct2_cfg_pad_i256;
-    input fabric_direct2_cfg_pad_i257;
-    input fabric_direct2_cfg_pad_i258;
-    input fabric_direct2_cfg_pad_i259;
-    input fabric_direct2_cfg_pad_i26;
-    input fabric_direct2_cfg_pad_i260;
-    input fabric_direct2_cfg_pad_i261;
-    input fabric_direct2_cfg_pad_i262;
-    input fabric_direct2_cfg_pad_i263;
-    input fabric_direct2_cfg_pad_i264;
-    input fabric_direct2_cfg_pad_i265;
-    input fabric_direct2_cfg_pad_i266;
-    input fabric_direct2_cfg_pad_i267;
-    input fabric_direct2_cfg_pad_i268;
-    input fabric_direct2_cfg_pad_i269;
-    input fabric_direct2_cfg_pad_i27;
-    input fabric_direct2_cfg_pad_i270;
-    input fabric_direct2_cfg_pad_i271;
-    input fabric_direct2_cfg_pad_i272;
-    input fabric_direct2_cfg_pad_i273;
-    input fabric_direct2_cfg_pad_i274;
-    input fabric_direct2_cfg_pad_i275;
-    input fabric_direct2_cfg_pad_i276;
-    input fabric_direct2_cfg_pad_i277;
-    input fabric_direct2_cfg_pad_i278;
-    input fabric_direct2_cfg_pad_i279;
-    input fabric_direct2_cfg_pad_i28;
-    input fabric_direct2_cfg_pad_i280;
-    input fabric_direct2_cfg_pad_i281;
-    input fabric_direct2_cfg_pad_i282;
-    input fabric_direct2_cfg_pad_i283;
-    input fabric_direct2_cfg_pad_i284;
-    input fabric_direct2_cfg_pad_i285;
-    input fabric_direct2_cfg_pad_i286;
-    input fabric_direct2_cfg_pad_i287;
-    input fabric_direct2_cfg_pad_i288;
-    input fabric_direct2_cfg_pad_i289;
-    input fabric_direct2_cfg_pad_i29;
-    input fabric_direct2_cfg_pad_i290;
-    input fabric_direct2_cfg_pad_i291;
-    input fabric_direct2_cfg_pad_i292;
-    input fabric_direct2_cfg_pad_i293;
-    input fabric_direct2_cfg_pad_i294;
-    input fabric_direct2_cfg_pad_i295;
-    input fabric_direct2_cfg_pad_i296;
-    input fabric_direct2_cfg_pad_i297;
-    input fabric_direct2_cfg_pad_i298;
-    input fabric_direct2_cfg_pad_i299;
-    input fabric_direct2_cfg_pad_i3;
-    input fabric_direct2_cfg_pad_i30;
-    input fabric_direct2_cfg_pad_i300;
-    input fabric_direct2_cfg_pad_i301;
-    input fabric_direct2_cfg_pad_i302;
-    input fabric_direct2_cfg_pad_i303;
-    input fabric_direct2_cfg_pad_i304;
-    input fabric_direct2_cfg_pad_i305;
-    input fabric_direct2_cfg_pad_i306;
-    input fabric_direct2_cfg_pad_i307;
-    input fabric_direct2_cfg_pad_i308;
-    input fabric_direct2_cfg_pad_i309;
-    input fabric_direct2_cfg_pad_i31;
-    input fabric_direct2_cfg_pad_i310;
-    input fabric_direct2_cfg_pad_i311;
-    input fabric_direct2_cfg_pad_i312;
-    input fabric_direct2_cfg_pad_i313;
-    input fabric_direct2_cfg_pad_i314;
-    input fabric_direct2_cfg_pad_i315;
-    input fabric_direct2_cfg_pad_i316;
-    input fabric_direct2_cfg_pad_i317;
-    input fabric_direct2_cfg_pad_i318;
-    input fabric_direct2_cfg_pad_i319;
-    input fabric_direct2_cfg_pad_i32;
-    input fabric_direct2_cfg_pad_i320;
-    input fabric_direct2_cfg_pad_i321;
-    input fabric_direct2_cfg_pad_i322;
-    input fabric_direct2_cfg_pad_i323;
-    input fabric_direct2_cfg_pad_i324;
-    input fabric_direct2_cfg_pad_i325;
-    input fabric_direct2_cfg_pad_i326;
-    input fabric_direct2_cfg_pad_i327;
-    input fabric_direct2_cfg_pad_i328;
-    input fabric_direct2_cfg_pad_i329;
-    input fabric_direct2_cfg_pad_i33;
-    input fabric_direct2_cfg_pad_i330;
-    input fabric_direct2_cfg_pad_i331;
-    input fabric_direct2_cfg_pad_i332;
-    input fabric_direct2_cfg_pad_i333;
-    input fabric_direct2_cfg_pad_i334;
-    input fabric_direct2_cfg_pad_i335;
-    input fabric_direct2_cfg_pad_i336;
-    input fabric_direct2_cfg_pad_i337;
-    input fabric_direct2_cfg_pad_i338;
-    input fabric_direct2_cfg_pad_i339;
-    input fabric_direct2_cfg_pad_i34;
-    input fabric_direct2_cfg_pad_i340;
-    input fabric_direct2_cfg_pad_i341;
-    input fabric_direct2_cfg_pad_i342;
-    input fabric_direct2_cfg_pad_i343;
-    input fabric_direct2_cfg_pad_i344;
-    input fabric_direct2_cfg_pad_i345;
-    input fabric_direct2_cfg_pad_i346;
-    input fabric_direct2_cfg_pad_i347;
-    input fabric_direct2_cfg_pad_i348;
-    input fabric_direct2_cfg_pad_i349;
-    input fabric_direct2_cfg_pad_i35;
-    input fabric_direct2_cfg_pad_i350;
-    input fabric_direct2_cfg_pad_i351;
-    input fabric_direct2_cfg_pad_i352;
-    input fabric_direct2_cfg_pad_i353;
-    input fabric_direct2_cfg_pad_i354;
-    input fabric_direct2_cfg_pad_i355;
-    input fabric_direct2_cfg_pad_i356;
-    input fabric_direct2_cfg_pad_i357;
-    input fabric_direct2_cfg_pad_i358;
-    input fabric_direct2_cfg_pad_i359;
-    input fabric_direct2_cfg_pad_i36;
-    input fabric_direct2_cfg_pad_i360;
-    input fabric_direct2_cfg_pad_i361;
-    input fabric_direct2_cfg_pad_i362;
-    input fabric_direct2_cfg_pad_i363;
-    input fabric_direct2_cfg_pad_i364;
-    input fabric_direct2_cfg_pad_i365;
-    input fabric_direct2_cfg_pad_i366;
-    input fabric_direct2_cfg_pad_i367;
-    input fabric_direct2_cfg_pad_i368;
-    input fabric_direct2_cfg_pad_i369;
-    input fabric_direct2_cfg_pad_i37;
-    input fabric_direct2_cfg_pad_i370;
-    input fabric_direct2_cfg_pad_i371;
-    input fabric_direct2_cfg_pad_i372;
-    input fabric_direct2_cfg_pad_i373;
-    input fabric_direct2_cfg_pad_i374;
-    input fabric_direct2_cfg_pad_i375;
-    input fabric_direct2_cfg_pad_i376;
-    input fabric_direct2_cfg_pad_i377;
-    input fabric_direct2_cfg_pad_i378;
-    input fabric_direct2_cfg_pad_i379;
-    input fabric_direct2_cfg_pad_i38;
-    input fabric_direct2_cfg_pad_i380;
-    input fabric_direct2_cfg_pad_i381;
-    input fabric_direct2_cfg_pad_i382;
-    input fabric_direct2_cfg_pad_i383;
-    input fabric_direct2_cfg_pad_i384;
-    input fabric_direct2_cfg_pad_i385;
-    input fabric_direct2_cfg_pad_i386;
-    input fabric_direct2_cfg_pad_i387;
-    input fabric_direct2_cfg_pad_i388;
-    input fabric_direct2_cfg_pad_i389;
-    input fabric_direct2_cfg_pad_i39;
-    input fabric_direct2_cfg_pad_i390;
-    input fabric_direct2_cfg_pad_i391;
-    input fabric_direct2_cfg_pad_i392;
-    input fabric_direct2_cfg_pad_i393;
-    input fabric_direct2_cfg_pad_i394;
-    input fabric_direct2_cfg_pad_i395;
-    input fabric_direct2_cfg_pad_i396;
-    input fabric_direct2_cfg_pad_i397;
-    input fabric_direct2_cfg_pad_i398;
-    input fabric_direct2_cfg_pad_i399;
-    input fabric_direct2_cfg_pad_i4;
-    input fabric_direct2_cfg_pad_i40;
-    input fabric_direct2_cfg_pad_i400;
-    input fabric_direct2_cfg_pad_i401;
-    input fabric_direct2_cfg_pad_i402;
-    input fabric_direct2_cfg_pad_i403;
-    input fabric_direct2_cfg_pad_i404;
-    input fabric_direct2_cfg_pad_i405;
-    input fabric_direct2_cfg_pad_i406;
-    input fabric_direct2_cfg_pad_i407;
-    input fabric_direct2_cfg_pad_i408;
-    input fabric_direct2_cfg_pad_i409;
-    input fabric_direct2_cfg_pad_i41;
-    input fabric_direct2_cfg_pad_i410;
-    input fabric_direct2_cfg_pad_i411;
-    input fabric_direct2_cfg_pad_i412;
-    input fabric_direct2_cfg_pad_i413;
-    input fabric_direct2_cfg_pad_i414;
-    input fabric_direct2_cfg_pad_i415;
-    input fabric_direct2_cfg_pad_i416;
-    input fabric_direct2_cfg_pad_i417;
-    input fabric_direct2_cfg_pad_i418;
-    input fabric_direct2_cfg_pad_i419;
-    input fabric_direct2_cfg_pad_i42;
-    input fabric_direct2_cfg_pad_i420;
-    input fabric_direct2_cfg_pad_i421;
-    input fabric_direct2_cfg_pad_i422;
-    input fabric_direct2_cfg_pad_i423;
-    input fabric_direct2_cfg_pad_i424;
-    input fabric_direct2_cfg_pad_i425;
-    input fabric_direct2_cfg_pad_i426;
-    input fabric_direct2_cfg_pad_i427;
-    input fabric_direct2_cfg_pad_i428;
-    input fabric_direct2_cfg_pad_i429;
-    input fabric_direct2_cfg_pad_i43;
-    input fabric_direct2_cfg_pad_i430;
-    input fabric_direct2_cfg_pad_i431;
-    input fabric_direct2_cfg_pad_i432;
-    input fabric_direct2_cfg_pad_i433;
-    input fabric_direct2_cfg_pad_i434;
-    input fabric_direct2_cfg_pad_i435;
-    input fabric_direct2_cfg_pad_i436;
-    input fabric_direct2_cfg_pad_i437;
-    input fabric_direct2_cfg_pad_i438;
-    input fabric_direct2_cfg_pad_i439;
-    input fabric_direct2_cfg_pad_i44;
-    input fabric_direct2_cfg_pad_i440;
-    input fabric_direct2_cfg_pad_i441;
-    input fabric_direct2_cfg_pad_i442;
-    input fabric_direct2_cfg_pad_i443;
-    input fabric_direct2_cfg_pad_i444;
-    input fabric_direct2_cfg_pad_i445;
-    input fabric_direct2_cfg_pad_i446;
-    input fabric_direct2_cfg_pad_i447;
-    input fabric_direct2_cfg_pad_i448;
-    input fabric_direct2_cfg_pad_i449;
-    input fabric_direct2_cfg_pad_i45;
-    input fabric_direct2_cfg_pad_i450;
-    input fabric_direct2_cfg_pad_i451;
-    input fabric_direct2_cfg_pad_i452;
-    input fabric_direct2_cfg_pad_i453;
-    input fabric_direct2_cfg_pad_i454;
-    input fabric_direct2_cfg_pad_i455;
-    input fabric_direct2_cfg_pad_i456;
-    input fabric_direct2_cfg_pad_i457;
-    input fabric_direct2_cfg_pad_i458;
-    input fabric_direct2_cfg_pad_i459;
-    input fabric_direct2_cfg_pad_i46;
-    input fabric_direct2_cfg_pad_i460;
-    input fabric_direct2_cfg_pad_i461;
-    input fabric_direct2_cfg_pad_i462;
-    input fabric_direct2_cfg_pad_i463;
-    input fabric_direct2_cfg_pad_i464;
-    input fabric_direct2_cfg_pad_i465;
-    input fabric_direct2_cfg_pad_i466;
-    input fabric_direct2_cfg_pad_i467;
-    input fabric_direct2_cfg_pad_i468;
-    input fabric_direct2_cfg_pad_i469;
-    input fabric_direct2_cfg_pad_i47;
-    input fabric_direct2_cfg_pad_i470;
-    input fabric_direct2_cfg_pad_i471;
-    input fabric_direct2_cfg_pad_i472;
-    input fabric_direct2_cfg_pad_i473;
-    input fabric_direct2_cfg_pad_i474;
-    input fabric_direct2_cfg_pad_i475;
-    input fabric_direct2_cfg_pad_i476;
-    input fabric_direct2_cfg_pad_i477;
-    input fabric_direct2_cfg_pad_i478;
-    input fabric_direct2_cfg_pad_i479;
-    input fabric_direct2_cfg_pad_i48;
-    input fabric_direct2_cfg_pad_i480;
-    input fabric_direct2_cfg_pad_i481;
-    input fabric_direct2_cfg_pad_i482;
-    input fabric_direct2_cfg_pad_i483;
-    input fabric_direct2_cfg_pad_i484;
-    input fabric_direct2_cfg_pad_i485;
-    input fabric_direct2_cfg_pad_i486;
-    input fabric_direct2_cfg_pad_i487;
-    input fabric_direct2_cfg_pad_i488;
-    input fabric_direct2_cfg_pad_i489;
-    input fabric_direct2_cfg_pad_i49;
-    input fabric_direct2_cfg_pad_i490;
-    input fabric_direct2_cfg_pad_i491;
-    input fabric_direct2_cfg_pad_i492;
-    input fabric_direct2_cfg_pad_i493;
-    input fabric_direct2_cfg_pad_i494;
-    input fabric_direct2_cfg_pad_i495;
-    input fabric_direct2_cfg_pad_i496;
-    input fabric_direct2_cfg_pad_i497;
-    input fabric_direct2_cfg_pad_i498;
-    input fabric_direct2_cfg_pad_i499;
-    input fabric_direct2_cfg_pad_i5;
-    input fabric_direct2_cfg_pad_i50;
-    input fabric_direct2_cfg_pad_i500;
-    input fabric_direct2_cfg_pad_i501;
-    input fabric_direct2_cfg_pad_i502;
-    input fabric_direct2_cfg_pad_i503;
-    input fabric_direct2_cfg_pad_i504;
-    input fabric_direct2_cfg_pad_i505;
-    input fabric_direct2_cfg_pad_i506;
-    input fabric_direct2_cfg_pad_i507;
-    input fabric_direct2_cfg_pad_i508;
-    input fabric_direct2_cfg_pad_i509;
-    input fabric_direct2_cfg_pad_i51;
-    input fabric_direct2_cfg_pad_i510;
-    input fabric_direct2_cfg_pad_i511;
-    input fabric_direct2_cfg_pad_i512;
-    input fabric_direct2_cfg_pad_i513;
-    input fabric_direct2_cfg_pad_i514;
-    input fabric_direct2_cfg_pad_i515;
-    input fabric_direct2_cfg_pad_i516;
-    input fabric_direct2_cfg_pad_i517;
-    input fabric_direct2_cfg_pad_i518;
-    input fabric_direct2_cfg_pad_i519;
-    input fabric_direct2_cfg_pad_i52;
-    input fabric_direct2_cfg_pad_i520;
-    input fabric_direct2_cfg_pad_i521;
-    input fabric_direct2_cfg_pad_i522;
-    input fabric_direct2_cfg_pad_i523;
-    input fabric_direct2_cfg_pad_i524;
-    input fabric_direct2_cfg_pad_i525;
-    input fabric_direct2_cfg_pad_i526;
-    input fabric_direct2_cfg_pad_i527;
-    input fabric_direct2_cfg_pad_i528;
-    input fabric_direct2_cfg_pad_i529;
-    input fabric_direct2_cfg_pad_i53;
-    input fabric_direct2_cfg_pad_i530;
-    input fabric_direct2_cfg_pad_i531;
-    input fabric_direct2_cfg_pad_i532;
-    input fabric_direct2_cfg_pad_i533;
-    input fabric_direct2_cfg_pad_i534;
-    input fabric_direct2_cfg_pad_i535;
-    input fabric_direct2_cfg_pad_i536;
-    input fabric_direct2_cfg_pad_i537;
-    input fabric_direct2_cfg_pad_i538;
-    input fabric_direct2_cfg_pad_i539;
-    input fabric_direct2_cfg_pad_i54;
-    input fabric_direct2_cfg_pad_i540;
-    input fabric_direct2_cfg_pad_i541;
-    input fabric_direct2_cfg_pad_i542;
-    input fabric_direct2_cfg_pad_i543;
-    input fabric_direct2_cfg_pad_i544;
-    input fabric_direct2_cfg_pad_i545;
-    input fabric_direct2_cfg_pad_i546;
-    input fabric_direct2_cfg_pad_i547;
-    input fabric_direct2_cfg_pad_i548;
-    input fabric_direct2_cfg_pad_i549;
-    input fabric_direct2_cfg_pad_i55;
-    input fabric_direct2_cfg_pad_i550;
-    input fabric_direct2_cfg_pad_i551;
-    input fabric_direct2_cfg_pad_i552;
-    input fabric_direct2_cfg_pad_i553;
-    input fabric_direct2_cfg_pad_i554;
-    input fabric_direct2_cfg_pad_i555;
-    input fabric_direct2_cfg_pad_i556;
-    input fabric_direct2_cfg_pad_i557;
-    input fabric_direct2_cfg_pad_i558;
-    input fabric_direct2_cfg_pad_i559;
-    input fabric_direct2_cfg_pad_i56;
-    input fabric_direct2_cfg_pad_i560;
-    input fabric_direct2_cfg_pad_i561;
-    input fabric_direct2_cfg_pad_i562;
-    input fabric_direct2_cfg_pad_i563;
-    input fabric_direct2_cfg_pad_i564;
-    input fabric_direct2_cfg_pad_i565;
-    input fabric_direct2_cfg_pad_i566;
-    input fabric_direct2_cfg_pad_i567;
-    input fabric_direct2_cfg_pad_i568;
-    input fabric_direct2_cfg_pad_i569;
-    input fabric_direct2_cfg_pad_i57;
-    input fabric_direct2_cfg_pad_i570;
-    input fabric_direct2_cfg_pad_i571;
-    input fabric_direct2_cfg_pad_i572;
-    input fabric_direct2_cfg_pad_i573;
-    input fabric_direct2_cfg_pad_i574;
-    input fabric_direct2_cfg_pad_i575;
-    input fabric_direct2_cfg_pad_i576;
-    input fabric_direct2_cfg_pad_i577;
-    input fabric_direct2_cfg_pad_i578;
-    input fabric_direct2_cfg_pad_i579;
-    input fabric_direct2_cfg_pad_i58;
-    input fabric_direct2_cfg_pad_i580;
-    input fabric_direct2_cfg_pad_i581;
-    input fabric_direct2_cfg_pad_i582;
-    input fabric_direct2_cfg_pad_i583;
-    input fabric_direct2_cfg_pad_i584;
-    input fabric_direct2_cfg_pad_i585;
-    input fabric_direct2_cfg_pad_i586;
-    input fabric_direct2_cfg_pad_i587;
-    input fabric_direct2_cfg_pad_i588;
-    input fabric_direct2_cfg_pad_i589;
-    input fabric_direct2_cfg_pad_i59;
-    input fabric_direct2_cfg_pad_i590;
-    input fabric_direct2_cfg_pad_i591;
-    input fabric_direct2_cfg_pad_i592;
-    input fabric_direct2_cfg_pad_i593;
-    input fabric_direct2_cfg_pad_i594;
-    input fabric_direct2_cfg_pad_i595;
-    input fabric_direct2_cfg_pad_i596;
-    input fabric_direct2_cfg_pad_i597;
-    input fabric_direct2_cfg_pad_i598;
-    input fabric_direct2_cfg_pad_i599;
-    input fabric_direct2_cfg_pad_i6;
-    input fabric_direct2_cfg_pad_i60;
-    input fabric_direct2_cfg_pad_i600;
-    input fabric_direct2_cfg_pad_i601;
-    input fabric_direct2_cfg_pad_i602;
-    input fabric_direct2_cfg_pad_i603;
-    input fabric_direct2_cfg_pad_i604;
-    input fabric_direct2_cfg_pad_i605;
-    input fabric_direct2_cfg_pad_i606;
-    input fabric_direct2_cfg_pad_i607;
-    input fabric_direct2_cfg_pad_i608;
-    input fabric_direct2_cfg_pad_i609;
-    input fabric_direct2_cfg_pad_i61;
-    input fabric_direct2_cfg_pad_i610;
-    input fabric_direct2_cfg_pad_i611;
-    input fabric_direct2_cfg_pad_i612;
-    input fabric_direct2_cfg_pad_i613;
-    input fabric_direct2_cfg_pad_i614;
-    input fabric_direct2_cfg_pad_i615;
-    input fabric_direct2_cfg_pad_i616;
-    input fabric_direct2_cfg_pad_i617;
-    input fabric_direct2_cfg_pad_i618;
-    input fabric_direct2_cfg_pad_i619;
-    input fabric_direct2_cfg_pad_i62;
-    input fabric_direct2_cfg_pad_i620;
-    input fabric_direct2_cfg_pad_i621;
-    input fabric_direct2_cfg_pad_i622;
-    input fabric_direct2_cfg_pad_i623;
-    input fabric_direct2_cfg_pad_i624;
-    input fabric_direct2_cfg_pad_i625;
-    input fabric_direct2_cfg_pad_i626;
-    input fabric_direct2_cfg_pad_i627;
-    input fabric_direct2_cfg_pad_i628;
-    input fabric_direct2_cfg_pad_i629;
-    input fabric_direct2_cfg_pad_i63;
-    input fabric_direct2_cfg_pad_i630;
-    input fabric_direct2_cfg_pad_i631;
-    input fabric_direct2_cfg_pad_i632;
-    input fabric_direct2_cfg_pad_i633;
-    input fabric_direct2_cfg_pad_i634;
-    input fabric_direct2_cfg_pad_i635;
-    input fabric_direct2_cfg_pad_i636;
-    input fabric_direct2_cfg_pad_i637;
-    input fabric_direct2_cfg_pad_i638;
-    input fabric_direct2_cfg_pad_i639;
-    input fabric_direct2_cfg_pad_i64;
-    input fabric_direct2_cfg_pad_i640;
-    input fabric_direct2_cfg_pad_i641;
-    input fabric_direct2_cfg_pad_i642;
-    input fabric_direct2_cfg_pad_i643;
-    input fabric_direct2_cfg_pad_i644;
-    input fabric_direct2_cfg_pad_i645;
-    input fabric_direct2_cfg_pad_i646;
-    input fabric_direct2_cfg_pad_i647;
-    input fabric_direct2_cfg_pad_i648;
-    input fabric_direct2_cfg_pad_i649;
-    input fabric_direct2_cfg_pad_i65;
-    input fabric_direct2_cfg_pad_i650;
-    input fabric_direct2_cfg_pad_i651;
-    input fabric_direct2_cfg_pad_i652;
-    input fabric_direct2_cfg_pad_i653;
-    input fabric_direct2_cfg_pad_i654;
-    input fabric_direct2_cfg_pad_i655;
-    input fabric_direct2_cfg_pad_i656;
-    input fabric_direct2_cfg_pad_i657;
-    input fabric_direct2_cfg_pad_i658;
-    input fabric_direct2_cfg_pad_i659;
-    input fabric_direct2_cfg_pad_i66;
-    input fabric_direct2_cfg_pad_i660;
-    input fabric_direct2_cfg_pad_i661;
-    input fabric_direct2_cfg_pad_i662;
-    input fabric_direct2_cfg_pad_i663;
-    input fabric_direct2_cfg_pad_i664;
-    input fabric_direct2_cfg_pad_i665;
-    input fabric_direct2_cfg_pad_i666;
-    input fabric_direct2_cfg_pad_i667;
-    input fabric_direct2_cfg_pad_i668;
-    input fabric_direct2_cfg_pad_i669;
-    input fabric_direct2_cfg_pad_i67;
-    input fabric_direct2_cfg_pad_i670;
-    input fabric_direct2_cfg_pad_i671;
-    input fabric_direct2_cfg_pad_i672;
-    input fabric_direct2_cfg_pad_i673;
-    input fabric_direct2_cfg_pad_i674;
-    input fabric_direct2_cfg_pad_i675;
-    input fabric_direct2_cfg_pad_i676;
-    input fabric_direct2_cfg_pad_i677;
-    input fabric_direct2_cfg_pad_i678;
-    input fabric_direct2_cfg_pad_i679;
-    input fabric_direct2_cfg_pad_i68;
-    input fabric_direct2_cfg_pad_i680;
-    input fabric_direct2_cfg_pad_i681;
-    input fabric_direct2_cfg_pad_i682;
-    input fabric_direct2_cfg_pad_i683;
-    input fabric_direct2_cfg_pad_i684;
-    input fabric_direct2_cfg_pad_i685;
-    input fabric_direct2_cfg_pad_i686;
-    input fabric_direct2_cfg_pad_i687;
-    input fabric_direct2_cfg_pad_i688;
-    input fabric_direct2_cfg_pad_i689;
-    input fabric_direct2_cfg_pad_i69;
-    input fabric_direct2_cfg_pad_i690;
-    input fabric_direct2_cfg_pad_i691;
-    input fabric_direct2_cfg_pad_i692;
-    input fabric_direct2_cfg_pad_i693;
-    input fabric_direct2_cfg_pad_i694;
-    input fabric_direct2_cfg_pad_i695;
-    input fabric_direct2_cfg_pad_i696;
-    input fabric_direct2_cfg_pad_i697;
-    input fabric_direct2_cfg_pad_i698;
-    input fabric_direct2_cfg_pad_i699;
-    input fabric_direct2_cfg_pad_i7;
-    input fabric_direct2_cfg_pad_i70;
-    input fabric_direct2_cfg_pad_i700;
-    input fabric_direct2_cfg_pad_i701;
-    input fabric_direct2_cfg_pad_i702;
-    input fabric_direct2_cfg_pad_i703;
-    input fabric_direct2_cfg_pad_i704;
-    input fabric_direct2_cfg_pad_i705;
-    input fabric_direct2_cfg_pad_i706;
-    input fabric_direct2_cfg_pad_i707;
-    input fabric_direct2_cfg_pad_i708;
-    input fabric_direct2_cfg_pad_i709;
-    input fabric_direct2_cfg_pad_i71;
-    input fabric_direct2_cfg_pad_i710;
-    input fabric_direct2_cfg_pad_i711;
-    input fabric_direct2_cfg_pad_i712;
-    input fabric_direct2_cfg_pad_i713;
-    input fabric_direct2_cfg_pad_i714;
-    input fabric_direct2_cfg_pad_i715;
-    input fabric_direct2_cfg_pad_i716;
-    input fabric_direct2_cfg_pad_i717;
-    input fabric_direct2_cfg_pad_i718;
-    input fabric_direct2_cfg_pad_i719;
-    input fabric_direct2_cfg_pad_i72;
-    input fabric_direct2_cfg_pad_i720;
-    input fabric_direct2_cfg_pad_i73;
-    input fabric_direct2_cfg_pad_i74;
-    input fabric_direct2_cfg_pad_i75;
-    input fabric_direct2_cfg_pad_i76;
-    input fabric_direct2_cfg_pad_i77;
-    input fabric_direct2_cfg_pad_i78;
-    input fabric_direct2_cfg_pad_i79;
-    input fabric_direct2_cfg_pad_i8;
-    input fabric_direct2_cfg_pad_i80;
-    input fabric_direct2_cfg_pad_i81;
-    input fabric_direct2_cfg_pad_i82;
-    input fabric_direct2_cfg_pad_i83;
-    input fabric_direct2_cfg_pad_i84;
-    input fabric_direct2_cfg_pad_i85;
-    input fabric_direct2_cfg_pad_i86;
-    input fabric_direct2_cfg_pad_i87;
-    input fabric_direct2_cfg_pad_i88;
-    input fabric_direct2_cfg_pad_i89;
-    input fabric_direct2_cfg_pad_i9;
-    input fabric_direct2_cfg_pad_i90;
-    input fabric_direct2_cfg_pad_i91;
-    input fabric_direct2_cfg_pad_i92;
-    input fabric_direct2_cfg_pad_i93;
-    input fabric_direct2_cfg_pad_i94;
-    input fabric_direct2_cfg_pad_i95;
-    input fabric_direct2_cfg_pad_i96;
-    input fabric_direct2_cfg_pad_i97;
-    input fabric_direct2_cfg_pad_i98;
-    input fabric_direct2_cfg_pad_i99;
-    input fabric_direct2_clock_fabric_i1;
-    input fabric_direct2_clock_fabric_i2;
-    input fabric_direct2_clock_fabric_i3;
-    input fabric_direct2_clock_fabric_i4;
-    input fabric_direct2_di_ena_i1;
-    input fabric_direct2_di_ena_i10;
-    input fabric_direct2_di_ena_i11;
-    input fabric_direct2_di_ena_i12;
-    input fabric_direct2_di_ena_i13;
-    input fabric_direct2_di_ena_i14;
-    input fabric_direct2_di_ena_i15;
-    input fabric_direct2_di_ena_i16;
-    input fabric_direct2_di_ena_i17;
-    input fabric_direct2_di_ena_i18;
-    input fabric_direct2_di_ena_i19;
-    input fabric_direct2_di_ena_i2;
-    input fabric_direct2_di_ena_i20;
-    input fabric_direct2_di_ena_i21;
-    input fabric_direct2_di_ena_i22;
-    input fabric_direct2_di_ena_i23;
-    input fabric_direct2_di_ena_i24;
-    input fabric_direct2_di_ena_i3;
-    input fabric_direct2_di_ena_i4;
-    input fabric_direct2_di_ena_i5;
-    input fabric_direct2_di_ena_i6;
-    input fabric_direct2_di_ena_i7;
-    input fabric_direct2_di_ena_i8;
-    input fabric_direct2_di_ena_i9;
-    output fabric_direct2_di_o1;
-    output fabric_direct2_di_o10;
-    output fabric_direct2_di_o11;
-    output fabric_direct2_di_o12;
-    output fabric_direct2_di_o13;
-    output fabric_direct2_di_o14;
-    output fabric_direct2_di_o15;
-    output fabric_direct2_di_o16;
-    output fabric_direct2_di_o17;
-    output fabric_direct2_di_o18;
-    output fabric_direct2_di_o19;
-    output fabric_direct2_di_o2;
-    output fabric_direct2_di_o20;
-    output fabric_direct2_di_o21;
-    output fabric_direct2_di_o22;
-    output fabric_direct2_di_o23;
-    output fabric_direct2_di_o24;
-    output fabric_direct2_di_o3;
-    output fabric_direct2_di_o4;
-    output fabric_direct2_di_o5;
-    output fabric_direct2_di_o6;
-    output fabric_direct2_di_o7;
-    output fabric_direct2_di_o8;
-    output fabric_direct2_di_o9;
-    input fabric_direct2_di_rs_i1;
-    input fabric_direct2_di_rs_i10;
-    input fabric_direct2_di_rs_i11;
-    input fabric_direct2_di_rs_i12;
-    input fabric_direct2_di_rs_i13;
-    input fabric_direct2_di_rs_i14;
-    input fabric_direct2_di_rs_i15;
-    input fabric_direct2_di_rs_i16;
-    input fabric_direct2_di_rs_i17;
-    input fabric_direct2_di_rs_i18;
-    input fabric_direct2_di_rs_i19;
-    input fabric_direct2_di_rs_i2;
-    input fabric_direct2_di_rs_i20;
-    input fabric_direct2_di_rs_i21;
-    input fabric_direct2_di_rs_i22;
-    input fabric_direct2_di_rs_i23;
-    input fabric_direct2_di_rs_i24;
-    input fabric_direct2_di_rs_i3;
-    input fabric_direct2_di_rs_i4;
-    input fabric_direct2_di_rs_i5;
-    input fabric_direct2_di_rs_i6;
-    input fabric_direct2_di_rs_i7;
-    input fabric_direct2_di_rs_i8;
-    input fabric_direct2_di_rs_i9;
-    input fabric_direct2_do_ena_i1;
-    input fabric_direct2_do_ena_i10;
-    input fabric_direct2_do_ena_i11;
-    input fabric_direct2_do_ena_i12;
-    input fabric_direct2_do_ena_i13;
-    input fabric_direct2_do_ena_i14;
-    input fabric_direct2_do_ena_i15;
-    input fabric_direct2_do_ena_i16;
-    input fabric_direct2_do_ena_i17;
-    input fabric_direct2_do_ena_i18;
-    input fabric_direct2_do_ena_i19;
-    input fabric_direct2_do_ena_i2;
-    input fabric_direct2_do_ena_i20;
-    input fabric_direct2_do_ena_i21;
-    input fabric_direct2_do_ena_i22;
-    input fabric_direct2_do_ena_i23;
-    input fabric_direct2_do_ena_i24;
-    input fabric_direct2_do_ena_i3;
-    input fabric_direct2_do_ena_i4;
-    input fabric_direct2_do_ena_i5;
-    input fabric_direct2_do_ena_i6;
-    input fabric_direct2_do_ena_i7;
-    input fabric_direct2_do_ena_i8;
-    input fabric_direct2_do_ena_i9;
-    input fabric_direct2_do_i1;
-    input fabric_direct2_do_i10;
-    input fabric_direct2_do_i11;
-    input fabric_direct2_do_i12;
-    input fabric_direct2_do_i13;
-    input fabric_direct2_do_i14;
-    input fabric_direct2_do_i15;
-    input fabric_direct2_do_i16;
-    input fabric_direct2_do_i17;
-    input fabric_direct2_do_i18;
-    input fabric_direct2_do_i19;
-    input fabric_direct2_do_i2;
-    input fabric_direct2_do_i20;
-    input fabric_direct2_do_i21;
-    input fabric_direct2_do_i22;
-    input fabric_direct2_do_i23;
-    input fabric_direct2_do_i24;
-    input fabric_direct2_do_i3;
-    input fabric_direct2_do_i4;
-    input fabric_direct2_do_i5;
-    input fabric_direct2_do_i6;
-    input fabric_direct2_do_i7;
-    input fabric_direct2_do_i8;
-    input fabric_direct2_do_i9;
-    input fabric_direct2_do_rs_i1;
-    input fabric_direct2_do_rs_i10;
-    input fabric_direct2_do_rs_i11;
-    input fabric_direct2_do_rs_i12;
-    input fabric_direct2_do_rs_i13;
-    input fabric_direct2_do_rs_i14;
-    input fabric_direct2_do_rs_i15;
-    input fabric_direct2_do_rs_i16;
-    input fabric_direct2_do_rs_i17;
-    input fabric_direct2_do_rs_i18;
-    input fabric_direct2_do_rs_i19;
-    input fabric_direct2_do_rs_i2;
-    input fabric_direct2_do_rs_i20;
-    input fabric_direct2_do_rs_i21;
-    input fabric_direct2_do_rs_i22;
-    input fabric_direct2_do_rs_i23;
-    input fabric_direct2_do_rs_i24;
-    input fabric_direct2_do_rs_i3;
-    input fabric_direct2_do_rs_i4;
-    input fabric_direct2_do_rs_i5;
-    input fabric_direct2_do_rs_i6;
-    input fabric_direct2_do_rs_i7;
-    input fabric_direct2_do_rs_i8;
-    input fabric_direct2_do_rs_i9;
-    input fabric_direct2_loopback_en_i;
-    input fabric_direct2_loopback_mux_i;
-    input fabric_direct2_oe_ena_i1;
-    input fabric_direct2_oe_ena_i10;
-    input fabric_direct2_oe_ena_i11;
-    input fabric_direct2_oe_ena_i12;
-    input fabric_direct2_oe_ena_i13;
-    input fabric_direct2_oe_ena_i14;
-    input fabric_direct2_oe_ena_i15;
-    input fabric_direct2_oe_ena_i16;
-    input fabric_direct2_oe_ena_i17;
-    input fabric_direct2_oe_ena_i18;
-    input fabric_direct2_oe_ena_i19;
-    input fabric_direct2_oe_ena_i2;
-    input fabric_direct2_oe_ena_i20;
-    input fabric_direct2_oe_ena_i21;
-    input fabric_direct2_oe_ena_i22;
-    input fabric_direct2_oe_ena_i23;
-    input fabric_direct2_oe_ena_i24;
-    input fabric_direct2_oe_ena_i3;
-    input fabric_direct2_oe_ena_i4;
-    input fabric_direct2_oe_ena_i5;
-    input fabric_direct2_oe_ena_i6;
-    input fabric_direct2_oe_ena_i7;
-    input fabric_direct2_oe_ena_i8;
-    input fabric_direct2_oe_ena_i9;
-    input fabric_direct2_oe_i1;
-    input fabric_direct2_oe_i10;
-    input fabric_direct2_oe_i11;
-    input fabric_direct2_oe_i12;
-    input fabric_direct2_oe_i13;
-    input fabric_direct2_oe_i14;
-    input fabric_direct2_oe_i15;
-    input fabric_direct2_oe_i16;
-    input fabric_direct2_oe_i17;
-    input fabric_direct2_oe_i18;
-    input fabric_direct2_oe_i19;
-    input fabric_direct2_oe_i2;
-    input fabric_direct2_oe_i20;
-    input fabric_direct2_oe_i21;
-    input fabric_direct2_oe_i22;
-    input fabric_direct2_oe_i23;
-    input fabric_direct2_oe_i24;
-    input fabric_direct2_oe_i3;
-    input fabric_direct2_oe_i4;
-    input fabric_direct2_oe_i5;
-    input fabric_direct2_oe_i6;
-    input fabric_direct2_oe_i7;
-    input fabric_direct2_oe_i8;
-    input fabric_direct2_oe_i9;
-    input fabric_direct2_oe_rs_i1;
-    input fabric_direct2_oe_rs_i10;
-    input fabric_direct2_oe_rs_i11;
-    input fabric_direct2_oe_rs_i12;
-    input fabric_direct2_oe_rs_i13;
-    input fabric_direct2_oe_rs_i14;
-    input fabric_direct2_oe_rs_i15;
-    input fabric_direct2_oe_rs_i16;
-    input fabric_direct2_oe_rs_i17;
-    input fabric_direct2_oe_rs_i18;
-    input fabric_direct2_oe_rs_i19;
-    input fabric_direct2_oe_rs_i2;
-    input fabric_direct2_oe_rs_i20;
-    input fabric_direct2_oe_rs_i21;
-    input fabric_direct2_oe_rs_i22;
-    input fabric_direct2_oe_rs_i23;
-    input fabric_direct2_oe_rs_i24;
-    input fabric_direct2_oe_rs_i3;
-    input fabric_direct2_oe_rs_i4;
-    input fabric_direct2_oe_rs_i5;
-    input fabric_direct2_oe_rs_i6;
-    input fabric_direct2_oe_rs_i7;
-    input fabric_direct2_oe_rs_i8;
-    input fabric_direct2_oe_rs_i9;
-    input fabric_direct2_scan_en_i;
-    input fabric_direct_data_i1;
-    input fabric_direct_data_i10;
-    input fabric_direct_data_i11;
-    input fabric_direct_data_i12;
-    input fabric_direct_data_i13;
-    input fabric_direct_data_i14;
-    input fabric_direct_data_i15;
-    input fabric_direct_data_i16;
-    input fabric_direct_data_i17;
-    input fabric_direct_data_i18;
-    input fabric_direct_data_i19;
-    input fabric_direct_data_i2;
-    input fabric_direct_data_i20;
-    input fabric_direct_data_i21;
-    input fabric_direct_data_i22;
-    input fabric_direct_data_i23;
-    input fabric_direct_data_i24;
-    input fabric_direct_data_i25;
-    input fabric_direct_data_i26;
-    input fabric_direct_data_i27;
-    input fabric_direct_data_i28;
-    input fabric_direct_data_i29;
-    input fabric_direct_data_i3;
-    input fabric_direct_data_i30;
-    input fabric_direct_data_i31;
-    input fabric_direct_data_i32;
-    input fabric_direct_data_i4;
-    input fabric_direct_data_i5;
-    input fabric_direct_data_i6;
-    input fabric_direct_data_i7;
-    input fabric_direct_data_i8;
-    input fabric_direct_data_i9;
-    output fabric_direct_data_o1;
-    output fabric_direct_data_o10;
-    output fabric_direct_data_o11;
-    output fabric_direct_data_o12;
-    output fabric_direct_data_o13;
-    output fabric_direct_data_o14;
-    output fabric_direct_data_o15;
-    output fabric_direct_data_o16;
-    output fabric_direct_data_o17;
-    output fabric_direct_data_o18;
-    output fabric_direct_data_o19;
-    output fabric_direct_data_o2;
-    output fabric_direct_data_o20;
-    output fabric_direct_data_o21;
-    output fabric_direct_data_o22;
-    output fabric_direct_data_o23;
-    output fabric_direct_data_o24;
-    output fabric_direct_data_o25;
-    output fabric_direct_data_o26;
-    output fabric_direct_data_o27;
-    output fabric_direct_data_o28;
-    output fabric_direct_data_o29;
-    output fabric_direct_data_o3;
-    output fabric_direct_data_o30;
-    output fabric_direct_data_o31;
-    output fabric_direct_data_o32;
-    output fabric_direct_data_o4;
-    output fabric_direct_data_o5;
-    output fabric_direct_data_o6;
-    output fabric_direct_data_o7;
-    output fabric_direct_data_o8;
-    output fabric_direct_data_o9;
-    input fabric_enable_TMR_i1;
-    input fabric_enable_TMR_i2;
-    input fabric_enable_TMR_i3;
-    output fabric_flag_ready_TMR_o1;
-    output fabric_flag_ready_TMR_o2;
-    output fabric_flag_ready_TMR_o3;
-    output fabric_flag_trigger0_o;
-    output fabric_flag_trigger1_o;
-    input fabric_io_in_i1;
-    input fabric_io_in_i10;
-    input fabric_io_in_i11;
-    input fabric_io_in_i12;
-    input fabric_io_in_i13;
-    input fabric_io_in_i14;
-    input fabric_io_in_i15;
-    input fabric_io_in_i16;
-    input fabric_io_in_i17;
-    input fabric_io_in_i18;
-    input fabric_io_in_i19;
-    input fabric_io_in_i2;
-    input fabric_io_in_i20;
-    input fabric_io_in_i21;
-    input fabric_io_in_i22;
-    input fabric_io_in_i23;
-    input fabric_io_in_i24;
-    input fabric_io_in_i25;
-    input fabric_io_in_i26;
-    input fabric_io_in_i27;
-    input fabric_io_in_i28;
-    input fabric_io_in_i29;
-    input fabric_io_in_i3;
-    input fabric_io_in_i30;
-    input fabric_io_in_i31;
-    input fabric_io_in_i32;
-    input fabric_io_in_i33;
-    input fabric_io_in_i34;
-    input fabric_io_in_i35;
-    input fabric_io_in_i4;
-    input fabric_io_in_i5;
-    input fabric_io_in_i6;
-    input fabric_io_in_i7;
-    input fabric_io_in_i8;
-    input fabric_io_in_i9;
-    input fabric_io_oe_i1;
-    input fabric_io_oe_i10;
-    input fabric_io_oe_i11;
-    input fabric_io_oe_i12;
-    input fabric_io_oe_i13;
-    input fabric_io_oe_i14;
-    input fabric_io_oe_i15;
-    input fabric_io_oe_i16;
-    input fabric_io_oe_i17;
-    input fabric_io_oe_i18;
-    input fabric_io_oe_i19;
-    input fabric_io_oe_i2;
-    input fabric_io_oe_i20;
-    input fabric_io_oe_i21;
-    input fabric_io_oe_i22;
-    input fabric_io_oe_i23;
-    input fabric_io_oe_i24;
-    input fabric_io_oe_i25;
-    input fabric_io_oe_i26;
-    input fabric_io_oe_i27;
-    input fabric_io_oe_i28;
-    input fabric_io_oe_i29;
-    input fabric_io_oe_i3;
-    input fabric_io_oe_i30;
-    input fabric_io_oe_i31;
-    input fabric_io_oe_i32;
-    input fabric_io_oe_i33;
-    input fabric_io_oe_i34;
-    input fabric_io_oe_i35;
-    input fabric_io_oe_i4;
-    input fabric_io_oe_i5;
-    input fabric_io_oe_i6;
-    input fabric_io_oe_i7;
-    input fabric_io_oe_i8;
-    input fabric_io_oe_i9;
-    output fabric_io_out_o1;
-    output fabric_io_out_o10;
-    output fabric_io_out_o11;
-    output fabric_io_out_o12;
-    output fabric_io_out_o13;
-    output fabric_io_out_o14;
-    output fabric_io_out_o15;
-    output fabric_io_out_o16;
-    output fabric_io_out_o17;
-    output fabric_io_out_o18;
-    output fabric_io_out_o19;
-    output fabric_io_out_o2;
-    output fabric_io_out_o20;
-    output fabric_io_out_o21;
-    output fabric_io_out_o22;
-    output fabric_io_out_o23;
-    output fabric_io_out_o24;
-    output fabric_io_out_o25;
-    output fabric_io_out_o26;
-    output fabric_io_out_o27;
-    output fabric_io_out_o28;
-    output fabric_io_out_o29;
-    output fabric_io_out_o3;
-    output fabric_io_out_o30;
-    output fabric_io_out_o31;
-    output fabric_io_out_o32;
-    output fabric_io_out_o33;
-    output fabric_io_out_o34;
-    output fabric_io_out_o35;
-    output fabric_io_out_o4;
-    output fabric_io_out_o5;
-    output fabric_io_out_o6;
-    output fabric_io_out_o7;
-    output fabric_io_out_o8;
-    output fabric_io_out_o9;
-    output fabric_jtag_tck_o;
-    output fabric_jtag_tdi_o;
-    input fabric_jtag_tdo_usr1_i;
-    input fabric_jtag_tdo_usr2_i;
-    output fabric_jtag_tms_o;
-    output fabric_jtag_trst_n_o;
-    output fabric_jtag_usr1_o;
-    output fabric_jtag_usr2_o;
-    input fabric_lowskew_i1;
-    input fabric_lowskew_i10;
-    input fabric_lowskew_i11;
-    input fabric_lowskew_i12;
-    input fabric_lowskew_i13;
-    input fabric_lowskew_i14;
-    input fabric_lowskew_i15;
-    input fabric_lowskew_i16;
-    input fabric_lowskew_i17;
-    input fabric_lowskew_i18;
-    input fabric_lowskew_i19;
-    input fabric_lowskew_i2;
-    input fabric_lowskew_i20;
-    input fabric_lowskew_i21;
-    input fabric_lowskew_i22;
-    input fabric_lowskew_i23;
-    input fabric_lowskew_i24;
-    input fabric_lowskew_i25;
-    input fabric_lowskew_i26;
-    input fabric_lowskew_i27;
-    input fabric_lowskew_i28;
-    input fabric_lowskew_i29;
-    input fabric_lowskew_i3;
-    input fabric_lowskew_i30;
-    input fabric_lowskew_i31;
-    input fabric_lowskew_i32;
-    input fabric_lowskew_i33;
-    input fabric_lowskew_i34;
-    input fabric_lowskew_i35;
-    input fabric_lowskew_i36;
-    input fabric_lowskew_i37;
-    input fabric_lowskew_i38;
-    input fabric_lowskew_i39;
-    input fabric_lowskew_i4;
-    input fabric_lowskew_i40;
-    input fabric_lowskew_i5;
-    input fabric_lowskew_i6;
-    input fabric_lowskew_i7;
-    input fabric_lowskew_i8;
-    input fabric_lowskew_i9;
-    output fabric_lowskew_o1;
-    output fabric_lowskew_o2;
-    output fabric_lowskew_o3;
-    output fabric_lowskew_o4;
-    output fabric_lowskew_o5;
-    output fabric_lowskew_o6;
-    input fabric_mrepair_bend_i;
-    output fabric_mrepair_bist_mode_o;
-    output fabric_mrepair_bypass_o;
-    output fabric_mrepair_chip_status_o1;
-    output fabric_mrepair_chip_status_o10;
-    output fabric_mrepair_chip_status_o11;
-    output fabric_mrepair_chip_status_o12;
-    output fabric_mrepair_chip_status_o13;
-    output fabric_mrepair_chip_status_o14;
-    output fabric_mrepair_chip_status_o15;
-    output fabric_mrepair_chip_status_o16;
-    output fabric_mrepair_chip_status_o17;
-    output fabric_mrepair_chip_status_o18;
-    output fabric_mrepair_chip_status_o19;
-    output fabric_mrepair_chip_status_o2;
-    output fabric_mrepair_chip_status_o20;
-    output fabric_mrepair_chip_status_o21;
-    output fabric_mrepair_chip_status_o22;
-    output fabric_mrepair_chip_status_o23;
-    output fabric_mrepair_chip_status_o24;
-    output fabric_mrepair_chip_status_o25;
-    output fabric_mrepair_chip_status_o26;
-    output fabric_mrepair_chip_status_o27;
-    output fabric_mrepair_chip_status_o28;
-    output fabric_mrepair_chip_status_o29;
-    output fabric_mrepair_chip_status_o3;
-    output fabric_mrepair_chip_status_o30;
-    output fabric_mrepair_chip_status_o31;
-    output fabric_mrepair_chip_status_o32;
-    output fabric_mrepair_chip_status_o33;
-    output fabric_mrepair_chip_status_o34;
-    output fabric_mrepair_chip_status_o35;
-    output fabric_mrepair_chip_status_o36;
-    output fabric_mrepair_chip_status_o37;
-    output fabric_mrepair_chip_status_o38;
-    output fabric_mrepair_chip_status_o39;
-    output fabric_mrepair_chip_status_o4;
-    output fabric_mrepair_chip_status_o40;
-    output fabric_mrepair_chip_status_o41;
-    output fabric_mrepair_chip_status_o42;
-    output fabric_mrepair_chip_status_o43;
-    output fabric_mrepair_chip_status_o44;
-    output fabric_mrepair_chip_status_o45;
-    output fabric_mrepair_chip_status_o46;
-    output fabric_mrepair_chip_status_o47;
-    output fabric_mrepair_chip_status_o48;
-    output fabric_mrepair_chip_status_o49;
-    output fabric_mrepair_chip_status_o5;
-    output fabric_mrepair_chip_status_o50;
-    output fabric_mrepair_chip_status_o51;
-    output fabric_mrepair_chip_status_o52;
-    output fabric_mrepair_chip_status_o53;
-    output fabric_mrepair_chip_status_o54;
-    output fabric_mrepair_chip_status_o55;
-    output fabric_mrepair_chip_status_o56;
-    output fabric_mrepair_chip_status_o57;
-    output fabric_mrepair_chip_status_o58;
-    output fabric_mrepair_chip_status_o59;
-    output fabric_mrepair_chip_status_o6;
-    output fabric_mrepair_chip_status_o60;
-    output fabric_mrepair_chip_status_o61;
-    output fabric_mrepair_chip_status_o62;
-    output fabric_mrepair_chip_status_o63;
-    output fabric_mrepair_chip_status_o64;
-    output fabric_mrepair_chip_status_o65;
-    output fabric_mrepair_chip_status_o66;
-    output fabric_mrepair_chip_status_o67;
-    output fabric_mrepair_chip_status_o68;
-    output fabric_mrepair_chip_status_o69;
-    output fabric_mrepair_chip_status_o7;
-    output fabric_mrepair_chip_status_o70;
-    output fabric_mrepair_chip_status_o71;
-    output fabric_mrepair_chip_status_o72;
-    output fabric_mrepair_chip_status_o73;
-    output fabric_mrepair_chip_status_o74;
-    output fabric_mrepair_chip_status_o75;
-    output fabric_mrepair_chip_status_o76;
-    output fabric_mrepair_chip_status_o77;
-    output fabric_mrepair_chip_status_o78;
-    output fabric_mrepair_chip_status_o8;
-    output fabric_mrepair_chip_status_o9;
-    input fabric_mrepair_cke_force_i;
-    input fabric_mrepair_cke_i;
-    input fabric_mrepair_clk_i;
-    input fabric_mrepair_data_from_bist_i1;
-    input fabric_mrepair_data_from_bist_i10;
-    input fabric_mrepair_data_from_bist_i11;
-    input fabric_mrepair_data_from_bist_i12;
-    input fabric_mrepair_data_from_bist_i13;
-    input fabric_mrepair_data_from_bist_i14;
-    input fabric_mrepair_data_from_bist_i15;
-    input fabric_mrepair_data_from_bist_i16;
-    input fabric_mrepair_data_from_bist_i17;
-    input fabric_mrepair_data_from_bist_i18;
-    input fabric_mrepair_data_from_bist_i19;
-    input fabric_mrepair_data_from_bist_i2;
-    input fabric_mrepair_data_from_bist_i20;
-    input fabric_mrepair_data_from_bist_i21;
-    input fabric_mrepair_data_from_bist_i22;
-    input fabric_mrepair_data_from_bist_i23;
-    input fabric_mrepair_data_from_bist_i24;
-    input fabric_mrepair_data_from_bist_i25;
-    input fabric_mrepair_data_from_bist_i26;
-    input fabric_mrepair_data_from_bist_i3;
-    input fabric_mrepair_data_from_bist_i4;
-    input fabric_mrepair_data_from_bist_i5;
-    input fabric_mrepair_data_from_bist_i6;
-    input fabric_mrepair_data_from_bist_i7;
-    input fabric_mrepair_data_from_bist_i8;
-    input fabric_mrepair_data_from_bist_i9;
-    input fabric_mrepair_data_from_system_i;
-    input fabric_mrepair_data_shift_en_i;
-    output fabric_mrepair_data_to_bist_o1;
-    output fabric_mrepair_data_to_bist_o10;
-    output fabric_mrepair_data_to_bist_o11;
-    output fabric_mrepair_data_to_bist_o12;
-    output fabric_mrepair_data_to_bist_o13;
-    output fabric_mrepair_data_to_bist_o14;
-    output fabric_mrepair_data_to_bist_o15;
-    output fabric_mrepair_data_to_bist_o16;
-    output fabric_mrepair_data_to_bist_o17;
-    output fabric_mrepair_data_to_bist_o18;
-    output fabric_mrepair_data_to_bist_o19;
-    output fabric_mrepair_data_to_bist_o2;
-    output fabric_mrepair_data_to_bist_o20;
-    output fabric_mrepair_data_to_bist_o21;
-    output fabric_mrepair_data_to_bist_o22;
-    output fabric_mrepair_data_to_bist_o23;
-    output fabric_mrepair_data_to_bist_o24;
-    output fabric_mrepair_data_to_bist_o25;
-    output fabric_mrepair_data_to_bist_o26;
-    output fabric_mrepair_data_to_bist_o3;
-    output fabric_mrepair_data_to_bist_o4;
-    output fabric_mrepair_data_to_bist_o5;
-    output fabric_mrepair_data_to_bist_o6;
-    output fabric_mrepair_data_to_bist_o7;
-    output fabric_mrepair_data_to_bist_o8;
-    output fabric_mrepair_data_to_bist_o9;
-    output fabric_mrepair_data_to_system_o;
-    output fabric_mrepair_decoder_init_ready_o;
-    input fabric_mrepair_end_encoding_i;
-    output fabric_mrepair_fuse_ack_o;
-    input fabric_mrepair_fuse_add_i1;
-    input fabric_mrepair_fuse_add_i2;
-    input fabric_mrepair_fuse_add_i3;
-    input fabric_mrepair_fuse_add_i4;
-    input fabric_mrepair_fuse_add_i5;
-    input fabric_mrepair_fuse_add_i6;
-    input fabric_mrepair_fuse_add_i7;
-    output fabric_mrepair_fuse_bbad_o;
-    output fabric_mrepair_fuse_bend1_o;
-    output fabric_mrepair_fuse_bend2_o;
-    output fabric_mrepair_fuse_bist1fail_o1;
-    output fabric_mrepair_fuse_bist1fail_o2;
-    output fabric_mrepair_fuse_bist1fail_o3;
-    output fabric_mrepair_fuse_bist1fail_o4;
-    output fabric_mrepair_fuse_bist1fail_o5;
-    output fabric_mrepair_fuse_bist1fail_o6;
-    output fabric_mrepair_fuse_bist1fail_o7;
-    output fabric_mrepair_fuse_bist1fail_o8;
-    output fabric_mrepair_fuse_bist2fail_o1;
-    output fabric_mrepair_fuse_bist2fail_o2;
-    output fabric_mrepair_fuse_bist2fail_o3;
-    output fabric_mrepair_fuse_bist2fail_o4;
-    output fabric_mrepair_fuse_bist2fail_o5;
-    output fabric_mrepair_fuse_bist2fail_o6;
-    output fabric_mrepair_fuse_bist2fail_o7;
-    input fabric_mrepair_fuse_bistmode_i;
-    output fabric_mrepair_fuse_calibrated_o;
-    output fabric_mrepair_fuse_ded_o;
-    input fabric_mrepair_fuse_din_i1;
-    input fabric_mrepair_fuse_din_i10;
-    input fabric_mrepair_fuse_din_i11;
-    input fabric_mrepair_fuse_din_i12;
-    input fabric_mrepair_fuse_din_i13;
-    input fabric_mrepair_fuse_din_i14;
-    input fabric_mrepair_fuse_din_i15;
-    input fabric_mrepair_fuse_din_i16;
-    input fabric_mrepair_fuse_din_i17;
-    input fabric_mrepair_fuse_din_i18;
-    input fabric_mrepair_fuse_din_i19;
-    input fabric_mrepair_fuse_din_i2;
-    input fabric_mrepair_fuse_din_i20;
-    input fabric_mrepair_fuse_din_i21;
-    input fabric_mrepair_fuse_din_i22;
-    input fabric_mrepair_fuse_din_i23;
-    input fabric_mrepair_fuse_din_i24;
-    input fabric_mrepair_fuse_din_i25;
-    input fabric_mrepair_fuse_din_i26;
-    input fabric_mrepair_fuse_din_i27;
-    input fabric_mrepair_fuse_din_i28;
-    input fabric_mrepair_fuse_din_i29;
-    input fabric_mrepair_fuse_din_i3;
-    input fabric_mrepair_fuse_din_i30;
-    input fabric_mrepair_fuse_din_i31;
-    input fabric_mrepair_fuse_din_i32;
-    input fabric_mrepair_fuse_din_i33;
-    input fabric_mrepair_fuse_din_i34;
-    input fabric_mrepair_fuse_din_i35;
-    input fabric_mrepair_fuse_din_i36;
-    input fabric_mrepair_fuse_din_i37;
-    input fabric_mrepair_fuse_din_i38;
-    input fabric_mrepair_fuse_din_i39;
-    input fabric_mrepair_fuse_din_i4;
-    input fabric_mrepair_fuse_din_i5;
-    input fabric_mrepair_fuse_din_i6;
-    input fabric_mrepair_fuse_din_i7;
-    input fabric_mrepair_fuse_din_i8;
-    input fabric_mrepair_fuse_din_i9;
-    input fabric_mrepair_fuse_disturbchecked_i;
-    output fabric_mrepair_fuse_disturbed_o;
-    output fabric_mrepair_fuse_dout_o1;
-    output fabric_mrepair_fuse_dout_o10;
-    output fabric_mrepair_fuse_dout_o11;
-    output fabric_mrepair_fuse_dout_o12;
-    output fabric_mrepair_fuse_dout_o13;
-    output fabric_mrepair_fuse_dout_o14;
-    output fabric_mrepair_fuse_dout_o15;
-    output fabric_mrepair_fuse_dout_o16;
-    output fabric_mrepair_fuse_dout_o17;
-    output fabric_mrepair_fuse_dout_o18;
-    output fabric_mrepair_fuse_dout_o19;
-    output fabric_mrepair_fuse_dout_o2;
-    output fabric_mrepair_fuse_dout_o20;
-    output fabric_mrepair_fuse_dout_o21;
-    output fabric_mrepair_fuse_dout_o22;
-    output fabric_mrepair_fuse_dout_o23;
-    output fabric_mrepair_fuse_dout_o24;
-    output fabric_mrepair_fuse_dout_o25;
-    output fabric_mrepair_fuse_dout_o26;
-    output fabric_mrepair_fuse_dout_o27;
-    output fabric_mrepair_fuse_dout_o28;
-    output fabric_mrepair_fuse_dout_o29;
-    output fabric_mrepair_fuse_dout_o3;
-    output fabric_mrepair_fuse_dout_o30;
-    output fabric_mrepair_fuse_dout_o31;
-    output fabric_mrepair_fuse_dout_o32;
-    output fabric_mrepair_fuse_dout_o33;
-    output fabric_mrepair_fuse_dout_o34;
-    output fabric_mrepair_fuse_dout_o35;
-    output fabric_mrepair_fuse_dout_o36;
-    output fabric_mrepair_fuse_dout_o37;
-    output fabric_mrepair_fuse_dout_o38;
-    output fabric_mrepair_fuse_dout_o39;
-    output fabric_mrepair_fuse_dout_o4;
-    output fabric_mrepair_fuse_dout_o40;
-    output fabric_mrepair_fuse_dout_o41;
-    output fabric_mrepair_fuse_dout_o5;
-    output fabric_mrepair_fuse_dout_o6;
-    output fabric_mrepair_fuse_dout_o7;
-    output fabric_mrepair_fuse_dout_o8;
-    output fabric_mrepair_fuse_dout_o9;
-    input fabric_mrepair_fuse_eccbypass_i;
-    output fabric_mrepair_fuse_flagstate_o1;
-    output fabric_mrepair_fuse_flagstate_o2;
-    output fabric_mrepair_fuse_flagstate_o3;
-    output fabric_mrepair_fuse_flagstate_o4;
-    output fabric_mrepair_fuse_locked_o;
-    input fabric_mrepair_fuse_pdn_i;
-    output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o;
-    input fabric_mrepair_fuse_prgwidth_i1;
-    input fabric_mrepair_fuse_prgwidth_i2;
-    input fabric_mrepair_fuse_prgwidth_i3;
-    input fabric_mrepair_fuse_prog_i;
-    output fabric_mrepair_fuse_progfail_o;
-    output fabric_mrepair_fuse_pwok_o;
-    input fabric_mrepair_fuse_rbact1_i;
-    input fabric_mrepair_fuse_rbact2_i;
-    input fabric_mrepair_fuse_read_i;
-    output fabric_mrepair_fuse_ready_o;
-    input fabric_mrepair_fuse_redbypass_i;
-    output fabric_mrepair_fuse_sec_o;
-    output fabric_mrepair_fuse_startword_o1;
-    output fabric_mrepair_fuse_startword_o10;
-    output fabric_mrepair_fuse_startword_o11;
-    output fabric_mrepair_fuse_startword_o12;
-    output fabric_mrepair_fuse_startword_o13;
-    output fabric_mrepair_fuse_startword_o14;
-    output fabric_mrepair_fuse_startword_o15;
-    output fabric_mrepair_fuse_startword_o16;
-    output fabric_mrepair_fuse_startword_o2;
-    output fabric_mrepair_fuse_startword_o3;
-    output fabric_mrepair_fuse_startword_o4;
-    output fabric_mrepair_fuse_startword_o5;
-    output fabric_mrepair_fuse_startword_o6;
-    output fabric_mrepair_fuse_startword_o7;
-    output fabric_mrepair_fuse_startword_o8;
-    output fabric_mrepair_fuse_startword_o9;
-    output fabric_mrepair_fuse_status_o1;
-    output fabric_mrepair_fuse_status_o2;
-    output fabric_mrepair_fuse_status_o3;
-    input fabric_mrepair_fuse_suppadd_i;
-    input fabric_mrepair_fuse_tm_i;
-    input fabric_mrepair_fuse_tst_scanin_i1;
-    input fabric_mrepair_fuse_tst_scanin_i2;
-    input fabric_mrepair_fuse_tst_scanin_i3;
-    input fabric_mrepair_fuse_tst_scanin_i4;
-    input fabric_mrepair_fuse_tst_scanin_i5;
-    input fabric_mrepair_fuse_tstscanenable_i;
-    output fabric_mrepair_fuse_tstscanout_o1;
-    output fabric_mrepair_fuse_tstscanout_o2;
-    output fabric_mrepair_fuse_tstscanout_o3;
-    output fabric_mrepair_fuse_tstscanout_o4;
-    output fabric_mrepair_fuse_tstscanout_o5;
-    output fabric_mrepair_fuse_wlromout_o1;
-    output fabric_mrepair_fuse_wlromout_o10;
-    output fabric_mrepair_fuse_wlromout_o2;
-    output fabric_mrepair_fuse_wlromout_o3;
-    output fabric_mrepair_fuse_wlromout_o4;
-    output fabric_mrepair_fuse_wlromout_o5;
-    output fabric_mrepair_fuse_wlromout_o6;
-    output fabric_mrepair_fuse_wlromout_o7;
-    output fabric_mrepair_fuse_wlromout_o8;
-    output fabric_mrepair_fuse_wlromout_o9;
-    input fabric_mrepair_fuse_wordlock_i;
-    input fabric_mrepair_global_bbad_i;
-    output fabric_mrepair_global_chip_status_o1;
-    output fabric_mrepair_global_chip_status_o2;
-    output fabric_mrepair_global_chip_status_o3;
-    input fabric_mrepair_global_repairable_i;
-    input fabric_mrepair_initn_i;
-    output fabric_mrepair_mem_atpg_mode_o;
-    output fabric_mrepair_mem_type_sel_o1;
-    output fabric_mrepair_mem_type_sel_o2;
-    output fabric_mrepair_mem_type_sel_o3;
-    output fabric_mrepair_mem_type_sel_o4;
-    output fabric_mrepair_mem_type_sel_o5;
-    output fabric_mrepair_memsafe_o;
-    input fabric_mrepair_mode_i1;
-    input fabric_mrepair_mode_i2;
-    input fabric_mrepair_mode_i3;
-    input fabric_mrepair_mode_i4;
-    output fabric_mrepair_mode_sel_o1;
-    output fabric_mrepair_mode_sel_o2;
-    output fabric_mrepair_mode_sel_o3;
-    output fabric_mrepair_mode_sel_o4;
-    input fabric_mrepair_pd_active_i1;
-    input fabric_mrepair_pd_active_i10;
-    input fabric_mrepair_pd_active_i11;
-    input fabric_mrepair_pd_active_i12;
-    input fabric_mrepair_pd_active_i13;
-    input fabric_mrepair_pd_active_i14;
-    input fabric_mrepair_pd_active_i15;
-    input fabric_mrepair_pd_active_i16;
-    input fabric_mrepair_pd_active_i17;
-    input fabric_mrepair_pd_active_i18;
-    input fabric_mrepair_pd_active_i19;
-    input fabric_mrepair_pd_active_i2;
-    input fabric_mrepair_pd_active_i20;
-    input fabric_mrepair_pd_active_i21;
-    input fabric_mrepair_pd_active_i22;
-    input fabric_mrepair_pd_active_i23;
-    input fabric_mrepair_pd_active_i24;
-    input fabric_mrepair_pd_active_i25;
-    input fabric_mrepair_pd_active_i26;
-    input fabric_mrepair_pd_active_i3;
-    input fabric_mrepair_pd_active_i4;
-    input fabric_mrepair_pd_active_i5;
-    input fabric_mrepair_pd_active_i6;
-    input fabric_mrepair_pd_active_i7;
-    input fabric_mrepair_pd_active_i8;
-    input fabric_mrepair_pd_active_i9;
-    output fabric_mrepair_pd_ready_o1;
-    output fabric_mrepair_pd_ready_o10;
-    output fabric_mrepair_pd_ready_o11;
-    output fabric_mrepair_pd_ready_o12;
-    output fabric_mrepair_pd_ready_o13;
-    output fabric_mrepair_pd_ready_o14;
-    output fabric_mrepair_pd_ready_o15;
-    output fabric_mrepair_pd_ready_o16;
-    output fabric_mrepair_pd_ready_o17;
-    output fabric_mrepair_pd_ready_o18;
-    output fabric_mrepair_pd_ready_o19;
-    output fabric_mrepair_pd_ready_o2;
-    output fabric_mrepair_pd_ready_o20;
-    output fabric_mrepair_pd_ready_o21;
-    output fabric_mrepair_pd_ready_o22;
-    output fabric_mrepair_pd_ready_o23;
-    output fabric_mrepair_pd_ready_o24;
-    output fabric_mrepair_pd_ready_o25;
-    output fabric_mrepair_pd_ready_o26;
-    output fabric_mrepair_pd_ready_o3;
-    output fabric_mrepair_pd_ready_o4;
-    output fabric_mrepair_pd_ready_o5;
-    output fabric_mrepair_pd_ready_o6;
-    output fabric_mrepair_pd_ready_o7;
-    output fabric_mrepair_pd_ready_o8;
-    output fabric_mrepair_pd_ready_o9;
-    input fabric_mrepair_por_i;
-    input fabric_mrepair_rst_n_i;
-    input fabric_mrepair_shift_en_i1;
-    input fabric_mrepair_shift_en_i10;
-    input fabric_mrepair_shift_en_i11;
-    input fabric_mrepair_shift_en_i12;
-    input fabric_mrepair_shift_en_i13;
-    input fabric_mrepair_shift_en_i14;
-    input fabric_mrepair_shift_en_i15;
-    input fabric_mrepair_shift_en_i16;
-    input fabric_mrepair_shift_en_i17;
-    input fabric_mrepair_shift_en_i18;
-    input fabric_mrepair_shift_en_i19;
-    input fabric_mrepair_shift_en_i2;
-    input fabric_mrepair_shift_en_i20;
-    input fabric_mrepair_shift_en_i21;
-    input fabric_mrepair_shift_en_i22;
-    input fabric_mrepair_shift_en_i23;
-    input fabric_mrepair_shift_en_i24;
-    input fabric_mrepair_shift_en_i25;
-    input fabric_mrepair_shift_en_i26;
-    input fabric_mrepair_shift_en_i3;
-    input fabric_mrepair_shift_en_i4;
-    input fabric_mrepair_shift_en_i5;
-    input fabric_mrepair_shift_en_i6;
-    input fabric_mrepair_shift_en_i7;
-    input fabric_mrepair_shift_en_i8;
-    input fabric_mrepair_shift_en_i9;
-    output fabric_mrepair_shift_en_to_bist_o1;
-    output fabric_mrepair_shift_en_to_bist_o10;
-    output fabric_mrepair_shift_en_to_bist_o11;
-    output fabric_mrepair_shift_en_to_bist_o12;
-    output fabric_mrepair_shift_en_to_bist_o13;
-    output fabric_mrepair_shift_en_to_bist_o14;
-    output fabric_mrepair_shift_en_to_bist_o15;
-    output fabric_mrepair_shift_en_to_bist_o16;
-    output fabric_mrepair_shift_en_to_bist_o17;
-    output fabric_mrepair_shift_en_to_bist_o18;
-    output fabric_mrepair_shift_en_to_bist_o19;
-    output fabric_mrepair_shift_en_to_bist_o2;
-    output fabric_mrepair_shift_en_to_bist_o20;
-    output fabric_mrepair_shift_en_to_bist_o21;
-    output fabric_mrepair_shift_en_to_bist_o22;
-    output fabric_mrepair_shift_en_to_bist_o23;
-    output fabric_mrepair_shift_en_to_bist_o24;
-    output fabric_mrepair_shift_en_to_bist_o25;
-    output fabric_mrepair_shift_en_to_bist_o26;
-    output fabric_mrepair_shift_en_to_bist_o3;
-    output fabric_mrepair_shift_en_to_bist_o4;
-    output fabric_mrepair_shift_en_to_bist_o5;
-    output fabric_mrepair_shift_en_to_bist_o6;
-    output fabric_mrepair_shift_en_to_bist_o7;
-    output fabric_mrepair_shift_en_to_bist_o8;
-    output fabric_mrepair_shift_en_to_bist_o9;
-    input fabric_mrepair_sif_load_en_i1;
-    input fabric_mrepair_sif_load_en_i10;
-    input fabric_mrepair_sif_load_en_i11;
-    input fabric_mrepair_sif_load_en_i12;
-    input fabric_mrepair_sif_load_en_i13;
-    input fabric_mrepair_sif_load_en_i14;
-    input fabric_mrepair_sif_load_en_i15;
-    input fabric_mrepair_sif_load_en_i16;
-    input fabric_mrepair_sif_load_en_i17;
-    input fabric_mrepair_sif_load_en_i18;
-    input fabric_mrepair_sif_load_en_i19;
-    input fabric_mrepair_sif_load_en_i2;
-    input fabric_mrepair_sif_load_en_i20;
-    input fabric_mrepair_sif_load_en_i21;
-    input fabric_mrepair_sif_load_en_i22;
-    input fabric_mrepair_sif_load_en_i23;
-    input fabric_mrepair_sif_load_en_i24;
-    input fabric_mrepair_sif_load_en_i25;
-    input fabric_mrepair_sif_load_en_i26;
-    input fabric_mrepair_sif_load_en_i3;
-    input fabric_mrepair_sif_load_en_i4;
-    input fabric_mrepair_sif_load_en_i5;
-    input fabric_mrepair_sif_load_en_i6;
-    input fabric_mrepair_sif_load_en_i7;
-    input fabric_mrepair_sif_load_en_i8;
-    input fabric_mrepair_sif_load_en_i9;
-    output fabric_mrepair_sif_load_en_to_bist_o1;
-    output fabric_mrepair_sif_load_en_to_bist_o10;
-    output fabric_mrepair_sif_load_en_to_bist_o11;
-    output fabric_mrepair_sif_load_en_to_bist_o12;
-    output fabric_mrepair_sif_load_en_to_bist_o13;
-    output fabric_mrepair_sif_load_en_to_bist_o14;
-    output fabric_mrepair_sif_load_en_to_bist_o15;
-    output fabric_mrepair_sif_load_en_to_bist_o16;
-    output fabric_mrepair_sif_load_en_to_bist_o17;
-    output fabric_mrepair_sif_load_en_to_bist_o18;
-    output fabric_mrepair_sif_load_en_to_bist_o19;
-    output fabric_mrepair_sif_load_en_to_bist_o2;
-    output fabric_mrepair_sif_load_en_to_bist_o20;
-    output fabric_mrepair_sif_load_en_to_bist_o21;
-    output fabric_mrepair_sif_load_en_to_bist_o22;
-    output fabric_mrepair_sif_load_en_to_bist_o23;
-    output fabric_mrepair_sif_load_en_to_bist_o24;
-    output fabric_mrepair_sif_load_en_to_bist_o25;
-    output fabric_mrepair_sif_load_en_to_bist_o26;
-    output fabric_mrepair_sif_load_en_to_bist_o3;
-    output fabric_mrepair_sif_load_en_to_bist_o4;
-    output fabric_mrepair_sif_load_en_to_bist_o5;
-    output fabric_mrepair_sif_load_en_to_bist_o6;
-    output fabric_mrepair_sif_load_en_to_bist_o7;
-    output fabric_mrepair_sif_load_en_to_bist_o8;
-    output fabric_mrepair_sif_load_en_to_bist_o9;
-    input fabric_mrepair_sif_reg_en_i1;
-    input fabric_mrepair_sif_reg_en_i10;
-    input fabric_mrepair_sif_reg_en_i11;
-    input fabric_mrepair_sif_reg_en_i12;
-    input fabric_mrepair_sif_reg_en_i13;
-    input fabric_mrepair_sif_reg_en_i14;
-    input fabric_mrepair_sif_reg_en_i15;
-    input fabric_mrepair_sif_reg_en_i16;
-    input fabric_mrepair_sif_reg_en_i17;
-    input fabric_mrepair_sif_reg_en_i18;
-    input fabric_mrepair_sif_reg_en_i19;
-    input fabric_mrepair_sif_reg_en_i2;
-    input fabric_mrepair_sif_reg_en_i20;
-    input fabric_mrepair_sif_reg_en_i21;
-    input fabric_mrepair_sif_reg_en_i22;
-    input fabric_mrepair_sif_reg_en_i23;
-    input fabric_mrepair_sif_reg_en_i24;
-    input fabric_mrepair_sif_reg_en_i25;
-    input fabric_mrepair_sif_reg_en_i26;
-    input fabric_mrepair_sif_reg_en_i3;
-    input fabric_mrepair_sif_reg_en_i4;
-    input fabric_mrepair_sif_reg_en_i5;
-    input fabric_mrepair_sif_reg_en_i6;
-    input fabric_mrepair_sif_reg_en_i7;
-    input fabric_mrepair_sif_reg_en_i8;
-    input fabric_mrepair_sif_reg_en_i9;
-    output fabric_mrepair_sif_reg_en_to_bist_o1;
-    output fabric_mrepair_sif_reg_en_to_bist_o10;
-    output fabric_mrepair_sif_reg_en_to_bist_o11;
-    output fabric_mrepair_sif_reg_en_to_bist_o12;
-    output fabric_mrepair_sif_reg_en_to_bist_o13;
-    output fabric_mrepair_sif_reg_en_to_bist_o14;
-    output fabric_mrepair_sif_reg_en_to_bist_o15;
-    output fabric_mrepair_sif_reg_en_to_bist_o16;
-    output fabric_mrepair_sif_reg_en_to_bist_o17;
-    output fabric_mrepair_sif_reg_en_to_bist_o18;
-    output fabric_mrepair_sif_reg_en_to_bist_o19;
-    output fabric_mrepair_sif_reg_en_to_bist_o2;
-    output fabric_mrepair_sif_reg_en_to_bist_o20;
-    output fabric_mrepair_sif_reg_en_to_bist_o21;
-    output fabric_mrepair_sif_reg_en_to_bist_o22;
-    output fabric_mrepair_sif_reg_en_to_bist_o23;
-    output fabric_mrepair_sif_reg_en_to_bist_o24;
-    output fabric_mrepair_sif_reg_en_to_bist_o25;
-    output fabric_mrepair_sif_reg_en_to_bist_o26;
-    output fabric_mrepair_sif_reg_en_to_bist_o3;
-    output fabric_mrepair_sif_reg_en_to_bist_o4;
-    output fabric_mrepair_sif_reg_en_to_bist_o5;
-    output fabric_mrepair_sif_reg_en_to_bist_o6;
-    output fabric_mrepair_sif_reg_en_to_bist_o7;
-    output fabric_mrepair_sif_reg_en_to_bist_o8;
-    output fabric_mrepair_sif_reg_en_to_bist_o9;
-    input fabric_mrepair_sif_update_en_i1;
-    input fabric_mrepair_sif_update_en_i10;
-    input fabric_mrepair_sif_update_en_i11;
-    input fabric_mrepair_sif_update_en_i12;
-    input fabric_mrepair_sif_update_en_i13;
-    input fabric_mrepair_sif_update_en_i14;
-    input fabric_mrepair_sif_update_en_i15;
-    input fabric_mrepair_sif_update_en_i16;
-    input fabric_mrepair_sif_update_en_i17;
-    input fabric_mrepair_sif_update_en_i18;
-    input fabric_mrepair_sif_update_en_i19;
-    input fabric_mrepair_sif_update_en_i2;
-    input fabric_mrepair_sif_update_en_i20;
-    input fabric_mrepair_sif_update_en_i21;
-    input fabric_mrepair_sif_update_en_i22;
-    input fabric_mrepair_sif_update_en_i23;
-    input fabric_mrepair_sif_update_en_i24;
-    input fabric_mrepair_sif_update_en_i25;
-    input fabric_mrepair_sif_update_en_i26;
-    input fabric_mrepair_sif_update_en_i3;
-    input fabric_mrepair_sif_update_en_i4;
-    input fabric_mrepair_sif_update_en_i5;
-    input fabric_mrepair_sif_update_en_i6;
-    input fabric_mrepair_sif_update_en_i7;
-    input fabric_mrepair_sif_update_en_i8;
-    input fabric_mrepair_sif_update_en_i9;
-    output fabric_mrepair_sif_update_en_to_bist_o1;
-    output fabric_mrepair_sif_update_en_to_bist_o10;
-    output fabric_mrepair_sif_update_en_to_bist_o11;
-    output fabric_mrepair_sif_update_en_to_bist_o12;
-    output fabric_mrepair_sif_update_en_to_bist_o13;
-    output fabric_mrepair_sif_update_en_to_bist_o14;
-    output fabric_mrepair_sif_update_en_to_bist_o15;
-    output fabric_mrepair_sif_update_en_to_bist_o16;
-    output fabric_mrepair_sif_update_en_to_bist_o17;
-    output fabric_mrepair_sif_update_en_to_bist_o18;
-    output fabric_mrepair_sif_update_en_to_bist_o19;
-    output fabric_mrepair_sif_update_en_to_bist_o2;
-    output fabric_mrepair_sif_update_en_to_bist_o20;
-    output fabric_mrepair_sif_update_en_to_bist_o21;
-    output fabric_mrepair_sif_update_en_to_bist_o22;
-    output fabric_mrepair_sif_update_en_to_bist_o23;
-    output fabric_mrepair_sif_update_en_to_bist_o24;
-    output fabric_mrepair_sif_update_en_to_bist_o25;
-    output fabric_mrepair_sif_update_en_to_bist_o26;
-    output fabric_mrepair_sif_update_en_to_bist_o3;
-    output fabric_mrepair_sif_update_en_to_bist_o4;
-    output fabric_mrepair_sif_update_en_to_bist_o5;
-    output fabric_mrepair_sif_update_en_to_bist_o6;
-    output fabric_mrepair_sif_update_en_to_bist_o7;
-    output fabric_mrepair_sif_update_en_to_bist_o8;
-    output fabric_mrepair_sif_update_en_to_bist_o9;
-    output fabric_mrepair_system_data_from_mem_bist_o1;
-    output fabric_mrepair_system_data_from_mem_bist_o10;
-    output fabric_mrepair_system_data_from_mem_bist_o11;
-    output fabric_mrepair_system_data_from_mem_bist_o12;
-    output fabric_mrepair_system_data_from_mem_bist_o13;
-    output fabric_mrepair_system_data_from_mem_bist_o14;
-    output fabric_mrepair_system_data_from_mem_bist_o15;
-    output fabric_mrepair_system_data_from_mem_bist_o16;
-    output fabric_mrepair_system_data_from_mem_bist_o17;
-    output fabric_mrepair_system_data_from_mem_bist_o18;
-    output fabric_mrepair_system_data_from_mem_bist_o19;
-    output fabric_mrepair_system_data_from_mem_bist_o2;
-    output fabric_mrepair_system_data_from_mem_bist_o20;
-    output fabric_mrepair_system_data_from_mem_bist_o21;
-    output fabric_mrepair_system_data_from_mem_bist_o22;
-    output fabric_mrepair_system_data_from_mem_bist_o23;
-    output fabric_mrepair_system_data_from_mem_bist_o24;
-    output fabric_mrepair_system_data_from_mem_bist_o25;
-    output fabric_mrepair_system_data_from_mem_bist_o26;
-    output fabric_mrepair_system_data_from_mem_bist_o3;
-    output fabric_mrepair_system_data_from_mem_bist_o4;
-    output fabric_mrepair_system_data_from_mem_bist_o5;
-    output fabric_mrepair_system_data_from_mem_bist_o6;
-    output fabric_mrepair_system_data_from_mem_bist_o7;
-    output fabric_mrepair_system_data_from_mem_bist_o8;
-    output fabric_mrepair_system_data_from_mem_bist_o9;
-    input fabric_mrepair_system_data_to_mem_bist_i1;
-    input fabric_mrepair_system_data_to_mem_bist_i10;
-    input fabric_mrepair_system_data_to_mem_bist_i11;
-    input fabric_mrepair_system_data_to_mem_bist_i12;
-    input fabric_mrepair_system_data_to_mem_bist_i13;
-    input fabric_mrepair_system_data_to_mem_bist_i14;
-    input fabric_mrepair_system_data_to_mem_bist_i15;
-    input fabric_mrepair_system_data_to_mem_bist_i16;
-    input fabric_mrepair_system_data_to_mem_bist_i17;
-    input fabric_mrepair_system_data_to_mem_bist_i18;
-    input fabric_mrepair_system_data_to_mem_bist_i19;
-    input fabric_mrepair_system_data_to_mem_bist_i2;
-    input fabric_mrepair_system_data_to_mem_bist_i20;
-    input fabric_mrepair_system_data_to_mem_bist_i21;
-    input fabric_mrepair_system_data_to_mem_bist_i22;
-    input fabric_mrepair_system_data_to_mem_bist_i23;
-    input fabric_mrepair_system_data_to_mem_bist_i24;
-    input fabric_mrepair_system_data_to_mem_bist_i25;
-    input fabric_mrepair_system_data_to_mem_bist_i26;
-    input fabric_mrepair_system_data_to_mem_bist_i3;
-    input fabric_mrepair_system_data_to_mem_bist_i4;
-    input fabric_mrepair_system_data_to_mem_bist_i5;
-    input fabric_mrepair_system_data_to_mem_bist_i6;
-    input fabric_mrepair_system_data_to_mem_bist_i7;
-    input fabric_mrepair_system_data_to_mem_bist_i8;
-    input fabric_mrepair_system_data_to_mem_bist_i9;
-    output fabric_mrepair_system_dataready_o;
-    output fabric_mrepair_test_se_o;
-    input fabric_mrepair_tst_atpg_mrepair_i;
-    output fabric_mrepair_tst_gatedclock_o;
-    input fabric_otp_apb_addr_i1;
-    input fabric_otp_apb_addr_i10;
-    input fabric_otp_apb_addr_i11;
-    input fabric_otp_apb_addr_i12;
-    input fabric_otp_apb_addr_i13;
-    input fabric_otp_apb_addr_i14;
-    input fabric_otp_apb_addr_i15;
-    input fabric_otp_apb_addr_i16;
-    input fabric_otp_apb_addr_i17;
-    input fabric_otp_apb_addr_i18;
-    input fabric_otp_apb_addr_i19;
-    input fabric_otp_apb_addr_i2;
-    input fabric_otp_apb_addr_i20;
-    input fabric_otp_apb_addr_i21;
-    input fabric_otp_apb_addr_i22;
-    input fabric_otp_apb_addr_i23;
-    input fabric_otp_apb_addr_i24;
-    input fabric_otp_apb_addr_i25;
-    input fabric_otp_apb_addr_i26;
-    input fabric_otp_apb_addr_i27;
-    input fabric_otp_apb_addr_i28;
-    input fabric_otp_apb_addr_i29;
-    input fabric_otp_apb_addr_i3;
-    input fabric_otp_apb_addr_i30;
-    input fabric_otp_apb_addr_i31;
-    input fabric_otp_apb_addr_i32;
-    input fabric_otp_apb_addr_i4;
-    input fabric_otp_apb_addr_i5;
-    input fabric_otp_apb_addr_i6;
-    input fabric_otp_apb_addr_i7;
-    input fabric_otp_apb_addr_i8;
-    input fabric_otp_apb_addr_i9;
-    input fabric_otp_apb_enable_i;
-    output fabric_otp_apb_rdata_o1;
-    output fabric_otp_apb_rdata_o10;
-    output fabric_otp_apb_rdata_o11;
-    output fabric_otp_apb_rdata_o12;
-    output fabric_otp_apb_rdata_o13;
-    output fabric_otp_apb_rdata_o14;
-    output fabric_otp_apb_rdata_o15;
-    output fabric_otp_apb_rdata_o16;
-    output fabric_otp_apb_rdata_o17;
-    output fabric_otp_apb_rdata_o18;
-    output fabric_otp_apb_rdata_o19;
-    output fabric_otp_apb_rdata_o2;
-    output fabric_otp_apb_rdata_o20;
-    output fabric_otp_apb_rdata_o21;
-    output fabric_otp_apb_rdata_o22;
-    output fabric_otp_apb_rdata_o23;
-    output fabric_otp_apb_rdata_o24;
-    output fabric_otp_apb_rdata_o25;
-    output fabric_otp_apb_rdata_o26;
-    output fabric_otp_apb_rdata_o27;
-    output fabric_otp_apb_rdata_o28;
-    output fabric_otp_apb_rdata_o29;
-    output fabric_otp_apb_rdata_o3;
-    output fabric_otp_apb_rdata_o30;
-    output fabric_otp_apb_rdata_o31;
-    output fabric_otp_apb_rdata_o32;
-    output fabric_otp_apb_rdata_o4;
-    output fabric_otp_apb_rdata_o5;
-    output fabric_otp_apb_rdata_o6;
-    output fabric_otp_apb_rdata_o7;
-    output fabric_otp_apb_rdata_o8;
-    output fabric_otp_apb_rdata_o9;
-    output fabric_otp_apb_ready_o;
-    input fabric_otp_apb_sel_i;
-    input fabric_otp_apb_wdata_i1;
-    input fabric_otp_apb_wdata_i10;
-    input fabric_otp_apb_wdata_i11;
-    input fabric_otp_apb_wdata_i12;
-    input fabric_otp_apb_wdata_i13;
-    input fabric_otp_apb_wdata_i14;
-    input fabric_otp_apb_wdata_i15;
-    input fabric_otp_apb_wdata_i16;
-    input fabric_otp_apb_wdata_i17;
-    input fabric_otp_apb_wdata_i18;
-    input fabric_otp_apb_wdata_i19;
-    input fabric_otp_apb_wdata_i2;
-    input fabric_otp_apb_wdata_i20;
-    input fabric_otp_apb_wdata_i21;
-    input fabric_otp_apb_wdata_i22;
-    input fabric_otp_apb_wdata_i23;
-    input fabric_otp_apb_wdata_i24;
-    input fabric_otp_apb_wdata_i25;
-    input fabric_otp_apb_wdata_i26;
-    input fabric_otp_apb_wdata_i27;
-    input fabric_otp_apb_wdata_i28;
-    input fabric_otp_apb_wdata_i29;
-    input fabric_otp_apb_wdata_i3;
-    input fabric_otp_apb_wdata_i30;
-    input fabric_otp_apb_wdata_i31;
-    input fabric_otp_apb_wdata_i32;
-    input fabric_otp_apb_wdata_i4;
-    input fabric_otp_apb_wdata_i5;
-    input fabric_otp_apb_wdata_i6;
-    input fabric_otp_apb_wdata_i7;
-    input fabric_otp_apb_wdata_i8;
-    input fabric_otp_apb_wdata_i9;
-    input fabric_otp_apb_write_i;
-    input fabric_otp_cfg_clk_fab_en_i;
-    input fabric_otp_cfg_clk_otpm_disable_i;
-    input fabric_otp_cfg_fabric_apb_en_i;
-    input fabric_otp_cfg_loader_read_en_i;
-    input fabric_otp_cfg_loader_write_en_i;
-    input fabric_otp_clk_i;
-    input fabric_otp_rst_i;
-    output fabric_otp_security_ack_o;
-    output fabric_otp_security_bist_bad_o;
-    output fabric_otp_security_bist_end1_o;
-    output fabric_otp_security_bist_end2_o;
-    output fabric_otp_security_bist_fail1_o1;
-    output fabric_otp_security_bist_fail1_o2;
-    output fabric_otp_security_bist_fail1_o3;
-    output fabric_otp_security_bist_fail1_o4;
-    output fabric_otp_security_bist_fail1_o5;
-    output fabric_otp_security_bist_fail1_o6;
-    output fabric_otp_security_bist_fail1_o7;
-    output fabric_otp_security_bist_fail2_o1;
-    output fabric_otp_security_bist_fail2_o2;
-    output fabric_otp_security_bist_fail2_o3;
-    output fabric_otp_security_bist_fail2_o4;
-    output fabric_otp_security_bist_fail2_o5;
-    output fabric_otp_security_bist_fail2_o6;
-    input fabric_otp_security_bistmode_i;
-    input fabric_otp_security_force_pdn1_i;
-    input fabric_otp_security_rbact1_i;
-    input fabric_otp_security_rbact2_i;
-    input fabric_otp_security_scanenable_i;
-    input fabric_otp_security_scanin_i1;
-    input fabric_otp_security_scanin_i2;
-    input fabric_otp_security_scanin_i3;
-    input fabric_otp_security_scanin_i4;
-    output fabric_otp_security_scanout_o1;
-    output fabric_otp_security_scanout_o2;
-    output fabric_otp_security_scanout_o3;
-    output fabric_otp_security_scanout_o4;
-    input fabric_otp_security_testmode_i;
-    output fabric_otp_user_ack_o;
-    input fabric_otp_user_add_i1;
-    input fabric_otp_user_add_i2;
-    input fabric_otp_user_add_i3;
-    input fabric_otp_user_add_i4;
-    input fabric_otp_user_add_i5;
-    input fabric_otp_user_add_i6;
-    input fabric_otp_user_add_i7;
-    output fabric_otp_user_bbad_o;
-    output fabric_otp_user_bend1_o;
-    output fabric_otp_user_bend2_o;
-    output fabric_otp_user_bist1fail_o1;
-    output fabric_otp_user_bist1fail_o2;
-    output fabric_otp_user_bist1fail_o3;
-    output fabric_otp_user_bist1fail_o4;
-    output fabric_otp_user_bist1fail_o5;
-    output fabric_otp_user_bist1fail_o6;
-    output fabric_otp_user_bist1fail_o7;
-    output fabric_otp_user_bist1fail_o8;
-    output fabric_otp_user_bist2fail_o1;
-    output fabric_otp_user_bist2fail_o2;
-    output fabric_otp_user_bist2fail_o3;
-    output fabric_otp_user_bist2fail_o4;
-    output fabric_otp_user_bist2fail_o5;
-    output fabric_otp_user_bist2fail_o6;
-    output fabric_otp_user_bist2fail_o7;
-    input fabric_otp_user_bistmode_i;
-    output fabric_otp_user_calibrated_o;
-    input fabric_otp_user_clk_i;
-    input fabric_otp_user_clock_frequency_range_i;
-    output fabric_otp_user_ded_o;
-    input fabric_otp_user_din_i1;
-    input fabric_otp_user_din_i10;
-    input fabric_otp_user_din_i11;
-    input fabric_otp_user_din_i12;
-    input fabric_otp_user_din_i13;
-    input fabric_otp_user_din_i14;
-    input fabric_otp_user_din_i15;
-    input fabric_otp_user_din_i16;
-    input fabric_otp_user_din_i17;
-    input fabric_otp_user_din_i18;
-    input fabric_otp_user_din_i19;
-    input fabric_otp_user_din_i2;
-    input fabric_otp_user_din_i20;
-    input fabric_otp_user_din_i21;
-    input fabric_otp_user_din_i22;
-    input fabric_otp_user_din_i23;
-    input fabric_otp_user_din_i24;
-    input fabric_otp_user_din_i25;
-    input fabric_otp_user_din_i26;
-    input fabric_otp_user_din_i27;
-    input fabric_otp_user_din_i28;
-    input fabric_otp_user_din_i29;
-    input fabric_otp_user_din_i3;
-    input fabric_otp_user_din_i30;
-    input fabric_otp_user_din_i31;
-    input fabric_otp_user_din_i32;
-    input fabric_otp_user_din_i33;
-    input fabric_otp_user_din_i34;
-    input fabric_otp_user_din_i35;
-    input fabric_otp_user_din_i36;
-    input fabric_otp_user_din_i37;
-    input fabric_otp_user_din_i38;
-    input fabric_otp_user_din_i39;
-    input fabric_otp_user_din_i4;
-    input fabric_otp_user_din_i5;
-    input fabric_otp_user_din_i6;
-    input fabric_otp_user_din_i7;
-    input fabric_otp_user_din_i8;
-    input fabric_otp_user_din_i9;
-    input fabric_otp_user_disturbcheck_i;
-    output fabric_otp_user_disturbed_o;
-    output fabric_otp_user_dout_o1;
-    output fabric_otp_user_dout_o10;
-    output fabric_otp_user_dout_o11;
-    output fabric_otp_user_dout_o12;
-    output fabric_otp_user_dout_o13;
-    output fabric_otp_user_dout_o14;
-    output fabric_otp_user_dout_o15;
-    output fabric_otp_user_dout_o16;
-    output fabric_otp_user_dout_o17;
-    output fabric_otp_user_dout_o18;
-    output fabric_otp_user_dout_o19;
-    output fabric_otp_user_dout_o2;
-    output fabric_otp_user_dout_o20;
-    output fabric_otp_user_dout_o21;
-    output fabric_otp_user_dout_o22;
-    output fabric_otp_user_dout_o23;
-    output fabric_otp_user_dout_o24;
-    output fabric_otp_user_dout_o25;
-    output fabric_otp_user_dout_o26;
-    output fabric_otp_user_dout_o27;
-    output fabric_otp_user_dout_o28;
-    output fabric_otp_user_dout_o29;
-    output fabric_otp_user_dout_o3;
-    output fabric_otp_user_dout_o30;
-    output fabric_otp_user_dout_o31;
-    output fabric_otp_user_dout_o32;
-    output fabric_otp_user_dout_o33;
-    output fabric_otp_user_dout_o34;
-    output fabric_otp_user_dout_o35;
-    output fabric_otp_user_dout_o36;
-    output fabric_otp_user_dout_o37;
-    output fabric_otp_user_dout_o38;
-    output fabric_otp_user_dout_o39;
-    output fabric_otp_user_dout_o4;
-    output fabric_otp_user_dout_o40;
-    output fabric_otp_user_dout_o41;
-    output fabric_otp_user_dout_o5;
-    output fabric_otp_user_dout_o6;
-    output fabric_otp_user_dout_o7;
-    output fabric_otp_user_dout_o8;
-    output fabric_otp_user_dout_o9;
-    input fabric_otp_user_eccbypass_i;
-    output fabric_otp_user_flagstate_o1;
-    output fabric_otp_user_flagstate_o2;
-    output fabric_otp_user_flagstate_o3;
-    output fabric_otp_user_flagstate_o4;
-    output fabric_otp_user_locked_o;
-    input fabric_otp_user_pdn_i;
-    input fabric_otp_user_prgwidth_i1;
-    input fabric_otp_user_prgwidth_i2;
-    input fabric_otp_user_prgwidth_i3;
-    input fabric_otp_user_prog_i;
-    output fabric_otp_user_progfail_o;
-    output fabric_otp_user_pwok_o;
-    input fabric_otp_user_rbact1_i;
-    input fabric_otp_user_rbact2_i;
-    input fabric_otp_user_read_i;
-    input fabric_otp_user_redbypass_i;
-    output fabric_otp_user_sec_o;
-    output fabric_otp_user_startword_o1;
-    output fabric_otp_user_startword_o10;
-    output fabric_otp_user_startword_o11;
-    output fabric_otp_user_startword_o12;
-    output fabric_otp_user_startword_o13;
-    output fabric_otp_user_startword_o14;
-    output fabric_otp_user_startword_o15;
-    output fabric_otp_user_startword_o16;
-    output fabric_otp_user_startword_o2;
-    output fabric_otp_user_startword_o3;
-    output fabric_otp_user_startword_o4;
-    output fabric_otp_user_startword_o5;
-    output fabric_otp_user_startword_o6;
-    output fabric_otp_user_startword_o7;
-    output fabric_otp_user_startword_o8;
-    output fabric_otp_user_startword_o9;
-    input fabric_otp_user_suppadd_i;
-    input fabric_otp_user_tm_i;
-    input fabric_otp_user_tst_scanenable_i;
-    input fabric_otp_user_tst_scanin_i1;
-    input fabric_otp_user_tst_scanin_i2;
-    input fabric_otp_user_tst_scanin_i3;
-    input fabric_otp_user_tst_scanin_i4;
-    input fabric_otp_user_tst_scanin_i5;
-    output fabric_otp_user_tst_scanout_o1;
-    output fabric_otp_user_tst_scanout_o2;
-    output fabric_otp_user_tst_scanout_o3;
-    output fabric_otp_user_tst_scanout_o4;
-    output fabric_otp_user_tst_scanout_o5;
-    output fabric_otp_user_wlromout_o1;
-    output fabric_otp_user_wlromout_o10;
-    output fabric_otp_user_wlromout_o2;
-    output fabric_otp_user_wlromout_o3;
-    output fabric_otp_user_wlromout_o4;
-    output fabric_otp_user_wlromout_o5;
-    output fabric_otp_user_wlromout_o6;
-    output fabric_otp_user_wlromout_o7;
-    output fabric_otp_user_wlromout_o8;
-    output fabric_otp_user_wlromout_o9;
-    input fabric_otp_user_wordlock_i;
-    input fabric_parusr_clk_i;
-    input fabric_parusr_cs_i;
-    input fabric_parusr_data_i1;
-    input fabric_parusr_data_i10;
-    input fabric_parusr_data_i11;
-    input fabric_parusr_data_i12;
-    input fabric_parusr_data_i13;
-    input fabric_parusr_data_i14;
-    input fabric_parusr_data_i15;
-    input fabric_parusr_data_i16;
-    input fabric_parusr_data_i2;
-    input fabric_parusr_data_i3;
-    input fabric_parusr_data_i4;
-    input fabric_parusr_data_i5;
-    input fabric_parusr_data_i6;
-    input fabric_parusr_data_i7;
-    input fabric_parusr_data_i8;
-    input fabric_parusr_data_i9;
-    output fabric_parusr_data_o1;
-    output fabric_parusr_data_o10;
-    output fabric_parusr_data_o11;
-    output fabric_parusr_data_o12;
-    output fabric_parusr_data_o13;
-    output fabric_parusr_data_o14;
-    output fabric_parusr_data_o15;
-    output fabric_parusr_data_o16;
-    output fabric_parusr_data_o2;
-    output fabric_parusr_data_o3;
-    output fabric_parusr_data_o4;
-    output fabric_parusr_data_o5;
-    output fabric_parusr_data_o6;
-    output fabric_parusr_data_o7;
-    output fabric_parusr_data_o8;
-    output fabric_parusr_data_o9;
-    output fabric_parusr_data_val_o;
-    input fabric_parusr_enable_i;
-    input fabric_parusr_type_i1;
-    input fabric_parusr_type_i2;
-    input fabric_spare_i1;
-    input fabric_spare_i10;
-    input fabric_spare_i100;
-    input fabric_spare_i101;
-    input fabric_spare_i102;
-    input fabric_spare_i103;
-    input fabric_spare_i104;
-    input fabric_spare_i105;
-    input fabric_spare_i106;
-    input fabric_spare_i107;
-    input fabric_spare_i108;
-    input fabric_spare_i109;
-    input fabric_spare_i11;
-    input fabric_spare_i110;
-    input fabric_spare_i111;
-    input fabric_spare_i112;
-    input fabric_spare_i113;
-    input fabric_spare_i114;
-    input fabric_spare_i115;
-    input fabric_spare_i116;
-    input fabric_spare_i117;
-    input fabric_spare_i118;
-    input fabric_spare_i119;
-    input fabric_spare_i12;
-    input fabric_spare_i120;
-    input fabric_spare_i121;
-    input fabric_spare_i122;
-    input fabric_spare_i123;
-    input fabric_spare_i124;
-    input fabric_spare_i125;
-    input fabric_spare_i126;
-    input fabric_spare_i127;
-    input fabric_spare_i128;
-    input fabric_spare_i13;
-    input fabric_spare_i14;
-    input fabric_spare_i15;
-    input fabric_spare_i16;
-    input fabric_spare_i17;
-    input fabric_spare_i18;
-    input fabric_spare_i19;
-    input fabric_spare_i2;
-    input fabric_spare_i20;
-    input fabric_spare_i21;
-    input fabric_spare_i22;
-    input fabric_spare_i23;
-    input fabric_spare_i24;
-    input fabric_spare_i25;
-    input fabric_spare_i26;
-    input fabric_spare_i27;
-    input fabric_spare_i28;
-    input fabric_spare_i29;
-    input fabric_spare_i3;
-    input fabric_spare_i30;
-    input fabric_spare_i31;
-    input fabric_spare_i32;
-    input fabric_spare_i33;
-    input fabric_spare_i34;
-    input fabric_spare_i35;
-    input fabric_spare_i36;
-    input fabric_spare_i37;
-    input fabric_spare_i38;
-    input fabric_spare_i39;
-    input fabric_spare_i4;
-    input fabric_spare_i40;
-    input fabric_spare_i41;
-    input fabric_spare_i42;
-    input fabric_spare_i43;
-    input fabric_spare_i44;
-    input fabric_spare_i45;
-    input fabric_spare_i46;
-    input fabric_spare_i47;
-    input fabric_spare_i48;
-    input fabric_spare_i49;
-    input fabric_spare_i5;
-    input fabric_spare_i50;
-    input fabric_spare_i51;
-    input fabric_spare_i52;
-    input fabric_spare_i53;
-    input fabric_spare_i54;
-    input fabric_spare_i55;
-    input fabric_spare_i56;
-    input fabric_spare_i57;
-    input fabric_spare_i58;
-    input fabric_spare_i59;
-    input fabric_spare_i6;
-    input fabric_spare_i60;
-    input fabric_spare_i61;
-    input fabric_spare_i62;
-    input fabric_spare_i63;
-    input fabric_spare_i64;
-    input fabric_spare_i65;
-    input fabric_spare_i66;
-    input fabric_spare_i67;
-    input fabric_spare_i68;
-    input fabric_spare_i69;
-    input fabric_spare_i7;
-    input fabric_spare_i70;
-    input fabric_spare_i71;
-    input fabric_spare_i72;
-    input fabric_spare_i73;
-    input fabric_spare_i74;
-    input fabric_spare_i75;
-    input fabric_spare_i76;
-    input fabric_spare_i77;
-    input fabric_spare_i78;
-    input fabric_spare_i79;
-    input fabric_spare_i8;
-    input fabric_spare_i80;
-    input fabric_spare_i81;
-    input fabric_spare_i82;
-    input fabric_spare_i83;
-    input fabric_spare_i84;
-    input fabric_spare_i85;
-    input fabric_spare_i86;
-    input fabric_spare_i87;
-    input fabric_spare_i88;
-    input fabric_spare_i89;
-    input fabric_spare_i9;
-    input fabric_spare_i90;
-    input fabric_spare_i91;
-    input fabric_spare_i92;
-    input fabric_spare_i93;
-    input fabric_spare_i94;
-    input fabric_spare_i95;
-    input fabric_spare_i96;
-    input fabric_spare_i97;
-    input fabric_spare_i98;
-    input fabric_spare_i99;
-    output fabric_spare_o1;
-    output fabric_spare_o10;
-    output fabric_spare_o100;
-    output fabric_spare_o101;
-    output fabric_spare_o102;
-    output fabric_spare_o103;
-    output fabric_spare_o104;
-    output fabric_spare_o105;
-    output fabric_spare_o106;
-    output fabric_spare_o107;
-    output fabric_spare_o108;
-    output fabric_spare_o109;
-    output fabric_spare_o11;
-    output fabric_spare_o110;
-    output fabric_spare_o111;
-    output fabric_spare_o112;
-    output fabric_spare_o113;
-    output fabric_spare_o114;
-    output fabric_spare_o115;
-    output fabric_spare_o116;
-    output fabric_spare_o117;
-    output fabric_spare_o118;
-    output fabric_spare_o119;
-    output fabric_spare_o12;
-    output fabric_spare_o120;
-    output fabric_spare_o121;
-    output fabric_spare_o122;
-    output fabric_spare_o123;
-    output fabric_spare_o124;
-    output fabric_spare_o125;
-    output fabric_spare_o126;
-    output fabric_spare_o127;
-    output fabric_spare_o128;
-    output fabric_spare_o13;
-    output fabric_spare_o14;
-    output fabric_spare_o15;
-    output fabric_spare_o16;
-    output fabric_spare_o17;
-    output fabric_spare_o18;
-    output fabric_spare_o19;
-    output fabric_spare_o2;
-    output fabric_spare_o20;
-    output fabric_spare_o21;
-    output fabric_spare_o22;
-    output fabric_spare_o23;
-    output fabric_spare_o24;
-    output fabric_spare_o25;
-    output fabric_spare_o26;
-    output fabric_spare_o27;
-    output fabric_spare_o28;
-    output fabric_spare_o29;
-    output fabric_spare_o3;
-    output fabric_spare_o30;
-    output fabric_spare_o31;
-    output fabric_spare_o32;
-    output fabric_spare_o33;
-    output fabric_spare_o34;
-    output fabric_spare_o35;
-    output fabric_spare_o36;
-    output fabric_spare_o37;
-    output fabric_spare_o38;
-    output fabric_spare_o39;
-    output fabric_spare_o4;
-    output fabric_spare_o40;
-    output fabric_spare_o41;
-    output fabric_spare_o42;
-    output fabric_spare_o43;
-    output fabric_spare_o44;
-    output fabric_spare_o45;
-    output fabric_spare_o46;
-    output fabric_spare_o47;
-    output fabric_spare_o48;
-    output fabric_spare_o49;
-    output fabric_spare_o5;
-    output fabric_spare_o50;
-    output fabric_spare_o51;
-    output fabric_spare_o52;
-    output fabric_spare_o53;
-    output fabric_spare_o54;
-    output fabric_spare_o55;
-    output fabric_spare_o56;
-    output fabric_spare_o57;
-    output fabric_spare_o58;
-    output fabric_spare_o59;
-    output fabric_spare_o6;
-    output fabric_spare_o60;
-    output fabric_spare_o61;
-    output fabric_spare_o62;
-    output fabric_spare_o63;
-    output fabric_spare_o64;
-    output fabric_spare_o65;
-    output fabric_spare_o66;
-    output fabric_spare_o67;
-    output fabric_spare_o68;
-    output fabric_spare_o69;
-    output fabric_spare_o7;
-    output fabric_spare_o70;
-    output fabric_spare_o71;
-    output fabric_spare_o72;
-    output fabric_spare_o73;
-    output fabric_spare_o74;
-    output fabric_spare_o75;
-    output fabric_spare_o76;
-    output fabric_spare_o77;
-    output fabric_spare_o78;
-    output fabric_spare_o79;
-    output fabric_spare_o8;
-    output fabric_spare_o80;
-    output fabric_spare_o81;
-    output fabric_spare_o82;
-    output fabric_spare_o83;
-    output fabric_spare_o84;
-    output fabric_spare_o85;
-    output fabric_spare_o86;
-    output fabric_spare_o87;
-    output fabric_spare_o88;
-    output fabric_spare_o89;
-    output fabric_spare_o9;
-    output fabric_spare_o90;
-    output fabric_spare_o91;
-    output fabric_spare_o92;
-    output fabric_spare_o93;
-    output fabric_spare_o94;
-    output fabric_spare_o95;
-    output fabric_spare_o96;
-    output fabric_spare_o97;
-    output fabric_spare_o98;
-    output fabric_spare_o99;
-    input fabric_spi_arst_tmr_n_i1;
-    input fabric_spi_arst_tmr_n_i2;
-    input fabric_spi_arst_tmr_n_i3;
-    input fabric_spi_arst_tmr_n_i4;
-    input fabric_spi_arst_tmr_n_i5;
-    input fabric_spi_arst_tmr_n_i6;
-    input fabric_spi_arst_tmr_n_i7;
-    input fabric_spi_arst_tmr_n_i8;
-    input fabric_spi_arst_tmr_n_i9;
-    output fabric_spi_bsm_release_o1;
-    output fabric_spi_bsm_release_o2;
-    output fabric_spi_bsm_release_o3;
-    output fabric_spi_busy_o1;
-    output fabric_spi_busy_o2;
-    output fabric_spi_busy_o3;
-    input fabric_spi_clk_i0;
-    input fabric_spi_clk_i1;
-    input fabric_spi_clk_i2;
-    input fabric_spi_cmd_bytes_i1;
-    input fabric_spi_cmd_bytes_i2;
-    input fabric_spi_cmd_bytes_i3;
-    input fabric_spi_cmd_bytes_i4;
-    input fabric_spi_cmd_bytes_i5;
-    input fabric_spi_cmd_bytes_i6;
-    output fabric_spi_cmd_full_o1;
-    output fabric_spi_cmd_full_o2;
-    output fabric_spi_cmd_full_o3;
-    input fabric_spi_cmd_mode_i1;
-    input fabric_spi_cmd_mode_i2;
-    input fabric_spi_cmd_mode_i3;
-    input fabric_spi_cmd_mode_i4;
-    input fabric_spi_cmd_mode_i5;
-    input fabric_spi_cmd_mode_i6;
-    input fabric_spi_cmd_push_i1;
-    input fabric_spi_cmd_push_i2;
-    input fabric_spi_cmd_push_i3;
-    input fabric_spi_cmd_type_i1;
-    input fabric_spi_cmd_type_i2;
-    input fabric_spi_cmd_type_i3;
-    input fabric_spi_cmd_type_i4;
-    input fabric_spi_cmd_type_i5;
-    input fabric_spi_cmd_type_i6;
-    input fabric_spi_cpha_i1;
-    input fabric_spi_cpha_i2;
-    input fabric_spi_cpha_i3;
-    input fabric_spi_cpol_i1;
-    input fabric_spi_cpol_i2;
-    input fabric_spi_cpol_i3;
-    input fabric_spi_cs_holdtime_i1;
-    input fabric_spi_cs_holdtime_i10;
-    input fabric_spi_cs_holdtime_i11;
-    input fabric_spi_cs_holdtime_i12;
-    input fabric_spi_cs_holdtime_i2;
-    input fabric_spi_cs_holdtime_i3;
-    input fabric_spi_cs_holdtime_i4;
-    input fabric_spi_cs_holdtime_i5;
-    input fabric_spi_cs_holdtime_i6;
-    input fabric_spi_cs_holdtime_i7;
-    input fabric_spi_cs_holdtime_i8;
-    input fabric_spi_cs_holdtime_i9;
-    input fabric_spi_cs_offtime_i1;
-    input fabric_spi_cs_offtime_i10;
-    input fabric_spi_cs_offtime_i11;
-    input fabric_spi_cs_offtime_i12;
-    input fabric_spi_cs_offtime_i2;
-    input fabric_spi_cs_offtime_i3;
-    input fabric_spi_cs_offtime_i4;
-    input fabric_spi_cs_offtime_i5;
-    input fabric_spi_cs_offtime_i6;
-    input fabric_spi_cs_offtime_i7;
-    input fabric_spi_cs_offtime_i8;
-    input fabric_spi_cs_offtime_i9;
-    input fabric_spi_cs_setuptime_i1;
-    input fabric_spi_cs_setuptime_i10;
-    input fabric_spi_cs_setuptime_i11;
-    input fabric_spi_cs_setuptime_i12;
-    input fabric_spi_cs_setuptime_i2;
-    input fabric_spi_cs_setuptime_i3;
-    input fabric_spi_cs_setuptime_i4;
-    input fabric_spi_cs_setuptime_i5;
-    input fabric_spi_cs_setuptime_i6;
-    input fabric_spi_cs_setuptime_i7;
-    input fabric_spi_cs_setuptime_i8;
-    input fabric_spi_cs_setuptime_i9;
-    input fabric_spi_data_in_unlimited_i1;
-    input fabric_spi_data_in_unlimited_i2;
-    input fabric_spi_data_in_unlimited_i3;
-    input fabric_spi_enable_i1;
-    input fabric_spi_enable_i2;
-    input fabric_spi_enable_i3;
-    output fabric_spi_error_endianness_o1;
-    output fabric_spi_error_endianness_o2;
-    output fabric_spi_error_endianness_o3;
-    output fabric_spi_error_loopback_o1;
-    output fabric_spi_error_loopback_o2;
-    output fabric_spi_error_loopback_o3;
-    output fabric_spi_error_mode_o1;
-    output fabric_spi_error_mode_o2;
-    output fabric_spi_error_mode_o3;
-    output fabric_spi_error_sel_o1;
-    output fabric_spi_error_sel_o2;
-    output fabric_spi_error_sel_o3;
-    input fabric_spi_fifo_arst_tmr_n_i1;
-    input fabric_spi_fifo_arst_tmr_n_i2;
-    input fabric_spi_fifo_arst_tmr_n_i3;
-    input fabric_spi_fifo_arst_tmr_n_i4;
-    input fabric_spi_fifo_arst_tmr_n_i5;
-    input fabric_spi_fifo_arst_tmr_n_i6;
-    input fabric_spi_fifo_arst_tmr_n_i7;
-    input fabric_spi_fifo_arst_tmr_n_i8;
-    input fabric_spi_fifo_arst_tmr_n_i9;
-    output fabric_spi_init_done_o1;
-    output fabric_spi_init_done_o2;
-    output fabric_spi_init_done_o3;
-    input fabric_spi_legacy_enable_i1;
-    input fabric_spi_legacy_enable_i2;
-    input fabric_spi_legacy_enable_i3;
-    input fabric_spi_legacy_master_i1;
-    input fabric_spi_legacy_master_i2;
-    input fabric_spi_legacy_master_i3;
-    input fabric_spi_loopback_i1;
-    input fabric_spi_loopback_i2;
-    input fabric_spi_loopback_i3;
-    input fabric_spi_lsb_first_i1;
-    input fabric_spi_lsb_first_i2;
-    input fabric_spi_lsb_first_i3;
-    output fabric_spi_miso_data_inv_o1;
-    output fabric_spi_miso_data_inv_o2;
-    output fabric_spi_miso_data_inv_o3;
-    output fabric_spi_miso_data_o1;
-    output fabric_spi_miso_data_o10;
-    output fabric_spi_miso_data_o11;
-    output fabric_spi_miso_data_o12;
-    output fabric_spi_miso_data_o13;
-    output fabric_spi_miso_data_o14;
-    output fabric_spi_miso_data_o15;
-    output fabric_spi_miso_data_o16;
-    output fabric_spi_miso_data_o17;
-    output fabric_spi_miso_data_o18;
-    output fabric_spi_miso_data_o19;
-    output fabric_spi_miso_data_o2;
-    output fabric_spi_miso_data_o20;
-    output fabric_spi_miso_data_o21;
-    output fabric_spi_miso_data_o22;
-    output fabric_spi_miso_data_o23;
-    output fabric_spi_miso_data_o24;
-    output fabric_spi_miso_data_o3;
-    output fabric_spi_miso_data_o4;
-    output fabric_spi_miso_data_o5;
-    output fabric_spi_miso_data_o6;
-    output fabric_spi_miso_data_o7;
-    output fabric_spi_miso_data_o8;
-    output fabric_spi_miso_data_o9;
-    output fabric_spi_miso_empty_o1;
-    output fabric_spi_miso_empty_o2;
-    output fabric_spi_miso_empty_o3;
-    input fabric_spi_miso_pop_i1;
-    input fabric_spi_miso_pop_i2;
-    input fabric_spi_miso_pop_i3;
-    input fabric_spi_mosi_data_i1;
-    input fabric_spi_mosi_data_i10;
-    input fabric_spi_mosi_data_i11;
-    input fabric_spi_mosi_data_i12;
-    input fabric_spi_mosi_data_i13;
-    input fabric_spi_mosi_data_i14;
-    input fabric_spi_mosi_data_i15;
-    input fabric_spi_mosi_data_i16;
-    input fabric_spi_mosi_data_i17;
-    input fabric_spi_mosi_data_i18;
-    input fabric_spi_mosi_data_i19;
-    input fabric_spi_mosi_data_i2;
-    input fabric_spi_mosi_data_i20;
-    input fabric_spi_mosi_data_i21;
-    input fabric_spi_mosi_data_i22;
-    input fabric_spi_mosi_data_i23;
-    input fabric_spi_mosi_data_i24;
-    input fabric_spi_mosi_data_i3;
-    input fabric_spi_mosi_data_i4;
-    input fabric_spi_mosi_data_i5;
-    input fabric_spi_mosi_data_i6;
-    input fabric_spi_mosi_data_i7;
-    input fabric_spi_mosi_data_i8;
-    input fabric_spi_mosi_data_i9;
-    input fabric_spi_mosi_data_inv_i1;
-    input fabric_spi_mosi_data_inv_i2;
-    input fabric_spi_mosi_data_inv_i3;
-    output fabric_spi_mosi_full_o1;
-    output fabric_spi_mosi_full_o2;
-    output fabric_spi_mosi_full_o3;
-    input fabric_spi_mosi_push_i1;
-    input fabric_spi_mosi_push_i2;
-    input fabric_spi_mosi_push_i3;
-    input fabric_spi_needed_i1;
-    input fabric_spi_needed_i2;
-    input fabric_spi_needed_i3;
-    input fabric_spi_powerdown_cycle_i1;
-    input fabric_spi_powerdown_cycle_i10;
-    input fabric_spi_powerdown_cycle_i11;
-    input fabric_spi_powerdown_cycle_i12;
-    input fabric_spi_powerdown_cycle_i13;
-    input fabric_spi_powerdown_cycle_i14;
-    input fabric_spi_powerdown_cycle_i15;
-    input fabric_spi_powerdown_cycle_i16;
-    input fabric_spi_powerdown_cycle_i17;
-    input fabric_spi_powerdown_cycle_i18;
-    input fabric_spi_powerdown_cycle_i19;
-    input fabric_spi_powerdown_cycle_i2;
-    input fabric_spi_powerdown_cycle_i20;
-    input fabric_spi_powerdown_cycle_i21;
-    input fabric_spi_powerdown_cycle_i22;
-    input fabric_spi_powerdown_cycle_i23;
-    input fabric_spi_powerdown_cycle_i24;
-    input fabric_spi_powerdown_cycle_i25;
-    input fabric_spi_powerdown_cycle_i26;
-    input fabric_spi_powerdown_cycle_i27;
-    input fabric_spi_powerdown_cycle_i28;
-    input fabric_spi_powerdown_cycle_i29;
-    input fabric_spi_powerdown_cycle_i3;
-    input fabric_spi_powerdown_cycle_i30;
-    input fabric_spi_powerdown_cycle_i31;
-    input fabric_spi_powerdown_cycle_i32;
-    input fabric_spi_powerdown_cycle_i33;
-    input fabric_spi_powerdown_cycle_i34;
-    input fabric_spi_powerdown_cycle_i35;
-    input fabric_spi_powerdown_cycle_i36;
-    input fabric_spi_powerdown_cycle_i37;
-    input fabric_spi_powerdown_cycle_i38;
-    input fabric_spi_powerdown_cycle_i39;
-    input fabric_spi_powerdown_cycle_i4;
-    input fabric_spi_powerdown_cycle_i40;
-    input fabric_spi_powerdown_cycle_i41;
-    input fabric_spi_powerdown_cycle_i42;
-    input fabric_spi_powerdown_cycle_i43;
-    input fabric_spi_powerdown_cycle_i44;
-    input fabric_spi_powerdown_cycle_i45;
-    input fabric_spi_powerdown_cycle_i46;
-    input fabric_spi_powerdown_cycle_i47;
-    input fabric_spi_powerdown_cycle_i48;
-    input fabric_spi_powerdown_cycle_i5;
-    input fabric_spi_powerdown_cycle_i6;
-    input fabric_spi_powerdown_cycle_i7;
-    input fabric_spi_powerdown_cycle_i8;
-    input fabric_spi_powerdown_cycle_i9;
-    input fabric_spi_powerup_cycle_i1;
-    input fabric_spi_powerup_cycle_i10;
-    input fabric_spi_powerup_cycle_i11;
-    input fabric_spi_powerup_cycle_i12;
-    input fabric_spi_powerup_cycle_i13;
-    input fabric_spi_powerup_cycle_i14;
-    input fabric_spi_powerup_cycle_i15;
-    input fabric_spi_powerup_cycle_i16;
-    input fabric_spi_powerup_cycle_i17;
-    input fabric_spi_powerup_cycle_i18;
-    input fabric_spi_powerup_cycle_i19;
-    input fabric_spi_powerup_cycle_i2;
-    input fabric_spi_powerup_cycle_i20;
-    input fabric_spi_powerup_cycle_i21;
-    input fabric_spi_powerup_cycle_i22;
-    input fabric_spi_powerup_cycle_i23;
-    input fabric_spi_powerup_cycle_i24;
-    input fabric_spi_powerup_cycle_i25;
-    input fabric_spi_powerup_cycle_i26;
-    input fabric_spi_powerup_cycle_i27;
-    input fabric_spi_powerup_cycle_i28;
-    input fabric_spi_powerup_cycle_i29;
-    input fabric_spi_powerup_cycle_i3;
-    input fabric_spi_powerup_cycle_i30;
-    input fabric_spi_powerup_cycle_i31;
-    input fabric_spi_powerup_cycle_i32;
-    input fabric_spi_powerup_cycle_i33;
-    input fabric_spi_powerup_cycle_i34;
-    input fabric_spi_powerup_cycle_i35;
-    input fabric_spi_powerup_cycle_i36;
-    input fabric_spi_powerup_cycle_i37;
-    input fabric_spi_powerup_cycle_i38;
-    input fabric_spi_powerup_cycle_i39;
-    input fabric_spi_powerup_cycle_i4;
-    input fabric_spi_powerup_cycle_i40;
-    input fabric_spi_powerup_cycle_i41;
-    input fabric_spi_powerup_cycle_i42;
-    input fabric_spi_powerup_cycle_i43;
-    input fabric_spi_powerup_cycle_i44;
-    input fabric_spi_powerup_cycle_i45;
-    input fabric_spi_powerup_cycle_i46;
-    input fabric_spi_powerup_cycle_i47;
-    input fabric_spi_powerup_cycle_i48;
-    input fabric_spi_powerup_cycle_i5;
-    input fabric_spi_powerup_cycle_i6;
-    input fabric_spi_powerup_cycle_i7;
-    input fabric_spi_powerup_cycle_i8;
-    input fabric_spi_powerup_cycle_i9;
-    input fabric_spi_rst_n_i1;
-    input fabric_spi_rst_n_i2;
-    input fabric_spi_rst_n_i3;
-    input fabric_spi_sck_i0;
-    input fabric_spi_sck_i1;
-    input fabric_spi_sck_i2;
-    input fabric_spi_vcc_enable_i1;
-    input fabric_spi_vcc_enable_i2;
-    input fabric_spi_vcc_enable_i3;
-    output fabric_spi_vcc_used_o1;
-    output fabric_spi_vcc_used_o2;
-    output fabric_spi_vcc_used_o3;
-    input fabric_spw0_apb_slv_paddr_i1;
-    input fabric_spw0_apb_slv_paddr_i2;
-    input fabric_spw0_apb_slv_paddr_i3;
-    input fabric_spw0_apb_slv_paddr_i4;
-    input fabric_spw0_apb_slv_paddr_i5;
-    input fabric_spw0_apb_slv_penable_i;
-    output fabric_spw0_apb_slv_prdata_o1;
-    output fabric_spw0_apb_slv_prdata_o10;
-    output fabric_spw0_apb_slv_prdata_o11;
-    output fabric_spw0_apb_slv_prdata_o12;
-    output fabric_spw0_apb_slv_prdata_o13;
-    output fabric_spw0_apb_slv_prdata_o14;
-    output fabric_spw0_apb_slv_prdata_o15;
-    output fabric_spw0_apb_slv_prdata_o16;
-    output fabric_spw0_apb_slv_prdata_o17;
-    output fabric_spw0_apb_slv_prdata_o18;
-    output fabric_spw0_apb_slv_prdata_o19;
-    output fabric_spw0_apb_slv_prdata_o2;
-    output fabric_spw0_apb_slv_prdata_o20;
-    output fabric_spw0_apb_slv_prdata_o21;
-    output fabric_spw0_apb_slv_prdata_o22;
-    output fabric_spw0_apb_slv_prdata_o23;
-    output fabric_spw0_apb_slv_prdata_o24;
-    output fabric_spw0_apb_slv_prdata_o25;
-    output fabric_spw0_apb_slv_prdata_o26;
-    output fabric_spw0_apb_slv_prdata_o27;
-    output fabric_spw0_apb_slv_prdata_o28;
-    output fabric_spw0_apb_slv_prdata_o29;
-    output fabric_spw0_apb_slv_prdata_o3;
-    output fabric_spw0_apb_slv_prdata_o30;
-    output fabric_spw0_apb_slv_prdata_o31;
-    output fabric_spw0_apb_slv_prdata_o4;
-    output fabric_spw0_apb_slv_prdata_o5;
-    output fabric_spw0_apb_slv_prdata_o6;
-    output fabric_spw0_apb_slv_prdata_o7;
-    output fabric_spw0_apb_slv_prdata_o8;
-    output fabric_spw0_apb_slv_prdata_o9;
-    output fabric_spw0_apb_slv_pready_o;
-    input fabric_spw0_apb_slv_psel_i;
-    output fabric_spw0_apb_slv_pslverr_o;
-    input fabric_spw0_apb_slv_pwdata_i1;
-    input fabric_spw0_apb_slv_pwdata_i10;
-    input fabric_spw0_apb_slv_pwdata_i11;
-    input fabric_spw0_apb_slv_pwdata_i12;
-    input fabric_spw0_apb_slv_pwdata_i13;
-    input fabric_spw0_apb_slv_pwdata_i14;
-    input fabric_spw0_apb_slv_pwdata_i15;
-    input fabric_spw0_apb_slv_pwdata_i16;
-    input fabric_spw0_apb_slv_pwdata_i17;
-    input fabric_spw0_apb_slv_pwdata_i18;
-    input fabric_spw0_apb_slv_pwdata_i19;
-    input fabric_spw0_apb_slv_pwdata_i2;
-    input fabric_spw0_apb_slv_pwdata_i20;
-    input fabric_spw0_apb_slv_pwdata_i21;
-    input fabric_spw0_apb_slv_pwdata_i22;
-    input fabric_spw0_apb_slv_pwdata_i23;
-    input fabric_spw0_apb_slv_pwdata_i24;
-    input fabric_spw0_apb_slv_pwdata_i25;
-    input fabric_spw0_apb_slv_pwdata_i26;
-    input fabric_spw0_apb_slv_pwdata_i27;
-    input fabric_spw0_apb_slv_pwdata_i28;
-    input fabric_spw0_apb_slv_pwdata_i29;
-    input fabric_spw0_apb_slv_pwdata_i3;
-    input fabric_spw0_apb_slv_pwdata_i30;
-    input fabric_spw0_apb_slv_pwdata_i31;
-    input fabric_spw0_apb_slv_pwdata_i4;
-    input fabric_spw0_apb_slv_pwdata_i5;
-    input fabric_spw0_apb_slv_pwdata_i6;
-    input fabric_spw0_apb_slv_pwdata_i7;
-    input fabric_spw0_apb_slv_pwdata_i8;
-    input fabric_spw0_apb_slv_pwdata_i9;
-    input fabric_spw0_apb_slv_pwrite_i;
-    input fabric_spw0_clk_i;
-    input fabric_spw0_clk_tx_i;
-    input fabric_spw0_rst_n_i;
-    output fabric_spw0_rx_fifo_data_o1;
-    output fabric_spw0_rx_fifo_data_o2;
-    output fabric_spw0_rx_fifo_data_o3;
-    output fabric_spw0_rx_fifo_data_o4;
-    output fabric_spw0_rx_fifo_data_o5;
-    output fabric_spw0_rx_fifo_data_o6;
-    output fabric_spw0_rx_fifo_data_o7;
-    output fabric_spw0_rx_fifo_data_o8;
-    output fabric_spw0_rx_fifo_data_o9;
-    output fabric_spw0_rx_fifo_empty_o;
-    input fabric_spw0_rx_fifo_read_i;
-    input fabric_spw0_tick_ctm_i;
-    output fabric_spw0_tick_ctm_o;
-    input fabric_spw0_tx_fifo_data_i1;
-    input fabric_spw0_tx_fifo_data_i2;
-    input fabric_spw0_tx_fifo_data_i3;
-    input fabric_spw0_tx_fifo_data_i4;
-    input fabric_spw0_tx_fifo_data_i5;
-    input fabric_spw0_tx_fifo_data_i6;
-    input fabric_spw0_tx_fifo_data_i7;
-    input fabric_spw0_tx_fifo_data_i8;
-    input fabric_spw0_tx_fifo_data_i9;
-    output fabric_spw0_tx_fifo_full_o;
-    input fabric_spw0_tx_fifo_write_i;
-    output fabric_spw0_user_shared_o;
-    input fabric_spw1_apb_slv_paddr_i1;
-    input fabric_spw1_apb_slv_paddr_i2;
-    input fabric_spw1_apb_slv_paddr_i3;
-    input fabric_spw1_apb_slv_paddr_i4;
-    input fabric_spw1_apb_slv_paddr_i5;
-    input fabric_spw1_apb_slv_penable_i;
-    output fabric_spw1_apb_slv_prdata_o1;
-    output fabric_spw1_apb_slv_prdata_o10;
-    output fabric_spw1_apb_slv_prdata_o11;
-    output fabric_spw1_apb_slv_prdata_o12;
-    output fabric_spw1_apb_slv_prdata_o13;
-    output fabric_spw1_apb_slv_prdata_o14;
-    output fabric_spw1_apb_slv_prdata_o15;
-    output fabric_spw1_apb_slv_prdata_o16;
-    output fabric_spw1_apb_slv_prdata_o17;
-    output fabric_spw1_apb_slv_prdata_o18;
-    output fabric_spw1_apb_slv_prdata_o19;
-    output fabric_spw1_apb_slv_prdata_o2;
-    output fabric_spw1_apb_slv_prdata_o20;
-    output fabric_spw1_apb_slv_prdata_o21;
-    output fabric_spw1_apb_slv_prdata_o22;
-    output fabric_spw1_apb_slv_prdata_o23;
-    output fabric_spw1_apb_slv_prdata_o24;
-    output fabric_spw1_apb_slv_prdata_o25;
-    output fabric_spw1_apb_slv_prdata_o26;
-    output fabric_spw1_apb_slv_prdata_o27;
-    output fabric_spw1_apb_slv_prdata_o28;
-    output fabric_spw1_apb_slv_prdata_o29;
-    output fabric_spw1_apb_slv_prdata_o3;
-    output fabric_spw1_apb_slv_prdata_o30;
-    output fabric_spw1_apb_slv_prdata_o31;
-    output fabric_spw1_apb_slv_prdata_o4;
-    output fabric_spw1_apb_slv_prdata_o5;
-    output fabric_spw1_apb_slv_prdata_o6;
-    output fabric_spw1_apb_slv_prdata_o7;
-    output fabric_spw1_apb_slv_prdata_o8;
-    output fabric_spw1_apb_slv_prdata_o9;
-    output fabric_spw1_apb_slv_pready_o;
-    input fabric_spw1_apb_slv_psel_i;
-    output fabric_spw1_apb_slv_pslverr_o;
-    input fabric_spw1_apb_slv_pwdata_i1;
-    input fabric_spw1_apb_slv_pwdata_i10;
-    input fabric_spw1_apb_slv_pwdata_i11;
-    input fabric_spw1_apb_slv_pwdata_i12;
-    input fabric_spw1_apb_slv_pwdata_i13;
-    input fabric_spw1_apb_slv_pwdata_i14;
-    input fabric_spw1_apb_slv_pwdata_i15;
-    input fabric_spw1_apb_slv_pwdata_i16;
-    input fabric_spw1_apb_slv_pwdata_i17;
-    input fabric_spw1_apb_slv_pwdata_i18;
-    input fabric_spw1_apb_slv_pwdata_i19;
-    input fabric_spw1_apb_slv_pwdata_i2;
-    input fabric_spw1_apb_slv_pwdata_i20;
-    input fabric_spw1_apb_slv_pwdata_i21;
-    input fabric_spw1_apb_slv_pwdata_i22;
-    input fabric_spw1_apb_slv_pwdata_i23;
-    input fabric_spw1_apb_slv_pwdata_i24;
-    input fabric_spw1_apb_slv_pwdata_i25;
-    input fabric_spw1_apb_slv_pwdata_i26;
-    input fabric_spw1_apb_slv_pwdata_i27;
-    input fabric_spw1_apb_slv_pwdata_i28;
-    input fabric_spw1_apb_slv_pwdata_i29;
-    input fabric_spw1_apb_slv_pwdata_i3;
-    input fabric_spw1_apb_slv_pwdata_i30;
-    input fabric_spw1_apb_slv_pwdata_i31;
-    input fabric_spw1_apb_slv_pwdata_i4;
-    input fabric_spw1_apb_slv_pwdata_i5;
-    input fabric_spw1_apb_slv_pwdata_i6;
-    input fabric_spw1_apb_slv_pwdata_i7;
-    input fabric_spw1_apb_slv_pwdata_i8;
-    input fabric_spw1_apb_slv_pwdata_i9;
-    input fabric_spw1_apb_slv_pwrite_i;
-    input fabric_spw1_clk_i;
-    input fabric_spw1_clk_tx_i;
-    input fabric_spw1_rst_n_i;
-    output fabric_spw1_rx_fifo_data_o1;
-    output fabric_spw1_rx_fifo_data_o2;
-    output fabric_spw1_rx_fifo_data_o3;
-    output fabric_spw1_rx_fifo_data_o4;
-    output fabric_spw1_rx_fifo_data_o5;
-    output fabric_spw1_rx_fifo_data_o6;
-    output fabric_spw1_rx_fifo_data_o7;
-    output fabric_spw1_rx_fifo_data_o8;
-    output fabric_spw1_rx_fifo_data_o9;
-    output fabric_spw1_rx_fifo_empty_o;
-    input fabric_spw1_rx_fifo_read_i;
-    input fabric_spw1_tick_ctm_i;
-    output fabric_spw1_tick_ctm_o;
-    input fabric_spw1_tx_fifo_data_i1;
-    input fabric_spw1_tx_fifo_data_i2;
-    input fabric_spw1_tx_fifo_data_i3;
-    input fabric_spw1_tx_fifo_data_i4;
-    input fabric_spw1_tx_fifo_data_i5;
-    input fabric_spw1_tx_fifo_data_i6;
-    input fabric_spw1_tx_fifo_data_i7;
-    input fabric_spw1_tx_fifo_data_i8;
-    input fabric_spw1_tx_fifo_data_i9;
-    output fabric_spw1_tx_fifo_full_o;
-    input fabric_spw1_tx_fifo_write_i;
-    output fabric_spw1_user_shared_o;
-    output fabric_status_cold_start_o;
-    input fabric_thsens_arst_tmr_n_i1;
-    input fabric_thsens_arst_tmr_n_i2;
-    input fabric_thsens_arst_tmr_n_i3;
-    input fabric_thsens_clk_div_ratio_i1;
-    input fabric_thsens_clk_div_ratio_i2;
-    input fabric_thsens_clk_div_ratio_i3;
-    input fabric_thsens_clk_div_ratio_i4;
-    input fabric_thsens_clk_div_ratio_i5;
-    input fabric_thsens_clk_div_ratio_i6;
-    input fabric_thsens_clk_div_ratio_i7;
-    input fabric_thsens_clk_div_ratio_i8;
-    input fabric_thsens_clk_i;
-    output fabric_thsens_fm_config_r_o1;
-    output fabric_thsens_fm_config_r_o10;
-    output fabric_thsens_fm_config_r_o11;
-    output fabric_thsens_fm_config_r_o12;
-    output fabric_thsens_fm_config_r_o13;
-    output fabric_thsens_fm_config_r_o14;
-    output fabric_thsens_fm_config_r_o15;
-    output fabric_thsens_fm_config_r_o16;
-    output fabric_thsens_fm_config_r_o17;
-    output fabric_thsens_fm_config_r_o18;
-    output fabric_thsens_fm_config_r_o19;
-    output fabric_thsens_fm_config_r_o2;
-    output fabric_thsens_fm_config_r_o20;
-    output fabric_thsens_fm_config_r_o21;
-    output fabric_thsens_fm_config_r_o22;
-    output fabric_thsens_fm_config_r_o23;
-    output fabric_thsens_fm_config_r_o24;
-    output fabric_thsens_fm_config_r_o25;
-    output fabric_thsens_fm_config_r_o26;
-    output fabric_thsens_fm_config_r_o27;
-    output fabric_thsens_fm_config_r_o3;
-    output fabric_thsens_fm_config_r_o4;
-    output fabric_thsens_fm_config_r_o5;
-    output fabric_thsens_fm_config_r_o6;
-    output fabric_thsens_fm_config_r_o7;
-    output fabric_thsens_fm_config_r_o8;
-    output fabric_thsens_fm_config_r_o9;
-    input fabric_thsens_fm_config_w_i1;
-    input fabric_thsens_fm_config_w_i10;
-    input fabric_thsens_fm_config_w_i11;
-    input fabric_thsens_fm_config_w_i12;
-    input fabric_thsens_fm_config_w_i13;
-    input fabric_thsens_fm_config_w_i14;
-    input fabric_thsens_fm_config_w_i15;
-    input fabric_thsens_fm_config_w_i16;
-    input fabric_thsens_fm_config_w_i17;
-    input fabric_thsens_fm_config_w_i18;
-    input fabric_thsens_fm_config_w_i19;
-    input fabric_thsens_fm_config_w_i2;
-    input fabric_thsens_fm_config_w_i20;
-    input fabric_thsens_fm_config_w_i21;
-    input fabric_thsens_fm_config_w_i22;
-    input fabric_thsens_fm_config_w_i23;
-    input fabric_thsens_fm_config_w_i24;
-    input fabric_thsens_fm_config_w_i25;
-    input fabric_thsens_fm_config_w_i26;
-    input fabric_thsens_fm_config_w_i27;
-    input fabric_thsens_fm_config_w_i3;
-    input fabric_thsens_fm_config_w_i4;
-    input fabric_thsens_fm_config_w_i5;
-    input fabric_thsens_fm_config_w_i6;
-    input fabric_thsens_fm_config_w_i7;
-    input fabric_thsens_fm_config_w_i8;
-    input fabric_thsens_fm_config_w_i9;
-    input fabric_thsens_fm_config_wen_i;
-    output fabric_thsens_fm_data_o1;
-    output fabric_thsens_fm_data_o10;
-    output fabric_thsens_fm_data_o11;
-    output fabric_thsens_fm_data_o12;
-    output fabric_thsens_fm_data_o13;
-    output fabric_thsens_fm_data_o14;
-    output fabric_thsens_fm_data_o2;
-    output fabric_thsens_fm_data_o3;
-    output fabric_thsens_fm_data_o4;
-    output fabric_thsens_fm_data_o5;
-    output fabric_thsens_fm_data_o6;
-    output fabric_thsens_fm_data_o7;
-    output fabric_thsens_fm_data_o8;
-    output fabric_thsens_fm_data_o9;
-    input fabric_thsens_fm_enable_i;
-    output fabric_thsens_fm_mode_r_o1;
-    output fabric_thsens_fm_mode_r_o10;
-    output fabric_thsens_fm_mode_r_o11;
-    output fabric_thsens_fm_mode_r_o12;
-    output fabric_thsens_fm_mode_r_o13;
-    output fabric_thsens_fm_mode_r_o14;
-    output fabric_thsens_fm_mode_r_o15;
-    output fabric_thsens_fm_mode_r_o16;
-    output fabric_thsens_fm_mode_r_o17;
-    output fabric_thsens_fm_mode_r_o18;
-    output fabric_thsens_fm_mode_r_o19;
-    output fabric_thsens_fm_mode_r_o2;
-    output fabric_thsens_fm_mode_r_o20;
-    output fabric_thsens_fm_mode_r_o21;
-    output fabric_thsens_fm_mode_r_o22;
-    output fabric_thsens_fm_mode_r_o23;
-    output fabric_thsens_fm_mode_r_o24;
-    output fabric_thsens_fm_mode_r_o25;
-    output fabric_thsens_fm_mode_r_o26;
-    output fabric_thsens_fm_mode_r_o27;
-    output fabric_thsens_fm_mode_r_o28;
-    output fabric_thsens_fm_mode_r_o29;
-    output fabric_thsens_fm_mode_r_o3;
-    output fabric_thsens_fm_mode_r_o30;
-    output fabric_thsens_fm_mode_r_o31;
-    output fabric_thsens_fm_mode_r_o32;
-    output fabric_thsens_fm_mode_r_o4;
-    output fabric_thsens_fm_mode_r_o5;
-    output fabric_thsens_fm_mode_r_o6;
-    output fabric_thsens_fm_mode_r_o7;
-    output fabric_thsens_fm_mode_r_o8;
-    output fabric_thsens_fm_mode_r_o9;
-    input fabric_thsens_fm_mode_w_i1;
-    input fabric_thsens_fm_mode_w_i10;
-    input fabric_thsens_fm_mode_w_i11;
-    input fabric_thsens_fm_mode_w_i12;
-    input fabric_thsens_fm_mode_w_i13;
-    input fabric_thsens_fm_mode_w_i14;
-    input fabric_thsens_fm_mode_w_i15;
-    input fabric_thsens_fm_mode_w_i16;
-    input fabric_thsens_fm_mode_w_i17;
-    input fabric_thsens_fm_mode_w_i18;
-    input fabric_thsens_fm_mode_w_i19;
-    input fabric_thsens_fm_mode_w_i2;
-    input fabric_thsens_fm_mode_w_i20;
-    input fabric_thsens_fm_mode_w_i21;
-    input fabric_thsens_fm_mode_w_i22;
-    input fabric_thsens_fm_mode_w_i23;
-    input fabric_thsens_fm_mode_w_i24;
-    input fabric_thsens_fm_mode_w_i25;
-    input fabric_thsens_fm_mode_w_i26;
-    input fabric_thsens_fm_mode_w_i27;
-    input fabric_thsens_fm_mode_w_i28;
-    input fabric_thsens_fm_mode_w_i29;
-    input fabric_thsens_fm_mode_w_i3;
-    input fabric_thsens_fm_mode_w_i30;
-    input fabric_thsens_fm_mode_w_i31;
-    input fabric_thsens_fm_mode_w_i32;
-    input fabric_thsens_fm_mode_w_i4;
-    input fabric_thsens_fm_mode_w_i5;
-    input fabric_thsens_fm_mode_w_i6;
-    input fabric_thsens_fm_mode_w_i7;
-    input fabric_thsens_fm_mode_w_i8;
-    input fabric_thsens_fm_mode_w_i9;
-    input fabric_thsens_fm_mode_wen_i;
-    output fabric_thsens_fm_overflow_o;
-    output fabric_thsens_fm_valid_o;
-    output fabric_thsens_otp_config_o1;
-    output fabric_thsens_otp_config_o10;
-    output fabric_thsens_otp_config_o11;
-    output fabric_thsens_otp_config_o12;
-    output fabric_thsens_otp_config_o13;
-    output fabric_thsens_otp_config_o14;
-    output fabric_thsens_otp_config_o15;
-    output fabric_thsens_otp_config_o16;
-    output fabric_thsens_otp_config_o17;
-    output fabric_thsens_otp_config_o18;
-    output fabric_thsens_otp_config_o19;
-    output fabric_thsens_otp_config_o2;
-    output fabric_thsens_otp_config_o20;
-    output fabric_thsens_otp_config_o21;
-    output fabric_thsens_otp_config_o22;
-    output fabric_thsens_otp_config_o23;
-    output fabric_thsens_otp_config_o24;
-    output fabric_thsens_otp_config_o25;
-    output fabric_thsens_otp_config_o26;
-    output fabric_thsens_otp_config_o27;
-    output fabric_thsens_otp_config_o3;
-    output fabric_thsens_otp_config_o4;
-    output fabric_thsens_otp_config_o5;
-    output fabric_thsens_otp_config_o6;
-    output fabric_thsens_otp_config_o7;
-    output fabric_thsens_otp_config_o8;
-    output fabric_thsens_otp_config_o9;
-    input fabric_thsens_tst_scanenable_i;
-    input fabric_thsens_tst_scanin1_i;
-    input fabric_thsens_tst_scanin2_i;
-    output fabric_thsens_tst_scanout1_o;
-    output fabric_thsens_tst_scanout2_o;
-    input fabric_user_clk_i;
-    input fabric_user_data_i1;
-    input fabric_user_data_i10;
-    input fabric_user_data_i11;
-    input fabric_user_data_i12;
-    input fabric_user_data_i13;
-    input fabric_user_data_i14;
-    input fabric_user_data_i15;
-    input fabric_user_data_i16;
-    input fabric_user_data_i17;
-    input fabric_user_data_i18;
-    input fabric_user_data_i19;
-    input fabric_user_data_i2;
-    input fabric_user_data_i20;
-    input fabric_user_data_i21;
-    input fabric_user_data_i22;
-    input fabric_user_data_i23;
-    input fabric_user_data_i24;
-    input fabric_user_data_i25;
-    input fabric_user_data_i26;
-    input fabric_user_data_i27;
-    input fabric_user_data_i28;
-    input fabric_user_data_i29;
-    input fabric_user_data_i3;
-    input fabric_user_data_i30;
-    input fabric_user_data_i31;
-    input fabric_user_data_i32;
-    input fabric_user_data_i4;
-    input fabric_user_data_i5;
-    input fabric_user_data_i6;
-    input fabric_user_data_i7;
-    input fabric_user_data_i8;
-    input fabric_user_data_i9;
-    output fabric_user_data_o1;
-    output fabric_user_data_o10;
-    output fabric_user_data_o11;
-    output fabric_user_data_o12;
-    output fabric_user_data_o13;
-    output fabric_user_data_o14;
-    output fabric_user_data_o15;
-    output fabric_user_data_o16;
-    output fabric_user_data_o17;
-    output fabric_user_data_o18;
-    output fabric_user_data_o19;
-    output fabric_user_data_o2;
-    output fabric_user_data_o20;
-    output fabric_user_data_o21;
-    output fabric_user_data_o22;
-    output fabric_user_data_o23;
-    output fabric_user_data_o24;
-    output fabric_user_data_o25;
-    output fabric_user_data_o26;
-    output fabric_user_data_o27;
-    output fabric_user_data_o28;
-    output fabric_user_data_o29;
-    output fabric_user_data_o3;
-    output fabric_user_data_o30;
-    output fabric_user_data_o31;
-    output fabric_user_data_o32;
-    output fabric_user_data_o4;
-    output fabric_user_data_o5;
-    output fabric_user_data_o6;
-    output fabric_user_data_o7;
-    output fabric_user_data_o8;
-    output fabric_user_data_o9;
-    output fabric_user_read_cycle_o;
-    output fabric_user_write_cycle_o;
-    parameter bsm_config = 0;
-endmodule
-
-(* blackbox *)
-module NX_SERVICE_IF_U_FULL_WRAP(fabric_mrepair_clk_i, fabric_clk_otp_mrepair_o, fabric_mrepair_cke_i, fabric_mrepair_por_i, fabric_mrepair_cke_force_i, fabric_mrepair_rst_n_i, fabric_mrepair_initn_i, fabric_mrepair_bist_mode_o, fabric_mrepair_bend_i, fabric_mrepair_global_bbad_i, fabric_mrepair_global_repairable_i, fabric_mrepair_bypass_o, fabric_mrepair_memsafe_o, fabric_mrepair_mem_atpg_mode_o, fabric_mrepair_tst_gatedclock_o, fabric_mrepair_test_se_o, fabric_mrepair_data_to_system_o, fabric_mrepair_tst_atpg_mrepair_i, fabric_mrepair_data_from_system_i, fabric_mrepair_end_encoding_i, fabric_mrepair_system_dataready_o
-, fabric_mrepair_decoder_init_ready_o, fabric_mrepair_fuse_pdn_i, fabric_mrepair_fuse_bistmode_i, fabric_mrepair_fuse_tm_i, fabric_mrepair_fuse_read_i, fabric_mrepair_fuse_prog_i, fabric_mrepair_fuse_rbact1_i, fabric_mrepair_fuse_rbact2_i, fabric_mrepair_fuse_tstscanenable_i, fabric_mrepair_fuse_eccbypass_i, fabric_mrepair_fuse_wordlock_i, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_redbypass_i, fabric_mrepair_fuse_disturbchecked_i, fabric_mrepair_data_shift_en_i, fabric_mrepair_fuse_pwok_o, fabric_mrepair_fuse_ack_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_ded_o, fabric_mrepair_fuse_progfail_o, fabric_mrepair_fuse_locked_o
-, fabric_mrepair_fuse_disturbed_o, fabric_mrepair_fuse_bend1_o, fabric_mrepair_fuse_bend2_o, fabric_mrepair_fuse_bbad_o, fabric_mrepair_fuse_calibrated_o, fabric_mrepair_fuse_ready_o, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_otp_user_clk_i, fabric_otp_user_bistmode_i, fabric_otp_user_disturbcheck_i, fabric_otp_user_eccbypass_i, fabric_otp_user_pdn_i, fabric_otp_user_prog_i, fabric_otp_user_rbact1_i, fabric_otp_user_rbact2_i, fabric_otp_user_read_i, fabric_otp_user_redbypass_i, fabric_otp_user_suppadd_i, fabric_otp_user_tm_i, fabric_otp_user_tst_scanenable_i, fabric_otp_user_wordlock_i
-, fabric_otp_user_clock_frequency_range_i, fabric_otp_user_ack_o, fabric_otp_user_bbad_o, fabric_otp_user_bend1_o, fabric_otp_user_bend2_o, fabric_otp_user_calibrated_o, fabric_otp_user_ded_o, fabric_otp_user_disturbed_o, fabric_otp_user_locked_o, fabric_otp_user_progfail_o, fabric_otp_user_pwok_o, fabric_otp_user_sec_o, fabric_clk_bsm_o, fabric_clk_otp_mux_i, fabric_clk_otp_o, fabric_clk_user0_o, fabric_clk_user1_o, fabric_user_clk_i, fabric_user_write_cycle_o, fabric_user_read_cycle_o, fabric_cfg_fabric_user_flag_o
-, fabric_cfg_fabric_user_enable_o, fabric_parusr_clk_i, fabric_parusr_enable_i, fabric_parusr_cs_i, fabric_parusr_data_val_o, fabric_jtag_tck_o, fabric_jtag_trst_n_o, fabric_jtag_tms_o, fabric_jtag_tdi_o, fabric_jtag_usr1_o, fabric_jtag_usr2_o, fabric_jtag_tdo_usr1_i, fabric_jtag_tdo_usr2_i, fabric_otp_clk_i, fabric_otp_rst_i, fabric_otp_apb_write_i, fabric_otp_apb_sel_i, fabric_otp_apb_enable_i, fabric_otp_apb_ready_o, fabric_otp_cfg_fabric_apb_en_i, fabric_otp_cfg_loader_read_en_i
-, fabric_otp_cfg_loader_write_en_i, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_cfg_clk_fab_en_i, fabric_otp_security_ack_o, fabric_otp_security_rbact1_i, fabric_otp_security_rbact2_i, fabric_otp_security_bistmode_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_bist_end1_o, fabric_otp_security_bist_end2_o, fabric_otp_security_bist_bad_o, fabric_otp_security_testmode_i, fabric_otp_security_scanenable_i, fabric_status_cold_start_o, fabric_flag_trigger0_o, fabric_flag_trigger1_o, fabric_debug_rst_soft_o, fabric_debug_error_o, fabric_debug_otp_manager_read_otp_o, fabric_debug_otp_manager_read_done_o, fabric_debug_frame_use_encryption_o
-, fabric_debug_key_correct_o, fabric_debug_otp_reload_err_o, fabric_debug_access_reg_data_ready_o, fabric_debug_security_error_read_o, fabric_debug_security_boot_done_o, fabric_debug_lock_reg_o, fabric_dac0_clk_i, fabric_dac0_clk_en_i, fabric_dac0_reg_pwr_down_n_i, fabric_dac0_rstn_i, fabric_dac0_op_en_i, fabric_dac0_filt_en_i, fabric_dac0_comp_en_i, fabric_dac0_comp_ref_sel_i, fabric_dac0_comp_hyst_en_i, fabric_dac0_comp_out_o, fabric_cfg_dac0_reg_vref_select_i, fabric_cfg_dac0_reg_cm_select_i, fabric_cfg_dac0_sync_i, fabric_dac1_clk_i, fabric_dac1_clk_en_i
-, fabric_dac1_reg_pwr_down_n_i, fabric_dac1_rstn_i, fabric_dac1_op_en_i, fabric_dac1_filt_en_i, fabric_dac1_comp_en_i, fabric_dac1_comp_ref_sel_i, fabric_dac1_comp_hyst_en_i, fabric_dac1_comp_out_o, fabric_cfg_dac1_reg_vref_select_i, fabric_cfg_dac1_reg_cm_select_i, fabric_cfg_dac1_sync_i, fabric_dac2_clk_i, fabric_dac2_clk_en_i, fabric_dac2_reg_pwr_down_n_i, fabric_dac2_rstn_i, fabric_dac2_op_en_i, fabric_dac2_filt_en_i, fabric_dac2_comp_en_i, fabric_dac2_comp_ref_sel_i, fabric_dac2_comp_hyst_en_i, fabric_dac2_comp_out_o
-, fabric_cfg_dac2_reg_vref_select_i, fabric_cfg_dac2_reg_cm_select_i, fabric_cfg_dac2_sync_i, fabric_dac3_clk_i, fabric_dac3_clk_en_i, fabric_dac3_reg_pwr_down_n_i, fabric_dac3_rstn_i, fabric_dac3_op_en_i, fabric_dac3_filt_en_i, fabric_dac3_comp_en_i, fabric_dac3_comp_ref_sel_i, fabric_dac3_comp_hyst_en_i, fabric_dac3_comp_out_o, fabric_cfg_dac3_reg_vref_select_i, fabric_cfg_dac3_reg_cm_select_i, fabric_cfg_dac3_sync_i, fabric_adc0_clk_i, fabric_adc0_cal_start_i, fabric_adc0_cal_done_o, fabric_adc0_cal_p_overflow_o, fabric_adc0_cal_p_underflow_o
-, fabric_adc0_cal_n_overflow_o, fabric_adc0_cal_n_underflow_o, fabric_adc0_dft_scan_en_i, fabric_adc0_usr_cke_i, fabric_adc0_usr_conv_start_i, fabric_adc0_usr_conv_done_o, fabric_cfg_adc0_conv_done_delayed_i, fabric_cfg_adc0_use_cdc_i, fabric_adc1_clk_i, fabric_adc1_cal_start_i, fabric_adc1_cal_done_o, fabric_adc1_cal_p_overflow_o, fabric_adc1_cal_p_underflow_o, fabric_adc1_cal_n_overflow_o, fabric_adc1_cal_n_underflow_o, fabric_adc1_dft_scan_en_i, fabric_adc1_usr_cke_i, fabric_adc1_usr_conv_start_i, fabric_adc1_usr_conv_done_o, fabric_cfg_adc1_conv_done_delayed_i, fabric_cfg_adc1_use_cdc_i
-, fabric_adc2_clk_i, fabric_adc2_cal_start_i, fabric_adc2_cal_done_o, fabric_adc2_cal_p_overflow_o, fabric_adc2_cal_p_underflow_o, fabric_adc2_cal_n_overflow_o, fabric_adc2_cal_n_underflow_o, fabric_adc2_dft_scan_en_i, fabric_adc2_usr_cke_i, fabric_adc2_usr_conv_start_i, fabric_adc2_usr_conv_done_o, fabric_cfg_adc2_conv_done_delayed_i, fabric_cfg_adc2_use_cdc_i, fabric_adc3_clk_i, fabric_adc3_cal_start_i, fabric_adc3_cal_done_o, fabric_adc3_cal_p_overflow_o, fabric_adc3_cal_p_underflow_o, fabric_adc3_cal_n_overflow_o, fabric_adc3_cal_n_underflow_o, fabric_adc3_dft_scan_en_i
-, fabric_adc3_usr_cke_i, fabric_adc3_usr_conv_start_i, fabric_adc3_usr_conv_done_o, fabric_cfg_adc3_conv_done_delayed_i, fabric_cfg_adc3_use_cdc_i, fabric_direct0_scan_en_i, fabric_direct0_loopback_en_i, fabric_direct0_loopback_mux_i, fabric_direct2_scan_en_i, fabric_direct2_loopback_en_i, fabric_direct2_loopback_mux_i, fabric_direct1_scan_en_i, fabric_direct1_loopback_en_i, fabric_direct1_loopback_mux_i, fabric_thsens_clk_i, fabric_thsens_fm_enable_i, fabric_thsens_fm_mode_wen_i, fabric_thsens_fm_config_wen_i, fabric_thsens_fm_valid_o, fabric_thsens_fm_overflow_o, fabric_thsens_tst_scanenable_i
-, fabric_thsens_tst_scanin1_i, fabric_thsens_tst_scanin2_i, fabric_thsens_tst_scanout1_o, fabric_thsens_tst_scanout2_o, fabric_spi_clk_i2, fabric_spi_sck_i2, fabric_spi_clk_i0, fabric_spi_sck_i0, fabric_spi_clk_i1, fabric_spi_sck_i1, fabric_spw0_clk_i, fabric_spw0_clk_tx_i, fabric_spw0_rst_n_i, fabric_spw0_user_shared_o, fabric_spw0_tx_fifo_write_i, fabric_spw0_tx_fifo_full_o, fabric_spw0_rx_fifo_read_i, fabric_spw0_rx_fifo_empty_o, fabric_spw0_tick_ctm_i, fabric_spw0_tick_ctm_o, fabric_spw0_apb_slv_psel_i
-, fabric_spw0_apb_slv_penable_i, fabric_spw0_apb_slv_pwrite_i, fabric_spw0_apb_slv_pready_o, fabric_spw0_apb_slv_pslverr_o, fabric_spw1_clk_i, fabric_spw1_clk_tx_i, fabric_spw1_rst_n_i, fabric_spw1_user_shared_o, fabric_spw1_tx_fifo_write_i, fabric_spw1_tx_fifo_full_o, fabric_spw1_rx_fifo_read_i, fabric_spw1_rx_fifo_empty_o, fabric_spw1_tick_ctm_i, fabric_spw1_tick_ctm_o, fabric_spw1_apb_slv_psel_i, fabric_spw1_apb_slv_penable_i, fabric_spw1_apb_slv_pwrite_i, fabric_spw1_apb_slv_pready_o, fabric_spw1_apb_slv_pslverr_o, fabric_mrepair_data_to_bist_o, fabric_mrepair_shift_en_to_bist_o
-, fabric_mrepair_sif_load_en_to_bist_o, fabric_mrepair_sif_update_en_to_bist_o, fabric_mrepair_sif_reg_en_to_bist_o, fabric_mrepair_system_data_to_mem_bist_i, fabric_mrepair_shift_en_i, fabric_mrepair_sif_load_en_i, fabric_mrepair_sif_update_en_i, fabric_mrepair_sif_reg_en_i, fabric_mrepair_system_data_from_mem_bist_o, fabric_mrepair_mem_type_sel_o, fabric_mrepair_mode_sel_o, fabric_mrepair_mode_i, fabric_mrepair_pd_active_i, fabric_mrepair_chip_status_o, fabric_mrepair_global_chip_status_o, fabric_mrepair_pd_ready_o, fabric_mrepair_fuse_add_i, fabric_mrepair_fuse_din_i, fabric_mrepair_fuse_tst_scanin_i, fabric_mrepair_fuse_prgwidth_i, fabric_mrepair_fuse_dout_o
-, fabric_mrepair_fuse_startword_o, fabric_mrepair_fuse_wlromout_o, fabric_mrepair_fuse_bist1fail_o, fabric_mrepair_fuse_bist2fail_o, fabric_mrepair_fuse_tstscanout_o, fabric_mrepair_fuse_flagstate_o, fabric_mrepair_fuse_status_o, fabric_otp_user_add_i, fabric_otp_user_din_i, fabric_otp_user_prgwidth_i, fabric_otp_user_tst_scanin_i, fabric_otp_user_bist1fail_o, fabric_otp_user_bist2fail_o, fabric_otp_user_dout_o, fabric_otp_user_flagstate_o, fabric_otp_user_startword_o, fabric_otp_user_tst_scanout_o, fabric_otp_user_wlromout_o, fabric_io_in_i, fabric_io_oe_i, fabric_io_out_o
-, fabric_user_data_i, fabric_user_data_o, fabric_parusr_type_i, fabric_parusr_data_i, fabric_parusr_data_o, fabric_direct_data_i, fabric_direct_data_o, fabric_otp_apb_addr_i, fabric_otp_apb_wdata_i, fabric_otp_apb_rdata_o, fabric_otp_security_bist_fail1_o, fabric_otp_security_bist_fail2_o, fabric_otp_security_scanin_i, fabric_otp_security_scanout_o, fabric_flag_ready_TMR_o, fabric_debug_lifecycle_o, fabric_debug_fsm_state_o, fabric_debug_direct_permission_write_o, fabric_debug_direct_permission_read_o, fabric_debug_frame_permission_frame_o, fabric_debug_otpmgmt_state_o
-, fabric_debug_otpapb_state_o, fabric_debug_otpboot_state_o, fabric_debug_cpt_retry_o, fabric_debug_bsec_core_status_o, fabric_debug_otpboot_curr_addr_o, fabric_enable_TMR_i, fabric_lowskew_i, fabric_lowskew_o, fabric_spare_i, fabric_spare_o, fabric_dac0_din_i, fabric_dac0_comp_in_sel_i, fabric_cfg_dac0_reg_res_i, fabric_dac1_din_i, fabric_dac1_comp_in_sel_i, fabric_cfg_dac1_reg_res_i, fabric_dac2_din_i, fabric_dac2_comp_in_sel_i, fabric_cfg_dac2_reg_res_i, fabric_dac3_din_i, fabric_dac3_comp_in_sel_i
-, fabric_cfg_dac3_reg_res_i, fabric_adc0_arst_b_tmr_i, fabric_adc0_pwr_down_b_tmr_i, fabric_adc0_spare_i, fabric_adc0_dft_test_mode_i, fabric_adc0_dft_si_i, fabric_adc0_usr_arst_b_tmr_i, fabric_adc0_usr_channel_i, fabric_adc0_usr_sample_o, fabric_adc0_usr_sample_lsb_i, fabric_adc0_dbg_addr_i, fabric_adc0_dbg_data_o, fabric_cfg_adc0_clk_cal_div_ratio_i, fabric_adc1_arst_b_tmr_i, fabric_adc1_pwr_down_b_tmr_i, fabric_adc1_spare_i, fabric_adc1_dft_test_mode_i, fabric_adc1_dft_si_i, fabric_adc1_usr_arst_b_tmr_i, fabric_adc1_usr_channel_i, fabric_adc1_usr_sample_o
-, fabric_adc1_usr_sample_lsb_i, fabric_adc1_dbg_addr_i, fabric_adc1_dbg_data_o, fabric_cfg_adc1_clk_cal_div_ratio_i, fabric_adc2_arst_b_tmr_i, fabric_adc2_pwr_down_b_tmr_i, fabric_adc2_spare_i, fabric_adc2_dft_test_mode_i, fabric_adc2_dft_si_i, fabric_adc2_usr_arst_b_tmr_i, fabric_adc2_usr_channel_i, fabric_adc2_usr_sample_o, fabric_adc2_usr_sample_lsb_i, fabric_adc2_dbg_addr_i, fabric_adc2_dbg_data_o, fabric_cfg_adc2_clk_cal_div_ratio_i, fabric_adc3_arst_b_tmr_i, fabric_adc3_pwr_down_b_tmr_i, fabric_adc3_spare_i, fabric_adc3_dft_test_mode_i, fabric_adc3_dft_si_i
-, fabric_adc3_usr_arst_b_tmr_i, fabric_adc3_usr_channel_i, fabric_adc3_usr_sample_o, fabric_adc3_usr_sample_lsb_i, fabric_adc3_dbg_addr_i, fabric_adc3_dbg_data_o, fabric_cfg_adc3_clk_cal_div_ratio_i, fabric_direct0_clock_fabric_i, fabric_direct0_oe_i, fabric_direct0_oe_ena_i, fabric_direct0_oe_rs_i, fabric_direct0_do_i, fabric_direct0_do_ena_i, fabric_direct0_do_rs_i, fabric_direct0_di_o, fabric_direct0_di_ena_i, fabric_direct0_di_rs_i, fabric_direct0_cfg_bank_i, fabric_direct0_cfg_pad_i, fabric_direct2_clock_fabric_i, fabric_direct2_oe_i
-, fabric_direct2_oe_ena_i, fabric_direct2_oe_rs_i, fabric_direct2_do_i, fabric_direct2_do_ena_i, fabric_direct2_do_rs_i, fabric_direct2_di_o, fabric_direct2_di_ena_i, fabric_direct2_di_rs_i, fabric_direct2_cfg_bank_i, fabric_direct2_cfg_pad_i, fabric_direct1_clock_fabric_i, fabric_direct1_oe_i, fabric_direct1_oe_ena_i, fabric_direct1_oe_rs_i, fabric_direct1_do_i, fabric_direct1_do_ena_i, fabric_direct1_do_rs_i, fabric_direct1_di_o, fabric_direct1_di_ena_i, fabric_direct1_di_rs_i, fabric_direct1_cfg_bank_i
-, fabric_direct1_cfg_pad_i, fabric_thsens_arst_tmr_n_i, fabric_thsens_fm_mode_w_i, fabric_thsens_fm_config_w_i, fabric_thsens_fm_data_o, fabric_thsens_fm_mode_r_o, fabric_thsens_fm_config_r_o, fabric_thsens_clk_div_ratio_i, fabric_thsens_otp_config_o, fabric_spi_needed_i, fabric_spi_bsm_release_o, fabric_spi_arst_tmr_n_i, fabric_spi_fifo_arst_tmr_n_i, fabric_spi_cpol_i, fabric_spi_cpha_i, fabric_spi_loopback_i, fabric_spi_lsb_first_i, fabric_spi_cs_setuptime_i, fabric_spi_cs_holdtime_i, fabric_spi_cs_offtime_i, fabric_spi_vcc_enable_i
-, fabric_spi_powerdown_cycle_i, fabric_spi_powerup_cycle_i, fabric_spi_legacy_enable_i, fabric_spi_legacy_master_i, fabric_spi_data_in_unlimited_i, fabric_spi_enable_i, fabric_spi_rst_n_i, fabric_spi_init_done_o, fabric_spi_busy_o, fabric_spi_vcc_used_o, fabric_spi_error_sel_o, fabric_spi_error_loopback_o, fabric_spi_error_mode_o, fabric_spi_error_endianness_o, fabric_spi_cmd_push_i, fabric_spi_cmd_full_o, fabric_spi_cmd_type_i, fabric_spi_cmd_mode_i, fabric_spi_cmd_bytes_i, fabric_spi_mosi_push_i, fabric_spi_mosi_full_o
-, fabric_spi_mosi_data_i, fabric_spi_mosi_data_inv_i, fabric_spi_miso_pop_i, fabric_spi_miso_empty_o, fabric_spi_miso_data_o, fabric_spi_miso_data_inv_o, fabric_spw0_tx_fifo_data_i, fabric_spw0_rx_fifo_data_o, fabric_spw0_apb_slv_paddr_i, fabric_spw0_apb_slv_pwdata_i, fabric_spw0_apb_slv_prdata_o, fabric_spw1_tx_fifo_data_i, fabric_spw1_rx_fifo_data_o, fabric_spw1_apb_slv_paddr_i, fabric_spw1_apb_slv_pwdata_i, fabric_spw1_apb_slv_prdata_o, fabric_mrepair_data_from_bist_i);
-    input [2:0] fabric_adc0_arst_b_tmr_i;
-    output fabric_adc0_cal_done_o;
-    output fabric_adc0_cal_n_overflow_o;
-    output fabric_adc0_cal_n_underflow_o;
-    output fabric_adc0_cal_p_overflow_o;
-    output fabric_adc0_cal_p_underflow_o;
-    input fabric_adc0_cal_start_i;
-    input fabric_adc0_clk_i;
-    input [3:0] fabric_adc0_dbg_addr_i;
-    output [31:0] fabric_adc0_dbg_data_o;
-    input fabric_adc0_dft_scan_en_i;
-    input [11:0] fabric_adc0_dft_si_i;
-    input [1:0] fabric_adc0_dft_test_mode_i;
-    input [2:0] fabric_adc0_pwr_down_b_tmr_i;
-    input [15:0] fabric_adc0_spare_i;
-    input [2:0] fabric_adc0_usr_arst_b_tmr_i;
-    input [2:0] fabric_adc0_usr_channel_i;
-    input fabric_adc0_usr_cke_i;
-    output fabric_adc0_usr_conv_done_o;
-    input fabric_adc0_usr_conv_start_i;
-    input [3:0] fabric_adc0_usr_sample_lsb_i;
-    output [11:0] fabric_adc0_usr_sample_o;
-    input [2:0] fabric_adc1_arst_b_tmr_i;
-    output fabric_adc1_cal_done_o;
-    output fabric_adc1_cal_n_overflow_o;
-    output fabric_adc1_cal_n_underflow_o;
-    output fabric_adc1_cal_p_overflow_o;
-    output fabric_adc1_cal_p_underflow_o;
-    input fabric_adc1_cal_start_i;
-    input fabric_adc1_clk_i;
-    input [3:0] fabric_adc1_dbg_addr_i;
-    output [31:0] fabric_adc1_dbg_data_o;
-    input fabric_adc1_dft_scan_en_i;
-    input [11:0] fabric_adc1_dft_si_i;
-    input [1:0] fabric_adc1_dft_test_mode_i;
-    input [2:0] fabric_adc1_pwr_down_b_tmr_i;
-    input [15:0] fabric_adc1_spare_i;
-    input [2:0] fabric_adc1_usr_arst_b_tmr_i;
-    input [2:0] fabric_adc1_usr_channel_i;
-    input fabric_adc1_usr_cke_i;
-    output fabric_adc1_usr_conv_done_o;
-    input fabric_adc1_usr_conv_start_i;
-    input [3:0] fabric_adc1_usr_sample_lsb_i;
-    output [11:0] fabric_adc1_usr_sample_o;
-    input [2:0] fabric_adc2_arst_b_tmr_i;
-    output fabric_adc2_cal_done_o;
-    output fabric_adc2_cal_n_overflow_o;
-    output fabric_adc2_cal_n_underflow_o;
-    output fabric_adc2_cal_p_overflow_o;
-    output fabric_adc2_cal_p_underflow_o;
-    input fabric_adc2_cal_start_i;
-    input fabric_adc2_clk_i;
-    input [3:0] fabric_adc2_dbg_addr_i;
-    output [31:0] fabric_adc2_dbg_data_o;
-    input fabric_adc2_dft_scan_en_i;
-    input [11:0] fabric_adc2_dft_si_i;
-    input [1:0] fabric_adc2_dft_test_mode_i;
-    input [2:0] fabric_adc2_pwr_down_b_tmr_i;
-    input [15:0] fabric_adc2_spare_i;
-    input [2:0] fabric_adc2_usr_arst_b_tmr_i;
-    input [2:0] fabric_adc2_usr_channel_i;
-    input fabric_adc2_usr_cke_i;
-    output fabric_adc2_usr_conv_done_o;
-    input fabric_adc2_usr_conv_start_i;
-    input [3:0] fabric_adc2_usr_sample_lsb_i;
-    output [11:0] fabric_adc2_usr_sample_o;
-    input [2:0] fabric_adc3_arst_b_tmr_i;
-    output fabric_adc3_cal_done_o;
-    output fabric_adc3_cal_n_overflow_o;
-    output fabric_adc3_cal_n_underflow_o;
-    output fabric_adc3_cal_p_overflow_o;
-    output fabric_adc3_cal_p_underflow_o;
-    input fabric_adc3_cal_start_i;
-    input fabric_adc3_clk_i;
-    input [3:0] fabric_adc3_dbg_addr_i;
-    output [31:0] fabric_adc3_dbg_data_o;
-    input fabric_adc3_dft_scan_en_i;
-    input [11:0] fabric_adc3_dft_si_i;
-    input [1:0] fabric_adc3_dft_test_mode_i;
-    input [2:0] fabric_adc3_pwr_down_b_tmr_i;
-    input [15:0] fabric_adc3_spare_i;
-    input [2:0] fabric_adc3_usr_arst_b_tmr_i;
-    input [2:0] fabric_adc3_usr_channel_i;
-    input fabric_adc3_usr_cke_i;
-    output fabric_adc3_usr_conv_done_o;
-    input fabric_adc3_usr_conv_start_i;
-    input [3:0] fabric_adc3_usr_sample_lsb_i;
-    output [11:0] fabric_adc3_usr_sample_o;
-    input [4:0] fabric_cfg_adc0_clk_cal_div_ratio_i;
-    input fabric_cfg_adc0_conv_done_delayed_i;
-    input fabric_cfg_adc0_use_cdc_i;
-    input [4:0] fabric_cfg_adc1_clk_cal_div_ratio_i;
-    input fabric_cfg_adc1_conv_done_delayed_i;
-    input fabric_cfg_adc1_use_cdc_i;
-    input [4:0] fabric_cfg_adc2_clk_cal_div_ratio_i;
-    input fabric_cfg_adc2_conv_done_delayed_i;
-    input fabric_cfg_adc2_use_cdc_i;
-    input [4:0] fabric_cfg_adc3_clk_cal_div_ratio_i;
-    input fabric_cfg_adc3_conv_done_delayed_i;
-    input fabric_cfg_adc3_use_cdc_i;
-    input fabric_cfg_dac0_reg_cm_select_i;
-    input [1:0] fabric_cfg_dac0_reg_res_i;
-    input fabric_cfg_dac0_reg_vref_select_i;
-    input fabric_cfg_dac0_sync_i;
-    input fabric_cfg_dac1_reg_cm_select_i;
-    input [1:0] fabric_cfg_dac1_reg_res_i;
-    input fabric_cfg_dac1_reg_vref_select_i;
-    input fabric_cfg_dac1_sync_i;
-    input fabric_cfg_dac2_reg_cm_select_i;
-    input [1:0] fabric_cfg_dac2_reg_res_i;
-    input fabric_cfg_dac2_reg_vref_select_i;
-    input fabric_cfg_dac2_sync_i;
-    input fabric_cfg_dac3_reg_cm_select_i;
-    input [1:0] fabric_cfg_dac3_reg_res_i;
-    input fabric_cfg_dac3_reg_vref_select_i;
-    input fabric_cfg_dac3_sync_i;
-    output fabric_cfg_fabric_user_enable_o;
-    output fabric_cfg_fabric_user_flag_o;
-    output fabric_clk_bsm_o;
-    output fabric_clk_otp_mrepair_o;
-    input fabric_clk_otp_mux_i;
-    output fabric_clk_otp_o;
-    output fabric_clk_user0_o;
-    output fabric_clk_user1_o;
-    input fabric_dac0_clk_en_i;
-    input fabric_dac0_clk_i;
-    input fabric_dac0_comp_en_i;
-    input fabric_dac0_comp_hyst_en_i;
-    input [3:0] fabric_dac0_comp_in_sel_i;
-    output fabric_dac0_comp_out_o;
-    input fabric_dac0_comp_ref_sel_i;
-    input [12:0] fabric_dac0_din_i;
-    input fabric_dac0_filt_en_i;
-    input fabric_dac0_op_en_i;
-    input fabric_dac0_reg_pwr_down_n_i;
-    input fabric_dac0_rstn_i;
-    input fabric_dac1_clk_en_i;
-    input fabric_dac1_clk_i;
-    input fabric_dac1_comp_en_i;
-    input fabric_dac1_comp_hyst_en_i;
-    input [3:0] fabric_dac1_comp_in_sel_i;
-    output fabric_dac1_comp_out_o;
-    input fabric_dac1_comp_ref_sel_i;
-    input [12:0] fabric_dac1_din_i;
-    input fabric_dac1_filt_en_i;
-    input fabric_dac1_op_en_i;
-    input fabric_dac1_reg_pwr_down_n_i;
-    input fabric_dac1_rstn_i;
-    input fabric_dac2_clk_en_i;
-    input fabric_dac2_clk_i;
-    input fabric_dac2_comp_en_i;
-    input fabric_dac2_comp_hyst_en_i;
-    input [12:0] fabric_dac2_comp_in_sel_i;
-    output fabric_dac2_comp_out_o;
-    input fabric_dac2_comp_ref_sel_i;
-    input [12:0] fabric_dac2_din_i;
-    input fabric_dac2_filt_en_i;
-    input fabric_dac2_op_en_i;
-    input fabric_dac2_reg_pwr_down_n_i;
-    input fabric_dac2_rstn_i;
-    input fabric_dac3_clk_en_i;
-    input fabric_dac3_clk_i;
-    input fabric_dac3_comp_en_i;
-    input fabric_dac3_comp_hyst_en_i;
-    input [3:0] fabric_dac3_comp_in_sel_i;
-    output fabric_dac3_comp_out_o;
-    input fabric_dac3_comp_ref_sel_i;
-    input [12:0] fabric_dac3_din_i;
-    input fabric_dac3_filt_en_i;
-    input fabric_dac3_op_en_i;
-    input fabric_dac3_reg_pwr_down_n_i;
-    input fabric_dac3_rstn_i;
-    output fabric_debug_access_reg_data_ready_o;
-    output [31:0] fabric_debug_bsec_core_status_o;
-    output [3:0] fabric_debug_cpt_retry_o;
-    output [3:0] fabric_debug_direct_permission_read_o;
-    output [3:0] fabric_debug_direct_permission_write_o;
-    output fabric_debug_error_o;
-    output [3:0] fabric_debug_frame_permission_frame_o;
-    output fabric_debug_frame_use_encryption_o;
-    output [2:0] fabric_debug_fsm_state_o;
-    output fabric_debug_key_correct_o;
-    output [3:0] fabric_debug_lifecycle_o;
-    output fabric_debug_lock_reg_o;
-    output fabric_debug_otp_manager_read_done_o;
-    output fabric_debug_otp_manager_read_otp_o;
-    output fabric_debug_otp_reload_err_o;
-    output [2:0] fabric_debug_otpapb_state_o;
-    output [7:0] fabric_debug_otpboot_curr_addr_o;
-    output [2:0] fabric_debug_otpboot_state_o;
-    output [2:0] fabric_debug_otpmgmt_state_o;
-    output fabric_debug_rst_soft_o;
-    output fabric_debug_security_boot_done_o;
-    output fabric_debug_security_error_read_o;
-    input [3:0] fabric_direct0_cfg_bank_i;
-    input [719:0] fabric_direct0_cfg_pad_i;
-    input [3:0] fabric_direct0_clock_fabric_i;
-    input [23:0] fabric_direct0_di_ena_i;
-    output [23:0] fabric_direct0_di_o;
-    input [23:0] fabric_direct0_di_rs_i;
-    input [23:0] fabric_direct0_do_ena_i;
-    input [23:0] fabric_direct0_do_i;
-    input [23:0] fabric_direct0_do_rs_i;
-    input fabric_direct0_loopback_en_i;
-    input fabric_direct0_loopback_mux_i;
-    input [23:0] fabric_direct0_oe_ena_i;
-    input [23:0] fabric_direct0_oe_i;
-    input [23:0] fabric_direct0_oe_rs_i;
-    input fabric_direct0_scan_en_i;
-    input [3:0] fabric_direct1_cfg_bank_i;
-    input [479:0] fabric_direct1_cfg_pad_i;
-    input [3:0] fabric_direct1_clock_fabric_i;
-    input [15:0] fabric_direct1_di_ena_i;
-    output [15:0] fabric_direct1_di_o;
-    input [15:0] fabric_direct1_di_rs_i;
-    input [15:0] fabric_direct1_do_ena_i;
-    input [15:0] fabric_direct1_do_i;
-    input [15:0] fabric_direct1_do_rs_i;
-    input fabric_direct1_loopback_en_i;
-    input fabric_direct1_loopback_mux_i;
-    input [15:0] fabric_direct1_oe_ena_i;
-    input [15:0] fabric_direct1_oe_i;
-    input [15:0] fabric_direct1_oe_rs_i;
-    input fabric_direct1_scan_en_i;
-    input [3:0] fabric_direct2_cfg_bank_i;
-    input [719:0] fabric_direct2_cfg_pad_i;
-    input [3:0] fabric_direct2_clock_fabric_i;
-    input [23:0] fabric_direct2_di_ena_i;
-    output [23:0] fabric_direct2_di_o;
-    input [23:0] fabric_direct2_di_rs_i;
-    input [23:0] fabric_direct2_do_ena_i;
-    input [23:0] fabric_direct2_do_i;
-    input [23:0] fabric_direct2_do_rs_i;
-    input fabric_direct2_loopback_en_i;
-    input fabric_direct2_loopback_mux_i;
-    input [23:0] fabric_direct2_oe_ena_i;
-    input [23:0] fabric_direct2_oe_i;
-    input [23:0] fabric_direct2_oe_rs_i;
-    input fabric_direct2_scan_en_i;
-    input [31:0] fabric_direct_data_i;
-    output [31:0] fabric_direct_data_o;
-    input [2:0] fabric_enable_TMR_i;
-    output [2:0] fabric_flag_ready_TMR_o;
-    output fabric_flag_trigger0_o;
-    output fabric_flag_trigger1_o;
-    input [34:0] fabric_io_in_i;
-    input [34:0] fabric_io_oe_i;
-    output [34:0] fabric_io_out_o;
-    output fabric_jtag_tck_o;
-    output fabric_jtag_tdi_o;
-    input fabric_jtag_tdo_usr1_i;
-    input fabric_jtag_tdo_usr2_i;
-    output fabric_jtag_tms_o;
-    output fabric_jtag_trst_n_o;
-    output fabric_jtag_usr1_o;
-    output fabric_jtag_usr2_o;
-    input [39:0] fabric_lowskew_i;
-    output [5:0] fabric_lowskew_o;
-    input fabric_mrepair_bend_i;
-    output fabric_mrepair_bist_mode_o;
-    output fabric_mrepair_bypass_o;
-    output [77:0] fabric_mrepair_chip_status_o;
-    input fabric_mrepair_cke_force_i;
-    input fabric_mrepair_cke_i;
-    input fabric_mrepair_clk_i;
-    input [25:0] fabric_mrepair_data_from_bist_i;
-    input fabric_mrepair_data_from_system_i;
-    input fabric_mrepair_data_shift_en_i;
-    output [25:0] fabric_mrepair_data_to_bist_o;
-    output fabric_mrepair_data_to_system_o;
-    output fabric_mrepair_decoder_init_ready_o;
-    input fabric_mrepair_end_encoding_i;
-    output fabric_mrepair_fuse_ack_o;
-    input [6:0] fabric_mrepair_fuse_add_i;
-    output fabric_mrepair_fuse_bbad_o;
-    output fabric_mrepair_fuse_bend1_o;
-    output fabric_mrepair_fuse_bend2_o;
-    output [7:0] fabric_mrepair_fuse_bist1fail_o;
-    output [6:0] fabric_mrepair_fuse_bist2fail_o;
-    input fabric_mrepair_fuse_bistmode_i;
-    output fabric_mrepair_fuse_calibrated_o;
-    output fabric_mrepair_fuse_ded_o;
-    input [38:0] fabric_mrepair_fuse_din_i;
-    input fabric_mrepair_fuse_disturbchecked_i;
-    output fabric_mrepair_fuse_disturbed_o;
-    output [40:0] fabric_mrepair_fuse_dout_o;
-    input fabric_mrepair_fuse_eccbypass_i;
-    output [3:0] fabric_mrepair_fuse_flagstate_o;
-    output fabric_mrepair_fuse_locked_o;
-    input fabric_mrepair_fuse_pdn_i;
-    output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o;
-    input [2:0] fabric_mrepair_fuse_prgwidth_i;
-    input fabric_mrepair_fuse_prog_i;
-    output fabric_mrepair_fuse_progfail_o;
-    output fabric_mrepair_fuse_pwok_o;
-    input fabric_mrepair_fuse_rbact1_i;
-    input fabric_mrepair_fuse_rbact2_i;
-    input fabric_mrepair_fuse_read_i;
-    output fabric_mrepair_fuse_ready_o;
-    input fabric_mrepair_fuse_redbypass_i;
-    output fabric_mrepair_fuse_sec_o;
-    output [15:0] fabric_mrepair_fuse_startword_o;
-    output [2:0] fabric_mrepair_fuse_status_o;
-    input fabric_mrepair_fuse_suppadd_i;
-    input fabric_mrepair_fuse_tm_i;
-    input [4:0] fabric_mrepair_fuse_tst_scanin_i;
-    input fabric_mrepair_fuse_tstscanenable_i;
-    output [4:0] fabric_mrepair_fuse_tstscanout_o;
-    output [9:0] fabric_mrepair_fuse_wlromout_o;
-    input fabric_mrepair_fuse_wordlock_i;
-    input fabric_mrepair_global_bbad_i;
-    output [2:0] fabric_mrepair_global_chip_status_o;
-    input fabric_mrepair_global_repairable_i;
-    input fabric_mrepair_initn_i;
-    output fabric_mrepair_mem_atpg_mode_o;
-    output [4:0] fabric_mrepair_mem_type_sel_o;
-    output fabric_mrepair_memsafe_o;
-    input [3:0] fabric_mrepair_mode_i;
-    output [3:0] fabric_mrepair_mode_sel_o;
-    input [25:0] fabric_mrepair_pd_active_i;
-    output [25:0] fabric_mrepair_pd_ready_o;
-    input fabric_mrepair_por_i;
-    input fabric_mrepair_rst_n_i;
-    input [25:0] fabric_mrepair_shift_en_i;
-    output [25:0] fabric_mrepair_shift_en_to_bist_o;
-    input [25:0] fabric_mrepair_sif_load_en_i;
-    output [25:0] fabric_mrepair_sif_load_en_to_bist_o;
-    input [25:0] fabric_mrepair_sif_reg_en_i;
-    output [25:0] fabric_mrepair_sif_reg_en_to_bist_o;
-    input [25:0] fabric_mrepair_sif_update_en_i;
-    output [25:0] fabric_mrepair_sif_update_en_to_bist_o;
-    output [25:0] fabric_mrepair_system_data_from_mem_bist_o;
-    input [25:0] fabric_mrepair_system_data_to_mem_bist_i;
-    output fabric_mrepair_system_dataready_o;
-    output fabric_mrepair_test_se_o;
-    input fabric_mrepair_tst_atpg_mrepair_i;
-    output fabric_mrepair_tst_gatedclock_o;
-    input [31:0] fabric_otp_apb_addr_i;
-    input fabric_otp_apb_enable_i;
-    output [31:0] fabric_otp_apb_rdata_o;
-    output fabric_otp_apb_ready_o;
-    input fabric_otp_apb_sel_i;
-    input [31:0] fabric_otp_apb_wdata_i;
-    input fabric_otp_apb_write_i;
-    input fabric_otp_cfg_clk_fab_en_i;
-    input fabric_otp_cfg_clk_otpm_disable_i;
-    input fabric_otp_cfg_fabric_apb_en_i;
-    input fabric_otp_cfg_loader_read_en_i;
-    input fabric_otp_cfg_loader_write_en_i;
-    input fabric_otp_clk_i;
-    input fabric_otp_rst_i;
-    output fabric_otp_security_ack_o;
-    output fabric_otp_security_bist_bad_o;
-    output fabric_otp_security_bist_end1_o;
-    output fabric_otp_security_bist_end2_o;
-    output [6:0] fabric_otp_security_bist_fail1_o;
-    output [5:0] fabric_otp_security_bist_fail2_o;
-    input fabric_otp_security_bistmode_i;
-    input fabric_otp_security_force_pdn1_i;
-    input fabric_otp_security_rbact1_i;
-    input fabric_otp_security_rbact2_i;
-    input fabric_otp_security_scanenable_i;
-    input [3:0] fabric_otp_security_scanin_i;
-    output [3:0] fabric_otp_security_scanout_o;
-    input fabric_otp_security_testmode_i;
-    output fabric_otp_user_ack_o;
-    input [6:0] fabric_otp_user_add_i;
-    output fabric_otp_user_bbad_o;
-    output fabric_otp_user_bend1_o;
-    output fabric_otp_user_bend2_o;
-    output [7:0] fabric_otp_user_bist1fail_o;
-    output [6:0] fabric_otp_user_bist2fail_o;
-    input fabric_otp_user_bistmode_i;
-    output fabric_otp_user_calibrated_o;
-    input fabric_otp_user_clk_i;
-    input fabric_otp_user_clock_frequency_range_i;
-    output fabric_otp_user_ded_o;
-    input [38:0] fabric_otp_user_din_i;
-    input fabric_otp_user_disturbcheck_i;
-    output fabric_otp_user_disturbed_o;
-    output [40:0] fabric_otp_user_dout_o;
-    input fabric_otp_user_eccbypass_i;
-    output [3:0] fabric_otp_user_flagstate_o;
-    output fabric_otp_user_locked_o;
-    input fabric_otp_user_pdn_i;
-    input [2:0] fabric_otp_user_prgwidth_i;
-    input fabric_otp_user_prog_i;
-    output fabric_otp_user_progfail_o;
-    output fabric_otp_user_pwok_o;
-    input fabric_otp_user_rbact1_i;
-    input fabric_otp_user_rbact2_i;
-    input fabric_otp_user_read_i;
-    input fabric_otp_user_redbypass_i;
-    output fabric_otp_user_sec_o;
-    output [15:0] fabric_otp_user_startword_o;
-    input fabric_otp_user_suppadd_i;
-    input fabric_otp_user_tm_i;
-    input fabric_otp_user_tst_scanenable_i;
-    input [4:0] fabric_otp_user_tst_scanin_i;
-    output [4:0] fabric_otp_user_tst_scanout_o;
-    output [9:0] fabric_otp_user_wlromout_o;
-    input fabric_otp_user_wordlock_i;
-    input fabric_parusr_clk_i;
-    input fabric_parusr_cs_i;
-    input [15:0] fabric_parusr_data_i;
-    output [15:0] fabric_parusr_data_o;
-    output fabric_parusr_data_val_o;
-    input fabric_parusr_enable_i;
-    input [1:0] fabric_parusr_type_i;
-    input [127:0] fabric_spare_i;
-    output [127:0] fabric_spare_o;
-    input [8:0] fabric_spi_arst_tmr_n_i;
-    output [2:0] fabric_spi_bsm_release_o;
-    output [2:0] fabric_spi_busy_o;
-    input fabric_spi_clk_i0;
-    input fabric_spi_clk_i1;
-    input fabric_spi_clk_i2;
-    input [5:0] fabric_spi_cmd_bytes_i;
-    output [2:0] fabric_spi_cmd_full_o;
-    input [5:0] fabric_spi_cmd_mode_i;
-    input [2:0] fabric_spi_cmd_push_i;
-    input [5:0] fabric_spi_cmd_type_i;
-    input [2:0] fabric_spi_cpha_i;
-    input [2:0] fabric_spi_cpol_i;
-    input [11:0] fabric_spi_cs_holdtime_i;
-    input [11:0] fabric_spi_cs_offtime_i;
-    input [11:0] fabric_spi_cs_setuptime_i;
-    input [2:0] fabric_spi_data_in_unlimited_i;
-    input [2:0] fabric_spi_enable_i;
-    output [2:0] fabric_spi_error_endianness_o;
-    output [2:0] fabric_spi_error_loopback_o;
-    output [2:0] fabric_spi_error_mode_o;
-    output [2:0] fabric_spi_error_sel_o;
-    input [8:0] fabric_spi_fifo_arst_tmr_n_i;
-    output [2:0] fabric_spi_init_done_o;
-    input [2:0] fabric_spi_legacy_enable_i;
-    input [2:0] fabric_spi_legacy_master_i;
-    input [2:0] fabric_spi_loopback_i;
-    input [2:0] fabric_spi_lsb_first_i;
-    output [2:0] fabric_spi_miso_data_inv_o;
-    output [23:0] fabric_spi_miso_data_o;
-    output [2:0] fabric_spi_miso_empty_o;
-    input [2:0] fabric_spi_miso_pop_i;
-    input [23:0] fabric_spi_mosi_data_i;
-    input [2:0] fabric_spi_mosi_data_inv_i;
-    output [2:0] fabric_spi_mosi_full_o;
-    input [2:0] fabric_spi_mosi_push_i;
-    input [2:0] fabric_spi_needed_i;
-    input [47:0] fabric_spi_powerdown_cycle_i;
-    input [47:0] fabric_spi_powerup_cycle_i;
-    input [2:0] fabric_spi_rst_n_i;
-    input fabric_spi_sck_i0;
-    input fabric_spi_sck_i1;
-    input fabric_spi_sck_i2;
-    input [2:0] fabric_spi_vcc_enable_i;
-    output [2:0] fabric_spi_vcc_used_o;
-    input [6:2] fabric_spw0_apb_slv_paddr_i;
-    input fabric_spw0_apb_slv_penable_i;
-    output [30:0] fabric_spw0_apb_slv_prdata_o;
-    output fabric_spw0_apb_slv_pready_o;
-    input fabric_spw0_apb_slv_psel_i;
-    output fabric_spw0_apb_slv_pslverr_o;
-    input [30:0] fabric_spw0_apb_slv_pwdata_i;
-    input fabric_spw0_apb_slv_pwrite_i;
-    input fabric_spw0_clk_i;
-    input fabric_spw0_clk_tx_i;
-    input fabric_spw0_rst_n_i;
-    output [8:0] fabric_spw0_rx_fifo_data_o;
-    output fabric_spw0_rx_fifo_empty_o;
-    input fabric_spw0_rx_fifo_read_i;
-    input fabric_spw0_tick_ctm_i;
-    output fabric_spw0_tick_ctm_o;
-    input [8:0] fabric_spw0_tx_fifo_data_i;
-    output fabric_spw0_tx_fifo_full_o;
-    input fabric_spw0_tx_fifo_write_i;
-    output fabric_spw0_user_shared_o;
-    input [6:2] fabric_spw1_apb_slv_paddr_i;
-    input fabric_spw1_apb_slv_penable_i;
-    output [30:0] fabric_spw1_apb_slv_prdata_o;
-    output fabric_spw1_apb_slv_pready_o;
-    input fabric_spw1_apb_slv_psel_i;
-    output fabric_spw1_apb_slv_pslverr_o;
-    input [30:0] fabric_spw1_apb_slv_pwdata_i;
-    input fabric_spw1_apb_slv_pwrite_i;
-    input fabric_spw1_clk_i;
-    input fabric_spw1_clk_tx_i;
-    input fabric_spw1_rst_n_i;
-    output [8:0] fabric_spw1_rx_fifo_data_o;
-    output fabric_spw1_rx_fifo_empty_o;
-    input fabric_spw1_rx_fifo_read_i;
-    input fabric_spw1_tick_ctm_i;
-    output fabric_spw1_tick_ctm_o;
-    input [8:0] fabric_spw1_tx_fifo_data_i;
-    output fabric_spw1_tx_fifo_full_o;
-    input fabric_spw1_tx_fifo_write_i;
-    output fabric_spw1_user_shared_o;
-    output fabric_status_cold_start_o;
-    input [2:0] fabric_thsens_arst_tmr_n_i;
-    input [7:0] fabric_thsens_clk_div_ratio_i;
-    input fabric_thsens_clk_i;
-    output [26:0] fabric_thsens_fm_config_r_o;
-    input [26:0] fabric_thsens_fm_config_w_i;
-    input fabric_thsens_fm_config_wen_i;
-    output [13:0] fabric_thsens_fm_data_o;
-    input fabric_thsens_fm_enable_i;
-    output [31:0] fabric_thsens_fm_mode_r_o;
-    input [31:0] fabric_thsens_fm_mode_w_i;
-    input fabric_thsens_fm_mode_wen_i;
-    output fabric_thsens_fm_overflow_o;
-    output fabric_thsens_fm_valid_o;
-    output [26:0] fabric_thsens_otp_config_o;
-    input fabric_thsens_tst_scanenable_i;
-    input fabric_thsens_tst_scanin1_i;
-    input fabric_thsens_tst_scanin2_i;
-    output fabric_thsens_tst_scanout1_o;
-    output fabric_thsens_tst_scanout2_o;
-    input fabric_user_clk_i;
-    input [31:0] fabric_user_data_i;
-    output [31:0] fabric_user_data_o;
-    output fabric_user_read_cycle_o;
-    output fabric_user_write_cycle_o;
-    parameter bsm_config = 0;
-endmodule
-
-(* blackbox *)
-module NX_SERVICE_IF_U_WRAP(fabric_otp_user_clk_i, fabric_otp_user_bistmode_i, fabric_otp_user_disturbcheck_i, fabric_otp_user_eccbypass_i, fabric_otp_user_pdn_i, fabric_otp_user_prog_i, fabric_otp_user_rbact1_i, fabric_otp_user_rbact2_i, fabric_otp_user_read_i, fabric_otp_user_redbypass_i, fabric_otp_user_suppadd_i, fabric_otp_user_tm_i, fabric_otp_user_tst_scanenable_i, fabric_otp_user_wordlock_i, fabric_otp_user_clock_frequency_range_i, fabric_otp_user_ack_o, fabric_otp_user_bbad_o, fabric_otp_user_bend1_o, fabric_otp_user_bend2_o, fabric_otp_user_calibrated_o, fabric_otp_user_ded_o
-, fabric_otp_user_disturbed_o, fabric_otp_user_locked_o, fabric_otp_user_progfail_o, fabric_otp_user_pwok_o, fabric_otp_user_sec_o, fabric_clk_bsm_o, fabric_clk_otp_mux_i, fabric_clk_otp_o, fabric_clk_user0_o, fabric_clk_user1_o, fabric_user_clk_i, fabric_user_write_cycle_o, fabric_user_read_cycle_o, fabric_cfg_fabric_user_flag_o, fabric_cfg_fabric_user_enable_o, fabric_parusr_clk_i, fabric_parusr_enable_i, fabric_parusr_cs_i, fabric_parusr_data_val_o, fabric_jtag_tck_o, fabric_jtag_trst_n_o
-, fabric_jtag_tms_o, fabric_jtag_tdi_o, fabric_jtag_usr1_o, fabric_jtag_usr2_o, fabric_jtag_tdo_usr1_i, fabric_jtag_tdo_usr2_i, fabric_status_cold_start_o, fabric_flag_trigger0_o, fabric_flag_trigger1_o, fabric_thsens_clk_i, fabric_thsens_fm_enable_i, fabric_thsens_fm_mode_wen_i, fabric_thsens_fm_config_wen_i, fabric_thsens_fm_valid_o, fabric_thsens_fm_overflow_o, fabric_spi_clk_i2, fabric_spi_sck_i2, fabric_spi_clk_i0, fabric_spi_sck_i0, fabric_spi_clk_i1, fabric_spi_sck_i1
-, fabric_spw0_clk_i, fabric_spw0_clk_tx_i, fabric_spw0_rst_n_i, fabric_spw0_user_shared_o, fabric_spw0_tx_fifo_write_i, fabric_spw0_tx_fifo_full_o, fabric_spw0_rx_fifo_read_i, fabric_spw0_rx_fifo_empty_o, fabric_spw0_tick_ctm_i, fabric_spw0_tick_ctm_o, fabric_spw0_apb_slv_psel_i, fabric_spw0_apb_slv_penable_i, fabric_spw0_apb_slv_pwrite_i, fabric_spw0_apb_slv_pready_o, fabric_spw0_apb_slv_pslverr_o, fabric_spw1_clk_i, fabric_spw1_clk_tx_i, fabric_spw1_rst_n_i, fabric_spw1_user_shared_o, fabric_spw1_tx_fifo_write_i, fabric_spw1_tx_fifo_full_o
-, fabric_spw1_rx_fifo_read_i, fabric_spw1_rx_fifo_empty_o, fabric_spw1_tick_ctm_i, fabric_spw1_tick_ctm_o, fabric_spw1_apb_slv_psel_i, fabric_spw1_apb_slv_penable_i, fabric_spw1_apb_slv_pwrite_i, fabric_spw1_apb_slv_pready_o, fabric_spw1_apb_slv_pslverr_o, fabric_otp_user_add_i, fabric_otp_user_din_i, fabric_otp_user_prgwidth_i, fabric_otp_user_tst_scanin_i, fabric_otp_user_bist1fail_o, fabric_otp_user_bist2fail_o, fabric_otp_user_dout_o, fabric_otp_user_flagstate_o, fabric_otp_user_startword_o, fabric_otp_user_tst_scanout_o, fabric_otp_user_wlromout_o, fabric_io_in_i
-, fabric_io_oe_i, fabric_io_out_o, fabric_user_data_i, fabric_user_data_o, fabric_parusr_type_i, fabric_parusr_data_i, fabric_parusr_data_o, fabric_flag_ready_TMR_o, fabric_enable_TMR_i, fabric_lowskew_i, fabric_lowskew_o, fabric_spare_i, fabric_spare_o, fabric_thsens_arst_tmr_n_i, fabric_thsens_fm_mode_w_i, fabric_thsens_fm_config_w_i, fabric_thsens_fm_data_o, fabric_thsens_fm_mode_r_o, fabric_thsens_fm_config_r_o, fabric_thsens_clk_div_ratio_i, fabric_thsens_otp_config_o
-, fabric_spi_needed_i, fabric_spi_bsm_release_o, fabric_spi_arst_tmr_n_i, fabric_spi_fifo_arst_tmr_n_i, fabric_spi_cpol_i, fabric_spi_cpha_i, fabric_spi_loopback_i, fabric_spi_lsb_first_i, fabric_spi_cs_setuptime_i, fabric_spi_cs_holdtime_i, fabric_spi_cs_offtime_i, fabric_spi_vcc_enable_i, fabric_spi_powerdown_cycle_i, fabric_spi_powerup_cycle_i, fabric_spi_legacy_enable_i, fabric_spi_legacy_master_i, fabric_spi_data_in_unlimited_i, fabric_spi_enable_i, fabric_spi_rst_n_i, fabric_spi_init_done_o, fabric_spi_busy_o
-, fabric_spi_vcc_used_o, fabric_spi_error_sel_o, fabric_spi_error_loopback_o, fabric_spi_error_mode_o, fabric_spi_error_endianness_o, fabric_spi_cmd_push_i, fabric_spi_cmd_full_o, fabric_spi_cmd_type_i, fabric_spi_cmd_mode_i, fabric_spi_cmd_bytes_i, fabric_spi_mosi_push_i, fabric_spi_mosi_full_o, fabric_spi_mosi_data_i, fabric_spi_mosi_data_inv_i, fabric_spi_miso_pop_i, fabric_spi_miso_empty_o, fabric_spi_miso_data_o, fabric_spi_miso_data_inv_o, fabric_spw0_tx_fifo_data_i, fabric_spw0_rx_fifo_data_o, fabric_spw0_apb_slv_paddr_i
-, fabric_spw0_apb_slv_pwdata_i, fabric_spw0_apb_slv_prdata_o, fabric_spw1_tx_fifo_data_i, fabric_spw1_rx_fifo_data_o, fabric_spw1_apb_slv_paddr_i, fabric_spw1_apb_slv_pwdata_i, fabric_spw1_apb_slv_prdata_o);
-    output fabric_cfg_fabric_user_enable_o;
-    output fabric_cfg_fabric_user_flag_o;
-    output fabric_clk_bsm_o;
-    input fabric_clk_otp_mux_i;
-    output fabric_clk_otp_o;
-    output fabric_clk_user0_o;
-    output fabric_clk_user1_o;
-    input [2:0] fabric_enable_TMR_i;
-    output [2:0] fabric_flag_ready_TMR_o;
-    output fabric_flag_trigger0_o;
-    output fabric_flag_trigger1_o;
-    input [34:0] fabric_io_in_i;
-    input [34:0] fabric_io_oe_i;
-    output [34:0] fabric_io_out_o;
-    output fabric_jtag_tck_o;
-    output fabric_jtag_tdi_o;
-    input fabric_jtag_tdo_usr1_i;
-    input fabric_jtag_tdo_usr2_i;
-    output fabric_jtag_tms_o;
-    output fabric_jtag_trst_n_o;
-    output fabric_jtag_usr1_o;
-    output fabric_jtag_usr2_o;
-    input [39:0] fabric_lowskew_i;
-    output [5:0] fabric_lowskew_o;
-    output fabric_otp_user_ack_o;
-    input [6:0] fabric_otp_user_add_i;
-    output fabric_otp_user_bbad_o;
-    output fabric_otp_user_bend1_o;
-    output fabric_otp_user_bend2_o;
-    output [7:0] fabric_otp_user_bist1fail_o;
-    output [6:0] fabric_otp_user_bist2fail_o;
-    input fabric_otp_user_bistmode_i;
-    output fabric_otp_user_calibrated_o;
-    input fabric_otp_user_clk_i;
-    input fabric_otp_user_clock_frequency_range_i;
-    output fabric_otp_user_ded_o;
-    input [38:0] fabric_otp_user_din_i;
-    input fabric_otp_user_disturbcheck_i;
-    output fabric_otp_user_disturbed_o;
-    output [40:0] fabric_otp_user_dout_o;
-    input fabric_otp_user_eccbypass_i;
-    output [3:0] fabric_otp_user_flagstate_o;
-    output fabric_otp_user_locked_o;
-    input fabric_otp_user_pdn_i;
-    input [2:0] fabric_otp_user_prgwidth_i;
-    input fabric_otp_user_prog_i;
-    output fabric_otp_user_progfail_o;
-    output fabric_otp_user_pwok_o;
-    input fabric_otp_user_rbact1_i;
-    input fabric_otp_user_rbact2_i;
-    input fabric_otp_user_read_i;
-    input fabric_otp_user_redbypass_i;
-    output fabric_otp_user_sec_o;
-    output [15:0] fabric_otp_user_startword_o;
-    input fabric_otp_user_suppadd_i;
-    input fabric_otp_user_tm_i;
-    input fabric_otp_user_tst_scanenable_i;
-    input [4:0] fabric_otp_user_tst_scanin_i;
-    output [4:0] fabric_otp_user_tst_scanout_o;
-    output [9:0] fabric_otp_user_wlromout_o;
-    input fabric_otp_user_wordlock_i;
-    input fabric_parusr_clk_i;
-    input fabric_parusr_cs_i;
-    input [15:0] fabric_parusr_data_i;
-    output [15:0] fabric_parusr_data_o;
-    output fabric_parusr_data_val_o;
-    input fabric_parusr_enable_i;
-    input [1:0] fabric_parusr_type_i;
-    input [127:0] fabric_spare_i;
-    output [127:0] fabric_spare_o;
-    input [8:0] fabric_spi_arst_tmr_n_i;
-    output [2:0] fabric_spi_bsm_release_o;
-    output [2:0] fabric_spi_busy_o;
-    input fabric_spi_clk_i0;
-    input fabric_spi_clk_i1;
-    input fabric_spi_clk_i2;
-    input [5:0] fabric_spi_cmd_bytes_i;
-    output [2:0] fabric_spi_cmd_full_o;
-    input [5:0] fabric_spi_cmd_mode_i;
-    input [2:0] fabric_spi_cmd_push_i;
-    input [5:0] fabric_spi_cmd_type_i;
-    input [2:0] fabric_spi_cpha_i;
-    input [2:0] fabric_spi_cpol_i;
-    input [11:0] fabric_spi_cs_holdtime_i;
-    input [11:0] fabric_spi_cs_offtime_i;
-    input [11:0] fabric_spi_cs_setuptime_i;
-    input [2:0] fabric_spi_data_in_unlimited_i;
-    input [2:0] fabric_spi_enable_i;
-    output [2:0] fabric_spi_error_endianness_o;
-    output [2:0] fabric_spi_error_loopback_o;
-    output [2:0] fabric_spi_error_mode_o;
-    output [2:0] fabric_spi_error_sel_o;
-    input [8:0] fabric_spi_fifo_arst_tmr_n_i;
-    output [2:0] fabric_spi_init_done_o;
-    input [2:0] fabric_spi_legacy_enable_i;
-    input [2:0] fabric_spi_legacy_master_i;
-    input [2:0] fabric_spi_loopback_i;
-    input [2:0] fabric_spi_lsb_first_i;
-    output [2:0] fabric_spi_miso_data_inv_o;
-    output [23:0] fabric_spi_miso_data_o;
-    output [2:0] fabric_spi_miso_empty_o;
-    input [2:0] fabric_spi_miso_pop_i;
-    input [23:0] fabric_spi_mosi_data_i;
-    input [2:0] fabric_spi_mosi_data_inv_i;
-    output [2:0] fabric_spi_mosi_full_o;
-    input [2:0] fabric_spi_mosi_push_i;
-    input [2:0] fabric_spi_needed_i;
-    input [47:0] fabric_spi_powerdown_cycle_i;
-    input [47:0] fabric_spi_powerup_cycle_i;
-    input [2:0] fabric_spi_rst_n_i;
-    input fabric_spi_sck_i0;
-    input fabric_spi_sck_i1;
-    input fabric_spi_sck_i2;
-    input [2:0] fabric_spi_vcc_enable_i;
-    output [2:0] fabric_spi_vcc_used_o;
-    input [6:2] fabric_spw0_apb_slv_paddr_i;
-    input fabric_spw0_apb_slv_penable_i;
-    output [30:0] fabric_spw0_apb_slv_prdata_o;
-    output fabric_spw0_apb_slv_pready_o;
-    input fabric_spw0_apb_slv_psel_i;
-    output fabric_spw0_apb_slv_pslverr_o;
-    input [30:0] fabric_spw0_apb_slv_pwdata_i;
-    input fabric_spw0_apb_slv_pwrite_i;
-    input fabric_spw0_clk_i;
-    input fabric_spw0_clk_tx_i;
-    input fabric_spw0_rst_n_i;
-    output [8:0] fabric_spw0_rx_fifo_data_o;
-    output fabric_spw0_rx_fifo_empty_o;
-    input fabric_spw0_rx_fifo_read_i;
-    input fabric_spw0_tick_ctm_i;
-    output fabric_spw0_tick_ctm_o;
-    input [8:0] fabric_spw0_tx_fifo_data_i;
-    output fabric_spw0_tx_fifo_full_o;
-    input fabric_spw0_tx_fifo_write_i;
-    output fabric_spw0_user_shared_o;
-    input [6:2] fabric_spw1_apb_slv_paddr_i;
-    input fabric_spw1_apb_slv_penable_i;
-    output [30:0] fabric_spw1_apb_slv_prdata_o;
-    output fabric_spw1_apb_slv_pready_o;
-    input fabric_spw1_apb_slv_psel_i;
-    output fabric_spw1_apb_slv_pslverr_o;
-    input [30:0] fabric_spw1_apb_slv_pwdata_i;
-    input fabric_spw1_apb_slv_pwrite_i;
-    input fabric_spw1_clk_i;
-    input fabric_spw1_clk_tx_i;
-    input fabric_spw1_rst_n_i;
-    output [8:0] fabric_spw1_rx_fifo_data_o;
-    output fabric_spw1_rx_fifo_empty_o;
-    input fabric_spw1_rx_fifo_read_i;
-    input fabric_spw1_tick_ctm_i;
-    output fabric_spw1_tick_ctm_o;
-    input [8:0] fabric_spw1_tx_fifo_data_i;
-    output fabric_spw1_tx_fifo_full_o;
-    input fabric_spw1_tx_fifo_write_i;
-    output fabric_spw1_user_shared_o;
-    output fabric_status_cold_start_o;
-    input [2:0] fabric_thsens_arst_tmr_n_i;
-    input [7:0] fabric_thsens_clk_div_ratio_i;
-    input fabric_thsens_clk_i;
-    output [26:0] fabric_thsens_fm_config_r_o;
-    input [26:0] fabric_thsens_fm_config_w_i;
-    input fabric_thsens_fm_config_wen_i;
-    output [13:0] fabric_thsens_fm_data_o;
-    input fabric_thsens_fm_enable_i;
-    output [31:0] fabric_thsens_fm_mode_r_o;
-    input [31:0] fabric_thsens_fm_mode_w_i;
-    input fabric_thsens_fm_mode_wen_i;
-    output fabric_thsens_fm_overflow_o;
-    output fabric_thsens_fm_valid_o;
-    output [26:0] fabric_thsens_otp_config_o;
-    input fabric_user_clk_i;
-    input [31:0] fabric_user_data_i;
-    output [31:0] fabric_user_data_o;
-    output fabric_user_read_cycle_o;
-    output fabric_user_write_cycle_o;
-    parameter bsm_config = 0;
-endmodule
-
-(* blackbox *)
-module NX_SERVICE_U(fabric_otp_user_tst_scanenable_i, fabric_otp_cfg_loader_read_en_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_scanenable_i, fabric_otp_user_din_i1, fabric_otp_user_din_i2, fabric_otp_user_din_i3, fabric_otp_user_din_i4, fabric_otp_user_din_i5, fabric_otp_user_din_i6, fabric_otp_user_din_i7, fabric_otp_user_din_i8, fabric_otp_user_din_i9, fabric_otp_user_din_i10, fabric_otp_user_din_i11, fabric_otp_user_din_i12, fabric_otp_user_din_i13, fabric_otp_user_din_i14, fabric_otp_user_din_i15, fabric_otp_user_din_i16, fabric_otp_user_din_i17
-, fabric_otp_user_din_i18, fabric_otp_user_din_i19, fabric_otp_user_din_i20, fabric_otp_user_din_i21, fabric_otp_user_din_i22, fabric_otp_user_din_i23, fabric_otp_user_din_i24, fabric_otp_user_din_i25, fabric_otp_user_din_i26, fabric_otp_user_din_i27, fabric_otp_user_din_i28, fabric_otp_user_din_i29, fabric_otp_user_din_i30, fabric_otp_user_din_i31, fabric_otp_user_din_i32, fabric_otp_user_din_i33, fabric_otp_user_din_i34, fabric_otp_user_din_i35, fabric_otp_user_din_i36, fabric_otp_user_din_i37, fabric_otp_user_din_i38
-, fabric_otp_user_din_i39, fabric_mrepair_fuse_prgwidth_i1, fabric_mrepair_fuse_prgwidth_i2, fabric_mrepair_fuse_prgwidth_i3, fabric_otp_apb_wdata_i1, fabric_otp_apb_wdata_i2, fabric_otp_apb_wdata_i3, fabric_otp_apb_wdata_i4, fabric_otp_apb_wdata_i5, fabric_otp_apb_wdata_i6, fabric_otp_apb_wdata_i7, fabric_otp_apb_wdata_i8, fabric_otp_apb_wdata_i9, fabric_otp_apb_wdata_i10, fabric_otp_apb_wdata_i11, fabric_otp_apb_wdata_i12, fabric_otp_apb_wdata_i13, fabric_otp_apb_wdata_i14, fabric_otp_apb_wdata_i15, fabric_otp_apb_wdata_i16, fabric_otp_apb_wdata_i17
-, fabric_otp_apb_wdata_i18, fabric_otp_apb_wdata_i19, fabric_otp_apb_wdata_i20, fabric_otp_apb_wdata_i21, fabric_otp_apb_wdata_i22, fabric_otp_apb_wdata_i23, fabric_otp_apb_wdata_i24, fabric_otp_apb_wdata_i25, fabric_otp_apb_wdata_i26, fabric_otp_apb_wdata_i27, fabric_otp_apb_wdata_i28, fabric_otp_apb_wdata_i29, fabric_otp_apb_wdata_i30, fabric_otp_apb_wdata_i31, fabric_otp_apb_wdata_i32, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_user_disturbcheck_i, fabric_mrepair_fuse_read_i, fabric_otp_user_rbact2_i, fabric_mrepair_fuse_eccbypass_i, fabric_otp_user_bistmode_i
-, fabric_otp_user_add_i1, fabric_otp_user_add_i2, fabric_otp_user_add_i3, fabric_otp_user_add_i4, fabric_otp_user_add_i5, fabric_otp_user_add_i6, fabric_otp_user_add_i7, fabric_otp_user_tm_i, fabric_otp_rst_i, fabric_mrepair_fuse_disturbchecked_i, fabric_otp_user_rbact1_i, fabric_mrepair_fuse_tst_scanin_i1, fabric_mrepair_fuse_tst_scanin_i2, fabric_mrepair_fuse_tst_scanin_i3, fabric_mrepair_fuse_tst_scanin_i4, fabric_mrepair_fuse_tst_scanin_i5, fabric_parusr_type_i1, fabric_parusr_type_i2, fabric_mrepair_fuse_redbypass_i, fabric_otp_user_eccbypass_i, fabric_otp_user_redbypass_i
-, fabric_mrepair_mode_i1, fabric_mrepair_mode_i2, fabric_mrepair_mode_i3, fabric_mrepair_mode_i4, fabric_parusr_cs_i, fabric_sif_reg_en_i1, fabric_sif_reg_en_i2, fabric_sif_reg_en_i3, fabric_sif_reg_en_i4, fabric_sif_reg_en_i5, fabric_sif_reg_en_i6, fabric_sif_reg_en_i7, fabric_sif_reg_en_i8, fabric_sif_reg_en_i9, fabric_sif_reg_en_i10, fabric_sif_reg_en_i11, fabric_sif_reg_en_i12, fabric_sif_reg_en_i13, fabric_sif_reg_en_i14, fabric_sif_reg_en_i15, fabric_sif_reg_en_i16
-, fabric_sif_reg_en_i17, fabric_sif_reg_en_i18, fabric_sif_reg_en_i19, fabric_sif_reg_en_i20, fabric_sif_reg_en_i21, fabric_sif_reg_en_i22, fabric_sif_reg_en_i23, fabric_sif_reg_en_i24, fabric_sif_reg_en_i25, fabric_sif_reg_en_i26, fabric_sif_reg_en_i27, fabric_sif_reg_en_i28, fabric_sif_reg_en_i29, fabric_sif_reg_en_i30, fabric_sif_reg_en_i31, fabric_sif_reg_en_i32, fabric_sif_reg_en_i33, fabric_sif_reg_en_i34, fabric_sif_reg_en_i35, fabric_sif_reg_en_i36, fabric_sif_reg_en_i37
-, fabric_sif_reg_en_i38, fabric_sif_reg_en_i39, fabric_sif_reg_en_i40, fabric_sif_reg_en_i41, fabric_sif_reg_en_i42, fabric_sif_reg_en_i43, fabric_sif_reg_en_i44, fabric_sif_reg_en_i45, fabric_sif_reg_en_i46, fabric_sif_reg_en_i47, fabric_sif_reg_en_i48, fabric_sif_reg_en_i49, fabric_sif_reg_en_i50, fabric_sif_reg_en_i51, fabric_sif_reg_en_i52, fabric_sif_reg_en_i53, fabric_sif_reg_en_i54, fabric_sif_reg_en_i55, fabric_sif_reg_en_i56, fabric_sif_reg_en_i57, fabric_sif_reg_en_i58
-, fabric_sif_reg_en_i59, fabric_sif_reg_en_i60, fabric_sif_reg_en_i61, fabric_sif_reg_en_i62, fabric_sif_reg_en_i63, fabric_sif_reg_en_i64, fabric_sif_reg_en_i65, fabric_sif_reg_en_i66, fabric_sif_reg_en_i67, fabric_sif_reg_en_i68, fabric_sif_reg_en_i69, fabric_sif_reg_en_i70, fabric_sif_reg_en_i71, fabric_sif_reg_en_i72, fabric_sif_reg_en_i73, fabric_sif_reg_en_i74, fabric_sif_reg_en_i75, fabric_sif_reg_en_i76, fabric_sif_reg_en_i77, fabric_sif_reg_en_i78, fabric_sif_reg_en_i79
-, fabric_sif_reg_en_i80, fabric_sif_reg_en_i81, fabric_sif_reg_en_i82, fabric_sif_reg_en_i83, fabric_sif_reg_en_i84, fabric_sif_reg_en_i85, fabric_sif_reg_en_i86, fabric_sif_reg_en_i87, fabric_sif_reg_en_i88, fabric_sif_reg_en_i89, fabric_sif_reg_en_i90, fabric_sif_reg_en_i91, fabric_sif_reg_en_i92, fabric_sif_reg_en_i93, fabric_sif_reg_en_i94, fabric_sif_reg_en_i95, fabric_sif_reg_en_i96, fabric_sif_reg_en_i97, fabric_sif_reg_en_i98, fabric_sif_reg_en_i99, fabric_sif_reg_en_i100
-, fabric_sif_reg_en_i101, fabric_sif_reg_en_i102, fabric_sif_reg_en_i103, fabric_sif_reg_en_i104, fabric_sif_reg_en_i105, fabric_sif_reg_en_i106, fabric_sif_reg_en_i107, fabric_sif_reg_en_i108, fabric_sif_reg_en_i109, fabric_sif_reg_en_i110, fabric_sif_reg_en_i111, fabric_sif_reg_en_i112, fabric_sif_reg_en_i113, fabric_sif_reg_en_i114, fabric_sif_reg_en_i115, fabric_sif_reg_en_i116, fabric_sif_reg_en_i117, fabric_sif_reg_en_i118, fabric_sif_reg_en_i119, fabric_sif_reg_en_i120, fabric_mrepair_fuse_rbact2_i
-, fabric_data_from_system_i, fabric_data_from_bist_i1, fabric_data_from_bist_i2, fabric_data_from_bist_i3, fabric_data_from_bist_i4, fabric_data_from_bist_i5, fabric_data_from_bist_i6, fabric_data_from_bist_i7, fabric_data_from_bist_i8, fabric_data_from_bist_i9, fabric_data_from_bist_i10, fabric_data_from_bist_i11, fabric_data_from_bist_i12, fabric_data_from_bist_i13, fabric_data_from_bist_i14, fabric_data_from_bist_i15, fabric_data_from_bist_i16, fabric_data_from_bist_i17, fabric_data_from_bist_i18, fabric_data_from_bist_i19, fabric_data_from_bist_i20
-, fabric_data_from_bist_i21, fabric_data_from_bist_i22, fabric_data_from_bist_i23, fabric_data_from_bist_i24, fabric_otp_apb_enable_i, fabric_mrepair_fuse_tm_i, fabric_otp_security_rbact2_i, fabric_otp_security_rbact1_i, fabric_shift_en_i1, fabric_shift_en_i2, fabric_shift_en_i3, fabric_shift_en_i4, fabric_shift_en_i5, fabric_shift_en_i6, fabric_shift_en_i7, fabric_shift_en_i8, fabric_shift_en_i9, fabric_shift_en_i10, fabric_shift_en_i11, fabric_shift_en_i12, fabric_shift_en_i13
-, fabric_shift_en_i14, fabric_shift_en_i15, fabric_shift_en_i16, fabric_shift_en_i17, fabric_shift_en_i18, fabric_shift_en_i19, fabric_shift_en_i20, fabric_shift_en_i21, fabric_shift_en_i22, fabric_shift_en_i23, fabric_shift_en_i24, fabric_otp_cfg_loader_write_en_i, fabric_user_data_i1, fabric_user_data_i2, fabric_user_data_i3, fabric_user_data_i4, fabric_user_data_i5, fabric_user_data_i6, fabric_user_data_i7, fabric_user_data_i8, fabric_user_data_i9
-, fabric_user_data_i10, fabric_user_data_i11, fabric_user_data_i12, fabric_user_data_i13, fabric_user_data_i14, fabric_user_data_i15, fabric_user_data_i16, fabric_user_data_i17, fabric_user_data_i18, fabric_user_data_i19, fabric_user_data_i20, fabric_user_data_i21, fabric_user_data_i22, fabric_user_data_i23, fabric_user_data_i24, fabric_user_data_i25, fabric_user_data_i26, fabric_user_data_i27, fabric_user_data_i28, fabric_user_data_i29, fabric_user_data_i30
-, fabric_user_data_i31, fabric_user_data_i32, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_prog_i, fabric_otp_user_wordlock_i, fabric_ahb_direct_data_i1, fabric_ahb_direct_data_i2, fabric_ahb_direct_data_i3, fabric_ahb_direct_data_i4, fabric_ahb_direct_data_i5, fabric_ahb_direct_data_i6, fabric_ahb_direct_data_i7, fabric_ahb_direct_data_i8, fabric_ahb_direct_data_i9, fabric_ahb_direct_data_i10, fabric_ahb_direct_data_i11, fabric_ahb_direct_data_i12, fabric_ahb_direct_data_i13, fabric_ahb_direct_data_i14, fabric_ahb_direct_data_i15, fabric_ahb_direct_data_i16
-, fabric_ahb_direct_data_i17, fabric_ahb_direct_data_i18, fabric_ahb_direct_data_i19, fabric_ahb_direct_data_i20, fabric_ahb_direct_data_i21, fabric_ahb_direct_data_i22, fabric_ahb_direct_data_i23, fabric_ahb_direct_data_i24, fabric_ahb_direct_data_i25, fabric_ahb_direct_data_i26, fabric_ahb_direct_data_i27, fabric_ahb_direct_data_i28, fabric_ahb_direct_data_i29, fabric_ahb_direct_data_i30, fabric_ahb_direct_data_i31, fabric_ahb_direct_data_i32, fabric_otp_user_prog_i, fabric_pd_active_i1, fabric_pd_active_i2, fabric_pd_active_i3, fabric_pd_active_i4
-, fabric_pd_active_i5, fabric_pd_active_i6, fabric_pd_active_i7, fabric_pd_active_i8, fabric_pd_active_i9, fabric_pd_active_i10, fabric_pd_active_i11, fabric_pd_active_i12, fabric_pd_active_i13, fabric_pd_active_i14, fabric_pd_active_i15, fabric_pd_active_i16, fabric_pd_active_i17, fabric_pd_active_i18, fabric_pd_active_i19, fabric_pd_active_i20, fabric_pd_active_i21, fabric_pd_active_i22, fabric_pd_active_i23, fabric_pd_active_i24, fabric_otp_user_suppadd_i
-, fabric_mrepair_fuse_pdn_i, fabric_otp_security_scanin_i1, fabric_otp_security_scanin_i2, fabric_otp_security_scanin_i3, fabric_otp_security_scanin_i4, fabric_otp_security_scanin_i5, fabric_end_encoding_i, fabric_jtag_tdo_usr2_i, fabric_mrepair_fuse_wordlock_i, fabric_otp_user_prgwidth_i1, fabric_otp_user_prgwidth_i2, fabric_otp_user_prgwidth_i3, fabric_otp_user_read_i, fabric_mrepair_fuse_add_i1, fabric_mrepair_fuse_add_i2, fabric_mrepair_fuse_add_i3, fabric_mrepair_fuse_add_i4, fabric_mrepair_fuse_add_i5, fabric_mrepair_fuse_add_i6, fabric_mrepair_fuse_add_i7, fabric_mrepair_fuse_bistmode_i
-, fabric_jtag_tdo_usr1_i, fabric_otp_cfg_clk_fab_en_i, fabric_io_in_i1, fabric_io_in_i2, fabric_io_in_i3, fabric_io_in_i4, fabric_io_in_i5, fabric_io_in_i6, fabric_io_in_i7, fabric_io_in_i8, fabric_io_in_i9, fabric_io_in_i10, fabric_io_in_i11, fabric_io_in_i12, fabric_io_in_i13, fabric_io_in_i14, fabric_io_in_i15, fabric_io_in_i16, fabric_io_in_i17, fabric_io_in_i18, fabric_io_in_i19
-, fabric_io_in_i20, fabric_io_in_i21, fabric_io_in_i22, fabric_io_in_i23, fabric_io_in_i24, fabric_io_in_i25, fabric_sif_load_en_i1, fabric_sif_load_en_i2, fabric_sif_load_en_i3, fabric_sif_load_en_i4, fabric_sif_load_en_i5, fabric_sif_load_en_i6, fabric_sif_load_en_i7, fabric_sif_load_en_i8, fabric_sif_load_en_i9, fabric_sif_load_en_i10, fabric_sif_load_en_i11, fabric_sif_load_en_i12, fabric_sif_load_en_i13, fabric_sif_load_en_i14, fabric_sif_load_en_i15
-, fabric_sif_load_en_i16, fabric_sif_load_en_i17, fabric_sif_load_en_i18, fabric_sif_load_en_i19, fabric_sif_load_en_i20, fabric_sif_load_en_i21, fabric_sif_load_en_i22, fabric_sif_load_en_i23, fabric_sif_load_en_i24, fabric_mrepair_fuse_din_i1, fabric_mrepair_fuse_din_i2, fabric_mrepair_fuse_din_i3, fabric_mrepair_fuse_din_i4, fabric_mrepair_fuse_din_i5, fabric_mrepair_fuse_din_i6, fabric_mrepair_fuse_din_i7, fabric_mrepair_fuse_din_i8, fabric_mrepair_fuse_din_i9, fabric_mrepair_fuse_din_i10, fabric_mrepair_fuse_din_i11, fabric_mrepair_fuse_din_i12
-, fabric_mrepair_fuse_din_i13, fabric_mrepair_fuse_din_i14, fabric_mrepair_fuse_din_i15, fabric_mrepair_fuse_din_i16, fabric_mrepair_fuse_din_i17, fabric_mrepair_fuse_din_i18, fabric_mrepair_fuse_din_i19, fabric_mrepair_fuse_din_i20, fabric_mrepair_fuse_din_i21, fabric_mrepair_fuse_din_i22, fabric_mrepair_fuse_din_i23, fabric_mrepair_fuse_din_i24, fabric_mrepair_fuse_din_i25, fabric_mrepair_fuse_din_i26, fabric_mrepair_fuse_din_i27, fabric_mrepair_fuse_din_i28, fabric_mrepair_fuse_din_i29, fabric_mrepair_fuse_din_i30, fabric_mrepair_fuse_din_i31, fabric_mrepair_fuse_din_i32, fabric_mrepair_fuse_din_i33
-, fabric_mrepair_fuse_din_i34, fabric_mrepair_fuse_din_i35, fabric_mrepair_fuse_din_i36, fabric_mrepair_fuse_din_i37, fabric_mrepair_fuse_din_i38, fabric_mrepair_fuse_din_i39, fabric_otp_apb_addr_i1, fabric_otp_apb_addr_i2, fabric_otp_apb_addr_i3, fabric_otp_apb_addr_i4, fabric_otp_apb_addr_i5, fabric_otp_apb_addr_i6, fabric_otp_apb_addr_i7, fabric_otp_apb_addr_i8, fabric_otp_apb_addr_i9, fabric_otp_apb_addr_i10, fabric_otp_apb_addr_i11, fabric_otp_apb_addr_i12, fabric_otp_apb_addr_i13, fabric_otp_apb_addr_i14, fabric_otp_apb_addr_i15
-, fabric_otp_apb_addr_i16, fabric_otp_apb_addr_i17, fabric_otp_apb_addr_i18, fabric_otp_apb_addr_i19, fabric_otp_apb_addr_i20, fabric_otp_apb_addr_i21, fabric_otp_apb_addr_i22, fabric_otp_apb_addr_i23, fabric_otp_apb_addr_i24, fabric_otp_apb_addr_i25, fabric_otp_apb_addr_i26, fabric_otp_apb_addr_i27, fabric_otp_apb_addr_i28, fabric_otp_apb_addr_i29, fabric_otp_apb_addr_i30, fabric_otp_apb_addr_i31, fabric_otp_apb_addr_i32, fabric_otp_apb_sel_i, fabric_mrepair_fuse_rbact1_i, fabric_otp_cfg_fabric_apb_en_i, fabric_data_shift_en_i
-, fabric_lowskew_i21, fabric_direct_data_i1, fabric_direct_data_i2, fabric_direct_data_i3, fabric_direct_data_i4, fabric_direct_data_i5, fabric_direct_data_i6, fabric_direct_data_i7, fabric_direct_data_i8, fabric_direct_data_i9, fabric_direct_data_i10, fabric_direct_data_i11, fabric_direct_data_i12, fabric_direct_data_i13, fabric_direct_data_i14, fabric_direct_data_i15, fabric_direct_data_i16, fabric_direct_data_i17, fabric_direct_data_i18, fabric_direct_data_i19, fabric_direct_data_i20
-, fabric_direct_data_i21, fabric_direct_data_i22, fabric_direct_data_i23, fabric_direct_data_i24, fabric_direct_data_i25, fabric_direct_data_i26, fabric_direct_data_i27, fabric_direct_data_i28, fabric_direct_data_i29, fabric_direct_data_i30, fabric_direct_data_i31, fabric_direct_data_i32, fabric_otp_user_pdn_i, fabric_io_oe_i1, fabric_io_oe_i2, fabric_io_oe_i3, fabric_io_oe_i4, fabric_io_oe_i5, fabric_io_oe_i6, fabric_io_oe_i7, fabric_io_oe_i8
-, fabric_io_oe_i9, fabric_io_oe_i10, fabric_io_oe_i11, fabric_io_oe_i12, fabric_io_oe_i13, fabric_io_oe_i14, fabric_io_oe_i15, fabric_io_oe_i16, fabric_io_oe_i17, fabric_io_oe_i18, fabric_io_oe_i19, fabric_io_oe_i20, fabric_io_oe_i21, fabric_io_oe_i22, fabric_io_oe_i23, fabric_io_oe_i24, fabric_io_oe_i25, fabric_parusr_data_i1, fabric_parusr_data_i2, fabric_parusr_data_i3, fabric_parusr_data_i4
-, fabric_parusr_data_i5, fabric_parusr_data_i6, fabric_parusr_data_i7, fabric_parusr_data_i8, fabric_parusr_data_i9, fabric_parusr_data_i10, fabric_parusr_data_i11, fabric_parusr_data_i12, fabric_parusr_data_i13, fabric_parusr_data_i14, fabric_parusr_data_i15, fabric_parusr_data_i16, fabric_otp_apb_write_i, fabric_otp_security_testmode_i, fabric_system_data_to_mem_bist_i1, fabric_system_data_to_mem_bist_i2, fabric_system_data_to_mem_bist_i3, fabric_system_data_to_mem_bist_i4, fabric_system_data_to_mem_bist_i5, fabric_system_data_to_mem_bist_i6, fabric_system_data_to_mem_bist_i7
-, fabric_system_data_to_mem_bist_i8, fabric_system_data_to_mem_bist_i9, fabric_system_data_to_mem_bist_i10, fabric_system_data_to_mem_bist_i11, fabric_system_data_to_mem_bist_i12, fabric_system_data_to_mem_bist_i13, fabric_system_data_to_mem_bist_i14, fabric_system_data_to_mem_bist_i15, fabric_system_data_to_mem_bist_i16, fabric_system_data_to_mem_bist_i17, fabric_system_data_to_mem_bist_i18, fabric_system_data_to_mem_bist_i19, fabric_system_data_to_mem_bist_i20, fabric_system_data_to_mem_bist_i21, fabric_system_data_to_mem_bist_i22, fabric_system_data_to_mem_bist_i23, fabric_system_data_to_mem_bist_i24, fabric_tst_atpg_mrepair_i, fabric_mrepair_fuse_tstscanenable_i, fabric_otp_security_bistmode_i, fabric_lowskew_i22
-, fabric_lowskew_i23, fabric_lowskew_i20, fabric_otp_user_tst_scanin_i1, fabric_otp_user_tst_scanin_i2, fabric_otp_user_tst_scanin_i3, fabric_otp_user_tst_scanin_i4, fabric_otp_user_tst_scanin_i5, fabric_sif_update_en_i1, fabric_sif_update_en_i2, fabric_sif_update_en_i3, fabric_sif_update_en_i4, fabric_sif_update_en_i5, fabric_sif_update_en_i6, fabric_sif_update_en_i7, fabric_sif_update_en_i8, fabric_sif_update_en_i9, fabric_sif_update_en_i10, fabric_sif_update_en_i11, fabric_sif_update_en_i12, fabric_sif_update_en_i13, fabric_sif_update_en_i14
-, fabric_sif_update_en_i15, fabric_sif_update_en_i16, fabric_sif_update_en_i17, fabric_sif_update_en_i18, fabric_sif_update_en_i19, fabric_sif_update_en_i20, fabric_sif_update_en_i21, fabric_sif_update_en_i22, fabric_sif_update_en_i23, fabric_sif_update_en_i24, fabric_mrepair_por_i, fabric_mrepair_rst_n_i, fabric_mrepair_initn_i, fabric_mrepair_cke_i, fabric_clk_otp_mux_i, fabric_mrepair_cke_force_i, fabric_mrepair_fuse_bbad_o, fabric_jtag_trst_n_o, fabric_debug_direct_permission_write_o1, fabric_debug_direct_permission_write_o2, fabric_debug_direct_permission_write_o3
-, fabric_debug_direct_permission_write_o4, fabric_otp_security_bist_end1_o, fabric_parusr_data_val_o, fabric_debug_lock_reg_o, fabric_debug_security_error_read_o, fabric_mrepair_fuse_tstscanout_o1, fabric_mrepair_fuse_tstscanout_o2, fabric_mrepair_fuse_tstscanout_o3, fabric_mrepair_fuse_tstscanout_o4, fabric_mrepair_fuse_tstscanout_o5, fabric_otp_user_tst_scanout_o1, fabric_otp_user_tst_scanout_o2, fabric_otp_user_tst_scanout_o3, fabric_otp_user_tst_scanout_o4, fabric_otp_user_tst_scanout_o5, fabric_sif_update_en_to_bist_o1, fabric_sif_update_en_to_bist_o2, fabric_sif_update_en_to_bist_o3, fabric_sif_update_en_to_bist_o4, fabric_sif_update_en_to_bist_o5, fabric_sif_update_en_to_bist_o6
-, fabric_sif_update_en_to_bist_o7, fabric_sif_update_en_to_bist_o8, fabric_sif_update_en_to_bist_o9, fabric_sif_update_en_to_bist_o10, fabric_sif_update_en_to_bist_o11, fabric_sif_update_en_to_bist_o12, fabric_sif_update_en_to_bist_o13, fabric_sif_update_en_to_bist_o14, fabric_sif_update_en_to_bist_o15, fabric_sif_update_en_to_bist_o16, fabric_sif_update_en_to_bist_o17, fabric_sif_update_en_to_bist_o18, fabric_sif_update_en_to_bist_o19, fabric_sif_update_en_to_bist_o20, fabric_sif_update_en_to_bist_o21, fabric_sif_update_en_to_bist_o22, fabric_sif_update_en_to_bist_o23, fabric_sif_update_en_to_bist_o24, fabric_otp_user_locked_o, fabric_otp_security_bist_bad_o, fabric_debug_frame_permission_frame_o1
-, fabric_debug_frame_permission_frame_o2, fabric_debug_frame_permission_frame_o3, fabric_debug_frame_permission_frame_o4, fabric_otp_user_pwok_o, fabric_otp_user_bend2_o, fabric_mrepair_fuse_ded_o, fabric_debug_access_reg_data_ready_o, fabric_data_to_bist_o1, fabric_data_to_bist_o2, fabric_data_to_bist_o3, fabric_data_to_bist_o4, fabric_data_to_bist_o5, fabric_data_to_bist_o6, fabric_data_to_bist_o7, fabric_data_to_bist_o8, fabric_data_to_bist_o9, fabric_data_to_bist_o10, fabric_data_to_bist_o11, fabric_data_to_bist_o12, fabric_data_to_bist_o13, fabric_data_to_bist_o14
-, fabric_data_to_bist_o15, fabric_data_to_bist_o16, fabric_data_to_bist_o17, fabric_data_to_bist_o18, fabric_data_to_bist_o19, fabric_data_to_bist_o20, fabric_data_to_bist_o21, fabric_data_to_bist_o22, fabric_data_to_bist_o23, fabric_data_to_bist_o24, fabric_otp_user_startword_o1, fabric_otp_user_startword_o2, fabric_otp_user_startword_o3, fabric_otp_user_startword_o4, fabric_otp_user_startword_o5, fabric_otp_user_startword_o6, fabric_otp_user_startword_o7, fabric_otp_user_startword_o8, fabric_otp_user_startword_o9, fabric_otp_user_startword_o10, fabric_otp_user_startword_o11
-, fabric_otp_user_startword_o12, fabric_otp_user_startword_o13, fabric_otp_user_startword_o14, fabric_otp_user_startword_o15, fabric_otp_user_startword_o16, fabric_ahb_direct_data_o1, fabric_ahb_direct_data_o2, fabric_ahb_direct_data_o3, fabric_ahb_direct_data_o4, fabric_ahb_direct_data_o5, fabric_ahb_direct_data_o6, fabric_ahb_direct_data_o7, fabric_ahb_direct_data_o8, fabric_ahb_direct_data_o9, fabric_ahb_direct_data_o10, fabric_ahb_direct_data_o11, fabric_ahb_direct_data_o12, fabric_ahb_direct_data_o13, fabric_ahb_direct_data_o14, fabric_ahb_direct_data_o15, fabric_ahb_direct_data_o16
-, fabric_ahb_direct_data_o17, fabric_ahb_direct_data_o18, fabric_ahb_direct_data_o19, fabric_ahb_direct_data_o20, fabric_ahb_direct_data_o21, fabric_ahb_direct_data_o22, fabric_ahb_direct_data_o23, fabric_ahb_direct_data_o24, fabric_ahb_direct_data_o25, fabric_ahb_direct_data_o26, fabric_ahb_direct_data_o27, fabric_ahb_direct_data_o28, fabric_ahb_direct_data_o29, fabric_ahb_direct_data_o30, fabric_ahb_direct_data_o31, fabric_ahb_direct_data_o32, fabric_parusr_data_o1, fabric_parusr_data_o2, fabric_parusr_data_o3, fabric_parusr_data_o4, fabric_parusr_data_o5
-, fabric_parusr_data_o6, fabric_parusr_data_o7, fabric_parusr_data_o8, fabric_parusr_data_o9, fabric_parusr_data_o10, fabric_parusr_data_o11, fabric_parusr_data_o12, fabric_parusr_data_o13, fabric_parusr_data_o14, fabric_parusr_data_o15, fabric_parusr_data_o16, fabric_debug_otp_reload_err_o, fabric_cfg_fabric_user_enable_o, fabric_decoder_init_ready_o, fabric_global_chip_status_o1, fabric_global_chip_status_o2, fabric_global_chip_status_o3, fabric_debug_security_boot_done_o, fabric_otp_user_calibrated_o, fabric_fuse_status_o1, fabric_fuse_status_o2
-, fabric_fuse_status_o3, fabric_otp_apb_rdata_o1, fabric_otp_apb_rdata_o2, fabric_otp_apb_rdata_o3, fabric_otp_apb_rdata_o4, fabric_otp_apb_rdata_o5, fabric_otp_apb_rdata_o6, fabric_otp_apb_rdata_o7, fabric_otp_apb_rdata_o8, fabric_otp_apb_rdata_o9, fabric_otp_apb_rdata_o10, fabric_otp_apb_rdata_o11, fabric_otp_apb_rdata_o12, fabric_otp_apb_rdata_o13, fabric_otp_apb_rdata_o14, fabric_otp_apb_rdata_o15, fabric_otp_apb_rdata_o16, fabric_otp_apb_rdata_o17, fabric_otp_apb_rdata_o18, fabric_otp_apb_rdata_o19, fabric_otp_apb_rdata_o20
-, fabric_otp_apb_rdata_o21, fabric_otp_apb_rdata_o22, fabric_otp_apb_rdata_o23, fabric_otp_apb_rdata_o24, fabric_otp_apb_rdata_o25, fabric_otp_apb_rdata_o26, fabric_otp_apb_rdata_o27, fabric_otp_apb_rdata_o28, fabric_otp_apb_rdata_o29, fabric_otp_apb_rdata_o30, fabric_otp_apb_rdata_o31, fabric_otp_apb_rdata_o32, fabric_jtag_tms_o, fabric_debug_bsec_core_status_o1, fabric_debug_bsec_core_status_o2, fabric_debug_bsec_core_status_o3, fabric_debug_bsec_core_status_o4, fabric_debug_bsec_core_status_o5, fabric_debug_bsec_core_status_o6, fabric_debug_bsec_core_status_o7, fabric_debug_bsec_core_status_o8
-, fabric_debug_bsec_core_status_o9, fabric_debug_bsec_core_status_o10, fabric_debug_bsec_core_status_o11, fabric_debug_bsec_core_status_o12, fabric_debug_bsec_core_status_o13, fabric_debug_bsec_core_status_o14, fabric_debug_bsec_core_status_o15, fabric_debug_bsec_core_status_o16, fabric_debug_bsec_core_status_o17, fabric_debug_bsec_core_status_o18, fabric_debug_bsec_core_status_o19, fabric_debug_bsec_core_status_o20, fabric_debug_bsec_core_status_o21, fabric_debug_bsec_core_status_o22, fabric_debug_bsec_core_status_o23, fabric_debug_bsec_core_status_o24, fabric_debug_bsec_core_status_o25, fabric_debug_bsec_core_status_o26, fabric_debug_bsec_core_status_o27, fabric_debug_bsec_core_status_o28, fabric_debug_bsec_core_status_o29
-, fabric_debug_bsec_core_status_o30, fabric_debug_bsec_core_status_o31, fabric_debug_bsec_core_status_o32, fabric_mrepair_fuse_bist1fail_o1, fabric_mrepair_fuse_bist1fail_o2, fabric_mrepair_fuse_bist1fail_o3, fabric_mrepair_fuse_bist1fail_o4, fabric_mrepair_fuse_bist1fail_o5, fabric_mrepair_fuse_bist1fail_o6, fabric_mrepair_fuse_bist1fail_o7, fabric_mrepair_fuse_bist1fail_o8, fabric_flag_ready_TMR_o1, fabric_flag_ready_TMR_o2, fabric_flag_ready_TMR_o3, fabric_mrepair_fuse_dout_o1, fabric_mrepair_fuse_dout_o2, fabric_mrepair_fuse_dout_o3, fabric_mrepair_fuse_dout_o4, fabric_mrepair_fuse_dout_o5, fabric_mrepair_fuse_dout_o6, fabric_mrepair_fuse_dout_o7
-, fabric_mrepair_fuse_dout_o8, fabric_mrepair_fuse_dout_o9, fabric_mrepair_fuse_dout_o10, fabric_mrepair_fuse_dout_o11, fabric_mrepair_fuse_dout_o12, fabric_mrepair_fuse_dout_o13, fabric_mrepair_fuse_dout_o14, fabric_mrepair_fuse_dout_o15, fabric_mrepair_fuse_dout_o16, fabric_mrepair_fuse_dout_o17, fabric_mrepair_fuse_dout_o18, fabric_mrepair_fuse_dout_o19, fabric_mrepair_fuse_dout_o20, fabric_mrepair_fuse_dout_o21, fabric_mrepair_fuse_dout_o22, fabric_mrepair_fuse_dout_o23, fabric_mrepair_fuse_dout_o24, fabric_mrepair_fuse_dout_o25, fabric_mrepair_fuse_dout_o26, fabric_mrepair_fuse_dout_o27, fabric_mrepair_fuse_dout_o28
-, fabric_mrepair_fuse_dout_o29, fabric_mrepair_fuse_dout_o30, fabric_mrepair_fuse_dout_o31, fabric_mrepair_fuse_dout_o32, fabric_mrepair_fuse_dout_o33, fabric_mrepair_fuse_dout_o34, fabric_mrepair_fuse_dout_o35, fabric_mrepair_fuse_dout_o36, fabric_mrepair_fuse_dout_o37, fabric_mrepair_fuse_dout_o38, fabric_mrepair_fuse_dout_o39, fabric_mrepair_fuse_dout_o40, fabric_mrepair_fuse_dout_o41, fabric_debug_rst_soft_o, fabric_otp_user_ack_o, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_shift_en_to_bist_o1, fabric_shift_en_to_bist_o2, fabric_shift_en_to_bist_o3, fabric_shift_en_to_bist_o4, fabric_shift_en_to_bist_o5
-, fabric_shift_en_to_bist_o6, fabric_shift_en_to_bist_o7, fabric_shift_en_to_bist_o8, fabric_shift_en_to_bist_o9, fabric_shift_en_to_bist_o10, fabric_shift_en_to_bist_o11, fabric_shift_en_to_bist_o12, fabric_shift_en_to_bist_o13, fabric_shift_en_to_bist_o14, fabric_shift_en_to_bist_o15, fabric_shift_en_to_bist_o16, fabric_shift_en_to_bist_o17, fabric_shift_en_to_bist_o18, fabric_shift_en_to_bist_o19, fabric_shift_en_to_bist_o20, fabric_shift_en_to_bist_o21, fabric_shift_en_to_bist_o22, fabric_shift_en_to_bist_o23, fabric_shift_en_to_bist_o24, fabric_sif_reg_en_to_bist_o1, fabric_sif_reg_en_to_bist_o2
-, fabric_sif_reg_en_to_bist_o3, fabric_sif_reg_en_to_bist_o4, fabric_sif_reg_en_to_bist_o5, fabric_sif_reg_en_to_bist_o6, fabric_sif_reg_en_to_bist_o7, fabric_sif_reg_en_to_bist_o8, fabric_sif_reg_en_to_bist_o9, fabric_sif_reg_en_to_bist_o10, fabric_sif_reg_en_to_bist_o11, fabric_sif_reg_en_to_bist_o12, fabric_sif_reg_en_to_bist_o13, fabric_sif_reg_en_to_bist_o14, fabric_sif_reg_en_to_bist_o15, fabric_sif_reg_en_to_bist_o16, fabric_sif_reg_en_to_bist_o17, fabric_sif_reg_en_to_bist_o18, fabric_sif_reg_en_to_bist_o19, fabric_sif_reg_en_to_bist_o20, fabric_sif_reg_en_to_bist_o21, fabric_sif_reg_en_to_bist_o22, fabric_sif_reg_en_to_bist_o23
-, fabric_sif_reg_en_to_bist_o24, fabric_sif_reg_en_to_bist_o25, fabric_sif_reg_en_to_bist_o26, fabric_sif_reg_en_to_bist_o27, fabric_sif_reg_en_to_bist_o28, fabric_sif_reg_en_to_bist_o29, fabric_sif_reg_en_to_bist_o30, fabric_sif_reg_en_to_bist_o31, fabric_sif_reg_en_to_bist_o32, fabric_sif_reg_en_to_bist_o33, fabric_sif_reg_en_to_bist_o34, fabric_sif_reg_en_to_bist_o35, fabric_sif_reg_en_to_bist_o36, fabric_sif_reg_en_to_bist_o37, fabric_sif_reg_en_to_bist_o38, fabric_sif_reg_en_to_bist_o39, fabric_sif_reg_en_to_bist_o40, fabric_sif_reg_en_to_bist_o41, fabric_sif_reg_en_to_bist_o42, fabric_sif_reg_en_to_bist_o43, fabric_sif_reg_en_to_bist_o44
-, fabric_sif_reg_en_to_bist_o45, fabric_sif_reg_en_to_bist_o46, fabric_sif_reg_en_to_bist_o47, fabric_sif_reg_en_to_bist_o48, fabric_sif_reg_en_to_bist_o49, fabric_sif_reg_en_to_bist_o50, fabric_sif_reg_en_to_bist_o51, fabric_sif_reg_en_to_bist_o52, fabric_sif_reg_en_to_bist_o53, fabric_sif_reg_en_to_bist_o54, fabric_sif_reg_en_to_bist_o55, fabric_sif_reg_en_to_bist_o56, fabric_sif_reg_en_to_bist_o57, fabric_sif_reg_en_to_bist_o58, fabric_sif_reg_en_to_bist_o59, fabric_sif_reg_en_to_bist_o60, fabric_sif_reg_en_to_bist_o61, fabric_sif_reg_en_to_bist_o62, fabric_sif_reg_en_to_bist_o63, fabric_sif_reg_en_to_bist_o64, fabric_sif_reg_en_to_bist_o65
-, fabric_sif_reg_en_to_bist_o66, fabric_sif_reg_en_to_bist_o67, fabric_sif_reg_en_to_bist_o68, fabric_sif_reg_en_to_bist_o69, fabric_sif_reg_en_to_bist_o70, fabric_sif_reg_en_to_bist_o71, fabric_sif_reg_en_to_bist_o72, fabric_sif_reg_en_to_bist_o73, fabric_sif_reg_en_to_bist_o74, fabric_sif_reg_en_to_bist_o75, fabric_sif_reg_en_to_bist_o76, fabric_sif_reg_en_to_bist_o77, fabric_sif_reg_en_to_bist_o78, fabric_sif_reg_en_to_bist_o79, fabric_sif_reg_en_to_bist_o80, fabric_sif_reg_en_to_bist_o81, fabric_sif_reg_en_to_bist_o82, fabric_sif_reg_en_to_bist_o83, fabric_sif_reg_en_to_bist_o84, fabric_sif_reg_en_to_bist_o85, fabric_sif_reg_en_to_bist_o86
-, fabric_sif_reg_en_to_bist_o87, fabric_sif_reg_en_to_bist_o88, fabric_sif_reg_en_to_bist_o89, fabric_sif_reg_en_to_bist_o90, fabric_sif_reg_en_to_bist_o91, fabric_sif_reg_en_to_bist_o92, fabric_sif_reg_en_to_bist_o93, fabric_sif_reg_en_to_bist_o94, fabric_sif_reg_en_to_bist_o95, fabric_sif_reg_en_to_bist_o96, fabric_sif_reg_en_to_bist_o97, fabric_sif_reg_en_to_bist_o98, fabric_sif_reg_en_to_bist_o99, fabric_sif_reg_en_to_bist_o100, fabric_sif_reg_en_to_bist_o101, fabric_sif_reg_en_to_bist_o102, fabric_sif_reg_en_to_bist_o103, fabric_sif_reg_en_to_bist_o104, fabric_sif_reg_en_to_bist_o105, fabric_sif_reg_en_to_bist_o106, fabric_sif_reg_en_to_bist_o107
-, fabric_sif_reg_en_to_bist_o108, fabric_sif_reg_en_to_bist_o109, fabric_sif_reg_en_to_bist_o110, fabric_sif_reg_en_to_bist_o111, fabric_sif_reg_en_to_bist_o112, fabric_sif_reg_en_to_bist_o113, fabric_sif_reg_en_to_bist_o114, fabric_sif_reg_en_to_bist_o115, fabric_sif_reg_en_to_bist_o116, fabric_sif_reg_en_to_bist_o117, fabric_sif_reg_en_to_bist_o118, fabric_sif_reg_en_to_bist_o119, fabric_sif_reg_en_to_bist_o120, fabric_debug_otp_manager_read_otp_o, fabric_otp_user_sec_o, fabric_otp_user_wlromout_o1, fabric_otp_user_wlromout_o2, fabric_otp_user_wlromout_o3, fabric_otp_user_wlromout_o4, fabric_otp_user_wlromout_o5, fabric_otp_user_wlromout_o6
-, fabric_otp_user_wlromout_o7, fabric_otp_user_wlromout_o8, fabric_otp_user_wlromout_o9, fabric_otp_user_wlromout_o10, fabric_mrepair_fuse_bend1_o, fabric_mrepair_fuse_flagstate_o1, fabric_mrepair_fuse_flagstate_o2, fabric_mrepair_fuse_flagstate_o3, fabric_mrepair_fuse_flagstate_o4, fabric_system_data_from_mem_bist_o1, fabric_system_data_from_mem_bist_o2, fabric_system_data_from_mem_bist_o3, fabric_system_data_from_mem_bist_o4, fabric_system_data_from_mem_bist_o5, fabric_system_data_from_mem_bist_o6, fabric_system_data_from_mem_bist_o7, fabric_system_data_from_mem_bist_o8, fabric_system_data_from_mem_bist_o9, fabric_system_data_from_mem_bist_o10, fabric_system_data_from_mem_bist_o11, fabric_system_data_from_mem_bist_o12
-, fabric_system_data_from_mem_bist_o13, fabric_system_data_from_mem_bist_o14, fabric_system_data_from_mem_bist_o15, fabric_system_data_from_mem_bist_o16, fabric_system_data_from_mem_bist_o17, fabric_system_data_from_mem_bist_o18, fabric_system_data_from_mem_bist_o19, fabric_system_data_from_mem_bist_o20, fabric_system_data_from_mem_bist_o21, fabric_system_data_from_mem_bist_o22, fabric_system_data_from_mem_bist_o23, fabric_system_data_from_mem_bist_o24, fabric_direct_data_o1, fabric_direct_data_o2, fabric_direct_data_o3, fabric_direct_data_o4, fabric_direct_data_o5, fabric_direct_data_o6, fabric_direct_data_o7, fabric_direct_data_o8, fabric_direct_data_o9
-, fabric_direct_data_o10, fabric_direct_data_o11, fabric_direct_data_o12, fabric_direct_data_o13, fabric_direct_data_o14, fabric_direct_data_o15, fabric_direct_data_o16, fabric_direct_data_o17, fabric_direct_data_o18, fabric_direct_data_o19, fabric_direct_data_o20, fabric_direct_data_o21, fabric_direct_data_o22, fabric_direct_data_o23, fabric_direct_data_o24, fabric_direct_data_o25, fabric_direct_data_o26, fabric_direct_data_o27, fabric_direct_data_o28, fabric_direct_data_o29, fabric_direct_data_o30
-, fabric_direct_data_o31, fabric_direct_data_o32, fabric_otp_user_bbad_o, fabric_user_read_cycle_o, fabric_chip_status_o1, fabric_chip_status_o2, fabric_chip_status_o3, fabric_chip_status_o4, fabric_chip_status_o5, fabric_chip_status_o6, fabric_chip_status_o7, fabric_chip_status_o8, fabric_chip_status_o9, fabric_chip_status_o10, fabric_chip_status_o11, fabric_chip_status_o12, fabric_chip_status_o13, fabric_chip_status_o14, fabric_chip_status_o15, fabric_chip_status_o16, fabric_chip_status_o17
-, fabric_chip_status_o18, fabric_chip_status_o19, fabric_chip_status_o20, fabric_chip_status_o21, fabric_chip_status_o22, fabric_chip_status_o23, fabric_chip_status_o24, fabric_chip_status_o25, fabric_chip_status_o26, fabric_chip_status_o27, fabric_chip_status_o28, fabric_chip_status_o29, fabric_chip_status_o30, fabric_chip_status_o31, fabric_chip_status_o32, fabric_chip_status_o33, fabric_chip_status_o34, fabric_chip_status_o35, fabric_chip_status_o36, fabric_chip_status_o37, fabric_chip_status_o38
-, fabric_chip_status_o39, fabric_chip_status_o40, fabric_chip_status_o41, fabric_chip_status_o42, fabric_chip_status_o43, fabric_chip_status_o44, fabric_chip_status_o45, fabric_chip_status_o46, fabric_chip_status_o47, fabric_chip_status_o48, fabric_chip_status_o49, fabric_chip_status_o50, fabric_chip_status_o51, fabric_chip_status_o52, fabric_chip_status_o53, fabric_chip_status_o54, fabric_chip_status_o55, fabric_chip_status_o56, fabric_chip_status_o57, fabric_chip_status_o58, fabric_chip_status_o59
-, fabric_chip_status_o60, fabric_chip_status_o61, fabric_chip_status_o62, fabric_chip_status_o63, fabric_chip_status_o64, fabric_chip_status_o65, fabric_chip_status_o66, fabric_chip_status_o67, fabric_chip_status_o68, fabric_chip_status_o69, fabric_chip_status_o70, fabric_chip_status_o71, fabric_chip_status_o72, fabric_mrepair_fuse_disturbed_o, fabric_debug_otpboot_state_o1, fabric_debug_otpboot_state_o2, fabric_debug_otpboot_state_o3, fabric_pd_ready_o1, fabric_pd_ready_o2, fabric_pd_ready_o3, fabric_pd_ready_o4
-, fabric_pd_ready_o5, fabric_pd_ready_o6, fabric_pd_ready_o7, fabric_pd_ready_o8, fabric_pd_ready_o9, fabric_pd_ready_o10, fabric_pd_ready_o11, fabric_pd_ready_o12, fabric_pd_ready_o13, fabric_pd_ready_o14, fabric_pd_ready_o15, fabric_pd_ready_o16, fabric_pd_ready_o17, fabric_pd_ready_o18, fabric_pd_ready_o19, fabric_pd_ready_o20, fabric_pd_ready_o21, fabric_pd_ready_o22, fabric_pd_ready_o23, fabric_pd_ready_o24, fabric_debug_key_correct_o
-, fabric_otp_apb_ready_o, fabric_otp_user_progfail_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_bend2_o, fabric_debug_lifecycle_o1, fabric_debug_lifecycle_o2, fabric_debug_lifecycle_o3, fabric_debug_lifecycle_o4, fabric_mrepair_fuse_ack_o, fabric_debug_cpt_retry_o1, fabric_debug_cpt_retry_o2, fabric_debug_cpt_retry_o3, fabric_debug_cpt_retry_o4, fabric_otp_security_ack_o, fabric_debug_otpmgmt_state_o1, fabric_debug_otpmgmt_state_o2, fabric_debug_otpmgmt_state_o3, fabric_mrepair_fuse_progfail_o, fabric_otp_user_bist2fail_o1, fabric_otp_user_bist2fail_o2, fabric_otp_user_bist2fail_o3
-, fabric_otp_user_bist2fail_o4, fabric_otp_user_bist2fail_o5, fabric_otp_user_bist2fail_o6, fabric_otp_user_bist2fail_o7, fabric_user_data_o1, fabric_user_data_o2, fabric_user_data_o3, fabric_user_data_o4, fabric_user_data_o5, fabric_user_data_o6, fabric_user_data_o7, fabric_user_data_o8, fabric_user_data_o9, fabric_user_data_o10, fabric_user_data_o11, fabric_user_data_o12, fabric_user_data_o13, fabric_user_data_o14, fabric_user_data_o15, fabric_user_data_o16, fabric_user_data_o17
-, fabric_user_data_o18, fabric_user_data_o19, fabric_user_data_o20, fabric_user_data_o21, fabric_user_data_o22, fabric_user_data_o23, fabric_user_data_o24, fabric_user_data_o25, fabric_user_data_o26, fabric_user_data_o27, fabric_user_data_o28, fabric_user_data_o29, fabric_user_data_o30, fabric_user_data_o31, fabric_user_data_o32, fabric_jtag_tdi_o, fabric_lowskew_o3, fabric_lowskew_o5, fabric_lowskew_o4, fabric_debug_error_o, fabric_jtag_usr2_o
-, fabric_mrepair_fuse_wlromout_o1, fabric_mrepair_fuse_wlromout_o2, fabric_mrepair_fuse_wlromout_o3, fabric_mrepair_fuse_wlromout_o4, fabric_mrepair_fuse_wlromout_o5, fabric_mrepair_fuse_wlromout_o6, fabric_mrepair_fuse_wlromout_o7, fabric_mrepair_fuse_wlromout_o8, fabric_mrepair_fuse_wlromout_o9, fabric_mrepair_fuse_wlromout_o10, fabric_debug_otpapb_state_o1, fabric_debug_otpapb_state_o2, fabric_debug_otpapb_state_o3, fabric_otp_user_bist1fail_o1, fabric_otp_user_bist1fail_o2, fabric_otp_user_bist1fail_o3, fabric_otp_user_bist1fail_o4, fabric_otp_user_bist1fail_o5, fabric_otp_user_bist1fail_o6, fabric_otp_user_bist1fail_o7, fabric_otp_user_bist1fail_o8
-, fabric_otp_security_bist_fail2_o1, fabric_otp_security_bist_fail2_o2, fabric_otp_security_bist_fail2_o3, fabric_otp_security_bist_fail2_o4, fabric_otp_security_bist_fail2_o5, fabric_otp_security_bist_fail2_o6, fabric_otp_security_bist_fail2_o7, fabric_otp_user_disturbed_o, fabric_flag_trigger_o, fabric_otp_security_bist_end2_o, fabric_otp_security_bist_fail1_o1, fabric_otp_security_bist_fail1_o2, fabric_otp_security_bist_fail1_o3, fabric_otp_security_bist_fail1_o4, fabric_otp_security_bist_fail1_o5, fabric_otp_security_bist_fail1_o6, fabric_otp_security_bist_fail1_o7, fabric_otp_security_bist_fail1_o8, fabric_mrepair_fuse_locked_o, fabric_otp_user_flagstate_o1, fabric_otp_user_flagstate_o2
-, fabric_otp_user_flagstate_o3, fabric_otp_user_flagstate_o4, fabric_otp_security_scanout_o1, fabric_otp_security_scanout_o2, fabric_otp_security_scanout_o3, fabric_otp_security_scanout_o4, fabric_otp_security_scanout_o5, fabric_user_write_cycle_o, fabric_debug_fsm_state_o1, fabric_debug_fsm_state_o2, fabric_debug_fsm_state_o3, fabric_otp_user_ded_o, fabric_debug_otp_manager_read_done_o, fabric_debug_frame_use_encryption_o, fabric_data_to_system_o, fabric_jtag_usr1_o, fabric_otp_user_bend1_o, fabric_debug_otpboot_curr_addr_o1, fabric_debug_otpboot_curr_addr_o2, fabric_debug_otpboot_curr_addr_o3, fabric_debug_otpboot_curr_addr_o4
-, fabric_debug_otpboot_curr_addr_o5, fabric_debug_otpboot_curr_addr_o6, fabric_debug_otpboot_curr_addr_o7, fabric_debug_otpboot_curr_addr_o8, fabric_mrepair_fuse_ready_o, fabric_mrepair_fuse_calibrated_o, fabric_sif_load_en_to_bist_o1, fabric_sif_load_en_to_bist_o2, fabric_sif_load_en_to_bist_o3, fabric_sif_load_en_to_bist_o4, fabric_sif_load_en_to_bist_o5, fabric_sif_load_en_to_bist_o6, fabric_sif_load_en_to_bist_o7, fabric_sif_load_en_to_bist_o8, fabric_sif_load_en_to_bist_o9, fabric_sif_load_en_to_bist_o10, fabric_sif_load_en_to_bist_o11, fabric_sif_load_en_to_bist_o12, fabric_sif_load_en_to_bist_o13, fabric_sif_load_en_to_bist_o14, fabric_sif_load_en_to_bist_o15
-, fabric_sif_load_en_to_bist_o16, fabric_sif_load_en_to_bist_o17, fabric_sif_load_en_to_bist_o18, fabric_sif_load_en_to_bist_o19, fabric_sif_load_en_to_bist_o20, fabric_sif_load_en_to_bist_o21, fabric_sif_load_en_to_bist_o22, fabric_sif_load_en_to_bist_o23, fabric_sif_load_en_to_bist_o24, fabric_io_out_o1, fabric_io_out_o2, fabric_io_out_o3, fabric_io_out_o4, fabric_io_out_o5, fabric_io_out_o6, fabric_io_out_o7, fabric_io_out_o8, fabric_io_out_o9, fabric_io_out_o10, fabric_io_out_o11, fabric_io_out_o12
-, fabric_io_out_o13, fabric_io_out_o14, fabric_io_out_o15, fabric_io_out_o16, fabric_io_out_o17, fabric_io_out_o18, fabric_io_out_o19, fabric_io_out_o20, fabric_io_out_o21, fabric_io_out_o22, fabric_io_out_o23, fabric_io_out_o24, fabric_io_out_o25, fabric_mrepair_fuse_startword_o1, fabric_mrepair_fuse_startword_o2, fabric_mrepair_fuse_startword_o3, fabric_mrepair_fuse_startword_o4, fabric_mrepair_fuse_startword_o5, fabric_mrepair_fuse_startword_o6, fabric_mrepair_fuse_startword_o7, fabric_mrepair_fuse_startword_o8
-, fabric_mrepair_fuse_startword_o9, fabric_mrepair_fuse_startword_o10, fabric_mrepair_fuse_startword_o11, fabric_mrepair_fuse_startword_o12, fabric_mrepair_fuse_startword_o13, fabric_mrepair_fuse_startword_o14, fabric_mrepair_fuse_startword_o15, fabric_mrepair_fuse_startword_o16, fabric_system_dataready_o, fabric_mrepair_fuse_pwok_o, fabric_lowskew_o6, fabric_cfg_fabric_user_flag_o, fabric_otp_user_dout_o1, fabric_otp_user_dout_o2, fabric_otp_user_dout_o3, fabric_otp_user_dout_o4, fabric_otp_user_dout_o5, fabric_otp_user_dout_o6, fabric_otp_user_dout_o7, fabric_otp_user_dout_o8, fabric_otp_user_dout_o9
-, fabric_otp_user_dout_o10, fabric_otp_user_dout_o11, fabric_otp_user_dout_o12, fabric_otp_user_dout_o13, fabric_otp_user_dout_o14, fabric_otp_user_dout_o15, fabric_otp_user_dout_o16, fabric_otp_user_dout_o17, fabric_otp_user_dout_o18, fabric_otp_user_dout_o19, fabric_otp_user_dout_o20, fabric_otp_user_dout_o21, fabric_otp_user_dout_o22, fabric_otp_user_dout_o23, fabric_otp_user_dout_o24, fabric_otp_user_dout_o25, fabric_otp_user_dout_o26, fabric_otp_user_dout_o27, fabric_otp_user_dout_o28, fabric_otp_user_dout_o29, fabric_otp_user_dout_o30
-, fabric_otp_user_dout_o31, fabric_otp_user_dout_o32, fabric_otp_user_dout_o33, fabric_otp_user_dout_o34, fabric_otp_user_dout_o35, fabric_otp_user_dout_o36, fabric_otp_user_dout_o37, fabric_otp_user_dout_o38, fabric_otp_user_dout_o39, fabric_otp_user_dout_o40, fabric_otp_user_dout_o41, fabric_mrepair_fuse_bist2fail_o1, fabric_mrepair_fuse_bist2fail_o2, fabric_mrepair_fuse_bist2fail_o3, fabric_mrepair_fuse_bist2fail_o4, fabric_mrepair_fuse_bist2fail_o5, fabric_mrepair_fuse_bist2fail_o6, fabric_mrepair_fuse_bist2fail_o7, fabric_status_cold_start_o, fabric_flag_error_o, fabric_debug_direct_permission_read_o1
-, fabric_debug_direct_permission_read_o2, fabric_debug_direct_permission_read_o3, fabric_debug_direct_permission_read_o4, fabric_otp_user_clock_frequency_range_i, fabric_parusr_enable_i);
-    input fabric_ahb_direct_data_i1;
-    input fabric_ahb_direct_data_i10;
-    input fabric_ahb_direct_data_i11;
-    input fabric_ahb_direct_data_i12;
-    input fabric_ahb_direct_data_i13;
-    input fabric_ahb_direct_data_i14;
-    input fabric_ahb_direct_data_i15;
-    input fabric_ahb_direct_data_i16;
-    input fabric_ahb_direct_data_i17;
-    input fabric_ahb_direct_data_i18;
-    input fabric_ahb_direct_data_i19;
-    input fabric_ahb_direct_data_i2;
-    input fabric_ahb_direct_data_i20;
-    input fabric_ahb_direct_data_i21;
-    input fabric_ahb_direct_data_i22;
-    input fabric_ahb_direct_data_i23;
-    input fabric_ahb_direct_data_i24;
-    input fabric_ahb_direct_data_i25;
-    input fabric_ahb_direct_data_i26;
-    input fabric_ahb_direct_data_i27;
-    input fabric_ahb_direct_data_i28;
-    input fabric_ahb_direct_data_i29;
-    input fabric_ahb_direct_data_i3;
-    input fabric_ahb_direct_data_i30;
-    input fabric_ahb_direct_data_i31;
-    input fabric_ahb_direct_data_i32;
-    input fabric_ahb_direct_data_i4;
-    input fabric_ahb_direct_data_i5;
-    input fabric_ahb_direct_data_i6;
-    input fabric_ahb_direct_data_i7;
-    input fabric_ahb_direct_data_i8;
-    input fabric_ahb_direct_data_i9;
-    output fabric_ahb_direct_data_o1;
-    output fabric_ahb_direct_data_o10;
-    output fabric_ahb_direct_data_o11;
-    output fabric_ahb_direct_data_o12;
-    output fabric_ahb_direct_data_o13;
-    output fabric_ahb_direct_data_o14;
-    output fabric_ahb_direct_data_o15;
-    output fabric_ahb_direct_data_o16;
-    output fabric_ahb_direct_data_o17;
-    output fabric_ahb_direct_data_o18;
-    output fabric_ahb_direct_data_o19;
-    output fabric_ahb_direct_data_o2;
-    output fabric_ahb_direct_data_o20;
-    output fabric_ahb_direct_data_o21;
-    output fabric_ahb_direct_data_o22;
-    output fabric_ahb_direct_data_o23;
-    output fabric_ahb_direct_data_o24;
-    output fabric_ahb_direct_data_o25;
-    output fabric_ahb_direct_data_o26;
-    output fabric_ahb_direct_data_o27;
-    output fabric_ahb_direct_data_o28;
-    output fabric_ahb_direct_data_o29;
-    output fabric_ahb_direct_data_o3;
-    output fabric_ahb_direct_data_o30;
-    output fabric_ahb_direct_data_o31;
-    output fabric_ahb_direct_data_o32;
-    output fabric_ahb_direct_data_o4;
-    output fabric_ahb_direct_data_o5;
-    output fabric_ahb_direct_data_o6;
-    output fabric_ahb_direct_data_o7;
-    output fabric_ahb_direct_data_o8;
-    output fabric_ahb_direct_data_o9;
-    output fabric_cfg_fabric_user_enable_o;
-    output fabric_cfg_fabric_user_flag_o;
-    output fabric_chip_status_o1;
-    output fabric_chip_status_o10;
-    output fabric_chip_status_o11;
-    output fabric_chip_status_o12;
-    output fabric_chip_status_o13;
-    output fabric_chip_status_o14;
-    output fabric_chip_status_o15;
-    output fabric_chip_status_o16;
-    output fabric_chip_status_o17;
-    output fabric_chip_status_o18;
-    output fabric_chip_status_o19;
-    output fabric_chip_status_o2;
-    output fabric_chip_status_o20;
-    output fabric_chip_status_o21;
-    output fabric_chip_status_o22;
-    output fabric_chip_status_o23;
-    output fabric_chip_status_o24;
-    output fabric_chip_status_o25;
-    output fabric_chip_status_o26;
-    output fabric_chip_status_o27;
-    output fabric_chip_status_o28;
-    output fabric_chip_status_o29;
-    output fabric_chip_status_o3;
-    output fabric_chip_status_o30;
-    output fabric_chip_status_o31;
-    output fabric_chip_status_o32;
-    output fabric_chip_status_o33;
-    output fabric_chip_status_o34;
-    output fabric_chip_status_o35;
-    output fabric_chip_status_o36;
-    output fabric_chip_status_o37;
-    output fabric_chip_status_o38;
-    output fabric_chip_status_o39;
-    output fabric_chip_status_o4;
-    output fabric_chip_status_o40;
-    output fabric_chip_status_o41;
-    output fabric_chip_status_o42;
-    output fabric_chip_status_o43;
-    output fabric_chip_status_o44;
-    output fabric_chip_status_o45;
-    output fabric_chip_status_o46;
-    output fabric_chip_status_o47;
-    output fabric_chip_status_o48;
-    output fabric_chip_status_o49;
-    output fabric_chip_status_o5;
-    output fabric_chip_status_o50;
-    output fabric_chip_status_o51;
-    output fabric_chip_status_o52;
-    output fabric_chip_status_o53;
-    output fabric_chip_status_o54;
-    output fabric_chip_status_o55;
-    output fabric_chip_status_o56;
-    output fabric_chip_status_o57;
-    output fabric_chip_status_o58;
-    output fabric_chip_status_o59;
-    output fabric_chip_status_o6;
-    output fabric_chip_status_o60;
-    output fabric_chip_status_o61;
-    output fabric_chip_status_o62;
-    output fabric_chip_status_o63;
-    output fabric_chip_status_o64;
-    output fabric_chip_status_o65;
-    output fabric_chip_status_o66;
-    output fabric_chip_status_o67;
-    output fabric_chip_status_o68;
-    output fabric_chip_status_o69;
-    output fabric_chip_status_o7;
-    output fabric_chip_status_o70;
-    output fabric_chip_status_o71;
-    output fabric_chip_status_o72;
-    output fabric_chip_status_o8;
-    output fabric_chip_status_o9;
-    input fabric_clk_otp_mux_i;
-    input fabric_data_from_bist_i1;
-    input fabric_data_from_bist_i10;
-    input fabric_data_from_bist_i11;
-    input fabric_data_from_bist_i12;
-    input fabric_data_from_bist_i13;
-    input fabric_data_from_bist_i14;
-    input fabric_data_from_bist_i15;
-    input fabric_data_from_bist_i16;
-    input fabric_data_from_bist_i17;
-    input fabric_data_from_bist_i18;
-    input fabric_data_from_bist_i19;
-    input fabric_data_from_bist_i2;
-    input fabric_data_from_bist_i20;
-    input fabric_data_from_bist_i21;
-    input fabric_data_from_bist_i22;
-    input fabric_data_from_bist_i23;
-    input fabric_data_from_bist_i24;
-    input fabric_data_from_bist_i3;
-    input fabric_data_from_bist_i4;
-    input fabric_data_from_bist_i5;
-    input fabric_data_from_bist_i6;
-    input fabric_data_from_bist_i7;
-    input fabric_data_from_bist_i8;
-    input fabric_data_from_bist_i9;
-    input fabric_data_from_system_i;
-    input fabric_data_shift_en_i;
-    output fabric_data_to_bist_o1;
-    output fabric_data_to_bist_o10;
-    output fabric_data_to_bist_o11;
-    output fabric_data_to_bist_o12;
-    output fabric_data_to_bist_o13;
-    output fabric_data_to_bist_o14;
-    output fabric_data_to_bist_o15;
-    output fabric_data_to_bist_o16;
-    output fabric_data_to_bist_o17;
-    output fabric_data_to_bist_o18;
-    output fabric_data_to_bist_o19;
-    output fabric_data_to_bist_o2;
-    output fabric_data_to_bist_o20;
-    output fabric_data_to_bist_o21;
-    output fabric_data_to_bist_o22;
-    output fabric_data_to_bist_o23;
-    output fabric_data_to_bist_o24;
-    output fabric_data_to_bist_o3;
-    output fabric_data_to_bist_o4;
-    output fabric_data_to_bist_o5;
-    output fabric_data_to_bist_o6;
-    output fabric_data_to_bist_o7;
-    output fabric_data_to_bist_o8;
-    output fabric_data_to_bist_o9;
-    output fabric_data_to_system_o;
-    output fabric_debug_access_reg_data_ready_o;
-    output fabric_debug_bsec_core_status_o1;
-    output fabric_debug_bsec_core_status_o10;
-    output fabric_debug_bsec_core_status_o11;
-    output fabric_debug_bsec_core_status_o12;
-    output fabric_debug_bsec_core_status_o13;
-    output fabric_debug_bsec_core_status_o14;
-    output fabric_debug_bsec_core_status_o15;
-    output fabric_debug_bsec_core_status_o16;
-    output fabric_debug_bsec_core_status_o17;
-    output fabric_debug_bsec_core_status_o18;
-    output fabric_debug_bsec_core_status_o19;
-    output fabric_debug_bsec_core_status_o2;
-    output fabric_debug_bsec_core_status_o20;
-    output fabric_debug_bsec_core_status_o21;
-    output fabric_debug_bsec_core_status_o22;
-    output fabric_debug_bsec_core_status_o23;
-    output fabric_debug_bsec_core_status_o24;
-    output fabric_debug_bsec_core_status_o25;
-    output fabric_debug_bsec_core_status_o26;
-    output fabric_debug_bsec_core_status_o27;
-    output fabric_debug_bsec_core_status_o28;
-    output fabric_debug_bsec_core_status_o29;
-    output fabric_debug_bsec_core_status_o3;
-    output fabric_debug_bsec_core_status_o30;
-    output fabric_debug_bsec_core_status_o31;
-    output fabric_debug_bsec_core_status_o32;
-    output fabric_debug_bsec_core_status_o4;
-    output fabric_debug_bsec_core_status_o5;
-    output fabric_debug_bsec_core_status_o6;
-    output fabric_debug_bsec_core_status_o7;
-    output fabric_debug_bsec_core_status_o8;
-    output fabric_debug_bsec_core_status_o9;
-    output fabric_debug_cpt_retry_o1;
-    output fabric_debug_cpt_retry_o2;
-    output fabric_debug_cpt_retry_o3;
-    output fabric_debug_cpt_retry_o4;
-    output fabric_debug_direct_permission_read_o1;
-    output fabric_debug_direct_permission_read_o2;
-    output fabric_debug_direct_permission_read_o3;
-    output fabric_debug_direct_permission_read_o4;
-    output fabric_debug_direct_permission_write_o1;
-    output fabric_debug_direct_permission_write_o2;
-    output fabric_debug_direct_permission_write_o3;
-    output fabric_debug_direct_permission_write_o4;
-    output fabric_debug_error_o;
-    output fabric_debug_frame_permission_frame_o1;
-    output fabric_debug_frame_permission_frame_o2;
-    output fabric_debug_frame_permission_frame_o3;
-    output fabric_debug_frame_permission_frame_o4;
-    output fabric_debug_frame_use_encryption_o;
-    output fabric_debug_fsm_state_o1;
-    output fabric_debug_fsm_state_o2;
-    output fabric_debug_fsm_state_o3;
-    output fabric_debug_key_correct_o;
-    output fabric_debug_lifecycle_o1;
-    output fabric_debug_lifecycle_o2;
-    output fabric_debug_lifecycle_o3;
-    output fabric_debug_lifecycle_o4;
-    output fabric_debug_lock_reg_o;
-    output fabric_debug_otp_manager_read_done_o;
-    output fabric_debug_otp_manager_read_otp_o;
-    output fabric_debug_otp_reload_err_o;
-    output fabric_debug_otpapb_state_o1;
-    output fabric_debug_otpapb_state_o2;
-    output fabric_debug_otpapb_state_o3;
-    output fabric_debug_otpboot_curr_addr_o1;
-    output fabric_debug_otpboot_curr_addr_o2;
-    output fabric_debug_otpboot_curr_addr_o3;
-    output fabric_debug_otpboot_curr_addr_o4;
-    output fabric_debug_otpboot_curr_addr_o5;
-    output fabric_debug_otpboot_curr_addr_o6;
-    output fabric_debug_otpboot_curr_addr_o7;
-    output fabric_debug_otpboot_curr_addr_o8;
-    output fabric_debug_otpboot_state_o1;
-    output fabric_debug_otpboot_state_o2;
-    output fabric_debug_otpboot_state_o3;
-    output fabric_debug_otpmgmt_state_o1;
-    output fabric_debug_otpmgmt_state_o2;
-    output fabric_debug_otpmgmt_state_o3;
-    output fabric_debug_rst_soft_o;
-    output fabric_debug_security_boot_done_o;
-    output fabric_debug_security_error_read_o;
-    output fabric_decoder_init_ready_o;
-    input fabric_direct_data_i1;
-    input fabric_direct_data_i10;
-    input fabric_direct_data_i11;
-    input fabric_direct_data_i12;
-    input fabric_direct_data_i13;
-    input fabric_direct_data_i14;
-    input fabric_direct_data_i15;
-    input fabric_direct_data_i16;
-    input fabric_direct_data_i17;
-    input fabric_direct_data_i18;
-    input fabric_direct_data_i19;
-    input fabric_direct_data_i2;
-    input fabric_direct_data_i20;
-    input fabric_direct_data_i21;
-    input fabric_direct_data_i22;
-    input fabric_direct_data_i23;
-    input fabric_direct_data_i24;
-    input fabric_direct_data_i25;
-    input fabric_direct_data_i26;
-    input fabric_direct_data_i27;
-    input fabric_direct_data_i28;
-    input fabric_direct_data_i29;
-    input fabric_direct_data_i3;
-    input fabric_direct_data_i30;
-    input fabric_direct_data_i31;
-    input fabric_direct_data_i32;
-    input fabric_direct_data_i4;
-    input fabric_direct_data_i5;
-    input fabric_direct_data_i6;
-    input fabric_direct_data_i7;
-    input fabric_direct_data_i8;
-    input fabric_direct_data_i9;
-    output fabric_direct_data_o1;
-    output fabric_direct_data_o10;
-    output fabric_direct_data_o11;
-    output fabric_direct_data_o12;
-    output fabric_direct_data_o13;
-    output fabric_direct_data_o14;
-    output fabric_direct_data_o15;
-    output fabric_direct_data_o16;
-    output fabric_direct_data_o17;
-    output fabric_direct_data_o18;
-    output fabric_direct_data_o19;
-    output fabric_direct_data_o2;
-    output fabric_direct_data_o20;
-    output fabric_direct_data_o21;
-    output fabric_direct_data_o22;
-    output fabric_direct_data_o23;
-    output fabric_direct_data_o24;
-    output fabric_direct_data_o25;
-    output fabric_direct_data_o26;
-    output fabric_direct_data_o27;
-    output fabric_direct_data_o28;
-    output fabric_direct_data_o29;
-    output fabric_direct_data_o3;
-    output fabric_direct_data_o30;
-    output fabric_direct_data_o31;
-    output fabric_direct_data_o32;
-    output fabric_direct_data_o4;
-    output fabric_direct_data_o5;
-    output fabric_direct_data_o6;
-    output fabric_direct_data_o7;
-    output fabric_direct_data_o8;
-    output fabric_direct_data_o9;
-    input fabric_end_encoding_i;
-    output fabric_flag_error_o;
-    output fabric_flag_ready_TMR_o1;
-    output fabric_flag_ready_TMR_o2;
-    output fabric_flag_ready_TMR_o3;
-    output fabric_flag_trigger_o;
-    output fabric_fuse_status_o1;
-    output fabric_fuse_status_o2;
-    output fabric_fuse_status_o3;
-    output fabric_global_chip_status_o1;
-    output fabric_global_chip_status_o2;
-    output fabric_global_chip_status_o3;
-    input fabric_io_in_i1;
-    input fabric_io_in_i10;
-    input fabric_io_in_i11;
-    input fabric_io_in_i12;
-    input fabric_io_in_i13;
-    input fabric_io_in_i14;
-    input fabric_io_in_i15;
-    input fabric_io_in_i16;
-    input fabric_io_in_i17;
-    input fabric_io_in_i18;
-    input fabric_io_in_i19;
-    input fabric_io_in_i2;
-    input fabric_io_in_i20;
-    input fabric_io_in_i21;
-    input fabric_io_in_i22;
-    input fabric_io_in_i23;
-    input fabric_io_in_i24;
-    input fabric_io_in_i25;
-    input fabric_io_in_i3;
-    input fabric_io_in_i4;
-    input fabric_io_in_i5;
-    input fabric_io_in_i6;
-    input fabric_io_in_i7;
-    input fabric_io_in_i8;
-    input fabric_io_in_i9;
-    input fabric_io_oe_i1;
-    input fabric_io_oe_i10;
-    input fabric_io_oe_i11;
-    input fabric_io_oe_i12;
-    input fabric_io_oe_i13;
-    input fabric_io_oe_i14;
-    input fabric_io_oe_i15;
-    input fabric_io_oe_i16;
-    input fabric_io_oe_i17;
-    input fabric_io_oe_i18;
-    input fabric_io_oe_i19;
-    input fabric_io_oe_i2;
-    input fabric_io_oe_i20;
-    input fabric_io_oe_i21;
-    input fabric_io_oe_i22;
-    input fabric_io_oe_i23;
-    input fabric_io_oe_i24;
-    input fabric_io_oe_i25;
-    input fabric_io_oe_i3;
-    input fabric_io_oe_i4;
-    input fabric_io_oe_i5;
-    input fabric_io_oe_i6;
-    input fabric_io_oe_i7;
-    input fabric_io_oe_i8;
-    input fabric_io_oe_i9;
-    output fabric_io_out_o1;
-    output fabric_io_out_o10;
-    output fabric_io_out_o11;
-    output fabric_io_out_o12;
-    output fabric_io_out_o13;
-    output fabric_io_out_o14;
-    output fabric_io_out_o15;
-    output fabric_io_out_o16;
-    output fabric_io_out_o17;
-    output fabric_io_out_o18;
-    output fabric_io_out_o19;
-    output fabric_io_out_o2;
-    output fabric_io_out_o20;
-    output fabric_io_out_o21;
-    output fabric_io_out_o22;
-    output fabric_io_out_o23;
-    output fabric_io_out_o24;
-    output fabric_io_out_o25;
-    output fabric_io_out_o3;
-    output fabric_io_out_o4;
-    output fabric_io_out_o5;
-    output fabric_io_out_o6;
-    output fabric_io_out_o7;
-    output fabric_io_out_o8;
-    output fabric_io_out_o9;
-    output fabric_jtag_tdi_o;
-    input fabric_jtag_tdo_usr1_i;
-    input fabric_jtag_tdo_usr2_i;
-    output fabric_jtag_tms_o;
-    output fabric_jtag_trst_n_o;
-    output fabric_jtag_usr1_o;
-    output fabric_jtag_usr2_o;
-    input fabric_lowskew_i20;
-    input fabric_lowskew_i21;
-    input fabric_lowskew_i22;
-    input fabric_lowskew_i23;
-    output fabric_lowskew_o3;
-    output fabric_lowskew_o4;
-    output fabric_lowskew_o5;
-    output fabric_lowskew_o6;
-    input fabric_mrepair_cke_force_i;
-    input fabric_mrepair_cke_i;
-    output fabric_mrepair_fuse_ack_o;
-    input fabric_mrepair_fuse_add_i1;
-    input fabric_mrepair_fuse_add_i2;
-    input fabric_mrepair_fuse_add_i3;
-    input fabric_mrepair_fuse_add_i4;
-    input fabric_mrepair_fuse_add_i5;
-    input fabric_mrepair_fuse_add_i6;
-    input fabric_mrepair_fuse_add_i7;
-    output fabric_mrepair_fuse_bbad_o;
-    output fabric_mrepair_fuse_bend1_o;
-    output fabric_mrepair_fuse_bend2_o;
-    output fabric_mrepair_fuse_bist1fail_o1;
-    output fabric_mrepair_fuse_bist1fail_o2;
-    output fabric_mrepair_fuse_bist1fail_o3;
-    output fabric_mrepair_fuse_bist1fail_o4;
-    output fabric_mrepair_fuse_bist1fail_o5;
-    output fabric_mrepair_fuse_bist1fail_o6;
-    output fabric_mrepair_fuse_bist1fail_o7;
-    output fabric_mrepair_fuse_bist1fail_o8;
-    output fabric_mrepair_fuse_bist2fail_o1;
-    output fabric_mrepair_fuse_bist2fail_o2;
-    output fabric_mrepair_fuse_bist2fail_o3;
-    output fabric_mrepair_fuse_bist2fail_o4;
-    output fabric_mrepair_fuse_bist2fail_o5;
-    output fabric_mrepair_fuse_bist2fail_o6;
-    output fabric_mrepair_fuse_bist2fail_o7;
-    input fabric_mrepair_fuse_bistmode_i;
-    output fabric_mrepair_fuse_calibrated_o;
-    output fabric_mrepair_fuse_ded_o;
-    input fabric_mrepair_fuse_din_i1;
-    input fabric_mrepair_fuse_din_i10;
-    input fabric_mrepair_fuse_din_i11;
-    input fabric_mrepair_fuse_din_i12;
-    input fabric_mrepair_fuse_din_i13;
-    input fabric_mrepair_fuse_din_i14;
-    input fabric_mrepair_fuse_din_i15;
-    input fabric_mrepair_fuse_din_i16;
-    input fabric_mrepair_fuse_din_i17;
-    input fabric_mrepair_fuse_din_i18;
-    input fabric_mrepair_fuse_din_i19;
-    input fabric_mrepair_fuse_din_i2;
-    input fabric_mrepair_fuse_din_i20;
-    input fabric_mrepair_fuse_din_i21;
-    input fabric_mrepair_fuse_din_i22;
-    input fabric_mrepair_fuse_din_i23;
-    input fabric_mrepair_fuse_din_i24;
-    input fabric_mrepair_fuse_din_i25;
-    input fabric_mrepair_fuse_din_i26;
-    input fabric_mrepair_fuse_din_i27;
-    input fabric_mrepair_fuse_din_i28;
-    input fabric_mrepair_fuse_din_i29;
-    input fabric_mrepair_fuse_din_i3;
-    input fabric_mrepair_fuse_din_i30;
-    input fabric_mrepair_fuse_din_i31;
-    input fabric_mrepair_fuse_din_i32;
-    input fabric_mrepair_fuse_din_i33;
-    input fabric_mrepair_fuse_din_i34;
-    input fabric_mrepair_fuse_din_i35;
-    input fabric_mrepair_fuse_din_i36;
-    input fabric_mrepair_fuse_din_i37;
-    input fabric_mrepair_fuse_din_i38;
-    input fabric_mrepair_fuse_din_i39;
-    input fabric_mrepair_fuse_din_i4;
-    input fabric_mrepair_fuse_din_i5;
-    input fabric_mrepair_fuse_din_i6;
-    input fabric_mrepair_fuse_din_i7;
-    input fabric_mrepair_fuse_din_i8;
-    input fabric_mrepair_fuse_din_i9;
-    input fabric_mrepair_fuse_disturbchecked_i;
-    output fabric_mrepair_fuse_disturbed_o;
-    output fabric_mrepair_fuse_dout_o1;
-    output fabric_mrepair_fuse_dout_o10;
-    output fabric_mrepair_fuse_dout_o11;
-    output fabric_mrepair_fuse_dout_o12;
-    output fabric_mrepair_fuse_dout_o13;
-    output fabric_mrepair_fuse_dout_o14;
-    output fabric_mrepair_fuse_dout_o15;
-    output fabric_mrepair_fuse_dout_o16;
-    output fabric_mrepair_fuse_dout_o17;
-    output fabric_mrepair_fuse_dout_o18;
-    output fabric_mrepair_fuse_dout_o19;
-    output fabric_mrepair_fuse_dout_o2;
-    output fabric_mrepair_fuse_dout_o20;
-    output fabric_mrepair_fuse_dout_o21;
-    output fabric_mrepair_fuse_dout_o22;
-    output fabric_mrepair_fuse_dout_o23;
-    output fabric_mrepair_fuse_dout_o24;
-    output fabric_mrepair_fuse_dout_o25;
-    output fabric_mrepair_fuse_dout_o26;
-    output fabric_mrepair_fuse_dout_o27;
-    output fabric_mrepair_fuse_dout_o28;
-    output fabric_mrepair_fuse_dout_o29;
-    output fabric_mrepair_fuse_dout_o3;
-    output fabric_mrepair_fuse_dout_o30;
-    output fabric_mrepair_fuse_dout_o31;
-    output fabric_mrepair_fuse_dout_o32;
-    output fabric_mrepair_fuse_dout_o33;
-    output fabric_mrepair_fuse_dout_o34;
-    output fabric_mrepair_fuse_dout_o35;
-    output fabric_mrepair_fuse_dout_o36;
-    output fabric_mrepair_fuse_dout_o37;
-    output fabric_mrepair_fuse_dout_o38;
-    output fabric_mrepair_fuse_dout_o39;
-    output fabric_mrepair_fuse_dout_o4;
-    output fabric_mrepair_fuse_dout_o40;
-    output fabric_mrepair_fuse_dout_o41;
-    output fabric_mrepair_fuse_dout_o5;
-    output fabric_mrepair_fuse_dout_o6;
-    output fabric_mrepair_fuse_dout_o7;
-    output fabric_mrepair_fuse_dout_o8;
-    output fabric_mrepair_fuse_dout_o9;
-    input fabric_mrepair_fuse_eccbypass_i;
-    output fabric_mrepair_fuse_flagstate_o1;
-    output fabric_mrepair_fuse_flagstate_o2;
-    output fabric_mrepair_fuse_flagstate_o3;
-    output fabric_mrepair_fuse_flagstate_o4;
-    output fabric_mrepair_fuse_locked_o;
-    input fabric_mrepair_fuse_pdn_i;
-    output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o;
-    input fabric_mrepair_fuse_prgwidth_i1;
-    input fabric_mrepair_fuse_prgwidth_i2;
-    input fabric_mrepair_fuse_prgwidth_i3;
-    input fabric_mrepair_fuse_prog_i;
-    output fabric_mrepair_fuse_progfail_o;
-    output fabric_mrepair_fuse_pwok_o;
-    input fabric_mrepair_fuse_rbact1_i;
-    input fabric_mrepair_fuse_rbact2_i;
-    input fabric_mrepair_fuse_read_i;
-    output fabric_mrepair_fuse_ready_o;
-    input fabric_mrepair_fuse_redbypass_i;
-    output fabric_mrepair_fuse_sec_o;
-    output fabric_mrepair_fuse_startword_o1;
-    output fabric_mrepair_fuse_startword_o10;
-    output fabric_mrepair_fuse_startword_o11;
-    output fabric_mrepair_fuse_startword_o12;
-    output fabric_mrepair_fuse_startword_o13;
-    output fabric_mrepair_fuse_startword_o14;
-    output fabric_mrepair_fuse_startword_o15;
-    output fabric_mrepair_fuse_startword_o16;
-    output fabric_mrepair_fuse_startword_o2;
-    output fabric_mrepair_fuse_startword_o3;
-    output fabric_mrepair_fuse_startword_o4;
-    output fabric_mrepair_fuse_startword_o5;
-    output fabric_mrepair_fuse_startword_o6;
-    output fabric_mrepair_fuse_startword_o7;
-    output fabric_mrepair_fuse_startword_o8;
-    output fabric_mrepair_fuse_startword_o9;
-    input fabric_mrepair_fuse_suppadd_i;
-    input fabric_mrepair_fuse_tm_i;
-    input fabric_mrepair_fuse_tst_scanin_i1;
-    input fabric_mrepair_fuse_tst_scanin_i2;
-    input fabric_mrepair_fuse_tst_scanin_i3;
-    input fabric_mrepair_fuse_tst_scanin_i4;
-    input fabric_mrepair_fuse_tst_scanin_i5;
-    input fabric_mrepair_fuse_tstscanenable_i;
-    output fabric_mrepair_fuse_tstscanout_o1;
-    output fabric_mrepair_fuse_tstscanout_o2;
-    output fabric_mrepair_fuse_tstscanout_o3;
-    output fabric_mrepair_fuse_tstscanout_o4;
-    output fabric_mrepair_fuse_tstscanout_o5;
-    output fabric_mrepair_fuse_wlromout_o1;
-    output fabric_mrepair_fuse_wlromout_o10;
-    output fabric_mrepair_fuse_wlromout_o2;
-    output fabric_mrepair_fuse_wlromout_o3;
-    output fabric_mrepair_fuse_wlromout_o4;
-    output fabric_mrepair_fuse_wlromout_o5;
-    output fabric_mrepair_fuse_wlromout_o6;
-    output fabric_mrepair_fuse_wlromout_o7;
-    output fabric_mrepair_fuse_wlromout_o8;
-    output fabric_mrepair_fuse_wlromout_o9;
-    input fabric_mrepair_fuse_wordlock_i;
-    input fabric_mrepair_initn_i;
-    input fabric_mrepair_mode_i1;
-    input fabric_mrepair_mode_i2;
-    input fabric_mrepair_mode_i3;
-    input fabric_mrepair_mode_i4;
-    input fabric_mrepair_por_i;
-    input fabric_mrepair_rst_n_i;
-    input fabric_otp_apb_addr_i1;
-    input fabric_otp_apb_addr_i10;
-    input fabric_otp_apb_addr_i11;
-    input fabric_otp_apb_addr_i12;
-    input fabric_otp_apb_addr_i13;
-    input fabric_otp_apb_addr_i14;
-    input fabric_otp_apb_addr_i15;
-    input fabric_otp_apb_addr_i16;
-    input fabric_otp_apb_addr_i17;
-    input fabric_otp_apb_addr_i18;
-    input fabric_otp_apb_addr_i19;
-    input fabric_otp_apb_addr_i2;
-    input fabric_otp_apb_addr_i20;
-    input fabric_otp_apb_addr_i21;
-    input fabric_otp_apb_addr_i22;
-    input fabric_otp_apb_addr_i23;
-    input fabric_otp_apb_addr_i24;
-    input fabric_otp_apb_addr_i25;
-    input fabric_otp_apb_addr_i26;
-    input fabric_otp_apb_addr_i27;
-    input fabric_otp_apb_addr_i28;
-    input fabric_otp_apb_addr_i29;
-    input fabric_otp_apb_addr_i3;
-    input fabric_otp_apb_addr_i30;
-    input fabric_otp_apb_addr_i31;
-    input fabric_otp_apb_addr_i32;
-    input fabric_otp_apb_addr_i4;
-    input fabric_otp_apb_addr_i5;
-    input fabric_otp_apb_addr_i6;
-    input fabric_otp_apb_addr_i7;
-    input fabric_otp_apb_addr_i8;
-    input fabric_otp_apb_addr_i9;
-    input fabric_otp_apb_enable_i;
-    output fabric_otp_apb_rdata_o1;
-    output fabric_otp_apb_rdata_o10;
-    output fabric_otp_apb_rdata_o11;
-    output fabric_otp_apb_rdata_o12;
-    output fabric_otp_apb_rdata_o13;
-    output fabric_otp_apb_rdata_o14;
-    output fabric_otp_apb_rdata_o15;
-    output fabric_otp_apb_rdata_o16;
-    output fabric_otp_apb_rdata_o17;
-    output fabric_otp_apb_rdata_o18;
-    output fabric_otp_apb_rdata_o19;
-    output fabric_otp_apb_rdata_o2;
-    output fabric_otp_apb_rdata_o20;
-    output fabric_otp_apb_rdata_o21;
-    output fabric_otp_apb_rdata_o22;
-    output fabric_otp_apb_rdata_o23;
-    output fabric_otp_apb_rdata_o24;
-    output fabric_otp_apb_rdata_o25;
-    output fabric_otp_apb_rdata_o26;
-    output fabric_otp_apb_rdata_o27;
-    output fabric_otp_apb_rdata_o28;
-    output fabric_otp_apb_rdata_o29;
-    output fabric_otp_apb_rdata_o3;
-    output fabric_otp_apb_rdata_o30;
-    output fabric_otp_apb_rdata_o31;
-    output fabric_otp_apb_rdata_o32;
-    output fabric_otp_apb_rdata_o4;
-    output fabric_otp_apb_rdata_o5;
-    output fabric_otp_apb_rdata_o6;
-    output fabric_otp_apb_rdata_o7;
-    output fabric_otp_apb_rdata_o8;
-    output fabric_otp_apb_rdata_o9;
-    output fabric_otp_apb_ready_o;
-    input fabric_otp_apb_sel_i;
-    input fabric_otp_apb_wdata_i1;
-    input fabric_otp_apb_wdata_i10;
-    input fabric_otp_apb_wdata_i11;
-    input fabric_otp_apb_wdata_i12;
-    input fabric_otp_apb_wdata_i13;
-    input fabric_otp_apb_wdata_i14;
-    input fabric_otp_apb_wdata_i15;
-    input fabric_otp_apb_wdata_i16;
-    input fabric_otp_apb_wdata_i17;
-    input fabric_otp_apb_wdata_i18;
-    input fabric_otp_apb_wdata_i19;
-    input fabric_otp_apb_wdata_i2;
-    input fabric_otp_apb_wdata_i20;
-    input fabric_otp_apb_wdata_i21;
-    input fabric_otp_apb_wdata_i22;
-    input fabric_otp_apb_wdata_i23;
-    input fabric_otp_apb_wdata_i24;
-    input fabric_otp_apb_wdata_i25;
-    input fabric_otp_apb_wdata_i26;
-    input fabric_otp_apb_wdata_i27;
-    input fabric_otp_apb_wdata_i28;
-    input fabric_otp_apb_wdata_i29;
-    input fabric_otp_apb_wdata_i3;
-    input fabric_otp_apb_wdata_i30;
-    input fabric_otp_apb_wdata_i31;
-    input fabric_otp_apb_wdata_i32;
-    input fabric_otp_apb_wdata_i4;
-    input fabric_otp_apb_wdata_i5;
-    input fabric_otp_apb_wdata_i6;
-    input fabric_otp_apb_wdata_i7;
-    input fabric_otp_apb_wdata_i8;
-    input fabric_otp_apb_wdata_i9;
-    input fabric_otp_apb_write_i;
-    input fabric_otp_cfg_clk_fab_en_i;
-    input fabric_otp_cfg_clk_otpm_disable_i;
-    input fabric_otp_cfg_fabric_apb_en_i;
-    input fabric_otp_cfg_loader_read_en_i;
-    input fabric_otp_cfg_loader_write_en_i;
-    input fabric_otp_rst_i;
-    output fabric_otp_security_ack_o;
-    output fabric_otp_security_bist_bad_o;
-    output fabric_otp_security_bist_end1_o;
-    output fabric_otp_security_bist_end2_o;
-    output fabric_otp_security_bist_fail1_o1;
-    output fabric_otp_security_bist_fail1_o2;
-    output fabric_otp_security_bist_fail1_o3;
-    output fabric_otp_security_bist_fail1_o4;
-    output fabric_otp_security_bist_fail1_o5;
-    output fabric_otp_security_bist_fail1_o6;
-    output fabric_otp_security_bist_fail1_o7;
-    output fabric_otp_security_bist_fail1_o8;
-    output fabric_otp_security_bist_fail2_o1;
-    output fabric_otp_security_bist_fail2_o2;
-    output fabric_otp_security_bist_fail2_o3;
-    output fabric_otp_security_bist_fail2_o4;
-    output fabric_otp_security_bist_fail2_o5;
-    output fabric_otp_security_bist_fail2_o6;
-    output fabric_otp_security_bist_fail2_o7;
-    input fabric_otp_security_bistmode_i;
-    input fabric_otp_security_force_pdn1_i;
-    input fabric_otp_security_rbact1_i;
-    input fabric_otp_security_rbact2_i;
-    input fabric_otp_security_scanenable_i;
-    input fabric_otp_security_scanin_i1;
-    input fabric_otp_security_scanin_i2;
-    input fabric_otp_security_scanin_i3;
-    input fabric_otp_security_scanin_i4;
-    input fabric_otp_security_scanin_i5;
-    output fabric_otp_security_scanout_o1;
-    output fabric_otp_security_scanout_o2;
-    output fabric_otp_security_scanout_o3;
-    output fabric_otp_security_scanout_o4;
-    output fabric_otp_security_scanout_o5;
-    input fabric_otp_security_testmode_i;
-    output fabric_otp_user_ack_o;
-    input fabric_otp_user_add_i1;
-    input fabric_otp_user_add_i2;
-    input fabric_otp_user_add_i3;
-    input fabric_otp_user_add_i4;
-    input fabric_otp_user_add_i5;
-    input fabric_otp_user_add_i6;
-    input fabric_otp_user_add_i7;
-    output fabric_otp_user_bbad_o;
-    output fabric_otp_user_bend1_o;
-    output fabric_otp_user_bend2_o;
-    output fabric_otp_user_bist1fail_o1;
-    output fabric_otp_user_bist1fail_o2;
-    output fabric_otp_user_bist1fail_o3;
-    output fabric_otp_user_bist1fail_o4;
-    output fabric_otp_user_bist1fail_o5;
-    output fabric_otp_user_bist1fail_o6;
-    output fabric_otp_user_bist1fail_o7;
-    output fabric_otp_user_bist1fail_o8;
-    output fabric_otp_user_bist2fail_o1;
-    output fabric_otp_user_bist2fail_o2;
-    output fabric_otp_user_bist2fail_o3;
-    output fabric_otp_user_bist2fail_o4;
-    output fabric_otp_user_bist2fail_o5;
-    output fabric_otp_user_bist2fail_o6;
-    output fabric_otp_user_bist2fail_o7;
-    input fabric_otp_user_bistmode_i;
-    output fabric_otp_user_calibrated_o;
-    input fabric_otp_user_clock_frequency_range_i;
-    output fabric_otp_user_ded_o;
-    input fabric_otp_user_din_i1;
-    input fabric_otp_user_din_i10;
-    input fabric_otp_user_din_i11;
-    input fabric_otp_user_din_i12;
-    input fabric_otp_user_din_i13;
-    input fabric_otp_user_din_i14;
-    input fabric_otp_user_din_i15;
-    input fabric_otp_user_din_i16;
-    input fabric_otp_user_din_i17;
-    input fabric_otp_user_din_i18;
-    input fabric_otp_user_din_i19;
-    input fabric_otp_user_din_i2;
-    input fabric_otp_user_din_i20;
-    input fabric_otp_user_din_i21;
-    input fabric_otp_user_din_i22;
-    input fabric_otp_user_din_i23;
-    input fabric_otp_user_din_i24;
-    input fabric_otp_user_din_i25;
-    input fabric_otp_user_din_i26;
-    input fabric_otp_user_din_i27;
-    input fabric_otp_user_din_i28;
-    input fabric_otp_user_din_i29;
-    input fabric_otp_user_din_i3;
-    input fabric_otp_user_din_i30;
-    input fabric_otp_user_din_i31;
-    input fabric_otp_user_din_i32;
-    input fabric_otp_user_din_i33;
-    input fabric_otp_user_din_i34;
-    input fabric_otp_user_din_i35;
-    input fabric_otp_user_din_i36;
-    input fabric_otp_user_din_i37;
-    input fabric_otp_user_din_i38;
-    input fabric_otp_user_din_i39;
-    input fabric_otp_user_din_i4;
-    input fabric_otp_user_din_i5;
-    input fabric_otp_user_din_i6;
-    input fabric_otp_user_din_i7;
-    input fabric_otp_user_din_i8;
-    input fabric_otp_user_din_i9;
-    input fabric_otp_user_disturbcheck_i;
-    output fabric_otp_user_disturbed_o;
-    output fabric_otp_user_dout_o1;
-    output fabric_otp_user_dout_o10;
-    output fabric_otp_user_dout_o11;
-    output fabric_otp_user_dout_o12;
-    output fabric_otp_user_dout_o13;
-    output fabric_otp_user_dout_o14;
-    output fabric_otp_user_dout_o15;
-    output fabric_otp_user_dout_o16;
-    output fabric_otp_user_dout_o17;
-    output fabric_otp_user_dout_o18;
-    output fabric_otp_user_dout_o19;
-    output fabric_otp_user_dout_o2;
-    output fabric_otp_user_dout_o20;
-    output fabric_otp_user_dout_o21;
-    output fabric_otp_user_dout_o22;
-    output fabric_otp_user_dout_o23;
-    output fabric_otp_user_dout_o24;
-    output fabric_otp_user_dout_o25;
-    output fabric_otp_user_dout_o26;
-    output fabric_otp_user_dout_o27;
-    output fabric_otp_user_dout_o28;
-    output fabric_otp_user_dout_o29;
-    output fabric_otp_user_dout_o3;
-    output fabric_otp_user_dout_o30;
-    output fabric_otp_user_dout_o31;
-    output fabric_otp_user_dout_o32;
-    output fabric_otp_user_dout_o33;
-    output fabric_otp_user_dout_o34;
-    output fabric_otp_user_dout_o35;
-    output fabric_otp_user_dout_o36;
-    output fabric_otp_user_dout_o37;
-    output fabric_otp_user_dout_o38;
-    output fabric_otp_user_dout_o39;
-    output fabric_otp_user_dout_o4;
-    output fabric_otp_user_dout_o40;
-    output fabric_otp_user_dout_o41;
-    output fabric_otp_user_dout_o5;
-    output fabric_otp_user_dout_o6;
-    output fabric_otp_user_dout_o7;
-    output fabric_otp_user_dout_o8;
-    output fabric_otp_user_dout_o9;
-    input fabric_otp_user_eccbypass_i;
-    output fabric_otp_user_flagstate_o1;
-    output fabric_otp_user_flagstate_o2;
-    output fabric_otp_user_flagstate_o3;
-    output fabric_otp_user_flagstate_o4;
-    output fabric_otp_user_locked_o;
-    input fabric_otp_user_pdn_i;
-    input fabric_otp_user_prgwidth_i1;
-    input fabric_otp_user_prgwidth_i2;
-    input fabric_otp_user_prgwidth_i3;
-    input fabric_otp_user_prog_i;
-    output fabric_otp_user_progfail_o;
-    output fabric_otp_user_pwok_o;
-    input fabric_otp_user_rbact1_i;
-    input fabric_otp_user_rbact2_i;
-    input fabric_otp_user_read_i;
-    input fabric_otp_user_redbypass_i;
-    output fabric_otp_user_sec_o;
-    output fabric_otp_user_startword_o1;
-    output fabric_otp_user_startword_o10;
-    output fabric_otp_user_startword_o11;
-    output fabric_otp_user_startword_o12;
-    output fabric_otp_user_startword_o13;
-    output fabric_otp_user_startword_o14;
-    output fabric_otp_user_startword_o15;
-    output fabric_otp_user_startword_o16;
-    output fabric_otp_user_startword_o2;
-    output fabric_otp_user_startword_o3;
-    output fabric_otp_user_startword_o4;
-    output fabric_otp_user_startword_o5;
-    output fabric_otp_user_startword_o6;
-    output fabric_otp_user_startword_o7;
-    output fabric_otp_user_startword_o8;
-    output fabric_otp_user_startword_o9;
-    input fabric_otp_user_suppadd_i;
-    input fabric_otp_user_tm_i;
-    input fabric_otp_user_tst_scanenable_i;
-    input fabric_otp_user_tst_scanin_i1;
-    input fabric_otp_user_tst_scanin_i2;
-    input fabric_otp_user_tst_scanin_i3;
-    input fabric_otp_user_tst_scanin_i4;
-    input fabric_otp_user_tst_scanin_i5;
-    output fabric_otp_user_tst_scanout_o1;
-    output fabric_otp_user_tst_scanout_o2;
-    output fabric_otp_user_tst_scanout_o3;
-    output fabric_otp_user_tst_scanout_o4;
-    output fabric_otp_user_tst_scanout_o5;
-    output fabric_otp_user_wlromout_o1;
-    output fabric_otp_user_wlromout_o10;
-    output fabric_otp_user_wlromout_o2;
-    output fabric_otp_user_wlromout_o3;
-    output fabric_otp_user_wlromout_o4;
-    output fabric_otp_user_wlromout_o5;
-    output fabric_otp_user_wlromout_o6;
-    output fabric_otp_user_wlromout_o7;
-    output fabric_otp_user_wlromout_o8;
-    output fabric_otp_user_wlromout_o9;
-    input fabric_otp_user_wordlock_i;
-    input fabric_parusr_cs_i;
-    input fabric_parusr_data_i1;
-    input fabric_parusr_data_i10;
-    input fabric_parusr_data_i11;
-    input fabric_parusr_data_i12;
-    input fabric_parusr_data_i13;
-    input fabric_parusr_data_i14;
-    input fabric_parusr_data_i15;
-    input fabric_parusr_data_i16;
-    input fabric_parusr_data_i2;
-    input fabric_parusr_data_i3;
-    input fabric_parusr_data_i4;
-    input fabric_parusr_data_i5;
-    input fabric_parusr_data_i6;
-    input fabric_parusr_data_i7;
-    input fabric_parusr_data_i8;
-    input fabric_parusr_data_i9;
-    output fabric_parusr_data_o1;
-    output fabric_parusr_data_o10;
-    output fabric_parusr_data_o11;
-    output fabric_parusr_data_o12;
-    output fabric_parusr_data_o13;
-    output fabric_parusr_data_o14;
-    output fabric_parusr_data_o15;
-    output fabric_parusr_data_o16;
-    output fabric_parusr_data_o2;
-    output fabric_parusr_data_o3;
-    output fabric_parusr_data_o4;
-    output fabric_parusr_data_o5;
-    output fabric_parusr_data_o6;
-    output fabric_parusr_data_o7;
-    output fabric_parusr_data_o8;
-    output fabric_parusr_data_o9;
-    output fabric_parusr_data_val_o;
-    input fabric_parusr_enable_i;
-    input fabric_parusr_type_i1;
-    input fabric_parusr_type_i2;
-    input fabric_pd_active_i1;
-    input fabric_pd_active_i10;
-    input fabric_pd_active_i11;
-    input fabric_pd_active_i12;
-    input fabric_pd_active_i13;
-    input fabric_pd_active_i14;
-    input fabric_pd_active_i15;
-    input fabric_pd_active_i16;
-    input fabric_pd_active_i17;
-    input fabric_pd_active_i18;
-    input fabric_pd_active_i19;
-    input fabric_pd_active_i2;
-    input fabric_pd_active_i20;
-    input fabric_pd_active_i21;
-    input fabric_pd_active_i22;
-    input fabric_pd_active_i23;
-    input fabric_pd_active_i24;
-    input fabric_pd_active_i3;
-    input fabric_pd_active_i4;
-    input fabric_pd_active_i5;
-    input fabric_pd_active_i6;
-    input fabric_pd_active_i7;
-    input fabric_pd_active_i8;
-    input fabric_pd_active_i9;
-    output fabric_pd_ready_o1;
-    output fabric_pd_ready_o10;
-    output fabric_pd_ready_o11;
-    output fabric_pd_ready_o12;
-    output fabric_pd_ready_o13;
-    output fabric_pd_ready_o14;
-    output fabric_pd_ready_o15;
-    output fabric_pd_ready_o16;
-    output fabric_pd_ready_o17;
-    output fabric_pd_ready_o18;
-    output fabric_pd_ready_o19;
-    output fabric_pd_ready_o2;
-    output fabric_pd_ready_o20;
-    output fabric_pd_ready_o21;
-    output fabric_pd_ready_o22;
-    output fabric_pd_ready_o23;
-    output fabric_pd_ready_o24;
-    output fabric_pd_ready_o3;
-    output fabric_pd_ready_o4;
-    output fabric_pd_ready_o5;
-    output fabric_pd_ready_o6;
-    output fabric_pd_ready_o7;
-    output fabric_pd_ready_o8;
-    output fabric_pd_ready_o9;
-    input fabric_shift_en_i1;
-    input fabric_shift_en_i10;
-    input fabric_shift_en_i11;
-    input fabric_shift_en_i12;
-    input fabric_shift_en_i13;
-    input fabric_shift_en_i14;
-    input fabric_shift_en_i15;
-    input fabric_shift_en_i16;
-    input fabric_shift_en_i17;
-    input fabric_shift_en_i18;
-    input fabric_shift_en_i19;
-    input fabric_shift_en_i2;
-    input fabric_shift_en_i20;
-    input fabric_shift_en_i21;
-    input fabric_shift_en_i22;
-    input fabric_shift_en_i23;
-    input fabric_shift_en_i24;
-    input fabric_shift_en_i3;
-    input fabric_shift_en_i4;
-    input fabric_shift_en_i5;
-    input fabric_shift_en_i6;
-    input fabric_shift_en_i7;
-    input fabric_shift_en_i8;
-    input fabric_shift_en_i9;
-    output fabric_shift_en_to_bist_o1;
-    output fabric_shift_en_to_bist_o10;
-    output fabric_shift_en_to_bist_o11;
-    output fabric_shift_en_to_bist_o12;
-    output fabric_shift_en_to_bist_o13;
-    output fabric_shift_en_to_bist_o14;
-    output fabric_shift_en_to_bist_o15;
-    output fabric_shift_en_to_bist_o16;
-    output fabric_shift_en_to_bist_o17;
-    output fabric_shift_en_to_bist_o18;
-    output fabric_shift_en_to_bist_o19;
-    output fabric_shift_en_to_bist_o2;
-    output fabric_shift_en_to_bist_o20;
-    output fabric_shift_en_to_bist_o21;
-    output fabric_shift_en_to_bist_o22;
-    output fabric_shift_en_to_bist_o23;
-    output fabric_shift_en_to_bist_o24;
-    output fabric_shift_en_to_bist_o3;
-    output fabric_shift_en_to_bist_o4;
-    output fabric_shift_en_to_bist_o5;
-    output fabric_shift_en_to_bist_o6;
-    output fabric_shift_en_to_bist_o7;
-    output fabric_shift_en_to_bist_o8;
-    output fabric_shift_en_to_bist_o9;
-    input fabric_sif_load_en_i1;
-    input fabric_sif_load_en_i10;
-    input fabric_sif_load_en_i11;
-    input fabric_sif_load_en_i12;
-    input fabric_sif_load_en_i13;
-    input fabric_sif_load_en_i14;
-    input fabric_sif_load_en_i15;
-    input fabric_sif_load_en_i16;
-    input fabric_sif_load_en_i17;
-    input fabric_sif_load_en_i18;
-    input fabric_sif_load_en_i19;
-    input fabric_sif_load_en_i2;
-    input fabric_sif_load_en_i20;
-    input fabric_sif_load_en_i21;
-    input fabric_sif_load_en_i22;
-    input fabric_sif_load_en_i23;
-    input fabric_sif_load_en_i24;
-    input fabric_sif_load_en_i3;
-    input fabric_sif_load_en_i4;
-    input fabric_sif_load_en_i5;
-    input fabric_sif_load_en_i6;
-    input fabric_sif_load_en_i7;
-    input fabric_sif_load_en_i8;
-    input fabric_sif_load_en_i9;
-    output fabric_sif_load_en_to_bist_o1;
-    output fabric_sif_load_en_to_bist_o10;
-    output fabric_sif_load_en_to_bist_o11;
-    output fabric_sif_load_en_to_bist_o12;
-    output fabric_sif_load_en_to_bist_o13;
-    output fabric_sif_load_en_to_bist_o14;
-    output fabric_sif_load_en_to_bist_o15;
-    output fabric_sif_load_en_to_bist_o16;
-    output fabric_sif_load_en_to_bist_o17;
-    output fabric_sif_load_en_to_bist_o18;
-    output fabric_sif_load_en_to_bist_o19;
-    output fabric_sif_load_en_to_bist_o2;
-    output fabric_sif_load_en_to_bist_o20;
-    output fabric_sif_load_en_to_bist_o21;
-    output fabric_sif_load_en_to_bist_o22;
-    output fabric_sif_load_en_to_bist_o23;
-    output fabric_sif_load_en_to_bist_o24;
-    output fabric_sif_load_en_to_bist_o3;
-    output fabric_sif_load_en_to_bist_o4;
-    output fabric_sif_load_en_to_bist_o5;
-    output fabric_sif_load_en_to_bist_o6;
-    output fabric_sif_load_en_to_bist_o7;
-    output fabric_sif_load_en_to_bist_o8;
-    output fabric_sif_load_en_to_bist_o9;
-    input fabric_sif_reg_en_i1;
-    input fabric_sif_reg_en_i10;
-    input fabric_sif_reg_en_i100;
-    input fabric_sif_reg_en_i101;
-    input fabric_sif_reg_en_i102;
-    input fabric_sif_reg_en_i103;
-    input fabric_sif_reg_en_i104;
-    input fabric_sif_reg_en_i105;
-    input fabric_sif_reg_en_i106;
-    input fabric_sif_reg_en_i107;
-    input fabric_sif_reg_en_i108;
-    input fabric_sif_reg_en_i109;
-    input fabric_sif_reg_en_i11;
-    input fabric_sif_reg_en_i110;
-    input fabric_sif_reg_en_i111;
-    input fabric_sif_reg_en_i112;
-    input fabric_sif_reg_en_i113;
-    input fabric_sif_reg_en_i114;
-    input fabric_sif_reg_en_i115;
-    input fabric_sif_reg_en_i116;
-    input fabric_sif_reg_en_i117;
-    input fabric_sif_reg_en_i118;
-    input fabric_sif_reg_en_i119;
-    input fabric_sif_reg_en_i12;
-    input fabric_sif_reg_en_i120;
-    input fabric_sif_reg_en_i13;
-    input fabric_sif_reg_en_i14;
-    input fabric_sif_reg_en_i15;
-    input fabric_sif_reg_en_i16;
-    input fabric_sif_reg_en_i17;
-    input fabric_sif_reg_en_i18;
-    input fabric_sif_reg_en_i19;
-    input fabric_sif_reg_en_i2;
-    input fabric_sif_reg_en_i20;
-    input fabric_sif_reg_en_i21;
-    input fabric_sif_reg_en_i22;
-    input fabric_sif_reg_en_i23;
-    input fabric_sif_reg_en_i24;
-    input fabric_sif_reg_en_i25;
-    input fabric_sif_reg_en_i26;
-    input fabric_sif_reg_en_i27;
-    input fabric_sif_reg_en_i28;
-    input fabric_sif_reg_en_i29;
-    input fabric_sif_reg_en_i3;
-    input fabric_sif_reg_en_i30;
-    input fabric_sif_reg_en_i31;
-    input fabric_sif_reg_en_i32;
-    input fabric_sif_reg_en_i33;
-    input fabric_sif_reg_en_i34;
-    input fabric_sif_reg_en_i35;
-    input fabric_sif_reg_en_i36;
-    input fabric_sif_reg_en_i37;
-    input fabric_sif_reg_en_i38;
-    input fabric_sif_reg_en_i39;
-    input fabric_sif_reg_en_i4;
-    input fabric_sif_reg_en_i40;
-    input fabric_sif_reg_en_i41;
-    input fabric_sif_reg_en_i42;
-    input fabric_sif_reg_en_i43;
-    input fabric_sif_reg_en_i44;
-    input fabric_sif_reg_en_i45;
-    input fabric_sif_reg_en_i46;
-    input fabric_sif_reg_en_i47;
-    input fabric_sif_reg_en_i48;
-    input fabric_sif_reg_en_i49;
-    input fabric_sif_reg_en_i5;
-    input fabric_sif_reg_en_i50;
-    input fabric_sif_reg_en_i51;
-    input fabric_sif_reg_en_i52;
-    input fabric_sif_reg_en_i53;
-    input fabric_sif_reg_en_i54;
-    input fabric_sif_reg_en_i55;
-    input fabric_sif_reg_en_i56;
-    input fabric_sif_reg_en_i57;
-    input fabric_sif_reg_en_i58;
-    input fabric_sif_reg_en_i59;
-    input fabric_sif_reg_en_i6;
-    input fabric_sif_reg_en_i60;
-    input fabric_sif_reg_en_i61;
-    input fabric_sif_reg_en_i62;
-    input fabric_sif_reg_en_i63;
-    input fabric_sif_reg_en_i64;
-    input fabric_sif_reg_en_i65;
-    input fabric_sif_reg_en_i66;
-    input fabric_sif_reg_en_i67;
-    input fabric_sif_reg_en_i68;
-    input fabric_sif_reg_en_i69;
-    input fabric_sif_reg_en_i7;
-    input fabric_sif_reg_en_i70;
-    input fabric_sif_reg_en_i71;
-    input fabric_sif_reg_en_i72;
-    input fabric_sif_reg_en_i73;
-    input fabric_sif_reg_en_i74;
-    input fabric_sif_reg_en_i75;
-    input fabric_sif_reg_en_i76;
-    input fabric_sif_reg_en_i77;
-    input fabric_sif_reg_en_i78;
-    input fabric_sif_reg_en_i79;
-    input fabric_sif_reg_en_i8;
-    input fabric_sif_reg_en_i80;
-    input fabric_sif_reg_en_i81;
-    input fabric_sif_reg_en_i82;
-    input fabric_sif_reg_en_i83;
-    input fabric_sif_reg_en_i84;
-    input fabric_sif_reg_en_i85;
-    input fabric_sif_reg_en_i86;
-    input fabric_sif_reg_en_i87;
-    input fabric_sif_reg_en_i88;
-    input fabric_sif_reg_en_i89;
-    input fabric_sif_reg_en_i9;
-    input fabric_sif_reg_en_i90;
-    input fabric_sif_reg_en_i91;
-    input fabric_sif_reg_en_i92;
-    input fabric_sif_reg_en_i93;
-    input fabric_sif_reg_en_i94;
-    input fabric_sif_reg_en_i95;
-    input fabric_sif_reg_en_i96;
-    input fabric_sif_reg_en_i97;
-    input fabric_sif_reg_en_i98;
-    input fabric_sif_reg_en_i99;
-    output fabric_sif_reg_en_to_bist_o1;
-    output fabric_sif_reg_en_to_bist_o10;
-    output fabric_sif_reg_en_to_bist_o100;
-    output fabric_sif_reg_en_to_bist_o101;
-    output fabric_sif_reg_en_to_bist_o102;
-    output fabric_sif_reg_en_to_bist_o103;
-    output fabric_sif_reg_en_to_bist_o104;
-    output fabric_sif_reg_en_to_bist_o105;
-    output fabric_sif_reg_en_to_bist_o106;
-    output fabric_sif_reg_en_to_bist_o107;
-    output fabric_sif_reg_en_to_bist_o108;
-    output fabric_sif_reg_en_to_bist_o109;
-    output fabric_sif_reg_en_to_bist_o11;
-    output fabric_sif_reg_en_to_bist_o110;
-    output fabric_sif_reg_en_to_bist_o111;
-    output fabric_sif_reg_en_to_bist_o112;
-    output fabric_sif_reg_en_to_bist_o113;
-    output fabric_sif_reg_en_to_bist_o114;
-    output fabric_sif_reg_en_to_bist_o115;
-    output fabric_sif_reg_en_to_bist_o116;
-    output fabric_sif_reg_en_to_bist_o117;
-    output fabric_sif_reg_en_to_bist_o118;
-    output fabric_sif_reg_en_to_bist_o119;
-    output fabric_sif_reg_en_to_bist_o12;
-    output fabric_sif_reg_en_to_bist_o120;
-    output fabric_sif_reg_en_to_bist_o13;
-    output fabric_sif_reg_en_to_bist_o14;
-    output fabric_sif_reg_en_to_bist_o15;
-    output fabric_sif_reg_en_to_bist_o16;
-    output fabric_sif_reg_en_to_bist_o17;
-    output fabric_sif_reg_en_to_bist_o18;
-    output fabric_sif_reg_en_to_bist_o19;
-    output fabric_sif_reg_en_to_bist_o2;
-    output fabric_sif_reg_en_to_bist_o20;
-    output fabric_sif_reg_en_to_bist_o21;
-    output fabric_sif_reg_en_to_bist_o22;
-    output fabric_sif_reg_en_to_bist_o23;
-    output fabric_sif_reg_en_to_bist_o24;
-    output fabric_sif_reg_en_to_bist_o25;
-    output fabric_sif_reg_en_to_bist_o26;
-    output fabric_sif_reg_en_to_bist_o27;
-    output fabric_sif_reg_en_to_bist_o28;
-    output fabric_sif_reg_en_to_bist_o29;
-    output fabric_sif_reg_en_to_bist_o3;
-    output fabric_sif_reg_en_to_bist_o30;
-    output fabric_sif_reg_en_to_bist_o31;
-    output fabric_sif_reg_en_to_bist_o32;
-    output fabric_sif_reg_en_to_bist_o33;
-    output fabric_sif_reg_en_to_bist_o34;
-    output fabric_sif_reg_en_to_bist_o35;
-    output fabric_sif_reg_en_to_bist_o36;
-    output fabric_sif_reg_en_to_bist_o37;
-    output fabric_sif_reg_en_to_bist_o38;
-    output fabric_sif_reg_en_to_bist_o39;
-    output fabric_sif_reg_en_to_bist_o4;
-    output fabric_sif_reg_en_to_bist_o40;
-    output fabric_sif_reg_en_to_bist_o41;
-    output fabric_sif_reg_en_to_bist_o42;
-    output fabric_sif_reg_en_to_bist_o43;
-    output fabric_sif_reg_en_to_bist_o44;
-    output fabric_sif_reg_en_to_bist_o45;
-    output fabric_sif_reg_en_to_bist_o46;
-    output fabric_sif_reg_en_to_bist_o47;
-    output fabric_sif_reg_en_to_bist_o48;
-    output fabric_sif_reg_en_to_bist_o49;
-    output fabric_sif_reg_en_to_bist_o5;
-    output fabric_sif_reg_en_to_bist_o50;
-    output fabric_sif_reg_en_to_bist_o51;
-    output fabric_sif_reg_en_to_bist_o52;
-    output fabric_sif_reg_en_to_bist_o53;
-    output fabric_sif_reg_en_to_bist_o54;
-    output fabric_sif_reg_en_to_bist_o55;
-    output fabric_sif_reg_en_to_bist_o56;
-    output fabric_sif_reg_en_to_bist_o57;
-    output fabric_sif_reg_en_to_bist_o58;
-    output fabric_sif_reg_en_to_bist_o59;
-    output fabric_sif_reg_en_to_bist_o6;
-    output fabric_sif_reg_en_to_bist_o60;
-    output fabric_sif_reg_en_to_bist_o61;
-    output fabric_sif_reg_en_to_bist_o62;
-    output fabric_sif_reg_en_to_bist_o63;
-    output fabric_sif_reg_en_to_bist_o64;
-    output fabric_sif_reg_en_to_bist_o65;
-    output fabric_sif_reg_en_to_bist_o66;
-    output fabric_sif_reg_en_to_bist_o67;
-    output fabric_sif_reg_en_to_bist_o68;
-    output fabric_sif_reg_en_to_bist_o69;
-    output fabric_sif_reg_en_to_bist_o7;
-    output fabric_sif_reg_en_to_bist_o70;
-    output fabric_sif_reg_en_to_bist_o71;
-    output fabric_sif_reg_en_to_bist_o72;
-    output fabric_sif_reg_en_to_bist_o73;
-    output fabric_sif_reg_en_to_bist_o74;
-    output fabric_sif_reg_en_to_bist_o75;
-    output fabric_sif_reg_en_to_bist_o76;
-    output fabric_sif_reg_en_to_bist_o77;
-    output fabric_sif_reg_en_to_bist_o78;
-    output fabric_sif_reg_en_to_bist_o79;
-    output fabric_sif_reg_en_to_bist_o8;
-    output fabric_sif_reg_en_to_bist_o80;
-    output fabric_sif_reg_en_to_bist_o81;
-    output fabric_sif_reg_en_to_bist_o82;
-    output fabric_sif_reg_en_to_bist_o83;
-    output fabric_sif_reg_en_to_bist_o84;
-    output fabric_sif_reg_en_to_bist_o85;
-    output fabric_sif_reg_en_to_bist_o86;
-    output fabric_sif_reg_en_to_bist_o87;
-    output fabric_sif_reg_en_to_bist_o88;
-    output fabric_sif_reg_en_to_bist_o89;
-    output fabric_sif_reg_en_to_bist_o9;
-    output fabric_sif_reg_en_to_bist_o90;
-    output fabric_sif_reg_en_to_bist_o91;
-    output fabric_sif_reg_en_to_bist_o92;
-    output fabric_sif_reg_en_to_bist_o93;
-    output fabric_sif_reg_en_to_bist_o94;
-    output fabric_sif_reg_en_to_bist_o95;
-    output fabric_sif_reg_en_to_bist_o96;
-    output fabric_sif_reg_en_to_bist_o97;
-    output fabric_sif_reg_en_to_bist_o98;
-    output fabric_sif_reg_en_to_bist_o99;
-    input fabric_sif_update_en_i1;
-    input fabric_sif_update_en_i10;
-    input fabric_sif_update_en_i11;
-    input fabric_sif_update_en_i12;
-    input fabric_sif_update_en_i13;
-    input fabric_sif_update_en_i14;
-    input fabric_sif_update_en_i15;
-    input fabric_sif_update_en_i16;
-    input fabric_sif_update_en_i17;
-    input fabric_sif_update_en_i18;
-    input fabric_sif_update_en_i19;
-    input fabric_sif_update_en_i2;
-    input fabric_sif_update_en_i20;
-    input fabric_sif_update_en_i21;
-    input fabric_sif_update_en_i22;
-    input fabric_sif_update_en_i23;
-    input fabric_sif_update_en_i24;
-    input fabric_sif_update_en_i3;
-    input fabric_sif_update_en_i4;
-    input fabric_sif_update_en_i5;
-    input fabric_sif_update_en_i6;
-    input fabric_sif_update_en_i7;
-    input fabric_sif_update_en_i8;
-    input fabric_sif_update_en_i9;
-    output fabric_sif_update_en_to_bist_o1;
-    output fabric_sif_update_en_to_bist_o10;
-    output fabric_sif_update_en_to_bist_o11;
-    output fabric_sif_update_en_to_bist_o12;
-    output fabric_sif_update_en_to_bist_o13;
-    output fabric_sif_update_en_to_bist_o14;
-    output fabric_sif_update_en_to_bist_o15;
-    output fabric_sif_update_en_to_bist_o16;
-    output fabric_sif_update_en_to_bist_o17;
-    output fabric_sif_update_en_to_bist_o18;
-    output fabric_sif_update_en_to_bist_o19;
-    output fabric_sif_update_en_to_bist_o2;
-    output fabric_sif_update_en_to_bist_o20;
-    output fabric_sif_update_en_to_bist_o21;
-    output fabric_sif_update_en_to_bist_o22;
-    output fabric_sif_update_en_to_bist_o23;
-    output fabric_sif_update_en_to_bist_o24;
-    output fabric_sif_update_en_to_bist_o3;
-    output fabric_sif_update_en_to_bist_o4;
-    output fabric_sif_update_en_to_bist_o5;
-    output fabric_sif_update_en_to_bist_o6;
-    output fabric_sif_update_en_to_bist_o7;
-    output fabric_sif_update_en_to_bist_o8;
-    output fabric_sif_update_en_to_bist_o9;
-    output fabric_status_cold_start_o;
-    output fabric_system_data_from_mem_bist_o1;
-    output fabric_system_data_from_mem_bist_o10;
-    output fabric_system_data_from_mem_bist_o11;
-    output fabric_system_data_from_mem_bist_o12;
-    output fabric_system_data_from_mem_bist_o13;
-    output fabric_system_data_from_mem_bist_o14;
-    output fabric_system_data_from_mem_bist_o15;
-    output fabric_system_data_from_mem_bist_o16;
-    output fabric_system_data_from_mem_bist_o17;
-    output fabric_system_data_from_mem_bist_o18;
-    output fabric_system_data_from_mem_bist_o19;
-    output fabric_system_data_from_mem_bist_o2;
-    output fabric_system_data_from_mem_bist_o20;
-    output fabric_system_data_from_mem_bist_o21;
-    output fabric_system_data_from_mem_bist_o22;
-    output fabric_system_data_from_mem_bist_o23;
-    output fabric_system_data_from_mem_bist_o24;
-    output fabric_system_data_from_mem_bist_o3;
-    output fabric_system_data_from_mem_bist_o4;
-    output fabric_system_data_from_mem_bist_o5;
-    output fabric_system_data_from_mem_bist_o6;
-    output fabric_system_data_from_mem_bist_o7;
-    output fabric_system_data_from_mem_bist_o8;
-    output fabric_system_data_from_mem_bist_o9;
-    input fabric_system_data_to_mem_bist_i1;
-    input fabric_system_data_to_mem_bist_i10;
-    input fabric_system_data_to_mem_bist_i11;
-    input fabric_system_data_to_mem_bist_i12;
-    input fabric_system_data_to_mem_bist_i13;
-    input fabric_system_data_to_mem_bist_i14;
-    input fabric_system_data_to_mem_bist_i15;
-    input fabric_system_data_to_mem_bist_i16;
-    input fabric_system_data_to_mem_bist_i17;
-    input fabric_system_data_to_mem_bist_i18;
-    input fabric_system_data_to_mem_bist_i19;
-    input fabric_system_data_to_mem_bist_i2;
-    input fabric_system_data_to_mem_bist_i20;
-    input fabric_system_data_to_mem_bist_i21;
-    input fabric_system_data_to_mem_bist_i22;
-    input fabric_system_data_to_mem_bist_i23;
-    input fabric_system_data_to_mem_bist_i24;
-    input fabric_system_data_to_mem_bist_i3;
-    input fabric_system_data_to_mem_bist_i4;
-    input fabric_system_data_to_mem_bist_i5;
-    input fabric_system_data_to_mem_bist_i6;
-    input fabric_system_data_to_mem_bist_i7;
-    input fabric_system_data_to_mem_bist_i8;
-    input fabric_system_data_to_mem_bist_i9;
-    output fabric_system_dataready_o;
-    input fabric_tst_atpg_mrepair_i;
-    input fabric_user_data_i1;
-    input fabric_user_data_i10;
-    input fabric_user_data_i11;
-    input fabric_user_data_i12;
-    input fabric_user_data_i13;
-    input fabric_user_data_i14;
-    input fabric_user_data_i15;
-    input fabric_user_data_i16;
-    input fabric_user_data_i17;
-    input fabric_user_data_i18;
-    input fabric_user_data_i19;
-    input fabric_user_data_i2;
-    input fabric_user_data_i20;
-    input fabric_user_data_i21;
-    input fabric_user_data_i22;
-    input fabric_user_data_i23;
-    input fabric_user_data_i24;
-    input fabric_user_data_i25;
-    input fabric_user_data_i26;
-    input fabric_user_data_i27;
-    input fabric_user_data_i28;
-    input fabric_user_data_i29;
-    input fabric_user_data_i3;
-    input fabric_user_data_i30;
-    input fabric_user_data_i31;
-    input fabric_user_data_i32;
-    input fabric_user_data_i4;
-    input fabric_user_data_i5;
-    input fabric_user_data_i6;
-    input fabric_user_data_i7;
-    input fabric_user_data_i8;
-    input fabric_user_data_i9;
-    output fabric_user_data_o1;
-    output fabric_user_data_o10;
-    output fabric_user_data_o11;
-    output fabric_user_data_o12;
-    output fabric_user_data_o13;
-    output fabric_user_data_o14;
-    output fabric_user_data_o15;
-    output fabric_user_data_o16;
-    output fabric_user_data_o17;
-    output fabric_user_data_o18;
-    output fabric_user_data_o19;
-    output fabric_user_data_o2;
-    output fabric_user_data_o20;
-    output fabric_user_data_o21;
-    output fabric_user_data_o22;
-    output fabric_user_data_o23;
-    output fabric_user_data_o24;
-    output fabric_user_data_o25;
-    output fabric_user_data_o26;
-    output fabric_user_data_o27;
-    output fabric_user_data_o28;
-    output fabric_user_data_o29;
-    output fabric_user_data_o3;
-    output fabric_user_data_o30;
-    output fabric_user_data_o31;
-    output fabric_user_data_o32;
-    output fabric_user_data_o4;
-    output fabric_user_data_o5;
-    output fabric_user_data_o6;
-    output fabric_user_data_o7;
-    output fabric_user_data_o8;
-    output fabric_user_data_o9;
-    output fabric_user_read_cycle_o;
-    output fabric_user_write_cycle_o;
-    parameter ahb_config = 0;
-    parameter bsm_config = 0;
-endmodule
-
-(* blackbox *)
-module NX_SERVICE_U_V1(fabric_otp_user_tst_scanenable_i, fabric_otp_cfg_loader_read_en_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_scanenable_i, fabric_otp_user_din_i1, fabric_otp_user_din_i2, fabric_otp_user_din_i3, fabric_otp_user_din_i4, fabric_otp_user_din_i5, fabric_otp_user_din_i6, fabric_otp_user_din_i7, fabric_otp_user_din_i8, fabric_otp_user_din_i9, fabric_otp_user_din_i10, fabric_otp_user_din_i11, fabric_otp_user_din_i12, fabric_otp_user_din_i13, fabric_otp_user_din_i14, fabric_otp_user_din_i15, fabric_otp_user_din_i16, fabric_otp_user_din_i17
-, fabric_otp_user_din_i18, fabric_otp_user_din_i19, fabric_otp_user_din_i20, fabric_otp_user_din_i21, fabric_otp_user_din_i22, fabric_otp_user_din_i23, fabric_otp_user_din_i24, fabric_otp_user_din_i25, fabric_otp_user_din_i26, fabric_otp_user_din_i27, fabric_otp_user_din_i28, fabric_otp_user_din_i29, fabric_otp_user_din_i30, fabric_otp_user_din_i31, fabric_otp_user_din_i32, fabric_otp_user_din_i33, fabric_otp_user_din_i34, fabric_otp_user_din_i35, fabric_otp_user_din_i36, fabric_otp_user_din_i37, fabric_otp_user_din_i38
-, fabric_otp_user_din_i39, fabric_mrepair_fuse_prgwidth_i1, fabric_mrepair_fuse_prgwidth_i2, fabric_mrepair_fuse_prgwidth_i3, fabric_otp_apb_wdata_i1, fabric_otp_apb_wdata_i2, fabric_otp_apb_wdata_i3, fabric_otp_apb_wdata_i4, fabric_otp_apb_wdata_i5, fabric_otp_apb_wdata_i6, fabric_otp_apb_wdata_i7, fabric_otp_apb_wdata_i8, fabric_otp_apb_wdata_i9, fabric_otp_apb_wdata_i10, fabric_otp_apb_wdata_i11, fabric_otp_apb_wdata_i12, fabric_otp_apb_wdata_i13, fabric_otp_apb_wdata_i14, fabric_otp_apb_wdata_i15, fabric_otp_apb_wdata_i16, fabric_otp_apb_wdata_i17
-, fabric_otp_apb_wdata_i18, fabric_otp_apb_wdata_i19, fabric_otp_apb_wdata_i20, fabric_otp_apb_wdata_i21, fabric_otp_apb_wdata_i22, fabric_otp_apb_wdata_i23, fabric_otp_apb_wdata_i24, fabric_otp_apb_wdata_i25, fabric_otp_apb_wdata_i26, fabric_otp_apb_wdata_i27, fabric_otp_apb_wdata_i28, fabric_otp_apb_wdata_i29, fabric_otp_apb_wdata_i30, fabric_otp_apb_wdata_i31, fabric_otp_apb_wdata_i32, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_user_disturbcheck_i, fabric_mrepair_fuse_read_i, fabric_otp_user_rbact2_i, fabric_mrepair_fuse_eccbypass_i, fabric_otp_user_bistmode_i
-, fabric_otp_user_add_i1, fabric_otp_user_add_i2, fabric_otp_user_add_i3, fabric_otp_user_add_i4, fabric_otp_user_add_i5, fabric_otp_user_add_i6, fabric_otp_user_add_i7, fabric_otp_user_tm_i, fabric_otp_rstn_i, fabric_mrepair_fuse_disturbchecked_i, fabric_otp_user_rbact1_i, fabric_mrepair_fuse_tst_scanin_i1, fabric_mrepair_fuse_tst_scanin_i2, fabric_mrepair_fuse_tst_scanin_i3, fabric_mrepair_fuse_tst_scanin_i4, fabric_mrepair_fuse_tst_scanin_i5, fabric_parusr_type_i1, fabric_parusr_type_i2, fabric_mrepair_fuse_redbypass_i, fabric_otp_user_eccbypass_i, fabric_otp_user_redbypass_i
-, fabric_mrepair_mode_i1, fabric_mrepair_mode_i2, fabric_mrepair_mode_i3, fabric_mrepair_mode_i4, fabric_parusr_cs_i, fabric_sif_reg_en_i1, fabric_sif_reg_en_i2, fabric_sif_reg_en_i3, fabric_sif_reg_en_i4, fabric_sif_reg_en_i5, fabric_sif_reg_en_i6, fabric_sif_reg_en_i7, fabric_sif_reg_en_i8, fabric_sif_reg_en_i9, fabric_sif_reg_en_i10, fabric_sif_reg_en_i11, fabric_sif_reg_en_i12, fabric_sif_reg_en_i13, fabric_sif_reg_en_i14, fabric_sif_reg_en_i15, fabric_sif_reg_en_i16
-, fabric_sif_reg_en_i17, fabric_sif_reg_en_i18, fabric_sif_reg_en_i19, fabric_sif_reg_en_i20, fabric_sif_reg_en_i21, fabric_sif_reg_en_i22, fabric_sif_reg_en_i23, fabric_sif_reg_en_i24, fabric_sif_reg_en_i25, fabric_sif_reg_en_i26, fabric_sif_reg_en_i27, fabric_sif_reg_en_i28, fabric_sif_reg_en_i29, fabric_sif_reg_en_i30, fabric_sif_reg_en_i31, fabric_sif_reg_en_i32, fabric_sif_reg_en_i33, fabric_sif_reg_en_i34, fabric_sif_reg_en_i35, fabric_sif_reg_en_i36, fabric_sif_reg_en_i37
-, fabric_sif_reg_en_i38, fabric_sif_reg_en_i39, fabric_sif_reg_en_i40, fabric_sif_reg_en_i41, fabric_sif_reg_en_i42, fabric_sif_reg_en_i43, fabric_sif_reg_en_i44, fabric_sif_reg_en_i45, fabric_sif_reg_en_i46, fabric_sif_reg_en_i47, fabric_sif_reg_en_i48, fabric_sif_reg_en_i49, fabric_sif_reg_en_i50, fabric_sif_reg_en_i51, fabric_sif_reg_en_i52, fabric_sif_reg_en_i53, fabric_sif_reg_en_i54, fabric_sif_reg_en_i55, fabric_sif_reg_en_i56, fabric_sif_reg_en_i57, fabric_sif_reg_en_i58
-, fabric_sif_reg_en_i59, fabric_sif_reg_en_i60, fabric_sif_reg_en_i61, fabric_sif_reg_en_i62, fabric_sif_reg_en_i63, fabric_sif_reg_en_i64, fabric_sif_reg_en_i65, fabric_sif_reg_en_i66, fabric_sif_reg_en_i67, fabric_sif_reg_en_i68, fabric_sif_reg_en_i69, fabric_sif_reg_en_i70, fabric_sif_reg_en_i71, fabric_sif_reg_en_i72, fabric_sif_reg_en_i73, fabric_sif_reg_en_i74, fabric_sif_reg_en_i75, fabric_sif_reg_en_i76, fabric_sif_reg_en_i77, fabric_sif_reg_en_i78, fabric_sif_reg_en_i79
-, fabric_sif_reg_en_i80, fabric_sif_reg_en_i81, fabric_sif_reg_en_i82, fabric_sif_reg_en_i83, fabric_sif_reg_en_i84, fabric_sif_reg_en_i85, fabric_sif_reg_en_i86, fabric_sif_reg_en_i87, fabric_sif_reg_en_i88, fabric_sif_reg_en_i89, fabric_sif_reg_en_i90, fabric_sif_reg_en_i91, fabric_sif_reg_en_i92, fabric_sif_reg_en_i93, fabric_sif_reg_en_i94, fabric_sif_reg_en_i95, fabric_sif_reg_en_i96, fabric_sif_reg_en_i97, fabric_sif_reg_en_i98, fabric_sif_reg_en_i99, fabric_sif_reg_en_i100
-, fabric_sif_reg_en_i101, fabric_sif_reg_en_i102, fabric_sif_reg_en_i103, fabric_sif_reg_en_i104, fabric_sif_reg_en_i105, fabric_sif_reg_en_i106, fabric_sif_reg_en_i107, fabric_sif_reg_en_i108, fabric_sif_reg_en_i109, fabric_sif_reg_en_i110, fabric_sif_reg_en_i111, fabric_sif_reg_en_i112, fabric_sif_reg_en_i113, fabric_sif_reg_en_i114, fabric_sif_reg_en_i115, fabric_sif_reg_en_i116, fabric_sif_reg_en_i117, fabric_sif_reg_en_i118, fabric_sif_reg_en_i119, fabric_sif_reg_en_i120, fabric_mrepair_fuse_rbact2_i
-, fabric_data_from_system_i, fabric_data_from_bist_i1, fabric_data_from_bist_i2, fabric_data_from_bist_i3, fabric_data_from_bist_i4, fabric_data_from_bist_i5, fabric_data_from_bist_i6, fabric_data_from_bist_i7, fabric_data_from_bist_i8, fabric_data_from_bist_i9, fabric_data_from_bist_i10, fabric_data_from_bist_i11, fabric_data_from_bist_i12, fabric_data_from_bist_i13, fabric_data_from_bist_i14, fabric_data_from_bist_i15, fabric_data_from_bist_i16, fabric_data_from_bist_i17, fabric_data_from_bist_i18, fabric_data_from_bist_i19, fabric_data_from_bist_i20
-, fabric_data_from_bist_i21, fabric_data_from_bist_i22, fabric_data_from_bist_i23, fabric_data_from_bist_i24, fabric_otp_apb_enable_i, fabric_mrepair_fuse_tm_i, fabric_otp_security_rbact2_i, fabric_otp_security_rbact1_i, fabric_shift_en_i1, fabric_shift_en_i2, fabric_shift_en_i3, fabric_shift_en_i4, fabric_shift_en_i5, fabric_shift_en_i6, fabric_shift_en_i7, fabric_shift_en_i8, fabric_shift_en_i9, fabric_shift_en_i10, fabric_shift_en_i11, fabric_shift_en_i12, fabric_shift_en_i13
-, fabric_shift_en_i14, fabric_shift_en_i15, fabric_shift_en_i16, fabric_shift_en_i17, fabric_shift_en_i18, fabric_shift_en_i19, fabric_shift_en_i20, fabric_shift_en_i21, fabric_shift_en_i22, fabric_shift_en_i23, fabric_shift_en_i24, fabric_otp_cfg_loader_write_en_i, fabric_user_data_i1, fabric_user_data_i2, fabric_user_data_i3, fabric_user_data_i4, fabric_user_data_i5, fabric_user_data_i6, fabric_user_data_i7, fabric_user_data_i8, fabric_user_data_i9
-, fabric_user_data_i10, fabric_user_data_i11, fabric_user_data_i12, fabric_user_data_i13, fabric_user_data_i14, fabric_user_data_i15, fabric_user_data_i16, fabric_user_data_i17, fabric_user_data_i18, fabric_user_data_i19, fabric_user_data_i20, fabric_user_data_i21, fabric_user_data_i22, fabric_user_data_i23, fabric_user_data_i24, fabric_user_data_i25, fabric_user_data_i26, fabric_user_data_i27, fabric_user_data_i28, fabric_user_data_i29, fabric_user_data_i30
-, fabric_user_data_i31, fabric_user_data_i32, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_prog_i, fabric_otp_user_wordlock_i, fabric_ahb_direct_data_i1, fabric_ahb_direct_data_i2, fabric_ahb_direct_data_i3, fabric_ahb_direct_data_i4, fabric_ahb_direct_data_i5, fabric_ahb_direct_data_i6, fabric_ahb_direct_data_i7, fabric_ahb_direct_data_i8, fabric_ahb_direct_data_i9, fabric_ahb_direct_data_i10, fabric_ahb_direct_data_i11, fabric_ahb_direct_data_i12, fabric_ahb_direct_data_i13, fabric_ahb_direct_data_i14, fabric_ahb_direct_data_i15, fabric_ahb_direct_data_i16
-, fabric_ahb_direct_data_i17, fabric_ahb_direct_data_i18, fabric_ahb_direct_data_i19, fabric_ahb_direct_data_i20, fabric_ahb_direct_data_i21, fabric_ahb_direct_data_i22, fabric_ahb_direct_data_i23, fabric_ahb_direct_data_i24, fabric_ahb_direct_data_i25, fabric_ahb_direct_data_i26, fabric_ahb_direct_data_i27, fabric_ahb_direct_data_i28, fabric_ahb_direct_data_i29, fabric_ahb_direct_data_i30, fabric_ahb_direct_data_i31, fabric_ahb_direct_data_i32, fabric_otp_user_prog_i, fabric_pd_active_i1, fabric_pd_active_i2, fabric_pd_active_i3, fabric_pd_active_i4
-, fabric_pd_active_i5, fabric_pd_active_i6, fabric_pd_active_i7, fabric_pd_active_i8, fabric_pd_active_i9, fabric_pd_active_i10, fabric_pd_active_i11, fabric_pd_active_i12, fabric_pd_active_i13, fabric_pd_active_i14, fabric_pd_active_i15, fabric_pd_active_i16, fabric_pd_active_i17, fabric_pd_active_i18, fabric_pd_active_i19, fabric_pd_active_i20, fabric_pd_active_i21, fabric_pd_active_i22, fabric_pd_active_i23, fabric_pd_active_i24, fabric_otp_user_suppadd_i
-, fabric_mrepair_fuse_pdn_i, fabric_otp_security_scanin_i1, fabric_otp_security_scanin_i2, fabric_otp_security_scanin_i3, fabric_otp_security_scanin_i4, fabric_otp_security_scanin_i5, fabric_end_encoding_i, fabric_jtag_tdo_usr2_i, fabric_mrepair_fuse_wordlock_i, fabric_otp_user_prgwidth_i1, fabric_otp_user_prgwidth_i2, fabric_otp_user_prgwidth_i3, fabric_otp_user_read_i, fabric_mrepair_fuse_add_i1, fabric_mrepair_fuse_add_i2, fabric_mrepair_fuse_add_i3, fabric_mrepair_fuse_add_i4, fabric_mrepair_fuse_add_i5, fabric_mrepair_fuse_add_i6, fabric_mrepair_fuse_add_i7, fabric_mrepair_fuse_bistmode_i
-, fabric_jtag_tdo_usr1_i, fabric_otp_cfg_clk_fab_en_i, fabric_io_in_i1, fabric_io_in_i2, fabric_io_in_i3, fabric_io_in_i4, fabric_io_in_i5, fabric_io_in_i6, fabric_io_in_i7, fabric_io_in_i8, fabric_io_in_i9, fabric_io_in_i10, fabric_io_in_i11, fabric_io_in_i12, fabric_io_in_i13, fabric_io_in_i14, fabric_io_in_i15, fabric_io_in_i16, fabric_io_in_i17, fabric_io_in_i18, fabric_io_in_i19
-, fabric_io_in_i20, fabric_io_in_i21, fabric_io_in_i22, fabric_io_in_i23, fabric_io_in_i24, fabric_io_in_i25, fabric_sif_load_en_i1, fabric_sif_load_en_i2, fabric_sif_load_en_i3, fabric_sif_load_en_i4, fabric_sif_load_en_i5, fabric_sif_load_en_i6, fabric_sif_load_en_i7, fabric_sif_load_en_i8, fabric_sif_load_en_i9, fabric_sif_load_en_i10, fabric_sif_load_en_i11, fabric_sif_load_en_i12, fabric_sif_load_en_i13, fabric_sif_load_en_i14, fabric_sif_load_en_i15
-, fabric_sif_load_en_i16, fabric_sif_load_en_i17, fabric_sif_load_en_i18, fabric_sif_load_en_i19, fabric_sif_load_en_i20, fabric_sif_load_en_i21, fabric_sif_load_en_i22, fabric_sif_load_en_i23, fabric_sif_load_en_i24, fabric_mrepair_fuse_din_i1, fabric_mrepair_fuse_din_i2, fabric_mrepair_fuse_din_i3, fabric_mrepair_fuse_din_i4, fabric_mrepair_fuse_din_i5, fabric_mrepair_fuse_din_i6, fabric_mrepair_fuse_din_i7, fabric_mrepair_fuse_din_i8, fabric_mrepair_fuse_din_i9, fabric_mrepair_fuse_din_i10, fabric_mrepair_fuse_din_i11, fabric_mrepair_fuse_din_i12
-, fabric_mrepair_fuse_din_i13, fabric_mrepair_fuse_din_i14, fabric_mrepair_fuse_din_i15, fabric_mrepair_fuse_din_i16, fabric_mrepair_fuse_din_i17, fabric_mrepair_fuse_din_i18, fabric_mrepair_fuse_din_i19, fabric_mrepair_fuse_din_i20, fabric_mrepair_fuse_din_i21, fabric_mrepair_fuse_din_i22, fabric_mrepair_fuse_din_i23, fabric_mrepair_fuse_din_i24, fabric_mrepair_fuse_din_i25, fabric_mrepair_fuse_din_i26, fabric_mrepair_fuse_din_i27, fabric_mrepair_fuse_din_i28, fabric_mrepair_fuse_din_i29, fabric_mrepair_fuse_din_i30, fabric_mrepair_fuse_din_i31, fabric_mrepair_fuse_din_i32, fabric_mrepair_fuse_din_i33
-, fabric_mrepair_fuse_din_i34, fabric_mrepair_fuse_din_i35, fabric_mrepair_fuse_din_i36, fabric_mrepair_fuse_din_i37, fabric_mrepair_fuse_din_i38, fabric_mrepair_fuse_din_i39, fabric_otp_apb_addr_i1, fabric_otp_apb_addr_i2, fabric_otp_apb_addr_i3, fabric_otp_apb_addr_i4, fabric_otp_apb_addr_i5, fabric_otp_apb_addr_i6, fabric_otp_apb_addr_i7, fabric_otp_apb_addr_i8, fabric_otp_apb_addr_i9, fabric_otp_apb_addr_i10, fabric_otp_apb_addr_i11, fabric_otp_apb_addr_i12, fabric_otp_apb_addr_i13, fabric_otp_apb_addr_i14, fabric_otp_apb_addr_i15
-, fabric_otp_apb_addr_i16, fabric_otp_apb_addr_i17, fabric_otp_apb_addr_i18, fabric_otp_apb_addr_i19, fabric_otp_apb_addr_i20, fabric_otp_apb_addr_i21, fabric_otp_apb_addr_i22, fabric_otp_apb_addr_i23, fabric_otp_apb_addr_i24, fabric_otp_apb_addr_i25, fabric_otp_apb_addr_i26, fabric_otp_apb_addr_i27, fabric_otp_apb_addr_i28, fabric_otp_apb_addr_i29, fabric_otp_apb_addr_i30, fabric_otp_apb_addr_i31, fabric_otp_apb_addr_i32, fabric_otp_apb_sel_i, fabric_mrepair_fuse_rbact1_i, fabric_mrepair_fuse_configreg_i1, fabric_mrepair_fuse_configreg_i2
-, fabric_mrepair_fuse_configreg_i3, fabric_mrepair_fuse_configreg_i4, fabric_mrepair_fuse_configreg_i5, fabric_mrepair_fuse_configreg_i6, fabric_mrepair_fuse_configreg_i7, fabric_mrepair_fuse_configreg_i8, fabric_mrepair_fuse_configreg_i9, fabric_mrepair_fuse_configreg_i10, fabric_mrepair_fuse_configreg_i11, fabric_mrepair_fuse_configreg_i12, fabric_mrepair_fuse_configreg_i13, fabric_mrepair_fuse_configreg_i14, fabric_mrepair_fuse_configreg_i15, fabric_mrepair_fuse_configreg_i16, fabric_mrepair_fuse_configreg_i17, fabric_mrepair_fuse_configreg_i18, fabric_mrepair_fuse_configreg_i19, fabric_mrepair_fuse_configreg_i20, fabric_mrepair_fuse_configreg_i21, fabric_mrepair_fuse_configreg_i22, fabric_mrepair_fuse_configreg_i23
-, fabric_mrepair_fuse_configreg_i24, fabric_mrepair_fuse_configreg_i25, fabric_mrepair_fuse_configreg_i26, fabric_mrepair_fuse_configreg_i27, fabric_mrepair_fuse_configreg_i28, fabric_mrepair_fuse_configreg_i29, fabric_mrepair_fuse_configreg_i30, fabric_mrepair_fuse_configreg_i31, fabric_mrepair_fuse_configreg_i32, fabric_otp_cfg_fabric_apb_en_i, fabric_data_shift_en_i, fabric_lowskew_i21, fabric_direct_data_i1, fabric_direct_data_i2, fabric_direct_data_i3, fabric_direct_data_i4, fabric_direct_data_i5, fabric_direct_data_i6, fabric_direct_data_i7, fabric_direct_data_i8, fabric_direct_data_i9
-, fabric_direct_data_i10, fabric_direct_data_i11, fabric_direct_data_i12, fabric_direct_data_i13, fabric_direct_data_i14, fabric_direct_data_i15, fabric_direct_data_i16, fabric_direct_data_i17, fabric_direct_data_i18, fabric_direct_data_i19, fabric_direct_data_i20, fabric_direct_data_i21, fabric_direct_data_i22, fabric_direct_data_i23, fabric_direct_data_i24, fabric_direct_data_i25, fabric_direct_data_i26, fabric_direct_data_i27, fabric_direct_data_i28, fabric_direct_data_i29, fabric_direct_data_i30
-, fabric_direct_data_i31, fabric_direct_data_i32, fabric_otp_user_pdn_i, fabric_io_oe_i1, fabric_io_oe_i2, fabric_io_oe_i3, fabric_io_oe_i4, fabric_io_oe_i5, fabric_io_oe_i6, fabric_io_oe_i7, fabric_io_oe_i8, fabric_io_oe_i9, fabric_io_oe_i10, fabric_io_oe_i11, fabric_io_oe_i12, fabric_io_oe_i13, fabric_io_oe_i14, fabric_io_oe_i15, fabric_io_oe_i16, fabric_io_oe_i17, fabric_io_oe_i18
-, fabric_io_oe_i19, fabric_io_oe_i20, fabric_io_oe_i21, fabric_io_oe_i22, fabric_io_oe_i23, fabric_io_oe_i24, fabric_io_oe_i25, fabric_parusr_data_i1, fabric_parusr_data_i2, fabric_parusr_data_i3, fabric_parusr_data_i4, fabric_parusr_data_i5, fabric_parusr_data_i6, fabric_parusr_data_i7, fabric_parusr_data_i8, fabric_parusr_data_i9, fabric_parusr_data_i10, fabric_parusr_data_i11, fabric_parusr_data_i12, fabric_parusr_data_i13, fabric_parusr_data_i14
-, fabric_parusr_data_i15, fabric_parusr_data_i16, fabric_otp_apb_write_i, fabric_otp_security_testmode_i, fabric_system_data_to_mem_bist_i1, fabric_system_data_to_mem_bist_i2, fabric_system_data_to_mem_bist_i3, fabric_system_data_to_mem_bist_i4, fabric_system_data_to_mem_bist_i5, fabric_system_data_to_mem_bist_i6, fabric_system_data_to_mem_bist_i7, fabric_system_data_to_mem_bist_i8, fabric_system_data_to_mem_bist_i9, fabric_system_data_to_mem_bist_i10, fabric_system_data_to_mem_bist_i11, fabric_system_data_to_mem_bist_i12, fabric_system_data_to_mem_bist_i13, fabric_system_data_to_mem_bist_i14, fabric_system_data_to_mem_bist_i15, fabric_system_data_to_mem_bist_i16, fabric_system_data_to_mem_bist_i17
-, fabric_system_data_to_mem_bist_i18, fabric_system_data_to_mem_bist_i19, fabric_system_data_to_mem_bist_i20, fabric_system_data_to_mem_bist_i21, fabric_system_data_to_mem_bist_i22, fabric_system_data_to_mem_bist_i23, fabric_system_data_to_mem_bist_i24, fabric_tst_atpg_mrepair_i, fabric_mrepair_fuse_tstscanenable_i, fabric_otp_security_bistmode_i, fabric_lowskew_i22, fabric_lowskew_i23, fabric_lowskew_i20, fabric_otp_user_configreg_i1, fabric_otp_user_configreg_i2, fabric_otp_user_configreg_i3, fabric_otp_user_configreg_i4, fabric_otp_user_configreg_i5, fabric_otp_user_configreg_i6, fabric_otp_user_configreg_i7, fabric_otp_user_configreg_i8
-, fabric_otp_user_configreg_i9, fabric_otp_user_configreg_i10, fabric_otp_user_configreg_i11, fabric_otp_user_configreg_i12, fabric_otp_user_configreg_i13, fabric_otp_user_configreg_i14, fabric_otp_user_configreg_i15, fabric_otp_user_configreg_i16, fabric_otp_user_configreg_i17, fabric_otp_user_configreg_i18, fabric_otp_user_configreg_i19, fabric_otp_user_configreg_i20, fabric_otp_user_configreg_i21, fabric_otp_user_configreg_i22, fabric_otp_user_configreg_i23, fabric_otp_user_configreg_i24, fabric_otp_user_configreg_i25, fabric_otp_user_configreg_i26, fabric_otp_user_configreg_i27, fabric_otp_user_configreg_i28, fabric_otp_user_configreg_i29
-, fabric_otp_user_configreg_i30, fabric_otp_user_configreg_i31, fabric_otp_user_configreg_i32, fabric_otp_user_tst_scanin_i1, fabric_otp_user_tst_scanin_i2, fabric_otp_user_tst_scanin_i3, fabric_otp_user_tst_scanin_i4, fabric_otp_user_tst_scanin_i5, fabric_sif_update_en_i1, fabric_sif_update_en_i2, fabric_sif_update_en_i3, fabric_sif_update_en_i4, fabric_sif_update_en_i5, fabric_sif_update_en_i6, fabric_sif_update_en_i7, fabric_sif_update_en_i8, fabric_sif_update_en_i9, fabric_sif_update_en_i10, fabric_sif_update_en_i11, fabric_sif_update_en_i12, fabric_sif_update_en_i13
-, fabric_sif_update_en_i14, fabric_sif_update_en_i15, fabric_sif_update_en_i16, fabric_sif_update_en_i17, fabric_sif_update_en_i18, fabric_sif_update_en_i19, fabric_sif_update_en_i20, fabric_sif_update_en_i21, fabric_sif_update_en_i22, fabric_sif_update_en_i23, fabric_sif_update_en_i24, fabric_mrepair_por_i, fabric_mrepair_rst_n_i, fabric_mrepair_initn_i, fabric_spare_i1, fabric_spare_i2, fabric_spare_i3, fabric_mrepair_fuse_bbad_o, fabric_jtag_trst_n_o, fabric_debug_direct_permission_write_o1, fabric_debug_direct_permission_write_o2
-, fabric_debug_direct_permission_write_o3, fabric_debug_direct_permission_write_o4, fabric_otp_security_bist_end1_o, fabric_parusr_data_val_o, fabric_debug_lock_reg_o, fabric_debug_security_error_read_o, fabric_mrepair_fuse_tstscanout_o1, fabric_mrepair_fuse_tstscanout_o2, fabric_mrepair_fuse_tstscanout_o3, fabric_mrepair_fuse_tstscanout_o4, fabric_mrepair_fuse_tstscanout_o5, fabric_otp_user_tst_scanout_o1, fabric_otp_user_tst_scanout_o2, fabric_otp_user_tst_scanout_o3, fabric_otp_user_tst_scanout_o4, fabric_otp_user_tst_scanout_o5, fabric_sif_update_en_to_bist_o1, fabric_sif_update_en_to_bist_o2, fabric_sif_update_en_to_bist_o3, fabric_sif_update_en_to_bist_o4, fabric_sif_update_en_to_bist_o5
-, fabric_sif_update_en_to_bist_o6, fabric_sif_update_en_to_bist_o7, fabric_sif_update_en_to_bist_o8, fabric_sif_update_en_to_bist_o9, fabric_sif_update_en_to_bist_o10, fabric_sif_update_en_to_bist_o11, fabric_sif_update_en_to_bist_o12, fabric_sif_update_en_to_bist_o13, fabric_sif_update_en_to_bist_o14, fabric_sif_update_en_to_bist_o15, fabric_sif_update_en_to_bist_o16, fabric_sif_update_en_to_bist_o17, fabric_sif_update_en_to_bist_o18, fabric_sif_update_en_to_bist_o19, fabric_sif_update_en_to_bist_o20, fabric_sif_update_en_to_bist_o21, fabric_sif_update_en_to_bist_o22, fabric_sif_update_en_to_bist_o23, fabric_sif_update_en_to_bist_o24, fabric_otp_user_locked_o, fabric_otp_security_bist_bad_o
-, fabric_debug_frame_permission_frame_o1, fabric_debug_frame_permission_frame_o2, fabric_debug_frame_permission_frame_o3, fabric_debug_frame_permission_frame_o4, fabric_otp_user_pwok_o, fabric_otp_user_bend2_o, fabric_mrepair_fuse_ded_o, fabric_debug_access_reg_data_ready_o, fabric_data_to_bist_o1, fabric_data_to_bist_o2, fabric_data_to_bist_o3, fabric_data_to_bist_o4, fabric_data_to_bist_o5, fabric_data_to_bist_o6, fabric_data_to_bist_o7, fabric_data_to_bist_o8, fabric_data_to_bist_o9, fabric_data_to_bist_o10, fabric_data_to_bist_o11, fabric_data_to_bist_o12, fabric_data_to_bist_o13
-, fabric_data_to_bist_o14, fabric_data_to_bist_o15, fabric_data_to_bist_o16, fabric_data_to_bist_o17, fabric_data_to_bist_o18, fabric_data_to_bist_o19, fabric_data_to_bist_o20, fabric_data_to_bist_o21, fabric_data_to_bist_o22, fabric_data_to_bist_o23, fabric_data_to_bist_o24, fabric_otp_user_startword_o1, fabric_otp_user_startword_o2, fabric_otp_user_startword_o3, fabric_otp_user_startword_o4, fabric_otp_user_startword_o5, fabric_otp_user_startword_o6, fabric_otp_user_startword_o7, fabric_otp_user_startword_o8, fabric_otp_user_startword_o9, fabric_otp_user_startword_o10
-, fabric_otp_user_startword_o11, fabric_otp_user_startword_o12, fabric_otp_user_startword_o13, fabric_otp_user_startword_o14, fabric_otp_user_startword_o15, fabric_otp_user_startword_o16, fabric_ahb_direct_data_o1, fabric_ahb_direct_data_o2, fabric_ahb_direct_data_o3, fabric_ahb_direct_data_o4, fabric_ahb_direct_data_o5, fabric_ahb_direct_data_o6, fabric_ahb_direct_data_o7, fabric_ahb_direct_data_o8, fabric_ahb_direct_data_o9, fabric_ahb_direct_data_o10, fabric_ahb_direct_data_o11, fabric_ahb_direct_data_o12, fabric_ahb_direct_data_o13, fabric_ahb_direct_data_o14, fabric_ahb_direct_data_o15
-, fabric_ahb_direct_data_o16, fabric_ahb_direct_data_o17, fabric_ahb_direct_data_o18, fabric_ahb_direct_data_o19, fabric_ahb_direct_data_o20, fabric_ahb_direct_data_o21, fabric_ahb_direct_data_o22, fabric_ahb_direct_data_o23, fabric_ahb_direct_data_o24, fabric_ahb_direct_data_o25, fabric_ahb_direct_data_o26, fabric_ahb_direct_data_o27, fabric_ahb_direct_data_o28, fabric_ahb_direct_data_o29, fabric_ahb_direct_data_o30, fabric_ahb_direct_data_o31, fabric_ahb_direct_data_o32, fabric_parusr_data_o1, fabric_parusr_data_o2, fabric_parusr_data_o3, fabric_parusr_data_o4
-, fabric_parusr_data_o5, fabric_parusr_data_o6, fabric_parusr_data_o7, fabric_parusr_data_o8, fabric_parusr_data_o9, fabric_parusr_data_o10, fabric_parusr_data_o11, fabric_parusr_data_o12, fabric_parusr_data_o13, fabric_parusr_data_o14, fabric_parusr_data_o15, fabric_parusr_data_o16, fabric_debug_otp_reload_err_o, fabric_cfg_fabric_user_unmask_o, fabric_decoder_init_ready_o, fabric_global_chip_status_o1, fabric_global_chip_status_o2, fabric_global_chip_status_o3, fabric_debug_security_boot_done_o, fabric_otp_user_calibrated_o, fabric_fuse_status_o1
-, fabric_fuse_status_o2, fabric_fuse_status_o3, fabric_otp_apb_rdata_o1, fabric_otp_apb_rdata_o2, fabric_otp_apb_rdata_o3, fabric_otp_apb_rdata_o4, fabric_otp_apb_rdata_o5, fabric_otp_apb_rdata_o6, fabric_otp_apb_rdata_o7, fabric_otp_apb_rdata_o8, fabric_otp_apb_rdata_o9, fabric_otp_apb_rdata_o10, fabric_otp_apb_rdata_o11, fabric_otp_apb_rdata_o12, fabric_otp_apb_rdata_o13, fabric_otp_apb_rdata_o14, fabric_otp_apb_rdata_o15, fabric_otp_apb_rdata_o16, fabric_otp_apb_rdata_o17, fabric_otp_apb_rdata_o18, fabric_otp_apb_rdata_o19
-, fabric_otp_apb_rdata_o20, fabric_otp_apb_rdata_o21, fabric_otp_apb_rdata_o22, fabric_otp_apb_rdata_o23, fabric_otp_apb_rdata_o24, fabric_otp_apb_rdata_o25, fabric_otp_apb_rdata_o26, fabric_otp_apb_rdata_o27, fabric_otp_apb_rdata_o28, fabric_otp_apb_rdata_o29, fabric_otp_apb_rdata_o30, fabric_otp_apb_rdata_o31, fabric_otp_apb_rdata_o32, fabric_jtag_tms_o, fabric_debug_bsec_core_status_o1, fabric_debug_bsec_core_status_o2, fabric_debug_bsec_core_status_o3, fabric_debug_bsec_core_status_o4, fabric_debug_bsec_core_status_o5, fabric_debug_bsec_core_status_o6, fabric_debug_bsec_core_status_o7
-, fabric_debug_bsec_core_status_o8, fabric_debug_bsec_core_status_o9, fabric_debug_bsec_core_status_o10, fabric_debug_bsec_core_status_o11, fabric_debug_bsec_core_status_o12, fabric_debug_bsec_core_status_o13, fabric_debug_bsec_core_status_o14, fabric_debug_bsec_core_status_o15, fabric_debug_bsec_core_status_o16, fabric_debug_bsec_core_status_o17, fabric_debug_bsec_core_status_o18, fabric_debug_bsec_core_status_o19, fabric_debug_bsec_core_status_o20, fabric_debug_bsec_core_status_o21, fabric_debug_bsec_core_status_o22, fabric_debug_bsec_core_status_o23, fabric_debug_bsec_core_status_o24, fabric_debug_bsec_core_status_o25, fabric_debug_bsec_core_status_o26, fabric_debug_bsec_core_status_o27, fabric_debug_bsec_core_status_o28
-, fabric_debug_bsec_core_status_o29, fabric_debug_bsec_core_status_o30, fabric_debug_bsec_core_status_o31, fabric_debug_bsec_core_status_o32, fabric_mrepair_fuse_bist1fail_o1, fabric_mrepair_fuse_bist1fail_o2, fabric_mrepair_fuse_bist1fail_o3, fabric_mrepair_fuse_bist1fail_o4, fabric_mrepair_fuse_bist1fail_o5, fabric_mrepair_fuse_bist1fail_o6, fabric_mrepair_fuse_bist1fail_o7, fabric_mrepair_fuse_bist1fail_o8, fabric_flag_ready_o, fabric_mrepair_fuse_dout_o1, fabric_mrepair_fuse_dout_o2, fabric_mrepair_fuse_dout_o3, fabric_mrepair_fuse_dout_o4, fabric_mrepair_fuse_dout_o5, fabric_mrepair_fuse_dout_o6, fabric_mrepair_fuse_dout_o7, fabric_mrepair_fuse_dout_o8
-, fabric_mrepair_fuse_dout_o9, fabric_mrepair_fuse_dout_o10, fabric_mrepair_fuse_dout_o11, fabric_mrepair_fuse_dout_o12, fabric_mrepair_fuse_dout_o13, fabric_mrepair_fuse_dout_o14, fabric_mrepair_fuse_dout_o15, fabric_mrepair_fuse_dout_o16, fabric_mrepair_fuse_dout_o17, fabric_mrepair_fuse_dout_o18, fabric_mrepair_fuse_dout_o19, fabric_mrepair_fuse_dout_o20, fabric_mrepair_fuse_dout_o21, fabric_mrepair_fuse_dout_o22, fabric_mrepair_fuse_dout_o23, fabric_mrepair_fuse_dout_o24, fabric_mrepair_fuse_dout_o25, fabric_mrepair_fuse_dout_o26, fabric_mrepair_fuse_dout_o27, fabric_mrepair_fuse_dout_o28, fabric_mrepair_fuse_dout_o29
-, fabric_mrepair_fuse_dout_o30, fabric_mrepair_fuse_dout_o31, fabric_mrepair_fuse_dout_o32, fabric_mrepair_fuse_dout_o33, fabric_mrepair_fuse_dout_o34, fabric_mrepair_fuse_dout_o35, fabric_mrepair_fuse_dout_o36, fabric_mrepair_fuse_dout_o37, fabric_mrepair_fuse_dout_o38, fabric_mrepair_fuse_dout_o39, fabric_mrepair_fuse_dout_o40, fabric_mrepair_fuse_dout_o41, fabric_debug_rst_soft_o, fabric_otp_user_ack_o, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_shift_en_to_bist_o1, fabric_shift_en_to_bist_o2, fabric_shift_en_to_bist_o3, fabric_shift_en_to_bist_o4, fabric_shift_en_to_bist_o5, fabric_shift_en_to_bist_o6
-, fabric_shift_en_to_bist_o7, fabric_shift_en_to_bist_o8, fabric_shift_en_to_bist_o9, fabric_shift_en_to_bist_o10, fabric_shift_en_to_bist_o11, fabric_shift_en_to_bist_o12, fabric_shift_en_to_bist_o13, fabric_shift_en_to_bist_o14, fabric_shift_en_to_bist_o15, fabric_shift_en_to_bist_o16, fabric_shift_en_to_bist_o17, fabric_shift_en_to_bist_o18, fabric_shift_en_to_bist_o19, fabric_shift_en_to_bist_o20, fabric_shift_en_to_bist_o21, fabric_shift_en_to_bist_o22, fabric_shift_en_to_bist_o23, fabric_shift_en_to_bist_o24, fabric_sif_reg_en_to_bist_o1, fabric_sif_reg_en_to_bist_o2, fabric_sif_reg_en_to_bist_o3
-, fabric_sif_reg_en_to_bist_o4, fabric_sif_reg_en_to_bist_o5, fabric_sif_reg_en_to_bist_o6, fabric_sif_reg_en_to_bist_o7, fabric_sif_reg_en_to_bist_o8, fabric_sif_reg_en_to_bist_o9, fabric_sif_reg_en_to_bist_o10, fabric_sif_reg_en_to_bist_o11, fabric_sif_reg_en_to_bist_o12, fabric_sif_reg_en_to_bist_o13, fabric_sif_reg_en_to_bist_o14, fabric_sif_reg_en_to_bist_o15, fabric_sif_reg_en_to_bist_o16, fabric_sif_reg_en_to_bist_o17, fabric_sif_reg_en_to_bist_o18, fabric_sif_reg_en_to_bist_o19, fabric_sif_reg_en_to_bist_o20, fabric_sif_reg_en_to_bist_o21, fabric_sif_reg_en_to_bist_o22, fabric_sif_reg_en_to_bist_o23, fabric_sif_reg_en_to_bist_o24
-, fabric_sif_reg_en_to_bist_o25, fabric_sif_reg_en_to_bist_o26, fabric_sif_reg_en_to_bist_o27, fabric_sif_reg_en_to_bist_o28, fabric_sif_reg_en_to_bist_o29, fabric_sif_reg_en_to_bist_o30, fabric_sif_reg_en_to_bist_o31, fabric_sif_reg_en_to_bist_o32, fabric_sif_reg_en_to_bist_o33, fabric_sif_reg_en_to_bist_o34, fabric_sif_reg_en_to_bist_o35, fabric_sif_reg_en_to_bist_o36, fabric_sif_reg_en_to_bist_o37, fabric_sif_reg_en_to_bist_o38, fabric_sif_reg_en_to_bist_o39, fabric_sif_reg_en_to_bist_o40, fabric_sif_reg_en_to_bist_o41, fabric_sif_reg_en_to_bist_o42, fabric_sif_reg_en_to_bist_o43, fabric_sif_reg_en_to_bist_o44, fabric_sif_reg_en_to_bist_o45
-, fabric_sif_reg_en_to_bist_o46, fabric_sif_reg_en_to_bist_o47, fabric_sif_reg_en_to_bist_o48, fabric_sif_reg_en_to_bist_o49, fabric_sif_reg_en_to_bist_o50, fabric_sif_reg_en_to_bist_o51, fabric_sif_reg_en_to_bist_o52, fabric_sif_reg_en_to_bist_o53, fabric_sif_reg_en_to_bist_o54, fabric_sif_reg_en_to_bist_o55, fabric_sif_reg_en_to_bist_o56, fabric_sif_reg_en_to_bist_o57, fabric_sif_reg_en_to_bist_o58, fabric_sif_reg_en_to_bist_o59, fabric_sif_reg_en_to_bist_o60, fabric_sif_reg_en_to_bist_o61, fabric_sif_reg_en_to_bist_o62, fabric_sif_reg_en_to_bist_o63, fabric_sif_reg_en_to_bist_o64, fabric_sif_reg_en_to_bist_o65, fabric_sif_reg_en_to_bist_o66
-, fabric_sif_reg_en_to_bist_o67, fabric_sif_reg_en_to_bist_o68, fabric_sif_reg_en_to_bist_o69, fabric_sif_reg_en_to_bist_o70, fabric_sif_reg_en_to_bist_o71, fabric_sif_reg_en_to_bist_o72, fabric_sif_reg_en_to_bist_o73, fabric_sif_reg_en_to_bist_o74, fabric_sif_reg_en_to_bist_o75, fabric_sif_reg_en_to_bist_o76, fabric_sif_reg_en_to_bist_o77, fabric_sif_reg_en_to_bist_o78, fabric_sif_reg_en_to_bist_o79, fabric_sif_reg_en_to_bist_o80, fabric_sif_reg_en_to_bist_o81, fabric_sif_reg_en_to_bist_o82, fabric_sif_reg_en_to_bist_o83, fabric_sif_reg_en_to_bist_o84, fabric_sif_reg_en_to_bist_o85, fabric_sif_reg_en_to_bist_o86, fabric_sif_reg_en_to_bist_o87
-, fabric_sif_reg_en_to_bist_o88, fabric_sif_reg_en_to_bist_o89, fabric_sif_reg_en_to_bist_o90, fabric_sif_reg_en_to_bist_o91, fabric_sif_reg_en_to_bist_o92, fabric_sif_reg_en_to_bist_o93, fabric_sif_reg_en_to_bist_o94, fabric_sif_reg_en_to_bist_o95, fabric_sif_reg_en_to_bist_o96, fabric_sif_reg_en_to_bist_o97, fabric_sif_reg_en_to_bist_o98, fabric_sif_reg_en_to_bist_o99, fabric_sif_reg_en_to_bist_o100, fabric_sif_reg_en_to_bist_o101, fabric_sif_reg_en_to_bist_o102, fabric_sif_reg_en_to_bist_o103, fabric_sif_reg_en_to_bist_o104, fabric_sif_reg_en_to_bist_o105, fabric_sif_reg_en_to_bist_o106, fabric_sif_reg_en_to_bist_o107, fabric_sif_reg_en_to_bist_o108
-, fabric_sif_reg_en_to_bist_o109, fabric_sif_reg_en_to_bist_o110, fabric_sif_reg_en_to_bist_o111, fabric_sif_reg_en_to_bist_o112, fabric_sif_reg_en_to_bist_o113, fabric_sif_reg_en_to_bist_o114, fabric_sif_reg_en_to_bist_o115, fabric_sif_reg_en_to_bist_o116, fabric_sif_reg_en_to_bist_o117, fabric_sif_reg_en_to_bist_o118, fabric_sif_reg_en_to_bist_o119, fabric_sif_reg_en_to_bist_o120, fabric_debug_otp_manager_read_otp_o, fabric_otp_user_sec_o, fabric_otp_user_wlromout_o1, fabric_otp_user_wlromout_o2, fabric_otp_user_wlromout_o3, fabric_otp_user_wlromout_o4, fabric_otp_user_wlromout_o5, fabric_otp_user_wlromout_o6, fabric_otp_user_wlromout_o7
-, fabric_otp_user_wlromout_o8, fabric_otp_user_wlromout_o9, fabric_otp_user_wlromout_o10, fabric_mrepair_fuse_bend1_o, fabric_mrepair_fuse_flagstate_o1, fabric_mrepair_fuse_flagstate_o2, fabric_mrepair_fuse_flagstate_o3, fabric_mrepair_fuse_flagstate_o4, fabric_system_data_from_mem_bist_o1, fabric_system_data_from_mem_bist_o2, fabric_system_data_from_mem_bist_o3, fabric_system_data_from_mem_bist_o4, fabric_system_data_from_mem_bist_o5, fabric_system_data_from_mem_bist_o6, fabric_system_data_from_mem_bist_o7, fabric_system_data_from_mem_bist_o8, fabric_system_data_from_mem_bist_o9, fabric_system_data_from_mem_bist_o10, fabric_system_data_from_mem_bist_o11, fabric_system_data_from_mem_bist_o12, fabric_system_data_from_mem_bist_o13
-, fabric_system_data_from_mem_bist_o14, fabric_system_data_from_mem_bist_o15, fabric_system_data_from_mem_bist_o16, fabric_system_data_from_mem_bist_o17, fabric_system_data_from_mem_bist_o18, fabric_system_data_from_mem_bist_o19, fabric_system_data_from_mem_bist_o20, fabric_system_data_from_mem_bist_o21, fabric_system_data_from_mem_bist_o22, fabric_system_data_from_mem_bist_o23, fabric_system_data_from_mem_bist_o24, fabric_direct_data_o1, fabric_direct_data_o2, fabric_direct_data_o3, fabric_direct_data_o4, fabric_direct_data_o5, fabric_direct_data_o6, fabric_direct_data_o7, fabric_direct_data_o8, fabric_direct_data_o9, fabric_direct_data_o10
-, fabric_direct_data_o11, fabric_direct_data_o12, fabric_direct_data_o13, fabric_direct_data_o14, fabric_direct_data_o15, fabric_direct_data_o16, fabric_direct_data_o17, fabric_direct_data_o18, fabric_direct_data_o19, fabric_direct_data_o20, fabric_direct_data_o21, fabric_direct_data_o22, fabric_direct_data_o23, fabric_direct_data_o24, fabric_direct_data_o25, fabric_direct_data_o26, fabric_direct_data_o27, fabric_direct_data_o28, fabric_direct_data_o29, fabric_direct_data_o30, fabric_direct_data_o31
-, fabric_direct_data_o32, fabric_otp_user_bbad_o, fabric_user_read_cycle_o, fabric_chip_status_o1, fabric_chip_status_o2, fabric_chip_status_o3, fabric_chip_status_o4, fabric_chip_status_o5, fabric_chip_status_o6, fabric_chip_status_o7, fabric_chip_status_o8, fabric_chip_status_o9, fabric_chip_status_o10, fabric_chip_status_o11, fabric_chip_status_o12, fabric_chip_status_o13, fabric_chip_status_o14, fabric_chip_status_o15, fabric_chip_status_o16, fabric_chip_status_o17, fabric_chip_status_o18
-, fabric_chip_status_o19, fabric_chip_status_o20, fabric_chip_status_o21, fabric_chip_status_o22, fabric_chip_status_o23, fabric_chip_status_o24, fabric_chip_status_o25, fabric_chip_status_o26, fabric_chip_status_o27, fabric_chip_status_o28, fabric_chip_status_o29, fabric_chip_status_o30, fabric_chip_status_o31, fabric_chip_status_o32, fabric_chip_status_o33, fabric_chip_status_o34, fabric_chip_status_o35, fabric_chip_status_o36, fabric_chip_status_o37, fabric_chip_status_o38, fabric_chip_status_o39
-, fabric_chip_status_o40, fabric_chip_status_o41, fabric_chip_status_o42, fabric_chip_status_o43, fabric_chip_status_o44, fabric_chip_status_o45, fabric_chip_status_o46, fabric_chip_status_o47, fabric_chip_status_o48, fabric_chip_status_o49, fabric_chip_status_o50, fabric_chip_status_o51, fabric_chip_status_o52, fabric_chip_status_o53, fabric_chip_status_o54, fabric_chip_status_o55, fabric_chip_status_o56, fabric_chip_status_o57, fabric_chip_status_o58, fabric_chip_status_o59, fabric_chip_status_o60
-, fabric_chip_status_o61, fabric_chip_status_o62, fabric_chip_status_o63, fabric_chip_status_o64, fabric_chip_status_o65, fabric_chip_status_o66, fabric_chip_status_o67, fabric_chip_status_o68, fabric_chip_status_o69, fabric_chip_status_o70, fabric_chip_status_o71, fabric_chip_status_o72, fabric_mrepair_fuse_disturbed_o, fabric_debug_otpboot_state_o1, fabric_debug_otpboot_state_o2, fabric_debug_otpboot_state_o3, fabric_pd_ready_o1, fabric_pd_ready_o2, fabric_pd_ready_o3, fabric_pd_ready_o4, fabric_pd_ready_o5
-, fabric_pd_ready_o6, fabric_pd_ready_o7, fabric_pd_ready_o8, fabric_pd_ready_o9, fabric_pd_ready_o10, fabric_pd_ready_o11, fabric_pd_ready_o12, fabric_pd_ready_o13, fabric_pd_ready_o14, fabric_pd_ready_o15, fabric_pd_ready_o16, fabric_pd_ready_o17, fabric_pd_ready_o18, fabric_pd_ready_o19, fabric_pd_ready_o20, fabric_pd_ready_o21, fabric_pd_ready_o22, fabric_pd_ready_o23, fabric_pd_ready_o24, fabric_debug_key_correct_o, fabric_otp_apb_ready_o
-, fabric_otp_user_progfail_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_bend2_o, fabric_debug_lifecycle_o1, fabric_debug_lifecycle_o2, fabric_debug_lifecycle_o3, fabric_debug_lifecycle_o4, fabric_mrepair_fuse_ack_o, fabric_debug_cpt_retry_o1, fabric_debug_cpt_retry_o2, fabric_debug_cpt_retry_o3, fabric_debug_cpt_retry_o4, fabric_otp_security_ack_o, fabric_debug_otpmgmt_state_o1, fabric_debug_otpmgmt_state_o2, fabric_debug_otpmgmt_state_o3, fabric_mrepair_fuse_progfail_o, fabric_otp_user_bist2fail_o1, fabric_otp_user_bist2fail_o2, fabric_otp_user_bist2fail_o3, fabric_otp_user_bist2fail_o4
-, fabric_otp_user_bist2fail_o5, fabric_otp_user_bist2fail_o6, fabric_otp_user_bist2fail_o7, fabric_user_data_o1, fabric_user_data_o2, fabric_user_data_o3, fabric_user_data_o4, fabric_user_data_o5, fabric_user_data_o6, fabric_user_data_o7, fabric_user_data_o8, fabric_user_data_o9, fabric_user_data_o10, fabric_user_data_o11, fabric_user_data_o12, fabric_user_data_o13, fabric_user_data_o14, fabric_user_data_o15, fabric_user_data_o16, fabric_user_data_o17, fabric_user_data_o18
-, fabric_user_data_o19, fabric_user_data_o20, fabric_user_data_o21, fabric_user_data_o22, fabric_user_data_o23, fabric_user_data_o24, fabric_user_data_o25, fabric_user_data_o26, fabric_user_data_o27, fabric_user_data_o28, fabric_user_data_o29, fabric_user_data_o30, fabric_user_data_o31, fabric_user_data_o32, fabric_jtag_tdi_o, fabric_lowskew_o3, fabric_lowskew_o5, fabric_lowskew_o4, fabric_debug_error_o, fabric_jtag_usr2_o, fabric_mrepair_fuse_wlromout_o1
-, fabric_mrepair_fuse_wlromout_o2, fabric_mrepair_fuse_wlromout_o3, fabric_mrepair_fuse_wlromout_o4, fabric_mrepair_fuse_wlromout_o5, fabric_mrepair_fuse_wlromout_o6, fabric_mrepair_fuse_wlromout_o7, fabric_mrepair_fuse_wlromout_o8, fabric_mrepair_fuse_wlromout_o9, fabric_mrepair_fuse_wlromout_o10, fabric_debug_otpapb_state_o1, fabric_debug_otpapb_state_o2, fabric_debug_otpapb_state_o3, fabric_otp_user_bist1fail_o1, fabric_otp_user_bist1fail_o2, fabric_otp_user_bist1fail_o3, fabric_otp_user_bist1fail_o4, fabric_otp_user_bist1fail_o5, fabric_otp_user_bist1fail_o6, fabric_otp_user_bist1fail_o7, fabric_otp_user_bist1fail_o8, fabric_otp_security_bist_fail2_o1
-, fabric_otp_security_bist_fail2_o2, fabric_otp_security_bist_fail2_o3, fabric_otp_security_bist_fail2_o4, fabric_otp_security_bist_fail2_o5, fabric_otp_security_bist_fail2_o6, fabric_otp_security_bist_fail2_o7, fabric_otp_user_disturbed_o, fabric_flag_trigger_o, fabric_otp_security_bist_end2_o, fabric_otp_security_bist_fail1_o1, fabric_otp_security_bist_fail1_o2, fabric_otp_security_bist_fail1_o3, fabric_otp_security_bist_fail1_o4, fabric_otp_security_bist_fail1_o5, fabric_otp_security_bist_fail1_o6, fabric_otp_security_bist_fail1_o7, fabric_otp_security_bist_fail1_o8, fabric_mrepair_fuse_locked_o, fabric_otp_user_flagstate_o1, fabric_otp_user_flagstate_o2, fabric_otp_user_flagstate_o3
-, fabric_otp_user_flagstate_o4, fabric_otp_security_scanout_o1, fabric_otp_security_scanout_o2, fabric_otp_security_scanout_o3, fabric_otp_security_scanout_o4, fabric_otp_security_scanout_o5, fabric_user_write_cycle_o, fabric_debug_fsm_state_o1, fabric_debug_fsm_state_o2, fabric_debug_fsm_state_o3, fabric_otp_user_ded_o, fabric_debug_otp_manager_read_done_o, fabric_debug_frame_use_encryption_o, fabric_data_to_system_o, fabric_jtag_usr1_o, fabric_otp_user_bend1_o, fabric_debug_otpboot_curr_addr_o1, fabric_debug_otpboot_curr_addr_o2, fabric_debug_otpboot_curr_addr_o3, fabric_debug_otpboot_curr_addr_o4, fabric_debug_otpboot_curr_addr_o5
-, fabric_debug_otpboot_curr_addr_o6, fabric_debug_otpboot_curr_addr_o7, fabric_debug_otpboot_curr_addr_o8, fabric_mrepair_fuse_ready_o, fabric_mrepair_fuse_calibrated_o, fabric_sif_load_en_to_bist_o1, fabric_sif_load_en_to_bist_o2, fabric_sif_load_en_to_bist_o3, fabric_sif_load_en_to_bist_o4, fabric_sif_load_en_to_bist_o5, fabric_sif_load_en_to_bist_o6, fabric_sif_load_en_to_bist_o7, fabric_sif_load_en_to_bist_o8, fabric_sif_load_en_to_bist_o9, fabric_sif_load_en_to_bist_o10, fabric_sif_load_en_to_bist_o11, fabric_sif_load_en_to_bist_o12, fabric_sif_load_en_to_bist_o13, fabric_sif_load_en_to_bist_o14, fabric_sif_load_en_to_bist_o15, fabric_sif_load_en_to_bist_o16
-, fabric_sif_load_en_to_bist_o17, fabric_sif_load_en_to_bist_o18, fabric_sif_load_en_to_bist_o19, fabric_sif_load_en_to_bist_o20, fabric_sif_load_en_to_bist_o21, fabric_sif_load_en_to_bist_o22, fabric_sif_load_en_to_bist_o23, fabric_sif_load_en_to_bist_o24, fabric_io_out_o1, fabric_io_out_o2, fabric_io_out_o3, fabric_io_out_o4, fabric_io_out_o5, fabric_io_out_o6, fabric_io_out_o7, fabric_io_out_o8, fabric_io_out_o9, fabric_io_out_o10, fabric_io_out_o11, fabric_io_out_o12, fabric_io_out_o13
-, fabric_io_out_o14, fabric_io_out_o15, fabric_io_out_o16, fabric_io_out_o17, fabric_io_out_o18, fabric_io_out_o19, fabric_io_out_o20, fabric_io_out_o21, fabric_io_out_o22, fabric_io_out_o23, fabric_io_out_o24, fabric_io_out_o25, fabric_mrepair_fuse_startword_o1, fabric_mrepair_fuse_startword_o2, fabric_mrepair_fuse_startword_o3, fabric_mrepair_fuse_startword_o4, fabric_mrepair_fuse_startword_o5, fabric_mrepair_fuse_startword_o6, fabric_mrepair_fuse_startword_o7, fabric_mrepair_fuse_startword_o8, fabric_mrepair_fuse_startword_o9
-, fabric_mrepair_fuse_startword_o10, fabric_mrepair_fuse_startword_o11, fabric_mrepair_fuse_startword_o12, fabric_mrepair_fuse_startword_o13, fabric_mrepair_fuse_startword_o14, fabric_mrepair_fuse_startword_o15, fabric_mrepair_fuse_startword_o16, fabric_system_dataready_o, fabric_mrepair_fuse_pwok_o, fabric_lowskew_o6, fabric_cfg_fabric_user_flag_o, fabric_otp_user_dout_o1, fabric_otp_user_dout_o2, fabric_otp_user_dout_o3, fabric_otp_user_dout_o4, fabric_otp_user_dout_o5, fabric_otp_user_dout_o6, fabric_otp_user_dout_o7, fabric_otp_user_dout_o8, fabric_otp_user_dout_o9, fabric_otp_user_dout_o10
-, fabric_otp_user_dout_o11, fabric_otp_user_dout_o12, fabric_otp_user_dout_o13, fabric_otp_user_dout_o14, fabric_otp_user_dout_o15, fabric_otp_user_dout_o16, fabric_otp_user_dout_o17, fabric_otp_user_dout_o18, fabric_otp_user_dout_o19, fabric_otp_user_dout_o20, fabric_otp_user_dout_o21, fabric_otp_user_dout_o22, fabric_otp_user_dout_o23, fabric_otp_user_dout_o24, fabric_otp_user_dout_o25, fabric_otp_user_dout_o26, fabric_otp_user_dout_o27, fabric_otp_user_dout_o28, fabric_otp_user_dout_o29, fabric_otp_user_dout_o30, fabric_otp_user_dout_o31
-, fabric_otp_user_dout_o32, fabric_otp_user_dout_o33, fabric_otp_user_dout_o34, fabric_otp_user_dout_o35, fabric_otp_user_dout_o36, fabric_otp_user_dout_o37, fabric_otp_user_dout_o38, fabric_otp_user_dout_o39, fabric_otp_user_dout_o40, fabric_otp_user_dout_o41, fabric_mrepair_fuse_bist2fail_o1, fabric_mrepair_fuse_bist2fail_o2, fabric_mrepair_fuse_bist2fail_o3, fabric_mrepair_fuse_bist2fail_o4, fabric_mrepair_fuse_bist2fail_o5, fabric_mrepair_fuse_bist2fail_o6, fabric_mrepair_fuse_bist2fail_o7, fabric_status_cold_start_o, fabric_flag_error_o, fabric_debug_direct_permission_read_o1, fabric_debug_direct_permission_read_o2
-, fabric_debug_direct_permission_read_o3, fabric_debug_direct_permission_read_o4);
-    input fabric_ahb_direct_data_i1;
-    input fabric_ahb_direct_data_i10;
-    input fabric_ahb_direct_data_i11;
-    input fabric_ahb_direct_data_i12;
-    input fabric_ahb_direct_data_i13;
-    input fabric_ahb_direct_data_i14;
-    input fabric_ahb_direct_data_i15;
-    input fabric_ahb_direct_data_i16;
-    input fabric_ahb_direct_data_i17;
-    input fabric_ahb_direct_data_i18;
-    input fabric_ahb_direct_data_i19;
-    input fabric_ahb_direct_data_i2;
-    input fabric_ahb_direct_data_i20;
-    input fabric_ahb_direct_data_i21;
-    input fabric_ahb_direct_data_i22;
-    input fabric_ahb_direct_data_i23;
-    input fabric_ahb_direct_data_i24;
-    input fabric_ahb_direct_data_i25;
-    input fabric_ahb_direct_data_i26;
-    input fabric_ahb_direct_data_i27;
-    input fabric_ahb_direct_data_i28;
-    input fabric_ahb_direct_data_i29;
-    input fabric_ahb_direct_data_i3;
-    input fabric_ahb_direct_data_i30;
-    input fabric_ahb_direct_data_i31;
-    input fabric_ahb_direct_data_i32;
-    input fabric_ahb_direct_data_i4;
-    input fabric_ahb_direct_data_i5;
-    input fabric_ahb_direct_data_i6;
-    input fabric_ahb_direct_data_i7;
-    input fabric_ahb_direct_data_i8;
-    input fabric_ahb_direct_data_i9;
-    output fabric_ahb_direct_data_o1;
-    output fabric_ahb_direct_data_o10;
-    output fabric_ahb_direct_data_o11;
-    output fabric_ahb_direct_data_o12;
-    output fabric_ahb_direct_data_o13;
-    output fabric_ahb_direct_data_o14;
-    output fabric_ahb_direct_data_o15;
-    output fabric_ahb_direct_data_o16;
-    output fabric_ahb_direct_data_o17;
-    output fabric_ahb_direct_data_o18;
-    output fabric_ahb_direct_data_o19;
-    output fabric_ahb_direct_data_o2;
-    output fabric_ahb_direct_data_o20;
-    output fabric_ahb_direct_data_o21;
-    output fabric_ahb_direct_data_o22;
-    output fabric_ahb_direct_data_o23;
-    output fabric_ahb_direct_data_o24;
-    output fabric_ahb_direct_data_o25;
-    output fabric_ahb_direct_data_o26;
-    output fabric_ahb_direct_data_o27;
-    output fabric_ahb_direct_data_o28;
-    output fabric_ahb_direct_data_o29;
-    output fabric_ahb_direct_data_o3;
-    output fabric_ahb_direct_data_o30;
-    output fabric_ahb_direct_data_o31;
-    output fabric_ahb_direct_data_o32;
-    output fabric_ahb_direct_data_o4;
-    output fabric_ahb_direct_data_o5;
-    output fabric_ahb_direct_data_o6;
-    output fabric_ahb_direct_data_o7;
-    output fabric_ahb_direct_data_o8;
-    output fabric_ahb_direct_data_o9;
-    output fabric_cfg_fabric_user_flag_o;
-    output fabric_cfg_fabric_user_unmask_o;
-    output fabric_chip_status_o1;
-    output fabric_chip_status_o10;
-    output fabric_chip_status_o11;
-    output fabric_chip_status_o12;
-    output fabric_chip_status_o13;
-    output fabric_chip_status_o14;
-    output fabric_chip_status_o15;
-    output fabric_chip_status_o16;
-    output fabric_chip_status_o17;
-    output fabric_chip_status_o18;
-    output fabric_chip_status_o19;
-    output fabric_chip_status_o2;
-    output fabric_chip_status_o20;
-    output fabric_chip_status_o21;
-    output fabric_chip_status_o22;
-    output fabric_chip_status_o23;
-    output fabric_chip_status_o24;
-    output fabric_chip_status_o25;
-    output fabric_chip_status_o26;
-    output fabric_chip_status_o27;
-    output fabric_chip_status_o28;
-    output fabric_chip_status_o29;
-    output fabric_chip_status_o3;
-    output fabric_chip_status_o30;
-    output fabric_chip_status_o31;
-    output fabric_chip_status_o32;
-    output fabric_chip_status_o33;
-    output fabric_chip_status_o34;
-    output fabric_chip_status_o35;
-    output fabric_chip_status_o36;
-    output fabric_chip_status_o37;
-    output fabric_chip_status_o38;
-    output fabric_chip_status_o39;
-    output fabric_chip_status_o4;
-    output fabric_chip_status_o40;
-    output fabric_chip_status_o41;
-    output fabric_chip_status_o42;
-    output fabric_chip_status_o43;
-    output fabric_chip_status_o44;
-    output fabric_chip_status_o45;
-    output fabric_chip_status_o46;
-    output fabric_chip_status_o47;
-    output fabric_chip_status_o48;
-    output fabric_chip_status_o49;
-    output fabric_chip_status_o5;
-    output fabric_chip_status_o50;
-    output fabric_chip_status_o51;
-    output fabric_chip_status_o52;
-    output fabric_chip_status_o53;
-    output fabric_chip_status_o54;
-    output fabric_chip_status_o55;
-    output fabric_chip_status_o56;
-    output fabric_chip_status_o57;
-    output fabric_chip_status_o58;
-    output fabric_chip_status_o59;
-    output fabric_chip_status_o6;
-    output fabric_chip_status_o60;
-    output fabric_chip_status_o61;
-    output fabric_chip_status_o62;
-    output fabric_chip_status_o63;
-    output fabric_chip_status_o64;
-    output fabric_chip_status_o65;
-    output fabric_chip_status_o66;
-    output fabric_chip_status_o67;
-    output fabric_chip_status_o68;
-    output fabric_chip_status_o69;
-    output fabric_chip_status_o7;
-    output fabric_chip_status_o70;
-    output fabric_chip_status_o71;
-    output fabric_chip_status_o72;
-    output fabric_chip_status_o8;
-    output fabric_chip_status_o9;
-    input fabric_data_from_bist_i1;
-    input fabric_data_from_bist_i10;
-    input fabric_data_from_bist_i11;
-    input fabric_data_from_bist_i12;
-    input fabric_data_from_bist_i13;
-    input fabric_data_from_bist_i14;
-    input fabric_data_from_bist_i15;
-    input fabric_data_from_bist_i16;
-    input fabric_data_from_bist_i17;
-    input fabric_data_from_bist_i18;
-    input fabric_data_from_bist_i19;
-    input fabric_data_from_bist_i2;
-    input fabric_data_from_bist_i20;
-    input fabric_data_from_bist_i21;
-    input fabric_data_from_bist_i22;
-    input fabric_data_from_bist_i23;
-    input fabric_data_from_bist_i24;
-    input fabric_data_from_bist_i3;
-    input fabric_data_from_bist_i4;
-    input fabric_data_from_bist_i5;
-    input fabric_data_from_bist_i6;
-    input fabric_data_from_bist_i7;
-    input fabric_data_from_bist_i8;
-    input fabric_data_from_bist_i9;
-    input fabric_data_from_system_i;
-    input fabric_data_shift_en_i;
-    output fabric_data_to_bist_o1;
-    output fabric_data_to_bist_o10;
-    output fabric_data_to_bist_o11;
-    output fabric_data_to_bist_o12;
-    output fabric_data_to_bist_o13;
-    output fabric_data_to_bist_o14;
-    output fabric_data_to_bist_o15;
-    output fabric_data_to_bist_o16;
-    output fabric_data_to_bist_o17;
-    output fabric_data_to_bist_o18;
-    output fabric_data_to_bist_o19;
-    output fabric_data_to_bist_o2;
-    output fabric_data_to_bist_o20;
-    output fabric_data_to_bist_o21;
-    output fabric_data_to_bist_o22;
-    output fabric_data_to_bist_o23;
-    output fabric_data_to_bist_o24;
-    output fabric_data_to_bist_o3;
-    output fabric_data_to_bist_o4;
-    output fabric_data_to_bist_o5;
-    output fabric_data_to_bist_o6;
-    output fabric_data_to_bist_o7;
-    output fabric_data_to_bist_o8;
-    output fabric_data_to_bist_o9;
-    output fabric_data_to_system_o;
-    output fabric_debug_access_reg_data_ready_o;
-    output fabric_debug_bsec_core_status_o1;
-    output fabric_debug_bsec_core_status_o10;
-    output fabric_debug_bsec_core_status_o11;
-    output fabric_debug_bsec_core_status_o12;
-    output fabric_debug_bsec_core_status_o13;
-    output fabric_debug_bsec_core_status_o14;
-    output fabric_debug_bsec_core_status_o15;
-    output fabric_debug_bsec_core_status_o16;
-    output fabric_debug_bsec_core_status_o17;
-    output fabric_debug_bsec_core_status_o18;
-    output fabric_debug_bsec_core_status_o19;
-    output fabric_debug_bsec_core_status_o2;
-    output fabric_debug_bsec_core_status_o20;
-    output fabric_debug_bsec_core_status_o21;
-    output fabric_debug_bsec_core_status_o22;
-    output fabric_debug_bsec_core_status_o23;
-    output fabric_debug_bsec_core_status_o24;
-    output fabric_debug_bsec_core_status_o25;
-    output fabric_debug_bsec_core_status_o26;
-    output fabric_debug_bsec_core_status_o27;
-    output fabric_debug_bsec_core_status_o28;
-    output fabric_debug_bsec_core_status_o29;
-    output fabric_debug_bsec_core_status_o3;
-    output fabric_debug_bsec_core_status_o30;
-    output fabric_debug_bsec_core_status_o31;
-    output fabric_debug_bsec_core_status_o32;
-    output fabric_debug_bsec_core_status_o4;
-    output fabric_debug_bsec_core_status_o5;
-    output fabric_debug_bsec_core_status_o6;
-    output fabric_debug_bsec_core_status_o7;
-    output fabric_debug_bsec_core_status_o8;
-    output fabric_debug_bsec_core_status_o9;
-    output fabric_debug_cpt_retry_o1;
-    output fabric_debug_cpt_retry_o2;
-    output fabric_debug_cpt_retry_o3;
-    output fabric_debug_cpt_retry_o4;
-    output fabric_debug_direct_permission_read_o1;
-    output fabric_debug_direct_permission_read_o2;
-    output fabric_debug_direct_permission_read_o3;
-    output fabric_debug_direct_permission_read_o4;
-    output fabric_debug_direct_permission_write_o1;
-    output fabric_debug_direct_permission_write_o2;
-    output fabric_debug_direct_permission_write_o3;
-    output fabric_debug_direct_permission_write_o4;
-    output fabric_debug_error_o;
-    output fabric_debug_frame_permission_frame_o1;
-    output fabric_debug_frame_permission_frame_o2;
-    output fabric_debug_frame_permission_frame_o3;
-    output fabric_debug_frame_permission_frame_o4;
-    output fabric_debug_frame_use_encryption_o;
-    output fabric_debug_fsm_state_o1;
-    output fabric_debug_fsm_state_o2;
-    output fabric_debug_fsm_state_o3;
-    output fabric_debug_key_correct_o;
-    output fabric_debug_lifecycle_o1;
-    output fabric_debug_lifecycle_o2;
-    output fabric_debug_lifecycle_o3;
-    output fabric_debug_lifecycle_o4;
-    output fabric_debug_lock_reg_o;
-    output fabric_debug_otp_manager_read_done_o;
-    output fabric_debug_otp_manager_read_otp_o;
-    output fabric_debug_otp_reload_err_o;
-    output fabric_debug_otpapb_state_o1;
-    output fabric_debug_otpapb_state_o2;
-    output fabric_debug_otpapb_state_o3;
-    output fabric_debug_otpboot_curr_addr_o1;
-    output fabric_debug_otpboot_curr_addr_o2;
-    output fabric_debug_otpboot_curr_addr_o3;
-    output fabric_debug_otpboot_curr_addr_o4;
-    output fabric_debug_otpboot_curr_addr_o5;
-    output fabric_debug_otpboot_curr_addr_o6;
-    output fabric_debug_otpboot_curr_addr_o7;
-    output fabric_debug_otpboot_curr_addr_o8;
-    output fabric_debug_otpboot_state_o1;
-    output fabric_debug_otpboot_state_o2;
-    output fabric_debug_otpboot_state_o3;
-    output fabric_debug_otpmgmt_state_o1;
-    output fabric_debug_otpmgmt_state_o2;
-    output fabric_debug_otpmgmt_state_o3;
-    output fabric_debug_rst_soft_o;
-    output fabric_debug_security_boot_done_o;
-    output fabric_debug_security_error_read_o;
-    output fabric_decoder_init_ready_o;
-    input fabric_direct_data_i1;
-    input fabric_direct_data_i10;
-    input fabric_direct_data_i11;
-    input fabric_direct_data_i12;
-    input fabric_direct_data_i13;
-    input fabric_direct_data_i14;
-    input fabric_direct_data_i15;
-    input fabric_direct_data_i16;
-    input fabric_direct_data_i17;
-    input fabric_direct_data_i18;
-    input fabric_direct_data_i19;
-    input fabric_direct_data_i2;
-    input fabric_direct_data_i20;
-    input fabric_direct_data_i21;
-    input fabric_direct_data_i22;
-    input fabric_direct_data_i23;
-    input fabric_direct_data_i24;
-    input fabric_direct_data_i25;
-    input fabric_direct_data_i26;
-    input fabric_direct_data_i27;
-    input fabric_direct_data_i28;
-    input fabric_direct_data_i29;
-    input fabric_direct_data_i3;
-    input fabric_direct_data_i30;
-    input fabric_direct_data_i31;
-    input fabric_direct_data_i32;
-    input fabric_direct_data_i4;
-    input fabric_direct_data_i5;
-    input fabric_direct_data_i6;
-    input fabric_direct_data_i7;
-    input fabric_direct_data_i8;
-    input fabric_direct_data_i9;
-    output fabric_direct_data_o1;
-    output fabric_direct_data_o10;
-    output fabric_direct_data_o11;
-    output fabric_direct_data_o12;
-    output fabric_direct_data_o13;
-    output fabric_direct_data_o14;
-    output fabric_direct_data_o15;
-    output fabric_direct_data_o16;
-    output fabric_direct_data_o17;
-    output fabric_direct_data_o18;
-    output fabric_direct_data_o19;
-    output fabric_direct_data_o2;
-    output fabric_direct_data_o20;
-    output fabric_direct_data_o21;
-    output fabric_direct_data_o22;
-    output fabric_direct_data_o23;
-    output fabric_direct_data_o24;
-    output fabric_direct_data_o25;
-    output fabric_direct_data_o26;
-    output fabric_direct_data_o27;
-    output fabric_direct_data_o28;
-    output fabric_direct_data_o29;
-    output fabric_direct_data_o3;
-    output fabric_direct_data_o30;
-    output fabric_direct_data_o31;
-    output fabric_direct_data_o32;
-    output fabric_direct_data_o4;
-    output fabric_direct_data_o5;
-    output fabric_direct_data_o6;
-    output fabric_direct_data_o7;
-    output fabric_direct_data_o8;
-    output fabric_direct_data_o9;
-    input fabric_end_encoding_i;
-    output fabric_flag_error_o;
-    output fabric_flag_ready_o;
-    output fabric_flag_trigger_o;
-    output fabric_fuse_status_o1;
-    output fabric_fuse_status_o2;
-    output fabric_fuse_status_o3;
-    output fabric_global_chip_status_o1;
-    output fabric_global_chip_status_o2;
-    output fabric_global_chip_status_o3;
-    input fabric_io_in_i1;
-    input fabric_io_in_i10;
-    input fabric_io_in_i11;
-    input fabric_io_in_i12;
-    input fabric_io_in_i13;
-    input fabric_io_in_i14;
-    input fabric_io_in_i15;
-    input fabric_io_in_i16;
-    input fabric_io_in_i17;
-    input fabric_io_in_i18;
-    input fabric_io_in_i19;
-    input fabric_io_in_i2;
-    input fabric_io_in_i20;
-    input fabric_io_in_i21;
-    input fabric_io_in_i22;
-    input fabric_io_in_i23;
-    input fabric_io_in_i24;
-    input fabric_io_in_i25;
-    input fabric_io_in_i3;
-    input fabric_io_in_i4;
-    input fabric_io_in_i5;
-    input fabric_io_in_i6;
-    input fabric_io_in_i7;
-    input fabric_io_in_i8;
-    input fabric_io_in_i9;
-    input fabric_io_oe_i1;
-    input fabric_io_oe_i10;
-    input fabric_io_oe_i11;
-    input fabric_io_oe_i12;
-    input fabric_io_oe_i13;
-    input fabric_io_oe_i14;
-    input fabric_io_oe_i15;
-    input fabric_io_oe_i16;
-    input fabric_io_oe_i17;
-    input fabric_io_oe_i18;
-    input fabric_io_oe_i19;
-    input fabric_io_oe_i2;
-    input fabric_io_oe_i20;
-    input fabric_io_oe_i21;
-    input fabric_io_oe_i22;
-    input fabric_io_oe_i23;
-    input fabric_io_oe_i24;
-    input fabric_io_oe_i25;
-    input fabric_io_oe_i3;
-    input fabric_io_oe_i4;
-    input fabric_io_oe_i5;
-    input fabric_io_oe_i6;
-    input fabric_io_oe_i7;
-    input fabric_io_oe_i8;
-    input fabric_io_oe_i9;
-    output fabric_io_out_o1;
-    output fabric_io_out_o10;
-    output fabric_io_out_o11;
-    output fabric_io_out_o12;
-    output fabric_io_out_o13;
-    output fabric_io_out_o14;
-    output fabric_io_out_o15;
-    output fabric_io_out_o16;
-    output fabric_io_out_o17;
-    output fabric_io_out_o18;
-    output fabric_io_out_o19;
-    output fabric_io_out_o2;
-    output fabric_io_out_o20;
-    output fabric_io_out_o21;
-    output fabric_io_out_o22;
-    output fabric_io_out_o23;
-    output fabric_io_out_o24;
-    output fabric_io_out_o25;
-    output fabric_io_out_o3;
-    output fabric_io_out_o4;
-    output fabric_io_out_o5;
-    output fabric_io_out_o6;
-    output fabric_io_out_o7;
-    output fabric_io_out_o8;
-    output fabric_io_out_o9;
-    output fabric_jtag_tdi_o;
-    input fabric_jtag_tdo_usr1_i;
-    input fabric_jtag_tdo_usr2_i;
-    output fabric_jtag_tms_o;
-    output fabric_jtag_trst_n_o;
-    output fabric_jtag_usr1_o;
-    output fabric_jtag_usr2_o;
-    input fabric_lowskew_i20;
-    input fabric_lowskew_i21;
-    input fabric_lowskew_i22;
-    input fabric_lowskew_i23;
-    output fabric_lowskew_o3;
-    output fabric_lowskew_o4;
-    output fabric_lowskew_o5;
-    output fabric_lowskew_o6;
-    output fabric_mrepair_fuse_ack_o;
-    input fabric_mrepair_fuse_add_i1;
-    input fabric_mrepair_fuse_add_i2;
-    input fabric_mrepair_fuse_add_i3;
-    input fabric_mrepair_fuse_add_i4;
-    input fabric_mrepair_fuse_add_i5;
-    input fabric_mrepair_fuse_add_i6;
-    input fabric_mrepair_fuse_add_i7;
-    output fabric_mrepair_fuse_bbad_o;
-    output fabric_mrepair_fuse_bend1_o;
-    output fabric_mrepair_fuse_bend2_o;
-    output fabric_mrepair_fuse_bist1fail_o1;
-    output fabric_mrepair_fuse_bist1fail_o2;
-    output fabric_mrepair_fuse_bist1fail_o3;
-    output fabric_mrepair_fuse_bist1fail_o4;
-    output fabric_mrepair_fuse_bist1fail_o5;
-    output fabric_mrepair_fuse_bist1fail_o6;
-    output fabric_mrepair_fuse_bist1fail_o7;
-    output fabric_mrepair_fuse_bist1fail_o8;
-    output fabric_mrepair_fuse_bist2fail_o1;
-    output fabric_mrepair_fuse_bist2fail_o2;
-    output fabric_mrepair_fuse_bist2fail_o3;
-    output fabric_mrepair_fuse_bist2fail_o4;
-    output fabric_mrepair_fuse_bist2fail_o5;
-    output fabric_mrepair_fuse_bist2fail_o6;
-    output fabric_mrepair_fuse_bist2fail_o7;
-    input fabric_mrepair_fuse_bistmode_i;
-    output fabric_mrepair_fuse_calibrated_o;
-    input fabric_mrepair_fuse_configreg_i1;
-    input fabric_mrepair_fuse_configreg_i10;
-    input fabric_mrepair_fuse_configreg_i11;
-    input fabric_mrepair_fuse_configreg_i12;
-    input fabric_mrepair_fuse_configreg_i13;
-    input fabric_mrepair_fuse_configreg_i14;
-    input fabric_mrepair_fuse_configreg_i15;
-    input fabric_mrepair_fuse_configreg_i16;
-    input fabric_mrepair_fuse_configreg_i17;
-    input fabric_mrepair_fuse_configreg_i18;
-    input fabric_mrepair_fuse_configreg_i19;
-    input fabric_mrepair_fuse_configreg_i2;
-    input fabric_mrepair_fuse_configreg_i20;
-    input fabric_mrepair_fuse_configreg_i21;
-    input fabric_mrepair_fuse_configreg_i22;
-    input fabric_mrepair_fuse_configreg_i23;
-    input fabric_mrepair_fuse_configreg_i24;
-    input fabric_mrepair_fuse_configreg_i25;
-    input fabric_mrepair_fuse_configreg_i26;
-    input fabric_mrepair_fuse_configreg_i27;
-    input fabric_mrepair_fuse_configreg_i28;
-    input fabric_mrepair_fuse_configreg_i29;
-    input fabric_mrepair_fuse_configreg_i3;
-    input fabric_mrepair_fuse_configreg_i30;
-    input fabric_mrepair_fuse_configreg_i31;
-    input fabric_mrepair_fuse_configreg_i32;
-    input fabric_mrepair_fuse_configreg_i4;
-    input fabric_mrepair_fuse_configreg_i5;
-    input fabric_mrepair_fuse_configreg_i6;
-    input fabric_mrepair_fuse_configreg_i7;
-    input fabric_mrepair_fuse_configreg_i8;
-    input fabric_mrepair_fuse_configreg_i9;
-    output fabric_mrepair_fuse_ded_o;
-    input fabric_mrepair_fuse_din_i1;
-    input fabric_mrepair_fuse_din_i10;
-    input fabric_mrepair_fuse_din_i11;
-    input fabric_mrepair_fuse_din_i12;
-    input fabric_mrepair_fuse_din_i13;
-    input fabric_mrepair_fuse_din_i14;
-    input fabric_mrepair_fuse_din_i15;
-    input fabric_mrepair_fuse_din_i16;
-    input fabric_mrepair_fuse_din_i17;
-    input fabric_mrepair_fuse_din_i18;
-    input fabric_mrepair_fuse_din_i19;
-    input fabric_mrepair_fuse_din_i2;
-    input fabric_mrepair_fuse_din_i20;
-    input fabric_mrepair_fuse_din_i21;
-    input fabric_mrepair_fuse_din_i22;
-    input fabric_mrepair_fuse_din_i23;
-    input fabric_mrepair_fuse_din_i24;
-    input fabric_mrepair_fuse_din_i25;
-    input fabric_mrepair_fuse_din_i26;
-    input fabric_mrepair_fuse_din_i27;
-    input fabric_mrepair_fuse_din_i28;
-    input fabric_mrepair_fuse_din_i29;
-    input fabric_mrepair_fuse_din_i3;
-    input fabric_mrepair_fuse_din_i30;
-    input fabric_mrepair_fuse_din_i31;
-    input fabric_mrepair_fuse_din_i32;
-    input fabric_mrepair_fuse_din_i33;
-    input fabric_mrepair_fuse_din_i34;
-    input fabric_mrepair_fuse_din_i35;
-    input fabric_mrepair_fuse_din_i36;
-    input fabric_mrepair_fuse_din_i37;
-    input fabric_mrepair_fuse_din_i38;
-    input fabric_mrepair_fuse_din_i39;
-    input fabric_mrepair_fuse_din_i4;
-    input fabric_mrepair_fuse_din_i5;
-    input fabric_mrepair_fuse_din_i6;
-    input fabric_mrepair_fuse_din_i7;
-    input fabric_mrepair_fuse_din_i8;
-    input fabric_mrepair_fuse_din_i9;
-    input fabric_mrepair_fuse_disturbchecked_i;
-    output fabric_mrepair_fuse_disturbed_o;
-    output fabric_mrepair_fuse_dout_o1;
-    output fabric_mrepair_fuse_dout_o10;
-    output fabric_mrepair_fuse_dout_o11;
-    output fabric_mrepair_fuse_dout_o12;
-    output fabric_mrepair_fuse_dout_o13;
-    output fabric_mrepair_fuse_dout_o14;
-    output fabric_mrepair_fuse_dout_o15;
-    output fabric_mrepair_fuse_dout_o16;
-    output fabric_mrepair_fuse_dout_o17;
-    output fabric_mrepair_fuse_dout_o18;
-    output fabric_mrepair_fuse_dout_o19;
-    output fabric_mrepair_fuse_dout_o2;
-    output fabric_mrepair_fuse_dout_o20;
-    output fabric_mrepair_fuse_dout_o21;
-    output fabric_mrepair_fuse_dout_o22;
-    output fabric_mrepair_fuse_dout_o23;
-    output fabric_mrepair_fuse_dout_o24;
-    output fabric_mrepair_fuse_dout_o25;
-    output fabric_mrepair_fuse_dout_o26;
-    output fabric_mrepair_fuse_dout_o27;
-    output fabric_mrepair_fuse_dout_o28;
-    output fabric_mrepair_fuse_dout_o29;
-    output fabric_mrepair_fuse_dout_o3;
-    output fabric_mrepair_fuse_dout_o30;
-    output fabric_mrepair_fuse_dout_o31;
-    output fabric_mrepair_fuse_dout_o32;
-    output fabric_mrepair_fuse_dout_o33;
-    output fabric_mrepair_fuse_dout_o34;
-    output fabric_mrepair_fuse_dout_o35;
-    output fabric_mrepair_fuse_dout_o36;
-    output fabric_mrepair_fuse_dout_o37;
-    output fabric_mrepair_fuse_dout_o38;
-    output fabric_mrepair_fuse_dout_o39;
-    output fabric_mrepair_fuse_dout_o4;
-    output fabric_mrepair_fuse_dout_o40;
-    output fabric_mrepair_fuse_dout_o41;
-    output fabric_mrepair_fuse_dout_o5;
-    output fabric_mrepair_fuse_dout_o6;
-    output fabric_mrepair_fuse_dout_o7;
-    output fabric_mrepair_fuse_dout_o8;
-    output fabric_mrepair_fuse_dout_o9;
-    input fabric_mrepair_fuse_eccbypass_i;
-    output fabric_mrepair_fuse_flagstate_o1;
-    output fabric_mrepair_fuse_flagstate_o2;
-    output fabric_mrepair_fuse_flagstate_o3;
-    output fabric_mrepair_fuse_flagstate_o4;
-    output fabric_mrepair_fuse_locked_o;
-    input fabric_mrepair_fuse_pdn_i;
-    output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o;
-    input fabric_mrepair_fuse_prgwidth_i1;
-    input fabric_mrepair_fuse_prgwidth_i2;
-    input fabric_mrepair_fuse_prgwidth_i3;
-    input fabric_mrepair_fuse_prog_i;
-    output fabric_mrepair_fuse_progfail_o;
-    output fabric_mrepair_fuse_pwok_o;
-    input fabric_mrepair_fuse_rbact1_i;
-    input fabric_mrepair_fuse_rbact2_i;
-    input fabric_mrepair_fuse_read_i;
-    output fabric_mrepair_fuse_ready_o;
-    input fabric_mrepair_fuse_redbypass_i;
-    output fabric_mrepair_fuse_sec_o;
-    output fabric_mrepair_fuse_startword_o1;
-    output fabric_mrepair_fuse_startword_o10;
-    output fabric_mrepair_fuse_startword_o11;
-    output fabric_mrepair_fuse_startword_o12;
-    output fabric_mrepair_fuse_startword_o13;
-    output fabric_mrepair_fuse_startword_o14;
-    output fabric_mrepair_fuse_startword_o15;
-    output fabric_mrepair_fuse_startword_o16;
-    output fabric_mrepair_fuse_startword_o2;
-    output fabric_mrepair_fuse_startword_o3;
-    output fabric_mrepair_fuse_startword_o4;
-    output fabric_mrepair_fuse_startword_o5;
-    output fabric_mrepair_fuse_startword_o6;
-    output fabric_mrepair_fuse_startword_o7;
-    output fabric_mrepair_fuse_startword_o8;
-    output fabric_mrepair_fuse_startword_o9;
-    input fabric_mrepair_fuse_suppadd_i;
-    input fabric_mrepair_fuse_tm_i;
-    input fabric_mrepair_fuse_tst_scanin_i1;
-    input fabric_mrepair_fuse_tst_scanin_i2;
-    input fabric_mrepair_fuse_tst_scanin_i3;
-    input fabric_mrepair_fuse_tst_scanin_i4;
-    input fabric_mrepair_fuse_tst_scanin_i5;
-    input fabric_mrepair_fuse_tstscanenable_i;
-    output fabric_mrepair_fuse_tstscanout_o1;
-    output fabric_mrepair_fuse_tstscanout_o2;
-    output fabric_mrepair_fuse_tstscanout_o3;
-    output fabric_mrepair_fuse_tstscanout_o4;
-    output fabric_mrepair_fuse_tstscanout_o5;
-    output fabric_mrepair_fuse_wlromout_o1;
-    output fabric_mrepair_fuse_wlromout_o10;
-    output fabric_mrepair_fuse_wlromout_o2;
-    output fabric_mrepair_fuse_wlromout_o3;
-    output fabric_mrepair_fuse_wlromout_o4;
-    output fabric_mrepair_fuse_wlromout_o5;
-    output fabric_mrepair_fuse_wlromout_o6;
-    output fabric_mrepair_fuse_wlromout_o7;
-    output fabric_mrepair_fuse_wlromout_o8;
-    output fabric_mrepair_fuse_wlromout_o9;
-    input fabric_mrepair_fuse_wordlock_i;
-    input fabric_mrepair_initn_i;
-    input fabric_mrepair_mode_i1;
-    input fabric_mrepair_mode_i2;
-    input fabric_mrepair_mode_i3;
-    input fabric_mrepair_mode_i4;
-    input fabric_mrepair_por_i;
-    input fabric_mrepair_rst_n_i;
-    input fabric_otp_apb_addr_i1;
-    input fabric_otp_apb_addr_i10;
-    input fabric_otp_apb_addr_i11;
-    input fabric_otp_apb_addr_i12;
-    input fabric_otp_apb_addr_i13;
-    input fabric_otp_apb_addr_i14;
-    input fabric_otp_apb_addr_i15;
-    input fabric_otp_apb_addr_i16;
-    input fabric_otp_apb_addr_i17;
-    input fabric_otp_apb_addr_i18;
-    input fabric_otp_apb_addr_i19;
-    input fabric_otp_apb_addr_i2;
-    input fabric_otp_apb_addr_i20;
-    input fabric_otp_apb_addr_i21;
-    input fabric_otp_apb_addr_i22;
-    input fabric_otp_apb_addr_i23;
-    input fabric_otp_apb_addr_i24;
-    input fabric_otp_apb_addr_i25;
-    input fabric_otp_apb_addr_i26;
-    input fabric_otp_apb_addr_i27;
-    input fabric_otp_apb_addr_i28;
-    input fabric_otp_apb_addr_i29;
-    input fabric_otp_apb_addr_i3;
-    input fabric_otp_apb_addr_i30;
-    input fabric_otp_apb_addr_i31;
-    input fabric_otp_apb_addr_i32;
-    input fabric_otp_apb_addr_i4;
-    input fabric_otp_apb_addr_i5;
-    input fabric_otp_apb_addr_i6;
-    input fabric_otp_apb_addr_i7;
-    input fabric_otp_apb_addr_i8;
-    input fabric_otp_apb_addr_i9;
-    input fabric_otp_apb_enable_i;
-    output fabric_otp_apb_rdata_o1;
-    output fabric_otp_apb_rdata_o10;
-    output fabric_otp_apb_rdata_o11;
-    output fabric_otp_apb_rdata_o12;
-    output fabric_otp_apb_rdata_o13;
-    output fabric_otp_apb_rdata_o14;
-    output fabric_otp_apb_rdata_o15;
-    output fabric_otp_apb_rdata_o16;
-    output fabric_otp_apb_rdata_o17;
-    output fabric_otp_apb_rdata_o18;
-    output fabric_otp_apb_rdata_o19;
-    output fabric_otp_apb_rdata_o2;
-    output fabric_otp_apb_rdata_o20;
-    output fabric_otp_apb_rdata_o21;
-    output fabric_otp_apb_rdata_o22;
-    output fabric_otp_apb_rdata_o23;
-    output fabric_otp_apb_rdata_o24;
-    output fabric_otp_apb_rdata_o25;
-    output fabric_otp_apb_rdata_o26;
-    output fabric_otp_apb_rdata_o27;
-    output fabric_otp_apb_rdata_o28;
-    output fabric_otp_apb_rdata_o29;
-    output fabric_otp_apb_rdata_o3;
-    output fabric_otp_apb_rdata_o30;
-    output fabric_otp_apb_rdata_o31;
-    output fabric_otp_apb_rdata_o32;
-    output fabric_otp_apb_rdata_o4;
-    output fabric_otp_apb_rdata_o5;
-    output fabric_otp_apb_rdata_o6;
-    output fabric_otp_apb_rdata_o7;
-    output fabric_otp_apb_rdata_o8;
-    output fabric_otp_apb_rdata_o9;
-    output fabric_otp_apb_ready_o;
-    input fabric_otp_apb_sel_i;
-    input fabric_otp_apb_wdata_i1;
-    input fabric_otp_apb_wdata_i10;
-    input fabric_otp_apb_wdata_i11;
-    input fabric_otp_apb_wdata_i12;
-    input fabric_otp_apb_wdata_i13;
-    input fabric_otp_apb_wdata_i14;
-    input fabric_otp_apb_wdata_i15;
-    input fabric_otp_apb_wdata_i16;
-    input fabric_otp_apb_wdata_i17;
-    input fabric_otp_apb_wdata_i18;
-    input fabric_otp_apb_wdata_i19;
-    input fabric_otp_apb_wdata_i2;
-    input fabric_otp_apb_wdata_i20;
-    input fabric_otp_apb_wdata_i21;
-    input fabric_otp_apb_wdata_i22;
-    input fabric_otp_apb_wdata_i23;
-    input fabric_otp_apb_wdata_i24;
-    input fabric_otp_apb_wdata_i25;
-    input fabric_otp_apb_wdata_i26;
-    input fabric_otp_apb_wdata_i27;
-    input fabric_otp_apb_wdata_i28;
-    input fabric_otp_apb_wdata_i29;
-    input fabric_otp_apb_wdata_i3;
-    input fabric_otp_apb_wdata_i30;
-    input fabric_otp_apb_wdata_i31;
-    input fabric_otp_apb_wdata_i32;
-    input fabric_otp_apb_wdata_i4;
-    input fabric_otp_apb_wdata_i5;
-    input fabric_otp_apb_wdata_i6;
-    input fabric_otp_apb_wdata_i7;
-    input fabric_otp_apb_wdata_i8;
-    input fabric_otp_apb_wdata_i9;
-    input fabric_otp_apb_write_i;
-    input fabric_otp_cfg_clk_fab_en_i;
-    input fabric_otp_cfg_clk_otpm_disable_i;
-    input fabric_otp_cfg_fabric_apb_en_i;
-    input fabric_otp_cfg_loader_read_en_i;
-    input fabric_otp_cfg_loader_write_en_i;
-    input fabric_otp_rstn_i;
-    output fabric_otp_security_ack_o;
-    output fabric_otp_security_bist_bad_o;
-    output fabric_otp_security_bist_end1_o;
-    output fabric_otp_security_bist_end2_o;
-    output fabric_otp_security_bist_fail1_o1;
-    output fabric_otp_security_bist_fail1_o2;
-    output fabric_otp_security_bist_fail1_o3;
-    output fabric_otp_security_bist_fail1_o4;
-    output fabric_otp_security_bist_fail1_o5;
-    output fabric_otp_security_bist_fail1_o6;
-    output fabric_otp_security_bist_fail1_o7;
-    output fabric_otp_security_bist_fail1_o8;
-    output fabric_otp_security_bist_fail2_o1;
-    output fabric_otp_security_bist_fail2_o2;
-    output fabric_otp_security_bist_fail2_o3;
-    output fabric_otp_security_bist_fail2_o4;
-    output fabric_otp_security_bist_fail2_o5;
-    output fabric_otp_security_bist_fail2_o6;
-    output fabric_otp_security_bist_fail2_o7;
-    input fabric_otp_security_bistmode_i;
-    input fabric_otp_security_force_pdn1_i;
-    input fabric_otp_security_rbact1_i;
-    input fabric_otp_security_rbact2_i;
-    input fabric_otp_security_scanenable_i;
-    input fabric_otp_security_scanin_i1;
-    input fabric_otp_security_scanin_i2;
-    input fabric_otp_security_scanin_i3;
-    input fabric_otp_security_scanin_i4;
-    input fabric_otp_security_scanin_i5;
-    output fabric_otp_security_scanout_o1;
-    output fabric_otp_security_scanout_o2;
-    output fabric_otp_security_scanout_o3;
-    output fabric_otp_security_scanout_o4;
-    output fabric_otp_security_scanout_o5;
-    input fabric_otp_security_testmode_i;
-    output fabric_otp_user_ack_o;
-    input fabric_otp_user_add_i1;
-    input fabric_otp_user_add_i2;
-    input fabric_otp_user_add_i3;
-    input fabric_otp_user_add_i4;
-    input fabric_otp_user_add_i5;
-    input fabric_otp_user_add_i6;
-    input fabric_otp_user_add_i7;
-    output fabric_otp_user_bbad_o;
-    output fabric_otp_user_bend1_o;
-    output fabric_otp_user_bend2_o;
-    output fabric_otp_user_bist1fail_o1;
-    output fabric_otp_user_bist1fail_o2;
-    output fabric_otp_user_bist1fail_o3;
-    output fabric_otp_user_bist1fail_o4;
-    output fabric_otp_user_bist1fail_o5;
-    output fabric_otp_user_bist1fail_o6;
-    output fabric_otp_user_bist1fail_o7;
-    output fabric_otp_user_bist1fail_o8;
-    output fabric_otp_user_bist2fail_o1;
-    output fabric_otp_user_bist2fail_o2;
-    output fabric_otp_user_bist2fail_o3;
-    output fabric_otp_user_bist2fail_o4;
-    output fabric_otp_user_bist2fail_o5;
-    output fabric_otp_user_bist2fail_o6;
-    output fabric_otp_user_bist2fail_o7;
-    input fabric_otp_user_bistmode_i;
-    output fabric_otp_user_calibrated_o;
-    input fabric_otp_user_configreg_i1;
-    input fabric_otp_user_configreg_i10;
-    input fabric_otp_user_configreg_i11;
-    input fabric_otp_user_configreg_i12;
-    input fabric_otp_user_configreg_i13;
-    input fabric_otp_user_configreg_i14;
-    input fabric_otp_user_configreg_i15;
-    input fabric_otp_user_configreg_i16;
-    input fabric_otp_user_configreg_i17;
-    input fabric_otp_user_configreg_i18;
-    input fabric_otp_user_configreg_i19;
-    input fabric_otp_user_configreg_i2;
-    input fabric_otp_user_configreg_i20;
-    input fabric_otp_user_configreg_i21;
-    input fabric_otp_user_configreg_i22;
-    input fabric_otp_user_configreg_i23;
-    input fabric_otp_user_configreg_i24;
-    input fabric_otp_user_configreg_i25;
-    input fabric_otp_user_configreg_i26;
-    input fabric_otp_user_configreg_i27;
-    input fabric_otp_user_configreg_i28;
-    input fabric_otp_user_configreg_i29;
-    input fabric_otp_user_configreg_i3;
-    input fabric_otp_user_configreg_i30;
-    input fabric_otp_user_configreg_i31;
-    input fabric_otp_user_configreg_i32;
-    input fabric_otp_user_configreg_i4;
-    input fabric_otp_user_configreg_i5;
-    input fabric_otp_user_configreg_i6;
-    input fabric_otp_user_configreg_i7;
-    input fabric_otp_user_configreg_i8;
-    input fabric_otp_user_configreg_i9;
-    output fabric_otp_user_ded_o;
-    input fabric_otp_user_din_i1;
-    input fabric_otp_user_din_i10;
-    input fabric_otp_user_din_i11;
-    input fabric_otp_user_din_i12;
-    input fabric_otp_user_din_i13;
-    input fabric_otp_user_din_i14;
-    input fabric_otp_user_din_i15;
-    input fabric_otp_user_din_i16;
-    input fabric_otp_user_din_i17;
-    input fabric_otp_user_din_i18;
-    input fabric_otp_user_din_i19;
-    input fabric_otp_user_din_i2;
-    input fabric_otp_user_din_i20;
-    input fabric_otp_user_din_i21;
-    input fabric_otp_user_din_i22;
-    input fabric_otp_user_din_i23;
-    input fabric_otp_user_din_i24;
-    input fabric_otp_user_din_i25;
-    input fabric_otp_user_din_i26;
-    input fabric_otp_user_din_i27;
-    input fabric_otp_user_din_i28;
-    input fabric_otp_user_din_i29;
-    input fabric_otp_user_din_i3;
-    input fabric_otp_user_din_i30;
-    input fabric_otp_user_din_i31;
-    input fabric_otp_user_din_i32;
-    input fabric_otp_user_din_i33;
-    input fabric_otp_user_din_i34;
-    input fabric_otp_user_din_i35;
-    input fabric_otp_user_din_i36;
-    input fabric_otp_user_din_i37;
-    input fabric_otp_user_din_i38;
-    input fabric_otp_user_din_i39;
-    input fabric_otp_user_din_i4;
-    input fabric_otp_user_din_i5;
-    input fabric_otp_user_din_i6;
-    input fabric_otp_user_din_i7;
-    input fabric_otp_user_din_i8;
-    input fabric_otp_user_din_i9;
-    input fabric_otp_user_disturbcheck_i;
-    output fabric_otp_user_disturbed_o;
-    output fabric_otp_user_dout_o1;
-    output fabric_otp_user_dout_o10;
-    output fabric_otp_user_dout_o11;
-    output fabric_otp_user_dout_o12;
-    output fabric_otp_user_dout_o13;
-    output fabric_otp_user_dout_o14;
-    output fabric_otp_user_dout_o15;
-    output fabric_otp_user_dout_o16;
-    output fabric_otp_user_dout_o17;
-    output fabric_otp_user_dout_o18;
-    output fabric_otp_user_dout_o19;
-    output fabric_otp_user_dout_o2;
-    output fabric_otp_user_dout_o20;
-    output fabric_otp_user_dout_o21;
-    output fabric_otp_user_dout_o22;
-    output fabric_otp_user_dout_o23;
-    output fabric_otp_user_dout_o24;
-    output fabric_otp_user_dout_o25;
-    output fabric_otp_user_dout_o26;
-    output fabric_otp_user_dout_o27;
-    output fabric_otp_user_dout_o28;
-    output fabric_otp_user_dout_o29;
-    output fabric_otp_user_dout_o3;
-    output fabric_otp_user_dout_o30;
-    output fabric_otp_user_dout_o31;
-    output fabric_otp_user_dout_o32;
-    output fabric_otp_user_dout_o33;
-    output fabric_otp_user_dout_o34;
-    output fabric_otp_user_dout_o35;
-    output fabric_otp_user_dout_o36;
-    output fabric_otp_user_dout_o37;
-    output fabric_otp_user_dout_o38;
-    output fabric_otp_user_dout_o39;
-    output fabric_otp_user_dout_o4;
-    output fabric_otp_user_dout_o40;
-    output fabric_otp_user_dout_o41;
-    output fabric_otp_user_dout_o5;
-    output fabric_otp_user_dout_o6;
-    output fabric_otp_user_dout_o7;
-    output fabric_otp_user_dout_o8;
-    output fabric_otp_user_dout_o9;
-    input fabric_otp_user_eccbypass_i;
-    output fabric_otp_user_flagstate_o1;
-    output fabric_otp_user_flagstate_o2;
-    output fabric_otp_user_flagstate_o3;
-    output fabric_otp_user_flagstate_o4;
-    output fabric_otp_user_locked_o;
-    input fabric_otp_user_pdn_i;
-    input fabric_otp_user_prgwidth_i1;
-    input fabric_otp_user_prgwidth_i2;
-    input fabric_otp_user_prgwidth_i3;
-    input fabric_otp_user_prog_i;
-    output fabric_otp_user_progfail_o;
-    output fabric_otp_user_pwok_o;
-    input fabric_otp_user_rbact1_i;
-    input fabric_otp_user_rbact2_i;
-    input fabric_otp_user_read_i;
-    input fabric_otp_user_redbypass_i;
-    output fabric_otp_user_sec_o;
-    output fabric_otp_user_startword_o1;
-    output fabric_otp_user_startword_o10;
-    output fabric_otp_user_startword_o11;
-    output fabric_otp_user_startword_o12;
-    output fabric_otp_user_startword_o13;
-    output fabric_otp_user_startword_o14;
-    output fabric_otp_user_startword_o15;
-    output fabric_otp_user_startword_o16;
-    output fabric_otp_user_startword_o2;
-    output fabric_otp_user_startword_o3;
-    output fabric_otp_user_startword_o4;
-    output fabric_otp_user_startword_o5;
-    output fabric_otp_user_startword_o6;
-    output fabric_otp_user_startword_o7;
-    output fabric_otp_user_startword_o8;
-    output fabric_otp_user_startword_o9;
-    input fabric_otp_user_suppadd_i;
-    input fabric_otp_user_tm_i;
-    input fabric_otp_user_tst_scanenable_i;
-    input fabric_otp_user_tst_scanin_i1;
-    input fabric_otp_user_tst_scanin_i2;
-    input fabric_otp_user_tst_scanin_i3;
-    input fabric_otp_user_tst_scanin_i4;
-    input fabric_otp_user_tst_scanin_i5;
-    output fabric_otp_user_tst_scanout_o1;
-    output fabric_otp_user_tst_scanout_o2;
-    output fabric_otp_user_tst_scanout_o3;
-    output fabric_otp_user_tst_scanout_o4;
-    output fabric_otp_user_tst_scanout_o5;
-    output fabric_otp_user_wlromout_o1;
-    output fabric_otp_user_wlromout_o10;
-    output fabric_otp_user_wlromout_o2;
-    output fabric_otp_user_wlromout_o3;
-    output fabric_otp_user_wlromout_o4;
-    output fabric_otp_user_wlromout_o5;
-    output fabric_otp_user_wlromout_o6;
-    output fabric_otp_user_wlromout_o7;
-    output fabric_otp_user_wlromout_o8;
-    output fabric_otp_user_wlromout_o9;
-    input fabric_otp_user_wordlock_i;
-    input fabric_parusr_cs_i;
-    input fabric_parusr_data_i1;
-    input fabric_parusr_data_i10;
-    input fabric_parusr_data_i11;
-    input fabric_parusr_data_i12;
-    input fabric_parusr_data_i13;
-    input fabric_parusr_data_i14;
-    input fabric_parusr_data_i15;
-    input fabric_parusr_data_i16;
-    input fabric_parusr_data_i2;
-    input fabric_parusr_data_i3;
-    input fabric_parusr_data_i4;
-    input fabric_parusr_data_i5;
-    input fabric_parusr_data_i6;
-    input fabric_parusr_data_i7;
-    input fabric_parusr_data_i8;
-    input fabric_parusr_data_i9;
-    output fabric_parusr_data_o1;
-    output fabric_parusr_data_o10;
-    output fabric_parusr_data_o11;
-    output fabric_parusr_data_o12;
-    output fabric_parusr_data_o13;
-    output fabric_parusr_data_o14;
-    output fabric_parusr_data_o15;
-    output fabric_parusr_data_o16;
-    output fabric_parusr_data_o2;
-    output fabric_parusr_data_o3;
-    output fabric_parusr_data_o4;
-    output fabric_parusr_data_o5;
-    output fabric_parusr_data_o6;
-    output fabric_parusr_data_o7;
-    output fabric_parusr_data_o8;
-    output fabric_parusr_data_o9;
-    output fabric_parusr_data_val_o;
-    input fabric_parusr_type_i1;
-    input fabric_parusr_type_i2;
-    input fabric_pd_active_i1;
-    input fabric_pd_active_i10;
-    input fabric_pd_active_i11;
-    input fabric_pd_active_i12;
-    input fabric_pd_active_i13;
-    input fabric_pd_active_i14;
-    input fabric_pd_active_i15;
-    input fabric_pd_active_i16;
-    input fabric_pd_active_i17;
-    input fabric_pd_active_i18;
-    input fabric_pd_active_i19;
-    input fabric_pd_active_i2;
-    input fabric_pd_active_i20;
-    input fabric_pd_active_i21;
-    input fabric_pd_active_i22;
-    input fabric_pd_active_i23;
-    input fabric_pd_active_i24;
-    input fabric_pd_active_i3;
-    input fabric_pd_active_i4;
-    input fabric_pd_active_i5;
-    input fabric_pd_active_i6;
-    input fabric_pd_active_i7;
-    input fabric_pd_active_i8;
-    input fabric_pd_active_i9;
-    output fabric_pd_ready_o1;
-    output fabric_pd_ready_o10;
-    output fabric_pd_ready_o11;
-    output fabric_pd_ready_o12;
-    output fabric_pd_ready_o13;
-    output fabric_pd_ready_o14;
-    output fabric_pd_ready_o15;
-    output fabric_pd_ready_o16;
-    output fabric_pd_ready_o17;
-    output fabric_pd_ready_o18;
-    output fabric_pd_ready_o19;
-    output fabric_pd_ready_o2;
-    output fabric_pd_ready_o20;
-    output fabric_pd_ready_o21;
-    output fabric_pd_ready_o22;
-    output fabric_pd_ready_o23;
-    output fabric_pd_ready_o24;
-    output fabric_pd_ready_o3;
-    output fabric_pd_ready_o4;
-    output fabric_pd_ready_o5;
-    output fabric_pd_ready_o6;
-    output fabric_pd_ready_o7;
-    output fabric_pd_ready_o8;
-    output fabric_pd_ready_o9;
-    input fabric_shift_en_i1;
-    input fabric_shift_en_i10;
-    input fabric_shift_en_i11;
-    input fabric_shift_en_i12;
-    input fabric_shift_en_i13;
-    input fabric_shift_en_i14;
-    input fabric_shift_en_i15;
-    input fabric_shift_en_i16;
-    input fabric_shift_en_i17;
-    input fabric_shift_en_i18;
-    input fabric_shift_en_i19;
-    input fabric_shift_en_i2;
-    input fabric_shift_en_i20;
-    input fabric_shift_en_i21;
-    input fabric_shift_en_i22;
-    input fabric_shift_en_i23;
-    input fabric_shift_en_i24;
-    input fabric_shift_en_i3;
-    input fabric_shift_en_i4;
-    input fabric_shift_en_i5;
-    input fabric_shift_en_i6;
-    input fabric_shift_en_i7;
-    input fabric_shift_en_i8;
-    input fabric_shift_en_i9;
-    output fabric_shift_en_to_bist_o1;
-    output fabric_shift_en_to_bist_o10;
-    output fabric_shift_en_to_bist_o11;
-    output fabric_shift_en_to_bist_o12;
-    output fabric_shift_en_to_bist_o13;
-    output fabric_shift_en_to_bist_o14;
-    output fabric_shift_en_to_bist_o15;
-    output fabric_shift_en_to_bist_o16;
-    output fabric_shift_en_to_bist_o17;
-    output fabric_shift_en_to_bist_o18;
-    output fabric_shift_en_to_bist_o19;
-    output fabric_shift_en_to_bist_o2;
-    output fabric_shift_en_to_bist_o20;
-    output fabric_shift_en_to_bist_o21;
-    output fabric_shift_en_to_bist_o22;
-    output fabric_shift_en_to_bist_o23;
-    output fabric_shift_en_to_bist_o24;
-    output fabric_shift_en_to_bist_o3;
-    output fabric_shift_en_to_bist_o4;
-    output fabric_shift_en_to_bist_o5;
-    output fabric_shift_en_to_bist_o6;
-    output fabric_shift_en_to_bist_o7;
-    output fabric_shift_en_to_bist_o8;
-    output fabric_shift_en_to_bist_o9;
-    input fabric_sif_load_en_i1;
-    input fabric_sif_load_en_i10;
-    input fabric_sif_load_en_i11;
-    input fabric_sif_load_en_i12;
-    input fabric_sif_load_en_i13;
-    input fabric_sif_load_en_i14;
-    input fabric_sif_load_en_i15;
-    input fabric_sif_load_en_i16;
-    input fabric_sif_load_en_i17;
-    input fabric_sif_load_en_i18;
-    input fabric_sif_load_en_i19;
-    input fabric_sif_load_en_i2;
-    input fabric_sif_load_en_i20;
-    input fabric_sif_load_en_i21;
-    input fabric_sif_load_en_i22;
-    input fabric_sif_load_en_i23;
-    input fabric_sif_load_en_i24;
-    input fabric_sif_load_en_i3;
-    input fabric_sif_load_en_i4;
-    input fabric_sif_load_en_i5;
-    input fabric_sif_load_en_i6;
-    input fabric_sif_load_en_i7;
-    input fabric_sif_load_en_i8;
-    input fabric_sif_load_en_i9;
-    output fabric_sif_load_en_to_bist_o1;
-    output fabric_sif_load_en_to_bist_o10;
-    output fabric_sif_load_en_to_bist_o11;
-    output fabric_sif_load_en_to_bist_o12;
-    output fabric_sif_load_en_to_bist_o13;
-    output fabric_sif_load_en_to_bist_o14;
-    output fabric_sif_load_en_to_bist_o15;
-    output fabric_sif_load_en_to_bist_o16;
-    output fabric_sif_load_en_to_bist_o17;
-    output fabric_sif_load_en_to_bist_o18;
-    output fabric_sif_load_en_to_bist_o19;
-    output fabric_sif_load_en_to_bist_o2;
-    output fabric_sif_load_en_to_bist_o20;
-    output fabric_sif_load_en_to_bist_o21;
-    output fabric_sif_load_en_to_bist_o22;
-    output fabric_sif_load_en_to_bist_o23;
-    output fabric_sif_load_en_to_bist_o24;
-    output fabric_sif_load_en_to_bist_o3;
-    output fabric_sif_load_en_to_bist_o4;
-    output fabric_sif_load_en_to_bist_o5;
-    output fabric_sif_load_en_to_bist_o6;
-    output fabric_sif_load_en_to_bist_o7;
-    output fabric_sif_load_en_to_bist_o8;
-    output fabric_sif_load_en_to_bist_o9;
-    input fabric_sif_reg_en_i1;
-    input fabric_sif_reg_en_i10;
-    input fabric_sif_reg_en_i100;
-    input fabric_sif_reg_en_i101;
-    input fabric_sif_reg_en_i102;
-    input fabric_sif_reg_en_i103;
-    input fabric_sif_reg_en_i104;
-    input fabric_sif_reg_en_i105;
-    input fabric_sif_reg_en_i106;
-    input fabric_sif_reg_en_i107;
-    input fabric_sif_reg_en_i108;
-    input fabric_sif_reg_en_i109;
-    input fabric_sif_reg_en_i11;
-    input fabric_sif_reg_en_i110;
-    input fabric_sif_reg_en_i111;
-    input fabric_sif_reg_en_i112;
-    input fabric_sif_reg_en_i113;
-    input fabric_sif_reg_en_i114;
-    input fabric_sif_reg_en_i115;
-    input fabric_sif_reg_en_i116;
-    input fabric_sif_reg_en_i117;
-    input fabric_sif_reg_en_i118;
-    input fabric_sif_reg_en_i119;
-    input fabric_sif_reg_en_i12;
-    input fabric_sif_reg_en_i120;
-    input fabric_sif_reg_en_i13;
-    input fabric_sif_reg_en_i14;
-    input fabric_sif_reg_en_i15;
-    input fabric_sif_reg_en_i16;
-    input fabric_sif_reg_en_i17;
-    input fabric_sif_reg_en_i18;
-    input fabric_sif_reg_en_i19;
-    input fabric_sif_reg_en_i2;
-    input fabric_sif_reg_en_i20;
-    input fabric_sif_reg_en_i21;
-    input fabric_sif_reg_en_i22;
-    input fabric_sif_reg_en_i23;
-    input fabric_sif_reg_en_i24;
-    input fabric_sif_reg_en_i25;
-    input fabric_sif_reg_en_i26;
-    input fabric_sif_reg_en_i27;
-    input fabric_sif_reg_en_i28;
-    input fabric_sif_reg_en_i29;
-    input fabric_sif_reg_en_i3;
-    input fabric_sif_reg_en_i30;
-    input fabric_sif_reg_en_i31;
-    input fabric_sif_reg_en_i32;
-    input fabric_sif_reg_en_i33;
-    input fabric_sif_reg_en_i34;
-    input fabric_sif_reg_en_i35;
-    input fabric_sif_reg_en_i36;
-    input fabric_sif_reg_en_i37;
-    input fabric_sif_reg_en_i38;
-    input fabric_sif_reg_en_i39;
-    input fabric_sif_reg_en_i4;
-    input fabric_sif_reg_en_i40;
-    input fabric_sif_reg_en_i41;
-    input fabric_sif_reg_en_i42;
-    input fabric_sif_reg_en_i43;
-    input fabric_sif_reg_en_i44;
-    input fabric_sif_reg_en_i45;
-    input fabric_sif_reg_en_i46;
-    input fabric_sif_reg_en_i47;
-    input fabric_sif_reg_en_i48;
-    input fabric_sif_reg_en_i49;
-    input fabric_sif_reg_en_i5;
-    input fabric_sif_reg_en_i50;
-    input fabric_sif_reg_en_i51;
-    input fabric_sif_reg_en_i52;
-    input fabric_sif_reg_en_i53;
-    input fabric_sif_reg_en_i54;
-    input fabric_sif_reg_en_i55;
-    input fabric_sif_reg_en_i56;
-    input fabric_sif_reg_en_i57;
-    input fabric_sif_reg_en_i58;
-    input fabric_sif_reg_en_i59;
-    input fabric_sif_reg_en_i6;
-    input fabric_sif_reg_en_i60;
-    input fabric_sif_reg_en_i61;
-    input fabric_sif_reg_en_i62;
-    input fabric_sif_reg_en_i63;
-    input fabric_sif_reg_en_i64;
-    input fabric_sif_reg_en_i65;
-    input fabric_sif_reg_en_i66;
-    input fabric_sif_reg_en_i67;
-    input fabric_sif_reg_en_i68;
-    input fabric_sif_reg_en_i69;
-    input fabric_sif_reg_en_i7;
-    input fabric_sif_reg_en_i70;
-    input fabric_sif_reg_en_i71;
-    input fabric_sif_reg_en_i72;
-    input fabric_sif_reg_en_i73;
-    input fabric_sif_reg_en_i74;
-    input fabric_sif_reg_en_i75;
-    input fabric_sif_reg_en_i76;
-    input fabric_sif_reg_en_i77;
-    input fabric_sif_reg_en_i78;
-    input fabric_sif_reg_en_i79;
-    input fabric_sif_reg_en_i8;
-    input fabric_sif_reg_en_i80;
-    input fabric_sif_reg_en_i81;
-    input fabric_sif_reg_en_i82;
-    input fabric_sif_reg_en_i83;
-    input fabric_sif_reg_en_i84;
-    input fabric_sif_reg_en_i85;
-    input fabric_sif_reg_en_i86;
-    input fabric_sif_reg_en_i87;
-    input fabric_sif_reg_en_i88;
-    input fabric_sif_reg_en_i89;
-    input fabric_sif_reg_en_i9;
-    input fabric_sif_reg_en_i90;
-    input fabric_sif_reg_en_i91;
-    input fabric_sif_reg_en_i92;
-    input fabric_sif_reg_en_i93;
-    input fabric_sif_reg_en_i94;
-    input fabric_sif_reg_en_i95;
-    input fabric_sif_reg_en_i96;
-    input fabric_sif_reg_en_i97;
-    input fabric_sif_reg_en_i98;
-    input fabric_sif_reg_en_i99;
-    output fabric_sif_reg_en_to_bist_o1;
-    output fabric_sif_reg_en_to_bist_o10;
-    output fabric_sif_reg_en_to_bist_o100;
-    output fabric_sif_reg_en_to_bist_o101;
-    output fabric_sif_reg_en_to_bist_o102;
-    output fabric_sif_reg_en_to_bist_o103;
-    output fabric_sif_reg_en_to_bist_o104;
-    output fabric_sif_reg_en_to_bist_o105;
-    output fabric_sif_reg_en_to_bist_o106;
-    output fabric_sif_reg_en_to_bist_o107;
-    output fabric_sif_reg_en_to_bist_o108;
-    output fabric_sif_reg_en_to_bist_o109;
-    output fabric_sif_reg_en_to_bist_o11;
-    output fabric_sif_reg_en_to_bist_o110;
-    output fabric_sif_reg_en_to_bist_o111;
-    output fabric_sif_reg_en_to_bist_o112;
-    output fabric_sif_reg_en_to_bist_o113;
-    output fabric_sif_reg_en_to_bist_o114;
-    output fabric_sif_reg_en_to_bist_o115;
-    output fabric_sif_reg_en_to_bist_o116;
-    output fabric_sif_reg_en_to_bist_o117;
-    output fabric_sif_reg_en_to_bist_o118;
-    output fabric_sif_reg_en_to_bist_o119;
-    output fabric_sif_reg_en_to_bist_o12;
-    output fabric_sif_reg_en_to_bist_o120;
-    output fabric_sif_reg_en_to_bist_o13;
-    output fabric_sif_reg_en_to_bist_o14;
-    output fabric_sif_reg_en_to_bist_o15;
-    output fabric_sif_reg_en_to_bist_o16;
-    output fabric_sif_reg_en_to_bist_o17;
-    output fabric_sif_reg_en_to_bist_o18;
-    output fabric_sif_reg_en_to_bist_o19;
-    output fabric_sif_reg_en_to_bist_o2;
-    output fabric_sif_reg_en_to_bist_o20;
-    output fabric_sif_reg_en_to_bist_o21;
-    output fabric_sif_reg_en_to_bist_o22;
-    output fabric_sif_reg_en_to_bist_o23;
-    output fabric_sif_reg_en_to_bist_o24;
-    output fabric_sif_reg_en_to_bist_o25;
-    output fabric_sif_reg_en_to_bist_o26;
-    output fabric_sif_reg_en_to_bist_o27;
-    output fabric_sif_reg_en_to_bist_o28;
-    output fabric_sif_reg_en_to_bist_o29;
-    output fabric_sif_reg_en_to_bist_o3;
-    output fabric_sif_reg_en_to_bist_o30;
-    output fabric_sif_reg_en_to_bist_o31;
-    output fabric_sif_reg_en_to_bist_o32;
-    output fabric_sif_reg_en_to_bist_o33;
-    output fabric_sif_reg_en_to_bist_o34;
-    output fabric_sif_reg_en_to_bist_o35;
-    output fabric_sif_reg_en_to_bist_o36;
-    output fabric_sif_reg_en_to_bist_o37;
-    output fabric_sif_reg_en_to_bist_o38;
-    output fabric_sif_reg_en_to_bist_o39;
-    output fabric_sif_reg_en_to_bist_o4;
-    output fabric_sif_reg_en_to_bist_o40;
-    output fabric_sif_reg_en_to_bist_o41;
-    output fabric_sif_reg_en_to_bist_o42;
-    output fabric_sif_reg_en_to_bist_o43;
-    output fabric_sif_reg_en_to_bist_o44;
-    output fabric_sif_reg_en_to_bist_o45;
-    output fabric_sif_reg_en_to_bist_o46;
-    output fabric_sif_reg_en_to_bist_o47;
-    output fabric_sif_reg_en_to_bist_o48;
-    output fabric_sif_reg_en_to_bist_o49;
-    output fabric_sif_reg_en_to_bist_o5;
-    output fabric_sif_reg_en_to_bist_o50;
-    output fabric_sif_reg_en_to_bist_o51;
-    output fabric_sif_reg_en_to_bist_o52;
-    output fabric_sif_reg_en_to_bist_o53;
-    output fabric_sif_reg_en_to_bist_o54;
-    output fabric_sif_reg_en_to_bist_o55;
-    output fabric_sif_reg_en_to_bist_o56;
-    output fabric_sif_reg_en_to_bist_o57;
-    output fabric_sif_reg_en_to_bist_o58;
-    output fabric_sif_reg_en_to_bist_o59;
-    output fabric_sif_reg_en_to_bist_o6;
-    output fabric_sif_reg_en_to_bist_o60;
-    output fabric_sif_reg_en_to_bist_o61;
-    output fabric_sif_reg_en_to_bist_o62;
-    output fabric_sif_reg_en_to_bist_o63;
-    output fabric_sif_reg_en_to_bist_o64;
-    output fabric_sif_reg_en_to_bist_o65;
-    output fabric_sif_reg_en_to_bist_o66;
-    output fabric_sif_reg_en_to_bist_o67;
-    output fabric_sif_reg_en_to_bist_o68;
-    output fabric_sif_reg_en_to_bist_o69;
-    output fabric_sif_reg_en_to_bist_o7;
-    output fabric_sif_reg_en_to_bist_o70;
-    output fabric_sif_reg_en_to_bist_o71;
-    output fabric_sif_reg_en_to_bist_o72;
-    output fabric_sif_reg_en_to_bist_o73;
-    output fabric_sif_reg_en_to_bist_o74;
-    output fabric_sif_reg_en_to_bist_o75;
-    output fabric_sif_reg_en_to_bist_o76;
-    output fabric_sif_reg_en_to_bist_o77;
-    output fabric_sif_reg_en_to_bist_o78;
-    output fabric_sif_reg_en_to_bist_o79;
-    output fabric_sif_reg_en_to_bist_o8;
-    output fabric_sif_reg_en_to_bist_o80;
-    output fabric_sif_reg_en_to_bist_o81;
-    output fabric_sif_reg_en_to_bist_o82;
-    output fabric_sif_reg_en_to_bist_o83;
-    output fabric_sif_reg_en_to_bist_o84;
-    output fabric_sif_reg_en_to_bist_o85;
-    output fabric_sif_reg_en_to_bist_o86;
-    output fabric_sif_reg_en_to_bist_o87;
-    output fabric_sif_reg_en_to_bist_o88;
-    output fabric_sif_reg_en_to_bist_o89;
-    output fabric_sif_reg_en_to_bist_o9;
-    output fabric_sif_reg_en_to_bist_o90;
-    output fabric_sif_reg_en_to_bist_o91;
-    output fabric_sif_reg_en_to_bist_o92;
-    output fabric_sif_reg_en_to_bist_o93;
-    output fabric_sif_reg_en_to_bist_o94;
-    output fabric_sif_reg_en_to_bist_o95;
-    output fabric_sif_reg_en_to_bist_o96;
-    output fabric_sif_reg_en_to_bist_o97;
-    output fabric_sif_reg_en_to_bist_o98;
-    output fabric_sif_reg_en_to_bist_o99;
-    input fabric_sif_update_en_i1;
-    input fabric_sif_update_en_i10;
-    input fabric_sif_update_en_i11;
-    input fabric_sif_update_en_i12;
-    input fabric_sif_update_en_i13;
-    input fabric_sif_update_en_i14;
-    input fabric_sif_update_en_i15;
-    input fabric_sif_update_en_i16;
-    input fabric_sif_update_en_i17;
-    input fabric_sif_update_en_i18;
-    input fabric_sif_update_en_i19;
-    input fabric_sif_update_en_i2;
-    input fabric_sif_update_en_i20;
-    input fabric_sif_update_en_i21;
-    input fabric_sif_update_en_i22;
-    input fabric_sif_update_en_i23;
-    input fabric_sif_update_en_i24;
-    input fabric_sif_update_en_i3;
-    input fabric_sif_update_en_i4;
-    input fabric_sif_update_en_i5;
-    input fabric_sif_update_en_i6;
-    input fabric_sif_update_en_i7;
-    input fabric_sif_update_en_i8;
-    input fabric_sif_update_en_i9;
-    output fabric_sif_update_en_to_bist_o1;
-    output fabric_sif_update_en_to_bist_o10;
-    output fabric_sif_update_en_to_bist_o11;
-    output fabric_sif_update_en_to_bist_o12;
-    output fabric_sif_update_en_to_bist_o13;
-    output fabric_sif_update_en_to_bist_o14;
-    output fabric_sif_update_en_to_bist_o15;
-    output fabric_sif_update_en_to_bist_o16;
-    output fabric_sif_update_en_to_bist_o17;
-    output fabric_sif_update_en_to_bist_o18;
-    output fabric_sif_update_en_to_bist_o19;
-    output fabric_sif_update_en_to_bist_o2;
-    output fabric_sif_update_en_to_bist_o20;
-    output fabric_sif_update_en_to_bist_o21;
-    output fabric_sif_update_en_to_bist_o22;
-    output fabric_sif_update_en_to_bist_o23;
-    output fabric_sif_update_en_to_bist_o24;
-    output fabric_sif_update_en_to_bist_o3;
-    output fabric_sif_update_en_to_bist_o4;
-    output fabric_sif_update_en_to_bist_o5;
-    output fabric_sif_update_en_to_bist_o6;
-    output fabric_sif_update_en_to_bist_o7;
-    output fabric_sif_update_en_to_bist_o8;
-    output fabric_sif_update_en_to_bist_o9;
-    input fabric_spare_i1;
-    input fabric_spare_i2;
-    input fabric_spare_i3;
-    output fabric_status_cold_start_o;
-    output fabric_system_data_from_mem_bist_o1;
-    output fabric_system_data_from_mem_bist_o10;
-    output fabric_system_data_from_mem_bist_o11;
-    output fabric_system_data_from_mem_bist_o12;
-    output fabric_system_data_from_mem_bist_o13;
-    output fabric_system_data_from_mem_bist_o14;
-    output fabric_system_data_from_mem_bist_o15;
-    output fabric_system_data_from_mem_bist_o16;
-    output fabric_system_data_from_mem_bist_o17;
-    output fabric_system_data_from_mem_bist_o18;
-    output fabric_system_data_from_mem_bist_o19;
-    output fabric_system_data_from_mem_bist_o2;
-    output fabric_system_data_from_mem_bist_o20;
-    output fabric_system_data_from_mem_bist_o21;
-    output fabric_system_data_from_mem_bist_o22;
-    output fabric_system_data_from_mem_bist_o23;
-    output fabric_system_data_from_mem_bist_o24;
-    output fabric_system_data_from_mem_bist_o3;
-    output fabric_system_data_from_mem_bist_o4;
-    output fabric_system_data_from_mem_bist_o5;
-    output fabric_system_data_from_mem_bist_o6;
-    output fabric_system_data_from_mem_bist_o7;
-    output fabric_system_data_from_mem_bist_o8;
-    output fabric_system_data_from_mem_bist_o9;
-    input fabric_system_data_to_mem_bist_i1;
-    input fabric_system_data_to_mem_bist_i10;
-    input fabric_system_data_to_mem_bist_i11;
-    input fabric_system_data_to_mem_bist_i12;
-    input fabric_system_data_to_mem_bist_i13;
-    input fabric_system_data_to_mem_bist_i14;
-    input fabric_system_data_to_mem_bist_i15;
-    input fabric_system_data_to_mem_bist_i16;
-    input fabric_system_data_to_mem_bist_i17;
-    input fabric_system_data_to_mem_bist_i18;
-    input fabric_system_data_to_mem_bist_i19;
-    input fabric_system_data_to_mem_bist_i2;
-    input fabric_system_data_to_mem_bist_i20;
-    input fabric_system_data_to_mem_bist_i21;
-    input fabric_system_data_to_mem_bist_i22;
-    input fabric_system_data_to_mem_bist_i23;
-    input fabric_system_data_to_mem_bist_i24;
-    input fabric_system_data_to_mem_bist_i3;
-    input fabric_system_data_to_mem_bist_i4;
-    input fabric_system_data_to_mem_bist_i5;
-    input fabric_system_data_to_mem_bist_i6;
-    input fabric_system_data_to_mem_bist_i7;
-    input fabric_system_data_to_mem_bist_i8;
-    input fabric_system_data_to_mem_bist_i9;
-    output fabric_system_dataready_o;
-    input fabric_tst_atpg_mrepair_i;
-    input fabric_user_data_i1;
-    input fabric_user_data_i10;
-    input fabric_user_data_i11;
-    input fabric_user_data_i12;
-    input fabric_user_data_i13;
-    input fabric_user_data_i14;
-    input fabric_user_data_i15;
-    input fabric_user_data_i16;
-    input fabric_user_data_i17;
-    input fabric_user_data_i18;
-    input fabric_user_data_i19;
-    input fabric_user_data_i2;
-    input fabric_user_data_i20;
-    input fabric_user_data_i21;
-    input fabric_user_data_i22;
-    input fabric_user_data_i23;
-    input fabric_user_data_i24;
-    input fabric_user_data_i25;
-    input fabric_user_data_i26;
-    input fabric_user_data_i27;
-    input fabric_user_data_i28;
-    input fabric_user_data_i29;
-    input fabric_user_data_i3;
-    input fabric_user_data_i30;
-    input fabric_user_data_i31;
-    input fabric_user_data_i32;
-    input fabric_user_data_i4;
-    input fabric_user_data_i5;
-    input fabric_user_data_i6;
-    input fabric_user_data_i7;
-    input fabric_user_data_i8;
-    input fabric_user_data_i9;
-    output fabric_user_data_o1;
-    output fabric_user_data_o10;
-    output fabric_user_data_o11;
-    output fabric_user_data_o12;
-    output fabric_user_data_o13;
-    output fabric_user_data_o14;
-    output fabric_user_data_o15;
-    output fabric_user_data_o16;
-    output fabric_user_data_o17;
-    output fabric_user_data_o18;
-    output fabric_user_data_o19;
-    output fabric_user_data_o2;
-    output fabric_user_data_o20;
-    output fabric_user_data_o21;
-    output fabric_user_data_o22;
-    output fabric_user_data_o23;
-    output fabric_user_data_o24;
-    output fabric_user_data_o25;
-    output fabric_user_data_o26;
-    output fabric_user_data_o27;
-    output fabric_user_data_o28;
-    output fabric_user_data_o29;
-    output fabric_user_data_o3;
-    output fabric_user_data_o30;
-    output fabric_user_data_o31;
-    output fabric_user_data_o32;
-    output fabric_user_data_o4;
-    output fabric_user_data_o5;
-    output fabric_user_data_o6;
-    output fabric_user_data_o7;
-    output fabric_user_data_o8;
-    output fabric_user_data_o9;
-    output fabric_user_read_cycle_o;
-    output fabric_user_write_cycle_o;
-    parameter ahb_config = 0;
-    parameter bsm_config = 0;
-endmodule
-
-(* blackbox *)
-module NX_SERVICE_U_V1_WRAP(fabric_otp_user_tst_scanenable_i, fabric_otp_cfg_loader_read_en_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_scanenable_i, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_user_disturbcheck_i, fabric_mrepair_fuse_read_i, fabric_otp_user_rbact2_i, fabric_mrepair_fuse_eccbypass_i, fabric_otp_user_bistmode_i, fabric_otp_user_tm_i, fabric_otp_rstn_i, fabric_mrepair_fuse_disturbchecked_i, fabric_otp_user_rbact1_i, fabric_mrepair_fuse_redbypass_i, fabric_otp_user_eccbypass_i, fabric_otp_user_redbypass_i, fabric_parusr_cs_i, fabric_mrepair_fuse_rbact2_i, fabric_data_from_system_i, fabric_otp_apb_enable_i
-, fabric_mrepair_fuse_tm_i, fabric_otp_security_rbact2_i, fabric_otp_security_rbact1_i, fabric_otp_cfg_loader_write_en_i, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_prog_i, fabric_otp_user_wordlock_i, fabric_otp_user_prog_i, fabric_otp_user_suppadd_i, fabric_mrepair_fuse_pdn_i, fabric_end_encoding_i, fabric_jtag_tdo_usr2_i, fabric_mrepair_fuse_wordlock_i, fabric_otp_user_read_i, fabric_mrepair_fuse_bistmode_i, fabric_jtag_tdo_usr1_i, fabric_otp_cfg_clk_fab_en_i, fabric_otp_apb_sel_i, fabric_mrepair_fuse_rbact1_i, fabric_otp_cfg_fabric_apb_en_i, fabric_data_shift_en_i
-, fabric_lowskew_i21, fabric_otp_user_pdn_i, fabric_otp_apb_write_i, fabric_otp_security_testmode_i, fabric_tst_atpg_mrepair_i, fabric_mrepair_fuse_tstscanenable_i, fabric_otp_security_bistmode_i, fabric_lowskew_i22, fabric_lowskew_i23, fabric_lowskew_i20, fabric_mrepair_por_i, fabric_mrepair_rst_n_i, fabric_mrepair_initn_i, fabric_mrepair_fuse_bbad_o, fabric_jtag_trst_n_o, fabric_otp_security_bist_end1_o, fabric_parusr_data_val_o, fabric_debug_lock_reg_o, fabric_debug_security_error_read_o, fabric_otp_user_locked_o, fabric_otp_security_bist_bad_o
-, fabric_otp_user_pwok_o, fabric_otp_user_bend2_o, fabric_mrepair_fuse_ded_o, fabric_debug_access_reg_data_ready_o, fabric_debug_otp_reload_err_o, fabric_cfg_fabric_user_unmask_o, fabric_decoder_init_ready_o, fabric_debug_security_boot_done_o, fabric_otp_user_calibrated_o, fabric_jtag_tms_o, fabric_flag_ready_o, fabric_debug_rst_soft_o, fabric_otp_user_ack_o, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_debug_otp_manager_read_otp_o, fabric_otp_user_sec_o, fabric_mrepair_fuse_bend1_o, fabric_otp_user_bbad_o, fabric_user_read_cycle_o, fabric_mrepair_fuse_disturbed_o, fabric_debug_key_correct_o
-, fabric_otp_apb_ready_o, fabric_otp_user_progfail_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_bend2_o, fabric_mrepair_fuse_ack_o, fabric_otp_security_ack_o, fabric_mrepair_fuse_progfail_o, fabric_jtag_tdi_o, fabric_lowskew_o3, fabric_lowskew_o5, fabric_lowskew_o4, fabric_debug_error_o, fabric_jtag_usr2_o, fabric_otp_user_disturbed_o, fabric_flag_trigger_o, fabric_otp_security_bist_end2_o, fabric_mrepair_fuse_locked_o, fabric_user_write_cycle_o, fabric_otp_user_ded_o, fabric_debug_otp_manager_read_done_o, fabric_debug_frame_use_encryption_o
-, fabric_data_to_system_o, fabric_jtag_usr1_o, fabric_otp_user_bend1_o, fabric_mrepair_fuse_ready_o, fabric_mrepair_fuse_calibrated_o, fabric_system_dataready_o, fabric_mrepair_fuse_pwok_o, fabric_lowskew_o6, fabric_cfg_fabric_user_flag_o, fabric_status_cold_start_o, fabric_flag_error_o, fabric_mrepair_mode_i, fabric_mrepair_fuse_add_i, fabric_mrepair_fuse_din_i, fabric_mrepair_fuse_tst_scanin_i, fabric_mrepair_fuse_prgwidth_i, fabric_mrepair_fuse_dout_o, fabric_mrepair_fuse_startword_o, fabric_mrepair_fuse_wlromout_o, fabric_mrepair_fuse_bist1fail_o, fabric_mrepair_fuse_bist2fail_o
-, fabric_mrepair_fuse_tstscanout_o, fabric_mrepair_fuse_flagstate_o, fabric_otp_user_add_i, fabric_otp_user_din_i, fabric_otp_user_prgwidth_i, fabric_otp_user_tst_scanin_i, fabric_otp_user_bist1fail_o, fabric_otp_user_bist2fail_o, fabric_otp_user_dout_o, fabric_otp_user_flagstate_o, fabric_otp_user_startword_o, fabric_otp_user_tst_scanout_o, fabric_otp_user_wlromout_o, fabric_io_in_i, fabric_io_oe_i, fabric_io_out_o, fabric_user_data_i, fabric_user_data_o, fabric_parusr_type_i, fabric_parusr_data_i, fabric_parusr_data_o
-, fabric_direct_data_i, fabric_direct_data_o, fabric_otp_apb_addr_i, fabric_otp_apb_wdata_i, fabric_otp_apb_rdata_o, fabric_otp_security_bist_fail1_o, fabric_otp_security_bist_fail2_o, fabric_otp_security_scanin_i, fabric_otp_security_scanout_o, fabric_debug_lifecycle_o, fabric_debug_fsm_state_o, fabric_debug_direct_permission_write_o, fabric_debug_direct_permission_read_o, fabric_debug_frame_permission_frame_o, fabric_debug_otpmgmt_state_o, fabric_debug_otpapb_state_o, fabric_debug_otpboot_state_o, fabric_debug_cpt_retry_o, fabric_debug_bsec_core_status_o, fabric_debug_otpboot_curr_addr_o, fabric_spare_i
-, fabric_sif_reg_en_i, fabric_data_from_bist_i, fabric_shift_en_i, fabric_ahb_direct_data_i, fabric_pd_active_i, fabric_sif_load_en_i, fabric_mrepair_fuse_configreg_i, fabric_system_data_to_mem_bist_i, fabric_otp_user_configreg_i, fabric_sif_update_en_i, fabric_sif_update_en_to_bist_o, fabric_data_to_bist_o, fabric_ahb_direct_data_o, fabric_global_chip_status_o, fabric_fuse_status_o, fabric_shift_en_to_bist_o, fabric_sif_reg_en_to_bist_o, fabric_system_data_from_mem_bist_o, fabric_chip_status_o, fabric_pd_ready_o, fabric_sif_load_en_to_bist_o
-);
-    input [31:0] fabric_ahb_direct_data_i;
-    output [31:0] fabric_ahb_direct_data_o;
-    output fabric_cfg_fabric_user_flag_o;
-    output fabric_cfg_fabric_user_unmask_o;
-    output [71:0] fabric_chip_status_o;
-    input [23:0] fabric_data_from_bist_i;
-    input fabric_data_from_system_i;
-    input fabric_data_shift_en_i;
-    output [23:0] fabric_data_to_bist_o;
-    output fabric_data_to_system_o;
-    output fabric_debug_access_reg_data_ready_o;
-    output [31:0] fabric_debug_bsec_core_status_o;
-    output [3:0] fabric_debug_cpt_retry_o;
-    output [3:0] fabric_debug_direct_permission_read_o;
-    output [3:0] fabric_debug_direct_permission_write_o;
-    output fabric_debug_error_o;
-    output [3:0] fabric_debug_frame_permission_frame_o;
-    output fabric_debug_frame_use_encryption_o;
-    output [2:0] fabric_debug_fsm_state_o;
-    output fabric_debug_key_correct_o;
-    output [3:0] fabric_debug_lifecycle_o;
-    output fabric_debug_lock_reg_o;
-    output fabric_debug_otp_manager_read_done_o;
-    output fabric_debug_otp_manager_read_otp_o;
-    output fabric_debug_otp_reload_err_o;
-    output [2:0] fabric_debug_otpapb_state_o;
-    output [7:0] fabric_debug_otpboot_curr_addr_o;
-    output [2:0] fabric_debug_otpboot_state_o;
-    output [2:0] fabric_debug_otpmgmt_state_o;
-    output fabric_debug_rst_soft_o;
-    output fabric_debug_security_boot_done_o;
-    output fabric_debug_security_error_read_o;
-    output fabric_decoder_init_ready_o;
-    input [31:0] fabric_direct_data_i;
-    output [31:0] fabric_direct_data_o;
-    input fabric_end_encoding_i;
-    output fabric_flag_error_o;
-    output fabric_flag_ready_o;
-    output fabric_flag_trigger_o;
-    output [2:0] fabric_fuse_status_o;
-    output [2:0] fabric_global_chip_status_o;
-    input [24:0] fabric_io_in_i;
-    input [24:0] fabric_io_oe_i;
-    output [24:0] fabric_io_out_o;
-    output fabric_jtag_tdi_o;
-    input fabric_jtag_tdo_usr1_i;
-    input fabric_jtag_tdo_usr2_i;
-    output fabric_jtag_tms_o;
-    output fabric_jtag_trst_n_o;
-    output fabric_jtag_usr1_o;
-    output fabric_jtag_usr2_o;
-    input fabric_lowskew_i20;
-    input fabric_lowskew_i21;
-    input fabric_lowskew_i22;
-    input fabric_lowskew_i23;
-    output fabric_lowskew_o3;
-    output fabric_lowskew_o4;
-    output fabric_lowskew_o5;
-    output fabric_lowskew_o6;
-    output fabric_mrepair_fuse_ack_o;
-    input [6:0] fabric_mrepair_fuse_add_i;
-    output fabric_mrepair_fuse_bbad_o;
-    output fabric_mrepair_fuse_bend1_o;
-    output fabric_mrepair_fuse_bend2_o;
-    output [7:0] fabric_mrepair_fuse_bist1fail_o;
-    output [6:0] fabric_mrepair_fuse_bist2fail_o;
-    input fabric_mrepair_fuse_bistmode_i;
-    output fabric_mrepair_fuse_calibrated_o;
-    input [31:0] fabric_mrepair_fuse_configreg_i;
-    output fabric_mrepair_fuse_ded_o;
-    input [38:0] fabric_mrepair_fuse_din_i;
-    input fabric_mrepair_fuse_disturbchecked_i;
-    output fabric_mrepair_fuse_disturbed_o;
-    output [40:0] fabric_mrepair_fuse_dout_o;
-    input fabric_mrepair_fuse_eccbypass_i;
-    output [3:0] fabric_mrepair_fuse_flagstate_o;
-    output fabric_mrepair_fuse_locked_o;
-    input fabric_mrepair_fuse_pdn_i;
-    output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o;
-    input [2:0] fabric_mrepair_fuse_prgwidth_i;
-    input fabric_mrepair_fuse_prog_i;
-    output fabric_mrepair_fuse_progfail_o;
-    output fabric_mrepair_fuse_pwok_o;
-    input fabric_mrepair_fuse_rbact1_i;
-    input fabric_mrepair_fuse_rbact2_i;
-    input fabric_mrepair_fuse_read_i;
-    output fabric_mrepair_fuse_ready_o;
-    input fabric_mrepair_fuse_redbypass_i;
-    output fabric_mrepair_fuse_sec_o;
-    output [15:0] fabric_mrepair_fuse_startword_o;
-    input fabric_mrepair_fuse_suppadd_i;
-    input fabric_mrepair_fuse_tm_i;
-    input [4:0] fabric_mrepair_fuse_tst_scanin_i;
-    input fabric_mrepair_fuse_tstscanenable_i;
-    output [4:0] fabric_mrepair_fuse_tstscanout_o;
-    output [9:0] fabric_mrepair_fuse_wlromout_o;
-    input fabric_mrepair_fuse_wordlock_i;
-    input fabric_mrepair_initn_i;
-    input [3:0] fabric_mrepair_mode_i;
-    input fabric_mrepair_por_i;
-    input fabric_mrepair_rst_n_i;
-    input [31:0] fabric_otp_apb_addr_i;
-    input fabric_otp_apb_enable_i;
-    output [31:0] fabric_otp_apb_rdata_o;
-    output fabric_otp_apb_ready_o;
-    input fabric_otp_apb_sel_i;
-    input [31:0] fabric_otp_apb_wdata_i;
-    input fabric_otp_apb_write_i;
-    input fabric_otp_cfg_clk_fab_en_i;
-    input fabric_otp_cfg_clk_otpm_disable_i;
-    input fabric_otp_cfg_fabric_apb_en_i;
-    input fabric_otp_cfg_loader_read_en_i;
-    input fabric_otp_cfg_loader_write_en_i;
-    input fabric_otp_rstn_i;
-    output fabric_otp_security_ack_o;
-    output fabric_otp_security_bist_bad_o;
-    output fabric_otp_security_bist_end1_o;
-    output fabric_otp_security_bist_end2_o;
-    output [7:0] fabric_otp_security_bist_fail1_o;
-    output [6:0] fabric_otp_security_bist_fail2_o;
-    input fabric_otp_security_bistmode_i;
-    input fabric_otp_security_force_pdn1_i;
-    input fabric_otp_security_rbact1_i;
-    input fabric_otp_security_rbact2_i;
-    input fabric_otp_security_scanenable_i;
-    input [4:0] fabric_otp_security_scanin_i;
-    output [4:0] fabric_otp_security_scanout_o;
-    input fabric_otp_security_testmode_i;
-    output fabric_otp_user_ack_o;
-    input [6:0] fabric_otp_user_add_i;
-    output fabric_otp_user_bbad_o;
-    output fabric_otp_user_bend1_o;
-    output fabric_otp_user_bend2_o;
-    output [7:0] fabric_otp_user_bist1fail_o;
-    output [6:0] fabric_otp_user_bist2fail_o;
-    input fabric_otp_user_bistmode_i;
-    output fabric_otp_user_calibrated_o;
-    input [31:0] fabric_otp_user_configreg_i;
-    output fabric_otp_user_ded_o;
-    input [38:0] fabric_otp_user_din_i;
-    input fabric_otp_user_disturbcheck_i;
-    output fabric_otp_user_disturbed_o;
-    output [40:0] fabric_otp_user_dout_o;
-    input fabric_otp_user_eccbypass_i;
-    output [3:0] fabric_otp_user_flagstate_o;
-    output fabric_otp_user_locked_o;
-    input fabric_otp_user_pdn_i;
-    input [2:0] fabric_otp_user_prgwidth_i;
-    input fabric_otp_user_prog_i;
-    output fabric_otp_user_progfail_o;
-    output fabric_otp_user_pwok_o;
-    input fabric_otp_user_rbact1_i;
-    input fabric_otp_user_rbact2_i;
-    input fabric_otp_user_read_i;
-    input fabric_otp_user_redbypass_i;
-    output fabric_otp_user_sec_o;
-    output [15:0] fabric_otp_user_startword_o;
-    input fabric_otp_user_suppadd_i;
-    input fabric_otp_user_tm_i;
-    input fabric_otp_user_tst_scanenable_i;
-    input [4:0] fabric_otp_user_tst_scanin_i;
-    output [4:0] fabric_otp_user_tst_scanout_o;
-    output [9:0] fabric_otp_user_wlromout_o;
-    input fabric_otp_user_wordlock_i;
-    input fabric_parusr_cs_i;
-    input [15:0] fabric_parusr_data_i;
-    output [15:0] fabric_parusr_data_o;
-    output fabric_parusr_data_val_o;
-    input [1:0] fabric_parusr_type_i;
-    input [23:0] fabric_pd_active_i;
-    output [23:0] fabric_pd_ready_o;
-    input [23:0] fabric_shift_en_i;
-    output [23:0] fabric_shift_en_to_bist_o;
-    input [23:0] fabric_sif_load_en_i;
-    output [23:0] fabric_sif_load_en_to_bist_o;
-    input [119:0] fabric_sif_reg_en_i;
-    output [119:0] fabric_sif_reg_en_to_bist_o;
-    input [23:0] fabric_sif_update_en_i;
-    output [23:0] fabric_sif_update_en_to_bist_o;
-    input [2:0] fabric_spare_i;
-    output fabric_status_cold_start_o;
-    output [23:0] fabric_system_data_from_mem_bist_o;
-    input [23:0] fabric_system_data_to_mem_bist_i;
-    output fabric_system_dataready_o;
-    input fabric_tst_atpg_mrepair_i;
-    input [31:0] fabric_user_data_i;
-    output [31:0] fabric_user_data_o;
-    output fabric_user_read_cycle_o;
-    output fabric_user_write_cycle_o;
-    parameter ahb_config = 0;
-    parameter bsm_config = 0;
-endmodule
-
-(* blackbox *)
-module NX_SERVICE_U_WRAP(fabric_otp_user_tst_scanenable_i, fabric_otp_cfg_loader_read_en_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_scanenable_i, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_user_disturbcheck_i, fabric_mrepair_fuse_read_i, fabric_otp_user_rbact2_i, fabric_mrepair_fuse_eccbypass_i, fabric_otp_user_bistmode_i, fabric_otp_user_tm_i, fabric_otp_rst_i, fabric_mrepair_fuse_disturbchecked_i, fabric_otp_user_rbact1_i, fabric_mrepair_fuse_redbypass_i, fabric_otp_user_eccbypass_i, fabric_otp_user_redbypass_i, fabric_parusr_cs_i, fabric_mrepair_fuse_rbact2_i, fabric_data_from_system_i, fabric_otp_apb_enable_i
-, fabric_mrepair_fuse_tm_i, fabric_otp_security_rbact2_i, fabric_otp_security_rbact1_i, fabric_otp_cfg_loader_write_en_i, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_prog_i, fabric_otp_user_wordlock_i, fabric_otp_user_prog_i, fabric_otp_user_suppadd_i, fabric_mrepair_fuse_pdn_i, fabric_end_encoding_i, fabric_jtag_tdo_usr2_i, fabric_mrepair_fuse_wordlock_i, fabric_otp_user_read_i, fabric_mrepair_fuse_bistmode_i, fabric_jtag_tdo_usr1_i, fabric_otp_cfg_clk_fab_en_i, fabric_otp_apb_sel_i, fabric_mrepair_fuse_rbact1_i, fabric_otp_cfg_fabric_apb_en_i, fabric_data_shift_en_i
-, fabric_lowskew_i21, fabric_otp_user_pdn_i, fabric_otp_apb_write_i, fabric_otp_security_testmode_i, fabric_tst_atpg_mrepair_i, fabric_mrepair_fuse_tstscanenable_i, fabric_otp_security_bistmode_i, fabric_lowskew_i22, fabric_lowskew_i23, fabric_lowskew_i20, fabric_mrepair_por_i, fabric_mrepair_cke_i, fabric_clk_otp_mux_i, fabric_mrepair_cke_force_i, fabric_mrepair_fuse_bbad_o, fabric_jtag_trst_n_o, fabric_otp_security_bist_end1_o, fabric_parusr_data_val_o, fabric_debug_lock_reg_o, fabric_debug_security_error_read_o, fabric_otp_user_locked_o
-, fabric_otp_security_bist_bad_o, fabric_otp_user_pwok_o, fabric_otp_user_bend2_o, fabric_mrepair_fuse_ded_o, fabric_debug_access_reg_data_ready_o, fabric_debug_otp_reload_err_o, fabric_cfg_fabric_user_enable_o, fabric_decoder_init_ready_o, fabric_debug_security_boot_done_o, fabric_otp_user_calibrated_o, fabric_jtag_tms_o, fabric_debug_rst_soft_o, fabric_otp_user_ack_o, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_debug_otp_manager_read_otp_o, fabric_otp_user_sec_o, fabric_mrepair_fuse_bend1_o, fabric_otp_user_bbad_o, fabric_user_read_cycle_o, fabric_mrepair_fuse_disturbed_o, fabric_debug_key_correct_o
-, fabric_otp_apb_ready_o, fabric_otp_user_progfail_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_bend2_o, fabric_mrepair_fuse_ack_o, fabric_otp_security_ack_o, fabric_mrepair_fuse_progfail_o, fabric_jtag_tdi_o, fabric_lowskew_o3, fabric_lowskew_o5, fabric_lowskew_o4, fabric_debug_error_o, fabric_jtag_usr2_o, fabric_otp_user_disturbed_o, fabric_flag_trigger_o, fabric_otp_security_bist_end2_o, fabric_mrepair_fuse_locked_o, fabric_user_write_cycle_o, fabric_otp_user_ded_o, fabric_debug_otp_manager_read_done_o, fabric_debug_frame_use_encryption_o
-, fabric_data_to_system_o, fabric_jtag_usr1_o, fabric_otp_user_bend1_o, fabric_mrepair_fuse_ready_o, fabric_mrepair_fuse_calibrated_o, fabric_system_dataready_o, fabric_mrepair_fuse_pwok_o, fabric_lowskew_o6, fabric_cfg_fabric_user_flag_o, fabric_status_cold_start_o, fabric_flag_error_o, fabric_otp_user_clock_frequency_range_i, fabric_parusr_enable_i, fabric_mrepair_mode_i, fabric_mrepair_fuse_add_i, fabric_mrepair_fuse_din_i, fabric_mrepair_fuse_tst_scanin_i, fabric_mrepair_fuse_prgwidth_i, fabric_mrepair_fuse_dout_o, fabric_mrepair_fuse_startword_o, fabric_mrepair_fuse_wlromout_o
-, fabric_mrepair_fuse_bist1fail_o, fabric_mrepair_fuse_bist2fail_o, fabric_mrepair_fuse_tstscanout_o, fabric_mrepair_fuse_flagstate_o, fabric_otp_user_add_i, fabric_otp_user_din_i, fabric_otp_user_prgwidth_i, fabric_otp_user_tst_scanin_i, fabric_otp_user_bist1fail_o, fabric_otp_user_bist2fail_o, fabric_otp_user_dout_o, fabric_otp_user_flagstate_o, fabric_otp_user_startword_o, fabric_otp_user_tst_scanout_o, fabric_otp_user_wlromout_o, fabric_io_in_i, fabric_io_oe_i, fabric_io_out_o, fabric_user_data_i, fabric_user_data_o, fabric_parusr_type_i
-, fabric_parusr_data_i, fabric_parusr_data_o, fabric_direct_data_i, fabric_direct_data_o, fabric_otp_apb_addr_i, fabric_otp_apb_wdata_i, fabric_otp_apb_rdata_o, fabric_otp_security_bist_fail1_o, fabric_otp_security_bist_fail2_o, fabric_otp_security_scanin_i, fabric_otp_security_scanout_o, fabric_flag_ready_TMR_o, fabric_debug_lifecycle_o, fabric_debug_fsm_state_o, fabric_debug_direct_permission_write_o, fabric_debug_direct_permission_read_o, fabric_debug_frame_permission_frame_o, fabric_debug_otpmgmt_state_o, fabric_debug_otpapb_state_o, fabric_debug_otpboot_state_o, fabric_debug_cpt_retry_o
-, fabric_debug_bsec_core_status_o, fabric_debug_otpboot_curr_addr_o, fabric_sif_reg_en_i, fabric_data_from_bist_i, fabric_shift_en_i, fabric_ahb_direct_data_i, fabric_pd_active_i, fabric_sif_load_en_i, fabric_system_data_to_mem_bist_i, fabric_sif_update_en_i, fabric_sif_update_en_to_bist_o, fabric_data_to_bist_o, fabric_ahb_direct_data_o, fabric_global_chip_status_o, fabric_fuse_status_o, fabric_shift_en_to_bist_o, fabric_sif_reg_en_to_bist_o, fabric_system_data_from_mem_bist_o, fabric_chip_status_o, fabric_pd_ready_o, fabric_sif_load_en_to_bist_o
-);
-    input [31:0] fabric_ahb_direct_data_i;
-    output [31:0] fabric_ahb_direct_data_o;
-    output fabric_cfg_fabric_user_enable_o;
-    output fabric_cfg_fabric_user_flag_o;
-    output [71:0] fabric_chip_status_o;
-    input fabric_clk_otp_mux_i;
-    input [23:0] fabric_data_from_bist_i;
-    input fabric_data_from_system_i;
-    input fabric_data_shift_en_i;
-    output [23:0] fabric_data_to_bist_o;
-    output fabric_data_to_system_o;
-    output fabric_debug_access_reg_data_ready_o;
-    output [31:0] fabric_debug_bsec_core_status_o;
-    output [3:0] fabric_debug_cpt_retry_o;
-    output [3:0] fabric_debug_direct_permission_read_o;
-    output [3:0] fabric_debug_direct_permission_write_o;
-    output fabric_debug_error_o;
-    output [3:0] fabric_debug_frame_permission_frame_o;
-    output fabric_debug_frame_use_encryption_o;
-    output [2:0] fabric_debug_fsm_state_o;
-    output fabric_debug_key_correct_o;
-    output [3:0] fabric_debug_lifecycle_o;
-    output fabric_debug_lock_reg_o;
-    output fabric_debug_otp_manager_read_done_o;
-    output fabric_debug_otp_manager_read_otp_o;
-    output fabric_debug_otp_reload_err_o;
-    output [2:0] fabric_debug_otpapb_state_o;
-    output [7:0] fabric_debug_otpboot_curr_addr_o;
-    output [2:0] fabric_debug_otpboot_state_o;
-    output [2:0] fabric_debug_otpmgmt_state_o;
-    output fabric_debug_rst_soft_o;
-    output fabric_debug_security_boot_done_o;
-    output fabric_debug_security_error_read_o;
-    output fabric_decoder_init_ready_o;
-    input [31:0] fabric_direct_data_i;
-    output [31:0] fabric_direct_data_o;
-    input fabric_end_encoding_i;
-    output fabric_flag_error_o;
-    output [2:0] fabric_flag_ready_TMR_o;
-    output fabric_flag_trigger_o;
-    output [2:0] fabric_fuse_status_o;
-    output [2:0] fabric_global_chip_status_o;
-    input [24:0] fabric_io_in_i;
-    input [24:0] fabric_io_oe_i;
-    output [24:0] fabric_io_out_o;
-    output fabric_jtag_tdi_o;
-    input fabric_jtag_tdo_usr1_i;
-    input fabric_jtag_tdo_usr2_i;
-    output fabric_jtag_tms_o;
-    output fabric_jtag_trst_n_o;
-    output fabric_jtag_usr1_o;
-    output fabric_jtag_usr2_o;
-    input fabric_lowskew_i20;
-    input fabric_lowskew_i21;
-    input fabric_lowskew_i22;
-    input fabric_lowskew_i23;
-    output fabric_lowskew_o3;
-    output fabric_lowskew_o4;
-    output fabric_lowskew_o5;
-    output fabric_lowskew_o6;
-    input fabric_mrepair_cke_force_i;
-    input fabric_mrepair_cke_i;
-    output fabric_mrepair_fuse_ack_o;
-    input [6:0] fabric_mrepair_fuse_add_i;
-    output fabric_mrepair_fuse_bbad_o;
-    output fabric_mrepair_fuse_bend1_o;
-    output fabric_mrepair_fuse_bend2_o;
-    output [7:0] fabric_mrepair_fuse_bist1fail_o;
-    output [6:0] fabric_mrepair_fuse_bist2fail_o;
-    input fabric_mrepair_fuse_bistmode_i;
-    output fabric_mrepair_fuse_calibrated_o;
-    output fabric_mrepair_fuse_ded_o;
-    input [38:0] fabric_mrepair_fuse_din_i;
-    input fabric_mrepair_fuse_disturbchecked_i;
-    output fabric_mrepair_fuse_disturbed_o;
-    output [40:0] fabric_mrepair_fuse_dout_o;
-    input fabric_mrepair_fuse_eccbypass_i;
-    output [3:0] fabric_mrepair_fuse_flagstate_o;
-    output fabric_mrepair_fuse_locked_o;
-    input fabric_mrepair_fuse_pdn_i;
-    output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o;
-    input [2:0] fabric_mrepair_fuse_prgwidth_i;
-    input fabric_mrepair_fuse_prog_i;
-    output fabric_mrepair_fuse_progfail_o;
-    output fabric_mrepair_fuse_pwok_o;
-    input fabric_mrepair_fuse_rbact1_i;
-    input fabric_mrepair_fuse_rbact2_i;
-    input fabric_mrepair_fuse_read_i;
-    output fabric_mrepair_fuse_ready_o;
-    input fabric_mrepair_fuse_redbypass_i;
-    output fabric_mrepair_fuse_sec_o;
-    output [15:0] fabric_mrepair_fuse_startword_o;
-    input fabric_mrepair_fuse_suppadd_i;
-    input fabric_mrepair_fuse_tm_i;
-    input [4:0] fabric_mrepair_fuse_tst_scanin_i;
-    input fabric_mrepair_fuse_tstscanenable_i;
-    output [4:0] fabric_mrepair_fuse_tstscanout_o;
-    output [9:0] fabric_mrepair_fuse_wlromout_o;
-    input fabric_mrepair_fuse_wordlock_i;
-    input [3:0] fabric_mrepair_mode_i;
-    input fabric_mrepair_por_i;
-    input [31:0] fabric_otp_apb_addr_i;
-    input fabric_otp_apb_enable_i;
-    output [31:0] fabric_otp_apb_rdata_o;
-    output fabric_otp_apb_ready_o;
-    input fabric_otp_apb_sel_i;
-    input [31:0] fabric_otp_apb_wdata_i;
-    input fabric_otp_apb_write_i;
-    input fabric_otp_cfg_clk_fab_en_i;
-    input fabric_otp_cfg_clk_otpm_disable_i;
-    input fabric_otp_cfg_fabric_apb_en_i;
-    input fabric_otp_cfg_loader_read_en_i;
-    input fabric_otp_cfg_loader_write_en_i;
-    input fabric_otp_rst_i;
-    output fabric_otp_security_ack_o;
-    output fabric_otp_security_bist_bad_o;
-    output fabric_otp_security_bist_end1_o;
-    output fabric_otp_security_bist_end2_o;
-    output [7:0] fabric_otp_security_bist_fail1_o;
-    output [6:0] fabric_otp_security_bist_fail2_o;
-    input fabric_otp_security_bistmode_i;
-    input fabric_otp_security_force_pdn1_i;
-    input fabric_otp_security_rbact1_i;
-    input fabric_otp_security_rbact2_i;
-    input fabric_otp_security_scanenable_i;
-    input [4:0] fabric_otp_security_scanin_i;
-    output [4:0] fabric_otp_security_scanout_o;
-    input fabric_otp_security_testmode_i;
-    output fabric_otp_user_ack_o;
-    input [6:0] fabric_otp_user_add_i;
-    output fabric_otp_user_bbad_o;
-    output fabric_otp_user_bend1_o;
-    output fabric_otp_user_bend2_o;
-    output [7:0] fabric_otp_user_bist1fail_o;
-    output [6:0] fabric_otp_user_bist2fail_o;
-    input fabric_otp_user_bistmode_i;
-    output fabric_otp_user_calibrated_o;
-    input fabric_otp_user_clock_frequency_range_i;
-    output fabric_otp_user_ded_o;
-    input [38:0] fabric_otp_user_din_i;
-    input fabric_otp_user_disturbcheck_i;
-    output fabric_otp_user_disturbed_o;
-    output [40:0] fabric_otp_user_dout_o;
-    input fabric_otp_user_eccbypass_i;
-    output [3:0] fabric_otp_user_flagstate_o;
-    output fabric_otp_user_locked_o;
-    input fabric_otp_user_pdn_i;
-    input [2:0] fabric_otp_user_prgwidth_i;
-    input fabric_otp_user_prog_i;
-    output fabric_otp_user_progfail_o;
-    output fabric_otp_user_pwok_o;
-    input fabric_otp_user_rbact1_i;
-    input fabric_otp_user_rbact2_i;
-    input fabric_otp_user_read_i;
-    input fabric_otp_user_redbypass_i;
-    output fabric_otp_user_sec_o;
-    output [15:0] fabric_otp_user_startword_o;
-    input fabric_otp_user_suppadd_i;
-    input fabric_otp_user_tm_i;
-    input fabric_otp_user_tst_scanenable_i;
-    input [4:0] fabric_otp_user_tst_scanin_i;
-    output [4:0] fabric_otp_user_tst_scanout_o;
-    output [9:0] fabric_otp_user_wlromout_o;
-    input fabric_otp_user_wordlock_i;
-    input fabric_parusr_cs_i;
-    input [15:0] fabric_parusr_data_i;
-    output [15:0] fabric_parusr_data_o;
-    output fabric_parusr_data_val_o;
-    input fabric_parusr_enable_i;
-    input [1:0] fabric_parusr_type_i;
-    input [23:0] fabric_pd_active_i;
-    output [23:0] fabric_pd_ready_o;
-    input [23:0] fabric_shift_en_i;
-    output [23:0] fabric_shift_en_to_bist_o;
-    input [23:0] fabric_sif_load_en_i;
-    output [23:0] fabric_sif_load_en_to_bist_o;
-    input [119:0] fabric_sif_reg_en_i;
-    output [119:0] fabric_sif_reg_en_to_bist_o;
-    input [23:0] fabric_sif_update_en_i;
-    output [23:0] fabric_sif_update_en_to_bist_o;
-    output fabric_status_cold_start_o;
-    output [23:0] fabric_system_data_from_mem_bist_o;
-    input [23:0] fabric_system_data_to_mem_bist_i;
-    output fabric_system_dataready_o;
-    input fabric_tst_atpg_mrepair_i;
-    input [31:0] fabric_user_data_i;
-    output [31:0] fabric_user_data_o;
-    output fabric_user_read_cycle_o;
-    output fabric_user_write_cycle_o;
-    parameter ahb_config = 0;
-    parameter bsm_config = 0;
-endmodule
-
-(* blackbox *)
-module NX_SOC_INTERFACE(fabric_lowskew_o1, fabric_lowskew_o2, fabric_lowskew_i3, fabric_lowskew_i4, fabric_lowskew_i5, fabric_lowskew_i6, fabric_lowskew_i7, fabric_lowskew_i8, fabric_lowskew_i9, fabric_lowskew_i10, fabric_lowskew_i11, fabric_lowskew_i12, fabric_lowskew_i13, fabric_lowskew_i14, fabric_lowskew_i15, fabric_lowskew_i16, fabric_lowskew_i17, fabric_lowskew_i18, fabric_lowskew_i19, fabric_fpga_nic_rstn_i1, fabric_fpga_nic_rstn_i2
-, fabric_fpga_nic_rstn_i3, fabric_fpga_nic_rstn_i4, fabric_fpga_nic_rstn_i5, fabric_fpga_nic_rstn_i6, fabric_fpga_nic_rstn_i7, fabric_fpga_nic_rstn_i8, fabric_fpga_nic_rstn_i9, fabric_fpga_nic_rstn_i10, fabric_fpga_pmrstn_i, fabric_fpga_sysrstn_i, fabric_fpga_trigger_in_o1, fabric_fpga_trigger_in_o2, fabric_fpga_trigger_in_o3, fabric_fpga_trigger_in_o4, fabric_fpga_trigger_in_o5, fabric_fpga_trigger_in_o6, fabric_fpga_trigger_in_o7, fabric_fpga_trigger_in_o8, fabric_fpga_trigger_out_i1, fabric_fpga_trigger_out_i2, fabric_fpga_trigger_out_i3
-, fabric_fpga_trigger_out_i4, fabric_fpga_trigger_out_i5, fabric_fpga_trigger_out_i6, fabric_fpga_trigger_out_i7, fabric_fpga_trigger_out_i8, fabric_fpga_interrupt_in_i1, fabric_fpga_interrupt_in_i2, fabric_fpga_interrupt_in_i3, fabric_fpga_interrupt_in_i4, fabric_fpga_interrupt_in_i5, fabric_fpga_interrupt_in_i6, fabric_fpga_interrupt_in_i7, fabric_fpga_interrupt_in_i8, fabric_fpga_interrupt_in_i9, fabric_fpga_interrupt_in_i10, fabric_fpga_interrupt_in_i11, fabric_fpga_interrupt_in_i12, fabric_fpga_interrupt_in_i13, fabric_fpga_interrupt_in_i14, fabric_fpga_interrupt_in_i15, fabric_fpga_interrupt_in_i16
-, fabric_fpga_interrupt_in_i17, fabric_fpga_interrupt_in_i18, fabric_fpga_interrupt_in_i19, fabric_fpga_interrupt_in_i20, fabric_fpga_interrupt_in_i21, fabric_fpga_interrupt_in_i22, fabric_fpga_interrupt_in_i23, fabric_fpga_interrupt_in_i24, fabric_fpga_interrupt_in_i25, fabric_fpga_interrupt_in_i26, fabric_fpga_interrupt_in_i27, fabric_fpga_interrupt_in_i28, fabric_fpga_interrupt_in_i29, fabric_fpga_interrupt_in_i30, fabric_fpga_interrupt_in_i31, fabric_fpga_interrupt_in_i32, fabric_fpga_interrupt_in_i33, fabric_fpga_interrupt_in_i34, fabric_fpga_interrupt_in_i35, fabric_fpga_interrupt_in_i36, fabric_fpga_interrupt_in_i37
-, fabric_fpga_interrupt_in_i38, fabric_fpga_interrupt_in_i39, fabric_fpga_interrupt_in_i40, fabric_fpga_interrupt_in_i41, fabric_fpga_interrupt_in_i42, fabric_fpga_interrupt_in_i43, fabric_fpga_interrupt_in_i44, fabric_fpga_interrupt_in_i45, fabric_fpga_interrupt_in_i46, fabric_fpga_interrupt_in_i47, fabric_fpga_interrupt_in_i48, fabric_fpga_interrupt_in_i49, fabric_fpga_interrupt_in_i50, fabric_fpga_interrupt_in_i51, fabric_fpga_interrupt_in_i52, fabric_fpga_interrupt_in_i53, fabric_fpga_interrupt_in_i54, fabric_fpga_interrupt_in_i55, fabric_fpga_interrupt_in_i56, fabric_fpga_interrupt_in_i57, fabric_fpga_interrupt_in_i58
-, fabric_fpga_interrupt_in_i59, fabric_fpga_interrupt_in_i60, fabric_fpga_interrupt_in_i61, fabric_fpga_interrupt_in_i62, fabric_fpga_interrupt_in_i63, fabric_fpga_interrupt_in_i64, fabric_fpga_interrupt_in_i65, fabric_fpga_interrupt_in_i66, fabric_fpga_interrupt_in_i67, fabric_fpga_interrupt_in_i68, fabric_fpga_interrupt_in_i69, fabric_fpga_interrupt_in_i70, fabric_fpga_interrupt_in_i71, fabric_fpga_interrupt_in_i72, fabric_fpga_interrupt_in_i73, fabric_fpga_interrupt_in_i74, fabric_fpga_interrupt_in_i75, fabric_fpga_interrupt_in_i76, fabric_fpga_interrupt_in_i77, fabric_fpga_interrupt_in_i78, fabric_fpga_interrupt_in_i79
-, fabric_fpga_interrupt_in_i80, fabric_fpga_interrupt_in_i81, fabric_fpga_interrupt_in_i82, fabric_fpga_interrupt_in_i83, fabric_fpga_interrupt_in_i84, fabric_fpga_interrupt_in_i85, fabric_fpga_interrupt_in_i86, fabric_fpga_interrupt_in_i87, fabric_fpga_interrupt_in_i88, fabric_fpga_interrupt_in_i89, fabric_fpga_interrupt_in_i90, fabric_fpga_interrupt_in_i91, fabric_fpga_interrupt_in_i92, fabric_fpga_interrupt_in_i93, fabric_fpga_interrupt_in_i94, fabric_fpga_interrupt_in_i95, fabric_fpga_interrupt_in_i96, fabric_fpga_interrupt_in_i97, fabric_fpga_interrupt_in_i98, fabric_fpga_interrupt_in_i99, fabric_fpga_interrupt_in_i100
-, fabric_fpga_interrupt_in_i101, fabric_fpga_interrupt_in_i102, fabric_fpga_interrupt_in_i103, fabric_fpga_interrupt_in_i104, fabric_fpga_interrupt_in_i105, fabric_fpga_interrupt_in_i106, fabric_fpga_interrupt_in_i107, fabric_fpga_interrupt_in_i108, fabric_fpga_interrupt_in_i109, fabric_fpga_interrupt_in_i110, fabric_fpga_interrupt_in_i111, fabric_fpga_interrupt_in_i112, fabric_fpga_interrupt_in_i113, fabric_fpga_interrupt_in_i114, fabric_fpga_interrupt_in_i115, fabric_fpga_interrupt_in_i116, fabric_fpga_interrupt_in_i117, fabric_fpga_interrupt_in_i118, fabric_fpga_interrupt_in_i119, fabric_fpga_interrupt_in_i120, fabric_sysc_hold_on_debug_i
-, fabric_fpga_events60_i1, fabric_fpga_events60_i2, fabric_fpga_events60_i3, fabric_fpga_events60_i4, fabric_fpga_events60_i5, fabric_fpga_events60_i6, fabric_fpga_events60_i7, fabric_fpga_events60_i8, fabric_fpga_events60_i9, fabric_fpga_events60_i10, fabric_fpga_events60_i11, fabric_fpga_events60_i12, fabric_fpga_events60_i13, fabric_fpga_events60_i14, fabric_fpga_events60_i15, fabric_fpga_events60_i16, fabric_fpga_events60_i17, fabric_fpga_events60_i18, fabric_fpga_events60_i19, fabric_fpga_events60_i20, fabric_fpga_events60_i21
-, fabric_fpga_events60_i22, fabric_fpga_events60_i23, fabric_fpga_events60_i24, fabric_fpga_events60_i25, fabric_fpga_events60_i26, fabric_fpga_events60_i27, fabric_fpga_events60_i28, fabric_fpga_events60_i29, fabric_fpga_events60_i30, fabric_fpga_events60_i31, fabric_fpga_events60_i32, fabric_fpga_events60_i33, fabric_fpga_events60_i34, fabric_fpga_events60_i35, fabric_fpga_events60_i36, fabric_fpga_events60_i37, fabric_fpga_events60_i38, fabric_fpga_events60_i39, fabric_fpga_events60_i40, fabric_fpga_events60_i41, fabric_fpga_events60_i42
-, fabric_fpga_events60_i43, fabric_fpga_events60_i44, fabric_fpga_events60_i45, fabric_fpga_events60_i46, fabric_fpga_events60_i47, fabric_fpga_events60_i48, fabric_fpga_events60_i49, fabric_fpga_events60_i50, fabric_fpga_events60_i51, fabric_fpga_events60_i52, fabric_fpga_events60_i53, fabric_fpga_events60_i54, fabric_fpga_events60_i55, fabric_fpga_events60_i56, fabric_fpga_events60_i57, fabric_fpga_events60_i58, fabric_fpga_events60_i59, fabric_fpga_events60_i60, fabric_fpga_araddr_axi_s1_o1, fabric_fpga_araddr_axi_s1_o2, fabric_fpga_araddr_axi_s1_o3
-, fabric_fpga_araddr_axi_s1_o4, fabric_fpga_araddr_axi_s1_o5, fabric_fpga_araddr_axi_s1_o6, fabric_fpga_araddr_axi_s1_o7, fabric_fpga_araddr_axi_s1_o8, fabric_fpga_araddr_axi_s1_o9, fabric_fpga_araddr_axi_s1_o10, fabric_fpga_araddr_axi_s1_o11, fabric_fpga_araddr_axi_s1_o12, fabric_fpga_araddr_axi_s1_o13, fabric_fpga_araddr_axi_s1_o14, fabric_fpga_araddr_axi_s1_o15, fabric_fpga_araddr_axi_s1_o16, fabric_fpga_araddr_axi_s1_o17, fabric_fpga_araddr_axi_s1_o18, fabric_fpga_araddr_axi_s1_o19, fabric_fpga_araddr_axi_s1_o20, fabric_fpga_araddr_axi_s1_o21, fabric_fpga_araddr_axi_s1_o22, fabric_fpga_araddr_axi_s1_o23, fabric_fpga_araddr_axi_s1_o24
-, fabric_fpga_araddr_axi_s1_o25, fabric_fpga_araddr_axi_s1_o26, fabric_fpga_araddr_axi_s1_o27, fabric_fpga_araddr_axi_s1_o28, fabric_fpga_araddr_axi_s1_o29, fabric_fpga_araddr_axi_s1_o30, fabric_fpga_araddr_axi_s1_o31, fabric_fpga_araddr_axi_s1_o32, fabric_fpga_araddr_axi_s1_o33, fabric_fpga_araddr_axi_s1_o34, fabric_fpga_araddr_axi_s1_o35, fabric_fpga_araddr_axi_s1_o36, fabric_fpga_araddr_axi_s1_o37, fabric_fpga_araddr_axi_s1_o38, fabric_fpga_araddr_axi_s1_o39, fabric_fpga_araddr_axi_s1_o40, fabric_fpga_arburst_axi_s1_o1, fabric_fpga_arburst_axi_s1_o2, fabric_fpga_arcache_axi_s1_o1, fabric_fpga_arcache_axi_s1_o2, fabric_fpga_arcache_axi_s1_o3
-, fabric_fpga_arcache_axi_s1_o4, fabric_fpga_arid_axi_s1_o1, fabric_fpga_arid_axi_s1_o2, fabric_fpga_arid_axi_s1_o3, fabric_fpga_arid_axi_s1_o4, fabric_fpga_arid_axi_s1_o5, fabric_fpga_arid_axi_s1_o6, fabric_fpga_arid_axi_s1_o7, fabric_fpga_arid_axi_s1_o8, fabric_fpga_arid_axi_s1_o9, fabric_fpga_arid_axi_s1_o10, fabric_fpga_arid_axi_s1_o11, fabric_fpga_arid_axi_s1_o12, fabric_fpga_arlen_axi_s1_o1, fabric_fpga_arlen_axi_s1_o2, fabric_fpga_arlen_axi_s1_o3, fabric_fpga_arlen_axi_s1_o4, fabric_fpga_arlen_axi_s1_o5, fabric_fpga_arlen_axi_s1_o6, fabric_fpga_arlen_axi_s1_o7, fabric_fpga_arlen_axi_s1_o8
-, fabric_fpga_arlock_axi_s1_o, fabric_fpga_arprot_axi_s1_o1, fabric_fpga_arprot_axi_s1_o2, fabric_fpga_arprot_axi_s1_o3, fabric_fpga_arqos_axi_s1_o1, fabric_fpga_arqos_axi_s1_o2, fabric_fpga_arqos_axi_s1_o3, fabric_fpga_arqos_axi_s1_o4, fabric_fpga_arregion_axi_s1_o1, fabric_fpga_arregion_axi_s1_o2, fabric_fpga_arregion_axi_s1_o3, fabric_fpga_arregion_axi_s1_o4, fabric_fpga_arsize_axi_s1_o1, fabric_fpga_arsize_axi_s1_o2, fabric_fpga_arsize_axi_s1_o3, fabric_fpga_arvalid_axi_s1_o, fabric_fpga_awaddr_axi_s1_o1, fabric_fpga_awaddr_axi_s1_o2, fabric_fpga_awaddr_axi_s1_o3, fabric_fpga_awaddr_axi_s1_o4, fabric_fpga_awaddr_axi_s1_o5
-, fabric_fpga_awaddr_axi_s1_o6, fabric_fpga_awaddr_axi_s1_o7, fabric_fpga_awaddr_axi_s1_o8, fabric_fpga_awaddr_axi_s1_o9, fabric_fpga_awaddr_axi_s1_o10, fabric_fpga_awaddr_axi_s1_o11, fabric_fpga_awaddr_axi_s1_o12, fabric_fpga_awaddr_axi_s1_o13, fabric_fpga_awaddr_axi_s1_o14, fabric_fpga_awaddr_axi_s1_o15, fabric_fpga_awaddr_axi_s1_o16, fabric_fpga_awaddr_axi_s1_o17, fabric_fpga_awaddr_axi_s1_o18, fabric_fpga_awaddr_axi_s1_o19, fabric_fpga_awaddr_axi_s1_o20, fabric_fpga_awaddr_axi_s1_o21, fabric_fpga_awaddr_axi_s1_o22, fabric_fpga_awaddr_axi_s1_o23, fabric_fpga_awaddr_axi_s1_o24, fabric_fpga_awaddr_axi_s1_o25, fabric_fpga_awaddr_axi_s1_o26
-, fabric_fpga_awaddr_axi_s1_o27, fabric_fpga_awaddr_axi_s1_o28, fabric_fpga_awaddr_axi_s1_o29, fabric_fpga_awaddr_axi_s1_o30, fabric_fpga_awaddr_axi_s1_o31, fabric_fpga_awaddr_axi_s1_o32, fabric_fpga_awaddr_axi_s1_o33, fabric_fpga_awaddr_axi_s1_o34, fabric_fpga_awaddr_axi_s1_o35, fabric_fpga_awaddr_axi_s1_o36, fabric_fpga_awaddr_axi_s1_o37, fabric_fpga_awaddr_axi_s1_o38, fabric_fpga_awaddr_axi_s1_o39, fabric_fpga_awaddr_axi_s1_o40, fabric_fpga_awburst_axi_s1_o1, fabric_fpga_awburst_axi_s1_o2, fabric_fpga_awcache_axi_s1_o1, fabric_fpga_awcache_axi_s1_o2, fabric_fpga_awcache_axi_s1_o3, fabric_fpga_awcache_axi_s1_o4, fabric_fpga_awid_axi_s1_o1
-, fabric_fpga_awid_axi_s1_o2, fabric_fpga_awid_axi_s1_o3, fabric_fpga_awid_axi_s1_o4, fabric_fpga_awid_axi_s1_o5, fabric_fpga_awid_axi_s1_o6, fabric_fpga_awid_axi_s1_o7, fabric_fpga_awid_axi_s1_o8, fabric_fpga_awid_axi_s1_o9, fabric_fpga_awid_axi_s1_o10, fabric_fpga_awid_axi_s1_o11, fabric_fpga_awid_axi_s1_o12, fabric_fpga_awlen_axi_s1_o1, fabric_fpga_awlen_axi_s1_o2, fabric_fpga_awlen_axi_s1_o3, fabric_fpga_awlen_axi_s1_o4, fabric_fpga_awlen_axi_s1_o5, fabric_fpga_awlen_axi_s1_o6, fabric_fpga_awlen_axi_s1_o7, fabric_fpga_awlen_axi_s1_o8, fabric_fpga_awlock_axi_s1_o, fabric_fpga_awprot_axi_s1_o1
-, fabric_fpga_awprot_axi_s1_o2, fabric_fpga_awprot_axi_s1_o3, fabric_fpga_awqos_axi_s1_o1, fabric_fpga_awqos_axi_s1_o2, fabric_fpga_awqos_axi_s1_o3, fabric_fpga_awqos_axi_s1_o4, fabric_fpga_awregion_axi_s1_o1, fabric_fpga_awregion_axi_s1_o2, fabric_fpga_awregion_axi_s1_o3, fabric_fpga_awregion_axi_s1_o4, fabric_fpga_awsize_axi_s1_o1, fabric_fpga_awsize_axi_s1_o2, fabric_fpga_awsize_axi_s1_o3, fabric_fpga_bready_axi_s1_o, fabric_fpga_rready_axi_s1_o, fabric_fpga_wdata_axi_s1_o1, fabric_fpga_wdata_axi_s1_o2, fabric_fpga_wdata_axi_s1_o3, fabric_fpga_wdata_axi_s1_o4, fabric_fpga_wdata_axi_s1_o5, fabric_fpga_wdata_axi_s1_o6
-, fabric_fpga_wdata_axi_s1_o7, fabric_fpga_wdata_axi_s1_o8, fabric_fpga_wdata_axi_s1_o9, fabric_fpga_wdata_axi_s1_o10, fabric_fpga_wdata_axi_s1_o11, fabric_fpga_wdata_axi_s1_o12, fabric_fpga_wdata_axi_s1_o13, fabric_fpga_wdata_axi_s1_o14, fabric_fpga_wdata_axi_s1_o15, fabric_fpga_wdata_axi_s1_o16, fabric_fpga_wdata_axi_s1_o17, fabric_fpga_wdata_axi_s1_o18, fabric_fpga_wdata_axi_s1_o19, fabric_fpga_wdata_axi_s1_o20, fabric_fpga_wdata_axi_s1_o21, fabric_fpga_wdata_axi_s1_o22, fabric_fpga_wdata_axi_s1_o23, fabric_fpga_wdata_axi_s1_o24, fabric_fpga_wdata_axi_s1_o25, fabric_fpga_wdata_axi_s1_o26, fabric_fpga_wdata_axi_s1_o27
-, fabric_fpga_wdata_axi_s1_o28, fabric_fpga_wdata_axi_s1_o29, fabric_fpga_wdata_axi_s1_o30, fabric_fpga_wdata_axi_s1_o31, fabric_fpga_wdata_axi_s1_o32, fabric_fpga_wdata_axi_s1_o33, fabric_fpga_wdata_axi_s1_o34, fabric_fpga_wdata_axi_s1_o35, fabric_fpga_wdata_axi_s1_o36, fabric_fpga_wdata_axi_s1_o37, fabric_fpga_wdata_axi_s1_o38, fabric_fpga_wdata_axi_s1_o39, fabric_fpga_wdata_axi_s1_o40, fabric_fpga_wdata_axi_s1_o41, fabric_fpga_wdata_axi_s1_o42, fabric_fpga_wdata_axi_s1_o43, fabric_fpga_wdata_axi_s1_o44, fabric_fpga_wdata_axi_s1_o45, fabric_fpga_wdata_axi_s1_o46, fabric_fpga_wdata_axi_s1_o47, fabric_fpga_wdata_axi_s1_o48
-, fabric_fpga_wdata_axi_s1_o49, fabric_fpga_wdata_axi_s1_o50, fabric_fpga_wdata_axi_s1_o51, fabric_fpga_wdata_axi_s1_o52, fabric_fpga_wdata_axi_s1_o53, fabric_fpga_wdata_axi_s1_o54, fabric_fpga_wdata_axi_s1_o55, fabric_fpga_wdata_axi_s1_o56, fabric_fpga_wdata_axi_s1_o57, fabric_fpga_wdata_axi_s1_o58, fabric_fpga_wdata_axi_s1_o59, fabric_fpga_wdata_axi_s1_o60, fabric_fpga_wdata_axi_s1_o61, fabric_fpga_wdata_axi_s1_o62, fabric_fpga_wdata_axi_s1_o63, fabric_fpga_wdata_axi_s1_o64, fabric_fpga_wdata_axi_s1_o65, fabric_fpga_wdata_axi_s1_o66, fabric_fpga_wdata_axi_s1_o67, fabric_fpga_wdata_axi_s1_o68, fabric_fpga_wdata_axi_s1_o69
-, fabric_fpga_wdata_axi_s1_o70, fabric_fpga_wdata_axi_s1_o71, fabric_fpga_wdata_axi_s1_o72, fabric_fpga_wdata_axi_s1_o73, fabric_fpga_wdata_axi_s1_o74, fabric_fpga_wdata_axi_s1_o75, fabric_fpga_wdata_axi_s1_o76, fabric_fpga_wdata_axi_s1_o77, fabric_fpga_wdata_axi_s1_o78, fabric_fpga_wdata_axi_s1_o79, fabric_fpga_wdata_axi_s1_o80, fabric_fpga_wdata_axi_s1_o81, fabric_fpga_wdata_axi_s1_o82, fabric_fpga_wdata_axi_s1_o83, fabric_fpga_wdata_axi_s1_o84, fabric_fpga_wdata_axi_s1_o85, fabric_fpga_wdata_axi_s1_o86, fabric_fpga_wdata_axi_s1_o87, fabric_fpga_wdata_axi_s1_o88, fabric_fpga_wdata_axi_s1_o89, fabric_fpga_wdata_axi_s1_o90
-, fabric_fpga_wdata_axi_s1_o91, fabric_fpga_wdata_axi_s1_o92, fabric_fpga_wdata_axi_s1_o93, fabric_fpga_wdata_axi_s1_o94, fabric_fpga_wdata_axi_s1_o95, fabric_fpga_wdata_axi_s1_o96, fabric_fpga_wdata_axi_s1_o97, fabric_fpga_wdata_axi_s1_o98, fabric_fpga_wdata_axi_s1_o99, fabric_fpga_wdata_axi_s1_o100, fabric_fpga_wdata_axi_s1_o101, fabric_fpga_wdata_axi_s1_o102, fabric_fpga_wdata_axi_s1_o103, fabric_fpga_wdata_axi_s1_o104, fabric_fpga_wdata_axi_s1_o105, fabric_fpga_wdata_axi_s1_o106, fabric_fpga_wdata_axi_s1_o107, fabric_fpga_wdata_axi_s1_o108, fabric_fpga_wdata_axi_s1_o109, fabric_fpga_wdata_axi_s1_o110, fabric_fpga_wdata_axi_s1_o111
-, fabric_fpga_wdata_axi_s1_o112, fabric_fpga_wdata_axi_s1_o113, fabric_fpga_wdata_axi_s1_o114, fabric_fpga_wdata_axi_s1_o115, fabric_fpga_wdata_axi_s1_o116, fabric_fpga_wdata_axi_s1_o117, fabric_fpga_wdata_axi_s1_o118, fabric_fpga_wdata_axi_s1_o119, fabric_fpga_wdata_axi_s1_o120, fabric_fpga_wdata_axi_s1_o121, fabric_fpga_wdata_axi_s1_o122, fabric_fpga_wdata_axi_s1_o123, fabric_fpga_wdata_axi_s1_o124, fabric_fpga_wdata_axi_s1_o125, fabric_fpga_wdata_axi_s1_o126, fabric_fpga_wdata_axi_s1_o127, fabric_fpga_wdata_axi_s1_o128, fabric_fpga_wlast_axi_s1_o, fabric_fpga_wstrb_axi_s1_o1, fabric_fpga_wstrb_axi_s1_o2, fabric_fpga_wstrb_axi_s1_o3
-, fabric_fpga_wstrb_axi_s1_o4, fabric_fpga_wstrb_axi_s1_o5, fabric_fpga_wstrb_axi_s1_o6, fabric_fpga_wstrb_axi_s1_o7, fabric_fpga_wstrb_axi_s1_o8, fabric_fpga_wstrb_axi_s1_o9, fabric_fpga_wstrb_axi_s1_o10, fabric_fpga_wstrb_axi_s1_o11, fabric_fpga_wstrb_axi_s1_o12, fabric_fpga_wstrb_axi_s1_o13, fabric_fpga_wstrb_axi_s1_o14, fabric_fpga_wstrb_axi_s1_o15, fabric_fpga_wstrb_axi_s1_o16, fabric_fpga_wvalid_axi_s1_o, fabric_fpga_awvalid_axi_s1_o, fabric_fpga_arready_axi_s1_i, fabric_fpga_awready_axi_s1_i, fabric_fpga_bid_axi_s1_i1, fabric_fpga_bid_axi_s1_i2, fabric_fpga_bid_axi_s1_i3, fabric_fpga_bid_axi_s1_i4
-, fabric_fpga_bid_axi_s1_i5, fabric_fpga_bid_axi_s1_i6, fabric_fpga_bid_axi_s1_i7, fabric_fpga_bid_axi_s1_i8, fabric_fpga_bid_axi_s1_i9, fabric_fpga_bid_axi_s1_i10, fabric_fpga_bid_axi_s1_i11, fabric_fpga_bid_axi_s1_i12, fabric_fpga_bresp_axi_s1_i1, fabric_fpga_bresp_axi_s1_i2, fabric_fpga_bvalid_axi_s1_i, fabric_fpga_rdata_axi_s1_i1, fabric_fpga_rdata_axi_s1_i2, fabric_fpga_rdata_axi_s1_i3, fabric_fpga_rdata_axi_s1_i4, fabric_fpga_rdata_axi_s1_i5, fabric_fpga_rdata_axi_s1_i6, fabric_fpga_rdata_axi_s1_i7, fabric_fpga_rdata_axi_s1_i8, fabric_fpga_rdata_axi_s1_i9, fabric_fpga_rdata_axi_s1_i10
-, fabric_fpga_rdata_axi_s1_i11, fabric_fpga_rdata_axi_s1_i12, fabric_fpga_rdata_axi_s1_i13, fabric_fpga_rdata_axi_s1_i14, fabric_fpga_rdata_axi_s1_i15, fabric_fpga_rdata_axi_s1_i16, fabric_fpga_rdata_axi_s1_i17, fabric_fpga_rdata_axi_s1_i18, fabric_fpga_rdata_axi_s1_i19, fabric_fpga_rdata_axi_s1_i20, fabric_fpga_rdata_axi_s1_i21, fabric_fpga_rdata_axi_s1_i22, fabric_fpga_rdata_axi_s1_i23, fabric_fpga_rdata_axi_s1_i24, fabric_fpga_rdata_axi_s1_i25, fabric_fpga_rdata_axi_s1_i26, fabric_fpga_rdata_axi_s1_i27, fabric_fpga_rdata_axi_s1_i28, fabric_fpga_rdata_axi_s1_i29, fabric_fpga_rdata_axi_s1_i30, fabric_fpga_rdata_axi_s1_i31
-, fabric_fpga_rdata_axi_s1_i32, fabric_fpga_rdata_axi_s1_i33, fabric_fpga_rdata_axi_s1_i34, fabric_fpga_rdata_axi_s1_i35, fabric_fpga_rdata_axi_s1_i36, fabric_fpga_rdata_axi_s1_i37, fabric_fpga_rdata_axi_s1_i38, fabric_fpga_rdata_axi_s1_i39, fabric_fpga_rdata_axi_s1_i40, fabric_fpga_rdata_axi_s1_i41, fabric_fpga_rdata_axi_s1_i42, fabric_fpga_rdata_axi_s1_i43, fabric_fpga_rdata_axi_s1_i44, fabric_fpga_rdata_axi_s1_i45, fabric_fpga_rdata_axi_s1_i46, fabric_fpga_rdata_axi_s1_i47, fabric_fpga_rdata_axi_s1_i48, fabric_fpga_rdata_axi_s1_i49, fabric_fpga_rdata_axi_s1_i50, fabric_fpga_rdata_axi_s1_i51, fabric_fpga_rdata_axi_s1_i52
-, fabric_fpga_rdata_axi_s1_i53, fabric_fpga_rdata_axi_s1_i54, fabric_fpga_rdata_axi_s1_i55, fabric_fpga_rdata_axi_s1_i56, fabric_fpga_rdata_axi_s1_i57, fabric_fpga_rdata_axi_s1_i58, fabric_fpga_rdata_axi_s1_i59, fabric_fpga_rdata_axi_s1_i60, fabric_fpga_rdata_axi_s1_i61, fabric_fpga_rdata_axi_s1_i62, fabric_fpga_rdata_axi_s1_i63, fabric_fpga_rdata_axi_s1_i64, fabric_fpga_rdata_axi_s1_i65, fabric_fpga_rdata_axi_s1_i66, fabric_fpga_rdata_axi_s1_i67, fabric_fpga_rdata_axi_s1_i68, fabric_fpga_rdata_axi_s1_i69, fabric_fpga_rdata_axi_s1_i70, fabric_fpga_rdata_axi_s1_i71, fabric_fpga_rdata_axi_s1_i72, fabric_fpga_rdata_axi_s1_i73
-, fabric_fpga_rdata_axi_s1_i74, fabric_fpga_rdata_axi_s1_i75, fabric_fpga_rdata_axi_s1_i76, fabric_fpga_rdata_axi_s1_i77, fabric_fpga_rdata_axi_s1_i78, fabric_fpga_rdata_axi_s1_i79, fabric_fpga_rdata_axi_s1_i80, fabric_fpga_rdata_axi_s1_i81, fabric_fpga_rdata_axi_s1_i82, fabric_fpga_rdata_axi_s1_i83, fabric_fpga_rdata_axi_s1_i84, fabric_fpga_rdata_axi_s1_i85, fabric_fpga_rdata_axi_s1_i86, fabric_fpga_rdata_axi_s1_i87, fabric_fpga_rdata_axi_s1_i88, fabric_fpga_rdata_axi_s1_i89, fabric_fpga_rdata_axi_s1_i90, fabric_fpga_rdata_axi_s1_i91, fabric_fpga_rdata_axi_s1_i92, fabric_fpga_rdata_axi_s1_i93, fabric_fpga_rdata_axi_s1_i94
-, fabric_fpga_rdata_axi_s1_i95, fabric_fpga_rdata_axi_s1_i96, fabric_fpga_rdata_axi_s1_i97, fabric_fpga_rdata_axi_s1_i98, fabric_fpga_rdata_axi_s1_i99, fabric_fpga_rdata_axi_s1_i100, fabric_fpga_rdata_axi_s1_i101, fabric_fpga_rdata_axi_s1_i102, fabric_fpga_rdata_axi_s1_i103, fabric_fpga_rdata_axi_s1_i104, fabric_fpga_rdata_axi_s1_i105, fabric_fpga_rdata_axi_s1_i106, fabric_fpga_rdata_axi_s1_i107, fabric_fpga_rdata_axi_s1_i108, fabric_fpga_rdata_axi_s1_i109, fabric_fpga_rdata_axi_s1_i110, fabric_fpga_rdata_axi_s1_i111, fabric_fpga_rdata_axi_s1_i112, fabric_fpga_rdata_axi_s1_i113, fabric_fpga_rdata_axi_s1_i114, fabric_fpga_rdata_axi_s1_i115
-, fabric_fpga_rdata_axi_s1_i116, fabric_fpga_rdata_axi_s1_i117, fabric_fpga_rdata_axi_s1_i118, fabric_fpga_rdata_axi_s1_i119, fabric_fpga_rdata_axi_s1_i120, fabric_fpga_rdata_axi_s1_i121, fabric_fpga_rdata_axi_s1_i122, fabric_fpga_rdata_axi_s1_i123, fabric_fpga_rdata_axi_s1_i124, fabric_fpga_rdata_axi_s1_i125, fabric_fpga_rdata_axi_s1_i126, fabric_fpga_rdata_axi_s1_i127, fabric_fpga_rdata_axi_s1_i128, fabric_fpga_rid_axi_s1_i1, fabric_fpga_rid_axi_s1_i2, fabric_fpga_rid_axi_s1_i3, fabric_fpga_rid_axi_s1_i4, fabric_fpga_rid_axi_s1_i5, fabric_fpga_rid_axi_s1_i6, fabric_fpga_rid_axi_s1_i7, fabric_fpga_rid_axi_s1_i8
-, fabric_fpga_rid_axi_s1_i9, fabric_fpga_rid_axi_s1_i10, fabric_fpga_rid_axi_s1_i11, fabric_fpga_rid_axi_s1_i12, fabric_fpga_rlast_axi_s1_i, fabric_fpga_rresp_axi_s1_i1, fabric_fpga_rresp_axi_s1_i2, fabric_fpga_rvalid_axi_s1_i, fabric_fpga_wready_axi_s1_i, fabric_fpga_araddr_axi_s2_o1, fabric_fpga_araddr_axi_s2_o2, fabric_fpga_araddr_axi_s2_o3, fabric_fpga_araddr_axi_s2_o4, fabric_fpga_araddr_axi_s2_o5, fabric_fpga_araddr_axi_s2_o6, fabric_fpga_araddr_axi_s2_o7, fabric_fpga_araddr_axi_s2_o8, fabric_fpga_araddr_axi_s2_o9, fabric_fpga_araddr_axi_s2_o10, fabric_fpga_araddr_axi_s2_o11, fabric_fpga_araddr_axi_s2_o12
-, fabric_fpga_araddr_axi_s2_o13, fabric_fpga_araddr_axi_s2_o14, fabric_fpga_araddr_axi_s2_o15, fabric_fpga_araddr_axi_s2_o16, fabric_fpga_araddr_axi_s2_o17, fabric_fpga_araddr_axi_s2_o18, fabric_fpga_araddr_axi_s2_o19, fabric_fpga_araddr_axi_s2_o20, fabric_fpga_araddr_axi_s2_o21, fabric_fpga_araddr_axi_s2_o22, fabric_fpga_araddr_axi_s2_o23, fabric_fpga_araddr_axi_s2_o24, fabric_fpga_araddr_axi_s2_o25, fabric_fpga_araddr_axi_s2_o26, fabric_fpga_araddr_axi_s2_o27, fabric_fpga_araddr_axi_s2_o28, fabric_fpga_araddr_axi_s2_o29, fabric_fpga_araddr_axi_s2_o30, fabric_fpga_araddr_axi_s2_o31, fabric_fpga_araddr_axi_s2_o32, fabric_fpga_araddr_axi_s2_o33
-, fabric_fpga_araddr_axi_s2_o34, fabric_fpga_araddr_axi_s2_o35, fabric_fpga_araddr_axi_s2_o36, fabric_fpga_araddr_axi_s2_o37, fabric_fpga_araddr_axi_s2_o38, fabric_fpga_araddr_axi_s2_o39, fabric_fpga_araddr_axi_s2_o40, fabric_fpga_arburst_axi_s2_o1, fabric_fpga_arburst_axi_s2_o2, fabric_fpga_arcache_axi_s2_o1, fabric_fpga_arcache_axi_s2_o2, fabric_fpga_arcache_axi_s2_o3, fabric_fpga_arcache_axi_s2_o4, fabric_fpga_arid_axi_s2_o1, fabric_fpga_arid_axi_s2_o2, fabric_fpga_arid_axi_s2_o3, fabric_fpga_arid_axi_s2_o4, fabric_fpga_arid_axi_s2_o5, fabric_fpga_arid_axi_s2_o6, fabric_fpga_arid_axi_s2_o7, fabric_fpga_arid_axi_s2_o8
-, fabric_fpga_arid_axi_s2_o9, fabric_fpga_arid_axi_s2_o10, fabric_fpga_arid_axi_s2_o11, fabric_fpga_arid_axi_s2_o12, fabric_fpga_arlen_axi_s2_o1, fabric_fpga_arlen_axi_s2_o2, fabric_fpga_arlen_axi_s2_o3, fabric_fpga_arlen_axi_s2_o4, fabric_fpga_arlen_axi_s2_o5, fabric_fpga_arlen_axi_s2_o6, fabric_fpga_arlen_axi_s2_o7, fabric_fpga_arlen_axi_s2_o8, fabric_fpga_arlock_axi_s2_o, fabric_fpga_arprot_axi_s2_o1, fabric_fpga_arprot_axi_s2_o2, fabric_fpga_arprot_axi_s2_o3, fabric_fpga_arqos_axi_s2_o1, fabric_fpga_arqos_axi_s2_o2, fabric_fpga_arqos_axi_s2_o3, fabric_fpga_arqos_axi_s2_o4, fabric_fpga_arregion_axi_s2_o1
-, fabric_fpga_arregion_axi_s2_o2, fabric_fpga_arregion_axi_s2_o3, fabric_fpga_arregion_axi_s2_o4, fabric_fpga_arsize_axi_s2_o1, fabric_fpga_arsize_axi_s2_o2, fabric_fpga_arsize_axi_s2_o3, fabric_fpga_arvalid_axi_s2_o, fabric_fpga_awaddr_axi_s2_o1, fabric_fpga_awaddr_axi_s2_o2, fabric_fpga_awaddr_axi_s2_o3, fabric_fpga_awaddr_axi_s2_o4, fabric_fpga_awaddr_axi_s2_o5, fabric_fpga_awaddr_axi_s2_o6, fabric_fpga_awaddr_axi_s2_o7, fabric_fpga_awaddr_axi_s2_o8, fabric_fpga_awaddr_axi_s2_o9, fabric_fpga_awaddr_axi_s2_o10, fabric_fpga_awaddr_axi_s2_o11, fabric_fpga_awaddr_axi_s2_o12, fabric_fpga_awaddr_axi_s2_o13, fabric_fpga_awaddr_axi_s2_o14
-, fabric_fpga_awaddr_axi_s2_o15, fabric_fpga_awaddr_axi_s2_o16, fabric_fpga_awaddr_axi_s2_o17, fabric_fpga_awaddr_axi_s2_o18, fabric_fpga_awaddr_axi_s2_o19, fabric_fpga_awaddr_axi_s2_o20, fabric_fpga_awaddr_axi_s2_o21, fabric_fpga_awaddr_axi_s2_o22, fabric_fpga_awaddr_axi_s2_o23, fabric_fpga_awaddr_axi_s2_o24, fabric_fpga_awaddr_axi_s2_o25, fabric_fpga_awaddr_axi_s2_o26, fabric_fpga_awaddr_axi_s2_o27, fabric_fpga_awaddr_axi_s2_o28, fabric_fpga_awaddr_axi_s2_o29, fabric_fpga_awaddr_axi_s2_o30, fabric_fpga_awaddr_axi_s2_o31, fabric_fpga_awaddr_axi_s2_o32, fabric_fpga_awaddr_axi_s2_o33, fabric_fpga_awaddr_axi_s2_o34, fabric_fpga_awaddr_axi_s2_o35
-, fabric_fpga_awaddr_axi_s2_o36, fabric_fpga_awaddr_axi_s2_o37, fabric_fpga_awaddr_axi_s2_o38, fabric_fpga_awaddr_axi_s2_o39, fabric_fpga_awaddr_axi_s2_o40, fabric_fpga_awburst_axi_s2_o1, fabric_fpga_awburst_axi_s2_o2, fabric_fpga_awcache_axi_s2_o1, fabric_fpga_awcache_axi_s2_o2, fabric_fpga_awcache_axi_s2_o3, fabric_fpga_awcache_axi_s2_o4, fabric_fpga_awid_axi_s2_o1, fabric_fpga_awid_axi_s2_o2, fabric_fpga_awid_axi_s2_o3, fabric_fpga_awid_axi_s2_o4, fabric_fpga_awid_axi_s2_o5, fabric_fpga_awid_axi_s2_o6, fabric_fpga_awid_axi_s2_o7, fabric_fpga_awid_axi_s2_o8, fabric_fpga_awid_axi_s2_o9, fabric_fpga_awid_axi_s2_o10
-, fabric_fpga_awid_axi_s2_o11, fabric_fpga_awid_axi_s2_o12, fabric_fpga_awlen_axi_s2_o1, fabric_fpga_awlen_axi_s2_o2, fabric_fpga_awlen_axi_s2_o3, fabric_fpga_awlen_axi_s2_o4, fabric_fpga_awlen_axi_s2_o5, fabric_fpga_awlen_axi_s2_o6, fabric_fpga_awlen_axi_s2_o7, fabric_fpga_awlen_axi_s2_o8, fabric_fpga_awlock_axi_s2_o, fabric_fpga_awprot_axi_s2_o1, fabric_fpga_awprot_axi_s2_o2, fabric_fpga_awprot_axi_s2_o3, fabric_fpga_awqos_axi_s2_o1, fabric_fpga_awqos_axi_s2_o2, fabric_fpga_awqos_axi_s2_o3, fabric_fpga_awqos_axi_s2_o4, fabric_fpga_awregion_axi_s2_o1, fabric_fpga_awregion_axi_s2_o2, fabric_fpga_awregion_axi_s2_o3
-, fabric_fpga_awregion_axi_s2_o4, fabric_fpga_awsize_axi_s2_o1, fabric_fpga_awsize_axi_s2_o2, fabric_fpga_awsize_axi_s2_o3, fabric_fpga_bready_axi_s2_o, fabric_fpga_rready_axi_s2_o, fabric_fpga_wdata_axi_s2_o1, fabric_fpga_wdata_axi_s2_o2, fabric_fpga_wdata_axi_s2_o3, fabric_fpga_wdata_axi_s2_o4, fabric_fpga_wdata_axi_s2_o5, fabric_fpga_wdata_axi_s2_o6, fabric_fpga_wdata_axi_s2_o7, fabric_fpga_wdata_axi_s2_o8, fabric_fpga_wdata_axi_s2_o9, fabric_fpga_wdata_axi_s2_o10, fabric_fpga_wdata_axi_s2_o11, fabric_fpga_wdata_axi_s2_o12, fabric_fpga_wdata_axi_s2_o13, fabric_fpga_wdata_axi_s2_o14, fabric_fpga_wdata_axi_s2_o15
-, fabric_fpga_wdata_axi_s2_o16, fabric_fpga_wdata_axi_s2_o17, fabric_fpga_wdata_axi_s2_o18, fabric_fpga_wdata_axi_s2_o19, fabric_fpga_wdata_axi_s2_o20, fabric_fpga_wdata_axi_s2_o21, fabric_fpga_wdata_axi_s2_o22, fabric_fpga_wdata_axi_s2_o23, fabric_fpga_wdata_axi_s2_o24, fabric_fpga_wdata_axi_s2_o25, fabric_fpga_wdata_axi_s2_o26, fabric_fpga_wdata_axi_s2_o27, fabric_fpga_wdata_axi_s2_o28, fabric_fpga_wdata_axi_s2_o29, fabric_fpga_wdata_axi_s2_o30, fabric_fpga_wdata_axi_s2_o31, fabric_fpga_wdata_axi_s2_o32, fabric_fpga_wdata_axi_s2_o33, fabric_fpga_wdata_axi_s2_o34, fabric_fpga_wdata_axi_s2_o35, fabric_fpga_wdata_axi_s2_o36
-, fabric_fpga_wdata_axi_s2_o37, fabric_fpga_wdata_axi_s2_o38, fabric_fpga_wdata_axi_s2_o39, fabric_fpga_wdata_axi_s2_o40, fabric_fpga_wdata_axi_s2_o41, fabric_fpga_wdata_axi_s2_o42, fabric_fpga_wdata_axi_s2_o43, fabric_fpga_wdata_axi_s2_o44, fabric_fpga_wdata_axi_s2_o45, fabric_fpga_wdata_axi_s2_o46, fabric_fpga_wdata_axi_s2_o47, fabric_fpga_wdata_axi_s2_o48, fabric_fpga_wdata_axi_s2_o49, fabric_fpga_wdata_axi_s2_o50, fabric_fpga_wdata_axi_s2_o51, fabric_fpga_wdata_axi_s2_o52, fabric_fpga_wdata_axi_s2_o53, fabric_fpga_wdata_axi_s2_o54, fabric_fpga_wdata_axi_s2_o55, fabric_fpga_wdata_axi_s2_o56, fabric_fpga_wdata_axi_s2_o57
-, fabric_fpga_wdata_axi_s2_o58, fabric_fpga_wdata_axi_s2_o59, fabric_fpga_wdata_axi_s2_o60, fabric_fpga_wdata_axi_s2_o61, fabric_fpga_wdata_axi_s2_o62, fabric_fpga_wdata_axi_s2_o63, fabric_fpga_wdata_axi_s2_o64, fabric_fpga_wdata_axi_s2_o65, fabric_fpga_wdata_axi_s2_o66, fabric_fpga_wdata_axi_s2_o67, fabric_fpga_wdata_axi_s2_o68, fabric_fpga_wdata_axi_s2_o69, fabric_fpga_wdata_axi_s2_o70, fabric_fpga_wdata_axi_s2_o71, fabric_fpga_wdata_axi_s2_o72, fabric_fpga_wdata_axi_s2_o73, fabric_fpga_wdata_axi_s2_o74, fabric_fpga_wdata_axi_s2_o75, fabric_fpga_wdata_axi_s2_o76, fabric_fpga_wdata_axi_s2_o77, fabric_fpga_wdata_axi_s2_o78
-, fabric_fpga_wdata_axi_s2_o79, fabric_fpga_wdata_axi_s2_o80, fabric_fpga_wdata_axi_s2_o81, fabric_fpga_wdata_axi_s2_o82, fabric_fpga_wdata_axi_s2_o83, fabric_fpga_wdata_axi_s2_o84, fabric_fpga_wdata_axi_s2_o85, fabric_fpga_wdata_axi_s2_o86, fabric_fpga_wdata_axi_s2_o87, fabric_fpga_wdata_axi_s2_o88, fabric_fpga_wdata_axi_s2_o89, fabric_fpga_wdata_axi_s2_o90, fabric_fpga_wdata_axi_s2_o91, fabric_fpga_wdata_axi_s2_o92, fabric_fpga_wdata_axi_s2_o93, fabric_fpga_wdata_axi_s2_o94, fabric_fpga_wdata_axi_s2_o95, fabric_fpga_wdata_axi_s2_o96, fabric_fpga_wdata_axi_s2_o97, fabric_fpga_wdata_axi_s2_o98, fabric_fpga_wdata_axi_s2_o99
-, fabric_fpga_wdata_axi_s2_o100, fabric_fpga_wdata_axi_s2_o101, fabric_fpga_wdata_axi_s2_o102, fabric_fpga_wdata_axi_s2_o103, fabric_fpga_wdata_axi_s2_o104, fabric_fpga_wdata_axi_s2_o105, fabric_fpga_wdata_axi_s2_o106, fabric_fpga_wdata_axi_s2_o107, fabric_fpga_wdata_axi_s2_o108, fabric_fpga_wdata_axi_s2_o109, fabric_fpga_wdata_axi_s2_o110, fabric_fpga_wdata_axi_s2_o111, fabric_fpga_wdata_axi_s2_o112, fabric_fpga_wdata_axi_s2_o113, fabric_fpga_wdata_axi_s2_o114, fabric_fpga_wdata_axi_s2_o115, fabric_fpga_wdata_axi_s2_o116, fabric_fpga_wdata_axi_s2_o117, fabric_fpga_wdata_axi_s2_o118, fabric_fpga_wdata_axi_s2_o119, fabric_fpga_wdata_axi_s2_o120
-, fabric_fpga_wdata_axi_s2_o121, fabric_fpga_wdata_axi_s2_o122, fabric_fpga_wdata_axi_s2_o123, fabric_fpga_wdata_axi_s2_o124, fabric_fpga_wdata_axi_s2_o125, fabric_fpga_wdata_axi_s2_o126, fabric_fpga_wdata_axi_s2_o127, fabric_fpga_wdata_axi_s2_o128, fabric_fpga_wlast_axi_s2_o, fabric_fpga_wstrb_axi_s2_o1, fabric_fpga_wstrb_axi_s2_o2, fabric_fpga_wstrb_axi_s2_o3, fabric_fpga_wstrb_axi_s2_o4, fabric_fpga_wstrb_axi_s2_o5, fabric_fpga_wstrb_axi_s2_o6, fabric_fpga_wstrb_axi_s2_o7, fabric_fpga_wstrb_axi_s2_o8, fabric_fpga_wstrb_axi_s2_o9, fabric_fpga_wstrb_axi_s2_o10, fabric_fpga_wstrb_axi_s2_o11, fabric_fpga_wstrb_axi_s2_o12
-, fabric_fpga_wstrb_axi_s2_o13, fabric_fpga_wstrb_axi_s2_o14, fabric_fpga_wstrb_axi_s2_o15, fabric_fpga_wstrb_axi_s2_o16, fabric_fpga_wvalid_axi_s2_o, fabric_fpga_awvalid_axi_s2_o, fabric_fpga_arready_axi_s2_i, fabric_fpga_awready_axi_s2_i, fabric_fpga_bid_axi_s2_i1, fabric_fpga_bid_axi_s2_i2, fabric_fpga_bid_axi_s2_i3, fabric_fpga_bid_axi_s2_i4, fabric_fpga_bid_axi_s2_i5, fabric_fpga_bid_axi_s2_i6, fabric_fpga_bid_axi_s2_i7, fabric_fpga_bid_axi_s2_i8, fabric_fpga_bid_axi_s2_i9, fabric_fpga_bid_axi_s2_i10, fabric_fpga_bid_axi_s2_i11, fabric_fpga_bid_axi_s2_i12, fabric_fpga_bresp_axi_s2_i1
-, fabric_fpga_bresp_axi_s2_i2, fabric_fpga_bvalid_axi_s2_i, fabric_fpga_rdata_axi_s2_i1, fabric_fpga_rdata_axi_s2_i2, fabric_fpga_rdata_axi_s2_i3, fabric_fpga_rdata_axi_s2_i4, fabric_fpga_rdata_axi_s2_i5, fabric_fpga_rdata_axi_s2_i6, fabric_fpga_rdata_axi_s2_i7, fabric_fpga_rdata_axi_s2_i8, fabric_fpga_rdata_axi_s2_i9, fabric_fpga_rdata_axi_s2_i10, fabric_fpga_rdata_axi_s2_i11, fabric_fpga_rdata_axi_s2_i12, fabric_fpga_rdata_axi_s2_i13, fabric_fpga_rdata_axi_s2_i14, fabric_fpga_rdata_axi_s2_i15, fabric_fpga_rdata_axi_s2_i16, fabric_fpga_rdata_axi_s2_i17, fabric_fpga_rdata_axi_s2_i18, fabric_fpga_rdata_axi_s2_i19
-, fabric_fpga_rdata_axi_s2_i20, fabric_fpga_rdata_axi_s2_i21, fabric_fpga_rdata_axi_s2_i22, fabric_fpga_rdata_axi_s2_i23, fabric_fpga_rdata_axi_s2_i24, fabric_fpga_rdata_axi_s2_i25, fabric_fpga_rdata_axi_s2_i26, fabric_fpga_rdata_axi_s2_i27, fabric_fpga_rdata_axi_s2_i28, fabric_fpga_rdata_axi_s2_i29, fabric_fpga_rdata_axi_s2_i30, fabric_fpga_rdata_axi_s2_i31, fabric_fpga_rdata_axi_s2_i32, fabric_fpga_rdata_axi_s2_i33, fabric_fpga_rdata_axi_s2_i34, fabric_fpga_rdata_axi_s2_i35, fabric_fpga_rdata_axi_s2_i36, fabric_fpga_rdata_axi_s2_i37, fabric_fpga_rdata_axi_s2_i38, fabric_fpga_rdata_axi_s2_i39, fabric_fpga_rdata_axi_s2_i40
-, fabric_fpga_rdata_axi_s2_i41, fabric_fpga_rdata_axi_s2_i42, fabric_fpga_rdata_axi_s2_i43, fabric_fpga_rdata_axi_s2_i44, fabric_fpga_rdata_axi_s2_i45, fabric_fpga_rdata_axi_s2_i46, fabric_fpga_rdata_axi_s2_i47, fabric_fpga_rdata_axi_s2_i48, fabric_fpga_rdata_axi_s2_i49, fabric_fpga_rdata_axi_s2_i50, fabric_fpga_rdata_axi_s2_i51, fabric_fpga_rdata_axi_s2_i52, fabric_fpga_rdata_axi_s2_i53, fabric_fpga_rdata_axi_s2_i54, fabric_fpga_rdata_axi_s2_i55, fabric_fpga_rdata_axi_s2_i56, fabric_fpga_rdata_axi_s2_i57, fabric_fpga_rdata_axi_s2_i58, fabric_fpga_rdata_axi_s2_i59, fabric_fpga_rdata_axi_s2_i60, fabric_fpga_rdata_axi_s2_i61
-, fabric_fpga_rdata_axi_s2_i62, fabric_fpga_rdata_axi_s2_i63, fabric_fpga_rdata_axi_s2_i64, fabric_fpga_rdata_axi_s2_i65, fabric_fpga_rdata_axi_s2_i66, fabric_fpga_rdata_axi_s2_i67, fabric_fpga_rdata_axi_s2_i68, fabric_fpga_rdata_axi_s2_i69, fabric_fpga_rdata_axi_s2_i70, fabric_fpga_rdata_axi_s2_i71, fabric_fpga_rdata_axi_s2_i72, fabric_fpga_rdata_axi_s2_i73, fabric_fpga_rdata_axi_s2_i74, fabric_fpga_rdata_axi_s2_i75, fabric_fpga_rdata_axi_s2_i76, fabric_fpga_rdata_axi_s2_i77, fabric_fpga_rdata_axi_s2_i78, fabric_fpga_rdata_axi_s2_i79, fabric_fpga_rdata_axi_s2_i80, fabric_fpga_rdata_axi_s2_i81, fabric_fpga_rdata_axi_s2_i82
-, fabric_fpga_rdata_axi_s2_i83, fabric_fpga_rdata_axi_s2_i84, fabric_fpga_rdata_axi_s2_i85, fabric_fpga_rdata_axi_s2_i86, fabric_fpga_rdata_axi_s2_i87, fabric_fpga_rdata_axi_s2_i88, fabric_fpga_rdata_axi_s2_i89, fabric_fpga_rdata_axi_s2_i90, fabric_fpga_rdata_axi_s2_i91, fabric_fpga_rdata_axi_s2_i92, fabric_fpga_rdata_axi_s2_i93, fabric_fpga_rdata_axi_s2_i94, fabric_fpga_rdata_axi_s2_i95, fabric_fpga_rdata_axi_s2_i96, fabric_fpga_rdata_axi_s2_i97, fabric_fpga_rdata_axi_s2_i98, fabric_fpga_rdata_axi_s2_i99, fabric_fpga_rdata_axi_s2_i100, fabric_fpga_rdata_axi_s2_i101, fabric_fpga_rdata_axi_s2_i102, fabric_fpga_rdata_axi_s2_i103
-, fabric_fpga_rdata_axi_s2_i104, fabric_fpga_rdata_axi_s2_i105, fabric_fpga_rdata_axi_s2_i106, fabric_fpga_rdata_axi_s2_i107, fabric_fpga_rdata_axi_s2_i108, fabric_fpga_rdata_axi_s2_i109, fabric_fpga_rdata_axi_s2_i110, fabric_fpga_rdata_axi_s2_i111, fabric_fpga_rdata_axi_s2_i112, fabric_fpga_rdata_axi_s2_i113, fabric_fpga_rdata_axi_s2_i114, fabric_fpga_rdata_axi_s2_i115, fabric_fpga_rdata_axi_s2_i116, fabric_fpga_rdata_axi_s2_i117, fabric_fpga_rdata_axi_s2_i118, fabric_fpga_rdata_axi_s2_i119, fabric_fpga_rdata_axi_s2_i120, fabric_fpga_rdata_axi_s2_i121, fabric_fpga_rdata_axi_s2_i122, fabric_fpga_rdata_axi_s2_i123, fabric_fpga_rdata_axi_s2_i124
-, fabric_fpga_rdata_axi_s2_i125, fabric_fpga_rdata_axi_s2_i126, fabric_fpga_rdata_axi_s2_i127, fabric_fpga_rdata_axi_s2_i128, fabric_fpga_rid_axi_s2_i1, fabric_fpga_rid_axi_s2_i2, fabric_fpga_rid_axi_s2_i3, fabric_fpga_rid_axi_s2_i4, fabric_fpga_rid_axi_s2_i5, fabric_fpga_rid_axi_s2_i6, fabric_fpga_rid_axi_s2_i7, fabric_fpga_rid_axi_s2_i8, fabric_fpga_rid_axi_s2_i9, fabric_fpga_rid_axi_s2_i10, fabric_fpga_rid_axi_s2_i11, fabric_fpga_rid_axi_s2_i12, fabric_fpga_rlast_axi_s2_i, fabric_fpga_rresp_axi_s2_i1, fabric_fpga_rresp_axi_s2_i2, fabric_fpga_rvalid_axi_s2_i, fabric_fpga_wready_axi_s2_i
-, fabric_fpga_arready_axi_m1_o, fabric_fpga_awready_axi_m1_o, fabric_fpga_bid_axi_m1_o1, fabric_fpga_bid_axi_m1_o2, fabric_fpga_bid_axi_m1_o3, fabric_fpga_bid_axi_m1_o4, fabric_fpga_bid_axi_m1_o5, fabric_fpga_bresp_axi_m1_o1, fabric_fpga_bresp_axi_m1_o2, fabric_fpga_bvalid_axi_m1_o, fabric_fpga_dma_ack_m1_o1, fabric_fpga_dma_ack_m1_o2, fabric_fpga_dma_ack_m1_o3, fabric_fpga_dma_ack_m1_o4, fabric_fpga_dma_ack_m1_o5, fabric_fpga_dma_ack_m1_o6, fabric_fpga_dma_finish_m1_o1, fabric_fpga_dma_finish_m1_o2, fabric_fpga_dma_finish_m1_o3, fabric_fpga_dma_finish_m1_o4, fabric_fpga_dma_finish_m1_o5
-, fabric_fpga_dma_finish_m1_o6, fabric_fpga_rdata_axi_m1_o1, fabric_fpga_rdata_axi_m1_o2, fabric_fpga_rdata_axi_m1_o3, fabric_fpga_rdata_axi_m1_o4, fabric_fpga_rdata_axi_m1_o5, fabric_fpga_rdata_axi_m1_o6, fabric_fpga_rdata_axi_m1_o7, fabric_fpga_rdata_axi_m1_o8, fabric_fpga_rdata_axi_m1_o9, fabric_fpga_rdata_axi_m1_o10, fabric_fpga_rdata_axi_m1_o11, fabric_fpga_rdata_axi_m1_o12, fabric_fpga_rdata_axi_m1_o13, fabric_fpga_rdata_axi_m1_o14, fabric_fpga_rdata_axi_m1_o15, fabric_fpga_rdata_axi_m1_o16, fabric_fpga_rdata_axi_m1_o17, fabric_fpga_rdata_axi_m1_o18, fabric_fpga_rdata_axi_m1_o19, fabric_fpga_rdata_axi_m1_o20
-, fabric_fpga_rdata_axi_m1_o21, fabric_fpga_rdata_axi_m1_o22, fabric_fpga_rdata_axi_m1_o23, fabric_fpga_rdata_axi_m1_o24, fabric_fpga_rdata_axi_m1_o25, fabric_fpga_rdata_axi_m1_o26, fabric_fpga_rdata_axi_m1_o27, fabric_fpga_rdata_axi_m1_o28, fabric_fpga_rdata_axi_m1_o29, fabric_fpga_rdata_axi_m1_o30, fabric_fpga_rdata_axi_m1_o31, fabric_fpga_rdata_axi_m1_o32, fabric_fpga_rdata_axi_m1_o33, fabric_fpga_rdata_axi_m1_o34, fabric_fpga_rdata_axi_m1_o35, fabric_fpga_rdata_axi_m1_o36, fabric_fpga_rdata_axi_m1_o37, fabric_fpga_rdata_axi_m1_o38, fabric_fpga_rdata_axi_m1_o39, fabric_fpga_rdata_axi_m1_o40, fabric_fpga_rdata_axi_m1_o41
-, fabric_fpga_rdata_axi_m1_o42, fabric_fpga_rdata_axi_m1_o43, fabric_fpga_rdata_axi_m1_o44, fabric_fpga_rdata_axi_m1_o45, fabric_fpga_rdata_axi_m1_o46, fabric_fpga_rdata_axi_m1_o47, fabric_fpga_rdata_axi_m1_o48, fabric_fpga_rdata_axi_m1_o49, fabric_fpga_rdata_axi_m1_o50, fabric_fpga_rdata_axi_m1_o51, fabric_fpga_rdata_axi_m1_o52, fabric_fpga_rdata_axi_m1_o53, fabric_fpga_rdata_axi_m1_o54, fabric_fpga_rdata_axi_m1_o55, fabric_fpga_rdata_axi_m1_o56, fabric_fpga_rdata_axi_m1_o57, fabric_fpga_rdata_axi_m1_o58, fabric_fpga_rdata_axi_m1_o59, fabric_fpga_rdata_axi_m1_o60, fabric_fpga_rdata_axi_m1_o61, fabric_fpga_rdata_axi_m1_o62
-, fabric_fpga_rdata_axi_m1_o63, fabric_fpga_rdata_axi_m1_o64, fabric_fpga_rdata_axi_m1_o65, fabric_fpga_rdata_axi_m1_o66, fabric_fpga_rdata_axi_m1_o67, fabric_fpga_rdata_axi_m1_o68, fabric_fpga_rdata_axi_m1_o69, fabric_fpga_rdata_axi_m1_o70, fabric_fpga_rdata_axi_m1_o71, fabric_fpga_rdata_axi_m1_o72, fabric_fpga_rdata_axi_m1_o73, fabric_fpga_rdata_axi_m1_o74, fabric_fpga_rdata_axi_m1_o75, fabric_fpga_rdata_axi_m1_o76, fabric_fpga_rdata_axi_m1_o77, fabric_fpga_rdata_axi_m1_o78, fabric_fpga_rdata_axi_m1_o79, fabric_fpga_rdata_axi_m1_o80, fabric_fpga_rdata_axi_m1_o81, fabric_fpga_rdata_axi_m1_o82, fabric_fpga_rdata_axi_m1_o83
-, fabric_fpga_rdata_axi_m1_o84, fabric_fpga_rdata_axi_m1_o85, fabric_fpga_rdata_axi_m1_o86, fabric_fpga_rdata_axi_m1_o87, fabric_fpga_rdata_axi_m1_o88, fabric_fpga_rdata_axi_m1_o89, fabric_fpga_rdata_axi_m1_o90, fabric_fpga_rdata_axi_m1_o91, fabric_fpga_rdata_axi_m1_o92, fabric_fpga_rdata_axi_m1_o93, fabric_fpga_rdata_axi_m1_o94, fabric_fpga_rdata_axi_m1_o95, fabric_fpga_rdata_axi_m1_o96, fabric_fpga_rdata_axi_m1_o97, fabric_fpga_rdata_axi_m1_o98, fabric_fpga_rdata_axi_m1_o99, fabric_fpga_rdata_axi_m1_o100, fabric_fpga_rdata_axi_m1_o101, fabric_fpga_rdata_axi_m1_o102, fabric_fpga_rdata_axi_m1_o103, fabric_fpga_rdata_axi_m1_o104
-, fabric_fpga_rdata_axi_m1_o105, fabric_fpga_rdata_axi_m1_o106, fabric_fpga_rdata_axi_m1_o107, fabric_fpga_rdata_axi_m1_o108, fabric_fpga_rdata_axi_m1_o109, fabric_fpga_rdata_axi_m1_o110, fabric_fpga_rdata_axi_m1_o111, fabric_fpga_rdata_axi_m1_o112, fabric_fpga_rdata_axi_m1_o113, fabric_fpga_rdata_axi_m1_o114, fabric_fpga_rdata_axi_m1_o115, fabric_fpga_rdata_axi_m1_o116, fabric_fpga_rdata_axi_m1_o117, fabric_fpga_rdata_axi_m1_o118, fabric_fpga_rdata_axi_m1_o119, fabric_fpga_rdata_axi_m1_o120, fabric_fpga_rdata_axi_m1_o121, fabric_fpga_rdata_axi_m1_o122, fabric_fpga_rdata_axi_m1_o123, fabric_fpga_rdata_axi_m1_o124, fabric_fpga_rdata_axi_m1_o125
-, fabric_fpga_rdata_axi_m1_o126, fabric_fpga_rdata_axi_m1_o127, fabric_fpga_rdata_axi_m1_o128, fabric_fpga_rid_axi_m1_o1, fabric_fpga_rid_axi_m1_o2, fabric_fpga_rid_axi_m1_o3, fabric_fpga_rid_axi_m1_o4, fabric_fpga_rid_axi_m1_o5, fabric_fpga_rlast_axi_m1_o, fabric_fpga_rresp_axi_m1_o1, fabric_fpga_rresp_axi_m1_o2, fabric_fpga_rvalid_axi_m1_o, fabric_fpga_wready_axi_m1_o, fabric_fpga_araddr_axi_m1_i1, fabric_fpga_araddr_axi_m1_i2, fabric_fpga_araddr_axi_m1_i3, fabric_fpga_araddr_axi_m1_i4, fabric_fpga_araddr_axi_m1_i5, fabric_fpga_araddr_axi_m1_i6, fabric_fpga_araddr_axi_m1_i7, fabric_fpga_araddr_axi_m1_i8
-, fabric_fpga_araddr_axi_m1_i9, fabric_fpga_araddr_axi_m1_i10, fabric_fpga_araddr_axi_m1_i11, fabric_fpga_araddr_axi_m1_i12, fabric_fpga_araddr_axi_m1_i13, fabric_fpga_araddr_axi_m1_i14, fabric_fpga_araddr_axi_m1_i15, fabric_fpga_araddr_axi_m1_i16, fabric_fpga_araddr_axi_m1_i17, fabric_fpga_araddr_axi_m1_i18, fabric_fpga_araddr_axi_m1_i19, fabric_fpga_araddr_axi_m1_i20, fabric_fpga_araddr_axi_m1_i21, fabric_fpga_araddr_axi_m1_i22, fabric_fpga_araddr_axi_m1_i23, fabric_fpga_araddr_axi_m1_i24, fabric_fpga_araddr_axi_m1_i25, fabric_fpga_araddr_axi_m1_i26, fabric_fpga_araddr_axi_m1_i27, fabric_fpga_araddr_axi_m1_i28, fabric_fpga_araddr_axi_m1_i29
-, fabric_fpga_araddr_axi_m1_i30, fabric_fpga_araddr_axi_m1_i31, fabric_fpga_araddr_axi_m1_i32, fabric_fpga_araddr_axi_m1_i33, fabric_fpga_araddr_axi_m1_i34, fabric_fpga_araddr_axi_m1_i35, fabric_fpga_araddr_axi_m1_i36, fabric_fpga_araddr_axi_m1_i37, fabric_fpga_araddr_axi_m1_i38, fabric_fpga_araddr_axi_m1_i39, fabric_fpga_araddr_axi_m1_i40, fabric_fpga_arburst_axi_m1_i1, fabric_fpga_arburst_axi_m1_i2, fabric_fpga_arcache_axi_m1_i1, fabric_fpga_arcache_axi_m1_i2, fabric_fpga_arcache_axi_m1_i3, fabric_fpga_arcache_axi_m1_i4, fabric_fpga_arid_axi_m1_i1, fabric_fpga_arid_axi_m1_i2, fabric_fpga_arid_axi_m1_i3, fabric_fpga_arid_axi_m1_i4
-, fabric_fpga_arid_axi_m1_i5, fabric_fpga_arlen_axi_m1_i1, fabric_fpga_arlen_axi_m1_i2, fabric_fpga_arlen_axi_m1_i3, fabric_fpga_arlen_axi_m1_i4, fabric_fpga_arlen_axi_m1_i5, fabric_fpga_arlen_axi_m1_i6, fabric_fpga_arlen_axi_m1_i7, fabric_fpga_arlen_axi_m1_i8, fabric_fpga_arlock_axi_m1_i, fabric_fpga_arprot_axi_m1_i1, fabric_fpga_arprot_axi_m1_i2, fabric_fpga_arprot_axi_m1_i3, fabric_fpga_arqos_axi_m1_i1, fabric_fpga_arqos_axi_m1_i2, fabric_fpga_arqos_axi_m1_i3, fabric_fpga_arqos_axi_m1_i4, fabric_fpga_arsize_axi_m1_i1, fabric_fpga_arsize_axi_m1_i2, fabric_fpga_arsize_axi_m1_i3, fabric_fpga_arvalid_axi_m1_i
-, fabric_fpga_awaddr_axi_m1_i1, fabric_fpga_awaddr_axi_m1_i2, fabric_fpga_awaddr_axi_m1_i3, fabric_fpga_awaddr_axi_m1_i4, fabric_fpga_awaddr_axi_m1_i5, fabric_fpga_awaddr_axi_m1_i6, fabric_fpga_awaddr_axi_m1_i7, fabric_fpga_awaddr_axi_m1_i8, fabric_fpga_awaddr_axi_m1_i9, fabric_fpga_awaddr_axi_m1_i10, fabric_fpga_awaddr_axi_m1_i11, fabric_fpga_awaddr_axi_m1_i12, fabric_fpga_awaddr_axi_m1_i13, fabric_fpga_awaddr_axi_m1_i14, fabric_fpga_awaddr_axi_m1_i15, fabric_fpga_awaddr_axi_m1_i16, fabric_fpga_awaddr_axi_m1_i17, fabric_fpga_awaddr_axi_m1_i18, fabric_fpga_awaddr_axi_m1_i19, fabric_fpga_awaddr_axi_m1_i20, fabric_fpga_awaddr_axi_m1_i21
-, fabric_fpga_awaddr_axi_m1_i22, fabric_fpga_awaddr_axi_m1_i23, fabric_fpga_awaddr_axi_m1_i24, fabric_fpga_awaddr_axi_m1_i25, fabric_fpga_awaddr_axi_m1_i26, fabric_fpga_awaddr_axi_m1_i27, fabric_fpga_awaddr_axi_m1_i28, fabric_fpga_awaddr_axi_m1_i29, fabric_fpga_awaddr_axi_m1_i30, fabric_fpga_awaddr_axi_m1_i31, fabric_fpga_awaddr_axi_m1_i32, fabric_fpga_awaddr_axi_m1_i33, fabric_fpga_awaddr_axi_m1_i34, fabric_fpga_awaddr_axi_m1_i35, fabric_fpga_awaddr_axi_m1_i36, fabric_fpga_awaddr_axi_m1_i37, fabric_fpga_awaddr_axi_m1_i38, fabric_fpga_awaddr_axi_m1_i39, fabric_fpga_awaddr_axi_m1_i40, fabric_fpga_awburst_axi_m1_i1, fabric_fpga_awburst_axi_m1_i2
-, fabric_fpga_awcache_axi_m1_i1, fabric_fpga_awcache_axi_m1_i2, fabric_fpga_awcache_axi_m1_i3, fabric_fpga_awcache_axi_m1_i4, fabric_fpga_awid_axi_m1_i1, fabric_fpga_awid_axi_m1_i2, fabric_fpga_awid_axi_m1_i3, fabric_fpga_awid_axi_m1_i4, fabric_fpga_awid_axi_m1_i5, fabric_fpga_awlen_axi_m1_i1, fabric_fpga_awlen_axi_m1_i2, fabric_fpga_awlen_axi_m1_i3, fabric_fpga_awlen_axi_m1_i4, fabric_fpga_awlen_axi_m1_i5, fabric_fpga_awlen_axi_m1_i6, fabric_fpga_awlen_axi_m1_i7, fabric_fpga_awlen_axi_m1_i8, fabric_fpga_awlock_axi_m1_i, fabric_fpga_awprot_axi_m1_i1, fabric_fpga_awprot_axi_m1_i2, fabric_fpga_awprot_axi_m1_i3
-, fabric_fpga_awqos_axi_m1_i1, fabric_fpga_awqos_axi_m1_i2, fabric_fpga_awqos_axi_m1_i3, fabric_fpga_awqos_axi_m1_i4, fabric_fpga_awsize_axi_m1_i1, fabric_fpga_awsize_axi_m1_i2, fabric_fpga_awsize_axi_m1_i3, fabric_fpga_awvalid_axi_m1_i, fabric_fpga_bready_axi_m1_i, fabric_fpga_dma_last_m1_i1, fabric_fpga_dma_last_m1_i2, fabric_fpga_dma_last_m1_i3, fabric_fpga_dma_last_m1_i4, fabric_fpga_dma_last_m1_i5, fabric_fpga_dma_last_m1_i6, fabric_fpga_dma_req_m1_i1, fabric_fpga_dma_req_m1_i2, fabric_fpga_dma_req_m1_i3, fabric_fpga_dma_req_m1_i4, fabric_fpga_dma_req_m1_i5, fabric_fpga_dma_req_m1_i6
-, fabric_fpga_dma_single_m1_i1, fabric_fpga_dma_single_m1_i2, fabric_fpga_dma_single_m1_i3, fabric_fpga_dma_single_m1_i4, fabric_fpga_dma_single_m1_i5, fabric_fpga_dma_single_m1_i6, fabric_fpga_rready_axi_m1_i, fabric_fpga_wdata_axi_m1_i1, fabric_fpga_wdata_axi_m1_i2, fabric_fpga_wdata_axi_m1_i3, fabric_fpga_wdata_axi_m1_i4, fabric_fpga_wdata_axi_m1_i5, fabric_fpga_wdata_axi_m1_i6, fabric_fpga_wdata_axi_m1_i7, fabric_fpga_wdata_axi_m1_i8, fabric_fpga_wdata_axi_m1_i9, fabric_fpga_wdata_axi_m1_i10, fabric_fpga_wdata_axi_m1_i11, fabric_fpga_wdata_axi_m1_i12, fabric_fpga_wdata_axi_m1_i13, fabric_fpga_wdata_axi_m1_i14
-, fabric_fpga_wdata_axi_m1_i15, fabric_fpga_wdata_axi_m1_i16, fabric_fpga_wdata_axi_m1_i17, fabric_fpga_wdata_axi_m1_i18, fabric_fpga_wdata_axi_m1_i19, fabric_fpga_wdata_axi_m1_i20, fabric_fpga_wdata_axi_m1_i21, fabric_fpga_wdata_axi_m1_i22, fabric_fpga_wdata_axi_m1_i23, fabric_fpga_wdata_axi_m1_i24, fabric_fpga_wdata_axi_m1_i25, fabric_fpga_wdata_axi_m1_i26, fabric_fpga_wdata_axi_m1_i27, fabric_fpga_wdata_axi_m1_i28, fabric_fpga_wdata_axi_m1_i29, fabric_fpga_wdata_axi_m1_i30, fabric_fpga_wdata_axi_m1_i31, fabric_fpga_wdata_axi_m1_i32, fabric_fpga_wdata_axi_m1_i33, fabric_fpga_wdata_axi_m1_i34, fabric_fpga_wdata_axi_m1_i35
-, fabric_fpga_wdata_axi_m1_i36, fabric_fpga_wdata_axi_m1_i37, fabric_fpga_wdata_axi_m1_i38, fabric_fpga_wdata_axi_m1_i39, fabric_fpga_wdata_axi_m1_i40, fabric_fpga_wdata_axi_m1_i41, fabric_fpga_wdata_axi_m1_i42, fabric_fpga_wdata_axi_m1_i43, fabric_fpga_wdata_axi_m1_i44, fabric_fpga_wdata_axi_m1_i45, fabric_fpga_wdata_axi_m1_i46, fabric_fpga_wdata_axi_m1_i47, fabric_fpga_wdata_axi_m1_i48, fabric_fpga_wdata_axi_m1_i49, fabric_fpga_wdata_axi_m1_i50, fabric_fpga_wdata_axi_m1_i51, fabric_fpga_wdata_axi_m1_i52, fabric_fpga_wdata_axi_m1_i53, fabric_fpga_wdata_axi_m1_i54, fabric_fpga_wdata_axi_m1_i55, fabric_fpga_wdata_axi_m1_i56
-, fabric_fpga_wdata_axi_m1_i57, fabric_fpga_wdata_axi_m1_i58, fabric_fpga_wdata_axi_m1_i59, fabric_fpga_wdata_axi_m1_i60, fabric_fpga_wdata_axi_m1_i61, fabric_fpga_wdata_axi_m1_i62, fabric_fpga_wdata_axi_m1_i63, fabric_fpga_wdata_axi_m1_i64, fabric_fpga_wdata_axi_m1_i65, fabric_fpga_wdata_axi_m1_i66, fabric_fpga_wdata_axi_m1_i67, fabric_fpga_wdata_axi_m1_i68, fabric_fpga_wdata_axi_m1_i69, fabric_fpga_wdata_axi_m1_i70, fabric_fpga_wdata_axi_m1_i71, fabric_fpga_wdata_axi_m1_i72, fabric_fpga_wdata_axi_m1_i73, fabric_fpga_wdata_axi_m1_i74, fabric_fpga_wdata_axi_m1_i75, fabric_fpga_wdata_axi_m1_i76, fabric_fpga_wdata_axi_m1_i77
-, fabric_fpga_wdata_axi_m1_i78, fabric_fpga_wdata_axi_m1_i79, fabric_fpga_wdata_axi_m1_i80, fabric_fpga_wdata_axi_m1_i81, fabric_fpga_wdata_axi_m1_i82, fabric_fpga_wdata_axi_m1_i83, fabric_fpga_wdata_axi_m1_i84, fabric_fpga_wdata_axi_m1_i85, fabric_fpga_wdata_axi_m1_i86, fabric_fpga_wdata_axi_m1_i87, fabric_fpga_wdata_axi_m1_i88, fabric_fpga_wdata_axi_m1_i89, fabric_fpga_wdata_axi_m1_i90, fabric_fpga_wdata_axi_m1_i91, fabric_fpga_wdata_axi_m1_i92, fabric_fpga_wdata_axi_m1_i93, fabric_fpga_wdata_axi_m1_i94, fabric_fpga_wdata_axi_m1_i95, fabric_fpga_wdata_axi_m1_i96, fabric_fpga_wdata_axi_m1_i97, fabric_fpga_wdata_axi_m1_i98
-, fabric_fpga_wdata_axi_m1_i99, fabric_fpga_wdata_axi_m1_i100, fabric_fpga_wdata_axi_m1_i101, fabric_fpga_wdata_axi_m1_i102, fabric_fpga_wdata_axi_m1_i103, fabric_fpga_wdata_axi_m1_i104, fabric_fpga_wdata_axi_m1_i105, fabric_fpga_wdata_axi_m1_i106, fabric_fpga_wdata_axi_m1_i107, fabric_fpga_wdata_axi_m1_i108, fabric_fpga_wdata_axi_m1_i109, fabric_fpga_wdata_axi_m1_i110, fabric_fpga_wdata_axi_m1_i111, fabric_fpga_wdata_axi_m1_i112, fabric_fpga_wdata_axi_m1_i113, fabric_fpga_wdata_axi_m1_i114, fabric_fpga_wdata_axi_m1_i115, fabric_fpga_wdata_axi_m1_i116, fabric_fpga_wdata_axi_m1_i117, fabric_fpga_wdata_axi_m1_i118, fabric_fpga_wdata_axi_m1_i119
-, fabric_fpga_wdata_axi_m1_i120, fabric_fpga_wdata_axi_m1_i121, fabric_fpga_wdata_axi_m1_i122, fabric_fpga_wdata_axi_m1_i123, fabric_fpga_wdata_axi_m1_i124, fabric_fpga_wdata_axi_m1_i125, fabric_fpga_wdata_axi_m1_i126, fabric_fpga_wdata_axi_m1_i127, fabric_fpga_wdata_axi_m1_i128, fabric_fpga_wlast_axi_m1_i, fabric_fpga_wstrb_axi_m1_i1, fabric_fpga_wstrb_axi_m1_i2, fabric_fpga_wstrb_axi_m1_i3, fabric_fpga_wstrb_axi_m1_i4, fabric_fpga_wstrb_axi_m1_i5, fabric_fpga_wstrb_axi_m1_i6, fabric_fpga_wstrb_axi_m1_i7, fabric_fpga_wstrb_axi_m1_i8, fabric_fpga_wstrb_axi_m1_i9, fabric_fpga_wstrb_axi_m1_i10, fabric_fpga_wstrb_axi_m1_i11
-, fabric_fpga_wstrb_axi_m1_i12, fabric_fpga_wstrb_axi_m1_i13, fabric_fpga_wstrb_axi_m1_i14, fabric_fpga_wstrb_axi_m1_i15, fabric_fpga_wstrb_axi_m1_i16, fabric_fpga_wvalid_axi_m1_i, fabric_fpga_arready_axi_m2_o, fabric_fpga_awready_axi_m2_o, fabric_fpga_bid_axi_m2_o1, fabric_fpga_bid_axi_m2_o2, fabric_fpga_bid_axi_m2_o3, fabric_fpga_bid_axi_m2_o4, fabric_fpga_bid_axi_m2_o5, fabric_fpga_bresp_axi_m2_o1, fabric_fpga_bresp_axi_m2_o2, fabric_fpga_bvalid_axi_m2_o, fabric_fpga_dma_ack_m2_o1, fabric_fpga_dma_ack_m2_o2, fabric_fpga_dma_ack_m2_o3, fabric_fpga_dma_ack_m2_o4, fabric_fpga_dma_ack_m2_o5
-, fabric_fpga_dma_ack_m2_o6, fabric_fpga_dma_finish_m2_o1, fabric_fpga_dma_finish_m2_o2, fabric_fpga_dma_finish_m2_o3, fabric_fpga_dma_finish_m2_o4, fabric_fpga_dma_finish_m2_o5, fabric_fpga_dma_finish_m2_o6, fabric_fpga_rdata_axi_m2_o1, fabric_fpga_rdata_axi_m2_o2, fabric_fpga_rdata_axi_m2_o3, fabric_fpga_rdata_axi_m2_o4, fabric_fpga_rdata_axi_m2_o5, fabric_fpga_rdata_axi_m2_o6, fabric_fpga_rdata_axi_m2_o7, fabric_fpga_rdata_axi_m2_o8, fabric_fpga_rdata_axi_m2_o9, fabric_fpga_rdata_axi_m2_o10, fabric_fpga_rdata_axi_m2_o11, fabric_fpga_rdata_axi_m2_o12, fabric_fpga_rdata_axi_m2_o13, fabric_fpga_rdata_axi_m2_o14
-, fabric_fpga_rdata_axi_m2_o15, fabric_fpga_rdata_axi_m2_o16, fabric_fpga_rdata_axi_m2_o17, fabric_fpga_rdata_axi_m2_o18, fabric_fpga_rdata_axi_m2_o19, fabric_fpga_rdata_axi_m2_o20, fabric_fpga_rdata_axi_m2_o21, fabric_fpga_rdata_axi_m2_o22, fabric_fpga_rdata_axi_m2_o23, fabric_fpga_rdata_axi_m2_o24, fabric_fpga_rdata_axi_m2_o25, fabric_fpga_rdata_axi_m2_o26, fabric_fpga_rdata_axi_m2_o27, fabric_fpga_rdata_axi_m2_o28, fabric_fpga_rdata_axi_m2_o29, fabric_fpga_rdata_axi_m2_o30, fabric_fpga_rdata_axi_m2_o31, fabric_fpga_rdata_axi_m2_o32, fabric_fpga_rdata_axi_m2_o33, fabric_fpga_rdata_axi_m2_o34, fabric_fpga_rdata_axi_m2_o35
-, fabric_fpga_rdata_axi_m2_o36, fabric_fpga_rdata_axi_m2_o37, fabric_fpga_rdata_axi_m2_o38, fabric_fpga_rdata_axi_m2_o39, fabric_fpga_rdata_axi_m2_o40, fabric_fpga_rdata_axi_m2_o41, fabric_fpga_rdata_axi_m2_o42, fabric_fpga_rdata_axi_m2_o43, fabric_fpga_rdata_axi_m2_o44, fabric_fpga_rdata_axi_m2_o45, fabric_fpga_rdata_axi_m2_o46, fabric_fpga_rdata_axi_m2_o47, fabric_fpga_rdata_axi_m2_o48, fabric_fpga_rdata_axi_m2_o49, fabric_fpga_rdata_axi_m2_o50, fabric_fpga_rdata_axi_m2_o51, fabric_fpga_rdata_axi_m2_o52, fabric_fpga_rdata_axi_m2_o53, fabric_fpga_rdata_axi_m2_o54, fabric_fpga_rdata_axi_m2_o55, fabric_fpga_rdata_axi_m2_o56
-, fabric_fpga_rdata_axi_m2_o57, fabric_fpga_rdata_axi_m2_o58, fabric_fpga_rdata_axi_m2_o59, fabric_fpga_rdata_axi_m2_o60, fabric_fpga_rdata_axi_m2_o61, fabric_fpga_rdata_axi_m2_o62, fabric_fpga_rdata_axi_m2_o63, fabric_fpga_rdata_axi_m2_o64, fabric_fpga_rdata_axi_m2_o65, fabric_fpga_rdata_axi_m2_o66, fabric_fpga_rdata_axi_m2_o67, fabric_fpga_rdata_axi_m2_o68, fabric_fpga_rdata_axi_m2_o69, fabric_fpga_rdata_axi_m2_o70, fabric_fpga_rdata_axi_m2_o71, fabric_fpga_rdata_axi_m2_o72, fabric_fpga_rdata_axi_m2_o73, fabric_fpga_rdata_axi_m2_o74, fabric_fpga_rdata_axi_m2_o75, fabric_fpga_rdata_axi_m2_o76, fabric_fpga_rdata_axi_m2_o77
-, fabric_fpga_rdata_axi_m2_o78, fabric_fpga_rdata_axi_m2_o79, fabric_fpga_rdata_axi_m2_o80, fabric_fpga_rdata_axi_m2_o81, fabric_fpga_rdata_axi_m2_o82, fabric_fpga_rdata_axi_m2_o83, fabric_fpga_rdata_axi_m2_o84, fabric_fpga_rdata_axi_m2_o85, fabric_fpga_rdata_axi_m2_o86, fabric_fpga_rdata_axi_m2_o87, fabric_fpga_rdata_axi_m2_o88, fabric_fpga_rdata_axi_m2_o89, fabric_fpga_rdata_axi_m2_o90, fabric_fpga_rdata_axi_m2_o91, fabric_fpga_rdata_axi_m2_o92, fabric_fpga_rdata_axi_m2_o93, fabric_fpga_rdata_axi_m2_o94, fabric_fpga_rdata_axi_m2_o95, fabric_fpga_rdata_axi_m2_o96, fabric_fpga_rdata_axi_m2_o97, fabric_fpga_rdata_axi_m2_o98
-, fabric_fpga_rdata_axi_m2_o99, fabric_fpga_rdata_axi_m2_o100, fabric_fpga_rdata_axi_m2_o101, fabric_fpga_rdata_axi_m2_o102, fabric_fpga_rdata_axi_m2_o103, fabric_fpga_rdata_axi_m2_o104, fabric_fpga_rdata_axi_m2_o105, fabric_fpga_rdata_axi_m2_o106, fabric_fpga_rdata_axi_m2_o107, fabric_fpga_rdata_axi_m2_o108, fabric_fpga_rdata_axi_m2_o109, fabric_fpga_rdata_axi_m2_o110, fabric_fpga_rdata_axi_m2_o111, fabric_fpga_rdata_axi_m2_o112, fabric_fpga_rdata_axi_m2_o113, fabric_fpga_rdata_axi_m2_o114, fabric_fpga_rdata_axi_m2_o115, fabric_fpga_rdata_axi_m2_o116, fabric_fpga_rdata_axi_m2_o117, fabric_fpga_rdata_axi_m2_o118, fabric_fpga_rdata_axi_m2_o119
-, fabric_fpga_rdata_axi_m2_o120, fabric_fpga_rdata_axi_m2_o121, fabric_fpga_rdata_axi_m2_o122, fabric_fpga_rdata_axi_m2_o123, fabric_fpga_rdata_axi_m2_o124, fabric_fpga_rdata_axi_m2_o125, fabric_fpga_rdata_axi_m2_o126, fabric_fpga_rdata_axi_m2_o127, fabric_fpga_rdata_axi_m2_o128, fabric_fpga_rid_axi_m2_o1, fabric_fpga_rid_axi_m2_o2, fabric_fpga_rid_axi_m2_o3, fabric_fpga_rid_axi_m2_o4, fabric_fpga_rid_axi_m2_o5, fabric_fpga_rlast_axi_m2_o, fabric_fpga_rresp_axi_m2_o1, fabric_fpga_rresp_axi_m2_o2, fabric_fpga_rvalid_axi_m2_o, fabric_fpga_wready_axi_m2_o, fabric_fpga_araddr_axi_m2_i1, fabric_fpga_araddr_axi_m2_i2
-, fabric_fpga_araddr_axi_m2_i3, fabric_fpga_araddr_axi_m2_i4, fabric_fpga_araddr_axi_m2_i5, fabric_fpga_araddr_axi_m2_i6, fabric_fpga_araddr_axi_m2_i7, fabric_fpga_araddr_axi_m2_i8, fabric_fpga_araddr_axi_m2_i9, fabric_fpga_araddr_axi_m2_i10, fabric_fpga_araddr_axi_m2_i11, fabric_fpga_araddr_axi_m2_i12, fabric_fpga_araddr_axi_m2_i13, fabric_fpga_araddr_axi_m2_i14, fabric_fpga_araddr_axi_m2_i15, fabric_fpga_araddr_axi_m2_i16, fabric_fpga_araddr_axi_m2_i17, fabric_fpga_araddr_axi_m2_i18, fabric_fpga_araddr_axi_m2_i19, fabric_fpga_araddr_axi_m2_i20, fabric_fpga_araddr_axi_m2_i21, fabric_fpga_araddr_axi_m2_i22, fabric_fpga_araddr_axi_m2_i23
-, fabric_fpga_araddr_axi_m2_i24, fabric_fpga_araddr_axi_m2_i25, fabric_fpga_araddr_axi_m2_i26, fabric_fpga_araddr_axi_m2_i27, fabric_fpga_araddr_axi_m2_i28, fabric_fpga_araddr_axi_m2_i29, fabric_fpga_araddr_axi_m2_i30, fabric_fpga_araddr_axi_m2_i31, fabric_fpga_araddr_axi_m2_i32, fabric_fpga_araddr_axi_m2_i33, fabric_fpga_araddr_axi_m2_i34, fabric_fpga_araddr_axi_m2_i35, fabric_fpga_araddr_axi_m2_i36, fabric_fpga_araddr_axi_m2_i37, fabric_fpga_araddr_axi_m2_i38, fabric_fpga_araddr_axi_m2_i39, fabric_fpga_araddr_axi_m2_i40, fabric_fpga_arburst_axi_m2_i1, fabric_fpga_arburst_axi_m2_i2, fabric_fpga_arcache_axi_m2_i1, fabric_fpga_arcache_axi_m2_i2
-, fabric_fpga_arcache_axi_m2_i3, fabric_fpga_arcache_axi_m2_i4, fabric_fpga_arid_axi_m2_i1, fabric_fpga_arid_axi_m2_i2, fabric_fpga_arid_axi_m2_i3, fabric_fpga_arid_axi_m2_i4, fabric_fpga_arid_axi_m2_i5, fabric_fpga_arlen_axi_m2_i1, fabric_fpga_arlen_axi_m2_i2, fabric_fpga_arlen_axi_m2_i3, fabric_fpga_arlen_axi_m2_i4, fabric_fpga_arlen_axi_m2_i5, fabric_fpga_arlen_axi_m2_i6, fabric_fpga_arlen_axi_m2_i7, fabric_fpga_arlen_axi_m2_i8, fabric_fpga_arlock_axi_m2_i, fabric_fpga_arprot_axi_m2_i1, fabric_fpga_arprot_axi_m2_i2, fabric_fpga_arprot_axi_m2_i3, fabric_fpga_arqos_axi_m2_i1, fabric_fpga_arqos_axi_m2_i2
-, fabric_fpga_arqos_axi_m2_i3, fabric_fpga_arqos_axi_m2_i4, fabric_fpga_arsize_axi_m2_i1, fabric_fpga_arsize_axi_m2_i2, fabric_fpga_arsize_axi_m2_i3, fabric_fpga_arvalid_axi_m2_i, fabric_fpga_awaddr_axi_m2_i1, fabric_fpga_awaddr_axi_m2_i2, fabric_fpga_awaddr_axi_m2_i3, fabric_fpga_awaddr_axi_m2_i4, fabric_fpga_awaddr_axi_m2_i5, fabric_fpga_awaddr_axi_m2_i6, fabric_fpga_awaddr_axi_m2_i7, fabric_fpga_awaddr_axi_m2_i8, fabric_fpga_awaddr_axi_m2_i9, fabric_fpga_awaddr_axi_m2_i10, fabric_fpga_awaddr_axi_m2_i11, fabric_fpga_awaddr_axi_m2_i12, fabric_fpga_awaddr_axi_m2_i13, fabric_fpga_awaddr_axi_m2_i14, fabric_fpga_awaddr_axi_m2_i15
-, fabric_fpga_awaddr_axi_m2_i16, fabric_fpga_awaddr_axi_m2_i17, fabric_fpga_awaddr_axi_m2_i18, fabric_fpga_awaddr_axi_m2_i19, fabric_fpga_awaddr_axi_m2_i20, fabric_fpga_awaddr_axi_m2_i21, fabric_fpga_awaddr_axi_m2_i22, fabric_fpga_awaddr_axi_m2_i23, fabric_fpga_awaddr_axi_m2_i24, fabric_fpga_awaddr_axi_m2_i25, fabric_fpga_awaddr_axi_m2_i26, fabric_fpga_awaddr_axi_m2_i27, fabric_fpga_awaddr_axi_m2_i28, fabric_fpga_awaddr_axi_m2_i29, fabric_fpga_awaddr_axi_m2_i30, fabric_fpga_awaddr_axi_m2_i31, fabric_fpga_awaddr_axi_m2_i32, fabric_fpga_awaddr_axi_m2_i33, fabric_fpga_awaddr_axi_m2_i34, fabric_fpga_awaddr_axi_m2_i35, fabric_fpga_awaddr_axi_m2_i36
-, fabric_fpga_awaddr_axi_m2_i37, fabric_fpga_awaddr_axi_m2_i38, fabric_fpga_awaddr_axi_m2_i39, fabric_fpga_awaddr_axi_m2_i40, fabric_fpga_awburst_axi_m2_i1, fabric_fpga_awburst_axi_m2_i2, fabric_fpga_awcache_axi_m2_i1, fabric_fpga_awcache_axi_m2_i2, fabric_fpga_awcache_axi_m2_i3, fabric_fpga_awcache_axi_m2_i4, fabric_fpga_awid_axi_m2_i1, fabric_fpga_awid_axi_m2_i2, fabric_fpga_awid_axi_m2_i3, fabric_fpga_awid_axi_m2_i4, fabric_fpga_awid_axi_m2_i5, fabric_fpga_awlen_axi_m2_i1, fabric_fpga_awlen_axi_m2_i2, fabric_fpga_awlen_axi_m2_i3, fabric_fpga_awlen_axi_m2_i4, fabric_fpga_awlen_axi_m2_i5, fabric_fpga_awlen_axi_m2_i6
-, fabric_fpga_awlen_axi_m2_i7, fabric_fpga_awlen_axi_m2_i8, fabric_fpga_awlock_axi_m2_i, fabric_fpga_awprot_axi_m2_i1, fabric_fpga_awprot_axi_m2_i2, fabric_fpga_awprot_axi_m2_i3, fabric_fpga_awqos_axi_m2_i1, fabric_fpga_awqos_axi_m2_i2, fabric_fpga_awqos_axi_m2_i3, fabric_fpga_awqos_axi_m2_i4, fabric_fpga_awsize_axi_m2_i1, fabric_fpga_awsize_axi_m2_i2, fabric_fpga_awsize_axi_m2_i3, fabric_fpga_awvalid_axi_m2_i, fabric_fpga_bready_axi_m2_i, fabric_fpga_dma_last_m2_i1, fabric_fpga_dma_last_m2_i2, fabric_fpga_dma_last_m2_i3, fabric_fpga_dma_last_m2_i4, fabric_fpga_dma_last_m2_i5, fabric_fpga_dma_last_m2_i6
-, fabric_fpga_dma_req_m2_i1, fabric_fpga_dma_req_m2_i2, fabric_fpga_dma_req_m2_i3, fabric_fpga_dma_req_m2_i4, fabric_fpga_dma_req_m2_i5, fabric_fpga_dma_req_m2_i6, fabric_fpga_dma_single_m2_i1, fabric_fpga_dma_single_m2_i2, fabric_fpga_dma_single_m2_i3, fabric_fpga_dma_single_m2_i4, fabric_fpga_dma_single_m2_i5, fabric_fpga_dma_single_m2_i6, fabric_fpga_rready_axi_m2_i, fabric_fpga_wdata_axi_m2_i1, fabric_fpga_wdata_axi_m2_i2, fabric_fpga_wdata_axi_m2_i3, fabric_fpga_wdata_axi_m2_i4, fabric_fpga_wdata_axi_m2_i5, fabric_fpga_wdata_axi_m2_i6, fabric_fpga_wdata_axi_m2_i7, fabric_fpga_wdata_axi_m2_i8
-, fabric_fpga_wdata_axi_m2_i9, fabric_fpga_wdata_axi_m2_i10, fabric_fpga_wdata_axi_m2_i11, fabric_fpga_wdata_axi_m2_i12, fabric_fpga_wdata_axi_m2_i13, fabric_fpga_wdata_axi_m2_i14, fabric_fpga_wdata_axi_m2_i15, fabric_fpga_wdata_axi_m2_i16, fabric_fpga_wdata_axi_m2_i17, fabric_fpga_wdata_axi_m2_i18, fabric_fpga_wdata_axi_m2_i19, fabric_fpga_wdata_axi_m2_i20, fabric_fpga_wdata_axi_m2_i21, fabric_fpga_wdata_axi_m2_i22, fabric_fpga_wdata_axi_m2_i23, fabric_fpga_wdata_axi_m2_i24, fabric_fpga_wdata_axi_m2_i25, fabric_fpga_wdata_axi_m2_i26, fabric_fpga_wdata_axi_m2_i27, fabric_fpga_wdata_axi_m2_i28, fabric_fpga_wdata_axi_m2_i29
-, fabric_fpga_wdata_axi_m2_i30, fabric_fpga_wdata_axi_m2_i31, fabric_fpga_wdata_axi_m2_i32, fabric_fpga_wdata_axi_m2_i33, fabric_fpga_wdata_axi_m2_i34, fabric_fpga_wdata_axi_m2_i35, fabric_fpga_wdata_axi_m2_i36, fabric_fpga_wdata_axi_m2_i37, fabric_fpga_wdata_axi_m2_i38, fabric_fpga_wdata_axi_m2_i39, fabric_fpga_wdata_axi_m2_i40, fabric_fpga_wdata_axi_m2_i41, fabric_fpga_wdata_axi_m2_i42, fabric_fpga_wdata_axi_m2_i43, fabric_fpga_wdata_axi_m2_i44, fabric_fpga_wdata_axi_m2_i45, fabric_fpga_wdata_axi_m2_i46, fabric_fpga_wdata_axi_m2_i47, fabric_fpga_wdata_axi_m2_i48, fabric_fpga_wdata_axi_m2_i49, fabric_fpga_wdata_axi_m2_i50
-, fabric_fpga_wdata_axi_m2_i51, fabric_fpga_wdata_axi_m2_i52, fabric_fpga_wdata_axi_m2_i53, fabric_fpga_wdata_axi_m2_i54, fabric_fpga_wdata_axi_m2_i55, fabric_fpga_wdata_axi_m2_i56, fabric_fpga_wdata_axi_m2_i57, fabric_fpga_wdata_axi_m2_i58, fabric_fpga_wdata_axi_m2_i59, fabric_fpga_wdata_axi_m2_i60, fabric_fpga_wdata_axi_m2_i61, fabric_fpga_wdata_axi_m2_i62, fabric_fpga_wdata_axi_m2_i63, fabric_fpga_wdata_axi_m2_i64, fabric_fpga_wdata_axi_m2_i65, fabric_fpga_wdata_axi_m2_i66, fabric_fpga_wdata_axi_m2_i67, fabric_fpga_wdata_axi_m2_i68, fabric_fpga_wdata_axi_m2_i69, fabric_fpga_wdata_axi_m2_i70, fabric_fpga_wdata_axi_m2_i71
-, fabric_fpga_wdata_axi_m2_i72, fabric_fpga_wdata_axi_m2_i73, fabric_fpga_wdata_axi_m2_i74, fabric_fpga_wdata_axi_m2_i75, fabric_fpga_wdata_axi_m2_i76, fabric_fpga_wdata_axi_m2_i77, fabric_fpga_wdata_axi_m2_i78, fabric_fpga_wdata_axi_m2_i79, fabric_fpga_wdata_axi_m2_i80, fabric_fpga_wdata_axi_m2_i81, fabric_fpga_wdata_axi_m2_i82, fabric_fpga_wdata_axi_m2_i83, fabric_fpga_wdata_axi_m2_i84, fabric_fpga_wdata_axi_m2_i85, fabric_fpga_wdata_axi_m2_i86, fabric_fpga_wdata_axi_m2_i87, fabric_fpga_wdata_axi_m2_i88, fabric_fpga_wdata_axi_m2_i89, fabric_fpga_wdata_axi_m2_i90, fabric_fpga_wdata_axi_m2_i91, fabric_fpga_wdata_axi_m2_i92
-, fabric_fpga_wdata_axi_m2_i93, fabric_fpga_wdata_axi_m2_i94, fabric_fpga_wdata_axi_m2_i95, fabric_fpga_wdata_axi_m2_i96, fabric_fpga_wdata_axi_m2_i97, fabric_fpga_wdata_axi_m2_i98, fabric_fpga_wdata_axi_m2_i99, fabric_fpga_wdata_axi_m2_i100, fabric_fpga_wdata_axi_m2_i101, fabric_fpga_wdata_axi_m2_i102, fabric_fpga_wdata_axi_m2_i103, fabric_fpga_wdata_axi_m2_i104, fabric_fpga_wdata_axi_m2_i105, fabric_fpga_wdata_axi_m2_i106, fabric_fpga_wdata_axi_m2_i107, fabric_fpga_wdata_axi_m2_i108, fabric_fpga_wdata_axi_m2_i109, fabric_fpga_wdata_axi_m2_i110, fabric_fpga_wdata_axi_m2_i111, fabric_fpga_wdata_axi_m2_i112, fabric_fpga_wdata_axi_m2_i113
-, fabric_fpga_wdata_axi_m2_i114, fabric_fpga_wdata_axi_m2_i115, fabric_fpga_wdata_axi_m2_i116, fabric_fpga_wdata_axi_m2_i117, fabric_fpga_wdata_axi_m2_i118, fabric_fpga_wdata_axi_m2_i119, fabric_fpga_wdata_axi_m2_i120, fabric_fpga_wdata_axi_m2_i121, fabric_fpga_wdata_axi_m2_i122, fabric_fpga_wdata_axi_m2_i123, fabric_fpga_wdata_axi_m2_i124, fabric_fpga_wdata_axi_m2_i125, fabric_fpga_wdata_axi_m2_i126, fabric_fpga_wdata_axi_m2_i127, fabric_fpga_wdata_axi_m2_i128, fabric_fpga_wlast_axi_m2_i, fabric_fpga_wstrb_axi_m2_i1, fabric_fpga_wstrb_axi_m2_i2, fabric_fpga_wstrb_axi_m2_i3, fabric_fpga_wstrb_axi_m2_i4, fabric_fpga_wstrb_axi_m2_i5
-, fabric_fpga_wstrb_axi_m2_i6, fabric_fpga_wstrb_axi_m2_i7, fabric_fpga_wstrb_axi_m2_i8, fabric_fpga_wstrb_axi_m2_i9, fabric_fpga_wstrb_axi_m2_i10, fabric_fpga_wstrb_axi_m2_i11, fabric_fpga_wstrb_axi_m2_i12, fabric_fpga_wstrb_axi_m2_i13, fabric_fpga_wstrb_axi_m2_i14, fabric_fpga_wstrb_axi_m2_i15, fabric_fpga_wstrb_axi_m2_i16, fabric_fpga_wvalid_axi_m2_i, fabric_fpga_ddr0_arready_o, fabric_fpga_ddr0_awready_o, fabric_fpga_ddr0_bid_o1, fabric_fpga_ddr0_bid_o2, fabric_fpga_ddr0_bid_o3, fabric_fpga_ddr0_bid_o4, fabric_fpga_ddr0_bid_o5, fabric_fpga_ddr0_bresp_o1, fabric_fpga_ddr0_bresp_o2
-, fabric_fpga_ddr0_bvalid_o, fabric_fpga_ddr0_rdata_o1, fabric_fpga_ddr0_rdata_o2, fabric_fpga_ddr0_rdata_o3, fabric_fpga_ddr0_rdata_o4, fabric_fpga_ddr0_rdata_o5, fabric_fpga_ddr0_rdata_o6, fabric_fpga_ddr0_rdata_o7, fabric_fpga_ddr0_rdata_o8, fabric_fpga_ddr0_rdata_o9, fabric_fpga_ddr0_rdata_o10, fabric_fpga_ddr0_rdata_o11, fabric_fpga_ddr0_rdata_o12, fabric_fpga_ddr0_rdata_o13, fabric_fpga_ddr0_rdata_o14, fabric_fpga_ddr0_rdata_o15, fabric_fpga_ddr0_rdata_o16, fabric_fpga_ddr0_rdata_o17, fabric_fpga_ddr0_rdata_o18, fabric_fpga_ddr0_rdata_o19, fabric_fpga_ddr0_rdata_o20
-, fabric_fpga_ddr0_rdata_o21, fabric_fpga_ddr0_rdata_o22, fabric_fpga_ddr0_rdata_o23, fabric_fpga_ddr0_rdata_o24, fabric_fpga_ddr0_rdata_o25, fabric_fpga_ddr0_rdata_o26, fabric_fpga_ddr0_rdata_o27, fabric_fpga_ddr0_rdata_o28, fabric_fpga_ddr0_rdata_o29, fabric_fpga_ddr0_rdata_o30, fabric_fpga_ddr0_rdata_o31, fabric_fpga_ddr0_rdata_o32, fabric_fpga_ddr0_rdata_o33, fabric_fpga_ddr0_rdata_o34, fabric_fpga_ddr0_rdata_o35, fabric_fpga_ddr0_rdata_o36, fabric_fpga_ddr0_rdata_o37, fabric_fpga_ddr0_rdata_o38, fabric_fpga_ddr0_rdata_o39, fabric_fpga_ddr0_rdata_o40, fabric_fpga_ddr0_rdata_o41
-, fabric_fpga_ddr0_rdata_o42, fabric_fpga_ddr0_rdata_o43, fabric_fpga_ddr0_rdata_o44, fabric_fpga_ddr0_rdata_o45, fabric_fpga_ddr0_rdata_o46, fabric_fpga_ddr0_rdata_o47, fabric_fpga_ddr0_rdata_o48, fabric_fpga_ddr0_rdata_o49, fabric_fpga_ddr0_rdata_o50, fabric_fpga_ddr0_rdata_o51, fabric_fpga_ddr0_rdata_o52, fabric_fpga_ddr0_rdata_o53, fabric_fpga_ddr0_rdata_o54, fabric_fpga_ddr0_rdata_o55, fabric_fpga_ddr0_rdata_o56, fabric_fpga_ddr0_rdata_o57, fabric_fpga_ddr0_rdata_o58, fabric_fpga_ddr0_rdata_o59, fabric_fpga_ddr0_rdata_o60, fabric_fpga_ddr0_rdata_o61, fabric_fpga_ddr0_rdata_o62
-, fabric_fpga_ddr0_rdata_o63, fabric_fpga_ddr0_rdata_o64, fabric_fpga_ddr0_rdata_o65, fabric_fpga_ddr0_rdata_o66, fabric_fpga_ddr0_rdata_o67, fabric_fpga_ddr0_rdata_o68, fabric_fpga_ddr0_rdata_o69, fabric_fpga_ddr0_rdata_o70, fabric_fpga_ddr0_rdata_o71, fabric_fpga_ddr0_rdata_o72, fabric_fpga_ddr0_rdata_o73, fabric_fpga_ddr0_rdata_o74, fabric_fpga_ddr0_rdata_o75, fabric_fpga_ddr0_rdata_o76, fabric_fpga_ddr0_rdata_o77, fabric_fpga_ddr0_rdata_o78, fabric_fpga_ddr0_rdata_o79, fabric_fpga_ddr0_rdata_o80, fabric_fpga_ddr0_rdata_o81, fabric_fpga_ddr0_rdata_o82, fabric_fpga_ddr0_rdata_o83
-, fabric_fpga_ddr0_rdata_o84, fabric_fpga_ddr0_rdata_o85, fabric_fpga_ddr0_rdata_o86, fabric_fpga_ddr0_rdata_o87, fabric_fpga_ddr0_rdata_o88, fabric_fpga_ddr0_rdata_o89, fabric_fpga_ddr0_rdata_o90, fabric_fpga_ddr0_rdata_o91, fabric_fpga_ddr0_rdata_o92, fabric_fpga_ddr0_rdata_o93, fabric_fpga_ddr0_rdata_o94, fabric_fpga_ddr0_rdata_o95, fabric_fpga_ddr0_rdata_o96, fabric_fpga_ddr0_rdata_o97, fabric_fpga_ddr0_rdata_o98, fabric_fpga_ddr0_rdata_o99, fabric_fpga_ddr0_rdata_o100, fabric_fpga_ddr0_rdata_o101, fabric_fpga_ddr0_rdata_o102, fabric_fpga_ddr0_rdata_o103, fabric_fpga_ddr0_rdata_o104
-, fabric_fpga_ddr0_rdata_o105, fabric_fpga_ddr0_rdata_o106, fabric_fpga_ddr0_rdata_o107, fabric_fpga_ddr0_rdata_o108, fabric_fpga_ddr0_rdata_o109, fabric_fpga_ddr0_rdata_o110, fabric_fpga_ddr0_rdata_o111, fabric_fpga_ddr0_rdata_o112, fabric_fpga_ddr0_rdata_o113, fabric_fpga_ddr0_rdata_o114, fabric_fpga_ddr0_rdata_o115, fabric_fpga_ddr0_rdata_o116, fabric_fpga_ddr0_rdata_o117, fabric_fpga_ddr0_rdata_o118, fabric_fpga_ddr0_rdata_o119, fabric_fpga_ddr0_rdata_o120, fabric_fpga_ddr0_rdata_o121, fabric_fpga_ddr0_rdata_o122, fabric_fpga_ddr0_rdata_o123, fabric_fpga_ddr0_rdata_o124, fabric_fpga_ddr0_rdata_o125
-, fabric_fpga_ddr0_rdata_o126, fabric_fpga_ddr0_rdata_o127, fabric_fpga_ddr0_rdata_o128, fabric_fpga_ddr0_rid_o1, fabric_fpga_ddr0_rid_o2, fabric_fpga_ddr0_rid_o3, fabric_fpga_ddr0_rid_o4, fabric_fpga_ddr0_rid_o5, fabric_fpga_ddr0_rlast_o, fabric_fpga_ddr0_rresp_o1, fabric_fpga_ddr0_rresp_o2, fabric_fpga_ddr0_rvalid_o, fabric_fpga_ddr0_wready_o, fabric_fpga_ddr0_araddr_i1, fabric_fpga_ddr0_araddr_i2, fabric_fpga_ddr0_araddr_i3, fabric_fpga_ddr0_araddr_i4, fabric_fpga_ddr0_araddr_i5, fabric_fpga_ddr0_araddr_i6, fabric_fpga_ddr0_araddr_i7, fabric_fpga_ddr0_araddr_i8
-, fabric_fpga_ddr0_araddr_i9, fabric_fpga_ddr0_araddr_i10, fabric_fpga_ddr0_araddr_i11, fabric_fpga_ddr0_araddr_i12, fabric_fpga_ddr0_araddr_i13, fabric_fpga_ddr0_araddr_i14, fabric_fpga_ddr0_araddr_i15, fabric_fpga_ddr0_araddr_i16, fabric_fpga_ddr0_araddr_i17, fabric_fpga_ddr0_araddr_i18, fabric_fpga_ddr0_araddr_i19, fabric_fpga_ddr0_araddr_i20, fabric_fpga_ddr0_araddr_i21, fabric_fpga_ddr0_araddr_i22, fabric_fpga_ddr0_araddr_i23, fabric_fpga_ddr0_araddr_i24, fabric_fpga_ddr0_araddr_i25, fabric_fpga_ddr0_araddr_i26, fabric_fpga_ddr0_araddr_i27, fabric_fpga_ddr0_araddr_i28, fabric_fpga_ddr0_araddr_i29
-, fabric_fpga_ddr0_araddr_i30, fabric_fpga_ddr0_araddr_i31, fabric_fpga_ddr0_araddr_i32, fabric_fpga_ddr0_araddr_i33, fabric_fpga_ddr0_araddr_i34, fabric_fpga_ddr0_araddr_i35, fabric_fpga_ddr0_araddr_i36, fabric_fpga_ddr0_araddr_i37, fabric_fpga_ddr0_araddr_i38, fabric_fpga_ddr0_araddr_i39, fabric_fpga_ddr0_araddr_i40, fabric_fpga_ddr0_arburst_i1, fabric_fpga_ddr0_arburst_i2, fabric_fpga_ddr0_arcache_i1, fabric_fpga_ddr0_arcache_i2, fabric_fpga_ddr0_arcache_i3, fabric_fpga_ddr0_arcache_i4, fabric_fpga_ddr0_arid_i1, fabric_fpga_ddr0_arid_i2, fabric_fpga_ddr0_arid_i3, fabric_fpga_ddr0_arid_i4
-, fabric_fpga_ddr0_arid_i5, fabric_fpga_ddr0_arlen_i1, fabric_fpga_ddr0_arlen_i2, fabric_fpga_ddr0_arlen_i3, fabric_fpga_ddr0_arlen_i4, fabric_fpga_ddr0_arlen_i5, fabric_fpga_ddr0_arlen_i6, fabric_fpga_ddr0_arlen_i7, fabric_fpga_ddr0_arlen_i8, fabric_fpga_ddr0_arlock_i, fabric_fpga_ddr0_arprot_i1, fabric_fpga_ddr0_arprot_i2, fabric_fpga_ddr0_arprot_i3, fabric_fpga_ddr0_arqos_i1, fabric_fpga_ddr0_arqos_i2, fabric_fpga_ddr0_arqos_i3, fabric_fpga_ddr0_arqos_i4, fabric_fpga_ddr0_arsize_i1, fabric_fpga_ddr0_arsize_i2, fabric_fpga_ddr0_arsize_i3, fabric_fpga_ddr0_arvalid_i
-, fabric_fpga_ddr0_awaddr_i1, fabric_fpga_ddr0_awaddr_i2, fabric_fpga_ddr0_awaddr_i3, fabric_fpga_ddr0_awaddr_i4, fabric_fpga_ddr0_awaddr_i5, fabric_fpga_ddr0_awaddr_i6, fabric_fpga_ddr0_awaddr_i7, fabric_fpga_ddr0_awaddr_i8, fabric_fpga_ddr0_awaddr_i9, fabric_fpga_ddr0_awaddr_i10, fabric_fpga_ddr0_awaddr_i11, fabric_fpga_ddr0_awaddr_i12, fabric_fpga_ddr0_awaddr_i13, fabric_fpga_ddr0_awaddr_i14, fabric_fpga_ddr0_awaddr_i15, fabric_fpga_ddr0_awaddr_i16, fabric_fpga_ddr0_awaddr_i17, fabric_fpga_ddr0_awaddr_i18, fabric_fpga_ddr0_awaddr_i19, fabric_fpga_ddr0_awaddr_i20, fabric_fpga_ddr0_awaddr_i21
-, fabric_fpga_ddr0_awaddr_i22, fabric_fpga_ddr0_awaddr_i23, fabric_fpga_ddr0_awaddr_i24, fabric_fpga_ddr0_awaddr_i25, fabric_fpga_ddr0_awaddr_i26, fabric_fpga_ddr0_awaddr_i27, fabric_fpga_ddr0_awaddr_i28, fabric_fpga_ddr0_awaddr_i29, fabric_fpga_ddr0_awaddr_i30, fabric_fpga_ddr0_awaddr_i31, fabric_fpga_ddr0_awaddr_i32, fabric_fpga_ddr0_awaddr_i33, fabric_fpga_ddr0_awaddr_i34, fabric_fpga_ddr0_awaddr_i35, fabric_fpga_ddr0_awaddr_i36, fabric_fpga_ddr0_awaddr_i37, fabric_fpga_ddr0_awaddr_i38, fabric_fpga_ddr0_awaddr_i39, fabric_fpga_ddr0_awaddr_i40, fabric_fpga_ddr0_awburst_i1, fabric_fpga_ddr0_awburst_i2
-, fabric_fpga_ddr0_awcache_i1, fabric_fpga_ddr0_awcache_i2, fabric_fpga_ddr0_awcache_i3, fabric_fpga_ddr0_awcache_i4, fabric_fpga_ddr0_awid_i1, fabric_fpga_ddr0_awid_i2, fabric_fpga_ddr0_awid_i3, fabric_fpga_ddr0_awid_i4, fabric_fpga_ddr0_awid_i5, fabric_fpga_ddr0_awlen_i1, fabric_fpga_ddr0_awlen_i2, fabric_fpga_ddr0_awlen_i3, fabric_fpga_ddr0_awlen_i4, fabric_fpga_ddr0_awlen_i5, fabric_fpga_ddr0_awlen_i6, fabric_fpga_ddr0_awlen_i7, fabric_fpga_ddr0_awlen_i8, fabric_fpga_ddr0_awlock_i, fabric_fpga_ddr0_awprot_i1, fabric_fpga_ddr0_awprot_i2, fabric_fpga_ddr0_awprot_i3
-, fabric_fpga_ddr0_awqos_i1, fabric_fpga_ddr0_awqos_i2, fabric_fpga_ddr0_awqos_i3, fabric_fpga_ddr0_awqos_i4, fabric_fpga_ddr0_awsize_i1, fabric_fpga_ddr0_awsize_i2, fabric_fpga_ddr0_awsize_i3, fabric_fpga_ddr0_awvalid_i, fabric_fpga_ddr0_bready_i, fabric_fpga_ddr0_rready_i, fabric_fpga_ddr0_wdata_i1, fabric_fpga_ddr0_wdata_i2, fabric_fpga_ddr0_wdata_i3, fabric_fpga_ddr0_wdata_i4, fabric_fpga_ddr0_wdata_i5, fabric_fpga_ddr0_wdata_i6, fabric_fpga_ddr0_wdata_i7, fabric_fpga_ddr0_wdata_i8, fabric_fpga_ddr0_wdata_i9, fabric_fpga_ddr0_wdata_i10, fabric_fpga_ddr0_wdata_i11
-, fabric_fpga_ddr0_wdata_i12, fabric_fpga_ddr0_wdata_i13, fabric_fpga_ddr0_wdata_i14, fabric_fpga_ddr0_wdata_i15, fabric_fpga_ddr0_wdata_i16, fabric_fpga_ddr0_wdata_i17, fabric_fpga_ddr0_wdata_i18, fabric_fpga_ddr0_wdata_i19, fabric_fpga_ddr0_wdata_i20, fabric_fpga_ddr0_wdata_i21, fabric_fpga_ddr0_wdata_i22, fabric_fpga_ddr0_wdata_i23, fabric_fpga_ddr0_wdata_i24, fabric_fpga_ddr0_wdata_i25, fabric_fpga_ddr0_wdata_i26, fabric_fpga_ddr0_wdata_i27, fabric_fpga_ddr0_wdata_i28, fabric_fpga_ddr0_wdata_i29, fabric_fpga_ddr0_wdata_i30, fabric_fpga_ddr0_wdata_i31, fabric_fpga_ddr0_wdata_i32
-, fabric_fpga_ddr0_wdata_i33, fabric_fpga_ddr0_wdata_i34, fabric_fpga_ddr0_wdata_i35, fabric_fpga_ddr0_wdata_i36, fabric_fpga_ddr0_wdata_i37, fabric_fpga_ddr0_wdata_i38, fabric_fpga_ddr0_wdata_i39, fabric_fpga_ddr0_wdata_i40, fabric_fpga_ddr0_wdata_i41, fabric_fpga_ddr0_wdata_i42, fabric_fpga_ddr0_wdata_i43, fabric_fpga_ddr0_wdata_i44, fabric_fpga_ddr0_wdata_i45, fabric_fpga_ddr0_wdata_i46, fabric_fpga_ddr0_wdata_i47, fabric_fpga_ddr0_wdata_i48, fabric_fpga_ddr0_wdata_i49, fabric_fpga_ddr0_wdata_i50, fabric_fpga_ddr0_wdata_i51, fabric_fpga_ddr0_wdata_i52, fabric_fpga_ddr0_wdata_i53
-, fabric_fpga_ddr0_wdata_i54, fabric_fpga_ddr0_wdata_i55, fabric_fpga_ddr0_wdata_i56, fabric_fpga_ddr0_wdata_i57, fabric_fpga_ddr0_wdata_i58, fabric_fpga_ddr0_wdata_i59, fabric_fpga_ddr0_wdata_i60, fabric_fpga_ddr0_wdata_i61, fabric_fpga_ddr0_wdata_i62, fabric_fpga_ddr0_wdata_i63, fabric_fpga_ddr0_wdata_i64, fabric_fpga_ddr0_wdata_i65, fabric_fpga_ddr0_wdata_i66, fabric_fpga_ddr0_wdata_i67, fabric_fpga_ddr0_wdata_i68, fabric_fpga_ddr0_wdata_i69, fabric_fpga_ddr0_wdata_i70, fabric_fpga_ddr0_wdata_i71, fabric_fpga_ddr0_wdata_i72, fabric_fpga_ddr0_wdata_i73, fabric_fpga_ddr0_wdata_i74
-, fabric_fpga_ddr0_wdata_i75, fabric_fpga_ddr0_wdata_i76, fabric_fpga_ddr0_wdata_i77, fabric_fpga_ddr0_wdata_i78, fabric_fpga_ddr0_wdata_i79, fabric_fpga_ddr0_wdata_i80, fabric_fpga_ddr0_wdata_i81, fabric_fpga_ddr0_wdata_i82, fabric_fpga_ddr0_wdata_i83, fabric_fpga_ddr0_wdata_i84, fabric_fpga_ddr0_wdata_i85, fabric_fpga_ddr0_wdata_i86, fabric_fpga_ddr0_wdata_i87, fabric_fpga_ddr0_wdata_i88, fabric_fpga_ddr0_wdata_i89, fabric_fpga_ddr0_wdata_i90, fabric_fpga_ddr0_wdata_i91, fabric_fpga_ddr0_wdata_i92, fabric_fpga_ddr0_wdata_i93, fabric_fpga_ddr0_wdata_i94, fabric_fpga_ddr0_wdata_i95
-, fabric_fpga_ddr0_wdata_i96, fabric_fpga_ddr0_wdata_i97, fabric_fpga_ddr0_wdata_i98, fabric_fpga_ddr0_wdata_i99, fabric_fpga_ddr0_wdata_i100, fabric_fpga_ddr0_wdata_i101, fabric_fpga_ddr0_wdata_i102, fabric_fpga_ddr0_wdata_i103, fabric_fpga_ddr0_wdata_i104, fabric_fpga_ddr0_wdata_i105, fabric_fpga_ddr0_wdata_i106, fabric_fpga_ddr0_wdata_i107, fabric_fpga_ddr0_wdata_i108, fabric_fpga_ddr0_wdata_i109, fabric_fpga_ddr0_wdata_i110, fabric_fpga_ddr0_wdata_i111, fabric_fpga_ddr0_wdata_i112, fabric_fpga_ddr0_wdata_i113, fabric_fpga_ddr0_wdata_i114, fabric_fpga_ddr0_wdata_i115, fabric_fpga_ddr0_wdata_i116
-, fabric_fpga_ddr0_wdata_i117, fabric_fpga_ddr0_wdata_i118, fabric_fpga_ddr0_wdata_i119, fabric_fpga_ddr0_wdata_i120, fabric_fpga_ddr0_wdata_i121, fabric_fpga_ddr0_wdata_i122, fabric_fpga_ddr0_wdata_i123, fabric_fpga_ddr0_wdata_i124, fabric_fpga_ddr0_wdata_i125, fabric_fpga_ddr0_wdata_i126, fabric_fpga_ddr0_wdata_i127, fabric_fpga_ddr0_wdata_i128, fabric_fpga_ddr0_wlast_i, fabric_fpga_ddr0_wstrb_i1, fabric_fpga_ddr0_wstrb_i2, fabric_fpga_ddr0_wstrb_i3, fabric_fpga_ddr0_wstrb_i4, fabric_fpga_ddr0_wstrb_i5, fabric_fpga_ddr0_wstrb_i6, fabric_fpga_ddr0_wstrb_i7, fabric_fpga_ddr0_wstrb_i8
-, fabric_fpga_ddr0_wstrb_i9, fabric_fpga_ddr0_wstrb_i10, fabric_fpga_ddr0_wstrb_i11, fabric_fpga_ddr0_wstrb_i12, fabric_fpga_ddr0_wstrb_i13, fabric_fpga_ddr0_wstrb_i14, fabric_fpga_ddr0_wstrb_i15, fabric_fpga_ddr0_wstrb_i16, fabric_fpga_ddr0_wvalid_i, fabric_fpga_paddr_apb_o1, fabric_fpga_paddr_apb_o2, fabric_fpga_paddr_apb_o3, fabric_fpga_paddr_apb_o4, fabric_fpga_paddr_apb_o5, fabric_fpga_paddr_apb_o6, fabric_fpga_paddr_apb_o7, fabric_fpga_paddr_apb_o8, fabric_fpga_paddr_apb_o9, fabric_fpga_paddr_apb_o10, fabric_fpga_paddr_apb_o11, fabric_fpga_paddr_apb_o12
-, fabric_fpga_paddr_apb_o13, fabric_fpga_paddr_apb_o14, fabric_fpga_paddr_apb_o15, fabric_fpga_paddr_apb_o16, fabric_fpga_paddr_apb_o17, fabric_fpga_paddr_apb_o18, fabric_fpga_paddr_apb_o19, fabric_fpga_paddr_apb_o20, fabric_fpga_paddr_apb_o21, fabric_fpga_paddr_apb_o22, fabric_fpga_paddr_apb_o23, fabric_fpga_paddr_apb_o24, fabric_fpga_paddr_apb_o25, fabric_fpga_paddr_apb_o26, fabric_fpga_paddr_apb_o27, fabric_fpga_paddr_apb_o28, fabric_fpga_paddr_apb_o29, fabric_fpga_paddr_apb_o30, fabric_fpga_paddr_apb_o31, fabric_fpga_paddr_apb_o32, fabric_fpga_penable_apb_o
-, fabric_fpga_psel_apb_o, fabric_fpga_pwdata_apb_o1, fabric_fpga_pwdata_apb_o2, fabric_fpga_pwdata_apb_o3, fabric_fpga_pwdata_apb_o4, fabric_fpga_pwdata_apb_o5, fabric_fpga_pwdata_apb_o6, fabric_fpga_pwdata_apb_o7, fabric_fpga_pwdata_apb_o8, fabric_fpga_pwdata_apb_o9, fabric_fpga_pwdata_apb_o10, fabric_fpga_pwdata_apb_o11, fabric_fpga_pwdata_apb_o12, fabric_fpga_pwdata_apb_o13, fabric_fpga_pwdata_apb_o14, fabric_fpga_pwdata_apb_o15, fabric_fpga_pwdata_apb_o16, fabric_fpga_pwdata_apb_o17, fabric_fpga_pwdata_apb_o18, fabric_fpga_pwdata_apb_o19, fabric_fpga_pwdata_apb_o20
-, fabric_fpga_pwdata_apb_o21, fabric_fpga_pwdata_apb_o22, fabric_fpga_pwdata_apb_o23, fabric_fpga_pwdata_apb_o24, fabric_fpga_pwdata_apb_o25, fabric_fpga_pwdata_apb_o26, fabric_fpga_pwdata_apb_o27, fabric_fpga_pwdata_apb_o28, fabric_fpga_pwdata_apb_o29, fabric_fpga_pwdata_apb_o30, fabric_fpga_pwdata_apb_o31, fabric_fpga_pwdata_apb_o32, fabric_fpga_pwrite_apb_o, fabric_fpga_prdata_apb_i1, fabric_fpga_prdata_apb_i2, fabric_fpga_prdata_apb_i3, fabric_fpga_prdata_apb_i4, fabric_fpga_prdata_apb_i5, fabric_fpga_prdata_apb_i6, fabric_fpga_prdata_apb_i7, fabric_fpga_prdata_apb_i8
-, fabric_fpga_prdata_apb_i9, fabric_fpga_prdata_apb_i10, fabric_fpga_prdata_apb_i11, fabric_fpga_prdata_apb_i12, fabric_fpga_prdata_apb_i13, fabric_fpga_prdata_apb_i14, fabric_fpga_prdata_apb_i15, fabric_fpga_prdata_apb_i16, fabric_fpga_prdata_apb_i17, fabric_fpga_prdata_apb_i18, fabric_fpga_prdata_apb_i19, fabric_fpga_prdata_apb_i20, fabric_fpga_prdata_apb_i21, fabric_fpga_prdata_apb_i22, fabric_fpga_prdata_apb_i23, fabric_fpga_prdata_apb_i24, fabric_fpga_prdata_apb_i25, fabric_fpga_prdata_apb_i26, fabric_fpga_prdata_apb_i27, fabric_fpga_prdata_apb_i28, fabric_fpga_prdata_apb_i29
-, fabric_fpga_prdata_apb_i30, fabric_fpga_prdata_apb_i31, fabric_fpga_prdata_apb_i32, fabric_fpga_pready_apb_i, fabric_fpga_pslverr_apb_i, fabric_llpp0_araddr_s_o1, fabric_llpp0_araddr_s_o2, fabric_llpp0_araddr_s_o3, fabric_llpp0_araddr_s_o4, fabric_llpp0_araddr_s_o5, fabric_llpp0_araddr_s_o6, fabric_llpp0_araddr_s_o7, fabric_llpp0_araddr_s_o8, fabric_llpp0_araddr_s_o9, fabric_llpp0_araddr_s_o10, fabric_llpp0_araddr_s_o11, fabric_llpp0_araddr_s_o12, fabric_llpp0_araddr_s_o13, fabric_llpp0_araddr_s_o14, fabric_llpp0_araddr_s_o15, fabric_llpp0_araddr_s_o16
-, fabric_llpp0_araddr_s_o17, fabric_llpp0_araddr_s_o18, fabric_llpp0_araddr_s_o19, fabric_llpp0_araddr_s_o20, fabric_llpp0_araddr_s_o21, fabric_llpp0_araddr_s_o22, fabric_llpp0_araddr_s_o23, fabric_llpp0_araddr_s_o24, fabric_llpp0_araddr_s_o25, fabric_llpp0_araddr_s_o26, fabric_llpp0_araddr_s_o27, fabric_llpp0_araddr_s_o28, fabric_llpp0_araddr_s_o29, fabric_llpp0_araddr_s_o30, fabric_llpp0_araddr_s_o31, fabric_llpp0_araddr_s_o32, fabric_llpp0_arburst_s_o1, fabric_llpp0_arburst_s_o2, fabric_llpp0_arcache_s_o1, fabric_llpp0_arcache_s_o2, fabric_llpp0_arcache_s_o3
-, fabric_llpp0_arcache_s_o4, fabric_llpp0_arid_s_o1, fabric_llpp0_arid_s_o2, fabric_llpp0_arid_s_o3, fabric_llpp0_arid_s_o4, fabric_llpp0_arid_s_o5, fabric_llpp0_arid_s_o6, fabric_llpp0_arid_s_o7, fabric_llpp0_arid_s_o8, fabric_llpp0_arid_s_o9, fabric_llpp0_arid_s_o10, fabric_llpp0_arid_s_o11, fabric_llpp0_arid_s_o12, fabric_llpp0_arlen_s_o1, fabric_llpp0_arlen_s_o2, fabric_llpp0_arlen_s_o3, fabric_llpp0_arlen_s_o4, fabric_llpp0_arlen_s_o5, fabric_llpp0_arlen_s_o6, fabric_llpp0_arlen_s_o7, fabric_llpp0_arlen_s_o8
-, fabric_llpp0_arlock_s_o, fabric_llpp0_arprot_s_o1, fabric_llpp0_arprot_s_o2, fabric_llpp0_arprot_s_o3, fabric_llpp0_arqos_s_o1, fabric_llpp0_arqos_s_o2, fabric_llpp0_arqos_s_o3, fabric_llpp0_arqos_s_o4, fabric_llpp0_arsize_s_o1, fabric_llpp0_arsize_s_o2, fabric_llpp0_arsize_s_o3, fabric_llpp0_arvalid_s_o, fabric_llpp0_awaddr_s_o1, fabric_llpp0_awaddr_s_o2, fabric_llpp0_awaddr_s_o3, fabric_llpp0_awaddr_s_o4, fabric_llpp0_awaddr_s_o5, fabric_llpp0_awaddr_s_o6, fabric_llpp0_awaddr_s_o7, fabric_llpp0_awaddr_s_o8, fabric_llpp0_awaddr_s_o9
-, fabric_llpp0_awaddr_s_o10, fabric_llpp0_awaddr_s_o11, fabric_llpp0_awaddr_s_o12, fabric_llpp0_awaddr_s_o13, fabric_llpp0_awaddr_s_o14, fabric_llpp0_awaddr_s_o15, fabric_llpp0_awaddr_s_o16, fabric_llpp0_awaddr_s_o17, fabric_llpp0_awaddr_s_o18, fabric_llpp0_awaddr_s_o19, fabric_llpp0_awaddr_s_o20, fabric_llpp0_awaddr_s_o21, fabric_llpp0_awaddr_s_o22, fabric_llpp0_awaddr_s_o23, fabric_llpp0_awaddr_s_o24, fabric_llpp0_awaddr_s_o25, fabric_llpp0_awaddr_s_o26, fabric_llpp0_awaddr_s_o27, fabric_llpp0_awaddr_s_o28, fabric_llpp0_awaddr_s_o29, fabric_llpp0_awaddr_s_o30
-, fabric_llpp0_awaddr_s_o31, fabric_llpp0_awaddr_s_o32, fabric_llpp0_awburst_s_o1, fabric_llpp0_awburst_s_o2, fabric_llpp0_awcache_s_o1, fabric_llpp0_awcache_s_o2, fabric_llpp0_awcache_s_o3, fabric_llpp0_awcache_s_o4, fabric_llpp0_awid_s_o1, fabric_llpp0_awid_s_o2, fabric_llpp0_awid_s_o3, fabric_llpp0_awid_s_o4, fabric_llpp0_awid_s_o5, fabric_llpp0_awid_s_o6, fabric_llpp0_awid_s_o7, fabric_llpp0_awid_s_o8, fabric_llpp0_awid_s_o9, fabric_llpp0_awid_s_o10, fabric_llpp0_awid_s_o11, fabric_llpp0_awid_s_o12, fabric_llpp0_awlen_s_o1
-, fabric_llpp0_awlen_s_o2, fabric_llpp0_awlen_s_o3, fabric_llpp0_awlen_s_o4, fabric_llpp0_awlen_s_o5, fabric_llpp0_awlen_s_o6, fabric_llpp0_awlen_s_o7, fabric_llpp0_awlen_s_o8, fabric_llpp0_awlock_s_o, fabric_llpp0_awprot_s_o1, fabric_llpp0_awprot_s_o2, fabric_llpp0_awprot_s_o3, fabric_llpp0_awqos_s_o1, fabric_llpp0_awqos_s_o2, fabric_llpp0_awqos_s_o3, fabric_llpp0_awqos_s_o4, fabric_llpp0_awsize_s_o1, fabric_llpp0_awsize_s_o2, fabric_llpp0_awsize_s_o3, fabric_llpp0_awvalid_s_o, fabric_llpp0_bready_s_o, fabric_llpp0_rready_s_o
-, fabric_llpp0_wdata_s_o1, fabric_llpp0_wdata_s_o2, fabric_llpp0_wdata_s_o3, fabric_llpp0_wdata_s_o4, fabric_llpp0_wdata_s_o5, fabric_llpp0_wdata_s_o6, fabric_llpp0_wdata_s_o7, fabric_llpp0_wdata_s_o8, fabric_llpp0_wdata_s_o9, fabric_llpp0_wdata_s_o10, fabric_llpp0_wdata_s_o11, fabric_llpp0_wdata_s_o12, fabric_llpp0_wdata_s_o13, fabric_llpp0_wdata_s_o14, fabric_llpp0_wdata_s_o15, fabric_llpp0_wdata_s_o16, fabric_llpp0_wdata_s_o17, fabric_llpp0_wdata_s_o18, fabric_llpp0_wdata_s_o19, fabric_llpp0_wdata_s_o20, fabric_llpp0_wdata_s_o21
-, fabric_llpp0_wdata_s_o22, fabric_llpp0_wdata_s_o23, fabric_llpp0_wdata_s_o24, fabric_llpp0_wdata_s_o25, fabric_llpp0_wdata_s_o26, fabric_llpp0_wdata_s_o27, fabric_llpp0_wdata_s_o28, fabric_llpp0_wdata_s_o29, fabric_llpp0_wdata_s_o30, fabric_llpp0_wdata_s_o31, fabric_llpp0_wdata_s_o32, fabric_llpp0_wlast_s_o, fabric_llpp0_wstrb_s_o1, fabric_llpp0_wstrb_s_o2, fabric_llpp0_wstrb_s_o3, fabric_llpp0_wstrb_s_o4, fabric_llpp0_wvalid_s_o, fabric_llpp0_arready_s_i, fabric_llpp0_awready_s_i, fabric_llpp0_bid_s_i1, fabric_llpp0_bid_s_i2
-, fabric_llpp0_bid_s_i3, fabric_llpp0_bid_s_i4, fabric_llpp0_bid_s_i5, fabric_llpp0_bid_s_i6, fabric_llpp0_bid_s_i7, fabric_llpp0_bid_s_i8, fabric_llpp0_bid_s_i9, fabric_llpp0_bid_s_i10, fabric_llpp0_bid_s_i11, fabric_llpp0_bid_s_i12, fabric_llpp0_bresp_s_i1, fabric_llpp0_bresp_s_i2, fabric_llpp0_bvalid_s_i, fabric_llpp0_rdata_s_i1, fabric_llpp0_rdata_s_i2, fabric_llpp0_rdata_s_i3, fabric_llpp0_rdata_s_i4, fabric_llpp0_rdata_s_i5, fabric_llpp0_rdata_s_i6, fabric_llpp0_rdata_s_i7, fabric_llpp0_rdata_s_i8
-, fabric_llpp0_rdata_s_i9, fabric_llpp0_rdata_s_i10, fabric_llpp0_rdata_s_i11, fabric_llpp0_rdata_s_i12, fabric_llpp0_rdata_s_i13, fabric_llpp0_rdata_s_i14, fabric_llpp0_rdata_s_i15, fabric_llpp0_rdata_s_i16, fabric_llpp0_rdata_s_i17, fabric_llpp0_rdata_s_i18, fabric_llpp0_rdata_s_i19, fabric_llpp0_rdata_s_i20, fabric_llpp0_rdata_s_i21, fabric_llpp0_rdata_s_i22, fabric_llpp0_rdata_s_i23, fabric_llpp0_rdata_s_i24, fabric_llpp0_rdata_s_i25, fabric_llpp0_rdata_s_i26, fabric_llpp0_rdata_s_i27, fabric_llpp0_rdata_s_i28, fabric_llpp0_rdata_s_i29
-, fabric_llpp0_rdata_s_i30, fabric_llpp0_rdata_s_i31, fabric_llpp0_rdata_s_i32, fabric_llpp0_rid_s_i1, fabric_llpp0_rid_s_i2, fabric_llpp0_rid_s_i3, fabric_llpp0_rid_s_i4, fabric_llpp0_rid_s_i5, fabric_llpp0_rid_s_i6, fabric_llpp0_rid_s_i7, fabric_llpp0_rid_s_i8, fabric_llpp0_rid_s_i9, fabric_llpp0_rid_s_i10, fabric_llpp0_rid_s_i11, fabric_llpp0_rid_s_i12, fabric_llpp0_rlast_s_i, fabric_llpp0_rresp_s_i1, fabric_llpp0_rresp_s_i2, fabric_llpp0_rvalid_s_i, fabric_llpp0_wready_s_i, fabric_llpp1_araddr_s_o1
-, fabric_llpp1_araddr_s_o2, fabric_llpp1_araddr_s_o3, fabric_llpp1_araddr_s_o4, fabric_llpp1_araddr_s_o5, fabric_llpp1_araddr_s_o6, fabric_llpp1_araddr_s_o7, fabric_llpp1_araddr_s_o8, fabric_llpp1_araddr_s_o9, fabric_llpp1_araddr_s_o10, fabric_llpp1_araddr_s_o11, fabric_llpp1_araddr_s_o12, fabric_llpp1_araddr_s_o13, fabric_llpp1_araddr_s_o14, fabric_llpp1_araddr_s_o15, fabric_llpp1_araddr_s_o16, fabric_llpp1_araddr_s_o17, fabric_llpp1_araddr_s_o18, fabric_llpp1_araddr_s_o19, fabric_llpp1_araddr_s_o20, fabric_llpp1_araddr_s_o21, fabric_llpp1_araddr_s_o22
-, fabric_llpp1_araddr_s_o23, fabric_llpp1_araddr_s_o24, fabric_llpp1_araddr_s_o25, fabric_llpp1_araddr_s_o26, fabric_llpp1_araddr_s_o27, fabric_llpp1_araddr_s_o28, fabric_llpp1_araddr_s_o29, fabric_llpp1_araddr_s_o30, fabric_llpp1_araddr_s_o31, fabric_llpp1_araddr_s_o32, fabric_llpp1_arburst_s_o1, fabric_llpp1_arburst_s_o2, fabric_llpp1_arcache_s_o1, fabric_llpp1_arcache_s_o2, fabric_llpp1_arcache_s_o3, fabric_llpp1_arcache_s_o4, fabric_llpp1_arid_s_o1, fabric_llpp1_arid_s_o2, fabric_llpp1_arid_s_o3, fabric_llpp1_arid_s_o4, fabric_llpp1_arid_s_o5
-, fabric_llpp1_arid_s_o6, fabric_llpp1_arid_s_o7, fabric_llpp1_arid_s_o8, fabric_llpp1_arid_s_o9, fabric_llpp1_arid_s_o10, fabric_llpp1_arid_s_o11, fabric_llpp1_arid_s_o12, fabric_llpp1_arlen_s_o1, fabric_llpp1_arlen_s_o2, fabric_llpp1_arlen_s_o3, fabric_llpp1_arlen_s_o4, fabric_llpp1_arlen_s_o5, fabric_llpp1_arlen_s_o6, fabric_llpp1_arlen_s_o7, fabric_llpp1_arlen_s_o8, fabric_llpp1_arlock_s_o, fabric_llpp1_arprot_s_o1, fabric_llpp1_arprot_s_o2, fabric_llpp1_arprot_s_o3, fabric_llpp1_arqos_s_o1, fabric_llpp1_arqos_s_o2
-, fabric_llpp1_arqos_s_o3, fabric_llpp1_arqos_s_o4, fabric_llpp1_arsize_s_o1, fabric_llpp1_arsize_s_o2, fabric_llpp1_arsize_s_o3, fabric_llpp1_arvalid_s_o, fabric_llpp1_awaddr_s_o1, fabric_llpp1_awaddr_s_o2, fabric_llpp1_awaddr_s_o3, fabric_llpp1_awaddr_s_o4, fabric_llpp1_awaddr_s_o5, fabric_llpp1_awaddr_s_o6, fabric_llpp1_awaddr_s_o7, fabric_llpp1_awaddr_s_o8, fabric_llpp1_awaddr_s_o9, fabric_llpp1_awaddr_s_o10, fabric_llpp1_awaddr_s_o11, fabric_llpp1_awaddr_s_o12, fabric_llpp1_awaddr_s_o13, fabric_llpp1_awaddr_s_o14, fabric_llpp1_awaddr_s_o15
-, fabric_llpp1_awaddr_s_o16, fabric_llpp1_awaddr_s_o17, fabric_llpp1_awaddr_s_o18, fabric_llpp1_awaddr_s_o19, fabric_llpp1_awaddr_s_o20, fabric_llpp1_awaddr_s_o21, fabric_llpp1_awaddr_s_o22, fabric_llpp1_awaddr_s_o23, fabric_llpp1_awaddr_s_o24, fabric_llpp1_awaddr_s_o25, fabric_llpp1_awaddr_s_o26, fabric_llpp1_awaddr_s_o27, fabric_llpp1_awaddr_s_o28, fabric_llpp1_awaddr_s_o29, fabric_llpp1_awaddr_s_o30, fabric_llpp1_awaddr_s_o31, fabric_llpp1_awaddr_s_o32, fabric_llpp1_awburst_s_o1, fabric_llpp1_awburst_s_o2, fabric_llpp1_awcache_s_o1, fabric_llpp1_awcache_s_o2
-, fabric_llpp1_awcache_s_o3, fabric_llpp1_awcache_s_o4, fabric_llpp1_awid_s_o1, fabric_llpp1_awid_s_o2, fabric_llpp1_awid_s_o3, fabric_llpp1_awid_s_o4, fabric_llpp1_awid_s_o5, fabric_llpp1_awid_s_o6, fabric_llpp1_awid_s_o7, fabric_llpp1_awid_s_o8, fabric_llpp1_awid_s_o9, fabric_llpp1_awid_s_o10, fabric_llpp1_awid_s_o11, fabric_llpp1_awid_s_o12, fabric_llpp1_awlen_s_o1, fabric_llpp1_awlen_s_o2, fabric_llpp1_awlen_s_o3, fabric_llpp1_awlen_s_o4, fabric_llpp1_awlen_s_o5, fabric_llpp1_awlen_s_o6, fabric_llpp1_awlen_s_o7
-, fabric_llpp1_awlen_s_o8, fabric_llpp1_awlock_s_o, fabric_llpp1_awprot_s_o1, fabric_llpp1_awprot_s_o2, fabric_llpp1_awprot_s_o3, fabric_llpp1_awqos_s_o1, fabric_llpp1_awqos_s_o2, fabric_llpp1_awqos_s_o3, fabric_llpp1_awqos_s_o4, fabric_llpp1_awsize_s_o1, fabric_llpp1_awsize_s_o2, fabric_llpp1_awsize_s_o3, fabric_llpp1_awvalid_s_o, fabric_llpp1_bready_s_o, fabric_llpp1_rready_s_o, fabric_llpp1_wdata_s_o1, fabric_llpp1_wdata_s_o2, fabric_llpp1_wdata_s_o3, fabric_llpp1_wdata_s_o4, fabric_llpp1_wdata_s_o5, fabric_llpp1_wdata_s_o6
-, fabric_llpp1_wdata_s_o7, fabric_llpp1_wdata_s_o8, fabric_llpp1_wdata_s_o9, fabric_llpp1_wdata_s_o10, fabric_llpp1_wdata_s_o11, fabric_llpp1_wdata_s_o12, fabric_llpp1_wdata_s_o13, fabric_llpp1_wdata_s_o14, fabric_llpp1_wdata_s_o15, fabric_llpp1_wdata_s_o16, fabric_llpp1_wdata_s_o17, fabric_llpp1_wdata_s_o18, fabric_llpp1_wdata_s_o19, fabric_llpp1_wdata_s_o20, fabric_llpp1_wdata_s_o21, fabric_llpp1_wdata_s_o22, fabric_llpp1_wdata_s_o23, fabric_llpp1_wdata_s_o24, fabric_llpp1_wdata_s_o25, fabric_llpp1_wdata_s_o26, fabric_llpp1_wdata_s_o27
-, fabric_llpp1_wdata_s_o28, fabric_llpp1_wdata_s_o29, fabric_llpp1_wdata_s_o30, fabric_llpp1_wdata_s_o31, fabric_llpp1_wdata_s_o32, fabric_llpp1_wlast_s_o, fabric_llpp1_wstrb_s_o1, fabric_llpp1_wstrb_s_o2, fabric_llpp1_wstrb_s_o3, fabric_llpp1_wstrb_s_o4, fabric_llpp1_wvalid_s_o, fabric_llpp1_arready_s_i, fabric_llpp1_awready_s_i, fabric_llpp1_bid_s_i1, fabric_llpp1_bid_s_i2, fabric_llpp1_bid_s_i3, fabric_llpp1_bid_s_i4, fabric_llpp1_bid_s_i5, fabric_llpp1_bid_s_i6, fabric_llpp1_bid_s_i7, fabric_llpp1_bid_s_i8
-, fabric_llpp1_bid_s_i9, fabric_llpp1_bid_s_i10, fabric_llpp1_bid_s_i11, fabric_llpp1_bid_s_i12, fabric_llpp1_bresp_s_i1, fabric_llpp1_bresp_s_i2, fabric_llpp1_bvalid_s_i, fabric_llpp1_rdata_s_i1, fabric_llpp1_rdata_s_i2, fabric_llpp1_rdata_s_i3, fabric_llpp1_rdata_s_i4, fabric_llpp1_rdata_s_i5, fabric_llpp1_rdata_s_i6, fabric_llpp1_rdata_s_i7, fabric_llpp1_rdata_s_i8, fabric_llpp1_rdata_s_i9, fabric_llpp1_rdata_s_i10, fabric_llpp1_rdata_s_i11, fabric_llpp1_rdata_s_i12, fabric_llpp1_rdata_s_i13, fabric_llpp1_rdata_s_i14
-, fabric_llpp1_rdata_s_i15, fabric_llpp1_rdata_s_i16, fabric_llpp1_rdata_s_i17, fabric_llpp1_rdata_s_i18, fabric_llpp1_rdata_s_i19, fabric_llpp1_rdata_s_i20, fabric_llpp1_rdata_s_i21, fabric_llpp1_rdata_s_i22, fabric_llpp1_rdata_s_i23, fabric_llpp1_rdata_s_i24, fabric_llpp1_rdata_s_i25, fabric_llpp1_rdata_s_i26, fabric_llpp1_rdata_s_i27, fabric_llpp1_rdata_s_i28, fabric_llpp1_rdata_s_i29, fabric_llpp1_rdata_s_i30, fabric_llpp1_rdata_s_i31, fabric_llpp1_rdata_s_i32, fabric_llpp1_rid_s_i1, fabric_llpp1_rid_s_i2, fabric_llpp1_rid_s_i3
-, fabric_llpp1_rid_s_i4, fabric_llpp1_rid_s_i5, fabric_llpp1_rid_s_i6, fabric_llpp1_rid_s_i7, fabric_llpp1_rid_s_i8, fabric_llpp1_rid_s_i9, fabric_llpp1_rid_s_i10, fabric_llpp1_rid_s_i11, fabric_llpp1_rid_s_i12, fabric_llpp1_rlast_s_i, fabric_llpp1_rresp_s_i1, fabric_llpp1_rresp_s_i2, fabric_llpp1_rvalid_s_i, fabric_llpp1_wready_s_i, fabric_llpp2_araddr_s_o1, fabric_llpp2_araddr_s_o2, fabric_llpp2_araddr_s_o3, fabric_llpp2_araddr_s_o4, fabric_llpp2_araddr_s_o5, fabric_llpp2_araddr_s_o6, fabric_llpp2_araddr_s_o7
-, fabric_llpp2_araddr_s_o8, fabric_llpp2_araddr_s_o9, fabric_llpp2_araddr_s_o10, fabric_llpp2_araddr_s_o11, fabric_llpp2_araddr_s_o12, fabric_llpp2_araddr_s_o13, fabric_llpp2_araddr_s_o14, fabric_llpp2_araddr_s_o15, fabric_llpp2_araddr_s_o16, fabric_llpp2_araddr_s_o17, fabric_llpp2_araddr_s_o18, fabric_llpp2_araddr_s_o19, fabric_llpp2_araddr_s_o20, fabric_llpp2_araddr_s_o21, fabric_llpp2_araddr_s_o22, fabric_llpp2_araddr_s_o23, fabric_llpp2_araddr_s_o24, fabric_llpp2_araddr_s_o25, fabric_llpp2_araddr_s_o26, fabric_llpp2_araddr_s_o27, fabric_llpp2_araddr_s_o28
-, fabric_llpp2_araddr_s_o29, fabric_llpp2_araddr_s_o30, fabric_llpp2_araddr_s_o31, fabric_llpp2_araddr_s_o32, fabric_llpp2_arburst_s_o1, fabric_llpp2_arburst_s_o2, fabric_llpp2_arcache_s_o1, fabric_llpp2_arcache_s_o2, fabric_llpp2_arcache_s_o3, fabric_llpp2_arcache_s_o4, fabric_llpp2_arid_s_o1, fabric_llpp2_arid_s_o2, fabric_llpp2_arid_s_o3, fabric_llpp2_arid_s_o4, fabric_llpp2_arid_s_o5, fabric_llpp2_arid_s_o6, fabric_llpp2_arid_s_o7, fabric_llpp2_arid_s_o8, fabric_llpp2_arid_s_o9, fabric_llpp2_arid_s_o10, fabric_llpp2_arid_s_o11
-, fabric_llpp2_arid_s_o12, fabric_llpp2_arlen_s_o1, fabric_llpp2_arlen_s_o2, fabric_llpp2_arlen_s_o3, fabric_llpp2_arlen_s_o4, fabric_llpp2_arlen_s_o5, fabric_llpp2_arlen_s_o6, fabric_llpp2_arlen_s_o7, fabric_llpp2_arlen_s_o8, fabric_llpp2_arlock_s_o, fabric_llpp2_arprot_s_o1, fabric_llpp2_arprot_s_o2, fabric_llpp2_arprot_s_o3, fabric_llpp2_arqos_s_o1, fabric_llpp2_arqos_s_o2, fabric_llpp2_arqos_s_o3, fabric_llpp2_arqos_s_o4, fabric_llpp2_arsize_s_o1, fabric_llpp2_arsize_s_o2, fabric_llpp2_arsize_s_o3, fabric_llpp2_arvalid_s_o
-, fabric_llpp2_awaddr_s_o1, fabric_llpp2_awaddr_s_o2, fabric_llpp2_awaddr_s_o3, fabric_llpp2_awaddr_s_o4, fabric_llpp2_awaddr_s_o5, fabric_llpp2_awaddr_s_o6, fabric_llpp2_awaddr_s_o7, fabric_llpp2_awaddr_s_o8, fabric_llpp2_awaddr_s_o9, fabric_llpp2_awaddr_s_o10, fabric_llpp2_awaddr_s_o11, fabric_llpp2_awaddr_s_o12, fabric_llpp2_awaddr_s_o13, fabric_llpp2_awaddr_s_o14, fabric_llpp2_awaddr_s_o15, fabric_llpp2_awaddr_s_o16, fabric_llpp2_awaddr_s_o17, fabric_llpp2_awaddr_s_o18, fabric_llpp2_awaddr_s_o19, fabric_llpp2_awaddr_s_o20, fabric_llpp2_awaddr_s_o21
-, fabric_llpp2_awaddr_s_o22, fabric_llpp2_awaddr_s_o23, fabric_llpp2_awaddr_s_o24, fabric_llpp2_awaddr_s_o25, fabric_llpp2_awaddr_s_o26, fabric_llpp2_awaddr_s_o27, fabric_llpp2_awaddr_s_o28, fabric_llpp2_awaddr_s_o29, fabric_llpp2_awaddr_s_o30, fabric_llpp2_awaddr_s_o31, fabric_llpp2_awaddr_s_o32, fabric_llpp2_awburst_s_o1, fabric_llpp2_awburst_s_o2, fabric_llpp2_awcache_s_o1, fabric_llpp2_awcache_s_o2, fabric_llpp2_awcache_s_o3, fabric_llpp2_awcache_s_o4, fabric_llpp2_awid_s_o1, fabric_llpp2_awid_s_o2, fabric_llpp2_awid_s_o3, fabric_llpp2_awid_s_o4
-, fabric_llpp2_awid_s_o5, fabric_llpp2_awid_s_o6, fabric_llpp2_awid_s_o7, fabric_llpp2_awid_s_o8, fabric_llpp2_awid_s_o9, fabric_llpp2_awid_s_o10, fabric_llpp2_awid_s_o11, fabric_llpp2_awid_s_o12, fabric_llpp2_awlen_s_o1, fabric_llpp2_awlen_s_o2, fabric_llpp2_awlen_s_o3, fabric_llpp2_awlen_s_o4, fabric_llpp2_awlen_s_o5, fabric_llpp2_awlen_s_o6, fabric_llpp2_awlen_s_o7, fabric_llpp2_awlen_s_o8, fabric_llpp2_awlock_s_o, fabric_llpp2_awprot_s_o1, fabric_llpp2_awprot_s_o2, fabric_llpp2_awprot_s_o3, fabric_llpp2_awqos_s_o1
-, fabric_llpp2_awqos_s_o2, fabric_llpp2_awqos_s_o3, fabric_llpp2_awqos_s_o4, fabric_llpp2_awsize_s_o1, fabric_llpp2_awsize_s_o2, fabric_llpp2_awsize_s_o3, fabric_llpp2_awvalid_s_o, fabric_llpp2_bready_s_o, fabric_llpp2_rready_s_o, fabric_llpp2_wdata_s_o1, fabric_llpp2_wdata_s_o2, fabric_llpp2_wdata_s_o3, fabric_llpp2_wdata_s_o4, fabric_llpp2_wdata_s_o5, fabric_llpp2_wdata_s_o6, fabric_llpp2_wdata_s_o7, fabric_llpp2_wdata_s_o8, fabric_llpp2_wdata_s_o9, fabric_llpp2_wdata_s_o10, fabric_llpp2_wdata_s_o11, fabric_llpp2_wdata_s_o12
-, fabric_llpp2_wdata_s_o13, fabric_llpp2_wdata_s_o14, fabric_llpp2_wdata_s_o15, fabric_llpp2_wdata_s_o16, fabric_llpp2_wdata_s_o17, fabric_llpp2_wdata_s_o18, fabric_llpp2_wdata_s_o19, fabric_llpp2_wdata_s_o20, fabric_llpp2_wdata_s_o21, fabric_llpp2_wdata_s_o22, fabric_llpp2_wdata_s_o23, fabric_llpp2_wdata_s_o24, fabric_llpp2_wdata_s_o25, fabric_llpp2_wdata_s_o26, fabric_llpp2_wdata_s_o27, fabric_llpp2_wdata_s_o28, fabric_llpp2_wdata_s_o29, fabric_llpp2_wdata_s_o30, fabric_llpp2_wdata_s_o31, fabric_llpp2_wdata_s_o32, fabric_llpp2_wlast_s_o
-, fabric_llpp2_wstrb_s_o1, fabric_llpp2_wstrb_s_o2, fabric_llpp2_wstrb_s_o3, fabric_llpp2_wstrb_s_o4, fabric_llpp2_wvalid_s_o, fabric_llpp2_arready_s_i, fabric_llpp2_awready_s_i, fabric_llpp2_bid_s_i1, fabric_llpp2_bid_s_i2, fabric_llpp2_bid_s_i3, fabric_llpp2_bid_s_i4, fabric_llpp2_bid_s_i5, fabric_llpp2_bid_s_i6, fabric_llpp2_bid_s_i7, fabric_llpp2_bid_s_i8, fabric_llpp2_bid_s_i9, fabric_llpp2_bid_s_i10, fabric_llpp2_bid_s_i11, fabric_llpp2_bid_s_i12, fabric_llpp2_bresp_s_i1, fabric_llpp2_bresp_s_i2
-, fabric_llpp2_bvalid_s_i, fabric_llpp2_rdata_s_i1, fabric_llpp2_rdata_s_i2, fabric_llpp2_rdata_s_i3, fabric_llpp2_rdata_s_i4, fabric_llpp2_rdata_s_i5, fabric_llpp2_rdata_s_i6, fabric_llpp2_rdata_s_i7, fabric_llpp2_rdata_s_i8, fabric_llpp2_rdata_s_i9, fabric_llpp2_rdata_s_i10, fabric_llpp2_rdata_s_i11, fabric_llpp2_rdata_s_i12, fabric_llpp2_rdata_s_i13, fabric_llpp2_rdata_s_i14, fabric_llpp2_rdata_s_i15, fabric_llpp2_rdata_s_i16, fabric_llpp2_rdata_s_i17, fabric_llpp2_rdata_s_i18, fabric_llpp2_rdata_s_i19, fabric_llpp2_rdata_s_i20
-, fabric_llpp2_rdata_s_i21, fabric_llpp2_rdata_s_i22, fabric_llpp2_rdata_s_i23, fabric_llpp2_rdata_s_i24, fabric_llpp2_rdata_s_i25, fabric_llpp2_rdata_s_i26, fabric_llpp2_rdata_s_i27, fabric_llpp2_rdata_s_i28, fabric_llpp2_rdata_s_i29, fabric_llpp2_rdata_s_i30, fabric_llpp2_rdata_s_i31, fabric_llpp2_rdata_s_i32, fabric_llpp2_rid_s_i1, fabric_llpp2_rid_s_i2, fabric_llpp2_rid_s_i3, fabric_llpp2_rid_s_i4, fabric_llpp2_rid_s_i5, fabric_llpp2_rid_s_i6, fabric_llpp2_rid_s_i7, fabric_llpp2_rid_s_i8, fabric_llpp2_rid_s_i9
-, fabric_llpp2_rid_s_i10, fabric_llpp2_rid_s_i11, fabric_llpp2_rid_s_i12, fabric_llpp2_rlast_s_i, fabric_llpp2_rresp_s_i1, fabric_llpp2_rresp_s_i2, fabric_llpp2_rvalid_s_i, fabric_llpp2_wready_s_i, fabric_llpp3_araddr_s_o1, fabric_llpp3_araddr_s_o2, fabric_llpp3_araddr_s_o3, fabric_llpp3_araddr_s_o4, fabric_llpp3_araddr_s_o5, fabric_llpp3_araddr_s_o6, fabric_llpp3_araddr_s_o7, fabric_llpp3_araddr_s_o8, fabric_llpp3_araddr_s_o9, fabric_llpp3_araddr_s_o10, fabric_llpp3_araddr_s_o11, fabric_llpp3_araddr_s_o12, fabric_llpp3_araddr_s_o13
-, fabric_llpp3_araddr_s_o14, fabric_llpp3_araddr_s_o15, fabric_llpp3_araddr_s_o16, fabric_llpp3_araddr_s_o17, fabric_llpp3_araddr_s_o18, fabric_llpp3_araddr_s_o19, fabric_llpp3_araddr_s_o20, fabric_llpp3_araddr_s_o21, fabric_llpp3_araddr_s_o22, fabric_llpp3_araddr_s_o23, fabric_llpp3_araddr_s_o24, fabric_llpp3_araddr_s_o25, fabric_llpp3_araddr_s_o26, fabric_llpp3_araddr_s_o27, fabric_llpp3_araddr_s_o28, fabric_llpp3_araddr_s_o29, fabric_llpp3_araddr_s_o30, fabric_llpp3_araddr_s_o31, fabric_llpp3_araddr_s_o32, fabric_llpp3_arburst_s_o1, fabric_llpp3_arburst_s_o2
-, fabric_llpp3_arcache_s_o1, fabric_llpp3_arcache_s_o2, fabric_llpp3_arcache_s_o3, fabric_llpp3_arcache_s_o4, fabric_llpp3_arid_s_o1, fabric_llpp3_arid_s_o2, fabric_llpp3_arid_s_o3, fabric_llpp3_arid_s_o4, fabric_llpp3_arid_s_o5, fabric_llpp3_arid_s_o6, fabric_llpp3_arid_s_o7, fabric_llpp3_arid_s_o8, fabric_llpp3_arid_s_o9, fabric_llpp3_arid_s_o10, fabric_llpp3_arid_s_o11, fabric_llpp3_arid_s_o12, fabric_llpp3_arlen_s_o1, fabric_llpp3_arlen_s_o2, fabric_llpp3_arlen_s_o3, fabric_llpp3_arlen_s_o4, fabric_llpp3_arlen_s_o5
-, fabric_llpp3_arlen_s_o6, fabric_llpp3_arlen_s_o7, fabric_llpp3_arlen_s_o8, fabric_llpp3_arlock_s_o, fabric_llpp3_arprot_s_o1, fabric_llpp3_arprot_s_o2, fabric_llpp3_arprot_s_o3, fabric_llpp3_arqos_s_o1, fabric_llpp3_arqos_s_o2, fabric_llpp3_arqos_s_o3, fabric_llpp3_arqos_s_o4, fabric_llpp3_arsize_s_o1, fabric_llpp3_arsize_s_o2, fabric_llpp3_arsize_s_o3, fabric_llpp3_arvalid_s_o, fabric_llpp3_awaddr_s_o1, fabric_llpp3_awaddr_s_o2, fabric_llpp3_awaddr_s_o3, fabric_llpp3_awaddr_s_o4, fabric_llpp3_awaddr_s_o5, fabric_llpp3_awaddr_s_o6
-, fabric_llpp3_awaddr_s_o7, fabric_llpp3_awaddr_s_o8, fabric_llpp3_awaddr_s_o9, fabric_llpp3_awaddr_s_o10, fabric_llpp3_awaddr_s_o11, fabric_llpp3_awaddr_s_o12, fabric_llpp3_awaddr_s_o13, fabric_llpp3_awaddr_s_o14, fabric_llpp3_awaddr_s_o15, fabric_llpp3_awaddr_s_o16, fabric_llpp3_awaddr_s_o17, fabric_llpp3_awaddr_s_o18, fabric_llpp3_awaddr_s_o19, fabric_llpp3_awaddr_s_o20, fabric_llpp3_awaddr_s_o21, fabric_llpp3_awaddr_s_o22, fabric_llpp3_awaddr_s_o23, fabric_llpp3_awaddr_s_o24, fabric_llpp3_awaddr_s_o25, fabric_llpp3_awaddr_s_o26, fabric_llpp3_awaddr_s_o27
-, fabric_llpp3_awaddr_s_o28, fabric_llpp3_awaddr_s_o29, fabric_llpp3_awaddr_s_o30, fabric_llpp3_awaddr_s_o31, fabric_llpp3_awaddr_s_o32, fabric_llpp3_awburst_s_o1, fabric_llpp3_awburst_s_o2, fabric_llpp3_awcache_s_o1, fabric_llpp3_awcache_s_o2, fabric_llpp3_awcache_s_o3, fabric_llpp3_awcache_s_o4, fabric_llpp3_awid_s_o1, fabric_llpp3_awid_s_o2, fabric_llpp3_awid_s_o3, fabric_llpp3_awid_s_o4, fabric_llpp3_awid_s_o5, fabric_llpp3_awid_s_o6, fabric_llpp3_awid_s_o7, fabric_llpp3_awid_s_o8, fabric_llpp3_awid_s_o9, fabric_llpp3_awid_s_o10
-, fabric_llpp3_awid_s_o11, fabric_llpp3_awid_s_o12, fabric_llpp3_awlen_s_o1, fabric_llpp3_awlen_s_o2, fabric_llpp3_awlen_s_o3, fabric_llpp3_awlen_s_o4, fabric_llpp3_awlen_s_o5, fabric_llpp3_awlen_s_o6, fabric_llpp3_awlen_s_o7, fabric_llpp3_awlen_s_o8, fabric_llpp3_awlock_s_o, fabric_llpp3_awprot_s_o1, fabric_llpp3_awprot_s_o2, fabric_llpp3_awprot_s_o3, fabric_llpp3_awqos_s_o1, fabric_llpp3_awqos_s_o2, fabric_llpp3_awqos_s_o3, fabric_llpp3_awqos_s_o4, fabric_llpp3_awsize_s_o1, fabric_llpp3_awsize_s_o2, fabric_llpp3_awsize_s_o3
-, fabric_llpp3_awvalid_s_o, fabric_llpp3_bready_s_o, fabric_llpp3_rready_s_o, fabric_llpp3_wdata_s_o1, fabric_llpp3_wdata_s_o2, fabric_llpp3_wdata_s_o3, fabric_llpp3_wdata_s_o4, fabric_llpp3_wdata_s_o5, fabric_llpp3_wdata_s_o6, fabric_llpp3_wdata_s_o7, fabric_llpp3_wdata_s_o8, fabric_llpp3_wdata_s_o9, fabric_llpp3_wdata_s_o10, fabric_llpp3_wdata_s_o11, fabric_llpp3_wdata_s_o12, fabric_llpp3_wdata_s_o13, fabric_llpp3_wdata_s_o14, fabric_llpp3_wdata_s_o15, fabric_llpp3_wdata_s_o16, fabric_llpp3_wdata_s_o17, fabric_llpp3_wdata_s_o18
-, fabric_llpp3_wdata_s_o19, fabric_llpp3_wdata_s_o20, fabric_llpp3_wdata_s_o21, fabric_llpp3_wdata_s_o22, fabric_llpp3_wdata_s_o23, fabric_llpp3_wdata_s_o24, fabric_llpp3_wdata_s_o25, fabric_llpp3_wdata_s_o26, fabric_llpp3_wdata_s_o27, fabric_llpp3_wdata_s_o28, fabric_llpp3_wdata_s_o29, fabric_llpp3_wdata_s_o30, fabric_llpp3_wdata_s_o31, fabric_llpp3_wdata_s_o32, fabric_llpp3_wlast_s_o, fabric_llpp3_wstrb_s_o1, fabric_llpp3_wstrb_s_o2, fabric_llpp3_wstrb_s_o3, fabric_llpp3_wstrb_s_o4, fabric_llpp3_wvalid_s_o, fabric_llpp3_arready_s_i
-, fabric_llpp3_awready_s_i, fabric_llpp3_bid_s_i1, fabric_llpp3_bid_s_i2, fabric_llpp3_bid_s_i3, fabric_llpp3_bid_s_i4, fabric_llpp3_bid_s_i5, fabric_llpp3_bid_s_i6, fabric_llpp3_bid_s_i7, fabric_llpp3_bid_s_i8, fabric_llpp3_bid_s_i9, fabric_llpp3_bid_s_i10, fabric_llpp3_bid_s_i11, fabric_llpp3_bid_s_i12, fabric_llpp3_bresp_s_i1, fabric_llpp3_bresp_s_i2, fabric_llpp3_bvalid_s_i, fabric_llpp3_rdata_s_i1, fabric_llpp3_rdata_s_i2, fabric_llpp3_rdata_s_i3, fabric_llpp3_rdata_s_i4, fabric_llpp3_rdata_s_i5
-, fabric_llpp3_rdata_s_i6, fabric_llpp3_rdata_s_i7, fabric_llpp3_rdata_s_i8, fabric_llpp3_rdata_s_i9, fabric_llpp3_rdata_s_i10, fabric_llpp3_rdata_s_i11, fabric_llpp3_rdata_s_i12, fabric_llpp3_rdata_s_i13, fabric_llpp3_rdata_s_i14, fabric_llpp3_rdata_s_i15, fabric_llpp3_rdata_s_i16, fabric_llpp3_rdata_s_i17, fabric_llpp3_rdata_s_i18, fabric_llpp3_rdata_s_i19, fabric_llpp3_rdata_s_i20, fabric_llpp3_rdata_s_i21, fabric_llpp3_rdata_s_i22, fabric_llpp3_rdata_s_i23, fabric_llpp3_rdata_s_i24, fabric_llpp3_rdata_s_i25, fabric_llpp3_rdata_s_i26
-, fabric_llpp3_rdata_s_i27, fabric_llpp3_rdata_s_i28, fabric_llpp3_rdata_s_i29, fabric_llpp3_rdata_s_i30, fabric_llpp3_rdata_s_i31, fabric_llpp3_rdata_s_i32, fabric_llpp3_rid_s_i1, fabric_llpp3_rid_s_i2, fabric_llpp3_rid_s_i3, fabric_llpp3_rid_s_i4, fabric_llpp3_rid_s_i5, fabric_llpp3_rid_s_i6, fabric_llpp3_rid_s_i7, fabric_llpp3_rid_s_i8, fabric_llpp3_rid_s_i9, fabric_llpp3_rid_s_i10, fabric_llpp3_rid_s_i11, fabric_llpp3_rid_s_i12, fabric_llpp3_rlast_s_i, fabric_llpp3_rresp_s_i1, fabric_llpp3_rresp_s_i2
-, fabric_llpp3_rvalid_s_i, fabric_llpp3_wready_s_i, fabric_qos_pprdata_o1, fabric_qos_pprdata_o2, fabric_qos_pprdata_o3, fabric_qos_pprdata_o4, fabric_qos_pprdata_o5, fabric_qos_pprdata_o6, fabric_qos_pprdata_o7, fabric_qos_pprdata_o8, fabric_qos_pprdata_o9, fabric_qos_pprdata_o10, fabric_qos_pprdata_o11, fabric_qos_pprdata_o12, fabric_qos_pprdata_o13, fabric_qos_pprdata_o14, fabric_qos_pprdata_o15, fabric_qos_pprdata_o16, fabric_qos_pprdata_o17, fabric_qos_pprdata_o18, fabric_qos_pprdata_o19
-, fabric_qos_pprdata_o20, fabric_qos_pprdata_o21, fabric_qos_pprdata_o22, fabric_qos_pprdata_o23, fabric_qos_pprdata_o24, fabric_qos_pprdata_o25, fabric_qos_pprdata_o26, fabric_qos_pprdata_o27, fabric_qos_pprdata_o28, fabric_qos_pprdata_o29, fabric_qos_pprdata_o30, fabric_qos_pprdata_o31, fabric_qos_pprdata_o32, fabric_qos_ppready_o, fabric_qos_ppslverr_o, fabric_qos_ppaddr_i1, fabric_qos_ppaddr_i2, fabric_qos_ppaddr_i3, fabric_qos_ppaddr_i4, fabric_qos_ppaddr_i5, fabric_qos_ppaddr_i6
-, fabric_qos_ppaddr_i7, fabric_qos_ppaddr_i8, fabric_qos_ppaddr_i9, fabric_qos_ppaddr_i10, fabric_qos_ppaddr_i11, fabric_qos_ppaddr_i12, fabric_qos_ppaddr_i13, fabric_qos_ppaddr_i14, fabric_qos_ppaddr_i15, fabric_qos_ppaddr_i16, fabric_qos_ppaddr_i17, fabric_qos_ppaddr_i18, fabric_qos_ppaddr_i19, fabric_qos_ppaddr_i20, fabric_qos_ppaddr_i21, fabric_qos_ppaddr_i22, fabric_qos_ppaddr_i23, fabric_qos_ppaddr_i24, fabric_qos_ppaddr_i25, fabric_qos_ppaddr_i26, fabric_qos_ppaddr_i27
-, fabric_qos_ppaddr_i28, fabric_qos_ppaddr_i29, fabric_qos_ppaddr_i30, fabric_qos_ppaddr_i31, fabric_qos_ppaddr_i32, fabric_qos_ppenable_i, fabric_qos_ppwdata_i1, fabric_qos_ppwdata_i2, fabric_qos_ppwdata_i3, fabric_qos_ppwdata_i4, fabric_qos_ppwdata_i5, fabric_qos_ppwdata_i6, fabric_qos_ppwdata_i7, fabric_qos_ppwdata_i8, fabric_qos_ppwdata_i9, fabric_qos_ppwdata_i10, fabric_qos_ppwdata_i11, fabric_qos_ppwdata_i12, fabric_qos_ppwdata_i13, fabric_qos_ppwdata_i14, fabric_qos_ppwdata_i15
-, fabric_qos_ppwdata_i16, fabric_qos_ppwdata_i17, fabric_qos_ppwdata_i18, fabric_qos_ppwdata_i19, fabric_qos_ppwdata_i20, fabric_qos_ppwdata_i21, fabric_qos_ppwdata_i22, fabric_qos_ppwdata_i23, fabric_qos_ppwdata_i24, fabric_qos_ppwdata_i25, fabric_qos_ppwdata_i26, fabric_qos_ppwdata_i27, fabric_qos_ppwdata_i28, fabric_qos_ppwdata_i29, fabric_qos_ppwdata_i30, fabric_qos_ppwdata_i31, fabric_qos_ppwdata_i32, fabric_qos_ppwrite_i, fabric_qos_presetn_i, fabric_qos_psel_i, fabric_tnd_hssl_flushin_o
-, fabric_tnd_hssl_trigin_o, fabric_tnd_fpga_apb_master_paddr_o1, fabric_tnd_fpga_apb_master_paddr_o2, fabric_tnd_fpga_apb_master_paddr_o3, fabric_tnd_fpga_apb_master_paddr_o4, fabric_tnd_fpga_apb_master_paddr_o5, fabric_tnd_fpga_apb_master_paddr_o6, fabric_tnd_fpga_apb_master_paddr_o7, fabric_tnd_fpga_apb_master_paddr_o8, fabric_tnd_fpga_apb_master_paddr_o9, fabric_tnd_fpga_apb_master_paddr_o10, fabric_tnd_fpga_apb_master_paddr_o11, fabric_tnd_fpga_apb_master_paddr_o12, fabric_tnd_fpga_apb_master_paddr_o13, fabric_tnd_fpga_apb_master_paddr_o14, fabric_tnd_fpga_apb_master_paddr_o15, fabric_tnd_fpga_apb_master_paddr_o16, fabric_tnd_fpga_apb_master_paddr_o17, fabric_tnd_fpga_apb_master_paddr_o18, fabric_tnd_fpga_apb_master_paddr_o19, fabric_tnd_fpga_apb_master_paddr_o20
-, fabric_tnd_fpga_apb_master_paddr_o21, fabric_tnd_fpga_apb_master_paddr_o22, fabric_tnd_fpga_apb_master_paddr_o23, fabric_tnd_fpga_apb_master_paddr_o24, fabric_tnd_fpga_apb_master_paddr_o25, fabric_tnd_fpga_apb_master_paddr_o26, fabric_tnd_fpga_apb_master_paddr_o27, fabric_tnd_fpga_apb_master_paddr_o28, fabric_tnd_fpga_apb_master_paddr_o29, fabric_tnd_fpga_apb_master_paddr_o30, fabric_tnd_fpga_apb_master_paddr_o31, fabric_tnd_fpga_apb_master_paddr_o32, fabric_tnd_fpga_apb_master_penable_o, fabric_tnd_fpga_apb_master_psel_o, fabric_tnd_fpga_apb_master_pwdata_o1, fabric_tnd_fpga_apb_master_pwdata_o2, fabric_tnd_fpga_apb_master_pwdata_o3, fabric_tnd_fpga_apb_master_pwdata_o4, fabric_tnd_fpga_apb_master_pwdata_o5, fabric_tnd_fpga_apb_master_pwdata_o6, fabric_tnd_fpga_apb_master_pwdata_o7
-, fabric_tnd_fpga_apb_master_pwdata_o8, fabric_tnd_fpga_apb_master_pwdata_o9, fabric_tnd_fpga_apb_master_pwdata_o10, fabric_tnd_fpga_apb_master_pwdata_o11, fabric_tnd_fpga_apb_master_pwdata_o12, fabric_tnd_fpga_apb_master_pwdata_o13, fabric_tnd_fpga_apb_master_pwdata_o14, fabric_tnd_fpga_apb_master_pwdata_o15, fabric_tnd_fpga_apb_master_pwdata_o16, fabric_tnd_fpga_apb_master_pwdata_o17, fabric_tnd_fpga_apb_master_pwdata_o18, fabric_tnd_fpga_apb_master_pwdata_o19, fabric_tnd_fpga_apb_master_pwdata_o20, fabric_tnd_fpga_apb_master_pwdata_o21, fabric_tnd_fpga_apb_master_pwdata_o22, fabric_tnd_fpga_apb_master_pwdata_o23, fabric_tnd_fpga_apb_master_pwdata_o24, fabric_tnd_fpga_apb_master_pwdata_o25, fabric_tnd_fpga_apb_master_pwdata_o26, fabric_tnd_fpga_apb_master_pwdata_o27, fabric_tnd_fpga_apb_master_pwdata_o28
-, fabric_tnd_fpga_apb_master_pwdata_o29, fabric_tnd_fpga_apb_master_pwdata_o30, fabric_tnd_fpga_apb_master_pwdata_o31, fabric_tnd_fpga_apb_master_pwdata_o32, fabric_tnd_fpga_apb_master_pwrite_o, fabric_tnd_fpga_atb_master_afvalid_o, fabric_tnd_fpga_atb_master_atready_o, fabric_tnd_fpga_atb_master_syncreq_o, fabric_tnd_hssl_apb_master_paddr_o1, fabric_tnd_hssl_apb_master_paddr_o2, fabric_tnd_hssl_apb_master_paddr_o3, fabric_tnd_hssl_apb_master_paddr_o4, fabric_tnd_hssl_apb_master_paddr_o5, fabric_tnd_hssl_apb_master_paddr_o6, fabric_tnd_hssl_apb_master_paddr_o7, fabric_tnd_hssl_apb_master_paddr_o8, fabric_tnd_hssl_apb_master_paddr_o9, fabric_tnd_hssl_apb_master_paddr_o10, fabric_tnd_hssl_apb_master_paddr_o11, fabric_tnd_hssl_apb_master_paddr_o12, fabric_tnd_hssl_apb_master_paddr_o13
-, fabric_tnd_hssl_apb_master_paddr_o14, fabric_tnd_hssl_apb_master_paddr_o15, fabric_tnd_hssl_apb_master_paddr_o16, fabric_tnd_hssl_apb_master_paddr_o17, fabric_tnd_hssl_apb_master_paddr_o18, fabric_tnd_hssl_apb_master_paddr_o19, fabric_tnd_hssl_apb_master_paddr_o20, fabric_tnd_hssl_apb_master_paddr_o21, fabric_tnd_hssl_apb_master_paddr_o22, fabric_tnd_hssl_apb_master_paddr_o23, fabric_tnd_hssl_apb_master_paddr_o24, fabric_tnd_hssl_apb_master_paddr_o25, fabric_tnd_hssl_apb_master_paddr_o26, fabric_tnd_hssl_apb_master_paddr_o27, fabric_tnd_hssl_apb_master_paddr_o28, fabric_tnd_hssl_apb_master_paddr_o29, fabric_tnd_hssl_apb_master_paddr_o30, fabric_tnd_hssl_apb_master_paddr_o31, fabric_tnd_hssl_apb_master_paddr_o32, fabric_tnd_hssl_apb_master_penable_o, fabric_tnd_hssl_apb_master_psel_o
-, fabric_tnd_hssl_apb_master_pwdata_o1, fabric_tnd_hssl_apb_master_pwdata_o2, fabric_tnd_hssl_apb_master_pwdata_o3, fabric_tnd_hssl_apb_master_pwdata_o4, fabric_tnd_hssl_apb_master_pwdata_o5, fabric_tnd_hssl_apb_master_pwdata_o6, fabric_tnd_hssl_apb_master_pwdata_o7, fabric_tnd_hssl_apb_master_pwdata_o8, fabric_tnd_hssl_apb_master_pwdata_o9, fabric_tnd_hssl_apb_master_pwdata_o10, fabric_tnd_hssl_apb_master_pwdata_o11, fabric_tnd_hssl_apb_master_pwdata_o12, fabric_tnd_hssl_apb_master_pwdata_o13, fabric_tnd_hssl_apb_master_pwdata_o14, fabric_tnd_hssl_apb_master_pwdata_o15, fabric_tnd_hssl_apb_master_pwdata_o16, fabric_tnd_hssl_apb_master_pwdata_o17, fabric_tnd_hssl_apb_master_pwdata_o18, fabric_tnd_hssl_apb_master_pwdata_o19, fabric_tnd_hssl_apb_master_pwdata_o20, fabric_tnd_hssl_apb_master_pwdata_o21
-, fabric_tnd_hssl_apb_master_pwdata_o22, fabric_tnd_hssl_apb_master_pwdata_o23, fabric_tnd_hssl_apb_master_pwdata_o24, fabric_tnd_hssl_apb_master_pwdata_o25, fabric_tnd_hssl_apb_master_pwdata_o26, fabric_tnd_hssl_apb_master_pwdata_o27, fabric_tnd_hssl_apb_master_pwdata_o28, fabric_tnd_hssl_apb_master_pwdata_o29, fabric_tnd_hssl_apb_master_pwdata_o30, fabric_tnd_hssl_apb_master_pwdata_o31, fabric_tnd_hssl_apb_master_pwdata_o32, fabric_tnd_hssl_apb_master_pwrite_o, fabric_tnd_hssl_atb_master_afready_o, fabric_tnd_hssl_atb_master_atbytes_o1, fabric_tnd_hssl_atb_master_atbytes_o2, fabric_tnd_hssl_atb_master_atbytes_o3, fabric_tnd_hssl_atb_master_atbytes_o4, fabric_tnd_hssl_atb_master_atdata_o1, fabric_tnd_hssl_atb_master_atdata_o2, fabric_tnd_hssl_atb_master_atdata_o3, fabric_tnd_hssl_atb_master_atdata_o4
-, fabric_tnd_hssl_atb_master_atdata_o5, fabric_tnd_hssl_atb_master_atdata_o6, fabric_tnd_hssl_atb_master_atdata_o7, fabric_tnd_hssl_atb_master_atdata_o8, fabric_tnd_hssl_atb_master_atdata_o9, fabric_tnd_hssl_atb_master_atdata_o10, fabric_tnd_hssl_atb_master_atdata_o11, fabric_tnd_hssl_atb_master_atdata_o12, fabric_tnd_hssl_atb_master_atdata_o13, fabric_tnd_hssl_atb_master_atdata_o14, fabric_tnd_hssl_atb_master_atdata_o15, fabric_tnd_hssl_atb_master_atdata_o16, fabric_tnd_hssl_atb_master_atdata_o17, fabric_tnd_hssl_atb_master_atdata_o18, fabric_tnd_hssl_atb_master_atdata_o19, fabric_tnd_hssl_atb_master_atdata_o20, fabric_tnd_hssl_atb_master_atdata_o21, fabric_tnd_hssl_atb_master_atdata_o22, fabric_tnd_hssl_atb_master_atdata_o23, fabric_tnd_hssl_atb_master_atdata_o24, fabric_tnd_hssl_atb_master_atdata_o25
-, fabric_tnd_hssl_atb_master_atdata_o26, fabric_tnd_hssl_atb_master_atdata_o27, fabric_tnd_hssl_atb_master_atdata_o28, fabric_tnd_hssl_atb_master_atdata_o29, fabric_tnd_hssl_atb_master_atdata_o30, fabric_tnd_hssl_atb_master_atdata_o31, fabric_tnd_hssl_atb_master_atdata_o32, fabric_tnd_hssl_atb_master_atdata_o33, fabric_tnd_hssl_atb_master_atdata_o34, fabric_tnd_hssl_atb_master_atdata_o35, fabric_tnd_hssl_atb_master_atdata_o36, fabric_tnd_hssl_atb_master_atdata_o37, fabric_tnd_hssl_atb_master_atdata_o38, fabric_tnd_hssl_atb_master_atdata_o39, fabric_tnd_hssl_atb_master_atdata_o40, fabric_tnd_hssl_atb_master_atdata_o41, fabric_tnd_hssl_atb_master_atdata_o42, fabric_tnd_hssl_atb_master_atdata_o43, fabric_tnd_hssl_atb_master_atdata_o44, fabric_tnd_hssl_atb_master_atdata_o45, fabric_tnd_hssl_atb_master_atdata_o46
-, fabric_tnd_hssl_atb_master_atdata_o47, fabric_tnd_hssl_atb_master_atdata_o48, fabric_tnd_hssl_atb_master_atdata_o49, fabric_tnd_hssl_atb_master_atdata_o50, fabric_tnd_hssl_atb_master_atdata_o51, fabric_tnd_hssl_atb_master_atdata_o52, fabric_tnd_hssl_atb_master_atdata_o53, fabric_tnd_hssl_atb_master_atdata_o54, fabric_tnd_hssl_atb_master_atdata_o55, fabric_tnd_hssl_atb_master_atdata_o56, fabric_tnd_hssl_atb_master_atdata_o57, fabric_tnd_hssl_atb_master_atdata_o58, fabric_tnd_hssl_atb_master_atdata_o59, fabric_tnd_hssl_atb_master_atdata_o60, fabric_tnd_hssl_atb_master_atdata_o61, fabric_tnd_hssl_atb_master_atdata_o62, fabric_tnd_hssl_atb_master_atdata_o63, fabric_tnd_hssl_atb_master_atdata_o64, fabric_tnd_hssl_atb_master_atdata_o65, fabric_tnd_hssl_atb_master_atdata_o66, fabric_tnd_hssl_atb_master_atdata_o67
-, fabric_tnd_hssl_atb_master_atdata_o68, fabric_tnd_hssl_atb_master_atdata_o69, fabric_tnd_hssl_atb_master_atdata_o70, fabric_tnd_hssl_atb_master_atdata_o71, fabric_tnd_hssl_atb_master_atdata_o72, fabric_tnd_hssl_atb_master_atdata_o73, fabric_tnd_hssl_atb_master_atdata_o74, fabric_tnd_hssl_atb_master_atdata_o75, fabric_tnd_hssl_atb_master_atdata_o76, fabric_tnd_hssl_atb_master_atdata_o77, fabric_tnd_hssl_atb_master_atdata_o78, fabric_tnd_hssl_atb_master_atdata_o79, fabric_tnd_hssl_atb_master_atdata_o80, fabric_tnd_hssl_atb_master_atdata_o81, fabric_tnd_hssl_atb_master_atdata_o82, fabric_tnd_hssl_atb_master_atdata_o83, fabric_tnd_hssl_atb_master_atdata_o84, fabric_tnd_hssl_atb_master_atdata_o85, fabric_tnd_hssl_atb_master_atdata_o86, fabric_tnd_hssl_atb_master_atdata_o87, fabric_tnd_hssl_atb_master_atdata_o88
-, fabric_tnd_hssl_atb_master_atdata_o89, fabric_tnd_hssl_atb_master_atdata_o90, fabric_tnd_hssl_atb_master_atdata_o91, fabric_tnd_hssl_atb_master_atdata_o92, fabric_tnd_hssl_atb_master_atdata_o93, fabric_tnd_hssl_atb_master_atdata_o94, fabric_tnd_hssl_atb_master_atdata_o95, fabric_tnd_hssl_atb_master_atdata_o96, fabric_tnd_hssl_atb_master_atdata_o97, fabric_tnd_hssl_atb_master_atdata_o98, fabric_tnd_hssl_atb_master_atdata_o99, fabric_tnd_hssl_atb_master_atdata_o100, fabric_tnd_hssl_atb_master_atdata_o101, fabric_tnd_hssl_atb_master_atdata_o102, fabric_tnd_hssl_atb_master_atdata_o103, fabric_tnd_hssl_atb_master_atdata_o104, fabric_tnd_hssl_atb_master_atdata_o105, fabric_tnd_hssl_atb_master_atdata_o106, fabric_tnd_hssl_atb_master_atdata_o107, fabric_tnd_hssl_atb_master_atdata_o108, fabric_tnd_hssl_atb_master_atdata_o109
-, fabric_tnd_hssl_atb_master_atdata_o110, fabric_tnd_hssl_atb_master_atdata_o111, fabric_tnd_hssl_atb_master_atdata_o112, fabric_tnd_hssl_atb_master_atdata_o113, fabric_tnd_hssl_atb_master_atdata_o114, fabric_tnd_hssl_atb_master_atdata_o115, fabric_tnd_hssl_atb_master_atdata_o116, fabric_tnd_hssl_atb_master_atdata_o117, fabric_tnd_hssl_atb_master_atdata_o118, fabric_tnd_hssl_atb_master_atdata_o119, fabric_tnd_hssl_atb_master_atdata_o120, fabric_tnd_hssl_atb_master_atdata_o121, fabric_tnd_hssl_atb_master_atdata_o122, fabric_tnd_hssl_atb_master_atdata_o123, fabric_tnd_hssl_atb_master_atdata_o124, fabric_tnd_hssl_atb_master_atdata_o125, fabric_tnd_hssl_atb_master_atdata_o126, fabric_tnd_hssl_atb_master_atdata_o127, fabric_tnd_hssl_atb_master_atdata_o128, fabric_tnd_hssl_atb_master_atid_o1, fabric_tnd_hssl_atb_master_atid_o2
-, fabric_tnd_hssl_atb_master_atid_o3, fabric_tnd_hssl_atb_master_atid_o4, fabric_tnd_hssl_atb_master_atid_o5, fabric_tnd_hssl_atb_master_atid_o6, fabric_tnd_hssl_atb_master_atid_o7, fabric_tnd_hssl_atb_master_atvalid_o, fabric_tnd_trace_clk_traceoutportintf_o, fabric_tnd_trace_ctl_traceoutportintf_o, fabric_tnd_trace_data_traceoutportintf_o1, fabric_tnd_trace_data_traceoutportintf_o2, fabric_tnd_trace_data_traceoutportintf_o3, fabric_tnd_trace_data_traceoutportintf_o4, fabric_tnd_trace_data_traceoutportintf_o5, fabric_tnd_trace_data_traceoutportintf_o6, fabric_tnd_trace_data_traceoutportintf_o7, fabric_tnd_trace_data_traceoutportintf_o8, fabric_tnd_trace_data_traceoutportintf_o9, fabric_tnd_trace_data_traceoutportintf_o10, fabric_tnd_trace_data_traceoutportintf_o11, fabric_tnd_trace_data_traceoutportintf_o12, fabric_tnd_trace_data_traceoutportintf_o13
-, fabric_tnd_trace_data_traceoutportintf_o14, fabric_tnd_trace_data_traceoutportintf_o15, fabric_tnd_trace_data_traceoutportintf_o16, fabric_tnd_trace_data_traceoutportintf_o17, fabric_tnd_trace_data_traceoutportintf_o18, fabric_tnd_trace_data_traceoutportintf_o19, fabric_tnd_trace_data_traceoutportintf_o20, fabric_tnd_trace_data_traceoutportintf_o21, fabric_tnd_trace_data_traceoutportintf_o22, fabric_tnd_trace_data_traceoutportintf_o23, fabric_tnd_trace_data_traceoutportintf_o24, fabric_tnd_trace_data_traceoutportintf_o25, fabric_tnd_trace_data_traceoutportintf_o26, fabric_tnd_trace_data_traceoutportintf_o27, fabric_tnd_trace_data_traceoutportintf_o28, fabric_tnd_trace_data_traceoutportintf_o29, fabric_tnd_trace_data_traceoutportintf_o30, fabric_tnd_trace_data_traceoutportintf_o31, fabric_tnd_trace_data_traceoutportintf_o32, fabric_tsvalue_tsgen_fpga_o1, fabric_tsvalue_tsgen_fpga_o2
-, fabric_tsvalue_tsgen_fpga_o3, fabric_tsvalue_tsgen_fpga_o4, fabric_tsvalue_tsgen_fpga_o5, fabric_tsvalue_tsgen_fpga_o6, fabric_tsvalue_tsgen_fpga_o7, fabric_tsvalue_tsgen_fpga_o8, fabric_tsvalue_tsgen_fpga_o9, fabric_tsvalue_tsgen_fpga_o10, fabric_tsvalue_tsgen_fpga_o11, fabric_tsvalue_tsgen_fpga_o12, fabric_tsvalue_tsgen_fpga_o13, fabric_tsvalue_tsgen_fpga_o14, fabric_tsvalue_tsgen_fpga_o15, fabric_tsvalue_tsgen_fpga_o16, fabric_tsvalue_tsgen_fpga_o17, fabric_tsvalue_tsgen_fpga_o18, fabric_tsvalue_tsgen_fpga_o19, fabric_tsvalue_tsgen_fpga_o20, fabric_tsvalue_tsgen_fpga_o21, fabric_tsvalue_tsgen_fpga_o22, fabric_tsvalue_tsgen_fpga_o23
-, fabric_tsvalue_tsgen_fpga_o24, fabric_tsvalue_tsgen_fpga_o25, fabric_tsvalue_tsgen_fpga_o26, fabric_tsvalue_tsgen_fpga_o27, fabric_tsvalue_tsgen_fpga_o28, fabric_tsvalue_tsgen_fpga_o29, fabric_tsvalue_tsgen_fpga_o30, fabric_tsvalue_tsgen_fpga_o31, fabric_tsvalue_tsgen_fpga_o32, fabric_tsvalue_tsgen_fpga_o33, fabric_tsvalue_tsgen_fpga_o34, fabric_tsvalue_tsgen_fpga_o35, fabric_tsvalue_tsgen_fpga_o36, fabric_tsvalue_tsgen_fpga_o37, fabric_tsvalue_tsgen_fpga_o38, fabric_tsvalue_tsgen_fpga_o39, fabric_tsvalue_tsgen_fpga_o40, fabric_tsvalue_tsgen_fpga_o41, fabric_tsvalue_tsgen_fpga_o42, fabric_tsvalue_tsgen_fpga_o43, fabric_tsvalue_tsgen_fpga_o44
-, fabric_tsvalue_tsgen_fpga_o45, fabric_tsvalue_tsgen_fpga_o46, fabric_tsvalue_tsgen_fpga_o47, fabric_tsvalue_tsgen_fpga_o48, fabric_tsvalue_tsgen_fpga_o49, fabric_tsvalue_tsgen_fpga_o50, fabric_tsvalue_tsgen_fpga_o51, fabric_tsvalue_tsgen_fpga_o52, fabric_tsvalue_tsgen_fpga_o53, fabric_tsvalue_tsgen_fpga_o54, fabric_tsvalue_tsgen_fpga_o55, fabric_tsvalue_tsgen_fpga_o56, fabric_tsvalue_tsgen_fpga_o57, fabric_tsvalue_tsgen_fpga_o58, fabric_tsvalue_tsgen_fpga_o59, fabric_tsvalue_tsgen_fpga_o60, fabric_tsvalue_tsgen_fpga_o61, fabric_tsvalue_tsgen_fpga_o62, fabric_tsvalue_tsgen_fpga_o63, fabric_tsvalue_tsgen_fpga_o64, fabric_tnd_fpga_apb_master_prdata_i1
-, fabric_tnd_fpga_apb_master_prdata_i2, fabric_tnd_fpga_apb_master_prdata_i3, fabric_tnd_fpga_apb_master_prdata_i4, fabric_tnd_fpga_apb_master_prdata_i5, fabric_tnd_fpga_apb_master_prdata_i6, fabric_tnd_fpga_apb_master_prdata_i7, fabric_tnd_fpga_apb_master_prdata_i8, fabric_tnd_fpga_apb_master_prdata_i9, fabric_tnd_fpga_apb_master_prdata_i10, fabric_tnd_fpga_apb_master_prdata_i11, fabric_tnd_fpga_apb_master_prdata_i12, fabric_tnd_fpga_apb_master_prdata_i13, fabric_tnd_fpga_apb_master_prdata_i14, fabric_tnd_fpga_apb_master_prdata_i15, fabric_tnd_fpga_apb_master_prdata_i16, fabric_tnd_fpga_apb_master_prdata_i17, fabric_tnd_fpga_apb_master_prdata_i18, fabric_tnd_fpga_apb_master_prdata_i19, fabric_tnd_fpga_apb_master_prdata_i20, fabric_tnd_fpga_apb_master_prdata_i21, fabric_tnd_fpga_apb_master_prdata_i22
-, fabric_tnd_fpga_apb_master_prdata_i23, fabric_tnd_fpga_apb_master_prdata_i24, fabric_tnd_fpga_apb_master_prdata_i25, fabric_tnd_fpga_apb_master_prdata_i26, fabric_tnd_fpga_apb_master_prdata_i27, fabric_tnd_fpga_apb_master_prdata_i28, fabric_tnd_fpga_apb_master_prdata_i29, fabric_tnd_fpga_apb_master_prdata_i30, fabric_tnd_fpga_apb_master_prdata_i31, fabric_tnd_fpga_apb_master_prdata_i32, fabric_tnd_fpga_apb_master_pready_i, fabric_tnd_fpga_apb_master_pslverr_i, fabric_tnd_fpga_atb_master_afready_i, fabric_tnd_fpga_atb_master_atbytes_i1, fabric_tnd_fpga_atb_master_atbytes_i2, fabric_tnd_fpga_atb_master_atbytes_i3, fabric_tnd_fpga_atb_master_atbytes_i4, fabric_tnd_fpga_atb_master_atdata_i1, fabric_tnd_fpga_atb_master_atdata_i2, fabric_tnd_fpga_atb_master_atdata_i3, fabric_tnd_fpga_atb_master_atdata_i4
-, fabric_tnd_fpga_atb_master_atdata_i5, fabric_tnd_fpga_atb_master_atdata_i6, fabric_tnd_fpga_atb_master_atdata_i7, fabric_tnd_fpga_atb_master_atdata_i8, fabric_tnd_fpga_atb_master_atdata_i9, fabric_tnd_fpga_atb_master_atdata_i10, fabric_tnd_fpga_atb_master_atdata_i11, fabric_tnd_fpga_atb_master_atdata_i12, fabric_tnd_fpga_atb_master_atdata_i13, fabric_tnd_fpga_atb_master_atdata_i14, fabric_tnd_fpga_atb_master_atdata_i15, fabric_tnd_fpga_atb_master_atdata_i16, fabric_tnd_fpga_atb_master_atdata_i17, fabric_tnd_fpga_atb_master_atdata_i18, fabric_tnd_fpga_atb_master_atdata_i19, fabric_tnd_fpga_atb_master_atdata_i20, fabric_tnd_fpga_atb_master_atdata_i21, fabric_tnd_fpga_atb_master_atdata_i22, fabric_tnd_fpga_atb_master_atdata_i23, fabric_tnd_fpga_atb_master_atdata_i24, fabric_tnd_fpga_atb_master_atdata_i25
-, fabric_tnd_fpga_atb_master_atdata_i26, fabric_tnd_fpga_atb_master_atdata_i27, fabric_tnd_fpga_atb_master_atdata_i28, fabric_tnd_fpga_atb_master_atdata_i29, fabric_tnd_fpga_atb_master_atdata_i30, fabric_tnd_fpga_atb_master_atdata_i31, fabric_tnd_fpga_atb_master_atdata_i32, fabric_tnd_fpga_atb_master_atdata_i33, fabric_tnd_fpga_atb_master_atdata_i34, fabric_tnd_fpga_atb_master_atdata_i35, fabric_tnd_fpga_atb_master_atdata_i36, fabric_tnd_fpga_atb_master_atdata_i37, fabric_tnd_fpga_atb_master_atdata_i38, fabric_tnd_fpga_atb_master_atdata_i39, fabric_tnd_fpga_atb_master_atdata_i40, fabric_tnd_fpga_atb_master_atdata_i41, fabric_tnd_fpga_atb_master_atdata_i42, fabric_tnd_fpga_atb_master_atdata_i43, fabric_tnd_fpga_atb_master_atdata_i44, fabric_tnd_fpga_atb_master_atdata_i45, fabric_tnd_fpga_atb_master_atdata_i46
-, fabric_tnd_fpga_atb_master_atdata_i47, fabric_tnd_fpga_atb_master_atdata_i48, fabric_tnd_fpga_atb_master_atdata_i49, fabric_tnd_fpga_atb_master_atdata_i50, fabric_tnd_fpga_atb_master_atdata_i51, fabric_tnd_fpga_atb_master_atdata_i52, fabric_tnd_fpga_atb_master_atdata_i53, fabric_tnd_fpga_atb_master_atdata_i54, fabric_tnd_fpga_atb_master_atdata_i55, fabric_tnd_fpga_atb_master_atdata_i56, fabric_tnd_fpga_atb_master_atdata_i57, fabric_tnd_fpga_atb_master_atdata_i58, fabric_tnd_fpga_atb_master_atdata_i59, fabric_tnd_fpga_atb_master_atdata_i60, fabric_tnd_fpga_atb_master_atdata_i61, fabric_tnd_fpga_atb_master_atdata_i62, fabric_tnd_fpga_atb_master_atdata_i63, fabric_tnd_fpga_atb_master_atdata_i64, fabric_tnd_fpga_atb_master_atdata_i65, fabric_tnd_fpga_atb_master_atdata_i66, fabric_tnd_fpga_atb_master_atdata_i67
-, fabric_tnd_fpga_atb_master_atdata_i68, fabric_tnd_fpga_atb_master_atdata_i69, fabric_tnd_fpga_atb_master_atdata_i70, fabric_tnd_fpga_atb_master_atdata_i71, fabric_tnd_fpga_atb_master_atdata_i72, fabric_tnd_fpga_atb_master_atdata_i73, fabric_tnd_fpga_atb_master_atdata_i74, fabric_tnd_fpga_atb_master_atdata_i75, fabric_tnd_fpga_atb_master_atdata_i76, fabric_tnd_fpga_atb_master_atdata_i77, fabric_tnd_fpga_atb_master_atdata_i78, fabric_tnd_fpga_atb_master_atdata_i79, fabric_tnd_fpga_atb_master_atdata_i80, fabric_tnd_fpga_atb_master_atdata_i81, fabric_tnd_fpga_atb_master_atdata_i82, fabric_tnd_fpga_atb_master_atdata_i83, fabric_tnd_fpga_atb_master_atdata_i84, fabric_tnd_fpga_atb_master_atdata_i85, fabric_tnd_fpga_atb_master_atdata_i86, fabric_tnd_fpga_atb_master_atdata_i87, fabric_tnd_fpga_atb_master_atdata_i88
-, fabric_tnd_fpga_atb_master_atdata_i89, fabric_tnd_fpga_atb_master_atdata_i90, fabric_tnd_fpga_atb_master_atdata_i91, fabric_tnd_fpga_atb_master_atdata_i92, fabric_tnd_fpga_atb_master_atdata_i93, fabric_tnd_fpga_atb_master_atdata_i94, fabric_tnd_fpga_atb_master_atdata_i95, fabric_tnd_fpga_atb_master_atdata_i96, fabric_tnd_fpga_atb_master_atdata_i97, fabric_tnd_fpga_atb_master_atdata_i98, fabric_tnd_fpga_atb_master_atdata_i99, fabric_tnd_fpga_atb_master_atdata_i100, fabric_tnd_fpga_atb_master_atdata_i101, fabric_tnd_fpga_atb_master_atdata_i102, fabric_tnd_fpga_atb_master_atdata_i103, fabric_tnd_fpga_atb_master_atdata_i104, fabric_tnd_fpga_atb_master_atdata_i105, fabric_tnd_fpga_atb_master_atdata_i106, fabric_tnd_fpga_atb_master_atdata_i107, fabric_tnd_fpga_atb_master_atdata_i108, fabric_tnd_fpga_atb_master_atdata_i109
-, fabric_tnd_fpga_atb_master_atdata_i110, fabric_tnd_fpga_atb_master_atdata_i111, fabric_tnd_fpga_atb_master_atdata_i112, fabric_tnd_fpga_atb_master_atdata_i113, fabric_tnd_fpga_atb_master_atdata_i114, fabric_tnd_fpga_atb_master_atdata_i115, fabric_tnd_fpga_atb_master_atdata_i116, fabric_tnd_fpga_atb_master_atdata_i117, fabric_tnd_fpga_atb_master_atdata_i118, fabric_tnd_fpga_atb_master_atdata_i119, fabric_tnd_fpga_atb_master_atdata_i120, fabric_tnd_fpga_atb_master_atdata_i121, fabric_tnd_fpga_atb_master_atdata_i122, fabric_tnd_fpga_atb_master_atdata_i123, fabric_tnd_fpga_atb_master_atdata_i124, fabric_tnd_fpga_atb_master_atdata_i125, fabric_tnd_fpga_atb_master_atdata_i126, fabric_tnd_fpga_atb_master_atdata_i127, fabric_tnd_fpga_atb_master_atdata_i128, fabric_tnd_fpga_atb_master_atid_i1, fabric_tnd_fpga_atb_master_atid_i2
-, fabric_tnd_fpga_atb_master_atid_i3, fabric_tnd_fpga_atb_master_atid_i4, fabric_tnd_fpga_atb_master_atid_i5, fabric_tnd_fpga_atb_master_atid_i6, fabric_tnd_fpga_atb_master_atid_i7, fabric_tnd_fpga_atb_master_atvalid_i, fabric_tnd_hssl_apb_master_prdata_i1, fabric_tnd_hssl_apb_master_prdata_i2, fabric_tnd_hssl_apb_master_prdata_i3, fabric_tnd_hssl_apb_master_prdata_i4, fabric_tnd_hssl_apb_master_prdata_i5, fabric_tnd_hssl_apb_master_prdata_i6, fabric_tnd_hssl_apb_master_prdata_i7, fabric_tnd_hssl_apb_master_prdata_i8, fabric_tnd_hssl_apb_master_prdata_i9, fabric_tnd_hssl_apb_master_prdata_i10, fabric_tnd_hssl_apb_master_prdata_i11, fabric_tnd_hssl_apb_master_prdata_i12, fabric_tnd_hssl_apb_master_prdata_i13, fabric_tnd_hssl_apb_master_prdata_i14, fabric_tnd_hssl_apb_master_prdata_i15
-, fabric_tnd_hssl_apb_master_prdata_i16, fabric_tnd_hssl_apb_master_prdata_i17, fabric_tnd_hssl_apb_master_prdata_i18, fabric_tnd_hssl_apb_master_prdata_i19, fabric_tnd_hssl_apb_master_prdata_i20, fabric_tnd_hssl_apb_master_prdata_i21, fabric_tnd_hssl_apb_master_prdata_i22, fabric_tnd_hssl_apb_master_prdata_i23, fabric_tnd_hssl_apb_master_prdata_i24, fabric_tnd_hssl_apb_master_prdata_i25, fabric_tnd_hssl_apb_master_prdata_i26, fabric_tnd_hssl_apb_master_prdata_i27, fabric_tnd_hssl_apb_master_prdata_i28, fabric_tnd_hssl_apb_master_prdata_i29, fabric_tnd_hssl_apb_master_prdata_i30, fabric_tnd_hssl_apb_master_prdata_i31, fabric_tnd_hssl_apb_master_prdata_i32, fabric_tnd_hssl_apb_master_pready_i, fabric_tnd_hssl_apb_master_pslverr_i, fabric_tnd_hssl_atb_master_afvalid_i, fabric_tnd_hssl_atb_master_atready_i
-, fabric_tnd_hssl_atb_master_syncreq_i, fabric_watchdog0_signal_0_o, fabric_watchdog0_signal_1_o, fabric_watchdog1_signal_0_o, fabric_watchdog1_signal_1_o, fabric_watchdog2_signal_0_o, fabric_watchdog2_signal_1_o, fabric_watchdog3_signal_0_o, fabric_watchdog3_signal_1_o, fabric_tst_pll_lock_o1, fabric_tst_pll_lock_o2, fabric_tst_pll_lock_o3, fabric_tst_pll_lock_o4, fabric_tst_pll_lock_o5, fabric_tst_pll_lock_o6, fabric_tst_pll_lock_o7, fabric_soc_mon_sensor_alarm_o, fabric_erom_fpga_cpu0_dbgen_i, fabric_erom_fpga_cpu0_hiden_i, fabric_erom_fpga_cpu0_hniden_i, fabric_erom_fpga_cpu0_niden_i
-, fabric_erom_fpga_cpu1_dbgen_i, fabric_erom_fpga_cpu1_hiden_i, fabric_erom_fpga_cpu1_hniden_i, fabric_erom_fpga_cpu1_niden_i, fabric_erom_fpga_cpu2_dbgen_i, fabric_erom_fpga_cpu2_hiden_i, fabric_erom_fpga_cpu2_hniden_i, fabric_erom_fpga_cpu2_niden_i, fabric_erom_fpga_cpu3_dbgen_i, fabric_erom_fpga_cpu3_hiden_i, fabric_erom_fpga_cpu3_hniden_i, fabric_erom_fpga_cpu3_niden_i, fabric_erom_fpga_cs_dbgen_i, fabric_erom_fpga_cs_niden_i, fabric_erom_fpga_cs_deviceen_i, fabric_erom_fpga_cs_rst_n_i, fabric_erom_fpga_debug_en_i, fabric_enable_TMR_i1, fabric_enable_TMR_i2, fabric_enable_TMR_i3, fabric_spw_interrupts_toggle_o1
-, fabric_spw_interrupts_toggle_o2, fabric_spw_interrupts_toggle_o3, fabric_spw_interrupts_o1, fabric_spw_interrupts_o2, fabric_spw_interrupts_o3, fabric_flash_irq_toggle_o, fabric_flash_irq_o, fabric_fpga_dma_hs_rstn_i1, fabric_fpga_dma_hs_rstn_i2, fabric_fpga_dma_hs_rstn_i3, fabric_fpga_dma_hs_rstn_i4, fabric_fpga_dma_hs_rstn_i5, fabric_fpga_dma_hs_rstn_i6);
-    input fabric_enable_TMR_i1;
-    input fabric_enable_TMR_i2;
-    input fabric_enable_TMR_i3;
-    input fabric_erom_fpga_cpu0_dbgen_i;
-    input fabric_erom_fpga_cpu0_hiden_i;
-    input fabric_erom_fpga_cpu0_hniden_i;
-    input fabric_erom_fpga_cpu0_niden_i;
-    input fabric_erom_fpga_cpu1_dbgen_i;
-    input fabric_erom_fpga_cpu1_hiden_i;
-    input fabric_erom_fpga_cpu1_hniden_i;
-    input fabric_erom_fpga_cpu1_niden_i;
-    input fabric_erom_fpga_cpu2_dbgen_i;
-    input fabric_erom_fpga_cpu2_hiden_i;
-    input fabric_erom_fpga_cpu2_hniden_i;
-    input fabric_erom_fpga_cpu2_niden_i;
-    input fabric_erom_fpga_cpu3_dbgen_i;
-    input fabric_erom_fpga_cpu3_hiden_i;
-    input fabric_erom_fpga_cpu3_hniden_i;
-    input fabric_erom_fpga_cpu3_niden_i;
-    input fabric_erom_fpga_cs_dbgen_i;
-    input fabric_erom_fpga_cs_deviceen_i;
-    input fabric_erom_fpga_cs_niden_i;
-    input fabric_erom_fpga_cs_rst_n_i;
-    input fabric_erom_fpga_debug_en_i;
-    output fabric_flash_irq_o;
-    output fabric_flash_irq_toggle_o;
-    input fabric_fpga_araddr_axi_m1_i1;
-    input fabric_fpga_araddr_axi_m1_i10;
-    input fabric_fpga_araddr_axi_m1_i11;
-    input fabric_fpga_araddr_axi_m1_i12;
-    input fabric_fpga_araddr_axi_m1_i13;
-    input fabric_fpga_araddr_axi_m1_i14;
-    input fabric_fpga_araddr_axi_m1_i15;
-    input fabric_fpga_araddr_axi_m1_i16;
-    input fabric_fpga_araddr_axi_m1_i17;
-    input fabric_fpga_araddr_axi_m1_i18;
-    input fabric_fpga_araddr_axi_m1_i19;
-    input fabric_fpga_araddr_axi_m1_i2;
-    input fabric_fpga_araddr_axi_m1_i20;
-    input fabric_fpga_araddr_axi_m1_i21;
-    input fabric_fpga_araddr_axi_m1_i22;
-    input fabric_fpga_araddr_axi_m1_i23;
-    input fabric_fpga_araddr_axi_m1_i24;
-    input fabric_fpga_araddr_axi_m1_i25;
-    input fabric_fpga_araddr_axi_m1_i26;
-    input fabric_fpga_araddr_axi_m1_i27;
-    input fabric_fpga_araddr_axi_m1_i28;
-    input fabric_fpga_araddr_axi_m1_i29;
-    input fabric_fpga_araddr_axi_m1_i3;
-    input fabric_fpga_araddr_axi_m1_i30;
-    input fabric_fpga_araddr_axi_m1_i31;
-    input fabric_fpga_araddr_axi_m1_i32;
-    input fabric_fpga_araddr_axi_m1_i33;
-    input fabric_fpga_araddr_axi_m1_i34;
-    input fabric_fpga_araddr_axi_m1_i35;
-    input fabric_fpga_araddr_axi_m1_i36;
-    input fabric_fpga_araddr_axi_m1_i37;
-    input fabric_fpga_araddr_axi_m1_i38;
-    input fabric_fpga_araddr_axi_m1_i39;
-    input fabric_fpga_araddr_axi_m1_i4;
-    input fabric_fpga_araddr_axi_m1_i40;
-    input fabric_fpga_araddr_axi_m1_i5;
-    input fabric_fpga_araddr_axi_m1_i6;
-    input fabric_fpga_araddr_axi_m1_i7;
-    input fabric_fpga_araddr_axi_m1_i8;
-    input fabric_fpga_araddr_axi_m1_i9;
-    input fabric_fpga_araddr_axi_m2_i1;
-    input fabric_fpga_araddr_axi_m2_i10;
-    input fabric_fpga_araddr_axi_m2_i11;
-    input fabric_fpga_araddr_axi_m2_i12;
-    input fabric_fpga_araddr_axi_m2_i13;
-    input fabric_fpga_araddr_axi_m2_i14;
-    input fabric_fpga_araddr_axi_m2_i15;
-    input fabric_fpga_araddr_axi_m2_i16;
-    input fabric_fpga_araddr_axi_m2_i17;
-    input fabric_fpga_araddr_axi_m2_i18;
-    input fabric_fpga_araddr_axi_m2_i19;
-    input fabric_fpga_araddr_axi_m2_i2;
-    input fabric_fpga_araddr_axi_m2_i20;
-    input fabric_fpga_araddr_axi_m2_i21;
-    input fabric_fpga_araddr_axi_m2_i22;
-    input fabric_fpga_araddr_axi_m2_i23;
-    input fabric_fpga_araddr_axi_m2_i24;
-    input fabric_fpga_araddr_axi_m2_i25;
-    input fabric_fpga_araddr_axi_m2_i26;
-    input fabric_fpga_araddr_axi_m2_i27;
-    input fabric_fpga_araddr_axi_m2_i28;
-    input fabric_fpga_araddr_axi_m2_i29;
-    input fabric_fpga_araddr_axi_m2_i3;
-    input fabric_fpga_araddr_axi_m2_i30;
-    input fabric_fpga_araddr_axi_m2_i31;
-    input fabric_fpga_araddr_axi_m2_i32;
-    input fabric_fpga_araddr_axi_m2_i33;
-    input fabric_fpga_araddr_axi_m2_i34;
-    input fabric_fpga_araddr_axi_m2_i35;
-    input fabric_fpga_araddr_axi_m2_i36;
-    input fabric_fpga_araddr_axi_m2_i37;
-    input fabric_fpga_araddr_axi_m2_i38;
-    input fabric_fpga_araddr_axi_m2_i39;
-    input fabric_fpga_araddr_axi_m2_i4;
-    input fabric_fpga_araddr_axi_m2_i40;
-    input fabric_fpga_araddr_axi_m2_i5;
-    input fabric_fpga_araddr_axi_m2_i6;
-    input fabric_fpga_araddr_axi_m2_i7;
-    input fabric_fpga_araddr_axi_m2_i8;
-    input fabric_fpga_araddr_axi_m2_i9;
-    output fabric_fpga_araddr_axi_s1_o1;
-    output fabric_fpga_araddr_axi_s1_o10;
-    output fabric_fpga_araddr_axi_s1_o11;
-    output fabric_fpga_araddr_axi_s1_o12;
-    output fabric_fpga_araddr_axi_s1_o13;
-    output fabric_fpga_araddr_axi_s1_o14;
-    output fabric_fpga_araddr_axi_s1_o15;
-    output fabric_fpga_araddr_axi_s1_o16;
-    output fabric_fpga_araddr_axi_s1_o17;
-    output fabric_fpga_araddr_axi_s1_o18;
-    output fabric_fpga_araddr_axi_s1_o19;
-    output fabric_fpga_araddr_axi_s1_o2;
-    output fabric_fpga_araddr_axi_s1_o20;
-    output fabric_fpga_araddr_axi_s1_o21;
-    output fabric_fpga_araddr_axi_s1_o22;
-    output fabric_fpga_araddr_axi_s1_o23;
-    output fabric_fpga_araddr_axi_s1_o24;
-    output fabric_fpga_araddr_axi_s1_o25;
-    output fabric_fpga_araddr_axi_s1_o26;
-    output fabric_fpga_araddr_axi_s1_o27;
-    output fabric_fpga_araddr_axi_s1_o28;
-    output fabric_fpga_araddr_axi_s1_o29;
-    output fabric_fpga_araddr_axi_s1_o3;
-    output fabric_fpga_araddr_axi_s1_o30;
-    output fabric_fpga_araddr_axi_s1_o31;
-    output fabric_fpga_araddr_axi_s1_o32;
-    output fabric_fpga_araddr_axi_s1_o33;
-    output fabric_fpga_araddr_axi_s1_o34;
-    output fabric_fpga_araddr_axi_s1_o35;
-    output fabric_fpga_araddr_axi_s1_o36;
-    output fabric_fpga_araddr_axi_s1_o37;
-    output fabric_fpga_araddr_axi_s1_o38;
-    output fabric_fpga_araddr_axi_s1_o39;
-    output fabric_fpga_araddr_axi_s1_o4;
-    output fabric_fpga_araddr_axi_s1_o40;
-    output fabric_fpga_araddr_axi_s1_o5;
-    output fabric_fpga_araddr_axi_s1_o6;
-    output fabric_fpga_araddr_axi_s1_o7;
-    output fabric_fpga_araddr_axi_s1_o8;
-    output fabric_fpga_araddr_axi_s1_o9;
-    output fabric_fpga_araddr_axi_s2_o1;
-    output fabric_fpga_araddr_axi_s2_o10;
-    output fabric_fpga_araddr_axi_s2_o11;
-    output fabric_fpga_araddr_axi_s2_o12;
-    output fabric_fpga_araddr_axi_s2_o13;
-    output fabric_fpga_araddr_axi_s2_o14;
-    output fabric_fpga_araddr_axi_s2_o15;
-    output fabric_fpga_araddr_axi_s2_o16;
-    output fabric_fpga_araddr_axi_s2_o17;
-    output fabric_fpga_araddr_axi_s2_o18;
-    output fabric_fpga_araddr_axi_s2_o19;
-    output fabric_fpga_araddr_axi_s2_o2;
-    output fabric_fpga_araddr_axi_s2_o20;
-    output fabric_fpga_araddr_axi_s2_o21;
-    output fabric_fpga_araddr_axi_s2_o22;
-    output fabric_fpga_araddr_axi_s2_o23;
-    output fabric_fpga_araddr_axi_s2_o24;
-    output fabric_fpga_araddr_axi_s2_o25;
-    output fabric_fpga_araddr_axi_s2_o26;
-    output fabric_fpga_araddr_axi_s2_o27;
-    output fabric_fpga_araddr_axi_s2_o28;
-    output fabric_fpga_araddr_axi_s2_o29;
-    output fabric_fpga_araddr_axi_s2_o3;
-    output fabric_fpga_araddr_axi_s2_o30;
-    output fabric_fpga_araddr_axi_s2_o31;
-    output fabric_fpga_araddr_axi_s2_o32;
-    output fabric_fpga_araddr_axi_s2_o33;
-    output fabric_fpga_araddr_axi_s2_o34;
-    output fabric_fpga_araddr_axi_s2_o35;
-    output fabric_fpga_araddr_axi_s2_o36;
-    output fabric_fpga_araddr_axi_s2_o37;
-    output fabric_fpga_araddr_axi_s2_o38;
-    output fabric_fpga_araddr_axi_s2_o39;
-    output fabric_fpga_araddr_axi_s2_o4;
-    output fabric_fpga_araddr_axi_s2_o40;
-    output fabric_fpga_araddr_axi_s2_o5;
-    output fabric_fpga_araddr_axi_s2_o6;
-    output fabric_fpga_araddr_axi_s2_o7;
-    output fabric_fpga_araddr_axi_s2_o8;
-    output fabric_fpga_araddr_axi_s2_o9;
-    input fabric_fpga_arburst_axi_m1_i1;
-    input fabric_fpga_arburst_axi_m1_i2;
-    input fabric_fpga_arburst_axi_m2_i1;
-    input fabric_fpga_arburst_axi_m2_i2;
-    output fabric_fpga_arburst_axi_s1_o1;
-    output fabric_fpga_arburst_axi_s1_o2;
-    output fabric_fpga_arburst_axi_s2_o1;
-    output fabric_fpga_arburst_axi_s2_o2;
-    input fabric_fpga_arcache_axi_m1_i1;
-    input fabric_fpga_arcache_axi_m1_i2;
-    input fabric_fpga_arcache_axi_m1_i3;
-    input fabric_fpga_arcache_axi_m1_i4;
-    input fabric_fpga_arcache_axi_m2_i1;
-    input fabric_fpga_arcache_axi_m2_i2;
-    input fabric_fpga_arcache_axi_m2_i3;
-    input fabric_fpga_arcache_axi_m2_i4;
-    output fabric_fpga_arcache_axi_s1_o1;
-    output fabric_fpga_arcache_axi_s1_o2;
-    output fabric_fpga_arcache_axi_s1_o3;
-    output fabric_fpga_arcache_axi_s1_o4;
-    output fabric_fpga_arcache_axi_s2_o1;
-    output fabric_fpga_arcache_axi_s2_o2;
-    output fabric_fpga_arcache_axi_s2_o3;
-    output fabric_fpga_arcache_axi_s2_o4;
-    input fabric_fpga_arid_axi_m1_i1;
-    input fabric_fpga_arid_axi_m1_i2;
-    input fabric_fpga_arid_axi_m1_i3;
-    input fabric_fpga_arid_axi_m1_i4;
-    input fabric_fpga_arid_axi_m1_i5;
-    input fabric_fpga_arid_axi_m2_i1;
-    input fabric_fpga_arid_axi_m2_i2;
-    input fabric_fpga_arid_axi_m2_i3;
-    input fabric_fpga_arid_axi_m2_i4;
-    input fabric_fpga_arid_axi_m2_i5;
-    output fabric_fpga_arid_axi_s1_o1;
-    output fabric_fpga_arid_axi_s1_o10;
-    output fabric_fpga_arid_axi_s1_o11;
-    output fabric_fpga_arid_axi_s1_o12;
-    output fabric_fpga_arid_axi_s1_o2;
-    output fabric_fpga_arid_axi_s1_o3;
-    output fabric_fpga_arid_axi_s1_o4;
-    output fabric_fpga_arid_axi_s1_o5;
-    output fabric_fpga_arid_axi_s1_o6;
-    output fabric_fpga_arid_axi_s1_o7;
-    output fabric_fpga_arid_axi_s1_o8;
-    output fabric_fpga_arid_axi_s1_o9;
-    output fabric_fpga_arid_axi_s2_o1;
-    output fabric_fpga_arid_axi_s2_o10;
-    output fabric_fpga_arid_axi_s2_o11;
-    output fabric_fpga_arid_axi_s2_o12;
-    output fabric_fpga_arid_axi_s2_o2;
-    output fabric_fpga_arid_axi_s2_o3;
-    output fabric_fpga_arid_axi_s2_o4;
-    output fabric_fpga_arid_axi_s2_o5;
-    output fabric_fpga_arid_axi_s2_o6;
-    output fabric_fpga_arid_axi_s2_o7;
-    output fabric_fpga_arid_axi_s2_o8;
-    output fabric_fpga_arid_axi_s2_o9;
-    input fabric_fpga_arlen_axi_m1_i1;
-    input fabric_fpga_arlen_axi_m1_i2;
-    input fabric_fpga_arlen_axi_m1_i3;
-    input fabric_fpga_arlen_axi_m1_i4;
-    input fabric_fpga_arlen_axi_m1_i5;
-    input fabric_fpga_arlen_axi_m1_i6;
-    input fabric_fpga_arlen_axi_m1_i7;
-    input fabric_fpga_arlen_axi_m1_i8;
-    input fabric_fpga_arlen_axi_m2_i1;
-    input fabric_fpga_arlen_axi_m2_i2;
-    input fabric_fpga_arlen_axi_m2_i3;
-    input fabric_fpga_arlen_axi_m2_i4;
-    input fabric_fpga_arlen_axi_m2_i5;
-    input fabric_fpga_arlen_axi_m2_i6;
-    input fabric_fpga_arlen_axi_m2_i7;
-    input fabric_fpga_arlen_axi_m2_i8;
-    output fabric_fpga_arlen_axi_s1_o1;
-    output fabric_fpga_arlen_axi_s1_o2;
-    output fabric_fpga_arlen_axi_s1_o3;
-    output fabric_fpga_arlen_axi_s1_o4;
-    output fabric_fpga_arlen_axi_s1_o5;
-    output fabric_fpga_arlen_axi_s1_o6;
-    output fabric_fpga_arlen_axi_s1_o7;
-    output fabric_fpga_arlen_axi_s1_o8;
-    output fabric_fpga_arlen_axi_s2_o1;
-    output fabric_fpga_arlen_axi_s2_o2;
-    output fabric_fpga_arlen_axi_s2_o3;
-    output fabric_fpga_arlen_axi_s2_o4;
-    output fabric_fpga_arlen_axi_s2_o5;
-    output fabric_fpga_arlen_axi_s2_o6;
-    output fabric_fpga_arlen_axi_s2_o7;
-    output fabric_fpga_arlen_axi_s2_o8;
-    input fabric_fpga_arlock_axi_m1_i;
-    input fabric_fpga_arlock_axi_m2_i;
-    output fabric_fpga_arlock_axi_s1_o;
-    output fabric_fpga_arlock_axi_s2_o;
-    input fabric_fpga_arprot_axi_m1_i1;
-    input fabric_fpga_arprot_axi_m1_i2;
-    input fabric_fpga_arprot_axi_m1_i3;
-    input fabric_fpga_arprot_axi_m2_i1;
-    input fabric_fpga_arprot_axi_m2_i2;
-    input fabric_fpga_arprot_axi_m2_i3;
-    output fabric_fpga_arprot_axi_s1_o1;
-    output fabric_fpga_arprot_axi_s1_o2;
-    output fabric_fpga_arprot_axi_s1_o3;
-    output fabric_fpga_arprot_axi_s2_o1;
-    output fabric_fpga_arprot_axi_s2_o2;
-    output fabric_fpga_arprot_axi_s2_o3;
-    input fabric_fpga_arqos_axi_m1_i1;
-    input fabric_fpga_arqos_axi_m1_i2;
-    input fabric_fpga_arqos_axi_m1_i3;
-    input fabric_fpga_arqos_axi_m1_i4;
-    input fabric_fpga_arqos_axi_m2_i1;
-    input fabric_fpga_arqos_axi_m2_i2;
-    input fabric_fpga_arqos_axi_m2_i3;
-    input fabric_fpga_arqos_axi_m2_i4;
-    output fabric_fpga_arqos_axi_s1_o1;
-    output fabric_fpga_arqos_axi_s1_o2;
-    output fabric_fpga_arqos_axi_s1_o3;
-    output fabric_fpga_arqos_axi_s1_o4;
-    output fabric_fpga_arqos_axi_s2_o1;
-    output fabric_fpga_arqos_axi_s2_o2;
-    output fabric_fpga_arqos_axi_s2_o3;
-    output fabric_fpga_arqos_axi_s2_o4;
-    output fabric_fpga_arready_axi_m1_o;
-    output fabric_fpga_arready_axi_m2_o;
-    input fabric_fpga_arready_axi_s1_i;
-    input fabric_fpga_arready_axi_s2_i;
-    output fabric_fpga_arregion_axi_s1_o1;
-    output fabric_fpga_arregion_axi_s1_o2;
-    output fabric_fpga_arregion_axi_s1_o3;
-    output fabric_fpga_arregion_axi_s1_o4;
-    output fabric_fpga_arregion_axi_s2_o1;
-    output fabric_fpga_arregion_axi_s2_o2;
-    output fabric_fpga_arregion_axi_s2_o3;
-    output fabric_fpga_arregion_axi_s2_o4;
-    input fabric_fpga_arsize_axi_m1_i1;
-    input fabric_fpga_arsize_axi_m1_i2;
-    input fabric_fpga_arsize_axi_m1_i3;
-    input fabric_fpga_arsize_axi_m2_i1;
-    input fabric_fpga_arsize_axi_m2_i2;
-    input fabric_fpga_arsize_axi_m2_i3;
-    output fabric_fpga_arsize_axi_s1_o1;
-    output fabric_fpga_arsize_axi_s1_o2;
-    output fabric_fpga_arsize_axi_s1_o3;
-    output fabric_fpga_arsize_axi_s2_o1;
-    output fabric_fpga_arsize_axi_s2_o2;
-    output fabric_fpga_arsize_axi_s2_o3;
-    input fabric_fpga_arvalid_axi_m1_i;
-    input fabric_fpga_arvalid_axi_m2_i;
-    output fabric_fpga_arvalid_axi_s1_o;
-    output fabric_fpga_arvalid_axi_s2_o;
-    input fabric_fpga_awaddr_axi_m1_i1;
-    input fabric_fpga_awaddr_axi_m1_i10;
-    input fabric_fpga_awaddr_axi_m1_i11;
-    input fabric_fpga_awaddr_axi_m1_i12;
-    input fabric_fpga_awaddr_axi_m1_i13;
-    input fabric_fpga_awaddr_axi_m1_i14;
-    input fabric_fpga_awaddr_axi_m1_i15;
-    input fabric_fpga_awaddr_axi_m1_i16;
-    input fabric_fpga_awaddr_axi_m1_i17;
-    input fabric_fpga_awaddr_axi_m1_i18;
-    input fabric_fpga_awaddr_axi_m1_i19;
-    input fabric_fpga_awaddr_axi_m1_i2;
-    input fabric_fpga_awaddr_axi_m1_i20;
-    input fabric_fpga_awaddr_axi_m1_i21;
-    input fabric_fpga_awaddr_axi_m1_i22;
-    input fabric_fpga_awaddr_axi_m1_i23;
-    input fabric_fpga_awaddr_axi_m1_i24;
-    input fabric_fpga_awaddr_axi_m1_i25;
-    input fabric_fpga_awaddr_axi_m1_i26;
-    input fabric_fpga_awaddr_axi_m1_i27;
-    input fabric_fpga_awaddr_axi_m1_i28;
-    input fabric_fpga_awaddr_axi_m1_i29;
-    input fabric_fpga_awaddr_axi_m1_i3;
-    input fabric_fpga_awaddr_axi_m1_i30;
-    input fabric_fpga_awaddr_axi_m1_i31;
-    input fabric_fpga_awaddr_axi_m1_i32;
-    input fabric_fpga_awaddr_axi_m1_i33;
-    input fabric_fpga_awaddr_axi_m1_i34;
-    input fabric_fpga_awaddr_axi_m1_i35;
-    input fabric_fpga_awaddr_axi_m1_i36;
-    input fabric_fpga_awaddr_axi_m1_i37;
-    input fabric_fpga_awaddr_axi_m1_i38;
-    input fabric_fpga_awaddr_axi_m1_i39;
-    input fabric_fpga_awaddr_axi_m1_i4;
-    input fabric_fpga_awaddr_axi_m1_i40;
-    input fabric_fpga_awaddr_axi_m1_i5;
-    input fabric_fpga_awaddr_axi_m1_i6;
-    input fabric_fpga_awaddr_axi_m1_i7;
-    input fabric_fpga_awaddr_axi_m1_i8;
-    input fabric_fpga_awaddr_axi_m1_i9;
-    input fabric_fpga_awaddr_axi_m2_i1;
-    input fabric_fpga_awaddr_axi_m2_i10;
-    input fabric_fpga_awaddr_axi_m2_i11;
-    input fabric_fpga_awaddr_axi_m2_i12;
-    input fabric_fpga_awaddr_axi_m2_i13;
-    input fabric_fpga_awaddr_axi_m2_i14;
-    input fabric_fpga_awaddr_axi_m2_i15;
-    input fabric_fpga_awaddr_axi_m2_i16;
-    input fabric_fpga_awaddr_axi_m2_i17;
-    input fabric_fpga_awaddr_axi_m2_i18;
-    input fabric_fpga_awaddr_axi_m2_i19;
-    input fabric_fpga_awaddr_axi_m2_i2;
-    input fabric_fpga_awaddr_axi_m2_i20;
-    input fabric_fpga_awaddr_axi_m2_i21;
-    input fabric_fpga_awaddr_axi_m2_i22;
-    input fabric_fpga_awaddr_axi_m2_i23;
-    input fabric_fpga_awaddr_axi_m2_i24;
-    input fabric_fpga_awaddr_axi_m2_i25;
-    input fabric_fpga_awaddr_axi_m2_i26;
-    input fabric_fpga_awaddr_axi_m2_i27;
-    input fabric_fpga_awaddr_axi_m2_i28;
-    input fabric_fpga_awaddr_axi_m2_i29;
-    input fabric_fpga_awaddr_axi_m2_i3;
-    input fabric_fpga_awaddr_axi_m2_i30;
-    input fabric_fpga_awaddr_axi_m2_i31;
-    input fabric_fpga_awaddr_axi_m2_i32;
-    input fabric_fpga_awaddr_axi_m2_i33;
-    input fabric_fpga_awaddr_axi_m2_i34;
-    input fabric_fpga_awaddr_axi_m2_i35;
-    input fabric_fpga_awaddr_axi_m2_i36;
-    input fabric_fpga_awaddr_axi_m2_i37;
-    input fabric_fpga_awaddr_axi_m2_i38;
-    input fabric_fpga_awaddr_axi_m2_i39;
-    input fabric_fpga_awaddr_axi_m2_i4;
-    input fabric_fpga_awaddr_axi_m2_i40;
-    input fabric_fpga_awaddr_axi_m2_i5;
-    input fabric_fpga_awaddr_axi_m2_i6;
-    input fabric_fpga_awaddr_axi_m2_i7;
-    input fabric_fpga_awaddr_axi_m2_i8;
-    input fabric_fpga_awaddr_axi_m2_i9;
-    output fabric_fpga_awaddr_axi_s1_o1;
-    output fabric_fpga_awaddr_axi_s1_o10;
-    output fabric_fpga_awaddr_axi_s1_o11;
-    output fabric_fpga_awaddr_axi_s1_o12;
-    output fabric_fpga_awaddr_axi_s1_o13;
-    output fabric_fpga_awaddr_axi_s1_o14;
-    output fabric_fpga_awaddr_axi_s1_o15;
-    output fabric_fpga_awaddr_axi_s1_o16;
-    output fabric_fpga_awaddr_axi_s1_o17;
-    output fabric_fpga_awaddr_axi_s1_o18;
-    output fabric_fpga_awaddr_axi_s1_o19;
-    output fabric_fpga_awaddr_axi_s1_o2;
-    output fabric_fpga_awaddr_axi_s1_o20;
-    output fabric_fpga_awaddr_axi_s1_o21;
-    output fabric_fpga_awaddr_axi_s1_o22;
-    output fabric_fpga_awaddr_axi_s1_o23;
-    output fabric_fpga_awaddr_axi_s1_o24;
-    output fabric_fpga_awaddr_axi_s1_o25;
-    output fabric_fpga_awaddr_axi_s1_o26;
-    output fabric_fpga_awaddr_axi_s1_o27;
-    output fabric_fpga_awaddr_axi_s1_o28;
-    output fabric_fpga_awaddr_axi_s1_o29;
-    output fabric_fpga_awaddr_axi_s1_o3;
-    output fabric_fpga_awaddr_axi_s1_o30;
-    output fabric_fpga_awaddr_axi_s1_o31;
-    output fabric_fpga_awaddr_axi_s1_o32;
-    output fabric_fpga_awaddr_axi_s1_o33;
-    output fabric_fpga_awaddr_axi_s1_o34;
-    output fabric_fpga_awaddr_axi_s1_o35;
-    output fabric_fpga_awaddr_axi_s1_o36;
-    output fabric_fpga_awaddr_axi_s1_o37;
-    output fabric_fpga_awaddr_axi_s1_o38;
-    output fabric_fpga_awaddr_axi_s1_o39;
-    output fabric_fpga_awaddr_axi_s1_o4;
-    output fabric_fpga_awaddr_axi_s1_o40;
-    output fabric_fpga_awaddr_axi_s1_o5;
-    output fabric_fpga_awaddr_axi_s1_o6;
-    output fabric_fpga_awaddr_axi_s1_o7;
-    output fabric_fpga_awaddr_axi_s1_o8;
-    output fabric_fpga_awaddr_axi_s1_o9;
-    output fabric_fpga_awaddr_axi_s2_o1;
-    output fabric_fpga_awaddr_axi_s2_o10;
-    output fabric_fpga_awaddr_axi_s2_o11;
-    output fabric_fpga_awaddr_axi_s2_o12;
-    output fabric_fpga_awaddr_axi_s2_o13;
-    output fabric_fpga_awaddr_axi_s2_o14;
-    output fabric_fpga_awaddr_axi_s2_o15;
-    output fabric_fpga_awaddr_axi_s2_o16;
-    output fabric_fpga_awaddr_axi_s2_o17;
-    output fabric_fpga_awaddr_axi_s2_o18;
-    output fabric_fpga_awaddr_axi_s2_o19;
-    output fabric_fpga_awaddr_axi_s2_o2;
-    output fabric_fpga_awaddr_axi_s2_o20;
-    output fabric_fpga_awaddr_axi_s2_o21;
-    output fabric_fpga_awaddr_axi_s2_o22;
-    output fabric_fpga_awaddr_axi_s2_o23;
-    output fabric_fpga_awaddr_axi_s2_o24;
-    output fabric_fpga_awaddr_axi_s2_o25;
-    output fabric_fpga_awaddr_axi_s2_o26;
-    output fabric_fpga_awaddr_axi_s2_o27;
-    output fabric_fpga_awaddr_axi_s2_o28;
-    output fabric_fpga_awaddr_axi_s2_o29;
-    output fabric_fpga_awaddr_axi_s2_o3;
-    output fabric_fpga_awaddr_axi_s2_o30;
-    output fabric_fpga_awaddr_axi_s2_o31;
-    output fabric_fpga_awaddr_axi_s2_o32;
-    output fabric_fpga_awaddr_axi_s2_o33;
-    output fabric_fpga_awaddr_axi_s2_o34;
-    output fabric_fpga_awaddr_axi_s2_o35;
-    output fabric_fpga_awaddr_axi_s2_o36;
-    output fabric_fpga_awaddr_axi_s2_o37;
-    output fabric_fpga_awaddr_axi_s2_o38;
-    output fabric_fpga_awaddr_axi_s2_o39;
-    output fabric_fpga_awaddr_axi_s2_o4;
-    output fabric_fpga_awaddr_axi_s2_o40;
-    output fabric_fpga_awaddr_axi_s2_o5;
-    output fabric_fpga_awaddr_axi_s2_o6;
-    output fabric_fpga_awaddr_axi_s2_o7;
-    output fabric_fpga_awaddr_axi_s2_o8;
-    output fabric_fpga_awaddr_axi_s2_o9;
-    input fabric_fpga_awburst_axi_m1_i1;
-    input fabric_fpga_awburst_axi_m1_i2;
-    input fabric_fpga_awburst_axi_m2_i1;
-    input fabric_fpga_awburst_axi_m2_i2;
-    output fabric_fpga_awburst_axi_s1_o1;
-    output fabric_fpga_awburst_axi_s1_o2;
-    output fabric_fpga_awburst_axi_s2_o1;
-    output fabric_fpga_awburst_axi_s2_o2;
-    input fabric_fpga_awcache_axi_m1_i1;
-    input fabric_fpga_awcache_axi_m1_i2;
-    input fabric_fpga_awcache_axi_m1_i3;
-    input fabric_fpga_awcache_axi_m1_i4;
-    input fabric_fpga_awcache_axi_m2_i1;
-    input fabric_fpga_awcache_axi_m2_i2;
-    input fabric_fpga_awcache_axi_m2_i3;
-    input fabric_fpga_awcache_axi_m2_i4;
-    output fabric_fpga_awcache_axi_s1_o1;
-    output fabric_fpga_awcache_axi_s1_o2;
-    output fabric_fpga_awcache_axi_s1_o3;
-    output fabric_fpga_awcache_axi_s1_o4;
-    output fabric_fpga_awcache_axi_s2_o1;
-    output fabric_fpga_awcache_axi_s2_o2;
-    output fabric_fpga_awcache_axi_s2_o3;
-    output fabric_fpga_awcache_axi_s2_o4;
-    input fabric_fpga_awid_axi_m1_i1;
-    input fabric_fpga_awid_axi_m1_i2;
-    input fabric_fpga_awid_axi_m1_i3;
-    input fabric_fpga_awid_axi_m1_i4;
-    input fabric_fpga_awid_axi_m1_i5;
-    input fabric_fpga_awid_axi_m2_i1;
-    input fabric_fpga_awid_axi_m2_i2;
-    input fabric_fpga_awid_axi_m2_i3;
-    input fabric_fpga_awid_axi_m2_i4;
-    input fabric_fpga_awid_axi_m2_i5;
-    output fabric_fpga_awid_axi_s1_o1;
-    output fabric_fpga_awid_axi_s1_o10;
-    output fabric_fpga_awid_axi_s1_o11;
-    output fabric_fpga_awid_axi_s1_o12;
-    output fabric_fpga_awid_axi_s1_o2;
-    output fabric_fpga_awid_axi_s1_o3;
-    output fabric_fpga_awid_axi_s1_o4;
-    output fabric_fpga_awid_axi_s1_o5;
-    output fabric_fpga_awid_axi_s1_o6;
-    output fabric_fpga_awid_axi_s1_o7;
-    output fabric_fpga_awid_axi_s1_o8;
-    output fabric_fpga_awid_axi_s1_o9;
-    output fabric_fpga_awid_axi_s2_o1;
-    output fabric_fpga_awid_axi_s2_o10;
-    output fabric_fpga_awid_axi_s2_o11;
-    output fabric_fpga_awid_axi_s2_o12;
-    output fabric_fpga_awid_axi_s2_o2;
-    output fabric_fpga_awid_axi_s2_o3;
-    output fabric_fpga_awid_axi_s2_o4;
-    output fabric_fpga_awid_axi_s2_o5;
-    output fabric_fpga_awid_axi_s2_o6;
-    output fabric_fpga_awid_axi_s2_o7;
-    output fabric_fpga_awid_axi_s2_o8;
-    output fabric_fpga_awid_axi_s2_o9;
-    input fabric_fpga_awlen_axi_m1_i1;
-    input fabric_fpga_awlen_axi_m1_i2;
-    input fabric_fpga_awlen_axi_m1_i3;
-    input fabric_fpga_awlen_axi_m1_i4;
-    input fabric_fpga_awlen_axi_m1_i5;
-    input fabric_fpga_awlen_axi_m1_i6;
-    input fabric_fpga_awlen_axi_m1_i7;
-    input fabric_fpga_awlen_axi_m1_i8;
-    input fabric_fpga_awlen_axi_m2_i1;
-    input fabric_fpga_awlen_axi_m2_i2;
-    input fabric_fpga_awlen_axi_m2_i3;
-    input fabric_fpga_awlen_axi_m2_i4;
-    input fabric_fpga_awlen_axi_m2_i5;
-    input fabric_fpga_awlen_axi_m2_i6;
-    input fabric_fpga_awlen_axi_m2_i7;
-    input fabric_fpga_awlen_axi_m2_i8;
-    output fabric_fpga_awlen_axi_s1_o1;
-    output fabric_fpga_awlen_axi_s1_o2;
-    output fabric_fpga_awlen_axi_s1_o3;
-    output fabric_fpga_awlen_axi_s1_o4;
-    output fabric_fpga_awlen_axi_s1_o5;
-    output fabric_fpga_awlen_axi_s1_o6;
-    output fabric_fpga_awlen_axi_s1_o7;
-    output fabric_fpga_awlen_axi_s1_o8;
-    output fabric_fpga_awlen_axi_s2_o1;
-    output fabric_fpga_awlen_axi_s2_o2;
-    output fabric_fpga_awlen_axi_s2_o3;
-    output fabric_fpga_awlen_axi_s2_o4;
-    output fabric_fpga_awlen_axi_s2_o5;
-    output fabric_fpga_awlen_axi_s2_o6;
-    output fabric_fpga_awlen_axi_s2_o7;
-    output fabric_fpga_awlen_axi_s2_o8;
-    input fabric_fpga_awlock_axi_m1_i;
-    input fabric_fpga_awlock_axi_m2_i;
-    output fabric_fpga_awlock_axi_s1_o;
-    output fabric_fpga_awlock_axi_s2_o;
-    input fabric_fpga_awprot_axi_m1_i1;
-    input fabric_fpga_awprot_axi_m1_i2;
-    input fabric_fpga_awprot_axi_m1_i3;
-    input fabric_fpga_awprot_axi_m2_i1;
-    input fabric_fpga_awprot_axi_m2_i2;
-    input fabric_fpga_awprot_axi_m2_i3;
-    output fabric_fpga_awprot_axi_s1_o1;
-    output fabric_fpga_awprot_axi_s1_o2;
-    output fabric_fpga_awprot_axi_s1_o3;
-    output fabric_fpga_awprot_axi_s2_o1;
-    output fabric_fpga_awprot_axi_s2_o2;
-    output fabric_fpga_awprot_axi_s2_o3;
-    input fabric_fpga_awqos_axi_m1_i1;
-    input fabric_fpga_awqos_axi_m1_i2;
-    input fabric_fpga_awqos_axi_m1_i3;
-    input fabric_fpga_awqos_axi_m1_i4;
-    input fabric_fpga_awqos_axi_m2_i1;
-    input fabric_fpga_awqos_axi_m2_i2;
-    input fabric_fpga_awqos_axi_m2_i3;
-    input fabric_fpga_awqos_axi_m2_i4;
-    output fabric_fpga_awqos_axi_s1_o1;
-    output fabric_fpga_awqos_axi_s1_o2;
-    output fabric_fpga_awqos_axi_s1_o3;
-    output fabric_fpga_awqos_axi_s1_o4;
-    output fabric_fpga_awqos_axi_s2_o1;
-    output fabric_fpga_awqos_axi_s2_o2;
-    output fabric_fpga_awqos_axi_s2_o3;
-    output fabric_fpga_awqos_axi_s2_o4;
-    output fabric_fpga_awready_axi_m1_o;
-    output fabric_fpga_awready_axi_m2_o;
-    input fabric_fpga_awready_axi_s1_i;
-    input fabric_fpga_awready_axi_s2_i;
-    output fabric_fpga_awregion_axi_s1_o1;
-    output fabric_fpga_awregion_axi_s1_o2;
-    output fabric_fpga_awregion_axi_s1_o3;
-    output fabric_fpga_awregion_axi_s1_o4;
-    output fabric_fpga_awregion_axi_s2_o1;
-    output fabric_fpga_awregion_axi_s2_o2;
-    output fabric_fpga_awregion_axi_s2_o3;
-    output fabric_fpga_awregion_axi_s2_o4;
-    input fabric_fpga_awsize_axi_m1_i1;
-    input fabric_fpga_awsize_axi_m1_i2;
-    input fabric_fpga_awsize_axi_m1_i3;
-    input fabric_fpga_awsize_axi_m2_i1;
-    input fabric_fpga_awsize_axi_m2_i2;
-    input fabric_fpga_awsize_axi_m2_i3;
-    output fabric_fpga_awsize_axi_s1_o1;
-    output fabric_fpga_awsize_axi_s1_o2;
-    output fabric_fpga_awsize_axi_s1_o3;
-    output fabric_fpga_awsize_axi_s2_o1;
-    output fabric_fpga_awsize_axi_s2_o2;
-    output fabric_fpga_awsize_axi_s2_o3;
-    input fabric_fpga_awvalid_axi_m1_i;
-    input fabric_fpga_awvalid_axi_m2_i;
-    output fabric_fpga_awvalid_axi_s1_o;
-    output fabric_fpga_awvalid_axi_s2_o;
-    output fabric_fpga_bid_axi_m1_o1;
-    output fabric_fpga_bid_axi_m1_o2;
-    output fabric_fpga_bid_axi_m1_o3;
-    output fabric_fpga_bid_axi_m1_o4;
-    output fabric_fpga_bid_axi_m1_o5;
-    output fabric_fpga_bid_axi_m2_o1;
-    output fabric_fpga_bid_axi_m2_o2;
-    output fabric_fpga_bid_axi_m2_o3;
-    output fabric_fpga_bid_axi_m2_o4;
-    output fabric_fpga_bid_axi_m2_o5;
-    input fabric_fpga_bid_axi_s1_i1;
-    input fabric_fpga_bid_axi_s1_i10;
-    input fabric_fpga_bid_axi_s1_i11;
-    input fabric_fpga_bid_axi_s1_i12;
-    input fabric_fpga_bid_axi_s1_i2;
-    input fabric_fpga_bid_axi_s1_i3;
-    input fabric_fpga_bid_axi_s1_i4;
-    input fabric_fpga_bid_axi_s1_i5;
-    input fabric_fpga_bid_axi_s1_i6;
-    input fabric_fpga_bid_axi_s1_i7;
-    input fabric_fpga_bid_axi_s1_i8;
-    input fabric_fpga_bid_axi_s1_i9;
-    input fabric_fpga_bid_axi_s2_i1;
-    input fabric_fpga_bid_axi_s2_i10;
-    input fabric_fpga_bid_axi_s2_i11;
-    input fabric_fpga_bid_axi_s2_i12;
-    input fabric_fpga_bid_axi_s2_i2;
-    input fabric_fpga_bid_axi_s2_i3;
-    input fabric_fpga_bid_axi_s2_i4;
-    input fabric_fpga_bid_axi_s2_i5;
-    input fabric_fpga_bid_axi_s2_i6;
-    input fabric_fpga_bid_axi_s2_i7;
-    input fabric_fpga_bid_axi_s2_i8;
-    input fabric_fpga_bid_axi_s2_i9;
-    input fabric_fpga_bready_axi_m1_i;
-    input fabric_fpga_bready_axi_m2_i;
-    output fabric_fpga_bready_axi_s1_o;
-    output fabric_fpga_bready_axi_s2_o;
-    output fabric_fpga_bresp_axi_m1_o1;
-    output fabric_fpga_bresp_axi_m1_o2;
-    output fabric_fpga_bresp_axi_m2_o1;
-    output fabric_fpga_bresp_axi_m2_o2;
-    input fabric_fpga_bresp_axi_s1_i1;
-    input fabric_fpga_bresp_axi_s1_i2;
-    input fabric_fpga_bresp_axi_s2_i1;
-    input fabric_fpga_bresp_axi_s2_i2;
-    output fabric_fpga_bvalid_axi_m1_o;
-    output fabric_fpga_bvalid_axi_m2_o;
-    input fabric_fpga_bvalid_axi_s1_i;
-    input fabric_fpga_bvalid_axi_s2_i;
-    input fabric_fpga_ddr0_araddr_i1;
-    input fabric_fpga_ddr0_araddr_i10;
-    input fabric_fpga_ddr0_araddr_i11;
-    input fabric_fpga_ddr0_araddr_i12;
-    input fabric_fpga_ddr0_araddr_i13;
-    input fabric_fpga_ddr0_araddr_i14;
-    input fabric_fpga_ddr0_araddr_i15;
-    input fabric_fpga_ddr0_araddr_i16;
-    input fabric_fpga_ddr0_araddr_i17;
-    input fabric_fpga_ddr0_araddr_i18;
-    input fabric_fpga_ddr0_araddr_i19;
-    input fabric_fpga_ddr0_araddr_i2;
-    input fabric_fpga_ddr0_araddr_i20;
-    input fabric_fpga_ddr0_araddr_i21;
-    input fabric_fpga_ddr0_araddr_i22;
-    input fabric_fpga_ddr0_araddr_i23;
-    input fabric_fpga_ddr0_araddr_i24;
-    input fabric_fpga_ddr0_araddr_i25;
-    input fabric_fpga_ddr0_araddr_i26;
-    input fabric_fpga_ddr0_araddr_i27;
-    input fabric_fpga_ddr0_araddr_i28;
-    input fabric_fpga_ddr0_araddr_i29;
-    input fabric_fpga_ddr0_araddr_i3;
-    input fabric_fpga_ddr0_araddr_i30;
-    input fabric_fpga_ddr0_araddr_i31;
-    input fabric_fpga_ddr0_araddr_i32;
-    input fabric_fpga_ddr0_araddr_i33;
-    input fabric_fpga_ddr0_araddr_i34;
-    input fabric_fpga_ddr0_araddr_i35;
-    input fabric_fpga_ddr0_araddr_i36;
-    input fabric_fpga_ddr0_araddr_i37;
-    input fabric_fpga_ddr0_araddr_i38;
-    input fabric_fpga_ddr0_araddr_i39;
-    input fabric_fpga_ddr0_araddr_i4;
-    input fabric_fpga_ddr0_araddr_i40;
-    input fabric_fpga_ddr0_araddr_i5;
-    input fabric_fpga_ddr0_araddr_i6;
-    input fabric_fpga_ddr0_araddr_i7;
-    input fabric_fpga_ddr0_araddr_i8;
-    input fabric_fpga_ddr0_araddr_i9;
-    input fabric_fpga_ddr0_arburst_i1;
-    input fabric_fpga_ddr0_arburst_i2;
-    input fabric_fpga_ddr0_arcache_i1;
-    input fabric_fpga_ddr0_arcache_i2;
-    input fabric_fpga_ddr0_arcache_i3;
-    input fabric_fpga_ddr0_arcache_i4;
-    input fabric_fpga_ddr0_arid_i1;
-    input fabric_fpga_ddr0_arid_i2;
-    input fabric_fpga_ddr0_arid_i3;
-    input fabric_fpga_ddr0_arid_i4;
-    input fabric_fpga_ddr0_arid_i5;
-    input fabric_fpga_ddr0_arlen_i1;
-    input fabric_fpga_ddr0_arlen_i2;
-    input fabric_fpga_ddr0_arlen_i3;
-    input fabric_fpga_ddr0_arlen_i4;
-    input fabric_fpga_ddr0_arlen_i5;
-    input fabric_fpga_ddr0_arlen_i6;
-    input fabric_fpga_ddr0_arlen_i7;
-    input fabric_fpga_ddr0_arlen_i8;
-    input fabric_fpga_ddr0_arlock_i;
-    input fabric_fpga_ddr0_arprot_i1;
-    input fabric_fpga_ddr0_arprot_i2;
-    input fabric_fpga_ddr0_arprot_i3;
-    input fabric_fpga_ddr0_arqos_i1;
-    input fabric_fpga_ddr0_arqos_i2;
-    input fabric_fpga_ddr0_arqos_i3;
-    input fabric_fpga_ddr0_arqos_i4;
-    output fabric_fpga_ddr0_arready_o;
-    input fabric_fpga_ddr0_arsize_i1;
-    input fabric_fpga_ddr0_arsize_i2;
-    input fabric_fpga_ddr0_arsize_i3;
-    input fabric_fpga_ddr0_arvalid_i;
-    input fabric_fpga_ddr0_awaddr_i1;
-    input fabric_fpga_ddr0_awaddr_i10;
-    input fabric_fpga_ddr0_awaddr_i11;
-    input fabric_fpga_ddr0_awaddr_i12;
-    input fabric_fpga_ddr0_awaddr_i13;
-    input fabric_fpga_ddr0_awaddr_i14;
-    input fabric_fpga_ddr0_awaddr_i15;
-    input fabric_fpga_ddr0_awaddr_i16;
-    input fabric_fpga_ddr0_awaddr_i17;
-    input fabric_fpga_ddr0_awaddr_i18;
-    input fabric_fpga_ddr0_awaddr_i19;
-    input fabric_fpga_ddr0_awaddr_i2;
-    input fabric_fpga_ddr0_awaddr_i20;
-    input fabric_fpga_ddr0_awaddr_i21;
-    input fabric_fpga_ddr0_awaddr_i22;
-    input fabric_fpga_ddr0_awaddr_i23;
-    input fabric_fpga_ddr0_awaddr_i24;
-    input fabric_fpga_ddr0_awaddr_i25;
-    input fabric_fpga_ddr0_awaddr_i26;
-    input fabric_fpga_ddr0_awaddr_i27;
-    input fabric_fpga_ddr0_awaddr_i28;
-    input fabric_fpga_ddr0_awaddr_i29;
-    input fabric_fpga_ddr0_awaddr_i3;
-    input fabric_fpga_ddr0_awaddr_i30;
-    input fabric_fpga_ddr0_awaddr_i31;
-    input fabric_fpga_ddr0_awaddr_i32;
-    input fabric_fpga_ddr0_awaddr_i33;
-    input fabric_fpga_ddr0_awaddr_i34;
-    input fabric_fpga_ddr0_awaddr_i35;
-    input fabric_fpga_ddr0_awaddr_i36;
-    input fabric_fpga_ddr0_awaddr_i37;
-    input fabric_fpga_ddr0_awaddr_i38;
-    input fabric_fpga_ddr0_awaddr_i39;
-    input fabric_fpga_ddr0_awaddr_i4;
-    input fabric_fpga_ddr0_awaddr_i40;
-    input fabric_fpga_ddr0_awaddr_i5;
-    input fabric_fpga_ddr0_awaddr_i6;
-    input fabric_fpga_ddr0_awaddr_i7;
-    input fabric_fpga_ddr0_awaddr_i8;
-    input fabric_fpga_ddr0_awaddr_i9;
-    input fabric_fpga_ddr0_awburst_i1;
-    input fabric_fpga_ddr0_awburst_i2;
-    input fabric_fpga_ddr0_awcache_i1;
-    input fabric_fpga_ddr0_awcache_i2;
-    input fabric_fpga_ddr0_awcache_i3;
-    input fabric_fpga_ddr0_awcache_i4;
-    input fabric_fpga_ddr0_awid_i1;
-    input fabric_fpga_ddr0_awid_i2;
-    input fabric_fpga_ddr0_awid_i3;
-    input fabric_fpga_ddr0_awid_i4;
-    input fabric_fpga_ddr0_awid_i5;
-    input fabric_fpga_ddr0_awlen_i1;
-    input fabric_fpga_ddr0_awlen_i2;
-    input fabric_fpga_ddr0_awlen_i3;
-    input fabric_fpga_ddr0_awlen_i4;
-    input fabric_fpga_ddr0_awlen_i5;
-    input fabric_fpga_ddr0_awlen_i6;
-    input fabric_fpga_ddr0_awlen_i7;
-    input fabric_fpga_ddr0_awlen_i8;
-    input fabric_fpga_ddr0_awlock_i;
-    input fabric_fpga_ddr0_awprot_i1;
-    input fabric_fpga_ddr0_awprot_i2;
-    input fabric_fpga_ddr0_awprot_i3;
-    input fabric_fpga_ddr0_awqos_i1;
-    input fabric_fpga_ddr0_awqos_i2;
-    input fabric_fpga_ddr0_awqos_i3;
-    input fabric_fpga_ddr0_awqos_i4;
-    output fabric_fpga_ddr0_awready_o;
-    input fabric_fpga_ddr0_awsize_i1;
-    input fabric_fpga_ddr0_awsize_i2;
-    input fabric_fpga_ddr0_awsize_i3;
-    input fabric_fpga_ddr0_awvalid_i;
-    output fabric_fpga_ddr0_bid_o1;
-    output fabric_fpga_ddr0_bid_o2;
-    output fabric_fpga_ddr0_bid_o3;
-    output fabric_fpga_ddr0_bid_o4;
-    output fabric_fpga_ddr0_bid_o5;
-    input fabric_fpga_ddr0_bready_i;
-    output fabric_fpga_ddr0_bresp_o1;
-    output fabric_fpga_ddr0_bresp_o2;
-    output fabric_fpga_ddr0_bvalid_o;
-    output fabric_fpga_ddr0_rdata_o1;
-    output fabric_fpga_ddr0_rdata_o10;
-    output fabric_fpga_ddr0_rdata_o100;
-    output fabric_fpga_ddr0_rdata_o101;
-    output fabric_fpga_ddr0_rdata_o102;
-    output fabric_fpga_ddr0_rdata_o103;
-    output fabric_fpga_ddr0_rdata_o104;
-    output fabric_fpga_ddr0_rdata_o105;
-    output fabric_fpga_ddr0_rdata_o106;
-    output fabric_fpga_ddr0_rdata_o107;
-    output fabric_fpga_ddr0_rdata_o108;
-    output fabric_fpga_ddr0_rdata_o109;
-    output fabric_fpga_ddr0_rdata_o11;
-    output fabric_fpga_ddr0_rdata_o110;
-    output fabric_fpga_ddr0_rdata_o111;
-    output fabric_fpga_ddr0_rdata_o112;
-    output fabric_fpga_ddr0_rdata_o113;
-    output fabric_fpga_ddr0_rdata_o114;
-    output fabric_fpga_ddr0_rdata_o115;
-    output fabric_fpga_ddr0_rdata_o116;
-    output fabric_fpga_ddr0_rdata_o117;
-    output fabric_fpga_ddr0_rdata_o118;
-    output fabric_fpga_ddr0_rdata_o119;
-    output fabric_fpga_ddr0_rdata_o12;
-    output fabric_fpga_ddr0_rdata_o120;
-    output fabric_fpga_ddr0_rdata_o121;
-    output fabric_fpga_ddr0_rdata_o122;
-    output fabric_fpga_ddr0_rdata_o123;
-    output fabric_fpga_ddr0_rdata_o124;
-    output fabric_fpga_ddr0_rdata_o125;
-    output fabric_fpga_ddr0_rdata_o126;
-    output fabric_fpga_ddr0_rdata_o127;
-    output fabric_fpga_ddr0_rdata_o128;
-    output fabric_fpga_ddr0_rdata_o13;
-    output fabric_fpga_ddr0_rdata_o14;
-    output fabric_fpga_ddr0_rdata_o15;
-    output fabric_fpga_ddr0_rdata_o16;
-    output fabric_fpga_ddr0_rdata_o17;
-    output fabric_fpga_ddr0_rdata_o18;
-    output fabric_fpga_ddr0_rdata_o19;
-    output fabric_fpga_ddr0_rdata_o2;
-    output fabric_fpga_ddr0_rdata_o20;
-    output fabric_fpga_ddr0_rdata_o21;
-    output fabric_fpga_ddr0_rdata_o22;
-    output fabric_fpga_ddr0_rdata_o23;
-    output fabric_fpga_ddr0_rdata_o24;
-    output fabric_fpga_ddr0_rdata_o25;
-    output fabric_fpga_ddr0_rdata_o26;
-    output fabric_fpga_ddr0_rdata_o27;
-    output fabric_fpga_ddr0_rdata_o28;
-    output fabric_fpga_ddr0_rdata_o29;
-    output fabric_fpga_ddr0_rdata_o3;
-    output fabric_fpga_ddr0_rdata_o30;
-    output fabric_fpga_ddr0_rdata_o31;
-    output fabric_fpga_ddr0_rdata_o32;
-    output fabric_fpga_ddr0_rdata_o33;
-    output fabric_fpga_ddr0_rdata_o34;
-    output fabric_fpga_ddr0_rdata_o35;
-    output fabric_fpga_ddr0_rdata_o36;
-    output fabric_fpga_ddr0_rdata_o37;
-    output fabric_fpga_ddr0_rdata_o38;
-    output fabric_fpga_ddr0_rdata_o39;
-    output fabric_fpga_ddr0_rdata_o4;
-    output fabric_fpga_ddr0_rdata_o40;
-    output fabric_fpga_ddr0_rdata_o41;
-    output fabric_fpga_ddr0_rdata_o42;
-    output fabric_fpga_ddr0_rdata_o43;
-    output fabric_fpga_ddr0_rdata_o44;
-    output fabric_fpga_ddr0_rdata_o45;
-    output fabric_fpga_ddr0_rdata_o46;
-    output fabric_fpga_ddr0_rdata_o47;
-    output fabric_fpga_ddr0_rdata_o48;
-    output fabric_fpga_ddr0_rdata_o49;
-    output fabric_fpga_ddr0_rdata_o5;
-    output fabric_fpga_ddr0_rdata_o50;
-    output fabric_fpga_ddr0_rdata_o51;
-    output fabric_fpga_ddr0_rdata_o52;
-    output fabric_fpga_ddr0_rdata_o53;
-    output fabric_fpga_ddr0_rdata_o54;
-    output fabric_fpga_ddr0_rdata_o55;
-    output fabric_fpga_ddr0_rdata_o56;
-    output fabric_fpga_ddr0_rdata_o57;
-    output fabric_fpga_ddr0_rdata_o58;
-    output fabric_fpga_ddr0_rdata_o59;
-    output fabric_fpga_ddr0_rdata_o6;
-    output fabric_fpga_ddr0_rdata_o60;
-    output fabric_fpga_ddr0_rdata_o61;
-    output fabric_fpga_ddr0_rdata_o62;
-    output fabric_fpga_ddr0_rdata_o63;
-    output fabric_fpga_ddr0_rdata_o64;
-    output fabric_fpga_ddr0_rdata_o65;
-    output fabric_fpga_ddr0_rdata_o66;
-    output fabric_fpga_ddr0_rdata_o67;
-    output fabric_fpga_ddr0_rdata_o68;
-    output fabric_fpga_ddr0_rdata_o69;
-    output fabric_fpga_ddr0_rdata_o7;
-    output fabric_fpga_ddr0_rdata_o70;
-    output fabric_fpga_ddr0_rdata_o71;
-    output fabric_fpga_ddr0_rdata_o72;
-    output fabric_fpga_ddr0_rdata_o73;
-    output fabric_fpga_ddr0_rdata_o74;
-    output fabric_fpga_ddr0_rdata_o75;
-    output fabric_fpga_ddr0_rdata_o76;
-    output fabric_fpga_ddr0_rdata_o77;
-    output fabric_fpga_ddr0_rdata_o78;
-    output fabric_fpga_ddr0_rdata_o79;
-    output fabric_fpga_ddr0_rdata_o8;
-    output fabric_fpga_ddr0_rdata_o80;
-    output fabric_fpga_ddr0_rdata_o81;
-    output fabric_fpga_ddr0_rdata_o82;
-    output fabric_fpga_ddr0_rdata_o83;
-    output fabric_fpga_ddr0_rdata_o84;
-    output fabric_fpga_ddr0_rdata_o85;
-    output fabric_fpga_ddr0_rdata_o86;
-    output fabric_fpga_ddr0_rdata_o87;
-    output fabric_fpga_ddr0_rdata_o88;
-    output fabric_fpga_ddr0_rdata_o89;
-    output fabric_fpga_ddr0_rdata_o9;
-    output fabric_fpga_ddr0_rdata_o90;
-    output fabric_fpga_ddr0_rdata_o91;
-    output fabric_fpga_ddr0_rdata_o92;
-    output fabric_fpga_ddr0_rdata_o93;
-    output fabric_fpga_ddr0_rdata_o94;
-    output fabric_fpga_ddr0_rdata_o95;
-    output fabric_fpga_ddr0_rdata_o96;
-    output fabric_fpga_ddr0_rdata_o97;
-    output fabric_fpga_ddr0_rdata_o98;
-    output fabric_fpga_ddr0_rdata_o99;
-    output fabric_fpga_ddr0_rid_o1;
-    output fabric_fpga_ddr0_rid_o2;
-    output fabric_fpga_ddr0_rid_o3;
-    output fabric_fpga_ddr0_rid_o4;
-    output fabric_fpga_ddr0_rid_o5;
-    output fabric_fpga_ddr0_rlast_o;
-    input fabric_fpga_ddr0_rready_i;
-    output fabric_fpga_ddr0_rresp_o1;
-    output fabric_fpga_ddr0_rresp_o2;
-    output fabric_fpga_ddr0_rvalid_o;
-    input fabric_fpga_ddr0_wdata_i1;
-    input fabric_fpga_ddr0_wdata_i10;
-    input fabric_fpga_ddr0_wdata_i100;
-    input fabric_fpga_ddr0_wdata_i101;
-    input fabric_fpga_ddr0_wdata_i102;
-    input fabric_fpga_ddr0_wdata_i103;
-    input fabric_fpga_ddr0_wdata_i104;
-    input fabric_fpga_ddr0_wdata_i105;
-    input fabric_fpga_ddr0_wdata_i106;
-    input fabric_fpga_ddr0_wdata_i107;
-    input fabric_fpga_ddr0_wdata_i108;
-    input fabric_fpga_ddr0_wdata_i109;
-    input fabric_fpga_ddr0_wdata_i11;
-    input fabric_fpga_ddr0_wdata_i110;
-    input fabric_fpga_ddr0_wdata_i111;
-    input fabric_fpga_ddr0_wdata_i112;
-    input fabric_fpga_ddr0_wdata_i113;
-    input fabric_fpga_ddr0_wdata_i114;
-    input fabric_fpga_ddr0_wdata_i115;
-    input fabric_fpga_ddr0_wdata_i116;
-    input fabric_fpga_ddr0_wdata_i117;
-    input fabric_fpga_ddr0_wdata_i118;
-    input fabric_fpga_ddr0_wdata_i119;
-    input fabric_fpga_ddr0_wdata_i12;
-    input fabric_fpga_ddr0_wdata_i120;
-    input fabric_fpga_ddr0_wdata_i121;
-    input fabric_fpga_ddr0_wdata_i122;
-    input fabric_fpga_ddr0_wdata_i123;
-    input fabric_fpga_ddr0_wdata_i124;
-    input fabric_fpga_ddr0_wdata_i125;
-    input fabric_fpga_ddr0_wdata_i126;
-    input fabric_fpga_ddr0_wdata_i127;
-    input fabric_fpga_ddr0_wdata_i128;
-    input fabric_fpga_ddr0_wdata_i13;
-    input fabric_fpga_ddr0_wdata_i14;
-    input fabric_fpga_ddr0_wdata_i15;
-    input fabric_fpga_ddr0_wdata_i16;
-    input fabric_fpga_ddr0_wdata_i17;
-    input fabric_fpga_ddr0_wdata_i18;
-    input fabric_fpga_ddr0_wdata_i19;
-    input fabric_fpga_ddr0_wdata_i2;
-    input fabric_fpga_ddr0_wdata_i20;
-    input fabric_fpga_ddr0_wdata_i21;
-    input fabric_fpga_ddr0_wdata_i22;
-    input fabric_fpga_ddr0_wdata_i23;
-    input fabric_fpga_ddr0_wdata_i24;
-    input fabric_fpga_ddr0_wdata_i25;
-    input fabric_fpga_ddr0_wdata_i26;
-    input fabric_fpga_ddr0_wdata_i27;
-    input fabric_fpga_ddr0_wdata_i28;
-    input fabric_fpga_ddr0_wdata_i29;
-    input fabric_fpga_ddr0_wdata_i3;
-    input fabric_fpga_ddr0_wdata_i30;
-    input fabric_fpga_ddr0_wdata_i31;
-    input fabric_fpga_ddr0_wdata_i32;
-    input fabric_fpga_ddr0_wdata_i33;
-    input fabric_fpga_ddr0_wdata_i34;
-    input fabric_fpga_ddr0_wdata_i35;
-    input fabric_fpga_ddr0_wdata_i36;
-    input fabric_fpga_ddr0_wdata_i37;
-    input fabric_fpga_ddr0_wdata_i38;
-    input fabric_fpga_ddr0_wdata_i39;
-    input fabric_fpga_ddr0_wdata_i4;
-    input fabric_fpga_ddr0_wdata_i40;
-    input fabric_fpga_ddr0_wdata_i41;
-    input fabric_fpga_ddr0_wdata_i42;
-    input fabric_fpga_ddr0_wdata_i43;
-    input fabric_fpga_ddr0_wdata_i44;
-    input fabric_fpga_ddr0_wdata_i45;
-    input fabric_fpga_ddr0_wdata_i46;
-    input fabric_fpga_ddr0_wdata_i47;
-    input fabric_fpga_ddr0_wdata_i48;
-    input fabric_fpga_ddr0_wdata_i49;
-    input fabric_fpga_ddr0_wdata_i5;
-    input fabric_fpga_ddr0_wdata_i50;
-    input fabric_fpga_ddr0_wdata_i51;
-    input fabric_fpga_ddr0_wdata_i52;
-    input fabric_fpga_ddr0_wdata_i53;
-    input fabric_fpga_ddr0_wdata_i54;
-    input fabric_fpga_ddr0_wdata_i55;
-    input fabric_fpga_ddr0_wdata_i56;
-    input fabric_fpga_ddr0_wdata_i57;
-    input fabric_fpga_ddr0_wdata_i58;
-    input fabric_fpga_ddr0_wdata_i59;
-    input fabric_fpga_ddr0_wdata_i6;
-    input fabric_fpga_ddr0_wdata_i60;
-    input fabric_fpga_ddr0_wdata_i61;
-    input fabric_fpga_ddr0_wdata_i62;
-    input fabric_fpga_ddr0_wdata_i63;
-    input fabric_fpga_ddr0_wdata_i64;
-    input fabric_fpga_ddr0_wdata_i65;
-    input fabric_fpga_ddr0_wdata_i66;
-    input fabric_fpga_ddr0_wdata_i67;
-    input fabric_fpga_ddr0_wdata_i68;
-    input fabric_fpga_ddr0_wdata_i69;
-    input fabric_fpga_ddr0_wdata_i7;
-    input fabric_fpga_ddr0_wdata_i70;
-    input fabric_fpga_ddr0_wdata_i71;
-    input fabric_fpga_ddr0_wdata_i72;
-    input fabric_fpga_ddr0_wdata_i73;
-    input fabric_fpga_ddr0_wdata_i74;
-    input fabric_fpga_ddr0_wdata_i75;
-    input fabric_fpga_ddr0_wdata_i76;
-    input fabric_fpga_ddr0_wdata_i77;
-    input fabric_fpga_ddr0_wdata_i78;
-    input fabric_fpga_ddr0_wdata_i79;
-    input fabric_fpga_ddr0_wdata_i8;
-    input fabric_fpga_ddr0_wdata_i80;
-    input fabric_fpga_ddr0_wdata_i81;
-    input fabric_fpga_ddr0_wdata_i82;
-    input fabric_fpga_ddr0_wdata_i83;
-    input fabric_fpga_ddr0_wdata_i84;
-    input fabric_fpga_ddr0_wdata_i85;
-    input fabric_fpga_ddr0_wdata_i86;
-    input fabric_fpga_ddr0_wdata_i87;
-    input fabric_fpga_ddr0_wdata_i88;
-    input fabric_fpga_ddr0_wdata_i89;
-    input fabric_fpga_ddr0_wdata_i9;
-    input fabric_fpga_ddr0_wdata_i90;
-    input fabric_fpga_ddr0_wdata_i91;
-    input fabric_fpga_ddr0_wdata_i92;
-    input fabric_fpga_ddr0_wdata_i93;
-    input fabric_fpga_ddr0_wdata_i94;
-    input fabric_fpga_ddr0_wdata_i95;
-    input fabric_fpga_ddr0_wdata_i96;
-    input fabric_fpga_ddr0_wdata_i97;
-    input fabric_fpga_ddr0_wdata_i98;
-    input fabric_fpga_ddr0_wdata_i99;
-    input fabric_fpga_ddr0_wlast_i;
-    output fabric_fpga_ddr0_wready_o;
-    input fabric_fpga_ddr0_wstrb_i1;
-    input fabric_fpga_ddr0_wstrb_i10;
-    input fabric_fpga_ddr0_wstrb_i11;
-    input fabric_fpga_ddr0_wstrb_i12;
-    input fabric_fpga_ddr0_wstrb_i13;
-    input fabric_fpga_ddr0_wstrb_i14;
-    input fabric_fpga_ddr0_wstrb_i15;
-    input fabric_fpga_ddr0_wstrb_i16;
-    input fabric_fpga_ddr0_wstrb_i2;
-    input fabric_fpga_ddr0_wstrb_i3;
-    input fabric_fpga_ddr0_wstrb_i4;
-    input fabric_fpga_ddr0_wstrb_i5;
-    input fabric_fpga_ddr0_wstrb_i6;
-    input fabric_fpga_ddr0_wstrb_i7;
-    input fabric_fpga_ddr0_wstrb_i8;
-    input fabric_fpga_ddr0_wstrb_i9;
-    input fabric_fpga_ddr0_wvalid_i;
-    output fabric_fpga_dma_ack_m1_o1;
-    output fabric_fpga_dma_ack_m1_o2;
-    output fabric_fpga_dma_ack_m1_o3;
-    output fabric_fpga_dma_ack_m1_o4;
-    output fabric_fpga_dma_ack_m1_o5;
-    output fabric_fpga_dma_ack_m1_o6;
-    output fabric_fpga_dma_ack_m2_o1;
-    output fabric_fpga_dma_ack_m2_o2;
-    output fabric_fpga_dma_ack_m2_o3;
-    output fabric_fpga_dma_ack_m2_o4;
-    output fabric_fpga_dma_ack_m2_o5;
-    output fabric_fpga_dma_ack_m2_o6;
-    output fabric_fpga_dma_finish_m1_o1;
-    output fabric_fpga_dma_finish_m1_o2;
-    output fabric_fpga_dma_finish_m1_o3;
-    output fabric_fpga_dma_finish_m1_o4;
-    output fabric_fpga_dma_finish_m1_o5;
-    output fabric_fpga_dma_finish_m1_o6;
-    output fabric_fpga_dma_finish_m2_o1;
-    output fabric_fpga_dma_finish_m2_o2;
-    output fabric_fpga_dma_finish_m2_o3;
-    output fabric_fpga_dma_finish_m2_o4;
-    output fabric_fpga_dma_finish_m2_o5;
-    output fabric_fpga_dma_finish_m2_o6;
-    input fabric_fpga_dma_hs_rstn_i1;
-    input fabric_fpga_dma_hs_rstn_i2;
-    input fabric_fpga_dma_hs_rstn_i3;
-    input fabric_fpga_dma_hs_rstn_i4;
-    input fabric_fpga_dma_hs_rstn_i5;
-    input fabric_fpga_dma_hs_rstn_i6;
-    input fabric_fpga_dma_last_m1_i1;
-    input fabric_fpga_dma_last_m1_i2;
-    input fabric_fpga_dma_last_m1_i3;
-    input fabric_fpga_dma_last_m1_i4;
-    input fabric_fpga_dma_last_m1_i5;
-    input fabric_fpga_dma_last_m1_i6;
-    input fabric_fpga_dma_last_m2_i1;
-    input fabric_fpga_dma_last_m2_i2;
-    input fabric_fpga_dma_last_m2_i3;
-    input fabric_fpga_dma_last_m2_i4;
-    input fabric_fpga_dma_last_m2_i5;
-    input fabric_fpga_dma_last_m2_i6;
-    input fabric_fpga_dma_req_m1_i1;
-    input fabric_fpga_dma_req_m1_i2;
-    input fabric_fpga_dma_req_m1_i3;
-    input fabric_fpga_dma_req_m1_i4;
-    input fabric_fpga_dma_req_m1_i5;
-    input fabric_fpga_dma_req_m1_i6;
-    input fabric_fpga_dma_req_m2_i1;
-    input fabric_fpga_dma_req_m2_i2;
-    input fabric_fpga_dma_req_m2_i3;
-    input fabric_fpga_dma_req_m2_i4;
-    input fabric_fpga_dma_req_m2_i5;
-    input fabric_fpga_dma_req_m2_i6;
-    input fabric_fpga_dma_single_m1_i1;
-    input fabric_fpga_dma_single_m1_i2;
-    input fabric_fpga_dma_single_m1_i3;
-    input fabric_fpga_dma_single_m1_i4;
-    input fabric_fpga_dma_single_m1_i5;
-    input fabric_fpga_dma_single_m1_i6;
-    input fabric_fpga_dma_single_m2_i1;
-    input fabric_fpga_dma_single_m2_i2;
-    input fabric_fpga_dma_single_m2_i3;
-    input fabric_fpga_dma_single_m2_i4;
-    input fabric_fpga_dma_single_m2_i5;
-    input fabric_fpga_dma_single_m2_i6;
-    input fabric_fpga_events60_i1;
-    input fabric_fpga_events60_i10;
-    input fabric_fpga_events60_i11;
-    input fabric_fpga_events60_i12;
-    input fabric_fpga_events60_i13;
-    input fabric_fpga_events60_i14;
-    input fabric_fpga_events60_i15;
-    input fabric_fpga_events60_i16;
-    input fabric_fpga_events60_i17;
-    input fabric_fpga_events60_i18;
-    input fabric_fpga_events60_i19;
-    input fabric_fpga_events60_i2;
-    input fabric_fpga_events60_i20;
-    input fabric_fpga_events60_i21;
-    input fabric_fpga_events60_i22;
-    input fabric_fpga_events60_i23;
-    input fabric_fpga_events60_i24;
-    input fabric_fpga_events60_i25;
-    input fabric_fpga_events60_i26;
-    input fabric_fpga_events60_i27;
-    input fabric_fpga_events60_i28;
-    input fabric_fpga_events60_i29;
-    input fabric_fpga_events60_i3;
-    input fabric_fpga_events60_i30;
-    input fabric_fpga_events60_i31;
-    input fabric_fpga_events60_i32;
-    input fabric_fpga_events60_i33;
-    input fabric_fpga_events60_i34;
-    input fabric_fpga_events60_i35;
-    input fabric_fpga_events60_i36;
-    input fabric_fpga_events60_i37;
-    input fabric_fpga_events60_i38;
-    input fabric_fpga_events60_i39;
-    input fabric_fpga_events60_i4;
-    input fabric_fpga_events60_i40;
-    input fabric_fpga_events60_i41;
-    input fabric_fpga_events60_i42;
-    input fabric_fpga_events60_i43;
-    input fabric_fpga_events60_i44;
-    input fabric_fpga_events60_i45;
-    input fabric_fpga_events60_i46;
-    input fabric_fpga_events60_i47;
-    input fabric_fpga_events60_i48;
-    input fabric_fpga_events60_i49;
-    input fabric_fpga_events60_i5;
-    input fabric_fpga_events60_i50;
-    input fabric_fpga_events60_i51;
-    input fabric_fpga_events60_i52;
-    input fabric_fpga_events60_i53;
-    input fabric_fpga_events60_i54;
-    input fabric_fpga_events60_i55;
-    input fabric_fpga_events60_i56;
-    input fabric_fpga_events60_i57;
-    input fabric_fpga_events60_i58;
-    input fabric_fpga_events60_i59;
-    input fabric_fpga_events60_i6;
-    input fabric_fpga_events60_i60;
-    input fabric_fpga_events60_i7;
-    input fabric_fpga_events60_i8;
-    input fabric_fpga_events60_i9;
-    input fabric_fpga_interrupt_in_i1;
-    input fabric_fpga_interrupt_in_i10;
-    input fabric_fpga_interrupt_in_i100;
-    input fabric_fpga_interrupt_in_i101;
-    input fabric_fpga_interrupt_in_i102;
-    input fabric_fpga_interrupt_in_i103;
-    input fabric_fpga_interrupt_in_i104;
-    input fabric_fpga_interrupt_in_i105;
-    input fabric_fpga_interrupt_in_i106;
-    input fabric_fpga_interrupt_in_i107;
-    input fabric_fpga_interrupt_in_i108;
-    input fabric_fpga_interrupt_in_i109;
-    input fabric_fpga_interrupt_in_i11;
-    input fabric_fpga_interrupt_in_i110;
-    input fabric_fpga_interrupt_in_i111;
-    input fabric_fpga_interrupt_in_i112;
-    input fabric_fpga_interrupt_in_i113;
-    input fabric_fpga_interrupt_in_i114;
-    input fabric_fpga_interrupt_in_i115;
-    input fabric_fpga_interrupt_in_i116;
-    input fabric_fpga_interrupt_in_i117;
-    input fabric_fpga_interrupt_in_i118;
-    input fabric_fpga_interrupt_in_i119;
-    input fabric_fpga_interrupt_in_i12;
-    input fabric_fpga_interrupt_in_i120;
-    input fabric_fpga_interrupt_in_i13;
-    input fabric_fpga_interrupt_in_i14;
-    input fabric_fpga_interrupt_in_i15;
-    input fabric_fpga_interrupt_in_i16;
-    input fabric_fpga_interrupt_in_i17;
-    input fabric_fpga_interrupt_in_i18;
-    input fabric_fpga_interrupt_in_i19;
-    input fabric_fpga_interrupt_in_i2;
-    input fabric_fpga_interrupt_in_i20;
-    input fabric_fpga_interrupt_in_i21;
-    input fabric_fpga_interrupt_in_i22;
-    input fabric_fpga_interrupt_in_i23;
-    input fabric_fpga_interrupt_in_i24;
-    input fabric_fpga_interrupt_in_i25;
-    input fabric_fpga_interrupt_in_i26;
-    input fabric_fpga_interrupt_in_i27;
-    input fabric_fpga_interrupt_in_i28;
-    input fabric_fpga_interrupt_in_i29;
-    input fabric_fpga_interrupt_in_i3;
-    input fabric_fpga_interrupt_in_i30;
-    input fabric_fpga_interrupt_in_i31;
-    input fabric_fpga_interrupt_in_i32;
-    input fabric_fpga_interrupt_in_i33;
-    input fabric_fpga_interrupt_in_i34;
-    input fabric_fpga_interrupt_in_i35;
-    input fabric_fpga_interrupt_in_i36;
-    input fabric_fpga_interrupt_in_i37;
-    input fabric_fpga_interrupt_in_i38;
-    input fabric_fpga_interrupt_in_i39;
-    input fabric_fpga_interrupt_in_i4;
-    input fabric_fpga_interrupt_in_i40;
-    input fabric_fpga_interrupt_in_i41;
-    input fabric_fpga_interrupt_in_i42;
-    input fabric_fpga_interrupt_in_i43;
-    input fabric_fpga_interrupt_in_i44;
-    input fabric_fpga_interrupt_in_i45;
-    input fabric_fpga_interrupt_in_i46;
-    input fabric_fpga_interrupt_in_i47;
-    input fabric_fpga_interrupt_in_i48;
-    input fabric_fpga_interrupt_in_i49;
-    input fabric_fpga_interrupt_in_i5;
-    input fabric_fpga_interrupt_in_i50;
-    input fabric_fpga_interrupt_in_i51;
-    input fabric_fpga_interrupt_in_i52;
-    input fabric_fpga_interrupt_in_i53;
-    input fabric_fpga_interrupt_in_i54;
-    input fabric_fpga_interrupt_in_i55;
-    input fabric_fpga_interrupt_in_i56;
-    input fabric_fpga_interrupt_in_i57;
-    input fabric_fpga_interrupt_in_i58;
-    input fabric_fpga_interrupt_in_i59;
-    input fabric_fpga_interrupt_in_i6;
-    input fabric_fpga_interrupt_in_i60;
-    input fabric_fpga_interrupt_in_i61;
-    input fabric_fpga_interrupt_in_i62;
-    input fabric_fpga_interrupt_in_i63;
-    input fabric_fpga_interrupt_in_i64;
-    input fabric_fpga_interrupt_in_i65;
-    input fabric_fpga_interrupt_in_i66;
-    input fabric_fpga_interrupt_in_i67;
-    input fabric_fpga_interrupt_in_i68;
-    input fabric_fpga_interrupt_in_i69;
-    input fabric_fpga_interrupt_in_i7;
-    input fabric_fpga_interrupt_in_i70;
-    input fabric_fpga_interrupt_in_i71;
-    input fabric_fpga_interrupt_in_i72;
-    input fabric_fpga_interrupt_in_i73;
-    input fabric_fpga_interrupt_in_i74;
-    input fabric_fpga_interrupt_in_i75;
-    input fabric_fpga_interrupt_in_i76;
-    input fabric_fpga_interrupt_in_i77;
-    input fabric_fpga_interrupt_in_i78;
-    input fabric_fpga_interrupt_in_i79;
-    input fabric_fpga_interrupt_in_i8;
-    input fabric_fpga_interrupt_in_i80;
-    input fabric_fpga_interrupt_in_i81;
-    input fabric_fpga_interrupt_in_i82;
-    input fabric_fpga_interrupt_in_i83;
-    input fabric_fpga_interrupt_in_i84;
-    input fabric_fpga_interrupt_in_i85;
-    input fabric_fpga_interrupt_in_i86;
-    input fabric_fpga_interrupt_in_i87;
-    input fabric_fpga_interrupt_in_i88;
-    input fabric_fpga_interrupt_in_i89;
-    input fabric_fpga_interrupt_in_i9;
-    input fabric_fpga_interrupt_in_i90;
-    input fabric_fpga_interrupt_in_i91;
-    input fabric_fpga_interrupt_in_i92;
-    input fabric_fpga_interrupt_in_i93;
-    input fabric_fpga_interrupt_in_i94;
-    input fabric_fpga_interrupt_in_i95;
-    input fabric_fpga_interrupt_in_i96;
-    input fabric_fpga_interrupt_in_i97;
-    input fabric_fpga_interrupt_in_i98;
-    input fabric_fpga_interrupt_in_i99;
-    input fabric_fpga_nic_rstn_i1;
-    input fabric_fpga_nic_rstn_i10;
-    input fabric_fpga_nic_rstn_i2;
-    input fabric_fpga_nic_rstn_i3;
-    input fabric_fpga_nic_rstn_i4;
-    input fabric_fpga_nic_rstn_i5;
-    input fabric_fpga_nic_rstn_i6;
-    input fabric_fpga_nic_rstn_i7;
-    input fabric_fpga_nic_rstn_i8;
-    input fabric_fpga_nic_rstn_i9;
-    output fabric_fpga_paddr_apb_o1;
-    output fabric_fpga_paddr_apb_o10;
-    output fabric_fpga_paddr_apb_o11;
-    output fabric_fpga_paddr_apb_o12;
-    output fabric_fpga_paddr_apb_o13;
-    output fabric_fpga_paddr_apb_o14;
-    output fabric_fpga_paddr_apb_o15;
-    output fabric_fpga_paddr_apb_o16;
-    output fabric_fpga_paddr_apb_o17;
-    output fabric_fpga_paddr_apb_o18;
-    output fabric_fpga_paddr_apb_o19;
-    output fabric_fpga_paddr_apb_o2;
-    output fabric_fpga_paddr_apb_o20;
-    output fabric_fpga_paddr_apb_o21;
-    output fabric_fpga_paddr_apb_o22;
-    output fabric_fpga_paddr_apb_o23;
-    output fabric_fpga_paddr_apb_o24;
-    output fabric_fpga_paddr_apb_o25;
-    output fabric_fpga_paddr_apb_o26;
-    output fabric_fpga_paddr_apb_o27;
-    output fabric_fpga_paddr_apb_o28;
-    output fabric_fpga_paddr_apb_o29;
-    output fabric_fpga_paddr_apb_o3;
-    output fabric_fpga_paddr_apb_o30;
-    output fabric_fpga_paddr_apb_o31;
-    output fabric_fpga_paddr_apb_o32;
-    output fabric_fpga_paddr_apb_o4;
-    output fabric_fpga_paddr_apb_o5;
-    output fabric_fpga_paddr_apb_o6;
-    output fabric_fpga_paddr_apb_o7;
-    output fabric_fpga_paddr_apb_o8;
-    output fabric_fpga_paddr_apb_o9;
-    output fabric_fpga_penable_apb_o;
-    input fabric_fpga_pmrstn_i;
-    input fabric_fpga_prdata_apb_i1;
-    input fabric_fpga_prdata_apb_i10;
-    input fabric_fpga_prdata_apb_i11;
-    input fabric_fpga_prdata_apb_i12;
-    input fabric_fpga_prdata_apb_i13;
-    input fabric_fpga_prdata_apb_i14;
-    input fabric_fpga_prdata_apb_i15;
-    input fabric_fpga_prdata_apb_i16;
-    input fabric_fpga_prdata_apb_i17;
-    input fabric_fpga_prdata_apb_i18;
-    input fabric_fpga_prdata_apb_i19;
-    input fabric_fpga_prdata_apb_i2;
-    input fabric_fpga_prdata_apb_i20;
-    input fabric_fpga_prdata_apb_i21;
-    input fabric_fpga_prdata_apb_i22;
-    input fabric_fpga_prdata_apb_i23;
-    input fabric_fpga_prdata_apb_i24;
-    input fabric_fpga_prdata_apb_i25;
-    input fabric_fpga_prdata_apb_i26;
-    input fabric_fpga_prdata_apb_i27;
-    input fabric_fpga_prdata_apb_i28;
-    input fabric_fpga_prdata_apb_i29;
-    input fabric_fpga_prdata_apb_i3;
-    input fabric_fpga_prdata_apb_i30;
-    input fabric_fpga_prdata_apb_i31;
-    input fabric_fpga_prdata_apb_i32;
-    input fabric_fpga_prdata_apb_i4;
-    input fabric_fpga_prdata_apb_i5;
-    input fabric_fpga_prdata_apb_i6;
-    input fabric_fpga_prdata_apb_i7;
-    input fabric_fpga_prdata_apb_i8;
-    input fabric_fpga_prdata_apb_i9;
-    input fabric_fpga_pready_apb_i;
-    output fabric_fpga_psel_apb_o;
-    input fabric_fpga_pslverr_apb_i;
-    output fabric_fpga_pwdata_apb_o1;
-    output fabric_fpga_pwdata_apb_o10;
-    output fabric_fpga_pwdata_apb_o11;
-    output fabric_fpga_pwdata_apb_o12;
-    output fabric_fpga_pwdata_apb_o13;
-    output fabric_fpga_pwdata_apb_o14;
-    output fabric_fpga_pwdata_apb_o15;
-    output fabric_fpga_pwdata_apb_o16;
-    output fabric_fpga_pwdata_apb_o17;
-    output fabric_fpga_pwdata_apb_o18;
-    output fabric_fpga_pwdata_apb_o19;
-    output fabric_fpga_pwdata_apb_o2;
-    output fabric_fpga_pwdata_apb_o20;
-    output fabric_fpga_pwdata_apb_o21;
-    output fabric_fpga_pwdata_apb_o22;
-    output fabric_fpga_pwdata_apb_o23;
-    output fabric_fpga_pwdata_apb_o24;
-    output fabric_fpga_pwdata_apb_o25;
-    output fabric_fpga_pwdata_apb_o26;
-    output fabric_fpga_pwdata_apb_o27;
-    output fabric_fpga_pwdata_apb_o28;
-    output fabric_fpga_pwdata_apb_o29;
-    output fabric_fpga_pwdata_apb_o3;
-    output fabric_fpga_pwdata_apb_o30;
-    output fabric_fpga_pwdata_apb_o31;
-    output fabric_fpga_pwdata_apb_o32;
-    output fabric_fpga_pwdata_apb_o4;
-    output fabric_fpga_pwdata_apb_o5;
-    output fabric_fpga_pwdata_apb_o6;
-    output fabric_fpga_pwdata_apb_o7;
-    output fabric_fpga_pwdata_apb_o8;
-    output fabric_fpga_pwdata_apb_o9;
-    output fabric_fpga_pwrite_apb_o;
-    output fabric_fpga_rdata_axi_m1_o1;
-    output fabric_fpga_rdata_axi_m1_o10;
-    output fabric_fpga_rdata_axi_m1_o100;
-    output fabric_fpga_rdata_axi_m1_o101;
-    output fabric_fpga_rdata_axi_m1_o102;
-    output fabric_fpga_rdata_axi_m1_o103;
-    output fabric_fpga_rdata_axi_m1_o104;
-    output fabric_fpga_rdata_axi_m1_o105;
-    output fabric_fpga_rdata_axi_m1_o106;
-    output fabric_fpga_rdata_axi_m1_o107;
-    output fabric_fpga_rdata_axi_m1_o108;
-    output fabric_fpga_rdata_axi_m1_o109;
-    output fabric_fpga_rdata_axi_m1_o11;
-    output fabric_fpga_rdata_axi_m1_o110;
-    output fabric_fpga_rdata_axi_m1_o111;
-    output fabric_fpga_rdata_axi_m1_o112;
-    output fabric_fpga_rdata_axi_m1_o113;
-    output fabric_fpga_rdata_axi_m1_o114;
-    output fabric_fpga_rdata_axi_m1_o115;
-    output fabric_fpga_rdata_axi_m1_o116;
-    output fabric_fpga_rdata_axi_m1_o117;
-    output fabric_fpga_rdata_axi_m1_o118;
-    output fabric_fpga_rdata_axi_m1_o119;
-    output fabric_fpga_rdata_axi_m1_o12;
-    output fabric_fpga_rdata_axi_m1_o120;
-    output fabric_fpga_rdata_axi_m1_o121;
-    output fabric_fpga_rdata_axi_m1_o122;
-    output fabric_fpga_rdata_axi_m1_o123;
-    output fabric_fpga_rdata_axi_m1_o124;
-    output fabric_fpga_rdata_axi_m1_o125;
-    output fabric_fpga_rdata_axi_m1_o126;
-    output fabric_fpga_rdata_axi_m1_o127;
-    output fabric_fpga_rdata_axi_m1_o128;
-    output fabric_fpga_rdata_axi_m1_o13;
-    output fabric_fpga_rdata_axi_m1_o14;
-    output fabric_fpga_rdata_axi_m1_o15;
-    output fabric_fpga_rdata_axi_m1_o16;
-    output fabric_fpga_rdata_axi_m1_o17;
-    output fabric_fpga_rdata_axi_m1_o18;
-    output fabric_fpga_rdata_axi_m1_o19;
-    output fabric_fpga_rdata_axi_m1_o2;
-    output fabric_fpga_rdata_axi_m1_o20;
-    output fabric_fpga_rdata_axi_m1_o21;
-    output fabric_fpga_rdata_axi_m1_o22;
-    output fabric_fpga_rdata_axi_m1_o23;
-    output fabric_fpga_rdata_axi_m1_o24;
-    output fabric_fpga_rdata_axi_m1_o25;
-    output fabric_fpga_rdata_axi_m1_o26;
-    output fabric_fpga_rdata_axi_m1_o27;
-    output fabric_fpga_rdata_axi_m1_o28;
-    output fabric_fpga_rdata_axi_m1_o29;
-    output fabric_fpga_rdata_axi_m1_o3;
-    output fabric_fpga_rdata_axi_m1_o30;
-    output fabric_fpga_rdata_axi_m1_o31;
-    output fabric_fpga_rdata_axi_m1_o32;
-    output fabric_fpga_rdata_axi_m1_o33;
-    output fabric_fpga_rdata_axi_m1_o34;
-    output fabric_fpga_rdata_axi_m1_o35;
-    output fabric_fpga_rdata_axi_m1_o36;
-    output fabric_fpga_rdata_axi_m1_o37;
-    output fabric_fpga_rdata_axi_m1_o38;
-    output fabric_fpga_rdata_axi_m1_o39;
-    output fabric_fpga_rdata_axi_m1_o4;
-    output fabric_fpga_rdata_axi_m1_o40;
-    output fabric_fpga_rdata_axi_m1_o41;
-    output fabric_fpga_rdata_axi_m1_o42;
-    output fabric_fpga_rdata_axi_m1_o43;
-    output fabric_fpga_rdata_axi_m1_o44;
-    output fabric_fpga_rdata_axi_m1_o45;
-    output fabric_fpga_rdata_axi_m1_o46;
-    output fabric_fpga_rdata_axi_m1_o47;
-    output fabric_fpga_rdata_axi_m1_o48;
-    output fabric_fpga_rdata_axi_m1_o49;
-    output fabric_fpga_rdata_axi_m1_o5;
-    output fabric_fpga_rdata_axi_m1_o50;
-    output fabric_fpga_rdata_axi_m1_o51;
-    output fabric_fpga_rdata_axi_m1_o52;
-    output fabric_fpga_rdata_axi_m1_o53;
-    output fabric_fpga_rdata_axi_m1_o54;
-    output fabric_fpga_rdata_axi_m1_o55;
-    output fabric_fpga_rdata_axi_m1_o56;
-    output fabric_fpga_rdata_axi_m1_o57;
-    output fabric_fpga_rdata_axi_m1_o58;
-    output fabric_fpga_rdata_axi_m1_o59;
-    output fabric_fpga_rdata_axi_m1_o6;
-    output fabric_fpga_rdata_axi_m1_o60;
-    output fabric_fpga_rdata_axi_m1_o61;
-    output fabric_fpga_rdata_axi_m1_o62;
-    output fabric_fpga_rdata_axi_m1_o63;
-    output fabric_fpga_rdata_axi_m1_o64;
-    output fabric_fpga_rdata_axi_m1_o65;
-    output fabric_fpga_rdata_axi_m1_o66;
-    output fabric_fpga_rdata_axi_m1_o67;
-    output fabric_fpga_rdata_axi_m1_o68;
-    output fabric_fpga_rdata_axi_m1_o69;
-    output fabric_fpga_rdata_axi_m1_o7;
-    output fabric_fpga_rdata_axi_m1_o70;
-    output fabric_fpga_rdata_axi_m1_o71;
-    output fabric_fpga_rdata_axi_m1_o72;
-    output fabric_fpga_rdata_axi_m1_o73;
-    output fabric_fpga_rdata_axi_m1_o74;
-    output fabric_fpga_rdata_axi_m1_o75;
-    output fabric_fpga_rdata_axi_m1_o76;
-    output fabric_fpga_rdata_axi_m1_o77;
-    output fabric_fpga_rdata_axi_m1_o78;
-    output fabric_fpga_rdata_axi_m1_o79;
-    output fabric_fpga_rdata_axi_m1_o8;
-    output fabric_fpga_rdata_axi_m1_o80;
-    output fabric_fpga_rdata_axi_m1_o81;
-    output fabric_fpga_rdata_axi_m1_o82;
-    output fabric_fpga_rdata_axi_m1_o83;
-    output fabric_fpga_rdata_axi_m1_o84;
-    output fabric_fpga_rdata_axi_m1_o85;
-    output fabric_fpga_rdata_axi_m1_o86;
-    output fabric_fpga_rdata_axi_m1_o87;
-    output fabric_fpga_rdata_axi_m1_o88;
-    output fabric_fpga_rdata_axi_m1_o89;
-    output fabric_fpga_rdata_axi_m1_o9;
-    output fabric_fpga_rdata_axi_m1_o90;
-    output fabric_fpga_rdata_axi_m1_o91;
-    output fabric_fpga_rdata_axi_m1_o92;
-    output fabric_fpga_rdata_axi_m1_o93;
-    output fabric_fpga_rdata_axi_m1_o94;
-    output fabric_fpga_rdata_axi_m1_o95;
-    output fabric_fpga_rdata_axi_m1_o96;
-    output fabric_fpga_rdata_axi_m1_o97;
-    output fabric_fpga_rdata_axi_m1_o98;
-    output fabric_fpga_rdata_axi_m1_o99;
-    output fabric_fpga_rdata_axi_m2_o1;
-    output fabric_fpga_rdata_axi_m2_o10;
-    output fabric_fpga_rdata_axi_m2_o100;
-    output fabric_fpga_rdata_axi_m2_o101;
-    output fabric_fpga_rdata_axi_m2_o102;
-    output fabric_fpga_rdata_axi_m2_o103;
-    output fabric_fpga_rdata_axi_m2_o104;
-    output fabric_fpga_rdata_axi_m2_o105;
-    output fabric_fpga_rdata_axi_m2_o106;
-    output fabric_fpga_rdata_axi_m2_o107;
-    output fabric_fpga_rdata_axi_m2_o108;
-    output fabric_fpga_rdata_axi_m2_o109;
-    output fabric_fpga_rdata_axi_m2_o11;
-    output fabric_fpga_rdata_axi_m2_o110;
-    output fabric_fpga_rdata_axi_m2_o111;
-    output fabric_fpga_rdata_axi_m2_o112;
-    output fabric_fpga_rdata_axi_m2_o113;
-    output fabric_fpga_rdata_axi_m2_o114;
-    output fabric_fpga_rdata_axi_m2_o115;
-    output fabric_fpga_rdata_axi_m2_o116;
-    output fabric_fpga_rdata_axi_m2_o117;
-    output fabric_fpga_rdata_axi_m2_o118;
-    output fabric_fpga_rdata_axi_m2_o119;
-    output fabric_fpga_rdata_axi_m2_o12;
-    output fabric_fpga_rdata_axi_m2_o120;
-    output fabric_fpga_rdata_axi_m2_o121;
-    output fabric_fpga_rdata_axi_m2_o122;
-    output fabric_fpga_rdata_axi_m2_o123;
-    output fabric_fpga_rdata_axi_m2_o124;
-    output fabric_fpga_rdata_axi_m2_o125;
-    output fabric_fpga_rdata_axi_m2_o126;
-    output fabric_fpga_rdata_axi_m2_o127;
-    output fabric_fpga_rdata_axi_m2_o128;
-    output fabric_fpga_rdata_axi_m2_o13;
-    output fabric_fpga_rdata_axi_m2_o14;
-    output fabric_fpga_rdata_axi_m2_o15;
-    output fabric_fpga_rdata_axi_m2_o16;
-    output fabric_fpga_rdata_axi_m2_o17;
-    output fabric_fpga_rdata_axi_m2_o18;
-    output fabric_fpga_rdata_axi_m2_o19;
-    output fabric_fpga_rdata_axi_m2_o2;
-    output fabric_fpga_rdata_axi_m2_o20;
-    output fabric_fpga_rdata_axi_m2_o21;
-    output fabric_fpga_rdata_axi_m2_o22;
-    output fabric_fpga_rdata_axi_m2_o23;
-    output fabric_fpga_rdata_axi_m2_o24;
-    output fabric_fpga_rdata_axi_m2_o25;
-    output fabric_fpga_rdata_axi_m2_o26;
-    output fabric_fpga_rdata_axi_m2_o27;
-    output fabric_fpga_rdata_axi_m2_o28;
-    output fabric_fpga_rdata_axi_m2_o29;
-    output fabric_fpga_rdata_axi_m2_o3;
-    output fabric_fpga_rdata_axi_m2_o30;
-    output fabric_fpga_rdata_axi_m2_o31;
-    output fabric_fpga_rdata_axi_m2_o32;
-    output fabric_fpga_rdata_axi_m2_o33;
-    output fabric_fpga_rdata_axi_m2_o34;
-    output fabric_fpga_rdata_axi_m2_o35;
-    output fabric_fpga_rdata_axi_m2_o36;
-    output fabric_fpga_rdata_axi_m2_o37;
-    output fabric_fpga_rdata_axi_m2_o38;
-    output fabric_fpga_rdata_axi_m2_o39;
-    output fabric_fpga_rdata_axi_m2_o4;
-    output fabric_fpga_rdata_axi_m2_o40;
-    output fabric_fpga_rdata_axi_m2_o41;
-    output fabric_fpga_rdata_axi_m2_o42;
-    output fabric_fpga_rdata_axi_m2_o43;
-    output fabric_fpga_rdata_axi_m2_o44;
-    output fabric_fpga_rdata_axi_m2_o45;
-    output fabric_fpga_rdata_axi_m2_o46;
-    output fabric_fpga_rdata_axi_m2_o47;
-    output fabric_fpga_rdata_axi_m2_o48;
-    output fabric_fpga_rdata_axi_m2_o49;
-    output fabric_fpga_rdata_axi_m2_o5;
-    output fabric_fpga_rdata_axi_m2_o50;
-    output fabric_fpga_rdata_axi_m2_o51;
-    output fabric_fpga_rdata_axi_m2_o52;
-    output fabric_fpga_rdata_axi_m2_o53;
-    output fabric_fpga_rdata_axi_m2_o54;
-    output fabric_fpga_rdata_axi_m2_o55;
-    output fabric_fpga_rdata_axi_m2_o56;
-    output fabric_fpga_rdata_axi_m2_o57;
-    output fabric_fpga_rdata_axi_m2_o58;
-    output fabric_fpga_rdata_axi_m2_o59;
-    output fabric_fpga_rdata_axi_m2_o6;
-    output fabric_fpga_rdata_axi_m2_o60;
-    output fabric_fpga_rdata_axi_m2_o61;
-    output fabric_fpga_rdata_axi_m2_o62;
-    output fabric_fpga_rdata_axi_m2_o63;
-    output fabric_fpga_rdata_axi_m2_o64;
-    output fabric_fpga_rdata_axi_m2_o65;
-    output fabric_fpga_rdata_axi_m2_o66;
-    output fabric_fpga_rdata_axi_m2_o67;
-    output fabric_fpga_rdata_axi_m2_o68;
-    output fabric_fpga_rdata_axi_m2_o69;
-    output fabric_fpga_rdata_axi_m2_o7;
-    output fabric_fpga_rdata_axi_m2_o70;
-    output fabric_fpga_rdata_axi_m2_o71;
-    output fabric_fpga_rdata_axi_m2_o72;
-    output fabric_fpga_rdata_axi_m2_o73;
-    output fabric_fpga_rdata_axi_m2_o74;
-    output fabric_fpga_rdata_axi_m2_o75;
-    output fabric_fpga_rdata_axi_m2_o76;
-    output fabric_fpga_rdata_axi_m2_o77;
-    output fabric_fpga_rdata_axi_m2_o78;
-    output fabric_fpga_rdata_axi_m2_o79;
-    output fabric_fpga_rdata_axi_m2_o8;
-    output fabric_fpga_rdata_axi_m2_o80;
-    output fabric_fpga_rdata_axi_m2_o81;
-    output fabric_fpga_rdata_axi_m2_o82;
-    output fabric_fpga_rdata_axi_m2_o83;
-    output fabric_fpga_rdata_axi_m2_o84;
-    output fabric_fpga_rdata_axi_m2_o85;
-    output fabric_fpga_rdata_axi_m2_o86;
-    output fabric_fpga_rdata_axi_m2_o87;
-    output fabric_fpga_rdata_axi_m2_o88;
-    output fabric_fpga_rdata_axi_m2_o89;
-    output fabric_fpga_rdata_axi_m2_o9;
-    output fabric_fpga_rdata_axi_m2_o90;
-    output fabric_fpga_rdata_axi_m2_o91;
-    output fabric_fpga_rdata_axi_m2_o92;
-    output fabric_fpga_rdata_axi_m2_o93;
-    output fabric_fpga_rdata_axi_m2_o94;
-    output fabric_fpga_rdata_axi_m2_o95;
-    output fabric_fpga_rdata_axi_m2_o96;
-    output fabric_fpga_rdata_axi_m2_o97;
-    output fabric_fpga_rdata_axi_m2_o98;
-    output fabric_fpga_rdata_axi_m2_o99;
-    input fabric_fpga_rdata_axi_s1_i1;
-    input fabric_fpga_rdata_axi_s1_i10;
-    input fabric_fpga_rdata_axi_s1_i100;
-    input fabric_fpga_rdata_axi_s1_i101;
-    input fabric_fpga_rdata_axi_s1_i102;
-    input fabric_fpga_rdata_axi_s1_i103;
-    input fabric_fpga_rdata_axi_s1_i104;
-    input fabric_fpga_rdata_axi_s1_i105;
-    input fabric_fpga_rdata_axi_s1_i106;
-    input fabric_fpga_rdata_axi_s1_i107;
-    input fabric_fpga_rdata_axi_s1_i108;
-    input fabric_fpga_rdata_axi_s1_i109;
-    input fabric_fpga_rdata_axi_s1_i11;
-    input fabric_fpga_rdata_axi_s1_i110;
-    input fabric_fpga_rdata_axi_s1_i111;
-    input fabric_fpga_rdata_axi_s1_i112;
-    input fabric_fpga_rdata_axi_s1_i113;
-    input fabric_fpga_rdata_axi_s1_i114;
-    input fabric_fpga_rdata_axi_s1_i115;
-    input fabric_fpga_rdata_axi_s1_i116;
-    input fabric_fpga_rdata_axi_s1_i117;
-    input fabric_fpga_rdata_axi_s1_i118;
-    input fabric_fpga_rdata_axi_s1_i119;
-    input fabric_fpga_rdata_axi_s1_i12;
-    input fabric_fpga_rdata_axi_s1_i120;
-    input fabric_fpga_rdata_axi_s1_i121;
-    input fabric_fpga_rdata_axi_s1_i122;
-    input fabric_fpga_rdata_axi_s1_i123;
-    input fabric_fpga_rdata_axi_s1_i124;
-    input fabric_fpga_rdata_axi_s1_i125;
-    input fabric_fpga_rdata_axi_s1_i126;
-    input fabric_fpga_rdata_axi_s1_i127;
-    input fabric_fpga_rdata_axi_s1_i128;
-    input fabric_fpga_rdata_axi_s1_i13;
-    input fabric_fpga_rdata_axi_s1_i14;
-    input fabric_fpga_rdata_axi_s1_i15;
-    input fabric_fpga_rdata_axi_s1_i16;
-    input fabric_fpga_rdata_axi_s1_i17;
-    input fabric_fpga_rdata_axi_s1_i18;
-    input fabric_fpga_rdata_axi_s1_i19;
-    input fabric_fpga_rdata_axi_s1_i2;
-    input fabric_fpga_rdata_axi_s1_i20;
-    input fabric_fpga_rdata_axi_s1_i21;
-    input fabric_fpga_rdata_axi_s1_i22;
-    input fabric_fpga_rdata_axi_s1_i23;
-    input fabric_fpga_rdata_axi_s1_i24;
-    input fabric_fpga_rdata_axi_s1_i25;
-    input fabric_fpga_rdata_axi_s1_i26;
-    input fabric_fpga_rdata_axi_s1_i27;
-    input fabric_fpga_rdata_axi_s1_i28;
-    input fabric_fpga_rdata_axi_s1_i29;
-    input fabric_fpga_rdata_axi_s1_i3;
-    input fabric_fpga_rdata_axi_s1_i30;
-    input fabric_fpga_rdata_axi_s1_i31;
-    input fabric_fpga_rdata_axi_s1_i32;
-    input fabric_fpga_rdata_axi_s1_i33;
-    input fabric_fpga_rdata_axi_s1_i34;
-    input fabric_fpga_rdata_axi_s1_i35;
-    input fabric_fpga_rdata_axi_s1_i36;
-    input fabric_fpga_rdata_axi_s1_i37;
-    input fabric_fpga_rdata_axi_s1_i38;
-    input fabric_fpga_rdata_axi_s1_i39;
-    input fabric_fpga_rdata_axi_s1_i4;
-    input fabric_fpga_rdata_axi_s1_i40;
-    input fabric_fpga_rdata_axi_s1_i41;
-    input fabric_fpga_rdata_axi_s1_i42;
-    input fabric_fpga_rdata_axi_s1_i43;
-    input fabric_fpga_rdata_axi_s1_i44;
-    input fabric_fpga_rdata_axi_s1_i45;
-    input fabric_fpga_rdata_axi_s1_i46;
-    input fabric_fpga_rdata_axi_s1_i47;
-    input fabric_fpga_rdata_axi_s1_i48;
-    input fabric_fpga_rdata_axi_s1_i49;
-    input fabric_fpga_rdata_axi_s1_i5;
-    input fabric_fpga_rdata_axi_s1_i50;
-    input fabric_fpga_rdata_axi_s1_i51;
-    input fabric_fpga_rdata_axi_s1_i52;
-    input fabric_fpga_rdata_axi_s1_i53;
-    input fabric_fpga_rdata_axi_s1_i54;
-    input fabric_fpga_rdata_axi_s1_i55;
-    input fabric_fpga_rdata_axi_s1_i56;
-    input fabric_fpga_rdata_axi_s1_i57;
-    input fabric_fpga_rdata_axi_s1_i58;
-    input fabric_fpga_rdata_axi_s1_i59;
-    input fabric_fpga_rdata_axi_s1_i6;
-    input fabric_fpga_rdata_axi_s1_i60;
-    input fabric_fpga_rdata_axi_s1_i61;
-    input fabric_fpga_rdata_axi_s1_i62;
-    input fabric_fpga_rdata_axi_s1_i63;
-    input fabric_fpga_rdata_axi_s1_i64;
-    input fabric_fpga_rdata_axi_s1_i65;
-    input fabric_fpga_rdata_axi_s1_i66;
-    input fabric_fpga_rdata_axi_s1_i67;
-    input fabric_fpga_rdata_axi_s1_i68;
-    input fabric_fpga_rdata_axi_s1_i69;
-    input fabric_fpga_rdata_axi_s1_i7;
-    input fabric_fpga_rdata_axi_s1_i70;
-    input fabric_fpga_rdata_axi_s1_i71;
-    input fabric_fpga_rdata_axi_s1_i72;
-    input fabric_fpga_rdata_axi_s1_i73;
-    input fabric_fpga_rdata_axi_s1_i74;
-    input fabric_fpga_rdata_axi_s1_i75;
-    input fabric_fpga_rdata_axi_s1_i76;
-    input fabric_fpga_rdata_axi_s1_i77;
-    input fabric_fpga_rdata_axi_s1_i78;
-    input fabric_fpga_rdata_axi_s1_i79;
-    input fabric_fpga_rdata_axi_s1_i8;
-    input fabric_fpga_rdata_axi_s1_i80;
-    input fabric_fpga_rdata_axi_s1_i81;
-    input fabric_fpga_rdata_axi_s1_i82;
-    input fabric_fpga_rdata_axi_s1_i83;
-    input fabric_fpga_rdata_axi_s1_i84;
-    input fabric_fpga_rdata_axi_s1_i85;
-    input fabric_fpga_rdata_axi_s1_i86;
-    input fabric_fpga_rdata_axi_s1_i87;
-    input fabric_fpga_rdata_axi_s1_i88;
-    input fabric_fpga_rdata_axi_s1_i89;
-    input fabric_fpga_rdata_axi_s1_i9;
-    input fabric_fpga_rdata_axi_s1_i90;
-    input fabric_fpga_rdata_axi_s1_i91;
-    input fabric_fpga_rdata_axi_s1_i92;
-    input fabric_fpga_rdata_axi_s1_i93;
-    input fabric_fpga_rdata_axi_s1_i94;
-    input fabric_fpga_rdata_axi_s1_i95;
-    input fabric_fpga_rdata_axi_s1_i96;
-    input fabric_fpga_rdata_axi_s1_i97;
-    input fabric_fpga_rdata_axi_s1_i98;
-    input fabric_fpga_rdata_axi_s1_i99;
-    input fabric_fpga_rdata_axi_s2_i1;
-    input fabric_fpga_rdata_axi_s2_i10;
-    input fabric_fpga_rdata_axi_s2_i100;
-    input fabric_fpga_rdata_axi_s2_i101;
-    input fabric_fpga_rdata_axi_s2_i102;
-    input fabric_fpga_rdata_axi_s2_i103;
-    input fabric_fpga_rdata_axi_s2_i104;
-    input fabric_fpga_rdata_axi_s2_i105;
-    input fabric_fpga_rdata_axi_s2_i106;
-    input fabric_fpga_rdata_axi_s2_i107;
-    input fabric_fpga_rdata_axi_s2_i108;
-    input fabric_fpga_rdata_axi_s2_i109;
-    input fabric_fpga_rdata_axi_s2_i11;
-    input fabric_fpga_rdata_axi_s2_i110;
-    input fabric_fpga_rdata_axi_s2_i111;
-    input fabric_fpga_rdata_axi_s2_i112;
-    input fabric_fpga_rdata_axi_s2_i113;
-    input fabric_fpga_rdata_axi_s2_i114;
-    input fabric_fpga_rdata_axi_s2_i115;
-    input fabric_fpga_rdata_axi_s2_i116;
-    input fabric_fpga_rdata_axi_s2_i117;
-    input fabric_fpga_rdata_axi_s2_i118;
-    input fabric_fpga_rdata_axi_s2_i119;
-    input fabric_fpga_rdata_axi_s2_i12;
-    input fabric_fpga_rdata_axi_s2_i120;
-    input fabric_fpga_rdata_axi_s2_i121;
-    input fabric_fpga_rdata_axi_s2_i122;
-    input fabric_fpga_rdata_axi_s2_i123;
-    input fabric_fpga_rdata_axi_s2_i124;
-    input fabric_fpga_rdata_axi_s2_i125;
-    input fabric_fpga_rdata_axi_s2_i126;
-    input fabric_fpga_rdata_axi_s2_i127;
-    input fabric_fpga_rdata_axi_s2_i128;
-    input fabric_fpga_rdata_axi_s2_i13;
-    input fabric_fpga_rdata_axi_s2_i14;
-    input fabric_fpga_rdata_axi_s2_i15;
-    input fabric_fpga_rdata_axi_s2_i16;
-    input fabric_fpga_rdata_axi_s2_i17;
-    input fabric_fpga_rdata_axi_s2_i18;
-    input fabric_fpga_rdata_axi_s2_i19;
-    input fabric_fpga_rdata_axi_s2_i2;
-    input fabric_fpga_rdata_axi_s2_i20;
-    input fabric_fpga_rdata_axi_s2_i21;
-    input fabric_fpga_rdata_axi_s2_i22;
-    input fabric_fpga_rdata_axi_s2_i23;
-    input fabric_fpga_rdata_axi_s2_i24;
-    input fabric_fpga_rdata_axi_s2_i25;
-    input fabric_fpga_rdata_axi_s2_i26;
-    input fabric_fpga_rdata_axi_s2_i27;
-    input fabric_fpga_rdata_axi_s2_i28;
-    input fabric_fpga_rdata_axi_s2_i29;
-    input fabric_fpga_rdata_axi_s2_i3;
-    input fabric_fpga_rdata_axi_s2_i30;
-    input fabric_fpga_rdata_axi_s2_i31;
-    input fabric_fpga_rdata_axi_s2_i32;
-    input fabric_fpga_rdata_axi_s2_i33;
-    input fabric_fpga_rdata_axi_s2_i34;
-    input fabric_fpga_rdata_axi_s2_i35;
-    input fabric_fpga_rdata_axi_s2_i36;
-    input fabric_fpga_rdata_axi_s2_i37;
-    input fabric_fpga_rdata_axi_s2_i38;
-    input fabric_fpga_rdata_axi_s2_i39;
-    input fabric_fpga_rdata_axi_s2_i4;
-    input fabric_fpga_rdata_axi_s2_i40;
-    input fabric_fpga_rdata_axi_s2_i41;
-    input fabric_fpga_rdata_axi_s2_i42;
-    input fabric_fpga_rdata_axi_s2_i43;
-    input fabric_fpga_rdata_axi_s2_i44;
-    input fabric_fpga_rdata_axi_s2_i45;
-    input fabric_fpga_rdata_axi_s2_i46;
-    input fabric_fpga_rdata_axi_s2_i47;
-    input fabric_fpga_rdata_axi_s2_i48;
-    input fabric_fpga_rdata_axi_s2_i49;
-    input fabric_fpga_rdata_axi_s2_i5;
-    input fabric_fpga_rdata_axi_s2_i50;
-    input fabric_fpga_rdata_axi_s2_i51;
-    input fabric_fpga_rdata_axi_s2_i52;
-    input fabric_fpga_rdata_axi_s2_i53;
-    input fabric_fpga_rdata_axi_s2_i54;
-    input fabric_fpga_rdata_axi_s2_i55;
-    input fabric_fpga_rdata_axi_s2_i56;
-    input fabric_fpga_rdata_axi_s2_i57;
-    input fabric_fpga_rdata_axi_s2_i58;
-    input fabric_fpga_rdata_axi_s2_i59;
-    input fabric_fpga_rdata_axi_s2_i6;
-    input fabric_fpga_rdata_axi_s2_i60;
-    input fabric_fpga_rdata_axi_s2_i61;
-    input fabric_fpga_rdata_axi_s2_i62;
-    input fabric_fpga_rdata_axi_s2_i63;
-    input fabric_fpga_rdata_axi_s2_i64;
-    input fabric_fpga_rdata_axi_s2_i65;
-    input fabric_fpga_rdata_axi_s2_i66;
-    input fabric_fpga_rdata_axi_s2_i67;
-    input fabric_fpga_rdata_axi_s2_i68;
-    input fabric_fpga_rdata_axi_s2_i69;
-    input fabric_fpga_rdata_axi_s2_i7;
-    input fabric_fpga_rdata_axi_s2_i70;
-    input fabric_fpga_rdata_axi_s2_i71;
-    input fabric_fpga_rdata_axi_s2_i72;
-    input fabric_fpga_rdata_axi_s2_i73;
-    input fabric_fpga_rdata_axi_s2_i74;
-    input fabric_fpga_rdata_axi_s2_i75;
-    input fabric_fpga_rdata_axi_s2_i76;
-    input fabric_fpga_rdata_axi_s2_i77;
-    input fabric_fpga_rdata_axi_s2_i78;
-    input fabric_fpga_rdata_axi_s2_i79;
-    input fabric_fpga_rdata_axi_s2_i8;
-    input fabric_fpga_rdata_axi_s2_i80;
-    input fabric_fpga_rdata_axi_s2_i81;
-    input fabric_fpga_rdata_axi_s2_i82;
-    input fabric_fpga_rdata_axi_s2_i83;
-    input fabric_fpga_rdata_axi_s2_i84;
-    input fabric_fpga_rdata_axi_s2_i85;
-    input fabric_fpga_rdata_axi_s2_i86;
-    input fabric_fpga_rdata_axi_s2_i87;
-    input fabric_fpga_rdata_axi_s2_i88;
-    input fabric_fpga_rdata_axi_s2_i89;
-    input fabric_fpga_rdata_axi_s2_i9;
-    input fabric_fpga_rdata_axi_s2_i90;
-    input fabric_fpga_rdata_axi_s2_i91;
-    input fabric_fpga_rdata_axi_s2_i92;
-    input fabric_fpga_rdata_axi_s2_i93;
-    input fabric_fpga_rdata_axi_s2_i94;
-    input fabric_fpga_rdata_axi_s2_i95;
-    input fabric_fpga_rdata_axi_s2_i96;
-    input fabric_fpga_rdata_axi_s2_i97;
-    input fabric_fpga_rdata_axi_s2_i98;
-    input fabric_fpga_rdata_axi_s2_i99;
-    output fabric_fpga_rid_axi_m1_o1;
-    output fabric_fpga_rid_axi_m1_o2;
-    output fabric_fpga_rid_axi_m1_o3;
-    output fabric_fpga_rid_axi_m1_o4;
-    output fabric_fpga_rid_axi_m1_o5;
-    output fabric_fpga_rid_axi_m2_o1;
-    output fabric_fpga_rid_axi_m2_o2;
-    output fabric_fpga_rid_axi_m2_o3;
-    output fabric_fpga_rid_axi_m2_o4;
-    output fabric_fpga_rid_axi_m2_o5;
-    input fabric_fpga_rid_axi_s1_i1;
-    input fabric_fpga_rid_axi_s1_i10;
-    input fabric_fpga_rid_axi_s1_i11;
-    input fabric_fpga_rid_axi_s1_i12;
-    input fabric_fpga_rid_axi_s1_i2;
-    input fabric_fpga_rid_axi_s1_i3;
-    input fabric_fpga_rid_axi_s1_i4;
-    input fabric_fpga_rid_axi_s1_i5;
-    input fabric_fpga_rid_axi_s1_i6;
-    input fabric_fpga_rid_axi_s1_i7;
-    input fabric_fpga_rid_axi_s1_i8;
-    input fabric_fpga_rid_axi_s1_i9;
-    input fabric_fpga_rid_axi_s2_i1;
-    input fabric_fpga_rid_axi_s2_i10;
-    input fabric_fpga_rid_axi_s2_i11;
-    input fabric_fpga_rid_axi_s2_i12;
-    input fabric_fpga_rid_axi_s2_i2;
-    input fabric_fpga_rid_axi_s2_i3;
-    input fabric_fpga_rid_axi_s2_i4;
-    input fabric_fpga_rid_axi_s2_i5;
-    input fabric_fpga_rid_axi_s2_i6;
-    input fabric_fpga_rid_axi_s2_i7;
-    input fabric_fpga_rid_axi_s2_i8;
-    input fabric_fpga_rid_axi_s2_i9;
-    output fabric_fpga_rlast_axi_m1_o;
-    output fabric_fpga_rlast_axi_m2_o;
-    input fabric_fpga_rlast_axi_s1_i;
-    input fabric_fpga_rlast_axi_s2_i;
-    input fabric_fpga_rready_axi_m1_i;
-    input fabric_fpga_rready_axi_m2_i;
-    output fabric_fpga_rready_axi_s1_o;
-    output fabric_fpga_rready_axi_s2_o;
-    output fabric_fpga_rresp_axi_m1_o1;
-    output fabric_fpga_rresp_axi_m1_o2;
-    output fabric_fpga_rresp_axi_m2_o1;
-    output fabric_fpga_rresp_axi_m2_o2;
-    input fabric_fpga_rresp_axi_s1_i1;
-    input fabric_fpga_rresp_axi_s1_i2;
-    input fabric_fpga_rresp_axi_s2_i1;
-    input fabric_fpga_rresp_axi_s2_i2;
-    output fabric_fpga_rvalid_axi_m1_o;
-    output fabric_fpga_rvalid_axi_m2_o;
-    input fabric_fpga_rvalid_axi_s1_i;
-    input fabric_fpga_rvalid_axi_s2_i;
-    input fabric_fpga_sysrstn_i;
-    output fabric_fpga_trigger_in_o1;
-    output fabric_fpga_trigger_in_o2;
-    output fabric_fpga_trigger_in_o3;
-    output fabric_fpga_trigger_in_o4;
-    output fabric_fpga_trigger_in_o5;
-    output fabric_fpga_trigger_in_o6;
-    output fabric_fpga_trigger_in_o7;
-    output fabric_fpga_trigger_in_o8;
-    input fabric_fpga_trigger_out_i1;
-    input fabric_fpga_trigger_out_i2;
-    input fabric_fpga_trigger_out_i3;
-    input fabric_fpga_trigger_out_i4;
-    input fabric_fpga_trigger_out_i5;
-    input fabric_fpga_trigger_out_i6;
-    input fabric_fpga_trigger_out_i7;
-    input fabric_fpga_trigger_out_i8;
-    input fabric_fpga_wdata_axi_m1_i1;
-    input fabric_fpga_wdata_axi_m1_i10;
-    input fabric_fpga_wdata_axi_m1_i100;
-    input fabric_fpga_wdata_axi_m1_i101;
-    input fabric_fpga_wdata_axi_m1_i102;
-    input fabric_fpga_wdata_axi_m1_i103;
-    input fabric_fpga_wdata_axi_m1_i104;
-    input fabric_fpga_wdata_axi_m1_i105;
-    input fabric_fpga_wdata_axi_m1_i106;
-    input fabric_fpga_wdata_axi_m1_i107;
-    input fabric_fpga_wdata_axi_m1_i108;
-    input fabric_fpga_wdata_axi_m1_i109;
-    input fabric_fpga_wdata_axi_m1_i11;
-    input fabric_fpga_wdata_axi_m1_i110;
-    input fabric_fpga_wdata_axi_m1_i111;
-    input fabric_fpga_wdata_axi_m1_i112;
-    input fabric_fpga_wdata_axi_m1_i113;
-    input fabric_fpga_wdata_axi_m1_i114;
-    input fabric_fpga_wdata_axi_m1_i115;
-    input fabric_fpga_wdata_axi_m1_i116;
-    input fabric_fpga_wdata_axi_m1_i117;
-    input fabric_fpga_wdata_axi_m1_i118;
-    input fabric_fpga_wdata_axi_m1_i119;
-    input fabric_fpga_wdata_axi_m1_i12;
-    input fabric_fpga_wdata_axi_m1_i120;
-    input fabric_fpga_wdata_axi_m1_i121;
-    input fabric_fpga_wdata_axi_m1_i122;
-    input fabric_fpga_wdata_axi_m1_i123;
-    input fabric_fpga_wdata_axi_m1_i124;
-    input fabric_fpga_wdata_axi_m1_i125;
-    input fabric_fpga_wdata_axi_m1_i126;
-    input fabric_fpga_wdata_axi_m1_i127;
-    input fabric_fpga_wdata_axi_m1_i128;
-    input fabric_fpga_wdata_axi_m1_i13;
-    input fabric_fpga_wdata_axi_m1_i14;
-    input fabric_fpga_wdata_axi_m1_i15;
-    input fabric_fpga_wdata_axi_m1_i16;
-    input fabric_fpga_wdata_axi_m1_i17;
-    input fabric_fpga_wdata_axi_m1_i18;
-    input fabric_fpga_wdata_axi_m1_i19;
-    input fabric_fpga_wdata_axi_m1_i2;
-    input fabric_fpga_wdata_axi_m1_i20;
-    input fabric_fpga_wdata_axi_m1_i21;
-    input fabric_fpga_wdata_axi_m1_i22;
-    input fabric_fpga_wdata_axi_m1_i23;
-    input fabric_fpga_wdata_axi_m1_i24;
-    input fabric_fpga_wdata_axi_m1_i25;
-    input fabric_fpga_wdata_axi_m1_i26;
-    input fabric_fpga_wdata_axi_m1_i27;
-    input fabric_fpga_wdata_axi_m1_i28;
-    input fabric_fpga_wdata_axi_m1_i29;
-    input fabric_fpga_wdata_axi_m1_i3;
-    input fabric_fpga_wdata_axi_m1_i30;
-    input fabric_fpga_wdata_axi_m1_i31;
-    input fabric_fpga_wdata_axi_m1_i32;
-    input fabric_fpga_wdata_axi_m1_i33;
-    input fabric_fpga_wdata_axi_m1_i34;
-    input fabric_fpga_wdata_axi_m1_i35;
-    input fabric_fpga_wdata_axi_m1_i36;
-    input fabric_fpga_wdata_axi_m1_i37;
-    input fabric_fpga_wdata_axi_m1_i38;
-    input fabric_fpga_wdata_axi_m1_i39;
-    input fabric_fpga_wdata_axi_m1_i4;
-    input fabric_fpga_wdata_axi_m1_i40;
-    input fabric_fpga_wdata_axi_m1_i41;
-    input fabric_fpga_wdata_axi_m1_i42;
-    input fabric_fpga_wdata_axi_m1_i43;
-    input fabric_fpga_wdata_axi_m1_i44;
-    input fabric_fpga_wdata_axi_m1_i45;
-    input fabric_fpga_wdata_axi_m1_i46;
-    input fabric_fpga_wdata_axi_m1_i47;
-    input fabric_fpga_wdata_axi_m1_i48;
-    input fabric_fpga_wdata_axi_m1_i49;
-    input fabric_fpga_wdata_axi_m1_i5;
-    input fabric_fpga_wdata_axi_m1_i50;
-    input fabric_fpga_wdata_axi_m1_i51;
-    input fabric_fpga_wdata_axi_m1_i52;
-    input fabric_fpga_wdata_axi_m1_i53;
-    input fabric_fpga_wdata_axi_m1_i54;
-    input fabric_fpga_wdata_axi_m1_i55;
-    input fabric_fpga_wdata_axi_m1_i56;
-    input fabric_fpga_wdata_axi_m1_i57;
-    input fabric_fpga_wdata_axi_m1_i58;
-    input fabric_fpga_wdata_axi_m1_i59;
-    input fabric_fpga_wdata_axi_m1_i6;
-    input fabric_fpga_wdata_axi_m1_i60;
-    input fabric_fpga_wdata_axi_m1_i61;
-    input fabric_fpga_wdata_axi_m1_i62;
-    input fabric_fpga_wdata_axi_m1_i63;
-    input fabric_fpga_wdata_axi_m1_i64;
-    input fabric_fpga_wdata_axi_m1_i65;
-    input fabric_fpga_wdata_axi_m1_i66;
-    input fabric_fpga_wdata_axi_m1_i67;
-    input fabric_fpga_wdata_axi_m1_i68;
-    input fabric_fpga_wdata_axi_m1_i69;
-    input fabric_fpga_wdata_axi_m1_i7;
-    input fabric_fpga_wdata_axi_m1_i70;
-    input fabric_fpga_wdata_axi_m1_i71;
-    input fabric_fpga_wdata_axi_m1_i72;
-    input fabric_fpga_wdata_axi_m1_i73;
-    input fabric_fpga_wdata_axi_m1_i74;
-    input fabric_fpga_wdata_axi_m1_i75;
-    input fabric_fpga_wdata_axi_m1_i76;
-    input fabric_fpga_wdata_axi_m1_i77;
-    input fabric_fpga_wdata_axi_m1_i78;
-    input fabric_fpga_wdata_axi_m1_i79;
-    input fabric_fpga_wdata_axi_m1_i8;
-    input fabric_fpga_wdata_axi_m1_i80;
-    input fabric_fpga_wdata_axi_m1_i81;
-    input fabric_fpga_wdata_axi_m1_i82;
-    input fabric_fpga_wdata_axi_m1_i83;
-    input fabric_fpga_wdata_axi_m1_i84;
-    input fabric_fpga_wdata_axi_m1_i85;
-    input fabric_fpga_wdata_axi_m1_i86;
-    input fabric_fpga_wdata_axi_m1_i87;
-    input fabric_fpga_wdata_axi_m1_i88;
-    input fabric_fpga_wdata_axi_m1_i89;
-    input fabric_fpga_wdata_axi_m1_i9;
-    input fabric_fpga_wdata_axi_m1_i90;
-    input fabric_fpga_wdata_axi_m1_i91;
-    input fabric_fpga_wdata_axi_m1_i92;
-    input fabric_fpga_wdata_axi_m1_i93;
-    input fabric_fpga_wdata_axi_m1_i94;
-    input fabric_fpga_wdata_axi_m1_i95;
-    input fabric_fpga_wdata_axi_m1_i96;
-    input fabric_fpga_wdata_axi_m1_i97;
-    input fabric_fpga_wdata_axi_m1_i98;
-    input fabric_fpga_wdata_axi_m1_i99;
-    input fabric_fpga_wdata_axi_m2_i1;
-    input fabric_fpga_wdata_axi_m2_i10;
-    input fabric_fpga_wdata_axi_m2_i100;
-    input fabric_fpga_wdata_axi_m2_i101;
-    input fabric_fpga_wdata_axi_m2_i102;
-    input fabric_fpga_wdata_axi_m2_i103;
-    input fabric_fpga_wdata_axi_m2_i104;
-    input fabric_fpga_wdata_axi_m2_i105;
-    input fabric_fpga_wdata_axi_m2_i106;
-    input fabric_fpga_wdata_axi_m2_i107;
-    input fabric_fpga_wdata_axi_m2_i108;
-    input fabric_fpga_wdata_axi_m2_i109;
-    input fabric_fpga_wdata_axi_m2_i11;
-    input fabric_fpga_wdata_axi_m2_i110;
-    input fabric_fpga_wdata_axi_m2_i111;
-    input fabric_fpga_wdata_axi_m2_i112;
-    input fabric_fpga_wdata_axi_m2_i113;
-    input fabric_fpga_wdata_axi_m2_i114;
-    input fabric_fpga_wdata_axi_m2_i115;
-    input fabric_fpga_wdata_axi_m2_i116;
-    input fabric_fpga_wdata_axi_m2_i117;
-    input fabric_fpga_wdata_axi_m2_i118;
-    input fabric_fpga_wdata_axi_m2_i119;
-    input fabric_fpga_wdata_axi_m2_i12;
-    input fabric_fpga_wdata_axi_m2_i120;
-    input fabric_fpga_wdata_axi_m2_i121;
-    input fabric_fpga_wdata_axi_m2_i122;
-    input fabric_fpga_wdata_axi_m2_i123;
-    input fabric_fpga_wdata_axi_m2_i124;
-    input fabric_fpga_wdata_axi_m2_i125;
-    input fabric_fpga_wdata_axi_m2_i126;
-    input fabric_fpga_wdata_axi_m2_i127;
-    input fabric_fpga_wdata_axi_m2_i128;
-    input fabric_fpga_wdata_axi_m2_i13;
-    input fabric_fpga_wdata_axi_m2_i14;
-    input fabric_fpga_wdata_axi_m2_i15;
-    input fabric_fpga_wdata_axi_m2_i16;
-    input fabric_fpga_wdata_axi_m2_i17;
-    input fabric_fpga_wdata_axi_m2_i18;
-    input fabric_fpga_wdata_axi_m2_i19;
-    input fabric_fpga_wdata_axi_m2_i2;
-    input fabric_fpga_wdata_axi_m2_i20;
-    input fabric_fpga_wdata_axi_m2_i21;
-    input fabric_fpga_wdata_axi_m2_i22;
-    input fabric_fpga_wdata_axi_m2_i23;
-    input fabric_fpga_wdata_axi_m2_i24;
-    input fabric_fpga_wdata_axi_m2_i25;
-    input fabric_fpga_wdata_axi_m2_i26;
-    input fabric_fpga_wdata_axi_m2_i27;
-    input fabric_fpga_wdata_axi_m2_i28;
-    input fabric_fpga_wdata_axi_m2_i29;
-    input fabric_fpga_wdata_axi_m2_i3;
-    input fabric_fpga_wdata_axi_m2_i30;
-    input fabric_fpga_wdata_axi_m2_i31;
-    input fabric_fpga_wdata_axi_m2_i32;
-    input fabric_fpga_wdata_axi_m2_i33;
-    input fabric_fpga_wdata_axi_m2_i34;
-    input fabric_fpga_wdata_axi_m2_i35;
-    input fabric_fpga_wdata_axi_m2_i36;
-    input fabric_fpga_wdata_axi_m2_i37;
-    input fabric_fpga_wdata_axi_m2_i38;
-    input fabric_fpga_wdata_axi_m2_i39;
-    input fabric_fpga_wdata_axi_m2_i4;
-    input fabric_fpga_wdata_axi_m2_i40;
-    input fabric_fpga_wdata_axi_m2_i41;
-    input fabric_fpga_wdata_axi_m2_i42;
-    input fabric_fpga_wdata_axi_m2_i43;
-    input fabric_fpga_wdata_axi_m2_i44;
-    input fabric_fpga_wdata_axi_m2_i45;
-    input fabric_fpga_wdata_axi_m2_i46;
-    input fabric_fpga_wdata_axi_m2_i47;
-    input fabric_fpga_wdata_axi_m2_i48;
-    input fabric_fpga_wdata_axi_m2_i49;
-    input fabric_fpga_wdata_axi_m2_i5;
-    input fabric_fpga_wdata_axi_m2_i50;
-    input fabric_fpga_wdata_axi_m2_i51;
-    input fabric_fpga_wdata_axi_m2_i52;
-    input fabric_fpga_wdata_axi_m2_i53;
-    input fabric_fpga_wdata_axi_m2_i54;
-    input fabric_fpga_wdata_axi_m2_i55;
-    input fabric_fpga_wdata_axi_m2_i56;
-    input fabric_fpga_wdata_axi_m2_i57;
-    input fabric_fpga_wdata_axi_m2_i58;
-    input fabric_fpga_wdata_axi_m2_i59;
-    input fabric_fpga_wdata_axi_m2_i6;
-    input fabric_fpga_wdata_axi_m2_i60;
-    input fabric_fpga_wdata_axi_m2_i61;
-    input fabric_fpga_wdata_axi_m2_i62;
-    input fabric_fpga_wdata_axi_m2_i63;
-    input fabric_fpga_wdata_axi_m2_i64;
-    input fabric_fpga_wdata_axi_m2_i65;
-    input fabric_fpga_wdata_axi_m2_i66;
-    input fabric_fpga_wdata_axi_m2_i67;
-    input fabric_fpga_wdata_axi_m2_i68;
-    input fabric_fpga_wdata_axi_m2_i69;
-    input fabric_fpga_wdata_axi_m2_i7;
-    input fabric_fpga_wdata_axi_m2_i70;
-    input fabric_fpga_wdata_axi_m2_i71;
-    input fabric_fpga_wdata_axi_m2_i72;
-    input fabric_fpga_wdata_axi_m2_i73;
-    input fabric_fpga_wdata_axi_m2_i74;
-    input fabric_fpga_wdata_axi_m2_i75;
-    input fabric_fpga_wdata_axi_m2_i76;
-    input fabric_fpga_wdata_axi_m2_i77;
-    input fabric_fpga_wdata_axi_m2_i78;
-    input fabric_fpga_wdata_axi_m2_i79;
-    input fabric_fpga_wdata_axi_m2_i8;
-    input fabric_fpga_wdata_axi_m2_i80;
-    input fabric_fpga_wdata_axi_m2_i81;
-    input fabric_fpga_wdata_axi_m2_i82;
-    input fabric_fpga_wdata_axi_m2_i83;
-    input fabric_fpga_wdata_axi_m2_i84;
-    input fabric_fpga_wdata_axi_m2_i85;
-    input fabric_fpga_wdata_axi_m2_i86;
-    input fabric_fpga_wdata_axi_m2_i87;
-    input fabric_fpga_wdata_axi_m2_i88;
-    input fabric_fpga_wdata_axi_m2_i89;
-    input fabric_fpga_wdata_axi_m2_i9;
-    input fabric_fpga_wdata_axi_m2_i90;
-    input fabric_fpga_wdata_axi_m2_i91;
-    input fabric_fpga_wdata_axi_m2_i92;
-    input fabric_fpga_wdata_axi_m2_i93;
-    input fabric_fpga_wdata_axi_m2_i94;
-    input fabric_fpga_wdata_axi_m2_i95;
-    input fabric_fpga_wdata_axi_m2_i96;
-    input fabric_fpga_wdata_axi_m2_i97;
-    input fabric_fpga_wdata_axi_m2_i98;
-    input fabric_fpga_wdata_axi_m2_i99;
-    output fabric_fpga_wdata_axi_s1_o1;
-    output fabric_fpga_wdata_axi_s1_o10;
-    output fabric_fpga_wdata_axi_s1_o100;
-    output fabric_fpga_wdata_axi_s1_o101;
-    output fabric_fpga_wdata_axi_s1_o102;
-    output fabric_fpga_wdata_axi_s1_o103;
-    output fabric_fpga_wdata_axi_s1_o104;
-    output fabric_fpga_wdata_axi_s1_o105;
-    output fabric_fpga_wdata_axi_s1_o106;
-    output fabric_fpga_wdata_axi_s1_o107;
-    output fabric_fpga_wdata_axi_s1_o108;
-    output fabric_fpga_wdata_axi_s1_o109;
-    output fabric_fpga_wdata_axi_s1_o11;
-    output fabric_fpga_wdata_axi_s1_o110;
-    output fabric_fpga_wdata_axi_s1_o111;
-    output fabric_fpga_wdata_axi_s1_o112;
-    output fabric_fpga_wdata_axi_s1_o113;
-    output fabric_fpga_wdata_axi_s1_o114;
-    output fabric_fpga_wdata_axi_s1_o115;
-    output fabric_fpga_wdata_axi_s1_o116;
-    output fabric_fpga_wdata_axi_s1_o117;
-    output fabric_fpga_wdata_axi_s1_o118;
-    output fabric_fpga_wdata_axi_s1_o119;
-    output fabric_fpga_wdata_axi_s1_o12;
-    output fabric_fpga_wdata_axi_s1_o120;
-    output fabric_fpga_wdata_axi_s1_o121;
-    output fabric_fpga_wdata_axi_s1_o122;
-    output fabric_fpga_wdata_axi_s1_o123;
-    output fabric_fpga_wdata_axi_s1_o124;
-    output fabric_fpga_wdata_axi_s1_o125;
-    output fabric_fpga_wdata_axi_s1_o126;
-    output fabric_fpga_wdata_axi_s1_o127;
-    output fabric_fpga_wdata_axi_s1_o128;
-    output fabric_fpga_wdata_axi_s1_o13;
-    output fabric_fpga_wdata_axi_s1_o14;
-    output fabric_fpga_wdata_axi_s1_o15;
-    output fabric_fpga_wdata_axi_s1_o16;
-    output fabric_fpga_wdata_axi_s1_o17;
-    output fabric_fpga_wdata_axi_s1_o18;
-    output fabric_fpga_wdata_axi_s1_o19;
-    output fabric_fpga_wdata_axi_s1_o2;
-    output fabric_fpga_wdata_axi_s1_o20;
-    output fabric_fpga_wdata_axi_s1_o21;
-    output fabric_fpga_wdata_axi_s1_o22;
-    output fabric_fpga_wdata_axi_s1_o23;
-    output fabric_fpga_wdata_axi_s1_o24;
-    output fabric_fpga_wdata_axi_s1_o25;
-    output fabric_fpga_wdata_axi_s1_o26;
-    output fabric_fpga_wdata_axi_s1_o27;
-    output fabric_fpga_wdata_axi_s1_o28;
-    output fabric_fpga_wdata_axi_s1_o29;
-    output fabric_fpga_wdata_axi_s1_o3;
-    output fabric_fpga_wdata_axi_s1_o30;
-    output fabric_fpga_wdata_axi_s1_o31;
-    output fabric_fpga_wdata_axi_s1_o32;
-    output fabric_fpga_wdata_axi_s1_o33;
-    output fabric_fpga_wdata_axi_s1_o34;
-    output fabric_fpga_wdata_axi_s1_o35;
-    output fabric_fpga_wdata_axi_s1_o36;
-    output fabric_fpga_wdata_axi_s1_o37;
-    output fabric_fpga_wdata_axi_s1_o38;
-    output fabric_fpga_wdata_axi_s1_o39;
-    output fabric_fpga_wdata_axi_s1_o4;
-    output fabric_fpga_wdata_axi_s1_o40;
-    output fabric_fpga_wdata_axi_s1_o41;
-    output fabric_fpga_wdata_axi_s1_o42;
-    output fabric_fpga_wdata_axi_s1_o43;
-    output fabric_fpga_wdata_axi_s1_o44;
-    output fabric_fpga_wdata_axi_s1_o45;
-    output fabric_fpga_wdata_axi_s1_o46;
-    output fabric_fpga_wdata_axi_s1_o47;
-    output fabric_fpga_wdata_axi_s1_o48;
-    output fabric_fpga_wdata_axi_s1_o49;
-    output fabric_fpga_wdata_axi_s1_o5;
-    output fabric_fpga_wdata_axi_s1_o50;
-    output fabric_fpga_wdata_axi_s1_o51;
-    output fabric_fpga_wdata_axi_s1_o52;
-    output fabric_fpga_wdata_axi_s1_o53;
-    output fabric_fpga_wdata_axi_s1_o54;
-    output fabric_fpga_wdata_axi_s1_o55;
-    output fabric_fpga_wdata_axi_s1_o56;
-    output fabric_fpga_wdata_axi_s1_o57;
-    output fabric_fpga_wdata_axi_s1_o58;
-    output fabric_fpga_wdata_axi_s1_o59;
-    output fabric_fpga_wdata_axi_s1_o6;
-    output fabric_fpga_wdata_axi_s1_o60;
-    output fabric_fpga_wdata_axi_s1_o61;
-    output fabric_fpga_wdata_axi_s1_o62;
-    output fabric_fpga_wdata_axi_s1_o63;
-    output fabric_fpga_wdata_axi_s1_o64;
-    output fabric_fpga_wdata_axi_s1_o65;
-    output fabric_fpga_wdata_axi_s1_o66;
-    output fabric_fpga_wdata_axi_s1_o67;
-    output fabric_fpga_wdata_axi_s1_o68;
-    output fabric_fpga_wdata_axi_s1_o69;
-    output fabric_fpga_wdata_axi_s1_o7;
-    output fabric_fpga_wdata_axi_s1_o70;
-    output fabric_fpga_wdata_axi_s1_o71;
-    output fabric_fpga_wdata_axi_s1_o72;
-    output fabric_fpga_wdata_axi_s1_o73;
-    output fabric_fpga_wdata_axi_s1_o74;
-    output fabric_fpga_wdata_axi_s1_o75;
-    output fabric_fpga_wdata_axi_s1_o76;
-    output fabric_fpga_wdata_axi_s1_o77;
-    output fabric_fpga_wdata_axi_s1_o78;
-    output fabric_fpga_wdata_axi_s1_o79;
-    output fabric_fpga_wdata_axi_s1_o8;
-    output fabric_fpga_wdata_axi_s1_o80;
-    output fabric_fpga_wdata_axi_s1_o81;
-    output fabric_fpga_wdata_axi_s1_o82;
-    output fabric_fpga_wdata_axi_s1_o83;
-    output fabric_fpga_wdata_axi_s1_o84;
-    output fabric_fpga_wdata_axi_s1_o85;
-    output fabric_fpga_wdata_axi_s1_o86;
-    output fabric_fpga_wdata_axi_s1_o87;
-    output fabric_fpga_wdata_axi_s1_o88;
-    output fabric_fpga_wdata_axi_s1_o89;
-    output fabric_fpga_wdata_axi_s1_o9;
-    output fabric_fpga_wdata_axi_s1_o90;
-    output fabric_fpga_wdata_axi_s1_o91;
-    output fabric_fpga_wdata_axi_s1_o92;
-    output fabric_fpga_wdata_axi_s1_o93;
-    output fabric_fpga_wdata_axi_s1_o94;
-    output fabric_fpga_wdata_axi_s1_o95;
-    output fabric_fpga_wdata_axi_s1_o96;
-    output fabric_fpga_wdata_axi_s1_o97;
-    output fabric_fpga_wdata_axi_s1_o98;
-    output fabric_fpga_wdata_axi_s1_o99;
-    output fabric_fpga_wdata_axi_s2_o1;
-    output fabric_fpga_wdata_axi_s2_o10;
-    output fabric_fpga_wdata_axi_s2_o100;
-    output fabric_fpga_wdata_axi_s2_o101;
-    output fabric_fpga_wdata_axi_s2_o102;
-    output fabric_fpga_wdata_axi_s2_o103;
-    output fabric_fpga_wdata_axi_s2_o104;
-    output fabric_fpga_wdata_axi_s2_o105;
-    output fabric_fpga_wdata_axi_s2_o106;
-    output fabric_fpga_wdata_axi_s2_o107;
-    output fabric_fpga_wdata_axi_s2_o108;
-    output fabric_fpga_wdata_axi_s2_o109;
-    output fabric_fpga_wdata_axi_s2_o11;
-    output fabric_fpga_wdata_axi_s2_o110;
-    output fabric_fpga_wdata_axi_s2_o111;
-    output fabric_fpga_wdata_axi_s2_o112;
-    output fabric_fpga_wdata_axi_s2_o113;
-    output fabric_fpga_wdata_axi_s2_o114;
-    output fabric_fpga_wdata_axi_s2_o115;
-    output fabric_fpga_wdata_axi_s2_o116;
-    output fabric_fpga_wdata_axi_s2_o117;
-    output fabric_fpga_wdata_axi_s2_o118;
-    output fabric_fpga_wdata_axi_s2_o119;
-    output fabric_fpga_wdata_axi_s2_o12;
-    output fabric_fpga_wdata_axi_s2_o120;
-    output fabric_fpga_wdata_axi_s2_o121;
-    output fabric_fpga_wdata_axi_s2_o122;
-    output fabric_fpga_wdata_axi_s2_o123;
-    output fabric_fpga_wdata_axi_s2_o124;
-    output fabric_fpga_wdata_axi_s2_o125;
-    output fabric_fpga_wdata_axi_s2_o126;
-    output fabric_fpga_wdata_axi_s2_o127;
-    output fabric_fpga_wdata_axi_s2_o128;
-    output fabric_fpga_wdata_axi_s2_o13;
-    output fabric_fpga_wdata_axi_s2_o14;
-    output fabric_fpga_wdata_axi_s2_o15;
-    output fabric_fpga_wdata_axi_s2_o16;
-    output fabric_fpga_wdata_axi_s2_o17;
-    output fabric_fpga_wdata_axi_s2_o18;
-    output fabric_fpga_wdata_axi_s2_o19;
-    output fabric_fpga_wdata_axi_s2_o2;
-    output fabric_fpga_wdata_axi_s2_o20;
-    output fabric_fpga_wdata_axi_s2_o21;
-    output fabric_fpga_wdata_axi_s2_o22;
-    output fabric_fpga_wdata_axi_s2_o23;
-    output fabric_fpga_wdata_axi_s2_o24;
-    output fabric_fpga_wdata_axi_s2_o25;
-    output fabric_fpga_wdata_axi_s2_o26;
-    output fabric_fpga_wdata_axi_s2_o27;
-    output fabric_fpga_wdata_axi_s2_o28;
-    output fabric_fpga_wdata_axi_s2_o29;
-    output fabric_fpga_wdata_axi_s2_o3;
-    output fabric_fpga_wdata_axi_s2_o30;
-    output fabric_fpga_wdata_axi_s2_o31;
-    output fabric_fpga_wdata_axi_s2_o32;
-    output fabric_fpga_wdata_axi_s2_o33;
-    output fabric_fpga_wdata_axi_s2_o34;
-    output fabric_fpga_wdata_axi_s2_o35;
-    output fabric_fpga_wdata_axi_s2_o36;
-    output fabric_fpga_wdata_axi_s2_o37;
-    output fabric_fpga_wdata_axi_s2_o38;
-    output fabric_fpga_wdata_axi_s2_o39;
-    output fabric_fpga_wdata_axi_s2_o4;
-    output fabric_fpga_wdata_axi_s2_o40;
-    output fabric_fpga_wdata_axi_s2_o41;
-    output fabric_fpga_wdata_axi_s2_o42;
-    output fabric_fpga_wdata_axi_s2_o43;
-    output fabric_fpga_wdata_axi_s2_o44;
-    output fabric_fpga_wdata_axi_s2_o45;
-    output fabric_fpga_wdata_axi_s2_o46;
-    output fabric_fpga_wdata_axi_s2_o47;
-    output fabric_fpga_wdata_axi_s2_o48;
-    output fabric_fpga_wdata_axi_s2_o49;
-    output fabric_fpga_wdata_axi_s2_o5;
-    output fabric_fpga_wdata_axi_s2_o50;
-    output fabric_fpga_wdata_axi_s2_o51;
-    output fabric_fpga_wdata_axi_s2_o52;
-    output fabric_fpga_wdata_axi_s2_o53;
-    output fabric_fpga_wdata_axi_s2_o54;
-    output fabric_fpga_wdata_axi_s2_o55;
-    output fabric_fpga_wdata_axi_s2_o56;
-    output fabric_fpga_wdata_axi_s2_o57;
-    output fabric_fpga_wdata_axi_s2_o58;
-    output fabric_fpga_wdata_axi_s2_o59;
-    output fabric_fpga_wdata_axi_s2_o6;
-    output fabric_fpga_wdata_axi_s2_o60;
-    output fabric_fpga_wdata_axi_s2_o61;
-    output fabric_fpga_wdata_axi_s2_o62;
-    output fabric_fpga_wdata_axi_s2_o63;
-    output fabric_fpga_wdata_axi_s2_o64;
-    output fabric_fpga_wdata_axi_s2_o65;
-    output fabric_fpga_wdata_axi_s2_o66;
-    output fabric_fpga_wdata_axi_s2_o67;
-    output fabric_fpga_wdata_axi_s2_o68;
-    output fabric_fpga_wdata_axi_s2_o69;
-    output fabric_fpga_wdata_axi_s2_o7;
-    output fabric_fpga_wdata_axi_s2_o70;
-    output fabric_fpga_wdata_axi_s2_o71;
-    output fabric_fpga_wdata_axi_s2_o72;
-    output fabric_fpga_wdata_axi_s2_o73;
-    output fabric_fpga_wdata_axi_s2_o74;
-    output fabric_fpga_wdata_axi_s2_o75;
-    output fabric_fpga_wdata_axi_s2_o76;
-    output fabric_fpga_wdata_axi_s2_o77;
-    output fabric_fpga_wdata_axi_s2_o78;
-    output fabric_fpga_wdata_axi_s2_o79;
-    output fabric_fpga_wdata_axi_s2_o8;
-    output fabric_fpga_wdata_axi_s2_o80;
-    output fabric_fpga_wdata_axi_s2_o81;
-    output fabric_fpga_wdata_axi_s2_o82;
-    output fabric_fpga_wdata_axi_s2_o83;
-    output fabric_fpga_wdata_axi_s2_o84;
-    output fabric_fpga_wdata_axi_s2_o85;
-    output fabric_fpga_wdata_axi_s2_o86;
-    output fabric_fpga_wdata_axi_s2_o87;
-    output fabric_fpga_wdata_axi_s2_o88;
-    output fabric_fpga_wdata_axi_s2_o89;
-    output fabric_fpga_wdata_axi_s2_o9;
-    output fabric_fpga_wdata_axi_s2_o90;
-    output fabric_fpga_wdata_axi_s2_o91;
-    output fabric_fpga_wdata_axi_s2_o92;
-    output fabric_fpga_wdata_axi_s2_o93;
-    output fabric_fpga_wdata_axi_s2_o94;
-    output fabric_fpga_wdata_axi_s2_o95;
-    output fabric_fpga_wdata_axi_s2_o96;
-    output fabric_fpga_wdata_axi_s2_o97;
-    output fabric_fpga_wdata_axi_s2_o98;
-    output fabric_fpga_wdata_axi_s2_o99;
-    input fabric_fpga_wlast_axi_m1_i;
-    input fabric_fpga_wlast_axi_m2_i;
-    output fabric_fpga_wlast_axi_s1_o;
-    output fabric_fpga_wlast_axi_s2_o;
-    output fabric_fpga_wready_axi_m1_o;
-    output fabric_fpga_wready_axi_m2_o;
-    input fabric_fpga_wready_axi_s1_i;
-    input fabric_fpga_wready_axi_s2_i;
-    input fabric_fpga_wstrb_axi_m1_i1;
-    input fabric_fpga_wstrb_axi_m1_i10;
-    input fabric_fpga_wstrb_axi_m1_i11;
-    input fabric_fpga_wstrb_axi_m1_i12;
-    input fabric_fpga_wstrb_axi_m1_i13;
-    input fabric_fpga_wstrb_axi_m1_i14;
-    input fabric_fpga_wstrb_axi_m1_i15;
-    input fabric_fpga_wstrb_axi_m1_i16;
-    input fabric_fpga_wstrb_axi_m1_i2;
-    input fabric_fpga_wstrb_axi_m1_i3;
-    input fabric_fpga_wstrb_axi_m1_i4;
-    input fabric_fpga_wstrb_axi_m1_i5;
-    input fabric_fpga_wstrb_axi_m1_i6;
-    input fabric_fpga_wstrb_axi_m1_i7;
-    input fabric_fpga_wstrb_axi_m1_i8;
-    input fabric_fpga_wstrb_axi_m1_i9;
-    input fabric_fpga_wstrb_axi_m2_i1;
-    input fabric_fpga_wstrb_axi_m2_i10;
-    input fabric_fpga_wstrb_axi_m2_i11;
-    input fabric_fpga_wstrb_axi_m2_i12;
-    input fabric_fpga_wstrb_axi_m2_i13;
-    input fabric_fpga_wstrb_axi_m2_i14;
-    input fabric_fpga_wstrb_axi_m2_i15;
-    input fabric_fpga_wstrb_axi_m2_i16;
-    input fabric_fpga_wstrb_axi_m2_i2;
-    input fabric_fpga_wstrb_axi_m2_i3;
-    input fabric_fpga_wstrb_axi_m2_i4;
-    input fabric_fpga_wstrb_axi_m2_i5;
-    input fabric_fpga_wstrb_axi_m2_i6;
-    input fabric_fpga_wstrb_axi_m2_i7;
-    input fabric_fpga_wstrb_axi_m2_i8;
-    input fabric_fpga_wstrb_axi_m2_i9;
-    output fabric_fpga_wstrb_axi_s1_o1;
-    output fabric_fpga_wstrb_axi_s1_o10;
-    output fabric_fpga_wstrb_axi_s1_o11;
-    output fabric_fpga_wstrb_axi_s1_o12;
-    output fabric_fpga_wstrb_axi_s1_o13;
-    output fabric_fpga_wstrb_axi_s1_o14;
-    output fabric_fpga_wstrb_axi_s1_o15;
-    output fabric_fpga_wstrb_axi_s1_o16;
-    output fabric_fpga_wstrb_axi_s1_o2;
-    output fabric_fpga_wstrb_axi_s1_o3;
-    output fabric_fpga_wstrb_axi_s1_o4;
-    output fabric_fpga_wstrb_axi_s1_o5;
-    output fabric_fpga_wstrb_axi_s1_o6;
-    output fabric_fpga_wstrb_axi_s1_o7;
-    output fabric_fpga_wstrb_axi_s1_o8;
-    output fabric_fpga_wstrb_axi_s1_o9;
-    output fabric_fpga_wstrb_axi_s2_o1;
-    output fabric_fpga_wstrb_axi_s2_o10;
-    output fabric_fpga_wstrb_axi_s2_o11;
-    output fabric_fpga_wstrb_axi_s2_o12;
-    output fabric_fpga_wstrb_axi_s2_o13;
-    output fabric_fpga_wstrb_axi_s2_o14;
-    output fabric_fpga_wstrb_axi_s2_o15;
-    output fabric_fpga_wstrb_axi_s2_o16;
-    output fabric_fpga_wstrb_axi_s2_o2;
-    output fabric_fpga_wstrb_axi_s2_o3;
-    output fabric_fpga_wstrb_axi_s2_o4;
-    output fabric_fpga_wstrb_axi_s2_o5;
-    output fabric_fpga_wstrb_axi_s2_o6;
-    output fabric_fpga_wstrb_axi_s2_o7;
-    output fabric_fpga_wstrb_axi_s2_o8;
-    output fabric_fpga_wstrb_axi_s2_o9;
-    input fabric_fpga_wvalid_axi_m1_i;
-    input fabric_fpga_wvalid_axi_m2_i;
-    output fabric_fpga_wvalid_axi_s1_o;
-    output fabric_fpga_wvalid_axi_s2_o;
-    output fabric_llpp0_araddr_s_o1;
-    output fabric_llpp0_araddr_s_o10;
-    output fabric_llpp0_araddr_s_o11;
-    output fabric_llpp0_araddr_s_o12;
-    output fabric_llpp0_araddr_s_o13;
-    output fabric_llpp0_araddr_s_o14;
-    output fabric_llpp0_araddr_s_o15;
-    output fabric_llpp0_araddr_s_o16;
-    output fabric_llpp0_araddr_s_o17;
-    output fabric_llpp0_araddr_s_o18;
-    output fabric_llpp0_araddr_s_o19;
-    output fabric_llpp0_araddr_s_o2;
-    output fabric_llpp0_araddr_s_o20;
-    output fabric_llpp0_araddr_s_o21;
-    output fabric_llpp0_araddr_s_o22;
-    output fabric_llpp0_araddr_s_o23;
-    output fabric_llpp0_araddr_s_o24;
-    output fabric_llpp0_araddr_s_o25;
-    output fabric_llpp0_araddr_s_o26;
-    output fabric_llpp0_araddr_s_o27;
-    output fabric_llpp0_araddr_s_o28;
-    output fabric_llpp0_araddr_s_o29;
-    output fabric_llpp0_araddr_s_o3;
-    output fabric_llpp0_araddr_s_o30;
-    output fabric_llpp0_araddr_s_o31;
-    output fabric_llpp0_araddr_s_o32;
-    output fabric_llpp0_araddr_s_o4;
-    output fabric_llpp0_araddr_s_o5;
-    output fabric_llpp0_araddr_s_o6;
-    output fabric_llpp0_araddr_s_o7;
-    output fabric_llpp0_araddr_s_o8;
-    output fabric_llpp0_araddr_s_o9;
-    output fabric_llpp0_arburst_s_o1;
-    output fabric_llpp0_arburst_s_o2;
-    output fabric_llpp0_arcache_s_o1;
-    output fabric_llpp0_arcache_s_o2;
-    output fabric_llpp0_arcache_s_o3;
-    output fabric_llpp0_arcache_s_o4;
-    output fabric_llpp0_arid_s_o1;
-    output fabric_llpp0_arid_s_o10;
-    output fabric_llpp0_arid_s_o11;
-    output fabric_llpp0_arid_s_o12;
-    output fabric_llpp0_arid_s_o2;
-    output fabric_llpp0_arid_s_o3;
-    output fabric_llpp0_arid_s_o4;
-    output fabric_llpp0_arid_s_o5;
-    output fabric_llpp0_arid_s_o6;
-    output fabric_llpp0_arid_s_o7;
-    output fabric_llpp0_arid_s_o8;
-    output fabric_llpp0_arid_s_o9;
-    output fabric_llpp0_arlen_s_o1;
-    output fabric_llpp0_arlen_s_o2;
-    output fabric_llpp0_arlen_s_o3;
-    output fabric_llpp0_arlen_s_o4;
-    output fabric_llpp0_arlen_s_o5;
-    output fabric_llpp0_arlen_s_o6;
-    output fabric_llpp0_arlen_s_o7;
-    output fabric_llpp0_arlen_s_o8;
-    output fabric_llpp0_arlock_s_o;
-    output fabric_llpp0_arprot_s_o1;
-    output fabric_llpp0_arprot_s_o2;
-    output fabric_llpp0_arprot_s_o3;
-    output fabric_llpp0_arqos_s_o1;
-    output fabric_llpp0_arqos_s_o2;
-    output fabric_llpp0_arqos_s_o3;
-    output fabric_llpp0_arqos_s_o4;
-    input fabric_llpp0_arready_s_i;
-    output fabric_llpp0_arsize_s_o1;
-    output fabric_llpp0_arsize_s_o2;
-    output fabric_llpp0_arsize_s_o3;
-    output fabric_llpp0_arvalid_s_o;
-    output fabric_llpp0_awaddr_s_o1;
-    output fabric_llpp0_awaddr_s_o10;
-    output fabric_llpp0_awaddr_s_o11;
-    output fabric_llpp0_awaddr_s_o12;
-    output fabric_llpp0_awaddr_s_o13;
-    output fabric_llpp0_awaddr_s_o14;
-    output fabric_llpp0_awaddr_s_o15;
-    output fabric_llpp0_awaddr_s_o16;
-    output fabric_llpp0_awaddr_s_o17;
-    output fabric_llpp0_awaddr_s_o18;
-    output fabric_llpp0_awaddr_s_o19;
-    output fabric_llpp0_awaddr_s_o2;
-    output fabric_llpp0_awaddr_s_o20;
-    output fabric_llpp0_awaddr_s_o21;
-    output fabric_llpp0_awaddr_s_o22;
-    output fabric_llpp0_awaddr_s_o23;
-    output fabric_llpp0_awaddr_s_o24;
-    output fabric_llpp0_awaddr_s_o25;
-    output fabric_llpp0_awaddr_s_o26;
-    output fabric_llpp0_awaddr_s_o27;
-    output fabric_llpp0_awaddr_s_o28;
-    output fabric_llpp0_awaddr_s_o29;
-    output fabric_llpp0_awaddr_s_o3;
-    output fabric_llpp0_awaddr_s_o30;
-    output fabric_llpp0_awaddr_s_o31;
-    output fabric_llpp0_awaddr_s_o32;
-    output fabric_llpp0_awaddr_s_o4;
-    output fabric_llpp0_awaddr_s_o5;
-    output fabric_llpp0_awaddr_s_o6;
-    output fabric_llpp0_awaddr_s_o7;
-    output fabric_llpp0_awaddr_s_o8;
-    output fabric_llpp0_awaddr_s_o9;
-    output fabric_llpp0_awburst_s_o1;
-    output fabric_llpp0_awburst_s_o2;
-    output fabric_llpp0_awcache_s_o1;
-    output fabric_llpp0_awcache_s_o2;
-    output fabric_llpp0_awcache_s_o3;
-    output fabric_llpp0_awcache_s_o4;
-    output fabric_llpp0_awid_s_o1;
-    output fabric_llpp0_awid_s_o10;
-    output fabric_llpp0_awid_s_o11;
-    output fabric_llpp0_awid_s_o12;
-    output fabric_llpp0_awid_s_o2;
-    output fabric_llpp0_awid_s_o3;
-    output fabric_llpp0_awid_s_o4;
-    output fabric_llpp0_awid_s_o5;
-    output fabric_llpp0_awid_s_o6;
-    output fabric_llpp0_awid_s_o7;
-    output fabric_llpp0_awid_s_o8;
-    output fabric_llpp0_awid_s_o9;
-    output fabric_llpp0_awlen_s_o1;
-    output fabric_llpp0_awlen_s_o2;
-    output fabric_llpp0_awlen_s_o3;
-    output fabric_llpp0_awlen_s_o4;
-    output fabric_llpp0_awlen_s_o5;
-    output fabric_llpp0_awlen_s_o6;
-    output fabric_llpp0_awlen_s_o7;
-    output fabric_llpp0_awlen_s_o8;
-    output fabric_llpp0_awlock_s_o;
-    output fabric_llpp0_awprot_s_o1;
-    output fabric_llpp0_awprot_s_o2;
-    output fabric_llpp0_awprot_s_o3;
-    output fabric_llpp0_awqos_s_o1;
-    output fabric_llpp0_awqos_s_o2;
-    output fabric_llpp0_awqos_s_o3;
-    output fabric_llpp0_awqos_s_o4;
-    input fabric_llpp0_awready_s_i;
-    output fabric_llpp0_awsize_s_o1;
-    output fabric_llpp0_awsize_s_o2;
-    output fabric_llpp0_awsize_s_o3;
-    output fabric_llpp0_awvalid_s_o;
-    input fabric_llpp0_bid_s_i1;
-    input fabric_llpp0_bid_s_i10;
-    input fabric_llpp0_bid_s_i11;
-    input fabric_llpp0_bid_s_i12;
-    input fabric_llpp0_bid_s_i2;
-    input fabric_llpp0_bid_s_i3;
-    input fabric_llpp0_bid_s_i4;
-    input fabric_llpp0_bid_s_i5;
-    input fabric_llpp0_bid_s_i6;
-    input fabric_llpp0_bid_s_i7;
-    input fabric_llpp0_bid_s_i8;
-    input fabric_llpp0_bid_s_i9;
-    output fabric_llpp0_bready_s_o;
-    input fabric_llpp0_bresp_s_i1;
-    input fabric_llpp0_bresp_s_i2;
-    input fabric_llpp0_bvalid_s_i;
-    input fabric_llpp0_rdata_s_i1;
-    input fabric_llpp0_rdata_s_i10;
-    input fabric_llpp0_rdata_s_i11;
-    input fabric_llpp0_rdata_s_i12;
-    input fabric_llpp0_rdata_s_i13;
-    input fabric_llpp0_rdata_s_i14;
-    input fabric_llpp0_rdata_s_i15;
-    input fabric_llpp0_rdata_s_i16;
-    input fabric_llpp0_rdata_s_i17;
-    input fabric_llpp0_rdata_s_i18;
-    input fabric_llpp0_rdata_s_i19;
-    input fabric_llpp0_rdata_s_i2;
-    input fabric_llpp0_rdata_s_i20;
-    input fabric_llpp0_rdata_s_i21;
-    input fabric_llpp0_rdata_s_i22;
-    input fabric_llpp0_rdata_s_i23;
-    input fabric_llpp0_rdata_s_i24;
-    input fabric_llpp0_rdata_s_i25;
-    input fabric_llpp0_rdata_s_i26;
-    input fabric_llpp0_rdata_s_i27;
-    input fabric_llpp0_rdata_s_i28;
-    input fabric_llpp0_rdata_s_i29;
-    input fabric_llpp0_rdata_s_i3;
-    input fabric_llpp0_rdata_s_i30;
-    input fabric_llpp0_rdata_s_i31;
-    input fabric_llpp0_rdata_s_i32;
-    input fabric_llpp0_rdata_s_i4;
-    input fabric_llpp0_rdata_s_i5;
-    input fabric_llpp0_rdata_s_i6;
-    input fabric_llpp0_rdata_s_i7;
-    input fabric_llpp0_rdata_s_i8;
-    input fabric_llpp0_rdata_s_i9;
-    input fabric_llpp0_rid_s_i1;
-    input fabric_llpp0_rid_s_i10;
-    input fabric_llpp0_rid_s_i11;
-    input fabric_llpp0_rid_s_i12;
-    input fabric_llpp0_rid_s_i2;
-    input fabric_llpp0_rid_s_i3;
-    input fabric_llpp0_rid_s_i4;
-    input fabric_llpp0_rid_s_i5;
-    input fabric_llpp0_rid_s_i6;
-    input fabric_llpp0_rid_s_i7;
-    input fabric_llpp0_rid_s_i8;
-    input fabric_llpp0_rid_s_i9;
-    input fabric_llpp0_rlast_s_i;
-    output fabric_llpp0_rready_s_o;
-    input fabric_llpp0_rresp_s_i1;
-    input fabric_llpp0_rresp_s_i2;
-    input fabric_llpp0_rvalid_s_i;
-    output fabric_llpp0_wdata_s_o1;
-    output fabric_llpp0_wdata_s_o10;
-    output fabric_llpp0_wdata_s_o11;
-    output fabric_llpp0_wdata_s_o12;
-    output fabric_llpp0_wdata_s_o13;
-    output fabric_llpp0_wdata_s_o14;
-    output fabric_llpp0_wdata_s_o15;
-    output fabric_llpp0_wdata_s_o16;
-    output fabric_llpp0_wdata_s_o17;
-    output fabric_llpp0_wdata_s_o18;
-    output fabric_llpp0_wdata_s_o19;
-    output fabric_llpp0_wdata_s_o2;
-    output fabric_llpp0_wdata_s_o20;
-    output fabric_llpp0_wdata_s_o21;
-    output fabric_llpp0_wdata_s_o22;
-    output fabric_llpp0_wdata_s_o23;
-    output fabric_llpp0_wdata_s_o24;
-    output fabric_llpp0_wdata_s_o25;
-    output fabric_llpp0_wdata_s_o26;
-    output fabric_llpp0_wdata_s_o27;
-    output fabric_llpp0_wdata_s_o28;
-    output fabric_llpp0_wdata_s_o29;
-    output fabric_llpp0_wdata_s_o3;
-    output fabric_llpp0_wdata_s_o30;
-    output fabric_llpp0_wdata_s_o31;
-    output fabric_llpp0_wdata_s_o32;
-    output fabric_llpp0_wdata_s_o4;
-    output fabric_llpp0_wdata_s_o5;
-    output fabric_llpp0_wdata_s_o6;
-    output fabric_llpp0_wdata_s_o7;
-    output fabric_llpp0_wdata_s_o8;
-    output fabric_llpp0_wdata_s_o9;
-    output fabric_llpp0_wlast_s_o;
-    input fabric_llpp0_wready_s_i;
-    output fabric_llpp0_wstrb_s_o1;
-    output fabric_llpp0_wstrb_s_o2;
-    output fabric_llpp0_wstrb_s_o3;
-    output fabric_llpp0_wstrb_s_o4;
-    output fabric_llpp0_wvalid_s_o;
-    output fabric_llpp1_araddr_s_o1;
-    output fabric_llpp1_araddr_s_o10;
-    output fabric_llpp1_araddr_s_o11;
-    output fabric_llpp1_araddr_s_o12;
-    output fabric_llpp1_araddr_s_o13;
-    output fabric_llpp1_araddr_s_o14;
-    output fabric_llpp1_araddr_s_o15;
-    output fabric_llpp1_araddr_s_o16;
-    output fabric_llpp1_araddr_s_o17;
-    output fabric_llpp1_araddr_s_o18;
-    output fabric_llpp1_araddr_s_o19;
-    output fabric_llpp1_araddr_s_o2;
-    output fabric_llpp1_araddr_s_o20;
-    output fabric_llpp1_araddr_s_o21;
-    output fabric_llpp1_araddr_s_o22;
-    output fabric_llpp1_araddr_s_o23;
-    output fabric_llpp1_araddr_s_o24;
-    output fabric_llpp1_araddr_s_o25;
-    output fabric_llpp1_araddr_s_o26;
-    output fabric_llpp1_araddr_s_o27;
-    output fabric_llpp1_araddr_s_o28;
-    output fabric_llpp1_araddr_s_o29;
-    output fabric_llpp1_araddr_s_o3;
-    output fabric_llpp1_araddr_s_o30;
-    output fabric_llpp1_araddr_s_o31;
-    output fabric_llpp1_araddr_s_o32;
-    output fabric_llpp1_araddr_s_o4;
-    output fabric_llpp1_araddr_s_o5;
-    output fabric_llpp1_araddr_s_o6;
-    output fabric_llpp1_araddr_s_o7;
-    output fabric_llpp1_araddr_s_o8;
-    output fabric_llpp1_araddr_s_o9;
-    output fabric_llpp1_arburst_s_o1;
-    output fabric_llpp1_arburst_s_o2;
-    output fabric_llpp1_arcache_s_o1;
-    output fabric_llpp1_arcache_s_o2;
-    output fabric_llpp1_arcache_s_o3;
-    output fabric_llpp1_arcache_s_o4;
-    output fabric_llpp1_arid_s_o1;
-    output fabric_llpp1_arid_s_o10;
-    output fabric_llpp1_arid_s_o11;
-    output fabric_llpp1_arid_s_o12;
-    output fabric_llpp1_arid_s_o2;
-    output fabric_llpp1_arid_s_o3;
-    output fabric_llpp1_arid_s_o4;
-    output fabric_llpp1_arid_s_o5;
-    output fabric_llpp1_arid_s_o6;
-    output fabric_llpp1_arid_s_o7;
-    output fabric_llpp1_arid_s_o8;
-    output fabric_llpp1_arid_s_o9;
-    output fabric_llpp1_arlen_s_o1;
-    output fabric_llpp1_arlen_s_o2;
-    output fabric_llpp1_arlen_s_o3;
-    output fabric_llpp1_arlen_s_o4;
-    output fabric_llpp1_arlen_s_o5;
-    output fabric_llpp1_arlen_s_o6;
-    output fabric_llpp1_arlen_s_o7;
-    output fabric_llpp1_arlen_s_o8;
-    output fabric_llpp1_arlock_s_o;
-    output fabric_llpp1_arprot_s_o1;
-    output fabric_llpp1_arprot_s_o2;
-    output fabric_llpp1_arprot_s_o3;
-    output fabric_llpp1_arqos_s_o1;
-    output fabric_llpp1_arqos_s_o2;
-    output fabric_llpp1_arqos_s_o3;
-    output fabric_llpp1_arqos_s_o4;
-    input fabric_llpp1_arready_s_i;
-    output fabric_llpp1_arsize_s_o1;
-    output fabric_llpp1_arsize_s_o2;
-    output fabric_llpp1_arsize_s_o3;
-    output fabric_llpp1_arvalid_s_o;
-    output fabric_llpp1_awaddr_s_o1;
-    output fabric_llpp1_awaddr_s_o10;
-    output fabric_llpp1_awaddr_s_o11;
-    output fabric_llpp1_awaddr_s_o12;
-    output fabric_llpp1_awaddr_s_o13;
-    output fabric_llpp1_awaddr_s_o14;
-    output fabric_llpp1_awaddr_s_o15;
-    output fabric_llpp1_awaddr_s_o16;
-    output fabric_llpp1_awaddr_s_o17;
-    output fabric_llpp1_awaddr_s_o18;
-    output fabric_llpp1_awaddr_s_o19;
-    output fabric_llpp1_awaddr_s_o2;
-    output fabric_llpp1_awaddr_s_o20;
-    output fabric_llpp1_awaddr_s_o21;
-    output fabric_llpp1_awaddr_s_o22;
-    output fabric_llpp1_awaddr_s_o23;
-    output fabric_llpp1_awaddr_s_o24;
-    output fabric_llpp1_awaddr_s_o25;
-    output fabric_llpp1_awaddr_s_o26;
-    output fabric_llpp1_awaddr_s_o27;
-    output fabric_llpp1_awaddr_s_o28;
-    output fabric_llpp1_awaddr_s_o29;
-    output fabric_llpp1_awaddr_s_o3;
-    output fabric_llpp1_awaddr_s_o30;
-    output fabric_llpp1_awaddr_s_o31;
-    output fabric_llpp1_awaddr_s_o32;
-    output fabric_llpp1_awaddr_s_o4;
-    output fabric_llpp1_awaddr_s_o5;
-    output fabric_llpp1_awaddr_s_o6;
-    output fabric_llpp1_awaddr_s_o7;
-    output fabric_llpp1_awaddr_s_o8;
-    output fabric_llpp1_awaddr_s_o9;
-    output fabric_llpp1_awburst_s_o1;
-    output fabric_llpp1_awburst_s_o2;
-    output fabric_llpp1_awcache_s_o1;
-    output fabric_llpp1_awcache_s_o2;
-    output fabric_llpp1_awcache_s_o3;
-    output fabric_llpp1_awcache_s_o4;
-    output fabric_llpp1_awid_s_o1;
-    output fabric_llpp1_awid_s_o10;
-    output fabric_llpp1_awid_s_o11;
-    output fabric_llpp1_awid_s_o12;
-    output fabric_llpp1_awid_s_o2;
-    output fabric_llpp1_awid_s_o3;
-    output fabric_llpp1_awid_s_o4;
-    output fabric_llpp1_awid_s_o5;
-    output fabric_llpp1_awid_s_o6;
-    output fabric_llpp1_awid_s_o7;
-    output fabric_llpp1_awid_s_o8;
-    output fabric_llpp1_awid_s_o9;
-    output fabric_llpp1_awlen_s_o1;
-    output fabric_llpp1_awlen_s_o2;
-    output fabric_llpp1_awlen_s_o3;
-    output fabric_llpp1_awlen_s_o4;
-    output fabric_llpp1_awlen_s_o5;
-    output fabric_llpp1_awlen_s_o6;
-    output fabric_llpp1_awlen_s_o7;
-    output fabric_llpp1_awlen_s_o8;
-    output fabric_llpp1_awlock_s_o;
-    output fabric_llpp1_awprot_s_o1;
-    output fabric_llpp1_awprot_s_o2;
-    output fabric_llpp1_awprot_s_o3;
-    output fabric_llpp1_awqos_s_o1;
-    output fabric_llpp1_awqos_s_o2;
-    output fabric_llpp1_awqos_s_o3;
-    output fabric_llpp1_awqos_s_o4;
-    input fabric_llpp1_awready_s_i;
-    output fabric_llpp1_awsize_s_o1;
-    output fabric_llpp1_awsize_s_o2;
-    output fabric_llpp1_awsize_s_o3;
-    output fabric_llpp1_awvalid_s_o;
-    input fabric_llpp1_bid_s_i1;
-    input fabric_llpp1_bid_s_i10;
-    input fabric_llpp1_bid_s_i11;
-    input fabric_llpp1_bid_s_i12;
-    input fabric_llpp1_bid_s_i2;
-    input fabric_llpp1_bid_s_i3;
-    input fabric_llpp1_bid_s_i4;
-    input fabric_llpp1_bid_s_i5;
-    input fabric_llpp1_bid_s_i6;
-    input fabric_llpp1_bid_s_i7;
-    input fabric_llpp1_bid_s_i8;
-    input fabric_llpp1_bid_s_i9;
-    output fabric_llpp1_bready_s_o;
-    input fabric_llpp1_bresp_s_i1;
-    input fabric_llpp1_bresp_s_i2;
-    input fabric_llpp1_bvalid_s_i;
-    input fabric_llpp1_rdata_s_i1;
-    input fabric_llpp1_rdata_s_i10;
-    input fabric_llpp1_rdata_s_i11;
-    input fabric_llpp1_rdata_s_i12;
-    input fabric_llpp1_rdata_s_i13;
-    input fabric_llpp1_rdata_s_i14;
-    input fabric_llpp1_rdata_s_i15;
-    input fabric_llpp1_rdata_s_i16;
-    input fabric_llpp1_rdata_s_i17;
-    input fabric_llpp1_rdata_s_i18;
-    input fabric_llpp1_rdata_s_i19;
-    input fabric_llpp1_rdata_s_i2;
-    input fabric_llpp1_rdata_s_i20;
-    input fabric_llpp1_rdata_s_i21;
-    input fabric_llpp1_rdata_s_i22;
-    input fabric_llpp1_rdata_s_i23;
-    input fabric_llpp1_rdata_s_i24;
-    input fabric_llpp1_rdata_s_i25;
-    input fabric_llpp1_rdata_s_i26;
-    input fabric_llpp1_rdata_s_i27;
-    input fabric_llpp1_rdata_s_i28;
-    input fabric_llpp1_rdata_s_i29;
-    input fabric_llpp1_rdata_s_i3;
-    input fabric_llpp1_rdata_s_i30;
-    input fabric_llpp1_rdata_s_i31;
-    input fabric_llpp1_rdata_s_i32;
-    input fabric_llpp1_rdata_s_i4;
-    input fabric_llpp1_rdata_s_i5;
-    input fabric_llpp1_rdata_s_i6;
-    input fabric_llpp1_rdata_s_i7;
-    input fabric_llpp1_rdata_s_i8;
-    input fabric_llpp1_rdata_s_i9;
-    input fabric_llpp1_rid_s_i1;
-    input fabric_llpp1_rid_s_i10;
-    input fabric_llpp1_rid_s_i11;
-    input fabric_llpp1_rid_s_i12;
-    input fabric_llpp1_rid_s_i2;
-    input fabric_llpp1_rid_s_i3;
-    input fabric_llpp1_rid_s_i4;
-    input fabric_llpp1_rid_s_i5;
-    input fabric_llpp1_rid_s_i6;
-    input fabric_llpp1_rid_s_i7;
-    input fabric_llpp1_rid_s_i8;
-    input fabric_llpp1_rid_s_i9;
-    input fabric_llpp1_rlast_s_i;
-    output fabric_llpp1_rready_s_o;
-    input fabric_llpp1_rresp_s_i1;
-    input fabric_llpp1_rresp_s_i2;
-    input fabric_llpp1_rvalid_s_i;
-    output fabric_llpp1_wdata_s_o1;
-    output fabric_llpp1_wdata_s_o10;
-    output fabric_llpp1_wdata_s_o11;
-    output fabric_llpp1_wdata_s_o12;
-    output fabric_llpp1_wdata_s_o13;
-    output fabric_llpp1_wdata_s_o14;
-    output fabric_llpp1_wdata_s_o15;
-    output fabric_llpp1_wdata_s_o16;
-    output fabric_llpp1_wdata_s_o17;
-    output fabric_llpp1_wdata_s_o18;
-    output fabric_llpp1_wdata_s_o19;
-    output fabric_llpp1_wdata_s_o2;
-    output fabric_llpp1_wdata_s_o20;
-    output fabric_llpp1_wdata_s_o21;
-    output fabric_llpp1_wdata_s_o22;
-    output fabric_llpp1_wdata_s_o23;
-    output fabric_llpp1_wdata_s_o24;
-    output fabric_llpp1_wdata_s_o25;
-    output fabric_llpp1_wdata_s_o26;
-    output fabric_llpp1_wdata_s_o27;
-    output fabric_llpp1_wdata_s_o28;
-    output fabric_llpp1_wdata_s_o29;
-    output fabric_llpp1_wdata_s_o3;
-    output fabric_llpp1_wdata_s_o30;
-    output fabric_llpp1_wdata_s_o31;
-    output fabric_llpp1_wdata_s_o32;
-    output fabric_llpp1_wdata_s_o4;
-    output fabric_llpp1_wdata_s_o5;
-    output fabric_llpp1_wdata_s_o6;
-    output fabric_llpp1_wdata_s_o7;
-    output fabric_llpp1_wdata_s_o8;
-    output fabric_llpp1_wdata_s_o9;
-    output fabric_llpp1_wlast_s_o;
-    input fabric_llpp1_wready_s_i;
-    output fabric_llpp1_wstrb_s_o1;
-    output fabric_llpp1_wstrb_s_o2;
-    output fabric_llpp1_wstrb_s_o3;
-    output fabric_llpp1_wstrb_s_o4;
-    output fabric_llpp1_wvalid_s_o;
-    output fabric_llpp2_araddr_s_o1;
-    output fabric_llpp2_araddr_s_o10;
-    output fabric_llpp2_araddr_s_o11;
-    output fabric_llpp2_araddr_s_o12;
-    output fabric_llpp2_araddr_s_o13;
-    output fabric_llpp2_araddr_s_o14;
-    output fabric_llpp2_araddr_s_o15;
-    output fabric_llpp2_araddr_s_o16;
-    output fabric_llpp2_araddr_s_o17;
-    output fabric_llpp2_araddr_s_o18;
-    output fabric_llpp2_araddr_s_o19;
-    output fabric_llpp2_araddr_s_o2;
-    output fabric_llpp2_araddr_s_o20;
-    output fabric_llpp2_araddr_s_o21;
-    output fabric_llpp2_araddr_s_o22;
-    output fabric_llpp2_araddr_s_o23;
-    output fabric_llpp2_araddr_s_o24;
-    output fabric_llpp2_araddr_s_o25;
-    output fabric_llpp2_araddr_s_o26;
-    output fabric_llpp2_araddr_s_o27;
-    output fabric_llpp2_araddr_s_o28;
-    output fabric_llpp2_araddr_s_o29;
-    output fabric_llpp2_araddr_s_o3;
-    output fabric_llpp2_araddr_s_o30;
-    output fabric_llpp2_araddr_s_o31;
-    output fabric_llpp2_araddr_s_o32;
-    output fabric_llpp2_araddr_s_o4;
-    output fabric_llpp2_araddr_s_o5;
-    output fabric_llpp2_araddr_s_o6;
-    output fabric_llpp2_araddr_s_o7;
-    output fabric_llpp2_araddr_s_o8;
-    output fabric_llpp2_araddr_s_o9;
-    output fabric_llpp2_arburst_s_o1;
-    output fabric_llpp2_arburst_s_o2;
-    output fabric_llpp2_arcache_s_o1;
-    output fabric_llpp2_arcache_s_o2;
-    output fabric_llpp2_arcache_s_o3;
-    output fabric_llpp2_arcache_s_o4;
-    output fabric_llpp2_arid_s_o1;
-    output fabric_llpp2_arid_s_o10;
-    output fabric_llpp2_arid_s_o11;
-    output fabric_llpp2_arid_s_o12;
-    output fabric_llpp2_arid_s_o2;
-    output fabric_llpp2_arid_s_o3;
-    output fabric_llpp2_arid_s_o4;
-    output fabric_llpp2_arid_s_o5;
-    output fabric_llpp2_arid_s_o6;
-    output fabric_llpp2_arid_s_o7;
-    output fabric_llpp2_arid_s_o8;
-    output fabric_llpp2_arid_s_o9;
-    output fabric_llpp2_arlen_s_o1;
-    output fabric_llpp2_arlen_s_o2;
-    output fabric_llpp2_arlen_s_o3;
-    output fabric_llpp2_arlen_s_o4;
-    output fabric_llpp2_arlen_s_o5;
-    output fabric_llpp2_arlen_s_o6;
-    output fabric_llpp2_arlen_s_o7;
-    output fabric_llpp2_arlen_s_o8;
-    output fabric_llpp2_arlock_s_o;
-    output fabric_llpp2_arprot_s_o1;
-    output fabric_llpp2_arprot_s_o2;
-    output fabric_llpp2_arprot_s_o3;
-    output fabric_llpp2_arqos_s_o1;
-    output fabric_llpp2_arqos_s_o2;
-    output fabric_llpp2_arqos_s_o3;
-    output fabric_llpp2_arqos_s_o4;
-    input fabric_llpp2_arready_s_i;
-    output fabric_llpp2_arsize_s_o1;
-    output fabric_llpp2_arsize_s_o2;
-    output fabric_llpp2_arsize_s_o3;
-    output fabric_llpp2_arvalid_s_o;
-    output fabric_llpp2_awaddr_s_o1;
-    output fabric_llpp2_awaddr_s_o10;
-    output fabric_llpp2_awaddr_s_o11;
-    output fabric_llpp2_awaddr_s_o12;
-    output fabric_llpp2_awaddr_s_o13;
-    output fabric_llpp2_awaddr_s_o14;
-    output fabric_llpp2_awaddr_s_o15;
-    output fabric_llpp2_awaddr_s_o16;
-    output fabric_llpp2_awaddr_s_o17;
-    output fabric_llpp2_awaddr_s_o18;
-    output fabric_llpp2_awaddr_s_o19;
-    output fabric_llpp2_awaddr_s_o2;
-    output fabric_llpp2_awaddr_s_o20;
-    output fabric_llpp2_awaddr_s_o21;
-    output fabric_llpp2_awaddr_s_o22;
-    output fabric_llpp2_awaddr_s_o23;
-    output fabric_llpp2_awaddr_s_o24;
-    output fabric_llpp2_awaddr_s_o25;
-    output fabric_llpp2_awaddr_s_o26;
-    output fabric_llpp2_awaddr_s_o27;
-    output fabric_llpp2_awaddr_s_o28;
-    output fabric_llpp2_awaddr_s_o29;
-    output fabric_llpp2_awaddr_s_o3;
-    output fabric_llpp2_awaddr_s_o30;
-    output fabric_llpp2_awaddr_s_o31;
-    output fabric_llpp2_awaddr_s_o32;
-    output fabric_llpp2_awaddr_s_o4;
-    output fabric_llpp2_awaddr_s_o5;
-    output fabric_llpp2_awaddr_s_o6;
-    output fabric_llpp2_awaddr_s_o7;
-    output fabric_llpp2_awaddr_s_o8;
-    output fabric_llpp2_awaddr_s_o9;
-    output fabric_llpp2_awburst_s_o1;
-    output fabric_llpp2_awburst_s_o2;
-    output fabric_llpp2_awcache_s_o1;
-    output fabric_llpp2_awcache_s_o2;
-    output fabric_llpp2_awcache_s_o3;
-    output fabric_llpp2_awcache_s_o4;
-    output fabric_llpp2_awid_s_o1;
-    output fabric_llpp2_awid_s_o10;
-    output fabric_llpp2_awid_s_o11;
-    output fabric_llpp2_awid_s_o12;
-    output fabric_llpp2_awid_s_o2;
-    output fabric_llpp2_awid_s_o3;
-    output fabric_llpp2_awid_s_o4;
-    output fabric_llpp2_awid_s_o5;
-    output fabric_llpp2_awid_s_o6;
-    output fabric_llpp2_awid_s_o7;
-    output fabric_llpp2_awid_s_o8;
-    output fabric_llpp2_awid_s_o9;
-    output fabric_llpp2_awlen_s_o1;
-    output fabric_llpp2_awlen_s_o2;
-    output fabric_llpp2_awlen_s_o3;
-    output fabric_llpp2_awlen_s_o4;
-    output fabric_llpp2_awlen_s_o5;
-    output fabric_llpp2_awlen_s_o6;
-    output fabric_llpp2_awlen_s_o7;
-    output fabric_llpp2_awlen_s_o8;
-    output fabric_llpp2_awlock_s_o;
-    output fabric_llpp2_awprot_s_o1;
-    output fabric_llpp2_awprot_s_o2;
-    output fabric_llpp2_awprot_s_o3;
-    output fabric_llpp2_awqos_s_o1;
-    output fabric_llpp2_awqos_s_o2;
-    output fabric_llpp2_awqos_s_o3;
-    output fabric_llpp2_awqos_s_o4;
-    input fabric_llpp2_awready_s_i;
-    output fabric_llpp2_awsize_s_o1;
-    output fabric_llpp2_awsize_s_o2;
-    output fabric_llpp2_awsize_s_o3;
-    output fabric_llpp2_awvalid_s_o;
-    input fabric_llpp2_bid_s_i1;
-    input fabric_llpp2_bid_s_i10;
-    input fabric_llpp2_bid_s_i11;
-    input fabric_llpp2_bid_s_i12;
-    input fabric_llpp2_bid_s_i2;
-    input fabric_llpp2_bid_s_i3;
-    input fabric_llpp2_bid_s_i4;
-    input fabric_llpp2_bid_s_i5;
-    input fabric_llpp2_bid_s_i6;
-    input fabric_llpp2_bid_s_i7;
-    input fabric_llpp2_bid_s_i8;
-    input fabric_llpp2_bid_s_i9;
-    output fabric_llpp2_bready_s_o;
-    input fabric_llpp2_bresp_s_i1;
-    input fabric_llpp2_bresp_s_i2;
-    input fabric_llpp2_bvalid_s_i;
-    input fabric_llpp2_rdata_s_i1;
-    input fabric_llpp2_rdata_s_i10;
-    input fabric_llpp2_rdata_s_i11;
-    input fabric_llpp2_rdata_s_i12;
-    input fabric_llpp2_rdata_s_i13;
-    input fabric_llpp2_rdata_s_i14;
-    input fabric_llpp2_rdata_s_i15;
-    input fabric_llpp2_rdata_s_i16;
-    input fabric_llpp2_rdata_s_i17;
-    input fabric_llpp2_rdata_s_i18;
-    input fabric_llpp2_rdata_s_i19;
-    input fabric_llpp2_rdata_s_i2;
-    input fabric_llpp2_rdata_s_i20;
-    input fabric_llpp2_rdata_s_i21;
-    input fabric_llpp2_rdata_s_i22;
-    input fabric_llpp2_rdata_s_i23;
-    input fabric_llpp2_rdata_s_i24;
-    input fabric_llpp2_rdata_s_i25;
-    input fabric_llpp2_rdata_s_i26;
-    input fabric_llpp2_rdata_s_i27;
-    input fabric_llpp2_rdata_s_i28;
-    input fabric_llpp2_rdata_s_i29;
-    input fabric_llpp2_rdata_s_i3;
-    input fabric_llpp2_rdata_s_i30;
-    input fabric_llpp2_rdata_s_i31;
-    input fabric_llpp2_rdata_s_i32;
-    input fabric_llpp2_rdata_s_i4;
-    input fabric_llpp2_rdata_s_i5;
-    input fabric_llpp2_rdata_s_i6;
-    input fabric_llpp2_rdata_s_i7;
-    input fabric_llpp2_rdata_s_i8;
-    input fabric_llpp2_rdata_s_i9;
-    input fabric_llpp2_rid_s_i1;
-    input fabric_llpp2_rid_s_i10;
-    input fabric_llpp2_rid_s_i11;
-    input fabric_llpp2_rid_s_i12;
-    input fabric_llpp2_rid_s_i2;
-    input fabric_llpp2_rid_s_i3;
-    input fabric_llpp2_rid_s_i4;
-    input fabric_llpp2_rid_s_i5;
-    input fabric_llpp2_rid_s_i6;
-    input fabric_llpp2_rid_s_i7;
-    input fabric_llpp2_rid_s_i8;
-    input fabric_llpp2_rid_s_i9;
-    input fabric_llpp2_rlast_s_i;
-    output fabric_llpp2_rready_s_o;
-    input fabric_llpp2_rresp_s_i1;
-    input fabric_llpp2_rresp_s_i2;
-    input fabric_llpp2_rvalid_s_i;
-    output fabric_llpp2_wdata_s_o1;
-    output fabric_llpp2_wdata_s_o10;
-    output fabric_llpp2_wdata_s_o11;
-    output fabric_llpp2_wdata_s_o12;
-    output fabric_llpp2_wdata_s_o13;
-    output fabric_llpp2_wdata_s_o14;
-    output fabric_llpp2_wdata_s_o15;
-    output fabric_llpp2_wdata_s_o16;
-    output fabric_llpp2_wdata_s_o17;
-    output fabric_llpp2_wdata_s_o18;
-    output fabric_llpp2_wdata_s_o19;
-    output fabric_llpp2_wdata_s_o2;
-    output fabric_llpp2_wdata_s_o20;
-    output fabric_llpp2_wdata_s_o21;
-    output fabric_llpp2_wdata_s_o22;
-    output fabric_llpp2_wdata_s_o23;
-    output fabric_llpp2_wdata_s_o24;
-    output fabric_llpp2_wdata_s_o25;
-    output fabric_llpp2_wdata_s_o26;
-    output fabric_llpp2_wdata_s_o27;
-    output fabric_llpp2_wdata_s_o28;
-    output fabric_llpp2_wdata_s_o29;
-    output fabric_llpp2_wdata_s_o3;
-    output fabric_llpp2_wdata_s_o30;
-    output fabric_llpp2_wdata_s_o31;
-    output fabric_llpp2_wdata_s_o32;
-    output fabric_llpp2_wdata_s_o4;
-    output fabric_llpp2_wdata_s_o5;
-    output fabric_llpp2_wdata_s_o6;
-    output fabric_llpp2_wdata_s_o7;
-    output fabric_llpp2_wdata_s_o8;
-    output fabric_llpp2_wdata_s_o9;
-    output fabric_llpp2_wlast_s_o;
-    input fabric_llpp2_wready_s_i;
-    output fabric_llpp2_wstrb_s_o1;
-    output fabric_llpp2_wstrb_s_o2;
-    output fabric_llpp2_wstrb_s_o3;
-    output fabric_llpp2_wstrb_s_o4;
-    output fabric_llpp2_wvalid_s_o;
-    output fabric_llpp3_araddr_s_o1;
-    output fabric_llpp3_araddr_s_o10;
-    output fabric_llpp3_araddr_s_o11;
-    output fabric_llpp3_araddr_s_o12;
-    output fabric_llpp3_araddr_s_o13;
-    output fabric_llpp3_araddr_s_o14;
-    output fabric_llpp3_araddr_s_o15;
-    output fabric_llpp3_araddr_s_o16;
-    output fabric_llpp3_araddr_s_o17;
-    output fabric_llpp3_araddr_s_o18;
-    output fabric_llpp3_araddr_s_o19;
-    output fabric_llpp3_araddr_s_o2;
-    output fabric_llpp3_araddr_s_o20;
-    output fabric_llpp3_araddr_s_o21;
-    output fabric_llpp3_araddr_s_o22;
-    output fabric_llpp3_araddr_s_o23;
-    output fabric_llpp3_araddr_s_o24;
-    output fabric_llpp3_araddr_s_o25;
-    output fabric_llpp3_araddr_s_o26;
-    output fabric_llpp3_araddr_s_o27;
-    output fabric_llpp3_araddr_s_o28;
-    output fabric_llpp3_araddr_s_o29;
-    output fabric_llpp3_araddr_s_o3;
-    output fabric_llpp3_araddr_s_o30;
-    output fabric_llpp3_araddr_s_o31;
-    output fabric_llpp3_araddr_s_o32;
-    output fabric_llpp3_araddr_s_o4;
-    output fabric_llpp3_araddr_s_o5;
-    output fabric_llpp3_araddr_s_o6;
-    output fabric_llpp3_araddr_s_o7;
-    output fabric_llpp3_araddr_s_o8;
-    output fabric_llpp3_araddr_s_o9;
-    output fabric_llpp3_arburst_s_o1;
-    output fabric_llpp3_arburst_s_o2;
-    output fabric_llpp3_arcache_s_o1;
-    output fabric_llpp3_arcache_s_o2;
-    output fabric_llpp3_arcache_s_o3;
-    output fabric_llpp3_arcache_s_o4;
-    output fabric_llpp3_arid_s_o1;
-    output fabric_llpp3_arid_s_o10;
-    output fabric_llpp3_arid_s_o11;
-    output fabric_llpp3_arid_s_o12;
-    output fabric_llpp3_arid_s_o2;
-    output fabric_llpp3_arid_s_o3;
-    output fabric_llpp3_arid_s_o4;
-    output fabric_llpp3_arid_s_o5;
-    output fabric_llpp3_arid_s_o6;
-    output fabric_llpp3_arid_s_o7;
-    output fabric_llpp3_arid_s_o8;
-    output fabric_llpp3_arid_s_o9;
-    output fabric_llpp3_arlen_s_o1;
-    output fabric_llpp3_arlen_s_o2;
-    output fabric_llpp3_arlen_s_o3;
-    output fabric_llpp3_arlen_s_o4;
-    output fabric_llpp3_arlen_s_o5;
-    output fabric_llpp3_arlen_s_o6;
-    output fabric_llpp3_arlen_s_o7;
-    output fabric_llpp3_arlen_s_o8;
-    output fabric_llpp3_arlock_s_o;
-    output fabric_llpp3_arprot_s_o1;
-    output fabric_llpp3_arprot_s_o2;
-    output fabric_llpp3_arprot_s_o3;
-    output fabric_llpp3_arqos_s_o1;
-    output fabric_llpp3_arqos_s_o2;
-    output fabric_llpp3_arqos_s_o3;
-    output fabric_llpp3_arqos_s_o4;
-    input fabric_llpp3_arready_s_i;
-    output fabric_llpp3_arsize_s_o1;
-    output fabric_llpp3_arsize_s_o2;
-    output fabric_llpp3_arsize_s_o3;
-    output fabric_llpp3_arvalid_s_o;
-    output fabric_llpp3_awaddr_s_o1;
-    output fabric_llpp3_awaddr_s_o10;
-    output fabric_llpp3_awaddr_s_o11;
-    output fabric_llpp3_awaddr_s_o12;
-    output fabric_llpp3_awaddr_s_o13;
-    output fabric_llpp3_awaddr_s_o14;
-    output fabric_llpp3_awaddr_s_o15;
-    output fabric_llpp3_awaddr_s_o16;
-    output fabric_llpp3_awaddr_s_o17;
-    output fabric_llpp3_awaddr_s_o18;
-    output fabric_llpp3_awaddr_s_o19;
-    output fabric_llpp3_awaddr_s_o2;
-    output fabric_llpp3_awaddr_s_o20;
-    output fabric_llpp3_awaddr_s_o21;
-    output fabric_llpp3_awaddr_s_o22;
-    output fabric_llpp3_awaddr_s_o23;
-    output fabric_llpp3_awaddr_s_o24;
-    output fabric_llpp3_awaddr_s_o25;
-    output fabric_llpp3_awaddr_s_o26;
-    output fabric_llpp3_awaddr_s_o27;
-    output fabric_llpp3_awaddr_s_o28;
-    output fabric_llpp3_awaddr_s_o29;
-    output fabric_llpp3_awaddr_s_o3;
-    output fabric_llpp3_awaddr_s_o30;
-    output fabric_llpp3_awaddr_s_o31;
-    output fabric_llpp3_awaddr_s_o32;
-    output fabric_llpp3_awaddr_s_o4;
-    output fabric_llpp3_awaddr_s_o5;
-    output fabric_llpp3_awaddr_s_o6;
-    output fabric_llpp3_awaddr_s_o7;
-    output fabric_llpp3_awaddr_s_o8;
-    output fabric_llpp3_awaddr_s_o9;
-    output fabric_llpp3_awburst_s_o1;
-    output fabric_llpp3_awburst_s_o2;
-    output fabric_llpp3_awcache_s_o1;
-    output fabric_llpp3_awcache_s_o2;
-    output fabric_llpp3_awcache_s_o3;
-    output fabric_llpp3_awcache_s_o4;
-    output fabric_llpp3_awid_s_o1;
-    output fabric_llpp3_awid_s_o10;
-    output fabric_llpp3_awid_s_o11;
-    output fabric_llpp3_awid_s_o12;
-    output fabric_llpp3_awid_s_o2;
-    output fabric_llpp3_awid_s_o3;
-    output fabric_llpp3_awid_s_o4;
-    output fabric_llpp3_awid_s_o5;
-    output fabric_llpp3_awid_s_o6;
-    output fabric_llpp3_awid_s_o7;
-    output fabric_llpp3_awid_s_o8;
-    output fabric_llpp3_awid_s_o9;
-    output fabric_llpp3_awlen_s_o1;
-    output fabric_llpp3_awlen_s_o2;
-    output fabric_llpp3_awlen_s_o3;
-    output fabric_llpp3_awlen_s_o4;
-    output fabric_llpp3_awlen_s_o5;
-    output fabric_llpp3_awlen_s_o6;
-    output fabric_llpp3_awlen_s_o7;
-    output fabric_llpp3_awlen_s_o8;
-    output fabric_llpp3_awlock_s_o;
-    output fabric_llpp3_awprot_s_o1;
-    output fabric_llpp3_awprot_s_o2;
-    output fabric_llpp3_awprot_s_o3;
-    output fabric_llpp3_awqos_s_o1;
-    output fabric_llpp3_awqos_s_o2;
-    output fabric_llpp3_awqos_s_o3;
-    output fabric_llpp3_awqos_s_o4;
-    input fabric_llpp3_awready_s_i;
-    output fabric_llpp3_awsize_s_o1;
-    output fabric_llpp3_awsize_s_o2;
-    output fabric_llpp3_awsize_s_o3;
-    output fabric_llpp3_awvalid_s_o;
-    input fabric_llpp3_bid_s_i1;
-    input fabric_llpp3_bid_s_i10;
-    input fabric_llpp3_bid_s_i11;
-    input fabric_llpp3_bid_s_i12;
-    input fabric_llpp3_bid_s_i2;
-    input fabric_llpp3_bid_s_i3;
-    input fabric_llpp3_bid_s_i4;
-    input fabric_llpp3_bid_s_i5;
-    input fabric_llpp3_bid_s_i6;
-    input fabric_llpp3_bid_s_i7;
-    input fabric_llpp3_bid_s_i8;
-    input fabric_llpp3_bid_s_i9;
-    output fabric_llpp3_bready_s_o;
-    input fabric_llpp3_bresp_s_i1;
-    input fabric_llpp3_bresp_s_i2;
-    input fabric_llpp3_bvalid_s_i;
-    input fabric_llpp3_rdata_s_i1;
-    input fabric_llpp3_rdata_s_i10;
-    input fabric_llpp3_rdata_s_i11;
-    input fabric_llpp3_rdata_s_i12;
-    input fabric_llpp3_rdata_s_i13;
-    input fabric_llpp3_rdata_s_i14;
-    input fabric_llpp3_rdata_s_i15;
-    input fabric_llpp3_rdata_s_i16;
-    input fabric_llpp3_rdata_s_i17;
-    input fabric_llpp3_rdata_s_i18;
-    input fabric_llpp3_rdata_s_i19;
-    input fabric_llpp3_rdata_s_i2;
-    input fabric_llpp3_rdata_s_i20;
-    input fabric_llpp3_rdata_s_i21;
-    input fabric_llpp3_rdata_s_i22;
-    input fabric_llpp3_rdata_s_i23;
-    input fabric_llpp3_rdata_s_i24;
-    input fabric_llpp3_rdata_s_i25;
-    input fabric_llpp3_rdata_s_i26;
-    input fabric_llpp3_rdata_s_i27;
-    input fabric_llpp3_rdata_s_i28;
-    input fabric_llpp3_rdata_s_i29;
-    input fabric_llpp3_rdata_s_i3;
-    input fabric_llpp3_rdata_s_i30;
-    input fabric_llpp3_rdata_s_i31;
-    input fabric_llpp3_rdata_s_i32;
-    input fabric_llpp3_rdata_s_i4;
-    input fabric_llpp3_rdata_s_i5;
-    input fabric_llpp3_rdata_s_i6;
-    input fabric_llpp3_rdata_s_i7;
-    input fabric_llpp3_rdata_s_i8;
-    input fabric_llpp3_rdata_s_i9;
-    input fabric_llpp3_rid_s_i1;
-    input fabric_llpp3_rid_s_i10;
-    input fabric_llpp3_rid_s_i11;
-    input fabric_llpp3_rid_s_i12;
-    input fabric_llpp3_rid_s_i2;
-    input fabric_llpp3_rid_s_i3;
-    input fabric_llpp3_rid_s_i4;
-    input fabric_llpp3_rid_s_i5;
-    input fabric_llpp3_rid_s_i6;
-    input fabric_llpp3_rid_s_i7;
-    input fabric_llpp3_rid_s_i8;
-    input fabric_llpp3_rid_s_i9;
-    input fabric_llpp3_rlast_s_i;
-    output fabric_llpp3_rready_s_o;
-    input fabric_llpp3_rresp_s_i1;
-    input fabric_llpp3_rresp_s_i2;
-    input fabric_llpp3_rvalid_s_i;
-    output fabric_llpp3_wdata_s_o1;
-    output fabric_llpp3_wdata_s_o10;
-    output fabric_llpp3_wdata_s_o11;
-    output fabric_llpp3_wdata_s_o12;
-    output fabric_llpp3_wdata_s_o13;
-    output fabric_llpp3_wdata_s_o14;
-    output fabric_llpp3_wdata_s_o15;
-    output fabric_llpp3_wdata_s_o16;
-    output fabric_llpp3_wdata_s_o17;
-    output fabric_llpp3_wdata_s_o18;
-    output fabric_llpp3_wdata_s_o19;
-    output fabric_llpp3_wdata_s_o2;
-    output fabric_llpp3_wdata_s_o20;
-    output fabric_llpp3_wdata_s_o21;
-    output fabric_llpp3_wdata_s_o22;
-    output fabric_llpp3_wdata_s_o23;
-    output fabric_llpp3_wdata_s_o24;
-    output fabric_llpp3_wdata_s_o25;
-    output fabric_llpp3_wdata_s_o26;
-    output fabric_llpp3_wdata_s_o27;
-    output fabric_llpp3_wdata_s_o28;
-    output fabric_llpp3_wdata_s_o29;
-    output fabric_llpp3_wdata_s_o3;
-    output fabric_llpp3_wdata_s_o30;
-    output fabric_llpp3_wdata_s_o31;
-    output fabric_llpp3_wdata_s_o32;
-    output fabric_llpp3_wdata_s_o4;
-    output fabric_llpp3_wdata_s_o5;
-    output fabric_llpp3_wdata_s_o6;
-    output fabric_llpp3_wdata_s_o7;
-    output fabric_llpp3_wdata_s_o8;
-    output fabric_llpp3_wdata_s_o9;
-    output fabric_llpp3_wlast_s_o;
-    input fabric_llpp3_wready_s_i;
-    output fabric_llpp3_wstrb_s_o1;
-    output fabric_llpp3_wstrb_s_o2;
-    output fabric_llpp3_wstrb_s_o3;
-    output fabric_llpp3_wstrb_s_o4;
-    output fabric_llpp3_wvalid_s_o;
-    input fabric_lowskew_i10;
-    input fabric_lowskew_i11;
-    input fabric_lowskew_i12;
-    input fabric_lowskew_i13;
-    input fabric_lowskew_i14;
-    input fabric_lowskew_i15;
-    input fabric_lowskew_i16;
-    input fabric_lowskew_i17;
-    input fabric_lowskew_i18;
-    input fabric_lowskew_i19;
-    input fabric_lowskew_i3;
-    input fabric_lowskew_i4;
-    input fabric_lowskew_i5;
-    input fabric_lowskew_i6;
-    input fabric_lowskew_i7;
-    input fabric_lowskew_i8;
-    input fabric_lowskew_i9;
-    output fabric_lowskew_o1;
-    output fabric_lowskew_o2;
-    input fabric_qos_ppaddr_i1;
-    input fabric_qos_ppaddr_i10;
-    input fabric_qos_ppaddr_i11;
-    input fabric_qos_ppaddr_i12;
-    input fabric_qos_ppaddr_i13;
-    input fabric_qos_ppaddr_i14;
-    input fabric_qos_ppaddr_i15;
-    input fabric_qos_ppaddr_i16;
-    input fabric_qos_ppaddr_i17;
-    input fabric_qos_ppaddr_i18;
-    input fabric_qos_ppaddr_i19;
-    input fabric_qos_ppaddr_i2;
-    input fabric_qos_ppaddr_i20;
-    input fabric_qos_ppaddr_i21;
-    input fabric_qos_ppaddr_i22;
-    input fabric_qos_ppaddr_i23;
-    input fabric_qos_ppaddr_i24;
-    input fabric_qos_ppaddr_i25;
-    input fabric_qos_ppaddr_i26;
-    input fabric_qos_ppaddr_i27;
-    input fabric_qos_ppaddr_i28;
-    input fabric_qos_ppaddr_i29;
-    input fabric_qos_ppaddr_i3;
-    input fabric_qos_ppaddr_i30;
-    input fabric_qos_ppaddr_i31;
-    input fabric_qos_ppaddr_i32;
-    input fabric_qos_ppaddr_i4;
-    input fabric_qos_ppaddr_i5;
-    input fabric_qos_ppaddr_i6;
-    input fabric_qos_ppaddr_i7;
-    input fabric_qos_ppaddr_i8;
-    input fabric_qos_ppaddr_i9;
-    input fabric_qos_ppenable_i;
-    output fabric_qos_pprdata_o1;
-    output fabric_qos_pprdata_o10;
-    output fabric_qos_pprdata_o11;
-    output fabric_qos_pprdata_o12;
-    output fabric_qos_pprdata_o13;
-    output fabric_qos_pprdata_o14;
-    output fabric_qos_pprdata_o15;
-    output fabric_qos_pprdata_o16;
-    output fabric_qos_pprdata_o17;
-    output fabric_qos_pprdata_o18;
-    output fabric_qos_pprdata_o19;
-    output fabric_qos_pprdata_o2;
-    output fabric_qos_pprdata_o20;
-    output fabric_qos_pprdata_o21;
-    output fabric_qos_pprdata_o22;
-    output fabric_qos_pprdata_o23;
-    output fabric_qos_pprdata_o24;
-    output fabric_qos_pprdata_o25;
-    output fabric_qos_pprdata_o26;
-    output fabric_qos_pprdata_o27;
-    output fabric_qos_pprdata_o28;
-    output fabric_qos_pprdata_o29;
-    output fabric_qos_pprdata_o3;
-    output fabric_qos_pprdata_o30;
-    output fabric_qos_pprdata_o31;
-    output fabric_qos_pprdata_o32;
-    output fabric_qos_pprdata_o4;
-    output fabric_qos_pprdata_o5;
-    output fabric_qos_pprdata_o6;
-    output fabric_qos_pprdata_o7;
-    output fabric_qos_pprdata_o8;
-    output fabric_qos_pprdata_o9;
-    output fabric_qos_ppready_o;
-    output fabric_qos_ppslverr_o;
-    input fabric_qos_ppwdata_i1;
-    input fabric_qos_ppwdata_i10;
-    input fabric_qos_ppwdata_i11;
-    input fabric_qos_ppwdata_i12;
-    input fabric_qos_ppwdata_i13;
-    input fabric_qos_ppwdata_i14;
-    input fabric_qos_ppwdata_i15;
-    input fabric_qos_ppwdata_i16;
-    input fabric_qos_ppwdata_i17;
-    input fabric_qos_ppwdata_i18;
-    input fabric_qos_ppwdata_i19;
-    input fabric_qos_ppwdata_i2;
-    input fabric_qos_ppwdata_i20;
-    input fabric_qos_ppwdata_i21;
-    input fabric_qos_ppwdata_i22;
-    input fabric_qos_ppwdata_i23;
-    input fabric_qos_ppwdata_i24;
-    input fabric_qos_ppwdata_i25;
-    input fabric_qos_ppwdata_i26;
-    input fabric_qos_ppwdata_i27;
-    input fabric_qos_ppwdata_i28;
-    input fabric_qos_ppwdata_i29;
-    input fabric_qos_ppwdata_i3;
-    input fabric_qos_ppwdata_i30;
-    input fabric_qos_ppwdata_i31;
-    input fabric_qos_ppwdata_i32;
-    input fabric_qos_ppwdata_i4;
-    input fabric_qos_ppwdata_i5;
-    input fabric_qos_ppwdata_i6;
-    input fabric_qos_ppwdata_i7;
-    input fabric_qos_ppwdata_i8;
-    input fabric_qos_ppwdata_i9;
-    input fabric_qos_ppwrite_i;
-    input fabric_qos_presetn_i;
-    input fabric_qos_psel_i;
-    output fabric_soc_mon_sensor_alarm_o;
-    output fabric_spw_interrupts_o1;
-    output fabric_spw_interrupts_o2;
-    output fabric_spw_interrupts_o3;
-    output fabric_spw_interrupts_toggle_o1;
-    output fabric_spw_interrupts_toggle_o2;
-    output fabric_spw_interrupts_toggle_o3;
-    input fabric_sysc_hold_on_debug_i;
-    output fabric_tnd_fpga_apb_master_paddr_o1;
-    output fabric_tnd_fpga_apb_master_paddr_o10;
-    output fabric_tnd_fpga_apb_master_paddr_o11;
-    output fabric_tnd_fpga_apb_master_paddr_o12;
-    output fabric_tnd_fpga_apb_master_paddr_o13;
-    output fabric_tnd_fpga_apb_master_paddr_o14;
-    output fabric_tnd_fpga_apb_master_paddr_o15;
-    output fabric_tnd_fpga_apb_master_paddr_o16;
-    output fabric_tnd_fpga_apb_master_paddr_o17;
-    output fabric_tnd_fpga_apb_master_paddr_o18;
-    output fabric_tnd_fpga_apb_master_paddr_o19;
-    output fabric_tnd_fpga_apb_master_paddr_o2;
-    output fabric_tnd_fpga_apb_master_paddr_o20;
-    output fabric_tnd_fpga_apb_master_paddr_o21;
-    output fabric_tnd_fpga_apb_master_paddr_o22;
-    output fabric_tnd_fpga_apb_master_paddr_o23;
-    output fabric_tnd_fpga_apb_master_paddr_o24;
-    output fabric_tnd_fpga_apb_master_paddr_o25;
-    output fabric_tnd_fpga_apb_master_paddr_o26;
-    output fabric_tnd_fpga_apb_master_paddr_o27;
-    output fabric_tnd_fpga_apb_master_paddr_o28;
-    output fabric_tnd_fpga_apb_master_paddr_o29;
-    output fabric_tnd_fpga_apb_master_paddr_o3;
-    output fabric_tnd_fpga_apb_master_paddr_o30;
-    output fabric_tnd_fpga_apb_master_paddr_o31;
-    output fabric_tnd_fpga_apb_master_paddr_o32;
-    output fabric_tnd_fpga_apb_master_paddr_o4;
-    output fabric_tnd_fpga_apb_master_paddr_o5;
-    output fabric_tnd_fpga_apb_master_paddr_o6;
-    output fabric_tnd_fpga_apb_master_paddr_o7;
-    output fabric_tnd_fpga_apb_master_paddr_o8;
-    output fabric_tnd_fpga_apb_master_paddr_o9;
-    output fabric_tnd_fpga_apb_master_penable_o;
-    input fabric_tnd_fpga_apb_master_prdata_i1;
-    input fabric_tnd_fpga_apb_master_prdata_i10;
-    input fabric_tnd_fpga_apb_master_prdata_i11;
-    input fabric_tnd_fpga_apb_master_prdata_i12;
-    input fabric_tnd_fpga_apb_master_prdata_i13;
-    input fabric_tnd_fpga_apb_master_prdata_i14;
-    input fabric_tnd_fpga_apb_master_prdata_i15;
-    input fabric_tnd_fpga_apb_master_prdata_i16;
-    input fabric_tnd_fpga_apb_master_prdata_i17;
-    input fabric_tnd_fpga_apb_master_prdata_i18;
-    input fabric_tnd_fpga_apb_master_prdata_i19;
-    input fabric_tnd_fpga_apb_master_prdata_i2;
-    input fabric_tnd_fpga_apb_master_prdata_i20;
-    input fabric_tnd_fpga_apb_master_prdata_i21;
-    input fabric_tnd_fpga_apb_master_prdata_i22;
-    input fabric_tnd_fpga_apb_master_prdata_i23;
-    input fabric_tnd_fpga_apb_master_prdata_i24;
-    input fabric_tnd_fpga_apb_master_prdata_i25;
-    input fabric_tnd_fpga_apb_master_prdata_i26;
-    input fabric_tnd_fpga_apb_master_prdata_i27;
-    input fabric_tnd_fpga_apb_master_prdata_i28;
-    input fabric_tnd_fpga_apb_master_prdata_i29;
-    input fabric_tnd_fpga_apb_master_prdata_i3;
-    input fabric_tnd_fpga_apb_master_prdata_i30;
-    input fabric_tnd_fpga_apb_master_prdata_i31;
-    input fabric_tnd_fpga_apb_master_prdata_i32;
-    input fabric_tnd_fpga_apb_master_prdata_i4;
-    input fabric_tnd_fpga_apb_master_prdata_i5;
-    input fabric_tnd_fpga_apb_master_prdata_i6;
-    input fabric_tnd_fpga_apb_master_prdata_i7;
-    input fabric_tnd_fpga_apb_master_prdata_i8;
-    input fabric_tnd_fpga_apb_master_prdata_i9;
-    input fabric_tnd_fpga_apb_master_pready_i;
-    output fabric_tnd_fpga_apb_master_psel_o;
-    input fabric_tnd_fpga_apb_master_pslverr_i;
-    output fabric_tnd_fpga_apb_master_pwdata_o1;
-    output fabric_tnd_fpga_apb_master_pwdata_o10;
-    output fabric_tnd_fpga_apb_master_pwdata_o11;
-    output fabric_tnd_fpga_apb_master_pwdata_o12;
-    output fabric_tnd_fpga_apb_master_pwdata_o13;
-    output fabric_tnd_fpga_apb_master_pwdata_o14;
-    output fabric_tnd_fpga_apb_master_pwdata_o15;
-    output fabric_tnd_fpga_apb_master_pwdata_o16;
-    output fabric_tnd_fpga_apb_master_pwdata_o17;
-    output fabric_tnd_fpga_apb_master_pwdata_o18;
-    output fabric_tnd_fpga_apb_master_pwdata_o19;
-    output fabric_tnd_fpga_apb_master_pwdata_o2;
-    output fabric_tnd_fpga_apb_master_pwdata_o20;
-    output fabric_tnd_fpga_apb_master_pwdata_o21;
-    output fabric_tnd_fpga_apb_master_pwdata_o22;
-    output fabric_tnd_fpga_apb_master_pwdata_o23;
-    output fabric_tnd_fpga_apb_master_pwdata_o24;
-    output fabric_tnd_fpga_apb_master_pwdata_o25;
-    output fabric_tnd_fpga_apb_master_pwdata_o26;
-    output fabric_tnd_fpga_apb_master_pwdata_o27;
-    output fabric_tnd_fpga_apb_master_pwdata_o28;
-    output fabric_tnd_fpga_apb_master_pwdata_o29;
-    output fabric_tnd_fpga_apb_master_pwdata_o3;
-    output fabric_tnd_fpga_apb_master_pwdata_o30;
-    output fabric_tnd_fpga_apb_master_pwdata_o31;
-    output fabric_tnd_fpga_apb_master_pwdata_o32;
-    output fabric_tnd_fpga_apb_master_pwdata_o4;
-    output fabric_tnd_fpga_apb_master_pwdata_o5;
-    output fabric_tnd_fpga_apb_master_pwdata_o6;
-    output fabric_tnd_fpga_apb_master_pwdata_o7;
-    output fabric_tnd_fpga_apb_master_pwdata_o8;
-    output fabric_tnd_fpga_apb_master_pwdata_o9;
-    output fabric_tnd_fpga_apb_master_pwrite_o;
-    input fabric_tnd_fpga_atb_master_afready_i;
-    output fabric_tnd_fpga_atb_master_afvalid_o;
-    input fabric_tnd_fpga_atb_master_atbytes_i1;
-    input fabric_tnd_fpga_atb_master_atbytes_i2;
-    input fabric_tnd_fpga_atb_master_atbytes_i3;
-    input fabric_tnd_fpga_atb_master_atbytes_i4;
-    input fabric_tnd_fpga_atb_master_atdata_i1;
-    input fabric_tnd_fpga_atb_master_atdata_i10;
-    input fabric_tnd_fpga_atb_master_atdata_i100;
-    input fabric_tnd_fpga_atb_master_atdata_i101;
-    input fabric_tnd_fpga_atb_master_atdata_i102;
-    input fabric_tnd_fpga_atb_master_atdata_i103;
-    input fabric_tnd_fpga_atb_master_atdata_i104;
-    input fabric_tnd_fpga_atb_master_atdata_i105;
-    input fabric_tnd_fpga_atb_master_atdata_i106;
-    input fabric_tnd_fpga_atb_master_atdata_i107;
-    input fabric_tnd_fpga_atb_master_atdata_i108;
-    input fabric_tnd_fpga_atb_master_atdata_i109;
-    input fabric_tnd_fpga_atb_master_atdata_i11;
-    input fabric_tnd_fpga_atb_master_atdata_i110;
-    input fabric_tnd_fpga_atb_master_atdata_i111;
-    input fabric_tnd_fpga_atb_master_atdata_i112;
-    input fabric_tnd_fpga_atb_master_atdata_i113;
-    input fabric_tnd_fpga_atb_master_atdata_i114;
-    input fabric_tnd_fpga_atb_master_atdata_i115;
-    input fabric_tnd_fpga_atb_master_atdata_i116;
-    input fabric_tnd_fpga_atb_master_atdata_i117;
-    input fabric_tnd_fpga_atb_master_atdata_i118;
-    input fabric_tnd_fpga_atb_master_atdata_i119;
-    input fabric_tnd_fpga_atb_master_atdata_i12;
-    input fabric_tnd_fpga_atb_master_atdata_i120;
-    input fabric_tnd_fpga_atb_master_atdata_i121;
-    input fabric_tnd_fpga_atb_master_atdata_i122;
-    input fabric_tnd_fpga_atb_master_atdata_i123;
-    input fabric_tnd_fpga_atb_master_atdata_i124;
-    input fabric_tnd_fpga_atb_master_atdata_i125;
-    input fabric_tnd_fpga_atb_master_atdata_i126;
-    input fabric_tnd_fpga_atb_master_atdata_i127;
-    input fabric_tnd_fpga_atb_master_atdata_i128;
-    input fabric_tnd_fpga_atb_master_atdata_i13;
-    input fabric_tnd_fpga_atb_master_atdata_i14;
-    input fabric_tnd_fpga_atb_master_atdata_i15;
-    input fabric_tnd_fpga_atb_master_atdata_i16;
-    input fabric_tnd_fpga_atb_master_atdata_i17;
-    input fabric_tnd_fpga_atb_master_atdata_i18;
-    input fabric_tnd_fpga_atb_master_atdata_i19;
-    input fabric_tnd_fpga_atb_master_atdata_i2;
-    input fabric_tnd_fpga_atb_master_atdata_i20;
-    input fabric_tnd_fpga_atb_master_atdata_i21;
-    input fabric_tnd_fpga_atb_master_atdata_i22;
-    input fabric_tnd_fpga_atb_master_atdata_i23;
-    input fabric_tnd_fpga_atb_master_atdata_i24;
-    input fabric_tnd_fpga_atb_master_atdata_i25;
-    input fabric_tnd_fpga_atb_master_atdata_i26;
-    input fabric_tnd_fpga_atb_master_atdata_i27;
-    input fabric_tnd_fpga_atb_master_atdata_i28;
-    input fabric_tnd_fpga_atb_master_atdata_i29;
-    input fabric_tnd_fpga_atb_master_atdata_i3;
-    input fabric_tnd_fpga_atb_master_atdata_i30;
-    input fabric_tnd_fpga_atb_master_atdata_i31;
-    input fabric_tnd_fpga_atb_master_atdata_i32;
-    input fabric_tnd_fpga_atb_master_atdata_i33;
-    input fabric_tnd_fpga_atb_master_atdata_i34;
-    input fabric_tnd_fpga_atb_master_atdata_i35;
-    input fabric_tnd_fpga_atb_master_atdata_i36;
-    input fabric_tnd_fpga_atb_master_atdata_i37;
-    input fabric_tnd_fpga_atb_master_atdata_i38;
-    input fabric_tnd_fpga_atb_master_atdata_i39;
-    input fabric_tnd_fpga_atb_master_atdata_i4;
-    input fabric_tnd_fpga_atb_master_atdata_i40;
-    input fabric_tnd_fpga_atb_master_atdata_i41;
-    input fabric_tnd_fpga_atb_master_atdata_i42;
-    input fabric_tnd_fpga_atb_master_atdata_i43;
-    input fabric_tnd_fpga_atb_master_atdata_i44;
-    input fabric_tnd_fpga_atb_master_atdata_i45;
-    input fabric_tnd_fpga_atb_master_atdata_i46;
-    input fabric_tnd_fpga_atb_master_atdata_i47;
-    input fabric_tnd_fpga_atb_master_atdata_i48;
-    input fabric_tnd_fpga_atb_master_atdata_i49;
-    input fabric_tnd_fpga_atb_master_atdata_i5;
-    input fabric_tnd_fpga_atb_master_atdata_i50;
-    input fabric_tnd_fpga_atb_master_atdata_i51;
-    input fabric_tnd_fpga_atb_master_atdata_i52;
-    input fabric_tnd_fpga_atb_master_atdata_i53;
-    input fabric_tnd_fpga_atb_master_atdata_i54;
-    input fabric_tnd_fpga_atb_master_atdata_i55;
-    input fabric_tnd_fpga_atb_master_atdata_i56;
-    input fabric_tnd_fpga_atb_master_atdata_i57;
-    input fabric_tnd_fpga_atb_master_atdata_i58;
-    input fabric_tnd_fpga_atb_master_atdata_i59;
-    input fabric_tnd_fpga_atb_master_atdata_i6;
-    input fabric_tnd_fpga_atb_master_atdata_i60;
-    input fabric_tnd_fpga_atb_master_atdata_i61;
-    input fabric_tnd_fpga_atb_master_atdata_i62;
-    input fabric_tnd_fpga_atb_master_atdata_i63;
-    input fabric_tnd_fpga_atb_master_atdata_i64;
-    input fabric_tnd_fpga_atb_master_atdata_i65;
-    input fabric_tnd_fpga_atb_master_atdata_i66;
-    input fabric_tnd_fpga_atb_master_atdata_i67;
-    input fabric_tnd_fpga_atb_master_atdata_i68;
-    input fabric_tnd_fpga_atb_master_atdata_i69;
-    input fabric_tnd_fpga_atb_master_atdata_i7;
-    input fabric_tnd_fpga_atb_master_atdata_i70;
-    input fabric_tnd_fpga_atb_master_atdata_i71;
-    input fabric_tnd_fpga_atb_master_atdata_i72;
-    input fabric_tnd_fpga_atb_master_atdata_i73;
-    input fabric_tnd_fpga_atb_master_atdata_i74;
-    input fabric_tnd_fpga_atb_master_atdata_i75;
-    input fabric_tnd_fpga_atb_master_atdata_i76;
-    input fabric_tnd_fpga_atb_master_atdata_i77;
-    input fabric_tnd_fpga_atb_master_atdata_i78;
-    input fabric_tnd_fpga_atb_master_atdata_i79;
-    input fabric_tnd_fpga_atb_master_atdata_i8;
-    input fabric_tnd_fpga_atb_master_atdata_i80;
-    input fabric_tnd_fpga_atb_master_atdata_i81;
-    input fabric_tnd_fpga_atb_master_atdata_i82;
-    input fabric_tnd_fpga_atb_master_atdata_i83;
-    input fabric_tnd_fpga_atb_master_atdata_i84;
-    input fabric_tnd_fpga_atb_master_atdata_i85;
-    input fabric_tnd_fpga_atb_master_atdata_i86;
-    input fabric_tnd_fpga_atb_master_atdata_i87;
-    input fabric_tnd_fpga_atb_master_atdata_i88;
-    input fabric_tnd_fpga_atb_master_atdata_i89;
-    input fabric_tnd_fpga_atb_master_atdata_i9;
-    input fabric_tnd_fpga_atb_master_atdata_i90;
-    input fabric_tnd_fpga_atb_master_atdata_i91;
-    input fabric_tnd_fpga_atb_master_atdata_i92;
-    input fabric_tnd_fpga_atb_master_atdata_i93;
-    input fabric_tnd_fpga_atb_master_atdata_i94;
-    input fabric_tnd_fpga_atb_master_atdata_i95;
-    input fabric_tnd_fpga_atb_master_atdata_i96;
-    input fabric_tnd_fpga_atb_master_atdata_i97;
-    input fabric_tnd_fpga_atb_master_atdata_i98;
-    input fabric_tnd_fpga_atb_master_atdata_i99;
-    input fabric_tnd_fpga_atb_master_atid_i1;
-    input fabric_tnd_fpga_atb_master_atid_i2;
-    input fabric_tnd_fpga_atb_master_atid_i3;
-    input fabric_tnd_fpga_atb_master_atid_i4;
-    input fabric_tnd_fpga_atb_master_atid_i5;
-    input fabric_tnd_fpga_atb_master_atid_i6;
-    input fabric_tnd_fpga_atb_master_atid_i7;
-    output fabric_tnd_fpga_atb_master_atready_o;
-    input fabric_tnd_fpga_atb_master_atvalid_i;
-    output fabric_tnd_fpga_atb_master_syncreq_o;
-    output fabric_tnd_hssl_apb_master_paddr_o1;
-    output fabric_tnd_hssl_apb_master_paddr_o10;
-    output fabric_tnd_hssl_apb_master_paddr_o11;
-    output fabric_tnd_hssl_apb_master_paddr_o12;
-    output fabric_tnd_hssl_apb_master_paddr_o13;
-    output fabric_tnd_hssl_apb_master_paddr_o14;
-    output fabric_tnd_hssl_apb_master_paddr_o15;
-    output fabric_tnd_hssl_apb_master_paddr_o16;
-    output fabric_tnd_hssl_apb_master_paddr_o17;
-    output fabric_tnd_hssl_apb_master_paddr_o18;
-    output fabric_tnd_hssl_apb_master_paddr_o19;
-    output fabric_tnd_hssl_apb_master_paddr_o2;
-    output fabric_tnd_hssl_apb_master_paddr_o20;
-    output fabric_tnd_hssl_apb_master_paddr_o21;
-    output fabric_tnd_hssl_apb_master_paddr_o22;
-    output fabric_tnd_hssl_apb_master_paddr_o23;
-    output fabric_tnd_hssl_apb_master_paddr_o24;
-    output fabric_tnd_hssl_apb_master_paddr_o25;
-    output fabric_tnd_hssl_apb_master_paddr_o26;
-    output fabric_tnd_hssl_apb_master_paddr_o27;
-    output fabric_tnd_hssl_apb_master_paddr_o28;
-    output fabric_tnd_hssl_apb_master_paddr_o29;
-    output fabric_tnd_hssl_apb_master_paddr_o3;
-    output fabric_tnd_hssl_apb_master_paddr_o30;
-    output fabric_tnd_hssl_apb_master_paddr_o31;
-    output fabric_tnd_hssl_apb_master_paddr_o32;
-    output fabric_tnd_hssl_apb_master_paddr_o4;
-    output fabric_tnd_hssl_apb_master_paddr_o5;
-    output fabric_tnd_hssl_apb_master_paddr_o6;
-    output fabric_tnd_hssl_apb_master_paddr_o7;
-    output fabric_tnd_hssl_apb_master_paddr_o8;
-    output fabric_tnd_hssl_apb_master_paddr_o9;
-    output fabric_tnd_hssl_apb_master_penable_o;
-    input fabric_tnd_hssl_apb_master_prdata_i1;
-    input fabric_tnd_hssl_apb_master_prdata_i10;
-    input fabric_tnd_hssl_apb_master_prdata_i11;
-    input fabric_tnd_hssl_apb_master_prdata_i12;
-    input fabric_tnd_hssl_apb_master_prdata_i13;
-    input fabric_tnd_hssl_apb_master_prdata_i14;
-    input fabric_tnd_hssl_apb_master_prdata_i15;
-    input fabric_tnd_hssl_apb_master_prdata_i16;
-    input fabric_tnd_hssl_apb_master_prdata_i17;
-    input fabric_tnd_hssl_apb_master_prdata_i18;
-    input fabric_tnd_hssl_apb_master_prdata_i19;
-    input fabric_tnd_hssl_apb_master_prdata_i2;
-    input fabric_tnd_hssl_apb_master_prdata_i20;
-    input fabric_tnd_hssl_apb_master_prdata_i21;
-    input fabric_tnd_hssl_apb_master_prdata_i22;
-    input fabric_tnd_hssl_apb_master_prdata_i23;
-    input fabric_tnd_hssl_apb_master_prdata_i24;
-    input fabric_tnd_hssl_apb_master_prdata_i25;
-    input fabric_tnd_hssl_apb_master_prdata_i26;
-    input fabric_tnd_hssl_apb_master_prdata_i27;
-    input fabric_tnd_hssl_apb_master_prdata_i28;
-    input fabric_tnd_hssl_apb_master_prdata_i29;
-    input fabric_tnd_hssl_apb_master_prdata_i3;
-    input fabric_tnd_hssl_apb_master_prdata_i30;
-    input fabric_tnd_hssl_apb_master_prdata_i31;
-    input fabric_tnd_hssl_apb_master_prdata_i32;
-    input fabric_tnd_hssl_apb_master_prdata_i4;
-    input fabric_tnd_hssl_apb_master_prdata_i5;
-    input fabric_tnd_hssl_apb_master_prdata_i6;
-    input fabric_tnd_hssl_apb_master_prdata_i7;
-    input fabric_tnd_hssl_apb_master_prdata_i8;
-    input fabric_tnd_hssl_apb_master_prdata_i9;
-    input fabric_tnd_hssl_apb_master_pready_i;
-    output fabric_tnd_hssl_apb_master_psel_o;
-    input fabric_tnd_hssl_apb_master_pslverr_i;
-    output fabric_tnd_hssl_apb_master_pwdata_o1;
-    output fabric_tnd_hssl_apb_master_pwdata_o10;
-    output fabric_tnd_hssl_apb_master_pwdata_o11;
-    output fabric_tnd_hssl_apb_master_pwdata_o12;
-    output fabric_tnd_hssl_apb_master_pwdata_o13;
-    output fabric_tnd_hssl_apb_master_pwdata_o14;
-    output fabric_tnd_hssl_apb_master_pwdata_o15;
-    output fabric_tnd_hssl_apb_master_pwdata_o16;
-    output fabric_tnd_hssl_apb_master_pwdata_o17;
-    output fabric_tnd_hssl_apb_master_pwdata_o18;
-    output fabric_tnd_hssl_apb_master_pwdata_o19;
-    output fabric_tnd_hssl_apb_master_pwdata_o2;
-    output fabric_tnd_hssl_apb_master_pwdata_o20;
-    output fabric_tnd_hssl_apb_master_pwdata_o21;
-    output fabric_tnd_hssl_apb_master_pwdata_o22;
-    output fabric_tnd_hssl_apb_master_pwdata_o23;
-    output fabric_tnd_hssl_apb_master_pwdata_o24;
-    output fabric_tnd_hssl_apb_master_pwdata_o25;
-    output fabric_tnd_hssl_apb_master_pwdata_o26;
-    output fabric_tnd_hssl_apb_master_pwdata_o27;
-    output fabric_tnd_hssl_apb_master_pwdata_o28;
-    output fabric_tnd_hssl_apb_master_pwdata_o29;
-    output fabric_tnd_hssl_apb_master_pwdata_o3;
-    output fabric_tnd_hssl_apb_master_pwdata_o30;
-    output fabric_tnd_hssl_apb_master_pwdata_o31;
-    output fabric_tnd_hssl_apb_master_pwdata_o32;
-    output fabric_tnd_hssl_apb_master_pwdata_o4;
-    output fabric_tnd_hssl_apb_master_pwdata_o5;
-    output fabric_tnd_hssl_apb_master_pwdata_o6;
-    output fabric_tnd_hssl_apb_master_pwdata_o7;
-    output fabric_tnd_hssl_apb_master_pwdata_o8;
-    output fabric_tnd_hssl_apb_master_pwdata_o9;
-    output fabric_tnd_hssl_apb_master_pwrite_o;
-    output fabric_tnd_hssl_atb_master_afready_o;
-    input fabric_tnd_hssl_atb_master_afvalid_i;
-    output fabric_tnd_hssl_atb_master_atbytes_o1;
-    output fabric_tnd_hssl_atb_master_atbytes_o2;
-    output fabric_tnd_hssl_atb_master_atbytes_o3;
-    output fabric_tnd_hssl_atb_master_atbytes_o4;
-    output fabric_tnd_hssl_atb_master_atdata_o1;
-    output fabric_tnd_hssl_atb_master_atdata_o10;
-    output fabric_tnd_hssl_atb_master_atdata_o100;
-    output fabric_tnd_hssl_atb_master_atdata_o101;
-    output fabric_tnd_hssl_atb_master_atdata_o102;
-    output fabric_tnd_hssl_atb_master_atdata_o103;
-    output fabric_tnd_hssl_atb_master_atdata_o104;
-    output fabric_tnd_hssl_atb_master_atdata_o105;
-    output fabric_tnd_hssl_atb_master_atdata_o106;
-    output fabric_tnd_hssl_atb_master_atdata_o107;
-    output fabric_tnd_hssl_atb_master_atdata_o108;
-    output fabric_tnd_hssl_atb_master_atdata_o109;
-    output fabric_tnd_hssl_atb_master_atdata_o11;
-    output fabric_tnd_hssl_atb_master_atdata_o110;
-    output fabric_tnd_hssl_atb_master_atdata_o111;
-    output fabric_tnd_hssl_atb_master_atdata_o112;
-    output fabric_tnd_hssl_atb_master_atdata_o113;
-    output fabric_tnd_hssl_atb_master_atdata_o114;
-    output fabric_tnd_hssl_atb_master_atdata_o115;
-    output fabric_tnd_hssl_atb_master_atdata_o116;
-    output fabric_tnd_hssl_atb_master_atdata_o117;
-    output fabric_tnd_hssl_atb_master_atdata_o118;
-    output fabric_tnd_hssl_atb_master_atdata_o119;
-    output fabric_tnd_hssl_atb_master_atdata_o12;
-    output fabric_tnd_hssl_atb_master_atdata_o120;
-    output fabric_tnd_hssl_atb_master_atdata_o121;
-    output fabric_tnd_hssl_atb_master_atdata_o122;
-    output fabric_tnd_hssl_atb_master_atdata_o123;
-    output fabric_tnd_hssl_atb_master_atdata_o124;
-    output fabric_tnd_hssl_atb_master_atdata_o125;
-    output fabric_tnd_hssl_atb_master_atdata_o126;
-    output fabric_tnd_hssl_atb_master_atdata_o127;
-    output fabric_tnd_hssl_atb_master_atdata_o128;
-    output fabric_tnd_hssl_atb_master_atdata_o13;
-    output fabric_tnd_hssl_atb_master_atdata_o14;
-    output fabric_tnd_hssl_atb_master_atdata_o15;
-    output fabric_tnd_hssl_atb_master_atdata_o16;
-    output fabric_tnd_hssl_atb_master_atdata_o17;
-    output fabric_tnd_hssl_atb_master_atdata_o18;
-    output fabric_tnd_hssl_atb_master_atdata_o19;
-    output fabric_tnd_hssl_atb_master_atdata_o2;
-    output fabric_tnd_hssl_atb_master_atdata_o20;
-    output fabric_tnd_hssl_atb_master_atdata_o21;
-    output fabric_tnd_hssl_atb_master_atdata_o22;
-    output fabric_tnd_hssl_atb_master_atdata_o23;
-    output fabric_tnd_hssl_atb_master_atdata_o24;
-    output fabric_tnd_hssl_atb_master_atdata_o25;
-    output fabric_tnd_hssl_atb_master_atdata_o26;
-    output fabric_tnd_hssl_atb_master_atdata_o27;
-    output fabric_tnd_hssl_atb_master_atdata_o28;
-    output fabric_tnd_hssl_atb_master_atdata_o29;
-    output fabric_tnd_hssl_atb_master_atdata_o3;
-    output fabric_tnd_hssl_atb_master_atdata_o30;
-    output fabric_tnd_hssl_atb_master_atdata_o31;
-    output fabric_tnd_hssl_atb_master_atdata_o32;
-    output fabric_tnd_hssl_atb_master_atdata_o33;
-    output fabric_tnd_hssl_atb_master_atdata_o34;
-    output fabric_tnd_hssl_atb_master_atdata_o35;
-    output fabric_tnd_hssl_atb_master_atdata_o36;
-    output fabric_tnd_hssl_atb_master_atdata_o37;
-    output fabric_tnd_hssl_atb_master_atdata_o38;
-    output fabric_tnd_hssl_atb_master_atdata_o39;
-    output fabric_tnd_hssl_atb_master_atdata_o4;
-    output fabric_tnd_hssl_atb_master_atdata_o40;
-    output fabric_tnd_hssl_atb_master_atdata_o41;
-    output fabric_tnd_hssl_atb_master_atdata_o42;
-    output fabric_tnd_hssl_atb_master_atdata_o43;
-    output fabric_tnd_hssl_atb_master_atdata_o44;
-    output fabric_tnd_hssl_atb_master_atdata_o45;
-    output fabric_tnd_hssl_atb_master_atdata_o46;
-    output fabric_tnd_hssl_atb_master_atdata_o47;
-    output fabric_tnd_hssl_atb_master_atdata_o48;
-    output fabric_tnd_hssl_atb_master_atdata_o49;
-    output fabric_tnd_hssl_atb_master_atdata_o5;
-    output fabric_tnd_hssl_atb_master_atdata_o50;
-    output fabric_tnd_hssl_atb_master_atdata_o51;
-    output fabric_tnd_hssl_atb_master_atdata_o52;
-    output fabric_tnd_hssl_atb_master_atdata_o53;
-    output fabric_tnd_hssl_atb_master_atdata_o54;
-    output fabric_tnd_hssl_atb_master_atdata_o55;
-    output fabric_tnd_hssl_atb_master_atdata_o56;
-    output fabric_tnd_hssl_atb_master_atdata_o57;
-    output fabric_tnd_hssl_atb_master_atdata_o58;
-    output fabric_tnd_hssl_atb_master_atdata_o59;
-    output fabric_tnd_hssl_atb_master_atdata_o6;
-    output fabric_tnd_hssl_atb_master_atdata_o60;
-    output fabric_tnd_hssl_atb_master_atdata_o61;
-    output fabric_tnd_hssl_atb_master_atdata_o62;
-    output fabric_tnd_hssl_atb_master_atdata_o63;
-    output fabric_tnd_hssl_atb_master_atdata_o64;
-    output fabric_tnd_hssl_atb_master_atdata_o65;
-    output fabric_tnd_hssl_atb_master_atdata_o66;
-    output fabric_tnd_hssl_atb_master_atdata_o67;
-    output fabric_tnd_hssl_atb_master_atdata_o68;
-    output fabric_tnd_hssl_atb_master_atdata_o69;
-    output fabric_tnd_hssl_atb_master_atdata_o7;
-    output fabric_tnd_hssl_atb_master_atdata_o70;
-    output fabric_tnd_hssl_atb_master_atdata_o71;
-    output fabric_tnd_hssl_atb_master_atdata_o72;
-    output fabric_tnd_hssl_atb_master_atdata_o73;
-    output fabric_tnd_hssl_atb_master_atdata_o74;
-    output fabric_tnd_hssl_atb_master_atdata_o75;
-    output fabric_tnd_hssl_atb_master_atdata_o76;
-    output fabric_tnd_hssl_atb_master_atdata_o77;
-    output fabric_tnd_hssl_atb_master_atdata_o78;
-    output fabric_tnd_hssl_atb_master_atdata_o79;
-    output fabric_tnd_hssl_atb_master_atdata_o8;
-    output fabric_tnd_hssl_atb_master_atdata_o80;
-    output fabric_tnd_hssl_atb_master_atdata_o81;
-    output fabric_tnd_hssl_atb_master_atdata_o82;
-    output fabric_tnd_hssl_atb_master_atdata_o83;
-    output fabric_tnd_hssl_atb_master_atdata_o84;
-    output fabric_tnd_hssl_atb_master_atdata_o85;
-    output fabric_tnd_hssl_atb_master_atdata_o86;
-    output fabric_tnd_hssl_atb_master_atdata_o87;
-    output fabric_tnd_hssl_atb_master_atdata_o88;
-    output fabric_tnd_hssl_atb_master_atdata_o89;
-    output fabric_tnd_hssl_atb_master_atdata_o9;
-    output fabric_tnd_hssl_atb_master_atdata_o90;
-    output fabric_tnd_hssl_atb_master_atdata_o91;
-    output fabric_tnd_hssl_atb_master_atdata_o92;
-    output fabric_tnd_hssl_atb_master_atdata_o93;
-    output fabric_tnd_hssl_atb_master_atdata_o94;
-    output fabric_tnd_hssl_atb_master_atdata_o95;
-    output fabric_tnd_hssl_atb_master_atdata_o96;
-    output fabric_tnd_hssl_atb_master_atdata_o97;
-    output fabric_tnd_hssl_atb_master_atdata_o98;
-    output fabric_tnd_hssl_atb_master_atdata_o99;
-    output fabric_tnd_hssl_atb_master_atid_o1;
-    output fabric_tnd_hssl_atb_master_atid_o2;
-    output fabric_tnd_hssl_atb_master_atid_o3;
-    output fabric_tnd_hssl_atb_master_atid_o4;
-    output fabric_tnd_hssl_atb_master_atid_o5;
-    output fabric_tnd_hssl_atb_master_atid_o6;
-    output fabric_tnd_hssl_atb_master_atid_o7;
-    input fabric_tnd_hssl_atb_master_atready_i;
-    output fabric_tnd_hssl_atb_master_atvalid_o;
-    input fabric_tnd_hssl_atb_master_syncreq_i;
-    output fabric_tnd_hssl_flushin_o;
-    output fabric_tnd_hssl_trigin_o;
-    output fabric_tnd_trace_clk_traceoutportintf_o;
-    output fabric_tnd_trace_ctl_traceoutportintf_o;
-    output fabric_tnd_trace_data_traceoutportintf_o1;
-    output fabric_tnd_trace_data_traceoutportintf_o10;
-    output fabric_tnd_trace_data_traceoutportintf_o11;
-    output fabric_tnd_trace_data_traceoutportintf_o12;
-    output fabric_tnd_trace_data_traceoutportintf_o13;
-    output fabric_tnd_trace_data_traceoutportintf_o14;
-    output fabric_tnd_trace_data_traceoutportintf_o15;
-    output fabric_tnd_trace_data_traceoutportintf_o16;
-    output fabric_tnd_trace_data_traceoutportintf_o17;
-    output fabric_tnd_trace_data_traceoutportintf_o18;
-    output fabric_tnd_trace_data_traceoutportintf_o19;
-    output fabric_tnd_trace_data_traceoutportintf_o2;
-    output fabric_tnd_trace_data_traceoutportintf_o20;
-    output fabric_tnd_trace_data_traceoutportintf_o21;
-    output fabric_tnd_trace_data_traceoutportintf_o22;
-    output fabric_tnd_trace_data_traceoutportintf_o23;
-    output fabric_tnd_trace_data_traceoutportintf_o24;
-    output fabric_tnd_trace_data_traceoutportintf_o25;
-    output fabric_tnd_trace_data_traceoutportintf_o26;
-    output fabric_tnd_trace_data_traceoutportintf_o27;
-    output fabric_tnd_trace_data_traceoutportintf_o28;
-    output fabric_tnd_trace_data_traceoutportintf_o29;
-    output fabric_tnd_trace_data_traceoutportintf_o3;
-    output fabric_tnd_trace_data_traceoutportintf_o30;
-    output fabric_tnd_trace_data_traceoutportintf_o31;
-    output fabric_tnd_trace_data_traceoutportintf_o32;
-    output fabric_tnd_trace_data_traceoutportintf_o4;
-    output fabric_tnd_trace_data_traceoutportintf_o5;
-    output fabric_tnd_trace_data_traceoutportintf_o6;
-    output fabric_tnd_trace_data_traceoutportintf_o7;
-    output fabric_tnd_trace_data_traceoutportintf_o8;
-    output fabric_tnd_trace_data_traceoutportintf_o9;
-    output fabric_tst_pll_lock_o1;
-    output fabric_tst_pll_lock_o2;
-    output fabric_tst_pll_lock_o3;
-    output fabric_tst_pll_lock_o4;
-    output fabric_tst_pll_lock_o5;
-    output fabric_tst_pll_lock_o6;
-    output fabric_tst_pll_lock_o7;
-    output fabric_tsvalue_tsgen_fpga_o1;
-    output fabric_tsvalue_tsgen_fpga_o10;
-    output fabric_tsvalue_tsgen_fpga_o11;
-    output fabric_tsvalue_tsgen_fpga_o12;
-    output fabric_tsvalue_tsgen_fpga_o13;
-    output fabric_tsvalue_tsgen_fpga_o14;
-    output fabric_tsvalue_tsgen_fpga_o15;
-    output fabric_tsvalue_tsgen_fpga_o16;
-    output fabric_tsvalue_tsgen_fpga_o17;
-    output fabric_tsvalue_tsgen_fpga_o18;
-    output fabric_tsvalue_tsgen_fpga_o19;
-    output fabric_tsvalue_tsgen_fpga_o2;
-    output fabric_tsvalue_tsgen_fpga_o20;
-    output fabric_tsvalue_tsgen_fpga_o21;
-    output fabric_tsvalue_tsgen_fpga_o22;
-    output fabric_tsvalue_tsgen_fpga_o23;
-    output fabric_tsvalue_tsgen_fpga_o24;
-    output fabric_tsvalue_tsgen_fpga_o25;
-    output fabric_tsvalue_tsgen_fpga_o26;
-    output fabric_tsvalue_tsgen_fpga_o27;
-    output fabric_tsvalue_tsgen_fpga_o28;
-    output fabric_tsvalue_tsgen_fpga_o29;
-    output fabric_tsvalue_tsgen_fpga_o3;
-    output fabric_tsvalue_tsgen_fpga_o30;
-    output fabric_tsvalue_tsgen_fpga_o31;
-    output fabric_tsvalue_tsgen_fpga_o32;
-    output fabric_tsvalue_tsgen_fpga_o33;
-    output fabric_tsvalue_tsgen_fpga_o34;
-    output fabric_tsvalue_tsgen_fpga_o35;
-    output fabric_tsvalue_tsgen_fpga_o36;
-    output fabric_tsvalue_tsgen_fpga_o37;
-    output fabric_tsvalue_tsgen_fpga_o38;
-    output fabric_tsvalue_tsgen_fpga_o39;
-    output fabric_tsvalue_tsgen_fpga_o4;
-    output fabric_tsvalue_tsgen_fpga_o40;
-    output fabric_tsvalue_tsgen_fpga_o41;
-    output fabric_tsvalue_tsgen_fpga_o42;
-    output fabric_tsvalue_tsgen_fpga_o43;
-    output fabric_tsvalue_tsgen_fpga_o44;
-    output fabric_tsvalue_tsgen_fpga_o45;
-    output fabric_tsvalue_tsgen_fpga_o46;
-    output fabric_tsvalue_tsgen_fpga_o47;
-    output fabric_tsvalue_tsgen_fpga_o48;
-    output fabric_tsvalue_tsgen_fpga_o49;
-    output fabric_tsvalue_tsgen_fpga_o5;
-    output fabric_tsvalue_tsgen_fpga_o50;
-    output fabric_tsvalue_tsgen_fpga_o51;
-    output fabric_tsvalue_tsgen_fpga_o52;
-    output fabric_tsvalue_tsgen_fpga_o53;
-    output fabric_tsvalue_tsgen_fpga_o54;
-    output fabric_tsvalue_tsgen_fpga_o55;
-    output fabric_tsvalue_tsgen_fpga_o56;
-    output fabric_tsvalue_tsgen_fpga_o57;
-    output fabric_tsvalue_tsgen_fpga_o58;
-    output fabric_tsvalue_tsgen_fpga_o59;
-    output fabric_tsvalue_tsgen_fpga_o6;
-    output fabric_tsvalue_tsgen_fpga_o60;
-    output fabric_tsvalue_tsgen_fpga_o61;
-    output fabric_tsvalue_tsgen_fpga_o62;
-    output fabric_tsvalue_tsgen_fpga_o63;
-    output fabric_tsvalue_tsgen_fpga_o64;
-    output fabric_tsvalue_tsgen_fpga_o7;
-    output fabric_tsvalue_tsgen_fpga_o8;
-    output fabric_tsvalue_tsgen_fpga_o9;
-    output fabric_watchdog0_signal_0_o;
-    output fabric_watchdog0_signal_1_o;
-    output fabric_watchdog1_signal_0_o;
-    output fabric_watchdog1_signal_1_o;
-    output fabric_watchdog2_signal_0_o;
-    output fabric_watchdog2_signal_1_o;
-    output fabric_watchdog3_signal_0_o;
-    output fabric_watchdog3_signal_1_o;
-    parameter ahb_config = 0;
-    parameter bsm_config = 0;
-endmodule
-
-(* blackbox *)
-module NX_SOC_INTERFACE_V1(fabric_lowskew_o1, fabric_lowskew_i1, fabric_lowskew_i2, fabric_lowskew_i3, fabric_lowskew_i4, fabric_lowskew_i5, fabric_lowskew_i6, fabric_lowskew_i7, fabric_lowskew_i8, fabric_lowskew_i9, fabric_lowskew_i10, fabric_lowskew_o2, fabric_fpga_nic_rstn_i1, fabric_fpga_nic_rstn_i2, fabric_fpga_nic_rstn_i3, fabric_fpga_nic_rstn_i4, fabric_fpga_nic_rstn_i5, fabric_fpga_nic_rstn_i6, fabric_fpga_nic_rstn_i7, fabric_fpga_nic_rstn_i8, fabric_fpga_nic_rstn_i9
-, fabric_fpga_nic_rstn_i10, fabric_fpga_pmrstn_i, fabric_fpga_sysrstn_i, fabric_fpga_trigger_in_o1, fabric_fpga_trigger_in_o2, fabric_fpga_trigger_in_o3, fabric_fpga_trigger_in_o4, fabric_fpga_trigger_in_o5, fabric_fpga_trigger_in_o6, fabric_fpga_trigger_in_o7, fabric_fpga_trigger_in_o8, fabric_fpga_trigger_out_i1, fabric_fpga_trigger_out_i2, fabric_fpga_trigger_out_i3, fabric_fpga_trigger_out_i4, fabric_fpga_trigger_out_i5, fabric_fpga_trigger_out_i6, fabric_fpga_trigger_out_i7, fabric_fpga_trigger_out_i8, fabric_fpga_interrupt_in_i1, fabric_fpga_interrupt_in_i2
-, fabric_fpga_interrupt_in_i3, fabric_fpga_interrupt_in_i4, fabric_fpga_interrupt_in_i5, fabric_fpga_interrupt_in_i6, fabric_fpga_interrupt_in_i7, fabric_fpga_interrupt_in_i8, fabric_fpga_interrupt_in_i9, fabric_fpga_interrupt_in_i10, fabric_fpga_interrupt_in_i11, fabric_fpga_interrupt_in_i12, fabric_fpga_interrupt_in_i13, fabric_fpga_interrupt_in_i14, fabric_fpga_interrupt_in_i15, fabric_fpga_interrupt_in_i16, fabric_fpga_interrupt_in_i17, fabric_fpga_interrupt_in_i18, fabric_fpga_interrupt_in_i19, fabric_fpga_interrupt_in_i20, fabric_fpga_interrupt_in_i21, fabric_fpga_interrupt_in_i22, fabric_fpga_interrupt_in_i23
-, fabric_fpga_interrupt_in_i24, fabric_fpga_interrupt_in_i25, fabric_fpga_interrupt_in_i26, fabric_fpga_interrupt_in_i27, fabric_fpga_interrupt_in_i28, fabric_fpga_interrupt_in_i29, fabric_fpga_interrupt_in_i30, fabric_fpga_interrupt_in_i31, fabric_fpga_interrupt_in_i32, fabric_fpga_interrupt_in_i33, fabric_fpga_interrupt_in_i34, fabric_fpga_interrupt_in_i35, fabric_fpga_interrupt_in_i36, fabric_fpga_interrupt_in_i37, fabric_fpga_interrupt_in_i38, fabric_fpga_interrupt_in_i39, fabric_fpga_interrupt_in_i40, fabric_fpga_interrupt_in_i41, fabric_fpga_interrupt_in_i42, fabric_fpga_interrupt_in_i43, fabric_fpga_interrupt_in_i44
-, fabric_fpga_interrupt_in_i45, fabric_fpga_interrupt_in_i46, fabric_fpga_interrupt_in_i47, fabric_fpga_interrupt_in_i48, fabric_fpga_interrupt_in_i49, fabric_fpga_interrupt_in_i50, fabric_fpga_interrupt_in_i51, fabric_fpga_interrupt_in_i52, fabric_fpga_interrupt_in_i53, fabric_fpga_interrupt_in_i54, fabric_fpga_interrupt_in_i55, fabric_fpga_interrupt_in_i56, fabric_fpga_interrupt_in_i57, fabric_fpga_interrupt_in_i58, fabric_fpga_interrupt_in_i59, fabric_fpga_interrupt_in_i60, fabric_fpga_interrupt_in_i61, fabric_fpga_interrupt_in_i62, fabric_fpga_interrupt_in_i63, fabric_fpga_interrupt_in_i64, fabric_fpga_interrupt_in_i65
-, fabric_fpga_interrupt_in_i66, fabric_fpga_interrupt_in_i67, fabric_fpga_interrupt_in_i68, fabric_fpga_interrupt_in_i69, fabric_fpga_interrupt_in_i70, fabric_fpga_interrupt_in_i71, fabric_fpga_interrupt_in_i72, fabric_fpga_interrupt_in_i73, fabric_fpga_interrupt_in_i74, fabric_fpga_interrupt_in_i75, fabric_fpga_interrupt_in_i76, fabric_fpga_interrupt_in_i77, fabric_fpga_interrupt_in_i78, fabric_fpga_interrupt_in_i79, fabric_fpga_interrupt_in_i80, fabric_fpga_interrupt_in_i81, fabric_fpga_interrupt_in_i82, fabric_fpga_interrupt_in_i83, fabric_fpga_interrupt_in_i84, fabric_fpga_interrupt_in_i85, fabric_fpga_interrupt_in_i86
-, fabric_fpga_interrupt_in_i87, fabric_fpga_interrupt_in_i88, fabric_fpga_interrupt_in_i89, fabric_fpga_interrupt_in_i90, fabric_fpga_interrupt_in_i91, fabric_fpga_interrupt_in_i92, fabric_fpga_interrupt_in_i93, fabric_fpga_interrupt_in_i94, fabric_fpga_interrupt_in_i95, fabric_fpga_interrupt_in_i96, fabric_fpga_interrupt_in_i97, fabric_fpga_interrupt_in_i98, fabric_fpga_interrupt_in_i99, fabric_fpga_interrupt_in_i100, fabric_fpga_interrupt_in_i101, fabric_fpga_interrupt_in_i102, fabric_fpga_interrupt_in_i103, fabric_fpga_interrupt_in_i104, fabric_fpga_interrupt_in_i105, fabric_fpga_interrupt_in_i106, fabric_fpga_interrupt_in_i107
-, fabric_fpga_interrupt_in_i108, fabric_fpga_interrupt_in_i109, fabric_fpga_interrupt_in_i110, fabric_fpga_interrupt_in_i111, fabric_fpga_interrupt_in_i112, fabric_fpga_interrupt_in_i113, fabric_fpga_interrupt_in_i114, fabric_fpga_interrupt_in_i115, fabric_fpga_interrupt_in_i116, fabric_fpga_interrupt_in_i117, fabric_fpga_interrupt_in_i118, fabric_fpga_interrupt_in_i119, fabric_fpga_interrupt_in_i120, fabric_sysc_hold_on_debug_i, fabric_fpga_events60_i1, fabric_fpga_events60_i2, fabric_fpga_events60_i3, fabric_fpga_events60_i4, fabric_fpga_events60_i5, fabric_fpga_events60_i6, fabric_fpga_events60_i7
-, fabric_fpga_events60_i8, fabric_fpga_events60_i9, fabric_fpga_events60_i10, fabric_fpga_events60_i11, fabric_fpga_events60_i12, fabric_fpga_events60_i13, fabric_fpga_events60_i14, fabric_fpga_events60_i15, fabric_fpga_events60_i16, fabric_fpga_events60_i17, fabric_fpga_events60_i18, fabric_fpga_events60_i19, fabric_fpga_events60_i20, fabric_fpga_events60_i21, fabric_fpga_events60_i22, fabric_fpga_events60_i23, fabric_fpga_events60_i24, fabric_fpga_events60_i25, fabric_fpga_events60_i26, fabric_fpga_events60_i27, fabric_fpga_events60_i28
-, fabric_fpga_events60_i29, fabric_fpga_events60_i30, fabric_fpga_events60_i31, fabric_fpga_events60_i32, fabric_fpga_events60_i33, fabric_fpga_events60_i34, fabric_fpga_events60_i35, fabric_fpga_events60_i36, fabric_fpga_events60_i37, fabric_fpga_events60_i38, fabric_fpga_events60_i39, fabric_fpga_events60_i40, fabric_fpga_events60_i41, fabric_fpga_events60_i42, fabric_fpga_events60_i43, fabric_fpga_events60_i44, fabric_fpga_events60_i45, fabric_fpga_events60_i46, fabric_fpga_events60_i47, fabric_fpga_events60_i48, fabric_fpga_events60_i49
-, fabric_fpga_events60_i50, fabric_fpga_events60_i51, fabric_fpga_events60_i52, fabric_fpga_events60_i53, fabric_fpga_events60_i54, fabric_fpga_events60_i55, fabric_fpga_events60_i56, fabric_fpga_events60_i57, fabric_fpga_events60_i58, fabric_fpga_events60_i59, fabric_fpga_events60_i60, fabric_fpga_araddr_axi_s1_o1, fabric_fpga_araddr_axi_s1_o2, fabric_fpga_araddr_axi_s1_o3, fabric_fpga_araddr_axi_s1_o4, fabric_fpga_araddr_axi_s1_o5, fabric_fpga_araddr_axi_s1_o6, fabric_fpga_araddr_axi_s1_o7, fabric_fpga_araddr_axi_s1_o8, fabric_fpga_araddr_axi_s1_o9, fabric_fpga_araddr_axi_s1_o10
-, fabric_fpga_araddr_axi_s1_o11, fabric_fpga_araddr_axi_s1_o12, fabric_fpga_araddr_axi_s1_o13, fabric_fpga_araddr_axi_s1_o14, fabric_fpga_araddr_axi_s1_o15, fabric_fpga_araddr_axi_s1_o16, fabric_fpga_araddr_axi_s1_o17, fabric_fpga_araddr_axi_s1_o18, fabric_fpga_araddr_axi_s1_o19, fabric_fpga_araddr_axi_s1_o20, fabric_fpga_araddr_axi_s1_o21, fabric_fpga_araddr_axi_s1_o22, fabric_fpga_araddr_axi_s1_o23, fabric_fpga_araddr_axi_s1_o24, fabric_fpga_araddr_axi_s1_o25, fabric_fpga_araddr_axi_s1_o26, fabric_fpga_araddr_axi_s1_o27, fabric_fpga_araddr_axi_s1_o28, fabric_fpga_araddr_axi_s1_o29, fabric_fpga_araddr_axi_s1_o30, fabric_fpga_araddr_axi_s1_o31
-, fabric_fpga_araddr_axi_s1_o32, fabric_fpga_araddr_axi_s1_o33, fabric_fpga_araddr_axi_s1_o34, fabric_fpga_araddr_axi_s1_o35, fabric_fpga_araddr_axi_s1_o36, fabric_fpga_araddr_axi_s1_o37, fabric_fpga_araddr_axi_s1_o38, fabric_fpga_araddr_axi_s1_o39, fabric_fpga_araddr_axi_s1_o40, fabric_fpga_arburst_axi_s1_o1, fabric_fpga_arburst_axi_s1_o2, fabric_fpga_arcache_axi_s1_o1, fabric_fpga_arcache_axi_s1_o2, fabric_fpga_arcache_axi_s1_o3, fabric_fpga_arcache_axi_s1_o4, fabric_fpga_arid_axi_s1_o1, fabric_fpga_arid_axi_s1_o2, fabric_fpga_arid_axi_s1_o3, fabric_fpga_arid_axi_s1_o4, fabric_fpga_arid_axi_s1_o5, fabric_fpga_arid_axi_s1_o6
-, fabric_fpga_arid_axi_s1_o7, fabric_fpga_arid_axi_s1_o8, fabric_fpga_arid_axi_s1_o9, fabric_fpga_arid_axi_s1_o10, fabric_fpga_arid_axi_s1_o11, fabric_fpga_arid_axi_s1_o12, fabric_fpga_arlen_axi_s1_o1, fabric_fpga_arlen_axi_s1_o2, fabric_fpga_arlen_axi_s1_o3, fabric_fpga_arlen_axi_s1_o4, fabric_fpga_arlen_axi_s1_o5, fabric_fpga_arlen_axi_s1_o6, fabric_fpga_arlen_axi_s1_o7, fabric_fpga_arlen_axi_s1_o8, fabric_fpga_arlock_axi_s1_o, fabric_fpga_arprot_axi_s1_o1, fabric_fpga_arprot_axi_s1_o2, fabric_fpga_arprot_axi_s1_o3, fabric_fpga_arqos_axi_s1_o1, fabric_fpga_arqos_axi_s1_o2, fabric_fpga_arqos_axi_s1_o3
-, fabric_fpga_arqos_axi_s1_o4, fabric_fpga_arregion_axi_s1_o1, fabric_fpga_arregion_axi_s1_o2, fabric_fpga_arregion_axi_s1_o3, fabric_fpga_arregion_axi_s1_o4, fabric_fpga_arsize_axi_s1_o1, fabric_fpga_arsize_axi_s1_o2, fabric_fpga_arsize_axi_s1_o3, fabric_fpga_arvalid_axi_s1_o, fabric_fpga_awaddr_axi_s1_o1, fabric_fpga_awaddr_axi_s1_o2, fabric_fpga_awaddr_axi_s1_o3, fabric_fpga_awaddr_axi_s1_o4, fabric_fpga_awaddr_axi_s1_o5, fabric_fpga_awaddr_axi_s1_o6, fabric_fpga_awaddr_axi_s1_o7, fabric_fpga_awaddr_axi_s1_o8, fabric_fpga_awaddr_axi_s1_o9, fabric_fpga_awaddr_axi_s1_o10, fabric_fpga_awaddr_axi_s1_o11, fabric_fpga_awaddr_axi_s1_o12
-, fabric_fpga_awaddr_axi_s1_o13, fabric_fpga_awaddr_axi_s1_o14, fabric_fpga_awaddr_axi_s1_o15, fabric_fpga_awaddr_axi_s1_o16, fabric_fpga_awaddr_axi_s1_o17, fabric_fpga_awaddr_axi_s1_o18, fabric_fpga_awaddr_axi_s1_o19, fabric_fpga_awaddr_axi_s1_o20, fabric_fpga_awaddr_axi_s1_o21, fabric_fpga_awaddr_axi_s1_o22, fabric_fpga_awaddr_axi_s1_o23, fabric_fpga_awaddr_axi_s1_o24, fabric_fpga_awaddr_axi_s1_o25, fabric_fpga_awaddr_axi_s1_o26, fabric_fpga_awaddr_axi_s1_o27, fabric_fpga_awaddr_axi_s1_o28, fabric_fpga_awaddr_axi_s1_o29, fabric_fpga_awaddr_axi_s1_o30, fabric_fpga_awaddr_axi_s1_o31, fabric_fpga_awaddr_axi_s1_o32, fabric_fpga_awaddr_axi_s1_o33
-, fabric_fpga_awaddr_axi_s1_o34, fabric_fpga_awaddr_axi_s1_o35, fabric_fpga_awaddr_axi_s1_o36, fabric_fpga_awaddr_axi_s1_o37, fabric_fpga_awaddr_axi_s1_o38, fabric_fpga_awaddr_axi_s1_o39, fabric_fpga_awaddr_axi_s1_o40, fabric_fpga_awburst_axi_s1_o1, fabric_fpga_awburst_axi_s1_o2, fabric_fpga_awcache_axi_s1_o1, fabric_fpga_awcache_axi_s1_o2, fabric_fpga_awcache_axi_s1_o3, fabric_fpga_awcache_axi_s1_o4, fabric_fpga_awid_axi_s1_o1, fabric_fpga_awid_axi_s1_o2, fabric_fpga_awid_axi_s1_o3, fabric_fpga_awid_axi_s1_o4, fabric_fpga_awid_axi_s1_o5, fabric_fpga_awid_axi_s1_o6, fabric_fpga_awid_axi_s1_o7, fabric_fpga_awid_axi_s1_o8
-, fabric_fpga_awid_axi_s1_o9, fabric_fpga_awid_axi_s1_o10, fabric_fpga_awid_axi_s1_o11, fabric_fpga_awid_axi_s1_o12, fabric_fpga_awlen_axi_s1_o1, fabric_fpga_awlen_axi_s1_o2, fabric_fpga_awlen_axi_s1_o3, fabric_fpga_awlen_axi_s1_o4, fabric_fpga_awlen_axi_s1_o5, fabric_fpga_awlen_axi_s1_o6, fabric_fpga_awlen_axi_s1_o7, fabric_fpga_awlen_axi_s1_o8, fabric_fpga_awlock_axi_s1_o, fabric_fpga_awprot_axi_s1_o1, fabric_fpga_awprot_axi_s1_o2, fabric_fpga_awprot_axi_s1_o3, fabric_fpga_awqos_axi_s1_o1, fabric_fpga_awqos_axi_s1_o2, fabric_fpga_awqos_axi_s1_o3, fabric_fpga_awqos_axi_s1_o4, fabric_fpga_awregion_axi_s1_o1
-, fabric_fpga_awregion_axi_s1_o2, fabric_fpga_awregion_axi_s1_o3, fabric_fpga_awregion_axi_s1_o4, fabric_fpga_awsize_axi_s1_o1, fabric_fpga_awsize_axi_s1_o2, fabric_fpga_awsize_axi_s1_o3, fabric_fpga_bready_axi_s1_o, fabric_fpga_rready_axi_s1_o, fabric_fpga_wdata_axi_s1_o1, fabric_fpga_wdata_axi_s1_o2, fabric_fpga_wdata_axi_s1_o3, fabric_fpga_wdata_axi_s1_o4, fabric_fpga_wdata_axi_s1_o5, fabric_fpga_wdata_axi_s1_o6, fabric_fpga_wdata_axi_s1_o7, fabric_fpga_wdata_axi_s1_o8, fabric_fpga_wdata_axi_s1_o9, fabric_fpga_wdata_axi_s1_o10, fabric_fpga_wdata_axi_s1_o11, fabric_fpga_wdata_axi_s1_o12, fabric_fpga_wdata_axi_s1_o13
-, fabric_fpga_wdata_axi_s1_o14, fabric_fpga_wdata_axi_s1_o15, fabric_fpga_wdata_axi_s1_o16, fabric_fpga_wdata_axi_s1_o17, fabric_fpga_wdata_axi_s1_o18, fabric_fpga_wdata_axi_s1_o19, fabric_fpga_wdata_axi_s1_o20, fabric_fpga_wdata_axi_s1_o21, fabric_fpga_wdata_axi_s1_o22, fabric_fpga_wdata_axi_s1_o23, fabric_fpga_wdata_axi_s1_o24, fabric_fpga_wdata_axi_s1_o25, fabric_fpga_wdata_axi_s1_o26, fabric_fpga_wdata_axi_s1_o27, fabric_fpga_wdata_axi_s1_o28, fabric_fpga_wdata_axi_s1_o29, fabric_fpga_wdata_axi_s1_o30, fabric_fpga_wdata_axi_s1_o31, fabric_fpga_wdata_axi_s1_o32, fabric_fpga_wdata_axi_s1_o33, fabric_fpga_wdata_axi_s1_o34
-, fabric_fpga_wdata_axi_s1_o35, fabric_fpga_wdata_axi_s1_o36, fabric_fpga_wdata_axi_s1_o37, fabric_fpga_wdata_axi_s1_o38, fabric_fpga_wdata_axi_s1_o39, fabric_fpga_wdata_axi_s1_o40, fabric_fpga_wdata_axi_s1_o41, fabric_fpga_wdata_axi_s1_o42, fabric_fpga_wdata_axi_s1_o43, fabric_fpga_wdata_axi_s1_o44, fabric_fpga_wdata_axi_s1_o45, fabric_fpga_wdata_axi_s1_o46, fabric_fpga_wdata_axi_s1_o47, fabric_fpga_wdata_axi_s1_o48, fabric_fpga_wdata_axi_s1_o49, fabric_fpga_wdata_axi_s1_o50, fabric_fpga_wdata_axi_s1_o51, fabric_fpga_wdata_axi_s1_o52, fabric_fpga_wdata_axi_s1_o53, fabric_fpga_wdata_axi_s1_o54, fabric_fpga_wdata_axi_s1_o55
-, fabric_fpga_wdata_axi_s1_o56, fabric_fpga_wdata_axi_s1_o57, fabric_fpga_wdata_axi_s1_o58, fabric_fpga_wdata_axi_s1_o59, fabric_fpga_wdata_axi_s1_o60, fabric_fpga_wdata_axi_s1_o61, fabric_fpga_wdata_axi_s1_o62, fabric_fpga_wdata_axi_s1_o63, fabric_fpga_wdata_axi_s1_o64, fabric_fpga_wdata_axi_s1_o65, fabric_fpga_wdata_axi_s1_o66, fabric_fpga_wdata_axi_s1_o67, fabric_fpga_wdata_axi_s1_o68, fabric_fpga_wdata_axi_s1_o69, fabric_fpga_wdata_axi_s1_o70, fabric_fpga_wdata_axi_s1_o71, fabric_fpga_wdata_axi_s1_o72, fabric_fpga_wdata_axi_s1_o73, fabric_fpga_wdata_axi_s1_o74, fabric_fpga_wdata_axi_s1_o75, fabric_fpga_wdata_axi_s1_o76
-, fabric_fpga_wdata_axi_s1_o77, fabric_fpga_wdata_axi_s1_o78, fabric_fpga_wdata_axi_s1_o79, fabric_fpga_wdata_axi_s1_o80, fabric_fpga_wdata_axi_s1_o81, fabric_fpga_wdata_axi_s1_o82, fabric_fpga_wdata_axi_s1_o83, fabric_fpga_wdata_axi_s1_o84, fabric_fpga_wdata_axi_s1_o85, fabric_fpga_wdata_axi_s1_o86, fabric_fpga_wdata_axi_s1_o87, fabric_fpga_wdata_axi_s1_o88, fabric_fpga_wdata_axi_s1_o89, fabric_fpga_wdata_axi_s1_o90, fabric_fpga_wdata_axi_s1_o91, fabric_fpga_wdata_axi_s1_o92, fabric_fpga_wdata_axi_s1_o93, fabric_fpga_wdata_axi_s1_o94, fabric_fpga_wdata_axi_s1_o95, fabric_fpga_wdata_axi_s1_o96, fabric_fpga_wdata_axi_s1_o97
-, fabric_fpga_wdata_axi_s1_o98, fabric_fpga_wdata_axi_s1_o99, fabric_fpga_wdata_axi_s1_o100, fabric_fpga_wdata_axi_s1_o101, fabric_fpga_wdata_axi_s1_o102, fabric_fpga_wdata_axi_s1_o103, fabric_fpga_wdata_axi_s1_o104, fabric_fpga_wdata_axi_s1_o105, fabric_fpga_wdata_axi_s1_o106, fabric_fpga_wdata_axi_s1_o107, fabric_fpga_wdata_axi_s1_o108, fabric_fpga_wdata_axi_s1_o109, fabric_fpga_wdata_axi_s1_o110, fabric_fpga_wdata_axi_s1_o111, fabric_fpga_wdata_axi_s1_o112, fabric_fpga_wdata_axi_s1_o113, fabric_fpga_wdata_axi_s1_o114, fabric_fpga_wdata_axi_s1_o115, fabric_fpga_wdata_axi_s1_o116, fabric_fpga_wdata_axi_s1_o117, fabric_fpga_wdata_axi_s1_o118
-, fabric_fpga_wdata_axi_s1_o119, fabric_fpga_wdata_axi_s1_o120, fabric_fpga_wdata_axi_s1_o121, fabric_fpga_wdata_axi_s1_o122, fabric_fpga_wdata_axi_s1_o123, fabric_fpga_wdata_axi_s1_o124, fabric_fpga_wdata_axi_s1_o125, fabric_fpga_wdata_axi_s1_o126, fabric_fpga_wdata_axi_s1_o127, fabric_fpga_wdata_axi_s1_o128, fabric_fpga_wlast_axi_s1_o, fabric_fpga_wstrb_axi_s1_o1, fabric_fpga_wstrb_axi_s1_o2, fabric_fpga_wstrb_axi_s1_o3, fabric_fpga_wstrb_axi_s1_o4, fabric_fpga_wstrb_axi_s1_o5, fabric_fpga_wstrb_axi_s1_o6, fabric_fpga_wstrb_axi_s1_o7, fabric_fpga_wstrb_axi_s1_o8, fabric_fpga_wstrb_axi_s1_o9, fabric_fpga_wstrb_axi_s1_o10
-, fabric_fpga_wstrb_axi_s1_o11, fabric_fpga_wstrb_axi_s1_o12, fabric_fpga_wstrb_axi_s1_o13, fabric_fpga_wstrb_axi_s1_o14, fabric_fpga_wstrb_axi_s1_o15, fabric_fpga_wstrb_axi_s1_o16, fabric_fpga_wvalid_axi_s1_o, fabric_fpga_awvalid_axi_s1_o, fabric_fpga_arready_axi_s1_i, fabric_fpga_awready_axi_s1_i, fabric_fpga_bid_axi_s1_i1, fabric_fpga_bid_axi_s1_i2, fabric_fpga_bid_axi_s1_i3, fabric_fpga_bid_axi_s1_i4, fabric_fpga_bid_axi_s1_i5, fabric_fpga_bid_axi_s1_i6, fabric_fpga_bid_axi_s1_i7, fabric_fpga_bid_axi_s1_i8, fabric_fpga_bid_axi_s1_i9, fabric_fpga_bid_axi_s1_i10, fabric_fpga_bid_axi_s1_i11
-, fabric_fpga_bid_axi_s1_i12, fabric_fpga_bresp_axi_s1_i1, fabric_fpga_bresp_axi_s1_i2, fabric_fpga_bvalid_axi_s1_i, fabric_fpga_rdata_axi_s1_i1, fabric_fpga_rdata_axi_s1_i2, fabric_fpga_rdata_axi_s1_i3, fabric_fpga_rdata_axi_s1_i4, fabric_fpga_rdata_axi_s1_i5, fabric_fpga_rdata_axi_s1_i6, fabric_fpga_rdata_axi_s1_i7, fabric_fpga_rdata_axi_s1_i8, fabric_fpga_rdata_axi_s1_i9, fabric_fpga_rdata_axi_s1_i10, fabric_fpga_rdata_axi_s1_i11, fabric_fpga_rdata_axi_s1_i12, fabric_fpga_rdata_axi_s1_i13, fabric_fpga_rdata_axi_s1_i14, fabric_fpga_rdata_axi_s1_i15, fabric_fpga_rdata_axi_s1_i16, fabric_fpga_rdata_axi_s1_i17
-, fabric_fpga_rdata_axi_s1_i18, fabric_fpga_rdata_axi_s1_i19, fabric_fpga_rdata_axi_s1_i20, fabric_fpga_rdata_axi_s1_i21, fabric_fpga_rdata_axi_s1_i22, fabric_fpga_rdata_axi_s1_i23, fabric_fpga_rdata_axi_s1_i24, fabric_fpga_rdata_axi_s1_i25, fabric_fpga_rdata_axi_s1_i26, fabric_fpga_rdata_axi_s1_i27, fabric_fpga_rdata_axi_s1_i28, fabric_fpga_rdata_axi_s1_i29, fabric_fpga_rdata_axi_s1_i30, fabric_fpga_rdata_axi_s1_i31, fabric_fpga_rdata_axi_s1_i32, fabric_fpga_rdata_axi_s1_i33, fabric_fpga_rdata_axi_s1_i34, fabric_fpga_rdata_axi_s1_i35, fabric_fpga_rdata_axi_s1_i36, fabric_fpga_rdata_axi_s1_i37, fabric_fpga_rdata_axi_s1_i38
-, fabric_fpga_rdata_axi_s1_i39, fabric_fpga_rdata_axi_s1_i40, fabric_fpga_rdata_axi_s1_i41, fabric_fpga_rdata_axi_s1_i42, fabric_fpga_rdata_axi_s1_i43, fabric_fpga_rdata_axi_s1_i44, fabric_fpga_rdata_axi_s1_i45, fabric_fpga_rdata_axi_s1_i46, fabric_fpga_rdata_axi_s1_i47, fabric_fpga_rdata_axi_s1_i48, fabric_fpga_rdata_axi_s1_i49, fabric_fpga_rdata_axi_s1_i50, fabric_fpga_rdata_axi_s1_i51, fabric_fpga_rdata_axi_s1_i52, fabric_fpga_rdata_axi_s1_i53, fabric_fpga_rdata_axi_s1_i54, fabric_fpga_rdata_axi_s1_i55, fabric_fpga_rdata_axi_s1_i56, fabric_fpga_rdata_axi_s1_i57, fabric_fpga_rdata_axi_s1_i58, fabric_fpga_rdata_axi_s1_i59
-, fabric_fpga_rdata_axi_s1_i60, fabric_fpga_rdata_axi_s1_i61, fabric_fpga_rdata_axi_s1_i62, fabric_fpga_rdata_axi_s1_i63, fabric_fpga_rdata_axi_s1_i64, fabric_fpga_rdata_axi_s1_i65, fabric_fpga_rdata_axi_s1_i66, fabric_fpga_rdata_axi_s1_i67, fabric_fpga_rdata_axi_s1_i68, fabric_fpga_rdata_axi_s1_i69, fabric_fpga_rdata_axi_s1_i70, fabric_fpga_rdata_axi_s1_i71, fabric_fpga_rdata_axi_s1_i72, fabric_fpga_rdata_axi_s1_i73, fabric_fpga_rdata_axi_s1_i74, fabric_fpga_rdata_axi_s1_i75, fabric_fpga_rdata_axi_s1_i76, fabric_fpga_rdata_axi_s1_i77, fabric_fpga_rdata_axi_s1_i78, fabric_fpga_rdata_axi_s1_i79, fabric_fpga_rdata_axi_s1_i80
-, fabric_fpga_rdata_axi_s1_i81, fabric_fpga_rdata_axi_s1_i82, fabric_fpga_rdata_axi_s1_i83, fabric_fpga_rdata_axi_s1_i84, fabric_fpga_rdata_axi_s1_i85, fabric_fpga_rdata_axi_s1_i86, fabric_fpga_rdata_axi_s1_i87, fabric_fpga_rdata_axi_s1_i88, fabric_fpga_rdata_axi_s1_i89, fabric_fpga_rdata_axi_s1_i90, fabric_fpga_rdata_axi_s1_i91, fabric_fpga_rdata_axi_s1_i92, fabric_fpga_rdata_axi_s1_i93, fabric_fpga_rdata_axi_s1_i94, fabric_fpga_rdata_axi_s1_i95, fabric_fpga_rdata_axi_s1_i96, fabric_fpga_rdata_axi_s1_i97, fabric_fpga_rdata_axi_s1_i98, fabric_fpga_rdata_axi_s1_i99, fabric_fpga_rdata_axi_s1_i100, fabric_fpga_rdata_axi_s1_i101
-, fabric_fpga_rdata_axi_s1_i102, fabric_fpga_rdata_axi_s1_i103, fabric_fpga_rdata_axi_s1_i104, fabric_fpga_rdata_axi_s1_i105, fabric_fpga_rdata_axi_s1_i106, fabric_fpga_rdata_axi_s1_i107, fabric_fpga_rdata_axi_s1_i108, fabric_fpga_rdata_axi_s1_i109, fabric_fpga_rdata_axi_s1_i110, fabric_fpga_rdata_axi_s1_i111, fabric_fpga_rdata_axi_s1_i112, fabric_fpga_rdata_axi_s1_i113, fabric_fpga_rdata_axi_s1_i114, fabric_fpga_rdata_axi_s1_i115, fabric_fpga_rdata_axi_s1_i116, fabric_fpga_rdata_axi_s1_i117, fabric_fpga_rdata_axi_s1_i118, fabric_fpga_rdata_axi_s1_i119, fabric_fpga_rdata_axi_s1_i120, fabric_fpga_rdata_axi_s1_i121, fabric_fpga_rdata_axi_s1_i122
-, fabric_fpga_rdata_axi_s1_i123, fabric_fpga_rdata_axi_s1_i124, fabric_fpga_rdata_axi_s1_i125, fabric_fpga_rdata_axi_s1_i126, fabric_fpga_rdata_axi_s1_i127, fabric_fpga_rdata_axi_s1_i128, fabric_fpga_rid_axi_s1_i1, fabric_fpga_rid_axi_s1_i2, fabric_fpga_rid_axi_s1_i3, fabric_fpga_rid_axi_s1_i4, fabric_fpga_rid_axi_s1_i5, fabric_fpga_rid_axi_s1_i6, fabric_fpga_rid_axi_s1_i7, fabric_fpga_rid_axi_s1_i8, fabric_fpga_rid_axi_s1_i9, fabric_fpga_rid_axi_s1_i10, fabric_fpga_rid_axi_s1_i11, fabric_fpga_rid_axi_s1_i12, fabric_fpga_rlast_axi_s1_i, fabric_fpga_rresp_axi_s1_i1, fabric_fpga_rresp_axi_s1_i2
-, fabric_fpga_rvalid_axi_s1_i, fabric_fpga_wready_axi_s1_i, fabric_fpga_araddr_axi_s2_o1, fabric_fpga_araddr_axi_s2_o2, fabric_fpga_araddr_axi_s2_o3, fabric_fpga_araddr_axi_s2_o4, fabric_fpga_araddr_axi_s2_o5, fabric_fpga_araddr_axi_s2_o6, fabric_fpga_araddr_axi_s2_o7, fabric_fpga_araddr_axi_s2_o8, fabric_fpga_araddr_axi_s2_o9, fabric_fpga_araddr_axi_s2_o10, fabric_fpga_araddr_axi_s2_o11, fabric_fpga_araddr_axi_s2_o12, fabric_fpga_araddr_axi_s2_o13, fabric_fpga_araddr_axi_s2_o14, fabric_fpga_araddr_axi_s2_o15, fabric_fpga_araddr_axi_s2_o16, fabric_fpga_araddr_axi_s2_o17, fabric_fpga_araddr_axi_s2_o18, fabric_fpga_araddr_axi_s2_o19
-, fabric_fpga_araddr_axi_s2_o20, fabric_fpga_araddr_axi_s2_o21, fabric_fpga_araddr_axi_s2_o22, fabric_fpga_araddr_axi_s2_o23, fabric_fpga_araddr_axi_s2_o24, fabric_fpga_araddr_axi_s2_o25, fabric_fpga_araddr_axi_s2_o26, fabric_fpga_araddr_axi_s2_o27, fabric_fpga_araddr_axi_s2_o28, fabric_fpga_araddr_axi_s2_o29, fabric_fpga_araddr_axi_s2_o30, fabric_fpga_araddr_axi_s2_o31, fabric_fpga_araddr_axi_s2_o32, fabric_fpga_araddr_axi_s2_o33, fabric_fpga_araddr_axi_s2_o34, fabric_fpga_araddr_axi_s2_o35, fabric_fpga_araddr_axi_s2_o36, fabric_fpga_araddr_axi_s2_o37, fabric_fpga_araddr_axi_s2_o38, fabric_fpga_araddr_axi_s2_o39, fabric_fpga_araddr_axi_s2_o40
-, fabric_fpga_arburst_axi_s2_o1, fabric_fpga_arburst_axi_s2_o2, fabric_fpga_arcache_axi_s2_o1, fabric_fpga_arcache_axi_s2_o2, fabric_fpga_arcache_axi_s2_o3, fabric_fpga_arcache_axi_s2_o4, fabric_fpga_arid_axi_s2_o1, fabric_fpga_arid_axi_s2_o2, fabric_fpga_arid_axi_s2_o3, fabric_fpga_arid_axi_s2_o4, fabric_fpga_arid_axi_s2_o5, fabric_fpga_arid_axi_s2_o6, fabric_fpga_arid_axi_s2_o7, fabric_fpga_arid_axi_s2_o8, fabric_fpga_arid_axi_s2_o9, fabric_fpga_arid_axi_s2_o10, fabric_fpga_arid_axi_s2_o11, fabric_fpga_arid_axi_s2_o12, fabric_fpga_arlen_axi_s2_o1, fabric_fpga_arlen_axi_s2_o2, fabric_fpga_arlen_axi_s2_o3
-, fabric_fpga_arlen_axi_s2_o4, fabric_fpga_arlen_axi_s2_o5, fabric_fpga_arlen_axi_s2_o6, fabric_fpga_arlen_axi_s2_o7, fabric_fpga_arlen_axi_s2_o8, fabric_fpga_arlock_axi_s2_o, fabric_fpga_arprot_axi_s2_o1, fabric_fpga_arprot_axi_s2_o2, fabric_fpga_arprot_axi_s2_o3, fabric_fpga_arqos_axi_s2_o1, fabric_fpga_arqos_axi_s2_o2, fabric_fpga_arqos_axi_s2_o3, fabric_fpga_arqos_axi_s2_o4, fabric_fpga_arregion_axi_s2_o1, fabric_fpga_arregion_axi_s2_o2, fabric_fpga_arregion_axi_s2_o3, fabric_fpga_arregion_axi_s2_o4, fabric_fpga_arsize_axi_s2_o1, fabric_fpga_arsize_axi_s2_o2, fabric_fpga_arsize_axi_s2_o3, fabric_fpga_arvalid_axi_s2_o
-, fabric_fpga_awaddr_axi_s2_o1, fabric_fpga_awaddr_axi_s2_o2, fabric_fpga_awaddr_axi_s2_o3, fabric_fpga_awaddr_axi_s2_o4, fabric_fpga_awaddr_axi_s2_o5, fabric_fpga_awaddr_axi_s2_o6, fabric_fpga_awaddr_axi_s2_o7, fabric_fpga_awaddr_axi_s2_o8, fabric_fpga_awaddr_axi_s2_o9, fabric_fpga_awaddr_axi_s2_o10, fabric_fpga_awaddr_axi_s2_o11, fabric_fpga_awaddr_axi_s2_o12, fabric_fpga_awaddr_axi_s2_o13, fabric_fpga_awaddr_axi_s2_o14, fabric_fpga_awaddr_axi_s2_o15, fabric_fpga_awaddr_axi_s2_o16, fabric_fpga_awaddr_axi_s2_o17, fabric_fpga_awaddr_axi_s2_o18, fabric_fpga_awaddr_axi_s2_o19, fabric_fpga_awaddr_axi_s2_o20, fabric_fpga_awaddr_axi_s2_o21
-, fabric_fpga_awaddr_axi_s2_o22, fabric_fpga_awaddr_axi_s2_o23, fabric_fpga_awaddr_axi_s2_o24, fabric_fpga_awaddr_axi_s2_o25, fabric_fpga_awaddr_axi_s2_o26, fabric_fpga_awaddr_axi_s2_o27, fabric_fpga_awaddr_axi_s2_o28, fabric_fpga_awaddr_axi_s2_o29, fabric_fpga_awaddr_axi_s2_o30, fabric_fpga_awaddr_axi_s2_o31, fabric_fpga_awaddr_axi_s2_o32, fabric_fpga_awaddr_axi_s2_o33, fabric_fpga_awaddr_axi_s2_o34, fabric_fpga_awaddr_axi_s2_o35, fabric_fpga_awaddr_axi_s2_o36, fabric_fpga_awaddr_axi_s2_o37, fabric_fpga_awaddr_axi_s2_o38, fabric_fpga_awaddr_axi_s2_o39, fabric_fpga_awaddr_axi_s2_o40, fabric_fpga_awburst_axi_s2_o1, fabric_fpga_awburst_axi_s2_o2
-, fabric_fpga_awcache_axi_s2_o1, fabric_fpga_awcache_axi_s2_o2, fabric_fpga_awcache_axi_s2_o3, fabric_fpga_awcache_axi_s2_o4, fabric_fpga_awid_axi_s2_o1, fabric_fpga_awid_axi_s2_o2, fabric_fpga_awid_axi_s2_o3, fabric_fpga_awid_axi_s2_o4, fabric_fpga_awid_axi_s2_o5, fabric_fpga_awid_axi_s2_o6, fabric_fpga_awid_axi_s2_o7, fabric_fpga_awid_axi_s2_o8, fabric_fpga_awid_axi_s2_o9, fabric_fpga_awid_axi_s2_o10, fabric_fpga_awid_axi_s2_o11, fabric_fpga_awid_axi_s2_o12, fabric_fpga_awlen_axi_s2_o1, fabric_fpga_awlen_axi_s2_o2, fabric_fpga_awlen_axi_s2_o3, fabric_fpga_awlen_axi_s2_o4, fabric_fpga_awlen_axi_s2_o5
-, fabric_fpga_awlen_axi_s2_o6, fabric_fpga_awlen_axi_s2_o7, fabric_fpga_awlen_axi_s2_o8, fabric_fpga_awlock_axi_s2_o, fabric_fpga_awprot_axi_s2_o1, fabric_fpga_awprot_axi_s2_o2, fabric_fpga_awprot_axi_s2_o3, fabric_fpga_awqos_axi_s2_o1, fabric_fpga_awqos_axi_s2_o2, fabric_fpga_awqos_axi_s2_o3, fabric_fpga_awqos_axi_s2_o4, fabric_fpga_awregion_axi_s2_o1, fabric_fpga_awregion_axi_s2_o2, fabric_fpga_awregion_axi_s2_o3, fabric_fpga_awregion_axi_s2_o4, fabric_fpga_awsize_axi_s2_o1, fabric_fpga_awsize_axi_s2_o2, fabric_fpga_awsize_axi_s2_o3, fabric_fpga_bready_axi_s2_o, fabric_fpga_rready_axi_s2_o, fabric_fpga_wdata_axi_s2_o1
-, fabric_fpga_wdata_axi_s2_o2, fabric_fpga_wdata_axi_s2_o3, fabric_fpga_wdata_axi_s2_o4, fabric_fpga_wdata_axi_s2_o5, fabric_fpga_wdata_axi_s2_o6, fabric_fpga_wdata_axi_s2_o7, fabric_fpga_wdata_axi_s2_o8, fabric_fpga_wdata_axi_s2_o9, fabric_fpga_wdata_axi_s2_o10, fabric_fpga_wdata_axi_s2_o11, fabric_fpga_wdata_axi_s2_o12, fabric_fpga_wdata_axi_s2_o13, fabric_fpga_wdata_axi_s2_o14, fabric_fpga_wdata_axi_s2_o15, fabric_fpga_wdata_axi_s2_o16, fabric_fpga_wdata_axi_s2_o17, fabric_fpga_wdata_axi_s2_o18, fabric_fpga_wdata_axi_s2_o19, fabric_fpga_wdata_axi_s2_o20, fabric_fpga_wdata_axi_s2_o21, fabric_fpga_wdata_axi_s2_o22
-, fabric_fpga_wdata_axi_s2_o23, fabric_fpga_wdata_axi_s2_o24, fabric_fpga_wdata_axi_s2_o25, fabric_fpga_wdata_axi_s2_o26, fabric_fpga_wdata_axi_s2_o27, fabric_fpga_wdata_axi_s2_o28, fabric_fpga_wdata_axi_s2_o29, fabric_fpga_wdata_axi_s2_o30, fabric_fpga_wdata_axi_s2_o31, fabric_fpga_wdata_axi_s2_o32, fabric_fpga_wdata_axi_s2_o33, fabric_fpga_wdata_axi_s2_o34, fabric_fpga_wdata_axi_s2_o35, fabric_fpga_wdata_axi_s2_o36, fabric_fpga_wdata_axi_s2_o37, fabric_fpga_wdata_axi_s2_o38, fabric_fpga_wdata_axi_s2_o39, fabric_fpga_wdata_axi_s2_o40, fabric_fpga_wdata_axi_s2_o41, fabric_fpga_wdata_axi_s2_o42, fabric_fpga_wdata_axi_s2_o43
-, fabric_fpga_wdata_axi_s2_o44, fabric_fpga_wdata_axi_s2_o45, fabric_fpga_wdata_axi_s2_o46, fabric_fpga_wdata_axi_s2_o47, fabric_fpga_wdata_axi_s2_o48, fabric_fpga_wdata_axi_s2_o49, fabric_fpga_wdata_axi_s2_o50, fabric_fpga_wdata_axi_s2_o51, fabric_fpga_wdata_axi_s2_o52, fabric_fpga_wdata_axi_s2_o53, fabric_fpga_wdata_axi_s2_o54, fabric_fpga_wdata_axi_s2_o55, fabric_fpga_wdata_axi_s2_o56, fabric_fpga_wdata_axi_s2_o57, fabric_fpga_wdata_axi_s2_o58, fabric_fpga_wdata_axi_s2_o59, fabric_fpga_wdata_axi_s2_o60, fabric_fpga_wdata_axi_s2_o61, fabric_fpga_wdata_axi_s2_o62, fabric_fpga_wdata_axi_s2_o63, fabric_fpga_wdata_axi_s2_o64
-, fabric_fpga_wdata_axi_s2_o65, fabric_fpga_wdata_axi_s2_o66, fabric_fpga_wdata_axi_s2_o67, fabric_fpga_wdata_axi_s2_o68, fabric_fpga_wdata_axi_s2_o69, fabric_fpga_wdata_axi_s2_o70, fabric_fpga_wdata_axi_s2_o71, fabric_fpga_wdata_axi_s2_o72, fabric_fpga_wdata_axi_s2_o73, fabric_fpga_wdata_axi_s2_o74, fabric_fpga_wdata_axi_s2_o75, fabric_fpga_wdata_axi_s2_o76, fabric_fpga_wdata_axi_s2_o77, fabric_fpga_wdata_axi_s2_o78, fabric_fpga_wdata_axi_s2_o79, fabric_fpga_wdata_axi_s2_o80, fabric_fpga_wdata_axi_s2_o81, fabric_fpga_wdata_axi_s2_o82, fabric_fpga_wdata_axi_s2_o83, fabric_fpga_wdata_axi_s2_o84, fabric_fpga_wdata_axi_s2_o85
-, fabric_fpga_wdata_axi_s2_o86, fabric_fpga_wdata_axi_s2_o87, fabric_fpga_wdata_axi_s2_o88, fabric_fpga_wdata_axi_s2_o89, fabric_fpga_wdata_axi_s2_o90, fabric_fpga_wdata_axi_s2_o91, fabric_fpga_wdata_axi_s2_o92, fabric_fpga_wdata_axi_s2_o93, fabric_fpga_wdata_axi_s2_o94, fabric_fpga_wdata_axi_s2_o95, fabric_fpga_wdata_axi_s2_o96, fabric_fpga_wdata_axi_s2_o97, fabric_fpga_wdata_axi_s2_o98, fabric_fpga_wdata_axi_s2_o99, fabric_fpga_wdata_axi_s2_o100, fabric_fpga_wdata_axi_s2_o101, fabric_fpga_wdata_axi_s2_o102, fabric_fpga_wdata_axi_s2_o103, fabric_fpga_wdata_axi_s2_o104, fabric_fpga_wdata_axi_s2_o105, fabric_fpga_wdata_axi_s2_o106
-, fabric_fpga_wdata_axi_s2_o107, fabric_fpga_wdata_axi_s2_o108, fabric_fpga_wdata_axi_s2_o109, fabric_fpga_wdata_axi_s2_o110, fabric_fpga_wdata_axi_s2_o111, fabric_fpga_wdata_axi_s2_o112, fabric_fpga_wdata_axi_s2_o113, fabric_fpga_wdata_axi_s2_o114, fabric_fpga_wdata_axi_s2_o115, fabric_fpga_wdata_axi_s2_o116, fabric_fpga_wdata_axi_s2_o117, fabric_fpga_wdata_axi_s2_o118, fabric_fpga_wdata_axi_s2_o119, fabric_fpga_wdata_axi_s2_o120, fabric_fpga_wdata_axi_s2_o121, fabric_fpga_wdata_axi_s2_o122, fabric_fpga_wdata_axi_s2_o123, fabric_fpga_wdata_axi_s2_o124, fabric_fpga_wdata_axi_s2_o125, fabric_fpga_wdata_axi_s2_o126, fabric_fpga_wdata_axi_s2_o127
-, fabric_fpga_wdata_axi_s2_o128, fabric_fpga_wlast_axi_s2_o, fabric_fpga_wstrb_axi_s2_o1, fabric_fpga_wstrb_axi_s2_o2, fabric_fpga_wstrb_axi_s2_o3, fabric_fpga_wstrb_axi_s2_o4, fabric_fpga_wstrb_axi_s2_o5, fabric_fpga_wstrb_axi_s2_o6, fabric_fpga_wstrb_axi_s2_o7, fabric_fpga_wstrb_axi_s2_o8, fabric_fpga_wstrb_axi_s2_o9, fabric_fpga_wstrb_axi_s2_o10, fabric_fpga_wstrb_axi_s2_o11, fabric_fpga_wstrb_axi_s2_o12, fabric_fpga_wstrb_axi_s2_o13, fabric_fpga_wstrb_axi_s2_o14, fabric_fpga_wstrb_axi_s2_o15, fabric_fpga_wstrb_axi_s2_o16, fabric_fpga_wvalid_axi_s2_o, fabric_fpga_awvalid_axi_s2_o, fabric_fpga_arready_axi_s2_i
-, fabric_fpga_awready_axi_s2_i, fabric_fpga_bid_axi_s2_i1, fabric_fpga_bid_axi_s2_i2, fabric_fpga_bid_axi_s2_i3, fabric_fpga_bid_axi_s2_i4, fabric_fpga_bid_axi_s2_i5, fabric_fpga_bid_axi_s2_i6, fabric_fpga_bid_axi_s2_i7, fabric_fpga_bid_axi_s2_i8, fabric_fpga_bid_axi_s2_i9, fabric_fpga_bid_axi_s2_i10, fabric_fpga_bid_axi_s2_i11, fabric_fpga_bid_axi_s2_i12, fabric_fpga_bresp_axi_s2_i1, fabric_fpga_bresp_axi_s2_i2, fabric_fpga_bvalid_axi_s2_i, fabric_fpga_rdata_axi_s2_i1, fabric_fpga_rdata_axi_s2_i2, fabric_fpga_rdata_axi_s2_i3, fabric_fpga_rdata_axi_s2_i4, fabric_fpga_rdata_axi_s2_i5
-, fabric_fpga_rdata_axi_s2_i6, fabric_fpga_rdata_axi_s2_i7, fabric_fpga_rdata_axi_s2_i8, fabric_fpga_rdata_axi_s2_i9, fabric_fpga_rdata_axi_s2_i10, fabric_fpga_rdata_axi_s2_i11, fabric_fpga_rdata_axi_s2_i12, fabric_fpga_rdata_axi_s2_i13, fabric_fpga_rdata_axi_s2_i14, fabric_fpga_rdata_axi_s2_i15, fabric_fpga_rdata_axi_s2_i16, fabric_fpga_rdata_axi_s2_i17, fabric_fpga_rdata_axi_s2_i18, fabric_fpga_rdata_axi_s2_i19, fabric_fpga_rdata_axi_s2_i20, fabric_fpga_rdata_axi_s2_i21, fabric_fpga_rdata_axi_s2_i22, fabric_fpga_rdata_axi_s2_i23, fabric_fpga_rdata_axi_s2_i24, fabric_fpga_rdata_axi_s2_i25, fabric_fpga_rdata_axi_s2_i26
-, fabric_fpga_rdata_axi_s2_i27, fabric_fpga_rdata_axi_s2_i28, fabric_fpga_rdata_axi_s2_i29, fabric_fpga_rdata_axi_s2_i30, fabric_fpga_rdata_axi_s2_i31, fabric_fpga_rdata_axi_s2_i32, fabric_fpga_rdata_axi_s2_i33, fabric_fpga_rdata_axi_s2_i34, fabric_fpga_rdata_axi_s2_i35, fabric_fpga_rdata_axi_s2_i36, fabric_fpga_rdata_axi_s2_i37, fabric_fpga_rdata_axi_s2_i38, fabric_fpga_rdata_axi_s2_i39, fabric_fpga_rdata_axi_s2_i40, fabric_fpga_rdata_axi_s2_i41, fabric_fpga_rdata_axi_s2_i42, fabric_fpga_rdata_axi_s2_i43, fabric_fpga_rdata_axi_s2_i44, fabric_fpga_rdata_axi_s2_i45, fabric_fpga_rdata_axi_s2_i46, fabric_fpga_rdata_axi_s2_i47
-, fabric_fpga_rdata_axi_s2_i48, fabric_fpga_rdata_axi_s2_i49, fabric_fpga_rdata_axi_s2_i50, fabric_fpga_rdata_axi_s2_i51, fabric_fpga_rdata_axi_s2_i52, fabric_fpga_rdata_axi_s2_i53, fabric_fpga_rdata_axi_s2_i54, fabric_fpga_rdata_axi_s2_i55, fabric_fpga_rdata_axi_s2_i56, fabric_fpga_rdata_axi_s2_i57, fabric_fpga_rdata_axi_s2_i58, fabric_fpga_rdata_axi_s2_i59, fabric_fpga_rdata_axi_s2_i60, fabric_fpga_rdata_axi_s2_i61, fabric_fpga_rdata_axi_s2_i62, fabric_fpga_rdata_axi_s2_i63, fabric_fpga_rdata_axi_s2_i64, fabric_fpga_rdata_axi_s2_i65, fabric_fpga_rdata_axi_s2_i66, fabric_fpga_rdata_axi_s2_i67, fabric_fpga_rdata_axi_s2_i68
-, fabric_fpga_rdata_axi_s2_i69, fabric_fpga_rdata_axi_s2_i70, fabric_fpga_rdata_axi_s2_i71, fabric_fpga_rdata_axi_s2_i72, fabric_fpga_rdata_axi_s2_i73, fabric_fpga_rdata_axi_s2_i74, fabric_fpga_rdata_axi_s2_i75, fabric_fpga_rdata_axi_s2_i76, fabric_fpga_rdata_axi_s2_i77, fabric_fpga_rdata_axi_s2_i78, fabric_fpga_rdata_axi_s2_i79, fabric_fpga_rdata_axi_s2_i80, fabric_fpga_rdata_axi_s2_i81, fabric_fpga_rdata_axi_s2_i82, fabric_fpga_rdata_axi_s2_i83, fabric_fpga_rdata_axi_s2_i84, fabric_fpga_rdata_axi_s2_i85, fabric_fpga_rdata_axi_s2_i86, fabric_fpga_rdata_axi_s2_i87, fabric_fpga_rdata_axi_s2_i88, fabric_fpga_rdata_axi_s2_i89
-, fabric_fpga_rdata_axi_s2_i90, fabric_fpga_rdata_axi_s2_i91, fabric_fpga_rdata_axi_s2_i92, fabric_fpga_rdata_axi_s2_i93, fabric_fpga_rdata_axi_s2_i94, fabric_fpga_rdata_axi_s2_i95, fabric_fpga_rdata_axi_s2_i96, fabric_fpga_rdata_axi_s2_i97, fabric_fpga_rdata_axi_s2_i98, fabric_fpga_rdata_axi_s2_i99, fabric_fpga_rdata_axi_s2_i100, fabric_fpga_rdata_axi_s2_i101, fabric_fpga_rdata_axi_s2_i102, fabric_fpga_rdata_axi_s2_i103, fabric_fpga_rdata_axi_s2_i104, fabric_fpga_rdata_axi_s2_i105, fabric_fpga_rdata_axi_s2_i106, fabric_fpga_rdata_axi_s2_i107, fabric_fpga_rdata_axi_s2_i108, fabric_fpga_rdata_axi_s2_i109, fabric_fpga_rdata_axi_s2_i110
-, fabric_fpga_rdata_axi_s2_i111, fabric_fpga_rdata_axi_s2_i112, fabric_fpga_rdata_axi_s2_i113, fabric_fpga_rdata_axi_s2_i114, fabric_fpga_rdata_axi_s2_i115, fabric_fpga_rdata_axi_s2_i116, fabric_fpga_rdata_axi_s2_i117, fabric_fpga_rdata_axi_s2_i118, fabric_fpga_rdata_axi_s2_i119, fabric_fpga_rdata_axi_s2_i120, fabric_fpga_rdata_axi_s2_i121, fabric_fpga_rdata_axi_s2_i122, fabric_fpga_rdata_axi_s2_i123, fabric_fpga_rdata_axi_s2_i124, fabric_fpga_rdata_axi_s2_i125, fabric_fpga_rdata_axi_s2_i126, fabric_fpga_rdata_axi_s2_i127, fabric_fpga_rdata_axi_s2_i128, fabric_fpga_rid_axi_s2_i1, fabric_fpga_rid_axi_s2_i2, fabric_fpga_rid_axi_s2_i3
-, fabric_fpga_rid_axi_s2_i4, fabric_fpga_rid_axi_s2_i5, fabric_fpga_rid_axi_s2_i6, fabric_fpga_rid_axi_s2_i7, fabric_fpga_rid_axi_s2_i8, fabric_fpga_rid_axi_s2_i9, fabric_fpga_rid_axi_s2_i10, fabric_fpga_rid_axi_s2_i11, fabric_fpga_rid_axi_s2_i12, fabric_fpga_rlast_axi_s2_i, fabric_fpga_rresp_axi_s2_i1, fabric_fpga_rresp_axi_s2_i2, fabric_fpga_rvalid_axi_s2_i, fabric_fpga_wready_axi_s2_i, fabric_fpga_arready_axi_m1_o, fabric_fpga_awready_axi_m1_o, fabric_fpga_bid_axi_m1_o1, fabric_fpga_bid_axi_m1_o2, fabric_fpga_bid_axi_m1_o3, fabric_fpga_bid_axi_m1_o4, fabric_fpga_bid_axi_m1_o5
-, fabric_fpga_bresp_axi_m1_o1, fabric_fpga_bresp_axi_m1_o2, fabric_fpga_bvalid_axi_m1_o, fabric_fpga_dma_ack_m1_o1, fabric_fpga_dma_ack_m1_o2, fabric_fpga_dma_ack_m1_o3, fabric_fpga_dma_ack_m1_o4, fabric_fpga_dma_ack_m1_o5, fabric_fpga_dma_ack_m1_o6, fabric_fpga_dma_finish_m1_o1, fabric_fpga_dma_finish_m1_o2, fabric_fpga_dma_finish_m1_o3, fabric_fpga_dma_finish_m1_o4, fabric_fpga_dma_finish_m1_o5, fabric_fpga_dma_finish_m1_o6, fabric_fpga_rdata_axi_m1_o1, fabric_fpga_rdata_axi_m1_o2, fabric_fpga_rdata_axi_m1_o3, fabric_fpga_rdata_axi_m1_o4, fabric_fpga_rdata_axi_m1_o5, fabric_fpga_rdata_axi_m1_o6
-, fabric_fpga_rdata_axi_m1_o7, fabric_fpga_rdata_axi_m1_o8, fabric_fpga_rdata_axi_m1_o9, fabric_fpga_rdata_axi_m1_o10, fabric_fpga_rdata_axi_m1_o11, fabric_fpga_rdata_axi_m1_o12, fabric_fpga_rdata_axi_m1_o13, fabric_fpga_rdata_axi_m1_o14, fabric_fpga_rdata_axi_m1_o15, fabric_fpga_rdata_axi_m1_o16, fabric_fpga_rdata_axi_m1_o17, fabric_fpga_rdata_axi_m1_o18, fabric_fpga_rdata_axi_m1_o19, fabric_fpga_rdata_axi_m1_o20, fabric_fpga_rdata_axi_m1_o21, fabric_fpga_rdata_axi_m1_o22, fabric_fpga_rdata_axi_m1_o23, fabric_fpga_rdata_axi_m1_o24, fabric_fpga_rdata_axi_m1_o25, fabric_fpga_rdata_axi_m1_o26, fabric_fpga_rdata_axi_m1_o27
-, fabric_fpga_rdata_axi_m1_o28, fabric_fpga_rdata_axi_m1_o29, fabric_fpga_rdata_axi_m1_o30, fabric_fpga_rdata_axi_m1_o31, fabric_fpga_rdata_axi_m1_o32, fabric_fpga_rdata_axi_m1_o33, fabric_fpga_rdata_axi_m1_o34, fabric_fpga_rdata_axi_m1_o35, fabric_fpga_rdata_axi_m1_o36, fabric_fpga_rdata_axi_m1_o37, fabric_fpga_rdata_axi_m1_o38, fabric_fpga_rdata_axi_m1_o39, fabric_fpga_rdata_axi_m1_o40, fabric_fpga_rdata_axi_m1_o41, fabric_fpga_rdata_axi_m1_o42, fabric_fpga_rdata_axi_m1_o43, fabric_fpga_rdata_axi_m1_o44, fabric_fpga_rdata_axi_m1_o45, fabric_fpga_rdata_axi_m1_o46, fabric_fpga_rdata_axi_m1_o47, fabric_fpga_rdata_axi_m1_o48
-, fabric_fpga_rdata_axi_m1_o49, fabric_fpga_rdata_axi_m1_o50, fabric_fpga_rdata_axi_m1_o51, fabric_fpga_rdata_axi_m1_o52, fabric_fpga_rdata_axi_m1_o53, fabric_fpga_rdata_axi_m1_o54, fabric_fpga_rdata_axi_m1_o55, fabric_fpga_rdata_axi_m1_o56, fabric_fpga_rdata_axi_m1_o57, fabric_fpga_rdata_axi_m1_o58, fabric_fpga_rdata_axi_m1_o59, fabric_fpga_rdata_axi_m1_o60, fabric_fpga_rdata_axi_m1_o61, fabric_fpga_rdata_axi_m1_o62, fabric_fpga_rdata_axi_m1_o63, fabric_fpga_rdata_axi_m1_o64, fabric_fpga_rdata_axi_m1_o65, fabric_fpga_rdata_axi_m1_o66, fabric_fpga_rdata_axi_m1_o67, fabric_fpga_rdata_axi_m1_o68, fabric_fpga_rdata_axi_m1_o69
-, fabric_fpga_rdata_axi_m1_o70, fabric_fpga_rdata_axi_m1_o71, fabric_fpga_rdata_axi_m1_o72, fabric_fpga_rdata_axi_m1_o73, fabric_fpga_rdata_axi_m1_o74, fabric_fpga_rdata_axi_m1_o75, fabric_fpga_rdata_axi_m1_o76, fabric_fpga_rdata_axi_m1_o77, fabric_fpga_rdata_axi_m1_o78, fabric_fpga_rdata_axi_m1_o79, fabric_fpga_rdata_axi_m1_o80, fabric_fpga_rdata_axi_m1_o81, fabric_fpga_rdata_axi_m1_o82, fabric_fpga_rdata_axi_m1_o83, fabric_fpga_rdata_axi_m1_o84, fabric_fpga_rdata_axi_m1_o85, fabric_fpga_rdata_axi_m1_o86, fabric_fpga_rdata_axi_m1_o87, fabric_fpga_rdata_axi_m1_o88, fabric_fpga_rdata_axi_m1_o89, fabric_fpga_rdata_axi_m1_o90
-, fabric_fpga_rdata_axi_m1_o91, fabric_fpga_rdata_axi_m1_o92, fabric_fpga_rdata_axi_m1_o93, fabric_fpga_rdata_axi_m1_o94, fabric_fpga_rdata_axi_m1_o95, fabric_fpga_rdata_axi_m1_o96, fabric_fpga_rdata_axi_m1_o97, fabric_fpga_rdata_axi_m1_o98, fabric_fpga_rdata_axi_m1_o99, fabric_fpga_rdata_axi_m1_o100, fabric_fpga_rdata_axi_m1_o101, fabric_fpga_rdata_axi_m1_o102, fabric_fpga_rdata_axi_m1_o103, fabric_fpga_rdata_axi_m1_o104, fabric_fpga_rdata_axi_m1_o105, fabric_fpga_rdata_axi_m1_o106, fabric_fpga_rdata_axi_m1_o107, fabric_fpga_rdata_axi_m1_o108, fabric_fpga_rdata_axi_m1_o109, fabric_fpga_rdata_axi_m1_o110, fabric_fpga_rdata_axi_m1_o111
-, fabric_fpga_rdata_axi_m1_o112, fabric_fpga_rdata_axi_m1_o113, fabric_fpga_rdata_axi_m1_o114, fabric_fpga_rdata_axi_m1_o115, fabric_fpga_rdata_axi_m1_o116, fabric_fpga_rdata_axi_m1_o117, fabric_fpga_rdata_axi_m1_o118, fabric_fpga_rdata_axi_m1_o119, fabric_fpga_rdata_axi_m1_o120, fabric_fpga_rdata_axi_m1_o121, fabric_fpga_rdata_axi_m1_o122, fabric_fpga_rdata_axi_m1_o123, fabric_fpga_rdata_axi_m1_o124, fabric_fpga_rdata_axi_m1_o125, fabric_fpga_rdata_axi_m1_o126, fabric_fpga_rdata_axi_m1_o127, fabric_fpga_rdata_axi_m1_o128, fabric_fpga_rid_axi_m1_o1, fabric_fpga_rid_axi_m1_o2, fabric_fpga_rid_axi_m1_o3, fabric_fpga_rid_axi_m1_o4
-, fabric_fpga_rid_axi_m1_o5, fabric_fpga_rlast_axi_m1_o, fabric_fpga_rresp_axi_m1_o1, fabric_fpga_rresp_axi_m1_o2, fabric_fpga_rvalid_axi_m1_o, fabric_fpga_wready_axi_m1_o, fabric_fpga_araddr_axi_m1_i1, fabric_fpga_araddr_axi_m1_i2, fabric_fpga_araddr_axi_m1_i3, fabric_fpga_araddr_axi_m1_i4, fabric_fpga_araddr_axi_m1_i5, fabric_fpga_araddr_axi_m1_i6, fabric_fpga_araddr_axi_m1_i7, fabric_fpga_araddr_axi_m1_i8, fabric_fpga_araddr_axi_m1_i9, fabric_fpga_araddr_axi_m1_i10, fabric_fpga_araddr_axi_m1_i11, fabric_fpga_araddr_axi_m1_i12, fabric_fpga_araddr_axi_m1_i13, fabric_fpga_araddr_axi_m1_i14, fabric_fpga_araddr_axi_m1_i15
-, fabric_fpga_araddr_axi_m1_i16, fabric_fpga_araddr_axi_m1_i17, fabric_fpga_araddr_axi_m1_i18, fabric_fpga_araddr_axi_m1_i19, fabric_fpga_araddr_axi_m1_i20, fabric_fpga_araddr_axi_m1_i21, fabric_fpga_araddr_axi_m1_i22, fabric_fpga_araddr_axi_m1_i23, fabric_fpga_araddr_axi_m1_i24, fabric_fpga_araddr_axi_m1_i25, fabric_fpga_araddr_axi_m1_i26, fabric_fpga_araddr_axi_m1_i27, fabric_fpga_araddr_axi_m1_i28, fabric_fpga_araddr_axi_m1_i29, fabric_fpga_araddr_axi_m1_i30, fabric_fpga_araddr_axi_m1_i31, fabric_fpga_araddr_axi_m1_i32, fabric_fpga_araddr_axi_m1_i33, fabric_fpga_araddr_axi_m1_i34, fabric_fpga_araddr_axi_m1_i35, fabric_fpga_araddr_axi_m1_i36
-, fabric_fpga_araddr_axi_m1_i37, fabric_fpga_araddr_axi_m1_i38, fabric_fpga_araddr_axi_m1_i39, fabric_fpga_araddr_axi_m1_i40, fabric_fpga_arburst_axi_m1_i1, fabric_fpga_arburst_axi_m1_i2, fabric_fpga_arcache_axi_m1_i1, fabric_fpga_arcache_axi_m1_i2, fabric_fpga_arcache_axi_m1_i3, fabric_fpga_arcache_axi_m1_i4, fabric_fpga_arid_axi_m1_i1, fabric_fpga_arid_axi_m1_i2, fabric_fpga_arid_axi_m1_i3, fabric_fpga_arid_axi_m1_i4, fabric_fpga_arid_axi_m1_i5, fabric_fpga_arlen_axi_m1_i1, fabric_fpga_arlen_axi_m1_i2, fabric_fpga_arlen_axi_m1_i3, fabric_fpga_arlen_axi_m1_i4, fabric_fpga_arlen_axi_m1_i5, fabric_fpga_arlen_axi_m1_i6
-, fabric_fpga_arlen_axi_m1_i7, fabric_fpga_arlen_axi_m1_i8, fabric_fpga_arlock_axi_m1_i, fabric_fpga_arprot_axi_m1_i1, fabric_fpga_arprot_axi_m1_i2, fabric_fpga_arprot_axi_m1_i3, fabric_fpga_arqos_axi_m1_i1, fabric_fpga_arqos_axi_m1_i2, fabric_fpga_arqos_axi_m1_i3, fabric_fpga_arqos_axi_m1_i4, fabric_fpga_arsize_axi_m1_i1, fabric_fpga_arsize_axi_m1_i2, fabric_fpga_arsize_axi_m1_i3, fabric_fpga_arvalid_axi_m1_i, fabric_fpga_awaddr_axi_m1_i1, fabric_fpga_awaddr_axi_m1_i2, fabric_fpga_awaddr_axi_m1_i3, fabric_fpga_awaddr_axi_m1_i4, fabric_fpga_awaddr_axi_m1_i5, fabric_fpga_awaddr_axi_m1_i6, fabric_fpga_awaddr_axi_m1_i7
-, fabric_fpga_awaddr_axi_m1_i8, fabric_fpga_awaddr_axi_m1_i9, fabric_fpga_awaddr_axi_m1_i10, fabric_fpga_awaddr_axi_m1_i11, fabric_fpga_awaddr_axi_m1_i12, fabric_fpga_awaddr_axi_m1_i13, fabric_fpga_awaddr_axi_m1_i14, fabric_fpga_awaddr_axi_m1_i15, fabric_fpga_awaddr_axi_m1_i16, fabric_fpga_awaddr_axi_m1_i17, fabric_fpga_awaddr_axi_m1_i18, fabric_fpga_awaddr_axi_m1_i19, fabric_fpga_awaddr_axi_m1_i20, fabric_fpga_awaddr_axi_m1_i21, fabric_fpga_awaddr_axi_m1_i22, fabric_fpga_awaddr_axi_m1_i23, fabric_fpga_awaddr_axi_m1_i24, fabric_fpga_awaddr_axi_m1_i25, fabric_fpga_awaddr_axi_m1_i26, fabric_fpga_awaddr_axi_m1_i27, fabric_fpga_awaddr_axi_m1_i28
-, fabric_fpga_awaddr_axi_m1_i29, fabric_fpga_awaddr_axi_m1_i30, fabric_fpga_awaddr_axi_m1_i31, fabric_fpga_awaddr_axi_m1_i32, fabric_fpga_awaddr_axi_m1_i33, fabric_fpga_awaddr_axi_m1_i34, fabric_fpga_awaddr_axi_m1_i35, fabric_fpga_awaddr_axi_m1_i36, fabric_fpga_awaddr_axi_m1_i37, fabric_fpga_awaddr_axi_m1_i38, fabric_fpga_awaddr_axi_m1_i39, fabric_fpga_awaddr_axi_m1_i40, fabric_fpga_awburst_axi_m1_i1, fabric_fpga_awburst_axi_m1_i2, fabric_fpga_awcache_axi_m1_i1, fabric_fpga_awcache_axi_m1_i2, fabric_fpga_awcache_axi_m1_i3, fabric_fpga_awcache_axi_m1_i4, fabric_fpga_awid_axi_m1_i1, fabric_fpga_awid_axi_m1_i2, fabric_fpga_awid_axi_m1_i3
-, fabric_fpga_awid_axi_m1_i4, fabric_fpga_awid_axi_m1_i5, fabric_fpga_awlen_axi_m1_i1, fabric_fpga_awlen_axi_m1_i2, fabric_fpga_awlen_axi_m1_i3, fabric_fpga_awlen_axi_m1_i4, fabric_fpga_awlen_axi_m1_i5, fabric_fpga_awlen_axi_m1_i6, fabric_fpga_awlen_axi_m1_i7, fabric_fpga_awlen_axi_m1_i8, fabric_fpga_awlock_axi_m1_i, fabric_fpga_awprot_axi_m1_i1, fabric_fpga_awprot_axi_m1_i2, fabric_fpga_awprot_axi_m1_i3, fabric_fpga_awqos_axi_m1_i1, fabric_fpga_awqos_axi_m1_i2, fabric_fpga_awqos_axi_m1_i3, fabric_fpga_awqos_axi_m1_i4, fabric_fpga_awsize_axi_m1_i1, fabric_fpga_awsize_axi_m1_i2, fabric_fpga_awsize_axi_m1_i3
-, fabric_fpga_awvalid_axi_m1_i, fabric_fpga_bready_axi_m1_i, fabric_fpga_dma_last_m1_i1, fabric_fpga_dma_last_m1_i2, fabric_fpga_dma_last_m1_i3, fabric_fpga_dma_last_m1_i4, fabric_fpga_dma_last_m1_i5, fabric_fpga_dma_last_m1_i6, fabric_fpga_dma_req_m1_i1, fabric_fpga_dma_req_m1_i2, fabric_fpga_dma_req_m1_i3, fabric_fpga_dma_req_m1_i4, fabric_fpga_dma_req_m1_i5, fabric_fpga_dma_req_m1_i6, fabric_fpga_dma_single_m1_i1, fabric_fpga_dma_single_m1_i2, fabric_fpga_dma_single_m1_i3, fabric_fpga_dma_single_m1_i4, fabric_fpga_dma_single_m1_i5, fabric_fpga_dma_single_m1_i6, fabric_fpga_rready_axi_m1_i
-, fabric_fpga_wdata_axi_m1_i1, fabric_fpga_wdata_axi_m1_i2, fabric_fpga_wdata_axi_m1_i3, fabric_fpga_wdata_axi_m1_i4, fabric_fpga_wdata_axi_m1_i5, fabric_fpga_wdata_axi_m1_i6, fabric_fpga_wdata_axi_m1_i7, fabric_fpga_wdata_axi_m1_i8, fabric_fpga_wdata_axi_m1_i9, fabric_fpga_wdata_axi_m1_i10, fabric_fpga_wdata_axi_m1_i11, fabric_fpga_wdata_axi_m1_i12, fabric_fpga_wdata_axi_m1_i13, fabric_fpga_wdata_axi_m1_i14, fabric_fpga_wdata_axi_m1_i15, fabric_fpga_wdata_axi_m1_i16, fabric_fpga_wdata_axi_m1_i17, fabric_fpga_wdata_axi_m1_i18, fabric_fpga_wdata_axi_m1_i19, fabric_fpga_wdata_axi_m1_i20, fabric_fpga_wdata_axi_m1_i21
-, fabric_fpga_wdata_axi_m1_i22, fabric_fpga_wdata_axi_m1_i23, fabric_fpga_wdata_axi_m1_i24, fabric_fpga_wdata_axi_m1_i25, fabric_fpga_wdata_axi_m1_i26, fabric_fpga_wdata_axi_m1_i27, fabric_fpga_wdata_axi_m1_i28, fabric_fpga_wdata_axi_m1_i29, fabric_fpga_wdata_axi_m1_i30, fabric_fpga_wdata_axi_m1_i31, fabric_fpga_wdata_axi_m1_i32, fabric_fpga_wdata_axi_m1_i33, fabric_fpga_wdata_axi_m1_i34, fabric_fpga_wdata_axi_m1_i35, fabric_fpga_wdata_axi_m1_i36, fabric_fpga_wdata_axi_m1_i37, fabric_fpga_wdata_axi_m1_i38, fabric_fpga_wdata_axi_m1_i39, fabric_fpga_wdata_axi_m1_i40, fabric_fpga_wdata_axi_m1_i41, fabric_fpga_wdata_axi_m1_i42
-, fabric_fpga_wdata_axi_m1_i43, fabric_fpga_wdata_axi_m1_i44, fabric_fpga_wdata_axi_m1_i45, fabric_fpga_wdata_axi_m1_i46, fabric_fpga_wdata_axi_m1_i47, fabric_fpga_wdata_axi_m1_i48, fabric_fpga_wdata_axi_m1_i49, fabric_fpga_wdata_axi_m1_i50, fabric_fpga_wdata_axi_m1_i51, fabric_fpga_wdata_axi_m1_i52, fabric_fpga_wdata_axi_m1_i53, fabric_fpga_wdata_axi_m1_i54, fabric_fpga_wdata_axi_m1_i55, fabric_fpga_wdata_axi_m1_i56, fabric_fpga_wdata_axi_m1_i57, fabric_fpga_wdata_axi_m1_i58, fabric_fpga_wdata_axi_m1_i59, fabric_fpga_wdata_axi_m1_i60, fabric_fpga_wdata_axi_m1_i61, fabric_fpga_wdata_axi_m1_i62, fabric_fpga_wdata_axi_m1_i63
-, fabric_fpga_wdata_axi_m1_i64, fabric_fpga_wdata_axi_m1_i65, fabric_fpga_wdata_axi_m1_i66, fabric_fpga_wdata_axi_m1_i67, fabric_fpga_wdata_axi_m1_i68, fabric_fpga_wdata_axi_m1_i69, fabric_fpga_wdata_axi_m1_i70, fabric_fpga_wdata_axi_m1_i71, fabric_fpga_wdata_axi_m1_i72, fabric_fpga_wdata_axi_m1_i73, fabric_fpga_wdata_axi_m1_i74, fabric_fpga_wdata_axi_m1_i75, fabric_fpga_wdata_axi_m1_i76, fabric_fpga_wdata_axi_m1_i77, fabric_fpga_wdata_axi_m1_i78, fabric_fpga_wdata_axi_m1_i79, fabric_fpga_wdata_axi_m1_i80, fabric_fpga_wdata_axi_m1_i81, fabric_fpga_wdata_axi_m1_i82, fabric_fpga_wdata_axi_m1_i83, fabric_fpga_wdata_axi_m1_i84
-, fabric_fpga_wdata_axi_m1_i85, fabric_fpga_wdata_axi_m1_i86, fabric_fpga_wdata_axi_m1_i87, fabric_fpga_wdata_axi_m1_i88, fabric_fpga_wdata_axi_m1_i89, fabric_fpga_wdata_axi_m1_i90, fabric_fpga_wdata_axi_m1_i91, fabric_fpga_wdata_axi_m1_i92, fabric_fpga_wdata_axi_m1_i93, fabric_fpga_wdata_axi_m1_i94, fabric_fpga_wdata_axi_m1_i95, fabric_fpga_wdata_axi_m1_i96, fabric_fpga_wdata_axi_m1_i97, fabric_fpga_wdata_axi_m1_i98, fabric_fpga_wdata_axi_m1_i99, fabric_fpga_wdata_axi_m1_i100, fabric_fpga_wdata_axi_m1_i101, fabric_fpga_wdata_axi_m1_i102, fabric_fpga_wdata_axi_m1_i103, fabric_fpga_wdata_axi_m1_i104, fabric_fpga_wdata_axi_m1_i105
-, fabric_fpga_wdata_axi_m1_i106, fabric_fpga_wdata_axi_m1_i107, fabric_fpga_wdata_axi_m1_i108, fabric_fpga_wdata_axi_m1_i109, fabric_fpga_wdata_axi_m1_i110, fabric_fpga_wdata_axi_m1_i111, fabric_fpga_wdata_axi_m1_i112, fabric_fpga_wdata_axi_m1_i113, fabric_fpga_wdata_axi_m1_i114, fabric_fpga_wdata_axi_m1_i115, fabric_fpga_wdata_axi_m1_i116, fabric_fpga_wdata_axi_m1_i117, fabric_fpga_wdata_axi_m1_i118, fabric_fpga_wdata_axi_m1_i119, fabric_fpga_wdata_axi_m1_i120, fabric_fpga_wdata_axi_m1_i121, fabric_fpga_wdata_axi_m1_i122, fabric_fpga_wdata_axi_m1_i123, fabric_fpga_wdata_axi_m1_i124, fabric_fpga_wdata_axi_m1_i125, fabric_fpga_wdata_axi_m1_i126
-, fabric_fpga_wdata_axi_m1_i127, fabric_fpga_wdata_axi_m1_i128, fabric_fpga_wlast_axi_m1_i, fabric_fpga_wstrb_axi_m1_i1, fabric_fpga_wstrb_axi_m1_i2, fabric_fpga_wstrb_axi_m1_i3, fabric_fpga_wstrb_axi_m1_i4, fabric_fpga_wstrb_axi_m1_i5, fabric_fpga_wstrb_axi_m1_i6, fabric_fpga_wstrb_axi_m1_i7, fabric_fpga_wstrb_axi_m1_i8, fabric_fpga_wstrb_axi_m1_i9, fabric_fpga_wstrb_axi_m1_i10, fabric_fpga_wstrb_axi_m1_i11, fabric_fpga_wstrb_axi_m1_i12, fabric_fpga_wstrb_axi_m1_i13, fabric_fpga_wstrb_axi_m1_i14, fabric_fpga_wstrb_axi_m1_i15, fabric_fpga_wstrb_axi_m1_i16, fabric_fpga_wvalid_axi_m1_i, fabric_fpga_arready_axi_m2_o
-, fabric_fpga_awready_axi_m2_o, fabric_fpga_bid_axi_m2_o1, fabric_fpga_bid_axi_m2_o2, fabric_fpga_bid_axi_m2_o3, fabric_fpga_bid_axi_m2_o4, fabric_fpga_bid_axi_m2_o5, fabric_fpga_bresp_axi_m2_o1, fabric_fpga_bresp_axi_m2_o2, fabric_fpga_bvalid_axi_m2_o, fabric_fpga_dma_ack_m2_o1, fabric_fpga_dma_ack_m2_o2, fabric_fpga_dma_ack_m2_o3, fabric_fpga_dma_ack_m2_o4, fabric_fpga_dma_ack_m2_o5, fabric_fpga_dma_ack_m2_o6, fabric_fpga_dma_finish_m2_o1, fabric_fpga_dma_finish_m2_o2, fabric_fpga_dma_finish_m2_o3, fabric_fpga_dma_finish_m2_o4, fabric_fpga_dma_finish_m2_o5, fabric_fpga_dma_finish_m2_o6
-, fabric_fpga_rdata_axi_m2_o1, fabric_fpga_rdata_axi_m2_o2, fabric_fpga_rdata_axi_m2_o3, fabric_fpga_rdata_axi_m2_o4, fabric_fpga_rdata_axi_m2_o5, fabric_fpga_rdata_axi_m2_o6, fabric_fpga_rdata_axi_m2_o7, fabric_fpga_rdata_axi_m2_o8, fabric_fpga_rdata_axi_m2_o9, fabric_fpga_rdata_axi_m2_o10, fabric_fpga_rdata_axi_m2_o11, fabric_fpga_rdata_axi_m2_o12, fabric_fpga_rdata_axi_m2_o13, fabric_fpga_rdata_axi_m2_o14, fabric_fpga_rdata_axi_m2_o15, fabric_fpga_rdata_axi_m2_o16, fabric_fpga_rdata_axi_m2_o17, fabric_fpga_rdata_axi_m2_o18, fabric_fpga_rdata_axi_m2_o19, fabric_fpga_rdata_axi_m2_o20, fabric_fpga_rdata_axi_m2_o21
-, fabric_fpga_rdata_axi_m2_o22, fabric_fpga_rdata_axi_m2_o23, fabric_fpga_rdata_axi_m2_o24, fabric_fpga_rdata_axi_m2_o25, fabric_fpga_rdata_axi_m2_o26, fabric_fpga_rdata_axi_m2_o27, fabric_fpga_rdata_axi_m2_o28, fabric_fpga_rdata_axi_m2_o29, fabric_fpga_rdata_axi_m2_o30, fabric_fpga_rdata_axi_m2_o31, fabric_fpga_rdata_axi_m2_o32, fabric_fpga_rdata_axi_m2_o33, fabric_fpga_rdata_axi_m2_o34, fabric_fpga_rdata_axi_m2_o35, fabric_fpga_rdata_axi_m2_o36, fabric_fpga_rdata_axi_m2_o37, fabric_fpga_rdata_axi_m2_o38, fabric_fpga_rdata_axi_m2_o39, fabric_fpga_rdata_axi_m2_o40, fabric_fpga_rdata_axi_m2_o41, fabric_fpga_rdata_axi_m2_o42
-, fabric_fpga_rdata_axi_m2_o43, fabric_fpga_rdata_axi_m2_o44, fabric_fpga_rdata_axi_m2_o45, fabric_fpga_rdata_axi_m2_o46, fabric_fpga_rdata_axi_m2_o47, fabric_fpga_rdata_axi_m2_o48, fabric_fpga_rdata_axi_m2_o49, fabric_fpga_rdata_axi_m2_o50, fabric_fpga_rdata_axi_m2_o51, fabric_fpga_rdata_axi_m2_o52, fabric_fpga_rdata_axi_m2_o53, fabric_fpga_rdata_axi_m2_o54, fabric_fpga_rdata_axi_m2_o55, fabric_fpga_rdata_axi_m2_o56, fabric_fpga_rdata_axi_m2_o57, fabric_fpga_rdata_axi_m2_o58, fabric_fpga_rdata_axi_m2_o59, fabric_fpga_rdata_axi_m2_o60, fabric_fpga_rdata_axi_m2_o61, fabric_fpga_rdata_axi_m2_o62, fabric_fpga_rdata_axi_m2_o63
-, fabric_fpga_rdata_axi_m2_o64, fabric_fpga_rdata_axi_m2_o65, fabric_fpga_rdata_axi_m2_o66, fabric_fpga_rdata_axi_m2_o67, fabric_fpga_rdata_axi_m2_o68, fabric_fpga_rdata_axi_m2_o69, fabric_fpga_rdata_axi_m2_o70, fabric_fpga_rdata_axi_m2_o71, fabric_fpga_rdata_axi_m2_o72, fabric_fpga_rdata_axi_m2_o73, fabric_fpga_rdata_axi_m2_o74, fabric_fpga_rdata_axi_m2_o75, fabric_fpga_rdata_axi_m2_o76, fabric_fpga_rdata_axi_m2_o77, fabric_fpga_rdata_axi_m2_o78, fabric_fpga_rdata_axi_m2_o79, fabric_fpga_rdata_axi_m2_o80, fabric_fpga_rdata_axi_m2_o81, fabric_fpga_rdata_axi_m2_o82, fabric_fpga_rdata_axi_m2_o83, fabric_fpga_rdata_axi_m2_o84
-, fabric_fpga_rdata_axi_m2_o85, fabric_fpga_rdata_axi_m2_o86, fabric_fpga_rdata_axi_m2_o87, fabric_fpga_rdata_axi_m2_o88, fabric_fpga_rdata_axi_m2_o89, fabric_fpga_rdata_axi_m2_o90, fabric_fpga_rdata_axi_m2_o91, fabric_fpga_rdata_axi_m2_o92, fabric_fpga_rdata_axi_m2_o93, fabric_fpga_rdata_axi_m2_o94, fabric_fpga_rdata_axi_m2_o95, fabric_fpga_rdata_axi_m2_o96, fabric_fpga_rdata_axi_m2_o97, fabric_fpga_rdata_axi_m2_o98, fabric_fpga_rdata_axi_m2_o99, fabric_fpga_rdata_axi_m2_o100, fabric_fpga_rdata_axi_m2_o101, fabric_fpga_rdata_axi_m2_o102, fabric_fpga_rdata_axi_m2_o103, fabric_fpga_rdata_axi_m2_o104, fabric_fpga_rdata_axi_m2_o105
-, fabric_fpga_rdata_axi_m2_o106, fabric_fpga_rdata_axi_m2_o107, fabric_fpga_rdata_axi_m2_o108, fabric_fpga_rdata_axi_m2_o109, fabric_fpga_rdata_axi_m2_o110, fabric_fpga_rdata_axi_m2_o111, fabric_fpga_rdata_axi_m2_o112, fabric_fpga_rdata_axi_m2_o113, fabric_fpga_rdata_axi_m2_o114, fabric_fpga_rdata_axi_m2_o115, fabric_fpga_rdata_axi_m2_o116, fabric_fpga_rdata_axi_m2_o117, fabric_fpga_rdata_axi_m2_o118, fabric_fpga_rdata_axi_m2_o119, fabric_fpga_rdata_axi_m2_o120, fabric_fpga_rdata_axi_m2_o121, fabric_fpga_rdata_axi_m2_o122, fabric_fpga_rdata_axi_m2_o123, fabric_fpga_rdata_axi_m2_o124, fabric_fpga_rdata_axi_m2_o125, fabric_fpga_rdata_axi_m2_o126
-, fabric_fpga_rdata_axi_m2_o127, fabric_fpga_rdata_axi_m2_o128, fabric_fpga_rid_axi_m2_o1, fabric_fpga_rid_axi_m2_o2, fabric_fpga_rid_axi_m2_o3, fabric_fpga_rid_axi_m2_o4, fabric_fpga_rid_axi_m2_o5, fabric_fpga_rlast_axi_m2_o, fabric_fpga_rresp_axi_m2_o1, fabric_fpga_rresp_axi_m2_o2, fabric_fpga_rvalid_axi_m2_o, fabric_fpga_wready_axi_m2_o, fabric_fpga_araddr_axi_m2_i1, fabric_fpga_araddr_axi_m2_i2, fabric_fpga_araddr_axi_m2_i3, fabric_fpga_araddr_axi_m2_i4, fabric_fpga_araddr_axi_m2_i5, fabric_fpga_araddr_axi_m2_i6, fabric_fpga_araddr_axi_m2_i7, fabric_fpga_araddr_axi_m2_i8, fabric_fpga_araddr_axi_m2_i9
-, fabric_fpga_araddr_axi_m2_i10, fabric_fpga_araddr_axi_m2_i11, fabric_fpga_araddr_axi_m2_i12, fabric_fpga_araddr_axi_m2_i13, fabric_fpga_araddr_axi_m2_i14, fabric_fpga_araddr_axi_m2_i15, fabric_fpga_araddr_axi_m2_i16, fabric_fpga_araddr_axi_m2_i17, fabric_fpga_araddr_axi_m2_i18, fabric_fpga_araddr_axi_m2_i19, fabric_fpga_araddr_axi_m2_i20, fabric_fpga_araddr_axi_m2_i21, fabric_fpga_araddr_axi_m2_i22, fabric_fpga_araddr_axi_m2_i23, fabric_fpga_araddr_axi_m2_i24, fabric_fpga_araddr_axi_m2_i25, fabric_fpga_araddr_axi_m2_i26, fabric_fpga_araddr_axi_m2_i27, fabric_fpga_araddr_axi_m2_i28, fabric_fpga_araddr_axi_m2_i29, fabric_fpga_araddr_axi_m2_i30
-, fabric_fpga_araddr_axi_m2_i31, fabric_fpga_araddr_axi_m2_i32, fabric_fpga_araddr_axi_m2_i33, fabric_fpga_araddr_axi_m2_i34, fabric_fpga_araddr_axi_m2_i35, fabric_fpga_araddr_axi_m2_i36, fabric_fpga_araddr_axi_m2_i37, fabric_fpga_araddr_axi_m2_i38, fabric_fpga_araddr_axi_m2_i39, fabric_fpga_araddr_axi_m2_i40, fabric_fpga_arburst_axi_m2_i1, fabric_fpga_arburst_axi_m2_i2, fabric_fpga_arcache_axi_m2_i1, fabric_fpga_arcache_axi_m2_i2, fabric_fpga_arcache_axi_m2_i3, fabric_fpga_arcache_axi_m2_i4, fabric_fpga_arid_axi_m2_i1, fabric_fpga_arid_axi_m2_i2, fabric_fpga_arid_axi_m2_i3, fabric_fpga_arid_axi_m2_i4, fabric_fpga_arid_axi_m2_i5
-, fabric_fpga_arlen_axi_m2_i1, fabric_fpga_arlen_axi_m2_i2, fabric_fpga_arlen_axi_m2_i3, fabric_fpga_arlen_axi_m2_i4, fabric_fpga_arlen_axi_m2_i5, fabric_fpga_arlen_axi_m2_i6, fabric_fpga_arlen_axi_m2_i7, fabric_fpga_arlen_axi_m2_i8, fabric_fpga_arlock_axi_m2_i, fabric_fpga_arprot_axi_m2_i1, fabric_fpga_arprot_axi_m2_i2, fabric_fpga_arprot_axi_m2_i3, fabric_fpga_arqos_axi_m2_i1, fabric_fpga_arqos_axi_m2_i2, fabric_fpga_arqos_axi_m2_i3, fabric_fpga_arqos_axi_m2_i4, fabric_fpga_arsize_axi_m2_i1, fabric_fpga_arsize_axi_m2_i2, fabric_fpga_arsize_axi_m2_i3, fabric_fpga_arvalid_axi_m2_i, fabric_fpga_awaddr_axi_m2_i1
-, fabric_fpga_awaddr_axi_m2_i2, fabric_fpga_awaddr_axi_m2_i3, fabric_fpga_awaddr_axi_m2_i4, fabric_fpga_awaddr_axi_m2_i5, fabric_fpga_awaddr_axi_m2_i6, fabric_fpga_awaddr_axi_m2_i7, fabric_fpga_awaddr_axi_m2_i8, fabric_fpga_awaddr_axi_m2_i9, fabric_fpga_awaddr_axi_m2_i10, fabric_fpga_awaddr_axi_m2_i11, fabric_fpga_awaddr_axi_m2_i12, fabric_fpga_awaddr_axi_m2_i13, fabric_fpga_awaddr_axi_m2_i14, fabric_fpga_awaddr_axi_m2_i15, fabric_fpga_awaddr_axi_m2_i16, fabric_fpga_awaddr_axi_m2_i17, fabric_fpga_awaddr_axi_m2_i18, fabric_fpga_awaddr_axi_m2_i19, fabric_fpga_awaddr_axi_m2_i20, fabric_fpga_awaddr_axi_m2_i21, fabric_fpga_awaddr_axi_m2_i22
-, fabric_fpga_awaddr_axi_m2_i23, fabric_fpga_awaddr_axi_m2_i24, fabric_fpga_awaddr_axi_m2_i25, fabric_fpga_awaddr_axi_m2_i26, fabric_fpga_awaddr_axi_m2_i27, fabric_fpga_awaddr_axi_m2_i28, fabric_fpga_awaddr_axi_m2_i29, fabric_fpga_awaddr_axi_m2_i30, fabric_fpga_awaddr_axi_m2_i31, fabric_fpga_awaddr_axi_m2_i32, fabric_fpga_awaddr_axi_m2_i33, fabric_fpga_awaddr_axi_m2_i34, fabric_fpga_awaddr_axi_m2_i35, fabric_fpga_awaddr_axi_m2_i36, fabric_fpga_awaddr_axi_m2_i37, fabric_fpga_awaddr_axi_m2_i38, fabric_fpga_awaddr_axi_m2_i39, fabric_fpga_awaddr_axi_m2_i40, fabric_fpga_awburst_axi_m2_i1, fabric_fpga_awburst_axi_m2_i2, fabric_fpga_awcache_axi_m2_i1
-, fabric_fpga_awcache_axi_m2_i2, fabric_fpga_awcache_axi_m2_i3, fabric_fpga_awcache_axi_m2_i4, fabric_fpga_awid_axi_m2_i1, fabric_fpga_awid_axi_m2_i2, fabric_fpga_awid_axi_m2_i3, fabric_fpga_awid_axi_m2_i4, fabric_fpga_awid_axi_m2_i5, fabric_fpga_awlen_axi_m2_i1, fabric_fpga_awlen_axi_m2_i2, fabric_fpga_awlen_axi_m2_i3, fabric_fpga_awlen_axi_m2_i4, fabric_fpga_awlen_axi_m2_i5, fabric_fpga_awlen_axi_m2_i6, fabric_fpga_awlen_axi_m2_i7, fabric_fpga_awlen_axi_m2_i8, fabric_fpga_awlock_axi_m2_i, fabric_fpga_awprot_axi_m2_i1, fabric_fpga_awprot_axi_m2_i2, fabric_fpga_awprot_axi_m2_i3, fabric_fpga_awqos_axi_m2_i1
-, fabric_fpga_awqos_axi_m2_i2, fabric_fpga_awqos_axi_m2_i3, fabric_fpga_awqos_axi_m2_i4, fabric_fpga_awsize_axi_m2_i1, fabric_fpga_awsize_axi_m2_i2, fabric_fpga_awsize_axi_m2_i3, fabric_fpga_awvalid_axi_m2_i, fabric_fpga_bready_axi_m2_i, fabric_fpga_dma_last_m2_i1, fabric_fpga_dma_last_m2_i2, fabric_fpga_dma_last_m2_i3, fabric_fpga_dma_last_m2_i4, fabric_fpga_dma_last_m2_i5, fabric_fpga_dma_last_m2_i6, fabric_fpga_dma_req_m2_i1, fabric_fpga_dma_req_m2_i2, fabric_fpga_dma_req_m2_i3, fabric_fpga_dma_req_m2_i4, fabric_fpga_dma_req_m2_i5, fabric_fpga_dma_req_m2_i6, fabric_fpga_dma_single_m2_i1
-, fabric_fpga_dma_single_m2_i2, fabric_fpga_dma_single_m2_i3, fabric_fpga_dma_single_m2_i4, fabric_fpga_dma_single_m2_i5, fabric_fpga_dma_single_m2_i6, fabric_fpga_rready_axi_m2_i, fabric_fpga_wdata_axi_m2_i1, fabric_fpga_wdata_axi_m2_i2, fabric_fpga_wdata_axi_m2_i3, fabric_fpga_wdata_axi_m2_i4, fabric_fpga_wdata_axi_m2_i5, fabric_fpga_wdata_axi_m2_i6, fabric_fpga_wdata_axi_m2_i7, fabric_fpga_wdata_axi_m2_i8, fabric_fpga_wdata_axi_m2_i9, fabric_fpga_wdata_axi_m2_i10, fabric_fpga_wdata_axi_m2_i11, fabric_fpga_wdata_axi_m2_i12, fabric_fpga_wdata_axi_m2_i13, fabric_fpga_wdata_axi_m2_i14, fabric_fpga_wdata_axi_m2_i15
-, fabric_fpga_wdata_axi_m2_i16, fabric_fpga_wdata_axi_m2_i17, fabric_fpga_wdata_axi_m2_i18, fabric_fpga_wdata_axi_m2_i19, fabric_fpga_wdata_axi_m2_i20, fabric_fpga_wdata_axi_m2_i21, fabric_fpga_wdata_axi_m2_i22, fabric_fpga_wdata_axi_m2_i23, fabric_fpga_wdata_axi_m2_i24, fabric_fpga_wdata_axi_m2_i25, fabric_fpga_wdata_axi_m2_i26, fabric_fpga_wdata_axi_m2_i27, fabric_fpga_wdata_axi_m2_i28, fabric_fpga_wdata_axi_m2_i29, fabric_fpga_wdata_axi_m2_i30, fabric_fpga_wdata_axi_m2_i31, fabric_fpga_wdata_axi_m2_i32, fabric_fpga_wdata_axi_m2_i33, fabric_fpga_wdata_axi_m2_i34, fabric_fpga_wdata_axi_m2_i35, fabric_fpga_wdata_axi_m2_i36
-, fabric_fpga_wdata_axi_m2_i37, fabric_fpga_wdata_axi_m2_i38, fabric_fpga_wdata_axi_m2_i39, fabric_fpga_wdata_axi_m2_i40, fabric_fpga_wdata_axi_m2_i41, fabric_fpga_wdata_axi_m2_i42, fabric_fpga_wdata_axi_m2_i43, fabric_fpga_wdata_axi_m2_i44, fabric_fpga_wdata_axi_m2_i45, fabric_fpga_wdata_axi_m2_i46, fabric_fpga_wdata_axi_m2_i47, fabric_fpga_wdata_axi_m2_i48, fabric_fpga_wdata_axi_m2_i49, fabric_fpga_wdata_axi_m2_i50, fabric_fpga_wdata_axi_m2_i51, fabric_fpga_wdata_axi_m2_i52, fabric_fpga_wdata_axi_m2_i53, fabric_fpga_wdata_axi_m2_i54, fabric_fpga_wdata_axi_m2_i55, fabric_fpga_wdata_axi_m2_i56, fabric_fpga_wdata_axi_m2_i57
-, fabric_fpga_wdata_axi_m2_i58, fabric_fpga_wdata_axi_m2_i59, fabric_fpga_wdata_axi_m2_i60, fabric_fpga_wdata_axi_m2_i61, fabric_fpga_wdata_axi_m2_i62, fabric_fpga_wdata_axi_m2_i63, fabric_fpga_wdata_axi_m2_i64, fabric_fpga_wdata_axi_m2_i65, fabric_fpga_wdata_axi_m2_i66, fabric_fpga_wdata_axi_m2_i67, fabric_fpga_wdata_axi_m2_i68, fabric_fpga_wdata_axi_m2_i69, fabric_fpga_wdata_axi_m2_i70, fabric_fpga_wdata_axi_m2_i71, fabric_fpga_wdata_axi_m2_i72, fabric_fpga_wdata_axi_m2_i73, fabric_fpga_wdata_axi_m2_i74, fabric_fpga_wdata_axi_m2_i75, fabric_fpga_wdata_axi_m2_i76, fabric_fpga_wdata_axi_m2_i77, fabric_fpga_wdata_axi_m2_i78
-, fabric_fpga_wdata_axi_m2_i79, fabric_fpga_wdata_axi_m2_i80, fabric_fpga_wdata_axi_m2_i81, fabric_fpga_wdata_axi_m2_i82, fabric_fpga_wdata_axi_m2_i83, fabric_fpga_wdata_axi_m2_i84, fabric_fpga_wdata_axi_m2_i85, fabric_fpga_wdata_axi_m2_i86, fabric_fpga_wdata_axi_m2_i87, fabric_fpga_wdata_axi_m2_i88, fabric_fpga_wdata_axi_m2_i89, fabric_fpga_wdata_axi_m2_i90, fabric_fpga_wdata_axi_m2_i91, fabric_fpga_wdata_axi_m2_i92, fabric_fpga_wdata_axi_m2_i93, fabric_fpga_wdata_axi_m2_i94, fabric_fpga_wdata_axi_m2_i95, fabric_fpga_wdata_axi_m2_i96, fabric_fpga_wdata_axi_m2_i97, fabric_fpga_wdata_axi_m2_i98, fabric_fpga_wdata_axi_m2_i99
-, fabric_fpga_wdata_axi_m2_i100, fabric_fpga_wdata_axi_m2_i101, fabric_fpga_wdata_axi_m2_i102, fabric_fpga_wdata_axi_m2_i103, fabric_fpga_wdata_axi_m2_i104, fabric_fpga_wdata_axi_m2_i105, fabric_fpga_wdata_axi_m2_i106, fabric_fpga_wdata_axi_m2_i107, fabric_fpga_wdata_axi_m2_i108, fabric_fpga_wdata_axi_m2_i109, fabric_fpga_wdata_axi_m2_i110, fabric_fpga_wdata_axi_m2_i111, fabric_fpga_wdata_axi_m2_i112, fabric_fpga_wdata_axi_m2_i113, fabric_fpga_wdata_axi_m2_i114, fabric_fpga_wdata_axi_m2_i115, fabric_fpga_wdata_axi_m2_i116, fabric_fpga_wdata_axi_m2_i117, fabric_fpga_wdata_axi_m2_i118, fabric_fpga_wdata_axi_m2_i119, fabric_fpga_wdata_axi_m2_i120
-, fabric_fpga_wdata_axi_m2_i121, fabric_fpga_wdata_axi_m2_i122, fabric_fpga_wdata_axi_m2_i123, fabric_fpga_wdata_axi_m2_i124, fabric_fpga_wdata_axi_m2_i125, fabric_fpga_wdata_axi_m2_i126, fabric_fpga_wdata_axi_m2_i127, fabric_fpga_wdata_axi_m2_i128, fabric_fpga_wlast_axi_m2_i, fabric_fpga_wstrb_axi_m2_i1, fabric_fpga_wstrb_axi_m2_i2, fabric_fpga_wstrb_axi_m2_i3, fabric_fpga_wstrb_axi_m2_i4, fabric_fpga_wstrb_axi_m2_i5, fabric_fpga_wstrb_axi_m2_i6, fabric_fpga_wstrb_axi_m2_i7, fabric_fpga_wstrb_axi_m2_i8, fabric_fpga_wstrb_axi_m2_i9, fabric_fpga_wstrb_axi_m2_i10, fabric_fpga_wstrb_axi_m2_i11, fabric_fpga_wstrb_axi_m2_i12
-, fabric_fpga_wstrb_axi_m2_i13, fabric_fpga_wstrb_axi_m2_i14, fabric_fpga_wstrb_axi_m2_i15, fabric_fpga_wstrb_axi_m2_i16, fabric_fpga_wvalid_axi_m2_i, fabric_fpga_ddr0_arready_o, fabric_fpga_ddr0_awready_o, fabric_fpga_ddr0_bid_o1, fabric_fpga_ddr0_bid_o2, fabric_fpga_ddr0_bid_o3, fabric_fpga_ddr0_bid_o4, fabric_fpga_ddr0_bid_o5, fabric_fpga_ddr0_bresp_o1, fabric_fpga_ddr0_bresp_o2, fabric_fpga_ddr0_bvalid_o, fabric_fpga_ddr0_rdata_o1, fabric_fpga_ddr0_rdata_o2, fabric_fpga_ddr0_rdata_o3, fabric_fpga_ddr0_rdata_o4, fabric_fpga_ddr0_rdata_o5, fabric_fpga_ddr0_rdata_o6
-, fabric_fpga_ddr0_rdata_o7, fabric_fpga_ddr0_rdata_o8, fabric_fpga_ddr0_rdata_o9, fabric_fpga_ddr0_rdata_o10, fabric_fpga_ddr0_rdata_o11, fabric_fpga_ddr0_rdata_o12, fabric_fpga_ddr0_rdata_o13, fabric_fpga_ddr0_rdata_o14, fabric_fpga_ddr0_rdata_o15, fabric_fpga_ddr0_rdata_o16, fabric_fpga_ddr0_rdata_o17, fabric_fpga_ddr0_rdata_o18, fabric_fpga_ddr0_rdata_o19, fabric_fpga_ddr0_rdata_o20, fabric_fpga_ddr0_rdata_o21, fabric_fpga_ddr0_rdata_o22, fabric_fpga_ddr0_rdata_o23, fabric_fpga_ddr0_rdata_o24, fabric_fpga_ddr0_rdata_o25, fabric_fpga_ddr0_rdata_o26, fabric_fpga_ddr0_rdata_o27
-, fabric_fpga_ddr0_rdata_o28, fabric_fpga_ddr0_rdata_o29, fabric_fpga_ddr0_rdata_o30, fabric_fpga_ddr0_rdata_o31, fabric_fpga_ddr0_rdata_o32, fabric_fpga_ddr0_rdata_o33, fabric_fpga_ddr0_rdata_o34, fabric_fpga_ddr0_rdata_o35, fabric_fpga_ddr0_rdata_o36, fabric_fpga_ddr0_rdata_o37, fabric_fpga_ddr0_rdata_o38, fabric_fpga_ddr0_rdata_o39, fabric_fpga_ddr0_rdata_o40, fabric_fpga_ddr0_rdata_o41, fabric_fpga_ddr0_rdata_o42, fabric_fpga_ddr0_rdata_o43, fabric_fpga_ddr0_rdata_o44, fabric_fpga_ddr0_rdata_o45, fabric_fpga_ddr0_rdata_o46, fabric_fpga_ddr0_rdata_o47, fabric_fpga_ddr0_rdata_o48
-, fabric_fpga_ddr0_rdata_o49, fabric_fpga_ddr0_rdata_o50, fabric_fpga_ddr0_rdata_o51, fabric_fpga_ddr0_rdata_o52, fabric_fpga_ddr0_rdata_o53, fabric_fpga_ddr0_rdata_o54, fabric_fpga_ddr0_rdata_o55, fabric_fpga_ddr0_rdata_o56, fabric_fpga_ddr0_rdata_o57, fabric_fpga_ddr0_rdata_o58, fabric_fpga_ddr0_rdata_o59, fabric_fpga_ddr0_rdata_o60, fabric_fpga_ddr0_rdata_o61, fabric_fpga_ddr0_rdata_o62, fabric_fpga_ddr0_rdata_o63, fabric_fpga_ddr0_rdata_o64, fabric_fpga_ddr0_rdata_o65, fabric_fpga_ddr0_rdata_o66, fabric_fpga_ddr0_rdata_o67, fabric_fpga_ddr0_rdata_o68, fabric_fpga_ddr0_rdata_o69
-, fabric_fpga_ddr0_rdata_o70, fabric_fpga_ddr0_rdata_o71, fabric_fpga_ddr0_rdata_o72, fabric_fpga_ddr0_rdata_o73, fabric_fpga_ddr0_rdata_o74, fabric_fpga_ddr0_rdata_o75, fabric_fpga_ddr0_rdata_o76, fabric_fpga_ddr0_rdata_o77, fabric_fpga_ddr0_rdata_o78, fabric_fpga_ddr0_rdata_o79, fabric_fpga_ddr0_rdata_o80, fabric_fpga_ddr0_rdata_o81, fabric_fpga_ddr0_rdata_o82, fabric_fpga_ddr0_rdata_o83, fabric_fpga_ddr0_rdata_o84, fabric_fpga_ddr0_rdata_o85, fabric_fpga_ddr0_rdata_o86, fabric_fpga_ddr0_rdata_o87, fabric_fpga_ddr0_rdata_o88, fabric_fpga_ddr0_rdata_o89, fabric_fpga_ddr0_rdata_o90
-, fabric_fpga_ddr0_rdata_o91, fabric_fpga_ddr0_rdata_o92, fabric_fpga_ddr0_rdata_o93, fabric_fpga_ddr0_rdata_o94, fabric_fpga_ddr0_rdata_o95, fabric_fpga_ddr0_rdata_o96, fabric_fpga_ddr0_rdata_o97, fabric_fpga_ddr0_rdata_o98, fabric_fpga_ddr0_rdata_o99, fabric_fpga_ddr0_rdata_o100, fabric_fpga_ddr0_rdata_o101, fabric_fpga_ddr0_rdata_o102, fabric_fpga_ddr0_rdata_o103, fabric_fpga_ddr0_rdata_o104, fabric_fpga_ddr0_rdata_o105, fabric_fpga_ddr0_rdata_o106, fabric_fpga_ddr0_rdata_o107, fabric_fpga_ddr0_rdata_o108, fabric_fpga_ddr0_rdata_o109, fabric_fpga_ddr0_rdata_o110, fabric_fpga_ddr0_rdata_o111
-, fabric_fpga_ddr0_rdata_o112, fabric_fpga_ddr0_rdata_o113, fabric_fpga_ddr0_rdata_o114, fabric_fpga_ddr0_rdata_o115, fabric_fpga_ddr0_rdata_o116, fabric_fpga_ddr0_rdata_o117, fabric_fpga_ddr0_rdata_o118, fabric_fpga_ddr0_rdata_o119, fabric_fpga_ddr0_rdata_o120, fabric_fpga_ddr0_rdata_o121, fabric_fpga_ddr0_rdata_o122, fabric_fpga_ddr0_rdata_o123, fabric_fpga_ddr0_rdata_o124, fabric_fpga_ddr0_rdata_o125, fabric_fpga_ddr0_rdata_o126, fabric_fpga_ddr0_rdata_o127, fabric_fpga_ddr0_rdata_o128, fabric_fpga_ddr0_rid_o1, fabric_fpga_ddr0_rid_o2, fabric_fpga_ddr0_rid_o3, fabric_fpga_ddr0_rid_o4
-, fabric_fpga_ddr0_rid_o5, fabric_fpga_ddr0_rlast_o, fabric_fpga_ddr0_rresp_o1, fabric_fpga_ddr0_rresp_o2, fabric_fpga_ddr0_rvalid_o, fabric_fpga_ddr0_wready_o, fabric_fpga_ddr0_araddr_i1, fabric_fpga_ddr0_araddr_i2, fabric_fpga_ddr0_araddr_i3, fabric_fpga_ddr0_araddr_i4, fabric_fpga_ddr0_araddr_i5, fabric_fpga_ddr0_araddr_i6, fabric_fpga_ddr0_araddr_i7, fabric_fpga_ddr0_araddr_i8, fabric_fpga_ddr0_araddr_i9, fabric_fpga_ddr0_araddr_i10, fabric_fpga_ddr0_araddr_i11, fabric_fpga_ddr0_araddr_i12, fabric_fpga_ddr0_araddr_i13, fabric_fpga_ddr0_araddr_i14, fabric_fpga_ddr0_araddr_i15
-, fabric_fpga_ddr0_araddr_i16, fabric_fpga_ddr0_araddr_i17, fabric_fpga_ddr0_araddr_i18, fabric_fpga_ddr0_araddr_i19, fabric_fpga_ddr0_araddr_i20, fabric_fpga_ddr0_araddr_i21, fabric_fpga_ddr0_araddr_i22, fabric_fpga_ddr0_araddr_i23, fabric_fpga_ddr0_araddr_i24, fabric_fpga_ddr0_araddr_i25, fabric_fpga_ddr0_araddr_i26, fabric_fpga_ddr0_araddr_i27, fabric_fpga_ddr0_araddr_i28, fabric_fpga_ddr0_araddr_i29, fabric_fpga_ddr0_araddr_i30, fabric_fpga_ddr0_araddr_i31, fabric_fpga_ddr0_araddr_i32, fabric_fpga_ddr0_araddr_i33, fabric_fpga_ddr0_araddr_i34, fabric_fpga_ddr0_araddr_i35, fabric_fpga_ddr0_araddr_i36
-, fabric_fpga_ddr0_araddr_i37, fabric_fpga_ddr0_araddr_i38, fabric_fpga_ddr0_araddr_i39, fabric_fpga_ddr0_araddr_i40, fabric_fpga_ddr0_arburst_i1, fabric_fpga_ddr0_arburst_i2, fabric_fpga_ddr0_arcache_i1, fabric_fpga_ddr0_arcache_i2, fabric_fpga_ddr0_arcache_i3, fabric_fpga_ddr0_arcache_i4, fabric_fpga_ddr0_arid_i1, fabric_fpga_ddr0_arid_i2, fabric_fpga_ddr0_arid_i3, fabric_fpga_ddr0_arid_i4, fabric_fpga_ddr0_arid_i5, fabric_fpga_ddr0_arlen_i1, fabric_fpga_ddr0_arlen_i2, fabric_fpga_ddr0_arlen_i3, fabric_fpga_ddr0_arlen_i4, fabric_fpga_ddr0_arlen_i5, fabric_fpga_ddr0_arlen_i6
-, fabric_fpga_ddr0_arlen_i7, fabric_fpga_ddr0_arlen_i8, fabric_fpga_ddr0_arlock_i, fabric_fpga_ddr0_arprot_i1, fabric_fpga_ddr0_arprot_i2, fabric_fpga_ddr0_arprot_i3, fabric_fpga_ddr0_arqos_i1, fabric_fpga_ddr0_arqos_i2, fabric_fpga_ddr0_arqos_i3, fabric_fpga_ddr0_arqos_i4, fabric_fpga_ddr0_arsize_i1, fabric_fpga_ddr0_arsize_i2, fabric_fpga_ddr0_arsize_i3, fabric_fpga_ddr0_arvalid_i, fabric_fpga_ddr0_awaddr_i1, fabric_fpga_ddr0_awaddr_i2, fabric_fpga_ddr0_awaddr_i3, fabric_fpga_ddr0_awaddr_i4, fabric_fpga_ddr0_awaddr_i5, fabric_fpga_ddr0_awaddr_i6, fabric_fpga_ddr0_awaddr_i7
-, fabric_fpga_ddr0_awaddr_i8, fabric_fpga_ddr0_awaddr_i9, fabric_fpga_ddr0_awaddr_i10, fabric_fpga_ddr0_awaddr_i11, fabric_fpga_ddr0_awaddr_i12, fabric_fpga_ddr0_awaddr_i13, fabric_fpga_ddr0_awaddr_i14, fabric_fpga_ddr0_awaddr_i15, fabric_fpga_ddr0_awaddr_i16, fabric_fpga_ddr0_awaddr_i17, fabric_fpga_ddr0_awaddr_i18, fabric_fpga_ddr0_awaddr_i19, fabric_fpga_ddr0_awaddr_i20, fabric_fpga_ddr0_awaddr_i21, fabric_fpga_ddr0_awaddr_i22, fabric_fpga_ddr0_awaddr_i23, fabric_fpga_ddr0_awaddr_i24, fabric_fpga_ddr0_awaddr_i25, fabric_fpga_ddr0_awaddr_i26, fabric_fpga_ddr0_awaddr_i27, fabric_fpga_ddr0_awaddr_i28
-, fabric_fpga_ddr0_awaddr_i29, fabric_fpga_ddr0_awaddr_i30, fabric_fpga_ddr0_awaddr_i31, fabric_fpga_ddr0_awaddr_i32, fabric_fpga_ddr0_awaddr_i33, fabric_fpga_ddr0_awaddr_i34, fabric_fpga_ddr0_awaddr_i35, fabric_fpga_ddr0_awaddr_i36, fabric_fpga_ddr0_awaddr_i37, fabric_fpga_ddr0_awaddr_i38, fabric_fpga_ddr0_awaddr_i39, fabric_fpga_ddr0_awaddr_i40, fabric_fpga_ddr0_awburst_i1, fabric_fpga_ddr0_awburst_i2, fabric_fpga_ddr0_awcache_i1, fabric_fpga_ddr0_awcache_i2, fabric_fpga_ddr0_awcache_i3, fabric_fpga_ddr0_awcache_i4, fabric_fpga_ddr0_awid_i1, fabric_fpga_ddr0_awid_i2, fabric_fpga_ddr0_awid_i3
-, fabric_fpga_ddr0_awid_i4, fabric_fpga_ddr0_awid_i5, fabric_fpga_ddr0_awlen_i1, fabric_fpga_ddr0_awlen_i2, fabric_fpga_ddr0_awlen_i3, fabric_fpga_ddr0_awlen_i4, fabric_fpga_ddr0_awlen_i5, fabric_fpga_ddr0_awlen_i6, fabric_fpga_ddr0_awlen_i7, fabric_fpga_ddr0_awlen_i8, fabric_fpga_ddr0_awlock_i, fabric_fpga_ddr0_awprot_i1, fabric_fpga_ddr0_awprot_i2, fabric_fpga_ddr0_awprot_i3, fabric_fpga_ddr0_awqos_i1, fabric_fpga_ddr0_awqos_i2, fabric_fpga_ddr0_awqos_i3, fabric_fpga_ddr0_awqos_i4, fabric_fpga_ddr0_awsize_i1, fabric_fpga_ddr0_awsize_i2, fabric_fpga_ddr0_awsize_i3
-, fabric_fpga_ddr0_awvalid_i, fabric_fpga_ddr0_bready_i, fabric_fpga_ddr0_rready_i, fabric_fpga_ddr0_wdata_i1, fabric_fpga_ddr0_wdata_i2, fabric_fpga_ddr0_wdata_i3, fabric_fpga_ddr0_wdata_i4, fabric_fpga_ddr0_wdata_i5, fabric_fpga_ddr0_wdata_i6, fabric_fpga_ddr0_wdata_i7, fabric_fpga_ddr0_wdata_i8, fabric_fpga_ddr0_wdata_i9, fabric_fpga_ddr0_wdata_i10, fabric_fpga_ddr0_wdata_i11, fabric_fpga_ddr0_wdata_i12, fabric_fpga_ddr0_wdata_i13, fabric_fpga_ddr0_wdata_i14, fabric_fpga_ddr0_wdata_i15, fabric_fpga_ddr0_wdata_i16, fabric_fpga_ddr0_wdata_i17, fabric_fpga_ddr0_wdata_i18
-, fabric_fpga_ddr0_wdata_i19, fabric_fpga_ddr0_wdata_i20, fabric_fpga_ddr0_wdata_i21, fabric_fpga_ddr0_wdata_i22, fabric_fpga_ddr0_wdata_i23, fabric_fpga_ddr0_wdata_i24, fabric_fpga_ddr0_wdata_i25, fabric_fpga_ddr0_wdata_i26, fabric_fpga_ddr0_wdata_i27, fabric_fpga_ddr0_wdata_i28, fabric_fpga_ddr0_wdata_i29, fabric_fpga_ddr0_wdata_i30, fabric_fpga_ddr0_wdata_i31, fabric_fpga_ddr0_wdata_i32, fabric_fpga_ddr0_wdata_i33, fabric_fpga_ddr0_wdata_i34, fabric_fpga_ddr0_wdata_i35, fabric_fpga_ddr0_wdata_i36, fabric_fpga_ddr0_wdata_i37, fabric_fpga_ddr0_wdata_i38, fabric_fpga_ddr0_wdata_i39
-, fabric_fpga_ddr0_wdata_i40, fabric_fpga_ddr0_wdata_i41, fabric_fpga_ddr0_wdata_i42, fabric_fpga_ddr0_wdata_i43, fabric_fpga_ddr0_wdata_i44, fabric_fpga_ddr0_wdata_i45, fabric_fpga_ddr0_wdata_i46, fabric_fpga_ddr0_wdata_i47, fabric_fpga_ddr0_wdata_i48, fabric_fpga_ddr0_wdata_i49, fabric_fpga_ddr0_wdata_i50, fabric_fpga_ddr0_wdata_i51, fabric_fpga_ddr0_wdata_i52, fabric_fpga_ddr0_wdata_i53, fabric_fpga_ddr0_wdata_i54, fabric_fpga_ddr0_wdata_i55, fabric_fpga_ddr0_wdata_i56, fabric_fpga_ddr0_wdata_i57, fabric_fpga_ddr0_wdata_i58, fabric_fpga_ddr0_wdata_i59, fabric_fpga_ddr0_wdata_i60
-, fabric_fpga_ddr0_wdata_i61, fabric_fpga_ddr0_wdata_i62, fabric_fpga_ddr0_wdata_i63, fabric_fpga_ddr0_wdata_i64, fabric_fpga_ddr0_wdata_i65, fabric_fpga_ddr0_wdata_i66, fabric_fpga_ddr0_wdata_i67, fabric_fpga_ddr0_wdata_i68, fabric_fpga_ddr0_wdata_i69, fabric_fpga_ddr0_wdata_i70, fabric_fpga_ddr0_wdata_i71, fabric_fpga_ddr0_wdata_i72, fabric_fpga_ddr0_wdata_i73, fabric_fpga_ddr0_wdata_i74, fabric_fpga_ddr0_wdata_i75, fabric_fpga_ddr0_wdata_i76, fabric_fpga_ddr0_wdata_i77, fabric_fpga_ddr0_wdata_i78, fabric_fpga_ddr0_wdata_i79, fabric_fpga_ddr0_wdata_i80, fabric_fpga_ddr0_wdata_i81
-, fabric_fpga_ddr0_wdata_i82, fabric_fpga_ddr0_wdata_i83, fabric_fpga_ddr0_wdata_i84, fabric_fpga_ddr0_wdata_i85, fabric_fpga_ddr0_wdata_i86, fabric_fpga_ddr0_wdata_i87, fabric_fpga_ddr0_wdata_i88, fabric_fpga_ddr0_wdata_i89, fabric_fpga_ddr0_wdata_i90, fabric_fpga_ddr0_wdata_i91, fabric_fpga_ddr0_wdata_i92, fabric_fpga_ddr0_wdata_i93, fabric_fpga_ddr0_wdata_i94, fabric_fpga_ddr0_wdata_i95, fabric_fpga_ddr0_wdata_i96, fabric_fpga_ddr0_wdata_i97, fabric_fpga_ddr0_wdata_i98, fabric_fpga_ddr0_wdata_i99, fabric_fpga_ddr0_wdata_i100, fabric_fpga_ddr0_wdata_i101, fabric_fpga_ddr0_wdata_i102
-, fabric_fpga_ddr0_wdata_i103, fabric_fpga_ddr0_wdata_i104, fabric_fpga_ddr0_wdata_i105, fabric_fpga_ddr0_wdata_i106, fabric_fpga_ddr0_wdata_i107, fabric_fpga_ddr0_wdata_i108, fabric_fpga_ddr0_wdata_i109, fabric_fpga_ddr0_wdata_i110, fabric_fpga_ddr0_wdata_i111, fabric_fpga_ddr0_wdata_i112, fabric_fpga_ddr0_wdata_i113, fabric_fpga_ddr0_wdata_i114, fabric_fpga_ddr0_wdata_i115, fabric_fpga_ddr0_wdata_i116, fabric_fpga_ddr0_wdata_i117, fabric_fpga_ddr0_wdata_i118, fabric_fpga_ddr0_wdata_i119, fabric_fpga_ddr0_wdata_i120, fabric_fpga_ddr0_wdata_i121, fabric_fpga_ddr0_wdata_i122, fabric_fpga_ddr0_wdata_i123
-, fabric_fpga_ddr0_wdata_i124, fabric_fpga_ddr0_wdata_i125, fabric_fpga_ddr0_wdata_i126, fabric_fpga_ddr0_wdata_i127, fabric_fpga_ddr0_wdata_i128, fabric_fpga_ddr0_wlast_i, fabric_fpga_ddr0_wstrb_i1, fabric_fpga_ddr0_wstrb_i2, fabric_fpga_ddr0_wstrb_i3, fabric_fpga_ddr0_wstrb_i4, fabric_fpga_ddr0_wstrb_i5, fabric_fpga_ddr0_wstrb_i6, fabric_fpga_ddr0_wstrb_i7, fabric_fpga_ddr0_wstrb_i8, fabric_fpga_ddr0_wstrb_i9, fabric_fpga_ddr0_wstrb_i10, fabric_fpga_ddr0_wstrb_i11, fabric_fpga_ddr0_wstrb_i12, fabric_fpga_ddr0_wstrb_i13, fabric_fpga_ddr0_wstrb_i14, fabric_fpga_ddr0_wstrb_i15
-, fabric_fpga_ddr0_wstrb_i16, fabric_fpga_ddr0_wvalid_i, fabric_fpga_paddr_apb_o1, fabric_fpga_paddr_apb_o2, fabric_fpga_paddr_apb_o3, fabric_fpga_paddr_apb_o4, fabric_fpga_paddr_apb_o5, fabric_fpga_paddr_apb_o6, fabric_fpga_paddr_apb_o7, fabric_fpga_paddr_apb_o8, fabric_fpga_paddr_apb_o9, fabric_fpga_paddr_apb_o10, fabric_fpga_paddr_apb_o11, fabric_fpga_paddr_apb_o12, fabric_fpga_paddr_apb_o13, fabric_fpga_paddr_apb_o14, fabric_fpga_paddr_apb_o15, fabric_fpga_paddr_apb_o16, fabric_fpga_paddr_apb_o17, fabric_fpga_paddr_apb_o18, fabric_fpga_paddr_apb_o19
-, fabric_fpga_paddr_apb_o20, fabric_fpga_paddr_apb_o21, fabric_fpga_paddr_apb_o22, fabric_fpga_paddr_apb_o23, fabric_fpga_paddr_apb_o24, fabric_fpga_paddr_apb_o25, fabric_fpga_paddr_apb_o26, fabric_fpga_paddr_apb_o27, fabric_fpga_paddr_apb_o28, fabric_fpga_paddr_apb_o29, fabric_fpga_paddr_apb_o30, fabric_fpga_paddr_apb_o31, fabric_fpga_paddr_apb_o32, fabric_fpga_penable_apb_o, fabric_fpga_psel_apb_o, fabric_fpga_pwdata_apb_o1, fabric_fpga_pwdata_apb_o2, fabric_fpga_pwdata_apb_o3, fabric_fpga_pwdata_apb_o4, fabric_fpga_pwdata_apb_o5, fabric_fpga_pwdata_apb_o6
-, fabric_fpga_pwdata_apb_o7, fabric_fpga_pwdata_apb_o8, fabric_fpga_pwdata_apb_o9, fabric_fpga_pwdata_apb_o10, fabric_fpga_pwdata_apb_o11, fabric_fpga_pwdata_apb_o12, fabric_fpga_pwdata_apb_o13, fabric_fpga_pwdata_apb_o14, fabric_fpga_pwdata_apb_o15, fabric_fpga_pwdata_apb_o16, fabric_fpga_pwdata_apb_o17, fabric_fpga_pwdata_apb_o18, fabric_fpga_pwdata_apb_o19, fabric_fpga_pwdata_apb_o20, fabric_fpga_pwdata_apb_o21, fabric_fpga_pwdata_apb_o22, fabric_fpga_pwdata_apb_o23, fabric_fpga_pwdata_apb_o24, fabric_fpga_pwdata_apb_o25, fabric_fpga_pwdata_apb_o26, fabric_fpga_pwdata_apb_o27
-, fabric_fpga_pwdata_apb_o28, fabric_fpga_pwdata_apb_o29, fabric_fpga_pwdata_apb_o30, fabric_fpga_pwdata_apb_o31, fabric_fpga_pwdata_apb_o32, fabric_fpga_pwrite_apb_o, fabric_fpga_prdata_apb_i1, fabric_fpga_prdata_apb_i2, fabric_fpga_prdata_apb_i3, fabric_fpga_prdata_apb_i4, fabric_fpga_prdata_apb_i5, fabric_fpga_prdata_apb_i6, fabric_fpga_prdata_apb_i7, fabric_fpga_prdata_apb_i8, fabric_fpga_prdata_apb_i9, fabric_fpga_prdata_apb_i10, fabric_fpga_prdata_apb_i11, fabric_fpga_prdata_apb_i12, fabric_fpga_prdata_apb_i13, fabric_fpga_prdata_apb_i14, fabric_fpga_prdata_apb_i15
-, fabric_fpga_prdata_apb_i16, fabric_fpga_prdata_apb_i17, fabric_fpga_prdata_apb_i18, fabric_fpga_prdata_apb_i19, fabric_fpga_prdata_apb_i20, fabric_fpga_prdata_apb_i21, fabric_fpga_prdata_apb_i22, fabric_fpga_prdata_apb_i23, fabric_fpga_prdata_apb_i24, fabric_fpga_prdata_apb_i25, fabric_fpga_prdata_apb_i26, fabric_fpga_prdata_apb_i27, fabric_fpga_prdata_apb_i28, fabric_fpga_prdata_apb_i29, fabric_fpga_prdata_apb_i30, fabric_fpga_prdata_apb_i31, fabric_fpga_prdata_apb_i32, fabric_fpga_pready_apb_i, fabric_fpga_pslverr_apb_i, fabric_llpp0_araddr_s_o1, fabric_llpp0_araddr_s_o2
-, fabric_llpp0_araddr_s_o3, fabric_llpp0_araddr_s_o4, fabric_llpp0_araddr_s_o5, fabric_llpp0_araddr_s_o6, fabric_llpp0_araddr_s_o7, fabric_llpp0_araddr_s_o8, fabric_llpp0_araddr_s_o9, fabric_llpp0_araddr_s_o10, fabric_llpp0_araddr_s_o11, fabric_llpp0_araddr_s_o12, fabric_llpp0_araddr_s_o13, fabric_llpp0_araddr_s_o14, fabric_llpp0_araddr_s_o15, fabric_llpp0_araddr_s_o16, fabric_llpp0_araddr_s_o17, fabric_llpp0_araddr_s_o18, fabric_llpp0_araddr_s_o19, fabric_llpp0_araddr_s_o20, fabric_llpp0_araddr_s_o21, fabric_llpp0_araddr_s_o22, fabric_llpp0_araddr_s_o23
-, fabric_llpp0_araddr_s_o24, fabric_llpp0_araddr_s_o25, fabric_llpp0_araddr_s_o26, fabric_llpp0_araddr_s_o27, fabric_llpp0_araddr_s_o28, fabric_llpp0_araddr_s_o29, fabric_llpp0_araddr_s_o30, fabric_llpp0_araddr_s_o31, fabric_llpp0_araddr_s_o32, fabric_llpp0_arburst_s_o1, fabric_llpp0_arburst_s_o2, fabric_llpp0_arcache_s_o1, fabric_llpp0_arcache_s_o2, fabric_llpp0_arcache_s_o3, fabric_llpp0_arcache_s_o4, fabric_llpp0_arid_s_o1, fabric_llpp0_arid_s_o2, fabric_llpp0_arid_s_o3, fabric_llpp0_arid_s_o4, fabric_llpp0_arid_s_o5, fabric_llpp0_arid_s_o6
-, fabric_llpp0_arid_s_o7, fabric_llpp0_arid_s_o8, fabric_llpp0_arid_s_o9, fabric_llpp0_arid_s_o10, fabric_llpp0_arid_s_o11, fabric_llpp0_arid_s_o12, fabric_llpp0_arlen_s_o1, fabric_llpp0_arlen_s_o2, fabric_llpp0_arlen_s_o3, fabric_llpp0_arlen_s_o4, fabric_llpp0_arlen_s_o5, fabric_llpp0_arlen_s_o6, fabric_llpp0_arlen_s_o7, fabric_llpp0_arlen_s_o8, fabric_llpp0_arlock_s_o, fabric_llpp0_arprot_s_o1, fabric_llpp0_arprot_s_o2, fabric_llpp0_arprot_s_o3, fabric_llpp0_arqos_s_o1, fabric_llpp0_arqos_s_o2, fabric_llpp0_arqos_s_o3
-, fabric_llpp0_arqos_s_o4, fabric_llpp0_arsize_s_o1, fabric_llpp0_arsize_s_o2, fabric_llpp0_arsize_s_o3, fabric_llpp0_arvalid_s_o, fabric_llpp0_awaddr_s_o1, fabric_llpp0_awaddr_s_o2, fabric_llpp0_awaddr_s_o3, fabric_llpp0_awaddr_s_o4, fabric_llpp0_awaddr_s_o5, fabric_llpp0_awaddr_s_o6, fabric_llpp0_awaddr_s_o7, fabric_llpp0_awaddr_s_o8, fabric_llpp0_awaddr_s_o9, fabric_llpp0_awaddr_s_o10, fabric_llpp0_awaddr_s_o11, fabric_llpp0_awaddr_s_o12, fabric_llpp0_awaddr_s_o13, fabric_llpp0_awaddr_s_o14, fabric_llpp0_awaddr_s_o15, fabric_llpp0_awaddr_s_o16
-, fabric_llpp0_awaddr_s_o17, fabric_llpp0_awaddr_s_o18, fabric_llpp0_awaddr_s_o19, fabric_llpp0_awaddr_s_o20, fabric_llpp0_awaddr_s_o21, fabric_llpp0_awaddr_s_o22, fabric_llpp0_awaddr_s_o23, fabric_llpp0_awaddr_s_o24, fabric_llpp0_awaddr_s_o25, fabric_llpp0_awaddr_s_o26, fabric_llpp0_awaddr_s_o27, fabric_llpp0_awaddr_s_o28, fabric_llpp0_awaddr_s_o29, fabric_llpp0_awaddr_s_o30, fabric_llpp0_awaddr_s_o31, fabric_llpp0_awaddr_s_o32, fabric_llpp0_awburst_s_o1, fabric_llpp0_awburst_s_o2, fabric_llpp0_awcache_s_o1, fabric_llpp0_awcache_s_o2, fabric_llpp0_awcache_s_o3
-, fabric_llpp0_awcache_s_o4, fabric_llpp0_awid_s_o1, fabric_llpp0_awid_s_o2, fabric_llpp0_awid_s_o3, fabric_llpp0_awid_s_o4, fabric_llpp0_awid_s_o5, fabric_llpp0_awid_s_o6, fabric_llpp0_awid_s_o7, fabric_llpp0_awid_s_o8, fabric_llpp0_awid_s_o9, fabric_llpp0_awid_s_o10, fabric_llpp0_awid_s_o11, fabric_llpp0_awid_s_o12, fabric_llpp0_awlen_s_o1, fabric_llpp0_awlen_s_o2, fabric_llpp0_awlen_s_o3, fabric_llpp0_awlen_s_o4, fabric_llpp0_awlen_s_o5, fabric_llpp0_awlen_s_o6, fabric_llpp0_awlen_s_o7, fabric_llpp0_awlen_s_o8
-, fabric_llpp0_awlock_s_o, fabric_llpp0_awprot_s_o1, fabric_llpp0_awprot_s_o2, fabric_llpp0_awprot_s_o3, fabric_llpp0_awqos_s_o1, fabric_llpp0_awqos_s_o2, fabric_llpp0_awqos_s_o3, fabric_llpp0_awqos_s_o4, fabric_llpp0_awsize_s_o1, fabric_llpp0_awsize_s_o2, fabric_llpp0_awsize_s_o3, fabric_llpp0_awvalid_s_o, fabric_llpp0_bready_s_o, fabric_llpp0_rready_s_o, fabric_llpp0_wdata_s_o1, fabric_llpp0_wdata_s_o2, fabric_llpp0_wdata_s_o3, fabric_llpp0_wdata_s_o4, fabric_llpp0_wdata_s_o5, fabric_llpp0_wdata_s_o6, fabric_llpp0_wdata_s_o7
-, fabric_llpp0_wdata_s_o8, fabric_llpp0_wdata_s_o9, fabric_llpp0_wdata_s_o10, fabric_llpp0_wdata_s_o11, fabric_llpp0_wdata_s_o12, fabric_llpp0_wdata_s_o13, fabric_llpp0_wdata_s_o14, fabric_llpp0_wdata_s_o15, fabric_llpp0_wdata_s_o16, fabric_llpp0_wdata_s_o17, fabric_llpp0_wdata_s_o18, fabric_llpp0_wdata_s_o19, fabric_llpp0_wdata_s_o20, fabric_llpp0_wdata_s_o21, fabric_llpp0_wdata_s_o22, fabric_llpp0_wdata_s_o23, fabric_llpp0_wdata_s_o24, fabric_llpp0_wdata_s_o25, fabric_llpp0_wdata_s_o26, fabric_llpp0_wdata_s_o27, fabric_llpp0_wdata_s_o28
-, fabric_llpp0_wdata_s_o29, fabric_llpp0_wdata_s_o30, fabric_llpp0_wdata_s_o31, fabric_llpp0_wdata_s_o32, fabric_llpp0_wlast_s_o, fabric_llpp0_wstrb_s_o1, fabric_llpp0_wstrb_s_o2, fabric_llpp0_wstrb_s_o3, fabric_llpp0_wstrb_s_o4, fabric_llpp0_wvalid_s_o, fabric_llpp0_arready_s_i, fabric_llpp0_awready_s_i, fabric_llpp0_bid_s_i1, fabric_llpp0_bid_s_i2, fabric_llpp0_bid_s_i3, fabric_llpp0_bid_s_i4, fabric_llpp0_bid_s_i5, fabric_llpp0_bid_s_i6, fabric_llpp0_bid_s_i7, fabric_llpp0_bid_s_i8, fabric_llpp0_bid_s_i9
-, fabric_llpp0_bid_s_i10, fabric_llpp0_bid_s_i11, fabric_llpp0_bid_s_i12, fabric_llpp0_bresp_s_i1, fabric_llpp0_bresp_s_i2, fabric_llpp0_bvalid_s_i, fabric_llpp0_rdata_s_i1, fabric_llpp0_rdata_s_i2, fabric_llpp0_rdata_s_i3, fabric_llpp0_rdata_s_i4, fabric_llpp0_rdata_s_i5, fabric_llpp0_rdata_s_i6, fabric_llpp0_rdata_s_i7, fabric_llpp0_rdata_s_i8, fabric_llpp0_rdata_s_i9, fabric_llpp0_rdata_s_i10, fabric_llpp0_rdata_s_i11, fabric_llpp0_rdata_s_i12, fabric_llpp0_rdata_s_i13, fabric_llpp0_rdata_s_i14, fabric_llpp0_rdata_s_i15
-, fabric_llpp0_rdata_s_i16, fabric_llpp0_rdata_s_i17, fabric_llpp0_rdata_s_i18, fabric_llpp0_rdata_s_i19, fabric_llpp0_rdata_s_i20, fabric_llpp0_rdata_s_i21, fabric_llpp0_rdata_s_i22, fabric_llpp0_rdata_s_i23, fabric_llpp0_rdata_s_i24, fabric_llpp0_rdata_s_i25, fabric_llpp0_rdata_s_i26, fabric_llpp0_rdata_s_i27, fabric_llpp0_rdata_s_i28, fabric_llpp0_rdata_s_i29, fabric_llpp0_rdata_s_i30, fabric_llpp0_rdata_s_i31, fabric_llpp0_rdata_s_i32, fabric_llpp0_rid_s_i1, fabric_llpp0_rid_s_i2, fabric_llpp0_rid_s_i3, fabric_llpp0_rid_s_i4
-, fabric_llpp0_rid_s_i5, fabric_llpp0_rid_s_i6, fabric_llpp0_rid_s_i7, fabric_llpp0_rid_s_i8, fabric_llpp0_rid_s_i9, fabric_llpp0_rid_s_i10, fabric_llpp0_rid_s_i11, fabric_llpp0_rid_s_i12, fabric_llpp0_rlast_s_i, fabric_llpp0_rresp_s_i1, fabric_llpp0_rresp_s_i2, fabric_llpp0_rvalid_s_i, fabric_llpp0_wready_s_i, fabric_llpp1_araddr_s_o1, fabric_llpp1_araddr_s_o2, fabric_llpp1_araddr_s_o3, fabric_llpp1_araddr_s_o4, fabric_llpp1_araddr_s_o5, fabric_llpp1_araddr_s_o6, fabric_llpp1_araddr_s_o7, fabric_llpp1_araddr_s_o8
-, fabric_llpp1_araddr_s_o9, fabric_llpp1_araddr_s_o10, fabric_llpp1_araddr_s_o11, fabric_llpp1_araddr_s_o12, fabric_llpp1_araddr_s_o13, fabric_llpp1_araddr_s_o14, fabric_llpp1_araddr_s_o15, fabric_llpp1_araddr_s_o16, fabric_llpp1_araddr_s_o17, fabric_llpp1_araddr_s_o18, fabric_llpp1_araddr_s_o19, fabric_llpp1_araddr_s_o20, fabric_llpp1_araddr_s_o21, fabric_llpp1_araddr_s_o22, fabric_llpp1_araddr_s_o23, fabric_llpp1_araddr_s_o24, fabric_llpp1_araddr_s_o25, fabric_llpp1_araddr_s_o26, fabric_llpp1_araddr_s_o27, fabric_llpp1_araddr_s_o28, fabric_llpp1_araddr_s_o29
-, fabric_llpp1_araddr_s_o30, fabric_llpp1_araddr_s_o31, fabric_llpp1_araddr_s_o32, fabric_llpp1_arburst_s_o1, fabric_llpp1_arburst_s_o2, fabric_llpp1_arcache_s_o1, fabric_llpp1_arcache_s_o2, fabric_llpp1_arcache_s_o3, fabric_llpp1_arcache_s_o4, fabric_llpp1_arid_s_o1, fabric_llpp1_arid_s_o2, fabric_llpp1_arid_s_o3, fabric_llpp1_arid_s_o4, fabric_llpp1_arid_s_o5, fabric_llpp1_arid_s_o6, fabric_llpp1_arid_s_o7, fabric_llpp1_arid_s_o8, fabric_llpp1_arid_s_o9, fabric_llpp1_arid_s_o10, fabric_llpp1_arid_s_o11, fabric_llpp1_arid_s_o12
-, fabric_llpp1_arlen_s_o1, fabric_llpp1_arlen_s_o2, fabric_llpp1_arlen_s_o3, fabric_llpp1_arlen_s_o4, fabric_llpp1_arlen_s_o5, fabric_llpp1_arlen_s_o6, fabric_llpp1_arlen_s_o7, fabric_llpp1_arlen_s_o8, fabric_llpp1_arlock_s_o, fabric_llpp1_arprot_s_o1, fabric_llpp1_arprot_s_o2, fabric_llpp1_arprot_s_o3, fabric_llpp1_arqos_s1_o1, fabric_llpp1_arqos_s1_o2, fabric_llpp1_arqos_s1_o3, fabric_llpp1_arqos_s1_o4, fabric_llpp1_arsize_s_o1, fabric_llpp1_arsize_s_o2, fabric_llpp1_arsize_s_o3, fabric_llpp1_arvalid_s_o, fabric_llpp1_awaddr_s_o1
-, fabric_llpp1_awaddr_s_o2, fabric_llpp1_awaddr_s_o3, fabric_llpp1_awaddr_s_o4, fabric_llpp1_awaddr_s_o5, fabric_llpp1_awaddr_s_o6, fabric_llpp1_awaddr_s_o7, fabric_llpp1_awaddr_s_o8, fabric_llpp1_awaddr_s_o9, fabric_llpp1_awaddr_s_o10, fabric_llpp1_awaddr_s_o11, fabric_llpp1_awaddr_s_o12, fabric_llpp1_awaddr_s_o13, fabric_llpp1_awaddr_s_o14, fabric_llpp1_awaddr_s_o15, fabric_llpp1_awaddr_s_o16, fabric_llpp1_awaddr_s_o17, fabric_llpp1_awaddr_s_o18, fabric_llpp1_awaddr_s_o19, fabric_llpp1_awaddr_s_o20, fabric_llpp1_awaddr_s_o21, fabric_llpp1_awaddr_s_o22
-, fabric_llpp1_awaddr_s_o23, fabric_llpp1_awaddr_s_o24, fabric_llpp1_awaddr_s_o25, fabric_llpp1_awaddr_s_o26, fabric_llpp1_awaddr_s_o27, fabric_llpp1_awaddr_s_o28, fabric_llpp1_awaddr_s_o29, fabric_llpp1_awaddr_s_o30, fabric_llpp1_awaddr_s_o31, fabric_llpp1_awaddr_s_o32, fabric_llpp1_awburst_s_o1, fabric_llpp1_awburst_s_o2, fabric_llpp1_awcache_s_o1, fabric_llpp1_awcache_s_o2, fabric_llpp1_awcache_s_o3, fabric_llpp1_awcache_s_o4, fabric_llpp1_awid_s_o1, fabric_llpp1_awid_s_o2, fabric_llpp1_awid_s_o3, fabric_llpp1_awid_s_o4, fabric_llpp1_awid_s_o5
-, fabric_llpp1_awid_s_o6, fabric_llpp1_awid_s_o7, fabric_llpp1_awid_s_o8, fabric_llpp1_awid_s_o9, fabric_llpp1_awid_s_o10, fabric_llpp1_awid_s_o11, fabric_llpp1_awid_s_o12, fabric_llpp1_awlen_s_o1, fabric_llpp1_awlen_s_o2, fabric_llpp1_awlen_s_o3, fabric_llpp1_awlen_s_o4, fabric_llpp1_awlen_s_o5, fabric_llpp1_awlen_s_o6, fabric_llpp1_awlen_s_o7, fabric_llpp1_awlen_s_o8, fabric_llpp1_awlock_s_o, fabric_llpp1_awprot_s_o1, fabric_llpp1_awprot_s_o2, fabric_llpp1_awprot_s_o3, fabric_llpp1_awqos_s_o1, fabric_llpp1_awqos_s_o2
-, fabric_llpp1_awqos_s_o3, fabric_llpp1_awqos_s_o4, fabric_llpp1_awsize_s_o1, fabric_llpp1_awsize_s_o2, fabric_llpp1_awsize_s_o3, fabric_llpp1_awvalid_s_o, fabric_llpp1_bready_s_o, fabric_llpp1_rready_s_o, fabric_llpp1_wdata_s_o1, fabric_llpp1_wdata_s_o2, fabric_llpp1_wdata_s_o3, fabric_llpp1_wdata_s_o4, fabric_llpp1_wdata_s_o5, fabric_llpp1_wdata_s_o6, fabric_llpp1_wdata_s_o7, fabric_llpp1_wdata_s_o8, fabric_llpp1_wdata_s_o9, fabric_llpp1_wdata_s_o10, fabric_llpp1_wdata_s_o11, fabric_llpp1_wdata_s_o12, fabric_llpp1_wdata_s_o13
-, fabric_llpp1_wdata_s_o14, fabric_llpp1_wdata_s_o15, fabric_llpp1_wdata_s_o16, fabric_llpp1_wdata_s_o17, fabric_llpp1_wdata_s_o18, fabric_llpp1_wdata_s_o19, fabric_llpp1_wdata_s_o20, fabric_llpp1_wdata_s_o21, fabric_llpp1_wdata_s_o22, fabric_llpp1_wdata_s_o23, fabric_llpp1_wdata_s_o24, fabric_llpp1_wdata_s_o25, fabric_llpp1_wdata_s_o26, fabric_llpp1_wdata_s_o27, fabric_llpp1_wdata_s_o28, fabric_llpp1_wdata_s_o29, fabric_llpp1_wdata_s_o30, fabric_llpp1_wdata_s_o31, fabric_llpp1_wdata_s_o32, fabric_llpp1_wlast_s_o, fabric_llpp1_wstrb_s_o1
-, fabric_llpp1_wstrb_s_o2, fabric_llpp1_wstrb_s_o3, fabric_llpp1_wstrb_s_o4, fabric_llpp1_wvalid_s_o, fabric_llpp1_arready_s_i, fabric_llpp1_awready_s_i, fabric_llpp1_bid_s_i1, fabric_llpp1_bid_s_i2, fabric_llpp1_bid_s_i3, fabric_llpp1_bid_s_i4, fabric_llpp1_bid_s_i5, fabric_llpp1_bid_s_i6, fabric_llpp1_bid_s_i7, fabric_llpp1_bid_s_i8, fabric_llpp1_bid_s_i9, fabric_llpp1_bid_s_i10, fabric_llpp1_bid_s_i11, fabric_llpp1_bid_s_i12, fabric_llpp1_bresp_s_i1, fabric_llpp1_bresp_s_i2, fabric_llpp1_bvalid_s_i
-, fabric_llpp1_rdata_s_i1, fabric_llpp1_rdata_s_i2, fabric_llpp1_rdata_s_i3, fabric_llpp1_rdata_s_i4, fabric_llpp1_rdata_s_i5, fabric_llpp1_rdata_s_i6, fabric_llpp1_rdata_s_i7, fabric_llpp1_rdata_s_i8, fabric_llpp1_rdata_s_i9, fabric_llpp1_rdata_s_i10, fabric_llpp1_rdata_s_i11, fabric_llpp1_rdata_s_i12, fabric_llpp1_rdata_s_i13, fabric_llpp1_rdata_s_i14, fabric_llpp1_rdata_s_i15, fabric_llpp1_rdata_s_i16, fabric_llpp1_rdata_s_i17, fabric_llpp1_rdata_s_i18, fabric_llpp1_rdata_s_i19, fabric_llpp1_rdata_s_i20, fabric_llpp1_rdata_s_i21
-, fabric_llpp1_rdata_s_i22, fabric_llpp1_rdata_s_i23, fabric_llpp1_rdata_s_i24, fabric_llpp1_rdata_s_i25, fabric_llpp1_rdata_s_i26, fabric_llpp1_rdata_s_i27, fabric_llpp1_rdata_s_i28, fabric_llpp1_rdata_s_i29, fabric_llpp1_rdata_s_i30, fabric_llpp1_rdata_s_i31, fabric_llpp1_rdata_s_i32, fabric_llpp1_rid_s_i1, fabric_llpp1_rid_s_i2, fabric_llpp1_rid_s_i3, fabric_llpp1_rid_s_i4, fabric_llpp1_rid_s_i5, fabric_llpp1_rid_s_i6, fabric_llpp1_rid_s_i7, fabric_llpp1_rid_s_i8, fabric_llpp1_rid_s_i9, fabric_llpp1_rid_s_i10
-, fabric_llpp1_rid_s_i11, fabric_llpp1_rid_s_i12, fabric_llpp1_rlast_s_i, fabric_llpp1_rresp_s_i1, fabric_llpp1_rresp_s_i2, fabric_llpp1_rvalid_s_i, fabric_llpp1_wready_s_i, fabric_llpp2_araddr_s_o1, fabric_llpp2_araddr_s_o2, fabric_llpp2_araddr_s_o3, fabric_llpp2_araddr_s_o4, fabric_llpp2_araddr_s_o5, fabric_llpp2_araddr_s_o6, fabric_llpp2_araddr_s_o7, fabric_llpp2_araddr_s_o8, fabric_llpp2_araddr_s_o9, fabric_llpp2_araddr_s_o10, fabric_llpp2_araddr_s_o11, fabric_llpp2_araddr_s_o12, fabric_llpp2_araddr_s_o13, fabric_llpp2_araddr_s_o14
-, fabric_llpp2_araddr_s_o15, fabric_llpp2_araddr_s_o16, fabric_llpp2_araddr_s_o17, fabric_llpp2_araddr_s_o18, fabric_llpp2_araddr_s_o19, fabric_llpp2_araddr_s_o20, fabric_llpp2_araddr_s_o21, fabric_llpp2_araddr_s_o22, fabric_llpp2_araddr_s_o23, fabric_llpp2_araddr_s_o24, fabric_llpp2_araddr_s_o25, fabric_llpp2_araddr_s_o26, fabric_llpp2_araddr_s_o27, fabric_llpp2_araddr_s_o28, fabric_llpp2_araddr_s_o29, fabric_llpp2_araddr_s_o30, fabric_llpp2_araddr_s_o31, fabric_llpp2_araddr_s_o32, fabric_llpp2_arburst_s_o1, fabric_llpp2_arburst_s_o2, fabric_llpp2_arcache_s_o1
-, fabric_llpp2_arcache_s_o2, fabric_llpp2_arcache_s_o3, fabric_llpp2_arcache_s_o4, fabric_llpp2_arid_s_o1, fabric_llpp2_arid_s_o2, fabric_llpp2_arid_s_o3, fabric_llpp2_arid_s_o4, fabric_llpp2_arid_s_o5, fabric_llpp2_arid_s_o6, fabric_llpp2_arid_s_o7, fabric_llpp2_arid_s_o8, fabric_llpp2_arid_s_o9, fabric_llpp2_arid_s_o10, fabric_llpp2_arid_s_o11, fabric_llpp2_arid_s_o12, fabric_llpp2_arlen_s_o1, fabric_llpp2_arlen_s_o2, fabric_llpp2_arlen_s_o3, fabric_llpp2_arlen_s_o4, fabric_llpp2_arlen_s_o5, fabric_llpp2_arlen_s_o6
-, fabric_llpp2_arlen_s_o7, fabric_llpp2_arlen_s_o8, fabric_llpp2_arlock_s_o, fabric_llpp2_arprot_s_o1, fabric_llpp2_arprot_s_o2, fabric_llpp2_arprot_s_o3, fabric_llpp2_arqos_s_o1, fabric_llpp2_arqos_s_o2, fabric_llpp2_arqos_s_o3, fabric_llpp2_arqos_s_o4, fabric_llpp2_arsize_s_o1, fabric_llpp2_arsize_s_o2, fabric_llpp2_arsize_s_o3, fabric_llpp2_arvalid_s_o, fabric_llpp2_awaddr_s_o1, fabric_llpp2_awaddr_s_o2, fabric_llpp2_awaddr_s_o3, fabric_llpp2_awaddr_s_o4, fabric_llpp2_awaddr_s_o5, fabric_llpp2_awaddr_s_o6, fabric_llpp2_awaddr_s_o7
-, fabric_llpp2_awaddr_s_o8, fabric_llpp2_awaddr_s_o9, fabric_llpp2_awaddr_s_o10, fabric_llpp2_awaddr_s_o11, fabric_llpp2_awaddr_s_o12, fabric_llpp2_awaddr_s_o13, fabric_llpp2_awaddr_s_o14, fabric_llpp2_awaddr_s_o15, fabric_llpp2_awaddr_s_o16, fabric_llpp2_awaddr_s_o17, fabric_llpp2_awaddr_s_o18, fabric_llpp2_awaddr_s_o19, fabric_llpp2_awaddr_s_o20, fabric_llpp2_awaddr_s_o21, fabric_llpp2_awaddr_s_o22, fabric_llpp2_awaddr_s_o23, fabric_llpp2_awaddr_s_o24, fabric_llpp2_awaddr_s_o25, fabric_llpp2_awaddr_s_o26, fabric_llpp2_awaddr_s_o27, fabric_llpp2_awaddr_s_o28
-, fabric_llpp2_awaddr_s_o29, fabric_llpp2_awaddr_s_o30, fabric_llpp2_awaddr_s_o31, fabric_llpp2_awaddr_s_o32, fabric_llpp2_awburst_s_o1, fabric_llpp2_awburst_s_o2, fabric_llpp2_awcache_s_o1, fabric_llpp2_awcache_s_o2, fabric_llpp2_awcache_s_o3, fabric_llpp2_awcache_s_o4, fabric_llpp2_awid_s_o1, fabric_llpp2_awid_s_o2, fabric_llpp2_awid_s_o3, fabric_llpp2_awid_s_o4, fabric_llpp2_awid_s_o5, fabric_llpp2_awid_s_o6, fabric_llpp2_awid_s_o7, fabric_llpp2_awid_s_o8, fabric_llpp2_awid_s_o9, fabric_llpp2_awid_s_o10, fabric_llpp2_awid_s_o11
-, fabric_llpp2_awid_s_o12, fabric_llpp2_awlen_s_o1, fabric_llpp2_awlen_s_o2, fabric_llpp2_awlen_s_o3, fabric_llpp2_awlen_s_o4, fabric_llpp2_awlen_s_o5, fabric_llpp2_awlen_s_o6, fabric_llpp2_awlen_s_o7, fabric_llpp2_awlen_s_o8, fabric_llpp2_awlock_s_o, fabric_llpp2_awprot_s_o1, fabric_llpp2_awprot_s_o2, fabric_llpp2_awprot_s_o3, fabric_llpp2_awqos_s_o1, fabric_llpp2_awqos_s_o2, fabric_llpp2_awqos_s_o3, fabric_llpp2_awqos_s_o4, fabric_llpp2_awsize_s_o1, fabric_llpp2_awsize_s_o2, fabric_llpp2_awsize_s_o3, fabric_llpp2_awvalid_s_o
-, fabric_llpp2_bready_s_o, fabric_llpp2_rready_s_o, fabric_llpp2_wdata_s_o1, fabric_llpp2_wdata_s_o2, fabric_llpp2_wdata_s_o3, fabric_llpp2_wdata_s_o4, fabric_llpp2_wdata_s_o5, fabric_llpp2_wdata_s_o6, fabric_llpp2_wdata_s_o7, fabric_llpp2_wdata_s_o8, fabric_llpp2_wdata_s_o9, fabric_llpp2_wdata_s_o10, fabric_llpp2_wdata_s_o11, fabric_llpp2_wdata_s_o12, fabric_llpp2_wdata_s_o13, fabric_llpp2_wdata_s_o14, fabric_llpp2_wdata_s_o15, fabric_llpp2_wdata_s_o16, fabric_llpp2_wdata_s_o17, fabric_llpp2_wdata_s_o18, fabric_llpp2_wdata_s_o19
-, fabric_llpp2_wdata_s_o20, fabric_llpp2_wdata_s_o21, fabric_llpp2_wdata_s_o22, fabric_llpp2_wdata_s_o23, fabric_llpp2_wdata_s_o24, fabric_llpp2_wdata_s_o25, fabric_llpp2_wdata_s_o26, fabric_llpp2_wdata_s_o27, fabric_llpp2_wdata_s_o28, fabric_llpp2_wdata_s_o29, fabric_llpp2_wdata_s_o30, fabric_llpp2_wdata_s_o31, fabric_llpp2_wdata_s_o32, fabric_llpp2_wlast_s_o, fabric_llpp2_wstrb_s_o1, fabric_llpp2_wstrb_s_o2, fabric_llpp2_wstrb_s_o3, fabric_llpp2_wstrb_s_o4, fabric_llpp2_wvalid_s_o, fabric_llpp2_arready_s_i, fabric_llpp2_awready_s_i
-, fabric_llpp2_bid_s_i1, fabric_llpp2_bid_s_i2, fabric_llpp2_bid_s_i3, fabric_llpp2_bid_s_i4, fabric_llpp2_bid_s_i5, fabric_llpp2_bid_s_i6, fabric_llpp2_bid_s_i7, fabric_llpp2_bid_s_i8, fabric_llpp2_bid_s_i9, fabric_llpp2_bid_s_i10, fabric_llpp2_bid_s_i11, fabric_llpp2_bid_s_i12, fabric_llpp2_bresp_s_i1, fabric_llpp2_bresp_s_i2, fabric_llpp2_bvalid_s_i, fabric_llpp2_rdata_s_i1, fabric_llpp2_rdata_s_i2, fabric_llpp2_rdata_s_i3, fabric_llpp2_rdata_s_i4, fabric_llpp2_rdata_s_i5, fabric_llpp2_rdata_s_i6
-, fabric_llpp2_rdata_s_i7, fabric_llpp2_rdata_s_i8, fabric_llpp2_rdata_s_i9, fabric_llpp2_rdata_s_i10, fabric_llpp2_rdata_s_i11, fabric_llpp2_rdata_s_i12, fabric_llpp2_rdata_s_i13, fabric_llpp2_rdata_s_i14, fabric_llpp2_rdata_s_i15, fabric_llpp2_rdata_s_i16, fabric_llpp2_rdata_s_i17, fabric_llpp2_rdata_s_i18, fabric_llpp2_rdata_s_i19, fabric_llpp2_rdata_s_i20, fabric_llpp2_rdata_s_i21, fabric_llpp2_rdata_s_i22, fabric_llpp2_rdata_s_i23, fabric_llpp2_rdata_s_i24, fabric_llpp2_rdata_s_i25, fabric_llpp2_rdata_s_i26, fabric_llpp2_rdata_s_i27
-, fabric_llpp2_rdata_s_i28, fabric_llpp2_rdata_s_i29, fabric_llpp2_rdata_s_i30, fabric_llpp2_rdata_s_i31, fabric_llpp2_rdata_s_i32, fabric_llpp2_rid_s_i1, fabric_llpp2_rid_s_i2, fabric_llpp2_rid_s_i3, fabric_llpp2_rid_s_i4, fabric_llpp2_rid_s_i5, fabric_llpp2_rid_s_i6, fabric_llpp2_rid_s_i7, fabric_llpp2_rid_s_i8, fabric_llpp2_rid_s_i9, fabric_llpp2_rid_s_i10, fabric_llpp2_rid_s_i11, fabric_llpp2_rid_s_i12, fabric_llpp2_rlast_s_i, fabric_llpp2_rresp_s_i1, fabric_llpp2_rresp_s_i2, fabric_llpp2_rvalid_s_i
-, fabric_llpp2_wready_s_i, fabric_llpp3_araddr_s_o1, fabric_llpp3_araddr_s_o2, fabric_llpp3_araddr_s_o3, fabric_llpp3_araddr_s_o4, fabric_llpp3_araddr_s_o5, fabric_llpp3_araddr_s_o6, fabric_llpp3_araddr_s_o7, fabric_llpp3_araddr_s_o8, fabric_llpp3_araddr_s_o9, fabric_llpp3_araddr_s_o10, fabric_llpp3_araddr_s_o11, fabric_llpp3_araddr_s_o12, fabric_llpp3_araddr_s_o13, fabric_llpp3_araddr_s_o14, fabric_llpp3_araddr_s_o15, fabric_llpp3_araddr_s_o16, fabric_llpp3_araddr_s_o17, fabric_llpp3_araddr_s_o18, fabric_llpp3_araddr_s_o19, fabric_llpp3_araddr_s_o20
-, fabric_llpp3_araddr_s_o21, fabric_llpp3_araddr_s_o22, fabric_llpp3_araddr_s_o23, fabric_llpp3_araddr_s_o24, fabric_llpp3_araddr_s_o25, fabric_llpp3_araddr_s_o26, fabric_llpp3_araddr_s_o27, fabric_llpp3_araddr_s_o28, fabric_llpp3_araddr_s_o29, fabric_llpp3_araddr_s_o30, fabric_llpp3_araddr_s_o31, fabric_llpp3_araddr_s_o32, fabric_llpp3_arburst_s_o1, fabric_llpp3_arburst_s_o2, fabric_llpp3_arcache_s_o1, fabric_llpp3_arcache_s_o2, fabric_llpp3_arcache_s_o3, fabric_llpp3_arcache_s_o4, fabric_llpp3_arid_s_o1, fabric_llpp3_arid_s_o2, fabric_llpp3_arid_s_o3
-, fabric_llpp3_arid_s_o4, fabric_llpp3_arid_s_o5, fabric_llpp3_arid_s_o6, fabric_llpp3_arid_s_o7, fabric_llpp3_arid_s_o8, fabric_llpp3_arid_s_o9, fabric_llpp3_arid_s_o10, fabric_llpp3_arid_s_o11, fabric_llpp3_arid_s_o12, fabric_llpp3_arlen_s_o1, fabric_llpp3_arlen_s_o2, fabric_llpp3_arlen_s_o3, fabric_llpp3_arlen_s_o4, fabric_llpp3_arlen_s_o5, fabric_llpp3_arlen_s_o6, fabric_llpp3_arlen_s_o7, fabric_llpp3_arlen_s_o8, fabric_llpp3_arlock_s_o, fabric_llpp3_arprot_s_o1, fabric_llpp3_arprot_s_o2, fabric_llpp3_arprot_s_o3
-, fabric_llpp3_arqos_s_o1, fabric_llpp3_arqos_s_o2, fabric_llpp3_arqos_s_o3, fabric_llpp3_arqos_s_o4, fabric_llpp3_arsize_s_o1, fabric_llpp3_arsize_s_o2, fabric_llpp3_arsize_s_o3, fabric_llpp3_arvalid_s_o, fabric_llpp3_awaddr_s_o1, fabric_llpp3_awaddr_s_o2, fabric_llpp3_awaddr_s_o3, fabric_llpp3_awaddr_s_o4, fabric_llpp3_awaddr_s_o5, fabric_llpp3_awaddr_s_o6, fabric_llpp3_awaddr_s_o7, fabric_llpp3_awaddr_s_o8, fabric_llpp3_awaddr_s_o9, fabric_llpp3_awaddr_s_o10, fabric_llpp3_awaddr_s_o11, fabric_llpp3_awaddr_s_o12, fabric_llpp3_awaddr_s_o13
-, fabric_llpp3_awaddr_s_o14, fabric_llpp3_awaddr_s_o15, fabric_llpp3_awaddr_s_o16, fabric_llpp3_awaddr_s_o17, fabric_llpp3_awaddr_s_o18, fabric_llpp3_awaddr_s_o19, fabric_llpp3_awaddr_s_o20, fabric_llpp3_awaddr_s_o21, fabric_llpp3_awaddr_s_o22, fabric_llpp3_awaddr_s_o23, fabric_llpp3_awaddr_s_o24, fabric_llpp3_awaddr_s_o25, fabric_llpp3_awaddr_s_o26, fabric_llpp3_awaddr_s_o27, fabric_llpp3_awaddr_s_o28, fabric_llpp3_awaddr_s_o29, fabric_llpp3_awaddr_s_o30, fabric_llpp3_awaddr_s_o31, fabric_llpp3_awaddr_s_o32, fabric_llpp3_awburst_s_o1, fabric_llpp3_awburst_s_o2
-, fabric_llpp3_awcache_s_o1, fabric_llpp3_awcache_s_o2, fabric_llpp3_awcache_s_o3, fabric_llpp3_awcache_s_o4, fabric_llpp3_awid_s_o1, fabric_llpp3_awid_s_o2, fabric_llpp3_awid_s_o3, fabric_llpp3_awid_s_o4, fabric_llpp3_awid_s_o5, fabric_llpp3_awid_s_o6, fabric_llpp3_awid_s_o7, fabric_llpp3_awid_s_o8, fabric_llpp3_awid_s_o9, fabric_llpp3_awid_s_o10, fabric_llpp3_awid_s_o11, fabric_llpp3_awid_s_o12, fabric_llpp3_awlen_s_o1, fabric_llpp3_awlen_s_o2, fabric_llpp3_awlen_s_o3, fabric_llpp3_awlen_s_o4, fabric_llpp3_awlen_s_o5
-, fabric_llpp3_awlen_s_o6, fabric_llpp3_awlen_s_o7, fabric_llpp3_awlen_s_o8, fabric_llpp3_awlock_s_o, fabric_llpp3_awprot_s_o1, fabric_llpp3_awprot_s_o2, fabric_llpp3_awprot_s_o3, fabric_llpp3_awqos_s_o1, fabric_llpp3_awqos_s_o2, fabric_llpp3_awqos_s_o3, fabric_llpp3_awqos_s_o4, fabric_llpp3_awsize_s_o1, fabric_llpp3_awsize_s_o2, fabric_llpp3_awsize_s_o3, fabric_llpp3_awvalid_s_o, fabric_llpp3_bready_s_o, fabric_llpp3_rready_s_o, fabric_llpp3_wdata_s_o1, fabric_llpp3_wdata_s_o2, fabric_llpp3_wdata_s_o3, fabric_llpp3_wdata_s_o4
-, fabric_llpp3_wdata_s_o5, fabric_llpp3_wdata_s_o6, fabric_llpp3_wdata_s_o7, fabric_llpp3_wdata_s_o8, fabric_llpp3_wdata_s_o9, fabric_llpp3_wdata_s_o10, fabric_llpp3_wdata_s_o11, fabric_llpp3_wdata_s_o12, fabric_llpp3_wdata_s_o13, fabric_llpp3_wdata_s_o14, fabric_llpp3_wdata_s_o15, fabric_llpp3_wdata_s_o16, fabric_llpp3_wdata_s_o17, fabric_llpp3_wdata_s_o18, fabric_llpp3_wdata_s_o19, fabric_llpp3_wdata_s_o20, fabric_llpp3_wdata_s_o21, fabric_llpp3_wdata_s_o22, fabric_llpp3_wdata_s_o23, fabric_llpp3_wdata_s_o24, fabric_llpp3_wdata_s_o25
-, fabric_llpp3_wdata_s_o26, fabric_llpp3_wdata_s_o27, fabric_llpp3_wdata_s_o28, fabric_llpp3_wdata_s_o29, fabric_llpp3_wdata_s_o30, fabric_llpp3_wdata_s_o31, fabric_llpp3_wdata_s_o32, fabric_llpp3_wlast_s_o, fabric_llpp3_wstrb_s_o1, fabric_llpp3_wstrb_s_o2, fabric_llpp3_wstrb_s_o3, fabric_llpp3_wstrb_s_o4, fabric_llpp3_wvalid_s_o, fabric_llpp3_arready_s_i, fabric_llpp3_awready_s_i, fabric_llpp3_bid_s_i1, fabric_llpp3_bid_s_i2, fabric_llpp3_bid_s_i3, fabric_llpp3_bid_s_i4, fabric_llpp3_bid_s_i5, fabric_llpp3_bid_s_i6
-, fabric_llpp3_bid_s_i7, fabric_llpp3_bid_s_i8, fabric_llpp3_bid_s_i9, fabric_llpp3_bid_s_i10, fabric_llpp3_bid_s_i11, fabric_llpp3_bid_s_i12, fabric_llpp3_bresp_s_i1, fabric_llpp3_bresp_s_i2, fabric_llpp3_bvalid_s_i, fabric_llpp3_rdata_s_i1, fabric_llpp3_rdata_s_i2, fabric_llpp3_rdata_s_i3, fabric_llpp3_rdata_s_i4, fabric_llpp3_rdata_s_i5, fabric_llpp3_rdata_s_i6, fabric_llpp3_rdata_s_i7, fabric_llpp3_rdata_s_i8, fabric_llpp3_rdata_s_i9, fabric_llpp3_rdata_s_i10, fabric_llpp3_rdata_s_i11, fabric_llpp3_rdata_s_i12
-, fabric_llpp3_rdata_s_i13, fabric_llpp3_rdata_s_i14, fabric_llpp3_rdata_s_i15, fabric_llpp3_rdata_s_i16, fabric_llpp3_rdata_s_i17, fabric_llpp3_rdata_s_i18, fabric_llpp3_rdata_s_i19, fabric_llpp3_rdata_s_i20, fabric_llpp3_rdata_s_i21, fabric_llpp3_rdata_s_i22, fabric_llpp3_rdata_s_i23, fabric_llpp3_rdata_s_i24, fabric_llpp3_rdata_s_i25, fabric_llpp3_rdata_s_i26, fabric_llpp3_rdata_s_i27, fabric_llpp3_rdata_s_i28, fabric_llpp3_rdata_s_i29, fabric_llpp3_rdata_s_i30, fabric_llpp3_rdata_s_i31, fabric_llpp3_rdata_s_i32, fabric_llpp3_rid_s_i1
-, fabric_llpp3_rid_s_i2, fabric_llpp3_rid_s_i3, fabric_llpp3_rid_s_i4, fabric_llpp3_rid_s_i5, fabric_llpp3_rid_s_i6, fabric_llpp3_rid_s_i7, fabric_llpp3_rid_s_i8, fabric_llpp3_rid_s_i9, fabric_llpp3_rid_s_i10, fabric_llpp3_rid_s_i11, fabric_llpp3_rid_s_i12, fabric_llpp3_rlast_s_i, fabric_llpp3_rresp_s_i1, fabric_llpp3_rresp_s_i2, fabric_llpp3_rvalid_s_i, fabric_llpp3_wready_s_i, fabric_qos_pprdata_o1, fabric_qos_pprdata_o2, fabric_qos_pprdata_o3, fabric_qos_pprdata_o4, fabric_qos_pprdata_o5
-, fabric_qos_pprdata_o6, fabric_qos_pprdata_o7, fabric_qos_pprdata_o8, fabric_qos_pprdata_o9, fabric_qos_pprdata_o10, fabric_qos_pprdata_o11, fabric_qos_pprdata_o12, fabric_qos_pprdata_o13, fabric_qos_pprdata_o14, fabric_qos_pprdata_o15, fabric_qos_pprdata_o16, fabric_qos_pprdata_o17, fabric_qos_pprdata_o18, fabric_qos_pprdata_o19, fabric_qos_pprdata_o20, fabric_qos_pprdata_o21, fabric_qos_pprdata_o22, fabric_qos_pprdata_o23, fabric_qos_pprdata_o24, fabric_qos_pprdata_o25, fabric_qos_pprdata_o26
-, fabric_qos_pprdata_o27, fabric_qos_pprdata_o28, fabric_qos_pprdata_o29, fabric_qos_pprdata_o30, fabric_qos_pprdata_o31, fabric_qos_pprdata_o32, fabric_qos_ppready_o, fabric_qos_ppslverr_o, fabric_qos_pclk_i, fabric_qos_ppaddr_i1, fabric_qos_ppaddr_i2, fabric_qos_ppaddr_i3, fabric_qos_ppaddr_i4, fabric_qos_ppaddr_i5, fabric_qos_ppaddr_i6, fabric_qos_ppaddr_i7, fabric_qos_ppaddr_i8, fabric_qos_ppaddr_i9, fabric_qos_ppaddr_i10, fabric_qos_ppaddr_i11, fabric_qos_ppaddr_i12
-, fabric_qos_ppaddr_i13, fabric_qos_ppaddr_i14, fabric_qos_ppaddr_i15, fabric_qos_ppaddr_i16, fabric_qos_ppaddr_i17, fabric_qos_ppaddr_i18, fabric_qos_ppaddr_i19, fabric_qos_ppaddr_i20, fabric_qos_ppaddr_i21, fabric_qos_ppaddr_i22, fabric_qos_ppaddr_i23, fabric_qos_ppaddr_i24, fabric_qos_ppaddr_i25, fabric_qos_ppaddr_i26, fabric_qos_ppaddr_i27, fabric_qos_ppaddr_i28, fabric_qos_ppaddr_i29, fabric_qos_ppaddr_i30, fabric_qos_ppaddr_i31, fabric_qos_ppaddr_i32, fabric_qos_ppenable_i
-, fabric_qos_ppwdata_i1, fabric_qos_ppwdata_i2, fabric_qos_ppwdata_i3, fabric_qos_ppwdata_i4, fabric_qos_ppwdata_i5, fabric_qos_ppwdata_i6, fabric_qos_ppwdata_i7, fabric_qos_ppwdata_i8, fabric_qos_ppwdata_i9, fabric_qos_ppwdata_i10, fabric_qos_ppwdata_i11, fabric_qos_ppwdata_i12, fabric_qos_ppwdata_i13, fabric_qos_ppwdata_i14, fabric_qos_ppwdata_i15, fabric_qos_ppwdata_i16, fabric_qos_ppwdata_i17, fabric_qos_ppwdata_i18, fabric_qos_ppwdata_i19, fabric_qos_ppwdata_i20, fabric_qos_ppwdata_i21
-, fabric_qos_ppwdata_i22, fabric_qos_ppwdata_i23, fabric_qos_ppwdata_i24, fabric_qos_ppwdata_i25, fabric_qos_ppwdata_i26, fabric_qos_ppwdata_i27, fabric_qos_ppwdata_i28, fabric_qos_ppwdata_i29, fabric_qos_ppwdata_i30, fabric_qos_ppwdata_i31, fabric_qos_ppwdata_i32, fabric_qos_ppwrite_i, fabric_qos_presetn_i, fabric_qos_psel_i, fabric_tnd_hssl_flushin_o, fabric_tnd_hssl_trigin_o, fabric_tnd_fpga_apb_master_paddr_o1, fabric_tnd_fpga_apb_master_paddr_o2, fabric_tnd_fpga_apb_master_paddr_o3, fabric_tnd_fpga_apb_master_paddr_o4, fabric_tnd_fpga_apb_master_paddr_o5
-, fabric_tnd_fpga_apb_master_paddr_o6, fabric_tnd_fpga_apb_master_paddr_o7, fabric_tnd_fpga_apb_master_paddr_o8, fabric_tnd_fpga_apb_master_paddr_o9, fabric_tnd_fpga_apb_master_paddr_o10, fabric_tnd_fpga_apb_master_paddr_o11, fabric_tnd_fpga_apb_master_paddr_o12, fabric_tnd_fpga_apb_master_paddr_o13, fabric_tnd_fpga_apb_master_paddr_o14, fabric_tnd_fpga_apb_master_paddr_o15, fabric_tnd_fpga_apb_master_paddr_o16, fabric_tnd_fpga_apb_master_paddr_o17, fabric_tnd_fpga_apb_master_paddr_o18, fabric_tnd_fpga_apb_master_paddr_o19, fabric_tnd_fpga_apb_master_paddr_o20, fabric_tnd_fpga_apb_master_paddr_o21, fabric_tnd_fpga_apb_master_paddr_o22, fabric_tnd_fpga_apb_master_paddr_o23, fabric_tnd_fpga_apb_master_paddr_o24, fabric_tnd_fpga_apb_master_paddr_o25, fabric_tnd_fpga_apb_master_paddr_o26
-, fabric_tnd_fpga_apb_master_paddr_o27, fabric_tnd_fpga_apb_master_paddr_o28, fabric_tnd_fpga_apb_master_paddr_o29, fabric_tnd_fpga_apb_master_paddr_o30, fabric_tnd_fpga_apb_master_paddr_o31, fabric_tnd_fpga_apb_master_paddr_o32, fabric_tnd_fpga_apb_master_penable_o, fabric_tnd_fpga_apb_master_psel_o, fabric_tnd_fpga_apb_master_pwdata_o1, fabric_tnd_fpga_apb_master_pwdata_o2, fabric_tnd_fpga_apb_master_pwdata_o3, fabric_tnd_fpga_apb_master_pwdata_o4, fabric_tnd_fpga_apb_master_pwdata_o5, fabric_tnd_fpga_apb_master_pwdata_o6, fabric_tnd_fpga_apb_master_pwdata_o7, fabric_tnd_fpga_apb_master_pwdata_o8, fabric_tnd_fpga_apb_master_pwdata_o9, fabric_tnd_fpga_apb_master_pwdata_o10, fabric_tnd_fpga_apb_master_pwdata_o11, fabric_tnd_fpga_apb_master_pwdata_o12, fabric_tnd_fpga_apb_master_pwdata_o13
-, fabric_tnd_fpga_apb_master_pwdata_o14, fabric_tnd_fpga_apb_master_pwdata_o15, fabric_tnd_fpga_apb_master_pwdata_o16, fabric_tnd_fpga_apb_master_pwdata_o17, fabric_tnd_fpga_apb_master_pwdata_o18, fabric_tnd_fpga_apb_master_pwdata_o19, fabric_tnd_fpga_apb_master_pwdata_o20, fabric_tnd_fpga_apb_master_pwdata_o21, fabric_tnd_fpga_apb_master_pwdata_o22, fabric_tnd_fpga_apb_master_pwdata_o23, fabric_tnd_fpga_apb_master_pwdata_o24, fabric_tnd_fpga_apb_master_pwdata_o25, fabric_tnd_fpga_apb_master_pwdata_o26, fabric_tnd_fpga_apb_master_pwdata_o27, fabric_tnd_fpga_apb_master_pwdata_o28, fabric_tnd_fpga_apb_master_pwdata_o29, fabric_tnd_fpga_apb_master_pwdata_o30, fabric_tnd_fpga_apb_master_pwdata_o31, fabric_tnd_fpga_apb_master_pwdata_o32, fabric_tnd_fpga_apb_master_pwrite_o, fabric_tnd_fpga_atb_master_afvalid_o
-, fabric_tnd_fpga_atb_master_atready_o, fabric_tnd_fpga_atb_master_syncreq_o, fabric_tnd_hssl_apb_master_paddr_o1, fabric_tnd_hssl_apb_master_paddr_o2, fabric_tnd_hssl_apb_master_paddr_o3, fabric_tnd_hssl_apb_master_paddr_o4, fabric_tnd_hssl_apb_master_paddr_o5, fabric_tnd_hssl_apb_master_paddr_o6, fabric_tnd_hssl_apb_master_paddr_o7, fabric_tnd_hssl_apb_master_paddr_o8, fabric_tnd_hssl_apb_master_paddr_o9, fabric_tnd_hssl_apb_master_paddr_o10, fabric_tnd_hssl_apb_master_paddr_o11, fabric_tnd_hssl_apb_master_paddr_o12, fabric_tnd_hssl_apb_master_paddr_o13, fabric_tnd_hssl_apb_master_paddr_o14, fabric_tnd_hssl_apb_master_paddr_o15, fabric_tnd_hssl_apb_master_paddr_o16, fabric_tnd_hssl_apb_master_paddr_o17, fabric_tnd_hssl_apb_master_paddr_o18, fabric_tnd_hssl_apb_master_paddr_o19
-, fabric_tnd_hssl_apb_master_paddr_o20, fabric_tnd_hssl_apb_master_paddr_o21, fabric_tnd_hssl_apb_master_paddr_o22, fabric_tnd_hssl_apb_master_paddr_o23, fabric_tnd_hssl_apb_master_paddr_o24, fabric_tnd_hssl_apb_master_paddr_o25, fabric_tnd_hssl_apb_master_paddr_o26, fabric_tnd_hssl_apb_master_paddr_o27, fabric_tnd_hssl_apb_master_paddr_o28, fabric_tnd_hssl_apb_master_paddr_o29, fabric_tnd_hssl_apb_master_paddr_o30, fabric_tnd_hssl_apb_master_paddr_o31, fabric_tnd_hssl_apb_master_paddr_o32, fabric_tnd_hssl_apb_master_penable_o, fabric_tnd_hssl_apb_master_psel_o, fabric_tnd_hssl_apb_master_pwdata_o1, fabric_tnd_hssl_apb_master_pwdata_o2, fabric_tnd_hssl_apb_master_pwdata_o3, fabric_tnd_hssl_apb_master_pwdata_o4, fabric_tnd_hssl_apb_master_pwdata_o5, fabric_tnd_hssl_apb_master_pwdata_o6
-, fabric_tnd_hssl_apb_master_pwdata_o7, fabric_tnd_hssl_apb_master_pwdata_o8, fabric_tnd_hssl_apb_master_pwdata_o9, fabric_tnd_hssl_apb_master_pwdata_o10, fabric_tnd_hssl_apb_master_pwdata_o11, fabric_tnd_hssl_apb_master_pwdata_o12, fabric_tnd_hssl_apb_master_pwdata_o13, fabric_tnd_hssl_apb_master_pwdata_o14, fabric_tnd_hssl_apb_master_pwdata_o15, fabric_tnd_hssl_apb_master_pwdata_o16, fabric_tnd_hssl_apb_master_pwdata_o17, fabric_tnd_hssl_apb_master_pwdata_o18, fabric_tnd_hssl_apb_master_pwdata_o19, fabric_tnd_hssl_apb_master_pwdata_o20, fabric_tnd_hssl_apb_master_pwdata_o21, fabric_tnd_hssl_apb_master_pwdata_o22, fabric_tnd_hssl_apb_master_pwdata_o23, fabric_tnd_hssl_apb_master_pwdata_o24, fabric_tnd_hssl_apb_master_pwdata_o25, fabric_tnd_hssl_apb_master_pwdata_o26, fabric_tnd_hssl_apb_master_pwdata_o27
-, fabric_tnd_hssl_apb_master_pwdata_o28, fabric_tnd_hssl_apb_master_pwdata_o29, fabric_tnd_hssl_apb_master_pwdata_o30, fabric_tnd_hssl_apb_master_pwdata_o31, fabric_tnd_hssl_apb_master_pwdata_o32, fabric_tnd_hssl_apb_master_pwrite_o, fabric_tnd_hssl_atb_master_afready_o, fabric_tnd_hssl_atb_master_atbytes_o1, fabric_tnd_hssl_atb_master_atbytes_o2, fabric_tnd_hssl_atb_master_atbytes_o3, fabric_tnd_hssl_atb_master_atbytes_o4, fabric_tnd_hssl_atb_master_atdata_o1, fabric_tnd_hssl_atb_master_atdata_o2, fabric_tnd_hssl_atb_master_atdata_o3, fabric_tnd_hssl_atb_master_atdata_o4, fabric_tnd_hssl_atb_master_atdata_o5, fabric_tnd_hssl_atb_master_atdata_o6, fabric_tnd_hssl_atb_master_atdata_o7, fabric_tnd_hssl_atb_master_atdata_o8, fabric_tnd_hssl_atb_master_atdata_o9, fabric_tnd_hssl_atb_master_atdata_o10
-, fabric_tnd_hssl_atb_master_atdata_o11, fabric_tnd_hssl_atb_master_atdata_o12, fabric_tnd_hssl_atb_master_atdata_o13, fabric_tnd_hssl_atb_master_atdata_o14, fabric_tnd_hssl_atb_master_atdata_o15, fabric_tnd_hssl_atb_master_atdata_o16, fabric_tnd_hssl_atb_master_atdata_o17, fabric_tnd_hssl_atb_master_atdata_o18, fabric_tnd_hssl_atb_master_atdata_o19, fabric_tnd_hssl_atb_master_atdata_o20, fabric_tnd_hssl_atb_master_atdata_o21, fabric_tnd_hssl_atb_master_atdata_o22, fabric_tnd_hssl_atb_master_atdata_o23, fabric_tnd_hssl_atb_master_atdata_o24, fabric_tnd_hssl_atb_master_atdata_o25, fabric_tnd_hssl_atb_master_atdata_o26, fabric_tnd_hssl_atb_master_atdata_o27, fabric_tnd_hssl_atb_master_atdata_o28, fabric_tnd_hssl_atb_master_atdata_o29, fabric_tnd_hssl_atb_master_atdata_o30, fabric_tnd_hssl_atb_master_atdata_o31
-, fabric_tnd_hssl_atb_master_atdata_o32, fabric_tnd_hssl_atb_master_atdata_o33, fabric_tnd_hssl_atb_master_atdata_o34, fabric_tnd_hssl_atb_master_atdata_o35, fabric_tnd_hssl_atb_master_atdata_o36, fabric_tnd_hssl_atb_master_atdata_o37, fabric_tnd_hssl_atb_master_atdata_o38, fabric_tnd_hssl_atb_master_atdata_o39, fabric_tnd_hssl_atb_master_atdata_o40, fabric_tnd_hssl_atb_master_atdata_o41, fabric_tnd_hssl_atb_master_atdata_o42, fabric_tnd_hssl_atb_master_atdata_o43, fabric_tnd_hssl_atb_master_atdata_o44, fabric_tnd_hssl_atb_master_atdata_o45, fabric_tnd_hssl_atb_master_atdata_o46, fabric_tnd_hssl_atb_master_atdata_o47, fabric_tnd_hssl_atb_master_atdata_o48, fabric_tnd_hssl_atb_master_atdata_o49, fabric_tnd_hssl_atb_master_atdata_o50, fabric_tnd_hssl_atb_master_atdata_o51, fabric_tnd_hssl_atb_master_atdata_o52
-, fabric_tnd_hssl_atb_master_atdata_o53, fabric_tnd_hssl_atb_master_atdata_o54, fabric_tnd_hssl_atb_master_atdata_o55, fabric_tnd_hssl_atb_master_atdata_o56, fabric_tnd_hssl_atb_master_atdata_o57, fabric_tnd_hssl_atb_master_atdata_o58, fabric_tnd_hssl_atb_master_atdata_o59, fabric_tnd_hssl_atb_master_atdata_o60, fabric_tnd_hssl_atb_master_atdata_o61, fabric_tnd_hssl_atb_master_atdata_o62, fabric_tnd_hssl_atb_master_atdata_o63, fabric_tnd_hssl_atb_master_atdata_o64, fabric_tnd_hssl_atb_master_atdata_o65, fabric_tnd_hssl_atb_master_atdata_o66, fabric_tnd_hssl_atb_master_atdata_o67, fabric_tnd_hssl_atb_master_atdata_o68, fabric_tnd_hssl_atb_master_atdata_o69, fabric_tnd_hssl_atb_master_atdata_o70, fabric_tnd_hssl_atb_master_atdata_o71, fabric_tnd_hssl_atb_master_atdata_o72, fabric_tnd_hssl_atb_master_atdata_o73
-, fabric_tnd_hssl_atb_master_atdata_o74, fabric_tnd_hssl_atb_master_atdata_o75, fabric_tnd_hssl_atb_master_atdata_o76, fabric_tnd_hssl_atb_master_atdata_o77, fabric_tnd_hssl_atb_master_atdata_o78, fabric_tnd_hssl_atb_master_atdata_o79, fabric_tnd_hssl_atb_master_atdata_o80, fabric_tnd_hssl_atb_master_atdata_o81, fabric_tnd_hssl_atb_master_atdata_o82, fabric_tnd_hssl_atb_master_atdata_o83, fabric_tnd_hssl_atb_master_atdata_o84, fabric_tnd_hssl_atb_master_atdata_o85, fabric_tnd_hssl_atb_master_atdata_o86, fabric_tnd_hssl_atb_master_atdata_o87, fabric_tnd_hssl_atb_master_atdata_o88, fabric_tnd_hssl_atb_master_atdata_o89, fabric_tnd_hssl_atb_master_atdata_o90, fabric_tnd_hssl_atb_master_atdata_o91, fabric_tnd_hssl_atb_master_atdata_o92, fabric_tnd_hssl_atb_master_atdata_o93, fabric_tnd_hssl_atb_master_atdata_o94
-, fabric_tnd_hssl_atb_master_atdata_o95, fabric_tnd_hssl_atb_master_atdata_o96, fabric_tnd_hssl_atb_master_atdata_o97, fabric_tnd_hssl_atb_master_atdata_o98, fabric_tnd_hssl_atb_master_atdata_o99, fabric_tnd_hssl_atb_master_atdata_o100, fabric_tnd_hssl_atb_master_atdata_o101, fabric_tnd_hssl_atb_master_atdata_o102, fabric_tnd_hssl_atb_master_atdata_o103, fabric_tnd_hssl_atb_master_atdata_o104, fabric_tnd_hssl_atb_master_atdata_o105, fabric_tnd_hssl_atb_master_atdata_o106, fabric_tnd_hssl_atb_master_atdata_o107, fabric_tnd_hssl_atb_master_atdata_o108, fabric_tnd_hssl_atb_master_atdata_o109, fabric_tnd_hssl_atb_master_atdata_o110, fabric_tnd_hssl_atb_master_atdata_o111, fabric_tnd_hssl_atb_master_atdata_o112, fabric_tnd_hssl_atb_master_atdata_o113, fabric_tnd_hssl_atb_master_atdata_o114, fabric_tnd_hssl_atb_master_atdata_o115
-, fabric_tnd_hssl_atb_master_atdata_o116, fabric_tnd_hssl_atb_master_atdata_o117, fabric_tnd_hssl_atb_master_atdata_o118, fabric_tnd_hssl_atb_master_atdata_o119, fabric_tnd_hssl_atb_master_atdata_o120, fabric_tnd_hssl_atb_master_atdata_o121, fabric_tnd_hssl_atb_master_atdata_o122, fabric_tnd_hssl_atb_master_atdata_o123, fabric_tnd_hssl_atb_master_atdata_o124, fabric_tnd_hssl_atb_master_atdata_o125, fabric_tnd_hssl_atb_master_atdata_o126, fabric_tnd_hssl_atb_master_atdata_o127, fabric_tnd_hssl_atb_master_atdata_o128, fabric_tnd_hssl_atb_master_atid_o1, fabric_tnd_hssl_atb_master_atid_o2, fabric_tnd_hssl_atb_master_atid_o3, fabric_tnd_hssl_atb_master_atid_o4, fabric_tnd_hssl_atb_master_atid_o5, fabric_tnd_hssl_atb_master_atid_o6, fabric_tnd_hssl_atb_master_atid_o7, fabric_tnd_hssl_atb_master_atvalid_o
-, fabric_tnd_trace_clk_traceoutportintf_o, fabric_tnd_trace_ctl_traceoutportintf_o, fabric_tnd_trace_data_traceoutportintf_o1, fabric_tnd_trace_data_traceoutportintf_o2, fabric_tnd_trace_data_traceoutportintf_o3, fabric_tnd_trace_data_traceoutportintf_o4, fabric_tnd_trace_data_traceoutportintf_o5, fabric_tnd_trace_data_traceoutportintf_o6, fabric_tnd_trace_data_traceoutportintf_o7, fabric_tnd_trace_data_traceoutportintf_o8, fabric_tnd_trace_data_traceoutportintf_o9, fabric_tnd_trace_data_traceoutportintf_o10, fabric_tnd_trace_data_traceoutportintf_o11, fabric_tnd_trace_data_traceoutportintf_o12, fabric_tnd_trace_data_traceoutportintf_o13, fabric_tnd_trace_data_traceoutportintf_o14, fabric_tnd_trace_data_traceoutportintf_o15, fabric_tnd_trace_data_traceoutportintf_o16, fabric_tnd_trace_data_traceoutportintf_o17, fabric_tnd_trace_data_traceoutportintf_o18, fabric_tnd_trace_data_traceoutportintf_o19
-, fabric_tnd_trace_data_traceoutportintf_o20, fabric_tnd_trace_data_traceoutportintf_o21, fabric_tnd_trace_data_traceoutportintf_o22, fabric_tnd_trace_data_traceoutportintf_o23, fabric_tnd_trace_data_traceoutportintf_o24, fabric_tnd_trace_data_traceoutportintf_o25, fabric_tnd_trace_data_traceoutportintf_o26, fabric_tnd_trace_data_traceoutportintf_o27, fabric_tnd_trace_data_traceoutportintf_o28, fabric_tnd_trace_data_traceoutportintf_o29, fabric_tnd_trace_data_traceoutportintf_o30, fabric_tnd_trace_data_traceoutportintf_o31, fabric_tnd_trace_data_traceoutportintf_o32, fabric_tsvalue_tsgen_fpga_o1, fabric_tsvalue_tsgen_fpga_o2, fabric_tsvalue_tsgen_fpga_o3, fabric_tsvalue_tsgen_fpga_o4, fabric_tsvalue_tsgen_fpga_o5, fabric_tsvalue_tsgen_fpga_o6, fabric_tsvalue_tsgen_fpga_o7, fabric_tsvalue_tsgen_fpga_o8
-, fabric_tsvalue_tsgen_fpga_o9, fabric_tsvalue_tsgen_fpga_o10, fabric_tsvalue_tsgen_fpga_o11, fabric_tsvalue_tsgen_fpga_o12, fabric_tsvalue_tsgen_fpga_o13, fabric_tsvalue_tsgen_fpga_o14, fabric_tsvalue_tsgen_fpga_o15, fabric_tsvalue_tsgen_fpga_o16, fabric_tsvalue_tsgen_fpga_o17, fabric_tsvalue_tsgen_fpga_o18, fabric_tsvalue_tsgen_fpga_o19, fabric_tsvalue_tsgen_fpga_o20, fabric_tsvalue_tsgen_fpga_o21, fabric_tsvalue_tsgen_fpga_o22, fabric_tsvalue_tsgen_fpga_o23, fabric_tsvalue_tsgen_fpga_o24, fabric_tsvalue_tsgen_fpga_o25, fabric_tsvalue_tsgen_fpga_o26, fabric_tsvalue_tsgen_fpga_o27, fabric_tsvalue_tsgen_fpga_o28, fabric_tsvalue_tsgen_fpga_o29
-, fabric_tsvalue_tsgen_fpga_o30, fabric_tsvalue_tsgen_fpga_o31, fabric_tsvalue_tsgen_fpga_o32, fabric_tsvalue_tsgen_fpga_o33, fabric_tsvalue_tsgen_fpga_o34, fabric_tsvalue_tsgen_fpga_o35, fabric_tsvalue_tsgen_fpga_o36, fabric_tsvalue_tsgen_fpga_o37, fabric_tsvalue_tsgen_fpga_o38, fabric_tsvalue_tsgen_fpga_o39, fabric_tsvalue_tsgen_fpga_o40, fabric_tsvalue_tsgen_fpga_o41, fabric_tsvalue_tsgen_fpga_o42, fabric_tsvalue_tsgen_fpga_o43, fabric_tsvalue_tsgen_fpga_o44, fabric_tsvalue_tsgen_fpga_o45, fabric_tsvalue_tsgen_fpga_o46, fabric_tsvalue_tsgen_fpga_o47, fabric_tsvalue_tsgen_fpga_o48, fabric_tsvalue_tsgen_fpga_o49, fabric_tsvalue_tsgen_fpga_o50
-, fabric_tsvalue_tsgen_fpga_o51, fabric_tsvalue_tsgen_fpga_o52, fabric_tsvalue_tsgen_fpga_o53, fabric_tsvalue_tsgen_fpga_o54, fabric_tsvalue_tsgen_fpga_o55, fabric_tsvalue_tsgen_fpga_o56, fabric_tsvalue_tsgen_fpga_o57, fabric_tsvalue_tsgen_fpga_o58, fabric_tsvalue_tsgen_fpga_o59, fabric_tsvalue_tsgen_fpga_o60, fabric_tsvalue_tsgen_fpga_o61, fabric_tsvalue_tsgen_fpga_o62, fabric_tsvalue_tsgen_fpga_o63, fabric_tsvalue_tsgen_fpga_o64, fabric_tnd_fpga_apb_master_prdata_i1, fabric_tnd_fpga_apb_master_prdata_i2, fabric_tnd_fpga_apb_master_prdata_i3, fabric_tnd_fpga_apb_master_prdata_i4, fabric_tnd_fpga_apb_master_prdata_i5, fabric_tnd_fpga_apb_master_prdata_i6, fabric_tnd_fpga_apb_master_prdata_i7
-, fabric_tnd_fpga_apb_master_prdata_i8, fabric_tnd_fpga_apb_master_prdata_i9, fabric_tnd_fpga_apb_master_prdata_i10, fabric_tnd_fpga_apb_master_prdata_i11, fabric_tnd_fpga_apb_master_prdata_i12, fabric_tnd_fpga_apb_master_prdata_i13, fabric_tnd_fpga_apb_master_prdata_i14, fabric_tnd_fpga_apb_master_prdata_i15, fabric_tnd_fpga_apb_master_prdata_i16, fabric_tnd_fpga_apb_master_prdata_i17, fabric_tnd_fpga_apb_master_prdata_i18, fabric_tnd_fpga_apb_master_prdata_i19, fabric_tnd_fpga_apb_master_prdata_i20, fabric_tnd_fpga_apb_master_prdata_i21, fabric_tnd_fpga_apb_master_prdata_i22, fabric_tnd_fpga_apb_master_prdata_i23, fabric_tnd_fpga_apb_master_prdata_i24, fabric_tnd_fpga_apb_master_prdata_i25, fabric_tnd_fpga_apb_master_prdata_i26, fabric_tnd_fpga_apb_master_prdata_i27, fabric_tnd_fpga_apb_master_prdata_i28
-, fabric_tnd_fpga_apb_master_prdata_i29, fabric_tnd_fpga_apb_master_prdata_i30, fabric_tnd_fpga_apb_master_prdata_i31, fabric_tnd_fpga_apb_master_prdata_i32, fabric_tnd_fpga_apb_master_pready_i, fabric_tnd_fpga_apb_master_pslverr_i, fabric_tnd_fpga_atb_master_afready_i, fabric_tnd_fpga_atb_master_atbytes_i1, fabric_tnd_fpga_atb_master_atbytes_i2, fabric_tnd_fpga_atb_master_atbytes_i3, fabric_tnd_fpga_atb_master_atbytes_i4, fabric_tnd_fpga_atb_master_atdata_i1, fabric_tnd_fpga_atb_master_atdata_i2, fabric_tnd_fpga_atb_master_atdata_i3, fabric_tnd_fpga_atb_master_atdata_i4, fabric_tnd_fpga_atb_master_atdata_i5, fabric_tnd_fpga_atb_master_atdata_i6, fabric_tnd_fpga_atb_master_atdata_i7, fabric_tnd_fpga_atb_master_atdata_i8, fabric_tnd_fpga_atb_master_atdata_i9, fabric_tnd_fpga_atb_master_atdata_i10
-, fabric_tnd_fpga_atb_master_atdata_i11, fabric_tnd_fpga_atb_master_atdata_i12, fabric_tnd_fpga_atb_master_atdata_i13, fabric_tnd_fpga_atb_master_atdata_i14, fabric_tnd_fpga_atb_master_atdata_i15, fabric_tnd_fpga_atb_master_atdata_i16, fabric_tnd_fpga_atb_master_atdata_i17, fabric_tnd_fpga_atb_master_atdata_i18, fabric_tnd_fpga_atb_master_atdata_i19, fabric_tnd_fpga_atb_master_atdata_i20, fabric_tnd_fpga_atb_master_atdata_i21, fabric_tnd_fpga_atb_master_atdata_i22, fabric_tnd_fpga_atb_master_atdata_i23, fabric_tnd_fpga_atb_master_atdata_i24, fabric_tnd_fpga_atb_master_atdata_i25, fabric_tnd_fpga_atb_master_atdata_i26, fabric_tnd_fpga_atb_master_atdata_i27, fabric_tnd_fpga_atb_master_atdata_i28, fabric_tnd_fpga_atb_master_atdata_i29, fabric_tnd_fpga_atb_master_atdata_i30, fabric_tnd_fpga_atb_master_atdata_i31
-, fabric_tnd_fpga_atb_master_atdata_i32, fabric_tnd_fpga_atb_master_atdata_i33, fabric_tnd_fpga_atb_master_atdata_i34, fabric_tnd_fpga_atb_master_atdata_i35, fabric_tnd_fpga_atb_master_atdata_i36, fabric_tnd_fpga_atb_master_atdata_i37, fabric_tnd_fpga_atb_master_atdata_i38, fabric_tnd_fpga_atb_master_atdata_i39, fabric_tnd_fpga_atb_master_atdata_i40, fabric_tnd_fpga_atb_master_atdata_i41, fabric_tnd_fpga_atb_master_atdata_i42, fabric_tnd_fpga_atb_master_atdata_i43, fabric_tnd_fpga_atb_master_atdata_i44, fabric_tnd_fpga_atb_master_atdata_i45, fabric_tnd_fpga_atb_master_atdata_i46, fabric_tnd_fpga_atb_master_atdata_i47, fabric_tnd_fpga_atb_master_atdata_i48, fabric_tnd_fpga_atb_master_atdata_i49, fabric_tnd_fpga_atb_master_atdata_i50, fabric_tnd_fpga_atb_master_atdata_i51, fabric_tnd_fpga_atb_master_atdata_i52
-, fabric_tnd_fpga_atb_master_atdata_i53, fabric_tnd_fpga_atb_master_atdata_i54, fabric_tnd_fpga_atb_master_atdata_i55, fabric_tnd_fpga_atb_master_atdata_i56, fabric_tnd_fpga_atb_master_atdata_i57, fabric_tnd_fpga_atb_master_atdata_i58, fabric_tnd_fpga_atb_master_atdata_i59, fabric_tnd_fpga_atb_master_atdata_i60, fabric_tnd_fpga_atb_master_atdata_i61, fabric_tnd_fpga_atb_master_atdata_i62, fabric_tnd_fpga_atb_master_atdata_i63, fabric_tnd_fpga_atb_master_atdata_i64, fabric_tnd_fpga_atb_master_atdata_i65, fabric_tnd_fpga_atb_master_atdata_i66, fabric_tnd_fpga_atb_master_atdata_i67, fabric_tnd_fpga_atb_master_atdata_i68, fabric_tnd_fpga_atb_master_atdata_i69, fabric_tnd_fpga_atb_master_atdata_i70, fabric_tnd_fpga_atb_master_atdata_i71, fabric_tnd_fpga_atb_master_atdata_i72, fabric_tnd_fpga_atb_master_atdata_i73
-, fabric_tnd_fpga_atb_master_atdata_i74, fabric_tnd_fpga_atb_master_atdata_i75, fabric_tnd_fpga_atb_master_atdata_i76, fabric_tnd_fpga_atb_master_atdata_i77, fabric_tnd_fpga_atb_master_atdata_i78, fabric_tnd_fpga_atb_master_atdata_i79, fabric_tnd_fpga_atb_master_atdata_i80, fabric_tnd_fpga_atb_master_atdata_i81, fabric_tnd_fpga_atb_master_atdata_i82, fabric_tnd_fpga_atb_master_atdata_i83, fabric_tnd_fpga_atb_master_atdata_i84, fabric_tnd_fpga_atb_master_atdata_i85, fabric_tnd_fpga_atb_master_atdata_i86, fabric_tnd_fpga_atb_master_atdata_i87, fabric_tnd_fpga_atb_master_atdata_i88, fabric_tnd_fpga_atb_master_atdata_i89, fabric_tnd_fpga_atb_master_atdata_i90, fabric_tnd_fpga_atb_master_atdata_i91, fabric_tnd_fpga_atb_master_atdata_i92, fabric_tnd_fpga_atb_master_atdata_i93, fabric_tnd_fpga_atb_master_atdata_i94
-, fabric_tnd_fpga_atb_master_atdata_i95, fabric_tnd_fpga_atb_master_atdata_i96, fabric_tnd_fpga_atb_master_atdata_i97, fabric_tnd_fpga_atb_master_atdata_i98, fabric_tnd_fpga_atb_master_atdata_i99, fabric_tnd_fpga_atb_master_atdata_i100, fabric_tnd_fpga_atb_master_atdata_i101, fabric_tnd_fpga_atb_master_atdata_i102, fabric_tnd_fpga_atb_master_atdata_i103, fabric_tnd_fpga_atb_master_atdata_i104, fabric_tnd_fpga_atb_master_atdata_i105, fabric_tnd_fpga_atb_master_atdata_i106, fabric_tnd_fpga_atb_master_atdata_i107, fabric_tnd_fpga_atb_master_atdata_i108, fabric_tnd_fpga_atb_master_atdata_i109, fabric_tnd_fpga_atb_master_atdata_i110, fabric_tnd_fpga_atb_master_atdata_i111, fabric_tnd_fpga_atb_master_atdata_i112, fabric_tnd_fpga_atb_master_atdata_i113, fabric_tnd_fpga_atb_master_atdata_i114, fabric_tnd_fpga_atb_master_atdata_i115
-, fabric_tnd_fpga_atb_master_atdata_i116, fabric_tnd_fpga_atb_master_atdata_i117, fabric_tnd_fpga_atb_master_atdata_i118, fabric_tnd_fpga_atb_master_atdata_i119, fabric_tnd_fpga_atb_master_atdata_i120, fabric_tnd_fpga_atb_master_atdata_i121, fabric_tnd_fpga_atb_master_atdata_i122, fabric_tnd_fpga_atb_master_atdata_i123, fabric_tnd_fpga_atb_master_atdata_i124, fabric_tnd_fpga_atb_master_atdata_i125, fabric_tnd_fpga_atb_master_atdata_i126, fabric_tnd_fpga_atb_master_atdata_i127, fabric_tnd_fpga_atb_master_atdata_i128, fabric_tnd_fpga_atb_master_atid_i1, fabric_tnd_fpga_atb_master_atid_i2, fabric_tnd_fpga_atb_master_atid_i3, fabric_tnd_fpga_atb_master_atid_i4, fabric_tnd_fpga_atb_master_atid_i5, fabric_tnd_fpga_atb_master_atid_i6, fabric_tnd_fpga_atb_master_atid_i7, fabric_tnd_fpga_atb_master_atvalid_i
-, fabric_tnd_hssl_apb_master_prdata_i1, fabric_tnd_hssl_apb_master_prdata_i2, fabric_tnd_hssl_apb_master_prdata_i3, fabric_tnd_hssl_apb_master_prdata_i4, fabric_tnd_hssl_apb_master_prdata_i5, fabric_tnd_hssl_apb_master_prdata_i6, fabric_tnd_hssl_apb_master_prdata_i7, fabric_tnd_hssl_apb_master_prdata_i8, fabric_tnd_hssl_apb_master_prdata_i9, fabric_tnd_hssl_apb_master_prdata_i10, fabric_tnd_hssl_apb_master_prdata_i11, fabric_tnd_hssl_apb_master_prdata_i12, fabric_tnd_hssl_apb_master_prdata_i13, fabric_tnd_hssl_apb_master_prdata_i14, fabric_tnd_hssl_apb_master_prdata_i15, fabric_tnd_hssl_apb_master_prdata_i16, fabric_tnd_hssl_apb_master_prdata_i17, fabric_tnd_hssl_apb_master_prdata_i18, fabric_tnd_hssl_apb_master_prdata_i19, fabric_tnd_hssl_apb_master_prdata_i20, fabric_tnd_hssl_apb_master_prdata_i21
-, fabric_tnd_hssl_apb_master_prdata_i22, fabric_tnd_hssl_apb_master_prdata_i23, fabric_tnd_hssl_apb_master_prdata_i24, fabric_tnd_hssl_apb_master_prdata_i25, fabric_tnd_hssl_apb_master_prdata_i26, fabric_tnd_hssl_apb_master_prdata_i27, fabric_tnd_hssl_apb_master_prdata_i28, fabric_tnd_hssl_apb_master_prdata_i29, fabric_tnd_hssl_apb_master_prdata_i30, fabric_tnd_hssl_apb_master_prdata_i31, fabric_tnd_hssl_apb_master_prdata_i32, fabric_tnd_hssl_apb_master_pready_i, fabric_tnd_hssl_apb_master_pslverr_i, fabric_tnd_hssl_atb_master_afvalid_i, fabric_tnd_hssl_atb_master_atready_i, fabric_tnd_hssl_atb_master_syncreq_i, fabric_watchdog0_signal_0_o, fabric_watchdog0_signal_1_o, fabric_watchdog1_signal_0_o, fabric_watchdog1_signal_1_o, fabric_watchdog2_signal_0_o
-, fabric_watchdog2_signal_1_o, fabric_watchdog3_signal_0_o, fabric_watchdog3_signal_1_o, fabric_tst_pll_lock_o1, fabric_tst_pll_lock_o2, fabric_tst_pll_lock_o3, fabric_tst_pll_lock_o4, fabric_tst_pll_lock_o5, fabric_tst_pll_lock_o6, fabric_tst_pll_lock_o7, fabric_soc_mon_sensor_alarm_o, fabric_erom_fpga_cpu0_dbgen_i, fabric_erom_fpga_cpu0_hiden_i, fabric_erom_fpga_cpu0_hniden_i, fabric_erom_fpga_cpu0_niden_i, fabric_erom_fpga_cpu1_dbgen_i, fabric_erom_fpga_cpu1_hiden_i, fabric_erom_fpga_cpu1_hniden_i, fabric_erom_fpga_cpu1_niden_i, fabric_erom_fpga_cpu2_dbgen_i, fabric_erom_fpga_cpu2_hiden_i
-, fabric_erom_fpga_cpu2_hniden_i, fabric_erom_fpga_cpu2_niden_i, fabric_erom_fpga_cpu3_dbgen_i, fabric_erom_fpga_cpu3_hiden_i, fabric_erom_fpga_cpu3_hniden_i, fabric_erom_fpga_cpu3_niden_i, fabric_erom_fpga_cs_dbgen_i, fabric_erom_fpga_cs_niden_i, fabric_erom_fpga_cs_deviceen_i, fabric_erom_fpga_cs_rst_n_i, fabric_erom_fpga_debug_en_i, fabric_enable_TMR_i1, fabric_enable_TMR_i2, fabric_enable_TMR_i3);
-    input fabric_enable_TMR_i1;
-    input fabric_enable_TMR_i2;
-    input fabric_enable_TMR_i3;
-    input fabric_erom_fpga_cpu0_dbgen_i;
-    input fabric_erom_fpga_cpu0_hiden_i;
-    input fabric_erom_fpga_cpu0_hniden_i;
-    input fabric_erom_fpga_cpu0_niden_i;
-    input fabric_erom_fpga_cpu1_dbgen_i;
-    input fabric_erom_fpga_cpu1_hiden_i;
-    input fabric_erom_fpga_cpu1_hniden_i;
-    input fabric_erom_fpga_cpu1_niden_i;
-    input fabric_erom_fpga_cpu2_dbgen_i;
-    input fabric_erom_fpga_cpu2_hiden_i;
-    input fabric_erom_fpga_cpu2_hniden_i;
-    input fabric_erom_fpga_cpu2_niden_i;
-    input fabric_erom_fpga_cpu3_dbgen_i;
-    input fabric_erom_fpga_cpu3_hiden_i;
-    input fabric_erom_fpga_cpu3_hniden_i;
-    input fabric_erom_fpga_cpu3_niden_i;
-    input fabric_erom_fpga_cs_dbgen_i;
-    input fabric_erom_fpga_cs_deviceen_i;
-    input fabric_erom_fpga_cs_niden_i;
-    input fabric_erom_fpga_cs_rst_n_i;
-    input fabric_erom_fpga_debug_en_i;
-    input fabric_fpga_araddr_axi_m1_i1;
-    input fabric_fpga_araddr_axi_m1_i10;
-    input fabric_fpga_araddr_axi_m1_i11;
-    input fabric_fpga_araddr_axi_m1_i12;
-    input fabric_fpga_araddr_axi_m1_i13;
-    input fabric_fpga_araddr_axi_m1_i14;
-    input fabric_fpga_araddr_axi_m1_i15;
-    input fabric_fpga_araddr_axi_m1_i16;
-    input fabric_fpga_araddr_axi_m1_i17;
-    input fabric_fpga_araddr_axi_m1_i18;
-    input fabric_fpga_araddr_axi_m1_i19;
-    input fabric_fpga_araddr_axi_m1_i2;
-    input fabric_fpga_araddr_axi_m1_i20;
-    input fabric_fpga_araddr_axi_m1_i21;
-    input fabric_fpga_araddr_axi_m1_i22;
-    input fabric_fpga_araddr_axi_m1_i23;
-    input fabric_fpga_araddr_axi_m1_i24;
-    input fabric_fpga_araddr_axi_m1_i25;
-    input fabric_fpga_araddr_axi_m1_i26;
-    input fabric_fpga_araddr_axi_m1_i27;
-    input fabric_fpga_araddr_axi_m1_i28;
-    input fabric_fpga_araddr_axi_m1_i29;
-    input fabric_fpga_araddr_axi_m1_i3;
-    input fabric_fpga_araddr_axi_m1_i30;
-    input fabric_fpga_araddr_axi_m1_i31;
-    input fabric_fpga_araddr_axi_m1_i32;
-    input fabric_fpga_araddr_axi_m1_i33;
-    input fabric_fpga_araddr_axi_m1_i34;
-    input fabric_fpga_araddr_axi_m1_i35;
-    input fabric_fpga_araddr_axi_m1_i36;
-    input fabric_fpga_araddr_axi_m1_i37;
-    input fabric_fpga_araddr_axi_m1_i38;
-    input fabric_fpga_araddr_axi_m1_i39;
-    input fabric_fpga_araddr_axi_m1_i4;
-    input fabric_fpga_araddr_axi_m1_i40;
-    input fabric_fpga_araddr_axi_m1_i5;
-    input fabric_fpga_araddr_axi_m1_i6;
-    input fabric_fpga_araddr_axi_m1_i7;
-    input fabric_fpga_araddr_axi_m1_i8;
-    input fabric_fpga_araddr_axi_m1_i9;
-    input fabric_fpga_araddr_axi_m2_i1;
-    input fabric_fpga_araddr_axi_m2_i10;
-    input fabric_fpga_araddr_axi_m2_i11;
-    input fabric_fpga_araddr_axi_m2_i12;
-    input fabric_fpga_araddr_axi_m2_i13;
-    input fabric_fpga_araddr_axi_m2_i14;
-    input fabric_fpga_araddr_axi_m2_i15;
-    input fabric_fpga_araddr_axi_m2_i16;
-    input fabric_fpga_araddr_axi_m2_i17;
-    input fabric_fpga_araddr_axi_m2_i18;
-    input fabric_fpga_araddr_axi_m2_i19;
-    input fabric_fpga_araddr_axi_m2_i2;
-    input fabric_fpga_araddr_axi_m2_i20;
-    input fabric_fpga_araddr_axi_m2_i21;
-    input fabric_fpga_araddr_axi_m2_i22;
-    input fabric_fpga_araddr_axi_m2_i23;
-    input fabric_fpga_araddr_axi_m2_i24;
-    input fabric_fpga_araddr_axi_m2_i25;
-    input fabric_fpga_araddr_axi_m2_i26;
-    input fabric_fpga_araddr_axi_m2_i27;
-    input fabric_fpga_araddr_axi_m2_i28;
-    input fabric_fpga_araddr_axi_m2_i29;
-    input fabric_fpga_araddr_axi_m2_i3;
-    input fabric_fpga_araddr_axi_m2_i30;
-    input fabric_fpga_araddr_axi_m2_i31;
-    input fabric_fpga_araddr_axi_m2_i32;
-    input fabric_fpga_araddr_axi_m2_i33;
-    input fabric_fpga_araddr_axi_m2_i34;
-    input fabric_fpga_araddr_axi_m2_i35;
-    input fabric_fpga_araddr_axi_m2_i36;
-    input fabric_fpga_araddr_axi_m2_i37;
-    input fabric_fpga_araddr_axi_m2_i38;
-    input fabric_fpga_araddr_axi_m2_i39;
-    input fabric_fpga_araddr_axi_m2_i4;
-    input fabric_fpga_araddr_axi_m2_i40;
-    input fabric_fpga_araddr_axi_m2_i5;
-    input fabric_fpga_araddr_axi_m2_i6;
-    input fabric_fpga_araddr_axi_m2_i7;
-    input fabric_fpga_araddr_axi_m2_i8;
-    input fabric_fpga_araddr_axi_m2_i9;
-    output fabric_fpga_araddr_axi_s1_o1;
-    output fabric_fpga_araddr_axi_s1_o10;
-    output fabric_fpga_araddr_axi_s1_o11;
-    output fabric_fpga_araddr_axi_s1_o12;
-    output fabric_fpga_araddr_axi_s1_o13;
-    output fabric_fpga_araddr_axi_s1_o14;
-    output fabric_fpga_araddr_axi_s1_o15;
-    output fabric_fpga_araddr_axi_s1_o16;
-    output fabric_fpga_araddr_axi_s1_o17;
-    output fabric_fpga_araddr_axi_s1_o18;
-    output fabric_fpga_araddr_axi_s1_o19;
-    output fabric_fpga_araddr_axi_s1_o2;
-    output fabric_fpga_araddr_axi_s1_o20;
-    output fabric_fpga_araddr_axi_s1_o21;
-    output fabric_fpga_araddr_axi_s1_o22;
-    output fabric_fpga_araddr_axi_s1_o23;
-    output fabric_fpga_araddr_axi_s1_o24;
-    output fabric_fpga_araddr_axi_s1_o25;
-    output fabric_fpga_araddr_axi_s1_o26;
-    output fabric_fpga_araddr_axi_s1_o27;
-    output fabric_fpga_araddr_axi_s1_o28;
-    output fabric_fpga_araddr_axi_s1_o29;
-    output fabric_fpga_araddr_axi_s1_o3;
-    output fabric_fpga_araddr_axi_s1_o30;
-    output fabric_fpga_araddr_axi_s1_o31;
-    output fabric_fpga_araddr_axi_s1_o32;
-    output fabric_fpga_araddr_axi_s1_o33;
-    output fabric_fpga_araddr_axi_s1_o34;
-    output fabric_fpga_araddr_axi_s1_o35;
-    output fabric_fpga_araddr_axi_s1_o36;
-    output fabric_fpga_araddr_axi_s1_o37;
-    output fabric_fpga_araddr_axi_s1_o38;
-    output fabric_fpga_araddr_axi_s1_o39;
-    output fabric_fpga_araddr_axi_s1_o4;
-    output fabric_fpga_araddr_axi_s1_o40;
-    output fabric_fpga_araddr_axi_s1_o5;
-    output fabric_fpga_araddr_axi_s1_o6;
-    output fabric_fpga_araddr_axi_s1_o7;
-    output fabric_fpga_araddr_axi_s1_o8;
-    output fabric_fpga_araddr_axi_s1_o9;
-    output fabric_fpga_araddr_axi_s2_o1;
-    output fabric_fpga_araddr_axi_s2_o10;
-    output fabric_fpga_araddr_axi_s2_o11;
-    output fabric_fpga_araddr_axi_s2_o12;
-    output fabric_fpga_araddr_axi_s2_o13;
-    output fabric_fpga_araddr_axi_s2_o14;
-    output fabric_fpga_araddr_axi_s2_o15;
-    output fabric_fpga_araddr_axi_s2_o16;
-    output fabric_fpga_araddr_axi_s2_o17;
-    output fabric_fpga_araddr_axi_s2_o18;
-    output fabric_fpga_araddr_axi_s2_o19;
-    output fabric_fpga_araddr_axi_s2_o2;
-    output fabric_fpga_araddr_axi_s2_o20;
-    output fabric_fpga_araddr_axi_s2_o21;
-    output fabric_fpga_araddr_axi_s2_o22;
-    output fabric_fpga_araddr_axi_s2_o23;
-    output fabric_fpga_araddr_axi_s2_o24;
-    output fabric_fpga_araddr_axi_s2_o25;
-    output fabric_fpga_araddr_axi_s2_o26;
-    output fabric_fpga_araddr_axi_s2_o27;
-    output fabric_fpga_araddr_axi_s2_o28;
-    output fabric_fpga_araddr_axi_s2_o29;
-    output fabric_fpga_araddr_axi_s2_o3;
-    output fabric_fpga_araddr_axi_s2_o30;
-    output fabric_fpga_araddr_axi_s2_o31;
-    output fabric_fpga_araddr_axi_s2_o32;
-    output fabric_fpga_araddr_axi_s2_o33;
-    output fabric_fpga_araddr_axi_s2_o34;
-    output fabric_fpga_araddr_axi_s2_o35;
-    output fabric_fpga_araddr_axi_s2_o36;
-    output fabric_fpga_araddr_axi_s2_o37;
-    output fabric_fpga_araddr_axi_s2_o38;
-    output fabric_fpga_araddr_axi_s2_o39;
-    output fabric_fpga_araddr_axi_s2_o4;
-    output fabric_fpga_araddr_axi_s2_o40;
-    output fabric_fpga_araddr_axi_s2_o5;
-    output fabric_fpga_araddr_axi_s2_o6;
-    output fabric_fpga_araddr_axi_s2_o7;
-    output fabric_fpga_araddr_axi_s2_o8;
-    output fabric_fpga_araddr_axi_s2_o9;
-    input fabric_fpga_arburst_axi_m1_i1;
-    input fabric_fpga_arburst_axi_m1_i2;
-    input fabric_fpga_arburst_axi_m2_i1;
-    input fabric_fpga_arburst_axi_m2_i2;
-    output fabric_fpga_arburst_axi_s1_o1;
-    output fabric_fpga_arburst_axi_s1_o2;
-    output fabric_fpga_arburst_axi_s2_o1;
-    output fabric_fpga_arburst_axi_s2_o2;
-    input fabric_fpga_arcache_axi_m1_i1;
-    input fabric_fpga_arcache_axi_m1_i2;
-    input fabric_fpga_arcache_axi_m1_i3;
-    input fabric_fpga_arcache_axi_m1_i4;
-    input fabric_fpga_arcache_axi_m2_i1;
-    input fabric_fpga_arcache_axi_m2_i2;
-    input fabric_fpga_arcache_axi_m2_i3;
-    input fabric_fpga_arcache_axi_m2_i4;
-    output fabric_fpga_arcache_axi_s1_o1;
-    output fabric_fpga_arcache_axi_s1_o2;
-    output fabric_fpga_arcache_axi_s1_o3;
-    output fabric_fpga_arcache_axi_s1_o4;
-    output fabric_fpga_arcache_axi_s2_o1;
-    output fabric_fpga_arcache_axi_s2_o2;
-    output fabric_fpga_arcache_axi_s2_o3;
-    output fabric_fpga_arcache_axi_s2_o4;
-    input fabric_fpga_arid_axi_m1_i1;
-    input fabric_fpga_arid_axi_m1_i2;
-    input fabric_fpga_arid_axi_m1_i3;
-    input fabric_fpga_arid_axi_m1_i4;
-    input fabric_fpga_arid_axi_m1_i5;
-    input fabric_fpga_arid_axi_m2_i1;
-    input fabric_fpga_arid_axi_m2_i2;
-    input fabric_fpga_arid_axi_m2_i3;
-    input fabric_fpga_arid_axi_m2_i4;
-    input fabric_fpga_arid_axi_m2_i5;
-    output fabric_fpga_arid_axi_s1_o1;
-    output fabric_fpga_arid_axi_s1_o10;
-    output fabric_fpga_arid_axi_s1_o11;
-    output fabric_fpga_arid_axi_s1_o12;
-    output fabric_fpga_arid_axi_s1_o2;
-    output fabric_fpga_arid_axi_s1_o3;
-    output fabric_fpga_arid_axi_s1_o4;
-    output fabric_fpga_arid_axi_s1_o5;
-    output fabric_fpga_arid_axi_s1_o6;
-    output fabric_fpga_arid_axi_s1_o7;
-    output fabric_fpga_arid_axi_s1_o8;
-    output fabric_fpga_arid_axi_s1_o9;
-    output fabric_fpga_arid_axi_s2_o1;
-    output fabric_fpga_arid_axi_s2_o10;
-    output fabric_fpga_arid_axi_s2_o11;
-    output fabric_fpga_arid_axi_s2_o12;
-    output fabric_fpga_arid_axi_s2_o2;
-    output fabric_fpga_arid_axi_s2_o3;
-    output fabric_fpga_arid_axi_s2_o4;
-    output fabric_fpga_arid_axi_s2_o5;
-    output fabric_fpga_arid_axi_s2_o6;
-    output fabric_fpga_arid_axi_s2_o7;
-    output fabric_fpga_arid_axi_s2_o8;
-    output fabric_fpga_arid_axi_s2_o9;
-    input fabric_fpga_arlen_axi_m1_i1;
-    input fabric_fpga_arlen_axi_m1_i2;
-    input fabric_fpga_arlen_axi_m1_i3;
-    input fabric_fpga_arlen_axi_m1_i4;
-    input fabric_fpga_arlen_axi_m1_i5;
-    input fabric_fpga_arlen_axi_m1_i6;
-    input fabric_fpga_arlen_axi_m1_i7;
-    input fabric_fpga_arlen_axi_m1_i8;
-    input fabric_fpga_arlen_axi_m2_i1;
-    input fabric_fpga_arlen_axi_m2_i2;
-    input fabric_fpga_arlen_axi_m2_i3;
-    input fabric_fpga_arlen_axi_m2_i4;
-    input fabric_fpga_arlen_axi_m2_i5;
-    input fabric_fpga_arlen_axi_m2_i6;
-    input fabric_fpga_arlen_axi_m2_i7;
-    input fabric_fpga_arlen_axi_m2_i8;
-    output fabric_fpga_arlen_axi_s1_o1;
-    output fabric_fpga_arlen_axi_s1_o2;
-    output fabric_fpga_arlen_axi_s1_o3;
-    output fabric_fpga_arlen_axi_s1_o4;
-    output fabric_fpga_arlen_axi_s1_o5;
-    output fabric_fpga_arlen_axi_s1_o6;
-    output fabric_fpga_arlen_axi_s1_o7;
-    output fabric_fpga_arlen_axi_s1_o8;
-    output fabric_fpga_arlen_axi_s2_o1;
-    output fabric_fpga_arlen_axi_s2_o2;
-    output fabric_fpga_arlen_axi_s2_o3;
-    output fabric_fpga_arlen_axi_s2_o4;
-    output fabric_fpga_arlen_axi_s2_o5;
-    output fabric_fpga_arlen_axi_s2_o6;
-    output fabric_fpga_arlen_axi_s2_o7;
-    output fabric_fpga_arlen_axi_s2_o8;
-    input fabric_fpga_arlock_axi_m1_i;
-    input fabric_fpga_arlock_axi_m2_i;
-    output fabric_fpga_arlock_axi_s1_o;
-    output fabric_fpga_arlock_axi_s2_o;
-    input fabric_fpga_arprot_axi_m1_i1;
-    input fabric_fpga_arprot_axi_m1_i2;
-    input fabric_fpga_arprot_axi_m1_i3;
-    input fabric_fpga_arprot_axi_m2_i1;
-    input fabric_fpga_arprot_axi_m2_i2;
-    input fabric_fpga_arprot_axi_m2_i3;
-    output fabric_fpga_arprot_axi_s1_o1;
-    output fabric_fpga_arprot_axi_s1_o2;
-    output fabric_fpga_arprot_axi_s1_o3;
-    output fabric_fpga_arprot_axi_s2_o1;
-    output fabric_fpga_arprot_axi_s2_o2;
-    output fabric_fpga_arprot_axi_s2_o3;
-    input fabric_fpga_arqos_axi_m1_i1;
-    input fabric_fpga_arqos_axi_m1_i2;
-    input fabric_fpga_arqos_axi_m1_i3;
-    input fabric_fpga_arqos_axi_m1_i4;
-    input fabric_fpga_arqos_axi_m2_i1;
-    input fabric_fpga_arqos_axi_m2_i2;
-    input fabric_fpga_arqos_axi_m2_i3;
-    input fabric_fpga_arqos_axi_m2_i4;
-    output fabric_fpga_arqos_axi_s1_o1;
-    output fabric_fpga_arqos_axi_s1_o2;
-    output fabric_fpga_arqos_axi_s1_o3;
-    output fabric_fpga_arqos_axi_s1_o4;
-    output fabric_fpga_arqos_axi_s2_o1;
-    output fabric_fpga_arqos_axi_s2_o2;
-    output fabric_fpga_arqos_axi_s2_o3;
-    output fabric_fpga_arqos_axi_s2_o4;
-    output fabric_fpga_arready_axi_m1_o;
-    output fabric_fpga_arready_axi_m2_o;
-    input fabric_fpga_arready_axi_s1_i;
-    input fabric_fpga_arready_axi_s2_i;
-    output fabric_fpga_arregion_axi_s1_o1;
-    output fabric_fpga_arregion_axi_s1_o2;
-    output fabric_fpga_arregion_axi_s1_o3;
-    output fabric_fpga_arregion_axi_s1_o4;
-    output fabric_fpga_arregion_axi_s2_o1;
-    output fabric_fpga_arregion_axi_s2_o2;
-    output fabric_fpga_arregion_axi_s2_o3;
-    output fabric_fpga_arregion_axi_s2_o4;
-    input fabric_fpga_arsize_axi_m1_i1;
-    input fabric_fpga_arsize_axi_m1_i2;
-    input fabric_fpga_arsize_axi_m1_i3;
-    input fabric_fpga_arsize_axi_m2_i1;
-    input fabric_fpga_arsize_axi_m2_i2;
-    input fabric_fpga_arsize_axi_m2_i3;
-    output fabric_fpga_arsize_axi_s1_o1;
-    output fabric_fpga_arsize_axi_s1_o2;
-    output fabric_fpga_arsize_axi_s1_o3;
-    output fabric_fpga_arsize_axi_s2_o1;
-    output fabric_fpga_arsize_axi_s2_o2;
-    output fabric_fpga_arsize_axi_s2_o3;
-    input fabric_fpga_arvalid_axi_m1_i;
-    input fabric_fpga_arvalid_axi_m2_i;
-    output fabric_fpga_arvalid_axi_s1_o;
-    output fabric_fpga_arvalid_axi_s2_o;
-    input fabric_fpga_awaddr_axi_m1_i1;
-    input fabric_fpga_awaddr_axi_m1_i10;
-    input fabric_fpga_awaddr_axi_m1_i11;
-    input fabric_fpga_awaddr_axi_m1_i12;
-    input fabric_fpga_awaddr_axi_m1_i13;
-    input fabric_fpga_awaddr_axi_m1_i14;
-    input fabric_fpga_awaddr_axi_m1_i15;
-    input fabric_fpga_awaddr_axi_m1_i16;
-    input fabric_fpga_awaddr_axi_m1_i17;
-    input fabric_fpga_awaddr_axi_m1_i18;
-    input fabric_fpga_awaddr_axi_m1_i19;
-    input fabric_fpga_awaddr_axi_m1_i2;
-    input fabric_fpga_awaddr_axi_m1_i20;
-    input fabric_fpga_awaddr_axi_m1_i21;
-    input fabric_fpga_awaddr_axi_m1_i22;
-    input fabric_fpga_awaddr_axi_m1_i23;
-    input fabric_fpga_awaddr_axi_m1_i24;
-    input fabric_fpga_awaddr_axi_m1_i25;
-    input fabric_fpga_awaddr_axi_m1_i26;
-    input fabric_fpga_awaddr_axi_m1_i27;
-    input fabric_fpga_awaddr_axi_m1_i28;
-    input fabric_fpga_awaddr_axi_m1_i29;
-    input fabric_fpga_awaddr_axi_m1_i3;
-    input fabric_fpga_awaddr_axi_m1_i30;
-    input fabric_fpga_awaddr_axi_m1_i31;
-    input fabric_fpga_awaddr_axi_m1_i32;
-    input fabric_fpga_awaddr_axi_m1_i33;
-    input fabric_fpga_awaddr_axi_m1_i34;
-    input fabric_fpga_awaddr_axi_m1_i35;
-    input fabric_fpga_awaddr_axi_m1_i36;
-    input fabric_fpga_awaddr_axi_m1_i37;
-    input fabric_fpga_awaddr_axi_m1_i38;
-    input fabric_fpga_awaddr_axi_m1_i39;
-    input fabric_fpga_awaddr_axi_m1_i4;
-    input fabric_fpga_awaddr_axi_m1_i40;
-    input fabric_fpga_awaddr_axi_m1_i5;
-    input fabric_fpga_awaddr_axi_m1_i6;
-    input fabric_fpga_awaddr_axi_m1_i7;
-    input fabric_fpga_awaddr_axi_m1_i8;
-    input fabric_fpga_awaddr_axi_m1_i9;
-    input fabric_fpga_awaddr_axi_m2_i1;
-    input fabric_fpga_awaddr_axi_m2_i10;
-    input fabric_fpga_awaddr_axi_m2_i11;
-    input fabric_fpga_awaddr_axi_m2_i12;
-    input fabric_fpga_awaddr_axi_m2_i13;
-    input fabric_fpga_awaddr_axi_m2_i14;
-    input fabric_fpga_awaddr_axi_m2_i15;
-    input fabric_fpga_awaddr_axi_m2_i16;
-    input fabric_fpga_awaddr_axi_m2_i17;
-    input fabric_fpga_awaddr_axi_m2_i18;
-    input fabric_fpga_awaddr_axi_m2_i19;
-    input fabric_fpga_awaddr_axi_m2_i2;
-    input fabric_fpga_awaddr_axi_m2_i20;
-    input fabric_fpga_awaddr_axi_m2_i21;
-    input fabric_fpga_awaddr_axi_m2_i22;
-    input fabric_fpga_awaddr_axi_m2_i23;
-    input fabric_fpga_awaddr_axi_m2_i24;
-    input fabric_fpga_awaddr_axi_m2_i25;
-    input fabric_fpga_awaddr_axi_m2_i26;
-    input fabric_fpga_awaddr_axi_m2_i27;
-    input fabric_fpga_awaddr_axi_m2_i28;
-    input fabric_fpga_awaddr_axi_m2_i29;
-    input fabric_fpga_awaddr_axi_m2_i3;
-    input fabric_fpga_awaddr_axi_m2_i30;
-    input fabric_fpga_awaddr_axi_m2_i31;
-    input fabric_fpga_awaddr_axi_m2_i32;
-    input fabric_fpga_awaddr_axi_m2_i33;
-    input fabric_fpga_awaddr_axi_m2_i34;
-    input fabric_fpga_awaddr_axi_m2_i35;
-    input fabric_fpga_awaddr_axi_m2_i36;
-    input fabric_fpga_awaddr_axi_m2_i37;
-    input fabric_fpga_awaddr_axi_m2_i38;
-    input fabric_fpga_awaddr_axi_m2_i39;
-    input fabric_fpga_awaddr_axi_m2_i4;
-    input fabric_fpga_awaddr_axi_m2_i40;
-    input fabric_fpga_awaddr_axi_m2_i5;
-    input fabric_fpga_awaddr_axi_m2_i6;
-    input fabric_fpga_awaddr_axi_m2_i7;
-    input fabric_fpga_awaddr_axi_m2_i8;
-    input fabric_fpga_awaddr_axi_m2_i9;
-    output fabric_fpga_awaddr_axi_s1_o1;
-    output fabric_fpga_awaddr_axi_s1_o10;
-    output fabric_fpga_awaddr_axi_s1_o11;
-    output fabric_fpga_awaddr_axi_s1_o12;
-    output fabric_fpga_awaddr_axi_s1_o13;
-    output fabric_fpga_awaddr_axi_s1_o14;
-    output fabric_fpga_awaddr_axi_s1_o15;
-    output fabric_fpga_awaddr_axi_s1_o16;
-    output fabric_fpga_awaddr_axi_s1_o17;
-    output fabric_fpga_awaddr_axi_s1_o18;
-    output fabric_fpga_awaddr_axi_s1_o19;
-    output fabric_fpga_awaddr_axi_s1_o2;
-    output fabric_fpga_awaddr_axi_s1_o20;
-    output fabric_fpga_awaddr_axi_s1_o21;
-    output fabric_fpga_awaddr_axi_s1_o22;
-    output fabric_fpga_awaddr_axi_s1_o23;
-    output fabric_fpga_awaddr_axi_s1_o24;
-    output fabric_fpga_awaddr_axi_s1_o25;
-    output fabric_fpga_awaddr_axi_s1_o26;
-    output fabric_fpga_awaddr_axi_s1_o27;
-    output fabric_fpga_awaddr_axi_s1_o28;
-    output fabric_fpga_awaddr_axi_s1_o29;
-    output fabric_fpga_awaddr_axi_s1_o3;
-    output fabric_fpga_awaddr_axi_s1_o30;
-    output fabric_fpga_awaddr_axi_s1_o31;
-    output fabric_fpga_awaddr_axi_s1_o32;
-    output fabric_fpga_awaddr_axi_s1_o33;
-    output fabric_fpga_awaddr_axi_s1_o34;
-    output fabric_fpga_awaddr_axi_s1_o35;
-    output fabric_fpga_awaddr_axi_s1_o36;
-    output fabric_fpga_awaddr_axi_s1_o37;
-    output fabric_fpga_awaddr_axi_s1_o38;
-    output fabric_fpga_awaddr_axi_s1_o39;
-    output fabric_fpga_awaddr_axi_s1_o4;
-    output fabric_fpga_awaddr_axi_s1_o40;
-    output fabric_fpga_awaddr_axi_s1_o5;
-    output fabric_fpga_awaddr_axi_s1_o6;
-    output fabric_fpga_awaddr_axi_s1_o7;
-    output fabric_fpga_awaddr_axi_s1_o8;
-    output fabric_fpga_awaddr_axi_s1_o9;
-    output fabric_fpga_awaddr_axi_s2_o1;
-    output fabric_fpga_awaddr_axi_s2_o10;
-    output fabric_fpga_awaddr_axi_s2_o11;
-    output fabric_fpga_awaddr_axi_s2_o12;
-    output fabric_fpga_awaddr_axi_s2_o13;
-    output fabric_fpga_awaddr_axi_s2_o14;
-    output fabric_fpga_awaddr_axi_s2_o15;
-    output fabric_fpga_awaddr_axi_s2_o16;
-    output fabric_fpga_awaddr_axi_s2_o17;
-    output fabric_fpga_awaddr_axi_s2_o18;
-    output fabric_fpga_awaddr_axi_s2_o19;
-    output fabric_fpga_awaddr_axi_s2_o2;
-    output fabric_fpga_awaddr_axi_s2_o20;
-    output fabric_fpga_awaddr_axi_s2_o21;
-    output fabric_fpga_awaddr_axi_s2_o22;
-    output fabric_fpga_awaddr_axi_s2_o23;
-    output fabric_fpga_awaddr_axi_s2_o24;
-    output fabric_fpga_awaddr_axi_s2_o25;
-    output fabric_fpga_awaddr_axi_s2_o26;
-    output fabric_fpga_awaddr_axi_s2_o27;
-    output fabric_fpga_awaddr_axi_s2_o28;
-    output fabric_fpga_awaddr_axi_s2_o29;
-    output fabric_fpga_awaddr_axi_s2_o3;
-    output fabric_fpga_awaddr_axi_s2_o30;
-    output fabric_fpga_awaddr_axi_s2_o31;
-    output fabric_fpga_awaddr_axi_s2_o32;
-    output fabric_fpga_awaddr_axi_s2_o33;
-    output fabric_fpga_awaddr_axi_s2_o34;
-    output fabric_fpga_awaddr_axi_s2_o35;
-    output fabric_fpga_awaddr_axi_s2_o36;
-    output fabric_fpga_awaddr_axi_s2_o37;
-    output fabric_fpga_awaddr_axi_s2_o38;
-    output fabric_fpga_awaddr_axi_s2_o39;
-    output fabric_fpga_awaddr_axi_s2_o4;
-    output fabric_fpga_awaddr_axi_s2_o40;
-    output fabric_fpga_awaddr_axi_s2_o5;
-    output fabric_fpga_awaddr_axi_s2_o6;
-    output fabric_fpga_awaddr_axi_s2_o7;
-    output fabric_fpga_awaddr_axi_s2_o8;
-    output fabric_fpga_awaddr_axi_s2_o9;
-    input fabric_fpga_awburst_axi_m1_i1;
-    input fabric_fpga_awburst_axi_m1_i2;
-    input fabric_fpga_awburst_axi_m2_i1;
-    input fabric_fpga_awburst_axi_m2_i2;
-    output fabric_fpga_awburst_axi_s1_o1;
-    output fabric_fpga_awburst_axi_s1_o2;
-    output fabric_fpga_awburst_axi_s2_o1;
-    output fabric_fpga_awburst_axi_s2_o2;
-    input fabric_fpga_awcache_axi_m1_i1;
-    input fabric_fpga_awcache_axi_m1_i2;
-    input fabric_fpga_awcache_axi_m1_i3;
-    input fabric_fpga_awcache_axi_m1_i4;
-    input fabric_fpga_awcache_axi_m2_i1;
-    input fabric_fpga_awcache_axi_m2_i2;
-    input fabric_fpga_awcache_axi_m2_i3;
-    input fabric_fpga_awcache_axi_m2_i4;
-    output fabric_fpga_awcache_axi_s1_o1;
-    output fabric_fpga_awcache_axi_s1_o2;
-    output fabric_fpga_awcache_axi_s1_o3;
-    output fabric_fpga_awcache_axi_s1_o4;
-    output fabric_fpga_awcache_axi_s2_o1;
-    output fabric_fpga_awcache_axi_s2_o2;
-    output fabric_fpga_awcache_axi_s2_o3;
-    output fabric_fpga_awcache_axi_s2_o4;
-    input fabric_fpga_awid_axi_m1_i1;
-    input fabric_fpga_awid_axi_m1_i2;
-    input fabric_fpga_awid_axi_m1_i3;
-    input fabric_fpga_awid_axi_m1_i4;
-    input fabric_fpga_awid_axi_m1_i5;
-    input fabric_fpga_awid_axi_m2_i1;
-    input fabric_fpga_awid_axi_m2_i2;
-    input fabric_fpga_awid_axi_m2_i3;
-    input fabric_fpga_awid_axi_m2_i4;
-    input fabric_fpga_awid_axi_m2_i5;
-    output fabric_fpga_awid_axi_s1_o1;
-    output fabric_fpga_awid_axi_s1_o10;
-    output fabric_fpga_awid_axi_s1_o11;
-    output fabric_fpga_awid_axi_s1_o12;
-    output fabric_fpga_awid_axi_s1_o2;
-    output fabric_fpga_awid_axi_s1_o3;
-    output fabric_fpga_awid_axi_s1_o4;
-    output fabric_fpga_awid_axi_s1_o5;
-    output fabric_fpga_awid_axi_s1_o6;
-    output fabric_fpga_awid_axi_s1_o7;
-    output fabric_fpga_awid_axi_s1_o8;
-    output fabric_fpga_awid_axi_s1_o9;
-    output fabric_fpga_awid_axi_s2_o1;
-    output fabric_fpga_awid_axi_s2_o10;
-    output fabric_fpga_awid_axi_s2_o11;
-    output fabric_fpga_awid_axi_s2_o12;
-    output fabric_fpga_awid_axi_s2_o2;
-    output fabric_fpga_awid_axi_s2_o3;
-    output fabric_fpga_awid_axi_s2_o4;
-    output fabric_fpga_awid_axi_s2_o5;
-    output fabric_fpga_awid_axi_s2_o6;
-    output fabric_fpga_awid_axi_s2_o7;
-    output fabric_fpga_awid_axi_s2_o8;
-    output fabric_fpga_awid_axi_s2_o9;
-    input fabric_fpga_awlen_axi_m1_i1;
-    input fabric_fpga_awlen_axi_m1_i2;
-    input fabric_fpga_awlen_axi_m1_i3;
-    input fabric_fpga_awlen_axi_m1_i4;
-    input fabric_fpga_awlen_axi_m1_i5;
-    input fabric_fpga_awlen_axi_m1_i6;
-    input fabric_fpga_awlen_axi_m1_i7;
-    input fabric_fpga_awlen_axi_m1_i8;
-    input fabric_fpga_awlen_axi_m2_i1;
-    input fabric_fpga_awlen_axi_m2_i2;
-    input fabric_fpga_awlen_axi_m2_i3;
-    input fabric_fpga_awlen_axi_m2_i4;
-    input fabric_fpga_awlen_axi_m2_i5;
-    input fabric_fpga_awlen_axi_m2_i6;
-    input fabric_fpga_awlen_axi_m2_i7;
-    input fabric_fpga_awlen_axi_m2_i8;
-    output fabric_fpga_awlen_axi_s1_o1;
-    output fabric_fpga_awlen_axi_s1_o2;
-    output fabric_fpga_awlen_axi_s1_o3;
-    output fabric_fpga_awlen_axi_s1_o4;
-    output fabric_fpga_awlen_axi_s1_o5;
-    output fabric_fpga_awlen_axi_s1_o6;
-    output fabric_fpga_awlen_axi_s1_o7;
-    output fabric_fpga_awlen_axi_s1_o8;
-    output fabric_fpga_awlen_axi_s2_o1;
-    output fabric_fpga_awlen_axi_s2_o2;
-    output fabric_fpga_awlen_axi_s2_o3;
-    output fabric_fpga_awlen_axi_s2_o4;
-    output fabric_fpga_awlen_axi_s2_o5;
-    output fabric_fpga_awlen_axi_s2_o6;
-    output fabric_fpga_awlen_axi_s2_o7;
-    output fabric_fpga_awlen_axi_s2_o8;
-    input fabric_fpga_awlock_axi_m1_i;
-    input fabric_fpga_awlock_axi_m2_i;
-    output fabric_fpga_awlock_axi_s1_o;
-    output fabric_fpga_awlock_axi_s2_o;
-    input fabric_fpga_awprot_axi_m1_i1;
-    input fabric_fpga_awprot_axi_m1_i2;
-    input fabric_fpga_awprot_axi_m1_i3;
-    input fabric_fpga_awprot_axi_m2_i1;
-    input fabric_fpga_awprot_axi_m2_i2;
-    input fabric_fpga_awprot_axi_m2_i3;
-    output fabric_fpga_awprot_axi_s1_o1;
-    output fabric_fpga_awprot_axi_s1_o2;
-    output fabric_fpga_awprot_axi_s1_o3;
-    output fabric_fpga_awprot_axi_s2_o1;
-    output fabric_fpga_awprot_axi_s2_o2;
-    output fabric_fpga_awprot_axi_s2_o3;
-    input fabric_fpga_awqos_axi_m1_i1;
-    input fabric_fpga_awqos_axi_m1_i2;
-    input fabric_fpga_awqos_axi_m1_i3;
-    input fabric_fpga_awqos_axi_m1_i4;
-    input fabric_fpga_awqos_axi_m2_i1;
-    input fabric_fpga_awqos_axi_m2_i2;
-    input fabric_fpga_awqos_axi_m2_i3;
-    input fabric_fpga_awqos_axi_m2_i4;
-    output fabric_fpga_awqos_axi_s1_o1;
-    output fabric_fpga_awqos_axi_s1_o2;
-    output fabric_fpga_awqos_axi_s1_o3;
-    output fabric_fpga_awqos_axi_s1_o4;
-    output fabric_fpga_awqos_axi_s2_o1;
-    output fabric_fpga_awqos_axi_s2_o2;
-    output fabric_fpga_awqos_axi_s2_o3;
-    output fabric_fpga_awqos_axi_s2_o4;
-    output fabric_fpga_awready_axi_m1_o;
-    output fabric_fpga_awready_axi_m2_o;
-    input fabric_fpga_awready_axi_s1_i;
-    input fabric_fpga_awready_axi_s2_i;
-    output fabric_fpga_awregion_axi_s1_o1;
-    output fabric_fpga_awregion_axi_s1_o2;
-    output fabric_fpga_awregion_axi_s1_o3;
-    output fabric_fpga_awregion_axi_s1_o4;
-    output fabric_fpga_awregion_axi_s2_o1;
-    output fabric_fpga_awregion_axi_s2_o2;
-    output fabric_fpga_awregion_axi_s2_o3;
-    output fabric_fpga_awregion_axi_s2_o4;
-    input fabric_fpga_awsize_axi_m1_i1;
-    input fabric_fpga_awsize_axi_m1_i2;
-    input fabric_fpga_awsize_axi_m1_i3;
-    input fabric_fpga_awsize_axi_m2_i1;
-    input fabric_fpga_awsize_axi_m2_i2;
-    input fabric_fpga_awsize_axi_m2_i3;
-    output fabric_fpga_awsize_axi_s1_o1;
-    output fabric_fpga_awsize_axi_s1_o2;
-    output fabric_fpga_awsize_axi_s1_o3;
-    output fabric_fpga_awsize_axi_s2_o1;
-    output fabric_fpga_awsize_axi_s2_o2;
-    output fabric_fpga_awsize_axi_s2_o3;
-    input fabric_fpga_awvalid_axi_m1_i;
-    input fabric_fpga_awvalid_axi_m2_i;
-    output fabric_fpga_awvalid_axi_s1_o;
-    output fabric_fpga_awvalid_axi_s2_o;
-    output fabric_fpga_bid_axi_m1_o1;
-    output fabric_fpga_bid_axi_m1_o2;
-    output fabric_fpga_bid_axi_m1_o3;
-    output fabric_fpga_bid_axi_m1_o4;
-    output fabric_fpga_bid_axi_m1_o5;
-    output fabric_fpga_bid_axi_m2_o1;
-    output fabric_fpga_bid_axi_m2_o2;
-    output fabric_fpga_bid_axi_m2_o3;
-    output fabric_fpga_bid_axi_m2_o4;
-    output fabric_fpga_bid_axi_m2_o5;
-    input fabric_fpga_bid_axi_s1_i1;
-    input fabric_fpga_bid_axi_s1_i10;
-    input fabric_fpga_bid_axi_s1_i11;
-    input fabric_fpga_bid_axi_s1_i12;
-    input fabric_fpga_bid_axi_s1_i2;
-    input fabric_fpga_bid_axi_s1_i3;
-    input fabric_fpga_bid_axi_s1_i4;
-    input fabric_fpga_bid_axi_s1_i5;
-    input fabric_fpga_bid_axi_s1_i6;
-    input fabric_fpga_bid_axi_s1_i7;
-    input fabric_fpga_bid_axi_s1_i8;
-    input fabric_fpga_bid_axi_s1_i9;
-    input fabric_fpga_bid_axi_s2_i1;
-    input fabric_fpga_bid_axi_s2_i10;
-    input fabric_fpga_bid_axi_s2_i11;
-    input fabric_fpga_bid_axi_s2_i12;
-    input fabric_fpga_bid_axi_s2_i2;
-    input fabric_fpga_bid_axi_s2_i3;
-    input fabric_fpga_bid_axi_s2_i4;
-    input fabric_fpga_bid_axi_s2_i5;
-    input fabric_fpga_bid_axi_s2_i6;
-    input fabric_fpga_bid_axi_s2_i7;
-    input fabric_fpga_bid_axi_s2_i8;
-    input fabric_fpga_bid_axi_s2_i9;
-    input fabric_fpga_bready_axi_m1_i;
-    input fabric_fpga_bready_axi_m2_i;
-    output fabric_fpga_bready_axi_s1_o;
-    output fabric_fpga_bready_axi_s2_o;
-    output fabric_fpga_bresp_axi_m1_o1;
-    output fabric_fpga_bresp_axi_m1_o2;
-    output fabric_fpga_bresp_axi_m2_o1;
-    output fabric_fpga_bresp_axi_m2_o2;
-    input fabric_fpga_bresp_axi_s1_i1;
-    input fabric_fpga_bresp_axi_s1_i2;
-    input fabric_fpga_bresp_axi_s2_i1;
-    input fabric_fpga_bresp_axi_s2_i2;
-    output fabric_fpga_bvalid_axi_m1_o;
-    output fabric_fpga_bvalid_axi_m2_o;
-    input fabric_fpga_bvalid_axi_s1_i;
-    input fabric_fpga_bvalid_axi_s2_i;
-    input fabric_fpga_ddr0_araddr_i1;
-    input fabric_fpga_ddr0_araddr_i10;
-    input fabric_fpga_ddr0_araddr_i11;
-    input fabric_fpga_ddr0_araddr_i12;
-    input fabric_fpga_ddr0_araddr_i13;
-    input fabric_fpga_ddr0_araddr_i14;
-    input fabric_fpga_ddr0_araddr_i15;
-    input fabric_fpga_ddr0_araddr_i16;
-    input fabric_fpga_ddr0_araddr_i17;
-    input fabric_fpga_ddr0_araddr_i18;
-    input fabric_fpga_ddr0_araddr_i19;
-    input fabric_fpga_ddr0_araddr_i2;
-    input fabric_fpga_ddr0_araddr_i20;
-    input fabric_fpga_ddr0_araddr_i21;
-    input fabric_fpga_ddr0_araddr_i22;
-    input fabric_fpga_ddr0_araddr_i23;
-    input fabric_fpga_ddr0_araddr_i24;
-    input fabric_fpga_ddr0_araddr_i25;
-    input fabric_fpga_ddr0_araddr_i26;
-    input fabric_fpga_ddr0_araddr_i27;
-    input fabric_fpga_ddr0_araddr_i28;
-    input fabric_fpga_ddr0_araddr_i29;
-    input fabric_fpga_ddr0_araddr_i3;
-    input fabric_fpga_ddr0_araddr_i30;
-    input fabric_fpga_ddr0_araddr_i31;
-    input fabric_fpga_ddr0_araddr_i32;
-    input fabric_fpga_ddr0_araddr_i33;
-    input fabric_fpga_ddr0_araddr_i34;
-    input fabric_fpga_ddr0_araddr_i35;
-    input fabric_fpga_ddr0_araddr_i36;
-    input fabric_fpga_ddr0_araddr_i37;
-    input fabric_fpga_ddr0_araddr_i38;
-    input fabric_fpga_ddr0_araddr_i39;
-    input fabric_fpga_ddr0_araddr_i4;
-    input fabric_fpga_ddr0_araddr_i40;
-    input fabric_fpga_ddr0_araddr_i5;
-    input fabric_fpga_ddr0_araddr_i6;
-    input fabric_fpga_ddr0_araddr_i7;
-    input fabric_fpga_ddr0_araddr_i8;
-    input fabric_fpga_ddr0_araddr_i9;
-    input fabric_fpga_ddr0_arburst_i1;
-    input fabric_fpga_ddr0_arburst_i2;
-    input fabric_fpga_ddr0_arcache_i1;
-    input fabric_fpga_ddr0_arcache_i2;
-    input fabric_fpga_ddr0_arcache_i3;
-    input fabric_fpga_ddr0_arcache_i4;
-    input fabric_fpga_ddr0_arid_i1;
-    input fabric_fpga_ddr0_arid_i2;
-    input fabric_fpga_ddr0_arid_i3;
-    input fabric_fpga_ddr0_arid_i4;
-    input fabric_fpga_ddr0_arid_i5;
-    input fabric_fpga_ddr0_arlen_i1;
-    input fabric_fpga_ddr0_arlen_i2;
-    input fabric_fpga_ddr0_arlen_i3;
-    input fabric_fpga_ddr0_arlen_i4;
-    input fabric_fpga_ddr0_arlen_i5;
-    input fabric_fpga_ddr0_arlen_i6;
-    input fabric_fpga_ddr0_arlen_i7;
-    input fabric_fpga_ddr0_arlen_i8;
-    input fabric_fpga_ddr0_arlock_i;
-    input fabric_fpga_ddr0_arprot_i1;
-    input fabric_fpga_ddr0_arprot_i2;
-    input fabric_fpga_ddr0_arprot_i3;
-    input fabric_fpga_ddr0_arqos_i1;
-    input fabric_fpga_ddr0_arqos_i2;
-    input fabric_fpga_ddr0_arqos_i3;
-    input fabric_fpga_ddr0_arqos_i4;
-    output fabric_fpga_ddr0_arready_o;
-    input fabric_fpga_ddr0_arsize_i1;
-    input fabric_fpga_ddr0_arsize_i2;
-    input fabric_fpga_ddr0_arsize_i3;
-    input fabric_fpga_ddr0_arvalid_i;
-    input fabric_fpga_ddr0_awaddr_i1;
-    input fabric_fpga_ddr0_awaddr_i10;
-    input fabric_fpga_ddr0_awaddr_i11;
-    input fabric_fpga_ddr0_awaddr_i12;
-    input fabric_fpga_ddr0_awaddr_i13;
-    input fabric_fpga_ddr0_awaddr_i14;
-    input fabric_fpga_ddr0_awaddr_i15;
-    input fabric_fpga_ddr0_awaddr_i16;
-    input fabric_fpga_ddr0_awaddr_i17;
-    input fabric_fpga_ddr0_awaddr_i18;
-    input fabric_fpga_ddr0_awaddr_i19;
-    input fabric_fpga_ddr0_awaddr_i2;
-    input fabric_fpga_ddr0_awaddr_i20;
-    input fabric_fpga_ddr0_awaddr_i21;
-    input fabric_fpga_ddr0_awaddr_i22;
-    input fabric_fpga_ddr0_awaddr_i23;
-    input fabric_fpga_ddr0_awaddr_i24;
-    input fabric_fpga_ddr0_awaddr_i25;
-    input fabric_fpga_ddr0_awaddr_i26;
-    input fabric_fpga_ddr0_awaddr_i27;
-    input fabric_fpga_ddr0_awaddr_i28;
-    input fabric_fpga_ddr0_awaddr_i29;
-    input fabric_fpga_ddr0_awaddr_i3;
-    input fabric_fpga_ddr0_awaddr_i30;
-    input fabric_fpga_ddr0_awaddr_i31;
-    input fabric_fpga_ddr0_awaddr_i32;
-    input fabric_fpga_ddr0_awaddr_i33;
-    input fabric_fpga_ddr0_awaddr_i34;
-    input fabric_fpga_ddr0_awaddr_i35;
-    input fabric_fpga_ddr0_awaddr_i36;
-    input fabric_fpga_ddr0_awaddr_i37;
-    input fabric_fpga_ddr0_awaddr_i38;
-    input fabric_fpga_ddr0_awaddr_i39;
-    input fabric_fpga_ddr0_awaddr_i4;
-    input fabric_fpga_ddr0_awaddr_i40;
-    input fabric_fpga_ddr0_awaddr_i5;
-    input fabric_fpga_ddr0_awaddr_i6;
-    input fabric_fpga_ddr0_awaddr_i7;
-    input fabric_fpga_ddr0_awaddr_i8;
-    input fabric_fpga_ddr0_awaddr_i9;
-    input fabric_fpga_ddr0_awburst_i1;
-    input fabric_fpga_ddr0_awburst_i2;
-    input fabric_fpga_ddr0_awcache_i1;
-    input fabric_fpga_ddr0_awcache_i2;
-    input fabric_fpga_ddr0_awcache_i3;
-    input fabric_fpga_ddr0_awcache_i4;
-    input fabric_fpga_ddr0_awid_i1;
-    input fabric_fpga_ddr0_awid_i2;
-    input fabric_fpga_ddr0_awid_i3;
-    input fabric_fpga_ddr0_awid_i4;
-    input fabric_fpga_ddr0_awid_i5;
-    input fabric_fpga_ddr0_awlen_i1;
-    input fabric_fpga_ddr0_awlen_i2;
-    input fabric_fpga_ddr0_awlen_i3;
-    input fabric_fpga_ddr0_awlen_i4;
-    input fabric_fpga_ddr0_awlen_i5;
-    input fabric_fpga_ddr0_awlen_i6;
-    input fabric_fpga_ddr0_awlen_i7;
-    input fabric_fpga_ddr0_awlen_i8;
-    input fabric_fpga_ddr0_awlock_i;
-    input fabric_fpga_ddr0_awprot_i1;
-    input fabric_fpga_ddr0_awprot_i2;
-    input fabric_fpga_ddr0_awprot_i3;
-    input fabric_fpga_ddr0_awqos_i1;
-    input fabric_fpga_ddr0_awqos_i2;
-    input fabric_fpga_ddr0_awqos_i3;
-    input fabric_fpga_ddr0_awqos_i4;
-    output fabric_fpga_ddr0_awready_o;
-    input fabric_fpga_ddr0_awsize_i1;
-    input fabric_fpga_ddr0_awsize_i2;
-    input fabric_fpga_ddr0_awsize_i3;
-    input fabric_fpga_ddr0_awvalid_i;
-    output fabric_fpga_ddr0_bid_o1;
-    output fabric_fpga_ddr0_bid_o2;
-    output fabric_fpga_ddr0_bid_o3;
-    output fabric_fpga_ddr0_bid_o4;
-    output fabric_fpga_ddr0_bid_o5;
-    input fabric_fpga_ddr0_bready_i;
-    output fabric_fpga_ddr0_bresp_o1;
-    output fabric_fpga_ddr0_bresp_o2;
-    output fabric_fpga_ddr0_bvalid_o;
-    output fabric_fpga_ddr0_rdata_o1;
-    output fabric_fpga_ddr0_rdata_o10;
-    output fabric_fpga_ddr0_rdata_o100;
-    output fabric_fpga_ddr0_rdata_o101;
-    output fabric_fpga_ddr0_rdata_o102;
-    output fabric_fpga_ddr0_rdata_o103;
-    output fabric_fpga_ddr0_rdata_o104;
-    output fabric_fpga_ddr0_rdata_o105;
-    output fabric_fpga_ddr0_rdata_o106;
-    output fabric_fpga_ddr0_rdata_o107;
-    output fabric_fpga_ddr0_rdata_o108;
-    output fabric_fpga_ddr0_rdata_o109;
-    output fabric_fpga_ddr0_rdata_o11;
-    output fabric_fpga_ddr0_rdata_o110;
-    output fabric_fpga_ddr0_rdata_o111;
-    output fabric_fpga_ddr0_rdata_o112;
-    output fabric_fpga_ddr0_rdata_o113;
-    output fabric_fpga_ddr0_rdata_o114;
-    output fabric_fpga_ddr0_rdata_o115;
-    output fabric_fpga_ddr0_rdata_o116;
-    output fabric_fpga_ddr0_rdata_o117;
-    output fabric_fpga_ddr0_rdata_o118;
-    output fabric_fpga_ddr0_rdata_o119;
-    output fabric_fpga_ddr0_rdata_o12;
-    output fabric_fpga_ddr0_rdata_o120;
-    output fabric_fpga_ddr0_rdata_o121;
-    output fabric_fpga_ddr0_rdata_o122;
-    output fabric_fpga_ddr0_rdata_o123;
-    output fabric_fpga_ddr0_rdata_o124;
-    output fabric_fpga_ddr0_rdata_o125;
-    output fabric_fpga_ddr0_rdata_o126;
-    output fabric_fpga_ddr0_rdata_o127;
-    output fabric_fpga_ddr0_rdata_o128;
-    output fabric_fpga_ddr0_rdata_o13;
-    output fabric_fpga_ddr0_rdata_o14;
-    output fabric_fpga_ddr0_rdata_o15;
-    output fabric_fpga_ddr0_rdata_o16;
-    output fabric_fpga_ddr0_rdata_o17;
-    output fabric_fpga_ddr0_rdata_o18;
-    output fabric_fpga_ddr0_rdata_o19;
-    output fabric_fpga_ddr0_rdata_o2;
-    output fabric_fpga_ddr0_rdata_o20;
-    output fabric_fpga_ddr0_rdata_o21;
-    output fabric_fpga_ddr0_rdata_o22;
-    output fabric_fpga_ddr0_rdata_o23;
-    output fabric_fpga_ddr0_rdata_o24;
-    output fabric_fpga_ddr0_rdata_o25;
-    output fabric_fpga_ddr0_rdata_o26;
-    output fabric_fpga_ddr0_rdata_o27;
-    output fabric_fpga_ddr0_rdata_o28;
-    output fabric_fpga_ddr0_rdata_o29;
-    output fabric_fpga_ddr0_rdata_o3;
-    output fabric_fpga_ddr0_rdata_o30;
-    output fabric_fpga_ddr0_rdata_o31;
-    output fabric_fpga_ddr0_rdata_o32;
-    output fabric_fpga_ddr0_rdata_o33;
-    output fabric_fpga_ddr0_rdata_o34;
-    output fabric_fpga_ddr0_rdata_o35;
-    output fabric_fpga_ddr0_rdata_o36;
-    output fabric_fpga_ddr0_rdata_o37;
-    output fabric_fpga_ddr0_rdata_o38;
-    output fabric_fpga_ddr0_rdata_o39;
-    output fabric_fpga_ddr0_rdata_o4;
-    output fabric_fpga_ddr0_rdata_o40;
-    output fabric_fpga_ddr0_rdata_o41;
-    output fabric_fpga_ddr0_rdata_o42;
-    output fabric_fpga_ddr0_rdata_o43;
-    output fabric_fpga_ddr0_rdata_o44;
-    output fabric_fpga_ddr0_rdata_o45;
-    output fabric_fpga_ddr0_rdata_o46;
-    output fabric_fpga_ddr0_rdata_o47;
-    output fabric_fpga_ddr0_rdata_o48;
-    output fabric_fpga_ddr0_rdata_o49;
-    output fabric_fpga_ddr0_rdata_o5;
-    output fabric_fpga_ddr0_rdata_o50;
-    output fabric_fpga_ddr0_rdata_o51;
-    output fabric_fpga_ddr0_rdata_o52;
-    output fabric_fpga_ddr0_rdata_o53;
-    output fabric_fpga_ddr0_rdata_o54;
-    output fabric_fpga_ddr0_rdata_o55;
-    output fabric_fpga_ddr0_rdata_o56;
-    output fabric_fpga_ddr0_rdata_o57;
-    output fabric_fpga_ddr0_rdata_o58;
-    output fabric_fpga_ddr0_rdata_o59;
-    output fabric_fpga_ddr0_rdata_o6;
-    output fabric_fpga_ddr0_rdata_o60;
-    output fabric_fpga_ddr0_rdata_o61;
-    output fabric_fpga_ddr0_rdata_o62;
-    output fabric_fpga_ddr0_rdata_o63;
-    output fabric_fpga_ddr0_rdata_o64;
-    output fabric_fpga_ddr0_rdata_o65;
-    output fabric_fpga_ddr0_rdata_o66;
-    output fabric_fpga_ddr0_rdata_o67;
-    output fabric_fpga_ddr0_rdata_o68;
-    output fabric_fpga_ddr0_rdata_o69;
-    output fabric_fpga_ddr0_rdata_o7;
-    output fabric_fpga_ddr0_rdata_o70;
-    output fabric_fpga_ddr0_rdata_o71;
-    output fabric_fpga_ddr0_rdata_o72;
-    output fabric_fpga_ddr0_rdata_o73;
-    output fabric_fpga_ddr0_rdata_o74;
-    output fabric_fpga_ddr0_rdata_o75;
-    output fabric_fpga_ddr0_rdata_o76;
-    output fabric_fpga_ddr0_rdata_o77;
-    output fabric_fpga_ddr0_rdata_o78;
-    output fabric_fpga_ddr0_rdata_o79;
-    output fabric_fpga_ddr0_rdata_o8;
-    output fabric_fpga_ddr0_rdata_o80;
-    output fabric_fpga_ddr0_rdata_o81;
-    output fabric_fpga_ddr0_rdata_o82;
-    output fabric_fpga_ddr0_rdata_o83;
-    output fabric_fpga_ddr0_rdata_o84;
-    output fabric_fpga_ddr0_rdata_o85;
-    output fabric_fpga_ddr0_rdata_o86;
-    output fabric_fpga_ddr0_rdata_o87;
-    output fabric_fpga_ddr0_rdata_o88;
-    output fabric_fpga_ddr0_rdata_o89;
-    output fabric_fpga_ddr0_rdata_o9;
-    output fabric_fpga_ddr0_rdata_o90;
-    output fabric_fpga_ddr0_rdata_o91;
-    output fabric_fpga_ddr0_rdata_o92;
-    output fabric_fpga_ddr0_rdata_o93;
-    output fabric_fpga_ddr0_rdata_o94;
-    output fabric_fpga_ddr0_rdata_o95;
-    output fabric_fpga_ddr0_rdata_o96;
-    output fabric_fpga_ddr0_rdata_o97;
-    output fabric_fpga_ddr0_rdata_o98;
-    output fabric_fpga_ddr0_rdata_o99;
-    output fabric_fpga_ddr0_rid_o1;
-    output fabric_fpga_ddr0_rid_o2;
-    output fabric_fpga_ddr0_rid_o3;
-    output fabric_fpga_ddr0_rid_o4;
-    output fabric_fpga_ddr0_rid_o5;
-    output fabric_fpga_ddr0_rlast_o;
-    input fabric_fpga_ddr0_rready_i;
-    output fabric_fpga_ddr0_rresp_o1;
-    output fabric_fpga_ddr0_rresp_o2;
-    output fabric_fpga_ddr0_rvalid_o;
-    input fabric_fpga_ddr0_wdata_i1;
-    input fabric_fpga_ddr0_wdata_i10;
-    input fabric_fpga_ddr0_wdata_i100;
-    input fabric_fpga_ddr0_wdata_i101;
-    input fabric_fpga_ddr0_wdata_i102;
-    input fabric_fpga_ddr0_wdata_i103;
-    input fabric_fpga_ddr0_wdata_i104;
-    input fabric_fpga_ddr0_wdata_i105;
-    input fabric_fpga_ddr0_wdata_i106;
-    input fabric_fpga_ddr0_wdata_i107;
-    input fabric_fpga_ddr0_wdata_i108;
-    input fabric_fpga_ddr0_wdata_i109;
-    input fabric_fpga_ddr0_wdata_i11;
-    input fabric_fpga_ddr0_wdata_i110;
-    input fabric_fpga_ddr0_wdata_i111;
-    input fabric_fpga_ddr0_wdata_i112;
-    input fabric_fpga_ddr0_wdata_i113;
-    input fabric_fpga_ddr0_wdata_i114;
-    input fabric_fpga_ddr0_wdata_i115;
-    input fabric_fpga_ddr0_wdata_i116;
-    input fabric_fpga_ddr0_wdata_i117;
-    input fabric_fpga_ddr0_wdata_i118;
-    input fabric_fpga_ddr0_wdata_i119;
-    input fabric_fpga_ddr0_wdata_i12;
-    input fabric_fpga_ddr0_wdata_i120;
-    input fabric_fpga_ddr0_wdata_i121;
-    input fabric_fpga_ddr0_wdata_i122;
-    input fabric_fpga_ddr0_wdata_i123;
-    input fabric_fpga_ddr0_wdata_i124;
-    input fabric_fpga_ddr0_wdata_i125;
-    input fabric_fpga_ddr0_wdata_i126;
-    input fabric_fpga_ddr0_wdata_i127;
-    input fabric_fpga_ddr0_wdata_i128;
-    input fabric_fpga_ddr0_wdata_i13;
-    input fabric_fpga_ddr0_wdata_i14;
-    input fabric_fpga_ddr0_wdata_i15;
-    input fabric_fpga_ddr0_wdata_i16;
-    input fabric_fpga_ddr0_wdata_i17;
-    input fabric_fpga_ddr0_wdata_i18;
-    input fabric_fpga_ddr0_wdata_i19;
-    input fabric_fpga_ddr0_wdata_i2;
-    input fabric_fpga_ddr0_wdata_i20;
-    input fabric_fpga_ddr0_wdata_i21;
-    input fabric_fpga_ddr0_wdata_i22;
-    input fabric_fpga_ddr0_wdata_i23;
-    input fabric_fpga_ddr0_wdata_i24;
-    input fabric_fpga_ddr0_wdata_i25;
-    input fabric_fpga_ddr0_wdata_i26;
-    input fabric_fpga_ddr0_wdata_i27;
-    input fabric_fpga_ddr0_wdata_i28;
-    input fabric_fpga_ddr0_wdata_i29;
-    input fabric_fpga_ddr0_wdata_i3;
-    input fabric_fpga_ddr0_wdata_i30;
-    input fabric_fpga_ddr0_wdata_i31;
-    input fabric_fpga_ddr0_wdata_i32;
-    input fabric_fpga_ddr0_wdata_i33;
-    input fabric_fpga_ddr0_wdata_i34;
-    input fabric_fpga_ddr0_wdata_i35;
-    input fabric_fpga_ddr0_wdata_i36;
-    input fabric_fpga_ddr0_wdata_i37;
-    input fabric_fpga_ddr0_wdata_i38;
-    input fabric_fpga_ddr0_wdata_i39;
-    input fabric_fpga_ddr0_wdata_i4;
-    input fabric_fpga_ddr0_wdata_i40;
-    input fabric_fpga_ddr0_wdata_i41;
-    input fabric_fpga_ddr0_wdata_i42;
-    input fabric_fpga_ddr0_wdata_i43;
-    input fabric_fpga_ddr0_wdata_i44;
-    input fabric_fpga_ddr0_wdata_i45;
-    input fabric_fpga_ddr0_wdata_i46;
-    input fabric_fpga_ddr0_wdata_i47;
-    input fabric_fpga_ddr0_wdata_i48;
-    input fabric_fpga_ddr0_wdata_i49;
-    input fabric_fpga_ddr0_wdata_i5;
-    input fabric_fpga_ddr0_wdata_i50;
-    input fabric_fpga_ddr0_wdata_i51;
-    input fabric_fpga_ddr0_wdata_i52;
-    input fabric_fpga_ddr0_wdata_i53;
-    input fabric_fpga_ddr0_wdata_i54;
-    input fabric_fpga_ddr0_wdata_i55;
-    input fabric_fpga_ddr0_wdata_i56;
-    input fabric_fpga_ddr0_wdata_i57;
-    input fabric_fpga_ddr0_wdata_i58;
-    input fabric_fpga_ddr0_wdata_i59;
-    input fabric_fpga_ddr0_wdata_i6;
-    input fabric_fpga_ddr0_wdata_i60;
-    input fabric_fpga_ddr0_wdata_i61;
-    input fabric_fpga_ddr0_wdata_i62;
-    input fabric_fpga_ddr0_wdata_i63;
-    input fabric_fpga_ddr0_wdata_i64;
-    input fabric_fpga_ddr0_wdata_i65;
-    input fabric_fpga_ddr0_wdata_i66;
-    input fabric_fpga_ddr0_wdata_i67;
-    input fabric_fpga_ddr0_wdata_i68;
-    input fabric_fpga_ddr0_wdata_i69;
-    input fabric_fpga_ddr0_wdata_i7;
-    input fabric_fpga_ddr0_wdata_i70;
-    input fabric_fpga_ddr0_wdata_i71;
-    input fabric_fpga_ddr0_wdata_i72;
-    input fabric_fpga_ddr0_wdata_i73;
-    input fabric_fpga_ddr0_wdata_i74;
-    input fabric_fpga_ddr0_wdata_i75;
-    input fabric_fpga_ddr0_wdata_i76;
-    input fabric_fpga_ddr0_wdata_i77;
-    input fabric_fpga_ddr0_wdata_i78;
-    input fabric_fpga_ddr0_wdata_i79;
-    input fabric_fpga_ddr0_wdata_i8;
-    input fabric_fpga_ddr0_wdata_i80;
-    input fabric_fpga_ddr0_wdata_i81;
-    input fabric_fpga_ddr0_wdata_i82;
-    input fabric_fpga_ddr0_wdata_i83;
-    input fabric_fpga_ddr0_wdata_i84;
-    input fabric_fpga_ddr0_wdata_i85;
-    input fabric_fpga_ddr0_wdata_i86;
-    input fabric_fpga_ddr0_wdata_i87;
-    input fabric_fpga_ddr0_wdata_i88;
-    input fabric_fpga_ddr0_wdata_i89;
-    input fabric_fpga_ddr0_wdata_i9;
-    input fabric_fpga_ddr0_wdata_i90;
-    input fabric_fpga_ddr0_wdata_i91;
-    input fabric_fpga_ddr0_wdata_i92;
-    input fabric_fpga_ddr0_wdata_i93;
-    input fabric_fpga_ddr0_wdata_i94;
-    input fabric_fpga_ddr0_wdata_i95;
-    input fabric_fpga_ddr0_wdata_i96;
-    input fabric_fpga_ddr0_wdata_i97;
-    input fabric_fpga_ddr0_wdata_i98;
-    input fabric_fpga_ddr0_wdata_i99;
-    input fabric_fpga_ddr0_wlast_i;
-    output fabric_fpga_ddr0_wready_o;
-    input fabric_fpga_ddr0_wstrb_i1;
-    input fabric_fpga_ddr0_wstrb_i10;
-    input fabric_fpga_ddr0_wstrb_i11;
-    input fabric_fpga_ddr0_wstrb_i12;
-    input fabric_fpga_ddr0_wstrb_i13;
-    input fabric_fpga_ddr0_wstrb_i14;
-    input fabric_fpga_ddr0_wstrb_i15;
-    input fabric_fpga_ddr0_wstrb_i16;
-    input fabric_fpga_ddr0_wstrb_i2;
-    input fabric_fpga_ddr0_wstrb_i3;
-    input fabric_fpga_ddr0_wstrb_i4;
-    input fabric_fpga_ddr0_wstrb_i5;
-    input fabric_fpga_ddr0_wstrb_i6;
-    input fabric_fpga_ddr0_wstrb_i7;
-    input fabric_fpga_ddr0_wstrb_i8;
-    input fabric_fpga_ddr0_wstrb_i9;
-    input fabric_fpga_ddr0_wvalid_i;
-    output fabric_fpga_dma_ack_m1_o1;
-    output fabric_fpga_dma_ack_m1_o2;
-    output fabric_fpga_dma_ack_m1_o3;
-    output fabric_fpga_dma_ack_m1_o4;
-    output fabric_fpga_dma_ack_m1_o5;
-    output fabric_fpga_dma_ack_m1_o6;
-    output fabric_fpga_dma_ack_m2_o1;
-    output fabric_fpga_dma_ack_m2_o2;
-    output fabric_fpga_dma_ack_m2_o3;
-    output fabric_fpga_dma_ack_m2_o4;
-    output fabric_fpga_dma_ack_m2_o5;
-    output fabric_fpga_dma_ack_m2_o6;
-    output fabric_fpga_dma_finish_m1_o1;
-    output fabric_fpga_dma_finish_m1_o2;
-    output fabric_fpga_dma_finish_m1_o3;
-    output fabric_fpga_dma_finish_m1_o4;
-    output fabric_fpga_dma_finish_m1_o5;
-    output fabric_fpga_dma_finish_m1_o6;
-    output fabric_fpga_dma_finish_m2_o1;
-    output fabric_fpga_dma_finish_m2_o2;
-    output fabric_fpga_dma_finish_m2_o3;
-    output fabric_fpga_dma_finish_m2_o4;
-    output fabric_fpga_dma_finish_m2_o5;
-    output fabric_fpga_dma_finish_m2_o6;
-    input fabric_fpga_dma_last_m1_i1;
-    input fabric_fpga_dma_last_m1_i2;
-    input fabric_fpga_dma_last_m1_i3;
-    input fabric_fpga_dma_last_m1_i4;
-    input fabric_fpga_dma_last_m1_i5;
-    input fabric_fpga_dma_last_m1_i6;
-    input fabric_fpga_dma_last_m2_i1;
-    input fabric_fpga_dma_last_m2_i2;
-    input fabric_fpga_dma_last_m2_i3;
-    input fabric_fpga_dma_last_m2_i4;
-    input fabric_fpga_dma_last_m2_i5;
-    input fabric_fpga_dma_last_m2_i6;
-    input fabric_fpga_dma_req_m1_i1;
-    input fabric_fpga_dma_req_m1_i2;
-    input fabric_fpga_dma_req_m1_i3;
-    input fabric_fpga_dma_req_m1_i4;
-    input fabric_fpga_dma_req_m1_i5;
-    input fabric_fpga_dma_req_m1_i6;
-    input fabric_fpga_dma_req_m2_i1;
-    input fabric_fpga_dma_req_m2_i2;
-    input fabric_fpga_dma_req_m2_i3;
-    input fabric_fpga_dma_req_m2_i4;
-    input fabric_fpga_dma_req_m2_i5;
-    input fabric_fpga_dma_req_m2_i6;
-    input fabric_fpga_dma_single_m1_i1;
-    input fabric_fpga_dma_single_m1_i2;
-    input fabric_fpga_dma_single_m1_i3;
-    input fabric_fpga_dma_single_m1_i4;
-    input fabric_fpga_dma_single_m1_i5;
-    input fabric_fpga_dma_single_m1_i6;
-    input fabric_fpga_dma_single_m2_i1;
-    input fabric_fpga_dma_single_m2_i2;
-    input fabric_fpga_dma_single_m2_i3;
-    input fabric_fpga_dma_single_m2_i4;
-    input fabric_fpga_dma_single_m2_i5;
-    input fabric_fpga_dma_single_m2_i6;
-    input fabric_fpga_events60_i1;
-    input fabric_fpga_events60_i10;
-    input fabric_fpga_events60_i11;
-    input fabric_fpga_events60_i12;
-    input fabric_fpga_events60_i13;
-    input fabric_fpga_events60_i14;
-    input fabric_fpga_events60_i15;
-    input fabric_fpga_events60_i16;
-    input fabric_fpga_events60_i17;
-    input fabric_fpga_events60_i18;
-    input fabric_fpga_events60_i19;
-    input fabric_fpga_events60_i2;
-    input fabric_fpga_events60_i20;
-    input fabric_fpga_events60_i21;
-    input fabric_fpga_events60_i22;
-    input fabric_fpga_events60_i23;
-    input fabric_fpga_events60_i24;
-    input fabric_fpga_events60_i25;
-    input fabric_fpga_events60_i26;
-    input fabric_fpga_events60_i27;
-    input fabric_fpga_events60_i28;
-    input fabric_fpga_events60_i29;
-    input fabric_fpga_events60_i3;
-    input fabric_fpga_events60_i30;
-    input fabric_fpga_events60_i31;
-    input fabric_fpga_events60_i32;
-    input fabric_fpga_events60_i33;
-    input fabric_fpga_events60_i34;
-    input fabric_fpga_events60_i35;
-    input fabric_fpga_events60_i36;
-    input fabric_fpga_events60_i37;
-    input fabric_fpga_events60_i38;
-    input fabric_fpga_events60_i39;
-    input fabric_fpga_events60_i4;
-    input fabric_fpga_events60_i40;
-    input fabric_fpga_events60_i41;
-    input fabric_fpga_events60_i42;
-    input fabric_fpga_events60_i43;
-    input fabric_fpga_events60_i44;
-    input fabric_fpga_events60_i45;
-    input fabric_fpga_events60_i46;
-    input fabric_fpga_events60_i47;
-    input fabric_fpga_events60_i48;
-    input fabric_fpga_events60_i49;
-    input fabric_fpga_events60_i5;
-    input fabric_fpga_events60_i50;
-    input fabric_fpga_events60_i51;
-    input fabric_fpga_events60_i52;
-    input fabric_fpga_events60_i53;
-    input fabric_fpga_events60_i54;
-    input fabric_fpga_events60_i55;
-    input fabric_fpga_events60_i56;
-    input fabric_fpga_events60_i57;
-    input fabric_fpga_events60_i58;
-    input fabric_fpga_events60_i59;
-    input fabric_fpga_events60_i6;
-    input fabric_fpga_events60_i60;
-    input fabric_fpga_events60_i7;
-    input fabric_fpga_events60_i8;
-    input fabric_fpga_events60_i9;
-    input fabric_fpga_interrupt_in_i1;
-    input fabric_fpga_interrupt_in_i10;
-    input fabric_fpga_interrupt_in_i100;
-    input fabric_fpga_interrupt_in_i101;
-    input fabric_fpga_interrupt_in_i102;
-    input fabric_fpga_interrupt_in_i103;
-    input fabric_fpga_interrupt_in_i104;
-    input fabric_fpga_interrupt_in_i105;
-    input fabric_fpga_interrupt_in_i106;
-    input fabric_fpga_interrupt_in_i107;
-    input fabric_fpga_interrupt_in_i108;
-    input fabric_fpga_interrupt_in_i109;
-    input fabric_fpga_interrupt_in_i11;
-    input fabric_fpga_interrupt_in_i110;
-    input fabric_fpga_interrupt_in_i111;
-    input fabric_fpga_interrupt_in_i112;
-    input fabric_fpga_interrupt_in_i113;
-    input fabric_fpga_interrupt_in_i114;
-    input fabric_fpga_interrupt_in_i115;
-    input fabric_fpga_interrupt_in_i116;
-    input fabric_fpga_interrupt_in_i117;
-    input fabric_fpga_interrupt_in_i118;
-    input fabric_fpga_interrupt_in_i119;
-    input fabric_fpga_interrupt_in_i12;
-    input fabric_fpga_interrupt_in_i120;
-    input fabric_fpga_interrupt_in_i13;
-    input fabric_fpga_interrupt_in_i14;
-    input fabric_fpga_interrupt_in_i15;
-    input fabric_fpga_interrupt_in_i16;
-    input fabric_fpga_interrupt_in_i17;
-    input fabric_fpga_interrupt_in_i18;
-    input fabric_fpga_interrupt_in_i19;
-    input fabric_fpga_interrupt_in_i2;
-    input fabric_fpga_interrupt_in_i20;
-    input fabric_fpga_interrupt_in_i21;
-    input fabric_fpga_interrupt_in_i22;
-    input fabric_fpga_interrupt_in_i23;
-    input fabric_fpga_interrupt_in_i24;
-    input fabric_fpga_interrupt_in_i25;
-    input fabric_fpga_interrupt_in_i26;
-    input fabric_fpga_interrupt_in_i27;
-    input fabric_fpga_interrupt_in_i28;
-    input fabric_fpga_interrupt_in_i29;
-    input fabric_fpga_interrupt_in_i3;
-    input fabric_fpga_interrupt_in_i30;
-    input fabric_fpga_interrupt_in_i31;
-    input fabric_fpga_interrupt_in_i32;
-    input fabric_fpga_interrupt_in_i33;
-    input fabric_fpga_interrupt_in_i34;
-    input fabric_fpga_interrupt_in_i35;
-    input fabric_fpga_interrupt_in_i36;
-    input fabric_fpga_interrupt_in_i37;
-    input fabric_fpga_interrupt_in_i38;
-    input fabric_fpga_interrupt_in_i39;
-    input fabric_fpga_interrupt_in_i4;
-    input fabric_fpga_interrupt_in_i40;
-    input fabric_fpga_interrupt_in_i41;
-    input fabric_fpga_interrupt_in_i42;
-    input fabric_fpga_interrupt_in_i43;
-    input fabric_fpga_interrupt_in_i44;
-    input fabric_fpga_interrupt_in_i45;
-    input fabric_fpga_interrupt_in_i46;
-    input fabric_fpga_interrupt_in_i47;
-    input fabric_fpga_interrupt_in_i48;
-    input fabric_fpga_interrupt_in_i49;
-    input fabric_fpga_interrupt_in_i5;
-    input fabric_fpga_interrupt_in_i50;
-    input fabric_fpga_interrupt_in_i51;
-    input fabric_fpga_interrupt_in_i52;
-    input fabric_fpga_interrupt_in_i53;
-    input fabric_fpga_interrupt_in_i54;
-    input fabric_fpga_interrupt_in_i55;
-    input fabric_fpga_interrupt_in_i56;
-    input fabric_fpga_interrupt_in_i57;
-    input fabric_fpga_interrupt_in_i58;
-    input fabric_fpga_interrupt_in_i59;
-    input fabric_fpga_interrupt_in_i6;
-    input fabric_fpga_interrupt_in_i60;
-    input fabric_fpga_interrupt_in_i61;
-    input fabric_fpga_interrupt_in_i62;
-    input fabric_fpga_interrupt_in_i63;
-    input fabric_fpga_interrupt_in_i64;
-    input fabric_fpga_interrupt_in_i65;
-    input fabric_fpga_interrupt_in_i66;
-    input fabric_fpga_interrupt_in_i67;
-    input fabric_fpga_interrupt_in_i68;
-    input fabric_fpga_interrupt_in_i69;
-    input fabric_fpga_interrupt_in_i7;
-    input fabric_fpga_interrupt_in_i70;
-    input fabric_fpga_interrupt_in_i71;
-    input fabric_fpga_interrupt_in_i72;
-    input fabric_fpga_interrupt_in_i73;
-    input fabric_fpga_interrupt_in_i74;
-    input fabric_fpga_interrupt_in_i75;
-    input fabric_fpga_interrupt_in_i76;
-    input fabric_fpga_interrupt_in_i77;
-    input fabric_fpga_interrupt_in_i78;
-    input fabric_fpga_interrupt_in_i79;
-    input fabric_fpga_interrupt_in_i8;
-    input fabric_fpga_interrupt_in_i80;
-    input fabric_fpga_interrupt_in_i81;
-    input fabric_fpga_interrupt_in_i82;
-    input fabric_fpga_interrupt_in_i83;
-    input fabric_fpga_interrupt_in_i84;
-    input fabric_fpga_interrupt_in_i85;
-    input fabric_fpga_interrupt_in_i86;
-    input fabric_fpga_interrupt_in_i87;
-    input fabric_fpga_interrupt_in_i88;
-    input fabric_fpga_interrupt_in_i89;
-    input fabric_fpga_interrupt_in_i9;
-    input fabric_fpga_interrupt_in_i90;
-    input fabric_fpga_interrupt_in_i91;
-    input fabric_fpga_interrupt_in_i92;
-    input fabric_fpga_interrupt_in_i93;
-    input fabric_fpga_interrupt_in_i94;
-    input fabric_fpga_interrupt_in_i95;
-    input fabric_fpga_interrupt_in_i96;
-    input fabric_fpga_interrupt_in_i97;
-    input fabric_fpga_interrupt_in_i98;
-    input fabric_fpga_interrupt_in_i99;
-    input fabric_fpga_nic_rstn_i1;
-    input fabric_fpga_nic_rstn_i10;
-    input fabric_fpga_nic_rstn_i2;
-    input fabric_fpga_nic_rstn_i3;
-    input fabric_fpga_nic_rstn_i4;
-    input fabric_fpga_nic_rstn_i5;
-    input fabric_fpga_nic_rstn_i6;
-    input fabric_fpga_nic_rstn_i7;
-    input fabric_fpga_nic_rstn_i8;
-    input fabric_fpga_nic_rstn_i9;
-    output fabric_fpga_paddr_apb_o1;
-    output fabric_fpga_paddr_apb_o10;
-    output fabric_fpga_paddr_apb_o11;
-    output fabric_fpga_paddr_apb_o12;
-    output fabric_fpga_paddr_apb_o13;
-    output fabric_fpga_paddr_apb_o14;
-    output fabric_fpga_paddr_apb_o15;
-    output fabric_fpga_paddr_apb_o16;
-    output fabric_fpga_paddr_apb_o17;
-    output fabric_fpga_paddr_apb_o18;
-    output fabric_fpga_paddr_apb_o19;
-    output fabric_fpga_paddr_apb_o2;
-    output fabric_fpga_paddr_apb_o20;
-    output fabric_fpga_paddr_apb_o21;
-    output fabric_fpga_paddr_apb_o22;
-    output fabric_fpga_paddr_apb_o23;
-    output fabric_fpga_paddr_apb_o24;
-    output fabric_fpga_paddr_apb_o25;
-    output fabric_fpga_paddr_apb_o26;
-    output fabric_fpga_paddr_apb_o27;
-    output fabric_fpga_paddr_apb_o28;
-    output fabric_fpga_paddr_apb_o29;
-    output fabric_fpga_paddr_apb_o3;
-    output fabric_fpga_paddr_apb_o30;
-    output fabric_fpga_paddr_apb_o31;
-    output fabric_fpga_paddr_apb_o32;
-    output fabric_fpga_paddr_apb_o4;
-    output fabric_fpga_paddr_apb_o5;
-    output fabric_fpga_paddr_apb_o6;
-    output fabric_fpga_paddr_apb_o7;
-    output fabric_fpga_paddr_apb_o8;
-    output fabric_fpga_paddr_apb_o9;
-    output fabric_fpga_penable_apb_o;
-    input fabric_fpga_pmrstn_i;
-    input fabric_fpga_prdata_apb_i1;
-    input fabric_fpga_prdata_apb_i10;
-    input fabric_fpga_prdata_apb_i11;
-    input fabric_fpga_prdata_apb_i12;
-    input fabric_fpga_prdata_apb_i13;
-    input fabric_fpga_prdata_apb_i14;
-    input fabric_fpga_prdata_apb_i15;
-    input fabric_fpga_prdata_apb_i16;
-    input fabric_fpga_prdata_apb_i17;
-    input fabric_fpga_prdata_apb_i18;
-    input fabric_fpga_prdata_apb_i19;
-    input fabric_fpga_prdata_apb_i2;
-    input fabric_fpga_prdata_apb_i20;
-    input fabric_fpga_prdata_apb_i21;
-    input fabric_fpga_prdata_apb_i22;
-    input fabric_fpga_prdata_apb_i23;
-    input fabric_fpga_prdata_apb_i24;
-    input fabric_fpga_prdata_apb_i25;
-    input fabric_fpga_prdata_apb_i26;
-    input fabric_fpga_prdata_apb_i27;
-    input fabric_fpga_prdata_apb_i28;
-    input fabric_fpga_prdata_apb_i29;
-    input fabric_fpga_prdata_apb_i3;
-    input fabric_fpga_prdata_apb_i30;
-    input fabric_fpga_prdata_apb_i31;
-    input fabric_fpga_prdata_apb_i32;
-    input fabric_fpga_prdata_apb_i4;
-    input fabric_fpga_prdata_apb_i5;
-    input fabric_fpga_prdata_apb_i6;
-    input fabric_fpga_prdata_apb_i7;
-    input fabric_fpga_prdata_apb_i8;
-    input fabric_fpga_prdata_apb_i9;
-    input fabric_fpga_pready_apb_i;
-    output fabric_fpga_psel_apb_o;
-    input fabric_fpga_pslverr_apb_i;
-    output fabric_fpga_pwdata_apb_o1;
-    output fabric_fpga_pwdata_apb_o10;
-    output fabric_fpga_pwdata_apb_o11;
-    output fabric_fpga_pwdata_apb_o12;
-    output fabric_fpga_pwdata_apb_o13;
-    output fabric_fpga_pwdata_apb_o14;
-    output fabric_fpga_pwdata_apb_o15;
-    output fabric_fpga_pwdata_apb_o16;
-    output fabric_fpga_pwdata_apb_o17;
-    output fabric_fpga_pwdata_apb_o18;
-    output fabric_fpga_pwdata_apb_o19;
-    output fabric_fpga_pwdata_apb_o2;
-    output fabric_fpga_pwdata_apb_o20;
-    output fabric_fpga_pwdata_apb_o21;
-    output fabric_fpga_pwdata_apb_o22;
-    output fabric_fpga_pwdata_apb_o23;
-    output fabric_fpga_pwdata_apb_o24;
-    output fabric_fpga_pwdata_apb_o25;
-    output fabric_fpga_pwdata_apb_o26;
-    output fabric_fpga_pwdata_apb_o27;
-    output fabric_fpga_pwdata_apb_o28;
-    output fabric_fpga_pwdata_apb_o29;
-    output fabric_fpga_pwdata_apb_o3;
-    output fabric_fpga_pwdata_apb_o30;
-    output fabric_fpga_pwdata_apb_o31;
-    output fabric_fpga_pwdata_apb_o32;
-    output fabric_fpga_pwdata_apb_o4;
-    output fabric_fpga_pwdata_apb_o5;
-    output fabric_fpga_pwdata_apb_o6;
-    output fabric_fpga_pwdata_apb_o7;
-    output fabric_fpga_pwdata_apb_o8;
-    output fabric_fpga_pwdata_apb_o9;
-    output fabric_fpga_pwrite_apb_o;
-    output fabric_fpga_rdata_axi_m1_o1;
-    output fabric_fpga_rdata_axi_m1_o10;
-    output fabric_fpga_rdata_axi_m1_o100;
-    output fabric_fpga_rdata_axi_m1_o101;
-    output fabric_fpga_rdata_axi_m1_o102;
-    output fabric_fpga_rdata_axi_m1_o103;
-    output fabric_fpga_rdata_axi_m1_o104;
-    output fabric_fpga_rdata_axi_m1_o105;
-    output fabric_fpga_rdata_axi_m1_o106;
-    output fabric_fpga_rdata_axi_m1_o107;
-    output fabric_fpga_rdata_axi_m1_o108;
-    output fabric_fpga_rdata_axi_m1_o109;
-    output fabric_fpga_rdata_axi_m1_o11;
-    output fabric_fpga_rdata_axi_m1_o110;
-    output fabric_fpga_rdata_axi_m1_o111;
-    output fabric_fpga_rdata_axi_m1_o112;
-    output fabric_fpga_rdata_axi_m1_o113;
-    output fabric_fpga_rdata_axi_m1_o114;
-    output fabric_fpga_rdata_axi_m1_o115;
-    output fabric_fpga_rdata_axi_m1_o116;
-    output fabric_fpga_rdata_axi_m1_o117;
-    output fabric_fpga_rdata_axi_m1_o118;
-    output fabric_fpga_rdata_axi_m1_o119;
-    output fabric_fpga_rdata_axi_m1_o12;
-    output fabric_fpga_rdata_axi_m1_o120;
-    output fabric_fpga_rdata_axi_m1_o121;
-    output fabric_fpga_rdata_axi_m1_o122;
-    output fabric_fpga_rdata_axi_m1_o123;
-    output fabric_fpga_rdata_axi_m1_o124;
-    output fabric_fpga_rdata_axi_m1_o125;
-    output fabric_fpga_rdata_axi_m1_o126;
-    output fabric_fpga_rdata_axi_m1_o127;
-    output fabric_fpga_rdata_axi_m1_o128;
-    output fabric_fpga_rdata_axi_m1_o13;
-    output fabric_fpga_rdata_axi_m1_o14;
-    output fabric_fpga_rdata_axi_m1_o15;
-    output fabric_fpga_rdata_axi_m1_o16;
-    output fabric_fpga_rdata_axi_m1_o17;
-    output fabric_fpga_rdata_axi_m1_o18;
-    output fabric_fpga_rdata_axi_m1_o19;
-    output fabric_fpga_rdata_axi_m1_o2;
-    output fabric_fpga_rdata_axi_m1_o20;
-    output fabric_fpga_rdata_axi_m1_o21;
-    output fabric_fpga_rdata_axi_m1_o22;
-    output fabric_fpga_rdata_axi_m1_o23;
-    output fabric_fpga_rdata_axi_m1_o24;
-    output fabric_fpga_rdata_axi_m1_o25;
-    output fabric_fpga_rdata_axi_m1_o26;
-    output fabric_fpga_rdata_axi_m1_o27;
-    output fabric_fpga_rdata_axi_m1_o28;
-    output fabric_fpga_rdata_axi_m1_o29;
-    output fabric_fpga_rdata_axi_m1_o3;
-    output fabric_fpga_rdata_axi_m1_o30;
-    output fabric_fpga_rdata_axi_m1_o31;
-    output fabric_fpga_rdata_axi_m1_o32;
-    output fabric_fpga_rdata_axi_m1_o33;
-    output fabric_fpga_rdata_axi_m1_o34;
-    output fabric_fpga_rdata_axi_m1_o35;
-    output fabric_fpga_rdata_axi_m1_o36;
-    output fabric_fpga_rdata_axi_m1_o37;
-    output fabric_fpga_rdata_axi_m1_o38;
-    output fabric_fpga_rdata_axi_m1_o39;
-    output fabric_fpga_rdata_axi_m1_o4;
-    output fabric_fpga_rdata_axi_m1_o40;
-    output fabric_fpga_rdata_axi_m1_o41;
-    output fabric_fpga_rdata_axi_m1_o42;
-    output fabric_fpga_rdata_axi_m1_o43;
-    output fabric_fpga_rdata_axi_m1_o44;
-    output fabric_fpga_rdata_axi_m1_o45;
-    output fabric_fpga_rdata_axi_m1_o46;
-    output fabric_fpga_rdata_axi_m1_o47;
-    output fabric_fpga_rdata_axi_m1_o48;
-    output fabric_fpga_rdata_axi_m1_o49;
-    output fabric_fpga_rdata_axi_m1_o5;
-    output fabric_fpga_rdata_axi_m1_o50;
-    output fabric_fpga_rdata_axi_m1_o51;
-    output fabric_fpga_rdata_axi_m1_o52;
-    output fabric_fpga_rdata_axi_m1_o53;
-    output fabric_fpga_rdata_axi_m1_o54;
-    output fabric_fpga_rdata_axi_m1_o55;
-    output fabric_fpga_rdata_axi_m1_o56;
-    output fabric_fpga_rdata_axi_m1_o57;
-    output fabric_fpga_rdata_axi_m1_o58;
-    output fabric_fpga_rdata_axi_m1_o59;
-    output fabric_fpga_rdata_axi_m1_o6;
-    output fabric_fpga_rdata_axi_m1_o60;
-    output fabric_fpga_rdata_axi_m1_o61;
-    output fabric_fpga_rdata_axi_m1_o62;
-    output fabric_fpga_rdata_axi_m1_o63;
-    output fabric_fpga_rdata_axi_m1_o64;
-    output fabric_fpga_rdata_axi_m1_o65;
-    output fabric_fpga_rdata_axi_m1_o66;
-    output fabric_fpga_rdata_axi_m1_o67;
-    output fabric_fpga_rdata_axi_m1_o68;
-    output fabric_fpga_rdata_axi_m1_o69;
-    output fabric_fpga_rdata_axi_m1_o7;
-    output fabric_fpga_rdata_axi_m1_o70;
-    output fabric_fpga_rdata_axi_m1_o71;
-    output fabric_fpga_rdata_axi_m1_o72;
-    output fabric_fpga_rdata_axi_m1_o73;
-    output fabric_fpga_rdata_axi_m1_o74;
-    output fabric_fpga_rdata_axi_m1_o75;
-    output fabric_fpga_rdata_axi_m1_o76;
-    output fabric_fpga_rdata_axi_m1_o77;
-    output fabric_fpga_rdata_axi_m1_o78;
-    output fabric_fpga_rdata_axi_m1_o79;
-    output fabric_fpga_rdata_axi_m1_o8;
-    output fabric_fpga_rdata_axi_m1_o80;
-    output fabric_fpga_rdata_axi_m1_o81;
-    output fabric_fpga_rdata_axi_m1_o82;
-    output fabric_fpga_rdata_axi_m1_o83;
-    output fabric_fpga_rdata_axi_m1_o84;
-    output fabric_fpga_rdata_axi_m1_o85;
-    output fabric_fpga_rdata_axi_m1_o86;
-    output fabric_fpga_rdata_axi_m1_o87;
-    output fabric_fpga_rdata_axi_m1_o88;
-    output fabric_fpga_rdata_axi_m1_o89;
-    output fabric_fpga_rdata_axi_m1_o9;
-    output fabric_fpga_rdata_axi_m1_o90;
-    output fabric_fpga_rdata_axi_m1_o91;
-    output fabric_fpga_rdata_axi_m1_o92;
-    output fabric_fpga_rdata_axi_m1_o93;
-    output fabric_fpga_rdata_axi_m1_o94;
-    output fabric_fpga_rdata_axi_m1_o95;
-    output fabric_fpga_rdata_axi_m1_o96;
-    output fabric_fpga_rdata_axi_m1_o97;
-    output fabric_fpga_rdata_axi_m1_o98;
-    output fabric_fpga_rdata_axi_m1_o99;
-    output fabric_fpga_rdata_axi_m2_o1;
-    output fabric_fpga_rdata_axi_m2_o10;
-    output fabric_fpga_rdata_axi_m2_o100;
-    output fabric_fpga_rdata_axi_m2_o101;
-    output fabric_fpga_rdata_axi_m2_o102;
-    output fabric_fpga_rdata_axi_m2_o103;
-    output fabric_fpga_rdata_axi_m2_o104;
-    output fabric_fpga_rdata_axi_m2_o105;
-    output fabric_fpga_rdata_axi_m2_o106;
-    output fabric_fpga_rdata_axi_m2_o107;
-    output fabric_fpga_rdata_axi_m2_o108;
-    output fabric_fpga_rdata_axi_m2_o109;
-    output fabric_fpga_rdata_axi_m2_o11;
-    output fabric_fpga_rdata_axi_m2_o110;
-    output fabric_fpga_rdata_axi_m2_o111;
-    output fabric_fpga_rdata_axi_m2_o112;
-    output fabric_fpga_rdata_axi_m2_o113;
-    output fabric_fpga_rdata_axi_m2_o114;
-    output fabric_fpga_rdata_axi_m2_o115;
-    output fabric_fpga_rdata_axi_m2_o116;
-    output fabric_fpga_rdata_axi_m2_o117;
-    output fabric_fpga_rdata_axi_m2_o118;
-    output fabric_fpga_rdata_axi_m2_o119;
-    output fabric_fpga_rdata_axi_m2_o12;
-    output fabric_fpga_rdata_axi_m2_o120;
-    output fabric_fpga_rdata_axi_m2_o121;
-    output fabric_fpga_rdata_axi_m2_o122;
-    output fabric_fpga_rdata_axi_m2_o123;
-    output fabric_fpga_rdata_axi_m2_o124;
-    output fabric_fpga_rdata_axi_m2_o125;
-    output fabric_fpga_rdata_axi_m2_o126;
-    output fabric_fpga_rdata_axi_m2_o127;
-    output fabric_fpga_rdata_axi_m2_o128;
-    output fabric_fpga_rdata_axi_m2_o13;
-    output fabric_fpga_rdata_axi_m2_o14;
-    output fabric_fpga_rdata_axi_m2_o15;
-    output fabric_fpga_rdata_axi_m2_o16;
-    output fabric_fpga_rdata_axi_m2_o17;
-    output fabric_fpga_rdata_axi_m2_o18;
-    output fabric_fpga_rdata_axi_m2_o19;
-    output fabric_fpga_rdata_axi_m2_o2;
-    output fabric_fpga_rdata_axi_m2_o20;
-    output fabric_fpga_rdata_axi_m2_o21;
-    output fabric_fpga_rdata_axi_m2_o22;
-    output fabric_fpga_rdata_axi_m2_o23;
-    output fabric_fpga_rdata_axi_m2_o24;
-    output fabric_fpga_rdata_axi_m2_o25;
-    output fabric_fpga_rdata_axi_m2_o26;
-    output fabric_fpga_rdata_axi_m2_o27;
-    output fabric_fpga_rdata_axi_m2_o28;
-    output fabric_fpga_rdata_axi_m2_o29;
-    output fabric_fpga_rdata_axi_m2_o3;
-    output fabric_fpga_rdata_axi_m2_o30;
-    output fabric_fpga_rdata_axi_m2_o31;
-    output fabric_fpga_rdata_axi_m2_o32;
-    output fabric_fpga_rdata_axi_m2_o33;
-    output fabric_fpga_rdata_axi_m2_o34;
-    output fabric_fpga_rdata_axi_m2_o35;
-    output fabric_fpga_rdata_axi_m2_o36;
-    output fabric_fpga_rdata_axi_m2_o37;
-    output fabric_fpga_rdata_axi_m2_o38;
-    output fabric_fpga_rdata_axi_m2_o39;
-    output fabric_fpga_rdata_axi_m2_o4;
-    output fabric_fpga_rdata_axi_m2_o40;
-    output fabric_fpga_rdata_axi_m2_o41;
-    output fabric_fpga_rdata_axi_m2_o42;
-    output fabric_fpga_rdata_axi_m2_o43;
-    output fabric_fpga_rdata_axi_m2_o44;
-    output fabric_fpga_rdata_axi_m2_o45;
-    output fabric_fpga_rdata_axi_m2_o46;
-    output fabric_fpga_rdata_axi_m2_o47;
-    output fabric_fpga_rdata_axi_m2_o48;
-    output fabric_fpga_rdata_axi_m2_o49;
-    output fabric_fpga_rdata_axi_m2_o5;
-    output fabric_fpga_rdata_axi_m2_o50;
-    output fabric_fpga_rdata_axi_m2_o51;
-    output fabric_fpga_rdata_axi_m2_o52;
-    output fabric_fpga_rdata_axi_m2_o53;
-    output fabric_fpga_rdata_axi_m2_o54;
-    output fabric_fpga_rdata_axi_m2_o55;
-    output fabric_fpga_rdata_axi_m2_o56;
-    output fabric_fpga_rdata_axi_m2_o57;
-    output fabric_fpga_rdata_axi_m2_o58;
-    output fabric_fpga_rdata_axi_m2_o59;
-    output fabric_fpga_rdata_axi_m2_o6;
-    output fabric_fpga_rdata_axi_m2_o60;
-    output fabric_fpga_rdata_axi_m2_o61;
-    output fabric_fpga_rdata_axi_m2_o62;
-    output fabric_fpga_rdata_axi_m2_o63;
-    output fabric_fpga_rdata_axi_m2_o64;
-    output fabric_fpga_rdata_axi_m2_o65;
-    output fabric_fpga_rdata_axi_m2_o66;
-    output fabric_fpga_rdata_axi_m2_o67;
-    output fabric_fpga_rdata_axi_m2_o68;
-    output fabric_fpga_rdata_axi_m2_o69;
-    output fabric_fpga_rdata_axi_m2_o7;
-    output fabric_fpga_rdata_axi_m2_o70;
-    output fabric_fpga_rdata_axi_m2_o71;
-    output fabric_fpga_rdata_axi_m2_o72;
-    output fabric_fpga_rdata_axi_m2_o73;
-    output fabric_fpga_rdata_axi_m2_o74;
-    output fabric_fpga_rdata_axi_m2_o75;
-    output fabric_fpga_rdata_axi_m2_o76;
-    output fabric_fpga_rdata_axi_m2_o77;
-    output fabric_fpga_rdata_axi_m2_o78;
-    output fabric_fpga_rdata_axi_m2_o79;
-    output fabric_fpga_rdata_axi_m2_o8;
-    output fabric_fpga_rdata_axi_m2_o80;
-    output fabric_fpga_rdata_axi_m2_o81;
-    output fabric_fpga_rdata_axi_m2_o82;
-    output fabric_fpga_rdata_axi_m2_o83;
-    output fabric_fpga_rdata_axi_m2_o84;
-    output fabric_fpga_rdata_axi_m2_o85;
-    output fabric_fpga_rdata_axi_m2_o86;
-    output fabric_fpga_rdata_axi_m2_o87;
-    output fabric_fpga_rdata_axi_m2_o88;
-    output fabric_fpga_rdata_axi_m2_o89;
-    output fabric_fpga_rdata_axi_m2_o9;
-    output fabric_fpga_rdata_axi_m2_o90;
-    output fabric_fpga_rdata_axi_m2_o91;
-    output fabric_fpga_rdata_axi_m2_o92;
-    output fabric_fpga_rdata_axi_m2_o93;
-    output fabric_fpga_rdata_axi_m2_o94;
-    output fabric_fpga_rdata_axi_m2_o95;
-    output fabric_fpga_rdata_axi_m2_o96;
-    output fabric_fpga_rdata_axi_m2_o97;
-    output fabric_fpga_rdata_axi_m2_o98;
-    output fabric_fpga_rdata_axi_m2_o99;
-    input fabric_fpga_rdata_axi_s1_i1;
-    input fabric_fpga_rdata_axi_s1_i10;
-    input fabric_fpga_rdata_axi_s1_i100;
-    input fabric_fpga_rdata_axi_s1_i101;
-    input fabric_fpga_rdata_axi_s1_i102;
-    input fabric_fpga_rdata_axi_s1_i103;
-    input fabric_fpga_rdata_axi_s1_i104;
-    input fabric_fpga_rdata_axi_s1_i105;
-    input fabric_fpga_rdata_axi_s1_i106;
-    input fabric_fpga_rdata_axi_s1_i107;
-    input fabric_fpga_rdata_axi_s1_i108;
-    input fabric_fpga_rdata_axi_s1_i109;
-    input fabric_fpga_rdata_axi_s1_i11;
-    input fabric_fpga_rdata_axi_s1_i110;
-    input fabric_fpga_rdata_axi_s1_i111;
-    input fabric_fpga_rdata_axi_s1_i112;
-    input fabric_fpga_rdata_axi_s1_i113;
-    input fabric_fpga_rdata_axi_s1_i114;
-    input fabric_fpga_rdata_axi_s1_i115;
-    input fabric_fpga_rdata_axi_s1_i116;
-    input fabric_fpga_rdata_axi_s1_i117;
-    input fabric_fpga_rdata_axi_s1_i118;
-    input fabric_fpga_rdata_axi_s1_i119;
-    input fabric_fpga_rdata_axi_s1_i12;
-    input fabric_fpga_rdata_axi_s1_i120;
-    input fabric_fpga_rdata_axi_s1_i121;
-    input fabric_fpga_rdata_axi_s1_i122;
-    input fabric_fpga_rdata_axi_s1_i123;
-    input fabric_fpga_rdata_axi_s1_i124;
-    input fabric_fpga_rdata_axi_s1_i125;
-    input fabric_fpga_rdata_axi_s1_i126;
-    input fabric_fpga_rdata_axi_s1_i127;
-    input fabric_fpga_rdata_axi_s1_i128;
-    input fabric_fpga_rdata_axi_s1_i13;
-    input fabric_fpga_rdata_axi_s1_i14;
-    input fabric_fpga_rdata_axi_s1_i15;
-    input fabric_fpga_rdata_axi_s1_i16;
-    input fabric_fpga_rdata_axi_s1_i17;
-    input fabric_fpga_rdata_axi_s1_i18;
-    input fabric_fpga_rdata_axi_s1_i19;
-    input fabric_fpga_rdata_axi_s1_i2;
-    input fabric_fpga_rdata_axi_s1_i20;
-    input fabric_fpga_rdata_axi_s1_i21;
-    input fabric_fpga_rdata_axi_s1_i22;
-    input fabric_fpga_rdata_axi_s1_i23;
-    input fabric_fpga_rdata_axi_s1_i24;
-    input fabric_fpga_rdata_axi_s1_i25;
-    input fabric_fpga_rdata_axi_s1_i26;
-    input fabric_fpga_rdata_axi_s1_i27;
-    input fabric_fpga_rdata_axi_s1_i28;
-    input fabric_fpga_rdata_axi_s1_i29;
-    input fabric_fpga_rdata_axi_s1_i3;
-    input fabric_fpga_rdata_axi_s1_i30;
-    input fabric_fpga_rdata_axi_s1_i31;
-    input fabric_fpga_rdata_axi_s1_i32;
-    input fabric_fpga_rdata_axi_s1_i33;
-    input fabric_fpga_rdata_axi_s1_i34;
-    input fabric_fpga_rdata_axi_s1_i35;
-    input fabric_fpga_rdata_axi_s1_i36;
-    input fabric_fpga_rdata_axi_s1_i37;
-    input fabric_fpga_rdata_axi_s1_i38;
-    input fabric_fpga_rdata_axi_s1_i39;
-    input fabric_fpga_rdata_axi_s1_i4;
-    input fabric_fpga_rdata_axi_s1_i40;
-    input fabric_fpga_rdata_axi_s1_i41;
-    input fabric_fpga_rdata_axi_s1_i42;
-    input fabric_fpga_rdata_axi_s1_i43;
-    input fabric_fpga_rdata_axi_s1_i44;
-    input fabric_fpga_rdata_axi_s1_i45;
-    input fabric_fpga_rdata_axi_s1_i46;
-    input fabric_fpga_rdata_axi_s1_i47;
-    input fabric_fpga_rdata_axi_s1_i48;
-    input fabric_fpga_rdata_axi_s1_i49;
-    input fabric_fpga_rdata_axi_s1_i5;
-    input fabric_fpga_rdata_axi_s1_i50;
-    input fabric_fpga_rdata_axi_s1_i51;
-    input fabric_fpga_rdata_axi_s1_i52;
-    input fabric_fpga_rdata_axi_s1_i53;
-    input fabric_fpga_rdata_axi_s1_i54;
-    input fabric_fpga_rdata_axi_s1_i55;
-    input fabric_fpga_rdata_axi_s1_i56;
-    input fabric_fpga_rdata_axi_s1_i57;
-    input fabric_fpga_rdata_axi_s1_i58;
-    input fabric_fpga_rdata_axi_s1_i59;
-    input fabric_fpga_rdata_axi_s1_i6;
-    input fabric_fpga_rdata_axi_s1_i60;
-    input fabric_fpga_rdata_axi_s1_i61;
-    input fabric_fpga_rdata_axi_s1_i62;
-    input fabric_fpga_rdata_axi_s1_i63;
-    input fabric_fpga_rdata_axi_s1_i64;
-    input fabric_fpga_rdata_axi_s1_i65;
-    input fabric_fpga_rdata_axi_s1_i66;
-    input fabric_fpga_rdata_axi_s1_i67;
-    input fabric_fpga_rdata_axi_s1_i68;
-    input fabric_fpga_rdata_axi_s1_i69;
-    input fabric_fpga_rdata_axi_s1_i7;
-    input fabric_fpga_rdata_axi_s1_i70;
-    input fabric_fpga_rdata_axi_s1_i71;
-    input fabric_fpga_rdata_axi_s1_i72;
-    input fabric_fpga_rdata_axi_s1_i73;
-    input fabric_fpga_rdata_axi_s1_i74;
-    input fabric_fpga_rdata_axi_s1_i75;
-    input fabric_fpga_rdata_axi_s1_i76;
-    input fabric_fpga_rdata_axi_s1_i77;
-    input fabric_fpga_rdata_axi_s1_i78;
-    input fabric_fpga_rdata_axi_s1_i79;
-    input fabric_fpga_rdata_axi_s1_i8;
-    input fabric_fpga_rdata_axi_s1_i80;
-    input fabric_fpga_rdata_axi_s1_i81;
-    input fabric_fpga_rdata_axi_s1_i82;
-    input fabric_fpga_rdata_axi_s1_i83;
-    input fabric_fpga_rdata_axi_s1_i84;
-    input fabric_fpga_rdata_axi_s1_i85;
-    input fabric_fpga_rdata_axi_s1_i86;
-    input fabric_fpga_rdata_axi_s1_i87;
-    input fabric_fpga_rdata_axi_s1_i88;
-    input fabric_fpga_rdata_axi_s1_i89;
-    input fabric_fpga_rdata_axi_s1_i9;
-    input fabric_fpga_rdata_axi_s1_i90;
-    input fabric_fpga_rdata_axi_s1_i91;
-    input fabric_fpga_rdata_axi_s1_i92;
-    input fabric_fpga_rdata_axi_s1_i93;
-    input fabric_fpga_rdata_axi_s1_i94;
-    input fabric_fpga_rdata_axi_s1_i95;
-    input fabric_fpga_rdata_axi_s1_i96;
-    input fabric_fpga_rdata_axi_s1_i97;
-    input fabric_fpga_rdata_axi_s1_i98;
-    input fabric_fpga_rdata_axi_s1_i99;
-    input fabric_fpga_rdata_axi_s2_i1;
-    input fabric_fpga_rdata_axi_s2_i10;
-    input fabric_fpga_rdata_axi_s2_i100;
-    input fabric_fpga_rdata_axi_s2_i101;
-    input fabric_fpga_rdata_axi_s2_i102;
-    input fabric_fpga_rdata_axi_s2_i103;
-    input fabric_fpga_rdata_axi_s2_i104;
-    input fabric_fpga_rdata_axi_s2_i105;
-    input fabric_fpga_rdata_axi_s2_i106;
-    input fabric_fpga_rdata_axi_s2_i107;
-    input fabric_fpga_rdata_axi_s2_i108;
-    input fabric_fpga_rdata_axi_s2_i109;
-    input fabric_fpga_rdata_axi_s2_i11;
-    input fabric_fpga_rdata_axi_s2_i110;
-    input fabric_fpga_rdata_axi_s2_i111;
-    input fabric_fpga_rdata_axi_s2_i112;
-    input fabric_fpga_rdata_axi_s2_i113;
-    input fabric_fpga_rdata_axi_s2_i114;
-    input fabric_fpga_rdata_axi_s2_i115;
-    input fabric_fpga_rdata_axi_s2_i116;
-    input fabric_fpga_rdata_axi_s2_i117;
-    input fabric_fpga_rdata_axi_s2_i118;
-    input fabric_fpga_rdata_axi_s2_i119;
-    input fabric_fpga_rdata_axi_s2_i12;
-    input fabric_fpga_rdata_axi_s2_i120;
-    input fabric_fpga_rdata_axi_s2_i121;
-    input fabric_fpga_rdata_axi_s2_i122;
-    input fabric_fpga_rdata_axi_s2_i123;
-    input fabric_fpga_rdata_axi_s2_i124;
-    input fabric_fpga_rdata_axi_s2_i125;
-    input fabric_fpga_rdata_axi_s2_i126;
-    input fabric_fpga_rdata_axi_s2_i127;
-    input fabric_fpga_rdata_axi_s2_i128;
-    input fabric_fpga_rdata_axi_s2_i13;
-    input fabric_fpga_rdata_axi_s2_i14;
-    input fabric_fpga_rdata_axi_s2_i15;
-    input fabric_fpga_rdata_axi_s2_i16;
-    input fabric_fpga_rdata_axi_s2_i17;
-    input fabric_fpga_rdata_axi_s2_i18;
-    input fabric_fpga_rdata_axi_s2_i19;
-    input fabric_fpga_rdata_axi_s2_i2;
-    input fabric_fpga_rdata_axi_s2_i20;
-    input fabric_fpga_rdata_axi_s2_i21;
-    input fabric_fpga_rdata_axi_s2_i22;
-    input fabric_fpga_rdata_axi_s2_i23;
-    input fabric_fpga_rdata_axi_s2_i24;
-    input fabric_fpga_rdata_axi_s2_i25;
-    input fabric_fpga_rdata_axi_s2_i26;
-    input fabric_fpga_rdata_axi_s2_i27;
-    input fabric_fpga_rdata_axi_s2_i28;
-    input fabric_fpga_rdata_axi_s2_i29;
-    input fabric_fpga_rdata_axi_s2_i3;
-    input fabric_fpga_rdata_axi_s2_i30;
-    input fabric_fpga_rdata_axi_s2_i31;
-    input fabric_fpga_rdata_axi_s2_i32;
-    input fabric_fpga_rdata_axi_s2_i33;
-    input fabric_fpga_rdata_axi_s2_i34;
-    input fabric_fpga_rdata_axi_s2_i35;
-    input fabric_fpga_rdata_axi_s2_i36;
-    input fabric_fpga_rdata_axi_s2_i37;
-    input fabric_fpga_rdata_axi_s2_i38;
-    input fabric_fpga_rdata_axi_s2_i39;
-    input fabric_fpga_rdata_axi_s2_i4;
-    input fabric_fpga_rdata_axi_s2_i40;
-    input fabric_fpga_rdata_axi_s2_i41;
-    input fabric_fpga_rdata_axi_s2_i42;
-    input fabric_fpga_rdata_axi_s2_i43;
-    input fabric_fpga_rdata_axi_s2_i44;
-    input fabric_fpga_rdata_axi_s2_i45;
-    input fabric_fpga_rdata_axi_s2_i46;
-    input fabric_fpga_rdata_axi_s2_i47;
-    input fabric_fpga_rdata_axi_s2_i48;
-    input fabric_fpga_rdata_axi_s2_i49;
-    input fabric_fpga_rdata_axi_s2_i5;
-    input fabric_fpga_rdata_axi_s2_i50;
-    input fabric_fpga_rdata_axi_s2_i51;
-    input fabric_fpga_rdata_axi_s2_i52;
-    input fabric_fpga_rdata_axi_s2_i53;
-    input fabric_fpga_rdata_axi_s2_i54;
-    input fabric_fpga_rdata_axi_s2_i55;
-    input fabric_fpga_rdata_axi_s2_i56;
-    input fabric_fpga_rdata_axi_s2_i57;
-    input fabric_fpga_rdata_axi_s2_i58;
-    input fabric_fpga_rdata_axi_s2_i59;
-    input fabric_fpga_rdata_axi_s2_i6;
-    input fabric_fpga_rdata_axi_s2_i60;
-    input fabric_fpga_rdata_axi_s2_i61;
-    input fabric_fpga_rdata_axi_s2_i62;
-    input fabric_fpga_rdata_axi_s2_i63;
-    input fabric_fpga_rdata_axi_s2_i64;
-    input fabric_fpga_rdata_axi_s2_i65;
-    input fabric_fpga_rdata_axi_s2_i66;
-    input fabric_fpga_rdata_axi_s2_i67;
-    input fabric_fpga_rdata_axi_s2_i68;
-    input fabric_fpga_rdata_axi_s2_i69;
-    input fabric_fpga_rdata_axi_s2_i7;
-    input fabric_fpga_rdata_axi_s2_i70;
-    input fabric_fpga_rdata_axi_s2_i71;
-    input fabric_fpga_rdata_axi_s2_i72;
-    input fabric_fpga_rdata_axi_s2_i73;
-    input fabric_fpga_rdata_axi_s2_i74;
-    input fabric_fpga_rdata_axi_s2_i75;
-    input fabric_fpga_rdata_axi_s2_i76;
-    input fabric_fpga_rdata_axi_s2_i77;
-    input fabric_fpga_rdata_axi_s2_i78;
-    input fabric_fpga_rdata_axi_s2_i79;
-    input fabric_fpga_rdata_axi_s2_i8;
-    input fabric_fpga_rdata_axi_s2_i80;
-    input fabric_fpga_rdata_axi_s2_i81;
-    input fabric_fpga_rdata_axi_s2_i82;
-    input fabric_fpga_rdata_axi_s2_i83;
-    input fabric_fpga_rdata_axi_s2_i84;
-    input fabric_fpga_rdata_axi_s2_i85;
-    input fabric_fpga_rdata_axi_s2_i86;
-    input fabric_fpga_rdata_axi_s2_i87;
-    input fabric_fpga_rdata_axi_s2_i88;
-    input fabric_fpga_rdata_axi_s2_i89;
-    input fabric_fpga_rdata_axi_s2_i9;
-    input fabric_fpga_rdata_axi_s2_i90;
-    input fabric_fpga_rdata_axi_s2_i91;
-    input fabric_fpga_rdata_axi_s2_i92;
-    input fabric_fpga_rdata_axi_s2_i93;
-    input fabric_fpga_rdata_axi_s2_i94;
-    input fabric_fpga_rdata_axi_s2_i95;
-    input fabric_fpga_rdata_axi_s2_i96;
-    input fabric_fpga_rdata_axi_s2_i97;
-    input fabric_fpga_rdata_axi_s2_i98;
-    input fabric_fpga_rdata_axi_s2_i99;
-    output fabric_fpga_rid_axi_m1_o1;
-    output fabric_fpga_rid_axi_m1_o2;
-    output fabric_fpga_rid_axi_m1_o3;
-    output fabric_fpga_rid_axi_m1_o4;
-    output fabric_fpga_rid_axi_m1_o5;
-    output fabric_fpga_rid_axi_m2_o1;
-    output fabric_fpga_rid_axi_m2_o2;
-    output fabric_fpga_rid_axi_m2_o3;
-    output fabric_fpga_rid_axi_m2_o4;
-    output fabric_fpga_rid_axi_m2_o5;
-    input fabric_fpga_rid_axi_s1_i1;
-    input fabric_fpga_rid_axi_s1_i10;
-    input fabric_fpga_rid_axi_s1_i11;
-    input fabric_fpga_rid_axi_s1_i12;
-    input fabric_fpga_rid_axi_s1_i2;
-    input fabric_fpga_rid_axi_s1_i3;
-    input fabric_fpga_rid_axi_s1_i4;
-    input fabric_fpga_rid_axi_s1_i5;
-    input fabric_fpga_rid_axi_s1_i6;
-    input fabric_fpga_rid_axi_s1_i7;
-    input fabric_fpga_rid_axi_s1_i8;
-    input fabric_fpga_rid_axi_s1_i9;
-    input fabric_fpga_rid_axi_s2_i1;
-    input fabric_fpga_rid_axi_s2_i10;
-    input fabric_fpga_rid_axi_s2_i11;
-    input fabric_fpga_rid_axi_s2_i12;
-    input fabric_fpga_rid_axi_s2_i2;
-    input fabric_fpga_rid_axi_s2_i3;
-    input fabric_fpga_rid_axi_s2_i4;
-    input fabric_fpga_rid_axi_s2_i5;
-    input fabric_fpga_rid_axi_s2_i6;
-    input fabric_fpga_rid_axi_s2_i7;
-    input fabric_fpga_rid_axi_s2_i8;
-    input fabric_fpga_rid_axi_s2_i9;
-    output fabric_fpga_rlast_axi_m1_o;
-    output fabric_fpga_rlast_axi_m2_o;
-    input fabric_fpga_rlast_axi_s1_i;
-    input fabric_fpga_rlast_axi_s2_i;
-    input fabric_fpga_rready_axi_m1_i;
-    input fabric_fpga_rready_axi_m2_i;
-    output fabric_fpga_rready_axi_s1_o;
-    output fabric_fpga_rready_axi_s2_o;
-    output fabric_fpga_rresp_axi_m1_o1;
-    output fabric_fpga_rresp_axi_m1_o2;
-    output fabric_fpga_rresp_axi_m2_o1;
-    output fabric_fpga_rresp_axi_m2_o2;
-    input fabric_fpga_rresp_axi_s1_i1;
-    input fabric_fpga_rresp_axi_s1_i2;
-    input fabric_fpga_rresp_axi_s2_i1;
-    input fabric_fpga_rresp_axi_s2_i2;
-    output fabric_fpga_rvalid_axi_m1_o;
-    output fabric_fpga_rvalid_axi_m2_o;
-    input fabric_fpga_rvalid_axi_s1_i;
-    input fabric_fpga_rvalid_axi_s2_i;
-    input fabric_fpga_sysrstn_i;
-    output fabric_fpga_trigger_in_o1;
-    output fabric_fpga_trigger_in_o2;
-    output fabric_fpga_trigger_in_o3;
-    output fabric_fpga_trigger_in_o4;
-    output fabric_fpga_trigger_in_o5;
-    output fabric_fpga_trigger_in_o6;
-    output fabric_fpga_trigger_in_o7;
-    output fabric_fpga_trigger_in_o8;
-    input fabric_fpga_trigger_out_i1;
-    input fabric_fpga_trigger_out_i2;
-    input fabric_fpga_trigger_out_i3;
-    input fabric_fpga_trigger_out_i4;
-    input fabric_fpga_trigger_out_i5;
-    input fabric_fpga_trigger_out_i6;
-    input fabric_fpga_trigger_out_i7;
-    input fabric_fpga_trigger_out_i8;
-    input fabric_fpga_wdata_axi_m1_i1;
-    input fabric_fpga_wdata_axi_m1_i10;
-    input fabric_fpga_wdata_axi_m1_i100;
-    input fabric_fpga_wdata_axi_m1_i101;
-    input fabric_fpga_wdata_axi_m1_i102;
-    input fabric_fpga_wdata_axi_m1_i103;
-    input fabric_fpga_wdata_axi_m1_i104;
-    input fabric_fpga_wdata_axi_m1_i105;
-    input fabric_fpga_wdata_axi_m1_i106;
-    input fabric_fpga_wdata_axi_m1_i107;
-    input fabric_fpga_wdata_axi_m1_i108;
-    input fabric_fpga_wdata_axi_m1_i109;
-    input fabric_fpga_wdata_axi_m1_i11;
-    input fabric_fpga_wdata_axi_m1_i110;
-    input fabric_fpga_wdata_axi_m1_i111;
-    input fabric_fpga_wdata_axi_m1_i112;
-    input fabric_fpga_wdata_axi_m1_i113;
-    input fabric_fpga_wdata_axi_m1_i114;
-    input fabric_fpga_wdata_axi_m1_i115;
-    input fabric_fpga_wdata_axi_m1_i116;
-    input fabric_fpga_wdata_axi_m1_i117;
-    input fabric_fpga_wdata_axi_m1_i118;
-    input fabric_fpga_wdata_axi_m1_i119;
-    input fabric_fpga_wdata_axi_m1_i12;
-    input fabric_fpga_wdata_axi_m1_i120;
-    input fabric_fpga_wdata_axi_m1_i121;
-    input fabric_fpga_wdata_axi_m1_i122;
-    input fabric_fpga_wdata_axi_m1_i123;
-    input fabric_fpga_wdata_axi_m1_i124;
-    input fabric_fpga_wdata_axi_m1_i125;
-    input fabric_fpga_wdata_axi_m1_i126;
-    input fabric_fpga_wdata_axi_m1_i127;
-    input fabric_fpga_wdata_axi_m1_i128;
-    input fabric_fpga_wdata_axi_m1_i13;
-    input fabric_fpga_wdata_axi_m1_i14;
-    input fabric_fpga_wdata_axi_m1_i15;
-    input fabric_fpga_wdata_axi_m1_i16;
-    input fabric_fpga_wdata_axi_m1_i17;
-    input fabric_fpga_wdata_axi_m1_i18;
-    input fabric_fpga_wdata_axi_m1_i19;
-    input fabric_fpga_wdata_axi_m1_i2;
-    input fabric_fpga_wdata_axi_m1_i20;
-    input fabric_fpga_wdata_axi_m1_i21;
-    input fabric_fpga_wdata_axi_m1_i22;
-    input fabric_fpga_wdata_axi_m1_i23;
-    input fabric_fpga_wdata_axi_m1_i24;
-    input fabric_fpga_wdata_axi_m1_i25;
-    input fabric_fpga_wdata_axi_m1_i26;
-    input fabric_fpga_wdata_axi_m1_i27;
-    input fabric_fpga_wdata_axi_m1_i28;
-    input fabric_fpga_wdata_axi_m1_i29;
-    input fabric_fpga_wdata_axi_m1_i3;
-    input fabric_fpga_wdata_axi_m1_i30;
-    input fabric_fpga_wdata_axi_m1_i31;
-    input fabric_fpga_wdata_axi_m1_i32;
-    input fabric_fpga_wdata_axi_m1_i33;
-    input fabric_fpga_wdata_axi_m1_i34;
-    input fabric_fpga_wdata_axi_m1_i35;
-    input fabric_fpga_wdata_axi_m1_i36;
-    input fabric_fpga_wdata_axi_m1_i37;
-    input fabric_fpga_wdata_axi_m1_i38;
-    input fabric_fpga_wdata_axi_m1_i39;
-    input fabric_fpga_wdata_axi_m1_i4;
-    input fabric_fpga_wdata_axi_m1_i40;
-    input fabric_fpga_wdata_axi_m1_i41;
-    input fabric_fpga_wdata_axi_m1_i42;
-    input fabric_fpga_wdata_axi_m1_i43;
-    input fabric_fpga_wdata_axi_m1_i44;
-    input fabric_fpga_wdata_axi_m1_i45;
-    input fabric_fpga_wdata_axi_m1_i46;
-    input fabric_fpga_wdata_axi_m1_i47;
-    input fabric_fpga_wdata_axi_m1_i48;
-    input fabric_fpga_wdata_axi_m1_i49;
-    input fabric_fpga_wdata_axi_m1_i5;
-    input fabric_fpga_wdata_axi_m1_i50;
-    input fabric_fpga_wdata_axi_m1_i51;
-    input fabric_fpga_wdata_axi_m1_i52;
-    input fabric_fpga_wdata_axi_m1_i53;
-    input fabric_fpga_wdata_axi_m1_i54;
-    input fabric_fpga_wdata_axi_m1_i55;
-    input fabric_fpga_wdata_axi_m1_i56;
-    input fabric_fpga_wdata_axi_m1_i57;
-    input fabric_fpga_wdata_axi_m1_i58;
-    input fabric_fpga_wdata_axi_m1_i59;
-    input fabric_fpga_wdata_axi_m1_i6;
-    input fabric_fpga_wdata_axi_m1_i60;
-    input fabric_fpga_wdata_axi_m1_i61;
-    input fabric_fpga_wdata_axi_m1_i62;
-    input fabric_fpga_wdata_axi_m1_i63;
-    input fabric_fpga_wdata_axi_m1_i64;
-    input fabric_fpga_wdata_axi_m1_i65;
-    input fabric_fpga_wdata_axi_m1_i66;
-    input fabric_fpga_wdata_axi_m1_i67;
-    input fabric_fpga_wdata_axi_m1_i68;
-    input fabric_fpga_wdata_axi_m1_i69;
-    input fabric_fpga_wdata_axi_m1_i7;
-    input fabric_fpga_wdata_axi_m1_i70;
-    input fabric_fpga_wdata_axi_m1_i71;
-    input fabric_fpga_wdata_axi_m1_i72;
-    input fabric_fpga_wdata_axi_m1_i73;
-    input fabric_fpga_wdata_axi_m1_i74;
-    input fabric_fpga_wdata_axi_m1_i75;
-    input fabric_fpga_wdata_axi_m1_i76;
-    input fabric_fpga_wdata_axi_m1_i77;
-    input fabric_fpga_wdata_axi_m1_i78;
-    input fabric_fpga_wdata_axi_m1_i79;
-    input fabric_fpga_wdata_axi_m1_i8;
-    input fabric_fpga_wdata_axi_m1_i80;
-    input fabric_fpga_wdata_axi_m1_i81;
-    input fabric_fpga_wdata_axi_m1_i82;
-    input fabric_fpga_wdata_axi_m1_i83;
-    input fabric_fpga_wdata_axi_m1_i84;
-    input fabric_fpga_wdata_axi_m1_i85;
-    input fabric_fpga_wdata_axi_m1_i86;
-    input fabric_fpga_wdata_axi_m1_i87;
-    input fabric_fpga_wdata_axi_m1_i88;
-    input fabric_fpga_wdata_axi_m1_i89;
-    input fabric_fpga_wdata_axi_m1_i9;
-    input fabric_fpga_wdata_axi_m1_i90;
-    input fabric_fpga_wdata_axi_m1_i91;
-    input fabric_fpga_wdata_axi_m1_i92;
-    input fabric_fpga_wdata_axi_m1_i93;
-    input fabric_fpga_wdata_axi_m1_i94;
-    input fabric_fpga_wdata_axi_m1_i95;
-    input fabric_fpga_wdata_axi_m1_i96;
-    input fabric_fpga_wdata_axi_m1_i97;
-    input fabric_fpga_wdata_axi_m1_i98;
-    input fabric_fpga_wdata_axi_m1_i99;
-    input fabric_fpga_wdata_axi_m2_i1;
-    input fabric_fpga_wdata_axi_m2_i10;
-    input fabric_fpga_wdata_axi_m2_i100;
-    input fabric_fpga_wdata_axi_m2_i101;
-    input fabric_fpga_wdata_axi_m2_i102;
-    input fabric_fpga_wdata_axi_m2_i103;
-    input fabric_fpga_wdata_axi_m2_i104;
-    input fabric_fpga_wdata_axi_m2_i105;
-    input fabric_fpga_wdata_axi_m2_i106;
-    input fabric_fpga_wdata_axi_m2_i107;
-    input fabric_fpga_wdata_axi_m2_i108;
-    input fabric_fpga_wdata_axi_m2_i109;
-    input fabric_fpga_wdata_axi_m2_i11;
-    input fabric_fpga_wdata_axi_m2_i110;
-    input fabric_fpga_wdata_axi_m2_i111;
-    input fabric_fpga_wdata_axi_m2_i112;
-    input fabric_fpga_wdata_axi_m2_i113;
-    input fabric_fpga_wdata_axi_m2_i114;
-    input fabric_fpga_wdata_axi_m2_i115;
-    input fabric_fpga_wdata_axi_m2_i116;
-    input fabric_fpga_wdata_axi_m2_i117;
-    input fabric_fpga_wdata_axi_m2_i118;
-    input fabric_fpga_wdata_axi_m2_i119;
-    input fabric_fpga_wdata_axi_m2_i12;
-    input fabric_fpga_wdata_axi_m2_i120;
-    input fabric_fpga_wdata_axi_m2_i121;
-    input fabric_fpga_wdata_axi_m2_i122;
-    input fabric_fpga_wdata_axi_m2_i123;
-    input fabric_fpga_wdata_axi_m2_i124;
-    input fabric_fpga_wdata_axi_m2_i125;
-    input fabric_fpga_wdata_axi_m2_i126;
-    input fabric_fpga_wdata_axi_m2_i127;
-    input fabric_fpga_wdata_axi_m2_i128;
-    input fabric_fpga_wdata_axi_m2_i13;
-    input fabric_fpga_wdata_axi_m2_i14;
-    input fabric_fpga_wdata_axi_m2_i15;
-    input fabric_fpga_wdata_axi_m2_i16;
-    input fabric_fpga_wdata_axi_m2_i17;
-    input fabric_fpga_wdata_axi_m2_i18;
-    input fabric_fpga_wdata_axi_m2_i19;
-    input fabric_fpga_wdata_axi_m2_i2;
-    input fabric_fpga_wdata_axi_m2_i20;
-    input fabric_fpga_wdata_axi_m2_i21;
-    input fabric_fpga_wdata_axi_m2_i22;
-    input fabric_fpga_wdata_axi_m2_i23;
-    input fabric_fpga_wdata_axi_m2_i24;
-    input fabric_fpga_wdata_axi_m2_i25;
-    input fabric_fpga_wdata_axi_m2_i26;
-    input fabric_fpga_wdata_axi_m2_i27;
-    input fabric_fpga_wdata_axi_m2_i28;
-    input fabric_fpga_wdata_axi_m2_i29;
-    input fabric_fpga_wdata_axi_m2_i3;
-    input fabric_fpga_wdata_axi_m2_i30;
-    input fabric_fpga_wdata_axi_m2_i31;
-    input fabric_fpga_wdata_axi_m2_i32;
-    input fabric_fpga_wdata_axi_m2_i33;
-    input fabric_fpga_wdata_axi_m2_i34;
-    input fabric_fpga_wdata_axi_m2_i35;
-    input fabric_fpga_wdata_axi_m2_i36;
-    input fabric_fpga_wdata_axi_m2_i37;
-    input fabric_fpga_wdata_axi_m2_i38;
-    input fabric_fpga_wdata_axi_m2_i39;
-    input fabric_fpga_wdata_axi_m2_i4;
-    input fabric_fpga_wdata_axi_m2_i40;
-    input fabric_fpga_wdata_axi_m2_i41;
-    input fabric_fpga_wdata_axi_m2_i42;
-    input fabric_fpga_wdata_axi_m2_i43;
-    input fabric_fpga_wdata_axi_m2_i44;
-    input fabric_fpga_wdata_axi_m2_i45;
-    input fabric_fpga_wdata_axi_m2_i46;
-    input fabric_fpga_wdata_axi_m2_i47;
-    input fabric_fpga_wdata_axi_m2_i48;
-    input fabric_fpga_wdata_axi_m2_i49;
-    input fabric_fpga_wdata_axi_m2_i5;
-    input fabric_fpga_wdata_axi_m2_i50;
-    input fabric_fpga_wdata_axi_m2_i51;
-    input fabric_fpga_wdata_axi_m2_i52;
-    input fabric_fpga_wdata_axi_m2_i53;
-    input fabric_fpga_wdata_axi_m2_i54;
-    input fabric_fpga_wdata_axi_m2_i55;
-    input fabric_fpga_wdata_axi_m2_i56;
-    input fabric_fpga_wdata_axi_m2_i57;
-    input fabric_fpga_wdata_axi_m2_i58;
-    input fabric_fpga_wdata_axi_m2_i59;
-    input fabric_fpga_wdata_axi_m2_i6;
-    input fabric_fpga_wdata_axi_m2_i60;
-    input fabric_fpga_wdata_axi_m2_i61;
-    input fabric_fpga_wdata_axi_m2_i62;
-    input fabric_fpga_wdata_axi_m2_i63;
-    input fabric_fpga_wdata_axi_m2_i64;
-    input fabric_fpga_wdata_axi_m2_i65;
-    input fabric_fpga_wdata_axi_m2_i66;
-    input fabric_fpga_wdata_axi_m2_i67;
-    input fabric_fpga_wdata_axi_m2_i68;
-    input fabric_fpga_wdata_axi_m2_i69;
-    input fabric_fpga_wdata_axi_m2_i7;
-    input fabric_fpga_wdata_axi_m2_i70;
-    input fabric_fpga_wdata_axi_m2_i71;
-    input fabric_fpga_wdata_axi_m2_i72;
-    input fabric_fpga_wdata_axi_m2_i73;
-    input fabric_fpga_wdata_axi_m2_i74;
-    input fabric_fpga_wdata_axi_m2_i75;
-    input fabric_fpga_wdata_axi_m2_i76;
-    input fabric_fpga_wdata_axi_m2_i77;
-    input fabric_fpga_wdata_axi_m2_i78;
-    input fabric_fpga_wdata_axi_m2_i79;
-    input fabric_fpga_wdata_axi_m2_i8;
-    input fabric_fpga_wdata_axi_m2_i80;
-    input fabric_fpga_wdata_axi_m2_i81;
-    input fabric_fpga_wdata_axi_m2_i82;
-    input fabric_fpga_wdata_axi_m2_i83;
-    input fabric_fpga_wdata_axi_m2_i84;
-    input fabric_fpga_wdata_axi_m2_i85;
-    input fabric_fpga_wdata_axi_m2_i86;
-    input fabric_fpga_wdata_axi_m2_i87;
-    input fabric_fpga_wdata_axi_m2_i88;
-    input fabric_fpga_wdata_axi_m2_i89;
-    input fabric_fpga_wdata_axi_m2_i9;
-    input fabric_fpga_wdata_axi_m2_i90;
-    input fabric_fpga_wdata_axi_m2_i91;
-    input fabric_fpga_wdata_axi_m2_i92;
-    input fabric_fpga_wdata_axi_m2_i93;
-    input fabric_fpga_wdata_axi_m2_i94;
-    input fabric_fpga_wdata_axi_m2_i95;
-    input fabric_fpga_wdata_axi_m2_i96;
-    input fabric_fpga_wdata_axi_m2_i97;
-    input fabric_fpga_wdata_axi_m2_i98;
-    input fabric_fpga_wdata_axi_m2_i99;
-    output fabric_fpga_wdata_axi_s1_o1;
-    output fabric_fpga_wdata_axi_s1_o10;
-    output fabric_fpga_wdata_axi_s1_o100;
-    output fabric_fpga_wdata_axi_s1_o101;
-    output fabric_fpga_wdata_axi_s1_o102;
-    output fabric_fpga_wdata_axi_s1_o103;
-    output fabric_fpga_wdata_axi_s1_o104;
-    output fabric_fpga_wdata_axi_s1_o105;
-    output fabric_fpga_wdata_axi_s1_o106;
-    output fabric_fpga_wdata_axi_s1_o107;
-    output fabric_fpga_wdata_axi_s1_o108;
-    output fabric_fpga_wdata_axi_s1_o109;
-    output fabric_fpga_wdata_axi_s1_o11;
-    output fabric_fpga_wdata_axi_s1_o110;
-    output fabric_fpga_wdata_axi_s1_o111;
-    output fabric_fpga_wdata_axi_s1_o112;
-    output fabric_fpga_wdata_axi_s1_o113;
-    output fabric_fpga_wdata_axi_s1_o114;
-    output fabric_fpga_wdata_axi_s1_o115;
-    output fabric_fpga_wdata_axi_s1_o116;
-    output fabric_fpga_wdata_axi_s1_o117;
-    output fabric_fpga_wdata_axi_s1_o118;
-    output fabric_fpga_wdata_axi_s1_o119;
-    output fabric_fpga_wdata_axi_s1_o12;
-    output fabric_fpga_wdata_axi_s1_o120;
-    output fabric_fpga_wdata_axi_s1_o121;
-    output fabric_fpga_wdata_axi_s1_o122;
-    output fabric_fpga_wdata_axi_s1_o123;
-    output fabric_fpga_wdata_axi_s1_o124;
-    output fabric_fpga_wdata_axi_s1_o125;
-    output fabric_fpga_wdata_axi_s1_o126;
-    output fabric_fpga_wdata_axi_s1_o127;
-    output fabric_fpga_wdata_axi_s1_o128;
-    output fabric_fpga_wdata_axi_s1_o13;
-    output fabric_fpga_wdata_axi_s1_o14;
-    output fabric_fpga_wdata_axi_s1_o15;
-    output fabric_fpga_wdata_axi_s1_o16;
-    output fabric_fpga_wdata_axi_s1_o17;
-    output fabric_fpga_wdata_axi_s1_o18;
-    output fabric_fpga_wdata_axi_s1_o19;
-    output fabric_fpga_wdata_axi_s1_o2;
-    output fabric_fpga_wdata_axi_s1_o20;
-    output fabric_fpga_wdata_axi_s1_o21;
-    output fabric_fpga_wdata_axi_s1_o22;
-    output fabric_fpga_wdata_axi_s1_o23;
-    output fabric_fpga_wdata_axi_s1_o24;
-    output fabric_fpga_wdata_axi_s1_o25;
-    output fabric_fpga_wdata_axi_s1_o26;
-    output fabric_fpga_wdata_axi_s1_o27;
-    output fabric_fpga_wdata_axi_s1_o28;
-    output fabric_fpga_wdata_axi_s1_o29;
-    output fabric_fpga_wdata_axi_s1_o3;
-    output fabric_fpga_wdata_axi_s1_o30;
-    output fabric_fpga_wdata_axi_s1_o31;
-    output fabric_fpga_wdata_axi_s1_o32;
-    output fabric_fpga_wdata_axi_s1_o33;
-    output fabric_fpga_wdata_axi_s1_o34;
-    output fabric_fpga_wdata_axi_s1_o35;
-    output fabric_fpga_wdata_axi_s1_o36;
-    output fabric_fpga_wdata_axi_s1_o37;
-    output fabric_fpga_wdata_axi_s1_o38;
-    output fabric_fpga_wdata_axi_s1_o39;
-    output fabric_fpga_wdata_axi_s1_o4;
-    output fabric_fpga_wdata_axi_s1_o40;
-    output fabric_fpga_wdata_axi_s1_o41;
-    output fabric_fpga_wdata_axi_s1_o42;
-    output fabric_fpga_wdata_axi_s1_o43;
-    output fabric_fpga_wdata_axi_s1_o44;
-    output fabric_fpga_wdata_axi_s1_o45;
-    output fabric_fpga_wdata_axi_s1_o46;
-    output fabric_fpga_wdata_axi_s1_o47;
-    output fabric_fpga_wdata_axi_s1_o48;
-    output fabric_fpga_wdata_axi_s1_o49;
-    output fabric_fpga_wdata_axi_s1_o5;
-    output fabric_fpga_wdata_axi_s1_o50;
-    output fabric_fpga_wdata_axi_s1_o51;
-    output fabric_fpga_wdata_axi_s1_o52;
-    output fabric_fpga_wdata_axi_s1_o53;
-    output fabric_fpga_wdata_axi_s1_o54;
-    output fabric_fpga_wdata_axi_s1_o55;
-    output fabric_fpga_wdata_axi_s1_o56;
-    output fabric_fpga_wdata_axi_s1_o57;
-    output fabric_fpga_wdata_axi_s1_o58;
-    output fabric_fpga_wdata_axi_s1_o59;
-    output fabric_fpga_wdata_axi_s1_o6;
-    output fabric_fpga_wdata_axi_s1_o60;
-    output fabric_fpga_wdata_axi_s1_o61;
-    output fabric_fpga_wdata_axi_s1_o62;
-    output fabric_fpga_wdata_axi_s1_o63;
-    output fabric_fpga_wdata_axi_s1_o64;
-    output fabric_fpga_wdata_axi_s1_o65;
-    output fabric_fpga_wdata_axi_s1_o66;
-    output fabric_fpga_wdata_axi_s1_o67;
-    output fabric_fpga_wdata_axi_s1_o68;
-    output fabric_fpga_wdata_axi_s1_o69;
-    output fabric_fpga_wdata_axi_s1_o7;
-    output fabric_fpga_wdata_axi_s1_o70;
-    output fabric_fpga_wdata_axi_s1_o71;
-    output fabric_fpga_wdata_axi_s1_o72;
-    output fabric_fpga_wdata_axi_s1_o73;
-    output fabric_fpga_wdata_axi_s1_o74;
-    output fabric_fpga_wdata_axi_s1_o75;
-    output fabric_fpga_wdata_axi_s1_o76;
-    output fabric_fpga_wdata_axi_s1_o77;
-    output fabric_fpga_wdata_axi_s1_o78;
-    output fabric_fpga_wdata_axi_s1_o79;
-    output fabric_fpga_wdata_axi_s1_o8;
-    output fabric_fpga_wdata_axi_s1_o80;
-    output fabric_fpga_wdata_axi_s1_o81;
-    output fabric_fpga_wdata_axi_s1_o82;
-    output fabric_fpga_wdata_axi_s1_o83;
-    output fabric_fpga_wdata_axi_s1_o84;
-    output fabric_fpga_wdata_axi_s1_o85;
-    output fabric_fpga_wdata_axi_s1_o86;
-    output fabric_fpga_wdata_axi_s1_o87;
-    output fabric_fpga_wdata_axi_s1_o88;
-    output fabric_fpga_wdata_axi_s1_o89;
-    output fabric_fpga_wdata_axi_s1_o9;
-    output fabric_fpga_wdata_axi_s1_o90;
-    output fabric_fpga_wdata_axi_s1_o91;
-    output fabric_fpga_wdata_axi_s1_o92;
-    output fabric_fpga_wdata_axi_s1_o93;
-    output fabric_fpga_wdata_axi_s1_o94;
-    output fabric_fpga_wdata_axi_s1_o95;
-    output fabric_fpga_wdata_axi_s1_o96;
-    output fabric_fpga_wdata_axi_s1_o97;
-    output fabric_fpga_wdata_axi_s1_o98;
-    output fabric_fpga_wdata_axi_s1_o99;
-    output fabric_fpga_wdata_axi_s2_o1;
-    output fabric_fpga_wdata_axi_s2_o10;
-    output fabric_fpga_wdata_axi_s2_o100;
-    output fabric_fpga_wdata_axi_s2_o101;
-    output fabric_fpga_wdata_axi_s2_o102;
-    output fabric_fpga_wdata_axi_s2_o103;
-    output fabric_fpga_wdata_axi_s2_o104;
-    output fabric_fpga_wdata_axi_s2_o105;
-    output fabric_fpga_wdata_axi_s2_o106;
-    output fabric_fpga_wdata_axi_s2_o107;
-    output fabric_fpga_wdata_axi_s2_o108;
-    output fabric_fpga_wdata_axi_s2_o109;
-    output fabric_fpga_wdata_axi_s2_o11;
-    output fabric_fpga_wdata_axi_s2_o110;
-    output fabric_fpga_wdata_axi_s2_o111;
-    output fabric_fpga_wdata_axi_s2_o112;
-    output fabric_fpga_wdata_axi_s2_o113;
-    output fabric_fpga_wdata_axi_s2_o114;
-    output fabric_fpga_wdata_axi_s2_o115;
-    output fabric_fpga_wdata_axi_s2_o116;
-    output fabric_fpga_wdata_axi_s2_o117;
-    output fabric_fpga_wdata_axi_s2_o118;
-    output fabric_fpga_wdata_axi_s2_o119;
-    output fabric_fpga_wdata_axi_s2_o12;
-    output fabric_fpga_wdata_axi_s2_o120;
-    output fabric_fpga_wdata_axi_s2_o121;
-    output fabric_fpga_wdata_axi_s2_o122;
-    output fabric_fpga_wdata_axi_s2_o123;
-    output fabric_fpga_wdata_axi_s2_o124;
-    output fabric_fpga_wdata_axi_s2_o125;
-    output fabric_fpga_wdata_axi_s2_o126;
-    output fabric_fpga_wdata_axi_s2_o127;
-    output fabric_fpga_wdata_axi_s2_o128;
-    output fabric_fpga_wdata_axi_s2_o13;
-    output fabric_fpga_wdata_axi_s2_o14;
-    output fabric_fpga_wdata_axi_s2_o15;
-    output fabric_fpga_wdata_axi_s2_o16;
-    output fabric_fpga_wdata_axi_s2_o17;
-    output fabric_fpga_wdata_axi_s2_o18;
-    output fabric_fpga_wdata_axi_s2_o19;
-    output fabric_fpga_wdata_axi_s2_o2;
-    output fabric_fpga_wdata_axi_s2_o20;
-    output fabric_fpga_wdata_axi_s2_o21;
-    output fabric_fpga_wdata_axi_s2_o22;
-    output fabric_fpga_wdata_axi_s2_o23;
-    output fabric_fpga_wdata_axi_s2_o24;
-    output fabric_fpga_wdata_axi_s2_o25;
-    output fabric_fpga_wdata_axi_s2_o26;
-    output fabric_fpga_wdata_axi_s2_o27;
-    output fabric_fpga_wdata_axi_s2_o28;
-    output fabric_fpga_wdata_axi_s2_o29;
-    output fabric_fpga_wdata_axi_s2_o3;
-    output fabric_fpga_wdata_axi_s2_o30;
-    output fabric_fpga_wdata_axi_s2_o31;
-    output fabric_fpga_wdata_axi_s2_o32;
-    output fabric_fpga_wdata_axi_s2_o33;
-    output fabric_fpga_wdata_axi_s2_o34;
-    output fabric_fpga_wdata_axi_s2_o35;
-    output fabric_fpga_wdata_axi_s2_o36;
-    output fabric_fpga_wdata_axi_s2_o37;
-    output fabric_fpga_wdata_axi_s2_o38;
-    output fabric_fpga_wdata_axi_s2_o39;
-    output fabric_fpga_wdata_axi_s2_o4;
-    output fabric_fpga_wdata_axi_s2_o40;
-    output fabric_fpga_wdata_axi_s2_o41;
-    output fabric_fpga_wdata_axi_s2_o42;
-    output fabric_fpga_wdata_axi_s2_o43;
-    output fabric_fpga_wdata_axi_s2_o44;
-    output fabric_fpga_wdata_axi_s2_o45;
-    output fabric_fpga_wdata_axi_s2_o46;
-    output fabric_fpga_wdata_axi_s2_o47;
-    output fabric_fpga_wdata_axi_s2_o48;
-    output fabric_fpga_wdata_axi_s2_o49;
-    output fabric_fpga_wdata_axi_s2_o5;
-    output fabric_fpga_wdata_axi_s2_o50;
-    output fabric_fpga_wdata_axi_s2_o51;
-    output fabric_fpga_wdata_axi_s2_o52;
-    output fabric_fpga_wdata_axi_s2_o53;
-    output fabric_fpga_wdata_axi_s2_o54;
-    output fabric_fpga_wdata_axi_s2_o55;
-    output fabric_fpga_wdata_axi_s2_o56;
-    output fabric_fpga_wdata_axi_s2_o57;
-    output fabric_fpga_wdata_axi_s2_o58;
-    output fabric_fpga_wdata_axi_s2_o59;
-    output fabric_fpga_wdata_axi_s2_o6;
-    output fabric_fpga_wdata_axi_s2_o60;
-    output fabric_fpga_wdata_axi_s2_o61;
-    output fabric_fpga_wdata_axi_s2_o62;
-    output fabric_fpga_wdata_axi_s2_o63;
-    output fabric_fpga_wdata_axi_s2_o64;
-    output fabric_fpga_wdata_axi_s2_o65;
-    output fabric_fpga_wdata_axi_s2_o66;
-    output fabric_fpga_wdata_axi_s2_o67;
-    output fabric_fpga_wdata_axi_s2_o68;
-    output fabric_fpga_wdata_axi_s2_o69;
-    output fabric_fpga_wdata_axi_s2_o7;
-    output fabric_fpga_wdata_axi_s2_o70;
-    output fabric_fpga_wdata_axi_s2_o71;
-    output fabric_fpga_wdata_axi_s2_o72;
-    output fabric_fpga_wdata_axi_s2_o73;
-    output fabric_fpga_wdata_axi_s2_o74;
-    output fabric_fpga_wdata_axi_s2_o75;
-    output fabric_fpga_wdata_axi_s2_o76;
-    output fabric_fpga_wdata_axi_s2_o77;
-    output fabric_fpga_wdata_axi_s2_o78;
-    output fabric_fpga_wdata_axi_s2_o79;
-    output fabric_fpga_wdata_axi_s2_o8;
-    output fabric_fpga_wdata_axi_s2_o80;
-    output fabric_fpga_wdata_axi_s2_o81;
-    output fabric_fpga_wdata_axi_s2_o82;
-    output fabric_fpga_wdata_axi_s2_o83;
-    output fabric_fpga_wdata_axi_s2_o84;
-    output fabric_fpga_wdata_axi_s2_o85;
-    output fabric_fpga_wdata_axi_s2_o86;
-    output fabric_fpga_wdata_axi_s2_o87;
-    output fabric_fpga_wdata_axi_s2_o88;
-    output fabric_fpga_wdata_axi_s2_o89;
-    output fabric_fpga_wdata_axi_s2_o9;
-    output fabric_fpga_wdata_axi_s2_o90;
-    output fabric_fpga_wdata_axi_s2_o91;
-    output fabric_fpga_wdata_axi_s2_o92;
-    output fabric_fpga_wdata_axi_s2_o93;
-    output fabric_fpga_wdata_axi_s2_o94;
-    output fabric_fpga_wdata_axi_s2_o95;
-    output fabric_fpga_wdata_axi_s2_o96;
-    output fabric_fpga_wdata_axi_s2_o97;
-    output fabric_fpga_wdata_axi_s2_o98;
-    output fabric_fpga_wdata_axi_s2_o99;
-    input fabric_fpga_wlast_axi_m1_i;
-    input fabric_fpga_wlast_axi_m2_i;
-    output fabric_fpga_wlast_axi_s1_o;
-    output fabric_fpga_wlast_axi_s2_o;
-    output fabric_fpga_wready_axi_m1_o;
-    output fabric_fpga_wready_axi_m2_o;
-    input fabric_fpga_wready_axi_s1_i;
-    input fabric_fpga_wready_axi_s2_i;
-    input fabric_fpga_wstrb_axi_m1_i1;
-    input fabric_fpga_wstrb_axi_m1_i10;
-    input fabric_fpga_wstrb_axi_m1_i11;
-    input fabric_fpga_wstrb_axi_m1_i12;
-    input fabric_fpga_wstrb_axi_m1_i13;
-    input fabric_fpga_wstrb_axi_m1_i14;
-    input fabric_fpga_wstrb_axi_m1_i15;
-    input fabric_fpga_wstrb_axi_m1_i16;
-    input fabric_fpga_wstrb_axi_m1_i2;
-    input fabric_fpga_wstrb_axi_m1_i3;
-    input fabric_fpga_wstrb_axi_m1_i4;
-    input fabric_fpga_wstrb_axi_m1_i5;
-    input fabric_fpga_wstrb_axi_m1_i6;
-    input fabric_fpga_wstrb_axi_m1_i7;
-    input fabric_fpga_wstrb_axi_m1_i8;
-    input fabric_fpga_wstrb_axi_m1_i9;
-    input fabric_fpga_wstrb_axi_m2_i1;
-    input fabric_fpga_wstrb_axi_m2_i10;
-    input fabric_fpga_wstrb_axi_m2_i11;
-    input fabric_fpga_wstrb_axi_m2_i12;
-    input fabric_fpga_wstrb_axi_m2_i13;
-    input fabric_fpga_wstrb_axi_m2_i14;
-    input fabric_fpga_wstrb_axi_m2_i15;
-    input fabric_fpga_wstrb_axi_m2_i16;
-    input fabric_fpga_wstrb_axi_m2_i2;
-    input fabric_fpga_wstrb_axi_m2_i3;
-    input fabric_fpga_wstrb_axi_m2_i4;
-    input fabric_fpga_wstrb_axi_m2_i5;
-    input fabric_fpga_wstrb_axi_m2_i6;
-    input fabric_fpga_wstrb_axi_m2_i7;
-    input fabric_fpga_wstrb_axi_m2_i8;
-    input fabric_fpga_wstrb_axi_m2_i9;
-    output fabric_fpga_wstrb_axi_s1_o1;
-    output fabric_fpga_wstrb_axi_s1_o10;
-    output fabric_fpga_wstrb_axi_s1_o11;
-    output fabric_fpga_wstrb_axi_s1_o12;
-    output fabric_fpga_wstrb_axi_s1_o13;
-    output fabric_fpga_wstrb_axi_s1_o14;
-    output fabric_fpga_wstrb_axi_s1_o15;
-    output fabric_fpga_wstrb_axi_s1_o16;
-    output fabric_fpga_wstrb_axi_s1_o2;
-    output fabric_fpga_wstrb_axi_s1_o3;
-    output fabric_fpga_wstrb_axi_s1_o4;
-    output fabric_fpga_wstrb_axi_s1_o5;
-    output fabric_fpga_wstrb_axi_s1_o6;
-    output fabric_fpga_wstrb_axi_s1_o7;
-    output fabric_fpga_wstrb_axi_s1_o8;
-    output fabric_fpga_wstrb_axi_s1_o9;
-    output fabric_fpga_wstrb_axi_s2_o1;
-    output fabric_fpga_wstrb_axi_s2_o10;
-    output fabric_fpga_wstrb_axi_s2_o11;
-    output fabric_fpga_wstrb_axi_s2_o12;
-    output fabric_fpga_wstrb_axi_s2_o13;
-    output fabric_fpga_wstrb_axi_s2_o14;
-    output fabric_fpga_wstrb_axi_s2_o15;
-    output fabric_fpga_wstrb_axi_s2_o16;
-    output fabric_fpga_wstrb_axi_s2_o2;
-    output fabric_fpga_wstrb_axi_s2_o3;
-    output fabric_fpga_wstrb_axi_s2_o4;
-    output fabric_fpga_wstrb_axi_s2_o5;
-    output fabric_fpga_wstrb_axi_s2_o6;
-    output fabric_fpga_wstrb_axi_s2_o7;
-    output fabric_fpga_wstrb_axi_s2_o8;
-    output fabric_fpga_wstrb_axi_s2_o9;
-    input fabric_fpga_wvalid_axi_m1_i;
-    input fabric_fpga_wvalid_axi_m2_i;
-    output fabric_fpga_wvalid_axi_s1_o;
-    output fabric_fpga_wvalid_axi_s2_o;
-    output fabric_llpp0_araddr_s_o1;
-    output fabric_llpp0_araddr_s_o10;
-    output fabric_llpp0_araddr_s_o11;
-    output fabric_llpp0_araddr_s_o12;
-    output fabric_llpp0_araddr_s_o13;
-    output fabric_llpp0_araddr_s_o14;
-    output fabric_llpp0_araddr_s_o15;
-    output fabric_llpp0_araddr_s_o16;
-    output fabric_llpp0_araddr_s_o17;
-    output fabric_llpp0_araddr_s_o18;
-    output fabric_llpp0_araddr_s_o19;
-    output fabric_llpp0_araddr_s_o2;
-    output fabric_llpp0_araddr_s_o20;
-    output fabric_llpp0_araddr_s_o21;
-    output fabric_llpp0_araddr_s_o22;
-    output fabric_llpp0_araddr_s_o23;
-    output fabric_llpp0_araddr_s_o24;
-    output fabric_llpp0_araddr_s_o25;
-    output fabric_llpp0_araddr_s_o26;
-    output fabric_llpp0_araddr_s_o27;
-    output fabric_llpp0_araddr_s_o28;
-    output fabric_llpp0_araddr_s_o29;
-    output fabric_llpp0_araddr_s_o3;
-    output fabric_llpp0_araddr_s_o30;
-    output fabric_llpp0_araddr_s_o31;
-    output fabric_llpp0_araddr_s_o32;
-    output fabric_llpp0_araddr_s_o4;
-    output fabric_llpp0_araddr_s_o5;
-    output fabric_llpp0_araddr_s_o6;
-    output fabric_llpp0_araddr_s_o7;
-    output fabric_llpp0_araddr_s_o8;
-    output fabric_llpp0_araddr_s_o9;
-    output fabric_llpp0_arburst_s_o1;
-    output fabric_llpp0_arburst_s_o2;
-    output fabric_llpp0_arcache_s_o1;
-    output fabric_llpp0_arcache_s_o2;
-    output fabric_llpp0_arcache_s_o3;
-    output fabric_llpp0_arcache_s_o4;
-    output fabric_llpp0_arid_s_o1;
-    output fabric_llpp0_arid_s_o10;
-    output fabric_llpp0_arid_s_o11;
-    output fabric_llpp0_arid_s_o12;
-    output fabric_llpp0_arid_s_o2;
-    output fabric_llpp0_arid_s_o3;
-    output fabric_llpp0_arid_s_o4;
-    output fabric_llpp0_arid_s_o5;
-    output fabric_llpp0_arid_s_o6;
-    output fabric_llpp0_arid_s_o7;
-    output fabric_llpp0_arid_s_o8;
-    output fabric_llpp0_arid_s_o9;
-    output fabric_llpp0_arlen_s_o1;
-    output fabric_llpp0_arlen_s_o2;
-    output fabric_llpp0_arlen_s_o3;
-    output fabric_llpp0_arlen_s_o4;
-    output fabric_llpp0_arlen_s_o5;
-    output fabric_llpp0_arlen_s_o6;
-    output fabric_llpp0_arlen_s_o7;
-    output fabric_llpp0_arlen_s_o8;
-    output fabric_llpp0_arlock_s_o;
-    output fabric_llpp0_arprot_s_o1;
-    output fabric_llpp0_arprot_s_o2;
-    output fabric_llpp0_arprot_s_o3;
-    output fabric_llpp0_arqos_s_o1;
-    output fabric_llpp0_arqos_s_o2;
-    output fabric_llpp0_arqos_s_o3;
-    output fabric_llpp0_arqos_s_o4;
-    input fabric_llpp0_arready_s_i;
-    output fabric_llpp0_arsize_s_o1;
-    output fabric_llpp0_arsize_s_o2;
-    output fabric_llpp0_arsize_s_o3;
-    output fabric_llpp0_arvalid_s_o;
-    output fabric_llpp0_awaddr_s_o1;
-    output fabric_llpp0_awaddr_s_o10;
-    output fabric_llpp0_awaddr_s_o11;
-    output fabric_llpp0_awaddr_s_o12;
-    output fabric_llpp0_awaddr_s_o13;
-    output fabric_llpp0_awaddr_s_o14;
-    output fabric_llpp0_awaddr_s_o15;
-    output fabric_llpp0_awaddr_s_o16;
-    output fabric_llpp0_awaddr_s_o17;
-    output fabric_llpp0_awaddr_s_o18;
-    output fabric_llpp0_awaddr_s_o19;
-    output fabric_llpp0_awaddr_s_o2;
-    output fabric_llpp0_awaddr_s_o20;
-    output fabric_llpp0_awaddr_s_o21;
-    output fabric_llpp0_awaddr_s_o22;
-    output fabric_llpp0_awaddr_s_o23;
-    output fabric_llpp0_awaddr_s_o24;
-    output fabric_llpp0_awaddr_s_o25;
-    output fabric_llpp0_awaddr_s_o26;
-    output fabric_llpp0_awaddr_s_o27;
-    output fabric_llpp0_awaddr_s_o28;
-    output fabric_llpp0_awaddr_s_o29;
-    output fabric_llpp0_awaddr_s_o3;
-    output fabric_llpp0_awaddr_s_o30;
-    output fabric_llpp0_awaddr_s_o31;
-    output fabric_llpp0_awaddr_s_o32;
-    output fabric_llpp0_awaddr_s_o4;
-    output fabric_llpp0_awaddr_s_o5;
-    output fabric_llpp0_awaddr_s_o6;
-    output fabric_llpp0_awaddr_s_o7;
-    output fabric_llpp0_awaddr_s_o8;
-    output fabric_llpp0_awaddr_s_o9;
-    output fabric_llpp0_awburst_s_o1;
-    output fabric_llpp0_awburst_s_o2;
-    output fabric_llpp0_awcache_s_o1;
-    output fabric_llpp0_awcache_s_o2;
-    output fabric_llpp0_awcache_s_o3;
-    output fabric_llpp0_awcache_s_o4;
-    output fabric_llpp0_awid_s_o1;
-    output fabric_llpp0_awid_s_o10;
-    output fabric_llpp0_awid_s_o11;
-    output fabric_llpp0_awid_s_o12;
-    output fabric_llpp0_awid_s_o2;
-    output fabric_llpp0_awid_s_o3;
-    output fabric_llpp0_awid_s_o4;
-    output fabric_llpp0_awid_s_o5;
-    output fabric_llpp0_awid_s_o6;
-    output fabric_llpp0_awid_s_o7;
-    output fabric_llpp0_awid_s_o8;
-    output fabric_llpp0_awid_s_o9;
-    output fabric_llpp0_awlen_s_o1;
-    output fabric_llpp0_awlen_s_o2;
-    output fabric_llpp0_awlen_s_o3;
-    output fabric_llpp0_awlen_s_o4;
-    output fabric_llpp0_awlen_s_o5;
-    output fabric_llpp0_awlen_s_o6;
-    output fabric_llpp0_awlen_s_o7;
-    output fabric_llpp0_awlen_s_o8;
-    output fabric_llpp0_awlock_s_o;
-    output fabric_llpp0_awprot_s_o1;
-    output fabric_llpp0_awprot_s_o2;
-    output fabric_llpp0_awprot_s_o3;
-    output fabric_llpp0_awqos_s_o1;
-    output fabric_llpp0_awqos_s_o2;
-    output fabric_llpp0_awqos_s_o3;
-    output fabric_llpp0_awqos_s_o4;
-    input fabric_llpp0_awready_s_i;
-    output fabric_llpp0_awsize_s_o1;
-    output fabric_llpp0_awsize_s_o2;
-    output fabric_llpp0_awsize_s_o3;
-    output fabric_llpp0_awvalid_s_o;
-    input fabric_llpp0_bid_s_i1;
-    input fabric_llpp0_bid_s_i10;
-    input fabric_llpp0_bid_s_i11;
-    input fabric_llpp0_bid_s_i12;
-    input fabric_llpp0_bid_s_i2;
-    input fabric_llpp0_bid_s_i3;
-    input fabric_llpp0_bid_s_i4;
-    input fabric_llpp0_bid_s_i5;
-    input fabric_llpp0_bid_s_i6;
-    input fabric_llpp0_bid_s_i7;
-    input fabric_llpp0_bid_s_i8;
-    input fabric_llpp0_bid_s_i9;
-    output fabric_llpp0_bready_s_o;
-    input fabric_llpp0_bresp_s_i1;
-    input fabric_llpp0_bresp_s_i2;
-    input fabric_llpp0_bvalid_s_i;
-    input fabric_llpp0_rdata_s_i1;
-    input fabric_llpp0_rdata_s_i10;
-    input fabric_llpp0_rdata_s_i11;
-    input fabric_llpp0_rdata_s_i12;
-    input fabric_llpp0_rdata_s_i13;
-    input fabric_llpp0_rdata_s_i14;
-    input fabric_llpp0_rdata_s_i15;
-    input fabric_llpp0_rdata_s_i16;
-    input fabric_llpp0_rdata_s_i17;
-    input fabric_llpp0_rdata_s_i18;
-    input fabric_llpp0_rdata_s_i19;
-    input fabric_llpp0_rdata_s_i2;
-    input fabric_llpp0_rdata_s_i20;
-    input fabric_llpp0_rdata_s_i21;
-    input fabric_llpp0_rdata_s_i22;
-    input fabric_llpp0_rdata_s_i23;
-    input fabric_llpp0_rdata_s_i24;
-    input fabric_llpp0_rdata_s_i25;
-    input fabric_llpp0_rdata_s_i26;
-    input fabric_llpp0_rdata_s_i27;
-    input fabric_llpp0_rdata_s_i28;
-    input fabric_llpp0_rdata_s_i29;
-    input fabric_llpp0_rdata_s_i3;
-    input fabric_llpp0_rdata_s_i30;
-    input fabric_llpp0_rdata_s_i31;
-    input fabric_llpp0_rdata_s_i32;
-    input fabric_llpp0_rdata_s_i4;
-    input fabric_llpp0_rdata_s_i5;
-    input fabric_llpp0_rdata_s_i6;
-    input fabric_llpp0_rdata_s_i7;
-    input fabric_llpp0_rdata_s_i8;
-    input fabric_llpp0_rdata_s_i9;
-    input fabric_llpp0_rid_s_i1;
-    input fabric_llpp0_rid_s_i10;
-    input fabric_llpp0_rid_s_i11;
-    input fabric_llpp0_rid_s_i12;
-    input fabric_llpp0_rid_s_i2;
-    input fabric_llpp0_rid_s_i3;
-    input fabric_llpp0_rid_s_i4;
-    input fabric_llpp0_rid_s_i5;
-    input fabric_llpp0_rid_s_i6;
-    input fabric_llpp0_rid_s_i7;
-    input fabric_llpp0_rid_s_i8;
-    input fabric_llpp0_rid_s_i9;
-    input fabric_llpp0_rlast_s_i;
-    output fabric_llpp0_rready_s_o;
-    input fabric_llpp0_rresp_s_i1;
-    input fabric_llpp0_rresp_s_i2;
-    input fabric_llpp0_rvalid_s_i;
-    output fabric_llpp0_wdata_s_o1;
-    output fabric_llpp0_wdata_s_o10;
-    output fabric_llpp0_wdata_s_o11;
-    output fabric_llpp0_wdata_s_o12;
-    output fabric_llpp0_wdata_s_o13;
-    output fabric_llpp0_wdata_s_o14;
-    output fabric_llpp0_wdata_s_o15;
-    output fabric_llpp0_wdata_s_o16;
-    output fabric_llpp0_wdata_s_o17;
-    output fabric_llpp0_wdata_s_o18;
-    output fabric_llpp0_wdata_s_o19;
-    output fabric_llpp0_wdata_s_o2;
-    output fabric_llpp0_wdata_s_o20;
-    output fabric_llpp0_wdata_s_o21;
-    output fabric_llpp0_wdata_s_o22;
-    output fabric_llpp0_wdata_s_o23;
-    output fabric_llpp0_wdata_s_o24;
-    output fabric_llpp0_wdata_s_o25;
-    output fabric_llpp0_wdata_s_o26;
-    output fabric_llpp0_wdata_s_o27;
-    output fabric_llpp0_wdata_s_o28;
-    output fabric_llpp0_wdata_s_o29;
-    output fabric_llpp0_wdata_s_o3;
-    output fabric_llpp0_wdata_s_o30;
-    output fabric_llpp0_wdata_s_o31;
-    output fabric_llpp0_wdata_s_o32;
-    output fabric_llpp0_wdata_s_o4;
-    output fabric_llpp0_wdata_s_o5;
-    output fabric_llpp0_wdata_s_o6;
-    output fabric_llpp0_wdata_s_o7;
-    output fabric_llpp0_wdata_s_o8;
-    output fabric_llpp0_wdata_s_o9;
-    output fabric_llpp0_wlast_s_o;
-    input fabric_llpp0_wready_s_i;
-    output fabric_llpp0_wstrb_s_o1;
-    output fabric_llpp0_wstrb_s_o2;
-    output fabric_llpp0_wstrb_s_o3;
-    output fabric_llpp0_wstrb_s_o4;
-    output fabric_llpp0_wvalid_s_o;
-    output fabric_llpp1_araddr_s_o1;
-    output fabric_llpp1_araddr_s_o10;
-    output fabric_llpp1_araddr_s_o11;
-    output fabric_llpp1_araddr_s_o12;
-    output fabric_llpp1_araddr_s_o13;
-    output fabric_llpp1_araddr_s_o14;
-    output fabric_llpp1_araddr_s_o15;
-    output fabric_llpp1_araddr_s_o16;
-    output fabric_llpp1_araddr_s_o17;
-    output fabric_llpp1_araddr_s_o18;
-    output fabric_llpp1_araddr_s_o19;
-    output fabric_llpp1_araddr_s_o2;
-    output fabric_llpp1_araddr_s_o20;
-    output fabric_llpp1_araddr_s_o21;
-    output fabric_llpp1_araddr_s_o22;
-    output fabric_llpp1_araddr_s_o23;
-    output fabric_llpp1_araddr_s_o24;
-    output fabric_llpp1_araddr_s_o25;
-    output fabric_llpp1_araddr_s_o26;
-    output fabric_llpp1_araddr_s_o27;
-    output fabric_llpp1_araddr_s_o28;
-    output fabric_llpp1_araddr_s_o29;
-    output fabric_llpp1_araddr_s_o3;
-    output fabric_llpp1_araddr_s_o30;
-    output fabric_llpp1_araddr_s_o31;
-    output fabric_llpp1_araddr_s_o32;
-    output fabric_llpp1_araddr_s_o4;
-    output fabric_llpp1_araddr_s_o5;
-    output fabric_llpp1_araddr_s_o6;
-    output fabric_llpp1_araddr_s_o7;
-    output fabric_llpp1_araddr_s_o8;
-    output fabric_llpp1_araddr_s_o9;
-    output fabric_llpp1_arburst_s_o1;
-    output fabric_llpp1_arburst_s_o2;
-    output fabric_llpp1_arcache_s_o1;
-    output fabric_llpp1_arcache_s_o2;
-    output fabric_llpp1_arcache_s_o3;
-    output fabric_llpp1_arcache_s_o4;
-    output fabric_llpp1_arid_s_o1;
-    output fabric_llpp1_arid_s_o10;
-    output fabric_llpp1_arid_s_o11;
-    output fabric_llpp1_arid_s_o12;
-    output fabric_llpp1_arid_s_o2;
-    output fabric_llpp1_arid_s_o3;
-    output fabric_llpp1_arid_s_o4;
-    output fabric_llpp1_arid_s_o5;
-    output fabric_llpp1_arid_s_o6;
-    output fabric_llpp1_arid_s_o7;
-    output fabric_llpp1_arid_s_o8;
-    output fabric_llpp1_arid_s_o9;
-    output fabric_llpp1_arlen_s_o1;
-    output fabric_llpp1_arlen_s_o2;
-    output fabric_llpp1_arlen_s_o3;
-    output fabric_llpp1_arlen_s_o4;
-    output fabric_llpp1_arlen_s_o5;
-    output fabric_llpp1_arlen_s_o6;
-    output fabric_llpp1_arlen_s_o7;
-    output fabric_llpp1_arlen_s_o8;
-    output fabric_llpp1_arlock_s_o;
-    output fabric_llpp1_arprot_s_o1;
-    output fabric_llpp1_arprot_s_o2;
-    output fabric_llpp1_arprot_s_o3;
-    output fabric_llpp1_arqos_s1_o1;
-    output fabric_llpp1_arqos_s1_o2;
-    output fabric_llpp1_arqos_s1_o3;
-    output fabric_llpp1_arqos_s1_o4;
-    input fabric_llpp1_arready_s_i;
-    output fabric_llpp1_arsize_s_o1;
-    output fabric_llpp1_arsize_s_o2;
-    output fabric_llpp1_arsize_s_o3;
-    output fabric_llpp1_arvalid_s_o;
-    output fabric_llpp1_awaddr_s_o1;
-    output fabric_llpp1_awaddr_s_o10;
-    output fabric_llpp1_awaddr_s_o11;
-    output fabric_llpp1_awaddr_s_o12;
-    output fabric_llpp1_awaddr_s_o13;
-    output fabric_llpp1_awaddr_s_o14;
-    output fabric_llpp1_awaddr_s_o15;
-    output fabric_llpp1_awaddr_s_o16;
-    output fabric_llpp1_awaddr_s_o17;
-    output fabric_llpp1_awaddr_s_o18;
-    output fabric_llpp1_awaddr_s_o19;
-    output fabric_llpp1_awaddr_s_o2;
-    output fabric_llpp1_awaddr_s_o20;
-    output fabric_llpp1_awaddr_s_o21;
-    output fabric_llpp1_awaddr_s_o22;
-    output fabric_llpp1_awaddr_s_o23;
-    output fabric_llpp1_awaddr_s_o24;
-    output fabric_llpp1_awaddr_s_o25;
-    output fabric_llpp1_awaddr_s_o26;
-    output fabric_llpp1_awaddr_s_o27;
-    output fabric_llpp1_awaddr_s_o28;
-    output fabric_llpp1_awaddr_s_o29;
-    output fabric_llpp1_awaddr_s_o3;
-    output fabric_llpp1_awaddr_s_o30;
-    output fabric_llpp1_awaddr_s_o31;
-    output fabric_llpp1_awaddr_s_o32;
-    output fabric_llpp1_awaddr_s_o4;
-    output fabric_llpp1_awaddr_s_o5;
-    output fabric_llpp1_awaddr_s_o6;
-    output fabric_llpp1_awaddr_s_o7;
-    output fabric_llpp1_awaddr_s_o8;
-    output fabric_llpp1_awaddr_s_o9;
-    output fabric_llpp1_awburst_s_o1;
-    output fabric_llpp1_awburst_s_o2;
-    output fabric_llpp1_awcache_s_o1;
-    output fabric_llpp1_awcache_s_o2;
-    output fabric_llpp1_awcache_s_o3;
-    output fabric_llpp1_awcache_s_o4;
-    output fabric_llpp1_awid_s_o1;
-    output fabric_llpp1_awid_s_o10;
-    output fabric_llpp1_awid_s_o11;
-    output fabric_llpp1_awid_s_o12;
-    output fabric_llpp1_awid_s_o2;
-    output fabric_llpp1_awid_s_o3;
-    output fabric_llpp1_awid_s_o4;
-    output fabric_llpp1_awid_s_o5;
-    output fabric_llpp1_awid_s_o6;
-    output fabric_llpp1_awid_s_o7;
-    output fabric_llpp1_awid_s_o8;
-    output fabric_llpp1_awid_s_o9;
-    output fabric_llpp1_awlen_s_o1;
-    output fabric_llpp1_awlen_s_o2;
-    output fabric_llpp1_awlen_s_o3;
-    output fabric_llpp1_awlen_s_o4;
-    output fabric_llpp1_awlen_s_o5;
-    output fabric_llpp1_awlen_s_o6;
-    output fabric_llpp1_awlen_s_o7;
-    output fabric_llpp1_awlen_s_o8;
-    output fabric_llpp1_awlock_s_o;
-    output fabric_llpp1_awprot_s_o1;
-    output fabric_llpp1_awprot_s_o2;
-    output fabric_llpp1_awprot_s_o3;
-    output fabric_llpp1_awqos_s_o1;
-    output fabric_llpp1_awqos_s_o2;
-    output fabric_llpp1_awqos_s_o3;
-    output fabric_llpp1_awqos_s_o4;
-    input fabric_llpp1_awready_s_i;
-    output fabric_llpp1_awsize_s_o1;
-    output fabric_llpp1_awsize_s_o2;
-    output fabric_llpp1_awsize_s_o3;
-    output fabric_llpp1_awvalid_s_o;
-    input fabric_llpp1_bid_s_i1;
-    input fabric_llpp1_bid_s_i10;
-    input fabric_llpp1_bid_s_i11;
-    input fabric_llpp1_bid_s_i12;
-    input fabric_llpp1_bid_s_i2;
-    input fabric_llpp1_bid_s_i3;
-    input fabric_llpp1_bid_s_i4;
-    input fabric_llpp1_bid_s_i5;
-    input fabric_llpp1_bid_s_i6;
-    input fabric_llpp1_bid_s_i7;
-    input fabric_llpp1_bid_s_i8;
-    input fabric_llpp1_bid_s_i9;
-    output fabric_llpp1_bready_s_o;
-    input fabric_llpp1_bresp_s_i1;
-    input fabric_llpp1_bresp_s_i2;
-    input fabric_llpp1_bvalid_s_i;
-    input fabric_llpp1_rdata_s_i1;
-    input fabric_llpp1_rdata_s_i10;
-    input fabric_llpp1_rdata_s_i11;
-    input fabric_llpp1_rdata_s_i12;
-    input fabric_llpp1_rdata_s_i13;
-    input fabric_llpp1_rdata_s_i14;
-    input fabric_llpp1_rdata_s_i15;
-    input fabric_llpp1_rdata_s_i16;
-    input fabric_llpp1_rdata_s_i17;
-    input fabric_llpp1_rdata_s_i18;
-    input fabric_llpp1_rdata_s_i19;
-    input fabric_llpp1_rdata_s_i2;
-    input fabric_llpp1_rdata_s_i20;
-    input fabric_llpp1_rdata_s_i21;
-    input fabric_llpp1_rdata_s_i22;
-    input fabric_llpp1_rdata_s_i23;
-    input fabric_llpp1_rdata_s_i24;
-    input fabric_llpp1_rdata_s_i25;
-    input fabric_llpp1_rdata_s_i26;
-    input fabric_llpp1_rdata_s_i27;
-    input fabric_llpp1_rdata_s_i28;
-    input fabric_llpp1_rdata_s_i29;
-    input fabric_llpp1_rdata_s_i3;
-    input fabric_llpp1_rdata_s_i30;
-    input fabric_llpp1_rdata_s_i31;
-    input fabric_llpp1_rdata_s_i32;
-    input fabric_llpp1_rdata_s_i4;
-    input fabric_llpp1_rdata_s_i5;
-    input fabric_llpp1_rdata_s_i6;
-    input fabric_llpp1_rdata_s_i7;
-    input fabric_llpp1_rdata_s_i8;
-    input fabric_llpp1_rdata_s_i9;
-    input fabric_llpp1_rid_s_i1;
-    input fabric_llpp1_rid_s_i10;
-    input fabric_llpp1_rid_s_i11;
-    input fabric_llpp1_rid_s_i12;
-    input fabric_llpp1_rid_s_i2;
-    input fabric_llpp1_rid_s_i3;
-    input fabric_llpp1_rid_s_i4;
-    input fabric_llpp1_rid_s_i5;
-    input fabric_llpp1_rid_s_i6;
-    input fabric_llpp1_rid_s_i7;
-    input fabric_llpp1_rid_s_i8;
-    input fabric_llpp1_rid_s_i9;
-    input fabric_llpp1_rlast_s_i;
-    output fabric_llpp1_rready_s_o;
-    input fabric_llpp1_rresp_s_i1;
-    input fabric_llpp1_rresp_s_i2;
-    input fabric_llpp1_rvalid_s_i;
-    output fabric_llpp1_wdata_s_o1;
-    output fabric_llpp1_wdata_s_o10;
-    output fabric_llpp1_wdata_s_o11;
-    output fabric_llpp1_wdata_s_o12;
-    output fabric_llpp1_wdata_s_o13;
-    output fabric_llpp1_wdata_s_o14;
-    output fabric_llpp1_wdata_s_o15;
-    output fabric_llpp1_wdata_s_o16;
-    output fabric_llpp1_wdata_s_o17;
-    output fabric_llpp1_wdata_s_o18;
-    output fabric_llpp1_wdata_s_o19;
-    output fabric_llpp1_wdata_s_o2;
-    output fabric_llpp1_wdata_s_o20;
-    output fabric_llpp1_wdata_s_o21;
-    output fabric_llpp1_wdata_s_o22;
-    output fabric_llpp1_wdata_s_o23;
-    output fabric_llpp1_wdata_s_o24;
-    output fabric_llpp1_wdata_s_o25;
-    output fabric_llpp1_wdata_s_o26;
-    output fabric_llpp1_wdata_s_o27;
-    output fabric_llpp1_wdata_s_o28;
-    output fabric_llpp1_wdata_s_o29;
-    output fabric_llpp1_wdata_s_o3;
-    output fabric_llpp1_wdata_s_o30;
-    output fabric_llpp1_wdata_s_o31;
-    output fabric_llpp1_wdata_s_o32;
-    output fabric_llpp1_wdata_s_o4;
-    output fabric_llpp1_wdata_s_o5;
-    output fabric_llpp1_wdata_s_o6;
-    output fabric_llpp1_wdata_s_o7;
-    output fabric_llpp1_wdata_s_o8;
-    output fabric_llpp1_wdata_s_o9;
-    output fabric_llpp1_wlast_s_o;
-    input fabric_llpp1_wready_s_i;
-    output fabric_llpp1_wstrb_s_o1;
-    output fabric_llpp1_wstrb_s_o2;
-    output fabric_llpp1_wstrb_s_o3;
-    output fabric_llpp1_wstrb_s_o4;
-    output fabric_llpp1_wvalid_s_o;
-    output fabric_llpp2_araddr_s_o1;
-    output fabric_llpp2_araddr_s_o10;
-    output fabric_llpp2_araddr_s_o11;
-    output fabric_llpp2_araddr_s_o12;
-    output fabric_llpp2_araddr_s_o13;
-    output fabric_llpp2_araddr_s_o14;
-    output fabric_llpp2_araddr_s_o15;
-    output fabric_llpp2_araddr_s_o16;
-    output fabric_llpp2_araddr_s_o17;
-    output fabric_llpp2_araddr_s_o18;
-    output fabric_llpp2_araddr_s_o19;
-    output fabric_llpp2_araddr_s_o2;
-    output fabric_llpp2_araddr_s_o20;
-    output fabric_llpp2_araddr_s_o21;
-    output fabric_llpp2_araddr_s_o22;
-    output fabric_llpp2_araddr_s_o23;
-    output fabric_llpp2_araddr_s_o24;
-    output fabric_llpp2_araddr_s_o25;
-    output fabric_llpp2_araddr_s_o26;
-    output fabric_llpp2_araddr_s_o27;
-    output fabric_llpp2_araddr_s_o28;
-    output fabric_llpp2_araddr_s_o29;
-    output fabric_llpp2_araddr_s_o3;
-    output fabric_llpp2_araddr_s_o30;
-    output fabric_llpp2_araddr_s_o31;
-    output fabric_llpp2_araddr_s_o32;
-    output fabric_llpp2_araddr_s_o4;
-    output fabric_llpp2_araddr_s_o5;
-    output fabric_llpp2_araddr_s_o6;
-    output fabric_llpp2_araddr_s_o7;
-    output fabric_llpp2_araddr_s_o8;
-    output fabric_llpp2_araddr_s_o9;
-    output fabric_llpp2_arburst_s_o1;
-    output fabric_llpp2_arburst_s_o2;
-    output fabric_llpp2_arcache_s_o1;
-    output fabric_llpp2_arcache_s_o2;
-    output fabric_llpp2_arcache_s_o3;
-    output fabric_llpp2_arcache_s_o4;
-    output fabric_llpp2_arid_s_o1;
-    output fabric_llpp2_arid_s_o10;
-    output fabric_llpp2_arid_s_o11;
-    output fabric_llpp2_arid_s_o12;
-    output fabric_llpp2_arid_s_o2;
-    output fabric_llpp2_arid_s_o3;
-    output fabric_llpp2_arid_s_o4;
-    output fabric_llpp2_arid_s_o5;
-    output fabric_llpp2_arid_s_o6;
-    output fabric_llpp2_arid_s_o7;
-    output fabric_llpp2_arid_s_o8;
-    output fabric_llpp2_arid_s_o9;
-    output fabric_llpp2_arlen_s_o1;
-    output fabric_llpp2_arlen_s_o2;
-    output fabric_llpp2_arlen_s_o3;
-    output fabric_llpp2_arlen_s_o4;
-    output fabric_llpp2_arlen_s_o5;
-    output fabric_llpp2_arlen_s_o6;
-    output fabric_llpp2_arlen_s_o7;
-    output fabric_llpp2_arlen_s_o8;
-    output fabric_llpp2_arlock_s_o;
-    output fabric_llpp2_arprot_s_o1;
-    output fabric_llpp2_arprot_s_o2;
-    output fabric_llpp2_arprot_s_o3;
-    output fabric_llpp2_arqos_s_o1;
-    output fabric_llpp2_arqos_s_o2;
-    output fabric_llpp2_arqos_s_o3;
-    output fabric_llpp2_arqos_s_o4;
-    input fabric_llpp2_arready_s_i;
-    output fabric_llpp2_arsize_s_o1;
-    output fabric_llpp2_arsize_s_o2;
-    output fabric_llpp2_arsize_s_o3;
-    output fabric_llpp2_arvalid_s_o;
-    output fabric_llpp2_awaddr_s_o1;
-    output fabric_llpp2_awaddr_s_o10;
-    output fabric_llpp2_awaddr_s_o11;
-    output fabric_llpp2_awaddr_s_o12;
-    output fabric_llpp2_awaddr_s_o13;
-    output fabric_llpp2_awaddr_s_o14;
-    output fabric_llpp2_awaddr_s_o15;
-    output fabric_llpp2_awaddr_s_o16;
-    output fabric_llpp2_awaddr_s_o17;
-    output fabric_llpp2_awaddr_s_o18;
-    output fabric_llpp2_awaddr_s_o19;
-    output fabric_llpp2_awaddr_s_o2;
-    output fabric_llpp2_awaddr_s_o20;
-    output fabric_llpp2_awaddr_s_o21;
-    output fabric_llpp2_awaddr_s_o22;
-    output fabric_llpp2_awaddr_s_o23;
-    output fabric_llpp2_awaddr_s_o24;
-    output fabric_llpp2_awaddr_s_o25;
-    output fabric_llpp2_awaddr_s_o26;
-    output fabric_llpp2_awaddr_s_o27;
-    output fabric_llpp2_awaddr_s_o28;
-    output fabric_llpp2_awaddr_s_o29;
-    output fabric_llpp2_awaddr_s_o3;
-    output fabric_llpp2_awaddr_s_o30;
-    output fabric_llpp2_awaddr_s_o31;
-    output fabric_llpp2_awaddr_s_o32;
-    output fabric_llpp2_awaddr_s_o4;
-    output fabric_llpp2_awaddr_s_o5;
-    output fabric_llpp2_awaddr_s_o6;
-    output fabric_llpp2_awaddr_s_o7;
-    output fabric_llpp2_awaddr_s_o8;
-    output fabric_llpp2_awaddr_s_o9;
-    output fabric_llpp2_awburst_s_o1;
-    output fabric_llpp2_awburst_s_o2;
-    output fabric_llpp2_awcache_s_o1;
-    output fabric_llpp2_awcache_s_o2;
-    output fabric_llpp2_awcache_s_o3;
-    output fabric_llpp2_awcache_s_o4;
-    output fabric_llpp2_awid_s_o1;
-    output fabric_llpp2_awid_s_o10;
-    output fabric_llpp2_awid_s_o11;
-    output fabric_llpp2_awid_s_o12;
-    output fabric_llpp2_awid_s_o2;
-    output fabric_llpp2_awid_s_o3;
-    output fabric_llpp2_awid_s_o4;
-    output fabric_llpp2_awid_s_o5;
-    output fabric_llpp2_awid_s_o6;
-    output fabric_llpp2_awid_s_o7;
-    output fabric_llpp2_awid_s_o8;
-    output fabric_llpp2_awid_s_o9;
-    output fabric_llpp2_awlen_s_o1;
-    output fabric_llpp2_awlen_s_o2;
-    output fabric_llpp2_awlen_s_o3;
-    output fabric_llpp2_awlen_s_o4;
-    output fabric_llpp2_awlen_s_o5;
-    output fabric_llpp2_awlen_s_o6;
-    output fabric_llpp2_awlen_s_o7;
-    output fabric_llpp2_awlen_s_o8;
-    output fabric_llpp2_awlock_s_o;
-    output fabric_llpp2_awprot_s_o1;
-    output fabric_llpp2_awprot_s_o2;
-    output fabric_llpp2_awprot_s_o3;
-    output fabric_llpp2_awqos_s_o1;
-    output fabric_llpp2_awqos_s_o2;
-    output fabric_llpp2_awqos_s_o3;
-    output fabric_llpp2_awqos_s_o4;
-    input fabric_llpp2_awready_s_i;
-    output fabric_llpp2_awsize_s_o1;
-    output fabric_llpp2_awsize_s_o2;
-    output fabric_llpp2_awsize_s_o3;
-    output fabric_llpp2_awvalid_s_o;
-    input fabric_llpp2_bid_s_i1;
-    input fabric_llpp2_bid_s_i10;
-    input fabric_llpp2_bid_s_i11;
-    input fabric_llpp2_bid_s_i12;
-    input fabric_llpp2_bid_s_i2;
-    input fabric_llpp2_bid_s_i3;
-    input fabric_llpp2_bid_s_i4;
-    input fabric_llpp2_bid_s_i5;
-    input fabric_llpp2_bid_s_i6;
-    input fabric_llpp2_bid_s_i7;
-    input fabric_llpp2_bid_s_i8;
-    input fabric_llpp2_bid_s_i9;
-    output fabric_llpp2_bready_s_o;
-    input fabric_llpp2_bresp_s_i1;
-    input fabric_llpp2_bresp_s_i2;
-    input fabric_llpp2_bvalid_s_i;
-    input fabric_llpp2_rdata_s_i1;
-    input fabric_llpp2_rdata_s_i10;
-    input fabric_llpp2_rdata_s_i11;
-    input fabric_llpp2_rdata_s_i12;
-    input fabric_llpp2_rdata_s_i13;
-    input fabric_llpp2_rdata_s_i14;
-    input fabric_llpp2_rdata_s_i15;
-    input fabric_llpp2_rdata_s_i16;
-    input fabric_llpp2_rdata_s_i17;
-    input fabric_llpp2_rdata_s_i18;
-    input fabric_llpp2_rdata_s_i19;
-    input fabric_llpp2_rdata_s_i2;
-    input fabric_llpp2_rdata_s_i20;
-    input fabric_llpp2_rdata_s_i21;
-    input fabric_llpp2_rdata_s_i22;
-    input fabric_llpp2_rdata_s_i23;
-    input fabric_llpp2_rdata_s_i24;
-    input fabric_llpp2_rdata_s_i25;
-    input fabric_llpp2_rdata_s_i26;
-    input fabric_llpp2_rdata_s_i27;
-    input fabric_llpp2_rdata_s_i28;
-    input fabric_llpp2_rdata_s_i29;
-    input fabric_llpp2_rdata_s_i3;
-    input fabric_llpp2_rdata_s_i30;
-    input fabric_llpp2_rdata_s_i31;
-    input fabric_llpp2_rdata_s_i32;
-    input fabric_llpp2_rdata_s_i4;
-    input fabric_llpp2_rdata_s_i5;
-    input fabric_llpp2_rdata_s_i6;
-    input fabric_llpp2_rdata_s_i7;
-    input fabric_llpp2_rdata_s_i8;
-    input fabric_llpp2_rdata_s_i9;
-    input fabric_llpp2_rid_s_i1;
-    input fabric_llpp2_rid_s_i10;
-    input fabric_llpp2_rid_s_i11;
-    input fabric_llpp2_rid_s_i12;
-    input fabric_llpp2_rid_s_i2;
-    input fabric_llpp2_rid_s_i3;
-    input fabric_llpp2_rid_s_i4;
-    input fabric_llpp2_rid_s_i5;
-    input fabric_llpp2_rid_s_i6;
-    input fabric_llpp2_rid_s_i7;
-    input fabric_llpp2_rid_s_i8;
-    input fabric_llpp2_rid_s_i9;
-    input fabric_llpp2_rlast_s_i;
-    output fabric_llpp2_rready_s_o;
-    input fabric_llpp2_rresp_s_i1;
-    input fabric_llpp2_rresp_s_i2;
-    input fabric_llpp2_rvalid_s_i;
-    output fabric_llpp2_wdata_s_o1;
-    output fabric_llpp2_wdata_s_o10;
-    output fabric_llpp2_wdata_s_o11;
-    output fabric_llpp2_wdata_s_o12;
-    output fabric_llpp2_wdata_s_o13;
-    output fabric_llpp2_wdata_s_o14;
-    output fabric_llpp2_wdata_s_o15;
-    output fabric_llpp2_wdata_s_o16;
-    output fabric_llpp2_wdata_s_o17;
-    output fabric_llpp2_wdata_s_o18;
-    output fabric_llpp2_wdata_s_o19;
-    output fabric_llpp2_wdata_s_o2;
-    output fabric_llpp2_wdata_s_o20;
-    output fabric_llpp2_wdata_s_o21;
-    output fabric_llpp2_wdata_s_o22;
-    output fabric_llpp2_wdata_s_o23;
-    output fabric_llpp2_wdata_s_o24;
-    output fabric_llpp2_wdata_s_o25;
-    output fabric_llpp2_wdata_s_o26;
-    output fabric_llpp2_wdata_s_o27;
-    output fabric_llpp2_wdata_s_o28;
-    output fabric_llpp2_wdata_s_o29;
-    output fabric_llpp2_wdata_s_o3;
-    output fabric_llpp2_wdata_s_o30;
-    output fabric_llpp2_wdata_s_o31;
-    output fabric_llpp2_wdata_s_o32;
-    output fabric_llpp2_wdata_s_o4;
-    output fabric_llpp2_wdata_s_o5;
-    output fabric_llpp2_wdata_s_o6;
-    output fabric_llpp2_wdata_s_o7;
-    output fabric_llpp2_wdata_s_o8;
-    output fabric_llpp2_wdata_s_o9;
-    output fabric_llpp2_wlast_s_o;
-    input fabric_llpp2_wready_s_i;
-    output fabric_llpp2_wstrb_s_o1;
-    output fabric_llpp2_wstrb_s_o2;
-    output fabric_llpp2_wstrb_s_o3;
-    output fabric_llpp2_wstrb_s_o4;
-    output fabric_llpp2_wvalid_s_o;
-    output fabric_llpp3_araddr_s_o1;
-    output fabric_llpp3_araddr_s_o10;
-    output fabric_llpp3_araddr_s_o11;
-    output fabric_llpp3_araddr_s_o12;
-    output fabric_llpp3_araddr_s_o13;
-    output fabric_llpp3_araddr_s_o14;
-    output fabric_llpp3_araddr_s_o15;
-    output fabric_llpp3_araddr_s_o16;
-    output fabric_llpp3_araddr_s_o17;
-    output fabric_llpp3_araddr_s_o18;
-    output fabric_llpp3_araddr_s_o19;
-    output fabric_llpp3_araddr_s_o2;
-    output fabric_llpp3_araddr_s_o20;
-    output fabric_llpp3_araddr_s_o21;
-    output fabric_llpp3_araddr_s_o22;
-    output fabric_llpp3_araddr_s_o23;
-    output fabric_llpp3_araddr_s_o24;
-    output fabric_llpp3_araddr_s_o25;
-    output fabric_llpp3_araddr_s_o26;
-    output fabric_llpp3_araddr_s_o27;
-    output fabric_llpp3_araddr_s_o28;
-    output fabric_llpp3_araddr_s_o29;
-    output fabric_llpp3_araddr_s_o3;
-    output fabric_llpp3_araddr_s_o30;
-    output fabric_llpp3_araddr_s_o31;
-    output fabric_llpp3_araddr_s_o32;
-    output fabric_llpp3_araddr_s_o4;
-    output fabric_llpp3_araddr_s_o5;
-    output fabric_llpp3_araddr_s_o6;
-    output fabric_llpp3_araddr_s_o7;
-    output fabric_llpp3_araddr_s_o8;
-    output fabric_llpp3_araddr_s_o9;
-    output fabric_llpp3_arburst_s_o1;
-    output fabric_llpp3_arburst_s_o2;
-    output fabric_llpp3_arcache_s_o1;
-    output fabric_llpp3_arcache_s_o2;
-    output fabric_llpp3_arcache_s_o3;
-    output fabric_llpp3_arcache_s_o4;
-    output fabric_llpp3_arid_s_o1;
-    output fabric_llpp3_arid_s_o10;
-    output fabric_llpp3_arid_s_o11;
-    output fabric_llpp3_arid_s_o12;
-    output fabric_llpp3_arid_s_o2;
-    output fabric_llpp3_arid_s_o3;
-    output fabric_llpp3_arid_s_o4;
-    output fabric_llpp3_arid_s_o5;
-    output fabric_llpp3_arid_s_o6;
-    output fabric_llpp3_arid_s_o7;
-    output fabric_llpp3_arid_s_o8;
-    output fabric_llpp3_arid_s_o9;
-    output fabric_llpp3_arlen_s_o1;
-    output fabric_llpp3_arlen_s_o2;
-    output fabric_llpp3_arlen_s_o3;
-    output fabric_llpp3_arlen_s_o4;
-    output fabric_llpp3_arlen_s_o5;
-    output fabric_llpp3_arlen_s_o6;
-    output fabric_llpp3_arlen_s_o7;
-    output fabric_llpp3_arlen_s_o8;
-    output fabric_llpp3_arlock_s_o;
-    output fabric_llpp3_arprot_s_o1;
-    output fabric_llpp3_arprot_s_o2;
-    output fabric_llpp3_arprot_s_o3;
-    output fabric_llpp3_arqos_s_o1;
-    output fabric_llpp3_arqos_s_o2;
-    output fabric_llpp3_arqos_s_o3;
-    output fabric_llpp3_arqos_s_o4;
-    input fabric_llpp3_arready_s_i;
-    output fabric_llpp3_arsize_s_o1;
-    output fabric_llpp3_arsize_s_o2;
-    output fabric_llpp3_arsize_s_o3;
-    output fabric_llpp3_arvalid_s_o;
-    output fabric_llpp3_awaddr_s_o1;
-    output fabric_llpp3_awaddr_s_o10;
-    output fabric_llpp3_awaddr_s_o11;
-    output fabric_llpp3_awaddr_s_o12;
-    output fabric_llpp3_awaddr_s_o13;
-    output fabric_llpp3_awaddr_s_o14;
-    output fabric_llpp3_awaddr_s_o15;
-    output fabric_llpp3_awaddr_s_o16;
-    output fabric_llpp3_awaddr_s_o17;
-    output fabric_llpp3_awaddr_s_o18;
-    output fabric_llpp3_awaddr_s_o19;
-    output fabric_llpp3_awaddr_s_o2;
-    output fabric_llpp3_awaddr_s_o20;
-    output fabric_llpp3_awaddr_s_o21;
-    output fabric_llpp3_awaddr_s_o22;
-    output fabric_llpp3_awaddr_s_o23;
-    output fabric_llpp3_awaddr_s_o24;
-    output fabric_llpp3_awaddr_s_o25;
-    output fabric_llpp3_awaddr_s_o26;
-    output fabric_llpp3_awaddr_s_o27;
-    output fabric_llpp3_awaddr_s_o28;
-    output fabric_llpp3_awaddr_s_o29;
-    output fabric_llpp3_awaddr_s_o3;
-    output fabric_llpp3_awaddr_s_o30;
-    output fabric_llpp3_awaddr_s_o31;
-    output fabric_llpp3_awaddr_s_o32;
-    output fabric_llpp3_awaddr_s_o4;
-    output fabric_llpp3_awaddr_s_o5;
-    output fabric_llpp3_awaddr_s_o6;
-    output fabric_llpp3_awaddr_s_o7;
-    output fabric_llpp3_awaddr_s_o8;
-    output fabric_llpp3_awaddr_s_o9;
-    output fabric_llpp3_awburst_s_o1;
-    output fabric_llpp3_awburst_s_o2;
-    output fabric_llpp3_awcache_s_o1;
-    output fabric_llpp3_awcache_s_o2;
-    output fabric_llpp3_awcache_s_o3;
-    output fabric_llpp3_awcache_s_o4;
-    output fabric_llpp3_awid_s_o1;
-    output fabric_llpp3_awid_s_o10;
-    output fabric_llpp3_awid_s_o11;
-    output fabric_llpp3_awid_s_o12;
-    output fabric_llpp3_awid_s_o2;
-    output fabric_llpp3_awid_s_o3;
-    output fabric_llpp3_awid_s_o4;
-    output fabric_llpp3_awid_s_o5;
-    output fabric_llpp3_awid_s_o6;
-    output fabric_llpp3_awid_s_o7;
-    output fabric_llpp3_awid_s_o8;
-    output fabric_llpp3_awid_s_o9;
-    output fabric_llpp3_awlen_s_o1;
-    output fabric_llpp3_awlen_s_o2;
-    output fabric_llpp3_awlen_s_o3;
-    output fabric_llpp3_awlen_s_o4;
-    output fabric_llpp3_awlen_s_o5;
-    output fabric_llpp3_awlen_s_o6;
-    output fabric_llpp3_awlen_s_o7;
-    output fabric_llpp3_awlen_s_o8;
-    output fabric_llpp3_awlock_s_o;
-    output fabric_llpp3_awprot_s_o1;
-    output fabric_llpp3_awprot_s_o2;
-    output fabric_llpp3_awprot_s_o3;
-    output fabric_llpp3_awqos_s_o1;
-    output fabric_llpp3_awqos_s_o2;
-    output fabric_llpp3_awqos_s_o3;
-    output fabric_llpp3_awqos_s_o4;
-    input fabric_llpp3_awready_s_i;
-    output fabric_llpp3_awsize_s_o1;
-    output fabric_llpp3_awsize_s_o2;
-    output fabric_llpp3_awsize_s_o3;
-    output fabric_llpp3_awvalid_s_o;
-    input fabric_llpp3_bid_s_i1;
-    input fabric_llpp3_bid_s_i10;
-    input fabric_llpp3_bid_s_i11;
-    input fabric_llpp3_bid_s_i12;
-    input fabric_llpp3_bid_s_i2;
-    input fabric_llpp3_bid_s_i3;
-    input fabric_llpp3_bid_s_i4;
-    input fabric_llpp3_bid_s_i5;
-    input fabric_llpp3_bid_s_i6;
-    input fabric_llpp3_bid_s_i7;
-    input fabric_llpp3_bid_s_i8;
-    input fabric_llpp3_bid_s_i9;
-    output fabric_llpp3_bready_s_o;
-    input fabric_llpp3_bresp_s_i1;
-    input fabric_llpp3_bresp_s_i2;
-    input fabric_llpp3_bvalid_s_i;
-    input fabric_llpp3_rdata_s_i1;
-    input fabric_llpp3_rdata_s_i10;
-    input fabric_llpp3_rdata_s_i11;
-    input fabric_llpp3_rdata_s_i12;
-    input fabric_llpp3_rdata_s_i13;
-    input fabric_llpp3_rdata_s_i14;
-    input fabric_llpp3_rdata_s_i15;
-    input fabric_llpp3_rdata_s_i16;
-    input fabric_llpp3_rdata_s_i17;
-    input fabric_llpp3_rdata_s_i18;
-    input fabric_llpp3_rdata_s_i19;
-    input fabric_llpp3_rdata_s_i2;
-    input fabric_llpp3_rdata_s_i20;
-    input fabric_llpp3_rdata_s_i21;
-    input fabric_llpp3_rdata_s_i22;
-    input fabric_llpp3_rdata_s_i23;
-    input fabric_llpp3_rdata_s_i24;
-    input fabric_llpp3_rdata_s_i25;
-    input fabric_llpp3_rdata_s_i26;
-    input fabric_llpp3_rdata_s_i27;
-    input fabric_llpp3_rdata_s_i28;
-    input fabric_llpp3_rdata_s_i29;
-    input fabric_llpp3_rdata_s_i3;
-    input fabric_llpp3_rdata_s_i30;
-    input fabric_llpp3_rdata_s_i31;
-    input fabric_llpp3_rdata_s_i32;
-    input fabric_llpp3_rdata_s_i4;
-    input fabric_llpp3_rdata_s_i5;
-    input fabric_llpp3_rdata_s_i6;
-    input fabric_llpp3_rdata_s_i7;
-    input fabric_llpp3_rdata_s_i8;
-    input fabric_llpp3_rdata_s_i9;
-    input fabric_llpp3_rid_s_i1;
-    input fabric_llpp3_rid_s_i10;
-    input fabric_llpp3_rid_s_i11;
-    input fabric_llpp3_rid_s_i12;
-    input fabric_llpp3_rid_s_i2;
-    input fabric_llpp3_rid_s_i3;
-    input fabric_llpp3_rid_s_i4;
-    input fabric_llpp3_rid_s_i5;
-    input fabric_llpp3_rid_s_i6;
-    input fabric_llpp3_rid_s_i7;
-    input fabric_llpp3_rid_s_i8;
-    input fabric_llpp3_rid_s_i9;
-    input fabric_llpp3_rlast_s_i;
-    output fabric_llpp3_rready_s_o;
-    input fabric_llpp3_rresp_s_i1;
-    input fabric_llpp3_rresp_s_i2;
-    input fabric_llpp3_rvalid_s_i;
-    output fabric_llpp3_wdata_s_o1;
-    output fabric_llpp3_wdata_s_o10;
-    output fabric_llpp3_wdata_s_o11;
-    output fabric_llpp3_wdata_s_o12;
-    output fabric_llpp3_wdata_s_o13;
-    output fabric_llpp3_wdata_s_o14;
-    output fabric_llpp3_wdata_s_o15;
-    output fabric_llpp3_wdata_s_o16;
-    output fabric_llpp3_wdata_s_o17;
-    output fabric_llpp3_wdata_s_o18;
-    output fabric_llpp3_wdata_s_o19;
-    output fabric_llpp3_wdata_s_o2;
-    output fabric_llpp3_wdata_s_o20;
-    output fabric_llpp3_wdata_s_o21;
-    output fabric_llpp3_wdata_s_o22;
-    output fabric_llpp3_wdata_s_o23;
-    output fabric_llpp3_wdata_s_o24;
-    output fabric_llpp3_wdata_s_o25;
-    output fabric_llpp3_wdata_s_o26;
-    output fabric_llpp3_wdata_s_o27;
-    output fabric_llpp3_wdata_s_o28;
-    output fabric_llpp3_wdata_s_o29;
-    output fabric_llpp3_wdata_s_o3;
-    output fabric_llpp3_wdata_s_o30;
-    output fabric_llpp3_wdata_s_o31;
-    output fabric_llpp3_wdata_s_o32;
-    output fabric_llpp3_wdata_s_o4;
-    output fabric_llpp3_wdata_s_o5;
-    output fabric_llpp3_wdata_s_o6;
-    output fabric_llpp3_wdata_s_o7;
-    output fabric_llpp3_wdata_s_o8;
-    output fabric_llpp3_wdata_s_o9;
-    output fabric_llpp3_wlast_s_o;
-    input fabric_llpp3_wready_s_i;
-    output fabric_llpp3_wstrb_s_o1;
-    output fabric_llpp3_wstrb_s_o2;
-    output fabric_llpp3_wstrb_s_o3;
-    output fabric_llpp3_wstrb_s_o4;
-    output fabric_llpp3_wvalid_s_o;
-    input fabric_lowskew_i1;
-    input fabric_lowskew_i10;
-    input fabric_lowskew_i2;
-    input fabric_lowskew_i3;
-    input fabric_lowskew_i4;
-    input fabric_lowskew_i5;
-    input fabric_lowskew_i6;
-    input fabric_lowskew_i7;
-    input fabric_lowskew_i8;
-    input fabric_lowskew_i9;
-    output fabric_lowskew_o1;
-    output fabric_lowskew_o2;
-    input fabric_qos_pclk_i;
-    input fabric_qos_ppaddr_i1;
-    input fabric_qos_ppaddr_i10;
-    input fabric_qos_ppaddr_i11;
-    input fabric_qos_ppaddr_i12;
-    input fabric_qos_ppaddr_i13;
-    input fabric_qos_ppaddr_i14;
-    input fabric_qos_ppaddr_i15;
-    input fabric_qos_ppaddr_i16;
-    input fabric_qos_ppaddr_i17;
-    input fabric_qos_ppaddr_i18;
-    input fabric_qos_ppaddr_i19;
-    input fabric_qos_ppaddr_i2;
-    input fabric_qos_ppaddr_i20;
-    input fabric_qos_ppaddr_i21;
-    input fabric_qos_ppaddr_i22;
-    input fabric_qos_ppaddr_i23;
-    input fabric_qos_ppaddr_i24;
-    input fabric_qos_ppaddr_i25;
-    input fabric_qos_ppaddr_i26;
-    input fabric_qos_ppaddr_i27;
-    input fabric_qos_ppaddr_i28;
-    input fabric_qos_ppaddr_i29;
-    input fabric_qos_ppaddr_i3;
-    input fabric_qos_ppaddr_i30;
-    input fabric_qos_ppaddr_i31;
-    input fabric_qos_ppaddr_i32;
-    input fabric_qos_ppaddr_i4;
-    input fabric_qos_ppaddr_i5;
-    input fabric_qos_ppaddr_i6;
-    input fabric_qos_ppaddr_i7;
-    input fabric_qos_ppaddr_i8;
-    input fabric_qos_ppaddr_i9;
-    input fabric_qos_ppenable_i;
-    output fabric_qos_pprdata_o1;
-    output fabric_qos_pprdata_o10;
-    output fabric_qos_pprdata_o11;
-    output fabric_qos_pprdata_o12;
-    output fabric_qos_pprdata_o13;
-    output fabric_qos_pprdata_o14;
-    output fabric_qos_pprdata_o15;
-    output fabric_qos_pprdata_o16;
-    output fabric_qos_pprdata_o17;
-    output fabric_qos_pprdata_o18;
-    output fabric_qos_pprdata_o19;
-    output fabric_qos_pprdata_o2;
-    output fabric_qos_pprdata_o20;
-    output fabric_qos_pprdata_o21;
-    output fabric_qos_pprdata_o22;
-    output fabric_qos_pprdata_o23;
-    output fabric_qos_pprdata_o24;
-    output fabric_qos_pprdata_o25;
-    output fabric_qos_pprdata_o26;
-    output fabric_qos_pprdata_o27;
-    output fabric_qos_pprdata_o28;
-    output fabric_qos_pprdata_o29;
-    output fabric_qos_pprdata_o3;
-    output fabric_qos_pprdata_o30;
-    output fabric_qos_pprdata_o31;
-    output fabric_qos_pprdata_o32;
-    output fabric_qos_pprdata_o4;
-    output fabric_qos_pprdata_o5;
-    output fabric_qos_pprdata_o6;
-    output fabric_qos_pprdata_o7;
-    output fabric_qos_pprdata_o8;
-    output fabric_qos_pprdata_o9;
-    output fabric_qos_ppready_o;
-    output fabric_qos_ppslverr_o;
-    input fabric_qos_ppwdata_i1;
-    input fabric_qos_ppwdata_i10;
-    input fabric_qos_ppwdata_i11;
-    input fabric_qos_ppwdata_i12;
-    input fabric_qos_ppwdata_i13;
-    input fabric_qos_ppwdata_i14;
-    input fabric_qos_ppwdata_i15;
-    input fabric_qos_ppwdata_i16;
-    input fabric_qos_ppwdata_i17;
-    input fabric_qos_ppwdata_i18;
-    input fabric_qos_ppwdata_i19;
-    input fabric_qos_ppwdata_i2;
-    input fabric_qos_ppwdata_i20;
-    input fabric_qos_ppwdata_i21;
-    input fabric_qos_ppwdata_i22;
-    input fabric_qos_ppwdata_i23;
-    input fabric_qos_ppwdata_i24;
-    input fabric_qos_ppwdata_i25;
-    input fabric_qos_ppwdata_i26;
-    input fabric_qos_ppwdata_i27;
-    input fabric_qos_ppwdata_i28;
-    input fabric_qos_ppwdata_i29;
-    input fabric_qos_ppwdata_i3;
-    input fabric_qos_ppwdata_i30;
-    input fabric_qos_ppwdata_i31;
-    input fabric_qos_ppwdata_i32;
-    input fabric_qos_ppwdata_i4;
-    input fabric_qos_ppwdata_i5;
-    input fabric_qos_ppwdata_i6;
-    input fabric_qos_ppwdata_i7;
-    input fabric_qos_ppwdata_i8;
-    input fabric_qos_ppwdata_i9;
-    input fabric_qos_ppwrite_i;
-    input fabric_qos_presetn_i;
-    input fabric_qos_psel_i;
-    output fabric_soc_mon_sensor_alarm_o;
-    input fabric_sysc_hold_on_debug_i;
-    output fabric_tnd_fpga_apb_master_paddr_o1;
-    output fabric_tnd_fpga_apb_master_paddr_o10;
-    output fabric_tnd_fpga_apb_master_paddr_o11;
-    output fabric_tnd_fpga_apb_master_paddr_o12;
-    output fabric_tnd_fpga_apb_master_paddr_o13;
-    output fabric_tnd_fpga_apb_master_paddr_o14;
-    output fabric_tnd_fpga_apb_master_paddr_o15;
-    output fabric_tnd_fpga_apb_master_paddr_o16;
-    output fabric_tnd_fpga_apb_master_paddr_o17;
-    output fabric_tnd_fpga_apb_master_paddr_o18;
-    output fabric_tnd_fpga_apb_master_paddr_o19;
-    output fabric_tnd_fpga_apb_master_paddr_o2;
-    output fabric_tnd_fpga_apb_master_paddr_o20;
-    output fabric_tnd_fpga_apb_master_paddr_o21;
-    output fabric_tnd_fpga_apb_master_paddr_o22;
-    output fabric_tnd_fpga_apb_master_paddr_o23;
-    output fabric_tnd_fpga_apb_master_paddr_o24;
-    output fabric_tnd_fpga_apb_master_paddr_o25;
-    output fabric_tnd_fpga_apb_master_paddr_o26;
-    output fabric_tnd_fpga_apb_master_paddr_o27;
-    output fabric_tnd_fpga_apb_master_paddr_o28;
-    output fabric_tnd_fpga_apb_master_paddr_o29;
-    output fabric_tnd_fpga_apb_master_paddr_o3;
-    output fabric_tnd_fpga_apb_master_paddr_o30;
-    output fabric_tnd_fpga_apb_master_paddr_o31;
-    output fabric_tnd_fpga_apb_master_paddr_o32;
-    output fabric_tnd_fpga_apb_master_paddr_o4;
-    output fabric_tnd_fpga_apb_master_paddr_o5;
-    output fabric_tnd_fpga_apb_master_paddr_o6;
-    output fabric_tnd_fpga_apb_master_paddr_o7;
-    output fabric_tnd_fpga_apb_master_paddr_o8;
-    output fabric_tnd_fpga_apb_master_paddr_o9;
-    output fabric_tnd_fpga_apb_master_penable_o;
-    input fabric_tnd_fpga_apb_master_prdata_i1;
-    input fabric_tnd_fpga_apb_master_prdata_i10;
-    input fabric_tnd_fpga_apb_master_prdata_i11;
-    input fabric_tnd_fpga_apb_master_prdata_i12;
-    input fabric_tnd_fpga_apb_master_prdata_i13;
-    input fabric_tnd_fpga_apb_master_prdata_i14;
-    input fabric_tnd_fpga_apb_master_prdata_i15;
-    input fabric_tnd_fpga_apb_master_prdata_i16;
-    input fabric_tnd_fpga_apb_master_prdata_i17;
-    input fabric_tnd_fpga_apb_master_prdata_i18;
-    input fabric_tnd_fpga_apb_master_prdata_i19;
-    input fabric_tnd_fpga_apb_master_prdata_i2;
-    input fabric_tnd_fpga_apb_master_prdata_i20;
-    input fabric_tnd_fpga_apb_master_prdata_i21;
-    input fabric_tnd_fpga_apb_master_prdata_i22;
-    input fabric_tnd_fpga_apb_master_prdata_i23;
-    input fabric_tnd_fpga_apb_master_prdata_i24;
-    input fabric_tnd_fpga_apb_master_prdata_i25;
-    input fabric_tnd_fpga_apb_master_prdata_i26;
-    input fabric_tnd_fpga_apb_master_prdata_i27;
-    input fabric_tnd_fpga_apb_master_prdata_i28;
-    input fabric_tnd_fpga_apb_master_prdata_i29;
-    input fabric_tnd_fpga_apb_master_prdata_i3;
-    input fabric_tnd_fpga_apb_master_prdata_i30;
-    input fabric_tnd_fpga_apb_master_prdata_i31;
-    input fabric_tnd_fpga_apb_master_prdata_i32;
-    input fabric_tnd_fpga_apb_master_prdata_i4;
-    input fabric_tnd_fpga_apb_master_prdata_i5;
-    input fabric_tnd_fpga_apb_master_prdata_i6;
-    input fabric_tnd_fpga_apb_master_prdata_i7;
-    input fabric_tnd_fpga_apb_master_prdata_i8;
-    input fabric_tnd_fpga_apb_master_prdata_i9;
-    input fabric_tnd_fpga_apb_master_pready_i;
-    output fabric_tnd_fpga_apb_master_psel_o;
-    input fabric_tnd_fpga_apb_master_pslverr_i;
-    output fabric_tnd_fpga_apb_master_pwdata_o1;
-    output fabric_tnd_fpga_apb_master_pwdata_o10;
-    output fabric_tnd_fpga_apb_master_pwdata_o11;
-    output fabric_tnd_fpga_apb_master_pwdata_o12;
-    output fabric_tnd_fpga_apb_master_pwdata_o13;
-    output fabric_tnd_fpga_apb_master_pwdata_o14;
-    output fabric_tnd_fpga_apb_master_pwdata_o15;
-    output fabric_tnd_fpga_apb_master_pwdata_o16;
-    output fabric_tnd_fpga_apb_master_pwdata_o17;
-    output fabric_tnd_fpga_apb_master_pwdata_o18;
-    output fabric_tnd_fpga_apb_master_pwdata_o19;
-    output fabric_tnd_fpga_apb_master_pwdata_o2;
-    output fabric_tnd_fpga_apb_master_pwdata_o20;
-    output fabric_tnd_fpga_apb_master_pwdata_o21;
-    output fabric_tnd_fpga_apb_master_pwdata_o22;
-    output fabric_tnd_fpga_apb_master_pwdata_o23;
-    output fabric_tnd_fpga_apb_master_pwdata_o24;
-    output fabric_tnd_fpga_apb_master_pwdata_o25;
-    output fabric_tnd_fpga_apb_master_pwdata_o26;
-    output fabric_tnd_fpga_apb_master_pwdata_o27;
-    output fabric_tnd_fpga_apb_master_pwdata_o28;
-    output fabric_tnd_fpga_apb_master_pwdata_o29;
-    output fabric_tnd_fpga_apb_master_pwdata_o3;
-    output fabric_tnd_fpga_apb_master_pwdata_o30;
-    output fabric_tnd_fpga_apb_master_pwdata_o31;
-    output fabric_tnd_fpga_apb_master_pwdata_o32;
-    output fabric_tnd_fpga_apb_master_pwdata_o4;
-    output fabric_tnd_fpga_apb_master_pwdata_o5;
-    output fabric_tnd_fpga_apb_master_pwdata_o6;
-    output fabric_tnd_fpga_apb_master_pwdata_o7;
-    output fabric_tnd_fpga_apb_master_pwdata_o8;
-    output fabric_tnd_fpga_apb_master_pwdata_o9;
-    output fabric_tnd_fpga_apb_master_pwrite_o;
-    input fabric_tnd_fpga_atb_master_afready_i;
-    output fabric_tnd_fpga_atb_master_afvalid_o;
-    input fabric_tnd_fpga_atb_master_atbytes_i1;
-    input fabric_tnd_fpga_atb_master_atbytes_i2;
-    input fabric_tnd_fpga_atb_master_atbytes_i3;
-    input fabric_tnd_fpga_atb_master_atbytes_i4;
-    input fabric_tnd_fpga_atb_master_atdata_i1;
-    input fabric_tnd_fpga_atb_master_atdata_i10;
-    input fabric_tnd_fpga_atb_master_atdata_i100;
-    input fabric_tnd_fpga_atb_master_atdata_i101;
-    input fabric_tnd_fpga_atb_master_atdata_i102;
-    input fabric_tnd_fpga_atb_master_atdata_i103;
-    input fabric_tnd_fpga_atb_master_atdata_i104;
-    input fabric_tnd_fpga_atb_master_atdata_i105;
-    input fabric_tnd_fpga_atb_master_atdata_i106;
-    input fabric_tnd_fpga_atb_master_atdata_i107;
-    input fabric_tnd_fpga_atb_master_atdata_i108;
-    input fabric_tnd_fpga_atb_master_atdata_i109;
-    input fabric_tnd_fpga_atb_master_atdata_i11;
-    input fabric_tnd_fpga_atb_master_atdata_i110;
-    input fabric_tnd_fpga_atb_master_atdata_i111;
-    input fabric_tnd_fpga_atb_master_atdata_i112;
-    input fabric_tnd_fpga_atb_master_atdata_i113;
-    input fabric_tnd_fpga_atb_master_atdata_i114;
-    input fabric_tnd_fpga_atb_master_atdata_i115;
-    input fabric_tnd_fpga_atb_master_atdata_i116;
-    input fabric_tnd_fpga_atb_master_atdata_i117;
-    input fabric_tnd_fpga_atb_master_atdata_i118;
-    input fabric_tnd_fpga_atb_master_atdata_i119;
-    input fabric_tnd_fpga_atb_master_atdata_i12;
-    input fabric_tnd_fpga_atb_master_atdata_i120;
-    input fabric_tnd_fpga_atb_master_atdata_i121;
-    input fabric_tnd_fpga_atb_master_atdata_i122;
-    input fabric_tnd_fpga_atb_master_atdata_i123;
-    input fabric_tnd_fpga_atb_master_atdata_i124;
-    input fabric_tnd_fpga_atb_master_atdata_i125;
-    input fabric_tnd_fpga_atb_master_atdata_i126;
-    input fabric_tnd_fpga_atb_master_atdata_i127;
-    input fabric_tnd_fpga_atb_master_atdata_i128;
-    input fabric_tnd_fpga_atb_master_atdata_i13;
-    input fabric_tnd_fpga_atb_master_atdata_i14;
-    input fabric_tnd_fpga_atb_master_atdata_i15;
-    input fabric_tnd_fpga_atb_master_atdata_i16;
-    input fabric_tnd_fpga_atb_master_atdata_i17;
-    input fabric_tnd_fpga_atb_master_atdata_i18;
-    input fabric_tnd_fpga_atb_master_atdata_i19;
-    input fabric_tnd_fpga_atb_master_atdata_i2;
-    input fabric_tnd_fpga_atb_master_atdata_i20;
-    input fabric_tnd_fpga_atb_master_atdata_i21;
-    input fabric_tnd_fpga_atb_master_atdata_i22;
-    input fabric_tnd_fpga_atb_master_atdata_i23;
-    input fabric_tnd_fpga_atb_master_atdata_i24;
-    input fabric_tnd_fpga_atb_master_atdata_i25;
-    input fabric_tnd_fpga_atb_master_atdata_i26;
-    input fabric_tnd_fpga_atb_master_atdata_i27;
-    input fabric_tnd_fpga_atb_master_atdata_i28;
-    input fabric_tnd_fpga_atb_master_atdata_i29;
-    input fabric_tnd_fpga_atb_master_atdata_i3;
-    input fabric_tnd_fpga_atb_master_atdata_i30;
-    input fabric_tnd_fpga_atb_master_atdata_i31;
-    input fabric_tnd_fpga_atb_master_atdata_i32;
-    input fabric_tnd_fpga_atb_master_atdata_i33;
-    input fabric_tnd_fpga_atb_master_atdata_i34;
-    input fabric_tnd_fpga_atb_master_atdata_i35;
-    input fabric_tnd_fpga_atb_master_atdata_i36;
-    input fabric_tnd_fpga_atb_master_atdata_i37;
-    input fabric_tnd_fpga_atb_master_atdata_i38;
-    input fabric_tnd_fpga_atb_master_atdata_i39;
-    input fabric_tnd_fpga_atb_master_atdata_i4;
-    input fabric_tnd_fpga_atb_master_atdata_i40;
-    input fabric_tnd_fpga_atb_master_atdata_i41;
-    input fabric_tnd_fpga_atb_master_atdata_i42;
-    input fabric_tnd_fpga_atb_master_atdata_i43;
-    input fabric_tnd_fpga_atb_master_atdata_i44;
-    input fabric_tnd_fpga_atb_master_atdata_i45;
-    input fabric_tnd_fpga_atb_master_atdata_i46;
-    input fabric_tnd_fpga_atb_master_atdata_i47;
-    input fabric_tnd_fpga_atb_master_atdata_i48;
-    input fabric_tnd_fpga_atb_master_atdata_i49;
-    input fabric_tnd_fpga_atb_master_atdata_i5;
-    input fabric_tnd_fpga_atb_master_atdata_i50;
-    input fabric_tnd_fpga_atb_master_atdata_i51;
-    input fabric_tnd_fpga_atb_master_atdata_i52;
-    input fabric_tnd_fpga_atb_master_atdata_i53;
-    input fabric_tnd_fpga_atb_master_atdata_i54;
-    input fabric_tnd_fpga_atb_master_atdata_i55;
-    input fabric_tnd_fpga_atb_master_atdata_i56;
-    input fabric_tnd_fpga_atb_master_atdata_i57;
-    input fabric_tnd_fpga_atb_master_atdata_i58;
-    input fabric_tnd_fpga_atb_master_atdata_i59;
-    input fabric_tnd_fpga_atb_master_atdata_i6;
-    input fabric_tnd_fpga_atb_master_atdata_i60;
-    input fabric_tnd_fpga_atb_master_atdata_i61;
-    input fabric_tnd_fpga_atb_master_atdata_i62;
-    input fabric_tnd_fpga_atb_master_atdata_i63;
-    input fabric_tnd_fpga_atb_master_atdata_i64;
-    input fabric_tnd_fpga_atb_master_atdata_i65;
-    input fabric_tnd_fpga_atb_master_atdata_i66;
-    input fabric_tnd_fpga_atb_master_atdata_i67;
-    input fabric_tnd_fpga_atb_master_atdata_i68;
-    input fabric_tnd_fpga_atb_master_atdata_i69;
-    input fabric_tnd_fpga_atb_master_atdata_i7;
-    input fabric_tnd_fpga_atb_master_atdata_i70;
-    input fabric_tnd_fpga_atb_master_atdata_i71;
-    input fabric_tnd_fpga_atb_master_atdata_i72;
-    input fabric_tnd_fpga_atb_master_atdata_i73;
-    input fabric_tnd_fpga_atb_master_atdata_i74;
-    input fabric_tnd_fpga_atb_master_atdata_i75;
-    input fabric_tnd_fpga_atb_master_atdata_i76;
-    input fabric_tnd_fpga_atb_master_atdata_i77;
-    input fabric_tnd_fpga_atb_master_atdata_i78;
-    input fabric_tnd_fpga_atb_master_atdata_i79;
-    input fabric_tnd_fpga_atb_master_atdata_i8;
-    input fabric_tnd_fpga_atb_master_atdata_i80;
-    input fabric_tnd_fpga_atb_master_atdata_i81;
-    input fabric_tnd_fpga_atb_master_atdata_i82;
-    input fabric_tnd_fpga_atb_master_atdata_i83;
-    input fabric_tnd_fpga_atb_master_atdata_i84;
-    input fabric_tnd_fpga_atb_master_atdata_i85;
-    input fabric_tnd_fpga_atb_master_atdata_i86;
-    input fabric_tnd_fpga_atb_master_atdata_i87;
-    input fabric_tnd_fpga_atb_master_atdata_i88;
-    input fabric_tnd_fpga_atb_master_atdata_i89;
-    input fabric_tnd_fpga_atb_master_atdata_i9;
-    input fabric_tnd_fpga_atb_master_atdata_i90;
-    input fabric_tnd_fpga_atb_master_atdata_i91;
-    input fabric_tnd_fpga_atb_master_atdata_i92;
-    input fabric_tnd_fpga_atb_master_atdata_i93;
-    input fabric_tnd_fpga_atb_master_atdata_i94;
-    input fabric_tnd_fpga_atb_master_atdata_i95;
-    input fabric_tnd_fpga_atb_master_atdata_i96;
-    input fabric_tnd_fpga_atb_master_atdata_i97;
-    input fabric_tnd_fpga_atb_master_atdata_i98;
-    input fabric_tnd_fpga_atb_master_atdata_i99;
-    input fabric_tnd_fpga_atb_master_atid_i1;
-    input fabric_tnd_fpga_atb_master_atid_i2;
-    input fabric_tnd_fpga_atb_master_atid_i3;
-    input fabric_tnd_fpga_atb_master_atid_i4;
-    input fabric_tnd_fpga_atb_master_atid_i5;
-    input fabric_tnd_fpga_atb_master_atid_i6;
-    input fabric_tnd_fpga_atb_master_atid_i7;
-    output fabric_tnd_fpga_atb_master_atready_o;
-    input fabric_tnd_fpga_atb_master_atvalid_i;
-    output fabric_tnd_fpga_atb_master_syncreq_o;
-    output fabric_tnd_hssl_apb_master_paddr_o1;
-    output fabric_tnd_hssl_apb_master_paddr_o10;
-    output fabric_tnd_hssl_apb_master_paddr_o11;
-    output fabric_tnd_hssl_apb_master_paddr_o12;
-    output fabric_tnd_hssl_apb_master_paddr_o13;
-    output fabric_tnd_hssl_apb_master_paddr_o14;
-    output fabric_tnd_hssl_apb_master_paddr_o15;
-    output fabric_tnd_hssl_apb_master_paddr_o16;
-    output fabric_tnd_hssl_apb_master_paddr_o17;
-    output fabric_tnd_hssl_apb_master_paddr_o18;
-    output fabric_tnd_hssl_apb_master_paddr_o19;
-    output fabric_tnd_hssl_apb_master_paddr_o2;
-    output fabric_tnd_hssl_apb_master_paddr_o20;
-    output fabric_tnd_hssl_apb_master_paddr_o21;
-    output fabric_tnd_hssl_apb_master_paddr_o22;
-    output fabric_tnd_hssl_apb_master_paddr_o23;
-    output fabric_tnd_hssl_apb_master_paddr_o24;
-    output fabric_tnd_hssl_apb_master_paddr_o25;
-    output fabric_tnd_hssl_apb_master_paddr_o26;
-    output fabric_tnd_hssl_apb_master_paddr_o27;
-    output fabric_tnd_hssl_apb_master_paddr_o28;
-    output fabric_tnd_hssl_apb_master_paddr_o29;
-    output fabric_tnd_hssl_apb_master_paddr_o3;
-    output fabric_tnd_hssl_apb_master_paddr_o30;
-    output fabric_tnd_hssl_apb_master_paddr_o31;
-    output fabric_tnd_hssl_apb_master_paddr_o32;
-    output fabric_tnd_hssl_apb_master_paddr_o4;
-    output fabric_tnd_hssl_apb_master_paddr_o5;
-    output fabric_tnd_hssl_apb_master_paddr_o6;
-    output fabric_tnd_hssl_apb_master_paddr_o7;
-    output fabric_tnd_hssl_apb_master_paddr_o8;
-    output fabric_tnd_hssl_apb_master_paddr_o9;
-    output fabric_tnd_hssl_apb_master_penable_o;
-    input fabric_tnd_hssl_apb_master_prdata_i1;
-    input fabric_tnd_hssl_apb_master_prdata_i10;
-    input fabric_tnd_hssl_apb_master_prdata_i11;
-    input fabric_tnd_hssl_apb_master_prdata_i12;
-    input fabric_tnd_hssl_apb_master_prdata_i13;
-    input fabric_tnd_hssl_apb_master_prdata_i14;
-    input fabric_tnd_hssl_apb_master_prdata_i15;
-    input fabric_tnd_hssl_apb_master_prdata_i16;
-    input fabric_tnd_hssl_apb_master_prdata_i17;
-    input fabric_tnd_hssl_apb_master_prdata_i18;
-    input fabric_tnd_hssl_apb_master_prdata_i19;
-    input fabric_tnd_hssl_apb_master_prdata_i2;
-    input fabric_tnd_hssl_apb_master_prdata_i20;
-    input fabric_tnd_hssl_apb_master_prdata_i21;
-    input fabric_tnd_hssl_apb_master_prdata_i22;
-    input fabric_tnd_hssl_apb_master_prdata_i23;
-    input fabric_tnd_hssl_apb_master_prdata_i24;
-    input fabric_tnd_hssl_apb_master_prdata_i25;
-    input fabric_tnd_hssl_apb_master_prdata_i26;
-    input fabric_tnd_hssl_apb_master_prdata_i27;
-    input fabric_tnd_hssl_apb_master_prdata_i28;
-    input fabric_tnd_hssl_apb_master_prdata_i29;
-    input fabric_tnd_hssl_apb_master_prdata_i3;
-    input fabric_tnd_hssl_apb_master_prdata_i30;
-    input fabric_tnd_hssl_apb_master_prdata_i31;
-    input fabric_tnd_hssl_apb_master_prdata_i32;
-    input fabric_tnd_hssl_apb_master_prdata_i4;
-    input fabric_tnd_hssl_apb_master_prdata_i5;
-    input fabric_tnd_hssl_apb_master_prdata_i6;
-    input fabric_tnd_hssl_apb_master_prdata_i7;
-    input fabric_tnd_hssl_apb_master_prdata_i8;
-    input fabric_tnd_hssl_apb_master_prdata_i9;
-    input fabric_tnd_hssl_apb_master_pready_i;
-    output fabric_tnd_hssl_apb_master_psel_o;
-    input fabric_tnd_hssl_apb_master_pslverr_i;
-    output fabric_tnd_hssl_apb_master_pwdata_o1;
-    output fabric_tnd_hssl_apb_master_pwdata_o10;
-    output fabric_tnd_hssl_apb_master_pwdata_o11;
-    output fabric_tnd_hssl_apb_master_pwdata_o12;
-    output fabric_tnd_hssl_apb_master_pwdata_o13;
-    output fabric_tnd_hssl_apb_master_pwdata_o14;
-    output fabric_tnd_hssl_apb_master_pwdata_o15;
-    output fabric_tnd_hssl_apb_master_pwdata_o16;
-    output fabric_tnd_hssl_apb_master_pwdata_o17;
-    output fabric_tnd_hssl_apb_master_pwdata_o18;
-    output fabric_tnd_hssl_apb_master_pwdata_o19;
-    output fabric_tnd_hssl_apb_master_pwdata_o2;
-    output fabric_tnd_hssl_apb_master_pwdata_o20;
-    output fabric_tnd_hssl_apb_master_pwdata_o21;
-    output fabric_tnd_hssl_apb_master_pwdata_o22;
-    output fabric_tnd_hssl_apb_master_pwdata_o23;
-    output fabric_tnd_hssl_apb_master_pwdata_o24;
-    output fabric_tnd_hssl_apb_master_pwdata_o25;
-    output fabric_tnd_hssl_apb_master_pwdata_o26;
-    output fabric_tnd_hssl_apb_master_pwdata_o27;
-    output fabric_tnd_hssl_apb_master_pwdata_o28;
-    output fabric_tnd_hssl_apb_master_pwdata_o29;
-    output fabric_tnd_hssl_apb_master_pwdata_o3;
-    output fabric_tnd_hssl_apb_master_pwdata_o30;
-    output fabric_tnd_hssl_apb_master_pwdata_o31;
-    output fabric_tnd_hssl_apb_master_pwdata_o32;
-    output fabric_tnd_hssl_apb_master_pwdata_o4;
-    output fabric_tnd_hssl_apb_master_pwdata_o5;
-    output fabric_tnd_hssl_apb_master_pwdata_o6;
-    output fabric_tnd_hssl_apb_master_pwdata_o7;
-    output fabric_tnd_hssl_apb_master_pwdata_o8;
-    output fabric_tnd_hssl_apb_master_pwdata_o9;
-    output fabric_tnd_hssl_apb_master_pwrite_o;
-    output fabric_tnd_hssl_atb_master_afready_o;
-    input fabric_tnd_hssl_atb_master_afvalid_i;
-    output fabric_tnd_hssl_atb_master_atbytes_o1;
-    output fabric_tnd_hssl_atb_master_atbytes_o2;
-    output fabric_tnd_hssl_atb_master_atbytes_o3;
-    output fabric_tnd_hssl_atb_master_atbytes_o4;
-    output fabric_tnd_hssl_atb_master_atdata_o1;
-    output fabric_tnd_hssl_atb_master_atdata_o10;
-    output fabric_tnd_hssl_atb_master_atdata_o100;
-    output fabric_tnd_hssl_atb_master_atdata_o101;
-    output fabric_tnd_hssl_atb_master_atdata_o102;
-    output fabric_tnd_hssl_atb_master_atdata_o103;
-    output fabric_tnd_hssl_atb_master_atdata_o104;
-    output fabric_tnd_hssl_atb_master_atdata_o105;
-    output fabric_tnd_hssl_atb_master_atdata_o106;
-    output fabric_tnd_hssl_atb_master_atdata_o107;
-    output fabric_tnd_hssl_atb_master_atdata_o108;
-    output fabric_tnd_hssl_atb_master_atdata_o109;
-    output fabric_tnd_hssl_atb_master_atdata_o11;
-    output fabric_tnd_hssl_atb_master_atdata_o110;
-    output fabric_tnd_hssl_atb_master_atdata_o111;
-    output fabric_tnd_hssl_atb_master_atdata_o112;
-    output fabric_tnd_hssl_atb_master_atdata_o113;
-    output fabric_tnd_hssl_atb_master_atdata_o114;
-    output fabric_tnd_hssl_atb_master_atdata_o115;
-    output fabric_tnd_hssl_atb_master_atdata_o116;
-    output fabric_tnd_hssl_atb_master_atdata_o117;
-    output fabric_tnd_hssl_atb_master_atdata_o118;
-    output fabric_tnd_hssl_atb_master_atdata_o119;
-    output fabric_tnd_hssl_atb_master_atdata_o12;
-    output fabric_tnd_hssl_atb_master_atdata_o120;
-    output fabric_tnd_hssl_atb_master_atdata_o121;
-    output fabric_tnd_hssl_atb_master_atdata_o122;
-    output fabric_tnd_hssl_atb_master_atdata_o123;
-    output fabric_tnd_hssl_atb_master_atdata_o124;
-    output fabric_tnd_hssl_atb_master_atdata_o125;
-    output fabric_tnd_hssl_atb_master_atdata_o126;
-    output fabric_tnd_hssl_atb_master_atdata_o127;
-    output fabric_tnd_hssl_atb_master_atdata_o128;
-    output fabric_tnd_hssl_atb_master_atdata_o13;
-    output fabric_tnd_hssl_atb_master_atdata_o14;
-    output fabric_tnd_hssl_atb_master_atdata_o15;
-    output fabric_tnd_hssl_atb_master_atdata_o16;
-    output fabric_tnd_hssl_atb_master_atdata_o17;
-    output fabric_tnd_hssl_atb_master_atdata_o18;
-    output fabric_tnd_hssl_atb_master_atdata_o19;
-    output fabric_tnd_hssl_atb_master_atdata_o2;
-    output fabric_tnd_hssl_atb_master_atdata_o20;
-    output fabric_tnd_hssl_atb_master_atdata_o21;
-    output fabric_tnd_hssl_atb_master_atdata_o22;
-    output fabric_tnd_hssl_atb_master_atdata_o23;
-    output fabric_tnd_hssl_atb_master_atdata_o24;
-    output fabric_tnd_hssl_atb_master_atdata_o25;
-    output fabric_tnd_hssl_atb_master_atdata_o26;
-    output fabric_tnd_hssl_atb_master_atdata_o27;
-    output fabric_tnd_hssl_atb_master_atdata_o28;
-    output fabric_tnd_hssl_atb_master_atdata_o29;
-    output fabric_tnd_hssl_atb_master_atdata_o3;
-    output fabric_tnd_hssl_atb_master_atdata_o30;
-    output fabric_tnd_hssl_atb_master_atdata_o31;
-    output fabric_tnd_hssl_atb_master_atdata_o32;
-    output fabric_tnd_hssl_atb_master_atdata_o33;
-    output fabric_tnd_hssl_atb_master_atdata_o34;
-    output fabric_tnd_hssl_atb_master_atdata_o35;
-    output fabric_tnd_hssl_atb_master_atdata_o36;
-    output fabric_tnd_hssl_atb_master_atdata_o37;
-    output fabric_tnd_hssl_atb_master_atdata_o38;
-    output fabric_tnd_hssl_atb_master_atdata_o39;
-    output fabric_tnd_hssl_atb_master_atdata_o4;
-    output fabric_tnd_hssl_atb_master_atdata_o40;
-    output fabric_tnd_hssl_atb_master_atdata_o41;
-    output fabric_tnd_hssl_atb_master_atdata_o42;
-    output fabric_tnd_hssl_atb_master_atdata_o43;
-    output fabric_tnd_hssl_atb_master_atdata_o44;
-    output fabric_tnd_hssl_atb_master_atdata_o45;
-    output fabric_tnd_hssl_atb_master_atdata_o46;
-    output fabric_tnd_hssl_atb_master_atdata_o47;
-    output fabric_tnd_hssl_atb_master_atdata_o48;
-    output fabric_tnd_hssl_atb_master_atdata_o49;
-    output fabric_tnd_hssl_atb_master_atdata_o5;
-    output fabric_tnd_hssl_atb_master_atdata_o50;
-    output fabric_tnd_hssl_atb_master_atdata_o51;
-    output fabric_tnd_hssl_atb_master_atdata_o52;
-    output fabric_tnd_hssl_atb_master_atdata_o53;
-    output fabric_tnd_hssl_atb_master_atdata_o54;
-    output fabric_tnd_hssl_atb_master_atdata_o55;
-    output fabric_tnd_hssl_atb_master_atdata_o56;
-    output fabric_tnd_hssl_atb_master_atdata_o57;
-    output fabric_tnd_hssl_atb_master_atdata_o58;
-    output fabric_tnd_hssl_atb_master_atdata_o59;
-    output fabric_tnd_hssl_atb_master_atdata_o6;
-    output fabric_tnd_hssl_atb_master_atdata_o60;
-    output fabric_tnd_hssl_atb_master_atdata_o61;
-    output fabric_tnd_hssl_atb_master_atdata_o62;
-    output fabric_tnd_hssl_atb_master_atdata_o63;
-    output fabric_tnd_hssl_atb_master_atdata_o64;
-    output fabric_tnd_hssl_atb_master_atdata_o65;
-    output fabric_tnd_hssl_atb_master_atdata_o66;
-    output fabric_tnd_hssl_atb_master_atdata_o67;
-    output fabric_tnd_hssl_atb_master_atdata_o68;
-    output fabric_tnd_hssl_atb_master_atdata_o69;
-    output fabric_tnd_hssl_atb_master_atdata_o7;
-    output fabric_tnd_hssl_atb_master_atdata_o70;
-    output fabric_tnd_hssl_atb_master_atdata_o71;
-    output fabric_tnd_hssl_atb_master_atdata_o72;
-    output fabric_tnd_hssl_atb_master_atdata_o73;
-    output fabric_tnd_hssl_atb_master_atdata_o74;
-    output fabric_tnd_hssl_atb_master_atdata_o75;
-    output fabric_tnd_hssl_atb_master_atdata_o76;
-    output fabric_tnd_hssl_atb_master_atdata_o77;
-    output fabric_tnd_hssl_atb_master_atdata_o78;
-    output fabric_tnd_hssl_atb_master_atdata_o79;
-    output fabric_tnd_hssl_atb_master_atdata_o8;
-    output fabric_tnd_hssl_atb_master_atdata_o80;
-    output fabric_tnd_hssl_atb_master_atdata_o81;
-    output fabric_tnd_hssl_atb_master_atdata_o82;
-    output fabric_tnd_hssl_atb_master_atdata_o83;
-    output fabric_tnd_hssl_atb_master_atdata_o84;
-    output fabric_tnd_hssl_atb_master_atdata_o85;
-    output fabric_tnd_hssl_atb_master_atdata_o86;
-    output fabric_tnd_hssl_atb_master_atdata_o87;
-    output fabric_tnd_hssl_atb_master_atdata_o88;
-    output fabric_tnd_hssl_atb_master_atdata_o89;
-    output fabric_tnd_hssl_atb_master_atdata_o9;
-    output fabric_tnd_hssl_atb_master_atdata_o90;
-    output fabric_tnd_hssl_atb_master_atdata_o91;
-    output fabric_tnd_hssl_atb_master_atdata_o92;
-    output fabric_tnd_hssl_atb_master_atdata_o93;
-    output fabric_tnd_hssl_atb_master_atdata_o94;
-    output fabric_tnd_hssl_atb_master_atdata_o95;
-    output fabric_tnd_hssl_atb_master_atdata_o96;
-    output fabric_tnd_hssl_atb_master_atdata_o97;
-    output fabric_tnd_hssl_atb_master_atdata_o98;
-    output fabric_tnd_hssl_atb_master_atdata_o99;
-    output fabric_tnd_hssl_atb_master_atid_o1;
-    output fabric_tnd_hssl_atb_master_atid_o2;
-    output fabric_tnd_hssl_atb_master_atid_o3;
-    output fabric_tnd_hssl_atb_master_atid_o4;
-    output fabric_tnd_hssl_atb_master_atid_o5;
-    output fabric_tnd_hssl_atb_master_atid_o6;
-    output fabric_tnd_hssl_atb_master_atid_o7;
-    input fabric_tnd_hssl_atb_master_atready_i;
-    output fabric_tnd_hssl_atb_master_atvalid_o;
-    input fabric_tnd_hssl_atb_master_syncreq_i;
-    output fabric_tnd_hssl_flushin_o;
-    output fabric_tnd_hssl_trigin_o;
-    output fabric_tnd_trace_clk_traceoutportintf_o;
-    output fabric_tnd_trace_ctl_traceoutportintf_o;
-    output fabric_tnd_trace_data_traceoutportintf_o1;
-    output fabric_tnd_trace_data_traceoutportintf_o10;
-    output fabric_tnd_trace_data_traceoutportintf_o11;
-    output fabric_tnd_trace_data_traceoutportintf_o12;
-    output fabric_tnd_trace_data_traceoutportintf_o13;
-    output fabric_tnd_trace_data_traceoutportintf_o14;
-    output fabric_tnd_trace_data_traceoutportintf_o15;
-    output fabric_tnd_trace_data_traceoutportintf_o16;
-    output fabric_tnd_trace_data_traceoutportintf_o17;
-    output fabric_tnd_trace_data_traceoutportintf_o18;
-    output fabric_tnd_trace_data_traceoutportintf_o19;
-    output fabric_tnd_trace_data_traceoutportintf_o2;
-    output fabric_tnd_trace_data_traceoutportintf_o20;
-    output fabric_tnd_trace_data_traceoutportintf_o21;
-    output fabric_tnd_trace_data_traceoutportintf_o22;
-    output fabric_tnd_trace_data_traceoutportintf_o23;
-    output fabric_tnd_trace_data_traceoutportintf_o24;
-    output fabric_tnd_trace_data_traceoutportintf_o25;
-    output fabric_tnd_trace_data_traceoutportintf_o26;
-    output fabric_tnd_trace_data_traceoutportintf_o27;
-    output fabric_tnd_trace_data_traceoutportintf_o28;
-    output fabric_tnd_trace_data_traceoutportintf_o29;
-    output fabric_tnd_trace_data_traceoutportintf_o3;
-    output fabric_tnd_trace_data_traceoutportintf_o30;
-    output fabric_tnd_trace_data_traceoutportintf_o31;
-    output fabric_tnd_trace_data_traceoutportintf_o32;
-    output fabric_tnd_trace_data_traceoutportintf_o4;
-    output fabric_tnd_trace_data_traceoutportintf_o5;
-    output fabric_tnd_trace_data_traceoutportintf_o6;
-    output fabric_tnd_trace_data_traceoutportintf_o7;
-    output fabric_tnd_trace_data_traceoutportintf_o8;
-    output fabric_tnd_trace_data_traceoutportintf_o9;
-    output fabric_tst_pll_lock_o1;
-    output fabric_tst_pll_lock_o2;
-    output fabric_tst_pll_lock_o3;
-    output fabric_tst_pll_lock_o4;
-    output fabric_tst_pll_lock_o5;
-    output fabric_tst_pll_lock_o6;
-    output fabric_tst_pll_lock_o7;
-    output fabric_tsvalue_tsgen_fpga_o1;
-    output fabric_tsvalue_tsgen_fpga_o10;
-    output fabric_tsvalue_tsgen_fpga_o11;
-    output fabric_tsvalue_tsgen_fpga_o12;
-    output fabric_tsvalue_tsgen_fpga_o13;
-    output fabric_tsvalue_tsgen_fpga_o14;
-    output fabric_tsvalue_tsgen_fpga_o15;
-    output fabric_tsvalue_tsgen_fpga_o16;
-    output fabric_tsvalue_tsgen_fpga_o17;
-    output fabric_tsvalue_tsgen_fpga_o18;
-    output fabric_tsvalue_tsgen_fpga_o19;
-    output fabric_tsvalue_tsgen_fpga_o2;
-    output fabric_tsvalue_tsgen_fpga_o20;
-    output fabric_tsvalue_tsgen_fpga_o21;
-    output fabric_tsvalue_tsgen_fpga_o22;
-    output fabric_tsvalue_tsgen_fpga_o23;
-    output fabric_tsvalue_tsgen_fpga_o24;
-    output fabric_tsvalue_tsgen_fpga_o25;
-    output fabric_tsvalue_tsgen_fpga_o26;
-    output fabric_tsvalue_tsgen_fpga_o27;
-    output fabric_tsvalue_tsgen_fpga_o28;
-    output fabric_tsvalue_tsgen_fpga_o29;
-    output fabric_tsvalue_tsgen_fpga_o3;
-    output fabric_tsvalue_tsgen_fpga_o30;
-    output fabric_tsvalue_tsgen_fpga_o31;
-    output fabric_tsvalue_tsgen_fpga_o32;
-    output fabric_tsvalue_tsgen_fpga_o33;
-    output fabric_tsvalue_tsgen_fpga_o34;
-    output fabric_tsvalue_tsgen_fpga_o35;
-    output fabric_tsvalue_tsgen_fpga_o36;
-    output fabric_tsvalue_tsgen_fpga_o37;
-    output fabric_tsvalue_tsgen_fpga_o38;
-    output fabric_tsvalue_tsgen_fpga_o39;
-    output fabric_tsvalue_tsgen_fpga_o4;
-    output fabric_tsvalue_tsgen_fpga_o40;
-    output fabric_tsvalue_tsgen_fpga_o41;
-    output fabric_tsvalue_tsgen_fpga_o42;
-    output fabric_tsvalue_tsgen_fpga_o43;
-    output fabric_tsvalue_tsgen_fpga_o44;
-    output fabric_tsvalue_tsgen_fpga_o45;
-    output fabric_tsvalue_tsgen_fpga_o46;
-    output fabric_tsvalue_tsgen_fpga_o47;
-    output fabric_tsvalue_tsgen_fpga_o48;
-    output fabric_tsvalue_tsgen_fpga_o49;
-    output fabric_tsvalue_tsgen_fpga_o5;
-    output fabric_tsvalue_tsgen_fpga_o50;
-    output fabric_tsvalue_tsgen_fpga_o51;
-    output fabric_tsvalue_tsgen_fpga_o52;
-    output fabric_tsvalue_tsgen_fpga_o53;
-    output fabric_tsvalue_tsgen_fpga_o54;
-    output fabric_tsvalue_tsgen_fpga_o55;
-    output fabric_tsvalue_tsgen_fpga_o56;
-    output fabric_tsvalue_tsgen_fpga_o57;
-    output fabric_tsvalue_tsgen_fpga_o58;
-    output fabric_tsvalue_tsgen_fpga_o59;
-    output fabric_tsvalue_tsgen_fpga_o6;
-    output fabric_tsvalue_tsgen_fpga_o60;
-    output fabric_tsvalue_tsgen_fpga_o61;
-    output fabric_tsvalue_tsgen_fpga_o62;
-    output fabric_tsvalue_tsgen_fpga_o63;
-    output fabric_tsvalue_tsgen_fpga_o64;
-    output fabric_tsvalue_tsgen_fpga_o7;
-    output fabric_tsvalue_tsgen_fpga_o8;
-    output fabric_tsvalue_tsgen_fpga_o9;
-    output fabric_watchdog0_signal_0_o;
-    output fabric_watchdog0_signal_1_o;
-    output fabric_watchdog1_signal_0_o;
-    output fabric_watchdog1_signal_1_o;
-    output fabric_watchdog2_signal_0_o;
-    output fabric_watchdog2_signal_1_o;
-    output fabric_watchdog3_signal_0_o;
-    output fabric_watchdog3_signal_1_o;
-    parameter ahb_config = 0;
-    parameter bsm_config = 0;
-endmodule
-
-(* blackbox *)
-module NX_SOC_INTERFACE_V1_WRAP(fabric_fpga_pmrstn_i, fabric_fpga_sysrstn_i, fabric_sysc_hold_on_debug_i, fabric_fpga_arlock_axi_s1_o, fabric_fpga_arvalid_axi_s1_o, fabric_fpga_awlock_axi_s1_o, fabric_fpga_bready_axi_s1_o, fabric_fpga_rready_axi_s1_o, fabric_fpga_wlast_axi_s1_o, fabric_fpga_wvalid_axi_s1_o, fabric_fpga_awvalid_axi_s1_o, fabric_fpga_arready_axi_s1_i, fabric_fpga_awready_axi_s1_i, fabric_fpga_bvalid_axi_s1_i, fabric_fpga_rlast_axi_s1_i, fabric_fpga_rvalid_axi_s1_i, fabric_fpga_wready_axi_s1_i, fabric_fpga_arlock_axi_s2_o, fabric_fpga_arvalid_axi_s2_o, fabric_fpga_awlock_axi_s2_o, fabric_fpga_bready_axi_s2_o
-, fabric_fpga_rready_axi_s2_o, fabric_fpga_wlast_axi_s2_o, fabric_fpga_wvalid_axi_s2_o, fabric_fpga_awvalid_axi_s2_o, fabric_fpga_arready_axi_s2_i, fabric_fpga_awready_axi_s2_i, fabric_fpga_bvalid_axi_s2_i, fabric_fpga_rlast_axi_s2_i, fabric_fpga_rvalid_axi_s2_i, fabric_fpga_wready_axi_s2_i, fabric_fpga_arready_axi_m1_o, fabric_fpga_awready_axi_m1_o, fabric_fpga_bvalid_axi_m1_o, fabric_fpga_rlast_axi_m1_o, fabric_fpga_rvalid_axi_m1_o, fabric_fpga_wready_axi_m1_o, fabric_fpga_arlock_axi_m1_i, fabric_fpga_arvalid_axi_m1_i, fabric_fpga_awlock_axi_m1_i, fabric_fpga_awvalid_axi_m1_i, fabric_fpga_bready_axi_m1_i
-, fabric_fpga_rready_axi_m1_i, fabric_fpga_wlast_axi_m1_i, fabric_fpga_wvalid_axi_m1_i, fabric_fpga_arready_axi_m2_o, fabric_fpga_awready_axi_m2_o, fabric_fpga_bvalid_axi_m2_o, fabric_fpga_rlast_axi_m2_o, fabric_fpga_rvalid_axi_m2_o, fabric_fpga_wready_axi_m2_o, fabric_fpga_arlock_axi_m2_i, fabric_fpga_arvalid_axi_m2_i, fabric_fpga_awlock_axi_m2_i, fabric_fpga_awvalid_axi_m2_i, fabric_fpga_bready_axi_m2_i, fabric_fpga_rready_axi_m2_i, fabric_fpga_wlast_axi_m2_i, fabric_fpga_wvalid_axi_m2_i, fabric_fpga_ddr0_arready_o, fabric_fpga_ddr0_awready_o, fabric_fpga_ddr0_bvalid_o, fabric_fpga_ddr0_rlast_o
-, fabric_fpga_ddr0_rvalid_o, fabric_fpga_ddr0_wready_o, fabric_fpga_ddr0_arlock_i, fabric_fpga_ddr0_arvalid_i, fabric_fpga_ddr0_awlock_i, fabric_fpga_ddr0_awvalid_i, fabric_fpga_ddr0_bready_i, fabric_fpga_ddr0_rready_i, fabric_fpga_ddr0_wlast_i, fabric_fpga_ddr0_wvalid_i, fabric_fpga_penable_apb_o, fabric_fpga_psel_apb_o, fabric_fpga_pwrite_apb_o, fabric_fpga_pready_apb_i, fabric_fpga_pslverr_apb_i, fabric_llpp0_arlock_s_o, fabric_llpp0_arvalid_s_o, fabric_llpp0_awlock_s_o, fabric_llpp0_awvalid_s_o, fabric_llpp0_bready_s_o, fabric_llpp0_rready_s_o
-, fabric_llpp0_wlast_s_o, fabric_llpp0_wvalid_s_o, fabric_llpp0_arready_s_i, fabric_llpp0_awready_s_i, fabric_llpp0_bvalid_s_i, fabric_llpp0_rlast_s_i, fabric_llpp0_rvalid_s_i, fabric_llpp0_wready_s_i, fabric_llpp1_arlock_s_o, fabric_llpp1_arvalid_s_o, fabric_llpp1_awlock_s_o, fabric_llpp1_awvalid_s_o, fabric_llpp1_bready_s_o, fabric_llpp1_rready_s_o, fabric_llpp1_wlast_s_o, fabric_llpp1_wvalid_s_o, fabric_llpp1_arready_s_i, fabric_llpp1_awready_s_i, fabric_llpp1_bvalid_s_i, fabric_llpp1_rlast_s_i, fabric_llpp1_rvalid_s_i
-, fabric_llpp1_wready_s_i, fabric_llpp2_arlock_s_o, fabric_llpp2_arvalid_s_o, fabric_llpp2_awlock_s_o, fabric_llpp2_awvalid_s_o, fabric_llpp2_bready_s_o, fabric_llpp2_rready_s_o, fabric_llpp2_wlast_s_o, fabric_llpp2_wvalid_s_o, fabric_llpp2_arready_s_i, fabric_llpp2_awready_s_i, fabric_llpp2_bvalid_s_i, fabric_llpp2_rlast_s_i, fabric_llpp2_rvalid_s_i, fabric_llpp2_wready_s_i, fabric_llpp3_arlock_s_o, fabric_llpp3_arvalid_s_o, fabric_llpp3_awlock_s_o, fabric_llpp3_awvalid_s_o, fabric_llpp3_bready_s_o, fabric_llpp3_rready_s_o
-, fabric_llpp3_wlast_s_o, fabric_llpp3_wvalid_s_o, fabric_llpp3_arready_s_i, fabric_llpp3_awready_s_i, fabric_llpp3_bvalid_s_i, fabric_llpp3_rlast_s_i, fabric_llpp3_rvalid_s_i, fabric_llpp3_wready_s_i, fabric_qos_ppready_o, fabric_qos_ppslverr_o, fabric_qos_pclk_i, fabric_qos_ppenable_i, fabric_qos_ppwrite_i, fabric_qos_presetn_i, fabric_qos_psel_i, fabric_tnd_hssl_flushin_o, fabric_tnd_hssl_trigin_o, fabric_tnd_fpga_apb_master_penable_o, fabric_tnd_fpga_apb_master_psel_o, fabric_tnd_fpga_apb_master_pwrite_o, fabric_tnd_fpga_atb_master_afvalid_o
-, fabric_tnd_fpga_atb_master_atready_o, fabric_tnd_fpga_atb_master_syncreq_o, fabric_tnd_hssl_apb_master_penable_o, fabric_tnd_hssl_apb_master_psel_o, fabric_tnd_hssl_apb_master_pwrite_o, fabric_tnd_hssl_atb_master_afready_o, fabric_tnd_hssl_atb_master_atvalid_o, fabric_tnd_trace_clk_traceoutportintf_o, fabric_tnd_trace_ctl_traceoutportintf_o, fabric_tnd_fpga_apb_master_pready_i, fabric_tnd_fpga_apb_master_pslverr_i, fabric_tnd_fpga_atb_master_afready_i, fabric_tnd_fpga_atb_master_atvalid_i, fabric_tnd_hssl_apb_master_pready_i, fabric_tnd_hssl_apb_master_pslverr_i, fabric_tnd_hssl_atb_master_afvalid_i, fabric_tnd_hssl_atb_master_atready_i, fabric_tnd_hssl_atb_master_syncreq_i, fabric_watchdog0_signal_0_o, fabric_watchdog0_signal_1_o, fabric_watchdog1_signal_0_o
-, fabric_watchdog1_signal_1_o, fabric_watchdog2_signal_0_o, fabric_watchdog2_signal_1_o, fabric_watchdog3_signal_0_o, fabric_watchdog3_signal_1_o, fabric_soc_mon_sensor_alarm_o, fabric_erom_fpga_cpu0_dbgen_i, fabric_erom_fpga_cpu0_hiden_i, fabric_erom_fpga_cpu0_hniden_i, fabric_erom_fpga_cpu0_niden_i, fabric_erom_fpga_cpu1_dbgen_i, fabric_erom_fpga_cpu1_hiden_i, fabric_erom_fpga_cpu1_hniden_i, fabric_erom_fpga_cpu1_niden_i, fabric_erom_fpga_cpu2_dbgen_i, fabric_erom_fpga_cpu2_hiden_i, fabric_erom_fpga_cpu2_hniden_i, fabric_erom_fpga_cpu2_niden_i, fabric_erom_fpga_cpu3_dbgen_i, fabric_erom_fpga_cpu3_hiden_i, fabric_erom_fpga_cpu3_hniden_i
-, fabric_erom_fpga_cpu3_niden_i, fabric_erom_fpga_cs_dbgen_i, fabric_erom_fpga_cs_niden_i, fabric_erom_fpga_cs_deviceen_i, fabric_erom_fpga_cs_rst_n_i, fabric_erom_fpga_debug_en_i, fabric_enable_TMR_i, fabric_lowskew_i, fabric_lowskew_o, fabric_fpga_nic_rstn_i, fabric_fpga_trigger_in_o, fabric_fpga_trigger_out_i, fabric_fpga_interrupt_in_i, fabric_fpga_events60_i, fabric_fpga_araddr_axi_s1_o, fabric_fpga_arburst_axi_s1_o, fabric_fpga_arcache_axi_s1_o, fabric_fpga_arid_axi_s1_o, fabric_fpga_arlen_axi_s1_o, fabric_fpga_arprot_axi_s1_o, fabric_fpga_arqos_axi_s1_o
-, fabric_fpga_arregion_axi_s1_o, fabric_fpga_arsize_axi_s1_o, fabric_fpga_awaddr_axi_s1_o, fabric_fpga_awburst_axi_s1_o, fabric_fpga_awcache_axi_s1_o, fabric_fpga_awid_axi_s1_o, fabric_fpga_awlen_axi_s1_o, fabric_fpga_awprot_axi_s1_o, fabric_fpga_awqos_axi_s1_o, fabric_fpga_awregion_axi_s1_o, fabric_fpga_awsize_axi_s1_o, fabric_fpga_wdata_axi_s1_o, fabric_fpga_wstrb_axi_s1_o, fabric_fpga_bid_axi_s1_i, fabric_fpga_bresp_axi_s1_i, fabric_fpga_rdata_axi_s1_i, fabric_fpga_rid_axi_s1_i, fabric_fpga_rresp_axi_s1_i, fabric_fpga_araddr_axi_s2_o, fabric_fpga_arburst_axi_s2_o, fabric_fpga_arcache_axi_s2_o
-, fabric_fpga_arid_axi_s2_o, fabric_fpga_arlen_axi_s2_o, fabric_fpga_arprot_axi_s2_o, fabric_fpga_arqos_axi_s2_o, fabric_fpga_arregion_axi_s2_o, fabric_fpga_arsize_axi_s2_o, fabric_fpga_awaddr_axi_s2_o, fabric_fpga_awburst_axi_s2_o, fabric_fpga_awcache_axi_s2_o, fabric_fpga_awid_axi_s2_o, fabric_fpga_awlen_axi_s2_o, fabric_fpga_awprot_axi_s2_o, fabric_fpga_awqos_axi_s2_o, fabric_fpga_awregion_axi_s2_o, fabric_fpga_awsize_axi_s2_o, fabric_fpga_wdata_axi_s2_o, fabric_fpga_wstrb_axi_s2_o, fabric_fpga_bid_axi_s2_i, fabric_fpga_bresp_axi_s2_i, fabric_fpga_rdata_axi_s2_i, fabric_fpga_rid_axi_s2_i
-, fabric_fpga_rresp_axi_s2_i, fabric_fpga_bid_axi_m1_o, fabric_fpga_bresp_axi_m1_o, fabric_fpga_dma_ack_m1_o, fabric_fpga_dma_finish_m1_o, fabric_fpga_rdata_axi_m1_o, fabric_fpga_rid_axi_m1_o, fabric_fpga_rresp_axi_m1_o, fabric_fpga_araddr_axi_m1_i, fabric_fpga_arburst_axi_m1_i, fabric_fpga_arcache_axi_m1_i, fabric_fpga_arid_axi_m1_i, fabric_fpga_arlen_axi_m1_i, fabric_fpga_arprot_axi_m1_i, fabric_fpga_arqos_axi_m1_i, fabric_fpga_arsize_axi_m1_i, fabric_fpga_awaddr_axi_m1_i, fabric_fpga_awburst_axi_m1_i, fabric_fpga_awcache_axi_m1_i, fabric_fpga_awid_axi_m1_i, fabric_fpga_awlen_axi_m1_i
-, fabric_fpga_awprot_axi_m1_i, fabric_fpga_awqos_axi_m1_i, fabric_fpga_awsize_axi_m1_i, fabric_fpga_dma_last_m1_i, fabric_fpga_dma_req_m1_i, fabric_fpga_dma_single_m1_i, fabric_fpga_wdata_axi_m1_i, fabric_fpga_wstrb_axi_m1_i, fabric_fpga_bid_axi_m2_o, fabric_fpga_bresp_axi_m2_o, fabric_fpga_dma_ack_m2_o, fabric_fpga_dma_finish_m2_o, fabric_fpga_rdata_axi_m2_o, fabric_fpga_rid_axi_m2_o, fabric_fpga_rresp_axi_m2_o, fabric_fpga_araddr_axi_m2_i, fabric_fpga_arburst_axi_m2_i, fabric_fpga_arcache_axi_m2_i, fabric_fpga_arid_axi_m2_i, fabric_fpga_arlen_axi_m2_i, fabric_fpga_arprot_axi_m2_i
-, fabric_fpga_arqos_axi_m2_i, fabric_fpga_arsize_axi_m2_i, fabric_fpga_awaddr_axi_m2_i, fabric_fpga_awburst_axi_m2_i, fabric_fpga_awcache_axi_m2_i, fabric_fpga_awid_axi_m2_i, fabric_fpga_awlen_axi_m2_i, fabric_fpga_awprot_axi_m2_i, fabric_fpga_awqos_axi_m2_i, fabric_fpga_awsize_axi_m2_i, fabric_fpga_dma_last_m2_i, fabric_fpga_dma_req_m2_i, fabric_fpga_dma_single_m2_i, fabric_fpga_wdata_axi_m2_i, fabric_fpga_wstrb_axi_m2_i, fabric_fpga_ddr0_bid_o, fabric_fpga_ddr0_bresp_o, fabric_fpga_ddr0_rdata_o, fabric_fpga_ddr0_rid_o, fabric_fpga_ddr0_rresp_o, fabric_fpga_ddr0_araddr_i
-, fabric_fpga_ddr0_arburst_i, fabric_fpga_ddr0_arcache_i, fabric_fpga_ddr0_arid_i, fabric_fpga_ddr0_arlen_i, fabric_fpga_ddr0_arprot_i, fabric_fpga_ddr0_arqos_i, fabric_fpga_ddr0_arsize_i, fabric_fpga_ddr0_awaddr_i, fabric_fpga_ddr0_awburst_i, fabric_fpga_ddr0_awcache_i, fabric_fpga_ddr0_awid_i, fabric_fpga_ddr0_awlen_i, fabric_fpga_ddr0_awprot_i, fabric_fpga_ddr0_awqos_i, fabric_fpga_ddr0_awsize_i, fabric_fpga_ddr0_wdata_i, fabric_fpga_ddr0_wstrb_i, fabric_fpga_paddr_apb_o, fabric_fpga_pwdata_apb_o, fabric_fpga_prdata_apb_i, fabric_llpp0_araddr_s_o
-, fabric_llpp0_arburst_s_o, fabric_llpp0_arcache_s_o, fabric_llpp0_arid_s_o, fabric_llpp0_arlen_s_o, fabric_llpp0_arprot_s_o, fabric_llpp0_arqos_s_o, fabric_llpp0_arsize_s_o, fabric_llpp0_awaddr_s_o, fabric_llpp0_awburst_s_o, fabric_llpp0_awcache_s_o, fabric_llpp0_awid_s_o, fabric_llpp0_awlen_s_o, fabric_llpp0_awprot_s_o, fabric_llpp0_awqos_s_o, fabric_llpp0_awsize_s_o, fabric_llpp0_wdata_s_o, fabric_llpp0_wstrb_s_o, fabric_llpp0_bid_s_i, fabric_llpp0_bresp_s_i, fabric_llpp0_rdata_s_i, fabric_llpp0_rid_s_i
-, fabric_llpp0_rresp_s_i, fabric_llpp1_araddr_s_o, fabric_llpp1_arburst_s_o, fabric_llpp1_arcache_s_o, fabric_llpp1_arid_s_o, fabric_llpp1_arlen_s_o, fabric_llpp1_arprot_s_o, fabric_llpp1_arqos_s1_o, fabric_llpp1_arsize_s_o, fabric_llpp1_awaddr_s_o, fabric_llpp1_awburst_s_o, fabric_llpp1_awcache_s_o, fabric_llpp1_awid_s_o, fabric_llpp1_awlen_s_o, fabric_llpp1_awprot_s_o, fabric_llpp1_awqos_s_o, fabric_llpp1_awsize_s_o, fabric_llpp1_wdata_s_o, fabric_llpp1_wstrb_s_o, fabric_llpp1_bid_s_i, fabric_llpp1_bresp_s_i
-, fabric_llpp1_rdata_s_i, fabric_llpp1_rid_s_i, fabric_llpp1_rresp_s_i, fabric_llpp2_araddr_s_o, fabric_llpp2_arburst_s_o, fabric_llpp2_arcache_s_o, fabric_llpp2_arid_s_o, fabric_llpp2_arlen_s_o, fabric_llpp2_arprot_s_o, fabric_llpp2_arqos_s_o, fabric_llpp2_arsize_s_o, fabric_llpp2_awaddr_s_o, fabric_llpp2_awburst_s_o, fabric_llpp2_awcache_s_o, fabric_llpp2_awid_s_o, fabric_llpp2_awlen_s_o, fabric_llpp2_awprot_s_o, fabric_llpp2_awqos_s_o, fabric_llpp2_awsize_s_o, fabric_llpp2_wdata_s_o, fabric_llpp2_wstrb_s_o
-, fabric_llpp2_bid_s_i, fabric_llpp2_bresp_s_i, fabric_llpp2_rdata_s_i, fabric_llpp2_rid_s_i, fabric_llpp2_rresp_s_i, fabric_llpp3_araddr_s_o, fabric_llpp3_arburst_s_o, fabric_llpp3_arcache_s_o, fabric_llpp3_arid_s_o, fabric_llpp3_arlen_s_o, fabric_llpp3_arprot_s_o, fabric_llpp3_arqos_s_o, fabric_llpp3_arsize_s_o, fabric_llpp3_awaddr_s_o, fabric_llpp3_awburst_s_o, fabric_llpp3_awcache_s_o, fabric_llpp3_awid_s_o, fabric_llpp3_awlen_s_o, fabric_llpp3_awprot_s_o, fabric_llpp3_awqos_s_o, fabric_llpp3_awsize_s_o
-, fabric_llpp3_wdata_s_o, fabric_llpp3_wstrb_s_o, fabric_llpp3_bid_s_i, fabric_llpp3_bresp_s_i, fabric_llpp3_rdata_s_i, fabric_llpp3_rid_s_i, fabric_llpp3_rresp_s_i, fabric_qos_pprdata_o, fabric_qos_ppaddr_i, fabric_qos_ppwdata_i, fabric_tnd_fpga_apb_master_paddr_o, fabric_tnd_fpga_apb_master_pwdata_o, fabric_tnd_hssl_apb_master_paddr_o, fabric_tnd_hssl_apb_master_pwdata_o, fabric_tnd_hssl_atb_master_atbytes_o, fabric_tnd_hssl_atb_master_atdata_o, fabric_tnd_hssl_atb_master_atid_o, fabric_tnd_trace_data_traceoutportintf_o, fabric_tsvalue_tsgen_fpga_o, fabric_tnd_fpga_apb_master_prdata_i, fabric_tnd_fpga_atb_master_atbytes_i
-, fabric_tnd_fpga_atb_master_atdata_i, fabric_tnd_fpga_atb_master_atid_i, fabric_tnd_hssl_apb_master_prdata_i, fabric_tst_pll_lock_o);
-    input [2:0] fabric_enable_TMR_i;
-    input fabric_erom_fpga_cpu0_dbgen_i;
-    input fabric_erom_fpga_cpu0_hiden_i;
-    input fabric_erom_fpga_cpu0_hniden_i;
-    input fabric_erom_fpga_cpu0_niden_i;
-    input fabric_erom_fpga_cpu1_dbgen_i;
-    input fabric_erom_fpga_cpu1_hiden_i;
-    input fabric_erom_fpga_cpu1_hniden_i;
-    input fabric_erom_fpga_cpu1_niden_i;
-    input fabric_erom_fpga_cpu2_dbgen_i;
-    input fabric_erom_fpga_cpu2_hiden_i;
-    input fabric_erom_fpga_cpu2_hniden_i;
-    input fabric_erom_fpga_cpu2_niden_i;
-    input fabric_erom_fpga_cpu3_dbgen_i;
-    input fabric_erom_fpga_cpu3_hiden_i;
-    input fabric_erom_fpga_cpu3_hniden_i;
-    input fabric_erom_fpga_cpu3_niden_i;
-    input fabric_erom_fpga_cs_dbgen_i;
-    input fabric_erom_fpga_cs_deviceen_i;
-    input fabric_erom_fpga_cs_niden_i;
-    input fabric_erom_fpga_cs_rst_n_i;
-    input fabric_erom_fpga_debug_en_i;
-    input [39:0] fabric_fpga_araddr_axi_m1_i;
-    input [39:0] fabric_fpga_araddr_axi_m2_i;
-    output [39:0] fabric_fpga_araddr_axi_s1_o;
-    output [39:0] fabric_fpga_araddr_axi_s2_o;
-    input [1:0] fabric_fpga_arburst_axi_m1_i;
-    input [1:0] fabric_fpga_arburst_axi_m2_i;
-    output [1:0] fabric_fpga_arburst_axi_s1_o;
-    output [1:0] fabric_fpga_arburst_axi_s2_o;
-    input [3:0] fabric_fpga_arcache_axi_m1_i;
-    input [3:0] fabric_fpga_arcache_axi_m2_i;
-    output [3:0] fabric_fpga_arcache_axi_s1_o;
-    output [3:0] fabric_fpga_arcache_axi_s2_o;
-    input [4:0] fabric_fpga_arid_axi_m1_i;
-    input [4:0] fabric_fpga_arid_axi_m2_i;
-    output [11:0] fabric_fpga_arid_axi_s1_o;
-    output [11:0] fabric_fpga_arid_axi_s2_o;
-    input [7:0] fabric_fpga_arlen_axi_m1_i;
-    input [7:0] fabric_fpga_arlen_axi_m2_i;
-    output [7:0] fabric_fpga_arlen_axi_s1_o;
-    output [7:0] fabric_fpga_arlen_axi_s2_o;
-    input fabric_fpga_arlock_axi_m1_i;
-    input fabric_fpga_arlock_axi_m2_i;
-    output fabric_fpga_arlock_axi_s1_o;
-    output fabric_fpga_arlock_axi_s2_o;
-    input [2:0] fabric_fpga_arprot_axi_m1_i;
-    input [2:0] fabric_fpga_arprot_axi_m2_i;
-    output [2:0] fabric_fpga_arprot_axi_s1_o;
-    output [2:0] fabric_fpga_arprot_axi_s2_o;
-    input [3:0] fabric_fpga_arqos_axi_m1_i;
-    input [3:0] fabric_fpga_arqos_axi_m2_i;
-    output [3:0] fabric_fpga_arqos_axi_s1_o;
-    output [3:0] fabric_fpga_arqos_axi_s2_o;
-    output fabric_fpga_arready_axi_m1_o;
-    output fabric_fpga_arready_axi_m2_o;
-    input fabric_fpga_arready_axi_s1_i;
-    input fabric_fpga_arready_axi_s2_i;
-    output [3:0] fabric_fpga_arregion_axi_s1_o;
-    output [3:0] fabric_fpga_arregion_axi_s2_o;
-    input [2:0] fabric_fpga_arsize_axi_m1_i;
-    input [2:0] fabric_fpga_arsize_axi_m2_i;
-    output [2:0] fabric_fpga_arsize_axi_s1_o;
-    output [2:0] fabric_fpga_arsize_axi_s2_o;
-    input fabric_fpga_arvalid_axi_m1_i;
-    input fabric_fpga_arvalid_axi_m2_i;
-    output fabric_fpga_arvalid_axi_s1_o;
-    output fabric_fpga_arvalid_axi_s2_o;
-    input [39:0] fabric_fpga_awaddr_axi_m1_i;
-    input [39:0] fabric_fpga_awaddr_axi_m2_i;
-    output [39:0] fabric_fpga_awaddr_axi_s1_o;
-    output [39:0] fabric_fpga_awaddr_axi_s2_o;
-    input [1:0] fabric_fpga_awburst_axi_m1_i;
-    input [1:0] fabric_fpga_awburst_axi_m2_i;
-    output [1:0] fabric_fpga_awburst_axi_s1_o;
-    output [1:0] fabric_fpga_awburst_axi_s2_o;
-    input [3:0] fabric_fpga_awcache_axi_m1_i;
-    input [3:0] fabric_fpga_awcache_axi_m2_i;
-    output [3:0] fabric_fpga_awcache_axi_s1_o;
-    output [3:0] fabric_fpga_awcache_axi_s2_o;
-    input [4:0] fabric_fpga_awid_axi_m1_i;
-    input [4:0] fabric_fpga_awid_axi_m2_i;
-    output [11:0] fabric_fpga_awid_axi_s1_o;
-    output [11:0] fabric_fpga_awid_axi_s2_o;
-    input [7:0] fabric_fpga_awlen_axi_m1_i;
-    input [7:0] fabric_fpga_awlen_axi_m2_i;
-    output [7:0] fabric_fpga_awlen_axi_s1_o;
-    output [7:0] fabric_fpga_awlen_axi_s2_o;
-    input fabric_fpga_awlock_axi_m1_i;
-    input fabric_fpga_awlock_axi_m2_i;
-    output fabric_fpga_awlock_axi_s1_o;
-    output fabric_fpga_awlock_axi_s2_o;
-    input [2:0] fabric_fpga_awprot_axi_m1_i;
-    input [2:0] fabric_fpga_awprot_axi_m2_i;
-    output [2:0] fabric_fpga_awprot_axi_s1_o;
-    output [2:0] fabric_fpga_awprot_axi_s2_o;
-    input [3:0] fabric_fpga_awqos_axi_m1_i;
-    input [3:0] fabric_fpga_awqos_axi_m2_i;
-    output [3:0] fabric_fpga_awqos_axi_s1_o;
-    output [3:0] fabric_fpga_awqos_axi_s2_o;
-    output fabric_fpga_awready_axi_m1_o;
-    output fabric_fpga_awready_axi_m2_o;
-    input fabric_fpga_awready_axi_s1_i;
-    input fabric_fpga_awready_axi_s2_i;
-    output [3:0] fabric_fpga_awregion_axi_s1_o;
-    output [3:0] fabric_fpga_awregion_axi_s2_o;
-    input [2:0] fabric_fpga_awsize_axi_m1_i;
-    input [2:0] fabric_fpga_awsize_axi_m2_i;
-    output [2:0] fabric_fpga_awsize_axi_s1_o;
-    output [2:0] fabric_fpga_awsize_axi_s2_o;
-    input fabric_fpga_awvalid_axi_m1_i;
-    input fabric_fpga_awvalid_axi_m2_i;
-    output fabric_fpga_awvalid_axi_s1_o;
-    output fabric_fpga_awvalid_axi_s2_o;
-    output [4:0] fabric_fpga_bid_axi_m1_o;
-    output [4:0] fabric_fpga_bid_axi_m2_o;
-    input [11:0] fabric_fpga_bid_axi_s1_i;
-    input [11:0] fabric_fpga_bid_axi_s2_i;
-    input fabric_fpga_bready_axi_m1_i;
-    input fabric_fpga_bready_axi_m2_i;
-    output fabric_fpga_bready_axi_s1_o;
-    output fabric_fpga_bready_axi_s2_o;
-    output [1:0] fabric_fpga_bresp_axi_m1_o;
-    output [1:0] fabric_fpga_bresp_axi_m2_o;
-    input [1:0] fabric_fpga_bresp_axi_s1_i;
-    input [1:0] fabric_fpga_bresp_axi_s2_i;
-    output fabric_fpga_bvalid_axi_m1_o;
-    output fabric_fpga_bvalid_axi_m2_o;
-    input fabric_fpga_bvalid_axi_s1_i;
-    input fabric_fpga_bvalid_axi_s2_i;
-    input [39:0] fabric_fpga_ddr0_araddr_i;
-    input [1:0] fabric_fpga_ddr0_arburst_i;
-    input [3:0] fabric_fpga_ddr0_arcache_i;
-    input [4:0] fabric_fpga_ddr0_arid_i;
-    input [7:0] fabric_fpga_ddr0_arlen_i;
-    input fabric_fpga_ddr0_arlock_i;
-    input [2:0] fabric_fpga_ddr0_arprot_i;
-    input [3:0] fabric_fpga_ddr0_arqos_i;
-    output fabric_fpga_ddr0_arready_o;
-    input [2:0] fabric_fpga_ddr0_arsize_i;
-    input fabric_fpga_ddr0_arvalid_i;
-    input [39:0] fabric_fpga_ddr0_awaddr_i;
-    input [1:0] fabric_fpga_ddr0_awburst_i;
-    input [3:0] fabric_fpga_ddr0_awcache_i;
-    input [4:0] fabric_fpga_ddr0_awid_i;
-    input [7:0] fabric_fpga_ddr0_awlen_i;
-    input fabric_fpga_ddr0_awlock_i;
-    input [2:0] fabric_fpga_ddr0_awprot_i;
-    input [3:0] fabric_fpga_ddr0_awqos_i;
-    output fabric_fpga_ddr0_awready_o;
-    input [2:0] fabric_fpga_ddr0_awsize_i;
-    input fabric_fpga_ddr0_awvalid_i;
-    output [4:0] fabric_fpga_ddr0_bid_o;
-    input fabric_fpga_ddr0_bready_i;
-    output [1:0] fabric_fpga_ddr0_bresp_o;
-    output fabric_fpga_ddr0_bvalid_o;
-    output [127:0] fabric_fpga_ddr0_rdata_o;
-    output [4:0] fabric_fpga_ddr0_rid_o;
-    output fabric_fpga_ddr0_rlast_o;
-    input fabric_fpga_ddr0_rready_i;
-    output [1:0] fabric_fpga_ddr0_rresp_o;
-    output fabric_fpga_ddr0_rvalid_o;
-    input [127:0] fabric_fpga_ddr0_wdata_i;
-    input fabric_fpga_ddr0_wlast_i;
-    output fabric_fpga_ddr0_wready_o;
-    input [15:0] fabric_fpga_ddr0_wstrb_i;
-    input fabric_fpga_ddr0_wvalid_i;
-    output [5:0] fabric_fpga_dma_ack_m1_o;
-    output [5:0] fabric_fpga_dma_ack_m2_o;
-    output [5:0] fabric_fpga_dma_finish_m1_o;
-    output [5:0] fabric_fpga_dma_finish_m2_o;
-    input [5:0] fabric_fpga_dma_last_m1_i;
-    input [5:0] fabric_fpga_dma_last_m2_i;
-    input [5:0] fabric_fpga_dma_req_m1_i;
-    input [5:0] fabric_fpga_dma_req_m2_i;
-    input [5:0] fabric_fpga_dma_single_m1_i;
-    input [5:0] fabric_fpga_dma_single_m2_i;
-    input [59:0] fabric_fpga_events60_i;
-    input [119:0] fabric_fpga_interrupt_in_i;
-    input [9:0] fabric_fpga_nic_rstn_i;
-    output [31:0] fabric_fpga_paddr_apb_o;
-    output fabric_fpga_penable_apb_o;
-    input fabric_fpga_pmrstn_i;
-    input [31:0] fabric_fpga_prdata_apb_i;
-    input fabric_fpga_pready_apb_i;
-    output fabric_fpga_psel_apb_o;
-    input fabric_fpga_pslverr_apb_i;
-    output [31:0] fabric_fpga_pwdata_apb_o;
-    output fabric_fpga_pwrite_apb_o;
-    output [127:0] fabric_fpga_rdata_axi_m1_o;
-    output [127:0] fabric_fpga_rdata_axi_m2_o;
-    input [127:0] fabric_fpga_rdata_axi_s1_i;
-    input [127:0] fabric_fpga_rdata_axi_s2_i;
-    output [4:0] fabric_fpga_rid_axi_m1_o;
-    output [4:0] fabric_fpga_rid_axi_m2_o;
-    input [11:0] fabric_fpga_rid_axi_s1_i;
-    input [11:0] fabric_fpga_rid_axi_s2_i;
-    output fabric_fpga_rlast_axi_m1_o;
-    output fabric_fpga_rlast_axi_m2_o;
-    input fabric_fpga_rlast_axi_s1_i;
-    input fabric_fpga_rlast_axi_s2_i;
-    input fabric_fpga_rready_axi_m1_i;
-    input fabric_fpga_rready_axi_m2_i;
-    output fabric_fpga_rready_axi_s1_o;
-    output fabric_fpga_rready_axi_s2_o;
-    output [1:0] fabric_fpga_rresp_axi_m1_o;
-    output [1:0] fabric_fpga_rresp_axi_m2_o;
-    input [1:0] fabric_fpga_rresp_axi_s1_i;
-    input [1:0] fabric_fpga_rresp_axi_s2_i;
-    output fabric_fpga_rvalid_axi_m1_o;
-    output fabric_fpga_rvalid_axi_m2_o;
-    input fabric_fpga_rvalid_axi_s1_i;
-    input fabric_fpga_rvalid_axi_s2_i;
-    input fabric_fpga_sysrstn_i;
-    output [7:0] fabric_fpga_trigger_in_o;
-    input [7:0] fabric_fpga_trigger_out_i;
-    input [127:0] fabric_fpga_wdata_axi_m1_i;
-    input [127:0] fabric_fpga_wdata_axi_m2_i;
-    output [127:0] fabric_fpga_wdata_axi_s1_o;
-    output [127:0] fabric_fpga_wdata_axi_s2_o;
-    input fabric_fpga_wlast_axi_m1_i;
-    input fabric_fpga_wlast_axi_m2_i;
-    output fabric_fpga_wlast_axi_s1_o;
-    output fabric_fpga_wlast_axi_s2_o;
-    output fabric_fpga_wready_axi_m1_o;
-    output fabric_fpga_wready_axi_m2_o;
-    input fabric_fpga_wready_axi_s1_i;
-    input fabric_fpga_wready_axi_s2_i;
-    input [15:0] fabric_fpga_wstrb_axi_m1_i;
-    input [15:0] fabric_fpga_wstrb_axi_m2_i;
-    output [15:0] fabric_fpga_wstrb_axi_s1_o;
-    output [15:0] fabric_fpga_wstrb_axi_s2_o;
-    input fabric_fpga_wvalid_axi_m1_i;
-    input fabric_fpga_wvalid_axi_m2_i;
-    output fabric_fpga_wvalid_axi_s1_o;
-    output fabric_fpga_wvalid_axi_s2_o;
-    output [31:0] fabric_llpp0_araddr_s_o;
-    output [1:0] fabric_llpp0_arburst_s_o;
-    output [3:0] fabric_llpp0_arcache_s_o;
-    output [11:0] fabric_llpp0_arid_s_o;
-    output [7:0] fabric_llpp0_arlen_s_o;
-    output fabric_llpp0_arlock_s_o;
-    output [2:0] fabric_llpp0_arprot_s_o;
-    output [3:0] fabric_llpp0_arqos_s_o;
-    input fabric_llpp0_arready_s_i;
-    output [2:0] fabric_llpp0_arsize_s_o;
-    output fabric_llpp0_arvalid_s_o;
-    output [31:0] fabric_llpp0_awaddr_s_o;
-    output [1:0] fabric_llpp0_awburst_s_o;
-    output [3:0] fabric_llpp0_awcache_s_o;
-    output [11:0] fabric_llpp0_awid_s_o;
-    output [7:0] fabric_llpp0_awlen_s_o;
-    output fabric_llpp0_awlock_s_o;
-    output [2:0] fabric_llpp0_awprot_s_o;
-    output [3:0] fabric_llpp0_awqos_s_o;
-    input fabric_llpp0_awready_s_i;
-    output [2:0] fabric_llpp0_awsize_s_o;
-    output fabric_llpp0_awvalid_s_o;
-    input [11:0] fabric_llpp0_bid_s_i;
-    output fabric_llpp0_bready_s_o;
-    input [1:0] fabric_llpp0_bresp_s_i;
-    input fabric_llpp0_bvalid_s_i;
-    input [31:0] fabric_llpp0_rdata_s_i;
-    input [11:0] fabric_llpp0_rid_s_i;
-    input fabric_llpp0_rlast_s_i;
-    output fabric_llpp0_rready_s_o;
-    input [1:0] fabric_llpp0_rresp_s_i;
-    input fabric_llpp0_rvalid_s_i;
-    output [31:0] fabric_llpp0_wdata_s_o;
-    output fabric_llpp0_wlast_s_o;
-    input fabric_llpp0_wready_s_i;
-    output [3:0] fabric_llpp0_wstrb_s_o;
-    output fabric_llpp0_wvalid_s_o;
-    output [31:0] fabric_llpp1_araddr_s_o;
-    output [1:0] fabric_llpp1_arburst_s_o;
-    output [3:0] fabric_llpp1_arcache_s_o;
-    output [11:0] fabric_llpp1_arid_s_o;
-    output [7:0] fabric_llpp1_arlen_s_o;
-    output fabric_llpp1_arlock_s_o;
-    output [2:0] fabric_llpp1_arprot_s_o;
-    output [3:0] fabric_llpp1_arqos_s1_o;
-    input fabric_llpp1_arready_s_i;
-    output [2:0] fabric_llpp1_arsize_s_o;
-    output fabric_llpp1_arvalid_s_o;
-    output [31:0] fabric_llpp1_awaddr_s_o;
-    output [1:0] fabric_llpp1_awburst_s_o;
-    output [3:0] fabric_llpp1_awcache_s_o;
-    output [11:0] fabric_llpp1_awid_s_o;
-    output [7:0] fabric_llpp1_awlen_s_o;
-    output fabric_llpp1_awlock_s_o;
-    output [2:0] fabric_llpp1_awprot_s_o;
-    output [3:0] fabric_llpp1_awqos_s_o;
-    input fabric_llpp1_awready_s_i;
-    output [2:0] fabric_llpp1_awsize_s_o;
-    output fabric_llpp1_awvalid_s_o;
-    input [11:0] fabric_llpp1_bid_s_i;
-    output fabric_llpp1_bready_s_o;
-    input [1:0] fabric_llpp1_bresp_s_i;
-    input fabric_llpp1_bvalid_s_i;
-    input [31:0] fabric_llpp1_rdata_s_i;
-    input [11:0] fabric_llpp1_rid_s_i;
-    input fabric_llpp1_rlast_s_i;
-    output fabric_llpp1_rready_s_o;
-    input [1:0] fabric_llpp1_rresp_s_i;
-    input fabric_llpp1_rvalid_s_i;
-    output [31:0] fabric_llpp1_wdata_s_o;
-    output fabric_llpp1_wlast_s_o;
-    input fabric_llpp1_wready_s_i;
-    output [3:0] fabric_llpp1_wstrb_s_o;
-    output fabric_llpp1_wvalid_s_o;
-    output [31:0] fabric_llpp2_araddr_s_o;
-    output [1:0] fabric_llpp2_arburst_s_o;
-    output [3:0] fabric_llpp2_arcache_s_o;
-    output [11:0] fabric_llpp2_arid_s_o;
-    output [7:0] fabric_llpp2_arlen_s_o;
-    output fabric_llpp2_arlock_s_o;
-    output [2:0] fabric_llpp2_arprot_s_o;
-    output [3:0] fabric_llpp2_arqos_s_o;
-    input fabric_llpp2_arready_s_i;
-    output [2:0] fabric_llpp2_arsize_s_o;
-    output fabric_llpp2_arvalid_s_o;
-    output [31:0] fabric_llpp2_awaddr_s_o;
-    output [1:0] fabric_llpp2_awburst_s_o;
-    output [3:0] fabric_llpp2_awcache_s_o;
-    output [11:0] fabric_llpp2_awid_s_o;
-    output [7:0] fabric_llpp2_awlen_s_o;
-    output fabric_llpp2_awlock_s_o;
-    output [2:0] fabric_llpp2_awprot_s_o;
-    output [3:0] fabric_llpp2_awqos_s_o;
-    input fabric_llpp2_awready_s_i;
-    output [2:0] fabric_llpp2_awsize_s_o;
-    output fabric_llpp2_awvalid_s_o;
-    input [11:0] fabric_llpp2_bid_s_i;
-    output fabric_llpp2_bready_s_o;
-    input [1:0] fabric_llpp2_bresp_s_i;
-    input fabric_llpp2_bvalid_s_i;
-    input [31:0] fabric_llpp2_rdata_s_i;
-    input [11:0] fabric_llpp2_rid_s_i;
-    input fabric_llpp2_rlast_s_i;
-    output fabric_llpp2_rready_s_o;
-    input [1:0] fabric_llpp2_rresp_s_i;
-    input fabric_llpp2_rvalid_s_i;
-    output [31:0] fabric_llpp2_wdata_s_o;
-    output fabric_llpp2_wlast_s_o;
-    input fabric_llpp2_wready_s_i;
-    output [3:0] fabric_llpp2_wstrb_s_o;
-    output fabric_llpp2_wvalid_s_o;
-    output [31:0] fabric_llpp3_araddr_s_o;
-    output [1:0] fabric_llpp3_arburst_s_o;
-    output [3:0] fabric_llpp3_arcache_s_o;
-    output [11:0] fabric_llpp3_arid_s_o;
-    output [7:0] fabric_llpp3_arlen_s_o;
-    output fabric_llpp3_arlock_s_o;
-    output [2:0] fabric_llpp3_arprot_s_o;
-    output [3:0] fabric_llpp3_arqos_s_o;
-    input fabric_llpp3_arready_s_i;
-    output [2:0] fabric_llpp3_arsize_s_o;
-    output fabric_llpp3_arvalid_s_o;
-    output [31:0] fabric_llpp3_awaddr_s_o;
-    output [1:0] fabric_llpp3_awburst_s_o;
-    output [3:0] fabric_llpp3_awcache_s_o;
-    output [11:0] fabric_llpp3_awid_s_o;
-    output [7:0] fabric_llpp3_awlen_s_o;
-    output fabric_llpp3_awlock_s_o;
-    output [2:0] fabric_llpp3_awprot_s_o;
-    output [3:0] fabric_llpp3_awqos_s_o;
-    input fabric_llpp3_awready_s_i;
-    output [2:0] fabric_llpp3_awsize_s_o;
-    output fabric_llpp3_awvalid_s_o;
-    input [11:0] fabric_llpp3_bid_s_i;
-    output fabric_llpp3_bready_s_o;
-    input [1:0] fabric_llpp3_bresp_s_i;
-    input fabric_llpp3_bvalid_s_i;
-    input [31:0] fabric_llpp3_rdata_s_i;
-    input [11:0] fabric_llpp3_rid_s_i;
-    input fabric_llpp3_rlast_s_i;
-    output fabric_llpp3_rready_s_o;
-    input [1:0] fabric_llpp3_rresp_s_i;
-    input fabric_llpp3_rvalid_s_i;
-    output [31:0] fabric_llpp3_wdata_s_o;
-    output fabric_llpp3_wlast_s_o;
-    input fabric_llpp3_wready_s_i;
-    output [3:0] fabric_llpp3_wstrb_s_o;
-    output fabric_llpp3_wvalid_s_o;
-    input [9:0] fabric_lowskew_i;
-    output [1:0] fabric_lowskew_o;
-    input fabric_qos_pclk_i;
-    input [31:0] fabric_qos_ppaddr_i;
-    input fabric_qos_ppenable_i;
-    output [31:0] fabric_qos_pprdata_o;
-    output fabric_qos_ppready_o;
-    output fabric_qos_ppslverr_o;
-    input [31:0] fabric_qos_ppwdata_i;
-    input fabric_qos_ppwrite_i;
-    input fabric_qos_presetn_i;
-    input fabric_qos_psel_i;
-    output fabric_soc_mon_sensor_alarm_o;
-    input fabric_sysc_hold_on_debug_i;
-    output [31:0] fabric_tnd_fpga_apb_master_paddr_o;
-    output fabric_tnd_fpga_apb_master_penable_o;
-    input [31:0] fabric_tnd_fpga_apb_master_prdata_i;
-    input fabric_tnd_fpga_apb_master_pready_i;
-    output fabric_tnd_fpga_apb_master_psel_o;
-    input fabric_tnd_fpga_apb_master_pslverr_i;
-    output [31:0] fabric_tnd_fpga_apb_master_pwdata_o;
-    output fabric_tnd_fpga_apb_master_pwrite_o;
-    input fabric_tnd_fpga_atb_master_afready_i;
-    output fabric_tnd_fpga_atb_master_afvalid_o;
-    input [3:0] fabric_tnd_fpga_atb_master_atbytes_i;
-    input [127:0] fabric_tnd_fpga_atb_master_atdata_i;
-    input [6:0] fabric_tnd_fpga_atb_master_atid_i;
-    output fabric_tnd_fpga_atb_master_atready_o;
-    input fabric_tnd_fpga_atb_master_atvalid_i;
-    output fabric_tnd_fpga_atb_master_syncreq_o;
-    output [31:0] fabric_tnd_hssl_apb_master_paddr_o;
-    output fabric_tnd_hssl_apb_master_penable_o;
-    input [31:0] fabric_tnd_hssl_apb_master_prdata_i;
-    input fabric_tnd_hssl_apb_master_pready_i;
-    output fabric_tnd_hssl_apb_master_psel_o;
-    input fabric_tnd_hssl_apb_master_pslverr_i;
-    output [31:0] fabric_tnd_hssl_apb_master_pwdata_o;
-    output fabric_tnd_hssl_apb_master_pwrite_o;
-    output fabric_tnd_hssl_atb_master_afready_o;
-    input fabric_tnd_hssl_atb_master_afvalid_i;
-    output [3:0] fabric_tnd_hssl_atb_master_atbytes_o;
-    output [127:0] fabric_tnd_hssl_atb_master_atdata_o;
-    output [6:0] fabric_tnd_hssl_atb_master_atid_o;
-    input fabric_tnd_hssl_atb_master_atready_i;
-    output fabric_tnd_hssl_atb_master_atvalid_o;
-    input fabric_tnd_hssl_atb_master_syncreq_i;
-    output fabric_tnd_hssl_flushin_o;
-    output fabric_tnd_hssl_trigin_o;
-    output fabric_tnd_trace_clk_traceoutportintf_o;
-    output fabric_tnd_trace_ctl_traceoutportintf_o;
-    output [31:0] fabric_tnd_trace_data_traceoutportintf_o;
-    output [6:0] fabric_tst_pll_lock_o;
-    output [63:0] fabric_tsvalue_tsgen_fpga_o;
-    output fabric_watchdog0_signal_0_o;
-    output fabric_watchdog0_signal_1_o;
-    output fabric_watchdog1_signal_0_o;
-    output fabric_watchdog1_signal_1_o;
-    output fabric_watchdog2_signal_0_o;
-    output fabric_watchdog2_signal_1_o;
-    output fabric_watchdog3_signal_0_o;
-    output fabric_watchdog3_signal_1_o;
-    parameter ahb_config = 0;
-    parameter bsm_config = 0;
-endmodule
-
-(* blackbox *)
-module NX_SOC_INTERFACE_WRAP(fabric_fpga_pmrstn_i, fabric_fpga_sysrstn_i, fabric_sysc_hold_on_debug_i, fabric_fpga_arlock_axi_s1_o, fabric_fpga_arvalid_axi_s1_o, fabric_fpga_awlock_axi_s1_o, fabric_fpga_bready_axi_s1_o, fabric_fpga_rready_axi_s1_o, fabric_fpga_wlast_axi_s1_o, fabric_fpga_wvalid_axi_s1_o, fabric_fpga_awvalid_axi_s1_o, fabric_fpga_arready_axi_s1_i, fabric_fpga_awready_axi_s1_i, fabric_fpga_bvalid_axi_s1_i, fabric_fpga_rlast_axi_s1_i, fabric_fpga_rvalid_axi_s1_i, fabric_fpga_wready_axi_s1_i, fabric_fpga_arlock_axi_s2_o, fabric_fpga_arvalid_axi_s2_o, fabric_fpga_awlock_axi_s2_o, fabric_fpga_bready_axi_s2_o
-, fabric_fpga_rready_axi_s2_o, fabric_fpga_wlast_axi_s2_o, fabric_fpga_wvalid_axi_s2_o, fabric_fpga_awvalid_axi_s2_o, fabric_fpga_arready_axi_s2_i, fabric_fpga_awready_axi_s2_i, fabric_fpga_bvalid_axi_s2_i, fabric_fpga_rlast_axi_s2_i, fabric_fpga_rvalid_axi_s2_i, fabric_fpga_wready_axi_s2_i, fabric_fpga_arready_axi_m1_o, fabric_fpga_awready_axi_m1_o, fabric_fpga_bvalid_axi_m1_o, fabric_fpga_rlast_axi_m1_o, fabric_fpga_rvalid_axi_m1_o, fabric_fpga_wready_axi_m1_o, fabric_fpga_arlock_axi_m1_i, fabric_fpga_arvalid_axi_m1_i, fabric_fpga_awlock_axi_m1_i, fabric_fpga_awvalid_axi_m1_i, fabric_fpga_bready_axi_m1_i
-, fabric_fpga_rready_axi_m1_i, fabric_fpga_wlast_axi_m1_i, fabric_fpga_wvalid_axi_m1_i, fabric_fpga_arready_axi_m2_o, fabric_fpga_awready_axi_m2_o, fabric_fpga_bvalid_axi_m2_o, fabric_fpga_rlast_axi_m2_o, fabric_fpga_rvalid_axi_m2_o, fabric_fpga_wready_axi_m2_o, fabric_fpga_arlock_axi_m2_i, fabric_fpga_arvalid_axi_m2_i, fabric_fpga_awlock_axi_m2_i, fabric_fpga_awvalid_axi_m2_i, fabric_fpga_bready_axi_m2_i, fabric_fpga_rready_axi_m2_i, fabric_fpga_wlast_axi_m2_i, fabric_fpga_wvalid_axi_m2_i, fabric_fpga_ddr0_arready_o, fabric_fpga_ddr0_awready_o, fabric_fpga_ddr0_bvalid_o, fabric_fpga_ddr0_rlast_o
-, fabric_fpga_ddr0_rvalid_o, fabric_fpga_ddr0_wready_o, fabric_fpga_ddr0_arlock_i, fabric_fpga_ddr0_arvalid_i, fabric_fpga_ddr0_awlock_i, fabric_fpga_ddr0_awvalid_i, fabric_fpga_ddr0_bready_i, fabric_fpga_ddr0_rready_i, fabric_fpga_ddr0_wlast_i, fabric_fpga_ddr0_wvalid_i, fabric_fpga_penable_apb_o, fabric_fpga_psel_apb_o, fabric_fpga_pwrite_apb_o, fabric_fpga_pready_apb_i, fabric_fpga_pslverr_apb_i, fabric_llpp0_arlock_s_o, fabric_llpp0_arvalid_s_o, fabric_llpp0_awlock_s_o, fabric_llpp0_awvalid_s_o, fabric_llpp0_bready_s_o, fabric_llpp0_rready_s_o
-, fabric_llpp0_wlast_s_o, fabric_llpp0_wvalid_s_o, fabric_llpp0_arready_s_i, fabric_llpp0_awready_s_i, fabric_llpp0_bvalid_s_i, fabric_llpp0_rlast_s_i, fabric_llpp0_rvalid_s_i, fabric_llpp0_wready_s_i, fabric_llpp1_arlock_s_o, fabric_llpp1_arvalid_s_o, fabric_llpp1_awlock_s_o, fabric_llpp1_awvalid_s_o, fabric_llpp1_bready_s_o, fabric_llpp1_rready_s_o, fabric_llpp1_wlast_s_o, fabric_llpp1_wvalid_s_o, fabric_llpp1_arready_s_i, fabric_llpp1_awready_s_i, fabric_llpp1_bvalid_s_i, fabric_llpp1_rlast_s_i, fabric_llpp1_rvalid_s_i
-, fabric_llpp1_wready_s_i, fabric_llpp2_arlock_s_o, fabric_llpp2_arvalid_s_o, fabric_llpp2_awlock_s_o, fabric_llpp2_awvalid_s_o, fabric_llpp2_bready_s_o, fabric_llpp2_rready_s_o, fabric_llpp2_wlast_s_o, fabric_llpp2_wvalid_s_o, fabric_llpp2_arready_s_i, fabric_llpp2_awready_s_i, fabric_llpp2_bvalid_s_i, fabric_llpp2_rlast_s_i, fabric_llpp2_rvalid_s_i, fabric_llpp2_wready_s_i, fabric_llpp3_arlock_s_o, fabric_llpp3_arvalid_s_o, fabric_llpp3_awlock_s_o, fabric_llpp3_awvalid_s_o, fabric_llpp3_bready_s_o, fabric_llpp3_rready_s_o
-, fabric_llpp3_wlast_s_o, fabric_llpp3_wvalid_s_o, fabric_llpp3_arready_s_i, fabric_llpp3_awready_s_i, fabric_llpp3_bvalid_s_i, fabric_llpp3_rlast_s_i, fabric_llpp3_rvalid_s_i, fabric_llpp3_wready_s_i, fabric_qos_ppready_o, fabric_qos_ppslverr_o, fabric_qos_ppenable_i, fabric_qos_ppwrite_i, fabric_qos_presetn_i, fabric_qos_psel_i, fabric_tnd_hssl_flushin_o, fabric_tnd_hssl_trigin_o, fabric_tnd_fpga_apb_master_penable_o, fabric_tnd_fpga_apb_master_psel_o, fabric_tnd_fpga_apb_master_pwrite_o, fabric_tnd_fpga_atb_master_afvalid_o, fabric_tnd_fpga_atb_master_atready_o
-, fabric_tnd_fpga_atb_master_syncreq_o, fabric_tnd_hssl_apb_master_penable_o, fabric_tnd_hssl_apb_master_psel_o, fabric_tnd_hssl_apb_master_pwrite_o, fabric_tnd_hssl_atb_master_afready_o, fabric_tnd_hssl_atb_master_atvalid_o, fabric_tnd_trace_clk_traceoutportintf_o, fabric_tnd_trace_ctl_traceoutportintf_o, fabric_tnd_fpga_apb_master_pready_i, fabric_tnd_fpga_apb_master_pslverr_i, fabric_tnd_fpga_atb_master_afready_i, fabric_tnd_fpga_atb_master_atvalid_i, fabric_tnd_hssl_apb_master_pready_i, fabric_tnd_hssl_apb_master_pslverr_i, fabric_tnd_hssl_atb_master_afvalid_i, fabric_tnd_hssl_atb_master_atready_i, fabric_tnd_hssl_atb_master_syncreq_i, fabric_watchdog0_signal_0_o, fabric_watchdog0_signal_1_o, fabric_watchdog1_signal_0_o, fabric_watchdog1_signal_1_o
-, fabric_watchdog2_signal_0_o, fabric_watchdog2_signal_1_o, fabric_watchdog3_signal_0_o, fabric_watchdog3_signal_1_o, fabric_soc_mon_sensor_alarm_o, fabric_erom_fpga_cpu0_dbgen_i, fabric_erom_fpga_cpu0_hiden_i, fabric_erom_fpga_cpu0_hniden_i, fabric_erom_fpga_cpu0_niden_i, fabric_erom_fpga_cpu1_dbgen_i, fabric_erom_fpga_cpu1_hiden_i, fabric_erom_fpga_cpu1_hniden_i, fabric_erom_fpga_cpu1_niden_i, fabric_erom_fpga_cpu2_dbgen_i, fabric_erom_fpga_cpu2_hiden_i, fabric_erom_fpga_cpu2_hniden_i, fabric_erom_fpga_cpu2_niden_i, fabric_erom_fpga_cpu3_dbgen_i, fabric_erom_fpga_cpu3_hiden_i, fabric_erom_fpga_cpu3_hniden_i, fabric_erom_fpga_cpu3_niden_i
-, fabric_erom_fpga_cs_dbgen_i, fabric_erom_fpga_cs_niden_i, fabric_erom_fpga_cs_deviceen_i, fabric_erom_fpga_cs_rst_n_i, fabric_erom_fpga_debug_en_i, fabric_flash_irq_toggle_o, fabric_flash_irq_o, fabric_enable_TMR_i, fabric_lowskew_i, fabric_lowskew_o, fabric_fpga_nic_rstn_i, fabric_fpga_trigger_in_o, fabric_fpga_trigger_out_i, fabric_fpga_interrupt_in_i, fabric_fpga_events60_i, fabric_fpga_araddr_axi_s1_o, fabric_fpga_arburst_axi_s1_o, fabric_fpga_arcache_axi_s1_o, fabric_fpga_arid_axi_s1_o, fabric_fpga_arlen_axi_s1_o, fabric_fpga_arprot_axi_s1_o
-, fabric_fpga_arqos_axi_s1_o, fabric_fpga_arregion_axi_s1_o, fabric_fpga_arsize_axi_s1_o, fabric_fpga_awaddr_axi_s1_o, fabric_fpga_awburst_axi_s1_o, fabric_fpga_awcache_axi_s1_o, fabric_fpga_awid_axi_s1_o, fabric_fpga_awlen_axi_s1_o, fabric_fpga_awprot_axi_s1_o, fabric_fpga_awqos_axi_s1_o, fabric_fpga_awregion_axi_s1_o, fabric_fpga_awsize_axi_s1_o, fabric_fpga_wdata_axi_s1_o, fabric_fpga_wstrb_axi_s1_o, fabric_fpga_bid_axi_s1_i, fabric_fpga_bresp_axi_s1_i, fabric_fpga_rdata_axi_s1_i, fabric_fpga_rid_axi_s1_i, fabric_fpga_rresp_axi_s1_i, fabric_fpga_araddr_axi_s2_o, fabric_fpga_arburst_axi_s2_o
-, fabric_fpga_arcache_axi_s2_o, fabric_fpga_arid_axi_s2_o, fabric_fpga_arlen_axi_s2_o, fabric_fpga_arprot_axi_s2_o, fabric_fpga_arqos_axi_s2_o, fabric_fpga_arregion_axi_s2_o, fabric_fpga_arsize_axi_s2_o, fabric_fpga_awaddr_axi_s2_o, fabric_fpga_awburst_axi_s2_o, fabric_fpga_awcache_axi_s2_o, fabric_fpga_awid_axi_s2_o, fabric_fpga_awlen_axi_s2_o, fabric_fpga_awprot_axi_s2_o, fabric_fpga_awqos_axi_s2_o, fabric_fpga_awregion_axi_s2_o, fabric_fpga_awsize_axi_s2_o, fabric_fpga_wdata_axi_s2_o, fabric_fpga_wstrb_axi_s2_o, fabric_fpga_bid_axi_s2_i, fabric_fpga_bresp_axi_s2_i, fabric_fpga_rdata_axi_s2_i
-, fabric_fpga_rid_axi_s2_i, fabric_fpga_rresp_axi_s2_i, fabric_fpga_bid_axi_m1_o, fabric_fpga_bresp_axi_m1_o, fabric_fpga_dma_ack_m1_o, fabric_fpga_dma_finish_m1_o, fabric_fpga_rdata_axi_m1_o, fabric_fpga_rid_axi_m1_o, fabric_fpga_rresp_axi_m1_o, fabric_fpga_araddr_axi_m1_i, fabric_fpga_arburst_axi_m1_i, fabric_fpga_arcache_axi_m1_i, fabric_fpga_arid_axi_m1_i, fabric_fpga_arlen_axi_m1_i, fabric_fpga_arprot_axi_m1_i, fabric_fpga_arqos_axi_m1_i, fabric_fpga_arsize_axi_m1_i, fabric_fpga_awaddr_axi_m1_i, fabric_fpga_awburst_axi_m1_i, fabric_fpga_awcache_axi_m1_i, fabric_fpga_awid_axi_m1_i
-, fabric_fpga_awlen_axi_m1_i, fabric_fpga_awprot_axi_m1_i, fabric_fpga_awqos_axi_m1_i, fabric_fpga_awsize_axi_m1_i, fabric_fpga_dma_last_m1_i, fabric_fpga_dma_req_m1_i, fabric_fpga_dma_single_m1_i, fabric_fpga_wdata_axi_m1_i, fabric_fpga_wstrb_axi_m1_i, fabric_fpga_bid_axi_m2_o, fabric_fpga_bresp_axi_m2_o, fabric_fpga_dma_ack_m2_o, fabric_fpga_dma_finish_m2_o, fabric_fpga_rdata_axi_m2_o, fabric_fpga_rid_axi_m2_o, fabric_fpga_rresp_axi_m2_o, fabric_fpga_araddr_axi_m2_i, fabric_fpga_arburst_axi_m2_i, fabric_fpga_arcache_axi_m2_i, fabric_fpga_arid_axi_m2_i, fabric_fpga_arlen_axi_m2_i
-, fabric_fpga_arprot_axi_m2_i, fabric_fpga_arqos_axi_m2_i, fabric_fpga_arsize_axi_m2_i, fabric_fpga_awaddr_axi_m2_i, fabric_fpga_awburst_axi_m2_i, fabric_fpga_awcache_axi_m2_i, fabric_fpga_awid_axi_m2_i, fabric_fpga_awlen_axi_m2_i, fabric_fpga_awprot_axi_m2_i, fabric_fpga_awqos_axi_m2_i, fabric_fpga_awsize_axi_m2_i, fabric_fpga_dma_last_m2_i, fabric_fpga_dma_req_m2_i, fabric_fpga_dma_single_m2_i, fabric_fpga_wdata_axi_m2_i, fabric_fpga_wstrb_axi_m2_i, fabric_fpga_ddr0_bid_o, fabric_fpga_ddr0_bresp_o, fabric_fpga_ddr0_rdata_o, fabric_fpga_ddr0_rid_o, fabric_fpga_ddr0_rresp_o
-, fabric_fpga_ddr0_araddr_i, fabric_fpga_ddr0_arburst_i, fabric_fpga_ddr0_arcache_i, fabric_fpga_ddr0_arid_i, fabric_fpga_ddr0_arlen_i, fabric_fpga_ddr0_arprot_i, fabric_fpga_ddr0_arqos_i, fabric_fpga_ddr0_arsize_i, fabric_fpga_ddr0_awaddr_i, fabric_fpga_ddr0_awburst_i, fabric_fpga_ddr0_awcache_i, fabric_fpga_ddr0_awid_i, fabric_fpga_ddr0_awlen_i, fabric_fpga_ddr0_awprot_i, fabric_fpga_ddr0_awqos_i, fabric_fpga_ddr0_awsize_i, fabric_fpga_ddr0_wdata_i, fabric_fpga_ddr0_wstrb_i, fabric_fpga_paddr_apb_o, fabric_fpga_pwdata_apb_o, fabric_fpga_prdata_apb_i
-, fabric_llpp0_araddr_s_o, fabric_llpp0_arburst_s_o, fabric_llpp0_arcache_s_o, fabric_llpp0_arid_s_o, fabric_llpp0_arlen_s_o, fabric_llpp0_arprot_s_o, fabric_llpp0_arqos_s_o, fabric_llpp0_arsize_s_o, fabric_llpp0_awaddr_s_o, fabric_llpp0_awburst_s_o, fabric_llpp0_awcache_s_o, fabric_llpp0_awid_s_o, fabric_llpp0_awlen_s_o, fabric_llpp0_awprot_s_o, fabric_llpp0_awqos_s_o, fabric_llpp0_awsize_s_o, fabric_llpp0_wdata_s_o, fabric_llpp0_wstrb_s_o, fabric_llpp0_bid_s_i, fabric_llpp0_bresp_s_i, fabric_llpp0_rdata_s_i
-, fabric_llpp0_rid_s_i, fabric_llpp0_rresp_s_i, fabric_llpp1_araddr_s_o, fabric_llpp1_arburst_s_o, fabric_llpp1_arcache_s_o, fabric_llpp1_arid_s_o, fabric_llpp1_arlen_s_o, fabric_llpp1_arprot_s_o, fabric_llpp1_arsize_s_o, fabric_llpp1_awaddr_s_o, fabric_llpp1_awburst_s_o, fabric_llpp1_awcache_s_o, fabric_llpp1_awid_s_o, fabric_llpp1_awlen_s_o, fabric_llpp1_awprot_s_o, fabric_llpp1_awqos_s_o, fabric_llpp1_awsize_s_o, fabric_llpp1_wdata_s_o, fabric_llpp1_wstrb_s_o, fabric_llpp1_bid_s_i, fabric_llpp1_bresp_s_i
-, fabric_llpp1_rdata_s_i, fabric_llpp1_rid_s_i, fabric_llpp1_rresp_s_i, fabric_llpp2_araddr_s_o, fabric_llpp2_arburst_s_o, fabric_llpp2_arcache_s_o, fabric_llpp2_arid_s_o, fabric_llpp2_arlen_s_o, fabric_llpp2_arprot_s_o, fabric_llpp2_arqos_s_o, fabric_llpp2_arsize_s_o, fabric_llpp2_awaddr_s_o, fabric_llpp2_awburst_s_o, fabric_llpp2_awcache_s_o, fabric_llpp2_awid_s_o, fabric_llpp2_awlen_s_o, fabric_llpp2_awprot_s_o, fabric_llpp2_awqos_s_o, fabric_llpp2_awsize_s_o, fabric_llpp2_wdata_s_o, fabric_llpp2_wstrb_s_o
-, fabric_llpp2_bid_s_i, fabric_llpp2_bresp_s_i, fabric_llpp2_rdata_s_i, fabric_llpp2_rid_s_i, fabric_llpp2_rresp_s_i, fabric_llpp3_araddr_s_o, fabric_llpp3_arburst_s_o, fabric_llpp3_arcache_s_o, fabric_llpp3_arid_s_o, fabric_llpp3_arlen_s_o, fabric_llpp3_arprot_s_o, fabric_llpp3_arqos_s_o, fabric_llpp3_arsize_s_o, fabric_llpp3_awaddr_s_o, fabric_llpp3_awburst_s_o, fabric_llpp3_awcache_s_o, fabric_llpp3_awid_s_o, fabric_llpp3_awlen_s_o, fabric_llpp3_awprot_s_o, fabric_llpp3_awqos_s_o, fabric_llpp3_awsize_s_o
-, fabric_llpp3_wdata_s_o, fabric_llpp3_wstrb_s_o, fabric_llpp3_bid_s_i, fabric_llpp3_bresp_s_i, fabric_llpp3_rdata_s_i, fabric_llpp3_rid_s_i, fabric_llpp3_rresp_s_i, fabric_qos_pprdata_o, fabric_qos_ppaddr_i, fabric_qos_ppwdata_i, fabric_tnd_fpga_apb_master_paddr_o, fabric_tnd_fpga_apb_master_pwdata_o, fabric_tnd_hssl_apb_master_paddr_o, fabric_tnd_hssl_apb_master_pwdata_o, fabric_tnd_hssl_atb_master_atbytes_o, fabric_tnd_hssl_atb_master_atdata_o, fabric_tnd_hssl_atb_master_atid_o, fabric_tnd_trace_data_traceoutportintf_o, fabric_tsvalue_tsgen_fpga_o, fabric_tnd_fpga_apb_master_prdata_i, fabric_tnd_fpga_atb_master_atbytes_i
-, fabric_tnd_fpga_atb_master_atdata_i, fabric_tnd_fpga_atb_master_atid_i, fabric_tnd_hssl_apb_master_prdata_i, fabric_tst_pll_lock_o, fabric_llpp1_arqos_s_o, fabric_spw_interrupts_toggle_o, fabric_spw_interrupts_o, fabric_fpga_dma_hs_rstn_i);
-    input [2:0] fabric_enable_TMR_i;
-    input fabric_erom_fpga_cpu0_dbgen_i;
-    input fabric_erom_fpga_cpu0_hiden_i;
-    input fabric_erom_fpga_cpu0_hniden_i;
-    input fabric_erom_fpga_cpu0_niden_i;
-    input fabric_erom_fpga_cpu1_dbgen_i;
-    input fabric_erom_fpga_cpu1_hiden_i;
-    input fabric_erom_fpga_cpu1_hniden_i;
-    input fabric_erom_fpga_cpu1_niden_i;
-    input fabric_erom_fpga_cpu2_dbgen_i;
-    input fabric_erom_fpga_cpu2_hiden_i;
-    input fabric_erom_fpga_cpu2_hniden_i;
-    input fabric_erom_fpga_cpu2_niden_i;
-    input fabric_erom_fpga_cpu3_dbgen_i;
-    input fabric_erom_fpga_cpu3_hiden_i;
-    input fabric_erom_fpga_cpu3_hniden_i;
-    input fabric_erom_fpga_cpu3_niden_i;
-    input fabric_erom_fpga_cs_dbgen_i;
-    input fabric_erom_fpga_cs_deviceen_i;
-    input fabric_erom_fpga_cs_niden_i;
-    input fabric_erom_fpga_cs_rst_n_i;
-    input fabric_erom_fpga_debug_en_i;
-    output fabric_flash_irq_o;
-    output fabric_flash_irq_toggle_o;
-    input [39:0] fabric_fpga_araddr_axi_m1_i;
-    input [39:0] fabric_fpga_araddr_axi_m2_i;
-    output [39:0] fabric_fpga_araddr_axi_s1_o;
-    output [39:0] fabric_fpga_araddr_axi_s2_o;
-    input [1:0] fabric_fpga_arburst_axi_m1_i;
-    input [1:0] fabric_fpga_arburst_axi_m2_i;
-    output [1:0] fabric_fpga_arburst_axi_s1_o;
-    output [1:0] fabric_fpga_arburst_axi_s2_o;
-    input [3:0] fabric_fpga_arcache_axi_m1_i;
-    input [3:0] fabric_fpga_arcache_axi_m2_i;
-    output [3:0] fabric_fpga_arcache_axi_s1_o;
-    output [3:0] fabric_fpga_arcache_axi_s2_o;
-    input [4:0] fabric_fpga_arid_axi_m1_i;
-    input [4:0] fabric_fpga_arid_axi_m2_i;
-    output [11:0] fabric_fpga_arid_axi_s1_o;
-    output [11:0] fabric_fpga_arid_axi_s2_o;
-    input [7:0] fabric_fpga_arlen_axi_m1_i;
-    input [7:0] fabric_fpga_arlen_axi_m2_i;
-    output [7:0] fabric_fpga_arlen_axi_s1_o;
-    output [7:0] fabric_fpga_arlen_axi_s2_o;
-    input fabric_fpga_arlock_axi_m1_i;
-    input fabric_fpga_arlock_axi_m2_i;
-    output fabric_fpga_arlock_axi_s1_o;
-    output fabric_fpga_arlock_axi_s2_o;
-    input [2:0] fabric_fpga_arprot_axi_m1_i;
-    input [2:0] fabric_fpga_arprot_axi_m2_i;
-    output [2:0] fabric_fpga_arprot_axi_s1_o;
-    output [2:0] fabric_fpga_arprot_axi_s2_o;
-    input [3:0] fabric_fpga_arqos_axi_m1_i;
-    input [3:0] fabric_fpga_arqos_axi_m2_i;
-    output [3:0] fabric_fpga_arqos_axi_s1_o;
-    output [3:0] fabric_fpga_arqos_axi_s2_o;
-    output fabric_fpga_arready_axi_m1_o;
-    output fabric_fpga_arready_axi_m2_o;
-    input fabric_fpga_arready_axi_s1_i;
-    input fabric_fpga_arready_axi_s2_i;
-    output [3:0] fabric_fpga_arregion_axi_s1_o;
-    output [3:0] fabric_fpga_arregion_axi_s2_o;
-    input [2:0] fabric_fpga_arsize_axi_m1_i;
-    input [2:0] fabric_fpga_arsize_axi_m2_i;
-    output [2:0] fabric_fpga_arsize_axi_s1_o;
-    output [2:0] fabric_fpga_arsize_axi_s2_o;
-    input fabric_fpga_arvalid_axi_m1_i;
-    input fabric_fpga_arvalid_axi_m2_i;
-    output fabric_fpga_arvalid_axi_s1_o;
-    output fabric_fpga_arvalid_axi_s2_o;
-    input [39:0] fabric_fpga_awaddr_axi_m1_i;
-    input [39:0] fabric_fpga_awaddr_axi_m2_i;
-    output [39:0] fabric_fpga_awaddr_axi_s1_o;
-    output [39:0] fabric_fpga_awaddr_axi_s2_o;
-    input [1:0] fabric_fpga_awburst_axi_m1_i;
-    input [1:0] fabric_fpga_awburst_axi_m2_i;
-    output [1:0] fabric_fpga_awburst_axi_s1_o;
-    output [1:0] fabric_fpga_awburst_axi_s2_o;
-    input [3:0] fabric_fpga_awcache_axi_m1_i;
-    input [3:0] fabric_fpga_awcache_axi_m2_i;
-    output [3:0] fabric_fpga_awcache_axi_s1_o;
-    output [3:0] fabric_fpga_awcache_axi_s2_o;
-    input [4:0] fabric_fpga_awid_axi_m1_i;
-    input [4:0] fabric_fpga_awid_axi_m2_i;
-    output [11:0] fabric_fpga_awid_axi_s1_o;
-    output [11:0] fabric_fpga_awid_axi_s2_o;
-    input [7:0] fabric_fpga_awlen_axi_m1_i;
-    input [7:0] fabric_fpga_awlen_axi_m2_i;
-    output [7:0] fabric_fpga_awlen_axi_s1_o;
-    output [7:0] fabric_fpga_awlen_axi_s2_o;
-    input fabric_fpga_awlock_axi_m1_i;
-    input fabric_fpga_awlock_axi_m2_i;
-    output fabric_fpga_awlock_axi_s1_o;
-    output fabric_fpga_awlock_axi_s2_o;
-    input [2:0] fabric_fpga_awprot_axi_m1_i;
-    input [2:0] fabric_fpga_awprot_axi_m2_i;
-    output [2:0] fabric_fpga_awprot_axi_s1_o;
-    output [2:0] fabric_fpga_awprot_axi_s2_o;
-    input [3:0] fabric_fpga_awqos_axi_m1_i;
-    input [3:0] fabric_fpga_awqos_axi_m2_i;
-    output [3:0] fabric_fpga_awqos_axi_s1_o;
-    output [3:0] fabric_fpga_awqos_axi_s2_o;
-    output fabric_fpga_awready_axi_m1_o;
-    output fabric_fpga_awready_axi_m2_o;
-    input fabric_fpga_awready_axi_s1_i;
-    input fabric_fpga_awready_axi_s2_i;
-    output [3:0] fabric_fpga_awregion_axi_s1_o;
-    output [3:0] fabric_fpga_awregion_axi_s2_o;
-    input [2:0] fabric_fpga_awsize_axi_m1_i;
-    input [2:0] fabric_fpga_awsize_axi_m2_i;
-    output [2:0] fabric_fpga_awsize_axi_s1_o;
-    output [2:0] fabric_fpga_awsize_axi_s2_o;
-    input fabric_fpga_awvalid_axi_m1_i;
-    input fabric_fpga_awvalid_axi_m2_i;
-    output fabric_fpga_awvalid_axi_s1_o;
-    output fabric_fpga_awvalid_axi_s2_o;
-    output [4:0] fabric_fpga_bid_axi_m1_o;
-    output [4:0] fabric_fpga_bid_axi_m2_o;
-    input [11:0] fabric_fpga_bid_axi_s1_i;
-    input [11:0] fabric_fpga_bid_axi_s2_i;
-    input fabric_fpga_bready_axi_m1_i;
-    input fabric_fpga_bready_axi_m2_i;
-    output fabric_fpga_bready_axi_s1_o;
-    output fabric_fpga_bready_axi_s2_o;
-    output [1:0] fabric_fpga_bresp_axi_m1_o;
-    output [1:0] fabric_fpga_bresp_axi_m2_o;
-    input [1:0] fabric_fpga_bresp_axi_s1_i;
-    input [1:0] fabric_fpga_bresp_axi_s2_i;
-    output fabric_fpga_bvalid_axi_m1_o;
-    output fabric_fpga_bvalid_axi_m2_o;
-    input fabric_fpga_bvalid_axi_s1_i;
-    input fabric_fpga_bvalid_axi_s2_i;
-    input [39:0] fabric_fpga_ddr0_araddr_i;
-    input [1:0] fabric_fpga_ddr0_arburst_i;
-    input [3:0] fabric_fpga_ddr0_arcache_i;
-    input [4:0] fabric_fpga_ddr0_arid_i;
-    input [7:0] fabric_fpga_ddr0_arlen_i;
-    input fabric_fpga_ddr0_arlock_i;
-    input [2:0] fabric_fpga_ddr0_arprot_i;
-    input [3:0] fabric_fpga_ddr0_arqos_i;
-    output fabric_fpga_ddr0_arready_o;
-    input [2:0] fabric_fpga_ddr0_arsize_i;
-    input fabric_fpga_ddr0_arvalid_i;
-    input [39:0] fabric_fpga_ddr0_awaddr_i;
-    input [1:0] fabric_fpga_ddr0_awburst_i;
-    input [3:0] fabric_fpga_ddr0_awcache_i;
-    input [4:0] fabric_fpga_ddr0_awid_i;
-    input [7:0] fabric_fpga_ddr0_awlen_i;
-    input fabric_fpga_ddr0_awlock_i;
-    input [2:0] fabric_fpga_ddr0_awprot_i;
-    input [3:0] fabric_fpga_ddr0_awqos_i;
-    output fabric_fpga_ddr0_awready_o;
-    input [2:0] fabric_fpga_ddr0_awsize_i;
-    input fabric_fpga_ddr0_awvalid_i;
-    output [4:0] fabric_fpga_ddr0_bid_o;
-    input fabric_fpga_ddr0_bready_i;
-    output [1:0] fabric_fpga_ddr0_bresp_o;
-    output fabric_fpga_ddr0_bvalid_o;
-    output [127:0] fabric_fpga_ddr0_rdata_o;
-    output [4:0] fabric_fpga_ddr0_rid_o;
-    output fabric_fpga_ddr0_rlast_o;
-    input fabric_fpga_ddr0_rready_i;
-    output [1:0] fabric_fpga_ddr0_rresp_o;
-    output fabric_fpga_ddr0_rvalid_o;
-    input [127:0] fabric_fpga_ddr0_wdata_i;
-    input fabric_fpga_ddr0_wlast_i;
-    output fabric_fpga_ddr0_wready_o;
-    input [15:0] fabric_fpga_ddr0_wstrb_i;
-    input fabric_fpga_ddr0_wvalid_i;
-    output [5:0] fabric_fpga_dma_ack_m1_o;
-    output [5:0] fabric_fpga_dma_ack_m2_o;
-    output [5:0] fabric_fpga_dma_finish_m1_o;
-    output [5:0] fabric_fpga_dma_finish_m2_o;
-    input [5:0] fabric_fpga_dma_hs_rstn_i;
-    input [5:0] fabric_fpga_dma_last_m1_i;
-    input [5:0] fabric_fpga_dma_last_m2_i;
-    input [5:0] fabric_fpga_dma_req_m1_i;
-    input [5:0] fabric_fpga_dma_req_m2_i;
-    input [5:0] fabric_fpga_dma_single_m1_i;
-    input [5:0] fabric_fpga_dma_single_m2_i;
-    input [59:0] fabric_fpga_events60_i;
-    input [119:0] fabric_fpga_interrupt_in_i;
-    input [9:0] fabric_fpga_nic_rstn_i;
-    output [31:0] fabric_fpga_paddr_apb_o;
-    output fabric_fpga_penable_apb_o;
-    input fabric_fpga_pmrstn_i;
-    input [31:0] fabric_fpga_prdata_apb_i;
-    input fabric_fpga_pready_apb_i;
-    output fabric_fpga_psel_apb_o;
-    input fabric_fpga_pslverr_apb_i;
-    output [31:0] fabric_fpga_pwdata_apb_o;
-    output fabric_fpga_pwrite_apb_o;
-    output [127:0] fabric_fpga_rdata_axi_m1_o;
-    output [127:0] fabric_fpga_rdata_axi_m2_o;
-    input [127:0] fabric_fpga_rdata_axi_s1_i;
-    input [127:0] fabric_fpga_rdata_axi_s2_i;
-    output [4:0] fabric_fpga_rid_axi_m1_o;
-    output [4:0] fabric_fpga_rid_axi_m2_o;
-    input [11:0] fabric_fpga_rid_axi_s1_i;
-    input [11:0] fabric_fpga_rid_axi_s2_i;
-    output fabric_fpga_rlast_axi_m1_o;
-    output fabric_fpga_rlast_axi_m2_o;
-    input fabric_fpga_rlast_axi_s1_i;
-    input fabric_fpga_rlast_axi_s2_i;
-    input fabric_fpga_rready_axi_m1_i;
-    input fabric_fpga_rready_axi_m2_i;
-    output fabric_fpga_rready_axi_s1_o;
-    output fabric_fpga_rready_axi_s2_o;
-    output [1:0] fabric_fpga_rresp_axi_m1_o;
-    output [1:0] fabric_fpga_rresp_axi_m2_o;
-    input [1:0] fabric_fpga_rresp_axi_s1_i;
-    input [1:0] fabric_fpga_rresp_axi_s2_i;
-    output fabric_fpga_rvalid_axi_m1_o;
-    output fabric_fpga_rvalid_axi_m2_o;
-    input fabric_fpga_rvalid_axi_s1_i;
-    input fabric_fpga_rvalid_axi_s2_i;
-    input fabric_fpga_sysrstn_i;
-    output [7:0] fabric_fpga_trigger_in_o;
-    input [7:0] fabric_fpga_trigger_out_i;
-    input [127:0] fabric_fpga_wdata_axi_m1_i;
-    input [127:0] fabric_fpga_wdata_axi_m2_i;
-    output [127:0] fabric_fpga_wdata_axi_s1_o;
-    output [127:0] fabric_fpga_wdata_axi_s2_o;
-    input fabric_fpga_wlast_axi_m1_i;
-    input fabric_fpga_wlast_axi_m2_i;
-    output fabric_fpga_wlast_axi_s1_o;
-    output fabric_fpga_wlast_axi_s2_o;
-    output fabric_fpga_wready_axi_m1_o;
-    output fabric_fpga_wready_axi_m2_o;
-    input fabric_fpga_wready_axi_s1_i;
-    input fabric_fpga_wready_axi_s2_i;
-    input [15:0] fabric_fpga_wstrb_axi_m1_i;
-    input [15:0] fabric_fpga_wstrb_axi_m2_i;
-    output [15:0] fabric_fpga_wstrb_axi_s1_o;
-    output [15:0] fabric_fpga_wstrb_axi_s2_o;
-    input fabric_fpga_wvalid_axi_m1_i;
-    input fabric_fpga_wvalid_axi_m2_i;
-    output fabric_fpga_wvalid_axi_s1_o;
-    output fabric_fpga_wvalid_axi_s2_o;
-    output [31:0] fabric_llpp0_araddr_s_o;
-    output [1:0] fabric_llpp0_arburst_s_o;
-    output [3:0] fabric_llpp0_arcache_s_o;
-    output [11:0] fabric_llpp0_arid_s_o;
-    output [7:0] fabric_llpp0_arlen_s_o;
-    output fabric_llpp0_arlock_s_o;
-    output [2:0] fabric_llpp0_arprot_s_o;
-    output [3:0] fabric_llpp0_arqos_s_o;
-    input fabric_llpp0_arready_s_i;
-    output [2:0] fabric_llpp0_arsize_s_o;
-    output fabric_llpp0_arvalid_s_o;
-    output [31:0] fabric_llpp0_awaddr_s_o;
-    output [1:0] fabric_llpp0_awburst_s_o;
-    output [3:0] fabric_llpp0_awcache_s_o;
-    output [11:0] fabric_llpp0_awid_s_o;
-    output [7:0] fabric_llpp0_awlen_s_o;
-    output fabric_llpp0_awlock_s_o;
-    output [2:0] fabric_llpp0_awprot_s_o;
-    output [3:0] fabric_llpp0_awqos_s_o;
-    input fabric_llpp0_awready_s_i;
-    output [2:0] fabric_llpp0_awsize_s_o;
-    output fabric_llpp0_awvalid_s_o;
-    input [11:0] fabric_llpp0_bid_s_i;
-    output fabric_llpp0_bready_s_o;
-    input [1:0] fabric_llpp0_bresp_s_i;
-    input fabric_llpp0_bvalid_s_i;
-    input [31:0] fabric_llpp0_rdata_s_i;
-    input [11:0] fabric_llpp0_rid_s_i;
-    input fabric_llpp0_rlast_s_i;
-    output fabric_llpp0_rready_s_o;
-    input [1:0] fabric_llpp0_rresp_s_i;
-    input fabric_llpp0_rvalid_s_i;
-    output [31:0] fabric_llpp0_wdata_s_o;
-    output fabric_llpp0_wlast_s_o;
-    input fabric_llpp0_wready_s_i;
-    output [3:0] fabric_llpp0_wstrb_s_o;
-    output fabric_llpp0_wvalid_s_o;
-    output [31:0] fabric_llpp1_araddr_s_o;
-    output [1:0] fabric_llpp1_arburst_s_o;
-    output [3:0] fabric_llpp1_arcache_s_o;
-    output [11:0] fabric_llpp1_arid_s_o;
-    output [7:0] fabric_llpp1_arlen_s_o;
-    output fabric_llpp1_arlock_s_o;
-    output [2:0] fabric_llpp1_arprot_s_o;
-    output [3:0] fabric_llpp1_arqos_s_o;
-    input fabric_llpp1_arready_s_i;
-    output [2:0] fabric_llpp1_arsize_s_o;
-    output fabric_llpp1_arvalid_s_o;
-    output [31:0] fabric_llpp1_awaddr_s_o;
-    output [1:0] fabric_llpp1_awburst_s_o;
-    output [3:0] fabric_llpp1_awcache_s_o;
-    output [11:0] fabric_llpp1_awid_s_o;
-    output [7:0] fabric_llpp1_awlen_s_o;
-    output fabric_llpp1_awlock_s_o;
-    output [2:0] fabric_llpp1_awprot_s_o;
-    output [3:0] fabric_llpp1_awqos_s_o;
-    input fabric_llpp1_awready_s_i;
-    output [2:0] fabric_llpp1_awsize_s_o;
-    output fabric_llpp1_awvalid_s_o;
-    input [11:0] fabric_llpp1_bid_s_i;
-    output fabric_llpp1_bready_s_o;
-    input [1:0] fabric_llpp1_bresp_s_i;
-    input fabric_llpp1_bvalid_s_i;
-    input [31:0] fabric_llpp1_rdata_s_i;
-    input [11:0] fabric_llpp1_rid_s_i;
-    input fabric_llpp1_rlast_s_i;
-    output fabric_llpp1_rready_s_o;
-    input [1:0] fabric_llpp1_rresp_s_i;
-    input fabric_llpp1_rvalid_s_i;
-    output [31:0] fabric_llpp1_wdata_s_o;
-    output fabric_llpp1_wlast_s_o;
-    input fabric_llpp1_wready_s_i;
-    output [3:0] fabric_llpp1_wstrb_s_o;
-    output fabric_llpp1_wvalid_s_o;
-    output [31:0] fabric_llpp2_araddr_s_o;
-    output [1:0] fabric_llpp2_arburst_s_o;
-    output [3:0] fabric_llpp2_arcache_s_o;
-    output [11:0] fabric_llpp2_arid_s_o;
-    output [7:0] fabric_llpp2_arlen_s_o;
-    output fabric_llpp2_arlock_s_o;
-    output [2:0] fabric_llpp2_arprot_s_o;
-    output [3:0] fabric_llpp2_arqos_s_o;
-    input fabric_llpp2_arready_s_i;
-    output [2:0] fabric_llpp2_arsize_s_o;
-    output fabric_llpp2_arvalid_s_o;
-    output [31:0] fabric_llpp2_awaddr_s_o;
-    output [1:0] fabric_llpp2_awburst_s_o;
-    output [3:0] fabric_llpp2_awcache_s_o;
-    output [11:0] fabric_llpp2_awid_s_o;
-    output [7:0] fabric_llpp2_awlen_s_o;
-    output fabric_llpp2_awlock_s_o;
-    output [2:0] fabric_llpp2_awprot_s_o;
-    output [3:0] fabric_llpp2_awqos_s_o;
-    input fabric_llpp2_awready_s_i;
-    output [2:0] fabric_llpp2_awsize_s_o;
-    output fabric_llpp2_awvalid_s_o;
-    input [11:0] fabric_llpp2_bid_s_i;
-    output fabric_llpp2_bready_s_o;
-    input [1:0] fabric_llpp2_bresp_s_i;
-    input fabric_llpp2_bvalid_s_i;
-    input [31:0] fabric_llpp2_rdata_s_i;
-    input [11:0] fabric_llpp2_rid_s_i;
-    input fabric_llpp2_rlast_s_i;
-    output fabric_llpp2_rready_s_o;
-    input [1:0] fabric_llpp2_rresp_s_i;
-    input fabric_llpp2_rvalid_s_i;
-    output [31:0] fabric_llpp2_wdata_s_o;
-    output fabric_llpp2_wlast_s_o;
-    input fabric_llpp2_wready_s_i;
-    output [3:0] fabric_llpp2_wstrb_s_o;
-    output fabric_llpp2_wvalid_s_o;
-    output [31:0] fabric_llpp3_araddr_s_o;
-    output [1:0] fabric_llpp3_arburst_s_o;
-    output [3:0] fabric_llpp3_arcache_s_o;
-    output [11:0] fabric_llpp3_arid_s_o;
-    output [7:0] fabric_llpp3_arlen_s_o;
-    output fabric_llpp3_arlock_s_o;
-    output [2:0] fabric_llpp3_arprot_s_o;
-    output [3:0] fabric_llpp3_arqos_s_o;
-    input fabric_llpp3_arready_s_i;
-    output [2:0] fabric_llpp3_arsize_s_o;
-    output fabric_llpp3_arvalid_s_o;
-    output [31:0] fabric_llpp3_awaddr_s_o;
-    output [1:0] fabric_llpp3_awburst_s_o;
-    output [3:0] fabric_llpp3_awcache_s_o;
-    output [11:0] fabric_llpp3_awid_s_o;
-    output [7:0] fabric_llpp3_awlen_s_o;
-    output fabric_llpp3_awlock_s_o;
-    output [2:0] fabric_llpp3_awprot_s_o;
-    output [3:0] fabric_llpp3_awqos_s_o;
-    input fabric_llpp3_awready_s_i;
-    output [2:0] fabric_llpp3_awsize_s_o;
-    output fabric_llpp3_awvalid_s_o;
-    input [11:0] fabric_llpp3_bid_s_i;
-    output fabric_llpp3_bready_s_o;
-    input [1:0] fabric_llpp3_bresp_s_i;
-    input fabric_llpp3_bvalid_s_i;
-    input [31:0] fabric_llpp3_rdata_s_i;
-    input [11:0] fabric_llpp3_rid_s_i;
-    input fabric_llpp3_rlast_s_i;
-    output fabric_llpp3_rready_s_o;
-    input [1:0] fabric_llpp3_rresp_s_i;
-    input fabric_llpp3_rvalid_s_i;
-    output [31:0] fabric_llpp3_wdata_s_o;
-    output fabric_llpp3_wlast_s_o;
-    input fabric_llpp3_wready_s_i;
-    output [3:0] fabric_llpp3_wstrb_s_o;
-    output fabric_llpp3_wvalid_s_o;
-    input [18:2] fabric_lowskew_i;
-    output [1:0] fabric_lowskew_o;
-    input [31:0] fabric_qos_ppaddr_i;
-    input fabric_qos_ppenable_i;
-    output [31:0] fabric_qos_pprdata_o;
-    output fabric_qos_ppready_o;
-    output fabric_qos_ppslverr_o;
-    input [31:0] fabric_qos_ppwdata_i;
-    input fabric_qos_ppwrite_i;
-    input fabric_qos_presetn_i;
-    input fabric_qos_psel_i;
-    output fabric_soc_mon_sensor_alarm_o;
-    output [2:0] fabric_spw_interrupts_o;
-    output [2:0] fabric_spw_interrupts_toggle_o;
-    input fabric_sysc_hold_on_debug_i;
-    output [31:0] fabric_tnd_fpga_apb_master_paddr_o;
-    output fabric_tnd_fpga_apb_master_penable_o;
-    input [31:0] fabric_tnd_fpga_apb_master_prdata_i;
-    input fabric_tnd_fpga_apb_master_pready_i;
-    output fabric_tnd_fpga_apb_master_psel_o;
-    input fabric_tnd_fpga_apb_master_pslverr_i;
-    output [31:0] fabric_tnd_fpga_apb_master_pwdata_o;
-    output fabric_tnd_fpga_apb_master_pwrite_o;
-    input fabric_tnd_fpga_atb_master_afready_i;
-    output fabric_tnd_fpga_atb_master_afvalid_o;
-    input [3:0] fabric_tnd_fpga_atb_master_atbytes_i;
-    input [127:0] fabric_tnd_fpga_atb_master_atdata_i;
-    input [6:0] fabric_tnd_fpga_atb_master_atid_i;
-    output fabric_tnd_fpga_atb_master_atready_o;
-    input fabric_tnd_fpga_atb_master_atvalid_i;
-    output fabric_tnd_fpga_atb_master_syncreq_o;
-    output [31:0] fabric_tnd_hssl_apb_master_paddr_o;
-    output fabric_tnd_hssl_apb_master_penable_o;
-    input [31:0] fabric_tnd_hssl_apb_master_prdata_i;
-    input fabric_tnd_hssl_apb_master_pready_i;
-    output fabric_tnd_hssl_apb_master_psel_o;
-    input fabric_tnd_hssl_apb_master_pslverr_i;
-    output [31:0] fabric_tnd_hssl_apb_master_pwdata_o;
-    output fabric_tnd_hssl_apb_master_pwrite_o;
-    output fabric_tnd_hssl_atb_master_afready_o;
-    input fabric_tnd_hssl_atb_master_afvalid_i;
-    output [3:0] fabric_tnd_hssl_atb_master_atbytes_o;
-    output [127:0] fabric_tnd_hssl_atb_master_atdata_o;
-    output [6:0] fabric_tnd_hssl_atb_master_atid_o;
-    input fabric_tnd_hssl_atb_master_atready_i;
-    output fabric_tnd_hssl_atb_master_atvalid_o;
-    input fabric_tnd_hssl_atb_master_syncreq_i;
-    output fabric_tnd_hssl_flushin_o;
-    output fabric_tnd_hssl_trigin_o;
-    output fabric_tnd_trace_clk_traceoutportintf_o;
-    output fabric_tnd_trace_ctl_traceoutportintf_o;
-    output [31:0] fabric_tnd_trace_data_traceoutportintf_o;
-    output [6:0] fabric_tst_pll_lock_o;
-    output [63:0] fabric_tsvalue_tsgen_fpga_o;
-    output fabric_watchdog0_signal_0_o;
-    output fabric_watchdog0_signal_1_o;
-    output fabric_watchdog1_signal_0_o;
-    output fabric_watchdog1_signal_1_o;
-    output fabric_watchdog2_signal_0_o;
-    output fabric_watchdog2_signal_1_o;
-    output fabric_watchdog3_signal_0_o;
-    output fabric_watchdog3_signal_1_o;
-    parameter ahb_config = 0;
-    parameter bsm_config = 0;
-endmodule
-
 (* blackbox *)
 module NX_WFG(SI, ZI, RDY, SO, ZO);
     input RDY;

From 827ea115037a975d9e7c8c3d2afa2878b814b3c9 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 11 Mar 2024 13:03:20 +0100
Subject: [PATCH 275/499] start splitting blackboxes and add wrapper techmap

---
 techlibs/nanoxplore/Makefile.inc        |  6 +++++
 techlibs/nanoxplore/cells_bb.v          | 26 -------------------
 techlibs/nanoxplore/cells_bb_l.v        |  0
 techlibs/nanoxplore/cells_bb_m.v        |  0
 techlibs/nanoxplore/cells_bb_u.v        | 10 ++++++++
 techlibs/nanoxplore/cells_wrap_l.v      |  0
 techlibs/nanoxplore/cells_wrap_m.v      |  0
 techlibs/nanoxplore/cells_wrap_u.v      | 34 +++++++++++++++++++++++++
 techlibs/nanoxplore/synth_nanoxplore.cc | 17 ++++++++++++-
 9 files changed, 66 insertions(+), 27 deletions(-)
 create mode 100644 techlibs/nanoxplore/cells_bb_l.v
 create mode 100644 techlibs/nanoxplore/cells_bb_m.v
 create mode 100644 techlibs/nanoxplore/cells_bb_u.v
 create mode 100644 techlibs/nanoxplore/cells_wrap_l.v
 create mode 100644 techlibs/nanoxplore/cells_wrap_m.v
 create mode 100644 techlibs/nanoxplore/cells_wrap_u.v

diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc
index 030cabd64b7..37755106bf4 100644
--- a/techlibs/nanoxplore/Makefile.inc
+++ b/techlibs/nanoxplore/Makefile.inc
@@ -4,7 +4,13 @@ OBJS += techlibs/nanoxplore/synth_nanoxplore.o
 # Techmap
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_l.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_m.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_u.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/drams.txt))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v))
diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index 01fc0e3f3b2..0ff72112153 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -419,21 +419,6 @@ module NX_CKS(CKI, CMD, CKO);
     parameter ck_edge = 1'b0;
 endmodule
 
-(* blackbox *)
-module NX_CKS_U(CKI, CMD, CKO);
-    input CKI;
-    output CKO;
-    input CMD;
-endmodule
-
-(* blackbox *)
-module NX_CMUX_U(CKI0, CKI1, SEL, CKO);
-    input CKI0;
-    input CKI1;
-    output CKO;
-    input SEL;
-endmodule
-
 (* blackbox *)
 module NX_CRX_L(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, BUF_FE_I, RST_N_I, CDR_R_I, CKG_RN_I, PLL_RN_I, TST_I1, TST_I2, TST_I3, TST_I4, LOS_O, DATA_O1, DATA_O2, DATA_O3
 , DATA_O4, DATA_O5, DATA_O6, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24
@@ -2839,17 +2824,6 @@ module NX_FIFO_U(RCK, WCK, WE, WEA, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11
     parameter wck_edge = 1'b0;
 endmodule
 
-(* blackbox *)
-module NX_GCK_U(SI1, SI2, CMD, SO);
-    input CMD;
-    input SI1;
-    input SI2;
-    output SO;
-    parameter inv_in = 1'b0;
-    parameter inv_out = 1'b0;
-    parameter std_mode = "BYPASS";
-endmodule
-
 (* blackbox *)
 module NX_HSSL_L_FULL(hssl_clk_user_i, hssl_clk_ref_i, hssl_clock_o, usr_com_tx_pma_pre_sign_i, usr_com_tx_pma_pre_en_i, usr_com_tx_pma_main_sign_i, usr_com_rx_pma_m_eye_i, usr_com_tx_pma_post_sign_i, usr_pll_pma_rst_n_i, usr_main_rst_n_i, usr_calibrate_pma_en_i, usr_pcs_ctrl_pll_lock_en_i, usr_pcs_ctrl_ovs_en_i, usr_pll_lock_o, usr_calibrate_pma_out_o, pma_clk_ext_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i, usr_tx0_pma_clk_en_i, usr_tx0_busy_o, pma_tx0_o
 , usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_ctrl_el_buff_fifo_en_i, usr_rx0_rst_n_i, usr_rx0_pma_cdr_rst_i, usr_rx0_pma_ckgen_rst_n_i, usr_rx0_pma_pll_rst_n_i, usr_rx0_pma_loss_of_signal_o, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_busy_o, usr_rx0_pll_lock_o, pma_rx0_i, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_pma_clk_en_i, usr_tx1_busy_o, pma_tx1_o
diff --git a/techlibs/nanoxplore/cells_bb_l.v b/techlibs/nanoxplore/cells_bb_l.v
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/techlibs/nanoxplore/cells_bb_m.v b/techlibs/nanoxplore/cells_bb_m.v
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v
new file mode 100644
index 00000000000..41f8736fc00
--- /dev/null
+++ b/techlibs/nanoxplore/cells_bb_u.v
@@ -0,0 +1,10 @@
+(* blackbox *)
+module NX_GCK_U(SI1, SI2, CMD, SO);
+    input CMD;
+    input SI1;
+    input SI2;
+    output SO;
+    parameter inv_in = 1'b0;
+    parameter inv_out = 1'b0;
+    parameter std_mode = "BYPASS";
+endmodule
diff --git a/techlibs/nanoxplore/cells_wrap_l.v b/techlibs/nanoxplore/cells_wrap_l.v
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/techlibs/nanoxplore/cells_wrap_m.v b/techlibs/nanoxplore/cells_wrap_m.v
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v
new file mode 100644
index 00000000000..e8f7936121c
--- /dev/null
+++ b/techlibs/nanoxplore/cells_wrap_u.v
@@ -0,0 +1,34 @@
+module NX_CKS_U(CKI, CMD, CKO);
+    input CKI;
+    output CKO;
+    input CMD;
+
+NX_GCK_U #(
+    .inv_in(1'b0),
+    .inv_out(1'b0),
+    .std_mode("CKS")
+) _TECHMAP_REPLACE_ (
+    .CMD(CMD),
+    .SI1(CKI),
+    .SI2(1'b0),
+    .SO(CKO)
+);
+endmodule
+
+module NX_CMUX_U(CKI0, CKI1, SEL, CKO);
+    input CKI0;
+    input CKI1;
+    output CKO;
+    input SEL;
+
+NX_GCK_U #(
+    .inv_in(1'b0),
+    .inv_out(1'b0),
+    .std_mode("MUX")
+) _TECHMAP_REPLACE_ (
+    .CMD(SEL),
+    .SI1(CKI0),
+    .SI2(CKI1),
+    .SO(CKO)
+);
+endmodule
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index 75168adcce2..2a8f48729b7 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -93,6 +93,7 @@ struct SynthNanoXplorePass : public ScriptPass
 
 	string top_opt, json_file, family;
 	bool flatten, abc9, nocy, nolutram, nobram, nodsp, iopad;
+	std::string postfix;
 
 	void clear_flags() override
 	{
@@ -106,6 +107,7 @@ struct SynthNanoXplorePass : public ScriptPass
 		nobram = false;
 		nodsp = false;
 		iopad = false;
+		postfix = "";
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -175,8 +177,20 @@ struct SynthNanoXplorePass : public ScriptPass
 		if (family.empty()) {
 			//log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n");
 			family = "ultra";
+			postfix = "_u";
 		}
 
+		if (family == "ultra") {
+			postfix = "_u";
+		} else if (family == "u300") {
+			postfix = "_u";
+		} else if (family == "medium") {
+			postfix = "_m";
+		} else if (family == "large") {
+			postfix = "_l";
+		} else 
+			log_cmd_error("Invalid NanoXplore -family setting: '%s'.\n", family.c_str());
+
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
 
@@ -192,7 +206,8 @@ struct SynthNanoXplorePass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_bb.v");
+			run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v");
+			run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 		}
 

From 815622f6853a911ce81390773a1ef2ab55117196 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 11 Mar 2024 13:58:15 +0100
Subject: [PATCH 276/499] CDC_L wrappers

---
 techlibs/nanoxplore/cells_bb.v     | 170 ---------------
 techlibs/nanoxplore/cells_bb_l.v   |  86 ++++++++
 techlibs/nanoxplore/cells_bb_m.v   |   8 +
 techlibs/nanoxplore/cells_wrap_l.v | 335 +++++++++++++++++++++++++++++
 4 files changed, 429 insertions(+), 170 deletions(-)

diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index 0ff72112153..2a3d8b62ff8 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -70,168 +70,6 @@ module NX_BFR(I, O);
     parameter ring = 0;
 endmodule
 
-(* blackbox *)
-module NX_CDC_L(CK1, CK2, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BI1, BI2, BI3, BI4, BI5, BI6, BO1
-, BO2, BO3, BO4, BO5, BO6, CI1, CI2, CI3, CI4, CI5, CI6, CO1, CO2, CO3, CO4, CO5, CO6, DI1, DI2, DI3, DI4
-, DI5, DI6, DO1, DO2, DO3, DO4, DO5, DO6);
-    input AI1;
-    input AI2;
-    input AI3;
-    input AI4;
-    input AI5;
-    input AI6;
-    output AO1;
-    output AO2;
-    output AO3;
-    output AO4;
-    output AO5;
-    output AO6;
-    input BI1;
-    input BI2;
-    input BI3;
-    input BI4;
-    input BI5;
-    input BI6;
-    output BO1;
-    output BO2;
-    output BO3;
-    output BO4;
-    output BO5;
-    output BO6;
-    input CI1;
-    input CI2;
-    input CI3;
-    input CI4;
-    input CI5;
-    input CI6;
-    input CK1;
-    input CK2;
-    output CO1;
-    output CO2;
-    output CO3;
-    output CO4;
-    output CO5;
-    output CO6;
-    input DI1;
-    input DI2;
-    input DI3;
-    input DI4;
-    input DI5;
-    input DI6;
-    output DO1;
-    output DO2;
-    output DO3;
-    output DO4;
-    output DO5;
-    output DO6;
-    parameter ack_sel = 1'b0;
-    parameter bck_sel = 1'b0;
-    parameter cck_sel = 1'b0;
-    parameter ck0_edge = 1'b0;
-    parameter ck1_edge = 1'b0;
-    parameter dck_sel = 1'b0;
-    parameter gt0_bypass_reg1 = 1'b0;
-    parameter gt0_bypass_reg2 = 1'b0;
-    parameter gt1_bypass_reg1 = 1'b0;
-    parameter gt1_bypass_reg2 = 1'b0;
-    parameter link_BA = 1'b0;
-    parameter link_CB = 1'b0;
-    parameter link_DC = 1'b0;
-    parameter mode = 0;
-    parameter use_adest_arst = 2'b00;
-    parameter use_asrc_arst = 2'b00;
-    parameter use_bdest_arst = 2'b00;
-    parameter use_bsrc_arst = 2'b00;
-    parameter use_cdest_arst = 2'b00;
-    parameter use_csrc_arst = 2'b00;
-    parameter use_ddest_arst = 2'b00;
-    parameter use_dsrc_arst = 2'b00;
-endmodule
-
-(* blackbox *)
-module NX_CDC_L_2DFF(CK1, CK2, ADRSTI, BDRSTI, BI, AO, BO, AI);
-    input ADRSTI;
-    input [5:0] AI;
-    output [5:0] AO;
-    input BDRSTI;
-    input [5:0] BI;
-    output [5:0] BO;
-    input CK1;
-    input CK2;
-    parameter ack_sel = 1'b0;
-    parameter bck_sel = 1'b0;
-    parameter ck0_edge = 1'b0;
-    parameter ck1_edge = 1'b0;
-    parameter gt0_bypass_reg1 = 1'b0;
-    parameter gt0_bypass_reg2 = 1'b0;
-    parameter gt1_bypass_reg1 = 1'b0;
-    parameter gt1_bypass_reg2 = 1'b0;
-    parameter use_adest_arst = 2'b00;
-    parameter use_bdest_arst = 2'b00;
-endmodule
-
-(* blackbox *)
-module NX_CDC_L_3DFF(CK1, CK2, ASRSTI, ADRSTI, BDRSTI, BSRSTI, BI, AO, BO, AI);
-    input ADRSTI;
-    input [5:0] AI;
-    output [5:0] AO;
-    input ASRSTI;
-    input BDRSTI;
-    input [5:0] BI;
-    output [5:0] BO;
-    input BSRSTI;
-    input CK1;
-    input CK2;
-    parameter ack_sel = 1'b0;
-    parameter bck_sel = 1'b0;
-    parameter ck0_edge = 1'b0;
-    parameter ck1_edge = 1'b0;
-    parameter gt0_bypass_reg1 = 1'b0;
-    parameter gt0_bypass_reg2 = 1'b0;
-    parameter gt1_bypass_reg1 = 1'b0;
-    parameter gt1_bypass_reg2 = 1'b0;
-    parameter use_adest_arst = 2'b00;
-    parameter use_asrc_arst = 2'b00;
-    parameter use_bdest_arst = 2'b00;
-    parameter use_bsrc_arst = 2'b00;
-endmodule
-
-(* blackbox *)
-module NX_CDC_L_BIN2GRAY(CK1, CK2, BI, AO, BO, AI);
-    input [5:0] AI;
-    output [5:0] AO;
-    input [5:0] BI;
-    output [5:0] BO;
-    input CK1;
-    input CK2;
-endmodule
-
-(* blackbox *)
-module NX_CDC_L_FULL(CK1, CK2, ASRSTI, ADRSTI, BDRSTI, BSRSTI, BI, AO, BO, AI);
-    input ADRSTI;
-    input [5:0] AI;
-    output [5:0] AO;
-    input ASRSTI;
-    input BDRSTI;
-    input [5:0] BI;
-    output [5:0] BO;
-    input BSRSTI;
-    input CK1;
-    input CK2;
-    parameter ack_sel = 1'b0;
-    parameter bck_sel = 1'b0;
-    parameter ck0_edge = 1'b0;
-    parameter ck1_edge = 1'b0;
-    parameter gt0_bypass_reg1 = 1'b0;
-    parameter gt0_bypass_reg2 = 1'b0;
-    parameter gt1_bypass_reg1 = 1'b0;
-    parameter gt1_bypass_reg2 = 1'b0;
-    parameter use_adest_arst = 2'b00;
-    parameter use_asrc_arst = 2'b00;
-    parameter use_bdest_arst = 2'b00;
-    parameter use_bsrc_arst = 2'b00;
-endmodule
-
 (* blackbox *)
 module NX_CDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BSRSTI, BDRSTI, BSRSTO
 , BDRSTO, BI1, BI2, BI3, BI4, BI5, BI6, BO1, BO2, BO3, BO4, BO5, BO6, CSRSTI, CDRSTI, CSRSTO, CDRSTO, CI1, CI2, CI3, CI4
@@ -411,14 +249,6 @@ module NX_CDC_U_GRAY2BIN(BI, AO, BO, AI);
     output [5:0] BO;
 endmodule
 
-(* blackbox *)
-module NX_CKS(CKI, CMD, CKO);
-    input CKI;
-    output CKO;
-    input CMD;
-    parameter ck_edge = 1'b0;
-endmodule
-
 (* blackbox *)
 module NX_CRX_L(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, BUF_FE_I, RST_N_I, CDR_R_I, CKG_RN_I, PLL_RN_I, TST_I1, TST_I2, TST_I3, TST_I4, LOS_O, DATA_O1, DATA_O2, DATA_O3
 , DATA_O4, DATA_O5, DATA_O6, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24
diff --git a/techlibs/nanoxplore/cells_bb_l.v b/techlibs/nanoxplore/cells_bb_l.v
index e69de29bb2d..e5a88023f8e 100644
--- a/techlibs/nanoxplore/cells_bb_l.v
+++ b/techlibs/nanoxplore/cells_bb_l.v
@@ -0,0 +1,86 @@
+(* blackbox *)
+module NX_CKS(CKI, CMD, CKO);
+    input CKI;
+    output CKO;
+    input CMD;
+    parameter ck_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_CDC_L(CK1, CK2, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BI1, BI2, BI3, BI4, BI5, BI6, BO1
+, BO2, BO3, BO4, BO5, BO6, CI1, CI2, CI3, CI4, CI5, CI6, CO1, CO2, CO3, CO4, CO5, CO6, DI1, DI2, DI3, DI4
+, DI5, DI6, DO1, DO2, DO3, DO4, DO5, DO6);
+    input AI1;
+    input AI2;
+    input AI3;
+    input AI4;
+    input AI5;
+    input AI6;
+    output AO1;
+    output AO2;
+    output AO3;
+    output AO4;
+    output AO5;
+    output AO6;
+    input BI1;
+    input BI2;
+    input BI3;
+    input BI4;
+    input BI5;
+    input BI6;
+    output BO1;
+    output BO2;
+    output BO3;
+    output BO4;
+    output BO5;
+    output BO6;
+    input CI1;
+    input CI2;
+    input CI3;
+    input CI4;
+    input CI5;
+    input CI6;
+    input CK1;
+    input CK2;
+    output CO1;
+    output CO2;
+    output CO3;
+    output CO4;
+    output CO5;
+    output CO6;
+    input DI1;
+    input DI2;
+    input DI3;
+    input DI4;
+    input DI5;
+    input DI6;
+    output DO1;
+    output DO2;
+    output DO3;
+    output DO4;
+    output DO5;
+    output DO6;
+    parameter ack_sel = 1'b0;
+    parameter bck_sel = 1'b0;
+    parameter cck_sel = 1'b0;
+    parameter ck0_edge = 1'b0;
+    parameter ck1_edge = 1'b0;
+    parameter dck_sel = 1'b0;
+    parameter gt0_bypass_reg1 = 1'b0;
+    parameter gt0_bypass_reg2 = 1'b0;
+    parameter gt1_bypass_reg1 = 1'b0;
+    parameter gt1_bypass_reg2 = 1'b0;
+    parameter link_BA = 1'b0;
+    parameter link_CB = 1'b0;
+    parameter link_DC = 1'b0;
+    parameter mode = 0;
+    parameter use_adest_arst = 2'b00;
+    parameter use_asrc_arst = 2'b00;
+    parameter use_bdest_arst = 2'b00;
+    parameter use_bsrc_arst = 2'b00;
+    parameter use_cdest_arst = 2'b00;
+    parameter use_csrc_arst = 2'b00;
+    parameter use_ddest_arst = 2'b00;
+    parameter use_dsrc_arst = 2'b00;
+endmodule
+
diff --git a/techlibs/nanoxplore/cells_bb_m.v b/techlibs/nanoxplore/cells_bb_m.v
index e69de29bb2d..85b288ea00d 100644
--- a/techlibs/nanoxplore/cells_bb_m.v
+++ b/techlibs/nanoxplore/cells_bb_m.v
@@ -0,0 +1,8 @@
+(* blackbox *)
+module NX_CKS(CKI, CMD, CKO);
+    input CKI;
+    output CKO;
+    input CMD;
+    parameter ck_edge = 1'b0;
+endmodule
+
diff --git a/techlibs/nanoxplore/cells_wrap_l.v b/techlibs/nanoxplore/cells_wrap_l.v
index e69de29bb2d..d0f5502f8c3 100644
--- a/techlibs/nanoxplore/cells_wrap_l.v
+++ b/techlibs/nanoxplore/cells_wrap_l.v
@@ -0,0 +1,335 @@
+module NX_CDC_L_2DFF(CK1, CK2, ADRSTI, BDRSTI, BI, AO, BO, AI);
+    input ADRSTI;
+    input [5:0] AI;
+    output [5:0] AO;
+    input BDRSTI;
+    input [5:0] BI;
+    output [5:0] BO;
+    input CK1;
+    input CK2;
+    parameter ack_sel = 1'b0;
+    parameter bck_sel = 1'b0;
+    parameter ck0_edge = 1'b0;
+    parameter ck1_edge = 1'b0;
+    parameter gt0_bypass_reg1 = 1'b0;
+    parameter gt0_bypass_reg2 = 1'b0;
+    parameter gt1_bypass_reg1 = 1'b0;
+    parameter gt1_bypass_reg2 = 1'b0;
+    parameter use_adest_arst = 2'b00;
+    parameter use_bdest_arst = 2'b00;
+
+  NX_CDC_L #(
+    .mode(0), // -- 0: 2DFF
+    .ck0_edge(ck0_edge),
+    .ck1_edge(ck1_edge),
+    .ack_sel(ack_sel),
+    .bck_sel(bck_sel),
+    .cck_sel(1'b0),
+    .dck_sel(1'b0),
+    .use_asrc_arst(2'b00),
+    .use_adest_arst(use_adest_arst),
+    .use_bsrc_arst(2'b00),
+    .use_bdest_arst(use_bdest_arst),
+    .use_csrc_arst(2'b00),
+    .use_cdest_arst(2'b00),
+    .use_dsrc_arst(2'b00),
+    .use_ddest_arst(2'b00),
+    .gt0_bypass_reg1(gt0_bypass_reg1),
+    .gt0_bypass_reg2(gt0_bypass_reg2),
+    .gt1_bypass_reg1(gt1_bypass_reg2),
+    .gt1_bypass_reg2(gt1_bypass_reg2),
+    .link_BA(1'b0),
+    .link_CB(1'b0),
+    .link_DC(1'b0),
+  ) _TECHMAP_REPLACE_ (
+    .CK1(CK1),
+    .CK2(CK2),
+    .AI1(AI[0]),
+    .AI2(AI[1]),
+    .AI3(AI[2]),
+    .AI4(AI[3]),
+    .AI5(AI[4]),
+    .AI6(AI[5]),
+    .AO1(AO[0]),
+    .AO2(AO[1]),
+    .AO3(AO[2]),
+    .AO4(AO[3]),
+    .AO5(AO[4]),
+    .AO6(AO[5]),
+    .BI1(BI[0]),
+    .BI2(BI[1]),
+    .BI3(BI[2]),
+    .BI4(BI[3]),
+    .BI5(BI[4]),
+    .BI6(BI[5]),
+    .BO1(BO[0]),
+    .BO2(BO[1]),
+    .BO3(BO[2]),
+    .BO4(BO[3]),
+    .BO5(BO[4]),
+    .BO6(BO[5]),
+    .CI1(1'b0),
+    .CI2(1'b0),
+    .CI3(1'b0),
+    .CI4(1'b0),
+    .CI5(1'b0),
+    .CI6(1'b0),
+    .DI1(1'b0),
+    .DI2(1'b0),
+    .DI3(1'b0),
+    .DI4(1'b0),
+    .DI5(1'b0),
+    .DI6(1'b0)
+  );
+endmodule
+
+module NX_CDC_L_3DFF(CK1, CK2, ASRSTI, ADRSTI, BDRSTI, BSRSTI, BI, AO, BO, AI);
+    input ADRSTI;
+    input [5:0] AI;
+    output [5:0] AO;
+    input ASRSTI;
+    input BDRSTI;
+    input [5:0] BI;
+    output [5:0] BO;
+    input BSRSTI;
+    input CK1;
+    input CK2;
+    parameter ack_sel = 1'b0;
+    parameter bck_sel = 1'b0;
+    parameter ck0_edge = 1'b0;
+    parameter ck1_edge = 1'b0;
+    parameter gt0_bypass_reg1 = 1'b0;
+    parameter gt0_bypass_reg2 = 1'b0;
+    parameter gt1_bypass_reg1 = 1'b0;
+    parameter gt1_bypass_reg2 = 1'b0;
+    parameter use_adest_arst = 2'b00;
+    parameter use_asrc_arst = 2'b00;
+    parameter use_bdest_arst = 2'b00;
+    parameter use_bsrc_arst = 2'b00;
+
+  NX_CDC_L #(
+    .mode(1), // -- 1: 3DFF
+    .ck0_edge(ck0_edge),
+    .ck1_edge(ck1_edge),
+    .ack_sel(ack_sel),
+    .bck_sel(bck_sel),
+    .cck_sel(1'b0),
+    .dck_sel(1'b0),
+    .use_asrc_arst(use_asrc_arst),
+    .use_adest_arst(use_adest_arst),
+    .use_bsrc_arst(use_bsrc_arst),
+    .use_bdest_arst(use_bdest_arst),
+    .use_csrc_arst(2'b00),
+    .use_cdest_arst(2'b00),
+    .use_dsrc_arst(2'b00),
+    .use_ddest_arst(2'b00),
+    .gt0_bypass_reg1(gt0_bypass_reg1),
+    .gt0_bypass_reg2(gt0_bypass_reg2),
+    .gt1_bypass_reg1(gt1_bypass_reg2),
+    .gt1_bypass_reg2(gt1_bypass_reg2),
+    .link_BA(1'b0),
+    .link_CB(1'b0),
+    .link_DC(1'b0),
+  ) _TECHMAP_REPLACE_ (
+    .CK1(CK1),
+    .CK2(CK2),
+    .AI1(AI[0]),
+    .AI2(AI[1]),
+    .AI3(AI[2]),
+    .AI4(AI[3]),
+    .AI5(AI[4]),
+    .AI6(AI[5]),
+    .AO1(AO[0]),
+    .AO2(AO[1]),
+    .AO3(AO[2]),
+    .AO4(AO[3]),
+    .AO5(AO[4]),
+    .AO6(AO[5]),
+    .BI1(BI[0]),
+    .BI2(BI[1]),
+    .BI3(BI[2]),
+    .BI4(BI[3]),
+    .BI5(BI[4]),
+    .BI6(BI[5]),
+    .BO1(BO[0]),
+    .BO2(BO[1]),
+    .BO3(BO[2]),
+    .BO4(BO[3]),
+    .BO5(BO[4]),
+    .BO6(BO[5]),
+    .CI1(1'b0),
+    .CI2(1'b0),
+    .CI3(1'b0),
+    .CI4(1'b0),
+    .CI5(1'b0),
+    .CI6(1'b0),
+    .DI1(1'b0),
+    .DI2(1'b0),
+    .DI3(1'b0),
+    .DI4(1'b0),
+    .DI5(1'b0),
+    .DI6(1'b0)
+  );
+endmodule
+
+module NX_CDC_L_FULL(CK1, CK2, ASRSTI, ADRSTI, BDRSTI, BSRSTI, BI, AO, BO, AI);
+    input ADRSTI;
+    input [5:0] AI;
+    output [5:0] AO;
+    input ASRSTI;
+    input BDRSTI;
+    input [5:0] BI;
+    output [5:0] BO;
+    input BSRSTI;
+    input CK1;
+    input CK2;
+    parameter ack_sel = 1'b0;
+    parameter bck_sel = 1'b0;
+    parameter ck0_edge = 1'b0;
+    parameter ck1_edge = 1'b0;
+    parameter gt0_bypass_reg1 = 1'b0;
+    parameter gt0_bypass_reg2 = 1'b0;
+    parameter gt1_bypass_reg1 = 1'b0;
+    parameter gt1_bypass_reg2 = 1'b0;
+    parameter use_adest_arst = 2'b00;
+    parameter use_asrc_arst = 2'b00;
+    parameter use_bdest_arst = 2'b00;
+    parameter use_bsrc_arst = 2'b00;
+
+  NX_CDC_L #(
+    .mode(2), // -- 2: B2G_3DFF_G2B
+    .ck0_edge(ck0_edge),
+    .ck1_edge(ck1_edge),
+    .ack_sel(ack_sel),
+    .bck_sel(bck_sel),
+    .cck_sel(1'b0),
+    .dck_sel(1'b0),
+    .use_asrc_arst(use_asrc_arst),
+    .use_adest_arst(use_adest_arst),
+    .use_bsrc_arst(use_bsrc_arst),
+    .use_bdest_arst(use_bdest_arst),
+    .use_csrc_arst(2'b00),
+    .use_cdest_arst(2'b00),
+    .use_dsrc_arst(2'b00),
+    .use_ddest_arst(2'b00),
+    .gt0_bypass_reg1(gt0_bypass_reg1),
+    .gt0_bypass_reg2(gt0_bypass_reg2),
+    .gt1_bypass_reg1(gt1_bypass_reg2),
+    .gt1_bypass_reg2(gt1_bypass_reg2),
+    .link_BA(1'b0),
+    .link_CB(1'b0),
+    .link_DC(1'b0),
+  ) _TECHMAP_REPLACE_ (
+    .CK1(CK1),
+    .CK2(CK2),
+    .AI1(AI[0]),
+    .AI2(AI[1]),
+    .AI3(AI[2]),
+    .AI4(AI[3]),
+    .AI5(AI[4]),
+    .AI6(AI[5]),
+    .AO1(AO[0]),
+    .AO2(AO[1]),
+    .AO3(AO[2]),
+    .AO4(AO[3]),
+    .AO5(AO[4]),
+    .AO6(AO[5]),
+    .BI1(BI[0]),
+    .BI2(BI[1]),
+    .BI3(BI[2]),
+    .BI4(BI[3]),
+    .BI5(BI[4]),
+    .BI6(BI[5]),
+    .BO1(BO[0]),
+    .BO2(BO[1]),
+    .BO3(BO[2]),
+    .BO4(BO[3]),
+    .BO5(BO[4]),
+    .BO6(BO[5]),
+    .CI1(1'b0),
+    .CI2(1'b0),
+    .CI3(1'b0),
+    .CI4(1'b0),
+    .CI5(1'b0),
+    .CI6(1'b0),
+    .DI1(1'b0),
+    .DI2(1'b0),
+    .DI3(1'b0),
+    .DI4(1'b0),
+    .DI5(1'b0),
+    .DI6(1'b0)
+  );
+endmodule
+
+module NX_CDC_L_BIN2GRAY(CK1, CK2, BI, AO, BO, AI);
+    input [5:0] AI;
+    output [5:0] AO;
+    input [5:0] BI;
+    output [5:0] BO;
+    input CK1;
+    input CK2;
+
+  NX_CDC_L #(
+    .mode(3), // -- 3: bin2gray
+    .ck0_edge(1'b0),
+    .ck1_edge(1'b0),
+    .ack_sel(1'b0),
+    .bck_sel(1'b0),
+    .cck_sel(1'b0),
+    .dck_sel(1'b0),
+    .use_asrc_arst(2'b00),
+    .use_adest_arst(2'b00),
+    .use_bsrc_arst(2'b00),
+    .use_bdest_arst(2'b00),
+    .use_csrc_arst(2'b00),
+    .use_cdest_arst(2'b00),
+    .use_dsrc_arst(2'b00),
+    .use_ddest_arst(2'b00),
+    .gt0_bypass_reg1(1'b0),
+    .gt0_bypass_reg2(1'b0),
+    .gt1_bypass_reg1(1'b0),
+    .gt1_bypass_reg2(1'b0),
+    .link_BA(1'b0),
+    .link_CB(1'b0),
+    .link_DC(1'b0),
+  ) _TECHMAP_REPLACE_ (
+    .CK1(CK1),
+    .CK2(CK2),
+    .AI1(AI[0]),
+    .AI2(AI[1]),
+    .AI3(AI[2]),
+    .AI4(AI[3]),
+    .AI5(AI[4]),
+    .AI6(AI[5]),
+    .AO1(AO[0]),
+    .AO2(AO[1]),
+    .AO3(AO[2]),
+    .AO4(AO[3]),
+    .AO5(AO[4]),
+    .AO6(AO[5]),
+    .BI1(BI[0]),
+    .BI2(BI[1]),
+    .BI3(BI[2]),
+    .BI4(BI[3]),
+    .BI5(BI[4]),
+    .BI6(BI[5]),
+    .BO1(BO[0]),
+    .BO2(BO[1]),
+    .BO3(BO[2]),
+    .BO4(BO[3]),
+    .BO5(BO[4]),
+    .BO6(BO[5]),
+    .CI1(1'b0),
+    .CI2(1'b0),
+    .CI3(1'b0),
+    .CI4(1'b0),
+    .CI5(1'b0),
+    .CI6(1'b0),
+    .DI1(1'b0),
+    .DI2(1'b0),
+    .DI3(1'b0),
+    .DI4(1'b0),
+    .DI5(1'b0),
+    .DI6(1'b0)
+  );
+endmodule

From 60611b936b5e67ad68ee07fb822f71112f85b3a0 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 11 Mar 2024 14:15:30 +0100
Subject: [PATCH 277/499] CDC_U

---
 techlibs/nanoxplore/cells_bb.v     | 179 ------------
 techlibs/nanoxplore/cells_bb_u.v   |  91 ++++++
 techlibs/nanoxplore/cells_wrap_u.v | 434 +++++++++++++++++++++++++++++
 3 files changed, 525 insertions(+), 179 deletions(-)

diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index 2a3d8b62ff8..5a2ec90f45b 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -70,185 +70,6 @@ module NX_BFR(I, O);
     parameter ring = 0;
 endmodule
 
-(* blackbox *)
-module NX_CDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BSRSTI, BDRSTI, BSRSTO
-, BDRSTO, BI1, BI2, BI3, BI4, BI5, BI6, BO1, BO2, BO3, BO4, BO5, BO6, CSRSTI, CDRSTI, CSRSTO, CDRSTO, CI1, CI2, CI3, CI4
-, CI5, CI6, CO1, CO2, CO3, CO4, CO5, CO6, DSRSTI, DDRSTI, DSRSTO, DDRSTO, DI1, DI2, DI3, DI4, DI5, DI6, DO1, DO2, DO3
-, DO4, DO5, DO6);
-    input ADRSTI;
-    output ADRSTO;
-    input AI1;
-    input AI2;
-    input AI3;
-    input AI4;
-    input AI5;
-    input AI6;
-    output AO1;
-    output AO2;
-    output AO3;
-    output AO4;
-    output AO5;
-    output AO6;
-    input ASRSTI;
-    output ASRSTO;
-    input BDRSTI;
-    output BDRSTO;
-    input BI1;
-    input BI2;
-    input BI3;
-    input BI4;
-    input BI5;
-    input BI6;
-    output BO1;
-    output BO2;
-    output BO3;
-    output BO4;
-    output BO5;
-    output BO6;
-    input BSRSTI;
-    output BSRSTO;
-    input CDRSTI;
-    output CDRSTO;
-    input CI1;
-    input CI2;
-    input CI3;
-    input CI4;
-    input CI5;
-    input CI6;
-    input CK1;
-    input CK2;
-    output CO1;
-    output CO2;
-    output CO3;
-    output CO4;
-    output CO5;
-    output CO6;
-    input CSRSTI;
-    output CSRSTO;
-    input DDRSTI;
-    output DDRSTO;
-    input DI1;
-    input DI2;
-    input DI3;
-    input DI4;
-    input DI5;
-    input DI6;
-    output DO1;
-    output DO2;
-    output DO3;
-    output DO4;
-    output DO5;
-    output DO6;
-    input DSRSTI;
-    output DSRSTO;
-    parameter ack_sel = 1'b0;
-    parameter bck_sel = 1'b0;
-    parameter cck_sel = 1'b0;
-    parameter ck0_edge = 1'b0;
-    parameter ck1_edge = 1'b0;
-    parameter dck_sel = 1'b0;
-    parameter link_BA = 1'b0;
-    parameter link_CB = 1'b0;
-    parameter link_DC = 1'b0;
-    parameter mode = 0;
-    parameter use_adest_arst = 1'b0;
-    parameter use_asrc_arst = 1'b0;
-    parameter use_bdest_arst = 1'b0;
-    parameter use_bsrc_arst = 1'b0;
-    parameter use_cdest_arst = 1'b0;
-    parameter use_csrc_arst = 1'b0;
-    parameter use_ddest_arst = 1'b0;
-    parameter use_dsrc_arst = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_CDC_U_2DFF(CK1, CK2, ADRSTI, ADRSTO, BDRSTI, BDRSTO, BI, AO, BO, AI);
-    input ADRSTI;
-    output ADRSTO;
-    input [5:0] AI;
-    output [5:0] AO;
-    input BDRSTI;
-    output BDRSTO;
-    input [5:0] BI;
-    output [5:0] BO;
-    input CK1;
-    input CK2;
-    parameter ack_sel = 1'b0;
-    parameter bck_sel = 1'b0;
-    parameter ck0_edge = 1'b0;
-    parameter ck1_edge = 1'b0;
-    parameter use_adest_arst = 1'b0;
-    parameter use_bdest_arst = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_CDC_U_3DFF(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, BI, AO, BO, AI);
-    input ADRSTI;
-    output ADRSTO;
-    input [5:0] AI;
-    output [5:0] AO;
-    input ASRSTI;
-    output ASRSTO;
-    input BDRSTI;
-    output BDRSTO;
-    input [5:0] BI;
-    output [5:0] BO;
-    input BSRSTI;
-    output BSRSTO;
-    input CK1;
-    input CK2;
-    parameter ack_sel = 1'b0;
-    parameter bck_sel = 1'b0;
-    parameter ck0_edge = 1'b0;
-    parameter ck1_edge = 1'b0;
-    parameter use_adest_arst = 1'b0;
-    parameter use_asrc_arst = 1'b0;
-    parameter use_bdest_arst = 1'b0;
-    parameter use_bsrc_arst = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_CDC_U_BIN2GRAY(BI, AO, BO, AI);
-    input [5:0] AI;
-    output [5:0] AO;
-    input [5:0] BI;
-    output [5:0] BO;
-endmodule
-
-(* blackbox *)
-module NX_CDC_U_FULL(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, BI, AO, BO, AI);
-    input ADRSTI;
-    output ADRSTO;
-    input [5:0] AI;
-    output [5:0] AO;
-    input ASRSTI;
-    output ASRSTO;
-    input BDRSTI;
-    output BDRSTO;
-    input [5:0] BI;
-    output [5:0] BO;
-    input BSRSTI;
-    output BSRSTO;
-    input CK1;
-    input CK2;
-    parameter ack_sel = 1'b0;
-    parameter bck_sel = 1'b0;
-    parameter ck0_edge = 1'b0;
-    parameter ck1_edge = 1'b0;
-    parameter use_adest_arst = 1'b0;
-    parameter use_asrc_arst = 1'b0;
-    parameter use_bdest_arst = 1'b0;
-    parameter use_bsrc_arst = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_CDC_U_GRAY2BIN(BI, AO, BO, AI);
-    input [5:0] AI;
-    output [5:0] AO;
-    input [5:0] BI;
-    output [5:0] BO;
-endmodule
-
 (* blackbox *)
 module NX_CRX_L(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, BUF_FE_I, RST_N_I, CDR_R_I, CKG_RN_I, PLL_RN_I, TST_I1, TST_I2, TST_I3, TST_I4, LOS_O, DATA_O1, DATA_O2, DATA_O3
 , DATA_O4, DATA_O5, DATA_O6, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24
diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v
index 41f8736fc00..fca409a5bcb 100644
--- a/techlibs/nanoxplore/cells_bb_u.v
+++ b/techlibs/nanoxplore/cells_bb_u.v
@@ -8,3 +8,94 @@ module NX_GCK_U(SI1, SI2, CMD, SO);
     parameter inv_out = 1'b0;
     parameter std_mode = "BYPASS";
 endmodule
+
+(* blackbox *)
+module NX_CDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BSRSTI, BDRSTI, BSRSTO
+, BDRSTO, BI1, BI2, BI3, BI4, BI5, BI6, BO1, BO2, BO3, BO4, BO5, BO6, CSRSTI, CDRSTI, CSRSTO, CDRSTO, CI1, CI2, CI3, CI4
+, CI5, CI6, CO1, CO2, CO3, CO4, CO5, CO6, DSRSTI, DDRSTI, DSRSTO, DDRSTO, DI1, DI2, DI3, DI4, DI5, DI6, DO1, DO2, DO3
+, DO4, DO5, DO6);
+    input ADRSTI;
+    output ADRSTO;
+    input AI1;
+    input AI2;
+    input AI3;
+    input AI4;
+    input AI5;
+    input AI6;
+    output AO1;
+    output AO2;
+    output AO3;
+    output AO4;
+    output AO5;
+    output AO6;
+    input ASRSTI;
+    output ASRSTO;
+    input BDRSTI;
+    output BDRSTO;
+    input BI1;
+    input BI2;
+    input BI3;
+    input BI4;
+    input BI5;
+    input BI6;
+    output BO1;
+    output BO2;
+    output BO3;
+    output BO4;
+    output BO5;
+    output BO6;
+    input BSRSTI;
+    output BSRSTO;
+    input CDRSTI;
+    output CDRSTO;
+    input CI1;
+    input CI2;
+    input CI3;
+    input CI4;
+    input CI5;
+    input CI6;
+    input CK1;
+    input CK2;
+    output CO1;
+    output CO2;
+    output CO3;
+    output CO4;
+    output CO5;
+    output CO6;
+    input CSRSTI;
+    output CSRSTO;
+    input DDRSTI;
+    output DDRSTO;
+    input DI1;
+    input DI2;
+    input DI3;
+    input DI4;
+    input DI5;
+    input DI6;
+    output DO1;
+    output DO2;
+    output DO3;
+    output DO4;
+    output DO5;
+    output DO6;
+    input DSRSTI;
+    output DSRSTO;
+    parameter ack_sel = 1'b0;
+    parameter bck_sel = 1'b0;
+    parameter cck_sel = 1'b0;
+    parameter ck0_edge = 1'b0;
+    parameter ck1_edge = 1'b0;
+    parameter dck_sel = 1'b0;
+    parameter link_BA = 1'b0;
+    parameter link_CB = 1'b0;
+    parameter link_DC = 1'b0;
+    parameter mode = 0;
+    parameter use_adest_arst = 1'b0;
+    parameter use_asrc_arst = 1'b0;
+    parameter use_bdest_arst = 1'b0;
+    parameter use_bsrc_arst = 1'b0;
+    parameter use_cdest_arst = 1'b0;
+    parameter use_csrc_arst = 1'b0;
+    parameter use_ddest_arst = 1'b0;
+    parameter use_dsrc_arst = 1'b0;
+endmodule
diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v
index e8f7936121c..ec536990620 100644
--- a/techlibs/nanoxplore/cells_wrap_u.v
+++ b/techlibs/nanoxplore/cells_wrap_u.v
@@ -32,3 +32,437 @@ NX_GCK_U #(
     .SO(CKO)
 );
 endmodule
+
+module NX_CDC_U_2DFF(CK1, CK2, ADRSTI, ADRSTO, BDRSTI, BDRSTO, BI, AO, BO, AI);
+    input ADRSTI;
+    output ADRSTO;
+    input [5:0] AI;
+    output [5:0] AO;
+    input BDRSTI;
+    output BDRSTO;
+    input [5:0] BI;
+    output [5:0] BO;
+    input CK1;
+    input CK2;
+    parameter ack_sel = 1'b0;
+    parameter bck_sel = 1'b0;
+    parameter ck0_edge = 1'b0;
+    parameter ck1_edge = 1'b0;
+    parameter use_adest_arst = 1'b0;
+    parameter use_bdest_arst = 1'b0;
+
+  NX_CDC_U #(
+    .mode(0), // -- 0: 2DFF
+    .ck0_edge(ck0_edge),
+    .ck1_edge(ck1_edge),
+    .ack_sel(ack_sel),
+    .bck_sel(bck_sel),
+    .cck_sel(1'b0),
+    .dck_sel(1'b0),
+    .use_asrc_arst(1'b0),
+    .use_adest_arst(use_adest_arst),
+    .use_bsrc_arst(1'b0),
+    .use_bdest_arst(use_bdest_arst),
+    .use_csrc_arst(1'b0),
+    .use_cdest_arst(1'b0),
+    .use_dsrc_arst(1'b0),
+    .use_ddest_arst(1'b0),
+    .link_BA(1'b0),
+    .link_CB(1'b0),
+    .link_DC(1'b0),
+  ) _TECHMAP_REPLACE_ (
+    .CK1(CK1),
+    .CK2(CK2),
+    .ASRSTI(1'b0),
+    .ADRSTI(ADRSTI),
+    .ADRSTO(ADRSTO),
+    .AI1(AI[0]),
+    .AI2(AI[1]),
+    .AI3(AI[2]),
+    .AI4(AI[3]),
+    .AI5(AI[4]),
+    .AI6(AI[5]),
+    .AO1(AO[0]),
+    .AO2(AO[1]),
+    .AO3(AO[2]),
+    .AO4(AO[3]),
+    .AO5(AO[4]),
+    .AO6(AO[5]),
+    .BSRSTI(1'b0),
+    .BDRSTI(BDRSTI),
+    .BDRSTO(BDRSTO),
+    .BI1(BI[0]),
+    .BI2(BI[1]),
+    .BI3(BI[2]),
+    .BI4(BI[3]),
+    .BI5(BI[4]),
+    .BI6(BI[5]),
+    .BO1(BO[0]),
+    .BO2(BO[1]),
+    .BO3(BO[2]),
+    .BO4(BO[3]),
+    .BO5(BO[4]),
+    .BO6(BO[5]),
+    .CSRSTI(1'b0),
+    .CDRSTI(1'b0),
+    .CI1(1'b0),
+    .CI2(1'b0),
+    .CI3(1'b0),
+    .CI4(1'b0),
+    .CI5(1'b0),
+    .CI6(1'b0),
+    .DSRSTI(1'b0),
+    .DDRSTI(1'b0),
+    .DI1(1'b0),
+    .DI2(1'b0),
+    .DI3(1'b0),
+    .DI4(1'b0),
+    .DI5(1'b0),
+    .DI6(1'b0),
+  );
+endmodule
+
+module NX_CDC_U_3DFF(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, BI, AO, BO, AI);
+    input ADRSTI;
+    output ADRSTO;
+    input [5:0] AI;
+    output [5:0] AO;
+    input ASRSTI;
+    output ASRSTO;
+    input BDRSTI;
+    output BDRSTO;
+    input [5:0] BI;
+    output [5:0] BO;
+    input BSRSTI;
+    output BSRSTO;
+    input CK1;
+    input CK2;
+    parameter ack_sel = 1'b0;
+    parameter bck_sel = 1'b0;
+    parameter ck0_edge = 1'b0;
+    parameter ck1_edge = 1'b0;
+    parameter use_adest_arst = 1'b0;
+    parameter use_asrc_arst = 1'b0;
+    parameter use_bdest_arst = 1'b0;
+    parameter use_bsrc_arst = 1'b0;
+
+  NX_CDC_U #(
+    .mode(1), // -- 1: 3DFF
+    .ck0_edge(ck0_edge),
+    .ck1_edge(ck1_edge),
+    .ack_sel(ack_sel),
+    .bck_sel(bck_sel),
+    .cck_sel(1'b0),
+    .dck_sel(1'b0),
+    .use_asrc_arst(use_asrc_arst),
+    .use_adest_arst(use_adest_arst),
+    .use_bsrc_arst(use_bsrc_arst),
+    .use_bdest_arst(use_bdest_arst),
+    .use_csrc_arst(1'b0),
+    .use_cdest_arst(1'b0),
+    .use_dsrc_arst(1'b0),
+    .use_ddest_arst(1'b0),
+    .link_BA(1'b0),
+    .link_CB(1'b0),
+    .link_DC(1'b0),
+  ) _TECHMAP_REPLACE_ (
+    .CK1(CK1),
+    .CK2(CK2),
+    .ASRSTI(ASRSTI),
+    .ADRSTI(ADRSTI),
+    .ASRSTO(ASRSTO),
+    .ADRSTO(ADRSTO),
+    .AI1(AI[0]),
+    .AI2(AI[1]),
+    .AI3(AI[2]),
+    .AI4(AI[3]),
+    .AI5(AI[4]),
+    .AI6(AI[5]),
+    .AO1(AO[0]),
+    .AO2(AO[1]),
+    .AO3(AO[2]),
+    .AO4(AO[3]),
+    .AO5(AO[4]),
+    .AO6(AO[5]),
+    .BSRSTI(BSRSTI),
+    .BDRSTI(BDRSTI),
+    .BSRSTO(BSRSTO),
+    .BDRSTO(BDRSTO),
+    .BI1(BI[0]),
+    .BI2(BI[1]),
+    .BI3(BI[2]),
+    .BI4(BI[3]),
+    .BI5(BI[4]),
+    .BI6(BI[5]),
+    .BO1(BO[0]),
+    .BO2(BO[1]),
+    .BO3(BO[2]),
+    .BO4(BO[3]),
+    .BO5(BO[4]),
+    .BO6(BO[5]),
+    .CSRSTI(1'b0),
+    .CDRSTI(1'b0),
+    .CI1(1'b0),
+    .CI2(1'b0),
+    .CI3(1'b0),
+    .CI4(1'b0),
+    .CI5(1'b0),
+    .CI6(1'b0),
+    .DSRSTI(1'b0),
+    .DDRSTI(1'b0),
+    .DI1(1'b0),
+    .DI2(1'b0),
+    .DI3(1'b0),
+    .DI4(1'b0),
+    .DI5(1'b0),
+    .DI6(1'b0),
+  );
+endmodule
+
+module NX_CDC_U_FULL(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, BI, AO, BO, AI);
+    input ADRSTI;
+    output ADRSTO;
+    input [5:0] AI;
+    output [5:0] AO;
+    input ASRSTI;
+    output ASRSTO;
+    input BDRSTI;
+    output BDRSTO;
+    input [5:0] BI;
+    output [5:0] BO;
+    input BSRSTI;
+    output BSRSTO;
+    input CK1;
+    input CK2;
+    parameter ack_sel = 1'b0;
+    parameter bck_sel = 1'b0;
+    parameter ck0_edge = 1'b0;
+    parameter ck1_edge = 1'b0;
+    parameter use_adest_arst = 1'b0;
+    parameter use_asrc_arst = 1'b0;
+    parameter use_bdest_arst = 1'b0;
+    parameter use_bsrc_arst = 1'b0;
+
+  NX_CDC_U #(
+    .mode(2), // -- 2: bin2gray + 3DFF + gray2bin
+    .ck0_edge(ck0_edge),
+    .ck1_edge(ck1_edge),
+    .ack_sel(ack_sel),
+    .bck_sel(bck_sel),
+    .cck_sel(1'b0),
+    .dck_sel(1'b0),
+    .use_asrc_arst(use_asrc_arst),
+    .use_adest_arst(use_adest_arst),
+    .use_bsrc_arst(use_bsrc_arst),
+    .use_bdest_arst(use_bdest_arst),
+    .use_csrc_arst(1'b0),
+    .use_cdest_arst(1'b0),
+    .use_dsrc_arst(1'b0),
+    .use_ddest_arst(1'b0),
+    .link_BA(1'b0),
+    .link_CB(1'b0),
+    .link_DC(1'b0),
+  ) _TECHMAP_REPLACE_ (
+    .CK1(CK1),
+    .CK2(CK2),
+    .ASRSTI(ASRSTI),
+    .ADRSTI(ADRSTI),
+    .ASRSTO(ASRSTO),
+    .ADRSTO(ADRSTO),
+    .AI1(AI[0]),
+    .AI2(AI[1]),
+    .AI3(AI[2]),
+    .AI4(AI[3]),
+    .AI5(AI[4]),
+    .AI6(AI[5]),
+    .AO1(AO[0]),
+    .AO2(AO[1]),
+    .AO3(AO[2]),
+    .AO4(AO[3]),
+    .AO5(AO[4]),
+    .AO6(AO[5]),
+    .BSRSTI(BSRSTI),
+    .BDRSTI(BDRSTI),
+    .BSRSTO(BSRSTO),
+    .BDRSTO(BDRSTO),
+    .BI1(BI[0]),
+    .BI2(BI[1]),
+    .BI3(BI[2]),
+    .BI4(BI[3]),
+    .BI5(BI[4]),
+    .BI6(BI[5]),
+    .BO1(BO[0]),
+    .BO2(BO[1]),
+    .BO3(BO[2]),
+    .BO4(BO[3]),
+    .BO5(BO[4]),
+    .BO6(BO[5]),
+    .CSRSTI(1'b0),
+    .CDRSTI(1'b0),
+    .CI1(1'b0),
+    .CI2(1'b0),
+    .CI3(1'b0),
+    .CI4(1'b0),
+    .CI5(1'b0),
+    .CI6(1'b0),
+    .DSRSTI(1'b0),
+    .DDRSTI(1'b0),
+    .DI1(1'b0),
+    .DI2(1'b0),
+    .DI3(1'b0),
+    .DI4(1'b0),
+    .DI5(1'b0),
+    .DI6(1'b0),
+  );
+endmodule
+
+module NX_CDC_U_BIN2GRAY(BI, AO, BO, AI);
+    input [5:0] AI;
+    output [5:0] AO;
+    input [5:0] BI;
+    output [5:0] BO;
+
+  NX_CDC_U #(
+    .mode(3), // -- 3: bin2gray
+    .ck0_edge(1'b0),
+    .ck1_edge(1'b0),
+    .ack_sel(1'b0),
+    .bck_sel(1'b0),
+    .cck_sel(1'b0),
+    .dck_sel(1'b0),
+    .use_asrc_arst(1'b0),
+    .use_adest_arst(1'b0),
+    .use_bsrc_arst(1'b0),
+    .use_bdest_arst(1'b0),
+    .use_csrc_arst(1'b0),
+    .use_cdest_arst(1'b0),
+    .use_dsrc_arst(1'b0),
+    .use_ddest_arst(1'b0),
+    .link_BA(1'b0),
+    .link_CB(1'b0),
+    .link_DC(1'b0),
+  ) _TECHMAP_REPLACE_ (
+    .CK1(1'b0),
+    .CK2(1'b0),
+    .ASRSTI(1'b0),
+    .ADRSTI(1'b0),
+    .AI1(AI[0]),
+    .AI2(AI[1]),
+    .AI3(AI[2]),
+    .AI4(AI[3]),
+    .AI5(AI[4]),
+    .AI6(AI[5]),
+    .AO1(AO[0]),
+    .AO2(AO[1]),
+    .AO3(AO[2]),
+    .AO4(AO[3]),
+    .AO5(AO[4]),
+    .AO6(AO[5]),
+    .BSRSTI(1'b0),
+    .BDRSTI(1'b0),
+    .BI1(BI[0]),
+    .BI2(BI[1]),
+    .BI3(BI[2]),
+    .BI4(BI[3]),
+    .BI5(BI[4]),
+    .BI6(BI[5]),
+    .BO1(BO[0]),
+    .BO2(BO[1]),
+    .BO3(BO[2]),
+    .BO4(BO[3]),
+    .BO5(BO[4]),
+    .BO6(BO[5]),
+    .CSRSTI(1'b0),
+    .CDRSTI(1'b0),
+    .CI1(1'b0),
+    .CI2(1'b0),
+    .CI3(1'b0),
+    .CI4(1'b0),
+    .CI5(1'b0),
+    .CI6(1'b0),
+    .DSRSTI(1'b0),
+    .DDRSTI(1'b0),
+    .DI1(1'b0),
+    .DI2(1'b0),
+    .DI3(1'b0),
+    .DI4(1'b0),
+    .DI5(1'b0),
+    .DI6(1'b0),
+  );
+endmodule
+
+module NX_CDC_U_GRAY2BIN(BI, AO, BO, AI);
+    input [5:0] AI;
+    output [5:0] AO;
+    input [5:0] BI;
+    output [5:0] BO;
+
+  NX_CDC_U #(
+    .mode(4), // -- 4: gray2bin
+    .ck0_edge(1'b0),
+    .ck1_edge(1'b0),
+    .ack_sel(1'b0),
+    .bck_sel(1'b0),
+    .cck_sel(1'b0),
+    .dck_sel(1'b0),
+    .use_asrc_arst(1'b0),
+    .use_adest_arst(1'b0),
+    .use_bsrc_arst(1'b0),
+    .use_bdest_arst(1'b0),
+    .use_csrc_arst(1'b0),
+    .use_cdest_arst(1'b0),
+    .use_dsrc_arst(1'b0),
+    .use_ddest_arst(1'b0),
+    .link_BA(1'b0),
+    .link_CB(1'b0),
+    .link_DC(1'b0),
+  ) _TECHMAP_REPLACE_ (
+    .CK1(1'b0),
+    .CK2(1'b0),
+    .ASRSTI(1'b0),
+    .ADRSTI(1'b0),
+    .AI1(AI[0]),
+    .AI2(AI[1]),
+    .AI3(AI[2]),
+    .AI4(AI[3]),
+    .AI5(AI[4]),
+    .AI6(AI[5]),
+    .AO1(AO[0]),
+    .AO2(AO[1]),
+    .AO3(AO[2]),
+    .AO4(AO[3]),
+    .AO5(AO[4]),
+    .AO6(AO[5]),
+    .BSRSTI(1'b0),
+    .BDRSTI(1'b0),
+    .BI1(BI[0]),
+    .BI2(BI[1]),
+    .BI3(BI[2]),
+    .BI4(BI[3]),
+    .BI5(BI[4]),
+    .BI6(BI[5]),
+    .BO1(BO[0]),
+    .BO2(BO[1]),
+    .BO3(BO[2]),
+    .BO4(BO[3]),
+    .BO5(BO[4]),
+    .BO6(BO[5]),
+    .CSRSTI(1'b0),
+    .CDRSTI(1'b0),
+    .CI1(1'b0),
+    .CI2(1'b0),
+    .CI3(1'b0),
+    .CI4(1'b0),
+    .CI5(1'b0),
+    .CI6(1'b0),
+    .DSRSTI(1'b0),
+    .DDRSTI(1'b0),
+    .DI1(1'b0),
+    .DI2(1'b0),
+    .DI3(1'b0),
+    .DI4(1'b0),
+    .DI5(1'b0),
+    .DI6(1'b0),
+  );
+endmodule
+

From ce635abc210e9cbbd0396a7fca7ce0d06f7ecbf5 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 11 Mar 2024 15:26:18 +0100
Subject: [PATCH 278/499] NX_DSP/SPLIT

---
 techlibs/nanoxplore/cells_bb.v     | 1214 ----------------------------
 techlibs/nanoxplore/cells_bb_l.v   |  385 +++++++++
 techlibs/nanoxplore/cells_bb_m.v   |  372 +++++++++
 techlibs/nanoxplore/cells_bb_u.v   |  386 +++++++++
 techlibs/nanoxplore/cells_wrap_m.v |  448 ++++++++++
 5 files changed, 1591 insertions(+), 1214 deletions(-)

diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index 5a2ec90f45b..7aa8dcfb7a7 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -853,763 +853,6 @@ module NX_DFR(I, CK, L, R, O);
     parameter ring = 0;
 endmodule
 
-(* blackbox *)
-module NX_DSP(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21
-, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18
-, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21
-, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6
-, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAO1, CAO2, CAO3, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9
-, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12
-, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15
-, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO, CO37, CO49, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11
-, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32
-, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53
-, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18
-, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39
-, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4
-, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, OVF, R, RZ, WE, Z1, Z2, Z3
-, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24
-, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45
-, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53, Z54, Z55, Z56);
-    input A1;
-    input A10;
-    input A11;
-    input A12;
-    input A13;
-    input A14;
-    input A15;
-    input A16;
-    input A17;
-    input A18;
-    input A19;
-    input A2;
-    input A20;
-    input A21;
-    input A22;
-    input A23;
-    input A24;
-    input A3;
-    input A4;
-    input A5;
-    input A6;
-    input A7;
-    input A8;
-    input A9;
-    input B1;
-    input B10;
-    input B11;
-    input B12;
-    input B13;
-    input B14;
-    input B15;
-    input B16;
-    input B17;
-    input B18;
-    input B2;
-    input B3;
-    input B4;
-    input B5;
-    input B6;
-    input B7;
-    input B8;
-    input B9;
-    input C1;
-    input C10;
-    input C11;
-    input C12;
-    input C13;
-    input C14;
-    input C15;
-    input C16;
-    input C17;
-    input C18;
-    input C19;
-    input C2;
-    input C20;
-    input C21;
-    input C22;
-    input C23;
-    input C24;
-    input C25;
-    input C26;
-    input C27;
-    input C28;
-    input C29;
-    input C3;
-    input C30;
-    input C31;
-    input C32;
-    input C33;
-    input C34;
-    input C35;
-    input C36;
-    input C4;
-    input C5;
-    input C6;
-    input C7;
-    input C8;
-    input C9;
-    input CAI1;
-    input CAI10;
-    input CAI11;
-    input CAI12;
-    input CAI13;
-    input CAI14;
-    input CAI15;
-    input CAI16;
-    input CAI17;
-    input CAI18;
-    input CAI2;
-    input CAI3;
-    input CAI4;
-    input CAI5;
-    input CAI6;
-    input CAI7;
-    input CAI8;
-    input CAI9;
-    output CAO1;
-    output CAO10;
-    output CAO11;
-    output CAO12;
-    output CAO13;
-    output CAO14;
-    output CAO15;
-    output CAO16;
-    output CAO17;
-    output CAO18;
-    output CAO2;
-    output CAO3;
-    output CAO4;
-    output CAO5;
-    output CAO6;
-    output CAO7;
-    output CAO8;
-    output CAO9;
-    input CBI1;
-    input CBI10;
-    input CBI11;
-    input CBI12;
-    input CBI13;
-    input CBI14;
-    input CBI15;
-    input CBI16;
-    input CBI17;
-    input CBI18;
-    input CBI2;
-    input CBI3;
-    input CBI4;
-    input CBI5;
-    input CBI6;
-    input CBI7;
-    input CBI8;
-    input CBI9;
-    output CBO1;
-    output CBO10;
-    output CBO11;
-    output CBO12;
-    output CBO13;
-    output CBO14;
-    output CBO15;
-    output CBO16;
-    output CBO17;
-    output CBO18;
-    output CBO2;
-    output CBO3;
-    output CBO4;
-    output CBO5;
-    output CBO6;
-    output CBO7;
-    output CBO8;
-    output CBO9;
-    input CCI;
-    output CCO;
-    input CI;
-    input CK;
-    output CO;
-    output CO37;
-    output CO49;
-    input CZI1;
-    input CZI10;
-    input CZI11;
-    input CZI12;
-    input CZI13;
-    input CZI14;
-    input CZI15;
-    input CZI16;
-    input CZI17;
-    input CZI18;
-    input CZI19;
-    input CZI2;
-    input CZI20;
-    input CZI21;
-    input CZI22;
-    input CZI23;
-    input CZI24;
-    input CZI25;
-    input CZI26;
-    input CZI27;
-    input CZI28;
-    input CZI29;
-    input CZI3;
-    input CZI30;
-    input CZI31;
-    input CZI32;
-    input CZI33;
-    input CZI34;
-    input CZI35;
-    input CZI36;
-    input CZI37;
-    input CZI38;
-    input CZI39;
-    input CZI4;
-    input CZI40;
-    input CZI41;
-    input CZI42;
-    input CZI43;
-    input CZI44;
-    input CZI45;
-    input CZI46;
-    input CZI47;
-    input CZI48;
-    input CZI49;
-    input CZI5;
-    input CZI50;
-    input CZI51;
-    input CZI52;
-    input CZI53;
-    input CZI54;
-    input CZI55;
-    input CZI56;
-    input CZI6;
-    input CZI7;
-    input CZI8;
-    input CZI9;
-    output CZO1;
-    output CZO10;
-    output CZO11;
-    output CZO12;
-    output CZO13;
-    output CZO14;
-    output CZO15;
-    output CZO16;
-    output CZO17;
-    output CZO18;
-    output CZO19;
-    output CZO2;
-    output CZO20;
-    output CZO21;
-    output CZO22;
-    output CZO23;
-    output CZO24;
-    output CZO25;
-    output CZO26;
-    output CZO27;
-    output CZO28;
-    output CZO29;
-    output CZO3;
-    output CZO30;
-    output CZO31;
-    output CZO32;
-    output CZO33;
-    output CZO34;
-    output CZO35;
-    output CZO36;
-    output CZO37;
-    output CZO38;
-    output CZO39;
-    output CZO4;
-    output CZO40;
-    output CZO41;
-    output CZO42;
-    output CZO43;
-    output CZO44;
-    output CZO45;
-    output CZO46;
-    output CZO47;
-    output CZO48;
-    output CZO49;
-    output CZO5;
-    output CZO50;
-    output CZO51;
-    output CZO52;
-    output CZO53;
-    output CZO54;
-    output CZO55;
-    output CZO56;
-    output CZO6;
-    output CZO7;
-    output CZO8;
-    output CZO9;
-    input D1;
-    input D10;
-    input D11;
-    input D12;
-    input D13;
-    input D14;
-    input D15;
-    input D16;
-    input D17;
-    input D18;
-    input D2;
-    input D3;
-    input D4;
-    input D5;
-    input D6;
-    input D7;
-    input D8;
-    input D9;
-    output OVF;
-    input R;
-    input RZ;
-    input WE;
-    output Z1;
-    output Z10;
-    output Z11;
-    output Z12;
-    output Z13;
-    output Z14;
-    output Z15;
-    output Z16;
-    output Z17;
-    output Z18;
-    output Z19;
-    output Z2;
-    output Z20;
-    output Z21;
-    output Z22;
-    output Z23;
-    output Z24;
-    output Z25;
-    output Z26;
-    output Z27;
-    output Z28;
-    output Z29;
-    output Z3;
-    output Z30;
-    output Z31;
-    output Z32;
-    output Z33;
-    output Z34;
-    output Z35;
-    output Z36;
-    output Z37;
-    output Z38;
-    output Z39;
-    output Z4;
-    output Z40;
-    output Z41;
-    output Z42;
-    output Z43;
-    output Z44;
-    output Z45;
-    output Z46;
-    output Z47;
-    output Z48;
-    output Z49;
-    output Z5;
-    output Z50;
-    output Z51;
-    output Z52;
-    output Z53;
-    output Z54;
-    output Z55;
-    output Z56;
-    output Z6;
-    output Z7;
-    output Z8;
-    output Z9;
-    parameter raw_config0 = 20'b00000000000000000000;
-    parameter raw_config1 = 19'b0000000000000000000;
-    parameter raw_config2 = 13'b0000000000000;
-    parameter raw_config3 = 7'b0000000;
-    parameter std_mode = "";
-endmodule
-
-(* blackbox *)
-module NX_DSP_L(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21
-, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18
-, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21
-, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6
-, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAI19, CAI20, CAI21, CAI22, CAI23, CAI24, CAO1, CAO2, CAO3
-, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CAO19, CAO20, CAO21, CAO22, CAO23, CAO24
-, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3
-, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO, CO37
-, CO57, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20
-, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41
-, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6
-, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27
-, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48
-, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13
-, D14, D15, D16, D17, D18, OVF, R, RZ, WE, Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11, Z12
-, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32, Z33
-, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53, Z54
-, Z55, Z56);
-    input A1;
-    input A10;
-    input A11;
-    input A12;
-    input A13;
-    input A14;
-    input A15;
-    input A16;
-    input A17;
-    input A18;
-    input A19;
-    input A2;
-    input A20;
-    input A21;
-    input A22;
-    input A23;
-    input A24;
-    input A3;
-    input A4;
-    input A5;
-    input A6;
-    input A7;
-    input A8;
-    input A9;
-    input B1;
-    input B10;
-    input B11;
-    input B12;
-    input B13;
-    input B14;
-    input B15;
-    input B16;
-    input B17;
-    input B18;
-    input B2;
-    input B3;
-    input B4;
-    input B5;
-    input B6;
-    input B7;
-    input B8;
-    input B9;
-    input C1;
-    input C10;
-    input C11;
-    input C12;
-    input C13;
-    input C14;
-    input C15;
-    input C16;
-    input C17;
-    input C18;
-    input C19;
-    input C2;
-    input C20;
-    input C21;
-    input C22;
-    input C23;
-    input C24;
-    input C25;
-    input C26;
-    input C27;
-    input C28;
-    input C29;
-    input C3;
-    input C30;
-    input C31;
-    input C32;
-    input C33;
-    input C34;
-    input C35;
-    input C36;
-    input C4;
-    input C5;
-    input C6;
-    input C7;
-    input C8;
-    input C9;
-    input CAI1;
-    input CAI10;
-    input CAI11;
-    input CAI12;
-    input CAI13;
-    input CAI14;
-    input CAI15;
-    input CAI16;
-    input CAI17;
-    input CAI18;
-    input CAI19;
-    input CAI2;
-    input CAI20;
-    input CAI21;
-    input CAI22;
-    input CAI23;
-    input CAI24;
-    input CAI3;
-    input CAI4;
-    input CAI5;
-    input CAI6;
-    input CAI7;
-    input CAI8;
-    input CAI9;
-    output CAO1;
-    output CAO10;
-    output CAO11;
-    output CAO12;
-    output CAO13;
-    output CAO14;
-    output CAO15;
-    output CAO16;
-    output CAO17;
-    output CAO18;
-    output CAO19;
-    output CAO2;
-    output CAO20;
-    output CAO21;
-    output CAO22;
-    output CAO23;
-    output CAO24;
-    output CAO3;
-    output CAO4;
-    output CAO5;
-    output CAO6;
-    output CAO7;
-    output CAO8;
-    output CAO9;
-    input CBI1;
-    input CBI10;
-    input CBI11;
-    input CBI12;
-    input CBI13;
-    input CBI14;
-    input CBI15;
-    input CBI16;
-    input CBI17;
-    input CBI18;
-    input CBI2;
-    input CBI3;
-    input CBI4;
-    input CBI5;
-    input CBI6;
-    input CBI7;
-    input CBI8;
-    input CBI9;
-    output CBO1;
-    output CBO10;
-    output CBO11;
-    output CBO12;
-    output CBO13;
-    output CBO14;
-    output CBO15;
-    output CBO16;
-    output CBO17;
-    output CBO18;
-    output CBO2;
-    output CBO3;
-    output CBO4;
-    output CBO5;
-    output CBO6;
-    output CBO7;
-    output CBO8;
-    output CBO9;
-    input CCI;
-    output CCO;
-    input CI;
-    input CK;
-    output CO;
-    output CO37;
-    output CO57;
-    input CZI1;
-    input CZI10;
-    input CZI11;
-    input CZI12;
-    input CZI13;
-    input CZI14;
-    input CZI15;
-    input CZI16;
-    input CZI17;
-    input CZI18;
-    input CZI19;
-    input CZI2;
-    input CZI20;
-    input CZI21;
-    input CZI22;
-    input CZI23;
-    input CZI24;
-    input CZI25;
-    input CZI26;
-    input CZI27;
-    input CZI28;
-    input CZI29;
-    input CZI3;
-    input CZI30;
-    input CZI31;
-    input CZI32;
-    input CZI33;
-    input CZI34;
-    input CZI35;
-    input CZI36;
-    input CZI37;
-    input CZI38;
-    input CZI39;
-    input CZI4;
-    input CZI40;
-    input CZI41;
-    input CZI42;
-    input CZI43;
-    input CZI44;
-    input CZI45;
-    input CZI46;
-    input CZI47;
-    input CZI48;
-    input CZI49;
-    input CZI5;
-    input CZI50;
-    input CZI51;
-    input CZI52;
-    input CZI53;
-    input CZI54;
-    input CZI55;
-    input CZI56;
-    input CZI6;
-    input CZI7;
-    input CZI8;
-    input CZI9;
-    output CZO1;
-    output CZO10;
-    output CZO11;
-    output CZO12;
-    output CZO13;
-    output CZO14;
-    output CZO15;
-    output CZO16;
-    output CZO17;
-    output CZO18;
-    output CZO19;
-    output CZO2;
-    output CZO20;
-    output CZO21;
-    output CZO22;
-    output CZO23;
-    output CZO24;
-    output CZO25;
-    output CZO26;
-    output CZO27;
-    output CZO28;
-    output CZO29;
-    output CZO3;
-    output CZO30;
-    output CZO31;
-    output CZO32;
-    output CZO33;
-    output CZO34;
-    output CZO35;
-    output CZO36;
-    output CZO37;
-    output CZO38;
-    output CZO39;
-    output CZO4;
-    output CZO40;
-    output CZO41;
-    output CZO42;
-    output CZO43;
-    output CZO44;
-    output CZO45;
-    output CZO46;
-    output CZO47;
-    output CZO48;
-    output CZO49;
-    output CZO5;
-    output CZO50;
-    output CZO51;
-    output CZO52;
-    output CZO53;
-    output CZO54;
-    output CZO55;
-    output CZO56;
-    output CZO6;
-    output CZO7;
-    output CZO8;
-    output CZO9;
-    input D1;
-    input D10;
-    input D11;
-    input D12;
-    input D13;
-    input D14;
-    input D15;
-    input D16;
-    input D17;
-    input D18;
-    input D2;
-    input D3;
-    input D4;
-    input D5;
-    input D6;
-    input D7;
-    input D8;
-    input D9;
-    output OVF;
-    input R;
-    input RZ;
-    input WE;
-    output Z1;
-    output Z10;
-    output Z11;
-    output Z12;
-    output Z13;
-    output Z14;
-    output Z15;
-    output Z16;
-    output Z17;
-    output Z18;
-    output Z19;
-    output Z2;
-    output Z20;
-    output Z21;
-    output Z22;
-    output Z23;
-    output Z24;
-    output Z25;
-    output Z26;
-    output Z27;
-    output Z28;
-    output Z29;
-    output Z3;
-    output Z30;
-    output Z31;
-    output Z32;
-    output Z33;
-    output Z34;
-    output Z35;
-    output Z36;
-    output Z37;
-    output Z38;
-    output Z39;
-    output Z4;
-    output Z40;
-    output Z41;
-    output Z42;
-    output Z43;
-    output Z44;
-    output Z45;
-    output Z46;
-    output Z47;
-    output Z48;
-    output Z49;
-    output Z5;
-    output Z50;
-    output Z51;
-    output Z52;
-    output Z53;
-    output Z54;
-    output Z55;
-    output Z56;
-    output Z6;
-    output Z7;
-    output Z8;
-    output Z9;
-    parameter raw_config0 = 20'b00000000000000000000;
-    parameter raw_config1 = 19'b0000000000000000000;
-    parameter raw_config2 = 13'b0000000000000;
-    parameter raw_config3 = 7'b0000000;
-    parameter std_mode = "";
-endmodule
-
 (* blackbox *)
 module NX_DSP_L_SPLIT(CK, R, RZ, WE, CI, CCI, CO, CO36, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
 , CZO);
@@ -1713,463 +956,6 @@ module NX_DSP_L_WRAP(CCI, CCO, CI, CK, CO, CO37, CO57, OVF, R, RZ, WE, A, B, C,
     parameter std_mode = "";
 endmodule
 
-(* blackbox *)
-module NX_DSP_SPLIT(CK, R, RZ, WE, CI, CCI, CO, CO36, CO48, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
-, CZO);
-    input [23:0] A;
-    input [17:0] B;
-    input [35:0] C;
-    input [17:0] CAI;
-    output [17:0] CAO;
-    input [17:0] CBI;
-    output [17:0] CBO;
-    input CCI;
-    output CCO;
-    input CI;
-    input CK;
-    output CO;
-    output CO36;
-    output CO48;
-    input [55:0] CZI;
-    output [55:0] CZO;
-    input [17:0] D;
-    output OVF;
-    input R;
-    input RZ;
-    input WE;
-    output [55:0] Z;
-    parameter ALU_DYNAMIC_OP = 1'b0;
-    parameter ALU_MUX = 1'b0;
-    parameter ALU_OP = 6'b000000;
-    parameter CO_SEL = 1'b0;
-    parameter ENABLE_PR_ALU_RST = 1'b0;
-    parameter ENABLE_PR_A_RST = 1'b0;
-    parameter ENABLE_PR_B_RST = 1'b0;
-    parameter ENABLE_PR_CI_RST = 1'b0;
-    parameter ENABLE_PR_CO_RST = 1'b0;
-    parameter ENABLE_PR_C_RST = 1'b0;
-    parameter ENABLE_PR_D_RST = 1'b0;
-    parameter ENABLE_PR_MULT_RST = 1'b0;
-    parameter ENABLE_PR_OV_RST = 1'b0;
-    parameter ENABLE_PR_P_RST = 1'b0;
-    parameter ENABLE_PR_X_RST = 1'b0;
-    parameter ENABLE_PR_Y_RST = 1'b0;
-    parameter ENABLE_PR_Z_RST = 1'b0;
-    parameter ENABLE_SATURATION = 1'b0;
-    parameter MUX_A = 1'b0;
-    parameter MUX_B = 1'b0;
-    parameter MUX_CI = 1'b0;
-    parameter MUX_P = 1'b0;
-    parameter MUX_X = 2'b00;
-    parameter MUX_Y = 1'b0;
-    parameter MUX_Z = 1'b0;
-    parameter PRE_ADDER_OP = 1'b0;
-    parameter PR_ALU_MUX = 1'b0;
-    parameter PR_A_CASCADE_MUX = 2'b00;
-    parameter PR_A_MUX = 2'b00;
-    parameter PR_B_CASCADE_MUX = 2'b00;
-    parameter PR_B_MUX = 2'b00;
-    parameter PR_CI_MUX = 1'b0;
-    parameter PR_CO_MUX = 1'b0;
-    parameter PR_C_MUX = 1'b0;
-    parameter PR_D_MUX = 1'b0;
-    parameter PR_MULT_MUX = 1'b0;
-    parameter PR_OV_MUX = 1'b0;
-    parameter PR_P_MUX = 1'b0;
-    parameter PR_X_MUX = 1'b0;
-    parameter PR_Y_MUX = 1'b0;
-    parameter PR_Z_MUX = 1'b0;
-    parameter SATURATION_RANK = 6'b000000;
-    parameter SIGNED_MODE = 1'b0;
-    parameter Z_FEEDBACK_SHL12 = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_DSP_U(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21
-, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18
-, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21
-, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6
-, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAI19, CAI20, CAI21, CAI22, CAI23, CAI24, CAO1, CAO2, CAO3
-, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CAO19, CAO20, CAO21, CAO22, CAO23, CAO24
-, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3
-, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO43, CO57
-, RESERVED, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20
-, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41
-, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6
-, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27
-, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48
-, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13
-, D14, D15, D16, D17, D18, OVF, R, RZ, WE, WEZ, Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11
-, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32
-, Z33, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53
-, Z54, Z55, Z56);
-    input A1;
-    input A10;
-    input A11;
-    input A12;
-    input A13;
-    input A14;
-    input A15;
-    input A16;
-    input A17;
-    input A18;
-    input A19;
-    input A2;
-    input A20;
-    input A21;
-    input A22;
-    input A23;
-    input A24;
-    input A3;
-    input A4;
-    input A5;
-    input A6;
-    input A7;
-    input A8;
-    input A9;
-    input B1;
-    input B10;
-    input B11;
-    input B12;
-    input B13;
-    input B14;
-    input B15;
-    input B16;
-    input B17;
-    input B18;
-    input B2;
-    input B3;
-    input B4;
-    input B5;
-    input B6;
-    input B7;
-    input B8;
-    input B9;
-    input C1;
-    input C10;
-    input C11;
-    input C12;
-    input C13;
-    input C14;
-    input C15;
-    input C16;
-    input C17;
-    input C18;
-    input C19;
-    input C2;
-    input C20;
-    input C21;
-    input C22;
-    input C23;
-    input C24;
-    input C25;
-    input C26;
-    input C27;
-    input C28;
-    input C29;
-    input C3;
-    input C30;
-    input C31;
-    input C32;
-    input C33;
-    input C34;
-    input C35;
-    input C36;
-    input C4;
-    input C5;
-    input C6;
-    input C7;
-    input C8;
-    input C9;
-    input CAI1;
-    input CAI10;
-    input CAI11;
-    input CAI12;
-    input CAI13;
-    input CAI14;
-    input CAI15;
-    input CAI16;
-    input CAI17;
-    input CAI18;
-    input CAI19;
-    input CAI2;
-    input CAI20;
-    input CAI21;
-    input CAI22;
-    input CAI23;
-    input CAI24;
-    input CAI3;
-    input CAI4;
-    input CAI5;
-    input CAI6;
-    input CAI7;
-    input CAI8;
-    input CAI9;
-    output CAO1;
-    output CAO10;
-    output CAO11;
-    output CAO12;
-    output CAO13;
-    output CAO14;
-    output CAO15;
-    output CAO16;
-    output CAO17;
-    output CAO18;
-    output CAO19;
-    output CAO2;
-    output CAO20;
-    output CAO21;
-    output CAO22;
-    output CAO23;
-    output CAO24;
-    output CAO3;
-    output CAO4;
-    output CAO5;
-    output CAO6;
-    output CAO7;
-    output CAO8;
-    output CAO9;
-    input CBI1;
-    input CBI10;
-    input CBI11;
-    input CBI12;
-    input CBI13;
-    input CBI14;
-    input CBI15;
-    input CBI16;
-    input CBI17;
-    input CBI18;
-    input CBI2;
-    input CBI3;
-    input CBI4;
-    input CBI5;
-    input CBI6;
-    input CBI7;
-    input CBI8;
-    input CBI9;
-    output CBO1;
-    output CBO10;
-    output CBO11;
-    output CBO12;
-    output CBO13;
-    output CBO14;
-    output CBO15;
-    output CBO16;
-    output CBO17;
-    output CBO18;
-    output CBO2;
-    output CBO3;
-    output CBO4;
-    output CBO5;
-    output CBO6;
-    output CBO7;
-    output CBO8;
-    output CBO9;
-    input CCI;
-    output CCO;
-    input CI;
-    input CK;
-    output CO43;
-    output CO57;
-    input CZI1;
-    input CZI10;
-    input CZI11;
-    input CZI12;
-    input CZI13;
-    input CZI14;
-    input CZI15;
-    input CZI16;
-    input CZI17;
-    input CZI18;
-    input CZI19;
-    input CZI2;
-    input CZI20;
-    input CZI21;
-    input CZI22;
-    input CZI23;
-    input CZI24;
-    input CZI25;
-    input CZI26;
-    input CZI27;
-    input CZI28;
-    input CZI29;
-    input CZI3;
-    input CZI30;
-    input CZI31;
-    input CZI32;
-    input CZI33;
-    input CZI34;
-    input CZI35;
-    input CZI36;
-    input CZI37;
-    input CZI38;
-    input CZI39;
-    input CZI4;
-    input CZI40;
-    input CZI41;
-    input CZI42;
-    input CZI43;
-    input CZI44;
-    input CZI45;
-    input CZI46;
-    input CZI47;
-    input CZI48;
-    input CZI49;
-    input CZI5;
-    input CZI50;
-    input CZI51;
-    input CZI52;
-    input CZI53;
-    input CZI54;
-    input CZI55;
-    input CZI56;
-    input CZI6;
-    input CZI7;
-    input CZI8;
-    input CZI9;
-    output CZO1;
-    output CZO10;
-    output CZO11;
-    output CZO12;
-    output CZO13;
-    output CZO14;
-    output CZO15;
-    output CZO16;
-    output CZO17;
-    output CZO18;
-    output CZO19;
-    output CZO2;
-    output CZO20;
-    output CZO21;
-    output CZO22;
-    output CZO23;
-    output CZO24;
-    output CZO25;
-    output CZO26;
-    output CZO27;
-    output CZO28;
-    output CZO29;
-    output CZO3;
-    output CZO30;
-    output CZO31;
-    output CZO32;
-    output CZO33;
-    output CZO34;
-    output CZO35;
-    output CZO36;
-    output CZO37;
-    output CZO38;
-    output CZO39;
-    output CZO4;
-    output CZO40;
-    output CZO41;
-    output CZO42;
-    output CZO43;
-    output CZO44;
-    output CZO45;
-    output CZO46;
-    output CZO47;
-    output CZO48;
-    output CZO49;
-    output CZO5;
-    output CZO50;
-    output CZO51;
-    output CZO52;
-    output CZO53;
-    output CZO54;
-    output CZO55;
-    output CZO56;
-    output CZO6;
-    output CZO7;
-    output CZO8;
-    output CZO9;
-    input D1;
-    input D10;
-    input D11;
-    input D12;
-    input D13;
-    input D14;
-    input D15;
-    input D16;
-    input D17;
-    input D18;
-    input D2;
-    input D3;
-    input D4;
-    input D5;
-    input D6;
-    input D7;
-    input D8;
-    input D9;
-    output OVF;
-    input R;
-    output RESERVED;
-    input RZ;
-    input WE;
-    input WEZ;
-    output Z1;
-    output Z10;
-    output Z11;
-    output Z12;
-    output Z13;
-    output Z14;
-    output Z15;
-    output Z16;
-    output Z17;
-    output Z18;
-    output Z19;
-    output Z2;
-    output Z20;
-    output Z21;
-    output Z22;
-    output Z23;
-    output Z24;
-    output Z25;
-    output Z26;
-    output Z27;
-    output Z28;
-    output Z29;
-    output Z3;
-    output Z30;
-    output Z31;
-    output Z32;
-    output Z33;
-    output Z34;
-    output Z35;
-    output Z36;
-    output Z37;
-    output Z38;
-    output Z39;
-    output Z4;
-    output Z40;
-    output Z41;
-    output Z42;
-    output Z43;
-    output Z44;
-    output Z45;
-    output Z46;
-    output Z47;
-    output Z48;
-    output Z49;
-    output Z5;
-    output Z50;
-    output Z51;
-    output Z52;
-    output Z53;
-    output Z54;
-    output Z55;
-    output Z56;
-    output Z6;
-    output Z7;
-    output Z8;
-    output Z9;
-    parameter raw_config0 = 27'b000000000000000000000000000;
-    parameter raw_config1 = 24'b000000000000000000000000;
-    parameter raw_config2 = 14'b00000000000000;
-    parameter raw_config3 = 3'b000;
-    parameter std_mode = "";
-endmodule
-
 (* blackbox *)
 module NX_DSP_U_SPLIT(CK, R, RZ, WE, WEZ, CI, CCI, CO42, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
 , CZO);
diff --git a/techlibs/nanoxplore/cells_bb_l.v b/techlibs/nanoxplore/cells_bb_l.v
index e5a88023f8e..a3a11a06c14 100644
--- a/techlibs/nanoxplore/cells_bb_l.v
+++ b/techlibs/nanoxplore/cells_bb_l.v
@@ -84,3 +84,388 @@ module NX_CDC_L(CK1, CK2, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5,
     parameter use_dsrc_arst = 2'b00;
 endmodule
 
+(* blackbox *)
+module NX_DSP_L(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21
+, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18
+, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21
+, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6
+, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAI19, CAI20, CAI21, CAI22, CAI23, CAI24, CAO1, CAO2, CAO3
+, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CAO19, CAO20, CAO21, CAO22, CAO23, CAO24
+, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3
+, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO, CO37
+, CO57, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20
+, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41
+, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6
+, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27
+, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48
+, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13
+, D14, D15, D16, D17, D18, OVF, R, RZ, WE, Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11, Z12
+, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32, Z33
+, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53, Z54
+, Z55, Z56);
+    input A1;
+    input A10;
+    input A11;
+    input A12;
+    input A13;
+    input A14;
+    input A15;
+    input A16;
+    input A17;
+    input A18;
+    input A19;
+    input A2;
+    input A20;
+    input A21;
+    input A22;
+    input A23;
+    input A24;
+    input A3;
+    input A4;
+    input A5;
+    input A6;
+    input A7;
+    input A8;
+    input A9;
+    input B1;
+    input B10;
+    input B11;
+    input B12;
+    input B13;
+    input B14;
+    input B15;
+    input B16;
+    input B17;
+    input B18;
+    input B2;
+    input B3;
+    input B4;
+    input B5;
+    input B6;
+    input B7;
+    input B8;
+    input B9;
+    input C1;
+    input C10;
+    input C11;
+    input C12;
+    input C13;
+    input C14;
+    input C15;
+    input C16;
+    input C17;
+    input C18;
+    input C19;
+    input C2;
+    input C20;
+    input C21;
+    input C22;
+    input C23;
+    input C24;
+    input C25;
+    input C26;
+    input C27;
+    input C28;
+    input C29;
+    input C3;
+    input C30;
+    input C31;
+    input C32;
+    input C33;
+    input C34;
+    input C35;
+    input C36;
+    input C4;
+    input C5;
+    input C6;
+    input C7;
+    input C8;
+    input C9;
+    input CAI1;
+    input CAI10;
+    input CAI11;
+    input CAI12;
+    input CAI13;
+    input CAI14;
+    input CAI15;
+    input CAI16;
+    input CAI17;
+    input CAI18;
+    input CAI19;
+    input CAI2;
+    input CAI20;
+    input CAI21;
+    input CAI22;
+    input CAI23;
+    input CAI24;
+    input CAI3;
+    input CAI4;
+    input CAI5;
+    input CAI6;
+    input CAI7;
+    input CAI8;
+    input CAI9;
+    output CAO1;
+    output CAO10;
+    output CAO11;
+    output CAO12;
+    output CAO13;
+    output CAO14;
+    output CAO15;
+    output CAO16;
+    output CAO17;
+    output CAO18;
+    output CAO19;
+    output CAO2;
+    output CAO20;
+    output CAO21;
+    output CAO22;
+    output CAO23;
+    output CAO24;
+    output CAO3;
+    output CAO4;
+    output CAO5;
+    output CAO6;
+    output CAO7;
+    output CAO8;
+    output CAO9;
+    input CBI1;
+    input CBI10;
+    input CBI11;
+    input CBI12;
+    input CBI13;
+    input CBI14;
+    input CBI15;
+    input CBI16;
+    input CBI17;
+    input CBI18;
+    input CBI2;
+    input CBI3;
+    input CBI4;
+    input CBI5;
+    input CBI6;
+    input CBI7;
+    input CBI8;
+    input CBI9;
+    output CBO1;
+    output CBO10;
+    output CBO11;
+    output CBO12;
+    output CBO13;
+    output CBO14;
+    output CBO15;
+    output CBO16;
+    output CBO17;
+    output CBO18;
+    output CBO2;
+    output CBO3;
+    output CBO4;
+    output CBO5;
+    output CBO6;
+    output CBO7;
+    output CBO8;
+    output CBO9;
+    input CCI;
+    output CCO;
+    input CI;
+    input CK;
+    output CO;
+    output CO37;
+    output CO57;
+    input CZI1;
+    input CZI10;
+    input CZI11;
+    input CZI12;
+    input CZI13;
+    input CZI14;
+    input CZI15;
+    input CZI16;
+    input CZI17;
+    input CZI18;
+    input CZI19;
+    input CZI2;
+    input CZI20;
+    input CZI21;
+    input CZI22;
+    input CZI23;
+    input CZI24;
+    input CZI25;
+    input CZI26;
+    input CZI27;
+    input CZI28;
+    input CZI29;
+    input CZI3;
+    input CZI30;
+    input CZI31;
+    input CZI32;
+    input CZI33;
+    input CZI34;
+    input CZI35;
+    input CZI36;
+    input CZI37;
+    input CZI38;
+    input CZI39;
+    input CZI4;
+    input CZI40;
+    input CZI41;
+    input CZI42;
+    input CZI43;
+    input CZI44;
+    input CZI45;
+    input CZI46;
+    input CZI47;
+    input CZI48;
+    input CZI49;
+    input CZI5;
+    input CZI50;
+    input CZI51;
+    input CZI52;
+    input CZI53;
+    input CZI54;
+    input CZI55;
+    input CZI56;
+    input CZI6;
+    input CZI7;
+    input CZI8;
+    input CZI9;
+    output CZO1;
+    output CZO10;
+    output CZO11;
+    output CZO12;
+    output CZO13;
+    output CZO14;
+    output CZO15;
+    output CZO16;
+    output CZO17;
+    output CZO18;
+    output CZO19;
+    output CZO2;
+    output CZO20;
+    output CZO21;
+    output CZO22;
+    output CZO23;
+    output CZO24;
+    output CZO25;
+    output CZO26;
+    output CZO27;
+    output CZO28;
+    output CZO29;
+    output CZO3;
+    output CZO30;
+    output CZO31;
+    output CZO32;
+    output CZO33;
+    output CZO34;
+    output CZO35;
+    output CZO36;
+    output CZO37;
+    output CZO38;
+    output CZO39;
+    output CZO4;
+    output CZO40;
+    output CZO41;
+    output CZO42;
+    output CZO43;
+    output CZO44;
+    output CZO45;
+    output CZO46;
+    output CZO47;
+    output CZO48;
+    output CZO49;
+    output CZO5;
+    output CZO50;
+    output CZO51;
+    output CZO52;
+    output CZO53;
+    output CZO54;
+    output CZO55;
+    output CZO56;
+    output CZO6;
+    output CZO7;
+    output CZO8;
+    output CZO9;
+    input D1;
+    input D10;
+    input D11;
+    input D12;
+    input D13;
+    input D14;
+    input D15;
+    input D16;
+    input D17;
+    input D18;
+    input D2;
+    input D3;
+    input D4;
+    input D5;
+    input D6;
+    input D7;
+    input D8;
+    input D9;
+    output OVF;
+    input R;
+    input RZ;
+    input WE;
+    output Z1;
+    output Z10;
+    output Z11;
+    output Z12;
+    output Z13;
+    output Z14;
+    output Z15;
+    output Z16;
+    output Z17;
+    output Z18;
+    output Z19;
+    output Z2;
+    output Z20;
+    output Z21;
+    output Z22;
+    output Z23;
+    output Z24;
+    output Z25;
+    output Z26;
+    output Z27;
+    output Z28;
+    output Z29;
+    output Z3;
+    output Z30;
+    output Z31;
+    output Z32;
+    output Z33;
+    output Z34;
+    output Z35;
+    output Z36;
+    output Z37;
+    output Z38;
+    output Z39;
+    output Z4;
+    output Z40;
+    output Z41;
+    output Z42;
+    output Z43;
+    output Z44;
+    output Z45;
+    output Z46;
+    output Z47;
+    output Z48;
+    output Z49;
+    output Z5;
+    output Z50;
+    output Z51;
+    output Z52;
+    output Z53;
+    output Z54;
+    output Z55;
+    output Z56;
+    output Z6;
+    output Z7;
+    output Z8;
+    output Z9;
+    parameter raw_config0 = 20'b00000000000000000000;
+    parameter raw_config1 = 19'b0000000000000000000;
+    parameter raw_config2 = 13'b0000000000000;
+    parameter raw_config3 = 7'b0000000;
+    parameter std_mode = "";
+endmodule
+
diff --git a/techlibs/nanoxplore/cells_bb_m.v b/techlibs/nanoxplore/cells_bb_m.v
index 85b288ea00d..e54c1fd8ac4 100644
--- a/techlibs/nanoxplore/cells_bb_m.v
+++ b/techlibs/nanoxplore/cells_bb_m.v
@@ -6,3 +6,375 @@ module NX_CKS(CKI, CMD, CKO);
     parameter ck_edge = 1'b0;
 endmodule
 
+(* blackbox *)
+module NX_DSP(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21
+, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18
+, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21
+, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6
+, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAO1, CAO2, CAO3, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9
+, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12
+, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15
+, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO, CO37, CO49, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11
+, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32
+, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53
+, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18
+, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39
+, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4
+, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, OVF, R, RZ, WE, Z1, Z2, Z3
+, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24
+, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45
+, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53, Z54, Z55, Z56);
+    input A1;
+    input A10;
+    input A11;
+    input A12;
+    input A13;
+    input A14;
+    input A15;
+    input A16;
+    input A17;
+    input A18;
+    input A19;
+    input A2;
+    input A20;
+    input A21;
+    input A22;
+    input A23;
+    input A24;
+    input A3;
+    input A4;
+    input A5;
+    input A6;
+    input A7;
+    input A8;
+    input A9;
+    input B1;
+    input B10;
+    input B11;
+    input B12;
+    input B13;
+    input B14;
+    input B15;
+    input B16;
+    input B17;
+    input B18;
+    input B2;
+    input B3;
+    input B4;
+    input B5;
+    input B6;
+    input B7;
+    input B8;
+    input B9;
+    input C1;
+    input C10;
+    input C11;
+    input C12;
+    input C13;
+    input C14;
+    input C15;
+    input C16;
+    input C17;
+    input C18;
+    input C19;
+    input C2;
+    input C20;
+    input C21;
+    input C22;
+    input C23;
+    input C24;
+    input C25;
+    input C26;
+    input C27;
+    input C28;
+    input C29;
+    input C3;
+    input C30;
+    input C31;
+    input C32;
+    input C33;
+    input C34;
+    input C35;
+    input C36;
+    input C4;
+    input C5;
+    input C6;
+    input C7;
+    input C8;
+    input C9;
+    input CAI1;
+    input CAI10;
+    input CAI11;
+    input CAI12;
+    input CAI13;
+    input CAI14;
+    input CAI15;
+    input CAI16;
+    input CAI17;
+    input CAI18;
+    input CAI2;
+    input CAI3;
+    input CAI4;
+    input CAI5;
+    input CAI6;
+    input CAI7;
+    input CAI8;
+    input CAI9;
+    output CAO1;
+    output CAO10;
+    output CAO11;
+    output CAO12;
+    output CAO13;
+    output CAO14;
+    output CAO15;
+    output CAO16;
+    output CAO17;
+    output CAO18;
+    output CAO2;
+    output CAO3;
+    output CAO4;
+    output CAO5;
+    output CAO6;
+    output CAO7;
+    output CAO8;
+    output CAO9;
+    input CBI1;
+    input CBI10;
+    input CBI11;
+    input CBI12;
+    input CBI13;
+    input CBI14;
+    input CBI15;
+    input CBI16;
+    input CBI17;
+    input CBI18;
+    input CBI2;
+    input CBI3;
+    input CBI4;
+    input CBI5;
+    input CBI6;
+    input CBI7;
+    input CBI8;
+    input CBI9;
+    output CBO1;
+    output CBO10;
+    output CBO11;
+    output CBO12;
+    output CBO13;
+    output CBO14;
+    output CBO15;
+    output CBO16;
+    output CBO17;
+    output CBO18;
+    output CBO2;
+    output CBO3;
+    output CBO4;
+    output CBO5;
+    output CBO6;
+    output CBO7;
+    output CBO8;
+    output CBO9;
+    input CCI;
+    output CCO;
+    input CI;
+    input CK;
+    output CO;
+    output CO37;
+    output CO49;
+    input CZI1;
+    input CZI10;
+    input CZI11;
+    input CZI12;
+    input CZI13;
+    input CZI14;
+    input CZI15;
+    input CZI16;
+    input CZI17;
+    input CZI18;
+    input CZI19;
+    input CZI2;
+    input CZI20;
+    input CZI21;
+    input CZI22;
+    input CZI23;
+    input CZI24;
+    input CZI25;
+    input CZI26;
+    input CZI27;
+    input CZI28;
+    input CZI29;
+    input CZI3;
+    input CZI30;
+    input CZI31;
+    input CZI32;
+    input CZI33;
+    input CZI34;
+    input CZI35;
+    input CZI36;
+    input CZI37;
+    input CZI38;
+    input CZI39;
+    input CZI4;
+    input CZI40;
+    input CZI41;
+    input CZI42;
+    input CZI43;
+    input CZI44;
+    input CZI45;
+    input CZI46;
+    input CZI47;
+    input CZI48;
+    input CZI49;
+    input CZI5;
+    input CZI50;
+    input CZI51;
+    input CZI52;
+    input CZI53;
+    input CZI54;
+    input CZI55;
+    input CZI56;
+    input CZI6;
+    input CZI7;
+    input CZI8;
+    input CZI9;
+    output CZO1;
+    output CZO10;
+    output CZO11;
+    output CZO12;
+    output CZO13;
+    output CZO14;
+    output CZO15;
+    output CZO16;
+    output CZO17;
+    output CZO18;
+    output CZO19;
+    output CZO2;
+    output CZO20;
+    output CZO21;
+    output CZO22;
+    output CZO23;
+    output CZO24;
+    output CZO25;
+    output CZO26;
+    output CZO27;
+    output CZO28;
+    output CZO29;
+    output CZO3;
+    output CZO30;
+    output CZO31;
+    output CZO32;
+    output CZO33;
+    output CZO34;
+    output CZO35;
+    output CZO36;
+    output CZO37;
+    output CZO38;
+    output CZO39;
+    output CZO4;
+    output CZO40;
+    output CZO41;
+    output CZO42;
+    output CZO43;
+    output CZO44;
+    output CZO45;
+    output CZO46;
+    output CZO47;
+    output CZO48;
+    output CZO49;
+    output CZO5;
+    output CZO50;
+    output CZO51;
+    output CZO52;
+    output CZO53;
+    output CZO54;
+    output CZO55;
+    output CZO56;
+    output CZO6;
+    output CZO7;
+    output CZO8;
+    output CZO9;
+    input D1;
+    input D10;
+    input D11;
+    input D12;
+    input D13;
+    input D14;
+    input D15;
+    input D16;
+    input D17;
+    input D18;
+    input D2;
+    input D3;
+    input D4;
+    input D5;
+    input D6;
+    input D7;
+    input D8;
+    input D9;
+    output OVF;
+    input R;
+    input RZ;
+    input WE;
+    output Z1;
+    output Z10;
+    output Z11;
+    output Z12;
+    output Z13;
+    output Z14;
+    output Z15;
+    output Z16;
+    output Z17;
+    output Z18;
+    output Z19;
+    output Z2;
+    output Z20;
+    output Z21;
+    output Z22;
+    output Z23;
+    output Z24;
+    output Z25;
+    output Z26;
+    output Z27;
+    output Z28;
+    output Z29;
+    output Z3;
+    output Z30;
+    output Z31;
+    output Z32;
+    output Z33;
+    output Z34;
+    output Z35;
+    output Z36;
+    output Z37;
+    output Z38;
+    output Z39;
+    output Z4;
+    output Z40;
+    output Z41;
+    output Z42;
+    output Z43;
+    output Z44;
+    output Z45;
+    output Z46;
+    output Z47;
+    output Z48;
+    output Z49;
+    output Z5;
+    output Z50;
+    output Z51;
+    output Z52;
+    output Z53;
+    output Z54;
+    output Z55;
+    output Z56;
+    output Z6;
+    output Z7;
+    output Z8;
+    output Z9;
+    parameter raw_config0 = 20'b00000000000000000000;
+    parameter raw_config1 = 19'b0000000000000000000;
+    parameter raw_config2 = 13'b0000000000000;
+    parameter raw_config3 = 7'b0000000;
+    parameter std_mode = "";
+endmodule
+
diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v
index fca409a5bcb..657cd6667e4 100644
--- a/techlibs/nanoxplore/cells_bb_u.v
+++ b/techlibs/nanoxplore/cells_bb_u.v
@@ -99,3 +99,389 @@ module NX_CDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, AI1, AI2, AI3, AI4, AI
     parameter use_ddest_arst = 1'b0;
     parameter use_dsrc_arst = 1'b0;
 endmodule
+
+(* blackbox *)
+module NX_DSP_U(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21
+, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18
+, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21
+, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6
+, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAI19, CAI20, CAI21, CAI22, CAI23, CAI24, CAO1, CAO2, CAO3
+, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CAO19, CAO20, CAO21, CAO22, CAO23, CAO24
+, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3
+, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO43, CO57
+, RESERVED, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20
+, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41
+, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6
+, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27
+, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48
+, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13
+, D14, D15, D16, D17, D18, OVF, R, RZ, WE, WEZ, Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11
+, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32
+, Z33, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53
+, Z54, Z55, Z56);
+    input A1;
+    input A10;
+    input A11;
+    input A12;
+    input A13;
+    input A14;
+    input A15;
+    input A16;
+    input A17;
+    input A18;
+    input A19;
+    input A2;
+    input A20;
+    input A21;
+    input A22;
+    input A23;
+    input A24;
+    input A3;
+    input A4;
+    input A5;
+    input A6;
+    input A7;
+    input A8;
+    input A9;
+    input B1;
+    input B10;
+    input B11;
+    input B12;
+    input B13;
+    input B14;
+    input B15;
+    input B16;
+    input B17;
+    input B18;
+    input B2;
+    input B3;
+    input B4;
+    input B5;
+    input B6;
+    input B7;
+    input B8;
+    input B9;
+    input C1;
+    input C10;
+    input C11;
+    input C12;
+    input C13;
+    input C14;
+    input C15;
+    input C16;
+    input C17;
+    input C18;
+    input C19;
+    input C2;
+    input C20;
+    input C21;
+    input C22;
+    input C23;
+    input C24;
+    input C25;
+    input C26;
+    input C27;
+    input C28;
+    input C29;
+    input C3;
+    input C30;
+    input C31;
+    input C32;
+    input C33;
+    input C34;
+    input C35;
+    input C36;
+    input C4;
+    input C5;
+    input C6;
+    input C7;
+    input C8;
+    input C9;
+    input CAI1;
+    input CAI10;
+    input CAI11;
+    input CAI12;
+    input CAI13;
+    input CAI14;
+    input CAI15;
+    input CAI16;
+    input CAI17;
+    input CAI18;
+    input CAI19;
+    input CAI2;
+    input CAI20;
+    input CAI21;
+    input CAI22;
+    input CAI23;
+    input CAI24;
+    input CAI3;
+    input CAI4;
+    input CAI5;
+    input CAI6;
+    input CAI7;
+    input CAI8;
+    input CAI9;
+    output CAO1;
+    output CAO10;
+    output CAO11;
+    output CAO12;
+    output CAO13;
+    output CAO14;
+    output CAO15;
+    output CAO16;
+    output CAO17;
+    output CAO18;
+    output CAO19;
+    output CAO2;
+    output CAO20;
+    output CAO21;
+    output CAO22;
+    output CAO23;
+    output CAO24;
+    output CAO3;
+    output CAO4;
+    output CAO5;
+    output CAO6;
+    output CAO7;
+    output CAO8;
+    output CAO9;
+    input CBI1;
+    input CBI10;
+    input CBI11;
+    input CBI12;
+    input CBI13;
+    input CBI14;
+    input CBI15;
+    input CBI16;
+    input CBI17;
+    input CBI18;
+    input CBI2;
+    input CBI3;
+    input CBI4;
+    input CBI5;
+    input CBI6;
+    input CBI7;
+    input CBI8;
+    input CBI9;
+    output CBO1;
+    output CBO10;
+    output CBO11;
+    output CBO12;
+    output CBO13;
+    output CBO14;
+    output CBO15;
+    output CBO16;
+    output CBO17;
+    output CBO18;
+    output CBO2;
+    output CBO3;
+    output CBO4;
+    output CBO5;
+    output CBO6;
+    output CBO7;
+    output CBO8;
+    output CBO9;
+    input CCI;
+    output CCO;
+    input CI;
+    input CK;
+    output CO43;
+    output CO57;
+    input CZI1;
+    input CZI10;
+    input CZI11;
+    input CZI12;
+    input CZI13;
+    input CZI14;
+    input CZI15;
+    input CZI16;
+    input CZI17;
+    input CZI18;
+    input CZI19;
+    input CZI2;
+    input CZI20;
+    input CZI21;
+    input CZI22;
+    input CZI23;
+    input CZI24;
+    input CZI25;
+    input CZI26;
+    input CZI27;
+    input CZI28;
+    input CZI29;
+    input CZI3;
+    input CZI30;
+    input CZI31;
+    input CZI32;
+    input CZI33;
+    input CZI34;
+    input CZI35;
+    input CZI36;
+    input CZI37;
+    input CZI38;
+    input CZI39;
+    input CZI4;
+    input CZI40;
+    input CZI41;
+    input CZI42;
+    input CZI43;
+    input CZI44;
+    input CZI45;
+    input CZI46;
+    input CZI47;
+    input CZI48;
+    input CZI49;
+    input CZI5;
+    input CZI50;
+    input CZI51;
+    input CZI52;
+    input CZI53;
+    input CZI54;
+    input CZI55;
+    input CZI56;
+    input CZI6;
+    input CZI7;
+    input CZI8;
+    input CZI9;
+    output CZO1;
+    output CZO10;
+    output CZO11;
+    output CZO12;
+    output CZO13;
+    output CZO14;
+    output CZO15;
+    output CZO16;
+    output CZO17;
+    output CZO18;
+    output CZO19;
+    output CZO2;
+    output CZO20;
+    output CZO21;
+    output CZO22;
+    output CZO23;
+    output CZO24;
+    output CZO25;
+    output CZO26;
+    output CZO27;
+    output CZO28;
+    output CZO29;
+    output CZO3;
+    output CZO30;
+    output CZO31;
+    output CZO32;
+    output CZO33;
+    output CZO34;
+    output CZO35;
+    output CZO36;
+    output CZO37;
+    output CZO38;
+    output CZO39;
+    output CZO4;
+    output CZO40;
+    output CZO41;
+    output CZO42;
+    output CZO43;
+    output CZO44;
+    output CZO45;
+    output CZO46;
+    output CZO47;
+    output CZO48;
+    output CZO49;
+    output CZO5;
+    output CZO50;
+    output CZO51;
+    output CZO52;
+    output CZO53;
+    output CZO54;
+    output CZO55;
+    output CZO56;
+    output CZO6;
+    output CZO7;
+    output CZO8;
+    output CZO9;
+    input D1;
+    input D10;
+    input D11;
+    input D12;
+    input D13;
+    input D14;
+    input D15;
+    input D16;
+    input D17;
+    input D18;
+    input D2;
+    input D3;
+    input D4;
+    input D5;
+    input D6;
+    input D7;
+    input D8;
+    input D9;
+    output OVF;
+    input R;
+    output RESERVED;
+    input RZ;
+    input WE;
+    input WEZ;
+    output Z1;
+    output Z10;
+    output Z11;
+    output Z12;
+    output Z13;
+    output Z14;
+    output Z15;
+    output Z16;
+    output Z17;
+    output Z18;
+    output Z19;
+    output Z2;
+    output Z20;
+    output Z21;
+    output Z22;
+    output Z23;
+    output Z24;
+    output Z25;
+    output Z26;
+    output Z27;
+    output Z28;
+    output Z29;
+    output Z3;
+    output Z30;
+    output Z31;
+    output Z32;
+    output Z33;
+    output Z34;
+    output Z35;
+    output Z36;
+    output Z37;
+    output Z38;
+    output Z39;
+    output Z4;
+    output Z40;
+    output Z41;
+    output Z42;
+    output Z43;
+    output Z44;
+    output Z45;
+    output Z46;
+    output Z47;
+    output Z48;
+    output Z49;
+    output Z5;
+    output Z50;
+    output Z51;
+    output Z52;
+    output Z53;
+    output Z54;
+    output Z55;
+    output Z56;
+    output Z6;
+    output Z7;
+    output Z8;
+    output Z9;
+    parameter raw_config0 = 27'b000000000000000000000000000;
+    parameter raw_config1 = 24'b000000000000000000000000;
+    parameter raw_config2 = 14'b00000000000000;
+    parameter raw_config3 = 3'b000;
+    parameter std_mode = "";
+endmodule
diff --git a/techlibs/nanoxplore/cells_wrap_m.v b/techlibs/nanoxplore/cells_wrap_m.v
index e69de29bb2d..04c9cd66735 100644
--- a/techlibs/nanoxplore/cells_wrap_m.v
+++ b/techlibs/nanoxplore/cells_wrap_m.v
@@ -0,0 +1,448 @@
+module NX_DSP_SPLIT(CK, R, RZ, WE, CI, CCI, CO, CO36, CO48, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO , CZO);
+    input [23:0] A;
+    input [17:0] B;
+    input [35:0] C;
+    input [17:0] CAI;
+    output [17:0] CAO;
+    input [17:0] CBI;
+    output [17:0] CBO;
+    input CCI;
+    output CCO;
+    input CI;
+    input CK;
+    output CO;
+    output CO36;
+    output CO48;
+    input [55:0] CZI;
+    output [55:0] CZO;
+    input [17:0] D;
+    output OVF;
+    input R;
+    input RZ;
+    input WE;
+    output [55:0] Z;
+    parameter ALU_DYNAMIC_OP = 1'b0;
+    parameter ALU_MUX = 1'b0;
+    parameter ALU_OP = 6'b000000;
+    parameter CO_SEL = 1'b0;
+    parameter ENABLE_PR_ALU_RST = 1'b0;
+    parameter ENABLE_PR_A_RST = 1'b0;
+    parameter ENABLE_PR_B_RST = 1'b0;
+    parameter ENABLE_PR_CI_RST = 1'b0;
+    parameter ENABLE_PR_CO_RST = 1'b0;
+    parameter ENABLE_PR_C_RST = 1'b0;
+    parameter ENABLE_PR_D_RST = 1'b0;
+    parameter ENABLE_PR_MULT_RST = 1'b0;
+    parameter ENABLE_PR_OV_RST = 1'b0;
+    parameter ENABLE_PR_P_RST = 1'b0;
+    parameter ENABLE_PR_X_RST = 1'b0;
+    parameter ENABLE_PR_Y_RST = 1'b0;
+    parameter ENABLE_PR_Z_RST = 1'b0;
+    parameter ENABLE_SATURATION = 1'b0;
+    parameter MUX_A = 1'b0;
+    parameter MUX_B = 1'b0;
+    parameter MUX_CI = 1'b0;
+    parameter MUX_P = 1'b0;
+    parameter MUX_X = 2'b00;
+    parameter MUX_Y = 1'b0;
+    parameter MUX_Z = 1'b0;
+    parameter PRE_ADDER_OP = 1'b0;
+    parameter PR_ALU_MUX = 1'b0;
+    parameter PR_A_CASCADE_MUX = 2'b00;
+    parameter PR_A_MUX = 2'b00;
+    parameter PR_B_CASCADE_MUX = 2'b00;
+    parameter PR_B_MUX = 2'b00;
+    parameter PR_CI_MUX = 1'b0;
+    parameter PR_CO_MUX = 1'b0;
+    parameter PR_C_MUX = 1'b0;
+    parameter PR_D_MUX = 1'b0;
+    parameter PR_MULT_MUX = 1'b0;
+    parameter PR_OV_MUX = 1'b0;
+    parameter PR_P_MUX = 1'b0;
+    parameter PR_X_MUX = 1'b0;
+    parameter PR_Y_MUX = 1'b0;
+    parameter PR_Z_MUX = 1'b0;
+    parameter SATURATION_RANK = 6'b000000;
+    parameter SIGNED_MODE = 1'b0;
+    parameter Z_FEEDBACK_SHL12 = 1'b0;
+
+localparam RAW_CONFIG0_GEN = { CO_SEL, ALU_DYNAMIC_OP, SATURATION_RANK, ENABLE_SATURATION, Z_FEEDBACK_SHL12, MUX_Z,
+       MUX_CI, MUX_Y, MUX_X, MUX_P, MUX_B, MUX_A, PRE_ADDER_OP, SIGNED_MODE };
+
+localparam RAW_CONFIG1_GEN = { PR_OV_MUX, PR_CO_MUX, PR_Z_MUX, PR_ALU_MUX, PR_MULT_MUX, PR_Y_MUX, PR_X_MUX,
+       PR_P_MUX, PR_CI_MUX, PR_D_MUX, PR_C_MUX, PR_B_CASCADE_MUX, PR_B_MUX, PR_A_CASCADE_MUX, PR_A_MUX };
+
+localparam RAW_CONFIG2_GEN = { ENABLE_PR_OV_RST, ENABLE_PR_CO_RST, ENABLE_PR_Z_RST, ENABLE_PR_ALU_RST,
+       ENABLE_PR_MULT_RST, ENABLE_PR_Y_RST, ENABLE_PR_X_RST, ENABLE_PR_P_RST, ENABLE_PR_CI_RST,
+       ENABLE_PR_D_RST, ENABLE_PR_C_RST, ENABLE_PR_B_RST, ENABLE_PR_A_RST };
+
+localparam RAW_CONFIG3_GEN = { ALU_MUX,  ALU_OP };
+
+  NX_DSP #(
+    .std_mode(""),
+    .raw_config0(RAW_CONFIG0_GEN),
+    .raw_config1(RAW_CONFIG1_GEN),
+    .raw_config2(RAW_CONFIG2_GEN),
+    .raw_config3(RAW_CONFIG3_GEN),
+  ) _TECHMAP_REPLACE_ (
+    .A1(A[0]),
+    .A2(A[1]),
+    .A3(A[2]),
+    .A4(A[3]),
+    .A5(A[4]),
+    .A6(A[5]),
+    .A7(A[6]),
+    .A8(A[7]),
+    .A9(A[8]),
+    .A10(A[9]),
+    .A11(A[10]),
+    .A12(A[11]),
+    .A13(A[12]),
+    .A14(A[13]),
+    .A15(A[14]),
+    .A16(A[15]),
+    .A17(A[16]),
+    .A18(A[17]),
+    .A19(A[18]),
+    .A20(A[19]),
+    .A21(A[20]),
+    .A22(A[21]),
+    .A23(A[22]),
+    .A24(A[23]),
+
+    .B1(B[0]),
+    .B2(B[1]),
+    .B3(B[2]),
+    .B4(B[3]),
+    .B5(B[4]),
+    .B6(B[5]),
+    .B7(B[6]),
+    .B8(B[7]),
+    .B9(B[8]),
+    .B10(B[9]),
+    .B11(B[10]),
+    .B12(B[11]),
+    .B13(B[12]),
+    .B14(B[13]),
+    .B15(B[14]),
+    .B16(B[15]),
+    .B17(B[16]),
+    .B18(B[17]),
+
+    .C1(C[0]),
+    .C2(C[1]),
+    .C3(C[2]),
+    .C4(C[3]),
+    .C5(C[4]),
+    .C6(C[5]),
+    .C7(C[6]),
+    .C8(C[7]),
+    .C9(C[8]),
+    .C10(C[9]),
+    .C11(C[10]),
+    .C12(C[11]),
+    .C13(C[12]),
+    .C14(C[13]),
+    .C15(C[14]),
+    .C16(C[15]),
+    .C17(C[16]),
+    .C18(C[17]),
+    .C19(C[18]),
+    .C20(C[19]),
+    .C21(C[20]),
+    .C22(C[21]),
+    .C23(C[22]),
+    .C24(C[23]),
+    .C25(C[24]),
+    .C26(C[25]),
+    .C27(C[26]),
+    .C28(C[27]),
+    .C29(C[28]),
+    .C30(C[29]),
+    .C31(C[30]),
+    .C32(C[31]),
+    .C33(C[32]),
+    .C34(C[33]),
+    .C35(C[34]),
+    .C36(C[35]),
+
+    .CAI1(CAI[0]),
+    .CAI2(CAI[1]),
+    .CAI3(CAI[2]),
+    .CAI4(CAI[3]),
+    .CAI5(CAI[4]),
+    .CAI6(CAI[5]),
+    .CAI7(CAI[6]),
+    .CAI8(CAI[7]),
+    .CAI9(CAI[8]),
+    .CAI10(CAI[9]),
+    .CAI11(CAI[10]),
+    .CAI12(CAI[11]),
+    .CAI13(CAI[12]),
+    .CAI14(CAI[13]),
+    .CAI15(CAI[14]),
+    .CAI16(CAI[15]),
+    .CAI17(CAI[16]),
+    .CAI18(CAI[17]),
+
+    .CAO1(CAO[0]),
+    .CAO2(CAO[1]),
+    .CAO3(CAO[2]),
+    .CAO4(CAO[3]),
+    .CAO5(CAO[4]),
+    .CAO6(CAO[5]),
+    .CAO7(CAO[6]),
+    .CAO8(CAO[7]),
+    .CAO9(CAO[8]),
+    .CAO10(CAO[9]),
+    .CAO11(CAO[10]),
+    .CAO12(CAO[11]),
+    .CAO13(CAO[12]),
+    .CAO14(CAO[13]),
+    .CAO15(CAO[14]),
+    .CAO16(CAO[15]),
+    .CAO17(CAO[16]),
+    .CAO18(CAO[17]),
+
+    .CBI1(CBI[0]),
+    .CBI2(CBI[1]),
+    .CBI3(CBI[2]),
+    .CBI4(CBI[3]),
+    .CBI5(CBI[4]),
+    .CBI6(CBI[5]),
+    .CBI7(CBI[6]),
+    .CBI8(CBI[7]),
+    .CBI9(CBI[8]),
+    .CBI10(CBI[9]),
+    .CBI11(CBI[10]),
+    .CBI12(CBI[11]),
+    .CBI13(CBI[12]),
+    .CBI14(CBI[13]),
+    .CBI15(CBI[14]),
+    .CBI16(CBI[15]),
+    .CBI17(CBI[16]),
+    .CBI18(CBI[17]),
+
+    .CBO1(CBO[0]),
+    .CBO2(CBO[1]),
+    .CBO3(CBO[2]),
+    .CBO4(CBO[3]),
+    .CBO5(CBO[4]),
+    .CBO6(CBO[5]),
+    .CBO7(CBO[6]),
+    .CBO8(CBO[7]),
+    .CBO9(CBO[8]),
+    .CBO10(CBO[9]),
+    .CBO11(CBO[10]),
+    .CBO12(CBO[11]),
+    .CBO13(CBO[12]),
+    .CBO14(CBO[13]),
+    .CBO15(CBO[14]),
+    .CBO16(CBO[15]),
+    .CBO17(CBO[16]),
+    .CBO18(CBO[17]),
+
+    .CCI(CCI),
+    .CCO(CCO),
+    .CI(CI),
+    .CK(CK),
+    .CO(CO),
+    .CO37(CO36),
+    .CO49(CO48),
+
+    .CZI1(CZI[0]),
+    .CZI2(CZI[1]),
+    .CZI3(CZI[2]),
+    .CZI4(CZI[3]),
+    .CZI5(CZI[4]),
+    .CZI6(CZI[5]),
+    .CZI7(CZI[6]),
+    .CZI8(CZI[7]),
+    .CZI9(CZI[8]),
+    .CZI10(CZI[9]),
+    .CZI11(CZI[10]),
+    .CZI12(CZI[11]),
+    .CZI13(CZI[12]),
+    .CZI14(CZI[13]),
+    .CZI15(CZI[14]),
+    .CZI16(CZI[15]),
+    .CZI17(CZI[16]),
+    .CZI18(CZI[17]),
+    .CZI19(CZI[18]),
+    .CZI20(CZI[19]),
+    .CZI21(CZI[20]),
+    .CZI22(CZI[21]),
+    .CZI23(CZI[22]),
+    .CZI24(CZI[23]),
+    .CZI25(CZI[24]),
+    .CZI26(CZI[25]),
+    .CZI27(CZI[26]),
+    .CZI28(CZI[27]),
+    .CZI29(CZI[28]),
+    .CZI30(CZI[29]),
+    .CZI31(CZI[30]),
+    .CZI32(CZI[31]),
+    .CZI33(CZI[32]),
+    .CZI34(CZI[33]),
+    .CZI35(CZI[34]),
+    .CZI36(CZI[35]),
+    .CZI37(CZI[36]),
+    .CZI38(CZI[37]),
+    .CZI39(CZI[38]),
+    .CZI40(CZI[39]),
+    .CZI41(CZI[40]),
+    .CZI42(CZI[41]),
+    .CZI43(CZI[42]),
+    .CZI44(CZI[43]),
+    .CZI45(CZI[44]),
+    .CZI46(CZI[45]),
+    .CZI47(CZI[46]),
+    .CZI48(CZI[47]),
+    .CZI49(CZI[48]),
+    .CZI50(CZI[49]),
+    .CZI51(CZI[50]),
+    .CZI52(CZI[51]),
+    .CZI53(CZI[52]),
+    .CZI54(CZI[53]),
+    .CZI55(CZI[54]),
+    .CZI56(CZI[55]),
+
+    .CZO1(CZO[0]),
+    .CZO2(CZO[1]),
+    .CZO3(CZO[2]),
+    .CZO4(CZO[3]),
+    .CZO5(CZO[4]),
+    .CZO6(CZO[5]),
+    .CZO7(CZO[6]),
+    .CZO8(CZO[7]),
+    .CZO9(CZO[8]),
+    .CZO10(CZO[9]),
+    .CZO11(CZO[10]),
+    .CZO12(CZO[11]),
+    .CZO13(CZO[12]),
+    .CZO14(CZO[13]),
+    .CZO15(CZO[14]),
+    .CZO16(CZO[15]),
+    .CZO17(CZO[16]),
+    .CZO18(CZO[17]),
+    .CZO19(CZO[18]),
+    .CZO20(CZO[19]),
+    .CZO21(CZO[20]),
+    .CZO22(CZO[21]),
+    .CZO23(CZO[22]),
+    .CZO24(CZO[23]),
+    .CZO25(CZO[24]),
+    .CZO26(CZO[25]),
+    .CZO27(CZO[26]),
+    .CZO28(CZO[27]),
+    .CZO29(CZO[28]),
+    .CZO30(CZO[29]),
+    .CZO31(CZO[30]),
+    .CZO32(CZO[31]),
+    .CZO33(CZO[32]),
+    .CZO34(CZO[33]),
+    .CZO35(CZO[34]),
+    .CZO36(CZO[35]),
+    .CZO37(CZO[36]),
+    .CZO38(CZO[37]),
+    .CZO39(CZO[38]),
+    .CZO40(CZO[39]),
+    .CZO41(CZO[40]),
+    .CZO42(CZO[41]),
+    .CZO43(CZO[42]),
+    .CZO44(CZO[43]),
+    .CZO45(CZO[44]),
+    .CZO46(CZO[45]),
+    .CZO47(CZO[46]),
+    .CZO48(CZO[47]),
+    .CZO49(CZO[48]),
+    .CZO50(CZO[49]),
+    .CZO51(CZO[50]),
+    .CZO52(CZO[51]),
+    .CZO53(CZO[52]),
+    .CZO54(CZO[53]),
+    .CZO55(CZO[54]),
+    .CZO56(CZO[55]),
+
+    .D1(D[0]),
+    .D2(D[1]),
+    .D3(D[2]),
+    .D4(D[3]),
+    .D5(D[4]),
+    .D6(D[5]),
+    .D7(D[6]),
+    .D8(D[7]),
+    .D9(D[8]),
+    .D10(D[9]),
+    .D11(D[10]),
+    .D12(D[11]),
+    .D13(D[12]),
+    .D14(D[13]),
+    .D15(D[14]),
+    .D16(D[15]),
+    .D17(D[16]),
+    .D18(D[17]),
+
+    .OVF(OVF),
+    .R(R),
+    .RZ(RZ),
+    .WE(WE),
+
+    .Z1(Z[0]),
+    .Z2(Z[1]),
+    .Z3(Z[2]),
+    .Z4(Z[3]),
+    .Z5(Z[4]),
+    .Z6(Z[5]),
+    .Z7(Z[6]),
+    .Z8(Z[7]),
+    .Z9(Z[8]),
+    .Z10(Z[9]),
+    .Z11(Z[10]),
+    .Z12(Z[11]),
+    .Z13(Z[12]),
+    .Z14(Z[13]),
+    .Z15(Z[14]),
+    .Z16(Z[15]),
+    .Z17(Z[16]),
+    .Z18(Z[17]),
+    .Z19(Z[18]),
+    .Z20(Z[19]),
+    .Z21(Z[20]),
+    .Z22(Z[21]),
+    .Z23(Z[22]),
+    .Z24(Z[23]),
+    .Z25(Z[24]),
+    .Z26(Z[25]),
+    .Z27(Z[26]),
+    .Z28(Z[27]),
+    .Z29(Z[28]),
+    .Z30(Z[29]),
+    .Z31(Z[30]),
+    .Z32(Z[31]),
+    .Z33(Z[32]),
+    .Z34(Z[33]),
+    .Z35(Z[34]),
+    .Z36(Z[35]),
+    .Z37(Z[36]),
+    .Z38(Z[37]),
+    .Z39(Z[38]),
+    .Z40(Z[39]),
+    .Z41(Z[40]),
+    .Z42(Z[41]),
+    .Z43(Z[42]),
+    .Z44(Z[43]),
+    .Z45(Z[44]),
+    .Z46(Z[45]),
+    .Z47(Z[46]),
+    .Z48(Z[47]),
+    .Z49(Z[48]),
+    .Z50(Z[49]),
+    .Z51(Z[50]),
+    .Z52(Z[51]),
+    .Z53(Z[52]),
+    .Z54(Z[53]),
+    .Z55(Z[54]),
+    .Z56(Z[55])
+  );
+endmodule

From 200e1a7bfea7bd950e372a4e2e8def4afe9be97f Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 12 Mar 2024 15:11:11 +0100
Subject: [PATCH 279/499] more DSP wrappers

---
 techlibs/nanoxplore/cells_bb.v     | 248 --------
 techlibs/nanoxplore/cells_wrap_l.v | 874 ++++++++++++++++++++++++++++
 techlibs/nanoxplore/cells_wrap_m.v | 399 +++++++++++++
 techlibs/nanoxplore/cells_wrap_u.v | 883 +++++++++++++++++++++++++++++
 4 files changed, 2156 insertions(+), 248 deletions(-)

diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index 7aa8dcfb7a7..f01d7571fe4 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -853,254 +853,6 @@ module NX_DFR(I, CK, L, R, O);
     parameter ring = 0;
 endmodule
 
-(* blackbox *)
-module NX_DSP_L_SPLIT(CK, R, RZ, WE, CI, CCI, CO, CO36, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
-, CZO);
-    input [23:0] A;
-    input [17:0] B;
-    input [35:0] C;
-    input [23:0] CAI;
-    output [23:0] CAO;
-    input [17:0] CBI;
-    output [17:0] CBO;
-    input CCI;
-    output CCO;
-    input CI;
-    input CK;
-    output CO;
-    output CO36;
-    output CO56;
-    input [55:0] CZI;
-    output [55:0] CZO;
-    input [17:0] D;
-    output OVF;
-    input R;
-    input RZ;
-    input WE;
-    output [55:0] Z;
-    parameter ALU_DYNAMIC_OP = 1'b0;
-    parameter ALU_MUX = 1'b0;
-    parameter ALU_OP = 6'b000000;
-    parameter CO_SEL = 1'b0;
-    parameter ENABLE_PR_ALU_RST = 1'b0;
-    parameter ENABLE_PR_A_RST = 1'b0;
-    parameter ENABLE_PR_B_RST = 1'b0;
-    parameter ENABLE_PR_CI_RST = 1'b0;
-    parameter ENABLE_PR_CO_RST = 1'b0;
-    parameter ENABLE_PR_C_RST = 1'b0;
-    parameter ENABLE_PR_D_RST = 1'b0;
-    parameter ENABLE_PR_MULT_RST = 1'b0;
-    parameter ENABLE_PR_OV_RST = 1'b0;
-    parameter ENABLE_PR_P_RST = 1'b0;
-    parameter ENABLE_PR_X_RST = 1'b0;
-    parameter ENABLE_PR_Y_RST = 1'b0;
-    parameter ENABLE_PR_Z_RST = 1'b0;
-    parameter ENABLE_SATURATION = 1'b0;
-    parameter MUX_A = 1'b0;
-    parameter MUX_B = 1'b0;
-    parameter MUX_CI = 1'b0;
-    parameter MUX_P = 1'b0;
-    parameter MUX_X = 2'b00;
-    parameter MUX_Y = 1'b0;
-    parameter MUX_Z = 1'b0;
-    parameter PRE_ADDER_OP = 1'b0;
-    parameter PR_ALU_MUX = 1'b0;
-    parameter PR_A_CASCADE_MUX = 2'b00;
-    parameter PR_A_MUX = 2'b00;
-    parameter PR_B_CASCADE_MUX = 2'b00;
-    parameter PR_B_MUX = 2'b00;
-    parameter PR_CI_MUX = 1'b0;
-    parameter PR_CO_MUX = 1'b0;
-    parameter PR_C_MUX = 1'b0;
-    parameter PR_D_MUX = 1'b0;
-    parameter PR_MULT_MUX = 1'b0;
-    parameter PR_OV_MUX = 1'b0;
-    parameter PR_P_MUX = 1'b0;
-    parameter PR_X_MUX = 1'b0;
-    parameter PR_Y_MUX = 1'b0;
-    parameter PR_Z_MUX = 1'b0;
-    parameter SATURATION_RANK = 6'b000000;
-    parameter SIGNED_MODE = 1'b0;
-    parameter Z_FEEDBACK_SHL12 = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_DSP_L_WRAP(CCI, CCO, CI, CK, CO, CO37, CO57, OVF, R, RZ, WE, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
-, CZO);
-    input [23:0] A;
-    input [17:0] B;
-    input [35:0] C;
-    input [23:0] CAI;
-    output [23:0] CAO;
-    input [17:0] CBI;
-    output [17:0] CBO;
-    input CCI;
-    output CCO;
-    input CI;
-    input CK;
-    output CO;
-    output CO37;
-    output CO57;
-    input [55:0] CZI;
-    output [55:0] CZO;
-    input [17:0] D;
-    output OVF;
-    input R;
-    input RZ;
-    input WE;
-    output [55:0] Z;
-    parameter raw_config0 = 20'b00000000000000000000;
-    parameter raw_config1 = 19'b0000000000000000000;
-    parameter raw_config2 = 13'b0000000000000;
-    parameter raw_config3 = 7'b0000000;
-    parameter std_mode = "";
-endmodule
-
-(* blackbox *)
-module NX_DSP_U_SPLIT(CK, R, RZ, WE, WEZ, CI, CCI, CO42, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
-, CZO);
-    input [23:0] A;
-    input [17:0] B;
-    input [35:0] C;
-    input [23:0] CAI;
-    output [23:0] CAO;
-    input [17:0] CBI;
-    output [17:0] CBO;
-    input CCI;
-    output CCO;
-    input CI;
-    input CK;
-    output CO42;
-    output CO56;
-    input [55:0] CZI;
-    output [55:0] CZO;
-    input [17:0] D;
-    output OVF;
-    input R;
-    input RZ;
-    input WE;
-    input WEZ;
-    output [55:0] Z;
-    parameter ALU_DYNAMIC_OP = 2'b00;
-    parameter ALU_OP = 3'b000;
-    parameter ENABLE_PR_A_RST = 1'b0;
-    parameter ENABLE_PR_B_RST = 1'b0;
-    parameter ENABLE_PR_CCO_RST = 1'b0;
-    parameter ENABLE_PR_CI_RST = 1'b0;
-    parameter ENABLE_PR_CO_RST = 1'b0;
-    parameter ENABLE_PR_CZ_RST = 1'b0;
-    parameter ENABLE_PR_C_RST = 1'b0;
-    parameter ENABLE_PR_D_RST = 1'b0;
-    parameter ENABLE_PR_MULT_RST = 1'b0;
-    parameter ENABLE_PR_OV_RST = 1'b0;
-    parameter ENABLE_PR_P_RST = 1'b0;
-    parameter ENABLE_PR_X_RST = 1'b0;
-    parameter ENABLE_PR_Y_RST = 1'b0;
-    parameter ENABLE_PR_Z_RST = 1'b0;
-    parameter ENABLE_SATURATION = 1'b0;
-    parameter INV_RST = 1'b0;
-    parameter INV_RSTZ = 1'b0;
-    parameter INV_WE = 1'b0;
-    parameter INV_WEZ = 1'b0;
-    parameter MUX_A = 1'b0;
-    parameter MUX_B = 1'b0;
-    parameter MUX_CCI = 1'b0;
-    parameter MUX_CCO = 1'b0;
-    parameter MUX_CI = 1'b0;
-    parameter MUX_CZ = 1'b0;
-    parameter MUX_P = 1'b0;
-    parameter MUX_X = 3'b000;
-    parameter MUX_Y = 1'b0;
-    parameter MUX_Z = 1'b0;
-    parameter PRE_ADDER_OP = 1'b0;
-    parameter PR_A_CASCADE_MUX = 2'b00;
-    parameter PR_A_MUX = 2'b00;
-    parameter PR_B_CASCADE_MUX = 2'b00;
-    parameter PR_B_MUX = 2'b00;
-    parameter PR_CCO_MUX = 1'b0;
-    parameter PR_CI_MUX = 1'b0;
-    parameter PR_CO_MUX = 1'b0;
-    parameter PR_CZ_MUX = 1'b0;
-    parameter PR_C_MUX = 1'b0;
-    parameter PR_D_MUX = 1'b0;
-    parameter PR_MULT_MUX = 1'b0;
-    parameter PR_OV_MUX = 1'b0;
-    parameter PR_P_MUX = 1'b0;
-    parameter PR_RSTZ_MUX = 1'b0;
-    parameter PR_RST_MUX = 1'b0;
-    parameter PR_WEZ_MUX = 1'b0;
-    parameter PR_WE_MUX = 1'b0;
-    parameter PR_X_MUX = 1'b0;
-    parameter PR_Y_MUX = 1'b0;
-    parameter PR_Z_MUX = 1'b0;
-    parameter SATURATION_RANK = 6'b000000;
-    parameter SIGNED_MODE = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_DSP_U_WRAP(CCI, CCO, CI, CK, CO43, CO57, OVF, R, RZ, WE, WEZ, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
-, CZO);
-    input [23:0] A;
-    input [17:0] B;
-    input [35:0] C;
-    input [23:0] CAI;
-    output [23:0] CAO;
-    input [17:0] CBI;
-    output [17:0] CBO;
-    input CCI;
-    output CCO;
-    input CI;
-    input CK;
-    output CO43;
-    output CO57;
-    input [55:0] CZI;
-    output [55:0] CZO;
-    input [17:0] D;
-    output OVF;
-    input R;
-    input RZ;
-    input WE;
-    input WEZ;
-    output [55:0] Z;
-    parameter raw_config0 = 27'b000000000000000000000000000;
-    parameter raw_config1 = 24'b000000000000000000000000;
-    parameter raw_config2 = 14'b00000000000000;
-    parameter raw_config3 = 3'b000;
-    parameter std_mode = "";
-endmodule
-
-(* blackbox *)
-module NX_DSP_WRAP(CCI, CCO, CI, CK, CO, CO37, CO49, OVF, R, RZ, WE, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
-, CZO);
-    input [23:0] A;
-    input [17:0] B;
-    input [35:0] C;
-    input [17:0] CAI;
-    output [17:0] CAO;
-    input [17:0] CBI;
-    output [17:0] CBO;
-    input CCI;
-    output CCO;
-    input CI;
-    input CK;
-    output CO;
-    output CO37;
-    output CO49;
-    input [55:0] CZI;
-    output [55:0] CZO;
-    input [17:0] D;
-    output OVF;
-    input R;
-    input RZ;
-    input WE;
-    output [55:0] Z;
-    parameter raw_config0 = 20'b00000000000000000000;
-    parameter raw_config1 = 19'b0000000000000000000;
-    parameter raw_config2 = 13'b0000000000000;
-    parameter raw_config3 = 7'b0000000;
-    parameter std_mode = "";
-endmodule
-
 (* blackbox *)
 module NX_ECC(CKD, CHK, COR, ERR);
     input CHK;
diff --git a/techlibs/nanoxplore/cells_wrap_l.v b/techlibs/nanoxplore/cells_wrap_l.v
index d0f5502f8c3..dc2e2a81cd0 100644
--- a/techlibs/nanoxplore/cells_wrap_l.v
+++ b/techlibs/nanoxplore/cells_wrap_l.v
@@ -333,3 +333,877 @@ module NX_CDC_L_BIN2GRAY(CK1, CK2, BI, AO, BO, AI);
     .DI6(1'b0)
   );
 endmodule
+
+module NX_DSP_L_SPLIT(CK, R, RZ, WE, CI, CCI, CO, CO36, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
+, CZO);
+    input [23:0] A;
+    input [17:0] B;
+    input [35:0] C;
+    input [23:0] CAI;
+    output [23:0] CAO;
+    input [17:0] CBI;
+    output [17:0] CBO;
+    input CCI;
+    output CCO;
+    input CI;
+    input CK;
+    output CO;
+    output CO36;
+    output CO56;
+    input [55:0] CZI;
+    output [55:0] CZO;
+    input [17:0] D;
+    output OVF;
+    input R;
+    input RZ;
+    input WE;
+    output [55:0] Z;
+    parameter ALU_DYNAMIC_OP = 1'b0;
+    parameter ALU_MUX = 1'b0;
+    parameter ALU_OP = 6'b000000;
+    parameter CO_SEL = 1'b0;
+    parameter ENABLE_PR_ALU_RST = 1'b0;
+    parameter ENABLE_PR_A_RST = 1'b0;
+    parameter ENABLE_PR_B_RST = 1'b0;
+    parameter ENABLE_PR_CI_RST = 1'b0;
+    parameter ENABLE_PR_CO_RST = 1'b0;
+    parameter ENABLE_PR_C_RST = 1'b0;
+    parameter ENABLE_PR_D_RST = 1'b0;
+    parameter ENABLE_PR_MULT_RST = 1'b0;
+    parameter ENABLE_PR_OV_RST = 1'b0;
+    parameter ENABLE_PR_P_RST = 1'b0;
+    parameter ENABLE_PR_X_RST = 1'b0;
+    parameter ENABLE_PR_Y_RST = 1'b0;
+    parameter ENABLE_PR_Z_RST = 1'b0;
+    parameter ENABLE_SATURATION = 1'b0;
+    parameter MUX_A = 1'b0;
+    parameter MUX_B = 1'b0;
+    parameter MUX_CI = 1'b0;
+    parameter MUX_P = 1'b0;
+    parameter MUX_X = 2'b00;
+    parameter MUX_Y = 1'b0;
+    parameter MUX_Z = 1'b0;
+    parameter PRE_ADDER_OP = 1'b0;
+    parameter PR_ALU_MUX = 1'b0;
+    parameter PR_A_CASCADE_MUX = 2'b00;
+    parameter PR_A_MUX = 2'b00;
+    parameter PR_B_CASCADE_MUX = 2'b00;
+    parameter PR_B_MUX = 2'b00;
+    parameter PR_CI_MUX = 1'b0;
+    parameter PR_CO_MUX = 1'b0;
+    parameter PR_C_MUX = 1'b0;
+    parameter PR_D_MUX = 1'b0;
+    parameter PR_MULT_MUX = 1'b0;
+    parameter PR_OV_MUX = 1'b0;
+    parameter PR_P_MUX = 1'b0;
+    parameter PR_X_MUX = 1'b0;
+    parameter PR_Y_MUX = 1'b0;
+    parameter PR_Z_MUX = 1'b0;
+    parameter SATURATION_RANK = 6'b000000;
+    parameter SIGNED_MODE = 1'b0;
+    parameter Z_FEEDBACK_SHL12 = 1'b0;
+
+localparam RAW_CONFIG0_GEN = { CO_SEL, ALU_DYNAMIC_OP, SATURATION_RANK, ENABLE_SATURATION, Z_FEEDBACK_SHL12, MUX_Z,
+       MUX_CI, MUX_Y, MUX_X, MUX_P, MUX_B, MUX_A, PRE_ADDER_OP, SIGNED_MODE };
+
+localparam RAW_CONFIG1_GEN = { PR_OV_MUX, PR_CO_MUX, PR_Z_MUX, PR_ALU_MUX, PR_MULT_MUX, PR_Y_MUX, PR_X_MUX,
+       PR_P_MUX, PR_CI_MUX, PR_D_MUX, PR_C_MUX, PR_B_CASCADE_MUX, PR_B_MUX, PR_A_CASCADE_MUX, PR_A_MUX };
+
+localparam RAW_CONFIG2_GEN = { ENABLE_PR_OV_RST, ENABLE_PR_CO_RST, ENABLE_PR_Z_RST, ENABLE_PR_ALU_RST,
+       ENABLE_PR_MULT_RST, ENABLE_PR_Y_RST, ENABLE_PR_X_RST, ENABLE_PR_P_RST, ENABLE_PR_CI_RST,
+       ENABLE_PR_D_RST, ENABLE_PR_C_RST, ENABLE_PR_B_RST, ENABLE_PR_A_RST };
+
+localparam RAW_CONFIG3_GEN = { ALU_MUX, ALU_OP };
+
+  NX_DSP_L #(
+    .std_mode(""),
+    .raw_config0(RAW_CONFIG0_GEN),
+    .raw_config1(RAW_CONFIG1_GEN),
+    .raw_config2(RAW_CONFIG2_GEN),
+    .raw_config3(RAW_CONFIG3_GEN),
+  ) _TECHMAP_REPLACE_ (
+    .A1(A[0]),
+    .A2(A[1]),
+    .A3(A[2]),
+    .A4(A[3]),
+    .A5(A[4]),
+    .A6(A[5]),
+    .A7(A[6]),
+    .A8(A[7]),
+    .A9(A[8]),
+    .A10(A[9]),
+    .A11(A[10]),
+    .A12(A[11]),
+    .A13(A[12]),
+    .A14(A[13]),
+    .A15(A[14]),
+    .A16(A[15]),
+    .A17(A[16]),
+    .A18(A[17]),
+    .A19(A[18]),
+    .A20(A[19]),
+    .A21(A[20]),
+    .A22(A[21]),
+    .A23(A[22]),
+    .A24(A[23]),
+
+    .B1(B[0]),
+    .B2(B[1]),
+    .B3(B[2]),
+    .B4(B[3]),
+    .B5(B[4]),
+    .B6(B[5]),
+    .B7(B[6]),
+    .B8(B[7]),
+    .B9(B[8]),
+    .B10(B[9]),
+    .B11(B[10]),
+    .B12(B[11]),
+    .B13(B[12]),
+    .B14(B[13]),
+    .B15(B[14]),
+    .B16(B[15]),
+    .B17(B[16]),
+    .B18(B[17]),
+
+    .C1(C[0]),
+    .C2(C[1]),
+    .C3(C[2]),
+    .C4(C[3]),
+    .C5(C[4]),
+    .C6(C[5]),
+    .C7(C[6]),
+    .C8(C[7]),
+    .C9(C[8]),
+    .C10(C[9]),
+    .C11(C[10]),
+    .C12(C[11]),
+    .C13(C[12]),
+    .C14(C[13]),
+    .C15(C[14]),
+    .C16(C[15]),
+    .C17(C[16]),
+    .C18(C[17]),
+    .C19(C[18]),
+    .C20(C[19]),
+    .C21(C[20]),
+    .C22(C[21]),
+    .C23(C[22]),
+    .C24(C[23]),
+    .C25(C[24]),
+    .C26(C[25]),
+    .C27(C[26]),
+    .C28(C[27]),
+    .C29(C[28]),
+    .C30(C[29]),
+    .C31(C[30]),
+    .C32(C[31]),
+    .C33(C[32]),
+    .C34(C[33]),
+    .C35(C[34]),
+    .C36(C[35]),
+
+    .CAI1(CAI[0]),
+    .CAI2(CAI[1]),
+    .CAI3(CAI[2]),
+    .CAI4(CAI[3]),
+    .CAI5(CAI[4]),
+    .CAI6(CAI[5]),
+    .CAI7(CAI[6]),
+    .CAI8(CAI[7]),
+    .CAI9(CAI[8]),
+    .CAI10(CAI[9]),
+    .CAI11(CAI[10]),
+    .CAI12(CAI[11]),
+    .CAI13(CAI[12]),
+    .CAI14(CAI[13]),
+    .CAI15(CAI[14]),
+    .CAI16(CAI[15]),
+    .CAI17(CAI[16]),
+    .CAI18(CAI[17]),
+    .CAI19(CAI[18]),
+    .CAI20(CAI[19]),
+    .CAI21(CAI[20]),
+    .CAI22(CAI[21]),
+    .CAI23(CAI[22]),
+    .CAI24(CAI[23]),
+
+    .CAO1(CAO[0]),
+    .CAO2(CAO[1]),
+    .CAO3(CAO[2]),
+    .CAO4(CAO[3]),
+    .CAO5(CAO[4]),
+    .CAO6(CAO[5]),
+    .CAO7(CAO[6]),
+    .CAO8(CAO[7]),
+    .CAO9(CAO[8]),
+    .CAO10(CAO[9]),
+    .CAO11(CAO[10]),
+    .CAO12(CAO[11]),
+    .CAO13(CAO[12]),
+    .CAO14(CAO[13]),
+    .CAO15(CAO[14]),
+    .CAO16(CAO[15]),
+    .CAO17(CAO[16]),
+    .CAO18(CAO[17]),
+    .CAO19(CAO[18]),
+    .CAO20(CAO[19]),
+    .CAO21(CAO[20]),
+    .CAO22(CAO[21]),
+    .CAO23(CAO[22]),
+    .CAO24(CAO[23]),
+
+    .CBI1(CBI[0]),
+    .CBI2(CBI[1]),
+    .CBI3(CBI[2]),
+    .CBI4(CBI[3]),
+    .CBI5(CBI[4]),
+    .CBI6(CBI[5]),
+    .CBI7(CBI[6]),
+    .CBI8(CBI[7]),
+    .CBI9(CBI[8]),
+    .CBI10(CBI[9]),
+    .CBI11(CBI[10]),
+    .CBI12(CBI[11]),
+    .CBI13(CBI[12]),
+    .CBI14(CBI[13]),
+    .CBI15(CBI[14]),
+    .CBI16(CBI[15]),
+    .CBI17(CBI[16]),
+    .CBI18(CBI[17]),
+
+    .CBO1(CBO[0]),
+    .CBO2(CBO[1]),
+    .CBO3(CBO[2]),
+    .CBO4(CBO[3]),
+    .CBO5(CBO[4]),
+    .CBO6(CBO[5]),
+    .CBO7(CBO[6]),
+    .CBO8(CBO[7]),
+    .CBO9(CBO[8]),
+    .CBO10(CBO[9]),
+    .CBO11(CBO[10]),
+    .CBO12(CBO[11]),
+    .CBO13(CBO[12]),
+    .CBO14(CBO[13]),
+    .CBO15(CBO[14]),
+    .CBO16(CBO[15]),
+    .CBO17(CBO[16]),
+    .CBO18(CBO[17]),
+
+    .CCI(CCI),
+    .CCO(CCO),
+    .CI(CI),
+    .CK(CK),
+    .CO(CO),
+    .CO37(CO36),
+    .CO57(CO56),
+
+    .CZI1(CZI[0]),
+    .CZI2(CZI[1]),
+    .CZI3(CZI[2]),
+    .CZI4(CZI[3]),
+    .CZI5(CZI[4]),
+    .CZI6(CZI[5]),
+    .CZI7(CZI[6]),
+    .CZI8(CZI[7]),
+    .CZI9(CZI[8]),
+    .CZI10(CZI[9]),
+    .CZI11(CZI[10]),
+    .CZI12(CZI[11]),
+    .CZI13(CZI[12]),
+    .CZI14(CZI[13]),
+    .CZI15(CZI[14]),
+    .CZI16(CZI[15]),
+    .CZI17(CZI[16]),
+    .CZI18(CZI[17]),
+    .CZI19(CZI[18]),
+    .CZI20(CZI[19]),
+    .CZI21(CZI[20]),
+    .CZI22(CZI[21]),
+    .CZI23(CZI[22]),
+    .CZI24(CZI[23]),
+    .CZI25(CZI[24]),
+    .CZI26(CZI[25]),
+    .CZI27(CZI[26]),
+    .CZI28(CZI[27]),
+    .CZI29(CZI[28]),
+    .CZI30(CZI[29]),
+    .CZI31(CZI[30]),
+    .CZI32(CZI[31]),
+    .CZI33(CZI[32]),
+    .CZI34(CZI[33]),
+    .CZI35(CZI[34]),
+    .CZI36(CZI[35]),
+    .CZI37(CZI[36]),
+    .CZI38(CZI[37]),
+    .CZI39(CZI[38]),
+    .CZI40(CZI[39]),
+    .CZI41(CZI[40]),
+    .CZI42(CZI[41]),
+    .CZI43(CZI[42]),
+    .CZI44(CZI[43]),
+    .CZI45(CZI[44]),
+    .CZI46(CZI[45]),
+    .CZI47(CZI[46]),
+    .CZI48(CZI[47]),
+    .CZI49(CZI[48]),
+    .CZI50(CZI[49]),
+    .CZI51(CZI[50]),
+    .CZI52(CZI[51]),
+    .CZI53(CZI[52]),
+    .CZI54(CZI[53]),
+    .CZI55(CZI[54]),
+    .CZI56(CZI[55]),
+
+    .CZO1(CZO[0]),
+    .CZO2(CZO[1]),
+    .CZO3(CZO[2]),
+    .CZO4(CZO[3]),
+    .CZO5(CZO[4]),
+    .CZO6(CZO[5]),
+    .CZO7(CZO[6]),
+    .CZO8(CZO[7]),
+    .CZO9(CZO[8]),
+    .CZO10(CZO[9]),
+    .CZO11(CZO[10]),
+    .CZO12(CZO[11]),
+    .CZO13(CZO[12]),
+    .CZO14(CZO[13]),
+    .CZO15(CZO[14]),
+    .CZO16(CZO[15]),
+    .CZO17(CZO[16]),
+    .CZO18(CZO[17]),
+    .CZO19(CZO[18]),
+    .CZO20(CZO[19]),
+    .CZO21(CZO[20]),
+    .CZO22(CZO[21]),
+    .CZO23(CZO[22]),
+    .CZO24(CZO[23]),
+    .CZO25(CZO[24]),
+    .CZO26(CZO[25]),
+    .CZO27(CZO[26]),
+    .CZO28(CZO[27]),
+    .CZO29(CZO[28]),
+    .CZO30(CZO[29]),
+    .CZO31(CZO[30]),
+    .CZO32(CZO[31]),
+    .CZO33(CZO[32]),
+    .CZO34(CZO[33]),
+    .CZO35(CZO[34]),
+    .CZO36(CZO[35]),
+    .CZO37(CZO[36]),
+    .CZO38(CZO[37]),
+    .CZO39(CZO[38]),
+    .CZO40(CZO[39]),
+    .CZO41(CZO[40]),
+    .CZO42(CZO[41]),
+    .CZO43(CZO[42]),
+    .CZO44(CZO[43]),
+    .CZO45(CZO[44]),
+    .CZO46(CZO[45]),
+    .CZO47(CZO[46]),
+    .CZO48(CZO[47]),
+    .CZO49(CZO[48]),
+    .CZO50(CZO[49]),
+    .CZO51(CZO[50]),
+    .CZO52(CZO[51]),
+    .CZO53(CZO[52]),
+    .CZO54(CZO[53]),
+    .CZO55(CZO[54]),
+    .CZO56(CZO[55]),
+
+    .D1(D[0]),
+    .D2(D[1]),
+    .D3(D[2]),
+    .D4(D[3]),
+    .D5(D[4]),
+    .D6(D[5]),
+    .D7(D[6]),
+    .D8(D[7]),
+    .D9(D[8]),
+    .D10(D[9]),
+    .D11(D[10]),
+    .D12(D[11]),
+    .D13(D[12]),
+    .D14(D[13]),
+    .D15(D[14]),
+    .D16(D[15]),
+    .D17(D[16]),
+    .D18(D[17]),
+
+    .OVF(OVF),
+    .R(R),
+    .RZ(RZ),
+    .WE(WE),
+
+    .Z1(Z[0]),
+    .Z2(Z[1]),
+    .Z3(Z[2]),
+    .Z4(Z[3]),
+    .Z5(Z[4]),
+    .Z6(Z[5]),
+    .Z7(Z[6]),
+    .Z8(Z[7]),
+    .Z9(Z[8]),
+    .Z10(Z[9]),
+    .Z11(Z[10]),
+    .Z12(Z[11]),
+    .Z13(Z[12]),
+    .Z14(Z[13]),
+    .Z15(Z[14]),
+    .Z16(Z[15]),
+    .Z17(Z[16]),
+    .Z18(Z[17]),
+    .Z19(Z[18]),
+    .Z20(Z[19]),
+    .Z21(Z[20]),
+    .Z22(Z[21]),
+    .Z23(Z[22]),
+    .Z24(Z[23]),
+    .Z25(Z[24]),
+    .Z26(Z[25]),
+    .Z27(Z[26]),
+    .Z28(Z[27]),
+    .Z29(Z[28]),
+    .Z30(Z[29]),
+    .Z31(Z[30]),
+    .Z32(Z[31]),
+    .Z33(Z[32]),
+    .Z34(Z[33]),
+    .Z35(Z[34]),
+    .Z36(Z[35]),
+    .Z37(Z[36]),
+    .Z38(Z[37]),
+    .Z39(Z[38]),
+    .Z40(Z[39]),
+    .Z41(Z[40]),
+    .Z42(Z[41]),
+    .Z43(Z[42]),
+    .Z44(Z[43]),
+    .Z45(Z[44]),
+    .Z46(Z[45]),
+    .Z47(Z[46]),
+    .Z48(Z[47]),
+    .Z49(Z[48]),
+    .Z50(Z[49]),
+    .Z51(Z[50]),
+    .Z52(Z[51]),
+    .Z53(Z[52]),
+    .Z54(Z[53]),
+    .Z55(Z[54]),
+    .Z56(Z[55])
+  );
+endmodule
+
+module NX_DSP_L_WRAP(CCI, CCO, CI, CK, CO, CO37, CO57, OVF, R, RZ, WE, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
+, CZO);
+    input [23:0] A;
+    input [17:0] B;
+    input [35:0] C;
+    input [23:0] CAI;
+    output [23:0] CAO;
+    input [17:0] CBI;
+    output [17:0] CBO;
+    input CCI;
+    output CCO;
+    input CI;
+    input CK;
+    output CO;
+    output CO37;
+    output CO57;
+    input [55:0] CZI;
+    output [55:0] CZO;
+    input [17:0] D;
+    output OVF;
+    input R;
+    input RZ;
+    input WE;
+    output [55:0] Z;
+    parameter raw_config0 = 20'b00000000000000000000;
+    parameter raw_config1 = 19'b0000000000000000000;
+    parameter raw_config2 = 13'b0000000000000;
+    parameter raw_config3 = 7'b0000000;
+    parameter std_mode = "";
+
+  NX_DSP_L #(
+    .std_mode(std_mode),
+    .raw_config0(raw_config0),
+    .raw_config1(raw_config1),
+    .raw_config2(raw_config2),
+    .raw_config3(raw_config3),
+  ) _TECHMAP_REPLACE_ (
+    .A1(A[0]),
+    .A2(A[1]),
+    .A3(A[2]),
+    .A4(A[3]),
+    .A5(A[4]),
+    .A6(A[5]),
+    .A7(A[6]),
+    .A8(A[7]),
+    .A9(A[8]),
+    .A10(A[9]),
+    .A11(A[10]),
+    .A12(A[11]),
+    .A13(A[12]),
+    .A14(A[13]),
+    .A15(A[14]),
+    .A16(A[15]),
+    .A17(A[16]),
+    .A18(A[17]),
+    .A19(A[18]),
+    .A20(A[19]),
+    .A21(A[20]),
+    .A22(A[21]),
+    .A23(A[22]),
+    .A24(A[23]),
+
+    .B1(B[0]),
+    .B2(B[1]),
+    .B3(B[2]),
+    .B4(B[3]),
+    .B5(B[4]),
+    .B6(B[5]),
+    .B7(B[6]),
+    .B8(B[7]),
+    .B9(B[8]),
+    .B10(B[9]),
+    .B11(B[10]),
+    .B12(B[11]),
+    .B13(B[12]),
+    .B14(B[13]),
+    .B15(B[14]),
+    .B16(B[15]),
+    .B17(B[16]),
+    .B18(B[17]),
+
+    .C1(C[0]),
+    .C2(C[1]),
+    .C3(C[2]),
+    .C4(C[3]),
+    .C5(C[4]),
+    .C6(C[5]),
+    .C7(C[6]),
+    .C8(C[7]),
+    .C9(C[8]),
+    .C10(C[9]),
+    .C11(C[10]),
+    .C12(C[11]),
+    .C13(C[12]),
+    .C14(C[13]),
+    .C15(C[14]),
+    .C16(C[15]),
+    .C17(C[16]),
+    .C18(C[17]),
+    .C19(C[18]),
+    .C20(C[19]),
+    .C21(C[20]),
+    .C22(C[21]),
+    .C23(C[22]),
+    .C24(C[23]),
+    .C25(C[24]),
+    .C26(C[25]),
+    .C27(C[26]),
+    .C28(C[27]),
+    .C29(C[28]),
+    .C30(C[29]),
+    .C31(C[30]),
+    .C32(C[31]),
+    .C33(C[32]),
+    .C34(C[33]),
+    .C35(C[34]),
+    .C36(C[35]),
+
+    .CAI1(CAI[0]),
+    .CAI2(CAI[1]),
+    .CAI3(CAI[2]),
+    .CAI4(CAI[3]),
+    .CAI5(CAI[4]),
+    .CAI6(CAI[5]),
+    .CAI7(CAI[6]),
+    .CAI8(CAI[7]),
+    .CAI9(CAI[8]),
+    .CAI10(CAI[9]),
+    .CAI11(CAI[10]),
+    .CAI12(CAI[11]),
+    .CAI13(CAI[12]),
+    .CAI14(CAI[13]),
+    .CAI15(CAI[14]),
+    .CAI16(CAI[15]),
+    .CAI17(CAI[16]),
+    .CAI18(CAI[17]),
+    .CAI19(CAI[18]),
+    .CAI20(CAI[19]),
+    .CAI21(CAI[20]),
+    .CAI22(CAI[21]),
+    .CAI23(CAI[22]),
+    .CAI24(CAI[23]),
+
+    .CAO1(CAO[0]),
+    .CAO2(CAO[1]),
+    .CAO3(CAO[2]),
+    .CAO4(CAO[3]),
+    .CAO5(CAO[4]),
+    .CAO6(CAO[5]),
+    .CAO7(CAO[6]),
+    .CAO8(CAO[7]),
+    .CAO9(CAO[8]),
+    .CAO10(CAO[9]),
+    .CAO11(CAO[10]),
+    .CAO12(CAO[11]),
+    .CAO13(CAO[12]),
+    .CAO14(CAO[13]),
+    .CAO15(CAO[14]),
+    .CAO16(CAO[15]),
+    .CAO17(CAO[16]),
+    .CAO18(CAO[17]),
+    .CAO19(CAO[18]),
+    .CAO20(CAO[19]),
+    .CAO21(CAO[20]),
+    .CAO22(CAO[21]),
+    .CAO23(CAO[22]),
+    .CAO24(CAO[23]),
+
+    .CBI1(CBI[0]),
+    .CBI2(CBI[1]),
+    .CBI3(CBI[2]),
+    .CBI4(CBI[3]),
+    .CBI5(CBI[4]),
+    .CBI6(CBI[5]),
+    .CBI7(CBI[6]),
+    .CBI8(CBI[7]),
+    .CBI9(CBI[8]),
+    .CBI10(CBI[9]),
+    .CBI11(CBI[10]),
+    .CBI12(CBI[11]),
+    .CBI13(CBI[12]),
+    .CBI14(CBI[13]),
+    .CBI15(CBI[14]),
+    .CBI16(CBI[15]),
+    .CBI17(CBI[16]),
+    .CBI18(CBI[17]),
+
+    .CBO1(CBO[0]),
+    .CBO2(CBO[1]),
+    .CBO3(CBO[2]),
+    .CBO4(CBO[3]),
+    .CBO5(CBO[4]),
+    .CBO6(CBO[5]),
+    .CBO7(CBO[6]),
+    .CBO8(CBO[7]),
+    .CBO9(CBO[8]),
+    .CBO10(CBO[9]),
+    .CBO11(CBO[10]),
+    .CBO12(CBO[11]),
+    .CBO13(CBO[12]),
+    .CBO14(CBO[13]),
+    .CBO15(CBO[14]),
+    .CBO16(CBO[15]),
+    .CBO17(CBO[16]),
+    .CBO18(CBO[17]),
+
+    .CCI(CCI),
+    .CCO(CCO),
+    .CI(CI),
+    .CK(CK),
+    .CO(CO),
+    .CO37(CO36),
+    .CO57(CO56),
+
+    .CZI1(CZI[0]),
+    .CZI2(CZI[1]),
+    .CZI3(CZI[2]),
+    .CZI4(CZI[3]),
+    .CZI5(CZI[4]),
+    .CZI6(CZI[5]),
+    .CZI7(CZI[6]),
+    .CZI8(CZI[7]),
+    .CZI9(CZI[8]),
+    .CZI10(CZI[9]),
+    .CZI11(CZI[10]),
+    .CZI12(CZI[11]),
+    .CZI13(CZI[12]),
+    .CZI14(CZI[13]),
+    .CZI15(CZI[14]),
+    .CZI16(CZI[15]),
+    .CZI17(CZI[16]),
+    .CZI18(CZI[17]),
+    .CZI19(CZI[18]),
+    .CZI20(CZI[19]),
+    .CZI21(CZI[20]),
+    .CZI22(CZI[21]),
+    .CZI23(CZI[22]),
+    .CZI24(CZI[23]),
+    .CZI25(CZI[24]),
+    .CZI26(CZI[25]),
+    .CZI27(CZI[26]),
+    .CZI28(CZI[27]),
+    .CZI29(CZI[28]),
+    .CZI30(CZI[29]),
+    .CZI31(CZI[30]),
+    .CZI32(CZI[31]),
+    .CZI33(CZI[32]),
+    .CZI34(CZI[33]),
+    .CZI35(CZI[34]),
+    .CZI36(CZI[35]),
+    .CZI37(CZI[36]),
+    .CZI38(CZI[37]),
+    .CZI39(CZI[38]),
+    .CZI40(CZI[39]),
+    .CZI41(CZI[40]),
+    .CZI42(CZI[41]),
+    .CZI43(CZI[42]),
+    .CZI44(CZI[43]),
+    .CZI45(CZI[44]),
+    .CZI46(CZI[45]),
+    .CZI47(CZI[46]),
+    .CZI48(CZI[47]),
+    .CZI49(CZI[48]),
+    .CZI50(CZI[49]),
+    .CZI51(CZI[50]),
+    .CZI52(CZI[51]),
+    .CZI53(CZI[52]),
+    .CZI54(CZI[53]),
+    .CZI55(CZI[54]),
+    .CZI56(CZI[55]),
+
+    .CZO1(CZO[0]),
+    .CZO2(CZO[1]),
+    .CZO3(CZO[2]),
+    .CZO4(CZO[3]),
+    .CZO5(CZO[4]),
+    .CZO6(CZO[5]),
+    .CZO7(CZO[6]),
+    .CZO8(CZO[7]),
+    .CZO9(CZO[8]),
+    .CZO10(CZO[9]),
+    .CZO11(CZO[10]),
+    .CZO12(CZO[11]),
+    .CZO13(CZO[12]),
+    .CZO14(CZO[13]),
+    .CZO15(CZO[14]),
+    .CZO16(CZO[15]),
+    .CZO17(CZO[16]),
+    .CZO18(CZO[17]),
+    .CZO19(CZO[18]),
+    .CZO20(CZO[19]),
+    .CZO21(CZO[20]),
+    .CZO22(CZO[21]),
+    .CZO23(CZO[22]),
+    .CZO24(CZO[23]),
+    .CZO25(CZO[24]),
+    .CZO26(CZO[25]),
+    .CZO27(CZO[26]),
+    .CZO28(CZO[27]),
+    .CZO29(CZO[28]),
+    .CZO30(CZO[29]),
+    .CZO31(CZO[30]),
+    .CZO32(CZO[31]),
+    .CZO33(CZO[32]),
+    .CZO34(CZO[33]),
+    .CZO35(CZO[34]),
+    .CZO36(CZO[35]),
+    .CZO37(CZO[36]),
+    .CZO38(CZO[37]),
+    .CZO39(CZO[38]),
+    .CZO40(CZO[39]),
+    .CZO41(CZO[40]),
+    .CZO42(CZO[41]),
+    .CZO43(CZO[42]),
+    .CZO44(CZO[43]),
+    .CZO45(CZO[44]),
+    .CZO46(CZO[45]),
+    .CZO47(CZO[46]),
+    .CZO48(CZO[47]),
+    .CZO49(CZO[48]),
+    .CZO50(CZO[49]),
+    .CZO51(CZO[50]),
+    .CZO52(CZO[51]),
+    .CZO53(CZO[52]),
+    .CZO54(CZO[53]),
+    .CZO55(CZO[54]),
+    .CZO56(CZO[55]),
+
+    .D1(D[0]),
+    .D2(D[1]),
+    .D3(D[2]),
+    .D4(D[3]),
+    .D5(D[4]),
+    .D6(D[5]),
+    .D7(D[6]),
+    .D8(D[7]),
+    .D9(D[8]),
+    .D10(D[9]),
+    .D11(D[10]),
+    .D12(D[11]),
+    .D13(D[12]),
+    .D14(D[13]),
+    .D15(D[14]),
+    .D16(D[15]),
+    .D17(D[16]),
+    .D18(D[17]),
+
+    .OVF(OVF),
+    .R(R),
+    .RZ(RZ),
+    .WE(WE),
+
+    .Z1(Z[0]),
+    .Z2(Z[1]),
+    .Z3(Z[2]),
+    .Z4(Z[3]),
+    .Z5(Z[4]),
+    .Z6(Z[5]),
+    .Z7(Z[6]),
+    .Z8(Z[7]),
+    .Z9(Z[8]),
+    .Z10(Z[9]),
+    .Z11(Z[10]),
+    .Z12(Z[11]),
+    .Z13(Z[12]),
+    .Z14(Z[13]),
+    .Z15(Z[14]),
+    .Z16(Z[15]),
+    .Z17(Z[16]),
+    .Z18(Z[17]),
+    .Z19(Z[18]),
+    .Z20(Z[19]),
+    .Z21(Z[20]),
+    .Z22(Z[21]),
+    .Z23(Z[22]),
+    .Z24(Z[23]),
+    .Z25(Z[24]),
+    .Z26(Z[25]),
+    .Z27(Z[26]),
+    .Z28(Z[27]),
+    .Z29(Z[28]),
+    .Z30(Z[29]),
+    .Z31(Z[30]),
+    .Z32(Z[31]),
+    .Z33(Z[32]),
+    .Z34(Z[33]),
+    .Z35(Z[34]),
+    .Z36(Z[35]),
+    .Z37(Z[36]),
+    .Z38(Z[37]),
+    .Z39(Z[38]),
+    .Z40(Z[39]),
+    .Z41(Z[40]),
+    .Z42(Z[41]),
+    .Z43(Z[42]),
+    .Z44(Z[43]),
+    .Z45(Z[44]),
+    .Z46(Z[45]),
+    .Z47(Z[46]),
+    .Z48(Z[47]),
+    .Z49(Z[48]),
+    .Z50(Z[49]),
+    .Z51(Z[50]),
+    .Z52(Z[51]),
+    .Z53(Z[52]),
+    .Z54(Z[53]),
+    .Z55(Z[54]),
+    .Z56(Z[55])
+  );
+endmodule
+
diff --git a/techlibs/nanoxplore/cells_wrap_m.v b/techlibs/nanoxplore/cells_wrap_m.v
index 04c9cd66735..f66bc636e32 100644
--- a/techlibs/nanoxplore/cells_wrap_m.v
+++ b/techlibs/nanoxplore/cells_wrap_m.v
@@ -446,3 +446,402 @@ localparam RAW_CONFIG3_GEN = { ALU_MUX,  ALU_OP };
     .Z56(Z[55])
   );
 endmodule
+
+module NX_DSP_WRAP(CCI, CCO, CI, CK, CO, CO37, CO49, OVF, R, RZ, WE, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
+, CZO);
+    input [23:0] A;
+    input [17:0] B;
+    input [35:0] C;
+    input [17:0] CAI;
+    output [17:0] CAO;
+    input [17:0] CBI;
+    output [17:0] CBO;
+    input CCI;
+    output CCO;
+    input CI;
+    input CK;
+    output CO;
+    output CO37;
+    output CO49;
+    input [55:0] CZI;
+    output [55:0] CZO;
+    input [17:0] D;
+    output OVF;
+    input R;
+    input RZ;
+    input WE;
+    output [55:0] Z;
+    parameter raw_config0 = 20'b00000000000000000000;
+    parameter raw_config1 = 19'b0000000000000000000;
+    parameter raw_config2 = 13'b0000000000000;
+    parameter raw_config3 = 7'b0000000;
+    parameter std_mode = "";
+
+  NX_DSP #(
+    .std_mode(std_mode),
+    .raw_config0(raw_config0),
+    .raw_config1(raw_config1),
+    .raw_config2(raw_config2),
+    .raw_config3(raw_config3),
+  ) _TECHMAP_REPLACE_ (
+    .A1(A[0]),
+    .A2(A[1]),
+    .A3(A[2]),
+    .A4(A[3]),
+    .A5(A[4]),
+    .A6(A[5]),
+    .A7(A[6]),
+    .A8(A[7]),
+    .A9(A[8]),
+    .A10(A[9]),
+    .A11(A[10]),
+    .A12(A[11]),
+    .A13(A[12]),
+    .A14(A[13]),
+    .A15(A[14]),
+    .A16(A[15]),
+    .A17(A[16]),
+    .A18(A[17]),
+    .A19(A[18]),
+    .A20(A[19]),
+    .A21(A[20]),
+    .A22(A[21]),
+    .A23(A[22]),
+    .A24(A[23]),
+
+    .B1(B[0]),
+    .B2(B[1]),
+    .B3(B[2]),
+    .B4(B[3]),
+    .B5(B[4]),
+    .B6(B[5]),
+    .B7(B[6]),
+    .B8(B[7]),
+    .B9(B[8]),
+    .B10(B[9]),
+    .B11(B[10]),
+    .B12(B[11]),
+    .B13(B[12]),
+    .B14(B[13]),
+    .B15(B[14]),
+    .B16(B[15]),
+    .B17(B[16]),
+    .B18(B[17]),
+
+    .C1(C[0]),
+    .C2(C[1]),
+    .C3(C[2]),
+    .C4(C[3]),
+    .C5(C[4]),
+    .C6(C[5]),
+    .C7(C[6]),
+    .C8(C[7]),
+    .C9(C[8]),
+    .C10(C[9]),
+    .C11(C[10]),
+    .C12(C[11]),
+    .C13(C[12]),
+    .C14(C[13]),
+    .C15(C[14]),
+    .C16(C[15]),
+    .C17(C[16]),
+    .C18(C[17]),
+    .C19(C[18]),
+    .C20(C[19]),
+    .C21(C[20]),
+    .C22(C[21]),
+    .C23(C[22]),
+    .C24(C[23]),
+    .C25(C[24]),
+    .C26(C[25]),
+    .C27(C[26]),
+    .C28(C[27]),
+    .C29(C[28]),
+    .C30(C[29]),
+    .C31(C[30]),
+    .C32(C[31]),
+    .C33(C[32]),
+    .C34(C[33]),
+    .C35(C[34]),
+    .C36(C[35]),
+
+    .CAI1(CAI[0]),
+    .CAI2(CAI[1]),
+    .CAI3(CAI[2]),
+    .CAI4(CAI[3]),
+    .CAI5(CAI[4]),
+    .CAI6(CAI[5]),
+    .CAI7(CAI[6]),
+    .CAI8(CAI[7]),
+    .CAI9(CAI[8]),
+    .CAI10(CAI[9]),
+    .CAI11(CAI[10]),
+    .CAI12(CAI[11]),
+    .CAI13(CAI[12]),
+    .CAI14(CAI[13]),
+    .CAI15(CAI[14]),
+    .CAI16(CAI[15]),
+    .CAI17(CAI[16]),
+    .CAI18(CAI[17]),
+
+    .CAO1(CAO[0]),
+    .CAO2(CAO[1]),
+    .CAO3(CAO[2]),
+    .CAO4(CAO[3]),
+    .CAO5(CAO[4]),
+    .CAO6(CAO[5]),
+    .CAO7(CAO[6]),
+    .CAO8(CAO[7]),
+    .CAO9(CAO[8]),
+    .CAO10(CAO[9]),
+    .CAO11(CAO[10]),
+    .CAO12(CAO[11]),
+    .CAO13(CAO[12]),
+    .CAO14(CAO[13]),
+    .CAO15(CAO[14]),
+    .CAO16(CAO[15]),
+    .CAO17(CAO[16]),
+    .CAO18(CAO[17]),
+
+    .CBI1(CBI[0]),
+    .CBI2(CBI[1]),
+    .CBI3(CBI[2]),
+    .CBI4(CBI[3]),
+    .CBI5(CBI[4]),
+    .CBI6(CBI[5]),
+    .CBI7(CBI[6]),
+    .CBI8(CBI[7]),
+    .CBI9(CBI[8]),
+    .CBI10(CBI[9]),
+    .CBI11(CBI[10]),
+    .CBI12(CBI[11]),
+    .CBI13(CBI[12]),
+    .CBI14(CBI[13]),
+    .CBI15(CBI[14]),
+    .CBI16(CBI[15]),
+    .CBI17(CBI[16]),
+    .CBI18(CBI[17]),
+
+    .CBO1(CBO[0]),
+    .CBO2(CBO[1]),
+    .CBO3(CBO[2]),
+    .CBO4(CBO[3]),
+    .CBO5(CBO[4]),
+    .CBO6(CBO[5]),
+    .CBO7(CBO[6]),
+    .CBO8(CBO[7]),
+    .CBO9(CBO[8]),
+    .CBO10(CBO[9]),
+    .CBO11(CBO[10]),
+    .CBO12(CBO[11]),
+    .CBO13(CBO[12]),
+    .CBO14(CBO[13]),
+    .CBO15(CBO[14]),
+    .CBO16(CBO[15]),
+    .CBO17(CBO[16]),
+    .CBO18(CBO[17]),
+
+    .CCI(CCI),
+    .CCO(CCO),
+    .CI(CI),
+    .CK(CK),
+    .CO(CO),
+    .CO37(CO36),
+    .CO49(CO48),
+
+    .CZI1(CZI[0]),
+    .CZI2(CZI[1]),
+    .CZI3(CZI[2]),
+    .CZI4(CZI[3]),
+    .CZI5(CZI[4]),
+    .CZI6(CZI[5]),
+    .CZI7(CZI[6]),
+    .CZI8(CZI[7]),
+    .CZI9(CZI[8]),
+    .CZI10(CZI[9]),
+    .CZI11(CZI[10]),
+    .CZI12(CZI[11]),
+    .CZI13(CZI[12]),
+    .CZI14(CZI[13]),
+    .CZI15(CZI[14]),
+    .CZI16(CZI[15]),
+    .CZI17(CZI[16]),
+    .CZI18(CZI[17]),
+    .CZI19(CZI[18]),
+    .CZI20(CZI[19]),
+    .CZI21(CZI[20]),
+    .CZI22(CZI[21]),
+    .CZI23(CZI[22]),
+    .CZI24(CZI[23]),
+    .CZI25(CZI[24]),
+    .CZI26(CZI[25]),
+    .CZI27(CZI[26]),
+    .CZI28(CZI[27]),
+    .CZI29(CZI[28]),
+    .CZI30(CZI[29]),
+    .CZI31(CZI[30]),
+    .CZI32(CZI[31]),
+    .CZI33(CZI[32]),
+    .CZI34(CZI[33]),
+    .CZI35(CZI[34]),
+    .CZI36(CZI[35]),
+    .CZI37(CZI[36]),
+    .CZI38(CZI[37]),
+    .CZI39(CZI[38]),
+    .CZI40(CZI[39]),
+    .CZI41(CZI[40]),
+    .CZI42(CZI[41]),
+    .CZI43(CZI[42]),
+    .CZI44(CZI[43]),
+    .CZI45(CZI[44]),
+    .CZI46(CZI[45]),
+    .CZI47(CZI[46]),
+    .CZI48(CZI[47]),
+    .CZI49(CZI[48]),
+    .CZI50(CZI[49]),
+    .CZI51(CZI[50]),
+    .CZI52(CZI[51]),
+    .CZI53(CZI[52]),
+    .CZI54(CZI[53]),
+    .CZI55(CZI[54]),
+    .CZI56(CZI[55]),
+
+    .CZO1(CZO[0]),
+    .CZO2(CZO[1]),
+    .CZO3(CZO[2]),
+    .CZO4(CZO[3]),
+    .CZO5(CZO[4]),
+    .CZO6(CZO[5]),
+    .CZO7(CZO[6]),
+    .CZO8(CZO[7]),
+    .CZO9(CZO[8]),
+    .CZO10(CZO[9]),
+    .CZO11(CZO[10]),
+    .CZO12(CZO[11]),
+    .CZO13(CZO[12]),
+    .CZO14(CZO[13]),
+    .CZO15(CZO[14]),
+    .CZO16(CZO[15]),
+    .CZO17(CZO[16]),
+    .CZO18(CZO[17]),
+    .CZO19(CZO[18]),
+    .CZO20(CZO[19]),
+    .CZO21(CZO[20]),
+    .CZO22(CZO[21]),
+    .CZO23(CZO[22]),
+    .CZO24(CZO[23]),
+    .CZO25(CZO[24]),
+    .CZO26(CZO[25]),
+    .CZO27(CZO[26]),
+    .CZO28(CZO[27]),
+    .CZO29(CZO[28]),
+    .CZO30(CZO[29]),
+    .CZO31(CZO[30]),
+    .CZO32(CZO[31]),
+    .CZO33(CZO[32]),
+    .CZO34(CZO[33]),
+    .CZO35(CZO[34]),
+    .CZO36(CZO[35]),
+    .CZO37(CZO[36]),
+    .CZO38(CZO[37]),
+    .CZO39(CZO[38]),
+    .CZO40(CZO[39]),
+    .CZO41(CZO[40]),
+    .CZO42(CZO[41]),
+    .CZO43(CZO[42]),
+    .CZO44(CZO[43]),
+    .CZO45(CZO[44]),
+    .CZO46(CZO[45]),
+    .CZO47(CZO[46]),
+    .CZO48(CZO[47]),
+    .CZO49(CZO[48]),
+    .CZO50(CZO[49]),
+    .CZO51(CZO[50]),
+    .CZO52(CZO[51]),
+    .CZO53(CZO[52]),
+    .CZO54(CZO[53]),
+    .CZO55(CZO[54]),
+    .CZO56(CZO[55]),
+
+    .D1(D[0]),
+    .D2(D[1]),
+    .D3(D[2]),
+    .D4(D[3]),
+    .D5(D[4]),
+    .D6(D[5]),
+    .D7(D[6]),
+    .D8(D[7]),
+    .D9(D[8]),
+    .D10(D[9]),
+    .D11(D[10]),
+    .D12(D[11]),
+    .D13(D[12]),
+    .D14(D[13]),
+    .D15(D[14]),
+    .D16(D[15]),
+    .D17(D[16]),
+    .D18(D[17]),
+
+    .OVF(OVF),
+    .R(R),
+    .RZ(RZ),
+    .WE(WE),
+
+    .Z1(Z[0]),
+    .Z2(Z[1]),
+    .Z3(Z[2]),
+    .Z4(Z[3]),
+    .Z5(Z[4]),
+    .Z6(Z[5]),
+    .Z7(Z[6]),
+    .Z8(Z[7]),
+    .Z9(Z[8]),
+    .Z10(Z[9]),
+    .Z11(Z[10]),
+    .Z12(Z[11]),
+    .Z13(Z[12]),
+    .Z14(Z[13]),
+    .Z15(Z[14]),
+    .Z16(Z[15]),
+    .Z17(Z[16]),
+    .Z18(Z[17]),
+    .Z19(Z[18]),
+    .Z20(Z[19]),
+    .Z21(Z[20]),
+    .Z22(Z[21]),
+    .Z23(Z[22]),
+    .Z24(Z[23]),
+    .Z25(Z[24]),
+    .Z26(Z[25]),
+    .Z27(Z[26]),
+    .Z28(Z[27]),
+    .Z29(Z[28]),
+    .Z30(Z[29]),
+    .Z31(Z[30]),
+    .Z32(Z[31]),
+    .Z33(Z[32]),
+    .Z34(Z[33]),
+    .Z35(Z[34]),
+    .Z36(Z[35]),
+    .Z37(Z[36]),
+    .Z38(Z[37]),
+    .Z39(Z[38]),
+    .Z40(Z[39]),
+    .Z41(Z[40]),
+    .Z42(Z[41]),
+    .Z43(Z[42]),
+    .Z44(Z[43]),
+    .Z45(Z[44]),
+    .Z46(Z[45]),
+    .Z47(Z[46]),
+    .Z48(Z[47]),
+    .Z49(Z[48]),
+    .Z50(Z[49]),
+    .Z51(Z[50]),
+    .Z52(Z[51]),
+    .Z53(Z[52]),
+    .Z54(Z[53]),
+    .Z55(Z[54]),
+    .Z56(Z[55])
+  );
+endmodule
diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v
index ec536990620..7f7fda78983 100644
--- a/techlibs/nanoxplore/cells_wrap_u.v
+++ b/techlibs/nanoxplore/cells_wrap_u.v
@@ -466,3 +466,886 @@ module NX_CDC_U_GRAY2BIN(BI, AO, BO, AI);
   );
 endmodule
 
+module NX_DSP_U_SPLIT(CK, R, RZ, WE, WEZ, CI, CCI, CO42, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO, CZO);
+    input [23:0] A;
+    input [17:0] B;
+    input [35:0] C;
+    input [23:0] CAI;
+    output [23:0] CAO;
+    input [17:0] CBI;
+    output [17:0] CBO;
+    input CCI;
+    output CCO;
+    input CI;
+    input CK;
+    output CO42;
+    output CO56;
+    input [55:0] CZI;
+    output [55:0] CZO;
+    input [17:0] D;
+    output OVF;
+    input R;
+    input RZ;
+    input WE;
+    input WEZ;
+    output [55:0] Z;
+    parameter ALU_DYNAMIC_OP = 2'b00;
+    parameter ALU_OP = 3'b000;
+    parameter ENABLE_PR_A_RST = 1'b0;
+    parameter ENABLE_PR_B_RST = 1'b0;
+    parameter ENABLE_PR_CCO_RST = 1'b0;
+    parameter ENABLE_PR_CI_RST = 1'b0;
+    parameter ENABLE_PR_CO_RST = 1'b0;
+    parameter ENABLE_PR_CZ_RST = 1'b0;
+    parameter ENABLE_PR_C_RST = 1'b0;
+    parameter ENABLE_PR_D_RST = 1'b0;
+    parameter ENABLE_PR_MULT_RST = 1'b0;
+    parameter ENABLE_PR_OV_RST = 1'b0;
+    parameter ENABLE_PR_P_RST = 1'b0;
+    parameter ENABLE_PR_X_RST = 1'b0;
+    parameter ENABLE_PR_Y_RST = 1'b0;
+    parameter ENABLE_PR_Z_RST = 1'b0;
+    parameter ENABLE_SATURATION = 1'b0;
+    parameter INV_RST = 1'b0;
+    parameter INV_RSTZ = 1'b0;
+    parameter INV_WE = 1'b0;
+    parameter INV_WEZ = 1'b0;
+    parameter MUX_A = 1'b0;
+    parameter MUX_B = 1'b0;
+    parameter MUX_CCI = 1'b0;
+    parameter MUX_CCO = 1'b0;
+    parameter MUX_CI = 1'b0;
+    parameter MUX_CZ = 1'b0;
+    parameter MUX_P = 1'b0;
+    parameter MUX_X = 3'b000;
+    parameter MUX_Y = 1'b0;
+    parameter MUX_Z = 1'b0;
+    parameter PRE_ADDER_OP = 1'b0;
+    parameter PR_A_CASCADE_MUX = 2'b00;
+    parameter PR_A_MUX = 2'b00;
+    parameter PR_B_CASCADE_MUX = 2'b00;
+    parameter PR_B_MUX = 2'b00;
+    parameter PR_CCO_MUX = 1'b0;
+    parameter PR_CI_MUX = 1'b0;
+    parameter PR_CO_MUX = 1'b0;
+    parameter PR_CZ_MUX = 1'b0;
+    parameter PR_C_MUX = 1'b0;
+    parameter PR_D_MUX = 1'b0;
+    parameter PR_MULT_MUX = 1'b0;
+    parameter PR_OV_MUX = 1'b0;
+    parameter PR_P_MUX = 1'b0;
+    parameter PR_RSTZ_MUX = 1'b0;
+    parameter PR_RST_MUX = 1'b0;
+    parameter PR_WEZ_MUX = 1'b0;
+    parameter PR_WE_MUX = 1'b0;
+    parameter PR_X_MUX = 1'b0;
+    parameter PR_Y_MUX = 1'b0;
+    parameter PR_Z_MUX = 1'b0;
+    parameter SATURATION_RANK = 6'b000000;
+    parameter SIGNED_MODE = 1'b0;
+
+    localparam RAW_CONFIG0_GEN = { INV_WE, INV_WEZ, INV_RST, INV_RSTZ, MUX_CCO, ALU_DYNAMIC_OP, SATURATION_RANK,
+     ENABLE_SATURATION, MUX_Z, MUX_CCI, MUX_CI, MUX_Y, MUX_CZ, MUX_X, MUX_P,
+     MUX_B, MUX_A, PRE_ADDER_OP, SIGNED_MODE };
+
+    localparam RAW_CONFIG1_GEN = { PR_WE_MUX, PR_WEZ_MUX, PR_RST_MUX, PR_RSTZ_MUX, PR_OV_MUX, PR_CO_MUX, PR_CCO_MUX,
+    PR_Z_MUX, PR_CZ_MUX, PR_Y_MUX, PR_X_MUX, PR_CI_MUX, PR_MULT_MUX, PR_P_MUX, PR_D_MUX,
+    PR_C_MUX, PR_B_CASCADE_MUX, PR_B_MUX, PR_A_CASCADE_MUX, PR_A_MUX };
+
+    localparam RAW_CONFIG2_GEN = { ENABLE_PR_OV_RST, ENABLE_PR_CO_RST, ENABLE_PR_CCO_RST, ENABLE_PR_Z_RST, ENABLE_PR_CZ_RST,
+    ENABLE_PR_MULT_RST, ENABLE_PR_Y_RST, ENABLE_PR_X_RST, ENABLE_PR_P_RST, ENABLE_PR_CI_RST,
+    ENABLE_PR_D_RST, ENABLE_PR_C_RST, ENABLE_PR_B_RST, ENABLE_PR_A_RST };
+
+    localparam RAW_CONFIG3_GEN = { ALU_OP };
+
+  NX_DSP_U #(
+    .std_mode(""),
+    .raw_config0(RAW_CONFIG0_GEN),
+    .raw_config1(RAW_CONFIG1_GEN),
+    .raw_config2(RAW_CONFIG2_GEN),
+    .raw_config3(RAW_CONFIG3_GEN)
+  ) _TECHMAP_REPLACE_ (
+    .A1(A[0]),
+    .A2(A[1]),
+    .A3(A[2]),
+    .A4(A[3]),
+    .A5(A[4]),
+    .A6(A[5]),
+    .A7(A[6]),
+    .A8(A[7]),
+    .A9(A[8]),
+    .A10(A[9]),
+    .A11(A[10]),
+    .A12(A[11]),
+    .A13(A[12]),
+    .A14(A[13]),
+    .A15(A[14]),
+    .A16(A[15]),
+    .A17(A[16]),
+    .A18(A[17]),
+    .A19(A[18]),
+    .A20(A[19]),
+    .A21(A[20]),
+    .A22(A[21]),
+    .A23(A[22]),
+    .A24(A[23]),
+
+    .B1(B[0]),
+    .B2(B[1]),
+    .B3(B[2]),
+    .B4(B[3]),
+    .B5(B[4]),
+    .B6(B[5]),
+    .B7(B[6]),
+    .B8(B[7]),
+    .B9(B[8]),
+    .B10(B[9]),
+    .B11(B[10]),
+    .B12(B[11]),
+    .B13(B[12]),
+    .B14(B[13]),
+    .B15(B[14]),
+    .B16(B[15]),
+    .B17(B[16]),
+    .B18(B[17]),
+
+    .C1(C[0]),
+    .C2(C[1]),
+    .C3(C[2]),
+    .C4(C[3]),
+    .C5(C[4]),
+    .C6(C[5]),
+    .C7(C[6]),
+    .C8(C[7]),
+    .C9(C[8]),
+    .C10(C[9]),
+    .C11(C[10]),
+    .C12(C[11]),
+    .C13(C[12]),
+    .C14(C[13]),
+    .C15(C[14]),
+    .C16(C[15]),
+    .C17(C[16]),
+    .C18(C[17]),
+    .C19(C[18]),
+    .C20(C[19]),
+    .C21(C[20]),
+    .C22(C[21]),
+    .C23(C[22]),
+    .C24(C[23]),
+    .C25(C[24]),
+    .C26(C[25]),
+    .C27(C[26]),
+    .C28(C[27]),
+    .C29(C[28]),
+    .C30(C[29]),
+    .C31(C[30]),
+    .C32(C[31]),
+    .C33(C[32]),
+    .C34(C[33]),
+    .C35(C[34]),
+    .C36(C[35]),
+
+    .CAI1(CAI[0]),
+    .CAI2(CAI[1]),
+    .CAI3(CAI[2]),
+    .CAI4(CAI[3]),
+    .CAI5(CAI[4]),
+    .CAI6(CAI[5]),
+    .CAI7(CAI[6]),
+    .CAI8(CAI[7]),
+    .CAI9(CAI[8]),
+    .CAI10(CAI[9]),
+    .CAI11(CAI[10]),
+    .CAI12(CAI[11]),
+    .CAI13(CAI[12]),
+    .CAI14(CAI[13]),
+    .CAI15(CAI[14]),
+    .CAI16(CAI[15]),
+    .CAI17(CAI[16]),
+    .CAI18(CAI[17]),
+    .CAI19(CAI[18]),
+    .CAI20(CAI[19]),
+    .CAI21(CAI[20]),
+    .CAI22(CAI[21]),
+    .CAI23(CAI[22]),
+    .CAI24(CAI[23]),
+
+    .CAO1(CAO[0]),
+    .CAO2(CAO[1]),
+    .CAO3(CAO[2]),
+    .CAO4(CAO[3]),
+    .CAO5(CAO[4]),
+    .CAO6(CAO[5]),
+    .CAO7(CAO[6]),
+    .CAO8(CAO[7]),
+    .CAO9(CAO[8]),
+    .CAO10(CAO[9]),
+    .CAO11(CAO[10]),
+    .CAO12(CAO[11]),
+    .CAO13(CAO[12]),
+    .CAO14(CAO[13]),
+    .CAO15(CAO[14]),
+    .CAO16(CAO[15]),
+    .CAO17(CAO[16]),
+    .CAO18(CAO[17]),
+    .CAO19(CAO[18]),
+    .CAO20(CAO[19]),
+    .CAO21(CAO[20]),
+    .CAO22(CAO[21]),
+    .CAO23(CAO[22]),
+    .CAO24(CAO[23]),
+
+    .CBI1(CBI[0]),
+    .CBI2(CBI[1]),
+    .CBI3(CBI[2]),
+    .CBI4(CBI[3]),
+    .CBI5(CBI[4]),
+    .CBI6(CBI[5]),
+    .CBI7(CBI[6]),
+    .CBI8(CBI[7]),
+    .CBI9(CBI[8]),
+    .CBI10(CBI[9]),
+    .CBI11(CBI[10]),
+    .CBI12(CBI[11]),
+    .CBI13(CBI[12]),
+    .CBI14(CBI[13]),
+    .CBI15(CBI[14]),
+    .CBI16(CBI[15]),
+    .CBI17(CBI[16]),
+    .CBI18(CBI[17]),
+
+    .CBO1(CBO[0]),
+    .CBO2(CBO[1]),
+    .CBO3(CBO[2]),
+    .CBO4(CBO[3]),
+    .CBO5(CBO[4]),
+    .CBO6(CBO[5]),
+    .CBO7(CBO[6]),
+    .CBO8(CBO[7]),
+    .CBO9(CBO[8]),
+    .CBO10(CBO[9]),
+    .CBO11(CBO[10]),
+    .CBO12(CBO[11]),
+    .CBO13(CBO[12]),
+    .CBO14(CBO[13]),
+    .CBO15(CBO[14]),
+    .CBO16(CBO[15]),
+    .CBO17(CBO[16]),
+    .CBO18(CBO[17]),
+
+    .CCI(CCI),
+    .CCO(CCO),
+    .CI(CI),
+    .CK(CK),
+    .CO43(CO42),
+    .CO57(CO56),
+
+    .CZI1(CZI[0]),
+    .CZI2(CZI[1]),
+    .CZI3(CZI[2]),
+    .CZI4(CZI[3]),
+    .CZI5(CZI[4]),
+    .CZI6(CZI[5]),
+    .CZI7(CZI[6]),
+    .CZI8(CZI[7]),
+    .CZI9(CZI[8]),
+    .CZI10(CZI[9]),
+    .CZI11(CZI[10]),
+    .CZI12(CZI[11]),
+    .CZI13(CZI[12]),
+    .CZI14(CZI[13]),
+    .CZI15(CZI[14]),
+    .CZI16(CZI[15]),
+    .CZI17(CZI[16]),
+    .CZI18(CZI[17]),
+    .CZI19(CZI[18]),
+    .CZI20(CZI[19]),
+    .CZI21(CZI[20]),
+    .CZI22(CZI[21]),
+    .CZI23(CZI[22]),
+    .CZI24(CZI[23]),
+    .CZI25(CZI[24]),
+    .CZI26(CZI[25]),
+    .CZI27(CZI[26]),
+    .CZI28(CZI[27]),
+    .CZI29(CZI[28]),
+    .CZI30(CZI[29]),
+    .CZI31(CZI[30]),
+    .CZI32(CZI[31]),
+    .CZI33(CZI[32]),
+    .CZI34(CZI[33]),
+    .CZI35(CZI[34]),
+    .CZI36(CZI[35]),
+    .CZI37(CZI[36]),
+    .CZI38(CZI[37]),
+    .CZI39(CZI[38]),
+    .CZI40(CZI[39]),
+    .CZI41(CZI[40]),
+    .CZI42(CZI[41]),
+    .CZI43(CZI[42]),
+    .CZI44(CZI[43]),
+    .CZI45(CZI[44]),
+    .CZI46(CZI[45]),
+    .CZI47(CZI[46]),
+    .CZI48(CZI[47]),
+    .CZI49(CZI[48]),
+    .CZI50(CZI[49]),
+    .CZI51(CZI[50]),
+    .CZI52(CZI[51]),
+    .CZI53(CZI[52]),
+    .CZI54(CZI[53]),
+    .CZI55(CZI[54]),
+    .CZI56(CZI[55]),
+
+    .CZO1(CZO[0]),
+    .CZO2(CZO[1]),
+    .CZO3(CZO[2]),
+    .CZO4(CZO[3]),
+    .CZO5(CZO[4]),
+    .CZO6(CZO[5]),
+    .CZO7(CZO[6]),
+    .CZO8(CZO[7]),
+    .CZO9(CZO[8]),
+    .CZO10(CZO[9]),
+    .CZO11(CZO[10]),
+    .CZO12(CZO[11]),
+    .CZO13(CZO[12]),
+    .CZO14(CZO[13]),
+    .CZO15(CZO[14]),
+    .CZO16(CZO[15]),
+    .CZO17(CZO[16]),
+    .CZO18(CZO[17]),
+    .CZO19(CZO[18]),
+    .CZO20(CZO[19]),
+    .CZO21(CZO[20]),
+    .CZO22(CZO[21]),
+    .CZO23(CZO[22]),
+    .CZO24(CZO[23]),
+    .CZO25(CZO[24]),
+    .CZO26(CZO[25]),
+    .CZO27(CZO[26]),
+    .CZO28(CZO[27]),
+    .CZO29(CZO[28]),
+    .CZO30(CZO[29]),
+    .CZO31(CZO[30]),
+    .CZO32(CZO[31]),
+    .CZO33(CZO[32]),
+    .CZO34(CZO[33]),
+    .CZO35(CZO[34]),
+    .CZO36(CZO[35]),
+    .CZO37(CZO[36]),
+    .CZO38(CZO[37]),
+    .CZO39(CZO[38]),
+    .CZO40(CZO[39]),
+    .CZO41(CZO[40]),
+    .CZO42(CZO[41]),
+    .CZO43(CZO[42]),
+    .CZO44(CZO[43]),
+    .CZO45(CZO[44]),
+    .CZO46(CZO[45]),
+    .CZO47(CZO[46]),
+    .CZO48(CZO[47]),
+    .CZO49(CZO[48]),
+    .CZO50(CZO[49]),
+    .CZO51(CZO[50]),
+    .CZO52(CZO[51]),
+    .CZO53(CZO[52]),
+    .CZO54(CZO[53]),
+    .CZO55(CZO[54]),
+    .CZO56(CZO[55]),
+
+    .D1(D[0]),
+    .D2(D[1]),
+    .D3(D[2]),
+    .D4(D[3]),
+    .D5(D[4]),
+    .D6(D[5]),
+    .D7(D[6]),
+    .D8(D[7]),
+    .D9(D[8]),
+    .D10(D[9]),
+    .D11(D[10]),
+    .D12(D[11]),
+    .D13(D[12]),
+    .D14(D[13]),
+    .D15(D[14]),
+    .D16(D[15]),
+    .D17(D[16]),
+    .D18(D[17]),
+
+    .OVF(OVF),
+    .R(R),
+    .RZ(RZ),
+    .WE(WE),
+    .WEZ(WEZ),
+
+    .Z1(Z[0]),
+    .Z2(Z[1]),
+    .Z3(Z[2]),
+    .Z4(Z[3]),
+    .Z5(Z[4]),
+    .Z6(Z[5]),
+    .Z7(Z[6]),
+    .Z8(Z[7]),
+    .Z9(Z[8]),
+    .Z10(Z[9]),
+    .Z11(Z[10]),
+    .Z12(Z[11]),
+    .Z13(Z[12]),
+    .Z14(Z[13]),
+    .Z15(Z[14]),
+    .Z16(Z[15]),
+    .Z17(Z[16]),
+    .Z18(Z[17]),
+    .Z19(Z[18]),
+    .Z20(Z[19]),
+    .Z21(Z[20]),
+    .Z22(Z[21]),
+    .Z23(Z[22]),
+    .Z24(Z[23]),
+    .Z25(Z[24]),
+    .Z26(Z[25]),
+    .Z27(Z[26]),
+    .Z28(Z[27]),
+    .Z29(Z[28]),
+    .Z30(Z[29]),
+    .Z31(Z[30]),
+    .Z32(Z[31]),
+    .Z33(Z[32]),
+    .Z34(Z[33]),
+    .Z35(Z[34]),
+    .Z36(Z[35]),
+    .Z37(Z[36]),
+    .Z38(Z[37]),
+    .Z39(Z[38]),
+    .Z40(Z[39]),
+    .Z41(Z[40]),
+    .Z42(Z[41]),
+    .Z43(Z[42]),
+    .Z44(Z[43]),
+    .Z45(Z[44]),
+    .Z46(Z[45]),
+    .Z47(Z[46]),
+    .Z48(Z[47]),
+    .Z49(Z[48]),
+    .Z50(Z[49]),
+    .Z51(Z[50]),
+    .Z52(Z[51]),
+    .Z53(Z[52]),
+    .Z54(Z[53]),
+    .Z55(Z[54]),
+    .Z56(Z[55])
+  );
+endmodule
+
+module NX_DSP_U_WRAP(CCI, CCO, CI, CK, CO43, CO57, OVF, R, RZ, WE, WEZ, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
+, CZO);
+    input [23:0] A;
+    input [17:0] B;
+    input [35:0] C;
+    input [23:0] CAI;
+    output [23:0] CAO;
+    input [17:0] CBI;
+    output [17:0] CBO;
+    input CCI;
+    output CCO;
+    input CI;
+    input CK;
+    output CO43;
+    output CO57;
+    input [55:0] CZI;
+    output [55:0] CZO;
+    input [17:0] D;
+    output OVF;
+    input R;
+    input RZ;
+    input WE;
+    input WEZ;
+    output [55:0] Z;
+    parameter raw_config0 = 27'b000000000000000000000000000;
+    parameter raw_config1 = 24'b000000000000000000000000;
+    parameter raw_config2 = 14'b00000000000000;
+    parameter raw_config3 = 3'b000;
+    parameter std_mode = "";
+
+  NX_DSP_U #(
+    .std_mode(std_mode),
+    .raw_config0(raw_config0),
+    .raw_config1(raw_config1),
+    .raw_config2(raw_config2),
+    .raw_config3(raw_config3)
+  ) _TECHMAP_REPLACE_ (
+    .A1(A[0]),
+    .A2(A[1]),
+    .A3(A[2]),
+    .A4(A[3]),
+    .A5(A[4]),
+    .A6(A[5]),
+    .A7(A[6]),
+    .A8(A[7]),
+    .A9(A[8]),
+    .A10(A[9]),
+    .A11(A[10]),
+    .A12(A[11]),
+    .A13(A[12]),
+    .A14(A[13]),
+    .A15(A[14]),
+    .A16(A[15]),
+    .A17(A[16]),
+    .A18(A[17]),
+    .A19(A[18]),
+    .A20(A[19]),
+    .A21(A[20]),
+    .A22(A[21]),
+    .A23(A[22]),
+    .A24(A[23]),
+
+    .B1(B[0]),
+    .B2(B[1]),
+    .B3(B[2]),
+    .B4(B[3]),
+    .B5(B[4]),
+    .B6(B[5]),
+    .B7(B[6]),
+    .B8(B[7]),
+    .B9(B[8]),
+    .B10(B[9]),
+    .B11(B[10]),
+    .B12(B[11]),
+    .B13(B[12]),
+    .B14(B[13]),
+    .B15(B[14]),
+    .B16(B[15]),
+    .B17(B[16]),
+    .B18(B[17]),
+
+    .C1(C[0]),
+    .C2(C[1]),
+    .C3(C[2]),
+    .C4(C[3]),
+    .C5(C[4]),
+    .C6(C[5]),
+    .C7(C[6]),
+    .C8(C[7]),
+    .C9(C[8]),
+    .C10(C[9]),
+    .C11(C[10]),
+    .C12(C[11]),
+    .C13(C[12]),
+    .C14(C[13]),
+    .C15(C[14]),
+    .C16(C[15]),
+    .C17(C[16]),
+    .C18(C[17]),
+    .C19(C[18]),
+    .C20(C[19]),
+    .C21(C[20]),
+    .C22(C[21]),
+    .C23(C[22]),
+    .C24(C[23]),
+    .C25(C[24]),
+    .C26(C[25]),
+    .C27(C[26]),
+    .C28(C[27]),
+    .C29(C[28]),
+    .C30(C[29]),
+    .C31(C[30]),
+    .C32(C[31]),
+    .C33(C[32]),
+    .C34(C[33]),
+    .C35(C[34]),
+    .C36(C[35]),
+
+    .CAI1(CAI[0]),
+    .CAI2(CAI[1]),
+    .CAI3(CAI[2]),
+    .CAI4(CAI[3]),
+    .CAI5(CAI[4]),
+    .CAI6(CAI[5]),
+    .CAI7(CAI[6]),
+    .CAI8(CAI[7]),
+    .CAI9(CAI[8]),
+    .CAI10(CAI[9]),
+    .CAI11(CAI[10]),
+    .CAI12(CAI[11]),
+    .CAI13(CAI[12]),
+    .CAI14(CAI[13]),
+    .CAI15(CAI[14]),
+    .CAI16(CAI[15]),
+    .CAI17(CAI[16]),
+    .CAI18(CAI[17]),
+    .CAI19(CAI[18]),
+    .CAI20(CAI[19]),
+    .CAI21(CAI[20]),
+    .CAI22(CAI[21]),
+    .CAI23(CAI[22]),
+    .CAI24(CAI[23]),
+
+    .CAO1(CAO[0]),
+    .CAO2(CAO[1]),
+    .CAO3(CAO[2]),
+    .CAO4(CAO[3]),
+    .CAO5(CAO[4]),
+    .CAO6(CAO[5]),
+    .CAO7(CAO[6]),
+    .CAO8(CAO[7]),
+    .CAO9(CAO[8]),
+    .CAO10(CAO[9]),
+    .CAO11(CAO[10]),
+    .CAO12(CAO[11]),
+    .CAO13(CAO[12]),
+    .CAO14(CAO[13]),
+    .CAO15(CAO[14]),
+    .CAO16(CAO[15]),
+    .CAO17(CAO[16]),
+    .CAO18(CAO[17]),
+    .CAO19(CAO[18]),
+    .CAO20(CAO[19]),
+    .CAO21(CAO[20]),
+    .CAO22(CAO[21]),
+    .CAO23(CAO[22]),
+    .CAO24(CAO[23]),
+
+    .CBI1(CBI[0]),
+    .CBI2(CBI[1]),
+    .CBI3(CBI[2]),
+    .CBI4(CBI[3]),
+    .CBI5(CBI[4]),
+    .CBI6(CBI[5]),
+    .CBI7(CBI[6]),
+    .CBI8(CBI[7]),
+    .CBI9(CBI[8]),
+    .CBI10(CBI[9]),
+    .CBI11(CBI[10]),
+    .CBI12(CBI[11]),
+    .CBI13(CBI[12]),
+    .CBI14(CBI[13]),
+    .CBI15(CBI[14]),
+    .CBI16(CBI[15]),
+    .CBI17(CBI[16]),
+    .CBI18(CBI[17]),
+
+    .CBO1(CBO[0]),
+    .CBO2(CBO[1]),
+    .CBO3(CBO[2]),
+    .CBO4(CBO[3]),
+    .CBO5(CBO[4]),
+    .CBO6(CBO[5]),
+    .CBO7(CBO[6]),
+    .CBO8(CBO[7]),
+    .CBO9(CBO[8]),
+    .CBO10(CBO[9]),
+    .CBO11(CBO[10]),
+    .CBO12(CBO[11]),
+    .CBO13(CBO[12]),
+    .CBO14(CBO[13]),
+    .CBO15(CBO[14]),
+    .CBO16(CBO[15]),
+    .CBO17(CBO[16]),
+    .CBO18(CBO[17]),
+
+    .CCI(CCI),
+    .CCO(CCO),
+    .CI(CI),
+    .CK(CK),
+    .CO43(CO42),
+    .CO57(CO56),
+
+    .CZI1(CZI[0]),
+    .CZI2(CZI[1]),
+    .CZI3(CZI[2]),
+    .CZI4(CZI[3]),
+    .CZI5(CZI[4]),
+    .CZI6(CZI[5]),
+    .CZI7(CZI[6]),
+    .CZI8(CZI[7]),
+    .CZI9(CZI[8]),
+    .CZI10(CZI[9]),
+    .CZI11(CZI[10]),
+    .CZI12(CZI[11]),
+    .CZI13(CZI[12]),
+    .CZI14(CZI[13]),
+    .CZI15(CZI[14]),
+    .CZI16(CZI[15]),
+    .CZI17(CZI[16]),
+    .CZI18(CZI[17]),
+    .CZI19(CZI[18]),
+    .CZI20(CZI[19]),
+    .CZI21(CZI[20]),
+    .CZI22(CZI[21]),
+    .CZI23(CZI[22]),
+    .CZI24(CZI[23]),
+    .CZI25(CZI[24]),
+    .CZI26(CZI[25]),
+    .CZI27(CZI[26]),
+    .CZI28(CZI[27]),
+    .CZI29(CZI[28]),
+    .CZI30(CZI[29]),
+    .CZI31(CZI[30]),
+    .CZI32(CZI[31]),
+    .CZI33(CZI[32]),
+    .CZI34(CZI[33]),
+    .CZI35(CZI[34]),
+    .CZI36(CZI[35]),
+    .CZI37(CZI[36]),
+    .CZI38(CZI[37]),
+    .CZI39(CZI[38]),
+    .CZI40(CZI[39]),
+    .CZI41(CZI[40]),
+    .CZI42(CZI[41]),
+    .CZI43(CZI[42]),
+    .CZI44(CZI[43]),
+    .CZI45(CZI[44]),
+    .CZI46(CZI[45]),
+    .CZI47(CZI[46]),
+    .CZI48(CZI[47]),
+    .CZI49(CZI[48]),
+    .CZI50(CZI[49]),
+    .CZI51(CZI[50]),
+    .CZI52(CZI[51]),
+    .CZI53(CZI[52]),
+    .CZI54(CZI[53]),
+    .CZI55(CZI[54]),
+    .CZI56(CZI[55]),
+
+    .CZO1(CZO[0]),
+    .CZO2(CZO[1]),
+    .CZO3(CZO[2]),
+    .CZO4(CZO[3]),
+    .CZO5(CZO[4]),
+    .CZO6(CZO[5]),
+    .CZO7(CZO[6]),
+    .CZO8(CZO[7]),
+    .CZO9(CZO[8]),
+    .CZO10(CZO[9]),
+    .CZO11(CZO[10]),
+    .CZO12(CZO[11]),
+    .CZO13(CZO[12]),
+    .CZO14(CZO[13]),
+    .CZO15(CZO[14]),
+    .CZO16(CZO[15]),
+    .CZO17(CZO[16]),
+    .CZO18(CZO[17]),
+    .CZO19(CZO[18]),
+    .CZO20(CZO[19]),
+    .CZO21(CZO[20]),
+    .CZO22(CZO[21]),
+    .CZO23(CZO[22]),
+    .CZO24(CZO[23]),
+    .CZO25(CZO[24]),
+    .CZO26(CZO[25]),
+    .CZO27(CZO[26]),
+    .CZO28(CZO[27]),
+    .CZO29(CZO[28]),
+    .CZO30(CZO[29]),
+    .CZO31(CZO[30]),
+    .CZO32(CZO[31]),
+    .CZO33(CZO[32]),
+    .CZO34(CZO[33]),
+    .CZO35(CZO[34]),
+    .CZO36(CZO[35]),
+    .CZO37(CZO[36]),
+    .CZO38(CZO[37]),
+    .CZO39(CZO[38]),
+    .CZO40(CZO[39]),
+    .CZO41(CZO[40]),
+    .CZO42(CZO[41]),
+    .CZO43(CZO[42]),
+    .CZO44(CZO[43]),
+    .CZO45(CZO[44]),
+    .CZO46(CZO[45]),
+    .CZO47(CZO[46]),
+    .CZO48(CZO[47]),
+    .CZO49(CZO[48]),
+    .CZO50(CZO[49]),
+    .CZO51(CZO[50]),
+    .CZO52(CZO[51]),
+    .CZO53(CZO[52]),
+    .CZO54(CZO[53]),
+    .CZO55(CZO[54]),
+    .CZO56(CZO[55]),
+
+    .D1(D[0]),
+    .D2(D[1]),
+    .D3(D[2]),
+    .D4(D[3]),
+    .D5(D[4]),
+    .D6(D[5]),
+    .D7(D[6]),
+    .D8(D[7]),
+    .D9(D[8]),
+    .D10(D[9]),
+    .D11(D[10]),
+    .D12(D[11]),
+    .D13(D[12]),
+    .D14(D[13]),
+    .D15(D[14]),
+    .D16(D[15]),
+    .D17(D[16]),
+    .D18(D[17]),
+
+    .OVF(OVF),
+    .R(R),
+    .RZ(RZ),
+    .WE(WE),
+    .WEZ(WEZ),
+
+    .Z1(Z[0]),
+    .Z2(Z[1]),
+    .Z3(Z[2]),
+    .Z4(Z[3]),
+    .Z5(Z[4]),
+    .Z6(Z[5]),
+    .Z7(Z[6]),
+    .Z8(Z[7]),
+    .Z9(Z[8]),
+    .Z10(Z[9]),
+    .Z11(Z[10]),
+    .Z12(Z[11]),
+    .Z13(Z[12]),
+    .Z14(Z[13]),
+    .Z15(Z[14]),
+    .Z16(Z[15]),
+    .Z17(Z[16]),
+    .Z18(Z[17]),
+    .Z19(Z[18]),
+    .Z20(Z[19]),
+    .Z21(Z[20]),
+    .Z22(Z[21]),
+    .Z23(Z[22]),
+    .Z24(Z[23]),
+    .Z25(Z[24]),
+    .Z26(Z[25]),
+    .Z27(Z[26]),
+    .Z28(Z[27]),
+    .Z29(Z[28]),
+    .Z30(Z[29]),
+    .Z31(Z[30]),
+    .Z32(Z[31]),
+    .Z33(Z[32]),
+    .Z34(Z[33]),
+    .Z35(Z[34]),
+    .Z36(Z[35]),
+    .Z37(Z[36]),
+    .Z38(Z[37]),
+    .Z39(Z[38]),
+    .Z40(Z[39]),
+    .Z41(Z[40]),
+    .Z42(Z[41]),
+    .Z43(Z[42]),
+    .Z44(Z[43]),
+    .Z45(Z[44]),
+    .Z46(Z[45]),
+    .Z47(Z[46]),
+    .Z48(Z[47]),
+    .Z49(Z[48]),
+    .Z50(Z[49]),
+    .Z51(Z[50]),
+    .Z52(Z[51]),
+    .Z53(Z[52]),
+    .Z54(Z[53]),
+    .Z55(Z[54]),
+    .Z56(Z[55])
+  );
+endmodule
\ No newline at end of file

From 0ecc2e597fe149a94fdf56949ad1c2721e16fc79 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 12 Mar 2024 15:23:42 +0100
Subject: [PATCH 280/499] PLLs

---
 techlibs/nanoxplore/cells_bb.v     | 168 -----------------------------
 techlibs/nanoxplore/cells_bb_l.v   |  32 ++++++
 techlibs/nanoxplore/cells_bb_m.v   |  23 ++++
 techlibs/nanoxplore/cells_bb_u.v   |  64 +++++++++++
 techlibs/nanoxplore/cells_wrap_u.v | 112 ++++++++++++++++++-
 5 files changed, 230 insertions(+), 169 deletions(-)

diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index f01d7571fe4..7b49616ce7c 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -5846,174 +5846,6 @@ endmodule
 //    parameter lut_table = 16'b0000000000000000;
 //endmodule
 
-(* blackbox *)
-module NX_PLL(REF, FBK, VCO, D1, D2, D3, OSC, RDY);
-    output D1;
-    output D2;
-    output D3;
-    input FBK;
-    output OSC;
-    output RDY;
-    input REF;
-    output VCO;
-    parameter clk_outdiv1 = 0;
-    parameter clk_outdiv2 = 0;
-    parameter clk_outdiv3 = 0;
-    parameter ext_fbk_on = 1'b0;
-    parameter fbk_delay = 0;
-    parameter fbk_delay_on = 1'b0;
-    parameter fbk_div_on = 1'b0;
-    parameter fbk_intdiv = 2;
-    parameter location = "";
-    parameter ref_div_on = 1'b0;
-    parameter vco_range = 0;
-endmodule
-
-(* blackbox *)
-module NX_PLL_L(REF, FBK, R, VCO, LDFO, REFO, DIVO1, DIVO2, DIVP1, DIVP2, DIVP3, OSC, PLL_LOCKED, CAL_LOCKED);
-    output CAL_LOCKED;
-    output DIVO1;
-    output DIVO2;
-    output DIVP1;
-    output DIVP2;
-    output DIVP3;
-    input FBK;
-    output LDFO;
-    output OSC;
-    output PLL_LOCKED;
-    input R;
-    input REF;
-    output REFO;
-    output VCO;
-    parameter cfg_use_pll = 1'b1;
-    parameter clk_outdivo1 = 0;
-    parameter clk_outdivp1 = 0;
-    parameter clk_outdivp2 = 0;
-    parameter clk_outdivp3o2 = 0;
-    parameter ext_fbk_on = 1'b0;
-    parameter fbk_delay = 0;
-    parameter fbk_delay_on = 1'b0;
-    parameter fbk_intdiv = 2;
-    parameter location = "";
-    parameter pll_cpump = 3'b010;
-    parameter ref_intdiv = 0;
-    parameter ref_osc_on = 1'b0;
-    parameter wfg_sync_cal_lock = 1'b0;
-    parameter wfg_sync_pll_lock = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_PLL_U(R, REF, FBK, OSC, VCO, LDFO, REFO, CLK_DIV1, CLK_DIV2, CLK_DIV3, CLK_DIV4, CLK_DIVD1, CLK_DIVD2, CLK_DIVD3, CLK_DIVD4, CLK_DIVD5, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV
-, CAL_LOCKED, EXT_CAL_LOCKED, CAL1, CAL2, CAL3, CAL4, CAL5, EXT_CAL1, EXT_CAL2, EXT_CAL3, EXT_CAL4, EXT_CAL5);
-    input ARST_CAL;
-    output CAL1;
-    output CAL2;
-    output CAL3;
-    output CAL4;
-    output CAL5;
-    output CAL_LOCKED;
-    input CLK_CAL;
-    output CLK_CAL_DIV;
-    output CLK_DIV1;
-    output CLK_DIV2;
-    output CLK_DIV3;
-    output CLK_DIV4;
-    output CLK_DIVD1;
-    output CLK_DIVD2;
-    output CLK_DIVD3;
-    output CLK_DIVD4;
-    output CLK_DIVD5;
-    input EXT_CAL1;
-    input EXT_CAL2;
-    input EXT_CAL3;
-    input EXT_CAL4;
-    input EXT_CAL5;
-    input EXT_CAL_LOCKED;
-    input FBK;
-    output LDFO;
-    output OSC;
-    output PLL_LOCKED;
-    output PLL_LOCKEDA;
-    input R;
-    input REF;
-    output REFO;
-    output VCO;
-    parameter cal_delay = 6'b011011;
-    parameter cal_div = 4'b0111;
-    parameter clk_cal_sel = 2'b01;
-    parameter clk_outdiv1 = 3'b000;
-    parameter clk_outdiv2 = 3'b000;
-    parameter clk_outdiv3 = 3'b000;
-    parameter clk_outdiv4 = 3'b000;
-    parameter clk_outdivd1 = 4'b0000;
-    parameter clk_outdivd2 = 4'b0000;
-    parameter clk_outdivd3 = 4'b0000;
-    parameter clk_outdivd4 = 4'b0000;
-    parameter clk_outdivd5 = 4'b0000;
-    parameter ext_fbk_on = 1'b0;
-    parameter fbk_delay = 6'b000000;
-    parameter fbk_delay_on = 1'b0;
-    parameter fbk_intdiv = 7'b0000000;
-    parameter location = "";
-    parameter pll_cpump = 4'b0000;
-    parameter pll_lock = 4'b0000;
-    parameter pll_lpf_cap = 4'b0000;
-    parameter pll_lpf_res = 4'b0000;
-    parameter pll_odf = 2'b00;
-    parameter ref_intdiv = 5'b00000;
-    parameter ref_osc_on = 1'b0;
-    parameter use_cal = 1'b0;
-    parameter use_pll = 1'b1;
-endmodule
-
-(* blackbox *)
-module NX_PLL_U_WRAP(R, REF, FBK, OSC, VCO, LDFO, REFO, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV, CAL_LOCKED, EXT_CAL_LOCKED, CAL, CLK_DIVD, EXT_CAL, CLK_DIV);
-    input ARST_CAL;
-    output [4:0] CAL;
-    output CAL_LOCKED;
-    input CLK_CAL;
-    output CLK_CAL_DIV;
-    output [3:0] CLK_DIV;
-    output [4:0] CLK_DIVD;
-    input [4:0] EXT_CAL;
-    input EXT_CAL_LOCKED;
-    input FBK;
-    output LDFO;
-    output OSC;
-    output PLL_LOCKED;
-    output PLL_LOCKEDA;
-    input R;
-    input REF;
-    output REFO;
-    output VCO;
-    parameter cal_delay = 6'b011011;
-    parameter cal_div = 4'b0111;
-    parameter clk_cal_sel = 2'b01;
-    parameter clk_outdiv1 = 3'b000;
-    parameter clk_outdiv2 = 3'b000;
-    parameter clk_outdiv3 = 3'b000;
-    parameter clk_outdiv4 = 3'b000;
-    parameter clk_outdivd1 = 4'b0000;
-    parameter clk_outdivd2 = 4'b0000;
-    parameter clk_outdivd3 = 4'b0000;
-    parameter clk_outdivd4 = 4'b0000;
-    parameter clk_outdivd5 = 4'b0000;
-    parameter ext_fbk_on = 1'b0;
-    parameter fbk_delay = 6'b000000;
-    parameter fbk_delay_on = 1'b0;
-    parameter fbk_intdiv = 7'b0000000;
-    parameter location = "";
-    parameter pll_cpump = 4'b0000;
-    parameter pll_lock = 4'b0000;
-    parameter pll_lpf_cap = 4'b0000;
-    parameter pll_lpf_res = 4'b0000;
-    parameter pll_odf = 2'b00;
-    parameter ref_intdiv = 5'b00000;
-    parameter ref_osc_on = 1'b0;
-    parameter use_cal = 1'b0;
-    parameter use_pll = 1'b1;
-endmodule
-
 (* blackbox *)
 module NX_PMA_L(CLK_USER_I, CLK_REF_I, PRE_SG_I, PRE_EN_I, PRE_IS_I1, PRE_IS_I2, PRE_IS_I3, PRE_IS_I4, MAIN_SG_I, MAIN_EN_I1, MAIN_EN_I2, MAIN_EN_I3, MAIN_EN_I4, MAIN_EN_I5, MAIN_EN_I6, MARG_S_I1, MARG_S_I2, MARG_S_I3, MARG_S_I4, MARG_IS_I1, MARG_IS_I2
 , MARG_IS_I3, MARG_IS_I4, MARG_SV_I1, MARG_SV_I2, MARG_SV_I3, MARG_SV_I4, MARG_SV_I5, MARG_ISV_I1, MARG_ISV_I2, MARG_ISV_I3, MARG_ISV_I4, MARG_ISV_I5, POST_EN_I1, POST_EN_I2, POST_EN_I3, POST_EN_I4, POST_EN_I5, POST_SG_I, POST_IS_I1, POST_IS_I2, POST_IS_I3
diff --git a/techlibs/nanoxplore/cells_bb_l.v b/techlibs/nanoxplore/cells_bb_l.v
index a3a11a06c14..991600e6559 100644
--- a/techlibs/nanoxplore/cells_bb_l.v
+++ b/techlibs/nanoxplore/cells_bb_l.v
@@ -469,3 +469,35 @@ module NX_DSP_L(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15
     parameter std_mode = "";
 endmodule
 
+(* blackbox *)
+module NX_PLL_L(REF, FBK, R, VCO, LDFO, REFO, DIVO1, DIVO2, DIVP1, DIVP2, DIVP3, OSC, PLL_LOCKED, CAL_LOCKED);
+    output CAL_LOCKED;
+    output DIVO1;
+    output DIVO2;
+    output DIVP1;
+    output DIVP2;
+    output DIVP3;
+    input FBK;
+    output LDFO;
+    output OSC;
+    output PLL_LOCKED;
+    input R;
+    input REF;
+    output REFO;
+    output VCO;
+    parameter cfg_use_pll = 1'b1;
+    parameter clk_outdivo1 = 0;
+    parameter clk_outdivp1 = 0;
+    parameter clk_outdivp2 = 0;
+    parameter clk_outdivp3o2 = 0;
+    parameter ext_fbk_on = 1'b0;
+    parameter fbk_delay = 0;
+    parameter fbk_delay_on = 1'b0;
+    parameter fbk_intdiv = 2;
+    parameter location = "";
+    parameter pll_cpump = 3'b010;
+    parameter ref_intdiv = 0;
+    parameter ref_osc_on = 1'b0;
+    parameter wfg_sync_cal_lock = 1'b0;
+    parameter wfg_sync_pll_lock = 1'b0;
+endmodule
diff --git a/techlibs/nanoxplore/cells_bb_m.v b/techlibs/nanoxplore/cells_bb_m.v
index e54c1fd8ac4..0be57e720b1 100644
--- a/techlibs/nanoxplore/cells_bb_m.v
+++ b/techlibs/nanoxplore/cells_bb_m.v
@@ -378,3 +378,26 @@ module NX_DSP(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15,
     parameter std_mode = "";
 endmodule
 
+(* blackbox *)
+module NX_PLL(REF, FBK, VCO, D1, D2, D3, OSC, RDY);
+    output D1;
+    output D2;
+    output D3;
+    input FBK;
+    output OSC;
+    output RDY;
+    input REF;
+    output VCO;
+    parameter clk_outdiv1 = 0;
+    parameter clk_outdiv2 = 0;
+    parameter clk_outdiv3 = 0;
+    parameter ext_fbk_on = 1'b0;
+    parameter fbk_delay = 0;
+    parameter fbk_delay_on = 1'b0;
+    parameter fbk_div_on = 1'b0;
+    parameter fbk_intdiv = 2;
+    parameter location = "";
+    parameter ref_div_on = 1'b0;
+    parameter vco_range = 0;
+endmodule
+
diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v
index 657cd6667e4..988ddb4c516 100644
--- a/techlibs/nanoxplore/cells_bb_u.v
+++ b/techlibs/nanoxplore/cells_bb_u.v
@@ -485,3 +485,67 @@ module NX_DSP_U(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15
     parameter raw_config3 = 3'b000;
     parameter std_mode = "";
 endmodule
+
+(* blackbox *)
+module NX_PLL_U(R, REF, FBK, OSC, VCO, LDFO, REFO, CLK_DIV1, CLK_DIV2, CLK_DIV3, CLK_DIV4, CLK_DIVD1, CLK_DIVD2, CLK_DIVD3, CLK_DIVD4, CLK_DIVD5, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV
+, CAL_LOCKED, EXT_CAL_LOCKED, CAL1, CAL2, CAL3, CAL4, CAL5, EXT_CAL1, EXT_CAL2, EXT_CAL3, EXT_CAL4, EXT_CAL5);
+    input ARST_CAL;
+    output CAL1;
+    output CAL2;
+    output CAL3;
+    output CAL4;
+    output CAL5;
+    output CAL_LOCKED;
+    input CLK_CAL;
+    output CLK_CAL_DIV;
+    output CLK_DIV1;
+    output CLK_DIV2;
+    output CLK_DIV3;
+    output CLK_DIV4;
+    output CLK_DIVD1;
+    output CLK_DIVD2;
+    output CLK_DIVD3;
+    output CLK_DIVD4;
+    output CLK_DIVD5;
+    input EXT_CAL1;
+    input EXT_CAL2;
+    input EXT_CAL3;
+    input EXT_CAL4;
+    input EXT_CAL5;
+    input EXT_CAL_LOCKED;
+    input FBK;
+    output LDFO;
+    output OSC;
+    output PLL_LOCKED;
+    output PLL_LOCKEDA;
+    input R;
+    input REF;
+    output REFO;
+    output VCO;
+    parameter cal_delay = 6'b011011;
+    parameter cal_div = 4'b0111;
+    parameter clk_cal_sel = 2'b01;
+    parameter clk_outdiv1 = 3'b000;
+    parameter clk_outdiv2 = 3'b000;
+    parameter clk_outdiv3 = 3'b000;
+    parameter clk_outdiv4 = 3'b000;
+    parameter clk_outdivd1 = 4'b0000;
+    parameter clk_outdivd2 = 4'b0000;
+    parameter clk_outdivd3 = 4'b0000;
+    parameter clk_outdivd4 = 4'b0000;
+    parameter clk_outdivd5 = 4'b0000;
+    parameter ext_fbk_on = 1'b0;
+    parameter fbk_delay = 6'b000000;
+    parameter fbk_delay_on = 1'b0;
+    parameter fbk_intdiv = 7'b0000000;
+    parameter location = "";
+    parameter pll_cpump = 4'b0000;
+    parameter pll_lock = 4'b0000;
+    parameter pll_lpf_cap = 4'b0000;
+    parameter pll_lpf_res = 4'b0000;
+    parameter pll_odf = 2'b00;
+    parameter ref_intdiv = 5'b00000;
+    parameter ref_osc_on = 1'b0;
+    parameter use_cal = 1'b0;
+    parameter use_pll = 1'b1;
+endmodule
diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v
index 7f7fda78983..be5561c3e09 100644
--- a/techlibs/nanoxplore/cells_wrap_u.v
+++ b/techlibs/nanoxplore/cells_wrap_u.v
@@ -1348,4 +1348,114 @@ module NX_DSP_U_WRAP(CCI, CCO, CI, CK, CO43, CO57, OVF, R, RZ, WE, WEZ, A, B, C,
     .Z55(Z[54]),
     .Z56(Z[55])
   );
-endmodule
\ No newline at end of file
+endmodule
+
+module NX_PLL_U_WRAP(R, REF, FBK, OSC, VCO, LDFO, REFO, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV, CAL_LOCKED, EXT_CAL_LOCKED, CAL, CLK_DIVD, EXT_CAL, CLK_DIV);
+    input ARST_CAL;
+    output [4:0] CAL;
+    output CAL_LOCKED;
+    input CLK_CAL;
+    output CLK_CAL_DIV;
+    output [3:0] CLK_DIV;
+    output [4:0] CLK_DIVD;
+    input [4:0] EXT_CAL;
+    input EXT_CAL_LOCKED;
+    input FBK;
+    output LDFO;
+    output OSC;
+    output PLL_LOCKED;
+    output PLL_LOCKEDA;
+    input R;
+    input REF;
+    output REFO;
+    output VCO;
+    parameter cal_delay = 6'b011011;
+    parameter cal_div = 4'b0111;
+    parameter clk_cal_sel = 2'b01;
+    parameter clk_outdiv1 = 3'b000;
+    parameter clk_outdiv2 = 3'b000;
+    parameter clk_outdiv3 = 3'b000;
+    parameter clk_outdiv4 = 3'b000;
+    parameter clk_outdivd1 = 4'b0000;
+    parameter clk_outdivd2 = 4'b0000;
+    parameter clk_outdivd3 = 4'b0000;
+    parameter clk_outdivd4 = 4'b0000;
+    parameter clk_outdivd5 = 4'b0000;
+    parameter ext_fbk_on = 1'b0;
+    parameter fbk_delay = 6'b000000;
+    parameter fbk_delay_on = 1'b0;
+    parameter fbk_intdiv = 7'b0000000;
+    parameter location = "";
+    parameter pll_cpump = 4'b0000;
+    parameter pll_lock = 4'b0000;
+    parameter pll_lpf_cap = 4'b0000;
+    parameter pll_lpf_res = 4'b0000;
+    parameter pll_odf = 2'b00;
+    parameter ref_intdiv = 5'b00000;
+    parameter ref_osc_on = 1'b0;
+    parameter use_cal = 1'b0;
+    parameter use_pll = 1'b1;
+
+  NX_PLL_U #(
+    .cal_delay(cal_delay),
+    .cal_div(cal_div),
+    .clk_cal_sel(clk_cal_sel),
+    .clk_outdiv1(clk_outdiv1),
+    .clk_outdiv2(clk_outdiv2),
+    .clk_outdiv3(clk_outdiv3),
+    .clk_outdiv4(clk_outdiv4),
+    .clk_outdivd1(clk_outdivd1),
+    .clk_outdivd2(clk_outdivd2),
+    .clk_outdivd3(clk_outdivd3),
+    .clk_outdivd4(clk_outdivd4),
+    .clk_outdivd5(clk_outdivd5),
+    .ext_fbk_on(ext_fbk_on),
+    .fbk_delay(fbk_delay),
+    .fbk_delay_on(fbk_delay_on),
+    .fbk_intdiv(fbk_intdiv),
+    .location(location),
+    .pll_cpump(pll_cpump),
+    .pll_lock(pll_lock),
+    .pll_lpf_cap(pll_lpf_cap),
+    .pll_lpf_res(pll_lpf_res),
+    .pll_odf(pll_odf),
+    .ref_intdiv(ref_intdiv),
+    .ref_osc_on(ref_osc_on),
+    .use_cal(use_cal),
+    .use_pll(use_pll)
+  ) _TECHMAP_REPLACE_ (
+    .ARST_CAL(ARST_CAL),
+    .CAL1(CAL[0]),
+    .CAL2(CAL[1]),
+    .CAL3(CAL[2]),
+    .CAL4(CAL[3]),
+    .CAL5(CAL[4]),
+    .CAL_LOCKED(CAL_LOCKED),
+    .CLK_CAL(CLK_CAL),
+    .CLK_CAL_DIV(CLK_CAL_DIV),
+    .CLK_DIV1(CLK_DIV[0]),
+    .CLK_DIV2(CLK_DIV[1]),
+    .CLK_DIV3(CLK_DIV[2]),
+    .CLK_DIV4(CLK_DIV[3]),
+    .CLK_DIVD1(CLK_DIVD[0]),
+    .CLK_DIVD2(CLK_DIVD[1]),
+    .CLK_DIVD3(CLK_DIVD[2]),
+    .CLK_DIVD4(CLK_DIVD[3]),
+    .CLK_DIVD5(CLK_DIVD[4]),
+    .EXT_CAL1(EXT_CAL[0]),
+    .EXT_CAL2(EXT_CAL[1]),
+    .EXT_CAL3(EXT_CAL[2]),
+    .EXT_CAL4(EXT_CAL[3]),
+    .EXT_CAL5(EXT_CAL[4]),
+    .EXT_CAL_LOCKED(EXT_CAL_LOCKED),
+    .FBK(FBK),
+    .LDFO(LDFO),
+    .OSC(OSC),
+    .PLL_LOCKED(PLL_LOCKED),
+    .PLL_LOCKEDA(PLL_LOCKEDA),
+    .R(R),
+    .REF(REF),
+    .REFO(REFO),
+    .VCO(VCO)
+  );
+endmodule

From 3ed5ea24b2144ec076350e2ae84abb1846d92e12 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 12 Mar 2024 16:45:46 +0100
Subject: [PATCH 281/499] sortout more blackboxes

---
 techlibs/nanoxplore/cells_bb.v   | 4065 ------------------------------
 techlibs/nanoxplore/cells_bb_l.v | 1441 +++++++++++
 techlibs/nanoxplore/cells_bb_m.v |  828 ++++++
 techlibs/nanoxplore/cells_bb_u.v | 1800 +++++++++++++
 4 files changed, 4069 insertions(+), 4065 deletions(-)

diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index 7b49616ce7c..6b46317afea 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -70,702 +70,6 @@ module NX_BFR(I, O);
     parameter ring = 0;
 endmodule
 
-(* blackbox *)
-module NX_CRX_L(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, BUF_FE_I, RST_N_I, CDR_R_I, CKG_RN_I, PLL_RN_I, TST_I1, TST_I2, TST_I3, TST_I4, LOS_O, DATA_O1, DATA_O2, DATA_O3
-, DATA_O4, DATA_O5, DATA_O6, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24
-, DATA_O25, DATA_O26, DATA_O27, DATA_O28, DATA_O29, DATA_O30, DATA_O31, DATA_O32, DATA_O33, DATA_O34, DATA_O35, DATA_O36, DATA_O37, DATA_O38, DATA_O39, DATA_O40, DATA_O41, DATA_O42, DATA_O43, DATA_O44, DATA_O45
-, DATA_O46, DATA_O47, DATA_O48, DATA_O49, DATA_O50, DATA_O51, DATA_O52, DATA_O53, DATA_O54, DATA_O55, DATA_O56, DATA_O57, DATA_O58, DATA_O59, DATA_O60, DATA_O61, DATA_O62, DATA_O63, DATA_O64, CH_COM_O1, CH_COM_O2
-, CH_COM_O3, CH_COM_O4, CH_COM_O5, CH_COM_O6, CH_COM_O7, CH_COM_O8, CH_K_O1, CH_K_O2, CH_K_O3, CH_K_O4, CH_K_O5, CH_K_O6, CH_K_O7, CH_K_O8, NIT_O1, NIT_O2, NIT_O3, NIT_O4, NIT_O5, NIT_O6, NIT_O7
-, NIT_O8, D_ERR_O1, D_ERR_O2, D_ERR_O3, D_ERR_O4, D_ERR_O5, D_ERR_O6, D_ERR_O7, D_ERR_O8, CH_A_O1, CH_A_O2, CH_A_O3, CH_A_O4, CH_A_O5, CH_A_O6, CH_A_O7, CH_A_O8, CH_F_O1, CH_F_O2, CH_F_O3, CH_F_O4
-, CH_F_O5, CH_F_O6, CH_F_O7, CH_F_O8, ALIGN_O, BUSY_O, TST_O1, TST_O2, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, LOCK_O, RX_I, LINK);
-    input ALIGN_E_I;
-    output ALIGN_O;
-    input ALIGN_S_I;
-    input BUF_FE_I;
-    input BUF_R_I;
-    output BUSY_O;
-    input CDR_R_I;
-    output CH_A_O1;
-    output CH_A_O2;
-    output CH_A_O3;
-    output CH_A_O4;
-    output CH_A_O5;
-    output CH_A_O6;
-    output CH_A_O7;
-    output CH_A_O8;
-    output CH_COM_O1;
-    output CH_COM_O2;
-    output CH_COM_O3;
-    output CH_COM_O4;
-    output CH_COM_O5;
-    output CH_COM_O6;
-    output CH_COM_O7;
-    output CH_COM_O8;
-    output CH_F_O1;
-    output CH_F_O2;
-    output CH_F_O3;
-    output CH_F_O4;
-    output CH_F_O5;
-    output CH_F_O6;
-    output CH_F_O7;
-    output CH_F_O8;
-    output CH_K_O1;
-    output CH_K_O2;
-    output CH_K_O3;
-    output CH_K_O4;
-    output CH_K_O5;
-    output CH_K_O6;
-    output CH_K_O7;
-    output CH_K_O8;
-    input CKG_RN_I;
-    output DATA_O1;
-    output DATA_O10;
-    output DATA_O11;
-    output DATA_O12;
-    output DATA_O13;
-    output DATA_O14;
-    output DATA_O15;
-    output DATA_O16;
-    output DATA_O17;
-    output DATA_O18;
-    output DATA_O19;
-    output DATA_O2;
-    output DATA_O20;
-    output DATA_O21;
-    output DATA_O22;
-    output DATA_O23;
-    output DATA_O24;
-    output DATA_O25;
-    output DATA_O26;
-    output DATA_O27;
-    output DATA_O28;
-    output DATA_O29;
-    output DATA_O3;
-    output DATA_O30;
-    output DATA_O31;
-    output DATA_O32;
-    output DATA_O33;
-    output DATA_O34;
-    output DATA_O35;
-    output DATA_O36;
-    output DATA_O37;
-    output DATA_O38;
-    output DATA_O39;
-    output DATA_O4;
-    output DATA_O40;
-    output DATA_O41;
-    output DATA_O42;
-    output DATA_O43;
-    output DATA_O44;
-    output DATA_O45;
-    output DATA_O46;
-    output DATA_O47;
-    output DATA_O48;
-    output DATA_O49;
-    output DATA_O5;
-    output DATA_O50;
-    output DATA_O51;
-    output DATA_O52;
-    output DATA_O53;
-    output DATA_O54;
-    output DATA_O55;
-    output DATA_O56;
-    output DATA_O57;
-    output DATA_O58;
-    output DATA_O59;
-    output DATA_O6;
-    output DATA_O60;
-    output DATA_O61;
-    output DATA_O62;
-    output DATA_O63;
-    output DATA_O64;
-    output DATA_O7;
-    output DATA_O8;
-    output DATA_O9;
-    input DEC_E_I;
-    input DSCR_E_I;
-    output D_ERR_O1;
-    output D_ERR_O2;
-    output D_ERR_O3;
-    output D_ERR_O4;
-    output D_ERR_O5;
-    output D_ERR_O6;
-    output D_ERR_O7;
-    output D_ERR_O8;
-    inout [9:0] LINK;
-    output LOCK_O;
-    output LOS_O;
-    output NIT_O1;
-    output NIT_O2;
-    output NIT_O3;
-    output NIT_O4;
-    output NIT_O5;
-    output NIT_O6;
-    output NIT_O7;
-    output NIT_O8;
-    input OVS_BS_I1;
-    input OVS_BS_I2;
-    input PLL_RN_I;
-    input REP_E_I;
-    input RST_N_I;
-    input RX_I;
-    input TST_I1;
-    input TST_I2;
-    input TST_I3;
-    input TST_I4;
-    output TST_O1;
-    output TST_O2;
-    output TST_O3;
-    output TST_O4;
-    output TST_O5;
-    output TST_O6;
-    output TST_O7;
-    output TST_O8;
-    parameter location = "";
-    parameter pcs_8b_dscr_sel = 1'b0;
-    parameter pcs_align_bypass = 1'b0;
-    parameter pcs_buffers_bypass = 1'b0;
-    parameter pcs_buffers_use_cdc = 1'b0;
-    parameter pcs_bypass_pma_cdc = 1'b0;
-    parameter pcs_bypass_usr_cdc = 1'b0;
-    parameter pcs_comma_mask = 10'b0000000000;
-    parameter pcs_debug_en = 1'b0;
-    parameter pcs_dec_bypass = 1'b0;
-    parameter pcs_dscr_bypass = 1'b0;
-    parameter pcs_el_buff_diff_bef_comp = 3'b000;
-    parameter pcs_el_buff_max_comp = 3'b000;
-    parameter pcs_el_buff_only_one_skp = 1'b0;
-    parameter pcs_el_buff_skp_char_0 = 9'b000000000;
-    parameter pcs_el_buff_skp_char_1 = 9'b000000000;
-    parameter pcs_el_buff_skp_char_2 = 9'b000000000;
-    parameter pcs_el_buff_skp_char_3 = 9'b000000000;
-    parameter pcs_el_buff_skp_header_0 = 9'b000000000;
-    parameter pcs_el_buff_skp_header_1 = 9'b000000000;
-    parameter pcs_el_buff_skp_header_2 = 9'b000000000;
-    parameter pcs_el_buff_skp_header_3 = 9'b000000000;
-    parameter pcs_el_buff_skp_header_size = 2'b00;
-    parameter pcs_el_buff_skp_seq_size = 2'b00;
-    parameter pcs_el_buff_underflow_handle = 1'b0;
-    parameter pcs_fsm_sel = 2'b00;
-    parameter pcs_fsm_watchdog_en = 1'b0;
-    parameter pcs_loopback = 1'b0;
-    parameter pcs_m_comma_en = 1'b0;
-    parameter pcs_m_comma_val = 10'b0000000000;
-    parameter pcs_nb_comma_bef_realign = 2'b00;
-    parameter pcs_p_comma_en = 1'b0;
-    parameter pcs_p_comma_val = 10'b0000000000;
-    parameter pcs_polarity = 1'b0;
-    parameter pcs_protocol_size = 1'b0;
-    parameter pcs_replace_bypass = 1'b0;
-    parameter pcs_sync_supported = 1'b0;
-    parameter pma_cdr_cp = 4'b0000;
-    parameter pma_clk_pos = 1'b0;
-    parameter pma_ctrl_term = 6'b000000;
-    parameter pma_loopback = 1'b0;
-    parameter pma_pll_cpump_n = 3'b000;
-    parameter pma_pll_divf = 2'b00;
-    parameter pma_pll_divf_en_n = 1'b0;
-    parameter pma_pll_divm = 2'b00;
-    parameter pma_pll_divm_en_n = 1'b0;
-    parameter pma_pll_divn = 1'b0;
-    parameter pma_pll_divn_en_n = 1'b0;
-    parameter test = 2'b00;
-endmodule
-
-(* blackbox *)
-module NX_CRX_U(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, RST_N_I, PMA_RSTN_I, MEYE_RST_I, PWDN_N_I, DBG_S_I1, DBG_S_I2, DBG_S_I3, DATA_O1, DATA_O2, DATA_O3, DATA_O4, DATA_O5, DATA_O6
-, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24, DATA_O25, DATA_O26, DATA_O27
-, DATA_O28, DATA_O29, DATA_O30, DATA_O31, DATA_O32, DATA_O33, DATA_O34, DATA_O35, DATA_O36, DATA_O37, DATA_O38, DATA_O39, DATA_O40, DATA_O41, DATA_O42, DATA_O43, DATA_O44, DATA_O45, DATA_O46, DATA_O47, DATA_O48
-, DATA_O49, DATA_O50, DATA_O51, DATA_O52, DATA_O53, DATA_O54, DATA_O55, DATA_O56, DATA_O57, DATA_O58, DATA_O59, DATA_O60, DATA_O61, DATA_O62, DATA_O63, DATA_O64, CH_COM_O1, CH_COM_O2, CH_COM_O3, CH_COM_O4, CH_COM_O5
-, CH_COM_O6, CH_COM_O7, CH_COM_O8, CH_K_O1, CH_K_O2, CH_K_O3, CH_K_O4, CH_K_O5, CH_K_O6, CH_K_O7, CH_K_O8, NIT_O1, NIT_O2, NIT_O3, NIT_O4, NIT_O5, NIT_O6, NIT_O7, NIT_O8, D_ERR_O1, D_ERR_O2
-, D_ERR_O3, D_ERR_O4, D_ERR_O5, D_ERR_O6, D_ERR_O7, D_ERR_O8, CH_A_O1, CH_A_O2, CH_A_O3, CH_A_O4, CH_A_O5, CH_A_O6, CH_A_O7, CH_A_O8, CH_F_O1, CH_F_O2, CH_F_O3, CH_F_O4, CH_F_O5, CH_F_O6, CH_F_O7
-, CH_F_O8, ALIGN_O, VREALIGN_O, BUSY_O, TST_O1, TST_O2, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, LOS_O, LL_FLOCK_O, LL_SLOCK_O, PLL_LOCK_O, PLL_LOCKT_O, LINK);
-    input ALIGN_E_I;
-    output ALIGN_O;
-    input ALIGN_S_I;
-    input BUF_R_I;
-    output BUSY_O;
-    output CH_A_O1;
-    output CH_A_O2;
-    output CH_A_O3;
-    output CH_A_O4;
-    output CH_A_O5;
-    output CH_A_O6;
-    output CH_A_O7;
-    output CH_A_O8;
-    output CH_COM_O1;
-    output CH_COM_O2;
-    output CH_COM_O3;
-    output CH_COM_O4;
-    output CH_COM_O5;
-    output CH_COM_O6;
-    output CH_COM_O7;
-    output CH_COM_O8;
-    output CH_F_O1;
-    output CH_F_O2;
-    output CH_F_O3;
-    output CH_F_O4;
-    output CH_F_O5;
-    output CH_F_O6;
-    output CH_F_O7;
-    output CH_F_O8;
-    output CH_K_O1;
-    output CH_K_O2;
-    output CH_K_O3;
-    output CH_K_O4;
-    output CH_K_O5;
-    output CH_K_O6;
-    output CH_K_O7;
-    output CH_K_O8;
-    output DATA_O1;
-    output DATA_O10;
-    output DATA_O11;
-    output DATA_O12;
-    output DATA_O13;
-    output DATA_O14;
-    output DATA_O15;
-    output DATA_O16;
-    output DATA_O17;
-    output DATA_O18;
-    output DATA_O19;
-    output DATA_O2;
-    output DATA_O20;
-    output DATA_O21;
-    output DATA_O22;
-    output DATA_O23;
-    output DATA_O24;
-    output DATA_O25;
-    output DATA_O26;
-    output DATA_O27;
-    output DATA_O28;
-    output DATA_O29;
-    output DATA_O3;
-    output DATA_O30;
-    output DATA_O31;
-    output DATA_O32;
-    output DATA_O33;
-    output DATA_O34;
-    output DATA_O35;
-    output DATA_O36;
-    output DATA_O37;
-    output DATA_O38;
-    output DATA_O39;
-    output DATA_O4;
-    output DATA_O40;
-    output DATA_O41;
-    output DATA_O42;
-    output DATA_O43;
-    output DATA_O44;
-    output DATA_O45;
-    output DATA_O46;
-    output DATA_O47;
-    output DATA_O48;
-    output DATA_O49;
-    output DATA_O5;
-    output DATA_O50;
-    output DATA_O51;
-    output DATA_O52;
-    output DATA_O53;
-    output DATA_O54;
-    output DATA_O55;
-    output DATA_O56;
-    output DATA_O57;
-    output DATA_O58;
-    output DATA_O59;
-    output DATA_O6;
-    output DATA_O60;
-    output DATA_O61;
-    output DATA_O62;
-    output DATA_O63;
-    output DATA_O64;
-    output DATA_O7;
-    output DATA_O8;
-    output DATA_O9;
-    input DBG_S_I1;
-    input DBG_S_I2;
-    input DBG_S_I3;
-    input DEC_E_I;
-    input DSCR_E_I;
-    output D_ERR_O1;
-    output D_ERR_O2;
-    output D_ERR_O3;
-    output D_ERR_O4;
-    output D_ERR_O5;
-    output D_ERR_O6;
-    output D_ERR_O7;
-    output D_ERR_O8;
-    inout [9:0] LINK;
-    output LL_FLOCK_O;
-    output LL_SLOCK_O;
-    output LOS_O;
-    input MEYE_RST_I;
-    output NIT_O1;
-    output NIT_O2;
-    output NIT_O3;
-    output NIT_O4;
-    output NIT_O5;
-    output NIT_O6;
-    output NIT_O7;
-    output NIT_O8;
-    input OVS_BS_I1;
-    input OVS_BS_I2;
-    output PLL_LOCKT_O;
-    output PLL_LOCK_O;
-    input PMA_RSTN_I;
-    input PWDN_N_I;
-    input REP_E_I;
-    input RST_N_I;
-    output TST_O1;
-    output TST_O2;
-    output TST_O3;
-    output TST_O4;
-    output TST_O5;
-    output TST_O6;
-    output TST_O7;
-    output TST_O8;
-    output VREALIGN_O;
-    parameter gearbox_en = 1'b0;
-    parameter gearbox_mode = 1'b0;
-    parameter location = "";
-    parameter pcs_8b_dscr_sel = 1'b0;
-    parameter pcs_align_bypass = 1'b0;
-    parameter pcs_buffers_bypass = 1'b0;
-    parameter pcs_buffers_use_cdc = 1'b0;
-    parameter pcs_bypass_pma_cdc = 1'b0;
-    parameter pcs_bypass_usr_cdc = 1'b0;
-    parameter pcs_comma_mask = 10'b0000000000;
-    parameter pcs_debug_en = 1'b0;
-    parameter pcs_dec_bypass = 1'b0;
-    parameter pcs_dscr_bypass = 1'b0;
-    parameter pcs_el_buff_diff_bef_comp = 4'b0000;
-    parameter pcs_el_buff_max_comp = 4'b0000;
-    parameter pcs_el_buff_only_one_skp = 1'b0;
-    parameter pcs_el_buff_skp_char_0 = 9'b000000000;
-    parameter pcs_el_buff_skp_char_1 = 9'b000000000;
-    parameter pcs_el_buff_skp_char_2 = 9'b000000000;
-    parameter pcs_el_buff_skp_char_3 = 9'b000000000;
-    parameter pcs_el_buff_skp_header_0 = 9'b000000000;
-    parameter pcs_el_buff_skp_header_1 = 9'b000000000;
-    parameter pcs_el_buff_skp_header_2 = 9'b000000000;
-    parameter pcs_el_buff_skp_header_3 = 9'b000000000;
-    parameter pcs_el_buff_skp_header_size = 2'b00;
-    parameter pcs_el_buff_skp_seq_size = 2'b00;
-    parameter pcs_fsm_sel = 2'b00;
-    parameter pcs_fsm_watchdog_en = 1'b0;
-    parameter pcs_loopback = 1'b0;
-    parameter pcs_m_comma_en = 1'b0;
-    parameter pcs_m_comma_val = 10'b0000000000;
-    parameter pcs_nb_comma_bef_realign = 2'b00;
-    parameter pcs_p_comma_en = 1'b0;
-    parameter pcs_p_comma_val = 10'b0000000000;
-    parameter pcs_polarity = 1'b0;
-    parameter pcs_protocol_size = 1'b0;
-    parameter pcs_replace_bypass = 1'b0;
-    parameter pcs_sync_supported = 1'b0;
-    parameter pma_cdr_cp = 4'b0000;
-    parameter pma_clk_pos = 1'b0;
-    parameter pma_coarse_ppm = 3'b000;
-    parameter pma_ctrl_term = 6'b000000;
-    parameter pma_dco_divl = 2'b00;
-    parameter pma_dco_divm = 1'b0;
-    parameter pma_dco_divn = 2'b00;
-    parameter pma_dco_reg_res = 2'b00;
-    parameter pma_dco_vref_sel = 1'b0;
-    parameter pma_fine_ppm = 3'b000;
-    parameter pma_loopback = 1'b0;
-    parameter pma_m_eye_ppm = 3'b000;
-    parameter pma_peak_detect_cmd = 2'b00;
-    parameter pma_peak_detect_on = 1'b0;
-    parameter pma_pll_cpump_n = 3'b000;
-    parameter pma_pll_divf = 2'b00;
-    parameter pma_pll_divf_en_n = 1'b0;
-    parameter pma_pll_divm = 2'b00;
-    parameter pma_pll_divm_en_n = 1'b0;
-    parameter pma_pll_divn = 1'b0;
-    parameter pma_pll_divn_en_n = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_CTX_L(ENC_E_I1, ENC_E_I2, ENC_E_I3, ENC_E_I4, ENC_E_I5, ENC_E_I6, ENC_E_I7, ENC_E_I8, CH_K_I1, CH_K_I2, CH_K_I3, CH_K_I4, CH_K_I5, CH_K_I6, CH_K_I7, CH_K_I8, SCR_E_I1, SCR_E_I2, SCR_E_I3, SCR_E_I4, SCR_E_I5
-, SCR_E_I6, SCR_E_I7, SCR_E_I8, EOMF_I1, EOMF_I2, EOMF_I3, EOMF_I4, EOMF_I5, EOMF_I6, EOMF_I7, EOMF_I8, EOF_I1, EOF_I2, EOF_I3, EOF_I4, EOF_I5, EOF_I6, EOF_I7, EOF_I8, REP_E_I, RST_N_I
-, TST_I1, TST_I2, TST_I3, TST_I4, DATA_I1, DATA_I2, DATA_I3, DATA_I4, DATA_I5, DATA_I6, DATA_I7, DATA_I8, DATA_I9, DATA_I10, DATA_I11, DATA_I12, DATA_I13, DATA_I14, DATA_I15, DATA_I16, DATA_I17
-, DATA_I18, DATA_I19, DATA_I20, DATA_I21, DATA_I22, DATA_I23, DATA_I24, DATA_I25, DATA_I26, DATA_I27, DATA_I28, DATA_I29, DATA_I30, DATA_I31, DATA_I32, DATA_I33, DATA_I34, DATA_I35, DATA_I36, DATA_I37, DATA_I38
-, DATA_I39, DATA_I40, DATA_I41, DATA_I42, DATA_I43, DATA_I44, DATA_I45, DATA_I46, DATA_I47, DATA_I48, DATA_I49, DATA_I50, DATA_I51, DATA_I52, DATA_I53, DATA_I54, DATA_I55, DATA_I56, DATA_I57, DATA_I58, DATA_I59
-, DATA_I60, DATA_I61, DATA_I62, DATA_I63, DATA_I64, TST_O1, TST_O2, TST_O3, TST_O4, BUSY_O, CLK_E_I, TX_O, LINK);
-    output BUSY_O;
-    input CH_K_I1;
-    input CH_K_I2;
-    input CH_K_I3;
-    input CH_K_I4;
-    input CH_K_I5;
-    input CH_K_I6;
-    input CH_K_I7;
-    input CH_K_I8;
-    input CLK_E_I;
-    input DATA_I1;
-    input DATA_I10;
-    input DATA_I11;
-    input DATA_I12;
-    input DATA_I13;
-    input DATA_I14;
-    input DATA_I15;
-    input DATA_I16;
-    input DATA_I17;
-    input DATA_I18;
-    input DATA_I19;
-    input DATA_I2;
-    input DATA_I20;
-    input DATA_I21;
-    input DATA_I22;
-    input DATA_I23;
-    input DATA_I24;
-    input DATA_I25;
-    input DATA_I26;
-    input DATA_I27;
-    input DATA_I28;
-    input DATA_I29;
-    input DATA_I3;
-    input DATA_I30;
-    input DATA_I31;
-    input DATA_I32;
-    input DATA_I33;
-    input DATA_I34;
-    input DATA_I35;
-    input DATA_I36;
-    input DATA_I37;
-    input DATA_I38;
-    input DATA_I39;
-    input DATA_I4;
-    input DATA_I40;
-    input DATA_I41;
-    input DATA_I42;
-    input DATA_I43;
-    input DATA_I44;
-    input DATA_I45;
-    input DATA_I46;
-    input DATA_I47;
-    input DATA_I48;
-    input DATA_I49;
-    input DATA_I5;
-    input DATA_I50;
-    input DATA_I51;
-    input DATA_I52;
-    input DATA_I53;
-    input DATA_I54;
-    input DATA_I55;
-    input DATA_I56;
-    input DATA_I57;
-    input DATA_I58;
-    input DATA_I59;
-    input DATA_I6;
-    input DATA_I60;
-    input DATA_I61;
-    input DATA_I62;
-    input DATA_I63;
-    input DATA_I64;
-    input DATA_I7;
-    input DATA_I8;
-    input DATA_I9;
-    input ENC_E_I1;
-    input ENC_E_I2;
-    input ENC_E_I3;
-    input ENC_E_I4;
-    input ENC_E_I5;
-    input ENC_E_I6;
-    input ENC_E_I7;
-    input ENC_E_I8;
-    input EOF_I1;
-    input EOF_I2;
-    input EOF_I3;
-    input EOF_I4;
-    input EOF_I5;
-    input EOF_I6;
-    input EOF_I7;
-    input EOF_I8;
-    input EOMF_I1;
-    input EOMF_I2;
-    input EOMF_I3;
-    input EOMF_I4;
-    input EOMF_I5;
-    input EOMF_I6;
-    input EOMF_I7;
-    input EOMF_I8;
-    inout [19:0] LINK;
-    input REP_E_I;
-    input RST_N_I;
-    input SCR_E_I1;
-    input SCR_E_I2;
-    input SCR_E_I3;
-    input SCR_E_I4;
-    input SCR_E_I5;
-    input SCR_E_I6;
-    input SCR_E_I7;
-    input SCR_E_I8;
-    input TST_I1;
-    input TST_I2;
-    input TST_I3;
-    input TST_I4;
-    output TST_O1;
-    output TST_O2;
-    output TST_O3;
-    output TST_O4;
-    output TX_O;
-    parameter location = "";
-    parameter pcs_8b_scr_sel = 1'b0;
-    parameter pcs_bypass_pma_cdc = 1'b0;
-    parameter pcs_bypass_usr_cdc = 1'b0;
-    parameter pcs_enc_bypass = 1'b0;
-    parameter pcs_esistream_fsm_en = 1'b0;
-    parameter pcs_loopback = 1'b0;
-    parameter pcs_polarity = 1'b0;
-    parameter pcs_protocol_size = 1'b0;
-    parameter pcs_replace_bypass = 1'b0;
-    parameter pcs_scr_bypass = 1'b0;
-    parameter pcs_scr_init = 17'b00000000000000000;
-    parameter pcs_sync_supported = 1'b0;
-    parameter pma_clk_pos = 1'b0;
-    parameter pma_loopback = 1'b0;
-    parameter test = 2'b00;
-endmodule
-
-(* blackbox *)
-module NX_CTX_U(ENC_E_I1, ENC_E_I2, ENC_E_I3, ENC_E_I4, ENC_E_I5, ENC_E_I6, ENC_E_I7, ENC_E_I8, CH_K_I1, CH_K_I2, CH_K_I3, CH_K_I4, CH_K_I5, CH_K_I6, CH_K_I7, CH_K_I8, SCR_E_I1, SCR_E_I2, SCR_E_I3, SCR_E_I4, SCR_E_I5
-, SCR_E_I6, SCR_E_I7, SCR_E_I8, EOMF_I1, EOMF_I2, EOMF_I3, EOMF_I4, EOMF_I5, EOMF_I6, EOMF_I7, EOMF_I8, EOF_I1, EOF_I2, EOF_I3, EOF_I4, EOF_I5, EOF_I6, EOF_I7, EOF_I8, REP_E_I, RST_N_I
-, DATA_I1, DATA_I2, DATA_I3, DATA_I4, DATA_I5, DATA_I6, DATA_I7, DATA_I8, DATA_I9, DATA_I10, DATA_I11, DATA_I12, DATA_I13, DATA_I14, DATA_I15, DATA_I16, DATA_I17, DATA_I18, DATA_I19, DATA_I20, DATA_I21
-, DATA_I22, DATA_I23, DATA_I24, DATA_I25, DATA_I26, DATA_I27, DATA_I28, DATA_I29, DATA_I30, DATA_I31, DATA_I32, DATA_I33, DATA_I34, DATA_I35, DATA_I36, DATA_I37, DATA_I38, DATA_I39, DATA_I40, DATA_I41, DATA_I42
-, DATA_I43, DATA_I44, DATA_I45, DATA_I46, DATA_I47, DATA_I48, DATA_I49, DATA_I50, DATA_I51, DATA_I52, DATA_I53, DATA_I54, DATA_I55, DATA_I56, DATA_I57, DATA_I58, DATA_I59, DATA_I60, DATA_I61, DATA_I62, DATA_I63
-, DATA_I64, BUSY_O, INV_K_O, PWDN_N_I, CLK_E_I, CLK_O, LINK);
-    output BUSY_O;
-    input CH_K_I1;
-    input CH_K_I2;
-    input CH_K_I3;
-    input CH_K_I4;
-    input CH_K_I5;
-    input CH_K_I6;
-    input CH_K_I7;
-    input CH_K_I8;
-    input CLK_E_I;
-    output CLK_O;
-    input DATA_I1;
-    input DATA_I10;
-    input DATA_I11;
-    input DATA_I12;
-    input DATA_I13;
-    input DATA_I14;
-    input DATA_I15;
-    input DATA_I16;
-    input DATA_I17;
-    input DATA_I18;
-    input DATA_I19;
-    input DATA_I2;
-    input DATA_I20;
-    input DATA_I21;
-    input DATA_I22;
-    input DATA_I23;
-    input DATA_I24;
-    input DATA_I25;
-    input DATA_I26;
-    input DATA_I27;
-    input DATA_I28;
-    input DATA_I29;
-    input DATA_I3;
-    input DATA_I30;
-    input DATA_I31;
-    input DATA_I32;
-    input DATA_I33;
-    input DATA_I34;
-    input DATA_I35;
-    input DATA_I36;
-    input DATA_I37;
-    input DATA_I38;
-    input DATA_I39;
-    input DATA_I4;
-    input DATA_I40;
-    input DATA_I41;
-    input DATA_I42;
-    input DATA_I43;
-    input DATA_I44;
-    input DATA_I45;
-    input DATA_I46;
-    input DATA_I47;
-    input DATA_I48;
-    input DATA_I49;
-    input DATA_I5;
-    input DATA_I50;
-    input DATA_I51;
-    input DATA_I52;
-    input DATA_I53;
-    input DATA_I54;
-    input DATA_I55;
-    input DATA_I56;
-    input DATA_I57;
-    input DATA_I58;
-    input DATA_I59;
-    input DATA_I6;
-    input DATA_I60;
-    input DATA_I61;
-    input DATA_I62;
-    input DATA_I63;
-    input DATA_I64;
-    input DATA_I7;
-    input DATA_I8;
-    input DATA_I9;
-    input ENC_E_I1;
-    input ENC_E_I2;
-    input ENC_E_I3;
-    input ENC_E_I4;
-    input ENC_E_I5;
-    input ENC_E_I6;
-    input ENC_E_I7;
-    input ENC_E_I8;
-    input EOF_I1;
-    input EOF_I2;
-    input EOF_I3;
-    input EOF_I4;
-    input EOF_I5;
-    input EOF_I6;
-    input EOF_I7;
-    input EOF_I8;
-    input EOMF_I1;
-    input EOMF_I2;
-    input EOMF_I3;
-    input EOMF_I4;
-    input EOMF_I5;
-    input EOMF_I6;
-    input EOMF_I7;
-    input EOMF_I8;
-    output INV_K_O;
-    inout [19:0] LINK;
-    input PWDN_N_I;
-    input REP_E_I;
-    input RST_N_I;
-    input SCR_E_I1;
-    input SCR_E_I2;
-    input SCR_E_I3;
-    input SCR_E_I4;
-    input SCR_E_I5;
-    input SCR_E_I6;
-    input SCR_E_I7;
-    input SCR_E_I8;
-    parameter gearbox_en = 1'b0;
-    parameter gearbox_mode = 1'b0;
-    parameter location = "";
-    parameter pcs_8b_scr_sel = 1'b0;
-    parameter pcs_bypass_pma_cdc = 1'b0;
-    parameter pcs_bypass_usr_cdc = 1'b0;
-    parameter pcs_enc_bypass = 1'b0;
-    parameter pcs_esistream_fsm_en = 1'b0;
-    parameter pcs_loopback = 1'b0;
-    parameter pcs_polarity = 1'b0;
-    parameter pcs_protocol_size = 1'b0;
-    parameter pcs_replace_bypass = 1'b0;
-    parameter pcs_scr_bypass = 1'b0;
-    parameter pcs_scr_init = 17'b00000000000000000;
-    parameter pcs_sync_supported = 1'b0;
-    parameter pma_clk_pos = 1'b0;
-    parameter pma_loopback = 1'b0;
-endmodule
-
 //(* blackbox *)
 //module NX_CY(A1, A2, A3, A4, B1, B2, B3, B4, CI, CO, S1, S2, S3, S4);
 //    input A1;
@@ -2000,817 +1304,6 @@ module NX_IOB_O(I, C, T, IO);
     parameter weakTermination = "";
 endmodule
 
-(* blackbox *)
-module NX_IOM(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, CCK, DCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1
-, C2RW2, C2RW3, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FZ, DC, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4
-, DRA5, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1, CAP2, CAP3
-, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3
-, DRO4, DRO5, DRO6, CAL, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EL, P1ER, P1EO, P1RI, P1RL, P1RR
-, P1RO1, P1RO2, P1RO3, P1RO4, P1RO5, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EL, P2ER, P2EO, P2RI, P2RL
-, P2RR, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P3CI1, P3CL, P3CR, P3CO, P3CTI, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EL, P3ER, P3EO, P3RI
-, P3RL, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EL, P4ER, P4EO
-, P4RI, P4RL, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P5CI1, P5CI2, P5CI3, P5CI4, P5CI5, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3
-, P5EI4, P5EI5, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P6CI1, P6CL, P6CR, P6CO, P6CTI, P6CTO, P6EI1, P6EI2
-, P6EI3, P6EI4, P6EI5, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1
-, P7EI2, P7EI3, P7EI4, P7EI5, P7EL, P7ER, P7EO, P7RI, P7RL, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO
-, P8EI1, P8EI2, P8EI3, P8EI4, P8EI5, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P9CI1, P9CL, P9CR, P9CO, P9CTI
-, P9CTO, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P10CI1, P10CL, P10CR, P10CO
-, P10CTI, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EL, P10ER, P10EO, P10RI, P10RL, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P11CI1, P11CL, P11CR
-, P11CO, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P12CI1, P12CL
-, P12CR, P12CO, P12CTI, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P13CI1
-, P13CL, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EL, P13ER, P13EO, P13RI, P13RL, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5
-, P14CI1, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4
-, P14RO5, P15CI1, P15CL, P15CR, P15CO, P15CTI, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3
-, P15RO4, P15RO5, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EL, P16ER, P16EO, P16RI, P16RL, P16RR, P16RO1, P16RO2
-, P16RO3, P16RO4, P16RO5, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1
-, P17RO2, P17RO3, P17RO4, P17RO5, P18CI1, P18CL, P18CR, P18CO, P18CTI, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR
-, P18RO1, P18RO2, P18RO3, P18RO4, P18RO5, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EL, P19ER, P19EO, P19RI, P19RL
-, P19RR, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EL, P20ER, P20EO, P20RI
-, P20RL, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P21CI1, P21CL, P21CR, P21CO, P21CTI, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EL, P21ER, P21EO
-, P21RI, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EL, P22ER
-, P22EO, P22RI, P22RL, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EL
-, P23ER, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P24CI1, P24CL, P24CR, P24CO, P24CTI, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5
-, P24EL, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P25CI1, P25CI2, P25CI3, P25CI4, P25CI5, P25CL, P25CR, P25CO, P25CTI, P25CTO
-, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5, P25EL, P25ER, P25EO, P25RI, P25RL, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P26CI1, P26CL, P26CR, P26CO, P26CTI
-, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4, P26EI5, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P27CI1, P27CL, P27CR, P27CO
-, P27CTI, P27CTO, P27EI1, P27EI2, P27EI3, P27EI4, P27EI5, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P28CI1, P28CL, P28CR
-, P28CO, P28CTI, P28CTO, P28EI1, P28EI2, P28EI3, P28EI4, P28EI5, P28EL, P28ER, P28EO, P28RI, P28RL, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P29CI1, P29CL
-, P29CR, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P30CI1
-, P30CL, P30CR, P30CO, P30CTI, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5
-);
-    output C1RED;
-    input C1RNE;
-    input C1RS;
-    input C1RW1;
-    input C1RW2;
-    input C1RW3;
-    input C1TS;
-    input C1TW;
-    output C2RED;
-    input C2RNE;
-    input C2RS;
-    input C2RW1;
-    input C2RW2;
-    input C2RW3;
-    input C2TS;
-    input C2TW;
-    input CAD1;
-    input CAD2;
-    input CAD3;
-    input CAD4;
-    input CAD5;
-    input CAD6;
-    output CAL;
-    input CAN1;
-    input CAN2;
-    input CAN3;
-    input CAN4;
-    input CAP1;
-    input CAP2;
-    input CAP3;
-    input CAP4;
-    input CAT1;
-    input CAT2;
-    input CAT3;
-    input CAT4;
-    input CCK;
-    output CKO1;
-    output CKO2;
-    input CTCK;
-    input DC;
-    input DCK;
-    input DIG;
-    input DIS;
-    input DOG;
-    input DOS;
-    input DPAG;
-    input DPAS;
-    input DQSG;
-    input DQSS;
-    input DRA1;
-    input DRA2;
-    input DRA3;
-    input DRA4;
-    input DRA5;
-    input DRI1;
-    input DRI2;
-    input DRI3;
-    input DRI4;
-    input DRI5;
-    input DRI6;
-    input DRL;
-    output DRO1;
-    output DRO2;
-    output DRO3;
-    output DRO4;
-    output DRO5;
-    output DRO6;
-    input DS1;
-    input DS2;
-    input FA1;
-    input FA2;
-    input FA3;
-    input FA4;
-    input FA5;
-    output FLD;
-    output FLG;
-    input FZ;
-    input P10CI1;
-    input P10CL;
-    output P10CO;
-    input P10CR;
-    input P10CTI;
-    output P10CTO;
-    input P10EI1;
-    input P10EI2;
-    input P10EI3;
-    input P10EI4;
-    input P10EI5;
-    input P10EL;
-    output P10EO;
-    input P10ER;
-    input P10RI;
-    input P10RL;
-    output P10RO1;
-    output P10RO2;
-    output P10RO3;
-    output P10RO4;
-    output P10RO5;
-    input P10RR;
-    input P11CI1;
-    input P11CL;
-    output P11CO;
-    input P11CR;
-    input P11CTI;
-    output P11CTO;
-    input P11EI1;
-    input P11EI2;
-    input P11EI3;
-    input P11EI4;
-    input P11EI5;
-    input P11EL;
-    output P11EO;
-    input P11ER;
-    input P11RI;
-    input P11RL;
-    output P11RO1;
-    output P11RO2;
-    output P11RO3;
-    output P11RO4;
-    output P11RO5;
-    input P11RR;
-    input P12CI1;
-    input P12CL;
-    output P12CO;
-    input P12CR;
-    input P12CTI;
-    output P12CTO;
-    input P12EI1;
-    input P12EI2;
-    input P12EI3;
-    input P12EI4;
-    input P12EI5;
-    input P12EL;
-    output P12EO;
-    input P12ER;
-    input P12RI;
-    input P12RL;
-    output P12RO1;
-    output P12RO2;
-    output P12RO3;
-    output P12RO4;
-    output P12RO5;
-    input P12RR;
-    input P13CI1;
-    input P13CL;
-    output P13CO;
-    input P13CR;
-    input P13CTI;
-    output P13CTO;
-    input P13EI1;
-    input P13EI2;
-    input P13EI3;
-    input P13EI4;
-    input P13EI5;
-    input P13EL;
-    output P13EO;
-    input P13ER;
-    input P13RI;
-    input P13RL;
-    output P13RO1;
-    output P13RO2;
-    output P13RO3;
-    output P13RO4;
-    output P13RO5;
-    input P13RR;
-    input P14CI1;
-    input P14CL;
-    output P14CO;
-    input P14CR;
-    input P14CTI;
-    output P14CTO;
-    input P14EI1;
-    input P14EI2;
-    input P14EI3;
-    input P14EI4;
-    input P14EI5;
-    input P14EL;
-    output P14EO;
-    input P14ER;
-    input P14RI;
-    input P14RL;
-    output P14RO1;
-    output P14RO2;
-    output P14RO3;
-    output P14RO4;
-    output P14RO5;
-    input P14RR;
-    input P15CI1;
-    input P15CL;
-    output P15CO;
-    input P15CR;
-    input P15CTI;
-    output P15CTO;
-    input P15EI1;
-    input P15EI2;
-    input P15EI3;
-    input P15EI4;
-    input P15EI5;
-    input P15EL;
-    output P15EO;
-    input P15ER;
-    input P15RI;
-    input P15RL;
-    output P15RO1;
-    output P15RO2;
-    output P15RO3;
-    output P15RO4;
-    output P15RO5;
-    input P15RR;
-    input P16CI1;
-    input P16CL;
-    output P16CO;
-    input P16CR;
-    input P16CTI;
-    output P16CTO;
-    input P16EI1;
-    input P16EI2;
-    input P16EI3;
-    input P16EI4;
-    input P16EI5;
-    input P16EL;
-    output P16EO;
-    input P16ER;
-    input P16RI;
-    input P16RL;
-    output P16RO1;
-    output P16RO2;
-    output P16RO3;
-    output P16RO4;
-    output P16RO5;
-    input P16RR;
-    input P17CI1;
-    input P17CL;
-    output P17CO;
-    input P17CR;
-    input P17CTI;
-    output P17CTO;
-    input P17EI1;
-    input P17EI2;
-    input P17EI3;
-    input P17EI4;
-    input P17EI5;
-    input P17EL;
-    output P17EO;
-    input P17ER;
-    input P17RI;
-    input P17RL;
-    output P17RO1;
-    output P17RO2;
-    output P17RO3;
-    output P17RO4;
-    output P17RO5;
-    input P17RR;
-    input P18CI1;
-    input P18CL;
-    output P18CO;
-    input P18CR;
-    input P18CTI;
-    output P18CTO;
-    input P18EI1;
-    input P18EI2;
-    input P18EI3;
-    input P18EI4;
-    input P18EI5;
-    input P18EL;
-    output P18EO;
-    input P18ER;
-    input P18RI;
-    input P18RL;
-    output P18RO1;
-    output P18RO2;
-    output P18RO3;
-    output P18RO4;
-    output P18RO5;
-    input P18RR;
-    input P19CI1;
-    input P19CL;
-    output P19CO;
-    input P19CR;
-    input P19CTI;
-    output P19CTO;
-    input P19EI1;
-    input P19EI2;
-    input P19EI3;
-    input P19EI4;
-    input P19EI5;
-    input P19EL;
-    output P19EO;
-    input P19ER;
-    input P19RI;
-    input P19RL;
-    output P19RO1;
-    output P19RO2;
-    output P19RO3;
-    output P19RO4;
-    output P19RO5;
-    input P19RR;
-    input P1CI1;
-    input P1CL;
-    output P1CO;
-    input P1CR;
-    input P1CTI;
-    output P1CTO;
-    input P1EI1;
-    input P1EI2;
-    input P1EI3;
-    input P1EI4;
-    input P1EI5;
-    input P1EL;
-    output P1EO;
-    input P1ER;
-    input P1RI;
-    input P1RL;
-    output P1RO1;
-    output P1RO2;
-    output P1RO3;
-    output P1RO4;
-    output P1RO5;
-    input P1RR;
-    input P20CI1;
-    input P20CL;
-    output P20CO;
-    input P20CR;
-    input P20CTI;
-    output P20CTO;
-    input P20EI1;
-    input P20EI2;
-    input P20EI3;
-    input P20EI4;
-    input P20EI5;
-    input P20EL;
-    output P20EO;
-    input P20ER;
-    input P20RI;
-    input P20RL;
-    output P20RO1;
-    output P20RO2;
-    output P20RO3;
-    output P20RO4;
-    output P20RO5;
-    input P20RR;
-    input P21CI1;
-    input P21CL;
-    output P21CO;
-    input P21CR;
-    input P21CTI;
-    output P21CTO;
-    input P21EI1;
-    input P21EI2;
-    input P21EI3;
-    input P21EI4;
-    input P21EI5;
-    input P21EL;
-    output P21EO;
-    input P21ER;
-    input P21RI;
-    input P21RL;
-    output P21RO1;
-    output P21RO2;
-    output P21RO3;
-    output P21RO4;
-    output P21RO5;
-    input P21RR;
-    input P22CI1;
-    input P22CL;
-    output P22CO;
-    input P22CR;
-    input P22CTI;
-    output P22CTO;
-    input P22EI1;
-    input P22EI2;
-    input P22EI3;
-    input P22EI4;
-    input P22EI5;
-    input P22EL;
-    output P22EO;
-    input P22ER;
-    input P22RI;
-    input P22RL;
-    output P22RO1;
-    output P22RO2;
-    output P22RO3;
-    output P22RO4;
-    output P22RO5;
-    input P22RR;
-    input P23CI1;
-    input P23CL;
-    output P23CO;
-    input P23CR;
-    input P23CTI;
-    output P23CTO;
-    input P23EI1;
-    input P23EI2;
-    input P23EI3;
-    input P23EI4;
-    input P23EI5;
-    input P23EL;
-    output P23EO;
-    input P23ER;
-    input P23RI;
-    input P23RL;
-    output P23RO1;
-    output P23RO2;
-    output P23RO3;
-    output P23RO4;
-    output P23RO5;
-    input P23RR;
-    input P24CI1;
-    input P24CL;
-    output P24CO;
-    input P24CR;
-    input P24CTI;
-    output P24CTO;
-    input P24EI1;
-    input P24EI2;
-    input P24EI3;
-    input P24EI4;
-    input P24EI5;
-    input P24EL;
-    output P24EO;
-    input P24ER;
-    input P24RI;
-    input P24RL;
-    output P24RO1;
-    output P24RO2;
-    output P24RO3;
-    output P24RO4;
-    output P24RO5;
-    input P24RR;
-    input P25CI1;
-    input P25CI2;
-    input P25CI3;
-    input P25CI4;
-    input P25CI5;
-    input P25CL;
-    output P25CO;
-    input P25CR;
-    input P25CTI;
-    output P25CTO;
-    input P25EI1;
-    input P25EI2;
-    input P25EI3;
-    input P25EI4;
-    input P25EI5;
-    input P25EL;
-    output P25EO;
-    input P25ER;
-    input P25RI;
-    input P25RL;
-    output P25RO1;
-    output P25RO2;
-    output P25RO3;
-    output P25RO4;
-    output P25RO5;
-    input P25RR;
-    input P26CI1;
-    input P26CL;
-    output P26CO;
-    input P26CR;
-    input P26CTI;
-    output P26CTO;
-    input P26EI1;
-    input P26EI2;
-    input P26EI3;
-    input P26EI4;
-    input P26EI5;
-    input P26EL;
-    output P26EO;
-    input P26ER;
-    input P26RI;
-    input P26RL;
-    output P26RO1;
-    output P26RO2;
-    output P26RO3;
-    output P26RO4;
-    output P26RO5;
-    input P26RR;
-    input P27CI1;
-    input P27CL;
-    output P27CO;
-    input P27CR;
-    input P27CTI;
-    output P27CTO;
-    input P27EI1;
-    input P27EI2;
-    input P27EI3;
-    input P27EI4;
-    input P27EI5;
-    input P27EL;
-    output P27EO;
-    input P27ER;
-    input P27RI;
-    input P27RL;
-    output P27RO1;
-    output P27RO2;
-    output P27RO3;
-    output P27RO4;
-    output P27RO5;
-    input P27RR;
-    input P28CI1;
-    input P28CL;
-    output P28CO;
-    input P28CR;
-    input P28CTI;
-    output P28CTO;
-    input P28EI1;
-    input P28EI2;
-    input P28EI3;
-    input P28EI4;
-    input P28EI5;
-    input P28EL;
-    output P28EO;
-    input P28ER;
-    input P28RI;
-    input P28RL;
-    output P28RO1;
-    output P28RO2;
-    output P28RO3;
-    output P28RO4;
-    output P28RO5;
-    input P28RR;
-    input P29CI1;
-    input P29CL;
-    output P29CO;
-    input P29CR;
-    input P29CTI;
-    output P29CTO;
-    input P29EI1;
-    input P29EI2;
-    input P29EI3;
-    input P29EI4;
-    input P29EI5;
-    input P29EL;
-    output P29EO;
-    input P29ER;
-    input P29RI;
-    input P29RL;
-    output P29RO1;
-    output P29RO2;
-    output P29RO3;
-    output P29RO4;
-    output P29RO5;
-    input P29RR;
-    input P2CI1;
-    input P2CL;
-    output P2CO;
-    input P2CR;
-    input P2CTI;
-    output P2CTO;
-    input P2EI1;
-    input P2EI2;
-    input P2EI3;
-    input P2EI4;
-    input P2EI5;
-    input P2EL;
-    output P2EO;
-    input P2ER;
-    input P2RI;
-    input P2RL;
-    output P2RO1;
-    output P2RO2;
-    output P2RO3;
-    output P2RO4;
-    output P2RO5;
-    input P2RR;
-    input P30CI1;
-    input P30CL;
-    output P30CO;
-    input P30CR;
-    input P30CTI;
-    output P30CTO;
-    input P30EI1;
-    input P30EI2;
-    input P30EI3;
-    input P30EI4;
-    input P30EI5;
-    input P30EL;
-    output P30EO;
-    input P30ER;
-    input P30RI;
-    input P30RL;
-    output P30RO1;
-    output P30RO2;
-    output P30RO3;
-    output P30RO4;
-    output P30RO5;
-    input P30RR;
-    input P3CI1;
-    input P3CL;
-    output P3CO;
-    input P3CR;
-    input P3CTI;
-    output P3CTO;
-    input P3EI1;
-    input P3EI2;
-    input P3EI3;
-    input P3EI4;
-    input P3EI5;
-    input P3EL;
-    output P3EO;
-    input P3ER;
-    input P3RI;
-    input P3RL;
-    output P3RO1;
-    output P3RO2;
-    output P3RO3;
-    output P3RO4;
-    output P3RO5;
-    input P3RR;
-    input P4CI1;
-    input P4CL;
-    output P4CO;
-    input P4CR;
-    input P4CTI;
-    output P4CTO;
-    input P4EI1;
-    input P4EI2;
-    input P4EI3;
-    input P4EI4;
-    input P4EI5;
-    input P4EL;
-    output P4EO;
-    input P4ER;
-    input P4RI;
-    input P4RL;
-    output P4RO1;
-    output P4RO2;
-    output P4RO3;
-    output P4RO4;
-    output P4RO5;
-    input P4RR;
-    input P5CI1;
-    input P5CI2;
-    input P5CI3;
-    input P5CI4;
-    input P5CI5;
-    input P5CL;
-    output P5CO;
-    input P5CR;
-    input P5CTI;
-    output P5CTO;
-    input P5EI1;
-    input P5EI2;
-    input P5EI3;
-    input P5EI4;
-    input P5EI5;
-    input P5EL;
-    output P5EO;
-    input P5ER;
-    input P5RI;
-    input P5RL;
-    output P5RO1;
-    output P5RO2;
-    output P5RO3;
-    output P5RO4;
-    output P5RO5;
-    input P5RR;
-    input P6CI1;
-    input P6CL;
-    output P6CO;
-    input P6CR;
-    input P6CTI;
-    output P6CTO;
-    input P6EI1;
-    input P6EI2;
-    input P6EI3;
-    input P6EI4;
-    input P6EI5;
-    input P6EL;
-    output P6EO;
-    input P6ER;
-    input P6RI;
-    input P6RL;
-    output P6RO1;
-    output P6RO2;
-    output P6RO3;
-    output P6RO4;
-    output P6RO5;
-    input P6RR;
-    input P7CI1;
-    input P7CL;
-    output P7CO;
-    input P7CR;
-    input P7CTI;
-    output P7CTO;
-    input P7EI1;
-    input P7EI2;
-    input P7EI3;
-    input P7EI4;
-    input P7EI5;
-    input P7EL;
-    output P7EO;
-    input P7ER;
-    input P7RI;
-    input P7RL;
-    output P7RO1;
-    output P7RO2;
-    output P7RO3;
-    output P7RO4;
-    output P7RO5;
-    input P7RR;
-    input P8CI1;
-    input P8CL;
-    output P8CO;
-    input P8CR;
-    input P8CTI;
-    output P8CTO;
-    input P8EI1;
-    input P8EI2;
-    input P8EI3;
-    input P8EI4;
-    input P8EI5;
-    input P8EL;
-    output P8EO;
-    input P8ER;
-    input P8RI;
-    input P8RL;
-    output P8RO1;
-    output P8RO2;
-    output P8RO3;
-    output P8RO4;
-    output P8RO5;
-    input P8RR;
-    input P9CI1;
-    input P9CL;
-    output P9CO;
-    input P9CR;
-    input P9CTI;
-    output P9CTO;
-    input P9EI1;
-    input P9EI2;
-    input P9EI3;
-    input P9EI4;
-    input P9EI5;
-    input P9EL;
-    output P9EO;
-    input P9ER;
-    input P9RI;
-    input P9RL;
-    output P9RO1;
-    output P9RO2;
-    output P9RO3;
-    output P9RO4;
-    output P9RO5;
-    input P9RR;
-    input RRCK1;
-    input RRCK2;
-    input RTCK1;
-    input RTCK2;
-    input SPI1;
-    input SPI2;
-    input SPI3;
-    input WRCK1;
-    input WRCK2;
-    input WTCK1;
-    input WTCK2;
-    parameter div_rx1 = 4'b0000;
-    parameter div_rx2 = 4'b0000;
-    parameter div_tx1 = 4'b0000;
-    parameter div_tx2 = 4'b0000;
-    parameter mode_io_cal = 1'b0;
-    parameter mode_side1 = 0;
-    parameter mode_side2 = 0;
-    parameter pads_dict = "";
-    parameter pads_path = "";
-    parameter sel_clk_out1 = 1'b0;
-    parameter sel_clk_out2 = 1'b0;
-    parameter sel_clkr_rx1 = 1'b0;
-    parameter sel_clkr_rx2 = 1'b0;
-    parameter sel_clkw_rx1 = 2'b00;
-    parameter sel_clkw_rx2 = 2'b00;
-endmodule
-
 (* blackbox *)
 module NX_IOM_BIN2GRP(GS, DS, GVON, GVIN, GVDN, PA, LA);
     input [1:0] DS;
@@ -3673,908 +2166,6 @@ module NX_IOM_DRIVER_U(EI1, EI2, EI3, EI4, EI5, EI6, EI7, EI8, EL, ER, CI1, CL,
     parameter tpath_mode = 1'b0;
 endmodule
 
-(* blackbox *)
-module NX_IOM_L(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, CCK, DCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1
-, C2RW2, C2RW3, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3
-, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1
-, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3, DRO4
-, DRO5, DRO6, CAL, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EL, P1ER, P1EO, P1RI, P1RL, P1RR, P1RO1
-, P1RO2, P1RO3, P1RO4, P1RO5, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EL, P2ER, P2EO, P2RI, P2RL, P2RR
-, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P3CI1, P3CL, P3CR, P3CO, P3CTI, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EL, P3ER, P3EO, P3RI, P3RL
-, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EL, P4ER, P4EO, P4RI
-, P4RL, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P5CI1, P5CI2, P5CI3, P5CI4, P5CI5, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3, P5EI4
-, P5EI5, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P6CI1, P6CL, P6CR, P6CO, P6CTI, P6CTO, P6EI1, P6EI2, P6EI3
-, P6EI4, P6EI5, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1, P7EI2
-, P7EI3, P7EI4, P7EI5, P7EL, P7ER, P7EO, P7RI, P7RL, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO, P8EI1
-, P8EI2, P8EI3, P8EI4, P8EI5, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P9CI1, P9CL, P9CR, P9CO, P9CTI, P9CTO
-, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P10CI1, P10CL, P10CR, P10CO, P10CTI
-, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EL, P10ER, P10EO, P10RI, P10RL, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P11CI1, P11CL, P11CR, P11CO
-, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P12CI1, P12CL, P12CR
-, P12CO, P12CTI, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P13CI1, P13CL
-, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EL, P13ER, P13EO, P13RI, P13RL, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5, P14CI1
-, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4, P14RO5
-, P15CI1, P15CL, P15CR, P15CO, P15CTI, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3, P15RO4
-, P15RO5, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EL, P16ER, P16EO, P16RI, P16RL, P16RR, P16RO1, P16RO2, P16RO3
-, P16RO4, P16RO5, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1, P17RO2
-, P17RO3, P17RO4, P17RO5, P18CI1, P18CL, P18CR, P18CO, P18CTI, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR, P18RO1
-, P18RO2, P18RO3, P18RO4, P18RO5, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EL, P19ER, P19EO, P19RI, P19RL, P19RR
-, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EL, P20ER, P20EO, P20RI, P20RL
-, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P21CI1, P21CL, P21CR, P21CO, P21CTI, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EL, P21ER, P21EO, P21RI
-, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EL, P22ER, P22EO
-, P22RI, P22RL, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EL, P23ER
-, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P24CI1, P24CL, P24CR, P24CO, P24CTI, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5, P24EL
-, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P25CI1, P25CL, P25CR, P25CO, P25CTI, P25CTO, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5
-, P25EL, P25ER, P25EO, P25RI, P25RL, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P26CI1, P26CL, P26CR, P26CO, P26CTI, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4
-, P26EI5, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P27CI1, P27CL, P27CR, P27CO, P27CTI, P27CTO, P27EI1, P27EI2, P27EI3
-, P27EI4, P27EI5, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P28CI1, P28CL, P28CR, P28CO, P28CTI, P28CTO, P28EI1, P28EI2
-, P28EI3, P28EI4, P28EI5, P28EL, P28ER, P28EO, P28RI, P28RL, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P29CI1, P29CI2, P29CI3, P29CI4, P29CI5, P29CL, P29CR
-, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P30CI1, P30CL
-, P30CR, P30CO, P30CTI, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5, P31CI1
-, P31CL, P31CR, P31CO, P31CTI, P31CTO, P31EI1, P31EI2, P31EI3, P31EI4, P31EI5, P31EL, P31ER, P31EO, P31RI, P31RL, P31RR, P31RO1, P31RO2, P31RO3, P31RO4, P31RO5
-, P32CI1, P32CL, P32CR, P32CO, P32CTI, P32CTO, P32EI1, P32EI2, P32EI3, P32EI4, P32EI5, P32EL, P32ER, P32EO, P32RI, P32RL, P32RR, P32RO1, P32RO2, P32RO3, P32RO4
-, P32RO5, P33CI1, P33CL, P33CR, P33CO, P33CTI, P33CTO, P33EI1, P33EI2, P33EI3, P33EI4, P33EI5, P33EL, P33ER, P33EO, P33RI, P33RL, P33RR, P33RO1, P33RO2, P33RO3
-, P33RO4, P33RO5, P34CI1, P34CL, P34CR, P34CO, P34CTI, P34CTO, P34EI1, P34EI2, P34EI3, P34EI4, P34EI5, P34EL, P34ER, P34EO, P34RI, P34RL, P34RR, P34RO1, P34RO2
-, P34RO3, P34RO4, P34RO5);
-    output C1RED;
-    input C1RNE;
-    input C1RS;
-    input C1RW1;
-    input C1RW2;
-    input C1RW3;
-    input C1TS;
-    input C1TW;
-    output C2RED;
-    input C2RNE;
-    input C2RS;
-    input C2RW1;
-    input C2RW2;
-    input C2RW3;
-    input C2TS;
-    input C2TW;
-    input CAD1;
-    input CAD2;
-    input CAD3;
-    input CAD4;
-    input CAD5;
-    input CAD6;
-    output CAL;
-    input CAN1;
-    input CAN2;
-    input CAN3;
-    input CAN4;
-    input CAP1;
-    input CAP2;
-    input CAP3;
-    input CAP4;
-    input CAT1;
-    input CAT2;
-    input CAT3;
-    input CAT4;
-    input CCK;
-    output CKO1;
-    output CKO2;
-    input CTCK;
-    input DC;
-    input DCK;
-    input DIG;
-    input DIS;
-    input DOG;
-    input DOS;
-    input DPAG;
-    input DPAS;
-    input DQSG;
-    input DQSS;
-    input DRA1;
-    input DRA2;
-    input DRA3;
-    input DRA4;
-    input DRA5;
-    input DRA6;
-    input DRI1;
-    input DRI2;
-    input DRI3;
-    input DRI4;
-    input DRI5;
-    input DRI6;
-    input DRL;
-    output DRO1;
-    output DRO2;
-    output DRO3;
-    output DRO4;
-    output DRO5;
-    output DRO6;
-    input DS1;
-    input DS2;
-    input FA1;
-    input FA2;
-    input FA3;
-    input FA4;
-    input FA5;
-    input FA6;
-    output FLD;
-    output FLG;
-    input FZ;
-    input P10CI1;
-    input P10CL;
-    output P10CO;
-    input P10CR;
-    input P10CTI;
-    output P10CTO;
-    input P10EI1;
-    input P10EI2;
-    input P10EI3;
-    input P10EI4;
-    input P10EI5;
-    input P10EL;
-    output P10EO;
-    input P10ER;
-    input P10RI;
-    input P10RL;
-    output P10RO1;
-    output P10RO2;
-    output P10RO3;
-    output P10RO4;
-    output P10RO5;
-    input P10RR;
-    input P11CI1;
-    input P11CL;
-    output P11CO;
-    input P11CR;
-    input P11CTI;
-    output P11CTO;
-    input P11EI1;
-    input P11EI2;
-    input P11EI3;
-    input P11EI4;
-    input P11EI5;
-    input P11EL;
-    output P11EO;
-    input P11ER;
-    input P11RI;
-    input P11RL;
-    output P11RO1;
-    output P11RO2;
-    output P11RO3;
-    output P11RO4;
-    output P11RO5;
-    input P11RR;
-    input P12CI1;
-    input P12CL;
-    output P12CO;
-    input P12CR;
-    input P12CTI;
-    output P12CTO;
-    input P12EI1;
-    input P12EI2;
-    input P12EI3;
-    input P12EI4;
-    input P12EI5;
-    input P12EL;
-    output P12EO;
-    input P12ER;
-    input P12RI;
-    input P12RL;
-    output P12RO1;
-    output P12RO2;
-    output P12RO3;
-    output P12RO4;
-    output P12RO5;
-    input P12RR;
-    input P13CI1;
-    input P13CL;
-    output P13CO;
-    input P13CR;
-    input P13CTI;
-    output P13CTO;
-    input P13EI1;
-    input P13EI2;
-    input P13EI3;
-    input P13EI4;
-    input P13EI5;
-    input P13EL;
-    output P13EO;
-    input P13ER;
-    input P13RI;
-    input P13RL;
-    output P13RO1;
-    output P13RO2;
-    output P13RO3;
-    output P13RO4;
-    output P13RO5;
-    input P13RR;
-    input P14CI1;
-    input P14CL;
-    output P14CO;
-    input P14CR;
-    input P14CTI;
-    output P14CTO;
-    input P14EI1;
-    input P14EI2;
-    input P14EI3;
-    input P14EI4;
-    input P14EI5;
-    input P14EL;
-    output P14EO;
-    input P14ER;
-    input P14RI;
-    input P14RL;
-    output P14RO1;
-    output P14RO2;
-    output P14RO3;
-    output P14RO4;
-    output P14RO5;
-    input P14RR;
-    input P15CI1;
-    input P15CL;
-    output P15CO;
-    input P15CR;
-    input P15CTI;
-    output P15CTO;
-    input P15EI1;
-    input P15EI2;
-    input P15EI3;
-    input P15EI4;
-    input P15EI5;
-    input P15EL;
-    output P15EO;
-    input P15ER;
-    input P15RI;
-    input P15RL;
-    output P15RO1;
-    output P15RO2;
-    output P15RO3;
-    output P15RO4;
-    output P15RO5;
-    input P15RR;
-    input P16CI1;
-    input P16CL;
-    output P16CO;
-    input P16CR;
-    input P16CTI;
-    output P16CTO;
-    input P16EI1;
-    input P16EI2;
-    input P16EI3;
-    input P16EI4;
-    input P16EI5;
-    input P16EL;
-    output P16EO;
-    input P16ER;
-    input P16RI;
-    input P16RL;
-    output P16RO1;
-    output P16RO2;
-    output P16RO3;
-    output P16RO4;
-    output P16RO5;
-    input P16RR;
-    input P17CI1;
-    input P17CL;
-    output P17CO;
-    input P17CR;
-    input P17CTI;
-    output P17CTO;
-    input P17EI1;
-    input P17EI2;
-    input P17EI3;
-    input P17EI4;
-    input P17EI5;
-    input P17EL;
-    output P17EO;
-    input P17ER;
-    input P17RI;
-    input P17RL;
-    output P17RO1;
-    output P17RO2;
-    output P17RO3;
-    output P17RO4;
-    output P17RO5;
-    input P17RR;
-    input P18CI1;
-    input P18CL;
-    output P18CO;
-    input P18CR;
-    input P18CTI;
-    output P18CTO;
-    input P18EI1;
-    input P18EI2;
-    input P18EI3;
-    input P18EI4;
-    input P18EI5;
-    input P18EL;
-    output P18EO;
-    input P18ER;
-    input P18RI;
-    input P18RL;
-    output P18RO1;
-    output P18RO2;
-    output P18RO3;
-    output P18RO4;
-    output P18RO5;
-    input P18RR;
-    input P19CI1;
-    input P19CL;
-    output P19CO;
-    input P19CR;
-    input P19CTI;
-    output P19CTO;
-    input P19EI1;
-    input P19EI2;
-    input P19EI3;
-    input P19EI4;
-    input P19EI5;
-    input P19EL;
-    output P19EO;
-    input P19ER;
-    input P19RI;
-    input P19RL;
-    output P19RO1;
-    output P19RO2;
-    output P19RO3;
-    output P19RO4;
-    output P19RO5;
-    input P19RR;
-    input P1CI1;
-    input P1CL;
-    output P1CO;
-    input P1CR;
-    input P1CTI;
-    output P1CTO;
-    input P1EI1;
-    input P1EI2;
-    input P1EI3;
-    input P1EI4;
-    input P1EI5;
-    input P1EL;
-    output P1EO;
-    input P1ER;
-    input P1RI;
-    input P1RL;
-    output P1RO1;
-    output P1RO2;
-    output P1RO3;
-    output P1RO4;
-    output P1RO5;
-    input P1RR;
-    input P20CI1;
-    input P20CL;
-    output P20CO;
-    input P20CR;
-    input P20CTI;
-    output P20CTO;
-    input P20EI1;
-    input P20EI2;
-    input P20EI3;
-    input P20EI4;
-    input P20EI5;
-    input P20EL;
-    output P20EO;
-    input P20ER;
-    input P20RI;
-    input P20RL;
-    output P20RO1;
-    output P20RO2;
-    output P20RO3;
-    output P20RO4;
-    output P20RO5;
-    input P20RR;
-    input P21CI1;
-    input P21CL;
-    output P21CO;
-    input P21CR;
-    input P21CTI;
-    output P21CTO;
-    input P21EI1;
-    input P21EI2;
-    input P21EI3;
-    input P21EI4;
-    input P21EI5;
-    input P21EL;
-    output P21EO;
-    input P21ER;
-    input P21RI;
-    input P21RL;
-    output P21RO1;
-    output P21RO2;
-    output P21RO3;
-    output P21RO4;
-    output P21RO5;
-    input P21RR;
-    input P22CI1;
-    input P22CL;
-    output P22CO;
-    input P22CR;
-    input P22CTI;
-    output P22CTO;
-    input P22EI1;
-    input P22EI2;
-    input P22EI3;
-    input P22EI4;
-    input P22EI5;
-    input P22EL;
-    output P22EO;
-    input P22ER;
-    input P22RI;
-    input P22RL;
-    output P22RO1;
-    output P22RO2;
-    output P22RO3;
-    output P22RO4;
-    output P22RO5;
-    input P22RR;
-    input P23CI1;
-    input P23CL;
-    output P23CO;
-    input P23CR;
-    input P23CTI;
-    output P23CTO;
-    input P23EI1;
-    input P23EI2;
-    input P23EI3;
-    input P23EI4;
-    input P23EI5;
-    input P23EL;
-    output P23EO;
-    input P23ER;
-    input P23RI;
-    input P23RL;
-    output P23RO1;
-    output P23RO2;
-    output P23RO3;
-    output P23RO4;
-    output P23RO5;
-    input P23RR;
-    input P24CI1;
-    input P24CL;
-    output P24CO;
-    input P24CR;
-    input P24CTI;
-    output P24CTO;
-    input P24EI1;
-    input P24EI2;
-    input P24EI3;
-    input P24EI4;
-    input P24EI5;
-    input P24EL;
-    output P24EO;
-    input P24ER;
-    input P24RI;
-    input P24RL;
-    output P24RO1;
-    output P24RO2;
-    output P24RO3;
-    output P24RO4;
-    output P24RO5;
-    input P24RR;
-    input P25CI1;
-    input P25CL;
-    output P25CO;
-    input P25CR;
-    input P25CTI;
-    output P25CTO;
-    input P25EI1;
-    input P25EI2;
-    input P25EI3;
-    input P25EI4;
-    input P25EI5;
-    input P25EL;
-    output P25EO;
-    input P25ER;
-    input P25RI;
-    input P25RL;
-    output P25RO1;
-    output P25RO2;
-    output P25RO3;
-    output P25RO4;
-    output P25RO5;
-    input P25RR;
-    input P26CI1;
-    input P26CL;
-    output P26CO;
-    input P26CR;
-    input P26CTI;
-    output P26CTO;
-    input P26EI1;
-    input P26EI2;
-    input P26EI3;
-    input P26EI4;
-    input P26EI5;
-    input P26EL;
-    output P26EO;
-    input P26ER;
-    input P26RI;
-    input P26RL;
-    output P26RO1;
-    output P26RO2;
-    output P26RO3;
-    output P26RO4;
-    output P26RO5;
-    input P26RR;
-    input P27CI1;
-    input P27CL;
-    output P27CO;
-    input P27CR;
-    input P27CTI;
-    output P27CTO;
-    input P27EI1;
-    input P27EI2;
-    input P27EI3;
-    input P27EI4;
-    input P27EI5;
-    input P27EL;
-    output P27EO;
-    input P27ER;
-    input P27RI;
-    input P27RL;
-    output P27RO1;
-    output P27RO2;
-    output P27RO3;
-    output P27RO4;
-    output P27RO5;
-    input P27RR;
-    input P28CI1;
-    input P28CL;
-    output P28CO;
-    input P28CR;
-    input P28CTI;
-    output P28CTO;
-    input P28EI1;
-    input P28EI2;
-    input P28EI3;
-    input P28EI4;
-    input P28EI5;
-    input P28EL;
-    output P28EO;
-    input P28ER;
-    input P28RI;
-    input P28RL;
-    output P28RO1;
-    output P28RO2;
-    output P28RO3;
-    output P28RO4;
-    output P28RO5;
-    input P28RR;
-    input P29CI1;
-    input P29CI2;
-    input P29CI3;
-    input P29CI4;
-    input P29CI5;
-    input P29CL;
-    output P29CO;
-    input P29CR;
-    input P29CTI;
-    output P29CTO;
-    input P29EI1;
-    input P29EI2;
-    input P29EI3;
-    input P29EI4;
-    input P29EI5;
-    input P29EL;
-    output P29EO;
-    input P29ER;
-    input P29RI;
-    input P29RL;
-    output P29RO1;
-    output P29RO2;
-    output P29RO3;
-    output P29RO4;
-    output P29RO5;
-    input P29RR;
-    input P2CI1;
-    input P2CL;
-    output P2CO;
-    input P2CR;
-    input P2CTI;
-    output P2CTO;
-    input P2EI1;
-    input P2EI2;
-    input P2EI3;
-    input P2EI4;
-    input P2EI5;
-    input P2EL;
-    output P2EO;
-    input P2ER;
-    input P2RI;
-    input P2RL;
-    output P2RO1;
-    output P2RO2;
-    output P2RO3;
-    output P2RO4;
-    output P2RO5;
-    input P2RR;
-    input P30CI1;
-    input P30CL;
-    output P30CO;
-    input P30CR;
-    input P30CTI;
-    output P30CTO;
-    input P30EI1;
-    input P30EI2;
-    input P30EI3;
-    input P30EI4;
-    input P30EI5;
-    input P30EL;
-    output P30EO;
-    input P30ER;
-    input P30RI;
-    input P30RL;
-    output P30RO1;
-    output P30RO2;
-    output P30RO3;
-    output P30RO4;
-    output P30RO5;
-    input P30RR;
-    input P31CI1;
-    input P31CL;
-    output P31CO;
-    input P31CR;
-    input P31CTI;
-    output P31CTO;
-    input P31EI1;
-    input P31EI2;
-    input P31EI3;
-    input P31EI4;
-    input P31EI5;
-    input P31EL;
-    output P31EO;
-    input P31ER;
-    input P31RI;
-    input P31RL;
-    output P31RO1;
-    output P31RO2;
-    output P31RO3;
-    output P31RO4;
-    output P31RO5;
-    input P31RR;
-    input P32CI1;
-    input P32CL;
-    output P32CO;
-    input P32CR;
-    input P32CTI;
-    output P32CTO;
-    input P32EI1;
-    input P32EI2;
-    input P32EI3;
-    input P32EI4;
-    input P32EI5;
-    input P32EL;
-    output P32EO;
-    input P32ER;
-    input P32RI;
-    input P32RL;
-    output P32RO1;
-    output P32RO2;
-    output P32RO3;
-    output P32RO4;
-    output P32RO5;
-    input P32RR;
-    input P33CI1;
-    input P33CL;
-    output P33CO;
-    input P33CR;
-    input P33CTI;
-    output P33CTO;
-    input P33EI1;
-    input P33EI2;
-    input P33EI3;
-    input P33EI4;
-    input P33EI5;
-    input P33EL;
-    output P33EO;
-    input P33ER;
-    input P33RI;
-    input P33RL;
-    output P33RO1;
-    output P33RO2;
-    output P33RO3;
-    output P33RO4;
-    output P33RO5;
-    input P33RR;
-    input P34CI1;
-    input P34CL;
-    output P34CO;
-    input P34CR;
-    input P34CTI;
-    output P34CTO;
-    input P34EI1;
-    input P34EI2;
-    input P34EI3;
-    input P34EI4;
-    input P34EI5;
-    input P34EL;
-    output P34EO;
-    input P34ER;
-    input P34RI;
-    input P34RL;
-    output P34RO1;
-    output P34RO2;
-    output P34RO3;
-    output P34RO4;
-    output P34RO5;
-    input P34RR;
-    input P3CI1;
-    input P3CL;
-    output P3CO;
-    input P3CR;
-    input P3CTI;
-    output P3CTO;
-    input P3EI1;
-    input P3EI2;
-    input P3EI3;
-    input P3EI4;
-    input P3EI5;
-    input P3EL;
-    output P3EO;
-    input P3ER;
-    input P3RI;
-    input P3RL;
-    output P3RO1;
-    output P3RO2;
-    output P3RO3;
-    output P3RO4;
-    output P3RO5;
-    input P3RR;
-    input P4CI1;
-    input P4CL;
-    output P4CO;
-    input P4CR;
-    input P4CTI;
-    output P4CTO;
-    input P4EI1;
-    input P4EI2;
-    input P4EI3;
-    input P4EI4;
-    input P4EI5;
-    input P4EL;
-    output P4EO;
-    input P4ER;
-    input P4RI;
-    input P4RL;
-    output P4RO1;
-    output P4RO2;
-    output P4RO3;
-    output P4RO4;
-    output P4RO5;
-    input P4RR;
-    input P5CI1;
-    input P5CI2;
-    input P5CI3;
-    input P5CI4;
-    input P5CI5;
-    input P5CL;
-    output P5CO;
-    input P5CR;
-    input P5CTI;
-    output P5CTO;
-    input P5EI1;
-    input P5EI2;
-    input P5EI3;
-    input P5EI4;
-    input P5EI5;
-    input P5EL;
-    output P5EO;
-    input P5ER;
-    input P5RI;
-    input P5RL;
-    output P5RO1;
-    output P5RO2;
-    output P5RO3;
-    output P5RO4;
-    output P5RO5;
-    input P5RR;
-    input P6CI1;
-    input P6CL;
-    output P6CO;
-    input P6CR;
-    input P6CTI;
-    output P6CTO;
-    input P6EI1;
-    input P6EI2;
-    input P6EI3;
-    input P6EI4;
-    input P6EI5;
-    input P6EL;
-    output P6EO;
-    input P6ER;
-    input P6RI;
-    input P6RL;
-    output P6RO1;
-    output P6RO2;
-    output P6RO3;
-    output P6RO4;
-    output P6RO5;
-    input P6RR;
-    input P7CI1;
-    input P7CL;
-    output P7CO;
-    input P7CR;
-    input P7CTI;
-    output P7CTO;
-    input P7EI1;
-    input P7EI2;
-    input P7EI3;
-    input P7EI4;
-    input P7EI5;
-    input P7EL;
-    output P7EO;
-    input P7ER;
-    input P7RI;
-    input P7RL;
-    output P7RO1;
-    output P7RO2;
-    output P7RO3;
-    output P7RO4;
-    output P7RO5;
-    input P7RR;
-    input P8CI1;
-    input P8CL;
-    output P8CO;
-    input P8CR;
-    input P8CTI;
-    output P8CTO;
-    input P8EI1;
-    input P8EI2;
-    input P8EI3;
-    input P8EI4;
-    input P8EI5;
-    input P8EL;
-    output P8EO;
-    input P8ER;
-    input P8RI;
-    input P8RL;
-    output P8RO1;
-    output P8RO2;
-    output P8RO3;
-    output P8RO4;
-    output P8RO5;
-    input P8RR;
-    input P9CI1;
-    input P9CL;
-    output P9CO;
-    input P9CR;
-    input P9CTI;
-    output P9CTO;
-    input P9EI1;
-    input P9EI2;
-    input P9EI3;
-    input P9EI4;
-    input P9EI5;
-    input P9EL;
-    output P9EO;
-    input P9ER;
-    input P9RI;
-    input P9RL;
-    output P9RO1;
-    output P9RO2;
-    output P9RO3;
-    output P9RO4;
-    output P9RO5;
-    input P9RR;
-    input RRCK1;
-    input RRCK2;
-    input RTCK1;
-    input RTCK2;
-    input WRCK1;
-    input WRCK2;
-    input WTCK1;
-    input WTCK2;
-    parameter div_rx1 = 4'b0000;
-    parameter div_rx2 = 4'b0000;
-    parameter div_tx1 = 4'b0000;
-    parameter div_tx2 = 4'b0000;
-    parameter mode_io_cal = 1'b0;
-    parameter mode_side1 = 0;
-    parameter mode_side2 = 0;
-    parameter pads_dict = "";
-    parameter pads_path = "";
-    parameter sel_clk_out1 = 1'b0;
-    parameter sel_clk_out2 = 1'b0;
-    parameter sel_clkr_rx1 = 1'b0;
-    parameter sel_clkr_rx2 = 1'b0;
-    parameter sel_clkw_rx1 = 2'b00;
-    parameter sel_clkw_rx2 = 2'b00;
-endmodule
-
 (* blackbox *)
 module NX_IOM_SERDES(RTCK, WRCK, WTCK, RRCK, TRST, RRST, CTCK, DCK, DRL, DIG, FZ, FLD, FLG, DS, DRA, DRI, DRO, DID, LINKN, LINKP);
     input CTCK;
@@ -4653,1189 +2244,6 @@ module NX_IOM_SERDES_U(FCK, SCK, LDRN, DRWDS, DRWEN, DRE, FZ, ALD, ALT, FLD, FLG
     parameter location = "";
 endmodule
 
-(* blackbox *)
-module NX_IOM_U(ALCK1, ALCK2, ALCK3, LDSCK1, LDSCK2, LDSCK3, SWRX1CK, SWRX2CK, FCK1, FCK2, FDCK, CCK, DQ1CI1, DQ1CI2, DQ1CI3, DQ1CI4, DQ1CI5, DQ1CI6, DQ1CI7, DQ1CI8, DQ2CI1
-, DQ2CI2, DQ2CI3, DQ2CI4, DQ2CI5, DQ2CI6, DQ2CI7, DQ2CI8, DQ3CI1, DQ3CI2, DQ3CI3, DQ3CI4, DQ3CI5, DQ3CI6, DQ3CI7, DQ3CI8, DQS1CI1, DQS1CI2, DQS1CI3, DQS1CI4, DQS1CI5, DQS1CI6
-, DQS1CI7, DQS1CI8, DQS2CI1, DQS2CI2, DQS2CI3, DQS2CI4, DQS2CI5, DQS2CI6, DQS2CI7, DQS2CI8, DQS3CI1, DQS3CI2, DQS3CI3, DQS3CI4, DQS3CI5, DQS3CI6, DQS3CI7, DQS3CI8, LD1RN, LD2RN, LD3RN
-, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DCRN, LE, SE, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4, DRO1CSN
-, DRO2CSN, DRO3CSN, DRI1CSN, DRI2CSN, DRI3CSN, DRDPA1CSN, DRDPA2CSN, DRDPA3CSN, DRCCSN, DRWDS, DRWEN, DRE, CA1P1, CA1P2, CA1P3, CA1P4, CA2P1, CA2P2, CA2P3, CA2P4, CA1N1
-, CA1N2, CA1N3, CA1N4, CA2N1, CA2N2, CA2N3, CA2N4, CA1T1, CA1T2, CA1T3, CA1T4, CA2T1, CA2T2, CA2T3, CA2T4, CA1D1, CA1D2, CA1D3, CA1D4, CA1D5, CA1D6
-, CA2D1, CA2D2, CA2D3, CA2D4, CA2D5, CA2D6, CKO1, CKO2, FLD, FLG, AL1D, AL2D, AL3D, AL1T, AL2T, AL3T, DCL, DRO1, DRO2, DRO3, DRO4
-, DRO5, DRO6, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EI6, P1EI7, P1EI8, P1EL, P1ER, P1EO, P1RI, P1RL
-, P1RR, P1RO1, P1RO2, P1RO3, P1RO4, P1RO5, P1RO6, P1RO7, P1RO8, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EI6
-, P2EI7, P2EI8, P2EL, P2ER, P2EO, P2RI, P2RL, P2RR, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P2RO6, P2RO7, P2RO8, P3CI1, P3CL, P3CR, P3CO, P3CTI
-, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EI6, P3EI7, P3EI8, P3EL, P3ER, P3EO, P3RI, P3RL, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P3RO6
-, P3RO7, P3RO8, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EI6, P4EI7, P4EI8, P4EL, P4ER, P4EO, P4RI, P4RL
-, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P4RO6, P4RO7, P4RO8, P5CI1, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3, P5EI4, P5EI5, P5EI6
-, P5EI7, P5EI8, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P5RO6, P5RO7, P5RO8, P6CI1, P6CL, P6CR, P6CO, P6CTI
-, P6CTO, P6EI1, P6EI2, P6EI3, P6EI4, P6EI5, P6EI6, P6EI7, P6EI8, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P6RO6
-, P6RO7, P6RO8, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1, P7EI2, P7EI3, P7EI4, P7EI5, P7EI6, P7EI7, P7EI8, P7EL, P7ER, P7EO, P7RI, P7RL
-, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P7RO6, P7RO7, P7RO8, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO, P8EI1, P8EI2, P8EI3, P8EI4, P8EI5, P8EI6
-, P8EI7, P8EI8, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P8RO6, P8RO7, P8RO8, P9CI1, P9CL, P9CR, P9CO, P9CTI
-, P9CTO, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EI6, P9EI7, P9EI8, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P9RO6
-, P9RO7, P9RO8, P10CI1, P10CL, P10CR, P10CO, P10CTI, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EI6, P10EI7, P10EI8, P10EL, P10ER, P10EO, P10RI, P10RL
-, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P10RO6, P10RO7, P10RO8, P11CI1, P11CL, P11CR, P11CO, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EI6
-, P11EI7, P11EI8, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P11RO6, P11RO7, P11RO8, P12CI1, P12CL, P12CR, P12CO, P12CTI
-, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EI6, P12EI7, P12EI8, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P12RO6
-, P12RO7, P12RO8, P13CI1, P13CL, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EI6, P13EI7, P13EI8, P13EL, P13ER, P13EO, P13RI, P13RL
-, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5, P13RO6, P13RO7, P13RO8, P14CI1, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EI6
-, P14EI7, P14EI8, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4, P14RO5, P14RO6, P14RO7, P14RO8, P15CI1, P15CL, P15CR, P15CO, P15CTI
-, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EI6, P15EI7, P15EI8, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3, P15RO4, P15RO5, P15RO6
-, P15RO7, P15RO8, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EI6, P16EI7, P16EI8, P16EL, P16ER, P16EO, P16RI, P16RL
-, P16RR, P16RO1, P16RO2, P16RO3, P16RO4, P16RO5, P16RO6, P16RO7, P16RO8, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EI6
-, P17EI7, P17EI8, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1, P17RO2, P17RO3, P17RO4, P17RO5, P17RO6, P17RO7, P17RO8, P18CI1, P18CL, P18CR, P18CO, P18CTI
-, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EI6, P18EI7, P18EI8, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR, P18RO1, P18RO2, P18RO3, P18RO4, P18RO5, P18RO6
-, P18RO7, P18RO8, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EI6, P19EI7, P19EI8, P19EL, P19ER, P19EO, P19RI, P19RL
-, P19RR, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P19RO6, P19RO7, P19RO8, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EI6
-, P20EI7, P20EI8, P20EL, P20ER, P20EO, P20RI, P20RL, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P20RO6, P20RO7, P20RO8, P21CI1, P21CL, P21CR, P21CO, P21CTI
-, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EI6, P21EI7, P21EI8, P21EL, P21ER, P21EO, P21RI, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P21RO6
-, P21RO7, P21RO8, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EI6, P22EI7, P22EI8, P22EL, P22ER, P22EO, P22RI, P22RL
-, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P22RO6, P22RO7, P22RO8, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EI6
-, P23EI7, P23EI8, P23EL, P23ER, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P23RO6, P23RO7, P23RO8, P24CI1, P24CL, P24CR, P24CO, P24CTI
-, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5, P24EI6, P24EI7, P24EI8, P24EL, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P24RO6
-, P24RO7, P24RO8, P25CI1, P25CL, P25CR, P25CO, P25CTI, P25CTO, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5, P25EI6, P25EI7, P25EI8, P25EL, P25ER, P25EO, P25RI, P25RL
-, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P25RO6, P25RO7, P25RO8, P26CI1, P26CL, P26CR, P26CO, P26CTI, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4, P26EI5, P26EI6
-, P26EI7, P26EI8, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P26RO6, P26RO7, P26RO8, P27CI1, P27CL, P27CR, P27CO, P27CTI
-, P27CTO, P27EI1, P27EI2, P27EI3, P27EI4, P27EI5, P27EI6, P27EI7, P27EI8, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P27RO6
-, P27RO7, P27RO8, P28CI1, P28CL, P28CR, P28CO, P28CTI, P28CTO, P28EI1, P28EI2, P28EI3, P28EI4, P28EI5, P28EI6, P28EI7, P28EI8, P28EL, P28ER, P28EO, P28RI, P28RL
-, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P28RO6, P28RO7, P28RO8, P29CI1, P29CL, P29CR, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EI6
-, P29EI7, P29EI8, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P29RO6, P29RO7, P29RO8, P30CI1, P30CL, P30CR, P30CO, P30CTI
-, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EI6, P30EI7, P30EI8, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5, P30RO6
-, P30RO7, P30RO8, P31CI1, P31CL, P31CR, P31CO, P31CTI, P31CTO, P31EI1, P31EI2, P31EI3, P31EI4, P31EI5, P31EI6, P31EI7, P31EI8, P31EL, P31ER, P31EO, P31RI, P31RL
-, P31RR, P31RO1, P31RO2, P31RO3, P31RO4, P31RO5, P31RO6, P31RO7, P31RO8, P32CI1, P32CL, P32CR, P32CO, P32CTI, P32CTO, P32EI1, P32EI2, P32EI3, P32EI4, P32EI5, P32EI6
-, P32EI7, P32EI8, P32EL, P32ER, P32EO, P32RI, P32RL, P32RR, P32RO1, P32RO2, P32RO3, P32RO4, P32RO5, P32RO6, P32RO7, P32RO8, P33CI1, P33CL, P33CR, P33CO, P33CTI
-, P33CTO, P33EI1, P33EI2, P33EI3, P33EI4, P33EI5, P33EI6, P33EI7, P33EI8, P33EL, P33ER, P33EO, P33RI, P33RL, P33RR, P33RO1, P33RO2, P33RO3, P33RO4, P33RO5, P33RO6
-, P33RO7, P33RO8, P34CI1, P34CL, P34CR, P34CO, P34CTI, P34CTO, P34EI1, P34EI2, P34EI3, P34EI4, P34EI5, P34EI6, P34EI7, P34EI8, P34EL, P34ER, P34EO, P34RI, P34RL
-, P34RR, P34RO1, P34RO2, P34RO3, P34RO4, P34RO5, P34RO6, P34RO7, P34RO8);
-    output AL1D;
-    output AL1T;
-    output AL2D;
-    output AL2T;
-    output AL3D;
-    output AL3T;
-    input ALCK1;
-    input ALCK2;
-    input ALCK3;
-    input CA1D1;
-    input CA1D2;
-    input CA1D3;
-    input CA1D4;
-    input CA1D5;
-    input CA1D6;
-    input CA1N1;
-    input CA1N2;
-    input CA1N3;
-    input CA1N4;
-    input CA1P1;
-    input CA1P2;
-    input CA1P3;
-    input CA1P4;
-    input CA1T1;
-    input CA1T2;
-    input CA1T3;
-    input CA1T4;
-    input CA2D1;
-    input CA2D2;
-    input CA2D3;
-    input CA2D4;
-    input CA2D5;
-    input CA2D6;
-    input CA2N1;
-    input CA2N2;
-    input CA2N3;
-    input CA2N4;
-    input CA2P1;
-    input CA2P2;
-    input CA2P3;
-    input CA2P4;
-    input CA2T1;
-    input CA2T2;
-    input CA2T3;
-    input CA2T4;
-    input CCK;
-    output CKO1;
-    output CKO2;
-    output DCL;
-    input DCRN;
-    input DQ1CI1;
-    input DQ1CI2;
-    input DQ1CI3;
-    input DQ1CI4;
-    input DQ1CI5;
-    input DQ1CI6;
-    input DQ1CI7;
-    input DQ1CI8;
-    input DQ2CI1;
-    input DQ2CI2;
-    input DQ2CI3;
-    input DQ2CI4;
-    input DQ2CI5;
-    input DQ2CI6;
-    input DQ2CI7;
-    input DQ2CI8;
-    input DQ3CI1;
-    input DQ3CI2;
-    input DQ3CI3;
-    input DQ3CI4;
-    input DQ3CI5;
-    input DQ3CI6;
-    input DQ3CI7;
-    input DQ3CI8;
-    input DQS1CI1;
-    input DQS1CI2;
-    input DQS1CI3;
-    input DQS1CI4;
-    input DQS1CI5;
-    input DQS1CI6;
-    input DQS1CI7;
-    input DQS1CI8;
-    input DQS2CI1;
-    input DQS2CI2;
-    input DQS2CI3;
-    input DQS2CI4;
-    input DQS2CI5;
-    input DQS2CI6;
-    input DQS2CI7;
-    input DQS2CI8;
-    input DQS3CI1;
-    input DQS3CI2;
-    input DQS3CI3;
-    input DQS3CI4;
-    input DQS3CI5;
-    input DQS3CI6;
-    input DQS3CI7;
-    input DQS3CI8;
-    input DRA1;
-    input DRA2;
-    input DRA3;
-    input DRA4;
-    input DRCCSN;
-    input DRDPA1CSN;
-    input DRDPA2CSN;
-    input DRDPA3CSN;
-    input DRE;
-    input DRI1;
-    input DRI1CSN;
-    input DRI2;
-    input DRI2CSN;
-    input DRI3;
-    input DRI3CSN;
-    input DRI4;
-    input DRI5;
-    input DRI6;
-    output DRO1;
-    input DRO1CSN;
-    output DRO2;
-    input DRO2CSN;
-    output DRO3;
-    input DRO3CSN;
-    output DRO4;
-    output DRO5;
-    output DRO6;
-    input DRWDS;
-    input DRWEN;
-    input FA1;
-    input FA2;
-    input FA3;
-    input FA4;
-    input FA5;
-    input FA6;
-    input FCK1;
-    input FCK2;
-    input FDCK;
-    output FLD;
-    output FLG;
-    input FZ;
-    input LD1RN;
-    input LD2RN;
-    input LD3RN;
-    input LDSCK1;
-    input LDSCK2;
-    input LDSCK3;
-    input LE;
-    input P10CI1;
-    input P10CL;
-    output P10CO;
-    input P10CR;
-    input P10CTI;
-    output P10CTO;
-    input P10EI1;
-    input P10EI2;
-    input P10EI3;
-    input P10EI4;
-    input P10EI5;
-    input P10EI6;
-    input P10EI7;
-    input P10EI8;
-    input P10EL;
-    output P10EO;
-    input P10ER;
-    input P10RI;
-    input P10RL;
-    output P10RO1;
-    output P10RO2;
-    output P10RO3;
-    output P10RO4;
-    output P10RO5;
-    output P10RO6;
-    output P10RO7;
-    output P10RO8;
-    input P10RR;
-    input P11CI1;
-    input P11CL;
-    output P11CO;
-    input P11CR;
-    input P11CTI;
-    output P11CTO;
-    input P11EI1;
-    input P11EI2;
-    input P11EI3;
-    input P11EI4;
-    input P11EI5;
-    input P11EI6;
-    input P11EI7;
-    input P11EI8;
-    input P11EL;
-    output P11EO;
-    input P11ER;
-    input P11RI;
-    input P11RL;
-    output P11RO1;
-    output P11RO2;
-    output P11RO3;
-    output P11RO4;
-    output P11RO5;
-    output P11RO6;
-    output P11RO7;
-    output P11RO8;
-    input P11RR;
-    input P12CI1;
-    input P12CL;
-    output P12CO;
-    input P12CR;
-    input P12CTI;
-    output P12CTO;
-    input P12EI1;
-    input P12EI2;
-    input P12EI3;
-    input P12EI4;
-    input P12EI5;
-    input P12EI6;
-    input P12EI7;
-    input P12EI8;
-    input P12EL;
-    output P12EO;
-    input P12ER;
-    input P12RI;
-    input P12RL;
-    output P12RO1;
-    output P12RO2;
-    output P12RO3;
-    output P12RO4;
-    output P12RO5;
-    output P12RO6;
-    output P12RO7;
-    output P12RO8;
-    input P12RR;
-    input P13CI1;
-    input P13CL;
-    output P13CO;
-    input P13CR;
-    input P13CTI;
-    output P13CTO;
-    input P13EI1;
-    input P13EI2;
-    input P13EI3;
-    input P13EI4;
-    input P13EI5;
-    input P13EI6;
-    input P13EI7;
-    input P13EI8;
-    input P13EL;
-    output P13EO;
-    input P13ER;
-    input P13RI;
-    input P13RL;
-    output P13RO1;
-    output P13RO2;
-    output P13RO3;
-    output P13RO4;
-    output P13RO5;
-    output P13RO6;
-    output P13RO7;
-    output P13RO8;
-    input P13RR;
-    input P14CI1;
-    input P14CL;
-    output P14CO;
-    input P14CR;
-    input P14CTI;
-    output P14CTO;
-    input P14EI1;
-    input P14EI2;
-    input P14EI3;
-    input P14EI4;
-    input P14EI5;
-    input P14EI6;
-    input P14EI7;
-    input P14EI8;
-    input P14EL;
-    output P14EO;
-    input P14ER;
-    input P14RI;
-    input P14RL;
-    output P14RO1;
-    output P14RO2;
-    output P14RO3;
-    output P14RO4;
-    output P14RO5;
-    output P14RO6;
-    output P14RO7;
-    output P14RO8;
-    input P14RR;
-    input P15CI1;
-    input P15CL;
-    output P15CO;
-    input P15CR;
-    input P15CTI;
-    output P15CTO;
-    input P15EI1;
-    input P15EI2;
-    input P15EI3;
-    input P15EI4;
-    input P15EI5;
-    input P15EI6;
-    input P15EI7;
-    input P15EI8;
-    input P15EL;
-    output P15EO;
-    input P15ER;
-    input P15RI;
-    input P15RL;
-    output P15RO1;
-    output P15RO2;
-    output P15RO3;
-    output P15RO4;
-    output P15RO5;
-    output P15RO6;
-    output P15RO7;
-    output P15RO8;
-    input P15RR;
-    input P16CI1;
-    input P16CL;
-    output P16CO;
-    input P16CR;
-    input P16CTI;
-    output P16CTO;
-    input P16EI1;
-    input P16EI2;
-    input P16EI3;
-    input P16EI4;
-    input P16EI5;
-    input P16EI6;
-    input P16EI7;
-    input P16EI8;
-    input P16EL;
-    output P16EO;
-    input P16ER;
-    input P16RI;
-    input P16RL;
-    output P16RO1;
-    output P16RO2;
-    output P16RO3;
-    output P16RO4;
-    output P16RO5;
-    output P16RO6;
-    output P16RO7;
-    output P16RO8;
-    input P16RR;
-    input P17CI1;
-    input P17CL;
-    output P17CO;
-    input P17CR;
-    input P17CTI;
-    output P17CTO;
-    input P17EI1;
-    input P17EI2;
-    input P17EI3;
-    input P17EI4;
-    input P17EI5;
-    input P17EI6;
-    input P17EI7;
-    input P17EI8;
-    input P17EL;
-    output P17EO;
-    input P17ER;
-    input P17RI;
-    input P17RL;
-    output P17RO1;
-    output P17RO2;
-    output P17RO3;
-    output P17RO4;
-    output P17RO5;
-    output P17RO6;
-    output P17RO7;
-    output P17RO8;
-    input P17RR;
-    input P18CI1;
-    input P18CL;
-    output P18CO;
-    input P18CR;
-    input P18CTI;
-    output P18CTO;
-    input P18EI1;
-    input P18EI2;
-    input P18EI3;
-    input P18EI4;
-    input P18EI5;
-    input P18EI6;
-    input P18EI7;
-    input P18EI8;
-    input P18EL;
-    output P18EO;
-    input P18ER;
-    input P18RI;
-    input P18RL;
-    output P18RO1;
-    output P18RO2;
-    output P18RO3;
-    output P18RO4;
-    output P18RO5;
-    output P18RO6;
-    output P18RO7;
-    output P18RO8;
-    input P18RR;
-    input P19CI1;
-    input P19CL;
-    output P19CO;
-    input P19CR;
-    input P19CTI;
-    output P19CTO;
-    input P19EI1;
-    input P19EI2;
-    input P19EI3;
-    input P19EI4;
-    input P19EI5;
-    input P19EI6;
-    input P19EI7;
-    input P19EI8;
-    input P19EL;
-    output P19EO;
-    input P19ER;
-    input P19RI;
-    input P19RL;
-    output P19RO1;
-    output P19RO2;
-    output P19RO3;
-    output P19RO4;
-    output P19RO5;
-    output P19RO6;
-    output P19RO7;
-    output P19RO8;
-    input P19RR;
-    input P1CI1;
-    input P1CL;
-    output P1CO;
-    input P1CR;
-    input P1CTI;
-    output P1CTO;
-    input P1EI1;
-    input P1EI2;
-    input P1EI3;
-    input P1EI4;
-    input P1EI5;
-    input P1EI6;
-    input P1EI7;
-    input P1EI8;
-    input P1EL;
-    output P1EO;
-    input P1ER;
-    input P1RI;
-    input P1RL;
-    output P1RO1;
-    output P1RO2;
-    output P1RO3;
-    output P1RO4;
-    output P1RO5;
-    output P1RO6;
-    output P1RO7;
-    output P1RO8;
-    input P1RR;
-    input P20CI1;
-    input P20CL;
-    output P20CO;
-    input P20CR;
-    input P20CTI;
-    output P20CTO;
-    input P20EI1;
-    input P20EI2;
-    input P20EI3;
-    input P20EI4;
-    input P20EI5;
-    input P20EI6;
-    input P20EI7;
-    input P20EI8;
-    input P20EL;
-    output P20EO;
-    input P20ER;
-    input P20RI;
-    input P20RL;
-    output P20RO1;
-    output P20RO2;
-    output P20RO3;
-    output P20RO4;
-    output P20RO5;
-    output P20RO6;
-    output P20RO7;
-    output P20RO8;
-    input P20RR;
-    input P21CI1;
-    input P21CL;
-    output P21CO;
-    input P21CR;
-    input P21CTI;
-    output P21CTO;
-    input P21EI1;
-    input P21EI2;
-    input P21EI3;
-    input P21EI4;
-    input P21EI5;
-    input P21EI6;
-    input P21EI7;
-    input P21EI8;
-    input P21EL;
-    output P21EO;
-    input P21ER;
-    input P21RI;
-    input P21RL;
-    output P21RO1;
-    output P21RO2;
-    output P21RO3;
-    output P21RO4;
-    output P21RO5;
-    output P21RO6;
-    output P21RO7;
-    output P21RO8;
-    input P21RR;
-    input P22CI1;
-    input P22CL;
-    output P22CO;
-    input P22CR;
-    input P22CTI;
-    output P22CTO;
-    input P22EI1;
-    input P22EI2;
-    input P22EI3;
-    input P22EI4;
-    input P22EI5;
-    input P22EI6;
-    input P22EI7;
-    input P22EI8;
-    input P22EL;
-    output P22EO;
-    input P22ER;
-    input P22RI;
-    input P22RL;
-    output P22RO1;
-    output P22RO2;
-    output P22RO3;
-    output P22RO4;
-    output P22RO5;
-    output P22RO6;
-    output P22RO7;
-    output P22RO8;
-    input P22RR;
-    input P23CI1;
-    input P23CL;
-    output P23CO;
-    input P23CR;
-    input P23CTI;
-    output P23CTO;
-    input P23EI1;
-    input P23EI2;
-    input P23EI3;
-    input P23EI4;
-    input P23EI5;
-    input P23EI6;
-    input P23EI7;
-    input P23EI8;
-    input P23EL;
-    output P23EO;
-    input P23ER;
-    input P23RI;
-    input P23RL;
-    output P23RO1;
-    output P23RO2;
-    output P23RO3;
-    output P23RO4;
-    output P23RO5;
-    output P23RO6;
-    output P23RO7;
-    output P23RO8;
-    input P23RR;
-    input P24CI1;
-    input P24CL;
-    output P24CO;
-    input P24CR;
-    input P24CTI;
-    output P24CTO;
-    input P24EI1;
-    input P24EI2;
-    input P24EI3;
-    input P24EI4;
-    input P24EI5;
-    input P24EI6;
-    input P24EI7;
-    input P24EI8;
-    input P24EL;
-    output P24EO;
-    input P24ER;
-    input P24RI;
-    input P24RL;
-    output P24RO1;
-    output P24RO2;
-    output P24RO3;
-    output P24RO4;
-    output P24RO5;
-    output P24RO6;
-    output P24RO7;
-    output P24RO8;
-    input P24RR;
-    input P25CI1;
-    input P25CL;
-    output P25CO;
-    input P25CR;
-    input P25CTI;
-    output P25CTO;
-    input P25EI1;
-    input P25EI2;
-    input P25EI3;
-    input P25EI4;
-    input P25EI5;
-    input P25EI6;
-    input P25EI7;
-    input P25EI8;
-    input P25EL;
-    output P25EO;
-    input P25ER;
-    input P25RI;
-    input P25RL;
-    output P25RO1;
-    output P25RO2;
-    output P25RO3;
-    output P25RO4;
-    output P25RO5;
-    output P25RO6;
-    output P25RO7;
-    output P25RO8;
-    input P25RR;
-    input P26CI1;
-    input P26CL;
-    output P26CO;
-    input P26CR;
-    input P26CTI;
-    output P26CTO;
-    input P26EI1;
-    input P26EI2;
-    input P26EI3;
-    input P26EI4;
-    input P26EI5;
-    input P26EI6;
-    input P26EI7;
-    input P26EI8;
-    input P26EL;
-    output P26EO;
-    input P26ER;
-    input P26RI;
-    input P26RL;
-    output P26RO1;
-    output P26RO2;
-    output P26RO3;
-    output P26RO4;
-    output P26RO5;
-    output P26RO6;
-    output P26RO7;
-    output P26RO8;
-    input P26RR;
-    input P27CI1;
-    input P27CL;
-    output P27CO;
-    input P27CR;
-    input P27CTI;
-    output P27CTO;
-    input P27EI1;
-    input P27EI2;
-    input P27EI3;
-    input P27EI4;
-    input P27EI5;
-    input P27EI6;
-    input P27EI7;
-    input P27EI8;
-    input P27EL;
-    output P27EO;
-    input P27ER;
-    input P27RI;
-    input P27RL;
-    output P27RO1;
-    output P27RO2;
-    output P27RO3;
-    output P27RO4;
-    output P27RO5;
-    output P27RO6;
-    output P27RO7;
-    output P27RO8;
-    input P27RR;
-    input P28CI1;
-    input P28CL;
-    output P28CO;
-    input P28CR;
-    input P28CTI;
-    output P28CTO;
-    input P28EI1;
-    input P28EI2;
-    input P28EI3;
-    input P28EI4;
-    input P28EI5;
-    input P28EI6;
-    input P28EI7;
-    input P28EI8;
-    input P28EL;
-    output P28EO;
-    input P28ER;
-    input P28RI;
-    input P28RL;
-    output P28RO1;
-    output P28RO2;
-    output P28RO3;
-    output P28RO4;
-    output P28RO5;
-    output P28RO6;
-    output P28RO7;
-    output P28RO8;
-    input P28RR;
-    input P29CI1;
-    input P29CL;
-    output P29CO;
-    input P29CR;
-    input P29CTI;
-    output P29CTO;
-    input P29EI1;
-    input P29EI2;
-    input P29EI3;
-    input P29EI4;
-    input P29EI5;
-    input P29EI6;
-    input P29EI7;
-    input P29EI8;
-    input P29EL;
-    output P29EO;
-    input P29ER;
-    input P29RI;
-    input P29RL;
-    output P29RO1;
-    output P29RO2;
-    output P29RO3;
-    output P29RO4;
-    output P29RO5;
-    output P29RO6;
-    output P29RO7;
-    output P29RO8;
-    input P29RR;
-    input P2CI1;
-    input P2CL;
-    output P2CO;
-    input P2CR;
-    input P2CTI;
-    output P2CTO;
-    input P2EI1;
-    input P2EI2;
-    input P2EI3;
-    input P2EI4;
-    input P2EI5;
-    input P2EI6;
-    input P2EI7;
-    input P2EI8;
-    input P2EL;
-    output P2EO;
-    input P2ER;
-    input P2RI;
-    input P2RL;
-    output P2RO1;
-    output P2RO2;
-    output P2RO3;
-    output P2RO4;
-    output P2RO5;
-    output P2RO6;
-    output P2RO7;
-    output P2RO8;
-    input P2RR;
-    input P30CI1;
-    input P30CL;
-    output P30CO;
-    input P30CR;
-    input P30CTI;
-    output P30CTO;
-    input P30EI1;
-    input P30EI2;
-    input P30EI3;
-    input P30EI4;
-    input P30EI5;
-    input P30EI6;
-    input P30EI7;
-    input P30EI8;
-    input P30EL;
-    output P30EO;
-    input P30ER;
-    input P30RI;
-    input P30RL;
-    output P30RO1;
-    output P30RO2;
-    output P30RO3;
-    output P30RO4;
-    output P30RO5;
-    output P30RO6;
-    output P30RO7;
-    output P30RO8;
-    input P30RR;
-    input P31CI1;
-    input P31CL;
-    output P31CO;
-    input P31CR;
-    input P31CTI;
-    output P31CTO;
-    input P31EI1;
-    input P31EI2;
-    input P31EI3;
-    input P31EI4;
-    input P31EI5;
-    input P31EI6;
-    input P31EI7;
-    input P31EI8;
-    input P31EL;
-    output P31EO;
-    input P31ER;
-    input P31RI;
-    input P31RL;
-    output P31RO1;
-    output P31RO2;
-    output P31RO3;
-    output P31RO4;
-    output P31RO5;
-    output P31RO6;
-    output P31RO7;
-    output P31RO8;
-    input P31RR;
-    input P32CI1;
-    input P32CL;
-    output P32CO;
-    input P32CR;
-    input P32CTI;
-    output P32CTO;
-    input P32EI1;
-    input P32EI2;
-    input P32EI3;
-    input P32EI4;
-    input P32EI5;
-    input P32EI6;
-    input P32EI7;
-    input P32EI8;
-    input P32EL;
-    output P32EO;
-    input P32ER;
-    input P32RI;
-    input P32RL;
-    output P32RO1;
-    output P32RO2;
-    output P32RO3;
-    output P32RO4;
-    output P32RO5;
-    output P32RO6;
-    output P32RO7;
-    output P32RO8;
-    input P32RR;
-    input P33CI1;
-    input P33CL;
-    output P33CO;
-    input P33CR;
-    input P33CTI;
-    output P33CTO;
-    input P33EI1;
-    input P33EI2;
-    input P33EI3;
-    input P33EI4;
-    input P33EI5;
-    input P33EI6;
-    input P33EI7;
-    input P33EI8;
-    input P33EL;
-    output P33EO;
-    input P33ER;
-    input P33RI;
-    input P33RL;
-    output P33RO1;
-    output P33RO2;
-    output P33RO3;
-    output P33RO4;
-    output P33RO5;
-    output P33RO6;
-    output P33RO7;
-    output P33RO8;
-    input P33RR;
-    input P34CI1;
-    input P34CL;
-    output P34CO;
-    input P34CR;
-    input P34CTI;
-    output P34CTO;
-    input P34EI1;
-    input P34EI2;
-    input P34EI3;
-    input P34EI4;
-    input P34EI5;
-    input P34EI6;
-    input P34EI7;
-    input P34EI8;
-    input P34EL;
-    output P34EO;
-    input P34ER;
-    input P34RI;
-    input P34RL;
-    output P34RO1;
-    output P34RO2;
-    output P34RO3;
-    output P34RO4;
-    output P34RO5;
-    output P34RO6;
-    output P34RO7;
-    output P34RO8;
-    input P34RR;
-    input P3CI1;
-    input P3CL;
-    output P3CO;
-    input P3CR;
-    input P3CTI;
-    output P3CTO;
-    input P3EI1;
-    input P3EI2;
-    input P3EI3;
-    input P3EI4;
-    input P3EI5;
-    input P3EI6;
-    input P3EI7;
-    input P3EI8;
-    input P3EL;
-    output P3EO;
-    input P3ER;
-    input P3RI;
-    input P3RL;
-    output P3RO1;
-    output P3RO2;
-    output P3RO3;
-    output P3RO4;
-    output P3RO5;
-    output P3RO6;
-    output P3RO7;
-    output P3RO8;
-    input P3RR;
-    input P4CI1;
-    input P4CL;
-    output P4CO;
-    input P4CR;
-    input P4CTI;
-    output P4CTO;
-    input P4EI1;
-    input P4EI2;
-    input P4EI3;
-    input P4EI4;
-    input P4EI5;
-    input P4EI6;
-    input P4EI7;
-    input P4EI8;
-    input P4EL;
-    output P4EO;
-    input P4ER;
-    input P4RI;
-    input P4RL;
-    output P4RO1;
-    output P4RO2;
-    output P4RO3;
-    output P4RO4;
-    output P4RO5;
-    output P4RO6;
-    output P4RO7;
-    output P4RO8;
-    input P4RR;
-    input P5CI1;
-    input P5CL;
-    output P5CO;
-    input P5CR;
-    input P5CTI;
-    output P5CTO;
-    input P5EI1;
-    input P5EI2;
-    input P5EI3;
-    input P5EI4;
-    input P5EI5;
-    input P5EI6;
-    input P5EI7;
-    input P5EI8;
-    input P5EL;
-    output P5EO;
-    input P5ER;
-    input P5RI;
-    input P5RL;
-    output P5RO1;
-    output P5RO2;
-    output P5RO3;
-    output P5RO4;
-    output P5RO5;
-    output P5RO6;
-    output P5RO7;
-    output P5RO8;
-    input P5RR;
-    input P6CI1;
-    input P6CL;
-    output P6CO;
-    input P6CR;
-    input P6CTI;
-    output P6CTO;
-    input P6EI1;
-    input P6EI2;
-    input P6EI3;
-    input P6EI4;
-    input P6EI5;
-    input P6EI6;
-    input P6EI7;
-    input P6EI8;
-    input P6EL;
-    output P6EO;
-    input P6ER;
-    input P6RI;
-    input P6RL;
-    output P6RO1;
-    output P6RO2;
-    output P6RO3;
-    output P6RO4;
-    output P6RO5;
-    output P6RO6;
-    output P6RO7;
-    output P6RO8;
-    input P6RR;
-    input P7CI1;
-    input P7CL;
-    output P7CO;
-    input P7CR;
-    input P7CTI;
-    output P7CTO;
-    input P7EI1;
-    input P7EI2;
-    input P7EI3;
-    input P7EI4;
-    input P7EI5;
-    input P7EI6;
-    input P7EI7;
-    input P7EI8;
-    input P7EL;
-    output P7EO;
-    input P7ER;
-    input P7RI;
-    input P7RL;
-    output P7RO1;
-    output P7RO2;
-    output P7RO3;
-    output P7RO4;
-    output P7RO5;
-    output P7RO6;
-    output P7RO7;
-    output P7RO8;
-    input P7RR;
-    input P8CI1;
-    input P8CL;
-    output P8CO;
-    input P8CR;
-    input P8CTI;
-    output P8CTO;
-    input P8EI1;
-    input P8EI2;
-    input P8EI3;
-    input P8EI4;
-    input P8EI5;
-    input P8EI6;
-    input P8EI7;
-    input P8EI8;
-    input P8EL;
-    output P8EO;
-    input P8ER;
-    input P8RI;
-    input P8RL;
-    output P8RO1;
-    output P8RO2;
-    output P8RO3;
-    output P8RO4;
-    output P8RO5;
-    output P8RO6;
-    output P8RO7;
-    output P8RO8;
-    input P8RR;
-    input P9CI1;
-    input P9CL;
-    output P9CO;
-    input P9CR;
-    input P9CTI;
-    output P9CTO;
-    input P9EI1;
-    input P9EI2;
-    input P9EI3;
-    input P9EI4;
-    input P9EI5;
-    input P9EI6;
-    input P9EI7;
-    input P9EI8;
-    input P9EL;
-    output P9EO;
-    input P9ER;
-    input P9RI;
-    input P9RL;
-    output P9RO1;
-    output P9RO2;
-    output P9RO3;
-    output P9RO4;
-    output P9RO5;
-    output P9RO6;
-    output P9RO7;
-    output P9RO8;
-    input P9RR;
-    input SE;
-    input SWRX1CK;
-    input SWRX2CK;
-    parameter cal_delay1 = "";
-    parameter cal_delay2 = "";
-    parameter div1 = 3'b000;
-    parameter div2 = 3'b000;
-    parameter div3 = 3'b000;
-    parameter div_swrx1 = 3'b000;
-    parameter div_swrx2 = 3'b000;
-    parameter inv_ld_sck1 = 1'b0;
-    parameter inv_ld_sck2 = 1'b0;
-    parameter inv_ld_sck3 = 1'b0;
-    parameter link_ld_12 = 1'b0;
-    parameter link_ld_23 = 1'b0;
-    parameter mode_side1 = 0;
-    parameter mode_side2 = 0;
-    parameter mode_side3 = 0;
-    parameter pads_dict = "";
-    parameter pads_path = "";
-    parameter sel_clk_out1 = 1'b0;
-    parameter sel_clk_out2 = 1'b0;
-    parameter sel_dc_clk = 2'b00;
-    parameter sel_ld_fck1 = 2'b00;
-    parameter sel_ld_fck2 = 2'b00;
-    parameter sel_ld_fck3 = 2'b00;
-    parameter sel_sw_fck1 = 2'b00;
-    parameter sel_sw_fck2 = 2'b00;
-    parameter use_dc = 1'b0;
-endmodule
-
 //(* blackbox *)
 //module NX_LUT(I1, I2, I3, I4, O);
 //    input I1;
@@ -5846,377 +2254,6 @@ endmodule
 //    parameter lut_table = 16'b0000000000000000;
 //endmodule
 
-(* blackbox *)
-module NX_PMA_L(CLK_USER_I, CLK_REF_I, PRE_SG_I, PRE_EN_I, PRE_IS_I1, PRE_IS_I2, PRE_IS_I3, PRE_IS_I4, MAIN_SG_I, MAIN_EN_I1, MAIN_EN_I2, MAIN_EN_I3, MAIN_EN_I4, MAIN_EN_I5, MAIN_EN_I6, MARG_S_I1, MARG_S_I2, MARG_S_I3, MARG_S_I4, MARG_IS_I1, MARG_IS_I2
-, MARG_IS_I3, MARG_IS_I4, MARG_SV_I1, MARG_SV_I2, MARG_SV_I3, MARG_SV_I4, MARG_SV_I5, MARG_ISV_I1, MARG_ISV_I2, MARG_ISV_I3, MARG_ISV_I4, MARG_ISV_I5, POST_EN_I1, POST_EN_I2, POST_EN_I3, POST_EN_I4, POST_EN_I5, POST_SG_I, POST_IS_I1, POST_IS_I2, POST_IS_I3
-, POST_IS_I4, POST_ISV_I1, POST_ISV_I2, POST_ISV_I3, POST_ISV_I4, TX_SEL_I1, TX_SEL_I2, TX_SEL_I3, TX_SEL_I4, TX_SEL_I5, TX_SEL_I6, CT_CAP_I1, CT_CAP_I2, CT_CAP_I3, CT_CAP_I4, CT_RESP_I1, CT_RESP_I2, CT_RESP_I3, CT_RESP_I4, CT_RESN_I1, CT_RESN_I2
-, CT_RESN_I3, CT_RESN_I4, M_EYE_I, RX_SEL_I1, RX_SEL_I2, RX_SEL_I3, RX_SEL_I4, RX_SEL_I5, RX_SEL_I6, PLL_RN_I, RST_N_I, CAL_1P_I1, CAL_1P_I2, CAL_1P_I3, CAL_1P_I4, CAL_1P_I5, CAL_1P_I6, CAL_1P_I7, CAL_1P_I8, CAL_2N_I1, CAL_2N_I2
-, CAL_2N_I3, CAL_2N_I4, CAL_2N_I5, CAL_2N_I6, CAL_2N_I7, CAL_2N_I8, CAL_3N_I1, CAL_3N_I2, CAL_3N_I3, CAL_3N_I4, CAL_3N_I5, CAL_3N_I6, CAL_3N_I7, CAL_3N_I8, CAL_4P_I1, CAL_4P_I2, CAL_4P_I3, CAL_4P_I4, CAL_4P_I5, CAL_4P_I6, CAL_4P_I7
-, CAL_4P_I8, CAL_SEL_I1, CAL_SEL_I2, CAL_SEL_I3, CAL_SEL_I4, CAL_E_I, LOCK_E_I, OVS_E_I, TST_I1, TST_I2, TST_I3, TST_I4, TST_I5, TST_I6, TST_I7, TST_I8, CLK_O, LOCK_O, CAL_O, TST_O1, TST_O2
-, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, CLK_EXT_I, LINK_TX1, LINK_TX2, LINK_TX3, LINK_TX4, LINK_TX5, LINK_RX0, LINK_RX1, LINK_RX2, LINK_RX3, LINK_RX4, LINK_RX5, LINK_TX0);
-    input CAL_1P_I1;
-    input CAL_1P_I2;
-    input CAL_1P_I3;
-    input CAL_1P_I4;
-    input CAL_1P_I5;
-    input CAL_1P_I6;
-    input CAL_1P_I7;
-    input CAL_1P_I8;
-    input CAL_2N_I1;
-    input CAL_2N_I2;
-    input CAL_2N_I3;
-    input CAL_2N_I4;
-    input CAL_2N_I5;
-    input CAL_2N_I6;
-    input CAL_2N_I7;
-    input CAL_2N_I8;
-    input CAL_3N_I1;
-    input CAL_3N_I2;
-    input CAL_3N_I3;
-    input CAL_3N_I4;
-    input CAL_3N_I5;
-    input CAL_3N_I6;
-    input CAL_3N_I7;
-    input CAL_3N_I8;
-    input CAL_4P_I1;
-    input CAL_4P_I2;
-    input CAL_4P_I3;
-    input CAL_4P_I4;
-    input CAL_4P_I5;
-    input CAL_4P_I6;
-    input CAL_4P_I7;
-    input CAL_4P_I8;
-    input CAL_E_I;
-    output CAL_O;
-    input CAL_SEL_I1;
-    input CAL_SEL_I2;
-    input CAL_SEL_I3;
-    input CAL_SEL_I4;
-    input CLK_EXT_I;
-    output CLK_O;
-    input CLK_REF_I;
-    input CLK_USER_I;
-    input CT_CAP_I1;
-    input CT_CAP_I2;
-    input CT_CAP_I3;
-    input CT_CAP_I4;
-    input CT_RESN_I1;
-    input CT_RESN_I2;
-    input CT_RESN_I3;
-    input CT_RESN_I4;
-    input CT_RESP_I1;
-    input CT_RESP_I2;
-    input CT_RESP_I3;
-    input CT_RESP_I4;
-    inout [9:0] LINK_RX0;
-    inout [9:0] LINK_RX1;
-    inout [9:0] LINK_RX2;
-    inout [9:0] LINK_RX3;
-    inout [9:0] LINK_RX4;
-    inout [9:0] LINK_RX5;
-    inout [19:0] LINK_TX0;
-    inout [19:0] LINK_TX1;
-    inout [19:0] LINK_TX2;
-    inout [19:0] LINK_TX3;
-    inout [19:0] LINK_TX4;
-    inout [19:0] LINK_TX5;
-    input LOCK_E_I;
-    output LOCK_O;
-    input MAIN_EN_I1;
-    input MAIN_EN_I2;
-    input MAIN_EN_I3;
-    input MAIN_EN_I4;
-    input MAIN_EN_I5;
-    input MAIN_EN_I6;
-    input MAIN_SG_I;
-    input MARG_ISV_I1;
-    input MARG_ISV_I2;
-    input MARG_ISV_I3;
-    input MARG_ISV_I4;
-    input MARG_ISV_I5;
-    input MARG_IS_I1;
-    input MARG_IS_I2;
-    input MARG_IS_I3;
-    input MARG_IS_I4;
-    input MARG_SV_I1;
-    input MARG_SV_I2;
-    input MARG_SV_I3;
-    input MARG_SV_I4;
-    input MARG_SV_I5;
-    input MARG_S_I1;
-    input MARG_S_I2;
-    input MARG_S_I3;
-    input MARG_S_I4;
-    input M_EYE_I;
-    input OVS_E_I;
-    input PLL_RN_I;
-    input POST_EN_I1;
-    input POST_EN_I2;
-    input POST_EN_I3;
-    input POST_EN_I4;
-    input POST_EN_I5;
-    input POST_ISV_I1;
-    input POST_ISV_I2;
-    input POST_ISV_I3;
-    input POST_ISV_I4;
-    input POST_IS_I1;
-    input POST_IS_I2;
-    input POST_IS_I3;
-    input POST_IS_I4;
-    input POST_SG_I;
-    input PRE_EN_I;
-    input PRE_IS_I1;
-    input PRE_IS_I2;
-    input PRE_IS_I3;
-    input PRE_IS_I4;
-    input PRE_SG_I;
-    input RST_N_I;
-    input RX_SEL_I1;
-    input RX_SEL_I2;
-    input RX_SEL_I3;
-    input RX_SEL_I4;
-    input RX_SEL_I5;
-    input RX_SEL_I6;
-    input TST_I1;
-    input TST_I2;
-    input TST_I3;
-    input TST_I4;
-    input TST_I5;
-    input TST_I6;
-    input TST_I7;
-    input TST_I8;
-    output TST_O1;
-    output TST_O2;
-    output TST_O3;
-    output TST_O4;
-    output TST_O5;
-    output TST_O6;
-    output TST_O7;
-    output TST_O8;
-    input TX_SEL_I1;
-    input TX_SEL_I2;
-    input TX_SEL_I3;
-    input TX_SEL_I4;
-    input TX_SEL_I5;
-    input TX_SEL_I6;
-    parameter location = "";
-    parameter main_clk_to_fabric_div_en = 1'b0;
-    parameter main_clk_to_fabric_div_mode = 1'b0;
-    parameter main_clk_to_fabric_sel = 1'b0;
-    parameter main_test = 8'b00000000;
-    parameter main_use_only_usr_clock = 1'b0;
-    parameter main_use_pcs_clk_2 = 1'b0;
-    parameter pcs_ovs_mode = 1'b0;
-    parameter pcs_pll_lock_count = 3'b000;
-    parameter pcs_word_len = 2'b00;
-    parameter pll_pma_cpump_n = 3'b000;
-    parameter pll_pma_divf = 2'b00;
-    parameter pll_pma_divf_en_n = 1'b0;
-    parameter pll_pma_divm = 2'b00;
-    parameter pll_pma_divm_en_n = 1'b0;
-    parameter pll_pma_divn = 1'b0;
-    parameter pll_pma_divn_en_n = 1'b0;
-    parameter pll_pma_int_data_len = 1'b0;
-    parameter pll_pma_lvds_mux = 1'b0;
-    parameter pll_pma_mux_ckref = 1'b0;
-    parameter rx_pma_half_step = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_PMA_U(CLK_TX_I, CLK_RX_I, CLK_REF_I, DC_E_I, DC_LCSN_I1, DC_LCSN_I2, DC_LCSN_I3, DC_LCSN_I4, DC_CCSN_I, DC_WE_N_I, DC_ADD_I1, DC_ADD_I2, DC_ADD_I3, DC_ADD_I4, DC_WDATAS_I, DC_WDATA_I1, DC_WDATA_I2, DC_WDATA_I3, DC_WDATA_I4, DC_WDATA_I5, DC_WDATA_I6
-, DC_WDATA_I7, DC_WDATA_I8, DC_WDATA_I9, DC_WDATA_I10, DC_WDATA_I11, DC_WDATA_I12, PLL_RN_I, PWDN_N_I, RST_N_I, DBG_S_I1, DBG_S_I2, DBG_A_I, SE_I, SCAN_I1, SCAN_I2, SCAN_I3, SCAN_I4, SCAN_I5, SCAN_I6, SCAN_I7, SCAN_I8
-, CLK_O, CLK_RX_O, LOCK_O, LOCKA_O, FB_LOCK_O, CAL_OUT_O, DBG_R_O, LL_O1, LL_O2, LL_O3, LL_O4, LL_O5, LL_O6, LL_O7, LL_O8, LL_O9, LL_O10, LL_O11, LL_O12, LL_O13, LL_O14
-, LL_O15, LL_O16, LL_O17, LL_O18, LL_O19, LL_O20, SCAN_O1, SCAN_O2, SCAN_O3, SCAN_O4, SCAN_O5, SCAN_O6, SCAN_O7, SCAN_O8, LINK_TX1, LINK_TX2, LINK_TX3, LINK_RX0, LINK_RX1, LINK_RX2, LINK_RX3
-, LINK_TX0);
-    output CAL_OUT_O;
-    output CLK_O;
-    input CLK_REF_I;
-    input CLK_RX_I;
-    output CLK_RX_O;
-    input CLK_TX_I;
-    input DBG_A_I;
-    output DBG_R_O;
-    input DBG_S_I1;
-    input DBG_S_I2;
-    input DC_ADD_I1;
-    input DC_ADD_I2;
-    input DC_ADD_I3;
-    input DC_ADD_I4;
-    input DC_CCSN_I;
-    input DC_E_I;
-    input DC_LCSN_I1;
-    input DC_LCSN_I2;
-    input DC_LCSN_I3;
-    input DC_LCSN_I4;
-    input DC_WDATAS_I;
-    input DC_WDATA_I1;
-    input DC_WDATA_I10;
-    input DC_WDATA_I11;
-    input DC_WDATA_I12;
-    input DC_WDATA_I2;
-    input DC_WDATA_I3;
-    input DC_WDATA_I4;
-    input DC_WDATA_I5;
-    input DC_WDATA_I6;
-    input DC_WDATA_I7;
-    input DC_WDATA_I8;
-    input DC_WDATA_I9;
-    input DC_WE_N_I;
-    output FB_LOCK_O;
-    inout [9:0] LINK_RX0;
-    inout [9:0] LINK_RX1;
-    inout [9:0] LINK_RX2;
-    inout [9:0] LINK_RX3;
-    inout [19:0] LINK_TX0;
-    inout [19:0] LINK_TX1;
-    inout [19:0] LINK_TX2;
-    inout [19:0] LINK_TX3;
-    output LL_O1;
-    output LL_O10;
-    output LL_O11;
-    output LL_O12;
-    output LL_O13;
-    output LL_O14;
-    output LL_O15;
-    output LL_O16;
-    output LL_O17;
-    output LL_O18;
-    output LL_O19;
-    output LL_O2;
-    output LL_O20;
-    output LL_O3;
-    output LL_O4;
-    output LL_O5;
-    output LL_O6;
-    output LL_O7;
-    output LL_O8;
-    output LL_O9;
-    output LOCKA_O;
-    output LOCK_O;
-    input PLL_RN_I;
-    input PWDN_N_I;
-    input RST_N_I;
-    input SCAN_I1;
-    input SCAN_I2;
-    input SCAN_I3;
-    input SCAN_I4;
-    input SCAN_I5;
-    input SCAN_I6;
-    input SCAN_I7;
-    input SCAN_I8;
-    output SCAN_O1;
-    output SCAN_O2;
-    output SCAN_O3;
-    output SCAN_O4;
-    output SCAN_O5;
-    output SCAN_O6;
-    output SCAN_O7;
-    output SCAN_O8;
-    input SE_I;
-    parameter dyn_all_rx_pma_m_eye = 1'b0;
-    parameter dyn_all_rx_pma_m_eye_coarse_ena = 1'b0;
-    parameter dyn_all_rx_pma_m_eye_dn = 1'b0;
-    parameter dyn_all_rx_pma_m_eye_fine_ena = 1'b0;
-    parameter dyn_all_rx_pma_m_eye_step = 4'b0000;
-    parameter dyn_all_rx_pma_m_eye_up = 1'b0;
-    parameter dyn_all_rx_pma_threshold_1 = 5'b00000;
-    parameter dyn_all_rx_pma_threshold_2 = 5'b00000;
-    parameter dyn_all_rx_pma_trim_locked = 3'b000;
-    parameter dyn_all_rx_pma_trim_mode = 2'b00;
-    parameter dyn_all_rx_pma_trim_unlocked = 3'b000;
-    parameter dyn_rx0_pma_ctle_cap_p = 4'b0000;
-    parameter dyn_rx0_pma_ctle_res_p = 4'b0000;
-    parameter dyn_rx0_pma_dfe_idac_tap1_n = 6'b000000;
-    parameter dyn_rx0_pma_dfe_idac_tap2_n = 6'b000000;
-    parameter dyn_rx0_pma_dfe_idac_tap3_n = 6'b000000;
-    parameter dyn_rx0_pma_dfe_idac_tap4_n = 6'b000000;
-    parameter dyn_rx0_pma_termination_cmd = 6'b000000;
-    parameter dyn_rx1_pma_ctle_cap_p = 4'b0000;
-    parameter dyn_rx1_pma_ctle_res_p = 4'b0000;
-    parameter dyn_rx1_pma_dfe_idac_tap1_n = 6'b000000;
-    parameter dyn_rx1_pma_dfe_idac_tap2_n = 6'b000000;
-    parameter dyn_rx1_pma_dfe_idac_tap3_n = 6'b000000;
-    parameter dyn_rx1_pma_dfe_idac_tap4_n = 6'b000000;
-    parameter dyn_rx1_pma_termination_cmd = 6'b000000;
-    parameter dyn_rx2_pma_ctle_cap_p = 4'b0000;
-    parameter dyn_rx2_pma_ctle_res_p = 4'b0000;
-    parameter dyn_rx2_pma_dfe_idac_tap1_n = 6'b000000;
-    parameter dyn_rx2_pma_dfe_idac_tap2_n = 6'b000000;
-    parameter dyn_rx2_pma_dfe_idac_tap3_n = 6'b000000;
-    parameter dyn_rx2_pma_dfe_idac_tap4_n = 6'b000000;
-    parameter dyn_rx2_pma_termination_cmd = 6'b000000;
-    parameter dyn_rx3_pma_ctle_cap_p = 4'b0000;
-    parameter dyn_rx3_pma_ctle_res_p = 4'b0000;
-    parameter dyn_rx3_pma_dfe_idac_tap1_n = 6'b000000;
-    parameter dyn_rx3_pma_dfe_idac_tap2_n = 6'b000000;
-    parameter dyn_rx3_pma_dfe_idac_tap3_n = 6'b000000;
-    parameter dyn_rx3_pma_dfe_idac_tap4_n = 6'b000000;
-    parameter dyn_rx3_pma_termination_cmd = 6'b000000;
-    parameter dyn_tx0_pma_main_en = 6'b000000;
-    parameter dyn_tx0_pma_main_sign = 1'b0;
-    parameter dyn_tx0_pma_margin_input = 9'b000000000;
-    parameter dyn_tx0_pma_margin_sel = 9'b000000000;
-    parameter dyn_tx0_pma_post_en = 5'b00000;
-    parameter dyn_tx0_pma_post_sel = 8'b00000000;
-    parameter dyn_tx0_pma_post_sign = 1'b0;
-    parameter dyn_tx0_pma_pre_en = 1'b0;
-    parameter dyn_tx0_pma_pre_sel = 4'b0000;
-    parameter dyn_tx0_pma_pre_sign = 1'b0;
-    parameter dyn_tx1_pma_main_en = 6'b000000;
-    parameter dyn_tx1_pma_main_sign = 1'b0;
-    parameter dyn_tx1_pma_margin_input = 9'b000000000;
-    parameter dyn_tx1_pma_margin_sel = 9'b000000000;
-    parameter dyn_tx1_pma_post_en = 5'b00000;
-    parameter dyn_tx1_pma_post_sel = 8'b00000000;
-    parameter dyn_tx1_pma_post_sign = 1'b0;
-    parameter dyn_tx1_pma_pre_en = 1'b0;
-    parameter dyn_tx1_pma_pre_sel = 4'b0000;
-    parameter dyn_tx1_pma_pre_sign = 1'b0;
-    parameter dyn_tx2_pma_main_en = 6'b000000;
-    parameter dyn_tx2_pma_main_sign = 1'b0;
-    parameter dyn_tx2_pma_margin_input = 9'b000000000;
-    parameter dyn_tx2_pma_margin_sel = 9'b000000000;
-    parameter dyn_tx2_pma_post_en = 5'b00000;
-    parameter dyn_tx2_pma_post_sel = 8'b00000000;
-    parameter dyn_tx2_pma_post_sign = 1'b0;
-    parameter dyn_tx2_pma_pre_en = 1'b0;
-    parameter dyn_tx2_pma_pre_sel = 4'b0000;
-    parameter dyn_tx2_pma_pre_sign = 1'b0;
-    parameter dyn_tx3_pma_main_en = 6'b000000;
-    parameter dyn_tx3_pma_main_sign = 1'b0;
-    parameter dyn_tx3_pma_margin_input = 9'b000000000;
-    parameter dyn_tx3_pma_margin_sel = 9'b000000000;
-    parameter dyn_tx3_pma_post_en = 5'b00000;
-    parameter dyn_tx3_pma_post_sel = 8'b00000000;
-    parameter dyn_tx3_pma_post_sign = 1'b0;
-    parameter dyn_tx3_pma_pre_en = 1'b0;
-    parameter dyn_tx3_pma_pre_sel = 4'b0000;
-    parameter dyn_tx3_pma_pre_sign = 1'b0;
-    parameter location = "";
-    parameter main_clk_to_fabric_div_en = 1'b0;
-    parameter main_clk_to_fabric_div_mode = 1'b0;
-    parameter main_clk_to_fabric_sel = 1'b0;
-    parameter main_rclk_to_fabric_sel = 2'b00;
-    parameter main_use_only_usr_clock = 1'b0;
-    parameter pcs_ovs_en = 1'b0;
-    parameter pcs_ovs_mode = 1'b0;
-    parameter pcs_pll_lock_ppm = 3'b000;
-    parameter pcs_word_len = 2'b00;
-    parameter pll_pma_ckref_ext = 1'b0;
-    parameter pll_pma_cpump = 4'b0000;
-    parameter pll_pma_divl = 2'b00;
-    parameter pll_pma_divm = 1'b0;
-    parameter pll_pma_divn = 2'b00;
-    parameter pll_pma_gbx_en = 1'b0;
-    parameter pll_pma_int_data_len = 1'b0;
-    parameter pll_pma_lvds_en = 1'b0;
-    parameter pll_pma_lvds_mux = 1'b0;
-    parameter pll_pma_mux_ckref = 1'b0;
-    parameter rx_usrclk_use_pcs_clk_2 = 1'b0;
-    parameter test_mode = 2'b00;
-    parameter tx_usrclk_use_pcs_clk_2 = 1'b0;
-endmodule
-
 (* blackbox *)
 module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13
 , AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10
@@ -7701,108 +3738,6 @@ module NX_SERDES(FCK, SCK, RTX, RRX, CI, CCK, CL, CR, IO, DCK, DRL, DIG, FZ, FLD
     parameter weakTermination = "";
 endmodule
 
-(* blackbox *)
-module NX_WFG(SI, ZI, RDY, SO, ZO);
-    input RDY;
-    input SI;
-    output SO;
-    input ZI;
-    output ZO;
-    parameter delay = 0;
-    parameter delay_on = 1'b0;
-    parameter location = "";
-    parameter mode = 1'b0;
-    parameter pattern = 16'b0000000000000000;
-    parameter pattern_end = 1;
-    parameter wfg_edge = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_WFG_L(R, SI, ZI, RDY, SO, ZO);
-    input R;
-    input RDY;
-    input SI;
-    output SO;
-    input ZI;
-    output ZO;
-    parameter delay = 0;
-    parameter delay_on = 1'b0;
-    parameter location = "";
-    parameter mode = 1'b0;
-    parameter pattern = 16'b0000000000000000;
-    parameter pattern_end = 1;
-    parameter wfg_edge = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_WFG_U(R, SI, ZI, SO, ZO);
-    input R;
-    input SI;
-    output SO;
-    input ZI;
-    output ZO;
-    parameter delay = 0;
-    parameter delay_on = 1'b0;
-    parameter div_phase = 1'b0;
-    parameter div_ratio = 0;
-    parameter location = "";
-    parameter mode = 0;
-    parameter pattern = 16'b0000000000000000;
-    parameter pattern_end = 0;
-    parameter reset_on_cal_lock_n = 1'b0;
-    parameter reset_on_pll_lock_n = 1'b0;
-    parameter reset_on_pll_locka_n = 1'b0;
-    parameter wfg_edge = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_XCDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, CSRSTI, CDRSTI, CSRSTO, CDRSTO, DSRSTI, DDRSTI, DSRSTO, DDRSTO, BI, CI, CO
-, AO, BO, AI, DI, DO);
-    input ADRSTI;
-    output ADRSTO;
-    input [5:0] AI;
-    output [5:0] AO;
-    input ASRSTI;
-    output ASRSTO;
-    input BDRSTI;
-    output BDRSTO;
-    input [5:0] BI;
-    output [5:0] BO;
-    input BSRSTI;
-    output BSRSTO;
-    input CDRSTI;
-    output CDRSTO;
-    input [5:0] CI;
-    input CK1;
-    input CK2;
-    output [5:0] CO;
-    input CSRSTI;
-    output CSRSTO;
-    input DDRSTI;
-    output DDRSTO;
-    input [5:0] DI;
-    output [5:0] DO;
-    input DSRSTI;
-    output DSRSTO;
-    parameter ack_sel = 1'b0;
-    parameter bck_sel = 1'b0;
-    parameter cck_sel = 1'b0;
-    parameter ck0_edge = 1'b0;
-    parameter ck1_edge = 1'b0;
-    parameter dck_sel = 1'b0;
-    parameter link_BA = 1'b0;
-    parameter link_CB = 1'b0;
-    parameter link_DC = 1'b0;
-    parameter use_adest_arst = 1'b0;
-    parameter use_asrc_arst = 1'b0;
-    parameter use_bdest_arst = 1'b0;
-    parameter use_bsrc_arst = 1'b0;
-    parameter use_cdest_arst = 1'b0;
-    parameter use_csrc_arst = 1'b0;
-    parameter use_ddest_arst = 1'b0;
-    parameter use_dsrc_arst = 1'b0;
-endmodule
-
 (* blackbox *)
 module NX_XFIFO_32x36(RCK, WCK, WE, WEA, WRSTI, WEQ, RRSTI, REQ, I, O, WAI, WAO, RAI, RAO);
     input [35:0] I;
diff --git a/techlibs/nanoxplore/cells_bb_l.v b/techlibs/nanoxplore/cells_bb_l.v
index 991600e6559..cae2a0f2971 100644
--- a/techlibs/nanoxplore/cells_bb_l.v
+++ b/techlibs/nanoxplore/cells_bb_l.v
@@ -501,3 +501,1444 @@ module NX_PLL_L(REF, FBK, R, VCO, LDFO, REFO, DIVO1, DIVO2, DIVP1, DIVP2, DIVP3,
     parameter wfg_sync_cal_lock = 1'b0;
     parameter wfg_sync_pll_lock = 1'b0;
 endmodule
+
+(* blackbox *)
+module NX_WFG_L(R, SI, ZI, RDY, SO, ZO);
+    input R;
+    input RDY;
+    input SI;
+    output SO;
+    input ZI;
+    output ZO;
+    parameter delay = 0;
+    parameter delay_on = 1'b0;
+    parameter location = "";
+    parameter mode = 1'b0;
+    parameter pattern = 16'b0000000000000000;
+    parameter pattern_end = 1;
+    parameter wfg_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_CRX_L(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, BUF_FE_I, RST_N_I, CDR_R_I, CKG_RN_I, PLL_RN_I, TST_I1, TST_I2, TST_I3, TST_I4, LOS_O, DATA_O1, DATA_O2, DATA_O3
+, DATA_O4, DATA_O5, DATA_O6, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24
+, DATA_O25, DATA_O26, DATA_O27, DATA_O28, DATA_O29, DATA_O30, DATA_O31, DATA_O32, DATA_O33, DATA_O34, DATA_O35, DATA_O36, DATA_O37, DATA_O38, DATA_O39, DATA_O40, DATA_O41, DATA_O42, DATA_O43, DATA_O44, DATA_O45
+, DATA_O46, DATA_O47, DATA_O48, DATA_O49, DATA_O50, DATA_O51, DATA_O52, DATA_O53, DATA_O54, DATA_O55, DATA_O56, DATA_O57, DATA_O58, DATA_O59, DATA_O60, DATA_O61, DATA_O62, DATA_O63, DATA_O64, CH_COM_O1, CH_COM_O2
+, CH_COM_O3, CH_COM_O4, CH_COM_O5, CH_COM_O6, CH_COM_O7, CH_COM_O8, CH_K_O1, CH_K_O2, CH_K_O3, CH_K_O4, CH_K_O5, CH_K_O6, CH_K_O7, CH_K_O8, NIT_O1, NIT_O2, NIT_O3, NIT_O4, NIT_O5, NIT_O6, NIT_O7
+, NIT_O8, D_ERR_O1, D_ERR_O2, D_ERR_O3, D_ERR_O4, D_ERR_O5, D_ERR_O6, D_ERR_O7, D_ERR_O8, CH_A_O1, CH_A_O2, CH_A_O3, CH_A_O4, CH_A_O5, CH_A_O6, CH_A_O7, CH_A_O8, CH_F_O1, CH_F_O2, CH_F_O3, CH_F_O4
+, CH_F_O5, CH_F_O6, CH_F_O7, CH_F_O8, ALIGN_O, BUSY_O, TST_O1, TST_O2, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, LOCK_O, RX_I, LINK);
+    input ALIGN_E_I;
+    output ALIGN_O;
+    input ALIGN_S_I;
+    input BUF_FE_I;
+    input BUF_R_I;
+    output BUSY_O;
+    input CDR_R_I;
+    output CH_A_O1;
+    output CH_A_O2;
+    output CH_A_O3;
+    output CH_A_O4;
+    output CH_A_O5;
+    output CH_A_O6;
+    output CH_A_O7;
+    output CH_A_O8;
+    output CH_COM_O1;
+    output CH_COM_O2;
+    output CH_COM_O3;
+    output CH_COM_O4;
+    output CH_COM_O5;
+    output CH_COM_O6;
+    output CH_COM_O7;
+    output CH_COM_O8;
+    output CH_F_O1;
+    output CH_F_O2;
+    output CH_F_O3;
+    output CH_F_O4;
+    output CH_F_O5;
+    output CH_F_O6;
+    output CH_F_O7;
+    output CH_F_O8;
+    output CH_K_O1;
+    output CH_K_O2;
+    output CH_K_O3;
+    output CH_K_O4;
+    output CH_K_O5;
+    output CH_K_O6;
+    output CH_K_O7;
+    output CH_K_O8;
+    input CKG_RN_I;
+    output DATA_O1;
+    output DATA_O10;
+    output DATA_O11;
+    output DATA_O12;
+    output DATA_O13;
+    output DATA_O14;
+    output DATA_O15;
+    output DATA_O16;
+    output DATA_O17;
+    output DATA_O18;
+    output DATA_O19;
+    output DATA_O2;
+    output DATA_O20;
+    output DATA_O21;
+    output DATA_O22;
+    output DATA_O23;
+    output DATA_O24;
+    output DATA_O25;
+    output DATA_O26;
+    output DATA_O27;
+    output DATA_O28;
+    output DATA_O29;
+    output DATA_O3;
+    output DATA_O30;
+    output DATA_O31;
+    output DATA_O32;
+    output DATA_O33;
+    output DATA_O34;
+    output DATA_O35;
+    output DATA_O36;
+    output DATA_O37;
+    output DATA_O38;
+    output DATA_O39;
+    output DATA_O4;
+    output DATA_O40;
+    output DATA_O41;
+    output DATA_O42;
+    output DATA_O43;
+    output DATA_O44;
+    output DATA_O45;
+    output DATA_O46;
+    output DATA_O47;
+    output DATA_O48;
+    output DATA_O49;
+    output DATA_O5;
+    output DATA_O50;
+    output DATA_O51;
+    output DATA_O52;
+    output DATA_O53;
+    output DATA_O54;
+    output DATA_O55;
+    output DATA_O56;
+    output DATA_O57;
+    output DATA_O58;
+    output DATA_O59;
+    output DATA_O6;
+    output DATA_O60;
+    output DATA_O61;
+    output DATA_O62;
+    output DATA_O63;
+    output DATA_O64;
+    output DATA_O7;
+    output DATA_O8;
+    output DATA_O9;
+    input DEC_E_I;
+    input DSCR_E_I;
+    output D_ERR_O1;
+    output D_ERR_O2;
+    output D_ERR_O3;
+    output D_ERR_O4;
+    output D_ERR_O5;
+    output D_ERR_O6;
+    output D_ERR_O7;
+    output D_ERR_O8;
+    inout [9:0] LINK;
+    output LOCK_O;
+    output LOS_O;
+    output NIT_O1;
+    output NIT_O2;
+    output NIT_O3;
+    output NIT_O4;
+    output NIT_O5;
+    output NIT_O6;
+    output NIT_O7;
+    output NIT_O8;
+    input OVS_BS_I1;
+    input OVS_BS_I2;
+    input PLL_RN_I;
+    input REP_E_I;
+    input RST_N_I;
+    input RX_I;
+    input TST_I1;
+    input TST_I2;
+    input TST_I3;
+    input TST_I4;
+    output TST_O1;
+    output TST_O2;
+    output TST_O3;
+    output TST_O4;
+    output TST_O5;
+    output TST_O6;
+    output TST_O7;
+    output TST_O8;
+    parameter location = "";
+    parameter pcs_8b_dscr_sel = 1'b0;
+    parameter pcs_align_bypass = 1'b0;
+    parameter pcs_buffers_bypass = 1'b0;
+    parameter pcs_buffers_use_cdc = 1'b0;
+    parameter pcs_bypass_pma_cdc = 1'b0;
+    parameter pcs_bypass_usr_cdc = 1'b0;
+    parameter pcs_comma_mask = 10'b0000000000;
+    parameter pcs_debug_en = 1'b0;
+    parameter pcs_dec_bypass = 1'b0;
+    parameter pcs_dscr_bypass = 1'b0;
+    parameter pcs_el_buff_diff_bef_comp = 3'b000;
+    parameter pcs_el_buff_max_comp = 3'b000;
+    parameter pcs_el_buff_only_one_skp = 1'b0;
+    parameter pcs_el_buff_skp_char_0 = 9'b000000000;
+    parameter pcs_el_buff_skp_char_1 = 9'b000000000;
+    parameter pcs_el_buff_skp_char_2 = 9'b000000000;
+    parameter pcs_el_buff_skp_char_3 = 9'b000000000;
+    parameter pcs_el_buff_skp_header_0 = 9'b000000000;
+    parameter pcs_el_buff_skp_header_1 = 9'b000000000;
+    parameter pcs_el_buff_skp_header_2 = 9'b000000000;
+    parameter pcs_el_buff_skp_header_3 = 9'b000000000;
+    parameter pcs_el_buff_skp_header_size = 2'b00;
+    parameter pcs_el_buff_skp_seq_size = 2'b00;
+    parameter pcs_el_buff_underflow_handle = 1'b0;
+    parameter pcs_fsm_sel = 2'b00;
+    parameter pcs_fsm_watchdog_en = 1'b0;
+    parameter pcs_loopback = 1'b0;
+    parameter pcs_m_comma_en = 1'b0;
+    parameter pcs_m_comma_val = 10'b0000000000;
+    parameter pcs_nb_comma_bef_realign = 2'b00;
+    parameter pcs_p_comma_en = 1'b0;
+    parameter pcs_p_comma_val = 10'b0000000000;
+    parameter pcs_polarity = 1'b0;
+    parameter pcs_protocol_size = 1'b0;
+    parameter pcs_replace_bypass = 1'b0;
+    parameter pcs_sync_supported = 1'b0;
+    parameter pma_cdr_cp = 4'b0000;
+    parameter pma_clk_pos = 1'b0;
+    parameter pma_ctrl_term = 6'b000000;
+    parameter pma_loopback = 1'b0;
+    parameter pma_pll_cpump_n = 3'b000;
+    parameter pma_pll_divf = 2'b00;
+    parameter pma_pll_divf_en_n = 1'b0;
+    parameter pma_pll_divm = 2'b00;
+    parameter pma_pll_divm_en_n = 1'b0;
+    parameter pma_pll_divn = 1'b0;
+    parameter pma_pll_divn_en_n = 1'b0;
+    parameter test = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_CTX_L(ENC_E_I1, ENC_E_I2, ENC_E_I3, ENC_E_I4, ENC_E_I5, ENC_E_I6, ENC_E_I7, ENC_E_I8, CH_K_I1, CH_K_I2, CH_K_I3, CH_K_I4, CH_K_I5, CH_K_I6, CH_K_I7, CH_K_I8, SCR_E_I1, SCR_E_I2, SCR_E_I3, SCR_E_I4, SCR_E_I5
+, SCR_E_I6, SCR_E_I7, SCR_E_I8, EOMF_I1, EOMF_I2, EOMF_I3, EOMF_I4, EOMF_I5, EOMF_I6, EOMF_I7, EOMF_I8, EOF_I1, EOF_I2, EOF_I3, EOF_I4, EOF_I5, EOF_I6, EOF_I7, EOF_I8, REP_E_I, RST_N_I
+, TST_I1, TST_I2, TST_I3, TST_I4, DATA_I1, DATA_I2, DATA_I3, DATA_I4, DATA_I5, DATA_I6, DATA_I7, DATA_I8, DATA_I9, DATA_I10, DATA_I11, DATA_I12, DATA_I13, DATA_I14, DATA_I15, DATA_I16, DATA_I17
+, DATA_I18, DATA_I19, DATA_I20, DATA_I21, DATA_I22, DATA_I23, DATA_I24, DATA_I25, DATA_I26, DATA_I27, DATA_I28, DATA_I29, DATA_I30, DATA_I31, DATA_I32, DATA_I33, DATA_I34, DATA_I35, DATA_I36, DATA_I37, DATA_I38
+, DATA_I39, DATA_I40, DATA_I41, DATA_I42, DATA_I43, DATA_I44, DATA_I45, DATA_I46, DATA_I47, DATA_I48, DATA_I49, DATA_I50, DATA_I51, DATA_I52, DATA_I53, DATA_I54, DATA_I55, DATA_I56, DATA_I57, DATA_I58, DATA_I59
+, DATA_I60, DATA_I61, DATA_I62, DATA_I63, DATA_I64, TST_O1, TST_O2, TST_O3, TST_O4, BUSY_O, CLK_E_I, TX_O, LINK);
+    output BUSY_O;
+    input CH_K_I1;
+    input CH_K_I2;
+    input CH_K_I3;
+    input CH_K_I4;
+    input CH_K_I5;
+    input CH_K_I6;
+    input CH_K_I7;
+    input CH_K_I8;
+    input CLK_E_I;
+    input DATA_I1;
+    input DATA_I10;
+    input DATA_I11;
+    input DATA_I12;
+    input DATA_I13;
+    input DATA_I14;
+    input DATA_I15;
+    input DATA_I16;
+    input DATA_I17;
+    input DATA_I18;
+    input DATA_I19;
+    input DATA_I2;
+    input DATA_I20;
+    input DATA_I21;
+    input DATA_I22;
+    input DATA_I23;
+    input DATA_I24;
+    input DATA_I25;
+    input DATA_I26;
+    input DATA_I27;
+    input DATA_I28;
+    input DATA_I29;
+    input DATA_I3;
+    input DATA_I30;
+    input DATA_I31;
+    input DATA_I32;
+    input DATA_I33;
+    input DATA_I34;
+    input DATA_I35;
+    input DATA_I36;
+    input DATA_I37;
+    input DATA_I38;
+    input DATA_I39;
+    input DATA_I4;
+    input DATA_I40;
+    input DATA_I41;
+    input DATA_I42;
+    input DATA_I43;
+    input DATA_I44;
+    input DATA_I45;
+    input DATA_I46;
+    input DATA_I47;
+    input DATA_I48;
+    input DATA_I49;
+    input DATA_I5;
+    input DATA_I50;
+    input DATA_I51;
+    input DATA_I52;
+    input DATA_I53;
+    input DATA_I54;
+    input DATA_I55;
+    input DATA_I56;
+    input DATA_I57;
+    input DATA_I58;
+    input DATA_I59;
+    input DATA_I6;
+    input DATA_I60;
+    input DATA_I61;
+    input DATA_I62;
+    input DATA_I63;
+    input DATA_I64;
+    input DATA_I7;
+    input DATA_I8;
+    input DATA_I9;
+    input ENC_E_I1;
+    input ENC_E_I2;
+    input ENC_E_I3;
+    input ENC_E_I4;
+    input ENC_E_I5;
+    input ENC_E_I6;
+    input ENC_E_I7;
+    input ENC_E_I8;
+    input EOF_I1;
+    input EOF_I2;
+    input EOF_I3;
+    input EOF_I4;
+    input EOF_I5;
+    input EOF_I6;
+    input EOF_I7;
+    input EOF_I8;
+    input EOMF_I1;
+    input EOMF_I2;
+    input EOMF_I3;
+    input EOMF_I4;
+    input EOMF_I5;
+    input EOMF_I6;
+    input EOMF_I7;
+    input EOMF_I8;
+    inout [19:0] LINK;
+    input REP_E_I;
+    input RST_N_I;
+    input SCR_E_I1;
+    input SCR_E_I2;
+    input SCR_E_I3;
+    input SCR_E_I4;
+    input SCR_E_I5;
+    input SCR_E_I6;
+    input SCR_E_I7;
+    input SCR_E_I8;
+    input TST_I1;
+    input TST_I2;
+    input TST_I3;
+    input TST_I4;
+    output TST_O1;
+    output TST_O2;
+    output TST_O3;
+    output TST_O4;
+    output TX_O;
+    parameter location = "";
+    parameter pcs_8b_scr_sel = 1'b0;
+    parameter pcs_bypass_pma_cdc = 1'b0;
+    parameter pcs_bypass_usr_cdc = 1'b0;
+    parameter pcs_enc_bypass = 1'b0;
+    parameter pcs_esistream_fsm_en = 1'b0;
+    parameter pcs_loopback = 1'b0;
+    parameter pcs_polarity = 1'b0;
+    parameter pcs_protocol_size = 1'b0;
+    parameter pcs_replace_bypass = 1'b0;
+    parameter pcs_scr_bypass = 1'b0;
+    parameter pcs_scr_init = 17'b00000000000000000;
+    parameter pcs_sync_supported = 1'b0;
+    parameter pma_clk_pos = 1'b0;
+    parameter pma_loopback = 1'b0;
+    parameter test = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_IOM_L(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, CCK, DCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1
+, C2RW2, C2RW3, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3
+, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1
+, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3, DRO4
+, DRO5, DRO6, CAL, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EL, P1ER, P1EO, P1RI, P1RL, P1RR, P1RO1
+, P1RO2, P1RO3, P1RO4, P1RO5, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EL, P2ER, P2EO, P2RI, P2RL, P2RR
+, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P3CI1, P3CL, P3CR, P3CO, P3CTI, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EL, P3ER, P3EO, P3RI, P3RL
+, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EL, P4ER, P4EO, P4RI
+, P4RL, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P5CI1, P5CI2, P5CI3, P5CI4, P5CI5, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3, P5EI4
+, P5EI5, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P6CI1, P6CL, P6CR, P6CO, P6CTI, P6CTO, P6EI1, P6EI2, P6EI3
+, P6EI4, P6EI5, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1, P7EI2
+, P7EI3, P7EI4, P7EI5, P7EL, P7ER, P7EO, P7RI, P7RL, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO, P8EI1
+, P8EI2, P8EI3, P8EI4, P8EI5, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P9CI1, P9CL, P9CR, P9CO, P9CTI, P9CTO
+, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P10CI1, P10CL, P10CR, P10CO, P10CTI
+, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EL, P10ER, P10EO, P10RI, P10RL, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P11CI1, P11CL, P11CR, P11CO
+, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P12CI1, P12CL, P12CR
+, P12CO, P12CTI, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P13CI1, P13CL
+, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EL, P13ER, P13EO, P13RI, P13RL, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5, P14CI1
+, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4, P14RO5
+, P15CI1, P15CL, P15CR, P15CO, P15CTI, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3, P15RO4
+, P15RO5, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EL, P16ER, P16EO, P16RI, P16RL, P16RR, P16RO1, P16RO2, P16RO3
+, P16RO4, P16RO5, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1, P17RO2
+, P17RO3, P17RO4, P17RO5, P18CI1, P18CL, P18CR, P18CO, P18CTI, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR, P18RO1
+, P18RO2, P18RO3, P18RO4, P18RO5, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EL, P19ER, P19EO, P19RI, P19RL, P19RR
+, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EL, P20ER, P20EO, P20RI, P20RL
+, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P21CI1, P21CL, P21CR, P21CO, P21CTI, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EL, P21ER, P21EO, P21RI
+, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EL, P22ER, P22EO
+, P22RI, P22RL, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EL, P23ER
+, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P24CI1, P24CL, P24CR, P24CO, P24CTI, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5, P24EL
+, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P25CI1, P25CL, P25CR, P25CO, P25CTI, P25CTO, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5
+, P25EL, P25ER, P25EO, P25RI, P25RL, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P26CI1, P26CL, P26CR, P26CO, P26CTI, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4
+, P26EI5, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P27CI1, P27CL, P27CR, P27CO, P27CTI, P27CTO, P27EI1, P27EI2, P27EI3
+, P27EI4, P27EI5, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P28CI1, P28CL, P28CR, P28CO, P28CTI, P28CTO, P28EI1, P28EI2
+, P28EI3, P28EI4, P28EI5, P28EL, P28ER, P28EO, P28RI, P28RL, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P29CI1, P29CI2, P29CI3, P29CI4, P29CI5, P29CL, P29CR
+, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P30CI1, P30CL
+, P30CR, P30CO, P30CTI, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5, P31CI1
+, P31CL, P31CR, P31CO, P31CTI, P31CTO, P31EI1, P31EI2, P31EI3, P31EI4, P31EI5, P31EL, P31ER, P31EO, P31RI, P31RL, P31RR, P31RO1, P31RO2, P31RO3, P31RO4, P31RO5
+, P32CI1, P32CL, P32CR, P32CO, P32CTI, P32CTO, P32EI1, P32EI2, P32EI3, P32EI4, P32EI5, P32EL, P32ER, P32EO, P32RI, P32RL, P32RR, P32RO1, P32RO2, P32RO3, P32RO4
+, P32RO5, P33CI1, P33CL, P33CR, P33CO, P33CTI, P33CTO, P33EI1, P33EI2, P33EI3, P33EI4, P33EI5, P33EL, P33ER, P33EO, P33RI, P33RL, P33RR, P33RO1, P33RO2, P33RO3
+, P33RO4, P33RO5, P34CI1, P34CL, P34CR, P34CO, P34CTI, P34CTO, P34EI1, P34EI2, P34EI3, P34EI4, P34EI5, P34EL, P34ER, P34EO, P34RI, P34RL, P34RR, P34RO1, P34RO2
+, P34RO3, P34RO4, P34RO5);
+    output C1RED;
+    input C1RNE;
+    input C1RS;
+    input C1RW1;
+    input C1RW2;
+    input C1RW3;
+    input C1TS;
+    input C1TW;
+    output C2RED;
+    input C2RNE;
+    input C2RS;
+    input C2RW1;
+    input C2RW2;
+    input C2RW3;
+    input C2TS;
+    input C2TW;
+    input CAD1;
+    input CAD2;
+    input CAD3;
+    input CAD4;
+    input CAD5;
+    input CAD6;
+    output CAL;
+    input CAN1;
+    input CAN2;
+    input CAN3;
+    input CAN4;
+    input CAP1;
+    input CAP2;
+    input CAP3;
+    input CAP4;
+    input CAT1;
+    input CAT2;
+    input CAT3;
+    input CAT4;
+    input CCK;
+    output CKO1;
+    output CKO2;
+    input CTCK;
+    input DC;
+    input DCK;
+    input DIG;
+    input DIS;
+    input DOG;
+    input DOS;
+    input DPAG;
+    input DPAS;
+    input DQSG;
+    input DQSS;
+    input DRA1;
+    input DRA2;
+    input DRA3;
+    input DRA4;
+    input DRA5;
+    input DRA6;
+    input DRI1;
+    input DRI2;
+    input DRI3;
+    input DRI4;
+    input DRI5;
+    input DRI6;
+    input DRL;
+    output DRO1;
+    output DRO2;
+    output DRO3;
+    output DRO4;
+    output DRO5;
+    output DRO6;
+    input DS1;
+    input DS2;
+    input FA1;
+    input FA2;
+    input FA3;
+    input FA4;
+    input FA5;
+    input FA6;
+    output FLD;
+    output FLG;
+    input FZ;
+    input P10CI1;
+    input P10CL;
+    output P10CO;
+    input P10CR;
+    input P10CTI;
+    output P10CTO;
+    input P10EI1;
+    input P10EI2;
+    input P10EI3;
+    input P10EI4;
+    input P10EI5;
+    input P10EL;
+    output P10EO;
+    input P10ER;
+    input P10RI;
+    input P10RL;
+    output P10RO1;
+    output P10RO2;
+    output P10RO3;
+    output P10RO4;
+    output P10RO5;
+    input P10RR;
+    input P11CI1;
+    input P11CL;
+    output P11CO;
+    input P11CR;
+    input P11CTI;
+    output P11CTO;
+    input P11EI1;
+    input P11EI2;
+    input P11EI3;
+    input P11EI4;
+    input P11EI5;
+    input P11EL;
+    output P11EO;
+    input P11ER;
+    input P11RI;
+    input P11RL;
+    output P11RO1;
+    output P11RO2;
+    output P11RO3;
+    output P11RO4;
+    output P11RO5;
+    input P11RR;
+    input P12CI1;
+    input P12CL;
+    output P12CO;
+    input P12CR;
+    input P12CTI;
+    output P12CTO;
+    input P12EI1;
+    input P12EI2;
+    input P12EI3;
+    input P12EI4;
+    input P12EI5;
+    input P12EL;
+    output P12EO;
+    input P12ER;
+    input P12RI;
+    input P12RL;
+    output P12RO1;
+    output P12RO2;
+    output P12RO3;
+    output P12RO4;
+    output P12RO5;
+    input P12RR;
+    input P13CI1;
+    input P13CL;
+    output P13CO;
+    input P13CR;
+    input P13CTI;
+    output P13CTO;
+    input P13EI1;
+    input P13EI2;
+    input P13EI3;
+    input P13EI4;
+    input P13EI5;
+    input P13EL;
+    output P13EO;
+    input P13ER;
+    input P13RI;
+    input P13RL;
+    output P13RO1;
+    output P13RO2;
+    output P13RO3;
+    output P13RO4;
+    output P13RO5;
+    input P13RR;
+    input P14CI1;
+    input P14CL;
+    output P14CO;
+    input P14CR;
+    input P14CTI;
+    output P14CTO;
+    input P14EI1;
+    input P14EI2;
+    input P14EI3;
+    input P14EI4;
+    input P14EI5;
+    input P14EL;
+    output P14EO;
+    input P14ER;
+    input P14RI;
+    input P14RL;
+    output P14RO1;
+    output P14RO2;
+    output P14RO3;
+    output P14RO4;
+    output P14RO5;
+    input P14RR;
+    input P15CI1;
+    input P15CL;
+    output P15CO;
+    input P15CR;
+    input P15CTI;
+    output P15CTO;
+    input P15EI1;
+    input P15EI2;
+    input P15EI3;
+    input P15EI4;
+    input P15EI5;
+    input P15EL;
+    output P15EO;
+    input P15ER;
+    input P15RI;
+    input P15RL;
+    output P15RO1;
+    output P15RO2;
+    output P15RO3;
+    output P15RO4;
+    output P15RO5;
+    input P15RR;
+    input P16CI1;
+    input P16CL;
+    output P16CO;
+    input P16CR;
+    input P16CTI;
+    output P16CTO;
+    input P16EI1;
+    input P16EI2;
+    input P16EI3;
+    input P16EI4;
+    input P16EI5;
+    input P16EL;
+    output P16EO;
+    input P16ER;
+    input P16RI;
+    input P16RL;
+    output P16RO1;
+    output P16RO2;
+    output P16RO3;
+    output P16RO4;
+    output P16RO5;
+    input P16RR;
+    input P17CI1;
+    input P17CL;
+    output P17CO;
+    input P17CR;
+    input P17CTI;
+    output P17CTO;
+    input P17EI1;
+    input P17EI2;
+    input P17EI3;
+    input P17EI4;
+    input P17EI5;
+    input P17EL;
+    output P17EO;
+    input P17ER;
+    input P17RI;
+    input P17RL;
+    output P17RO1;
+    output P17RO2;
+    output P17RO3;
+    output P17RO4;
+    output P17RO5;
+    input P17RR;
+    input P18CI1;
+    input P18CL;
+    output P18CO;
+    input P18CR;
+    input P18CTI;
+    output P18CTO;
+    input P18EI1;
+    input P18EI2;
+    input P18EI3;
+    input P18EI4;
+    input P18EI5;
+    input P18EL;
+    output P18EO;
+    input P18ER;
+    input P18RI;
+    input P18RL;
+    output P18RO1;
+    output P18RO2;
+    output P18RO3;
+    output P18RO4;
+    output P18RO5;
+    input P18RR;
+    input P19CI1;
+    input P19CL;
+    output P19CO;
+    input P19CR;
+    input P19CTI;
+    output P19CTO;
+    input P19EI1;
+    input P19EI2;
+    input P19EI3;
+    input P19EI4;
+    input P19EI5;
+    input P19EL;
+    output P19EO;
+    input P19ER;
+    input P19RI;
+    input P19RL;
+    output P19RO1;
+    output P19RO2;
+    output P19RO3;
+    output P19RO4;
+    output P19RO5;
+    input P19RR;
+    input P1CI1;
+    input P1CL;
+    output P1CO;
+    input P1CR;
+    input P1CTI;
+    output P1CTO;
+    input P1EI1;
+    input P1EI2;
+    input P1EI3;
+    input P1EI4;
+    input P1EI5;
+    input P1EL;
+    output P1EO;
+    input P1ER;
+    input P1RI;
+    input P1RL;
+    output P1RO1;
+    output P1RO2;
+    output P1RO3;
+    output P1RO4;
+    output P1RO5;
+    input P1RR;
+    input P20CI1;
+    input P20CL;
+    output P20CO;
+    input P20CR;
+    input P20CTI;
+    output P20CTO;
+    input P20EI1;
+    input P20EI2;
+    input P20EI3;
+    input P20EI4;
+    input P20EI5;
+    input P20EL;
+    output P20EO;
+    input P20ER;
+    input P20RI;
+    input P20RL;
+    output P20RO1;
+    output P20RO2;
+    output P20RO3;
+    output P20RO4;
+    output P20RO5;
+    input P20RR;
+    input P21CI1;
+    input P21CL;
+    output P21CO;
+    input P21CR;
+    input P21CTI;
+    output P21CTO;
+    input P21EI1;
+    input P21EI2;
+    input P21EI3;
+    input P21EI4;
+    input P21EI5;
+    input P21EL;
+    output P21EO;
+    input P21ER;
+    input P21RI;
+    input P21RL;
+    output P21RO1;
+    output P21RO2;
+    output P21RO3;
+    output P21RO4;
+    output P21RO5;
+    input P21RR;
+    input P22CI1;
+    input P22CL;
+    output P22CO;
+    input P22CR;
+    input P22CTI;
+    output P22CTO;
+    input P22EI1;
+    input P22EI2;
+    input P22EI3;
+    input P22EI4;
+    input P22EI5;
+    input P22EL;
+    output P22EO;
+    input P22ER;
+    input P22RI;
+    input P22RL;
+    output P22RO1;
+    output P22RO2;
+    output P22RO3;
+    output P22RO4;
+    output P22RO5;
+    input P22RR;
+    input P23CI1;
+    input P23CL;
+    output P23CO;
+    input P23CR;
+    input P23CTI;
+    output P23CTO;
+    input P23EI1;
+    input P23EI2;
+    input P23EI3;
+    input P23EI4;
+    input P23EI5;
+    input P23EL;
+    output P23EO;
+    input P23ER;
+    input P23RI;
+    input P23RL;
+    output P23RO1;
+    output P23RO2;
+    output P23RO3;
+    output P23RO4;
+    output P23RO5;
+    input P23RR;
+    input P24CI1;
+    input P24CL;
+    output P24CO;
+    input P24CR;
+    input P24CTI;
+    output P24CTO;
+    input P24EI1;
+    input P24EI2;
+    input P24EI3;
+    input P24EI4;
+    input P24EI5;
+    input P24EL;
+    output P24EO;
+    input P24ER;
+    input P24RI;
+    input P24RL;
+    output P24RO1;
+    output P24RO2;
+    output P24RO3;
+    output P24RO4;
+    output P24RO5;
+    input P24RR;
+    input P25CI1;
+    input P25CL;
+    output P25CO;
+    input P25CR;
+    input P25CTI;
+    output P25CTO;
+    input P25EI1;
+    input P25EI2;
+    input P25EI3;
+    input P25EI4;
+    input P25EI5;
+    input P25EL;
+    output P25EO;
+    input P25ER;
+    input P25RI;
+    input P25RL;
+    output P25RO1;
+    output P25RO2;
+    output P25RO3;
+    output P25RO4;
+    output P25RO5;
+    input P25RR;
+    input P26CI1;
+    input P26CL;
+    output P26CO;
+    input P26CR;
+    input P26CTI;
+    output P26CTO;
+    input P26EI1;
+    input P26EI2;
+    input P26EI3;
+    input P26EI4;
+    input P26EI5;
+    input P26EL;
+    output P26EO;
+    input P26ER;
+    input P26RI;
+    input P26RL;
+    output P26RO1;
+    output P26RO2;
+    output P26RO3;
+    output P26RO4;
+    output P26RO5;
+    input P26RR;
+    input P27CI1;
+    input P27CL;
+    output P27CO;
+    input P27CR;
+    input P27CTI;
+    output P27CTO;
+    input P27EI1;
+    input P27EI2;
+    input P27EI3;
+    input P27EI4;
+    input P27EI5;
+    input P27EL;
+    output P27EO;
+    input P27ER;
+    input P27RI;
+    input P27RL;
+    output P27RO1;
+    output P27RO2;
+    output P27RO3;
+    output P27RO4;
+    output P27RO5;
+    input P27RR;
+    input P28CI1;
+    input P28CL;
+    output P28CO;
+    input P28CR;
+    input P28CTI;
+    output P28CTO;
+    input P28EI1;
+    input P28EI2;
+    input P28EI3;
+    input P28EI4;
+    input P28EI5;
+    input P28EL;
+    output P28EO;
+    input P28ER;
+    input P28RI;
+    input P28RL;
+    output P28RO1;
+    output P28RO2;
+    output P28RO3;
+    output P28RO4;
+    output P28RO5;
+    input P28RR;
+    input P29CI1;
+    input P29CI2;
+    input P29CI3;
+    input P29CI4;
+    input P29CI5;
+    input P29CL;
+    output P29CO;
+    input P29CR;
+    input P29CTI;
+    output P29CTO;
+    input P29EI1;
+    input P29EI2;
+    input P29EI3;
+    input P29EI4;
+    input P29EI5;
+    input P29EL;
+    output P29EO;
+    input P29ER;
+    input P29RI;
+    input P29RL;
+    output P29RO1;
+    output P29RO2;
+    output P29RO3;
+    output P29RO4;
+    output P29RO5;
+    input P29RR;
+    input P2CI1;
+    input P2CL;
+    output P2CO;
+    input P2CR;
+    input P2CTI;
+    output P2CTO;
+    input P2EI1;
+    input P2EI2;
+    input P2EI3;
+    input P2EI4;
+    input P2EI5;
+    input P2EL;
+    output P2EO;
+    input P2ER;
+    input P2RI;
+    input P2RL;
+    output P2RO1;
+    output P2RO2;
+    output P2RO3;
+    output P2RO4;
+    output P2RO5;
+    input P2RR;
+    input P30CI1;
+    input P30CL;
+    output P30CO;
+    input P30CR;
+    input P30CTI;
+    output P30CTO;
+    input P30EI1;
+    input P30EI2;
+    input P30EI3;
+    input P30EI4;
+    input P30EI5;
+    input P30EL;
+    output P30EO;
+    input P30ER;
+    input P30RI;
+    input P30RL;
+    output P30RO1;
+    output P30RO2;
+    output P30RO3;
+    output P30RO4;
+    output P30RO5;
+    input P30RR;
+    input P31CI1;
+    input P31CL;
+    output P31CO;
+    input P31CR;
+    input P31CTI;
+    output P31CTO;
+    input P31EI1;
+    input P31EI2;
+    input P31EI3;
+    input P31EI4;
+    input P31EI5;
+    input P31EL;
+    output P31EO;
+    input P31ER;
+    input P31RI;
+    input P31RL;
+    output P31RO1;
+    output P31RO2;
+    output P31RO3;
+    output P31RO4;
+    output P31RO5;
+    input P31RR;
+    input P32CI1;
+    input P32CL;
+    output P32CO;
+    input P32CR;
+    input P32CTI;
+    output P32CTO;
+    input P32EI1;
+    input P32EI2;
+    input P32EI3;
+    input P32EI4;
+    input P32EI5;
+    input P32EL;
+    output P32EO;
+    input P32ER;
+    input P32RI;
+    input P32RL;
+    output P32RO1;
+    output P32RO2;
+    output P32RO3;
+    output P32RO4;
+    output P32RO5;
+    input P32RR;
+    input P33CI1;
+    input P33CL;
+    output P33CO;
+    input P33CR;
+    input P33CTI;
+    output P33CTO;
+    input P33EI1;
+    input P33EI2;
+    input P33EI3;
+    input P33EI4;
+    input P33EI5;
+    input P33EL;
+    output P33EO;
+    input P33ER;
+    input P33RI;
+    input P33RL;
+    output P33RO1;
+    output P33RO2;
+    output P33RO3;
+    output P33RO4;
+    output P33RO5;
+    input P33RR;
+    input P34CI1;
+    input P34CL;
+    output P34CO;
+    input P34CR;
+    input P34CTI;
+    output P34CTO;
+    input P34EI1;
+    input P34EI2;
+    input P34EI3;
+    input P34EI4;
+    input P34EI5;
+    input P34EL;
+    output P34EO;
+    input P34ER;
+    input P34RI;
+    input P34RL;
+    output P34RO1;
+    output P34RO2;
+    output P34RO3;
+    output P34RO4;
+    output P34RO5;
+    input P34RR;
+    input P3CI1;
+    input P3CL;
+    output P3CO;
+    input P3CR;
+    input P3CTI;
+    output P3CTO;
+    input P3EI1;
+    input P3EI2;
+    input P3EI3;
+    input P3EI4;
+    input P3EI5;
+    input P3EL;
+    output P3EO;
+    input P3ER;
+    input P3RI;
+    input P3RL;
+    output P3RO1;
+    output P3RO2;
+    output P3RO3;
+    output P3RO4;
+    output P3RO5;
+    input P3RR;
+    input P4CI1;
+    input P4CL;
+    output P4CO;
+    input P4CR;
+    input P4CTI;
+    output P4CTO;
+    input P4EI1;
+    input P4EI2;
+    input P4EI3;
+    input P4EI4;
+    input P4EI5;
+    input P4EL;
+    output P4EO;
+    input P4ER;
+    input P4RI;
+    input P4RL;
+    output P4RO1;
+    output P4RO2;
+    output P4RO3;
+    output P4RO4;
+    output P4RO5;
+    input P4RR;
+    input P5CI1;
+    input P5CI2;
+    input P5CI3;
+    input P5CI4;
+    input P5CI5;
+    input P5CL;
+    output P5CO;
+    input P5CR;
+    input P5CTI;
+    output P5CTO;
+    input P5EI1;
+    input P5EI2;
+    input P5EI3;
+    input P5EI4;
+    input P5EI5;
+    input P5EL;
+    output P5EO;
+    input P5ER;
+    input P5RI;
+    input P5RL;
+    output P5RO1;
+    output P5RO2;
+    output P5RO3;
+    output P5RO4;
+    output P5RO5;
+    input P5RR;
+    input P6CI1;
+    input P6CL;
+    output P6CO;
+    input P6CR;
+    input P6CTI;
+    output P6CTO;
+    input P6EI1;
+    input P6EI2;
+    input P6EI3;
+    input P6EI4;
+    input P6EI5;
+    input P6EL;
+    output P6EO;
+    input P6ER;
+    input P6RI;
+    input P6RL;
+    output P6RO1;
+    output P6RO2;
+    output P6RO3;
+    output P6RO4;
+    output P6RO5;
+    input P6RR;
+    input P7CI1;
+    input P7CL;
+    output P7CO;
+    input P7CR;
+    input P7CTI;
+    output P7CTO;
+    input P7EI1;
+    input P7EI2;
+    input P7EI3;
+    input P7EI4;
+    input P7EI5;
+    input P7EL;
+    output P7EO;
+    input P7ER;
+    input P7RI;
+    input P7RL;
+    output P7RO1;
+    output P7RO2;
+    output P7RO3;
+    output P7RO4;
+    output P7RO5;
+    input P7RR;
+    input P8CI1;
+    input P8CL;
+    output P8CO;
+    input P8CR;
+    input P8CTI;
+    output P8CTO;
+    input P8EI1;
+    input P8EI2;
+    input P8EI3;
+    input P8EI4;
+    input P8EI5;
+    input P8EL;
+    output P8EO;
+    input P8ER;
+    input P8RI;
+    input P8RL;
+    output P8RO1;
+    output P8RO2;
+    output P8RO3;
+    output P8RO4;
+    output P8RO5;
+    input P8RR;
+    input P9CI1;
+    input P9CL;
+    output P9CO;
+    input P9CR;
+    input P9CTI;
+    output P9CTO;
+    input P9EI1;
+    input P9EI2;
+    input P9EI3;
+    input P9EI4;
+    input P9EI5;
+    input P9EL;
+    output P9EO;
+    input P9ER;
+    input P9RI;
+    input P9RL;
+    output P9RO1;
+    output P9RO2;
+    output P9RO3;
+    output P9RO4;
+    output P9RO5;
+    input P9RR;
+    input RRCK1;
+    input RRCK2;
+    input RTCK1;
+    input RTCK2;
+    input WRCK1;
+    input WRCK2;
+    input WTCK1;
+    input WTCK2;
+    parameter div_rx1 = 4'b0000;
+    parameter div_rx2 = 4'b0000;
+    parameter div_tx1 = 4'b0000;
+    parameter div_tx2 = 4'b0000;
+    parameter mode_io_cal = 1'b0;
+    parameter mode_side1 = 0;
+    parameter mode_side2 = 0;
+    parameter pads_dict = "";
+    parameter pads_path = "";
+    parameter sel_clk_out1 = 1'b0;
+    parameter sel_clk_out2 = 1'b0;
+    parameter sel_clkr_rx1 = 1'b0;
+    parameter sel_clkr_rx2 = 1'b0;
+    parameter sel_clkw_rx1 = 2'b00;
+    parameter sel_clkw_rx2 = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_PMA_L(CLK_USER_I, CLK_REF_I, PRE_SG_I, PRE_EN_I, PRE_IS_I1, PRE_IS_I2, PRE_IS_I3, PRE_IS_I4, MAIN_SG_I, MAIN_EN_I1, MAIN_EN_I2, MAIN_EN_I3, MAIN_EN_I4, MAIN_EN_I5, MAIN_EN_I6, MARG_S_I1, MARG_S_I2, MARG_S_I3, MARG_S_I4, MARG_IS_I1, MARG_IS_I2
+, MARG_IS_I3, MARG_IS_I4, MARG_SV_I1, MARG_SV_I2, MARG_SV_I3, MARG_SV_I4, MARG_SV_I5, MARG_ISV_I1, MARG_ISV_I2, MARG_ISV_I3, MARG_ISV_I4, MARG_ISV_I5, POST_EN_I1, POST_EN_I2, POST_EN_I3, POST_EN_I4, POST_EN_I5, POST_SG_I, POST_IS_I1, POST_IS_I2, POST_IS_I3
+, POST_IS_I4, POST_ISV_I1, POST_ISV_I2, POST_ISV_I3, POST_ISV_I4, TX_SEL_I1, TX_SEL_I2, TX_SEL_I3, TX_SEL_I4, TX_SEL_I5, TX_SEL_I6, CT_CAP_I1, CT_CAP_I2, CT_CAP_I3, CT_CAP_I4, CT_RESP_I1, CT_RESP_I2, CT_RESP_I3, CT_RESP_I4, CT_RESN_I1, CT_RESN_I2
+, CT_RESN_I3, CT_RESN_I4, M_EYE_I, RX_SEL_I1, RX_SEL_I2, RX_SEL_I3, RX_SEL_I4, RX_SEL_I5, RX_SEL_I6, PLL_RN_I, RST_N_I, CAL_1P_I1, CAL_1P_I2, CAL_1P_I3, CAL_1P_I4, CAL_1P_I5, CAL_1P_I6, CAL_1P_I7, CAL_1P_I8, CAL_2N_I1, CAL_2N_I2
+, CAL_2N_I3, CAL_2N_I4, CAL_2N_I5, CAL_2N_I6, CAL_2N_I7, CAL_2N_I8, CAL_3N_I1, CAL_3N_I2, CAL_3N_I3, CAL_3N_I4, CAL_3N_I5, CAL_3N_I6, CAL_3N_I7, CAL_3N_I8, CAL_4P_I1, CAL_4P_I2, CAL_4P_I3, CAL_4P_I4, CAL_4P_I5, CAL_4P_I6, CAL_4P_I7
+, CAL_4P_I8, CAL_SEL_I1, CAL_SEL_I2, CAL_SEL_I3, CAL_SEL_I4, CAL_E_I, LOCK_E_I, OVS_E_I, TST_I1, TST_I2, TST_I3, TST_I4, TST_I5, TST_I6, TST_I7, TST_I8, CLK_O, LOCK_O, CAL_O, TST_O1, TST_O2
+, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, CLK_EXT_I, LINK_TX1, LINK_TX2, LINK_TX3, LINK_TX4, LINK_TX5, LINK_RX0, LINK_RX1, LINK_RX2, LINK_RX3, LINK_RX4, LINK_RX5, LINK_TX0);
+    input CAL_1P_I1;
+    input CAL_1P_I2;
+    input CAL_1P_I3;
+    input CAL_1P_I4;
+    input CAL_1P_I5;
+    input CAL_1P_I6;
+    input CAL_1P_I7;
+    input CAL_1P_I8;
+    input CAL_2N_I1;
+    input CAL_2N_I2;
+    input CAL_2N_I3;
+    input CAL_2N_I4;
+    input CAL_2N_I5;
+    input CAL_2N_I6;
+    input CAL_2N_I7;
+    input CAL_2N_I8;
+    input CAL_3N_I1;
+    input CAL_3N_I2;
+    input CAL_3N_I3;
+    input CAL_3N_I4;
+    input CAL_3N_I5;
+    input CAL_3N_I6;
+    input CAL_3N_I7;
+    input CAL_3N_I8;
+    input CAL_4P_I1;
+    input CAL_4P_I2;
+    input CAL_4P_I3;
+    input CAL_4P_I4;
+    input CAL_4P_I5;
+    input CAL_4P_I6;
+    input CAL_4P_I7;
+    input CAL_4P_I8;
+    input CAL_E_I;
+    output CAL_O;
+    input CAL_SEL_I1;
+    input CAL_SEL_I2;
+    input CAL_SEL_I3;
+    input CAL_SEL_I4;
+    input CLK_EXT_I;
+    output CLK_O;
+    input CLK_REF_I;
+    input CLK_USER_I;
+    input CT_CAP_I1;
+    input CT_CAP_I2;
+    input CT_CAP_I3;
+    input CT_CAP_I4;
+    input CT_RESN_I1;
+    input CT_RESN_I2;
+    input CT_RESN_I3;
+    input CT_RESN_I4;
+    input CT_RESP_I1;
+    input CT_RESP_I2;
+    input CT_RESP_I3;
+    input CT_RESP_I4;
+    inout [9:0] LINK_RX0;
+    inout [9:0] LINK_RX1;
+    inout [9:0] LINK_RX2;
+    inout [9:0] LINK_RX3;
+    inout [9:0] LINK_RX4;
+    inout [9:0] LINK_RX5;
+    inout [19:0] LINK_TX0;
+    inout [19:0] LINK_TX1;
+    inout [19:0] LINK_TX2;
+    inout [19:0] LINK_TX3;
+    inout [19:0] LINK_TX4;
+    inout [19:0] LINK_TX5;
+    input LOCK_E_I;
+    output LOCK_O;
+    input MAIN_EN_I1;
+    input MAIN_EN_I2;
+    input MAIN_EN_I3;
+    input MAIN_EN_I4;
+    input MAIN_EN_I5;
+    input MAIN_EN_I6;
+    input MAIN_SG_I;
+    input MARG_ISV_I1;
+    input MARG_ISV_I2;
+    input MARG_ISV_I3;
+    input MARG_ISV_I4;
+    input MARG_ISV_I5;
+    input MARG_IS_I1;
+    input MARG_IS_I2;
+    input MARG_IS_I3;
+    input MARG_IS_I4;
+    input MARG_SV_I1;
+    input MARG_SV_I2;
+    input MARG_SV_I3;
+    input MARG_SV_I4;
+    input MARG_SV_I5;
+    input MARG_S_I1;
+    input MARG_S_I2;
+    input MARG_S_I3;
+    input MARG_S_I4;
+    input M_EYE_I;
+    input OVS_E_I;
+    input PLL_RN_I;
+    input POST_EN_I1;
+    input POST_EN_I2;
+    input POST_EN_I3;
+    input POST_EN_I4;
+    input POST_EN_I5;
+    input POST_ISV_I1;
+    input POST_ISV_I2;
+    input POST_ISV_I3;
+    input POST_ISV_I4;
+    input POST_IS_I1;
+    input POST_IS_I2;
+    input POST_IS_I3;
+    input POST_IS_I4;
+    input POST_SG_I;
+    input PRE_EN_I;
+    input PRE_IS_I1;
+    input PRE_IS_I2;
+    input PRE_IS_I3;
+    input PRE_IS_I4;
+    input PRE_SG_I;
+    input RST_N_I;
+    input RX_SEL_I1;
+    input RX_SEL_I2;
+    input RX_SEL_I3;
+    input RX_SEL_I4;
+    input RX_SEL_I5;
+    input RX_SEL_I6;
+    input TST_I1;
+    input TST_I2;
+    input TST_I3;
+    input TST_I4;
+    input TST_I5;
+    input TST_I6;
+    input TST_I7;
+    input TST_I8;
+    output TST_O1;
+    output TST_O2;
+    output TST_O3;
+    output TST_O4;
+    output TST_O5;
+    output TST_O6;
+    output TST_O7;
+    output TST_O8;
+    input TX_SEL_I1;
+    input TX_SEL_I2;
+    input TX_SEL_I3;
+    input TX_SEL_I4;
+    input TX_SEL_I5;
+    input TX_SEL_I6;
+    parameter location = "";
+    parameter main_clk_to_fabric_div_en = 1'b0;
+    parameter main_clk_to_fabric_div_mode = 1'b0;
+    parameter main_clk_to_fabric_sel = 1'b0;
+    parameter main_test = 8'b00000000;
+    parameter main_use_only_usr_clock = 1'b0;
+    parameter main_use_pcs_clk_2 = 1'b0;
+    parameter pcs_ovs_mode = 1'b0;
+    parameter pcs_pll_lock_count = 3'b000;
+    parameter pcs_word_len = 2'b00;
+    parameter pll_pma_cpump_n = 3'b000;
+    parameter pll_pma_divf = 2'b00;
+    parameter pll_pma_divf_en_n = 1'b0;
+    parameter pll_pma_divm = 2'b00;
+    parameter pll_pma_divm_en_n = 1'b0;
+    parameter pll_pma_divn = 1'b0;
+    parameter pll_pma_divn_en_n = 1'b0;
+    parameter pll_pma_int_data_len = 1'b0;
+    parameter pll_pma_lvds_mux = 1'b0;
+    parameter pll_pma_mux_ckref = 1'b0;
+    parameter rx_pma_half_step = 1'b0;
+endmodule
+
diff --git a/techlibs/nanoxplore/cells_bb_m.v b/techlibs/nanoxplore/cells_bb_m.v
index 0be57e720b1..620e9107d50 100644
--- a/techlibs/nanoxplore/cells_bb_m.v
+++ b/techlibs/nanoxplore/cells_bb_m.v
@@ -401,3 +401,831 @@ module NX_PLL(REF, FBK, VCO, D1, D2, D3, OSC, RDY);
     parameter vco_range = 0;
 endmodule
 
+(* blackbox *)
+module NX_WFG(SI, ZI, RDY, SO, ZO);
+    input RDY;
+    input SI;
+    output SO;
+    input ZI;
+    output ZO;
+    parameter delay = 0;
+    parameter delay_on = 1'b0;
+    parameter location = "";
+    parameter mode = 1'b0;
+    parameter pattern = 16'b0000000000000000;
+    parameter pattern_end = 1;
+    parameter wfg_edge = 1'b0;
+endmodule
+
+
+(* blackbox *)
+module NX_IOM(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, CCK, DCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1
+, C2RW2, C2RW3, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FZ, DC, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4
+, DRA5, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1, CAP2, CAP3
+, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3
+, DRO4, DRO5, DRO6, CAL, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EL, P1ER, P1EO, P1RI, P1RL, P1RR
+, P1RO1, P1RO2, P1RO3, P1RO4, P1RO5, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EL, P2ER, P2EO, P2RI, P2RL
+, P2RR, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P3CI1, P3CL, P3CR, P3CO, P3CTI, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EL, P3ER, P3EO, P3RI
+, P3RL, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EL, P4ER, P4EO
+, P4RI, P4RL, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P5CI1, P5CI2, P5CI3, P5CI4, P5CI5, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3
+, P5EI4, P5EI5, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P6CI1, P6CL, P6CR, P6CO, P6CTI, P6CTO, P6EI1, P6EI2
+, P6EI3, P6EI4, P6EI5, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1
+, P7EI2, P7EI3, P7EI4, P7EI5, P7EL, P7ER, P7EO, P7RI, P7RL, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO
+, P8EI1, P8EI2, P8EI3, P8EI4, P8EI5, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P9CI1, P9CL, P9CR, P9CO, P9CTI
+, P9CTO, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P10CI1, P10CL, P10CR, P10CO
+, P10CTI, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EL, P10ER, P10EO, P10RI, P10RL, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P11CI1, P11CL, P11CR
+, P11CO, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P12CI1, P12CL
+, P12CR, P12CO, P12CTI, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P13CI1
+, P13CL, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EL, P13ER, P13EO, P13RI, P13RL, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5
+, P14CI1, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4
+, P14RO5, P15CI1, P15CL, P15CR, P15CO, P15CTI, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3
+, P15RO4, P15RO5, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EL, P16ER, P16EO, P16RI, P16RL, P16RR, P16RO1, P16RO2
+, P16RO3, P16RO4, P16RO5, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1
+, P17RO2, P17RO3, P17RO4, P17RO5, P18CI1, P18CL, P18CR, P18CO, P18CTI, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR
+, P18RO1, P18RO2, P18RO3, P18RO4, P18RO5, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EL, P19ER, P19EO, P19RI, P19RL
+, P19RR, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EL, P20ER, P20EO, P20RI
+, P20RL, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P21CI1, P21CL, P21CR, P21CO, P21CTI, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EL, P21ER, P21EO
+, P21RI, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EL, P22ER
+, P22EO, P22RI, P22RL, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EL
+, P23ER, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P24CI1, P24CL, P24CR, P24CO, P24CTI, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5
+, P24EL, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P25CI1, P25CI2, P25CI3, P25CI4, P25CI5, P25CL, P25CR, P25CO, P25CTI, P25CTO
+, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5, P25EL, P25ER, P25EO, P25RI, P25RL, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P26CI1, P26CL, P26CR, P26CO, P26CTI
+, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4, P26EI5, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P27CI1, P27CL, P27CR, P27CO
+, P27CTI, P27CTO, P27EI1, P27EI2, P27EI3, P27EI4, P27EI5, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P28CI1, P28CL, P28CR
+, P28CO, P28CTI, P28CTO, P28EI1, P28EI2, P28EI3, P28EI4, P28EI5, P28EL, P28ER, P28EO, P28RI, P28RL, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P29CI1, P29CL
+, P29CR, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P30CI1
+, P30CL, P30CR, P30CO, P30CTI, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5
+);
+    output C1RED;
+    input C1RNE;
+    input C1RS;
+    input C1RW1;
+    input C1RW2;
+    input C1RW3;
+    input C1TS;
+    input C1TW;
+    output C2RED;
+    input C2RNE;
+    input C2RS;
+    input C2RW1;
+    input C2RW2;
+    input C2RW3;
+    input C2TS;
+    input C2TW;
+    input CAD1;
+    input CAD2;
+    input CAD3;
+    input CAD4;
+    input CAD5;
+    input CAD6;
+    output CAL;
+    input CAN1;
+    input CAN2;
+    input CAN3;
+    input CAN4;
+    input CAP1;
+    input CAP2;
+    input CAP3;
+    input CAP4;
+    input CAT1;
+    input CAT2;
+    input CAT3;
+    input CAT4;
+    input CCK;
+    output CKO1;
+    output CKO2;
+    input CTCK;
+    input DC;
+    input DCK;
+    input DIG;
+    input DIS;
+    input DOG;
+    input DOS;
+    input DPAG;
+    input DPAS;
+    input DQSG;
+    input DQSS;
+    input DRA1;
+    input DRA2;
+    input DRA3;
+    input DRA4;
+    input DRA5;
+    input DRI1;
+    input DRI2;
+    input DRI3;
+    input DRI4;
+    input DRI5;
+    input DRI6;
+    input DRL;
+    output DRO1;
+    output DRO2;
+    output DRO3;
+    output DRO4;
+    output DRO5;
+    output DRO6;
+    input DS1;
+    input DS2;
+    input FA1;
+    input FA2;
+    input FA3;
+    input FA4;
+    input FA5;
+    output FLD;
+    output FLG;
+    input FZ;
+    input P10CI1;
+    input P10CL;
+    output P10CO;
+    input P10CR;
+    input P10CTI;
+    output P10CTO;
+    input P10EI1;
+    input P10EI2;
+    input P10EI3;
+    input P10EI4;
+    input P10EI5;
+    input P10EL;
+    output P10EO;
+    input P10ER;
+    input P10RI;
+    input P10RL;
+    output P10RO1;
+    output P10RO2;
+    output P10RO3;
+    output P10RO4;
+    output P10RO5;
+    input P10RR;
+    input P11CI1;
+    input P11CL;
+    output P11CO;
+    input P11CR;
+    input P11CTI;
+    output P11CTO;
+    input P11EI1;
+    input P11EI2;
+    input P11EI3;
+    input P11EI4;
+    input P11EI5;
+    input P11EL;
+    output P11EO;
+    input P11ER;
+    input P11RI;
+    input P11RL;
+    output P11RO1;
+    output P11RO2;
+    output P11RO3;
+    output P11RO4;
+    output P11RO5;
+    input P11RR;
+    input P12CI1;
+    input P12CL;
+    output P12CO;
+    input P12CR;
+    input P12CTI;
+    output P12CTO;
+    input P12EI1;
+    input P12EI2;
+    input P12EI3;
+    input P12EI4;
+    input P12EI5;
+    input P12EL;
+    output P12EO;
+    input P12ER;
+    input P12RI;
+    input P12RL;
+    output P12RO1;
+    output P12RO2;
+    output P12RO3;
+    output P12RO4;
+    output P12RO5;
+    input P12RR;
+    input P13CI1;
+    input P13CL;
+    output P13CO;
+    input P13CR;
+    input P13CTI;
+    output P13CTO;
+    input P13EI1;
+    input P13EI2;
+    input P13EI3;
+    input P13EI4;
+    input P13EI5;
+    input P13EL;
+    output P13EO;
+    input P13ER;
+    input P13RI;
+    input P13RL;
+    output P13RO1;
+    output P13RO2;
+    output P13RO3;
+    output P13RO4;
+    output P13RO5;
+    input P13RR;
+    input P14CI1;
+    input P14CL;
+    output P14CO;
+    input P14CR;
+    input P14CTI;
+    output P14CTO;
+    input P14EI1;
+    input P14EI2;
+    input P14EI3;
+    input P14EI4;
+    input P14EI5;
+    input P14EL;
+    output P14EO;
+    input P14ER;
+    input P14RI;
+    input P14RL;
+    output P14RO1;
+    output P14RO2;
+    output P14RO3;
+    output P14RO4;
+    output P14RO5;
+    input P14RR;
+    input P15CI1;
+    input P15CL;
+    output P15CO;
+    input P15CR;
+    input P15CTI;
+    output P15CTO;
+    input P15EI1;
+    input P15EI2;
+    input P15EI3;
+    input P15EI4;
+    input P15EI5;
+    input P15EL;
+    output P15EO;
+    input P15ER;
+    input P15RI;
+    input P15RL;
+    output P15RO1;
+    output P15RO2;
+    output P15RO3;
+    output P15RO4;
+    output P15RO5;
+    input P15RR;
+    input P16CI1;
+    input P16CL;
+    output P16CO;
+    input P16CR;
+    input P16CTI;
+    output P16CTO;
+    input P16EI1;
+    input P16EI2;
+    input P16EI3;
+    input P16EI4;
+    input P16EI5;
+    input P16EL;
+    output P16EO;
+    input P16ER;
+    input P16RI;
+    input P16RL;
+    output P16RO1;
+    output P16RO2;
+    output P16RO3;
+    output P16RO4;
+    output P16RO5;
+    input P16RR;
+    input P17CI1;
+    input P17CL;
+    output P17CO;
+    input P17CR;
+    input P17CTI;
+    output P17CTO;
+    input P17EI1;
+    input P17EI2;
+    input P17EI3;
+    input P17EI4;
+    input P17EI5;
+    input P17EL;
+    output P17EO;
+    input P17ER;
+    input P17RI;
+    input P17RL;
+    output P17RO1;
+    output P17RO2;
+    output P17RO3;
+    output P17RO4;
+    output P17RO5;
+    input P17RR;
+    input P18CI1;
+    input P18CL;
+    output P18CO;
+    input P18CR;
+    input P18CTI;
+    output P18CTO;
+    input P18EI1;
+    input P18EI2;
+    input P18EI3;
+    input P18EI4;
+    input P18EI5;
+    input P18EL;
+    output P18EO;
+    input P18ER;
+    input P18RI;
+    input P18RL;
+    output P18RO1;
+    output P18RO2;
+    output P18RO3;
+    output P18RO4;
+    output P18RO5;
+    input P18RR;
+    input P19CI1;
+    input P19CL;
+    output P19CO;
+    input P19CR;
+    input P19CTI;
+    output P19CTO;
+    input P19EI1;
+    input P19EI2;
+    input P19EI3;
+    input P19EI4;
+    input P19EI5;
+    input P19EL;
+    output P19EO;
+    input P19ER;
+    input P19RI;
+    input P19RL;
+    output P19RO1;
+    output P19RO2;
+    output P19RO3;
+    output P19RO4;
+    output P19RO5;
+    input P19RR;
+    input P1CI1;
+    input P1CL;
+    output P1CO;
+    input P1CR;
+    input P1CTI;
+    output P1CTO;
+    input P1EI1;
+    input P1EI2;
+    input P1EI3;
+    input P1EI4;
+    input P1EI5;
+    input P1EL;
+    output P1EO;
+    input P1ER;
+    input P1RI;
+    input P1RL;
+    output P1RO1;
+    output P1RO2;
+    output P1RO3;
+    output P1RO4;
+    output P1RO5;
+    input P1RR;
+    input P20CI1;
+    input P20CL;
+    output P20CO;
+    input P20CR;
+    input P20CTI;
+    output P20CTO;
+    input P20EI1;
+    input P20EI2;
+    input P20EI3;
+    input P20EI4;
+    input P20EI5;
+    input P20EL;
+    output P20EO;
+    input P20ER;
+    input P20RI;
+    input P20RL;
+    output P20RO1;
+    output P20RO2;
+    output P20RO3;
+    output P20RO4;
+    output P20RO5;
+    input P20RR;
+    input P21CI1;
+    input P21CL;
+    output P21CO;
+    input P21CR;
+    input P21CTI;
+    output P21CTO;
+    input P21EI1;
+    input P21EI2;
+    input P21EI3;
+    input P21EI4;
+    input P21EI5;
+    input P21EL;
+    output P21EO;
+    input P21ER;
+    input P21RI;
+    input P21RL;
+    output P21RO1;
+    output P21RO2;
+    output P21RO3;
+    output P21RO4;
+    output P21RO5;
+    input P21RR;
+    input P22CI1;
+    input P22CL;
+    output P22CO;
+    input P22CR;
+    input P22CTI;
+    output P22CTO;
+    input P22EI1;
+    input P22EI2;
+    input P22EI3;
+    input P22EI4;
+    input P22EI5;
+    input P22EL;
+    output P22EO;
+    input P22ER;
+    input P22RI;
+    input P22RL;
+    output P22RO1;
+    output P22RO2;
+    output P22RO3;
+    output P22RO4;
+    output P22RO5;
+    input P22RR;
+    input P23CI1;
+    input P23CL;
+    output P23CO;
+    input P23CR;
+    input P23CTI;
+    output P23CTO;
+    input P23EI1;
+    input P23EI2;
+    input P23EI3;
+    input P23EI4;
+    input P23EI5;
+    input P23EL;
+    output P23EO;
+    input P23ER;
+    input P23RI;
+    input P23RL;
+    output P23RO1;
+    output P23RO2;
+    output P23RO3;
+    output P23RO4;
+    output P23RO5;
+    input P23RR;
+    input P24CI1;
+    input P24CL;
+    output P24CO;
+    input P24CR;
+    input P24CTI;
+    output P24CTO;
+    input P24EI1;
+    input P24EI2;
+    input P24EI3;
+    input P24EI4;
+    input P24EI5;
+    input P24EL;
+    output P24EO;
+    input P24ER;
+    input P24RI;
+    input P24RL;
+    output P24RO1;
+    output P24RO2;
+    output P24RO3;
+    output P24RO4;
+    output P24RO5;
+    input P24RR;
+    input P25CI1;
+    input P25CI2;
+    input P25CI3;
+    input P25CI4;
+    input P25CI5;
+    input P25CL;
+    output P25CO;
+    input P25CR;
+    input P25CTI;
+    output P25CTO;
+    input P25EI1;
+    input P25EI2;
+    input P25EI3;
+    input P25EI4;
+    input P25EI5;
+    input P25EL;
+    output P25EO;
+    input P25ER;
+    input P25RI;
+    input P25RL;
+    output P25RO1;
+    output P25RO2;
+    output P25RO3;
+    output P25RO4;
+    output P25RO5;
+    input P25RR;
+    input P26CI1;
+    input P26CL;
+    output P26CO;
+    input P26CR;
+    input P26CTI;
+    output P26CTO;
+    input P26EI1;
+    input P26EI2;
+    input P26EI3;
+    input P26EI4;
+    input P26EI5;
+    input P26EL;
+    output P26EO;
+    input P26ER;
+    input P26RI;
+    input P26RL;
+    output P26RO1;
+    output P26RO2;
+    output P26RO3;
+    output P26RO4;
+    output P26RO5;
+    input P26RR;
+    input P27CI1;
+    input P27CL;
+    output P27CO;
+    input P27CR;
+    input P27CTI;
+    output P27CTO;
+    input P27EI1;
+    input P27EI2;
+    input P27EI3;
+    input P27EI4;
+    input P27EI5;
+    input P27EL;
+    output P27EO;
+    input P27ER;
+    input P27RI;
+    input P27RL;
+    output P27RO1;
+    output P27RO2;
+    output P27RO3;
+    output P27RO4;
+    output P27RO5;
+    input P27RR;
+    input P28CI1;
+    input P28CL;
+    output P28CO;
+    input P28CR;
+    input P28CTI;
+    output P28CTO;
+    input P28EI1;
+    input P28EI2;
+    input P28EI3;
+    input P28EI4;
+    input P28EI5;
+    input P28EL;
+    output P28EO;
+    input P28ER;
+    input P28RI;
+    input P28RL;
+    output P28RO1;
+    output P28RO2;
+    output P28RO3;
+    output P28RO4;
+    output P28RO5;
+    input P28RR;
+    input P29CI1;
+    input P29CL;
+    output P29CO;
+    input P29CR;
+    input P29CTI;
+    output P29CTO;
+    input P29EI1;
+    input P29EI2;
+    input P29EI3;
+    input P29EI4;
+    input P29EI5;
+    input P29EL;
+    output P29EO;
+    input P29ER;
+    input P29RI;
+    input P29RL;
+    output P29RO1;
+    output P29RO2;
+    output P29RO3;
+    output P29RO4;
+    output P29RO5;
+    input P29RR;
+    input P2CI1;
+    input P2CL;
+    output P2CO;
+    input P2CR;
+    input P2CTI;
+    output P2CTO;
+    input P2EI1;
+    input P2EI2;
+    input P2EI3;
+    input P2EI4;
+    input P2EI5;
+    input P2EL;
+    output P2EO;
+    input P2ER;
+    input P2RI;
+    input P2RL;
+    output P2RO1;
+    output P2RO2;
+    output P2RO3;
+    output P2RO4;
+    output P2RO5;
+    input P2RR;
+    input P30CI1;
+    input P30CL;
+    output P30CO;
+    input P30CR;
+    input P30CTI;
+    output P30CTO;
+    input P30EI1;
+    input P30EI2;
+    input P30EI3;
+    input P30EI4;
+    input P30EI5;
+    input P30EL;
+    output P30EO;
+    input P30ER;
+    input P30RI;
+    input P30RL;
+    output P30RO1;
+    output P30RO2;
+    output P30RO3;
+    output P30RO4;
+    output P30RO5;
+    input P30RR;
+    input P3CI1;
+    input P3CL;
+    output P3CO;
+    input P3CR;
+    input P3CTI;
+    output P3CTO;
+    input P3EI1;
+    input P3EI2;
+    input P3EI3;
+    input P3EI4;
+    input P3EI5;
+    input P3EL;
+    output P3EO;
+    input P3ER;
+    input P3RI;
+    input P3RL;
+    output P3RO1;
+    output P3RO2;
+    output P3RO3;
+    output P3RO4;
+    output P3RO5;
+    input P3RR;
+    input P4CI1;
+    input P4CL;
+    output P4CO;
+    input P4CR;
+    input P4CTI;
+    output P4CTO;
+    input P4EI1;
+    input P4EI2;
+    input P4EI3;
+    input P4EI4;
+    input P4EI5;
+    input P4EL;
+    output P4EO;
+    input P4ER;
+    input P4RI;
+    input P4RL;
+    output P4RO1;
+    output P4RO2;
+    output P4RO3;
+    output P4RO4;
+    output P4RO5;
+    input P4RR;
+    input P5CI1;
+    input P5CI2;
+    input P5CI3;
+    input P5CI4;
+    input P5CI5;
+    input P5CL;
+    output P5CO;
+    input P5CR;
+    input P5CTI;
+    output P5CTO;
+    input P5EI1;
+    input P5EI2;
+    input P5EI3;
+    input P5EI4;
+    input P5EI5;
+    input P5EL;
+    output P5EO;
+    input P5ER;
+    input P5RI;
+    input P5RL;
+    output P5RO1;
+    output P5RO2;
+    output P5RO3;
+    output P5RO4;
+    output P5RO5;
+    input P5RR;
+    input P6CI1;
+    input P6CL;
+    output P6CO;
+    input P6CR;
+    input P6CTI;
+    output P6CTO;
+    input P6EI1;
+    input P6EI2;
+    input P6EI3;
+    input P6EI4;
+    input P6EI5;
+    input P6EL;
+    output P6EO;
+    input P6ER;
+    input P6RI;
+    input P6RL;
+    output P6RO1;
+    output P6RO2;
+    output P6RO3;
+    output P6RO4;
+    output P6RO5;
+    input P6RR;
+    input P7CI1;
+    input P7CL;
+    output P7CO;
+    input P7CR;
+    input P7CTI;
+    output P7CTO;
+    input P7EI1;
+    input P7EI2;
+    input P7EI3;
+    input P7EI4;
+    input P7EI5;
+    input P7EL;
+    output P7EO;
+    input P7ER;
+    input P7RI;
+    input P7RL;
+    output P7RO1;
+    output P7RO2;
+    output P7RO3;
+    output P7RO4;
+    output P7RO5;
+    input P7RR;
+    input P8CI1;
+    input P8CL;
+    output P8CO;
+    input P8CR;
+    input P8CTI;
+    output P8CTO;
+    input P8EI1;
+    input P8EI2;
+    input P8EI3;
+    input P8EI4;
+    input P8EI5;
+    input P8EL;
+    output P8EO;
+    input P8ER;
+    input P8RI;
+    input P8RL;
+    output P8RO1;
+    output P8RO2;
+    output P8RO3;
+    output P8RO4;
+    output P8RO5;
+    input P8RR;
+    input P9CI1;
+    input P9CL;
+    output P9CO;
+    input P9CR;
+    input P9CTI;
+    output P9CTO;
+    input P9EI1;
+    input P9EI2;
+    input P9EI3;
+    input P9EI4;
+    input P9EI5;
+    input P9EL;
+    output P9EO;
+    input P9ER;
+    input P9RI;
+    input P9RL;
+    output P9RO1;
+    output P9RO2;
+    output P9RO3;
+    output P9RO4;
+    output P9RO5;
+    input P9RR;
+    input RRCK1;
+    input RRCK2;
+    input RTCK1;
+    input RTCK2;
+    input SPI1;
+    input SPI2;
+    input SPI3;
+    input WRCK1;
+    input WRCK2;
+    input WTCK1;
+    input WTCK2;
+    parameter div_rx1 = 4'b0000;
+    parameter div_rx2 = 4'b0000;
+    parameter div_tx1 = 4'b0000;
+    parameter div_tx2 = 4'b0000;
+    parameter mode_io_cal = 1'b0;
+    parameter mode_side1 = 0;
+    parameter mode_side2 = 0;
+    parameter pads_dict = "";
+    parameter pads_path = "";
+    parameter sel_clk_out1 = 1'b0;
+    parameter sel_clk_out2 = 1'b0;
+    parameter sel_clkr_rx1 = 1'b0;
+    parameter sel_clkr_rx2 = 1'b0;
+    parameter sel_clkw_rx1 = 2'b00;
+    parameter sel_clkw_rx2 = 2'b00;
+endmodule
+
diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v
index 988ddb4c516..2bcaa532691 100644
--- a/techlibs/nanoxplore/cells_bb_u.v
+++ b/techlibs/nanoxplore/cells_bb_u.v
@@ -549,3 +549,1803 @@ module NX_PLL_U(R, REF, FBK, OSC, VCO, LDFO, REFO, CLK_DIV1, CLK_DIV2, CLK_DIV3,
     parameter use_cal = 1'b0;
     parameter use_pll = 1'b1;
 endmodule
+
+(* blackbox *)
+module NX_WFG_U(R, SI, ZI, SO, ZO);
+    input R;
+    input SI;
+    output SO;
+    input ZI;
+    output ZO;
+    parameter delay = 0;
+    parameter delay_on = 1'b0;
+    parameter div_phase = 1'b0;
+    parameter div_ratio = 0;
+    parameter location = "";
+    parameter mode = 0;
+    parameter pattern = 16'b0000000000000000;
+    parameter pattern_end = 0;
+    parameter reset_on_cal_lock_n = 1'b0;
+    parameter reset_on_pll_lock_n = 1'b0;
+    parameter reset_on_pll_locka_n = 1'b0;
+    parameter wfg_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_XCDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, CSRSTI, CDRSTI, CSRSTO, CDRSTO, DSRSTI, DDRSTI, DSRSTO, DDRSTO, BI, CI, CO
+, AO, BO, AI, DI, DO);
+    input ADRSTI;
+    output ADRSTO;
+    input [5:0] AI;
+    output [5:0] AO;
+    input ASRSTI;
+    output ASRSTO;
+    input BDRSTI;
+    output BDRSTO;
+    input [5:0] BI;
+    output [5:0] BO;
+    input BSRSTI;
+    output BSRSTO;
+    input CDRSTI;
+    output CDRSTO;
+    input [5:0] CI;
+    input CK1;
+    input CK2;
+    output [5:0] CO;
+    input CSRSTI;
+    output CSRSTO;
+    input DDRSTI;
+    output DDRSTO;
+    input [5:0] DI;
+    output [5:0] DO;
+    input DSRSTI;
+    output DSRSTO;
+    parameter ack_sel = 1'b0;
+    parameter bck_sel = 1'b0;
+    parameter cck_sel = 1'b0;
+    parameter ck0_edge = 1'b0;
+    parameter ck1_edge = 1'b0;
+    parameter dck_sel = 1'b0;
+    parameter link_BA = 1'b0;
+    parameter link_CB = 1'b0;
+    parameter link_DC = 1'b0;
+    parameter use_adest_arst = 1'b0;
+    parameter use_asrc_arst = 1'b0;
+    parameter use_bdest_arst = 1'b0;
+    parameter use_bsrc_arst = 1'b0;
+    parameter use_cdest_arst = 1'b0;
+    parameter use_csrc_arst = 1'b0;
+    parameter use_ddest_arst = 1'b0;
+    parameter use_dsrc_arst = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_CRX_U(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, RST_N_I, PMA_RSTN_I, MEYE_RST_I, PWDN_N_I, DBG_S_I1, DBG_S_I2, DBG_S_I3, DATA_O1, DATA_O2, DATA_O3, DATA_O4, DATA_O5, DATA_O6
+, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24, DATA_O25, DATA_O26, DATA_O27
+, DATA_O28, DATA_O29, DATA_O30, DATA_O31, DATA_O32, DATA_O33, DATA_O34, DATA_O35, DATA_O36, DATA_O37, DATA_O38, DATA_O39, DATA_O40, DATA_O41, DATA_O42, DATA_O43, DATA_O44, DATA_O45, DATA_O46, DATA_O47, DATA_O48
+, DATA_O49, DATA_O50, DATA_O51, DATA_O52, DATA_O53, DATA_O54, DATA_O55, DATA_O56, DATA_O57, DATA_O58, DATA_O59, DATA_O60, DATA_O61, DATA_O62, DATA_O63, DATA_O64, CH_COM_O1, CH_COM_O2, CH_COM_O3, CH_COM_O4, CH_COM_O5
+, CH_COM_O6, CH_COM_O7, CH_COM_O8, CH_K_O1, CH_K_O2, CH_K_O3, CH_K_O4, CH_K_O5, CH_K_O6, CH_K_O7, CH_K_O8, NIT_O1, NIT_O2, NIT_O3, NIT_O4, NIT_O5, NIT_O6, NIT_O7, NIT_O8, D_ERR_O1, D_ERR_O2
+, D_ERR_O3, D_ERR_O4, D_ERR_O5, D_ERR_O6, D_ERR_O7, D_ERR_O8, CH_A_O1, CH_A_O2, CH_A_O3, CH_A_O4, CH_A_O5, CH_A_O6, CH_A_O7, CH_A_O8, CH_F_O1, CH_F_O2, CH_F_O3, CH_F_O4, CH_F_O5, CH_F_O6, CH_F_O7
+, CH_F_O8, ALIGN_O, VREALIGN_O, BUSY_O, TST_O1, TST_O2, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, LOS_O, LL_FLOCK_O, LL_SLOCK_O, PLL_LOCK_O, PLL_LOCKT_O, LINK);
+    input ALIGN_E_I;
+    output ALIGN_O;
+    input ALIGN_S_I;
+    input BUF_R_I;
+    output BUSY_O;
+    output CH_A_O1;
+    output CH_A_O2;
+    output CH_A_O3;
+    output CH_A_O4;
+    output CH_A_O5;
+    output CH_A_O6;
+    output CH_A_O7;
+    output CH_A_O8;
+    output CH_COM_O1;
+    output CH_COM_O2;
+    output CH_COM_O3;
+    output CH_COM_O4;
+    output CH_COM_O5;
+    output CH_COM_O6;
+    output CH_COM_O7;
+    output CH_COM_O8;
+    output CH_F_O1;
+    output CH_F_O2;
+    output CH_F_O3;
+    output CH_F_O4;
+    output CH_F_O5;
+    output CH_F_O6;
+    output CH_F_O7;
+    output CH_F_O8;
+    output CH_K_O1;
+    output CH_K_O2;
+    output CH_K_O3;
+    output CH_K_O4;
+    output CH_K_O5;
+    output CH_K_O6;
+    output CH_K_O7;
+    output CH_K_O8;
+    output DATA_O1;
+    output DATA_O10;
+    output DATA_O11;
+    output DATA_O12;
+    output DATA_O13;
+    output DATA_O14;
+    output DATA_O15;
+    output DATA_O16;
+    output DATA_O17;
+    output DATA_O18;
+    output DATA_O19;
+    output DATA_O2;
+    output DATA_O20;
+    output DATA_O21;
+    output DATA_O22;
+    output DATA_O23;
+    output DATA_O24;
+    output DATA_O25;
+    output DATA_O26;
+    output DATA_O27;
+    output DATA_O28;
+    output DATA_O29;
+    output DATA_O3;
+    output DATA_O30;
+    output DATA_O31;
+    output DATA_O32;
+    output DATA_O33;
+    output DATA_O34;
+    output DATA_O35;
+    output DATA_O36;
+    output DATA_O37;
+    output DATA_O38;
+    output DATA_O39;
+    output DATA_O4;
+    output DATA_O40;
+    output DATA_O41;
+    output DATA_O42;
+    output DATA_O43;
+    output DATA_O44;
+    output DATA_O45;
+    output DATA_O46;
+    output DATA_O47;
+    output DATA_O48;
+    output DATA_O49;
+    output DATA_O5;
+    output DATA_O50;
+    output DATA_O51;
+    output DATA_O52;
+    output DATA_O53;
+    output DATA_O54;
+    output DATA_O55;
+    output DATA_O56;
+    output DATA_O57;
+    output DATA_O58;
+    output DATA_O59;
+    output DATA_O6;
+    output DATA_O60;
+    output DATA_O61;
+    output DATA_O62;
+    output DATA_O63;
+    output DATA_O64;
+    output DATA_O7;
+    output DATA_O8;
+    output DATA_O9;
+    input DBG_S_I1;
+    input DBG_S_I2;
+    input DBG_S_I3;
+    input DEC_E_I;
+    input DSCR_E_I;
+    output D_ERR_O1;
+    output D_ERR_O2;
+    output D_ERR_O3;
+    output D_ERR_O4;
+    output D_ERR_O5;
+    output D_ERR_O6;
+    output D_ERR_O7;
+    output D_ERR_O8;
+    inout [9:0] LINK;
+    output LL_FLOCK_O;
+    output LL_SLOCK_O;
+    output LOS_O;
+    input MEYE_RST_I;
+    output NIT_O1;
+    output NIT_O2;
+    output NIT_O3;
+    output NIT_O4;
+    output NIT_O5;
+    output NIT_O6;
+    output NIT_O7;
+    output NIT_O8;
+    input OVS_BS_I1;
+    input OVS_BS_I2;
+    output PLL_LOCKT_O;
+    output PLL_LOCK_O;
+    input PMA_RSTN_I;
+    input PWDN_N_I;
+    input REP_E_I;
+    input RST_N_I;
+    output TST_O1;
+    output TST_O2;
+    output TST_O3;
+    output TST_O4;
+    output TST_O5;
+    output TST_O6;
+    output TST_O7;
+    output TST_O8;
+    output VREALIGN_O;
+    parameter gearbox_en = 1'b0;
+    parameter gearbox_mode = 1'b0;
+    parameter location = "";
+    parameter pcs_8b_dscr_sel = 1'b0;
+    parameter pcs_align_bypass = 1'b0;
+    parameter pcs_buffers_bypass = 1'b0;
+    parameter pcs_buffers_use_cdc = 1'b0;
+    parameter pcs_bypass_pma_cdc = 1'b0;
+    parameter pcs_bypass_usr_cdc = 1'b0;
+    parameter pcs_comma_mask = 10'b0000000000;
+    parameter pcs_debug_en = 1'b0;
+    parameter pcs_dec_bypass = 1'b0;
+    parameter pcs_dscr_bypass = 1'b0;
+    parameter pcs_el_buff_diff_bef_comp = 4'b0000;
+    parameter pcs_el_buff_max_comp = 4'b0000;
+    parameter pcs_el_buff_only_one_skp = 1'b0;
+    parameter pcs_el_buff_skp_char_0 = 9'b000000000;
+    parameter pcs_el_buff_skp_char_1 = 9'b000000000;
+    parameter pcs_el_buff_skp_char_2 = 9'b000000000;
+    parameter pcs_el_buff_skp_char_3 = 9'b000000000;
+    parameter pcs_el_buff_skp_header_0 = 9'b000000000;
+    parameter pcs_el_buff_skp_header_1 = 9'b000000000;
+    parameter pcs_el_buff_skp_header_2 = 9'b000000000;
+    parameter pcs_el_buff_skp_header_3 = 9'b000000000;
+    parameter pcs_el_buff_skp_header_size = 2'b00;
+    parameter pcs_el_buff_skp_seq_size = 2'b00;
+    parameter pcs_fsm_sel = 2'b00;
+    parameter pcs_fsm_watchdog_en = 1'b0;
+    parameter pcs_loopback = 1'b0;
+    parameter pcs_m_comma_en = 1'b0;
+    parameter pcs_m_comma_val = 10'b0000000000;
+    parameter pcs_nb_comma_bef_realign = 2'b00;
+    parameter pcs_p_comma_en = 1'b0;
+    parameter pcs_p_comma_val = 10'b0000000000;
+    parameter pcs_polarity = 1'b0;
+    parameter pcs_protocol_size = 1'b0;
+    parameter pcs_replace_bypass = 1'b0;
+    parameter pcs_sync_supported = 1'b0;
+    parameter pma_cdr_cp = 4'b0000;
+    parameter pma_clk_pos = 1'b0;
+    parameter pma_coarse_ppm = 3'b000;
+    parameter pma_ctrl_term = 6'b000000;
+    parameter pma_dco_divl = 2'b00;
+    parameter pma_dco_divm = 1'b0;
+    parameter pma_dco_divn = 2'b00;
+    parameter pma_dco_reg_res = 2'b00;
+    parameter pma_dco_vref_sel = 1'b0;
+    parameter pma_fine_ppm = 3'b000;
+    parameter pma_loopback = 1'b0;
+    parameter pma_m_eye_ppm = 3'b000;
+    parameter pma_peak_detect_cmd = 2'b00;
+    parameter pma_peak_detect_on = 1'b0;
+    parameter pma_pll_cpump_n = 3'b000;
+    parameter pma_pll_divf = 2'b00;
+    parameter pma_pll_divf_en_n = 1'b0;
+    parameter pma_pll_divm = 2'b00;
+    parameter pma_pll_divm_en_n = 1'b0;
+    parameter pma_pll_divn = 1'b0;
+    parameter pma_pll_divn_en_n = 1'b0;
+endmodule
+
+
+(* blackbox *)
+module NX_CTX_U(ENC_E_I1, ENC_E_I2, ENC_E_I3, ENC_E_I4, ENC_E_I5, ENC_E_I6, ENC_E_I7, ENC_E_I8, CH_K_I1, CH_K_I2, CH_K_I3, CH_K_I4, CH_K_I5, CH_K_I6, CH_K_I7, CH_K_I8, SCR_E_I1, SCR_E_I2, SCR_E_I3, SCR_E_I4, SCR_E_I5
+, SCR_E_I6, SCR_E_I7, SCR_E_I8, EOMF_I1, EOMF_I2, EOMF_I3, EOMF_I4, EOMF_I5, EOMF_I6, EOMF_I7, EOMF_I8, EOF_I1, EOF_I2, EOF_I3, EOF_I4, EOF_I5, EOF_I6, EOF_I7, EOF_I8, REP_E_I, RST_N_I
+, DATA_I1, DATA_I2, DATA_I3, DATA_I4, DATA_I5, DATA_I6, DATA_I7, DATA_I8, DATA_I9, DATA_I10, DATA_I11, DATA_I12, DATA_I13, DATA_I14, DATA_I15, DATA_I16, DATA_I17, DATA_I18, DATA_I19, DATA_I20, DATA_I21
+, DATA_I22, DATA_I23, DATA_I24, DATA_I25, DATA_I26, DATA_I27, DATA_I28, DATA_I29, DATA_I30, DATA_I31, DATA_I32, DATA_I33, DATA_I34, DATA_I35, DATA_I36, DATA_I37, DATA_I38, DATA_I39, DATA_I40, DATA_I41, DATA_I42
+, DATA_I43, DATA_I44, DATA_I45, DATA_I46, DATA_I47, DATA_I48, DATA_I49, DATA_I50, DATA_I51, DATA_I52, DATA_I53, DATA_I54, DATA_I55, DATA_I56, DATA_I57, DATA_I58, DATA_I59, DATA_I60, DATA_I61, DATA_I62, DATA_I63
+, DATA_I64, BUSY_O, INV_K_O, PWDN_N_I, CLK_E_I, CLK_O, LINK);
+    output BUSY_O;
+    input CH_K_I1;
+    input CH_K_I2;
+    input CH_K_I3;
+    input CH_K_I4;
+    input CH_K_I5;
+    input CH_K_I6;
+    input CH_K_I7;
+    input CH_K_I8;
+    input CLK_E_I;
+    output CLK_O;
+    input DATA_I1;
+    input DATA_I10;
+    input DATA_I11;
+    input DATA_I12;
+    input DATA_I13;
+    input DATA_I14;
+    input DATA_I15;
+    input DATA_I16;
+    input DATA_I17;
+    input DATA_I18;
+    input DATA_I19;
+    input DATA_I2;
+    input DATA_I20;
+    input DATA_I21;
+    input DATA_I22;
+    input DATA_I23;
+    input DATA_I24;
+    input DATA_I25;
+    input DATA_I26;
+    input DATA_I27;
+    input DATA_I28;
+    input DATA_I29;
+    input DATA_I3;
+    input DATA_I30;
+    input DATA_I31;
+    input DATA_I32;
+    input DATA_I33;
+    input DATA_I34;
+    input DATA_I35;
+    input DATA_I36;
+    input DATA_I37;
+    input DATA_I38;
+    input DATA_I39;
+    input DATA_I4;
+    input DATA_I40;
+    input DATA_I41;
+    input DATA_I42;
+    input DATA_I43;
+    input DATA_I44;
+    input DATA_I45;
+    input DATA_I46;
+    input DATA_I47;
+    input DATA_I48;
+    input DATA_I49;
+    input DATA_I5;
+    input DATA_I50;
+    input DATA_I51;
+    input DATA_I52;
+    input DATA_I53;
+    input DATA_I54;
+    input DATA_I55;
+    input DATA_I56;
+    input DATA_I57;
+    input DATA_I58;
+    input DATA_I59;
+    input DATA_I6;
+    input DATA_I60;
+    input DATA_I61;
+    input DATA_I62;
+    input DATA_I63;
+    input DATA_I64;
+    input DATA_I7;
+    input DATA_I8;
+    input DATA_I9;
+    input ENC_E_I1;
+    input ENC_E_I2;
+    input ENC_E_I3;
+    input ENC_E_I4;
+    input ENC_E_I5;
+    input ENC_E_I6;
+    input ENC_E_I7;
+    input ENC_E_I8;
+    input EOF_I1;
+    input EOF_I2;
+    input EOF_I3;
+    input EOF_I4;
+    input EOF_I5;
+    input EOF_I6;
+    input EOF_I7;
+    input EOF_I8;
+    input EOMF_I1;
+    input EOMF_I2;
+    input EOMF_I3;
+    input EOMF_I4;
+    input EOMF_I5;
+    input EOMF_I6;
+    input EOMF_I7;
+    input EOMF_I8;
+    output INV_K_O;
+    inout [19:0] LINK;
+    input PWDN_N_I;
+    input REP_E_I;
+    input RST_N_I;
+    input SCR_E_I1;
+    input SCR_E_I2;
+    input SCR_E_I3;
+    input SCR_E_I4;
+    input SCR_E_I5;
+    input SCR_E_I6;
+    input SCR_E_I7;
+    input SCR_E_I8;
+    parameter gearbox_en = 1'b0;
+    parameter gearbox_mode = 1'b0;
+    parameter location = "";
+    parameter pcs_8b_scr_sel = 1'b0;
+    parameter pcs_bypass_pma_cdc = 1'b0;
+    parameter pcs_bypass_usr_cdc = 1'b0;
+    parameter pcs_enc_bypass = 1'b0;
+    parameter pcs_esistream_fsm_en = 1'b0;
+    parameter pcs_loopback = 1'b0;
+    parameter pcs_polarity = 1'b0;
+    parameter pcs_protocol_size = 1'b0;
+    parameter pcs_replace_bypass = 1'b0;
+    parameter pcs_scr_bypass = 1'b0;
+    parameter pcs_scr_init = 17'b00000000000000000;
+    parameter pcs_sync_supported = 1'b0;
+    parameter pma_clk_pos = 1'b0;
+    parameter pma_loopback = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_IOM_U(ALCK1, ALCK2, ALCK3, LDSCK1, LDSCK2, LDSCK3, SWRX1CK, SWRX2CK, FCK1, FCK2, FDCK, CCK, DQ1CI1, DQ1CI2, DQ1CI3, DQ1CI4, DQ1CI5, DQ1CI6, DQ1CI7, DQ1CI8, DQ2CI1
+, DQ2CI2, DQ2CI3, DQ2CI4, DQ2CI5, DQ2CI6, DQ2CI7, DQ2CI8, DQ3CI1, DQ3CI2, DQ3CI3, DQ3CI4, DQ3CI5, DQ3CI6, DQ3CI7, DQ3CI8, DQS1CI1, DQS1CI2, DQS1CI3, DQS1CI4, DQS1CI5, DQS1CI6
+, DQS1CI7, DQS1CI8, DQS2CI1, DQS2CI2, DQS2CI3, DQS2CI4, DQS2CI5, DQS2CI6, DQS2CI7, DQS2CI8, DQS3CI1, DQS3CI2, DQS3CI3, DQS3CI4, DQS3CI5, DQS3CI6, DQS3CI7, DQS3CI8, LD1RN, LD2RN, LD3RN
+, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DCRN, LE, SE, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4, DRO1CSN
+, DRO2CSN, DRO3CSN, DRI1CSN, DRI2CSN, DRI3CSN, DRDPA1CSN, DRDPA2CSN, DRDPA3CSN, DRCCSN, DRWDS, DRWEN, DRE, CA1P1, CA1P2, CA1P3, CA1P4, CA2P1, CA2P2, CA2P3, CA2P4, CA1N1
+, CA1N2, CA1N3, CA1N4, CA2N1, CA2N2, CA2N3, CA2N4, CA1T1, CA1T2, CA1T3, CA1T4, CA2T1, CA2T2, CA2T3, CA2T4, CA1D1, CA1D2, CA1D3, CA1D4, CA1D5, CA1D6
+, CA2D1, CA2D2, CA2D3, CA2D4, CA2D5, CA2D6, CKO1, CKO2, FLD, FLG, AL1D, AL2D, AL3D, AL1T, AL2T, AL3T, DCL, DRO1, DRO2, DRO3, DRO4
+, DRO5, DRO6, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EI6, P1EI7, P1EI8, P1EL, P1ER, P1EO, P1RI, P1RL
+, P1RR, P1RO1, P1RO2, P1RO3, P1RO4, P1RO5, P1RO6, P1RO7, P1RO8, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EI6
+, P2EI7, P2EI8, P2EL, P2ER, P2EO, P2RI, P2RL, P2RR, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P2RO6, P2RO7, P2RO8, P3CI1, P3CL, P3CR, P3CO, P3CTI
+, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EI6, P3EI7, P3EI8, P3EL, P3ER, P3EO, P3RI, P3RL, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P3RO6
+, P3RO7, P3RO8, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EI6, P4EI7, P4EI8, P4EL, P4ER, P4EO, P4RI, P4RL
+, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P4RO6, P4RO7, P4RO8, P5CI1, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3, P5EI4, P5EI5, P5EI6
+, P5EI7, P5EI8, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P5RO6, P5RO7, P5RO8, P6CI1, P6CL, P6CR, P6CO, P6CTI
+, P6CTO, P6EI1, P6EI2, P6EI3, P6EI4, P6EI5, P6EI6, P6EI7, P6EI8, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P6RO6
+, P6RO7, P6RO8, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1, P7EI2, P7EI3, P7EI4, P7EI5, P7EI6, P7EI7, P7EI8, P7EL, P7ER, P7EO, P7RI, P7RL
+, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P7RO6, P7RO7, P7RO8, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO, P8EI1, P8EI2, P8EI3, P8EI4, P8EI5, P8EI6
+, P8EI7, P8EI8, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P8RO6, P8RO7, P8RO8, P9CI1, P9CL, P9CR, P9CO, P9CTI
+, P9CTO, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EI6, P9EI7, P9EI8, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P9RO6
+, P9RO7, P9RO8, P10CI1, P10CL, P10CR, P10CO, P10CTI, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EI6, P10EI7, P10EI8, P10EL, P10ER, P10EO, P10RI, P10RL
+, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P10RO6, P10RO7, P10RO8, P11CI1, P11CL, P11CR, P11CO, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EI6
+, P11EI7, P11EI8, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P11RO6, P11RO7, P11RO8, P12CI1, P12CL, P12CR, P12CO, P12CTI
+, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EI6, P12EI7, P12EI8, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P12RO6
+, P12RO7, P12RO8, P13CI1, P13CL, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EI6, P13EI7, P13EI8, P13EL, P13ER, P13EO, P13RI, P13RL
+, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5, P13RO6, P13RO7, P13RO8, P14CI1, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EI6
+, P14EI7, P14EI8, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4, P14RO5, P14RO6, P14RO7, P14RO8, P15CI1, P15CL, P15CR, P15CO, P15CTI
+, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EI6, P15EI7, P15EI8, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3, P15RO4, P15RO5, P15RO6
+, P15RO7, P15RO8, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EI6, P16EI7, P16EI8, P16EL, P16ER, P16EO, P16RI, P16RL
+, P16RR, P16RO1, P16RO2, P16RO3, P16RO4, P16RO5, P16RO6, P16RO7, P16RO8, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EI6
+, P17EI7, P17EI8, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1, P17RO2, P17RO3, P17RO4, P17RO5, P17RO6, P17RO7, P17RO8, P18CI1, P18CL, P18CR, P18CO, P18CTI
+, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EI6, P18EI7, P18EI8, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR, P18RO1, P18RO2, P18RO3, P18RO4, P18RO5, P18RO6
+, P18RO7, P18RO8, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EI6, P19EI7, P19EI8, P19EL, P19ER, P19EO, P19RI, P19RL
+, P19RR, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P19RO6, P19RO7, P19RO8, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EI6
+, P20EI7, P20EI8, P20EL, P20ER, P20EO, P20RI, P20RL, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P20RO6, P20RO7, P20RO8, P21CI1, P21CL, P21CR, P21CO, P21CTI
+, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EI6, P21EI7, P21EI8, P21EL, P21ER, P21EO, P21RI, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P21RO6
+, P21RO7, P21RO8, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EI6, P22EI7, P22EI8, P22EL, P22ER, P22EO, P22RI, P22RL
+, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P22RO6, P22RO7, P22RO8, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EI6
+, P23EI7, P23EI8, P23EL, P23ER, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P23RO6, P23RO7, P23RO8, P24CI1, P24CL, P24CR, P24CO, P24CTI
+, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5, P24EI6, P24EI7, P24EI8, P24EL, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P24RO6
+, P24RO7, P24RO8, P25CI1, P25CL, P25CR, P25CO, P25CTI, P25CTO, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5, P25EI6, P25EI7, P25EI8, P25EL, P25ER, P25EO, P25RI, P25RL
+, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P25RO6, P25RO7, P25RO8, P26CI1, P26CL, P26CR, P26CO, P26CTI, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4, P26EI5, P26EI6
+, P26EI7, P26EI8, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P26RO6, P26RO7, P26RO8, P27CI1, P27CL, P27CR, P27CO, P27CTI
+, P27CTO, P27EI1, P27EI2, P27EI3, P27EI4, P27EI5, P27EI6, P27EI7, P27EI8, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P27RO6
+, P27RO7, P27RO8, P28CI1, P28CL, P28CR, P28CO, P28CTI, P28CTO, P28EI1, P28EI2, P28EI3, P28EI4, P28EI5, P28EI6, P28EI7, P28EI8, P28EL, P28ER, P28EO, P28RI, P28RL
+, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P28RO6, P28RO7, P28RO8, P29CI1, P29CL, P29CR, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EI6
+, P29EI7, P29EI8, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P29RO6, P29RO7, P29RO8, P30CI1, P30CL, P30CR, P30CO, P30CTI
+, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EI6, P30EI7, P30EI8, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5, P30RO6
+, P30RO7, P30RO8, P31CI1, P31CL, P31CR, P31CO, P31CTI, P31CTO, P31EI1, P31EI2, P31EI3, P31EI4, P31EI5, P31EI6, P31EI7, P31EI8, P31EL, P31ER, P31EO, P31RI, P31RL
+, P31RR, P31RO1, P31RO2, P31RO3, P31RO4, P31RO5, P31RO6, P31RO7, P31RO8, P32CI1, P32CL, P32CR, P32CO, P32CTI, P32CTO, P32EI1, P32EI2, P32EI3, P32EI4, P32EI5, P32EI6
+, P32EI7, P32EI8, P32EL, P32ER, P32EO, P32RI, P32RL, P32RR, P32RO1, P32RO2, P32RO3, P32RO4, P32RO5, P32RO6, P32RO7, P32RO8, P33CI1, P33CL, P33CR, P33CO, P33CTI
+, P33CTO, P33EI1, P33EI2, P33EI3, P33EI4, P33EI5, P33EI6, P33EI7, P33EI8, P33EL, P33ER, P33EO, P33RI, P33RL, P33RR, P33RO1, P33RO2, P33RO3, P33RO4, P33RO5, P33RO6
+, P33RO7, P33RO8, P34CI1, P34CL, P34CR, P34CO, P34CTI, P34CTO, P34EI1, P34EI2, P34EI3, P34EI4, P34EI5, P34EI6, P34EI7, P34EI8, P34EL, P34ER, P34EO, P34RI, P34RL
+, P34RR, P34RO1, P34RO2, P34RO3, P34RO4, P34RO5, P34RO6, P34RO7, P34RO8);
+    output AL1D;
+    output AL1T;
+    output AL2D;
+    output AL2T;
+    output AL3D;
+    output AL3T;
+    input ALCK1;
+    input ALCK2;
+    input ALCK3;
+    input CA1D1;
+    input CA1D2;
+    input CA1D3;
+    input CA1D4;
+    input CA1D5;
+    input CA1D6;
+    input CA1N1;
+    input CA1N2;
+    input CA1N3;
+    input CA1N4;
+    input CA1P1;
+    input CA1P2;
+    input CA1P3;
+    input CA1P4;
+    input CA1T1;
+    input CA1T2;
+    input CA1T3;
+    input CA1T4;
+    input CA2D1;
+    input CA2D2;
+    input CA2D3;
+    input CA2D4;
+    input CA2D5;
+    input CA2D6;
+    input CA2N1;
+    input CA2N2;
+    input CA2N3;
+    input CA2N4;
+    input CA2P1;
+    input CA2P2;
+    input CA2P3;
+    input CA2P4;
+    input CA2T1;
+    input CA2T2;
+    input CA2T3;
+    input CA2T4;
+    input CCK;
+    output CKO1;
+    output CKO2;
+    output DCL;
+    input DCRN;
+    input DQ1CI1;
+    input DQ1CI2;
+    input DQ1CI3;
+    input DQ1CI4;
+    input DQ1CI5;
+    input DQ1CI6;
+    input DQ1CI7;
+    input DQ1CI8;
+    input DQ2CI1;
+    input DQ2CI2;
+    input DQ2CI3;
+    input DQ2CI4;
+    input DQ2CI5;
+    input DQ2CI6;
+    input DQ2CI7;
+    input DQ2CI8;
+    input DQ3CI1;
+    input DQ3CI2;
+    input DQ3CI3;
+    input DQ3CI4;
+    input DQ3CI5;
+    input DQ3CI6;
+    input DQ3CI7;
+    input DQ3CI8;
+    input DQS1CI1;
+    input DQS1CI2;
+    input DQS1CI3;
+    input DQS1CI4;
+    input DQS1CI5;
+    input DQS1CI6;
+    input DQS1CI7;
+    input DQS1CI8;
+    input DQS2CI1;
+    input DQS2CI2;
+    input DQS2CI3;
+    input DQS2CI4;
+    input DQS2CI5;
+    input DQS2CI6;
+    input DQS2CI7;
+    input DQS2CI8;
+    input DQS3CI1;
+    input DQS3CI2;
+    input DQS3CI3;
+    input DQS3CI4;
+    input DQS3CI5;
+    input DQS3CI6;
+    input DQS3CI7;
+    input DQS3CI8;
+    input DRA1;
+    input DRA2;
+    input DRA3;
+    input DRA4;
+    input DRCCSN;
+    input DRDPA1CSN;
+    input DRDPA2CSN;
+    input DRDPA3CSN;
+    input DRE;
+    input DRI1;
+    input DRI1CSN;
+    input DRI2;
+    input DRI2CSN;
+    input DRI3;
+    input DRI3CSN;
+    input DRI4;
+    input DRI5;
+    input DRI6;
+    output DRO1;
+    input DRO1CSN;
+    output DRO2;
+    input DRO2CSN;
+    output DRO3;
+    input DRO3CSN;
+    output DRO4;
+    output DRO5;
+    output DRO6;
+    input DRWDS;
+    input DRWEN;
+    input FA1;
+    input FA2;
+    input FA3;
+    input FA4;
+    input FA5;
+    input FA6;
+    input FCK1;
+    input FCK2;
+    input FDCK;
+    output FLD;
+    output FLG;
+    input FZ;
+    input LD1RN;
+    input LD2RN;
+    input LD3RN;
+    input LDSCK1;
+    input LDSCK2;
+    input LDSCK3;
+    input LE;
+    input P10CI1;
+    input P10CL;
+    output P10CO;
+    input P10CR;
+    input P10CTI;
+    output P10CTO;
+    input P10EI1;
+    input P10EI2;
+    input P10EI3;
+    input P10EI4;
+    input P10EI5;
+    input P10EI6;
+    input P10EI7;
+    input P10EI8;
+    input P10EL;
+    output P10EO;
+    input P10ER;
+    input P10RI;
+    input P10RL;
+    output P10RO1;
+    output P10RO2;
+    output P10RO3;
+    output P10RO4;
+    output P10RO5;
+    output P10RO6;
+    output P10RO7;
+    output P10RO8;
+    input P10RR;
+    input P11CI1;
+    input P11CL;
+    output P11CO;
+    input P11CR;
+    input P11CTI;
+    output P11CTO;
+    input P11EI1;
+    input P11EI2;
+    input P11EI3;
+    input P11EI4;
+    input P11EI5;
+    input P11EI6;
+    input P11EI7;
+    input P11EI8;
+    input P11EL;
+    output P11EO;
+    input P11ER;
+    input P11RI;
+    input P11RL;
+    output P11RO1;
+    output P11RO2;
+    output P11RO3;
+    output P11RO4;
+    output P11RO5;
+    output P11RO6;
+    output P11RO7;
+    output P11RO8;
+    input P11RR;
+    input P12CI1;
+    input P12CL;
+    output P12CO;
+    input P12CR;
+    input P12CTI;
+    output P12CTO;
+    input P12EI1;
+    input P12EI2;
+    input P12EI3;
+    input P12EI4;
+    input P12EI5;
+    input P12EI6;
+    input P12EI7;
+    input P12EI8;
+    input P12EL;
+    output P12EO;
+    input P12ER;
+    input P12RI;
+    input P12RL;
+    output P12RO1;
+    output P12RO2;
+    output P12RO3;
+    output P12RO4;
+    output P12RO5;
+    output P12RO6;
+    output P12RO7;
+    output P12RO8;
+    input P12RR;
+    input P13CI1;
+    input P13CL;
+    output P13CO;
+    input P13CR;
+    input P13CTI;
+    output P13CTO;
+    input P13EI1;
+    input P13EI2;
+    input P13EI3;
+    input P13EI4;
+    input P13EI5;
+    input P13EI6;
+    input P13EI7;
+    input P13EI8;
+    input P13EL;
+    output P13EO;
+    input P13ER;
+    input P13RI;
+    input P13RL;
+    output P13RO1;
+    output P13RO2;
+    output P13RO3;
+    output P13RO4;
+    output P13RO5;
+    output P13RO6;
+    output P13RO7;
+    output P13RO8;
+    input P13RR;
+    input P14CI1;
+    input P14CL;
+    output P14CO;
+    input P14CR;
+    input P14CTI;
+    output P14CTO;
+    input P14EI1;
+    input P14EI2;
+    input P14EI3;
+    input P14EI4;
+    input P14EI5;
+    input P14EI6;
+    input P14EI7;
+    input P14EI8;
+    input P14EL;
+    output P14EO;
+    input P14ER;
+    input P14RI;
+    input P14RL;
+    output P14RO1;
+    output P14RO2;
+    output P14RO3;
+    output P14RO4;
+    output P14RO5;
+    output P14RO6;
+    output P14RO7;
+    output P14RO8;
+    input P14RR;
+    input P15CI1;
+    input P15CL;
+    output P15CO;
+    input P15CR;
+    input P15CTI;
+    output P15CTO;
+    input P15EI1;
+    input P15EI2;
+    input P15EI3;
+    input P15EI4;
+    input P15EI5;
+    input P15EI6;
+    input P15EI7;
+    input P15EI8;
+    input P15EL;
+    output P15EO;
+    input P15ER;
+    input P15RI;
+    input P15RL;
+    output P15RO1;
+    output P15RO2;
+    output P15RO3;
+    output P15RO4;
+    output P15RO5;
+    output P15RO6;
+    output P15RO7;
+    output P15RO8;
+    input P15RR;
+    input P16CI1;
+    input P16CL;
+    output P16CO;
+    input P16CR;
+    input P16CTI;
+    output P16CTO;
+    input P16EI1;
+    input P16EI2;
+    input P16EI3;
+    input P16EI4;
+    input P16EI5;
+    input P16EI6;
+    input P16EI7;
+    input P16EI8;
+    input P16EL;
+    output P16EO;
+    input P16ER;
+    input P16RI;
+    input P16RL;
+    output P16RO1;
+    output P16RO2;
+    output P16RO3;
+    output P16RO4;
+    output P16RO5;
+    output P16RO6;
+    output P16RO7;
+    output P16RO8;
+    input P16RR;
+    input P17CI1;
+    input P17CL;
+    output P17CO;
+    input P17CR;
+    input P17CTI;
+    output P17CTO;
+    input P17EI1;
+    input P17EI2;
+    input P17EI3;
+    input P17EI4;
+    input P17EI5;
+    input P17EI6;
+    input P17EI7;
+    input P17EI8;
+    input P17EL;
+    output P17EO;
+    input P17ER;
+    input P17RI;
+    input P17RL;
+    output P17RO1;
+    output P17RO2;
+    output P17RO3;
+    output P17RO4;
+    output P17RO5;
+    output P17RO6;
+    output P17RO7;
+    output P17RO8;
+    input P17RR;
+    input P18CI1;
+    input P18CL;
+    output P18CO;
+    input P18CR;
+    input P18CTI;
+    output P18CTO;
+    input P18EI1;
+    input P18EI2;
+    input P18EI3;
+    input P18EI4;
+    input P18EI5;
+    input P18EI6;
+    input P18EI7;
+    input P18EI8;
+    input P18EL;
+    output P18EO;
+    input P18ER;
+    input P18RI;
+    input P18RL;
+    output P18RO1;
+    output P18RO2;
+    output P18RO3;
+    output P18RO4;
+    output P18RO5;
+    output P18RO6;
+    output P18RO7;
+    output P18RO8;
+    input P18RR;
+    input P19CI1;
+    input P19CL;
+    output P19CO;
+    input P19CR;
+    input P19CTI;
+    output P19CTO;
+    input P19EI1;
+    input P19EI2;
+    input P19EI3;
+    input P19EI4;
+    input P19EI5;
+    input P19EI6;
+    input P19EI7;
+    input P19EI8;
+    input P19EL;
+    output P19EO;
+    input P19ER;
+    input P19RI;
+    input P19RL;
+    output P19RO1;
+    output P19RO2;
+    output P19RO3;
+    output P19RO4;
+    output P19RO5;
+    output P19RO6;
+    output P19RO7;
+    output P19RO8;
+    input P19RR;
+    input P1CI1;
+    input P1CL;
+    output P1CO;
+    input P1CR;
+    input P1CTI;
+    output P1CTO;
+    input P1EI1;
+    input P1EI2;
+    input P1EI3;
+    input P1EI4;
+    input P1EI5;
+    input P1EI6;
+    input P1EI7;
+    input P1EI8;
+    input P1EL;
+    output P1EO;
+    input P1ER;
+    input P1RI;
+    input P1RL;
+    output P1RO1;
+    output P1RO2;
+    output P1RO3;
+    output P1RO4;
+    output P1RO5;
+    output P1RO6;
+    output P1RO7;
+    output P1RO8;
+    input P1RR;
+    input P20CI1;
+    input P20CL;
+    output P20CO;
+    input P20CR;
+    input P20CTI;
+    output P20CTO;
+    input P20EI1;
+    input P20EI2;
+    input P20EI3;
+    input P20EI4;
+    input P20EI5;
+    input P20EI6;
+    input P20EI7;
+    input P20EI8;
+    input P20EL;
+    output P20EO;
+    input P20ER;
+    input P20RI;
+    input P20RL;
+    output P20RO1;
+    output P20RO2;
+    output P20RO3;
+    output P20RO4;
+    output P20RO5;
+    output P20RO6;
+    output P20RO7;
+    output P20RO8;
+    input P20RR;
+    input P21CI1;
+    input P21CL;
+    output P21CO;
+    input P21CR;
+    input P21CTI;
+    output P21CTO;
+    input P21EI1;
+    input P21EI2;
+    input P21EI3;
+    input P21EI4;
+    input P21EI5;
+    input P21EI6;
+    input P21EI7;
+    input P21EI8;
+    input P21EL;
+    output P21EO;
+    input P21ER;
+    input P21RI;
+    input P21RL;
+    output P21RO1;
+    output P21RO2;
+    output P21RO3;
+    output P21RO4;
+    output P21RO5;
+    output P21RO6;
+    output P21RO7;
+    output P21RO8;
+    input P21RR;
+    input P22CI1;
+    input P22CL;
+    output P22CO;
+    input P22CR;
+    input P22CTI;
+    output P22CTO;
+    input P22EI1;
+    input P22EI2;
+    input P22EI3;
+    input P22EI4;
+    input P22EI5;
+    input P22EI6;
+    input P22EI7;
+    input P22EI8;
+    input P22EL;
+    output P22EO;
+    input P22ER;
+    input P22RI;
+    input P22RL;
+    output P22RO1;
+    output P22RO2;
+    output P22RO3;
+    output P22RO4;
+    output P22RO5;
+    output P22RO6;
+    output P22RO7;
+    output P22RO8;
+    input P22RR;
+    input P23CI1;
+    input P23CL;
+    output P23CO;
+    input P23CR;
+    input P23CTI;
+    output P23CTO;
+    input P23EI1;
+    input P23EI2;
+    input P23EI3;
+    input P23EI4;
+    input P23EI5;
+    input P23EI6;
+    input P23EI7;
+    input P23EI8;
+    input P23EL;
+    output P23EO;
+    input P23ER;
+    input P23RI;
+    input P23RL;
+    output P23RO1;
+    output P23RO2;
+    output P23RO3;
+    output P23RO4;
+    output P23RO5;
+    output P23RO6;
+    output P23RO7;
+    output P23RO8;
+    input P23RR;
+    input P24CI1;
+    input P24CL;
+    output P24CO;
+    input P24CR;
+    input P24CTI;
+    output P24CTO;
+    input P24EI1;
+    input P24EI2;
+    input P24EI3;
+    input P24EI4;
+    input P24EI5;
+    input P24EI6;
+    input P24EI7;
+    input P24EI8;
+    input P24EL;
+    output P24EO;
+    input P24ER;
+    input P24RI;
+    input P24RL;
+    output P24RO1;
+    output P24RO2;
+    output P24RO3;
+    output P24RO4;
+    output P24RO5;
+    output P24RO6;
+    output P24RO7;
+    output P24RO8;
+    input P24RR;
+    input P25CI1;
+    input P25CL;
+    output P25CO;
+    input P25CR;
+    input P25CTI;
+    output P25CTO;
+    input P25EI1;
+    input P25EI2;
+    input P25EI3;
+    input P25EI4;
+    input P25EI5;
+    input P25EI6;
+    input P25EI7;
+    input P25EI8;
+    input P25EL;
+    output P25EO;
+    input P25ER;
+    input P25RI;
+    input P25RL;
+    output P25RO1;
+    output P25RO2;
+    output P25RO3;
+    output P25RO4;
+    output P25RO5;
+    output P25RO6;
+    output P25RO7;
+    output P25RO8;
+    input P25RR;
+    input P26CI1;
+    input P26CL;
+    output P26CO;
+    input P26CR;
+    input P26CTI;
+    output P26CTO;
+    input P26EI1;
+    input P26EI2;
+    input P26EI3;
+    input P26EI4;
+    input P26EI5;
+    input P26EI6;
+    input P26EI7;
+    input P26EI8;
+    input P26EL;
+    output P26EO;
+    input P26ER;
+    input P26RI;
+    input P26RL;
+    output P26RO1;
+    output P26RO2;
+    output P26RO3;
+    output P26RO4;
+    output P26RO5;
+    output P26RO6;
+    output P26RO7;
+    output P26RO8;
+    input P26RR;
+    input P27CI1;
+    input P27CL;
+    output P27CO;
+    input P27CR;
+    input P27CTI;
+    output P27CTO;
+    input P27EI1;
+    input P27EI2;
+    input P27EI3;
+    input P27EI4;
+    input P27EI5;
+    input P27EI6;
+    input P27EI7;
+    input P27EI8;
+    input P27EL;
+    output P27EO;
+    input P27ER;
+    input P27RI;
+    input P27RL;
+    output P27RO1;
+    output P27RO2;
+    output P27RO3;
+    output P27RO4;
+    output P27RO5;
+    output P27RO6;
+    output P27RO7;
+    output P27RO8;
+    input P27RR;
+    input P28CI1;
+    input P28CL;
+    output P28CO;
+    input P28CR;
+    input P28CTI;
+    output P28CTO;
+    input P28EI1;
+    input P28EI2;
+    input P28EI3;
+    input P28EI4;
+    input P28EI5;
+    input P28EI6;
+    input P28EI7;
+    input P28EI8;
+    input P28EL;
+    output P28EO;
+    input P28ER;
+    input P28RI;
+    input P28RL;
+    output P28RO1;
+    output P28RO2;
+    output P28RO3;
+    output P28RO4;
+    output P28RO5;
+    output P28RO6;
+    output P28RO7;
+    output P28RO8;
+    input P28RR;
+    input P29CI1;
+    input P29CL;
+    output P29CO;
+    input P29CR;
+    input P29CTI;
+    output P29CTO;
+    input P29EI1;
+    input P29EI2;
+    input P29EI3;
+    input P29EI4;
+    input P29EI5;
+    input P29EI6;
+    input P29EI7;
+    input P29EI8;
+    input P29EL;
+    output P29EO;
+    input P29ER;
+    input P29RI;
+    input P29RL;
+    output P29RO1;
+    output P29RO2;
+    output P29RO3;
+    output P29RO4;
+    output P29RO5;
+    output P29RO6;
+    output P29RO7;
+    output P29RO8;
+    input P29RR;
+    input P2CI1;
+    input P2CL;
+    output P2CO;
+    input P2CR;
+    input P2CTI;
+    output P2CTO;
+    input P2EI1;
+    input P2EI2;
+    input P2EI3;
+    input P2EI4;
+    input P2EI5;
+    input P2EI6;
+    input P2EI7;
+    input P2EI8;
+    input P2EL;
+    output P2EO;
+    input P2ER;
+    input P2RI;
+    input P2RL;
+    output P2RO1;
+    output P2RO2;
+    output P2RO3;
+    output P2RO4;
+    output P2RO5;
+    output P2RO6;
+    output P2RO7;
+    output P2RO8;
+    input P2RR;
+    input P30CI1;
+    input P30CL;
+    output P30CO;
+    input P30CR;
+    input P30CTI;
+    output P30CTO;
+    input P30EI1;
+    input P30EI2;
+    input P30EI3;
+    input P30EI4;
+    input P30EI5;
+    input P30EI6;
+    input P30EI7;
+    input P30EI8;
+    input P30EL;
+    output P30EO;
+    input P30ER;
+    input P30RI;
+    input P30RL;
+    output P30RO1;
+    output P30RO2;
+    output P30RO3;
+    output P30RO4;
+    output P30RO5;
+    output P30RO6;
+    output P30RO7;
+    output P30RO8;
+    input P30RR;
+    input P31CI1;
+    input P31CL;
+    output P31CO;
+    input P31CR;
+    input P31CTI;
+    output P31CTO;
+    input P31EI1;
+    input P31EI2;
+    input P31EI3;
+    input P31EI4;
+    input P31EI5;
+    input P31EI6;
+    input P31EI7;
+    input P31EI8;
+    input P31EL;
+    output P31EO;
+    input P31ER;
+    input P31RI;
+    input P31RL;
+    output P31RO1;
+    output P31RO2;
+    output P31RO3;
+    output P31RO4;
+    output P31RO5;
+    output P31RO6;
+    output P31RO7;
+    output P31RO8;
+    input P31RR;
+    input P32CI1;
+    input P32CL;
+    output P32CO;
+    input P32CR;
+    input P32CTI;
+    output P32CTO;
+    input P32EI1;
+    input P32EI2;
+    input P32EI3;
+    input P32EI4;
+    input P32EI5;
+    input P32EI6;
+    input P32EI7;
+    input P32EI8;
+    input P32EL;
+    output P32EO;
+    input P32ER;
+    input P32RI;
+    input P32RL;
+    output P32RO1;
+    output P32RO2;
+    output P32RO3;
+    output P32RO4;
+    output P32RO5;
+    output P32RO6;
+    output P32RO7;
+    output P32RO8;
+    input P32RR;
+    input P33CI1;
+    input P33CL;
+    output P33CO;
+    input P33CR;
+    input P33CTI;
+    output P33CTO;
+    input P33EI1;
+    input P33EI2;
+    input P33EI3;
+    input P33EI4;
+    input P33EI5;
+    input P33EI6;
+    input P33EI7;
+    input P33EI8;
+    input P33EL;
+    output P33EO;
+    input P33ER;
+    input P33RI;
+    input P33RL;
+    output P33RO1;
+    output P33RO2;
+    output P33RO3;
+    output P33RO4;
+    output P33RO5;
+    output P33RO6;
+    output P33RO7;
+    output P33RO8;
+    input P33RR;
+    input P34CI1;
+    input P34CL;
+    output P34CO;
+    input P34CR;
+    input P34CTI;
+    output P34CTO;
+    input P34EI1;
+    input P34EI2;
+    input P34EI3;
+    input P34EI4;
+    input P34EI5;
+    input P34EI6;
+    input P34EI7;
+    input P34EI8;
+    input P34EL;
+    output P34EO;
+    input P34ER;
+    input P34RI;
+    input P34RL;
+    output P34RO1;
+    output P34RO2;
+    output P34RO3;
+    output P34RO4;
+    output P34RO5;
+    output P34RO6;
+    output P34RO7;
+    output P34RO8;
+    input P34RR;
+    input P3CI1;
+    input P3CL;
+    output P3CO;
+    input P3CR;
+    input P3CTI;
+    output P3CTO;
+    input P3EI1;
+    input P3EI2;
+    input P3EI3;
+    input P3EI4;
+    input P3EI5;
+    input P3EI6;
+    input P3EI7;
+    input P3EI8;
+    input P3EL;
+    output P3EO;
+    input P3ER;
+    input P3RI;
+    input P3RL;
+    output P3RO1;
+    output P3RO2;
+    output P3RO3;
+    output P3RO4;
+    output P3RO5;
+    output P3RO6;
+    output P3RO7;
+    output P3RO8;
+    input P3RR;
+    input P4CI1;
+    input P4CL;
+    output P4CO;
+    input P4CR;
+    input P4CTI;
+    output P4CTO;
+    input P4EI1;
+    input P4EI2;
+    input P4EI3;
+    input P4EI4;
+    input P4EI5;
+    input P4EI6;
+    input P4EI7;
+    input P4EI8;
+    input P4EL;
+    output P4EO;
+    input P4ER;
+    input P4RI;
+    input P4RL;
+    output P4RO1;
+    output P4RO2;
+    output P4RO3;
+    output P4RO4;
+    output P4RO5;
+    output P4RO6;
+    output P4RO7;
+    output P4RO8;
+    input P4RR;
+    input P5CI1;
+    input P5CL;
+    output P5CO;
+    input P5CR;
+    input P5CTI;
+    output P5CTO;
+    input P5EI1;
+    input P5EI2;
+    input P5EI3;
+    input P5EI4;
+    input P5EI5;
+    input P5EI6;
+    input P5EI7;
+    input P5EI8;
+    input P5EL;
+    output P5EO;
+    input P5ER;
+    input P5RI;
+    input P5RL;
+    output P5RO1;
+    output P5RO2;
+    output P5RO3;
+    output P5RO4;
+    output P5RO5;
+    output P5RO6;
+    output P5RO7;
+    output P5RO8;
+    input P5RR;
+    input P6CI1;
+    input P6CL;
+    output P6CO;
+    input P6CR;
+    input P6CTI;
+    output P6CTO;
+    input P6EI1;
+    input P6EI2;
+    input P6EI3;
+    input P6EI4;
+    input P6EI5;
+    input P6EI6;
+    input P6EI7;
+    input P6EI8;
+    input P6EL;
+    output P6EO;
+    input P6ER;
+    input P6RI;
+    input P6RL;
+    output P6RO1;
+    output P6RO2;
+    output P6RO3;
+    output P6RO4;
+    output P6RO5;
+    output P6RO6;
+    output P6RO7;
+    output P6RO8;
+    input P6RR;
+    input P7CI1;
+    input P7CL;
+    output P7CO;
+    input P7CR;
+    input P7CTI;
+    output P7CTO;
+    input P7EI1;
+    input P7EI2;
+    input P7EI3;
+    input P7EI4;
+    input P7EI5;
+    input P7EI6;
+    input P7EI7;
+    input P7EI8;
+    input P7EL;
+    output P7EO;
+    input P7ER;
+    input P7RI;
+    input P7RL;
+    output P7RO1;
+    output P7RO2;
+    output P7RO3;
+    output P7RO4;
+    output P7RO5;
+    output P7RO6;
+    output P7RO7;
+    output P7RO8;
+    input P7RR;
+    input P8CI1;
+    input P8CL;
+    output P8CO;
+    input P8CR;
+    input P8CTI;
+    output P8CTO;
+    input P8EI1;
+    input P8EI2;
+    input P8EI3;
+    input P8EI4;
+    input P8EI5;
+    input P8EI6;
+    input P8EI7;
+    input P8EI8;
+    input P8EL;
+    output P8EO;
+    input P8ER;
+    input P8RI;
+    input P8RL;
+    output P8RO1;
+    output P8RO2;
+    output P8RO3;
+    output P8RO4;
+    output P8RO5;
+    output P8RO6;
+    output P8RO7;
+    output P8RO8;
+    input P8RR;
+    input P9CI1;
+    input P9CL;
+    output P9CO;
+    input P9CR;
+    input P9CTI;
+    output P9CTO;
+    input P9EI1;
+    input P9EI2;
+    input P9EI3;
+    input P9EI4;
+    input P9EI5;
+    input P9EI6;
+    input P9EI7;
+    input P9EI8;
+    input P9EL;
+    output P9EO;
+    input P9ER;
+    input P9RI;
+    input P9RL;
+    output P9RO1;
+    output P9RO2;
+    output P9RO3;
+    output P9RO4;
+    output P9RO5;
+    output P9RO6;
+    output P9RO7;
+    output P9RO8;
+    input P9RR;
+    input SE;
+    input SWRX1CK;
+    input SWRX2CK;
+    parameter cal_delay1 = "";
+    parameter cal_delay2 = "";
+    parameter div1 = 3'b000;
+    parameter div2 = 3'b000;
+    parameter div3 = 3'b000;
+    parameter div_swrx1 = 3'b000;
+    parameter div_swrx2 = 3'b000;
+    parameter inv_ld_sck1 = 1'b0;
+    parameter inv_ld_sck2 = 1'b0;
+    parameter inv_ld_sck3 = 1'b0;
+    parameter link_ld_12 = 1'b0;
+    parameter link_ld_23 = 1'b0;
+    parameter mode_side1 = 0;
+    parameter mode_side2 = 0;
+    parameter mode_side3 = 0;
+    parameter pads_dict = "";
+    parameter pads_path = "";
+    parameter sel_clk_out1 = 1'b0;
+    parameter sel_clk_out2 = 1'b0;
+    parameter sel_dc_clk = 2'b00;
+    parameter sel_ld_fck1 = 2'b00;
+    parameter sel_ld_fck2 = 2'b00;
+    parameter sel_ld_fck3 = 2'b00;
+    parameter sel_sw_fck1 = 2'b00;
+    parameter sel_sw_fck2 = 2'b00;
+    parameter use_dc = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_PMA_U(CLK_TX_I, CLK_RX_I, CLK_REF_I, DC_E_I, DC_LCSN_I1, DC_LCSN_I2, DC_LCSN_I3, DC_LCSN_I4, DC_CCSN_I, DC_WE_N_I, DC_ADD_I1, DC_ADD_I2, DC_ADD_I3, DC_ADD_I4, DC_WDATAS_I, DC_WDATA_I1, DC_WDATA_I2, DC_WDATA_I3, DC_WDATA_I4, DC_WDATA_I5, DC_WDATA_I6
+, DC_WDATA_I7, DC_WDATA_I8, DC_WDATA_I9, DC_WDATA_I10, DC_WDATA_I11, DC_WDATA_I12, PLL_RN_I, PWDN_N_I, RST_N_I, DBG_S_I1, DBG_S_I2, DBG_A_I, SE_I, SCAN_I1, SCAN_I2, SCAN_I3, SCAN_I4, SCAN_I5, SCAN_I6, SCAN_I7, SCAN_I8
+, CLK_O, CLK_RX_O, LOCK_O, LOCKA_O, FB_LOCK_O, CAL_OUT_O, DBG_R_O, LL_O1, LL_O2, LL_O3, LL_O4, LL_O5, LL_O6, LL_O7, LL_O8, LL_O9, LL_O10, LL_O11, LL_O12, LL_O13, LL_O14
+, LL_O15, LL_O16, LL_O17, LL_O18, LL_O19, LL_O20, SCAN_O1, SCAN_O2, SCAN_O3, SCAN_O4, SCAN_O5, SCAN_O6, SCAN_O7, SCAN_O8, LINK_TX1, LINK_TX2, LINK_TX3, LINK_RX0, LINK_RX1, LINK_RX2, LINK_RX3
+, LINK_TX0);
+    output CAL_OUT_O;
+    output CLK_O;
+    input CLK_REF_I;
+    input CLK_RX_I;
+    output CLK_RX_O;
+    input CLK_TX_I;
+    input DBG_A_I;
+    output DBG_R_O;
+    input DBG_S_I1;
+    input DBG_S_I2;
+    input DC_ADD_I1;
+    input DC_ADD_I2;
+    input DC_ADD_I3;
+    input DC_ADD_I4;
+    input DC_CCSN_I;
+    input DC_E_I;
+    input DC_LCSN_I1;
+    input DC_LCSN_I2;
+    input DC_LCSN_I3;
+    input DC_LCSN_I4;
+    input DC_WDATAS_I;
+    input DC_WDATA_I1;
+    input DC_WDATA_I10;
+    input DC_WDATA_I11;
+    input DC_WDATA_I12;
+    input DC_WDATA_I2;
+    input DC_WDATA_I3;
+    input DC_WDATA_I4;
+    input DC_WDATA_I5;
+    input DC_WDATA_I6;
+    input DC_WDATA_I7;
+    input DC_WDATA_I8;
+    input DC_WDATA_I9;
+    input DC_WE_N_I;
+    output FB_LOCK_O;
+    inout [9:0] LINK_RX0;
+    inout [9:0] LINK_RX1;
+    inout [9:0] LINK_RX2;
+    inout [9:0] LINK_RX3;
+    inout [19:0] LINK_TX0;
+    inout [19:0] LINK_TX1;
+    inout [19:0] LINK_TX2;
+    inout [19:0] LINK_TX3;
+    output LL_O1;
+    output LL_O10;
+    output LL_O11;
+    output LL_O12;
+    output LL_O13;
+    output LL_O14;
+    output LL_O15;
+    output LL_O16;
+    output LL_O17;
+    output LL_O18;
+    output LL_O19;
+    output LL_O2;
+    output LL_O20;
+    output LL_O3;
+    output LL_O4;
+    output LL_O5;
+    output LL_O6;
+    output LL_O7;
+    output LL_O8;
+    output LL_O9;
+    output LOCKA_O;
+    output LOCK_O;
+    input PLL_RN_I;
+    input PWDN_N_I;
+    input RST_N_I;
+    input SCAN_I1;
+    input SCAN_I2;
+    input SCAN_I3;
+    input SCAN_I4;
+    input SCAN_I5;
+    input SCAN_I6;
+    input SCAN_I7;
+    input SCAN_I8;
+    output SCAN_O1;
+    output SCAN_O2;
+    output SCAN_O3;
+    output SCAN_O4;
+    output SCAN_O5;
+    output SCAN_O6;
+    output SCAN_O7;
+    output SCAN_O8;
+    input SE_I;
+    parameter dyn_all_rx_pma_m_eye = 1'b0;
+    parameter dyn_all_rx_pma_m_eye_coarse_ena = 1'b0;
+    parameter dyn_all_rx_pma_m_eye_dn = 1'b0;
+    parameter dyn_all_rx_pma_m_eye_fine_ena = 1'b0;
+    parameter dyn_all_rx_pma_m_eye_step = 4'b0000;
+    parameter dyn_all_rx_pma_m_eye_up = 1'b0;
+    parameter dyn_all_rx_pma_threshold_1 = 5'b00000;
+    parameter dyn_all_rx_pma_threshold_2 = 5'b00000;
+    parameter dyn_all_rx_pma_trim_locked = 3'b000;
+    parameter dyn_all_rx_pma_trim_mode = 2'b00;
+    parameter dyn_all_rx_pma_trim_unlocked = 3'b000;
+    parameter dyn_rx0_pma_ctle_cap_p = 4'b0000;
+    parameter dyn_rx0_pma_ctle_res_p = 4'b0000;
+    parameter dyn_rx0_pma_dfe_idac_tap1_n = 6'b000000;
+    parameter dyn_rx0_pma_dfe_idac_tap2_n = 6'b000000;
+    parameter dyn_rx0_pma_dfe_idac_tap3_n = 6'b000000;
+    parameter dyn_rx0_pma_dfe_idac_tap4_n = 6'b000000;
+    parameter dyn_rx0_pma_termination_cmd = 6'b000000;
+    parameter dyn_rx1_pma_ctle_cap_p = 4'b0000;
+    parameter dyn_rx1_pma_ctle_res_p = 4'b0000;
+    parameter dyn_rx1_pma_dfe_idac_tap1_n = 6'b000000;
+    parameter dyn_rx1_pma_dfe_idac_tap2_n = 6'b000000;
+    parameter dyn_rx1_pma_dfe_idac_tap3_n = 6'b000000;
+    parameter dyn_rx1_pma_dfe_idac_tap4_n = 6'b000000;
+    parameter dyn_rx1_pma_termination_cmd = 6'b000000;
+    parameter dyn_rx2_pma_ctle_cap_p = 4'b0000;
+    parameter dyn_rx2_pma_ctle_res_p = 4'b0000;
+    parameter dyn_rx2_pma_dfe_idac_tap1_n = 6'b000000;
+    parameter dyn_rx2_pma_dfe_idac_tap2_n = 6'b000000;
+    parameter dyn_rx2_pma_dfe_idac_tap3_n = 6'b000000;
+    parameter dyn_rx2_pma_dfe_idac_tap4_n = 6'b000000;
+    parameter dyn_rx2_pma_termination_cmd = 6'b000000;
+    parameter dyn_rx3_pma_ctle_cap_p = 4'b0000;
+    parameter dyn_rx3_pma_ctle_res_p = 4'b0000;
+    parameter dyn_rx3_pma_dfe_idac_tap1_n = 6'b000000;
+    parameter dyn_rx3_pma_dfe_idac_tap2_n = 6'b000000;
+    parameter dyn_rx3_pma_dfe_idac_tap3_n = 6'b000000;
+    parameter dyn_rx3_pma_dfe_idac_tap4_n = 6'b000000;
+    parameter dyn_rx3_pma_termination_cmd = 6'b000000;
+    parameter dyn_tx0_pma_main_en = 6'b000000;
+    parameter dyn_tx0_pma_main_sign = 1'b0;
+    parameter dyn_tx0_pma_margin_input = 9'b000000000;
+    parameter dyn_tx0_pma_margin_sel = 9'b000000000;
+    parameter dyn_tx0_pma_post_en = 5'b00000;
+    parameter dyn_tx0_pma_post_sel = 8'b00000000;
+    parameter dyn_tx0_pma_post_sign = 1'b0;
+    parameter dyn_tx0_pma_pre_en = 1'b0;
+    parameter dyn_tx0_pma_pre_sel = 4'b0000;
+    parameter dyn_tx0_pma_pre_sign = 1'b0;
+    parameter dyn_tx1_pma_main_en = 6'b000000;
+    parameter dyn_tx1_pma_main_sign = 1'b0;
+    parameter dyn_tx1_pma_margin_input = 9'b000000000;
+    parameter dyn_tx1_pma_margin_sel = 9'b000000000;
+    parameter dyn_tx1_pma_post_en = 5'b00000;
+    parameter dyn_tx1_pma_post_sel = 8'b00000000;
+    parameter dyn_tx1_pma_post_sign = 1'b0;
+    parameter dyn_tx1_pma_pre_en = 1'b0;
+    parameter dyn_tx1_pma_pre_sel = 4'b0000;
+    parameter dyn_tx1_pma_pre_sign = 1'b0;
+    parameter dyn_tx2_pma_main_en = 6'b000000;
+    parameter dyn_tx2_pma_main_sign = 1'b0;
+    parameter dyn_tx2_pma_margin_input = 9'b000000000;
+    parameter dyn_tx2_pma_margin_sel = 9'b000000000;
+    parameter dyn_tx2_pma_post_en = 5'b00000;
+    parameter dyn_tx2_pma_post_sel = 8'b00000000;
+    parameter dyn_tx2_pma_post_sign = 1'b0;
+    parameter dyn_tx2_pma_pre_en = 1'b0;
+    parameter dyn_tx2_pma_pre_sel = 4'b0000;
+    parameter dyn_tx2_pma_pre_sign = 1'b0;
+    parameter dyn_tx3_pma_main_en = 6'b000000;
+    parameter dyn_tx3_pma_main_sign = 1'b0;
+    parameter dyn_tx3_pma_margin_input = 9'b000000000;
+    parameter dyn_tx3_pma_margin_sel = 9'b000000000;
+    parameter dyn_tx3_pma_post_en = 5'b00000;
+    parameter dyn_tx3_pma_post_sel = 8'b00000000;
+    parameter dyn_tx3_pma_post_sign = 1'b0;
+    parameter dyn_tx3_pma_pre_en = 1'b0;
+    parameter dyn_tx3_pma_pre_sel = 4'b0000;
+    parameter dyn_tx3_pma_pre_sign = 1'b0;
+    parameter location = "";
+    parameter main_clk_to_fabric_div_en = 1'b0;
+    parameter main_clk_to_fabric_div_mode = 1'b0;
+    parameter main_clk_to_fabric_sel = 1'b0;
+    parameter main_rclk_to_fabric_sel = 2'b00;
+    parameter main_use_only_usr_clock = 1'b0;
+    parameter pcs_ovs_en = 1'b0;
+    parameter pcs_ovs_mode = 1'b0;
+    parameter pcs_pll_lock_ppm = 3'b000;
+    parameter pcs_word_len = 2'b00;
+    parameter pll_pma_ckref_ext = 1'b0;
+    parameter pll_pma_cpump = 4'b0000;
+    parameter pll_pma_divl = 2'b00;
+    parameter pll_pma_divm = 1'b0;
+    parameter pll_pma_divn = 2'b00;
+    parameter pll_pma_gbx_en = 1'b0;
+    parameter pll_pma_int_data_len = 1'b0;
+    parameter pll_pma_lvds_en = 1'b0;
+    parameter pll_pma_lvds_mux = 1'b0;
+    parameter pll_pma_mux_ckref = 1'b0;
+    parameter rx_usrclk_use_pcs_clk_2 = 1'b0;
+    parameter test_mode = 2'b00;
+    parameter tx_usrclk_use_pcs_clk_2 = 1'b0;
+endmodule
+

From 012f0e2952bec71cdf1182ac3393b3ac030ed23b Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 13 Mar 2024 09:26:19 +0100
Subject: [PATCH 282/499] memory blocks

---
 techlibs/nanoxplore/cells_bb.v     | 384 ----------------
 techlibs/nanoxplore/cells_bb_l.v   |  59 +++
 techlibs/nanoxplore/cells_bb_m.v   |  59 +++
 techlibs/nanoxplore/cells_bb_u.v   | 102 +++++
 techlibs/nanoxplore/cells_wrap_l.v | 193 +++++++++
 techlibs/nanoxplore/cells_wrap_m.v | 191 ++++++++
 techlibs/nanoxplore/cells_wrap_u.v | 674 +++++++++++++++++++++++++++++
 7 files changed, 1278 insertions(+), 384 deletions(-)

diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index 6b46317afea..a9d18edee17 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -3324,349 +3324,6 @@ module NX_RB_WRAP(EI_CK, EO_CK, CK, EO, EI, FI, FO);
     parameter outputContext = "";
 endmodule
 
-(* blackbox *)
-module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1
-, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6
-, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);
-    output COR;
-    output ERR;
-    input I1;
-    input I10;
-    input I11;
-    input I12;
-    input I13;
-    input I14;
-    input I15;
-    input I16;
-    input I2;
-    input I3;
-    input I4;
-    input I5;
-    input I6;
-    input I7;
-    input I8;
-    input I9;
-    output O1;
-    output O10;
-    output O11;
-    output O12;
-    output O13;
-    output O14;
-    output O15;
-    output O16;
-    output O2;
-    output O3;
-    output O4;
-    output O5;
-    output O6;
-    output O7;
-    output O8;
-    output O9;
-    input RA1;
-    input RA2;
-    input RA3;
-    input RA4;
-    input RA5;
-    input RA6;
-    input RCK;
-    input RE;
-    input WA1;
-    input WA2;
-    input WA3;
-    input WA4;
-    input WA5;
-    input WA6;
-    input WCK;
-    input WE;
-    parameter addr_mask = 5'b00000;
-    parameter mem_ctxt = "";
-    parameter rck_edge = 1'b0;
-    parameter wck_edge = 1'b0;
-    parameter we_mask = 1'b0;
-    parameter wea_mask = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_RFBDP_U_WRAP(WCK, WE, WEA, I, O, RA, WA);
-    input [17:0] I;
-    output [17:0] O;
-    input [4:0] RA;
-    input [4:0] WA;
-    input WCK;
-    input WE;
-    input WEA;
-    parameter mem_ctxt = "";
-    parameter wck_edge = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_RFBSP_U_WRAP(WCK, WE, WEA, I, O, WA);
-    input [17:0] I;
-    output [17:0] O;
-    input [4:0] WA;
-    input WCK;
-    input WE;
-    input WEA;
-    parameter mem_ctxt = "";
-    parameter wck_edge = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_RFB_L(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1
-, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6
-, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);
-    output COR;
-    output ERR;
-    input I1;
-    input I10;
-    input I11;
-    input I12;
-    input I13;
-    input I14;
-    input I15;
-    input I16;
-    input I2;
-    input I3;
-    input I4;
-    input I5;
-    input I6;
-    input I7;
-    input I8;
-    input I9;
-    output O1;
-    output O10;
-    output O11;
-    output O12;
-    output O13;
-    output O14;
-    output O15;
-    output O16;
-    output O2;
-    output O3;
-    output O4;
-    output O5;
-    output O6;
-    output O7;
-    output O8;
-    output O9;
-    input RA1;
-    input RA2;
-    input RA3;
-    input RA4;
-    input RA5;
-    input RA6;
-    input RCK;
-    input RE;
-    input WA1;
-    input WA2;
-    input WA3;
-    input WA4;
-    input WA5;
-    input WA6;
-    input WCK;
-    input WE;
-    parameter mem_ctxt = "";
-    parameter mode = 0;
-    parameter rck_edge = 1'b0;
-    parameter wck_edge = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_RFB_L_WRAP(RCK, WCK, COR, ERR, RE, WE, I, O, RA, WA);
-    output COR;
-    output ERR;
-    input [15:0] I;
-    output [15:0] O;
-    input [5:0] RA;
-    input RCK;
-    input RE;
-    input [5:0] WA;
-    input WCK;
-    input WE;
-    parameter mem_ctxt = "";
-    parameter mode = 0;
-    parameter rck_edge = 1'b0;
-    parameter wck_edge = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_RFB_M(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1
-, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6
-, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);
-    output COR;
-    output ERR;
-    input I1;
-    input I10;
-    input I11;
-    input I12;
-    input I13;
-    input I14;
-    input I15;
-    input I16;
-    input I2;
-    input I3;
-    input I4;
-    input I5;
-    input I6;
-    input I7;
-    input I8;
-    input I9;
-    output O1;
-    output O10;
-    output O11;
-    output O12;
-    output O13;
-    output O14;
-    output O15;
-    output O16;
-    output O2;
-    output O3;
-    output O4;
-    output O5;
-    output O6;
-    output O7;
-    output O8;
-    output O9;
-    input RA1;
-    input RA2;
-    input RA3;
-    input RA4;
-    input RA5;
-    input RA6;
-    input RCK;
-    input RE;
-    input WA1;
-    input WA2;
-    input WA3;
-    input WA4;
-    input WA5;
-    input WA6;
-    input WCK;
-    input WE;
-    parameter mem_ctxt = "";
-    parameter rck_edge = 1'b0;
-    parameter wck_edge = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20
-, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2, O3, O4, O5
-, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23, O24, O25, O26
-, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, WA1
-, WA2, WA3, WA4, WA5, WA6, WE, WEA);
-    input I1;
-    input I10;
-    input I11;
-    input I12;
-    input I13;
-    input I14;
-    input I15;
-    input I16;
-    input I17;
-    input I18;
-    input I19;
-    input I2;
-    input I20;
-    input I21;
-    input I22;
-    input I23;
-    input I24;
-    input I25;
-    input I26;
-    input I27;
-    input I28;
-    input I29;
-    input I3;
-    input I30;
-    input I31;
-    input I32;
-    input I33;
-    input I34;
-    input I35;
-    input I36;
-    input I4;
-    input I5;
-    input I6;
-    input I7;
-    input I8;
-    input I9;
-    output O1;
-    output O10;
-    output O11;
-    output O12;
-    output O13;
-    output O14;
-    output O15;
-    output O16;
-    output O17;
-    output O18;
-    output O19;
-    output O2;
-    output O20;
-    output O21;
-    output O22;
-    output O23;
-    output O24;
-    output O25;
-    output O26;
-    output O27;
-    output O28;
-    output O29;
-    output O3;
-    output O30;
-    output O31;
-    output O32;
-    output O33;
-    output O34;
-    output O35;
-    output O36;
-    output O4;
-    output O5;
-    output O6;
-    output O7;
-    output O8;
-    output O9;
-    input RA1;
-    input RA10;
-    input RA2;
-    input RA3;
-    input RA4;
-    input RA5;
-    input RA6;
-    input RA7;
-    input RA8;
-    input RA9;
-    input WA1;
-    input WA2;
-    input WA3;
-    input WA4;
-    input WA5;
-    input WA6;
-    input WCK;
-    input WE;
-    input WEA;
-    parameter mem_ctxt = "";
-    parameter mode = 0;
-    parameter wck_edge = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_RFB_WRAP(RCK, WCK, COR, ERR, RE, WE, I, O, RA, WA);
-    output COR;
-    output ERR;
-    input [15:0] I;
-    output [15:0] O;
-    input [5:0] RA;
-    input RCK;
-    input RE;
-    input [5:0] WA;
-    input WCK;
-    input WE;
-    parameter mem_ctxt = "";
-    parameter rck_edge = 1'b0;
-    parameter wck_edge = 1'b0;
-endmodule
-
 (* blackbox *)
 module NX_SER(FCK, SCK, R, IO, DCK, DRL, I, DS, DRA, DRI, DRO, DID);
     input DCK;
@@ -3784,47 +3441,6 @@ module NX_XFIFO_64x18(RCK, WCK, WE, WEA, WRSTI, RRSTI, I, O, WEQ, REQ, WAI, WAO,
     parameter wck_edge = 1'b0;
 endmodule
 
-(* blackbox *)
-module NX_XRFB_2R_1W(WCK, WE, WEA, I, AO, BO, WA, ARA, BRA);
-    output [17:0] AO;
-    input [4:0] ARA;
-    output [17:0] BO;
-    input [4:0] BRA;
-    input [17:0] I;
-    input [4:0] WA;
-    input WCK;
-    input WE;
-    input WEA;
-    parameter mem_ctxt = "";
-    parameter wck_edge = 1'b0;
-endmodule
-
-//(* blackbox *)
-//module NX_XRFB_32x36(WCK, WE, WEA, I, O, RA, WA);
-//    input [35:0] I;
-//    output [35:0] O;
-//    input [4:0] RA;
-//    input [4:0] WA;
-//    input WCK;
-//    input WE;
-//    input WEA;
-//    parameter mem_ctxt = "";
-//    parameter wck_edge = 1'b0;
-//endmodule
-//
-//(* blackbox *)
-//module NX_XRFB_64x18(WCK, WE, WEA, I, O, RA, WA);
-//    input [17:0] I;
-//    output [17:0] O;
-//    input [5:0] RA;
-//    input [5:0] WA;
-//    input WCK;
-//    input WE;
-//    input WEA;
-//    parameter mem_ctxt = "";
-//    parameter wck_edge = 1'b0;
-//endmodule
-
 (* blackbox *)
 module SMACC24x18_1DSP(clk, rst, A, B, Z);
     input [23:0] A;
diff --git a/techlibs/nanoxplore/cells_bb_l.v b/techlibs/nanoxplore/cells_bb_l.v
index cae2a0f2971..3ed9c1a89fb 100644
--- a/techlibs/nanoxplore/cells_bb_l.v
+++ b/techlibs/nanoxplore/cells_bb_l.v
@@ -1942,3 +1942,62 @@ module NX_PMA_L(CLK_USER_I, CLK_REF_I, PRE_SG_I, PRE_EN_I, PRE_IS_I1, PRE_IS_I2,
     parameter rx_pma_half_step = 1'b0;
 endmodule
 
+(* blackbox *)
+module NX_RFB_L(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1
+, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6
+, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);
+    output COR;
+    output ERR;
+    input I1;
+    input I10;
+    input I11;
+    input I12;
+    input I13;
+    input I14;
+    input I15;
+    input I16;
+    input I2;
+    input I3;
+    input I4;
+    input I5;
+    input I6;
+    input I7;
+    input I8;
+    input I9;
+    output O1;
+    output O10;
+    output O11;
+    output O12;
+    output O13;
+    output O14;
+    output O15;
+    output O16;
+    output O2;
+    output O3;
+    output O4;
+    output O5;
+    output O6;
+    output O7;
+    output O8;
+    output O9;
+    input RA1;
+    input RA2;
+    input RA3;
+    input RA4;
+    input RA5;
+    input RA6;
+    input RCK;
+    input RE;
+    input WA1;
+    input WA2;
+    input WA3;
+    input WA4;
+    input WA5;
+    input WA6;
+    input WCK;
+    input WE;
+    parameter mem_ctxt = "";
+    parameter mode = 0;
+    parameter rck_edge = 1'b0;
+    parameter wck_edge = 1'b0;
+endmodule
diff --git a/techlibs/nanoxplore/cells_bb_m.v b/techlibs/nanoxplore/cells_bb_m.v
index 620e9107d50..b3e94ac1597 100644
--- a/techlibs/nanoxplore/cells_bb_m.v
+++ b/techlibs/nanoxplore/cells_bb_m.v
@@ -1229,3 +1229,62 @@ module NX_IOM(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, CCK,
     parameter sel_clkw_rx2 = 2'b00;
 endmodule
 
+(* blackbox *)
+module NX_RFB_M(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1
+, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6
+, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);
+    output COR;
+    output ERR;
+    input I1;
+    input I10;
+    input I11;
+    input I12;
+    input I13;
+    input I14;
+    input I15;
+    input I16;
+    input I2;
+    input I3;
+    input I4;
+    input I5;
+    input I6;
+    input I7;
+    input I8;
+    input I9;
+    output O1;
+    output O10;
+    output O11;
+    output O12;
+    output O13;
+    output O14;
+    output O15;
+    output O16;
+    output O2;
+    output O3;
+    output O4;
+    output O5;
+    output O6;
+    output O7;
+    output O8;
+    output O9;
+    input RA1;
+    input RA2;
+    input RA3;
+    input RA4;
+    input RA5;
+    input RA6;
+    input RCK;
+    input RE;
+    input WA1;
+    input WA2;
+    input WA3;
+    input WA4;
+    input WA5;
+    input WA6;
+    input WCK;
+    input WE;
+    parameter mem_ctxt = "";
+    parameter rck_edge = 1'b0;
+    parameter wck_edge = 1'b0;
+endmodule
+
diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v
index 2bcaa532691..f828ebb3a79 100644
--- a/techlibs/nanoxplore/cells_bb_u.v
+++ b/techlibs/nanoxplore/cells_bb_u.v
@@ -2349,3 +2349,105 @@ module NX_PMA_U(CLK_TX_I, CLK_RX_I, CLK_REF_I, DC_E_I, DC_LCSN_I1, DC_LCSN_I2, D
     parameter tx_usrclk_use_pcs_clk_2 = 1'b0;
 endmodule
 
+(* blackbox *)
+module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20
+, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2, O3, O4, O5
+, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23, O24, O25, O26
+, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, WA1
+, WA2, WA3, WA4, WA5, WA6, WE, WEA);
+    input I1;
+    input I10;
+    input I11;
+    input I12;
+    input I13;
+    input I14;
+    input I15;
+    input I16;
+    input I17;
+    input I18;
+    input I19;
+    input I2;
+    input I20;
+    input I21;
+    input I22;
+    input I23;
+    input I24;
+    input I25;
+    input I26;
+    input I27;
+    input I28;
+    input I29;
+    input I3;
+    input I30;
+    input I31;
+    input I32;
+    input I33;
+    input I34;
+    input I35;
+    input I36;
+    input I4;
+    input I5;
+    input I6;
+    input I7;
+    input I8;
+    input I9;
+    output O1;
+    output O10;
+    output O11;
+    output O12;
+    output O13;
+    output O14;
+    output O15;
+    output O16;
+    output O17;
+    output O18;
+    output O19;
+    output O2;
+    output O20;
+    output O21;
+    output O22;
+    output O23;
+    output O24;
+    output O25;
+    output O26;
+    output O27;
+    output O28;
+    output O29;
+    output O3;
+    output O30;
+    output O31;
+    output O32;
+    output O33;
+    output O34;
+    output O35;
+    output O36;
+    output O4;
+    output O5;
+    output O6;
+    output O7;
+    output O8;
+    output O9;
+    input RA1;
+    input RA10;
+    input RA2;
+    input RA3;
+    input RA4;
+    input RA5;
+    input RA6;
+    input RA7;
+    input RA8;
+    input RA9;
+    input WA1;
+    input WA2;
+    input WA3;
+    input WA4;
+    input WA5;
+    input WA6;
+    input WCK;
+    input WE;
+    input WEA;
+    parameter mem_ctxt = "";
+    parameter mode = 0;
+    parameter wck_edge = 1'b0;
+endmodule
+
diff --git a/techlibs/nanoxplore/cells_wrap_l.v b/techlibs/nanoxplore/cells_wrap_l.v
index dc2e2a81cd0..57ad7e94761 100644
--- a/techlibs/nanoxplore/cells_wrap_l.v
+++ b/techlibs/nanoxplore/cells_wrap_l.v
@@ -1207,3 +1207,196 @@ module NX_DSP_L_WRAP(CCI, CCO, CI, CK, CO, CO37, CO57, OVF, R, RZ, WE, A, B, C,
   );
 endmodule
 
+module NX_RFB_L_WRAP(RCK, WCK, COR, ERR, RE, WE, I, O, RA, WA);
+    output COR;
+    output ERR;
+    input [15:0] I;
+    output [15:0] O;
+    input [5:0] RA;
+    input RCK;
+    input RE;
+    input [5:0] WA;
+    input WCK;
+    input WE;
+    parameter mem_ctxt = "";
+    parameter mode = 0;
+    parameter rck_edge = 1'b0;
+    parameter wck_edge = 1'b0;
+
+  NX_RFB_L #(
+    .mode(mode),
+    .rck_edge(rck_edge),
+    .wck_edge(wck_edge),
+    .mem_ctxt(mem_ctxt)
+  ) _TECHMAP_REPLACE_ (
+    .RCK(RCK),
+    .WCK(WCK),
+    .I1(I[0]),
+    .I2(I[1]),
+    .I3(I[2]),
+    .I4(I[3]),
+    .I5(I[4]),
+    .I6(I[5]),
+    .I7(I[6]),
+    .I8(I[7]),
+    .I9(I[8]),
+    .I10(I[9]),
+    .I11(I[10]),
+    .I12(I[11]),
+    .I13(I[12]),
+    .I14(I[13]),
+    .I15(I[14]),
+    .I16(I[15]),
+    .COR(COR),
+    .ERR(ERR),
+    .O1(O[0]),
+    .O2(O[1]),
+    .O3(O[2]),
+    .O4(O[3]),
+    .O5(O[4]),
+    .O6(O[5]),
+    .O7(O[6]),
+    .O8(O[7]),
+    .O9(O[8]),
+    .O10(O[9]),
+    .O11(O[10]),
+    .O12(O[11]),
+    .O13(O[12]),
+    .O14(O[13]),
+    .O15(O[14]),
+    .O16(O[15]),
+    .RA1(RA[0]),
+    .RA2(RA[1]),
+    .RA3(RA[2]),
+    .RA4(RA[3]),
+    .RA5(RA[4]),
+    .RA6(RA[5]),
+    .RE(RE),
+    .WA1(WA[0]),
+    .WA2(WA[1]),
+    .WA3(WA[2]),
+    .WA4(WA[3]),
+    .WA5(WA[4]),
+    .WA6(WA[5]),
+    .WE(WE)
+  );
+endmodule
+
+module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1
+, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6
+, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);
+    output COR;
+    output ERR;
+    input I1;
+    input I10;
+    input I11;
+    input I12;
+    input I13;
+    input I14;
+    input I15;
+    input I16;
+    input I2;
+    input I3;
+    input I4;
+    input I5;
+    input I6;
+    input I7;
+    input I8;
+    input I9;
+    output O1;
+    output O10;
+    output O11;
+    output O12;
+    output O13;
+    output O14;
+    output O15;
+    output O16;
+    output O2;
+    output O3;
+    output O4;
+    output O5;
+    output O6;
+    output O7;
+    output O8;
+    output O9;
+    input RA1;
+    input RA2;
+    input RA3;
+    input RA4;
+    input RA5;
+    input RA6;
+    input RCK;
+    input RE;
+    input WA1;
+    input WA2;
+    input WA3;
+    input WA4;
+    input WA5;
+    input WA6;
+    input WCK;
+    input WE;
+    parameter addr_mask = 5'b00000;
+    parameter mem_ctxt = "";
+    parameter rck_edge = 1'b0;
+    parameter wck_edge = 1'b0;
+    parameter we_mask = 1'b0;
+    parameter wea_mask = 1'b0;
+
+  NX_RFB_L #(
+    .mode(0),
+    .mem_ctxt(mem_ctxt),
+    .rck_edge(rck_edge),
+    .wck_edge(wck_edge)
+  ) _TECHMAP_REPLACE_ (
+    .RCK(RCK),
+    .WCK(WCK),
+    .I1(I1),
+    .I2(I2),
+    .I3(I3),
+    .I4(I4),
+    .I5(I5),
+    .I6(I6),
+    .I7(I7),
+    .I8(I8),
+    .I9(I9),
+    .I10(I10),
+    .I11(I11),
+    .I12(I12),
+    .I13(I13),
+    .I14(I14),
+    .I15(I15),
+    .I16(I16),
+    .COR(COR),
+    .ERR(ERR),
+    .O1(O1),
+    .O2(O2),
+    .O3(O3),
+    .O4(O4),
+    .O5(O5),
+    .O6(O6),
+    .O7(O7),
+    .O8(O8),
+    .O9(O9),
+    .O10(O10),
+    .O11(O11),
+    .O12(O12),
+    .O13(O13),
+    .O14(O14),
+    .O15(O15),
+    .O16(O16),
+    .RA1(RA1),
+    .RA2(RA2),
+    .RA3(RA3),
+    .RA4(RA4),
+    .RA5(RA5),
+    .RA6(RA6),
+    .RE(RE),
+    .WA1(WA1),
+    .WA2(WA2),
+    .WA3(WA3),
+    .WA4(WA4),
+    .WA5(WA5),
+    .WA6(WA6),
+    .WE(WE)
+  );
+endmodule
\ No newline at end of file
diff --git a/techlibs/nanoxplore/cells_wrap_m.v b/techlibs/nanoxplore/cells_wrap_m.v
index f66bc636e32..190196e2fbc 100644
--- a/techlibs/nanoxplore/cells_wrap_m.v
+++ b/techlibs/nanoxplore/cells_wrap_m.v
@@ -845,3 +845,194 @@ module NX_DSP_WRAP(CCI, CCO, CI, CK, CO, CO37, CO49, OVF, R, RZ, WE, A, B, C, D,
     .Z56(Z[55])
   );
 endmodule
+
+module NX_RFB_WRAP(RCK, WCK, COR, ERR, RE, WE, I, O, RA, WA);
+    output COR;
+    output ERR;
+    input [15:0] I;
+    output [15:0] O;
+    input [5:0] RA;
+    input RCK;
+    input RE;
+    input [5:0] WA;
+    input WCK;
+    input WE;
+    parameter mem_ctxt = "";
+    parameter rck_edge = 1'b0;
+    parameter wck_edge = 1'b0;
+
+  NX_RFB_M #(
+    .mem_ctxt(mem_ctxt),
+    .rck_edge(rck_edge),
+    .wck_edge(wck_edge)
+  ) _TECHMAP_REPLACE_ (
+    .RCK(RCK),
+    .WCK(WCK),
+    .I1(I[0]),
+    .I2(I[1]),
+    .I3(I[2]),
+    .I4(I[3]),
+    .I5(I[4]),
+    .I6(I[5]),
+    .I7(I[6]),
+    .I8(I[7]),
+    .I9(I[8]),
+    .I10(I[9]),
+    .I11(I[10]),
+    .I12(I[11]),
+    .I13(I[12]),
+    .I14(I[13]),
+    .I15(I[14]),
+    .I16(I[15]),
+    .COR(COR),
+    .ERR(ERR),
+    .O1(O[0]),
+    .O2(O[1]),
+    .O3(O[2]),
+    .O4(O[3]),
+    .O5(O[4]),
+    .O6(O[5]),
+    .O7(O[6]),
+    .O8(O[7]),
+    .O9(O[8]),
+    .O10(O[9]),
+    .O11(O[10]),
+    .O12(O[11]),
+    .O13(O[12]),
+    .O14(O[13]),
+    .O15(O[14]),
+    .O16(O[15]),
+    .RA1(RA[0]),
+    .RA2(RA[1]),
+    .RA3(RA[2]),
+    .RA4(RA[3]),
+    .RA5(RA[4]),
+    .RA6(RA[5]),
+    .RE(RE),
+    .WA1(WA[0]),
+    .WA2(WA[1]),
+    .WA3(WA[2]),
+    .WA4(WA[3]),
+    .WA5(WA[4]),
+    .WA6(WA[5]),
+    .WE(WE)
+  );
+endmodule
+
+module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1
+, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6
+, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);
+    output COR;
+    output ERR;
+    input I1;
+    input I10;
+    input I11;
+    input I12;
+    input I13;
+    input I14;
+    input I15;
+    input I16;
+    input I2;
+    input I3;
+    input I4;
+    input I5;
+    input I6;
+    input I7;
+    input I8;
+    input I9;
+    output O1;
+    output O10;
+    output O11;
+    output O12;
+    output O13;
+    output O14;
+    output O15;
+    output O16;
+    output O2;
+    output O3;
+    output O4;
+    output O5;
+    output O6;
+    output O7;
+    output O8;
+    output O9;
+    input RA1;
+    input RA2;
+    input RA3;
+    input RA4;
+    input RA5;
+    input RA6;
+    input RCK;
+    input RE;
+    input WA1;
+    input WA2;
+    input WA3;
+    input WA4;
+    input WA5;
+    input WA6;
+    input WCK;
+    input WE;
+    parameter addr_mask = 5'b00000;
+    parameter mem_ctxt = "";
+    parameter rck_edge = 1'b0;
+    parameter wck_edge = 1'b0;
+    parameter we_mask = 1'b0;
+    parameter wea_mask = 1'b0;
+
+  NX_RFB_M #(
+    .mem_ctxt(mem_ctxt),
+    .rck_edge(rck_edge),
+    .wck_edge(wck_edge)
+  ) _TECHMAP_REPLACE_ (
+    .RCK(RCK),
+    .WCK(WCK),
+    .I1(I1),
+    .I2(I2),
+    .I3(I3),
+    .I4(I4),
+    .I5(I5),
+    .I6(I6),
+    .I7(I7),
+    .I8(I8),
+    .I9(I9),
+    .I10(I10),
+    .I11(I11),
+    .I12(I12),
+    .I13(I13),
+    .I14(I14),
+    .I15(I15),
+    .I16(I16),
+    .COR(COR),
+    .ERR(ERR),
+    .O1(O1),
+    .O2(O2),
+    .O3(O3),
+    .O4(O4),
+    .O5(O5),
+    .O6(O6),
+    .O7(O7),
+    .O8(O8),
+    .O9(O9),
+    .O10(O10),
+    .O11(O11),
+    .O12(O12),
+    .O13(O13),
+    .O14(O14),
+    .O15(O15),
+    .O16(O16),
+    .RA1(RA1),
+    .RA2(RA2),
+    .RA3(RA3),
+    .RA4(RA4),
+    .RA5(RA5),
+    .RA6(RA6),
+    .RE(RE),
+    .WA1(WA1),
+    .WA2(WA2),
+    .WA3(WA3),
+    .WA4(WA4),
+    .WA5(WA5),
+    .WA6(WA6),
+    .WE(WE)
+  );
+endmodule
\ No newline at end of file
diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v
index be5561c3e09..eda3565b384 100644
--- a/techlibs/nanoxplore/cells_wrap_u.v
+++ b/techlibs/nanoxplore/cells_wrap_u.v
@@ -1459,3 +1459,677 @@ module NX_PLL_U_WRAP(R, REF, FBK, OSC, VCO, LDFO, REFO, PLL_LOCKED, PLL_LOCKEDA,
     .VCO(VCO)
   );
 endmodule
+
+module NX_RFBDP_U_WRAP(WCK, WE, WEA, I, O, RA, WA);
+    input [17:0] I;
+    output [17:0] O;
+    input [4:0] RA;
+    input [4:0] WA;
+    input WCK;
+    input WE;
+    input WEA;
+    parameter mem_ctxt = "";
+    parameter wck_edge = 1'b0;
+
+  NX_RFB_U #(
+    .mode(0),
+    .mem_ctxt(mem_ctxt),
+    .wck_edge(wck_edge)
+  ) _TECHMAP_REPLACE_ (
+    .WCK(WCK),
+    .I1(I[0]),
+    .I2(I[1]),
+    .I3(I[2]),
+    .I4(I[3]),
+    .I5(I[4]),
+    .I6(I[5]),
+    .I7(I[6]),
+    .I8(I[7]),
+    .I9(I[8]),
+    .I10(I[9]),
+    .I11(I[10]),
+    .I12(I[11]),
+    .I13(I[12]),
+    .I14(I[13]),
+    .I15(I[14]),
+    .I16(I[15]),
+    .I17(I[16]),
+    .I18(I[17]),
+    .I19(1'b0),
+    .I20(1'b0),
+    .I21(1'b0),
+    .I22(1'b0),
+    .I23(1'b0),
+    .I24(1'b0),
+    .I25(1'b0),
+    .I26(1'b0),
+    .I27(1'b0),
+    .I28(1'b0),
+    .I29(1'b0),
+    .I30(1'b0),
+    .I31(1'b0),
+    .I32(1'b0),
+    .I33(1'b0),
+    .I34(1'b0),
+    .I35(1'b0),
+    .I36(1'b0),
+    .O1(O[0]),
+    .O2(O[1]),
+    .O3(O[2]),
+    .O4(O[3]),
+    .O5(O[4]),
+    .O6(O[5]),
+    .O7(O[6]),
+    .O8(O[7]),
+    .O9(O[8]),
+    .O10(O[9]),
+    .O11(O[10]),
+    .O12(O[11]),
+    .O13(O[12]),
+    .O14(O[13]),
+    .O15(O[14]),
+    .O16(O[15]),
+    .O17(O[16]),
+    .O18(O[17]),
+    .RA1(RA[0]),
+    .RA2(RA[1]),
+    .RA3(RA[2]),
+    .RA4(RA[3]),
+    .RA5(RA[4]),
+    .RA6(1'b0),
+    .RA7(1'b0),
+    .RA8(1'b0),
+    .RA9(1'b0),
+    .RA10(1'b0),
+    .WA1(WA[0]),
+    .WA2(WA[1]),
+    .WA3(WA[2]),
+    .WA4(WA[3]),
+    .WA5(WA[4]),
+    .WA6(1'b0),
+    .WE(WE),
+    .WEA(WEA)
+  );
+
+endmodule
+
+module NX_RFBSP_U_WRAP(WCK, WE, WEA, I, O, WA);
+    input [17:0] I;
+    output [17:0] O;
+    input [4:0] WA;
+    input WCK;
+    input WE;
+    input WEA;
+    parameter mem_ctxt = "";
+    parameter wck_edge = 1'b0;
+
+  NX_RFB_U #(
+    .mode(1),
+    .mem_ctxt(mem_ctxt),
+    .wck_edge(wck_edge)
+  ) _TECHMAP_REPLACE_ (
+    .WCK(WCK),
+    .I1(I[0]),
+    .I2(I[1]),
+    .I3(I[2]),
+    .I4(I[3]),
+    .I5(I[4]),
+    .I6(I[5]),
+    .I7(I[6]),
+    .I8(I[7]),
+    .I9(I[8]),
+    .I10(I[9]),
+    .I11(I[10]),
+    .I12(I[11]),
+    .I13(I[12]),
+    .I14(I[13]),
+    .I15(I[14]),
+    .I16(I[15]),
+    .I17(I[16]),
+    .I18(I[17]),
+    .I19(1'b0),
+    .I20(1'b0),
+    .I21(1'b0),
+    .I22(1'b0),
+    .I23(1'b0),
+    .I24(1'b0),
+    .I25(1'b0),
+    .I26(1'b0),
+    .I27(1'b0),
+    .I28(1'b0),
+    .I29(1'b0),
+    .I30(1'b0),
+    .I31(1'b0),
+    .I32(1'b0),
+    .I33(1'b0),
+    .I34(1'b0),
+    .I35(1'b0),
+    .I36(1'b0),
+    .O1(O[0]),
+    .O2(O[1]),
+    .O3(O[2]),
+    .O4(O[3]),
+    .O5(O[4]),
+    .O6(O[5]),
+    .O7(O[6]),
+    .O8(O[7]),
+    .O9(O[8]),
+    .O10(O[9]),
+    .O11(O[10]),
+    .O12(O[11]),
+    .O13(O[12]),
+    .O14(O[13]),
+    .O15(O[14]),
+    .O16(O[15]),
+    .O17(O[16]),
+    .O18(O[17]),
+    .RA1(1'b0),
+    .RA2(1'b0),
+    .RA3(1'b0),
+    .RA4(1'b0),
+    .RA5(1'b0),
+    .RA6(1'b0),
+    .RA7(1'b0),
+    .RA8(1'b0),
+    .RA9(1'b0),
+    .RA10(1'b0),
+    .WA1(WA[0]),
+    .WA2(WA[1]),
+    .WA3(WA[2]),
+    .WA4(WA[3]),
+    .WA5(WA[4]),
+    .WA6(1'b0),
+    .WE(WE),
+    .WEA(WEA)
+  );
+endmodule
+
+module NX_XRFB_64x18(WCK, WE, WEA, I, O, RA, WA);
+    input [17:0] I;
+    output [17:0] O;
+    input [5:0] RA;
+    input [5:0] WA;
+    input WCK;
+    input WE;
+    input WEA;
+    parameter mem_ctxt = "";
+    parameter wck_edge = 1'b0;
+
+  NX_RFB_U #(
+    .mode(2),
+    .mem_ctxt(mem_ctxt),
+    .wck_edge(wck_edge)
+  ) _TECHMAP_REPLACE_ (
+    .WCK(WCK),
+    .I1(I[0]),
+    .I2(I[1]),
+    .I3(I[2]),
+    .I4(I[3]),
+    .I5(I[4]),
+    .I6(I[5]),
+    .I7(I[6]),
+    .I8(I[7]),
+    .I9(I[8]),
+    .I10(I[9]),
+    .I11(I[10]),
+    .I12(I[11]),
+    .I13(I[12]),
+    .I14(I[13]),
+    .I15(I[14]),
+    .I16(I[15]),
+    .I17(I[16]),
+    .I18(I[17]),
+    .I19(1'b0),
+    .I20(1'b0),
+    .I21(1'b0),
+    .I22(1'b0),
+    .I23(1'b0),
+    .I24(1'b0),
+    .I25(1'b0),
+    .I26(1'b0),
+    .I27(1'b0),
+    .I28(1'b0),
+    .I29(1'b0),
+    .I30(1'b0),
+    .I31(1'b0),
+    .I32(1'b0),
+    .I33(1'b0),
+    .I34(1'b0),
+    .I35(1'b0),
+    .I36(1'b0),
+    .O1(O[0]),
+    .O2(O[1]),
+    .O3(O[2]),
+    .O4(O[3]),
+    .O5(O[4]),
+    .O6(O[5]),
+    .O7(O[6]),
+    .O8(O[7]),
+    .O9(O[8]),
+    .O10(O[9]),
+    .O11(O[10]),
+    .O12(O[11]),
+    .O13(O[12]),
+    .O14(O[13]),
+    .O15(O[14]),
+    .O16(O[15]),
+    .O17(O[16]),
+    .O18(O[17]),
+    .RA1(RA[0]),
+    .RA2(RA[1]),
+    .RA3(RA[2]),
+    .RA4(RA[3]),
+    .RA5(RA[4]),
+    .RA6(RA[5]),
+    .RA7(1'b0),
+    .RA8(1'b0),
+    .RA9(1'b0),
+    .RA10(1'b0),
+    .WA1(WA[0]),
+    .WA2(WA[1]),
+    .WA3(WA[2]),
+    .WA4(WA[3]),
+    .WA5(WA[4]),
+    .WA6(WA[5]),
+    .WE(WE),
+    .WEA(WEA)
+  );
+endmodule
+
+module NX_XRFB_32x36(WCK, WE, WEA, I, O, RA, WA);
+    input [35:0] I;
+    output [35:0] O;
+    input [4:0] RA;
+    input [4:0] WA;
+    input WCK;
+    input WE;
+    input WEA;
+    parameter mem_ctxt = "";
+    parameter wck_edge = 1'b0;
+
+  NX_RFB_U #(
+    .mode(3),
+    .mem_ctxt(mem_ctxt),
+    .wck_edge(wck_edge)
+  ) _TECHMAP_REPLACE_ (
+    .WCK(WCK),
+    .I1(I[0]),
+    .I2(I[1]),
+    .I3(I[2]),
+    .I4(I[3]),
+    .I5(I[4]),
+    .I6(I[5]),
+    .I7(I[6]),
+    .I8(I[7]),
+    .I9(I[8]),
+    .I10(I[9]),
+    .I11(I[10]),
+    .I12(I[11]),
+    .I13(I[12]),
+    .I14(I[13]),
+    .I15(I[14]),
+    .I16(I[15]),
+    .I17(I[16]),
+    .I18(I[17]),
+    .I19(I[18]),
+    .I20(I[19]),
+    .I21(I[20]),
+    .I22(I[21]),
+    .I23(I[22]),
+    .I24(I[23]),
+    .I25(I[24]),
+    .I26(I[25]),
+    .I27(I[26]),
+    .I28(I[27]),
+    .I29(I[28]),
+    .I30(I[29]),
+    .I31(I[30]),
+    .I32(I[31]),
+    .I33(I[32]),
+    .I34(I[33]),
+    .I35(I[34]),
+    .I36(I[35]),
+    .O1(O[0]),
+    .O2(O[1]),
+    .O3(O[2]),
+    .O4(O[3]),
+    .O5(O[4]),
+    .O6(O[5]),
+    .O7(O[6]),
+    .O8(O[7]),
+    .O9(O[8]),
+    .O10(O[9]),
+    .O11(O[10]),
+    .O12(O[11]),
+    .O13(O[12]),
+    .O14(O[13]),
+    .O15(O[14]),
+    .O16(O[15]),
+    .O17(O[16]),
+    .O18(O[17]),
+    .O19(O[18]),
+    .O20(O[19]),
+    .O21(O[20]),
+    .O22(O[21]),
+    .O23(O[22]),
+    .O24(O[23]),
+    .O25(O[24]),
+    .O26(O[25]),
+    .O27(O[26]),
+    .O28(O[27]),
+    .O29(O[28]),
+    .O30(O[29]),
+    .O31(O[30]),
+    .O32(O[31]),
+    .O33(O[32]),
+    .O34(O[33]),
+    .O35(O[34]),
+    .O36(O[35]),
+    .RA1(RA[0]),
+    .RA2(RA[1]),
+    .RA3(RA[2]),
+    .RA4(RA[3]),
+    .RA5(RA[4]),
+    .RA6(1'b0),
+    .RA7(1'b0),
+    .RA8(1'b0),
+    .RA9(1'b0),
+    .RA10(1'b0),
+    .WA1(WA[0]),
+    .WA2(WA[1]),
+    .WA3(WA[2]),
+    .WA4(WA[3]),
+    .WA5(WA[4]),
+    .WA6(1'b0),
+    .WE(WE),
+    .WEA(WEA)
+  );
+endmodule
+
+module NX_XRFB_2R_1W(WCK, WE, WEA, I, AO, BO, WA, ARA, BRA);
+    output [17:0] AO;
+    input [4:0] ARA;
+    output [17:0] BO;
+    input [4:0] BRA;
+    input [17:0] I;
+    input [4:0] WA;
+    input WCK;
+    input WE;
+    input WEA;
+    parameter mem_ctxt = "";
+    parameter wck_edge = 1'b0;
+
+  NX_RFB_U #(
+    .mode(32'd4),
+    .mem_ctxt(mem_ctxt),
+    .wck_edge(wck_edge)
+  ) _TECHMAP_REPLACE_ (
+    .WCK(WCK),
+    .I1(I[0]),
+    .I2(I[1]),
+    .I3(I[2]),
+    .I4(I[3]),
+    .I5(I[4]),
+    .I6(I[5]),
+    .I7(I[6]),
+    .I8(I[7]),
+    .I9(I[8]),
+    .I10(I[9]),
+    .I11(I[10]),
+    .I12(I[11]),
+    .I13(I[12]),
+    .I14(I[13]),
+    .I15(I[14]),
+    .I16(I[15]),
+    .I17(I[16]),
+    .I18(I[17]),
+    .I19(1'b0),
+    .I20(1'b0),
+    .I21(1'b0),
+    .I22(1'b0),
+    .I23(1'b0),
+    .I24(1'b0),
+    .I25(1'b0),
+    .I26(1'b0),
+    .I27(1'b0),
+    .I28(1'b0),
+    .I29(1'b0),
+    .I30(1'b0),
+    .I31(1'b0),
+    .I32(1'b0),
+    .I33(1'b0),
+    .I34(1'b0),
+    .I35(1'b0),
+    .I36(1'b0),
+    .O1(AO[0]),
+    .O2(AO[1]),
+    .O3(AO[2]),
+    .O4(AO[3]),
+    .O5(AO[4]),
+    .O6(AO[5]),
+    .O7(AO[6]),
+    .O8(AO[7]),
+    .O9(AO[8]),
+    .O10(AO[9]),
+    .O11(AO[10]),
+    .O12(AO[11]),
+    .O13(AO[12]),
+    .O14(AO[13]),
+    .O15(AO[14]),
+    .O16(AO[15]),
+    .O17(AO[16]),
+    .O18(AO[17]),
+    .O19(BO[0]),
+    .O20(BO[1]),
+    .O21(BO[2]),
+    .O22(BO[3]),
+    .O23(BO[4]),
+    .O24(BO[5]),
+    .O25(BO[6]),
+    .O26(BO[7]),
+    .O27(BO[8]),
+    .O28(BO[9]),
+    .O29(BO[10]),
+    .O30(BO[11]),
+    .O31(BO[12]),
+    .O32(BO[13]),
+    .O33(BO[14]),
+    .O34(BO[15]),
+    .O35(BO[16]),
+    .O36(BO[17]),
+    .RA1(ARA[0]),
+    .RA2(ARA[1]),
+    .RA3(ARA[2]),
+    .RA4(ARA[3]),
+    .RA5(ARA[4]),
+    .RA6(BRA[0]),
+    .RA7(BRA[1]),
+    .RA8(BRA[2]),
+    .RA9(BRA[3]),
+    .RA10(BRA[4]),
+    .WA1(WA[0]),
+    .WA2(WA[1]),
+    .WA3(WA[2]),
+    .WA4(WA[3]),
+    .WA5(WA[4]),
+    .WA6(1'b0),
+    .WE(WE),
+    .WEA(WEA)
+  );
+endmodule
+
+module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1
+, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6
+, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);
+    output COR;
+    output ERR;
+    input I1;
+    input I10;
+    input I11;
+    input I12;
+    input I13;
+    input I14;
+    input I15;
+    input I16;
+    input I2;
+    input I3;
+    input I4;
+    input I5;
+    input I6;
+    input I7;
+    input I8;
+    input I9;
+    output O1;
+    output O10;
+    output O11;
+    output O12;
+    output O13;
+    output O14;
+    output O15;
+    output O16;
+    output O2;
+    output O3;
+    output O4;
+    output O5;
+    output O6;
+    output O7;
+    output O8;
+    output O9;
+    input RA1;
+    input RA2;
+    input RA3;
+    input RA4;
+    input RA5;
+    input RA6;
+    input RCK;
+    input RE;
+    input WA1;
+    input WA2;
+    input WA3;
+    input WA4;
+    input WA5;
+    input WA6;
+    input WCK;
+    input WE;
+    parameter addr_mask = 5'b00000;
+    parameter mem_ctxt = "";
+    parameter rck_edge = 1'b0;
+    parameter wck_edge = 1'b0;
+    parameter we_mask = 1'b0;
+    parameter wea_mask = 1'b0;
+
+  wire [15:0] D;
+  wire [15:0] Q;
+
+  NX_RFB_U #(
+    .mem_ctxt(mem_ctxt),
+    .mode(2),
+    .wck_edge(wck_edge)
+  ) _TECHMAP_REPLACE_ (
+    .WCK(WCK),
+    .I1(I1),
+    .I2(I2),
+    .I3(I3),
+    .I4(I4),
+    .I5(I5),
+    .I6(I6),
+    .I7(I7),
+    .I8(I8),
+    .I9(I9),
+    .I10(I10),
+    .I11(I11),
+    .I12(I12),
+    .I13(I13),
+    .I14(I14),
+    .I15(I15),
+    .I16(I16),
+    .I17(1'b0),
+    .I18(1'b0),
+    .I19(1'b0),
+    .I20(1'b0),
+    .I21(1'b0),
+    .I22(1'b0),
+    .I23(1'b0),
+    .I24(1'b0),
+    .I25(1'b0),
+    .I26(1'b0),
+    .I27(1'b0),
+    .I28(1'b0),
+    .I29(1'b0),
+    .I30(1'b0),
+    .I31(1'b0),
+    .I32(1'b0),
+    .I33(1'b0),
+    .I34(1'b0),
+    .I35(1'b0),
+    .I36(1'b0),
+    .O1(D[0]),
+    .O2(D[1]),
+    .O3(D[2]),
+    .O4(D[3]),
+    .O5(D[4]),
+    .O6(D[5]),
+    .O7(D[6]),
+    .O8(D[7]),
+    .O9(D[8]),
+    .O10(D[9]),
+    .O11(D[10]),
+    .O12(D[11]),
+    .O13(D[12]),
+    .O14(D[13]),
+    .O15(D[14]),
+    .O16(D[15]),
+    .RA1(RA1),
+    .RA2(RA2),
+    .RA3(RA3),
+    .RA4(RA4),
+    .RA5(RA5),
+    .RA6(RA6),
+    .RA7(1'b0),
+    .RA8(1'b0),
+    .RA9(1'b0),
+    .RA10(1'b0),
+    .WA1(WA1),
+    .WA2(WA2),
+    .WA3(WA3),
+    .WA4(WA4),
+    .WA5(WA5),
+    .WA6(WA6),
+    .WE(WE),
+    .WEA(1'b0)
+  );
+
+  genvar i;
+  generate for (i = 0; i < 16; i = i + 1) begin:q_reg
+    NX_DFF #(
+      .dff_edge(rck_edge),
+      .dff_init(1'b0),
+      .dff_load(1'b1)
+    ) out_reg_i (
+        .CK(RCK),
+        .I(D[i]),
+        .L(RE),
+        .R(1'b0),
+        .O(Q[i])
+    );
+  end endgenerate;
+  assign O1=Q[0];
+  assign O2=Q[1];
+  assign O3=Q[2];
+  assign O4=Q[3];
+  assign O5=Q[4];
+  assign O6=Q[5];
+  assign O7=Q[6];
+  assign O8=Q[7];
+  assign O9=Q[8];
+  assign O10=Q[9];
+  assign O11=Q[10];
+  assign O12=Q[11];
+  assign O13=Q[12];
+  assign O14=Q[13];
+  assign O15=Q[14];
+  assign O16=Q[15];
+
+  assign COR=1'b0;
+  assign ERR=1'b0;
+endmodule

From 8f42d6dacea3ea3fab5862ecb6ac77f33b28a90e Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 13 Mar 2024 09:48:16 +0100
Subject: [PATCH 283/499] fifo

---
 techlibs/nanoxplore/cells_bb.v     | 198 ---------------
 techlibs/nanoxplore/cells_bb_u.v   | 127 ++++++++++
 techlibs/nanoxplore/cells_wrap_u.v | 386 +++++++++++++++++++++++++++++
 3 files changed, 513 insertions(+), 198 deletions(-)

diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index a9d18edee17..e5207ad3441 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -165,158 +165,6 @@ module NX_ECC(CKD, CHK, COR, ERR);
     output ERR;
 endmodule
 
-(* blackbox *)
-module NX_FIFO_DPREG(RCK, WCK, WE, WEA, WRSTI, WRSTO, WEQ, RRSTI, RRSTO, REQ, I, O, WAI, WAO, RAI, RAO);
-    input [17:0] I;
-    output [17:0] O;
-    input [5:0] RAI;
-    output [5:0] RAO;
-    input RCK;
-    output REQ;
-    input RRSTI;
-    output RRSTO;
-    input [5:0] WAI;
-    output [5:0] WAO;
-    input WCK;
-    input WE;
-    input WEA;
-    output WEQ;
-    input WRSTI;
-    output WRSTO;
-    parameter rck_edge = 1'b0;
-    parameter read_addr_inv = 6'b000000;
-    parameter use_read_arst = 1'b0;
-    parameter use_write_arst = 1'b0;
-    parameter wck_edge = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_FIFO_U(RCK, WCK, WE, WEA, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17
-, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2
-, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23
-, O24, O25, O26, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, WRSTI, WAI1, WAI2, WAI3, WAI4, WAI5, WAI6, WAI7
-, WRSTO, WAO1, WAO2, WAO3, WAO4, WAO5, WAO6, WAO7, WEQ1, WEQ2, RRSTI, RAI1, RAI2, RAI3, RAI4, RAI5, RAI6, RAI7, RRSTO, RAO1, RAO2
-, RAO3, RAO4, RAO5, RAO6, RAO7, REQ1, REQ2);
-    input I1;
-    input I10;
-    input I11;
-    input I12;
-    input I13;
-    input I14;
-    input I15;
-    input I16;
-    input I17;
-    input I18;
-    input I19;
-    input I2;
-    input I20;
-    input I21;
-    input I22;
-    input I23;
-    input I24;
-    input I25;
-    input I26;
-    input I27;
-    input I28;
-    input I29;
-    input I3;
-    input I30;
-    input I31;
-    input I32;
-    input I33;
-    input I34;
-    input I35;
-    input I36;
-    input I4;
-    input I5;
-    input I6;
-    input I7;
-    input I8;
-    input I9;
-    output O1;
-    output O10;
-    output O11;
-    output O12;
-    output O13;
-    output O14;
-    output O15;
-    output O16;
-    output O17;
-    output O18;
-    output O19;
-    output O2;
-    output O20;
-    output O21;
-    output O22;
-    output O23;
-    output O24;
-    output O25;
-    output O26;
-    output O27;
-    output O28;
-    output O29;
-    output O3;
-    output O30;
-    output O31;
-    output O32;
-    output O33;
-    output O34;
-    output O35;
-    output O36;
-    output O4;
-    output O5;
-    output O6;
-    output O7;
-    output O8;
-    output O9;
-    input RAI1;
-    input RAI2;
-    input RAI3;
-    input RAI4;
-    input RAI5;
-    input RAI6;
-    input RAI7;
-    output RAO1;
-    output RAO2;
-    output RAO3;
-    output RAO4;
-    output RAO5;
-    output RAO6;
-    output RAO7;
-    input RCK;
-    output REQ1;
-    output REQ2;
-    input RRSTI;
-    output RRSTO;
-    input WAI1;
-    input WAI2;
-    input WAI3;
-    input WAI4;
-    input WAI5;
-    input WAI6;
-    input WAI7;
-    output WAO1;
-    output WAO2;
-    output WAO3;
-    output WAO4;
-    output WAO5;
-    output WAO6;
-    output WAO7;
-    input WCK;
-    input WE;
-    input WEA;
-    output WEQ1;
-    output WEQ2;
-    input WRSTI;
-    output WRSTO;
-    parameter mode = 0;
-    parameter rck_edge = 1'b0;
-    parameter read_addr_inv = 7'b0000000;
-    parameter use_read_arst = 1'b0;
-    parameter use_write_arst = 1'b0;
-    parameter wck_edge = 1'b0;
-endmodule
-
 (* blackbox *)
 module NX_HSSL_L_FULL(hssl_clk_user_i, hssl_clk_ref_i, hssl_clock_o, usr_com_tx_pma_pre_sign_i, usr_com_tx_pma_pre_en_i, usr_com_tx_pma_main_sign_i, usr_com_rx_pma_m_eye_i, usr_com_tx_pma_post_sign_i, usr_pll_pma_rst_n_i, usr_main_rst_n_i, usr_calibrate_pma_en_i, usr_pcs_ctrl_pll_lock_en_i, usr_pcs_ctrl_ovs_en_i, usr_pll_lock_o, usr_calibrate_pma_out_o, pma_clk_ext_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i, usr_tx0_pma_clk_en_i, usr_tx0_busy_o, pma_tx0_o
 , usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_ctrl_el_buff_fifo_en_i, usr_rx0_rst_n_i, usr_rx0_pma_cdr_rst_i, usr_rx0_pma_ckgen_rst_n_i, usr_rx0_pma_pll_rst_n_i, usr_rx0_pma_loss_of_signal_o, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_busy_o, usr_rx0_pll_lock_o, pma_rx0_i, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_pma_clk_en_i, usr_tx1_busy_o, pma_tx1_o
@@ -3395,52 +3243,6 @@ module NX_SERDES(FCK, SCK, RTX, RRX, CI, CCK, CL, CR, IO, DCK, DRL, DIG, FZ, FLD
     parameter weakTermination = "";
 endmodule
 
-(* blackbox *)
-module NX_XFIFO_32x36(RCK, WCK, WE, WEA, WRSTI, WEQ, RRSTI, REQ, I, O, WAI, WAO, RAI, RAO);
-    input [35:0] I;
-    output [35:0] O;
-    input [5:0] RAI;
-    output [5:0] RAO;
-    input RCK;
-    output REQ;
-    input RRSTI;
-    input [5:0] WAI;
-    output [5:0] WAO;
-    input WCK;
-    input WE;
-    input WEA;
-    output WEQ;
-    input WRSTI;
-    parameter rck_edge = 1'b0;
-    parameter read_addr_inv = 7'b0000000;
-    parameter use_read_arst = 1'b0;
-    parameter use_write_arst = 1'b0;
-    parameter wck_edge = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_XFIFO_64x18(RCK, WCK, WE, WEA, WRSTI, RRSTI, I, O, WEQ, REQ, WAI, WAO, RAI, RAO);
-    input [17:0] I;
-    output [17:0] O;
-    input [6:0] RAI;
-    output [6:0] RAO;
-    input RCK;
-    output [1:0] REQ;
-    input RRSTI;
-    input [6:0] WAI;
-    output [6:0] WAO;
-    input WCK;
-    input WE;
-    input WEA;
-    output [1:0] WEQ;
-    input WRSTI;
-    parameter rck_edge = 1'b0;
-    parameter read_addr_inv = 7'b0000000;
-    parameter use_read_arst = 1'b0;
-    parameter use_write_arst = 1'b0;
-    parameter wck_edge = 1'b0;
-endmodule
-
 (* blackbox *)
 module SMACC24x18_1DSP(clk, rst, A, B, Z);
     input [23:0] A;
diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v
index f828ebb3a79..598eb8d2c9f 100644
--- a/techlibs/nanoxplore/cells_bb_u.v
+++ b/techlibs/nanoxplore/cells_bb_u.v
@@ -2451,3 +2451,130 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14
     parameter wck_edge = 1'b0;
 endmodule
 
+
+(* blackbox *)
+module NX_FIFO_U(RCK, WCK, WE, WEA, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17
+, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2
+, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23
+, O24, O25, O26, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, WRSTI, WAI1, WAI2, WAI3, WAI4, WAI5, WAI6, WAI7
+, WRSTO, WAO1, WAO2, WAO3, WAO4, WAO5, WAO6, WAO7, WEQ1, WEQ2, RRSTI, RAI1, RAI2, RAI3, RAI4, RAI5, RAI6, RAI7, RRSTO, RAO1, RAO2
+, RAO3, RAO4, RAO5, RAO6, RAO7, REQ1, REQ2);
+    input I1;
+    input I10;
+    input I11;
+    input I12;
+    input I13;
+    input I14;
+    input I15;
+    input I16;
+    input I17;
+    input I18;
+    input I19;
+    input I2;
+    input I20;
+    input I21;
+    input I22;
+    input I23;
+    input I24;
+    input I25;
+    input I26;
+    input I27;
+    input I28;
+    input I29;
+    input I3;
+    input I30;
+    input I31;
+    input I32;
+    input I33;
+    input I34;
+    input I35;
+    input I36;
+    input I4;
+    input I5;
+    input I6;
+    input I7;
+    input I8;
+    input I9;
+    output O1;
+    output O10;
+    output O11;
+    output O12;
+    output O13;
+    output O14;
+    output O15;
+    output O16;
+    output O17;
+    output O18;
+    output O19;
+    output O2;
+    output O20;
+    output O21;
+    output O22;
+    output O23;
+    output O24;
+    output O25;
+    output O26;
+    output O27;
+    output O28;
+    output O29;
+    output O3;
+    output O30;
+    output O31;
+    output O32;
+    output O33;
+    output O34;
+    output O35;
+    output O36;
+    output O4;
+    output O5;
+    output O6;
+    output O7;
+    output O8;
+    output O9;
+    input RAI1;
+    input RAI2;
+    input RAI3;
+    input RAI4;
+    input RAI5;
+    input RAI6;
+    input RAI7;
+    output RAO1;
+    output RAO2;
+    output RAO3;
+    output RAO4;
+    output RAO5;
+    output RAO6;
+    output RAO7;
+    input RCK;
+    output REQ1;
+    output REQ2;
+    input RRSTI;
+    output RRSTO;
+    input WAI1;
+    input WAI2;
+    input WAI3;
+    input WAI4;
+    input WAI5;
+    input WAI6;
+    input WAI7;
+    output WAO1;
+    output WAO2;
+    output WAO3;
+    output WAO4;
+    output WAO5;
+    output WAO6;
+    output WAO7;
+    input WCK;
+    input WE;
+    input WEA;
+    output WEQ1;
+    output WEQ2;
+    input WRSTI;
+    output WRSTO;
+    parameter mode = 0;
+    parameter rck_edge = 1'b0;
+    parameter read_addr_inv = 7'b0000000;
+    parameter use_read_arst = 1'b0;
+    parameter use_write_arst = 1'b0;
+    parameter wck_edge = 1'b0;
+endmodule
diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v
index eda3565b384..3c9eba1aa12 100644
--- a/techlibs/nanoxplore/cells_wrap_u.v
+++ b/techlibs/nanoxplore/cells_wrap_u.v
@@ -2133,3 +2133,389 @@ module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13,
   assign COR=1'b0;
   assign ERR=1'b0;
 endmodule
+
+module NX_FIFO_DPREG(RCK, WCK, WE, WEA, WRSTI, WRSTO, WEQ, RRSTI, RRSTO, REQ, I, O, WAI, WAO, RAI, RAO);
+    input [17:0] I;
+    output [17:0] O;
+    input [5:0] RAI;
+    output [5:0] RAO;
+    input RCK;
+    output REQ;
+    input RRSTI;
+    output RRSTO;
+    input [5:0] WAI;
+    output [5:0] WAO;
+    input WCK;
+    input WE;
+    input WEA;
+    output WEQ;
+    input WRSTI;
+    output WRSTO;
+    parameter rck_edge = 1'b0;
+    parameter read_addr_inv = 6'b000000;
+    parameter use_read_arst = 1'b0;
+    parameter use_write_arst = 1'b0;
+    parameter wck_edge = 1'b0;
+
+  NX_FIFO_U #(
+    .mode(0),
+    .wck_edge(wck_edge),
+    .rck_edge(rck_edge),
+    .read_addr_inv(read_addr_inv),
+    .use_write_arst(use_write_arst),
+    .use_read_arst(use_read_arst)
+  ) _TECHMAP_REPLACE_ (
+    .RCK(RCK),
+    .WCK(WCK),
+    .WE(WE),
+    .WEA(WEA),
+    .I1(I[0]),
+    .I2(I[1]),
+    .I3(I[2]),
+    .I4(I[3]),
+    .I5(I[4]),
+    .I6(I[5]),
+    .I7(I[6]),
+    .I8(I[7]),
+    .I9(I[8]),
+    .I10(I[9]),
+    .I11(I[10]),
+    .I12(I[11]),
+    .I13(I[12]),
+    .I14(I[13]),
+    .I15(I[14]),
+    .I16(I[15]),
+    .I17(I[16]),
+    .I18(I[17]),
+    .I19(1'b0),
+    .I20(1'b0),
+    .I21(1'b0),
+    .I22(1'b0),
+    .I23(1'b0),
+    .I24(1'b0),
+    .I25(1'b0),
+    .I26(1'b0),
+    .I27(1'b0),
+    .I28(1'b0),
+    .I29(1'b0),
+    .I30(1'b0),
+    .I31(1'b0),
+    .I32(1'b0),
+    .I33(1'b0),
+    .I34(1'b0),
+    .I35(1'b0),
+    .I36(1'b0),
+    .O1(O[0]),
+    .O2(O[1]),
+    .O3(O[2]),
+    .O4(O[3]),
+    .O5(O[4]),
+    .O6(O[5]),
+    .O7(O[6]),
+    .O8(O[7]),
+    .O9(O[8]),
+    .O10(O[9]),
+    .O11(O[10]),
+    .O12(O[11]),
+    .O13(O[12]),
+    .O14(O[13]),
+    .O15(O[14]),
+    .O16(O[15]),
+    .O17(O[16]),
+    .O18(O[17]),
+    .WRSTI(WRSTI),
+    .WAI1(WAI[0]),
+    .WAI2(WAI[1]),
+    .WAI3(WAI[2]),
+    .WAI4(WAI[3]),
+    .WAI5(WAI[4]),
+    .WAI6(WAI[5]),
+    .WAI7(1'b0),
+    .WRSTO(WRSTO),
+    .WAO1(WAO[0]),
+    .WAO2(WAO[1]),
+    .WAO3(WAO[2]),
+    .WAO4(WAO[3]),
+    .WAO5(WAO[4]),
+    .WAO6(WAO[5]),
+    .WEQ1(WEQ),
+    .RRSTI(RRSTI),
+    .RAI1(RAI[0]),
+    .RAI2(RAI[1]),
+    .RAI3(RAI[2]),
+    .RAI4(RAI[3]),
+    .RAI5(RAI[4]),
+    .RAI6(RAI[5]),
+    .RAI7(1'b0),
+    .RRSTO(RRSTO),
+    .RAO1(RAO[0]),
+    .RAO2(RAO[1]),
+    .RAO3(RAO[2]),
+    .RAO4(RAO[3]),
+    .RAO5(RAO[4]),
+    .RAO6(RAO[5]),
+    .REQ1(REQ)
+  );
+endmodule
+
+module NX_XFIFO_64x18(RCK, WCK, WE, WEA, WRSTI, RRSTI, I, O, WEQ, REQ, WAI, WAO, RAI, RAO);
+    input [17:0] I;
+    output [17:0] O;
+    input [6:0] RAI;
+    output [6:0] RAO;
+    input RCK;
+    output [1:0] REQ;
+    input RRSTI;
+    input [6:0] WAI;
+    output [6:0] WAO;
+    input WCK;
+    input WE;
+    input WEA;
+    output [1:0] WEQ;
+    input WRSTI;
+    parameter rck_edge = 1'b0;
+    parameter read_addr_inv = 7'b0000000;
+    parameter use_read_arst = 1'b0;
+    parameter use_write_arst = 1'b0;
+    parameter wck_edge = 1'b0;
+
+  NX_FIFO_U #(
+    .mode(1),
+    .wck_edge(wck_edge),
+    .rck_edge(rck_edge),
+    .read_addr_inv(read_addr_inv),
+    .use_write_arst(use_write_arst),
+    .use_read_arst(use_read_arst)
+  ) _TECHMAP_REPLACE_ (
+    .RCK(RCK),
+    .WCK(WCK),
+    .WE(WE),
+    .WEA(WEA),
+    .I1(I[0]),
+    .I2(I[1]),
+    .I3(I[2]),
+    .I4(I[3]),
+    .I5(I[4]),
+    .I6(I[5]),
+    .I7(I[6]),
+    .I8(I[7]),
+    .I9(I[8]),
+    .I10(I[9]),
+    .I11(I[10]),
+    .I12(I[11]),
+    .I13(I[12]),
+    .I14(I[13]),
+    .I15(I[14]),
+    .I16(I[15]),
+    .I17(I[16]),
+    .I18(I[17]),
+    .I19(1'b0),
+    .I20(1'b0),
+    .I21(1'b0),
+    .I22(1'b0),
+    .I23(1'b0),
+    .I24(1'b0),
+    .I25(1'b0),
+    .I26(1'b0),
+    .I27(1'b0),
+    .I28(1'b0),
+    .I29(1'b0),
+    .I30(1'b0),
+    .I31(1'b0),
+    .I32(1'b0),
+    .I33(1'b0),
+    .I34(1'b0),
+    .I35(1'b0),
+    .I36(1'b0),
+    .O1(O[0]),
+    .O2(O[1]),
+    .O3(O[2]),
+    .O4(O[3]),
+    .O5(O[4]),
+    .O6(O[5]),
+    .O7(O[6]),
+    .O8(O[7]),
+    .O9(O[8]),
+    .O10(O[9]),
+    .O11(O[10]),
+    .O12(O[11]),
+    .O13(O[12]),
+    .O14(O[13]),
+    .O15(O[14]),
+    .O16(O[15]),
+    .O17(O[16]),
+    .O18(O[17]),
+    .WRSTI(WRSTI),
+    .WAI1(WAI[0]),
+    .WAI2(WAI[1]),
+    .WAI3(WAI[2]),
+    .WAI4(WAI[3]),
+    .WAI5(WAI[4]),
+    .WAI6(WAI[5]),
+    .WAI7(WAI[6]),
+    .WAO1(WAO[0]),
+    .WAO2(WAO[1]),
+    .WAO3(WAO[2]),
+    .WAO4(WAO[3]),
+    .WAO5(WAO[4]),
+    .WAO6(WAO[5]),
+    .WAO7(WAO[6]),
+    .WEQ1(WEQ[0]),
+    .WEQ2(WEQ[1]),
+    .RRSTI(RRSTI),
+    .RAI1(RAI[0]),
+    .RAI2(RAI[1]),
+    .RAI3(RAI[2]),
+    .RAI4(RAI[3]),
+    .RAI5(RAI[4]),
+    .RAI6(RAI[5]),
+    .RAI7(RAI[6]),
+    .RAO1(RAO[0]),
+    .RAO2(RAO[1]),
+    .RAO3(RAO[2]),
+    .RAO4(RAO[3]),
+    .RAO5(RAO[4]),
+    .RAO6(RAO[5]),
+    .RAO7(RAO[6]),
+    .REQ1(REQ[0]),
+    .REQ2(REQ[1])
+  );
+endmodule
+
+module NX_XFIFO_32x36(RCK, WCK, WE, WEA, WRSTI, WEQ, RRSTI, REQ, I, O, WAI, WAO, RAI, RAO);
+    input [35:0] I;
+    output [35:0] O;
+    input [5:0] RAI;
+    output [5:0] RAO;
+    input RCK;
+    output REQ;
+    input RRSTI;
+    input [5:0] WAI;
+    output [5:0] WAO;
+    input WCK;
+    input WE;
+    input WEA;
+    output WEQ;
+    input WRSTI;
+    parameter rck_edge = 1'b0;
+    parameter read_addr_inv = 7'b0000000;
+    parameter use_read_arst = 1'b0;
+    parameter use_write_arst = 1'b0;
+    parameter wck_edge = 1'b0;
+
+  NX_FIFO_U #(
+    .mode(2),
+    .wck_edge(wck_edge),
+    .rck_edge(rck_edge),
+    .read_addr_inv(read_addr_inv),
+    .use_write_arst(use_write_arst),
+    .use_read_arst(use_read_arst)
+  ) _TECHMAP_REPLACE_ (
+    .RCK(RCK),
+    .WCK(WCK),
+    .WE(WE),
+    .WEA(WEA),
+    .I1(I[0]),
+    .I2(I[1]),
+    .I3(I[2]),
+    .I4(I[3]),
+    .I5(I[4]),
+    .I6(I[5]),
+    .I7(I[6]),
+    .I8(I[7]),
+    .I9(I[8]),
+    .I10(I[9]),
+    .I11(I[10]),
+    .I12(I[11]),
+    .I13(I[12]),
+    .I14(I[13]),
+    .I15(I[14]),
+    .I16(I[15]),
+    .I17(I[16]),
+    .I18(I[17]),
+    .I19(I[18]),
+    .I20(I[19]),
+    .I21(I[20]),
+    .I22(I[21]),
+    .I23(I[22]),
+    .I24(I[23]),
+    .I25(I[24]),
+    .I26(I[25]),
+    .I27(I[26]),
+    .I28(I[27]),
+    .I29(I[28]),
+    .I30(I[29]),
+    .I31(I[30]),
+    .I32(I[31]),
+    .I33(I[32]),
+    .I34(I[33]),
+    .I35(I[34]),
+    .I36(I[35]),
+    .O1(O[0]),
+    .O2(O[1]),
+    .O3(O[2]),
+    .O4(O[3]),
+    .O5(O[4]),
+    .O6(O[5]),
+    .O7(O[6]),
+    .O8(O[7]),
+    .O9(O[8]),
+    .O10(O[9]),
+    .O11(O[10]),
+    .O12(O[11]),
+    .O13(O[12]),
+    .O14(O[13]),
+    .O15(O[14]),
+    .O16(O[15]),
+    .O17(O[16]),
+    .O18(O[17]),
+    .O19(O[18]),
+    .O20(O[19]),
+    .O21(O[20]),
+    .O22(O[21]),
+    .O23(O[22]),
+    .O24(O[23]),
+    .O25(O[24]),
+    .O26(O[25]),
+    .O27(O[26]),
+    .O28(O[27]),
+    .O29(O[28]),
+    .O30(O[29]),
+    .O31(O[30]),
+    .O32(O[31]),
+    .O33(O[32]),
+    .O34(O[33]),
+    .O35(O[34]),
+    .O36(O[35]),
+    .WRSTI(WRSTI),
+    .WAI1(WAI[0]),
+    .WAI2(WAI[1]),
+    .WAI3(WAI[2]),
+    .WAI4(WAI[3]),
+    .WAI5(WAI[4]),
+    .WAI6(WAI[5]),
+    .WAI7(1'b0),
+    .WAO1(WAO[0]),
+    .WAO2(WAO[1]),
+    .WAO3(WAO[2]),
+    .WAO4(WAO[3]),
+    .WAO5(WAO[4]),
+    .WAO6(WAO[5]),
+    .WEQ1(WEQ),
+    .RRSTI(RRSTI),
+    .RAI1(RAI[0]),
+    .RAI2(RAI[1]),
+    .RAI3(RAI[2]),
+    .RAI4(RAI[3]),
+    .RAI5(RAI[4]),
+    .RAI6(RAI[5]),
+    .RAI7(1'b0),
+    .RAO1(RAO[0]),
+    .RAO2(RAO[1]),
+    .RAO3(RAO[2]),
+    .RAO4(RAO[3]),
+    .RAO5(RAO[4]),
+    .RAO6(RAO[5]),
+    .REQ1(REQ)
+  );
+endmodule
\ No newline at end of file

From f836de6bccd250ff0183dec521523c1a0c9bc4a2 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 13 Mar 2024 10:07:54 +0100
Subject: [PATCH 284/499] mark DSPs as TODOs for now

---
 techlibs/nanoxplore/cells_bb.v     | 195 -----------------------------
 techlibs/nanoxplore/cells_wrap_l.v |  13 +-
 techlibs/nanoxplore/cells_wrap_u.v | 187 ++++++++++++++++++++++++++-
 3 files changed, 198 insertions(+), 197 deletions(-)

diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index e5207ad3441..2b79cc4721e 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -1,50 +1,3 @@
-(* blackbox *)
-module ACC84_2DSP(clk, rst, X, Z);
-    input [83:0] X;
-    output [84:0] Z;
-    input clk;
-    input rst;
-    parameter g_pipe = 2;
-endmodule
-
-(* blackbox *)
-module ACC92_2DSP(clk, rst, X, Z);
-    input [55:0] X;
-    output [91:0] Z;
-    input clk;
-    input rst;
-    parameter g_pipe = 2;
-endmodule
-
-(* blackbox *)
-module ACC98_2DSP(clk, rst, X, Z);
-    input [55:0] X;
-    output [97:0] Z;
-    input clk;
-    input rst;
-    parameter g_pipe = 2;
-endmodule
-
-(* blackbox *)
-module ADD84_1DSP_2CYCLES(clk, rst, X, Y, Z);
-    input [41:0] X;
-    input [41:0] Y;
-    output [84:0] Z;
-    input clk;
-    input rst;
-    parameter piped = "true";
-endmodule
-
-(* blackbox *)
-module ADD84_2DSP(clk, rst, X, Y, Z);
-    input [83:0] X;
-    input [83:0] Y;
-    output [84:0] Z;
-    input clk;
-    input rst;
-    parameter piped = "true";
-endmodule
-
 (* blackbox *)
 module NX_BD(I, O);
     input I;
@@ -3242,151 +3195,3 @@ module NX_SERDES(FCK, SCK, RTX, RRX, CI, CCK, CL, CR, IO, DCK, DRL, DIG, FZ, FLD
     parameter turbo = "";
     parameter weakTermination = "";
 endmodule
-
-(* blackbox *)
-module SMACC24x18_1DSP(clk, rst, A, B, Z);
-    input [23:0] A;
-    input [17:0] B;
-    output [55:0] Z;
-    input clk;
-    input rst;
-    parameter g_pipe = 1;
-endmodule
-
-(* blackbox *)
-module SMACC24x32_2DSP(clk, rst, A, B, Z);
-    input [23:0] A;
-    input [31:0] B;
-    output [55:0] Z;
-    input clk;
-    input rst;
-    parameter g_pipe = 1;
-endmodule
-
-(* blackbox *)
-module SMACC24x32_enable_2DSP(clk, rst, we, A, B, Z);
-    input [23:0] A;
-    input [31:0] B;
-    output [55:0] Z;
-    input clk;
-    input rst;
-    input we;
-    parameter STAGE_1 = "false";
-    parameter STAGE_2 = "false";
-    parameter STAGE_3 = "false";
-    parameter STAGE_4 = "false";
-endmodule
-
-(* blackbox *)
-module SMUL24x32_2DSP(clk, rst, A, B, Z);
-    input [23:0] A;
-    input [31:0] B;
-    output [54:0] Z;
-    input clk;
-    input rst;
-    parameter g_pipe = 1;
-endmodule
-
-(* blackbox *)
-module SMUL24x32_2DSP_ACC_2DSP(clk, rst, we, A, B, Z);
-    input [23:0] A;
-    input [31:0] B;
-    output [97:0] Z;
-    input clk;
-    input rst;
-    input we;
-    parameter STAGE_1 = "false";
-    parameter STAGE_2 = "false";
-    parameter STAGE_3 = "false";
-endmodule
-
-(* blackbox *)
-module SMUL24x32_2DSP_ACC_2DSP_L(clk, rst, we, A, B, Z);
-    input [23:0] A;
-    input [31:0] B;
-    output [91:0] Z;
-    input clk;
-    input rst;
-    input we;
-endmodule
-
-(* blackbox *)
-module SMUL47x35_4DSP(clk, rst, A, B, Z);
-    input [46:0] A;
-    input [34:0] B;
-    output [80:0] Z;
-    input clk;
-    input rst;
-    parameter piped = "true";
-endmodule
-
-(* blackbox *)
-module UMADD24_2DSP(clk, rst, A, B, C, Z);
-    input [23:0] A;
-    input [31:0] B;
-    input [55:0] C;
-    output [55:0] Z;
-    input clk;
-    input rst;
-    parameter piped = "true";
-endmodule
-
-(* blackbox *)
-module UMUL24x32_1DSP_2CYCLES(clk, rst, A, B, Z);
-    input [23:0] A;
-    input [15:0] B;
-    output [55:0] Z;
-    input clk;
-    input rst;
-    parameter piped = "true";
-endmodule
-
-(* blackbox *)
-module UMUL24x32_2DSP(clk, rst, A, B, Z);
-    input [23:0] A;
-    input [31:0] B;
-    output [55:0] Z;
-    input clk;
-    input rst;
-    parameter piped = "true";
-endmodule
-
-(* blackbox *)
-module UMUL24x36_1DSP_2CYCLES(clk, rst, A, B, Z);
-    input [23:0] A;
-    input [17:0] B;
-    output [59:0] Z;
-    input clk;
-    input rst;
-    parameter piped = "true";
-endmodule
-
-(* blackbox *)
-module UMUL24x36_2DSP(clk, rst, A, B, Z);
-    input [23:0] A;
-    input [35:0] B;
-    output [59:0] Z;
-    input clk;
-    input rst;
-    parameter piped = "true";
-endmodule
-
-(* blackbox *)
-module UMUL48x36_1DSP_4CYCLES(clk, rst, A, B, Z);
-    input [23:0] A;
-    input [17:0] B;
-    output [83:0] Z;
-    input clk;
-    input rst;
-    parameter piped = "true";
-endmodule
-
-(* blackbox *)
-module UMUL48x36_4DSP(clk, rst, A, B, Z);
-    input [47:0] A;
-    input [35:0] B;
-    output [83:0] Z;
-    input clk;
-    input rst;
-    parameter piped = "true";
-endmodule
diff --git a/techlibs/nanoxplore/cells_wrap_l.v b/techlibs/nanoxplore/cells_wrap_l.v
index 57ad7e94761..24430052f94 100644
--- a/techlibs/nanoxplore/cells_wrap_l.v
+++ b/techlibs/nanoxplore/cells_wrap_l.v
@@ -1399,4 +1399,15 @@ module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13,
     .WA6(WA6),
     .WE(WE)
   );
-endmodule
\ No newline at end of file
+endmodule
+
+// TODO
+module SMUL24x32_2DSP_ACC_2DSP_L(clk, rst, we, A, B, Z);
+    input [23:0] A;
+    input [31:0] B;
+    output [91:0] Z;
+    input clk;
+    input rst;
+    input we;
+endmodule
+
diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v
index 3c9eba1aa12..b07c9e46bd2 100644
--- a/techlibs/nanoxplore/cells_wrap_u.v
+++ b/techlibs/nanoxplore/cells_wrap_u.v
@@ -2518,4 +2518,189 @@ module NX_XFIFO_32x36(RCK, WCK, WE, WEA, WRSTI, WEQ, RRSTI, REQ, I, O, WAI, WAO,
     .RAO6(RAO[5]),
     .REQ1(REQ)
   );
-endmodule
\ No newline at end of file
+endmodule
+
+//TODO
+module ACC84_2DSP(clk, rst, X, Z);
+    input [83:0] X;
+    output [84:0] Z;
+    input clk;
+    input rst;
+    parameter g_pipe = 2;
+endmodule
+
+//TODO
+module ACC92_2DSP(clk, rst, X, Z);
+    input [55:0] X;
+    output [91:0] Z;
+    input clk;
+    input rst;
+    parameter g_pipe = 2;
+endmodule
+
+//TODO
+module ACC98_2DSP(clk, rst, X, Z);
+    input [55:0] X;
+    output [97:0] Z;
+    input clk;
+    input rst;
+    parameter g_pipe = 2;
+endmodule
+
+//TODO
+module ADD84_1DSP_2CYCLES(clk, rst, X, Y, Z);
+    input [41:0] X;
+    input [41:0] Y;
+    output [84:0] Z;
+    input clk;
+    input rst;
+    parameter piped = "true";
+endmodule
+
+//TODO
+module ADD84_2DSP(clk, rst, X, Y, Z);
+    input [83:0] X;
+    input [83:0] Y;
+    output [84:0] Z;
+    input clk;
+    input rst;
+    parameter piped = "true";
+endmodule
+
+//TODO
+module SMACC24x18_1DSP(clk, rst, A, B, Z);
+    input [23:0] A;
+    input [17:0] B;
+    output [55:0] Z;
+    input clk;
+    input rst;
+    parameter g_pipe = 1;
+endmodule
+
+//TODO
+module SMACC24x32_2DSP(clk, rst, A, B, Z);
+    input [23:0] A;
+    input [31:0] B;
+    output [55:0] Z;
+    input clk;
+    input rst;
+    parameter g_pipe = 1;
+endmodule
+
+//TODO
+module SMACC24x32_enable_2DSP(clk, rst, we, A, B, Z);
+    input [23:0] A;
+    input [31:0] B;
+    output [55:0] Z;
+    input clk;
+    input rst;
+    input we;
+    parameter STAGE_1 = "false";
+    parameter STAGE_2 = "false";
+    parameter STAGE_3 = "false";
+    parameter STAGE_4 = "false";
+endmodule
+
+//TODO
+module SMUL24x32_2DSP(clk, rst, A, B, Z);
+    input [23:0] A;
+    input [31:0] B;
+    output [54:0] Z;
+    input clk;
+    input rst;
+    parameter g_pipe = 1;
+endmodule
+
+//TODO
+module SMUL24x32_2DSP_ACC_2DSP(clk, rst, we, A, B, Z);
+    input [23:0] A;
+    input [31:0] B;
+    output [97:0] Z;
+    input clk;
+    input rst;
+    input we;
+    parameter STAGE_1 = "false";
+    parameter STAGE_2 = "false";
+    parameter STAGE_3 = "false";
+endmodule
+
+//TODO
+module SMUL47x35_4DSP(clk, rst, A, B, Z);
+    input [46:0] A;
+    input [34:0] B;
+    output [80:0] Z;
+    input clk;
+    input rst;
+    parameter piped = "true";
+endmodule
+
+//TODO
+module UMADD24_2DSP(clk, rst, A, B, C, Z);
+    input [23:0] A;
+    input [31:0] B;
+    input [55:0] C;
+    output [55:0] Z;
+    input clk;
+    input rst;
+    parameter piped = "true";
+endmodule
+
+//TODO
+module UMUL24x32_1DSP_2CYCLES(clk, rst, A, B, Z);
+    input [23:0] A;
+    input [15:0] B;
+    output [55:0] Z;
+    input clk;
+    input rst;
+    parameter piped = "true";
+endmodule
+
+//TODO
+module UMUL24x32_2DSP(clk, rst, A, B, Z);
+    input [23:0] A;
+    input [31:0] B;
+    output [55:0] Z;
+    input clk;
+    input rst;
+    parameter piped = "true";
+endmodule
+
+//TODO
+module UMUL24x36_1DSP_2CYCLES(clk, rst, A, B, Z);
+    input [23:0] A;
+    input [17:0] B;
+    output [59:0] Z;
+    input clk;
+    input rst;
+    parameter piped = "true";
+endmodule
+
+//TODO
+module UMUL24x36_2DSP(clk, rst, A, B, Z);
+    input [23:0] A;
+    input [35:0] B;
+    output [59:0] Z;
+    input clk;
+    input rst;
+    parameter piped = "true";
+endmodule
+
+//TODO
+module UMUL48x36_1DSP_4CYCLES(clk, rst, A, B, Z);
+    input [23:0] A;
+    input [17:0] B;
+    output [83:0] Z;
+    input clk;
+    input rst;
+    parameter piped = "true";
+endmodule
+
+//TODO
+module UMUL48x36_4DSP(clk, rst, A, B, Z);
+    input [47:0] A;
+    input [35:0] B;
+    output [83:0] Z;
+    input clk;
+    input rst;
+    parameter piped = "true";
+endmodule

From ef15325dce40a79d7317bb6b299306e724a74ef2 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 13 Mar 2024 10:08:18 +0100
Subject: [PATCH 285/499] removed virtual primitive

---
 techlibs/nanoxplore/cells_bb.v | 837 ---------------------------------
 1 file changed, 837 deletions(-)

diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index 2b79cc4721e..b040ece785e 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -2288,843 +2288,6 @@ module NX_RAM_WRAP(ACK, ACKD, ACKR, BCK, BCKD, BCKR, ACOR, AERR, BCOR, BERR, ACS
     parameter std_mode = "";
 endmodule
 
-(* blackbox *)
-module NX_RB(CK1, CK2, CK3, CK4, EI1, EI2, EI3, EI4, EI5, EI6, EI7, EI8, EI9, EI10, EI11, EI12, EI13, EI14, EI15, EI16, EI17
-, EI18, EI19, EI20, EI21, EI22, EI23, EI24, EI25, EI26, EI27, EI28, EI29, EI30, EI31, EI32, EI33, EI34, EI35, EI36, EI37, EI38
-, EI39, EI40, EI41, EI42, EI43, EI44, EI45, EI46, EI47, EI48, EI49, EI50, EI51, EI52, EI53, EI54, EI55, EI56, EI57, EI58, EI59
-, EI60, EI61, EI62, EI63, EI64, EI65, EI66, EI67, EI68, EI69, EI70, EI71, EI72, EI73, EI74, EI75, EI76, EI77, EI78, EI79, EI80
-, EI81, EI82, EI83, EI84, EI85, EI86, EI87, EI88, EI89, EI90, EI91, EI92, EI93, EI94, EI95, EI96, EI97, EI98, EI99, EI100, EI101
-, EI102, EI103, EI104, EI105, EI106, EI107, EI108, EI109, EI110, EI111, EI112, EI113, EI114, EI115, EI116, EI117, EI118, EI119, EI120, EI121, EI122
-, EI123, EI124, EI125, EI126, EI127, EI128, EI129, EI130, EI131, EI132, EI133, EI134, EI135, EI136, EI137, EI138, EI139, EI140, EI141, EI142, EI143
-, EI144, EI145, EI146, EI147, EI148, EI149, EI150, EI151, EI152, EI153, EI154, EI155, EI156, EI157, EI158, EI159, EI160, EI161, EI162, EI163, EI164
-, EI165, EI166, EI167, EI168, EI169, EI170, EI171, EI172, EI173, EI174, EI175, EI176, EI177, EI178, EI179, EI180, EI181, EI182, EI183, EI184, EI185
-, EI186, EI187, EI188, EI189, EI190, EI191, EI192, EI_CK, EO_CK, EO1, EO2, EO3, EO4, EO5, EO6, EO7, EO8, EO9, EO10, EO11, EO12
-, EO13, EO14, EO15, EO16, EO17, EO18, EO19, EO20, EO21, EO22, EO23, EO24, EO25, EO26, EO27, EO28, EO29, EO30, EO31, EO32, EO33
-, EO34, EO35, EO36, EO37, EO38, EO39, EO40, EO41, EO42, EO43, EO44, EO45, EO46, EO47, EO48, EO49, EO50, EO51, EO52, EO53, EO54
-, EO55, EO56, EO57, EO58, EO59, EO60, EO61, EO62, EO63, EO64, EO65, EO66, EO67, EO68, EO69, EO70, EO71, EO72, EO73, EO74, EO75
-, EO76, EO77, EO78, EO79, EO80, EO81, EO82, EO83, EO84, EO85, EO86, EO87, EO88, EO89, EO90, EO91, EO92, EO93, EO94, EO95, EO96
-, EO97, EO98, EO99, EO100, EO101, EO102, EO103, EO104, EO105, EO106, EO107, EO108, EO109, EO110, EO111, EO112, EO113, EO114, EO115, EO116, EO117
-, EO118, EO119, EO120, EO121, EO122, EO123, EO124, EO125, EO126, EO127, EO128, EO129, EO130, EO131, EO132, EO133, EO134, EO135, EO136, EO137, EO138
-, EO139, EO140, EO141, EO142, EO143, EO144, EO145, EO146, EO147, EO148, EO149, EO150, EO151, EO152, EO153, EO154, EO155, EO156, EO157, EO158, EO159
-, EO160, EO161, EO162, EO163, EO164, EO165, EO166, EO167, EO168, EO169, EO170, EO171, EO172, EO173, EO174, EO175, EO176, EO177, EO178, EO179, EO180
-, EO181, EO182, EO183, EO184, EO185, EO186, EO187, EO188, EO189, EO190, EO191, EO192, FI1, FI2, FI3, FI4, FI5, FI6, FI7, FI8, FI9
-, FI10, FI11, FI12, FI13, FI14, FI15, FI16, FI17, FI18, FI19, FI20, FI21, FI22, FI23, FI24, FI25, FI26, FI27, FI28, FI29, FI30
-, FI31, FI32, FI33, FI34, FI35, FI36, FI37, FI38, FI39, FI40, FI41, FI42, FI43, FI44, FI45, FI46, FI47, FI48, FI49, FI50, FI51
-, FI52, FI53, FI54, FI55, FI56, FI57, FI58, FI59, FI60, FI61, FI62, FI63, FI64, FI65, FI66, FI67, FI68, FI69, FI70, FI71, FI72
-, FI73, FI74, FI75, FI76, FI77, FI78, FI79, FI80, FI81, FI82, FI83, FI84, FI85, FI86, FI87, FI88, FI89, FI90, FI91, FI92, FI93
-, FI94, FI95, FI96, FI97, FI98, FI99, FI100, FI101, FI102, FI103, FI104, FI105, FI106, FI107, FI108, FI109, FI110, FI111, FI112, FI113, FI114
-, FI115, FI116, FI117, FI118, FI119, FI120, FI121, FI122, FI123, FI124, FI125, FI126, FI127, FI128, FI129, FI130, FI131, FI132, FI133, FI134, FI135
-, FI136, FI137, FI138, FI139, FI140, FI141, FI142, FI143, FI144, FI145, FI146, FI147, FI148, FI149, FI150, FI151, FI152, FI153, FI154, FI155, FI156
-, FI157, FI158, FI159, FI160, FI161, FI162, FI163, FI164, FI165, FI166, FI167, FI168, FI169, FI170, FI171, FI172, FI173, FI174, FI175, FI176, FI177
-, FI178, FI179, FI180, FI181, FI182, FI183, FI184, FI185, FI186, FI187, FI188, FI189, FI190, FI191, FI192, FO1, FO2, FO3, FO4, FO5, FO6
-, FO7, FO8, FO9, FO10, FO11, FO12, FO13, FO14, FO15, FO16, FO17, FO18, FO19, FO20, FO21, FO22, FO23, FO24, FO25, FO26, FO27
-, FO28, FO29, FO30, FO31, FO32, FO33, FO34, FO35, FO36, FO37, FO38, FO39, FO40, FO41, FO42, FO43, FO44, FO45, FO46, FO47, FO48
-, FO49, FO50, FO51, FO52, FO53, FO54, FO55, FO56, FO57, FO58, FO59, FO60, FO61, FO62, FO63, FO64, FO65, FO66, FO67, FO68, FO69
-, FO70, FO71, FO72, FO73, FO74, FO75, FO76, FO77, FO78, FO79, FO80, FO81, FO82, FO83, FO84, FO85, FO86, FO87, FO88, FO89, FO90
-, FO91, FO92, FO93, FO94, FO95, FO96, FO97, FO98, FO99, FO100, FO101, FO102, FO103, FO104, FO105, FO106, FO107, FO108, FO109, FO110, FO111
-, FO112, FO113, FO114, FO115, FO116, FO117, FO118, FO119, FO120, FO121, FO122, FO123, FO124, FO125, FO126, FO127, FO128, FO129, FO130, FO131, FO132
-, FO133, FO134, FO135, FO136, FO137, FO138, FO139, FO140, FO141, FO142, FO143, FO144, FO145, FO146, FO147, FO148, FO149, FO150, FO151, FO152, FO153
-, FO154, FO155, FO156, FO157, FO158, FO159, FO160, FO161, FO162, FO163, FO164, FO165, FO166, FO167, FO168, FO169, FO170, FO171, FO172, FO173, FO174
-, FO175, FO176, FO177, FO178, FO179, FO180, FO181, FO182, FO183, FO184, FO185, FO186, FO187, FO188, FO189, FO190, FO191, FO192);
-    input CK1;
-    input CK2;
-    input CK3;
-    input CK4;
-    input EI1;
-    input EI10;
-    input EI100;
-    input EI101;
-    input EI102;
-    input EI103;
-    input EI104;
-    input EI105;
-    input EI106;
-    input EI107;
-    input EI108;
-    input EI109;
-    input EI11;
-    input EI110;
-    input EI111;
-    input EI112;
-    input EI113;
-    input EI114;
-    input EI115;
-    input EI116;
-    input EI117;
-    input EI118;
-    input EI119;
-    input EI12;
-    input EI120;
-    input EI121;
-    input EI122;
-    input EI123;
-    input EI124;
-    input EI125;
-    input EI126;
-    input EI127;
-    input EI128;
-    input EI129;
-    input EI13;
-    input EI130;
-    input EI131;
-    input EI132;
-    input EI133;
-    input EI134;
-    input EI135;
-    input EI136;
-    input EI137;
-    input EI138;
-    input EI139;
-    input EI14;
-    input EI140;
-    input EI141;
-    input EI142;
-    input EI143;
-    input EI144;
-    input EI145;
-    input EI146;
-    input EI147;
-    input EI148;
-    input EI149;
-    input EI15;
-    input EI150;
-    input EI151;
-    input EI152;
-    input EI153;
-    input EI154;
-    input EI155;
-    input EI156;
-    input EI157;
-    input EI158;
-    input EI159;
-    input EI16;
-    input EI160;
-    input EI161;
-    input EI162;
-    input EI163;
-    input EI164;
-    input EI165;
-    input EI166;
-    input EI167;
-    input EI168;
-    input EI169;
-    input EI17;
-    input EI170;
-    input EI171;
-    input EI172;
-    input EI173;
-    input EI174;
-    input EI175;
-    input EI176;
-    input EI177;
-    input EI178;
-    input EI179;
-    input EI18;
-    input EI180;
-    input EI181;
-    input EI182;
-    input EI183;
-    input EI184;
-    input EI185;
-    input EI186;
-    input EI187;
-    input EI188;
-    input EI189;
-    input EI19;
-    input EI190;
-    input EI191;
-    input EI192;
-    input EI2;
-    input EI20;
-    input EI21;
-    input EI22;
-    input EI23;
-    input EI24;
-    input EI25;
-    input EI26;
-    input EI27;
-    input EI28;
-    input EI29;
-    input EI3;
-    input EI30;
-    input EI31;
-    input EI32;
-    input EI33;
-    input EI34;
-    input EI35;
-    input EI36;
-    input EI37;
-    input EI38;
-    input EI39;
-    input EI4;
-    input EI40;
-    input EI41;
-    input EI42;
-    input EI43;
-    input EI44;
-    input EI45;
-    input EI46;
-    input EI47;
-    input EI48;
-    input EI49;
-    input EI5;
-    input EI50;
-    input EI51;
-    input EI52;
-    input EI53;
-    input EI54;
-    input EI55;
-    input EI56;
-    input EI57;
-    input EI58;
-    input EI59;
-    input EI6;
-    input EI60;
-    input EI61;
-    input EI62;
-    input EI63;
-    input EI64;
-    input EI65;
-    input EI66;
-    input EI67;
-    input EI68;
-    input EI69;
-    input EI7;
-    input EI70;
-    input EI71;
-    input EI72;
-    input EI73;
-    input EI74;
-    input EI75;
-    input EI76;
-    input EI77;
-    input EI78;
-    input EI79;
-    input EI8;
-    input EI80;
-    input EI81;
-    input EI82;
-    input EI83;
-    input EI84;
-    input EI85;
-    input EI86;
-    input EI87;
-    input EI88;
-    input EI89;
-    input EI9;
-    input EI90;
-    input EI91;
-    input EI92;
-    input EI93;
-    input EI94;
-    input EI95;
-    input EI96;
-    input EI97;
-    input EI98;
-    input EI99;
-    output EI_CK;
-    output EO1;
-    output EO10;
-    output EO100;
-    output EO101;
-    output EO102;
-    output EO103;
-    output EO104;
-    output EO105;
-    output EO106;
-    output EO107;
-    output EO108;
-    output EO109;
-    output EO11;
-    output EO110;
-    output EO111;
-    output EO112;
-    output EO113;
-    output EO114;
-    output EO115;
-    output EO116;
-    output EO117;
-    output EO118;
-    output EO119;
-    output EO12;
-    output EO120;
-    output EO121;
-    output EO122;
-    output EO123;
-    output EO124;
-    output EO125;
-    output EO126;
-    output EO127;
-    output EO128;
-    output EO129;
-    output EO13;
-    output EO130;
-    output EO131;
-    output EO132;
-    output EO133;
-    output EO134;
-    output EO135;
-    output EO136;
-    output EO137;
-    output EO138;
-    output EO139;
-    output EO14;
-    output EO140;
-    output EO141;
-    output EO142;
-    output EO143;
-    output EO144;
-    output EO145;
-    output EO146;
-    output EO147;
-    output EO148;
-    output EO149;
-    output EO15;
-    output EO150;
-    output EO151;
-    output EO152;
-    output EO153;
-    output EO154;
-    output EO155;
-    output EO156;
-    output EO157;
-    output EO158;
-    output EO159;
-    output EO16;
-    output EO160;
-    output EO161;
-    output EO162;
-    output EO163;
-    output EO164;
-    output EO165;
-    output EO166;
-    output EO167;
-    output EO168;
-    output EO169;
-    output EO17;
-    output EO170;
-    output EO171;
-    output EO172;
-    output EO173;
-    output EO174;
-    output EO175;
-    output EO176;
-    output EO177;
-    output EO178;
-    output EO179;
-    output EO18;
-    output EO180;
-    output EO181;
-    output EO182;
-    output EO183;
-    output EO184;
-    output EO185;
-    output EO186;
-    output EO187;
-    output EO188;
-    output EO189;
-    output EO19;
-    output EO190;
-    output EO191;
-    output EO192;
-    output EO2;
-    output EO20;
-    output EO21;
-    output EO22;
-    output EO23;
-    output EO24;
-    output EO25;
-    output EO26;
-    output EO27;
-    output EO28;
-    output EO29;
-    output EO3;
-    output EO30;
-    output EO31;
-    output EO32;
-    output EO33;
-    output EO34;
-    output EO35;
-    output EO36;
-    output EO37;
-    output EO38;
-    output EO39;
-    output EO4;
-    output EO40;
-    output EO41;
-    output EO42;
-    output EO43;
-    output EO44;
-    output EO45;
-    output EO46;
-    output EO47;
-    output EO48;
-    output EO49;
-    output EO5;
-    output EO50;
-    output EO51;
-    output EO52;
-    output EO53;
-    output EO54;
-    output EO55;
-    output EO56;
-    output EO57;
-    output EO58;
-    output EO59;
-    output EO6;
-    output EO60;
-    output EO61;
-    output EO62;
-    output EO63;
-    output EO64;
-    output EO65;
-    output EO66;
-    output EO67;
-    output EO68;
-    output EO69;
-    output EO7;
-    output EO70;
-    output EO71;
-    output EO72;
-    output EO73;
-    output EO74;
-    output EO75;
-    output EO76;
-    output EO77;
-    output EO78;
-    output EO79;
-    output EO8;
-    output EO80;
-    output EO81;
-    output EO82;
-    output EO83;
-    output EO84;
-    output EO85;
-    output EO86;
-    output EO87;
-    output EO88;
-    output EO89;
-    output EO9;
-    output EO90;
-    output EO91;
-    output EO92;
-    output EO93;
-    output EO94;
-    output EO95;
-    output EO96;
-    output EO97;
-    output EO98;
-    output EO99;
-    output EO_CK;
-    input FI1;
-    input FI10;
-    input FI100;
-    input FI101;
-    input FI102;
-    input FI103;
-    input FI104;
-    input FI105;
-    input FI106;
-    input FI107;
-    input FI108;
-    input FI109;
-    input FI11;
-    input FI110;
-    input FI111;
-    input FI112;
-    input FI113;
-    input FI114;
-    input FI115;
-    input FI116;
-    input FI117;
-    input FI118;
-    input FI119;
-    input FI12;
-    input FI120;
-    input FI121;
-    input FI122;
-    input FI123;
-    input FI124;
-    input FI125;
-    input FI126;
-    input FI127;
-    input FI128;
-    input FI129;
-    input FI13;
-    input FI130;
-    input FI131;
-    input FI132;
-    input FI133;
-    input FI134;
-    input FI135;
-    input FI136;
-    input FI137;
-    input FI138;
-    input FI139;
-    input FI14;
-    input FI140;
-    input FI141;
-    input FI142;
-    input FI143;
-    input FI144;
-    input FI145;
-    input FI146;
-    input FI147;
-    input FI148;
-    input FI149;
-    input FI15;
-    input FI150;
-    input FI151;
-    input FI152;
-    input FI153;
-    input FI154;
-    input FI155;
-    input FI156;
-    input FI157;
-    input FI158;
-    input FI159;
-    input FI16;
-    input FI160;
-    input FI161;
-    input FI162;
-    input FI163;
-    input FI164;
-    input FI165;
-    input FI166;
-    input FI167;
-    input FI168;
-    input FI169;
-    input FI17;
-    input FI170;
-    input FI171;
-    input FI172;
-    input FI173;
-    input FI174;
-    input FI175;
-    input FI176;
-    input FI177;
-    input FI178;
-    input FI179;
-    input FI18;
-    input FI180;
-    input FI181;
-    input FI182;
-    input FI183;
-    input FI184;
-    input FI185;
-    input FI186;
-    input FI187;
-    input FI188;
-    input FI189;
-    input FI19;
-    input FI190;
-    input FI191;
-    input FI192;
-    input FI2;
-    input FI20;
-    input FI21;
-    input FI22;
-    input FI23;
-    input FI24;
-    input FI25;
-    input FI26;
-    input FI27;
-    input FI28;
-    input FI29;
-    input FI3;
-    input FI30;
-    input FI31;
-    input FI32;
-    input FI33;
-    input FI34;
-    input FI35;
-    input FI36;
-    input FI37;
-    input FI38;
-    input FI39;
-    input FI4;
-    input FI40;
-    input FI41;
-    input FI42;
-    input FI43;
-    input FI44;
-    input FI45;
-    input FI46;
-    input FI47;
-    input FI48;
-    input FI49;
-    input FI5;
-    input FI50;
-    input FI51;
-    input FI52;
-    input FI53;
-    input FI54;
-    input FI55;
-    input FI56;
-    input FI57;
-    input FI58;
-    input FI59;
-    input FI6;
-    input FI60;
-    input FI61;
-    input FI62;
-    input FI63;
-    input FI64;
-    input FI65;
-    input FI66;
-    input FI67;
-    input FI68;
-    input FI69;
-    input FI7;
-    input FI70;
-    input FI71;
-    input FI72;
-    input FI73;
-    input FI74;
-    input FI75;
-    input FI76;
-    input FI77;
-    input FI78;
-    input FI79;
-    input FI8;
-    input FI80;
-    input FI81;
-    input FI82;
-    input FI83;
-    input FI84;
-    input FI85;
-    input FI86;
-    input FI87;
-    input FI88;
-    input FI89;
-    input FI9;
-    input FI90;
-    input FI91;
-    input FI92;
-    input FI93;
-    input FI94;
-    input FI95;
-    input FI96;
-    input FI97;
-    input FI98;
-    input FI99;
-    output FO1;
-    output FO10;
-    output FO100;
-    output FO101;
-    output FO102;
-    output FO103;
-    output FO104;
-    output FO105;
-    output FO106;
-    output FO107;
-    output FO108;
-    output FO109;
-    output FO11;
-    output FO110;
-    output FO111;
-    output FO112;
-    output FO113;
-    output FO114;
-    output FO115;
-    output FO116;
-    output FO117;
-    output FO118;
-    output FO119;
-    output FO12;
-    output FO120;
-    output FO121;
-    output FO122;
-    output FO123;
-    output FO124;
-    output FO125;
-    output FO126;
-    output FO127;
-    output FO128;
-    output FO129;
-    output FO13;
-    output FO130;
-    output FO131;
-    output FO132;
-    output FO133;
-    output FO134;
-    output FO135;
-    output FO136;
-    output FO137;
-    output FO138;
-    output FO139;
-    output FO14;
-    output FO140;
-    output FO141;
-    output FO142;
-    output FO143;
-    output FO144;
-    output FO145;
-    output FO146;
-    output FO147;
-    output FO148;
-    output FO149;
-    output FO15;
-    output FO150;
-    output FO151;
-    output FO152;
-    output FO153;
-    output FO154;
-    output FO155;
-    output FO156;
-    output FO157;
-    output FO158;
-    output FO159;
-    output FO16;
-    output FO160;
-    output FO161;
-    output FO162;
-    output FO163;
-    output FO164;
-    output FO165;
-    output FO166;
-    output FO167;
-    output FO168;
-    output FO169;
-    output FO17;
-    output FO170;
-    output FO171;
-    output FO172;
-    output FO173;
-    output FO174;
-    output FO175;
-    output FO176;
-    output FO177;
-    output FO178;
-    output FO179;
-    output FO18;
-    output FO180;
-    output FO181;
-    output FO182;
-    output FO183;
-    output FO184;
-    output FO185;
-    output FO186;
-    output FO187;
-    output FO188;
-    output FO189;
-    output FO19;
-    output FO190;
-    output FO191;
-    output FO192;
-    output FO2;
-    output FO20;
-    output FO21;
-    output FO22;
-    output FO23;
-    output FO24;
-    output FO25;
-    output FO26;
-    output FO27;
-    output FO28;
-    output FO29;
-    output FO3;
-    output FO30;
-    output FO31;
-    output FO32;
-    output FO33;
-    output FO34;
-    output FO35;
-    output FO36;
-    output FO37;
-    output FO38;
-    output FO39;
-    output FO4;
-    output FO40;
-    output FO41;
-    output FO42;
-    output FO43;
-    output FO44;
-    output FO45;
-    output FO46;
-    output FO47;
-    output FO48;
-    output FO49;
-    output FO5;
-    output FO50;
-    output FO51;
-    output FO52;
-    output FO53;
-    output FO54;
-    output FO55;
-    output FO56;
-    output FO57;
-    output FO58;
-    output FO59;
-    output FO6;
-    output FO60;
-    output FO61;
-    output FO62;
-    output FO63;
-    output FO64;
-    output FO65;
-    output FO66;
-    output FO67;
-    output FO68;
-    output FO69;
-    output FO7;
-    output FO70;
-    output FO71;
-    output FO72;
-    output FO73;
-    output FO74;
-    output FO75;
-    output FO76;
-    output FO77;
-    output FO78;
-    output FO79;
-    output FO8;
-    output FO80;
-    output FO81;
-    output FO82;
-    output FO83;
-    output FO84;
-    output FO85;
-    output FO86;
-    output FO87;
-    output FO88;
-    output FO89;
-    output FO9;
-    output FO90;
-    output FO91;
-    output FO92;
-    output FO93;
-    output FO94;
-    output FO95;
-    output FO96;
-    output FO97;
-    output FO98;
-    output FO99;
-    parameter inputBypass = 24'b000000000000000000000000;
-    parameter inputClk = 2'b00;
-    parameter inputContext = "";
-    parameter outputBypass = 24'b000000000000000000000000;
-    parameter outputClk = 2'b00;
-    parameter outputContext = "";
-endmodule
-
-(* blackbox *)
-module NX_RB_WRAP(EI_CK, EO_CK, CK, EO, EI, FI, FO);
-    input [3:0] CK;
-    input [191:0] EI;
-    output EI_CK;
-    output [191:0] EO;
-    output EO_CK;
-    input [191:0] FI;
-    output [191:0] FO;
-    parameter inputBypass = 24'b000000000000000000000000;
-    parameter inputClk = 2'b00;
-    parameter inputContext = "";
-    parameter outputBypass = 24'b000000000000000000000000;
-    parameter outputClk = 2'b00;
-    parameter outputContext = "";
-endmodule
-
 (* blackbox *)
 module NX_SER(FCK, SCK, R, IO, DCK, DRL, I, DS, DRA, DRI, DRO, DID);
     input DCK;

From 71f0984dc9874d7d0b298e58fcc92d3932f226d0 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 13 Mar 2024 10:16:09 +0100
Subject: [PATCH 286/499] fixes

---
 techlibs/nanoxplore/cells_wrap_l.v | 4 ++--
 techlibs/nanoxplore/cells_wrap_m.v | 4 ++--
 techlibs/nanoxplore/cells_wrap_u.v | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/techlibs/nanoxplore/cells_wrap_l.v b/techlibs/nanoxplore/cells_wrap_l.v
index 24430052f94..d86b4518ba9 100644
--- a/techlibs/nanoxplore/cells_wrap_l.v
+++ b/techlibs/nanoxplore/cells_wrap_l.v
@@ -1007,8 +1007,8 @@ module NX_DSP_L_WRAP(CCI, CCO, CI, CK, CO, CO37, CO57, OVF, R, RZ, WE, A, B, C,
     .CI(CI),
     .CK(CK),
     .CO(CO),
-    .CO37(CO36),
-    .CO57(CO56),
+    .CO37(CO37),
+    .CO57(CO57),
 
     .CZI1(CZI[0]),
     .CZI2(CZI[1]),
diff --git a/techlibs/nanoxplore/cells_wrap_m.v b/techlibs/nanoxplore/cells_wrap_m.v
index 190196e2fbc..0bf3a905096 100644
--- a/techlibs/nanoxplore/cells_wrap_m.v
+++ b/techlibs/nanoxplore/cells_wrap_m.v
@@ -646,8 +646,8 @@ module NX_DSP_WRAP(CCI, CCO, CI, CK, CO, CO37, CO49, OVF, R, RZ, WE, A, B, C, D,
     .CI(CI),
     .CK(CK),
     .CO(CO),
-    .CO37(CO36),
-    .CO49(CO48),
+    .CO37(CO37),
+    .CO49(CO49),
 
     .CZI1(CZI[0]),
     .CZI2(CZI[1]),
diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v
index b07c9e46bd2..f5623dfeb43 100644
--- a/techlibs/nanoxplore/cells_wrap_u.v
+++ b/techlibs/nanoxplore/cells_wrap_u.v
@@ -1149,8 +1149,8 @@ module NX_DSP_U_WRAP(CCI, CCO, CI, CK, CO43, CO57, OVF, R, RZ, WE, WEZ, A, B, C,
     .CCO(CCO),
     .CI(CI),
     .CK(CK),
-    .CO43(CO42),
-    .CO57(CO56),
+    .CO43(CO43),
+    .CO57(CO57),
 
     .CZI1(CZI[0]),
     .CZI2(CZI[1]),

From b202126c76ca921dee6768f7bf9f80efe38acb41 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 13 Mar 2024 10:57:58 +0100
Subject: [PATCH 287/499] IOM

---
 techlibs/nanoxplore/cells_bb.v     | 1831 ----------------------------
 techlibs/nanoxplore/cells_bb_l.v   |  153 +++
 techlibs/nanoxplore/cells_bb_m.v   |  237 ++++
 techlibs/nanoxplore/cells_bb_u.v   |  361 ++++++
 techlibs/nanoxplore/cells_wrap_l.v |  302 ++++-
 techlibs/nanoxplore/cells_wrap_m.v |  465 ++++++-
 techlibs/nanoxplore/cells_wrap_u.v |  602 +++++++++
 7 files changed, 2118 insertions(+), 1833 deletions(-)

diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index b040ece785e..ba7318c7318 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -118,908 +118,6 @@ module NX_ECC(CKD, CHK, COR, ERR);
     output ERR;
 endmodule
 
-(* blackbox *)
-module NX_HSSL_L_FULL(hssl_clk_user_i, hssl_clk_ref_i, hssl_clock_o, usr_com_tx_pma_pre_sign_i, usr_com_tx_pma_pre_en_i, usr_com_tx_pma_main_sign_i, usr_com_rx_pma_m_eye_i, usr_com_tx_pma_post_sign_i, usr_pll_pma_rst_n_i, usr_main_rst_n_i, usr_calibrate_pma_en_i, usr_pcs_ctrl_pll_lock_en_i, usr_pcs_ctrl_ovs_en_i, usr_pll_lock_o, usr_calibrate_pma_out_o, pma_clk_ext_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i, usr_tx0_pma_clk_en_i, usr_tx0_busy_o, pma_tx0_o
-, usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_ctrl_el_buff_fifo_en_i, usr_rx0_rst_n_i, usr_rx0_pma_cdr_rst_i, usr_rx0_pma_ckgen_rst_n_i, usr_rx0_pma_pll_rst_n_i, usr_rx0_pma_loss_of_signal_o, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_busy_o, usr_rx0_pll_lock_o, pma_rx0_i, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_pma_clk_en_i, usr_tx1_busy_o, pma_tx1_o
-, usr_rx1_ctrl_dscr_en_i, usr_rx1_ctrl_dec_en_i, usr_rx1_ctrl_align_en_i, usr_rx1_ctrl_align_sync_i, usr_rx1_ctrl_replace_en_i, usr_rx1_ctrl_el_buff_rst_i, usr_rx1_ctrl_el_buff_fifo_en_i, usr_rx1_rst_n_i, usr_rx1_pma_cdr_rst_i, usr_rx1_pma_ckgen_rst_n_i, usr_rx1_pma_pll_rst_n_i, usr_rx1_pma_loss_of_signal_o, usr_rx1_ctrl_char_is_aligned_o, usr_rx1_busy_o, usr_rx1_pll_lock_o, pma_rx1_i, usr_tx2_ctrl_replace_en_i, usr_tx2_rst_n_i, usr_tx2_pma_clk_en_i, usr_tx2_busy_o, pma_tx2_o
-, usr_rx2_ctrl_dscr_en_i, usr_rx2_ctrl_dec_en_i, usr_rx2_ctrl_align_en_i, usr_rx2_ctrl_align_sync_i, usr_rx2_ctrl_replace_en_i, usr_rx2_ctrl_el_buff_rst_i, usr_rx2_ctrl_el_buff_fifo_en_i, usr_rx2_rst_n_i, usr_rx2_pma_cdr_rst_i, usr_rx2_pma_ckgen_rst_n_i, usr_rx2_pma_pll_rst_n_i, usr_rx2_pma_loss_of_signal_o, usr_rx2_ctrl_char_is_aligned_o, usr_rx2_busy_o, usr_rx2_pll_lock_o, pma_rx2_i, usr_tx3_ctrl_replace_en_i, usr_tx3_rst_n_i, usr_tx3_pma_clk_en_i, usr_tx3_busy_o, pma_tx3_o
-, usr_rx3_ctrl_dscr_en_i, usr_rx3_ctrl_dec_en_i, usr_rx3_ctrl_align_en_i, usr_rx3_ctrl_align_sync_i, usr_rx3_ctrl_replace_en_i, usr_rx3_ctrl_el_buff_rst_i, usr_rx3_ctrl_el_buff_fifo_en_i, usr_rx3_rst_n_i, usr_rx3_pma_cdr_rst_i, usr_rx3_pma_ckgen_rst_n_i, usr_rx3_pma_pll_rst_n_i, usr_rx3_pma_loss_of_signal_o, usr_rx3_ctrl_char_is_aligned_o, usr_rx3_busy_o, usr_rx3_pll_lock_o, pma_rx3_i, usr_tx4_ctrl_replace_en_i, usr_tx4_rst_n_i, usr_tx4_pma_clk_en_i, usr_tx4_busy_o, pma_tx4_o
-, usr_rx4_ctrl_dscr_en_i, usr_rx4_ctrl_dec_en_i, usr_rx4_ctrl_align_en_i, usr_rx4_ctrl_align_sync_i, usr_rx4_ctrl_replace_en_i, usr_rx4_ctrl_el_buff_rst_i, usr_rx4_ctrl_el_buff_fifo_en_i, usr_rx4_rst_n_i, usr_rx4_pma_cdr_rst_i, usr_rx4_pma_ckgen_rst_n_i, usr_rx4_pma_pll_rst_n_i, usr_rx4_pma_loss_of_signal_o, usr_rx4_ctrl_char_is_aligned_o, usr_rx4_busy_o, usr_rx4_pll_lock_o, pma_rx4_i, usr_tx5_ctrl_replace_en_i, usr_tx5_rst_n_i, usr_tx5_pma_clk_en_i, usr_tx5_busy_o, pma_tx5_o
-, usr_rx5_ctrl_dscr_en_i, usr_rx5_ctrl_dec_en_i, usr_rx5_ctrl_align_en_i, usr_rx5_ctrl_align_sync_i, usr_rx5_ctrl_replace_en_i, usr_rx5_ctrl_el_buff_rst_i, usr_rx5_ctrl_el_buff_fifo_en_i, usr_rx5_rst_n_i, usr_rx5_pma_cdr_rst_i, usr_rx5_pma_ckgen_rst_n_i, usr_rx5_pma_pll_rst_n_i, usr_rx5_pma_loss_of_signal_o, usr_rx5_ctrl_char_is_aligned_o, usr_rx5_busy_o, usr_rx5_pll_lock_o, pma_rx5_i, usr_com_tx_pma_main_en_i, usr_com_tx_pma_margin_sel_i, usr_com_tx_pma_margin_input_sel_i, usr_com_tx_pma_margin_sel_var_i, usr_com_tx_pma_margin_input_sel_var_i
-, usr_com_tx_pma_post_en_i, usr_com_tx_pma_post_input_sel_i, usr_com_tx_pma_post_input_sel_var_i, usr_com_rx_pma_ctle_cap_i, usr_com_rx_pma_ctle_resp_i, usr_com_rx_pma_ctle_resn_i, usr_com_ctrl_tx_sel_i, usr_com_ctrl_rx_sel_i, usr_calibrate_pma_res_p1_i, usr_calibrate_pma_res_n2_i, usr_calibrate_pma_res_n3_i, usr_calibrate_pma_res_p4_i, usr_calibrate_pma_sel_i, usr_main_test_i, usr_main_test_o, usr_tx0_ctrl_enc_en_i, usr_tx0_ctrl_char_is_k_i, usr_tx0_ctrl_scr_en_i, usr_tx0_ctrl_end_of_multiframe_i, usr_tx0_ctrl_end_of_frame_i, usr_tx0_test_i
-, usr_tx0_data_i, usr_tx0_test_o, usr_rx0_data_o, usr_rx0_ctrl_ovs_bit_sel_i, usr_rx0_test_i, usr_rx0_ctrl_char_is_comma_o, usr_rx0_ctrl_char_is_k_o, usr_rx0_ctrl_not_in_table_o, usr_rx0_ctrl_disp_err_o, usr_rx0_ctrl_char_is_a_o, usr_rx0_ctrl_char_is_f_o, usr_rx0_test_o, usr_tx1_ctrl_enc_en_i, usr_tx1_ctrl_char_is_k_i, usr_tx1_ctrl_scr_en_i, usr_tx1_ctrl_end_of_multiframe_i, usr_tx1_ctrl_end_of_frame_i, usr_tx1_test_i, usr_tx1_data_i, usr_tx1_test_o, usr_rx1_data_o
-, usr_rx1_ctrl_ovs_bit_sel_i, usr_rx1_test_i, usr_rx1_ctrl_char_is_comma_o, usr_rx1_ctrl_char_is_k_o, usr_rx1_ctrl_not_in_table_o, usr_rx1_ctrl_disp_err_o, usr_rx1_ctrl_char_is_a_o, usr_rx1_ctrl_char_is_f_o, usr_rx1_test_o, usr_tx2_ctrl_enc_en_i, usr_tx2_ctrl_char_is_k_i, usr_tx2_ctrl_scr_en_i, usr_tx2_ctrl_end_of_multiframe_i, usr_tx2_ctrl_end_of_frame_i, usr_tx2_test_i, usr_tx2_data_i, usr_tx2_test_o, usr_rx2_data_o, usr_rx2_ctrl_ovs_bit_sel_i, usr_rx2_test_i, usr_rx2_ctrl_char_is_comma_o
-, usr_rx2_ctrl_char_is_k_o, usr_rx2_ctrl_not_in_table_o, usr_rx2_ctrl_disp_err_o, usr_rx2_ctrl_char_is_a_o, usr_rx2_ctrl_char_is_f_o, usr_rx2_test_o, usr_tx3_ctrl_enc_en_i, usr_tx3_ctrl_char_is_k_i, usr_tx3_ctrl_scr_en_i, usr_tx3_ctrl_end_of_multiframe_i, usr_tx3_ctrl_end_of_frame_i, usr_tx3_test_i, usr_tx3_data_i, usr_tx3_test_o, usr_rx3_data_o, usr_rx3_ctrl_ovs_bit_sel_i, usr_rx3_test_i, usr_rx3_ctrl_char_is_comma_o, usr_rx3_ctrl_char_is_k_o, usr_rx3_ctrl_not_in_table_o, usr_rx3_ctrl_disp_err_o
-, usr_rx3_ctrl_char_is_a_o, usr_rx3_ctrl_char_is_f_o, usr_rx3_test_o, usr_tx4_ctrl_enc_en_i, usr_tx4_ctrl_char_is_k_i, usr_tx4_ctrl_scr_en_i, usr_tx4_ctrl_end_of_multiframe_i, usr_tx4_ctrl_end_of_frame_i, usr_tx4_test_i, usr_tx4_data_i, usr_tx4_test_o, usr_rx4_data_o, usr_rx4_ctrl_ovs_bit_sel_i, usr_rx4_test_i, usr_rx4_ctrl_char_is_comma_o, usr_rx4_ctrl_char_is_k_o, usr_rx4_ctrl_not_in_table_o, usr_rx4_ctrl_disp_err_o, usr_rx4_ctrl_char_is_a_o, usr_rx4_ctrl_char_is_f_o, usr_rx4_test_o
-, usr_tx5_ctrl_enc_en_i, usr_tx5_ctrl_char_is_k_i, usr_tx5_ctrl_scr_en_i, usr_tx5_ctrl_end_of_multiframe_i, usr_tx5_ctrl_end_of_frame_i, usr_tx5_test_i, usr_tx5_data_i, usr_tx5_test_o, usr_rx5_data_o, usr_rx5_ctrl_ovs_bit_sel_i, usr_rx5_test_i, usr_rx5_ctrl_char_is_comma_o, usr_rx5_ctrl_char_is_k_o, usr_rx5_ctrl_not_in_table_o, usr_rx5_ctrl_disp_err_o, usr_rx5_ctrl_char_is_a_o, usr_rx5_ctrl_char_is_f_o, usr_rx5_test_o, usr_com_tx_pma_pre_input_sel_i);
-    input hssl_clk_ref_i;
-    input hssl_clk_user_i;
-    output hssl_clock_o;
-    input pma_clk_ext_i;
-    input pma_rx0_i;
-    input pma_rx1_i;
-    input pma_rx2_i;
-    input pma_rx3_i;
-    input pma_rx4_i;
-    input pma_rx5_i;
-    output pma_tx0_o;
-    output pma_tx1_o;
-    output pma_tx2_o;
-    output pma_tx3_o;
-    output pma_tx4_o;
-    output pma_tx5_o;
-    input usr_calibrate_pma_en_i;
-    output usr_calibrate_pma_out_o;
-    input [7:0] usr_calibrate_pma_res_n2_i;
-    input [7:0] usr_calibrate_pma_res_n3_i;
-    input [7:0] usr_calibrate_pma_res_p1_i;
-    input [7:0] usr_calibrate_pma_res_p4_i;
-    input [3:0] usr_calibrate_pma_sel_i;
-    input [5:0] usr_com_ctrl_rx_sel_i;
-    input [5:0] usr_com_ctrl_tx_sel_i;
-    input [3:0] usr_com_rx_pma_ctle_cap_i;
-    input [3:0] usr_com_rx_pma_ctle_resn_i;
-    input [3:0] usr_com_rx_pma_ctle_resp_i;
-    input usr_com_rx_pma_m_eye_i;
-    input [5:0] usr_com_tx_pma_main_en_i;
-    input usr_com_tx_pma_main_sign_i;
-    input [3:0] usr_com_tx_pma_margin_input_sel_i;
-    input [4:0] usr_com_tx_pma_margin_input_sel_var_i;
-    input [3:0] usr_com_tx_pma_margin_sel_i;
-    input [4:0] usr_com_tx_pma_margin_sel_var_i;
-    input [4:0] usr_com_tx_pma_post_en_i;
-    input [3:0] usr_com_tx_pma_post_input_sel_i;
-    input [3:0] usr_com_tx_pma_post_input_sel_var_i;
-    input usr_com_tx_pma_post_sign_i;
-    input usr_com_tx_pma_pre_en_i;
-    input [3:0] usr_com_tx_pma_pre_input_sel_i;
-    input usr_com_tx_pma_pre_sign_i;
-    input usr_main_rst_n_i;
-    input [7:0] usr_main_test_i;
-    output [7:0] usr_main_test_o;
-    input usr_pcs_ctrl_ovs_en_i;
-    input usr_pcs_ctrl_pll_lock_en_i;
-    output usr_pll_lock_o;
-    input usr_pll_pma_rst_n_i;
-    output usr_rx0_busy_o;
-    input usr_rx0_ctrl_align_en_i;
-    input usr_rx0_ctrl_align_sync_i;
-    output [7:0] usr_rx0_ctrl_char_is_a_o;
-    output usr_rx0_ctrl_char_is_aligned_o;
-    output [7:0] usr_rx0_ctrl_char_is_comma_o;
-    output [7:0] usr_rx0_ctrl_char_is_f_o;
-    output [7:0] usr_rx0_ctrl_char_is_k_o;
-    input usr_rx0_ctrl_dec_en_i;
-    output [7:0] usr_rx0_ctrl_disp_err_o;
-    input usr_rx0_ctrl_dscr_en_i;
-    input usr_rx0_ctrl_el_buff_fifo_en_i;
-    input usr_rx0_ctrl_el_buff_rst_i;
-    output [7:0] usr_rx0_ctrl_not_in_table_o;
-    input [1:0] usr_rx0_ctrl_ovs_bit_sel_i;
-    input usr_rx0_ctrl_replace_en_i;
-    output [63:0] usr_rx0_data_o;
-    output usr_rx0_pll_lock_o;
-    input usr_rx0_pma_cdr_rst_i;
-    input usr_rx0_pma_ckgen_rst_n_i;
-    output usr_rx0_pma_loss_of_signal_o;
-    input usr_rx0_pma_pll_rst_n_i;
-    input usr_rx0_rst_n_i;
-    input [3:0] usr_rx0_test_i;
-    output [7:0] usr_rx0_test_o;
-    output usr_rx1_busy_o;
-    input usr_rx1_ctrl_align_en_i;
-    input usr_rx1_ctrl_align_sync_i;
-    output [7:0] usr_rx1_ctrl_char_is_a_o;
-    output usr_rx1_ctrl_char_is_aligned_o;
-    output [7:0] usr_rx1_ctrl_char_is_comma_o;
-    output [7:0] usr_rx1_ctrl_char_is_f_o;
-    output [7:0] usr_rx1_ctrl_char_is_k_o;
-    input usr_rx1_ctrl_dec_en_i;
-    output [7:0] usr_rx1_ctrl_disp_err_o;
-    input usr_rx1_ctrl_dscr_en_i;
-    input usr_rx1_ctrl_el_buff_fifo_en_i;
-    input usr_rx1_ctrl_el_buff_rst_i;
-    output [7:0] usr_rx1_ctrl_not_in_table_o;
-    input [1:0] usr_rx1_ctrl_ovs_bit_sel_i;
-    input usr_rx1_ctrl_replace_en_i;
-    output [63:0] usr_rx1_data_o;
-    output usr_rx1_pll_lock_o;
-    input usr_rx1_pma_cdr_rst_i;
-    input usr_rx1_pma_ckgen_rst_n_i;
-    output usr_rx1_pma_loss_of_signal_o;
-    input usr_rx1_pma_pll_rst_n_i;
-    input usr_rx1_rst_n_i;
-    input [3:0] usr_rx1_test_i;
-    output [7:0] usr_rx1_test_o;
-    output usr_rx2_busy_o;
-    input usr_rx2_ctrl_align_en_i;
-    input usr_rx2_ctrl_align_sync_i;
-    output [7:0] usr_rx2_ctrl_char_is_a_o;
-    output usr_rx2_ctrl_char_is_aligned_o;
-    output [7:0] usr_rx2_ctrl_char_is_comma_o;
-    output [7:0] usr_rx2_ctrl_char_is_f_o;
-    output [7:0] usr_rx2_ctrl_char_is_k_o;
-    input usr_rx2_ctrl_dec_en_i;
-    output [7:0] usr_rx2_ctrl_disp_err_o;
-    input usr_rx2_ctrl_dscr_en_i;
-    input usr_rx2_ctrl_el_buff_fifo_en_i;
-    input usr_rx2_ctrl_el_buff_rst_i;
-    output [7:0] usr_rx2_ctrl_not_in_table_o;
-    input [1:0] usr_rx2_ctrl_ovs_bit_sel_i;
-    input usr_rx2_ctrl_replace_en_i;
-    output [63:0] usr_rx2_data_o;
-    output usr_rx2_pll_lock_o;
-    input usr_rx2_pma_cdr_rst_i;
-    input usr_rx2_pma_ckgen_rst_n_i;
-    output usr_rx2_pma_loss_of_signal_o;
-    input usr_rx2_pma_pll_rst_n_i;
-    input usr_rx2_rst_n_i;
-    input [3:0] usr_rx2_test_i;
-    output [7:0] usr_rx2_test_o;
-    output usr_rx3_busy_o;
-    input usr_rx3_ctrl_align_en_i;
-    input usr_rx3_ctrl_align_sync_i;
-    output [7:0] usr_rx3_ctrl_char_is_a_o;
-    output usr_rx3_ctrl_char_is_aligned_o;
-    output [7:0] usr_rx3_ctrl_char_is_comma_o;
-    output [7:0] usr_rx3_ctrl_char_is_f_o;
-    output [7:0] usr_rx3_ctrl_char_is_k_o;
-    input usr_rx3_ctrl_dec_en_i;
-    output [7:0] usr_rx3_ctrl_disp_err_o;
-    input usr_rx3_ctrl_dscr_en_i;
-    input usr_rx3_ctrl_el_buff_fifo_en_i;
-    input usr_rx3_ctrl_el_buff_rst_i;
-    output [7:0] usr_rx3_ctrl_not_in_table_o;
-    input [1:0] usr_rx3_ctrl_ovs_bit_sel_i;
-    input usr_rx3_ctrl_replace_en_i;
-    output [63:0] usr_rx3_data_o;
-    output usr_rx3_pll_lock_o;
-    input usr_rx3_pma_cdr_rst_i;
-    input usr_rx3_pma_ckgen_rst_n_i;
-    output usr_rx3_pma_loss_of_signal_o;
-    input usr_rx3_pma_pll_rst_n_i;
-    input usr_rx3_rst_n_i;
-    input [3:0] usr_rx3_test_i;
-    output [7:0] usr_rx3_test_o;
-    output usr_rx4_busy_o;
-    input usr_rx4_ctrl_align_en_i;
-    input usr_rx4_ctrl_align_sync_i;
-    output [7:0] usr_rx4_ctrl_char_is_a_o;
-    output usr_rx4_ctrl_char_is_aligned_o;
-    output [7:0] usr_rx4_ctrl_char_is_comma_o;
-    output [7:0] usr_rx4_ctrl_char_is_f_o;
-    output [7:0] usr_rx4_ctrl_char_is_k_o;
-    input usr_rx4_ctrl_dec_en_i;
-    output [7:0] usr_rx4_ctrl_disp_err_o;
-    input usr_rx4_ctrl_dscr_en_i;
-    input usr_rx4_ctrl_el_buff_fifo_en_i;
-    input usr_rx4_ctrl_el_buff_rst_i;
-    output [7:0] usr_rx4_ctrl_not_in_table_o;
-    input [1:0] usr_rx4_ctrl_ovs_bit_sel_i;
-    input usr_rx4_ctrl_replace_en_i;
-    output [63:0] usr_rx4_data_o;
-    output usr_rx4_pll_lock_o;
-    input usr_rx4_pma_cdr_rst_i;
-    input usr_rx4_pma_ckgen_rst_n_i;
-    output usr_rx4_pma_loss_of_signal_o;
-    input usr_rx4_pma_pll_rst_n_i;
-    input usr_rx4_rst_n_i;
-    input [3:0] usr_rx4_test_i;
-    output [7:0] usr_rx4_test_o;
-    output usr_rx5_busy_o;
-    input usr_rx5_ctrl_align_en_i;
-    input usr_rx5_ctrl_align_sync_i;
-    output [7:0] usr_rx5_ctrl_char_is_a_o;
-    output usr_rx5_ctrl_char_is_aligned_o;
-    output [7:0] usr_rx5_ctrl_char_is_comma_o;
-    output [7:0] usr_rx5_ctrl_char_is_f_o;
-    output [7:0] usr_rx5_ctrl_char_is_k_o;
-    input usr_rx5_ctrl_dec_en_i;
-    output [7:0] usr_rx5_ctrl_disp_err_o;
-    input usr_rx5_ctrl_dscr_en_i;
-    input usr_rx5_ctrl_el_buff_fifo_en_i;
-    input usr_rx5_ctrl_el_buff_rst_i;
-    output [7:0] usr_rx5_ctrl_not_in_table_o;
-    input [1:0] usr_rx5_ctrl_ovs_bit_sel_i;
-    input usr_rx5_ctrl_replace_en_i;
-    output [63:0] usr_rx5_data_o;
-    output usr_rx5_pll_lock_o;
-    input usr_rx5_pma_cdr_rst_i;
-    input usr_rx5_pma_ckgen_rst_n_i;
-    output usr_rx5_pma_loss_of_signal_o;
-    input usr_rx5_pma_pll_rst_n_i;
-    input usr_rx5_rst_n_i;
-    input [3:0] usr_rx5_test_i;
-    output [7:0] usr_rx5_test_o;
-    output usr_tx0_busy_o;
-    input [7:0] usr_tx0_ctrl_char_is_k_i;
-    input [7:0] usr_tx0_ctrl_enc_en_i;
-    input [7:0] usr_tx0_ctrl_end_of_frame_i;
-    input [7:0] usr_tx0_ctrl_end_of_multiframe_i;
-    input usr_tx0_ctrl_replace_en_i;
-    input [7:0] usr_tx0_ctrl_scr_en_i;
-    input [63:0] usr_tx0_data_i;
-    input usr_tx0_pma_clk_en_i;
-    input usr_tx0_rst_n_i;
-    input [3:0] usr_tx0_test_i;
-    output [3:0] usr_tx0_test_o;
-    output usr_tx1_busy_o;
-    input [7:0] usr_tx1_ctrl_char_is_k_i;
-    input [7:0] usr_tx1_ctrl_enc_en_i;
-    input [7:0] usr_tx1_ctrl_end_of_frame_i;
-    input [7:0] usr_tx1_ctrl_end_of_multiframe_i;
-    input usr_tx1_ctrl_replace_en_i;
-    input [7:0] usr_tx1_ctrl_scr_en_i;
-    input [63:0] usr_tx1_data_i;
-    input usr_tx1_pma_clk_en_i;
-    input usr_tx1_rst_n_i;
-    input [3:0] usr_tx1_test_i;
-    output [3:0] usr_tx1_test_o;
-    output usr_tx2_busy_o;
-    input [7:0] usr_tx2_ctrl_char_is_k_i;
-    input [7:0] usr_tx2_ctrl_enc_en_i;
-    input [7:0] usr_tx2_ctrl_end_of_frame_i;
-    input [7:0] usr_tx2_ctrl_end_of_multiframe_i;
-    input usr_tx2_ctrl_replace_en_i;
-    input [7:0] usr_tx2_ctrl_scr_en_i;
-    input [63:0] usr_tx2_data_i;
-    input usr_tx2_pma_clk_en_i;
-    input usr_tx2_rst_n_i;
-    input [3:0] usr_tx2_test_i;
-    output [3:0] usr_tx2_test_o;
-    output usr_tx3_busy_o;
-    input [7:0] usr_tx3_ctrl_char_is_k_i;
-    input [7:0] usr_tx3_ctrl_enc_en_i;
-    input [7:0] usr_tx3_ctrl_end_of_frame_i;
-    input [7:0] usr_tx3_ctrl_end_of_multiframe_i;
-    input usr_tx3_ctrl_replace_en_i;
-    input [7:0] usr_tx3_ctrl_scr_en_i;
-    input [63:0] usr_tx3_data_i;
-    input usr_tx3_pma_clk_en_i;
-    input usr_tx3_rst_n_i;
-    input [3:0] usr_tx3_test_i;
-    output [3:0] usr_tx3_test_o;
-    output usr_tx4_busy_o;
-    input [7:0] usr_tx4_ctrl_char_is_k_i;
-    input [7:0] usr_tx4_ctrl_enc_en_i;
-    input [7:0] usr_tx4_ctrl_end_of_frame_i;
-    input [7:0] usr_tx4_ctrl_end_of_multiframe_i;
-    input usr_tx4_ctrl_replace_en_i;
-    input [7:0] usr_tx4_ctrl_scr_en_i;
-    input [63:0] usr_tx4_data_i;
-    input usr_tx4_pma_clk_en_i;
-    input usr_tx4_rst_n_i;
-    input [3:0] usr_tx4_test_i;
-    output [3:0] usr_tx4_test_o;
-    output usr_tx5_busy_o;
-    input [7:0] usr_tx5_ctrl_char_is_k_i;
-    input [7:0] usr_tx5_ctrl_enc_en_i;
-    input [7:0] usr_tx5_ctrl_end_of_frame_i;
-    input [7:0] usr_tx5_ctrl_end_of_multiframe_i;
-    input usr_tx5_ctrl_replace_en_i;
-    input [7:0] usr_tx5_ctrl_scr_en_i;
-    input [63:0] usr_tx5_data_i;
-    input usr_tx5_pma_clk_en_i;
-    input usr_tx5_rst_n_i;
-    input [3:0] usr_tx5_test_i;
-    output [3:0] usr_tx5_test_o;
-    parameter cfg_main_i = 34'b0000000000000000000000000000000000;
-    parameter cfg_rx0_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter cfg_rx1_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter cfg_rx2_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter cfg_rx3_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter cfg_rx4_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter cfg_rx5_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter cfg_tx0_i = 0;
-    parameter cfg_tx1_i = 0;
-    parameter cfg_tx2_i = 0;
-    parameter cfg_tx3_i = 0;
-    parameter cfg_tx4_i = 0;
-    parameter cfg_tx5_i = 0;
-    parameter location = "";
-endmodule
-
-(* blackbox *)
-module NX_HSSL_U_FULL(hssl_clk_user_tx_i, hssl_clk_user_rx_i, hssl_clk_ref_i, hssl_clock_o, hssl_rclock_o, usr_dyn_cfg_en_i, usr_dyn_cfg_calibration_cs_n_i, usr_dyn_cfg_we_n_i, usr_dyn_cfg_wdata_sel_i, usr_pll_pma_rst_n_i, usr_pll_pma_pwr_down_n_i, usr_main_rst_n_i, usr_pll_lock_o, usr_pll_pma_lock_analog_o, usr_pll_ckfb_lock_o, usr_calibrate_pma_out_o, usr_main_async_debug_ack_i, usr_main_async_debug_req_o, scan_en_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i
-, usr_tx0_busy_o, usr_tx0_ctrl_invalid_k_o, usr_tx0_ctrl_driver_pwrdwn_n_i, usr_tx0_pma_clk_en_i, usr_tx0_pma_tx_clk_o, usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_rst_n_i, usr_rx0_pma_rst_n_i, usr_rx0_pma_m_eye_rst_i, usr_rx0_pma_pwr_down_n_i, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_ctrl_valid_realign_o, usr_rx0_busy_o, usr_rx0_pma_loss_of_signal_o, usr_rx0_pma_ll_fast_locked_o, usr_rx0_pma_ll_slow_locked_o
-, usr_rx0_pma_pll_lock_o, usr_rx0_pma_pll_lock_track_o, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_busy_o, usr_tx1_ctrl_invalid_k_o, usr_tx1_ctrl_driver_pwrdwn_n_i, usr_tx1_pma_clk_en_i, usr_tx1_pma_tx_clk_o, usr_rx1_ctrl_dscr_en_i, usr_rx1_ctrl_dec_en_i, usr_rx1_ctrl_align_en_i, usr_rx1_ctrl_align_sync_i, usr_rx1_ctrl_replace_en_i, usr_rx1_ctrl_el_buff_rst_i, usr_rx1_rst_n_i, usr_rx1_pma_rst_n_i, usr_rx1_pma_m_eye_rst_i, usr_rx1_pma_pwr_down_n_i, usr_rx1_ctrl_char_is_aligned_o, usr_rx1_ctrl_valid_realign_o
-, usr_rx1_busy_o, usr_rx1_pma_loss_of_signal_o, usr_rx1_pma_ll_fast_locked_o, usr_rx1_pma_ll_slow_locked_o, usr_rx1_pma_pll_lock_o, usr_rx1_pma_pll_lock_track_o, usr_tx2_ctrl_replace_en_i, usr_tx2_rst_n_i, usr_tx2_busy_o, usr_tx2_ctrl_invalid_k_o, usr_tx2_ctrl_driver_pwrdwn_n_i, usr_tx2_pma_clk_en_i, usr_tx2_pma_tx_clk_o, usr_rx2_ctrl_dscr_en_i, usr_rx2_ctrl_dec_en_i, usr_rx2_ctrl_align_en_i, usr_rx2_ctrl_align_sync_i, usr_rx2_ctrl_replace_en_i, usr_rx2_ctrl_el_buff_rst_i, usr_rx2_rst_n_i, usr_rx2_pma_rst_n_i
-, usr_rx2_pma_m_eye_rst_i, usr_rx2_pma_pwr_down_n_i, usr_rx2_ctrl_char_is_aligned_o, usr_rx2_ctrl_valid_realign_o, usr_rx2_busy_o, usr_rx2_pma_loss_of_signal_o, usr_rx2_pma_ll_fast_locked_o, usr_rx2_pma_ll_slow_locked_o, usr_rx2_pma_pll_lock_o, usr_rx2_pma_pll_lock_track_o, usr_tx3_ctrl_replace_en_i, usr_tx3_rst_n_i, usr_tx3_busy_o, usr_tx3_ctrl_invalid_k_o, usr_tx3_ctrl_driver_pwrdwn_n_i, usr_tx3_pma_clk_en_i, usr_tx3_pma_tx_clk_o, usr_rx3_ctrl_dscr_en_i, usr_rx3_ctrl_dec_en_i, usr_rx3_ctrl_align_en_i, usr_rx3_ctrl_align_sync_i
-, usr_rx3_ctrl_replace_en_i, usr_rx3_ctrl_el_buff_rst_i, usr_rx3_rst_n_i, usr_rx3_pma_rst_n_i, usr_rx3_pma_m_eye_rst_i, usr_rx3_pma_pwr_down_n_i, usr_rx3_ctrl_char_is_aligned_o, usr_rx3_ctrl_valid_realign_o, usr_rx3_busy_o, usr_rx3_pma_loss_of_signal_o, usr_rx3_pma_ll_fast_locked_o, usr_rx3_pma_ll_slow_locked_o, usr_rx3_pma_pll_lock_o, usr_rx3_pma_pll_lock_track_o, usr_tx0_ctrl_enc_en_i, usr_tx0_ctrl_char_is_k_i, usr_tx0_ctrl_scr_en_i, usr_tx0_ctrl_end_of_multiframe_i, usr_tx0_ctrl_end_of_frame_i, usr_tx0_data_i, usr_rx0_data_o
-, usr_rx0_ctrl_ovs_bit_sel_i, usr_rx0_ctrl_char_is_comma_o, usr_rx0_ctrl_char_is_k_o, usr_rx0_ctrl_not_in_table_o, usr_rx0_ctrl_disp_err_o, usr_rx0_ctrl_char_is_a_o, usr_rx0_ctrl_char_is_f_o, usr_rx0_test_o, usr_tx1_ctrl_enc_en_i, usr_tx1_ctrl_char_is_k_i, usr_tx1_ctrl_scr_en_i, usr_tx1_ctrl_end_of_multiframe_i, usr_tx1_ctrl_end_of_frame_i, usr_tx1_data_i, usr_rx1_data_o, usr_rx1_ctrl_ovs_bit_sel_i, usr_rx1_ctrl_char_is_comma_o, usr_rx1_ctrl_char_is_k_o, usr_rx1_ctrl_not_in_table_o, usr_rx1_ctrl_disp_err_o, usr_rx1_ctrl_char_is_a_o
-, usr_rx1_ctrl_char_is_f_o, usr_rx1_test_o, usr_tx2_ctrl_enc_en_i, usr_tx2_ctrl_char_is_k_i, usr_tx2_ctrl_scr_en_i, usr_tx2_ctrl_end_of_multiframe_i, usr_tx2_ctrl_end_of_frame_i, usr_tx2_data_i, usr_rx2_data_o, usr_rx2_ctrl_ovs_bit_sel_i, usr_rx2_ctrl_char_is_comma_o, usr_rx2_ctrl_char_is_k_o, usr_rx2_ctrl_not_in_table_o, usr_rx2_ctrl_disp_err_o, usr_rx2_ctrl_char_is_a_o, usr_rx2_ctrl_char_is_f_o, usr_rx2_test_o, usr_tx3_ctrl_enc_en_i, usr_tx3_ctrl_char_is_k_i, usr_tx3_ctrl_scr_en_i, usr_tx3_ctrl_end_of_multiframe_i
-, usr_tx3_ctrl_end_of_frame_i, usr_tx3_data_i, usr_rx3_data_o, usr_rx3_ctrl_ovs_bit_sel_i, usr_rx3_ctrl_char_is_comma_o, usr_rx3_ctrl_char_is_k_o, usr_rx3_ctrl_not_in_table_o, usr_rx3_ctrl_disp_err_o, usr_rx3_ctrl_char_is_a_o, usr_rx3_ctrl_char_is_f_o, usr_rx3_test_o, usr_dyn_cfg_addr_i, usr_dyn_cfg_wdata_i, usr_main_async_debug_lane_sel_i, usr_main_rx_pma_ll_out_o, scan_in_i, scan_out_o, usr_rx0_ctrl_debug_sel_i, usr_rx1_ctrl_debug_sel_i, usr_rx2_ctrl_debug_sel_i, usr_rx3_ctrl_debug_sel_i
-, usr_dyn_cfg_lane_cs_n_i);
-    input hssl_clk_ref_i;
-    input hssl_clk_user_rx_i;
-    input hssl_clk_user_tx_i;
-    output hssl_clock_o;
-    output hssl_rclock_o;
-    input scan_en_i;
-    input [7:0] scan_in_i;
-    output [7:0] scan_out_o;
-    output usr_calibrate_pma_out_o;
-    input [3:0] usr_dyn_cfg_addr_i;
-    input usr_dyn_cfg_calibration_cs_n_i;
-    input usr_dyn_cfg_en_i;
-    input [3:0] usr_dyn_cfg_lane_cs_n_i;
-    input [11:0] usr_dyn_cfg_wdata_i;
-    input usr_dyn_cfg_wdata_sel_i;
-    input usr_dyn_cfg_we_n_i;
-    input usr_main_async_debug_ack_i;
-    input [1:0] usr_main_async_debug_lane_sel_i;
-    output usr_main_async_debug_req_o;
-    input usr_main_rst_n_i;
-    output [19:0] usr_main_rx_pma_ll_out_o;
-    output usr_pll_ckfb_lock_o;
-    output usr_pll_lock_o;
-    output usr_pll_pma_lock_analog_o;
-    input usr_pll_pma_pwr_down_n_i;
-    input usr_pll_pma_rst_n_i;
-    output usr_rx0_busy_o;
-    input usr_rx0_ctrl_align_en_i;
-    input usr_rx0_ctrl_align_sync_i;
-    output [7:0] usr_rx0_ctrl_char_is_a_o;
-    output usr_rx0_ctrl_char_is_aligned_o;
-    output [7:0] usr_rx0_ctrl_char_is_comma_o;
-    output [7:0] usr_rx0_ctrl_char_is_f_o;
-    output [7:0] usr_rx0_ctrl_char_is_k_o;
-    input [2:0] usr_rx0_ctrl_debug_sel_i;
-    input usr_rx0_ctrl_dec_en_i;
-    output [7:0] usr_rx0_ctrl_disp_err_o;
-    input usr_rx0_ctrl_dscr_en_i;
-    input usr_rx0_ctrl_el_buff_rst_i;
-    output [7:0] usr_rx0_ctrl_not_in_table_o;
-    input [1:0] usr_rx0_ctrl_ovs_bit_sel_i;
-    input usr_rx0_ctrl_replace_en_i;
-    output usr_rx0_ctrl_valid_realign_o;
-    output [63:0] usr_rx0_data_o;
-    output usr_rx0_pma_ll_fast_locked_o;
-    output usr_rx0_pma_ll_slow_locked_o;
-    output usr_rx0_pma_loss_of_signal_o;
-    input usr_rx0_pma_m_eye_rst_i;
-    output usr_rx0_pma_pll_lock_o;
-    output usr_rx0_pma_pll_lock_track_o;
-    input usr_rx0_pma_pwr_down_n_i;
-    input usr_rx0_pma_rst_n_i;
-    input usr_rx0_rst_n_i;
-    output [7:0] usr_rx0_test_o;
-    output usr_rx1_busy_o;
-    input usr_rx1_ctrl_align_en_i;
-    input usr_rx1_ctrl_align_sync_i;
-    output [7:0] usr_rx1_ctrl_char_is_a_o;
-    output usr_rx1_ctrl_char_is_aligned_o;
-    output [7:0] usr_rx1_ctrl_char_is_comma_o;
-    output [7:0] usr_rx1_ctrl_char_is_f_o;
-    output [7:0] usr_rx1_ctrl_char_is_k_o;
-    input [2:0] usr_rx1_ctrl_debug_sel_i;
-    input usr_rx1_ctrl_dec_en_i;
-    output [7:0] usr_rx1_ctrl_disp_err_o;
-    input usr_rx1_ctrl_dscr_en_i;
-    input usr_rx1_ctrl_el_buff_rst_i;
-    output [7:0] usr_rx1_ctrl_not_in_table_o;
-    input [1:0] usr_rx1_ctrl_ovs_bit_sel_i;
-    input usr_rx1_ctrl_replace_en_i;
-    output usr_rx1_ctrl_valid_realign_o;
-    output [63:0] usr_rx1_data_o;
-    output usr_rx1_pma_ll_fast_locked_o;
-    output usr_rx1_pma_ll_slow_locked_o;
-    output usr_rx1_pma_loss_of_signal_o;
-    input usr_rx1_pma_m_eye_rst_i;
-    output usr_rx1_pma_pll_lock_o;
-    output usr_rx1_pma_pll_lock_track_o;
-    input usr_rx1_pma_pwr_down_n_i;
-    input usr_rx1_pma_rst_n_i;
-    input usr_rx1_rst_n_i;
-    output [7:0] usr_rx1_test_o;
-    output usr_rx2_busy_o;
-    input usr_rx2_ctrl_align_en_i;
-    input usr_rx2_ctrl_align_sync_i;
-    output [7:0] usr_rx2_ctrl_char_is_a_o;
-    output usr_rx2_ctrl_char_is_aligned_o;
-    output [7:0] usr_rx2_ctrl_char_is_comma_o;
-    output [7:0] usr_rx2_ctrl_char_is_f_o;
-    output [7:0] usr_rx2_ctrl_char_is_k_o;
-    input [2:0] usr_rx2_ctrl_debug_sel_i;
-    input usr_rx2_ctrl_dec_en_i;
-    output [7:0] usr_rx2_ctrl_disp_err_o;
-    input usr_rx2_ctrl_dscr_en_i;
-    input usr_rx2_ctrl_el_buff_rst_i;
-    output [7:0] usr_rx2_ctrl_not_in_table_o;
-    input [1:0] usr_rx2_ctrl_ovs_bit_sel_i;
-    input usr_rx2_ctrl_replace_en_i;
-    output usr_rx2_ctrl_valid_realign_o;
-    output [63:0] usr_rx2_data_o;
-    output usr_rx2_pma_ll_fast_locked_o;
-    output usr_rx2_pma_ll_slow_locked_o;
-    output usr_rx2_pma_loss_of_signal_o;
-    input usr_rx2_pma_m_eye_rst_i;
-    output usr_rx2_pma_pll_lock_o;
-    output usr_rx2_pma_pll_lock_track_o;
-    input usr_rx2_pma_pwr_down_n_i;
-    input usr_rx2_pma_rst_n_i;
-    input usr_rx2_rst_n_i;
-    output [7:0] usr_rx2_test_o;
-    output usr_rx3_busy_o;
-    input usr_rx3_ctrl_align_en_i;
-    input usr_rx3_ctrl_align_sync_i;
-    output [7:0] usr_rx3_ctrl_char_is_a_o;
-    output usr_rx3_ctrl_char_is_aligned_o;
-    output [7:0] usr_rx3_ctrl_char_is_comma_o;
-    output [7:0] usr_rx3_ctrl_char_is_f_o;
-    output [7:0] usr_rx3_ctrl_char_is_k_o;
-    input [2:0] usr_rx3_ctrl_debug_sel_i;
-    input usr_rx3_ctrl_dec_en_i;
-    output [7:0] usr_rx3_ctrl_disp_err_o;
-    input usr_rx3_ctrl_dscr_en_i;
-    input usr_rx3_ctrl_el_buff_rst_i;
-    output [7:0] usr_rx3_ctrl_not_in_table_o;
-    input [1:0] usr_rx3_ctrl_ovs_bit_sel_i;
-    input usr_rx3_ctrl_replace_en_i;
-    output usr_rx3_ctrl_valid_realign_o;
-    output [63:0] usr_rx3_data_o;
-    output usr_rx3_pma_ll_fast_locked_o;
-    output usr_rx3_pma_ll_slow_locked_o;
-    output usr_rx3_pma_loss_of_signal_o;
-    input usr_rx3_pma_m_eye_rst_i;
-    output usr_rx3_pma_pll_lock_o;
-    output usr_rx3_pma_pll_lock_track_o;
-    input usr_rx3_pma_pwr_down_n_i;
-    input usr_rx3_pma_rst_n_i;
-    input usr_rx3_rst_n_i;
-    output [7:0] usr_rx3_test_o;
-    output usr_tx0_busy_o;
-    input [7:0] usr_tx0_ctrl_char_is_k_i;
-    input usr_tx0_ctrl_driver_pwrdwn_n_i;
-    input [7:0] usr_tx0_ctrl_enc_en_i;
-    input [7:0] usr_tx0_ctrl_end_of_frame_i;
-    input [7:0] usr_tx0_ctrl_end_of_multiframe_i;
-    output usr_tx0_ctrl_invalid_k_o;
-    input usr_tx0_ctrl_replace_en_i;
-    input [7:0] usr_tx0_ctrl_scr_en_i;
-    input [63:0] usr_tx0_data_i;
-    input usr_tx0_pma_clk_en_i;
-    output usr_tx0_pma_tx_clk_o;
-    input usr_tx0_rst_n_i;
-    output usr_tx1_busy_o;
-    input [7:0] usr_tx1_ctrl_char_is_k_i;
-    input usr_tx1_ctrl_driver_pwrdwn_n_i;
-    input [7:0] usr_tx1_ctrl_enc_en_i;
-    input [7:0] usr_tx1_ctrl_end_of_frame_i;
-    input [7:0] usr_tx1_ctrl_end_of_multiframe_i;
-    output usr_tx1_ctrl_invalid_k_o;
-    input usr_tx1_ctrl_replace_en_i;
-    input [7:0] usr_tx1_ctrl_scr_en_i;
-    input [63:0] usr_tx1_data_i;
-    input usr_tx1_pma_clk_en_i;
-    output usr_tx1_pma_tx_clk_o;
-    input usr_tx1_rst_n_i;
-    output usr_tx2_busy_o;
-    input [7:0] usr_tx2_ctrl_char_is_k_i;
-    input usr_tx2_ctrl_driver_pwrdwn_n_i;
-    input [7:0] usr_tx2_ctrl_enc_en_i;
-    input [7:0] usr_tx2_ctrl_end_of_frame_i;
-    input [7:0] usr_tx2_ctrl_end_of_multiframe_i;
-    output usr_tx2_ctrl_invalid_k_o;
-    input usr_tx2_ctrl_replace_en_i;
-    input [7:0] usr_tx2_ctrl_scr_en_i;
-    input [63:0] usr_tx2_data_i;
-    input usr_tx2_pma_clk_en_i;
-    output usr_tx2_pma_tx_clk_o;
-    input usr_tx2_rst_n_i;
-    output usr_tx3_busy_o;
-    input [7:0] usr_tx3_ctrl_char_is_k_i;
-    input usr_tx3_ctrl_driver_pwrdwn_n_i;
-    input [7:0] usr_tx3_ctrl_enc_en_i;
-    input [7:0] usr_tx3_ctrl_end_of_frame_i;
-    input [7:0] usr_tx3_ctrl_end_of_multiframe_i;
-    output usr_tx3_ctrl_invalid_k_o;
-    input usr_tx3_ctrl_replace_en_i;
-    input [7:0] usr_tx3_ctrl_scr_en_i;
-    input [63:0] usr_tx3_data_i;
-    input usr_tx3_pma_clk_en_i;
-    output usr_tx3_pma_tx_clk_o;
-    input usr_tx3_rst_n_i;
-    parameter cfg_dyn_all_rx_pma_m_eye_coarse_ena_i = 1'b0;
-    parameter cfg_dyn_all_rx_pma_m_eye_dn_i = 1'b0;
-    parameter cfg_dyn_all_rx_pma_m_eye_fine_ena_i = 1'b0;
-    parameter cfg_dyn_all_rx_pma_m_eye_i = 1'b0;
-    parameter cfg_dyn_all_rx_pma_m_eye_step_i = 4'b0000;
-    parameter cfg_dyn_all_rx_pma_m_eye_up_i = 1'b0;
-    parameter cfg_dyn_all_rx_pma_threshold_1 = 5'b00000;
-    parameter cfg_dyn_all_rx_pma_threshold_2 = 5'b00000;
-    parameter cfg_dyn_all_rx_pma_trim_locked_i = 3'b000;
-    parameter cfg_dyn_all_rx_pma_trim_mode_i = 2'b00;
-    parameter cfg_dyn_all_rx_pma_trim_unlocked_i = 3'b000;
-    parameter cfg_dyn_rx0_pma_ctle_cap_p_i = 4'b0000;
-    parameter cfg_dyn_rx0_pma_ctle_res_p_i = 4'b0000;
-    parameter cfg_dyn_rx0_pma_dfe_idac_tap1_n_i = 6'b000000;
-    parameter cfg_dyn_rx0_pma_dfe_idac_tap2_n_i = 6'b000000;
-    parameter cfg_dyn_rx0_pma_dfe_idac_tap3_n_i = 6'b000000;
-    parameter cfg_dyn_rx0_pma_dfe_idac_tap4_n_i = 6'b000000;
-    parameter cfg_dyn_rx0_pma_termination_cmd_i = 6'b000000;
-    parameter cfg_dyn_rx1_pma_ctle_cap_p_i = 4'b0000;
-    parameter cfg_dyn_rx1_pma_ctle_res_p_i = 4'b0000;
-    parameter cfg_dyn_rx1_pma_dfe_idac_tap1_n_i = 6'b000000;
-    parameter cfg_dyn_rx1_pma_dfe_idac_tap2_n_i = 6'b000000;
-    parameter cfg_dyn_rx1_pma_dfe_idac_tap3_n_i = 6'b000000;
-    parameter cfg_dyn_rx1_pma_dfe_idac_tap4_n_i = 6'b000000;
-    parameter cfg_dyn_rx1_pma_termination_cmd_i = 6'b000000;
-    parameter cfg_dyn_rx2_pma_ctle_cap_p_i = 4'b0000;
-    parameter cfg_dyn_rx2_pma_ctle_res_p_i = 4'b0000;
-    parameter cfg_dyn_rx2_pma_dfe_idac_tap1_n_i = 6'b000000;
-    parameter cfg_dyn_rx2_pma_dfe_idac_tap2_n_i = 6'b000000;
-    parameter cfg_dyn_rx2_pma_dfe_idac_tap3_n_i = 6'b000000;
-    parameter cfg_dyn_rx2_pma_dfe_idac_tap4_n_i = 6'b000000;
-    parameter cfg_dyn_rx2_pma_termination_cmd_i = 6'b000000;
-    parameter cfg_dyn_rx3_pma_ctle_cap_p_i = 4'b0000;
-    parameter cfg_dyn_rx3_pma_ctle_res_p_i = 4'b0000;
-    parameter cfg_dyn_rx3_pma_dfe_idac_tap1_n_i = 6'b000000;
-    parameter cfg_dyn_rx3_pma_dfe_idac_tap2_n_i = 6'b000000;
-    parameter cfg_dyn_rx3_pma_dfe_idac_tap3_n_i = 6'b000000;
-    parameter cfg_dyn_rx3_pma_dfe_idac_tap4_n_i = 6'b000000;
-    parameter cfg_dyn_rx3_pma_termination_cmd_i = 6'b000000;
-    parameter cfg_dyn_tx0_pma_main_en_i = 6'b000000;
-    parameter cfg_dyn_tx0_pma_main_sign_i = 1'b0;
-    parameter cfg_dyn_tx0_pma_margin_input_i = 9'b000000000;
-    parameter cfg_dyn_tx0_pma_margin_sel_i = 9'b000000000;
-    parameter cfg_dyn_tx0_pma_post_en_i = 5'b00000;
-    parameter cfg_dyn_tx0_pma_post_sel_i = 8'b00000000;
-    parameter cfg_dyn_tx0_pma_post_sign_i = 1'b0;
-    parameter cfg_dyn_tx0_pma_pre_en_i = 1'b0;
-    parameter cfg_dyn_tx0_pma_pre_sel_i = 4'b0000;
-    parameter cfg_dyn_tx0_pma_pre_sign_i = 1'b0;
-    parameter cfg_dyn_tx1_pma_main_en_i = 6'b000000;
-    parameter cfg_dyn_tx1_pma_main_sign_i = 1'b0;
-    parameter cfg_dyn_tx1_pma_margin_input_i = 9'b000000000;
-    parameter cfg_dyn_tx1_pma_margin_sel_i = 9'b000000000;
-    parameter cfg_dyn_tx1_pma_post_en_i = 5'b00000;
-    parameter cfg_dyn_tx1_pma_post_sel_i = 8'b00000000;
-    parameter cfg_dyn_tx1_pma_post_sign_i = 1'b0;
-    parameter cfg_dyn_tx1_pma_pre_en_i = 1'b0;
-    parameter cfg_dyn_tx1_pma_pre_sel_i = 4'b0000;
-    parameter cfg_dyn_tx1_pma_pre_sign_i = 1'b0;
-    parameter cfg_dyn_tx2_pma_main_en_i = 6'b000000;
-    parameter cfg_dyn_tx2_pma_main_sign_i = 1'b0;
-    parameter cfg_dyn_tx2_pma_margin_input_i = 9'b000000000;
-    parameter cfg_dyn_tx2_pma_margin_sel_i = 9'b000000000;
-    parameter cfg_dyn_tx2_pma_post_en_i = 5'b00000;
-    parameter cfg_dyn_tx2_pma_post_sel_i = 8'b00000000;
-    parameter cfg_dyn_tx2_pma_post_sign_i = 1'b0;
-    parameter cfg_dyn_tx2_pma_pre_en_i = 1'b0;
-    parameter cfg_dyn_tx2_pma_pre_sel_i = 4'b0000;
-    parameter cfg_dyn_tx2_pma_pre_sign_i = 1'b0;
-    parameter cfg_dyn_tx3_pma_main_en_i = 6'b000000;
-    parameter cfg_dyn_tx3_pma_main_sign_i = 1'b0;
-    parameter cfg_dyn_tx3_pma_margin_input_i = 9'b000000000;
-    parameter cfg_dyn_tx3_pma_margin_sel_i = 9'b000000000;
-    parameter cfg_dyn_tx3_pma_post_en_i = 5'b00000;
-    parameter cfg_dyn_tx3_pma_post_sel_i = 8'b00000000;
-    parameter cfg_dyn_tx3_pma_post_sign_i = 1'b0;
-    parameter cfg_dyn_tx3_pma_pre_en_i = 1'b0;
-    parameter cfg_dyn_tx3_pma_pre_sel_i = 4'b0000;
-    parameter cfg_dyn_tx3_pma_pre_sign_i = 1'b0;
-    parameter cfg_main_clk_to_fabric_div_en_i = 1'b0;
-    parameter cfg_main_clk_to_fabric_div_mode_i = 1'b0;
-    parameter cfg_main_clk_to_fabric_sel_i = 1'b0;
-    parameter cfg_main_rclk_to_fabric_sel_i = 2'b00;
-    parameter cfg_main_use_only_usr_clock_i = 1'b0;
-    parameter cfg_pcs_ovs_en_i = 1'b0;
-    parameter cfg_pcs_ovs_mode_i = 1'b0;
-    parameter cfg_pcs_pll_lock_ppm_i = 3'b000;
-    parameter cfg_pcs_word_len_i = 2'b00;
-    parameter cfg_pll_pma_ckref_ext_i = 1'b0;
-    parameter cfg_pll_pma_cpump_i = 4'b0000;
-    parameter cfg_pll_pma_divl_i = 2'b00;
-    parameter cfg_pll_pma_divm_i = 1'b0;
-    parameter cfg_pll_pma_divn_i = 2'b00;
-    parameter cfg_pll_pma_gbx_en_i = 1'b0;
-    parameter cfg_pll_pma_int_data_len_i = 1'b0;
-    parameter cfg_pll_pma_lvds_en_i = 1'b0;
-    parameter cfg_pll_pma_lvds_mux_i = 1'b0;
-    parameter cfg_pll_pma_mux_ckref_i = 1'b0;
-    parameter cfg_rx0_gearbox_en_i = 1'b0;
-    parameter cfg_rx0_gearbox_mode_i = 1'b0;
-    parameter cfg_rx0_pcs_8b_dscr_sel_i = 1'b0;
-    parameter cfg_rx0_pcs_align_bypass_i = 1'b0;
-    parameter cfg_rx0_pcs_buffers_bypass_i = 1'b0;
-    parameter cfg_rx0_pcs_buffers_use_cdc_i = 1'b0;
-    parameter cfg_rx0_pcs_bypass_pma_cdc_i = 1'b0;
-    parameter cfg_rx0_pcs_bypass_usr_cdc_i = 1'b0;
-    parameter cfg_rx0_pcs_comma_mask_i = 10'b0000000000;
-    parameter cfg_rx0_pcs_debug_en_i = 1'b0;
-    parameter cfg_rx0_pcs_dec_bypass_i = 1'b0;
-    parameter cfg_rx0_pcs_dscr_bypass_i = 1'b0;
-    parameter cfg_rx0_pcs_el_buff_diff_bef_comp_i = 4'b0000;
-    parameter cfg_rx0_pcs_el_buff_max_comp_i = 4'b0000;
-    parameter cfg_rx0_pcs_el_buff_only_one_skp_i = 1'b0;
-    parameter cfg_rx0_pcs_el_buff_skp_char_0_i = 9'b000000000;
-    parameter cfg_rx0_pcs_el_buff_skp_char_1_i = 9'b000000000;
-    parameter cfg_rx0_pcs_el_buff_skp_char_2_i = 9'b000000000;
-    parameter cfg_rx0_pcs_el_buff_skp_char_3_i = 9'b000000000;
-    parameter cfg_rx0_pcs_el_buff_skp_header_0_i = 9'b000000000;
-    parameter cfg_rx0_pcs_el_buff_skp_header_1_i = 9'b000000000;
-    parameter cfg_rx0_pcs_el_buff_skp_header_2_i = 9'b000000000;
-    parameter cfg_rx0_pcs_el_buff_skp_header_3_i = 9'b000000000;
-    parameter cfg_rx0_pcs_el_buff_skp_header_size_i = 2'b00;
-    parameter cfg_rx0_pcs_el_buff_skp_seq_size_i = 2'b00;
-    parameter cfg_rx0_pcs_fsm_sel_i = 2'b00;
-    parameter cfg_rx0_pcs_fsm_watchdog_en_i = 1'b0;
-    parameter cfg_rx0_pcs_loopback_i = 1'b0;
-    parameter cfg_rx0_pcs_m_comma_en_i = 1'b0;
-    parameter cfg_rx0_pcs_m_comma_val_i = 10'b0000000000;
-    parameter cfg_rx0_pcs_nb_comma_bef_realign_i = 2'b00;
-    parameter cfg_rx0_pcs_p_comma_en_i = 1'b0;
-    parameter cfg_rx0_pcs_p_comma_val_i = 10'b0000000000;
-    parameter cfg_rx0_pcs_polarity_i = 1'b0;
-    parameter cfg_rx0_pcs_protocol_size_i = 1'b0;
-    parameter cfg_rx0_pcs_replace_bypass_i = 1'b0;
-    parameter cfg_rx0_pcs_sync_supported_i = 1'b0;
-    parameter cfg_rx0_pma_cdr_cp_i = 4'b0000;
-    parameter cfg_rx0_pma_clk_pos_i = 1'b0;
-    parameter cfg_rx0_pma_coarse_ppm_i = 3'b000;
-    parameter cfg_rx0_pma_ctrl_term_i = 6'b000000;
-    parameter cfg_rx0_pma_dco_divl_i = 2'b00;
-    parameter cfg_rx0_pma_dco_divm_i = 1'b0;
-    parameter cfg_rx0_pma_dco_divn_i = 2'b00;
-    parameter cfg_rx0_pma_dco_reg_res_i = 2'b00;
-    parameter cfg_rx0_pma_dco_vref_sel_i = 1'b0;
-    parameter cfg_rx0_pma_fine_ppm_i = 3'b000;
-    parameter cfg_rx0_pma_loopback_i = 1'b0;
-    parameter cfg_rx0_pma_m_eye_ppm_i = 3'b000;
-    parameter cfg_rx0_pma_peak_detect_cmd_i = 2'b00;
-    parameter cfg_rx0_pma_peak_detect_on_i = 1'b0;
-    parameter cfg_rx0_pma_pll_cpump_n_i = 3'b000;
-    parameter cfg_rx0_pma_pll_divf_en_n_i = 1'b0;
-    parameter cfg_rx0_pma_pll_divf_i = 2'b00;
-    parameter cfg_rx0_pma_pll_divm_en_n_i = 1'b0;
-    parameter cfg_rx0_pma_pll_divm_i = 2'b00;
-    parameter cfg_rx0_pma_pll_divn_en_n_i = 1'b0;
-    parameter cfg_rx0_pma_pll_divn_i = 1'b0;
-    parameter cfg_rx1_gearbox_en_i = 1'b0;
-    parameter cfg_rx1_gearbox_mode_i = 1'b0;
-    parameter cfg_rx1_pcs_8b_dscr_sel_i = 1'b0;
-    parameter cfg_rx1_pcs_align_bypass_i = 1'b0;
-    parameter cfg_rx1_pcs_buffers_bypass_i = 1'b0;
-    parameter cfg_rx1_pcs_buffers_use_cdc_i = 1'b0;
-    parameter cfg_rx1_pcs_bypass_pma_cdc_i = 1'b0;
-    parameter cfg_rx1_pcs_bypass_usr_cdc_i = 1'b0;
-    parameter cfg_rx1_pcs_comma_mask_i = 10'b0000000000;
-    parameter cfg_rx1_pcs_debug_en_i = 1'b0;
-    parameter cfg_rx1_pcs_dec_bypass_i = 1'b0;
-    parameter cfg_rx1_pcs_dscr_bypass_i = 1'b0;
-    parameter cfg_rx1_pcs_el_buff_diff_bef_comp_i = 4'b0000;
-    parameter cfg_rx1_pcs_el_buff_max_comp_i = 4'b0000;
-    parameter cfg_rx1_pcs_el_buff_only_one_skp_i = 1'b0;
-    parameter cfg_rx1_pcs_el_buff_skp_char_0_i = 9'b000000000;
-    parameter cfg_rx1_pcs_el_buff_skp_char_1_i = 9'b000000000;
-    parameter cfg_rx1_pcs_el_buff_skp_char_2_i = 9'b000000000;
-    parameter cfg_rx1_pcs_el_buff_skp_char_3_i = 9'b000000000;
-    parameter cfg_rx1_pcs_el_buff_skp_header_0_i = 9'b000000000;
-    parameter cfg_rx1_pcs_el_buff_skp_header_1_i = 9'b000000000;
-    parameter cfg_rx1_pcs_el_buff_skp_header_2_i = 9'b000000000;
-    parameter cfg_rx1_pcs_el_buff_skp_header_3_i = 9'b000000000;
-    parameter cfg_rx1_pcs_el_buff_skp_header_size_i = 2'b00;
-    parameter cfg_rx1_pcs_el_buff_skp_seq_size_i = 2'b00;
-    parameter cfg_rx1_pcs_fsm_sel_i = 2'b00;
-    parameter cfg_rx1_pcs_fsm_watchdog_en_i = 1'b0;
-    parameter cfg_rx1_pcs_loopback_i = 1'b0;
-    parameter cfg_rx1_pcs_m_comma_en_i = 1'b0;
-    parameter cfg_rx1_pcs_m_comma_val_i = 10'b0000000000;
-    parameter cfg_rx1_pcs_nb_comma_bef_realign_i = 2'b00;
-    parameter cfg_rx1_pcs_p_comma_en_i = 1'b0;
-    parameter cfg_rx1_pcs_p_comma_val_i = 10'b0000000000;
-    parameter cfg_rx1_pcs_polarity_i = 1'b0;
-    parameter cfg_rx1_pcs_protocol_size_i = 1'b0;
-    parameter cfg_rx1_pcs_replace_bypass_i = 1'b0;
-    parameter cfg_rx1_pcs_sync_supported_i = 1'b0;
-    parameter cfg_rx1_pma_cdr_cp_i = 4'b0000;
-    parameter cfg_rx1_pma_clk_pos_i = 1'b0;
-    parameter cfg_rx1_pma_coarse_ppm_i = 3'b000;
-    parameter cfg_rx1_pma_ctrl_term_i = 6'b000000;
-    parameter cfg_rx1_pma_dco_divl_i = 2'b00;
-    parameter cfg_rx1_pma_dco_divm_i = 1'b0;
-    parameter cfg_rx1_pma_dco_divn_i = 2'b00;
-    parameter cfg_rx1_pma_dco_reg_res_i = 2'b00;
-    parameter cfg_rx1_pma_dco_vref_sel_i = 1'b0;
-    parameter cfg_rx1_pma_fine_ppm_i = 3'b000;
-    parameter cfg_rx1_pma_loopback_i = 1'b0;
-    parameter cfg_rx1_pma_m_eye_ppm_i = 3'b000;
-    parameter cfg_rx1_pma_peak_detect_cmd_i = 2'b00;
-    parameter cfg_rx1_pma_peak_detect_on_i = 1'b0;
-    parameter cfg_rx1_pma_pll_cpump_n_i = 3'b000;
-    parameter cfg_rx1_pma_pll_divf_en_n_i = 1'b0;
-    parameter cfg_rx1_pma_pll_divf_i = 2'b00;
-    parameter cfg_rx1_pma_pll_divm_en_n_i = 1'b0;
-    parameter cfg_rx1_pma_pll_divm_i = 2'b00;
-    parameter cfg_rx1_pma_pll_divn_en_n_i = 1'b0;
-    parameter cfg_rx1_pma_pll_divn_i = 1'b0;
-    parameter cfg_rx2_gearbox_en_i = 1'b0;
-    parameter cfg_rx2_gearbox_mode_i = 1'b0;
-    parameter cfg_rx2_pcs_8b_dscr_sel_i = 1'b0;
-    parameter cfg_rx2_pcs_align_bypass_i = 1'b0;
-    parameter cfg_rx2_pcs_buffers_bypass_i = 1'b0;
-    parameter cfg_rx2_pcs_buffers_use_cdc_i = 1'b0;
-    parameter cfg_rx2_pcs_bypass_pma_cdc_i = 1'b0;
-    parameter cfg_rx2_pcs_bypass_usr_cdc_i = 1'b0;
-    parameter cfg_rx2_pcs_comma_mask_i = 10'b0000000000;
-    parameter cfg_rx2_pcs_debug_en_i = 1'b0;
-    parameter cfg_rx2_pcs_dec_bypass_i = 1'b0;
-    parameter cfg_rx2_pcs_dscr_bypass_i = 1'b0;
-    parameter cfg_rx2_pcs_el_buff_diff_bef_comp_i = 4'b0000;
-    parameter cfg_rx2_pcs_el_buff_max_comp_i = 4'b0000;
-    parameter cfg_rx2_pcs_el_buff_only_one_skp_i = 1'b0;
-    parameter cfg_rx2_pcs_el_buff_skp_char_0_i = 9'b000000000;
-    parameter cfg_rx2_pcs_el_buff_skp_char_1_i = 9'b000000000;
-    parameter cfg_rx2_pcs_el_buff_skp_char_2_i = 9'b000000000;
-    parameter cfg_rx2_pcs_el_buff_skp_char_3_i = 9'b000000000;
-    parameter cfg_rx2_pcs_el_buff_skp_header_0_i = 9'b000000000;
-    parameter cfg_rx2_pcs_el_buff_skp_header_1_i = 9'b000000000;
-    parameter cfg_rx2_pcs_el_buff_skp_header_2_i = 9'b000000000;
-    parameter cfg_rx2_pcs_el_buff_skp_header_3_i = 9'b000000000;
-    parameter cfg_rx2_pcs_el_buff_skp_header_size_i = 2'b00;
-    parameter cfg_rx2_pcs_el_buff_skp_seq_size_i = 2'b00;
-    parameter cfg_rx2_pcs_fsm_sel_i = 2'b00;
-    parameter cfg_rx2_pcs_fsm_watchdog_en_i = 1'b0;
-    parameter cfg_rx2_pcs_loopback_i = 1'b0;
-    parameter cfg_rx2_pcs_m_comma_en_i = 1'b0;
-    parameter cfg_rx2_pcs_m_comma_val_i = 10'b0000000000;
-    parameter cfg_rx2_pcs_nb_comma_bef_realign_i = 2'b00;
-    parameter cfg_rx2_pcs_p_comma_en_i = 1'b0;
-    parameter cfg_rx2_pcs_p_comma_val_i = 10'b0000000000;
-    parameter cfg_rx2_pcs_polarity_i = 1'b0;
-    parameter cfg_rx2_pcs_protocol_size_i = 1'b0;
-    parameter cfg_rx2_pcs_replace_bypass_i = 1'b0;
-    parameter cfg_rx2_pcs_sync_supported_i = 1'b0;
-    parameter cfg_rx2_pma_cdr_cp_i = 4'b0000;
-    parameter cfg_rx2_pma_clk_pos_i = 1'b0;
-    parameter cfg_rx2_pma_coarse_ppm_i = 3'b000;
-    parameter cfg_rx2_pma_ctrl_term_i = 6'b000000;
-    parameter cfg_rx2_pma_dco_divl_i = 2'b00;
-    parameter cfg_rx2_pma_dco_divm_i = 1'b0;
-    parameter cfg_rx2_pma_dco_divn_i = 2'b00;
-    parameter cfg_rx2_pma_dco_reg_res_i = 2'b00;
-    parameter cfg_rx2_pma_dco_vref_sel_i = 1'b0;
-    parameter cfg_rx2_pma_fine_ppm_i = 3'b000;
-    parameter cfg_rx2_pma_loopback_i = 1'b0;
-    parameter cfg_rx2_pma_m_eye_ppm_i = 3'b000;
-    parameter cfg_rx2_pma_peak_detect_cmd_i = 2'b00;
-    parameter cfg_rx2_pma_peak_detect_on_i = 1'b0;
-    parameter cfg_rx2_pma_pll_cpump_n_i = 3'b000;
-    parameter cfg_rx2_pma_pll_divf_en_n_i = 1'b0;
-    parameter cfg_rx2_pma_pll_divf_i = 2'b00;
-    parameter cfg_rx2_pma_pll_divm_en_n_i = 1'b0;
-    parameter cfg_rx2_pma_pll_divm_i = 2'b00;
-    parameter cfg_rx2_pma_pll_divn_en_n_i = 1'b0;
-    parameter cfg_rx2_pma_pll_divn_i = 1'b0;
-    parameter cfg_rx3_gearbox_en_i = 1'b0;
-    parameter cfg_rx3_gearbox_mode_i = 1'b0;
-    parameter cfg_rx3_pcs_8b_dscr_sel_i = 1'b0;
-    parameter cfg_rx3_pcs_align_bypass_i = 1'b0;
-    parameter cfg_rx3_pcs_buffers_bypass_i = 1'b0;
-    parameter cfg_rx3_pcs_buffers_use_cdc_i = 1'b0;
-    parameter cfg_rx3_pcs_bypass_pma_cdc_i = 1'b0;
-    parameter cfg_rx3_pcs_bypass_usr_cdc_i = 1'b0;
-    parameter cfg_rx3_pcs_comma_mask_i = 10'b0000000000;
-    parameter cfg_rx3_pcs_debug_en_i = 1'b0;
-    parameter cfg_rx3_pcs_dec_bypass_i = 1'b0;
-    parameter cfg_rx3_pcs_dscr_bypass_i = 1'b0;
-    parameter cfg_rx3_pcs_el_buff_diff_bef_comp_i = 4'b0000;
-    parameter cfg_rx3_pcs_el_buff_max_comp_i = 4'b0000;
-    parameter cfg_rx3_pcs_el_buff_only_one_skp_i = 1'b0;
-    parameter cfg_rx3_pcs_el_buff_skp_char_0_i = 9'b000000000;
-    parameter cfg_rx3_pcs_el_buff_skp_char_1_i = 9'b000000000;
-    parameter cfg_rx3_pcs_el_buff_skp_char_2_i = 9'b000000000;
-    parameter cfg_rx3_pcs_el_buff_skp_char_3_i = 9'b000000000;
-    parameter cfg_rx3_pcs_el_buff_skp_header_0_i = 9'b000000000;
-    parameter cfg_rx3_pcs_el_buff_skp_header_1_i = 9'b000000000;
-    parameter cfg_rx3_pcs_el_buff_skp_header_2_i = 9'b000000000;
-    parameter cfg_rx3_pcs_el_buff_skp_header_3_i = 9'b000000000;
-    parameter cfg_rx3_pcs_el_buff_skp_header_size_i = 2'b00;
-    parameter cfg_rx3_pcs_el_buff_skp_seq_size_i = 2'b00;
-    parameter cfg_rx3_pcs_fsm_sel_i = 2'b00;
-    parameter cfg_rx3_pcs_fsm_watchdog_en_i = 1'b0;
-    parameter cfg_rx3_pcs_loopback_i = 1'b0;
-    parameter cfg_rx3_pcs_m_comma_en_i = 1'b0;
-    parameter cfg_rx3_pcs_m_comma_val_i = 10'b0000000000;
-    parameter cfg_rx3_pcs_nb_comma_bef_realign_i = 2'b00;
-    parameter cfg_rx3_pcs_p_comma_en_i = 1'b0;
-    parameter cfg_rx3_pcs_p_comma_val_i = 10'b0000000000;
-    parameter cfg_rx3_pcs_polarity_i = 1'b0;
-    parameter cfg_rx3_pcs_protocol_size_i = 1'b0;
-    parameter cfg_rx3_pcs_replace_bypass_i = 1'b0;
-    parameter cfg_rx3_pcs_sync_supported_i = 1'b0;
-    parameter cfg_rx3_pma_cdr_cp_i = 4'b0000;
-    parameter cfg_rx3_pma_clk_pos_i = 1'b0;
-    parameter cfg_rx3_pma_coarse_ppm_i = 3'b000;
-    parameter cfg_rx3_pma_ctrl_term_i = 6'b000000;
-    parameter cfg_rx3_pma_dco_divl_i = 2'b00;
-    parameter cfg_rx3_pma_dco_divm_i = 1'b0;
-    parameter cfg_rx3_pma_dco_divn_i = 2'b00;
-    parameter cfg_rx3_pma_dco_reg_res_i = 2'b00;
-    parameter cfg_rx3_pma_dco_vref_sel_i = 1'b0;
-    parameter cfg_rx3_pma_fine_ppm_i = 3'b000;
-    parameter cfg_rx3_pma_loopback_i = 1'b0;
-    parameter cfg_rx3_pma_m_eye_ppm_i = 3'b000;
-    parameter cfg_rx3_pma_peak_detect_cmd_i = 2'b00;
-    parameter cfg_rx3_pma_peak_detect_on_i = 1'b0;
-    parameter cfg_rx3_pma_pll_cpump_n_i = 3'b000;
-    parameter cfg_rx3_pma_pll_divf_en_n_i = 1'b0;
-    parameter cfg_rx3_pma_pll_divf_i = 2'b00;
-    parameter cfg_rx3_pma_pll_divm_en_n_i = 1'b0;
-    parameter cfg_rx3_pma_pll_divm_i = 2'b00;
-    parameter cfg_rx3_pma_pll_divn_en_n_i = 1'b0;
-    parameter cfg_rx3_pma_pll_divn_i = 1'b0;
-    parameter cfg_test_mode_i = 2'b00;
-    parameter cfg_tx0_gearbox_en_i = 1'b0;
-    parameter cfg_tx0_gearbox_mode_i = 1'b0;
-    parameter cfg_tx0_pcs_8b_scr_sel_i = 1'b0;
-    parameter cfg_tx0_pcs_bypass_pma_cdc_i = 1'b0;
-    parameter cfg_tx0_pcs_bypass_usr_cdc_i = 1'b0;
-    parameter cfg_tx0_pcs_enc_bypass_i = 1'b0;
-    parameter cfg_tx0_pcs_esistream_fsm_en_i = 1'b0;
-    parameter cfg_tx0_pcs_loopback_i = 1'b0;
-    parameter cfg_tx0_pcs_polarity_i = 1'b0;
-    parameter cfg_tx0_pcs_protocol_size_i = 1'b0;
-    parameter cfg_tx0_pcs_replace_bypass_i = 1'b0;
-    parameter cfg_tx0_pcs_scr_bypass_i = 1'b0;
-    parameter cfg_tx0_pcs_scr_init_i = 17'b00000000000000000;
-    parameter cfg_tx0_pcs_sync_supported_i = 1'b0;
-    parameter cfg_tx0_pma_clk_pos_i = 1'b0;
-    parameter cfg_tx0_pma_loopback_i = 1'b0;
-    parameter cfg_tx1_gearbox_en_i = 1'b0;
-    parameter cfg_tx1_gearbox_mode_i = 1'b0;
-    parameter cfg_tx1_pcs_8b_scr_sel_i = 1'b0;
-    parameter cfg_tx1_pcs_bypass_pma_cdc_i = 1'b0;
-    parameter cfg_tx1_pcs_bypass_usr_cdc_i = 1'b0;
-    parameter cfg_tx1_pcs_enc_bypass_i = 1'b0;
-    parameter cfg_tx1_pcs_esistream_fsm_en_i = 1'b0;
-    parameter cfg_tx1_pcs_loopback_i = 1'b0;
-    parameter cfg_tx1_pcs_polarity_i = 1'b0;
-    parameter cfg_tx1_pcs_protocol_size_i = 1'b0;
-    parameter cfg_tx1_pcs_replace_bypass_i = 1'b0;
-    parameter cfg_tx1_pcs_scr_bypass_i = 1'b0;
-    parameter cfg_tx1_pcs_scr_init_i = 17'b00000000000000000;
-    parameter cfg_tx1_pcs_sync_supported_i = 1'b0;
-    parameter cfg_tx1_pma_clk_pos_i = 1'b0;
-    parameter cfg_tx1_pma_loopback_i = 1'b0;
-    parameter cfg_tx2_gearbox_en_i = 1'b0;
-    parameter cfg_tx2_gearbox_mode_i = 1'b0;
-    parameter cfg_tx2_pcs_8b_scr_sel_i = 1'b0;
-    parameter cfg_tx2_pcs_bypass_pma_cdc_i = 1'b0;
-    parameter cfg_tx2_pcs_bypass_usr_cdc_i = 1'b0;
-    parameter cfg_tx2_pcs_enc_bypass_i = 1'b0;
-    parameter cfg_tx2_pcs_esistream_fsm_en_i = 1'b0;
-    parameter cfg_tx2_pcs_loopback_i = 1'b0;
-    parameter cfg_tx2_pcs_polarity_i = 1'b0;
-    parameter cfg_tx2_pcs_protocol_size_i = 1'b0;
-    parameter cfg_tx2_pcs_replace_bypass_i = 1'b0;
-    parameter cfg_tx2_pcs_scr_bypass_i = 1'b0;
-    parameter cfg_tx2_pcs_scr_init_i = 17'b00000000000000000;
-    parameter cfg_tx2_pcs_sync_supported_i = 1'b0;
-    parameter cfg_tx2_pma_clk_pos_i = 1'b0;
-    parameter cfg_tx2_pma_loopback_i = 1'b0;
-    parameter cfg_tx3_gearbox_en_i = 1'b0;
-    parameter cfg_tx3_gearbox_mode_i = 1'b0;
-    parameter cfg_tx3_pcs_8b_scr_sel_i = 1'b0;
-    parameter cfg_tx3_pcs_bypass_pma_cdc_i = 1'b0;
-    parameter cfg_tx3_pcs_bypass_usr_cdc_i = 1'b0;
-    parameter cfg_tx3_pcs_enc_bypass_i = 1'b0;
-    parameter cfg_tx3_pcs_esistream_fsm_en_i = 1'b0;
-    parameter cfg_tx3_pcs_loopback_i = 1'b0;
-    parameter cfg_tx3_pcs_polarity_i = 1'b0;
-    parameter cfg_tx3_pcs_protocol_size_i = 1'b0;
-    parameter cfg_tx3_pcs_replace_bypass_i = 1'b0;
-    parameter cfg_tx3_pcs_scr_bypass_i = 1'b0;
-    parameter cfg_tx3_pcs_scr_init_i = 17'b00000000000000000;
-    parameter cfg_tx3_pcs_sync_supported_i = 1'b0;
-    parameter cfg_tx3_pma_clk_pos_i = 1'b0;
-    parameter cfg_tx3_pma_loopback_i = 1'b0;
-    parameter location = "";
-    parameter rx_usrclk_use_pcs_clk_2 = 1'b0;
-    parameter tx_usrclk_use_pcs_clk_2 = 1'b0;
-endmodule
-
 (* blackbox *)
 module NX_IOB(I, C, T, O, IO);
     input C;
@@ -1116,935 +214,6 @@ module NX_IOM_BIN2GRP(GS, DS, GVON, GVIN, GVDN, PA, LA);
     output [3:0] PA;
 endmodule
 
-(* blackbox *)
-module NX_IOM_CONTROL(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3
-, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3
-, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1
-, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1
-, DRO2, DRO3, DRO4, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16
-, LINK17, LINK18, LINK19, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);
-    output C1RED;
-    input C1RNE;
-    input C1RS;
-    input C1RW1;
-    input C1RW2;
-    input C1RW3;
-    input C1TS;
-    input C1TW;
-    output C2RED;
-    input C2RNE;
-    input C2RS;
-    input C2RW1;
-    input C2RW2;
-    input C2RW3;
-    input C2TS;
-    input C2TW;
-    input CAD1;
-    input CAD2;
-    input CAD3;
-    input CAD4;
-    input CAD5;
-    input CAD6;
-    output CAL;
-    input CAN1;
-    input CAN2;
-    input CAN3;
-    input CAN4;
-    input CAP1;
-    input CAP2;
-    input CAP3;
-    input CAP4;
-    input CAT1;
-    input CAT2;
-    input CAT3;
-    input CAT4;
-    input CCK;
-    output CKO1;
-    output CKO2;
-    input CTCK;
-    input DC;
-    input DCK;
-    input DIG;
-    input DIS;
-    input DOG;
-    input DOS;
-    input DPAG;
-    input DPAS;
-    input DQSG;
-    input DQSS;
-    input DRA1;
-    input DRA2;
-    input DRA3;
-    input DRA4;
-    input DRA5;
-    input DRA6;
-    input DRI1;
-    input DRI2;
-    input DRI3;
-    input DRI4;
-    input DRI5;
-    input DRI6;
-    input DRL;
-    output DRO1;
-    output DRO2;
-    output DRO3;
-    output DRO4;
-    output DRO5;
-    output DRO6;
-    input DS1;
-    input DS2;
-    input FA1;
-    input FA2;
-    input FA3;
-    input FA4;
-    input FA5;
-    input FA6;
-    output FLD;
-    output FLG;
-    input FZ;
-    inout [41:0] LINK1;
-    inout [41:0] LINK10;
-    inout [41:0] LINK11;
-    inout [41:0] LINK12;
-    inout [41:0] LINK13;
-    inout [41:0] LINK14;
-    inout [41:0] LINK15;
-    inout [41:0] LINK16;
-    inout [41:0] LINK17;
-    inout [41:0] LINK18;
-    inout [41:0] LINK19;
-    inout [41:0] LINK2;
-    inout [41:0] LINK20;
-    inout [41:0] LINK21;
-    inout [41:0] LINK22;
-    inout [41:0] LINK23;
-    inout [41:0] LINK24;
-    inout [41:0] LINK25;
-    inout [41:0] LINK26;
-    inout [41:0] LINK27;
-    inout [41:0] LINK28;
-    inout [41:0] LINK29;
-    inout [41:0] LINK3;
-    inout [41:0] LINK30;
-    inout [41:0] LINK31;
-    inout [41:0] LINK32;
-    inout [41:0] LINK33;
-    inout [41:0] LINK34;
-    inout [41:0] LINK4;
-    inout [41:0] LINK5;
-    inout [41:0] LINK6;
-    inout [41:0] LINK7;
-    inout [41:0] LINK8;
-    inout [41:0] LINK9;
-    input RRCK1;
-    input RRCK2;
-    input RTCK1;
-    input RTCK2;
-    input SPI1;
-    input SPI2;
-    input SPI3;
-    input WRCK1;
-    input WRCK2;
-    input WTCK1;
-    input WTCK2;
-    parameter div_rx1 = 4'b0000;
-    parameter div_rx2 = 4'b0000;
-    parameter div_tx1 = 4'b0000;
-    parameter div_tx2 = 4'b0000;
-    parameter inv_di_fclk1 = 1'b0;
-    parameter inv_di_fclk2 = 1'b0;
-    parameter latency1 = 1'b0;
-    parameter latency2 = 1'b0;
-    parameter location = "";
-    parameter mode_cpath = "";
-    parameter mode_epath = "";
-    parameter mode_io_cal = 1'b0;
-    parameter mode_rpath = "";
-    parameter mode_side1 = 0;
-    parameter mode_side2 = 0;
-    parameter mode_tpath = "";
-    parameter sel_clk_out1 = 1'b0;
-    parameter sel_clk_out2 = 1'b0;
-    parameter sel_clkr_rx1 = 1'b0;
-    parameter sel_clkr_rx2 = 1'b0;
-    parameter sel_clkw_rx1 = 2'b00;
-    parameter sel_clkw_rx2 = 2'b00;
-endmodule
-
-(* blackbox *)
-module NX_IOM_CONTROL_L(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3
-, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3
-, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1
-, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3, DRO4
-, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16, LINK17, LINK18, LINK19
-, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);
-    output C1RED;
-    input C1RNE;
-    input C1RS;
-    input C1RW1;
-    input C1RW2;
-    input C1RW3;
-    input C1TS;
-    input C1TW;
-    output C2RED;
-    input C2RNE;
-    input C2RS;
-    input C2RW1;
-    input C2RW2;
-    input C2RW3;
-    input C2TS;
-    input C2TW;
-    input CAD1;
-    input CAD2;
-    input CAD3;
-    input CAD4;
-    input CAD5;
-    input CAD6;
-    output CAL;
-    input CAN1;
-    input CAN2;
-    input CAN3;
-    input CAN4;
-    input CAP1;
-    input CAP2;
-    input CAP3;
-    input CAP4;
-    input CAT1;
-    input CAT2;
-    input CAT3;
-    input CAT4;
-    input CCK;
-    output CKO1;
-    output CKO2;
-    input CTCK;
-    input DC;
-    input DCK;
-    input DIG;
-    input DIS;
-    input DOG;
-    input DOS;
-    input DPAG;
-    input DPAS;
-    input DQSG;
-    input DQSS;
-    input DRA1;
-    input DRA2;
-    input DRA3;
-    input DRA4;
-    input DRA5;
-    input DRA6;
-    input DRI1;
-    input DRI2;
-    input DRI3;
-    input DRI4;
-    input DRI5;
-    input DRI6;
-    input DRL;
-    output DRO1;
-    output DRO2;
-    output DRO3;
-    output DRO4;
-    output DRO5;
-    output DRO6;
-    input DS1;
-    input DS2;
-    input FA1;
-    input FA2;
-    input FA3;
-    input FA4;
-    input FA5;
-    input FA6;
-    output FLD;
-    output FLG;
-    input FZ;
-    inout [41:0] LINK1;
-    inout [41:0] LINK10;
-    inout [41:0] LINK11;
-    inout [41:0] LINK12;
-    inout [41:0] LINK13;
-    inout [41:0] LINK14;
-    inout [41:0] LINK15;
-    inout [41:0] LINK16;
-    inout [41:0] LINK17;
-    inout [41:0] LINK18;
-    inout [41:0] LINK19;
-    inout [41:0] LINK2;
-    inout [41:0] LINK20;
-    inout [41:0] LINK21;
-    inout [41:0] LINK22;
-    inout [41:0] LINK23;
-    inout [41:0] LINK24;
-    inout [41:0] LINK25;
-    inout [41:0] LINK26;
-    inout [41:0] LINK27;
-    inout [41:0] LINK28;
-    inout [41:0] LINK29;
-    inout [41:0] LINK3;
-    inout [41:0] LINK30;
-    inout [41:0] LINK31;
-    inout [41:0] LINK32;
-    inout [41:0] LINK33;
-    inout [41:0] LINK34;
-    inout [41:0] LINK4;
-    inout [41:0] LINK5;
-    inout [41:0] LINK6;
-    inout [41:0] LINK7;
-    inout [41:0] LINK8;
-    inout [41:0] LINK9;
-    input RRCK1;
-    input RRCK2;
-    input RTCK1;
-    input RTCK2;
-    input WRCK1;
-    input WRCK2;
-    input WTCK1;
-    input WTCK2;
-    parameter div_rx1 = 4'b0000;
-    parameter div_rx2 = 4'b0000;
-    parameter div_tx1 = 4'b0000;
-    parameter div_tx2 = 4'b0000;
-    parameter inv_di_fclk1 = 1'b0;
-    parameter inv_di_fclk2 = 1'b0;
-    parameter latency1 = 1'b0;
-    parameter latency2 = 1'b0;
-    parameter location = "";
-    parameter mode_cpath = "";
-    parameter mode_epath = "";
-    parameter mode_io_cal = 1'b0;
-    parameter mode_rpath = "";
-    parameter mode_side1 = 0;
-    parameter mode_side2 = 0;
-    parameter mode_tpath = "";
-    parameter sel_clk_out1 = 1'b0;
-    parameter sel_clk_out2 = 1'b0;
-    parameter sel_clkr_rx1 = 1'b0;
-    parameter sel_clkr_rx2 = 1'b0;
-    parameter sel_clkw_rx1 = 2'b00;
-    parameter sel_clkw_rx2 = 2'b00;
-endmodule
-
-(* blackbox *)
-module NX_IOM_CONTROL_M(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3
-, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3
-, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1
-, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1
-, DRO2, DRO3, DRO4, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16
-, LINK17, LINK18, LINK19, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);
-    output C1RED;
-    input C1RNE;
-    input C1RS;
-    input C1RW1;
-    input C1RW2;
-    input C1RW3;
-    input C1TS;
-    input C1TW;
-    output C2RED;
-    input C2RNE;
-    input C2RS;
-    input C2RW1;
-    input C2RW2;
-    input C2RW3;
-    input C2TS;
-    input C2TW;
-    input CAD1;
-    input CAD2;
-    input CAD3;
-    input CAD4;
-    input CAD5;
-    input CAD6;
-    output CAL;
-    input CAN1;
-    input CAN2;
-    input CAN3;
-    input CAN4;
-    input CAP1;
-    input CAP2;
-    input CAP3;
-    input CAP4;
-    input CAT1;
-    input CAT2;
-    input CAT3;
-    input CAT4;
-    input CCK;
-    output CKO1;
-    output CKO2;
-    input CTCK;
-    input DC;
-    input DCK;
-    input DIG;
-    input DIS;
-    input DOG;
-    input DOS;
-    input DPAG;
-    input DPAS;
-    input DQSG;
-    input DQSS;
-    input DRA1;
-    input DRA2;
-    input DRA3;
-    input DRA4;
-    input DRA5;
-    input DRA6;
-    input DRI1;
-    input DRI2;
-    input DRI3;
-    input DRI4;
-    input DRI5;
-    input DRI6;
-    input DRL;
-    output DRO1;
-    output DRO2;
-    output DRO3;
-    output DRO4;
-    output DRO5;
-    output DRO6;
-    input DS1;
-    input DS2;
-    input FA1;
-    input FA2;
-    input FA3;
-    input FA4;
-    input FA5;
-    input FA6;
-    output FLD;
-    output FLG;
-    input FZ;
-    inout [41:0] LINK1;
-    inout [41:0] LINK10;
-    inout [41:0] LINK11;
-    inout [41:0] LINK12;
-    inout [41:0] LINK13;
-    inout [41:0] LINK14;
-    inout [41:0] LINK15;
-    inout [41:0] LINK16;
-    inout [41:0] LINK17;
-    inout [41:0] LINK18;
-    inout [41:0] LINK19;
-    inout [41:0] LINK2;
-    inout [41:0] LINK20;
-    inout [41:0] LINK21;
-    inout [41:0] LINK22;
-    inout [41:0] LINK23;
-    inout [41:0] LINK24;
-    inout [41:0] LINK25;
-    inout [41:0] LINK26;
-    inout [41:0] LINK27;
-    inout [41:0] LINK28;
-    inout [41:0] LINK29;
-    inout [41:0] LINK3;
-    inout [41:0] LINK30;
-    inout [41:0] LINK31;
-    inout [41:0] LINK32;
-    inout [41:0] LINK33;
-    inout [41:0] LINK34;
-    inout [41:0] LINK4;
-    inout [41:0] LINK5;
-    inout [41:0] LINK6;
-    inout [41:0] LINK7;
-    inout [41:0] LINK8;
-    inout [41:0] LINK9;
-    input RRCK1;
-    input RRCK2;
-    input RTCK1;
-    input RTCK2;
-    input SPI1;
-    input SPI2;
-    input SPI3;
-    input WRCK1;
-    input WRCK2;
-    input WTCK1;
-    input WTCK2;
-    parameter div_rx1 = 4'b0000;
-    parameter div_rx2 = 4'b0000;
-    parameter div_tx1 = 4'b0000;
-    parameter div_tx2 = 4'b0000;
-    parameter inv_di_fclk1 = 1'b0;
-    parameter inv_di_fclk2 = 1'b0;
-    parameter latency1 = 1'b0;
-    parameter latency2 = 1'b0;
-    parameter location = "";
-    parameter mode_cpath = "";
-    parameter mode_epath = "";
-    parameter mode_io_cal = 1'b0;
-    parameter mode_rpath = "";
-    parameter mode_side1 = 0;
-    parameter mode_side2 = 0;
-    parameter mode_tpath = "";
-    parameter sel_clk_out1 = 1'b0;
-    parameter sel_clk_out2 = 1'b0;
-    parameter sel_clkr_rx1 = 1'b0;
-    parameter sel_clkr_rx2 = 1'b0;
-    parameter sel_clkw_rx1 = 2'b00;
-    parameter sel_clkw_rx2 = 2'b00;
-endmodule
-
-(* blackbox *)
-module NX_IOM_CONTROL_U(ALCK1, ALCK2, ALCK3, LDSCK1, LDSCK2, LDSCK3, SWRX1CK, SWRX2CK, FCK1, FCK2, FDCK, CCK, DQ1CI1, DQ1CI2, DQ1CI3, DQ1CI4, DQ1CI5, DQ1CI6, DQ1CI7, DQ1CI8, DQ2CI1
-, DQ2CI2, DQ2CI3, DQ2CI4, DQ2CI5, DQ2CI6, DQ2CI7, DQ2CI8, DQ3CI1, DQ3CI2, DQ3CI3, DQ3CI4, DQ3CI5, DQ3CI6, DQ3CI7, DQ3CI8, DQS1CI1, DQS1CI2, DQS1CI3, DQS1CI4, DQS1CI5, DQS1CI6
-, DQS1CI7, DQS1CI8, DQS2CI1, DQS2CI2, DQS2CI3, DQS2CI4, DQS2CI5, DQS2CI6, DQS2CI7, DQS2CI8, DQS3CI1, DQS3CI2, DQS3CI3, DQS3CI4, DQS3CI5, DQS3CI6, DQS3CI7, DQS3CI8, LD1RN, LD2RN, LD3RN
-, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DCRN, LE, SE, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4, DRO1CSN
-, DRO2CSN, DRO3CSN, DRI1CSN, DRI2CSN, DRI3CSN, DRDPA1CSN, DRDPA2CSN, DRDPA3CSN, DRCCSN, DRWDS, DRWEN, DRE, CA1P1, CA1P2, CA1P3, CA1P4, CA2P1, CA2P2, CA2P3, CA2P4, CA1N1
-, CA1N2, CA1N3, CA1N4, CA2N1, CA2N2, CA2N3, CA2N4, CA1T1, CA1T2, CA1T3, CA1T4, CA2T1, CA2T2, CA2T3, CA2T4, CA1D1, CA1D2, CA1D3, CA1D4, CA1D5, CA1D6
-, CA2D1, CA2D2, CA2D3, CA2D4, CA2D5, CA2D6, CKO1, CKO2, FLD, FLG, AL1D, AL2D, AL3D, AL1T, AL2T, AL3T, DCL, DRO1, DRO2, DRO3, DRO4
-, DRO5, DRO6, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16, LINK17, LINK18, LINK19, LINK20
-, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);
-    output AL1D;
-    output AL1T;
-    output AL2D;
-    output AL2T;
-    output AL3D;
-    output AL3T;
-    input ALCK1;
-    input ALCK2;
-    input ALCK3;
-    input CA1D1;
-    input CA1D2;
-    input CA1D3;
-    input CA1D4;
-    input CA1D5;
-    input CA1D6;
-    input CA1N1;
-    input CA1N2;
-    input CA1N3;
-    input CA1N4;
-    input CA1P1;
-    input CA1P2;
-    input CA1P3;
-    input CA1P4;
-    input CA1T1;
-    input CA1T2;
-    input CA1T3;
-    input CA1T4;
-    input CA2D1;
-    input CA2D2;
-    input CA2D3;
-    input CA2D4;
-    input CA2D5;
-    input CA2D6;
-    input CA2N1;
-    input CA2N2;
-    input CA2N3;
-    input CA2N4;
-    input CA2P1;
-    input CA2P2;
-    input CA2P3;
-    input CA2P4;
-    input CA2T1;
-    input CA2T2;
-    input CA2T3;
-    input CA2T4;
-    input CCK;
-    output CKO1;
-    output CKO2;
-    output DCL;
-    input DCRN;
-    input DQ1CI1;
-    input DQ1CI2;
-    input DQ1CI3;
-    input DQ1CI4;
-    input DQ1CI5;
-    input DQ1CI6;
-    input DQ1CI7;
-    input DQ1CI8;
-    input DQ2CI1;
-    input DQ2CI2;
-    input DQ2CI3;
-    input DQ2CI4;
-    input DQ2CI5;
-    input DQ2CI6;
-    input DQ2CI7;
-    input DQ2CI8;
-    input DQ3CI1;
-    input DQ3CI2;
-    input DQ3CI3;
-    input DQ3CI4;
-    input DQ3CI5;
-    input DQ3CI6;
-    input DQ3CI7;
-    input DQ3CI8;
-    input DQS1CI1;
-    input DQS1CI2;
-    input DQS1CI3;
-    input DQS1CI4;
-    input DQS1CI5;
-    input DQS1CI6;
-    input DQS1CI7;
-    input DQS1CI8;
-    input DQS2CI1;
-    input DQS2CI2;
-    input DQS2CI3;
-    input DQS2CI4;
-    input DQS2CI5;
-    input DQS2CI6;
-    input DQS2CI7;
-    input DQS2CI8;
-    input DQS3CI1;
-    input DQS3CI2;
-    input DQS3CI3;
-    input DQS3CI4;
-    input DQS3CI5;
-    input DQS3CI6;
-    input DQS3CI7;
-    input DQS3CI8;
-    input DRA1;
-    input DRA2;
-    input DRA3;
-    input DRA4;
-    input DRCCSN;
-    input DRDPA1CSN;
-    input DRDPA2CSN;
-    input DRDPA3CSN;
-    input DRE;
-    input DRI1;
-    input DRI1CSN;
-    input DRI2;
-    input DRI2CSN;
-    input DRI3;
-    input DRI3CSN;
-    input DRI4;
-    input DRI5;
-    input DRI6;
-    output DRO1;
-    input DRO1CSN;
-    output DRO2;
-    input DRO2CSN;
-    output DRO3;
-    input DRO3CSN;
-    output DRO4;
-    output DRO5;
-    output DRO6;
-    input DRWDS;
-    input DRWEN;
-    input FA1;
-    input FA2;
-    input FA3;
-    input FA4;
-    input FA5;
-    input FA6;
-    input FCK1;
-    input FCK2;
-    input FDCK;
-    output FLD;
-    output FLG;
-    input FZ;
-    input LD1RN;
-    input LD2RN;
-    input LD3RN;
-    input LDSCK1;
-    input LDSCK2;
-    input LDSCK3;
-    input LE;
-    inout [41:0] LINK1;
-    inout [41:0] LINK10;
-    inout [41:0] LINK11;
-    inout [41:0] LINK12;
-    inout [41:0] LINK13;
-    inout [41:0] LINK14;
-    inout [41:0] LINK15;
-    inout [41:0] LINK16;
-    inout [41:0] LINK17;
-    inout [41:0] LINK18;
-    inout [41:0] LINK19;
-    inout [41:0] LINK2;
-    inout [41:0] LINK20;
-    inout [41:0] LINK21;
-    inout [41:0] LINK22;
-    inout [41:0] LINK23;
-    inout [41:0] LINK24;
-    inout [41:0] LINK25;
-    inout [41:0] LINK26;
-    inout [41:0] LINK27;
-    inout [41:0] LINK28;
-    inout [41:0] LINK29;
-    inout [41:0] LINK3;
-    inout [41:0] LINK30;
-    inout [41:0] LINK31;
-    inout [41:0] LINK32;
-    inout [41:0] LINK33;
-    inout [41:0] LINK34;
-    inout [41:0] LINK4;
-    inout [41:0] LINK5;
-    inout [41:0] LINK6;
-    inout [41:0] LINK7;
-    inout [41:0] LINK8;
-    inout [41:0] LINK9;
-    input SE;
-    input SWRX1CK;
-    input SWRX2CK;
-    parameter cal_delay1 = "";
-    parameter cal_delay2 = "";
-    parameter div1 = 3'b000;
-    parameter div2 = 3'b000;
-    parameter div3 = 3'b000;
-    parameter div_swrx1 = 3'b000;
-    parameter div_swrx2 = 3'b000;
-    parameter inv_ld_sck1 = 1'b0;
-    parameter inv_ld_sck2 = 1'b0;
-    parameter inv_ld_sck3 = 1'b0;
-    parameter link_ld_12 = 1'b0;
-    parameter link_ld_23 = 1'b0;
-    parameter location = "";
-    parameter mode_side1 = 0;
-    parameter mode_side2 = 0;
-    parameter mode_side3 = 0;
-    parameter sel_clk_out1 = 1'b0;
-    parameter sel_clk_out2 = 1'b0;
-    parameter sel_dc_clk = 2'b00;
-    parameter sel_ld_fck1 = 2'b00;
-    parameter sel_ld_fck2 = 2'b00;
-    parameter sel_ld_fck3 = 2'b00;
-    parameter sel_sw_fck1 = 2'b00;
-    parameter sel_sw_fck2 = 2'b00;
-    parameter use_dc = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_IOM_DRIVER(EI1, EI2, EI3, EI4, EI5, EL, ER, CI1, CI2, CI3, CI4, CI5, CL, CR, CTI, RI, RL, RR, CO, EO, RO1
-, RO2, RO3, RO4, RO5, CTO, LINK);
-    input CI1;
-    input CI2;
-    input CI3;
-    input CI4;
-    input CI5;
-    input CL;
-    output CO;
-    input CR;
-    input CTI;
-    output CTO;
-    input EI1;
-    input EI2;
-    input EI3;
-    input EI4;
-    input EI5;
-    input EL;
-    output EO;
-    input ER;
-    inout [41:0] LINK;
-    input RI;
-    input RL;
-    output RO1;
-    output RO2;
-    output RO3;
-    output RO4;
-    output RO5;
-    input RR;
-    parameter chained = 1'b0;
-    parameter cpath_edge = 1'b0;
-    parameter cpath_init = 1'b0;
-    parameter cpath_inv = 1'b0;
-    parameter cpath_load = 1'b0;
-    parameter cpath_mode = 4'b0000;
-    parameter cpath_sync = 1'b0;
-    parameter epath_dynamic = 1'b0;
-    parameter epath_edge = 1'b0;
-    parameter epath_init = 1'b0;
-    parameter epath_load = 1'b0;
-    parameter epath_mode = 4'b0000;
-    parameter epath_sync = 1'b0;
-    parameter location = "";
-    parameter rpath_dynamic = 1'b0;
-    parameter rpath_edge = 1'b0;
-    parameter rpath_init = 1'b0;
-    parameter rpath_load = 1'b0;
-    parameter rpath_mode = 4'b0000;
-    parameter rpath_sync = 1'b0;
-    parameter symbol = "";
-    parameter tpath_mode = 2'b00;
-    parameter variant = "";
-endmodule
-
-(* blackbox *)
-module NX_IOM_DRIVER_M(EI1, EI2, EI3, EI4, EI5, EL, ER, CI1, CI2, CI3, CI4, CI5, CL, CR, CTI, RI, RL, RR, CO, EO, RO1
-, RO2, RO3, RO4, RO5, CTO, LINK);
-    input CI1;
-    input CI2;
-    input CI3;
-    input CI4;
-    input CI5;
-    input CL;
-    output CO;
-    input CR;
-    input CTI;
-    output CTO;
-    input EI1;
-    input EI2;
-    input EI3;
-    input EI4;
-    input EI5;
-    input EL;
-    output EO;
-    input ER;
-    inout [41:0] LINK;
-    input RI;
-    input RL;
-    output RO1;
-    output RO2;
-    output RO3;
-    output RO4;
-    output RO5;
-    input RR;
-    parameter chained = 1'b0;
-    parameter cpath_edge = 1'b0;
-    parameter cpath_init = 1'b0;
-    parameter cpath_inv = 1'b0;
-    parameter cpath_load = 1'b0;
-    parameter cpath_mode = 4'b0000;
-    parameter cpath_sync = 1'b0;
-    parameter epath_dynamic = 1'b0;
-    parameter epath_edge = 1'b0;
-    parameter epath_init = 1'b0;
-    parameter epath_load = 1'b0;
-    parameter epath_mode = 4'b0000;
-    parameter epath_sync = 1'b0;
-    parameter location = "";
-    parameter rpath_dynamic = 1'b0;
-    parameter rpath_edge = 1'b0;
-    parameter rpath_init = 1'b0;
-    parameter rpath_load = 1'b0;
-    parameter rpath_mode = 4'b0000;
-    parameter rpath_sync = 1'b0;
-    parameter symbol = "";
-    parameter tpath_mode = 2'b00;
-    parameter variant = "";
-endmodule
-
-(* blackbox *)
-module NX_IOM_DRIVER_U(EI1, EI2, EI3, EI4, EI5, EI6, EI7, EI8, EL, ER, CI1, CL, CR, RI, RL, RR, CO, CTI, CTO, EO, RO1
-, RO2, RO3, RO4, RO5, RO6, RO7, RO8, LINK);
-    input CI1;
-    input CL;
-    output CO;
-    input CR;
-    input CTI;
-    output CTO;
-    input EI1;
-    input EI2;
-    input EI3;
-    input EI4;
-    input EI5;
-    input EI6;
-    input EI7;
-    input EI8;
-    input EL;
-    output EO;
-    input ER;
-    inout [41:0] LINK;
-    input RI;
-    input RL;
-    output RO1;
-    output RO2;
-    output RO3;
-    output RO4;
-    output RO5;
-    output RO6;
-    output RO7;
-    output RO8;
-    input RR;
-    parameter chained = 1'b0;
-    parameter cpath_edge = 1'b0;
-    parameter cpath_init = 1'b0;
-    parameter cpath_inv = 1'b0;
-    parameter cpath_load = 1'b0;
-    parameter cpath_mode = 4'b0000;
-    parameter cpath_sync = 1'b0;
-    parameter cpath_type = 1'b0;
-    parameter epath_dynamic = 1'b0;
-    parameter epath_edge = 1'b0;
-    parameter epath_init = 1'b0;
-    parameter epath_load = 1'b0;
-    parameter epath_mode = 4'b0000;
-    parameter epath_sync = 1'b0;
-    parameter epath_type = 1'b0;
-    parameter location = "";
-    parameter rpath_dynamic = 1'b0;
-    parameter rpath_edge = 1'b0;
-    parameter rpath_init = 1'b0;
-    parameter rpath_load = 1'b0;
-    parameter rpath_mode = 4'b0000;
-    parameter rpath_sync = 1'b0;
-    parameter rpath_type = 1'b0;
-    parameter symbol = "";
-    parameter tpath_mode = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_IOM_SERDES(RTCK, WRCK, WTCK, RRCK, TRST, RRST, CTCK, DCK, DRL, DIG, FZ, FLD, FLG, DS, DRA, DRI, DRO, DID, LINKN, LINKP);
-    input CTCK;
-    input DCK;
-    output [5:0] DID;
-    input DIG;
-    input [5:0] DRA;
-    input [5:0] DRI;
-    input DRL;
-    output [5:0] DRO;
-    input [1:0] DS;
-    output FLD;
-    output FLG;
-    input FZ;
-    inout [41:0] LINKN;
-    inout [41:0] LINKP;
-    input RRCK;
-    input RRST;
-    input RTCK;
-    input TRST;
-    input WRCK;
-    input WTCK;
-    parameter data_size = 5;
-    parameter location = "";
-endmodule
-
-(* blackbox *)
-module NX_IOM_SERDES_M(RTCK, WRCK, WTCK, RRCK, TRST, RRST, CTCK, DCK, DRL, DIG, FZ, FLD, FLG, DS, DRA, DRI, DRO, DID, LINKN, LINKP);
-    input CTCK;
-    input DCK;
-    output [5:0] DID;
-    input DIG;
-    input [5:0] DRA;
-    input [5:0] DRI;
-    input DRL;
-    output [5:0] DRO;
-    input [1:0] DS;
-    output FLD;
-    output FLG;
-    input FZ;
-    inout [41:0] LINKN;
-    inout [41:0] LINKP;
-    input RRCK;
-    input RRST;
-    input RTCK;
-    input TRST;
-    input WRCK;
-    input WTCK;
-    parameter data_size = 5;
-    parameter location = "";
-endmodule
-
-(* blackbox *)
-module NX_IOM_SERDES_U(FCK, SCK, LDRN, DRWDS, DRWEN, DRE, FZ, ALD, ALT, FLD, FLG, LINK, DRA, DRI, DRO, DID, DRIN, DRDN, FA, DRON);
-    output ALD;
-    output ALT;
-    output [5:0] DID;
-    input [3:0] DRA;
-    input [2:0] DRDN;
-    input DRE;
-    input [5:0] DRI;
-    input [2:0] DRIN;
-    output [5:0] DRO;
-    input [2:0] DRON;
-    input DRWDS;
-    input DRWEN;
-    input [5:0] FA;
-    input FCK;
-    output FLD;
-    output FLG;
-    input FZ;
-    input LDRN;
-    inout [41:0] LINK;
-    input SCK;
-    parameter data_size = 5;
-    parameter location = "";
-endmodule
-
 //(* blackbox *)
 //module NX_LUT(I1, I2, I3, I4, O);
 //    input I1;
diff --git a/techlibs/nanoxplore/cells_bb_l.v b/techlibs/nanoxplore/cells_bb_l.v
index 3ed9c1a89fb..376e524ce9f 100644
--- a/techlibs/nanoxplore/cells_bb_l.v
+++ b/techlibs/nanoxplore/cells_bb_l.v
@@ -2001,3 +2001,156 @@ module NX_RFB_L(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13
     parameter rck_edge = 1'b0;
     parameter wck_edge = 1'b0;
 endmodule
+
+(* blackbox *)
+module NX_IOM_CONTROL_L(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3
+, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3
+, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1
+, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3, DRO4
+, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16, LINK17, LINK18, LINK19
+, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);
+    output C1RED;
+    input C1RNE;
+    input C1RS;
+    input C1RW1;
+    input C1RW2;
+    input C1RW3;
+    input C1TS;
+    input C1TW;
+    output C2RED;
+    input C2RNE;
+    input C2RS;
+    input C2RW1;
+    input C2RW2;
+    input C2RW3;
+    input C2TS;
+    input C2TW;
+    input CAD1;
+    input CAD2;
+    input CAD3;
+    input CAD4;
+    input CAD5;
+    input CAD6;
+    output CAL;
+    input CAN1;
+    input CAN2;
+    input CAN3;
+    input CAN4;
+    input CAP1;
+    input CAP2;
+    input CAP3;
+    input CAP4;
+    input CAT1;
+    input CAT2;
+    input CAT3;
+    input CAT4;
+    input CCK;
+    output CKO1;
+    output CKO2;
+    input CTCK;
+    input DC;
+    input DCK;
+    input DIG;
+    input DIS;
+    input DOG;
+    input DOS;
+    input DPAG;
+    input DPAS;
+    input DQSG;
+    input DQSS;
+    input DRA1;
+    input DRA2;
+    input DRA3;
+    input DRA4;
+    input DRA5;
+    input DRA6;
+    input DRI1;
+    input DRI2;
+    input DRI3;
+    input DRI4;
+    input DRI5;
+    input DRI6;
+    input DRL;
+    output DRO1;
+    output DRO2;
+    output DRO3;
+    output DRO4;
+    output DRO5;
+    output DRO6;
+    input DS1;
+    input DS2;
+    input FA1;
+    input FA2;
+    input FA3;
+    input FA4;
+    input FA5;
+    input FA6;
+    output FLD;
+    output FLG;
+    input FZ;
+    inout [41:0] LINK1;
+    inout [41:0] LINK10;
+    inout [41:0] LINK11;
+    inout [41:0] LINK12;
+    inout [41:0] LINK13;
+    inout [41:0] LINK14;
+    inout [41:0] LINK15;
+    inout [41:0] LINK16;
+    inout [41:0] LINK17;
+    inout [41:0] LINK18;
+    inout [41:0] LINK19;
+    inout [41:0] LINK2;
+    inout [41:0] LINK20;
+    inout [41:0] LINK21;
+    inout [41:0] LINK22;
+    inout [41:0] LINK23;
+    inout [41:0] LINK24;
+    inout [41:0] LINK25;
+    inout [41:0] LINK26;
+    inout [41:0] LINK27;
+    inout [41:0] LINK28;
+    inout [41:0] LINK29;
+    inout [41:0] LINK3;
+    inout [41:0] LINK30;
+    inout [41:0] LINK31;
+    inout [41:0] LINK32;
+    inout [41:0] LINK33;
+    inout [41:0] LINK34;
+    inout [41:0] LINK4;
+    inout [41:0] LINK5;
+    inout [41:0] LINK6;
+    inout [41:0] LINK7;
+    inout [41:0] LINK8;
+    inout [41:0] LINK9;
+    input RRCK1;
+    input RRCK2;
+    input RTCK1;
+    input RTCK2;
+    input WRCK1;
+    input WRCK2;
+    input WTCK1;
+    input WTCK2;
+    parameter div_rx1 = 4'b0000;
+    parameter div_rx2 = 4'b0000;
+    parameter div_tx1 = 4'b0000;
+    parameter div_tx2 = 4'b0000;
+    parameter inv_di_fclk1 = 1'b0;
+    parameter inv_di_fclk2 = 1'b0;
+    parameter latency1 = 1'b0;
+    parameter latency2 = 1'b0;
+    parameter location = "";
+    parameter mode_cpath = "";
+    parameter mode_epath = "";
+    parameter mode_io_cal = 1'b0;
+    parameter mode_rpath = "";
+    parameter mode_side1 = 0;
+    parameter mode_side2 = 0;
+    parameter mode_tpath = "";
+    parameter sel_clk_out1 = 1'b0;
+    parameter sel_clk_out2 = 1'b0;
+    parameter sel_clkr_rx1 = 1'b0;
+    parameter sel_clkr_rx2 = 1'b0;
+    parameter sel_clkw_rx1 = 2'b00;
+    parameter sel_clkw_rx2 = 2'b00;
+endmodule
+
diff --git a/techlibs/nanoxplore/cells_bb_m.v b/techlibs/nanoxplore/cells_bb_m.v
index b3e94ac1597..d0497c49030 100644
--- a/techlibs/nanoxplore/cells_bb_m.v
+++ b/techlibs/nanoxplore/cells_bb_m.v
@@ -1288,3 +1288,240 @@ module NX_RFB_M(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13
     parameter wck_edge = 1'b0;
 endmodule
 
+
+(* blackbox *)
+module NX_IOM_CONTROL_M(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3
+, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3
+, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1
+, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1
+, DRO2, DRO3, DRO4, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16
+, LINK17, LINK18, LINK19, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);
+    output C1RED;
+    input C1RNE;
+    input C1RS;
+    input C1RW1;
+    input C1RW2;
+    input C1RW3;
+    input C1TS;
+    input C1TW;
+    output C2RED;
+    input C2RNE;
+    input C2RS;
+    input C2RW1;
+    input C2RW2;
+    input C2RW3;
+    input C2TS;
+    input C2TW;
+    input CAD1;
+    input CAD2;
+    input CAD3;
+    input CAD4;
+    input CAD5;
+    input CAD6;
+    output CAL;
+    input CAN1;
+    input CAN2;
+    input CAN3;
+    input CAN4;
+    input CAP1;
+    input CAP2;
+    input CAP3;
+    input CAP4;
+    input CAT1;
+    input CAT2;
+    input CAT3;
+    input CAT4;
+    input CCK;
+    output CKO1;
+    output CKO2;
+    input CTCK;
+    input DC;
+    input DCK;
+    input DIG;
+    input DIS;
+    input DOG;
+    input DOS;
+    input DPAG;
+    input DPAS;
+    input DQSG;
+    input DQSS;
+    input DRA1;
+    input DRA2;
+    input DRA3;
+    input DRA4;
+    input DRA5;
+    input DRA6;
+    input DRI1;
+    input DRI2;
+    input DRI3;
+    input DRI4;
+    input DRI5;
+    input DRI6;
+    input DRL;
+    output DRO1;
+    output DRO2;
+    output DRO3;
+    output DRO4;
+    output DRO5;
+    output DRO6;
+    input DS1;
+    input DS2;
+    input FA1;
+    input FA2;
+    input FA3;
+    input FA4;
+    input FA5;
+    input FA6;
+    output FLD;
+    output FLG;
+    input FZ;
+    inout [41:0] LINK1;
+    inout [41:0] LINK10;
+    inout [41:0] LINK11;
+    inout [41:0] LINK12;
+    inout [41:0] LINK13;
+    inout [41:0] LINK14;
+    inout [41:0] LINK15;
+    inout [41:0] LINK16;
+    inout [41:0] LINK17;
+    inout [41:0] LINK18;
+    inout [41:0] LINK19;
+    inout [41:0] LINK2;
+    inout [41:0] LINK20;
+    inout [41:0] LINK21;
+    inout [41:0] LINK22;
+    inout [41:0] LINK23;
+    inout [41:0] LINK24;
+    inout [41:0] LINK25;
+    inout [41:0] LINK26;
+    inout [41:0] LINK27;
+    inout [41:0] LINK28;
+    inout [41:0] LINK29;
+    inout [41:0] LINK3;
+    inout [41:0] LINK30;
+    inout [41:0] LINK31;
+    inout [41:0] LINK32;
+    inout [41:0] LINK33;
+    inout [41:0] LINK34;
+    inout [41:0] LINK4;
+    inout [41:0] LINK5;
+    inout [41:0] LINK6;
+    inout [41:0] LINK7;
+    inout [41:0] LINK8;
+    inout [41:0] LINK9;
+    input RRCK1;
+    input RRCK2;
+    input RTCK1;
+    input RTCK2;
+    input SPI1;
+    input SPI2;
+    input SPI3;
+    input WRCK1;
+    input WRCK2;
+    input WTCK1;
+    input WTCK2;
+    parameter div_rx1 = 4'b0000;
+    parameter div_rx2 = 4'b0000;
+    parameter div_tx1 = 4'b0000;
+    parameter div_tx2 = 4'b0000;
+    parameter inv_di_fclk1 = 1'b0;
+    parameter inv_di_fclk2 = 1'b0;
+    parameter latency1 = 1'b0;
+    parameter latency2 = 1'b0;
+    parameter location = "";
+    parameter mode_cpath = "";
+    parameter mode_epath = "";
+    parameter mode_io_cal = 1'b0;
+    parameter mode_rpath = "";
+    parameter mode_side1 = 0;
+    parameter mode_side2 = 0;
+    parameter mode_tpath = "";
+    parameter sel_clk_out1 = 1'b0;
+    parameter sel_clk_out2 = 1'b0;
+    parameter sel_clkr_rx1 = 1'b0;
+    parameter sel_clkr_rx2 = 1'b0;
+    parameter sel_clkw_rx1 = 2'b00;
+    parameter sel_clkw_rx2 = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_IOM_DRIVER_M(EI1, EI2, EI3, EI4, EI5, EL, ER, CI1, CI2, CI3, CI4, CI5, CL, CR, CTI, RI, RL, RR, CO, EO, RO1
+, RO2, RO3, RO4, RO5, CTO, LINK);
+    input CI1;
+    input CI2;
+    input CI3;
+    input CI4;
+    input CI5;
+    input CL;
+    output CO;
+    input CR;
+    input CTI;
+    output CTO;
+    input EI1;
+    input EI2;
+    input EI3;
+    input EI4;
+    input EI5;
+    input EL;
+    output EO;
+    input ER;
+    inout [41:0] LINK;
+    input RI;
+    input RL;
+    output RO1;
+    output RO2;
+    output RO3;
+    output RO4;
+    output RO5;
+    input RR;
+    parameter chained = 1'b0;
+    parameter cpath_edge = 1'b0;
+    parameter cpath_init = 1'b0;
+    parameter cpath_inv = 1'b0;
+    parameter cpath_load = 1'b0;
+    parameter cpath_mode = 4'b0000;
+    parameter cpath_sync = 1'b0;
+    parameter epath_dynamic = 1'b0;
+    parameter epath_edge = 1'b0;
+    parameter epath_init = 1'b0;
+    parameter epath_load = 1'b0;
+    parameter epath_mode = 4'b0000;
+    parameter epath_sync = 1'b0;
+    parameter location = "";
+    parameter rpath_dynamic = 1'b0;
+    parameter rpath_edge = 1'b0;
+    parameter rpath_init = 1'b0;
+    parameter rpath_load = 1'b0;
+    parameter rpath_mode = 4'b0000;
+    parameter rpath_sync = 1'b0;
+    parameter symbol = "";
+    parameter tpath_mode = 2'b00;
+    parameter variant = "";
+endmodule
+
+(* blackbox *)
+module NX_IOM_SERDES_M(RTCK, WRCK, WTCK, RRCK, TRST, RRST, CTCK, DCK, DRL, DIG, FZ, FLD, FLG, DS, DRA, DRI, DRO, DID, LINKN, LINKP);
+    input CTCK;
+    input DCK;
+    output [5:0] DID;
+    input DIG;
+    input [5:0] DRA;
+    input [5:0] DRI;
+    input DRL;
+    output [5:0] DRO;
+    input [1:0] DS;
+    output FLD;
+    output FLG;
+    input FZ;
+    inout [41:0] LINKN;
+    inout [41:0] LINKP;
+    input RRCK;
+    input RRST;
+    input RTCK;
+    input TRST;
+    input WRCK;
+    input WTCK;
+    parameter data_size = 5;
+    parameter location = "";
+endmodule
+
diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v
index 598eb8d2c9f..5c1e8bcb0dd 100644
--- a/techlibs/nanoxplore/cells_bb_u.v
+++ b/techlibs/nanoxplore/cells_bb_u.v
@@ -2578,3 +2578,364 @@ module NX_FIFO_U(RCK, WCK, WE, WEA, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11
     parameter use_write_arst = 1'b0;
     parameter wck_edge = 1'b0;
 endmodule
+
+
+(* blackbox *)
+module NX_IOM_CONTROL_U(ALCK1, ALCK2, ALCK3, LDSCK1, LDSCK2, LDSCK3, SWRX1CK, SWRX2CK, FCK1, FCK2, FDCK, CCK, DQ1CI1, DQ1CI2, DQ1CI3, DQ1CI4, DQ1CI5, DQ1CI6, DQ1CI7, DQ1CI8, DQ2CI1
+, DQ2CI2, DQ2CI3, DQ2CI4, DQ2CI5, DQ2CI6, DQ2CI7, DQ2CI8, DQ3CI1, DQ3CI2, DQ3CI3, DQ3CI4, DQ3CI5, DQ3CI6, DQ3CI7, DQ3CI8, DQS1CI1, DQS1CI2, DQS1CI3, DQS1CI4, DQS1CI5, DQS1CI6
+, DQS1CI7, DQS1CI8, DQS2CI1, DQS2CI2, DQS2CI3, DQS2CI4, DQS2CI5, DQS2CI6, DQS2CI7, DQS2CI8, DQS3CI1, DQS3CI2, DQS3CI3, DQS3CI4, DQS3CI5, DQS3CI6, DQS3CI7, DQS3CI8, LD1RN, LD2RN, LD3RN
+, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DCRN, LE, SE, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4, DRO1CSN
+, DRO2CSN, DRO3CSN, DRI1CSN, DRI2CSN, DRI3CSN, DRDPA1CSN, DRDPA2CSN, DRDPA3CSN, DRCCSN, DRWDS, DRWEN, DRE, CA1P1, CA1P2, CA1P3, CA1P4, CA2P1, CA2P2, CA2P3, CA2P4, CA1N1
+, CA1N2, CA1N3, CA1N4, CA2N1, CA2N2, CA2N3, CA2N4, CA1T1, CA1T2, CA1T3, CA1T4, CA2T1, CA2T2, CA2T3, CA2T4, CA1D1, CA1D2, CA1D3, CA1D4, CA1D5, CA1D6
+, CA2D1, CA2D2, CA2D3, CA2D4, CA2D5, CA2D6, CKO1, CKO2, FLD, FLG, AL1D, AL2D, AL3D, AL1T, AL2T, AL3T, DCL, DRO1, DRO2, DRO3, DRO4
+, DRO5, DRO6, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16, LINK17, LINK18, LINK19, LINK20
+, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);
+    output AL1D;
+    output AL1T;
+    output AL2D;
+    output AL2T;
+    output AL3D;
+    output AL3T;
+    input ALCK1;
+    input ALCK2;
+    input ALCK3;
+    input CA1D1;
+    input CA1D2;
+    input CA1D3;
+    input CA1D4;
+    input CA1D5;
+    input CA1D6;
+    input CA1N1;
+    input CA1N2;
+    input CA1N3;
+    input CA1N4;
+    input CA1P1;
+    input CA1P2;
+    input CA1P3;
+    input CA1P4;
+    input CA1T1;
+    input CA1T2;
+    input CA1T3;
+    input CA1T4;
+    input CA2D1;
+    input CA2D2;
+    input CA2D3;
+    input CA2D4;
+    input CA2D5;
+    input CA2D6;
+    input CA2N1;
+    input CA2N2;
+    input CA2N3;
+    input CA2N4;
+    input CA2P1;
+    input CA2P2;
+    input CA2P3;
+    input CA2P4;
+    input CA2T1;
+    input CA2T2;
+    input CA2T3;
+    input CA2T4;
+    input CCK;
+    output CKO1;
+    output CKO2;
+    output DCL;
+    input DCRN;
+    input DQ1CI1;
+    input DQ1CI2;
+    input DQ1CI3;
+    input DQ1CI4;
+    input DQ1CI5;
+    input DQ1CI6;
+    input DQ1CI7;
+    input DQ1CI8;
+    input DQ2CI1;
+    input DQ2CI2;
+    input DQ2CI3;
+    input DQ2CI4;
+    input DQ2CI5;
+    input DQ2CI6;
+    input DQ2CI7;
+    input DQ2CI8;
+    input DQ3CI1;
+    input DQ3CI2;
+    input DQ3CI3;
+    input DQ3CI4;
+    input DQ3CI5;
+    input DQ3CI6;
+    input DQ3CI7;
+    input DQ3CI8;
+    input DQS1CI1;
+    input DQS1CI2;
+    input DQS1CI3;
+    input DQS1CI4;
+    input DQS1CI5;
+    input DQS1CI6;
+    input DQS1CI7;
+    input DQS1CI8;
+    input DQS2CI1;
+    input DQS2CI2;
+    input DQS2CI3;
+    input DQS2CI4;
+    input DQS2CI5;
+    input DQS2CI6;
+    input DQS2CI7;
+    input DQS2CI8;
+    input DQS3CI1;
+    input DQS3CI2;
+    input DQS3CI3;
+    input DQS3CI4;
+    input DQS3CI5;
+    input DQS3CI6;
+    input DQS3CI7;
+    input DQS3CI8;
+    input DRA1;
+    input DRA2;
+    input DRA3;
+    input DRA4;
+    input DRCCSN;
+    input DRDPA1CSN;
+    input DRDPA2CSN;
+    input DRDPA3CSN;
+    input DRE;
+    input DRI1;
+    input DRI1CSN;
+    input DRI2;
+    input DRI2CSN;
+    input DRI3;
+    input DRI3CSN;
+    input DRI4;
+    input DRI5;
+    input DRI6;
+    output DRO1;
+    input DRO1CSN;
+    output DRO2;
+    input DRO2CSN;
+    output DRO3;
+    input DRO3CSN;
+    output DRO4;
+    output DRO5;
+    output DRO6;
+    input DRWDS;
+    input DRWEN;
+    input FA1;
+    input FA2;
+    input FA3;
+    input FA4;
+    input FA5;
+    input FA6;
+    input FCK1;
+    input FCK2;
+    input FDCK;
+    output FLD;
+    output FLG;
+    input FZ;
+    input LD1RN;
+    input LD2RN;
+    input LD3RN;
+    input LDSCK1;
+    input LDSCK2;
+    input LDSCK3;
+    input LE;
+    inout [41:0] LINK1;
+    inout [41:0] LINK10;
+    inout [41:0] LINK11;
+    inout [41:0] LINK12;
+    inout [41:0] LINK13;
+    inout [41:0] LINK14;
+    inout [41:0] LINK15;
+    inout [41:0] LINK16;
+    inout [41:0] LINK17;
+    inout [41:0] LINK18;
+    inout [41:0] LINK19;
+    inout [41:0] LINK2;
+    inout [41:0] LINK20;
+    inout [41:0] LINK21;
+    inout [41:0] LINK22;
+    inout [41:0] LINK23;
+    inout [41:0] LINK24;
+    inout [41:0] LINK25;
+    inout [41:0] LINK26;
+    inout [41:0] LINK27;
+    inout [41:0] LINK28;
+    inout [41:0] LINK29;
+    inout [41:0] LINK3;
+    inout [41:0] LINK30;
+    inout [41:0] LINK31;
+    inout [41:0] LINK32;
+    inout [41:0] LINK33;
+    inout [41:0] LINK34;
+    inout [41:0] LINK4;
+    inout [41:0] LINK5;
+    inout [41:0] LINK6;
+    inout [41:0] LINK7;
+    inout [41:0] LINK8;
+    inout [41:0] LINK9;
+    input SE;
+    input SWRX1CK;
+    input SWRX2CK;
+    parameter cal_delay1 = "";
+    parameter cal_delay2 = "";
+    parameter div1 = 3'b000;
+    parameter div2 = 3'b000;
+    parameter div3 = 3'b000;
+    parameter div_swrx1 = 3'b000;
+    parameter div_swrx2 = 3'b000;
+    parameter inv_ld_sck1 = 1'b0;
+    parameter inv_ld_sck2 = 1'b0;
+    parameter inv_ld_sck3 = 1'b0;
+    parameter link_ld_12 = 1'b0;
+    parameter link_ld_23 = 1'b0;
+    parameter location = "";
+    parameter mode_side1 = 0;
+    parameter mode_side2 = 0;
+    parameter mode_side3 = 0;
+    parameter sel_clk_out1 = 1'b0;
+    parameter sel_clk_out2 = 1'b0;
+    parameter sel_dc_clk = 2'b00;
+    parameter sel_ld_fck1 = 2'b00;
+    parameter sel_ld_fck2 = 2'b00;
+    parameter sel_ld_fck3 = 2'b00;
+    parameter sel_sw_fck1 = 2'b00;
+    parameter sel_sw_fck2 = 2'b00;
+    parameter use_dc = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_IOM_DRIVER_M(EI1, EI2, EI3, EI4, EI5, EL, ER, CI1, CI2, CI3, CI4, CI5, CL, CR, CTI, RI, RL, RR, CO, EO, RO1
+, RO2, RO3, RO4, RO5, CTO, LINK);
+    input CI1;
+    input CI2;
+    input CI3;
+    input CI4;
+    input CI5;
+    input CL;
+    output CO;
+    input CR;
+    input CTI;
+    output CTO;
+    input EI1;
+    input EI2;
+    input EI3;
+    input EI4;
+    input EI5;
+    input EL;
+    output EO;
+    input ER;
+    inout [41:0] LINK;
+    input RI;
+    input RL;
+    output RO1;
+    output RO2;
+    output RO3;
+    output RO4;
+    output RO5;
+    input RR;
+    parameter chained = 1'b0;
+    parameter cpath_edge = 1'b0;
+    parameter cpath_init = 1'b0;
+    parameter cpath_inv = 1'b0;
+    parameter cpath_load = 1'b0;
+    parameter cpath_mode = 4'b0000;
+    parameter cpath_sync = 1'b0;
+    parameter epath_dynamic = 1'b0;
+    parameter epath_edge = 1'b0;
+    parameter epath_init = 1'b0;
+    parameter epath_load = 1'b0;
+    parameter epath_mode = 4'b0000;
+    parameter epath_sync = 1'b0;
+    parameter location = "";
+    parameter rpath_dynamic = 1'b0;
+    parameter rpath_edge = 1'b0;
+    parameter rpath_init = 1'b0;
+    parameter rpath_load = 1'b0;
+    parameter rpath_mode = 4'b0000;
+    parameter rpath_sync = 1'b0;
+    parameter symbol = "";
+    parameter tpath_mode = 2'b00;
+    parameter variant = "";
+endmodule
+
+(* blackbox *)
+module NX_IOM_DRIVER_U(EI1, EI2, EI3, EI4, EI5, EI6, EI7, EI8, EL, ER, CI1, CL, CR, RI, RL, RR, CO, CTI, CTO, EO, RO1
+, RO2, RO3, RO4, RO5, RO6, RO7, RO8, LINK);
+    input CI1;
+    input CL;
+    output CO;
+    input CR;
+    input CTI;
+    output CTO;
+    input EI1;
+    input EI2;
+    input EI3;
+    input EI4;
+    input EI5;
+    input EI6;
+    input EI7;
+    input EI8;
+    input EL;
+    output EO;
+    input ER;
+    inout [41:0] LINK;
+    input RI;
+    input RL;
+    output RO1;
+    output RO2;
+    output RO3;
+    output RO4;
+    output RO5;
+    output RO6;
+    output RO7;
+    output RO8;
+    input RR;
+    parameter chained = 1'b0;
+    parameter cpath_edge = 1'b0;
+    parameter cpath_init = 1'b0;
+    parameter cpath_inv = 1'b0;
+    parameter cpath_load = 1'b0;
+    parameter cpath_mode = 4'b0000;
+    parameter cpath_sync = 1'b0;
+    parameter cpath_type = 1'b0;
+    parameter epath_dynamic = 1'b0;
+    parameter epath_edge = 1'b0;
+    parameter epath_init = 1'b0;
+    parameter epath_load = 1'b0;
+    parameter epath_mode = 4'b0000;
+    parameter epath_sync = 1'b0;
+    parameter epath_type = 1'b0;
+    parameter location = "";
+    parameter rpath_dynamic = 1'b0;
+    parameter rpath_edge = 1'b0;
+    parameter rpath_init = 1'b0;
+    parameter rpath_load = 1'b0;
+    parameter rpath_mode = 4'b0000;
+    parameter rpath_sync = 1'b0;
+    parameter rpath_type = 1'b0;
+    parameter symbol = "";
+    parameter tpath_mode = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_IOM_SERDES_U(FCK, SCK, LDRN, DRWDS, DRWEN, DRE, FZ, ALD, ALT, FLD, FLG, LINK, DRA, DRI, DRO, DID, DRIN, DRDN, FA, DRON);
+    output ALD;
+    output ALT;
+    output [5:0] DID;
+    input [3:0] DRA;
+    input [2:0] DRDN;
+    input DRE;
+    input [5:0] DRI;
+    input [2:0] DRIN;
+    output [5:0] DRO;
+    input [2:0] DRON;
+    input DRWDS;
+    input DRWEN;
+    input [5:0] FA;
+    input FCK;
+    output FLD;
+    output FLG;
+    input FZ;
+    input LDRN;
+    inout [41:0] LINK;
+    input SCK;
+    parameter data_size = 5;
+    parameter location = "";
+endmodule
diff --git a/techlibs/nanoxplore/cells_wrap_l.v b/techlibs/nanoxplore/cells_wrap_l.v
index d86b4518ba9..5bfdd4d1345 100644
--- a/techlibs/nanoxplore/cells_wrap_l.v
+++ b/techlibs/nanoxplore/cells_wrap_l.v
@@ -1401,7 +1401,7 @@ module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13,
   );
 endmodule
 
-// TODO
+//TODO
 module SMUL24x32_2DSP_ACC_2DSP_L(clk, rst, we, A, B, Z);
     input [23:0] A;
     input [31:0] B;
@@ -1411,3 +1411,303 @@ module SMUL24x32_2DSP_ACC_2DSP_L(clk, rst, we, A, B, Z);
     input we;
 endmodule
 
+//TODO
+module NX_HSSL_L_FULL(hssl_clk_user_i, hssl_clk_ref_i, hssl_clock_o, usr_com_tx_pma_pre_sign_i, usr_com_tx_pma_pre_en_i, usr_com_tx_pma_main_sign_i, usr_com_rx_pma_m_eye_i, usr_com_tx_pma_post_sign_i, usr_pll_pma_rst_n_i, usr_main_rst_n_i, usr_calibrate_pma_en_i, usr_pcs_ctrl_pll_lock_en_i, usr_pcs_ctrl_ovs_en_i, usr_pll_lock_o, usr_calibrate_pma_out_o, pma_clk_ext_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i, usr_tx0_pma_clk_en_i, usr_tx0_busy_o, pma_tx0_o
+, usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_ctrl_el_buff_fifo_en_i, usr_rx0_rst_n_i, usr_rx0_pma_cdr_rst_i, usr_rx0_pma_ckgen_rst_n_i, usr_rx0_pma_pll_rst_n_i, usr_rx0_pma_loss_of_signal_o, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_busy_o, usr_rx0_pll_lock_o, pma_rx0_i, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_pma_clk_en_i, usr_tx1_busy_o, pma_tx1_o
+, usr_rx1_ctrl_dscr_en_i, usr_rx1_ctrl_dec_en_i, usr_rx1_ctrl_align_en_i, usr_rx1_ctrl_align_sync_i, usr_rx1_ctrl_replace_en_i, usr_rx1_ctrl_el_buff_rst_i, usr_rx1_ctrl_el_buff_fifo_en_i, usr_rx1_rst_n_i, usr_rx1_pma_cdr_rst_i, usr_rx1_pma_ckgen_rst_n_i, usr_rx1_pma_pll_rst_n_i, usr_rx1_pma_loss_of_signal_o, usr_rx1_ctrl_char_is_aligned_o, usr_rx1_busy_o, usr_rx1_pll_lock_o, pma_rx1_i, usr_tx2_ctrl_replace_en_i, usr_tx2_rst_n_i, usr_tx2_pma_clk_en_i, usr_tx2_busy_o, pma_tx2_o
+, usr_rx2_ctrl_dscr_en_i, usr_rx2_ctrl_dec_en_i, usr_rx2_ctrl_align_en_i, usr_rx2_ctrl_align_sync_i, usr_rx2_ctrl_replace_en_i, usr_rx2_ctrl_el_buff_rst_i, usr_rx2_ctrl_el_buff_fifo_en_i, usr_rx2_rst_n_i, usr_rx2_pma_cdr_rst_i, usr_rx2_pma_ckgen_rst_n_i, usr_rx2_pma_pll_rst_n_i, usr_rx2_pma_loss_of_signal_o, usr_rx2_ctrl_char_is_aligned_o, usr_rx2_busy_o, usr_rx2_pll_lock_o, pma_rx2_i, usr_tx3_ctrl_replace_en_i, usr_tx3_rst_n_i, usr_tx3_pma_clk_en_i, usr_tx3_busy_o, pma_tx3_o
+, usr_rx3_ctrl_dscr_en_i, usr_rx3_ctrl_dec_en_i, usr_rx3_ctrl_align_en_i, usr_rx3_ctrl_align_sync_i, usr_rx3_ctrl_replace_en_i, usr_rx3_ctrl_el_buff_rst_i, usr_rx3_ctrl_el_buff_fifo_en_i, usr_rx3_rst_n_i, usr_rx3_pma_cdr_rst_i, usr_rx3_pma_ckgen_rst_n_i, usr_rx3_pma_pll_rst_n_i, usr_rx3_pma_loss_of_signal_o, usr_rx3_ctrl_char_is_aligned_o, usr_rx3_busy_o, usr_rx3_pll_lock_o, pma_rx3_i, usr_tx4_ctrl_replace_en_i, usr_tx4_rst_n_i, usr_tx4_pma_clk_en_i, usr_tx4_busy_o, pma_tx4_o
+, usr_rx4_ctrl_dscr_en_i, usr_rx4_ctrl_dec_en_i, usr_rx4_ctrl_align_en_i, usr_rx4_ctrl_align_sync_i, usr_rx4_ctrl_replace_en_i, usr_rx4_ctrl_el_buff_rst_i, usr_rx4_ctrl_el_buff_fifo_en_i, usr_rx4_rst_n_i, usr_rx4_pma_cdr_rst_i, usr_rx4_pma_ckgen_rst_n_i, usr_rx4_pma_pll_rst_n_i, usr_rx4_pma_loss_of_signal_o, usr_rx4_ctrl_char_is_aligned_o, usr_rx4_busy_o, usr_rx4_pll_lock_o, pma_rx4_i, usr_tx5_ctrl_replace_en_i, usr_tx5_rst_n_i, usr_tx5_pma_clk_en_i, usr_tx5_busy_o, pma_tx5_o
+, usr_rx5_ctrl_dscr_en_i, usr_rx5_ctrl_dec_en_i, usr_rx5_ctrl_align_en_i, usr_rx5_ctrl_align_sync_i, usr_rx5_ctrl_replace_en_i, usr_rx5_ctrl_el_buff_rst_i, usr_rx5_ctrl_el_buff_fifo_en_i, usr_rx5_rst_n_i, usr_rx5_pma_cdr_rst_i, usr_rx5_pma_ckgen_rst_n_i, usr_rx5_pma_pll_rst_n_i, usr_rx5_pma_loss_of_signal_o, usr_rx5_ctrl_char_is_aligned_o, usr_rx5_busy_o, usr_rx5_pll_lock_o, pma_rx5_i, usr_com_tx_pma_main_en_i, usr_com_tx_pma_margin_sel_i, usr_com_tx_pma_margin_input_sel_i, usr_com_tx_pma_margin_sel_var_i, usr_com_tx_pma_margin_input_sel_var_i
+, usr_com_tx_pma_post_en_i, usr_com_tx_pma_post_input_sel_i, usr_com_tx_pma_post_input_sel_var_i, usr_com_rx_pma_ctle_cap_i, usr_com_rx_pma_ctle_resp_i, usr_com_rx_pma_ctle_resn_i, usr_com_ctrl_tx_sel_i, usr_com_ctrl_rx_sel_i, usr_calibrate_pma_res_p1_i, usr_calibrate_pma_res_n2_i, usr_calibrate_pma_res_n3_i, usr_calibrate_pma_res_p4_i, usr_calibrate_pma_sel_i, usr_main_test_i, usr_main_test_o, usr_tx0_ctrl_enc_en_i, usr_tx0_ctrl_char_is_k_i, usr_tx0_ctrl_scr_en_i, usr_tx0_ctrl_end_of_multiframe_i, usr_tx0_ctrl_end_of_frame_i, usr_tx0_test_i
+, usr_tx0_data_i, usr_tx0_test_o, usr_rx0_data_o, usr_rx0_ctrl_ovs_bit_sel_i, usr_rx0_test_i, usr_rx0_ctrl_char_is_comma_o, usr_rx0_ctrl_char_is_k_o, usr_rx0_ctrl_not_in_table_o, usr_rx0_ctrl_disp_err_o, usr_rx0_ctrl_char_is_a_o, usr_rx0_ctrl_char_is_f_o, usr_rx0_test_o, usr_tx1_ctrl_enc_en_i, usr_tx1_ctrl_char_is_k_i, usr_tx1_ctrl_scr_en_i, usr_tx1_ctrl_end_of_multiframe_i, usr_tx1_ctrl_end_of_frame_i, usr_tx1_test_i, usr_tx1_data_i, usr_tx1_test_o, usr_rx1_data_o
+, usr_rx1_ctrl_ovs_bit_sel_i, usr_rx1_test_i, usr_rx1_ctrl_char_is_comma_o, usr_rx1_ctrl_char_is_k_o, usr_rx1_ctrl_not_in_table_o, usr_rx1_ctrl_disp_err_o, usr_rx1_ctrl_char_is_a_o, usr_rx1_ctrl_char_is_f_o, usr_rx1_test_o, usr_tx2_ctrl_enc_en_i, usr_tx2_ctrl_char_is_k_i, usr_tx2_ctrl_scr_en_i, usr_tx2_ctrl_end_of_multiframe_i, usr_tx2_ctrl_end_of_frame_i, usr_tx2_test_i, usr_tx2_data_i, usr_tx2_test_o, usr_rx2_data_o, usr_rx2_ctrl_ovs_bit_sel_i, usr_rx2_test_i, usr_rx2_ctrl_char_is_comma_o
+, usr_rx2_ctrl_char_is_k_o, usr_rx2_ctrl_not_in_table_o, usr_rx2_ctrl_disp_err_o, usr_rx2_ctrl_char_is_a_o, usr_rx2_ctrl_char_is_f_o, usr_rx2_test_o, usr_tx3_ctrl_enc_en_i, usr_tx3_ctrl_char_is_k_i, usr_tx3_ctrl_scr_en_i, usr_tx3_ctrl_end_of_multiframe_i, usr_tx3_ctrl_end_of_frame_i, usr_tx3_test_i, usr_tx3_data_i, usr_tx3_test_o, usr_rx3_data_o, usr_rx3_ctrl_ovs_bit_sel_i, usr_rx3_test_i, usr_rx3_ctrl_char_is_comma_o, usr_rx3_ctrl_char_is_k_o, usr_rx3_ctrl_not_in_table_o, usr_rx3_ctrl_disp_err_o
+, usr_rx3_ctrl_char_is_a_o, usr_rx3_ctrl_char_is_f_o, usr_rx3_test_o, usr_tx4_ctrl_enc_en_i, usr_tx4_ctrl_char_is_k_i, usr_tx4_ctrl_scr_en_i, usr_tx4_ctrl_end_of_multiframe_i, usr_tx4_ctrl_end_of_frame_i, usr_tx4_test_i, usr_tx4_data_i, usr_tx4_test_o, usr_rx4_data_o, usr_rx4_ctrl_ovs_bit_sel_i, usr_rx4_test_i, usr_rx4_ctrl_char_is_comma_o, usr_rx4_ctrl_char_is_k_o, usr_rx4_ctrl_not_in_table_o, usr_rx4_ctrl_disp_err_o, usr_rx4_ctrl_char_is_a_o, usr_rx4_ctrl_char_is_f_o, usr_rx4_test_o
+, usr_tx5_ctrl_enc_en_i, usr_tx5_ctrl_char_is_k_i, usr_tx5_ctrl_scr_en_i, usr_tx5_ctrl_end_of_multiframe_i, usr_tx5_ctrl_end_of_frame_i, usr_tx5_test_i, usr_tx5_data_i, usr_tx5_test_o, usr_rx5_data_o, usr_rx5_ctrl_ovs_bit_sel_i, usr_rx5_test_i, usr_rx5_ctrl_char_is_comma_o, usr_rx5_ctrl_char_is_k_o, usr_rx5_ctrl_not_in_table_o, usr_rx5_ctrl_disp_err_o, usr_rx5_ctrl_char_is_a_o, usr_rx5_ctrl_char_is_f_o, usr_rx5_test_o, usr_com_tx_pma_pre_input_sel_i);
+    input hssl_clk_ref_i;
+    input hssl_clk_user_i;
+    output hssl_clock_o;
+    input pma_clk_ext_i;
+    input pma_rx0_i;
+    input pma_rx1_i;
+    input pma_rx2_i;
+    input pma_rx3_i;
+    input pma_rx4_i;
+    input pma_rx5_i;
+    output pma_tx0_o;
+    output pma_tx1_o;
+    output pma_tx2_o;
+    output pma_tx3_o;
+    output pma_tx4_o;
+    output pma_tx5_o;
+    input usr_calibrate_pma_en_i;
+    output usr_calibrate_pma_out_o;
+    input [7:0] usr_calibrate_pma_res_n2_i;
+    input [7:0] usr_calibrate_pma_res_n3_i;
+    input [7:0] usr_calibrate_pma_res_p1_i;
+    input [7:0] usr_calibrate_pma_res_p4_i;
+    input [3:0] usr_calibrate_pma_sel_i;
+    input [5:0] usr_com_ctrl_rx_sel_i;
+    input [5:0] usr_com_ctrl_tx_sel_i;
+    input [3:0] usr_com_rx_pma_ctle_cap_i;
+    input [3:0] usr_com_rx_pma_ctle_resn_i;
+    input [3:0] usr_com_rx_pma_ctle_resp_i;
+    input usr_com_rx_pma_m_eye_i;
+    input [5:0] usr_com_tx_pma_main_en_i;
+    input usr_com_tx_pma_main_sign_i;
+    input [3:0] usr_com_tx_pma_margin_input_sel_i;
+    input [4:0] usr_com_tx_pma_margin_input_sel_var_i;
+    input [3:0] usr_com_tx_pma_margin_sel_i;
+    input [4:0] usr_com_tx_pma_margin_sel_var_i;
+    input [4:0] usr_com_tx_pma_post_en_i;
+    input [3:0] usr_com_tx_pma_post_input_sel_i;
+    input [3:0] usr_com_tx_pma_post_input_sel_var_i;
+    input usr_com_tx_pma_post_sign_i;
+    input usr_com_tx_pma_pre_en_i;
+    input [3:0] usr_com_tx_pma_pre_input_sel_i;
+    input usr_com_tx_pma_pre_sign_i;
+    input usr_main_rst_n_i;
+    input [7:0] usr_main_test_i;
+    output [7:0] usr_main_test_o;
+    input usr_pcs_ctrl_ovs_en_i;
+    input usr_pcs_ctrl_pll_lock_en_i;
+    output usr_pll_lock_o;
+    input usr_pll_pma_rst_n_i;
+    output usr_rx0_busy_o;
+    input usr_rx0_ctrl_align_en_i;
+    input usr_rx0_ctrl_align_sync_i;
+    output [7:0] usr_rx0_ctrl_char_is_a_o;
+    output usr_rx0_ctrl_char_is_aligned_o;
+    output [7:0] usr_rx0_ctrl_char_is_comma_o;
+    output [7:0] usr_rx0_ctrl_char_is_f_o;
+    output [7:0] usr_rx0_ctrl_char_is_k_o;
+    input usr_rx0_ctrl_dec_en_i;
+    output [7:0] usr_rx0_ctrl_disp_err_o;
+    input usr_rx0_ctrl_dscr_en_i;
+    input usr_rx0_ctrl_el_buff_fifo_en_i;
+    input usr_rx0_ctrl_el_buff_rst_i;
+    output [7:0] usr_rx0_ctrl_not_in_table_o;
+    input [1:0] usr_rx0_ctrl_ovs_bit_sel_i;
+    input usr_rx0_ctrl_replace_en_i;
+    output [63:0] usr_rx0_data_o;
+    output usr_rx0_pll_lock_o;
+    input usr_rx0_pma_cdr_rst_i;
+    input usr_rx0_pma_ckgen_rst_n_i;
+    output usr_rx0_pma_loss_of_signal_o;
+    input usr_rx0_pma_pll_rst_n_i;
+    input usr_rx0_rst_n_i;
+    input [3:0] usr_rx0_test_i;
+    output [7:0] usr_rx0_test_o;
+    output usr_rx1_busy_o;
+    input usr_rx1_ctrl_align_en_i;
+    input usr_rx1_ctrl_align_sync_i;
+    output [7:0] usr_rx1_ctrl_char_is_a_o;
+    output usr_rx1_ctrl_char_is_aligned_o;
+    output [7:0] usr_rx1_ctrl_char_is_comma_o;
+    output [7:0] usr_rx1_ctrl_char_is_f_o;
+    output [7:0] usr_rx1_ctrl_char_is_k_o;
+    input usr_rx1_ctrl_dec_en_i;
+    output [7:0] usr_rx1_ctrl_disp_err_o;
+    input usr_rx1_ctrl_dscr_en_i;
+    input usr_rx1_ctrl_el_buff_fifo_en_i;
+    input usr_rx1_ctrl_el_buff_rst_i;
+    output [7:0] usr_rx1_ctrl_not_in_table_o;
+    input [1:0] usr_rx1_ctrl_ovs_bit_sel_i;
+    input usr_rx1_ctrl_replace_en_i;
+    output [63:0] usr_rx1_data_o;
+    output usr_rx1_pll_lock_o;
+    input usr_rx1_pma_cdr_rst_i;
+    input usr_rx1_pma_ckgen_rst_n_i;
+    output usr_rx1_pma_loss_of_signal_o;
+    input usr_rx1_pma_pll_rst_n_i;
+    input usr_rx1_rst_n_i;
+    input [3:0] usr_rx1_test_i;
+    output [7:0] usr_rx1_test_o;
+    output usr_rx2_busy_o;
+    input usr_rx2_ctrl_align_en_i;
+    input usr_rx2_ctrl_align_sync_i;
+    output [7:0] usr_rx2_ctrl_char_is_a_o;
+    output usr_rx2_ctrl_char_is_aligned_o;
+    output [7:0] usr_rx2_ctrl_char_is_comma_o;
+    output [7:0] usr_rx2_ctrl_char_is_f_o;
+    output [7:0] usr_rx2_ctrl_char_is_k_o;
+    input usr_rx2_ctrl_dec_en_i;
+    output [7:0] usr_rx2_ctrl_disp_err_o;
+    input usr_rx2_ctrl_dscr_en_i;
+    input usr_rx2_ctrl_el_buff_fifo_en_i;
+    input usr_rx2_ctrl_el_buff_rst_i;
+    output [7:0] usr_rx2_ctrl_not_in_table_o;
+    input [1:0] usr_rx2_ctrl_ovs_bit_sel_i;
+    input usr_rx2_ctrl_replace_en_i;
+    output [63:0] usr_rx2_data_o;
+    output usr_rx2_pll_lock_o;
+    input usr_rx2_pma_cdr_rst_i;
+    input usr_rx2_pma_ckgen_rst_n_i;
+    output usr_rx2_pma_loss_of_signal_o;
+    input usr_rx2_pma_pll_rst_n_i;
+    input usr_rx2_rst_n_i;
+    input [3:0] usr_rx2_test_i;
+    output [7:0] usr_rx2_test_o;
+    output usr_rx3_busy_o;
+    input usr_rx3_ctrl_align_en_i;
+    input usr_rx3_ctrl_align_sync_i;
+    output [7:0] usr_rx3_ctrl_char_is_a_o;
+    output usr_rx3_ctrl_char_is_aligned_o;
+    output [7:0] usr_rx3_ctrl_char_is_comma_o;
+    output [7:0] usr_rx3_ctrl_char_is_f_o;
+    output [7:0] usr_rx3_ctrl_char_is_k_o;
+    input usr_rx3_ctrl_dec_en_i;
+    output [7:0] usr_rx3_ctrl_disp_err_o;
+    input usr_rx3_ctrl_dscr_en_i;
+    input usr_rx3_ctrl_el_buff_fifo_en_i;
+    input usr_rx3_ctrl_el_buff_rst_i;
+    output [7:0] usr_rx3_ctrl_not_in_table_o;
+    input [1:0] usr_rx3_ctrl_ovs_bit_sel_i;
+    input usr_rx3_ctrl_replace_en_i;
+    output [63:0] usr_rx3_data_o;
+    output usr_rx3_pll_lock_o;
+    input usr_rx3_pma_cdr_rst_i;
+    input usr_rx3_pma_ckgen_rst_n_i;
+    output usr_rx3_pma_loss_of_signal_o;
+    input usr_rx3_pma_pll_rst_n_i;
+    input usr_rx3_rst_n_i;
+    input [3:0] usr_rx3_test_i;
+    output [7:0] usr_rx3_test_o;
+    output usr_rx4_busy_o;
+    input usr_rx4_ctrl_align_en_i;
+    input usr_rx4_ctrl_align_sync_i;
+    output [7:0] usr_rx4_ctrl_char_is_a_o;
+    output usr_rx4_ctrl_char_is_aligned_o;
+    output [7:0] usr_rx4_ctrl_char_is_comma_o;
+    output [7:0] usr_rx4_ctrl_char_is_f_o;
+    output [7:0] usr_rx4_ctrl_char_is_k_o;
+    input usr_rx4_ctrl_dec_en_i;
+    output [7:0] usr_rx4_ctrl_disp_err_o;
+    input usr_rx4_ctrl_dscr_en_i;
+    input usr_rx4_ctrl_el_buff_fifo_en_i;
+    input usr_rx4_ctrl_el_buff_rst_i;
+    output [7:0] usr_rx4_ctrl_not_in_table_o;
+    input [1:0] usr_rx4_ctrl_ovs_bit_sel_i;
+    input usr_rx4_ctrl_replace_en_i;
+    output [63:0] usr_rx4_data_o;
+    output usr_rx4_pll_lock_o;
+    input usr_rx4_pma_cdr_rst_i;
+    input usr_rx4_pma_ckgen_rst_n_i;
+    output usr_rx4_pma_loss_of_signal_o;
+    input usr_rx4_pma_pll_rst_n_i;
+    input usr_rx4_rst_n_i;
+    input [3:0] usr_rx4_test_i;
+    output [7:0] usr_rx4_test_o;
+    output usr_rx5_busy_o;
+    input usr_rx5_ctrl_align_en_i;
+    input usr_rx5_ctrl_align_sync_i;
+    output [7:0] usr_rx5_ctrl_char_is_a_o;
+    output usr_rx5_ctrl_char_is_aligned_o;
+    output [7:0] usr_rx5_ctrl_char_is_comma_o;
+    output [7:0] usr_rx5_ctrl_char_is_f_o;
+    output [7:0] usr_rx5_ctrl_char_is_k_o;
+    input usr_rx5_ctrl_dec_en_i;
+    output [7:0] usr_rx5_ctrl_disp_err_o;
+    input usr_rx5_ctrl_dscr_en_i;
+    input usr_rx5_ctrl_el_buff_fifo_en_i;
+    input usr_rx5_ctrl_el_buff_rst_i;
+    output [7:0] usr_rx5_ctrl_not_in_table_o;
+    input [1:0] usr_rx5_ctrl_ovs_bit_sel_i;
+    input usr_rx5_ctrl_replace_en_i;
+    output [63:0] usr_rx5_data_o;
+    output usr_rx5_pll_lock_o;
+    input usr_rx5_pma_cdr_rst_i;
+    input usr_rx5_pma_ckgen_rst_n_i;
+    output usr_rx5_pma_loss_of_signal_o;
+    input usr_rx5_pma_pll_rst_n_i;
+    input usr_rx5_rst_n_i;
+    input [3:0] usr_rx5_test_i;
+    output [7:0] usr_rx5_test_o;
+    output usr_tx0_busy_o;
+    input [7:0] usr_tx0_ctrl_char_is_k_i;
+    input [7:0] usr_tx0_ctrl_enc_en_i;
+    input [7:0] usr_tx0_ctrl_end_of_frame_i;
+    input [7:0] usr_tx0_ctrl_end_of_multiframe_i;
+    input usr_tx0_ctrl_replace_en_i;
+    input [7:0] usr_tx0_ctrl_scr_en_i;
+    input [63:0] usr_tx0_data_i;
+    input usr_tx0_pma_clk_en_i;
+    input usr_tx0_rst_n_i;
+    input [3:0] usr_tx0_test_i;
+    output [3:0] usr_tx0_test_o;
+    output usr_tx1_busy_o;
+    input [7:0] usr_tx1_ctrl_char_is_k_i;
+    input [7:0] usr_tx1_ctrl_enc_en_i;
+    input [7:0] usr_tx1_ctrl_end_of_frame_i;
+    input [7:0] usr_tx1_ctrl_end_of_multiframe_i;
+    input usr_tx1_ctrl_replace_en_i;
+    input [7:0] usr_tx1_ctrl_scr_en_i;
+    input [63:0] usr_tx1_data_i;
+    input usr_tx1_pma_clk_en_i;
+    input usr_tx1_rst_n_i;
+    input [3:0] usr_tx1_test_i;
+    output [3:0] usr_tx1_test_o;
+    output usr_tx2_busy_o;
+    input [7:0] usr_tx2_ctrl_char_is_k_i;
+    input [7:0] usr_tx2_ctrl_enc_en_i;
+    input [7:0] usr_tx2_ctrl_end_of_frame_i;
+    input [7:0] usr_tx2_ctrl_end_of_multiframe_i;
+    input usr_tx2_ctrl_replace_en_i;
+    input [7:0] usr_tx2_ctrl_scr_en_i;
+    input [63:0] usr_tx2_data_i;
+    input usr_tx2_pma_clk_en_i;
+    input usr_tx2_rst_n_i;
+    input [3:0] usr_tx2_test_i;
+    output [3:0] usr_tx2_test_o;
+    output usr_tx3_busy_o;
+    input [7:0] usr_tx3_ctrl_char_is_k_i;
+    input [7:0] usr_tx3_ctrl_enc_en_i;
+    input [7:0] usr_tx3_ctrl_end_of_frame_i;
+    input [7:0] usr_tx3_ctrl_end_of_multiframe_i;
+    input usr_tx3_ctrl_replace_en_i;
+    input [7:0] usr_tx3_ctrl_scr_en_i;
+    input [63:0] usr_tx3_data_i;
+    input usr_tx3_pma_clk_en_i;
+    input usr_tx3_rst_n_i;
+    input [3:0] usr_tx3_test_i;
+    output [3:0] usr_tx3_test_o;
+    output usr_tx4_busy_o;
+    input [7:0] usr_tx4_ctrl_char_is_k_i;
+    input [7:0] usr_tx4_ctrl_enc_en_i;
+    input [7:0] usr_tx4_ctrl_end_of_frame_i;
+    input [7:0] usr_tx4_ctrl_end_of_multiframe_i;
+    input usr_tx4_ctrl_replace_en_i;
+    input [7:0] usr_tx4_ctrl_scr_en_i;
+    input [63:0] usr_tx4_data_i;
+    input usr_tx4_pma_clk_en_i;
+    input usr_tx4_rst_n_i;
+    input [3:0] usr_tx4_test_i;
+    output [3:0] usr_tx4_test_o;
+    output usr_tx5_busy_o;
+    input [7:0] usr_tx5_ctrl_char_is_k_i;
+    input [7:0] usr_tx5_ctrl_enc_en_i;
+    input [7:0] usr_tx5_ctrl_end_of_frame_i;
+    input [7:0] usr_tx5_ctrl_end_of_multiframe_i;
+    input usr_tx5_ctrl_replace_en_i;
+    input [7:0] usr_tx5_ctrl_scr_en_i;
+    input [63:0] usr_tx5_data_i;
+    input usr_tx5_pma_clk_en_i;
+    input usr_tx5_rst_n_i;
+    input [3:0] usr_tx5_test_i;
+    output [3:0] usr_tx5_test_o;
+    parameter cfg_main_i = 34'b0000000000000000000000000000000000;
+    parameter cfg_rx0_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter cfg_rx1_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter cfg_rx2_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter cfg_rx3_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter cfg_rx4_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter cfg_rx5_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter cfg_tx0_i = 0;
+    parameter cfg_tx1_i = 0;
+    parameter cfg_tx2_i = 0;
+    parameter cfg_tx3_i = 0;
+    parameter cfg_tx4_i = 0;
+    parameter cfg_tx5_i = 0;
+    parameter location = "";
+endmodule
diff --git a/techlibs/nanoxplore/cells_wrap_m.v b/techlibs/nanoxplore/cells_wrap_m.v
index 0bf3a905096..ff4c011c7c6 100644
--- a/techlibs/nanoxplore/cells_wrap_m.v
+++ b/techlibs/nanoxplore/cells_wrap_m.v
@@ -1035,4 +1035,467 @@ module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13,
     .WA6(WA6),
     .WE(WE)
   );
-endmodule
\ No newline at end of file
+endmodule
+
+module NX_IOM_CONTROL(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3
+, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3
+, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1
+, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1
+, DRO2, DRO3, DRO4, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16
+, LINK17, LINK18, LINK19, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);
+    output C1RED;
+    input C1RNE;
+    input C1RS;
+    input C1RW1;
+    input C1RW2;
+    input C1RW3;
+    input C1TS;
+    input C1TW;
+    output C2RED;
+    input C2RNE;
+    input C2RS;
+    input C2RW1;
+    input C2RW2;
+    input C2RW3;
+    input C2TS;
+    input C2TW;
+    input CAD1;
+    input CAD2;
+    input CAD3;
+    input CAD4;
+    input CAD5;
+    input CAD6;
+    output CAL;
+    input CAN1;
+    input CAN2;
+    input CAN3;
+    input CAN4;
+    input CAP1;
+    input CAP2;
+    input CAP3;
+    input CAP4;
+    input CAT1;
+    input CAT2;
+    input CAT3;
+    input CAT4;
+    input CCK;
+    output CKO1;
+    output CKO2;
+    input CTCK;
+    input DC;
+    input DCK;
+    input DIG;
+    input DIS;
+    input DOG;
+    input DOS;
+    input DPAG;
+    input DPAS;
+    input DQSG;
+    input DQSS;
+    input DRA1;
+    input DRA2;
+    input DRA3;
+    input DRA4;
+    input DRA5;
+    input DRA6;
+    input DRI1;
+    input DRI2;
+    input DRI3;
+    input DRI4;
+    input DRI5;
+    input DRI6;
+    input DRL;
+    output DRO1;
+    output DRO2;
+    output DRO3;
+    output DRO4;
+    output DRO5;
+    output DRO6;
+    input DS1;
+    input DS2;
+    input FA1;
+    input FA2;
+    input FA3;
+    input FA4;
+    input FA5;
+    input FA6;
+    output FLD;
+    output FLG;
+    input FZ;
+    inout [41:0] LINK1;
+    inout [41:0] LINK10;
+    inout [41:0] LINK11;
+    inout [41:0] LINK12;
+    inout [41:0] LINK13;
+    inout [41:0] LINK14;
+    inout [41:0] LINK15;
+    inout [41:0] LINK16;
+    inout [41:0] LINK17;
+    inout [41:0] LINK18;
+    inout [41:0] LINK19;
+    inout [41:0] LINK2;
+    inout [41:0] LINK20;
+    inout [41:0] LINK21;
+    inout [41:0] LINK22;
+    inout [41:0] LINK23;
+    inout [41:0] LINK24;
+    inout [41:0] LINK25;
+    inout [41:0] LINK26;
+    inout [41:0] LINK27;
+    inout [41:0] LINK28;
+    inout [41:0] LINK29;
+    inout [41:0] LINK3;
+    inout [41:0] LINK30;
+    inout [41:0] LINK31;
+    inout [41:0] LINK32;
+    inout [41:0] LINK33;
+    inout [41:0] LINK34;
+    inout [41:0] LINK4;
+    inout [41:0] LINK5;
+    inout [41:0] LINK6;
+    inout [41:0] LINK7;
+    inout [41:0] LINK8;
+    inout [41:0] LINK9;
+    input RRCK1;
+    input RRCK2;
+    input RTCK1;
+    input RTCK2;
+    input SPI1;
+    input SPI2;
+    input SPI3;
+    input WRCK1;
+    input WRCK2;
+    input WTCK1;
+    input WTCK2;
+    parameter div_rx1 = 4'b0000;
+    parameter div_rx2 = 4'b0000;
+    parameter div_tx1 = 4'b0000;
+    parameter div_tx2 = 4'b0000;
+    parameter inv_di_fclk1 = 1'b0;
+    parameter inv_di_fclk2 = 1'b0;
+    parameter latency1 = 1'b0;
+    parameter latency2 = 1'b0;
+    parameter location = "";
+    parameter mode_cpath = "";
+    parameter mode_epath = "";
+    parameter mode_io_cal = 1'b0;
+    parameter mode_rpath = "";
+    parameter mode_side1 = 0;
+    parameter mode_side2 = 0;
+    parameter mode_tpath = "";
+    parameter sel_clk_out1 = 1'b0;
+    parameter sel_clk_out2 = 1'b0;
+    parameter sel_clkr_rx1 = 1'b0;
+    parameter sel_clkr_rx2 = 1'b0;
+    parameter sel_clkw_rx1 = 2'b00;
+    parameter sel_clkw_rx2 = 2'b00;
+
+  NX_IOM_CONTROL_M #(
+    .div_rx1(div_rx1),
+    .div_rx2(div_rx2),
+    .div_tx1(div_tx1),
+    .div_tx2(div_tx2),
+    .inv_di_fclk1(inv_di_fclk1),
+    .inv_di_fclk2(inv_di_fclk2),
+    .latency1(latency1),
+    .latency2(latency2),
+    .location(location),
+    .mode_cpath(mode_cpath),
+    .mode_epath(mode_epath),
+    .mode_io_cal(mode_io_cal),
+    .mode_rpath(mode_rpath),
+    .mode_side1(mode_side1),
+    .mode_side2(mode_side2),
+    .mode_tpath(mode_tpath),
+    .sel_clk_out1(sel_clk_out1),
+    .sel_clk_out2(sel_clk_out2),
+    .sel_clkr_rx1(sel_clkr_rx1),
+    .sel_clkr_rx2(sel_clkr_rx2),
+    .sel_clkw_rx1(sel_clkw_rx1),
+    .sel_clkw_rx2(sel_clkw_rx2)
+  ) _TECHMAP_REPLACE_ (
+    .C1RED(C1RED),
+    .C1RNE(C1RNE),
+    .C1RS(C1RS),
+    .C1RW1(C1RW1),
+    .C1RW2(C1RW2),
+    .C1RW3(C1RW3),
+    .C1TS(C1TS),
+    .C1TW(C1TW),
+    .C2RED(C2RED),
+    .C2RNE(C2RNE),
+    .C2RS(C2RS),
+    .C2RW1(C2RW1),
+    .C2RW2(C2RW2),
+    .C2RW3(C2RW3),
+    .C2TS(C2TS),
+    .C2TW(C2TW),
+    .CAD1(CAD1),
+    .CAD2(CAD2),
+    .CAD3(CAD3),
+    .CAD4(CAD4),
+    .CAD5(CAD5),
+    .CAD6(CAD6),
+    .CAL(CAL),
+    .CAN1(CAN1),
+    .CAN2(CAN2),
+    .CAN3(CAN3),
+    .CAN4(CAN4),
+    .CAP1(CAP1),
+    .CAP2(CAP2),
+    .CAP3(CAP3),
+    .CAP4(CAP4),
+    .CAT1(CAT1),
+    .CAT2(CAT2),
+    .CAT3(CAT3),
+    .CAT4(CAT4),
+    .CCK(CCK),
+    .CKO1(CKO1),
+    .CKO2(CKO2),
+    .CTCK(CTCK),
+    .DC(DC),
+    .DCK(DCK),
+    .DIG(DIG),
+    .DIS(DIS),
+    .DOG(DOG),
+    .DOS(DOS),
+    .DPAG(DPAG),
+    .DPAS(DPAS),
+    .DQSG(DQSG),
+    .DQSS(DQSS),
+    .DRA1(DRA1),
+    .DRA2(DRA2),
+    .DRA3(DRA3),
+    .DRA4(DRA4),
+    .DRA5(DRA5),
+    .DRA6(DRA6),
+    .DRI1(DRI1),
+    .DRI2(DRI2),
+    .DRI3(DRI3),
+    .DRI4(DRI4),
+    .DRI5(DRI5),
+    .DRI6(DRI6),
+    .DRL(DRL),
+    .DRO1(DRO1),
+    .DRO2(DRO2),
+    .DRO3(DRO3),
+    .DRO4(DRO4),
+    .DRO5(DRO5),
+    .DRO6(DRO6),
+    .DS1(DS1),
+    .DS2(DS2),
+    .FA1(FA1),
+    .FA2(FA2),
+    .FA3(FA3),
+    .FA4(FA4),
+    .FA5(FA5),
+    .FA6(FA6),
+    .FLD(FLD),
+    .FLG(FLG),
+    .FZ(FZ),
+    .LINK1(LINK1),
+    .LINK10(LINK10),
+    .LINK11(LINK11),
+    .LINK12(LINK12),
+    .LINK13(LINK13),
+    .LINK14(LINK14),
+    .LINK15(LINK15),
+    .LINK16(LINK16),
+    .LINK17(LINK17),
+    .LINK18(LINK18),
+    .LINK19(LINK19),
+    .LINK2(LINK2),
+    .LINK20(LINK20),
+    .LINK21(LINK21),
+    .LINK22(LINK22),
+    .LINK23(LINK23),
+    .LINK24(LINK24),
+    .LINK25(LINK25),
+    .LINK26(LINK26),
+    .LINK27(LINK27),
+    .LINK28(LINK28),
+    .LINK29(LINK29),
+    .LINK3(LINK3),
+    .LINK30(LINK30),
+    .LINK31(LINK31),
+    .LINK32(LINK32),
+    .LINK33(LINK33),
+    .LINK34(LINK34),
+    .LINK4(LINK4),
+    .LINK5(LINK5),
+    .LINK6(LINK6),
+    .LINK7(LINK7),
+    .LINK8(LINK8),
+    .LINK9(LINK9),
+    .RRCK1(RRCK1),
+    .RRCK2(RRCK2),
+    .RTCK1(RTCK1),
+    .RTCK2(RTCK2),
+    .SPI1(SPI1),
+    .SPI2(SPI2),
+    .SPI3(SPI3),
+    .WRCK1(WRCK1),
+    .WRCK2(WRCK2),
+    .WTCK1(WTCK1),
+    .WTCK2(WTCK2)
+  );
+endmodule
+
+module NX_IOM_DRIVER(EI1, EI2, EI3, EI4, EI5, EL, ER, CI1, CI2, CI3, CI4, CI5, CL, CR, CTI, RI, RL, RR, CO, EO, RO1
+, RO2, RO3, RO4, RO5, CTO, LINK);
+    input CI1;
+    input CI2;
+    input CI3;
+    input CI4;
+    input CI5;
+    input CL;
+    output CO;
+    input CR;
+    input CTI;
+    output CTO;
+    input EI1;
+    input EI2;
+    input EI3;
+    input EI4;
+    input EI5;
+    input EL;
+    output EO;
+    input ER;
+    inout [41:0] LINK;
+    input RI;
+    input RL;
+    output RO1;
+    output RO2;
+    output RO3;
+    output RO4;
+    output RO5;
+    input RR;
+    parameter chained = 1'b0;
+    parameter cpath_edge = 1'b0;
+    parameter cpath_init = 1'b0;
+    parameter cpath_inv = 1'b0;
+    parameter cpath_load = 1'b0;
+    parameter cpath_mode = 4'b0000;
+    parameter cpath_sync = 1'b0;
+    parameter epath_dynamic = 1'b0;
+    parameter epath_edge = 1'b0;
+    parameter epath_init = 1'b0;
+    parameter epath_load = 1'b0;
+    parameter epath_mode = 4'b0000;
+    parameter epath_sync = 1'b0;
+    parameter location = "";
+    parameter rpath_dynamic = 1'b0;
+    parameter rpath_edge = 1'b0;
+    parameter rpath_init = 1'b0;
+    parameter rpath_load = 1'b0;
+    parameter rpath_mode = 4'b0000;
+    parameter rpath_sync = 1'b0;
+    parameter symbol = "";
+    parameter tpath_mode = 2'b00;
+    parameter variant = "";
+
+  NX_IOM_DRIVER_M #(
+    .chained(chained),
+    .cpath_edge(cpath_edge),
+    .cpath_init(cpath_init),
+    .cpath_inv(cpath_inv),
+    .cpath_load(cpath_load),
+    .cpath_mode(cpath_mode),
+    .cpath_sync(cpath_sync),
+    .epath_dynamic(epath_dynamic),
+    .epath_edge(epath_edge),
+    .epath_init(epath_init),
+    .epath_load(epath_load),
+    .epath_mode(epath_mode),
+    .epath_sync(epath_sync),
+    .location(location),
+    .rpath_dynamic(rpath_dynamic),
+    .rpath_edge(rpath_edge),
+    .rpath_init(rpath_init),
+    .rpath_load(rpath_load),
+    .rpath_mode(rpath_mode),
+    .rpath_sync(rpath_sync),
+    .symbol(symbol),
+    .tpath_mode(tpath_mode),
+    .variant(variant)
+  ) _TECHMAP_REPLACE_ (
+    .CI1(CI1),
+    .CI2(CI2),
+    .CI3(CI3),
+    .CI4(CI4),
+    .CI5(CI5),
+    .CL(CL),
+    .CO(CO),
+    .CR(CR),
+    .CTI(CTI),
+    .CTO(CTO),
+    .EI1(EI1),
+    .EI2(EI2),
+    .EI3(EI3),
+    .EI4(EI4),
+    .EI5(EI5),
+    .EL(EL),
+    .EO(EO),
+    .ER(ER),
+    .LINK(LINK),
+    .RI(RI),
+    .RL(RL),
+    .RO1(RO1),
+    .RO2(RO2),
+    .RO3(RO3),
+    .RO4(RO4),
+    .RO5(RO5),
+    .RR(RR)
+  );
+endmodule
+
+module NX_IOM_SERDES(RTCK, WRCK, WTCK, RRCK, TRST, RRST, CTCK, DCK, DRL, DIG, FZ, FLD, FLG, DS, DRA, DRI, DRO, DID, LINKN, LINKP);
+    input CTCK;
+    input DCK;
+    output [5:0] DID;
+    input DIG;
+    input [5:0] DRA;
+    input [5:0] DRI;
+    input DRL;
+    output [5:0] DRO;
+    input [1:0] DS;
+    output FLD;
+    output FLG;
+    input FZ;
+    inout [41:0] LINKN;
+    inout [41:0] LINKP;
+    input RRCK;
+    input RRST;
+    input RTCK;
+    input TRST;
+    input WRCK;
+    input WTCK;
+    parameter data_size = 5;
+    parameter location = "";
+
+  NX_IOM_SERDES_M #(
+    .data_size(data_size),
+    .location(location)
+  ) _TECHMAP_REPLACE_ (
+    .CTCK(CTCK),
+    .DCK(DCK),
+    .DID(DID),
+    .DIG(DIG),
+    .DRA(DRA),
+    .DRI(DRI),
+    .DRL(DRL),
+    .DRO(DRO),
+    .DS(DS),
+    .FLD(FLD),
+    .FLG(FLG),
+    .FZ(FZ),
+    .LINKN(LINKN),
+    .LINKP(LINKP),
+    .RRCK(RRCK),
+    .RRST(RRST),
+    .RTCK(RTCK),
+    .TRST(TRST),
+    .WRCK(WRCK),
+    .WTCK(WTCK)
+  );
+endmodule
diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v
index f5623dfeb43..b753c54660a 100644
--- a/techlibs/nanoxplore/cells_wrap_u.v
+++ b/techlibs/nanoxplore/cells_wrap_u.v
@@ -2704,3 +2704,605 @@ module UMUL48x36_4DSP(clk, rst, A, B, Z);
     input rst;
     parameter piped = "true";
 endmodule
+
+//TODO
+module NX_HSSL_U_FULL(hssl_clk_user_tx_i, hssl_clk_user_rx_i, hssl_clk_ref_i, hssl_clock_o, hssl_rclock_o, usr_dyn_cfg_en_i, usr_dyn_cfg_calibration_cs_n_i, usr_dyn_cfg_we_n_i, usr_dyn_cfg_wdata_sel_i, usr_pll_pma_rst_n_i, usr_pll_pma_pwr_down_n_i, usr_main_rst_n_i, usr_pll_lock_o, usr_pll_pma_lock_analog_o, usr_pll_ckfb_lock_o, usr_calibrate_pma_out_o, usr_main_async_debug_ack_i, usr_main_async_debug_req_o, scan_en_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i
+, usr_tx0_busy_o, usr_tx0_ctrl_invalid_k_o, usr_tx0_ctrl_driver_pwrdwn_n_i, usr_tx0_pma_clk_en_i, usr_tx0_pma_tx_clk_o, usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_rst_n_i, usr_rx0_pma_rst_n_i, usr_rx0_pma_m_eye_rst_i, usr_rx0_pma_pwr_down_n_i, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_ctrl_valid_realign_o, usr_rx0_busy_o, usr_rx0_pma_loss_of_signal_o, usr_rx0_pma_ll_fast_locked_o, usr_rx0_pma_ll_slow_locked_o
+, usr_rx0_pma_pll_lock_o, usr_rx0_pma_pll_lock_track_o, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_busy_o, usr_tx1_ctrl_invalid_k_o, usr_tx1_ctrl_driver_pwrdwn_n_i, usr_tx1_pma_clk_en_i, usr_tx1_pma_tx_clk_o, usr_rx1_ctrl_dscr_en_i, usr_rx1_ctrl_dec_en_i, usr_rx1_ctrl_align_en_i, usr_rx1_ctrl_align_sync_i, usr_rx1_ctrl_replace_en_i, usr_rx1_ctrl_el_buff_rst_i, usr_rx1_rst_n_i, usr_rx1_pma_rst_n_i, usr_rx1_pma_m_eye_rst_i, usr_rx1_pma_pwr_down_n_i, usr_rx1_ctrl_char_is_aligned_o, usr_rx1_ctrl_valid_realign_o
+, usr_rx1_busy_o, usr_rx1_pma_loss_of_signal_o, usr_rx1_pma_ll_fast_locked_o, usr_rx1_pma_ll_slow_locked_o, usr_rx1_pma_pll_lock_o, usr_rx1_pma_pll_lock_track_o, usr_tx2_ctrl_replace_en_i, usr_tx2_rst_n_i, usr_tx2_busy_o, usr_tx2_ctrl_invalid_k_o, usr_tx2_ctrl_driver_pwrdwn_n_i, usr_tx2_pma_clk_en_i, usr_tx2_pma_tx_clk_o, usr_rx2_ctrl_dscr_en_i, usr_rx2_ctrl_dec_en_i, usr_rx2_ctrl_align_en_i, usr_rx2_ctrl_align_sync_i, usr_rx2_ctrl_replace_en_i, usr_rx2_ctrl_el_buff_rst_i, usr_rx2_rst_n_i, usr_rx2_pma_rst_n_i
+, usr_rx2_pma_m_eye_rst_i, usr_rx2_pma_pwr_down_n_i, usr_rx2_ctrl_char_is_aligned_o, usr_rx2_ctrl_valid_realign_o, usr_rx2_busy_o, usr_rx2_pma_loss_of_signal_o, usr_rx2_pma_ll_fast_locked_o, usr_rx2_pma_ll_slow_locked_o, usr_rx2_pma_pll_lock_o, usr_rx2_pma_pll_lock_track_o, usr_tx3_ctrl_replace_en_i, usr_tx3_rst_n_i, usr_tx3_busy_o, usr_tx3_ctrl_invalid_k_o, usr_tx3_ctrl_driver_pwrdwn_n_i, usr_tx3_pma_clk_en_i, usr_tx3_pma_tx_clk_o, usr_rx3_ctrl_dscr_en_i, usr_rx3_ctrl_dec_en_i, usr_rx3_ctrl_align_en_i, usr_rx3_ctrl_align_sync_i
+, usr_rx3_ctrl_replace_en_i, usr_rx3_ctrl_el_buff_rst_i, usr_rx3_rst_n_i, usr_rx3_pma_rst_n_i, usr_rx3_pma_m_eye_rst_i, usr_rx3_pma_pwr_down_n_i, usr_rx3_ctrl_char_is_aligned_o, usr_rx3_ctrl_valid_realign_o, usr_rx3_busy_o, usr_rx3_pma_loss_of_signal_o, usr_rx3_pma_ll_fast_locked_o, usr_rx3_pma_ll_slow_locked_o, usr_rx3_pma_pll_lock_o, usr_rx3_pma_pll_lock_track_o, usr_tx0_ctrl_enc_en_i, usr_tx0_ctrl_char_is_k_i, usr_tx0_ctrl_scr_en_i, usr_tx0_ctrl_end_of_multiframe_i, usr_tx0_ctrl_end_of_frame_i, usr_tx0_data_i, usr_rx0_data_o
+, usr_rx0_ctrl_ovs_bit_sel_i, usr_rx0_ctrl_char_is_comma_o, usr_rx0_ctrl_char_is_k_o, usr_rx0_ctrl_not_in_table_o, usr_rx0_ctrl_disp_err_o, usr_rx0_ctrl_char_is_a_o, usr_rx0_ctrl_char_is_f_o, usr_rx0_test_o, usr_tx1_ctrl_enc_en_i, usr_tx1_ctrl_char_is_k_i, usr_tx1_ctrl_scr_en_i, usr_tx1_ctrl_end_of_multiframe_i, usr_tx1_ctrl_end_of_frame_i, usr_tx1_data_i, usr_rx1_data_o, usr_rx1_ctrl_ovs_bit_sel_i, usr_rx1_ctrl_char_is_comma_o, usr_rx1_ctrl_char_is_k_o, usr_rx1_ctrl_not_in_table_o, usr_rx1_ctrl_disp_err_o, usr_rx1_ctrl_char_is_a_o
+, usr_rx1_ctrl_char_is_f_o, usr_rx1_test_o, usr_tx2_ctrl_enc_en_i, usr_tx2_ctrl_char_is_k_i, usr_tx2_ctrl_scr_en_i, usr_tx2_ctrl_end_of_multiframe_i, usr_tx2_ctrl_end_of_frame_i, usr_tx2_data_i, usr_rx2_data_o, usr_rx2_ctrl_ovs_bit_sel_i, usr_rx2_ctrl_char_is_comma_o, usr_rx2_ctrl_char_is_k_o, usr_rx2_ctrl_not_in_table_o, usr_rx2_ctrl_disp_err_o, usr_rx2_ctrl_char_is_a_o, usr_rx2_ctrl_char_is_f_o, usr_rx2_test_o, usr_tx3_ctrl_enc_en_i, usr_tx3_ctrl_char_is_k_i, usr_tx3_ctrl_scr_en_i, usr_tx3_ctrl_end_of_multiframe_i
+, usr_tx3_ctrl_end_of_frame_i, usr_tx3_data_i, usr_rx3_data_o, usr_rx3_ctrl_ovs_bit_sel_i, usr_rx3_ctrl_char_is_comma_o, usr_rx3_ctrl_char_is_k_o, usr_rx3_ctrl_not_in_table_o, usr_rx3_ctrl_disp_err_o, usr_rx3_ctrl_char_is_a_o, usr_rx3_ctrl_char_is_f_o, usr_rx3_test_o, usr_dyn_cfg_addr_i, usr_dyn_cfg_wdata_i, usr_main_async_debug_lane_sel_i, usr_main_rx_pma_ll_out_o, scan_in_i, scan_out_o, usr_rx0_ctrl_debug_sel_i, usr_rx1_ctrl_debug_sel_i, usr_rx2_ctrl_debug_sel_i, usr_rx3_ctrl_debug_sel_i
+, usr_dyn_cfg_lane_cs_n_i);
+    input hssl_clk_ref_i;
+    input hssl_clk_user_rx_i;
+    input hssl_clk_user_tx_i;
+    output hssl_clock_o;
+    output hssl_rclock_o;
+    input scan_en_i;
+    input [7:0] scan_in_i;
+    output [7:0] scan_out_o;
+    output usr_calibrate_pma_out_o;
+    input [3:0] usr_dyn_cfg_addr_i;
+    input usr_dyn_cfg_calibration_cs_n_i;
+    input usr_dyn_cfg_en_i;
+    input [3:0] usr_dyn_cfg_lane_cs_n_i;
+    input [11:0] usr_dyn_cfg_wdata_i;
+    input usr_dyn_cfg_wdata_sel_i;
+    input usr_dyn_cfg_we_n_i;
+    input usr_main_async_debug_ack_i;
+    input [1:0] usr_main_async_debug_lane_sel_i;
+    output usr_main_async_debug_req_o;
+    input usr_main_rst_n_i;
+    output [19:0] usr_main_rx_pma_ll_out_o;
+    output usr_pll_ckfb_lock_o;
+    output usr_pll_lock_o;
+    output usr_pll_pma_lock_analog_o;
+    input usr_pll_pma_pwr_down_n_i;
+    input usr_pll_pma_rst_n_i;
+    output usr_rx0_busy_o;
+    input usr_rx0_ctrl_align_en_i;
+    input usr_rx0_ctrl_align_sync_i;
+    output [7:0] usr_rx0_ctrl_char_is_a_o;
+    output usr_rx0_ctrl_char_is_aligned_o;
+    output [7:0] usr_rx0_ctrl_char_is_comma_o;
+    output [7:0] usr_rx0_ctrl_char_is_f_o;
+    output [7:0] usr_rx0_ctrl_char_is_k_o;
+    input [2:0] usr_rx0_ctrl_debug_sel_i;
+    input usr_rx0_ctrl_dec_en_i;
+    output [7:0] usr_rx0_ctrl_disp_err_o;
+    input usr_rx0_ctrl_dscr_en_i;
+    input usr_rx0_ctrl_el_buff_rst_i;
+    output [7:0] usr_rx0_ctrl_not_in_table_o;
+    input [1:0] usr_rx0_ctrl_ovs_bit_sel_i;
+    input usr_rx0_ctrl_replace_en_i;
+    output usr_rx0_ctrl_valid_realign_o;
+    output [63:0] usr_rx0_data_o;
+    output usr_rx0_pma_ll_fast_locked_o;
+    output usr_rx0_pma_ll_slow_locked_o;
+    output usr_rx0_pma_loss_of_signal_o;
+    input usr_rx0_pma_m_eye_rst_i;
+    output usr_rx0_pma_pll_lock_o;
+    output usr_rx0_pma_pll_lock_track_o;
+    input usr_rx0_pma_pwr_down_n_i;
+    input usr_rx0_pma_rst_n_i;
+    input usr_rx0_rst_n_i;
+    output [7:0] usr_rx0_test_o;
+    output usr_rx1_busy_o;
+    input usr_rx1_ctrl_align_en_i;
+    input usr_rx1_ctrl_align_sync_i;
+    output [7:0] usr_rx1_ctrl_char_is_a_o;
+    output usr_rx1_ctrl_char_is_aligned_o;
+    output [7:0] usr_rx1_ctrl_char_is_comma_o;
+    output [7:0] usr_rx1_ctrl_char_is_f_o;
+    output [7:0] usr_rx1_ctrl_char_is_k_o;
+    input [2:0] usr_rx1_ctrl_debug_sel_i;
+    input usr_rx1_ctrl_dec_en_i;
+    output [7:0] usr_rx1_ctrl_disp_err_o;
+    input usr_rx1_ctrl_dscr_en_i;
+    input usr_rx1_ctrl_el_buff_rst_i;
+    output [7:0] usr_rx1_ctrl_not_in_table_o;
+    input [1:0] usr_rx1_ctrl_ovs_bit_sel_i;
+    input usr_rx1_ctrl_replace_en_i;
+    output usr_rx1_ctrl_valid_realign_o;
+    output [63:0] usr_rx1_data_o;
+    output usr_rx1_pma_ll_fast_locked_o;
+    output usr_rx1_pma_ll_slow_locked_o;
+    output usr_rx1_pma_loss_of_signal_o;
+    input usr_rx1_pma_m_eye_rst_i;
+    output usr_rx1_pma_pll_lock_o;
+    output usr_rx1_pma_pll_lock_track_o;
+    input usr_rx1_pma_pwr_down_n_i;
+    input usr_rx1_pma_rst_n_i;
+    input usr_rx1_rst_n_i;
+    output [7:0] usr_rx1_test_o;
+    output usr_rx2_busy_o;
+    input usr_rx2_ctrl_align_en_i;
+    input usr_rx2_ctrl_align_sync_i;
+    output [7:0] usr_rx2_ctrl_char_is_a_o;
+    output usr_rx2_ctrl_char_is_aligned_o;
+    output [7:0] usr_rx2_ctrl_char_is_comma_o;
+    output [7:0] usr_rx2_ctrl_char_is_f_o;
+    output [7:0] usr_rx2_ctrl_char_is_k_o;
+    input [2:0] usr_rx2_ctrl_debug_sel_i;
+    input usr_rx2_ctrl_dec_en_i;
+    output [7:0] usr_rx2_ctrl_disp_err_o;
+    input usr_rx2_ctrl_dscr_en_i;
+    input usr_rx2_ctrl_el_buff_rst_i;
+    output [7:0] usr_rx2_ctrl_not_in_table_o;
+    input [1:0] usr_rx2_ctrl_ovs_bit_sel_i;
+    input usr_rx2_ctrl_replace_en_i;
+    output usr_rx2_ctrl_valid_realign_o;
+    output [63:0] usr_rx2_data_o;
+    output usr_rx2_pma_ll_fast_locked_o;
+    output usr_rx2_pma_ll_slow_locked_o;
+    output usr_rx2_pma_loss_of_signal_o;
+    input usr_rx2_pma_m_eye_rst_i;
+    output usr_rx2_pma_pll_lock_o;
+    output usr_rx2_pma_pll_lock_track_o;
+    input usr_rx2_pma_pwr_down_n_i;
+    input usr_rx2_pma_rst_n_i;
+    input usr_rx2_rst_n_i;
+    output [7:0] usr_rx2_test_o;
+    output usr_rx3_busy_o;
+    input usr_rx3_ctrl_align_en_i;
+    input usr_rx3_ctrl_align_sync_i;
+    output [7:0] usr_rx3_ctrl_char_is_a_o;
+    output usr_rx3_ctrl_char_is_aligned_o;
+    output [7:0] usr_rx3_ctrl_char_is_comma_o;
+    output [7:0] usr_rx3_ctrl_char_is_f_o;
+    output [7:0] usr_rx3_ctrl_char_is_k_o;
+    input [2:0] usr_rx3_ctrl_debug_sel_i;
+    input usr_rx3_ctrl_dec_en_i;
+    output [7:0] usr_rx3_ctrl_disp_err_o;
+    input usr_rx3_ctrl_dscr_en_i;
+    input usr_rx3_ctrl_el_buff_rst_i;
+    output [7:0] usr_rx3_ctrl_not_in_table_o;
+    input [1:0] usr_rx3_ctrl_ovs_bit_sel_i;
+    input usr_rx3_ctrl_replace_en_i;
+    output usr_rx3_ctrl_valid_realign_o;
+    output [63:0] usr_rx3_data_o;
+    output usr_rx3_pma_ll_fast_locked_o;
+    output usr_rx3_pma_ll_slow_locked_o;
+    output usr_rx3_pma_loss_of_signal_o;
+    input usr_rx3_pma_m_eye_rst_i;
+    output usr_rx3_pma_pll_lock_o;
+    output usr_rx3_pma_pll_lock_track_o;
+    input usr_rx3_pma_pwr_down_n_i;
+    input usr_rx3_pma_rst_n_i;
+    input usr_rx3_rst_n_i;
+    output [7:0] usr_rx3_test_o;
+    output usr_tx0_busy_o;
+    input [7:0] usr_tx0_ctrl_char_is_k_i;
+    input usr_tx0_ctrl_driver_pwrdwn_n_i;
+    input [7:0] usr_tx0_ctrl_enc_en_i;
+    input [7:0] usr_tx0_ctrl_end_of_frame_i;
+    input [7:0] usr_tx0_ctrl_end_of_multiframe_i;
+    output usr_tx0_ctrl_invalid_k_o;
+    input usr_tx0_ctrl_replace_en_i;
+    input [7:0] usr_tx0_ctrl_scr_en_i;
+    input [63:0] usr_tx0_data_i;
+    input usr_tx0_pma_clk_en_i;
+    output usr_tx0_pma_tx_clk_o;
+    input usr_tx0_rst_n_i;
+    output usr_tx1_busy_o;
+    input [7:0] usr_tx1_ctrl_char_is_k_i;
+    input usr_tx1_ctrl_driver_pwrdwn_n_i;
+    input [7:0] usr_tx1_ctrl_enc_en_i;
+    input [7:0] usr_tx1_ctrl_end_of_frame_i;
+    input [7:0] usr_tx1_ctrl_end_of_multiframe_i;
+    output usr_tx1_ctrl_invalid_k_o;
+    input usr_tx1_ctrl_replace_en_i;
+    input [7:0] usr_tx1_ctrl_scr_en_i;
+    input [63:0] usr_tx1_data_i;
+    input usr_tx1_pma_clk_en_i;
+    output usr_tx1_pma_tx_clk_o;
+    input usr_tx1_rst_n_i;
+    output usr_tx2_busy_o;
+    input [7:0] usr_tx2_ctrl_char_is_k_i;
+    input usr_tx2_ctrl_driver_pwrdwn_n_i;
+    input [7:0] usr_tx2_ctrl_enc_en_i;
+    input [7:0] usr_tx2_ctrl_end_of_frame_i;
+    input [7:0] usr_tx2_ctrl_end_of_multiframe_i;
+    output usr_tx2_ctrl_invalid_k_o;
+    input usr_tx2_ctrl_replace_en_i;
+    input [7:0] usr_tx2_ctrl_scr_en_i;
+    input [63:0] usr_tx2_data_i;
+    input usr_tx2_pma_clk_en_i;
+    output usr_tx2_pma_tx_clk_o;
+    input usr_tx2_rst_n_i;
+    output usr_tx3_busy_o;
+    input [7:0] usr_tx3_ctrl_char_is_k_i;
+    input usr_tx3_ctrl_driver_pwrdwn_n_i;
+    input [7:0] usr_tx3_ctrl_enc_en_i;
+    input [7:0] usr_tx3_ctrl_end_of_frame_i;
+    input [7:0] usr_tx3_ctrl_end_of_multiframe_i;
+    output usr_tx3_ctrl_invalid_k_o;
+    input usr_tx3_ctrl_replace_en_i;
+    input [7:0] usr_tx3_ctrl_scr_en_i;
+    input [63:0] usr_tx3_data_i;
+    input usr_tx3_pma_clk_en_i;
+    output usr_tx3_pma_tx_clk_o;
+    input usr_tx3_rst_n_i;
+    parameter cfg_dyn_all_rx_pma_m_eye_coarse_ena_i = 1'b0;
+    parameter cfg_dyn_all_rx_pma_m_eye_dn_i = 1'b0;
+    parameter cfg_dyn_all_rx_pma_m_eye_fine_ena_i = 1'b0;
+    parameter cfg_dyn_all_rx_pma_m_eye_i = 1'b0;
+    parameter cfg_dyn_all_rx_pma_m_eye_step_i = 4'b0000;
+    parameter cfg_dyn_all_rx_pma_m_eye_up_i = 1'b0;
+    parameter cfg_dyn_all_rx_pma_threshold_1 = 5'b00000;
+    parameter cfg_dyn_all_rx_pma_threshold_2 = 5'b00000;
+    parameter cfg_dyn_all_rx_pma_trim_locked_i = 3'b000;
+    parameter cfg_dyn_all_rx_pma_trim_mode_i = 2'b00;
+    parameter cfg_dyn_all_rx_pma_trim_unlocked_i = 3'b000;
+    parameter cfg_dyn_rx0_pma_ctle_cap_p_i = 4'b0000;
+    parameter cfg_dyn_rx0_pma_ctle_res_p_i = 4'b0000;
+    parameter cfg_dyn_rx0_pma_dfe_idac_tap1_n_i = 6'b000000;
+    parameter cfg_dyn_rx0_pma_dfe_idac_tap2_n_i = 6'b000000;
+    parameter cfg_dyn_rx0_pma_dfe_idac_tap3_n_i = 6'b000000;
+    parameter cfg_dyn_rx0_pma_dfe_idac_tap4_n_i = 6'b000000;
+    parameter cfg_dyn_rx0_pma_termination_cmd_i = 6'b000000;
+    parameter cfg_dyn_rx1_pma_ctle_cap_p_i = 4'b0000;
+    parameter cfg_dyn_rx1_pma_ctle_res_p_i = 4'b0000;
+    parameter cfg_dyn_rx1_pma_dfe_idac_tap1_n_i = 6'b000000;
+    parameter cfg_dyn_rx1_pma_dfe_idac_tap2_n_i = 6'b000000;
+    parameter cfg_dyn_rx1_pma_dfe_idac_tap3_n_i = 6'b000000;
+    parameter cfg_dyn_rx1_pma_dfe_idac_tap4_n_i = 6'b000000;
+    parameter cfg_dyn_rx1_pma_termination_cmd_i = 6'b000000;
+    parameter cfg_dyn_rx2_pma_ctle_cap_p_i = 4'b0000;
+    parameter cfg_dyn_rx2_pma_ctle_res_p_i = 4'b0000;
+    parameter cfg_dyn_rx2_pma_dfe_idac_tap1_n_i = 6'b000000;
+    parameter cfg_dyn_rx2_pma_dfe_idac_tap2_n_i = 6'b000000;
+    parameter cfg_dyn_rx2_pma_dfe_idac_tap3_n_i = 6'b000000;
+    parameter cfg_dyn_rx2_pma_dfe_idac_tap4_n_i = 6'b000000;
+    parameter cfg_dyn_rx2_pma_termination_cmd_i = 6'b000000;
+    parameter cfg_dyn_rx3_pma_ctle_cap_p_i = 4'b0000;
+    parameter cfg_dyn_rx3_pma_ctle_res_p_i = 4'b0000;
+    parameter cfg_dyn_rx3_pma_dfe_idac_tap1_n_i = 6'b000000;
+    parameter cfg_dyn_rx3_pma_dfe_idac_tap2_n_i = 6'b000000;
+    parameter cfg_dyn_rx3_pma_dfe_idac_tap3_n_i = 6'b000000;
+    parameter cfg_dyn_rx3_pma_dfe_idac_tap4_n_i = 6'b000000;
+    parameter cfg_dyn_rx3_pma_termination_cmd_i = 6'b000000;
+    parameter cfg_dyn_tx0_pma_main_en_i = 6'b000000;
+    parameter cfg_dyn_tx0_pma_main_sign_i = 1'b0;
+    parameter cfg_dyn_tx0_pma_margin_input_i = 9'b000000000;
+    parameter cfg_dyn_tx0_pma_margin_sel_i = 9'b000000000;
+    parameter cfg_dyn_tx0_pma_post_en_i = 5'b00000;
+    parameter cfg_dyn_tx0_pma_post_sel_i = 8'b00000000;
+    parameter cfg_dyn_tx0_pma_post_sign_i = 1'b0;
+    parameter cfg_dyn_tx0_pma_pre_en_i = 1'b0;
+    parameter cfg_dyn_tx0_pma_pre_sel_i = 4'b0000;
+    parameter cfg_dyn_tx0_pma_pre_sign_i = 1'b0;
+    parameter cfg_dyn_tx1_pma_main_en_i = 6'b000000;
+    parameter cfg_dyn_tx1_pma_main_sign_i = 1'b0;
+    parameter cfg_dyn_tx1_pma_margin_input_i = 9'b000000000;
+    parameter cfg_dyn_tx1_pma_margin_sel_i = 9'b000000000;
+    parameter cfg_dyn_tx1_pma_post_en_i = 5'b00000;
+    parameter cfg_dyn_tx1_pma_post_sel_i = 8'b00000000;
+    parameter cfg_dyn_tx1_pma_post_sign_i = 1'b0;
+    parameter cfg_dyn_tx1_pma_pre_en_i = 1'b0;
+    parameter cfg_dyn_tx1_pma_pre_sel_i = 4'b0000;
+    parameter cfg_dyn_tx1_pma_pre_sign_i = 1'b0;
+    parameter cfg_dyn_tx2_pma_main_en_i = 6'b000000;
+    parameter cfg_dyn_tx2_pma_main_sign_i = 1'b0;
+    parameter cfg_dyn_tx2_pma_margin_input_i = 9'b000000000;
+    parameter cfg_dyn_tx2_pma_margin_sel_i = 9'b000000000;
+    parameter cfg_dyn_tx2_pma_post_en_i = 5'b00000;
+    parameter cfg_dyn_tx2_pma_post_sel_i = 8'b00000000;
+    parameter cfg_dyn_tx2_pma_post_sign_i = 1'b0;
+    parameter cfg_dyn_tx2_pma_pre_en_i = 1'b0;
+    parameter cfg_dyn_tx2_pma_pre_sel_i = 4'b0000;
+    parameter cfg_dyn_tx2_pma_pre_sign_i = 1'b0;
+    parameter cfg_dyn_tx3_pma_main_en_i = 6'b000000;
+    parameter cfg_dyn_tx3_pma_main_sign_i = 1'b0;
+    parameter cfg_dyn_tx3_pma_margin_input_i = 9'b000000000;
+    parameter cfg_dyn_tx3_pma_margin_sel_i = 9'b000000000;
+    parameter cfg_dyn_tx3_pma_post_en_i = 5'b00000;
+    parameter cfg_dyn_tx3_pma_post_sel_i = 8'b00000000;
+    parameter cfg_dyn_tx3_pma_post_sign_i = 1'b0;
+    parameter cfg_dyn_tx3_pma_pre_en_i = 1'b0;
+    parameter cfg_dyn_tx3_pma_pre_sel_i = 4'b0000;
+    parameter cfg_dyn_tx3_pma_pre_sign_i = 1'b0;
+    parameter cfg_main_clk_to_fabric_div_en_i = 1'b0;
+    parameter cfg_main_clk_to_fabric_div_mode_i = 1'b0;
+    parameter cfg_main_clk_to_fabric_sel_i = 1'b0;
+    parameter cfg_main_rclk_to_fabric_sel_i = 2'b00;
+    parameter cfg_main_use_only_usr_clock_i = 1'b0;
+    parameter cfg_pcs_ovs_en_i = 1'b0;
+    parameter cfg_pcs_ovs_mode_i = 1'b0;
+    parameter cfg_pcs_pll_lock_ppm_i = 3'b000;
+    parameter cfg_pcs_word_len_i = 2'b00;
+    parameter cfg_pll_pma_ckref_ext_i = 1'b0;
+    parameter cfg_pll_pma_cpump_i = 4'b0000;
+    parameter cfg_pll_pma_divl_i = 2'b00;
+    parameter cfg_pll_pma_divm_i = 1'b0;
+    parameter cfg_pll_pma_divn_i = 2'b00;
+    parameter cfg_pll_pma_gbx_en_i = 1'b0;
+    parameter cfg_pll_pma_int_data_len_i = 1'b0;
+    parameter cfg_pll_pma_lvds_en_i = 1'b0;
+    parameter cfg_pll_pma_lvds_mux_i = 1'b0;
+    parameter cfg_pll_pma_mux_ckref_i = 1'b0;
+    parameter cfg_rx0_gearbox_en_i = 1'b0;
+    parameter cfg_rx0_gearbox_mode_i = 1'b0;
+    parameter cfg_rx0_pcs_8b_dscr_sel_i = 1'b0;
+    parameter cfg_rx0_pcs_align_bypass_i = 1'b0;
+    parameter cfg_rx0_pcs_buffers_bypass_i = 1'b0;
+    parameter cfg_rx0_pcs_buffers_use_cdc_i = 1'b0;
+    parameter cfg_rx0_pcs_bypass_pma_cdc_i = 1'b0;
+    parameter cfg_rx0_pcs_bypass_usr_cdc_i = 1'b0;
+    parameter cfg_rx0_pcs_comma_mask_i = 10'b0000000000;
+    parameter cfg_rx0_pcs_debug_en_i = 1'b0;
+    parameter cfg_rx0_pcs_dec_bypass_i = 1'b0;
+    parameter cfg_rx0_pcs_dscr_bypass_i = 1'b0;
+    parameter cfg_rx0_pcs_el_buff_diff_bef_comp_i = 4'b0000;
+    parameter cfg_rx0_pcs_el_buff_max_comp_i = 4'b0000;
+    parameter cfg_rx0_pcs_el_buff_only_one_skp_i = 1'b0;
+    parameter cfg_rx0_pcs_el_buff_skp_char_0_i = 9'b000000000;
+    parameter cfg_rx0_pcs_el_buff_skp_char_1_i = 9'b000000000;
+    parameter cfg_rx0_pcs_el_buff_skp_char_2_i = 9'b000000000;
+    parameter cfg_rx0_pcs_el_buff_skp_char_3_i = 9'b000000000;
+    parameter cfg_rx0_pcs_el_buff_skp_header_0_i = 9'b000000000;
+    parameter cfg_rx0_pcs_el_buff_skp_header_1_i = 9'b000000000;
+    parameter cfg_rx0_pcs_el_buff_skp_header_2_i = 9'b000000000;
+    parameter cfg_rx0_pcs_el_buff_skp_header_3_i = 9'b000000000;
+    parameter cfg_rx0_pcs_el_buff_skp_header_size_i = 2'b00;
+    parameter cfg_rx0_pcs_el_buff_skp_seq_size_i = 2'b00;
+    parameter cfg_rx0_pcs_fsm_sel_i = 2'b00;
+    parameter cfg_rx0_pcs_fsm_watchdog_en_i = 1'b0;
+    parameter cfg_rx0_pcs_loopback_i = 1'b0;
+    parameter cfg_rx0_pcs_m_comma_en_i = 1'b0;
+    parameter cfg_rx0_pcs_m_comma_val_i = 10'b0000000000;
+    parameter cfg_rx0_pcs_nb_comma_bef_realign_i = 2'b00;
+    parameter cfg_rx0_pcs_p_comma_en_i = 1'b0;
+    parameter cfg_rx0_pcs_p_comma_val_i = 10'b0000000000;
+    parameter cfg_rx0_pcs_polarity_i = 1'b0;
+    parameter cfg_rx0_pcs_protocol_size_i = 1'b0;
+    parameter cfg_rx0_pcs_replace_bypass_i = 1'b0;
+    parameter cfg_rx0_pcs_sync_supported_i = 1'b0;
+    parameter cfg_rx0_pma_cdr_cp_i = 4'b0000;
+    parameter cfg_rx0_pma_clk_pos_i = 1'b0;
+    parameter cfg_rx0_pma_coarse_ppm_i = 3'b000;
+    parameter cfg_rx0_pma_ctrl_term_i = 6'b000000;
+    parameter cfg_rx0_pma_dco_divl_i = 2'b00;
+    parameter cfg_rx0_pma_dco_divm_i = 1'b0;
+    parameter cfg_rx0_pma_dco_divn_i = 2'b00;
+    parameter cfg_rx0_pma_dco_reg_res_i = 2'b00;
+    parameter cfg_rx0_pma_dco_vref_sel_i = 1'b0;
+    parameter cfg_rx0_pma_fine_ppm_i = 3'b000;
+    parameter cfg_rx0_pma_loopback_i = 1'b0;
+    parameter cfg_rx0_pma_m_eye_ppm_i = 3'b000;
+    parameter cfg_rx0_pma_peak_detect_cmd_i = 2'b00;
+    parameter cfg_rx0_pma_peak_detect_on_i = 1'b0;
+    parameter cfg_rx0_pma_pll_cpump_n_i = 3'b000;
+    parameter cfg_rx0_pma_pll_divf_en_n_i = 1'b0;
+    parameter cfg_rx0_pma_pll_divf_i = 2'b00;
+    parameter cfg_rx0_pma_pll_divm_en_n_i = 1'b0;
+    parameter cfg_rx0_pma_pll_divm_i = 2'b00;
+    parameter cfg_rx0_pma_pll_divn_en_n_i = 1'b0;
+    parameter cfg_rx0_pma_pll_divn_i = 1'b0;
+    parameter cfg_rx1_gearbox_en_i = 1'b0;
+    parameter cfg_rx1_gearbox_mode_i = 1'b0;
+    parameter cfg_rx1_pcs_8b_dscr_sel_i = 1'b0;
+    parameter cfg_rx1_pcs_align_bypass_i = 1'b0;
+    parameter cfg_rx1_pcs_buffers_bypass_i = 1'b0;
+    parameter cfg_rx1_pcs_buffers_use_cdc_i = 1'b0;
+    parameter cfg_rx1_pcs_bypass_pma_cdc_i = 1'b0;
+    parameter cfg_rx1_pcs_bypass_usr_cdc_i = 1'b0;
+    parameter cfg_rx1_pcs_comma_mask_i = 10'b0000000000;
+    parameter cfg_rx1_pcs_debug_en_i = 1'b0;
+    parameter cfg_rx1_pcs_dec_bypass_i = 1'b0;
+    parameter cfg_rx1_pcs_dscr_bypass_i = 1'b0;
+    parameter cfg_rx1_pcs_el_buff_diff_bef_comp_i = 4'b0000;
+    parameter cfg_rx1_pcs_el_buff_max_comp_i = 4'b0000;
+    parameter cfg_rx1_pcs_el_buff_only_one_skp_i = 1'b0;
+    parameter cfg_rx1_pcs_el_buff_skp_char_0_i = 9'b000000000;
+    parameter cfg_rx1_pcs_el_buff_skp_char_1_i = 9'b000000000;
+    parameter cfg_rx1_pcs_el_buff_skp_char_2_i = 9'b000000000;
+    parameter cfg_rx1_pcs_el_buff_skp_char_3_i = 9'b000000000;
+    parameter cfg_rx1_pcs_el_buff_skp_header_0_i = 9'b000000000;
+    parameter cfg_rx1_pcs_el_buff_skp_header_1_i = 9'b000000000;
+    parameter cfg_rx1_pcs_el_buff_skp_header_2_i = 9'b000000000;
+    parameter cfg_rx1_pcs_el_buff_skp_header_3_i = 9'b000000000;
+    parameter cfg_rx1_pcs_el_buff_skp_header_size_i = 2'b00;
+    parameter cfg_rx1_pcs_el_buff_skp_seq_size_i = 2'b00;
+    parameter cfg_rx1_pcs_fsm_sel_i = 2'b00;
+    parameter cfg_rx1_pcs_fsm_watchdog_en_i = 1'b0;
+    parameter cfg_rx1_pcs_loopback_i = 1'b0;
+    parameter cfg_rx1_pcs_m_comma_en_i = 1'b0;
+    parameter cfg_rx1_pcs_m_comma_val_i = 10'b0000000000;
+    parameter cfg_rx1_pcs_nb_comma_bef_realign_i = 2'b00;
+    parameter cfg_rx1_pcs_p_comma_en_i = 1'b0;
+    parameter cfg_rx1_pcs_p_comma_val_i = 10'b0000000000;
+    parameter cfg_rx1_pcs_polarity_i = 1'b0;
+    parameter cfg_rx1_pcs_protocol_size_i = 1'b0;
+    parameter cfg_rx1_pcs_replace_bypass_i = 1'b0;
+    parameter cfg_rx1_pcs_sync_supported_i = 1'b0;
+    parameter cfg_rx1_pma_cdr_cp_i = 4'b0000;
+    parameter cfg_rx1_pma_clk_pos_i = 1'b0;
+    parameter cfg_rx1_pma_coarse_ppm_i = 3'b000;
+    parameter cfg_rx1_pma_ctrl_term_i = 6'b000000;
+    parameter cfg_rx1_pma_dco_divl_i = 2'b00;
+    parameter cfg_rx1_pma_dco_divm_i = 1'b0;
+    parameter cfg_rx1_pma_dco_divn_i = 2'b00;
+    parameter cfg_rx1_pma_dco_reg_res_i = 2'b00;
+    parameter cfg_rx1_pma_dco_vref_sel_i = 1'b0;
+    parameter cfg_rx1_pma_fine_ppm_i = 3'b000;
+    parameter cfg_rx1_pma_loopback_i = 1'b0;
+    parameter cfg_rx1_pma_m_eye_ppm_i = 3'b000;
+    parameter cfg_rx1_pma_peak_detect_cmd_i = 2'b00;
+    parameter cfg_rx1_pma_peak_detect_on_i = 1'b0;
+    parameter cfg_rx1_pma_pll_cpump_n_i = 3'b000;
+    parameter cfg_rx1_pma_pll_divf_en_n_i = 1'b0;
+    parameter cfg_rx1_pma_pll_divf_i = 2'b00;
+    parameter cfg_rx1_pma_pll_divm_en_n_i = 1'b0;
+    parameter cfg_rx1_pma_pll_divm_i = 2'b00;
+    parameter cfg_rx1_pma_pll_divn_en_n_i = 1'b0;
+    parameter cfg_rx1_pma_pll_divn_i = 1'b0;
+    parameter cfg_rx2_gearbox_en_i = 1'b0;
+    parameter cfg_rx2_gearbox_mode_i = 1'b0;
+    parameter cfg_rx2_pcs_8b_dscr_sel_i = 1'b0;
+    parameter cfg_rx2_pcs_align_bypass_i = 1'b0;
+    parameter cfg_rx2_pcs_buffers_bypass_i = 1'b0;
+    parameter cfg_rx2_pcs_buffers_use_cdc_i = 1'b0;
+    parameter cfg_rx2_pcs_bypass_pma_cdc_i = 1'b0;
+    parameter cfg_rx2_pcs_bypass_usr_cdc_i = 1'b0;
+    parameter cfg_rx2_pcs_comma_mask_i = 10'b0000000000;
+    parameter cfg_rx2_pcs_debug_en_i = 1'b0;
+    parameter cfg_rx2_pcs_dec_bypass_i = 1'b0;
+    parameter cfg_rx2_pcs_dscr_bypass_i = 1'b0;
+    parameter cfg_rx2_pcs_el_buff_diff_bef_comp_i = 4'b0000;
+    parameter cfg_rx2_pcs_el_buff_max_comp_i = 4'b0000;
+    parameter cfg_rx2_pcs_el_buff_only_one_skp_i = 1'b0;
+    parameter cfg_rx2_pcs_el_buff_skp_char_0_i = 9'b000000000;
+    parameter cfg_rx2_pcs_el_buff_skp_char_1_i = 9'b000000000;
+    parameter cfg_rx2_pcs_el_buff_skp_char_2_i = 9'b000000000;
+    parameter cfg_rx2_pcs_el_buff_skp_char_3_i = 9'b000000000;
+    parameter cfg_rx2_pcs_el_buff_skp_header_0_i = 9'b000000000;
+    parameter cfg_rx2_pcs_el_buff_skp_header_1_i = 9'b000000000;
+    parameter cfg_rx2_pcs_el_buff_skp_header_2_i = 9'b000000000;
+    parameter cfg_rx2_pcs_el_buff_skp_header_3_i = 9'b000000000;
+    parameter cfg_rx2_pcs_el_buff_skp_header_size_i = 2'b00;
+    parameter cfg_rx2_pcs_el_buff_skp_seq_size_i = 2'b00;
+    parameter cfg_rx2_pcs_fsm_sel_i = 2'b00;
+    parameter cfg_rx2_pcs_fsm_watchdog_en_i = 1'b0;
+    parameter cfg_rx2_pcs_loopback_i = 1'b0;
+    parameter cfg_rx2_pcs_m_comma_en_i = 1'b0;
+    parameter cfg_rx2_pcs_m_comma_val_i = 10'b0000000000;
+    parameter cfg_rx2_pcs_nb_comma_bef_realign_i = 2'b00;
+    parameter cfg_rx2_pcs_p_comma_en_i = 1'b0;
+    parameter cfg_rx2_pcs_p_comma_val_i = 10'b0000000000;
+    parameter cfg_rx2_pcs_polarity_i = 1'b0;
+    parameter cfg_rx2_pcs_protocol_size_i = 1'b0;
+    parameter cfg_rx2_pcs_replace_bypass_i = 1'b0;
+    parameter cfg_rx2_pcs_sync_supported_i = 1'b0;
+    parameter cfg_rx2_pma_cdr_cp_i = 4'b0000;
+    parameter cfg_rx2_pma_clk_pos_i = 1'b0;
+    parameter cfg_rx2_pma_coarse_ppm_i = 3'b000;
+    parameter cfg_rx2_pma_ctrl_term_i = 6'b000000;
+    parameter cfg_rx2_pma_dco_divl_i = 2'b00;
+    parameter cfg_rx2_pma_dco_divm_i = 1'b0;
+    parameter cfg_rx2_pma_dco_divn_i = 2'b00;
+    parameter cfg_rx2_pma_dco_reg_res_i = 2'b00;
+    parameter cfg_rx2_pma_dco_vref_sel_i = 1'b0;
+    parameter cfg_rx2_pma_fine_ppm_i = 3'b000;
+    parameter cfg_rx2_pma_loopback_i = 1'b0;
+    parameter cfg_rx2_pma_m_eye_ppm_i = 3'b000;
+    parameter cfg_rx2_pma_peak_detect_cmd_i = 2'b00;
+    parameter cfg_rx2_pma_peak_detect_on_i = 1'b0;
+    parameter cfg_rx2_pma_pll_cpump_n_i = 3'b000;
+    parameter cfg_rx2_pma_pll_divf_en_n_i = 1'b0;
+    parameter cfg_rx2_pma_pll_divf_i = 2'b00;
+    parameter cfg_rx2_pma_pll_divm_en_n_i = 1'b0;
+    parameter cfg_rx2_pma_pll_divm_i = 2'b00;
+    parameter cfg_rx2_pma_pll_divn_en_n_i = 1'b0;
+    parameter cfg_rx2_pma_pll_divn_i = 1'b0;
+    parameter cfg_rx3_gearbox_en_i = 1'b0;
+    parameter cfg_rx3_gearbox_mode_i = 1'b0;
+    parameter cfg_rx3_pcs_8b_dscr_sel_i = 1'b0;
+    parameter cfg_rx3_pcs_align_bypass_i = 1'b0;
+    parameter cfg_rx3_pcs_buffers_bypass_i = 1'b0;
+    parameter cfg_rx3_pcs_buffers_use_cdc_i = 1'b0;
+    parameter cfg_rx3_pcs_bypass_pma_cdc_i = 1'b0;
+    parameter cfg_rx3_pcs_bypass_usr_cdc_i = 1'b0;
+    parameter cfg_rx3_pcs_comma_mask_i = 10'b0000000000;
+    parameter cfg_rx3_pcs_debug_en_i = 1'b0;
+    parameter cfg_rx3_pcs_dec_bypass_i = 1'b0;
+    parameter cfg_rx3_pcs_dscr_bypass_i = 1'b0;
+    parameter cfg_rx3_pcs_el_buff_diff_bef_comp_i = 4'b0000;
+    parameter cfg_rx3_pcs_el_buff_max_comp_i = 4'b0000;
+    parameter cfg_rx3_pcs_el_buff_only_one_skp_i = 1'b0;
+    parameter cfg_rx3_pcs_el_buff_skp_char_0_i = 9'b000000000;
+    parameter cfg_rx3_pcs_el_buff_skp_char_1_i = 9'b000000000;
+    parameter cfg_rx3_pcs_el_buff_skp_char_2_i = 9'b000000000;
+    parameter cfg_rx3_pcs_el_buff_skp_char_3_i = 9'b000000000;
+    parameter cfg_rx3_pcs_el_buff_skp_header_0_i = 9'b000000000;
+    parameter cfg_rx3_pcs_el_buff_skp_header_1_i = 9'b000000000;
+    parameter cfg_rx3_pcs_el_buff_skp_header_2_i = 9'b000000000;
+    parameter cfg_rx3_pcs_el_buff_skp_header_3_i = 9'b000000000;
+    parameter cfg_rx3_pcs_el_buff_skp_header_size_i = 2'b00;
+    parameter cfg_rx3_pcs_el_buff_skp_seq_size_i = 2'b00;
+    parameter cfg_rx3_pcs_fsm_sel_i = 2'b00;
+    parameter cfg_rx3_pcs_fsm_watchdog_en_i = 1'b0;
+    parameter cfg_rx3_pcs_loopback_i = 1'b0;
+    parameter cfg_rx3_pcs_m_comma_en_i = 1'b0;
+    parameter cfg_rx3_pcs_m_comma_val_i = 10'b0000000000;
+    parameter cfg_rx3_pcs_nb_comma_bef_realign_i = 2'b00;
+    parameter cfg_rx3_pcs_p_comma_en_i = 1'b0;
+    parameter cfg_rx3_pcs_p_comma_val_i = 10'b0000000000;
+    parameter cfg_rx3_pcs_polarity_i = 1'b0;
+    parameter cfg_rx3_pcs_protocol_size_i = 1'b0;
+    parameter cfg_rx3_pcs_replace_bypass_i = 1'b0;
+    parameter cfg_rx3_pcs_sync_supported_i = 1'b0;
+    parameter cfg_rx3_pma_cdr_cp_i = 4'b0000;
+    parameter cfg_rx3_pma_clk_pos_i = 1'b0;
+    parameter cfg_rx3_pma_coarse_ppm_i = 3'b000;
+    parameter cfg_rx3_pma_ctrl_term_i = 6'b000000;
+    parameter cfg_rx3_pma_dco_divl_i = 2'b00;
+    parameter cfg_rx3_pma_dco_divm_i = 1'b0;
+    parameter cfg_rx3_pma_dco_divn_i = 2'b00;
+    parameter cfg_rx3_pma_dco_reg_res_i = 2'b00;
+    parameter cfg_rx3_pma_dco_vref_sel_i = 1'b0;
+    parameter cfg_rx3_pma_fine_ppm_i = 3'b000;
+    parameter cfg_rx3_pma_loopback_i = 1'b0;
+    parameter cfg_rx3_pma_m_eye_ppm_i = 3'b000;
+    parameter cfg_rx3_pma_peak_detect_cmd_i = 2'b00;
+    parameter cfg_rx3_pma_peak_detect_on_i = 1'b0;
+    parameter cfg_rx3_pma_pll_cpump_n_i = 3'b000;
+    parameter cfg_rx3_pma_pll_divf_en_n_i = 1'b0;
+    parameter cfg_rx3_pma_pll_divf_i = 2'b00;
+    parameter cfg_rx3_pma_pll_divm_en_n_i = 1'b0;
+    parameter cfg_rx3_pma_pll_divm_i = 2'b00;
+    parameter cfg_rx3_pma_pll_divn_en_n_i = 1'b0;
+    parameter cfg_rx3_pma_pll_divn_i = 1'b0;
+    parameter cfg_test_mode_i = 2'b00;
+    parameter cfg_tx0_gearbox_en_i = 1'b0;
+    parameter cfg_tx0_gearbox_mode_i = 1'b0;
+    parameter cfg_tx0_pcs_8b_scr_sel_i = 1'b0;
+    parameter cfg_tx0_pcs_bypass_pma_cdc_i = 1'b0;
+    parameter cfg_tx0_pcs_bypass_usr_cdc_i = 1'b0;
+    parameter cfg_tx0_pcs_enc_bypass_i = 1'b0;
+    parameter cfg_tx0_pcs_esistream_fsm_en_i = 1'b0;
+    parameter cfg_tx0_pcs_loopback_i = 1'b0;
+    parameter cfg_tx0_pcs_polarity_i = 1'b0;
+    parameter cfg_tx0_pcs_protocol_size_i = 1'b0;
+    parameter cfg_tx0_pcs_replace_bypass_i = 1'b0;
+    parameter cfg_tx0_pcs_scr_bypass_i = 1'b0;
+    parameter cfg_tx0_pcs_scr_init_i = 17'b00000000000000000;
+    parameter cfg_tx0_pcs_sync_supported_i = 1'b0;
+    parameter cfg_tx0_pma_clk_pos_i = 1'b0;
+    parameter cfg_tx0_pma_loopback_i = 1'b0;
+    parameter cfg_tx1_gearbox_en_i = 1'b0;
+    parameter cfg_tx1_gearbox_mode_i = 1'b0;
+    parameter cfg_tx1_pcs_8b_scr_sel_i = 1'b0;
+    parameter cfg_tx1_pcs_bypass_pma_cdc_i = 1'b0;
+    parameter cfg_tx1_pcs_bypass_usr_cdc_i = 1'b0;
+    parameter cfg_tx1_pcs_enc_bypass_i = 1'b0;
+    parameter cfg_tx1_pcs_esistream_fsm_en_i = 1'b0;
+    parameter cfg_tx1_pcs_loopback_i = 1'b0;
+    parameter cfg_tx1_pcs_polarity_i = 1'b0;
+    parameter cfg_tx1_pcs_protocol_size_i = 1'b0;
+    parameter cfg_tx1_pcs_replace_bypass_i = 1'b0;
+    parameter cfg_tx1_pcs_scr_bypass_i = 1'b0;
+    parameter cfg_tx1_pcs_scr_init_i = 17'b00000000000000000;
+    parameter cfg_tx1_pcs_sync_supported_i = 1'b0;
+    parameter cfg_tx1_pma_clk_pos_i = 1'b0;
+    parameter cfg_tx1_pma_loopback_i = 1'b0;
+    parameter cfg_tx2_gearbox_en_i = 1'b0;
+    parameter cfg_tx2_gearbox_mode_i = 1'b0;
+    parameter cfg_tx2_pcs_8b_scr_sel_i = 1'b0;
+    parameter cfg_tx2_pcs_bypass_pma_cdc_i = 1'b0;
+    parameter cfg_tx2_pcs_bypass_usr_cdc_i = 1'b0;
+    parameter cfg_tx2_pcs_enc_bypass_i = 1'b0;
+    parameter cfg_tx2_pcs_esistream_fsm_en_i = 1'b0;
+    parameter cfg_tx2_pcs_loopback_i = 1'b0;
+    parameter cfg_tx2_pcs_polarity_i = 1'b0;
+    parameter cfg_tx2_pcs_protocol_size_i = 1'b0;
+    parameter cfg_tx2_pcs_replace_bypass_i = 1'b0;
+    parameter cfg_tx2_pcs_scr_bypass_i = 1'b0;
+    parameter cfg_tx2_pcs_scr_init_i = 17'b00000000000000000;
+    parameter cfg_tx2_pcs_sync_supported_i = 1'b0;
+    parameter cfg_tx2_pma_clk_pos_i = 1'b0;
+    parameter cfg_tx2_pma_loopback_i = 1'b0;
+    parameter cfg_tx3_gearbox_en_i = 1'b0;
+    parameter cfg_tx3_gearbox_mode_i = 1'b0;
+    parameter cfg_tx3_pcs_8b_scr_sel_i = 1'b0;
+    parameter cfg_tx3_pcs_bypass_pma_cdc_i = 1'b0;
+    parameter cfg_tx3_pcs_bypass_usr_cdc_i = 1'b0;
+    parameter cfg_tx3_pcs_enc_bypass_i = 1'b0;
+    parameter cfg_tx3_pcs_esistream_fsm_en_i = 1'b0;
+    parameter cfg_tx3_pcs_loopback_i = 1'b0;
+    parameter cfg_tx3_pcs_polarity_i = 1'b0;
+    parameter cfg_tx3_pcs_protocol_size_i = 1'b0;
+    parameter cfg_tx3_pcs_replace_bypass_i = 1'b0;
+    parameter cfg_tx3_pcs_scr_bypass_i = 1'b0;
+    parameter cfg_tx3_pcs_scr_init_i = 17'b00000000000000000;
+    parameter cfg_tx3_pcs_sync_supported_i = 1'b0;
+    parameter cfg_tx3_pma_clk_pos_i = 1'b0;
+    parameter cfg_tx3_pma_loopback_i = 1'b0;
+    parameter location = "";
+    parameter rx_usrclk_use_pcs_clk_2 = 1'b0;
+    parameter tx_usrclk_use_pcs_clk_2 = 1'b0;
+endmodule
+

From 8023f921e3e07c5d9d0ac502a486474cbd6c3c52 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 13 Mar 2024 11:09:02 +0100
Subject: [PATCH 288/499] RAM

---
 techlibs/nanoxplore/Makefile.inc        |   1 +
 techlibs/nanoxplore/cells_bb.v          |  61 -------
 techlibs/nanoxplore/cells_wrap.v        | 201 ++++++++++++++++++++++++
 techlibs/nanoxplore/synth_nanoxplore.cc |   1 +
 4 files changed, 203 insertions(+), 61 deletions(-)
 create mode 100644 techlibs/nanoxplore/cells_wrap.v

diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc
index 37755106bf4..ca37a2d5d92 100644
--- a/techlibs/nanoxplore/Makefile.inc
+++ b/techlibs/nanoxplore/Makefile.inc
@@ -9,6 +9,7 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_m.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_u.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v))
diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index ba7318c7318..fc616521297 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -396,67 +396,6 @@ module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4,
     parameter std_mode = "";
 endmodule
 
-(* blackbox *)
-module NX_RAM_SLOWECC_1K_36_1r1w(ACK, BCK, ACOR, AERR, ACS, AWE, AR, BCS, BWE, BR, AO, AI, AA);
-    input [9:0] AA;
-    input ACK;
-    output ACOR;
-    input ACS;
-    output AERR;
-    input [35:0] AI;
-    output [35:0] AO;
-    input AR;
-    input AWE;
-    input BCK;
-    input BCS;
-    input BR;
-    input BWE;
-    parameter mem_ctxt = "";
-endmodule
-
-(* blackbox *)
-module NX_RAM_WRAP(ACK, ACKD, ACKR, BCK, BCKD, BCKR, ACOR, AERR, BCOR, BERR, ACS, AWE, AR, BCS, BWE, BR, BI, AO, BO, AI, AA
-, BA);
-    input [15:0] AA;
-    input ACK;
-    input ACKD;
-    input ACKR;
-    output ACOR;
-    input ACS;
-    output AERR;
-    input [23:0] AI;
-    output [23:0] AO;
-    input AR;
-    input AWE;
-    input [15:0] BA;
-    input BCK;
-    input BCKD;
-    input BCKR;
-    output BCOR;
-    input BCS;
-    output BERR;
-    input [23:0] BI;
-    output [23:0] BO;
-    input BR;
-    input BWE;
-    parameter mcka_edge = 1'b0;
-    parameter mckb_edge = 1'b0;
-    parameter mem_ctxt = "";
-    parameter pcka_edge = 1'b0;
-    parameter pckb_edge = 1'b0;
-    parameter pipe_ia = 1'b0;
-    parameter pipe_ib = 1'b0;
-    parameter pipe_oa = 1'b0;
-    parameter pipe_ob = 1'b0;
-    parameter raw_config0 = 4'b0000;
-    parameter raw_config1 = 16'b0000000000000000;
-    parameter raw_l_enable = 1'b0;
-    parameter raw_l_extend = 4'b0000;
-    parameter raw_u_enable = 1'b0;
-    parameter raw_u_extend = 8'b00000000;
-    parameter std_mode = "";
-endmodule
-
 (* blackbox *)
 module NX_SER(FCK, SCK, R, IO, DCK, DRL, I, DS, DRA, DRI, DRO, DID);
     input DCK;
diff --git a/techlibs/nanoxplore/cells_wrap.v b/techlibs/nanoxplore/cells_wrap.v
new file mode 100644
index 00000000000..aa328c4c683
--- /dev/null
+++ b/techlibs/nanoxplore/cells_wrap.v
@@ -0,0 +1,201 @@
+module NX_RAM_WRAP(ACK, ACKD, ACKR, BCK, BCKD, BCKR, ACOR, AERR, BCOR, BERR, ACS, AWE, AR, BCS, BWE, BR, BI, AO, BO, AI, AA
+, BA);
+    input [15:0] AA;
+    input ACK;
+    input ACKD;
+    input ACKR;
+    output ACOR;
+    input ACS;
+    output AERR;
+    input [23:0] AI;
+    output [23:0] AO;
+    input AR;
+    input AWE;
+    input [15:0] BA;
+    input BCK;
+    input BCKD;
+    input BCKR;
+    output BCOR;
+    input BCS;
+    output BERR;
+    input [23:0] BI;
+    output [23:0] BO;
+    input BR;
+    input BWE;
+    parameter mcka_edge = 1'b0;
+    parameter mckb_edge = 1'b0;
+    parameter mem_ctxt = "";
+    parameter pcka_edge = 1'b0;
+    parameter pckb_edge = 1'b0;
+    parameter pipe_ia = 1'b0;
+    parameter pipe_ib = 1'b0;
+    parameter pipe_oa = 1'b0;
+    parameter pipe_ob = 1'b0;
+    parameter raw_config0 = 4'b0000;
+    parameter raw_config1 = 16'b0000000000000000;
+    parameter std_mode = "";
+
+  NX_RAM #(
+    .mcka_edge(mcka_edge),
+    .mckb_edge(mckb_edge),
+    .mem_ctxt(mem_ctxt),
+    .pcka_edge(pcka_edge),
+    .pckb_edge(pckb_edge),
+    .pipe_ia(pipe_ia),
+    .pipe_ib(pipe_ib),
+    .pipe_oa(pipe_oa),
+    .pipe_ob(pipe_ob),
+    .raw_config0(raw_config0),
+    .raw_config1(raw_config1),
+    .std_mode(std_mode)
+  ) ram (
+    .AA1(AA[0]),
+    .AA10(AA[9]),
+    .AA11(AA[10]),
+    .AA12(AA[11]),
+    .AA13(AA[12]),
+    .AA14(AA[13]),
+    .AA15(AA[14]),
+    .AA16(AA[15]),
+    .AA2(AA[1]),
+    .AA3(AA[2]),
+    .AA4(AA[3]),
+    .AA5(AA[4]),
+    .AA6(AA[5]),
+    .AA7(AA[6]),
+    .AA8(AA[7]),
+    .AA9(AA[8]),
+    .ACK(ACK),
+    .ACKC(ACK),
+    .ACKD(ACKD),
+    .ACKR(ACKR),
+    .ACOR(ACOR),
+    .ACS(ACS),
+    .AERR(AERR),
+    .AI1(AI[0]),
+    .AI10(AI[9]),
+    .AI11(AI[10]),
+    .AI12(AI[11]),
+    .AI13(AI[12]),
+    .AI14(AI[13]),
+    .AI15(AI[14]),
+    .AI16(AI[15]),
+    .AI17(AI[16]),
+    .AI18(AI[17]),
+    .AI19(AI[18]),
+    .AI2(AI[1]),
+    .AI20(AI[19]),
+    .AI21(AI[20]),
+    .AI22(AI[21]),
+    .AI23(AI[22]),
+    .AI24(AI[23]),
+    .AI3(AI[2]),
+    .AI4(AI[3]),
+    .AI5(AI[4]),
+    .AI6(AI[5]),
+    .AI7(AI[6]),
+    .AI8(AI[7]),
+    .AI9(AI[8]),
+    .AO1(AO[0]),
+    .AO10(AO[9]),
+    .AO11(AO[10]),
+    .AO12(AO[11]),
+    .AO13(AO[12]),
+    .AO14(AO[13]),
+    .AO15(AO[14]),
+    .AO16(AO[15]),
+    .AO17(AO[16]),
+    .AO18(AO[17]),
+    .AO19(AO[18]),
+    .AO2(AO[1]),
+    .AO20(AO[19]),
+    .AO21(AO[20]),
+    .AO22(AO[21]),
+    .AO23(AO[22]),
+    .AO24(AO[23]),
+    .AO3(AO[2]),
+    .AO4(AO[3]),
+    .AO5(AO[4]),
+    .AO6(AO[5]),
+    .AO7(AO[6]),
+    .AO8(AO[7]),
+    .AO9(AO[8]),
+    .AR(AR),
+    .AWE(AWE),
+    .BA1(BA[0]),
+    .BA10(BA[9]),
+    .BA11(BA[10]),
+    .BA12(BA[11]),
+    .BA13(BA[12]),
+    .BA14(BA[13]),
+    .BA15(BA[14]),
+    .BA16(BA[15]),
+    .BA2(BA[1]),
+    .BA3(BA[2]),
+    .BA4(BA[3]),
+    .BA5(BA[4]),
+    .BA6(BA[5]),
+    .BA7(BA[6]),
+    .BA8(BA[7]),
+    .BA9(BA[8]),
+    .BCK(BCK),
+    .BCKC(BCK),
+    .BCKD(BCKD),
+    .BCKR(BCKR),
+    .BCOR(BCOR),
+    .BCS(BCS),
+    .BERR(BERR),
+    .BI1(BI[0]),
+    .BI10(BI[9]),
+    .BI11(BI[10]),
+    .BI12(BI[11]),
+    .BI13(BI[12]),
+    .BI14(BI[13]),
+    .BI15(BI[14]),
+    .BI16(BI[15]),
+    .BI17(BI[16]),
+    .BI18(BI[17]),
+    .BI19(BI[18]),
+    .BI2(BI[1]),
+    .BI20(BI[19]),
+    .BI21(BI[20]),
+    .BI22(BI[21]),
+    .BI23(BI[22]),
+    .BI24(BI[23]),
+    .BI3(BI[2]),
+    .BI4(BI[3]),
+    .BI5(BI[4]),
+    .BI6(BI[5]),
+    .BI7(BI[6]),
+    .BI8(BI[7]),
+    .BI9(BI[8]),
+    .BO1(BO[0]),
+    .BO10(BO[9]),
+    .BO11(BO[10]),
+    .BO12(BO[11]),
+    .BO13(BO[12]),
+    .BO14(BO[13]),
+    .BO15(BO[14]),
+    .BO16(BO[15]),
+    .BO17(BO[16]),
+    .BO18(BO[17]),
+    .BO19(BO[18]),
+    .BO2(BO[1]),
+    .BO20(BO[19]),
+    .BO21(BO[20]),
+    .BO22(BO[21]),
+    .BO23(BO[22]),
+    .BO24(BO[23]),
+    .BO3(BO[2]),
+    .BO4(BO[3]),
+    .BO5(BO[4]),
+    .BO6(BO[5]),
+    .BO7(BO[6]),
+    .BO8(BO[7]),
+    .BO9(BO[8]),
+    .BR(BR),
+    .BWE(BWE)
+  );
+
+endmodule
+
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index 2a8f48729b7..880e712c374 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -207,6 +207,7 @@ struct SynthNanoXplorePass : public ScriptPass
 		if (check_label("begin"))
 		{
 			run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v");
+			run("techmap -map +/nanoxplore/cells_wrap.v");
 			run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 		}

From fa14c600ffcb9ab13bd5793e4755a4ec8dbe3088 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 13 Mar 2024 11:23:33 +0100
Subject: [PATCH 289/499] commented remainder of primitives

---
 techlibs/nanoxplore/cells_bb.v | 168 +++++++++++++++++----------------
 1 file changed, 89 insertions(+), 79 deletions(-)

diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index fc616521297..1955f590b4c 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -1,27 +1,12 @@
-(* blackbox *)
-module NX_BD(I, O);
-    input I;
-    output O;
-    parameter mode = "global_lowskew";
-endmodule
-
-(* blackbox *)
-module NX_BFF(I, O);
-    input I;
-    output O;
-endmodule
-
-(* blackbox *)
-module NX_BFR(I, O);
-    input I;
-    output O;
-    parameter data_inv = 1'b0;
-    parameter iobname = "";
-    parameter location = "";
-    parameter mode = 0;
-    parameter path = 0;
-    parameter ring = 0;
-endmodule
+//(* blackbox *)
+//module NX_LUT(I1, I2, I3, I4, O);
+//    input I1;
+//    input I2;
+//    input I3;
+//    input I4;
+//    output O;
+//    parameter lut_table = 16'b0000000000000000;
+//endmodule
 
 //(* blackbox *)
 //module NX_CY(A1, A2, A3, A4, B1, B2, B3, B4, CI, CO, S1, S2, S3, S4);
@@ -42,37 +27,12 @@ endmodule
 //    parameter add_carry = 0;
 //endmodule
 
+// Bypass mode of NX_GCK_U
 (* blackbox *)
-module NX_DES(FCK, SCK, R, IO, DCK, DRL, DIG, FZ, FLD, FLG, O, DS, DRA, DRI, DRO, DID);
-    input DCK;
-    output [5:0] DID;
-    input DIG;
-    input [5:0] DRA;
-    input [5:0] DRI;
-    input DRL;
-    output [5:0] DRO;
-    input [1:0] DS;
-    input FCK;
-    output FLD;
-    output FLG;
-    input FZ;
-    input IO;
-    output [4:0] O;
-    input R;
-    input SCK;
-    parameter data_size = 5;
-    parameter differential = "";
-    parameter dpath_dynamic = 1'b0;
-    parameter drive = "";
-    parameter inputDelayLine = "";
-    parameter inputSignalSlope = "";
-    parameter location = "";
-    parameter locked = 1'b0;
-    parameter standard = "";
-    parameter termination = "";
-    parameter terminationReference = "";
-    parameter turbo = "";
-    parameter weakTermination = "";
+module NX_BD(I, O);
+    input I;
+    output O;
+    parameter mode = "global_lowskew";
 endmodule
 
 //(* blackbox *)
@@ -90,6 +50,14 @@ endmodule
 //    parameter dff_type = 1'b0;
 //endmodule
 
+// Special mode of NX_DFF
+(* blackbox *)
+module NX_BFF(I, O);
+    input I;
+    output O;
+endmodule
+
+
 (* blackbox *)
 module NX_DFR(I, CK, L, R, O);
     input CK;
@@ -110,12 +78,17 @@ module NX_DFR(I, CK, L, R, O);
     parameter ring = 0;
 endmodule
 
+// Special mode of NX_DFR
 (* blackbox *)
-module NX_ECC(CKD, CHK, COR, ERR);
-    input CHK;
-    input CKD;
-    output COR;
-    output ERR;
+module NX_BFR(I, O);
+    input I;
+    output O;
+    parameter data_inv = 1'b0;
+    parameter iobname = "";
+    parameter location = "";
+    parameter mode = 0;
+    parameter path = 0;
+    parameter ring = 0;
 endmodule
 
 (* blackbox *)
@@ -203,26 +176,6 @@ module NX_IOB_O(I, C, T, IO);
     parameter weakTermination = "";
 endmodule
 
-(* blackbox *)
-module NX_IOM_BIN2GRP(GS, DS, GVON, GVIN, GVDN, PA, LA);
-    input [1:0] DS;
-    input GS;
-    output [2:0] GVDN;
-    output [2:0] GVIN;
-    output [2:0] GVON;
-    input [5:0] LA;
-    output [3:0] PA;
-endmodule
-
-//(* blackbox *)
-//module NX_LUT(I1, I2, I3, I4, O);
-//    input I1;
-//    input I2;
-//    input I3;
-//    input I4;
-//    output O;
-//    parameter lut_table = 16'b0000000000000000;
-//endmodule
 
 (* blackbox *)
 module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13
@@ -396,6 +349,28 @@ module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4,
     parameter std_mode = "";
 endmodule
 
+// NX_RAM related
+(* blackbox *)
+module NX_ECC(CKD, CHK, COR, ERR);
+    input CHK;
+    input CKD;
+    output COR;
+    output ERR;
+endmodule
+
+//TODO
+(* blackbox *)
+module NX_IOM_BIN2GRP(GS, DS, GVON, GVIN, GVDN, PA, LA);
+    input [1:0] DS;
+    input GS;
+    output [2:0] GVDN;
+    output [2:0] GVIN;
+    output [2:0] GVON;
+    input [5:0] LA;
+    output [3:0] PA;
+endmodule
+
+//TODO
 (* blackbox *)
 module NX_SER(FCK, SCK, R, IO, DCK, DRL, I, DS, DRA, DRI, DRO, DID);
     input DCK;
@@ -422,6 +397,41 @@ module NX_SER(FCK, SCK, R, IO, DCK, DRL, I, DS, DRA, DRI, DRO, DID);
     parameter standard = "";
 endmodule
 
+//TODO
+(* blackbox *)
+module NX_DES(FCK, SCK, R, IO, DCK, DRL, DIG, FZ, FLD, FLG, O, DS, DRA, DRI, DRO, DID);
+    input DCK;
+    output [5:0] DID;
+    input DIG;
+    input [5:0] DRA;
+    input [5:0] DRI;
+    input DRL;
+    output [5:0] DRO;
+    input [1:0] DS;
+    input FCK;
+    output FLD;
+    output FLG;
+    input FZ;
+    input IO;
+    output [4:0] O;
+    input R;
+    input SCK;
+    parameter data_size = 5;
+    parameter differential = "";
+    parameter dpath_dynamic = 1'b0;
+    parameter drive = "";
+    parameter inputDelayLine = "";
+    parameter inputSignalSlope = "";
+    parameter location = "";
+    parameter locked = 1'b0;
+    parameter standard = "";
+    parameter termination = "";
+    parameter terminationReference = "";
+    parameter turbo = "";
+    parameter weakTermination = "";
+endmodule
+
+//TODO
 (* blackbox *)
 module NX_SERDES(FCK, SCK, RTX, RRX, CI, CCK, CL, CR, IO, DCK, DRL, DIG, FZ, FLD, FLG, I, O, DS, DRA, DRI, DRO
 , DID);

From 370517b1e6c4872742a7c62564320ad556b356f8 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 13 Mar 2024 12:52:40 +0100
Subject: [PATCH 290/499] IO

---
 techlibs/nanoxplore/cells_bb.v  | 86 ------------------------------
 techlibs/nanoxplore/cells_sim.v | 94 +++++++++++++++++++++++++++++++++
 2 files changed, 94 insertions(+), 86 deletions(-)

diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index 1955f590b4c..42953b6b202 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -91,92 +91,6 @@ module NX_BFR(I, O);
     parameter ring = 0;
 endmodule
 
-(* blackbox *)
-module NX_IOB(I, C, T, O, IO);
-    input C;
-    input I;
-    inout IO;
-    output O;
-    input T;
-    parameter differential = "";
-    parameter drive = "";
-    parameter dynDrive = "";
-    parameter dynInput = "";
-    parameter dynTerm = "";
-    parameter extra = 3;
-    parameter inputDelayLine = "";
-    parameter inputDelayOn = "";
-    parameter inputSignalSlope = "";
-    parameter location = "";
-    parameter locked = 1'b0;
-    parameter outputCapacity = "";
-    parameter outputDelayLine = "";
-    parameter outputDelayOn = "";
-    parameter slewRate = "";
-    parameter standard = "";
-    parameter termination = "";
-    parameter terminationReference = "";
-    parameter turbo = "";
-    parameter weakTermination = "";
-endmodule
-
-(* blackbox *)
-module NX_IOB_I(C, T, IO, O);
-    input C;
-    input IO;
-    output O;
-    input T;
-    parameter differential = "";
-    parameter drive = "";
-    parameter dynDrive = "";
-    parameter dynInput = "";
-    parameter dynTerm = "";
-    parameter extra = 1;
-    parameter inputDelayLine = "";
-    parameter inputDelayOn = "";
-    parameter inputSignalSlope = "";
-    parameter location = "";
-    parameter locked = 1'b0;
-    parameter outputCapacity = "";
-    parameter outputDelayLine = "";
-    parameter outputDelayOn = "";
-    parameter slewRate = "";
-    parameter standard = "";
-    parameter termination = "";
-    parameter terminationReference = "";
-    parameter turbo = "";
-    parameter weakTermination = "";
-endmodule
-
-(* blackbox *)
-module NX_IOB_O(I, C, T, IO);
-    input C;
-    input I;
-    output IO;
-    input T;
-    parameter differential = "";
-    parameter drive = "";
-    parameter dynDrive = "";
-    parameter dynInput = "";
-    parameter dynTerm = "";
-    parameter extra = 2;
-    parameter inputDelayLine = "";
-    parameter inputDelayOn = "";
-    parameter inputSignalSlope = "";
-    parameter location = "";
-    parameter locked = 1'b0;
-    parameter outputCapacity = "";
-    parameter outputDelayLine = "";
-    parameter outputDelayOn = "";
-    parameter slewRate = "";
-    parameter standard = "";
-    parameter termination = "";
-    parameter terminationReference = "";
-    parameter turbo = "";
-    parameter weakTermination = "";
-endmodule
-
-
 (* blackbox *)
 module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13
 , AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10
diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v
index 35b1574ba2a..88ec78b5ce1 100644
--- a/techlibs/nanoxplore/cells_sim.v
+++ b/techlibs/nanoxplore/cells_sim.v
@@ -91,3 +91,97 @@ always @(posedge clock)
 assign O = mem[RA];
 
 endmodule
+
+module NX_IOB(I, C, T, O, IO);
+    input C;
+    input I;
+	(* iopad_external_pin *)
+    inout IO;
+    output O;
+    input T;
+    parameter differential = "";
+    parameter drive = "";
+    parameter dynDrive = "";
+    parameter dynInput = "";
+    parameter dynTerm = "";
+    parameter extra = 3;
+    parameter inputDelayLine = "";
+    parameter inputDelayOn = "";
+    parameter inputSignalSlope = "";
+    parameter location = "";
+    parameter locked = 1'b0;
+    parameter outputCapacity = "";
+    parameter outputDelayLine = "";
+    parameter outputDelayOn = "";
+    parameter slewRate = "";
+    parameter standard = "";
+    parameter termination = "";
+    parameter terminationReference = "";
+    parameter turbo = "";
+    parameter weakTermination = "";
+
+	assign O = IO;
+	assign IO = C ? I : 1'bz;
+endmodule
+
+module NX_IOB_I(C, T, IO, O);
+    input C;
+	(* iopad_external_pin *)
+    input IO;
+    output O;
+    input T;
+    parameter differential = "";
+    parameter drive = "";
+    parameter dynDrive = "";
+    parameter dynInput = "";
+    parameter dynTerm = "";
+    parameter extra = 1;
+    parameter inputDelayLine = "";
+    parameter inputDelayOn = "";
+    parameter inputSignalSlope = "";
+    parameter location = "";
+    parameter locked = 1'b0;
+    parameter outputCapacity = "";
+    parameter outputDelayLine = "";
+    parameter outputDelayOn = "";
+    parameter slewRate = "";
+    parameter standard = "";
+    parameter termination = "";
+    parameter terminationReference = "";
+    parameter turbo = "";
+    parameter weakTermination = "";
+
+	assign O = IO;
+endmodule
+
+module NX_IOB_O(I, C, T, IO);
+    input C;
+    input I;
+	(* iopad_external_pin *)
+    output IO;
+    input T;
+    parameter differential = "";
+    parameter drive = "";
+    parameter dynDrive = "";
+    parameter dynInput = "";
+    parameter dynTerm = "";
+    parameter extra = 2;
+    parameter inputDelayLine = "";
+    parameter inputDelayOn = "";
+    parameter inputSignalSlope = "";
+    parameter location = "";
+    parameter locked = 1'b0;
+    parameter outputCapacity = "";
+    parameter outputDelayLine = "";
+    parameter outputDelayOn = "";
+    parameter slewRate = "";
+    parameter standard = "";
+    parameter termination = "";
+    parameter terminationReference = "";
+    parameter turbo = "";
+    parameter weakTermination = "";
+
+	assign IO = C ? I : 1'bz;
+endmodule
+
+

From a5bfb23b472966ccd55f526651c4c2b5a87db99d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 13 Mar 2024 18:19:41 +0100
Subject: [PATCH 291/499] start cleaning rams

---
 techlibs/nanoxplore/Makefile.inc              |  5 ++-
 techlibs/nanoxplore/brams.txt                 | 26 +++++++++++++
 techlibs/nanoxplore/brams_map.v               | 32 ++++++++++++++++
 techlibs/nanoxplore/cells_map.v               | 12 ------
 techlibs/nanoxplore/rf_rams_map_u.v           | 12 ++++++
 .../nanoxplore/{drams.txt => rf_rams_u.txt}   |  0
 techlibs/nanoxplore/synth_nanoxplore.cc       | 37 +++++++++++++------
 tests/arch/nanoxplore/lutram.ys               |  4 +-
 8 files changed, 101 insertions(+), 27 deletions(-)
 create mode 100644 techlibs/nanoxplore/brams.txt
 create mode 100644 techlibs/nanoxplore/brams_map.v
 create mode 100644 techlibs/nanoxplore/rf_rams_map_u.v
 rename techlibs/nanoxplore/{drams.txt => rf_rams_u.txt} (100%)

diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc
index ca37a2d5d92..40e730cbee3 100644
--- a/techlibs/nanoxplore/Makefile.inc
+++ b/techlibs/nanoxplore/Makefile.inc
@@ -3,6 +3,8 @@ OBJS += techlibs/nanoxplore/synth_nanoxplore.o
 
 # Techmap
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_map.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams.txt))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_l.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_m.v))
@@ -13,5 +15,6 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v))
-$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/drams.txt))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_u.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_u.txt))
diff --git a/techlibs/nanoxplore/brams.txt b/techlibs/nanoxplore/brams.txt
new file mode 100644
index 00000000000..bc3a1722e67
--- /dev/null
+++ b/techlibs/nanoxplore/brams.txt
@@ -0,0 +1,26 @@
+ram block $__NX_RAM_ {
+	abits 13;
+	widths 1 2 4 9 per_port;
+	cost 64;
+	init no_undef;
+	port srsw "A" "B" {
+		clock anyedge;
+		clken;
+		portoption "WRITEMODE" "NORMAL" {
+			rdwr no_change;
+		}
+		portoption "WRITEMODE" "WRITETHROUGH" {
+			rdwr new;
+		}
+		portoption "WRITEMODE" "READBEFOREWRITE" {
+			rdwr old;
+		}
+		option "RESETMODE" "SYNC" {
+			rdsrst zero ungated block_wr;
+		}
+		option "RESETMODE" "ASYNC" {
+			rdarst zero;
+		}
+		rdinit zero;
+	}
+}
\ No newline at end of file
diff --git a/techlibs/nanoxplore/brams_map.v b/techlibs/nanoxplore/brams_map.v
new file mode 100644
index 00000000000..04b6134c3cb
--- /dev/null
+++ b/techlibs/nanoxplore/brams_map.v
@@ -0,0 +1,32 @@
+module $__NX_RAM_ (...);
+
+parameter INIT = 0;
+parameter OPTION_RESETMODE = "SYNC";
+
+parameter PORT_A_WIDTH = 9;
+parameter PORT_A_CLK_POL = 1;
+parameter PORT_A_OPTION_WRITEMODE = "NORMAL";
+
+input PORT_A_CLK;
+input PORT_A_CLK_EN;
+input PORT_A_WR_EN;
+input PORT_A_RD_SRST;
+input PORT_A_RD_ARST;
+input [12:0] PORT_A_ADDR;
+input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
+output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
+
+parameter PORT_B_WIDTH = 9;
+parameter PORT_B_CLK_POL = 1;
+parameter PORT_B_OPTION_WRITEMODE = "NORMAL";
+
+input PORT_B_CLK;
+input PORT_B_CLK_EN;
+input PORT_B_WR_EN;
+input PORT_B_RD_SRST;
+input PORT_B_RD_ARST;
+input [12:0] PORT_B_ADDR;
+input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
+output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
+
+endmodule
\ No newline at end of file
diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v
index 54f2414c849..75e7140aae5 100644
--- a/techlibs/nanoxplore/cells_map.v
+++ b/techlibs/nanoxplore/cells_map.v
@@ -70,15 +70,3 @@ module \$_SDFF_NP1_ (input D, C, R, output Q);
   wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
   NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
 endmodule
-
-module $__NX_XRFB_64x18_ (input PORT_W_CLK, input [5:0] PORT_W_ADDR, PORT_R_ADDR, input [17:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [17:0] PORT_R_RD_DATA);
-  parameter INIT = 1152'bx;
-  parameter PORT_W_CLK_POL = 1'b1;
-  NX_XRFB_64x18 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA));
-endmodule
-
-module $__NX_XRFB_32x36_ (input PORT_W_CLK, input [4:0] PORT_W_ADDR, PORT_R_ADDR, input [35:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [35:0] PORT_R_RD_DATA);
-  parameter INIT = 1152'bx;
-  parameter PORT_W_CLK_POL = 1'b1;
-  NX_XRFB_32x36 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA));
-endmodule
diff --git a/techlibs/nanoxplore/rf_rams_map_u.v b/techlibs/nanoxplore/rf_rams_map_u.v
new file mode 100644
index 00000000000..397dd0fcdf3
--- /dev/null
+++ b/techlibs/nanoxplore/rf_rams_map_u.v
@@ -0,0 +1,12 @@
+
+module $__NX_XRFB_64x18_ (input PORT_W_CLK, input [5:0] PORT_W_ADDR, PORT_R_ADDR, input [17:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [17:0] PORT_R_RD_DATA);
+  parameter INIT = 1152'bx;
+  parameter PORT_W_CLK_POL = 1'b1;
+  NX_XRFB_64x18 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA));
+endmodule
+
+module $__NX_XRFB_32x36_ (input PORT_W_CLK, input [4:0] PORT_W_ADDR, PORT_R_ADDR, input [35:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [35:0] PORT_R_RD_DATA);
+  parameter INIT = 1152'bx;
+  parameter PORT_W_CLK_POL = 1'b1;
+  NX_XRFB_32x36 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA));
+endmodule
diff --git a/techlibs/nanoxplore/drams.txt b/techlibs/nanoxplore/rf_rams_u.txt
similarity index 100%
rename from techlibs/nanoxplore/drams.txt
rename to techlibs/nanoxplore/rf_rams_u.txt
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index 880e712c374..f6e507e6221 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -73,11 +73,11 @@ struct SynthNanoXplorePass : public ScriptPass
 		log("    -nocy\n");
 		log("        do not map adders to CY cells\n");
 		log("\n");
-		log("    -nolutram\n");
-		log("        do not use LUT RAM cells in output netlist\n");
+		log("    -norfram\n");
+		log("        do not use Register File RAM cells in output netlist\n");
 		log("\n");
 		log("    -nobram\n");
-		log("        do not use block RAM cells in output netlist\n");
+		log("        do not use block NX_RAM cells in output netlist\n");
 		log("\n");
 		log("    -nodsp\n");
 		log("        do not map multipliers to NX_DSP cells\n");
@@ -92,8 +92,8 @@ struct SynthNanoXplorePass : public ScriptPass
 	}
 
 	string top_opt, json_file, family;
-	bool flatten, abc9, nocy, nolutram, nobram, nodsp, iopad;
-	std::string postfix;
+	bool flatten, abc9, nocy, norfram, nobram, nodsp, iopad;
+	std::string postfix, rf_postfix;
 
 	void clear_flags() override
 	{
@@ -103,11 +103,12 @@ struct SynthNanoXplorePass : public ScriptPass
 		flatten = true;
 		abc9 = false;
 		nocy = false;
-		nolutram = false;
+		norfram = false;
 		nobram = false;
 		nodsp = false;
 		iopad = false;
 		postfix = "";
+		rf_postfix = "";
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -154,8 +155,8 @@ struct SynthNanoXplorePass : public ScriptPass
 				nocy = true;
 				continue;
 			}
-			if (args[argidx] == "-nolutram") {
-				nolutram = true;
+			if (args[argidx] == "-norfram") {
+				norfram = true;
 				continue;
 			}
 			if (args[argidx] == "-nobram") {
@@ -177,17 +178,20 @@ struct SynthNanoXplorePass : public ScriptPass
 		if (family.empty()) {
 			//log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n");
 			family = "ultra";
-			postfix = "_u";
 		}
 
 		if (family == "ultra") {
 			postfix = "_u";
+			rf_postfix = "_u";
 		} else if (family == "u300") {
 			postfix = "_u";
+			rf_postfix = "_u";
 		} else if (family == "medium") {
 			postfix = "_m";
+			rf_postfix = "_l";
 		} else if (family == "large") {
 			postfix = "_l";
+			rf_postfix = "_l";
 		} else 
 			log_cmd_error("Invalid NanoXplore -family setting: '%s'.\n", family.c_str());
 
@@ -238,9 +242,18 @@ struct SynthNanoXplorePass : public ScriptPass
 			run("opt_clean");
 		}
 
-		if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) {
-			run("memory_libmap -lib +/nanoxplore/drams.txt");
-			run("techmap -map +/nanoxplore/cells_map.v t:$__NX_XRFB_32x36_ t:$__NX_XRFB_64x18_");
+		if (check_label("map_ram"))
+		{
+			std::string args = "";
+			if (nobram)
+				args += " -no-auto-block";
+			if (norfram)
+				args += " -no-auto-distributed";
+			if (help_mode)
+				args += " [-no-auto-block] [-no-auto-distributed]";
+			run("memory_libmap -lib +/nanoxplore/rf_rams"+  rf_postfix+ ".txt -lib +/nanoxplore/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -norfram)");
+			run("techmap -map +/nanoxplore/rf_rams_map"+  rf_postfix+ ".v -map +/nanoxplore/brams_map.v");
+			run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v t:NX_XRFB* t:NX_RFB*");
 		}
 
 		if (check_label("map_ffram"))
diff --git a/tests/arch/nanoxplore/lutram.ys b/tests/arch/nanoxplore/lutram.ys
index 669cb000757..9809da928d0 100644
--- a/tests/arch/nanoxplore/lutram.ys
+++ b/tests/arch/nanoxplore/lutram.ys
@@ -2,7 +2,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r
 synth_nanoxplore
 cd lutram_1w1r
-select -assert-count 1 t:NX_XRFB_64x18
+select -assert-count 1 t:NX_RFB_U
 select -assert-count 8 t:NX_DFF
-select -assert-none t:NX_XRFB_64x18 t:NX_DFF %% t:* %D
+select -assert-none t:NX_RFB_U t:NX_DFF %% t:* %D
 

From 474ed28aee995131f8ece02090c648d931054055 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 14 Mar 2024 08:40:14 +0100
Subject: [PATCH 292/499] added no-rw-check, and new rfb models

---
 techlibs/nanoxplore/Makefile.inc        |  6 +++-
 techlibs/nanoxplore/rf_rams_l.txt       | 15 ++++++++
 techlibs/nanoxplore/rf_rams_m.txt       | 15 ++++++++
 techlibs/nanoxplore/rf_rams_map_l.v     | 30 ++++++++++++++++
 techlibs/nanoxplore/rf_rams_map_m.v     | 30 ++++++++++++++++
 techlibs/nanoxplore/rf_rams_map_u.v     | 46 ++++++++++++++++++++++---
 techlibs/nanoxplore/synth_nanoxplore.cc | 31 +++++++++++------
 7 files changed, 158 insertions(+), 15 deletions(-)
 create mode 100644 techlibs/nanoxplore/rf_rams_l.txt
 create mode 100644 techlibs/nanoxplore/rf_rams_m.txt
 create mode 100644 techlibs/nanoxplore/rf_rams_map_l.v
 create mode 100644 techlibs/nanoxplore/rf_rams_map_m.v

diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc
index 40e730cbee3..cae2817b36c 100644
--- a/techlibs/nanoxplore/Makefile.inc
+++ b/techlibs/nanoxplore/Makefile.inc
@@ -16,5 +16,9 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v))
-$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_u.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_l.txt))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_m.txt))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_u.txt))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_l.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_m.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_u.v))
diff --git a/techlibs/nanoxplore/rf_rams_l.txt b/techlibs/nanoxplore/rf_rams_l.txt
new file mode 100644
index 00000000000..112655184df
--- /dev/null
+++ b/techlibs/nanoxplore/rf_rams_l.txt
@@ -0,0 +1,15 @@
+ram distributed $__NX_RFB_L_ {
+    abits 6;
+    width 16;
+    cost 10;
+    init no_undef;
+    prune_rom;
+
+    port sw "W" {
+        clock anyedge;
+    }
+    port sr "R" {
+        clock anyedge;
+        rden;
+    }
+}
diff --git a/techlibs/nanoxplore/rf_rams_m.txt b/techlibs/nanoxplore/rf_rams_m.txt
new file mode 100644
index 00000000000..d872405a3dc
--- /dev/null
+++ b/techlibs/nanoxplore/rf_rams_m.txt
@@ -0,0 +1,15 @@
+ram distributed $__NX_RFB_M_ {
+    abits 6;
+    width 16;
+    cost 10;
+    init no_undef;
+    prune_rom;
+
+    port sw "W" {
+        clock anyedge;
+    }
+    port sr "R" {
+        clock anyedge;
+        rden;
+    }
+}
diff --git a/techlibs/nanoxplore/rf_rams_map_l.v b/techlibs/nanoxplore/rf_rams_map_l.v
new file mode 100644
index 00000000000..e529ce1e1fa
--- /dev/null
+++ b/techlibs/nanoxplore/rf_rams_map_l.v
@@ -0,0 +1,30 @@
+module $__NX_RFB_L_ (
+  input PORT_W_CLK,
+  input PORT_W_WR_EN,
+  input [5:0] PORT_W_ADDR,
+  input [15:0] PORT_W_WR_DATA, 
+  input PORT_R_CLK,
+  input PORT_R_RD_EN,
+  input [5:0] PORT_R_ADDR,
+  output [15:0] PORT_R_RD_DATA,
+);
+  parameter INIT = 1152'bx;
+  parameter PORT_W_CLK_POL = 1'b1;
+  parameter PORT_R_CLK_POL = 1'b1;
+
+  NX_RFB_L_WRAP #(
+    .mode(0),
+    .mem_ctxt(INIT),
+    .rck_edge(~PORT_R_CLK_POL),
+    .wck_edge(~PORT_W_CLK_POL)
+  ) _TECHMAP_REPLACE_ (
+    .RCK(PORT_R_CLK),
+    .WCK(PORT_W_CLK),
+    .I(PORT_W_WR_DATA),
+    .RA(PORT_R_ADDR),
+    .WA(PORT_W_ADDR),
+    .RE(PORT_R_RD_EN),
+    .WE(PORT_W_WR_EN),
+    .O(PORT_R_RD_DATA)
+  );
+endmodule
diff --git a/techlibs/nanoxplore/rf_rams_map_m.v b/techlibs/nanoxplore/rf_rams_map_m.v
new file mode 100644
index 00000000000..a64dc3388ce
--- /dev/null
+++ b/techlibs/nanoxplore/rf_rams_map_m.v
@@ -0,0 +1,30 @@
+module $__NX_RFB_M_ (
+  input PORT_W_CLK,
+  input PORT_W_WR_EN,
+  input [5:0] PORT_W_ADDR,
+  input [15:0] PORT_W_WR_DATA, 
+  input PORT_R_CLK,
+  input PORT_R_RD_EN,
+  input [5:0] PORT_R_ADDR,
+  output [15:0] PORT_R_RD_DATA,
+);
+  parameter INIT = 1152'bx;
+  parameter PORT_W_CLK_POL = 1'b1;
+  parameter PORT_R_CLK_POL = 1'b1;
+
+  NX_RFB_M_WRAP #(
+    .mode(0),
+    .mem_ctxt(INIT),
+    .rck_edge(~PORT_R_CLK_POL),
+    .wck_edge(~PORT_W_CLK_POL)
+  ) _TECHMAP_REPLACE_ (
+    .RCK(PORT_R_CLK),
+    .WCK(PORT_W_CLK),
+    .I(PORT_W_WR_DATA),
+    .RA(PORT_R_ADDR),
+    .WA(PORT_W_ADDR),
+    .RE(PORT_R_RD_EN),
+    .WE(PORT_W_WR_EN),
+    .O(PORT_R_RD_DATA)
+  );
+endmodule
diff --git a/techlibs/nanoxplore/rf_rams_map_u.v b/techlibs/nanoxplore/rf_rams_map_u.v
index 397dd0fcdf3..94d5df09795 100644
--- a/techlibs/nanoxplore/rf_rams_map_u.v
+++ b/techlibs/nanoxplore/rf_rams_map_u.v
@@ -1,12 +1,50 @@
 
-module $__NX_XRFB_64x18_ (input PORT_W_CLK, input [5:0] PORT_W_ADDR, PORT_R_ADDR, input [17:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [17:0] PORT_R_RD_DATA);
+module $__NX_XRFB_64x18_ (
+  input PORT_W_CLK,
+  input [5:0] PORT_W_ADDR,
+  input [5:0] PORT_R_ADDR,
+  input [17:0] PORT_W_WR_DATA,
+  input PORT_W_WR_EN,
+  output [17:0] PORT_R_RD_DATA
+);
   parameter INIT = 1152'bx;
   parameter PORT_W_CLK_POL = 1'b1;
-  NX_XRFB_64x18 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA));
+  
+  NX_XRFB_64x18 #(
+    .mem_ctxt(INIT),
+    .wck_edge(~PORT_W_CLK_POL)
+  ) _TECHMAP_REPLACE_ (
+    .WCK(PORT_W_CLK),
+    .I(PORT_W_WR_DATA),
+    .RA(PORT_R_ADDR),
+    .WA(PORT_W_ADDR),
+    .WE(PORT_W_WR_EN),
+    .WEA(1'b1),
+    .O(PORT_R_RD_DATA)
+  );
 endmodule
 
-module $__NX_XRFB_32x36_ (input PORT_W_CLK, input [4:0] PORT_W_ADDR, PORT_R_ADDR, input [35:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [35:0] PORT_R_RD_DATA);
+module $__NX_XRFB_32x36_ (
+  input PORT_W_CLK,
+  input [4:0] PORT_W_ADDR,
+  input [4:0] PORT_R_ADDR,
+  input [35:0] PORT_W_WR_DATA,
+  input PORT_W_WR_EN,
+  output [35:0] PORT_R_RD_DATA
+);
   parameter INIT = 1152'bx;
   parameter PORT_W_CLK_POL = 1'b1;
-  NX_XRFB_32x36 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA));
+
+  NX_XRFB_32x36 #(
+    .mem_ctxt(INIT),
+    .wck_edge(~PORT_W_CLK_POL)
+  ) _TECHMAP_REPLACE_ (
+    .WCK(PORT_W_CLK),
+    .I(PORT_W_WR_DATA),
+    .RA(PORT_R_ADDR),
+    .WA(PORT_W_ADDR),
+    .WE(PORT_W_WR_EN),
+    .WEA(1'b1),
+    .O(PORT_R_RD_DATA)
+  );
 endmodule
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index f6e507e6221..23a2af27868 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -85,6 +85,11 @@ struct SynthNanoXplorePass : public ScriptPass
 		log("    -iopad\n");
 		log("       insert IO buffers\n");
 		log("\n");
+		log("    -no-rw-check\n");
+		log("        marks all recognized read ports as \"return don't-care value on\n");
+		log("        read/write collision\" (same result as setting the no_rw_check\n");
+		log("        attribute on all memories).\n");
+		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
 		help_script();
@@ -92,8 +97,8 @@ struct SynthNanoXplorePass : public ScriptPass
 	}
 
 	string top_opt, json_file, family;
-	bool flatten, abc9, nocy, norfram, nobram, nodsp, iopad;
-	std::string postfix, rf_postfix;
+	bool flatten, abc9, nocy, norfram, nobram, nodsp, iopad, no_rw_check;
+	std::string postfix;
 
 	void clear_flags() override
 	{
@@ -107,8 +112,8 @@ struct SynthNanoXplorePass : public ScriptPass
 		nobram = false;
 		nodsp = false;
 		iopad = false;
+		no_rw_check = false;
 		postfix = "";
-		rf_postfix = "";
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -171,6 +176,10 @@ struct SynthNanoXplorePass : public ScriptPass
 				iopad = true;
 				continue;
 			}
+			if (args[argidx] == "-no-rw-check") {
+				no_rw_check = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -182,16 +191,12 @@ struct SynthNanoXplorePass : public ScriptPass
 
 		if (family == "ultra") {
 			postfix = "_u";
-			rf_postfix = "_u";
 		} else if (family == "u300") {
 			postfix = "_u";
-			rf_postfix = "_u";
 		} else if (family == "medium") {
 			postfix = "_m";
-			rf_postfix = "_l";
 		} else if (family == "large") {
 			postfix = "_l";
-			rf_postfix = "_l";
 		} else 
 			log_cmd_error("Invalid NanoXplore -family setting: '%s'.\n", family.c_str());
 
@@ -208,6 +213,12 @@ struct SynthNanoXplorePass : public ScriptPass
 
 	void script() override
 	{
+		std::string no_rw_check_opt = "";
+		if (no_rw_check)
+			no_rw_check_opt = " -no-rw-check";
+		if (help_mode)
+			no_rw_check_opt = " [-no-rw-check]";
+
 		if (check_label("begin"))
 		{
 			run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v");
@@ -238,7 +249,7 @@ struct SynthNanoXplorePass : public ScriptPass
 			run("opt_clean");
 			run("alumacc");
 			run("opt");
-			run("memory -nomap");
+			run("memory -nomap" + no_rw_check_opt);
 			run("opt_clean");
 		}
 
@@ -251,8 +262,8 @@ struct SynthNanoXplorePass : public ScriptPass
 				args += " -no-auto-distributed";
 			if (help_mode)
 				args += " [-no-auto-block] [-no-auto-distributed]";
-			run("memory_libmap -lib +/nanoxplore/rf_rams"+  rf_postfix+ ".txt -lib +/nanoxplore/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -norfram)");
-			run("techmap -map +/nanoxplore/rf_rams_map"+  rf_postfix+ ".v -map +/nanoxplore/brams_map.v");
+			run("memory_libmap -lib +/nanoxplore/rf_rams"+ postfix + ".txt -lib +/nanoxplore/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -norfram)");
+			run("techmap -map +/nanoxplore/rf_rams_map"+ postfix + ".v -map +/nanoxplore/brams_map.v");
 			run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v t:NX_XRFB* t:NX_RFB*");
 		}
 

From da6a62f3a0f29898b105d675d5880a52d8ff0c12 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 18 Mar 2024 13:27:33 +0100
Subject: [PATCH 293/499] Initial carry chain handling pass

---
 techlibs/nanoxplore/Makefile.inc        |   1 +
 techlibs/nanoxplore/arith_map.v         |  75 +++++------
 techlibs/nanoxplore/cells_sim.v         |  14 ++-
 techlibs/nanoxplore/nx_carry.cc         | 158 ++++++++++++++++++++++++
 techlibs/nanoxplore/synth_nanoxplore.cc |   4 +-
 5 files changed, 214 insertions(+), 38 deletions(-)
 create mode 100644 techlibs/nanoxplore/nx_carry.cc

diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc
index cae2817b36c..f6606639e31 100644
--- a/techlibs/nanoxplore/Makefile.inc
+++ b/techlibs/nanoxplore/Makefile.inc
@@ -1,5 +1,6 @@
 
 OBJS += techlibs/nanoxplore/synth_nanoxplore.o
+OBJS += techlibs/nanoxplore/nx_carry.o
 
 # Techmap
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v))
diff --git a/techlibs/nanoxplore/arith_map.v b/techlibs/nanoxplore/arith_map.v
index 69e83b68ccd..7b4534b8350 100644
--- a/techlibs/nanoxplore/arith_map.v
+++ b/techlibs/nanoxplore/arith_map.v
@@ -1,4 +1,21 @@
-`default_nettype none
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Miodrag Milanovic <micko@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
 
 (* techmap_celltype = "$alu" *)
 module _80_nx_cy_alu (A, B, CI, BI, X, Y, CO);
@@ -26,46 +43,32 @@ module _80_nx_cy_alu (A, B, CI, BI, X, Y, CO);
 	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 
-	function integer round_up4;
-		input integer N;
-		begin
-			round_up4 = ((N + 3) / 4) * 4;
-		end
-	endfunction
-
-	localparam Y_WIDTH4 = round_up4(Y_WIDTH);
-
-	(* force_downto *)
-	wire [Y_WIDTH4-1:0] AA = A_buf;
-	(* force_downto *)
-	wire [Y_WIDTH4-1:0] BB = BI ? ~B_buf : B_buf;
-	(* force_downto *)
-	wire [Y_WIDTH4-1:0] BX = B_buf;
 	(* force_downto *)
-	wire [Y_WIDTH4:0] C = {CO, CI};
+	wire [Y_WIDTH-1:0] AA = A_buf;
 	(* force_downto *)
-	wire [Y_WIDTH4-1:0] FCO, Y1;
+	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
 
 	genvar i;
-	generate for (i = 0; i < Y_WIDTH4; i = i + 4) begin:slice
-        NX_CY cy_i (
-            .CI(C[i]),
-            .A1(AA[i]), .A2(AA[i+1]), .A3(AA[i+2]), .A4(AA[i+3]),
-            .B1(BB[i]), .B2(BB[i+1]), .B3(BB[i+2]), .B4(BB[i+3]),
-            .S1(Y1[i]), .S2(Y1[i+1]), .S3(Y1[i+2]), .S4(Y1[i+3]),
-            .CO(FCO[i])
-        );
+	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
+		NX_CY_1BIT #(.first(i==0))
+			alu_i (
+			.CI(i==0 ? CI : CO[i-1]),
+			.A(AA[i]),
+			.B(BB[i]),
+			.S(Y[i]),
+			.CO(CO[i])
+		);
 
-		assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
-        if (i+1 < Y_WIDTH)
-		    assign CO[i+1] = (AA[i+1] && BB[i+1]) || (C[i+1] && (AA[i+1] || BB[i+1]));
-		if (i+2 < Y_WIDTH)
-            assign CO[i+2] = (AA[i+2] && BB[i+2]) || (C[i+2] && (AA[i+2] || BB[i+2]));
-        if (i+3 < Y_WIDTH)
-            assign CO[i+3] = FCO[i];
+	end: slice
+	endgenerate
 
-	end endgenerate
+	NX_CY_1BIT alu_cout(
+		.CI(CO[Y_WIDTH-1]),
+		.A(1'b0),
+		.B(1'b0),
+		.S(CO[Y_WIDTH-1])
+	);
 
-	assign X = AA ^ BB;
-    assign Y = Y1[Y_WIDTH-1:0];
+   /* End implementation */
+   assign X = AA ^ BB;
 endmodule
diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v
index 88ec78b5ce1..9c3cace479a 100644
--- a/techlibs/nanoxplore/cells_sim.v
+++ b/techlibs/nanoxplore/cells_sim.v
@@ -184,4 +184,16 @@ module NX_IOB_O(I, C, T, IO);
 	assign IO = C ? I : 1'bz;
 endmodule
 
-
+(* abc9_box, lib_whitebox *)
+module NX_CY_1BIT(CI, A, B, S, CO);
+    (* abc9_carry *)
+    input CI;
+    input A;
+    input B;
+    output S;
+    (* abc9_carry *)
+    output CO;
+    parameter first = 1'b0;
+
+    assign {CO, S} = A + B + CI;
+endmodule
diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc
new file mode 100644
index 00000000000..f67cc7d5c33
--- /dev/null
+++ b/techlibs/nanoxplore/nx_carry.cc
@@ -0,0 +1,158 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Miodrag Milanovic <micko@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+static SigBit get_bit_or_zero(const SigSpec &sig)
+{
+	if (GetSize(sig) == 0)
+		return State::S0;
+	return sig[0];
+}
+
+static void nx_carry_chain(Module *module)
+{
+	SigMap sigmap(module);
+
+	dict<Cell*,SigBit> carry_ci_propagate;
+	for (auto cell : module->cells())
+	{
+		if (cell->type == ID(NX_CY_1BIT)) {
+			// Only first can have CI generated that is not constant
+			if (cell->getParam(ID(first)).as_int() == 0) continue;
+			if (!cell->getPort(ID(CI)).is_wire()) continue;
+			carry_ci_propagate[cell] = cell->getPort(ID(CI)).as_bit();
+		}
+	}
+
+	for (auto cy : carry_ci_propagate)
+	{
+		Cell *cell = cy.first;
+		cell->setParam(ID(first), Const(0, 1));
+		
+		SigBit new_co = module->addWire(NEW_ID);
+		Cell *c = module->addCell(NEW_ID, ID(NX_CY_1BIT));
+		c->setParam(ID(first), Const(1));
+		c->setPort(ID(CI), State::S0);
+		c->setPort(ID(A), cy.second);
+		c->setPort(ID(B), State::S0);
+		c->setPort(ID(CO), new_co);
+		cell->setPort(ID(CI), new_co);
+
+		log("Adding cell %s to propaget CI signal.\n", log_id(cell));
+	}
+	carry_ci_propagate.clear();
+
+	dict<SigBit,Cell*> carry;
+	for (auto cell : module->cells())
+	{
+		if (cell->type == ID(NX_CY_1BIT)) {
+			if (cell->getParam(ID(first)).as_int() == 1) continue;
+			if (!cell->hasPort(ID(CI)))
+				log_error("Not able to find connected carry.\n");
+			SigBit ci = sigmap(cell->getPort(ID(CI)).as_bit());
+			carry[ci] = cell;
+		}
+	}
+
+	dict<Cell*,vector<Cell*>> carry_chains;
+	log("Detecting carry chains\n");
+	for (auto cell : module->cells())
+	{
+		if (cell->type == ID(NX_CY_1BIT)) {
+			if (cell->getParam(ID(first)).as_int() == 0) continue;
+			
+			vector<Cell*> chain;
+			SigBit co = sigmap(cell->getPort(ID(CO)).as_bit());
+			Cell *current = cell;
+			chain.push_back(current);
+			while (co.is_wire())
+			{
+				if (carry.count(co)==0)
+					break;
+					//log_error("Not able to find connected carry.\n");
+				current = carry[co];
+				chain.push_back(current);
+				if (!current->hasPort(ID(CO))) break;
+				co = sigmap(current->getPort(ID(CO)).as_bit());
+			}
+			carry_chains[cell] = chain;
+		}
+	}
+
+	log("Creating NX_CY cells.\n");
+	for(auto& c : carry_chains) {
+		Cell *cell = nullptr;
+		int j = 0;
+		IdString names_A[] = { ID(A1), ID(A2), ID(A3), ID(A4) };
+		IdString names_B[] = { ID(B1), ID(B2), ID(B3), ID(B4) };
+		IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) };
+		for (size_t i=0 ; i<c.second.size(); i++) {
+			if (j==0) {
+				cell = module->addCell(NEW_ID, ID(NX_CY));
+				cell->setPort(ID(CI), c.second.at(i)->getPort(ID(CI)));
+			}
+			if (j==3)
+				cell->setPort(ID(CO), c.second.at(i)->getPort(ID(CO)));
+
+			
+			cell->setPort(names_A[j], get_bit_or_zero(c.second.at(i)->getPort(ID(A))));
+			cell->setPort(names_B[j], get_bit_or_zero(c.second.at(i)->getPort(ID(B))));
+			
+			if (c.second.at(i)->hasPort(ID(S))) 
+				cell->setPort(names_S[j], c.second.at(i)->getPort(ID(S)));
+
+			j = (j + 1) % 4;
+			module->remove(c.second.at(i));
+		}
+	}
+}
+
+struct NXCarryPass : public Pass {
+	NXCarryPass() : Pass("nx_carry", "NanoXplore: create carry cells") { }
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    nx_carry [options] [selection]\n");
+		log("\n");
+		log("Fixes carry chain if needed, break it on 24 elements and group by 4 into NX_CY.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		log_header(design, "Executing NX_CARRY pass.\n");
+		
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+			nx_carry_chain(module);
+	}
+} NXCarryPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index 23a2af27868..975f78cae4d 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -279,8 +279,10 @@ struct SynthNanoXplorePass : public ScriptPass
 		{
 			if (nocy)
 				run("techmap");
-			else
+			else {
 				run("techmap -map +/techmap.v -map +/nanoxplore/arith_map.v");
+				run("nx_carry");
+			}
 			if (help_mode || iopad) {
 				run("iopadmap -bits -outpad $__BEYOND_OBUF I:PAD -inpad $__BEYOND_IBUF O:PAD A:top", "(only if '-iopad')");
 				run("techmap -map +/nanoxplore/io_map.v");

From ab32dde81b050a7d83791112ac8de5eafc1082cb Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 19 Mar 2024 15:22:53 +0100
Subject: [PATCH 294/499] optimized

---
 techlibs/nanoxplore/nx_carry.cc | 44 +++++++++++----------------------
 1 file changed, 14 insertions(+), 30 deletions(-)

diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc
index f67cc7d5c33..d8a8b67bfe1 100644
--- a/techlibs/nanoxplore/nx_carry.cc
+++ b/techlibs/nanoxplore/nx_carry.cc
@@ -34,35 +34,6 @@ static void nx_carry_chain(Module *module)
 {
 	SigMap sigmap(module);
 
-	dict<Cell*,SigBit> carry_ci_propagate;
-	for (auto cell : module->cells())
-	{
-		if (cell->type == ID(NX_CY_1BIT)) {
-			// Only first can have CI generated that is not constant
-			if (cell->getParam(ID(first)).as_int() == 0) continue;
-			if (!cell->getPort(ID(CI)).is_wire()) continue;
-			carry_ci_propagate[cell] = cell->getPort(ID(CI)).as_bit();
-		}
-	}
-
-	for (auto cy : carry_ci_propagate)
-	{
-		Cell *cell = cy.first;
-		cell->setParam(ID(first), Const(0, 1));
-		
-		SigBit new_co = module->addWire(NEW_ID);
-		Cell *c = module->addCell(NEW_ID, ID(NX_CY_1BIT));
-		c->setParam(ID(first), Const(1));
-		c->setPort(ID(CI), State::S0);
-		c->setPort(ID(A), cy.second);
-		c->setPort(ID(B), State::S0);
-		c->setPort(ID(CO), new_co);
-		cell->setPort(ID(CI), new_co);
-
-		log("Adding cell %s to propaget CI signal.\n", log_id(cell));
-	}
-	carry_ci_propagate.clear();
-
 	dict<SigBit,Cell*> carry;
 	for (auto cell : module->cells())
 	{
@@ -83,9 +54,10 @@ static void nx_carry_chain(Module *module)
 			if (cell->getParam(ID(first)).as_int() == 0) continue;
 			
 			vector<Cell*> chain;
-			SigBit co = sigmap(cell->getPort(ID(CO)).as_bit());
 			Cell *current = cell;
 			chain.push_back(current);
+
+			SigBit co = sigmap(cell->getPort(ID(CO)).as_bit());
 			while (co.is_wire())
 			{
 				if (carry.count(co)==0)
@@ -107,6 +79,18 @@ static void nx_carry_chain(Module *module)
 		IdString names_A[] = { ID(A1), ID(A2), ID(A3), ID(A4) };
 		IdString names_B[] = { ID(B1), ID(B2), ID(B3), ID(B4) };
 		IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) };
+		if (c.second.at(0)->getPort(ID(CI)).is_wire()) {
+			SigBit new_co = module->addWire(NEW_ID);
+			cell = module->addCell(NEW_ID, ID(NX_CY));
+			cell->setPort(ID(CI), State::S0);
+			cell->setPort(names_A[0], c.second.at(0)->getPort(ID(CI)).as_bit());
+			cell->setPort(names_B[0], State::S0);
+			cell->setPort(ID(CO), new_co);
+
+			c.second.at(0)->setPort(ID(CI), new_co);
+			j++;
+		}
+
 		for (size_t i=0 ; i<c.second.size(); i++) {
 			if (j==0) {
 				cell = module->addCell(NEW_ID, ID(NX_CY));

From b6f73837361196f2e510cceed51a56073469ba2f Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 19 Mar 2024 17:47:40 +0100
Subject: [PATCH 295/499] break long chains

---
 techlibs/nanoxplore/nx_carry.cc | 27 +++++++++++++++++++--------
 1 file changed, 19 insertions(+), 8 deletions(-)

diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc
index d8a8b67bfe1..2a495e41e8a 100644
--- a/techlibs/nanoxplore/nx_carry.cc
+++ b/techlibs/nanoxplore/nx_carry.cc
@@ -76,18 +76,15 @@ static void nx_carry_chain(Module *module)
 	for(auto& c : carry_chains) {
 		Cell *cell = nullptr;
 		int j = 0;
+		int cnt = 0;
 		IdString names_A[] = { ID(A1), ID(A2), ID(A3), ID(A4) };
 		IdString names_B[] = { ID(B1), ID(B2), ID(B3), ID(B4) };
 		IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) };
 		if (c.second.at(0)->getPort(ID(CI)).is_wire()) {
-			SigBit new_co = module->addWire(NEW_ID);
 			cell = module->addCell(NEW_ID, ID(NX_CY));
 			cell->setPort(ID(CI), State::S0);
 			cell->setPort(names_A[0], c.second.at(0)->getPort(ID(CI)).as_bit());
 			cell->setPort(names_B[0], State::S0);
-			cell->setPort(ID(CO), new_co);
-
-			c.second.at(0)->setPort(ID(CI), new_co);
 			j++;
 		}
 
@@ -96,10 +93,24 @@ static void nx_carry_chain(Module *module)
 				cell = module->addCell(NEW_ID, ID(NX_CY));
 				cell->setPort(ID(CI), c.second.at(i)->getPort(ID(CI)));
 			}
-			if (j==3)
-				cell->setPort(ID(CO), c.second.at(i)->getPort(ID(CO)));
-
-			
+			if (j==3) {
+				cell->set_string_attribute(ID(cnt), std::to_string(cnt));
+				if (cnt % 24 == 23) {
+					SigBit new_co = module->addWire(NEW_ID);
+					cell->setPort(ID(A4), State::S0);
+					cell->setPort(ID(B4), State::S0);
+					cell->setPort(ID(S4), new_co);
+					cell = module->addCell(NEW_ID, ID(NX_CY));
+					cell->setPort(ID(CI), State::S0);
+					cell->setPort(ID(A1), new_co);
+					cell->setPort(ID(B1), State::S0);
+					j = 1;
+				} else {
+					if (c.second.at(i)->hasPort(ID(CO)))
+						cell->setPort(ID(CO), c.second.at(i)->getPort(ID(CO)));
+				}
+				cnt++;
+			}
 			cell->setPort(names_A[j], get_bit_or_zero(c.second.at(i)->getPort(ID(A))));
 			cell->setPort(names_B[j], get_bit_or_zero(c.second.at(i)->getPort(ID(B))));
 			

From 31f943513bbee5905fc1241fe9edf1dbe24f3110 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 25 Mar 2024 09:23:31 +0100
Subject: [PATCH 296/499] set add_carry property and all inputs to 0

---
 techlibs/nanoxplore/nx_carry.cc | 37 ++++++++++++++++++++++++++++++++-
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc
index 2a495e41e8a..a61921e05c6 100644
--- a/techlibs/nanoxplore/nx_carry.cc
+++ b/techlibs/nanoxplore/nx_carry.cc
@@ -83,6 +83,16 @@ static void nx_carry_chain(Module *module)
 		if (c.second.at(0)->getPort(ID(CI)).is_wire()) {
 			cell = module->addCell(NEW_ID, ID(NX_CY));
 			cell->setPort(ID(CI), State::S0);
+			// Set all inputs on 0
+			cell->setPort(ID(A1), State::S0);
+			cell->setPort(ID(B1), State::S0);
+			cell->setPort(ID(A2), State::S0);
+			cell->setPort(ID(B2), State::S0);
+			cell->setPort(ID(A3), State::S0);
+			cell->setPort(ID(B3), State::S0);
+			cell->setPort(ID(A4), State::S0);
+			cell->setPort(ID(B4), State::S0);
+
 			cell->setPort(names_A[0], c.second.at(0)->getPort(ID(CI)).as_bit());
 			cell->setPort(names_B[0], State::S0);
 			j++;
@@ -91,7 +101,25 @@ static void nx_carry_chain(Module *module)
 		for (size_t i=0 ; i<c.second.size(); i++) {
 			if (j==0) {
 				cell = module->addCell(NEW_ID, ID(NX_CY));
-				cell->setPort(ID(CI), c.second.at(i)->getPort(ID(CI)));
+				SigBit ci = c.second.at(i)->getPort(ID(CI)).as_bit();
+				cell->setPort(ID(CI), ci);
+				// Set all inputs on 0
+				cell->setPort(ID(A1), State::S0);
+				cell->setPort(ID(B1), State::S0);
+				cell->setPort(ID(A2), State::S0);
+				cell->setPort(ID(B2), State::S0);
+				cell->setPort(ID(A3), State::S0);
+				cell->setPort(ID(B3), State::S0);
+				cell->setPort(ID(A4), State::S0);
+				cell->setPort(ID(B4), State::S0);
+				if (ci.is_wire()) {
+					cell->setParam(ID(add_carry), Const(2,2));
+				} else {
+					if (ci == State::S0)
+						cell->setParam(ID(add_carry), Const(0,2));
+					else
+						cell->setParam(ID(add_carry), Const(1,2));
+				}
 			}
 			if (j==3) {
 				cell->set_string_attribute(ID(cnt), std::to_string(cnt));
@@ -104,6 +132,13 @@ static void nx_carry_chain(Module *module)
 					cell->setPort(ID(CI), State::S0);
 					cell->setPort(ID(A1), new_co);
 					cell->setPort(ID(B1), State::S0);
+					// Set all inputs on 0
+					cell->setPort(ID(A2), State::S0);
+					cell->setPort(ID(B2), State::S0);
+					cell->setPort(ID(A3), State::S0);
+					cell->setPort(ID(B3), State::S0);
+					cell->setPort(ID(A4), State::S0);
+					cell->setPort(ID(B4), State::S0);
 					j = 1;
 				} else {
 					if (c.second.at(i)->hasPort(ID(CO)))

From cf21b48bfd60dccaeb6cf5efdace883ca80ac8e3 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sun, 7 Apr 2024 19:38:47 +0200
Subject: [PATCH 297/499] fix co on nx_cy

---
 techlibs/nanoxplore/arith_map.v | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/techlibs/nanoxplore/arith_map.v b/techlibs/nanoxplore/arith_map.v
index 7b4534b8350..39d03229dce 100644
--- a/techlibs/nanoxplore/arith_map.v
+++ b/techlibs/nanoxplore/arith_map.v
@@ -35,6 +35,8 @@ module _80_nx_cy_alu (A, B, CI, BI, X, Y, CO);
 	input CI, BI;
 	(* force_downto *)
 	output [Y_WIDTH-1:0] CO;
+    (* force_downto *)
+    wire [Y_WIDTH-1:0] COx;
 
 	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
 
@@ -52,18 +54,18 @@ module _80_nx_cy_alu (A, B, CI, BI, X, Y, CO);
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
 		NX_CY_1BIT #(.first(i==0))
 			alu_i (
-			.CI(i==0 ? CI : CO[i-1]),
+			.CI(i==0 ? CI : COx[i-1]),
 			.A(AA[i]),
 			.B(BB[i]),
 			.S(Y[i]),
-			.CO(CO[i])
+			.CO(COx[i])
 		);
 
 	end: slice
 	endgenerate
 
 	NX_CY_1BIT alu_cout(
-		.CI(CO[Y_WIDTH-1]),
+		.CI(COx[Y_WIDTH-1]),
 		.A(1'b0),
 		.B(1'b0),
 		.S(CO[Y_WIDTH-1])

From dac4f04460d6fdd7a1638aab637e41d72843a3ca Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 19 Apr 2024 18:09:47 +0200
Subject: [PATCH 298/499] add latch mapping, and remove aldff for now

---
 techlibs/nanoxplore/Makefile.inc        |  1 +
 techlibs/nanoxplore/cells_map.v         | 14 +++++++-------
 techlibs/nanoxplore/latches_map.v       | 11 +++++++++++
 techlibs/nanoxplore/synth_nanoxplore.cc |  3 ++-
 4 files changed, 21 insertions(+), 8 deletions(-)
 create mode 100644 techlibs/nanoxplore/latches_map.v

diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc
index f6606639e31..180922a50a7 100644
--- a/techlibs/nanoxplore/Makefile.inc
+++ b/techlibs/nanoxplore/Makefile.inc
@@ -17,6 +17,7 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/latches_map.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_l.txt))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_m.txt))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_u.txt))
diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v
index 75e7140aae5..e851b86bf08 100644
--- a/techlibs/nanoxplore/cells_map.v
+++ b/techlibs/nanoxplore/cells_map.v
@@ -43,13 +43,13 @@ module dff(input D, C, R, output Q);
   NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
 endmodule
 
-(* techmap_celltype = "$_ALDFF_[NP]P_" *)
-module aldff(input D, C, L, AD, output Q);
-	parameter _TECHMAP_CELLTYPE = "$_ALDFF_PP_";
-  localparam dff_edge = _TECHMAP_CELLTYPE[8*8 +: 8] == "N";
-  wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
-  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(2)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(AD), .R(L), .O(Q));
-endmodule
+//(* techmap_celltype = "$_ALDFF_[NP]P_" *)
+//module aldff(input D, C, L, AD, output Q);
+//	parameter _TECHMAP_CELLTYPE = "$_ALDFF_PP_";
+//  localparam dff_edge = _TECHMAP_CELLTYPE[8*8 +: 8] == "N";
+//  wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
+//  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(2)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(AD), .R(L), .O(Q));
+//endmodule
 
 module \$_SDFF_PP0_ (input D, C, R, output Q);
   wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
diff --git a/techlibs/nanoxplore/latches_map.v b/techlibs/nanoxplore/latches_map.v
new file mode 100644
index 00000000000..c28f88cf767
--- /dev/null
+++ b/techlibs/nanoxplore/latches_map.v
@@ -0,0 +1,11 @@
+module \$_DLATCH_N_ (E, D, Q);
+  wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+  input E, D;
+  output Q = !E ? D : Q;
+endmodule
+
+module \$_DLATCH_P_ (E, D, Q);
+  wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+  input E, D;
+  output Q = E ? D : Q;
+endmodule
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index 975f78cae4d..edbd67f261c 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -294,7 +294,8 @@ struct SynthNanoXplorePass : public ScriptPass
 
 		if (check_label("map_ffs"))
 		{
-			run("dfflegalize -cell $_DFF_?P?_ 0 -cell $_ALDFF_?P_ 0 -cell $_SDFF_?P?_ 0");
+			run("dfflegalize -cell $_DFF_?P?_ 0 -cell $_SDFF_?P?_ 0 -cell $_DLATCH_?_ x"); //-cell $_ALDFF_?P_ 0
+			run("techmap -map +/nanoxplore/latches_map.v");
 			run("techmap -map +/nanoxplore/cells_map.v");
 			run("opt_expr -undriven -mux_undef");
 			run("clean -purge");

From 1591d258a9302e97cedcb9d31241025d02338e4e Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 22 Apr 2024 14:06:03 +0200
Subject: [PATCH 299/499] Made NX_CY model more robust

---
 techlibs/nanoxplore/cells_sim.v | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v
index 9c3cace479a..3af9dd539a0 100644
--- a/techlibs/nanoxplore/cells_sim.v
+++ b/techlibs/nanoxplore/cells_sim.v
@@ -40,7 +40,15 @@ endmodule
 module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO);
 parameter add_carry = 0;
 
-assign {CO, S4, S3, S2, S1} = {A4, A3, A2, A1} + {B4, B3, B2, B1} + CI;
+wire CI_1;
+wire CO1, CO2, CO3;
+
+assign  CI_1 = (add_carry==2) ? CI : ((add_carry==1) ? 1'b1 : 1'b0);
+
+assign { CO1, S1 } = A1 + B1 + CI_1;
+assign { CO2, S2 } = A2 + B2 + CO1;
+assign { CO3, S3 } = A3 + B3 + CO2;
+assign { CO,  S4 } = A4 + B4 + CO3;
 
 endmodule
 

From 4cb8e6262629d361f65e79fbeb2c4acde75366fb Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 24 Apr 2024 11:01:27 +0200
Subject: [PATCH 300/499] Properly map ff ram

---
 techlibs/nanoxplore/synth_nanoxplore.cc | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index edbd67f261c..de422ae9c0f 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -269,10 +269,9 @@ struct SynthNanoXplorePass : public ScriptPass
 
 		if (check_label("map_ffram"))
 		{
-			//run("opt -fast -mux_undef -undriven -fine");
+			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");
-			run("opt -full");
-			//run("opt -undriven -fine -mux_undef");
+			run("opt -undriven -fine -mux_undef");
 		}
 
 		if (check_label("map_gates"))

From 606439b44c417773453694e69a940410e0bebe1a Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 24 Apr 2024 11:28:03 +0200
Subject: [PATCH 301/499] do not leave NX_RAM empty to prevent removing it

---
 techlibs/nanoxplore/brams_map.v         | 12 ++++++++++++
 techlibs/nanoxplore/synth_nanoxplore.cc |  1 +
 2 files changed, 13 insertions(+)

diff --git a/techlibs/nanoxplore/brams_map.v b/techlibs/nanoxplore/brams_map.v
index 04b6134c3cb..b025a678254 100644
--- a/techlibs/nanoxplore/brams_map.v
+++ b/techlibs/nanoxplore/brams_map.v
@@ -29,4 +29,16 @@ input [12:0] PORT_B_ADDR;
 input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
 output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
 
+NX_RAM_WRAP #(
+) _TECHMAP_REPLACE_ (
+    .ACK(PORT_A_CLK),
+    .AA(PORT_A_ADDR),
+    .AI(PORT_A_WR_DATA),
+    .AO(PORT_A_RD_DATA),
+
+    .BCK(PORT_B_CLK),
+    .BA(PORT_B_ADDR),
+    .BI(PORT_B_WR_DATA),
+    .BO(PORT_B_RD_DATA)
+);
 endmodule
\ No newline at end of file
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index de422ae9c0f..e34ae212e56 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -264,6 +264,7 @@ struct SynthNanoXplorePass : public ScriptPass
 				args += " [-no-auto-block] [-no-auto-distributed]";
 			run("memory_libmap -lib +/nanoxplore/rf_rams"+ postfix + ".txt -lib +/nanoxplore/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -norfram)");
 			run("techmap -map +/nanoxplore/rf_rams_map"+ postfix + ".v -map +/nanoxplore/brams_map.v");
+			run("techmap -map +/nanoxplore/cells_wrap.v t:NX_RAM*");
 			run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v t:NX_XRFB* t:NX_RFB*");
 		}
 

From 94675a5e0b7b00776244592f424d906a56430389 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 29 Apr 2024 08:06:01 +0200
Subject: [PATCH 302/499] Fix dff simulation model

---
 techlibs/nanoxplore/cells_sim.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v
index 3af9dd539a0..de3cffcc8dd 100644
--- a/techlibs/nanoxplore/cells_sim.v
+++ b/techlibs/nanoxplore/cells_sim.v
@@ -25,14 +25,14 @@ initial begin
 end
 
 wire clock = CK ^ dff_edge;
-wire load = (dff_type == 2) ? (dff_load ? L : 1'bx) : dff_type;
+wire load = dff_load ? L : 1'b1;
 wire async_reset = !dff_sync && dff_init && R;
 wire sync_reset = dff_sync && dff_init && R;
 
 always @(posedge clock, posedge async_reset)
-	if (async_reset) O <= load;
-	else if (sync_reset) O <= load;
-	else O <= I;
+	if (async_reset) O <= dff_type;
+	else if (sync_reset) O <= dff_type;
+	else if (load) O <= I;
 
 endmodule
 

From 0c4bbf7e4b59c3688e9cf67bff52892bd2394a2c Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 29 Apr 2024 08:06:32 +0200
Subject: [PATCH 303/499] Fix existing DFF mapping and add new types

---
 techlibs/nanoxplore/cells_map.v | 59 ++++++++++++++++++++++-----------
 1 file changed, 39 insertions(+), 20 deletions(-)

diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v
index e851b86bf08..73680df59a0 100644
--- a/techlibs/nanoxplore/cells_map.v
+++ b/techlibs/nanoxplore/cells_map.v
@@ -35,38 +35,57 @@ module \$lut (A, Y);
 endmodule
 
 (* techmap_celltype = "$_DFF_[NP]P[01]_" *)
-module dff(input D, C, R, output Q);
-	parameter _TECHMAP_CELLTYPE = "$_DFF_PP1_";
-  localparam dff_edge = _TECHMAP_CELLTYPE[6*8 +: 8] == "N";
-  localparam dff_type = _TECHMAP_CELLTYPE[8*8 +: 8] == "1";
+module \$_DFF_xxxx_ (input D, C, R, output Q);
+	parameter _TECHMAP_CELLTYPE_ = "";
+  localparam dff_edge = _TECHMAP_CELLTYPE_[3*8 +: 8] == "N";
+  localparam dff_type = _TECHMAP_CELLTYPE_[1*8 +: 8] == "1";
   wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
-  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
+  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(R), .O(Q));
 endmodule
 
-//(* techmap_celltype = "$_ALDFF_[NP]P_" *)
-//module aldff(input D, C, L, AD, output Q);
-//	parameter _TECHMAP_CELLTYPE = "$_ALDFF_PP_";
-//  localparam dff_edge = _TECHMAP_CELLTYPE[8*8 +: 8] == "N";
-//  wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
-//  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(2)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(AD), .R(L), .O(Q));
-//endmodule
+(* techmap_celltype = "$_SDFF_[NP]P[01]_" *)
+module \$_SDFF_xxxx_ (input D, C, R, output Q);
+	parameter _TECHMAP_CELLTYPE_ = "";
+  localparam dff_edge = _TECHMAP_CELLTYPE_[3*8 +: 8] == "N";
+  localparam dff_type = _TECHMAP_CELLTYPE_[1*8 +: 8] == "1";
+  wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
+  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(R), .O(Q));
+endmodule
+
+(* techmap_celltype = "$_DFFE_[NP]P[01]P_" *)
+module \$_DFFE_xxxx_ (input D, C, R, E, output Q);
+	parameter _TECHMAP_CELLTYPE_ = "";
+  localparam dff_edge = _TECHMAP_CELLTYPE_[4*8 +: 8] == "N";
+  localparam dff_type = _TECHMAP_CELLTYPE_[2*8 +: 8] == "1";
+  wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
+  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(R), .O(Q));
+endmodule
+
+(* techmap_celltype = "$_SDFFE_[NP]P[01]P_" *)
+module \$_SDFFE_xxxx_ (input D, C, R, E, output Q);
+	parameter _TECHMAP_CELLTYPE_ = "";
+  localparam dff_edge = _TECHMAP_CELLTYPE_[4*8 +: 8] == "N";
+  localparam dff_type = _TECHMAP_CELLTYPE_[2*8 +: 8] == "1";
+  wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
+  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b1), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(R), .O(Q));
+endmodule
 
-module \$_SDFF_PP0_ (input D, C, R, output Q);
+module \$_DFF_P_ (input D, C, output Q);
   wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
-  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
+  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q));
 endmodule
 
-module \$_SDFF_PP1_ (input D, C, R, output Q);
+module \$_DFF_N_ (input D, C, output Q);
   wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
-  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
+  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q));
 endmodule
 
-module \$_SDFF_NP0_ (input D, C, R, output Q);
+module \$_DFFE_PP_ (input D, C, E, output Q);
   wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
-  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
+  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q));
 endmodule
 
-module \$_SDFF_NP1_ (input D, C, R, output Q);
+module \$_DFFE_NN_ (input D, C, E, output Q);
   wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
-  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
+  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q));
 endmodule

From 198fc963ca713b3798ce9fce1872b41df8448fe8 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 29 Apr 2024 08:18:04 +0200
Subject: [PATCH 304/499] Add new DFF types, and added "-nodffe" option

---
 techlibs/nanoxplore/synth_nanoxplore.cc | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index e34ae212e56..1f6bc658c7b 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -73,6 +73,9 @@ struct SynthNanoXplorePass : public ScriptPass
 		log("    -nocy\n");
 		log("        do not map adders to CY cells\n");
 		log("\n");
+		log("    -nodffe\n");
+		log("        do not use flipflops with L in output netlist\n");
+		log("\n");
 		log("    -norfram\n");
 		log("        do not use Register File RAM cells in output netlist\n");
 		log("\n");
@@ -97,7 +100,7 @@ struct SynthNanoXplorePass : public ScriptPass
 	}
 
 	string top_opt, json_file, family;
-	bool flatten, abc9, nocy, norfram, nobram, nodsp, iopad, no_rw_check;
+	bool flatten, abc9, nocy, nodffe, norfram, nobram, nodsp, iopad, no_rw_check;
 	std::string postfix;
 
 	void clear_flags() override
@@ -108,6 +111,7 @@ struct SynthNanoXplorePass : public ScriptPass
 		flatten = true;
 		abc9 = false;
 		nocy = false;
+		nodffe = false;
 		norfram = false;
 		nobram = false;
 		nodsp = false;
@@ -160,6 +164,10 @@ struct SynthNanoXplorePass : public ScriptPass
 				nocy = true;
 				continue;
 			}
+			if (args[argidx] == "-nodffe") {
+				nodffe = true;
+				continue;
+			}
 			if (args[argidx] == "-norfram") {
 				norfram = true;
 				continue;
@@ -294,7 +302,14 @@ struct SynthNanoXplorePass : public ScriptPass
 
 		if (check_label("map_ffs"))
 		{
-			run("dfflegalize -cell $_DFF_?P?_ 0 -cell $_SDFF_?P?_ 0 -cell $_DLATCH_?_ x"); //-cell $_ALDFF_?P_ 0
+			std::string dfflegalize_args = " -cell $_DFF_?_ 0 -cell $_DFF_?P?_ 0 -cell $_SDFF_?P?_ 0";
+			if (help_mode) {
+				dfflegalize_args += " [-cell $_DFFE_PP_ 0 -cell $_DFFE_NN_ 0 -cell $_DFFE_?P?P_ 0 -cell $_SDFFE_?P?P_ 0]";
+			} else if (!nodffe) {
+				dfflegalize_args += " -cell $_DFFE_PP_ 0 -cell $_DFFE_NN_ 0 -cell $_DFFE_?P?P_ 0 -cell $_SDFFE_?P?P_ 0";
+			}
+			dfflegalize_args += " -cell $_DLATCH_?_ x";
+			run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)");
 			run("techmap -map +/nanoxplore/latches_map.v");
 			run("techmap -map +/nanoxplore/cells_map.v");
 			run("opt_expr -undriven -mux_undef");

From cb45f8b69df0699196f19f842252246aac05a318 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 30 Apr 2024 10:35:45 +0200
Subject: [PATCH 305/499] Fixed of mapping and initialization

---
 techlibs/nanoxplore/cells_map.v         | 2 +-
 techlibs/nanoxplore/synth_nanoxplore.cc | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v
index 73680df59a0..8e27b699251 100644
--- a/techlibs/nanoxplore/cells_map.v
+++ b/techlibs/nanoxplore/cells_map.v
@@ -85,7 +85,7 @@ module \$_DFFE_PP_ (input D, C, E, output Q);
   NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q));
 endmodule
 
-module \$_DFFE_NN_ (input D, C, E, output Q);
+module \$_DFFE_NP_ (input D, C, E, output Q);
   wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
   NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q));
 endmodule
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index 1f6bc658c7b..3b8351abcaf 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -302,11 +302,11 @@ struct SynthNanoXplorePass : public ScriptPass
 
 		if (check_label("map_ffs"))
 		{
-			std::string dfflegalize_args = " -cell $_DFF_?_ 0 -cell $_DFF_?P?_ 0 -cell $_SDFF_?P?_ 0";
+			std::string dfflegalize_args = " -cell $_DFF_?_ 0 -cell $_DFF_?P0_ 0 -cell $_SDFF_?P0_ 0";
 			if (help_mode) {
-				dfflegalize_args += " [-cell $_DFFE_PP_ 0 -cell $_DFFE_NN_ 0 -cell $_DFFE_?P?P_ 0 -cell $_SDFFE_?P?P_ 0]";
+				dfflegalize_args += " [-cell $_DFFE_?P_ 0 -cell $_DFFE_?P0P_ 0 -cell $_SDFFE_?P0P_ 0]";
 			} else if (!nodffe) {
-				dfflegalize_args += " -cell $_DFFE_PP_ 0 -cell $_DFFE_NN_ 0 -cell $_DFFE_?P?P_ 0 -cell $_SDFFE_?P?P_ 0";
+				dfflegalize_args += " -cell $_DFFE_?P_ 0 -cell $_DFFE_?P0P_ 0 -cell $_SDFFE_?P0P_ 0";
 			}
 			dfflegalize_args += " -cell $_DLATCH_?_ x";
 			run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)");

From dc16bdd85bb931a9111678fc5ce9225688cd3d90 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 30 Apr 2024 13:29:03 +0200
Subject: [PATCH 306/499] DFF reset and context must be in sync

---
 techlibs/nanoxplore/cells_map.v         | 8 ++++----
 techlibs/nanoxplore/synth_nanoxplore.cc | 6 +++---
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v
index 8e27b699251..8d6fb09fc84 100644
--- a/techlibs/nanoxplore/cells_map.v
+++ b/techlibs/nanoxplore/cells_map.v
@@ -40,7 +40,7 @@ module \$_DFF_xxxx_ (input D, C, R, output Q);
   localparam dff_edge = _TECHMAP_CELLTYPE_[3*8 +: 8] == "N";
   localparam dff_type = _TECHMAP_CELLTYPE_[1*8 +: 8] == "1";
   wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
-  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(R), .O(Q));
+  NX_DFF #(.dff_ctxt(dff_type), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(R), .O(Q));
 endmodule
 
 (* techmap_celltype = "$_SDFF_[NP]P[01]_" *)
@@ -49,7 +49,7 @@ module \$_SDFF_xxxx_ (input D, C, R, output Q);
   localparam dff_edge = _TECHMAP_CELLTYPE_[3*8 +: 8] == "N";
   localparam dff_type = _TECHMAP_CELLTYPE_[1*8 +: 8] == "1";
   wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
-  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(R), .O(Q));
+  NX_DFF #(.dff_ctxt(dff_type), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(R), .O(Q));
 endmodule
 
 (* techmap_celltype = "$_DFFE_[NP]P[01]P_" *)
@@ -58,7 +58,7 @@ module \$_DFFE_xxxx_ (input D, C, R, E, output Q);
   localparam dff_edge = _TECHMAP_CELLTYPE_[4*8 +: 8] == "N";
   localparam dff_type = _TECHMAP_CELLTYPE_[2*8 +: 8] == "1";
   wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
-  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(R), .O(Q));
+  NX_DFF #(.dff_ctxt(dff_type), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(R), .O(Q));
 endmodule
 
 (* techmap_celltype = "$_SDFFE_[NP]P[01]P_" *)
@@ -67,7 +67,7 @@ module \$_SDFFE_xxxx_ (input D, C, R, E, output Q);
   localparam dff_edge = _TECHMAP_CELLTYPE_[4*8 +: 8] == "N";
   localparam dff_type = _TECHMAP_CELLTYPE_[2*8 +: 8] == "1";
   wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
-  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b1), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(R), .O(Q));
+  NX_DFF #(.dff_ctxt(dff_type), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b1), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(R), .O(Q));
 endmodule
 
 module \$_DFF_P_ (input D, C, output Q);
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index 3b8351abcaf..38f1d2f2239 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -302,11 +302,11 @@ struct SynthNanoXplorePass : public ScriptPass
 
 		if (check_label("map_ffs"))
 		{
-			std::string dfflegalize_args = " -cell $_DFF_?_ 0 -cell $_DFF_?P0_ 0 -cell $_SDFF_?P0_ 0";
+			std::string dfflegalize_args = " -cell $_DFF_?_ 0 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r";
 			if (help_mode) {
-				dfflegalize_args += " [-cell $_DFFE_?P_ 0 -cell $_DFFE_?P0P_ 0 -cell $_SDFFE_?P0P_ 0]";
+				dfflegalize_args += " [-cell $_DFFE_?P_ 0 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r]";
 			} else if (!nodffe) {
-				dfflegalize_args += " -cell $_DFFE_?P_ 0 -cell $_DFFE_?P0P_ 0 -cell $_SDFFE_?P0P_ 0";
+				dfflegalize_args += " -cell $_DFFE_?P_ 0 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r";
 			}
 			dfflegalize_args += " -cell $_DLATCH_?_ x";
 			run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)");

From 9a9190b67d919598e31aad163040e6f429e1abd9 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 30 Apr 2024 13:40:35 +0200
Subject: [PATCH 307/499] enable dff context initialization

---
 techlibs/nanoxplore/cells_map.v         | 12 ++++++++----
 techlibs/nanoxplore/synth_nanoxplore.cc |  6 +++---
 2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v
index 8d6fb09fc84..39df93ee03b 100644
--- a/techlibs/nanoxplore/cells_map.v
+++ b/techlibs/nanoxplore/cells_map.v
@@ -71,21 +71,25 @@ module \$_SDFFE_xxxx_ (input D, C, R, E, output Q);
 endmodule
 
 module \$_DFF_P_ (input D, C, output Q);
+  parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
   wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
-  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q));
+  NX_DFF #(.dff_ctxt(_TECHMAP_WIREINIT_Q_), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q));
 endmodule
 
 module \$_DFF_N_ (input D, C, output Q);
+  parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
   wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
-  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q));
+  NX_DFF #(.dff_ctxt(_TECHMAP_WIREINIT_Q_), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q));
 endmodule
 
 module \$_DFFE_PP_ (input D, C, E, output Q);
+  parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
   wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
-  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q));
+  NX_DFF #(.dff_ctxt(_TECHMAP_WIREINIT_Q_), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q));
 endmodule
 
 module \$_DFFE_NP_ (input D, C, E, output Q);
+  parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
   wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
-  NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q));
+  NX_DFF #(.dff_ctxt(_TECHMAP_WIREINIT_Q_), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q));
 endmodule
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index 38f1d2f2239..3842877e433 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -302,11 +302,11 @@ struct SynthNanoXplorePass : public ScriptPass
 
 		if (check_label("map_ffs"))
 		{
-			std::string dfflegalize_args = " -cell $_DFF_?_ 0 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r";
+			std::string dfflegalize_args = " -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r";
 			if (help_mode) {
-				dfflegalize_args += " [-cell $_DFFE_?P_ 0 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r]";
+				dfflegalize_args += " [-cell $_DFFE_?P_ 01 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r]";
 			} else if (!nodffe) {
-				dfflegalize_args += " -cell $_DFFE_?P_ 0 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r";
+				dfflegalize_args += " -cell $_DFFE_?P_ 01 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r";
 			}
 			dfflegalize_args += " -cell $_DLATCH_?_ x";
 			run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)");

From 645888cff5ca6b1a91afb968db1a2b3a5a90a0a5 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 6 May 2024 15:00:06 +0200
Subject: [PATCH 308/499] cleanup

---
 techlibs/nanoxplore/nx_carry.cc | 25 -------------------------
 1 file changed, 25 deletions(-)

diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc
index a61921e05c6..08701b44ebd 100644
--- a/techlibs/nanoxplore/nx_carry.cc
+++ b/techlibs/nanoxplore/nx_carry.cc
@@ -83,15 +83,6 @@ static void nx_carry_chain(Module *module)
 		if (c.second.at(0)->getPort(ID(CI)).is_wire()) {
 			cell = module->addCell(NEW_ID, ID(NX_CY));
 			cell->setPort(ID(CI), State::S0);
-			// Set all inputs on 0
-			cell->setPort(ID(A1), State::S0);
-			cell->setPort(ID(B1), State::S0);
-			cell->setPort(ID(A2), State::S0);
-			cell->setPort(ID(B2), State::S0);
-			cell->setPort(ID(A3), State::S0);
-			cell->setPort(ID(B3), State::S0);
-			cell->setPort(ID(A4), State::S0);
-			cell->setPort(ID(B4), State::S0);
 
 			cell->setPort(names_A[0], c.second.at(0)->getPort(ID(CI)).as_bit());
 			cell->setPort(names_B[0], State::S0);
@@ -103,15 +94,6 @@ static void nx_carry_chain(Module *module)
 				cell = module->addCell(NEW_ID, ID(NX_CY));
 				SigBit ci = c.second.at(i)->getPort(ID(CI)).as_bit();
 				cell->setPort(ID(CI), ci);
-				// Set all inputs on 0
-				cell->setPort(ID(A1), State::S0);
-				cell->setPort(ID(B1), State::S0);
-				cell->setPort(ID(A2), State::S0);
-				cell->setPort(ID(B2), State::S0);
-				cell->setPort(ID(A3), State::S0);
-				cell->setPort(ID(B3), State::S0);
-				cell->setPort(ID(A4), State::S0);
-				cell->setPort(ID(B4), State::S0);
 				if (ci.is_wire()) {
 					cell->setParam(ID(add_carry), Const(2,2));
 				} else {
@@ -132,13 +114,6 @@ static void nx_carry_chain(Module *module)
 					cell->setPort(ID(CI), State::S0);
 					cell->setPort(ID(A1), new_co);
 					cell->setPort(ID(B1), State::S0);
-					// Set all inputs on 0
-					cell->setPort(ID(A2), State::S0);
-					cell->setPort(ID(B2), State::S0);
-					cell->setPort(ID(A3), State::S0);
-					cell->setPort(ID(B3), State::S0);
-					cell->setPort(ID(A4), State::S0);
-					cell->setPort(ID(B4), State::S0);
 					j = 1;
 				} else {
 					if (c.second.at(i)->hasPort(ID(CO)))

From 34f08bc639b56bf0b75c618b52e4ba1820e29d70 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 6 May 2024 15:25:29 +0200
Subject: [PATCH 309/499] Enable nanoxplore tests

---
 Makefile                         |  1 +
 tests/arch/nanoxplore/adffs.ys   |  3 ++-
 tests/arch/nanoxplore/dffs.ys    |  3 +--
 tests/arch/nanoxplore/fsm.ys     |  2 +-
 tests/arch/nanoxplore/latches.ys | 10 ++++------
 5 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/Makefile b/Makefile
index a2803ed5934..14a37b99557 100644
--- a/Makefile
+++ b/Makefile
@@ -877,6 +877,7 @@ endif
 	+cd tests/arch/anlogic && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/gowin && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/intel_alm && bash run-test.sh $(SEEDOPT)
+	+cd tests/arch/nanoxplore && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/nexus && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/quicklogic/pp3 && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/quicklogic/qlf_k6n10f && bash run-test.sh $(SEEDOPT)
diff --git a/tests/arch/nanoxplore/adffs.ys b/tests/arch/nanoxplore/adffs.ys
index 6a4f63ad7c7..9f4e1fac786 100644
--- a/tests/arch/nanoxplore/adffs.ys
+++ b/tests/arch/nanoxplore/adffs.ys
@@ -30,8 +30,9 @@ equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # e
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:NX_DFF
+select -assert-count 1 t:NX_LUT
 
-select -assert-none t:NX_DFF %% t:* %D
+select -assert-none t:NX_DFF t:NX_LUT %% t:* %D
 
 
 design -load read
diff --git a/tests/arch/nanoxplore/dffs.ys b/tests/arch/nanoxplore/dffs.ys
index ba7dff41c46..898765408c0 100644
--- a/tests/arch/nanoxplore/dffs.ys
+++ b/tests/arch/nanoxplore/dffs.ys
@@ -17,6 +17,5 @@ equiv_opt -assert -async2sync -map +/nanoxplore/cells_sim.v synth_nanoxplore # e
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:NX_DFF
-select -assert-count 1 t:NX_LUT
 
-select -assert-none t:NX_DFF t:NX_LUT %% t:* %D
+select -assert-none t:NX_DFF %% t:* %D
diff --git a/tests/arch/nanoxplore/fsm.ys b/tests/arch/nanoxplore/fsm.ys
index ee00be4e1bd..8582d111c23 100644
--- a/tests/arch/nanoxplore/fsm.ys
+++ b/tests/arch/nanoxplore/fsm.ys
@@ -12,5 +12,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd fsm # Constrain all select calls below inside the top module
 
 select -assert-count 6 t:NX_DFF
-select -assert-count 13 t:NX_LUT
+select -assert-count 14 t:NX_LUT
 select -assert-none t:NX_DFF t:NX_LUT %% t:* %D
diff --git a/tests/arch/nanoxplore/latches.ys b/tests/arch/nanoxplore/latches.ys
index 32609dbce40..4625348f916 100644
--- a/tests/arch/nanoxplore/latches.ys
+++ b/tests/arch/nanoxplore/latches.ys
@@ -6,9 +6,9 @@ proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
 synth_nanoxplore
 cd latchp # Constrain all select calls below inside the top module
-select -assert-count 1 t:NX_DFF
+select -assert-count 1 t:NX_LUT
 
-select -assert-none t:NX_DFF %% t:* %D
+select -assert-none t:NX_LUT %% t:* %D
 
 
 design -load read
@@ -18,9 +18,8 @@ proc
 synth_nanoxplore
 cd latchn # Constrain all select calls below inside the top module
 select -assert-count 1 t:NX_LUT
-select -assert-count 1 t:NX_DFF
 
-select -assert-none t:NX_LUT t:NX_DFF %% t:* %D
+select -assert-none t:NX_LUT %% t:* %D
 
 
 design -load read
@@ -30,6 +29,5 @@ proc
 synth_nanoxplore
 cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 2 t:NX_LUT
-select -assert-count 1 t:NX_DFF
 
-select -assert-none t:NX_LUT t:NX_DFF %% t:* %D
+select -assert-none t:NX_LUT %% t:* %D

From 41ae513d6090539d0bff85c18c307adf2dda073d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 7 May 2024 09:06:10 +0200
Subject: [PATCH 310/499] support other I/O configurations

---
 techlibs/nanoxplore/io_map.v            | 7 +++++++
 techlibs/nanoxplore/synth_nanoxplore.cc | 6 +++---
 tests/arch/nanoxplore/tribuf.ys         | 7 ++++---
 3 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/techlibs/nanoxplore/io_map.v b/techlibs/nanoxplore/io_map.v
index 42fac461903..edbb0437b11 100644
--- a/techlibs/nanoxplore/io_map.v
+++ b/techlibs/nanoxplore/io_map.v
@@ -6,3 +6,10 @@ module \$__BEYOND_OBUF (output PAD, input I);
 	NX_IOB_O _TECHMAP_REPLACE_ (.IO(PAD), .I(I), .C(1'b1));
 endmodule
 
+module \$__BEYOND_TOBUF (output PAD, input I, input C);
+	NX_IOB _TECHMAP_REPLACE_ (.IO(PAD), .I(I), .C(C));
+endmodule
+
+module \$__BEYOND_IOBUF (output PAD, input I, output O, output C);
+	NX_IOB _TECHMAP_REPLACE_ (.IO(PAD), .I(I), .O(O), .C(C));
+endmodule
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index 3842877e433..52d0256031e 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -292,10 +292,10 @@ struct SynthNanoXplorePass : public ScriptPass
 				run("nx_carry");
 			}
 			if (help_mode || iopad) {
-				run("iopadmap -bits -outpad $__BEYOND_OBUF I:PAD -inpad $__BEYOND_IBUF O:PAD A:top", "(only if '-iopad')");
+				run("iopadmap -bits -outpad $__BEYOND_OBUF I:PAD -toutpad $__BEYOND_TOBUF C:I:PAD -inpad $__BEYOND_IBUF O:PAD -tinoutpad $__BEYOND_IOBUF C:O:I:PAD A:top", "(only if '-iopad')");
 				run("techmap -map +/nanoxplore/io_map.v");
-				run("attrmvcp -attr LOC t:NX_IOB_O n:*");
-				run("attrmvcp -attr LOC -driven t:NX_IOB_I n:*");
+				run("attrmvcp -attr LOC t:NX_IOB_O t:NX_IOB n:*");
+				run("attrmvcp -attr LOC -driven t:NX_IOB_I t:NX_IOB n:*");
 			}
 			run("opt -fast");
 		}
diff --git a/tests/arch/nanoxplore/tribuf.ys b/tests/arch/nanoxplore/tribuf.ys
index c72e2e1ad5e..e55764f0126 100644
--- a/tests/arch/nanoxplore/tribuf.ys
+++ b/tests/arch/nanoxplore/tribuf.ys
@@ -4,9 +4,10 @@ proc
 tribuf
 flatten
 synth
-equiv_opt -assert -map +/nanoxplore/cells_sim.v -map +/simcells.v synth_nanoxplore # equivalency check
+equiv_opt -assert -map +/nanoxplore/cells_sim.v -map +/simcells.v synth_nanoxplore -iopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
 #Internal cell type used. Need support it.
-select -assert-count 1 t:$_TBUF_
-select -assert-none t:$_TBUF_ %% t:* %D
+select -assert-count 1 t:NX_IOB
+select -assert-count 2 t:NX_IOB_I
+select -assert-none t:NX_IOB t:NX_IOB_I %% t:* %D

From 04d36721213556403d6464e521e5fa382e63ee6d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 9 May 2024 14:01:53 +0200
Subject: [PATCH 311/499] No need for LOC

---
 techlibs/nanoxplore/synth_nanoxplore.cc | 2 --
 1 file changed, 2 deletions(-)

diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index 52d0256031e..9dd8011cc53 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -294,8 +294,6 @@ struct SynthNanoXplorePass : public ScriptPass
 			if (help_mode || iopad) {
 				run("iopadmap -bits -outpad $__BEYOND_OBUF I:PAD -toutpad $__BEYOND_TOBUF C:I:PAD -inpad $__BEYOND_IBUF O:PAD -tinoutpad $__BEYOND_IOBUF C:O:I:PAD A:top", "(only if '-iopad')");
 				run("techmap -map +/nanoxplore/io_map.v");
-				run("attrmvcp -attr LOC t:NX_IOB_O t:NX_IOB n:*");
-				run("attrmvcp -attr LOC -driven t:NX_IOB_I t:NX_IOB n:*");
 			}
 			run("opt -fast");
 		}

From f9f68c3cd1504fc6b7959a4d976628ac68795b28 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 10 May 2024 11:15:56 +0200
Subject: [PATCH 312/499] Split sim models into multiple files and implement
 few

---
 techlibs/nanoxplore/Makefile.inc        |  3 +
 techlibs/nanoxplore/cells_bb.v          | 45 +++++++--------
 techlibs/nanoxplore/cells_bb_u.v        | 11 ----
 techlibs/nanoxplore/cells_sim.v         | 76 +++++++++----------------
 techlibs/nanoxplore/cells_sim_l.v       |  0
 techlibs/nanoxplore/cells_sim_m.v       |  0
 techlibs/nanoxplore/cells_sim_u.v       | 30 ++++++++++
 techlibs/nanoxplore/synth_nanoxplore.cc |  2 +-
 8 files changed, 84 insertions(+), 83 deletions(-)
 create mode 100644 techlibs/nanoxplore/cells_sim_l.v
 create mode 100644 techlibs/nanoxplore/cells_sim_m.v
 create mode 100644 techlibs/nanoxplore/cells_sim_u.v

diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc
index 180922a50a7..3370adef70c 100644
--- a/techlibs/nanoxplore/Makefile.inc
+++ b/techlibs/nanoxplore/Makefile.inc
@@ -12,6 +12,9 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_m.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_u.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim_l.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim_m.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim_u.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v))
diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index 42953b6b202..2f6ae1ec25f 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -28,12 +28,12 @@
 //endmodule
 
 // Bypass mode of NX_GCK_U
-(* blackbox *)
-module NX_BD(I, O);
-    input I;
-    output O;
-    parameter mode = "global_lowskew";
-endmodule
+//(* blackbox *)
+//module NX_BD(I, O);
+//    input I;
+//    output O;
+//    parameter mode = "global_lowskew";
+//endmodule
 
 //(* blackbox *)
 //module NX_DFF(I, CK, L, R, O);
@@ -51,12 +51,11 @@ endmodule
 //endmodule
 
 // Special mode of NX_DFF
-(* blackbox *)
-module NX_BFF(I, O);
-    input I;
-    output O;
-endmodule
-
+//(* blackbox *)
+//module NX_BFF(I, O);
+//    input I;
+//    output O;
+//endmodule
 
 (* blackbox *)
 module NX_DFR(I, CK, L, R, O);
@@ -79,17 +78,17 @@ module NX_DFR(I, CK, L, R, O);
 endmodule
 
 // Special mode of NX_DFR
-(* blackbox *)
-module NX_BFR(I, O);
-    input I;
-    output O;
-    parameter data_inv = 1'b0;
-    parameter iobname = "";
-    parameter location = "";
-    parameter mode = 0;
-    parameter path = 0;
-    parameter ring = 0;
-endmodule
+//(* blackbox *)
+//module NX_BFR(I, O);
+//    input I;
+//    output O;
+//    parameter data_inv = 1'b0;
+//    parameter iobname = "";
+//    parameter location = "";
+//    parameter mode = 0;
+//    parameter path = 0;
+//    parameter ring = 0;
+//endmodule
 
 (* blackbox *)
 module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13
diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v
index 5c1e8bcb0dd..2cc16f410e2 100644
--- a/techlibs/nanoxplore/cells_bb_u.v
+++ b/techlibs/nanoxplore/cells_bb_u.v
@@ -1,14 +1,3 @@
-(* blackbox *)
-module NX_GCK_U(SI1, SI2, CMD, SO);
-    input CMD;
-    input SI1;
-    input SI2;
-    output SO;
-    parameter inv_in = 1'b0;
-    parameter inv_out = 1'b0;
-    parameter std_mode = "BYPASS";
-endmodule
-
 (* blackbox *)
 module NX_CDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BSRSTI, BDRSTI, BSRSTO
 , BDRSTO, BI1, BI2, BI3, BI4, BI5, BI6, BO1, BO2, BO3, BO4, BO5, BO6, CSRSTI, CDRSTI, CSRSTO, CDRSTO, CI1, CI2, CI3, CI4
diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v
index de3cffcc8dd..392ee18e4e3 100644
--- a/techlibs/nanoxplore/cells_sim.v
+++ b/techlibs/nanoxplore/cells_sim.v
@@ -52,54 +52,6 @@ assign { CO,  S4 } = A4 + B4 + CO3;
 
 endmodule
 
-(* abc9_box, lib_whitebox *)
-module NX_XRFB_64x18(input WCK, input [17:0] I, input [5:0] RA, WA, input WE, WEA, output [17:0] O);
-
-parameter wck_edge = 1'b0;
-parameter mem_ctxt = 1152'b0;
-
-reg [17:0] mem [63:0];
-
-integer i;
-initial begin
-	for (i = 0; i < 64; i = i + 1)
-		mem[i] = mem_ctxt[18*i +: 18];
-end
-
-wire clock = WCK ^ wck_edge;
-
-always @(posedge clock)
-	if (WE && WEA)
-		mem[WA] <= I;
-
-assign O = mem[RA];
-
-endmodule
-
-(* abc9_box, lib_whitebox *)
-module NX_XRFB_32x36(input WCK, input [35:0] I, input [4:0] RA, WA, input WE, WEA, output [35:0] O);
-
-parameter wck_edge = 1'b0;
-parameter mem_ctxt = 1152'b0;
-
-reg [35:0] mem [31:0];
-
-integer i;
-initial begin
-	for (i = 0; i < 32; i = i + 1)
-		mem[i] = mem_ctxt[36*i +: 36];
-end
-
-wire clock = WCK ^ wck_edge;
-
-always @(posedge clock)
-	if (WE && WEA)
-		mem[WA] <= I;
-
-assign O = mem[RA];
-
-endmodule
-
 module NX_IOB(I, C, T, O, IO);
     input C;
     input I;
@@ -205,3 +157,31 @@ module NX_CY_1BIT(CI, A, B, S, CO);
 
     assign {CO, S} = A + B + CI;
 endmodule
+
+module NX_BD(I, O);
+    input I;
+    output O;
+    parameter mode = "global_lowskew";
+
+    assign O = I;
+endmodule
+
+module NX_BFF(I, O);
+    input I;
+    output O;
+
+    assign O = I;
+endmodule
+
+module NX_BFR(I, O);
+    input I;
+    output O;
+    parameter data_inv = 1'b0;
+    parameter iobname = "";
+    parameter location = "";
+    parameter mode = 0;
+    parameter path = 0;
+    parameter ring = 0;
+
+    assign O = data_inv ? ~I : I;
+endmodule
diff --git a/techlibs/nanoxplore/cells_sim_l.v b/techlibs/nanoxplore/cells_sim_l.v
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/techlibs/nanoxplore/cells_sim_m.v b/techlibs/nanoxplore/cells_sim_m.v
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v
new file mode 100644
index 00000000000..794dd4e6a60
--- /dev/null
+++ b/techlibs/nanoxplore/cells_sim_u.v
@@ -0,0 +1,30 @@
+module NX_GCK_U(SI1, SI2, CMD, SO);
+    input CMD;
+    input SI1;
+    input SI2;
+    output SO;
+    parameter inv_in = 1'b0;
+    parameter inv_out = 1'b0;
+    parameter std_mode = "BYPASS";
+
+    wire SI1_int = inv_in ? ~SI1 : SI1;
+    wire SI2_int = inv_in ? ~SI2 : SI2;
+
+    wire SO_int;
+    generate if (std_mode == "BYPASS") begin
+        assign SO_int = SI1_int;
+    end
+    else if (std_mode == "MUX") begin
+        assign SO_int = CMD ? SI1_int : SI2_int;
+    end
+    else if (std_mode == "CKS") begin
+        assign SO_int = CMD ? SI1_int : 1'b0;
+    end
+    else if (std_mode == "CSC") begin
+        assign SO_int = CMD;
+    end
+    else
+    $error("Unrecognised std_mode");
+    endgenerate
+    assign SO = inv_out ? ~SO_int : SO_int;
+endmodule
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index 9dd8011cc53..054ca5b0d5a 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -229,7 +229,7 @@ struct SynthNanoXplorePass : public ScriptPass
 
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v");
+			run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim" + postfix + ".v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v");
 			run("techmap -map +/nanoxplore/cells_wrap.v");
 			run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));

From 11449ec493a1d1f84d38423bbb40a35bd9eb949c Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 15 May 2024 15:55:26 +0200
Subject: [PATCH 313/499] Cleanup not connected ports

---
 techlibs/nanoxplore/cells_wrap_u.v | 334 ++++++++++++++---------------
 1 file changed, 167 insertions(+), 167 deletions(-)

diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v
index b753c54660a..74adfaa5173 100644
--- a/techlibs/nanoxplore/cells_wrap_u.v
+++ b/techlibs/nanoxplore/cells_wrap_u.v
@@ -10,7 +10,7 @@ NX_GCK_U #(
 ) _TECHMAP_REPLACE_ (
     .CMD(CMD),
     .SI1(CKI),
-    .SI2(1'b0),
+    .SI2(),
     .SO(CKO)
 );
 endmodule
@@ -1495,24 +1495,24 @@ module NX_RFBDP_U_WRAP(WCK, WE, WEA, I, O, RA, WA);
     .I16(I[15]),
     .I17(I[16]),
     .I18(I[17]),
-    .I19(1'b0),
-    .I20(1'b0),
-    .I21(1'b0),
-    .I22(1'b0),
-    .I23(1'b0),
-    .I24(1'b0),
-    .I25(1'b0),
-    .I26(1'b0),
-    .I27(1'b0),
-    .I28(1'b0),
-    .I29(1'b0),
-    .I30(1'b0),
-    .I31(1'b0),
-    .I32(1'b0),
-    .I33(1'b0),
-    .I34(1'b0),
-    .I35(1'b0),
-    .I36(1'b0),
+    .I19(),
+    .I20(),
+    .I21(),
+    .I22(),
+    .I23(),
+    .I24(),
+    .I25(),
+    .I26(),
+    .I27(),
+    .I28(),
+    .I29(),
+    .I30(),
+    .I31(),
+    .I32(),
+    .I33(),
+    .I34(),
+    .I35(),
+    .I36(),
     .O1(O[0]),
     .O2(O[1]),
     .O3(O[2]),
@@ -1536,17 +1536,17 @@ module NX_RFBDP_U_WRAP(WCK, WE, WEA, I, O, RA, WA);
     .RA3(RA[2]),
     .RA4(RA[3]),
     .RA5(RA[4]),
-    .RA6(1'b0),
-    .RA7(1'b0),
-    .RA8(1'b0),
-    .RA9(1'b0),
-    .RA10(1'b0),
+    .RA6(),
+    .RA7(),
+    .RA8(),
+    .RA9(),
+    .RA10(),
     .WA1(WA[0]),
     .WA2(WA[1]),
     .WA3(WA[2]),
     .WA4(WA[3]),
     .WA5(WA[4]),
-    .WA6(1'b0),
+    .WA6(),
     .WE(WE),
     .WEA(WEA)
   );
@@ -1587,24 +1587,24 @@ module NX_RFBSP_U_WRAP(WCK, WE, WEA, I, O, WA);
     .I16(I[15]),
     .I17(I[16]),
     .I18(I[17]),
-    .I19(1'b0),
-    .I20(1'b0),
-    .I21(1'b0),
-    .I22(1'b0),
-    .I23(1'b0),
-    .I24(1'b0),
-    .I25(1'b0),
-    .I26(1'b0),
-    .I27(1'b0),
-    .I28(1'b0),
-    .I29(1'b0),
-    .I30(1'b0),
-    .I31(1'b0),
-    .I32(1'b0),
-    .I33(1'b0),
-    .I34(1'b0),
-    .I35(1'b0),
-    .I36(1'b0),
+    .I19(),
+    .I20(),
+    .I21(),
+    .I22(),
+    .I23(),
+    .I24(),
+    .I25(),
+    .I26(),
+    .I27(),
+    .I28(),
+    .I29(),
+    .I30(),
+    .I31(),
+    .I32(),
+    .I33(),
+    .I34(),
+    .I35(),
+    .I36(),
     .O1(O[0]),
     .O2(O[1]),
     .O3(O[2]),
@@ -1623,22 +1623,22 @@ module NX_RFBSP_U_WRAP(WCK, WE, WEA, I, O, WA);
     .O16(O[15]),
     .O17(O[16]),
     .O18(O[17]),
-    .RA1(1'b0),
-    .RA2(1'b0),
-    .RA3(1'b0),
-    .RA4(1'b0),
-    .RA5(1'b0),
-    .RA6(1'b0),
-    .RA7(1'b0),
-    .RA8(1'b0),
-    .RA9(1'b0),
-    .RA10(1'b0),
+    .RA1(),
+    .RA2(),
+    .RA3(),
+    .RA4(),
+    .RA5(),
+    .RA6(),
+    .RA7(),
+    .RA8(),
+    .RA9(),
+    .RA10(),
     .WA1(WA[0]),
     .WA2(WA[1]),
     .WA3(WA[2]),
     .WA4(WA[3]),
     .WA5(WA[4]),
-    .WA6(1'b0),
+    .WA6(),
     .WE(WE),
     .WEA(WEA)
   );
@@ -1679,24 +1679,24 @@ module NX_XRFB_64x18(WCK, WE, WEA, I, O, RA, WA);
     .I16(I[15]),
     .I17(I[16]),
     .I18(I[17]),
-    .I19(1'b0),
-    .I20(1'b0),
-    .I21(1'b0),
-    .I22(1'b0),
-    .I23(1'b0),
-    .I24(1'b0),
-    .I25(1'b0),
-    .I26(1'b0),
-    .I27(1'b0),
-    .I28(1'b0),
-    .I29(1'b0),
-    .I30(1'b0),
-    .I31(1'b0),
-    .I32(1'b0),
-    .I33(1'b0),
-    .I34(1'b0),
-    .I35(1'b0),
-    .I36(1'b0),
+    .I19(),
+    .I20(),
+    .I21(),
+    .I22(),
+    .I23(),
+    .I24(),
+    .I25(),
+    .I26(),
+    .I27(),
+    .I28(),
+    .I29(),
+    .I30(),
+    .I31(),
+    .I32(),
+    .I33(),
+    .I34(),
+    .I35(),
+    .I36(),
     .O1(O[0]),
     .O2(O[1]),
     .O3(O[2]),
@@ -1721,10 +1721,10 @@ module NX_XRFB_64x18(WCK, WE, WEA, I, O, RA, WA);
     .RA4(RA[3]),
     .RA5(RA[4]),
     .RA6(RA[5]),
-    .RA7(1'b0),
-    .RA8(1'b0),
-    .RA9(1'b0),
-    .RA10(1'b0),
+    .RA7(),
+    .RA8(),
+    .RA9(),
+    .RA10(),
     .WA1(WA[0]),
     .WA2(WA[1]),
     .WA3(WA[2]),
@@ -1830,17 +1830,17 @@ module NX_XRFB_32x36(WCK, WE, WEA, I, O, RA, WA);
     .RA3(RA[2]),
     .RA4(RA[3]),
     .RA5(RA[4]),
-    .RA6(1'b0),
-    .RA7(1'b0),
-    .RA8(1'b0),
-    .RA9(1'b0),
-    .RA10(1'b0),
+    .RA6(),
+    .RA7(),
+    .RA8(),
+    .RA9(),
+    .RA10(),
     .WA1(WA[0]),
     .WA2(WA[1]),
     .WA3(WA[2]),
     .WA4(WA[3]),
     .WA5(WA[4]),
-    .WA6(1'b0),
+    .WA6(),
     .WE(WE),
     .WEA(WEA)
   );
@@ -1883,24 +1883,24 @@ module NX_XRFB_2R_1W(WCK, WE, WEA, I, AO, BO, WA, ARA, BRA);
     .I16(I[15]),
     .I17(I[16]),
     .I18(I[17]),
-    .I19(1'b0),
-    .I20(1'b0),
-    .I21(1'b0),
-    .I22(1'b0),
-    .I23(1'b0),
-    .I24(1'b0),
-    .I25(1'b0),
-    .I26(1'b0),
-    .I27(1'b0),
-    .I28(1'b0),
-    .I29(1'b0),
-    .I30(1'b0),
-    .I31(1'b0),
-    .I32(1'b0),
-    .I33(1'b0),
-    .I34(1'b0),
-    .I35(1'b0),
-    .I36(1'b0),
+    .I19(),
+    .I20(),
+    .I21(),
+    .I22(),
+    .I23(),
+    .I24(),
+    .I25(),
+    .I26(),
+    .I27(),
+    .I28(),
+    .I29(),
+    .I30(),
+    .I31(),
+    .I32(),
+    .I33(),
+    .I34(),
+    .I35(),
+    .I36(),
     .O1(AO[0]),
     .O2(AO[1]),
     .O3(AO[2]),
@@ -1952,7 +1952,7 @@ module NX_XRFB_2R_1W(WCK, WE, WEA, I, AO, BO, WA, ARA, BRA);
     .WA3(WA[2]),
     .WA4(WA[3]),
     .WA5(WA[4]),
-    .WA6(1'b0),
+    .WA6(),
     .WE(WE),
     .WEA(WEA)
   );
@@ -2043,26 +2043,26 @@ module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13,
     .I14(I14),
     .I15(I15),
     .I16(I16),
-    .I17(1'b0),
-    .I18(1'b0),
-    .I19(1'b0),
-    .I20(1'b0),
-    .I21(1'b0),
-    .I22(1'b0),
-    .I23(1'b0),
-    .I24(1'b0),
-    .I25(1'b0),
-    .I26(1'b0),
-    .I27(1'b0),
-    .I28(1'b0),
-    .I29(1'b0),
-    .I30(1'b0),
-    .I31(1'b0),
-    .I32(1'b0),
-    .I33(1'b0),
-    .I34(1'b0),
-    .I35(1'b0),
-    .I36(1'b0),
+    .I17(),
+    .I18(),
+    .I19(),
+    .I20(),
+    .I21(),
+    .I22(),
+    .I23(),
+    .I24(),
+    .I25(),
+    .I26(),
+    .I27(),
+    .I28(),
+    .I29(),
+    .I30(),
+    .I31(),
+    .I32(),
+    .I33(),
+    .I34(),
+    .I35(),
+    .I36(),
     .O1(D[0]),
     .O2(D[1]),
     .O3(D[2]),
@@ -2085,10 +2085,10 @@ module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13,
     .RA4(RA4),
     .RA5(RA5),
     .RA6(RA6),
-    .RA7(1'b0),
-    .RA8(1'b0),
-    .RA9(1'b0),
-    .RA10(1'b0),
+    .RA7(),
+    .RA8(),
+    .RA9(),
+    .RA10(),
     .WA1(WA1),
     .WA2(WA2),
     .WA3(WA3),
@@ -2096,7 +2096,7 @@ module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13,
     .WA5(WA5),
     .WA6(WA6),
     .WE(WE),
-    .WEA(1'b0)
+    .WEA()
   );
 
   genvar i;
@@ -2109,7 +2109,7 @@ module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13,
         .CK(RCK),
         .I(D[i]),
         .L(RE),
-        .R(1'b0),
+        .R(),
         .O(Q[i])
     );
   end endgenerate;
@@ -2187,24 +2187,24 @@ module NX_FIFO_DPREG(RCK, WCK, WE, WEA, WRSTI, WRSTO, WEQ, RRSTI, RRSTO, REQ, I,
     .I16(I[15]),
     .I17(I[16]),
     .I18(I[17]),
-    .I19(1'b0),
-    .I20(1'b0),
-    .I21(1'b0),
-    .I22(1'b0),
-    .I23(1'b0),
-    .I24(1'b0),
-    .I25(1'b0),
-    .I26(1'b0),
-    .I27(1'b0),
-    .I28(1'b0),
-    .I29(1'b0),
-    .I30(1'b0),
-    .I31(1'b0),
-    .I32(1'b0),
-    .I33(1'b0),
-    .I34(1'b0),
-    .I35(1'b0),
-    .I36(1'b0),
+    .I19(),
+    .I20(),
+    .I21(),
+    .I22(),
+    .I23(),
+    .I24(),
+    .I25(),
+    .I26(),
+    .I27(),
+    .I28(),
+    .I29(),
+    .I30(),
+    .I31(),
+    .I32(),
+    .I33(),
+    .I34(),
+    .I35(),
+    .I36(),
     .O1(O[0]),
     .O2(O[1]),
     .O3(O[2]),
@@ -2230,7 +2230,7 @@ module NX_FIFO_DPREG(RCK, WCK, WE, WEA, WRSTI, WRSTO, WEQ, RRSTI, RRSTO, REQ, I,
     .WAI4(WAI[3]),
     .WAI5(WAI[4]),
     .WAI6(WAI[5]),
-    .WAI7(1'b0),
+    .WAI7(),
     .WRSTO(WRSTO),
     .WAO1(WAO[0]),
     .WAO2(WAO[1]),
@@ -2246,7 +2246,7 @@ module NX_FIFO_DPREG(RCK, WCK, WE, WEA, WRSTI, WRSTO, WEQ, RRSTI, RRSTO, REQ, I,
     .RAI4(RAI[3]),
     .RAI5(RAI[4]),
     .RAI6(RAI[5]),
-    .RAI7(1'b0),
+    .RAI7(),
     .RRSTO(RRSTO),
     .RAO1(RAO[0]),
     .RAO2(RAO[1]),
@@ -2309,24 +2309,24 @@ module NX_XFIFO_64x18(RCK, WCK, WE, WEA, WRSTI, RRSTI, I, O, WEQ, REQ, WAI, WAO,
     .I16(I[15]),
     .I17(I[16]),
     .I18(I[17]),
-    .I19(1'b0),
-    .I20(1'b0),
-    .I21(1'b0),
-    .I22(1'b0),
-    .I23(1'b0),
-    .I24(1'b0),
-    .I25(1'b0),
-    .I26(1'b0),
-    .I27(1'b0),
-    .I28(1'b0),
-    .I29(1'b0),
-    .I30(1'b0),
-    .I31(1'b0),
-    .I32(1'b0),
-    .I33(1'b0),
-    .I34(1'b0),
-    .I35(1'b0),
-    .I36(1'b0),
+    .I19(),
+    .I20(),
+    .I21(),
+    .I22(),
+    .I23(),
+    .I24(),
+    .I25(),
+    .I26(),
+    .I27(),
+    .I28(),
+    .I29(),
+    .I30(),
+    .I31(),
+    .I32(),
+    .I33(),
+    .I34(),
+    .I35(),
+    .I36(),
     .O1(O[0]),
     .O2(O[1]),
     .O3(O[2]),
@@ -2494,7 +2494,7 @@ module NX_XFIFO_32x36(RCK, WCK, WE, WEA, WRSTI, WEQ, RRSTI, REQ, I, O, WAI, WAO,
     .WAI4(WAI[3]),
     .WAI5(WAI[4]),
     .WAI6(WAI[5]),
-    .WAI7(1'b0),
+    .WAI7(),
     .WAO1(WAO[0]),
     .WAO2(WAO[1]),
     .WAO3(WAO[2]),
@@ -2509,7 +2509,7 @@ module NX_XFIFO_32x36(RCK, WCK, WE, WEA, WRSTI, WEQ, RRSTI, REQ, I, O, WAI, WAO,
     .RAI4(RAI[3]),
     .RAI5(RAI[4]),
     .RAI6(RAI[5]),
-    .RAI7(1'b0),
+    .RAI7(),
     .RAO1(RAO[0]),
     .RAO2(RAO[1]),
     .RAO3(RAO[2]),

From 7e4aef06e469de70baf73d8e62ade29ec4e6beb1 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 16 May 2024 17:15:55 +0200
Subject: [PATCH 314/499] Add register file mapping

---
 techlibs/nanoxplore/rf_rams_map_u.v | 339 ++++++++++++++++++++++++++--
 techlibs/nanoxplore/rf_rams_u.txt   |  64 +++++-
 tests/arch/nanoxplore/lutram.ys     |  64 +++++-
 3 files changed, 428 insertions(+), 39 deletions(-)

diff --git a/techlibs/nanoxplore/rf_rams_map_u.v b/techlibs/nanoxplore/rf_rams_map_u.v
index 94d5df09795..b55d3e594bb 100644
--- a/techlibs/nanoxplore/rf_rams_map_u.v
+++ b/techlibs/nanoxplore/rf_rams_map_u.v
@@ -1,50 +1,339 @@
 
-module $__NX_XRFB_64x18_ (
+module $__NX_RFB_U_DPREG_ (
   input PORT_W_CLK,
-  input [5:0] PORT_W_ADDR,
-  input [5:0] PORT_R_ADDR,
-  input [17:0] PORT_W_WR_DATA,
+  input [6-1:0] PORT_W_ADDR,
+  input [6-1:0] PORT_R_ADDR,
+  input [36-1:0] PORT_W_WR_DATA,
   input PORT_W_WR_EN,
-  output [17:0] PORT_R_RD_DATA
+  output [36-1:0] PORT_R_RD_DATA
 );
   parameter INIT = 1152'bx;
   parameter PORT_W_CLK_POL = 1'b1;
-  
-  NX_XRFB_64x18 #(
+  parameter OPTION_MODE = 0;
+  parameter WIDTH = 18;
+  parameter BITS_USED = 0;
+
+  // mode 0 - DPREG
+  // mode 2 - NX_XRFB_64x18
+  // mode 3 - NX_XRFB_32x36
+  NX_RFB_U #(
+    .mode(OPTION_MODE),
     .mem_ctxt(INIT),
-    .wck_edge(~PORT_W_CLK_POL)
+    .wck_edge(PORT_W_CLK_POL == 1 ? 1'b0 : 1'b1)
   ) _TECHMAP_REPLACE_ (
     .WCK(PORT_W_CLK),
-    .I(PORT_W_WR_DATA),
-    .RA(PORT_R_ADDR),
-    .WA(PORT_W_ADDR),
+    .I1(PORT_W_WR_DATA[0]),
+    .I2(PORT_W_WR_DATA[1]),
+    .I3(PORT_W_WR_DATA[2]),
+    .I4(PORT_W_WR_DATA[3]),
+    .I5(PORT_W_WR_DATA[4]),
+    .I6(PORT_W_WR_DATA[5]),
+    .I7(PORT_W_WR_DATA[6]),
+    .I8(PORT_W_WR_DATA[7]),
+    .I9(PORT_W_WR_DATA[8]),
+    .I10(PORT_W_WR_DATA[9]),
+    .I11(PORT_W_WR_DATA[10]),
+    .I12(PORT_W_WR_DATA[11]),
+    .I13(PORT_W_WR_DATA[12]),
+    .I14(PORT_W_WR_DATA[13]),
+    .I15(PORT_W_WR_DATA[14]),
+    .I16(PORT_W_WR_DATA[15]),
+    .I17(PORT_W_WR_DATA[16]),
+    .I18(PORT_W_WR_DATA[17]),
+    .I19(PORT_W_WR_DATA[18]),
+    .I20(PORT_W_WR_DATA[19]),
+    .I21(PORT_W_WR_DATA[20]),
+    .I22(PORT_W_WR_DATA[21]),
+    .I23(PORT_W_WR_DATA[22]),
+    .I24(PORT_W_WR_DATA[23]),
+    .I25(PORT_W_WR_DATA[24]),
+    .I26(PORT_W_WR_DATA[25]),
+    .I27(PORT_W_WR_DATA[26]),
+    .I28(PORT_W_WR_DATA[27]),
+    .I29(PORT_W_WR_DATA[28]),
+    .I30(PORT_W_WR_DATA[29]),
+    .I31(PORT_W_WR_DATA[30]),
+    .I32(PORT_W_WR_DATA[31]),
+    .I33(PORT_W_WR_DATA[32]),
+    .I34(PORT_W_WR_DATA[33]),
+    .I35(PORT_W_WR_DATA[34]),
+    .I36(PORT_W_WR_DATA[35]),
+    .O1(PORT_R_RD_DATA[0]),
+    .O2(PORT_R_RD_DATA[1]),
+    .O3(PORT_R_RD_DATA[2]),
+    .O4(PORT_R_RD_DATA[3]),
+    .O5(PORT_R_RD_DATA[4]),
+    .O6(PORT_R_RD_DATA[5]),
+    .O7(PORT_R_RD_DATA[6]),
+    .O8(PORT_R_RD_DATA[7]),
+    .O9(PORT_R_RD_DATA[8]),
+    .O10(PORT_R_RD_DATA[9]),
+    .O11(PORT_R_RD_DATA[10]),
+    .O12(PORT_R_RD_DATA[11]),
+    .O13(PORT_R_RD_DATA[12]),
+    .O14(PORT_R_RD_DATA[13]),
+    .O15(PORT_R_RD_DATA[14]),
+    .O16(PORT_R_RD_DATA[15]),
+    .O17(PORT_R_RD_DATA[16]),
+    .O18(PORT_R_RD_DATA[17]),
+    .O19(PORT_R_RD_DATA[18]),
+    .O20(PORT_R_RD_DATA[19]),
+    .O21(PORT_R_RD_DATA[20]),
+    .O22(PORT_R_RD_DATA[21]),
+    .O23(PORT_R_RD_DATA[22]),
+    .O24(PORT_R_RD_DATA[23]),
+    .O25(PORT_R_RD_DATA[24]),
+    .O26(PORT_R_RD_DATA[25]),
+    .O27(PORT_R_RD_DATA[26]),
+    .O28(PORT_R_RD_DATA[27]),
+    .O29(PORT_R_RD_DATA[28]),
+    .O30(PORT_R_RD_DATA[29]),
+    .O31(PORT_R_RD_DATA[30]),
+    .O32(PORT_R_RD_DATA[31]),
+    .O33(PORT_R_RD_DATA[32]),
+    .O34(PORT_R_RD_DATA[33]),
+    .O35(PORT_R_RD_DATA[34]),
+    .O36(PORT_R_RD_DATA[35]),
+    .RA1(PORT_R_ADDR[0]),
+    .RA2(PORT_R_ADDR[1]),
+    .RA3(PORT_R_ADDR[2]),
+    .RA4(PORT_R_ADDR[3]),
+    .RA5(PORT_R_ADDR[4]),
+    .RA6(PORT_R_ADDR[5]),
+    .RA7(),
+    .RA8(),
+    .RA9(),
+    .RA10(),
+    .WA1(PORT_W_ADDR[0]),
+    .WA2(PORT_W_ADDR[1]),
+    .WA3(PORT_W_ADDR[2]),
+    .WA4(PORT_W_ADDR[3]),
+    .WA5(PORT_W_ADDR[4]),
+    .WA6(PORT_W_ADDR[5]),
     .WE(PORT_W_WR_EN),
-    .WEA(1'b1),
-    .O(PORT_R_RD_DATA)
+    .WEA(1'b0)
+  );
+endmodule
+
+module $__NX_RFB_U_SPREG_ (
+  input PORT_RW_CLK,
+  input [4:0] PORT_RW_ADDR,
+  input [17:0] PORT_RW_WR_DATA,
+  input PORT_RW_WR_EN,
+  output [17:0] PORT_RW_RD_DATA
+);
+  parameter INIT = 1152'bx;
+  parameter PORT_RW_CLK_POL = 1'b1;
+  parameter BITS_USED = 0;
+
+  NX_RFB_U #(
+    .mode(1),
+    .mem_ctxt(INIT),
+    .wck_edge(PORT_RW_CLK_POL == 1 ? 1'b0 : 1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .WCK(PORT_RW_CLK),
+    .I1(PORT_RW_WR_DATA[0]),
+    .I2(PORT_RW_WR_DATA[1]),
+    .I3(PORT_RW_WR_DATA[2]),
+    .I4(PORT_RW_WR_DATA[3]),
+    .I5(PORT_RW_WR_DATA[4]),
+    .I6(PORT_RW_WR_DATA[5]),
+    .I7(PORT_RW_WR_DATA[6]),
+    .I8(PORT_RW_WR_DATA[7]),
+    .I9(PORT_RW_WR_DATA[8]),
+    .I10(PORT_RW_WR_DATA[9]),
+    .I11(PORT_RW_WR_DATA[10]),
+    .I12(PORT_RW_WR_DATA[11]),
+    .I13(PORT_RW_WR_DATA[12]),
+    .I14(PORT_RW_WR_DATA[13]),
+    .I15(PORT_RW_WR_DATA[14]),
+    .I16(PORT_RW_WR_DATA[15]),
+    .I17(PORT_RW_WR_DATA[16]),
+    .I18(PORT_RW_WR_DATA[17]),
+    .I19(),
+    .I20(),
+    .I21(),
+    .I22(),
+    .I23(),
+    .I24(),
+    .I25(),
+    .I26(),
+    .I27(),
+    .I28(),
+    .I29(),
+    .I30(),
+    .I31(),
+    .I32(),
+    .I33(),
+    .I34(),
+    .I35(),
+    .I36(),
+    .O1(PORT_RW_RD_DATA[0]),
+    .O2(PORT_RW_RD_DATA[1]),
+    .O3(PORT_RW_RD_DATA[2]),
+    .O4(PORT_RW_RD_DATA[3]),
+    .O5(PORT_RW_RD_DATA[4]),
+    .O6(PORT_RW_RD_DATA[5]),
+    .O7(PORT_RW_RD_DATA[6]),
+    .O8(PORT_RW_RD_DATA[7]),
+    .O9(PORT_RW_RD_DATA[8]),
+    .O10(PORT_RW_RD_DATA[9]),
+    .O11(PORT_RW_RD_DATA[10]),
+    .O12(PORT_RW_RD_DATA[11]),
+    .O13(PORT_RW_RD_DATA[12]),
+    .O14(PORT_RW_RD_DATA[13]),
+    .O15(PORT_RW_RD_DATA[14]),
+    .O16(PORT_RW_RD_DATA[15]),
+    .O17(PORT_RW_RD_DATA[16]),
+    .O18(PORT_RW_RD_DATA[17]),
+    .O19(),
+    .O20(),
+    .O21(),
+    .O22(),
+    .O23(),
+    .O24(),
+    .O25(),
+    .O26(),
+    .O27(),
+    .O28(),
+    .O29(),
+    .O30(),
+    .O31(),
+    .O32(),
+    .O33(),
+    .O34(),
+    .O35(),
+    .O36(),
+    .RA1(),
+    .RA2(),
+    .RA3(),
+    .RA4(),
+    .RA5(),
+    .RA6(),
+    .RA7(),
+    .RA8(),
+    .RA9(),
+    .RA10(),
+    .WA1(PORT_RW_ADDR[0]),
+    .WA2(PORT_RW_ADDR[1]),
+    .WA3(PORT_RW_ADDR[2]),
+    .WA4(PORT_RW_ADDR[3]),
+    .WA5(PORT_RW_ADDR[4]),
+    .WA6(),
+    .WE(PORT_RW_WR_EN),
+    .WEA(1'b0)
   );
 endmodule
 
-module $__NX_XRFB_32x36_ (
+module $__NX_XRFB_2R_1W_ (
   input PORT_W_CLK,
   input [4:0] PORT_W_ADDR,
-  input [4:0] PORT_R_ADDR,
-  input [35:0] PORT_W_WR_DATA,
+  input [4:0] PORT_A_ADDR,
+  input [4:0] PORT_B_ADDR,
+  input [17:0] PORT_W_WR_DATA,
   input PORT_W_WR_EN,
-  output [35:0] PORT_R_RD_DATA
+  output [17:0] PORT_A_RD_DATA,
+  output [17:0] PORT_B_RD_DATA
 );
   parameter INIT = 1152'bx;
   parameter PORT_W_CLK_POL = 1'b1;
+  parameter BITS_USED = 0;
 
-  NX_XRFB_32x36 #(
+  NX_RFB_U #(
+    .mode(4),
     .mem_ctxt(INIT),
-    .wck_edge(~PORT_W_CLK_POL)
+    .wck_edge(PORT_W_CLK_POL == 1 ? 1'b0 : 1'b1)
   ) _TECHMAP_REPLACE_ (
     .WCK(PORT_W_CLK),
-    .I(PORT_W_WR_DATA),
-    .RA(PORT_R_ADDR),
-    .WA(PORT_W_ADDR),
+    .I1(PORT_W_WR_DATA[0]),
+    .I2(PORT_W_WR_DATA[1]),
+    .I3(PORT_W_WR_DATA[2]),
+    .I4(PORT_W_WR_DATA[3]),
+    .I5(PORT_W_WR_DATA[4]),
+    .I6(PORT_W_WR_DATA[5]),
+    .I7(PORT_W_WR_DATA[6]),
+    .I8(PORT_W_WR_DATA[7]),
+    .I9(PORT_W_WR_DATA[8]),
+    .I10(PORT_W_WR_DATA[9]),
+    .I11(PORT_W_WR_DATA[10]),
+    .I12(PORT_W_WR_DATA[11]),
+    .I13(PORT_W_WR_DATA[12]),
+    .I14(PORT_W_WR_DATA[13]),
+    .I15(PORT_W_WR_DATA[14]),
+    .I16(PORT_W_WR_DATA[15]),
+    .I17(PORT_W_WR_DATA[16]),
+    .I18(PORT_W_WR_DATA[17]),
+    .I19(),
+    .I20(),
+    .I21(),
+    .I22(),
+    .I23(),
+    .I24(),
+    .I25(),
+    .I26(),
+    .I27(),
+    .I28(),
+    .I29(),
+    .I30(),
+    .I31(),
+    .I32(),
+    .I33(),
+    .I34(),
+    .I35(),
+    .I36(),
+    .O1(PORT_A_RD_DATA[0]),
+    .O2(PORT_A_RD_DATA[1]),
+    .O3(PORT_A_RD_DATA[2]),
+    .O4(PORT_A_RD_DATA[3]),
+    .O5(PORT_A_RD_DATA[4]),
+    .O6(PORT_A_RD_DATA[5]),
+    .O7(PORT_A_RD_DATA[6]),
+    .O8(PORT_A_RD_DATA[7]),
+    .O9(PORT_A_RD_DATA[8]),
+    .O10(PORT_A_RD_DATA[9]),
+    .O11(PORT_A_RD_DATA[10]),
+    .O12(PORT_A_RD_DATA[11]),
+    .O13(PORT_A_RD_DATA[12]),
+    .O14(PORT_A_RD_DATA[13]),
+    .O15(PORT_A_RD_DATA[14]),
+    .O16(PORT_A_RD_DATA[15]),
+    .O17(PORT_A_RD_DATA[16]),
+    .O18(PORT_A_RD_DATA[17]),
+    .O19(PORT_B_RD_DATA[0]),
+    .O20(PORT_B_RD_DATA[1]),
+    .O21(PORT_B_RD_DATA[2]),
+    .O22(PORT_B_RD_DATA[3]),
+    .O23(PORT_B_RD_DATA[4]),
+    .O24(PORT_B_RD_DATA[5]),
+    .O25(PORT_B_RD_DATA[6]),
+    .O26(PORT_B_RD_DATA[7]),
+    .O27(PORT_B_RD_DATA[8]),
+    .O28(PORT_B_RD_DATA[9]),
+    .O29(PORT_B_RD_DATA[10]),
+    .O30(PORT_B_RD_DATA[11]),
+    .O31(PORT_B_RD_DATA[12]),
+    .O32(PORT_B_RD_DATA[13]),
+    .O33(PORT_B_RD_DATA[14]),
+    .O34(PORT_B_RD_DATA[15]),
+    .O35(PORT_B_RD_DATA[16]),
+    .O36(PORT_B_RD_DATA[17]),
+    .RA1(PORT_A_ADDR[0]),
+    .RA2(PORT_A_ADDR[1]),
+    .RA3(PORT_A_ADDR[2]),
+    .RA4(PORT_A_ADDR[3]),
+    .RA5(PORT_A_ADDR[4]),
+    .RA6(PORT_B_ADDR[0]),
+    .RA7(PORT_B_ADDR[1]),
+    .RA8(PORT_B_ADDR[2]),
+    .RA9(PORT_B_ADDR[3]),
+    .RA10(PORT_B_ADDR[4]),
+    .WA1(PORT_W_ADDR[0]),
+    .WA2(PORT_W_ADDR[1]),
+    .WA3(PORT_W_ADDR[2]),
+    .WA4(PORT_W_ADDR[3]),
+    .WA5(PORT_W_ADDR[4]),
+    .WA6(),
     .WE(PORT_W_WR_EN),
-    .WEA(1'b1),
-    .O(PORT_R_RD_DATA)
+    .WEA(1'b0)
   );
-endmodule
+endmodule
\ No newline at end of file
diff --git a/techlibs/nanoxplore/rf_rams_u.txt b/techlibs/nanoxplore/rf_rams_u.txt
index 370b62b1638..7b80e2f24b4 100644
--- a/techlibs/nanoxplore/rf_rams_u.txt
+++ b/techlibs/nanoxplore/rf_rams_u.txt
@@ -1,7 +1,29 @@
-ram distributed $__NX_XRFB_64x18_ {
-    abits 6;
-    width 18;
-    cost 10;
+# Register-File  RAMs for NanoXplore NG-ULTRA
+
+# Dual-port RAMs.
+# NX_RFB_U in mode 0 (DPREG)
+# NX_RFB_U in mode 2 (NX_XRFB_64x18)
+# NX_RFB_U in mode 3 (NX_XRFB_32x36)
+
+ram distributed $__NX_RFB_U_DPREG_ {
+	option "MODE" 0 {
+        cost 35;
+        widthscale 30;
+		abits 5;
+		widths 18 global;
+	}
+	option "MODE" 2 {
+        cost 50;
+        widthscale 30;
+		abits 6;
+		widths 18 global;
+	}
+	option "MODE" 3 {
+        cost 50;
+        widthscale 30;
+		abits 5;
+		widths 36 global;
+	}
     init no_undef;
     prune_rom;
 
@@ -12,16 +34,36 @@ ram distributed $__NX_XRFB_64x18_ {
     }
 }
 
-ram distributed $__NX_XRFB_32x36_ {
+# Single-port RAMs.
+# NX_RFB_U in mode 1 (SPREG)
+
+ram distributed $__NX_RFB_U_SPREG_ {
+	cost 30;
+    widthscale;
     abits 5;
-    width 36;
-    cost 10;
-    init no_undef;
-    prune_rom;
+    width 18;
+	init no_undef;
+	prune_rom;
+	port arsw "RW" {
+		clock anyedge;
+	}
+}
+
+# Single write dual read RAMs.
+# NX_RFB_U in mode 4 (NX_XRFB_2R_1W)
 
+ram distributed $__NX_XRFB_2R_1W_ {
+	cost 30;
+    widthscale;
+    abits 5;
+    width 18;
+	init no_undef;
+	prune_rom;
     port sw "W" {
         clock anyedge;
     }
-    port ar "R" {
+    port ar "A" {
+    }
+    port ar "B" {
     }
-}
\ No newline at end of file
+}
diff --git a/tests/arch/nanoxplore/lutram.ys b/tests/arch/nanoxplore/lutram.ys
index 9809da928d0..72f4919ea94 100644
--- a/tests/arch/nanoxplore/lutram.ys
+++ b/tests/arch/nanoxplore/lutram.ys
@@ -1,8 +1,66 @@
+# Single-port RAMs.
+# NX_RFB_U in mode 1 (SPREG)
 read_verilog ../common/lutram.v
-hierarchy -top lutram_1w1r
+hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 18
 synth_nanoxplore
 cd lutram_1w1r
-select -assert-count 1 t:NX_RFB_U
-select -assert-count 8 t:NX_DFF
+select -assert-count 1 t:NX_RFB_U r:mode=1 %i
+select -assert-count 18 t:NX_DFF
 select -assert-none t:NX_RFB_U t:NX_DFF %% t:* %D
 
+# Dual-port RAMs.
+# NX_RFB_U in mode 2 (NX_XRFB_64x18)
+design -reset
+read_verilog ../common/lutram.v
+hierarchy -top lutram_1w1r -chparam A_WIDTH 6 -chparam D_WIDTH 18
+synth_nanoxplore
+cd lutram_1w1r
+stat
+select -assert-count 1 t:NX_RFB_U r:mode=2 %i
+select -assert-count 18 t:NX_DFF
+select -assert-none t:NX_RFB_U t:NX_DFF %% t:* %D
+
+# Dual-port RAMs.
+# NX_RFB_U in mode 3 (NX_XRFB_32x36)
+design -reset
+read_verilog ../common/lutram.v
+hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 36
+synth_nanoxplore
+cd lutram_1w1r
+select -assert-count 1 t:NX_RFB_U r:mode=3 %i
+select -assert-count 36 t:NX_DFF
+select -assert-none t:NX_RFB_U t:NX_DFF %% t:* %D
+
+# Single write dual read RAMs.
+# NX_RFB_U in mode 4 (NX_XRFB_2R_1W)
+design -reset
+
+read_verilog <<EOT
+module lutram_1w2r
+#(parameter D_WIDTH=8, A_WIDTH=5)
+(
+	input [D_WIDTH-1:0] data_a, data_b, data_c,
+	input [A_WIDTH:1] addr_a, addr_b, addr_c,
+	input we_a, clk,
+	output reg [D_WIDTH-1:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [D_WIDTH-1:0] ram[(2**A_WIDTH)-1:0];
+
+	// Port A
+	always @ (posedge clk)
+	begin
+		if (we_a)
+			ram[addr_a] <= data_a;
+		q_a <= ram[addr_a];
+		q_b <= ram[addr_b];
+	end
+endmodule
+EOT
+
+hierarchy -top lutram_1w2r -chparam A_WIDTH 5 -chparam D_WIDTH 18
+synth_nanoxplore
+cd lutram_1w2r
+select -assert-count 1 t:NX_RFB_U r:mode=4 %i
+select -assert-count 36 t:NX_DFF
+select -assert-none t:NX_RFB_U t:NX_DFF %% t:* %D

From 9d6b47466fa8d2f2b2e52dfc813b707da5a491e2 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 17 May 2024 09:28:07 +0200
Subject: [PATCH 315/499] Add RF initialization

---
 techlibs/nanoxplore/Makefile.inc    |  1 +
 techlibs/nanoxplore/rf_init.vh      | 17 +++++++++++++++++
 techlibs/nanoxplore/rf_rams_map_u.v | 16 +++++++++++-----
 3 files changed, 29 insertions(+), 5 deletions(-)
 create mode 100644 techlibs/nanoxplore/rf_init.vh

diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc
index 3370adef70c..481429c663a 100644
--- a/techlibs/nanoxplore/Makefile.inc
+++ b/techlibs/nanoxplore/Makefile.inc
@@ -21,6 +21,7 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/latches_map.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_init.vh))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_l.txt))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_m.txt))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_u.txt))
diff --git a/techlibs/nanoxplore/rf_init.vh b/techlibs/nanoxplore/rf_init.vh
new file mode 100644
index 00000000000..909a1c0cd7c
--- /dev/null
+++ b/techlibs/nanoxplore/rf_init.vh
@@ -0,0 +1,17 @@
+function [9728-1:0] rf_init_to_string;
+    input [1152-1:0] array;
+    input integer blocks;
+    input integer width;
+    reg [9728-1:0] temp; // (1152+1152/18)*8
+    integer i;
+begin
+    temp = "";
+    for (i = 0; i < blocks; i = i + 1) begin
+    if (i != 0) begin
+        temp = {temp, ","};
+    end
+    temp = {temp, $sformatf("%b",array[(i+1)*width-1: i*width])};
+    end
+    rf_init_to_string = temp;
+end
+endfunction
diff --git a/techlibs/nanoxplore/rf_rams_map_u.v b/techlibs/nanoxplore/rf_rams_map_u.v
index b55d3e594bb..2f572650b07 100644
--- a/techlibs/nanoxplore/rf_rams_map_u.v
+++ b/techlibs/nanoxplore/rf_rams_map_u.v
@@ -12,13 +12,17 @@ module $__NX_RFB_U_DPREG_ (
   parameter OPTION_MODE = 0;
   parameter WIDTH = 18;
   parameter BITS_USED = 0;
+  localparam BLOCK_NUM  = OPTION_MODE == 2 ? 64 : 32;
+  localparam BLOCK_SIZE = OPTION_MODE == 3 ? 36 : 18;
+
+`include "rf_init.vh"
 
   // mode 0 - DPREG
   // mode 2 - NX_XRFB_64x18
   // mode 3 - NX_XRFB_32x36
   NX_RFB_U #(
     .mode(OPTION_MODE),
-    .mem_ctxt(INIT),
+    .mem_ctxt($sformatf("%s",rf_init_to_string(INIT, BLOCK_NUM, BLOCK_SIZE))),
     .wck_edge(PORT_W_CLK_POL == 1 ? 1'b0 : 1'b1)
   ) _TECHMAP_REPLACE_ (
     .WCK(PORT_W_CLK),
@@ -122,13 +126,14 @@ module $__NX_RFB_U_SPREG_ (
   input PORT_RW_WR_EN,
   output [17:0] PORT_RW_RD_DATA
 );
-  parameter INIT = 1152'bx;
+  parameter INIT = 576'bx;
   parameter PORT_RW_CLK_POL = 1'b1;
   parameter BITS_USED = 0;
+`include "rf_init.vh"
 
   NX_RFB_U #(
     .mode(1),
-    .mem_ctxt(INIT),
+    .mem_ctxt($sformatf("%s",rf_init_to_string(INIT, 32, 18))),
     .wck_edge(PORT_RW_CLK_POL == 1 ? 1'b0 : 1'b1)
   ) _TECHMAP_REPLACE_ (
     .WCK(PORT_RW_CLK),
@@ -235,13 +240,14 @@ module $__NX_XRFB_2R_1W_ (
   output [17:0] PORT_A_RD_DATA,
   output [17:0] PORT_B_RD_DATA
 );
-  parameter INIT = 1152'bx;
+  parameter INIT = 576'bx;
   parameter PORT_W_CLK_POL = 1'b1;
   parameter BITS_USED = 0;
+`include "rf_init.vh"
 
   NX_RFB_U #(
     .mode(4),
-    .mem_ctxt(INIT),
+    .mem_ctxt($sformatf("%s",rf_init_to_string(INIT, 32, 18))),
     .wck_edge(PORT_W_CLK_POL == 1 ? 1'b0 : 1'b1)
   ) _TECHMAP_REPLACE_ (
     .WCK(PORT_W_CLK),

From 829dd62054047ce388d751821dc8ff14521219f0 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 17 May 2024 15:59:18 +0200
Subject: [PATCH 316/499] block ram mapping for standard modes

---
 techlibs/nanoxplore/brams.txt   | 56 +++++++++++++++-------
 techlibs/nanoxplore/brams_map.v | 84 ++++++++++++++++++++++++++-------
 techlibs/nanoxplore/cells_bb.v  |  8 ++--
 3 files changed, 109 insertions(+), 39 deletions(-)

diff --git a/techlibs/nanoxplore/brams.txt b/techlibs/nanoxplore/brams.txt
index bc3a1722e67..55edc3ef375 100644
--- a/techlibs/nanoxplore/brams.txt
+++ b/techlibs/nanoxplore/brams.txt
@@ -1,26 +1,46 @@
 ram block $__NX_RAM_ {
-	abits 13;
-	widths 1 2 4 9 per_port;
+	option "STD_MODE" "NOECC_48kx1" {
+		# only 32k used
+		abits 15;
+		widths 1 global;
+	}
+	option "STD_MODE" "NOECC_24kx2" {
+		# only 16k used
+		abits 14;
+		widths 2 global;
+	}
+	option "STD_MODE" "NOECC_16kx3" {
+		abits 14;
+		widths 3 global;
+	}
+	option "STD_MODE" "NOECC_12kx4" {
+		# only 8k used
+		abits 13;
+		widths 4 global;
+	}
+	option "STD_MODE" "NOECC_8kx6" {
+		abits 13;
+		widths 6 global;
+	}
+	option "STD_MODE" "NOECC_6kx8" {
+		# only 4k used
+		abits 12;
+		widths 8 global;
+	}
+	option "STD_MODE" "NOECC_4kx12" {
+		abits 12;
+		widths 12 global;
+	}
+	option "STD_MODE" "NOECC_2kx24" {
+		abits 11;
+		widths 24 global;
+	}
 	cost 64;
 	init no_undef;
 	port srsw "A" "B" {
 		clock anyedge;
 		clken;
-		portoption "WRITEMODE" "NORMAL" {
-			rdwr no_change;
-		}
-		portoption "WRITEMODE" "WRITETHROUGH" {
-			rdwr new;
-		}
-		portoption "WRITEMODE" "READBEFOREWRITE" {
-			rdwr old;
-		}
-		option "RESETMODE" "SYNC" {
-			rdsrst zero ungated block_wr;
-		}
-		option "RESETMODE" "ASYNC" {
-			rdarst zero;
-		}
-		rdinit zero;
+		rdwr no_change;
+		rdinit none;
 	}
 }
\ No newline at end of file
diff --git a/techlibs/nanoxplore/brams_map.v b/techlibs/nanoxplore/brams_map.v
index b025a678254..8b32982038b 100644
--- a/techlibs/nanoxplore/brams_map.v
+++ b/techlibs/nanoxplore/brams_map.v
@@ -1,43 +1,93 @@
 module $__NX_RAM_ (...);
 
 parameter INIT = 0;
-parameter OPTION_RESETMODE = "SYNC";
+parameter OPTION_STD_MODE = "";
 
-parameter PORT_A_WIDTH = 9;
+parameter WIDTH = 24;
 parameter PORT_A_CLK_POL = 1;
-parameter PORT_A_OPTION_WRITEMODE = "NORMAL";
 
 input PORT_A_CLK;
 input PORT_A_CLK_EN;
 input PORT_A_WR_EN;
-input PORT_A_RD_SRST;
-input PORT_A_RD_ARST;
-input [12:0] PORT_A_ADDR;
-input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
-output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
+input [15:0] PORT_A_ADDR;
+input [WIDTH-1:0] PORT_A_WR_DATA;
+wire [24-1:0] A_DATA;
+output [WIDTH-1:0] PORT_A_RD_DATA;
 
-parameter PORT_B_WIDTH = 9;
 parameter PORT_B_CLK_POL = 1;
-parameter PORT_B_OPTION_WRITEMODE = "NORMAL";
 
 input PORT_B_CLK;
 input PORT_B_CLK_EN;
 input PORT_B_WR_EN;
-input PORT_B_RD_SRST;
-input PORT_B_RD_ARST;
-input [12:0] PORT_B_ADDR;
-input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
-output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
+input [15:0] PORT_B_ADDR;
+input [WIDTH-1:0] PORT_B_WR_DATA;
+wire [24-1:0] B_DATA;
+output [WIDTH-1:0] PORT_B_RD_DATA;
+
+generate
+    if (OPTION_STD_MODE == "NOECC_48kx1") begin
+        assign A_DATA = {24{PORT_A_WR_DATA[WIDTH-1:0]}};
+        assign B_DATA = {24{PORT_B_WR_DATA[WIDTH-1:0]}};
+    end
+    else if (OPTION_STD_MODE == "NOECC_24kx2") begin
+        assign A_DATA = {12{PORT_A_WR_DATA[WIDTH-1:0]}};
+        assign B_DATA = {12{PORT_B_WR_DATA[WIDTH-1:0]}};
+    end
+    else if (OPTION_STD_MODE == "NOECC_16kx3") begin
+        assign A_DATA = {8{PORT_A_WR_DATA[WIDTH-1:0]}};
+        assign B_DATA = {8{PORT_B_WR_DATA[WIDTH-1:0]}};
+    end
+    else if (OPTION_STD_MODE == "NOECC_12kx4") begin
+        assign A_DATA = {6{PORT_A_WR_DATA[WIDTH-1:0]}};
+        assign B_DATA = {6{PORT_B_WR_DATA[WIDTH-1:0]}};
+    end
+    else if (OPTION_STD_MODE == "NOECC_8kx6") begin
+        assign A_DATA = {4{PORT_A_WR_DATA[WIDTH-1:0]}};
+        assign B_DATA = {4{PORT_B_WR_DATA[WIDTH-1:0]}};
+    end
+    else if (OPTION_STD_MODE == "NOECC_6kx8") begin
+        assign A_DATA = {3{PORT_A_WR_DATA[WIDTH-1:0]}};
+        assign B_DATA = {3{PORT_B_WR_DATA[WIDTH-1:0]}};
+    end
+    else if (OPTION_STD_MODE == "NOECC_4kx12") begin
+        assign A_DATA = {2{PORT_A_WR_DATA[WIDTH-1:0]}};
+        assign B_DATA = {2{PORT_B_WR_DATA[WIDTH-1:0]}};
+    end
+    else if (OPTION_STD_MODE == "NOECC_2kx24") begin
+        assign A_DATA = PORT_A_WR_DATA;
+        assign B_DATA = PORT_B_WR_DATA;
+    end
+endgenerate
 
 NX_RAM_WRAP #(
+    .std_mode(OPTION_STD_MODE),
+    .mcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1),
+    .mckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),
 ) _TECHMAP_REPLACE_ (
     .ACK(PORT_A_CLK),
+    //.ACKS(PORT_A_CLK),
+    //.ACKD(), // Not used in Non-ECC modes
+    //.ACKR(),
+    //.AR(),
+    //.ACOR(),
+    //.AERR(),
+    .ACS(PORT_A_CLK_EN),
+    .AWE(PORT_A_WR_EN),
+
     .AA(PORT_A_ADDR),
-    .AI(PORT_A_WR_DATA),
+    .AI(A_DATA),
     .AO(PORT_A_RD_DATA),
 
     .BCK(PORT_B_CLK),
-    .BA(PORT_B_ADDR),
+    //.BCKC(PORT_B_CLK),
+    //.BCKD(), // Not used in Non-ECC modes
+    //.BCKR()
+    //.BR(),
+    //.BCOR(),
+    //.BERR(),
+    .BCS(PORT_B_CLK_EN),
+    .BWE(PORT_B_WR_EN),
+    .BA(B_DATA),
     .BI(PORT_B_WR_DATA),
     .BO(PORT_B_RD_DATA)
 );
diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index 2f6ae1ec25f..634e29b19e7 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -255,10 +255,10 @@ module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4,
     parameter pipe_ob = 1'b0;
     parameter raw_config0 = 4'b0000;
     parameter raw_config1 = 16'b0000000000000000;
-    parameter raw_l_enable = 1'b0;
-    parameter raw_l_extend = 4'b0000;
-    parameter raw_u_enable = 1'b0;
-    parameter raw_u_extend = 8'b00000000;
+    //parameter raw_l_enable = 1'b0;
+    //parameter raw_l_extend = 4'b0000;
+    //parameter raw_u_enable = 1'b0;
+    //parameter raw_u_extend = 8'b00000000;
     parameter std_mode = "";
 endmodule
 

From 8eb099c1f4e3eb273abc6426c37b52cecdc5b482 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 20 May 2024 13:19:02 +0200
Subject: [PATCH 317/499] remove debug attribute

---
 techlibs/nanoxplore/nx_carry.cc | 1 -
 1 file changed, 1 deletion(-)

diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc
index 08701b44ebd..aec2d1a3c97 100644
--- a/techlibs/nanoxplore/nx_carry.cc
+++ b/techlibs/nanoxplore/nx_carry.cc
@@ -104,7 +104,6 @@ static void nx_carry_chain(Module *module)
 				}
 			}
 			if (j==3) {
-				cell->set_string_attribute(ID(cnt), std::to_string(cnt));
 				if (cnt % 24 == 23) {
 					SigBit new_co = module->addWire(NEW_ID);
 					cell->setPort(ID(A4), State::S0);

From f4d8ea4c403a482e367a3a130a43d9cc92c637a8 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 20 May 2024 18:26:04 +0200
Subject: [PATCH 318/499] Start adding RFB simulation models

---
 techlibs/nanoxplore/cells_bb_u.v  | 103 --------------------
 techlibs/nanoxplore/cells_sim_u.v | 150 ++++++++++++++++++++++++++++++
 techlibs/nanoxplore/rf_rams_u.txt |   6 +-
 tests/arch/nanoxplore/fsm.ys      |   2 +-
 tests/arch/nanoxplore/lutram.ys   |  93 ++++++++++++++++--
 5 files changed, 240 insertions(+), 114 deletions(-)

diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v
index 2cc16f410e2..95cb7158ff0 100644
--- a/techlibs/nanoxplore/cells_bb_u.v
+++ b/techlibs/nanoxplore/cells_bb_u.v
@@ -2338,109 +2338,6 @@ module NX_PMA_U(CLK_TX_I, CLK_RX_I, CLK_REF_I, DC_E_I, DC_LCSN_I1, DC_LCSN_I2, D
     parameter tx_usrclk_use_pcs_clk_2 = 1'b0;
 endmodule
 
-(* blackbox *)
-module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20
-, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2, O3, O4, O5
-, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23, O24, O25, O26
-, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, WA1
-, WA2, WA3, WA4, WA5, WA6, WE, WEA);
-    input I1;
-    input I10;
-    input I11;
-    input I12;
-    input I13;
-    input I14;
-    input I15;
-    input I16;
-    input I17;
-    input I18;
-    input I19;
-    input I2;
-    input I20;
-    input I21;
-    input I22;
-    input I23;
-    input I24;
-    input I25;
-    input I26;
-    input I27;
-    input I28;
-    input I29;
-    input I3;
-    input I30;
-    input I31;
-    input I32;
-    input I33;
-    input I34;
-    input I35;
-    input I36;
-    input I4;
-    input I5;
-    input I6;
-    input I7;
-    input I8;
-    input I9;
-    output O1;
-    output O10;
-    output O11;
-    output O12;
-    output O13;
-    output O14;
-    output O15;
-    output O16;
-    output O17;
-    output O18;
-    output O19;
-    output O2;
-    output O20;
-    output O21;
-    output O22;
-    output O23;
-    output O24;
-    output O25;
-    output O26;
-    output O27;
-    output O28;
-    output O29;
-    output O3;
-    output O30;
-    output O31;
-    output O32;
-    output O33;
-    output O34;
-    output O35;
-    output O36;
-    output O4;
-    output O5;
-    output O6;
-    output O7;
-    output O8;
-    output O9;
-    input RA1;
-    input RA10;
-    input RA2;
-    input RA3;
-    input RA4;
-    input RA5;
-    input RA6;
-    input RA7;
-    input RA8;
-    input RA9;
-    input WA1;
-    input WA2;
-    input WA3;
-    input WA4;
-    input WA5;
-    input WA6;
-    input WCK;
-    input WE;
-    input WEA;
-    parameter mem_ctxt = "";
-    parameter mode = 0;
-    parameter wck_edge = 1'b0;
-endmodule
-
-
 (* blackbox *)
 module NX_FIFO_U(RCK, WCK, WE, WEA, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17
 , I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2
diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v
index 794dd4e6a60..e7e8fcc9aa7 100644
--- a/techlibs/nanoxplore/cells_sim_u.v
+++ b/techlibs/nanoxplore/cells_sim_u.v
@@ -1,3 +1,4 @@
+(* abc9_box, lib_whitebox *)
 module NX_GCK_U(SI1, SI2, CMD, SO);
     input CMD;
     input SI1;
@@ -28,3 +29,152 @@ module NX_GCK_U(SI1, SI2, CMD, SO);
     endgenerate
     assign SO = inv_out ? ~SO_int : SO_int;
 endmodule
+
+(* abc9_box, lib_whitebox *)
+module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20
+, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2, O3, O4, O5
+, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23, O24, O25, O26
+, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, WA1
+, WA2, WA3, WA4, WA5, WA6, WE, WEA);
+    input I1;
+    input I10;
+    input I11;
+    input I12;
+    input I13;
+    input I14;
+    input I15;
+    input I16;
+    input I17;
+    input I18;
+    input I19;
+    input I2;
+    input I20;
+    input I21;
+    input I22;
+    input I23;
+    input I24;
+    input I25;
+    input I26;
+    input I27;
+    input I28;
+    input I29;
+    input I3;
+    input I30;
+    input I31;
+    input I32;
+    input I33;
+    input I34;
+    input I35;
+    input I36;
+    input I4;
+    input I5;
+    input I6;
+    input I7;
+    input I8;
+    input I9;
+    output O1;
+    output O10;
+    output O11;
+    output O12;
+    output O13;
+    output O14;
+    output O15;
+    output O16;
+    output O17;
+    output O18;
+    output O19;
+    output O2;
+    output O20;
+    output O21;
+    output O22;
+    output O23;
+    output O24;
+    output O25;
+    output O26;
+    output O27;
+    output O28;
+    output O29;
+    output O3;
+    output O30;
+    output O31;
+    output O32;
+    output O33;
+    output O34;
+    output O35;
+    output O36;
+    output O4;
+    output O5;
+    output O6;
+    output O7;
+    output O8;
+    output O9;
+    input RA1;
+    input RA10;
+    input RA2;
+    input RA3;
+    input RA4;
+    input RA5;
+    input RA6;
+    input RA7;
+    input RA8;
+    input RA9;
+    input WA1;
+    input WA2;
+    input WA3;
+    input WA4;
+    input WA5;
+    input WA6;
+    input WCK;
+    input WE;
+    input WEA;
+    parameter mem_ctxt = "";
+    parameter mode = 0;
+    parameter wck_edge = 1'b0;
+
+    wire clock = WCK ^ wck_edge;
+
+    localparam MEM_SIZE  = mode == 2 ? 64 : 32;
+    localparam MEM_WIDTH = mode == 3 ? 36 : 18;
+    localparam ADDR_WIDTH = mode == 2 ? 6 : 5;
+
+    reg [MEM_WIDTH-1:0] mem [MEM_SIZE-1:0];
+
+    integer i;
+    initial begin
+        for (i = 0; i < MEM_SIZE; i = i + 1)
+            mem[i] = MEM_SIZE'b0;
+    end
+
+    wire [ADDR_WIDTH-1:0] WA = (mode==2) ? { WA6, WA5, WA4, WA3, WA2, WA1 } : { WA5, WA4, WA3, WA2, WA1 };
+    wire [36-1:0] O = { O36, O35, O34, O33, O32, O31, O30, O29, O28, 
+                        O27, O26, O25, O24, O23, O22, O21, O20, O19, 
+                        O18, O17, O16, O15, O14, O13, O12, O11, O10,
+                         O9,  O8,  O7,  O6,  O5,  O4,  O3,  O2,  O1 };
+    wire [36-1:0] I = { I36, I35, I34, I33, I32, I31, I30, I29, I28,
+                        I27, I26, I25, I24, I23, I22, I21, I20, I19,
+                        I18, I17, I16, I15, I14, I13, I12, I11, I10,
+                         I9,  I8,  I7,  I6,  I5,  I4,  I3,  I2,  I1 };
+    generate 
+        if (mode==0) begin
+            assign O[17:0] = mem[{ RA5, RA4, RA3, RA2, RA1 }];
+        end
+        else if (mode==1) begin
+            assign O[17:0] = mem[{ WA5, WA4, WA3, WA2, WA1 }];
+        end
+        else if (mode==2) begin
+            assign O[17:0] = mem[{ RA6, RA5, RA4, RA3, RA2, RA1 }];
+        end
+        else if (mode==3) begin
+            assign O[35:0] = mem[{ RA5, RA4, RA3, RA2, RA1 }];
+        end
+        else if (mode==4) begin
+            assign O[35:0] = { mem[{ RA10, RA9, RA8, RA7, RA6 }], mem[{ RA5, RA4, RA3, RA2, RA1 }] };
+        end
+        else 
+            $error("Unknown NX_RFB_U mode");
+    endgenerate
+
+    always @(posedge clock)
+        if (WE)
+            mem[WA] <= I[MEM_WIDTH-1:0];
+endmodule
\ No newline at end of file
diff --git a/techlibs/nanoxplore/rf_rams_u.txt b/techlibs/nanoxplore/rf_rams_u.txt
index 7b80e2f24b4..3dd3d3614ea 100644
--- a/techlibs/nanoxplore/rf_rams_u.txt
+++ b/techlibs/nanoxplore/rf_rams_u.txt
@@ -7,7 +7,7 @@
 
 ram distributed $__NX_RFB_U_DPREG_ {
 	option "MODE" 0 {
-        cost 35;
+        cost 30;
         widthscale 30;
 		abits 5;
 		widths 18 global;
@@ -53,8 +53,8 @@ ram distributed $__NX_RFB_U_SPREG_ {
 # NX_RFB_U in mode 4 (NX_XRFB_2R_1W)
 
 ram distributed $__NX_XRFB_2R_1W_ {
-	cost 30;
-    widthscale;
+	cost 40;
+    widthscale 30;
     abits 5;
     width 18;
 	init no_undef;
diff --git a/tests/arch/nanoxplore/fsm.ys b/tests/arch/nanoxplore/fsm.ys
index 8582d111c23..f5d44453d6d 100644
--- a/tests/arch/nanoxplore/fsm.ys
+++ b/tests/arch/nanoxplore/fsm.ys
@@ -12,5 +12,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd fsm # Constrain all select calls below inside the top module
 
 select -assert-count 6 t:NX_DFF
-select -assert-count 14 t:NX_LUT
+select -assert-min 13 t:NX_LUT
 select -assert-none t:NX_DFF t:NX_LUT %% t:* %D
diff --git a/tests/arch/nanoxplore/lutram.ys b/tests/arch/nanoxplore/lutram.ys
index 72f4919ea94..547e03b30b7 100644
--- a/tests/arch/nanoxplore/lutram.ys
+++ b/tests/arch/nanoxplore/lutram.ys
@@ -1,8 +1,61 @@
+# Dual-port RAMs.
+# NX_RFB_U in mode 0 (DPREG)
+
+read_verilog <<EOT
+module lutram_dpreg
+#(parameter D_WIDTH=18, A_WIDTH=5)
+(
+	input [D_WIDTH-1:0] data,
+	input [A_WIDTH:1] addr_w, addr_r,
+	input we, clk,
+	output reg [D_WIDTH-1:0] q
+);
+	// Declare the RAM variable
+	reg [D_WIDTH-1:0] ram[(2**A_WIDTH)-1:0];
+
+	// Port A
+	always @ (posedge clk)
+	begin
+		if (we)
+			ram[addr_w] <= data;
+		q <= ram[addr_r];
+	end
+endmodule
+EOT
+
+hierarchy -top lutram_dpreg
+proc
+memory -nomap
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd lutram_dpreg
+stat
+select -assert-count 1 t:NX_RFB_U r:mode=0 %i
+select -assert-count 18 t:NX_DFF
+select -assert-none t:NX_RFB_U t:NX_DFF %% t:* %D
+
 # Single-port RAMs.
 # NX_RFB_U in mode 1 (SPREG)
+design -reset
+
 read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 18
-synth_nanoxplore
+proc
+memory -nomap
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
 cd lutram_1w1r
 select -assert-count 1 t:NX_RFB_U r:mode=1 %i
 select -assert-count 18 t:NX_DFF
@@ -13,9 +66,17 @@ select -assert-none t:NX_RFB_U t:NX_DFF %% t:* %D
 design -reset
 read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r -chparam A_WIDTH 6 -chparam D_WIDTH 18
-synth_nanoxplore
+proc
+memory -nomap
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
 cd lutram_1w1r
-stat
 select -assert-count 1 t:NX_RFB_U r:mode=2 %i
 select -assert-count 18 t:NX_DFF
 select -assert-none t:NX_RFB_U t:NX_DFF %% t:* %D
@@ -25,7 +86,16 @@ select -assert-none t:NX_RFB_U t:NX_DFF %% t:* %D
 design -reset
 read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 36
-synth_nanoxplore
+proc
+memory -nomap
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
 cd lutram_1w1r
 select -assert-count 1 t:NX_RFB_U r:mode=3 %i
 select -assert-count 36 t:NX_DFF
@@ -39,8 +109,8 @@ read_verilog <<EOT
 module lutram_1w2r
 #(parameter D_WIDTH=8, A_WIDTH=5)
 (
-	input [D_WIDTH-1:0] data_a, data_b, data_c,
-	input [A_WIDTH:1] addr_a, addr_b, addr_c,
+	input [D_WIDTH-1:0] data_a, data_b,
+	input [A_WIDTH:1] addr_a, addr_b,
 	input we_a, clk,
 	output reg [D_WIDTH-1:0] q_a, q_b
 );
@@ -59,7 +129,16 @@ endmodule
 EOT
 
 hierarchy -top lutram_1w2r -chparam A_WIDTH 5 -chparam D_WIDTH 18
-synth_nanoxplore
+proc
+memory -nomap
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
 cd lutram_1w2r
 select -assert-count 1 t:NX_RFB_U r:mode=4 %i
 select -assert-count 36 t:NX_DFF

From 41a86fdb2ce311758c03a636afd851e0e335dacb Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 21 May 2024 14:07:20 +0200
Subject: [PATCH 319/499] fix

---
 techlibs/nanoxplore/cells_sim_u.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v
index e7e8fcc9aa7..094adcaf8b4 100644
--- a/techlibs/nanoxplore/cells_sim_u.v
+++ b/techlibs/nanoxplore/cells_sim_u.v
@@ -142,7 +142,7 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14
     integer i;
     initial begin
         for (i = 0; i < MEM_SIZE; i = i + 1)
-            mem[i] = MEM_SIZE'b0;
+            mem[i] = MEM_WIDTH'b0;
     end
 
     wire [ADDR_WIDTH-1:0] WA = (mode==2) ? { WA6, WA5, WA4, WA3, WA2, WA1 } : { WA5, WA4, WA3, WA2, WA1 };

From 4aaab8f3953e44b51b84ca0895b68745be26344b Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 22 May 2024 15:45:18 +0200
Subject: [PATCH 320/499] start adding wfg model

---
 techlibs/nanoxplore/cells_bb_u.v  | 21 -------------
 techlibs/nanoxplore/cells_sim_u.v | 51 +++++++++++++++++++++++++++++--
 2 files changed, 49 insertions(+), 23 deletions(-)

diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v
index 95cb7158ff0..56559fd237f 100644
--- a/techlibs/nanoxplore/cells_bb_u.v
+++ b/techlibs/nanoxplore/cells_bb_u.v
@@ -539,27 +539,6 @@ module NX_PLL_U(R, REF, FBK, OSC, VCO, LDFO, REFO, CLK_DIV1, CLK_DIV2, CLK_DIV3,
     parameter use_pll = 1'b1;
 endmodule
 
-(* blackbox *)
-module NX_WFG_U(R, SI, ZI, SO, ZO);
-    input R;
-    input SI;
-    output SO;
-    input ZI;
-    output ZO;
-    parameter delay = 0;
-    parameter delay_on = 1'b0;
-    parameter div_phase = 1'b0;
-    parameter div_ratio = 0;
-    parameter location = "";
-    parameter mode = 0;
-    parameter pattern = 16'b0000000000000000;
-    parameter pattern_end = 0;
-    parameter reset_on_cal_lock_n = 1'b0;
-    parameter reset_on_pll_lock_n = 1'b0;
-    parameter reset_on_pll_locka_n = 1'b0;
-    parameter wfg_edge = 1'b0;
-endmodule
-
 (* blackbox *)
 module NX_XCDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, CSRSTI, CDRSTI, CSRSTO, CDRSTO, DSRSTI, DDRSTI, DSRSTO, DDRSTO, BI, CI, CO
 , AO, BO, AI, DI, DO);
diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v
index 094adcaf8b4..209da3b5f80 100644
--- a/techlibs/nanoxplore/cells_sim_u.v
+++ b/techlibs/nanoxplore/cells_sim_u.v
@@ -142,7 +142,7 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14
     integer i;
     initial begin
         for (i = 0; i < MEM_SIZE; i = i + 1)
-            mem[i] = MEM_WIDTH'b0;
+            mem[i] = 36'b0;
     end
 
     wire [ADDR_WIDTH-1:0] WA = (mode==2) ? { WA6, WA5, WA4, WA3, WA2, WA1 } : { WA5, WA4, WA3, WA2, WA1 };
@@ -177,4 +177,51 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14
     always @(posedge clock)
         if (WE)
             mem[WA] <= I[MEM_WIDTH-1:0];
-endmodule
\ No newline at end of file
+endmodule
+
+(* abc9_box, lib_whitebox *)
+module NX_WFG_U(R, SI, ZI, SO, ZO);
+    input R;
+    input SI;
+    output SO;
+    input ZI;
+    output ZO;
+    parameter delay = 0;
+    parameter delay_on = 1'b0;
+    parameter div_phase = 1'b0;
+    parameter div_ratio = 0;
+    parameter location = "";
+    parameter mode = 0;
+    parameter pattern = 16'b0000000000000000;
+    parameter pattern_end = 0;
+    parameter reset_on_cal_lock_n = 1'b0;
+    parameter reset_on_pll_lock_n = 1'b0;
+    parameter reset_on_pll_locka_n = 1'b0;
+    parameter wfg_edge = 1'b0;
+
+    generate
+        if (mode==0) begin
+            assign SO = SI;
+        end
+        else if (mode==1) begin
+            wire clock = ZI ^ wfg_edge;
+            wire reset = R || SI;
+            reg [3:0] counter = 0;
+            reg [15:0] rom = pattern;
+
+            always @(posedge clock)
+            begin
+                if (reset)
+                    counter <= 4'b0;
+                else
+                    counter <= counter + 1;
+            end
+            assign SO = counter == pattern_end;
+            assign ZO = rom[counter];
+        end
+        else if (mode==2) begin
+        end
+        else
+            $error("Unknown NX_WFG_U mode");
+    endgenerate
+endmodule

From 57665556424b50ba73031171a1ef8bb6c151aa1d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 28 May 2024 14:21:36 +0200
Subject: [PATCH 321/499] Support brams with initialization

---
 techlibs/nanoxplore/Makefile.inc  |   1 +
 techlibs/nanoxplore/brams.txt     |  16 +--
 techlibs/nanoxplore/brams_init.vh |  23 ++++
 techlibs/nanoxplore/brams_map.v   |  74 +++++------
 techlibs/nanoxplore/cells_bb.v    | 172 -------------------------
 techlibs/nanoxplore/cells_sim.v   | 203 ++++++++++++++++++++++++++++++
 6 files changed, 267 insertions(+), 222 deletions(-)
 create mode 100644 techlibs/nanoxplore/brams_init.vh

diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc
index 481429c663a..807cf36a4b2 100644
--- a/techlibs/nanoxplore/Makefile.inc
+++ b/techlibs/nanoxplore/Makefile.inc
@@ -4,6 +4,7 @@ OBJS += techlibs/nanoxplore/nx_carry.o
 
 # Techmap
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_init.vh))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_map.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams.txt))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v))
diff --git a/techlibs/nanoxplore/brams.txt b/techlibs/nanoxplore/brams.txt
index 55edc3ef375..6098ee72ec6 100644
--- a/techlibs/nanoxplore/brams.txt
+++ b/techlibs/nanoxplore/brams.txt
@@ -2,38 +2,38 @@ ram block $__NX_RAM_ {
 	option "STD_MODE" "NOECC_48kx1" {
 		# only 32k used
 		abits 15;
-		widths 1 global;
+		widths 1 per_port;
 	}
 	option "STD_MODE" "NOECC_24kx2" {
 		# only 16k used
 		abits 14;
-		widths 2 global;
+		widths 2 per_port;
 	}
 	option "STD_MODE" "NOECC_16kx3" {
 		abits 14;
-		widths 3 global;
+		widths 3 per_port;
 	}
 	option "STD_MODE" "NOECC_12kx4" {
 		# only 8k used
 		abits 13;
-		widths 4 global;
+		widths 4 per_port;
 	}
 	option "STD_MODE" "NOECC_8kx6" {
 		abits 13;
-		widths 6 global;
+		widths 6 per_port;
 	}
 	option "STD_MODE" "NOECC_6kx8" {
 		# only 4k used
 		abits 12;
-		widths 8 global;
+		widths 8 per_port;
 	}
 	option "STD_MODE" "NOECC_4kx12" {
 		abits 12;
-		widths 12 global;
+		widths 12 per_port;
 	}
 	option "STD_MODE" "NOECC_2kx24" {
 		abits 11;
-		widths 24 global;
+		widths 24 per_port;
 	}
 	cost 64;
 	init no_undef;
diff --git a/techlibs/nanoxplore/brams_init.vh b/techlibs/nanoxplore/brams_init.vh
new file mode 100644
index 00000000000..b93839c5a31
--- /dev/null
+++ b/techlibs/nanoxplore/brams_init.vh
@@ -0,0 +1,23 @@
+function [409600-1:0] bram_init_to_string;
+    input [49152-1:0] array;
+    input integer blocks;
+    input integer width;
+    reg [409600-1:0] temp; // (49152+2048)*8 48K bit data + 2k commas
+    reg [24-1:0] temp2; 
+    integer i;
+    integer j;
+begin
+    temp = "";
+    for (i = 0; i < 2048; i = i + 1) begin
+        if (i != 0) begin
+            temp = {temp, ","};
+        end
+        temp2 = 24'b0;
+        for (j = 0; j < blocks; j = j + 1) begin
+            temp2[j*width +: width] = array[{j, i[10:0]}*width +: width];
+        end
+        temp = {temp, $sformatf("%b",temp2[23:0])};
+    end
+    bram_init_to_string = temp;
+end
+endfunction
diff --git a/techlibs/nanoxplore/brams_map.v b/techlibs/nanoxplore/brams_map.v
index 8b32982038b..a721d6775ac 100644
--- a/techlibs/nanoxplore/brams_map.v
+++ b/techlibs/nanoxplore/brams_map.v
@@ -1,18 +1,20 @@
 module $__NX_RAM_ (...);
 
 parameter INIT = 0;
-parameter OPTION_STD_MODE = "";
+parameter OPTION_STD_MODE = "NOECC_24kx2";
+
+parameter PORT_A_WIDTH = 24;
+parameter PORT_B_WIDTH = 24;
 
-parameter WIDTH = 24;
 parameter PORT_A_CLK_POL = 1;
 
 input PORT_A_CLK;
 input PORT_A_CLK_EN;
 input PORT_A_WR_EN;
 input [15:0] PORT_A_ADDR;
-input [WIDTH-1:0] PORT_A_WR_DATA;
+input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
 wire [24-1:0] A_DATA;
-output [WIDTH-1:0] PORT_A_RD_DATA;
+output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
 
 parameter PORT_B_CLK_POL = 1;
 
@@ -20,49 +22,37 @@ input PORT_B_CLK;
 input PORT_B_CLK_EN;
 input PORT_B_WR_EN;
 input [15:0] PORT_B_ADDR;
-input [WIDTH-1:0] PORT_B_WR_DATA;
+input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
 wire [24-1:0] B_DATA;
-output [WIDTH-1:0] PORT_B_RD_DATA;
+output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
+
+`include "brams_init.vh"
+
+localparam raw_config1_val = OPTION_STD_MODE == "NOECC_48kx1" ? 16'b0000000000000000:
+                             OPTION_STD_MODE == "NOECC_24kx2" ? 16'b0000001001001001:
+                             OPTION_STD_MODE == "NOECC_16kx3" ? 16'b0000110110110110:
+                             OPTION_STD_MODE == "NOECC_12kx4" ? 16'b0000010010010010:
+                             OPTION_STD_MODE == "NOECC_8kx6"  ? 16'b0000111111111111:
+                             OPTION_STD_MODE == "NOECC_6kx8"  ? 16'b0000011011011011:
+                             OPTION_STD_MODE == "NOECC_4kx12" ? 16'b0000100100100100:
+                             OPTION_STD_MODE == "NOECC_2kx24" ? 16'b0000101101101101:
+                             'bx;
+
+localparam A_REPEAT  =  24 / PORT_A_WIDTH;
+localparam B_REPEAT  =  24 / PORT_B_WIDTH;
 
-generate
-    if (OPTION_STD_MODE == "NOECC_48kx1") begin
-        assign A_DATA = {24{PORT_A_WR_DATA[WIDTH-1:0]}};
-        assign B_DATA = {24{PORT_B_WR_DATA[WIDTH-1:0]}};
-    end
-    else if (OPTION_STD_MODE == "NOECC_24kx2") begin
-        assign A_DATA = {12{PORT_A_WR_DATA[WIDTH-1:0]}};
-        assign B_DATA = {12{PORT_B_WR_DATA[WIDTH-1:0]}};
-    end
-    else if (OPTION_STD_MODE == "NOECC_16kx3") begin
-        assign A_DATA = {8{PORT_A_WR_DATA[WIDTH-1:0]}};
-        assign B_DATA = {8{PORT_B_WR_DATA[WIDTH-1:0]}};
-    end
-    else if (OPTION_STD_MODE == "NOECC_12kx4") begin
-        assign A_DATA = {6{PORT_A_WR_DATA[WIDTH-1:0]}};
-        assign B_DATA = {6{PORT_B_WR_DATA[WIDTH-1:0]}};
-    end
-    else if (OPTION_STD_MODE == "NOECC_8kx6") begin
-        assign A_DATA = {4{PORT_A_WR_DATA[WIDTH-1:0]}};
-        assign B_DATA = {4{PORT_B_WR_DATA[WIDTH-1:0]}};
-    end
-    else if (OPTION_STD_MODE == "NOECC_6kx8") begin
-        assign A_DATA = {3{PORT_A_WR_DATA[WIDTH-1:0]}};
-        assign B_DATA = {3{PORT_B_WR_DATA[WIDTH-1:0]}};
-    end
-    else if (OPTION_STD_MODE == "NOECC_4kx12") begin
-        assign A_DATA = {2{PORT_A_WR_DATA[WIDTH-1:0]}};
-        assign B_DATA = {2{PORT_B_WR_DATA[WIDTH-1:0]}};
-    end
-    else if (OPTION_STD_MODE == "NOECC_2kx24") begin
-        assign A_DATA = PORT_A_WR_DATA;
-        assign B_DATA = PORT_B_WR_DATA;
-    end
-endgenerate
+assign A_DATA = {A_REPEAT{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}};
+assign B_DATA = {B_REPEAT{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}};
 
 NX_RAM_WRAP #(
     .std_mode(OPTION_STD_MODE),
     .mcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1),
     .mckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),
+    .pcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1),
+    .pckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),
+    .raw_config0(4'b0000),
+    .raw_config1(raw_config1_val),
+    .mem_ctxt($sformatf("%s",bram_init_to_string(INIT,A_REPEAT,PORT_A_WIDTH))),
 ) _TECHMAP_REPLACE_ (
     .ACK(PORT_A_CLK),
     //.ACKS(PORT_A_CLK),
@@ -87,8 +77,8 @@ NX_RAM_WRAP #(
     //.BERR(),
     .BCS(PORT_B_CLK_EN),
     .BWE(PORT_B_WR_EN),
-    .BA(B_DATA),
-    .BI(PORT_B_WR_DATA),
+    .BA(PORT_B_ADDR),
+    .BI(B_DATA),
     .BO(PORT_B_RD_DATA)
 );
 endmodule
\ No newline at end of file
diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index 634e29b19e7..c66bfaf08a2 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -90,178 +90,6 @@ endmodule
 //    parameter ring = 0;
 //endmodule
 
-(* blackbox *)
-module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13
-, AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10
-, BI11, BI12, BI13, BI14, BI15, BI16, BI17, BI18, BI19, BI20, BI21, BI22, BI23, BI24, ACOR, AERR, BCOR, BERR, AO1, AO2, AO3
-, AO4, AO5, AO6, AO7, AO8, AO9, AO10, AO11, AO12, AO13, AO14, AO15, AO16, AO17, AO18, AO19, AO20, AO21, AO22, AO23, AO24
-, BO1, BO2, BO3, BO4, BO5, BO6, BO7, BO8, BO9, BO10, BO11, BO12, BO13, BO14, BO15, BO16, BO17, BO18, BO19, BO20, BO21
-, BO22, BO23, BO24, AA1, AA2, AA3, AA4, AA5, AA6, AA7, AA8, AA9, AA10, AA11, AA12, AA13, AA14, AA15, AA16, ACS, AWE
-, AR, BA1, BA2, BA3, BA4, BA5, BA6, BA7, BA8, BA9, BA10, BA11, BA12, BA13, BA14, BA15, BA16, BCS, BWE, BR);
-    input AA1;
-    input AA10;
-    input AA11;
-    input AA12;
-    input AA13;
-    input AA14;
-    input AA15;
-    input AA16;
-    input AA2;
-    input AA3;
-    input AA4;
-    input AA5;
-    input AA6;
-    input AA7;
-    input AA8;
-    input AA9;
-    input ACK;
-    input ACKC;
-    input ACKD;
-    input ACKR;
-    output ACOR;
-    input ACS;
-    output AERR;
-    input AI1;
-    input AI10;
-    input AI11;
-    input AI12;
-    input AI13;
-    input AI14;
-    input AI15;
-    input AI16;
-    input AI17;
-    input AI18;
-    input AI19;
-    input AI2;
-    input AI20;
-    input AI21;
-    input AI22;
-    input AI23;
-    input AI24;
-    input AI3;
-    input AI4;
-    input AI5;
-    input AI6;
-    input AI7;
-    input AI8;
-    input AI9;
-    output AO1;
-    output AO10;
-    output AO11;
-    output AO12;
-    output AO13;
-    output AO14;
-    output AO15;
-    output AO16;
-    output AO17;
-    output AO18;
-    output AO19;
-    output AO2;
-    output AO20;
-    output AO21;
-    output AO22;
-    output AO23;
-    output AO24;
-    output AO3;
-    output AO4;
-    output AO5;
-    output AO6;
-    output AO7;
-    output AO8;
-    output AO9;
-    input AR;
-    input AWE;
-    input BA1;
-    input BA10;
-    input BA11;
-    input BA12;
-    input BA13;
-    input BA14;
-    input BA15;
-    input BA16;
-    input BA2;
-    input BA3;
-    input BA4;
-    input BA5;
-    input BA6;
-    input BA7;
-    input BA8;
-    input BA9;
-    input BCK;
-    input BCKC;
-    input BCKD;
-    input BCKR;
-    output BCOR;
-    input BCS;
-    output BERR;
-    input BI1;
-    input BI10;
-    input BI11;
-    input BI12;
-    input BI13;
-    input BI14;
-    input BI15;
-    input BI16;
-    input BI17;
-    input BI18;
-    input BI19;
-    input BI2;
-    input BI20;
-    input BI21;
-    input BI22;
-    input BI23;
-    input BI24;
-    input BI3;
-    input BI4;
-    input BI5;
-    input BI6;
-    input BI7;
-    input BI8;
-    input BI9;
-    output BO1;
-    output BO10;
-    output BO11;
-    output BO12;
-    output BO13;
-    output BO14;
-    output BO15;
-    output BO16;
-    output BO17;
-    output BO18;
-    output BO19;
-    output BO2;
-    output BO20;
-    output BO21;
-    output BO22;
-    output BO23;
-    output BO24;
-    output BO3;
-    output BO4;
-    output BO5;
-    output BO6;
-    output BO7;
-    output BO8;
-    output BO9;
-    input BR;
-    input BWE;
-    parameter mcka_edge = 1'b0;
-    parameter mckb_edge = 1'b0;
-    parameter mem_ctxt = "";
-    parameter pcka_edge = 1'b0;
-    parameter pckb_edge = 1'b0;
-    parameter pipe_ia = 1'b0;
-    parameter pipe_ib = 1'b0;
-    parameter pipe_oa = 1'b0;
-    parameter pipe_ob = 1'b0;
-    parameter raw_config0 = 4'b0000;
-    parameter raw_config1 = 16'b0000000000000000;
-    //parameter raw_l_enable = 1'b0;
-    //parameter raw_l_extend = 4'b0000;
-    //parameter raw_u_enable = 1'b0;
-    //parameter raw_u_extend = 8'b00000000;
-    parameter std_mode = "";
-endmodule
-
 // NX_RAM related
 (* blackbox *)
 module NX_ECC(CKD, CHK, COR, ERR);
diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v
index 392ee18e4e3..86606ce9cd9 100644
--- a/techlibs/nanoxplore/cells_sim.v
+++ b/techlibs/nanoxplore/cells_sim.v
@@ -185,3 +185,206 @@ module NX_BFR(I, O);
 
     assign O = data_inv ? ~I : I;
 endmodule
+
+(* abc9_box, lib_whitebox *)
+module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13
+, AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10
+, BI11, BI12, BI13, BI14, BI15, BI16, BI17, BI18, BI19, BI20, BI21, BI22, BI23, BI24, ACOR, AERR, BCOR, BERR, AO1, AO2, AO3
+, AO4, AO5, AO6, AO7, AO8, AO9, AO10, AO11, AO12, AO13, AO14, AO15, AO16, AO17, AO18, AO19, AO20, AO21, AO22, AO23, AO24
+, BO1, BO2, BO3, BO4, BO5, BO6, BO7, BO8, BO9, BO10, BO11, BO12, BO13, BO14, BO15, BO16, BO17, BO18, BO19, BO20, BO21
+, BO22, BO23, BO24, AA1, AA2, AA3, AA4, AA5, AA6, AA7, AA8, AA9, AA10, AA11, AA12, AA13, AA14, AA15, AA16, ACS, AWE
+, AR, BA1, BA2, BA3, BA4, BA5, BA6, BA7, BA8, BA9, BA10, BA11, BA12, BA13, BA14, BA15, BA16, BCS, BWE, BR);
+    input AA1;
+    input AA10;
+    input AA11;
+    input AA12;
+    input AA13;
+    input AA14;
+    input AA15;
+    input AA16;
+    input AA2;
+    input AA3;
+    input AA4;
+    input AA5;
+    input AA6;
+    input AA7;
+    input AA8;
+    input AA9;
+    input ACK;
+    input ACKC;
+    input ACKD;
+    input ACKR;
+    output ACOR;
+    input ACS;
+    output AERR;
+    input AI1;
+    input AI10;
+    input AI11;
+    input AI12;
+    input AI13;
+    input AI14;
+    input AI15;
+    input AI16;
+    input AI17;
+    input AI18;
+    input AI19;
+    input AI2;
+    input AI20;
+    input AI21;
+    input AI22;
+    input AI23;
+    input AI24;
+    input AI3;
+    input AI4;
+    input AI5;
+    input AI6;
+    input AI7;
+    input AI8;
+    input AI9;
+    output reg AO1;
+    output reg AO10;
+    output reg AO11;
+    output reg AO12;
+    output reg AO13;
+    output reg AO14;
+    output reg AO15;
+    output reg AO16;
+    output reg AO17;
+    output reg AO18;
+    output reg AO19;
+    output reg AO2;
+    output reg AO20;
+    output reg AO21;
+    output reg AO22;
+    output reg AO23;
+    output reg AO24;
+    output reg AO3;
+    output reg AO4;
+    output reg AO5;
+    output reg AO6;
+    output reg AO7;
+    output reg AO8;
+    output reg AO9;
+    input AR;
+    input AWE;
+    input BA1;
+    input BA10;
+    input BA11;
+    input BA12;
+    input BA13;
+    input BA14;
+    input BA15;
+    input BA16;
+    input BA2;
+    input BA3;
+    input BA4;
+    input BA5;
+    input BA6;
+    input BA7;
+    input BA8;
+    input BA9;
+    input BCK;
+    input BCKC;
+    input BCKD;
+    input BCKR;
+    output BCOR;
+    input BCS;
+    output BERR;
+    input BI1;
+    input BI10;
+    input BI11;
+    input BI12;
+    input BI13;
+    input BI14;
+    input BI15;
+    input BI16;
+    input BI17;
+    input BI18;
+    input BI19;
+    input BI2;
+    input BI20;
+    input BI21;
+    input BI22;
+    input BI23;
+    input BI24;
+    input BI3;
+    input BI4;
+    input BI5;
+    input BI6;
+    input BI7;
+    input BI8;
+    input BI9;
+    output reg BO1;
+    output reg BO10;
+    output reg BO11;
+    output reg BO12;
+    output reg BO13;
+    output reg BO14;
+    output reg BO15;
+    output reg BO16;
+    output reg BO17;
+    output reg BO18;
+    output reg BO19;
+    output reg BO2;
+    output reg BO20;
+    output reg BO21;
+    output reg BO22;
+    output reg BO23;
+    output reg BO24;
+    output reg BO3;
+    output reg BO4;
+    output reg BO5;
+    output reg BO6;
+    output reg BO7;
+    output reg BO8;
+    output reg BO9;
+    input BR;
+    input BWE;
+    parameter mcka_edge = 1'b0;
+    parameter mckb_edge = 1'b0;
+    parameter mem_ctxt = "";
+    parameter pcka_edge = 1'b0;
+    parameter pckb_edge = 1'b0;
+    parameter pipe_ia = 1'b0;
+    parameter pipe_ib = 1'b0;
+    parameter pipe_oa = 1'b0;
+    parameter pipe_ob = 1'b0;
+    parameter raw_config0 = 4'b0000;
+    parameter raw_config1 = 16'b0000000000000000;
+    //parameter raw_l_enable = 1'b0;
+    //parameter raw_l_extend = 4'b0000;
+    //parameter raw_u_enable = 1'b0;
+    //parameter raw_u_extend = 8'b00000000;
+    parameter std_mode = "";
+
+    reg [24-1:0] mem [2048-1:0]; // 48 Kbit of memory
+
+    /*integer i;
+    initial begin
+        for (i = 0; i < 2048; i = i + 1)
+            mem[i] = 24'b0;
+    end*/
+
+    wire [15:0] AA = { AA16, AA15, AA14, AA13, AA12, AA11, AA10, AA9, AA8, AA7, AA6, AA5, AA4, AA3, AA2, AA1 };
+    wire [23:0] AI = { AI24, AI23, AI22, AI21, AI20, AI19, AI18, AI17, AI16, AI15, AI14, AI13, AI12, AI11, AI10, AI9, AI8, AI7, AI6, AI5, AI4, AI3, AI2, AI1 };
+    wire [23:0] AO = { AO24, AO23, AO22, AO21, AO20, AO19, AO18, AO17, AO16, AO15, AO14, AO13, AO12, AO11, AO10, AO9, AO8, AO7, AO6, AO5, AO4, AO3, AO2, AO1 };
+    wire [15:0] BA = { BA16, BA15, BA14, BA13, BA12, BA11, BA10, BA9, BA8, BA7, BA6, BA5, BA4, BA3, BA2, BA1 };
+    wire [23:0] BI = { BI24, BI23, BI22, BI21, BI20, BI19, BI18, BI17, BI16, BI15, BI14, BI13, BI12, BI11, BI10, BI9, BI8, BI7, BI6, BI5, BI4, BI3, BI2, BI1 };
+    wire [23:0] BO = { BO24, BO23, BO22, BO21, BO20, BO19, BO18, BO17, BO16, BO15, BO14, BO13, BO12, BO11, BO10, BO9, BO8, BO7, BO6, BO5, BO4, BO3, BO2, BO1 };
+
+    always @(posedge ACK)
+        if (AWE)
+            mem[AA[10:0]] <= AI;
+        else
+            { AO24, AO23, AO22, AO21, AO20, AO19, AO18, AO17, AO16, AO15, AO14, AO13, AO12, AO11, AO10, AO9, AO8, AO7, AO6, AO5, AO4, AO3, AO2, AO1 } <= mem[AA[10:0]];
+    assign ACOR = 1'b0;
+    assign AERR = 1'b0;
+
+    always @(posedge BCK)
+        if (BWE)
+            mem[BA[10:0]] <= BI;
+        else
+            { BO24, BO23, BO22, BO21, BO20, BO19, BO18, BO17, BO16, BO15, BO14, BO13, BO12, BO11, BO10, BO9, BO8, BO7, BO6, BO5, BO4, BO3, BO2, BO1 } <= mem[BA[10:0]];
+    assign BCOR = 1'b0;
+    assign BERR = 1'b0;
+endmodule

From 8909a427964156ba3a915f2cd6697590efc5ec6f Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 30 May 2024 08:06:30 +0200
Subject: [PATCH 322/499] Better wire check

---
 techlibs/nanoxplore/nx_carry.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc
index aec2d1a3c97..5440950816c 100644
--- a/techlibs/nanoxplore/nx_carry.cc
+++ b/techlibs/nanoxplore/nx_carry.cc
@@ -80,7 +80,7 @@ static void nx_carry_chain(Module *module)
 		IdString names_A[] = { ID(A1), ID(A2), ID(A3), ID(A4) };
 		IdString names_B[] = { ID(B1), ID(B2), ID(B3), ID(B4) };
 		IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) };
-		if (c.second.at(0)->getPort(ID(CI)).is_wire()) {
+		if (!c.second.at(0)->getPort(ID(CI)).is_fully_const()) {
 			cell = module->addCell(NEW_ID, ID(NX_CY));
 			cell->setPort(ID(CI), State::S0);
 

From 596506b88b79511551aa9a6b44a0d0a23d29fba4 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 30 May 2024 09:06:12 +0200
Subject: [PATCH 323/499] Add NX_XCDC_U to wrappers

---
 techlibs/nanoxplore/cells_bb_u.v   |  48 ----------
 techlibs/nanoxplore/cells_wrap_u.v | 135 +++++++++++++++++++++++++++++
 2 files changed, 135 insertions(+), 48 deletions(-)

diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v
index 56559fd237f..bfe04dc25ab 100644
--- a/techlibs/nanoxplore/cells_bb_u.v
+++ b/techlibs/nanoxplore/cells_bb_u.v
@@ -539,54 +539,6 @@ module NX_PLL_U(R, REF, FBK, OSC, VCO, LDFO, REFO, CLK_DIV1, CLK_DIV2, CLK_DIV3,
     parameter use_pll = 1'b1;
 endmodule
 
-(* blackbox *)
-module NX_XCDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, CSRSTI, CDRSTI, CSRSTO, CDRSTO, DSRSTI, DDRSTI, DSRSTO, DDRSTO, BI, CI, CO
-, AO, BO, AI, DI, DO);
-    input ADRSTI;
-    output ADRSTO;
-    input [5:0] AI;
-    output [5:0] AO;
-    input ASRSTI;
-    output ASRSTO;
-    input BDRSTI;
-    output BDRSTO;
-    input [5:0] BI;
-    output [5:0] BO;
-    input BSRSTI;
-    output BSRSTO;
-    input CDRSTI;
-    output CDRSTO;
-    input [5:0] CI;
-    input CK1;
-    input CK2;
-    output [5:0] CO;
-    input CSRSTI;
-    output CSRSTO;
-    input DDRSTI;
-    output DDRSTO;
-    input [5:0] DI;
-    output [5:0] DO;
-    input DSRSTI;
-    output DSRSTO;
-    parameter ack_sel = 1'b0;
-    parameter bck_sel = 1'b0;
-    parameter cck_sel = 1'b0;
-    parameter ck0_edge = 1'b0;
-    parameter ck1_edge = 1'b0;
-    parameter dck_sel = 1'b0;
-    parameter link_BA = 1'b0;
-    parameter link_CB = 1'b0;
-    parameter link_DC = 1'b0;
-    parameter use_adest_arst = 1'b0;
-    parameter use_asrc_arst = 1'b0;
-    parameter use_bdest_arst = 1'b0;
-    parameter use_bsrc_arst = 1'b0;
-    parameter use_cdest_arst = 1'b0;
-    parameter use_csrc_arst = 1'b0;
-    parameter use_ddest_arst = 1'b0;
-    parameter use_dsrc_arst = 1'b0;
-endmodule
-
 (* blackbox *)
 module NX_CRX_U(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, RST_N_I, PMA_RSTN_I, MEYE_RST_I, PWDN_N_I, DBG_S_I1, DBG_S_I2, DBG_S_I3, DATA_O1, DATA_O2, DATA_O3, DATA_O4, DATA_O5, DATA_O6
 , DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24, DATA_O25, DATA_O26, DATA_O27
diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v
index 74adfaa5173..c9eaa5e5b8f 100644
--- a/techlibs/nanoxplore/cells_wrap_u.v
+++ b/techlibs/nanoxplore/cells_wrap_u.v
@@ -466,6 +466,141 @@ module NX_CDC_U_GRAY2BIN(BI, AO, BO, AI);
   );
 endmodule
 
+module NX_XCDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, CSRSTI, CDRSTI, CSRSTO, CDRSTO, DSRSTI, DDRSTI, DSRSTO, DDRSTO, BI, CI, CO
+, AO, BO, AI, DI, DO);
+    input ADRSTI;
+    output ADRSTO;
+    input [5:0] AI;
+    output [5:0] AO;
+    input ASRSTI;
+    output ASRSTO;
+    input BDRSTI;
+    output BDRSTO;
+    input [5:0] BI;
+    output [5:0] BO;
+    input BSRSTI;
+    output BSRSTO;
+    input CDRSTI;
+    output CDRSTO;
+    input [5:0] CI;
+    input CK1;
+    input CK2;
+    output [5:0] CO;
+    input CSRSTI;
+    output CSRSTO;
+    input DDRSTI;
+    output DDRSTO;
+    input [5:0] DI;
+    output [5:0] DO;
+    input DSRSTI;
+    output DSRSTO;
+    parameter ack_sel = 1'b0;
+    parameter bck_sel = 1'b0;
+    parameter cck_sel = 1'b0;
+    parameter ck0_edge = 1'b0;
+    parameter ck1_edge = 1'b0;
+    parameter dck_sel = 1'b0;
+    parameter link_BA = 1'b0;
+    parameter link_CB = 1'b0;
+    parameter link_DC = 1'b0;
+    parameter use_adest_arst = 1'b0;
+    parameter use_asrc_arst = 1'b0;
+    parameter use_bdest_arst = 1'b0;
+    parameter use_bsrc_arst = 1'b0;
+    parameter use_cdest_arst = 1'b0;
+    parameter use_csrc_arst = 1'b0;
+    parameter use_ddest_arst = 1'b0;
+    parameter use_dsrc_arst = 1'b0;
+
+  NX_CDC_U #(
+    .mode(5), // -- 5: XCDC
+    .ck0_edge(ck0_edge),
+    .ck1_edge(ck1_edge),
+    .ack_sel(ack_sel),
+    .bck_sel(bck_sel),
+    .cck_sel(cck_sel),
+    .dck_sel(dck_sel),
+    .use_asrc_arst(use_asrc_arst),
+    .use_adest_arst(use_adest_arst),
+    .use_bsrc_arst(use_bsrc_arst),
+    .use_bdest_arst(use_bdest_arst),
+    .use_csrc_arst(use_csrc_arst),
+    .use_cdest_arst(use_cdest_arst),
+    .use_dsrc_arst(use_dsrc_arst),
+    .use_ddest_arst(use_ddest_arst),
+    .link_BA(link_BA),
+    .link_CB(link_CB),
+    .link_DC(link_DC),
+  ) _TECHMAP_REPLACE_ (
+    .CK1(CK1),
+    .CK2(CK2),
+    .ASRSTI(ASRSTI),
+    .ADRSTI(ADRSTI),
+    .ASRSTO(ASRSTO),
+    .ADRSTO(ADRSTO),
+    .AI1(AI[0]),
+    .AI2(AI[1]),
+    .AI3(AI[2]),
+    .AI4(AI[3]),
+    .AI5(AI[4]),
+    .AI6(AI[5]),
+    .AO1(AO[0]),
+    .AO2(AO[1]),
+    .AO3(AO[2]),
+    .AO4(AO[3]),
+    .AO5(AO[4]),
+    .AO6(AO[5]),
+    .BSRSTI(BSRSTI),
+    .BDRSTI(BDRSTI),
+    .BSRSTO(BSRSTO),
+    .BDRSTO(BDRSTO),
+    .BI1(BI[0]),
+    .BI2(BI[1]),
+    .BI3(BI[2]),
+    .BI4(BI[3]),
+    .BI5(BI[4]),
+    .BI6(BI[5]),
+    .BO1(BO[0]),
+    .BO2(BO[1]),
+    .BO3(BO[2]),
+    .BO4(BO[3]),
+    .BO5(BO[4]),
+    .BO6(BO[5]),
+    .CSRSTI(CSRSTI),
+    .CDRSTI(CDRSTI),
+    .CSRSTO(CSRSTO),
+    .CDRSTO(CDRSTO),
+    .CI1(CI[0]),
+    .CI2(CI[1]),
+    .CI3(CI[2]),
+    .CI4(CI[3]),
+    .CI5(CI[4]),
+    .CI6(CI[5]),
+    .CO1(CO[0]),
+    .CO2(CO[1]),
+    .CO3(CO[2]),
+    .CO4(CO[3]),
+    .CO5(CO[4]),
+    .CO6(CO[5]),
+    .DSRSTI(DSRSTI),
+    .DDRSTI(DDRSTI),
+    .DSRSTO(DSRSTO),
+    .DDRSTO(DDRSTO),
+    .DI1(DI[0]),
+    .DI2(DI[1]),
+    .DI3(DI[2]),
+    .DI4(DI[3]),
+    .DI5(DI[4]),
+    .DI6(DI[5]),
+    .DO1(DO[0]),
+    .DO2(DO[1]),
+    .DO3(DO[2]),
+    .DO4(DO[3]),
+    .DO5(DO[4]),
+    .DO6(DO[5]),
+  );
+endmodule
+
 module NX_DSP_U_SPLIT(CK, R, RZ, WE, WEZ, CI, CCI, CO42, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO, CZO);
     input [23:0] A;
     input [17:0] B;

From 40f05009e37372d4cd17be8a03757999f487d76a Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 30 May 2024 17:29:33 +0200
Subject: [PATCH 324/499] Fix CY chaining and CI injection

---
 techlibs/nanoxplore/nx_carry.cc  |  8 ++--
 tests/arch/nanoxplore/add_sub.ys | 63 +++++++++++++++++++++++++++++++-
 2 files changed, 67 insertions(+), 4 deletions(-)

diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc
index 5440950816c..6e6a9603542 100644
--- a/techlibs/nanoxplore/nx_carry.cc
+++ b/techlibs/nanoxplore/nx_carry.cc
@@ -82,7 +82,8 @@ static void nx_carry_chain(Module *module)
 		IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) };
 		if (!c.second.at(0)->getPort(ID(CI)).is_fully_const()) {
 			cell = module->addCell(NEW_ID, ID(NX_CY));
-			cell->setPort(ID(CI), State::S0);
+			cell->setParam(ID(add_carry), Const(1,2));
+			cell->setPort(ID(CI), State::S1);
 
 			cell->setPort(names_A[0], c.second.at(0)->getPort(ID(CI)).as_bit());
 			cell->setPort(names_B[0], State::S0);
@@ -104,13 +105,14 @@ static void nx_carry_chain(Module *module)
 				}
 			}
 			if (j==3) {
-				if (cnt % 24 == 23) {
+				if (cnt !=0 && (cnt % 24 == 0)) {
 					SigBit new_co = module->addWire(NEW_ID);
 					cell->setPort(ID(A4), State::S0);
 					cell->setPort(ID(B4), State::S0);
 					cell->setPort(ID(S4), new_co);
 					cell = module->addCell(NEW_ID, ID(NX_CY));
-					cell->setPort(ID(CI), State::S0);
+					cell->setParam(ID(add_carry), Const(1,2));
+					cell->setPort(ID(CI), State::S1);
 					cell->setPort(ID(A1), new_co);
 					cell->setPort(ID(B1), State::S0);
 					j = 1;
diff --git a/tests/arch/nanoxplore/add_sub.ys b/tests/arch/nanoxplore/add_sub.ys
index 0cfc201f502..9b23cef1533 100644
--- a/tests/arch/nanoxplore/add_sub.ys
+++ b/tests/arch/nanoxplore/add_sub.ys
@@ -1,10 +1,71 @@
 read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 2 t:NX_CY
 select -assert-count 4 t:NX_LUT
 select -assert-none t:NX_CY t:NX_LUT %% t:* %D
 
+design -reset
+read_verilog <<EOT
+module top
+(
+    input [5:0] x,
+    input [5:0] y,
+
+    output [5:0] A,
+    input CI,
+    output CO
+);
+
+    assign {CO, A} =  x + y + CI;
+endmodule
+EOT
+
+hierarchy -top top
+proc
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd top
+stat
+select -assert-count 2 t:NX_CY
+select -assert-none t:NX_CY %% t:* %D
+
+design -reset
+read_verilog <<EOT
+module top
+(
+    input [189:0] x,
+    input [189:0] y,
+
+    output [189:0] A
+);
+
+    assign A =  x + y;
+endmodule
+EOT
+
+hierarchy -top top
+proc
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd top
+stat
+select -assert-count 48 t:NX_CY
+select -assert-none t:NX_CY %% t:* %D
\ No newline at end of file

From f8ae93c0ea00432c4e2914b967a73310b3aa19a3 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 6 Jun 2024 18:07:39 +0200
Subject: [PATCH 325/499] run setundef for all x inputs

---
 techlibs/nanoxplore/synth_nanoxplore.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index 054ca5b0d5a..babc9139144 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -341,6 +341,7 @@ struct SynthNanoXplorePass : public ScriptPass
 			run("stat");
 			run("check -noinit");
 			run("blackbox =A:whitebox");
+			run("setundef -zero -undriven");
 		}
 
 		if (check_label("json"))

From 4372487a6f6d1b9fae41d3bd477a59dbf3655a00 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 7 Jun 2024 10:52:44 +0200
Subject: [PATCH 326/499] raw must be 16 bits for nx tools to work

---
 techlibs/nanoxplore/brams_map.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/techlibs/nanoxplore/brams_map.v b/techlibs/nanoxplore/brams_map.v
index a721d6775ac..4609eee8409 100644
--- a/techlibs/nanoxplore/brams_map.v
+++ b/techlibs/nanoxplore/brams_map.v
@@ -36,7 +36,7 @@ localparam raw_config1_val = OPTION_STD_MODE == "NOECC_48kx1" ? 16'b000000000000
                              OPTION_STD_MODE == "NOECC_6kx8"  ? 16'b0000011011011011:
                              OPTION_STD_MODE == "NOECC_4kx12" ? 16'b0000100100100100:
                              OPTION_STD_MODE == "NOECC_2kx24" ? 16'b0000101101101101:
-                             'bx;
+                             16'bx;
 
 localparam A_REPEAT  =  24 / PORT_A_WIDTH;
 localparam B_REPEAT  =  24 / PORT_B_WIDTH;
@@ -51,7 +51,7 @@ NX_RAM_WRAP #(
     .pcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1),
     .pckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),
     .raw_config0(4'b0000),
-    .raw_config1(raw_config1_val),
+    .raw_config1(raw_config1_val[15:0]),
     .mem_ctxt($sformatf("%s",bram_init_to_string(INIT,A_REPEAT,PORT_A_WIDTH))),
 ) _TECHMAP_REPLACE_ (
     .ACK(PORT_A_CLK),

From 7601dc740be084d623fafa2df98d4c36f44f0855 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 11 Jun 2024 11:05:45 +0200
Subject: [PATCH 327/499] Some memory types are only supported on NG-LARGE

---
 techlibs/nanoxplore/brams.txt           | 16 ++++++++++------
 techlibs/nanoxplore/synth_nanoxplore.cc |  2 ++
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/techlibs/nanoxplore/brams.txt b/techlibs/nanoxplore/brams.txt
index 6098ee72ec6..046f54c2340 100644
--- a/techlibs/nanoxplore/brams.txt
+++ b/techlibs/nanoxplore/brams.txt
@@ -9,18 +9,22 @@ ram block $__NX_RAM_ {
 		abits 14;
 		widths 2 per_port;
 	}
-	option "STD_MODE" "NOECC_16kx3" {
-		abits 14;
-		widths 3 per_port;
+	ifdef IS_NG_LARGE {
+		option "STD_MODE" "NOECC_16kx3" {
+			abits 14;
+			widths 3 per_port;
+		}
 	}
 	option "STD_MODE" "NOECC_12kx4" {
 		# only 8k used
 		abits 13;
 		widths 4 per_port;
 	}
-	option "STD_MODE" "NOECC_8kx6" {
-		abits 13;
-		widths 6 per_port;
+	ifdef IS_NG_LARGE {
+		option "STD_MODE" "NOECC_8kx6" {
+			abits 13;
+			widths 6 per_port;
+		}
 	}
 	option "STD_MODE" "NOECC_6kx8" {
 		# only 4k used
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index babc9139144..2d80a418910 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -264,6 +264,8 @@ struct SynthNanoXplorePass : public ScriptPass
 		if (check_label("map_ram"))
 		{
 			std::string args = "";
+			if (family == "large")
+				args += " -D IS_NG_LARGE";
 			if (nobram)
 				args += " -no-auto-block";
 			if (norfram)

From eb30be6189662165513730d29e5dd55381fe676c Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 24 Jun 2024 11:06:41 +0200
Subject: [PATCH 328/499] Impulse does not support these types but NG-ULTRA
 architecture does

---
 techlibs/nanoxplore/brams.txt           | 4 ++--
 techlibs/nanoxplore/synth_nanoxplore.cc | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/techlibs/nanoxplore/brams.txt b/techlibs/nanoxplore/brams.txt
index 046f54c2340..d151cffa456 100644
--- a/techlibs/nanoxplore/brams.txt
+++ b/techlibs/nanoxplore/brams.txt
@@ -9,7 +9,7 @@ ram block $__NX_RAM_ {
 		abits 14;
 		widths 2 per_port;
 	}
-	ifdef IS_NG_LARGE {
+	ifndef IS_NG_MEDIUM {
 		option "STD_MODE" "NOECC_16kx3" {
 			abits 14;
 			widths 3 per_port;
@@ -20,7 +20,7 @@ ram block $__NX_RAM_ {
 		abits 13;
 		widths 4 per_port;
 	}
-	ifdef IS_NG_LARGE {
+	ifndef IS_NG_MEDIUM {
 		option "STD_MODE" "NOECC_8kx6" {
 			abits 13;
 			widths 6 per_port;
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index 2d80a418910..b54b0e0d91c 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -264,8 +264,8 @@ struct SynthNanoXplorePass : public ScriptPass
 		if (check_label("map_ram"))
 		{
 			std::string args = "";
-			if (family == "large")
-				args += " -D IS_NG_LARGE";
+			if (family == "medium")
+				args += " -D IS_NG_MEDIUM";
 			if (nobram)
 				args += " -no-auto-block";
 			if (norfram)

From 6876a2754786c1f59ee0f3a752142be0f94f6ed5 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 4 Jul 2024 07:41:55 +0200
Subject: [PATCH 329/499] Add NX_DFR simulation model

---
 techlibs/nanoxplore/cells_bb.v  | 38 ++++++++++++++++-----------------
 techlibs/nanoxplore/cells_sim.v | 31 +++++++++++++++++++++++++++
 2 files changed, 50 insertions(+), 19 deletions(-)

diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index c66bfaf08a2..1e98a6f3b9d 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -57,25 +57,25 @@
 //    output O;
 //endmodule
 
-(* blackbox *)
-module NX_DFR(I, CK, L, R, O);
-    input CK;
-    input I;
-    input L;
-    output O;
-    input R;
-    parameter data_inv = 1'b0;
-    parameter dff_edge = 1'b0;
-    parameter dff_init = 1'b0;
-    parameter dff_load = 1'b0;
-    parameter dff_sync = 1'b0;
-    parameter dff_type = 1'b0;
-    parameter iobname = "";
-    parameter location = "";
-    parameter mode = 0;
-    parameter path = 0;
-    parameter ring = 0;
-endmodule
+// (* blackbox *)
+// module NX_DFR(I, CK, L, R, O);
+//     input CK;
+//     input I;
+//     input L;
+//     output O;
+//     input R;
+//     parameter data_inv = 1'b0;
+//     parameter dff_edge = 1'b0;
+//     parameter dff_init = 1'b0;
+//     parameter dff_load = 1'b0;
+//     parameter dff_sync = 1'b0;
+//     parameter dff_type = 1'b0;
+//     parameter iobname = "";
+//     parameter location = "";
+//     parameter mode = 0;
+//     parameter path = 0;
+//     parameter ring = 0;
+// endmodule
 
 // Special mode of NX_DFR
 //(* blackbox *)
diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v
index 86606ce9cd9..7453821d08b 100644
--- a/techlibs/nanoxplore/cells_sim.v
+++ b/techlibs/nanoxplore/cells_sim.v
@@ -36,6 +36,37 @@ always @(posedge clock, posedge async_reset)
 
 endmodule
 
+(* abc9_box, lib_whitebox *)
+module NX_DFR(input I, CK, L, R, output O);
+
+parameter data_inv = 1'b0;
+parameter dff_edge = 1'b0;
+parameter dff_init = 1'b0;
+parameter dff_load = 1'b0;
+parameter dff_sync = 1'b0;
+parameter dff_type = 1'b0;
+parameter iobname = "";
+parameter location = "";
+parameter mode = 0;
+parameter path = 0;
+parameter ring = 0;
+
+wire clock = CK ^ dff_edge;
+wire load = dff_load ? L : 1'b1;
+wire async_reset = !dff_sync && dff_init && R;
+wire sync_reset = dff_sync && dff_init && R;
+reg O_reg;
+
+always @(posedge clock, posedge async_reset)
+	if (async_reset) O_reg <= dff_type;
+	else if (sync_reset) O_reg <= dff_type;
+	else if (load) O_reg <= I;
+
+assign O = data_inv ? O_reg : ~O_reg;
+
+endmodule
+
+
 (* abc9_box, lib_whitebox *)
 module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO);
 parameter add_carry = 0;

From 1a6e5c671f5a3f53a2b1bd99519b96554c06b47e Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 11 Jul 2024 17:43:46 +0200
Subject: [PATCH 330/499] Add meminit handling for  NX_RFB_U

---
 techlibs/nanoxplore/cells_sim_u.v | 27 ++++++++++++++++-
 techlibs/nanoxplore/rf_rams_u.txt |  3 --
 tests/arch/nanoxplore/meminit.v   | 50 +++++++++++++++++++++++++++++++
 tests/arch/nanoxplore/meminit.ys  | 44 +++++++++++++++++++++++++++
 4 files changed, 120 insertions(+), 4 deletions(-)
 create mode 100644 tests/arch/nanoxplore/meminit.v
 create mode 100644 tests/arch/nanoxplore/meminit.ys

diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v
index 209da3b5f80..c2c9c8b34c8 100644
--- a/techlibs/nanoxplore/cells_sim_u.v
+++ b/techlibs/nanoxplore/cells_sim_u.v
@@ -136,13 +136,38 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14
     localparam MEM_SIZE  = mode == 2 ? 64 : 32;
     localparam MEM_WIDTH = mode == 3 ? 36 : 18;
     localparam ADDR_WIDTH = mode == 2 ? 6 : 5;
+    localparam DATA_SIZE = MEM_SIZE * MEM_WIDTH;
+    localparam MAX_SIZE = DATA_SIZE + MEM_SIZE + 1;
 
     reg [MEM_WIDTH-1:0] mem [MEM_SIZE-1:0];
 
+	function [DATA_SIZE-1:0] convert_initval;
+		input [8*MAX_SIZE-1:0] hex_initval;
+		reg done;
+		reg [DATA_SIZE-1:0] temp;
+		reg [7:0] char;
+		integer i,j;
+		begin
+			done = 1'b0;
+			temp = 0;
+            j = 0;
+			for (i = 0; i < MAX_SIZE; i = i + 1) begin
+                char = hex_initval[8*i +: 8];
+                if (char >= "0" && char <= "1") begin
+                    temp[j] = char - "0";
+                    j = j + 1;
+                end
+			end
+			convert_initval = temp;
+		end
+	endfunction
+
     integer i;
+    reg [DATA_SIZE-1:0] mem_data;
     initial begin
+        mem_data = convert_initval(mem_ctxt);
         for (i = 0; i < MEM_SIZE; i = i + 1)
-            mem[i] = 36'b0;
+            mem[i] = mem_data[MEM_WIDTH*(MEM_SIZE-i-1) +: MEM_WIDTH];
     end
 
     wire [ADDR_WIDTH-1:0] WA = (mode==2) ? { WA6, WA5, WA4, WA3, WA2, WA1 } : { WA5, WA4, WA3, WA2, WA1 };
diff --git a/techlibs/nanoxplore/rf_rams_u.txt b/techlibs/nanoxplore/rf_rams_u.txt
index 3dd3d3614ea..94e002eeb9d 100644
--- a/techlibs/nanoxplore/rf_rams_u.txt
+++ b/techlibs/nanoxplore/rf_rams_u.txt
@@ -25,7 +25,6 @@ ram distributed $__NX_RFB_U_DPREG_ {
 		widths 36 global;
 	}
     init no_undef;
-    prune_rom;
 
     port sw "W" {
         clock anyedge;
@@ -43,7 +42,6 @@ ram distributed $__NX_RFB_U_SPREG_ {
     abits 5;
     width 18;
 	init no_undef;
-	prune_rom;
 	port arsw "RW" {
 		clock anyedge;
 	}
@@ -58,7 +56,6 @@ ram distributed $__NX_XRFB_2R_1W_ {
     abits 5;
     width 18;
 	init no_undef;
-	prune_rom;
     port sw "W" {
         clock anyedge;
     }
diff --git a/tests/arch/nanoxplore/meminit.v b/tests/arch/nanoxplore/meminit.v
new file mode 100644
index 00000000000..24d5a57f7bc
--- /dev/null
+++ b/tests/arch/nanoxplore/meminit.v
@@ -0,0 +1,50 @@
+module top(clk);
+parameter DEPTH_LOG2 = 10;
+parameter WIDTH = 36;
+parameter PRIME = 237481091;
+localparam DEPTH = 2**DEPTH_LOG2;
+
+input wire clk;
+
+(* syn_ramstyle = "distributed" *)
+reg [WIDTH-1:0] mem [DEPTH-1:0];
+
+integer i;
+initial begin
+    for (i = 0; i < DEPTH; i = i + 1) begin
+        // Make up data by multiplying a large prime with the address,
+        // then cropping and retaining the lower bits
+        mem[i] = PRIME * (i*2+1);
+    end
+end
+
+reg [DEPTH_LOG2-1:0] counter = 0;
+reg done = 1'b0;
+
+reg did_read = 1'b0;
+reg [DEPTH_LOG2-1:0] read_addr;
+reg [WIDTH-1:0] read_val;
+
+always @(posedge clk) begin
+    if (!done) begin
+        did_read <= 1'b1;
+        read_addr <= counter;
+        read_val <= mem[counter];
+    end else begin
+        did_read <= 1'b0; 
+    end
+
+    if (!done)
+        counter = counter + 1;
+    if (counter == 0)
+        done = 1;
+end
+
+wire [WIDTH-1:0] expect_val = PRIME * (read_addr*2+1);
+always @(posedge clk) begin
+    if (did_read) begin
+        $display("addr %x expected %x actual %x", read_addr, expect_val, read_val);
+        assert(read_val == expect_val);
+    end
+end
+endmodule
diff --git a/tests/arch/nanoxplore/meminit.ys b/tests/arch/nanoxplore/meminit.ys
new file mode 100644
index 00000000000..ca93e65001d
--- /dev/null
+++ b/tests/arch/nanoxplore/meminit.ys
@@ -0,0 +1,44 @@
+read_verilog -sv meminit.v
+chparam -set DEPTH_LOG2 5 -set WIDTH 36
+prep
+opt_dff
+prep -rdff
+synth_nanoxplore 
+clean_zerowidth
+select -assert-none t:$mem_v2 t:$mem
+read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
+prep
+async2sync
+hierarchy -top top
+sim -assert -q -n 66 -clock clk
+
+design -reset
+read_verilog -sv meminit.v
+chparam -set DEPTH_LOG2 6 -set WIDTH 18
+prep
+opt_dff
+prep -rdff
+synth_nanoxplore 
+clean_zerowidth
+select -assert-none t:$mem_v2 t:$mem
+read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
+prep
+async2sync
+hierarchy -top top
+sim -assert -q -n 34 -clock clk
+
+
+design -reset
+read_verilog -sv meminit.v
+chparam -set DEPTH_LOG2 8 -set WIDTH 18
+prep
+opt_dff
+prep -rdff
+synth_nanoxplore 
+clean_zerowidth
+select -assert-none t:$mem_v2 t:$mem
+read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
+prep
+async2sync
+hierarchy -top top
+sim -assert -q -n 258 -clock clk

From 8f806c0d129c6878c4d57999584a4a6fb4a29744 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 24 Jul 2024 13:00:56 +0200
Subject: [PATCH 331/499] Added DDFR support

---
 techlibs/nanoxplore/cells_sim_u.v  |  54 +++++++++++++++
 techlibs/nanoxplore/cells_wrap_u.v | 105 +++++++++++++++++++++++------
 2 files changed, 138 insertions(+), 21 deletions(-)

diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v
index c2c9c8b34c8..af46b24b0d2 100644
--- a/techlibs/nanoxplore/cells_sim_u.v
+++ b/techlibs/nanoxplore/cells_sim_u.v
@@ -250,3 +250,57 @@ module NX_WFG_U(R, SI, ZI, SO, ZO);
             $error("Unknown NX_WFG_U mode");
     endgenerate
 endmodule
+
+module NX_DDFR_U(CK,CKF,R,I,I2,L,O,O2);
+    input CK;
+    input CKF;
+    input R;
+    input I;
+    input I2;
+    input L;
+    output O;
+    output O2;
+
+    parameter location = "";
+    parameter path = 0;
+    parameter dff_type = 1'b0;
+    parameter dff_sync = 1'b0;
+    parameter dff_load = 1'b0;
+
+    wire load = dff_load ? 1'b1 : L; // reversed when compared to DFF
+    wire async_reset = !dff_sync && R;
+    wire sync_reset = dff_sync && R;
+
+    generate
+        if (path==1) begin
+            // IDDFR
+            always @(posedge CK, posedge async_reset)
+                if (async_reset) O <= dff_type;
+                else if (sync_reset) O <= dff_type;
+                else if (load) O <= I;
+
+            always @(posedge CKF, posedge async_reset)
+                if (async_reset) O2 <= dff_type;
+                else if (sync_reset) O2 <= dff_type;
+                else if (load) O2 <= I;
+        end
+        else if (path==0 || path==2) begin
+            reg q1, q2;
+            // ODDFR
+            always @(posedge CK, posedge async_reset)
+                if (async_reset) q1 <= dff_type;
+                else if (sync_reset) q1 <= dff_type;
+                else if (load) q1 <= I;
+
+            always @(posedge CKF, posedge async_reset)
+                if (async_reset) q2 <= dff_type;
+                else if (sync_reset) q2 <= dff_type;
+                else if (load) q2 <= I2;
+
+            assign O = CK ? q1 : q2;
+        end
+        else
+            $error("Unknown NX_DDFR_U path");
+    endgenerate
+
+endmodule
diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v
index c9eaa5e5b8f..e504f734483 100644
--- a/techlibs/nanoxplore/cells_wrap_u.v
+++ b/techlibs/nanoxplore/cells_wrap_u.v
@@ -1,18 +1,82 @@
+
+module NX_ODDFR_U(CK,R,I1,I2,L,O);
+    input CK;
+    input R;
+    input I1;
+    input I2;
+    input L;
+    output O;
+
+    parameter location = "";
+    parameter path = 0;
+    parameter dff_type = 1'b0;
+    parameter dff_sync = 1'b0;
+    parameter dff_load = 1'b0;
+
+  NX_DDFR_U #(
+      .location(location),
+      .path(path),
+      .dff_type(dff_type),
+      .dff_sync(dff_sync),
+      .dff_load(dff_load)
+  ) _TECHMAP_REPLACE_ (
+      .CK(CK),
+      .CKF(CK),
+      .R(R),
+      .I(I1),
+      .I2(I2),
+      .L(L),
+      .O(O),
+      .O2()
+  );
+endmodule
+
+module NX_IDDFR_U(CK,R,I,L,O1,O2);
+    input CK;
+    input R;
+    input I;
+    input L;
+    output O1;
+    output O2;
+
+    parameter location = "";
+    parameter dff_type = 1'b0;
+    parameter dff_sync = 1'b0;
+    parameter dff_load = 1'b0;
+
+  NX_DDFR_U #(
+      .location(location),
+      .path(1),
+      .dff_type(dff_type),
+      .dff_sync(dff_sync),
+      .dff_load(dff_load)
+  ) _TECHMAP_REPLACE_ (
+      .CK(CK),
+      .CKF(CK),
+      .R(R),
+      .I(I),
+      .I2(1'b0),
+      .L(L),
+      .O(O1),
+      .O2(O2)
+  );
+endmodule
+
 module NX_CKS_U(CKI, CMD, CKO);
     input CKI;
     output CKO;
     input CMD;
 
-NX_GCK_U #(
-    .inv_in(1'b0),
-    .inv_out(1'b0),
-    .std_mode("CKS")
-) _TECHMAP_REPLACE_ (
-    .CMD(CMD),
-    .SI1(CKI),
-    .SI2(),
-    .SO(CKO)
-);
+  NX_GCK_U #(
+      .inv_in(1'b0),
+      .inv_out(1'b0),
+      .std_mode("CKS")
+  ) _TECHMAP_REPLACE_ (
+      .CMD(CMD),
+      .SI1(CKI),
+      .SI2(),
+      .SO(CKO)
+  );
 endmodule
 
 module NX_CMUX_U(CKI0, CKI1, SEL, CKO);
@@ -21,16 +85,16 @@ module NX_CMUX_U(CKI0, CKI1, SEL, CKO);
     output CKO;
     input SEL;
 
-NX_GCK_U #(
-    .inv_in(1'b0),
-    .inv_out(1'b0),
-    .std_mode("MUX")
-) _TECHMAP_REPLACE_ (
-    .CMD(SEL),
-    .SI1(CKI0),
-    .SI2(CKI1),
-    .SO(CKO)
-);
+  NX_GCK_U #(
+      .inv_in(1'b0),
+      .inv_out(1'b0),
+      .std_mode("MUX")
+  ) _TECHMAP_REPLACE_ (
+      .CMD(SEL),
+      .SI1(CKI0),
+      .SI2(CKI1),
+      .SO(CKO)
+  );
 endmodule
 
 module NX_CDC_U_2DFF(CK1, CK2, ADRSTI, ADRSTO, BDRSTI, BDRSTO, BI, AO, BO, AI);
@@ -3440,4 +3504,3 @@ module NX_HSSL_U_FULL(hssl_clk_user_tx_i, hssl_clk_user_rx_i, hssl_clk_ref_i, hs
     parameter rx_usrclk_use_pcs_clk_2 = 1'b0;
     parameter tx_usrclk_use_pcs_clk_2 = 1'b0;
 endmodule
-

From 262ad03cd3a9acc24eeb14b3fb11fa9b0c8b2ccd Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 24 Jul 2024 13:23:34 +0200
Subject: [PATCH 332/499] Add iopads by default add option to disable and keep
 old one for compatibility

---
 techlibs/nanoxplore/synth_nanoxplore.cc | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index b54b0e0d91c..394b0ab54e2 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -85,8 +85,8 @@ struct SynthNanoXplorePass : public ScriptPass
 		log("    -nodsp\n");
 		log("        do not map multipliers to NX_DSP cells\n");
 		log("\n");
-		log("    -iopad\n");
-		log("       insert IO buffers\n");
+		log("    -noiopad\n");
+		log("        do not insert IO buffers\n");
 		log("\n");
 		log("    -no-rw-check\n");
 		log("        marks all recognized read ports as \"return don't-care value on\n");
@@ -100,7 +100,7 @@ struct SynthNanoXplorePass : public ScriptPass
 	}
 
 	string top_opt, json_file, family;
-	bool flatten, abc9, nocy, nodffe, norfram, nobram, nodsp, iopad, no_rw_check;
+	bool flatten, abc9, nocy, nodffe, norfram, nobram, nodsp, noiopad, no_rw_check;
 	std::string postfix;
 
 	void clear_flags() override
@@ -115,7 +115,7 @@ struct SynthNanoXplorePass : public ScriptPass
 		norfram = false;
 		nobram = false;
 		nodsp = false;
-		iopad = false;
+		noiopad = false;
 		no_rw_check = false;
 		postfix = "";
 	}
@@ -181,7 +181,11 @@ struct SynthNanoXplorePass : public ScriptPass
 				continue;
 			}
 			if (args[argidx] == "-iopad") {
-				iopad = true;
+				noiopad = false;
+				continue;
+			}
+			if (args[argidx] == "-noiopad") {
+				noiopad = true;
 				continue;
 			}
 			if (args[argidx] == "-no-rw-check") {
@@ -293,8 +297,8 @@ struct SynthNanoXplorePass : public ScriptPass
 				run("techmap -map +/techmap.v -map +/nanoxplore/arith_map.v");
 				run("nx_carry");
 			}
-			if (help_mode || iopad) {
-				run("iopadmap -bits -outpad $__BEYOND_OBUF I:PAD -toutpad $__BEYOND_TOBUF C:I:PAD -inpad $__BEYOND_IBUF O:PAD -tinoutpad $__BEYOND_IOBUF C:O:I:PAD A:top", "(only if '-iopad')");
+			if (help_mode || !noiopad) {
+				run("iopadmap -bits -outpad $__BEYOND_OBUF I:PAD -toutpad $__BEYOND_TOBUF C:I:PAD -inpad $__BEYOND_IBUF O:PAD -tinoutpad $__BEYOND_IOBUF C:O:I:PAD A:top", "(skip if '-noiopad')");
 				run("techmap -map +/nanoxplore/io_map.v");
 			}
 			run("opt -fast");

From 3848563600bfc60d2849670a725d1e951dff606c Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 24 Jul 2024 13:29:51 +0200
Subject: [PATCH 333/499] Update tests

---
 tests/arch/nanoxplore/add_sub.ys |  6 +++---
 tests/arch/nanoxplore/adffs.ys   |  8 ++++----
 tests/arch/nanoxplore/dffs.ys    |  4 ++--
 tests/arch/nanoxplore/fsm.ys     |  2 +-
 tests/arch/nanoxplore/latches.ys |  6 +++---
 tests/arch/nanoxplore/logic.ys   |  2 +-
 tests/arch/nanoxplore/lutram.ys  | 10 +++++-----
 tests/arch/nanoxplore/mux.ys     |  8 ++++----
 tests/arch/nanoxplore/shifter.ys |  2 +-
 tests/arch/nanoxplore/tribuf.ys  |  2 +-
 10 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/tests/arch/nanoxplore/add_sub.ys b/tests/arch/nanoxplore/add_sub.ys
index 9b23cef1533..f7895ac5bb2 100644
--- a/tests/arch/nanoxplore/add_sub.ys
+++ b/tests/arch/nanoxplore/add_sub.ys
@@ -1,7 +1,7 @@
 read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
-equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore -noiopad
 opt -full
 
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
@@ -30,7 +30,7 @@ EOT
 
 hierarchy -top top
 proc
-equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore -noiopad
 opt -full
 
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
@@ -58,7 +58,7 @@ EOT
 
 hierarchy -top top
 proc
-equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore -noiopad
 opt -full
 
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
diff --git a/tests/arch/nanoxplore/adffs.ys b/tests/arch/nanoxplore/adffs.ys
index 9f4e1fac786..7fe24a0b583 100644
--- a/tests/arch/nanoxplore/adffs.ys
+++ b/tests/arch/nanoxplore/adffs.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top adff
 proc
-equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:NX_DFF
@@ -14,7 +14,7 @@ select -assert-none t:NX_DFF %% t:* %D
 design -load read
 hierarchy -top adffn
 proc
-equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:NX_DFF
@@ -26,7 +26,7 @@ select -assert-none t:NX_DFF t:NX_LUT %% t:* %D
 design -load read
 hierarchy -top dffs
 proc
-equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:NX_DFF
@@ -38,7 +38,7 @@ select -assert-none t:NX_DFF t:NX_LUT %% t:* %D
 design -load read
 hierarchy -top ndffnr
 proc
-equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:NX_DFF
diff --git a/tests/arch/nanoxplore/dffs.ys b/tests/arch/nanoxplore/dffs.ys
index 898765408c0..6643b01a52f 100644
--- a/tests/arch/nanoxplore/dffs.ys
+++ b/tests/arch/nanoxplore/dffs.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top dff
 proc
-equiv_opt -assert -async2sync -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+equiv_opt -assert -async2sync -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:NX_DFF
@@ -13,7 +13,7 @@ select -assert-none t:NX_DFF %% t:* %D
 design -load read
 hierarchy -top dffe
 proc
-equiv_opt -assert -async2sync -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+equiv_opt -assert -async2sync -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:NX_DFF
diff --git a/tests/arch/nanoxplore/fsm.ys b/tests/arch/nanoxplore/fsm.ys
index f5d44453d6d..136b220b737 100644
--- a/tests/arch/nanoxplore/fsm.ys
+++ b/tests/arch/nanoxplore/fsm.ys
@@ -3,7 +3,7 @@ hierarchy -top fsm
 proc
 flatten
 
-equiv_opt -run :prove -map +/nanoxplore/cells_sim.v synth_nanoxplore
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad
 async2sync
 miter -equiv -make_assert -flatten gold gate miter
 sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
diff --git a/tests/arch/nanoxplore/latches.ys b/tests/arch/nanoxplore/latches.ys
index 4625348f916..b2eccfd80ae 100644
--- a/tests/arch/nanoxplore/latches.ys
+++ b/tests/arch/nanoxplore/latches.ys
@@ -4,7 +4,7 @@ design -save read
 hierarchy -top latchp
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_nanoxplore
+synth_nanoxplore -noiopad
 cd latchp # Constrain all select calls below inside the top module
 select -assert-count 1 t:NX_LUT
 
@@ -15,7 +15,7 @@ design -load read
 hierarchy -top latchn
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_nanoxplore
+synth_nanoxplore -noiopad
 cd latchn # Constrain all select calls below inside the top module
 select -assert-count 1 t:NX_LUT
 
@@ -26,7 +26,7 @@ design -load read
 hierarchy -top latchsr
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_nanoxplore
+synth_nanoxplore -noiopad
 cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 2 t:NX_LUT
 
diff --git a/tests/arch/nanoxplore/logic.ys b/tests/arch/nanoxplore/logic.ys
index 2edcbfebd79..061ab7a7de5 100644
--- a/tests/arch/nanoxplore/logic.ys
+++ b/tests/arch/nanoxplore/logic.ys
@@ -1,7 +1,7 @@
 read_verilog ../common/logic.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/arch/nanoxplore/lutram.ys b/tests/arch/nanoxplore/lutram.ys
index 547e03b30b7..61b813bfb11 100644
--- a/tests/arch/nanoxplore/lutram.ys
+++ b/tests/arch/nanoxplore/lutram.ys
@@ -26,7 +26,7 @@ EOT
 hierarchy -top lutram_dpreg
 proc
 memory -nomap
-equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore -noiopad
 memory
 opt -full
 
@@ -48,7 +48,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 18
 proc
 memory -nomap
-equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore -noiopad
 memory
 opt -full
 
@@ -68,7 +68,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r -chparam A_WIDTH 6 -chparam D_WIDTH 18
 proc
 memory -nomap
-equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore -noiopad
 memory
 opt -full
 
@@ -88,7 +88,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 36
 proc
 memory -nomap
-equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore -noiopad
 memory
 opt -full
 
@@ -131,7 +131,7 @@ EOT
 hierarchy -top lutram_1w2r -chparam A_WIDTH 5 -chparam D_WIDTH 18
 proc
 memory -nomap
-equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore -noiopad
 memory
 opt -full
 
diff --git a/tests/arch/nanoxplore/mux.ys b/tests/arch/nanoxplore/mux.ys
index 8c92ab15609..f6309ce4013 100644
--- a/tests/arch/nanoxplore/mux.ys
+++ b/tests/arch/nanoxplore/mux.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top mux2
 proc
-equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux2 # Constrain all select calls below inside the top module
 select -assert-count 1 t:NX_LUT
@@ -13,7 +13,7 @@ select -assert-none t:NX_LUT %% t:* %D
 design -load read
 hierarchy -top mux4
 proc
-equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
 #select -assert-count 2 t:NX_LUT
@@ -23,7 +23,7 @@ select -assert-none t:NX_LUT %% t:* %D
 design -load read
 hierarchy -top mux8
 proc
-equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
 #select -assert-count 5 t:NX_LUT
@@ -33,7 +33,7 @@ select -assert-none t:NX_LUT %% t:* %D
 design -load read
 hierarchy -top mux16
 proc
-equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
 select -assert-max 13 t:NX_LUT
diff --git a/tests/arch/nanoxplore/shifter.ys b/tests/arch/nanoxplore/shifter.ys
index a3502df2a3e..f30e653e3cf 100644
--- a/tests/arch/nanoxplore/shifter.ys
+++ b/tests/arch/nanoxplore/shifter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/arch/nanoxplore/tribuf.ys b/tests/arch/nanoxplore/tribuf.ys
index e55764f0126..b3df55ac95f 100644
--- a/tests/arch/nanoxplore/tribuf.ys
+++ b/tests/arch/nanoxplore/tribuf.ys
@@ -4,7 +4,7 @@ proc
 tribuf
 flatten
 synth
-equiv_opt -assert -map +/nanoxplore/cells_sim.v -map +/simcells.v synth_nanoxplore -iopad # equivalency check
+equiv_opt -assert -map +/nanoxplore/cells_sim.v -map +/simcells.v synth_nanoxplore # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
 #Internal cell type used. Need support it.

From 7bf623a0c75453bedd4922321226f67c087e2d46 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 24 Jul 2024 13:34:41 +0200
Subject: [PATCH 334/499] Fix simulation model warnings

---
 techlibs/nanoxplore/cells_sim_u.v | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v
index af46b24b0d2..0456a46911e 100644
--- a/techlibs/nanoxplore/cells_sim_u.v
+++ b/techlibs/nanoxplore/cells_sim_u.v
@@ -181,19 +181,19 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14
                          I9,  I8,  I7,  I6,  I5,  I4,  I3,  I2,  I1 };
     generate 
         if (mode==0) begin
-            assign O[17:0] = mem[{ RA5, RA4, RA3, RA2, RA1 }];
+            assign O = mem[{ RA5, RA4, RA3, RA2, RA1 }];
         end
         else if (mode==1) begin
-            assign O[17:0] = mem[{ WA5, WA4, WA3, WA2, WA1 }];
+            assign O = mem[{ WA5, WA4, WA3, WA2, WA1 }];
         end
         else if (mode==2) begin
-            assign O[17:0] = mem[{ RA6, RA5, RA4, RA3, RA2, RA1 }];
+            assign O = mem[{ RA6, RA5, RA4, RA3, RA2, RA1 }];
         end
         else if (mode==3) begin
-            assign O[35:0] = mem[{ RA5, RA4, RA3, RA2, RA1 }];
+            assign O = mem[{ RA5, RA4, RA3, RA2, RA1 }];
         end
         else if (mode==4) begin
-            assign O[35:0] = { mem[{ RA10, RA9, RA8, RA7, RA6 }], mem[{ RA5, RA4, RA3, RA2, RA1 }] };
+            assign O = { mem[{ RA10, RA9, RA8, RA7, RA6 }], mem[{ RA5, RA4, RA3, RA2, RA1 }] };
         end
         else 
             $error("Unknown NX_RFB_U mode");

From dbf1d037e806e925db6ba249432cc90dd64605a1 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 24 Jul 2024 13:41:12 +0200
Subject: [PATCH 335/499] Cleanup

---
 techlibs/nanoxplore/brams_map.v   |  2 +-
 techlibs/nanoxplore/cells_bb.v    | 92 -------------------------------
 techlibs/nanoxplore/cells_sim_u.v | 30 +++++-----
 tests/arch/nanoxplore/add_sub.ys  |  2 +-
 4 files changed, 17 insertions(+), 109 deletions(-)

diff --git a/techlibs/nanoxplore/brams_map.v b/techlibs/nanoxplore/brams_map.v
index 4609eee8409..506e2dd0bdd 100644
--- a/techlibs/nanoxplore/brams_map.v
+++ b/techlibs/nanoxplore/brams_map.v
@@ -81,4 +81,4 @@ NX_RAM_WRAP #(
     .BI(B_DATA),
     .BO(PORT_B_RD_DATA)
 );
-endmodule
\ No newline at end of file
+endmodule
diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index 1e98a6f3b9d..919a02f820d 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -1,95 +1,3 @@
-//(* blackbox *)
-//module NX_LUT(I1, I2, I3, I4, O);
-//    input I1;
-//    input I2;
-//    input I3;
-//    input I4;
-//    output O;
-//    parameter lut_table = 16'b0000000000000000;
-//endmodule
-
-//(* blackbox *)
-//module NX_CY(A1, A2, A3, A4, B1, B2, B3, B4, CI, CO, S1, S2, S3, S4);
-//    input A1;
-//    input A2;
-//    input A3;
-//    input A4;
-//    input B1;
-//    input B2;
-//    input B3;
-//    input B4;
-//    input CI;
-//    output CO;
-//    output S1;
-//    output S2;
-//    output S3;
-//    output S4;
-//    parameter add_carry = 0;
-//endmodule
-
-// Bypass mode of NX_GCK_U
-//(* blackbox *)
-//module NX_BD(I, O);
-//    input I;
-//    output O;
-//    parameter mode = "global_lowskew";
-//endmodule
-
-//(* blackbox *)
-//module NX_DFF(I, CK, L, R, O);
-//    input CK;
-//    input I;
-//    input L;
-//    output O;
-//    input R;
-//    parameter dff_ctxt = 1'b0;
-//    parameter dff_edge = 1'b0;
-//    parameter dff_init = 1'b0;
-//    parameter dff_load = 1'b0;
-//    parameter dff_sync = 1'b0;
-//    parameter dff_type = 1'b0;
-//endmodule
-
-// Special mode of NX_DFF
-//(* blackbox *)
-//module NX_BFF(I, O);
-//    input I;
-//    output O;
-//endmodule
-
-// (* blackbox *)
-// module NX_DFR(I, CK, L, R, O);
-//     input CK;
-//     input I;
-//     input L;
-//     output O;
-//     input R;
-//     parameter data_inv = 1'b0;
-//     parameter dff_edge = 1'b0;
-//     parameter dff_init = 1'b0;
-//     parameter dff_load = 1'b0;
-//     parameter dff_sync = 1'b0;
-//     parameter dff_type = 1'b0;
-//     parameter iobname = "";
-//     parameter location = "";
-//     parameter mode = 0;
-//     parameter path = 0;
-//     parameter ring = 0;
-// endmodule
-
-// Special mode of NX_DFR
-//(* blackbox *)
-//module NX_BFR(I, O);
-//    input I;
-//    output O;
-//    parameter data_inv = 1'b0;
-//    parameter iobname = "";
-//    parameter location = "";
-//    parameter mode = 0;
-//    parameter path = 0;
-//    parameter ring = 0;
-//endmodule
-
 // NX_RAM related
 (* blackbox *)
 module NX_ECC(CKD, CHK, COR, ERR);
diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v
index 0456a46911e..e11aaabee68 100644
--- a/techlibs/nanoxplore/cells_sim_u.v
+++ b/techlibs/nanoxplore/cells_sim_u.v
@@ -12,20 +12,21 @@ module NX_GCK_U(SI1, SI2, CMD, SO);
     wire SI2_int = inv_in ? ~SI2 : SI2;
 
     wire SO_int;
-    generate if (std_mode == "BYPASS") begin
-        assign SO_int = SI1_int;
-    end
-    else if (std_mode == "MUX") begin
-        assign SO_int = CMD ? SI1_int : SI2_int;
-    end
-    else if (std_mode == "CKS") begin
-        assign SO_int = CMD ? SI1_int : 1'b0;
-    end
-    else if (std_mode == "CSC") begin
-        assign SO_int = CMD;
-    end
-    else
-    $error("Unrecognised std_mode");
+    generate
+        if (std_mode == "BYPASS") begin
+            assign SO_int = SI1_int;
+        end
+        else if (std_mode == "MUX") begin
+            assign SO_int = CMD ? SI1_int : SI2_int;
+        end
+        else if (std_mode == "CKS") begin
+            assign SO_int = CMD ? SI1_int : 1'b0;
+        end
+        else if (std_mode == "CSC") begin
+            assign SO_int = CMD;
+        end
+        else
+            $error("Unrecognised std_mode");
     endgenerate
     assign SO = inv_out ? ~SO_int : SO_int;
 endmodule
@@ -302,5 +303,4 @@ module NX_DDFR_U(CK,CKF,R,I,I2,L,O,O2);
         else
             $error("Unknown NX_DDFR_U path");
     endgenerate
-
 endmodule
diff --git a/tests/arch/nanoxplore/add_sub.ys b/tests/arch/nanoxplore/add_sub.ys
index f7895ac5bb2..9356944c8ac 100644
--- a/tests/arch/nanoxplore/add_sub.ys
+++ b/tests/arch/nanoxplore/add_sub.ys
@@ -68,4 +68,4 @@ design -load postopt
 cd top
 stat
 select -assert-count 48 t:NX_CY
-select -assert-none t:NX_CY %% t:* %D
\ No newline at end of file
+select -assert-none t:NX_CY %% t:* %D

From 220ddeac4d3db35cf439ca31c542d860d46efb62 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 14 Aug 2024 12:13:15 +0200
Subject: [PATCH 336/499] Set -mince and -minsrst

---
 techlibs/nanoxplore/synth_nanoxplore.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index 394b0ab54e2..cb2bb8a9670 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -312,7 +312,7 @@ struct SynthNanoXplorePass : public ScriptPass
 			} else if (!nodffe) {
 				dfflegalize_args += " -cell $_DFFE_?P_ 01 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r";
 			}
-			dfflegalize_args += " -cell $_DLATCH_?_ x";
+			dfflegalize_args += " -cell $_DLATCH_?_ x -mince 8 -minsrst 8";
 			run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)");
 			run("techmap -map +/nanoxplore/latches_map.v");
 			run("techmap -map +/nanoxplore/cells_map.v");

From 14e43139cbfcefe75a36ce57f5c345b0de30a339 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 14 Aug 2024 12:14:21 +0200
Subject: [PATCH 337/499] Run opt_merge, helps with inverted reset/load signals

---
 techlibs/nanoxplore/synth_nanoxplore.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index cb2bb8a9670..0948bb5ca24 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -314,6 +314,7 @@ struct SynthNanoXplorePass : public ScriptPass
 			}
 			dfflegalize_args += " -cell $_DLATCH_?_ x -mince 8 -minsrst 8";
 			run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)");
+			run("opt_merge");
 			run("techmap -map +/nanoxplore/latches_map.v");
 			run("techmap -map +/nanoxplore/cells_map.v");
 			run("opt_expr -undriven -mux_undef");

From 54d237ff82c72714c094f8abd149b5a317aeea9f Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 15 Aug 2024 09:42:27 +0200
Subject: [PATCH 338/499] add min_ce_use and min_srst_use parameters

---
 techlibs/nanoxplore/synth_nanoxplore.cc | 21 ++++++++++++++++++++-
 tests/arch/nanoxplore/dffs.ys           |  3 ++-
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index 0948bb5ca24..8349caa21d5 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -76,6 +76,14 @@ struct SynthNanoXplorePass : public ScriptPass
 		log("    -nodffe\n");
 		log("        do not use flipflops with L in output netlist\n");
 		log("\n");
+		log("    -min_ce_use <min_ce_use>\n");
+		log("        do not use flip-flops with load signal if the resulting count is less\n");
+		log("        than min_ce_use in output netlist\n");
+		log("\n");
+		log("    -min_srst_use <min_srst_use>\n");
+		log("        do not use flip-flops with async reset signal if the resulting count is less\n");
+		log("        than min_srst_use in output netlist\n");
+		log("\n");
 		log("    -norfram\n");
 		log("        do not use Register File RAM cells in output netlist\n");
 		log("\n");
@@ -102,6 +110,7 @@ struct SynthNanoXplorePass : public ScriptPass
 	string top_opt, json_file, family;
 	bool flatten, abc9, nocy, nodffe, norfram, nobram, nodsp, noiopad, no_rw_check;
 	std::string postfix;
+	int min_ce_use, min_srst_use;
 
 	void clear_flags() override
 	{
@@ -118,6 +127,8 @@ struct SynthNanoXplorePass : public ScriptPass
 		noiopad = false;
 		no_rw_check = false;
 		postfix = "";
+		min_ce_use = 8;
+		min_srst_use = 8;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -168,6 +179,14 @@ struct SynthNanoXplorePass : public ScriptPass
 				nodffe = true;
 				continue;
 			}
+			if (args[argidx] == "-min_ce_use" && argidx+1 < args.size()) {
+				min_ce_use = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-min_srst_use" && argidx+1 < args.size()) {
+				min_srst_use = atoi(args[++argidx].c_str());
+				continue;
+			}
 			if (args[argidx] == "-norfram") {
 				norfram = true;
 				continue;
@@ -312,7 +331,7 @@ struct SynthNanoXplorePass : public ScriptPass
 			} else if (!nodffe) {
 				dfflegalize_args += " -cell $_DFFE_?P_ 01 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r";
 			}
-			dfflegalize_args += " -cell $_DLATCH_?_ x -mince 8 -minsrst 8";
+			dfflegalize_args += stringf(" -cell $_DLATCH_?_ x -mince %d -minsrst %d", min_ce_use, min_srst_use);
 			run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)");
 			run("opt_merge");
 			run("techmap -map +/nanoxplore/latches_map.v");
diff --git a/tests/arch/nanoxplore/dffs.ys b/tests/arch/nanoxplore/dffs.ys
index 6643b01a52f..5b1e2e360ea 100644
--- a/tests/arch/nanoxplore/dffs.ys
+++ b/tests/arch/nanoxplore/dffs.ys
@@ -13,9 +13,10 @@ select -assert-none t:NX_DFF %% t:* %D
 design -load read
 hierarchy -top dffe
 proc
-equiv_opt -assert -async2sync -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check
+equiv_opt -assert -async2sync -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad -min_ce_use 0 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
+stat
 select -assert-count 1 t:NX_DFF
 
 select -assert-none t:NX_DFF %% t:* %D

From 7b47f645d7e2ea94fc581ae3a69f5df2169814d8 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 16 Aug 2024 04:30:31 +1200
Subject: [PATCH 339/499] Address warnings

- Setting default values
- Fixing mismatched types
- Guarding unused var
---
 kernel/fmt.cc         | 2 +-
 kernel/satgen.cc      | 6 +++---
 libs/fst/fstapi.cc    | 4 ++++
 passes/techmap/abc.cc | 2 +-
 4 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/kernel/fmt.cc b/kernel/fmt.cc
index cbf2d12e9ac..d1c6b8ac96d 100644
--- a/kernel/fmt.cc
+++ b/kernel/fmt.cc
@@ -832,7 +832,7 @@ std::string Fmt::render() const
 						}
 					} else log_abort();
 					if (part.justify == FmtPart::NUMERIC && part.group && part.padding == '0') {
-						int group_size = part.base == 10 ? 3 : 4;
+						size_t group_size = part.base == 10 ? 3 : 4;
 						while (prefix.size() + buf.size() < part.width) {
 							if (buf.size() % (group_size + 1) == group_size)
 								buf += '_';
diff --git a/kernel/satgen.cc b/kernel/satgen.cc
index baaf22d1faf..a6db78868a3 100644
--- a/kernel/satgen.cc
+++ b/kernel/satgen.cc
@@ -1228,7 +1228,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 			if (ff.has_srst && ff.has_ce && ff.ce_over_srst) {
 				int srst = importDefSigSpec(ff.sig_srst, timestep-1).at(0);
 				std::vector<int> rval = importDefSigSpec(ff.val_srst, timestep-1);
-				int undef_srst;
+				int undef_srst = -1;
 				std::vector<int> undef_rval;
 				if (model_undef) {
 					undef_srst = importUndefSigSpec(ff.sig_srst, timestep-1).at(0);
@@ -1242,7 +1242,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 			if (ff.has_ce) {
 				int ce = importDefSigSpec(ff.sig_ce, timestep-1).at(0);
 				std::vector<int> old_q = importDefSigSpec(ff.sig_q, timestep-1);
-				int undef_ce;
+				int undef_ce = -1;
 				std::vector<int> undef_old_q;
 				if (model_undef) {
 					undef_ce = importUndefSigSpec(ff.sig_ce, timestep-1).at(0);
@@ -1256,7 +1256,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 			if (ff.has_srst && !(ff.has_ce && ff.ce_over_srst)) {
 				int srst = importDefSigSpec(ff.sig_srst, timestep-1).at(0);
 				std::vector<int> rval = importDefSigSpec(ff.val_srst, timestep-1);
-				int undef_srst;
+				int undef_srst = -1;
 				std::vector<int> undef_rval;
 				if (model_undef) {
 					undef_srst = importUndefSigSpec(ff.sig_srst, timestep-1).at(0);
diff --git a/libs/fst/fstapi.cc b/libs/fst/fstapi.cc
index 592b5cae6a7..14c981a429d 100644
--- a/libs/fst/fstapi.cc
+++ b/libs/fst/fstapi.cc
@@ -5536,7 +5536,9 @@ char *fstReaderGetValueFromHandleAtTime(void *ctx, uint64_t tim, fstHandle facid
     fst_off_t blkpos = 0, prev_blkpos;
     uint64_t beg_tim, end_tim, beg_tim2, end_tim2;
     int sectype;
+#ifdef FST_DEBUG
     unsigned int secnum = 0;
+#endif
     uint64_t seclen;
     uint64_t tsec_uclen = 0, tsec_clen = 0;
     uint64_t tsec_nitems;
@@ -5620,7 +5622,9 @@ char *fstReaderGetValueFromHandleAtTime(void *ctx, uint64_t tim, fstHandle facid
         }
 
         blkpos += seclen;
+#ifdef FST_DEBUG
         secnum++;
+#endif
     }
 
     xc->rvat_beg_tim = beg_tim;
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index b33e1a17df4..07f9ee45d82 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1718,7 +1718,7 @@ struct AbcPass : public Pass {
 			show_tempdir = true;
 		}
 
-		size_t argidx, g_argidx;
+		size_t argidx, g_argidx = -1;
 		bool g_arg_from_cmd = false;
 #if defined(__wasm)
 		const char *pwd = ".";

From 636ce9ac2ce3386c28b256712530580dc08c4c71 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 16 Aug 2024 04:30:36 +1200
Subject: [PATCH 340/499] snprintf

---
 libs/fst/fstapi.cc     | 36 ++++++++++++++++++------------------
 libs/minisat/System.cc |  4 ++--
 2 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/libs/fst/fstapi.cc b/libs/fst/fstapi.cc
index 14c981a429d..b0f4a83c942 100644
--- a/libs/fst/fstapi.cc
+++ b/libs/fst/fstapi.cc
@@ -1991,7 +1991,7 @@ void fstWriterClose(void *ctx)
             fflush(xc->handle);
 
 #ifndef __MINGW32__
-            sprintf(fnam, "%s.hier", xc->filename);
+            snprintf(fnam, sizeof(fnam), "%s.hier", xc->filename);
             unlink(fnam);
             free(fnam);
 #endif
@@ -2616,7 +2616,7 @@ fstEnumHandle fstWriterCreateEnumTable(void *ctx, const char *name, uint32_t ele
         uint32_t i;
 
         name_len = strlen(name);
-        elem_count_len = sprintf(elem_count_buf, "%" PRIu32, elem_count);
+        elem_count_len = snprintf(elem_count_buf, sizeof(elem_count_buf), "%" PRIu32, elem_count);
 
         literal_lens = (unsigned int *)calloc(elem_count, sizeof(unsigned int));
         val_lens = (unsigned int *)calloc(elem_count, sizeof(unsigned int));
@@ -3594,7 +3594,7 @@ static int fstReaderRecreateHierFile(struct fstReaderContext *xc)
             htyp = xc->contains_hier_section_lz4duo ? FST_BL_HIER_LZ4DUO : FST_BL_HIER_LZ4;
         }
 
-        sprintf(fnam, "%s.hier_%d_%p", xc->filename, getpid(), (void *)xc);
+        snprintf(fnam, sizeof(fnam), "%s.hier_%d_%p", xc->filename, getpid(), (void *)xc);
         fstReaderFseeko(xc, xc->f, xc->hier_pos, SEEK_SET);
         uclen = fstReaderUint64(xc->f);
 #ifndef __MINGW32__
@@ -4241,7 +4241,7 @@ int fstReaderInit(struct fstReaderContext *xc)
 
         hf = (char *)calloc(1, flen + 16 + 32 + 1);
 
-        sprintf(hf, "%s.upk_%d_%p", xc->filename, getpid(), (void *)xc);
+        snprintf(hf, sizeof(hf), "%s.upk_%d_%p", xc->filename, getpid(), (void *)xc);
         fcomp = fopen(hf, "w+b");
         if (!fcomp) {
             fcomp = tmpfile_open(&xc->f_nam);
@@ -4799,21 +4799,21 @@ int fstReaderIterBlocks2(void *ctx,
 
                     if (beg_tim) {
                         if (dumpvars_state == 1) {
-                            wx_len = sprintf(wx_buf, "$end\n");
+                            wx_len = snprintf(wx_buf, 6, "$end\n");
                             fstWritex(xc, wx_buf, wx_len);
                             dumpvars_state = 2;
                         }
-                        wx_len = sprintf(wx_buf, "#%" PRIu64 "\n", beg_tim);
+                        wx_len = snprintf(wx_buf, 20, "#%" PRIu64 "\n", beg_tim);
                         fstWritex(xc, wx_buf, wx_len);
                         if (!dumpvars_state) {
-                            wx_len = sprintf(wx_buf, "$dumpvars\n");
+                            wx_len = snprintf(wx_buf, 11, "$dumpvars\n");
                             fstWritex(xc, wx_buf, wx_len);
                             dumpvars_state = 1;
                         }
                     }
                     if ((xc->num_blackouts) && (cur_blackout != xc->num_blackouts)) {
                         if (beg_tim == xc->blackout_times[cur_blackout]) {
-                            wx_len = sprintf(wx_buf, "$dump%s $end\n",
+                            wx_len = snprintf(wx_buf, 16, "$dump%s $end\n",
                                              (xc->blackout_activity[cur_blackout++]) ? "on" : "off");
                             fstWritex(xc, wx_buf, wx_len);
                         }
@@ -4914,7 +4914,7 @@ int fstReaderIterBlocks2(void *ctx,
                                                 clone_d[j] = srcdata[7 - j];
                                             }
                                         }
-                                        sprintf((char *)xc->temp_signal_value_buf, "%.16g", d);
+                                        snprintf((char *)xc->temp_signal_value_buf, 32, "%.16g", d);
                                         value_change_callback(user_callback_data_pointer, beg_tim, idx + 1,
                                                               xc->temp_signal_value_buf);
                                     }
@@ -4936,7 +4936,7 @@ int fstReaderIterBlocks2(void *ctx,
                                         }
 
                                         fstVcdID(vcdid_buf, idx + 1);
-                                        wx_len = sprintf(wx_buf, "r%.16g %s\n", d, vcdid_buf);
+                                        wx_len = snprintf(wx_buf, sizeof(wx_buf), "r%.16g %s\n", d, vcdid_buf);
                                         fstWritex(xc, wx_buf, wx_len);
                                     }
                                 }
@@ -5179,21 +5179,21 @@ int fstReaderIterBlocks2(void *ctx,
                     }
 
                     if (dumpvars_state == 1) {
-                        wx_len = sprintf(wx_buf, "$end\n");
+                        wx_len = snprintf(wx_buf, 6, "$end\n");
                         fstWritex(xc, wx_buf, wx_len);
                         dumpvars_state = 2;
                     }
-                    wx_len = sprintf(wx_buf, "#%" PRIu64 "\n", time_table[i]);
+                    wx_len = snprintf(wx_buf, 20, "#%" PRIu64 "\n", time_table[i]);
                     fstWritex(xc, wx_buf, wx_len);
                     if (!dumpvars_state) {
-                        wx_len = sprintf(wx_buf, "$dumpvars\n");
+                        wx_len = snprintf(wx_buf, 11, "$dumpvars\n");
                         fstWritex(xc, wx_buf, wx_len);
                         dumpvars_state = 1;
                     }
 
                     if ((xc->num_blackouts) && (cur_blackout != xc->num_blackouts)) {
                         if (time_table[i] == xc->blackout_times[cur_blackout]) {
-                            wx_len = sprintf(wx_buf, "$dump%s $end\n",
+                            wx_len = snprintf(wx_buf, 16, "$dump%s $end\n",
                                              (xc->blackout_activity[cur_blackout++]) ? "on" : "off");
                             fstWritex(xc, wx_buf, wx_len);
                         }
@@ -5407,7 +5407,7 @@ int fstReaderIterBlocks2(void *ctx,
                                         clone_d[j] = srcdata[7 - j];
                                     }
                                 }
-                                sprintf((char *)xc->temp_signal_value_buf, "%.16g", d);
+                                snprintf((char *)xc->temp_signal_value_buf, 32, "%.16g", d);
                                 value_change_callback(user_callback_data_pointer, time_table[i], idx + 1,
                                                       xc->temp_signal_value_buf);
                             }
@@ -5427,7 +5427,7 @@ int fstReaderIterBlocks2(void *ctx,
                                     }
                                 }
 
-                                wx_len = sprintf(wx_buf, "r%.16g", d);
+                                wx_len = snprintf(wx_buf, sizeof(wx_buf), "r%.16g", d);
                                 fstWritex(xc, wx_buf, wx_len);
                             }
                         }
@@ -5523,7 +5523,7 @@ static char *fstExtractRvatDataFromFrame(struct fstReaderContext *xc, fstHandle
                 }
             }
 
-            sprintf((char *)buf, "%.16g", d);
+            snprintf((char *)buf, 32, "%.16g", d);
         }
     }
 
@@ -6045,7 +6045,7 @@ char *fstReaderGetValueFromHandleAtTime(void *ctx, uint64_t tim, fstHandle facid
                         }
                     }
 
-                    sprintf(buf, "r%.16g", d);
+                    snprintf(buf, sizeof(buf), "r%.16g", d);
                     return (buf);
                 }
             } else {
diff --git a/libs/minisat/System.cc b/libs/minisat/System.cc
index 807e46c694b..658f5d28ce1 100644
--- a/libs/minisat/System.cc
+++ b/libs/minisat/System.cc
@@ -43,7 +43,7 @@ static inline int memReadStat(int field)
     pid_t pid = getpid();
     int   value;
 
-    sprintf(name, "/proc/%d/statm", pid);
+    snprintf(name, 256, "/proc/%d/statm", pid);
     FILE* in = fopen(name, "rb");
     if (in == NULL) return 0;
 
@@ -60,7 +60,7 @@ static inline int memReadPeak(void)
     char  name[256];
     pid_t pid = getpid();
 
-    sprintf(name, "/proc/%d/status", pid);
+    snprintf(name, 256, "/proc/%d/status", pid);
     FILE* in = fopen(name, "rb");
     if (in == NULL) return 0;
 

From d34833d177edce8b528190e3e1f4c17bba8faa50 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 16 Aug 2024 04:30:37 +1200
Subject: [PATCH 341/499] Better snprintf size handling

---
 libs/fst/fstapi.cc | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/libs/fst/fstapi.cc b/libs/fst/fstapi.cc
index b0f4a83c942..bd70d725005 100644
--- a/libs/fst/fstapi.cc
+++ b/libs/fst/fstapi.cc
@@ -1907,7 +1907,8 @@ void fstWriterClose(void *ctx)
             int zfd;
             int fourpack_duo = 0;
 #ifndef __MINGW32__
-            char *fnam = (char *)malloc(strlen(xc->filename) + 5 + 1);
+            auto fnam_size = strlen(xc->filename) + 5 + 1;
+            char *fnam = (char *)malloc(fnam_size);
 #endif
 
             fixup_offs = ftello(xc->handle);
@@ -1991,7 +1992,7 @@ void fstWriterClose(void *ctx)
             fflush(xc->handle);
 
 #ifndef __MINGW32__
-            snprintf(fnam, sizeof(fnam), "%s.hier", xc->filename);
+            snprintf(fnam, fnam_size, "%s.hier", xc->filename);
             unlink(fnam);
             free(fnam);
 #endif
@@ -3579,7 +3580,8 @@ static int fstReaderRecreateHierFile(struct fstReaderContext *xc)
 
     if (!xc->fh) {
         fst_off_t offs_cache = ftello(xc->f);
-        char *fnam = (char *)malloc(strlen(xc->filename) + 6 + 16 + 32 + 1);
+	auto fnam_size = strlen(xc->filename) + 6 + 16 + 32 + 1;
+        char *fnam = (char *)malloc(fnam_size);
         unsigned char *mem = (unsigned char *)malloc(FST_GZIO_LEN);
         fst_off_t hl, uclen;
         fst_off_t clen = 0;
@@ -3594,7 +3596,7 @@ static int fstReaderRecreateHierFile(struct fstReaderContext *xc)
             htyp = xc->contains_hier_section_lz4duo ? FST_BL_HIER_LZ4DUO : FST_BL_HIER_LZ4;
         }
 
-        snprintf(fnam, sizeof(fnam), "%s.hier_%d_%p", xc->filename, getpid(), (void *)xc);
+        snprintf(fnam, fnam_size, "%s.hier_%d_%p", xc->filename, getpid(), (void *)xc);
         fstReaderFseeko(xc, xc->f, xc->hier_pos, SEEK_SET);
         uclen = fstReaderUint64(xc->f);
 #ifndef __MINGW32__
@@ -4239,9 +4241,10 @@ int fstReaderInit(struct fstReaderContext *xc)
         if (!seclen)
             return (0); /* not finished compressing, this is a failed read */
 
-        hf = (char *)calloc(1, flen + 16 + 32 + 1);
+	size_t hf_size = flen + 16 + 32 + 1;
+        hf = (char *)calloc(1, hf_size);
 
-        snprintf(hf, sizeof(hf), "%s.upk_%d_%p", xc->filename, getpid(), (void *)xc);
+        snprintf(hf, hf_size, "%s.upk_%d_%p", xc->filename, getpid(), (void *)xc);
         fcomp = fopen(hf, "w+b");
         if (!fcomp) {
             fcomp = tmpfile_open(&xc->f_nam);
@@ -6045,7 +6048,7 @@ char *fstReaderGetValueFromHandleAtTime(void *ctx, uint64_t tim, fstHandle facid
                         }
                     }
 
-                    snprintf(buf, sizeof(buf), "r%.16g", d);
+                    snprintf(buf, 32, "r%.16g", d);
                     return (buf);
                 }
             } else {

From eb02ab07da3fca60def0dd90d4f73d401c97c33f Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 16 Aug 2024 04:30:37 +1200
Subject: [PATCH 342/499] minisat: Use reallocarray

Avoid gcc warning about non-trivial copying.
---
 libs/minisat/Vec.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libs/minisat/Vec.h b/libs/minisat/Vec.h
index 6e398801f58..9e6d21174f9 100644
--- a/libs/minisat/Vec.h
+++ b/libs/minisat/Vec.h
@@ -100,7 +100,7 @@ void vec<T,_Size>::capacity(Size min_cap) {
     Size add = max((min_cap - cap + 1) & ~1, ((cap >> 1) + 2) & ~1);   // NOTE: grow by approximately 3/2
     const Size size_max = std::numeric_limits<Size>::max();
     if ( ((size_max <= std::numeric_limits<int>::max()) && (add > size_max - cap))
-    ||   (((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) && errno == ENOMEM) )
+    ||   (((data = (T*)::reallocarray(data, (cap += add), sizeof(T))) == NULL) && errno == ENOMEM) )
         throw OutOfMemoryException();
  }
 

From 55307a5452d2138d58b7f56a415a27733e8ca6be Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 16 Aug 2024 04:30:37 +1200
Subject: [PATCH 343/499] minisat: Check for gcc

---
 libs/minisat/Vec.h | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/libs/minisat/Vec.h b/libs/minisat/Vec.h
index 9e6d21174f9..c5c913be989 100644
--- a/libs/minisat/Vec.h
+++ b/libs/minisat/Vec.h
@@ -100,7 +100,13 @@ void vec<T,_Size>::capacity(Size min_cap) {
     Size add = max((min_cap - cap + 1) & ~1, ((cap >> 1) + 2) & ~1);   // NOTE: grow by approximately 3/2
     const Size size_max = std::numeric_limits<Size>::max();
     if ( ((size_max <= std::numeric_limits<int>::max()) && (add > size_max - cap))
-    ||   (((data = (T*)::reallocarray(data, (cap += add), sizeof(T))) == NULL) && errno == ENOMEM) )
+    ||   (
+#ifdef _DEFAULT_SOURCE
+            ((data = (T*)::reallocarray(data, (cap += add), sizeof(T))) == NULL)
+#else
+            ((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) 
+#endif
+	&& errno == ENOMEM) )
         throw OutOfMemoryException();
  }
 

From 3b63ab07ae289397573d32f2851cd78aedeeea94 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 16 Aug 2024 10:43:51 +1200
Subject: [PATCH 344/499] docs: Build RTD artifacts directly

Use rtds-action instead of yosys-cmd-ref repo.
Add rtds_action to docs configuration.
Add `.readthedocs.yaml`.
Update `DOCS_USAGE_` make target to be able to use pre-generated executables without forcing a remake.
---
 .github/workflows/test-verific.yml | 71 ++++++++++++++++++++----------
 .readthedocs.yaml                  | 19 ++++++++
 Makefile                           |  8 ++--
 docs/source/conf.py                |  8 +++-
 docs/source/requirements.txt       |  1 +
 5 files changed, 78 insertions(+), 29 deletions(-)
 create mode 100644 .readthedocs.yaml

diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml
index e08f7bd2e0f..d896340096b 100644
--- a/.github/workflows/test-verific.yml
+++ b/.github/workflows/test-verific.yml
@@ -47,30 +47,6 @@ jobs:
         run: |
           make install DESTDIR=${GITHUB_WORKSPACE}/.local PREFIX=
 
-      - name: Checkout Documentation
-        if: ${{ github.ref == 'refs/heads/main' }}
-        uses: actions/checkout@v4
-        with:
-          path: 'yosys-cmd-ref'
-          repository: 'YosysHQ-Docs/yosys-cmd-ref'
-          fetch-depth: 0
-          token: ${{ secrets.CI_DOCS_UPDATE_PAT }}
-          persist-credentials: true
-
-      - name: Update documentation
-        if: ${{ github.ref == 'refs/heads/main' }}
-        run: |
-          make docs
-          rm -rf docs/build
-          cd yosys-cmd-ref
-          rm -rf *
-          git checkout README.md
-          cp -R ../docs/* .
-          rm -rf util/__pycache__
-          git add -A .
-          git diff-index --quiet HEAD || git commit -m "Update"
-          git push
-
       - name: Checkout SBY
         uses: actions/checkout@v4
         with:
@@ -94,3 +70,50 @@ jobs:
         if: ${{ github.ref == 'refs/heads/main' }}
         run: |
           make -C sby run_ci
+
+  prepare-docs:
+    name: Generate docs artifact
+    needs: pre_job, test-verific
+    if: needs.pre_job.outputs.should_skip != 'true'
+    runs-on: [self-hosted, linux, x64]
+    steps:
+      - name: Checkout Yosys
+        uses: actions/checkout@v4
+        with:
+          persist-credentials: false
+          submodules: true
+      - name: Runtime environment
+        run: |
+          echo "procs=$(nproc)" >> $GITHUB_ENV
+
+      - name: Build Yosys
+        run: |
+          make config-clang
+          echo "ENABLE_VERIFIC := 1" >> Makefile.conf
+          echo "ENABLE_VERIFIC_EDIF := 1" >> Makefile.conf
+          echo "ENABLE_VERIFIC_LIBERTY := 1" >> Makefile.conf
+          echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1" >> Makefile.conf
+          echo "ENABLE_CCACHE := 1" >> Makefile.conf
+          make -j${{ env.procs }} ENABLE_LTO=1
+
+      - name: Prepare docs
+        shell: bash
+        run:
+          make docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage docs/reqs TARGETS= EXTRA_TARGETS=
+
+      - name: Upload artifact
+        uses: actions/upload-artifact@v4
+        with:
+          name: cmd-ref-${{ github.sha }}
+          path: |
+            docs/source/cmd
+            docs/source/generated
+            docs/source/_images
+            docs/source/code_examples
+
+      - name: Trigger RTDs build
+        uses: dfm/rtds-action@v1.1.0
+        with:
+          webhook_url: ${{ secrets.RTDS_WEBHOOK_URL }}
+          webhook_token: ${{ secrets.RTDS_WEBHOOK_TOKEN }}
+          commit_ref: ${{ github.ref }}
diff --git a/.readthedocs.yaml b/.readthedocs.yaml
new file mode 100644
index 00000000000..cb700dc1c72
--- /dev/null
+++ b/.readthedocs.yaml
@@ -0,0 +1,19 @@
+# .readthedocs.yaml
+# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details
+
+version: 2
+
+build:
+    os: ubuntu-22.04
+    tools:
+        python: '3.12'
+
+formats:
+  - pdf
+
+sphinx:
+  configuration: docs/source/conf.py
+
+python:
+  install:
+    - requirements: docs/source/requirements.txt
diff --git a/Makefile b/Makefile
index a2803ed5934..44c77eeaad1 100644
--- a/Makefile
+++ b/Makefile
@@ -984,8 +984,8 @@ docs/guidelines docs/source/generated:
 
 # some commands return an error and print the usage text to stderr
 define DOC_USAGE_STDERR
-docs/source/generated/$(1): $(PROGRAM_PREFIX)$(1) docs/source/generated
-	-$(Q) ./$$< --help 2> $$@
+docs/source/generated/$(1): $(TARGETS) docs/source/generated
+	-$(Q) ./$(PROGRAM_PREFIX)$(1) --help 2> $$@
 endef
 DOCS_USAGE_STDERR := yosys-config yosys-filterlib
 
@@ -998,8 +998,8 @@ $(foreach usage,$(DOCS_USAGE_STDERR),$(eval $(call DOC_USAGE_STDERR,$(usage))))
 
 # others print to stdout
 define DOC_USAGE_STDOUT
-docs/source/generated/$(1): $(PROGRAM_PREFIX)$(1) docs/source/generated
-	$(Q) ./$$< --help > $$@
+docs/source/generated/$(1): $(TARGETS) docs/source/generated
+	$(Q) ./$(PROGRAM_PREFIX)$(1) --help > $$@
 endef
 DOCS_USAGE_STDOUT := yosys yosys-smtbmc yosys-witness
 $(foreach usage,$(DOCS_USAGE_STDOUT),$(eval $(call DOC_USAGE_STDOUT,$(usage))))
diff --git a/docs/source/conf.py b/docs/source/conf.py
index 2fdd43a31a0..23efe2b43c2 100644
--- a/docs/source/conf.py
+++ b/docs/source/conf.py
@@ -41,7 +41,13 @@
 pygments_style = 'colorful'
 highlight_language = 'none'
 
-extensions = ['sphinx.ext.autosectionlabel', 'sphinxcontrib.bibtex']
+extensions = ['sphinx.ext.autosectionlabel', 'sphinxcontrib.bibtex', 'rtds_action']
+
+# rtds_action
+rtds_action_github_repo = "YosysHQ/yosys"
+rtds_action_path = "."
+rtds_action_artifact_prefix = "cmd-ref-"
+rtds_action_github_token = os.environ["GITHUB_TOKEN"]
 
 # Ensure that autosectionlabel will produce unique names
 autosectionlabel_prefix_document = True
diff --git a/docs/source/requirements.txt b/docs/source/requirements.txt
index 74c8dd090cb..dbba558321e 100644
--- a/docs/source/requirements.txt
+++ b/docs/source/requirements.txt
@@ -1,2 +1,3 @@
 furo
 sphinxcontrib-bibtex
+rtds-action

From 7bd3c7b968432896771d2294103bd7a8b88487d7 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 16 Aug 2024 10:43:51 +1200
Subject: [PATCH 345/499] Fix test-verific.yml

---
 .github/workflows/test-verific.yml | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml
index d896340096b..b76718c2165 100644
--- a/.github/workflows/test-verific.yml
+++ b/.github/workflows/test-verific.yml
@@ -3,7 +3,7 @@ name: Build and run tests with Verific (Linux)
 on: [push, pull_request]
 
 jobs:
-  pre_job:
+  pre-job:
     runs-on: ubuntu-latest
     outputs:
       should_skip: ${{ steps.skip_check.outputs.should_skip }}
@@ -20,8 +20,8 @@ jobs:
           skip_after_successful_duplicate: 'false'
 
   test-verific:
-    needs: pre_job
-    if: needs.pre_job.outputs.should_skip != 'true'
+    needs: pre-job
+    if: needs.pre-job.outputs.should_skip != 'true'
     runs-on: [self-hosted, linux, x64]
     steps:
       - name: Checkout Yosys
@@ -73,8 +73,8 @@ jobs:
 
   prepare-docs:
     name: Generate docs artifact
-    needs: pre_job, test-verific
-    if: needs.pre_job.outputs.should_skip != 'true'
+    needs: [pre-job, test-verific]
+    if: needs.pre-job.outputs.should_skip != 'true'
     runs-on: [self-hosted, linux, x64]
     steps:
       - name: Checkout Yosys

From e9f909aa25dda4491ac25400dd12732fcc4626b8 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Sat, 17 Aug 2024 10:01:25 +1200
Subject: [PATCH 346/499] minisat: Record changes in patch

---
 libs/minisat/00_PATCH_warnings.patch | 37 ++++++++++++++++++++++++++++
 libs/minisat/00_UPDATE.sh            |  1 +
 2 files changed, 38 insertions(+)
 create mode 100644 libs/minisat/00_PATCH_warnings.patch

diff --git a/libs/minisat/00_PATCH_warnings.patch b/libs/minisat/00_PATCH_warnings.patch
new file mode 100644
index 00000000000..e543b104681
--- /dev/null
+++ b/libs/minisat/00_PATCH_warnings.patch
@@ -0,0 +1,37 @@
+--- System.cc
++++ System.cc
+@@ -43,7 +43,7 @@ static inline int memReadStat(int field)
+     pid_t pid = getpid();
+     int   value;
+ 
+-    sprintf(name, "/proc/%d/statm", pid);
++    snprintf(name, 256, "/proc/%d/statm", pid);
+     FILE* in = fopen(name, "rb");
+     if (in == NULL) return 0;
+ 
+@@ -60,7 +60,7 @@ static inline int memReadPeak(void)
+     char  name[256];
+     pid_t pid = getpid();
+ 
+-    sprintf(name, "/proc/%d/status", pid);
++    snprintf(name, 256, "/proc/%d/status", pid);
+     FILE* in = fopen(name, "rb");
+     if (in == NULL) return 0;
+ 
+--- Vec.h
++++ Vec.h
+@@ -100,7 +100,13 @@ void vec<T,_Size>::capacity(Size min_cap) {
+     Size add = max((min_cap - cap + 1) & ~1, ((cap >> 1) + 2) & ~1);   // NOTE: grow by approximately 3/2
+     const Size size_max = std::numeric_limits<Size>::max();
+     if ( ((size_max <= std::numeric_limits<int>::max()) && (add > size_max - cap))
+-    ||   (((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) && errno == ENOMEM) )
++    ||   (
++#ifdef _DEFAULT_SOURCE
++            ((data = (T*)::reallocarray(data, (cap += add), sizeof(T))) == NULL)
++#else
++            ((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) 
++#endif
++	&& errno == ENOMEM) )
+         throw OutOfMemoryException();
+  }
+ 
diff --git a/libs/minisat/00_UPDATE.sh b/libs/minisat/00_UPDATE.sh
index 51107e4506a..6f3eadfe720 100755
--- a/libs/minisat/00_UPDATE.sh
+++ b/libs/minisat/00_UPDATE.sh
@@ -17,3 +17,4 @@ patch -p0 < 00_PATCH_remove_zlib.patch
 patch -p0 < 00_PATCH_no_fpu_control.patch
 patch -p0 < 00_PATCH_typofixes.patch
 patch -p0 < 00_PATCH_wasm.patch
+patch -p0 < 00_PATCH_warnings.patch

From 3dd32d741ac74914e4839de5b36dc58979cca8e3 Mon Sep 17 00:00:00 2001
From: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com>
Date: Mon, 5 Aug 2024 11:20:05 +1200
Subject: [PATCH 347/499] Stop unconditionally building abc

_What are the reasons/motivation for this change?_
abc builds unconditional because `check-git-abc` is a phony prerequisite and therefore always runs, and since it always runs it will always trigger abc to rebuild.

_Explain how this is achieved._
Convert `check-git-abc` to an order-only prerequisite.  It still runs as before, but no longer triggers yosys-abc to rebuild when it does.

_If applicable, please suggest to reviewers how they can test the change._
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index a2803ed5934..5594a605a1b 100644
--- a/Makefile
+++ b/Makefile
@@ -807,7 +807,7 @@ check-git-abc:
 		exit 1; \
 	fi
 
-abc/abc$(EXE) abc/libabc.a: check-git-abc
+abc/abc$(EXE) abc/libabc.a: | check-git-abc
 	$(P)
 	$(Q) mkdir -p abc && $(MAKE) -C $(PROGRAM_PREFIX)abc -f "$(realpath $(YOSYS_SRC)/abc/Makefile)" ABCSRC="$(realpath $(YOSYS_SRC)/abc/)" $(S) $(ABCMKARGS) $(if $(filter %.a,$@),PROG="abc",PROG="abc$(EXE)") MSG_PREFIX="$(eval P_OFFSET = 5)$(call P_SHOW)$(eval P_OFFSET = 10) ABC: " $(if $(filter %.a,$@),libabc.a)
 

From 5fb3c0b1d982eebc3b996c4fa4e42ed98030440d Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Sat, 17 Aug 2024 00:17:44 +0000
Subject: [PATCH 348/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 5594a605a1b..556d1726e5b 100644
--- a/Makefile
+++ b/Makefile
@@ -153,7 +153,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.44+16
+YOSYS_VER := 0.44+20
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From d80d4dc51c2deebbd26b9eab6af00298e979c957 Mon Sep 17 00:00:00 2001
From: Saish Karole <72208314+NachtSpyder04@users.noreply.github.com>
Date: Sat, 17 Aug 2024 15:47:00 +0530
Subject: [PATCH 349/499] [Docs]:Add new cell type help messages (#1)

* add shift operators description

* update shift operations' descriptions, add desciptions for add, sub, logic_*, tribuf, mux, demux, concat, pow and comparison operators
---
 techlibs/common/simlib.v | 141 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 141 insertions(+)

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 7dc03da6d2d..de7726582a3 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -371,6 +371,12 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $shl (A, B, Y)
+//-
+//- A logical shift-left operation. This corresponds to the Verilog '<<' operator.
+//-
 module \$shl (A, B, Y);
 
 parameter A_SIGNED = 0;
@@ -395,6 +401,12 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $shr (A, B, Y)
+//-
+//- A logical shift-right operation. This corresponds to the Verilog '>>' operator.
+//-
 module \$shr (A, B, Y);
 
 parameter A_SIGNED = 0;
@@ -419,6 +431,12 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $sshl (A, B, Y)
+//-
+//- An arithmatic shift-left operation. This corresponds to the Verilog '<<<' operator.
+//-
 module \$sshl (A, B, Y);
 
 parameter A_SIGNED = 0;
@@ -443,6 +461,12 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $sshr (A, B, Y)
+//-
+//- An arithmatic shift-right operation. This corresponds to the Verilog '>>>' operator.
+//-
 module \$sshr (A, B, Y);
 
 parameter A_SIGNED = 0;
@@ -639,6 +663,12 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $lt (A, B, Y)
+//-
+//- A less-than comparison between inputs 'A' and 'B'. This corresponds to the Verilog '<' operator.
+//-
 module \$lt (A, B, Y);
 
 parameter A_SIGNED = 0;
@@ -663,6 +693,12 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $le (A, B, Y)
+//-
+//- A less-than-or-equal-to comparison between inputs 'A' and 'B'. This corresponds to the Verilog '<=' operator.
+//-
 module \$le (A, B, Y);
 
 parameter A_SIGNED = 0;
@@ -687,6 +723,12 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $eq (A, B, Y)
+//-
+//- An equality comparison between inputs 'A' and 'B'. This corresponds to the Verilog '==' operator.
+//-
 module \$eq (A, B, Y);
 
 parameter A_SIGNED = 0;
@@ -711,6 +753,12 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $ne (A, B, Y)
+//-
+//- An inequality comparison between inputs 'A' and 'B'. This corresponds to the Verilog '!=' operator.
+//-
 module \$ne (A, B, Y);
 
 parameter A_SIGNED = 0;
@@ -735,6 +783,13 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $eqx (A, B, Y)
+//-
+//- An exact equality comparison between inputs 'A' and 'B'. This corresponds to the Verilog '===' operator.
+//- Unlike equality comparison that can give 'x' as output, an exact equality comparison will strictly give '0' or '1' as output.
+//-
 module \$eqx (A, B, Y);
 
 parameter A_SIGNED = 0;
@@ -759,6 +814,13 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $nex (A, B, Y)
+//-
+//- An exact inequality comparison between inputs 'A' and 'B'. This corresponds to the Verilog '!==' operator.
+//- Unlike inequality comparison that can give 'x' as output, an exact inequality comparison will strictly give '0' or '1' as output.
+//-
 module \$nex (A, B, Y);
 
 parameter A_SIGNED = 0;
@@ -783,6 +845,12 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $ge (A, B, Y)
+//-
+//- A greater-than-or-equal-to comparison between inputs 'A' and 'B'. This corresponds to the Verilog '>=' operator.
+//-
 module \$ge (A, B, Y);
 
 parameter A_SIGNED = 0;
@@ -807,6 +875,12 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $gt (A, B, Y)
+//-
+//- A greater-than comparison between inputs 'A' and 'B'. This corresponds to the Verilog '>' operator.
+//-
 module \$gt (A, B, Y);
 
 parameter A_SIGNED = 0;
@@ -831,6 +905,12 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $add (A, B, Y)
+//-
+//-  Addition of inputs 'A' and 'B'. This corresponds to the Verilog '+' operator.
+//-
 module \$add (A, B, Y);
 
 parameter A_SIGNED = 0;
@@ -855,6 +935,12 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $sub (A, B, Y)
+//-
+//-  Subtraction between inputs 'A' and 'B'. This corresponds to the Verilog '-' operator.
+//-
 module \$sub (A, B, Y);
 
 parameter A_SIGNED = 0;
@@ -879,6 +965,12 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $mul (A, B, Y)
+//-
+//- Multiplication of inputs 'A' and 'B'. This corresponds to the Verilog '*' operator.
+//-
 module \$mul (A, B, Y);
 
 parameter A_SIGNED = 0;
@@ -1191,6 +1283,13 @@ endgenerate
 endmodule
 
 // --------------------------------------------------------
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $pow (A, B, Y)
+//-
+//-  Exponentiation of inputs (Y = A ** B). This corresponds to the Verilog '**' operator.
+//-
 `ifndef SIMLIB_NOPOW
 
 module \$pow (A, B, Y);
@@ -1222,6 +1321,12 @@ endmodule
 `endif
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $logic_not (A, Y)
+//-
+//- A logical inverter. This corresponds to the Verilog unary prefix '!' operator.
+//-
 module \$logic_not (A, Y);
 
 parameter A_SIGNED = 0;
@@ -1243,6 +1348,12 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $logic_and (A, B, Y)
+//-
+//- A logical AND. This corresponds to the Verilog '&&' operator.
+//-
 module \$logic_and (A, B, Y);
 
 parameter A_SIGNED = 0;
@@ -1267,6 +1378,12 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $logic_or (A, B, Y)
+//-
+//- A logical OR. This corresponds to the Verilog '||' operator.
+//-
 module \$logic_or (A, B, Y);
 
 parameter A_SIGNED = 0;
@@ -1306,6 +1423,12 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $concat (A, B, Y)
+//-
+//- Concatenation of inputs into a single output ( Y = {B, A} ).
+//-
 module \$concat (A, B, Y);
 
 parameter A_WIDTH = 0;
@@ -1321,6 +1444,12 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $mux (A, B, S, Y)
+//-
+//- Multiplexer i.e selecting inputs based on select signal.
+//-
 module \$mux (A, B, S, Y);
 
 parameter WIDTH = 0;
@@ -1396,6 +1525,12 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $demux (A, S, Y)
+//-
+//- Demultiplexer i.e routing single input to several outputs based on select signal.
+//-
 module \$demux (A, S, Y);
 
 parameter WIDTH = 1;
@@ -1460,6 +1595,12 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $tribuf (A, EN, Y)
+//-
+//- A tri-state buffer. This buffer conditionally passes the input to the output based on the enable signal.
+//-
 module \$tribuf (A, EN, Y);
 
 parameter WIDTH = 0;

From 34aabd56cca445996d332343b06a29fadd78d534 Mon Sep 17 00:00:00 2001
From: Saish Karole <72208314+NachtSpyder04@users.noreply.github.com>
Date: Sun, 18 Aug 2024 20:12:53 +0530
Subject: [PATCH 350/499] Apply suggestions from code review
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Co-authored-by: Martin Povišer <povik@cutebit.org>
---
 techlibs/common/simlib.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index de7726582a3..e035e92c4b8 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1288,7 +1288,7 @@ endmodule
 //-
 //-     $pow (A, B, Y)
 //-
-//-  Exponentiation of inputs (Y = A ** B). This corresponds to the Verilog '**' operator.
+//-  Exponentiation of an input (Y = A ** B). This corresponds to the Verilog '**' operator.
 //-
 `ifndef SIMLIB_NOPOW
 
@@ -1448,7 +1448,7 @@ endmodule
 //-
 //-     $mux (A, B, S, Y)
 //-
-//- Multiplexer i.e selecting inputs based on select signal.
+//- Multiplexer i.e selecting between two inputs based on select signal.
 //-
 module \$mux (A, B, S, Y);
 
@@ -1529,7 +1529,7 @@ endmodule
 //-
 //-     $demux (A, S, Y)
 //-
-//- Demultiplexer i.e routing single input to several outputs based on select signal.
+//- Demultiplexer i.e routing single input to several outputs based on select signal. Unselected outputs are driven to zero.
 //-
 module \$demux (A, S, Y);
 
@@ -1599,7 +1599,7 @@ endmodule
 //-
 //-     $tribuf (A, EN, Y)
 //-
-//- A tri-state buffer. This buffer conditionally passes the input to the output based on the enable signal.
+//- A tri-state buffer. This buffer conditionally drives the output with the value of the input based on the enable signal.
 //-
 module \$tribuf (A, EN, Y);
 

From aa60255e0e3750207bfcab8b3545f81e1cefa202 Mon Sep 17 00:00:00 2001
From: NachtSpyder04 <sskarole.1504@gmail.com>
Date: Sun, 18 Aug 2024 20:27:35 +0530
Subject: [PATCH 351/499] update help messages that went beyond line length
 limit

---
 techlibs/common/simlib.v | 52 +++++++++++++++++++++++++++-------------
 1 file changed, 35 insertions(+), 17 deletions(-)

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index e035e92c4b8..5bbad34f677 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -435,7 +435,8 @@ endmodule
 //-
 //-     $sshl (A, B, Y)
 //-
-//- An arithmatic shift-left operation. This corresponds to the Verilog '<<<' operator.
+//- An arithmatic shift-left operation. 
+//- This corresponds to the Verilog '<<<' operator.
 //-
 module \$sshl (A, B, Y);
 
@@ -465,7 +466,8 @@ endmodule
 //-
 //-     $sshr (A, B, Y)
 //-
-//- An arithmatic shift-right operation. This corresponds to the Verilog '>>>' operator.
+//- An arithmatic shift-right operation.
+//- This corresponds to the Verilog '>>>' operator.
 //-
 module \$sshr (A, B, Y);
 
@@ -667,7 +669,8 @@ endmodule
 //-
 //-     $lt (A, B, Y)
 //-
-//- A less-than comparison between inputs 'A' and 'B'. This corresponds to the Verilog '<' operator.
+//- A less-than comparison between inputs 'A' and 'B'. 
+//- This corresponds to the Verilog '<' operator.
 //-
 module \$lt (A, B, Y);
 
@@ -697,7 +700,8 @@ endmodule
 //-
 //-     $le (A, B, Y)
 //-
-//- A less-than-or-equal-to comparison between inputs 'A' and 'B'. This corresponds to the Verilog '<=' operator.
+//- A less-than-or-equal-to comparison between inputs 'A' and 'B'. 
+//- This corresponds to the Verilog '<=' operator.
 //-
 module \$le (A, B, Y);
 
@@ -727,7 +731,8 @@ endmodule
 //-
 //-     $eq (A, B, Y)
 //-
-//- An equality comparison between inputs 'A' and 'B'. This corresponds to the Verilog '==' operator.
+//- An equality comparison between inputs 'A' and 'B'. 
+//- This corresponds to the Verilog '==' operator.
 //-
 module \$eq (A, B, Y);
 
@@ -757,7 +762,8 @@ endmodule
 //-
 //-     $ne (A, B, Y)
 //-
-//- An inequality comparison between inputs 'A' and 'B'. This corresponds to the Verilog '!=' operator.
+//- An inequality comparison between inputs 'A' and 'B'. 
+//- This corresponds to the Verilog '!=' operator.
 //-
 module \$ne (A, B, Y);
 
@@ -787,8 +793,10 @@ endmodule
 //-
 //-     $eqx (A, B, Y)
 //-
-//- An exact equality comparison between inputs 'A' and 'B'. This corresponds to the Verilog '===' operator.
-//- Unlike equality comparison that can give 'x' as output, an exact equality comparison will strictly give '0' or '1' as output.
+//- An exact equality comparison between inputs 'A' and 'B'. 
+//- This corresponds to the Verilog '===' operator.
+//- Unlike equality comparison that can give 'x' as output, 
+//- an exact equality comparison will strictly give '0' or '1' as output.
 //-
 module \$eqx (A, B, Y);
 
@@ -818,8 +826,10 @@ endmodule
 //-
 //-     $nex (A, B, Y)
 //-
-//- An exact inequality comparison between inputs 'A' and 'B'. This corresponds to the Verilog '!==' operator.
-//- Unlike inequality comparison that can give 'x' as output, an exact inequality comparison will strictly give '0' or '1' as output.
+//- An exact inequality comparison between inputs 'A' and 'B'. 
+//- This corresponds to the Verilog '!==' operator.
+//- Unlike inequality comparison that can give 'x' as output, 
+//- an exact inequality comparison will strictly give '0' or '1' as output.
 //-
 module \$nex (A, B, Y);
 
@@ -849,7 +859,8 @@ endmodule
 //-
 //-     $ge (A, B, Y)
 //-
-//- A greater-than-or-equal-to comparison between inputs 'A' and 'B'. This corresponds to the Verilog '>=' operator.
+//- A greater-than-or-equal-to comparison between inputs 'A' and 'B'.
+//- This corresponds to the Verilog '>=' operator.
 //-
 module \$ge (A, B, Y);
 
@@ -879,7 +890,8 @@ endmodule
 //-
 //-     $gt (A, B, Y)
 //-
-//- A greater-than comparison between inputs 'A' and 'B'. This corresponds to the Verilog '>' operator.
+//- A greater-than comparison between inputs 'A' and 'B'. 
+//- This corresponds to the Verilog '>' operator.
 //-
 module \$gt (A, B, Y);
 
@@ -939,7 +951,8 @@ endmodule
 //-
 //-     $sub (A, B, Y)
 //-
-//-  Subtraction between inputs 'A' and 'B'. This corresponds to the Verilog '-' operator.
+//- Subtraction between inputs 'A' and 'B'.
+//- This corresponds to the Verilog '-' operator.
 //-
 module \$sub (A, B, Y);
 
@@ -969,7 +982,8 @@ endmodule
 //-
 //-     $mul (A, B, Y)
 //-
-//- Multiplication of inputs 'A' and 'B'. This corresponds to the Verilog '*' operator.
+//- Multiplication of inputs 'A' and 'B'.
+//- This corresponds to the Verilog '*' operator.
 //-
 module \$mul (A, B, Y);
 
@@ -1288,7 +1302,8 @@ endmodule
 //-
 //-     $pow (A, B, Y)
 //-
-//-  Exponentiation of an input (Y = A ** B). This corresponds to the Verilog '**' operator.
+//- Exponentiation of an input (Y = A ** B). 
+//- This corresponds to the Verilog '**' operator.
 //-
 `ifndef SIMLIB_NOPOW
 
@@ -1529,7 +1544,8 @@ endmodule
 //-
 //-     $demux (A, S, Y)
 //-
-//- Demultiplexer i.e routing single input to several outputs based on select signal. Unselected outputs are driven to zero.
+//- Demultiplexer i.e routing single input to several outputs based on select signal.
+//- Unselected outputs are driven to zero.
 //-
 module \$demux (A, S, Y);
 
@@ -1599,7 +1615,9 @@ endmodule
 //-
 //-     $tribuf (A, EN, Y)
 //-
-//- A tri-state buffer. This buffer conditionally drives the output with the value of the input based on the enable signal.
+//- A tri-state buffer. 
+//- This buffer conditionally drives the output with the value of the input
+//- based on the enable signal.
 //-
 module \$tribuf (A, EN, Y);
 

From d1b767ea8b453fc234928b12653d1cc2c2d69a19 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?David=20Lanzend=C3=B6rfer?= <leviathan@libresilicon.com>
Date: Sat, 17 Aug 2024 01:15:37 +0100
Subject: [PATCH 352/499] Adding missing to Gowin tech files

Without OSER4_MEM, IDES4_MEM and DQS the synthesis of my Rocket Chip
design for my Sipeed Tang FPGA fails.
---
 techlibs/gowin/cells_sim.v | 52 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index 3edf6c8fcd9..96121a881e1 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -618,6 +618,21 @@ module OSER4(D3, D2, D1, D0, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);
 	parameter HWL = "false";
 endmodule
 
+module OSER4_MEM (Q0, Q1, D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET)  ;
+    parameter GSREN = "";
+    parameter LSREN = "";
+    parameter HWL = "";
+    parameter TCLK_SOURCE = "";
+    parameter TXCLK_POL = "";
+
+    input D0, D1, D2, D3;
+    input TX0, TX1;
+    input PCLK, FCLK, TCLK, RESET;
+    output  Q0,  Q1;
+
+    parameter ID = "";
+endmodule
+
 module OSER8(D7, D6, D5, D4, D3, D2, D1, D0, TX3, TX2, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);
 	output Q1;
 	output Q0;
@@ -729,6 +744,21 @@ RESET, CALIB, D);
 	parameter LSREN = "true";
 endmodule
 
+module IDES4_MEM (Q0, Q1, Q2, Q3, D, WADDR,
+RADDR, CALIB, PCLK, FCLK, ICLK, RESET)  ;
+parameter GSREN = "";
+parameter LSREN = "";
+
+input D, ICLK, FCLK, PCLK;
+input [2:0] WADDR;
+input [2:0] RADDR;
+input CALIB, RESET;
+
+output Q0,Q1,Q2,Q3;
+
+parameter ID = "";
+endmodule
+
 module IDES8(Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,
 RESET, CALIB, D);
 	input D;
@@ -842,6 +872,28 @@ module IDDRC(D, CLK, CLEAR, Q0, Q1);
 	parameter Q1_INIT = 1'b0;
 endmodule
 
+module DQS(DQSR90, DQSW0, DQSW270, RPOINT, WPOINT, RVALID, RBURST, RFLAG,
+WFLAG, DQSIN, DLLSTEP, WSTEP, READ, RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR,
+HOLD, RCLKSEL, PCLK, FCLK, RESET) ;
+    input DQSIN,PCLK,FCLK,RESET;
+    input [3:0] READ;
+    input [2:0] RCLKSEL;
+    input [7:0] DLLSTEP;
+    input [7:0] WSTEP;
+    input RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD;
+
+    output DQSR90, DQSW0, DQSW270;
+    output [2:0] RPOINT, WPOINT;
+    output RVALID,RBURST, RFLAG, WFLAG;
+
+    parameter FIFO_MODE_SEL = "";
+    parameter RD_PNTR = "";
+    parameter DQS_MODE = "";
+    parameter HWL = "";
+    parameter GSREN = "";
+    parameter ID = "";
+endmodule
+
 (* blackbox *)
 module ODDR(D0, D1, TX, CLK, Q0, Q1);
 	input D0;

From 8773cf77214824de688f7b155c10bc650393510b Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Mon, 19 Aug 2024 21:24:48 +1200
Subject: [PATCH 353/499] test-verific: Use fast runner

---
 .github/workflows/test-verific.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml
index b76718c2165..fc3c3dacfed 100644
--- a/.github/workflows/test-verific.yml
+++ b/.github/workflows/test-verific.yml
@@ -22,7 +22,7 @@ jobs:
   test-verific:
     needs: pre-job
     if: needs.pre-job.outputs.should_skip != 'true'
-    runs-on: [self-hosted, linux, x64]
+    runs-on: [self-hosted, linux, x64, fast]
     steps:
       - name: Checkout Yosys
         uses: actions/checkout@v4
@@ -75,7 +75,7 @@ jobs:
     name: Generate docs artifact
     needs: [pre-job, test-verific]
     if: needs.pre-job.outputs.should_skip != 'true'
-    runs-on: [self-hosted, linux, x64]
+    runs-on: [self-hosted, linux, x64, fast]
     steps:
       - name: Checkout Yosys
         uses: actions/checkout@v4

From 6df0c3d9ec9fa735535dc983e5f5e2559768bc40 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Mon, 19 Aug 2024 21:25:51 +1200
Subject: [PATCH 354/499] docs: Fix synth_flow generation

---
 docs/source/code_examples/synth_flow/Makefile | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/docs/source/code_examples/synth_flow/Makefile b/docs/source/code_examples/synth_flow/Makefile
index cc5a34b26b5..7db1c12f490 100644
--- a/docs/source/code_examples/synth_flow/Makefile
+++ b/docs/source/code_examples/synth_flow/Makefile
@@ -1,13 +1,13 @@
 
-TARGETS += proc_01 proc_02 proc_03
-TARGETS += memory_01 memory_02
-TARGETS += techmap_01
+DOT_TARGETS += proc_01 proc_02 proc_03
+DOT_TARGETS += memory_01 memory_02
+DOT_TARGETS += techmap_01
 
 PROGRAM_PREFIX :=
 
 YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
 
-DOTS = $(addsuffix .dot,$(TARGETS))
+DOTS = $(addsuffix .dot,$(DOT_TARGETS))
 
 .PHONY: all dots
 all: dots

From 4847caac49b91bdffb7605be56fa2bc456e746b2 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 19 Aug 2024 12:50:12 +0200
Subject: [PATCH 355/499] driver: print maximum memory usage on macOS as well

---
 kernel/driver.cc | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/kernel/driver.cc b/kernel/driver.cc
index 79dff7ddabe..1e4cd005266 100644
--- a/kernel/driver.cc
+++ b/kernel/driver.cc
@@ -721,13 +721,17 @@ int main(int argc, char **argv)
 			ru_buffer.ru_utime.tv_usec += ru_buffer_children.ru_utime.tv_usec;
 			ru_buffer.ru_stime.tv_sec += ru_buffer_children.ru_stime.tv_sec;
 			ru_buffer.ru_stime.tv_usec += ru_buffer_children.ru_stime.tv_usec;
-#if defined(__linux__) || defined(__FreeBSD__)
+#if defined(__linux__) || defined(__FreeBSD__) || defined(__APPLE__)
 			ru_buffer.ru_maxrss = std::max(ru_buffer.ru_maxrss, ru_buffer_children.ru_maxrss);
 #endif
 		}
 #if defined(__linux__) || defined(__FreeBSD__)
 		meminfo = stringf(", MEM: %.2f MB peak",
 				ru_buffer.ru_maxrss / 1024.0);
+#elif defined(__APPLE__)
+// https://stackoverflow.com/questions/59913657/strange-values-of-get-rusage-maxrss-on-macos-and-linux
+		meminfo = stringf(", MEM: %.2f MB peak",
+				ru_buffer.ru_maxrss / (1024.0 * 1024.0));
 #endif
 		log("End of script. Logfile hash: %s%sCPU: user %.2fs system %.2fs%s\n", hash.c_str(),
 				stats_divider.c_str(), ru_buffer.ru_utime.tv_sec + 1e-6 * ru_buffer.ru_utime.tv_usec,

From 7d779c64a35a07bb521c355f67fe48437d2b177a Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 20 Aug 2024 04:26:16 +1200
Subject: [PATCH 356/499] docs: Only trigger RTDs on main

---
 .github/workflows/test-verific.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml
index fc3c3dacfed..627a70d4794 100644
--- a/.github/workflows/test-verific.yml
+++ b/.github/workflows/test-verific.yml
@@ -112,6 +112,7 @@ jobs:
             docs/source/code_examples
 
       - name: Trigger RTDs build
+        if: ${{ github.ref == 'refs/heads/main' }}
         uses: dfm/rtds-action@v1.1.0
         with:
           webhook_url: ${{ secrets.RTDS_WEBHOOK_URL }}

From 4cddc19994f45d297088a6298dee1bcd16c7c132 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Tue, 20 Aug 2024 00:18:24 +0000
Subject: [PATCH 357/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index addbc41aa6e..d5e7e52356a 100644
--- a/Makefile
+++ b/Makefile
@@ -153,7 +153,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.44+20
+YOSYS_VER := 0.44+39
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 092214256791007a433999635ed39fb9fc5d00ad Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Mon, 15 Apr 2024 13:55:54 +0200
Subject: [PATCH 358/499] Add generic topological sort and SCC detection

This adds a generic non-recursive implementation of Tarjan's linear time
SCC algorithm that produces components in topological order. It can be
instantiated to work directly on any graph representation for which the
enumerate_nodes and enumerate_successors interface can be implemented.
---
 kernel/topo_scc.h | 328 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 328 insertions(+)
 create mode 100644 kernel/topo_scc.h

diff --git a/kernel/topo_scc.h b/kernel/topo_scc.h
new file mode 100644
index 00000000000..0ae0e696b47
--- /dev/null
+++ b/kernel/topo_scc.h
@@ -0,0 +1,328 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Jannis Harder <jix@yosyshq.com> <me@jix.one>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef TOPO_SCC_H
+#define TOPO_SCC_H
+
+#include "kernel/yosys.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+class SigCellGraph {
+public:
+    typedef int node_type;
+
+    struct successor_enumerator {
+        std::vector<std::pair<int, int>>::const_iterator current, end;
+        bool finished() const { return current == end; }
+        node_type next() {
+            log_assert(!finished());
+            node_type result = current->second;
+            ++current;
+            return result;
+        }
+    };
+
+    struct node_enumerator {
+        int current, end;
+        bool finished() const { return current == end; }
+        node_type next() {
+            log_assert(!finished());
+            node_type result = current;
+            ++current;
+            return result;
+        }
+    };
+
+private:
+    idict<RTLIL::Cell *> cell_ids;
+    idict<RTLIL::SigBit> sig_ids;
+    std::vector<std::pair<int, int>> edges;
+    std::vector<std::pair<int, int>> edge_ranges;
+    std::vector<int> indices_;
+    int offset;
+    bool computed = false;
+
+    void compute() {
+        offset = GetSize(sig_ids);
+        edge_ranges.clear();
+        indices_.clear();
+        indices_.resize(GetSize(sig_ids) + GetSize(cell_ids), -1);
+
+        std::sort(edges.begin(), edges.end());
+        auto last = std::unique(edges.begin(), edges.end());
+        edges.erase(last, edges.end());
+        auto edge = edges.begin();
+        auto edge_end = edges.end();
+        int range_begin = 0;
+        for (int node = -offset, node_end = GetSize(cell_ids); node != node_end; ++node) {
+            while (edge != edge_end && edge->first <= node)
+                ++edge;
+            int range_end = edge - edges.begin();
+            edge_ranges.emplace_back(std::make_pair(range_begin, range_end));
+            range_begin = range_end;
+        }
+    }
+
+public:
+    node_type node(RTLIL::Cell *cell) { return cell_ids(cell); }
+    node_type node(SigBit const &bit) { return ~sig_ids(bit); }
+
+    bool is_cell(node_type node) { return node >= 0; }
+    bool is_sig(node_type node) { return node < 0; }
+
+    Cell *cell(node_type node) { return node >= 0 ? cell_ids[node] : nullptr; }
+    SigBit sig(node_type node) { return node < 0 ? sig_ids[~node] : SigBit(); }
+
+    template<typename Src, typename Dst>
+    void add_edge(Src &&src, Dst &&dst) {
+        computed = false;
+        node_type src_node = node(std::forward<Src>(src));
+        node_type dst_node = node(std::forward<Dst>(dst));
+        edges.emplace_back(std::make_pair(src_node, dst_node));
+    }
+
+    node_enumerator enumerate_nodes() {
+        if (!computed) compute();
+        return {-GetSize(sig_ids), GetSize(cell_ids)};
+    }
+
+    successor_enumerator enumerate_successors(node_type const &node) const {
+        auto range = edge_ranges[node + offset];
+        return {edges.begin() + range.first, edges.begin() + range.second};
+    }
+
+    int &dfs_index(node_type const &node) {
+        return indices_[node + offset];
+    }
+};
+
+
+class IntGraph {
+public:
+    typedef int node_type;
+
+    struct successor_enumerator {
+        std::vector<std::pair<int, int>>::const_iterator current, end;
+        bool finished() const { return current == end; }
+        node_type next() {
+            log_assert(!finished());
+            node_type result = current->second;
+            ++current;
+            return result;
+        }
+    };
+
+    struct node_enumerator {
+        int current, end;
+        bool finished() const { return current == end; }
+        node_type next() {
+            log_assert(!finished());
+            node_type result = current;
+            ++current;
+            return result;
+        }
+    };
+
+private:
+    std::vector<std::pair<int, int>> edges;
+    std::vector<std::pair<int, int>> edge_ranges;
+    std::vector<int> indices_;
+    bool computed = false;
+
+    void compute() {
+        edge_ranges.clear();
+
+        int node_end = 0;
+        for (auto const &edge : edges)
+            node_end = std::max(node_end, std::max(edge.first, edge.second) + 1);
+        indices_.clear();
+        indices_.resize(node_end, -1);
+
+        std::sort(edges.begin(), edges.end());
+        auto last = std::unique(edges.begin(), edges.end());
+        edges.erase(last, edges.end());
+        auto edge = edges.begin();
+        auto edge_end = edges.end();
+        int range_begin = 0;
+        for (int node = 0; node != node_end; ++node) {
+            while (edge != edge_end && edge->first <= node)
+                ++edge;
+            int range_end = edge - edges.begin();
+            edge_ranges.emplace_back(std::make_pair(range_begin, range_end));
+            range_begin = range_end;
+        }
+    }
+
+public:
+    void add_edge(int src, int dst) {
+        log_assert(src >= 0);
+        log_assert(dst >= 0);
+        computed = false;
+        edges.emplace_back(std::make_pair(src, dst));
+    }
+
+    node_enumerator enumerate_nodes() {
+        if (!computed) compute();
+        return {0, GetSize(indices_)};
+    }
+
+    successor_enumerator enumerate_successors(int node) const {
+        auto range = edge_ranges[node];
+        return {edges.begin() + range.first, edges.begin() + range.second};
+    }
+
+    int &dfs_index(node_type const &node) {
+        return indices_[node];
+    }
+};
+
+template<typename G, typename ComponentCallback>
+void topo_sorted_sccs(G &graph, ComponentCallback component)
+{
+    typedef typename G::node_enumerator node_enumerator;
+    typedef typename G::successor_enumerator successor_enumerator;
+    typedef typename G::node_type node_type;
+
+    struct dfs_entry {
+        node_type node;
+        successor_enumerator successors;
+        int lowlink;
+
+        dfs_entry(node_type node, successor_enumerator successors, int lowlink) :
+            node(node), successors(successors), lowlink(lowlink)
+        {}
+    };
+
+    std::vector<dfs_entry> dfs_stack;
+    std::vector<node_type> component_stack;
+    int next_index = 0;
+
+
+    node_enumerator nodes = graph.enumerate_nodes();
+
+    // iterate over all nodes to ensure we process the whole graph
+    while (!nodes.finished()) {
+        node_type node = nodes.next();
+        // only start a new search if the node wasn't visited yet
+        if (graph.dfs_index(node) >= 0)
+            continue;
+
+        while (true) {
+            // at this point we're visiting the node for the first time during
+            // the DFS search
+
+            // we record the timestamp of when we first visited the node as the
+            // dfs_index
+            int lowlink = next_index;
+            next_index++;
+            graph.dfs_index(node) = lowlink;
+
+            // and we add the node to the component stack where it will remain
+            // until all nodes of the component containing this node are popped
+            component_stack.push_back(node);
+
+            // then we start iterating over the successors of this node
+            successor_enumerator successors = graph.enumerate_successors(node);
+            while (true) {
+                if (successors.finished()) {
+                    // when we processed all successors, i.e. when we visited
+                    // the complete DFS subtree rooted at the current node, we
+                    // first check whether the current node is a SCC root
+                    //
+                    // (why this check identifies SCC roots is out of scope for
+                    // this comment, see other material on Tarjan's SCC
+                    // algorithm)
+                    if (lowlink == graph.dfs_index(node)) {
+                        // the SCC containing the current node is at the top of
+                        // the component stack, with the current node at the bottom
+                        int current = GetSize(component_stack);
+                        do {
+                            --current;
+                        } while (component_stack[current] != node);
+
+                        // we invoke the callback with a pointer range of the
+                        // nodes in the SCC
+
+                        node_type *stack_ptr = component_stack.data();
+                        node_type *component_begin = stack_ptr + current;
+                        node_type *component_end = stack_ptr + component_stack.size();
+
+                        // note that we allow the callback to permute the nodes
+                        // in this range as well as to modify dfs_index of the
+                        // nodes in the SCC.
+                        component(component_begin, component_end);
+
+                        // by setting the dfs_index of all already emitted
+                        // nodes to INT_MAX, we don't need a separate check for
+                        // whether successor nodes are still on the component
+                        // stack before updating the lowlink value
+                        for (; component_begin != component_end; ++component_begin)
+                            graph.dfs_index(*component_begin) = INT_MAX;
+                        component_stack.resize(current);
+                    }
+
+                    // after checking for a completed SCC the DFS either
+                    // continues the search at the parent node or returns to
+                    // the outer loop if we already are at the root node.
+                    if (dfs_stack.empty())
+                        goto next_search;
+                    auto &dfs_top = dfs_stack.back();
+
+                    node = dfs_top.node;
+                    successors = std::move(dfs_top.successors);
+
+                    // the parent's lowlink is updated when returning
+                    lowlink = min(lowlink, dfs_top.lowlink);
+                    dfs_stack.pop_back();
+                    // continue checking the remaining successors of the parent node.
+                } else {
+                    node_type succ = successors.next();
+                    if (graph.dfs_index(succ) < 0) {
+                        // if the successor wasn't visted yet, the DFS recurses
+                        // into the successor
+
+                        // we save the state for this node and make the
+                        // successor the current node.
+                        dfs_stack.emplace_back(node, std::move(successors), lowlink);
+                        node = succ;
+
+                        // this break gets us to the section corresponding to
+                        // the function entry in the recursive version
+                        break;
+                    } else {
+                        // the textbook version guards this update with a check
+                        // whether the successor is still on the component
+                        // stack. If the successor node was already visisted
+                        // but is not on the component stack, it must be part
+                        // of an already emitted SCC. We can avoid this check
+                        // by setting the DFS index of all nodes in a SCC to
+                        // INT_MAX when the SCC is emitted.
+                        lowlink = min(lowlink, graph.dfs_index(succ));
+                    }
+                }
+            }
+        }
+    next_search:;
+    }
+}
+
+YOSYS_NAMESPACE_END
+
+#endif

From c73c8a39cf27c1daae8b28b1874fd856efb2509b Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Mon, 15 Apr 2024 14:01:10 +0200
Subject: [PATCH 359/499] kernel/log: Add log_str helper for custom log_*
 functions/overloads

When implementing custom log_... functions or custom overloads for the
core log functions like log_signal it is necessary to return `char *`
that are valid long enough.

The log_... functions implemented in log.cc use either `log_id_cache` or
`string_buf` which both are cleared on log_pop.

This commit adds a public `log_str` function which stores its argument
in the `log_id_cache` and returns the stored copy, such that custom
log functions outside of log.cc can also create strings that remain
valid until the next `log_pop`.
---
 kernel/log.cc | 10 ++++++++++
 kernel/log.h  |  2 ++
 2 files changed, 12 insertions(+)

diff --git a/kernel/log.cc b/kernel/log.cc
index 9a61e8f08b3..55895da06d7 100644
--- a/kernel/log.cc
+++ b/kernel/log.cc
@@ -662,6 +662,16 @@ const char *log_id(const RTLIL::IdString &str)
 	return p+1;
 }
 
+const char *log_str(const char *str)
+{
+	log_id_cache.push_back(strdup(str));
+	return log_id_cache.back();
+}
+
+const char *log_str(std::string const &str) {
+	return log_str(str.c_str());
+}
+
 void log_module(RTLIL::Module *module, std::string indent)
 {
 	std::stringstream buf;
diff --git a/kernel/log.h b/kernel/log.h
index 53aae58c6bc..4b90cf9dceb 100644
--- a/kernel/log.h
+++ b/kernel/log.h
@@ -206,6 +206,8 @@ void log_check_expected();
 const char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true);
 const char *log_const(const RTLIL::Const &value, bool autoint = true);
 const char *log_id(const RTLIL::IdString &id);
+const char *log_str(const char *str);
+const char *log_str(std::string const &str);
 
 template<typename T> static inline const char *log_id(T *obj, const char *nullstr = nullptr) {
 	if (nullstr && obj == nullptr)

From f24e2536c657346853ac71b8483eca004f695d0e Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Mon, 15 Apr 2024 14:08:58 +0200
Subject: [PATCH 360/499] kernel/rtlil: Add `SigBit operator[](int offset)` to
 `SigChunk`

This is already supported by `SigSpec` and since both `SigChunk` and
`SigSpec` implement `extract` which is the multi-bit variant of this,
there is no good reason for `SigChunk` to not support
`SigBit operator[](int offset)`.
---
 kernel/rtlil.cc | 14 ++++++++++++++
 kernel/rtlil.h  |  1 +
 2 files changed, 15 insertions(+)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index d3946a620de..b77f8f5fe73 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -3754,6 +3754,20 @@ RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
 	return ret;
 }
 
+RTLIL::SigBit RTLIL::SigChunk::operator[](int offset) const
+{
+	log_assert(offset >= 0);
+	log_assert(offset <= width);
+	RTLIL::SigBit ret;
+	if (wire) {
+		ret.wire = wire;
+		ret.offset = this->offset + offset;
+	} else {
+		ret.data = data[offset];
+	}
+	return ret;
+}
+
 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
 {
 	if (wire && other.wire)
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index f9da2949508..685acf90426 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -769,6 +769,7 @@ struct RTLIL::SigChunk
 	SigChunk(const RTLIL::SigBit &bit);
 
 	RTLIL::SigChunk extract(int offset, int length) const;
+	RTLIL::SigBit operator[](int offset) const;
 	inline int size() const { return width; }
 	inline bool is_wire() const { return wire != NULL; }
 

From 56572978f51a5f81cfb6b706fbd5c123b9133bc6 Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Mon, 15 Apr 2024 14:12:16 +0200
Subject: [PATCH 361/499] drivertools: Utility code for indexing and traversing
 signal drivers

It adds `DriveBit`, `DriveChunk` and `DriveSpec` types which are similar
to `SigBit`, `SigChunk` and `SigSpec` but can also directly represent
cell ports, undriven bits and multiple drivers. For indexing an RTLIL
module and for querying signal drivers it comes with a `DriverMap` type
which is somewhat similar to a `SigMap` but is guaranteed to produce
signal drivers as returned representatives.

A `DriverMap` can also optionally preserve connections via intermediate
wires (e.g. querying the driver of a cell input port will return a
connected intermediate wire, querying the driver of that wire will
return the cell output port that's driving the wire).
---
 Makefile              |    2 +
 kernel/drivertools.cc |  946 +++++++++++++++++++++++++++++
 kernel/drivertools.h  | 1317 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 2265 insertions(+)
 create mode 100644 kernel/drivertools.cc
 create mode 100644 kernel/drivertools.h

diff --git a/Makefile b/Makefile
index d5e7e52356a..812a69271a7 100644
--- a/Makefile
+++ b/Makefile
@@ -598,6 +598,7 @@ $(eval $(call add_include_file,kernel/celltypes.h))
 $(eval $(call add_include_file,kernel/consteval.h))
 $(eval $(call add_include_file,kernel/constids.inc))
 $(eval $(call add_include_file,kernel/cost.h))
+$(eval $(call add_include_file,kernel/drivertools.h))
 $(eval $(call add_include_file,kernel/ff.h))
 $(eval $(call add_include_file,kernel/ffinit.h))
 $(eval $(call add_include_file,kernel/ffmerge.h))
@@ -638,6 +639,7 @@ $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h))
 OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o
 OBJS += kernel/binding.o
 OBJS += kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o
+OBJS += kernel/drivertools.o
 ifeq ($(ENABLE_ZLIB),1)
 OBJS += kernel/fstdata.o
 endif
diff --git a/kernel/drivertools.cc b/kernel/drivertools.cc
new file mode 100644
index 00000000000..499a9399c46
--- /dev/null
+++ b/kernel/drivertools.cc
@@ -0,0 +1,946 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Jannis Harder <jix@yosyshq.com> <me@jix.one>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/drivertools.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+DriveBit::DriveBit(SigBit const &bit)
+{
+	if (bit.is_wire())
+		*this = DriveBitWire(bit.wire, bit.offset);
+	else
+		*this = bit.data;
+}
+
+void DriveBit::merge(DriveBit const &other)
+{
+	if (other.type_ == DriveType::NONE)
+		return;
+	if (type_ == DriveType::NONE) {
+		*this = other;
+		return;
+	}
+	if (type_ != DriveType::MULTIPLE) {
+		DriveBitMultiple multi(std::move(*this));
+		*this = std::move(multi);
+	}
+	multiple().merge(other);
+}
+
+
+void DriveBitMultiple::merge(DriveBit const &single)
+{
+	if (single.type() == DriveType::NONE)
+		return;
+	if (single.type() == DriveType::MULTIPLE) {
+		merge(single.multiple());
+		return;
+	}
+	multiple_.emplace(single);
+}
+
+void DriveBitMultiple::merge(DriveBit &&single)
+{
+	if (single.type() == DriveType::NONE)
+		return;
+	if (single.type() == DriveType::MULTIPLE) {
+		merge(std::move(single.multiple()));
+		return;
+	}
+	multiple_.emplace(std::move(single));
+}
+
+DriveBitMultiple DriveChunkMultiple::operator[](int i) const
+{
+	DriveBitMultiple result;
+	for (auto const &single : multiple_)
+		result.merge(single[i]);
+	return result;
+}
+
+
+bool DriveChunkWire::can_append(DriveBitWire const &bit) const
+{
+	return bit.wire == wire && bit.offset == offset + width;
+}
+
+bool DriveChunkWire::try_append(DriveBitWire const &bit)
+{
+	if (!can_append(bit))
+		return false;
+	width += 1;
+	return true;
+}
+
+bool DriveChunkWire::try_append(DriveChunkWire const &chunk)
+{
+	if (chunk.wire != wire || chunk.offset != offset + width)
+		return false;
+	width += chunk.width;
+	return true;
+}
+
+bool DriveChunkPort::can_append(DriveBitPort const &bit) const
+{
+	return bit.cell == cell && bit.port == port && bit.offset == offset + width;
+}
+
+bool DriveChunkPort::try_append(DriveBitPort const &bit)
+{
+	if (!can_append(bit))
+		return false;
+	width += 1;
+	return true;
+}
+
+bool DriveChunkPort::try_append(DriveChunkPort const &chunk)
+{
+	if (chunk.cell != cell || chunk.port != port || chunk.offset != offset + width)
+		return false;
+	width += chunk.width;
+	return true;
+}
+
+bool DriveChunkMarker::can_append(DriveBitMarker const &bit) const
+{
+	return bit.marker == marker && bit.offset == offset + width;
+}
+
+bool DriveChunkMarker::try_append(DriveBitMarker const &bit)
+{
+	if (!can_append(bit))
+		return false;
+	width += 1;
+	return true;
+}
+
+bool DriveChunkMarker::try_append(DriveChunkMarker const &chunk)
+{
+	if (chunk.marker != marker || chunk.offset != offset + width)
+		return false;
+	width += chunk.width;
+	return true;
+}
+
+
+bool DriveChunkMultiple::can_append(DriveBitMultiple const &bit) const
+{
+	if (bit.multiple().size() != multiple_.size())
+		return false;
+
+	int const_drivers = 0;
+	for (DriveChunk const &single : multiple_)
+		if (single.is_constant())
+			const_drivers += 1;
+
+	if (const_drivers > 1)
+		return false;
+
+	for (DriveBit const &single : bit.multiple())
+		if (single.is_constant())
+			const_drivers -= 1;
+
+	if (const_drivers != 0)
+		return false;
+
+	for (DriveChunk const &single : multiple_)
+	{
+		switch (single.type())
+		{
+			case DriveType::CONSTANT: {
+			} break;
+			case DriveType::WIRE: {
+				auto const &wire = single.wire();
+				DriveBit next = DriveBitWire(wire.wire, wire.offset + wire.width);
+				if (!bit.multiple().count(next))
+					return false;
+			} break;
+			case DriveType::PORT: {
+				auto const &port = single.port();
+				DriveBit next = DriveBitPort(port.cell, port.port, port.offset + port.width);
+				if (!bit.multiple().count(next))
+					return false;
+			} break;
+			case DriveType::MARKER: {
+				auto const &marker = single.marker();
+				DriveBit next = DriveBitMarker(marker.marker, marker.offset + marker.width);
+				if (!bit.multiple().count(next))
+					return false;
+			} break;
+			default:
+				return false;
+		}
+	}
+
+	return true;
+}
+
+bool DriveChunkMultiple::can_append(DriveChunkMultiple const &chunk) const
+{
+	if (chunk.multiple().size() != multiple_.size())
+		return false;
+
+	int const_drivers = 0;
+	for (DriveChunk const &single : multiple_)
+		if (single.is_constant())
+			const_drivers += 1;
+
+	if (const_drivers > 1)
+		return false;
+
+	for (DriveChunk const &single : chunk.multiple())
+		if (single.is_constant())
+			const_drivers -= 1;
+
+	if (const_drivers != 0)
+		return false;
+
+	for (DriveChunk const &single : multiple_)
+	{
+		switch (single.type())
+		{
+			case DriveType::CONSTANT: {
+			} break;
+			case DriveType::WIRE: {
+				auto const &wire = single.wire();
+				DriveChunk next = DriveChunkWire(wire.wire, wire.offset + wire.width, chunk.size());
+				if (!chunk.multiple().count(next))
+					return false;
+			} break;
+			case DriveType::PORT: {
+				auto const &port = single.port();
+				DriveChunk next = DriveChunkPort(port.cell, port.port, port.offset + port.width, chunk.size());
+				if (!chunk.multiple().count(next))
+					return false;
+			} break;
+			case DriveType::MARKER: {
+				auto const &marker = single.marker();
+				DriveChunk next = DriveChunkMarker(marker.marker, marker.offset + marker.width, chunk.size());
+				if (!chunk.multiple().count(next))
+					return false;
+			} break;
+			default:
+				return false;
+		}
+	}
+
+	return true;
+}
+
+bool DriveChunkMultiple::try_append(DriveBitMultiple const &bit)
+{
+	if (!can_append(bit))
+		return false;
+	width_ += 1;
+	State constant;
+
+	for (DriveBit const &single : bit.multiple())
+		if (single.is_constant())
+			constant = single.constant();
+
+	for (DriveChunk &single : multiple_)
+	{
+		switch (single.type())
+		{
+			case DriveType::CONSTANT: {
+				single.constant().bits.push_back(constant);
+			} break;
+			case DriveType::WIRE: {
+				single.wire().width += 1;
+			} break;
+			case DriveType::PORT: {
+				single.port().width += 1;
+			} break;
+			case DriveType::MARKER: {
+				single.marker().width += 1;
+			} break;
+			default:
+				log_abort();
+		}
+	}
+	return true;
+}
+
+bool DriveChunkMultiple::try_append(DriveChunkMultiple const &chunk)
+{
+	if (!can_append(chunk))
+		return false;
+	int width = chunk.size();
+	width_ += width;
+	Const constant;
+
+	for (DriveChunk const &single : chunk.multiple())
+		if (single.is_constant())
+			constant = single.constant();
+
+	for (DriveChunk &single : multiple_)
+	{
+		switch (single.type())
+		{
+			case DriveType::CONSTANT: {
+				auto &bits = single.constant().bits;
+				bits.insert(bits.end(), constant.bits.begin(), constant.bits.end());
+			} break;
+			case DriveType::WIRE: {
+				single.wire().width += width;
+			} break;
+			case DriveType::PORT: {
+				single.port().width += width;
+			} break;
+			case DriveType::MARKER: {
+				single.marker().width += width;
+			} break;
+			default:
+				log_abort();
+		}
+	}
+	return true;
+}
+
+bool DriveChunk::can_append(DriveBit const &bit) const
+{
+	if (size() == 0)
+		return true;
+	if (bit.type() != type_)
+		return false;
+	switch (type_)
+	{
+		case DriveType::NONE:
+			return true;
+		case DriveType::CONSTANT:
+			return true;
+		case DriveType::WIRE:
+			return wire_.can_append(bit.wire());
+		case DriveType::PORT:
+			return port_.can_append(bit.port());
+		case DriveType::MULTIPLE:
+			return multiple_.can_append(bit.multiple());
+		default:
+			log_abort();
+	}
+}
+
+bool DriveChunk::try_append(DriveBit const &bit)
+{
+	if (size() == 0)
+		*this = bit;
+	if (bit.type() != type_)
+		return false;
+	switch (type_)
+	{
+		case DriveType::NONE:
+			none_ += 1;
+			return true;
+		case DriveType::CONSTANT:
+			constant_.bits.push_back(bit.constant());
+			return true;
+		case DriveType::WIRE:
+			return wire_.try_append(bit.wire());
+		case DriveType::PORT:
+			return port_.try_append(bit.port());
+		case DriveType::MULTIPLE:
+			return multiple_.try_append(bit.multiple());
+		default:
+			log_abort();
+	}
+}
+
+
+bool DriveChunk::try_append(DriveChunk const &chunk)
+{
+	if (size() == 0)
+		*this = chunk;
+	if (chunk.type_ != type_)
+		return false;
+	switch (type_)
+	{
+		case DriveType::NONE:
+			none_ += chunk.none_;
+			return true;
+		case DriveType::CONSTANT:
+			constant_.bits.insert(constant_.bits.end(), chunk.constant_.bits.begin(), chunk.constant_.bits.end());
+			return true;
+		case DriveType::WIRE:
+			return wire_.try_append(chunk.wire());
+		case DriveType::PORT:
+			return port_.try_append(chunk.port());
+		case DriveType::MARKER:
+			return marker_.try_append(chunk.marker());
+		case DriveType::MULTIPLE:
+			return multiple_.try_append(chunk.multiple());
+	}
+	log_abort();
+}
+
+void DriveSpec::append(DriveBit const &bit)
+{
+	hash_ = 0;
+	if (!packed()) {
+		bits_.push_back(bit);
+		width_ += 1;
+		return;
+	}
+
+	if (chunks_.empty() || !chunks_.back().try_append(bit))
+		chunks_.emplace_back(bit);
+	width_ += 1;
+}
+
+void DriveSpec::append(DriveChunk const &chunk)
+{
+	hash_ = 0;
+	pack();
+	if (chunks_.empty() || !chunks_.back().try_append(chunk))
+		chunks_.emplace_back(chunk);
+	width_ += chunk.size();
+}
+
+void DriveSpec::pack() const {
+	if (bits_.empty())
+		return;
+	std::vector<DriveBit> bits(std::move(bits_));
+	for (auto &bit : bits)
+		if (chunks_.empty() || !chunks_.back().try_append(bit))
+			chunks_.emplace_back(std::move(bit));
+}
+
+void DriveSpec::unpack() const {
+	if (chunks_.empty())
+		return;
+	for (auto &chunk : chunks_)
+	{
+		for (int i = 0, width = chunk.size(); i != width; ++i)
+		{
+			bits_.emplace_back(chunk[i]);
+		}
+	}
+	chunks_.clear();
+}
+
+void DriveSpec::compute_width()
+{
+	width_ = 0;
+	for (auto const &chunk : chunks_)
+		width_ += chunk.size();
+}
+
+void DriverMap::DriveBitGraph::add_edge(DriveBitId src, DriveBitId dst)
+{
+	if (first_edges.emplace(src, dst).first->second == dst)
+		return;
+	if (second_edges.emplace(src, dst).first->second == dst)
+		return;
+	more_edges[src].emplace(dst);
+}
+
+DriverMap::DriveBitId DriverMap::DriveBitGraph::pop_edge(DriveBitId src)
+{
+	// TODO unused I think?
+	auto found_more = more_edges.find(src);
+	if (found_more != more_edges.end()) {
+		auto result = found_more->second.pop();
+		if (found_more->second.empty())
+			more_edges.erase(found_more);
+		return result;
+	}
+
+	auto found_second = second_edges.find(src);
+	if (found_second != second_edges.end()) {
+		auto result = found_second->second;
+		second_edges.erase(found_second);
+		return result;
+	}
+
+	auto found_first = first_edges.find(src);
+	if (found_first != first_edges.end()) {
+		auto result = found_first->second;
+		first_edges.erase(found_first);
+		return result;
+	}
+
+	return DriveBitId();
+}
+
+void DriverMap::DriveBitGraph::clear(DriveBitId src)
+{
+	first_edges.erase(src);
+	second_edges.erase(src);
+	more_edges.erase(src);
+}
+
+bool DriverMap::DriveBitGraph::contains(DriveBitId src)
+{
+	return first_edges.count(src);
+}
+
+int DriverMap::DriveBitGraph::count(DriveBitId src)
+{
+	if (!first_edges.count(src))
+		return 0;
+	if (!second_edges.count(src))
+		return 1;
+	auto found = more_edges.find(src);
+	if (found == more_edges.end())
+		return 2;
+	return GetSize(found->second);
+}
+
+DriverMap::DriveBitId DriverMap::DriveBitGraph::at(DriveBitId src, int index)
+{
+	if (index == 0)
+		return first_edges.at(src);
+	else if (index == 1)
+		return second_edges.at(src);
+	else
+		return *more_edges.at(src).element(index - 2);
+}
+
+
+DriverMap::BitMode DriverMap::bit_mode(DriveBit const &bit)
+{
+	switch (bit.type())
+	{
+		case DriveType::NONE:
+			return BitMode::NONE;
+		case DriveType::CONSTANT:
+			// TODO how to handle Sx here?
+			return bit.constant() == State::Sz ? BitMode::NONE : BitMode::DRIVER;
+		case DriveType::WIRE: {
+			auto const &wire = bit.wire();
+			bool driver = wire.wire->port_input;
+			bool driven = wire.wire->port_output;
+
+			if (driver && !driven)
+				return BitMode::DRIVER;
+			else if (driven && !driver)
+				return BitMode::DRIVEN;
+			else if (driver && driven)
+				return BitMode::TRISTATE;
+			else
+				return keep_wire(bit.wire().wire) ? BitMode::KEEP : BitMode::NONE;
+		}
+		case DriveType::PORT: {
+			auto const &port = bit.port();
+			bool driver = celltypes.cell_output(port.cell->type, port.port);
+			bool driven = celltypes.cell_input(port.cell->type, port.port);
+			if (driver && !driven)
+				return BitMode::DRIVER;
+			else if (driven && !driver)
+				return BitMode::DRIVEN_UNIQUE;
+			else
+				return BitMode::TRISTATE;
+		}
+		case DriveType::MARKER: {
+			// TODO user supplied classification
+			log_abort();
+		}
+		default:
+			log_abort();
+	}
+}
+
+DriverMap::DriveBitId DriverMap::id_from_drive_bit(DriveBit const &bit)
+{
+	switch (bit.type())
+	{
+		case DriveType::NONE:
+			return -1;
+		case DriveType::CONSTANT:
+			return (int)bit.constant();
+		case DriveType::WIRE: {
+			auto const &wire_bit = bit.wire();
+			int offset = next_offset;
+			auto insertion = wire_offsets.emplace(wire_bit.wire, offset);
+			if (insertion.second) {
+				if (wire_bit.wire->width == 1) {
+					log_assert(wire_bit.offset == 0);
+					isolated_drive_bits.emplace(offset, bit);
+				} else
+					drive_bits.emplace(offset, DriveBitWire(wire_bit.wire, 0));
+				next_offset += wire_bit.wire->width;
+			}
+			return insertion.first->second.id + wire_bit.offset;
+		}
+		case DriveType::PORT: {
+			auto const &port_bit = bit.port();
+			auto key = std::make_pair(port_bit.cell, port_bit.port);
+			int offset = next_offset;
+			auto insertion = port_offsets.emplace(key, offset);
+			if (insertion.second) {
+				int width = port_bit.cell->connections().at(port_bit.port).size();
+				if (width == 1 && offset == 0) {
+					log_assert(port_bit.offset == 0);
+					isolated_drive_bits.emplace(offset, bit);
+				} else
+					drive_bits.emplace(offset, DriveBitPort(port_bit.cell, port_bit.port, 0));
+				next_offset += width;
+			}
+			return insertion.first->second.id + port_bit.offset;
+		}
+		default:
+			log_assert(false && "unsupported DriveType in DriverMap");
+	}
+	log_abort();
+}
+
+DriveBit DriverMap::drive_bit_from_id(DriveBitId id)
+{
+	auto found_isolated = isolated_drive_bits.find(id);
+	if (found_isolated != isolated_drive_bits.end())
+		return found_isolated->second;
+
+	auto found = drive_bits.upper_bound(id);
+	if (found == drive_bits.begin()) {
+		return id < 0 ? DriveBit() : DriveBit((State) id.id);
+	}
+	--found;
+	DriveBit result = found->second;
+	if (result.is_wire()) {
+		result.wire().offset += id.id - found->first.id;
+	} else {
+		log_assert(result.is_port());
+		result.port().offset += id.id - found->first.id;
+	}
+	return result;
+}
+
+void DriverMap::connect_directed_merge(DriveBitId driven_id, DriveBitId driver_id)
+{
+	if (driven_id == driver_id)
+		return;
+
+	same_driver.merge(driven_id, driver_id);
+
+	for (int i = 0, end = connected_drivers.count(driven_id); i != end; ++i)
+		connected_drivers.add_edge(driver_id, connected_drivers.at(driven_id, i));
+
+	connected_drivers.clear(driven_id);
+
+	for (int i = 0, end = connected_undirected.count(driven_id); i != end; ++i)
+		connected_undirected.add_edge(driver_id, connected_undirected.at(driven_id, i));
+
+	connected_undirected.clear(driven_id);
+}
+
+void DriverMap::connect_directed_buffer(DriveBitId driven_id, DriveBitId driver_id)
+{
+	connected_drivers.add_edge(driven_id, driver_id);
+}
+
+void DriverMap::connect_undirected(DriveBitId a_id, DriveBitId b_id)
+{
+	connected_undirected.add_edge(a_id, b_id);
+	connected_undirected.add_edge(b_id, a_id);
+}
+
+void DriverMap::add(Module *module)
+{
+	for (auto const &conn : module->connections())
+		add(conn.first, conn.second);
+
+	for (auto cell : module->cells())
+		for (auto const &conn : cell->connections())
+			add_port(cell, conn.first, conn.second);
+}
+
+// Add a single bit connection to the driver map.
+void DriverMap::add(DriveBit const &a, DriveBit const &b)
+{
+	DriveBitId a_id = id_from_drive_bit(a);
+	DriveBitId b_id = id_from_drive_bit(b);
+
+	DriveBitId orig_a_id = a_id;
+	DriveBitId orig_b_id = b_id;
+
+	a_id = same_driver.find(a_id);
+	b_id = same_driver.find(b_id);
+
+	if (a_id == b_id)
+		return;
+
+	BitMode a_mode = bit_mode(orig_a_id == a_id ? a : drive_bit_from_id(a_id));
+	BitMode b_mode = bit_mode(orig_b_id == b_id ? b : drive_bit_from_id(b_id));
+
+	// If either bit is just a wire that we don't need to keep, merge and
+	// use the other end as representative bit.
+	if (a_mode == BitMode::NONE)
+		connect_directed_merge(a_id, b_id);
+	else if (b_mode == BitMode::NONE)
+		connect_directed_merge(b_id, a_id);
+	// If either bit requires a driven value and has a unique driver, merge
+	// and use the other end as representative bit.
+	else if (a_mode == BitMode::DRIVEN_UNIQUE && !(b_mode == BitMode::DRIVEN_UNIQUE || b_mode == BitMode::DRIVEN))
+		connect_directed_buffer(a_id, b_id);
+	else if (b_mode == BitMode::DRIVEN_UNIQUE && !(b_mode == BitMode::DRIVEN_UNIQUE || b_mode == BitMode::DRIVEN))
+		connect_directed_buffer(b_id, a_id);
+	// If either bit only drives a value, store a directed connection from
+	// it to the other bit.
+	else if (a_mode == BitMode::DRIVER)
+		connect_directed_buffer(b_id, a_id);
+	else if (b_mode == BitMode::DRIVER)
+		connect_directed_buffer(a_id, b_id);
+	// Otherwise we store an undirected connection which we will resolve
+	// during querying.
+	else
+		connect_undirected(a_id, b_id);
+
+	return;
+}
+
+// Specialized version that avoids unpacking
+void DriverMap::add(SigSpec const &a, SigSpec const &b)
+{
+	log_assert(a.size() == b.size());
+	auto const &a_chunks = a.chunks();
+	auto const &b_chunks = b.chunks();
+
+	auto a_chunk = a_chunks.begin();
+	auto a_end = a_chunks.end();
+	int a_offset = 0;
+
+	auto b_chunk = b_chunks.begin();
+	int b_offset = 0;
+
+	SigChunk tmp_a, tmp_b;
+	while (a_chunk != a_end) {
+		int a_width = a_chunk->width - a_offset;
+		if (a_width == 0) {
+			a_offset = 0;
+			++a_chunk;
+			continue;
+		}
+		int b_width = b_chunk->width - b_offset;
+		if (b_width == 0) {
+			b_offset = 0;
+			++b_chunk;
+			continue;
+		}
+		int width = std::min(a_width, b_width);
+		log_assert(width > 0);
+
+		SigChunk const &a_subchunk =
+			a_offset == 0 && a_width == width ? *a_chunk : a_chunk->extract(a_offset, width);
+		SigChunk const &b_subchunk =
+			b_offset == 0 && b_width == width ? *b_chunk : b_chunk->extract(b_offset, width);
+
+		add(a_subchunk, b_subchunk);
+
+		a_offset += width;
+		b_offset += width;
+	}
+}
+
+void DriverMap::add_port(Cell *cell, IdString const &port, SigSpec const &b)
+{
+	int offset = 0;
+	for (auto const &chunk : b.chunks()) {
+		add(chunk, DriveChunkPort(cell, port, offset, chunk.width));
+		offset += chunk.size();
+	}
+}
+
+void DriverMap::orient_undirected(DriveBitId id)
+{
+	pool<DriveBitId> &seen = orient_undirected_seen;
+	pool<DriveBitId> &drivers = orient_undirected_drivers;
+	dict<DriveBitId, int> &distance = orient_undirected_distance;
+	seen.clear();
+	drivers.clear();
+
+	seen.emplace(id);
+
+	for (int pos = 0; pos < GetSize(seen); ++pos) {
+		DriveBitId current = *seen.element(seen.size() - 1 - pos);
+		DriveBit bit = drive_bit_from_id(current);
+
+		BitMode mode = bit_mode(bit);
+
+		if (mode == BitMode::DRIVER || mode == BitMode::TRISTATE)
+			drivers.emplace(current);
+
+		if (connected_drivers.contains(current))
+			drivers.emplace(current);
+
+		int undirected_driver_count = connected_undirected.count(current);
+
+		for (int i = 0; i != undirected_driver_count; ++i)
+			seen.emplace(same_driver.find(connected_undirected.at(current, i)));
+	}
+
+	if (drivers.empty())
+		for (auto seen_id : seen)
+			drivers.emplace(seen_id);
+
+	for (auto driver : drivers)
+	{
+		distance.clear();
+		distance.emplace(driver, 0);
+
+		for (int pos = 0; pos < GetSize(distance); ++pos) {
+			auto current_it = distance.element(distance.size() - 1 - pos);
+
+			DriveBitId current = current_it->first;
+			int undirected_driver_count = connected_undirected.count(current);
+
+			for (int i = 0; i != undirected_driver_count; ++i)
+			{
+				DriveBitId next = same_driver.find(connected_undirected.at(current, i));
+				auto emplaced = distance.emplace(next, current_it->second + 1);
+				if (emplaced.first->second == current_it->second + 1)
+					connected_oriented.add_edge(next, current);
+			}
+		}
+	}
+
+	for (auto seen_id : seen)
+		oriented_present.emplace(seen_id);
+}
+
+DriveBit DriverMap::operator()(DriveBit const &bit)
+{
+	if (bit.type() == DriveType::MARKER || bit.type() == DriveType::NONE)
+		return bit;
+	if (bit.type() == DriveType::MULTIPLE)
+	{
+		DriveBit result;
+		for (auto const &inner : bit.multiple().multiple())
+			result.merge((*this)(inner));
+		return result;
+	}
+
+	DriveBitId bit_id = id_from_drive_bit(bit);
+
+	bit_id = same_driver.find(bit_id);
+
+	DriveBit bit_repr = drive_bit_from_id(bit_id);
+
+	BitMode mode = bit_mode(bit_repr);
+
+	int implicit_driver_count = connected_drivers.count(bit_id);
+	if (connected_undirected.contains(bit_id) && !oriented_present.count(bit_id))
+		orient_undirected(bit_id);
+
+	DriveBit driver;
+
+	if (mode == BitMode::DRIVER || mode == BitMode::TRISTATE)
+		driver = bit_repr;
+
+	for (int i = 0; i != implicit_driver_count; ++i)
+		driver.merge(drive_bit_from_id(connected_drivers.at(bit_id, i)));
+
+	int oriented_driver_count = connected_oriented.count(bit_id);
+	for (int i = 0; i != oriented_driver_count; ++i)
+		driver.merge(drive_bit_from_id(connected_oriented.at(bit_id, i)));
+
+	return driver;
+}
+
+DriveSpec DriverMap::operator()(DriveSpec spec)
+{
+	DriveSpec result;
+
+	for (int i = 0, width = spec.size(); i != width; ++i)
+		result.append((*this)(spec[i]));
+
+	return result;
+}
+
+const char *log_signal(DriveChunkWire const &chunk)
+{
+	const char *id = log_id(chunk.wire->name);
+	if (chunk.is_whole())
+		return id;
+	if (chunk.width == 1)
+		return log_str(stringf("%s [%d]", id, chunk.offset));
+	return log_str(stringf("%s [%d:%d]", id, chunk.offset + chunk.width - 1, chunk.offset));
+}
+
+
+const char *log_signal(DriveChunkPort const &chunk)
+{
+	const char *cell_id = log_id(chunk.cell->name);
+	const char *port_id = log_id(chunk.port);
+	if (chunk.is_whole())
+		return log_str(stringf("%s <%s>", cell_id, port_id));
+	if (chunk.width == 1)
+		return log_str(stringf("%s <%s> [%d]", cell_id, port_id, chunk.offset));
+	return log_str(stringf("%s <%s> [%d:%d]", cell_id, port_id, chunk.offset + chunk.width - 1, chunk.offset));
+}
+
+const char *log_signal(DriveChunkMarker const &chunk)
+{
+	if (chunk.width == 1)
+		return log_str(stringf("<marker %d> [%d]", chunk.marker, chunk.offset));
+	return log_str(stringf("<marker %d> [%d:%d]", chunk.marker, chunk.offset + chunk.width - 1, chunk.offset));
+}
+
+const char *log_signal(DriveChunk const &chunk)
+{
+	switch (chunk.type())
+	{
+		case DriveType::NONE:
+			return log_str(stringf("<none x%d>", chunk.size()));
+		case DriveType::CONSTANT:
+			return log_const(chunk.constant());
+		case DriveType::WIRE:
+			return log_signal(chunk.wire());
+		case DriveType::PORT:
+			return log_signal(chunk.port());
+		case DriveType::MARKER:
+			return log_signal(chunk.marker());
+		case DriveType::MULTIPLE: {
+			std::string str = "<multiple";
+			const char *sep = " ";
+			for (auto const &single : chunk.multiple().multiple()) {
+				str += sep;
+				sep = ", ";
+				str += log_signal(single);
+			}
+			str += ">";
+			return log_str(str);
+		}
+		default:
+			log_abort();
+	}
+}
+
+const char *log_signal(DriveSpec const &spec)
+{
+	auto &chunks = spec.chunks();
+	if (chunks.empty())
+		return "{}";
+	if (chunks.size() == 1)
+		return log_signal(chunks[0]);
+
+	std::string str;
+	const char *sep = "{ ";
+
+	for (auto i = chunks.rbegin(), end = chunks.rend(); i != end; ++i)
+	{
+		str += sep;
+		sep = " ";
+		str += log_signal(*i);
+	}
+	str += " }";
+
+	return log_str(str);
+}
+
+YOSYS_NAMESPACE_END
diff --git a/kernel/drivertools.h b/kernel/drivertools.h
new file mode 100644
index 00000000000..b440afddaa2
--- /dev/null
+++ b/kernel/drivertools.h
@@ -0,0 +1,1317 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Jannis Harder <jix@yosyshq.com> <me@jix.one>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef DRIVERTOOLS_H
+#define DRIVERTOOLS_H
+
+#include <type_traits>
+
+#include "kernel/rtlil.h"
+#include "kernel/sigtools.h"
+#include "kernel/celltypes.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+// TODO move implementation into a .cc file
+
+struct DriveBit;
+
+struct DriveChunkWire;
+struct DriveChunkPort;
+struct DriveChunkMarker;
+struct DriveChunk;
+
+struct DriveSpec;
+
+const char *log_signal(DriveChunkWire const &chunk);
+const char *log_signal(DriveChunkPort const &chunk);
+const char *log_signal(DriveChunkMarker const &chunk);
+const char *log_signal(DriveChunk const &chunk);
+const char *log_signal(DriveSpec const &chunk);
+
+enum class DriveType : unsigned char
+{
+	NONE,
+	CONSTANT,
+	WIRE,
+	PORT,
+	MULTIPLE,
+	MARKER,
+};
+
+struct DriveBitWire
+{
+	Wire *wire;
+	int offset;
+
+	DriveBitWire(Wire *wire, int offset) : wire(wire), offset(offset) {}
+
+	bool operator==(const DriveBitWire &other) const
+	{
+		return wire == other.wire && offset == other.offset;
+	}
+
+	bool operator<(const DriveBitWire &other) const
+	{
+		if (wire != other.wire)
+			return wire->name < other.wire->name;
+		return offset < other.offset;
+	}
+
+	unsigned int hash() const
+	{
+		return mkhash_add(wire->name.hash(), offset);
+	}
+
+	operator SigBit() const
+	{
+		return SigBit(wire, offset);
+	}
+};
+
+struct DriveBitPort
+{
+	Cell *cell;
+	IdString port;
+	int offset;
+
+	DriveBitPort(Cell *cell, IdString port, int offset) : cell(cell), port(port), offset(offset) {}
+
+	bool operator==(const DriveBitPort &other) const
+	{
+		return cell == other.cell && port == other.port && offset == other.offset;
+	}
+
+	bool operator<(const DriveBitPort &other) const
+	{
+		if (cell != other.cell)
+			return cell->name < other.cell->name;
+		if (port != other.port)
+			return port < other.port;
+		return offset < other.offset;
+	}
+
+	unsigned int hash() const
+	{
+		return mkhash_add(mkhash(cell->name.hash(), port.hash()), offset);
+	}
+};
+
+
+struct DriveBitMarker
+{
+	int marker;
+	int offset;
+
+	DriveBitMarker(int marker, int offset) : marker(marker), offset(offset) {}
+
+	bool operator==(const DriveBitMarker &other) const
+	{
+		return marker == other.marker && offset == other.offset;
+	}
+
+	bool operator<(const DriveBitMarker &other) const
+	{
+		if (marker != other.marker)
+			return marker < other.marker;
+		return offset < other.offset;
+	}
+
+	unsigned int hash() const
+	{
+		return mkhash_add(marker, offset);
+	}
+
+};
+
+struct DriveBitMultiple
+{
+private:
+	pool<DriveBit> multiple_;
+
+public:
+	DriveBitMultiple() {}
+	DriveBitMultiple(DriveBit const &single)
+	{
+		multiple_.emplace(single);
+	}
+
+	pool<DriveBit> const &multiple() const { return multiple_; }
+
+	void merge(DriveBitMultiple const &other)
+	{
+		for (DriveBit const &single : other.multiple_)
+			merge(single);
+	}
+
+	void merge(DriveBitMultiple &&other)
+	{
+		for (DriveBit &single : other.multiple_)
+			merge(std::move(single));
+	}
+
+	void merge(DriveBit const &single);
+	void merge(DriveBit &&single);
+
+	bool operator==(const DriveBitMultiple &other) const
+	{
+		return multiple_ == other.multiple_;
+	}
+
+	unsigned int hash() const
+	{
+	   return multiple_.hash();
+	}
+};
+
+struct DriveBit
+{
+private:
+	DriveType type_ = DriveType::NONE;
+	union
+	{
+		State constant_;
+		DriveBitWire wire_;
+		DriveBitPort port_;
+		DriveBitMarker marker_;
+		DriveBitMultiple multiple_;
+	};
+public:
+	DriveBit()  {}
+
+	DriveBit(SigBit const &bit);
+
+	DriveBit(DriveBit const &other) { *this = other; }
+	DriveBit(DriveBit &&other) { *this = other; }
+
+
+	DriveBit(State constant) { *this = constant; }
+	DriveBit(DriveBitWire const &wire) { *this = wire; }
+	DriveBit(DriveBitWire &&wire) { *this = wire; }
+	DriveBit(DriveBitPort const &port) { *this = port; }
+	DriveBit(DriveBitPort &&port) { *this = port; }
+	DriveBit(DriveBitMarker const &marker) { *this = marker; }
+	DriveBit(DriveBitMarker &&marker) { *this = marker; }
+	DriveBit(DriveBitMultiple const &multiple) { *this = multiple; }
+	DriveBit(DriveBitMultiple &&multiple) { *this = multiple; }
+
+	~DriveBit() { set_none(); }
+
+	void set_none()
+	{
+		switch (type_)
+		{
+			case DriveType::NONE:
+				break;
+			case DriveType::CONSTANT:
+				break;
+			case DriveType::WIRE:
+				wire_.~DriveBitWire();
+				break;
+			case DriveType::PORT:
+				port_.~DriveBitPort();
+				break;
+			case DriveType::MARKER:
+				marker_.~DriveBitMarker();
+				break;
+			case DriveType::MULTIPLE:
+				multiple_.~DriveBitMultiple();
+				break;
+		}
+		type_ = DriveType::NONE;
+	}
+
+	DriveBit &operator=(DriveBit const &other)
+	{
+		switch (other.type_)
+		{
+			case DriveType::NONE:
+				set_none();
+				break;
+			case DriveType::CONSTANT:
+				*this = other.constant_;
+				break;
+			case DriveType::WIRE:
+				*this = other.wire_;
+				break;
+			case DriveType::PORT:
+				*this = other.port_;
+				break;
+			case DriveType::MARKER:
+				*this = other.marker_;
+				break;
+			case DriveType::MULTIPLE:
+				*this = other.multiple_;
+				break;
+		}
+		return *this;
+	}
+
+	DriveBit &operator=(DriveBit &&other)
+	{
+		switch (other.type_)
+		{
+			case DriveType::NONE:
+				set_none();
+				break;
+			case DriveType::CONSTANT:
+				*this = std::move(other.constant_);
+				break;
+			case DriveType::WIRE:
+				*this = std::move(other.wire_);
+				break;
+			case DriveType::PORT:
+				*this = std::move(other.port_);
+				break;
+			case DriveType::MARKER:
+				*this = std::move(other.marker_);
+				break;
+			case DriveType::MULTIPLE:
+				*this = std::move(other.multiple_);
+				break;
+		}
+		return *this;
+	}
+
+	DriveBit &operator=(State constant)
+	{
+		set_none();
+		constant_ = constant;
+		type_ = DriveType::CONSTANT;
+		return *this;
+	}
+
+	DriveBit &operator=(DriveBitWire const &wire)
+	{
+		set_none();
+		new (&wire_) DriveBitWire(wire);
+		type_ = DriveType::WIRE;
+		return *this;
+	}
+
+	DriveBit &operator=(DriveBitWire &&wire)
+	{
+		set_none();
+		new (&wire_) DriveBitWire(wire);
+		type_ = DriveType::WIRE;
+		return *this;
+	}
+
+	DriveBit &operator=(DriveBitPort const &port)
+	{
+		set_none();
+		new (&port_) DriveBitPort(port);
+		type_ = DriveType::PORT;
+		return *this;
+	}
+
+	DriveBit &operator=(DriveBitPort &&port)
+	{
+		set_none();
+		new (&port_) DriveBitPort(port);
+		type_ = DriveType::PORT;
+		return *this;
+	}
+
+	DriveBit &operator=(DriveBitMarker const &marker)
+	{
+		set_none();
+		new (&marker_) DriveBitMarker(marker);
+		type_ = DriveType::MARKER;
+		return *this;
+	}
+
+	DriveBit &operator=(DriveBitMarker &&marker)
+	{
+		set_none();
+		new (&marker_) DriveBitMarker(marker);
+		type_ = DriveType::MARKER;
+		return *this;
+	}
+
+	DriveBit &operator=(DriveBitMultiple const &multiple)
+	{
+		set_none();
+		if (multiple.multiple().empty())
+			return *this;
+		new (&multiple_) DriveBitMultiple(multiple);
+		type_ = DriveType::MULTIPLE;
+		return *this;
+	}
+
+	DriveBit &operator=(DriveBitMultiple &&multiple)
+	{
+		set_none();
+		if (multiple.multiple().empty())
+			return *this;
+		new (&multiple_) DriveBitMultiple(multiple);
+		type_ = DriveType::MULTIPLE;
+		return *this;
+	}
+
+	unsigned int hash() const
+	{
+		unsigned int inner;
+		switch (type_)
+		{
+			case DriveType::NONE:
+				inner = 0;
+				break;
+			case DriveType::CONSTANT:
+				inner = constant_;
+				break;
+			case DriveType::WIRE:
+				inner = wire_.hash();
+				break;
+			case DriveType::PORT:
+				inner = port_.hash();
+				break;
+			case DriveType::MARKER:
+				inner = marker_.hash();
+				break;
+			case DriveType::MULTIPLE:
+				inner = multiple_.hash();
+				break;
+		}
+		return mkhash((unsigned int)type_, inner);
+	}
+
+	bool operator==(const DriveBit &other) const
+	{
+		if (type_ != other.type_)
+			return false;
+
+		switch (type_)
+		{
+			case DriveType::NONE:
+				return true;
+			case DriveType::CONSTANT:
+				return constant_ == other.constant_;
+			case DriveType::WIRE:
+				return wire_ == other.wire_;
+			case DriveType::PORT:
+				return port_ == other.port_;
+			case DriveType::MARKER:
+				return marker_ == other.marker_;
+			case DriveType::MULTIPLE:
+				return multiple_ == other.multiple_;
+		}
+		log_assert(false);
+	}
+
+	bool operator!=(const DriveBit &other) const
+	{
+		return !(*this == other);
+	}
+
+	bool operator<(const DriveBit &other) const
+	{
+		if (type_ != other.type_)
+			return type_ < other.type_;
+		switch (type_)
+		{
+			case DriveType::NONE:
+				return false;
+			case DriveType::CONSTANT:
+				return constant_ < other.constant_;
+			case DriveType::WIRE:
+				return wire_ < other.wire_;
+			case DriveType::PORT:
+				return port_ < other.port_;
+			case DriveType::MARKER:
+				return marker_ < other.marker_;
+			case DriveType::MULTIPLE:
+				log_assert(!"TODO");
+		}
+		log_abort();
+	}
+
+
+	DriveType type() const { return type_; }
+
+	bool is_none() const { return type_ == DriveType::NONE; }
+	bool is_constant() const { return type_ == DriveType::CONSTANT; }
+	bool is_wire() const { return type_ == DriveType::WIRE; }
+	bool is_port() const { return type_ == DriveType::PORT; }
+	bool is_marker() const { return type_ == DriveType::MARKER; }
+	bool is_multiple() const { return type_ == DriveType::MULTIPLE; }
+
+	State &constant() { log_assert(is_constant()); return constant_; }
+	State const &constant() const { log_assert(is_constant()); return constant_; }
+	DriveBitWire &wire() { log_assert(is_wire()); return wire_; }
+	DriveBitWire const &wire() const { log_assert(is_wire()); return wire_; }
+	DriveBitPort &port() { log_assert(is_port()); return port_; }
+	DriveBitPort const &port() const { log_assert(is_port()); return port_; }
+	DriveBitMarker &marker() { log_assert(is_marker()); return marker_; }
+	DriveBitMarker const &marker() const { log_assert(is_marker()); return marker_; }
+	DriveBitMultiple &multiple() { log_assert(is_multiple()); return multiple_; }
+	DriveBitMultiple const &multiple() const { log_assert(is_multiple()); return multiple_; }
+
+	void merge(DriveBit const &other);
+
+};
+
+
+struct DriveChunkWire
+{
+	Wire *wire;
+	int offset;
+	int width;
+
+	DriveChunkWire(Wire *wire, int offset, int width) : wire(wire), offset(offset), width(width) {}
+	DriveChunkWire(DriveBitWire const &bit) : wire(bit.wire), offset(bit.offset), width(1) {}
+
+	int size() const { return width; }
+
+	DriveBitWire operator[](int i) const
+	{
+		log_assert(i >= 0 && i < width);
+		return DriveBitWire(wire, offset + i);
+	}
+
+	bool can_append(DriveBitWire const &bit) const;
+	bool try_append(DriveBitWire const &bit);
+	bool try_append(DriveChunkWire const &chunk);
+
+	// Whether this chunk is a whole wire
+	bool is_whole() const { return offset == 0 && width == wire->width; }
+
+	bool operator==(const DriveChunkWire &other) const
+	{
+		return wire == other.wire && offset == other.offset && width == other.width;
+	}
+
+	bool operator<(const DriveChunkWire &other) const
+	{
+		if (wire != other.wire)
+			return wire->name < other.wire->name;
+		if (width != other.width)
+			return width < other.width;
+		return offset < other.offset;
+	}
+
+	unsigned int hash() const
+	{
+		return mkhash_add(mkhash(wire->name.hash(), width), offset);
+	}
+
+	explicit operator SigChunk() const
+	{
+		return SigChunk(wire, offset, width);
+	}
+};
+
+struct DriveChunkPort
+{
+	Cell *cell;
+	IdString port;
+	int offset;
+	int width;
+
+	DriveChunkPort(Cell *cell, IdString port, int offset, int width) :
+		cell(cell), port(port), offset(offset), width(width) { }
+	DriveChunkPort(Cell *cell, IdString port) :
+		cell(cell), port(port), offset(0), width(GetSize(cell->connections().at(port))) { }
+	DriveChunkPort(Cell *cell, std::pair<IdString, SigSpec> const &conn) :
+		cell(cell), port(conn.first), offset(0), width(GetSize(conn.second)) { }
+	DriveChunkPort(DriveBitPort const &bit) :
+		cell(bit.cell), port(bit.port), offset(bit.offset), width(1) { }
+
+	int size() const { return width; }
+
+	DriveBitPort operator[](int i) const
+	{
+		log_assert(i >= 0 && i < width);
+		return DriveBitPort(cell, port, offset + i);
+	}
+
+	bool can_append(DriveBitPort const &bit) const;
+	bool try_append(DriveBitPort const &bit);
+	bool try_append(DriveChunkPort const &chunk);
+
+	// Whether this chunk is a whole port
+	bool is_whole() const
+	{
+		return offset == 0 && width == cell->connections().at(port).size();
+	}
+
+	bool operator==(const DriveChunkPort &other) const
+	{
+		return cell == other.cell && port == other.port && offset == other.offset && width == other.width;
+	}
+
+	bool operator<(const DriveChunkPort &other) const
+	{
+		if (cell != other.cell)
+			return cell->name < other.cell->name;
+		if (port != other.port)
+			return port < other.port;
+		if (width != other.width)
+			return width < other.width;
+		return offset < other.offset;
+	}
+
+	unsigned int hash() const
+	{
+		return mkhash_add(mkhash(mkhash(cell->name.hash(), port.hash()), width), offset);
+	}
+};
+
+
+struct DriveChunkMarker
+{
+	int marker;
+	int offset;
+	int width;
+
+	DriveChunkMarker(int marker, int offset, int width) :
+		marker(marker), offset(offset), width(width) {}
+	DriveChunkMarker(DriveBitMarker const &bit) :
+		marker(bit.marker), offset(bit.offset), width(1) {}
+
+	int size() const { return width; }
+
+	DriveBitMarker operator[](int i) const
+	{
+		log_assert(i >= 0 && i < width);
+		return DriveBitMarker(marker, offset + i);
+	}
+
+	bool can_append(DriveBitMarker const &bit) const;
+	bool try_append(DriveBitMarker const &bit);
+	bool try_append(DriveChunkMarker const &chunk);
+
+	bool operator==(const DriveChunkMarker &other) const
+	{
+		return marker == other.marker && offset == other.offset && width == other.width;
+	}
+
+	bool operator<(const DriveChunkMarker &other) const
+	{
+		if (marker != other.marker)
+			return marker < other.marker;
+		if (width != other.width)
+			return width < other.width;
+		return offset < other.offset;
+	}
+
+	unsigned int hash() const
+	{
+		return mkhash_add(mkhash(marker, width), offset);
+	}
+};
+
+struct DriveChunkMultiple
+{
+private:
+	mutable pool<DriveChunk> multiple_;
+	int width_;
+
+public:
+	pool<DriveChunk> const &multiple() const { return multiple_; }
+
+	DriveChunkMultiple(DriveBitMultiple const &bit) : width_(1) {
+		for (auto const &bit : bit.multiple())
+			multiple_.emplace(bit);
+	}
+
+	int size() const { return width_; }
+
+	DriveBitMultiple operator[](int i) const;
+
+	bool can_append(DriveBitMultiple const &bit) const;
+
+	bool try_append(DriveBitMultiple const &bit);
+
+
+	bool can_append(DriveChunkMultiple const &bit) const;
+
+	bool try_append(DriveChunkMultiple const &bit);
+
+	bool operator==(const DriveChunkMultiple &other) const
+	{
+		return width_ == other.width_ && multiple_ == other.multiple_;
+	}
+
+	bool operator<(const DriveChunkMultiple &other) const
+	{
+		if (multiple_.size() < other.multiple_.size())
+
+		multiple_.sort();
+		return false; // TODO implement, canonicalize order
+	}
+
+	unsigned int hash() const
+	{
+	   return mkhash(width_, multiple_.hash());
+	}
+};
+
+struct DriveChunk
+{
+private:
+	DriveType type_ = DriveType::NONE;
+	union
+	{
+		int none_;
+		Const constant_;
+		DriveChunkWire wire_;
+		DriveChunkPort port_;
+		DriveChunkMarker marker_;
+		DriveChunkMultiple multiple_;
+	};
+
+public:
+	DriveChunk() { set_none(); }
+
+	DriveChunk(DriveChunk const &other) { *this = other; }
+	DriveChunk(DriveChunk &&other) { *this = other; }
+
+	DriveChunk(DriveBit const &other) { *this = other; }
+
+	DriveChunk(Const const &constant) { *this = constant; }
+	DriveChunk(Const &&constant) { *this = constant; }
+	DriveChunk(DriveChunkWire const &wire) { *this = wire; }
+	DriveChunk(DriveChunkWire &&wire) { *this = wire; }
+	DriveChunk(DriveChunkPort const &port) { *this = port; }
+	DriveChunk(DriveChunkPort &&port) { *this = port; }
+	DriveChunk(DriveChunkMarker const &marker) { *this = marker; }
+	DriveChunk(DriveChunkMarker &&marker) { *this = marker; }
+	DriveChunk(DriveChunkMultiple const &multiple) { *this = multiple; }
+	DriveChunk(DriveChunkMultiple &&multiple) { *this = multiple; }
+
+	~DriveChunk() { set_none(); }
+
+	DriveBit operator[](int i) const
+	{
+		switch (type_)
+		{
+			case DriveType::NONE:
+				return DriveBit();
+			case DriveType::CONSTANT:
+				return constant_[i];
+			case DriveType::WIRE:
+				return wire_[i];
+			case DriveType::PORT:
+				return port_[i];
+			case DriveType::MARKER:
+				return marker_[i];
+			case DriveType::MULTIPLE:
+				return multiple_[i];
+		}
+		log_abort();
+	}
+
+	void set_none(int width = 0)
+	{
+		switch (type_)
+		{
+			case DriveType::NONE:
+				none_ = width;
+				break;
+			case DriveType::CONSTANT:
+				constant_.~Const();
+				break;
+			case DriveType::WIRE:
+				wire_.~DriveChunkWire();
+				break;
+			case DriveType::PORT:
+				port_.~DriveChunkPort();
+				break;
+			case DriveType::MARKER:
+				marker_.~DriveChunkMarker();
+				break;
+			case DriveType::MULTIPLE:
+				multiple_.~DriveChunkMultiple();
+				break;
+		}
+		type_ = DriveType::NONE;
+		none_ = width;
+	}
+
+	DriveChunk &operator=(DriveChunk const &other)
+	{
+		switch (other.type_)
+		{
+			case DriveType::NONE:
+				set_none(other.none_);
+				break;
+			case DriveType::CONSTANT:
+				*this = other.constant_;
+				break;
+			case DriveType::WIRE:
+				*this = other.wire_;
+				break;
+			case DriveType::PORT:
+				*this = other.port_;
+				break;
+			case DriveType::MARKER:
+				*this = other.marker_;
+				break;
+			case DriveType::MULTIPLE:
+				*this = other.multiple_;
+				break;
+		}
+		return *this;
+	}
+
+	DriveChunk &operator=(DriveChunk &&other)
+	{
+		switch (other.type_)
+		{
+			case DriveType::NONE:
+				set_none(other.none_);
+				break;
+			case DriveType::CONSTANT:
+				*this = std::move(other.constant_);
+				break;
+			case DriveType::WIRE:
+				*this = std::move(other.wire_);
+				break;
+			case DriveType::PORT:
+				*this = std::move(other.port_);
+				break;
+			case DriveType::MARKER:
+				*this = std::move(other.marker_);
+				break;
+			case DriveType::MULTIPLE:
+				*this = std::move(other.multiple_);
+				break;
+		}
+		return *this;
+	}
+
+	DriveChunk &operator=(Const const &constant)
+	{
+		set_none();
+		new (&constant_) Const(constant);
+		type_ = DriveType::CONSTANT;
+		return *this;
+	}
+
+	DriveChunk &operator=(Const &&constant)
+	{
+		set_none();
+		new (&constant_) Const(std::move(constant));
+		type_ = DriveType::CONSTANT;
+		return *this;
+	}
+
+	DriveChunk &operator=(DriveChunkWire const &wire)
+	{
+		set_none();
+		new (&wire_) DriveChunkWire(wire);
+		type_ = DriveType::WIRE;
+		return *this;
+	}
+
+	DriveChunk &operator=(DriveChunkWire &&wire)
+	{
+		set_none();
+		new (&wire_) DriveChunkWire(wire);
+		type_ = DriveType::WIRE;
+		return *this;
+	}
+
+	DriveChunk &operator=(DriveChunkPort const &port)
+	{
+		set_none();
+		new (&port_) DriveChunkPort(port);
+		type_ = DriveType::PORT;
+		return *this;
+	}
+
+	DriveChunk &operator=(DriveChunkPort &&port)
+	{
+		set_none();
+		new (&port_) DriveChunkPort(port);
+		type_ = DriveType::PORT;
+		return *this;
+	}
+
+	DriveChunk &operator=(DriveChunkMarker const &marker)
+	{
+		set_none();
+		new (&marker_) DriveChunkMarker(marker);
+		type_ = DriveType::MARKER;
+		return *this;
+	}
+
+	DriveChunk &operator=(DriveChunkMarker &&marker)
+	{
+		set_none();
+		new (&marker_) DriveChunkMarker(marker);
+		type_ = DriveType::MARKER;
+		return *this;
+	}
+
+	DriveChunk &operator=(DriveChunkMultiple const &multiple)
+	{
+		set_none(multiple.size());
+		if (multiple.multiple().empty())
+			return *this;
+		new (&multiple_) DriveChunkMultiple(multiple);
+		type_ = DriveType::MULTIPLE;
+		return *this;
+	}
+
+	DriveChunk &operator=(DriveChunkMultiple &&multiple)
+	{
+		set_none(multiple.size());
+		if (multiple.multiple().empty())
+			return *this;
+		new (&multiple_) DriveChunkMultiple(multiple);
+		type_ = DriveType::MULTIPLE;
+		return *this;
+	}
+
+	DriveChunk &operator=(DriveBit const &other)
+	{
+		switch (other.type())
+		{
+			case DriveType::NONE:
+				set_none(1);
+				break;
+			case DriveType::CONSTANT:
+				*this = Const(other.constant());
+				break;
+			case DriveType::WIRE:
+				*this = DriveChunkWire(other.wire());
+				break;
+			case DriveType::PORT:
+				*this = DriveChunkPort(other.port());
+				break;
+			case DriveType::MARKER:
+				*this = DriveChunkMarker(other.marker());
+				break;
+			case DriveType::MULTIPLE:
+				*this = DriveChunkMultiple(other.multiple());
+				break;
+		}
+		return *this;
+	}
+
+	bool can_append(DriveBit const &bit) const;
+	bool try_append(DriveBit const &bit);
+	bool try_append(DriveChunk const &chunk);
+
+	unsigned int hash() const
+	{
+		unsigned int inner;
+		switch (type_)
+		{
+			case DriveType::NONE:
+				inner = 0;
+				break;
+			case DriveType::CONSTANT:
+				inner = constant_.hash();
+				break;
+			case DriveType::WIRE:
+				inner = wire_.hash();
+				break;
+			case DriveType::PORT:
+				inner = port_.hash();
+				break;
+			case DriveType::MARKER:
+				inner = marker_.hash();
+				break;
+			case DriveType::MULTIPLE:
+				inner = multiple_.hash();
+				break;
+		}
+		return mkhash((unsigned int)type_, inner);
+	}
+
+	bool operator==(const DriveChunk &other) const
+	{
+		if (type_ != other.type_)
+			return false;
+
+		switch (type_)
+		{
+			case DriveType::NONE:
+				return true;
+			case DriveType::CONSTANT:
+				return constant_ == other.constant_;
+			case DriveType::WIRE:
+				return wire_ == other.wire_;
+			case DriveType::PORT:
+				return port_ == other.port_;
+			case DriveType::MARKER:
+				return marker_ == other.marker_;
+			case DriveType::MULTIPLE:
+				return multiple_ == other.multiple_;
+		}
+		log_assert(false);
+	}
+
+	bool operator!=(const DriveChunk &other) const
+	{
+		return !(*this == other);
+	}
+
+	bool operator<(const DriveChunk &other) const
+	{
+		if (type_ != other.type_)
+			return type_ < other.type_;
+		switch (type_)
+		{
+			case DriveType::NONE:
+				return false;
+			case DriveType::CONSTANT:
+				return constant_ < other.constant_;
+			case DriveType::WIRE:
+				return wire_ < other.wire_;
+			case DriveType::PORT:
+				return port_ < other.port_;
+			case DriveType::MARKER:
+				return marker_ < other.marker_;
+			case DriveType::MULTIPLE:
+				return multiple_ < other.multiple_;
+		}
+		log_assert(false);
+	}
+
+	DriveType type() const { return type_; }
+
+	bool is_none() const { return type_ == DriveType::NONE; }
+	bool is_constant() const { return type_ == DriveType::CONSTANT; }
+	bool is_wire() const { return type_ == DriveType::WIRE; }
+	bool is_port() const { return type_ == DriveType::PORT; }
+	bool is_marker() const { return type_ == DriveType::MARKER; }
+	bool is_multiple() const { return type_ == DriveType::MULTIPLE; }
+
+	Const &constant() { log_assert(is_constant()); return constant_; }
+	Const const &constant() const { log_assert(is_constant()); return constant_; }
+	DriveChunkWire &wire() { log_assert(is_wire()); return wire_; }
+	DriveChunkWire const &wire() const { log_assert(is_wire()); return wire_; }
+	DriveChunkPort &port() { log_assert(is_port()); return port_; }
+	DriveChunkPort const &port() const { log_assert(is_port()); return port_; }
+	DriveChunkMarker &marker() { log_assert(is_marker()); return marker_; }
+	DriveChunkMarker const &marker() const { log_assert(is_marker()); return marker_; }
+	DriveChunkMultiple &multiple() { log_assert(is_multiple()); return multiple_; }
+	DriveChunkMultiple const &multiple() const { log_assert(is_multiple()); return multiple_; }
+
+
+	int size() const
+	{
+		switch (type_)
+		{
+			case DriveType::NONE:
+				return none_;
+			case DriveType::CONSTANT:
+				return constant_.size();
+			case DriveType::WIRE:
+				return wire_.size();
+			case DriveType::PORT:
+				return port_.size();
+			case DriveType::MARKER:
+				return marker_.size();
+			case DriveType::MULTIPLE:
+				return multiple_.size();
+		}
+	}
+};
+
+struct DriveSpec
+{
+private:
+	int width_ = 0;
+	mutable std::vector<DriveChunk> chunks_;
+	mutable std::vector<DriveBit> bits_;
+	mutable unsigned int hash_ = 0;
+public:
+
+	inline bool packed() const {
+		return bits_.empty();
+	}
+
+	DriveSpec() {}
+
+	DriveSpec(DriveChunk const &chunk) { *this = chunk; }
+	DriveSpec(DriveChunkWire const &chunk) { *this = chunk; }
+	DriveSpec(DriveChunkPort const &chunk) { *this = chunk; }
+	DriveSpec(DriveChunkMarker const &chunk) { *this = chunk; }
+	DriveSpec(DriveChunkMultiple const &chunk) { *this = chunk; }
+
+	DriveSpec(DriveBit const &bit) { *this = bit; }
+	DriveSpec(DriveBitWire const &bit) { *this = bit; }
+	DriveSpec(DriveBitPort const &bit) { *this = bit; }
+	DriveSpec(DriveBitMarker const &bit) { *this = bit; }
+	DriveSpec(DriveBitMultiple const &bit) { *this = bit; }
+
+	DriveSpec(std::vector<DriveChunk> const &chunks) : chunks_(chunks) { compute_width(); }
+
+	DriveSpec(std::vector<DriveBit> const &bits)
+	{
+		for (auto const &bit : bits)
+			append(bit);
+	}
+
+	std::vector<DriveChunk> const &chunks() const { pack(); return chunks_; }
+	std::vector<DriveBit> const &bits() const { unpack(); return bits_; }
+
+	int size() const { return width_; }
+
+	void append(DriveBit const &bit);
+
+	void append(DriveChunk const &chunk);
+
+	void pack() const;
+
+	void unpack() const;
+
+	DriveBit &operator[](int index)
+	{
+		log_assert(index >= 0 && index < size());
+		unpack();
+		return bits_[index];
+	}
+
+	const DriveBit &operator[](int index) const
+	{
+		log_assert(index >= 0 && index < size());
+		unpack();
+		return bits_[index];
+	}
+
+	void clear()
+	{
+		chunks_.clear();
+		bits_.clear();
+		width_ = 0;
+	}
+
+	DriveSpec &operator=(DriveChunk const &chunk)
+	{
+		chunks_.clear();
+		bits_.clear();
+		append(chunk);
+		return *this;
+	}
+
+	DriveSpec &operator=(DriveChunkWire const &chunk) { return *this = DriveChunk(chunk); }
+	DriveSpec &operator=(DriveChunkPort const &chunk) { return *this = DriveChunk(chunk); }
+	DriveSpec &operator=(DriveChunkMarker const &chunk) { return *this = DriveChunk(chunk); }
+	DriveSpec &operator=(DriveChunkMultiple const &chunk) { return *this = DriveChunk(chunk); }
+
+	DriveSpec &operator=(DriveBit const &bit)
+	{
+		chunks_.clear();
+		bits_.clear();
+		append(bit);
+		return *this;
+	}
+
+	DriveSpec &operator=(DriveBitWire const &bit) { return *this = DriveBit(bit); }
+	DriveSpec &operator=(DriveBitPort const &bit) { return *this = DriveBit(bit); }
+	DriveSpec &operator=(DriveBitMarker const &bit) { return *this = DriveBit(bit); }
+	DriveSpec &operator=(DriveBitMultiple const &bit) { return *this = DriveBit(bit); }
+
+	unsigned int hash() const {
+		if (hash_ != 0) return hash_;
+
+		pack();
+		hash_ = hash_ops<std::vector<DriveChunk>>().hash(chunks_);
+		hash_ |= (hash_ == 0);
+		return hash_;
+	}
+
+	bool operator==(DriveSpec const &other) const {
+		if (size() != other.size() || hash() != other.hash())
+			return false;
+		return chunks() == other.chunks();
+	}
+
+private:
+	void compute_width();
+};
+
+
+
+struct DriverMap
+{
+	CellTypes celltypes;
+
+	DriverMap() { celltypes.setup(); }
+	DriverMap(Design *design) { celltypes.setup(); celltypes.setup_design(design); }
+
+private:
+
+	// Internally we represent all DriveBits by mapping them to DriveBitIds
+	// which use less memory and are cheaper to compare.
+	struct DriveBitId
+	{
+		int id = -1;
+
+		DriveBitId() {};
+
+		DriveBitId(int id) : id(id) { }
+
+		bool operator==(const DriveBitId &other) const { return id == other.id; }
+		bool operator<(const DriveBitId &other) const { return id < other.id; }
+		unsigned int hash() const { return id; }
+	};
+	// Essentially a dict<DriveBitId, pool<DriveBitId>> but using less memory
+	// and fewer allocations
+	struct DriveBitGraph {
+		dict<DriveBitId, DriveBitId> first_edges;
+		dict<DriveBitId, DriveBitId> second_edges;
+		dict<DriveBitId, pool<DriveBitId>> more_edges;
+
+		void add_edge(DriveBitId src, DriveBitId dst);
+		DriveBitId pop_edge(DriveBitId src);
+		void clear(DriveBitId src);
+		bool contains(DriveBitId src);
+		int count(DriveBitId src);
+
+		DriveBitId at(DriveBitId src, int index);
+	};
+
+	// The following two maps maintain a sparse DriveBit to DriveBitId mapping.
+	// This saves a lot of memory compared to a `dict<DriveBit, DriveBitId>` or
+	// `idict<DriveBit>`.
+
+	// Maps wires to the first DriveBitId of the consecutive range used for
+	// that wire.
+	dict<Wire *, DriveBitId> wire_offsets;
+
+	// Maps cell ports to a the first DriveBitId of the consecutive range used
+	// for that cell port.
+	dict<pair<Cell *, IdString>, DriveBitId> port_offsets;
+
+	// For the inverse map that maps DriveBitIds back to DriveBits we use a
+	// sorted map containing only the first DriveBit for each wire and cell
+	// port.
+	std::map<DriveBitId, DriveBit> drive_bits;
+
+	// As a memory optimization for gate level net lists we store single-bit
+	// wires and cell ports in a `dict` which requires less memory and fewer
+	// allocations than `std::map` but doesn't support the kind of lookups we
+	// need for a sparse coarse grained mapping.
+	dict<DriveBitId, DriveBit> isolated_drive_bits;
+
+	// Used for allocating DriveBitIds, none and constant states use a fixewd
+	// mapping to the first few ids, which we need to skip.
+	int next_offset = 1 + (int)State::Sm;
+
+	// Union-Find over directly connected bits that share the same single
+	// driver or are undriven. We never merge connections between drivers
+	// and/or kept wires.
+	mfp<DriveBitId> same_driver;
+
+	// For each bit, store a set of connected driver bits for which the
+	// explicit connection should be preserved and the driving direction is
+	// locally unambiguous (one side only drives or requires a driven value).
+	DriveBitGraph connected_drivers;
+
+	// For each bit, store a set of connected driver bits for which the
+	// explicit connection should be preserved and the driving direction is
+	// locally ambiguous. Every such ambiguous connection is also present in
+	// the reverse direction and has to be resolved when querying drivers.
+	DriveBitGraph connected_undirected;
+
+	// Subset of `connected_undirected` for caching the resolved driving
+	// direction. In case multiple drivers are present this can still contain
+	// both orientations of a single connection, but for a single driver only
+	// one will be present.
+	DriveBitGraph connected_oriented;
+
+	// Stores for which bits we already resolved the orientation (cached in
+	// `connected_oriented`).
+	pool<DriveBitId> oriented_present;
+
+
+	enum class BitMode {
+		NONE = 0, // Not driven, no need to keep wire
+		DRIVEN = 1, // Not driven, uses a value driven elsewhere
+		DRIVEN_UNIQUE = 2, // Uses a value driven elsewhere, has at most one direct connection
+		KEEP = 3, // Wire that should be kept
+		TRISTATE = 4, // Can drive a value but can also use a value driven elsewhere
+		DRIVER = 5, // Drives a value
+	};
+
+	BitMode bit_mode(DriveBit const &bit);
+	DriveBitId id_from_drive_bit(DriveBit const &bit);
+	DriveBit drive_bit_from_id(DriveBitId id);
+
+	void connect_directed_merge(DriveBitId driven_id, DriveBitId driver_id);
+	void connect_directed_buffer(DriveBitId driven_id, DriveBitId driver_id);
+	void connect_undirected(DriveBitId a_id, DriveBitId b_id);
+
+public:
+
+	void add(Module *module);
+
+	// Add a single bit connection to the driver map.
+	void add(DriveBit const &a, DriveBit const &b);
+
+	template<typename T>
+	static constexpr bool is_sig_type() {
+		return
+			std::is_same<T, SigSpec>::value ||
+			std::is_same<T, SigChunk>::value ||
+			std::is_same<T, DriveSpec>::value ||
+			std::is_same<T, DriveChunk>::value ||
+			std::is_same<T, DriveChunkPort>::value ||
+			std::is_same<T, DriveChunkWire>::value ||
+			std::is_same<T, Const>::value;
+	}
+
+	// We use the enable_if to produce better compiler errors when unsupported
+	// types are used
+	template<typename T, typename U>
+	typename std::enable_if<is_sig_type<T>() && is_sig_type<U>()>::type
+	add(T const &a, U const &b)
+	{
+		log_assert(a.size() == b.size());
+		for (int i = 0; i != GetSize(a); ++i)
+			add(DriveBit(a[i]), DriveBit(b[i]));
+	}
+
+
+	// Specialized version that avoids unpacking
+	void add(SigSpec const &a, SigSpec const &b);
+
+private:
+	void add_port(Cell *cell, IdString const &port, SigSpec const &b);
+
+	// Only used a local variables in `orient_undirected`, always cleared, only
+	// stored to reduce allocations.
+	pool<DriveBitId> orient_undirected_seen;
+	pool<DriveBitId> orient_undirected_drivers;
+	dict<DriveBitId, int> orient_undirected_distance;
+
+	void orient_undirected(DriveBitId id);
+
+public:
+	DriveBit operator()(DriveBit const &bit);
+
+	DriveSpec operator()(DriveSpec spec);
+
+private:
+	bool keep_wire(Wire *wire) {
+		// TODO configurable
+		return wire->has_attribute(ID(keep));
+	}
+};
+
+YOSYS_NAMESPACE_END
+
+#endif

From 68c3a47945972a685f65620eef73f10c86b87741 Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Mon, 15 Apr 2024 14:14:50 +0200
Subject: [PATCH 362/499] WIP temporary drivertools example

---
 passes/cmds/Makefile.inc  |   1 +
 passes/cmds/example_dt.cc | 140 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 141 insertions(+)
 create mode 100644 passes/cmds/example_dt.cc

diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index 33e3ae1bc5a..0918a07df0f 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -49,3 +49,4 @@ OBJS += passes/cmds/xprop.o
 OBJS += passes/cmds/dft_tag.o
 OBJS += passes/cmds/future.o
 OBJS += passes/cmds/box_derive.o
+OBJS += passes/cmds/example_dt.o
diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc
new file mode 100644
index 00000000000..de84fa3cda8
--- /dev/null
+++ b/passes/cmds/example_dt.cc
@@ -0,0 +1,140 @@
+#include "kernel/yosys.h"
+#include "kernel/drivertools.h"
+#include "kernel/topo_scc.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+
+
+
+struct ExampleWorker
+{
+	DriverMap dm;
+	Module *module;
+
+	ExampleWorker(Module *module) : module(module) {
+		dm.celltypes.setup();
+	}
+};
+
+struct ExampleDtPass : public Pass
+{
+	ExampleDtPass() : Pass("example_dt", "drivertools example") {}
+
+    void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+    }
+
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		size_t argidx = 1;
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules()) {
+			ExampleWorker worker(module);
+			DriverMap dm;
+
+			dm.add(module);
+
+			idict<DriveSpec> queue;
+			idict<Cell *> cells;
+
+			IntGraph edges;
+
+
+			for (auto cell : module->cells()) {
+				if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($check)))
+					queue(DriveBitMarker(cells(cell), 0));
+			}
+
+			for (auto wire : module->wires()) {
+				if (!wire->port_output)
+					continue;
+				queue(DriveChunk(DriveChunkWire(wire, 0, wire->width)));
+			}
+
+#define emit log
+// #define emit(X...) do {} while (false)
+
+			for (int i = 0; i != GetSize(queue); ++i)
+			{
+				emit("n%d: ", i);
+				DriveSpec spec = queue[i];
+				if (spec.chunks().size() > 1) {
+					emit("concat %s <-\n", log_signal(spec));
+					for (auto const &chunk : spec.chunks()) {
+						emit("  * %s\n", log_signal(chunk));
+						edges.add_edge(i, queue(chunk));
+					}
+				} else if (spec.chunks().size() == 1) {
+					DriveChunk chunk = spec.chunks()[0];
+					if (chunk.is_wire()) {
+						DriveChunkWire wire_chunk = chunk.wire();
+						if (wire_chunk.is_whole()) {
+							if (wire_chunk.wire->port_input) {
+								emit("input %s\n", log_signal(spec));
+							} else {
+								DriveSpec driver = dm(DriveSpec(wire_chunk));
+								edges.add_edge(i, queue(driver));
+								emit("wire driver %s <- %s\n", log_signal(spec), log_signal(driver));
+							}
+						} else {
+							DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.width);
+							edges.add_edge(i, queue(whole_wire));
+							emit("wire slice %s <- %s\n", log_signal(spec), log_signal(DriveSpec(whole_wire)));
+						}
+					} else if (chunk.is_port()) {
+						DriveChunkPort port_chunk = chunk.port();
+						if (port_chunk.is_whole()) {
+							if (dm.celltypes.cell_output(port_chunk.cell->type, port_chunk.port)) {
+								int cell_marker = queue(DriveBitMarker(cells(port_chunk.cell), 0));
+								if (!port_chunk.cell->type.in(ID($dff), ID($ff)))
+									edges.add_edge(i, cell_marker);
+								emit("cell output %s %s\n", log_id(port_chunk.cell), log_id(port_chunk.port));
+							} else {
+								DriveSpec driver = dm(DriveSpec(port_chunk));
+								edges.add_edge(i, queue(driver));
+								emit("cell port driver %s <- %s\n", log_signal(spec), log_signal(driver));
+							}
+
+						} else {
+							DriveChunkPort whole_port(port_chunk.cell, port_chunk.port, 0, GetSize(port_chunk.cell->connections().at(port_chunk.port)));
+							edges.add_edge(i, queue(whole_port));
+							emit("port slice %s <- %s\n", log_signal(spec), log_signal(DriveSpec(whole_port)));
+						}
+					} else if (chunk.is_constant()) {
+						emit("constant %s <- %s\n", log_signal(spec), log_const(chunk.constant()));
+					} else if (chunk.is_marker()) {
+						Cell *cell = cells[chunk.marker().marker];
+						emit("cell %s %s\n", log_id(cell->type), log_id(cell));
+						for (auto const &conn : cell->connections()) {
+							if (!dm.celltypes.cell_input(cell->type, conn.first))
+								continue;
+							emit("  * %s <- %s\n", log_id(conn.first), log_signal(conn.second));
+							edges.add_edge(i, queue(DriveChunkPort(cell, conn)));
+						}
+					} else {
+						log_abort();
+					}
+				} else {
+					log_abort();
+				}
+			}
+
+			topo_sorted_sccs(edges, [&](int *begin, int *end) {
+				emit("scc:");
+				for (int *i = begin; i != end; ++i)
+					emit(" n%d", *i);
+				emit("\n");
+			});
+
+		}
+		log("Plugin test passed!\n");
+	}
+} ExampleDtPass;
+
+PRIVATE_NAMESPACE_END

From f29422f745a534d09cb0917a8587639ac5b08e10 Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Thu, 11 Apr 2024 13:47:14 +0200
Subject: [PATCH 363/499] topo_scc: Add sources_first option

---
 kernel/topo_scc.h | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/kernel/topo_scc.h b/kernel/topo_scc.h
index 0ae0e696b47..89df8928aa2 100644
--- a/kernel/topo_scc.h
+++ b/kernel/topo_scc.h
@@ -194,7 +194,7 @@ class IntGraph {
 };
 
 template<typename G, typename ComponentCallback>
-void topo_sorted_sccs(G &graph, ComponentCallback component)
+void topo_sorted_sccs(G &graph, ComponentCallback component, bool sources_first = false)
 {
     typedef typename G::node_enumerator node_enumerator;
     typedef typename G::successor_enumerator successor_enumerator;
@@ -217,6 +217,23 @@ void topo_sorted_sccs(G &graph, ComponentCallback component)
 
     node_enumerator nodes = graph.enumerate_nodes();
 
+    if (sources_first) {
+        while (!nodes.finished()) {
+            node_type node = nodes.next();
+            successor_enumerator successors = graph.enumerate_successors(node);
+            if (successors.finished())
+            {
+                graph.dfs_index(node) = next_index;
+                next_index++;
+                component_stack.push_back(node);
+                component(component_stack.data(), component_stack.data() + 1);
+                component_stack.clear();
+                graph.dfs_index(node) = INT_MAX;
+            }
+        }
+        nodes = graph.enumerate_nodes();
+    }
+
     // iterate over all nodes to ensure we process the whole graph
     while (!nodes.finished()) {
         node_type node = nodes.next();

From d4e3daa9d0037e2397dc74e3862b5b41c67716e5 Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Thu, 11 Apr 2024 13:48:25 +0200
Subject: [PATCH 364/499] ComputeGraph datatype for the upcoming functional
 backend

---
 kernel/functional.h       | 369 ++++++++++++++++++++++++++++++++++++++
 passes/cmds/example_dt.cc | 178 ++++++++++++++----
 2 files changed, 515 insertions(+), 32 deletions(-)
 create mode 100644 kernel/functional.h

diff --git a/kernel/functional.h b/kernel/functional.h
new file mode 100644
index 00000000000..e5ee8824099
--- /dev/null
+++ b/kernel/functional.h
@@ -0,0 +1,369 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Jannis Harder <jix@yosyshq.com> <me@jix.one>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef FUNCTIONAL_H
+#define FUNCTIONAL_H
+
+#include <tuple>
+#include "kernel/yosys.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+template<
+    typename Fn, // Function type (deduplicated across whole graph)
+    typename Attr = std::tuple<>, // Call attributes (present in every node)
+    typename SparseAttr = std::tuple<>, // Sparse call attributes (optional per node)
+    typename Key = std::tuple<> // Stable keys to refer to nodes
+>
+struct ComputeGraph
+{
+    struct Ref;
+private:
+
+    // Functions are deduplicated by assigning unique ids
+    idict<Fn> functions;
+
+    struct Node {
+        int fn_index;
+        int arg_offset;
+        int arg_count;
+        Attr attr;
+
+        Node(int fn_index, Attr &&attr, int arg_offset, int arg_count = 0)
+            : fn_index(fn_index), arg_offset(arg_offset), arg_count(arg_count), attr(std::move(attr)) {}
+
+        Node(int fn_index, Attr const &attr, int arg_offset, int arg_count = 0)
+            : fn_index(fn_index), arg_offset(arg_offset), arg_count(arg_count), attr(attr) {}
+    };
+
+
+    std::vector<Node> nodes;
+    std::vector<int> args;
+    dict<Key, int> keys_;
+    dict<int, SparseAttr> sparse_attrs;
+
+public:
+    template<typename Graph>
+    struct BaseRef
+    {
+    protected:
+        friend struct ComputeGraph;
+        Graph *graph_;
+        int index_;
+        BaseRef(Graph *graph, int index) : graph_(graph), index_(index) {
+            log_assert(index_ >= 0);
+            check();
+        }
+
+        void check() const { log_assert(index_ < graph_->size()); }
+
+        Node const &deref() const { check(); return graph_->nodes[index_]; }
+
+    public:
+        ComputeGraph const &graph() const { return graph_; }
+        int index() const { return index_; }
+
+        int size() const { return deref().arg_count; }
+
+        BaseRef arg(int n) const
+        {
+            Node const &node = deref();
+            log_assert(n >= 0 && n < node.arg_count);
+            return BaseRef(graph_, graph_->args[node.arg_offset + n]);
+        }
+
+        std::vector<int>::const_iterator arg_indices_cbegin() const
+        {
+            Node const &node = deref();
+            return graph_->args.cbegin() + node.arg_offset;
+        }
+
+        std::vector<int>::const_iterator arg_indices_cend() const
+        {
+            Node const &node = deref();
+            return graph_->args.cbegin() + node.arg_offset + node.arg_count;
+        }
+
+        Fn const &function() const { return graph_->functions[deref().fn_index]; }
+        Attr const &attr() const { return deref().attr; }
+
+        bool has_sparse_attr() const { return graph_->sparse_attrs.count(index_); }
+
+        SparseAttr const &sparse_attr() const
+        {
+            auto found = graph_->sparse_attrs.find(index_);
+            log_assert(found != graph_->sparse_attrs.end());
+            return *found;
+        }
+    };
+
+    using ConstRef = BaseRef<ComputeGraph const>;
+
+    struct Ref : public BaseRef<ComputeGraph>
+    {
+    private:
+        friend struct ComputeGraph;
+        Ref(ComputeGraph *graph, int index) : BaseRef<ComputeGraph>(graph, index) {}
+        Node &deref() const { this->check(); return this->graph_->nodes[this->index_]; }
+
+    public:
+        void set_function(Fn const &function) const
+        {
+            deref().fn_index = this->graph_->functions(function);
+        }
+
+        Attr &attr() const { return deref().attr; }
+
+        void append_arg(ConstRef arg) const
+        {
+            log_assert(arg.graph_ == this->graph_);
+            append_arg(arg.index());
+        }
+
+        void append_arg(int arg) const
+        {
+            log_assert(arg >= 0 && arg < this->graph_->size());
+            Node &node = deref();
+            if (node.arg_offset + node.arg_count != GetSize(this->graph_->args))
+                move_args(node);
+            this->graph_->args.push_back(arg);
+            node.arg_count++;
+        }
+
+        operator ConstRef() const
+        {
+            return ConstRef(this->graph_, this->index_);
+        }
+
+        SparseAttr &sparse_attr() const
+        {
+            return this->graph_->sparse_attrs[this->index_];
+        }
+
+        void clear_sparse_attr() const
+        {
+            this->graph_->sparse_attrs.erase(this->index_);
+        }
+
+        void assign_key(Key const &key) const
+        {
+            this->graph_->keys_.emplace(key, this->index_);
+        }
+
+    private:
+        void move_args(Node &node) const
+        {
+            auto &args = this->graph_->args;
+            int old_offset = node.arg_offset;
+            node.arg_offset = GetSize(args);
+            for (int i = 0; i != node.arg_count; ++i)
+                args.push_back(args[old_offset + i]);
+        }
+
+    };
+
+    bool has_key(Key const &key) const
+    {
+        return keys_.count(key);
+    }
+
+    dict<Key, int> const &keys() const
+    {
+        return keys_;
+    }
+
+    ConstRef operator()(Key const &key) const
+    {
+        auto it = keys_.find(key);
+        log_assert(it != keys_.end());
+        return (*this)[it->second];
+    }
+
+    Ref operator()(Key const &key)
+    {
+        auto it = keys_.find(key);
+        log_assert(it != keys_.end());
+        return (*this)[it->second];
+    }
+
+    int size() const { return GetSize(nodes); }
+
+    ConstRef operator[](int index) const { return ConstRef(this, index); }
+    Ref operator[](int index) { return Ref(this, index); }
+
+    Ref add(Fn const &function, Attr &&attr)
+    {
+        int index = GetSize(nodes);
+        int fn_index = functions(function);
+        nodes.emplace_back(fn_index, std::move(attr), GetSize(args));
+        return Ref(this, index);
+    }
+
+    Ref add(Fn const &function, Attr const &attr)
+    {
+        int index = GetSize(nodes);
+        int fn_index = functions(function);
+        nodes.emplace_back(fn_index, attr,  GetSize(args));
+        return Ref(this, index);
+    }
+
+    template<typename T>
+    Ref add(Fn const &function, Attr const &attr, T const &args)
+    {
+        Ref added = add(function, attr);
+        for (auto arg : args)
+            added.append_arg(arg);
+        return added;
+    }
+
+    template<typename T>
+    Ref add(Fn const &function, Attr &&attr, T const &args)
+    {
+        Ref added = add(function, std::move(attr));
+        for (auto arg : args)
+            added.append_arg(arg);
+        return added;
+    }
+
+    template<typename T>
+    Ref add(Fn const &function, Attr const &attr, T begin, T end)
+    {
+        Ref added = add(function, attr);
+        for (; begin != end; ++begin)
+            added.append_arg(*begin);
+        return added;
+    }
+
+    void permute(std::vector<int> const &perm)
+    {
+        log_assert(perm.size() <= nodes.size());
+        std::vector<int> inv_perm;
+        inv_perm.resize(nodes.size(), -1);
+        for (int i = 0; i < GetSize(perm); ++i)
+        {
+            int j = perm[i];
+            log_assert(j >= 0 && j < GetSize(perm));
+            log_assert(inv_perm[j] == -1);
+            inv_perm[j] = i;
+        }
+        permute(perm, inv_perm);
+    }
+
+    void permute(std::vector<int> const &perm, std::vector<int> const &inv_perm)
+    {
+        log_assert(inv_perm.size() == nodes.size());
+        std::vector<Node> new_nodes;
+        new_nodes.reserve(perm.size());
+        dict<int, SparseAttr> new_sparse_attrs;
+        for (int i : perm)
+        {
+            int j = GetSize(new_nodes);
+            new_nodes.emplace_back(std::move(nodes[i]));
+            auto found = sparse_attrs.find(i);
+            if (found != sparse_attrs.end())
+                new_sparse_attrs.emplace(j, std::move(found->second));
+        }
+
+        std::swap(nodes, new_nodes);
+        std::swap(sparse_attrs, new_sparse_attrs);
+
+        for (int &arg : args)
+        {
+            log_assert(arg < GetSize(inv_perm));
+            arg = inv_perm[arg];
+        }
+
+        for (auto &key : keys_)
+        {
+            log_assert(key.second < GetSize(inv_perm));
+            key.second = inv_perm[key.second];
+        }
+    }
+
+    struct SccAdaptor
+    {
+    private:
+        ComputeGraph const &graph_;
+        std::vector<int> indices_;
+    public:
+        SccAdaptor(ComputeGraph const &graph) : graph_(graph)
+        {
+            indices_.resize(graph.size(), -1);
+        }
+
+
+        typedef int node_type;
+
+        struct node_enumerator {
+        private:
+            friend struct SccAdaptor;
+            int current, end;
+            node_enumerator(int current, int end) : current(current), end(end) {}
+
+        public:
+
+            bool finished() const { return current == end; }
+            node_type next() {
+                log_assert(!finished());
+                node_type result = current;
+                ++current;
+                return result;
+            }
+        };
+
+        node_enumerator enumerate_nodes() {
+            return node_enumerator(0, GetSize(indices_));
+        }
+
+
+        struct successor_enumerator {
+        private:
+            friend struct SccAdaptor;
+            std::vector<int>::const_iterator current, end;
+            successor_enumerator(std::vector<int>::const_iterator current, std::vector<int>::const_iterator end) :
+                current(current), end(end) {}
+
+        public:
+            bool finished() const { return current == end; }
+            node_type next() {
+                log_assert(!finished());
+                node_type result = *current;
+                ++current;
+                return result;
+            }
+        };
+
+        successor_enumerator enumerate_successors(int index) const {
+            auto const &ref = graph_[index];
+            return successor_enumerator(ref.arg_indices_cbegin(), ref.arg_indices_cend());
+        }
+
+        int &dfs_index(node_type const &node) { return indices_[node]; }
+
+        std::vector<int> const &dfs_indices() { return indices_; }
+    };
+
+};
+
+
+
+YOSYS_NAMESPACE_END
+
+
+#endif
diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc
index de84fa3cda8..dec554d6c71 100644
--- a/passes/cmds/example_dt.cc
+++ b/passes/cmds/example_dt.cc
@@ -1,6 +1,7 @@
 #include "kernel/yosys.h"
 #include "kernel/drivertools.h"
 #include "kernel/topo_scc.h"
+#include "kernel/functional.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
@@ -38,86 +39,137 @@ struct ExampleDtPass : public Pass
 			ExampleWorker worker(module);
 			DriverMap dm;
 
+			struct ExampleFn {
+				IdString name;
+				dict<IdString, Const> parameters;
+
+				ExampleFn(IdString name) : name(name) {}
+				ExampleFn(IdString name, dict<IdString, Const> parameters) : name(name), parameters(parameters) {}
+
+				bool operator==(ExampleFn const &other) const {
+					return name == other.name && parameters == other.parameters;
+				}
+
+				unsigned int hash() const {
+					return mkhash(name.hash(), parameters.hash());
+				}
+			};
+
+			typedef ComputeGraph<ExampleFn, int, IdString, IdString> ExampleGraph;
+
+			ExampleGraph compute_graph;
+
+
 			dm.add(module);
 
 			idict<DriveSpec> queue;
 			idict<Cell *> cells;
 
 			IntGraph edges;
+			std::vector<int> graph_nodes;
 
+			auto enqueue = [&](DriveSpec const &spec) {
+				int index = queue(spec);
+				if (index == GetSize(graph_nodes))
+					graph_nodes.emplace_back(compute_graph.add(ID($pending), index).index());
+				//if (index >= GetSize(graph_nodes))
+				return compute_graph[graph_nodes[index]];
+			};
 
 			for (auto cell : module->cells()) {
 				if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($check)))
-					queue(DriveBitMarker(cells(cell), 0));
+					enqueue(DriveBitMarker(cells(cell), 0));
 			}
 
 			for (auto wire : module->wires()) {
 				if (!wire->port_output)
 					continue;
-				queue(DriveChunk(DriveChunkWire(wire, 0, wire->width)));
+				enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width))).assign_key(wire->name);
 			}
 
-#define emit log
-// #define emit(X...) do {} while (false)
-
 			for (int i = 0; i != GetSize(queue); ++i)
 			{
-				emit("n%d: ", i);
 				DriveSpec spec = queue[i];
+				ExampleGraph::Ref node = compute_graph[i];
+
 				if (spec.chunks().size() > 1) {
-					emit("concat %s <-\n", log_signal(spec));
+					node.set_function(ID($$concat));
+
 					for (auto const &chunk : spec.chunks()) {
-						emit("  * %s\n", log_signal(chunk));
-						edges.add_edge(i, queue(chunk));
+						node.append_arg(enqueue(chunk));
 					}
 				} else if (spec.chunks().size() == 1) {
 					DriveChunk chunk = spec.chunks()[0];
 					if (chunk.is_wire()) {
 						DriveChunkWire wire_chunk = chunk.wire();
 						if (wire_chunk.is_whole()) {
+							node.sparse_attr() = wire_chunk.wire->name;
 							if (wire_chunk.wire->port_input) {
-								emit("input %s\n", log_signal(spec));
+								node.set_function(ExampleFn(ID($$input), {{wire_chunk.wire->name, {}}}));
 							} else {
 								DriveSpec driver = dm(DriveSpec(wire_chunk));
-								edges.add_edge(i, queue(driver));
-								emit("wire driver %s <- %s\n", log_signal(spec), log_signal(driver));
+								node.set_function(ID($$buf));
+
+								node.append_arg(enqueue(driver));
 							}
 						} else {
 							DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.width);
-							edges.add_edge(i, queue(whole_wire));
-							emit("wire slice %s <- %s\n", log_signal(spec), log_signal(DriveSpec(whole_wire)));
+							node.set_function(ExampleFn(ID($$slice), {{ID(offset), wire_chunk.offset}, {ID(width), wire_chunk.width}}));
+							node.append_arg(enqueue(whole_wire));
 						}
 					} else if (chunk.is_port()) {
 						DriveChunkPort port_chunk = chunk.port();
 						if (port_chunk.is_whole()) {
 							if (dm.celltypes.cell_output(port_chunk.cell->type, port_chunk.port)) {
-								int cell_marker = queue(DriveBitMarker(cells(port_chunk.cell), 0));
-								if (!port_chunk.cell->type.in(ID($dff), ID($ff)))
-									edges.add_edge(i, cell_marker);
-								emit("cell output %s %s\n", log_id(port_chunk.cell), log_id(port_chunk.port));
+								if (port_chunk.cell->type.in(ID($dff), ID($ff)))
+								{
+									Cell *cell = port_chunk.cell;
+									node.set_function(ExampleFn(ID($$state), {{cell->name, {}}}));
+									for (auto const &conn : cell->connections()) {
+										if (!dm.celltypes.cell_input(cell->type, conn.first))
+											continue;
+										enqueue(DriveChunkPort(cell, conn)).assign_key(cell->name);
+									}
+								}
+								else
+								{
+									node.set_function(ExampleFn(ID($$cell_output), {{port_chunk.port, {}}}));
+									node.append_arg(enqueue(DriveBitMarker(cells(port_chunk.cell), 0)));
+								}
 							} else {
+								node.set_function(ID($$buf));
+
 								DriveSpec driver = dm(DriveSpec(port_chunk));
-								edges.add_edge(i, queue(driver));
-								emit("cell port driver %s <- %s\n", log_signal(spec), log_signal(driver));
+								node.append_arg(enqueue(driver));
 							}
 
 						} else {
 							DriveChunkPort whole_port(port_chunk.cell, port_chunk.port, 0, GetSize(port_chunk.cell->connections().at(port_chunk.port)));
-							edges.add_edge(i, queue(whole_port));
-							emit("port slice %s <- %s\n", log_signal(spec), log_signal(DriveSpec(whole_port)));
+							node.set_function(ID($$buf));
+							node.append_arg(enqueue(whole_port));
 						}
 					} else if (chunk.is_constant()) {
-						emit("constant %s <- %s\n", log_signal(spec), log_const(chunk.constant()));
+						node.set_function(ExampleFn(ID($$const), {{ID(value), chunk.constant()}}));
+
+					} else if (chunk.is_multiple()) {
+						node.set_function(ID($$multi));
+						for (auto const &driver : chunk.multiple().multiple())
+							node.append_arg(enqueue(driver));
 					} else if (chunk.is_marker()) {
 						Cell *cell = cells[chunk.marker().marker];
-						emit("cell %s %s\n", log_id(cell->type), log_id(cell));
+
+						node.set_function(ExampleFn(cell->type, cell->parameters));
 						for (auto const &conn : cell->connections()) {
 							if (!dm.celltypes.cell_input(cell->type, conn.first))
 								continue;
-							emit("  * %s <- %s\n", log_id(conn.first), log_signal(conn.second));
-							edges.add_edge(i, queue(DriveChunkPort(cell, conn)));
+
+							node.append_arg(enqueue(DriveChunkPort(cell, conn)));
 						}
+					} else if (chunk.is_none()) {
+						node.set_function(ID($$undriven));
+
 					} else {
+						log_error("unhandled drivespec: %s\n", log_signal(chunk));
 						log_abort();
 					}
 				} else {
@@ -125,13 +177,75 @@ struct ExampleDtPass : public Pass
 				}
 			}
 
-			topo_sorted_sccs(edges, [&](int *begin, int *end) {
-				emit("scc:");
-				for (int *i = begin; i != end; ++i)
-					emit(" n%d", *i);
-				emit("\n");
-			});
 
+			// Perform topo sort and detect SCCs
+			ExampleGraph::SccAdaptor compute_graph_scc(compute_graph);
+
+
+			std::vector<int> perm;
+			topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) {
+				perm.insert(perm.end(), begin, end);
+				if (end > begin + 1)
+				{
+					log_warning("SCC:");
+					for (int *i = begin; i != end; ++i)
+						log(" %d", *i);
+					log("\n");
+				}
+			}, /* sources_first */ true);
+			compute_graph.permute(perm);
+
+
+			// Forward $$buf unless we have a name in the sparse attribute
+			std::vector<int> alias;
+			perm.clear();
+
+			for (int i = 0; i < compute_graph.size(); ++i)
+			{
+				if (compute_graph[i].function().name == ID($$buf) && !compute_graph[i].has_sparse_attr() && compute_graph[i].arg(0).index() < i)
+				{
+
+					alias.push_back(alias[compute_graph[i].arg(0).index()]);
+				}
+				else
+				{
+					alias.push_back(GetSize(perm));
+					perm.push_back(i);
+				}
+			}
+			compute_graph.permute(perm, alias);
+
+			// Dump the compute graph
+			for (int i = 0; i < compute_graph.size(); ++i)
+			{
+				auto ref = compute_graph[i];
+				log("n%d ", i);
+				log("%s", log_id(ref.function().name));
+				for (auto const &param : ref.function().parameters)
+				{
+					if (param.second.empty())
+						log("[%s]", log_id(param.first));
+					else
+						log("[%s=%s]", log_id(param.first), log_const(param.second));
+				}
+				log("(");
+
+				for (int i = 0, end = ref.size(); i != end; ++i)
+				{
+					if (i > 0)
+						log(", ");
+					log("n%d", ref.arg(i).index());
+				}
+				log(")\n");
+				if (ref.has_sparse_attr())
+					log("// wire %s\n", log_id(ref.sparse_attr()));
+				log("// was #%d %s\n", ref.attr(), log_signal(queue[ref.attr()]));
+			}
+
+			for (auto const &key : compute_graph.keys())
+			{
+				log("return %d as %s \n", key.second, log_id(key.first));
+			}
 		}
 		log("Plugin test passed!\n");
 	}

From d90268f6104d8b88294629c636ec0ab979785c44 Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Wed, 17 Apr 2024 14:52:36 +0200
Subject: [PATCH 365/499] fixup! drivertools: Utility code for indexing and
 traversing signal drivers

---
 kernel/drivertools.cc | 23 +++++++++++++----------
 kernel/drivertools.h  |  1 +
 2 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/kernel/drivertools.cc b/kernel/drivertools.cc
index 499a9399c46..286c913a246 100644
--- a/kernel/drivertools.cc
+++ b/kernel/drivertools.cc
@@ -499,7 +499,7 @@ int DriverMap::DriveBitGraph::count(DriveBitId src)
 	auto found = more_edges.find(src);
 	if (found == more_edges.end())
 		return 2;
-	return GetSize(found->second);
+	return GetSize(found->second) + 2;
 }
 
 DriverMap::DriveBitId DriverMap::DriveBitGraph::at(DriveBitId src, int index)
@@ -688,7 +688,7 @@ void DriverMap::add(DriveBit const &a, DriveBit const &b)
 	// and use the other end as representative bit.
 	else if (a_mode == BitMode::DRIVEN_UNIQUE && !(b_mode == BitMode::DRIVEN_UNIQUE || b_mode == BitMode::DRIVEN))
 		connect_directed_buffer(a_id, b_id);
-	else if (b_mode == BitMode::DRIVEN_UNIQUE && !(b_mode == BitMode::DRIVEN_UNIQUE || b_mode == BitMode::DRIVEN))
+	else if (b_mode == BitMode::DRIVEN_UNIQUE && !(a_mode == BitMode::DRIVEN_UNIQUE || a_mode == BitMode::DRIVEN))
 		connect_directed_buffer(b_id, a_id);
 	// If either bit only drives a value, store a directed connection from
 	// it to the other bit.
@@ -827,15 +827,18 @@ DriveBit DriverMap::operator()(DriveBit const &bit)
 
 	DriveBitId bit_id = id_from_drive_bit(bit);
 
-	bit_id = same_driver.find(bit_id);
+	DriveBitId bit_repr_id = same_driver.find(bit_id);
 
-	DriveBit bit_repr = drive_bit_from_id(bit_id);
+	DriveBit bit_repr = drive_bit_from_id(bit_repr_id);
 
 	BitMode mode = bit_mode(bit_repr);
 
-	int implicit_driver_count = connected_drivers.count(bit_id);
-	if (connected_undirected.contains(bit_id) && !oriented_present.count(bit_id))
-		orient_undirected(bit_id);
+	if (mode == BitMode::KEEP && bit_repr_id != bit_id)
+		return bit_repr;
+
+	int implicit_driver_count = connected_drivers.count(bit_repr_id);
+	if (connected_undirected.contains(bit_repr_id) && !oriented_present.count(bit_repr_id))
+		orient_undirected(bit_repr_id);
 
 	DriveBit driver;
 
@@ -843,11 +846,11 @@ DriveBit DriverMap::operator()(DriveBit const &bit)
 		driver = bit_repr;
 
 	for (int i = 0; i != implicit_driver_count; ++i)
-		driver.merge(drive_bit_from_id(connected_drivers.at(bit_id, i)));
+		driver.merge(drive_bit_from_id(connected_drivers.at(bit_repr_id, i)));
 
-	int oriented_driver_count = connected_oriented.count(bit_id);
+	int oriented_driver_count = connected_oriented.count(bit_repr_id);
 	for (int i = 0; i != oriented_driver_count; ++i)
-		driver.merge(drive_bit_from_id(connected_oriented.at(bit_id, i)));
+		driver.merge(drive_bit_from_id(connected_oriented.at(bit_repr_id, i)));
 
 	return driver;
 }
diff --git a/kernel/drivertools.h b/kernel/drivertools.h
index b440afddaa2..1cb835df2cc 100644
--- a/kernel/drivertools.h
+++ b/kernel/drivertools.h
@@ -1165,6 +1165,7 @@ struct DriverMap
 		DriveBitId(int id) : id(id) { }
 
 		bool operator==(const DriveBitId &other) const { return id == other.id; }
+		bool operator!=(const DriveBitId &other) const { return id != other.id; }
 		bool operator<(const DriveBitId &other) const { return id < other.id; }
 		unsigned int hash() const { return id; }
 	};

From dd5ec84a26725a085038a3afcc1e211ae7cdcd5c Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Wed, 1 May 2024 11:47:16 +0100
Subject: [PATCH 366/499] fix bugs in drivertools

---
 kernel/drivertools.cc     | 4 ++--
 passes/cmds/example_dt.cc | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/kernel/drivertools.cc b/kernel/drivertools.cc
index 286c913a246..9627a467015 100644
--- a/kernel/drivertools.cc
+++ b/kernel/drivertools.cc
@@ -680,9 +680,9 @@ void DriverMap::add(DriveBit const &a, DriveBit const &b)
 
 	// If either bit is just a wire that we don't need to keep, merge and
 	// use the other end as representative bit.
-	if (a_mode == BitMode::NONE)
+	if (a_mode == BitMode::NONE && !(b_mode == BitMode::DRIVEN_UNIQUE || b_mode == BitMode::DRIVEN))
 		connect_directed_merge(a_id, b_id);
-	else if (b_mode == BitMode::NONE)
+	else if (b_mode == BitMode::NONE && !(a_mode == BitMode::DRIVEN_UNIQUE || a_mode == BitMode::DRIVEN))
 		connect_directed_merge(b_id, a_id);
 	// If either bit requires a driven value and has a unique driver, merge
 	// and use the other end as representative bit.
diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc
index dec554d6c71..859b0b7ba4b 100644
--- a/passes/cmds/example_dt.cc
+++ b/passes/cmds/example_dt.cc
@@ -113,7 +113,7 @@ struct ExampleDtPass : public Pass
 								node.append_arg(enqueue(driver));
 							}
 						} else {
-							DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.width);
+							DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.wire->width);
 							node.set_function(ExampleFn(ID($$slice), {{ID(offset), wire_chunk.offset}, {ID(width), wire_chunk.width}}));
 							node.append_arg(enqueue(whole_wire));
 						}
@@ -145,7 +145,7 @@ struct ExampleDtPass : public Pass
 
 						} else {
 							DriveChunkPort whole_port(port_chunk.cell, port_chunk.port, 0, GetSize(port_chunk.cell->connections().at(port_chunk.port)));
-							node.set_function(ID($$buf));
+							node.set_function(ExampleFn(ID($$slice), {{ID(offset), port_chunk.offset}}));
 							node.append_arg(enqueue(whole_port));
 						}
 					} else if (chunk.is_constant()) {

From 63dea89facd9676b14da11f2e6bb79aa0ff3c583 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Wed, 1 May 2024 11:48:04 +0100
Subject: [PATCH 367/499] add initial version of functional C++ backend

---
 backends/functional/Makefile.inc      |   1 +
 backends/functional/cxx.cc            | 417 ++++++++++++++++++++++++++
 backends/functional/cxx_runtime/sim.h | 366 ++++++++++++++++++++++
 kernel/graphtools.h                   | 332 ++++++++++++++++++++
 4 files changed, 1116 insertions(+)
 create mode 100644 backends/functional/Makefile.inc
 create mode 100644 backends/functional/cxx.cc
 create mode 100644 backends/functional/cxx_runtime/sim.h
 create mode 100644 kernel/graphtools.h

diff --git a/backends/functional/Makefile.inc b/backends/functional/Makefile.inc
new file mode 100644
index 00000000000..011e662646c
--- /dev/null
+++ b/backends/functional/Makefile.inc
@@ -0,0 +1 @@
+OBJS += backends/functional/cxx.o
diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
new file mode 100644
index 00000000000..46ce88bd62c
--- /dev/null
+++ b/backends/functional/cxx.cc
@@ -0,0 +1,417 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/drivertools.h"
+#include "kernel/topo_scc.h"
+#include "kernel/functional.h"
+#include "kernel/graphtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+const char *reserved_keywords[] = {
+	"alignas","alignof","and","and_eq","asm","atomic_cancel","atomic_commit",
+	"atomic_noexcept","auto","bitand","bitor","bool","break","case",
+	"catch","char","char16_t","char32_t","char8_t","class","co_await",
+	"co_return","co_yield","compl","concept","const","const_cast","consteval",
+	"constexpr","constinit","continue","decltype","default","delete",
+	"do","double","dynamic_cast","else","enum","explicit","export",
+	"extern","false","float","for","friend","goto","if","inline",
+	"int","long","mutable","namespace","new","noexcept","not","not_eq",
+	"nullptr","operator","or","or_eq","private","protected","public",
+	"reflexpr","register","reinterpret_cast","requires","return","short",
+	"signed","sizeof","static","static_assert","static_cast","struct",
+	"switch","synchronized","template","this","thread_local","throw",
+	"true","try","typedef","typeid","typename","union","unsigned",
+	"using","virtual","void","volatile","wchar_t","while","xor","xor_eq",
+	nullptr
+};
+
+struct CxxScope {
+	pool<std::string> used_names;
+	dict<IdString, std::string> name_map;
+
+	CxxScope() {
+		for(const char **p = reserved_keywords; *p != nullptr; p++)
+			reserve(*p);
+	}
+	void reserve(std::string name) {
+		used_names.insert(name);
+	}
+	std::string insert(IdString id) {
+		std::string str = RTLIL::unescape_id(id);
+		for(size_t i = 0; i < str.size(); i++)
+			if(strchr("!\"#%&'()*+,-./:;<=>?@[]\\^`{|}~ ", str[i]))
+				str[i] = '_';
+		if(used_names.count(str) == 0){
+			used_names.insert(str);
+			name_map.insert({id, str});
+			return str;
+		}
+		for (int idx = 0 ; ; idx++){
+			std::string suffixed = str + "_" + std::to_string(idx);
+			if (used_names.count(suffixed) == 0) {
+				used_names.insert(suffixed);
+				if(name_map.count(id) == 0)
+					name_map.insert({id, suffixed});
+				return suffixed;
+			}
+		}
+	}
+	std::string operator[](IdString id) {
+		if(name_map.count(id) > 0)
+			return name_map[id];
+		else
+			return insert(id);
+	}
+};
+
+struct CxxWriter {
+	std::ostream &f;
+	CxxWriter(std::ostream &out) : f(out) {}
+	void printf(const char *fmt, ...)
+	{
+		va_list va;
+		va_start(va, fmt);
+		f << vstringf(fmt, va);
+		va_end(va);
+	}
+};
+
+struct CxxStruct {
+	std::string name;
+	dict<IdString, std::string> types;
+	CxxScope scope;
+	CxxStruct(std::string name) : name(name) {
+		scope.reserve("out");
+		scope.reserve("dump");
+	}
+	void insert(IdString name, std::string type) {
+		scope.insert(name);
+		types.insert({name, type});
+	}
+	void print(CxxWriter &f) {
+		f.printf("struct %s {\n", name.c_str());
+		for (auto p : types) {
+			f.printf("\t%s %s;\n", p.second.c_str(), scope[p.first].c_str());
+		}
+		f.printf("\n\ttemplate <typename T> void dump(T &out) {\n");
+		for (auto p : types) {
+			f.printf("\t\tout(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope[p.first].c_str());
+		}
+		f.printf("\t}\n};\n\n");
+	}
+	std::string operator[](IdString field) {
+		return scope[field];
+	}
+};
+
+struct CxxFunction {
+	IdString name;
+	int width;
+	dict<IdString, Const> parameters;
+
+	CxxFunction(IdString name, int width) : name(name), width(width) {}
+	CxxFunction(IdString name, int width, dict<IdString, Const> parameters) : name(name), width(width), parameters(parameters) {}
+
+	bool operator==(CxxFunction const &other) const {
+		return name == other.name && parameters == other.parameters && width == other.width;
+	}
+
+	unsigned int hash() const {
+		return mkhash(name.hash(), parameters.hash());
+	}
+};
+
+typedef ComputeGraph<CxxFunction, int, IdString, IdString> CxxComputeGraph;
+
+class CxxComputeGraphFactory {
+	CxxComputeGraph &graph;
+	using T = CxxComputeGraph::Ref;
+	static bool is_single_output(IdString type)
+	{
+		auto it = yosys_celltypes.cell_types.find(type);
+		return it != yosys_celltypes.cell_types.end() && it->second.outputs.size() <= 1;
+	}
+public:
+	CxxComputeGraphFactory(CxxComputeGraph &g) : graph(g) {}
+	T slice(T a, int in_width, int offset, int out_width) {
+		assert(offset + out_width <= in_width);
+		return graph.add(CxxFunction(ID($$slice), out_width, {{ID(offset), offset}}), 0, std::array<T, 1>{a});
+	}
+	T extend(T a, int in_width, int out_width, bool is_signed) {
+		assert(in_width < out_width);
+		if(is_signed)
+			return graph.add(CxxFunction(ID($sign_extend), out_width, {{ID(WIDTH), out_width}}), 0, std::array<T, 1>{a});
+		else
+			return graph.add(CxxFunction(ID($zero_extend), out_width, {{ID(WIDTH), out_width}}), 0, std::array<T, 1>{a});
+	}
+	T concat(T a, int a_width, T b, int b_width) {
+		return graph.add(CxxFunction(ID($$concat), a_width + b_width), 0, std::array<T, 2>{a, b});
+	}
+	T add(T a, T b, int width) { return graph.add(CxxFunction(ID($add), width), 0, std::array<T, 2>{a, b}); }
+	T sub(T a, T b, int width) { return graph.add(CxxFunction(ID($sub), width), 0, std::array<T, 2>{a, b}); }
+	T bitwise_and(T a, T b, int width) { return graph.add(CxxFunction(ID($and), width), 0, std::array<T, 2>{a, b}); }
+	T bitwise_or(T a, T b, int width) { return graph.add(CxxFunction(ID($or), width), 0, std::array<T, 2>{a, b}); }
+	T bitwise_xor(T a, T b, int width) { return graph.add(CxxFunction(ID($xor), width), 0, std::array<T, 2>{a, b}); }
+	T bitwise_not(T a, int width) { return graph.add(CxxFunction(ID($not), width), 0, std::array<T, 1>{a}); }
+	T neg(T a, int width) { return graph.add(CxxFunction(ID($neg), width), 0, std::array<T, 1>{a}); }
+	T mux(T a, T b, T s, int width) { return graph.add(CxxFunction(ID($mux), width), 0, std::array<T, 3>{a, b, s}); }
+	T pmux(T a, T b, T s, int width, int) { return graph.add(CxxFunction(ID($pmux), width), 0, std::array<T, 3>{a, b, s}); }
+	T reduce_and(T a, int) { return graph.add(CxxFunction(ID($reduce_and), 1), 0, std::array<T, 1>{a}); }
+	T reduce_or(T a, int) { return graph.add(CxxFunction(ID($reduce_or), 1), 0, std::array<T, 1>{a}); }
+	T reduce_xor(T a, int) { return graph.add(CxxFunction(ID($reduce_xor), 1), 0, std::array<T, 1>{a}); }
+	T eq(T a, T b, int) { return graph.add(CxxFunction(ID($eq), 1), 0, std::array<T, 2>{a, b}); }
+	T ne(T a, T b, int) { return graph.add(CxxFunction(ID($ne), 1), 0, std::array<T, 2>{a, b}); }
+	T gt(T a, T b, int) { return graph.add(CxxFunction(ID($gt), 1), 0, std::array<T, 2>{a, b}); }
+	T ge(T a, T b, int) { return graph.add(CxxFunction(ID($ge), 1), 0, std::array<T, 2>{a, b}); }
+	T ugt(T a, T b, int) { return graph.add(CxxFunction(ID($ugt), 1), 0, std::array<T, 2>{a, b}); }
+	T uge(T a, T b, int) { return graph.add(CxxFunction(ID($uge), 1), 0, std::array<T, 2>{a, b}); }
+	T logical_shift_left(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shl), y_width, {{ID(WIDTH), y_width}}), 0, std::array<T, 2>{a, b}); }
+	T logical_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shr), y_width, {{ID(WIDTH), y_width}}), 0, std::array<T, 2>{a, b}); }
+	T arithmetic_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($asr), y_width, {{ID(WIDTH), y_width}}), 0, std::array<T, 2>{a, b}); }
+
+	T constant(RTLIL::Const value) {
+		return graph.add(CxxFunction(ID($$const), value.size(), {{ID(value), value}}), 0);
+	}
+	T input(IdString name, int width) { return graph.add(CxxFunction(ID($$input), width, {{name, {}}}), 0); }
+	T state(IdString name, int width) { return graph.add(CxxFunction(ID($$state), width, {{name, {}}}), 0); }
+	T cell_output(T cell, IdString type, IdString name, int width) {
+		if (is_single_output(type))
+			return cell;
+		else
+			return graph.add(CxxFunction(ID($$cell_output), width, {{name, {}}}), 0, std::array<T, 1>{cell});
+	}
+	T multiple(vector<T> args, int width) {
+		return graph.add(CxxFunction(ID($$multiple), width), 0, args);
+	}
+	T undriven(int width) {
+		return graph.add(CxxFunction(ID($$undriven), width), 0);
+	}
+
+	T create_pending(int width) {
+		return graph.add(CxxFunction(ID($$pending), width), 0);
+	}
+	void update_pending(T pending, T node) {
+		assert(pending.function().name == ID($$pending));
+		pending.set_function(CxxFunction(ID($$buf), pending.function().width));
+		pending.append_arg(node);
+	}
+	void declare_output(T node, IdString name) {
+		node.assign_key(name);
+	}
+	void declare_state(T node, IdString name) {
+		node.assign_key(name);
+	}
+	void suggest_name(T node, IdString name) {
+		node.sparse_attr() = name;
+	}
+};
+
+struct FunctionalCxxBackend : public Backend
+{
+	FunctionalCxxBackend() : Backend("functional_cxx", "convert design to C++ using the functional backend") {}
+
+    void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+    }
+
+	CxxComputeGraph calculate_compute_graph(RTLIL::Module *module)
+	{
+		CxxComputeGraph compute_graph;
+		CxxComputeGraphFactory factory(compute_graph);
+		ComputeGraphConstruction<CxxComputeGraph::Ref, CxxComputeGraphFactory> construction(factory);
+		construction.add_module(module);
+		construction.process_queue();
+
+		// Perform topo sort and detect SCCs
+		CxxComputeGraph::SccAdaptor compute_graph_scc(compute_graph);
+
+		bool scc = false;
+		std::vector<int> perm;
+		topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) {
+			perm.insert(perm.end(), begin, end);
+			if (end > begin + 1)
+			{
+				log_warning("SCC:");
+				for (int *i = begin; i != end; ++i)
+					log(" %d(%s)(%s)", *i, compute_graph[*i].function().name.c_str(), compute_graph[*i].has_sparse_attr() ? compute_graph[*i].sparse_attr().c_str() : "");
+				log("\n");
+				scc = true;
+			}
+		}, /* sources_first */ true);
+		compute_graph.permute(perm);
+		if(scc) log_error("combinational loops, aborting\n");
+
+		// Forward $$buf
+		std::vector<int> alias;
+		perm.clear();
+
+		for (int i = 0; i < compute_graph.size(); ++i)
+		{
+			auto node = compute_graph[i];
+			if (node.function().name == ID($$buf) && node.arg(0).index() < i)
+			{
+				int target_index = alias[node.arg(0).index()];
+				auto target_node = compute_graph[perm[target_index]];
+				if(!target_node.has_sparse_attr() && node.has_sparse_attr())
+					target_node.sparse_attr() = node.sparse_attr();
+				alias.push_back(target_index);
+			}
+			else
+			{
+				alias.push_back(GetSize(perm));
+				perm.push_back(i);
+			}
+		}
+		compute_graph.permute(perm, alias);
+		return compute_graph;
+	}
+
+	void printCxx(std::ostream &stream, std::string, std::string const & name, CxxComputeGraph &compute_graph)
+	{
+		dict<IdString, int> inputs, state;
+		CxxWriter f(stream);
+
+		// Dump the compute graph
+		for (int i = 0; i < compute_graph.size(); ++i)
+		{
+			auto ref = compute_graph[i];
+			if(ref.function().name == ID($$input))
+				inputs[ref.function().parameters.begin()->first] = ref.function().width;
+			if(ref.function().name == ID($$state))
+				state[ref.function().parameters.begin()->first] = ref.function().width;
+		}
+		f.printf("#include \"sim.h\"\n");
+		CxxStruct input_struct(name + "_Inputs");
+		for (auto const &input : inputs)
+			input_struct.insert(input.first, "Signal<" + std::to_string(input.second) + ">");
+		CxxStruct output_struct(name + "_Outputs");
+		for (auto const &key : compute_graph.keys())
+			if(state.count(key.first) == 0)
+				output_struct.insert(key.first, "Signal<" + std::to_string(compute_graph[key.second].function().width) + ">");
+		CxxStruct state_struct(name + "_State");
+		for (auto const &state_var : state)
+			state_struct.insert(state_var.first, "Signal<" + std::to_string(state_var.second) + ">");
+
+		idict<std::string> node_names;
+		CxxScope locals;
+
+		input_struct.print(f);
+		output_struct.print(f);
+		state_struct.print(f);
+
+		f.printf("void %s(%s_Inputs const &input, %s_Outputs &output, %s_State const &current_state, %s_State &next_state)\n{\n", name.c_str(), name.c_str(), name.c_str(), name.c_str(), name.c_str());
+		locals.reserve("input");
+		locals.reserve("output");
+		locals.reserve("current_state");
+		locals.reserve("next_state");
+		for (int i = 0; i < compute_graph.size(); ++i)
+		{
+			auto ref = compute_graph[i];
+			int width = ref.function().width;
+			std::string name;
+			if(ref.has_sparse_attr())
+				name = locals.insert(ref.sparse_attr());
+			else
+				name = locals.insert("\\n" + std::to_string(i));
+			node_names(name);
+			if(ref.function().name == ID($$input))
+				f.printf("\tSignal<%d> %s = input.%s;\n", width, name.c_str(), input_struct[ref.function().parameters.begin()->first].c_str());
+			else if(ref.function().name == ID($$state))
+				f.printf("\tSignal<%d> %s = current_state.%s;\n", width, name.c_str(), state_struct[ref.function().parameters.begin()->first].c_str());
+			else if(ref.function().name == ID($$buf))
+				f.printf("\tSignal<%d> %s = %s;\n", width, name.c_str(), node_names[ref.arg(0).index()].c_str());
+			else if(ref.function().name == ID($$cell_output))
+				f.printf("\tSignal<%d> %s = %s.%s;\n", width, name.c_str(), node_names[ref.arg(0).index()].c_str(), RTLIL::unescape_id(ref.function().parameters.begin()->first).c_str());
+			else if(ref.function().name == ID($$const)){
+				auto c = ref.function().parameters.begin()->second;
+				if(c.size() <= 32){
+					f.printf("\tSignal<%d> %s = $const<%d>(%#x);\n", width, name.c_str(), width, (uint32_t) c.as_int());
+				}else{
+					f.printf("\tSignal<%d> %s = $const<%d>({%#x", width, name.c_str(), width, (uint32_t) c.as_int());
+					while(c.size() > 32){
+						c = c.extract(32, c.size() - 32);
+						f.printf(", %#x", c.as_int());
+					}
+					f.printf("});\n");
+				}
+			}else if(ref.function().name == ID($$undriven))
+				f.printf("\tSignal<%d> %s; //undriven\n", width, name.c_str());
+			else if(ref.function().name == ID($$slice))
+				f.printf("\tSignal<%d> %s = slice<%d>(%s, %d);\n", width, name.c_str(), width, node_names[ref.arg(0).index()].c_str(), ref.function().parameters.at(ID(offset)).as_int());
+			else if(ref.function().name == ID($$concat)){
+				f.printf("\tauto %s = concat(", name.c_str());
+				for (int i = 0, end = ref.size(); i != end; ++i){
+					if(i > 0)
+						f.printf(", ");
+					f.printf("%s", node_names[ref.arg(i).index()].c_str());
+				}
+				f.printf(");\n");
+			}else{
+				f.printf("\t");
+				if(ref.function().width > 0)
+					f.printf("Signal<%d>", ref.function().width);
+				else
+					f.printf("%s_Outputs", log_id(ref.function().name));
+				f.printf(" %s = %s", name.c_str(), log_id(ref.function().name));
+				if(ref.function().parameters.count(ID(WIDTH))){
+					f.printf("<%d>", ref.function().parameters.at(ID(WIDTH)).as_int());
+				}
+				f.printf("(");
+				for (int i = 0, end = ref.size(); i != end; ++i)
+					f.printf("%s%s", i>0?", ":"", node_names[ref.arg(i).index()].c_str());
+				f.printf("); //");
+				for (auto const &param : ref.function().parameters)
+				{
+					if (param.second.empty())
+						f.printf("[%s]", log_id(param.first));
+					else
+						f.printf("[%s=%s]", log_id(param.first), log_const(param.second));
+				}
+				f.printf("\n");
+			}
+		}
+
+		for (auto const &key : compute_graph.keys())
+		{
+			f.printf("\t%s.%s = %s;\n", state.count(key.first) > 0 ? "next_state" : "output", state_struct[key.first].c_str(), node_names[key.second].c_str());
+		}
+		f.printf("}\n");
+	}
+
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
+	{
+        log_header(design, "Executing Functional C++ backend.\n");
+
+		size_t argidx = 1;
+		extra_args(f, filename, args, argidx, design);
+
+		for (auto module : design->selected_modules()) {
+            log("Dumping module `%s'.\n", module->name.c_str());
+			auto compute_graph = calculate_compute_graph(module);
+			printCxx(*f, filename, RTLIL::unescape_id(module->name), compute_graph);
+		}
+	}
+} FunctionalCxxBackend;
+
+PRIVATE_NAMESPACE_END
diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h
new file mode 100644
index 00000000000..4e7d9b60142
--- /dev/null
+++ b/backends/functional/cxx_runtime/sim.h
@@ -0,0 +1,366 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef SIM_H
+#define SIM_H
+
+#include <array>
+
+template<size_t n>
+using Signal = std::array<bool, n>;
+
+template<size_t n, size_t m>
+Signal<n> slice(Signal<m> const& a, size_t offset)
+{
+    Signal<n> ret;
+
+    std::copy(a.begin() + offset, a.begin() + offset + n, ret.begin());
+    return ret;
+}
+
+template<size_t n>
+Signal<n> $const(uint32_t val)
+{
+    size_t i;
+    Signal<n> ret;
+
+    for(i = 0; i < n; i++)
+        if(i < 32)
+            ret[i] = val & (1<<i);
+        else
+            ret[i] = false;
+    return ret;
+}
+
+template<size_t n>
+Signal<n> $const(std::initializer_list<uint32_t> vals)
+{
+    size_t k, i;
+    Signal<n> ret;
+
+    k = 0;
+    for (auto val : vals) {
+        for(i = 0; i < 32; i++)
+            if(i + k < n)
+                ret[i + k] = val & (1<<i);
+        k += 32;
+    }
+    for(; k < n; k++)
+        ret[k] = false;
+    return ret;
+}
+
+template<size_t n>
+bool as_bool(Signal<n> sig)
+{
+    for(int i = 0; i < n; i++)
+        if(sig[i])
+            return true;
+    return false;
+}
+
+template<size_t n>
+uint32_t as_int(Signal<n> sig)
+{
+    uint32_t ret = 0;
+    for(int i = 0; i < n; i++)
+        if(sig[i] && i < 32)
+            ret |= 1<<i;
+    return ret;
+}
+
+template<size_t n>
+Signal<n> $mux(Signal<n> const& a, Signal<n> const &b, Signal<1> const &s)
+{
+    return s[0] ? b : a;
+}
+
+template<size_t n>
+Signal<n> $not(Signal<n> const& a)
+{
+    Signal<n> ret;
+    for(size_t i = 0; i < n; i++)
+        ret[i] = !a[i];
+    return ret;
+}
+
+template<size_t n>
+Signal<n> $neg(Signal<n> const& a)
+{
+    Signal<n> ret;
+    bool carry = true;
+    for(size_t i = 0; i < n; i++) {
+        int r = !a[i] + carry;
+        ret[i] = (r & 1) != 0;
+        carry = (r >> 1) != 0;
+    }
+    return ret;
+}
+
+template<size_t n>
+Signal<1> $reduce_or(Signal<n> const& a)
+{
+    return { as_bool(a) };
+}
+
+template<size_t n>
+Signal<1> $reduce_and(Signal<n> const& a)
+{
+    for(size_t i = 0; i < n; i++)
+        if(!a[i])
+            return { false };
+    return { true };
+}
+
+template<size_t n>
+Signal<1> $reduce_bool(Signal<n> const& a)
+{
+    return { as_bool(a) };
+}
+
+template<size_t n>
+Signal<1> $logic_and(Signal<n> const& a, Signal<n> const& b)
+{
+    return { as_bool(a) && as_bool(b) };
+}
+
+template<size_t n>
+Signal<1> $logic_or(Signal<n> const& a, Signal<n> const& b)
+{
+    return { as_bool(a) || as_bool(b) };
+}
+
+template<size_t n>
+Signal<1> $logic_not(Signal<n> const& a)
+{
+    return { !as_bool(a) };
+}
+
+template<size_t n>
+Signal<n> $add(Signal<n> const& a, Signal<n> const &b)
+{
+    Signal<n> ret;
+    size_t i;
+    int x = 0;
+    for(i = 0; i < n; i++){
+        x += (int)a[i] + (int)b[i];
+        ret[i] = x & 1;
+        x >>= 1;
+    }
+    return ret;
+}
+template<size_t n>
+Signal<n> $sub(Signal<n> const& a, Signal<n> const &b)
+{
+    Signal<n> ret;
+    int x = 1;
+    for(size_t i = 0; i < n; i++){
+        x += (int)a[i] + (int)!b[i];
+        ret[i] = x & 1;
+        x >>= 1;
+    }
+    return ret;
+}
+
+template<size_t n>
+Signal<1> $uge(Signal<n> const& a, Signal<n> const &b)
+{
+    for(size_t i = n; i-- != 0; )
+        if(a[i] != b[i])
+            return { a[i] };
+    return { true };
+}
+
+template<size_t n>
+Signal<1> $ugt(Signal<n> const& a, Signal<n> const &b)
+{
+    for(size_t i = n; i-- != 0; )
+        if(a[i] != b[i])
+            return { a[i] };
+    return { false };
+}
+
+template<size_t n>
+Signal<1> $ge(Signal<n> const& a, Signal<n> const &b)
+{
+    if(a[n-1] != b[n-1])
+        return { b[n-1] };
+    return $uge(a, b);
+}
+
+template<size_t n>
+Signal<1> $gt(Signal<n> const& a, Signal<n> const &b)
+{
+    if(a[n-1] != b[n-1])
+        return { b[n-1] };
+    return $ugt(a, b);
+}
+
+template<size_t n> Signal<1> $ule(Signal<n> const& a, Signal<n> const &b) { return $uge(b, a); }
+template<size_t n> Signal<1> $ult(Signal<n> const& a, Signal<n> const &b) { return $ugt(b, a); }
+template<size_t n> Signal<1> $le(Signal<n> const& a, Signal<n> const &b) { return $ge(b, a); }
+template<size_t n> Signal<1> $lt(Signal<n> const& a, Signal<n> const &b) { return $gt(b, a); }
+
+template<size_t n>
+Signal<n> $and(Signal<n> const& a, Signal<n> const &b)
+{
+    Signal<n> ret;
+    for(size_t i = 0; i < n; i++)
+        ret[i] = a[i] && b[i];
+    return ret;
+}
+
+template<size_t n>
+Signal<n> $or(Signal<n> const& a, Signal<n> const &b)
+{
+    Signal<n> ret;
+    for(size_t i = 0; i < n; i++)
+        ret[i] = a[i] || b[i];
+    return ret;
+}
+
+template<size_t n>
+Signal<n> $xor(Signal<n> const& a, Signal<n> const &b)
+{
+    Signal<n> ret;
+    for(size_t i = 0; i < n; i++)
+        ret[i] = a[i] != b[i];
+    return ret;
+}
+
+template<size_t n, size_t na, size_t nb>
+Signal<n> $shl(Signal<na> const& a, Signal<nb> const &b)
+{
+    if(nb >= sizeof(int) * 8 - 1)
+        for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
+            assert(!b[i]);
+    size_t amount = as_int(b);
+    Signal<n> ret = $const<n>(0);
+    if(amount < n){
+        if(amount + na > n)
+            std::copy(a.begin(), a.begin() + (n - amount), ret.begin() + amount);
+        else
+            std::copy(a.begin(), a.end(), ret.begin() + amount);
+    }
+    return ret;
+}
+
+template<size_t n, size_t nb>
+Signal<n> $shr(Signal<n> const& a, Signal<nb> const &b)
+{
+    if(nb >= sizeof(int) * 8 - 1)
+        for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
+            assert(!b[i]);
+    size_t amount = as_int(b);
+    Signal<n> ret;
+    for (size_t i = 0; i < n; i++) {
+        if(i + amount < n)
+            ret[i] = a[i + amount];
+        else
+            ret[i] = false;
+    }
+    return ret;
+}
+
+template<size_t n, size_t nb>
+Signal<n> $asr(Signal<n> const& a, Signal<nb> const &b)
+{
+    if(nb >= sizeof(int) * 8 - 1)
+        for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
+            assert(!b[i]);
+    size_t amount = as_int(b);
+    Signal<n> ret;
+    for (size_t i = 0; i < n; i++) {
+        if(i + amount < n)
+            ret[i] = a[i + amount];
+        else
+            ret[i] = a[n - 1];
+    }
+    return ret;
+}
+
+template<size_t n>
+Signal<1> $eq(Signal<n> const& a, Signal<n> const &b)
+{
+    for(size_t i = 0; i < n; i++)
+        if(a[i] != b[i])
+            return { false };
+    return { true };
+}
+
+template<size_t n>
+Signal<1> $ne(Signal<n> const& a, Signal<n> const &b)
+{
+    for(size_t i = 0; i < n; i++)
+        if(a[i] != b[i])
+            return { true };
+    return { false };
+}
+
+template<size_t n, size_t ns>
+Signal<n> $pmux(Signal<n> const& a, Signal<n*ns> const &b, Signal<ns> const &s)
+{
+    bool found;
+    Signal<n> ret;
+
+    found = false;
+    ret = a;
+    for(size_t i = 0; i < ns; i++){
+        if(s[i]){
+            if(found)
+                return $const<n>(0);
+            found = true;
+            ret = slice<n>(b, n * i);
+        }
+    }
+    return ret;
+}
+
+template<size_t n, size_t m>
+Signal<n+m> concat(Signal<n> const& a, Signal<m> const& b)
+{
+    Signal<n + m> ret;
+    std::copy(a.begin(), a.end(), ret.begin());
+    std::copy(b.begin(), b.end(), ret.begin() + n);
+    return ret;
+}
+
+template<size_t n, size_t m>
+Signal<n> $zero_extend(Signal<m> const& a)
+{
+    assert(n >= m);
+    Signal<n> ret;
+    std::copy(a.begin(), a.end(), ret.begin());
+    for(size_t i = m; i < n; i++)
+        ret[i] = false;
+    return ret;
+}
+
+template<size_t n, size_t m>
+Signal<n> $sign_extend(Signal<m> const& a)
+{
+    assert(n >= m);
+    Signal<n> ret;
+    std::copy(a.begin(), a.end(), ret.begin());
+    for(size_t i = m; i < n; i++)
+        ret[i] = a[m-1];
+    return ret;
+}
+
+#endif
diff --git a/kernel/graphtools.h b/kernel/graphtools.h
new file mode 100644
index 00000000000..1a59ef1b537
--- /dev/null
+++ b/kernel/graphtools.h
@@ -0,0 +1,332 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef GRAPHTOOLS_H
+#define GRAPHTOOLS_H
+
+#include "kernel/yosys.h"
+#include "kernel/drivertools.h"
+#include "kernel/functional.h"
+
+USING_YOSYS_NAMESPACE
+YOSYS_NAMESPACE_BEGIN
+
+template <class T, class Factory>
+class CellSimplifier {
+	Factory &factory;
+	T reduce_shift_width(T b, int b_width, int y_width, int &reduced_b_width) {
+		log_assert(y_width > 0);
+		int new_width = sizeof(int) * 8 - __builtin_clz(y_width);
+		if (b_width <= new_width) {
+			reduced_b_width = b_width;
+			return b;
+		} else {
+			reduced_b_width = new_width;
+			T lower_b = factory.slice(b, b_width, 0, new_width);
+			T overflow = factory.gt(b, factory.constant(RTLIL::Const(y_width, b_width)), b_width);
+			return factory.mux(lower_b, factory.constant(RTLIL::Const(y_width, new_width)), overflow, new_width);
+		}
+	}
+public:
+	T reduce_or(T a, int width) {
+		if (width == 1)
+			return a;
+		return factory.reduce_or(a, width);
+	}
+	T extend(T a, int in_width, int out_width, bool is_signed) {
+		if(in_width == out_width)
+			return a;
+		if(in_width > out_width)
+			return factory.slice(a, in_width, 0, out_width);
+		return factory.extend(a, in_width, out_width, is_signed);
+	}
+	T logical_shift_left(T a, T b, int y_width, int b_width) {
+		int reduced_b_width;
+		T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width);
+		return factory.logical_shift_left(a, reduced_b, y_width, reduced_b_width);
+	}
+	T logical_shift_right(T a, T b, int y_width, int b_width) {
+		int reduced_b_width;
+		T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width);
+		return factory.logical_shift_right(a, reduced_b, y_width, reduced_b_width);
+	}
+	T arithmetic_shift_right(T a, T b, int y_width, int b_width) {
+		int reduced_b_width;
+		T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width);
+		return factory.arithmetic_shift_right(a, reduced_b, y_width, reduced_b_width);
+	}
+	CellSimplifier(Factory &f) : factory(f) {}
+	T handle(IdString cellType, dict<IdString, Const> parameters, dict<IdString, T> inputs)
+	{
+		int a_width = parameters.at(ID(A_WIDTH), Const(-1)).as_int();
+		int b_width = parameters.at(ID(B_WIDTH), Const(-1)).as_int();
+		int y_width = parameters.at(ID(Y_WIDTH), Const(-1)).as_int();
+		bool a_signed = parameters.at(ID(A_SIGNED), Const(0)).as_bool();
+		bool b_signed = parameters.at(ID(B_SIGNED), Const(0)).as_bool();
+		if(cellType.in({ID($add), ID($sub), ID($and), ID($or), ID($xor), ID($xnor)})){
+			bool is_signed = a_signed && b_signed;
+			T a = extend(inputs.at(ID(A)), a_width, y_width, is_signed);
+			T b = extend(inputs.at(ID(B)), b_width, y_width, is_signed);
+			if(cellType == ID($add))
+				return factory.add(a, b, y_width);
+			else if(cellType == ID($sub))
+				return factory.sub(a, b, y_width);
+			else if(cellType == ID($and))
+				return factory.bitwise_and(a, b, y_width);
+			else if(cellType == ID($or))
+				return factory.bitwise_or(a, b, y_width);
+			else if(cellType == ID($xor))
+				return factory.bitwise_xor(a, b, y_width);
+			else if(cellType == ID($xnor))
+				return factory.bitwise_not(factory.bitwise_xor(a, b, y_width), y_width);
+			else
+				log_abort();
+		}else if(cellType.in({ID($eq), ID($ne), ID($eqx), ID($nex), ID($le), ID($lt), ID($ge), ID($gt)})){
+			bool is_signed = a_signed && b_signed;
+			int width = max(a_width, b_width);
+			T a = extend(inputs.at(ID(A)), a_width, width, is_signed);
+			T b = extend(inputs.at(ID(B)), b_width, width, is_signed);
+			if(cellType.in({ID($eq), ID($eqx)}))
+				return extend(factory.eq(a, b, width), 1, y_width, false);
+			if(cellType.in({ID($ne), ID($nex)}))
+				return extend(factory.ne(a, b, width), 1, y_width, false);
+			else if(cellType == ID($lt))
+				return extend(is_signed ? factory.gt(b, a, width) : factory.ugt(b, a, width), 1, y_width, false);
+			else if(cellType == ID($le))
+				return extend(is_signed ? factory.ge(b, a, width) : factory.uge(b, a, width), 1, y_width, false);
+			else if(cellType == ID($gt))
+				return extend(is_signed ? factory.gt(a, b, width) : factory.ugt(a, b, width), 1, y_width, false);
+			else if(cellType == ID($ge))
+				return extend(is_signed ? factory.ge(a, b, width) : factory.uge(a, b, width), 1, y_width, false);
+			else
+				log_abort();
+		}else if(cellType.in({ID($logic_or), ID($logic_and)})){
+			T a = reduce_or(inputs.at(ID(A)), a_width);
+			T b = reduce_or(inputs.at(ID(B)), b_width);
+			T y = cellType == ID($logic_and) ? factory.bitwise_and(a, b, 1) : factory.bitwise_or(a, b, 1);
+			return extend(y, 1, y_width, false);
+		}else if(cellType == ID($not)){
+			T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed);
+			return factory.bitwise_not(a, y_width);
+		}else if(cellType == ID($pos)){
+			return extend(inputs.at(ID(A)), a_width, y_width, a_signed);
+		}else if(cellType == ID($neg)){
+			T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed);
+			return factory.neg(a, y_width);
+		}else if(cellType == ID($logic_not)){
+			T a = reduce_or(inputs.at(ID(A)), a_width);
+			T y = factory.bitwise_not(a, 1);
+			return extend(y, 1, y_width, false);
+		}else if(cellType.in({ID($reduce_or), ID($reduce_bool)})){
+			T a = reduce_or(inputs.at(ID(A)), a_width);
+			return extend(a, 1, y_width, false);
+		}else if(cellType == ID($reduce_and)){
+			T a = factory.reduce_and(inputs.at(ID(A)), a_width);
+			return extend(a, 1, y_width, false);
+		}else if(cellType.in({ID($reduce_xor), ID($reduce_xnor)})){
+			T a = factory.reduce_xor(inputs.at(ID(A)), a_width);
+			T y = cellType == ID($reduce_xnor) ? factory.bitwise_not(a, 1) : a;
+			return extend(y, 1, y_width, false);
+		}else if(cellType == ID($shl) || cellType == ID($sshl)){
+			T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed);
+			T b = inputs.at(ID(B));
+			return logical_shift_left(a, b, y_width, b_width);
+		}else if(cellType == ID($shr) || cellType == ID($sshr)){
+			int width = max(a_width, y_width);
+			T a = extend(inputs.at(ID(A)), a_width, width, a_signed);
+			T b = inputs.at(ID(B));
+			T y = a_signed && cellType == ID($sshr) ?
+				arithmetic_shift_right(a, b, width, b_width) :
+				logical_shift_right(a, b, width, b_width);
+			return extend(y, width, y_width, a_signed);
+		}else if(cellType == ID($shiftx) || cellType == ID($shift)){
+			int width = max(a_width, y_width);
+			T a = extend(inputs.at(ID(A)), a_width, width, cellType == ID($shift) && a_signed);
+			T b = inputs.at(ID(B));
+			T shr = logical_shift_right(a, b, width, b_width);
+			if(b_signed) {
+				T sign_b = factory.slice(b, b_width, b_width - 1, 1);
+				T shl = logical_shift_left(a, factory.neg(b, b_width), width, b_width);
+				T y = factory.mux(shr, shl, sign_b, width);
+				return extend(y, width, y_width, false);
+			} else {
+				return extend(shr, width, y_width, false);
+			}
+		}else if(cellType == ID($mux)){
+			int width = parameters.at(ID(WIDTH)).as_int();
+			return factory.mux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S)), width);
+		}else if(cellType == ID($pmux)){
+			int width = parameters.at(ID(WIDTH)).as_int();
+			int s_width = parameters.at(ID(S_WIDTH)).as_int();
+			return factory.pmux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S)), width, s_width);
+		}else if(cellType == ID($concat)){
+			T a = inputs.at(ID(A));
+			T b = inputs.at(ID(B));
+			return factory.concat(a, a_width, b, b_width);
+		}else if(cellType == ID($slice)){
+			int offset = parameters.at(ID(OFFSET)).as_int();
+			T a = inputs.at(ID(A));
+			return factory.slice(a, a_width, offset, y_width);
+		}else{
+			log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str());
+		}
+	}
+};
+
+template <class T, class Factory>
+class ComputeGraphConstruction {
+	std::deque<DriveSpec> queue;
+	dict<DriveSpec, T> graph_nodes;
+	idict<Cell *> cells;
+	DriverMap driver_map;
+	Factory& factory;
+	CellSimplifier<T, Factory> simplifier;
+
+	T enqueue(DriveSpec const &spec)
+	{
+		auto it = graph_nodes.find(spec);
+		if(it == graph_nodes.end()){
+			auto node = factory.create_pending(spec.size());
+			graph_nodes.insert({spec, node});
+			queue.emplace_back(spec);
+			return node;
+		}else
+			return it->second;
+	}
+public:
+	ComputeGraphConstruction(Factory &f) : factory(f), simplifier(f) {}
+	void add_module(Module *module)
+	{
+		driver_map.add(module);
+		for (auto cell : module->cells()) {
+			if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($check)))
+				enqueue(DriveBitMarker(cells(cell), 0));
+		}
+		for (auto wire : module->wires()) {
+			if (wire->port_output) {
+				T node = enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width)));
+				factory.declare_output(node, wire->name);
+			}
+		}
+	}
+	void process_queue()
+	{
+		for (; !queue.empty(); queue.pop_front()) {
+			DriveSpec spec = queue.front();
+			T pending = graph_nodes.at(spec);
+
+			if (spec.chunks().size() > 1) {
+				auto chunks = spec.chunks();
+				T node = enqueue(chunks[0]);
+				int width = chunks[0].size();
+				for(size_t i = 1; i < chunks.size(); i++) {
+					node = factory.concat(node, width, enqueue(chunks[i]), chunks[i].size());
+					width += chunks[i].size();
+				}
+				factory.update_pending(pending, node);
+			} else if (spec.chunks().size() == 1) {
+				DriveChunk chunk = spec.chunks()[0];
+				if (chunk.is_wire()) {
+					DriveChunkWire wire_chunk = chunk.wire();
+					if (wire_chunk.is_whole()) {
+						if (wire_chunk.wire->port_input) {
+							T node = factory.input(wire_chunk.wire->name, wire_chunk.width);
+							factory.suggest_name(node, wire_chunk.wire->name);
+							factory.update_pending(pending, node);
+						} else {
+							DriveSpec driver = driver_map(DriveSpec(wire_chunk));
+							T node = enqueue(driver);
+							factory.suggest_name(node, wire_chunk.wire->name);
+							factory.update_pending(pending, node);
+						}
+					} else {
+						DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.wire->width);
+						T node = factory.slice(enqueue(whole_wire), wire_chunk.wire->width, wire_chunk.offset, wire_chunk.width);
+						factory.update_pending(pending, node);
+					}
+				} else if (chunk.is_port()) {
+					DriveChunkPort port_chunk = chunk.port();
+					if (port_chunk.is_whole()) {
+						if (driver_map.celltypes.cell_output(port_chunk.cell->type, port_chunk.port)) {
+							if (port_chunk.cell->type.in(ID($dff), ID($ff)))
+							{
+								Cell *cell = port_chunk.cell;
+								T node = factory.state(cell->name, port_chunk.width);
+								factory.suggest_name(node, port_chunk.cell->name);
+								factory.update_pending(pending, node);
+								for (auto const &conn : cell->connections()) {
+									if (driver_map.celltypes.cell_input(cell->type, conn.first)) {
+										T node = enqueue(DriveChunkPort(cell, conn));
+										factory.declare_state(node, cell->name);
+									}
+								}
+							}
+							else
+							{
+								T cell = enqueue(DriveChunkMarker(cells(port_chunk.cell), 0, port_chunk.width));
+								factory.suggest_name(cell, port_chunk.cell->name);
+								T node = factory.cell_output(cell, port_chunk.cell->type, port_chunk.port, port_chunk.width);
+								factory.suggest_name(node, port_chunk.cell->name.str() + "$" + port_chunk.port.str());
+								factory.update_pending(pending, node);
+							}
+						} else {
+							DriveSpec driver = driver_map(DriveSpec(port_chunk));
+							factory.update_pending(pending, enqueue(driver));
+						}
+					} else {
+						DriveChunkPort whole_port(port_chunk.cell, port_chunk.port, 0, GetSize(port_chunk.cell->connections().at(port_chunk.port)));
+						T node = factory.slice(enqueue(whole_port), whole_port.width, port_chunk.offset, port_chunk.width);
+						factory.update_pending(pending, node);
+					}
+				} else if (chunk.is_constant()) {
+					T node = factory.constant(chunk.constant());
+					factory.suggest_name(node, "$const" + std::to_string(chunk.size()) + "b" + chunk.constant().as_string());
+					factory.update_pending(pending, node);
+				} else if (chunk.is_multiple()) {
+					vector<T> args;
+					for (auto const &driver : chunk.multiple().multiple())
+						args.push_back(enqueue(driver));
+					T node = factory.multiple(args, chunk.size());
+					factory.update_pending(pending, node);
+				} else if (chunk.is_marker()) {
+					Cell *cell = cells[chunk.marker().marker];
+					dict<IdString, T> connections;
+					for(auto const &conn : cell->connections()) {
+						if(driver_map.celltypes.cell_input(cell->type, conn.first))
+							connections.insert({ conn.first, enqueue(DriveChunkPort(cell, conn)) });
+					}
+					T node = simplifier.handle(cell->type, cell->parameters, connections);
+					factory.update_pending(pending, node);
+				} else if (chunk.is_none()) {
+					T node = factory.undriven(chunk.size());
+					factory.update_pending(pending, node);
+				} else {
+					log_error("unhandled drivespec: %s\n", log_signal(chunk));
+					log_abort();
+				}
+			} else {
+				log_abort();
+			}
+		}
+	}
+};
+
+YOSYS_NAMESPACE_END
+
+#endif

From 7611dda2ebfbbc29623e13bc8850910d21398a98 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 23 May 2024 11:40:41 +0100
Subject: [PATCH 368/499] add initial version of functional smtlib backend

---
 backends/functional/Makefile.inc |   1 +
 backends/functional/cxx.cc       |   4 +-
 backends/functional/smtlib.cc    | 541 +++++++++++++++++++++++++++++++
 kernel/graphtools.h              |   6 +-
 4 files changed, 547 insertions(+), 5 deletions(-)
 create mode 100644 backends/functional/smtlib.cc

diff --git a/backends/functional/Makefile.inc b/backends/functional/Makefile.inc
index 011e662646c..c712d2aefe5 100644
--- a/backends/functional/Makefile.inc
+++ b/backends/functional/Makefile.inc
@@ -1 +1,2 @@
 OBJS += backends/functional/cxx.o
+OBJS += backends/functional/smtlib.o
diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index 46ce88bd62c..c0444e7fe5a 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -214,10 +214,10 @@ class CxxComputeGraphFactory {
 		pending.set_function(CxxFunction(ID($$buf), pending.function().width));
 		pending.append_arg(node);
 	}
-	void declare_output(T node, IdString name) {
+	void declare_output(T node, IdString name, int) {
 		node.assign_key(name);
 	}
-	void declare_state(T node, IdString name) {
+	void declare_state(T node, IdString name, int) {
 		node.assign_key(name);
 	}
 	void suggest_name(T node, IdString name) {
diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
new file mode 100644
index 00000000000..f6af797919b
--- /dev/null
+++ b/backends/functional/smtlib.cc
@@ -0,0 +1,541 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/drivertools.h"
+#include "kernel/topo_scc.h"
+#include "kernel/functional.h"
+#include "kernel/graphtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SmtlibScope {
+	pool<std::string> used_names;
+	dict<IdString, std::string> name_map;
+
+	SmtlibScope() {
+		/*for(const char **p = reserved_keywords; *p != nullptr; p++)
+			reserve(*p);*/
+	}
+	void reserve(std::string name) {
+		used_names.insert(name);
+	}
+	std::string insert(IdString id) {
+		std::string str = RTLIL::unescape_id(id);
+		for(size_t i = 0; i < str.size(); i++)
+			if(!((unsigned char)str[i] < 0x80 && (isalnum(str[i]) || strchr("~!@$%^&*_-+=<>.?/", str[i]))))
+				str[i] = '_';
+		if(used_names.count(str) == 0){
+			used_names.insert(str);
+			name_map.insert({id, str});
+			return str;
+		}
+		for (int idx = 0 ; ; idx++){
+			std::string suffixed = str + "_" + std::to_string(idx);
+			if (used_names.count(suffixed) == 0) {
+				used_names.insert(suffixed);
+				if(name_map.count(id) == 0)
+					name_map.insert({id, suffixed});
+				return suffixed;
+			}
+		}
+	}
+	std::string operator[](IdString id) {
+		if(name_map.count(id) > 0)
+			return name_map[id];
+		else
+			return insert(id);
+	}
+};
+
+struct SmtlibWriter {
+	std::ostream &f;
+	SmtlibWriter(std::ostream &out) : f(out) {}
+	void printf(const char *fmt, ...)
+	{
+		va_list va;
+		va_start(va, fmt);
+		f << vstringf(fmt, va);
+		va_end(va);
+	}
+	template <typename T>
+	SmtlibWriter & operator <<(T &&arg) {
+		f << std::forward<T>(arg);
+		return *this;
+	}
+};
+
+struct Arg {
+    int n;
+    explicit Arg(int n_) : n(n_) {}
+	bool operator ==(Arg const &other) const { return n == other.n; }
+};
+
+class SExpr {
+	enum class Type {
+		None,
+		List,
+		Atom,
+		Arg,
+	};
+	Type type = Type::None;
+	union {
+		std::string atom_;
+		vector<SExpr> list_;
+        Arg arg_;
+	};
+    void set_none() {
+        switch(type) {
+        case Type::None: break;
+        case Type::Atom: atom_.~basic_string(); break;
+        case Type::List: list_.~vector(); break;
+        case Type::Arg: arg_.~Arg(); break;
+        }
+        type = Type::None;
+    }
+public:
+	SExpr() {}
+    SExpr(const char *atom) : type(Type::Atom), atom_(atom) {}
+	SExpr(std::string atom) : type(Type::Atom), atom_(atom) {}
+	SExpr(int n) : type(Type::Atom), atom_(std::to_string(n)) {}
+	SExpr(RTLIL::Const const & n) : type(Type::Atom) {
+		new(&atom_) std::string("#b");
+		atom_.reserve(n.size() + 2);
+		for (size_t i = n.size(); i > 0; i--)
+			if(n[i-1] == State::S1)
+				atom_ += "1";
+			else
+				atom_ += "0";
+	}
+	SExpr(vector<SExpr> &&list) : type(Type::List), list_(list) {}
+    SExpr(std::initializer_list<SExpr> list) : type(Type::List), list_(list) {}
+    SExpr(Arg arg) : type(Type::Arg), arg_(arg) {}
+    SExpr(SExpr const &other) { *this = other; }
+    SExpr(SExpr &&other) { *this = std::move(other); }
+    SExpr &operator =(SExpr const &other) {
+        set_none();
+        switch(other.type) {
+        case Type::None: break;
+        case Type::Atom: new(&atom_) std::string(other.atom_); break;
+        case Type::List: new(&list_) vector<SExpr>(other.list_); break;
+        case Type::Arg: new(&arg_) Arg(other.arg_); break;
+        }
+        type = other.type;
+        return *this;
+    }
+    SExpr &operator =(SExpr &&other) {
+        set_none();
+        switch(other.type) {
+        case Type::None: break;
+        case Type::Atom: new(&atom_) std::string(std::move(other.atom_)); break;
+        case Type::List: new(&list_) vector<SExpr>(std::move(other.list_)); break;
+        case Type::Arg: new(&arg_) Arg(std::move(other.arg_)); break;
+        }
+        type = other.type;
+        return *this;
+    }
+    ~SExpr() { set_none(); }
+	bool operator==(SExpr const &other) const {
+		if(type != other.type) return false;
+		switch(type) {
+		case Type::None: return true;
+		case Type::Atom: return atom_ == other.atom_;
+		case Type::List: return list_ == other.list_;
+		case Type::Arg: return arg_ == other.arg_;
+		}
+	}
+    bool is_none() const { return type == Type::None; }
+	bool is_atom() const { return type == Type::Atom; }
+	bool is_list() const { return type == Type::List; }
+    bool is_arg() const { return type == Type::Arg; }
+    std::string const &atom() const { log_assert(is_atom()); return atom_; }
+    std::vector<SExpr> const &list() const { log_assert(is_list()); return list_; }
+    Arg const &arg() const { log_assert(is_arg()); return arg_; }
+	unsigned int hash() const {
+		unsigned int inner;
+		switch(type) {
+		case Type::None: inner = 0; break;
+		case Type::Atom: inner = mkhash(atom_); break;
+		case Type::List: inner = mkhash(list_); break;
+		case Type::Arg: inner = arg_.n; break;
+		}
+		return mkhash((unsigned int) type, inner);
+	}
+	SExpr subst_args(std::vector<SExpr> const & args) const {
+		switch(type) {
+		case Type::None:
+		case Type::Atom:
+			return *this;
+		case Type::List: {
+			vector<SExpr> ret;
+			for(auto & a : list_)
+				ret.emplace_back(a.subst_args(args));
+			return SExpr(std::move(ret));
+		}
+		case Type::Arg:
+			if(arg_.n >= 1 && (size_t)arg_.n <= args.size())
+				return args[arg_.n - 1];
+			else
+				return *this;
+		}
+	}
+};
+
+std::ostream& operator << (std::ostream &os, SExpr const &s) {
+    if(s.is_atom())
+        os << s.atom();
+    else if(s.is_list()){
+        os << "(";
+        bool first = true;
+        for(auto &el: s.list()) {
+            if(!first) os << " ";
+            else first = false;
+            os << el;
+        }
+        os << ")";
+    }else if(s.is_arg())
+        os << "#" << s.arg().n;
+    else if(s.is_none())
+        os << "<none>";
+    else
+        os << "???";
+    return os;
+}
+
+struct SmtlibStruct {
+	SmtlibScope &scope;
+	std::string name;
+	idict<IdString> members;
+	vector<int> widths;
+	vector<std::string> accessors;
+	SmtlibStruct(std::string name, SmtlibScope &scope) : scope(scope), name(name) {
+	}
+	std::string insert(IdString field, int width) {
+		if(members.at(field, -1) == -1){
+			members(field);
+			scope.insert(field);
+			widths.push_back(width);
+			accessors.push_back(scope.insert(std::string("\\") + name + "_" + RTLIL::unescape_id(field)));
+		}
+		return scope[field];
+	}
+	void print(SmtlibWriter &f) {
+		f.printf("(declare-datatype %s ((%s\n", name.c_str(), name.c_str());
+		for (size_t i = 0; i < members.size(); i++)
+			f.printf("  (%s (_ BitVec %d))\n", accessors[i].c_str(), widths[i]);
+		f.printf(")))\n");
+	}
+	void print_value(SmtlibWriter &f, dict<IdString, SExpr> values, int indentation) {
+		std::string spaces(indentation, ' ');
+		f << spaces << "(" << name << "\n";
+		for (size_t i = 0; i < members.size(); i++)
+			f << spaces << "  " << values[members[i]] << "    ; " << RTLIL::unescape_id(members[i]) << "\n";
+		f << spaces << ")\n";
+	}
+	SExpr access(SExpr record, IdString member) {
+		int i = members.at(member);
+		return SExpr{accessors[i], record};
+	}
+	std::string operator[](IdString field) {
+		return scope[field];
+	}
+};
+
+struct Node {
+	SExpr expr;
+	int width;
+
+	Node(SExpr &&expr, int width) : expr(std::move(expr)), width(width) {}
+
+	bool operator==(Node const &other) const {
+		return expr == other.expr && width == other.width;
+	}
+
+	unsigned int hash() const {
+		return mkhash(expr.hash(), width);
+	}
+};
+
+typedef ComputeGraph<Node, int, IdString, IdString> SmtlibComputeGraph;
+
+struct SmtlibModule {
+	std::string name;
+	SmtlibScope global_scope;
+	SmtlibStruct input_struct;
+	SmtlibStruct output_struct;
+	SmtlibStruct state_struct;
+	SmtlibComputeGraph compute_graph;
+
+	SmtlibModule(std::string const &name) :
+		name(name),
+		input_struct(name + "_inputs", global_scope),
+		output_struct(name + "_outputs", global_scope),
+		state_struct(name + "_state", global_scope)
+	{ }
+	void calculate_compute_graph(RTLIL::Module *module);
+	void write(std::ostream &stream);
+};
+
+class SmtlibComputeGraphFactory {
+	SmtlibModule &module;
+	SmtlibComputeGraph &graph;
+	using T = SmtlibComputeGraph::Ref;
+	static bool is_single_output(IdString type)
+	{
+		auto it = yosys_celltypes.cell_types.find(type);
+		return it != yosys_celltypes.cell_types.end() && it->second.outputs.size() <= 1;
+	}
+	T node(SExpr &&expr, int width, std::initializer_list<T> args) {
+		return graph.add(Node(std::move(expr), width), 0, args);
+	}
+	T shift(const char *name, T a, T b, int y_width, int b_width, bool a_signed = false) {
+		int width = max(y_width, b_width);
+		T a_ = y_width < width ? extend(a, y_width, width, a_signed) : a;
+		T b_ = b_width < width ? extend(b, b_width, width, false) : b;
+		T y_ = node(SExpr {name, Arg(1), Arg(2)}, width, {a_, b_});
+		if(y_width < width)
+			return slice(y_, width, 0, y_width);
+		else
+			return y_;
+	}
+	SExpr from_bool(SExpr &&arg) {
+		return SExpr{"ite", std::move(arg), RTLIL::Const(State::S1), RTLIL::Const(State::S0)};
+	}
+	SExpr to_bool(SExpr &&arg) {
+		return SExpr{"=", std::move(arg), RTLIL::Const(State::S1)};
+	}
+	SExpr extract(SExpr &&arg, int offset, int out_width) {
+		return SExpr {SExpr {"_", "extract", offset + out_width - 1, offset}, std::move(arg)};
+	}
+public:
+	SmtlibComputeGraphFactory(SmtlibModule &mod) : module(mod), graph(mod.compute_graph) {}
+	T slice(T a, int in_width, int offset, int out_width) {
+		assert(offset + out_width <= in_width);
+		return node(extract(Arg(1), offset, out_width), out_width, {a});
+	}
+	T extend(T a, int in_width, int out_width, bool is_signed) {
+		assert(in_width < out_width);
+		if(is_signed)
+			return node(SExpr {SExpr {"_", "sign_extend", out_width - in_width}, Arg(1)}, out_width, {a});
+		else
+			return node(SExpr {SExpr {"_", "zero_extend", out_width - in_width}, Arg(1)}, out_width, {a});
+	}
+	T concat(T a, int a_width, T b, int b_width) {
+		return node(SExpr {"concat", Arg(1), Arg(2)}, a_width + b_width, {a, b});
+	}
+	T add(T a, T b, int width) { return node(SExpr {"bvadd", Arg(1), Arg(2)}, width, {a, b}); }
+	T sub(T a, T b, int width) { return node(SExpr {"bvsub", Arg(1), Arg(2)}, width, {a, b}); }
+	T bitwise_and(T a, T b, int width) { return node(SExpr {"bvand", Arg(1), Arg(2)}, width, {a, b}); }
+	T bitwise_or(T a, T b, int width) { return node(SExpr {"bvor", Arg(1), Arg(2)}, width, {a, b}); }
+	T bitwise_xor(T a, T b, int width) { return node(SExpr {"bvxor", Arg(1), Arg(2)}, width, {a, b}); }
+	T bitwise_not(T a, int width) { return node(SExpr {"bvnot", Arg(1)}, width, {a}); }
+	T neg(T a, int width) { return node(SExpr {"bvneg", Arg(1)}, width, {a}); }
+	T mux(T a, T b, T s, int width) { return node(SExpr {"ite", to_bool(Arg(1)), Arg(2), Arg(3)}, width, {s, a, b}); }
+	T pmux(T a, T b, T s, int width, int s_width) { 
+		T rv = a;
+		for(int i = 0; i < s_width; i++)
+			rv = node(SExpr {"ite", to_bool(extract(Arg(1), i, 1)), extract(Arg(2), width * i, width), Arg(3)}, width, {s, b, rv});
+		return rv;
+	}
+	T reduce_and(T a, int width) { return node(from_bool(SExpr {"=", Arg(1), RTLIL::Const(State::S1, width)}), 1, {a}); }
+	T reduce_or(T a, int width) { return node(from_bool(SExpr {"distinct", Arg(1), RTLIL::Const(State::S0, width)}), 1, {a}); }
+	T reduce_xor(T a, int) { return node(SExpr {"reduce_xor", Arg(1)}, 1, {a}); }
+	T eq(T a, T b, int) { return node(from_bool(SExpr {"=", Arg(1), Arg(2)}), 1, {a, b}); }
+	T ne(T a, T b, int) { return node(from_bool(SExpr {"distinct", Arg(1), Arg(2)}), 1, {a, b}); }
+	T gt(T a, T b, int) { return node(from_bool(SExpr {"bvsgt", Arg(1), Arg(2)}), 1, {a, b}); }
+	T ge(T a, T b, int) { return node(from_bool(SExpr {"bvsge", Arg(1), Arg(2)}), 1, {a, b}); }
+	T ugt(T a, T b, int) { return node(from_bool(SExpr {"bvugt", Arg(1), Arg(2)}), 1, {a, b}); }
+	T uge(T a, T b, int) { return node(from_bool(SExpr {"bvuge", Arg(1), Arg(2)}), 1, {a, b}); }
+	T logical_shift_left(T a, T b, int y_width, int b_width) { return shift("bvshl", a, b, y_width, b_width); }
+	T logical_shift_right(T a, T b, int y_width, int b_width) { return shift("bvlshl", a, b, y_width, b_width); }
+	T arithmetic_shift_right(T a, T b, int y_width, int b_width) { return shift("bvashr", a, b, y_width, b_width, true); }
+
+	T constant(RTLIL::Const value) { return node(SExpr(value), value.size(), {}); }
+	T input(IdString name, int width) {
+		module.input_struct.insert(name, width);
+		return node(module.input_struct.access("inputs", name), width, {});
+	}
+	T state(IdString name, int width) {
+		module.state_struct.insert(name, width);
+		return node(module.state_struct.access("current_state", name), width, {});
+	}
+	T cell_output(T cell, IdString type, IdString name, int width) {
+		if (is_single_output(type))
+			return cell;
+		else
+			return node(SExpr {"cell_output", Arg(1), RTLIL::unescape_id(name)}, width, {cell});
+	}
+	T multiple(vector<T> args, int width) {
+		vector<SExpr> expr;
+		expr.reserve(args.size() + 1);
+		expr.push_back("multiple");
+		for(size_t i = 1; i <= args.size(); i++)
+			expr.push_back(Arg(i));
+		return graph.add(Node(SExpr(std::move(expr)), width), 0, args);
+	}
+	T undriven(int width) {
+		return constant(RTLIL::Const(State::S0, width));
+		//return node(SExpr {"undriven"}, width, {});
+	}
+	T create_pending(int width) {
+		return node(SExpr(), width, {});
+	}
+	void update_pending(T pending, T node) {
+		assert(pending.function().expr.is_none());
+		pending.set_function(Node(Arg(1), pending.function().width));
+		pending.append_arg(node);
+	}
+	void declare_output(T node, IdString name, int width) {
+		module.output_struct.insert(name, width);
+		node.assign_key(name);
+	}
+	void declare_state(T node, IdString name, int width) {
+		module.state_struct.insert(name, width);
+		node.assign_key(name);
+	}
+	void suggest_name(T node, IdString name) {
+		node.sparse_attr() = name;
+	}
+};
+
+void SmtlibModule::calculate_compute_graph(RTLIL::Module *module)
+{
+	SmtlibComputeGraphFactory factory(*this);
+	ComputeGraphConstruction<SmtlibComputeGraph::Ref, SmtlibComputeGraphFactory> construction(factory);
+	construction.add_module(module);
+	construction.process_queue();
+
+	// Perform topo sort and detect SCCs
+	SmtlibComputeGraph::SccAdaptor compute_graph_scc(compute_graph);
+
+	bool scc = false;
+	std::vector<int> perm;
+	topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) {
+		perm.insert(perm.end(), begin, end);
+		if (end > begin + 1)
+		{
+			log_warning("SCC:");
+			for (int *i = begin; i != end; ++i)
+				log(" %d", *i);
+			log("\n");
+			scc = true;
+		}
+	}, /* sources_first */ true);
+	compute_graph.permute(perm);
+	if(scc) log_error("combinational loops, aborting\n");
+
+	// Forward $$buf
+	std::vector<int> alias;
+	perm.clear();
+
+	for (int i = 0; i < compute_graph.size(); ++i)
+	{
+		auto node = compute_graph[i];
+		if (node.function().expr == Arg(1) && node.arg(0).index() < i)
+		{
+			int target_index = alias[node.arg(0).index()];
+			auto target_node = compute_graph[perm[target_index]];
+			if(!target_node.has_sparse_attr() && node.has_sparse_attr())
+				target_node.sparse_attr() = node.sparse_attr();
+			alias.push_back(target_index);
+		}
+		else
+		{
+			alias.push_back(GetSize(perm));
+			perm.push_back(i);
+		}
+	}
+	compute_graph.permute(perm, alias);
+}
+
+void SmtlibModule::write(std::ostream &stream)
+{
+	SmtlibWriter f(stream);
+
+	idict<std::string> node_names;
+	SmtlibScope locals;
+	int paren_count = 0;
+
+	input_struct.print(f);
+	output_struct.print(f);
+	state_struct.print(f);
+
+	f << "(declare-datatypes ((Pair 2)) ((par (X Y) ((pair (first X) (second Y))))))\n";
+	f.printf("(define-fun %s_step ((inputs %s_inputs) (current_state %s_state)) (Pair %s_outputs %s_state)\n",
+		name.c_str(), name.c_str(), name.c_str(), name.c_str(), name.c_str());
+
+	for (int i = 0; i < compute_graph.size(); ++i)
+	{
+		auto ref = compute_graph[i];
+		std::string name;
+		if(ref.has_sparse_attr())
+			name = locals.insert(ref.sparse_attr());
+		else
+			name = locals.insert("\\n" + std::to_string(i));
+		node_names(name);
+		vector<SExpr> args;
+		args.reserve(ref.size());
+		for (int i = 0, end = ref.size(); i != end; ++i)
+			args.push_back(node_names[ref.arg(i).index()]);
+		f << "  (let " << SExpr{{SExpr{name, ref.function().expr.subst_args(args)}}} << "\n";
+		paren_count++;
+	}
+	dict<IdString, SExpr> outputs;
+	for(auto &a: compute_graph.keys())
+		outputs.insert({a.first, node_names[a.second]});
+	f.printf("    (pair \n");
+	output_struct.print_value(f, outputs, 6);
+	state_struct.print_value(f, outputs, 6);
+	f.printf("    )\n");
+	while(paren_count > 0){
+		int n = min(paren_count, 80);
+		f << "  " << std::string(n, ')') << "\n";
+		paren_count -= n;
+	}
+	f.printf(")\n");
+}
+
+struct FunctionalSmtlibBackend : public Backend
+{
+	FunctionalSmtlibBackend() : Backend("functional_smtlib", "convert design to SMTLIB using the functional backend") {}
+
+    void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+    }
+
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
+	{
+        log_header(design, "Executing Functional SMTLIB backend.\n");
+
+		size_t argidx = 1;
+		extra_args(f, filename, args, argidx, design);
+
+		for (auto module : design->selected_modules()) {
+            log("Dumping module `%s'.\n", module->name.c_str());
+			SmtlibModule smt(RTLIL::unescape_id(module->name));
+			smt.calculate_compute_graph(module);
+			smt.write(*f);
+		}
+	}
+} FunctionalSmtlibBackend;
+
+PRIVATE_NAMESPACE_END
diff --git a/kernel/graphtools.h b/kernel/graphtools.h
index 1a59ef1b537..adf4764c201 100644
--- a/kernel/graphtools.h
+++ b/kernel/graphtools.h
@@ -32,7 +32,7 @@ class CellSimplifier {
 	Factory &factory;
 	T reduce_shift_width(T b, int b_width, int y_width, int &reduced_b_width) {
 		log_assert(y_width > 0);
-		int new_width = sizeof(int) * 8 - __builtin_clz(y_width);
+		int new_width = ceil_log2(y_width + 1);
 		if (b_width <= new_width) {
 			reduced_b_width = b_width;
 			return b;
@@ -221,7 +221,7 @@ class ComputeGraphConstruction {
 		for (auto wire : module->wires()) {
 			if (wire->port_output) {
 				T node = enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width)));
-				factory.declare_output(node, wire->name);
+				factory.declare_output(node, wire->name, wire->width);
 			}
 		}
 	}
@@ -273,7 +273,7 @@ class ComputeGraphConstruction {
 								for (auto const &conn : cell->connections()) {
 									if (driver_map.celltypes.cell_input(cell->type, conn.first)) {
 										T node = enqueue(DriveChunkPort(cell, conn));
-										factory.declare_state(node, cell->name);
+										factory.declare_state(node, cell->name, port_chunk.width);
 									}
 								}
 							}

From 720429b1fd9eef2f87ec4b2d623964ca5b066b0c Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Wed, 12 Jun 2024 08:32:24 +0200
Subject: [PATCH 369/499] Add test_cell tests for C++ functional backend

---
 backends/functional/cxx.cc                    |  93 +++++++++----
 backends/functional/cxx_runtime/sim.h         |   1 +
 backends/functional/smtlib.cc                 |   1 +
 tests/functional/.gitignore                   |   4 +
 .../single_cells/rtlil/test_cell_add_00000.il |  17 +++
 .../single_cells/rtlil/test_cell_alu_00000.il |  25 ++++
 .../single_cells/rtlil/test_cell_and_00000.il |  17 +++
 .../rtlil/test_cell_bmux_00000.il             |  14 ++
 .../rtlil/test_cell_demux_00000.il            |  14 ++
 .../single_cells/rtlil/test_cell_div_00000.il |  17 +++
 .../rtlil/test_cell_divfloor_00000.il         |  17 +++
 .../single_cells/rtlil/test_cell_eq_00000.il  |  17 +++
 .../single_cells/rtlil/test_cell_fa_00000.il  |  17 +++
 .../single_cells/rtlil/test_cell_ge_00000.il  |  17 +++
 .../single_cells/rtlil/test_cell_gt_00000.il  |  17 +++
 .../single_cells/rtlil/test_cell_lcu_00000.il |  15 +++
 .../single_cells/rtlil/test_cell_le_00000.il  |  17 +++
 .../rtlil/test_cell_logic_and_00000.il        |  17 +++
 .../rtlil/test_cell_logic_not_00000.il        |  13 ++
 .../rtlil/test_cell_logic_or_00000.il         |  17 +++
 .../single_cells/rtlil/test_cell_lt_00000.il  |  17 +++
 .../single_cells/rtlil/test_cell_lut_00000.il |  12 ++
 .../rtlil/test_cell_macc_00000.il             |  17 +++
 .../single_cells/rtlil/test_cell_mod_00000.il |  17 +++
 .../rtlil/test_cell_modfloor_00000.il         |  17 +++
 .../single_cells/rtlil/test_cell_mul_00000.il |  17 +++
 .../single_cells/rtlil/test_cell_mux_00000.il |  15 +++
 .../single_cells/rtlil/test_cell_ne_00000.il  |  17 +++
 .../single_cells/rtlil/test_cell_neg_00000.il |  13 ++
 .../single_cells/rtlil/test_cell_not_00000.il |  13 ++
 .../single_cells/rtlil/test_cell_or_00000.il  |  17 +++
 .../single_cells/rtlil/test_cell_pos_00000.il |  13 ++
 .../rtlil/test_cell_reduce_and_00000.il       |  13 ++
 .../rtlil/test_cell_reduce_bool_00000.il      |  13 ++
 .../rtlil/test_cell_reduce_or_00000.il        |  13 ++
 .../rtlil/test_cell_reduce_xnor_00000.il      |  13 ++
 .../rtlil/test_cell_reduce_xor_00000.il       |  13 ++
 .../rtlil/test_cell_shift_00000.il            |  17 +++
 .../rtlil/test_cell_shiftx_00000.il           |  17 +++
 .../single_cells/rtlil/test_cell_shl_00000.il |  17 +++
 .../single_cells/rtlil/test_cell_shr_00000.il |  17 +++
 .../single_cells/rtlil/test_cell_sop_00000.il |  13 ++
 .../rtlil/test_cell_sshl_00000.il             |  17 +++
 .../rtlil/test_cell_sshr_00000.il             |  17 +++
 .../single_cells/rtlil/test_cell_sub_00000.il |  17 +++
 .../rtlil/test_cell_xnor_00000.il             |  17 +++
 .../single_cells/rtlil/test_cell_xor_00000.il |  17 +++
 tests/functional/single_cells/run-test.sh     |  83 ++++++++++++
 tests/functional/single_cells/vcd_harness.cc  | 123 ++++++++++++++++++
 49 files changed, 963 insertions(+), 26 deletions(-)
 create mode 100644 tests/functional/.gitignore
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_add_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_alu_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_and_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_bmux_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_demux_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_div_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_eq_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_fa_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_ge_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_gt_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_lcu_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_le_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_logic_not_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_logic_or_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_lt_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_lut_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_macc_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_mod_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_modfloor_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_mul_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_mux_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_ne_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_neg_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_not_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_or_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_pos_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_reduce_and_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_reduce_bool_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_reduce_or_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_reduce_xnor_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_reduce_xor_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_shift_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_shiftx_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_shl_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_shr_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_sop_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_sshl_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_sshr_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_sub_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_xnor_00000.il
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_xor_00000.il
 create mode 100755 tests/functional/single_cells/run-test.sh
 create mode 100644 tests/functional/single_cells/vcd_harness.cc

diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index c0444e7fe5a..03f33092cdc 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -17,6 +17,7 @@
  *
  */
 
+#include <cassert>
 #include "kernel/yosys.h"
 #include "kernel/drivertools.h"
 #include "kernel/topo_scc.h"
@@ -96,31 +97,70 @@ struct CxxWriter {
 };
 
 struct CxxStruct {
-	std::string name;
-	dict<IdString, std::string> types;
-	CxxScope scope;
-	CxxStruct(std::string name) : name(name) {
-		scope.reserve("out");
-		scope.reserve("dump");
-	}
-	void insert(IdString name, std::string type) {
-		scope.insert(name);
-		types.insert({name, type});
-	}
-	void print(CxxWriter &f) {
-		f.printf("struct %s {\n", name.c_str());
-		for (auto p : types) {
-			f.printf("\t%s %s;\n", p.second.c_str(), scope[p.first].c_str());
-		}
-		f.printf("\n\ttemplate <typename T> void dump(T &out) {\n");
-		for (auto p : types) {
-			f.printf("\t\tout(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope[p.first].c_str());
-		}
-		f.printf("\t}\n};\n\n");
-	}
-	std::string operator[](IdString field) {
-		return scope[field];
-	}
+  std::string name;
+  dict<IdString, std::string> types;
+  CxxScope scope;
+  bool generate_methods;
+  int count;
+  CxxStruct(std::string name, bool generate_methods = false, int count = 0) 
+    : name(name), generate_methods(generate_methods), count(count) {
+    scope.reserve("out");
+    scope.reserve("dump");
+  }
+  void insert(IdString name, std::string type) {
+    scope.insert(name);
+    types.insert({name, type});
+  }
+  void print(CxxWriter &f) {
+    f.printf("struct %s {\n", name.c_str());
+    for (auto p : types) {
+      f.printf("\t%s %s;\n", p.second.c_str(), scope[p.first].c_str());
+    }
+    f.printf("\n\ttemplate <typename T> void dump(T &out) const {\n");
+    for (auto p : types) {
+      f.printf("\t\tout(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope[p.first].c_str());
+    }
+    f.printf("\t}\n\n");
+
+    if (generate_methods) {
+      // Add size method
+      f.printf("\tint size() const {\n");
+      f.printf("\t\treturn %d;\n", count);
+      f.printf("\t}\n\n");
+
+      // Add get_input method
+      f.printf("\tstd::variant<%s> get_input(const int index) {\n", generate_variant_types().c_str());
+      f.printf("\t\tswitch (index) {\n");
+      int idx = 0;
+      for (auto p : types) {
+	f.printf("\t\t\tcase %d: return std::ref(%s);\n", idx, scope[p.first].c_str());
+	idx++;
+      }
+      f.printf("\t\t\tdefault: throw std::out_of_range(\"Invalid input index\");\n");
+      f.printf("\t\t}\n");
+      f.printf("\t}\n");
+    }
+    
+    f.printf("};\n\n");
+  };
+  std::string operator[](IdString field) {
+    return scope[field];
+  }
+  private:
+  std::string generate_variant_types() const {
+        std::set<std::string> unique_types;
+        for (const auto& p : types) {
+            unique_types.insert("std::reference_wrapper<" + p.second + ">");
+        }
+        std::ostringstream oss;
+        for (auto it = unique_types.begin(); it != unique_types.end(); ++it) {
+            if (it != unique_types.begin()) {
+                oss << ", ";
+            }
+            oss << *it;
+        }
+        return oss.str();
+  }
 };
 
 struct CxxFunction {
@@ -302,7 +342,8 @@ struct FunctionalCxxBackend : public Backend
 				state[ref.function().parameters.begin()->first] = ref.function().width;
 		}
 		f.printf("#include \"sim.h\"\n");
-		CxxStruct input_struct(name + "_Inputs");
+		f.printf("#include <variant>\n");
+		CxxStruct input_struct(name + "_Inputs", true, inputs.size());
 		for (auto const &input : inputs)
 			input_struct.insert(input.first, "Signal<" + std::to_string(input.second) + ">");
 		CxxStruct output_struct(name + "_Outputs");
diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h
index 4e7d9b60142..1e5a282639c 100644
--- a/backends/functional/cxx_runtime/sim.h
+++ b/backends/functional/cxx_runtime/sim.h
@@ -20,6 +20,7 @@
 #ifndef SIM_H
 #define SIM_H
 
+#include <cassert>
 #include <array>
 
 template<size_t n>
diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index f6af797919b..cd11111b9d8 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -17,6 +17,7 @@
  *
  */
 
+#include <cassert>
 #include "kernel/yosys.h"
 #include "kernel/drivertools.h"
 #include "kernel/topo_scc.h"
diff --git a/tests/functional/.gitignore b/tests/functional/.gitignore
new file mode 100644
index 00000000000..543226b49dc
--- /dev/null
+++ b/tests/functional/.gitignore
@@ -0,0 +1,4 @@
+my_module_cxxrtl.cc
+my_module_functional_cxx.cc
+vcd_harness
+*.vcd
\ No newline at end of file
diff --git a/tests/functional/single_cells/rtlil/test_cell_add_00000.il b/tests/functional/single_cells/rtlil/test_cell_add_00000.il
new file mode 100644
index 00000000000..531dabe41fa
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_add_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 5 input 1 \A
+  wire width 4 input 2 \B
+  wire width 6 output 3 \Y
+  cell $add \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 5
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_alu_00000.il b/tests/functional/single_cells/rtlil/test_cell_alu_00000.il
new file mode 100644
index 00000000000..ebdd3b7343b
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_alu_00000.il
@@ -0,0 +1,25 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 8 input 1 \A
+  wire width 7 input 2 \B
+  wire input 3 \BI
+  wire input 4 \CI
+  wire width 6 output 5 \CO
+  wire width 6 output 6 \X
+  wire width 6 output 7 \Y
+  cell $alu \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 8
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \BI \BI
+    connect \CI \CI
+    connect \CO \CO
+    connect \X \X
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_and_00000.il b/tests/functional/single_cells/rtlil/test_cell_and_00000.il
new file mode 100644
index 00000000000..2578f60b774
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_and_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 2 input 1 \A
+  wire width 3 input 2 \B
+  wire width 2 output 3 \Y
+  cell $and \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_bmux_00000.il b/tests/functional/single_cells/rtlil/test_cell_bmux_00000.il
new file mode 100644
index 00000000000..1b613bd698c
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_bmux_00000.il
@@ -0,0 +1,14 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 8 input 1 \A
+  wire input 2 \S
+  wire width 4 output 3 \Y
+  cell $bmux \UUT
+    parameter \S_WIDTH 1
+    parameter \WIDTH 4
+    connect \A \A
+    connect \S \S
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_demux_00000.il b/tests/functional/single_cells/rtlil/test_cell_demux_00000.il
new file mode 100644
index 00000000000..dbe2dee62ac
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_demux_00000.il
@@ -0,0 +1,14 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 6 input 1 \A
+  wire width 5 input 2 \S
+  wire width 192 output 3 \Y
+  cell $demux \UUT
+    parameter \S_WIDTH 5
+    parameter \WIDTH 6
+    connect \A \A
+    connect \S \S
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_div_00000.il b/tests/functional/single_cells/rtlil/test_cell_div_00000.il
new file mode 100644
index 00000000000..6f278a7a079
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_div_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 4 input 1 \A
+  wire width 6 input 2 \B
+  wire output 3 \Y
+  cell $div \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 6
+    parameter \Y_WIDTH 1
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il b/tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il
new file mode 100644
index 00000000000..67fce36b331
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 4 input 1 \A
+  wire width 4 input 2 \B
+  wire width 6 output 3 \Y
+  cell $divfloor \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_eq_00000.il b/tests/functional/single_cells/rtlil/test_cell_eq_00000.il
new file mode 100644
index 00000000000..06fef02b5b2
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_eq_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 5 input 1 \A
+  wire input 2 \B
+  wire width 4 output 3 \Y
+  cell $eq \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 5
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_fa_00000.il b/tests/functional/single_cells/rtlil/test_cell_fa_00000.il
new file mode 100644
index 00000000000..97f0eb0297d
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_fa_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire input 1 \A
+  wire input 2 \B
+  wire input 3 \C
+  wire output 4 \X
+  wire output 5 \Y
+  cell $fa \UUT
+    parameter \WIDTH 1
+    connect \A \A
+    connect \B \B
+    connect \C \C
+    connect \X \X
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_ge_00000.il b/tests/functional/single_cells/rtlil/test_cell_ge_00000.il
new file mode 100644
index 00000000000..0ac72e9433d
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_ge_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 3 input 1 \A
+  wire width 7 input 2 \B
+  wire width 6 output 3 \Y
+  cell $ge \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_gt_00000.il b/tests/functional/single_cells/rtlil/test_cell_gt_00000.il
new file mode 100644
index 00000000000..d4498d36f9e
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_gt_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 7 input 1 \A
+  wire width 3 input 2 \B
+  wire width 4 output 3 \Y
+  cell $gt \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_lcu_00000.il b/tests/functional/single_cells/rtlil/test_cell_lcu_00000.il
new file mode 100644
index 00000000000..e1bda0b433c
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_lcu_00000.il
@@ -0,0 +1,15 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire input 1 \CI
+  wire width 2 output 2 \CO
+  wire width 2 input 3 \G
+  wire width 2 input 4 \P
+  cell $lcu \UUT
+    parameter \WIDTH 2
+    connect \CI \CI
+    connect \CO \CO
+    connect \G \G
+    connect \P \P
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_le_00000.il b/tests/functional/single_cells/rtlil/test_cell_le_00000.il
new file mode 100644
index 00000000000..609d99ce8a4
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_le_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 5 input 1 \A
+  wire width 4 input 2 \B
+  wire width 6 output 3 \Y
+  cell $le \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 5
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il b/tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il
new file mode 100644
index 00000000000..2eae6e3fcb1
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 2 input 1 \A
+  wire width 7 input 2 \B
+  wire output 3 \Y
+  cell $logic_and \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 1
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_logic_not_00000.il b/tests/functional/single_cells/rtlil/test_cell_logic_not_00000.il
new file mode 100644
index 00000000000..c7898491ca5
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_logic_not_00000.il
@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 3 input 1 \A
+  wire width 8 output 2 \Y
+  cell $logic_not \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 8
+    connect \A \A
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_logic_or_00000.il b/tests/functional/single_cells/rtlil/test_cell_logic_or_00000.il
new file mode 100644
index 00000000000..7a1ef6cbda0
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_logic_or_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 8 input 1 \A
+  wire width 7 input 2 \B
+  wire width 2 output 3 \Y
+  cell $logic_or \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 8
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_lt_00000.il b/tests/functional/single_cells/rtlil/test_cell_lt_00000.il
new file mode 100644
index 00000000000..fd3ee1f8bad
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_lt_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 8 input 1 \A
+  wire width 5 input 2 \B
+  wire width 6 output 3 \Y
+  cell $lt \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 8
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_lut_00000.il b/tests/functional/single_cells/rtlil/test_cell_lut_00000.il
new file mode 100644
index 00000000000..7c4882bb61a
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_lut_00000.il
@@ -0,0 +1,12 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 2 input 1 \A
+  wire output 2 \Y
+  cell $lut \UUT
+    parameter \LUT 4'1111
+    parameter \WIDTH 2
+    connect \A \A
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_macc_00000.il b/tests/functional/single_cells/rtlil/test_cell_macc_00000.il
new file mode 100644
index 00000000000..66b51634e97
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_macc_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 3 input 1 \A
+  wire width 0 input 2 \B
+  wire width 2 output 3 \Y
+  cell $macc \UUT
+    parameter \A_WIDTH 3
+    parameter \B_WIDTH 0
+    parameter \CONFIG 10'0110000010
+    parameter \CONFIG_WIDTH 10
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B { }
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_mod_00000.il b/tests/functional/single_cells/rtlil/test_cell_mod_00000.il
new file mode 100644
index 00000000000..a484918f05c
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_mod_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 6 input 1 \A
+  wire width 8 input 2 \B
+  wire width 2 output 3 \Y
+  cell $mod \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 8
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_modfloor_00000.il b/tests/functional/single_cells/rtlil/test_cell_modfloor_00000.il
new file mode 100644
index 00000000000..6cd00aeea5d
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_modfloor_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 5 input 1 \A
+  wire width 7 input 2 \B
+  wire width 4 output 3 \Y
+  cell $modfloor \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 5
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_mul_00000.il b/tests/functional/single_cells/rtlil/test_cell_mul_00000.il
new file mode 100644
index 00000000000..c77aaffb87e
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_mul_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 6 input 1 \A
+  wire width 2 input 2 \B
+  wire width 5 output 3 \Y
+  cell $mul \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 5
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_mux_00000.il b/tests/functional/single_cells/rtlil/test_cell_mux_00000.il
new file mode 100644
index 00000000000..3fc52ac7716
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_mux_00000.il
@@ -0,0 +1,15 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 4 input 1 \A
+  wire width 4 input 2 \B
+  wire input 3 \S
+  wire width 4 output 4 \Y
+  cell $mux \UUT
+    parameter \WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \S \S
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_ne_00000.il b/tests/functional/single_cells/rtlil/test_cell_ne_00000.il
new file mode 100644
index 00000000000..47ba31397ed
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_ne_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 7 input 1 \A
+  wire width 5 input 2 \B
+  wire width 4 output 3 \Y
+  cell $ne \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_neg_00000.il b/tests/functional/single_cells/rtlil/test_cell_neg_00000.il
new file mode 100644
index 00000000000..ee4273508d1
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_neg_00000.il
@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 2 input 1 \A
+  wire width 5 output 2 \Y
+  cell $neg \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \Y_WIDTH 5
+    connect \A \A
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_not_00000.il b/tests/functional/single_cells/rtlil/test_cell_not_00000.il
new file mode 100644
index 00000000000..9281ded0dfa
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_not_00000.il
@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 7 input 1 \A
+  wire width 7 output 2 \Y
+  cell $not \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 7
+    parameter \Y_WIDTH 7
+    connect \A \A
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_or_00000.il b/tests/functional/single_cells/rtlil/test_cell_or_00000.il
new file mode 100644
index 00000000000..100ea42cd38
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_or_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 7 input 1 \A
+  wire input 2 \B
+  wire width 2 output 3 \Y
+  cell $or \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_pos_00000.il b/tests/functional/single_cells/rtlil/test_cell_pos_00000.il
new file mode 100644
index 00000000000..182f0acd38f
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_pos_00000.il
@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire input 1 \A
+  wire width 3 output 2 \Y
+  cell $pos \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 3
+    connect \A \A
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_reduce_and_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_and_00000.il
new file mode 100644
index 00000000000..079ed33ade5
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_reduce_and_00000.il
@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 4 input 1 \A
+  wire width 5 output 2 \Y
+  cell $reduce_and \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 5
+    connect \A \A
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_reduce_bool_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_bool_00000.il
new file mode 100644
index 00000000000..a417179c818
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_reduce_bool_00000.il
@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire input 1 \A
+  wire width 2 output 2 \Y
+  cell $reduce_bool \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_reduce_or_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_or_00000.il
new file mode 100644
index 00000000000..881c6dfe3a1
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_reduce_or_00000.il
@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 2 input 1 \A
+  wire width 7 output 2 \Y
+  cell $reduce_or \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \Y_WIDTH 7
+    connect \A \A
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_reduce_xnor_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_xnor_00000.il
new file mode 100644
index 00000000000..c06562729ea
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_reduce_xnor_00000.il
@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 4 input 1 \A
+  wire width 4 output 2 \Y
+  cell $reduce_xnor \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_reduce_xor_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_xor_00000.il
new file mode 100644
index 00000000000..428d2ea87a2
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_reduce_xor_00000.il
@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 4 input 1 \A
+  wire output 2 \Y
+  cell $reduce_xor \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A \A
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_shift_00000.il b/tests/functional/single_cells/rtlil/test_cell_shift_00000.il
new file mode 100644
index 00000000000..f82a2a79df7
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_shift_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire input 1 \A
+  wire width 6 input 2 \B
+  wire width 4 output 3 \Y
+  cell $shift \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 6
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_shiftx_00000.il b/tests/functional/single_cells/rtlil/test_cell_shiftx_00000.il
new file mode 100644
index 00000000000..b89ac5bef91
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_shiftx_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire input 1 \A
+  wire width 5 input 2 \B
+  wire width 3 output 3 \Y
+  cell $shiftx \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 3
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_shl_00000.il b/tests/functional/single_cells/rtlil/test_cell_shl_00000.il
new file mode 100644
index 00000000000..1cfee2a52b5
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_shl_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 8 input 1 \A
+  wire width 2 input 2 \B
+  wire width 3 output 3 \Y
+  cell $shl \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 8
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 3
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_shr_00000.il b/tests/functional/single_cells/rtlil/test_cell_shr_00000.il
new file mode 100644
index 00000000000..35dd379099c
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_shr_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 7 input 1 \A
+  wire width 6 input 2 \B
+  wire width 4 output 3 \Y
+  cell $shr \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 6
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_sop_00000.il b/tests/functional/single_cells/rtlil/test_cell_sop_00000.il
new file mode 100644
index 00000000000..df0f8f20abe
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_sop_00000.il
@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 8 input 1 \A
+  wire output 2 \Y
+  cell $sop \UUT
+    parameter \DEPTH 8
+    parameter \TABLE 128'10010000100100000101101010001001101000101010010100010000010100000101010100000001001010010110101010101010101000100100011001000110
+    parameter \WIDTH 8
+    connect \A \A
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_sshl_00000.il b/tests/functional/single_cells/rtlil/test_cell_sshl_00000.il
new file mode 100644
index 00000000000..798288754ce
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_sshl_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 5 input 1 \A
+  wire width 3 input 2 \B
+  wire width 6 output 3 \Y
+  cell $sshl \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 5
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_sshr_00000.il b/tests/functional/single_cells/rtlil/test_cell_sshr_00000.il
new file mode 100644
index 00000000000..3f59a693f24
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_sshr_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 3 input 1 \A
+  wire width 2 input 2 \B
+  wire width 2 output 3 \Y
+  cell $sshr \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_sub_00000.il b/tests/functional/single_cells/rtlil/test_cell_sub_00000.il
new file mode 100644
index 00000000000..cb9ec2f7904
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_sub_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 6 input 1 \A
+  wire width 6 input 2 \B
+  wire width 6 output 3 \Y
+  cell $sub \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 6
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_xnor_00000.il b/tests/functional/single_cells/rtlil/test_cell_xnor_00000.il
new file mode 100644
index 00000000000..85bd7d239df
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_xnor_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 7 input 1 \A
+  wire width 8 input 2 \B
+  wire width 7 output 3 \Y
+  cell $xnor \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 8
+    parameter \Y_WIDTH 7
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/rtlil/test_cell_xor_00000.il b/tests/functional/single_cells/rtlil/test_cell_xor_00000.il
new file mode 100644
index 00000000000..2359698b55b
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_xor_00000.il
@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 6 input 1 \A
+  wire width 2 input 2 \B
+  wire width 8 output 3 \Y
+  cell $xor \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 8
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end
diff --git a/tests/functional/single_cells/run-test.sh b/tests/functional/single_cells/run-test.sh
new file mode 100755
index 00000000000..67cdf4a11c4
--- /dev/null
+++ b/tests/functional/single_cells/run-test.sh
@@ -0,0 +1,83 @@
+#!/bin/bash
+
+# Initialize an array to store the names of failing RTLIL files and their failure types
+declare -A failing_files
+# Initialize an array to store the names of successful RTLIL files
+declare -A successful_files
+
+# Function to run the test on a given RTLIL file
+run_test() {
+    # Define the common variable for the relative path
+    BASE_PATH="../../../"
+
+    local rtlil_file=$1
+
+    # Extract the base name without extension
+    local base_name=$(basename "$rtlil_file" .v)
+    
+    # Run yosys to process each RTLIL file
+    if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; write_functional_cxx my_module_functional_cxx.cc"; then
+        echo "Yosys processed $rtlil_file successfully."
+        
+        # Compile the generated C++ files with vcd_harness.cpp
+        if ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cc -I ${BASE_PATH}backends/functional/cxx_runtime/ -std=c++17 -o vcd_harness; then
+            echo "Compilation successful."
+            # Generate VCD files with base_name
+            if ./vcd_harness ${base_name}_functional_cxx.vcd; then
+		
+		# Run yosys to process each RTLIL file
+		if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -r ${base_name}_functional_cxx.vcd -scope gold -vcd ${base_name}_yosys_sim.vcd -timescale 1us -sim-gold"; then
+		    echo "Yosys sim $rtlil_file successfully."
+		    successful_files["$rtlil_file"]="Success"
+		else
+		    ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys_sim.vcd -r ${base_name}_functional_cxx.vcd -scope gold -timescale 1us"
+		    echo "Yosys simulation of $rtlil_file failed. There is a discrepancy with functional cxx"
+		    failing_files["$rtlil_file"]="Yosys sim failure"
+		fi
+		
+            else
+		echo "Failed to generate VCD files for $rtlil_file."
+		failing_files["$rtlil_file"]="VCD generation failure"
+            fi
+	else
+	    echo "Failed to compile harness for $rtlil_file."
+	    failing_files["$rtlil_file"]="Compilation failure"
+	fi
+	else
+            echo "Yosys failed to process $rtlil_file."
+            failing_files["$rtlil_file"]="Yosys failure"
+	fi
+}
+
+# Main function to run all tests
+run_all_tests() {
+    # Loop through all RTLIL files in the rtlil directory
+    for rtlil_file in rtlil/*.il; do
+        run_test "$rtlil_file"
+    done
+
+    # Check if the array of failing files is empty
+    if [ ${#failing_files[@]} -eq 0 ]; then
+        echo "All files passed."
+	echo "The following files passed:"
+        for file in "${!successful_files[@]}"; do
+            echo "$file"
+        done
+        return 0
+    else
+        echo "The following files failed:"
+        for file in "${!failing_files[@]}"; do
+            echo "$file: ${failing_files[$file]}"
+        done
+	echo "The following files passed:"
+        for file in "${!successful_files[@]}"; do
+            echo "$file"
+        done
+        return 1
+    fi
+}
+
+# If the script is being sourced, do not execute the tests
+if [[ "${BASH_SOURCE[0]}" == "${0}" ]]; then
+    run_all_tests
+fi
diff --git a/tests/functional/single_cells/vcd_harness.cc b/tests/functional/single_cells/vcd_harness.cc
new file mode 100644
index 00000000000..10ab10e428e
--- /dev/null
+++ b/tests/functional/single_cells/vcd_harness.cc
@@ -0,0 +1,123 @@
+#include <cstdio>
+#include <iostream>
+#include <fstream>
+#include <random>
+
+#include "my_module_functional_cxx.cc"
+
+struct DumpHeader {
+  std::ofstream &ofs;
+  DumpHeader(std::ofstream &ofs) : ofs(ofs) {}
+  template <size_t n>
+  void operator()(const char *name, Signal<n> value) {
+    ofs << "$var wire " << n << " " << name[0] << " " << name << " $end\n";
+  }
+};
+
+struct Dump {
+  std::ofstream &ofs;
+  Dump(std::ofstream &ofs) : ofs(ofs) {}
+  template <size_t n>
+  void operator()(const char *name, Signal<n> value) {
+    // Bit
+    if (n == 1) {
+      ofs << (value[0] ? '1' : '0');
+      ofs << name[0] << "\n";
+      return;
+    }
+    // vector (multi-bit) signals
+    ofs << "b";
+    for (size_t i = n; i-- > 0;)
+      ofs << (value[i] ? '1' : '0');
+    ofs << " " << name[0] << "\n";
+  }
+};
+
+// Function to set all values in a signal to false
+template<std::size_t n>
+void set_all_false(Signal<n>& signal) {
+  std::fill(signal.begin(), signal.end(), false);
+}
+
+template<std::size_t n>
+void set_all_random(Signal<n>& signal) {
+  std::random_device rd;  // Random device for seeding
+  std::mt19937 gen(rd()); // Mersenne Twister engine
+  std::bernoulli_distribution dist(0.5); // 50-50 distribution
+
+  for (auto& value : signal) {
+    value = dist(gen); // Set each value to a random boolean
+  }
+}
+
+int main(int argc, char **argv)
+{
+  if (argc != 2) {
+    std::cerr << "Usage: " << argv[0] << " <functional_vcd_filename>\n";
+    return 1;
+  }
+
+  const std::string functional_vcd_filename = argv[1];
+
+  constexpr int steps = 10;
+  constexpr int number_timescale = 1;
+  const std::string units_timescale = "us";
+  gold_Inputs inputs;
+  gold_Outputs outputs;
+  gold_State state;
+  gold_State next_state;
+
+  std::ofstream vcd_file(functional_vcd_filename);
+
+  vcd_file << "$timescale " << number_timescale << " " << units_timescale << " $end\n";
+  vcd_file << "$scope module gold $end\n";
+  {
+    DumpHeader d(vcd_file);
+    inputs.dump(d);
+    outputs.dump(d);
+    state.dump(d);
+  }
+  vcd_file << "$enddefinitions $end\n$dumpvars\n";
+  vcd_file << "#0\n";
+  // Set all signals to false
+  for (int i = 0; i < inputs.size(); ++i) {
+    auto input_variant = inputs.get_input(i);
+    std::visit([](auto& signal_ref) {
+      set_all_false(signal_ref.get());
+    }, input_variant);
+  }
+     
+  gold(inputs, outputs, state, next_state);
+  {
+    Dump d(vcd_file);
+    inputs.dump(d);
+    outputs.dump(d);
+    state.dump(d);
+  }
+    
+  for (int step = 0; step < steps; ++step) {
+    // Functional backend cxx
+    vcd_file << "#" << (step + 1) << "\n";
+    // Set all signals to random
+    for (int i = 0; i < inputs.size(); ++i) {
+      auto input_variant = inputs.get_input(i);
+      std::visit([](auto& signal_ref) {
+	set_all_random(signal_ref.get());
+      }, input_variant);
+    }
+
+    gold(inputs, outputs, state, next_state);
+    {
+      Dump d(vcd_file);
+      inputs.dump(d);
+      outputs.dump(d);
+      state.dump(d);
+    }
+	
+    state = next_state;
+  }
+
+  vcd_file.close();
+
+  return 0;
+}

From 76371d177fa759c000778a0969b2333fbc4dc594 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Wed, 12 Jun 2024 09:23:44 +0200
Subject: [PATCH 370/499] Change assert to log_assert

---
 backends/functional/cxx.cc            |  9 ++++-----
 backends/functional/cxx_runtime/sim.h | 11 +++++------
 backends/functional/smtlib.cc         |  7 +++----
 3 files changed, 12 insertions(+), 15 deletions(-)

diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index 03f33092cdc..b42e20ca718 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -17,7 +17,6 @@
  *
  */
 
-#include <cassert>
 #include "kernel/yosys.h"
 #include "kernel/drivertools.h"
 #include "kernel/topo_scc.h"
@@ -38,7 +37,7 @@ const char *reserved_keywords[] = {
 	"int","long","mutable","namespace","new","noexcept","not","not_eq",
 	"nullptr","operator","or","or_eq","private","protected","public",
 	"reflexpr","register","reinterpret_cast","requires","return","short",
-	"signed","sizeof","static","static_assert","static_cast","struct",
+	"signed","sizeof","static","static_log_assert","static_cast","struct",
 	"switch","synchronized","template","this","thread_local","throw",
 	"true","try","typedef","typeid","typename","union","unsigned",
 	"using","virtual","void","volatile","wchar_t","while","xor","xor_eq",
@@ -193,11 +192,11 @@ class CxxComputeGraphFactory {
 public:
 	CxxComputeGraphFactory(CxxComputeGraph &g) : graph(g) {}
 	T slice(T a, int in_width, int offset, int out_width) {
-		assert(offset + out_width <= in_width);
+		log_assert(offset + out_width <= in_width);
 		return graph.add(CxxFunction(ID($$slice), out_width, {{ID(offset), offset}}), 0, std::array<T, 1>{a});
 	}
 	T extend(T a, int in_width, int out_width, bool is_signed) {
-		assert(in_width < out_width);
+		log_assert(in_width < out_width);
 		if(is_signed)
 			return graph.add(CxxFunction(ID($sign_extend), out_width, {{ID(WIDTH), out_width}}), 0, std::array<T, 1>{a});
 		else
@@ -250,7 +249,7 @@ class CxxComputeGraphFactory {
 		return graph.add(CxxFunction(ID($$pending), width), 0);
 	}
 	void update_pending(T pending, T node) {
-		assert(pending.function().name == ID($$pending));
+		log_assert(pending.function().name == ID($$pending));
 		pending.set_function(CxxFunction(ID($$buf), pending.function().width));
 		pending.append_arg(node);
 	}
diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h
index 1e5a282639c..75d045ccf35 100644
--- a/backends/functional/cxx_runtime/sim.h
+++ b/backends/functional/cxx_runtime/sim.h
@@ -20,7 +20,6 @@
 #ifndef SIM_H
 #define SIM_H
 
-#include <cassert>
 #include <array>
 
 template<size_t n>
@@ -250,7 +249,7 @@ Signal<n> $shl(Signal<na> const& a, Signal<nb> const &b)
 {
     if(nb >= sizeof(int) * 8 - 1)
         for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
-            assert(!b[i]);
+            log_assert(!b[i]);
     size_t amount = as_int(b);
     Signal<n> ret = $const<n>(0);
     if(amount < n){
@@ -267,7 +266,7 @@ Signal<n> $shr(Signal<n> const& a, Signal<nb> const &b)
 {
     if(nb >= sizeof(int) * 8 - 1)
         for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
-            assert(!b[i]);
+            log_assert(!b[i]);
     size_t amount = as_int(b);
     Signal<n> ret;
     for (size_t i = 0; i < n; i++) {
@@ -284,7 +283,7 @@ Signal<n> $asr(Signal<n> const& a, Signal<nb> const &b)
 {
     if(nb >= sizeof(int) * 8 - 1)
         for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
-            assert(!b[i]);
+            log_assert(!b[i]);
     size_t amount = as_int(b);
     Signal<n> ret;
     for (size_t i = 0; i < n; i++) {
@@ -345,7 +344,7 @@ Signal<n+m> concat(Signal<n> const& a, Signal<m> const& b)
 template<size_t n, size_t m>
 Signal<n> $zero_extend(Signal<m> const& a)
 {
-    assert(n >= m);
+    log_assert(n >= m);
     Signal<n> ret;
     std::copy(a.begin(), a.end(), ret.begin());
     for(size_t i = m; i < n; i++)
@@ -356,7 +355,7 @@ Signal<n> $zero_extend(Signal<m> const& a)
 template<size_t n, size_t m>
 Signal<n> $sign_extend(Signal<m> const& a)
 {
-    assert(n >= m);
+    log_assert(n >= m);
     Signal<n> ret;
     std::copy(a.begin(), a.end(), ret.begin());
     for(size_t i = m; i < n; i++)
diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index cd11111b9d8..7a283cccf26 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -17,7 +17,6 @@
  *
  */
 
-#include <cassert>
 #include "kernel/yosys.h"
 #include "kernel/drivertools.h"
 #include "kernel/topo_scc.h"
@@ -328,11 +327,11 @@ class SmtlibComputeGraphFactory {
 public:
 	SmtlibComputeGraphFactory(SmtlibModule &mod) : module(mod), graph(mod.compute_graph) {}
 	T slice(T a, int in_width, int offset, int out_width) {
-		assert(offset + out_width <= in_width);
+		log_assert(offset + out_width <= in_width);
 		return node(extract(Arg(1), offset, out_width), out_width, {a});
 	}
 	T extend(T a, int in_width, int out_width, bool is_signed) {
-		assert(in_width < out_width);
+		log_assert(in_width < out_width);
 		if(is_signed)
 			return node(SExpr {SExpr {"_", "sign_extend", out_width - in_width}, Arg(1)}, out_width, {a});
 		else
@@ -399,7 +398,7 @@ class SmtlibComputeGraphFactory {
 		return node(SExpr(), width, {});
 	}
 	void update_pending(T pending, T node) {
-		assert(pending.function().expr.is_none());
+		log_assert(pending.function().expr.is_none());
 		pending.set_function(Node(Arg(1), pending.function().width));
 		pending.append_arg(node);
 	}

From 7b29d177ac511cd68a4c51001e6ad3522268b08e Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Wed, 12 Jun 2024 11:27:10 +0100
Subject: [PATCH 371/499] add support for memories to c++ and smtlib functional
 backends

---
 backends/functional/cxx.cc            | 110 ++++++++++++++++++--------
 backends/functional/cxx_runtime/sim.h |  19 +++++
 backends/functional/smtlib.cc         |  72 ++++++++++++++---
 kernel/drivertools.h                  |   7 ++
 kernel/graphtools.h                   |  68 ++++++++++++++--
 5 files changed, 226 insertions(+), 50 deletions(-)

diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index b42e20ca718..08d9ba7914b 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -83,6 +83,41 @@ struct CxxScope {
 	}
 };
 
+struct CxxType {
+	bool _is_memory;
+	int _width;
+	int _addr_width;
+public:
+	CxxType() : _is_memory(false), _width(0), _addr_width(0) { }
+	CxxType(int width) : _is_memory(false), _width(width), _addr_width(0) { }
+	CxxType(int addr_width, int data_width) : _is_memory(true), _width(data_width), _addr_width(addr_width) { }
+	static CxxType signal(int width) { return CxxType(width); }
+	static CxxType memory(int addr_width, int data_width) { return CxxType(addr_width, data_width); }
+	bool is_signal() const { return !_is_memory; }
+	bool is_memory() const { return _is_memory; }
+	int width() const { log_assert(is_signal()); return _width; }
+	int addr_width() const { log_assert(is_memory()); return _addr_width; }
+	int data_width() const { log_assert(is_memory()); return _width; }
+	std::string to_string() const {
+		if(_is_memory) {
+			return stringf("Memory<%d, %d>", addr_width(), data_width());
+		} else {
+			return stringf("Signal<%d>", width());
+		}
+	}
+	bool operator ==(CxxType const& other) const {
+		if(_is_memory != other._is_memory) return false;
+		if(_is_memory && _addr_width != other._addr_width) return false;
+		return _width == other._width;
+	}
+	unsigned int hash() const {
+		if(_is_memory)
+			return mkhash(1, mkhash(_width, _addr_width));
+		else
+			return mkhash(0, _width);
+	}
+};
+
 struct CxxWriter {
 	std::ostream &f;
 	CxxWriter(std::ostream &out) : f(out) {}
@@ -97,7 +132,7 @@ struct CxxWriter {
 
 struct CxxStruct {
   std::string name;
-  dict<IdString, std::string> types;
+  dict<IdString, CxxType> types;
   CxxScope scope;
   bool generate_methods;
   int count;
@@ -106,14 +141,14 @@ struct CxxStruct {
     scope.reserve("out");
     scope.reserve("dump");
   }
-  void insert(IdString name, std::string type) {
+  void insert(IdString name, CxxType type) {
     scope.insert(name);
     types.insert({name, type});
   }
   void print(CxxWriter &f) {
     f.printf("struct %s {\n", name.c_str());
     for (auto p : types) {
-      f.printf("\t%s %s;\n", p.second.c_str(), scope[p.first].c_str());
+      f.printf("\t%s %s;\n", p.second.to_string().c_str(), scope[p.first].c_str());
     }
     f.printf("\n\ttemplate <typename T> void dump(T &out) const {\n");
     for (auto p : types) {
@@ -149,7 +184,7 @@ struct CxxStruct {
   std::string generate_variant_types() const {
         std::set<std::string> unique_types;
         for (const auto& p : types) {
-            unique_types.insert("std::reference_wrapper<" + p.second + ">");
+            unique_types.insert("std::reference_wrapper<" + p.second.to_string() + ">");
         }
         std::ostringstream oss;
         for (auto it = unique_types.begin(); it != unique_types.end(); ++it) {
@@ -164,18 +199,18 @@ struct CxxStruct {
 
 struct CxxFunction {
 	IdString name;
-	int width;
+	CxxType type;
 	dict<IdString, Const> parameters;
 
-	CxxFunction(IdString name, int width) : name(name), width(width) {}
-	CxxFunction(IdString name, int width, dict<IdString, Const> parameters) : name(name), width(width), parameters(parameters) {}
+	CxxFunction(IdString name, CxxType type) : name(name), type(type) {}
+	CxxFunction(IdString name, CxxType type, dict<IdString, Const> parameters) : name(name), type(type), parameters(parameters) {}
 
 	bool operator==(CxxFunction const &other) const {
-		return name == other.name && parameters == other.parameters && width == other.width;
+		return name == other.name && parameters == other.parameters && type == other.type;
 	}
 
 	unsigned int hash() const {
-		return mkhash(name.hash(), parameters.hash());
+		return mkhash(name.hash(), mkhash(type.hash(), parameters.hash()));
 	}
 };
 
@@ -232,6 +267,9 @@ class CxxComputeGraphFactory {
 	}
 	T input(IdString name, int width) { return graph.add(CxxFunction(ID($$input), width, {{name, {}}}), 0); }
 	T state(IdString name, int width) { return graph.add(CxxFunction(ID($$state), width, {{name, {}}}), 0); }
+	T state_memory(IdString name, int addr_width, int data_width) {
+		return graph.add(CxxFunction(ID($$state), CxxType::memory(addr_width, data_width), {{name, {}}}), 0);
+	}
 	T cell_output(T cell, IdString type, IdString name, int width) {
 		if (is_single_output(type))
 			return cell;
@@ -245,12 +283,19 @@ class CxxComputeGraphFactory {
 		return graph.add(CxxFunction(ID($$undriven), width), 0);
 	}
 
+	T memory_read(T mem, T addr, int addr_width, int data_width) {
+		return graph.add(CxxFunction(ID($memory_read), data_width), 0, std::array<T, 2>{mem, addr});
+	}
+	T memory_write(T mem, T addr, T data, int addr_width, int data_width) {
+		return graph.add(CxxFunction(ID($memory_write), CxxType::memory(addr_width, data_width)), 0, std::array<T, 3>{mem, addr, data});
+	}
+
 	T create_pending(int width) {
 		return graph.add(CxxFunction(ID($$pending), width), 0);
 	}
 	void update_pending(T pending, T node) {
 		log_assert(pending.function().name == ID($$pending));
-		pending.set_function(CxxFunction(ID($$buf), pending.function().width));
+		pending.set_function(CxxFunction(ID($$buf), pending.function().type));
 		pending.append_arg(node);
 	}
 	void declare_output(T node, IdString name, int) {
@@ -259,6 +304,9 @@ class CxxComputeGraphFactory {
 	void declare_state(T node, IdString name, int) {
 		node.assign_key(name);
 	}
+	void declare_state_memory(T node, IdString name, int, int) {
+		node.assign_key(name);
+	}
 	void suggest_name(T node, IdString name) {
 		node.sparse_attr() = name;
 	}
@@ -312,8 +360,10 @@ struct FunctionalCxxBackend : public Backend
 			{
 				int target_index = alias[node.arg(0).index()];
 				auto target_node = compute_graph[perm[target_index]];
-				if(!target_node.has_sparse_attr() && node.has_sparse_attr())
-					target_node.sparse_attr() = node.sparse_attr();
+				if(!target_node.has_sparse_attr() && node.has_sparse_attr()){
+					IdString id = node.sparse_attr();
+					target_node.sparse_attr() = id;
+				}
 				alias.push_back(target_index);
 			}
 			else
@@ -328,7 +378,7 @@ struct FunctionalCxxBackend : public Backend
 
 	void printCxx(std::ostream &stream, std::string, std::string const & name, CxxComputeGraph &compute_graph)
 	{
-		dict<IdString, int> inputs, state;
+		dict<IdString, CxxType> inputs, state;
 		CxxWriter f(stream);
 
 		// Dump the compute graph
@@ -336,22 +386,22 @@ struct FunctionalCxxBackend : public Backend
 		{
 			auto ref = compute_graph[i];
 			if(ref.function().name == ID($$input))
-				inputs[ref.function().parameters.begin()->first] = ref.function().width;
+				inputs[ref.function().parameters.begin()->first] = ref.function().type;
 			if(ref.function().name == ID($$state))
-				state[ref.function().parameters.begin()->first] = ref.function().width;
+				state[ref.function().parameters.begin()->first] = ref.function().type;
 		}
 		f.printf("#include \"sim.h\"\n");
 		f.printf("#include <variant>\n");
 		CxxStruct input_struct(name + "_Inputs", true, inputs.size());
 		for (auto const &input : inputs)
-			input_struct.insert(input.first, "Signal<" + std::to_string(input.second) + ">");
+			input_struct.insert(input.first, input.second);
 		CxxStruct output_struct(name + "_Outputs");
 		for (auto const &key : compute_graph.keys())
 			if(state.count(key.first) == 0)
-				output_struct.insert(key.first, "Signal<" + std::to_string(compute_graph[key.second].function().width) + ">");
+				output_struct.insert(key.first, compute_graph[key.second].function().type);
 		CxxStruct state_struct(name + "_State");
 		for (auto const &state_var : state)
-			state_struct.insert(state_var.first, "Signal<" + std::to_string(state_var.second) + ">");
+			state_struct.insert(state_var.first, state_var.second);
 
 		idict<std::string> node_names;
 		CxxScope locals;
@@ -368,7 +418,7 @@ struct FunctionalCxxBackend : public Backend
 		for (int i = 0; i < compute_graph.size(); ++i)
 		{
 			auto ref = compute_graph[i];
-			int width = ref.function().width;
+			auto type = ref.function().type;
 			std::string name;
 			if(ref.has_sparse_attr())
 				name = locals.insert(ref.sparse_attr());
@@ -376,19 +426,19 @@ struct FunctionalCxxBackend : public Backend
 				name = locals.insert("\\n" + std::to_string(i));
 			node_names(name);
 			if(ref.function().name == ID($$input))
-				f.printf("\tSignal<%d> %s = input.%s;\n", width, name.c_str(), input_struct[ref.function().parameters.begin()->first].c_str());
+				f.printf("\t%s %s = input.%s;\n", type.to_string().c_str(), name.c_str(), input_struct[ref.function().parameters.begin()->first].c_str());
 			else if(ref.function().name == ID($$state))
-				f.printf("\tSignal<%d> %s = current_state.%s;\n", width, name.c_str(), state_struct[ref.function().parameters.begin()->first].c_str());
+				f.printf("\t%s %s = current_state.%s;\n", type.to_string().c_str(), name.c_str(), state_struct[ref.function().parameters.begin()->first].c_str());
 			else if(ref.function().name == ID($$buf))
-				f.printf("\tSignal<%d> %s = %s;\n", width, name.c_str(), node_names[ref.arg(0).index()].c_str());
+				f.printf("\t%s %s = %s;\n", type.to_string().c_str(), name.c_str(), node_names[ref.arg(0).index()].c_str());
 			else if(ref.function().name == ID($$cell_output))
-				f.printf("\tSignal<%d> %s = %s.%s;\n", width, name.c_str(), node_names[ref.arg(0).index()].c_str(), RTLIL::unescape_id(ref.function().parameters.begin()->first).c_str());
+				f.printf("\t%s %s = %s.%s;\n", type.to_string().c_str(), name.c_str(), node_names[ref.arg(0).index()].c_str(), RTLIL::unescape_id(ref.function().parameters.begin()->first).c_str());
 			else if(ref.function().name == ID($$const)){
 				auto c = ref.function().parameters.begin()->second;
 				if(c.size() <= 32){
-					f.printf("\tSignal<%d> %s = $const<%d>(%#x);\n", width, name.c_str(), width, (uint32_t) c.as_int());
+					f.printf("\t%s %s = $const<%d>(%#x);\n", type.to_string().c_str(), name.c_str(), type.width(), (uint32_t) c.as_int());
 				}else{
-					f.printf("\tSignal<%d> %s = $const<%d>({%#x", width, name.c_str(), width, (uint32_t) c.as_int());
+					f.printf("\t%s %s = $const<%d>({%#x", type.to_string().c_str(), name.c_str(), type.width(), (uint32_t) c.as_int());
 					while(c.size() > 32){
 						c = c.extract(32, c.size() - 32);
 						f.printf(", %#x", c.as_int());
@@ -396,9 +446,9 @@ struct FunctionalCxxBackend : public Backend
 					f.printf("});\n");
 				}
 			}else if(ref.function().name == ID($$undriven))
-				f.printf("\tSignal<%d> %s; //undriven\n", width, name.c_str());
+				f.printf("\t%s %s; //undriven\n", type.to_string().c_str(), name.c_str());
 			else if(ref.function().name == ID($$slice))
-				f.printf("\tSignal<%d> %s = slice<%d>(%s, %d);\n", width, name.c_str(), width, node_names[ref.arg(0).index()].c_str(), ref.function().parameters.at(ID(offset)).as_int());
+				f.printf("\t%s %s = slice<%d>(%s, %d);\n", type.to_string().c_str(), name.c_str(), type.width(), node_names[ref.arg(0).index()].c_str(), ref.function().parameters.at(ID(offset)).as_int());
 			else if(ref.function().name == ID($$concat)){
 				f.printf("\tauto %s = concat(", name.c_str());
 				for (int i = 0, end = ref.size(); i != end; ++i){
@@ -409,11 +459,7 @@ struct FunctionalCxxBackend : public Backend
 				f.printf(");\n");
 			}else{
 				f.printf("\t");
-				if(ref.function().width > 0)
-					f.printf("Signal<%d>", ref.function().width);
-				else
-					f.printf("%s_Outputs", log_id(ref.function().name));
-				f.printf(" %s = %s", name.c_str(), log_id(ref.function().name));
+				f.printf("%s %s = %s", type.to_string().c_str(), name.c_str(), log_id(ref.function().name));
 				if(ref.function().parameters.count(ID(WIDTH))){
 					f.printf("<%d>", ref.function().parameters.at(ID(WIDTH)).as_int());
 				}
diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h
index 75d045ccf35..310927f5b7b 100644
--- a/backends/functional/cxx_runtime/sim.h
+++ b/backends/functional/cxx_runtime/sim.h
@@ -363,4 +363,23 @@ Signal<n> $sign_extend(Signal<m> const& a)
     return ret;
 }
 
+template<size_t a, size_t d>
+struct Memory {
+    std::array<Signal<d>, 1<<a> contents;
+};
+
+template<size_t a, size_t d>
+Signal<d> $memory_read(Memory<a, d> memory, Signal<a> addr)
+{
+    return memory.contents[as_int(addr)];
+}
+
+template<size_t a, size_t d>
+Memory<a, d> $memory_write(Memory<a, d> memory, Signal<a> addr, Signal<d> data)
+{
+    Memory<a, d> ret = memory;
+    ret.contents[as_int(addr)] = data;
+    return ret;
+}
+
 #endif
diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index 7a283cccf26..a90927ab6f5 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -219,19 +219,54 @@ std::ostream& operator << (std::ostream &os, SExpr const &s) {
     return os;
 }
 
+struct SmtlibType {
+	bool _is_memory;
+	int _width;
+	int _addr_width;
+public:
+	SmtlibType() : _is_memory(false), _width(0), _addr_width(0) { }
+	SmtlibType(int width) : _is_memory(false), _width(width), _addr_width(0) { }
+	SmtlibType(int addr_width, int data_width) : _is_memory(true), _width(data_width), _addr_width(addr_width) { }
+	static SmtlibType signal(int width) { return SmtlibType(width); }
+	static SmtlibType memory(int addr_width, int data_width) { return SmtlibType(addr_width, data_width); }
+	bool is_signal() const { return !_is_memory; }
+	bool is_memory() const { return _is_memory; }
+	int width() const { log_assert(is_signal()); return _width; }
+	int addr_width() const { log_assert(is_memory()); return _addr_width; }
+	int data_width() const { log_assert(is_memory()); return _width; }
+	SExpr to_sexpr() const {
+		if(_is_memory) {
+			return SExpr{ "Array", SExpr{ "_", "BitVec", addr_width() }, SExpr{ "_", "BitVec", data_width() }};
+		} else {
+			return SExpr{ "_", "BitVec", width() };
+		}
+	}
+	bool operator ==(SmtlibType const& other) const {
+		if(_is_memory != other._is_memory) return false;
+		if(_is_memory && _addr_width != other._addr_width) return false;
+		return _width == other._width;
+	}
+	unsigned int hash() const {
+		if(_is_memory)
+			return mkhash(1, mkhash(_width, _addr_width));
+		else
+			return mkhash(0, _width);
+	}
+};
+
 struct SmtlibStruct {
 	SmtlibScope &scope;
 	std::string name;
 	idict<IdString> members;
-	vector<int> widths;
+	vector<SmtlibType> types;
 	vector<std::string> accessors;
 	SmtlibStruct(std::string name, SmtlibScope &scope) : scope(scope), name(name) {
 	}
-	std::string insert(IdString field, int width) {
+	std::string insert(IdString field, SmtlibType type) {
 		if(members.at(field, -1) == -1){
 			members(field);
 			scope.insert(field);
-			widths.push_back(width);
+			types.push_back(type);
 			accessors.push_back(scope.insert(std::string("\\") + name + "_" + RTLIL::unescape_id(field)));
 		}
 		return scope[field];
@@ -239,7 +274,7 @@ struct SmtlibStruct {
 	void print(SmtlibWriter &f) {
 		f.printf("(declare-datatype %s ((%s\n", name.c_str(), name.c_str());
 		for (size_t i = 0; i < members.size(); i++)
-			f.printf("  (%s (_ BitVec %d))\n", accessors[i].c_str(), widths[i]);
+			f << "  " << SExpr{accessors[i], types[i].to_sexpr()} << "\n";
 		f.printf(")))\n");
 	}
 	void print_value(SmtlibWriter &f, dict<IdString, SExpr> values, int indentation) {
@@ -260,16 +295,16 @@ struct SmtlibStruct {
 
 struct Node {
 	SExpr expr;
-	int width;
+	SmtlibType type;
 
-	Node(SExpr &&expr, int width) : expr(std::move(expr)), width(width) {}
+	Node(SExpr &&expr, SmtlibType type) : expr(std::move(expr)), type(type) {}
 
 	bool operator==(Node const &other) const {
-		return expr == other.expr && width == other.width;
+		return expr == other.expr && type == other.type;
 	}
 
 	unsigned int hash() const {
-		return mkhash(expr.hash(), width);
+		return mkhash(expr.hash(), type.hash());
 	}
 };
 
@@ -302,8 +337,8 @@ class SmtlibComputeGraphFactory {
 		auto it = yosys_celltypes.cell_types.find(type);
 		return it != yosys_celltypes.cell_types.end() && it->second.outputs.size() <= 1;
 	}
-	T node(SExpr &&expr, int width, std::initializer_list<T> args) {
-		return graph.add(Node(std::move(expr), width), 0, args);
+	T node(SExpr &&expr, SmtlibType type, std::initializer_list<T> args) {
+		return graph.add(Node(std::move(expr), type), 0, args);
 	}
 	T shift(const char *name, T a, T b, int y_width, int b_width, bool a_signed = false) {
 		int width = max(y_width, b_width);
@@ -367,6 +402,13 @@ class SmtlibComputeGraphFactory {
 	T logical_shift_right(T a, T b, int y_width, int b_width) { return shift("bvlshl", a, b, y_width, b_width); }
 	T arithmetic_shift_right(T a, T b, int y_width, int b_width) { return shift("bvashr", a, b, y_width, b_width, true); }
 
+	T memory_read(T mem, T addr, int addr_width, int data_width) {
+		return node(SExpr {"select", Arg(1), Arg(2)}, data_width, {mem, addr});
+	}
+	T memory_write(T mem, T addr, T data, int addr_width, int data_width) {
+		return node(SExpr {"store", Arg(1), Arg(2), Arg(3)}, SmtlibType::memory(addr_width, data_width), {mem, addr, data});
+	}
+
 	T constant(RTLIL::Const value) { return node(SExpr(value), value.size(), {}); }
 	T input(IdString name, int width) {
 		module.input_struct.insert(name, width);
@@ -376,6 +418,10 @@ class SmtlibComputeGraphFactory {
 		module.state_struct.insert(name, width);
 		return node(module.state_struct.access("current_state", name), width, {});
 	}
+	T state_memory(IdString name, int addr_width, int data_width) {
+		module.state_struct.insert(name, SmtlibType::memory(addr_width, data_width));
+		return node(module.state_struct.access("current_state", name), SmtlibType::memory(addr_width, data_width), {});
+	}
 	T cell_output(T cell, IdString type, IdString name, int width) {
 		if (is_single_output(type))
 			return cell;
@@ -399,7 +445,7 @@ class SmtlibComputeGraphFactory {
 	}
 	void update_pending(T pending, T node) {
 		log_assert(pending.function().expr.is_none());
-		pending.set_function(Node(Arg(1), pending.function().width));
+		pending.set_function(Node(Arg(1), pending.function().type));
 		pending.append_arg(node);
 	}
 	void declare_output(T node, IdString name, int width) {
@@ -410,6 +456,10 @@ class SmtlibComputeGraphFactory {
 		module.state_struct.insert(name, width);
 		node.assign_key(name);
 	}
+	void declare_state_memory(T node, IdString name, int addr_width, int data_width) {
+		module.state_struct.insert(name, SmtlibType::memory(addr_width, data_width));
+		node.assign_key(name);
+	}
 	void suggest_name(T node, IdString name) {
 		node.sparse_attr() = name;
 	}
diff --git a/kernel/drivertools.h b/kernel/drivertools.h
index 1cb835df2cc..48c846b5f79 100644
--- a/kernel/drivertools.h
+++ b/kernel/drivertools.h
@@ -1064,6 +1064,13 @@ struct DriveSpec
 			append(bit);
 	}
 
+	DriveSpec(SigSpec const &sig)
+	{
+		// TODO: converting one chunk at a time would be faster
+		for (auto const &bit : sig.bits())
+			append(bit);
+	}
+
 	std::vector<DriveChunk> const &chunks() const { pack(); return chunks_; }
 	std::vector<DriveBit> const &bits() const { unpack(); return bits_; }
 
diff --git a/kernel/graphtools.h b/kernel/graphtools.h
index adf4764c201..98046c6be0b 100644
--- a/kernel/graphtools.h
+++ b/kernel/graphtools.h
@@ -23,6 +23,7 @@
 #include "kernel/yosys.h"
 #include "kernel/drivertools.h"
 #include "kernel/functional.h"
+#include "kernel/mem.h"
 
 USING_YOSYS_NAMESPACE
 YOSYS_NAMESPACE_BEGIN
@@ -71,6 +72,11 @@ class CellSimplifier {
 		T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width);
 		return factory.arithmetic_shift_right(a, reduced_b, y_width, reduced_b_width);
 	}
+	T bitwise_mux(T a, T b, T s, int width) {
+		T aa = factory.bitwise_and(a, factory.bitwise_not(s, width), width);
+		T bb = factory.bitwise_and(b, s, width);
+		return factory.bitwise_or(aa, bb, width);
+	}
 	CellSimplifier(Factory &f) : factory(f) {}
 	T handle(IdString cellType, dict<IdString, Const> parameters, dict<IdString, T> inputs)
 	{
@@ -104,7 +110,7 @@ class CellSimplifier {
 			T b = extend(inputs.at(ID(B)), b_width, width, is_signed);
 			if(cellType.in({ID($eq), ID($eqx)}))
 				return extend(factory.eq(a, b, width), 1, y_width, false);
-			if(cellType.in({ID($ne), ID($nex)}))
+			else if(cellType.in({ID($ne), ID($nex)}))
 				return extend(factory.ne(a, b, width), 1, y_width, false);
 			else if(cellType == ID($lt))
 				return extend(is_signed ? factory.gt(b, a, width) : factory.ugt(b, a, width), 1, y_width, false);
@@ -197,6 +203,8 @@ class ComputeGraphConstruction {
 	DriverMap driver_map;
 	Factory& factory;
 	CellSimplifier<T, Factory> simplifier;
+	vector<Mem> memories_vector;
+	dict<Cell*, Mem*> memories;
 
 	T enqueue(DriveSpec const &spec)
 	{
@@ -224,6 +232,45 @@ class ComputeGraphConstruction {
 				factory.declare_output(node, wire->name, wire->width);
 			}
 		}
+		memories_vector = Mem::get_all_memories(module);
+		for (auto &mem : memories_vector) {
+			if (mem.cell != nullptr)
+				memories[mem.cell] = &mem;
+		}
+	}
+	T concatenate_read_results(Mem *mem, vector<T> results)
+	{
+		if(results.size() == 0)
+			return factory.undriven(0);
+		T node = results[0];
+		int size = results[0].size();
+		for(size_t i = 1; i < results.size(); i++) {
+			node = factory.concat(node, size, results[i], results[i].size());
+			size += results[i].size();
+		}
+		return node;
+	}
+	T handle_memory(Mem *mem)
+	{
+		vector<T> read_results;
+		int addr_width = ceil_log2(mem->size);
+		int data_width = mem->width;
+		T node = factory.state_memory(mem->cell->name, addr_width, data_width);
+		for (auto &rd : mem->rd_ports) {
+			log_assert(!rd.clk_enable);
+			T addr = enqueue(driver_map(DriveSpec(rd.addr)));
+			read_results.push_back(factory.memory_read(node, addr, addr_width, data_width));
+		}
+		for (auto &wr : mem->wr_ports) {
+			T en = enqueue(driver_map(DriveSpec(wr.en)));
+			T addr = enqueue(driver_map(DriveSpec(wr.addr)));
+			T new_data = enqueue(driver_map(DriveSpec(wr.data)));
+			T old_data = factory.memory_read(node, addr, addr_width, data_width);
+			T wr_data = simplifier.bitwise_mux(old_data, new_data, en, data_width);
+			node = factory.memory_write(node, addr, wr_data, addr_width, data_width);
+		}
+		factory.declare_state_memory(node, mem->cell->name, addr_width, data_width);
+		return concatenate_read_results(mem, read_results);
 	}
 	void process_queue()
 	{
@@ -306,13 +353,20 @@ class ComputeGraphConstruction {
 					factory.update_pending(pending, node);
 				} else if (chunk.is_marker()) {
 					Cell *cell = cells[chunk.marker().marker];
-					dict<IdString, T> connections;
-					for(auto const &conn : cell->connections()) {
-						if(driver_map.celltypes.cell_input(cell->type, conn.first))
-							connections.insert({ conn.first, enqueue(DriveChunkPort(cell, conn)) });
+					if (cell->is_mem_cell()) {
+						Mem *mem = memories.at(cell, nullptr);
+						log_assert(mem != nullptr);
+						T node = handle_memory(mem);
+						factory.update_pending(pending, node);
+					} else {
+						dict<IdString, T> connections;
+						for(auto const &conn : cell->connections()) {
+							if(driver_map.celltypes.cell_input(cell->type, conn.first))
+								connections.insert({ conn.first, enqueue(DriveChunkPort(cell, conn)) });
+						}
+						T node = simplifier.handle(cell->type, cell->parameters, connections);
+						factory.update_pending(pending, node);
 					}
-					T node = simplifier.handle(cell->type, cell->parameters, connections);
-					factory.update_pending(pending, node);
 				} else if (chunk.is_none()) {
 					T node = factory.undriven(chunk.size());
 					factory.update_pending(pending, node);

From 3552a8a2b2cfe9ab487bb44377e48d9f4fc4fd84 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Wed, 12 Jun 2024 09:41:42 +0200
Subject: [PATCH 372/499] sim.h cannot use log_assert because does not include
 yosys headers

---
 backends/functional/cxx_runtime/sim.h | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h
index 310927f5b7b..3a398a13a5a 100644
--- a/backends/functional/cxx_runtime/sim.h
+++ b/backends/functional/cxx_runtime/sim.h
@@ -21,6 +21,7 @@
 #define SIM_H
 
 #include <array>
+#include <cassert>
 
 template<size_t n>
 using Signal = std::array<bool, n>;
@@ -249,7 +250,7 @@ Signal<n> $shl(Signal<na> const& a, Signal<nb> const &b)
 {
     if(nb >= sizeof(int) * 8 - 1)
         for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
-            log_assert(!b[i]);
+            assert(!b[i]);
     size_t amount = as_int(b);
     Signal<n> ret = $const<n>(0);
     if(amount < n){
@@ -266,7 +267,7 @@ Signal<n> $shr(Signal<n> const& a, Signal<nb> const &b)
 {
     if(nb >= sizeof(int) * 8 - 1)
         for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
-            log_assert(!b[i]);
+            assert(!b[i]);
     size_t amount = as_int(b);
     Signal<n> ret;
     for (size_t i = 0; i < n; i++) {
@@ -283,7 +284,7 @@ Signal<n> $asr(Signal<n> const& a, Signal<nb> const &b)
 {
     if(nb >= sizeof(int) * 8 - 1)
         for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
-            log_assert(!b[i]);
+            assert(!b[i]);
     size_t amount = as_int(b);
     Signal<n> ret;
     for (size_t i = 0; i < n; i++) {
@@ -344,7 +345,7 @@ Signal<n+m> concat(Signal<n> const& a, Signal<m> const& b)
 template<size_t n, size_t m>
 Signal<n> $zero_extend(Signal<m> const& a)
 {
-    log_assert(n >= m);
+    assert(n >= m);
     Signal<n> ret;
     std::copy(a.begin(), a.end(), ret.begin());
     for(size_t i = m; i < n; i++)
@@ -355,7 +356,7 @@ Signal<n> $zero_extend(Signal<m> const& a)
 template<size_t n, size_t m>
 Signal<n> $sign_extend(Signal<m> const& a)
 {
-    log_assert(n >= m);
+    assert(n >= m);
     Signal<n> ret;
     std::copy(a.begin(), a.end(), ret.begin());
     for(size_t i = m; i < n; i++)

From dbf2bc3b1dfe0a316e33ada2abb99fa65c8e0616 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Wed, 12 Jun 2024 12:27:43 +0100
Subject: [PATCH 373/499] need unsigned comparison when checking shift widths
 for overflow in functional backend

---
 kernel/graphtools.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/graphtools.h b/kernel/graphtools.h
index 98046c6be0b..4fb7aacf444 100644
--- a/kernel/graphtools.h
+++ b/kernel/graphtools.h
@@ -40,7 +40,7 @@ class CellSimplifier {
 		} else {
 			reduced_b_width = new_width;
 			T lower_b = factory.slice(b, b_width, 0, new_width);
-			T overflow = factory.gt(b, factory.constant(RTLIL::Const(y_width, b_width)), b_width);
+			T overflow = factory.ugt(b, factory.constant(RTLIL::Const(y_width, b_width)), b_width);
 			return factory.mux(lower_b, factory.constant(RTLIL::Const(y_width, new_width)), overflow, new_width);
 		}
 	}

From 248d5f72d41c7194b54f493a692f9f312e198979 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 20 Jun 2024 16:25:21 +0100
Subject: [PATCH 374/499] add support for std::variant to hashlib

---
 kernel/hashlib.h      | 19 +++++++++++++++++++
 kernel/yosys_common.h |  1 +
 2 files changed, 20 insertions(+)

diff --git a/kernel/hashlib.h b/kernel/hashlib.h
index 6b880f3a666..d32db6832fa 100644
--- a/kernel/hashlib.h
+++ b/kernel/hashlib.h
@@ -186,6 +186,25 @@ inline unsigned int mkhash(const T &v) {
 	return hash_ops<T>().hash(v);
 }
 
+template<> struct hash_ops<std::monostate> {
+	static inline bool cmp(std::monostate a, std::monostate b) {
+		return a == b;
+	}
+	static inline unsigned int hash(std::monostate) {
+		return mkhash_init;
+	}
+};
+
+template<typename... T> struct hash_ops<std::variant<T...>> {
+	static inline bool cmp(std::variant<T...> a, std::variant<T...> b) {
+		return a == b;
+	}
+	static inline unsigned int hash(std::variant<T...> a) {
+		unsigned int h = std::visit([](const auto &v) { return mkhash(v); }, a);
+		return mkhash(a.index(), h);
+	}
+};
+
 inline int hashtable_size(int min_size)
 {
 	// Primes as generated by https://oeis.org/A175953
diff --git a/kernel/yosys_common.h b/kernel/yosys_common.h
index 56d2356b102..e71e94a78c5 100644
--- a/kernel/yosys_common.h
+++ b/kernel/yosys_common.h
@@ -30,6 +30,7 @@
 #include <unordered_map>
 #include <unordered_set>
 #include <initializer_list>
+#include <variant>
 #include <stdexcept>
 #include <memory>
 #include <cmath>

From 6f9e21219b8536cd957c49b49f442d4372038590 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 20 Jun 2024 16:40:02 +0100
Subject: [PATCH 375/499] add new generic compute graph and rewrite c++
 functional backend to use it

---
 Makefile                                 |   2 +-
 backends/functional/Makefile.inc         |   3 +-
 backends/functional/cxx.cc               | 392 +++++++----------------
 backends/functional/test_generic.cc      |  56 ++++
 kernel/functional.h                      |  22 +-
 kernel/{graphtools.h => functionalir.cc} |  74 ++++-
 kernel/functionalir.h                    | 381 ++++++++++++++++++++++
 7 files changed, 628 insertions(+), 302 deletions(-)
 create mode 100644 backends/functional/test_generic.cc
 rename kernel/{graphtools.h => functionalir.cc} (88%)
 create mode 100644 kernel/functionalir.h

diff --git a/Makefile b/Makefile
index 812a69271a7..1feeeab95d6 100644
--- a/Makefile
+++ b/Makefile
@@ -639,7 +639,7 @@ $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h))
 OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o
 OBJS += kernel/binding.o
 OBJS += kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o
-OBJS += kernel/drivertools.o
+OBJS += kernel/drivertools.o kernel/functionalir.o
 ifeq ($(ENABLE_ZLIB),1)
 OBJS += kernel/fstdata.o
 endif
diff --git a/backends/functional/Makefile.inc b/backends/functional/Makefile.inc
index c712d2aefe5..f4b968ef371 100644
--- a/backends/functional/Makefile.inc
+++ b/backends/functional/Makefile.inc
@@ -1,2 +1,3 @@
 OBJS += backends/functional/cxx.o
-OBJS += backends/functional/smtlib.o
+#OBJS += backends/functional/smtlib.o
+OBJS += backends/functional/test_generic.o
diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index 08d9ba7914b..789ab7949ba 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -18,10 +18,7 @@
  */
 
 #include "kernel/yosys.h"
-#include "kernel/drivertools.h"
-#include "kernel/topo_scc.h"
-#include "kernel/functional.h"
-#include "kernel/graphtools.h"
+#include "kernel/functionalir.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
@@ -84,38 +81,17 @@ struct CxxScope {
 };
 
 struct CxxType {
-	bool _is_memory;
-	int _width;
-	int _addr_width;
-public:
-	CxxType() : _is_memory(false), _width(0), _addr_width(0) { }
-	CxxType(int width) : _is_memory(false), _width(width), _addr_width(0) { }
-	CxxType(int addr_width, int data_width) : _is_memory(true), _width(data_width), _addr_width(addr_width) { }
-	static CxxType signal(int width) { return CxxType(width); }
-	static CxxType memory(int addr_width, int data_width) { return CxxType(addr_width, data_width); }
-	bool is_signal() const { return !_is_memory; }
-	bool is_memory() const { return _is_memory; }
-	int width() const { log_assert(is_signal()); return _width; }
-	int addr_width() const { log_assert(is_memory()); return _addr_width; }
-	int data_width() const { log_assert(is_memory()); return _width; }
+	FunctionalIR::Sort sort;
+	CxxType(FunctionalIR::Sort sort) : sort(sort) {}
 	std::string to_string() const {
-		if(_is_memory) {
-			return stringf("Memory<%d, %d>", addr_width(), data_width());
+		if(sort.is_memory()) {
+			return stringf("Memory<%d, %d>", sort.addr_width(), sort.data_width());
+		} else if(sort.is_signal()) {
+			return stringf("Signal<%d>", sort.width());
 		} else {
-			return stringf("Signal<%d>", width());
+			log_error("unknown sort");
 		}
 	}
-	bool operator ==(CxxType const& other) const {
-		if(_is_memory != other._is_memory) return false;
-		if(_is_memory && _addr_width != other._addr_width) return false;
-		return _width == other._width;
-	}
-	unsigned int hash() const {
-		if(_is_memory)
-			return mkhash(1, mkhash(_width, _addr_width));
-		else
-			return mkhash(0, _width);
-	}
 };
 
 struct CxxWriter {
@@ -135,9 +111,8 @@ struct CxxStruct {
   dict<IdString, CxxType> types;
   CxxScope scope;
   bool generate_methods;
-  int count;
-  CxxStruct(std::string name, bool generate_methods = false, int count = 0) 
-    : name(name), generate_methods(generate_methods), count(count) {
+  CxxStruct(std::string name, bool generate_methods = false)
+    : name(name), generate_methods(generate_methods) {
     scope.reserve("out");
     scope.reserve("dump");
   }
@@ -159,7 +134,7 @@ struct CxxStruct {
     if (generate_methods) {
       // Add size method
       f.printf("\tint size() const {\n");
-      f.printf("\t\treturn %d;\n", count);
+      f.printf("\t\treturn %d;\n", types.size());
       f.printf("\t}\n\n");
 
       // Add get_input method
@@ -197,119 +172,87 @@ struct CxxStruct {
   }
 };
 
-struct CxxFunction {
-	IdString name;
-	CxxType type;
-	dict<IdString, Const> parameters;
-
-	CxxFunction(IdString name, CxxType type) : name(name), type(type) {}
-	CxxFunction(IdString name, CxxType type, dict<IdString, Const> parameters) : name(name), type(type), parameters(parameters) {}
-
-	bool operator==(CxxFunction const &other) const {
-		return name == other.name && parameters == other.parameters && type == other.type;
-	}
-
-	unsigned int hash() const {
-		return mkhash(name.hash(), mkhash(type.hash(), parameters.hash()));
-	}
-};
-
-typedef ComputeGraph<CxxFunction, int, IdString, IdString> CxxComputeGraph;
-
-class CxxComputeGraphFactory {
-	CxxComputeGraph &graph;
-	using T = CxxComputeGraph::Ref;
-	static bool is_single_output(IdString type)
-	{
-		auto it = yosys_celltypes.cell_types.find(type);
-		return it != yosys_celltypes.cell_types.end() && it->second.outputs.size() <= 1;
-	}
+struct CxxTemplate {
+	vector<std::variant<std::string, int>> _v;
 public:
-	CxxComputeGraphFactory(CxxComputeGraph &g) : graph(g) {}
-	T slice(T a, int in_width, int offset, int out_width) {
-		log_assert(offset + out_width <= in_width);
-		return graph.add(CxxFunction(ID($$slice), out_width, {{ID(offset), offset}}), 0, std::array<T, 1>{a});
-	}
-	T extend(T a, int in_width, int out_width, bool is_signed) {
-		log_assert(in_width < out_width);
-		if(is_signed)
-			return graph.add(CxxFunction(ID($sign_extend), out_width, {{ID(WIDTH), out_width}}), 0, std::array<T, 1>{a});
-		else
-			return graph.add(CxxFunction(ID($zero_extend), out_width, {{ID(WIDTH), out_width}}), 0, std::array<T, 1>{a});
-	}
-	T concat(T a, int a_width, T b, int b_width) {
-		return graph.add(CxxFunction(ID($$concat), a_width + b_width), 0, std::array<T, 2>{a, b});
-	}
-	T add(T a, T b, int width) { return graph.add(CxxFunction(ID($add), width), 0, std::array<T, 2>{a, b}); }
-	T sub(T a, T b, int width) { return graph.add(CxxFunction(ID($sub), width), 0, std::array<T, 2>{a, b}); }
-	T bitwise_and(T a, T b, int width) { return graph.add(CxxFunction(ID($and), width), 0, std::array<T, 2>{a, b}); }
-	T bitwise_or(T a, T b, int width) { return graph.add(CxxFunction(ID($or), width), 0, std::array<T, 2>{a, b}); }
-	T bitwise_xor(T a, T b, int width) { return graph.add(CxxFunction(ID($xor), width), 0, std::array<T, 2>{a, b}); }
-	T bitwise_not(T a, int width) { return graph.add(CxxFunction(ID($not), width), 0, std::array<T, 1>{a}); }
-	T neg(T a, int width) { return graph.add(CxxFunction(ID($neg), width), 0, std::array<T, 1>{a}); }
-	T mux(T a, T b, T s, int width) { return graph.add(CxxFunction(ID($mux), width), 0, std::array<T, 3>{a, b, s}); }
-	T pmux(T a, T b, T s, int width, int) { return graph.add(CxxFunction(ID($pmux), width), 0, std::array<T, 3>{a, b, s}); }
-	T reduce_and(T a, int) { return graph.add(CxxFunction(ID($reduce_and), 1), 0, std::array<T, 1>{a}); }
-	T reduce_or(T a, int) { return graph.add(CxxFunction(ID($reduce_or), 1), 0, std::array<T, 1>{a}); }
-	T reduce_xor(T a, int) { return graph.add(CxxFunction(ID($reduce_xor), 1), 0, std::array<T, 1>{a}); }
-	T eq(T a, T b, int) { return graph.add(CxxFunction(ID($eq), 1), 0, std::array<T, 2>{a, b}); }
-	T ne(T a, T b, int) { return graph.add(CxxFunction(ID($ne), 1), 0, std::array<T, 2>{a, b}); }
-	T gt(T a, T b, int) { return graph.add(CxxFunction(ID($gt), 1), 0, std::array<T, 2>{a, b}); }
-	T ge(T a, T b, int) { return graph.add(CxxFunction(ID($ge), 1), 0, std::array<T, 2>{a, b}); }
-	T ugt(T a, T b, int) { return graph.add(CxxFunction(ID($ugt), 1), 0, std::array<T, 2>{a, b}); }
-	T uge(T a, T b, int) { return graph.add(CxxFunction(ID($uge), 1), 0, std::array<T, 2>{a, b}); }
-	T logical_shift_left(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shl), y_width, {{ID(WIDTH), y_width}}), 0, std::array<T, 2>{a, b}); }
-	T logical_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shr), y_width, {{ID(WIDTH), y_width}}), 0, std::array<T, 2>{a, b}); }
-	T arithmetic_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($asr), y_width, {{ID(WIDTH), y_width}}), 0, std::array<T, 2>{a, b}); }
-
-	T constant(RTLIL::Const value) {
-		return graph.add(CxxFunction(ID($$const), value.size(), {{ID(value), value}}), 0);
-	}
-	T input(IdString name, int width) { return graph.add(CxxFunction(ID($$input), width, {{name, {}}}), 0); }
-	T state(IdString name, int width) { return graph.add(CxxFunction(ID($$state), width, {{name, {}}}), 0); }
-	T state_memory(IdString name, int addr_width, int data_width) {
-		return graph.add(CxxFunction(ID($$state), CxxType::memory(addr_width, data_width), {{name, {}}}), 0);
-	}
-	T cell_output(T cell, IdString type, IdString name, int width) {
-		if (is_single_output(type))
-			return cell;
-		else
-			return graph.add(CxxFunction(ID($$cell_output), width, {{name, {}}}), 0, std::array<T, 1>{cell});
-	}
-	T multiple(vector<T> args, int width) {
-		return graph.add(CxxFunction(ID($$multiple), width), 0, args);
-	}
-	T undriven(int width) {
-		return graph.add(CxxFunction(ID($$undriven), width), 0);
-	}
-
-	T memory_read(T mem, T addr, int addr_width, int data_width) {
-		return graph.add(CxxFunction(ID($memory_read), data_width), 0, std::array<T, 2>{mem, addr});
+	CxxTemplate(std::string fmt) {
+		std::string buf;
+		for(auto it = fmt.begin(); it != fmt.end(); it++){
+			if(*it == '%'){
+				it++;
+				log_assert(it != fmt.end());
+				if(*it == '%')
+					buf += *it;
+				else {
+					log_assert(*it >= '0' && *it <= '9');
+					_v.emplace_back(std::move(buf));
+					_v.emplace_back((int)(*it - '0'));
+				}
+			}else
+				buf += *it;
+		}
+		if(!buf.empty())
+			_v.emplace_back(std::move(buf));
 	}
-	T memory_write(T mem, T addr, T data, int addr_width, int data_width) {
-		return graph.add(CxxFunction(ID($memory_write), CxxType::memory(addr_width, data_width)), 0, std::array<T, 3>{mem, addr, data});
+	template<typename... Args> static std::string format(CxxTemplate fmt, Args&&... args) {
+		vector<std::string> strs = {args...};
+		std::string result;
+		for(auto &v : fmt._v){
+			if(std::string *s = std::get_if<std::string>(&v))
+				result += *s;
+			else if(int *i = std::get_if<int>(&v))
+				result += strs[*i];
+			else
+				log_error("missing case");
+		}
+		return result;
 	}
+};
 
-	T create_pending(int width) {
-		return graph.add(CxxFunction(ID($$pending), width), 0);
-	}
-	void update_pending(T pending, T node) {
-		log_assert(pending.function().name == ID($$pending));
-		pending.set_function(CxxFunction(ID($$buf), pending.function().type));
-		pending.append_arg(node);
-	}
-	void declare_output(T node, IdString name, int) {
-		node.assign_key(name);
-	}
-	void declare_state(T node, IdString name, int) {
-		node.assign_key(name);
-	}
-	void declare_state_memory(T node, IdString name, int, int) {
-		node.assign_key(name);
-	}
-	void suggest_name(T node, IdString name) {
-		node.sparse_attr() = name;
+template<class NodeNames> struct CxxPrintVisitor {
+	using Node = FunctionalIR::Node;
+	NodeNames np;
+	CxxStruct &input_struct;
+	CxxStruct &state_struct;
+	CxxPrintVisitor(NodeNames np, CxxStruct &input_struct, CxxStruct &state_struct) : np(np), input_struct(input_struct), state_struct(state_struct) { }
+	template<class T> std::string arg_to_string(T n) { return std::to_string(n); }
+	template<> std::string arg_to_string(std::string n) { return n; }
+	template<> std::string arg_to_string(Node n) { return np(n); }
+	template<typename... Args> std::string format(std::string fmt, Args&&... args) {
+		return CxxTemplate::format(fmt, arg_to_string(args)...);
 	}
+	std::string buf(Node, Node n) { return np(n); }
+	std::string slice(Node, Node a, int, int offset, int out_width) { return format("slice<%2>(%0, %1)", a, offset, out_width); }
+	std::string zero_extend(Node, Node a, int, int out_width) { return format("$zero_extend<%1>(%0)", a, out_width); }
+	std::string sign_extend(Node, Node a, int, int out_width) { return format("$sign_extend<%1>(%0)", a, out_width); }
+	std::string concat(Node, Node a, int, Node b, int) { return format("concat(%0, %1)", a, b); }
+	std::string add(Node, Node a, Node b, int) { return format("$add(%0, %1)", a, b); }
+	std::string sub(Node, Node a, Node b, int) { return format("$sub(%0, %1)", a, b); }
+	std::string bitwise_and(Node, Node a, Node b, int) { return format("$and(%0, %1)", a, b); }
+	std::string bitwise_or(Node, Node a, Node b, int) { return format("$or(%0, %1)", a, b); }
+	std::string bitwise_xor(Node, Node a, Node b, int) { return format("$xor(%0, %1)", a, b); }
+	std::string bitwise_not(Node, Node a, int) { return format("$not(%0)", a); }
+	std::string unary_minus(Node, Node a, int) { return format("$neg(%0)", a); }
+	std::string reduce_and(Node, Node a, int) { return format("$reduce_and(%0)", a); }
+	std::string reduce_or(Node, Node a, int) { return format("$reduce_or(%0)", a); }
+	std::string reduce_xor(Node, Node a, int) { return format("$reduce_xor(%0)", a); }
+	std::string equal(Node, Node a, Node b, int) { return format("$eq(%0, %1)", a, b); }
+	std::string not_equal(Node, Node a, Node b, int) { return format("$ne(%0, %1)", a, b); }
+	std::string signed_greater_than(Node, Node a, Node b, int) { return format("$gt(%0, %1)", a, b); }
+	std::string signed_greater_equal(Node, Node a, Node b, int) { return format("$ge(%0, %1)", a, b); }
+	std::string unsigned_greater_than(Node, Node a, Node b, int) { return format("$ugt(%0, %1)", a, b); }
+	std::string unsigned_greater_equal(Node, Node a, Node b, int) { return format("$uge(%0, %1)", a, b); }
+	std::string logical_shift_left(Node, Node a, Node b, int, int) { return format("$shl<%2>(%0, %1)", a, b, a.width()); }
+	std::string logical_shift_right(Node, Node a, Node b, int, int) { return format("$shr<%2>(%0, %1)", a, b, a.width()); }
+	std::string arithmetic_shift_right(Node, Node a, Node b, int, int) { return format("$asr<%2>(%0, %1)", a, b, a.width()); }
+	std::string mux(Node, Node a, Node b, Node s, int) { return format("$mux(%0, %1, %2)", a, b, s); }
+	std::string pmux(Node, Node a, Node b, Node s, int, int) { return format("$pmux(%0, %1, %2)", a, b, s); }
+	std::string constant(Node, RTLIL::Const value) { return format("$const<%0>(%1)", value.size(), value.as_int()); }
+	std::string input(Node, IdString name) { return format("input.%0", input_struct[name]); }
+	std::string state(Node, IdString name) { return format("current_state.%0", state_struct[name]); }
+	std::string memory_read(Node, Node mem, Node addr, int, int) { return format("$memory_read(%0, %1)", mem, addr); }
+	std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { return format("$memory_write(%0, %1, %2)", mem, addr, data); }
+	std::string undriven(Node, int width) { return format("$const<%0>(0)", width); }
 };
 
 struct FunctionalCxxBackend : public Backend
@@ -322,88 +265,24 @@ struct FunctionalCxxBackend : public Backend
 		log("\n");
     }
 
-	CxxComputeGraph calculate_compute_graph(RTLIL::Module *module)
-	{
-		CxxComputeGraph compute_graph;
-		CxxComputeGraphFactory factory(compute_graph);
-		ComputeGraphConstruction<CxxComputeGraph::Ref, CxxComputeGraphFactory> construction(factory);
-		construction.add_module(module);
-		construction.process_queue();
-
-		// Perform topo sort and detect SCCs
-		CxxComputeGraph::SccAdaptor compute_graph_scc(compute_graph);
-
-		bool scc = false;
-		std::vector<int> perm;
-		topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) {
-			perm.insert(perm.end(), begin, end);
-			if (end > begin + 1)
-			{
-				log_warning("SCC:");
-				for (int *i = begin; i != end; ++i)
-					log(" %d(%s)(%s)", *i, compute_graph[*i].function().name.c_str(), compute_graph[*i].has_sparse_attr() ? compute_graph[*i].sparse_attr().c_str() : "");
-				log("\n");
-				scc = true;
-			}
-		}, /* sources_first */ true);
-		compute_graph.permute(perm);
-		if(scc) log_error("combinational loops, aborting\n");
-
-		// Forward $$buf
-		std::vector<int> alias;
-		perm.clear();
-
-		for (int i = 0; i < compute_graph.size(); ++i)
-		{
-			auto node = compute_graph[i];
-			if (node.function().name == ID($$buf) && node.arg(0).index() < i)
-			{
-				int target_index = alias[node.arg(0).index()];
-				auto target_node = compute_graph[perm[target_index]];
-				if(!target_node.has_sparse_attr() && node.has_sparse_attr()){
-					IdString id = node.sparse_attr();
-					target_node.sparse_attr() = id;
-				}
-				alias.push_back(target_index);
-			}
-			else
-			{
-				alias.push_back(GetSize(perm));
-				perm.push_back(i);
-			}
-		}
-		compute_graph.permute(perm, alias);
-		return compute_graph;
-	}
-
-	void printCxx(std::ostream &stream, std::string, std::string const & name, CxxComputeGraph &compute_graph)
+	void printCxx(std::ostream &stream, std::string, std::string const & name, Module *module)
 	{
-		dict<IdString, CxxType> inputs, state;
+		auto ir = FunctionalIR::from_module(module);
 		CxxWriter f(stream);
 
-		// Dump the compute graph
-		for (int i = 0; i < compute_graph.size(); ++i)
-		{
-			auto ref = compute_graph[i];
-			if(ref.function().name == ID($$input))
-				inputs[ref.function().parameters.begin()->first] = ref.function().type;
-			if(ref.function().name == ID($$state))
-				state[ref.function().parameters.begin()->first] = ref.function().type;
-		}
 		f.printf("#include \"sim.h\"\n");
 		f.printf("#include <variant>\n");
-		CxxStruct input_struct(name + "_Inputs", true, inputs.size());
-		for (auto const &input : inputs)
-			input_struct.insert(input.first, input.second);
+		CxxStruct input_struct(name + "_Inputs", true);
+		for (auto [name, sort] : ir.inputs())
+			input_struct.insert(name, sort);
 		CxxStruct output_struct(name + "_Outputs");
-		for (auto const &key : compute_graph.keys())
-			if(state.count(key.first) == 0)
-				output_struct.insert(key.first, compute_graph[key.second].function().type);
+		for (auto [name, sort] : ir.outputs())
+			output_struct.insert(name, sort);
 		CxxStruct state_struct(name + "_State");
-		for (auto const &state_var : state)
-			state_struct.insert(state_var.first, state_var.second);
+		for (auto [name, sort] : ir.state())
+			state_struct.insert(name, sort);
 
-		idict<std::string> node_names;
+		dict<int, std::string> node_names;
 		CxxScope locals;
 
 		input_struct.print(f);
@@ -415,73 +294,17 @@ struct FunctionalCxxBackend : public Backend
 		locals.reserve("output");
 		locals.reserve("current_state");
 		locals.reserve("next_state");
-		for (int i = 0; i < compute_graph.size(); ++i)
-		{
-			auto ref = compute_graph[i];
-			auto type = ref.function().type;
-			std::string name;
-			if(ref.has_sparse_attr())
-				name = locals.insert(ref.sparse_attr());
-			else
-				name = locals.insert("\\n" + std::to_string(i));
-			node_names(name);
-			if(ref.function().name == ID($$input))
-				f.printf("\t%s %s = input.%s;\n", type.to_string().c_str(), name.c_str(), input_struct[ref.function().parameters.begin()->first].c_str());
-			else if(ref.function().name == ID($$state))
-				f.printf("\t%s %s = current_state.%s;\n", type.to_string().c_str(), name.c_str(), state_struct[ref.function().parameters.begin()->first].c_str());
-			else if(ref.function().name == ID($$buf))
-				f.printf("\t%s %s = %s;\n", type.to_string().c_str(), name.c_str(), node_names[ref.arg(0).index()].c_str());
-			else if(ref.function().name == ID($$cell_output))
-				f.printf("\t%s %s = %s.%s;\n", type.to_string().c_str(), name.c_str(), node_names[ref.arg(0).index()].c_str(), RTLIL::unescape_id(ref.function().parameters.begin()->first).c_str());
-			else if(ref.function().name == ID($$const)){
-				auto c = ref.function().parameters.begin()->second;
-				if(c.size() <= 32){
-					f.printf("\t%s %s = $const<%d>(%#x);\n", type.to_string().c_str(), name.c_str(), type.width(), (uint32_t) c.as_int());
-				}else{
-					f.printf("\t%s %s = $const<%d>({%#x", type.to_string().c_str(), name.c_str(), type.width(), (uint32_t) c.as_int());
-					while(c.size() > 32){
-						c = c.extract(32, c.size() - 32);
-						f.printf(", %#x", c.as_int());
-					}
-					f.printf("});\n");
-				}
-			}else if(ref.function().name == ID($$undriven))
-				f.printf("\t%s %s; //undriven\n", type.to_string().c_str(), name.c_str());
-			else if(ref.function().name == ID($$slice))
-				f.printf("\t%s %s = slice<%d>(%s, %d);\n", type.to_string().c_str(), name.c_str(), type.width(), node_names[ref.arg(0).index()].c_str(), ref.function().parameters.at(ID(offset)).as_int());
-			else if(ref.function().name == ID($$concat)){
-				f.printf("\tauto %s = concat(", name.c_str());
-				for (int i = 0, end = ref.size(); i != end; ++i){
-					if(i > 0)
-						f.printf(", ");
-					f.printf("%s", node_names[ref.arg(i).index()].c_str());
-				}
-				f.printf(");\n");
-			}else{
-				f.printf("\t");
-				f.printf("%s %s = %s", type.to_string().c_str(), name.c_str(), log_id(ref.function().name));
-				if(ref.function().parameters.count(ID(WIDTH))){
-					f.printf("<%d>", ref.function().parameters.at(ID(WIDTH)).as_int());
-				}
-				f.printf("(");
-				for (int i = 0, end = ref.size(); i != end; ++i)
-					f.printf("%s%s", i>0?", ":"", node_names[ref.arg(i).index()].c_str());
-				f.printf("); //");
-				for (auto const &param : ref.function().parameters)
-				{
-					if (param.second.empty())
-						f.printf("[%s]", log_id(param.first));
-					else
-						f.printf("[%s=%s]", log_id(param.first), log_const(param.second));
-				}
-				f.printf("\n");
-			}
-		}
-
-		for (auto const &key : compute_graph.keys())
+		auto node_to_string = [&](FunctionalIR::Node n) { return node_names.at(n.id()); };
+		for (auto node : ir)
 		{
-			f.printf("\t%s.%s = %s;\n", state.count(key.first) > 0 ? "next_state" : "output", state_struct[key.first].c_str(), node_names[key.second].c_str());
+			std::string name = locals.insert(node.name());
+			node_names.emplace(node.id(), name);
+			f.printf("\t%s %s = %s;\n", CxxType(node.sort()).to_string().c_str(), name.c_str(), node.visit(CxxPrintVisitor(node_to_string, input_struct, state_struct)).c_str());
 		}
+		for (auto [name, sort] : ir.state())
+			f.printf("\tnext_state.%s = %s;\n", state_struct[name].c_str(), node_to_string(ir.get_state_next_node(name)).c_str());
+		for (auto [name, sort] : ir.outputs())
+			f.printf("\toutput.%s = %s;\n", output_struct[name].c_str(), node_to_string(ir.get_output_node(name)).c_str());
 		f.printf("}\n");
 	}
 
@@ -494,8 +317,7 @@ struct FunctionalCxxBackend : public Backend
 
 		for (auto module : design->selected_modules()) {
             log("Dumping module `%s'.\n", module->name.c_str());
-			auto compute_graph = calculate_compute_graph(module);
-			printCxx(*f, filename, RTLIL::unescape_id(module->name), compute_graph);
+			printCxx(*f, filename, RTLIL::unescape_id(module->name), module);
 		}
 	}
 } FunctionalCxxBackend;
diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc
new file mode 100644
index 00000000000..172ac7fd6f5
--- /dev/null
+++ b/backends/functional/test_generic.cc
@@ -0,0 +1,56 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/functionalir.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct FunctionalTestGeneric : public Pass
+{
+	FunctionalTestGeneric() : Pass("test_generic", "test the generic compute graph") {}
+
+    void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+    }
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+        log_header(design, "Executing Test Generic.\n");
+
+		size_t argidx = 1;
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules()) {
+            log("Dumping module `%s'.\n", module->name.c_str());
+			auto fir = FunctionalIR::from_module(module);
+			for(auto node : fir)
+				std::cout << RTLIL::unescape_id(node.name()) << " = " << node.to_string([](auto n) { return RTLIL::unescape_id(n.name()); }) << "\n";
+			for(auto [name, sort] : fir.outputs())
+				std::cout << RTLIL::unescape_id(name) << " = " << RTLIL::unescape_id(fir.get_output_node(name).name()) << "\n";
+			for(auto [name, sort] : fir.state())
+				std::cout << RTLIL::unescape_id(name) << " = " << RTLIL::unescape_id(fir.get_state_next_node(name).name()) << "\n";
+		}
+	}
+} FunctionalCxxBackend;
+
+PRIVATE_NAMESPACE_END
diff --git a/kernel/functional.h b/kernel/functional.h
index e5ee8824099..09a8826433c 100644
--- a/kernel/functional.h
+++ b/kernel/functional.h
@@ -123,6 +123,8 @@ struct ComputeGraph
         Node &deref() const { this->check(); return this->graph_->nodes[this->index_]; }
 
     public:
+        Ref(BaseRef<ComputeGraph> ref) : Ref(ref.graph_, ref.index_) {}
+
         void set_function(Fn const &function) const
         {
             deref().fn_index = this->graph_->functions(function);
@@ -224,7 +226,7 @@ struct ComputeGraph
     }
 
     template<typename T>
-    Ref add(Fn const &function, Attr const &attr, T const &args)
+    Ref add(Fn const &function, Attr const &attr, T &&args)
     {
         Ref added = add(function, attr);
         for (auto arg : args)
@@ -233,7 +235,23 @@ struct ComputeGraph
     }
 
     template<typename T>
-    Ref add(Fn const &function, Attr &&attr, T const &args)
+    Ref add(Fn const &function, Attr &&attr, T &&args)
+    {
+        Ref added = add(function, std::move(attr));
+        for (auto arg : args)
+            added.append_arg(arg);
+        return added;
+    }
+
+    Ref add(Fn const &function, Attr const &attr, std::initializer_list<Ref> args)
+    {
+        Ref added = add(function, attr);
+        for (auto arg : args)
+            added.append_arg(arg);
+        return added;
+    }
+
+    Ref add(Fn const &function, Attr &&attr, std::initializer_list<Ref> args)
     {
         Ref added = add(function, std::move(attr));
         for (auto arg : args)
diff --git a/kernel/graphtools.h b/kernel/functionalir.cc
similarity index 88%
rename from kernel/graphtools.h
rename to kernel/functionalir.cc
index 4fb7aacf444..27765ac26c5 100644
--- a/kernel/graphtools.h
+++ b/kernel/functionalir.cc
@@ -17,15 +17,8 @@
  *
  */
 
-#ifndef GRAPHTOOLS_H
-#define GRAPHTOOLS_H
+#include "kernel/functionalir.h"
 
-#include "kernel/yosys.h"
-#include "kernel/drivertools.h"
-#include "kernel/functional.h"
-#include "kernel/mem.h"
-
-USING_YOSYS_NAMESPACE
 YOSYS_NAMESPACE_BEGIN
 
 template <class T, class Factory>
@@ -196,7 +189,7 @@ class CellSimplifier {
 };
 
 template <class T, class Factory>
-class ComputeGraphConstruction {
+class FunctionalIRConstruction {
 	std::deque<DriveSpec> queue;
 	dict<DriveSpec, T> graph_nodes;
 	idict<Cell *> cells;
@@ -218,7 +211,7 @@ class ComputeGraphConstruction {
 			return it->second;
 	}
 public:
-	ComputeGraphConstruction(Factory &f) : factory(f), simplifier(f) {}
+	FunctionalIRConstruction(Factory &f) : factory(f), simplifier(f) {}
 	void add_module(Module *module)
 	{
 		driver_map.add(module);
@@ -238,8 +231,9 @@ class ComputeGraphConstruction {
 				memories[mem.cell] = &mem;
 		}
 	}
-	T concatenate_read_results(Mem *mem, vector<T> results)
+	T concatenate_read_results(Mem *, vector<T> results)
 	{
+        /* TODO: write code to check that this is ok to do */
 		if(results.size() == 0)
 			return factory.undriven(0);
 		T node = results[0];
@@ -381,6 +375,60 @@ class ComputeGraphConstruction {
 	}
 };
 
-YOSYS_NAMESPACE_END
+FunctionalIR FunctionalIR::from_module(Module *module) {
+    FunctionalIR ir;
+    auto factory = ir.factory();
+    FunctionalIRConstruction<FunctionalIR::Node, FunctionalIR::Factory> ctor(factory);
+    ctor.add_module(module);
+    ctor.process_queue();
+    ir.topological_sort();
+    ir.forward_buf();
+    return ir;
+}
+
+void FunctionalIR::topological_sort() {
+    Graph::SccAdaptor compute_graph_scc(_graph);
+    bool scc = false;
+    std::vector<int> perm;
+    topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) {
+        perm.insert(perm.end(), begin, end);
+        if (end > begin + 1)
+        {
+            log_warning("SCC:");
+            for (int *i = begin; i != end; ++i)
+                log(" %d", *i);
+            log("\n");
+            scc = true;
+        }
+    }, /* sources_first */ true);
+    _graph.permute(perm);
+    if(scc) log_error("combinational loops, aborting\n");
+}
 
-#endif
+void FunctionalIR::forward_buf() {
+    std::vector<int> perm, alias;
+    perm.clear();
+
+    for (int i = 0; i < _graph.size(); ++i)
+    {
+        auto node = _graph[i];
+        if (node.function().fn() == Fn::buf && node.arg(0).index() < i)
+        {
+            int target_index = alias[node.arg(0).index()];
+            auto target_node = _graph[perm[target_index]];
+            if(!target_node.has_sparse_attr() && node.has_sparse_attr()){
+                IdString id = node.sparse_attr();
+                target_node.sparse_attr() = id;
+            }
+            alias.push_back(target_index);
+        }
+        else
+        {
+            alias.push_back(GetSize(perm));
+            perm.push_back(i);
+        }
+    }
+    _graph.permute(perm, alias);
+}
+
+YOSYS_NAMESPACE_END
diff --git a/kernel/functionalir.h b/kernel/functionalir.h
new file mode 100644
index 00000000000..7eca9d87f83
--- /dev/null
+++ b/kernel/functionalir.h
@@ -0,0 +1,381 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef FUNCTIONALIR_H
+#define FUNCTIONALIR_H
+
+#include "kernel/yosys.h"
+#include "kernel/functional.h"
+#include "kernel/drivertools.h"
+#include "kernel/mem.h"
+#include "kernel/topo_scc.h"
+
+USING_YOSYS_NAMESPACE
+YOSYS_NAMESPACE_BEGIN
+
+class FunctionalIR {
+	enum class Fn {
+		invalid,
+		buf,
+		slice,
+		zero_extend,
+		sign_extend,
+		concat,
+		add,
+		sub,
+		bitwise_and,
+		bitwise_or,
+		bitwise_xor,
+		bitwise_not,
+		reduce_and,
+		reduce_or,
+		reduce_xor,
+		unary_minus,
+		equal,
+		not_equal,
+		signed_greater_than,
+		signed_greater_equal,
+		unsigned_greater_than,
+		unsigned_greater_equal,
+		logical_shift_left,
+		logical_shift_right,
+		arithmetic_shift_right,
+		mux,
+		pmux,
+		constant,
+		input,
+		state,
+		multiple,
+		undriven,
+		memory_read,
+		memory_write
+	};
+public:
+	class Sort {
+		std::variant<int, std::pair<int, int>> _v;
+	public:
+		explicit Sort(int width) : _v(width) { }
+		Sort(int addr_width, int data_width) : _v(std::make_pair(addr_width, data_width)) { }
+		bool is_signal() const { return _v.index() == 0; }
+		bool is_memory() const { return _v.index() == 1; }
+		int width() const { return std::get<0>(_v); }
+		int addr_width() const { return std::get<1>(_v).first; }
+		int data_width() const { return std::get<1>(_v).second; }
+		bool operator==(Sort const& other) const { return _v == other._v; }
+		unsigned int hash() const { return mkhash(_v); }
+	};
+private:
+	class NodeData {
+		Fn _fn;
+		std::variant<
+			std::monostate,
+			RTLIL::Const,
+			IdString,
+			int
+		> _extra;
+	public:
+		NodeData() : _fn(Fn::invalid) {}
+		NodeData(Fn fn) : _fn(fn) {}
+		template<class T> NodeData(Fn fn, T &&extra) : _fn(fn), _extra(std::forward<T>(extra)) {}
+		Fn fn() const { return _fn; }
+		const RTLIL::Const &as_const() const { return std::get<RTLIL::Const>(_extra); }
+		IdString as_idstring() const { return std::get<IdString>(_extra); }
+		int as_int() const { return std::get<int>(_extra); }
+		int hash() const {
+			return mkhash((unsigned int) _fn, mkhash(_extra));
+		}
+		bool operator==(NodeData const &other) const {
+			return _fn == other._fn && _extra == other._extra;
+		}
+	};
+	struct Attr {
+		Sort sort;
+	};
+	using Graph = ComputeGraph<NodeData, Attr, IdString, std::pair<IdString, bool>>;
+	Graph _graph;
+	dict<IdString, Sort> _inputs;
+	dict<IdString, Sort> _outputs;
+	dict<IdString, Sort> _state;
+	void add_input(IdString name, Sort sort) {
+		auto [it, found] = _inputs.emplace(name, std::move(sort));
+		if(found)
+			log_assert(it->second == sort);
+	}
+	void add_state(IdString name, Sort sort) {
+		auto [it, found] = _state.emplace(name, std::move(sort));
+		if(found)
+			log_assert(it->second == sort);
+	}
+	void add_output(IdString name, Sort sort) {
+		auto [it, found] = _outputs.emplace(name, std::move(sort));
+		if(found)
+			log_assert(it->second == sort);
+	}
+public:
+	class Factory;
+	class Node {
+		friend class Factory;
+		friend class FunctionalIR;
+		Graph::Ref _ref;
+		Node(Graph::Ref ref) : _ref(ref) { }
+		operator Graph::Ref() { return _ref; }
+		template<class NodePrinter> struct PrintVisitor {
+			NodePrinter np;
+			PrintVisitor(NodePrinter np) : np(np) { }
+			std::string buf(Node, Node n) { return "buf(" + np(n) + ")"; }
+			std::string slice(Node, Node a, int, int offset, int out_width) { return "slice(" + np(a) + ", " + std::to_string(offset) + ", " + std::to_string(out_width) + ")"; }
+			std::string zero_extend(Node, Node a, int, int out_width) { return "zero_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; }
+			std::string sign_extend(Node, Node a, int, int out_width) { return "sign_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; }
+			std::string concat(Node, Node a, int, Node b, int) { return "concat(" + np(a) + ", " + np(b) + ")"; }
+			std::string add(Node, Node a, Node b, int) { return "add(" + np(a) + ", " + np(b) + ")"; }
+			std::string sub(Node, Node a, Node b, int) { return "sub(" + np(a) + ", " + np(b) + ")"; }
+			std::string bitwise_and(Node, Node a, Node b, int) { return "bitwise_and(" + np(a) + ", " + np(b) + ")"; }
+			std::string bitwise_or(Node, Node a, Node b, int) { return "bitwise_or(" + np(a) + ", " + np(b) + ")"; }
+			std::string bitwise_xor(Node, Node a, Node b, int) { return "bitwise_xor(" + np(a) + ", " + np(b) + ")"; }
+			std::string bitwise_not(Node, Node a, int) { return "bitwise_not(" + np(a) + ")"; }
+			std::string unary_minus(Node, Node a, int) { return "unary_minus(" + np(a) + ")"; }
+			std::string reduce_and(Node, Node a, int) { return "reduce_and(" + np(a) + ")"; }
+			std::string reduce_or(Node, Node a, int) { return "reduce_or(" + np(a) + ")"; }
+			std::string reduce_xor(Node, Node a, int) { return "reduce_xor(" + np(a) + ")"; }
+			std::string equal(Node, Node a, Node b, int) { return "equal(" + np(a) + ", " + np(b) + ")"; }
+			std::string not_equal(Node, Node a, Node b, int) { return "not_equal(" + np(a) + ", " + np(b) + ")"; }
+			std::string signed_greater_than(Node, Node a, Node b, int) { return "signed_greater_than(" + np(a) + ", " + np(b) + ")"; }
+			std::string signed_greater_equal(Node, Node a, Node b, int) { return "signed_greater_equal(" + np(a) + ", " + np(b) + ")"; }
+			std::string unsigned_greater_than(Node, Node a, Node b, int) { return "unsigned_greater_than(" + np(a) + ", " + np(b) + ")"; }
+			std::string unsigned_greater_equal(Node, Node a, Node b, int) { return "unsigned_greater_equal(" + np(a) + ", " + np(b) + ")"; }
+			std::string logical_shift_left(Node, Node a, Node b, int, int) { return "logical_shift_left(" + np(a) + ", " + np(b) + ")"; }
+			std::string logical_shift_right(Node, Node a, Node b, int, int) { return "logical_shift_right(" + np(a) + ", " + np(b) + ")"; }
+			std::string arithmetic_shift_right(Node, Node a, Node b, int, int) { return "arithmetic_shift_right(" + np(a) + ", " + np(b) + ")"; }
+			std::string mux(Node, Node a, Node b, Node s, int) { return "mux(" + np(a) + ", " + np(b) + ", " + np(s) + ")"; }
+			std::string pmux(Node, Node a, Node b, Node s, int, int) { return "pmux(" + np(a) + ", " + np(b) + ", " + np(s) + ")"; }
+			std::string constant(Node, RTLIL::Const value) { return "constant(" + value.as_string() + ")"; }
+			std::string input(Node, IdString name) { return "input(" + name.str() + ")"; }
+			std::string state(Node, IdString name) { return "state(" + name.str() + ")"; }
+			std::string memory_read(Node, Node mem, Node addr, int, int) { return "memory_read(" + np(mem) + ", " + np(addr) + ")"; }
+			std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { return "memory_write(" + np(mem) + ", " + np(addr) + ", " + np(data) + ")"; }
+			std::string undriven(Node, int width) { return "undriven(" + std::to_string(width) + ")"; }
+		};
+	public:
+		int id() const { return _ref.index(); }
+		IdString name() const {
+			if(_ref.has_sparse_attr())
+				return _ref.sparse_attr();
+			else
+				return std::string("\\n") + std::to_string(id());
+		}
+		Sort sort() const { return _ref.attr().sort; }
+		int width() const { return sort().width(); }
+		Node arg(int n) const { return Node(_ref.arg(n)); }
+		template<class Visitor> auto visit(Visitor v) const
+		{
+			switch(_ref.function().fn()) {
+			case Fn::invalid: log_error("invalid node in visit"); break;
+			case Fn::buf: return v.buf(*this, arg(0)); break;
+			case Fn::slice: return v.slice(*this, arg(0), arg(0).width(), _ref.function().as_int(), sort().width()); break;
+			case Fn::zero_extend: return v.zero_extend(*this, arg(0), arg(0).width(), width()); break;
+			case Fn::sign_extend: return v.sign_extend(*this, arg(0), arg(0).width(), width()); break;
+			case Fn::concat: return v.concat(*this, arg(0), arg(0).width(), arg(1), arg(1).width()); break;
+			case Fn::add: return v.add(*this, arg(0), arg(1), sort().width()); break;
+			case Fn::sub: return v.sub(*this, arg(0), arg(1), sort().width()); break;
+			case Fn::bitwise_and: return v.bitwise_and(*this, arg(0), arg(1), sort().width()); break;
+			case Fn::bitwise_or: return v.bitwise_or(*this, arg(0), arg(1), sort().width()); break;
+			case Fn::bitwise_xor: return v.bitwise_xor(*this, arg(0), arg(1), sort().width()); break;
+			case Fn::bitwise_not: return v.bitwise_not(*this, arg(0), sort().width()); break;
+			case Fn::unary_minus: return v.bitwise_not(*this, arg(0), sort().width()); break;
+			case Fn::reduce_and: return v.reduce_and(*this, arg(0), arg(0).width()); break;
+			case Fn::reduce_or: return v.reduce_or(*this, arg(0), arg(0).width()); break;
+			case Fn::reduce_xor: return v.reduce_xor(*this, arg(0), arg(0).width()); break;
+			case Fn::equal: return v.equal(*this, arg(0), arg(1), arg(0).width()); break;
+			case Fn::not_equal: return v.not_equal(*this, arg(0), arg(1), arg(0).width()); break;
+			case Fn::signed_greater_than: return v.signed_greater_than(*this, arg(0), arg(1), arg(0).width()); break; 
+			case Fn::signed_greater_equal: return v.signed_greater_equal(*this, arg(0), arg(1), arg(0).width()); break;
+			case Fn::unsigned_greater_than: return v.unsigned_greater_than(*this, arg(0), arg(1), arg(0).width()); break; 
+			case Fn::unsigned_greater_equal: return v.unsigned_greater_equal(*this, arg(0), arg(1), arg(0).width()); break;
+			case Fn::logical_shift_left: return v.logical_shift_left(*this, arg(0), arg(1), arg(0).width(), arg(1).width()); break;
+			case Fn::logical_shift_right: return v.logical_shift_right(*this, arg(0), arg(1), arg(0).width(), arg(1).width()); break;
+			case Fn::arithmetic_shift_right: return v.arithmetic_shift_right(*this, arg(0), arg(1), arg(0).width(), arg(1).width()); break;
+			case Fn::mux: return v.mux(*this, arg(0), arg(1), arg(2), arg(0).width()); break;
+			case Fn::pmux: return v.pmux(*this, arg(0), arg(1), arg(2), arg(0).width(), arg(2).width()); break;
+			case Fn::constant: return v.constant(*this, _ref.function().as_const()); break;
+			case Fn::input: return v.input(*this, _ref.function().as_idstring()); break;
+			case Fn::state: return v.state(*this, _ref.function().as_idstring()); break;
+			case Fn::memory_read: return v.memory_read(*this, arg(0), arg(1), arg(1).width(), width()); break;
+			case Fn::memory_write: return v.memory_write(*this, arg(0), arg(1), arg(2), arg(1).width(), arg(2).width()); break;
+			case Fn::multiple: log_error("multiple in visit"); break;
+			case Fn::undriven: return v.undriven(*this, width()); break;
+			}
+		}
+		template<class NodePrinter> std::string to_string(NodePrinter np)
+		{
+			return visit(PrintVisitor(np));
+		}
+		/* TODO: delete */ int size() const { return sort().width(); }
+	};
+	class Factory {
+		FunctionalIR &_ir;
+		friend class FunctionalIR;
+		explicit Factory(FunctionalIR &ir) : _ir(ir) {}
+		Node add(NodeData &&fn, Sort &&sort, std::initializer_list<Node> args) {
+			Graph::Ref ref = _ir._graph.add(std::move(fn), {std::move(sort)});
+			for (auto arg : args)
+				ref.append_arg(Graph::Ref(arg));
+			return ref;
+		}
+		void check_basic_binary(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && a.sort() == b.sort()); }
+		void check_shift(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && b.sort().is_signal()); }
+		void check_unary(Node const &a) { log_assert(a.sort().is_signal()); }
+	public:
+		Node slice(Node a, int, int offset, int out_width) {
+			log_assert(a.sort().is_signal() && offset + out_width <= a.sort().width());
+			return add(NodeData(Fn::slice, offset), Sort(out_width), {a});
+		}
+		Node extend(Node a, int, int out_width, bool is_signed) {
+			log_assert(a.sort().is_signal() && a.sort().width() < out_width);
+			if(is_signed)
+				return add(Fn::sign_extend, Sort(out_width), {a});
+			else
+				return add(Fn::zero_extend, Sort(out_width), {a});
+		}
+		Node concat(Node a, int, Node b, int) {
+			log_assert(a.sort().is_signal() && b.sort().is_signal());
+			return add(Fn::concat, Sort(a.sort().width() + b.sort().width()), {a, b});
+		}
+		Node add(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::add, a.sort(), {a, b}); }
+		Node sub(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::sub, a.sort(), {a, b}); }
+		Node bitwise_and(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::bitwise_and, a.sort(), {a, b}); }
+		Node bitwise_or(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::bitwise_or, a.sort(), {a, b}); }
+		Node bitwise_xor(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::bitwise_xor, a.sort(), {a, b}); }
+		Node bitwise_not(Node a, int) { check_unary(a); return add(Fn::bitwise_not, a.sort(), {a}); }
+		Node unary_minus(Node a, int) { check_unary(a); return add(Fn::unary_minus, a.sort(), {a}); }
+		Node reduce_and(Node a, int) { check_unary(a); return add(Fn::reduce_and, Sort(1), {a}); }
+		Node reduce_or(Node a, int) { check_unary(a); return add(Fn::reduce_or, Sort(1), {a}); }
+		Node reduce_xor(Node a, int) { check_unary(a); return add(Fn::reduce_xor, Sort(1), {a}); }
+		Node equal(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::equal, Sort(1), {a, b}); }
+		Node not_equal(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::not_equal, Sort(1), {a, b}); }
+		Node signed_greater_than(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::signed_greater_than, Sort(1), {a, b}); }
+		Node signed_greater_equal(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::signed_greater_equal, Sort(1), {a, b}); }
+		Node unsigned_greater_than(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::unsigned_greater_than, Sort(1), {a, b}); }
+		Node unsigned_greater_equal(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::unsigned_greater_equal, Sort(1), {a, b}); }
+		Node logical_shift_left(Node a, Node b, int, int) { check_shift(a, b); return add(Fn::logical_shift_left, a.sort(), {a, b}); }
+		Node logical_shift_right(Node a, Node b, int, int) { check_shift(a, b); return add(Fn::logical_shift_right, a.sort(), {a, b}); }
+		Node arithmetic_shift_right(Node a, Node b, int, int) { check_shift(a, b); return add(Fn::arithmetic_shift_right, a.sort(), {a, b}); }
+		Node mux(Node a, Node b, Node s, int) {
+			log_assert(a.sort().is_signal() && a.sort() == b.sort() && s.sort() == Sort(1));
+			return add(Fn::mux, a.sort(), {a, b, s});
+		}
+		Node pmux(Node a, Node b, Node s, int, int) {
+			log_assert(a.sort().is_signal() && b.sort().is_signal() && s.sort().is_signal() && a.sort().width() * s.sort().width() == b.sort().width());
+			return add(Fn::pmux, a.sort(), {a, b, s});
+		}
+		Node memory_read(Node mem, Node addr, int, int) {
+			log_assert(mem.sort().is_memory() && addr.sort().is_signal() && mem.sort().addr_width() == addr.sort().width());
+			return add(Fn::memory_read, Sort(mem.sort().data_width()), {mem, addr});
+		}
+		Node memory_write(Node mem, Node addr, Node data, int, int) {
+			log_assert(mem.sort().is_memory() && addr.sort().is_signal() && data.sort().is_signal() &&
+				mem.sort().addr_width() == addr.sort().width() && mem.sort().data_width() == data.sort().width());
+			return add(Fn::memory_write, mem.sort(), {mem, addr, data});
+		}
+		Node constant(RTLIL::Const value) {
+			return add(NodeData(Fn::constant, std::move(value)), Sort(value.size()), {});
+		}
+		Node create_pending(int width) {
+			return add(Fn::buf, Sort(width), {});
+		}
+		void update_pending(Node node, Node value) {
+			log_assert(node._ref.function() == Fn::buf && node._ref.size() == 0 && node.sort() == value.sort());
+			node._ref.append_arg(value._ref);
+		} 
+		Node input(IdString name, int width) {
+			_ir.add_input(name, Sort(width));
+			return add(NodeData(Fn::input, name), Sort(width), {});
+		}
+		Node state(IdString name, int width) {
+			_ir.add_state(name, Sort(width));
+			return add(NodeData(Fn::state, name), Sort(width), {});
+		}
+		Node state_memory(IdString name, int addr_width, int data_width) {
+			_ir.add_state(name, Sort(addr_width, data_width));
+			return add(NodeData(Fn::state, name), Sort(addr_width, data_width), {});
+		}
+		Node cell_output(Node node, IdString, IdString, int) {
+			return node;
+		}
+		Node multiple(vector<Node> args, int width) {
+			auto node = add(Fn::multiple, Sort(width), {});
+			for(const auto &arg : args)
+				node._ref.append_arg(arg._ref);
+			return node;
+		}
+		Node undriven(int width) {
+			return add(Fn::undriven, Sort(width), {});
+		}
+		void declare_output(Node node, IdString name, int width) {
+			_ir.add_output(name, Sort(width));
+			node._ref.assign_key({name, false});
+		}
+		void declare_state(Node node, IdString name, int width) {
+			_ir.add_state(name, Sort(width));
+			node._ref.assign_key({name, true});
+		}
+		void declare_state_memory(Node node, IdString name, int addr_width, int data_width) {
+			_ir.add_state(name, Sort(addr_width, data_width));
+			node._ref.assign_key({name, true});
+		}
+		void suggest_name(Node node, IdString name) {
+			node._ref.sparse_attr() = name;
+		}
+
+		/* TODO delete this later*/
+		Node eq(Node a, Node b, int) { return equal(a, b, 0); }
+		Node ne(Node a, Node b, int) { return not_equal(a, b, 0); }
+		Node gt(Node a, Node b, int) { return signed_greater_than(a, b, 0); }
+		Node ge(Node a, Node b, int) { return signed_greater_equal(a, b, 0); }
+		Node ugt(Node a, Node b, int) { return unsigned_greater_than(a, b, 0); }
+		Node uge(Node a, Node b, int) { return unsigned_greater_equal(a, b, 0); }
+		Node neg(Node a, int) { return unary_minus(a, 0); }
+	};
+	static FunctionalIR from_module(Module *module);
+	Factory factory() { return Factory(*this); }
+	int size() const { return _graph.size(); }
+	Node operator[](int i) { return _graph[i]; }
+	void topological_sort();
+	void forward_buf();
+	dict<IdString, Sort> inputs() const { return _inputs; }
+	dict<IdString, Sort> outputs() const { return _outputs; }
+	dict<IdString, Sort> state() const { return _state; }
+	Node get_output_node(IdString name) { return _graph({name, false}); }
+	Node get_state_next_node(IdString name) { return _graph({name, true}); }
+	class Iterator {
+		friend class FunctionalIR;
+		FunctionalIR &_ir;
+		int _index;
+		Iterator(FunctionalIR &ir, int index) : _ir(ir), _index(index) {}
+	public:
+		Node operator*() { return _ir._graph[_index]; }
+		Iterator &operator++() { _index++; return *this; }
+		bool operator!=(Iterator const &other) const { return _index != other._index; }
+	};
+	Iterator begin() { return Iterator(*this, 0); }
+	Iterator end() { return Iterator(*this, _graph.size()); }
+};
+
+YOSYS_NAMESPACE_END
+
+#endif

From 4e370f4426bf53144b322911d0a68c4724d2dfea Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Fri, 21 Jun 2024 12:59:34 +0200
Subject: [PATCH 376/499] Initial functional SMT backend using functional IR

---
 backends/functional/Makefile.inc |   2 +-
 backends/functional/cxx.cc       |   4 +-
 backends/functional/smtlib.cc    | 835 +++++++++++--------------------
 3 files changed, 291 insertions(+), 550 deletions(-)

diff --git a/backends/functional/Makefile.inc b/backends/functional/Makefile.inc
index f4b968ef371..13c962c99ff 100644
--- a/backends/functional/Makefile.inc
+++ b/backends/functional/Makefile.inc
@@ -1,3 +1,3 @@
 OBJS += backends/functional/cxx.o
-#OBJS += backends/functional/smtlib.o
+OBJS += backends/functional/smtlib.o
 OBJS += backends/functional/test_generic.o
diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index 789ab7949ba..9571385ccb3 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -216,8 +216,8 @@ template<class NodeNames> struct CxxPrintVisitor {
 	CxxStruct &state_struct;
 	CxxPrintVisitor(NodeNames np, CxxStruct &input_struct, CxxStruct &state_struct) : np(np), input_struct(input_struct), state_struct(state_struct) { }
 	template<class T> std::string arg_to_string(T n) { return std::to_string(n); }
-	template<> std::string arg_to_string(std::string n) { return n; }
-	template<> std::string arg_to_string(Node n) { return np(n); }
+	std::string arg_to_string(std::string n) { return n; }
+	std::string arg_to_string(Node n) { return np(n); }
 	template<typename... Args> std::string format(std::string fmt, Args&&... args) {
 		return CxxTemplate::format(fmt, arg_to_string(args)...);
 	}
diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index a90927ab6f5..a24ab84017f 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -18,574 +18,315 @@
  */
 
 #include "kernel/yosys.h"
-#include "kernel/drivertools.h"
-#include "kernel/topo_scc.h"
-#include "kernel/functional.h"
-#include "kernel/graphtools.h"
+#include "kernel/functionalir.h"
+#include <cassert>
+#include <sstream>
+#include <vector>
+#include <string>
+#include <unordered_map>
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-struct SmtlibScope {
-	pool<std::string> used_names;
-	dict<IdString, std::string> name_map;
-
-	SmtlibScope() {
-		/*for(const char **p = reserved_keywords; *p != nullptr; p++)
-			reserve(*p);*/
-	}
-	void reserve(std::string name) {
-		used_names.insert(name);
-	}
-	std::string insert(IdString id) {
-		std::string str = RTLIL::unescape_id(id);
-		for(size_t i = 0; i < str.size(); i++)
-			if(!((unsigned char)str[i] < 0x80 && (isalnum(str[i]) || strchr("~!@$%^&*_-+=<>.?/", str[i]))))
-				str[i] = '_';
-		if(used_names.count(str) == 0){
-			used_names.insert(str);
-			name_map.insert({id, str});
-			return str;
-		}
-		for (int idx = 0 ; ; idx++){
-			std::string suffixed = str + "_" + std::to_string(idx);
-			if (used_names.count(suffixed) == 0) {
-				used_names.insert(suffixed);
-				if(name_map.count(id) == 0)
-					name_map.insert({id, suffixed});
-				return suffixed;
-			}
-		}
-	}
-	std::string operator[](IdString id) {
-		if(name_map.count(id) > 0)
-			return name_map[id];
-		else
-			return insert(id);
-	}
-};
+struct SmtScope {
+  pool<std::string> used_names;
+  dict<IdString, std::string> name_map;
+
+  SmtScope() {}
+    
+  void reserve(const std::string& name) {
+    used_names.insert(name);
+  }
+
+  std::string insert(IdString id) {
+    std::string name = RTLIL::unescape_id(id);
+    if (used_names.count(name) == 0) {
+      used_names.insert(name);
+      name_map[id] = name;
+      return name;
+    }
+    for (int idx = 0;; ++idx) {
+      std::string new_name = name + "_" + std::to_string(idx);
+      if (used_names.count(new_name) == 0) {
+	used_names.insert(new_name);
+	name_map[id] = new_name;
+	return new_name;
+      }
+    }
+  }
 
-struct SmtlibWriter {
-	std::ostream &f;
-	SmtlibWriter(std::ostream &out) : f(out) {}
-	void printf(const char *fmt, ...)
-	{
-		va_list va;
-		va_start(va, fmt);
-		f << vstringf(fmt, va);
-		va_end(va);
-	}
-	template <typename T>
-	SmtlibWriter & operator <<(T &&arg) {
-		f << std::forward<T>(arg);
-		return *this;
-	}
+  std::string operator[](IdString id) {
+    if (name_map.count(id)) {
+      return name_map[id];
+    } else {
+      return insert(id);
+    }
+  }
 };
 
-struct Arg {
-    int n;
-    explicit Arg(int n_) : n(n_) {}
-	bool operator ==(Arg const &other) const { return n == other.n; }
+struct SmtWriter {
+  std::ostream& stream;
+
+  SmtWriter(std::ostream& out) : stream(out) {}
+
+  void print(const char* fmt, ...) {
+    va_list args;
+    va_start(args, fmt);
+    stream << vstringf(fmt, args);
+    va_end(args);
+  }
 };
 
-class SExpr {
-	enum class Type {
-		None,
-		List,
-		Atom,
-		Arg,
-	};
-	Type type = Type::None;
-	union {
-		std::string atom_;
-		vector<SExpr> list_;
-        Arg arg_;
-	};
-    void set_none() {
-        switch(type) {
-        case Type::None: break;
-        case Type::Atom: atom_.~basic_string(); break;
-        case Type::List: list_.~vector(); break;
-        case Type::Arg: arg_.~Arg(); break;
-        }
-        type = Type::None;
-    }
-public:
-	SExpr() {}
-    SExpr(const char *atom) : type(Type::Atom), atom_(atom) {}
-	SExpr(std::string atom) : type(Type::Atom), atom_(atom) {}
-	SExpr(int n) : type(Type::Atom), atom_(std::to_string(n)) {}
-	SExpr(RTLIL::Const const & n) : type(Type::Atom) {
-		new(&atom_) std::string("#b");
-		atom_.reserve(n.size() + 2);
-		for (size_t i = n.size(); i > 0; i--)
-			if(n[i-1] == State::S1)
-				atom_ += "1";
-			else
-				atom_ += "0";
-	}
-	SExpr(vector<SExpr> &&list) : type(Type::List), list_(list) {}
-    SExpr(std::initializer_list<SExpr> list) : type(Type::List), list_(list) {}
-    SExpr(Arg arg) : type(Type::Arg), arg_(arg) {}
-    SExpr(SExpr const &other) { *this = other; }
-    SExpr(SExpr &&other) { *this = std::move(other); }
-    SExpr &operator =(SExpr const &other) {
-        set_none();
-        switch(other.type) {
-        case Type::None: break;
-        case Type::Atom: new(&atom_) std::string(other.atom_); break;
-        case Type::List: new(&list_) vector<SExpr>(other.list_); break;
-        case Type::Arg: new(&arg_) Arg(other.arg_); break;
-        }
-        type = other.type;
-        return *this;
-    }
-    SExpr &operator =(SExpr &&other) {
-        set_none();
-        switch(other.type) {
-        case Type::None: break;
-        case Type::Atom: new(&atom_) std::string(std::move(other.atom_)); break;
-        case Type::List: new(&list_) vector<SExpr>(std::move(other.list_)); break;
-        case Type::Arg: new(&arg_) Arg(std::move(other.arg_)); break;
-        }
-        type = other.type;
-        return *this;
+template<class NodeNames>
+struct SmtPrintVisitor {
+  using Node = FunctionalIR::Node;
+  NodeNames np;
+  SmtScope &scope;
+
+  SmtPrintVisitor(NodeNames np, SmtScope &scope)
+    : np(np), scope(scope) {}
+
+  template<class T>
+  std::string arg_to_string(T n) { return std::to_string(n); }
+
+  std::string arg_to_string(std::string n) { return n; }
+
+  std::string arg_to_string(Node n) { return np(n); }
+
+  template<typename... Args>
+  std::string format(std::string fmt, Args&&... args) {
+    std::vector<std::string> arg_strings = { arg_to_string(std::forward<Args>(args))... };
+    for (size_t i = 0; i < arg_strings.size(); ++i) {
+      std::string placeholder = "%" + std::to_string(i);
+      size_t pos = 0;
+      while ((pos = fmt.find(placeholder, pos)) != std::string::npos) {
+	fmt.replace(pos, placeholder.length(), arg_strings[i]);
+	pos += arg_strings[i].length();
+      }
     }
-    ~SExpr() { set_none(); }
-	bool operator==(SExpr const &other) const {
-		if(type != other.type) return false;
-		switch(type) {
-		case Type::None: return true;
-		case Type::Atom: return atom_ == other.atom_;
-		case Type::List: return list_ == other.list_;
-		case Type::Arg: return arg_ == other.arg_;
-		}
-	}
-    bool is_none() const { return type == Type::None; }
-	bool is_atom() const { return type == Type::Atom; }
-	bool is_list() const { return type == Type::List; }
-    bool is_arg() const { return type == Type::Arg; }
-    std::string const &atom() const { log_assert(is_atom()); return atom_; }
-    std::vector<SExpr> const &list() const { log_assert(is_list()); return list_; }
-    Arg const &arg() const { log_assert(is_arg()); return arg_; }
-	unsigned int hash() const {
-		unsigned int inner;
-		switch(type) {
-		case Type::None: inner = 0; break;
-		case Type::Atom: inner = mkhash(atom_); break;
-		case Type::List: inner = mkhash(list_); break;
-		case Type::Arg: inner = arg_.n; break;
-		}
-		return mkhash((unsigned int) type, inner);
-	}
-	SExpr subst_args(std::vector<SExpr> const & args) const {
-		switch(type) {
-		case Type::None:
-		case Type::Atom:
-			return *this;
-		case Type::List: {
-			vector<SExpr> ret;
-			for(auto & a : list_)
-				ret.emplace_back(a.subst_args(args));
-			return SExpr(std::move(ret));
-		}
-		case Type::Arg:
-			if(arg_.n >= 1 && (size_t)arg_.n <= args.size())
-				return args[arg_.n - 1];
-			else
-				return *this;
-		}
-	}
+    return fmt;
+  }
+  std::string buf(Node, Node n) { return np(n); }
+
+  std::string slice(Node, Node a, int, int offset, int out_width) {
+    return format("(_ extract %1 %2 %0)", np(a), offset, offset + out_width - 1);
+  }
+
+  std::string zero_extend(Node, Node a, int, int out_width) {
+    return format("((_ zero_extend %1) %0)", np(a), out_width);
+  }
+
+  std::string sign_extend(Node, Node a, int, int out_width) {
+    return format("((_ sign_extend %1) %0)", np(a), out_width);
+  }
+
+  std::string concat(Node, Node a, int, Node b, int) {
+    return format("(concat %0 %1)", np(a), np(b));
+  }
+
+  std::string add(Node, Node a, Node b, int) {
+    return format("(bvadd %0 %1)", np(a), np(b));
+  }
+
+  std::string sub(Node, Node a, Node b, int) {
+    return format("(bvsub %0 %1)", np(a), np(b));
+  }
+
+  std::string bitwise_and(Node, Node a, Node b, int) {
+    return format("(bvand %0 %1)", np(a), np(b));
+  }
+
+  std::string bitwise_or(Node, Node a, Node b, int) {
+    return format("(bvor %0 %1)", np(a), np(b));
+  }
+
+  std::string bitwise_xor(Node, Node a, Node b, int) {
+    return format("(bvxor %0 %1)", np(a), np(b));
+  }
+
+  std::string bitwise_not(Node, Node a, int) {
+    return format("(bvnot %0)", np(a));
+  }
+
+  std::string unary_minus(Node, Node a, int) {
+    return format("(bvneg %0)", np(a));
+  }
+
+  std::string reduce_and(Node, Node a, int) {
+    return format("(= %0 #b1)", np(a));
+  }
+
+  std::string reduce_or(Node, Node a, int) {
+    return format("(distinct %0 #b0)", np(a));
+  }
+
+  std::string reduce_xor(Node, Node a, int) {
+    return format("(bvxor_reduce %0)", np(a));
+  }
+
+  std::string equal(Node, Node a, Node b, int) {
+    return format("(= %0 %1)", np(a), np(b));
+  }
+
+  std::string not_equal(Node, Node a, Node b, int) {
+    return format("(distinct %0 %1)", np(a), np(b));
+  }
+
+  std::string signed_greater_than(Node, Node a, Node b, int) {
+    return format("(bvsgt %0 %1)", np(a), np(b));
+  }
+
+  std::string signed_greater_equal(Node, Node a, Node b, int) {
+    return format("(bvsge %0 %1)", np(a), np(b));
+  }
+
+  std::string unsigned_greater_than(Node, Node a, Node b, int) {
+    return format("(bvugt %0 %1)", np(a), np(b));
+  }
+
+  std::string unsigned_greater_equal(Node, Node a, Node b, int) {
+    return format("(bvuge %0 %1)", np(a), np(b));
+  }
+
+  std::string logical_shift_left(Node, Node a, Node b, int, int) {
+    return format("(bvshl %0 %1)", np(a), np(b));
+  }
+
+  std::string logical_shift_right(Node, Node a, Node b, int, int) {
+    return format("(bvlshr %0 %1)", np(a), np(b));
+  }
+
+  std::string arithmetic_shift_right(Node, Node a, Node b, int, int) {
+    return format("(bvashr %0 %1)", np(a), np(b));
+  }
+
+  std::string mux(Node, Node a, Node b, Node s, int) {
+    return format("(ite %2 %0 %1)", np(a), np(b), np(s));
+  }
+
+  std::string pmux(Node, Node a, Node b, Node s, int, int) {
+    // Assume s is a bit vector, combine a and b based on the selection bits
+    return format("(pmux %0 %1 %2)", np(a), np(b), np(s));
+  }
+
+  std::string constant(Node, RTLIL::Const value) {
+    return format("#b%1", value.as_string());
+  }
+
+  std::string input(Node, IdString name) {
+    return format("%0", scope[name]);
+  }
+
+  std::string state(Node, IdString name) {
+    return format("%0", scope[name]);
+  }
+
+  std::string memory_read(Node, Node mem, Node addr, int, int) {
+    return format("(select %0 %1)", np(mem), np(addr));
+  }
+
+  std::string memory_write(Node, Node mem, Node addr, Node data, int, int) {
+    return format("(store %0 %1 %2)", np(mem), np(addr), np(data));
+  }
+
+  std::string undriven(Node, int width) {
+    return format("#b%0", std::string(width, '0'));
+  }
 };
+struct SmtModule {
+  std::string name;
+  SmtScope scope;
+  FunctionalIR ir;
+
+  SmtModule(const std::string& module_name, FunctionalIR ir) 
+    : name(module_name), ir(std::move(ir)) {}
+
+  void write(std::ostream& out) {
+    SmtWriter writer(out);
+        
+    writer.print("(declare-fun %s () Bool)\n", name.c_str());
+
+    writer.print("(declare-datatypes () ((Inputs (mk_inputs");
+    for (const auto& input : ir.inputs()) {
+      std::string input_name = scope[input.first];
+      writer.print(" (%s (_ BitVec %d))", input_name.c_str(), input.second.width());
+    }
+    writer.print("))))\n");
 
-std::ostream& operator << (std::ostream &os, SExpr const &s) {
-    if(s.is_atom())
-        os << s.atom();
-    else if(s.is_list()){
-        os << "(";
-        bool first = true;
-        for(auto &el: s.list()) {
-            if(!first) os << " ";
-            else first = false;
-            os << el;
-        }
-        os << ")";
-    }else if(s.is_arg())
-        os << "#" << s.arg().n;
-    else if(s.is_none())
-        os << "<none>";
-    else
-        os << "???";
-    return os;
-}
-
-struct SmtlibType {
-	bool _is_memory;
-	int _width;
-	int _addr_width;
-public:
-	SmtlibType() : _is_memory(false), _width(0), _addr_width(0) { }
-	SmtlibType(int width) : _is_memory(false), _width(width), _addr_width(0) { }
-	SmtlibType(int addr_width, int data_width) : _is_memory(true), _width(data_width), _addr_width(addr_width) { }
-	static SmtlibType signal(int width) { return SmtlibType(width); }
-	static SmtlibType memory(int addr_width, int data_width) { return SmtlibType(addr_width, data_width); }
-	bool is_signal() const { return !_is_memory; }
-	bool is_memory() const { return _is_memory; }
-	int width() const { log_assert(is_signal()); return _width; }
-	int addr_width() const { log_assert(is_memory()); return _addr_width; }
-	int data_width() const { log_assert(is_memory()); return _width; }
-	SExpr to_sexpr() const {
-		if(_is_memory) {
-			return SExpr{ "Array", SExpr{ "_", "BitVec", addr_width() }, SExpr{ "_", "BitVec", data_width() }};
-		} else {
-			return SExpr{ "_", "BitVec", width() };
-		}
-	}
-	bool operator ==(SmtlibType const& other) const {
-		if(_is_memory != other._is_memory) return false;
-		if(_is_memory && _addr_width != other._addr_width) return false;
-		return _width == other._width;
-	}
-	unsigned int hash() const {
-		if(_is_memory)
-			return mkhash(1, mkhash(_width, _addr_width));
-		else
-			return mkhash(0, _width);
-	}
-};
+    writer.print("(declare-datatypes () ((Outputs (mk_outputs");
+    for (const auto& output : ir.outputs()) {
+      std::string output_name = scope[output.first];
+      writer.print(" (%s (_ BitVec %d))", output_name.c_str(), output.second.width());
+    }
+    writer.print("))))\n");
 
-struct SmtlibStruct {
-	SmtlibScope &scope;
-	std::string name;
-	idict<IdString> members;
-	vector<SmtlibType> types;
-	vector<std::string> accessors;
-	SmtlibStruct(std::string name, SmtlibScope &scope) : scope(scope), name(name) {
-	}
-	std::string insert(IdString field, SmtlibType type) {
-		if(members.at(field, -1) == -1){
-			members(field);
-			scope.insert(field);
-			types.push_back(type);
-			accessors.push_back(scope.insert(std::string("\\") + name + "_" + RTLIL::unescape_id(field)));
-		}
-		return scope[field];
-	}
-	void print(SmtlibWriter &f) {
-		f.printf("(declare-datatype %s ((%s\n", name.c_str(), name.c_str());
-		for (size_t i = 0; i < members.size(); i++)
-			f << "  " << SExpr{accessors[i], types[i].to_sexpr()} << "\n";
-		f.printf(")))\n");
-	}
-	void print_value(SmtlibWriter &f, dict<IdString, SExpr> values, int indentation) {
-		std::string spaces(indentation, ' ');
-		f << spaces << "(" << name << "\n";
-		for (size_t i = 0; i < members.size(); i++)
-			f << spaces << "  " << values[members[i]] << "    ; " << RTLIL::unescape_id(members[i]) << "\n";
-		f << spaces << ")\n";
-	}
-	SExpr access(SExpr record, IdString member) {
-		int i = members.at(member);
-		return SExpr{accessors[i], record};
-	}
-	std::string operator[](IdString field) {
-		return scope[field];
-	}
-};
+    writer.print("(declare-fun state () (_ BitVec 1))\n");
 
-struct Node {
-	SExpr expr;
-	SmtlibType type;
+    writer.print("(define-fun %s_step ((state (_ BitVec 1)) (inputs Inputs)) Outputs\n", name.c_str());
 
-	Node(SExpr &&expr, SmtlibType type) : expr(std::move(expr)), type(type) {}
+    writer.print("  (let (\n");
+    for (const auto& input : ir.inputs()) {
+      std::string input_name = scope[input.first];
+      writer.print("    (%s (%s inputs))\n", input_name.c_str(), input_name.c_str());
+    }
+    writer.print("  )\n");
+
+    auto node_to_string = [&](FunctionalIR::Node n) { return scope[n.name()]; };
+    SmtPrintVisitor<decltype(node_to_string)> visitor(node_to_string, scope);
+    writer.print("    (let (\n");
+    for (auto it = ir.begin(); it != ir.end(); ++it) {
+      const FunctionalIR::Node& node = *it;
+
+      if (ir.inputs().count(node.name()) > 0) {
+        continue;
+      }
+      
+      std::string node_name = scope[node.name()];
+      std::string node_expr = node.visit(visitor);
+      writer.print("      (%s %s)\n", node_name.c_str(), node_expr.c_str());
+    }
+    writer.print("    )\n");
 
-	bool operator==(Node const &other) const {
-		return expr == other.expr && type == other.type;
-	}
+    writer.print("      (let (\n");
+    for (const auto& output : ir.outputs()) {
+      std::string output_name = scope[output.first];
+      // writer.print("        (%s %s)\n", output_name.c_str(), scope[output_name].c_str());
+    }
+    writer.print("      )\n");
 
-	unsigned int hash() const {
-		return mkhash(expr.hash(), type.hash());
-	}
+    writer.print("        (mk_outputs\n");
+    for (const auto& output : ir.outputs()) {
+      std::string output_name = scope[output.first];
+      writer.print("          %s\n", output_name.c_str());
+    }
+    writer.print("        )\n");
+    writer.print("      )\n");
+    writer.print("    )\n");
+    writer.print("  )\n");
+    writer.print(")\n");
+  }
 };
 
-typedef ComputeGraph<Node, int, IdString, IdString> SmtlibComputeGraph;
-
-struct SmtlibModule {
-	std::string name;
-	SmtlibScope global_scope;
-	SmtlibStruct input_struct;
-	SmtlibStruct output_struct;
-	SmtlibStruct state_struct;
-	SmtlibComputeGraph compute_graph;
-
-	SmtlibModule(std::string const &name) :
-		name(name),
-		input_struct(name + "_inputs", global_scope),
-		output_struct(name + "_outputs", global_scope),
-		state_struct(name + "_state", global_scope)
-	{ }
-	void calculate_compute_graph(RTLIL::Module *module);
-	void write(std::ostream &stream);
-};
+struct FunctionalSmtBackend : public Backend {
+  FunctionalSmtBackend() : Backend("functional_smt2", "Generate SMT-LIB from Functional IR") {}
 
-class SmtlibComputeGraphFactory {
-	SmtlibModule &module;
-	SmtlibComputeGraph &graph;
-	using T = SmtlibComputeGraph::Ref;
-	static bool is_single_output(IdString type)
-	{
-		auto it = yosys_celltypes.cell_types.find(type);
-		return it != yosys_celltypes.cell_types.end() && it->second.outputs.size() <= 1;
-	}
-	T node(SExpr &&expr, SmtlibType type, std::initializer_list<T> args) {
-		return graph.add(Node(std::move(expr), type), 0, args);
-	}
-	T shift(const char *name, T a, T b, int y_width, int b_width, bool a_signed = false) {
-		int width = max(y_width, b_width);
-		T a_ = y_width < width ? extend(a, y_width, width, a_signed) : a;
-		T b_ = b_width < width ? extend(b, b_width, width, false) : b;
-		T y_ = node(SExpr {name, Arg(1), Arg(2)}, width, {a_, b_});
-		if(y_width < width)
-			return slice(y_, width, 0, y_width);
-		else
-			return y_;
-	}
-	SExpr from_bool(SExpr &&arg) {
-		return SExpr{"ite", std::move(arg), RTLIL::Const(State::S1), RTLIL::Const(State::S0)};
-	}
-	SExpr to_bool(SExpr &&arg) {
-		return SExpr{"=", std::move(arg), RTLIL::Const(State::S1)};
-	}
-	SExpr extract(SExpr &&arg, int offset, int out_width) {
-		return SExpr {SExpr {"_", "extract", offset + out_width - 1, offset}, std::move(arg)};
-	}
-public:
-	SmtlibComputeGraphFactory(SmtlibModule &mod) : module(mod), graph(mod.compute_graph) {}
-	T slice(T a, int in_width, int offset, int out_width) {
-		log_assert(offset + out_width <= in_width);
-		return node(extract(Arg(1), offset, out_width), out_width, {a});
-	}
-	T extend(T a, int in_width, int out_width, bool is_signed) {
-		log_assert(in_width < out_width);
-		if(is_signed)
-			return node(SExpr {SExpr {"_", "sign_extend", out_width - in_width}, Arg(1)}, out_width, {a});
-		else
-			return node(SExpr {SExpr {"_", "zero_extend", out_width - in_width}, Arg(1)}, out_width, {a});
-	}
-	T concat(T a, int a_width, T b, int b_width) {
-		return node(SExpr {"concat", Arg(1), Arg(2)}, a_width + b_width, {a, b});
-	}
-	T add(T a, T b, int width) { return node(SExpr {"bvadd", Arg(1), Arg(2)}, width, {a, b}); }
-	T sub(T a, T b, int width) { return node(SExpr {"bvsub", Arg(1), Arg(2)}, width, {a, b}); }
-	T bitwise_and(T a, T b, int width) { return node(SExpr {"bvand", Arg(1), Arg(2)}, width, {a, b}); }
-	T bitwise_or(T a, T b, int width) { return node(SExpr {"bvor", Arg(1), Arg(2)}, width, {a, b}); }
-	T bitwise_xor(T a, T b, int width) { return node(SExpr {"bvxor", Arg(1), Arg(2)}, width, {a, b}); }
-	T bitwise_not(T a, int width) { return node(SExpr {"bvnot", Arg(1)}, width, {a}); }
-	T neg(T a, int width) { return node(SExpr {"bvneg", Arg(1)}, width, {a}); }
-	T mux(T a, T b, T s, int width) { return node(SExpr {"ite", to_bool(Arg(1)), Arg(2), Arg(3)}, width, {s, a, b}); }
-	T pmux(T a, T b, T s, int width, int s_width) { 
-		T rv = a;
-		for(int i = 0; i < s_width; i++)
-			rv = node(SExpr {"ite", to_bool(extract(Arg(1), i, 1)), extract(Arg(2), width * i, width), Arg(3)}, width, {s, b, rv});
-		return rv;
-	}
-	T reduce_and(T a, int width) { return node(from_bool(SExpr {"=", Arg(1), RTLIL::Const(State::S1, width)}), 1, {a}); }
-	T reduce_or(T a, int width) { return node(from_bool(SExpr {"distinct", Arg(1), RTLIL::Const(State::S0, width)}), 1, {a}); }
-	T reduce_xor(T a, int) { return node(SExpr {"reduce_xor", Arg(1)}, 1, {a}); }
-	T eq(T a, T b, int) { return node(from_bool(SExpr {"=", Arg(1), Arg(2)}), 1, {a, b}); }
-	T ne(T a, T b, int) { return node(from_bool(SExpr {"distinct", Arg(1), Arg(2)}), 1, {a, b}); }
-	T gt(T a, T b, int) { return node(from_bool(SExpr {"bvsgt", Arg(1), Arg(2)}), 1, {a, b}); }
-	T ge(T a, T b, int) { return node(from_bool(SExpr {"bvsge", Arg(1), Arg(2)}), 1, {a, b}); }
-	T ugt(T a, T b, int) { return node(from_bool(SExpr {"bvugt", Arg(1), Arg(2)}), 1, {a, b}); }
-	T uge(T a, T b, int) { return node(from_bool(SExpr {"bvuge", Arg(1), Arg(2)}), 1, {a, b}); }
-	T logical_shift_left(T a, T b, int y_width, int b_width) { return shift("bvshl", a, b, y_width, b_width); }
-	T logical_shift_right(T a, T b, int y_width, int b_width) { return shift("bvlshl", a, b, y_width, b_width); }
-	T arithmetic_shift_right(T a, T b, int y_width, int b_width) { return shift("bvashr", a, b, y_width, b_width, true); }
-
-	T memory_read(T mem, T addr, int addr_width, int data_width) {
-		return node(SExpr {"select", Arg(1), Arg(2)}, data_width, {mem, addr});
-	}
-	T memory_write(T mem, T addr, T data, int addr_width, int data_width) {
-		return node(SExpr {"store", Arg(1), Arg(2), Arg(3)}, SmtlibType::memory(addr_width, data_width), {mem, addr, data});
-	}
-
-	T constant(RTLIL::Const value) { return node(SExpr(value), value.size(), {}); }
-	T input(IdString name, int width) {
-		module.input_struct.insert(name, width);
-		return node(module.input_struct.access("inputs", name), width, {});
-	}
-	T state(IdString name, int width) {
-		module.state_struct.insert(name, width);
-		return node(module.state_struct.access("current_state", name), width, {});
-	}
-	T state_memory(IdString name, int addr_width, int data_width) {
-		module.state_struct.insert(name, SmtlibType::memory(addr_width, data_width));
-		return node(module.state_struct.access("current_state", name), SmtlibType::memory(addr_width, data_width), {});
-	}
-	T cell_output(T cell, IdString type, IdString name, int width) {
-		if (is_single_output(type))
-			return cell;
-		else
-			return node(SExpr {"cell_output", Arg(1), RTLIL::unescape_id(name)}, width, {cell});
-	}
-	T multiple(vector<T> args, int width) {
-		vector<SExpr> expr;
-		expr.reserve(args.size() + 1);
-		expr.push_back("multiple");
-		for(size_t i = 1; i <= args.size(); i++)
-			expr.push_back(Arg(i));
-		return graph.add(Node(SExpr(std::move(expr)), width), 0, args);
-	}
-	T undriven(int width) {
-		return constant(RTLIL::Const(State::S0, width));
-		//return node(SExpr {"undriven"}, width, {});
-	}
-	T create_pending(int width) {
-		return node(SExpr(), width, {});
-	}
-	void update_pending(T pending, T node) {
-		log_assert(pending.function().expr.is_none());
-		pending.set_function(Node(Arg(1), pending.function().type));
-		pending.append_arg(node);
-	}
-	void declare_output(T node, IdString name, int width) {
-		module.output_struct.insert(name, width);
-		node.assign_key(name);
-	}
-	void declare_state(T node, IdString name, int width) {
-		module.state_struct.insert(name, width);
-		node.assign_key(name);
-	}
-	void declare_state_memory(T node, IdString name, int addr_width, int data_width) {
-		module.state_struct.insert(name, SmtlibType::memory(addr_width, data_width));
-		node.assign_key(name);
-	}
-	void suggest_name(T node, IdString name) {
-		node.sparse_attr() = name;
-	}
-};
+  void help() override {
+    log("\nFunctional SMT Backend.\n\n");
+  }
 
-void SmtlibModule::calculate_compute_graph(RTLIL::Module *module)
-{
-	SmtlibComputeGraphFactory factory(*this);
-	ComputeGraphConstruction<SmtlibComputeGraph::Ref, SmtlibComputeGraphFactory> construction(factory);
-	construction.add_module(module);
-	construction.process_queue();
-
-	// Perform topo sort and detect SCCs
-	SmtlibComputeGraph::SccAdaptor compute_graph_scc(compute_graph);
-
-	bool scc = false;
-	std::vector<int> perm;
-	topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) {
-		perm.insert(perm.end(), begin, end);
-		if (end > begin + 1)
-		{
-			log_warning("SCC:");
-			for (int *i = begin; i != end; ++i)
-				log(" %d", *i);
-			log("\n");
-			scc = true;
-		}
-	}, /* sources_first */ true);
-	compute_graph.permute(perm);
-	if(scc) log_error("combinational loops, aborting\n");
-
-	// Forward $$buf
-	std::vector<int> alias;
-	perm.clear();
-
-	for (int i = 0; i < compute_graph.size(); ++i)
-	{
-		auto node = compute_graph[i];
-		if (node.function().expr == Arg(1) && node.arg(0).index() < i)
-		{
-			int target_index = alias[node.arg(0).index()];
-			auto target_node = compute_graph[perm[target_index]];
-			if(!target_node.has_sparse_attr() && node.has_sparse_attr())
-				target_node.sparse_attr() = node.sparse_attr();
-			alias.push_back(target_index);
-		}
-		else
-		{
-			alias.push_back(GetSize(perm));
-			perm.push_back(i);
-		}
-	}
-	compute_graph.permute(perm, alias);
-}
-
-void SmtlibModule::write(std::ostream &stream)
-{
-	SmtlibWriter f(stream);
-
-	idict<std::string> node_names;
-	SmtlibScope locals;
-	int paren_count = 0;
-
-	input_struct.print(f);
-	output_struct.print(f);
-	state_struct.print(f);
-
-	f << "(declare-datatypes ((Pair 2)) ((par (X Y) ((pair (first X) (second Y))))))\n";
-	f.printf("(define-fun %s_step ((inputs %s_inputs) (current_state %s_state)) (Pair %s_outputs %s_state)\n",
-		name.c_str(), name.c_str(), name.c_str(), name.c_str(), name.c_str());
-
-	for (int i = 0; i < compute_graph.size(); ++i)
-	{
-		auto ref = compute_graph[i];
-		std::string name;
-		if(ref.has_sparse_attr())
-			name = locals.insert(ref.sparse_attr());
-		else
-			name = locals.insert("\\n" + std::to_string(i));
-		node_names(name);
-		vector<SExpr> args;
-		args.reserve(ref.size());
-		for (int i = 0, end = ref.size(); i != end; ++i)
-			args.push_back(node_names[ref.arg(i).index()]);
-		f << "  (let " << SExpr{{SExpr{name, ref.function().expr.subst_args(args)}}} << "\n";
-		paren_count++;
-	}
-	dict<IdString, SExpr> outputs;
-	for(auto &a: compute_graph.keys())
-		outputs.insert({a.first, node_names[a.second]});
-	f.printf("    (pair \n");
-	output_struct.print_value(f, outputs, 6);
-	state_struct.print_value(f, outputs, 6);
-	f.printf("    )\n");
-	while(paren_count > 0){
-		int n = min(paren_count, 80);
-		f << "  " << std::string(n, ')') << "\n";
-		paren_count -= n;
-	}
-	f.printf(")\n");
-}
-
-struct FunctionalSmtlibBackend : public Backend
-{
-	FunctionalSmtlibBackend() : Backend("functional_smtlib", "convert design to SMTLIB using the functional backend") {}
-
-    void help() override
-	{
-		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-		log("\n");
-    }
+  void execute(std::ostream*& f, std::string filename, std::vector<std::string> args, RTLIL::Design* design) override {
+    log_header(design, "Executing Functional SMT Backend.\n");
+
+    size_t argidx = 1;
+    extra_args(f, filename, args, argidx, design);
 
-	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
-	{
-        log_header(design, "Executing Functional SMTLIB backend.\n");
-
-		size_t argidx = 1;
-		extra_args(f, filename, args, argidx, design);
-
-		for (auto module : design->selected_modules()) {
-            log("Dumping module `%s'.\n", module->name.c_str());
-			SmtlibModule smt(RTLIL::unescape_id(module->name));
-			smt.calculate_compute_graph(module);
-			smt.write(*f);
-		}
-	}
-} FunctionalSmtlibBackend;
+    for (auto module : design->selected_modules()) {
+      log("Processing module `%s`.\n", module->name.c_str());
+      auto ir = FunctionalIR::from_module(module);
+      SmtModule smt(RTLIL::unescape_id(module->name), ir);
+      smt.write(*f);
+    }
+  }
+} FunctionalSmtBackend;
 
 PRIVATE_NAMESPACE_END

From 54225b5c4252778dc39ad0ef912a6ebaa7d99853 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Fri, 21 Jun 2024 12:59:45 +0200
Subject: [PATCH 377/499] Add test for SMT backend. Tests if SMT is valid and
 compares simulation with yosys sim

---
 tests/functional/single_cells/run-test_smt.sh | 91 +++++++++++++++++++
 1 file changed, 91 insertions(+)
 create mode 100755 tests/functional/single_cells/run-test_smt.sh

diff --git a/tests/functional/single_cells/run-test_smt.sh b/tests/functional/single_cells/run-test_smt.sh
new file mode 100755
index 00000000000..42e1a7c4b65
--- /dev/null
+++ b/tests/functional/single_cells/run-test_smt.sh
@@ -0,0 +1,91 @@
+#!/bin/bash
+
+# Initialize an array to store the names of failing RTLIL files and their failure types
+declare -A failing_files
+# Initialize an array to store the names of successful RTLIL files
+declare -A successful_files
+
+# Function to run the test on a given RTLIL file
+run_test() {
+    # Define the common variable for the relative path
+    BASE_PATH="../../../"
+
+    local rtlil_file=$1
+
+    # Extract the base name without extension
+    local base_name=$(basename "$rtlil_file" .il)
+
+    # Run yosys to process each RTLIL file
+    if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; write_functional_smt2 ${base_name}.smt2"; then
+        echo "Yosys processed $rtlil_file successfully."
+	# Check that the smt file generated is valid
+        # Execute the Python script to create a VCD file from the SMT2 file
+	if z3 "${base_name}.smt2"; then
+            echo "SMT file ${base_name}.smt2 is valid ."
+
+            if python3 using_smtio.py "${base_name}.smt2"; then
+		echo "Python script generated VCD file for $rtlil_file successfully."
+
+		# Check if VCD file was generated successfully
+		if [ -f "${base_name}.smt2.vcd" ]; then
+                    echo "VCD file ${base_name}.vcd generated successfully by Python."
+
+                    # Run yosys simulation to generate a reference VCD file
+                    if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys.vcd -r ${base_name}.smt2.vcd -scope gold -timescale 1us"; then
+			echo "Yosys simulation for $rtlil_file completed successfully."
+			successful_files["$rtlil_file"]="Success"
+                    else
+			echo "Yosys simulation failed for $rtlil_file."
+			failing_files["$rtlil_file"]="Yosys simulation failure"
+                    fi
+		else
+		    
+                    echo "Failed to generate VCD file (${base_name}.vcd) for $rtlil_file. "
+                    failing_files["$rtlil_file"]="VCD generation failure"
+		fi
+            else
+		echo "Failed to run Python script for $rtlil_file."
+		failing_files["$rtlil_file"]="Python script failure"
+	    fi
+	else
+	    echo "SMT file for $rtlil_file is invalid"
+	    failing_files["$rtlil_file"]="Invalid SMT"
+	fi
+    else
+        echo "Yosys failed to process $rtlil_file."
+        failing_files["$rtlil_file"]="Yosys failure"
+    fi
+}
+
+# Main function to run all tests
+run_all_tests() {
+    # Loop through all RTLIL files in the rtlil directory
+    for rtlil_file in rtlil/*.il; do
+        run_test "$rtlil_file"
+    done
+
+    # Check if the array of failing files is empty
+    if [ ${#failing_files[@]} -eq 0 ]; then
+        echo "All files passed."
+        echo "The following files passed:"
+        for file in "${!successful_files[@]}"; do
+            echo "$file"
+        done
+        return 0
+    else
+        echo "The following files failed:"
+        for file in "${!failing_files[@]}"]; do
+    echo "$file: ${failing_files[$file]}"
+done
+echo "The following files passed:"
+for file in "${!successful_files[@]}"]; do
+					 echo "$file"
+				     done
+				      return 1
+				     fi
+				      }
+
+				       # If the script is being sourced, do not execute the tests
+				       if [[ "${BASH_SOURCE[0]}" == "${0}" ]]; then
+					   run_all_tests
+				       fi

From c6e112686ca93403847a144ded8eefceef674c42 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Sun, 23 Jun 2024 22:13:31 +0200
Subject: [PATCH 378/499] Remove unused includes

---
 backends/functional/smtlib.cc | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index a24ab84017f..65541d8d8e9 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -19,11 +19,6 @@
 
 #include "kernel/yosys.h"
 #include "kernel/functionalir.h"
-#include <cassert>
-#include <sstream>
-#include <vector>
-#include <string>
-#include <unordered_map>
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN

From 547c5466ecc74d593793ba30dde20fc941170a89 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Mon, 24 Jun 2024 02:40:32 +0200
Subject: [PATCH 379/499] Ignore smt2 files, generated by the execution of the
 tests

---
 tests/functional/.gitignore | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/tests/functional/.gitignore b/tests/functional/.gitignore
index 543226b49dc..8b20fbedf55 100644
--- a/tests/functional/.gitignore
+++ b/tests/functional/.gitignore
@@ -1,4 +1,5 @@
 my_module_cxxrtl.cc
 my_module_functional_cxx.cc
 vcd_harness
-*.vcd
\ No newline at end of file
+*.vcd
+*.smt2
\ No newline at end of file

From 71aaa1c80dcf1ac8c5a9836025d4859a60fe9bd7 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Mon, 24 Jun 2024 03:05:44 +0200
Subject: [PATCH 380/499] Consolidate tests scripts into one

---
 tests/functional/single_cells/run-test.sh     | 116 +++++++++++++-----
 tests/functional/single_cells/run-test_smt.sh |  91 --------------
 2 files changed, 87 insertions(+), 120 deletions(-)
 delete mode 100755 tests/functional/single_cells/run-test_smt.sh

diff --git a/tests/functional/single_cells/run-test.sh b/tests/functional/single_cells/run-test.sh
index 67cdf4a11c4..fd1b178e45a 100755
--- a/tests/functional/single_cells/run-test.sh
+++ b/tests/functional/single_cells/run-test.sh
@@ -1,80 +1,138 @@
 #!/bin/bash
 
-# Initialize an array to store the names of failing RTLIL files and their failure types
-declare -A failing_files
-# Initialize an array to store the names of successful RTLIL files
-declare -A successful_files
+declare -A cxx_failing_files
+declare -A smt_failing_files
+declare -A cxx_successful_files
+declare -A smt_successful_files
 
-# Function to run the test on a given RTLIL file
-run_test() {
-    # Define the common variable for the relative path
+run_cxx_test() {
     BASE_PATH="../../../"
 
     local rtlil_file=$1
 
-    # Extract the base name without extension
     local base_name=$(basename "$rtlil_file" .v)
     
-    # Run yosys to process each RTLIL file
     if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; write_functional_cxx my_module_functional_cxx.cc"; then
         echo "Yosys processed $rtlil_file successfully."
         
-        # Compile the generated C++ files with vcd_harness.cpp
         if ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cc -I ${BASE_PATH}backends/functional/cxx_runtime/ -std=c++17 -o vcd_harness; then
             echo "Compilation successful."
-            # Generate VCD files with base_name
             if ./vcd_harness ${base_name}_functional_cxx.vcd; then
 		
-		# Run yosys to process each RTLIL file
 		if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -r ${base_name}_functional_cxx.vcd -scope gold -vcd ${base_name}_yosys_sim.vcd -timescale 1us -sim-gold"; then
 		    echo "Yosys sim $rtlil_file successfully."
-		    successful_files["$rtlil_file"]="Success"
+		    cxx_successful_files["$rtlil_file"]="Success"
 		else
 		    ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys_sim.vcd -r ${base_name}_functional_cxx.vcd -scope gold -timescale 1us"
 		    echo "Yosys simulation of $rtlil_file failed. There is a discrepancy with functional cxx"
-		    failing_files["$rtlil_file"]="Yosys sim failure"
+		    cxx_failing_files["$rtlil_file"]="Yosys sim failure"
 		fi
 		
             else
 		echo "Failed to generate VCD files for $rtlil_file."
-		failing_files["$rtlil_file"]="VCD generation failure"
+		cxx_failing_files["$rtlil_file"]="VCD generation failure"
             fi
 	else
 	    echo "Failed to compile harness for $rtlil_file."
-	    failing_files["$rtlil_file"]="Compilation failure"
+	    cxx_failing_files["$rtlil_file"]="Compilation failure"
 	fi
 	else
             echo "Yosys failed to process $rtlil_file."
-            failing_files["$rtlil_file"]="Yosys failure"
+            cxx_failing_files["$rtlil_file"]="Yosys failure"
 	fi
 }
 
-# Main function to run all tests
+run_smt_test() {
+    BASE_PATH="../../../"
+
+    local rtlil_file=$1
+
+    local base_name=$(basename "$rtlil_file" .il)
+
+    if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; write_functional_smt2 ${base_name}.smt2"; then
+        echo "Yosys processed $rtlil_file successfully."
+	# TODO: which SMT solver should be run?
+	if z3 "${base_name}.smt2"; then
+            echo "SMT file ${base_name}.smt2 is valid ."
+
+            if python3 using_smtio.py "${base_name}.smt2"; then
+		echo "Python script generated VCD file for $rtlil_file successfully."
+
+		if [ -f "${base_name}.smt2.vcd" ]; then
+                    echo "VCD file ${base_name}.vcd generated successfully by Python."
+
+                    if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys.vcd -r ${base_name}.smt2.vcd -scope gold -timescale 1us"; then
+			echo "Yosys simulation for $rtlil_file completed successfully."
+			smt_successful_files["$rtlil_file"]="Success"
+                    else
+			echo "Yosys simulation failed for $rtlil_file."
+			smt_failing_files["$rtlil_file"]="Yosys simulation failure"
+                    fi
+		else
+		    
+                    echo "Failed to generate VCD file (${base_name}.vcd) for $rtlil_file. "
+                    smt_failing_files["$rtlil_file"]="VCD generation failure"
+		fi
+            else
+		echo "Failed to run Python script for $rtlil_file."
+		smt_failing_files["$rtlil_file"]="Python script failure"
+	    fi
+	else
+	    echo "SMT file for $rtlil_file is invalid"
+	    smt_failing_files["$rtlil_file"]="Invalid SMT"
+	fi
+    else
+        echo "Yosys failed to process $rtlil_file."
+        smt_failing_files["$rtlil_file"]="Yosys failure"
+    fi
+}
+
+
 run_all_tests() {
-    # Loop through all RTLIL files in the rtlil directory
+    return_code=0
     for rtlil_file in rtlil/*.il; do
-        run_test "$rtlil_file"
+        run_cxx_test "$rtlil_file"
+	run_smt_test "$rtlil_file"
     done
-
-    # Check if the array of failing files is empty
-    if [ ${#failing_files[@]} -eq 0 ]; then
+    
+    echo "C++ tests results:"
+    if [ ${#cxx_failing_files[@]} -eq 0 ]; then
+        echo "All files passed."
+	echo "The following files passed:"
+        for file in "${!cxx_successful_files[@]}"; do
+            echo "$file"
+        done
+    else
+        echo "The following files failed:"
+        for file in "${!cxx_failing_files[@]}"; do
+            echo "$file: ${cxx_failing_files[$file]}"
+        done
+	echo "The following files passed:"
+        for file in "${!cxx_successful_files[@]}"; do
+            echo "$file"
+        done
+	return_code=1
+    fi
+    
+    echo "SMT tests results:"
+    if [ ${#smt_failing_files[@]} -eq 0 ]; then
         echo "All files passed."
 	echo "The following files passed:"
-        for file in "${!successful_files[@]}"; do
+        for file in "${!smt_successful_files[@]}"; do
             echo "$file"
         done
-        return 0
     else
         echo "The following files failed:"
-        for file in "${!failing_files[@]}"; do
-            echo "$file: ${failing_files[$file]}"
+        for file in "${!smt_failing_files[@]}"; do
+            echo "$file: ${smt_failing_files[$file]}"
         done
 	echo "The following files passed:"
-        for file in "${!successful_files[@]}"; do
+        for file in "${!smt_successful_files[@]}"; do
             echo "$file"
         done
-        return 1
+	return_code=1
     fi
+    return $return_code
 }
 
 # If the script is being sourced, do not execute the tests
diff --git a/tests/functional/single_cells/run-test_smt.sh b/tests/functional/single_cells/run-test_smt.sh
deleted file mode 100755
index 42e1a7c4b65..00000000000
--- a/tests/functional/single_cells/run-test_smt.sh
+++ /dev/null
@@ -1,91 +0,0 @@
-#!/bin/bash
-
-# Initialize an array to store the names of failing RTLIL files and their failure types
-declare -A failing_files
-# Initialize an array to store the names of successful RTLIL files
-declare -A successful_files
-
-# Function to run the test on a given RTLIL file
-run_test() {
-    # Define the common variable for the relative path
-    BASE_PATH="../../../"
-
-    local rtlil_file=$1
-
-    # Extract the base name without extension
-    local base_name=$(basename "$rtlil_file" .il)
-
-    # Run yosys to process each RTLIL file
-    if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; write_functional_smt2 ${base_name}.smt2"; then
-        echo "Yosys processed $rtlil_file successfully."
-	# Check that the smt file generated is valid
-        # Execute the Python script to create a VCD file from the SMT2 file
-	if z3 "${base_name}.smt2"; then
-            echo "SMT file ${base_name}.smt2 is valid ."
-
-            if python3 using_smtio.py "${base_name}.smt2"; then
-		echo "Python script generated VCD file for $rtlil_file successfully."
-
-		# Check if VCD file was generated successfully
-		if [ -f "${base_name}.smt2.vcd" ]; then
-                    echo "VCD file ${base_name}.vcd generated successfully by Python."
-
-                    # Run yosys simulation to generate a reference VCD file
-                    if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys.vcd -r ${base_name}.smt2.vcd -scope gold -timescale 1us"; then
-			echo "Yosys simulation for $rtlil_file completed successfully."
-			successful_files["$rtlil_file"]="Success"
-                    else
-			echo "Yosys simulation failed for $rtlil_file."
-			failing_files["$rtlil_file"]="Yosys simulation failure"
-                    fi
-		else
-		    
-                    echo "Failed to generate VCD file (${base_name}.vcd) for $rtlil_file. "
-                    failing_files["$rtlil_file"]="VCD generation failure"
-		fi
-            else
-		echo "Failed to run Python script for $rtlil_file."
-		failing_files["$rtlil_file"]="Python script failure"
-	    fi
-	else
-	    echo "SMT file for $rtlil_file is invalid"
-	    failing_files["$rtlil_file"]="Invalid SMT"
-	fi
-    else
-        echo "Yosys failed to process $rtlil_file."
-        failing_files["$rtlil_file"]="Yosys failure"
-    fi
-}
-
-# Main function to run all tests
-run_all_tests() {
-    # Loop through all RTLIL files in the rtlil directory
-    for rtlil_file in rtlil/*.il; do
-        run_test "$rtlil_file"
-    done
-
-    # Check if the array of failing files is empty
-    if [ ${#failing_files[@]} -eq 0 ]; then
-        echo "All files passed."
-        echo "The following files passed:"
-        for file in "${!successful_files[@]}"; do
-            echo "$file"
-        done
-        return 0
-    else
-        echo "The following files failed:"
-        for file in "${!failing_files[@]}"]; do
-    echo "$file: ${failing_files[$file]}"
-done
-echo "The following files passed:"
-for file in "${!successful_files[@]}"]; do
-					 echo "$file"
-				     done
-				      return 1
-				     fi
-				      }
-
-				       # If the script is being sourced, do not execute the tests
-				       if [[ "${BASH_SOURCE[0]}" == "${0}" ]]; then
-					   run_all_tests
-				       fi

From b98210d8ac312497bd3523f5b5cc81f602487226 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Wed, 26 Jun 2024 19:13:53 +0200
Subject: [PATCH 381/499] Valid SMT is emitted, improved test script

---
 backends/functional/smtlib.cc             | 59 +++++++++++++-------
 tests/functional/single_cells/run-test.sh | 67 ++++++++++++++++-------
 2 files changed, 86 insertions(+), 40 deletions(-)

diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index 65541d8d8e9..671b3a76312 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -108,11 +108,11 @@ struct SmtPrintVisitor {
   }
 
   std::string zero_extend(Node, Node a, int, int out_width) {
-    return format("((_ zero_extend %1) %0)", np(a), out_width);
+    return format("((_ zero_extend %1) %0)", np(a), out_width - a.width());
   }
 
   std::string sign_extend(Node, Node a, int, int out_width) {
-    return format("((_ sign_extend %1) %0)", np(a), out_width);
+    return format("((_ sign_extend %1) %0)", np(a), out_width - a.width());
   }
 
   std::string concat(Node, Node a, int, Node b, int) {
@@ -228,6 +228,7 @@ struct SmtPrintVisitor {
     return format("#b%0", std::string(width, '0'));
   }
 };
+
 struct SmtModule {
   std::string name;
   SmtScope scope;
@@ -236,11 +237,24 @@ struct SmtModule {
   SmtModule(const std::string& module_name, FunctionalIR ir) 
     : name(module_name), ir(std::move(ir)) {}
 
+  std::string replaceCharacters(const std::string& input) {
+    std::string result = input;
+    std::replace(result.begin(), result.end(), '$', '_');  // Replace $ with _
+    
+    // Since \ is an escape character, we use a loop to replace it
+    size_t pos = 0;
+    while ((pos = result.find('\\', pos)) != std::string::npos) {
+        result.replace(pos, 1, "_");
+        pos += 1;  // Move past the replaced character
+    }
+    
+    return result;
+  }
+  
   void write(std::ostream& out) {
     SmtWriter writer(out);
-        
+    
     writer.print("(declare-fun %s () Bool)\n", name.c_str());
-
     writer.print("(declare-datatypes () ((Inputs (mk_inputs");
     for (const auto& input : ir.inputs()) {
       std::string input_name = scope[input.first];
@@ -258,7 +272,6 @@ struct SmtModule {
     writer.print("(declare-fun state () (_ BitVec 1))\n");
 
     writer.print("(define-fun %s_step ((state (_ BitVec 1)) (inputs Inputs)) Outputs\n", name.c_str());
-
     writer.print("  (let (\n");
     for (const auto& input : ir.inputs()) {
       std::string input_name = scope[input.first];
@@ -268,35 +281,41 @@ struct SmtModule {
 
     auto node_to_string = [&](FunctionalIR::Node n) { return scope[n.name()]; };
     SmtPrintVisitor<decltype(node_to_string)> visitor(node_to_string, scope);
-    writer.print("    (let (\n");
+
+    std::string nested_lets;
     for (auto it = ir.begin(); it != ir.end(); ++it) {
       const FunctionalIR::Node& node = *it;
 
-      if (ir.inputs().count(node.name()) > 0) {
-        continue;
-      }
+      if (ir.inputs().count(node.name()) > 0) continue;
       
-      std::string node_name = scope[node.name()];
+      std::string node_name = replaceCharacters(scope[node.name()]);
       std::string node_expr = node.visit(visitor);
-      writer.print("      (%s %s)\n", node_name.c_str(), node_expr.c_str());
+      
+      nested_lets += "(let (\n      (" + node_name + " " + node_expr + "))\n";
     }
-    writer.print("    )\n");
 
-    writer.print("      (let (\n");
+    nested_lets += "          (let (\n";
     for (const auto& output : ir.outputs()) {
       std::string output_name = scope[output.first];
-      // writer.print("        (%s %s)\n", output_name.c_str(), scope[output_name].c_str());
+      const std::string output_assignment = ir.get_output_node(output.first).name().c_str();
+      nested_lets += "            (" + output_name + " " + replaceCharacters(output_assignment).substr(1) + ")\n";
     }
-    writer.print("      )\n");
+    nested_lets += "          )\n";
+    nested_lets += "            (mk_outputs\n";
 
-    writer.print("        (mk_outputs\n");
     for (const auto& output : ir.outputs()) {
       std::string output_name = scope[output.first];
-      writer.print("          %s\n", output_name.c_str());
+      nested_lets += "              " + output_name + "\n";
     }
-    writer.print("        )\n");
-    writer.print("      )\n");
-    writer.print("    )\n");
+    nested_lets += "            )\n";
+    nested_lets += "          )\n";
+
+    // Close the nested lets
+    for (size_t i = 0; i < ir.size() - ir.inputs().size(); ++i) {
+      nested_lets += "    )\n";
+    }
+
+    writer.print("%s", nested_lets.c_str());
     writer.print("  )\n");
     writer.print(")\n");
   }
diff --git a/tests/functional/single_cells/run-test.sh b/tests/functional/single_cells/run-test.sh
index fd1b178e45a..473c7faea51 100755
--- a/tests/functional/single_cells/run-test.sh
+++ b/tests/functional/single_cells/run-test.sh
@@ -54,29 +54,29 @@ run_smt_test() {
 	# TODO: which SMT solver should be run?
 	if z3 "${base_name}.smt2"; then
             echo "SMT file ${base_name}.smt2 is valid ."
+	    smt_successful_files["$rtlil_file"]="Success"
+            # if python3 using_smtio.py "${base_name}.smt2"; then
+	    # 	echo "Python script generated VCD file for $rtlil_file successfully."
 
-            if python3 using_smtio.py "${base_name}.smt2"; then
-		echo "Python script generated VCD file for $rtlil_file successfully."
+	    # 	if [ -f "${base_name}.smt2.vcd" ]; then
+            #         echo "VCD file ${base_name}.vcd generated successfully by Python."
 
-		if [ -f "${base_name}.smt2.vcd" ]; then
-                    echo "VCD file ${base_name}.vcd generated successfully by Python."
-
-                    if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys.vcd -r ${base_name}.smt2.vcd -scope gold -timescale 1us"; then
-			echo "Yosys simulation for $rtlil_file completed successfully."
-			smt_successful_files["$rtlil_file"]="Success"
-                    else
-			echo "Yosys simulation failed for $rtlil_file."
-			smt_failing_files["$rtlil_file"]="Yosys simulation failure"
-                    fi
-		else
+            #         if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys.vcd -r ${base_name}.smt2.vcd -scope gold -timescale 1us"; then
+	    # 		echo "Yosys simulation for $rtlil_file completed successfully."
+	    # 		smt_successful_files["$rtlil_file"]="Success"
+            #         else
+	    # 		echo "Yosys simulation failed for $rtlil_file."
+	    # 		smt_failing_files["$rtlil_file"]="Yosys simulation failure"
+            #         fi
+	    # 	else
 		    
-                    echo "Failed to generate VCD file (${base_name}.vcd) for $rtlil_file. "
-                    smt_failing_files["$rtlil_file"]="VCD generation failure"
-		fi
-            else
-		echo "Failed to run Python script for $rtlil_file."
-		smt_failing_files["$rtlil_file"]="Python script failure"
-	    fi
+            #         echo "Failed to generate VCD file (${base_name}.vcd) for $rtlil_file. "
+            #         smt_failing_files["$rtlil_file"]="VCD generation failure"
+	    # 	fi
+            # else
+	    # 	echo "Failed to run Python script for $rtlil_file."
+	    # 	smt_failing_files["$rtlil_file"]="Python script failure"
+	    # fi
 	else
 	    echo "SMT file for $rtlil_file is invalid"
 	    smt_failing_files["$rtlil_file"]="Invalid SMT"
@@ -135,6 +135,33 @@ run_all_tests() {
     return $return_code
 }
 
+run_smt_tests() {
+    return_code=0
+    for rtlil_file in rtlil/*.il; do
+        run_smt_test "$rtlil_file"
+    done
+
+    echo "SMT tests results:"
+    if [ ${#smt_failing_files[@]} -eq 0 ]; then
+        echo "All files passed."
+        echo "The following files passed:"
+        for file in "${!smt_successful_files[@]}"; do
+            echo "$file"
+        done
+    else
+        echo "The following files failed:"
+        for file in "${!smt_failing_files[@]}"; do
+            echo "$file: ${smt_failing_files[$file]}"
+        done
+        echo "The following files passed:"
+        for file in "${!smt_successful_files[@]}"; do
+            echo "$file"
+        done
+        return_code=1
+    fi
+    return $return_code
+}
+
 # If the script is being sourced, do not execute the tests
 if [[ "${BASH_SOURCE[0]}" == "${0}" ]]; then
     run_all_tests

From 94ddbc957727b6a71064a608a869405d49eb9dcb Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Wed, 26 Jun 2024 19:45:54 +0200
Subject: [PATCH 382/499] Fix reduce_or

---
 backends/functional/smtlib.cc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index 671b3a76312..2ece98d8999 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -152,7 +152,10 @@ struct SmtPrintVisitor {
   }
 
   std::string reduce_or(Node, Node a, int) {
-    return format("(distinct %0 #b0)", np(a));
+    std::stringstream ss;
+    // We use ite to set the result to bit vector, to ensure appropriate type
+    ss << "(ite (= " << np(a) << " #b" << std::string(a.width(), '0') << ") #b0 #b1)";
+    return ss.str();
   }
 
   std::string reduce_xor(Node, Node a, int) {

From 4109fcedcff1161b2c9a67d6651fdf416cb22e47 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Wed, 26 Jun 2024 20:56:29 +0200
Subject: [PATCH 383/499] clang-format smtlib.cc

---
 backends/functional/smtlib.cc | 554 +++++++++++++++-------------------
 1 file changed, 250 insertions(+), 304 deletions(-)

diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index 2ece98d8999..49dd5cf0d21 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -17,333 +17,279 @@
  *
  */
 
-#include "kernel/yosys.h"
 #include "kernel/functionalir.h"
+#include "kernel/yosys.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
 struct SmtScope {
-  pool<std::string> used_names;
-  dict<IdString, std::string> name_map;
-
-  SmtScope() {}
-    
-  void reserve(const std::string& name) {
-    used_names.insert(name);
-  }
-
-  std::string insert(IdString id) {
-    std::string name = RTLIL::unescape_id(id);
-    if (used_names.count(name) == 0) {
-      used_names.insert(name);
-      name_map[id] = name;
-      return name;
-    }
-    for (int idx = 0;; ++idx) {
-      std::string new_name = name + "_" + std::to_string(idx);
-      if (used_names.count(new_name) == 0) {
-	used_names.insert(new_name);
-	name_map[id] = new_name;
-	return new_name;
-      }
-    }
-  }
-
-  std::string operator[](IdString id) {
-    if (name_map.count(id)) {
-      return name_map[id];
-    } else {
-      return insert(id);
-    }
-  }
+	pool<std::string> used_names;
+	dict<IdString, std::string> name_map;
+
+	SmtScope() {}
+
+	void reserve(const std::string &name) { used_names.insert(name); }
+
+	std::string insert(IdString id)
+	{
+		std::string name = RTLIL::unescape_id(id);
+		if (used_names.count(name) == 0) {
+			used_names.insert(name);
+			name_map[id] = name;
+			return name;
+		}
+		for (int idx = 0;; ++idx) {
+			std::string new_name = name + "_" + std::to_string(idx);
+			if (used_names.count(new_name) == 0) {
+				used_names.insert(new_name);
+				name_map[id] = new_name;
+				return new_name;
+			}
+		}
+	}
+
+	std::string operator[](IdString id)
+	{
+		if (name_map.count(id)) {
+			return name_map[id];
+		} else {
+			return insert(id);
+		}
+	}
 };
 
 struct SmtWriter {
-  std::ostream& stream;
+	std::ostream &stream;
 
-  SmtWriter(std::ostream& out) : stream(out) {}
+	SmtWriter(std::ostream &out) : stream(out) {}
 
-  void print(const char* fmt, ...) {
-    va_list args;
-    va_start(args, fmt);
-    stream << vstringf(fmt, args);
-    va_end(args);
-  }
+	void print(const char *fmt, ...)
+	{
+		va_list args;
+		va_start(args, fmt);
+		stream << vstringf(fmt, args);
+		va_end(args);
+	}
 };
 
-template<class NodeNames>
-struct SmtPrintVisitor {
-  using Node = FunctionalIR::Node;
-  NodeNames np;
-  SmtScope &scope;
-
-  SmtPrintVisitor(NodeNames np, SmtScope &scope)
-    : np(np), scope(scope) {}
-
-  template<class T>
-  std::string arg_to_string(T n) { return std::to_string(n); }
-
-  std::string arg_to_string(std::string n) { return n; }
-
-  std::string arg_to_string(Node n) { return np(n); }
-
-  template<typename... Args>
-  std::string format(std::string fmt, Args&&... args) {
-    std::vector<std::string> arg_strings = { arg_to_string(std::forward<Args>(args))... };
-    for (size_t i = 0; i < arg_strings.size(); ++i) {
-      std::string placeholder = "%" + std::to_string(i);
-      size_t pos = 0;
-      while ((pos = fmt.find(placeholder, pos)) != std::string::npos) {
-	fmt.replace(pos, placeholder.length(), arg_strings[i]);
-	pos += arg_strings[i].length();
-      }
-    }
-    return fmt;
-  }
-  std::string buf(Node, Node n) { return np(n); }
-
-  std::string slice(Node, Node a, int, int offset, int out_width) {
-    return format("(_ extract %1 %2 %0)", np(a), offset, offset + out_width - 1);
-  }
-
-  std::string zero_extend(Node, Node a, int, int out_width) {
-    return format("((_ zero_extend %1) %0)", np(a), out_width - a.width());
-  }
-
-  std::string sign_extend(Node, Node a, int, int out_width) {
-    return format("((_ sign_extend %1) %0)", np(a), out_width - a.width());
-  }
-
-  std::string concat(Node, Node a, int, Node b, int) {
-    return format("(concat %0 %1)", np(a), np(b));
-  }
-
-  std::string add(Node, Node a, Node b, int) {
-    return format("(bvadd %0 %1)", np(a), np(b));
-  }
-
-  std::string sub(Node, Node a, Node b, int) {
-    return format("(bvsub %0 %1)", np(a), np(b));
-  }
-
-  std::string bitwise_and(Node, Node a, Node b, int) {
-    return format("(bvand %0 %1)", np(a), np(b));
-  }
-
-  std::string bitwise_or(Node, Node a, Node b, int) {
-    return format("(bvor %0 %1)", np(a), np(b));
-  }
-
-  std::string bitwise_xor(Node, Node a, Node b, int) {
-    return format("(bvxor %0 %1)", np(a), np(b));
-  }
-
-  std::string bitwise_not(Node, Node a, int) {
-    return format("(bvnot %0)", np(a));
-  }
-
-  std::string unary_minus(Node, Node a, int) {
-    return format("(bvneg %0)", np(a));
-  }
-
-  std::string reduce_and(Node, Node a, int) {
-    return format("(= %0 #b1)", np(a));
-  }
-
-  std::string reduce_or(Node, Node a, int) {
-    std::stringstream ss;
-    // We use ite to set the result to bit vector, to ensure appropriate type
-    ss << "(ite (= " << np(a) << " #b" << std::string(a.width(), '0') << ") #b0 #b1)";
-    return ss.str();
-  }
-
-  std::string reduce_xor(Node, Node a, int) {
-    return format("(bvxor_reduce %0)", np(a));
-  }
-
-  std::string equal(Node, Node a, Node b, int) {
-    return format("(= %0 %1)", np(a), np(b));
-  }
-
-  std::string not_equal(Node, Node a, Node b, int) {
-    return format("(distinct %0 %1)", np(a), np(b));
-  }
-
-  std::string signed_greater_than(Node, Node a, Node b, int) {
-    return format("(bvsgt %0 %1)", np(a), np(b));
-  }
-
-  std::string signed_greater_equal(Node, Node a, Node b, int) {
-    return format("(bvsge %0 %1)", np(a), np(b));
-  }
-
-  std::string unsigned_greater_than(Node, Node a, Node b, int) {
-    return format("(bvugt %0 %1)", np(a), np(b));
-  }
-
-  std::string unsigned_greater_equal(Node, Node a, Node b, int) {
-    return format("(bvuge %0 %1)", np(a), np(b));
-  }
-
-  std::string logical_shift_left(Node, Node a, Node b, int, int) {
-    return format("(bvshl %0 %1)", np(a), np(b));
-  }
-
-  std::string logical_shift_right(Node, Node a, Node b, int, int) {
-    return format("(bvlshr %0 %1)", np(a), np(b));
-  }
-
-  std::string arithmetic_shift_right(Node, Node a, Node b, int, int) {
-    return format("(bvashr %0 %1)", np(a), np(b));
-  }
-
-  std::string mux(Node, Node a, Node b, Node s, int) {
-    return format("(ite %2 %0 %1)", np(a), np(b), np(s));
-  }
-
-  std::string pmux(Node, Node a, Node b, Node s, int, int) {
-    // Assume s is a bit vector, combine a and b based on the selection bits
-    return format("(pmux %0 %1 %2)", np(a), np(b), np(s));
-  }
-
-  std::string constant(Node, RTLIL::Const value) {
-    return format("#b%1", value.as_string());
-  }
-
-  std::string input(Node, IdString name) {
-    return format("%0", scope[name]);
-  }
-
-  std::string state(Node, IdString name) {
-    return format("%0", scope[name]);
-  }
-
-  std::string memory_read(Node, Node mem, Node addr, int, int) {
-    return format("(select %0 %1)", np(mem), np(addr));
-  }
-
-  std::string memory_write(Node, Node mem, Node addr, Node data, int, int) {
-    return format("(store %0 %1 %2)", np(mem), np(addr), np(data));
-  }
-
-  std::string undriven(Node, int width) {
-    return format("#b%0", std::string(width, '0'));
-  }
+template <class NodeNames> struct SmtPrintVisitor {
+	using Node = FunctionalIR::Node;
+	NodeNames np;
+	SmtScope &scope;
+
+	SmtPrintVisitor(NodeNames np, SmtScope &scope) : np(np), scope(scope) {}
+
+	template <class T> std::string arg_to_string(T n) { return std::to_string(n); }
+
+	std::string arg_to_string(std::string n) { return n; }
+
+	std::string arg_to_string(Node n) { return np(n); }
+
+	template <typename... Args> std::string format(std::string fmt, Args &&...args)
+	{
+		std::vector<std::string> arg_strings = {arg_to_string(std::forward<Args>(args))...};
+		for (size_t i = 0; i < arg_strings.size(); ++i) {
+			std::string placeholder = "%" + std::to_string(i);
+			size_t pos = 0;
+			while ((pos = fmt.find(placeholder, pos)) != std::string::npos) {
+				fmt.replace(pos, placeholder.length(), arg_strings[i]);
+				pos += arg_strings[i].length();
+			}
+		}
+		return fmt;
+	}
+	std::string buf(Node, Node n) { return np(n); }
+
+	std::string slice(Node, Node a, int, int offset, int out_width)
+	{
+		return format("(_ extract %1 %2 %0)", np(a), offset, offset + out_width - 1);
+	}
+
+	std::string zero_extend(Node, Node a, int, int out_width) { return format("((_ zero_extend %1) %0)", np(a), out_width - a.width()); }
+
+	std::string sign_extend(Node, Node a, int, int out_width) { return format("((_ sign_extend %1) %0)", np(a), out_width - a.width()); }
+
+	std::string concat(Node, Node a, int, Node b, int) { return format("(concat %0 %1)", np(a), np(b)); }
+
+	std::string add(Node, Node a, Node b, int) { return format("(bvadd %0 %1)", np(a), np(b)); }
+
+	std::string sub(Node, Node a, Node b, int) { return format("(bvsub %0 %1)", np(a), np(b)); }
+
+	std::string bitwise_and(Node, Node a, Node b, int) { return format("(bvand %0 %1)", np(a), np(b)); }
+
+	std::string bitwise_or(Node, Node a, Node b, int) { return format("(bvor %0 %1)", np(a), np(b)); }
+
+	std::string bitwise_xor(Node, Node a, Node b, int) { return format("(bvxor %0 %1)", np(a), np(b)); }
+
+	std::string bitwise_not(Node, Node a, int) { return format("(bvnot %0)", np(a)); }
+
+	std::string unary_minus(Node, Node a, int) { return format("(bvneg %0)", np(a)); }
+
+	std::string reduce_and(Node, Node a, int) { return format("(= %0 #b1)", np(a)); }
+
+	std::string reduce_or(Node, Node a, int)
+	{
+		std::stringstream ss;
+		// We use ite to set the result to bit vector, to ensure appropriate type
+		ss << "(ite (= " << np(a) << " #b" << std::string(a.width(), '0') << ") #b0 #b1)";
+		return ss.str();
+	}
+
+	std::string reduce_xor(Node, Node a, int) { return format("(bvxor_reduce %0)", np(a)); }
+
+	std::string equal(Node, Node a, Node b, int) { return format("(= %0 %1)", np(a), np(b)); }
+
+	std::string not_equal(Node, Node a, Node b, int) { return format("(distinct %0 %1)", np(a), np(b)); }
+
+	std::string signed_greater_than(Node, Node a, Node b, int) { return format("(bvsgt %0 %1)", np(a), np(b)); }
+
+	std::string signed_greater_equal(Node, Node a, Node b, int) { return format("(bvsge %0 %1)", np(a), np(b)); }
+
+	std::string unsigned_greater_than(Node, Node a, Node b, int) { return format("(bvugt %0 %1)", np(a), np(b)); }
+
+	std::string unsigned_greater_equal(Node, Node a, Node b, int) { return format("(bvuge %0 %1)", np(a), np(b)); }
+
+	std::string logical_shift_left(Node, Node a, Node b, int, int) { return format("(bvshl %0 %1)", np(a), np(b)); }
+
+	std::string logical_shift_right(Node, Node a, Node b, int, int) { return format("(bvlshr %0 %1)", np(a), np(b)); }
+
+	std::string arithmetic_shift_right(Node, Node a, Node b, int, int) { return format("(bvashr %0 %1)", np(a), np(b)); }
+
+	std::string mux(Node, Node a, Node b, Node s, int) { return format("(ite %2 %0 %1)", np(a), np(b), np(s)); }
+
+	std::string pmux(Node, Node a, Node b, Node s, int, int)
+	{
+		// Assume s is a bit vector, combine a and b based on the selection bits
+		return format("(pmux %0 %1 %2)", np(a), np(b), np(s));
+	}
+
+	std::string constant(Node, RTLIL::Const value) { return format("#b%1", value.as_string()); }
+
+	std::string input(Node, IdString name) { return format("%0", scope[name]); }
+
+	std::string state(Node, IdString name) { return format("%0", scope[name]); }
+
+	std::string memory_read(Node, Node mem, Node addr, int, int) { return format("(select %0 %1)", np(mem), np(addr)); }
+
+	std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { return format("(store %0 %1 %2)", np(mem), np(addr), np(data)); }
+
+	std::string undriven(Node, int width) { return format("#b%0", std::string(width, '0')); }
 };
 
 struct SmtModule {
-  std::string name;
-  SmtScope scope;
-  FunctionalIR ir;
-
-  SmtModule(const std::string& module_name, FunctionalIR ir) 
-    : name(module_name), ir(std::move(ir)) {}
-
-  std::string replaceCharacters(const std::string& input) {
-    std::string result = input;
-    std::replace(result.begin(), result.end(), '$', '_');  // Replace $ with _
-    
-    // Since \ is an escape character, we use a loop to replace it
-    size_t pos = 0;
-    while ((pos = result.find('\\', pos)) != std::string::npos) {
-        result.replace(pos, 1, "_");
-        pos += 1;  // Move past the replaced character
-    }
-    
-    return result;
-  }
-  
-  void write(std::ostream& out) {
-    SmtWriter writer(out);
-    
-    writer.print("(declare-fun %s () Bool)\n", name.c_str());
-    writer.print("(declare-datatypes () ((Inputs (mk_inputs");
-    for (const auto& input : ir.inputs()) {
-      std::string input_name = scope[input.first];
-      writer.print(" (%s (_ BitVec %d))", input_name.c_str(), input.second.width());
-    }
-    writer.print("))))\n");
-
-    writer.print("(declare-datatypes () ((Outputs (mk_outputs");
-    for (const auto& output : ir.outputs()) {
-      std::string output_name = scope[output.first];
-      writer.print(" (%s (_ BitVec %d))", output_name.c_str(), output.second.width());
-    }
-    writer.print("))))\n");
-
-    writer.print("(declare-fun state () (_ BitVec 1))\n");
-
-    writer.print("(define-fun %s_step ((state (_ BitVec 1)) (inputs Inputs)) Outputs\n", name.c_str());
-    writer.print("  (let (\n");
-    for (const auto& input : ir.inputs()) {
-      std::string input_name = scope[input.first];
-      writer.print("    (%s (%s inputs))\n", input_name.c_str(), input_name.c_str());
-    }
-    writer.print("  )\n");
-
-    auto node_to_string = [&](FunctionalIR::Node n) { return scope[n.name()]; };
-    SmtPrintVisitor<decltype(node_to_string)> visitor(node_to_string, scope);
-
-    std::string nested_lets;
-    for (auto it = ir.begin(); it != ir.end(); ++it) {
-      const FunctionalIR::Node& node = *it;
-
-      if (ir.inputs().count(node.name()) > 0) continue;
-      
-      std::string node_name = replaceCharacters(scope[node.name()]);
-      std::string node_expr = node.visit(visitor);
-      
-      nested_lets += "(let (\n      (" + node_name + " " + node_expr + "))\n";
-    }
-
-    nested_lets += "          (let (\n";
-    for (const auto& output : ir.outputs()) {
-      std::string output_name = scope[output.first];
-      const std::string output_assignment = ir.get_output_node(output.first).name().c_str();
-      nested_lets += "            (" + output_name + " " + replaceCharacters(output_assignment).substr(1) + ")\n";
-    }
-    nested_lets += "          )\n";
-    nested_lets += "            (mk_outputs\n";
-
-    for (const auto& output : ir.outputs()) {
-      std::string output_name = scope[output.first];
-      nested_lets += "              " + output_name + "\n";
-    }
-    nested_lets += "            )\n";
-    nested_lets += "          )\n";
-
-    // Close the nested lets
-    for (size_t i = 0; i < ir.size() - ir.inputs().size(); ++i) {
-      nested_lets += "    )\n";
-    }
-
-    writer.print("%s", nested_lets.c_str());
-    writer.print("  )\n");
-    writer.print(")\n");
-  }
+	std::string name;
+	SmtScope scope;
+	FunctionalIR ir;
+
+	SmtModule(const std::string &module_name, FunctionalIR ir) : name(module_name), ir(std::move(ir)) {}
+
+	std::string replaceCharacters(const std::string &input)
+	{
+		std::string result = input;
+		std::replace(result.begin(), result.end(), '$', '_'); // Replace $ with _
+
+		// Since \ is an escape character, we use a loop to replace it
+		size_t pos = 0;
+		while ((pos = result.find('\\', pos)) != std::string::npos) {
+			result.replace(pos, 1, "_");
+			pos += 1; // Move past the replaced character
+		}
+
+		return result;
+	}
+
+	void write(std::ostream &out)
+	{
+		SmtWriter writer(out);
+
+		writer.print("(declare-fun %s () Bool)\n", name.c_str());
+		writer.print("(declare-datatypes () ((Inputs (mk_inputs");
+		for (const auto &input : ir.inputs()) {
+			std::string input_name = scope[input.first];
+			writer.print(" (%s (_ BitVec %d))", input_name.c_str(), input.second.width());
+		}
+		writer.print("))))\n");
+
+		writer.print("(declare-datatypes () ((Outputs (mk_outputs");
+		for (const auto &output : ir.outputs()) {
+			std::string output_name = scope[output.first];
+			writer.print(" (%s (_ BitVec %d))", output_name.c_str(), output.second.width());
+		}
+		writer.print("))))\n");
+
+		writer.print("(declare-fun state () (_ BitVec 1))\n");
+
+		writer.print("(define-fun %s_step ((state (_ BitVec 1)) (inputs Inputs)) Outputs", name.c_str());
+		writer.print("  (let (");
+		for (const auto &input : ir.inputs()) {
+			std::string input_name = scope[input.first];
+			writer.print("    (%s (%s inputs))", input_name.c_str(), input_name.c_str());
+		}
+		writer.print("  )");
+
+		auto node_to_string = [&](FunctionalIR::Node n) { return scope[n.name()]; };
+		SmtPrintVisitor<decltype(node_to_string)> visitor(node_to_string, scope);
+
+		std::string nested_lets;
+		for (auto it = ir.begin(); it != ir.end(); ++it) {
+			const FunctionalIR::Node &node = *it;
+
+			if (ir.inputs().count(node.name()) > 0)
+				continue;
+
+			std::string node_name = replaceCharacters(scope[node.name()]);
+			std::string node_expr = node.visit(visitor);
+
+			nested_lets += "(let (      (" + node_name + " " + node_expr + "))";
+		}
+
+		nested_lets += "          (let (";
+		for (const auto &output : ir.outputs()) {
+			std::string output_name = scope[output.first];
+			const std::string output_assignment = ir.get_output_node(output.first).name().c_str();
+			nested_lets += "            (" + output_name + " " + replaceCharacters(output_assignment).substr(1) + ")";
+		}
+		nested_lets += "          )";
+		nested_lets += "            (mk_outputs";
+
+		for (const auto &output : ir.outputs()) {
+			std::string output_name = scope[output.first];
+			nested_lets += "              " + output_name;
+		}
+		nested_lets += "            )";
+		nested_lets += "          )";
+
+		// Close the nested lets
+		for (size_t i = 0; i < ir.size() - ir.inputs().size(); ++i) {
+			nested_lets += "    )";
+		}
+
+		writer.print("%s", nested_lets.c_str());
+		writer.print("  )");
+		writer.print(")\n");
+	}
 };
 
 struct FunctionalSmtBackend : public Backend {
-  FunctionalSmtBackend() : Backend("functional_smt2", "Generate SMT-LIB from Functional IR") {}
+	FunctionalSmtBackend() : Backend("functional_smt2", "Generate SMT-LIB from Functional IR") {}
 
-  void help() override {
-    log("\nFunctional SMT Backend.\n\n");
-  }
+	void help() override { log("\nFunctional SMT Backend.\n\n"); }
 
-  void execute(std::ostream*& f, std::string filename, std::vector<std::string> args, RTLIL::Design* design) override {
-    log_header(design, "Executing Functional SMT Backend.\n");
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		log_header(design, "Executing Functional SMT Backend.\n");
 
-    size_t argidx = 1;
-    extra_args(f, filename, args, argidx, design);
+		size_t argidx = 1;
+		extra_args(f, filename, args, argidx, design);
 
-    for (auto module : design->selected_modules()) {
-      log("Processing module `%s`.\n", module->name.c_str());
-      auto ir = FunctionalIR::from_module(module);
-      SmtModule smt(RTLIL::unescape_id(module->name), ir);
-      smt.write(*f);
-    }
-  }
+		for (auto module : design->selected_modules()) {
+			log("Processing module `%s`.\n", module->name.c_str());
+			auto ir = FunctionalIR::from_module(module);
+			SmtModule smt(RTLIL::unescape_id(module->name), ir);
+			smt.write(*f);
+		}
+	}
 } FunctionalSmtBackend;
 
 PRIVATE_NAMESPACE_END

From 39bf4f04f73ef0f91fc793d277b64047a82e4ea9 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Thu, 27 Jun 2024 01:46:10 +0200
Subject: [PATCH 384/499] Create VCD file from SMT file

---
 backends/functional/smtio.py                  | 1331 +++++++++++++++++
 tests/functional/single_cells/run-test.sh     |   39 +-
 .../single_cells/vcd_harness_smt.py           |  199 +++
 3 files changed, 1549 insertions(+), 20 deletions(-)
 create mode 100644 backends/functional/smtio.py
 create mode 100644 tests/functional/single_cells/vcd_harness_smt.py

diff --git a/backends/functional/smtio.py b/backends/functional/smtio.py
new file mode 100644
index 00000000000..e32f43c60a0
--- /dev/null
+++ b/backends/functional/smtio.py
@@ -0,0 +1,1331 @@
+#
+# yosys -- Yosys Open SYnthesis Suite
+#
+# Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
+#
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+#
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+#
+
+import sys, re, os, signal, json
+import subprocess
+if os.name == "posix":
+    import resource
+from copy import copy
+from select import select
+from time import time
+from queue import Queue, Empty
+from threading import Thread
+
+
+# This is needed so that the recursive SMT2 S-expression parser
+# does not run out of stack frames when parsing large expressions
+if os.name == "posix":
+    smtio_reclimit = 64 * 1024
+    if sys.getrecursionlimit() < smtio_reclimit:
+        sys.setrecursionlimit(smtio_reclimit)
+
+    current_rlimit_stack = resource.getrlimit(resource.RLIMIT_STACK)
+    if current_rlimit_stack[0] != resource.RLIM_INFINITY:
+        smtio_stacksize = 128 * 1024 * 1024
+        if os.uname().sysname == "Darwin":
+            # MacOS has rather conservative stack limits
+            smtio_stacksize = 8 * 1024 * 1024
+        if current_rlimit_stack[1] != resource.RLIM_INFINITY:
+            smtio_stacksize = min(smtio_stacksize, current_rlimit_stack[1])
+        if current_rlimit_stack[0] < smtio_stacksize:
+            try:
+                resource.setrlimit(resource.RLIMIT_STACK, (smtio_stacksize, current_rlimit_stack[1]))
+            except ValueError:
+                # couldn't get more stack, just run with what we have
+                pass
+
+
+# currently running solvers (so we can kill them)
+running_solvers = dict()
+forced_shutdown = False
+solvers_index = 0
+
+def force_shutdown(signum, frame):
+    global forced_shutdown
+    if not forced_shutdown:
+        forced_shutdown = True
+        if signum is not None:
+            print("<%s>" % signal.Signals(signum).name)
+        for p in running_solvers.values():
+            # os.killpg(os.getpgid(p.pid), signal.SIGTERM)
+            os.kill(p.pid, signal.SIGTERM)
+    sys.exit(1)
+
+if os.name == "posix":
+    signal.signal(signal.SIGHUP, force_shutdown)
+signal.signal(signal.SIGINT, force_shutdown)
+signal.signal(signal.SIGTERM, force_shutdown)
+
+def except_hook(exctype, value, traceback):
+    if not forced_shutdown:
+        sys.__excepthook__(exctype, value, traceback)
+    force_shutdown(None, None)
+
+sys.excepthook = except_hook
+
+
+def recursion_helper(iteration, *request):
+    stack = [iteration(*request)]
+
+    while stack:
+        top = stack.pop()
+        try:
+            request = next(top)
+        except StopIteration:
+            continue
+
+        stack.append(top)
+        stack.append(iteration(*request))
+
+
+hex_dict = {
+    "0": "0000", "1": "0001", "2": "0010", "3": "0011",
+    "4": "0100", "5": "0101", "6": "0110", "7": "0111",
+    "8": "1000", "9": "1001", "A": "1010", "B": "1011",
+    "C": "1100", "D": "1101", "E": "1110", "F": "1111",
+    "a": "1010", "b": "1011", "c": "1100", "d": "1101",
+    "e": "1110", "f": "1111"
+}
+
+
+class SmtModInfo:
+    def __init__(self):
+        self.inputs = set()
+        self.outputs = set()
+        self.registers = set()
+        self.memories = dict()
+        self.wires = set()
+        self.wsize = dict()
+        self.clocks = dict()
+        self.cells = dict()
+        self.asserts = dict()
+        self.assumes = dict()
+        self.covers = dict()
+        self.maximize = set()
+        self.minimize = set()
+        self.anyconsts = dict()
+        self.anyseqs = dict()
+        self.allconsts = dict()
+        self.allseqs = dict()
+        self.asize = dict()
+        self.witness = []
+
+
+class SmtIo:
+    def __init__(self, opts=None):
+        global solvers_index
+
+        self.logic = None
+        self.logic_qf = True
+        self.logic_ax = True
+        self.logic_uf = True
+        self.logic_bv = True
+        self.logic_dt = False
+        self.forall = False
+        self.timeout = 0
+        self.produce_models = True
+        self.recheck = False
+        self.smt2cache = [list()]
+        self.smt2_options = dict()
+        self.smt2_assumptions = dict()
+        self.p = None
+        self.p_index = solvers_index
+        solvers_index += 1
+
+        if opts is not None:
+            self.logic = opts.logic
+            self.solver = opts.solver
+            self.solver_opts = opts.solver_opts
+            self.debug_print = opts.debug_print
+            self.debug_file = opts.debug_file
+            self.dummy_file = opts.dummy_file
+            self.timeinfo = opts.timeinfo
+            self.timeout = opts.timeout
+            self.unroll = opts.unroll
+            self.noincr = opts.noincr
+            self.info_stmts = opts.info_stmts
+            self.nocomments = opts.nocomments
+
+        else:
+            self.solver = "yices"
+            self.solver_opts = list()
+            self.debug_print = False
+            self.debug_file = None
+            self.dummy_file = None
+            self.timeinfo = os.name != "nt"
+            self.timeout = 0
+            self.unroll = False
+            self.noincr = False
+            self.info_stmts = list()
+            self.nocomments = False
+
+        self.start_time = time()
+
+        self.modinfo = dict()
+        self.curmod = None
+        self.topmod = None
+        self.setup_done = False
+
+    def __del__(self):
+        if self.p is not None and not forced_shutdown:
+            os.killpg(os.getpgid(self.p.pid), signal.SIGTERM)
+            if running_solvers is not None:
+                del running_solvers[self.p_index]
+
+    def setup(self):
+        assert not self.setup_done
+
+        if self.forall:
+            self.unroll = False
+
+        if self.solver == "yices":
+            if self.forall:
+                self.noincr = True
+
+            if self.noincr:
+                self.popen_vargs = ['yices-smt2'] + self.solver_opts
+            else:
+                self.popen_vargs = ['yices-smt2', '--incremental'] + self.solver_opts
+            if self.timeout != 0:
+                self.popen_vargs.append('-t')
+                self.popen_vargs.append('%d' % self.timeout);
+
+        if self.solver == "z3":
+            self.popen_vargs = ['z3', '-smt2', '-in'] + self.solver_opts
+            if self.timeout != 0:
+                self.popen_vargs.append('-T:%d' % self.timeout);
+
+        if self.solver in ["cvc4", "cvc5"]:
+            self.recheck = True
+            if self.noincr:
+                self.popen_vargs = [self.solver, '--lang', 'smt2.6' if self.logic_dt else 'smt2'] + self.solver_opts
+            else:
+                self.popen_vargs = [self.solver, '--incremental', '--lang', 'smt2.6' if self.logic_dt else 'smt2'] + self.solver_opts
+            if self.timeout != 0:
+                self.popen_vargs.append('--tlimit=%d000' % self.timeout);
+
+        if self.solver == "mathsat":
+            self.popen_vargs = ['mathsat'] + self.solver_opts
+            if self.timeout != 0:
+                print('timeout option is not supported for mathsat.')
+                sys.exit(1)
+
+        if self.solver in ["boolector", "bitwuzla"]:
+            if self.noincr:
+                self.popen_vargs = [self.solver, '--smt2'] + self.solver_opts
+            else:
+                self.popen_vargs = [self.solver, '--smt2', '-i'] + self.solver_opts
+            self.unroll = True
+            if self.timeout != 0:
+                print('timeout option is not supported for %s.' % self.solver)
+                sys.exit(1)
+
+        if self.solver == "abc":
+            if len(self.solver_opts) > 0:
+                self.popen_vargs = ['yosys-abc', '-S', '; '.join(self.solver_opts)]
+            else:
+                self.popen_vargs = ['yosys-abc', '-S', '%blast; &sweep -C 5000; &syn4; &cec -s -m -C 2000']
+            self.logic_ax = False
+            self.unroll = True
+            self.noincr = True
+            if self.timeout != 0:
+                print('timeout option is not supported for abc.')
+                sys.exit(1)
+
+        if self.solver == "dummy":
+            assert self.dummy_file is not None
+            self.dummy_fd = open(self.dummy_file, "r")
+        else:
+            if self.dummy_file is not None:
+                self.dummy_fd = open(self.dummy_file, "w")
+            if not self.noincr:
+                self.p_open()
+
+        if self.unroll:
+            assert not self.forall
+            self.logic_uf = False
+            self.unroll_idcnt = 0
+            self.unroll_buffer = ""
+            self.unroll_level = 0
+            self.unroll_sorts = set()
+            self.unroll_objs = set()
+            self.unroll_decls = dict()
+            self.unroll_cache = dict()
+            self.unroll_stack = list()
+
+        if self.logic is None:
+            self.logic = ""
+            if self.logic_qf: self.logic += "QF_"
+            if self.logic_ax: self.logic += "A"
+            if self.logic_uf: self.logic += "UF"
+            if self.logic_bv: self.logic += "BV"
+            if self.logic_dt: self.logic = "ALL"
+            if self.solver == "yices" and self.forall: self.logic = "BV"
+
+        self.setup_done = True
+
+        for stmt in self.info_stmts:
+            self.write(stmt)
+
+        if self.produce_models:
+            self.write("(set-option :produce-models true)")
+
+        #See the SMT-LIB Standard, Section 4.1.7
+        modestart_options = [":global-declarations", ":interactive-mode", ":produce-assertions", ":produce-assignments", ":produce-models", ":produce-proofs", ":produce-unsat-assumptions", ":produce-unsat-cores", ":random-seed"]
+        for key, val in self.smt2_options.items():
+            if key in modestart_options:
+                self.write("(set-option {} {})".format(key, val))
+
+        self.write("(set-logic %s)" % self.logic)
+
+        if self.forall and self.solver == "yices":
+            self.write("(set-option :yices-ef-max-iters 1000000000)")
+
+        for key, val in self.smt2_options.items():
+            if key not in modestart_options:
+                self.write("(set-option {} {})".format(key, val))
+
+    def timestamp(self):
+        secs = int(time() - self.start_time)
+        return "## %3d:%02d:%02d " % (secs // (60*60), (secs // 60) % 60, secs % 60)
+
+    def replace_in_stmt(self, stmt, pat, repl):
+        if stmt == pat:
+            return repl
+
+        if isinstance(stmt, list):
+            return [self.replace_in_stmt(s, pat, repl) for s in stmt]
+
+        return stmt
+
+    def unroll_stmt(self, stmt):
+        result = []
+        recursion_helper(self._unroll_stmt_into, stmt, result)
+        return result.pop()
+
+    def _unroll_stmt_into(self, stmt, output, depth=128):
+        if not isinstance(stmt, list):
+            output.append(stmt)
+            return
+
+        new_stmt = []
+        for s in stmt:
+            if depth:
+                yield from self._unroll_stmt_into(s, new_stmt, depth - 1)
+            else:
+                yield s, new_stmt
+        stmt = new_stmt
+
+        if len(stmt) >= 2 and not isinstance(stmt[0], list) and stmt[0] in self.unroll_decls:
+            assert stmt[1] in self.unroll_objs
+
+            key = tuple(stmt)
+            if key not in self.unroll_cache:
+                decl = copy(self.unroll_decls[key[0]])
+
+                self.unroll_cache[key] = "|UNROLL#%d|" % self.unroll_idcnt
+                decl[1] = self.unroll_cache[key]
+                self.unroll_idcnt += 1
+
+                if decl[0] == "declare-fun":
+                    if isinstance(decl[3], list) or decl[3] not in self.unroll_sorts:
+                        self.unroll_objs.add(decl[1])
+                        decl[2] = list()
+                    else:
+                        self.unroll_objs.add(decl[1])
+                        decl = list()
+
+                elif decl[0] == "define-fun":
+                    arg_index = 1
+                    for arg_name, arg_sort in decl[2]:
+                        decl[4] = self.replace_in_stmt(decl[4], arg_name, key[arg_index])
+                        arg_index += 1
+                    decl[2] = list()
+
+                if len(decl) > 0:
+                    tmp = []
+                    if depth:
+                        yield from self._unroll_stmt_into(decl, tmp, depth - 1)
+                    else:
+                        yield decl, tmp
+
+                    decl = tmp.pop()
+                    self.write(self.unparse(decl), unroll=False)
+
+            output.append(self.unroll_cache[key])
+            return
+
+        output.append(stmt)
+
+    def p_thread_main(self):
+        while True:
+            data = self.p.stdout.readline().decode("utf-8")
+            if data == "": break
+            self.p_queue.put(data)
+        self.p_queue.put("")
+        self.p_running = False
+
+    def p_open(self):
+        assert self.p is None
+        try:
+            self.p = subprocess.Popen(self.popen_vargs, stdin=subprocess.PIPE, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+        except FileNotFoundError:
+            print("%s SMT Solver '%s' not found in path." % (self.timestamp(), self.popen_vargs[0]), flush=True)
+            sys.exit(1)
+        running_solvers[self.p_index] = self.p
+        self.p_running = True
+        self.p_next = None
+        self.p_queue = Queue()
+        self.p_thread = Thread(target=self.p_thread_main)
+        self.p_thread.start()
+
+    def p_write(self, data, flush):
+        assert self.p is not None
+        self.p.stdin.write(bytes(data, "utf-8"))
+        if flush: self.p.stdin.flush()
+
+    def p_read(self):
+        assert self.p is not None
+        if self.p_next is not None:
+            data = self.p_next
+            self.p_next = None
+            return data
+        if not self.p_running:
+            return ""
+        return self.p_queue.get()
+
+    def p_poll(self, timeout=0.1):
+        assert self.p is not None
+        assert self.p_running
+        if self.p_next is not None:
+            return False
+        try:
+            self.p_next = self.p_queue.get(True, timeout)
+            return False
+        except Empty:
+            return True
+
+    def p_close(self):
+        assert self.p is not None
+        self.p.stdin.close()
+        self.p_thread.join()
+        assert not self.p_running
+        del running_solvers[self.p_index]
+        self.p = None
+        self.p_next = None
+        self.p_queue = None
+        self.p_thread = None
+
+    def write(self, stmt, unroll=True):
+        if stmt.startswith(";"):
+            self.info(stmt)
+            if not self.setup_done:
+                self.info_stmts.append(stmt)
+                return
+        elif not self.setup_done:
+            self.setup()
+
+        stmt = stmt.strip()
+
+        if self.nocomments or self.unroll:
+            stmt = re.sub(r" *;.*", "", stmt)
+            if stmt == "": return
+
+        recheck = None
+
+        if self.solver != "dummy":
+            if self.noincr:
+                # Don't close the solver yet, if we're just unrolling definitions
+                # required for a (get-...) statement
+                if self.p is not None and not stmt.startswith("(get-") and unroll:
+                    self.p_close()
+
+        if unroll and self.unroll:
+            s = re.sub(r"\|[^|]*\|", "", stmt)
+            self.unroll_level += s.count("(") - s.count(")")
+            if self.unroll_level > 0:
+                self.unroll_buffer += stmt
+                self.unroll_buffer += " "
+                return
+            else:
+                stmt = self.unroll_buffer + stmt
+                self.unroll_buffer = ""
+
+            s = self.parse(stmt)
+
+            if self.recheck and s and s[0].startswith("get-"):
+                recheck = self.unroll_idcnt
+
+            if self.debug_print:
+                print("-> %s" % s)
+
+            if len(s) == 3 and s[0] == "declare-sort" and s[2] == "0":
+                self.unroll_sorts.add(s[1])
+                return
+
+            elif len(s) == 4 and s[0] == "declare-fun" and s[2] == [] and s[3] in self.unroll_sorts:
+                self.unroll_objs.add(s[1])
+                return
+
+            elif len(s) >= 4 and s[0] == "declare-fun":
+                for arg_sort in s[2]:
+                    if arg_sort in self.unroll_sorts:
+                        self.unroll_decls[s[1]] = s
+                        return
+
+            elif len(s) >= 4 and s[0] == "define-fun":
+                for arg_name, arg_sort in s[2]:
+                    if arg_sort in self.unroll_sorts:
+                        self.unroll_decls[s[1]] = s
+                        return
+
+            stmt = self.unparse(self.unroll_stmt(s))
+
+            if recheck is not None and recheck != self.unroll_idcnt:
+                self.check_sat(["sat"])
+
+            if stmt == "(push 1)":
+                self.unroll_stack.append((
+                    copy(self.unroll_sorts),
+                    copy(self.unroll_objs),
+                    copy(self.unroll_decls),
+                    copy(self.unroll_cache),
+                ))
+
+            if stmt == "(pop 1)":
+                self.unroll_sorts, self.unroll_objs, self.unroll_decls, self.unroll_cache = self.unroll_stack.pop()
+
+        if self.debug_print:
+            print("> %s" % stmt)
+
+        if self.debug_file:
+            print(stmt, file=self.debug_file)
+            self.debug_file.flush()
+
+        if self.solver != "dummy":
+            if self.noincr:
+                if stmt == "(push 1)":
+                    self.smt2cache.append(list())
+                elif stmt == "(pop 1)":
+                    self.smt2cache.pop()
+                else:
+                    if self.p is not None:
+                        self.p_write(stmt + "\n", True)
+                    self.smt2cache[-1].append(stmt)
+            else:
+                self.p_write(stmt + "\n", True)
+
+    def info(self, stmt):
+        if not stmt.startswith("; yosys-smt2-"):
+            return
+
+        fields = stmt.split()
+
+        if fields[1] == "yosys-smt2-solver-option":
+            self.smt2_options[fields[2]] = fields[3]
+
+        if fields[1] == "yosys-smt2-nomem":
+            if self.logic is None:
+                self.logic_ax = False
+
+        if fields[1] == "yosys-smt2-nobv":
+            if self.logic is None:
+                self.logic_bv = False
+
+        if fields[1] == "yosys-smt2-stdt":
+            if self.logic is None:
+                self.logic_dt = True
+
+        if fields[1] == "yosys-smt2-forall":
+            if self.logic is None:
+                self.logic_qf = False
+            self.forall = True
+
+        if fields[1] == "yosys-smt2-module":
+            self.curmod = fields[2]
+            self.modinfo[self.curmod] = SmtModInfo()
+
+        if fields[1] == "yosys-smt2-cell":
+            self.modinfo[self.curmod].cells[fields[3]] = fields[2]
+
+        if fields[1] == "yosys-smt2-topmod":
+            self.topmod = fields[2]
+
+        if fields[1] == "yosys-smt2-input":
+            self.modinfo[self.curmod].inputs.add(fields[2])
+            self.modinfo[self.curmod].wsize[fields[2]] = int(fields[3])
+
+        if fields[1] == "yosys-smt2-output":
+            self.modinfo[self.curmod].outputs.add(fields[2])
+            self.modinfo[self.curmod].wsize[fields[2]] = int(fields[3])
+
+        if fields[1] == "yosys-smt2-register":
+            self.modinfo[self.curmod].registers.add(fields[2])
+            self.modinfo[self.curmod].wsize[fields[2]] = int(fields[3])
+
+        if fields[1] == "yosys-smt2-memory":
+            self.modinfo[self.curmod].memories[fields[2]] = (int(fields[3]), int(fields[4]), int(fields[5]), int(fields[6]), fields[7] == "async")
+
+        if fields[1] == "yosys-smt2-wire":
+            self.modinfo[self.curmod].wires.add(fields[2])
+            self.modinfo[self.curmod].wsize[fields[2]] = int(fields[3])
+
+        if fields[1] == "yosys-smt2-clock":
+            for edge in fields[3:]:
+                if fields[2] not in self.modinfo[self.curmod].clocks:
+                    self.modinfo[self.curmod].clocks[fields[2]] = edge
+                elif self.modinfo[self.curmod].clocks[fields[2]] != edge:
+                    self.modinfo[self.curmod].clocks[fields[2]] = "event"
+
+        if fields[1] == "yosys-smt2-assert":
+            if len(fields) > 4:
+                self.modinfo[self.curmod].asserts["%s_a %s" % (self.curmod, fields[2])] = f'{fields[4]} ({fields[3]})'
+            else:
+                self.modinfo[self.curmod].asserts["%s_a %s" % (self.curmod, fields[2])] = fields[3]
+
+        if fields[1] == "yosys-smt2-cover":
+            if len(fields) > 4:
+                self.modinfo[self.curmod].covers["%s_c %s" % (self.curmod, fields[2])] = f'{fields[4]} ({fields[3]})'
+            else:
+                self.modinfo[self.curmod].covers["%s_c %s" % (self.curmod, fields[2])] = fields[3]
+
+        if fields[1] == "yosys-smt2-assume":
+            if len(fields) > 4:
+                self.modinfo[self.curmod].assumes["%s_u %s" % (self.curmod, fields[2])] = f'{fields[4]} ({fields[3]})'
+            else:
+                self.modinfo[self.curmod].assumes["%s_u %s" % (self.curmod, fields[2])] = fields[3]
+
+        if fields[1] == "yosys-smt2-maximize":
+            self.modinfo[self.curmod].maximize.add(fields[2])
+
+        if fields[1] == "yosys-smt2-minimize":
+            self.modinfo[self.curmod].minimize.add(fields[2])
+
+        if fields[1] == "yosys-smt2-anyconst":
+            self.modinfo[self.curmod].anyconsts[fields[2]] = (fields[4], None if len(fields) <= 5 else fields[5])
+            self.modinfo[self.curmod].asize[fields[2]] = int(fields[3])
+
+        if fields[1] == "yosys-smt2-anyseq":
+            self.modinfo[self.curmod].anyseqs[fields[2]] = (fields[4], None if len(fields) <= 5 else fields[5])
+            self.modinfo[self.curmod].asize[fields[2]] = int(fields[3])
+
+        if fields[1] == "yosys-smt2-allconst":
+            self.modinfo[self.curmod].allconsts[fields[2]] = (fields[4], None if len(fields) <= 5 else fields[5])
+            self.modinfo[self.curmod].asize[fields[2]] = int(fields[3])
+
+        if fields[1] == "yosys-smt2-allseq":
+            self.modinfo[self.curmod].allseqs[fields[2]] = (fields[4], None if len(fields) <= 5 else fields[5])
+            self.modinfo[self.curmod].asize[fields[2]] = int(fields[3])
+
+        if fields[1] == "yosys-smt2-witness":
+            data = json.loads(stmt.split(None, 2)[2])
+            if data.get("type") in ["cell", "mem", "posedge", "negedge", "input", "reg", "init", "seq", "blackbox"]:
+                self.modinfo[self.curmod].witness.append(data)
+
+    def hiernets(self, top, regs_only=False):
+        def hiernets_worker(nets, mod, cursor):
+            for netname in sorted(self.modinfo[mod].wsize.keys()):
+                if not regs_only or netname in self.modinfo[mod].registers:
+                    nets.append(cursor + [netname])
+            for cellname, celltype in sorted(self.modinfo[mod].cells.items()):
+                hiernets_worker(nets, celltype, cursor + [cellname])
+
+        nets = list()
+        hiernets_worker(nets, top, [])
+        return nets
+
+    def hieranyconsts(self, top):
+        def worker(results, mod, cursor):
+            for name, value in sorted(self.modinfo[mod].anyconsts.items()):
+                width = self.modinfo[mod].asize[name]
+                results.append((cursor, name, value[0], value[1], width))
+            for cellname, celltype in sorted(self.modinfo[mod].cells.items()):
+                worker(results, celltype, cursor + [cellname])
+
+        results = list()
+        worker(results, top, [])
+        return results
+
+    def hieranyseqs(self, top):
+        def worker(results, mod, cursor):
+            for name, value in sorted(self.modinfo[mod].anyseqs.items()):
+                width = self.modinfo[mod].asize[name]
+                results.append((cursor, name, value[0], value[1], width))
+            for cellname, celltype in sorted(self.modinfo[mod].cells.items()):
+                worker(results, celltype, cursor + [cellname])
+
+        results = list()
+        worker(results, top, [])
+        return results
+
+    def hierallconsts(self, top):
+        def worker(results, mod, cursor):
+            for name, value in sorted(self.modinfo[mod].allconsts.items()):
+                width = self.modinfo[mod].asize[name]
+                results.append((cursor, name, value[0], value[1], width))
+            for cellname, celltype in sorted(self.modinfo[mod].cells.items()):
+                worker(results, celltype, cursor + [cellname])
+
+        results = list()
+        worker(results, top, [])
+        return results
+
+    def hierallseqs(self, top):
+        def worker(results, mod, cursor):
+            for name, value in sorted(self.modinfo[mod].allseqs.items()):
+                width = self.modinfo[mod].asize[name]
+                results.append((cursor, name, value[0], value[1], width))
+            for cellname, celltype in sorted(self.modinfo[mod].cells.items()):
+                worker(results, celltype, cursor + [cellname])
+
+        results = list()
+        worker(results, top, [])
+        return results
+
+    def hiermems(self, top):
+        def hiermems_worker(mems, mod, cursor):
+            for memname in sorted(self.modinfo[mod].memories.keys()):
+                mems.append(cursor + [memname])
+            for cellname, celltype in sorted(self.modinfo[mod].cells.items()):
+                hiermems_worker(mems, celltype, cursor + [cellname])
+
+        mems = list()
+        hiermems_worker(mems, top, [])
+        return mems
+
+    def hierwitness(self, top, allregs=False, blackbox=True):
+        init_witnesses = []
+        seq_witnesses = []
+        clk_witnesses = []
+        mem_witnesses = []
+
+        def absolute(path, cursor, witness):
+            return {
+                **witness,
+                "path": path + tuple(witness["path"]),
+                "smtpath": cursor + [witness["smtname"]],
+            }
+
+        for witness in self.modinfo[top].witness:
+            if witness["type"] == "input":
+                seq_witnesses.append(absolute((), [], witness))
+            if witness["type"] in ("posedge", "negedge"):
+                clk_witnesses.append(absolute((), [], witness))
+
+        init_types = ["init"]
+        if allregs:
+            init_types.append("reg")
+
+        seq_types = ["seq"]
+        if blackbox:
+            seq_types.append("blackbox")
+
+        def worker(mod, path, cursor):
+            cell_paths = {}
+            for witness in self.modinfo[mod].witness:
+                if witness["type"] in init_types:
+                    init_witnesses.append(absolute(path, cursor, witness))
+                if witness["type"] in seq_types:
+                    seq_witnesses.append(absolute(path, cursor, witness))
+                if witness["type"] == "mem":
+                    if allregs and not witness["rom"]:
+                        width, size = witness["width"], witness["size"]
+                        witness = {**witness, "uninitialized": [{"width": width * size, "offset": 0}]}
+                    if not witness["uninitialized"]:
+                        continue
+
+                    mem_witnesses.append(absolute(path, cursor, witness))
+                if witness["type"] == "cell":
+                    cell_paths[witness["smtname"]] = tuple(witness["path"])
+
+            for cellname, celltype in sorted(self.modinfo[mod].cells.items()):
+                worker(celltype, path + cell_paths.get(cellname, ("?" + cellname,)), cursor + [cellname])
+
+        worker(top, (), [])
+        return init_witnesses, seq_witnesses, clk_witnesses, mem_witnesses
+
+    def read(self):
+        stmt = []
+        count_brackets = 0
+
+        while True:
+            if self.solver == "dummy":
+                line = self.dummy_fd.readline().strip()
+            else:
+                line = self.p_read().strip()
+                if self.dummy_file is not None:
+                    self.dummy_fd.write(line + "\n")
+
+            count_brackets += line.count("(")
+            count_brackets -= line.count(")")
+            stmt.append(line)
+
+            if self.debug_print:
+                print("< %s" % line)
+            if count_brackets == 0:
+                break
+            if self.solver != "dummy" and self.p.poll():
+                print("%s Solver terminated unexpectedly: %s" % (self.timestamp(), "".join(stmt)), flush=True)
+                sys.exit(1)
+
+        stmt = "".join(stmt)
+        if stmt.startswith("(error"):
+            print("%s Solver Error: %s" % (self.timestamp(), stmt), flush=True)
+            if self.solver != "dummy":
+                self.p_close()
+            sys.exit(1)
+
+        return stmt
+
+    def check_sat(self, expected=["sat", "unsat", "unknown", "timeout", "interrupted"]):
+        if self.smt2_assumptions:
+            assume_exprs = " ".join(self.smt2_assumptions.values())
+            check_stmt = f"(check-sat-assuming ({assume_exprs}))"
+        else:
+            check_stmt = "(check-sat)"
+        if self.debug_print:
+            print(f"> {check_stmt}")
+        if self.debug_file and not self.nocomments:
+            print("; running check-sat..", file=self.debug_file)
+            self.debug_file.flush()
+
+        if self.solver != "dummy":
+            if self.noincr:
+                if self.p is not None:
+                    self.p_close()
+                self.p_open()
+                for cache_ctx in self.smt2cache:
+                    for cache_stmt in cache_ctx:
+                        self.p_write(cache_stmt + "\n", False)
+
+            self.p_write(f"{check_stmt}\n", True)
+
+            if self.timeinfo:
+                i = 0
+                s = r"/-\|"
+
+                count = 0
+                num_bs = 0
+                while self.p_poll():
+                    count += 1
+
+                    if count < 25:
+                        continue
+
+                    if count % 10 == 0 or count == 25:
+                        secs = count // 10
+
+                        if secs < 60:
+                            m = "(%d seconds)" % secs
+                        elif secs < 60*60:
+                            m = "(%d seconds -- %d:%02d)" % (secs, secs // 60, secs % 60)
+                        else:
+                            m = "(%d seconds -- %d:%02d:%02d)" % (secs, secs // (60*60), (secs // 60) % 60, secs % 60)
+
+                        print("%s %s %c" % ("\b \b" * num_bs, m, s[i]), end="", file=sys.stderr)
+                        num_bs = len(m) + 3
+
+                    else:
+                        print("\b" + s[i], end="", file=sys.stderr)
+
+                    sys.stderr.flush()
+                    i = (i + 1) % len(s)
+
+                if num_bs != 0:
+                    print("\b \b" * num_bs, end="", file=sys.stderr)
+                    sys.stderr.flush()
+
+            else:
+                count = 0
+                while self.p_poll(60):
+                    count += 1
+                    msg = None
+
+                    if count == 1:
+                        msg = "1 minute"
+
+                    elif count in [5, 10, 15, 30]:
+                        msg = "%d minutes" % count
+
+                    elif count == 60:
+                        msg = "1 hour"
+
+                    elif count % 60 == 0:
+                        msg = "%d hours" % (count // 60)
+
+                    if msg is not None:
+                        print("%s waiting for solver (%s)" % (self.timestamp(), msg), flush=True)
+
+        if self.forall:
+            result = self.read()
+            while result not in ["sat", "unsat", "unknown", "timeout", "interrupted", ""]:
+                print("%s %s: %s" % (self.timestamp(), self.solver, result))
+                result = self.read()
+        else:
+            result = self.read()
+
+        if self.debug_file:
+            print("(set-info :status %s)" % result, file=self.debug_file)
+            print(check_stmt, file=self.debug_file)
+            self.debug_file.flush()
+
+        if result not in expected:
+            if result == "":
+                print("%s Unexpected EOF response from solver." % (self.timestamp()), flush=True)
+            else:
+                print("%s Unexpected response from solver: %s" % (self.timestamp(), result), flush=True)
+            if self.solver != "dummy":
+                self.p_close()
+            sys.exit(1)
+
+        return result
+
+    def parse(self, stmt):
+        def worker(stmt, cursor=0):
+            while stmt[cursor] in [" ", "\t", "\r", "\n"]:
+                cursor += 1
+
+            if stmt[cursor] == '(':
+                expr = []
+                cursor += 1
+                while stmt[cursor] != ')':
+                    el, cursor = worker(stmt, cursor)
+                    expr.append(el)
+                return expr, cursor+1
+
+            if stmt[cursor] == '|':
+                expr = "|"
+                cursor += 1
+                while stmt[cursor] != '|':
+                    expr += stmt[cursor]
+                    cursor += 1
+                expr += "|"
+                return expr, cursor+1
+
+            expr = ""
+            while stmt[cursor] not in ["(", ")", "|", " ", "\t", "\r", "\n"]:
+                expr += stmt[cursor]
+                cursor += 1
+            return expr, cursor
+        return worker(stmt)[0]
+
+    def unparse(self, stmt):
+        if isinstance(stmt, list):
+            return "(" + " ".join([self.unparse(s) for s in stmt]) + ")"
+        return stmt
+
+    def bv2hex(self, v):
+        h = ""
+        v = self.bv2bin(v)
+        while len(v) > 0:
+            d = 0
+            if len(v) > 0 and v[-1] == "1": d += 1
+            if len(v) > 1 and v[-2] == "1": d += 2
+            if len(v) > 2 and v[-3] == "1": d += 4
+            if len(v) > 3 and v[-4] == "1": d += 8
+            h = hex(d)[2:] + h
+            if len(v) < 4: break
+            v = v[:-4]
+        return h
+
+    def bv2bin(self, v):
+        if type(v) is list and len(v) == 3 and v[0] == "_" and v[1].startswith("bv"):
+            x, n = int(v[1][2:]), int(v[2])
+            return "".join("1" if (x & (1 << i)) else "0" for i in range(n-1, -1, -1))
+        if v == "true": return "1"
+        if v == "false": return "0"
+        if v.startswith("#b"):
+            return v[2:]
+        if v.startswith("#x"):
+            return "".join(hex_dict.get(x) for x in v[2:])
+        assert False
+
+    def bv2int(self, v):
+        return int(self.bv2bin(v), 2)
+
+    def get_raw_unsat_assumptions(self):
+        self.write("(get-unsat-assumptions)")
+        exprs = set(self.unparse(part) for part in self.parse(self.read()))
+        unsat_assumptions = []
+        for key, value in self.smt2_assumptions.items():
+            # normalize expression
+            value = self.unparse(self.parse(value))
+            if value in exprs:
+                exprs.remove(value)
+                unsat_assumptions.append(key)
+        return unsat_assumptions
+
+    def get_unsat_assumptions(self, minimize=False):
+        if not minimize:
+            return self.get_raw_unsat_assumptions()
+        required_assumptions = {}
+
+        while True:
+            candidate_assumptions = {}
+            for key in self.get_raw_unsat_assumptions():
+                if key not in required_assumptions:
+                    candidate_assumptions[key] = self.smt2_assumptions[key]
+
+            while candidate_assumptions:
+
+                candidate_key, candidate_assume = candidate_assumptions.popitem()
+
+                self.smt2_assumptions = {}
+                for key, assume in candidate_assumptions.items():
+                    self.smt2_assumptions[key] = assume
+                for key, assume in required_assumptions.items():
+                    self.smt2_assumptions[key] = assume
+                result = self.check_sat()
+
+                if result == 'unsat':
+                    candidate_assumptions = None
+                else:
+                    required_assumptions[candidate_key] = candidate_assume
+
+            if candidate_assumptions is not None:
+                return list(required_assumptions)
+
+    def get(self, expr):
+        self.write("(get-value (%s))" % (expr))
+        return self.parse(self.read())[0][1]
+
+    def get_list(self, expr_list):
+        if len(expr_list) == 0:
+            return []
+        self.write("(get-value (%s))" % " ".join(expr_list))
+        return [n[1] for n in self.parse(self.read()) if n]
+
+    def get_path(self, mod, path):
+        assert mod in self.modinfo
+        path = path.replace("\\", "/").split(".")
+
+        for i in range(len(path)-1):
+            first = ".".join(path[0:i+1])
+            second = ".".join(path[i+1:])
+
+            if first in self.modinfo[mod].cells:
+                nextmod = self.modinfo[mod].cells[first]
+                return [first] + self.get_path(nextmod, second)
+
+        return [".".join(path)]
+
+    def net_expr(self, mod, base, path):
+        if len(path) == 0:
+            return base
+
+        if len(path) == 1:
+            assert mod in self.modinfo
+            if path[0] == "":
+                return base
+            if isinstance(path[0], int):
+                return "(|%s#%d| %s)" % (mod, path[0], base)
+            if path[0] in self.modinfo[mod].cells:
+                return "(|%s_h %s| %s)" % (mod, path[0], base)
+            if path[0] in self.modinfo[mod].wsize:
+                return "(|%s_n %s| %s)" % (mod, path[0], base)
+            if path[0] in self.modinfo[mod].memories:
+                return "(|%s_m %s| %s)" % (mod, path[0], base)
+            assert 0
+
+        assert mod in self.modinfo
+        assert path[0] in self.modinfo[mod].cells
+
+        nextmod = self.modinfo[mod].cells[path[0]]
+        nextbase = "(|%s_h %s| %s)" % (mod, path[0], base)
+        return self.net_expr(nextmod, nextbase, path[1:])
+
+    def witness_net_expr(self, mod, base, witness):
+        net = self.net_expr(mod, base, witness["smtpath"])
+        is_bool = self.net_width(mod, witness["smtpath"]) == 1
+        if is_bool:
+            assert witness["width"] == 1
+            assert witness["smtoffset"] == 0
+            return net
+        return "((_ extract %d %d) %s)" % (witness["smtoffset"] + witness["width"] - 1, witness["smtoffset"], net)
+
+    def net_width(self, mod, net_path):
+        for i in range(len(net_path)-1):
+            assert mod in self.modinfo
+            assert net_path[i] in self.modinfo[mod].cells
+            mod = self.modinfo[mod].cells[net_path[i]]
+
+        assert mod in self.modinfo
+        if isinstance(net_path[-1], int):
+            return None
+        assert net_path[-1] in self.modinfo[mod].wsize
+        return self.modinfo[mod].wsize[net_path[-1]]
+
+    def net_clock(self, mod, net_path):
+        for i in range(len(net_path)-1):
+            assert mod in self.modinfo
+            assert net_path[i] in self.modinfo[mod].cells
+            mod = self.modinfo[mod].cells[net_path[i]]
+
+        assert mod in self.modinfo
+        if net_path[-1] not in self.modinfo[mod].clocks:
+            return None
+        return self.modinfo[mod].clocks[net_path[-1]]
+
+    def net_exists(self, mod, net_path):
+        for i in range(len(net_path)-1):
+            if mod not in self.modinfo: return False
+            if net_path[i] not in self.modinfo[mod].cells: return False
+            mod = self.modinfo[mod].cells[net_path[i]]
+
+        if mod not in self.modinfo: return False
+        if net_path[-1] not in self.modinfo[mod].wsize: return False
+        return True
+
+    def mem_exists(self, mod, mem_path):
+        for i in range(len(mem_path)-1):
+            if mod not in self.modinfo: return False
+            if mem_path[i] not in self.modinfo[mod].cells: return False
+            mod = self.modinfo[mod].cells[mem_path[i]]
+
+        if mod not in self.modinfo: return False
+        if mem_path[-1] not in self.modinfo[mod].memories: return False
+        return True
+
+    def mem_expr(self, mod, base, path, port=None, infomode=False):
+        if len(path) == 1:
+            assert mod in self.modinfo
+            assert path[0] in self.modinfo[mod].memories
+            if infomode:
+                return self.modinfo[mod].memories[path[0]]
+            return "(|%s_m%s %s| %s)" % (mod, "" if port is None else ":%s" % port, path[0], base)
+
+        assert mod in self.modinfo
+        assert path[0] in self.modinfo[mod].cells
+
+        nextmod = self.modinfo[mod].cells[path[0]]
+        nextbase = "(|%s_h %s| %s)" % (mod, path[0], base)
+        return self.mem_expr(nextmod, nextbase, path[1:], port=port, infomode=infomode)
+
+    def mem_info(self, mod, path):
+        return self.mem_expr(mod, "", path, infomode=True)
+
+    def get_net(self, mod_name, net_path, state_name):
+        return self.get(self.net_expr(mod_name, state_name, net_path))
+
+    def get_net_list(self, mod_name, net_path_list, state_name):
+        return self.get_list([self.net_expr(mod_name, state_name, n) for n in net_path_list])
+
+    def get_net_hex(self, mod_name, net_path, state_name):
+        return self.bv2hex(self.get_net(mod_name, net_path, state_name))
+
+    def get_net_hex_list(self, mod_name, net_path_list, state_name):
+        return [self.bv2hex(v) for v in self.get_net_list(mod_name, net_path_list, state_name)]
+
+    def get_net_bin(self, mod_name, net_path, state_name):
+        return self.bv2bin(self.get_net(mod_name, net_path, state_name))
+
+    def get_net_bin_list(self, mod_name, net_path_list, state_name):
+        return [self.bv2bin(v) for v in self.get_net_list(mod_name, net_path_list, state_name)]
+
+    def wait(self):
+        if self.p is not None:
+            self.p.wait()
+            self.p_close()
+
+
+class SmtOpts:
+    def __init__(self):
+        self.shortopts = "s:S:v"
+        self.longopts = ["unroll", "noincr", "noprogress", "timeout=", "dump-smt2=", "logic=", "dummy=", "info=", "nocomments"]
+        self.solver = "yices"
+        self.solver_opts = list()
+        self.debug_print = False
+        self.debug_file = None
+        self.dummy_file = None
+        self.unroll = False
+        self.noincr = False
+        self.timeinfo = os.name != "nt"
+        self.timeout = 0
+        self.logic = None
+        self.info_stmts = list()
+        self.nocomments = False
+
+    def handle(self, o, a):
+        if o == "-s":
+            self.solver = a
+        elif o == "-S":
+            self.solver_opts.append(a)
+        elif o == "--timeout":
+            self.timeout = int(a)
+        elif o == "-v":
+            self.debug_print = True
+        elif o == "--unroll":
+            self.unroll = True
+        elif o == "--noincr":
+            self.noincr = True
+        elif o == "--noprogress":
+            self.timeinfo = False
+        elif o == "--dump-smt2":
+            self.debug_file = open(a, "w")
+        elif o == "--logic":
+            self.logic = a
+        elif o == "--dummy":
+            self.dummy_file = a
+        elif o == "--info":
+            self.info_stmts.append(a)
+        elif o == "--nocomments":
+            self.nocomments = True
+        else:
+            return False
+        return True
+
+    def helpmsg(self):
+        return """
+    -s <solver>
+        set SMT solver: z3, yices, boolector, bitwuzla, cvc4, mathsat, dummy
+        default: yices
+
+    -S <opt>
+        pass <opt> as command line argument to the solver
+
+    --timeout <value>
+        set the solver timeout to the specified value (in seconds).
+
+    --logic <smt2_logic>
+        use the specified SMT2 logic (e.g. QF_AUFBV)
+
+    --dummy <filename>
+        if solver is "dummy", read solver output from that file
+        otherwise: write solver output to that file
+
+    -v
+        enable debug output
+
+    --unroll
+        unroll uninterpreted functions
+
+    --noincr
+        don't use incremental solving, instead restart solver for
+        each (check-sat). This also avoids (push) and (pop).
+
+    --noprogress
+        disable timer display during solving
+        (this option is set implicitly on Windows)
+
+    --dump-smt2 <filename>
+        write smt2 statements to file
+
+    --info <smt2-info-stmt>
+        include the specified smt2 info statement in the smt2 output
+
+    --nocomments
+        strip all comments from the generated smt2 code
+"""
+
+
+class MkVcd:
+    def __init__(self, f):
+        self.f = f
+        self.t = -1
+        self.nets = dict()
+        self.clocks = dict()
+
+    def add_net(self, path, width):
+        path = tuple(path)
+        assert self.t == -1
+        key = "n%d" % len(self.nets)
+        self.nets[path] = (key, width)
+
+    def add_clock(self, path, edge):
+        path = tuple(path)
+        assert self.t == -1
+        key = "n%d" % len(self.nets)
+        self.nets[path] = (key, 1)
+        self.clocks[path] = (key, edge)
+
+    def set_net(self, path, bits):
+        path = tuple(path)
+        assert self.t >= 0
+        assert path in self.nets
+        if path not in self.clocks:
+            print("b%s %s" % (bits, self.nets[path][0]), file=self.f)
+
+    def escape_name(self, name):
+        name = re.sub(r"\[([0-9a-zA-Z_]*[a-zA-Z_][0-9a-zA-Z_]*)\]", r"<\1>", name)
+        if re.match(r"[\[\]]", name) and name[0] != "\\":
+            name = "\\" + name
+        return name
+
+    def set_time(self, t):
+        assert t >= self.t
+        if t != self.t:
+            if self.t == -1:
+                print("$version Generated by Yosys-SMTBMC $end", file=self.f)
+                print("$timescale 1ns $end", file=self.f)
+                print("$var integer 32 t smt_step $end", file=self.f)
+                print("$var event 1 ! smt_clock $end", file=self.f)
+
+                def vcdescape(n):
+                    if n.startswith("$") or ":" in n:
+                        return "\\" + n
+                    return n
+
+                scope = []
+                for path in sorted(self.nets):
+                    key, width = self.nets[path]
+
+                    uipath = list(path)
+                    if "." in uipath[-1] and not uipath[-1].startswith("$"):
+                        uipath = uipath[0:-1] + uipath[-1].split(".")
+                    for i in range(len(uipath)):
+                        uipath[i] = re.sub(r"\[([^\]]*)\]", r"<\1>", uipath[i])
+
+                    while uipath[:len(scope)] != scope:
+                        print("$upscope $end", file=self.f)
+                        scope = scope[:-1]
+
+                    while uipath[:-1] != scope:
+                        scopename = uipath[len(scope)]
+                        print("$scope module %s $end" % vcdescape(scopename), file=self.f)
+                        scope.append(uipath[len(scope)])
+
+                    if path in self.clocks and self.clocks[path][1] == "event":
+                        print("$var event 1 %s %s $end" % (key, vcdescape(uipath[-1])), file=self.f)
+                    else:
+                        print("$var wire %d %s %s $end" % (width, key, vcdescape(uipath[-1])), file=self.f)
+
+                for i in range(len(scope)):
+                    print("$upscope $end", file=self.f)
+
+                print("$enddefinitions $end", file=self.f)
+
+            self.t = t
+            assert self.t >= 0
+
+            if self.t > 0:
+                print("#%d" % (10 * self.t - 5), file=self.f)
+                for path in sorted(self.clocks.keys()):
+                    if self.clocks[path][1] == "posedge":
+                        print("b0 %s" % self.nets[path][0], file=self.f)
+                    elif self.clocks[path][1] == "negedge":
+                        print("b1 %s" % self.nets[path][0], file=self.f)
+
+            print("#%d" % (10 * self.t), file=self.f)
+            print("1!", file=self.f)
+            print("b%s t" % format(self.t, "032b"), file=self.f)
+
+            for path in sorted(self.clocks.keys()):
+                if self.clocks[path][1] == "negedge":
+                    print("b0 %s" % self.nets[path][0], file=self.f)
+                else:
+                    print("b1 %s" % self.nets[path][0], file=self.f)
diff --git a/tests/functional/single_cells/run-test.sh b/tests/functional/single_cells/run-test.sh
index 473c7faea51..67358639bf2 100755
--- a/tests/functional/single_cells/run-test.sh
+++ b/tests/functional/single_cells/run-test.sh
@@ -55,28 +55,27 @@ run_smt_test() {
 	if z3 "${base_name}.smt2"; then
             echo "SMT file ${base_name}.smt2 is valid ."
 	    smt_successful_files["$rtlil_file"]="Success"
-            # if python3 using_smtio.py "${base_name}.smt2"; then
-	    # 	echo "Python script generated VCD file for $rtlil_file successfully."
+            if python3 vcd_harness_smt.py "${base_name}.smt2"; then
+		echo "Python script generated VCD file for $rtlil_file successfully."
 
-	    # 	if [ -f "${base_name}.smt2.vcd" ]; then
-            #         echo "VCD file ${base_name}.vcd generated successfully by Python."
+		if [ -f "${base_name}.smt2.vcd" ]; then
+                    echo "VCD file ${base_name}.vcd generated successfully by Python."
 
-            #         if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys.vcd -r ${base_name}.smt2.vcd -scope gold -timescale 1us"; then
-	    # 		echo "Yosys simulation for $rtlil_file completed successfully."
-	    # 		smt_successful_files["$rtlil_file"]="Success"
-            #         else
-	    # 		echo "Yosys simulation failed for $rtlil_file."
-	    # 		smt_failing_files["$rtlil_file"]="Yosys simulation failure"
-            #         fi
-	    # 	else
-		    
-            #         echo "Failed to generate VCD file (${base_name}.vcd) for $rtlil_file. "
-            #         smt_failing_files["$rtlil_file"]="VCD generation failure"
-	    # 	fi
-            # else
-	    # 	echo "Failed to run Python script for $rtlil_file."
-	    # 	smt_failing_files["$rtlil_file"]="Python script failure"
-	    # fi
+                    if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys.vcd -r ${base_name}.smt2.vcd -scope gold -timescale 1us"; then
+			echo "Yosys simulation for $rtlil_file completed successfully."
+			smt_successful_files["$rtlil_file"]="Success"
+                    else
+			echo "Yosys simulation failed for $rtlil_file."
+			smt_failing_files["$rtlil_file"]="Yosys simulation failure"
+                    fi
+		else		    
+                    echo "Failed to generate VCD file (${base_name}.vcd) for $rtlil_file. "
+                    smt_failing_files["$rtlil_file"]="VCD generation failure"
+		fi
+            else
+		echo "Failed to run Python script for $rtlil_file."
+		smt_failing_files["$rtlil_file"]="Python script failure"
+	    fi
 	else
 	    echo "SMT file for $rtlil_file is invalid"
 	    smt_failing_files["$rtlil_file"]="Invalid SMT"
diff --git a/tests/functional/single_cells/vcd_harness_smt.py b/tests/functional/single_cells/vcd_harness_smt.py
new file mode 100644
index 00000000000..a44bf4570c9
--- /dev/null
+++ b/tests/functional/single_cells/vcd_harness_smt.py
@@ -0,0 +1,199 @@
+import sys
+import argparse
+import random
+import os
+
+# Parse command line arguments
+parser = argparse.ArgumentParser(description='Process SMT file for simulation.')
+parser.add_argument('smt_file', help='Path to the SMT file to simulate.')
+args = parser.parse_args()
+
+# Get the SMT file path from the command line argument
+smt_file_path = args.smt_file
+current_file_path = os.path.abspath(__file__)
+# Navigate to the directory you need relative to the current script
+# Assuming 'backends/smt2' is located three directories up from the current script
+desired_path = os.path.join(os.path.dirname(current_file_path), '..', '..', '..', 'backends', 'functional')
+
+# Normalize the path to resolve any '..'
+normalized_path = os.path.normpath(desired_path)
+
+# Append the directory to the Python path
+sys.path.append(normalized_path)
+
+# Import the module
+import smtio
+
+# Assuming the SmtIo class and other dependencies are available in your environment
+# You may need to include the entire script provided above in your script or have it available as a module
+
+# Step 1: Initialize an SmtIo object
+
+so = smtio.SmtOpts()
+so.solver = "z3"
+so.logic = "BV"
+so.debug_print = True
+# so.debug_file = "my_debug"
+smt_io = smtio.SmtIo(opts=so)
+# List to store the parsed results
+parsed_results = []
+
+# Load and execute the SMT file
+with open(smt_file_path, 'r') as smt_file:
+    for line in smt_file:
+        smt_io.write(line.strip())
+smt_io.check_sat()
+# Read and parse the SMT file line by line
+with open(smt_file_path, 'r') as smt_file:
+    for line in smt_file:
+        # Strip leading/trailing whitespace
+        stripped_line = line.strip()
+        
+        # Ignore empty lines
+        if not stripped_line:
+            continue
+        # comments
+        if stripped_line.startswith(';'):
+            smt_io.info(stripped_line)
+        
+        # Parse the line using SmtIo's parse method
+        parsed_line = smt_io.parse(stripped_line)
+        
+        # Append the parsed result to the list
+        parsed_results.append(parsed_line)
+
+# Display the parsed results
+for result in parsed_results:
+    print(result)
+
+inputs = {}
+outputs = {}
+
+for lst in parsed_results:
+    if lst[0] == 'declare-datatypes':
+        for datatype_group in lst[2]:  # Navigate into the nested lists
+            datatype_name = datatype_group[0]
+            declarations = datatype_group[1][1:]  # Skip the first item (e.g., 'mk_inputs')
+            if datatype_name == 'Inputs':
+                for declaration in declarations:
+                    input_name = declaration[0]
+                    bitvec_size = declaration[1][2]
+                    inputs[input_name] = int(bitvec_size)
+            elif datatype_name == 'Outputs':
+                for declaration in declarations:
+                    output_name = declaration[0]
+                    bitvec_size = declaration[1][2]
+                    outputs[output_name] = int(bitvec_size)
+    
+print(inputs)
+print(outputs)
+def set_step(inputs, step):
+    # This function assumes 'inputs' is a dictionary like {"A": 5, "B": 4}
+    # and 'input_values' is a dictionary like {"A": 5, "B": 13} specifying the concrete values for each input.
+    
+    # Construct input definitions
+    mk_inputs_parts = []
+    for input_name, width in inputs.items():
+        value = random.getrandbits(width)  # Generate a random number up to the maximum value for the bit size
+        binary_string = format(value, '0{}b'.format(width))  # Convert value to binary with leading zeros
+        mk_inputs_parts.append(f"#b{binary_string}")
+
+    # Join all parts for the mk_inputs constructor
+    mk_inputs_call = "mk_inputs " + " ".join(mk_inputs_parts)
+    define_inputs = f"(define-const test_inputs_step_n{step} Inputs ({mk_inputs_call}))\n"
+
+    # Create the output definition by calling the gold_step function
+    define_output = f"(define-const test_outputs_step_n{step} Outputs (gold_step #b0 test_inputs_step_n{step}))\n"
+    smt_commands = []
+    smt_commands.append(define_inputs)
+    smt_commands.append(define_output)
+    return smt_commands
+
+num_steps = 10
+smt_commands = []
+# Loop to generate SMT commands for each step
+for step in range(num_steps):
+    for step_command in set_step(inputs, step):
+        smt_commands.append(step_command)
+
+# Print or write the SMT commands to a file
+smt_file_content = ''.join(smt_commands)
+print(smt_file_content)  # Print to console
+
+# Optionally, write to a file
+with open('dynamic_commands.smt2', 'w') as smt_file:
+    smt_file.write(smt_file_content)
+
+# Execute the SMT commands
+for command in smt_commands:
+    print(command)
+    smt_io.write(command.strip())
+
+# Check for satisfiability
+# smt_io.setup()
+result = smt_io.check_sat()
+print(f'SAT result: {result}')
+
+value = smt_io.get(f'(Y test_outputs_step_n0)')
+print(f"  Y: {value}")
+
+# Store signal values
+signals = {name: [] for name in list(inputs.keys()) + list(outputs.keys())}
+# Retrieve and print values for each state
+def hex_to_bin(value):
+    if value.startswith('x'):
+        hex_value = value[1:]  # Remove the 'x' prefix
+        bin_value = bin(int(hex_value, 16))[2:]  # Convert to binary and remove the '0b' prefix
+        return f'b{bin_value.zfill(len(hex_value) * 4)}'  # Add 'b' prefix and pad with zeros
+    return value
+for step in range(num_steps):
+    print(f"Values for step {step + 1}:")
+    for input_name, width in inputs.items():
+        value = smt_io.get(f'({input_name} test_inputs_step_n{step})')
+        value = hex_to_bin(value[1:])
+        print(f"  {input_name}: {value}")        
+        signals[input_name].append((step, value))
+    for output_name, width in outputs.items():
+        value = smt_io.get(f'({output_name} test_outputs_step_n{step})')
+        value = hex_to_bin(value[1:])
+        print(f"  {output_name}: {value}")
+        signals[output_name].append((step, value))
+        
+smt_io.p_close()
+
+def write_vcd(filename, signals, timescale='1 ns', date='today'):
+    with open(filename, 'w') as f:
+        # Write the header
+        f.write(f"$date\n    {date}\n$end\n")
+        f.write(f"$timescale {timescale} $end\n")
+        
+        # Declare signals
+        f.write("$scope module gold $end\n")
+        for signal_name, changes in signals.items():
+            signal_size = len(changes[0][1])
+            f.write(f"$var wire {signal_size - 1} {signal_name} {signal_name} $end\n")
+        f.write("$upscope $end\n")
+        f.write("$enddefinitions $end\n")
+        
+        # Collect all unique timestamps
+        timestamps = sorted(set(time for changes in signals.values() for time, _ in changes))
+        
+        # Write initial values
+        f.write("#0\n")
+        for signal_name, changes in signals.items():
+            for time, value in changes:
+                if time == 0:
+                    f.write(f"{value} {signal_name}\n")
+        
+        # Write value changes
+        for time in timestamps:
+            if time != 0:
+                f.write(f"#{time}\n")
+                for signal_name, changes in signals.items():
+                    for change_time, value in changes:
+                        if change_time == time:
+                            f.write(f"b{value} {signal_name}\n")
+
+
+# Write the VCD file
+write_vcd(smt_file_path + '.vcd', signals)

From eb2bb8c45b462203b64e77c943d0e866eae3e85b Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 27 Jun 2024 13:16:57 +0100
Subject: [PATCH 385/499] tidy up generic functional backend, add generic scope
 class, tidy up c++ functional backend

---
 backends/functional/cxx.cc | 178 ++++++++++++-------------------------
 kernel/functionalir.cc     |  44 +++++----
 kernel/functionalir.h      |  82 ++++++++++++-----
 3 files changed, 149 insertions(+), 155 deletions(-)

diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index 9571385ccb3..5f63a06153b 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -23,6 +23,7 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+const char illegal_characters[] = "!\"#%&'()*+,-./:;<=>?@[]\\^`{|}~ ";
 const char *reserved_keywords[] = {
 	"alignas","alignof","and","and_eq","asm","atomic_cancel","atomic_commit",
 	"atomic_noexcept","auto","bitand","bitor","bool","break","case",
@@ -41,45 +42,6 @@ const char *reserved_keywords[] = {
 	nullptr
 };
 
-struct CxxScope {
-	pool<std::string> used_names;
-	dict<IdString, std::string> name_map;
-
-	CxxScope() {
-		for(const char **p = reserved_keywords; *p != nullptr; p++)
-			reserve(*p);
-	}
-	void reserve(std::string name) {
-		used_names.insert(name);
-	}
-	std::string insert(IdString id) {
-		std::string str = RTLIL::unescape_id(id);
-		for(size_t i = 0; i < str.size(); i++)
-			if(strchr("!\"#%&'()*+,-./:;<=>?@[]\\^`{|}~ ", str[i]))
-				str[i] = '_';
-		if(used_names.count(str) == 0){
-			used_names.insert(str);
-			name_map.insert({id, str});
-			return str;
-		}
-		for (int idx = 0 ; ; idx++){
-			std::string suffixed = str + "_" + std::to_string(idx);
-			if (used_names.count(suffixed) == 0) {
-				used_names.insert(suffixed);
-				if(name_map.count(id) == 0)
-					name_map.insert({id, suffixed});
-				return suffixed;
-			}
-		}
-	}
-	std::string operator[](IdString id) {
-		if(name_map.count(id) > 0)
-			return name_map[id];
-		else
-			return insert(id);
-	}
-};
-
 struct CxxType {
 	FunctionalIR::Sort sort;
 	CxxType(FunctionalIR::Sort sort) : sort(sort) {}
@@ -109,66 +71,30 @@ struct CxxWriter {
 struct CxxStruct {
   std::string name;
   dict<IdString, CxxType> types;
-  CxxScope scope;
-  bool generate_methods;
-  CxxStruct(std::string name, bool generate_methods = false)
-    : name(name), generate_methods(generate_methods) {
+  FunctionalTools::Scope scope;
+  CxxStruct(std::string name)
+    : name(name), scope(illegal_characters, reserved_keywords) {
     scope.reserve("out");
     scope.reserve("dump");
   }
   void insert(IdString name, CxxType type) {
-    scope.insert(name);
+    scope(name);
     types.insert({name, type});
   }
   void print(CxxWriter &f) {
-    f.printf("struct %s {\n", name.c_str());
+    f.printf("\tstruct %s {\n", name.c_str());
     for (auto p : types) {
-      f.printf("\t%s %s;\n", p.second.to_string().c_str(), scope[p.first].c_str());
+      f.printf("\t\t%s %s;\n", p.second.to_string().c_str(), scope(p.first).c_str());
     }
-    f.printf("\n\ttemplate <typename T> void dump(T &out) const {\n");
+    f.printf("\n\t\ttemplate <typename T> void visit(T &fn) {\n");
     for (auto p : types) {
-      f.printf("\t\tout(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope[p.first].c_str());
-    }
-    f.printf("\t}\n\n");
-
-    if (generate_methods) {
-      // Add size method
-      f.printf("\tint size() const {\n");
-      f.printf("\t\treturn %d;\n", types.size());
-      f.printf("\t}\n\n");
-
-      // Add get_input method
-      f.printf("\tstd::variant<%s> get_input(const int index) {\n", generate_variant_types().c_str());
-      f.printf("\t\tswitch (index) {\n");
-      int idx = 0;
-      for (auto p : types) {
-	f.printf("\t\t\tcase %d: return std::ref(%s);\n", idx, scope[p.first].c_str());
-	idx++;
-      }
-      f.printf("\t\t\tdefault: throw std::out_of_range(\"Invalid input index\");\n");
-      f.printf("\t\t}\n");
-      f.printf("\t}\n");
+      f.printf("\t\t\tfn(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope(p.first).c_str());
     }
-    
-    f.printf("};\n\n");
+    f.printf("\t\t}\n");
+    f.printf("\t};\n\n");
   };
   std::string operator[](IdString field) {
-    return scope[field];
-  }
-  private:
-  std::string generate_variant_types() const {
-        std::set<std::string> unique_types;
-        for (const auto& p : types) {
-            unique_types.insert("std::reference_wrapper<" + p.second.to_string() + ">");
-        }
-        std::ostringstream oss;
-        for (auto it = unique_types.begin(); it != unique_types.end(); ++it) {
-            if (it != unique_types.begin()) {
-                oss << ", ";
-            }
-            oss << *it;
-        }
-        return oss.str();
+    return scope(field);
   }
 };
 
@@ -255,58 +181,72 @@ template<class NodeNames> struct CxxPrintVisitor {
 	std::string undriven(Node, int width) { return format("$const<%0>(0)", width); }
 };
 
-struct FunctionalCxxBackend : public Backend
-{
-	FunctionalCxxBackend() : Backend("functional_cxx", "convert design to C++ using the functional backend") {}
+struct CxxModule {
+	FunctionalIR ir;
+	CxxStruct input_struct, output_struct, state_struct;
+	std::string module_name;
 
-    void help() override
+	explicit CxxModule(Module *module) :
+		ir(FunctionalIR::from_module(module)),
+		input_struct("Inputs"),
+		output_struct("Outputs"),
+		state_struct("State")
 	{
-		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-		log("\n");
-    }
-
-	void printCxx(std::ostream &stream, std::string, std::string const & name, Module *module)
-	{
-		auto ir = FunctionalIR::from_module(module);
-		CxxWriter f(stream);
-
-		f.printf("#include \"sim.h\"\n");
-		f.printf("#include <variant>\n");
-		CxxStruct input_struct(name + "_Inputs", true);
 		for (auto [name, sort] : ir.inputs())
 			input_struct.insert(name, sort);
-		CxxStruct output_struct(name + "_Outputs");
 		for (auto [name, sort] : ir.outputs())
 			output_struct.insert(name, sort);
-		CxxStruct state_struct(name + "_State");
 		for (auto [name, sort] : ir.state())
 			state_struct.insert(name, sort);
-
-		dict<int, std::string> node_names;
-		CxxScope locals;
-
+		module_name = FunctionalTools::Scope(illegal_characters, reserved_keywords)(module->name);
+	}
+	void write_header(CxxWriter &f) {
+		f.printf("#include \"sim.h\"\n\n");
+	}
+	void write_struct_def(CxxWriter &f) {
+		f.printf("struct %s {\n", module_name.c_str());
 		input_struct.print(f);
 		output_struct.print(f);
 		state_struct.print(f);
-
-		f.printf("void %s(%s_Inputs const &input, %s_Outputs &output, %s_State const &current_state, %s_State &next_state)\n{\n", name.c_str(), name.c_str(), name.c_str(), name.c_str(), name.c_str());
+		f.printf("\tstatic void eval(Inputs const &, Outputs &, State const &, State &);\n");
+		f.printf("};\n\n");
+	}
+	void write_eval_def(CxxWriter &f) {
+		f.printf("void %s::eval(%s::Inputs const &input, %s::Outputs &output, %s::State const &current_state, %s::State &next_state)\n{\n", module_name.c_str(), module_name.c_str(), module_name.c_str(), module_name.c_str(), module_name.c_str());
+		FunctionalTools::Scope locals(illegal_characters, reserved_keywords);
 		locals.reserve("input");
 		locals.reserve("output");
 		locals.reserve("current_state");
 		locals.reserve("next_state");
-		auto node_to_string = [&](FunctionalIR::Node n) { return node_names.at(n.id()); };
+		auto node_name = [&](FunctionalIR::Node n) { return locals(n.id(), n.name()); };
 		for (auto node : ir)
-		{
-			std::string name = locals.insert(node.name());
-			node_names.emplace(node.id(), name);
-			f.printf("\t%s %s = %s;\n", CxxType(node.sort()).to_string().c_str(), name.c_str(), node.visit(CxxPrintVisitor(node_to_string, input_struct, state_struct)).c_str());
-		}
+			f.printf("\t%s %s = %s;\n", CxxType(node.sort()).to_string().c_str(), node_name(node).c_str(), node.visit(CxxPrintVisitor(node_name, input_struct, state_struct)).c_str());
 		for (auto [name, sort] : ir.state())
-			f.printf("\tnext_state.%s = %s;\n", state_struct[name].c_str(), node_to_string(ir.get_state_next_node(name)).c_str());
+			f.printf("\tnext_state.%s = %s;\n", state_struct[name].c_str(), node_name(ir.get_state_next_node(name)).c_str());
 		for (auto [name, sort] : ir.outputs())
-			f.printf("\toutput.%s = %s;\n", output_struct[name].c_str(), node_to_string(ir.get_output_node(name)).c_str());
+			f.printf("\toutput.%s = %s;\n", output_struct[name].c_str(), node_name(ir.get_output_node(name)).c_str());
 		f.printf("}\n");
 	}
+};
+
+struct FunctionalCxxBackend : public Backend
+{
+	FunctionalCxxBackend() : Backend("functional_cxx", "convert design to C++ using the functional backend") {}
+
+    void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+    }
+
+	void printCxx(std::ostream &stream, std::string, Module *module)
+	{
+		CxxWriter f(stream);
+		CxxModule mod(module);
+		mod.write_header(f);
+		mod.write_struct_def(f);
+		mod.write_eval_def(f);
+	}
 
 	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
 	{
@@ -317,7 +257,7 @@ struct FunctionalCxxBackend : public Backend
 
 		for (auto module : design->selected_modules()) {
             log("Dumping module `%s'.\n", module->name.c_str());
-			printCxx(*f, filename, RTLIL::unescape_id(module->name), module);
+			printCxx(*f, filename, module);
 		}
 	}
 } FunctionalCxxBackend;
diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc
index 27765ac26c5..6ae66d6802b 100644
--- a/kernel/functionalir.cc
+++ b/kernel/functionalir.cc
@@ -33,7 +33,7 @@ class CellSimplifier {
 		} else {
 			reduced_b_width = new_width;
 			T lower_b = factory.slice(b, b_width, 0, new_width);
-			T overflow = factory.ugt(b, factory.constant(RTLIL::Const(y_width, b_width)), b_width);
+			T overflow = factory.unsigned_greater_than(b, factory.constant(RTLIL::Const(y_width, b_width)), b_width);
 			return factory.mux(lower_b, factory.constant(RTLIL::Const(y_width, new_width)), overflow, new_width);
 		}
 	}
@@ -102,17 +102,17 @@ class CellSimplifier {
 			T a = extend(inputs.at(ID(A)), a_width, width, is_signed);
 			T b = extend(inputs.at(ID(B)), b_width, width, is_signed);
 			if(cellType.in({ID($eq), ID($eqx)}))
-				return extend(factory.eq(a, b, width), 1, y_width, false);
+				return extend(factory.equal(a, b, width), 1, y_width, false);
 			else if(cellType.in({ID($ne), ID($nex)}))
-				return extend(factory.ne(a, b, width), 1, y_width, false);
+				return extend(factory.not_equal(a, b, width), 1, y_width, false);
 			else if(cellType == ID($lt))
-				return extend(is_signed ? factory.gt(b, a, width) : factory.ugt(b, a, width), 1, y_width, false);
+				return extend(is_signed ? factory.signed_greater_than(b, a, width) : factory.unsigned_greater_than(b, a, width), 1, y_width, false);
 			else if(cellType == ID($le))
-				return extend(is_signed ? factory.ge(b, a, width) : factory.uge(b, a, width), 1, y_width, false);
+				return extend(is_signed ? factory.signed_greater_equal(b, a, width) : factory.unsigned_greater_equal(b, a, width), 1, y_width, false);
 			else if(cellType == ID($gt))
-				return extend(is_signed ? factory.gt(a, b, width) : factory.ugt(a, b, width), 1, y_width, false);
+				return extend(is_signed ? factory.signed_greater_than(a, b, width) : factory.unsigned_greater_than(a, b, width), 1, y_width, false);
 			else if(cellType == ID($ge))
-				return extend(is_signed ? factory.ge(a, b, width) : factory.uge(a, b, width), 1, y_width, false);
+				return extend(is_signed ? factory.signed_greater_equal(a, b, width) : factory.unsigned_greater_equal(a, b, width), 1, y_width, false);
 			else
 				log_abort();
 		}else if(cellType.in({ID($logic_or), ID($logic_and)})){
@@ -127,7 +127,7 @@ class CellSimplifier {
 			return extend(inputs.at(ID(A)), a_width, y_width, a_signed);
 		}else if(cellType == ID($neg)){
 			T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed);
-			return factory.neg(a, y_width);
+			return factory.unary_minus(a, y_width);
 		}else if(cellType == ID($logic_not)){
 			T a = reduce_or(inputs.at(ID(A)), a_width);
 			T y = factory.bitwise_not(a, 1);
@@ -161,7 +161,7 @@ class CellSimplifier {
 			T shr = logical_shift_right(a, b, width, b_width);
 			if(b_signed) {
 				T sign_b = factory.slice(b, b_width, b_width - 1, 1);
-				T shl = logical_shift_left(a, factory.neg(b, b_width), width, b_width);
+				T shl = logical_shift_left(a, factory.unary_minus(b, b_width), width, b_width);
 				T y = factory.mux(shr, shl, sign_b, width);
 				return extend(y, width, y_width, false);
 			} else {
@@ -237,10 +237,10 @@ class FunctionalIRConstruction {
 		if(results.size() == 0)
 			return factory.undriven(0);
 		T node = results[0];
-		int size = results[0].size();
+		int size = results[0].width();
 		for(size_t i = 1; i < results.size(); i++) {
-			node = factory.concat(node, size, results[i], results[i].size());
-			size += results[i].size();
+			node = factory.concat(node, size, results[i], results[i].width());
+			size += results[i].width();
 		}
 		return node;
 	}
@@ -405,6 +405,13 @@ void FunctionalIR::topological_sort() {
     if(scc) log_error("combinational loops, aborting\n");
 }
 
+IdString merge_name(IdString a, IdString b) {
+	if(a[0] == '$' && b[0] == '\\')
+		return b;
+	else
+		return a;
+}
+
 void FunctionalIR::forward_buf() {
     std::vector<int> perm, alias;
     perm.clear();
@@ -416,10 +423,15 @@ void FunctionalIR::forward_buf() {
         {
             int target_index = alias[node.arg(0).index()];
             auto target_node = _graph[perm[target_index]];
-            if(!target_node.has_sparse_attr() && node.has_sparse_attr()){
-                IdString id = node.sparse_attr();
-                target_node.sparse_attr() = id;
-            }
+			if(node.has_sparse_attr()) {
+				if(target_node.has_sparse_attr()) {
+					IdString id = merge_name(node.sparse_attr(), target_node.sparse_attr());
+					target_node.sparse_attr() = id;
+				} else {
+					IdString id = node.sparse_attr();
+					target_node.sparse_attr() = id;
+				}
+			}
             alias.push_back(target_index);
         }
         else
diff --git a/kernel/functionalir.h b/kernel/functionalir.h
index 7eca9d87f83..f49a659f37b 100644
--- a/kernel/functionalir.h
+++ b/kernel/functionalir.h
@@ -29,6 +29,58 @@
 USING_YOSYS_NAMESPACE
 YOSYS_NAMESPACE_BEGIN
 
+namespace FunctionalTools {
+	class Scope {
+		const char *_illegal_characters;
+		pool<std::string> _used_names;
+		dict<int, std::string> _by_id;
+		dict<IdString, std::string> _by_name;
+		std::string allocate_name(IdString suggestion) {
+			std::string str = RTLIL::unescape_id(suggestion);
+			for(size_t i = 0; i < str.size(); i++)
+				if(strchr(_illegal_characters, str[i]))
+					str[i] = '_';
+			if(_used_names.count(str) == 0) {
+				_used_names.insert(str);
+				return str;
+			}
+			for (int idx = 0 ; ; idx++){
+				std::string suffixed = str + "_" + std::to_string(idx);
+				if(_used_names.count(suffixed) == 0) {
+					_used_names.insert(suffixed);
+					return suffixed;
+				}
+			}
+		}
+	public:
+		Scope(const char *illegal_characters = "", const char **keywords = nullptr) {
+			_illegal_characters = illegal_characters;
+			if(keywords != nullptr)
+				for(const char **p = keywords; *p != nullptr; p++)
+					reserve(*p);
+		}
+		void reserve(std::string name) {
+			_used_names.insert(std::move(name));
+		}
+		std::string operator()(int id, IdString suggestion) {
+			auto it = _by_id.find(id);
+			if(it != _by_id.end())
+				return it->second;
+			std::string str = allocate_name(suggestion);
+			_by_id.insert({id, str});
+			return str;
+		}
+		std::string operator()(IdString idstring) {
+			auto it = _by_name.find(idstring);
+			if(it != _by_name.end())
+				return it->second;
+			std::string str = allocate_name(idstring);
+			_by_name.insert({idstring, str});
+			return str;
+		}
+	};
+}
+
 class FunctionalIR {
 	enum class Fn {
 		invalid,
@@ -133,7 +185,7 @@ class FunctionalIR {
 		friend class Factory;
 		friend class FunctionalIR;
 		Graph::Ref _ref;
-		Node(Graph::Ref ref) : _ref(ref) { }
+		explicit Node(Graph::Ref ref) : _ref(ref) { }
 		operator Graph::Ref() { return _ref; }
 		template<class NodePrinter> struct PrintVisitor {
 			NodePrinter np;
@@ -225,7 +277,6 @@ class FunctionalIR {
 		{
 			return visit(PrintVisitor(np));
 		}
-		/* TODO: delete */ int size() const { return sort().width(); }
 	};
 	class Factory {
 		FunctionalIR &_ir;
@@ -235,7 +286,7 @@ class FunctionalIR {
 			Graph::Ref ref = _ir._graph.add(std::move(fn), {std::move(sort)});
 			for (auto arg : args)
 				ref.append_arg(Graph::Ref(arg));
-			return ref;
+			return Node(ref);
 		}
 		void check_basic_binary(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && a.sort() == b.sort()); }
 		void check_shift(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && b.sort().is_signal()); }
@@ -341,39 +392,30 @@ class FunctionalIR {
 		void suggest_name(Node node, IdString name) {
 			node._ref.sparse_attr() = name;
 		}
-
-		/* TODO delete this later*/
-		Node eq(Node a, Node b, int) { return equal(a, b, 0); }
-		Node ne(Node a, Node b, int) { return not_equal(a, b, 0); }
-		Node gt(Node a, Node b, int) { return signed_greater_than(a, b, 0); }
-		Node ge(Node a, Node b, int) { return signed_greater_equal(a, b, 0); }
-		Node ugt(Node a, Node b, int) { return unsigned_greater_than(a, b, 0); }
-		Node uge(Node a, Node b, int) { return unsigned_greater_equal(a, b, 0); }
-		Node neg(Node a, int) { return unary_minus(a, 0); }
 	};
 	static FunctionalIR from_module(Module *module);
 	Factory factory() { return Factory(*this); }
 	int size() const { return _graph.size(); }
-	Node operator[](int i) { return _graph[i]; }
+	Node operator[](int i) { return Node(_graph[i]); }
 	void topological_sort();
 	void forward_buf();
 	dict<IdString, Sort> inputs() const { return _inputs; }
 	dict<IdString, Sort> outputs() const { return _outputs; }
 	dict<IdString, Sort> state() const { return _state; }
-	Node get_output_node(IdString name) { return _graph({name, false}); }
-	Node get_state_next_node(IdString name) { return _graph({name, true}); }
+	Node get_output_node(IdString name) { return Node(_graph({name, false})); }
+	Node get_state_next_node(IdString name) { return Node(_graph({name, true})); }
 	class Iterator {
 		friend class FunctionalIR;
-		FunctionalIR &_ir;
+		FunctionalIR *_ir;
 		int _index;
-		Iterator(FunctionalIR &ir, int index) : _ir(ir), _index(index) {}
+		Iterator(FunctionalIR *ir, int index) : _ir(ir), _index(index) {}
 	public:
-		Node operator*() { return _ir._graph[_index]; }
+		Node operator*() { return Node(_ir->_graph[_index]); }
 		Iterator &operator++() { _index++; return *this; }
 		bool operator!=(Iterator const &other) const { return _index != other._index; }
 	};
-	Iterator begin() { return Iterator(*this, 0); }
-	Iterator end() { return Iterator(*this, _graph.size()); }
+	Iterator begin() { return Iterator(this, 0); }
+	Iterator end() { return Iterator(this, _graph.size()); }
 };
 
 YOSYS_NAMESPACE_END

From 21bb1cf1bc0383af88c58b0ddfa20db18ecbac27 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 27 Jun 2024 15:43:57 +0100
Subject: [PATCH 386/499] rewrite functional c++ simulation library

---
 backends/functional/cxx.cc                   |  60 +-
 backends/functional/cxx_runtime/sim.h        | 624 +++++++++----------
 tests/functional/single_cells/vcd_harness.cc |  77 ++-
 3 files changed, 364 insertions(+), 397 deletions(-)

diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index 5f63a06153b..d866dfea210 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -86,7 +86,7 @@ struct CxxStruct {
     for (auto p : types) {
       f.printf("\t\t%s %s;\n", p.second.to_string().c_str(), scope(p.first).c_str());
     }
-    f.printf("\n\t\ttemplate <typename T> void visit(T &fn) {\n");
+    f.printf("\n\t\ttemplate <typename T> void visit(T &&fn) {\n");
     for (auto p : types) {
       f.printf("\t\t\tfn(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope(p.first).c_str());
     }
@@ -148,37 +148,37 @@ template<class NodeNames> struct CxxPrintVisitor {
 		return CxxTemplate::format(fmt, arg_to_string(args)...);
 	}
 	std::string buf(Node, Node n) { return np(n); }
-	std::string slice(Node, Node a, int, int offset, int out_width) { return format("slice<%2>(%0, %1)", a, offset, out_width); }
-	std::string zero_extend(Node, Node a, int, int out_width) { return format("$zero_extend<%1>(%0)", a, out_width); }
-	std::string sign_extend(Node, Node a, int, int out_width) { return format("$sign_extend<%1>(%0)", a, out_width); }
-	std::string concat(Node, Node a, int, Node b, int) { return format("concat(%0, %1)", a, b); }
-	std::string add(Node, Node a, Node b, int) { return format("$add(%0, %1)", a, b); }
-	std::string sub(Node, Node a, Node b, int) { return format("$sub(%0, %1)", a, b); }
-	std::string bitwise_and(Node, Node a, Node b, int) { return format("$and(%0, %1)", a, b); }
-	std::string bitwise_or(Node, Node a, Node b, int) { return format("$or(%0, %1)", a, b); }
-	std::string bitwise_xor(Node, Node a, Node b, int) { return format("$xor(%0, %1)", a, b); }
-	std::string bitwise_not(Node, Node a, int) { return format("$not(%0)", a); }
-	std::string unary_minus(Node, Node a, int) { return format("$neg(%0)", a); }
-	std::string reduce_and(Node, Node a, int) { return format("$reduce_and(%0)", a); }
-	std::string reduce_or(Node, Node a, int) { return format("$reduce_or(%0)", a); }
-	std::string reduce_xor(Node, Node a, int) { return format("$reduce_xor(%0)", a); }
-	std::string equal(Node, Node a, Node b, int) { return format("$eq(%0, %1)", a, b); }
-	std::string not_equal(Node, Node a, Node b, int) { return format("$ne(%0, %1)", a, b); }
-	std::string signed_greater_than(Node, Node a, Node b, int) { return format("$gt(%0, %1)", a, b); }
-	std::string signed_greater_equal(Node, Node a, Node b, int) { return format("$ge(%0, %1)", a, b); }
-	std::string unsigned_greater_than(Node, Node a, Node b, int) { return format("$ugt(%0, %1)", a, b); }
-	std::string unsigned_greater_equal(Node, Node a, Node b, int) { return format("$uge(%0, %1)", a, b); }
-	std::string logical_shift_left(Node, Node a, Node b, int, int) { return format("$shl<%2>(%0, %1)", a, b, a.width()); }
-	std::string logical_shift_right(Node, Node a, Node b, int, int) { return format("$shr<%2>(%0, %1)", a, b, a.width()); }
-	std::string arithmetic_shift_right(Node, Node a, Node b, int, int) { return format("$asr<%2>(%0, %1)", a, b, a.width()); }
-	std::string mux(Node, Node a, Node b, Node s, int) { return format("$mux(%0, %1, %2)", a, b, s); }
-	std::string pmux(Node, Node a, Node b, Node s, int, int) { return format("$pmux(%0, %1, %2)", a, b, s); }
-	std::string constant(Node, RTLIL::Const value) { return format("$const<%0>(%1)", value.size(), value.as_int()); }
+	std::string slice(Node, Node a, int, int offset, int out_width) { return format("%0.slice<%2>(%1)", a, offset, out_width); }
+	std::string zero_extend(Node, Node a, int, int out_width) { return format("%0.zero_extend<%1>()", a, out_width); }
+	std::string sign_extend(Node, Node a, int, int out_width) { return format("%0.sign_extend<%1>()", a, out_width); }
+	std::string concat(Node, Node a, int, Node b, int) { return format("%0.concat(%1)", a, b); }
+	std::string add(Node, Node a, Node b, int) { return format("%0 + %1", a, b); }
+	std::string sub(Node, Node a, Node b, int) { return format("%0 - %1", a, b); }
+	std::string bitwise_and(Node, Node a, Node b, int) { return format("%0 & %1", a, b); }
+	std::string bitwise_or(Node, Node a, Node b, int) { return format("%0 | %1", a, b); }
+	std::string bitwise_xor(Node, Node a, Node b, int) { return format("%0 ^ %1", a, b); }
+	std::string bitwise_not(Node, Node a, int) { return format("~%0", a); }
+	std::string unary_minus(Node, Node a, int) { return format("-%0", a); }
+	std::string reduce_and(Node, Node a, int) { return format("%0.all()", a); }
+	std::string reduce_or(Node, Node a, int) { return format("%0.any()", a); }
+	std::string reduce_xor(Node, Node a, int) { return format("%0.parity()", a); }
+	std::string equal(Node, Node a, Node b, int) { return format("%0 == %1", a, b); }
+	std::string not_equal(Node, Node a, Node b, int) { return format("%0 != %1", a, b); }
+	std::string signed_greater_than(Node, Node a, Node b, int) { return format("%0.signed_greater_than(%1)", a, b); }
+	std::string signed_greater_equal(Node, Node a, Node b, int) { return format("%0.signed_greater_equal(%1)", a, b); }
+	std::string unsigned_greater_than(Node, Node a, Node b, int) { return format("%0 > %1", a, b); }
+	std::string unsigned_greater_equal(Node, Node a, Node b, int) { return format("%0 >= %1", a, b); }
+	std::string logical_shift_left(Node, Node a, Node b, int, int) { return format("%0 << %1", a, b); }
+	std::string logical_shift_right(Node, Node a, Node b, int, int) { return format("%0 >> %1", a, b); }
+	std::string arithmetic_shift_right(Node, Node a, Node b, int, int) { return format("%0.arithmetic_shift_right(%1)", a, b); }
+	std::string mux(Node, Node a, Node b, Node s, int) { return format("%2.any() ? %1 : %0", a, b, s); }
+	std::string pmux(Node, Node a, Node b, Node s, int, int) { return format("%0.pmux(%1, %2)", a, b, s); }
+	std::string constant(Node, RTLIL::Const value) { return format("Signal<%0>(%1)", value.size(), value.as_int()); }
 	std::string input(Node, IdString name) { return format("input.%0", input_struct[name]); }
 	std::string state(Node, IdString name) { return format("current_state.%0", state_struct[name]); }
-	std::string memory_read(Node, Node mem, Node addr, int, int) { return format("$memory_read(%0, %1)", mem, addr); }
-	std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { return format("$memory_write(%0, %1, %2)", mem, addr, data); }
-	std::string undriven(Node, int width) { return format("$const<%0>(0)", width); }
+	std::string memory_read(Node, Node mem, Node addr, int, int) { return format("%0.read(%1)", mem, addr); }
+	std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { return format("%0.write(%1, %2)", mem, addr, data); }
+	std::string undriven(Node, int width) { return format("Signal<%0>(0)", width); }
 };
 
 struct CxxModule {
diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h
index 3a398a13a5a..0614fb34cf7 100644
--- a/backends/functional/cxx_runtime/sim.h
+++ b/backends/functional/cxx_runtime/sim.h
@@ -24,363 +24,333 @@
 #include <cassert>
 
 template<size_t n>
-using Signal = std::array<bool, n>;
+class Signal {
+    template<size_t m> friend class Signal;
+    std::array<bool, n> _bits;
+public:
+    Signal() { }
+    Signal(uint32_t val)
+    {
+        for(size_t i = 0; i < n; i++)
+            if(i < 32)
+                _bits[i] = val & (1<<i);
+            else
+                _bits[i] = false;
+    }
 
-template<size_t n, size_t m>
-Signal<n> slice(Signal<m> const& a, size_t offset)
-{
-    Signal<n> ret;
+    Signal(std::initializer_list<uint32_t> vals)
+    {
+        size_t k, i;
 
-    std::copy(a.begin() + offset, a.begin() + offset + n, ret.begin());
-    return ret;
-}
+        k = 0;
+        for (auto val : vals) {
+            for(i = 0; i < 32; i++)
+                if(i + k < n)
+                    _bits[i + k] = val & (1<<i);
+            k += 32;
+        }
+        for(; k < n; k++)
+            _bits[k] = false;
+    }
 
-template<size_t n>
-Signal<n> $const(uint32_t val)
-{
-    size_t i;
-    Signal<n> ret;
-
-    for(i = 0; i < n; i++)
-        if(i < 32)
-            ret[i] = val & (1<<i);
-        else
-            ret[i] = false;
-    return ret;
-}
+    template<typename T>
+    static Signal from_array(T vals)
+    {
+        size_t k, i;
+        Signal ret;
+
+        k = 0;
+        for (auto val : vals) {
+            for(i = 0; i < 32; i++)
+                if(i + k < n)
+                    ret._bits[i + k] = val & (1<<i);
+            k += 32;
+        }
+        for(; k < n; k++)
+            ret._bits[k] = false;
+        return ret;
+    }
 
-template<size_t n>
-Signal<n> $const(std::initializer_list<uint32_t> vals)
-{
-    size_t k, i;
-    Signal<n> ret;
-
-    k = 0;
-    for (auto val : vals) {
-        for(i = 0; i < 32; i++)
-            if(i + k < n)
-                ret[i + k] = val & (1<<i);
-        k += 32;
-    }
-    for(; k < n; k++)
-        ret[k] = false;
-    return ret;
-}
+    static Signal from_signed(int32_t val)
+    {
+        Signal<n> ret;
+        for(size_t i = 0; i < n; i++)
+            if(i < 32)
+                ret._bits[i] = val & (1<<i);
+            else
+                ret._bits[i] = val < 0;
+        return ret;
+    }
+    static Signal repeat(bool b)
+    {
+        Signal<n> ret;
+        for(size_t i = 0; i < n; i++)
+            ret._bits[i] = b;
+        return ret;
+    }
 
-template<size_t n>
-bool as_bool(Signal<n> sig)
-{
-    for(int i = 0; i < n; i++)
-        if(sig[i])
-            return true;
-    return false;
-}
+    int size() const { return n; }
+    bool operator[](int i) const { assert(n >= 0 && i < n); return _bits[i]; }
 
-template<size_t n>
-uint32_t as_int(Signal<n> sig)
-{
-    uint32_t ret = 0;
-    for(int i = 0; i < n; i++)
-        if(sig[i] && i < 32)
-            ret |= 1<<i;
-    return ret;
-}
+    template<size_t m>
+    Signal<m> slice(size_t offset) const
+    {
+        Signal<m> ret;
 
-template<size_t n>
-Signal<n> $mux(Signal<n> const& a, Signal<n> const &b, Signal<1> const &s)
-{
-    return s[0] ? b : a;
-}
+        assert(offset + m <= n);
+        std::copy(_bits.begin() + offset, _bits.begin() + offset + m, ret._bits.begin());
+        return ret;
+    }
 
-template<size_t n>
-Signal<n> $not(Signal<n> const& a)
-{
-    Signal<n> ret;
-    for(size_t i = 0; i < n; i++)
-        ret[i] = !a[i];
-    return ret;
-}
+    bool any() const
+    {
+        for(int i = 0; i < n; i++)
+            if(_bits[i])
+                return true;
+        return false;
+    }
 
-template<size_t n>
-Signal<n> $neg(Signal<n> const& a)
-{
-    Signal<n> ret;
-    bool carry = true;
-    for(size_t i = 0; i < n; i++) {
-        int r = !a[i] + carry;
-        ret[i] = (r & 1) != 0;
-        carry = (r >> 1) != 0;
-    }
-    return ret;
-}
+    bool all() const
+    {
+        for(int i = 0; i < n; i++)
+            if(!_bits[i])
+                return false;
+        return true;
+    }
 
-template<size_t n>
-Signal<1> $reduce_or(Signal<n> const& a)
-{
-    return { as_bool(a) };
-}
+    bool parity() const
+    {
+        bool result = false;
+        for(int i = 0; i < n; i++)
+            result ^= _bits[i];
+        return result;
+    }
 
-template<size_t n>
-Signal<1> $reduce_and(Signal<n> const& a)
-{
-    for(size_t i = 0; i < n; i++)
-        if(!a[i])
-            return { false };
-    return { true };
-}
+    bool sign() const { return _bits[n-1]; }
 
-template<size_t n>
-Signal<1> $reduce_bool(Signal<n> const& a)
-{
-    return { as_bool(a) };
-}
+    template<typename T>
+    T as_numeric() const
+    {
+        T ret = 0;
+        for(size_t i = 0; i < std::min<size_t>(sizeof(T) * 8, n); i++)
+            if(_bits[i])
+                ret |= ((T)1)<<i;
+        return ret;
+    }
 
-template<size_t n>
-Signal<1> $logic_and(Signal<n> const& a, Signal<n> const& b)
-{
-    return { as_bool(a) && as_bool(b) };
-}
+    template<typename T>
+    T as_numeric_clamped() const
+    {
+        for(size_t i = sizeof(T) * 8; i < n; i++)
+            if(_bits[i])
+                return ~0;
+        return as_numeric<T>();
+    }
 
-template<size_t n>
-Signal<1> $logic_or(Signal<n> const& a, Signal<n> const& b)
-{
-    return { as_bool(a) || as_bool(b) };
-}
+    uint32_t as_int() { return as_numeric<uint32_t>(); }
 
-template<size_t n>
-Signal<1> $logic_not(Signal<n> const& a)
-{
-    return { !as_bool(a) };
-}
+    Signal<n> operator ~() const
+    {
+        Signal<n> ret;
+        for(size_t i = 0; i < n; i++)
+            ret._bits[i] = !_bits[i];
+        return ret;
+    }
 
-template<size_t n>
-Signal<n> $add(Signal<n> const& a, Signal<n> const &b)
-{
-    Signal<n> ret;
-    size_t i;
-    int x = 0;
-    for(i = 0; i < n; i++){
-        x += (int)a[i] + (int)b[i];
-        ret[i] = x & 1;
-        x >>= 1;
-    }
-    return ret;
-}
-template<size_t n>
-Signal<n> $sub(Signal<n> const& a, Signal<n> const &b)
-{
-    Signal<n> ret;
-    int x = 1;
-    for(size_t i = 0; i < n; i++){
-        x += (int)a[i] + (int)!b[i];
-        ret[i] = x & 1;
-        x >>= 1;
-    }
-    return ret;
-}
+    Signal<n> operator -() const
+    {
+        Signal<n> ret;
+        bool carry = true;
+        for(size_t i = 0; i < n; i++) {
+            int r = !_bits[i] + carry;
+            ret._bits[i] = (r & 1) != 0;
+            carry = (r >> 1) != 0;
+        }
+        return ret;
+    }
 
-template<size_t n>
-Signal<1> $uge(Signal<n> const& a, Signal<n> const &b)
-{
-    for(size_t i = n; i-- != 0; )
-        if(a[i] != b[i])
-            return { a[i] };
-    return { true };
-}
+    Signal<n> operator +(Signal<n> const &b) const
+    {
+        Signal<n> ret;
+        size_t i;
+        int x = 0;
+        for(i = 0; i < n; i++){
+            x += (int)_bits[i] + (int)b._bits[i];
+            ret._bits[i] = x & 1;
+            x >>= 1;
+        }
+        return ret;
+    }
 
-template<size_t n>
-Signal<1> $ugt(Signal<n> const& a, Signal<n> const &b)
-{
-    for(size_t i = n; i-- != 0; )
-        if(a[i] != b[i])
-            return { a[i] };
-    return { false };
-}
+    Signal<n> operator -(Signal<n> const &b) const
+    {
+        Signal<n> ret;
+        int x = 1;
+        for(size_t i = 0; i < n; i++){
+            x += (int)_bits[i] + (int)!b._bits[i];
+            ret._bits[i] = x & 1;
+            x >>= 1;
+        }
+        return ret;
+    }
 
-template<size_t n>
-Signal<1> $ge(Signal<n> const& a, Signal<n> const &b)
-{
-    if(a[n-1] != b[n-1])
-        return { b[n-1] };
-    return $uge(a, b);
-}
+    bool operator ==(Signal<n> const &b) const
+    {
+        for(size_t i = 0; i < n; i++)
+            if(_bits[i] != b._bits[i])
+                return false;
+        return true;
+    }
 
-template<size_t n>
-Signal<1> $gt(Signal<n> const& a, Signal<n> const &b)
-{
-    if(a[n-1] != b[n-1])
-        return { b[n-1] };
-    return $ugt(a, b);
-}
-
-template<size_t n> Signal<1> $ule(Signal<n> const& a, Signal<n> const &b) { return $uge(b, a); }
-template<size_t n> Signal<1> $ult(Signal<n> const& a, Signal<n> const &b) { return $ugt(b, a); }
-template<size_t n> Signal<1> $le(Signal<n> const& a, Signal<n> const &b) { return $ge(b, a); }
-template<size_t n> Signal<1> $lt(Signal<n> const& a, Signal<n> const &b) { return $gt(b, a); }
+    bool operator >=(Signal<n> const &b) const
+    {
+        for(size_t i = n; i-- != 0; )
+            if(_bits[i] != b._bits[i])
+                return _bits[i];
+        return true;
+    }
 
-template<size_t n>
-Signal<n> $and(Signal<n> const& a, Signal<n> const &b)
-{
-    Signal<n> ret;
-    for(size_t i = 0; i < n; i++)
-        ret[i] = a[i] && b[i];
-    return ret;
-}
+    bool operator >(Signal<n> const &b) const
+    {
+        for(size_t i = n; i-- != 0; )
+            if(_bits[i] != b._bits[i])
+                return _bits[i];
+        return false;
+    }
 
-template<size_t n>
-Signal<n> $or(Signal<n> const& a, Signal<n> const &b)
-{
-    Signal<n> ret;
-    for(size_t i = 0; i < n; i++)
-        ret[i] = a[i] || b[i];
-    return ret;
-}
+    bool operator !=(Signal<n> const &b) const { return !(*this == b); }
+    bool operator <=(Signal<n> const &b) const { return b <= *this; }
+    bool operator <(Signal<n> const &b) const { return b < *this; }
 
-template<size_t n>
-Signal<n> $xor(Signal<n> const& a, Signal<n> const &b)
-{
-    Signal<n> ret;
-    for(size_t i = 0; i < n; i++)
-        ret[i] = a[i] != b[i];
-    return ret;
-}
-
-template<size_t n, size_t na, size_t nb>
-Signal<n> $shl(Signal<na> const& a, Signal<nb> const &b)
-{
-    if(nb >= sizeof(int) * 8 - 1)
-        for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
-            assert(!b[i]);
-    size_t amount = as_int(b);
-    Signal<n> ret = $const<n>(0);
-    if(amount < n){
-        if(amount + na > n)
-            std::copy(a.begin(), a.begin() + (n - amount), ret.begin() + amount);
-        else
-            std::copy(a.begin(), a.end(), ret.begin() + amount);
-    }
-    return ret;
-}
-
-template<size_t n, size_t nb>
-Signal<n> $shr(Signal<n> const& a, Signal<nb> const &b)
-{
-    if(nb >= sizeof(int) * 8 - 1)
-        for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
-            assert(!b[i]);
-    size_t amount = as_int(b);
-    Signal<n> ret;
-    for (size_t i = 0; i < n; i++) {
-        if(i + amount < n)
-            ret[i] = a[i + amount];
-        else
-            ret[i] = false;
-    }
-    return ret;
-}
-
-template<size_t n, size_t nb>
-Signal<n> $asr(Signal<n> const& a, Signal<nb> const &b)
-{
-    if(nb >= sizeof(int) * 8 - 1)
-        for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
-            assert(!b[i]);
-    size_t amount = as_int(b);
-    Signal<n> ret;
-    for (size_t i = 0; i < n; i++) {
-        if(i + amount < n)
-            ret[i] = a[i + amount];
-        else
-            ret[i] = a[n - 1];
-    }
-    return ret;
-}
+    bool signed_greater_than(Signal<n> const &b) const
+    {
+        if(_bits[n-1] != b._bits[n-1])
+            return b._bits[n-1];
+        return *this > b;
+    }
 
-template<size_t n>
-Signal<1> $eq(Signal<n> const& a, Signal<n> const &b)
-{
-    for(size_t i = 0; i < n; i++)
-        if(a[i] != b[i])
-            return { false };
-    return { true };
-}
+    bool signed_greater_equal(Signal<n> const &b) const
+    {
+        if(_bits[n-1] != b._bits[n-1])
+            return b._bits[n-1];
+        return *this >= b;
+    }
 
-template<size_t n>
-Signal<1> $ne(Signal<n> const& a, Signal<n> const &b)
-{
-    for(size_t i = 0; i < n; i++)
-        if(a[i] != b[i])
-            return { true };
-    return { false };
-}
-
-template<size_t n, size_t ns>
-Signal<n> $pmux(Signal<n> const& a, Signal<n*ns> const &b, Signal<ns> const &s)
-{
-    bool found;
-    Signal<n> ret;
-
-    found = false;
-    ret = a;
-    for(size_t i = 0; i < ns; i++){
-        if(s[i]){
-            if(found)
-                return $const<n>(0);
-            found = true;
-            ret = slice<n>(b, n * i);
+    Signal<n> operator &(Signal<n> const &b) const
+    {
+        Signal<n> ret;
+        for(size_t i = 0; i < n; i++)
+            ret._bits[i] = _bits[i] && b._bits[i];
+        return ret;
+    }
+
+    Signal<n> operator |(Signal<n> const &b) const
+    {
+        Signal<n> ret;
+        for(size_t i = 0; i < n; i++)
+            ret._bits[i] = _bits[i] || b._bits[i];
+        return ret;
+    }
+
+    Signal<n> operator ^(Signal<n> const &b) const
+    {
+        Signal<n> ret;
+        for(size_t i = 0; i < n; i++)
+            ret._bits[i] = _bits[i] != b._bits[i];
+        return ret;
+    }
+
+    template<size_t nb>
+    Signal<n> operator <<(Signal<nb> const &b) const
+    {
+        Signal<n> ret = 0;
+        size_t amount = b.template as_numeric_clamped<size_t>();
+        if(amount < n)
+            std::copy(_bits.begin(), _bits.begin() + (n - amount), ret._bits.begin() + amount);
+        return ret;
+    }
+
+    template<size_t nb>
+    Signal<n> operator >>(Signal<nb> const &b) const
+    {
+        Signal<n> ret = 0;
+        size_t amount = b.template as_numeric_clamped<size_t>();
+        if(amount < n)
+            std::copy(_bits.begin() + amount, _bits.end(), ret._bits.begin());
+        return ret;
+    }
+
+    template<size_t nb>
+    Signal<n> arithmetic_shift_right(Signal<nb> const &b) const
+    {
+        Signal<n> ret = Signal::repeat(sign());
+        size_t amount = b.template as_numeric_clamped<size_t>();
+        if(amount < n)
+            std::copy(_bits.begin() + amount, _bits.end(), ret._bits.begin());
+        return ret;
+    }
+
+    template<size_t ns>
+    Signal<n> pmux(Signal<n*ns> const &b, Signal<ns> const &s) const
+    {
+        bool found;
+        Signal<n> ret;
+
+        found = false;
+        ret = *this;
+        for(size_t i = 0; i < ns; i++){
+            if(s._bits[i]){
+                if(found)
+                    return 0;
+                found = true;
+                ret = b.template slice<n>(n * i);
+            }
         }
+        return ret;
     }
-    return ret;
-}
-
-template<size_t n, size_t m>
-Signal<n+m> concat(Signal<n> const& a, Signal<m> const& b)
-{
-    Signal<n + m> ret;
-    std::copy(a.begin(), a.end(), ret.begin());
-    std::copy(b.begin(), b.end(), ret.begin() + n);
-    return ret;
-}
-
-template<size_t n, size_t m>
-Signal<n> $zero_extend(Signal<m> const& a)
-{
-    assert(n >= m);
-    Signal<n> ret;
-    std::copy(a.begin(), a.end(), ret.begin());
-    for(size_t i = m; i < n; i++)
-        ret[i] = false;
-    return ret;
-}
-
-template<size_t n, size_t m>
-Signal<n> $sign_extend(Signal<m> const& a)
-{
-    assert(n >= m);
-    Signal<n> ret;
-    std::copy(a.begin(), a.end(), ret.begin());
-    for(size_t i = m; i < n; i++)
-        ret[i] = a[m-1];
-    return ret;
-}
 
-template<size_t a, size_t d>
-struct Memory {
-    std::array<Signal<d>, 1<<a> contents;
-};
+    template<size_t m>
+    Signal<n+m> concat(Signal<m> const& b) const
+    {
+        Signal<n + m> ret;
+        std::copy(_bits.begin(), _bits.end(), ret._bits.begin());
+        std::copy(b._bits.begin(), b._bits.end(), ret._bits.begin() + n);
+        return ret;
+    }
 
-template<size_t a, size_t d>
-Signal<d> $memory_read(Memory<a, d> memory, Signal<a> addr)
-{
-    return memory.contents[as_int(addr)];
-}
+    template<size_t m>
+    Signal<m> zero_extend() const
+    {
+        assert(m >= n);
+        Signal<m> ret = 0;
+        std::copy(_bits.begin(), _bits.end(), ret._bits.begin());
+        return ret;
+    }
+
+    template<size_t m>
+    Signal<m> sign_extend() const
+    {
+        assert(m >= n);
+        Signal<m> ret = Signal<m>::repeat(sign());
+        std::copy(_bits.begin(), _bits.end(), ret._bits.begin());
+        return ret;
+    }
+};
 
 template<size_t a, size_t d>
-Memory<a, d> $memory_write(Memory<a, d> memory, Signal<a> addr, Signal<d> data)
-{
-    Memory<a, d> ret = memory;
-    ret.contents[as_int(addr)] = data;
-    return ret;
-}
+class Memory {
+    std::array<Signal<d>, 1<<a> _contents;
+public:
+    Signal<d> read(Signal<a> addr) const
+    {
+        return _contents[addr.template as_numeric<size_t>()];
+    }
+    Memory write(Signal<a> addr, Signal<d> data) const
+    {
+        Memory ret = *this;
+        ret._contents[addr.template as_numeric<size_t>()] = data;
+        return ret;
+    }
+};
 
 #endif
diff --git a/tests/functional/single_cells/vcd_harness.cc b/tests/functional/single_cells/vcd_harness.cc
index 10ab10e428e..18c9ed5dfaa 100644
--- a/tests/functional/single_cells/vcd_harness.cc
+++ b/tests/functional/single_cells/vcd_harness.cc
@@ -33,22 +33,30 @@ struct Dump {
   }
 };
 
-// Function to set all values in a signal to false
-template<std::size_t n>
-void set_all_false(Signal<n>& signal) {
-  std::fill(signal.begin(), signal.end(), false);
-}
-
-template<std::size_t n>
-void set_all_random(Signal<n>& signal) {
+template<size_t n>
+Signal<n> random_signal() {
   std::random_device rd;  // Random device for seeding
   std::mt19937 gen(rd()); // Mersenne Twister engine
-  std::bernoulli_distribution dist(0.5); // 50-50 distribution
+  std::uniform_int_distribution<uint32_t> dist;
+  std::array<uint32_t, (n+31)/32> words;
+  for(auto &w : words)
+    w = dist(gen);
+  return Signal<n>::from_array(words);
+}
 
-  for (auto& value : signal) {
-    value = dist(gen); // Set each value to a random boolean
+struct Reset {
+  template <size_t n>
+  void operator()(const char *, Signal<n> &signal) {
+    signal = 0;
   }
-}
+};
+
+struct Randomize {
+  template <size_t n>
+  void operator()(const char *, Signal<n> &signal) {
+    signal = random_signal<n>();
+  }
+};
 
 int main(int argc, char **argv)
 {
@@ -62,10 +70,10 @@ int main(int argc, char **argv)
   constexpr int steps = 10;
   constexpr int number_timescale = 1;
   const std::string units_timescale = "us";
-  gold_Inputs inputs;
-  gold_Outputs outputs;
-  gold_State state;
-  gold_State next_state;
+  gold::Inputs inputs;
+  gold::Outputs outputs;
+  gold::State state;
+  gold::State next_state;
 
   std::ofstream vcd_file(functional_vcd_filename);
 
@@ -73,45 +81,34 @@ int main(int argc, char **argv)
   vcd_file << "$scope module gold $end\n";
   {
     DumpHeader d(vcd_file);
-    inputs.dump(d);
-    outputs.dump(d);
-    state.dump(d);
+    inputs.visit(d);
+    outputs.visit(d);
+    state.visit(d);
   }
   vcd_file << "$enddefinitions $end\n$dumpvars\n";
   vcd_file << "#0\n";
   // Set all signals to false
-  for (int i = 0; i < inputs.size(); ++i) {
-    auto input_variant = inputs.get_input(i);
-    std::visit([](auto& signal_ref) {
-      set_all_false(signal_ref.get());
-    }, input_variant);
-  }
+  inputs.visit(Reset());
      
-  gold(inputs, outputs, state, next_state);
+  gold::eval(inputs, outputs, state, next_state);
   {
     Dump d(vcd_file);
-    inputs.dump(d);
-    outputs.dump(d);
-    state.dump(d);
+    inputs.visit(d);
+    outputs.visit(d);
+    state.visit(d);
   }
     
   for (int step = 0; step < steps; ++step) {
     // Functional backend cxx
     vcd_file << "#" << (step + 1) << "\n";
-    // Set all signals to random
-    for (int i = 0; i < inputs.size(); ++i) {
-      auto input_variant = inputs.get_input(i);
-      std::visit([](auto& signal_ref) {
-	set_all_random(signal_ref.get());
-      }, input_variant);
-    }
+    inputs.visit(Randomize());
 
-    gold(inputs, outputs, state, next_state);
+    gold::eval(inputs, outputs, state, next_state);
     {
       Dump d(vcd_file);
-      inputs.dump(d);
-      outputs.dump(d);
-      state.dump(d);
+      inputs.visit(d);
+      outputs.visit(d);
+      state.visit(d);
     }
 	
     state = next_state;

From e235fc704dba8726d69f3f5964aa986952488231 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Thu, 27 Jun 2024 02:09:19 +0200
Subject: [PATCH 387/499] Create std::mt19937 only once

---
 tests/functional/single_cells/vcd_harness.cc | 21 ++++++++++++--------
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/tests/functional/single_cells/vcd_harness.cc b/tests/functional/single_cells/vcd_harness.cc
index 18c9ed5dfaa..9b3777c37fd 100644
--- a/tests/functional/single_cells/vcd_harness.cc
+++ b/tests/functional/single_cells/vcd_harness.cc
@@ -34,9 +34,7 @@ struct Dump {
 };
 
 template<size_t n>
-Signal<n> random_signal() {
-  std::random_device rd;  // Random device for seeding
-  std::mt19937 gen(rd()); // Mersenne Twister engine
+Signal<n> random_signal(std::mt19937 &gen) {
   std::uniform_int_distribution<uint32_t> dist;
   std::array<uint32_t, (n+31)/32> words;
   for(auto &w : words)
@@ -52,9 +50,12 @@ struct Reset {
 };
 
 struct Randomize {
+  std::mt19937 &gen;
+  Randomize(std::mt19937 &gen) : gen(gen) {}
+
   template <size_t n>
   void operator()(const char *, Signal<n> &signal) {
-    signal = random_signal<n>();
+    signal = random_signal<n>(gen);
   }
 };
 
@@ -89,7 +90,7 @@ int main(int argc, char **argv)
   vcd_file << "#0\n";
   // Set all signals to false
   inputs.visit(Reset());
-     
+
   gold::eval(inputs, outputs, state, next_state);
   {
     Dump d(vcd_file);
@@ -97,11 +98,15 @@ int main(int argc, char **argv)
     outputs.visit(d);
     state.visit(d);
   }
-    
+
+  // Initialize random number generator once
+  std::random_device rd;
+  std::mt19937 gen(rd());
+
   for (int step = 0; step < steps; ++step) {
     // Functional backend cxx
     vcd_file << "#" << (step + 1) << "\n";
-    inputs.visit(Randomize());
+    inputs.visit(Randomize(gen));
 
     gold::eval(inputs, outputs, state, next_state);
     {
@@ -110,7 +115,7 @@ int main(int argc, char **argv)
       outputs.visit(d);
       state.visit(d);
     }
-	
+
     state = next_state;
   }
 

From ee6bd5943684f49d933f233ddc1dbe464521921c Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Thu, 27 Jun 2024 04:14:05 +0200
Subject: [PATCH 388/499] Removed unnecesary nested_lets variable, use
 writer.print instead

---
 backends/functional/smtlib.cc | 21 +++++++++------------
 1 file changed, 9 insertions(+), 12 deletions(-)

diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index 49dd5cf0d21..7f1ca0a61b6 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -231,7 +231,6 @@ struct SmtModule {
 		auto node_to_string = [&](FunctionalIR::Node n) { return scope[n.name()]; };
 		SmtPrintVisitor<decltype(node_to_string)> visitor(node_to_string, scope);
 
-		std::string nested_lets;
 		for (auto it = ir.begin(); it != ir.end(); ++it) {
 			const FunctionalIR::Node &node = *it;
 
@@ -241,31 +240,29 @@ struct SmtModule {
 			std::string node_name = replaceCharacters(scope[node.name()]);
 			std::string node_expr = node.visit(visitor);
 
-			nested_lets += "(let (      (" + node_name + " " + node_expr + "))";
+			writer.print("  (let (      (%s %s))", node_name.c_str(), node_expr.c_str());
 		}
 
-		nested_lets += "          (let (";
+		writer.print("    (let (");
 		for (const auto &output : ir.outputs()) {
 			std::string output_name = scope[output.first];
 			const std::string output_assignment = ir.get_output_node(output.first).name().c_str();
-			nested_lets += "            (" + output_name + " " + replaceCharacters(output_assignment).substr(1) + ")";
+			writer.print("      (%s %s)", output_name.c_str(), replaceCharacters(output_assignment).substr(1).c_str());
 		}
-		nested_lets += "          )";
-		nested_lets += "            (mk_outputs";
-
+		writer.print("    )");
+		writer.print("      (mk_outputs");
 		for (const auto &output : ir.outputs()) {
 			std::string output_name = scope[output.first];
-			nested_lets += "              " + output_name;
+			writer.print("        %s", output_name.c_str());
 		}
-		nested_lets += "            )";
-		nested_lets += "          )";
+		writer.print("      )");
+		writer.print("    )");
 
 		// Close the nested lets
 		for (size_t i = 0; i < ir.size() - ir.inputs().size(); ++i) {
-			nested_lets += "    )";
+			writer.print("  )");
 		}
 
-		writer.print("%s", nested_lets.c_str());
 		writer.print("  )");
 		writer.print(")\n");
 	}

From 32cdf25838da8e492935e4b87829b504dfa0aec9 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Thu, 27 Jun 2024 04:42:59 +0200
Subject: [PATCH 389/499] Use FunctionalTools::Scope instead of
 replaceCharacters

---
 backends/functional/smtlib.cc | 26 +++++++-------------------
 1 file changed, 7 insertions(+), 19 deletions(-)

diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index 7f1ca0a61b6..afddbd83440 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -23,11 +23,14 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+const char illegal_characters[] = "$\\";
+const char *reserved_keywords[] = {};
+
 struct SmtScope {
 	pool<std::string> used_names;
 	dict<IdString, std::string> name_map;
-
-	SmtScope() {}
+	FunctionalTools::Scope scope;
+	SmtScope() : scope(illegal_characters, reserved_keywords) {}
 
 	void reserve(const std::string &name) { used_names.insert(name); }
 
@@ -184,21 +187,6 @@ struct SmtModule {
 
 	SmtModule(const std::string &module_name, FunctionalIR ir) : name(module_name), ir(std::move(ir)) {}
 
-	std::string replaceCharacters(const std::string &input)
-	{
-		std::string result = input;
-		std::replace(result.begin(), result.end(), '$', '_'); // Replace $ with _
-
-		// Since \ is an escape character, we use a loop to replace it
-		size_t pos = 0;
-		while ((pos = result.find('\\', pos)) != std::string::npos) {
-			result.replace(pos, 1, "_");
-			pos += 1; // Move past the replaced character
-		}
-
-		return result;
-	}
-
 	void write(std::ostream &out)
 	{
 		SmtWriter writer(out);
@@ -237,7 +225,7 @@ struct SmtModule {
 			if (ir.inputs().count(node.name()) > 0)
 				continue;
 
-			std::string node_name = replaceCharacters(scope[node.name()]);
+			std::string node_name = scope[node.name()];
 			std::string node_expr = node.visit(visitor);
 
 			writer.print("  (let (      (%s %s))", node_name.c_str(), node_expr.c_str());
@@ -247,7 +235,7 @@ struct SmtModule {
 		for (const auto &output : ir.outputs()) {
 			std::string output_name = scope[output.first];
 			const std::string output_assignment = ir.get_output_node(output.first).name().c_str();
-			writer.print("      (%s %s)", output_name.c_str(), replaceCharacters(output_assignment).substr(1).c_str());
+			writer.print("      (%s %s)", output_name.c_str(), output_assignment.substr(1).c_str());
 		}
 		writer.print("    )");
 		writer.print("      (mk_outputs");

From 9700df50d6818d5df276bcfff41501fef0be0ac3 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 4 Jul 2024 10:22:51 +0100
Subject: [PATCH 390/499] add generic writer class with formatting function to
 FunctionalTools

---
 backends/functional/cxx.cc            | 180 +++++++++++---------------
 backends/functional/cxx_runtime/sim.h |   4 +-
 kernel/functionalir.cc                |  51 ++++++++
 kernel/functionalir.h                 | 128 ++++++++++--------
 4 files changed, 203 insertions(+), 160 deletions(-)

diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index d866dfea210..21e287a96c4 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -56,17 +56,7 @@ struct CxxType {
 	}
 };
 
-struct CxxWriter {
-	std::ostream &f;
-	CxxWriter(std::ostream &out) : f(out) {}
-	void printf(const char *fmt, ...)
-	{
-		va_list va;
-		va_start(va, fmt);
-		f << vstringf(fmt, va);
-		va_end(va);
-	}
-};
+using CxxWriter = FunctionalTools::Writer;
 
 struct CxxStruct {
   std::string name;
@@ -74,111 +64,85 @@ struct CxxStruct {
   FunctionalTools::Scope scope;
   CxxStruct(std::string name)
     : name(name), scope(illegal_characters, reserved_keywords) {
-    scope.reserve("out");
-    scope.reserve("dump");
+    scope.reserve("fn");
+    scope.reserve("visit");
   }
   void insert(IdString name, CxxType type) {
     scope(name);
     types.insert({name, type});
   }
   void print(CxxWriter &f) {
-    f.printf("\tstruct %s {\n", name.c_str());
+    f.print("\tstruct {} {{\n", name);
     for (auto p : types) {
-      f.printf("\t\t%s %s;\n", p.second.to_string().c_str(), scope(p.first).c_str());
+      f.print("\t\t{} {};\n", p.second.to_string(), scope(p.first));
     }
-    f.printf("\n\t\ttemplate <typename T> void visit(T &&fn) {\n");
+    f.print("\n\t\ttemplate <typename T> void visit(T &&fn) {{\n");
     for (auto p : types) {
-      f.printf("\t\t\tfn(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope(p.first).c_str());
+      f.print("\t\t\tfn(\"{}\", {});\n", RTLIL::unescape_id(p.first), scope(p.first));
     }
-    f.printf("\t\t}\n");
-    f.printf("\t};\n\n");
+    f.print("\t\t}}\n");
+    f.print("\t}};\n\n");
   };
   std::string operator[](IdString field) {
     return scope(field);
   }
 };
 
-struct CxxTemplate {
-	vector<std::variant<std::string, int>> _v;
-public:
-	CxxTemplate(std::string fmt) {
-		std::string buf;
-		for(auto it = fmt.begin(); it != fmt.end(); it++){
-			if(*it == '%'){
-				it++;
-				log_assert(it != fmt.end());
-				if(*it == '%')
-					buf += *it;
-				else {
-					log_assert(*it >= '0' && *it <= '9');
-					_v.emplace_back(std::move(buf));
-					_v.emplace_back((int)(*it - '0'));
-				}
-			}else
-				buf += *it;
-		}
-		if(!buf.empty())
-			_v.emplace_back(std::move(buf));
-	}
-	template<typename... Args> static std::string format(CxxTemplate fmt, Args&&... args) {
-		vector<std::string> strs = {args...};
-		std::string result;
-		for(auto &v : fmt._v){
-			if(std::string *s = std::get_if<std::string>(&v))
-				result += *s;
-			else if(int *i = std::get_if<int>(&v))
-				result += strs[*i];
-			else
-				log_error("missing case");
-		}
-		return result;
-	}
-};
-
-template<class NodeNames> struct CxxPrintVisitor {
+template<class NodePrinter> struct CxxPrintVisitor {
 	using Node = FunctionalIR::Node;
-	NodeNames np;
+	CxxWriter &f;
+	NodePrinter np;
 	CxxStruct &input_struct;
 	CxxStruct &state_struct;
-	CxxPrintVisitor(NodeNames np, CxxStruct &input_struct, CxxStruct &state_struct) : np(np), input_struct(input_struct), state_struct(state_struct) { }
-	template<class T> std::string arg_to_string(T n) { return std::to_string(n); }
-	std::string arg_to_string(std::string n) { return n; }
-	std::string arg_to_string(Node n) { return np(n); }
-	template<typename... Args> std::string format(std::string fmt, Args&&... args) {
-		return CxxTemplate::format(fmt, arg_to_string(args)...);
+	CxxPrintVisitor(CxxWriter &f, NodePrinter np, CxxStruct &input_struct, CxxStruct &state_struct) : f(f), np(np), input_struct(input_struct), state_struct(state_struct) { }
+	template<typename... Args> void print(const char *fmt, Args&&... args) {
+		f.print_with(np, fmt, std::forward<Args>(args)...);
 	}
-	std::string buf(Node, Node n) { return np(n); }
-	std::string slice(Node, Node a, int, int offset, int out_width) { return format("%0.slice<%2>(%1)", a, offset, out_width); }
-	std::string zero_extend(Node, Node a, int, int out_width) { return format("%0.zero_extend<%1>()", a, out_width); }
-	std::string sign_extend(Node, Node a, int, int out_width) { return format("%0.sign_extend<%1>()", a, out_width); }
-	std::string concat(Node, Node a, int, Node b, int) { return format("%0.concat(%1)", a, b); }
-	std::string add(Node, Node a, Node b, int) { return format("%0 + %1", a, b); }
-	std::string sub(Node, Node a, Node b, int) { return format("%0 - %1", a, b); }
-	std::string bitwise_and(Node, Node a, Node b, int) { return format("%0 & %1", a, b); }
-	std::string bitwise_or(Node, Node a, Node b, int) { return format("%0 | %1", a, b); }
-	std::string bitwise_xor(Node, Node a, Node b, int) { return format("%0 ^ %1", a, b); }
-	std::string bitwise_not(Node, Node a, int) { return format("~%0", a); }
-	std::string unary_minus(Node, Node a, int) { return format("-%0", a); }
-	std::string reduce_and(Node, Node a, int) { return format("%0.all()", a); }
-	std::string reduce_or(Node, Node a, int) { return format("%0.any()", a); }
-	std::string reduce_xor(Node, Node a, int) { return format("%0.parity()", a); }
-	std::string equal(Node, Node a, Node b, int) { return format("%0 == %1", a, b); }
-	std::string not_equal(Node, Node a, Node b, int) { return format("%0 != %1", a, b); }
-	std::string signed_greater_than(Node, Node a, Node b, int) { return format("%0.signed_greater_than(%1)", a, b); }
-	std::string signed_greater_equal(Node, Node a, Node b, int) { return format("%0.signed_greater_equal(%1)", a, b); }
-	std::string unsigned_greater_than(Node, Node a, Node b, int) { return format("%0 > %1", a, b); }
-	std::string unsigned_greater_equal(Node, Node a, Node b, int) { return format("%0 >= %1", a, b); }
-	std::string logical_shift_left(Node, Node a, Node b, int, int) { return format("%0 << %1", a, b); }
-	std::string logical_shift_right(Node, Node a, Node b, int, int) { return format("%0 >> %1", a, b); }
-	std::string arithmetic_shift_right(Node, Node a, Node b, int, int) { return format("%0.arithmetic_shift_right(%1)", a, b); }
-	std::string mux(Node, Node a, Node b, Node s, int) { return format("%2.any() ? %1 : %0", a, b, s); }
-	std::string pmux(Node, Node a, Node b, Node s, int, int) { return format("%0.pmux(%1, %2)", a, b, s); }
-	std::string constant(Node, RTLIL::Const value) { return format("Signal<%0>(%1)", value.size(), value.as_int()); }
-	std::string input(Node, IdString name) { return format("input.%0", input_struct[name]); }
-	std::string state(Node, IdString name) { return format("current_state.%0", state_struct[name]); }
-	std::string memory_read(Node, Node mem, Node addr, int, int) { return format("%0.read(%1)", mem, addr); }
-	std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { return format("%0.write(%1, %2)", mem, addr, data); }
-	std::string undriven(Node, int width) { return format("Signal<%0>(0)", width); }
+	void buf(Node, Node n) { print("{}", n); }
+	void slice(Node, Node a, int, int offset, int out_width) { print("{0}.slice<{2}>({1})", a, offset, out_width); }
+	void zero_extend(Node, Node a, int, int out_width) { print("{}.zero_extend<{}>()", a, out_width); }
+	void sign_extend(Node, Node a, int, int out_width) { print("{}.sign_extend<{}>()", a, out_width); }
+	void concat(Node, Node a, int, Node b, int) { print("{}.concat({})", a, b); }
+	void add(Node, Node a, Node b, int) { print("{} + {}", a, b); }
+	void sub(Node, Node a, Node b, int) { print("{} - {}", a, b); }
+	void bitwise_and(Node, Node a, Node b, int) { print("{} & {}", a, b); }
+	void bitwise_or(Node, Node a, Node b, int) { print("{} | {}", a, b); }
+	void bitwise_xor(Node, Node a, Node b, int) { print("{} ^ {}", a, b); }
+	void bitwise_not(Node, Node a, int) { print("~{}", a); }
+	void unary_minus(Node, Node a, int) { print("-{}", a); }
+	void reduce_and(Node, Node a, int) { print("{}.all()", a); }
+	void reduce_or(Node, Node a, int) { print("{}.any()", a); }
+	void reduce_xor(Node, Node a, int) { print("{}.parity()", a); }
+	void equal(Node, Node a, Node b, int) { print("{} == {}", a, b); }
+	void not_equal(Node, Node a, Node b, int) { print("{} != {}", a, b); }
+	void signed_greater_than(Node, Node a, Node b, int) { print("{}.signed_greater_than({})", a, b); }
+	void signed_greater_equal(Node, Node a, Node b, int) { print("{}.signed_greater_equal({})", a, b); }
+	void unsigned_greater_than(Node, Node a, Node b, int) { print("{} > {}", a, b); }
+	void unsigned_greater_equal(Node, Node a, Node b, int) { print("{} >= {}", a, b); }
+	void logical_shift_left(Node, Node a, Node b, int, int) { print("{} << {}", a, b); }
+	void logical_shift_right(Node, Node a, Node b, int, int) { print("{} >> {}", a, b); }
+	void arithmetic_shift_right(Node, Node a, Node b, int, int) { print("{}.arithmetic_shift_right{})", a, b); }
+	void mux(Node, Node a, Node b, Node s, int) { print("{2}.any() ? {1} : {0}", a, b, s); }
+	void pmux(Node, Node a, Node b, Node s, int, int) { print("{0}.pmux({1}, {2})", a, b, s); }
+	void constant(Node, RTLIL::Const value) {
+		std::stringstream ss;
+		bool multiple = value.size() > 32;
+		ss << "Signal<" << value.size() << ">(" << std::hex << std::showbase;
+		if(multiple) ss << "{";
+		while(value.size() > 32) {
+			ss << value.as_int() << ", ";
+			value = value.extract(32, value.size() - 32);
+		}
+		ss << value.as_int();
+		if(multiple) ss << "}";
+		ss << ")";
+		print("{}", ss.str());
+	}
+	void input(Node, IdString name) { print("input.{}", input_struct[name]); }
+	void state(Node, IdString name) { print("current_state.{}", state_struct[name]); }
+	void memory_read(Node, Node mem, Node addr, int, int) { print("{}.read({})", mem, addr); }
+	void memory_write(Node, Node mem, Node addr, Node data, int, int) { print("{}.write({}, {})", mem, addr, data); }
+	void undriven(Node, int width) { print("Signal<{}>(0)", width); }
 };
 
 struct CxxModule {
@@ -201,31 +165,35 @@ struct CxxModule {
 		module_name = FunctionalTools::Scope(illegal_characters, reserved_keywords)(module->name);
 	}
 	void write_header(CxxWriter &f) {
-		f.printf("#include \"sim.h\"\n\n");
+		f.print("#include \"sim.h\"\n\n");
 	}
 	void write_struct_def(CxxWriter &f) {
-		f.printf("struct %s {\n", module_name.c_str());
+		f.print("struct {} {{\n", module_name);
 		input_struct.print(f);
 		output_struct.print(f);
 		state_struct.print(f);
-		f.printf("\tstatic void eval(Inputs const &, Outputs &, State const &, State &);\n");
-		f.printf("};\n\n");
+		f.print("\tstatic void eval(Inputs const &, Outputs &, State const &, State &);\n");
+		f.print("}};\n\n");
 	}
 	void write_eval_def(CxxWriter &f) {
-		f.printf("void %s::eval(%s::Inputs const &input, %s::Outputs &output, %s::State const &current_state, %s::State &next_state)\n{\n", module_name.c_str(), module_name.c_str(), module_name.c_str(), module_name.c_str(), module_name.c_str());
+		f.print("void {0}::eval({0}::Inputs const &input, {0}::Outputs &output, {0}::State const &current_state, {0}::State &next_state)\n{{\n", module_name);
 		FunctionalTools::Scope locals(illegal_characters, reserved_keywords);
 		locals.reserve("input");
 		locals.reserve("output");
 		locals.reserve("current_state");
 		locals.reserve("next_state");
 		auto node_name = [&](FunctionalIR::Node n) { return locals(n.id(), n.name()); };
-		for (auto node : ir)
-			f.printf("\t%s %s = %s;\n", CxxType(node.sort()).to_string().c_str(), node_name(node).c_str(), node.visit(CxxPrintVisitor(node_name, input_struct, state_struct)).c_str());
+		CxxPrintVisitor printVisitor(f, node_name, input_struct, state_struct);
+		for (auto node : ir) {
+			f.print("\t{} {} = ", CxxType(node.sort()).to_string(), node_name(node));
+			node.visit(printVisitor);
+			f.print(";\n");
+		}
 		for (auto [name, sort] : ir.state())
-			f.printf("\tnext_state.%s = %s;\n", state_struct[name].c_str(), node_name(ir.get_state_next_node(name)).c_str());
+			f.print("\tnext_state.{} = {};\n", state_struct[name], node_name(ir.get_state_next_node(name)));
 		for (auto [name, sort] : ir.outputs())
-			f.printf("\toutput.%s = %s;\n", output_struct[name].c_str(), node_name(ir.get_output_node(name)).c_str());
-		f.printf("}\n");
+			f.print("\toutput.{} = {};\n", output_struct[name], node_name(ir.get_output_node(name)));
+		f.print("}}\n");
 	}
 };
 
diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h
index 0614fb34cf7..1985322f1c8 100644
--- a/backends/functional/cxx_runtime/sim.h
+++ b/backends/functional/cxx_runtime/sim.h
@@ -143,11 +143,11 @@ class Signal {
     {
         for(size_t i = sizeof(T) * 8; i < n; i++)
             if(_bits[i])
-                return ~0;
+                return ~((T)0);
         return as_numeric<T>();
     }
 
-    uint32_t as_int() { return as_numeric<uint32_t>(); }
+    uint32_t as_int() const { return as_numeric<uint32_t>(); }
 
     Signal<n> operator ~() const
     {
diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc
index 6ae66d6802b..3fd2d8240e7 100644
--- a/kernel/functionalir.cc
+++ b/kernel/functionalir.cc
@@ -443,4 +443,55 @@ void FunctionalIR::forward_buf() {
     _graph.permute(perm, alias);
 }
 
+static std::string quote_fmt(const char *fmt)
+{
+	std::string r;
+	for(const char *p = fmt; *p != 0; p++) {
+		switch(*p) {
+		case '\n': r += "\\n"; break;
+		case '\t': r += "\\t"; break;
+		case '"': r += "\\\""; break;
+		case '\\': r += "\\\\"; break;
+		default: r += *p; break;
+		}
+	}
+	return r;
+}
+
+void FunctionalTools::Writer::print_impl(const char *fmt, vector<std::function<void()>> &fns)
+{
+	size_t next_index = 0;
+	for(const char *p = fmt; *p != 0; p++)
+		switch(*p) {
+		case '{':
+			if(*++p == '{') {
+				*os << '{';
+			} else {
+				char *pe;
+				size_t index = strtoul(p, &pe, 10);
+				if(*pe != '}')
+					log_error("invalid format string: expected {<number>}, {} or {{, got \"%s\": \"%s\"\n",
+						quote_fmt(std::string(p - 1, pe - p + 2).c_str()).c_str(),
+						quote_fmt(fmt).c_str());
+				if(p == pe)
+					index = next_index;
+				else
+					p = pe;
+				if(index >= fns.size())
+					log_error("invalid format string: index %zu out of bounds (%zu): \"%s\"\n", index, fns.size(), quote_fmt(fmt).c_str());
+				fns[index]();
+				next_index = index + 1;
+			}
+			break;
+		case '}':
+			p++;
+			if(*p != '}')
+				log_error("invalid format string: unescaped }: \"%s\"\n", quote_fmt(fmt).c_str());
+			*os << '}';
+			break;
+		default:
+			*os << *p;
+		}
+}
+
 YOSYS_NAMESPACE_END
diff --git a/kernel/functionalir.h b/kernel/functionalir.h
index f49a659f37b..2c0d0f55c2c 100644
--- a/kernel/functionalir.h
+++ b/kernel/functionalir.h
@@ -29,58 +29,6 @@
 USING_YOSYS_NAMESPACE
 YOSYS_NAMESPACE_BEGIN
 
-namespace FunctionalTools {
-	class Scope {
-		const char *_illegal_characters;
-		pool<std::string> _used_names;
-		dict<int, std::string> _by_id;
-		dict<IdString, std::string> _by_name;
-		std::string allocate_name(IdString suggestion) {
-			std::string str = RTLIL::unescape_id(suggestion);
-			for(size_t i = 0; i < str.size(); i++)
-				if(strchr(_illegal_characters, str[i]))
-					str[i] = '_';
-			if(_used_names.count(str) == 0) {
-				_used_names.insert(str);
-				return str;
-			}
-			for (int idx = 0 ; ; idx++){
-				std::string suffixed = str + "_" + std::to_string(idx);
-				if(_used_names.count(suffixed) == 0) {
-					_used_names.insert(suffixed);
-					return suffixed;
-				}
-			}
-		}
-	public:
-		Scope(const char *illegal_characters = "", const char **keywords = nullptr) {
-			_illegal_characters = illegal_characters;
-			if(keywords != nullptr)
-				for(const char **p = keywords; *p != nullptr; p++)
-					reserve(*p);
-		}
-		void reserve(std::string name) {
-			_used_names.insert(std::move(name));
-		}
-		std::string operator()(int id, IdString suggestion) {
-			auto it = _by_id.find(id);
-			if(it != _by_id.end())
-				return it->second;
-			std::string str = allocate_name(suggestion);
-			_by_id.insert({id, str});
-			return str;
-		}
-		std::string operator()(IdString idstring) {
-			auto it = _by_name.find(idstring);
-			if(it != _by_name.end())
-				return it->second;
-			std::string str = allocate_name(idstring);
-			_by_name.insert({idstring, str});
-			return str;
-		}
-	};
-}
-
 class FunctionalIR {
 	enum class Fn {
 		invalid,
@@ -418,6 +366,82 @@ class FunctionalIR {
 	Iterator end() { return Iterator(this, _graph.size()); }
 };
 
+namespace FunctionalTools {
+	class Scope {
+		const char *_illegal_characters;
+		pool<std::string> _used_names;
+		dict<int, std::string> _by_id;
+		dict<IdString, std::string> _by_name;
+		std::string allocate_name(IdString suggestion) {
+			std::string str = RTLIL::unescape_id(suggestion);
+			for(size_t i = 0; i < str.size(); i++)
+				if(strchr(_illegal_characters, str[i]))
+					str[i] = '_';
+			if(_used_names.count(str) == 0) {
+				_used_names.insert(str);
+				return str;
+			}
+			for (int idx = 0 ; ; idx++){
+				std::string suffixed = str + "_" + std::to_string(idx);
+				if(_used_names.count(suffixed) == 0) {
+					_used_names.insert(suffixed);
+					return suffixed;
+				}
+			}
+		}
+	public:
+		Scope(const char *illegal_characters = "", const char **keywords = nullptr) {
+			_illegal_characters = illegal_characters;
+			if(keywords != nullptr)
+				for(const char **p = keywords; *p != nullptr; p++)
+					reserve(*p);
+		}
+		void reserve(std::string name) {
+			_used_names.insert(std::move(name));
+		}
+		std::string operator()(int id, IdString suggestion) {
+			auto it = _by_id.find(id);
+			if(it != _by_id.end())
+				return it->second;
+			std::string str = allocate_name(suggestion);
+			_by_id.insert({id, str});
+			return str;
+		}
+		std::string operator()(IdString idstring) {
+			auto it = _by_name.find(idstring);
+			if(it != _by_name.end())
+				return it->second;
+			std::string str = allocate_name(idstring);
+			_by_name.insert({idstring, str});
+			return str;
+		}
+	};
+	class Writer {
+		std::ostream *os;
+		void print_impl(const char *fmt, vector<std::function<void()>>& fns);
+	public:
+		Writer(std::ostream &os) : os(&os) {}
+		template<class T> Writer& operator <<(T&& arg) { *os << std::forward<T>(arg); return *this; }
+		template<typename... Args>
+		void print(const char *fmt, Args&&... args)
+		{
+			vector<std::function<void()>> fns { [&]() { *this << args; }... };
+			print_impl(fmt, fns);
+		}
+		template<typename Fn, typename... Args>
+		void print_with(Fn fn, const char *fmt, Args&&... args)
+		{
+			vector<std::function<void()>> fns { [&]() {
+				if constexpr (std::is_invocable_v<Fn, Args>)
+					*this << fn(args);
+				else
+					*this << args; }...
+			};
+			print_impl(fmt, fns);
+		}
+	};
+}
+
 YOSYS_NAMESPACE_END
 
 #endif

From cb5f08364c2a775c9725d94144875539edff8533 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Wed, 3 Jul 2024 17:07:50 +0200
Subject: [PATCH 391/499] =?UTF-8?q?=C2=B4SMT=20success=20only=20if=20simul?=
 =?UTF-8?q?ation=20is=20equivalent?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 tests/functional/single_cells/run-test.sh        | 1 -
 tests/functional/single_cells/vcd_harness_smt.py | 4 ++++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/tests/functional/single_cells/run-test.sh b/tests/functional/single_cells/run-test.sh
index 67358639bf2..11ff1b5ce0b 100755
--- a/tests/functional/single_cells/run-test.sh
+++ b/tests/functional/single_cells/run-test.sh
@@ -54,7 +54,6 @@ run_smt_test() {
 	# TODO: which SMT solver should be run?
 	if z3 "${base_name}.smt2"; then
             echo "SMT file ${base_name}.smt2 is valid ."
-	    smt_successful_files["$rtlil_file"]="Success"
             if python3 vcd_harness_smt.py "${base_name}.smt2"; then
 		echo "Python script generated VCD file for $rtlil_file successfully."
 
diff --git a/tests/functional/single_cells/vcd_harness_smt.py b/tests/functional/single_cells/vcd_harness_smt.py
index a44bf4570c9..5d8c735a6c1 100644
--- a/tests/functional/single_cells/vcd_harness_smt.py
+++ b/tests/functional/single_cells/vcd_harness_smt.py
@@ -133,6 +133,9 @@ def set_step(inputs, step):
 # smt_io.setup()
 result = smt_io.check_sat()
 print(f'SAT result: {result}')
+if result != 'sat':
+    smt_io.p_close()
+    sys.exit(1)
 
 value = smt_io.get(f'(Y test_outputs_step_n0)')
 print(f"  Y: {value}")
@@ -197,3 +200,4 @@ def write_vcd(filename, signals, timescale='1 ns', date='today'):
 
 # Write the VCD file
 write_vcd(smt_file_path + '.vcd', signals)
+sys.exit(0)

From 73ed5146233dca64405a30d82646b286df43144a Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Thu, 4 Jul 2024 12:35:00 +0200
Subject: [PATCH 392/499] Check that there are not other solutions other than
 the first given

---
 tests/functional/single_cells/vcd_harness_smt.py | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/tests/functional/single_cells/vcd_harness_smt.py b/tests/functional/single_cells/vcd_harness_smt.py
index 5d8c735a6c1..fd5e94f7e2f 100644
--- a/tests/functional/single_cells/vcd_harness_smt.py
+++ b/tests/functional/single_cells/vcd_harness_smt.py
@@ -41,7 +41,7 @@
 # Load and execute the SMT file
 with open(smt_file_path, 'r') as smt_file:
     for line in smt_file:
-        smt_io.write(line.strip())
+        smt_io.write(line.strip())    
 smt_io.check_sat()
 # Read and parse the SMT file line by line
 with open(smt_file_path, 'r') as smt_file:
@@ -161,6 +161,17 @@ def hex_to_bin(value):
         value = hex_to_bin(value[1:])
         print(f"  {output_name}: {value}")
         signals[output_name].append((step, value))
+        smt_io.write(f'(push 1)')
+        smt_io.write(f'(assert (not (= ({output_name} test_outputs_step_n{step}) #{value})))')
+        result = smt_io.check_sat(["unsat"])
+        if result != 'unsat':
+            smt_io.p_close()
+            sys.exit(1)
+        smt_io.write(f'(pop 1)')
+        result = smt_io.check_sat(["sat"])
+        if result != 'sat':
+            smt_io.p_close()
+            sys.exit(1)
         
 smt_io.p_close()
 

From 762f8dd8228e8b6219d67fb04e87deb434e0215a Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Thu, 4 Jul 2024 12:39:45 +0200
Subject: [PATCH 393/499] Add readme explaining how to create test files

---
 tests/functional/single_cells/rtlil/README.md | 2 ++
 1 file changed, 2 insertions(+)
 create mode 100644 tests/functional/single_cells/rtlil/README.md

diff --git a/tests/functional/single_cells/rtlil/README.md b/tests/functional/single_cells/rtlil/README.md
new file mode 100644
index 00000000000..4bb84565b7e
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/README.md
@@ -0,0 +1,2 @@
+# Creation of test files
+yosys -p "test_cell -n 1 -w test_cell all"
\ No newline at end of file

From 50f487e08c9a2343b013652e021d7e3314d0bcae Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Thu, 4 Jul 2024 16:04:21 +0200
Subject: [PATCH 394/499] Added $ff test

---
 tests/functional/single_cells/rtlil/ff.il | 83 +++++++++++++++++++++++
 1 file changed, 83 insertions(+)
 create mode 100644 tests/functional/single_cells/rtlil/ff.il

diff --git a/tests/functional/single_cells/rtlil/ff.il b/tests/functional/single_cells/rtlil/ff.il
new file mode 100644
index 00000000000..6e5a1a339d0
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/ff.il
@@ -0,0 +1,83 @@
+# Generated by Yosys 0.40+7 (git sha1 4fd5b29f9, g++ 13.2.0 -Og -fPIC)
+autoidx 19
+attribute \cells_not_processed 1
+attribute \src "dff.v:1.1-16.10"
+module \gold
+  attribute \src "dff.v:8.5-14.8"
+  wire $0\q[0:0]
+  attribute \init 1'0
+  wire $auto$clk2fflogic.cc:65:sample_control$\reset#sampled$13
+  attribute \init 1'1
+  wire $auto$clk2fflogic.cc:77:sample_control_edge$\clk#sampled$7
+  attribute \init 1'0
+  wire $auto$clk2fflogic.cc:91:sample_data$\d#sampled$5
+  attribute \init 1'x
+  wire $auto$clk2fflogic.cc:91:sample_data$\q#sampled$3
+  wire $auto$rtlil.cc:2525:Eqx$10
+  wire $auto$rtlil.cc:2582:Mux$12
+  wire $auto$rtlil.cc:2582:Mux$16
+  wire $auto$rtlil.cc:2582:Mux$18
+  attribute \src "dff.v:2.16-2.19"
+  wire input 1 \clk
+  attribute \src "dff.v:4.16-4.17"
+  wire input 3 \d
+  attribute \keep 1
+  attribute \src "dff.v:5.16-5.17"
+  wire output 4 \q
+  attribute \src "dff.v:3.16-3.21"
+  wire input 2 \reset
+  cell $mux $auto$clk2fflogic.cc:113:mux$11
+    parameter \WIDTH 1
+    connect \A $auto$clk2fflogic.cc:91:sample_data$\q#sampled$3
+    connect \B $auto$clk2fflogic.cc:91:sample_data$\d#sampled$5
+    connect \S $auto$rtlil.cc:2525:Eqx$10
+    connect \Y $auto$rtlil.cc:2582:Mux$12
+  end
+  cell $mux $auto$clk2fflogic.cc:113:mux$15
+    parameter \WIDTH 1
+    connect \A $auto$rtlil.cc:2582:Mux$12
+    connect \B 1'0
+    connect \S $auto$clk2fflogic.cc:65:sample_control$\reset#sampled$13
+    connect \Y $auto$rtlil.cc:2582:Mux$16
+  end
+  cell $mux $auto$clk2fflogic.cc:113:mux$17
+    parameter \WIDTH 1
+    connect \A $auto$rtlil.cc:2582:Mux$16
+    connect \B 1'0
+    connect \S \reset
+    connect \Y $auto$rtlil.cc:2582:Mux$18
+  end
+  cell $ff $auto$clk2fflogic.cc:70:sample_control$14
+    parameter \WIDTH 1
+    connect \D \reset
+    connect \Q $auto$clk2fflogic.cc:65:sample_control$\reset#sampled$13
+  end
+  cell $ff $auto$clk2fflogic.cc:82:sample_control_edge$8
+    parameter \WIDTH 1
+    connect \D \clk
+    connect \Q $auto$clk2fflogic.cc:77:sample_control_edge$\clk#sampled$7
+  end
+  cell $eqx $auto$clk2fflogic.cc:83:sample_control_edge$9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A { $auto$clk2fflogic.cc:77:sample_control_edge$\clk#sampled$7 \clk }
+    connect \B 2'01
+    connect \Y $auto$rtlil.cc:2525:Eqx$10
+  end
+  attribute \clk2fflogic 1
+  cell $ff $auto$clk2fflogic.cc:98:sample_data$4
+    parameter \WIDTH 1
+    connect \D \q
+    connect \Q $auto$clk2fflogic.cc:91:sample_data$\q#sampled$3
+  end
+  cell $ff $auto$clk2fflogic.cc:98:sample_data$6
+    parameter \WIDTH 1
+    connect \D \d
+    connect \Q $auto$clk2fflogic.cc:91:sample_data$\d#sampled$5
+  end
+  connect $0\q[0:0] \d
+  connect \q $auto$rtlil.cc:2582:Mux$18
+end

From 1b2986f7fb85e00a75a0c5c6d88905f78025c467 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 4 Jul 2024 16:58:07 +0100
Subject: [PATCH 395/499] add support for $mul, $div, $divfloor, $mod,
 $modfloor, $pow in functional backend

---
 backends/functional/cxx.cc            |  3 +
 backends/functional/cxx_runtime/sim.h | 89 +++++++++++++++++++++++++--
 backends/functional/smtlib.cc         |  6 ++
 kernel/functionalir.cc                | 73 +++++++++++++++++++++-
 kernel/functionalir.h                 | 17 ++++-
 5 files changed, 177 insertions(+), 11 deletions(-)

diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index 21e287a96c4..81af54c073e 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -105,6 +105,9 @@ template<class NodePrinter> struct CxxPrintVisitor {
 	void concat(Node, Node a, int, Node b, int) { print("{}.concat({})", a, b); }
 	void add(Node, Node a, Node b, int) { print("{} + {}", a, b); }
 	void sub(Node, Node a, Node b, int) { print("{} - {}", a, b); }
+	void mul(Node, Node a, Node b, int) { print("{} * {}", a, b); }
+	void unsigned_div(Node, Node a, Node b, int) { print("{} / {}", a, b); }
+	void unsigned_mod(Node, Node a, Node b, int) { print("{} % {}", a, b); }
 	void bitwise_and(Node, Node a, Node b, int) { print("{} & {}", a, b); }
 	void bitwise_or(Node, Node a, Node b, int) { print("{} | {}", a, b); }
 	void bitwise_xor(Node, Node a, Node b, int) { print("{} ^ {}", a, b); }
diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h
index 1985322f1c8..040c6aefce8 100644
--- a/backends/functional/cxx_runtime/sim.h
+++ b/backends/functional/cxx_runtime/sim.h
@@ -22,6 +22,8 @@
 
 #include <array>
 #include <cassert>
+#include <string>
+#include <iostream>
 
 template<size_t n>
 class Signal {
@@ -149,6 +151,48 @@ class Signal {
 
     uint32_t as_int() const { return as_numeric<uint32_t>(); }
 
+private:
+    std::string as_string_p2(int b) const {
+        std::string ret;
+        for(int i = (n - 1) - (n - 1) % b; i >= 0; i -= b)
+            ret += "0123456789abcdef"[(*this >> Signal<32>(i)).as_int() & ((1<<b)-1)];
+        return ret;
+    }
+    std::string as_string_b10() const {
+        std::string ret;
+        if(n < 4) return std::string() + (char)('0' + as_int());
+        Signal<n> t = *this;
+        Signal<n> b = 10;
+        do{
+            ret += (char)('0' + (t % b).as_int());
+            t = t / b;
+        }while(t.any());
+        std::reverse(ret.begin(), ret.end());
+        return ret;
+    }
+public:
+    std::string as_string(int base = 16, bool showbase = true) const {
+        std::string ret;
+        if(showbase) {
+            ret += std::to_string(n);
+            switch(base) {
+            case 2: ret += "'b"; break;
+            case 8: ret += "'o"; break;
+            case 10: ret += "'d"; break;
+            case 16: ret += "'h"; break;
+            default: assert(0);
+            }
+        }
+        switch(base) {
+        case 2: return ret + as_string_p2(1);
+        case 8: return ret + as_string_p2(3);
+        case 10: return ret + as_string_b10();
+        case 16: return ret + as_string_p2(4);
+        default: assert(0);
+        }
+    }
+    friend std::ostream &operator << (std::ostream &os, Signal<n> const &s) { return os << s.as_string(); }
+
     Signal<n> operator ~() const
     {
         Signal<n> ret;
@@ -160,11 +204,11 @@ class Signal {
     Signal<n> operator -() const
     {
         Signal<n> ret;
-        bool carry = true;
+        int x = 1;
         for(size_t i = 0; i < n; i++) {
-            int r = !_bits[i] + carry;
-            ret._bits[i] = (r & 1) != 0;
-            carry = (r >> 1) != 0;
+            x += (int)!_bits[i];
+            ret._bits[i] = (x & 1) != 0;
+            x >>= 1;
         }
         return ret;
     }
@@ -172,9 +216,8 @@ class Signal {
     Signal<n> operator +(Signal<n> const &b) const
     {
         Signal<n> ret;
-        size_t i;
         int x = 0;
-        for(i = 0; i < n; i++){
+        for(size_t i = 0; i < n; i++){
             x += (int)_bits[i] + (int)b._bits[i];
             ret._bits[i] = x & 1;
             x >>= 1;
@@ -194,6 +237,40 @@ class Signal {
         return ret;
     }
 
+    Signal<n> operator *(Signal<n> const &b) const
+    {
+        Signal<n> ret;
+        int x = 0;
+        for(size_t i = 0; i < n; i++){
+            for(size_t j = 0; j <= i; j++)
+                x += (int)_bits[j] & (int)b._bits[i-j];
+            ret._bits[i] = x & 1;
+            x >>= 1;
+        }
+        return ret;
+    }
+
+private:
+    Signal<n> divmod(Signal<n> const &b, bool modulo) const
+    {
+        if(!b.any()) return 0;
+        Signal<n> q = 0;
+        Signal<n> r = 0;
+        for(size_t i = n; i-- != 0; ){
+            r = r << Signal<1>(1);
+            r._bits[0] = _bits[i];
+            if(r >= b){
+                r = r - b;
+                q._bits[i] = true;
+            }
+        }
+        return modulo ? r : q;
+    }
+public:
+
+    Signal<n> operator /(Signal<n> const &b) const { return divmod(b, false); }
+    Signal<n> operator %(Signal<n> const &b) const { return divmod(b, true); }
+
     bool operator ==(Signal<n> const &b) const
     {
         for(size_t i = 0; i < n; i++)
diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index afddbd83440..55efc83c1c2 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -119,6 +119,12 @@ template <class NodeNames> struct SmtPrintVisitor {
 
 	std::string sub(Node, Node a, Node b, int) { return format("(bvsub %0 %1)", np(a), np(b)); }
 
+	std::string mul(Node, Node a, Node b, int) { return format("(bvmul %0 %1)", np(a), np(b)); }
+
+	std::string unsigned_div(Node, Node a, Node b, int) { return format("(bvudiv %0 %1)", np(a), np(b)); }
+
+	std::string unsigned_mod(Node, Node a, Node b, int) { return format("(bvurem %0 %1)", np(a), np(b)); }
+
 	std::string bitwise_and(Node, Node a, Node b, int) { return format("(bvand %0 %1)", np(a), np(b)); }
 
 	std::string bitwise_or(Node, Node a, Node b, int) { return format("(bvor %0 %1)", np(a), np(b)); }
diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc
index 3fd2d8240e7..6498ef63629 100644
--- a/kernel/functionalir.cc
+++ b/kernel/functionalir.cc
@@ -37,6 +37,15 @@ class CellSimplifier {
 			return factory.mux(lower_b, factory.constant(RTLIL::Const(y_width, new_width)), overflow, new_width);
 		}
 	}
+	T sign(T a, int a_width) {
+		return factory.slice(a, a_width, a_width - 1, 1);
+	}
+	T neg_if(T a, int a_width, T s) {
+		return factory.mux(a, factory.unary_minus(a, a_width), s, a_width);
+	}
+	T abs(T a, int a_width) {
+		return neg_if(a, a_width, sign(a, a_width));
+	}
 public:
 	T reduce_or(T a, int width) {
 		if (width == 1)
@@ -71,6 +80,23 @@ class CellSimplifier {
 		return factory.bitwise_or(aa, bb, width);
 	}
 	CellSimplifier(Factory &f) : factory(f) {}
+private:
+	T handle_pow(T a0, int a_width, T b, int b_width, int y_width, bool is_signed) {
+		T a = extend(a0, a_width, y_width, is_signed);
+		T r = factory.constant(Const(1, y_width));
+		for(int i = 0; i < b_width; i++) {
+			T b_bit = factory.slice(b, b_width, i, 1);
+			r = factory.mux(r, factory.mul(r, a, y_width), b_bit, y_width);
+			a = factory.mul(a, a, y_width);
+		}
+		if (is_signed) {
+			T a_ge_1 = factory.unsigned_greater_than(abs(a0, a_width), factory.constant(Const(1, a_width)), a_width);
+			T zero_result = factory.bitwise_and(a_ge_1, sign(b, b_width), 1);
+			r = factory.mux(r, factory.constant(Const(0, y_width)), zero_result, y_width);
+		}
+		return r;
+	}
+public:
 	T handle(IdString cellType, dict<IdString, Const> parameters, dict<IdString, T> inputs)
 	{
 		int a_width = parameters.at(ID(A_WIDTH), Const(-1)).as_int();
@@ -78,7 +104,7 @@ class CellSimplifier {
 		int y_width = parameters.at(ID(Y_WIDTH), Const(-1)).as_int();
 		bool a_signed = parameters.at(ID(A_SIGNED), Const(0)).as_bool();
 		bool b_signed = parameters.at(ID(B_SIGNED), Const(0)).as_bool();
-		if(cellType.in({ID($add), ID($sub), ID($and), ID($or), ID($xor), ID($xnor)})){
+		if(cellType.in({ID($add), ID($sub), ID($and), ID($or), ID($xor), ID($xnor), ID($mul)})){
 			bool is_signed = a_signed && b_signed;
 			T a = extend(inputs.at(ID(A)), a_width, y_width, is_signed);
 			T b = extend(inputs.at(ID(B)), b_width, y_width, is_signed);
@@ -86,6 +112,8 @@ class CellSimplifier {
 				return factory.add(a, b, y_width);
 			else if(cellType == ID($sub))
 				return factory.sub(a, b, y_width);
+			else if(cellType == ID($mul))
+				return factory.mul(a, b, y_width);
 			else if(cellType == ID($and))
 				return factory.bitwise_and(a, b, y_width);
 			else if(cellType == ID($or))
@@ -160,7 +188,7 @@ class CellSimplifier {
 			T b = inputs.at(ID(B));
 			T shr = logical_shift_right(a, b, width, b_width);
 			if(b_signed) {
-				T sign_b = factory.slice(b, b_width, b_width - 1, 1);
+				T sign_b = sign(b, b_width);
 				T shl = logical_shift_left(a, factory.unary_minus(b, b_width), width, b_width);
 				T y = factory.mux(shr, shl, sign_b, width);
 				return extend(y, width, y_width, false);
@@ -182,7 +210,46 @@ class CellSimplifier {
 			int offset = parameters.at(ID(OFFSET)).as_int();
 			T a = inputs.at(ID(A));
 			return factory.slice(a, a_width, offset, y_width);
-		}else{
+		}else if(cellType.in({ID($div), ID($mod), ID($divfloor), ID($modfloor)})) {
+			int width = max(a_width, b_width);
+			bool is_signed = a_signed && b_signed;
+			T a = extend(inputs.at(ID(A)), a_width, width, is_signed);
+			T b = extend(inputs.at(ID(B)), b_width, width, is_signed);
+			if(is_signed) {
+				if(cellType == ID($div)) {
+					T abs_y = factory.unsigned_div(abs(a, width), abs(b, width), width);
+					T out_sign = factory.not_equal(sign(a, width), sign(b, width), 1);
+					return neg_if(extend(abs_y, width, y_width, true), y_width, out_sign);
+				} else if(cellType == ID($mod)) {
+					T abs_y = factory.unsigned_mod(abs(a, width), abs(b, width), width);
+					return neg_if(extend(abs_y, width, y_width, true), y_width, sign(a, width));
+				} else if(cellType == ID($divfloor)) {
+					T b_sign = sign(b, width);
+					T a1 = neg_if(a, width, b_sign);
+					T b1 = neg_if(b, width, b_sign);
+					T a1_sign = sign(a1, width);
+					T a2 = factory.mux(a1, factory.bitwise_not(a1, width), a1_sign, width);
+					T y1 = factory.unsigned_div(a2, b1, width);
+					T y2 = factory.mux(y1, factory.bitwise_not(y1, width), a1_sign, width);
+					return extend(y2, width, y_width, true);
+				} else if(cellType == ID($modfloor)) {
+					T abs_b = abs(b, width);
+					T abs_y = factory.unsigned_mod(abs(a, width), abs_b, width);
+					T flip_y = factory.bitwise_and(factory.bitwise_xor(sign(a, width), sign(b, width), 1), factory.reduce_or(abs_y, width), 1);
+					T y_flipped = factory.mux(abs_y, factory.sub(abs_b, abs_y, width), flip_y, width);
+					T y = neg_if(y_flipped, width, sign(b, b_width));
+					return extend(y, width, y_width, true);
+				} else
+					log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str());
+			} else {
+				if(cellType.in({ID($mod), ID($modfloor)}))
+					return extend(factory.unsigned_mod(a, b, width), width, y_width, false);
+				else
+					return extend(factory.unsigned_div(a, b, width), width, y_width, false);
+			}
+		} else if(cellType == ID($pow)) {
+			return handle_pow(inputs.at(ID(A)), a_width, inputs.at(ID(B)), b_width, y_width, a_signed && b_signed);
+		} else{
 			log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str());
 		}
 	}
diff --git a/kernel/functionalir.h b/kernel/functionalir.h
index 2c0d0f55c2c..3e7c55ef4ec 100644
--- a/kernel/functionalir.h
+++ b/kernel/functionalir.h
@@ -39,6 +39,9 @@ class FunctionalIR {
 		concat,
 		add,
 		sub,
+		mul,
+		unsigned_div,
+		unsigned_mod,
 		bitwise_and,
 		bitwise_or,
 		bitwise_xor,
@@ -145,6 +148,9 @@ class FunctionalIR {
 			std::string concat(Node, Node a, int, Node b, int) { return "concat(" + np(a) + ", " + np(b) + ")"; }
 			std::string add(Node, Node a, Node b, int) { return "add(" + np(a) + ", " + np(b) + ")"; }
 			std::string sub(Node, Node a, Node b, int) { return "sub(" + np(a) + ", " + np(b) + ")"; }
+			std::string mul(Node, Node a, Node b, int) { return "mul(" + np(a) + ", " + np(b) + ")"; }
+			std::string unsigned_div(Node, Node a, Node b, int) { return "unsigned_div(" + np(a) + ", " + np(b) + ")"; }
+			std::string unsigned_mod(Node, Node a, Node b, int) { return "unsigned_mod(" + np(a) + ", " + np(b) + ")"; }
 			std::string bitwise_and(Node, Node a, Node b, int) { return "bitwise_and(" + np(a) + ", " + np(b) + ")"; }
 			std::string bitwise_or(Node, Node a, Node b, int) { return "bitwise_or(" + np(a) + ", " + np(b) + ")"; }
 			std::string bitwise_xor(Node, Node a, Node b, int) { return "bitwise_xor(" + np(a) + ", " + np(b) + ")"; }
@@ -193,11 +199,14 @@ class FunctionalIR {
 			case Fn::concat: return v.concat(*this, arg(0), arg(0).width(), arg(1), arg(1).width()); break;
 			case Fn::add: return v.add(*this, arg(0), arg(1), sort().width()); break;
 			case Fn::sub: return v.sub(*this, arg(0), arg(1), sort().width()); break;
+			case Fn::mul: return v.mul(*this, arg(0), arg(1), sort().width()); break;
+			case Fn::unsigned_div: return v.unsigned_div(*this, arg(0), arg(1), sort().width()); break;
+			case Fn::unsigned_mod: return v.unsigned_mod(*this, arg(0), arg(1), sort().width()); break;
 			case Fn::bitwise_and: return v.bitwise_and(*this, arg(0), arg(1), sort().width()); break;
 			case Fn::bitwise_or: return v.bitwise_or(*this, arg(0), arg(1), sort().width()); break;
 			case Fn::bitwise_xor: return v.bitwise_xor(*this, arg(0), arg(1), sort().width()); break;
 			case Fn::bitwise_not: return v.bitwise_not(*this, arg(0), sort().width()); break;
-			case Fn::unary_minus: return v.bitwise_not(*this, arg(0), sort().width()); break;
+			case Fn::unary_minus: return v.unary_minus(*this, arg(0), sort().width()); break;
 			case Fn::reduce_and: return v.reduce_and(*this, arg(0), arg(0).width()); break;
 			case Fn::reduce_or: return v.reduce_or(*this, arg(0), arg(0).width()); break;
 			case Fn::reduce_xor: return v.reduce_xor(*this, arg(0), arg(0).width()); break;
@@ -257,6 +266,9 @@ class FunctionalIR {
 		}
 		Node add(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::add, a.sort(), {a, b}); }
 		Node sub(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::sub, a.sort(), {a, b}); }
+		Node mul(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::mul, a.sort(), {a, b}); }
+		Node unsigned_div(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::unsigned_div, a.sort(), {a, b}); }
+		Node unsigned_mod(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::unsigned_mod, a.sort(), {a, b}); }
 		Node bitwise_and(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::bitwise_and, a.sort(), {a, b}); }
 		Node bitwise_or(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::bitwise_or, a.sort(), {a, b}); }
 		Node bitwise_xor(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::bitwise_xor, a.sort(), {a, b}); }
@@ -298,7 +310,8 @@ class FunctionalIR {
 			return add(Fn::buf, Sort(width), {});
 		}
 		void update_pending(Node node, Node value) {
-			log_assert(node._ref.function() == Fn::buf && node._ref.size() == 0 && node.sort() == value.sort());
+			log_assert(node._ref.function() == Fn::buf && node._ref.size() == 0);
+			log_assert(node.sort() == value.sort());
 			node._ref.append_arg(value._ref);
 		} 
 		Node input(IdString name, int width) {

From 57af68af96b534d32abbc636c0bc6f225a1f09a1 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Thu, 4 Jul 2024 19:21:38 +0200
Subject: [PATCH 396/499] include algorithm, needed for std::reverse

---
 backends/functional/cxx_runtime/sim.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h
index 040c6aefce8..950d4c5e10b 100644
--- a/backends/functional/cxx_runtime/sim.h
+++ b/backends/functional/cxx_runtime/sim.h
@@ -24,6 +24,7 @@
 #include <cassert>
 #include <string>
 #include <iostream>
+#include <algorithm>
 
 template<size_t n>
 class Signal {

From e296b884d5c1ddc610bb4ab916da4447ceb6d502 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 5 Jul 2024 14:50:00 +0200
Subject: [PATCH 397/499] Add Makefile helpers for coverage

---
 Makefile | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Makefile b/Makefile
index 1feeeab95d6..2bbb0dc5b48 100644
--- a/Makefile
+++ b/Makefile
@@ -1047,6 +1047,14 @@ coverage:
 	lcov --capture -d . --no-external -o coverage.info
 	genhtml coverage.info --output-directory coverage_html
 
+clean_coverage:
+	find . -name "*.gcda" -type f -delete
+
+coverage_functional:
+	rm -rf coverage.info coverage_html
+	lcov --capture -d backends/functional --no-external -o coverage.info
+	genhtml coverage.info --output-directory coverage_html
+
 qtcreator:
 	echo "$(CXXFLAGS)" | grep -o '\-D[^ ]*' | tr ' ' '\n' | sed 's/-D/#define /' | sed 's/=/ /'> qtcreator.config
 	{ for file in $(basename $(OBJS)); do \

From f0f436cbe7c870e947971e41c74232168dc77db4 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Fri, 5 Jul 2024 15:38:42 +0200
Subject: [PATCH 398/499] Fix parenthesis for arithmetic_shift_right

---
 backends/functional/cxx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index 81af54c073e..1d8caaaf440 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -124,7 +124,7 @@ template<class NodePrinter> struct CxxPrintVisitor {
 	void unsigned_greater_equal(Node, Node a, Node b, int) { print("{} >= {}", a, b); }
 	void logical_shift_left(Node, Node a, Node b, int, int) { print("{} << {}", a, b); }
 	void logical_shift_right(Node, Node a, Node b, int, int) { print("{} >> {}", a, b); }
-	void arithmetic_shift_right(Node, Node a, Node b, int, int) { print("{}.arithmetic_shift_right{})", a, b); }
+	void arithmetic_shift_right(Node, Node a, Node b, int, int) { print("{}.arithmetic_shift_right({})", a, b); }
 	void mux(Node, Node a, Node b, Node s, int) { print("{2}.any() ? {1} : {0}", a, b, s); }
 	void pmux(Node, Node a, Node b, Node s, int, int) { print("{0}.pmux({1}, {2})", a, b, s); }
 	void constant(Node, RTLIL::Const value) {

From 5780357cd91545ddda05a08bf701ac426ac227ed Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Sun, 7 Jul 2024 21:01:38 +0200
Subject: [PATCH 399/499] Emit valid SMT for stateful designs, fix some cells

---
 backends/functional/smtlib.cc                 | 581 +++++++++++-------
 tests/functional/.gitignore                   |   2 +-
 tests/functional/single_cells/run-test.sh     |   6 +
 .../single_cells/vcd_harness_smt.py           |   4 +-
 4 files changed, 358 insertions(+), 235 deletions(-)

diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index 55efc83c1c2..c496b537591 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -23,264 +23,379 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-const char illegal_characters[] = "$\\";
+const char illegal_characters[] = "#:\\";
 const char *reserved_keywords[] = {};
 
 struct SmtScope {
-	pool<std::string> used_names;
-	dict<IdString, std::string> name_map;
-	FunctionalTools::Scope scope;
-	SmtScope() : scope(illegal_characters, reserved_keywords) {}
-
-	void reserve(const std::string &name) { used_names.insert(name); }
-
-	std::string insert(IdString id)
-	{
-		std::string name = RTLIL::unescape_id(id);
-		if (used_names.count(name) == 0) {
-			used_names.insert(name);
-			name_map[id] = name;
-			return name;
-		}
-		for (int idx = 0;; ++idx) {
-			std::string new_name = name + "_" + std::to_string(idx);
-			if (used_names.count(new_name) == 0) {
-				used_names.insert(new_name);
-				name_map[id] = new_name;
-				return new_name;
-			}
-		}
-	}
-
-	std::string operator[](IdString id)
-	{
-		if (name_map.count(id)) {
-			return name_map[id];
-		} else {
-			return insert(id);
-		}
-	}
+  pool<std::string> used_names;
+  dict<IdString, std::string> name_map;
+  FunctionalTools::Scope scope;
+  SmtScope() : scope(illegal_characters, reserved_keywords) {}
+
+  void reserve(const std::string &name) { used_names.insert(name); }
+
+  std::string insert(IdString id)
+  {
+
+    std::string name = scope(id);
+    if (used_names.count(name) == 0) {
+      used_names.insert(name);
+      name_map[id] = name;
+      return name;
+    }
+    for (int idx = 0;; ++idx) {
+      std::string new_name = name + "_" + std::to_string(idx);
+      if (used_names.count(new_name) == 0) {
+	used_names.insert(new_name);
+	name_map[id] = new_name;
+	return new_name;
+      }
+    }
+  }
+
+  std::string operator[](IdString id)
+  {
+    if (name_map.count(id)) {
+      return name_map[id];
+    } else {
+      return insert(id);
+    }
+  }
 };
 
 struct SmtWriter {
-	std::ostream &stream;
+  std::ostream &stream;
 
-	SmtWriter(std::ostream &out) : stream(out) {}
+  SmtWriter(std::ostream &out) : stream(out) {}
 
-	void print(const char *fmt, ...)
-	{
-		va_list args;
-		va_start(args, fmt);
-		stream << vstringf(fmt, args);
-		va_end(args);
-	}
+  void print(const char *fmt, ...)
+  {
+    va_list args;
+    va_start(args, fmt);
+    stream << vstringf(fmt, args);
+    va_end(args);
+  }
 };
 
 template <class NodeNames> struct SmtPrintVisitor {
-	using Node = FunctionalIR::Node;
-	NodeNames np;
-	SmtScope &scope;
+  using Node = FunctionalIR::Node;
+  NodeNames np;
+  SmtScope &scope;
 
-	SmtPrintVisitor(NodeNames np, SmtScope &scope) : np(np), scope(scope) {}
+  SmtPrintVisitor(NodeNames np, SmtScope &scope) : np(np), scope(scope) {}
 
-	template <class T> std::string arg_to_string(T n) { return std::to_string(n); }
+  template <class T> std::string arg_to_string(T n) { return std::to_string(n); }
 
-	std::string arg_to_string(std::string n) { return n; }
+  std::string arg_to_string(std::string n) { return n; }
 
-	std::string arg_to_string(Node n) { return np(n); }
-
-	template <typename... Args> std::string format(std::string fmt, Args &&...args)
-	{
-		std::vector<std::string> arg_strings = {arg_to_string(std::forward<Args>(args))...};
-		for (size_t i = 0; i < arg_strings.size(); ++i) {
-			std::string placeholder = "%" + std::to_string(i);
-			size_t pos = 0;
-			while ((pos = fmt.find(placeholder, pos)) != std::string::npos) {
-				fmt.replace(pos, placeholder.length(), arg_strings[i]);
-				pos += arg_strings[i].length();
-			}
-		}
-		return fmt;
-	}
-	std::string buf(Node, Node n) { return np(n); }
-
-	std::string slice(Node, Node a, int, int offset, int out_width)
-	{
-		return format("(_ extract %1 %2 %0)", np(a), offset, offset + out_width - 1);
-	}
-
-	std::string zero_extend(Node, Node a, int, int out_width) { return format("((_ zero_extend %1) %0)", np(a), out_width - a.width()); }
-
-	std::string sign_extend(Node, Node a, int, int out_width) { return format("((_ sign_extend %1) %0)", np(a), out_width - a.width()); }
-
-	std::string concat(Node, Node a, int, Node b, int) { return format("(concat %0 %1)", np(a), np(b)); }
-
-	std::string add(Node, Node a, Node b, int) { return format("(bvadd %0 %1)", np(a), np(b)); }
-
-	std::string sub(Node, Node a, Node b, int) { return format("(bvsub %0 %1)", np(a), np(b)); }
-
-	std::string mul(Node, Node a, Node b, int) { return format("(bvmul %0 %1)", np(a), np(b)); }
-
-	std::string unsigned_div(Node, Node a, Node b, int) { return format("(bvudiv %0 %1)", np(a), np(b)); }
-
-	std::string unsigned_mod(Node, Node a, Node b, int) { return format("(bvurem %0 %1)", np(a), np(b)); }
-
-	std::string bitwise_and(Node, Node a, Node b, int) { return format("(bvand %0 %1)", np(a), np(b)); }
-
-	std::string bitwise_or(Node, Node a, Node b, int) { return format("(bvor %0 %1)", np(a), np(b)); }
-
-	std::string bitwise_xor(Node, Node a, Node b, int) { return format("(bvxor %0 %1)", np(a), np(b)); }
-
-	std::string bitwise_not(Node, Node a, int) { return format("(bvnot %0)", np(a)); }
-
-	std::string unary_minus(Node, Node a, int) { return format("(bvneg %0)", np(a)); }
-
-	std::string reduce_and(Node, Node a, int) { return format("(= %0 #b1)", np(a)); }
-
-	std::string reduce_or(Node, Node a, int)
-	{
-		std::stringstream ss;
-		// We use ite to set the result to bit vector, to ensure appropriate type
-		ss << "(ite (= " << np(a) << " #b" << std::string(a.width(), '0') << ") #b0 #b1)";
-		return ss.str();
-	}
-
-	std::string reduce_xor(Node, Node a, int) { return format("(bvxor_reduce %0)", np(a)); }
-
-	std::string equal(Node, Node a, Node b, int) { return format("(= %0 %1)", np(a), np(b)); }
-
-	std::string not_equal(Node, Node a, Node b, int) { return format("(distinct %0 %1)", np(a), np(b)); }
-
-	std::string signed_greater_than(Node, Node a, Node b, int) { return format("(bvsgt %0 %1)", np(a), np(b)); }
-
-	std::string signed_greater_equal(Node, Node a, Node b, int) { return format("(bvsge %0 %1)", np(a), np(b)); }
-
-	std::string unsigned_greater_than(Node, Node a, Node b, int) { return format("(bvugt %0 %1)", np(a), np(b)); }
-
-	std::string unsigned_greater_equal(Node, Node a, Node b, int) { return format("(bvuge %0 %1)", np(a), np(b)); }
-
-	std::string logical_shift_left(Node, Node a, Node b, int, int) { return format("(bvshl %0 %1)", np(a), np(b)); }
-
-	std::string logical_shift_right(Node, Node a, Node b, int, int) { return format("(bvlshr %0 %1)", np(a), np(b)); }
-
-	std::string arithmetic_shift_right(Node, Node a, Node b, int, int) { return format("(bvashr %0 %1)", np(a), np(b)); }
-
-	std::string mux(Node, Node a, Node b, Node s, int) { return format("(ite %2 %0 %1)", np(a), np(b), np(s)); }
-
-	std::string pmux(Node, Node a, Node b, Node s, int, int)
-	{
-		// Assume s is a bit vector, combine a and b based on the selection bits
-		return format("(pmux %0 %1 %2)", np(a), np(b), np(s));
-	}
-
-	std::string constant(Node, RTLIL::Const value) { return format("#b%1", value.as_string()); }
-
-	std::string input(Node, IdString name) { return format("%0", scope[name]); }
-
-	std::string state(Node, IdString name) { return format("%0", scope[name]); }
-
-	std::string memory_read(Node, Node mem, Node addr, int, int) { return format("(select %0 %1)", np(mem), np(addr)); }
-
-	std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { return format("(store %0 %1 %2)", np(mem), np(addr), np(data)); }
-
-	std::string undriven(Node, int width) { return format("#b%0", std::string(width, '0')); }
+  std::string arg_to_string(Node n) { return np(n); }
+
+  template <typename... Args> std::string format(std::string fmt, Args &&...args)
+  {
+    std::vector<std::string> arg_strings = {arg_to_string(std::forward<Args>(args))...};
+    for (size_t i = 0; i < arg_strings.size(); ++i) {
+      std::string placeholder = "%" + std::to_string(i);
+      size_t pos = 0;
+      while ((pos = fmt.find(placeholder, pos)) != std::string::npos) {
+	fmt.replace(pos, placeholder.length(), arg_strings[i]);
+	pos += arg_strings[i].length();
+      }
+    }
+    return fmt;
+  }
+  std::string buf(Node, Node n) { return np(n); }
+
+  std::string slice(Node, Node a, int, int offset, int out_width)
+  {
+    return format("((_ extract %2 %1) %0)", np(a), offset, offset + out_width - 1);
+  }
+
+  std::string zero_extend(Node, Node a, int, int out_width) { return format("((_ zero_extend %1) %0)", np(a), out_width - a.width()); }
+
+  std::string sign_extend(Node, Node a, int, int out_width) { return format("((_ sign_extend %1) %0)", np(a), out_width - a.width()); }
+
+  std::string concat(Node, Node a, int, Node b, int) { return format("(concat %0 %1)", np(a), np(b)); }
+
+  std::string add(Node, Node a, Node b, int) { return format("(bvadd %0 %1)", np(a), np(b)); }
+
+  std::string sub(Node, Node a, Node b, int) { return format("(bvsub %0 %1)", np(a), np(b)); }
+
+  std::string mul(Node, Node a, Node b, int) { return format("(bvmul %0 %1)", np(a), np(b)); }
+
+  std::string unsigned_div(Node, Node a, Node b, int) { return format("(bvudiv %0 %1)", np(a), np(b)); }
+
+  std::string unsigned_mod(Node, Node a, Node b, int) { return format("(bvurem %0 %1)", np(a), np(b)); }
+
+  std::string bitwise_and(Node, Node a, Node b, int) { return format("(bvand %0 %1)", np(a), np(b)); }
+
+  std::string bitwise_or(Node, Node a, Node b, int) { return format("(bvor %0 %1)", np(a), np(b)); }
+
+  std::string bitwise_xor(Node, Node a, Node b, int) { return format("(bvxor %0 %1)", np(a), np(b)); }
+
+  std::string bitwise_not(Node, Node a, int) { return format("(bvnot %0)", np(a)); }
+
+  std::string unary_minus(Node, Node a, int) { return format("(bvneg %0)", np(a)); }
+
+  std::string reduce_and(Node, Node a, int) {
+    std::stringstream ss;
+    // We use ite to set the result to bit vector, to ensure appropriate type
+    ss << "(ite (= " << np(a) << " #b" << std::string(a.width(), '1') << ") #b1 #b0)";
+    return ss.str();
+  }
+ 
+  std::string reduce_or(Node, Node a, int)
+  {
+    std::stringstream ss;
+    // We use ite to set the result to bit vector, to ensure appropriate type
+    ss << "(ite (= " << np(a) << " #b" << std::string(a.width(), '0') << ") #b0 #b1)";
+    return ss.str();
+  }
+
+  std::string reduce_xor(Node, Node a, int) {
+    std::stringstream ss;
+    ss << "(bvxor ";
+    for (int i = 0; i < a.width(); ++i) {
+      if (i > 0) ss << " ";
+      ss << "((_ extract " << i << " " << i << ") " << np(a) << ")";
+    }
+    ss << ")";
+    return ss.str();
+  }
+ 
+  std::string equal(Node, Node a, Node b, int) {
+    return format("(ite (= %0 %1) #b1 #b0)", np(a), np(b));
+  }
+
+  std::string not_equal(Node, Node a, Node b, int) {
+    return format("(ite (distinct %0 %1) #b1 #b0)", np(a), np(b));
+  }
+
+  std::string signed_greater_than(Node, Node a, Node b, int) { 
+    return format("(ite (bvsgt %0 %1) #b1 #b0)", np(a), np(b)); 
+  }
+
+  std::string signed_greater_equal(Node, Node a, Node b, int) {
+    return format("(ite (bvsge %0 %1) #b1 #b0)", np(a), np(b));
+  }
+
+  std::string unsigned_greater_than(Node, Node a, Node b, int) { 
+    return format("(ite (bvugt %0 %1) #b1 #b0)", np(a), np(b)); 
+  }
+
+  std::string unsigned_greater_equal(Node, Node a, Node b, int) { 
+    return format("(ite (bvuge %0 %1) #b1 #b0)", np(a), np(b)); 
+  }
+
+  std::string logical_shift_left(Node, Node a, Node b, int, int) {
+    // Get the bit-widths of a and b
+    int bit_width_a = a.width();
+    int bit_width_b = b.width();
+
+    // Extend b to match the bit-width of a if necessary
+    std::ostringstream oss;
+    if (bit_width_a > bit_width_b) {
+      oss << "((_ zero_extend " << (bit_width_a - bit_width_b) << ") " << np(b) << ")";
+    } else {
+      oss << np(b);  // No extension needed if b's width is already sufficient
+    }
+    std::string b_extended = oss.str();
+
+    // Format the bvshl operation with the extended b
+    oss.str(""); // Clear the stringstream
+    oss << "(bvshl " << np(a) << " " << b_extended << ")";
+    return oss.str();
+  }
+
+  std::string logical_shift_right(Node, Node a, Node b, int, int) {
+    // Get the bit-widths of a and b
+    int bit_width_a = a.width();
+    int bit_width_b = b.width();
+
+    // Extend b to match the bit-width of a if necessary
+    std::ostringstream oss;
+    if (bit_width_a > bit_width_b) {
+      oss << "((_ zero_extend " << (bit_width_a - bit_width_b) << ") " << np(b) << ")";
+    } else {
+      oss << np(b);  // No extension needed if b's width is already sufficient
+    }
+    std::string b_extended = oss.str();
+
+    // Format the bvlshr operation with the extended b
+    oss.str(""); // Clear the stringstream
+    oss << "(bvlshr " << np(a) << " " << b_extended << ")";
+    return oss.str();
+  }
+
+  std::string arithmetic_shift_right(Node, Node a, Node b, int, int) {
+    // Get the bit-widths of a and b
+    int bit_width_a = a.width();
+    int bit_width_b = b.width();
+
+    // Extend b to match the bit-width of a if necessary
+    std::ostringstream oss;
+    if (bit_width_a > bit_width_b) {
+      oss << "((_ zero_extend " << (bit_width_a - bit_width_b) << ") " << np(b) << ")";
+    } else {
+      oss << np(b);  // No extension needed if b's width is already sufficient
+    }
+    std::string b_extended = oss.str();
+
+    // Format the bvashr operation with the extended b
+    oss.str(""); // Clear the stringstream
+    oss << "(bvashr " << np(a) << " " << b_extended << ")";
+    return oss.str();
+  }
+ 
+  std::string mux(Node, Node a, Node b, Node s, int) {
+    return format("(ite (= %2 #b1) %0 %1)", np(a), np(b), np(s));
+  }
+
+  std::string pmux(Node, Node a, Node b, Node s, int, int)
+  {
+    // Assume s is a bit vector, combine a and b based on the selection bits
+    return format("(pmux %0 %1 %2)", np(a), np(b), np(s));
+  }
+
+  std::string constant(Node, RTLIL::Const value) { return format("#b%0", value.as_string()); }
+
+  std::string input(Node, IdString name) { return format("%0", scope[name]); }
+
+  std::string state(Node, IdString name) { return format("(%0 current_state)", scope[name]); }
+
+  std::string memory_read(Node, Node mem, Node addr, int, int) { return format("(select %0 %1)", np(mem), np(addr)); }
+
+  std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { return format("(store %0 %1 %2)", np(mem), np(addr), np(data)); }
+
+  std::string undriven(Node, int width) { return format("#b%0", std::string(width, '0')); }
 };
 
 struct SmtModule {
-	std::string name;
-	SmtScope scope;
-	FunctionalIR ir;
-
-	SmtModule(const std::string &module_name, FunctionalIR ir) : name(module_name), ir(std::move(ir)) {}
-
-	void write(std::ostream &out)
-	{
-		SmtWriter writer(out);
-
-		writer.print("(declare-fun %s () Bool)\n", name.c_str());
-		writer.print("(declare-datatypes () ((Inputs (mk_inputs");
-		for (const auto &input : ir.inputs()) {
-			std::string input_name = scope[input.first];
-			writer.print(" (%s (_ BitVec %d))", input_name.c_str(), input.second.width());
-		}
-		writer.print("))))\n");
-
-		writer.print("(declare-datatypes () ((Outputs (mk_outputs");
-		for (const auto &output : ir.outputs()) {
-			std::string output_name = scope[output.first];
-			writer.print(" (%s (_ BitVec %d))", output_name.c_str(), output.second.width());
-		}
-		writer.print("))))\n");
-
-		writer.print("(declare-fun state () (_ BitVec 1))\n");
-
-		writer.print("(define-fun %s_step ((state (_ BitVec 1)) (inputs Inputs)) Outputs", name.c_str());
-		writer.print("  (let (");
-		for (const auto &input : ir.inputs()) {
-			std::string input_name = scope[input.first];
-			writer.print("    (%s (%s inputs))", input_name.c_str(), input_name.c_str());
-		}
-		writer.print("  )");
-
-		auto node_to_string = [&](FunctionalIR::Node n) { return scope[n.name()]; };
-		SmtPrintVisitor<decltype(node_to_string)> visitor(node_to_string, scope);
-
-		for (auto it = ir.begin(); it != ir.end(); ++it) {
-			const FunctionalIR::Node &node = *it;
-
-			if (ir.inputs().count(node.name()) > 0)
-				continue;
-
-			std::string node_name = scope[node.name()];
-			std::string node_expr = node.visit(visitor);
-
-			writer.print("  (let (      (%s %s))", node_name.c_str(), node_expr.c_str());
-		}
-
-		writer.print("    (let (");
-		for (const auto &output : ir.outputs()) {
-			std::string output_name = scope[output.first];
-			const std::string output_assignment = ir.get_output_node(output.first).name().c_str();
-			writer.print("      (%s %s)", output_name.c_str(), output_assignment.substr(1).c_str());
-		}
-		writer.print("    )");
-		writer.print("      (mk_outputs");
-		for (const auto &output : ir.outputs()) {
-			std::string output_name = scope[output.first];
-			writer.print("        %s", output_name.c_str());
-		}
-		writer.print("      )");
-		writer.print("    )");
-
-		// Close the nested lets
-		for (size_t i = 0; i < ir.size() - ir.inputs().size(); ++i) {
-			writer.print("  )");
-		}
-
-		writer.print("  )");
-		writer.print(")\n");
-	}
+  std::string name;
+  SmtScope scope;
+  FunctionalIR ir;
+
+  SmtModule(const std::string &module_name, FunctionalIR ir) : name(module_name), ir(std::move(ir)) {}
+
+  void write(std::ostream &out)
+  {
+    const bool stateful = ir.state().size() != 0;
+    SmtWriter writer(out);
+
+    writer.print("(declare-fun %s () Bool)\n\n", name.c_str());
+
+    writer.print("(declare-datatypes ()  ((Inputs    (mk_inputs");
+    for (const auto &input : ir.inputs()) {
+      std::string input_name = scope[input.first];
+      writer.print(" (%s (_ BitVec %d))", input_name.c_str(), input.second.width());
+    }
+    writer.print("))))\n\n");
+
+    writer.print("(declare-datatypes () ((Outputs    (mk_outputs");
+    for (const auto &output : ir.outputs()) {
+      std::string output_name = scope[output.first];
+      writer.print(" (%s (_ BitVec %d))", output_name.c_str(), output.second.width());
+    }
+    writer.print("))))\n");
+
+    if (stateful) {
+      writer.print("(declare-datatypes ()  ((State   (mk_state");
+      for (const auto &state : ir.state()) {
+	std::string state_name = scope[state.first];
+	writer.print(" (%s (_ BitVec %d))", state_name.c_str(), state.second.width());
+      }
+      writer.print("))))\n");
+
+      writer.print("(declare-datatypes ()  ((Pair   (mk-pair (outputs Outputs) (next_state State)))))\n");
+    }
+
+    if (stateful)
+      writer.print("(define-fun %s_step ((current_state State) (inputs Inputs)) Pair", name.c_str());
+    else
+      writer.print("(define-fun %s_step ((inputs Inputs)) Outputs", name.c_str());
+
+    writer.print(" (let (");
+    for (const auto &input : ir.inputs()) {
+      std::string input_name = scope[input.first];
+      writer.print(" (%s (%s inputs))", input_name.c_str(), input_name.c_str());
+    }
+    writer.print(" )");
+
+    auto node_to_string = [&](FunctionalIR::Node n) { return scope[n.name()]; };
+    SmtPrintVisitor<decltype(node_to_string)> visitor(node_to_string, scope);
+
+    for (auto it = ir.begin(); it != ir.end(); ++it) {
+      const FunctionalIR::Node &node = *it;
+
+      if (ir.inputs().count(node.name()) > 0)
+	continue;
+
+      std::string node_name = scope[node.name()];
+      std::string node_expr = node.visit(visitor);
+
+      writer.print(" (let ( (%s %s))", node_name.c_str(), node_expr.c_str());
+    }
+
+    if (stateful) {
+      writer.print(" (let ( (next_state (mk_state ");
+      for (const auto &state : ir.state()) {
+	std::string state_name = scope[state.first];
+	const std::string state_assignment = ir.get_state_next_node(state.first).name().c_str();
+	writer.print(" %s", state_assignment.substr(1).c_str());
+      }
+      writer.print(" )))");
+    }
+
+    if (stateful) {
+      writer.print(" (let ( (outputs (mk_outputs ");
+      for (const auto &output : ir.outputs()) {
+	std::string output_name = scope[output.first];
+	writer.print(" %s", output_name.c_str());
+      }
+      writer.print(" )))");
+
+      writer.print("(mk-pair outputs next_state)");
+    }
+    else {
+      writer.print(" (mk_outputs ");
+      for (const auto &output : ir.outputs()) {
+	std::string output_name = scope[output.first];
+	writer.print(" %s", output_name.c_str());
+      }
+      writer.print(" )"); // Closing mk_outputs 
+    }
+    if (stateful) {
+      writer.print(" )"); // Closing outputs let statement
+      writer.print(" )"); // Closing next_state let statement
+    }
+    // Close the nested lets
+    for (size_t i = 0; i < ir.size() - ir.inputs().size(); ++i) {
+      writer.print(" )"); // Closing each node
+    }
+
+    writer.print(" )"); // Closing inputs let statement
+    writer.print(")\n"); // Closing step function
+  }
 };
 
 struct FunctionalSmtBackend : public Backend {
-	FunctionalSmtBackend() : Backend("functional_smt2", "Generate SMT-LIB from Functional IR") {}
+  FunctionalSmtBackend() : Backend("functional_smt2", "Generate SMT-LIB from Functional IR") {}
 
-	void help() override { log("\nFunctional SMT Backend.\n\n"); }
+  void help() override { log("\nFunctional SMT Backend.\n\n"); }
 
-	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
-	{
-		log_header(design, "Executing Functional SMT Backend.\n");
+  void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
+  {
+    log_header(design, "Executing Functional SMT Backend.\n");
 
-		size_t argidx = 1;
-		extra_args(f, filename, args, argidx, design);
+    size_t argidx = 1;
+    extra_args(f, filename, args, argidx, design);
 
-		for (auto module : design->selected_modules()) {
-			log("Processing module `%s`.\n", module->name.c_str());
-			auto ir = FunctionalIR::from_module(module);
-			SmtModule smt(RTLIL::unescape_id(module->name), ir);
-			smt.write(*f);
-		}
-	}
+    for (auto module : design->selected_modules()) {
+      log("Processing module `%s`.\n", module->name.c_str());
+      auto ir = FunctionalIR::from_module(module);
+      SmtModule smt(RTLIL::unescape_id(module->name), ir);
+      smt.write(*f);
+    }
+  }
 } FunctionalSmtBackend;
 
 PRIVATE_NAMESPACE_END
diff --git a/tests/functional/.gitignore b/tests/functional/.gitignore
index 8b20fbedf55..1ffe9926ef6 100644
--- a/tests/functional/.gitignore
+++ b/tests/functional/.gitignore
@@ -2,4 +2,4 @@ my_module_cxxrtl.cc
 my_module_functional_cxx.cc
 vcd_harness
 *.vcd
-*.smt2
\ No newline at end of file
+*.smt2
diff --git a/tests/functional/single_cells/run-test.sh b/tests/functional/single_cells/run-test.sh
index 11ff1b5ce0b..cc6bcf16086 100755
--- a/tests/functional/single_cells/run-test.sh
+++ b/tests/functional/single_cells/run-test.sh
@@ -87,6 +87,10 @@ run_smt_test() {
 
 
 run_all_tests() {
+    declare -A cxx_failing_files
+    declare -A smt_failing_files
+    declare -A cxx_successful_files
+    declare -A smt_successful_files
     return_code=0
     for rtlil_file in rtlil/*.il; do
         run_cxx_test "$rtlil_file"
@@ -134,6 +138,8 @@ run_all_tests() {
 }
 
 run_smt_tests() {
+    declare -A smt_failing_files
+    declare -A smt_successful_files
     return_code=0
     for rtlil_file in rtlil/*.il; do
         run_smt_test "$rtlil_file"
diff --git a/tests/functional/single_cells/vcd_harness_smt.py b/tests/functional/single_cells/vcd_harness_smt.py
index fd5e94f7e2f..88973eae0d1 100644
--- a/tests/functional/single_cells/vcd_harness_smt.py
+++ b/tests/functional/single_cells/vcd_harness_smt.py
@@ -76,6 +76,8 @@
             declarations = datatype_group[1][1:]  # Skip the first item (e.g., 'mk_inputs')
             if datatype_name == 'Inputs':
                 for declaration in declarations:
+                    print("My declaration")
+                    print(declaration)
                     input_name = declaration[0]
                     bitvec_size = declaration[1][2]
                     inputs[input_name] = int(bitvec_size)
@@ -103,7 +105,7 @@ def set_step(inputs, step):
     define_inputs = f"(define-const test_inputs_step_n{step} Inputs ({mk_inputs_call}))\n"
 
     # Create the output definition by calling the gold_step function
-    define_output = f"(define-const test_outputs_step_n{step} Outputs (gold_step #b0 test_inputs_step_n{step}))\n"
+    define_output = f"(define-const test_outputs_step_n{step} Outputs (gold_step test_inputs_step_n{step}))\n"
     smt_commands = []
     smt_commands.append(define_inputs)
     smt_commands.append(define_output)

From fad76ce67785c519ca6ed982a7916ccebf5f5411 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Sun, 7 Jul 2024 21:12:47 +0200
Subject: [PATCH 400/499] Fix memory leak

---
 backends/functional/smtlib.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index c496b537591..bc1253b8837 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -24,7 +24,7 @@ USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
 const char illegal_characters[] = "#:\\";
-const char *reserved_keywords[] = {};
+const char *reserved_keywords[] = {nullptr};
 
 struct SmtScope {
   pool<std::string> used_names;

From 7cff8fa3a31e999aa16a3f4ab25894939d08bb70 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Sun, 7 Jul 2024 21:29:33 +0200
Subject: [PATCH 401/499] Fix corner case of pos cell with input and output
 being same width

---
 backends/functional/smtlib.cc                       |  4 +++-
 .../single_cells/rtlil/test_cell_pos_00001.il       | 13 +++++++++++++
 2 files changed, 16 insertions(+), 1 deletion(-)
 create mode 100644 tests/functional/single_cells/rtlil/test_cell_pos_00001.il

diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index bc1253b8837..501d195ebde 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -277,7 +277,7 @@ struct SmtModule {
   SmtModule(const std::string &module_name, FunctionalIR ir) : name(module_name), ir(std::move(ir)) {}
 
   void write(std::ostream &out)
-  {
+  {    
     const bool stateful = ir.state().size() != 0;
     SmtWriter writer(out);
 
@@ -371,6 +371,8 @@ struct SmtModule {
     for (size_t i = 0; i < ir.size() - ir.inputs().size(); ++i) {
       writer.print(" )"); // Closing each node
     }
+    if (ir.size() == ir.inputs().size())
+      writer.print(" )"); // Corner case
 
     writer.print(" )"); // Closing inputs let statement
     writer.print(")\n"); // Closing step function
diff --git a/tests/functional/single_cells/rtlil/test_cell_pos_00001.il b/tests/functional/single_cells/rtlil/test_cell_pos_00001.il
new file mode 100644
index 00000000000..96e9c895a18
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/test_cell_pos_00001.il
@@ -0,0 +1,13 @@
+# Generated by Yosys 0.40+7 (git sha1 d8b5b90e7, g++ 13.2.0 -Og -fPIC)
+autoidx 1
+module \gold
+  wire width 6 input 1 \A
+  wire width 6 output 2 \Y
+  cell $pos \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \Y \Y
+  end
+end

From 566e57d24f45dbffec8b40a58d1ef15b45b9bb52 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Mon, 8 Jul 2024 00:07:07 +0200
Subject: [PATCH 402/499] Support $lut cells. Both C++ and SMT tests pass

---
 kernel/functionalir.cc | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc
index 6498ef63629..c5406f41283 100644
--- a/kernel/functionalir.cc
+++ b/kernel/functionalir.cc
@@ -248,9 +248,31 @@ class CellSimplifier {
 					return extend(factory.unsigned_div(a, b, width), width, y_width, false);
 			}
 		} else if(cellType == ID($pow)) {
-			return handle_pow(inputs.at(ID(A)), a_width, inputs.at(ID(B)), b_width, y_width, a_signed && b_signed);
+		  return handle_pow(inputs.at(ID(A)), a_width, inputs.at(ID(B)), b_width, y_width, a_signed && b_signed);
+		} else if (cellType == ID($lut)) {
+		  int width = parameters.at(ID(WIDTH)).as_int();
+		  Const lut_table = parameters.at(ID(LUT));
+		  T a = inputs.at(ID(A));
+
+		  // Output initialization
+		  T y = factory.constant(Const(0, 1));
+
+		  // Iterate over each possible input combination
+		  for (int i = 0; i < (1 << width); ++i) {
+		    // Create a constant representing the value of i
+		    T i_val = factory.constant(Const(i, width));
+		    // Check if the input matches this value
+		    T match = factory.equal(a, i_val, width);
+		    // Get the corresponding LUT value
+		    bool lut_val = lut_table.bits[i] == State::S1;
+		    T lut_output = factory.constant(Const(lut_val, 1));
+		    // Use a multiplexer to select the correct output based on the match
+		    y = factory.mux(y, lut_output, match, 1);
+		  }
+
+		  return y;
 		} else{
-			log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str());
+		  log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str());
 		}
 	}
 };

From 80582ed3afb7ebbfe1372dd97f57062b68c1eb79 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Mon, 8 Jul 2024 18:29:58 +0200
Subject: [PATCH 403/499] Check the existance of a different set of outputs. No
 need for (push 1) nor (pop 1)

---
 .../single_cells/rtlil/multiple_outputs.il    | 69 +++++++++++++++++++
 .../single_cells/vcd_harness_smt.py           | 28 ++++----
 2 files changed, 82 insertions(+), 15 deletions(-)
 create mode 100644 tests/functional/single_cells/rtlil/multiple_outputs.il

diff --git a/tests/functional/single_cells/rtlil/multiple_outputs.il b/tests/functional/single_cells/rtlil/multiple_outputs.il
new file mode 100644
index 00000000000..5e9141a20ad
--- /dev/null
+++ b/tests/functional/single_cells/rtlil/multiple_outputs.il
@@ -0,0 +1,69 @@
+# Generated by Yosys 0.40+7 (git sha1 cc795a3f5, g++ 13.2.0 -Og -fPIC)
+autoidx 5
+attribute \cells_not_processed 1
+attribute \src "multiple_outputs.v:1.1-15.10"
+module \gold
+  attribute \src "multiple_outputs.v:11.12-11.20"
+  wire $and$multiple_outputs.v:11$2_Y
+  attribute \src "multiple_outputs.v:10.12-10.14"
+  wire $not$multiple_outputs.v:10$1_Y
+  attribute \src "multiple_outputs.v:12.12-12.20"
+  wire $or$multiple_outputs.v:12$3_Y
+  attribute \src "multiple_outputs.v:13.12-13.20"
+  wire $xor$multiple_outputs.v:13$4_Y
+  attribute \src "multiple_outputs.v:2.16-2.17"
+  wire input 1 \a
+  attribute \src "multiple_outputs.v:3.17-3.18"
+  wire output 2 \b
+  attribute \src "multiple_outputs.v:4.17-4.18"
+  wire output 3 \c
+  attribute \src "multiple_outputs.v:5.17-5.18"
+  wire output 4 \d
+  attribute \src "multiple_outputs.v:6.17-6.18"
+  wire output 5 \e
+  attribute \src "multiple_outputs.v:11.12-11.20"
+  cell $and $and$multiple_outputs.v:11$2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \a
+    connect \B 1'1
+    connect \Y $and$multiple_outputs.v:11$2_Y
+  end
+  attribute \src "multiple_outputs.v:10.12-10.14"
+  cell $not $not$multiple_outputs.v:10$1
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \a
+    connect \Y $not$multiple_outputs.v:10$1_Y
+  end
+  attribute \src "multiple_outputs.v:12.12-12.20"
+  cell $or $or$multiple_outputs.v:12$3
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \a
+    connect \B 1'0
+    connect \Y $or$multiple_outputs.v:12$3_Y
+  end
+  attribute \src "multiple_outputs.v:13.12-13.20"
+  cell $xor $xor$multiple_outputs.v:13$4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \a
+    connect \B 1'1
+    connect \Y $xor$multiple_outputs.v:13$4_Y
+  end
+  connect \b $not$multiple_outputs.v:10$1_Y
+  connect \c $and$multiple_outputs.v:11$2_Y
+  connect \d $or$multiple_outputs.v:12$3_Y
+  connect \e $xor$multiple_outputs.v:13$4_Y
+end
diff --git a/tests/functional/single_cells/vcd_harness_smt.py b/tests/functional/single_cells/vcd_harness_smt.py
index 88973eae0d1..95947748ffe 100644
--- a/tests/functional/single_cells/vcd_harness_smt.py
+++ b/tests/functional/single_cells/vcd_harness_smt.py
@@ -139,9 +139,6 @@ def set_step(inputs, step):
     smt_io.p_close()
     sys.exit(1)
 
-value = smt_io.get(f'(Y test_outputs_step_n0)')
-print(f"  Y: {value}")
-
 # Store signal values
 signals = {name: [] for name in list(inputs.keys()) + list(outputs.keys())}
 # Retrieve and print values for each state
@@ -151,6 +148,8 @@ def hex_to_bin(value):
         bin_value = bin(int(hex_value, 16))[2:]  # Convert to binary and remove the '0b' prefix
         return f'b{bin_value.zfill(len(hex_value) * 4)}'  # Add 'b' prefix and pad with zeros
     return value
+
+combined_assertions = []
 for step in range(num_steps):
     print(f"Values for step {step + 1}:")
     for input_name, width in inputs.items():
@@ -163,18 +162,17 @@ def hex_to_bin(value):
         value = hex_to_bin(value[1:])
         print(f"  {output_name}: {value}")
         signals[output_name].append((step, value))
-        smt_io.write(f'(push 1)')
-        smt_io.write(f'(assert (not (= ({output_name} test_outputs_step_n{step}) #{value})))')
-        result = smt_io.check_sat(["unsat"])
-        if result != 'unsat':
-            smt_io.p_close()
-            sys.exit(1)
-        smt_io.write(f'(pop 1)')
-        result = smt_io.check_sat(["sat"])
-        if result != 'sat':
-            smt_io.p_close()
-            sys.exit(1)
-        
+        combined_assertions.append(f'(= ({output_name} test_outputs_step_n{step}) #{value})')
+# Create a single assertion covering all timesteps
+combined_condition = " ".join(combined_assertions)
+smt_io.write(f'(assert (not (and {combined_condition})))')
+
+# Check the combined assertion
+result = smt_io.check_sat(["unsat"])
+if result != 'unsat':
+    smt_io.p_close()
+    sys.exit(1)
+
 smt_io.p_close()
 
 def write_vcd(filename, signals, timescale='1 ns', date='today'):

From 9f660b1e4bf125db23d7f5c494d3c5f9fd715ee7 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Wed, 10 Jul 2024 14:28:48 +0100
Subject: [PATCH 404/499] rewrite smtlib pass to use SExpr class

---
 backends/functional/cxx.cc    |  28 +-
 backends/functional/smtlib.cc | 725 +++++++++++++++++-----------------
 kernel/functionalir.h         |  45 +--
 3 files changed, 409 insertions(+), 389 deletions(-)

diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index 1d8caaaf440..4ab9d53a1d4 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -19,11 +19,11 @@
 
 #include "kernel/yosys.h"
 #include "kernel/functionalir.h"
+#include <ctype.h>
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-const char illegal_characters[] = "!\"#%&'()*+,-./:;<=>?@[]\\^`{|}~ ";
 const char *reserved_keywords[] = {
 	"alignas","alignof","and","and_eq","asm","atomic_cancel","atomic_commit",
 	"atomic_noexcept","auto","bitand","bitor","bool","break","case",
@@ -42,6 +42,16 @@ const char *reserved_keywords[] = {
 	nullptr
 };
 
+template<typename Id> struct CxxScope : public FunctionalTools::Scope<Id> {
+	CxxScope() {
+		for(const char **p = reserved_keywords; *p != nullptr; p++)
+			this->reserve(*p);
+	}
+	bool is_character_legal(char c) override {
+		return isascii(c) && (isalnum(c) || c == '_' || c == '$');
+	}
+};
+
 struct CxxType {
 	FunctionalIR::Sort sort;
 	CxxType(FunctionalIR::Sort sort) : sort(sort) {}
@@ -61,30 +71,30 @@ using CxxWriter = FunctionalTools::Writer;
 struct CxxStruct {
   std::string name;
   dict<IdString, CxxType> types;
-  FunctionalTools::Scope scope;
+  CxxScope<IdString> scope;
   CxxStruct(std::string name)
-    : name(name), scope(illegal_characters, reserved_keywords) {
+    : name(name) {
     scope.reserve("fn");
     scope.reserve("visit");
   }
   void insert(IdString name, CxxType type) {
-    scope(name);
+    scope(name, name);
     types.insert({name, type});
   }
   void print(CxxWriter &f) {
     f.print("\tstruct {} {{\n", name);
     for (auto p : types) {
-      f.print("\t\t{} {};\n", p.second.to_string(), scope(p.first));
+      f.print("\t\t{} {};\n", p.second.to_string(), scope(p.first, p.first));
     }
     f.print("\n\t\ttemplate <typename T> void visit(T &&fn) {{\n");
     for (auto p : types) {
-      f.print("\t\t\tfn(\"{}\", {});\n", RTLIL::unescape_id(p.first), scope(p.first));
+      f.print("\t\t\tfn(\"{}\", {});\n", RTLIL::unescape_id(p.first), scope(p.first, p.first));
     }
     f.print("\t\t}}\n");
     f.print("\t}};\n\n");
   };
   std::string operator[](IdString field) {
-    return scope(field);
+    return scope(field, field);
   }
 };
 
@@ -165,7 +175,7 @@ struct CxxModule {
 			output_struct.insert(name, sort);
 		for (auto [name, sort] : ir.state())
 			state_struct.insert(name, sort);
-		module_name = FunctionalTools::Scope(illegal_characters, reserved_keywords)(module->name);
+		module_name = CxxScope<int>().unique_name(module->name);
 	}
 	void write_header(CxxWriter &f) {
 		f.print("#include \"sim.h\"\n\n");
@@ -180,7 +190,7 @@ struct CxxModule {
 	}
 	void write_eval_def(CxxWriter &f) {
 		f.print("void {0}::eval({0}::Inputs const &input, {0}::Outputs &output, {0}::State const &current_state, {0}::State &next_state)\n{{\n", module_name);
-		FunctionalTools::Scope locals(illegal_characters, reserved_keywords);
+		CxxScope<int> locals;
 		locals.reserve("input");
 		locals.reserve("output");
 		locals.reserve("current_state");
diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index 501d195ebde..c3e159eb31e 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -19,385 +19,406 @@
 
 #include "kernel/functionalir.h"
 #include "kernel/yosys.h"
+#include <ctype.h>
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-const char illegal_characters[] = "#:\\";
-const char *reserved_keywords[] = {nullptr};
-
-struct SmtScope {
-  pool<std::string> used_names;
-  dict<IdString, std::string> name_map;
-  FunctionalTools::Scope scope;
-  SmtScope() : scope(illegal_characters, reserved_keywords) {}
-
-  void reserve(const std::string &name) { used_names.insert(name); }
-
-  std::string insert(IdString id)
-  {
-
-    std::string name = scope(id);
-    if (used_names.count(name) == 0) {
-      used_names.insert(name);
-      name_map[id] = name;
-      return name;
-    }
-    for (int idx = 0;; ++idx) {
-      std::string new_name = name + "_" + std::to_string(idx);
-      if (used_names.count(new_name) == 0) {
-	used_names.insert(new_name);
-	name_map[id] = new_name;
-	return new_name;
-      }
-    }
-  }
-
-  std::string operator[](IdString id)
-  {
-    if (name_map.count(id)) {
-      return name_map[id];
-    } else {
-      return insert(id);
-    }
-  }
+const char *reserved_keywords[] = {
+	"BINARY", "DECIMAL", "HEXADECIMAL", "NUMERAL", "STRING", "_", "!", "as", "let", "exists", "forall", "match", "par",
+	"assert", "check-sat", "check-sat-assuming", "declare-const", "declare-datatype", "declare-datatypes",
+	"declare-fun", "declare-sort", "define-fun", "define-fun-rec", "define-funs-rec", "define-sort",
+	"exit", "get-assertions", "symbol", "sort", "get-assignment", "get-info", "get-model",
+	"get-option", "get-proof", "get-unsat-assumptions", "get-unsat-core", "get-value",
+	"pop", "push", "reset", "reset-assertions", "set-info", "set-logic", "set-option",
+
+	"pair", "Pair", "first", "second",
+	"inputs", "state",
+	nullptr
 };
 
-struct SmtWriter {
-  std::ostream &stream;
-
-  SmtWriter(std::ostream &out) : stream(out) {}
-
-  void print(const char *fmt, ...)
-  {
-    va_list args;
-    va_start(args, fmt);
-    stream << vstringf(fmt, args);
-    va_end(args);
-  }
+struct SmtScope : public FunctionalTools::Scope<int> {
+	SmtScope() {
+		for(const char **p = reserved_keywords; *p != nullptr; p++)
+			reserve(*p);
+	}
+	bool is_character_legal(char c) override {
+		return isascii(c) && (isalnum(c) || strchr("~!@$%^&*_-+=<>.?/", c));
+	}
 };
 
-template <class NodeNames> struct SmtPrintVisitor {
-  using Node = FunctionalIR::Node;
-  NodeNames np;
-  SmtScope &scope;
-
-  SmtPrintVisitor(NodeNames np, SmtScope &scope) : np(np), scope(scope) {}
-
-  template <class T> std::string arg_to_string(T n) { return std::to_string(n); }
-
-  std::string arg_to_string(std::string n) { return n; }
-
-  std::string arg_to_string(Node n) { return np(n); }
-
-  template <typename... Args> std::string format(std::string fmt, Args &&...args)
-  {
-    std::vector<std::string> arg_strings = {arg_to_string(std::forward<Args>(args))...};
-    for (size_t i = 0; i < arg_strings.size(); ++i) {
-      std::string placeholder = "%" + std::to_string(i);
-      size_t pos = 0;
-      while ((pos = fmt.find(placeholder, pos)) != std::string::npos) {
-	fmt.replace(pos, placeholder.length(), arg_strings[i]);
-	pos += arg_strings[i].length();
-      }
-    }
-    return fmt;
-  }
-  std::string buf(Node, Node n) { return np(n); }
-
-  std::string slice(Node, Node a, int, int offset, int out_width)
-  {
-    return format("((_ extract %2 %1) %0)", np(a), offset, offset + out_width - 1);
-  }
-
-  std::string zero_extend(Node, Node a, int, int out_width) { return format("((_ zero_extend %1) %0)", np(a), out_width - a.width()); }
-
-  std::string sign_extend(Node, Node a, int, int out_width) { return format("((_ sign_extend %1) %0)", np(a), out_width - a.width()); }
-
-  std::string concat(Node, Node a, int, Node b, int) { return format("(concat %0 %1)", np(a), np(b)); }
-
-  std::string add(Node, Node a, Node b, int) { return format("(bvadd %0 %1)", np(a), np(b)); }
-
-  std::string sub(Node, Node a, Node b, int) { return format("(bvsub %0 %1)", np(a), np(b)); }
-
-  std::string mul(Node, Node a, Node b, int) { return format("(bvmul %0 %1)", np(a), np(b)); }
-
-  std::string unsigned_div(Node, Node a, Node b, int) { return format("(bvudiv %0 %1)", np(a), np(b)); }
-
-  std::string unsigned_mod(Node, Node a, Node b, int) { return format("(bvurem %0 %1)", np(a), np(b)); }
-
-  std::string bitwise_and(Node, Node a, Node b, int) { return format("(bvand %0 %1)", np(a), np(b)); }
-
-  std::string bitwise_or(Node, Node a, Node b, int) { return format("(bvor %0 %1)", np(a), np(b)); }
-
-  std::string bitwise_xor(Node, Node a, Node b, int) { return format("(bvxor %0 %1)", np(a), np(b)); }
-
-  std::string bitwise_not(Node, Node a, int) { return format("(bvnot %0)", np(a)); }
-
-  std::string unary_minus(Node, Node a, int) { return format("(bvneg %0)", np(a)); }
-
-  std::string reduce_and(Node, Node a, int) {
-    std::stringstream ss;
-    // We use ite to set the result to bit vector, to ensure appropriate type
-    ss << "(ite (= " << np(a) << " #b" << std::string(a.width(), '1') << ") #b1 #b0)";
-    return ss.str();
-  }
- 
-  std::string reduce_or(Node, Node a, int)
-  {
-    std::stringstream ss;
-    // We use ite to set the result to bit vector, to ensure appropriate type
-    ss << "(ite (= " << np(a) << " #b" << std::string(a.width(), '0') << ") #b0 #b1)";
-    return ss.str();
-  }
-
-  std::string reduce_xor(Node, Node a, int) {
-    std::stringstream ss;
-    ss << "(bvxor ";
-    for (int i = 0; i < a.width(); ++i) {
-      if (i > 0) ss << " ";
-      ss << "((_ extract " << i << " " << i << ") " << np(a) << ")";
-    }
-    ss << ")";
-    return ss.str();
-  }
- 
-  std::string equal(Node, Node a, Node b, int) {
-    return format("(ite (= %0 %1) #b1 #b0)", np(a), np(b));
-  }
-
-  std::string not_equal(Node, Node a, Node b, int) {
-    return format("(ite (distinct %0 %1) #b1 #b0)", np(a), np(b));
-  }
-
-  std::string signed_greater_than(Node, Node a, Node b, int) { 
-    return format("(ite (bvsgt %0 %1) #b1 #b0)", np(a), np(b)); 
-  }
-
-  std::string signed_greater_equal(Node, Node a, Node b, int) {
-    return format("(ite (bvsge %0 %1) #b1 #b0)", np(a), np(b));
-  }
-
-  std::string unsigned_greater_than(Node, Node a, Node b, int) { 
-    return format("(ite (bvugt %0 %1) #b1 #b0)", np(a), np(b)); 
-  }
-
-  std::string unsigned_greater_equal(Node, Node a, Node b, int) { 
-    return format("(ite (bvuge %0 %1) #b1 #b0)", np(a), np(b)); 
-  }
-
-  std::string logical_shift_left(Node, Node a, Node b, int, int) {
-    // Get the bit-widths of a and b
-    int bit_width_a = a.width();
-    int bit_width_b = b.width();
-
-    // Extend b to match the bit-width of a if necessary
-    std::ostringstream oss;
-    if (bit_width_a > bit_width_b) {
-      oss << "((_ zero_extend " << (bit_width_a - bit_width_b) << ") " << np(b) << ")";
-    } else {
-      oss << np(b);  // No extension needed if b's width is already sufficient
-    }
-    std::string b_extended = oss.str();
-
-    // Format the bvshl operation with the extended b
-    oss.str(""); // Clear the stringstream
-    oss << "(bvshl " << np(a) << " " << b_extended << ")";
-    return oss.str();
-  }
-
-  std::string logical_shift_right(Node, Node a, Node b, int, int) {
-    // Get the bit-widths of a and b
-    int bit_width_a = a.width();
-    int bit_width_b = b.width();
+class SExpr {
+	std::variant<std::vector<SExpr>, std::string> _v;
+public:
+	SExpr(std::string a) : _v(std::move(a)) {}
+    SExpr(const char *a) : _v(a) {}
+	SExpr(int n) : _v(std::to_string(n)) {}
+    SExpr(std::vector<SExpr> const &a) : _v(std::in_place_index<0>, a) {}
+    SExpr(std::vector<SExpr> &&a) : _v(std::in_place_index<0>, std::move(a)) {}
+    SExpr(std::initializer_list<SExpr> a) : _v(std::in_place_index<0>, a) {}
+    bool is_atom() const { return std::holds_alternative<std::string>(_v); }
+    std::string const &atom() const { return std::get<std::string>(_v); }
+    bool is_list() const { return std::holds_alternative<std::vector<SExpr>>(_v); }
+    std::vector<SExpr> const &list() const { return std::get<std::vector<SExpr>>(_v); }
+	friend std::ostream &operator<<(std::ostream &os, SExpr const &sexpr) {
+		if(sexpr.is_atom())
+			os << sexpr.atom();
+		else if(sexpr.is_list()){
+			os << "(";
+			auto l = sexpr.list();
+			for(size_t i = 0; i < l.size(); i++) {
+				if(i > 0) os << " ";
+				os << l[i];
+			}
+			os << ")";
+		}else
+			os << "<invalid>";
+		return os;
+	}
+	std::string to_string() const {
+		std::stringstream ss;
+		ss << *this;
+		return ss.str();
+	}
+};
 
-    // Extend b to match the bit-width of a if necessary
-    std::ostringstream oss;
-    if (bit_width_a > bit_width_b) {
-      oss << "((_ zero_extend " << (bit_width_a - bit_width_b) << ") " << np(b) << ")";
-    } else {
-      oss << np(b);  // No extension needed if b's width is already sufficient
+class SExprWriter {
+    std::ostream &os;
+    int _max_line_width;
+    int _indent = 0;
+    int _pos = 0;
+    bool _pending_nl = false;
+	vector<bool> _unclosed;
+	vector<size_t> _unclosed_stack;
+	void nl_if_pending() {
+		if(_pending_nl) {
+            os << '\n';
+            _pos = 0;
+            _pending_nl = false;
+		}
+	}
+    void puts(std::string const &s) {
+        if(s.empty()) return;
+		nl_if_pending();
+        for(auto c : s) {
+            if(c == '\n') {
+                os << c;
+                _pos = 0;
+            } else {
+                if(_pos == 0) {
+                    for(int i = 0; i < _indent; i++)
+                        os << "  ";
+                    _pos = 2 * _indent;
+                }
+                os << c;
+                _pos++;
+            }
+        }
     }
-    std::string b_extended = oss.str();
-
-    // Format the bvlshr operation with the extended b
-    oss.str(""); // Clear the stringstream
-    oss << "(bvlshr " << np(a) << " " << b_extended << ")";
-    return oss.str();
-  }
-
-  std::string arithmetic_shift_right(Node, Node a, Node b, int, int) {
-    // Get the bit-widths of a and b
-    int bit_width_a = a.width();
-    int bit_width_b = b.width();
-
-    // Extend b to match the bit-width of a if necessary
-    std::ostringstream oss;
-    if (bit_width_a > bit_width_b) {
-      oss << "((_ zero_extend " << (bit_width_a - bit_width_b) << ") " << np(b) << ")";
-    } else {
-      oss << np(b);  // No extension needed if b's width is already sufficient
+    int width(SExpr const &sexpr) {
+        if(sexpr.is_atom())
+            return sexpr.atom().size();
+        else if(sexpr.is_list()) {
+            int w = 2;
+            for(auto arg : sexpr.list())
+                w += width(arg);
+            if(sexpr.list().size() > 1)
+                w += sexpr.list().size() - 1;
+            return w;
+        } else
+            return 0;
     }
-    std::string b_extended = oss.str();
-
-    // Format the bvashr operation with the extended b
-    oss.str(""); // Clear the stringstream
-    oss << "(bvashr " << np(a) << " " << b_extended << ")";
-    return oss.str();
-  }
- 
-  std::string mux(Node, Node a, Node b, Node s, int) {
-    return format("(ite (= %2 #b1) %0 %1)", np(a), np(b), np(s));
-  }
-
-  std::string pmux(Node, Node a, Node b, Node s, int, int)
-  {
-    // Assume s is a bit vector, combine a and b based on the selection bits
-    return format("(pmux %0 %1 %2)", np(a), np(b), np(s));
-  }
-
-  std::string constant(Node, RTLIL::Const value) { return format("#b%0", value.as_string()); }
-
-  std::string input(Node, IdString name) { return format("%0", scope[name]); }
-
-  std::string state(Node, IdString name) { return format("(%0 current_state)", scope[name]); }
-
-  std::string memory_read(Node, Node mem, Node addr, int, int) { return format("(select %0 %1)", np(mem), np(addr)); }
-
-  std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { return format("(store %0 %1 %2)", np(mem), np(addr), np(data)); }
-
-  std::string undriven(Node, int width) { return format("#b%0", std::string(width, '0')); }
-};
-
-struct SmtModule {
-  std::string name;
-  SmtScope scope;
-  FunctionalIR ir;
-
-  SmtModule(const std::string &module_name, FunctionalIR ir) : name(module_name), ir(std::move(ir)) {}
-
-  void write(std::ostream &out)
-  {    
-    const bool stateful = ir.state().size() != 0;
-    SmtWriter writer(out);
-
-    writer.print("(declare-fun %s () Bool)\n\n", name.c_str());
-
-    writer.print("(declare-datatypes ()  ((Inputs    (mk_inputs");
-    for (const auto &input : ir.inputs()) {
-      std::string input_name = scope[input.first];
-      writer.print(" (%s (_ BitVec %d))", input_name.c_str(), input.second.width());
+    void print(SExpr const &sexpr, bool close = true, bool indent_rest = true) {
+        if(sexpr.is_atom())
+            puts(sexpr.atom());
+        else if(sexpr.is_list()) {
+            auto args = sexpr.list();
+			puts("(");
+			bool vertical = args.size() > 1 && _pos + width(sexpr) > _max_line_width;
+			if(vertical) _indent++;
+			for(size_t i = 0; i < args.size(); i++) {
+				if(i > 0) puts(vertical ? "\n" : " ");
+				print(args[i]);
+			}
+			_indent += (!close && indent_rest) - vertical;
+			if(close)
+				puts(")");
+			else {
+				_unclosed.push_back(indent_rest);
+				_pending_nl = true;
+			}
+        }else
+            log_error("shouldn't happen in SExprWriter::print");
     }
-    writer.print("))))\n\n");
-
-    writer.print("(declare-datatypes () ((Outputs    (mk_outputs");
-    for (const auto &output : ir.outputs()) {
-      std::string output_name = scope[output.first];
-      writer.print(" (%s (_ BitVec %d))", output_name.c_str(), output.second.width());
+public:
+    SExprWriter(std::ostream &os, int max_line_width = 80)
+        : os(os)
+        , _max_line_width(max_line_width)
+    {}
+    void open(SExpr const &sexpr, bool indent_rest = true) {
+        log_assert(sexpr.is_list());
+        print(sexpr, false, indent_rest);
     }
-    writer.print("))))\n");
-
-    if (stateful) {
-      writer.print("(declare-datatypes ()  ((State   (mk_state");
-      for (const auto &state : ir.state()) {
-	std::string state_name = scope[state.first];
-	writer.print(" (%s (_ BitVec %d))", state_name.c_str(), state.second.width());
-      }
-      writer.print("))))\n");
-
-      writer.print("(declare-datatypes ()  ((Pair   (mk-pair (outputs Outputs) (next_state State)))))\n");
+    void close(size_t n = 1) {
+		log_assert(_unclosed.size() - (_unclosed_stack.empty() ? 0 : _unclosed_stack.back()) >= n);
+		while(n-- > 0) {
+			bool indented = _unclosed[_unclosed.size() - 1];
+			_unclosed.pop_back();
+			_pending_nl = _pos >= _max_line_width;
+			if(indented)
+				_indent--;
+			puts(")");
+			_pending_nl = true;
+		}
     }
-
-    if (stateful)
-      writer.print("(define-fun %s_step ((current_state State) (inputs Inputs)) Pair", name.c_str());
-    else
-      writer.print("(define-fun %s_step ((inputs Inputs)) Outputs", name.c_str());
-
-    writer.print(" (let (");
-    for (const auto &input : ir.inputs()) {
-      std::string input_name = scope[input.first];
-      writer.print(" (%s (%s inputs))", input_name.c_str(), input_name.c_str());
+	void push() {
+		_unclosed_stack.push_back(_unclosed.size());
+	}
+	void pop() {
+		auto t = _unclosed_stack.back();
+		log_assert(_unclosed.size() >= t);
+		close(_unclosed.size() - t);
+		_unclosed_stack.pop_back();
+	}
+    SExprWriter &operator <<(SExpr const &sexpr) {
+        print(sexpr);
+        _pending_nl = true;
+        return *this;
     }
-    writer.print(" )");
-
-    auto node_to_string = [&](FunctionalIR::Node n) { return scope[n.name()]; };
-    SmtPrintVisitor<decltype(node_to_string)> visitor(node_to_string, scope);
-
-    for (auto it = ir.begin(); it != ir.end(); ++it) {
-      const FunctionalIR::Node &node = *it;
-
-      if (ir.inputs().count(node.name()) > 0)
-	continue;
-
-      std::string node_name = scope[node.name()];
-      std::string node_expr = node.visit(visitor);
-
-      writer.print(" (let ( (%s %s))", node_name.c_str(), node_expr.c_str());
+	void comment(std::string const &str, bool hanging = false) {
+		if(hanging) {
+			if(_pending_nl) {
+				_pending_nl = false;
+				puts(" ");
+			}
+		}
+		puts("; ");
+		puts(str);
+		puts("\n");
+	}
+    ~SExprWriter() {
+		while(!_unclosed_stack.empty())
+			pop();
+		close(_unclosed.size());
+		nl_if_pending();
     }
+};
 
-    if (stateful) {
-      writer.print(" (let ( (next_state (mk_state ");
-      for (const auto &state : ir.state()) {
-	std::string state_name = scope[state.first];
-	const std::string state_assignment = ir.get_state_next_node(state.first).name().c_str();
-	writer.print(" %s", state_assignment.substr(1).c_str());
-      }
-      writer.print(" )))");
-    }
+struct SmtSort {
+	FunctionalIR::Sort sort;
+	SmtSort(FunctionalIR::Sort sort) : sort(sort) {}
+	SExpr to_sexpr() const {
+		if(sort.is_memory()) {
+			return SExpr{"Array", {"_", "BitVec", sort.addr_width()}, {"_", "BitVec", sort.data_width()}};
+		} else if(sort.is_signal()) {
+			return SExpr{"_", "BitVec", sort.width()};
+		} else {
+			log_error("unknown sort");
+		}
+	}
+};
 
-    if (stateful) {
-      writer.print(" (let ( (outputs (mk_outputs ");
-      for (const auto &output : ir.outputs()) {
-	std::string output_name = scope[output.first];
-	writer.print(" %s", output_name.c_str());
-      }
-      writer.print(" )))");
+class SmtStruct {
+	struct Field {
+		SmtSort sort;
+		std::string accessor;
+	};
+	idict<IdString> field_names;
+	vector<Field> fields;
+	SmtScope &scope;
+public:
+	std::string name;
+	SmtStruct(std::string name, SmtScope &scope) : scope(scope), name(name) {}
+	void insert(IdString field_name, SmtSort sort) {
+		field_names(field_name);
+		auto accessor = scope.unique_name("\\" + name + "_" + RTLIL::unescape_id(field_name));
+		fields.emplace_back(Field{sort, accessor});
+	}
+	void write_definition(SExprWriter &w) {
+		w.open(SExpr{"declare-datatype", name});
+		w.open(SExpr({}));
+		w.open(SExpr{name});
+		for(const auto &field : fields)
+			w << SExpr{field.accessor, field.sort.to_sexpr()};
+		w.close(3);
+	}
+	template<typename Fn> void write_value(SExprWriter &w, Fn fn) {
+		w.open(SExpr(std::initializer_list<SExpr>{name}));
+		for(auto field_name : field_names) {
+			w << fn(field_name);
+			w.comment(RTLIL::unescape_id(field_name), true);
+		}
+		w.close();
+	}
+	SExpr access(SExpr record, IdString name) {
+		size_t i = field_names.at(name);
+		return SExpr{fields[i].accessor, std::move(record)};
+	}
+};
 
-      writer.print("(mk-pair outputs next_state)");
-    }
-    else {
-      writer.print(" (mk_outputs ");
-      for (const auto &output : ir.outputs()) {
-	std::string output_name = scope[output.first];
-	writer.print(" %s", output_name.c_str());
-      }
-      writer.print(" )"); // Closing mk_outputs 
-    }
-    if (stateful) {
-      writer.print(" )"); // Closing outputs let statement
-      writer.print(" )"); // Closing next_state let statement
-    }
-    // Close the nested lets
-    for (size_t i = 0; i < ir.size() - ir.inputs().size(); ++i) {
-      writer.print(" )"); // Closing each node
-    }
-    if (ir.size() == ir.inputs().size())
-      writer.print(" )"); // Corner case
+struct SmtPrintVisitor {
+	using Node = FunctionalIR::Node;
+	std::function<SExpr(Node)> n;
+	SmtStruct &input_struct;
+	SmtStruct &state_struct;
+
+	SmtPrintVisitor(SmtStruct &input_struct, SmtStruct &state_struct) : input_struct(input_struct), state_struct(state_struct) {}
+
+	std::string literal(RTLIL::Const c) {
+		std::string s = "#b";
+		for(int i = c.size(); i-- > 0; )
+			s += c[i] == State::S1 ? '1' : '0';
+		return s;
+	}
+
+	SExpr from_bool(SExpr &&arg) {
+		return SExpr{"ite", std::move(arg), "#b1", "#b0"};
+	}
+	SExpr to_bool(SExpr &&arg) {
+		return SExpr{"=", std::move(arg), "#b1"};
+	}
+	SExpr extract(SExpr &&arg, int offset, int out_width = 1) {
+		return SExpr{{"_", "extract", offset + out_width - 1, offset}, std::move(arg)};
+	}
+
+	SExpr buf(Node, Node a) { return n(a); }
+	SExpr slice(Node, Node a, int, int offset, int out_width) { return extract(n(a), offset, out_width); }
+	SExpr zero_extend(Node, Node a, int, int out_width) { return SExpr{{"_", "zero_extend", out_width - a.width()}, n(a)}; }
+	SExpr sign_extend(Node, Node a, int, int out_width) { return SExpr{{"_", "sign_extend", out_width - a.width()}, n(a)}; }
+	SExpr concat(Node, Node a, int, Node b, int) { return SExpr{"concat", n(a), n(b)}; }
+	SExpr add(Node, Node a, Node b, int) { return SExpr{"bvadd", n(a), n(b)}; }
+	SExpr sub(Node, Node a, Node b, int) { return SExpr{"bvsub", n(a), n(b)}; }
+	SExpr mul(Node, Node a, Node b, int) { return SExpr{"bvmul", n(a), n(b)}; }
+	SExpr unsigned_div(Node, Node a, Node b, int) { return SExpr{"bvudiv", n(a), n(b)}; }
+	SExpr unsigned_mod(Node, Node a, Node b, int) { return SExpr{"bvurem", n(a), n(b)}; }
+	SExpr bitwise_and(Node, Node a, Node b, int) { return SExpr{"bvand", n(a), n(b)}; }
+	SExpr bitwise_or(Node, Node a, Node b, int) { return SExpr{"bvor", n(a), n(b)}; }
+	SExpr bitwise_xor(Node, Node a, Node b, int) { return SExpr{"bvxor", n(a), n(b)}; }
+	SExpr bitwise_not(Node, Node a, int) { return SExpr{"bvnot", n(a)}; }
+	SExpr unary_minus(Node, Node a, int) { return SExpr{"bvneg", n(a)}; }
+	SExpr reduce_and(Node, Node a, int) { return from_bool(SExpr{"=", n(a), literal(RTLIL::Const(State::S1, a.width()))}); }
+	SExpr reduce_or(Node, Node a, int) { return from_bool(SExpr{"=", n(a), literal(RTLIL::Const(State::S0, a.width()))}); }
+	SExpr reduce_xor(Node, Node a, int) {
+		vector<SExpr> s { "bvxor" };
+		for(int i = 0; i < a.width(); i++)
+			s.push_back(extract(n(a), i));
+		return s;
+	}
+	SExpr equal(Node, Node a, Node b, int) { return from_bool(SExpr{"=", n(a), n(b)}); }
+	SExpr not_equal(Node, Node a, Node b, int) { return from_bool(SExpr{"distinct", n(a), n(b)}); }
+	SExpr signed_greater_than(Node, Node a, Node b, int) { return from_bool(SExpr{"bvsgt", n(a), n(b)}); }
+	SExpr signed_greater_equal(Node, Node a, Node b, int) { return from_bool(SExpr{"bvsge", n(a), n(b)}); }
+	SExpr unsigned_greater_than(Node, Node a, Node b, int) { return from_bool(SExpr{"bvugt", n(a), n(b)}); }
+	SExpr unsigned_greater_equal(Node, Node a, Node b, int) { return from_bool(SExpr{"bvuge", n(a), n(b)}); }
+
+	SExpr extend(SExpr &&a, int in_width, int out_width) {
+		if(in_width < out_width)
+			return SExpr{{"_", "zero_extend", out_width - in_width}, std::move(a)};
+		else
+			return std::move(a);
+	}
+	SExpr logical_shift_left(Node, Node a, Node b, int, int) { return SExpr{"bvshl", n(a), extend(n(b), b.width(), a.width())}; }
+	SExpr logical_shift_right(Node, Node a, Node b, int, int) { return SExpr{"bvshr", n(a), extend(n(b), b.width(), a.width())}; }
+	SExpr arithmetic_shift_right(Node, Node a, Node b, int, int) { return SExpr{"bvasr", n(a), extend(n(b), b.width(), a.width())}; }
+	SExpr mux(Node, Node a, Node b, Node s, int) { return SExpr{"ite", to_bool(n(s)), n(a), n(b)}; }
+	SExpr pmux(Node, Node a, Node b, Node s, int, int) {
+		SExpr rv = n(a);
+		for(int i = 0; i < s.width(); i++)
+			rv = SExpr{"ite", to_bool(extract(n(s), i)), extract(n(b), a.width() * i, a.width()), rv};
+		return rv;
+	}
+	SExpr constant(Node, RTLIL::Const value) { return literal(value); }
+	SExpr memory_read(Node, Node mem, Node addr, int, int) { return SExpr{"select", n(mem), n(addr)}; }
+	SExpr memory_write(Node, Node mem, Node addr, Node data, int, int) { return SExpr{"store", n(mem), n(addr), n(data)}; }
+
+	SExpr input(Node, IdString name) { return input_struct.access("inputs", name); }
+	SExpr state(Node, IdString name) { return state_struct.access("state", name); }
+
+	SExpr undriven(Node, int width) { return literal(RTLIL::Const(State::S0, width)); }
+};
 
-    writer.print(" )"); // Closing inputs let statement
-    writer.print(")\n"); // Closing step function
-  }
+struct SmtModule {
+	FunctionalIR ir;
+	SmtScope scope;
+	std::string name;
+	
+	SmtStruct input_struct;
+	SmtStruct output_struct;
+	SmtStruct state_struct;
+
+	SmtModule(Module *module)
+		: ir(FunctionalIR::from_module(module))
+		, scope()
+		, name(scope.unique_name(module->name))
+		, input_struct(scope.unique_name(module->name.str() + "_Inputs"), scope)
+		, output_struct(scope.unique_name(module->name.str() + "_Outputs"), scope)
+		, state_struct(scope.unique_name(module->name.str() + "_State"), scope)
+	{
+		for (const auto &input : ir.inputs())
+			input_struct.insert(input.first, input.second);
+		for (const auto &output : ir.outputs())
+			output_struct.insert(output.first, output.second);
+		for (const auto &state : ir.state())
+			state_struct.insert(state.first, state.second);
+	}
+
+	void write(std::ostream &out)
+	{    
+		SExprWriter w(out);
+
+		input_struct.write_definition(w);
+		output_struct.write_definition(w);
+		state_struct.write_definition(w);
+
+		w << SExpr{"declare-datatypes", {{"Pair", 2}}, {{"par", {"X", "Y"}, {{"pair", {"first", "X"}, {"second", "Y"}}}}}};
+
+		w.push();
+		w.open(SExpr{"define-fun", name,
+			{{"inputs", input_struct.name},
+			 {"state", state_struct.name}},
+			{"Pair", output_struct.name, state_struct.name}});
+		auto inlined = [&](FunctionalIR::Node n) {
+			return n.fn() == FunctionalIR::Fn::constant ||
+				   n.fn() == FunctionalIR::Fn::undriven;
+		};
+		SmtPrintVisitor visitor(input_struct, state_struct);
+		auto node_to_sexpr = [&](FunctionalIR::Node n) -> SExpr {
+			if(inlined(n))
+				return n.visit(visitor);
+			else
+				return scope(n.id(), n.name());
+		};
+		visitor.n = node_to_sexpr;
+		for(auto n : ir)
+			if(!inlined(n)) {
+				w.open(SExpr{"let", {{node_to_sexpr(n), n.visit(visitor)}}}, false);
+				w.comment(SmtSort(n.sort()).to_sexpr().to_string(), true);
+			}
+		w.open(SExpr{"pair"});
+		output_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.get_output_node(name)); });
+		state_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.get_state_next_node(name)); });
+		w.pop();
+	}
 };
 
 struct FunctionalSmtBackend : public Backend {
-  FunctionalSmtBackend() : Backend("functional_smt2", "Generate SMT-LIB from Functional IR") {}
+	FunctionalSmtBackend() : Backend("functional_smt2", "Generate SMT-LIB from Functional IR") {}
 
-  void help() override { log("\nFunctional SMT Backend.\n\n"); }
+	void help() override { log("\nFunctional SMT Backend.\n\n"); }
 
-  void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
-  {
-    log_header(design, "Executing Functional SMT Backend.\n");
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		log_header(design, "Executing Functional SMT Backend.\n");
 
-    size_t argidx = 1;
-    extra_args(f, filename, args, argidx, design);
+		size_t argidx = 1;
+		extra_args(f, filename, args, argidx, design);
 
-    for (auto module : design->selected_modules()) {
-      log("Processing module `%s`.\n", module->name.c_str());
-      auto ir = FunctionalIR::from_module(module);
-      SmtModule smt(RTLIL::unescape_id(module->name), ir);
-      smt.write(*f);
-    }
-  }
+		for (auto module : design->selected_modules()) {
+			log("Processing module `%s`.\n", module->name.c_str());
+			SmtModule smt(module);
+			smt.write(*f);
+		}
+	}
 } FunctionalSmtBackend;
 
 PRIVATE_NAMESPACE_END
diff --git a/kernel/functionalir.h b/kernel/functionalir.h
index 3e7c55ef4ec..99fc872a81a 100644
--- a/kernel/functionalir.h
+++ b/kernel/functionalir.h
@@ -30,6 +30,7 @@ USING_YOSYS_NAMESPACE
 YOSYS_NAMESPACE_BEGIN
 
 class FunctionalIR {
+public:
 	enum class Fn {
 		invalid,
 		buf,
@@ -69,7 +70,6 @@ class FunctionalIR {
 		memory_read,
 		memory_write
 	};
-public:
 	class Sort {
 		std::variant<int, std::pair<int, int>> _v;
 	public:
@@ -185,6 +185,7 @@ class FunctionalIR {
 			else
 				return std::string("\\n") + std::to_string(id());
 		}
+		Fn fn() const { return _ref.function().fn(); }
 		Sort sort() const { return _ref.attr().sort; }
 		int width() const { return sort().width(); }
 		Node arg(int n) const { return Node(_ref.arg(n)); }
@@ -380,16 +381,22 @@ class FunctionalIR {
 };
 
 namespace FunctionalTools {
-	class Scope {
-		const char *_illegal_characters;
+	template<class Id> class Scope {
+	protected:
+		char substitution_character = '_';
+		virtual bool is_character_legal(char) = 0;
+	private:
 		pool<std::string> _used_names;
-		dict<int, std::string> _by_id;
-		dict<IdString, std::string> _by_name;
-		std::string allocate_name(IdString suggestion) {
+		dict<Id, std::string> _by_id;
+	public:
+		void reserve(std::string name) {
+			_used_names.insert(std::move(name));
+		}
+		std::string unique_name(IdString suggestion) {
 			std::string str = RTLIL::unescape_id(suggestion);
 			for(size_t i = 0; i < str.size(); i++)
-				if(strchr(_illegal_characters, str[i]))
-					str[i] = '_';
+				if(!is_character_legal(str[i]))
+					str[i] = substitution_character;
 			if(_used_names.count(str) == 0) {
 				_used_names.insert(str);
 				return str;
@@ -402,32 +409,14 @@ namespace FunctionalTools {
 				}
 			}
 		}
-	public:
-		Scope(const char *illegal_characters = "", const char **keywords = nullptr) {
-			_illegal_characters = illegal_characters;
-			if(keywords != nullptr)
-				for(const char **p = keywords; *p != nullptr; p++)
-					reserve(*p);
-		}
-		void reserve(std::string name) {
-			_used_names.insert(std::move(name));
-		}
-		std::string operator()(int id, IdString suggestion) {
+		std::string operator()(Id id, IdString suggestion) {
 			auto it = _by_id.find(id);
 			if(it != _by_id.end())
 				return it->second;
-			std::string str = allocate_name(suggestion);
+			std::string str = unique_name(suggestion);
 			_by_id.insert({id, str});
 			return str;
 		}
-		std::string operator()(IdString idstring) {
-			auto it = _by_name.find(idstring);
-			if(it != _by_name.end())
-				return it->second;
-			std::string str = allocate_name(idstring);
-			_by_name.insert({idstring, str});
-			return str;
-		}
 	};
 	class Writer {
 		std::ostream *os;

From c659ef29f4a00de5f1d7a656ffd646655fa4e859 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Wed, 10 Jul 2024 18:08:12 +0100
Subject: [PATCH 405/499] change smtlib backend to use list() function instead
 of SExpr{} constructor (leads to weird constructor overloading resolution
 issues)

---
 backends/functional/smtlib.cc | 105 ++++++++++++++++++----------------
 1 file changed, 55 insertions(+), 50 deletions(-)

diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index c3e159eb31e..cbff1398e8a 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -48,14 +48,14 @@ struct SmtScope : public FunctionalTools::Scope<int> {
 };
 
 class SExpr {
+public:
 	std::variant<std::vector<SExpr>, std::string> _v;
 public:
 	SExpr(std::string a) : _v(std::move(a)) {}
     SExpr(const char *a) : _v(a) {}
 	SExpr(int n) : _v(std::to_string(n)) {}
-    SExpr(std::vector<SExpr> const &a) : _v(std::in_place_index<0>, a) {}
-    SExpr(std::vector<SExpr> &&a) : _v(std::in_place_index<0>, std::move(a)) {}
-    SExpr(std::initializer_list<SExpr> a) : _v(std::in_place_index<0>, a) {}
+	SExpr(std::vector<SExpr> const &l) : _v(l) {}
+	SExpr(std::vector<SExpr> &&l) : _v(std::move(l)) {}
     bool is_atom() const { return std::holds_alternative<std::string>(_v); }
     std::string const &atom() const { return std::get<std::string>(_v); }
     bool is_list() const { return std::holds_alternative<std::vector<SExpr>>(_v); }
@@ -81,6 +81,9 @@ class SExpr {
 		return ss.str();
 	}
 };
+template<typename... Args> SExpr list(Args&&... args) {
+	return SExpr(std::vector<SExpr>{std::forward<Args>(args)...});
+}
 
 class SExprWriter {
     std::ostream &os;
@@ -209,9 +212,9 @@ struct SmtSort {
 	SmtSort(FunctionalIR::Sort sort) : sort(sort) {}
 	SExpr to_sexpr() const {
 		if(sort.is_memory()) {
-			return SExpr{"Array", {"_", "BitVec", sort.addr_width()}, {"_", "BitVec", sort.data_width()}};
+			return list("Array", list("_", "BitVec", sort.addr_width()), list("_", "BitVec", sort.data_width()));
 		} else if(sort.is_signal()) {
-			return SExpr{"_", "BitVec", sort.width()};
+			return list("_", "BitVec", sort.width());
 		} else {
 			log_error("unknown sort");
 		}
@@ -235,15 +238,15 @@ class SmtStruct {
 		fields.emplace_back(Field{sort, accessor});
 	}
 	void write_definition(SExprWriter &w) {
-		w.open(SExpr{"declare-datatype", name});
-		w.open(SExpr({}));
-		w.open(SExpr{name});
+		w.open(list("declare-datatype", name));
+		w.open(list());
+		w.open(list(name));
 		for(const auto &field : fields)
-			w << SExpr{field.accessor, field.sort.to_sexpr()};
+			w << list(field.accessor, field.sort.to_sexpr());
 		w.close(3);
 	}
 	template<typename Fn> void write_value(SExprWriter &w, Fn fn) {
-		w.open(SExpr(std::initializer_list<SExpr>{name}));
+		w.open(list(name));
 		for(auto field_name : field_names) {
 			w << fn(field_name);
 			w.comment(RTLIL::unescape_id(field_name), true);
@@ -252,7 +255,7 @@ class SmtStruct {
 	}
 	SExpr access(SExpr record, IdString name) {
 		size_t i = field_names.at(name);
-		return SExpr{fields[i].accessor, std::move(record)};
+		return list(fields[i].accessor, std::move(record));
 	}
 };
 
@@ -272,64 +275,64 @@ struct SmtPrintVisitor {
 	}
 
 	SExpr from_bool(SExpr &&arg) {
-		return SExpr{"ite", std::move(arg), "#b1", "#b0"};
+		return list("ite", std::move(arg), "#b1", "#b0");
 	}
 	SExpr to_bool(SExpr &&arg) {
-		return SExpr{"=", std::move(arg), "#b1"};
+		return list("=", std::move(arg), "#b1");
 	}
 	SExpr extract(SExpr &&arg, int offset, int out_width = 1) {
-		return SExpr{{"_", "extract", offset + out_width - 1, offset}, std::move(arg)};
+		return list(list("_", "extract", offset + out_width - 1, offset), std::move(arg));
 	}
 
 	SExpr buf(Node, Node a) { return n(a); }
 	SExpr slice(Node, Node a, int, int offset, int out_width) { return extract(n(a), offset, out_width); }
-	SExpr zero_extend(Node, Node a, int, int out_width) { return SExpr{{"_", "zero_extend", out_width - a.width()}, n(a)}; }
-	SExpr sign_extend(Node, Node a, int, int out_width) { return SExpr{{"_", "sign_extend", out_width - a.width()}, n(a)}; }
-	SExpr concat(Node, Node a, int, Node b, int) { return SExpr{"concat", n(a), n(b)}; }
-	SExpr add(Node, Node a, Node b, int) { return SExpr{"bvadd", n(a), n(b)}; }
-	SExpr sub(Node, Node a, Node b, int) { return SExpr{"bvsub", n(a), n(b)}; }
-	SExpr mul(Node, Node a, Node b, int) { return SExpr{"bvmul", n(a), n(b)}; }
-	SExpr unsigned_div(Node, Node a, Node b, int) { return SExpr{"bvudiv", n(a), n(b)}; }
-	SExpr unsigned_mod(Node, Node a, Node b, int) { return SExpr{"bvurem", n(a), n(b)}; }
-	SExpr bitwise_and(Node, Node a, Node b, int) { return SExpr{"bvand", n(a), n(b)}; }
-	SExpr bitwise_or(Node, Node a, Node b, int) { return SExpr{"bvor", n(a), n(b)}; }
-	SExpr bitwise_xor(Node, Node a, Node b, int) { return SExpr{"bvxor", n(a), n(b)}; }
-	SExpr bitwise_not(Node, Node a, int) { return SExpr{"bvnot", n(a)}; }
-	SExpr unary_minus(Node, Node a, int) { return SExpr{"bvneg", n(a)}; }
-	SExpr reduce_and(Node, Node a, int) { return from_bool(SExpr{"=", n(a), literal(RTLIL::Const(State::S1, a.width()))}); }
-	SExpr reduce_or(Node, Node a, int) { return from_bool(SExpr{"=", n(a), literal(RTLIL::Const(State::S0, a.width()))}); }
+	SExpr zero_extend(Node, Node a, int, int out_width) { return list(list("_", "zero_extend", out_width - a.width()), n(a)); }
+	SExpr sign_extend(Node, Node a, int, int out_width) { return list(list("_", "sign_extend", out_width - a.width()), n(a)); }
+	SExpr concat(Node, Node a, int, Node b, int) { return list("concat", n(a), n(b)); }
+	SExpr add(Node, Node a, Node b, int) { return list("bvadd", n(a), n(b)); }
+	SExpr sub(Node, Node a, Node b, int) { return list("bvsub", n(a), n(b)); }
+	SExpr mul(Node, Node a, Node b, int) { return list("bvmul", n(a), n(b)); }
+	SExpr unsigned_div(Node, Node a, Node b, int) { return list("bvudiv", n(a), n(b)); }
+	SExpr unsigned_mod(Node, Node a, Node b, int) { return list("bvurem", n(a), n(b)); }
+	SExpr bitwise_and(Node, Node a, Node b, int) { return list("bvand", n(a), n(b)); }
+	SExpr bitwise_or(Node, Node a, Node b, int) { return list("bvor", n(a), n(b)); }
+	SExpr bitwise_xor(Node, Node a, Node b, int) { return list("bvxor", n(a), n(b)); }
+	SExpr bitwise_not(Node, Node a, int) { return list("bvnot", n(a)); }
+	SExpr unary_minus(Node, Node a, int) { return list("bvneg", n(a)); }
+	SExpr reduce_and(Node, Node a, int) { return from_bool(list("=", n(a), literal(RTLIL::Const(State::S1, a.width())))); }
+	SExpr reduce_or(Node, Node a, int) { return from_bool(list("=", n(a), literal(RTLIL::Const(State::S0, a.width())))); }
 	SExpr reduce_xor(Node, Node a, int) {
 		vector<SExpr> s { "bvxor" };
 		for(int i = 0; i < a.width(); i++)
 			s.push_back(extract(n(a), i));
 		return s;
 	}
-	SExpr equal(Node, Node a, Node b, int) { return from_bool(SExpr{"=", n(a), n(b)}); }
-	SExpr not_equal(Node, Node a, Node b, int) { return from_bool(SExpr{"distinct", n(a), n(b)}); }
-	SExpr signed_greater_than(Node, Node a, Node b, int) { return from_bool(SExpr{"bvsgt", n(a), n(b)}); }
-	SExpr signed_greater_equal(Node, Node a, Node b, int) { return from_bool(SExpr{"bvsge", n(a), n(b)}); }
-	SExpr unsigned_greater_than(Node, Node a, Node b, int) { return from_bool(SExpr{"bvugt", n(a), n(b)}); }
-	SExpr unsigned_greater_equal(Node, Node a, Node b, int) { return from_bool(SExpr{"bvuge", n(a), n(b)}); }
+	SExpr equal(Node, Node a, Node b, int) { return from_bool(list("=", n(a), n(b))); }
+	SExpr not_equal(Node, Node a, Node b, int) { return from_bool(list("distinct", n(a), n(b))); }
+	SExpr signed_greater_than(Node, Node a, Node b, int) { return from_bool(list("bvsgt", n(a), n(b))); }
+	SExpr signed_greater_equal(Node, Node a, Node b, int) { return from_bool(list("bvsge", n(a), n(b))); }
+	SExpr unsigned_greater_than(Node, Node a, Node b, int) { return from_bool(list("bvugt", n(a), n(b))); }
+	SExpr unsigned_greater_equal(Node, Node a, Node b, int) { return from_bool(list("bvuge", n(a), n(b))); }
 
 	SExpr extend(SExpr &&a, int in_width, int out_width) {
 		if(in_width < out_width)
-			return SExpr{{"_", "zero_extend", out_width - in_width}, std::move(a)};
+			return list(list("_", "zero_extend", out_width - in_width), std::move(a));
 		else
 			return std::move(a);
 	}
-	SExpr logical_shift_left(Node, Node a, Node b, int, int) { return SExpr{"bvshl", n(a), extend(n(b), b.width(), a.width())}; }
-	SExpr logical_shift_right(Node, Node a, Node b, int, int) { return SExpr{"bvshr", n(a), extend(n(b), b.width(), a.width())}; }
-	SExpr arithmetic_shift_right(Node, Node a, Node b, int, int) { return SExpr{"bvasr", n(a), extend(n(b), b.width(), a.width())}; }
-	SExpr mux(Node, Node a, Node b, Node s, int) { return SExpr{"ite", to_bool(n(s)), n(a), n(b)}; }
+	SExpr logical_shift_left(Node, Node a, Node b, int, int) { return list("bvshl", n(a), extend(n(b), b.width(), a.width())); }
+	SExpr logical_shift_right(Node, Node a, Node b, int, int) { return list("bvshr", n(a), extend(n(b), b.width(), a.width())); }
+	SExpr arithmetic_shift_right(Node, Node a, Node b, int, int) { return list("bvasr", n(a), extend(n(b), b.width(), a.width())); }
+	SExpr mux(Node, Node a, Node b, Node s, int) { return list("ite", to_bool(n(s)), n(a), n(b)); }
 	SExpr pmux(Node, Node a, Node b, Node s, int, int) {
 		SExpr rv = n(a);
 		for(int i = 0; i < s.width(); i++)
-			rv = SExpr{"ite", to_bool(extract(n(s), i)), extract(n(b), a.width() * i, a.width()), rv};
+			rv = list("ite", to_bool(extract(n(s), i)), extract(n(b), a.width() * i, a.width()), rv);
 		return rv;
 	}
 	SExpr constant(Node, RTLIL::Const value) { return literal(value); }
-	SExpr memory_read(Node, Node mem, Node addr, int, int) { return SExpr{"select", n(mem), n(addr)}; }
-	SExpr memory_write(Node, Node mem, Node addr, Node data, int, int) { return SExpr{"store", n(mem), n(addr), n(data)}; }
+	SExpr memory_read(Node, Node mem, Node addr, int, int) { return list("select", n(mem), n(addr)); }
+	SExpr memory_write(Node, Node mem, Node addr, Node data, int, int) { return list("store", n(mem), n(addr), n(data)); }
 
 	SExpr input(Node, IdString name) { return input_struct.access("inputs", name); }
 	SExpr state(Node, IdString name) { return state_struct.access("state", name); }
@@ -370,13 +373,15 @@ struct SmtModule {
 		output_struct.write_definition(w);
 		state_struct.write_definition(w);
 
-		w << SExpr{"declare-datatypes", {{"Pair", 2}}, {{"par", {"X", "Y"}, {{"pair", {"first", "X"}, {"second", "Y"}}}}}};
+		w << list("declare-datatypes",
+			list(list("Pair", 2)),
+			list(list("par", list("X", "Y"), list(list("pair", list("first", "X"), list("second", "Y"))))));
 
 		w.push();
-		w.open(SExpr{"define-fun", name,
-			{{"inputs", input_struct.name},
-			 {"state", state_struct.name}},
-			{"Pair", output_struct.name, state_struct.name}});
+		w.open(list("define-fun", name,
+			list(list("inputs", input_struct.name),
+			     list("state", state_struct.name)),
+			list("Pair", output_struct.name, state_struct.name)));
 		auto inlined = [&](FunctionalIR::Node n) {
 			return n.fn() == FunctionalIR::Fn::constant ||
 				   n.fn() == FunctionalIR::Fn::undriven;
@@ -391,10 +396,10 @@ struct SmtModule {
 		visitor.n = node_to_sexpr;
 		for(auto n : ir)
 			if(!inlined(n)) {
-				w.open(SExpr{"let", {{node_to_sexpr(n), n.visit(visitor)}}}, false);
+				w.open(list("let", list(list(node_to_sexpr(n), n.visit(visitor)))), false);
 				w.comment(SmtSort(n.sort()).to_sexpr().to_string(), true);
 			}
-		w.open(SExpr{"pair"});
+		w.open(list("pair"));
 		output_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.get_output_node(name)); });
 		state_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.get_state_next_node(name)); });
 		w.pop();

From 00a65754bbf5ac5a456f6fce5812e4400ef5449c Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 11 Jul 2024 11:30:23 +0100
Subject: [PATCH 406/499] factor out SExpr/SExprWriter classes out of smtlib
 backend, and also tidy them up/document them

---
 Makefile                      |   3 +-
 backends/functional/smtlib.cc | 163 +---------------------------------
 kernel/sexpr.cc               | 163 ++++++++++++++++++++++++++++++++++
 kernel/sexpr.h                | 122 +++++++++++++++++++++++++
 4 files changed, 290 insertions(+), 161 deletions(-)
 create mode 100644 kernel/sexpr.cc
 create mode 100644 kernel/sexpr.h

diff --git a/Makefile b/Makefile
index 2bbb0dc5b48..68e6fda4a0c 100644
--- a/Makefile
+++ b/Makefile
@@ -617,6 +617,7 @@ $(eval $(call add_include_file,kernel/register.h))
 $(eval $(call add_include_file,kernel/rtlil.h))
 $(eval $(call add_include_file,kernel/satgen.h))
 $(eval $(call add_include_file,kernel/scopeinfo.h))
+$(eval $(call add_include_file,kernel/sexpr.h))
 $(eval $(call add_include_file,kernel/sigtools.h))
 $(eval $(call add_include_file,kernel/timinginfo.h))
 $(eval $(call add_include_file,kernel/utils.h))
@@ -638,7 +639,7 @@ $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h))
 
 OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o
 OBJS += kernel/binding.o
-OBJS += kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o
+OBJS += kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o kernel/sexpr.o
 OBJS += kernel/drivertools.o kernel/functionalir.o
 ifeq ($(ENABLE_ZLIB),1)
 OBJS += kernel/fstdata.o
diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index cbff1398e8a..43e6f5bf489 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -19,11 +19,14 @@
 
 #include "kernel/functionalir.h"
 #include "kernel/yosys.h"
+#include "kernel/sexpr.h"
 #include <ctype.h>
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+using SExprUtil::list;
+
 const char *reserved_keywords[] = {
 	"BINARY", "DECIMAL", "HEXADECIMAL", "NUMERAL", "STRING", "_", "!", "as", "let", "exists", "forall", "match", "par",
 	"assert", "check-sat", "check-sat-assuming", "declare-const", "declare-datatype", "declare-datatypes",
@@ -47,166 +50,6 @@ struct SmtScope : public FunctionalTools::Scope<int> {
 	}
 };
 
-class SExpr {
-public:
-	std::variant<std::vector<SExpr>, std::string> _v;
-public:
-	SExpr(std::string a) : _v(std::move(a)) {}
-    SExpr(const char *a) : _v(a) {}
-	SExpr(int n) : _v(std::to_string(n)) {}
-	SExpr(std::vector<SExpr> const &l) : _v(l) {}
-	SExpr(std::vector<SExpr> &&l) : _v(std::move(l)) {}
-    bool is_atom() const { return std::holds_alternative<std::string>(_v); }
-    std::string const &atom() const { return std::get<std::string>(_v); }
-    bool is_list() const { return std::holds_alternative<std::vector<SExpr>>(_v); }
-    std::vector<SExpr> const &list() const { return std::get<std::vector<SExpr>>(_v); }
-	friend std::ostream &operator<<(std::ostream &os, SExpr const &sexpr) {
-		if(sexpr.is_atom())
-			os << sexpr.atom();
-		else if(sexpr.is_list()){
-			os << "(";
-			auto l = sexpr.list();
-			for(size_t i = 0; i < l.size(); i++) {
-				if(i > 0) os << " ";
-				os << l[i];
-			}
-			os << ")";
-		}else
-			os << "<invalid>";
-		return os;
-	}
-	std::string to_string() const {
-		std::stringstream ss;
-		ss << *this;
-		return ss.str();
-	}
-};
-template<typename... Args> SExpr list(Args&&... args) {
-	return SExpr(std::vector<SExpr>{std::forward<Args>(args)...});
-}
-
-class SExprWriter {
-    std::ostream &os;
-    int _max_line_width;
-    int _indent = 0;
-    int _pos = 0;
-    bool _pending_nl = false;
-	vector<bool> _unclosed;
-	vector<size_t> _unclosed_stack;
-	void nl_if_pending() {
-		if(_pending_nl) {
-            os << '\n';
-            _pos = 0;
-            _pending_nl = false;
-		}
-	}
-    void puts(std::string const &s) {
-        if(s.empty()) return;
-		nl_if_pending();
-        for(auto c : s) {
-            if(c == '\n') {
-                os << c;
-                _pos = 0;
-            } else {
-                if(_pos == 0) {
-                    for(int i = 0; i < _indent; i++)
-                        os << "  ";
-                    _pos = 2 * _indent;
-                }
-                os << c;
-                _pos++;
-            }
-        }
-    }
-    int width(SExpr const &sexpr) {
-        if(sexpr.is_atom())
-            return sexpr.atom().size();
-        else if(sexpr.is_list()) {
-            int w = 2;
-            for(auto arg : sexpr.list())
-                w += width(arg);
-            if(sexpr.list().size() > 1)
-                w += sexpr.list().size() - 1;
-            return w;
-        } else
-            return 0;
-    }
-    void print(SExpr const &sexpr, bool close = true, bool indent_rest = true) {
-        if(sexpr.is_atom())
-            puts(sexpr.atom());
-        else if(sexpr.is_list()) {
-            auto args = sexpr.list();
-			puts("(");
-			bool vertical = args.size() > 1 && _pos + width(sexpr) > _max_line_width;
-			if(vertical) _indent++;
-			for(size_t i = 0; i < args.size(); i++) {
-				if(i > 0) puts(vertical ? "\n" : " ");
-				print(args[i]);
-			}
-			_indent += (!close && indent_rest) - vertical;
-			if(close)
-				puts(")");
-			else {
-				_unclosed.push_back(indent_rest);
-				_pending_nl = true;
-			}
-        }else
-            log_error("shouldn't happen in SExprWriter::print");
-    }
-public:
-    SExprWriter(std::ostream &os, int max_line_width = 80)
-        : os(os)
-        , _max_line_width(max_line_width)
-    {}
-    void open(SExpr const &sexpr, bool indent_rest = true) {
-        log_assert(sexpr.is_list());
-        print(sexpr, false, indent_rest);
-    }
-    void close(size_t n = 1) {
-		log_assert(_unclosed.size() - (_unclosed_stack.empty() ? 0 : _unclosed_stack.back()) >= n);
-		while(n-- > 0) {
-			bool indented = _unclosed[_unclosed.size() - 1];
-			_unclosed.pop_back();
-			_pending_nl = _pos >= _max_line_width;
-			if(indented)
-				_indent--;
-			puts(")");
-			_pending_nl = true;
-		}
-    }
-	void push() {
-		_unclosed_stack.push_back(_unclosed.size());
-	}
-	void pop() {
-		auto t = _unclosed_stack.back();
-		log_assert(_unclosed.size() >= t);
-		close(_unclosed.size() - t);
-		_unclosed_stack.pop_back();
-	}
-    SExprWriter &operator <<(SExpr const &sexpr) {
-        print(sexpr);
-        _pending_nl = true;
-        return *this;
-    }
-	void comment(std::string const &str, bool hanging = false) {
-		if(hanging) {
-			if(_pending_nl) {
-				_pending_nl = false;
-				puts(" ");
-			}
-		}
-		puts("; ");
-		puts(str);
-		puts("\n");
-	}
-    ~SExprWriter() {
-		while(!_unclosed_stack.empty())
-			pop();
-		close(_unclosed.size());
-		nl_if_pending();
-    }
-};
-
 struct SmtSort {
 	FunctionalIR::Sort sort;
 	SmtSort(FunctionalIR::Sort sort) : sort(sort) {}
diff --git a/kernel/sexpr.cc b/kernel/sexpr.cc
new file mode 100644
index 00000000000..0b977d2a89c
--- /dev/null
+++ b/kernel/sexpr.cc
@@ -0,0 +1,163 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "sexpr.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+std::ostream &operator<<(std::ostream &os, SExpr const &sexpr) {
+    if(sexpr.is_atom())
+        os << sexpr.atom();
+    else if(sexpr.is_list()){
+        os << "(";
+        auto l = sexpr.list();
+        for(size_t i = 0; i < l.size(); i++) {
+            if(i > 0) os << " ";
+            os << l[i];
+        }
+        os << ")";
+    }else
+        os << "<invalid>";
+    return os;
+}
+
+ std::string SExpr::to_string() const {
+    std::stringstream ss;
+    ss << *this;
+    return ss.str();
+}
+
+void SExprWriter::nl_if_pending() {
+    if(_pending_nl) {
+        os << '\n';
+        _pos = 0;
+        _pending_nl = false;
+    }
+}
+
+void SExprWriter::puts(std::string_view s) {
+    if(s.empty()) return;
+    nl_if_pending();
+    for(auto c : s) {
+        if(c == '\n') {
+            os << c;
+            _pos = 0;
+        } else {
+            if(_pos == 0) {
+                for(int i = 0; i < _indent; i++)
+                    os << "  ";
+                _pos = 2 * _indent;
+            }
+            os << c;
+            _pos++;
+        }
+    }
+}
+
+
+// Calculate how much space would be left if expression was written
+// out in full horizontally. Returns any negative value if it doesn't fit.
+//
+// (Ideally we would avoid recalculating the widths of subexpression,
+// but I can't figure out how to store the widths. As an alternative,
+// we bail out of the calculation as soon as we can tell the expression
+// doesn't fit in the available space.)
+int SExprWriter::check_fit(SExpr const &sexpr, int space) {
+    if(sexpr.is_atom())
+        return space - sexpr.atom().size();
+    else if(sexpr.is_list()) {
+        space -= 2;
+        if(sexpr.list().size() > 1)
+            space -= sexpr.list().size() - 1;
+        for(auto arg : sexpr.list()) {
+            if(space < 0) break;
+            space = check_fit(arg, space);
+        }
+        return space;
+    } else
+        return -1;
+}
+
+void SExprWriter::print(SExpr const &sexpr, bool close, bool indent_rest) {
+    if(sexpr.is_atom())
+        puts(sexpr.atom());
+    else if(sexpr.is_list()) {
+        auto args = sexpr.list();
+        puts("(");
+        // Expressions are printed horizontally if they fit on the line.
+        // We do the check *after* puts("(") to make sure that _pos is accurate.
+        // (Otherwise there could be a pending newline + indentation)
+        bool vertical = args.size() > 1 && check_fit(sexpr, _max_line_width - _pos + 1) < 0;
+        if(vertical) _indent++;
+        for(size_t i = 0; i < args.size(); i++) {
+            if(i > 0) puts(vertical ? "\n" : " ");
+            print(args[i]);
+        }
+        // Any remaining arguments are currently always printed vertically,
+        // but are not indented if indent_rest = false.
+        _indent += (!close && indent_rest) - vertical;
+        if(close)
+            puts(")");
+        else {
+            _unclosed.push_back(indent_rest);
+            _pending_nl = true;
+        }
+    }else
+        log_error("shouldn't happen: SExpr '%s' is neither an atom nor a list", sexpr.to_string().c_str());
+}
+
+void SExprWriter::close(size_t n) {
+    log_assert(_unclosed.size() - (_unclosed_stack.empty() ? 0 : _unclosed_stack.back()) >= n);
+    while(n-- > 0) {
+        bool indented = _unclosed[_unclosed.size() - 1];
+        _unclosed.pop_back();
+        // Only print ) on the same line if it fits.
+        _pending_nl = _pos >= _max_line_width;
+        if(indented)
+            _indent--;
+        puts(")");
+        _pending_nl = true;
+    }
+}
+
+void SExprWriter::comment(std::string const &str, bool hanging) {
+    if(hanging) {
+        if(_pending_nl) {
+            _pending_nl = false;
+            puts(" ");
+        }
+    }
+    size_t i = 0, e;
+    do{
+        e = str.find('\n', i);
+        puts("; ");
+        puts(std::string_view(str).substr(i, e - i));
+        puts("\n");
+        i = e + 1;
+    }while(e != std::string::npos);
+}
+
+SExprWriter::~SExprWriter() {
+    while(!_unclosed_stack.empty())
+        pop();
+    close(_unclosed.size());
+    nl_if_pending();
+}
+
+YOSYS_NAMESPACE_END
diff --git a/kernel/sexpr.h b/kernel/sexpr.h
new file mode 100644
index 00000000000..41073ea2327
--- /dev/null
+++ b/kernel/sexpr.h
@@ -0,0 +1,122 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef SEXPR_H
+#define SEXPR_H
+
+#include "kernel/yosys.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+class SExpr {
+public:
+	std::variant<std::vector<SExpr>, std::string> _v;
+public:
+	SExpr(std::string a) : _v(std::move(a)) {}
+    SExpr(const char *a) : _v(a) {}
+    // FIXME: should maybe be defined for all integral types
+	SExpr(int n) : _v(std::to_string(n)) {}
+	SExpr(std::vector<SExpr> const &l) : _v(l) {}
+	SExpr(std::vector<SExpr> &&l) : _v(std::move(l)) {}
+    // It would be nicer to have an std::initializer_list constructor,
+    // but that causes confusing issues with overload resolution sometimes.
+    template<typename... Args> static SExpr list(Args&&... args) {
+	    return SExpr(std::vector<SExpr>{std::forward<Args>(args)...});
+    }
+    bool is_atom() const { return std::holds_alternative<std::string>(_v); }
+    std::string const &atom() const { return std::get<std::string>(_v); }
+    bool is_list() const { return std::holds_alternative<std::vector<SExpr>>(_v); }
+    std::vector<SExpr> const &list() const { return std::get<std::vector<SExpr>>(_v); }
+	std::string to_string() const;
+};
+
+std::ostream &operator<<(std::ostream &os, SExpr const &sexpr);
+
+namespace SExprUtil {
+    // A little hack so that `using SExprUtil::list` lets you import a shortcut to `SExpr::list`
+    template<typename... Args> SExpr list(Args&&... args) {
+	    return SExpr(std::vector<SExpr>{std::forward<Args>(args)...});
+    }
+}
+
+// SExprWriter is a pretty printer for s-expr. It does not try very hard to get a good layout.
+class SExprWriter {
+    std::ostream &os;
+    int _max_line_width;
+    int _indent = 0;
+    int _pos = 0;
+    // If _pending_nl is set, print a newline before the next character.
+    // This lets us "undo" the last newline so we can put
+    // closing parentheses or a hanging comment on the same line.
+    bool _pending_nl = false;
+    // Unclosed parentheses (boolean stored is indent_rest)
+	vector<bool> _unclosed;
+    // Used only for push() and pop() (stores _unclosed.size())
+	vector<size_t> _unclosed_stack;
+	void nl_if_pending();
+    void puts(std::string_view s);
+    int check_fit(SExpr const &sexpr, int space);
+    void print(SExpr const &sexpr, bool close = true, bool indent_rest = true);
+public:
+    SExprWriter(std::ostream &os, int max_line_width = 80)
+        : os(os)
+        , _max_line_width(max_line_width)
+    {}
+    // Print an s-expr.
+    SExprWriter &operator <<(SExpr const &sexpr) {
+        print(sexpr);
+        _pending_nl = true;
+        return *this;
+    }
+    // Print an s-expr (which must be a list), but leave room for extra elements
+    // which may be printed using either << or further calls to open.
+    // If indent_rest = false, the remaining elements are not intended
+    // (for avoiding unreasonable indentation on deeply nested structures).
+    void open(SExpr const &sexpr, bool indent_rest = true) {
+        log_assert(sexpr.is_list());
+        print(sexpr, false, indent_rest);
+    }
+    // Close the s-expr opened with the last call to open
+    // (if an argument is given, close that many s-exprs).
+    void close(size_t n = 1);
+    // push() remembers how many s-exprs are currently open
+	void push() {
+		_unclosed_stack.push_back(_unclosed.size());
+	}
+    // pop() closes all s-expr opened since the corresponding call to push()
+	void pop() {
+		auto t = _unclosed_stack.back();
+		log_assert(_unclosed.size() >= t);
+		close(_unclosed.size() - t);
+		_unclosed_stack.pop_back();
+	}
+    // Print a comment.
+    // If hanging = true, append it to the end of the last printed s-expr.
+	void comment(std::string const &str, bool hanging = false);
+    // Flush any unprinted characters to the std::ostream, but does not close unclosed parentheses.
+    void flush() {
+        nl_if_pending();
+    }
+    // Destructor closes any unclosed parentheses and flushes.
+    ~SExprWriter();
+};
+
+YOSYS_NAMESPACE_END
+
+#endif

From 6e7ae88c6a22980bdcc290851b5a4533b211a84c Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Fri, 12 Jul 2024 10:45:31 +0100
Subject: [PATCH 407/499] fix bugs in smtlib backend

---
 backends/functional/smtlib.cc | 27 +++++++++++++++++----------
 1 file changed, 17 insertions(+), 10 deletions(-)

diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index 43e6f5bf489..113fb710080 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -28,6 +28,7 @@ PRIVATE_NAMESPACE_BEGIN
 using SExprUtil::list;
 
 const char *reserved_keywords[] = {
+	// reserved keywords from the smtlib spec
 	"BINARY", "DECIMAL", "HEXADECIMAL", "NUMERAL", "STRING", "_", "!", "as", "let", "exists", "forall", "match", "par",
 	"assert", "check-sat", "check-sat-assuming", "declare-const", "declare-datatype", "declare-datatypes",
 	"declare-fun", "declare-sort", "define-fun", "define-fun-rec", "define-funs-rec", "define-sort",
@@ -35,6 +36,7 @@ const char *reserved_keywords[] = {
 	"get-option", "get-proof", "get-unsat-assumptions", "get-unsat-core", "get-value",
 	"pop", "push", "reset", "reset-assertions", "set-info", "set-logic", "set-option",
 
+	// reserved for our own purposes
 	"pair", "Pair", "first", "second",
 	"inputs", "state",
 	nullptr
@@ -89,12 +91,17 @@ class SmtStruct {
 		w.close(3);
 	}
 	template<typename Fn> void write_value(SExprWriter &w, Fn fn) {
-		w.open(list(name));
-		for(auto field_name : field_names) {
-			w << fn(field_name);
-			w.comment(RTLIL::unescape_id(field_name), true);
+		if(field_names.empty()) {
+			// Zero-argument constructors in SMTLIB must not be called as functions.
+			w << name;
+		} else {
+			w.open(list(name));
+			for(auto field_name : field_names) {
+				w << fn(field_name);
+				w.comment(RTLIL::unescape_id(field_name), true);
+			}
+			w.close();
 		}
-		w.close();
 	}
 	SExpr access(SExpr record, IdString name) {
 		size_t i = field_names.at(name);
@@ -131,7 +138,7 @@ struct SmtPrintVisitor {
 	SExpr slice(Node, Node a, int, int offset, int out_width) { return extract(n(a), offset, out_width); }
 	SExpr zero_extend(Node, Node a, int, int out_width) { return list(list("_", "zero_extend", out_width - a.width()), n(a)); }
 	SExpr sign_extend(Node, Node a, int, int out_width) { return list(list("_", "sign_extend", out_width - a.width()), n(a)); }
-	SExpr concat(Node, Node a, int, Node b, int) { return list("concat", n(a), n(b)); }
+	SExpr concat(Node, Node a, int, Node b, int) { return list("concat", n(b), n(a)); }
 	SExpr add(Node, Node a, Node b, int) { return list("bvadd", n(a), n(b)); }
 	SExpr sub(Node, Node a, Node b, int) { return list("bvsub", n(a), n(b)); }
 	SExpr mul(Node, Node a, Node b, int) { return list("bvmul", n(a), n(b)); }
@@ -143,7 +150,7 @@ struct SmtPrintVisitor {
 	SExpr bitwise_not(Node, Node a, int) { return list("bvnot", n(a)); }
 	SExpr unary_minus(Node, Node a, int) { return list("bvneg", n(a)); }
 	SExpr reduce_and(Node, Node a, int) { return from_bool(list("=", n(a), literal(RTLIL::Const(State::S1, a.width())))); }
-	SExpr reduce_or(Node, Node a, int) { return from_bool(list("=", n(a), literal(RTLIL::Const(State::S0, a.width())))); }
+	SExpr reduce_or(Node, Node a, int) { return from_bool(list("distinct", n(a), literal(RTLIL::Const(State::S0, a.width())))); }
 	SExpr reduce_xor(Node, Node a, int) {
 		vector<SExpr> s { "bvxor" };
 		for(int i = 0; i < a.width(); i++)
@@ -164,9 +171,9 @@ struct SmtPrintVisitor {
 			return std::move(a);
 	}
 	SExpr logical_shift_left(Node, Node a, Node b, int, int) { return list("bvshl", n(a), extend(n(b), b.width(), a.width())); }
-	SExpr logical_shift_right(Node, Node a, Node b, int, int) { return list("bvshr", n(a), extend(n(b), b.width(), a.width())); }
-	SExpr arithmetic_shift_right(Node, Node a, Node b, int, int) { return list("bvasr", n(a), extend(n(b), b.width(), a.width())); }
-	SExpr mux(Node, Node a, Node b, Node s, int) { return list("ite", to_bool(n(s)), n(a), n(b)); }
+	SExpr logical_shift_right(Node, Node a, Node b, int, int) { return list("bvlshr", n(a), extend(n(b), b.width(), a.width())); }
+	SExpr arithmetic_shift_right(Node, Node a, Node b, int, int) { return list("bvashr", n(a), extend(n(b), b.width(), a.width())); }
+	SExpr mux(Node, Node a, Node b, Node s, int) { return list("ite", to_bool(n(s)), n(b), n(a)); }
 	SExpr pmux(Node, Node a, Node b, Node s, int, int) {
 		SExpr rv = n(a);
 		for(int i = 0; i < s.width(); i++)

From 9ad859fc0a9828ba339ec1fc40eecb842a42acac Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Fri, 12 Jul 2024 10:45:58 +0100
Subject: [PATCH 408/499] add bwmux, bweqx, bmux, demux cells

---
 kernel/functionalir.cc | 80 +++++++++++++++++++++++++++++-------------
 1 file changed, 56 insertions(+), 24 deletions(-)

diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc
index c5406f41283..6983facfb72 100644
--- a/kernel/functionalir.cc
+++ b/kernel/functionalir.cc
@@ -96,6 +96,15 @@ class CellSimplifier {
 		}
 		return r;
 	}
+	T handle_bmux(T a, T s, int a_width, int a_offset, int width, int s_width, int sn) {
+		if(sn < 1)
+			return factory.slice(a, a_width, a_offset, width);
+		else {
+			T y0 = handle_bmux(a, s, a_width, a_offset, width, s_width, sn - 1);
+			T y1 = handle_bmux(a, s, a_width, a_offset + (width << (sn - 1)), width, s_width, sn - 1);
+			return factory.mux(y0, y1, factory.slice(s, s_width, sn - 1, 1), width);
+		}
+	}
 public:
 	T handle(IdString cellType, dict<IdString, Const> parameters, dict<IdString, T> inputs)
 	{
@@ -248,31 +257,54 @@ class CellSimplifier {
 					return extend(factory.unsigned_div(a, b, width), width, y_width, false);
 			}
 		} else if(cellType == ID($pow)) {
-		  return handle_pow(inputs.at(ID(A)), a_width, inputs.at(ID(B)), b_width, y_width, a_signed && b_signed);
+			return handle_pow(inputs.at(ID(A)), a_width, inputs.at(ID(B)), b_width, y_width, a_signed && b_signed);
 		} else if (cellType == ID($lut)) {
-		  int width = parameters.at(ID(WIDTH)).as_int();
-		  Const lut_table = parameters.at(ID(LUT));
-		  T a = inputs.at(ID(A));
-
-		  // Output initialization
-		  T y = factory.constant(Const(0, 1));
-
-		  // Iterate over each possible input combination
-		  for (int i = 0; i < (1 << width); ++i) {
-		    // Create a constant representing the value of i
-		    T i_val = factory.constant(Const(i, width));
-		    // Check if the input matches this value
-		    T match = factory.equal(a, i_val, width);
-		    // Get the corresponding LUT value
-		    bool lut_val = lut_table.bits[i] == State::S1;
-		    T lut_output = factory.constant(Const(lut_val, 1));
-		    // Use a multiplexer to select the correct output based on the match
-		    y = factory.mux(y, lut_output, match, 1);
-		  }
-
-		  return y;
-		} else{
-		  log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str());
+			int width = parameters.at(ID(WIDTH)).as_int();
+			Const lut_table = parameters.at(ID(LUT));
+			T a = inputs.at(ID(A));
+			// Output initialization
+			T y = factory.constant(Const(0, 1));
+			// Iterate over each possible input combination
+			for (int i = 0; i < (1 << width); ++i) {
+				// Create a constant representing the value of i
+				T i_val = factory.constant(Const(i, width));
+				// Check if the input matches this value
+				T match = factory.equal(a, i_val, width);
+				// Get the corresponding LUT value
+				bool lut_val = lut_table.bits[i] == State::S1;
+				T lut_output = factory.constant(Const(lut_val, 1));
+				// Use a multiplexer to select the correct output based on the match
+				y = factory.mux(y, lut_output, match, 1);
+			}
+			return y;
+		} else if (cellType == ID($bwmux)) {
+			int width = parameters.at(ID(WIDTH)).as_int();
+			T a = inputs.at(ID(A));
+			T b = inputs.at(ID(B));
+			T s = inputs.at(ID(S));
+			return factory.bitwise_or(
+				factory.bitwise_and(a, factory.bitwise_not(s, width), width),
+				factory.bitwise_and(b, s, width), width);
+		} else if (cellType == ID($bweqx)) {
+			int width = parameters.at(ID(WIDTH)).as_int();
+			T a = inputs.at(ID(A));
+			T b = inputs.at(ID(B));
+			return factory.bitwise_not(factory.bitwise_xor(a, b, width), width);
+		} else if(cellType == ID($bmux)) {
+			int width = parameters.at(ID(WIDTH)).as_int();
+			int s_width = parameters.at(ID(S_WIDTH)).as_int();
+			return handle_bmux(inputs.at(ID(A)), inputs.at(ID(S)), width << s_width, 0, width, s_width, s_width);
+		} else if(cellType == ID($demux)) {
+			int width = parameters.at(ID(WIDTH)).as_int();
+			int s_width = parameters.at(ID(S_WIDTH)).as_int();
+			int y_width = width << s_width;
+			int b_width = ceil_log2(y_width + 1);
+			T a = extend(inputs.at(ID(A)), width, y_width, false);
+			T s = factory.extend(inputs.at(ID(S)), s_width, b_width, false);
+			T b = factory.mul(s, factory.constant(Const(width, b_width)), b_width);
+			return factory.logical_shift_left(a, b, y_width, b_width);
+		} else {
+			log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str());
 		}
 	}
 };

From 674e6d201de267806f435077007d41441dedae8d Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Fri, 12 Jul 2024 11:07:33 +0100
Subject: [PATCH 409/499] rewrite functional backend test code in python

---
 tests/functional/README.md                    |  19 ++
 tests/functional/conftest.py                  |  14 +
 tests/functional/rtlil_cells.py               | 275 ++++++++++++++++++
 tests/functional/run-test.sh                  |   2 +
 tests/functional/single_cells/rtlil/README.md |   2 -
 tests/functional/single_cells/rtlil/ff.il     |  83 ------
 .../single_cells/rtlil/multiple_outputs.il    |  69 -----
 .../single_cells/rtlil/test_cell_add_00000.il |  17 --
 .../single_cells/rtlil/test_cell_alu_00000.il |  25 --
 .../single_cells/rtlil/test_cell_and_00000.il |  17 --
 .../rtlil/test_cell_bmux_00000.il             |  14 -
 .../rtlil/test_cell_demux_00000.il            |  14 -
 .../single_cells/rtlil/test_cell_div_00000.il |  17 --
 .../rtlil/test_cell_divfloor_00000.il         |  17 --
 .../single_cells/rtlil/test_cell_eq_00000.il  |  17 --
 .../single_cells/rtlil/test_cell_fa_00000.il  |  17 --
 .../single_cells/rtlil/test_cell_ge_00000.il  |  17 --
 .../single_cells/rtlil/test_cell_gt_00000.il  |  17 --
 .../single_cells/rtlil/test_cell_lcu_00000.il |  15 -
 .../single_cells/rtlil/test_cell_le_00000.il  |  17 --
 .../rtlil/test_cell_logic_and_00000.il        |  17 --
 .../rtlil/test_cell_logic_not_00000.il        |  13 -
 .../rtlil/test_cell_logic_or_00000.il         |  17 --
 .../single_cells/rtlil/test_cell_lt_00000.il  |  17 --
 .../single_cells/rtlil/test_cell_lut_00000.il |  12 -
 .../rtlil/test_cell_macc_00000.il             |  17 --
 .../single_cells/rtlil/test_cell_mod_00000.il |  17 --
 .../rtlil/test_cell_modfloor_00000.il         |  17 --
 .../single_cells/rtlil/test_cell_mul_00000.il |  17 --
 .../single_cells/rtlil/test_cell_mux_00000.il |  15 -
 .../single_cells/rtlil/test_cell_ne_00000.il  |  17 --
 .../single_cells/rtlil/test_cell_neg_00000.il |  13 -
 .../single_cells/rtlil/test_cell_not_00000.il |  13 -
 .../single_cells/rtlil/test_cell_or_00000.il  |  17 --
 .../single_cells/rtlil/test_cell_pos_00000.il |  13 -
 .../single_cells/rtlil/test_cell_pos_00001.il |  13 -
 .../rtlil/test_cell_reduce_and_00000.il       |  13 -
 .../rtlil/test_cell_reduce_bool_00000.il      |  13 -
 .../rtlil/test_cell_reduce_or_00000.il        |  13 -
 .../rtlil/test_cell_reduce_xnor_00000.il      |  13 -
 .../rtlil/test_cell_reduce_xor_00000.il       |  13 -
 .../rtlil/test_cell_shift_00000.il            |  17 --
 .../rtlil/test_cell_shiftx_00000.il           |  17 --
 .../single_cells/rtlil/test_cell_shl_00000.il |  17 --
 .../single_cells/rtlil/test_cell_shr_00000.il |  17 --
 .../single_cells/rtlil/test_cell_sop_00000.il |  13 -
 .../rtlil/test_cell_sshl_00000.il             |  17 --
 .../rtlil/test_cell_sshr_00000.il             |  17 --
 .../single_cells/rtlil/test_cell_sub_00000.il |  17 --
 .../rtlil/test_cell_xnor_00000.il             |  17 --
 .../single_cells/rtlil/test_cell_xor_00000.il |  17 --
 tests/functional/single_cells/run-test.sh     | 172 -----------
 .../single_cells/vcd_harness_smt.py           | 214 --------------
 tests/functional/smt_vcd.py                   | 180 ++++++++++++
 {backends => tests}/functional/smtio.py       |   0
 tests/functional/test_functional.py           |  63 ++++
 .../{single_cells => }/vcd_harness.cc         |   2 +-
 57 files changed, 554 insertions(+), 1238 deletions(-)
 create mode 100644 tests/functional/README.md
 create mode 100644 tests/functional/conftest.py
 create mode 100644 tests/functional/rtlil_cells.py
 create mode 100755 tests/functional/run-test.sh
 delete mode 100644 tests/functional/single_cells/rtlil/README.md
 delete mode 100644 tests/functional/single_cells/rtlil/ff.il
 delete mode 100644 tests/functional/single_cells/rtlil/multiple_outputs.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_add_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_alu_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_and_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_bmux_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_demux_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_div_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_eq_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_fa_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_ge_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_gt_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_lcu_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_le_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_logic_not_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_logic_or_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_lt_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_lut_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_macc_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_mod_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_modfloor_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_mul_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_mux_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_ne_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_neg_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_not_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_or_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_pos_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_pos_00001.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_reduce_and_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_reduce_bool_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_reduce_or_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_reduce_xnor_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_reduce_xor_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_shift_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_shiftx_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_shl_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_shr_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_sop_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_sshl_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_sshr_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_sub_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_xnor_00000.il
 delete mode 100644 tests/functional/single_cells/rtlil/test_cell_xor_00000.il
 delete mode 100755 tests/functional/single_cells/run-test.sh
 delete mode 100644 tests/functional/single_cells/vcd_harness_smt.py
 create mode 100644 tests/functional/smt_vcd.py
 rename {backends => tests}/functional/smtio.py (100%)
 create mode 100644 tests/functional/test_functional.py
 rename tests/functional/{single_cells => }/vcd_harness.cc (98%)

diff --git a/tests/functional/README.md b/tests/functional/README.md
new file mode 100644
index 00000000000..1459c3198b8
--- /dev/null
+++ b/tests/functional/README.md
@@ -0,0 +1,19 @@
+Tests for the functional backend use pytest as a testrunner.
+
+Run with `pytest -v`
+
+Pytest options you might want:
+
+- `-v`: More progress indication.
+
+- `--basetemp tmp`: Store test files (including vcd results) in tmp. 
+  CAREFUL: contents of tmp will be deleted
+
+- `-k <pattern>`: Run only tests that contain the pattern, e.g.
+  `-k cxx` or `-k smt` or `-k demux` or `-k 'cxx[demux`
+ 
+- `-s`: Don't hide stdout/stderr from the test code.
+
+Custom options for functional backend tests:
+
+- `--per-cell N`: Run only N tests for each cell.
diff --git a/tests/functional/conftest.py b/tests/functional/conftest.py
new file mode 100644
index 00000000000..3a66abaab21
--- /dev/null
+++ b/tests/functional/conftest.py
@@ -0,0 +1,14 @@
+import pytest
+from rtlil_cells import generate_test_cases
+
+def pytest_addoption(parser):
+    parser.addoption(
+        "--per-cell", type=int, default=None, help="run only N tests per cell"
+    )
+
+def pytest_generate_tests(metafunc):
+    if "cell" in metafunc.fixturenames:
+        print(dir(metafunc.config))
+        per_cell = metafunc.config.getoption("per_cell", default=None)
+        names, cases = generate_test_cases(per_cell)
+        metafunc.parametrize("cell,parameters", cases, ids=names)
\ No newline at end of file
diff --git a/tests/functional/rtlil_cells.py b/tests/functional/rtlil_cells.py
new file mode 100644
index 00000000000..e96baa18ee8
--- /dev/null
+++ b/tests/functional/rtlil_cells.py
@@ -0,0 +1,275 @@
+from itertools import chain
+import random
+
+widths = [
+    (16, 32, 48, True),
+    (16, 32, 48, False),
+    (32, 16, 48, True),
+    (32, 16, 48, False),
+    (32, 32, 16, True),
+    (32, 32, 16, False)
+]
+
+shift_widths = [
+    (32, 6, 32, True, False),
+    (32, 6, 32, False, False),
+    (32, 6, 64, True, False),
+    (32, 6, 64, False, False),
+    (32, 32, 16, True, False),
+    (32, 32, 16, False, False),
+    (32, 6, 32, True, True),
+    (32, 6, 32, False, True),
+    (32, 6, 64, True, True),
+    (32, 6, 64, False, True),
+    (32, 32, 16, True, True),
+    (32, 32, 16, False, True),
+]
+
+def write_rtlil_cell(f, cell_type, inputs, outputs, parameters):
+    f.write('autoidx 1\n')
+    f.write('module \\gold\n')
+    idx = 1
+    for name, width in inputs.items():
+        f.write(f'\twire width {width} input {idx} \\{name}\n')
+        idx += 1
+    for name, width in outputs.items():
+        f.write(f'\twire width {width} output {idx} \\{name}\n')
+        idx += 1
+    f.write(f'\tcell ${cell_type} \\UUT\n')
+    for (name, value) in parameters.items():
+        f.write(f'\t\tparameter \\{name} {value}\n')
+    for name in chain(inputs.keys(), outputs.keys()):
+        f.write(f'\t\tconnect \\{name} \\{name}\n')
+    f.write(f'\tend\nend\n')
+
+class BaseCell:
+    def __init__(self, name):
+        self.name = name
+
+class UnaryCell(BaseCell):
+    def __init__(self, name):
+        super().__init__(name)
+    def generate_tests(self):
+        for (a_width, _, y_width, signed) in widths:
+            yield (f'{a_width}-{y_width}-{'S' if signed else 'U'}',
+                   {'A_WIDTH' : a_width,
+                    'A_SIGNED' : int(signed),
+                    'Y_WIDTH' : y_width})
+    def write_rtlil_file(self, f, parameters):
+        write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters)
+
+class BinaryCell(BaseCell):
+    def __init__(self, name):
+        super().__init__(name)
+    def generate_tests(self):
+        for (a_width, b_width, y_width, signed) in widths:
+            yield (f'{a_width}-{b_width}-{y_width}-{'S' if signed else 'U'}',
+                   {'A_WIDTH' : a_width,
+                    'A_SIGNED' : int(signed),
+                    'B_WIDTH' : b_width,
+                    'B_SIGNED' : int(signed),
+                    'Y_WIDTH' : y_width})
+    def write_rtlil_file(self, f, parameters):
+        write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH'], 'B': parameters['B_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters)
+
+class ShiftCell(BaseCell):
+    def __init__(self, name):
+        super().__init__(name)
+    def generate_tests(self):
+        for (a_width, b_width, y_width, a_signed, b_signed) in shift_widths:
+            if not self.name in ('shift', 'shiftx') and b_signed: continue
+            if self.name == 'shiftx' and a_signed: continue
+            yield (f'{a_width}-{b_width}-{y_width}-{'S' if a_signed else 'U'}{'S' if b_signed else 'U'}',
+                   {'A_WIDTH' : a_width,
+                    'A_SIGNED' : int(a_signed),
+                    'B_WIDTH' : b_width,
+                    'B_SIGNED' : int(b_signed),
+                    'Y_WIDTH' : y_width})
+    def write_rtlil_file(self, f, parameters):
+        write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH'], 'B': parameters['B_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters)
+
+class MuxCell(BaseCell):
+    def __init__(self, name):
+        super().__init__(name)
+    def generate_tests(self):
+        for width in [10, 20, 40]:
+            yield (f'{width}', {'WIDTH' : width})
+    def write_rtlil_file(self, f, parameters):
+        write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'], 'B': parameters['WIDTH'], 'S': 1}, {'Y': parameters['WIDTH']}, parameters)
+
+class BWCell(BaseCell):
+    def __init__(self, name):
+        super().__init__(name)
+    def generate_tests(self):
+        for width in [10, 20, 40]:
+            yield (f'{width}', {'WIDTH' : width})
+    def write_rtlil_file(self, f, parameters):
+        inputs = {'A': parameters['WIDTH'], 'B': parameters['WIDTH']}
+        if self.name == "bwmux": inputs['S'] = parameters['WIDTH']
+        write_rtlil_cell(f, self.name, inputs, {'Y': parameters['WIDTH']}, parameters)
+
+class PMuxCell(BaseCell):
+    def __init__(self, name):
+        super().__init__(name)
+    def generate_tests(self):
+        for (width, s_width) in [(10, 1), (10, 4), (20, 4)]:
+            yield (f'{width}-{s_width}',
+                   {'WIDTH' : width,
+                    'S_WIDTH' : s_width})
+    def write_rtlil_file(self, f, parameters):
+        s_width = parameters['S_WIDTH']
+        b_width = parameters['WIDTH'] * s_width
+        write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'], 'B': b_width, 'S': s_width}, {'Y': parameters['WIDTH']}, parameters)
+
+class BMuxCell(BaseCell):
+    def __init__(self, name):
+        super().__init__(name)
+    def generate_tests(self):
+        for (width, s_width) in [(10, 1), (10, 2), (10, 4)]:
+            yield (f'{width}-{s_width}', {'WIDTH' : width, 'S_WIDTH' : s_width})
+    def write_rtlil_file(self, f, parameters):
+        write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'] << parameters['S_WIDTH'], 'S': parameters['S_WIDTH']}, {'Y': parameters['WIDTH']}, parameters)
+
+class DemuxCell(BaseCell):
+    def __init__(self, name):
+        super().__init__(name)
+    def generate_tests(self):
+        for (width, s_width) in [(10, 1), (32, 2), (16, 4)]:
+            yield (f'{width}-{s_width}', {'WIDTH' : width, 'S_WIDTH' : s_width})
+    def write_rtlil_file(self, f, parameters):
+        write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'], 'S': parameters['S_WIDTH']}, {'Y': parameters['WIDTH'] << parameters['S_WIDTH']}, parameters)
+
+def seeded_randint(seed, a, b):
+    r = random.getstate()
+    random.seed(seed)
+    n = random.randint(a, b)
+    random.setstate(r)
+    return n
+
+class LUTCell(BaseCell):
+    def __init__(self, name):
+        super().__init__(name)
+    def generate_tests(self):
+        for width in [4, 6, 8]:
+            lut = seeded_randint(width, 0, 2**width - 1)
+            yield (f'{width}', {'WIDTH' : width, 'LUT' : lut})
+    def write_rtlil_file(self, f, parameters):
+        write_rtlil_cell(f, self.name, {'A': parameters['WIDTH']}, {'Y': 1}, parameters)
+
+class ConcatCell(BaseCell):
+    def __init__(self, name):
+        super().__init__(name)
+    def generate_tests(self):
+        for (a_width, b_width) in [(16, 16), (8, 14), (20, 10)]:
+            yield (f'{a_width}-{b_width}', {'A_WIDTH' : a_width, 'B_WIDTH' : b_width})
+    def write_rtlil_file(self, f, parameters):
+        write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH'], 'B' : parameters['B_WIDTH']}, {'Y': parameters['A_WIDTH'] + parameters['B_WIDTH']}, parameters)
+
+class SliceCell(BaseCell):
+    def __init__(self, name):
+        super().__init__(name)
+    def generate_tests(self):
+        for (a_width, offset, y_width) in [(32, 10, 15), (8, 0, 4), (10, 0, 10)]:
+            yield (f'{a_width}-{offset}-{y_width}', {'A_WIDTH' : a_width, 'OFFSET' : offset, 'Y_WIDTH': y_width})
+    def write_rtlil_file(self, f, parameters):
+        write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters)
+
+class FailCell(BaseCell):
+    def __init__(self, name):
+        super().__init__(name)
+    def generate_tests(self):
+        yield ('', {})
+    def write_rtlil_file(self, f, parameters):
+        raise Exception(f'\'{self.name}\' cell unimplemented in test generator')
+
+rtlil_cells = [
+    UnaryCell("not"),
+    UnaryCell("pos"),
+    UnaryCell("neg"),
+    BinaryCell("and"),
+    BinaryCell("or"),
+    BinaryCell("xor"),
+    BinaryCell("xnor"),
+    UnaryCell("reduce_and"),
+    UnaryCell("reduce_or"),
+    UnaryCell("reduce_xor"),
+    UnaryCell("reduce_xnor"),
+    UnaryCell("reduce_bool"),
+    ShiftCell("shl"),
+    ShiftCell("shr"),
+    ShiftCell("sshl"),
+    ShiftCell("sshr"),
+    ShiftCell("shift"),
+    ShiftCell("shiftx"),
+#    ("fa", ["A", "B", "C", "X", "Y"]),
+#    ("lcu", ["P", "G", "CI", "CO"]),
+#    ("alu", ["A", "B", "CI", "BI", "X", "Y", "CO"]),
+    BinaryCell("lt"),
+    BinaryCell("le"),
+    BinaryCell("eq"),
+    BinaryCell("ne"),
+    BinaryCell("eqx"),
+    BinaryCell("nex"),
+    BinaryCell("ge"),
+    BinaryCell("gt"),
+    BinaryCell("add"),
+    BinaryCell("sub"),
+    BinaryCell("mul"),
+#    BinaryCell("macc"),
+    BinaryCell("div"),
+    BinaryCell("mod"),
+    BinaryCell("divfloor"),
+    BinaryCell("modfloor"),
+    BinaryCell("pow"),
+    UnaryCell("logic_not"),
+    BinaryCell("logic_and"),
+    BinaryCell("logic_or"),
+    SliceCell("slice"),
+    ConcatCell("concat"),
+    MuxCell("mux"),
+    BMuxCell("bmux"),
+    PMuxCell("pmux"),
+    DemuxCell("demux"),
+    LUTCell("lut"),
+#    ("sop", ["A", "Y"]),
+#    ("tribuf", ["A", "EN", "Y"]),
+#    ("specify2", ["EN", "SRC", "DST"]),
+#    ("specify3", ["EN", "SRC", "DST", "DAT"]),
+#    ("specrule", ["EN_SRC", "EN_DST", "SRC", "DST"]),
+    BWCell("bweqx"),
+    BWCell("bwmux"),
+#    ("assert", ["A", "EN"]),
+#    ("assume", ["A", "EN"]),
+#    ("live", ["A", "EN"]),
+#    ("fair", ["A", "EN"]),
+#    ("cover", ["A", "EN"]),
+#    ("initstate", ["Y"]),
+#    ("anyconst", ["Y"]),
+#    ("anyseq", ["Y"]),
+#    ("anyinit", ["D", "Q"]),
+#    ("allconst", ["Y"]),
+#    ("allseq", ["Y"]),
+#    ("equiv", ["A", "B", "Y"]),
+#    ("print", ["EN", "TRG", "ARGS"]),
+#    ("check", ["A", "EN", "TRG", "ARGS"]),
+#    ("set_tag", ["A", "SET", "CLR", "Y"]),
+#    ("get_tag", ["A", "Y"]),
+#    ("overwrite_tag", ["A", "SET", "CLR"]),
+#    ("original_tag", ["A", "Y"]),
+#    ("future_ff", ["A", "Y"]),
+#    ("scopeinfo", []),
+]
+
+def generate_test_cases(per_cell):
+    tests = []
+    names = []
+    for cell in rtlil_cells:
+        seen_names = set()
+        for (name, parameters) in cell.generate_tests():
+            if not name in seen_names:
+                seen_names.add(name)
+                tests.append((cell, parameters))
+                names.append(f'{cell.name}-{name}' if name != '' else cell.name)
+                if per_cell is not None and len(seen_names) >= per_cell:
+                    break
+    return (names, tests)
\ No newline at end of file
diff --git a/tests/functional/run-test.sh b/tests/functional/run-test.sh
new file mode 100755
index 00000000000..b9a0595f663
--- /dev/null
+++ b/tests/functional/run-test.sh
@@ -0,0 +1,2 @@
+#!/usr/bin/env bash
+pytest -v "$@"
diff --git a/tests/functional/single_cells/rtlil/README.md b/tests/functional/single_cells/rtlil/README.md
deleted file mode 100644
index 4bb84565b7e..00000000000
--- a/tests/functional/single_cells/rtlil/README.md
+++ /dev/null
@@ -1,2 +0,0 @@
-# Creation of test files
-yosys -p "test_cell -n 1 -w test_cell all"
\ No newline at end of file
diff --git a/tests/functional/single_cells/rtlil/ff.il b/tests/functional/single_cells/rtlil/ff.il
deleted file mode 100644
index 6e5a1a339d0..00000000000
--- a/tests/functional/single_cells/rtlil/ff.il
+++ /dev/null
@@ -1,83 +0,0 @@
-# Generated by Yosys 0.40+7 (git sha1 4fd5b29f9, g++ 13.2.0 -Og -fPIC)
-autoidx 19
-attribute \cells_not_processed 1
-attribute \src "dff.v:1.1-16.10"
-module \gold
-  attribute \src "dff.v:8.5-14.8"
-  wire $0\q[0:0]
-  attribute \init 1'0
-  wire $auto$clk2fflogic.cc:65:sample_control$\reset#sampled$13
-  attribute \init 1'1
-  wire $auto$clk2fflogic.cc:77:sample_control_edge$\clk#sampled$7
-  attribute \init 1'0
-  wire $auto$clk2fflogic.cc:91:sample_data$\d#sampled$5
-  attribute \init 1'x
-  wire $auto$clk2fflogic.cc:91:sample_data$\q#sampled$3
-  wire $auto$rtlil.cc:2525:Eqx$10
-  wire $auto$rtlil.cc:2582:Mux$12
-  wire $auto$rtlil.cc:2582:Mux$16
-  wire $auto$rtlil.cc:2582:Mux$18
-  attribute \src "dff.v:2.16-2.19"
-  wire input 1 \clk
-  attribute \src "dff.v:4.16-4.17"
-  wire input 3 \d
-  attribute \keep 1
-  attribute \src "dff.v:5.16-5.17"
-  wire output 4 \q
-  attribute \src "dff.v:3.16-3.21"
-  wire input 2 \reset
-  cell $mux $auto$clk2fflogic.cc:113:mux$11
-    parameter \WIDTH 1
-    connect \A $auto$clk2fflogic.cc:91:sample_data$\q#sampled$3
-    connect \B $auto$clk2fflogic.cc:91:sample_data$\d#sampled$5
-    connect \S $auto$rtlil.cc:2525:Eqx$10
-    connect \Y $auto$rtlil.cc:2582:Mux$12
-  end
-  cell $mux $auto$clk2fflogic.cc:113:mux$15
-    parameter \WIDTH 1
-    connect \A $auto$rtlil.cc:2582:Mux$12
-    connect \B 1'0
-    connect \S $auto$clk2fflogic.cc:65:sample_control$\reset#sampled$13
-    connect \Y $auto$rtlil.cc:2582:Mux$16
-  end
-  cell $mux $auto$clk2fflogic.cc:113:mux$17
-    parameter \WIDTH 1
-    connect \A $auto$rtlil.cc:2582:Mux$16
-    connect \B 1'0
-    connect \S \reset
-    connect \Y $auto$rtlil.cc:2582:Mux$18
-  end
-  cell $ff $auto$clk2fflogic.cc:70:sample_control$14
-    parameter \WIDTH 1
-    connect \D \reset
-    connect \Q $auto$clk2fflogic.cc:65:sample_control$\reset#sampled$13
-  end
-  cell $ff $auto$clk2fflogic.cc:82:sample_control_edge$8
-    parameter \WIDTH 1
-    connect \D \clk
-    connect \Q $auto$clk2fflogic.cc:77:sample_control_edge$\clk#sampled$7
-  end
-  cell $eqx $auto$clk2fflogic.cc:83:sample_control_edge$9
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A { $auto$clk2fflogic.cc:77:sample_control_edge$\clk#sampled$7 \clk }
-    connect \B 2'01
-    connect \Y $auto$rtlil.cc:2525:Eqx$10
-  end
-  attribute \clk2fflogic 1
-  cell $ff $auto$clk2fflogic.cc:98:sample_data$4
-    parameter \WIDTH 1
-    connect \D \q
-    connect \Q $auto$clk2fflogic.cc:91:sample_data$\q#sampled$3
-  end
-  cell $ff $auto$clk2fflogic.cc:98:sample_data$6
-    parameter \WIDTH 1
-    connect \D \d
-    connect \Q $auto$clk2fflogic.cc:91:sample_data$\d#sampled$5
-  end
-  connect $0\q[0:0] \d
-  connect \q $auto$rtlil.cc:2582:Mux$18
-end
diff --git a/tests/functional/single_cells/rtlil/multiple_outputs.il b/tests/functional/single_cells/rtlil/multiple_outputs.il
deleted file mode 100644
index 5e9141a20ad..00000000000
--- a/tests/functional/single_cells/rtlil/multiple_outputs.il
+++ /dev/null
@@ -1,69 +0,0 @@
-# Generated by Yosys 0.40+7 (git sha1 cc795a3f5, g++ 13.2.0 -Og -fPIC)
-autoidx 5
-attribute \cells_not_processed 1
-attribute \src "multiple_outputs.v:1.1-15.10"
-module \gold
-  attribute \src "multiple_outputs.v:11.12-11.20"
-  wire $and$multiple_outputs.v:11$2_Y
-  attribute \src "multiple_outputs.v:10.12-10.14"
-  wire $not$multiple_outputs.v:10$1_Y
-  attribute \src "multiple_outputs.v:12.12-12.20"
-  wire $or$multiple_outputs.v:12$3_Y
-  attribute \src "multiple_outputs.v:13.12-13.20"
-  wire $xor$multiple_outputs.v:13$4_Y
-  attribute \src "multiple_outputs.v:2.16-2.17"
-  wire input 1 \a
-  attribute \src "multiple_outputs.v:3.17-3.18"
-  wire output 2 \b
-  attribute \src "multiple_outputs.v:4.17-4.18"
-  wire output 3 \c
-  attribute \src "multiple_outputs.v:5.17-5.18"
-  wire output 4 \d
-  attribute \src "multiple_outputs.v:6.17-6.18"
-  wire output 5 \e
-  attribute \src "multiple_outputs.v:11.12-11.20"
-  cell $and $and$multiple_outputs.v:11$2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \a
-    connect \B 1'1
-    connect \Y $and$multiple_outputs.v:11$2_Y
-  end
-  attribute \src "multiple_outputs.v:10.12-10.14"
-  cell $not $not$multiple_outputs.v:10$1
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \a
-    connect \Y $not$multiple_outputs.v:10$1_Y
-  end
-  attribute \src "multiple_outputs.v:12.12-12.20"
-  cell $or $or$multiple_outputs.v:12$3
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \a
-    connect \B 1'0
-    connect \Y $or$multiple_outputs.v:12$3_Y
-  end
-  attribute \src "multiple_outputs.v:13.12-13.20"
-  cell $xor $xor$multiple_outputs.v:13$4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \a
-    connect \B 1'1
-    connect \Y $xor$multiple_outputs.v:13$4_Y
-  end
-  connect \b $not$multiple_outputs.v:10$1_Y
-  connect \c $and$multiple_outputs.v:11$2_Y
-  connect \d $or$multiple_outputs.v:12$3_Y
-  connect \e $xor$multiple_outputs.v:13$4_Y
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_add_00000.il b/tests/functional/single_cells/rtlil/test_cell_add_00000.il
deleted file mode 100644
index 531dabe41fa..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_add_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 5 input 1 \A
-  wire width 4 input 2 \B
-  wire width 6 output 3 \Y
-  cell $add \UUT
-    parameter \A_SIGNED 1
-    parameter \A_WIDTH 5
-    parameter \B_SIGNED 1
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 6
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_alu_00000.il b/tests/functional/single_cells/rtlil/test_cell_alu_00000.il
deleted file mode 100644
index ebdd3b7343b..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_alu_00000.il
+++ /dev/null
@@ -1,25 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 8 input 1 \A
-  wire width 7 input 2 \B
-  wire input 3 \BI
-  wire input 4 \CI
-  wire width 6 output 5 \CO
-  wire width 6 output 6 \X
-  wire width 6 output 7 \Y
-  cell $alu \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 7
-    parameter \Y_WIDTH 6
-    connect \A \A
-    connect \B \B
-    connect \BI \BI
-    connect \CI \CI
-    connect \CO \CO
-    connect \X \X
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_and_00000.il b/tests/functional/single_cells/rtlil/test_cell_and_00000.il
deleted file mode 100644
index 2578f60b774..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_and_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 2 input 1 \A
-  wire width 3 input 2 \B
-  wire width 2 output 3 \Y
-  cell $and \UUT
-    parameter \A_SIGNED 1
-    parameter \A_WIDTH 2
-    parameter \B_SIGNED 1
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 2
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_bmux_00000.il b/tests/functional/single_cells/rtlil/test_cell_bmux_00000.il
deleted file mode 100644
index 1b613bd698c..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_bmux_00000.il
+++ /dev/null
@@ -1,14 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 8 input 1 \A
-  wire input 2 \S
-  wire width 4 output 3 \Y
-  cell $bmux \UUT
-    parameter \S_WIDTH 1
-    parameter \WIDTH 4
-    connect \A \A
-    connect \S \S
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_demux_00000.il b/tests/functional/single_cells/rtlil/test_cell_demux_00000.il
deleted file mode 100644
index dbe2dee62ac..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_demux_00000.il
+++ /dev/null
@@ -1,14 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 6 input 1 \A
-  wire width 5 input 2 \S
-  wire width 192 output 3 \Y
-  cell $demux \UUT
-    parameter \S_WIDTH 5
-    parameter \WIDTH 6
-    connect \A \A
-    connect \S \S
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_div_00000.il b/tests/functional/single_cells/rtlil/test_cell_div_00000.il
deleted file mode 100644
index 6f278a7a079..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_div_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 4 input 1 \A
-  wire width 6 input 2 \B
-  wire output 3 \Y
-  cell $div \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 6
-    parameter \Y_WIDTH 1
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il b/tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il
deleted file mode 100644
index 67fce36b331..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 4 input 1 \A
-  wire width 4 input 2 \B
-  wire width 6 output 3 \Y
-  cell $divfloor \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 6
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_eq_00000.il b/tests/functional/single_cells/rtlil/test_cell_eq_00000.il
deleted file mode 100644
index 06fef02b5b2..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_eq_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 5 input 1 \A
-  wire input 2 \B
-  wire width 4 output 3 \Y
-  cell $eq \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 5
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 4
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_fa_00000.il b/tests/functional/single_cells/rtlil/test_cell_fa_00000.il
deleted file mode 100644
index 97f0eb0297d..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_fa_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire input 1 \A
-  wire input 2 \B
-  wire input 3 \C
-  wire output 4 \X
-  wire output 5 \Y
-  cell $fa \UUT
-    parameter \WIDTH 1
-    connect \A \A
-    connect \B \B
-    connect \C \C
-    connect \X \X
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_ge_00000.il b/tests/functional/single_cells/rtlil/test_cell_ge_00000.il
deleted file mode 100644
index 0ac72e9433d..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_ge_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 3 input 1 \A
-  wire width 7 input 2 \B
-  wire width 6 output 3 \Y
-  cell $ge \UUT
-    parameter \A_SIGNED 1
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 1
-    parameter \B_WIDTH 7
-    parameter \Y_WIDTH 6
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_gt_00000.il b/tests/functional/single_cells/rtlil/test_cell_gt_00000.il
deleted file mode 100644
index d4498d36f9e..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_gt_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 7 input 1 \A
-  wire width 3 input 2 \B
-  wire width 4 output 3 \Y
-  cell $gt \UUT
-    parameter \A_SIGNED 1
-    parameter \A_WIDTH 7
-    parameter \B_SIGNED 1
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 4
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_lcu_00000.il b/tests/functional/single_cells/rtlil/test_cell_lcu_00000.il
deleted file mode 100644
index e1bda0b433c..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_lcu_00000.il
+++ /dev/null
@@ -1,15 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire input 1 \CI
-  wire width 2 output 2 \CO
-  wire width 2 input 3 \G
-  wire width 2 input 4 \P
-  cell $lcu \UUT
-    parameter \WIDTH 2
-    connect \CI \CI
-    connect \CO \CO
-    connect \G \G
-    connect \P \P
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_le_00000.il b/tests/functional/single_cells/rtlil/test_cell_le_00000.il
deleted file mode 100644
index 609d99ce8a4..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_le_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 5 input 1 \A
-  wire width 4 input 2 \B
-  wire width 6 output 3 \Y
-  cell $le \UUT
-    parameter \A_SIGNED 1
-    parameter \A_WIDTH 5
-    parameter \B_SIGNED 1
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 6
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il b/tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il
deleted file mode 100644
index 2eae6e3fcb1..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 2 input 1 \A
-  wire width 7 input 2 \B
-  wire output 3 \Y
-  cell $logic_and \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 7
-    parameter \Y_WIDTH 1
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_logic_not_00000.il b/tests/functional/single_cells/rtlil/test_cell_logic_not_00000.il
deleted file mode 100644
index c7898491ca5..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_logic_not_00000.il
+++ /dev/null
@@ -1,13 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 3 input 1 \A
-  wire width 8 output 2 \Y
-  cell $logic_not \UUT
-    parameter \A_SIGNED 1
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 8
-    connect \A \A
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_logic_or_00000.il b/tests/functional/single_cells/rtlil/test_cell_logic_or_00000.il
deleted file mode 100644
index 7a1ef6cbda0..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_logic_or_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 8 input 1 \A
-  wire width 7 input 2 \B
-  wire width 2 output 3 \Y
-  cell $logic_or \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 7
-    parameter \Y_WIDTH 2
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_lt_00000.il b/tests/functional/single_cells/rtlil/test_cell_lt_00000.il
deleted file mode 100644
index fd3ee1f8bad..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_lt_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 8 input 1 \A
-  wire width 5 input 2 \B
-  wire width 6 output 3 \Y
-  cell $lt \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 6
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_lut_00000.il b/tests/functional/single_cells/rtlil/test_cell_lut_00000.il
deleted file mode 100644
index 7c4882bb61a..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_lut_00000.il
+++ /dev/null
@@ -1,12 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 2 input 1 \A
-  wire output 2 \Y
-  cell $lut \UUT
-    parameter \LUT 4'1111
-    parameter \WIDTH 2
-    connect \A \A
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_macc_00000.il b/tests/functional/single_cells/rtlil/test_cell_macc_00000.il
deleted file mode 100644
index 66b51634e97..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_macc_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 3 input 1 \A
-  wire width 0 input 2 \B
-  wire width 2 output 3 \Y
-  cell $macc \UUT
-    parameter \A_WIDTH 3
-    parameter \B_WIDTH 0
-    parameter \CONFIG 10'0110000010
-    parameter \CONFIG_WIDTH 10
-    parameter \Y_WIDTH 2
-    connect \A \A
-    connect \B { }
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_mod_00000.il b/tests/functional/single_cells/rtlil/test_cell_mod_00000.il
deleted file mode 100644
index a484918f05c..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_mod_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 6 input 1 \A
-  wire width 8 input 2 \B
-  wire width 2 output 3 \Y
-  cell $mod \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 8
-    parameter \Y_WIDTH 2
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_modfloor_00000.il b/tests/functional/single_cells/rtlil/test_cell_modfloor_00000.il
deleted file mode 100644
index 6cd00aeea5d..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_modfloor_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 5 input 1 \A
-  wire width 7 input 2 \B
-  wire width 4 output 3 \Y
-  cell $modfloor \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 5
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 7
-    parameter \Y_WIDTH 4
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_mul_00000.il b/tests/functional/single_cells/rtlil/test_cell_mul_00000.il
deleted file mode 100644
index c77aaffb87e..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_mul_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 6 input 1 \A
-  wire width 2 input 2 \B
-  wire width 5 output 3 \Y
-  cell $mul \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 5
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_mux_00000.il b/tests/functional/single_cells/rtlil/test_cell_mux_00000.il
deleted file mode 100644
index 3fc52ac7716..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_mux_00000.il
+++ /dev/null
@@ -1,15 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 4 input 1 \A
-  wire width 4 input 2 \B
-  wire input 3 \S
-  wire width 4 output 4 \Y
-  cell $mux \UUT
-    parameter \WIDTH 4
-    connect \A \A
-    connect \B \B
-    connect \S \S
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_ne_00000.il b/tests/functional/single_cells/rtlil/test_cell_ne_00000.il
deleted file mode 100644
index 47ba31397ed..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_ne_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 7 input 1 \A
-  wire width 5 input 2 \B
-  wire width 4 output 3 \Y
-  cell $ne \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 7
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 4
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_neg_00000.il b/tests/functional/single_cells/rtlil/test_cell_neg_00000.il
deleted file mode 100644
index ee4273508d1..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_neg_00000.il
+++ /dev/null
@@ -1,13 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 2 input 1 \A
-  wire width 5 output 2 \Y
-  cell $neg \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 5
-    connect \A \A
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_not_00000.il b/tests/functional/single_cells/rtlil/test_cell_not_00000.il
deleted file mode 100644
index 9281ded0dfa..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_not_00000.il
+++ /dev/null
@@ -1,13 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 7 input 1 \A
-  wire width 7 output 2 \Y
-  cell $not \UUT
-    parameter \A_SIGNED 1
-    parameter \A_WIDTH 7
-    parameter \Y_WIDTH 7
-    connect \A \A
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_or_00000.il b/tests/functional/single_cells/rtlil/test_cell_or_00000.il
deleted file mode 100644
index 100ea42cd38..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_or_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 7 input 1 \A
-  wire input 2 \B
-  wire width 2 output 3 \Y
-  cell $or \UUT
-    parameter \A_SIGNED 1
-    parameter \A_WIDTH 7
-    parameter \B_SIGNED 1
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 2
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_pos_00000.il b/tests/functional/single_cells/rtlil/test_cell_pos_00000.il
deleted file mode 100644
index 182f0acd38f..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_pos_00000.il
+++ /dev/null
@@ -1,13 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire input 1 \A
-  wire width 3 output 2 \Y
-  cell $pos \UUT
-    parameter \A_SIGNED 1
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 3
-    connect \A \A
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_pos_00001.il b/tests/functional/single_cells/rtlil/test_cell_pos_00001.il
deleted file mode 100644
index 96e9c895a18..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_pos_00001.il
+++ /dev/null
@@ -1,13 +0,0 @@
-# Generated by Yosys 0.40+7 (git sha1 d8b5b90e7, g++ 13.2.0 -Og -fPIC)
-autoidx 1
-module \gold
-  wire width 6 input 1 \A
-  wire width 6 output 2 \Y
-  cell $pos \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
-    parameter \Y_WIDTH 6
-    connect \A \A
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_reduce_and_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_and_00000.il
deleted file mode 100644
index 079ed33ade5..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_reduce_and_00000.il
+++ /dev/null
@@ -1,13 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 4 input 1 \A
-  wire width 5 output 2 \Y
-  cell $reduce_and \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 5
-    connect \A \A
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_reduce_bool_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_bool_00000.il
deleted file mode 100644
index a417179c818..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_reduce_bool_00000.il
+++ /dev/null
@@ -1,13 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire input 1 \A
-  wire width 2 output 2 \Y
-  cell $reduce_bool \UUT
-    parameter \A_SIGNED 1
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 2
-    connect \A \A
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_reduce_or_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_or_00000.il
deleted file mode 100644
index 881c6dfe3a1..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_reduce_or_00000.il
+++ /dev/null
@@ -1,13 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 2 input 1 \A
-  wire width 7 output 2 \Y
-  cell $reduce_or \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 7
-    connect \A \A
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_reduce_xnor_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_xnor_00000.il
deleted file mode 100644
index c06562729ea..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_reduce_xnor_00000.il
+++ /dev/null
@@ -1,13 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 4 input 1 \A
-  wire width 4 output 2 \Y
-  cell $reduce_xnor \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \A
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_reduce_xor_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_xor_00000.il
deleted file mode 100644
index 428d2ea87a2..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_reduce_xor_00000.il
+++ /dev/null
@@ -1,13 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 4 input 1 \A
-  wire output 2 \Y
-  cell $reduce_xor \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 1
-    connect \A \A
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_shift_00000.il b/tests/functional/single_cells/rtlil/test_cell_shift_00000.il
deleted file mode 100644
index f82a2a79df7..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_shift_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire input 1 \A
-  wire width 6 input 2 \B
-  wire width 4 output 3 \Y
-  cell $shift \UUT
-    parameter \A_SIGNED 1
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 1
-    parameter \B_WIDTH 6
-    parameter \Y_WIDTH 4
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_shiftx_00000.il b/tests/functional/single_cells/rtlil/test_cell_shiftx_00000.il
deleted file mode 100644
index b89ac5bef91..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_shiftx_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire input 1 \A
-  wire width 5 input 2 \B
-  wire width 3 output 3 \Y
-  cell $shiftx \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 3
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_shl_00000.il b/tests/functional/single_cells/rtlil/test_cell_shl_00000.il
deleted file mode 100644
index 1cfee2a52b5..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_shl_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 8 input 1 \A
-  wire width 2 input 2 \B
-  wire width 3 output 3 \Y
-  cell $shl \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 3
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_shr_00000.il b/tests/functional/single_cells/rtlil/test_cell_shr_00000.il
deleted file mode 100644
index 35dd379099c..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_shr_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 7 input 1 \A
-  wire width 6 input 2 \B
-  wire width 4 output 3 \Y
-  cell $shr \UUT
-    parameter \A_SIGNED 1
-    parameter \A_WIDTH 7
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 6
-    parameter \Y_WIDTH 4
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_sop_00000.il b/tests/functional/single_cells/rtlil/test_cell_sop_00000.il
deleted file mode 100644
index df0f8f20abe..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_sop_00000.il
+++ /dev/null
@@ -1,13 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 8 input 1 \A
-  wire output 2 \Y
-  cell $sop \UUT
-    parameter \DEPTH 8
-    parameter \TABLE 128'10010000100100000101101010001001101000101010010100010000010100000101010100000001001010010110101010101010101000100100011001000110
-    parameter \WIDTH 8
-    connect \A \A
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_sshl_00000.il b/tests/functional/single_cells/rtlil/test_cell_sshl_00000.il
deleted file mode 100644
index 798288754ce..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_sshl_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 5 input 1 \A
-  wire width 3 input 2 \B
-  wire width 6 output 3 \Y
-  cell $sshl \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 5
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 6
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_sshr_00000.il b/tests/functional/single_cells/rtlil/test_cell_sshr_00000.il
deleted file mode 100644
index 3f59a693f24..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_sshr_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 3 input 1 \A
-  wire width 2 input 2 \B
-  wire width 2 output 3 \Y
-  cell $sshr \UUT
-    parameter \A_SIGNED 1
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 2
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_sub_00000.il b/tests/functional/single_cells/rtlil/test_cell_sub_00000.il
deleted file mode 100644
index cb9ec2f7904..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_sub_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 6 input 1 \A
-  wire width 6 input 2 \B
-  wire width 6 output 3 \Y
-  cell $sub \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 6
-    parameter \Y_WIDTH 6
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_xnor_00000.il b/tests/functional/single_cells/rtlil/test_cell_xnor_00000.il
deleted file mode 100644
index 85bd7d239df..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_xnor_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 7 input 1 \A
-  wire width 8 input 2 \B
-  wire width 7 output 3 \Y
-  cell $xnor \UUT
-    parameter \A_SIGNED 1
-    parameter \A_WIDTH 7
-    parameter \B_SIGNED 1
-    parameter \B_WIDTH 8
-    parameter \Y_WIDTH 7
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/rtlil/test_cell_xor_00000.il b/tests/functional/single_cells/rtlil/test_cell_xor_00000.il
deleted file mode 100644
index 2359698b55b..00000000000
--- a/tests/functional/single_cells/rtlil/test_cell_xor_00000.il
+++ /dev/null
@@ -1,17 +0,0 @@
-# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
-autoidx 1
-module \gold
-  wire width 6 input 1 \A
-  wire width 2 input 2 \B
-  wire width 8 output 3 \Y
-  cell $xor \UUT
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 8
-    connect \A \A
-    connect \B \B
-    connect \Y \Y
-  end
-end
diff --git a/tests/functional/single_cells/run-test.sh b/tests/functional/single_cells/run-test.sh
deleted file mode 100755
index cc6bcf16086..00000000000
--- a/tests/functional/single_cells/run-test.sh
+++ /dev/null
@@ -1,172 +0,0 @@
-#!/bin/bash
-
-declare -A cxx_failing_files
-declare -A smt_failing_files
-declare -A cxx_successful_files
-declare -A smt_successful_files
-
-run_cxx_test() {
-    BASE_PATH="../../../"
-
-    local rtlil_file=$1
-
-    local base_name=$(basename "$rtlil_file" .v)
-    
-    if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; write_functional_cxx my_module_functional_cxx.cc"; then
-        echo "Yosys processed $rtlil_file successfully."
-        
-        if ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cc -I ${BASE_PATH}backends/functional/cxx_runtime/ -std=c++17 -o vcd_harness; then
-            echo "Compilation successful."
-            if ./vcd_harness ${base_name}_functional_cxx.vcd; then
-		
-		if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -r ${base_name}_functional_cxx.vcd -scope gold -vcd ${base_name}_yosys_sim.vcd -timescale 1us -sim-gold"; then
-		    echo "Yosys sim $rtlil_file successfully."
-		    cxx_successful_files["$rtlil_file"]="Success"
-		else
-		    ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys_sim.vcd -r ${base_name}_functional_cxx.vcd -scope gold -timescale 1us"
-		    echo "Yosys simulation of $rtlil_file failed. There is a discrepancy with functional cxx"
-		    cxx_failing_files["$rtlil_file"]="Yosys sim failure"
-		fi
-		
-            else
-		echo "Failed to generate VCD files for $rtlil_file."
-		cxx_failing_files["$rtlil_file"]="VCD generation failure"
-            fi
-	else
-	    echo "Failed to compile harness for $rtlil_file."
-	    cxx_failing_files["$rtlil_file"]="Compilation failure"
-	fi
-	else
-            echo "Yosys failed to process $rtlil_file."
-            cxx_failing_files["$rtlil_file"]="Yosys failure"
-	fi
-}
-
-run_smt_test() {
-    BASE_PATH="../../../"
-
-    local rtlil_file=$1
-
-    local base_name=$(basename "$rtlil_file" .il)
-
-    if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; write_functional_smt2 ${base_name}.smt2"; then
-        echo "Yosys processed $rtlil_file successfully."
-	# TODO: which SMT solver should be run?
-	if z3 "${base_name}.smt2"; then
-            echo "SMT file ${base_name}.smt2 is valid ."
-            if python3 vcd_harness_smt.py "${base_name}.smt2"; then
-		echo "Python script generated VCD file for $rtlil_file successfully."
-
-		if [ -f "${base_name}.smt2.vcd" ]; then
-                    echo "VCD file ${base_name}.vcd generated successfully by Python."
-
-                    if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys.vcd -r ${base_name}.smt2.vcd -scope gold -timescale 1us"; then
-			echo "Yosys simulation for $rtlil_file completed successfully."
-			smt_successful_files["$rtlil_file"]="Success"
-                    else
-			echo "Yosys simulation failed for $rtlil_file."
-			smt_failing_files["$rtlil_file"]="Yosys simulation failure"
-                    fi
-		else		    
-                    echo "Failed to generate VCD file (${base_name}.vcd) for $rtlil_file. "
-                    smt_failing_files["$rtlil_file"]="VCD generation failure"
-		fi
-            else
-		echo "Failed to run Python script for $rtlil_file."
-		smt_failing_files["$rtlil_file"]="Python script failure"
-	    fi
-	else
-	    echo "SMT file for $rtlil_file is invalid"
-	    smt_failing_files["$rtlil_file"]="Invalid SMT"
-	fi
-    else
-        echo "Yosys failed to process $rtlil_file."
-        smt_failing_files["$rtlil_file"]="Yosys failure"
-    fi
-}
-
-
-run_all_tests() {
-    declare -A cxx_failing_files
-    declare -A smt_failing_files
-    declare -A cxx_successful_files
-    declare -A smt_successful_files
-    return_code=0
-    for rtlil_file in rtlil/*.il; do
-        run_cxx_test "$rtlil_file"
-	run_smt_test "$rtlil_file"
-    done
-    
-    echo "C++ tests results:"
-    if [ ${#cxx_failing_files[@]} -eq 0 ]; then
-        echo "All files passed."
-	echo "The following files passed:"
-        for file in "${!cxx_successful_files[@]}"; do
-            echo "$file"
-        done
-    else
-        echo "The following files failed:"
-        for file in "${!cxx_failing_files[@]}"; do
-            echo "$file: ${cxx_failing_files[$file]}"
-        done
-	echo "The following files passed:"
-        for file in "${!cxx_successful_files[@]}"; do
-            echo "$file"
-        done
-	return_code=1
-    fi
-    
-    echo "SMT tests results:"
-    if [ ${#smt_failing_files[@]} -eq 0 ]; then
-        echo "All files passed."
-	echo "The following files passed:"
-        for file in "${!smt_successful_files[@]}"; do
-            echo "$file"
-        done
-    else
-        echo "The following files failed:"
-        for file in "${!smt_failing_files[@]}"; do
-            echo "$file: ${smt_failing_files[$file]}"
-        done
-	echo "The following files passed:"
-        for file in "${!smt_successful_files[@]}"; do
-            echo "$file"
-        done
-	return_code=1
-    fi
-    return $return_code
-}
-
-run_smt_tests() {
-    declare -A smt_failing_files
-    declare -A smt_successful_files
-    return_code=0
-    for rtlil_file in rtlil/*.il; do
-        run_smt_test "$rtlil_file"
-    done
-
-    echo "SMT tests results:"
-    if [ ${#smt_failing_files[@]} -eq 0 ]; then
-        echo "All files passed."
-        echo "The following files passed:"
-        for file in "${!smt_successful_files[@]}"; do
-            echo "$file"
-        done
-    else
-        echo "The following files failed:"
-        for file in "${!smt_failing_files[@]}"; do
-            echo "$file: ${smt_failing_files[$file]}"
-        done
-        echo "The following files passed:"
-        for file in "${!smt_successful_files[@]}"; do
-            echo "$file"
-        done
-        return_code=1
-    fi
-    return $return_code
-}
-
-# If the script is being sourced, do not execute the tests
-if [[ "${BASH_SOURCE[0]}" == "${0}" ]]; then
-    run_all_tests
-fi
diff --git a/tests/functional/single_cells/vcd_harness_smt.py b/tests/functional/single_cells/vcd_harness_smt.py
deleted file mode 100644
index 95947748ffe..00000000000
--- a/tests/functional/single_cells/vcd_harness_smt.py
+++ /dev/null
@@ -1,214 +0,0 @@
-import sys
-import argparse
-import random
-import os
-
-# Parse command line arguments
-parser = argparse.ArgumentParser(description='Process SMT file for simulation.')
-parser.add_argument('smt_file', help='Path to the SMT file to simulate.')
-args = parser.parse_args()
-
-# Get the SMT file path from the command line argument
-smt_file_path = args.smt_file
-current_file_path = os.path.abspath(__file__)
-# Navigate to the directory you need relative to the current script
-# Assuming 'backends/smt2' is located three directories up from the current script
-desired_path = os.path.join(os.path.dirname(current_file_path), '..', '..', '..', 'backends', 'functional')
-
-# Normalize the path to resolve any '..'
-normalized_path = os.path.normpath(desired_path)
-
-# Append the directory to the Python path
-sys.path.append(normalized_path)
-
-# Import the module
-import smtio
-
-# Assuming the SmtIo class and other dependencies are available in your environment
-# You may need to include the entire script provided above in your script or have it available as a module
-
-# Step 1: Initialize an SmtIo object
-
-so = smtio.SmtOpts()
-so.solver = "z3"
-so.logic = "BV"
-so.debug_print = True
-# so.debug_file = "my_debug"
-smt_io = smtio.SmtIo(opts=so)
-# List to store the parsed results
-parsed_results = []
-
-# Load and execute the SMT file
-with open(smt_file_path, 'r') as smt_file:
-    for line in smt_file:
-        smt_io.write(line.strip())    
-smt_io.check_sat()
-# Read and parse the SMT file line by line
-with open(smt_file_path, 'r') as smt_file:
-    for line in smt_file:
-        # Strip leading/trailing whitespace
-        stripped_line = line.strip()
-        
-        # Ignore empty lines
-        if not stripped_line:
-            continue
-        # comments
-        if stripped_line.startswith(';'):
-            smt_io.info(stripped_line)
-        
-        # Parse the line using SmtIo's parse method
-        parsed_line = smt_io.parse(stripped_line)
-        
-        # Append the parsed result to the list
-        parsed_results.append(parsed_line)
-
-# Display the parsed results
-for result in parsed_results:
-    print(result)
-
-inputs = {}
-outputs = {}
-
-for lst in parsed_results:
-    if lst[0] == 'declare-datatypes':
-        for datatype_group in lst[2]:  # Navigate into the nested lists
-            datatype_name = datatype_group[0]
-            declarations = datatype_group[1][1:]  # Skip the first item (e.g., 'mk_inputs')
-            if datatype_name == 'Inputs':
-                for declaration in declarations:
-                    print("My declaration")
-                    print(declaration)
-                    input_name = declaration[0]
-                    bitvec_size = declaration[1][2]
-                    inputs[input_name] = int(bitvec_size)
-            elif datatype_name == 'Outputs':
-                for declaration in declarations:
-                    output_name = declaration[0]
-                    bitvec_size = declaration[1][2]
-                    outputs[output_name] = int(bitvec_size)
-    
-print(inputs)
-print(outputs)
-def set_step(inputs, step):
-    # This function assumes 'inputs' is a dictionary like {"A": 5, "B": 4}
-    # and 'input_values' is a dictionary like {"A": 5, "B": 13} specifying the concrete values for each input.
-    
-    # Construct input definitions
-    mk_inputs_parts = []
-    for input_name, width in inputs.items():
-        value = random.getrandbits(width)  # Generate a random number up to the maximum value for the bit size
-        binary_string = format(value, '0{}b'.format(width))  # Convert value to binary with leading zeros
-        mk_inputs_parts.append(f"#b{binary_string}")
-
-    # Join all parts for the mk_inputs constructor
-    mk_inputs_call = "mk_inputs " + " ".join(mk_inputs_parts)
-    define_inputs = f"(define-const test_inputs_step_n{step} Inputs ({mk_inputs_call}))\n"
-
-    # Create the output definition by calling the gold_step function
-    define_output = f"(define-const test_outputs_step_n{step} Outputs (gold_step test_inputs_step_n{step}))\n"
-    smt_commands = []
-    smt_commands.append(define_inputs)
-    smt_commands.append(define_output)
-    return smt_commands
-
-num_steps = 10
-smt_commands = []
-# Loop to generate SMT commands for each step
-for step in range(num_steps):
-    for step_command in set_step(inputs, step):
-        smt_commands.append(step_command)
-
-# Print or write the SMT commands to a file
-smt_file_content = ''.join(smt_commands)
-print(smt_file_content)  # Print to console
-
-# Optionally, write to a file
-with open('dynamic_commands.smt2', 'w') as smt_file:
-    smt_file.write(smt_file_content)
-
-# Execute the SMT commands
-for command in smt_commands:
-    print(command)
-    smt_io.write(command.strip())
-
-# Check for satisfiability
-# smt_io.setup()
-result = smt_io.check_sat()
-print(f'SAT result: {result}')
-if result != 'sat':
-    smt_io.p_close()
-    sys.exit(1)
-
-# Store signal values
-signals = {name: [] for name in list(inputs.keys()) + list(outputs.keys())}
-# Retrieve and print values for each state
-def hex_to_bin(value):
-    if value.startswith('x'):
-        hex_value = value[1:]  # Remove the 'x' prefix
-        bin_value = bin(int(hex_value, 16))[2:]  # Convert to binary and remove the '0b' prefix
-        return f'b{bin_value.zfill(len(hex_value) * 4)}'  # Add 'b' prefix and pad with zeros
-    return value
-
-combined_assertions = []
-for step in range(num_steps):
-    print(f"Values for step {step + 1}:")
-    for input_name, width in inputs.items():
-        value = smt_io.get(f'({input_name} test_inputs_step_n{step})')
-        value = hex_to_bin(value[1:])
-        print(f"  {input_name}: {value}")        
-        signals[input_name].append((step, value))
-    for output_name, width in outputs.items():
-        value = smt_io.get(f'({output_name} test_outputs_step_n{step})')
-        value = hex_to_bin(value[1:])
-        print(f"  {output_name}: {value}")
-        signals[output_name].append((step, value))
-        combined_assertions.append(f'(= ({output_name} test_outputs_step_n{step}) #{value})')
-# Create a single assertion covering all timesteps
-combined_condition = " ".join(combined_assertions)
-smt_io.write(f'(assert (not (and {combined_condition})))')
-
-# Check the combined assertion
-result = smt_io.check_sat(["unsat"])
-if result != 'unsat':
-    smt_io.p_close()
-    sys.exit(1)
-
-smt_io.p_close()
-
-def write_vcd(filename, signals, timescale='1 ns', date='today'):
-    with open(filename, 'w') as f:
-        # Write the header
-        f.write(f"$date\n    {date}\n$end\n")
-        f.write(f"$timescale {timescale} $end\n")
-        
-        # Declare signals
-        f.write("$scope module gold $end\n")
-        for signal_name, changes in signals.items():
-            signal_size = len(changes[0][1])
-            f.write(f"$var wire {signal_size - 1} {signal_name} {signal_name} $end\n")
-        f.write("$upscope $end\n")
-        f.write("$enddefinitions $end\n")
-        
-        # Collect all unique timestamps
-        timestamps = sorted(set(time for changes in signals.values() for time, _ in changes))
-        
-        # Write initial values
-        f.write("#0\n")
-        for signal_name, changes in signals.items():
-            for time, value in changes:
-                if time == 0:
-                    f.write(f"{value} {signal_name}\n")
-        
-        # Write value changes
-        for time in timestamps:
-            if time != 0:
-                f.write(f"#{time}\n")
-                for signal_name, changes in signals.items():
-                    for change_time, value in changes:
-                        if change_time == time:
-                            f.write(f"b{value} {signal_name}\n")
-
-
-# Write the VCD file
-write_vcd(smt_file_path + '.vcd', signals)
-sys.exit(0)
diff --git a/tests/functional/smt_vcd.py b/tests/functional/smt_vcd.py
new file mode 100644
index 00000000000..c38fe1bde7e
--- /dev/null
+++ b/tests/functional/smt_vcd.py
@@ -0,0 +1,180 @@
+import sys
+import argparse
+import random
+import os
+import smtio
+import re
+
+class SExprParserError(Exception):
+    pass
+
+class SExprParser:
+    def __init__(self):
+        self.peekbuf = None
+        self.stack = [[]]
+        self.atom_pattern = re.compile(r'[a-zA-Z0-9~!@$%^&*_\-+=<>.?/#]+')
+    def parse_line(self, line):
+        ptr = 0
+        while ptr < len(line):
+            if line[ptr].isspace():
+                ptr += 1
+            elif line[ptr] == ';':
+                break
+            elif line[ptr] == '(':
+                ptr += 1
+                self.stack.append([])
+            elif line[ptr] == ')':
+                ptr += 1
+                assert len(self.stack) > 1, "too many closed parentheses"
+                v = self.stack.pop()
+                self.stack[-1].append(v)
+            else:
+                match = self.atom_pattern.match(line, ptr)
+                if match is None:
+                    raise SExprParserError(f"invalid character '{line[ptr]}' in line '{line}'")
+                start, ptr = match.span()
+                self.stack[-1].append(line[start:ptr])
+    def finish(self):
+        assert len(self.stack) == 1, "too many open parentheses"
+    def retrieve(self):
+        rv, self.stack[0] = self.stack[0], []
+        return rv
+
+def simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io):
+    inputs = {}
+    outputs = {}
+
+    def handle_datatype(lst):
+        print(lst)
+        datatype_name = lst[1]
+        declarations = lst[2][0][1:]  # Skip the first item (e.g., 'mk_inputs')
+        if datatype_name.endswith("_Inputs"):
+            for declaration in declarations:
+                input_name = declaration[0]
+                bitvec_size = declaration[1][2]
+                assert input_name.startswith("gold_Inputs_")
+                inputs[input_name[len("gold_Inputs_"):]] = int(bitvec_size)
+        elif datatype_name.endswith("_Outputs"):
+            for declaration in declarations:
+                output_name = declaration[0]
+                bitvec_size = declaration[1][2]
+                assert output_name.startswith("gold_Outputs_")
+                outputs[output_name[len("gold_Outputs_"):]] = int(bitvec_size)
+
+    parser = SExprParser()
+    with open(smt_file_path, 'r') as smt_file:
+        for line in smt_file:
+            parser.parse_line(line)
+            for expr in parser.retrieve():
+                smt_io.write(smt_io.unparse(expr))
+                if expr[0] == "declare-datatype":
+                    handle_datatype(expr)
+                    
+    parser.finish()
+    assert smt_io.check_sat() == 'sat'
+
+    def set_step(inputs, step):
+        # This function assumes 'inputs' is a dictionary like {"A": 5, "B": 4}
+        # and 'input_values' is a dictionary like {"A": 5, "B": 13} specifying the concrete values for each input.
+        
+        mk_inputs_parts = []
+        for input_name, width in inputs.items():
+            value = random.getrandbits(width)  # Generate a random number up to the maximum value for the bit size
+            binary_string = format(value, '0{}b'.format(width))  # Convert value to binary with leading zeros
+            mk_inputs_parts.append(f"#b{binary_string}")
+
+        mk_inputs_call = "gold_Inputs " + " ".join(mk_inputs_parts)
+        define_inputs = f"(define-const test_inputs_step_n{step} gold_Inputs ({mk_inputs_call}))\n"
+
+        define_outputs = f"(define-const test_outputs_step_n{step} gold_Outputs (first (gold test_inputs_step_n{step} gold_State)))\n"
+        smt_commands = [define_inputs, define_outputs]
+        return smt_commands
+
+    num_steps = 1000
+    smt_commands = []
+    for step in range(num_steps):
+        for step_command in set_step(inputs, step):
+            smt_commands.append(step_command)
+
+    for command in smt_commands:
+        smt_io.write(command)
+
+    assert smt_io.check_sat() == 'sat'
+
+    # Store signal values
+    signals = {name: [] for name in list(inputs.keys()) + list(outputs.keys())}
+    # Retrieve and print values for each state
+    def hex_to_bin(value):
+        if value.startswith('x'):
+            hex_value = value[1:]  # Remove the 'x' prefix
+            bin_value = bin(int(hex_value, 16))[2:]  # Convert to binary and remove the '0b' prefix
+            return f'b{bin_value.zfill(len(hex_value) * 4)}'  # Add 'b' prefix and pad with zeros
+        return value
+
+    combined_assertions = []
+    for step in range(num_steps):
+        print(f"Values for step {step + 1}:")
+        for input_name, width in inputs.items():
+            value = smt_io.get(f'(gold_Inputs_{input_name} test_inputs_step_n{step})')
+            value = hex_to_bin(value[1:])
+            print(f"  {input_name}: {value}")        
+            signals[input_name].append((step, value))
+        for output_name, width in outputs.items():
+            value = smt_io.get(f'(gold_Outputs_{output_name} test_outputs_step_n{step})')
+            value = hex_to_bin(value[1:])
+            print(f"  {output_name}: {value}")
+            signals[output_name].append((step, value))
+            combined_assertions.append(f'(= (gold_Outputs_{output_name} test_outputs_step_n{step}) #{value})')
+    # Create a single assertion covering all timesteps
+    combined_condition = " ".join(combined_assertions)
+    smt_io.write(f'(assert (not (and {combined_condition})))')
+
+    # Check the combined assertion
+    assert smt_io.check_sat(["unsat"]) == "unsat"
+
+    def write_vcd(filename, signals, timescale='1 ns', date='today'):
+        with open(filename, 'w') as f:
+            # Write the header
+            f.write(f"$date\n    {date}\n$end\n")
+            f.write(f"$timescale {timescale} $end\n")
+            
+            # Declare signals
+            f.write("$scope module gold $end\n")
+            for signal_name, changes in signals.items():
+                signal_size = len(changes[0][1])
+                f.write(f"$var wire {signal_size - 1} {signal_name} {signal_name} $end\n")
+            f.write("$upscope $end\n")
+            f.write("$enddefinitions $end\n")
+            
+            # Collect all unique timestamps
+            timestamps = sorted(set(time for changes in signals.values() for time, _ in changes))
+            
+            # Write initial values
+            f.write("#0\n")
+            for signal_name, changes in signals.items():
+                for time, value in changes:
+                    if time == 0:
+                        f.write(f"{value} {signal_name}\n")
+            
+            # Write value changes
+            for time in timestamps:
+                if time != 0:
+                    f.write(f"#{time}\n")
+                    for signal_name, changes in signals.items():
+                        for change_time, value in changes:
+                            if change_time == time:
+                                f.write(f"{value} {signal_name}\n")
+
+
+    write_vcd(vcd_path, signals)
+
+def simulate_smt(smt_file_path, vcd_path):
+    so = smtio.SmtOpts()
+    so.solver = "z3"
+    so.logic = "BV"
+    so.debug_print = True
+    smt_io = smtio.SmtIo(opts=so)
+    try:
+        simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io)
+    finally:
+        smt_io.p_close()
\ No newline at end of file
diff --git a/backends/functional/smtio.py b/tests/functional/smtio.py
similarity index 100%
rename from backends/functional/smtio.py
rename to tests/functional/smtio.py
diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py
new file mode 100644
index 00000000000..9b4fab970f1
--- /dev/null
+++ b/tests/functional/test_functional.py
@@ -0,0 +1,63 @@
+import subprocess
+import pytest
+import sys
+import shlex
+from pathlib import Path
+
+base_path = Path(__file__).resolve().parent.parent.parent
+
+def quote(path):
+    return shlex.quote(str(path))
+
+def run(cmd, **kwargs):
+    print(' '.join([shlex.quote(str(x)) for x in cmd]))
+    status = subprocess.run(cmd, **kwargs)
+    assert status.returncode == 0, f"{cmd[0]} failed"
+
+def yosys(script):
+    run([base_path / 'yosys', '-Q', '-p', script])
+
+def compile_cpp(in_path, out_path, args):
+    run(['g++', '-g', '-std=c++17'] + args + [str(in_path), '-o', str(out_path)])
+
+def test_cxx(cell, parameters, tmp_path):
+    rtlil_file = tmp_path / 'rtlil.il'
+    vcdharness_cc_file = base_path / 'tests/functional/vcd_harness.cc'
+    cc_file = tmp_path / 'my_module_functional_cxx.cc'
+    vcdharness_exe_file = tmp_path / 'a.out'
+    vcd_functional_file = tmp_path / 'functional.vcd'
+    vcd_yosys_sim_file = tmp_path / 'yosys.vcd'
+
+    with open(rtlil_file, 'w') as f:
+        cell.write_rtlil_file(f, parameters)
+    yosys(f"read_rtlil {quote(rtlil_file)} ; write_functional_cxx {quote(cc_file)}")
+    compile_cpp(vcdharness_cc_file, vcdharness_exe_file, ['-I', tmp_path, '-I', str(base_path / 'backends/functional/cxx_runtime')])
+    run([str(vcdharness_exe_file.resolve()), str(vcd_functional_file)])
+    try:
+        yosys(f"read_rtlil {quote(rtlil_file)}; sim -r {quote(vcd_functional_file)} -scope gold -vcd {quote(vcd_yosys_sim_file)} -timescale 1us -sim-gold")
+    except:
+        subprocess.run([base_path / 'yosys', '-Q', '-p',
+            f'read_rtlil {quote(rtlil_file)}; sim -vcd {quote(vcd_yosys_sim_file)} -r {quote(vcd_functional_file)} -scope gold -timescale 1us'],
+            capture_output=True, check=False)
+        raise
+
+def test_smt(cell, parameters, tmp_path):
+    import smt_vcd
+
+    rtlil_file = tmp_path / 'rtlil.il'
+    smt_file = tmp_path / 'smtlib.smt'
+    vcd_functional_file = tmp_path / 'functional.vcd'
+    vcd_yosys_sim_file = tmp_path / 'yosys.vcd'
+
+    with open(rtlil_file, 'w') as f:
+        cell.write_rtlil_file(f, parameters)
+    yosys(f"read_rtlil {quote(rtlil_file)} ; write_functional_smt2 {quote(smt_file)}")
+    run(['z3', smt_file])
+    smt_vcd.simulate_smt(smt_file, vcd_functional_file)
+    try:
+        yosys(f"read_rtlil {quote(rtlil_file)}; sim -r {quote(vcd_functional_file)} -scope gold -vcd {quote(vcd_yosys_sim_file)} -timescale 1us -sim-gold")
+    except:
+        subprocess.run([base_path / 'yosys', '-Q', '-p',
+            f'read_rtlil {quote(rtlil_file)}; sim -vcd {quote(vcd_yosys_sim_file)} -r {quote(vcd_functional_file)} -scope gold -timescale 1us'],
+            capture_output=True, check=False)
+        raise
\ No newline at end of file
diff --git a/tests/functional/single_cells/vcd_harness.cc b/tests/functional/vcd_harness.cc
similarity index 98%
rename from tests/functional/single_cells/vcd_harness.cc
rename to tests/functional/vcd_harness.cc
index 9b3777c37fd..f99d2909ba0 100644
--- a/tests/functional/single_cells/vcd_harness.cc
+++ b/tests/functional/vcd_harness.cc
@@ -68,7 +68,7 @@ int main(int argc, char **argv)
 
   const std::string functional_vcd_filename = argv[1];
 
-  constexpr int steps = 10;
+  constexpr int steps = 1000;
   constexpr int number_timescale = 1;
   const std::string units_timescale = "us";
   gold::Inputs inputs;

From 6922633b0b1255975ceda7f3dd734946d85f08ea Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Tue, 16 Jul 2024 17:55:26 +0100
Subject: [PATCH 410/499] fix a few bugs in the functional backend and refactor
 the testing

---
 kernel/functionalir.cc              |  40 ++-
 tests/functional/conftest.py        |  26 +-
 tests/functional/rtlil_cells.py     | 393 +++++++++++++++-------------
 tests/functional/smt_vcd.py         |  55 +++-
 tests/functional/test_functional.py |  55 ++--
 tests/functional/vcd_harness.cc     |  69 +++--
 6 files changed, 367 insertions(+), 271 deletions(-)

diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc
index 6983facfb72..b8fa6b88e5f 100644
--- a/kernel/functionalir.cc
+++ b/kernel/functionalir.cc
@@ -226,26 +226,36 @@ class CellSimplifier {
 			T b = extend(inputs.at(ID(B)), b_width, width, is_signed);
 			if(is_signed) {
 				if(cellType == ID($div)) {
+					// divide absolute values, then flip the sign if input signs differ
+					// but extend the width first, to handle the case (most negative value) / (-1)
 					T abs_y = factory.unsigned_div(abs(a, width), abs(b, width), width);
 					T out_sign = factory.not_equal(sign(a, width), sign(b, width), 1);
-					return neg_if(extend(abs_y, width, y_width, true), y_width, out_sign);
+					return neg_if(extend(abs_y, width, y_width, false), y_width, out_sign);
 				} else if(cellType == ID($mod)) {
+					// similar to division but output sign == divisor sign
 					T abs_y = factory.unsigned_mod(abs(a, width), abs(b, width), width);
-					return neg_if(extend(abs_y, width, y_width, true), y_width, sign(a, width));
+					return neg_if(extend(abs_y, width, y_width, false), y_width, sign(a, width));
 				} else if(cellType == ID($divfloor)) {
+					// if b is negative, flip both signs so that b is positive
 					T b_sign = sign(b, width);
 					T a1 = neg_if(a, width, b_sign);
 					T b1 = neg_if(b, width, b_sign);
-					T a1_sign = sign(a1, width);
+					// if a is now negative, calculate ~((~a) / b) = -((-a - 1) / b + 1)
+					// which equals the negative of (-a) / b with rounding up rather than down
+					// note that to handle the case where a = most negative value properly,
+					// we have to calculate a1_sign from the original values rather than using sign(a1, width)
+					T a1_sign = factory.bitwise_and(factory.not_equal(sign(a, width), sign(b, width), 1), reduce_or(a, width), 1);
 					T a2 = factory.mux(a1, factory.bitwise_not(a1, width), a1_sign, width);
 					T y1 = factory.unsigned_div(a2, b1, width);
-					T y2 = factory.mux(y1, factory.bitwise_not(y1, width), a1_sign, width);
-					return extend(y2, width, y_width, true);
+					T y2 = extend(y1, width, y_width, false);
+					return factory.mux(y2, factory.bitwise_not(y2, y_width), a1_sign, y_width);
 				} else if(cellType == ID($modfloor)) {
+					// calculate |a| % |b| and then subtract from |b| if input signs differ and the remainder is non-zero
 					T abs_b = abs(b, width);
 					T abs_y = factory.unsigned_mod(abs(a, width), abs_b, width);
 					T flip_y = factory.bitwise_and(factory.bitwise_xor(sign(a, width), sign(b, width), 1), factory.reduce_or(abs_y, width), 1);
 					T y_flipped = factory.mux(abs_y, factory.sub(abs_b, abs_y, width), flip_y, width);
+					// since y_flipped is strictly less than |b|, the top bit is always 0 and we can just sign extend the flipped result
 					T y = neg_if(y_flipped, width, sign(b, b_width));
 					return extend(y, width, y_width, true);
 				} else
@@ -261,22 +271,8 @@ class CellSimplifier {
 		} else if (cellType == ID($lut)) {
 			int width = parameters.at(ID(WIDTH)).as_int();
 			Const lut_table = parameters.at(ID(LUT));
-			T a = inputs.at(ID(A));
-			// Output initialization
-			T y = factory.constant(Const(0, 1));
-			// Iterate over each possible input combination
-			for (int i = 0; i < (1 << width); ++i) {
-				// Create a constant representing the value of i
-				T i_val = factory.constant(Const(i, width));
-				// Check if the input matches this value
-				T match = factory.equal(a, i_val, width);
-				// Get the corresponding LUT value
-				bool lut_val = lut_table.bits[i] == State::S1;
-				T lut_output = factory.constant(Const(lut_val, 1));
-				// Use a multiplexer to select the correct output based on the match
-				y = factory.mux(y, lut_output, match, 1);
-			}
-			return y;
+			lut_table.extu(1 << width);
+			return handle_bmux(factory.constant(lut_table), inputs.at(ID(A)), 1 << width, 0, 1, width, width);
 		} else if (cellType == ID($bwmux)) {
 			int width = parameters.at(ID(WIDTH)).as_int();
 			T a = inputs.at(ID(A));
@@ -526,7 +522,7 @@ void FunctionalIR::topological_sort() {
     if(scc) log_error("combinational loops, aborting\n");
 }
 
-IdString merge_name(IdString a, IdString b) {
+static IdString merge_name(IdString a, IdString b) {
 	if(a[0] == '$' && b[0] == '\\')
 		return b;
 	else
diff --git a/tests/functional/conftest.py b/tests/functional/conftest.py
index 3a66abaab21..12db7f1d09b 100644
--- a/tests/functional/conftest.py
+++ b/tests/functional/conftest.py
@@ -1,14 +1,30 @@
 import pytest
 from rtlil_cells import generate_test_cases
+import random
+
+random_seed = random.getrandbits(32)
 
 def pytest_addoption(parser):
-    parser.addoption(
-        "--per-cell", type=int, default=None, help="run only N tests per cell"
-    )
+    parser.addoption("--per-cell", type=int, default=None, help="run only N tests per cell")
+    parser.addoption("--steps", type=int, default=1000, help="run each test for N steps")
+    parser.addoption("--seed", type=int, default=random_seed, help="seed for random number generation, use random seed if unspecified")
+
+def pytest_collection_finish(session):
+    print('random seed: {}'.format(session.config.getoption("seed")))
+
+@pytest.fixture
+def num_steps(request):
+    return request.config.getoption("steps")
+
+@pytest.fixture
+def rnd(request):
+    seed1 = request.config.getoption("seed")
+    return lambda seed2: random.Random('{}-{}'.format(seed1, seed2))
 
 def pytest_generate_tests(metafunc):
     if "cell" in metafunc.fixturenames:
-        print(dir(metafunc.config))
         per_cell = metafunc.config.getoption("per_cell", default=None)
-        names, cases = generate_test_cases(per_cell)
+        seed1 = metafunc.config.getoption("seed")
+        rnd = lambda seed2: random.Random('{}-{}'.format(seed1, seed2))
+        names, cases = generate_test_cases(per_cell, rnd)
         metafunc.parametrize("cell,parameters", cases, ids=names)
\ No newline at end of file
diff --git a/tests/functional/rtlil_cells.py b/tests/functional/rtlil_cells.py
index e96baa18ee8..b4c0ad1c1ef 100644
--- a/tests/functional/rtlil_cells.py
+++ b/tests/functional/rtlil_cells.py
@@ -1,30 +1,6 @@
 from itertools import chain
 import random
 
-widths = [
-    (16, 32, 48, True),
-    (16, 32, 48, False),
-    (32, 16, 48, True),
-    (32, 16, 48, False),
-    (32, 32, 16, True),
-    (32, 32, 16, False)
-]
-
-shift_widths = [
-    (32, 6, 32, True, False),
-    (32, 6, 32, False, False),
-    (32, 6, 64, True, False),
-    (32, 6, 64, False, False),
-    (32, 32, 16, True, False),
-    (32, 32, 16, False, False),
-    (32, 6, 32, True, True),
-    (32, 6, 32, False, True),
-    (32, 6, 64, True, True),
-    (32, 6, 64, False, True),
-    (32, 32, 16, True, True),
-    (32, 32, 16, False, True),
-]
-
 def write_rtlil_cell(f, cell_type, inputs, outputs, parameters):
     f.write('autoidx 1\n')
     f.write('module \\gold\n')
@@ -37,207 +13,260 @@ def write_rtlil_cell(f, cell_type, inputs, outputs, parameters):
         idx += 1
     f.write(f'\tcell ${cell_type} \\UUT\n')
     for (name, value) in parameters.items():
-        f.write(f'\t\tparameter \\{name} {value}\n')
+        if value >= 2**32:
+            f.write(f'\t\tparameter \\{name} {value.bit_length()}\'{value:b}\n')
+        else:
+            f.write(f'\t\tparameter \\{name} {value}\n')
     for name in chain(inputs.keys(), outputs.keys()):
         f.write(f'\t\tconnect \\{name} \\{name}\n')
     f.write(f'\tend\nend\n')
 
 class BaseCell:
-    def __init__(self, name):
+    def __init__(self, name, parameters, inputs, outputs, test_values):
         self.name = name
+        self.parameters = parameters
+        self.inputs = inputs
+        self.outputs = outputs
+        self.test_values = test_values
+    def get_port_width(self, port, parameters):
+        def parse_specifier(spec):
+            if isinstance(spec, int):
+                return spec
+            if isinstance(spec, str):
+                return parameters[spec]
+            if callable(spec):
+                return spec(parameters)
+            assert False, "expected int, str or lambda"
+        if port in self.inputs:
+            return parse_specifier(self.inputs[port])
+        elif port in self.outputs:
+            return parse_specifier(self.outputs[port])
+        else:
+            assert False, "expected input or output"
+    def generate_tests(self, rnd):
+        def print_parameter(v):
+            if isinstance(v, bool):
+                return "S" if v else "U"
+            else:
+                return str(v)
+        for values in self.test_values:
+            if isinstance(values, int):
+                values = [values]
+            name = '-'.join([print_parameter(v) for v in values])
+            parameters = {parameter: int(values[i]) for i, parameter in enumerate(self.parameters)}
+            if self.is_test_valid(values):
+                yield (name, parameters)
+    def write_rtlil_file(self, path, parameters):
+        inputs = {port: self.get_port_width(port, parameters) for port in self.inputs}
+        outputs = {port: self.get_port_width(port, parameters) for port in self.outputs}
+        with open(path, 'w') as f:
+            write_rtlil_cell(f, self.name, inputs, outputs, parameters)
+    def is_test_valid(self, values):
+        return True
 
 class UnaryCell(BaseCell):
-    def __init__(self, name):
-        super().__init__(name)
-    def generate_tests(self):
-        for (a_width, _, y_width, signed) in widths:
-            yield (f'{a_width}-{y_width}-{'S' if signed else 'U'}',
-                   {'A_WIDTH' : a_width,
-                    'A_SIGNED' : int(signed),
-                    'Y_WIDTH' : y_width})
-    def write_rtlil_file(self, f, parameters):
-        write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters)
+    def __init__(self, name, values):
+        super().__init__(name, ['A_WIDTH', 'Y_WIDTH', 'A_SIGNED'], {'A': 'A_WIDTH'}, {'Y': 'Y_WIDTH'}, values)
 
 class BinaryCell(BaseCell):
-    def __init__(self, name):
-        super().__init__(name)
-    def generate_tests(self):
-        for (a_width, b_width, y_width, signed) in widths:
-            yield (f'{a_width}-{b_width}-{y_width}-{'S' if signed else 'U'}',
-                   {'A_WIDTH' : a_width,
-                    'A_SIGNED' : int(signed),
-                    'B_WIDTH' : b_width,
-                    'B_SIGNED' : int(signed),
-                    'Y_WIDTH' : y_width})
-    def write_rtlil_file(self, f, parameters):
-        write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH'], 'B': parameters['B_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters)
+    def __init__(self, name, values):
+        super().__init__(name, ['A_WIDTH', 'B_WIDTH', 'Y_WIDTH', 'A_SIGNED', 'B_SIGNED'], {'A': 'A_WIDTH', 'B': 'B_WIDTH'}, {'Y': 'Y_WIDTH'}, values)
 
 class ShiftCell(BaseCell):
-    def __init__(self, name):
-        super().__init__(name)
-    def generate_tests(self):
-        for (a_width, b_width, y_width, a_signed, b_signed) in shift_widths:
-            if not self.name in ('shift', 'shiftx') and b_signed: continue
-            if self.name == 'shiftx' and a_signed: continue
-            yield (f'{a_width}-{b_width}-{y_width}-{'S' if a_signed else 'U'}{'S' if b_signed else 'U'}',
-                   {'A_WIDTH' : a_width,
-                    'A_SIGNED' : int(a_signed),
-                    'B_WIDTH' : b_width,
-                    'B_SIGNED' : int(b_signed),
-                    'Y_WIDTH' : y_width})
-    def write_rtlil_file(self, f, parameters):
-        write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH'], 'B': parameters['B_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters)
+    def __init__(self, name, values):
+        super().__init__(name,  ['A_WIDTH', 'B_WIDTH', 'Y_WIDTH', 'A_SIGNED', 'B_SIGNED'], {'A': 'A_WIDTH', 'B': 'B_WIDTH'}, {'Y': 'Y_WIDTH'}, values)
+    def is_test_valid(self, values):
+        (a_width, b_width, y_width, a_signed, b_signed) = values
+        if not self.name in ('shift', 'shiftx') and b_signed: return False
+        if self.name == 'shiftx' and a_signed: return False
+        return True
 
 class MuxCell(BaseCell):
-    def __init__(self, name):
-        super().__init__(name)
-    def generate_tests(self):
-        for width in [10, 20, 40]:
-            yield (f'{width}', {'WIDTH' : width})
-    def write_rtlil_file(self, f, parameters):
-        write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'], 'B': parameters['WIDTH'], 'S': 1}, {'Y': parameters['WIDTH']}, parameters)
+    def __init__(self, name, values):
+        super().__init__(name, ['WIDTH'], {'A': 'WIDTH', 'B': 'WIDTH', 'S': 1}, {'Y': 'WIDTH'}, values)
 
 class BWCell(BaseCell):
-    def __init__(self, name):
-        super().__init__(name)
-    def generate_tests(self):
-        for width in [10, 20, 40]:
-            yield (f'{width}', {'WIDTH' : width})
-    def write_rtlil_file(self, f, parameters):
-        inputs = {'A': parameters['WIDTH'], 'B': parameters['WIDTH']}
-        if self.name == "bwmux": inputs['S'] = parameters['WIDTH']
-        write_rtlil_cell(f, self.name, inputs, {'Y': parameters['WIDTH']}, parameters)
+    def __init__(self, name, values):
+        inputs = {'A': 'WIDTH', 'B': 'WIDTH'}
+        if name == "bwmux": inputs['S'] = 'WIDTH'
+        super().__init__(name, ['WIDTH'], inputs, {'Y': 'WIDTH'}, values)
 
 class PMuxCell(BaseCell):
-    def __init__(self, name):
-        super().__init__(name)
-    def generate_tests(self):
-        for (width, s_width) in [(10, 1), (10, 4), (20, 4)]:
-            yield (f'{width}-{s_width}',
-                   {'WIDTH' : width,
-                    'S_WIDTH' : s_width})
-    def write_rtlil_file(self, f, parameters):
-        s_width = parameters['S_WIDTH']
-        b_width = parameters['WIDTH'] * s_width
-        write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'], 'B': b_width, 'S': s_width}, {'Y': parameters['WIDTH']}, parameters)
+    def __init__(self, name, values):
+        b_width = lambda par: par['WIDTH'] * par['S_WIDTH']
+        super().__init__(name, ['WIDTH', 'S_WIDTH'], {'A': 'WIDTH', 'B': b_width, 'S': 'S_WIDTH'}, {'Y': 'WIDTH'}, values)
 
 class BMuxCell(BaseCell):
-    def __init__(self, name):
-        super().__init__(name)
-    def generate_tests(self):
-        for (width, s_width) in [(10, 1), (10, 2), (10, 4)]:
-            yield (f'{width}-{s_width}', {'WIDTH' : width, 'S_WIDTH' : s_width})
-    def write_rtlil_file(self, f, parameters):
-        write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'] << parameters['S_WIDTH'], 'S': parameters['S_WIDTH']}, {'Y': parameters['WIDTH']}, parameters)
+    def __init__(self, name, values):
+        a_width = lambda par: par['WIDTH'] << par['S_WIDTH']
+        super().__init__(name, ['WIDTH', 'S_WIDTH'], {'A': a_width, 'S': 'S_WIDTH'}, {'Y': 'WIDTH'}, values)
 
 class DemuxCell(BaseCell):
-    def __init__(self, name):
-        super().__init__(name)
-    def generate_tests(self):
-        for (width, s_width) in [(10, 1), (32, 2), (16, 4)]:
-            yield (f'{width}-{s_width}', {'WIDTH' : width, 'S_WIDTH' : s_width})
-    def write_rtlil_file(self, f, parameters):
-        write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'], 'S': parameters['S_WIDTH']}, {'Y': parameters['WIDTH'] << parameters['S_WIDTH']}, parameters)
-
-def seeded_randint(seed, a, b):
-    r = random.getstate()
-    random.seed(seed)
-    n = random.randint(a, b)
-    random.setstate(r)
-    return n
+    def __init__(self, name, values):
+        y_width = lambda par: par['WIDTH'] << par['S_WIDTH']
+        super().__init__(name, ['WIDTH', 'S_WIDTH'], {'A': 'WIDTH', 'S': 'S_WIDTH'}, {'Y': y_width}, values)
 
 class LUTCell(BaseCell):
-    def __init__(self, name):
-        super().__init__(name)
-    def generate_tests(self):
-        for width in [4, 6, 8]:
-            lut = seeded_randint(width, 0, 2**width - 1)
+    def __init__(self, name, values):
+        super().__init__(name, ['WIDTH', 'LUT'], {'A': 'WIDTH'}, {'Y': 1}, values)
+    def generate_tests(self, rnd):
+        for width in self.test_values:
+            lut = rnd(f'lut-{width}').getrandbits(2**width)
             yield (f'{width}', {'WIDTH' : width, 'LUT' : lut})
-    def write_rtlil_file(self, f, parameters):
-        write_rtlil_cell(f, self.name, {'A': parameters['WIDTH']}, {'Y': 1}, parameters)
 
 class ConcatCell(BaseCell):
-    def __init__(self, name):
-        super().__init__(name)
-    def generate_tests(self):
-        for (a_width, b_width) in [(16, 16), (8, 14), (20, 10)]:
-            yield (f'{a_width}-{b_width}', {'A_WIDTH' : a_width, 'B_WIDTH' : b_width})
-    def write_rtlil_file(self, f, parameters):
-        write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH'], 'B' : parameters['B_WIDTH']}, {'Y': parameters['A_WIDTH'] + parameters['B_WIDTH']}, parameters)
+    def __init__(self, name, values):
+        y_width = lambda par: par['A_WIDTH'] + par['B_WIDTH']
+        super().__init__(name, ['A_WIDTH', 'B_WIDTH'], {'A': 'A_WIDTH', 'B': 'B_WIDTH'}, {'Y': y_width}, values)
 
 class SliceCell(BaseCell):
-    def __init__(self, name):
-        super().__init__(name)
-    def generate_tests(self):
-        for (a_width, offset, y_width) in [(32, 10, 15), (8, 0, 4), (10, 0, 10)]:
-            yield (f'{a_width}-{offset}-{y_width}', {'A_WIDTH' : a_width, 'OFFSET' : offset, 'Y_WIDTH': y_width})
-    def write_rtlil_file(self, f, parameters):
-        write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters)
+    def __init__(self, name, values):
+        super().__init__(name, ['A_WIDTH', 'OFFSET', 'Y_WIDTH'], {'A': 'A_WIDTH'}, {'Y': 'Y_WIDTH'}, values)
 
 class FailCell(BaseCell):
     def __init__(self, name):
-        super().__init__(name)
-    def generate_tests(self):
+        super().__init__(name, [], {}, {})
+    def generate_tests(self, rnd):
         yield ('', {})
-    def write_rtlil_file(self, f, parameters):
+    def write_rtlil_file(self, path, parameters):
         raise Exception(f'\'{self.name}\' cell unimplemented in test generator')
 
+class FFCell(BaseCell):
+    def __init__(self, name, values):
+        super().__init__(name, ['WIDTH'], ['D'], ['Q'], values)
+    def write_rtlil_file(self, path, parameters):
+        from test_functional import yosys_synth
+        verilog_file = path.parent / 'verilog.v'
+        with open(verilog_file, 'w') as f:
+            f.write("""
+module gold(
+    input wire clk,
+    input wire [{0}:0] D,
+    output reg [{0}:0] Q
+);
+    always @(posedge clk)
+        Q <= D;
+endmodule""".format(parameters['WIDTH'] - 1))
+        yosys_synth(verilog_file, path)
+
+class MemCell(BaseCell):
+    def __init__(self, name, values):
+        super().__init__(name, ['DATA_WIDTH', 'ADDR_WIDTH'], {'WA': 'ADDR_WIDTH', 'RA': 'ADDR_WIDTH', 'WD': 'DATA_WIDTH'}, {'RD': 'DATA_WIDTH'}, values)
+    def write_rtlil_file(self, path, parameters):
+        from test_functional import yosys_synth
+        verilog_file = path.parent / 'verilog.v'
+        with open(verilog_file, 'w') as f:
+            f.write("""
+module gold(
+    input wire clk,
+    input wire [{1}:0] WA,
+    input wire [{0}:0] WD,
+    output reg [{0}:0] RD
+);
+    reg [{0}:0] mem[0:{1}];
+    always @(*)
+        RD = mem[RA];
+    always @(posedge clk)
+        mem[WA] <= WD;
+endmodule""".format(parameters['DATA_WIDTH'] - 1, parameters['ADDR_WIDTH'] - 1))
+        yosys_synth(verilog_file, path)
+
+binary_widths = [
+    # try to cover extending A operand, extending B operand, extending/truncating result
+    (16, 32, 48, True, True),
+    (16, 32, 48, False, False),
+    (32, 16, 48, True, True),
+    (32, 16, 48, False, False),
+    (32, 32, 16, True, True),
+    (32, 32, 16, False, False),
+    # have at least one test that checks small inputs, which will exercise the cornercases more
+    (4, 4, 8, True, True),
+    (4, 4, 8, False, False)
+]
+
+unary_widths = [
+    (6, 12, True),
+    (6, 12, False),
+    (32, 16, True),
+    (32, 16, False)
+]
+
+# note that meaningless combinations of signednesses are eliminated,
+# like e.g. most shift operations don't take signed shift amounts
+shift_widths = [
+    # one set of tests that definitely checks all possible shift amounts
+    # with a bigger result width to make sure it's not truncated
+    (32, 6, 64, True, False),
+    (32, 6, 64, False, False),
+    (32, 6, 64, True, True),
+    (32, 6, 64, False, True),
+    # one set that checks very oversized shifts
+    (32, 32, 64, True, False),
+    (32, 32, 64, False, False),
+    (32, 32, 64, True, True),
+    (32, 32, 64, False, True),
+    # at least one test where the result is going to be truncated
+    (32, 6, 16, False, False)
+]
+
 rtlil_cells = [
-    UnaryCell("not"),
-    UnaryCell("pos"),
-    UnaryCell("neg"),
-    BinaryCell("and"),
-    BinaryCell("or"),
-    BinaryCell("xor"),
-    BinaryCell("xnor"),
-    UnaryCell("reduce_and"),
-    UnaryCell("reduce_or"),
-    UnaryCell("reduce_xor"),
-    UnaryCell("reduce_xnor"),
-    UnaryCell("reduce_bool"),
-    ShiftCell("shl"),
-    ShiftCell("shr"),
-    ShiftCell("sshl"),
-    ShiftCell("sshr"),
-    ShiftCell("shift"),
-    ShiftCell("shiftx"),
+    UnaryCell("not", unary_widths),
+    UnaryCell("pos", unary_widths),
+    UnaryCell("neg", unary_widths),
+    BinaryCell("and", binary_widths),
+    BinaryCell("or", binary_widths),
+    BinaryCell("xor", binary_widths),
+    BinaryCell("xnor", binary_widths),
+    UnaryCell("reduce_and", unary_widths),
+    UnaryCell("reduce_or", unary_widths),
+    UnaryCell("reduce_xor", unary_widths),
+    UnaryCell("reduce_xnor", unary_widths),
+    UnaryCell("reduce_bool", unary_widths),
+    ShiftCell("shl", shift_widths),
+    ShiftCell("shr", shift_widths),
+    ShiftCell("sshl", shift_widths),
+    ShiftCell("sshr", shift_widths),
+    ShiftCell("shift", shift_widths),
+    ShiftCell("shiftx", shift_widths),
 #    ("fa", ["A", "B", "C", "X", "Y"]),
 #    ("lcu", ["P", "G", "CI", "CO"]),
 #    ("alu", ["A", "B", "CI", "BI", "X", "Y", "CO"]),
-    BinaryCell("lt"),
-    BinaryCell("le"),
-    BinaryCell("eq"),
-    BinaryCell("ne"),
-    BinaryCell("eqx"),
-    BinaryCell("nex"),
-    BinaryCell("ge"),
-    BinaryCell("gt"),
-    BinaryCell("add"),
-    BinaryCell("sub"),
-    BinaryCell("mul"),
+    BinaryCell("lt", binary_widths),
+    BinaryCell("le", binary_widths),
+    BinaryCell("eq", binary_widths),
+    BinaryCell("ne", binary_widths),
+    BinaryCell("eqx", binary_widths),
+    BinaryCell("nex", binary_widths),
+    BinaryCell("ge", binary_widths),
+    BinaryCell("gt", binary_widths),
+    BinaryCell("add", binary_widths),
+    BinaryCell("sub", binary_widths),
+    BinaryCell("mul", binary_widths),
 #    BinaryCell("macc"),
-    BinaryCell("div"),
-    BinaryCell("mod"),
-    BinaryCell("divfloor"),
-    BinaryCell("modfloor"),
-    BinaryCell("pow"),
-    UnaryCell("logic_not"),
-    BinaryCell("logic_and"),
-    BinaryCell("logic_or"),
-    SliceCell("slice"),
-    ConcatCell("concat"),
-    MuxCell("mux"),
-    BMuxCell("bmux"),
-    PMuxCell("pmux"),
-    DemuxCell("demux"),
-    LUTCell("lut"),
+    BinaryCell("div", binary_widths),
+    BinaryCell("mod", binary_widths),
+    BinaryCell("divfloor", binary_widths),
+    BinaryCell("modfloor", binary_widths),
+    BinaryCell("pow", binary_widths),
+    UnaryCell("logic_not", unary_widths),
+    BinaryCell("logic_and", binary_widths),
+    BinaryCell("logic_or", binary_widths),
+    SliceCell("slice", [(32, 10, 15), (8, 0, 4), (10, 0, 10)]),
+    ConcatCell("concat", [(16, 16), (8, 14), (20, 10)]),
+    MuxCell("mux", [10, 16, 40]),
+    BMuxCell("bmux", [(10, 1), (10, 2), (10, 4)]),
+    PMuxCell("pmux", [(10, 1), (10, 4), (20, 4)]),
+    DemuxCell("demux", [(10, 1), (32, 2), (16, 4)]),
+    LUTCell("lut", [4, 6, 8]),
 #    ("sop", ["A", "Y"]),
 #    ("tribuf", ["A", "EN", "Y"]),
 #    ("specify2", ["EN", "SRC", "DST"]),
 #    ("specify3", ["EN", "SRC", "DST", "DAT"]),
 #    ("specrule", ["EN_SRC", "EN_DST", "SRC", "DST"]),
-    BWCell("bweqx"),
-    BWCell("bwmux"),
+    BWCell("bweqx", [10, 16, 40]),
+    BWCell("bwmux", [10, 16, 40]),
+    FFCell("ff", [10, 20, 40]),
+    MemCell("mem", [(32, 4)])
 #    ("assert", ["A", "EN"]),
 #    ("assume", ["A", "EN"]),
 #    ("live", ["A", "EN"]),
@@ -260,12 +289,12 @@ def write_rtlil_file(self, f, parameters):
 #    ("scopeinfo", []),
 ]
 
-def generate_test_cases(per_cell):
+def generate_test_cases(per_cell, rnd):
     tests = []
     names = []
     for cell in rtlil_cells:
         seen_names = set()
-        for (name, parameters) in cell.generate_tests():
+        for (name, parameters) in cell.generate_tests(rnd):
             if not name in seen_names:
                 seen_names.add(name)
                 tests.append((cell, parameters))
diff --git a/tests/functional/smt_vcd.py b/tests/functional/smt_vcd.py
index c38fe1bde7e..37d2a209f71 100644
--- a/tests/functional/smt_vcd.py
+++ b/tests/functional/smt_vcd.py
@@ -1,6 +1,5 @@
 import sys
 import argparse
-import random
 import os
 import smtio
 import re
@@ -40,9 +39,10 @@ def retrieve(self):
         rv, self.stack[0] = self.stack[0], []
         return rv
 
-def simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io):
+def simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io, num_steps, rnd):
     inputs = {}
     outputs = {}
+    states = {}
 
     def handle_datatype(lst):
         print(lst)
@@ -60,6 +60,14 @@ def handle_datatype(lst):
                 bitvec_size = declaration[1][2]
                 assert output_name.startswith("gold_Outputs_")
                 outputs[output_name[len("gold_Outputs_"):]] = int(bitvec_size)
+        elif datatype_name.endswith("_State"):
+            for declaration in declarations:
+                state_name = declaration[0]
+                assert state_name.startswith("gold_State_")
+                if declaration[1][0] == "_":
+                    states[state_name[len("gold_State_"):]] = int(declaration[1][2])
+                else:
+                    states[state_name[len("gold_State_"):]] = (declaration[1][1][2], declaration[1][2][2])
 
     parser = SExprParser()
     with open(smt_file_path, 'r') as smt_file:
@@ -73,25 +81,44 @@ def handle_datatype(lst):
     parser.finish()
     assert smt_io.check_sat() == 'sat'
 
+    def initial_state(states):
+        mk_state_parts = []
+        rv = []
+        for name, width in states.items():
+            if isinstance(width, int):
+                binary_string = format(0, '0{}b'.format(width))
+                mk_state_parts.append(f"#b{binary_string}")
+            else:
+                binary_string = format(0, '0{}b'.format(width[1]))
+                rv.append(f"(declare-const test_state_initial_mem_{name} (Array (_ BitVec {width[0]}) (_ BitVec {width[1]})))")
+                rv.append(f"(assert (forall ((i (_ BitVec {width[0]}))) (= (select test_state_initial_mem_{name} i) #b{binary_string})))")
+                mk_state_parts.append(f"test_state_initial_mem_{name}")
+        if len(states) == 0:
+            mk_state_call = "gold_State"
+        else:
+            mk_state_call = "(gold_State {})".format(" ".join(mk_state_parts))
+        rv.append(f"(define-const test_state_step_n0 gold_State {mk_state_call})\n")
+        return rv
+
     def set_step(inputs, step):
         # This function assumes 'inputs' is a dictionary like {"A": 5, "B": 4}
         # and 'input_values' is a dictionary like {"A": 5, "B": 13} specifying the concrete values for each input.
         
         mk_inputs_parts = []
         for input_name, width in inputs.items():
-            value = random.getrandbits(width)  # Generate a random number up to the maximum value for the bit size
+            value = rnd.getrandbits(width)  # Generate a random number up to the maximum value for the bit size
             binary_string = format(value, '0{}b'.format(width))  # Convert value to binary with leading zeros
             mk_inputs_parts.append(f"#b{binary_string}")
 
         mk_inputs_call = "gold_Inputs " + " ".join(mk_inputs_parts)
-        define_inputs = f"(define-const test_inputs_step_n{step} gold_Inputs ({mk_inputs_call}))\n"
-
-        define_outputs = f"(define-const test_outputs_step_n{step} gold_Outputs (first (gold test_inputs_step_n{step} gold_State)))\n"
-        smt_commands = [define_inputs, define_outputs]
-        return smt_commands
-
-    num_steps = 1000
-    smt_commands = []
+        return [
+            f"(define-const test_inputs_step_n{step} gold_Inputs ({mk_inputs_call}))\n",
+            f"(define-const test_results_step_n{step} (Pair gold_Outputs gold_State) (gold test_inputs_step_n{step} test_state_step_n{step}))\n",
+            f"(define-const test_outputs_step_n{step} gold_Outputs (first test_results_step_n{step}))\n",
+            f"(define-const test_state_step_n{step+1} gold_State (second test_results_step_n{step}))\n",
+        ]
+
+    smt_commands = initial_state(states)
     for step in range(num_steps):
         for step_command in set_step(inputs, step):
             smt_commands.append(step_command)
@@ -168,13 +195,13 @@ def write_vcd(filename, signals, timescale='1 ns', date='today'):
 
     write_vcd(vcd_path, signals)
 
-def simulate_smt(smt_file_path, vcd_path):
+def simulate_smt(smt_file_path, vcd_path, num_steps, rnd):
     so = smtio.SmtOpts()
     so.solver = "z3"
-    so.logic = "BV"
+    so.logic = "ABV"
     so.debug_print = True
     smt_io = smtio.SmtIo(opts=so)
     try:
-        simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io)
+        simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io, num_steps, rnd)
     finally:
         smt_io.p_close()
\ No newline at end of file
diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py
index 9b4fab970f1..86e515d90a9 100644
--- a/tests/functional/test_functional.py
+++ b/tests/functional/test_functional.py
@@ -6,11 +6,14 @@
 
 base_path = Path(__file__).resolve().parent.parent.parent
 
+# quote a string or pathlib path so that it can be used by bash or yosys
+# TODO: is this really appropriate for yosys?
 def quote(path):
     return shlex.quote(str(path))
 
+# run a shell command and require the return code to be 0
 def run(cmd, **kwargs):
-    print(' '.join([shlex.quote(str(x)) for x in cmd]))
+    print(' '.join([quote(x) for x in cmd]))
     status = subprocess.run(cmd, **kwargs)
     assert status.returncode == 0, f"{cmd[0]} failed"
 
@@ -20,7 +23,24 @@ def yosys(script):
 def compile_cpp(in_path, out_path, args):
     run(['g++', '-g', '-std=c++17'] + args + [str(in_path), '-o', str(out_path)])
 
-def test_cxx(cell, parameters, tmp_path):
+def yosys_synth(verilog_file, rtlil_file):
+    yosys(f"read_verilog {quote(verilog_file)} ; prep ; clk2fflogic ; write_rtlil {quote(rtlil_file)}")
+
+# simulate an rtlil file with yosys, comparing with a given vcd file, and writing out the yosys simulation results into a second vcd file
+def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file):
+    try:
+        yosys(f"read_rtlil {quote(rtlil_file)}; sim -r {quote(vcd_reference_file)} -scope gold -vcd {quote(vcd_out_file)} -timescale 1us -sim-gold")
+    except:
+        # if yosys sim fails it's probably because of a simulation mismatch
+        # since yosys sim aborts on simulation mismatch to generate vcd output
+        # we have to re-run with a different set of flags
+        # on this run we ignore output and return code, we just want a best-effort attempt to get a vcd
+        subprocess.run([base_path / 'yosys', '-Q', '-p',
+            f'read_rtlil {quote(rtlil_file)}; sim -vcd {quote(vcd_out_file)} -a -r {quote(vcd_reference_file)} -scope gold -timescale 1us'],
+            capture_output=True, check=False)
+        raise
+
+def test_cxx(cell, parameters, tmp_path, num_steps, rnd):
     rtlil_file = tmp_path / 'rtlil.il'
     vcdharness_cc_file = base_path / 'tests/functional/vcd_harness.cc'
     cc_file = tmp_path / 'my_module_functional_cxx.cc'
@@ -28,20 +48,14 @@ def test_cxx(cell, parameters, tmp_path):
     vcd_functional_file = tmp_path / 'functional.vcd'
     vcd_yosys_sim_file = tmp_path / 'yosys.vcd'
 
-    with open(rtlil_file, 'w') as f:
-        cell.write_rtlil_file(f, parameters)
+    cell.write_rtlil_file(rtlil_file, parameters)
     yosys(f"read_rtlil {quote(rtlil_file)} ; write_functional_cxx {quote(cc_file)}")
     compile_cpp(vcdharness_cc_file, vcdharness_exe_file, ['-I', tmp_path, '-I', str(base_path / 'backends/functional/cxx_runtime')])
-    run([str(vcdharness_exe_file.resolve()), str(vcd_functional_file)])
-    try:
-        yosys(f"read_rtlil {quote(rtlil_file)}; sim -r {quote(vcd_functional_file)} -scope gold -vcd {quote(vcd_yosys_sim_file)} -timescale 1us -sim-gold")
-    except:
-        subprocess.run([base_path / 'yosys', '-Q', '-p',
-            f'read_rtlil {quote(rtlil_file)}; sim -vcd {quote(vcd_yosys_sim_file)} -r {quote(vcd_functional_file)} -scope gold -timescale 1us'],
-            capture_output=True, check=False)
-        raise
+    seed = str(rnd(cell.name + "-cxx").getrandbits(32))
+    run([str(vcdharness_exe_file.resolve()), str(vcd_functional_file), str(num_steps), str(seed)])
+    yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file)
 
-def test_smt(cell, parameters, tmp_path):
+def test_smt(cell, parameters, tmp_path, num_steps, rnd):
     import smt_vcd
 
     rtlil_file = tmp_path / 'rtlil.il'
@@ -49,15 +63,8 @@ def test_smt(cell, parameters, tmp_path):
     vcd_functional_file = tmp_path / 'functional.vcd'
     vcd_yosys_sim_file = tmp_path / 'yosys.vcd'
 
-    with open(rtlil_file, 'w') as f:
-        cell.write_rtlil_file(f, parameters)
+    cell.write_rtlil_file(rtlil_file, parameters)
     yosys(f"read_rtlil {quote(rtlil_file)} ; write_functional_smt2 {quote(smt_file)}")
-    run(['z3', smt_file])
-    smt_vcd.simulate_smt(smt_file, vcd_functional_file)
-    try:
-        yosys(f"read_rtlil {quote(rtlil_file)}; sim -r {quote(vcd_functional_file)} -scope gold -vcd {quote(vcd_yosys_sim_file)} -timescale 1us -sim-gold")
-    except:
-        subprocess.run([base_path / 'yosys', '-Q', '-p',
-            f'read_rtlil {quote(rtlil_file)}; sim -vcd {quote(vcd_yosys_sim_file)} -r {quote(vcd_functional_file)} -scope gold -timescale 1us'],
-            capture_output=True, check=False)
-        raise
\ No newline at end of file
+    run(['z3', smt_file]) # check if output is valid smtlib before continuing
+    smt_vcd.simulate_smt(smt_file, vcd_functional_file, num_steps, rnd(cell.name + "-smt"))
+    yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file)
\ No newline at end of file
diff --git a/tests/functional/vcd_harness.cc b/tests/functional/vcd_harness.cc
index f99d2909ba0..f01adf21832 100644
--- a/tests/functional/vcd_harness.cc
+++ b/tests/functional/vcd_harness.cc
@@ -2,15 +2,46 @@
 #include <iostream>
 #include <fstream>
 #include <random>
+#include <ctype.h>
+#include <vector>
 
 #include "my_module_functional_cxx.cc"
 
+std::string vcd_name_mangle(std::string name) {
+  std::string ret = name;
+  bool escape = ret.empty() || !isalpha(ret[0]) && ret[0] != '_';
+  for(size_t i = 0; i < ret.size(); i++) {
+    if(isspace(ret[i])) ret[i] = '_';
+    if(!isalnum(ret[i]) && ret[i] != '_' && ret[i] != '$')
+      escape = true;
+  }
+  if(escape)
+    return "\\" + ret;
+  else
+    return ret;
+}
+std::unordered_map<std::string, std::string> codes; 
+
 struct DumpHeader {
   std::ofstream &ofs;
+  std::string code = "!";
   DumpHeader(std::ofstream &ofs) : ofs(ofs) {}
+  void increment_code() {
+    for(size_t i = 0; i < code.size(); i++)
+      if(code[i]++ == '~')
+        code[i] = '!';
+      else
+        return;
+    code.push_back('!');
+  }
   template <size_t n>
   void operator()(const char *name, Signal<n> value) {
-    ofs << "$var wire " << n << " " << name[0] << " " << name << " $end\n";
+    ofs << "$var wire " << n << " " << code << " " << vcd_name_mangle(name) << " $end\n";
+    codes[name] = code;
+    increment_code();
+  }
+  template <size_t n, size_t m>
+  void operator()(const char *name, Memory<n, m> value) {
   }
 };
 
@@ -22,14 +53,17 @@ struct Dump {
     // Bit
     if (n == 1) {
       ofs << (value[0] ? '1' : '0');
-      ofs << name[0] << "\n";
+      ofs << codes[name] << "\n";
       return;
     }
     // vector (multi-bit) signals
     ofs << "b";
     for (size_t i = n; i-- > 0;)
       ofs << (value[i] ? '1' : '0');
-    ofs << " " << name[0] << "\n";
+    ofs << " " << codes[name] << "\n";
+  }
+  template <size_t n, size_t m>
+  void operator()(const char *name, Memory<n, m> value) {
   }
 };
 
@@ -61,14 +95,15 @@ struct Randomize {
 
 int main(int argc, char **argv)
 {
-  if (argc != 2) {
-    std::cerr << "Usage: " << argv[0] << " <functional_vcd_filename>\n";
+  if (argc != 4) {
+    std::cerr << "Usage: " << argv[0] << " <functional_vcd_filename> <steps> <seed>\n";
     return 1;
   }
 
   const std::string functional_vcd_filename = argv[1];
+  const int steps = atoi(argv[2]);
+  const uint32_t seed = atoi(argv[3]);
 
-  constexpr int steps = 1000;
   constexpr int number_timescale = 1;
   const std::string units_timescale = "us";
   gold::Inputs inputs;
@@ -87,27 +122,12 @@ int main(int argc, char **argv)
     state.visit(d);
   }
   vcd_file << "$enddefinitions $end\n$dumpvars\n";
-  vcd_file << "#0\n";
-  // Set all signals to false
-  inputs.visit(Reset());
+  std::mt19937 gen(seed);
 
-  gold::eval(inputs, outputs, state, next_state);
-  {
-    Dump d(vcd_file);
-    inputs.visit(d);
-    outputs.visit(d);
-    state.visit(d);
-  }
-
-  // Initialize random number generator once
-  std::random_device rd;
-  std::mt19937 gen(rd());
+  inputs.visit(Reset());
 
   for (int step = 0; step < steps; ++step) {
-    // Functional backend cxx
-    vcd_file << "#" << (step + 1) << "\n";
-    inputs.visit(Randomize(gen));
-
+    vcd_file << "#" << step << "\n";
     gold::eval(inputs, outputs, state, next_state);
     {
       Dump d(vcd_file);
@@ -117,6 +137,7 @@ int main(int argc, char **argv)
     }
 
     state = next_state;
+    inputs.visit(Randomize(gen));
   }
 
   vcd_file.close();

From 55c2c1785332ce862528ae06c60e551f7e5316a5 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Wed, 17 Jul 2024 11:53:42 +0100
Subject: [PATCH 411/499] document functionalir.h and change visitors to derive
 from AbstractVisitor. remove extraneous widths arguments from visitors.

---
 backends/functional/cxx.cc    |  72 ++++----
 backends/functional/smtlib.cc |  72 ++++----
 kernel/functional.h           |   2 +-
 kernel/functionalir.cc        |  93 +++++++++-
 kernel/functionalir.h         | 331 +++++++++++++++++++++++++---------
 5 files changed, 400 insertions(+), 170 deletions(-)

diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index 4ab9d53a1d4..920ccf363bc 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -98,7 +98,7 @@ struct CxxStruct {
   }
 };
 
-template<class NodePrinter> struct CxxPrintVisitor {
+template<class NodePrinter> struct CxxPrintVisitor : public FunctionalIR::AbstractVisitor<void> {
 	using Node = FunctionalIR::Node;
 	CxxWriter &f;
 	NodePrinter np;
@@ -108,36 +108,36 @@ template<class NodePrinter> struct CxxPrintVisitor {
 	template<typename... Args> void print(const char *fmt, Args&&... args) {
 		f.print_with(np, fmt, std::forward<Args>(args)...);
 	}
-	void buf(Node, Node n) { print("{}", n); }
-	void slice(Node, Node a, int, int offset, int out_width) { print("{0}.slice<{2}>({1})", a, offset, out_width); }
-	void zero_extend(Node, Node a, int, int out_width) { print("{}.zero_extend<{}>()", a, out_width); }
-	void sign_extend(Node, Node a, int, int out_width) { print("{}.sign_extend<{}>()", a, out_width); }
-	void concat(Node, Node a, int, Node b, int) { print("{}.concat({})", a, b); }
-	void add(Node, Node a, Node b, int) { print("{} + {}", a, b); }
-	void sub(Node, Node a, Node b, int) { print("{} - {}", a, b); }
-	void mul(Node, Node a, Node b, int) { print("{} * {}", a, b); }
-	void unsigned_div(Node, Node a, Node b, int) { print("{} / {}", a, b); }
-	void unsigned_mod(Node, Node a, Node b, int) { print("{} % {}", a, b); }
-	void bitwise_and(Node, Node a, Node b, int) { print("{} & {}", a, b); }
-	void bitwise_or(Node, Node a, Node b, int) { print("{} | {}", a, b); }
-	void bitwise_xor(Node, Node a, Node b, int) { print("{} ^ {}", a, b); }
-	void bitwise_not(Node, Node a, int) { print("~{}", a); }
-	void unary_minus(Node, Node a, int) { print("-{}", a); }
-	void reduce_and(Node, Node a, int) { print("{}.all()", a); }
-	void reduce_or(Node, Node a, int) { print("{}.any()", a); }
-	void reduce_xor(Node, Node a, int) { print("{}.parity()", a); }
-	void equal(Node, Node a, Node b, int) { print("{} == {}", a, b); }
-	void not_equal(Node, Node a, Node b, int) { print("{} != {}", a, b); }
-	void signed_greater_than(Node, Node a, Node b, int) { print("{}.signed_greater_than({})", a, b); }
-	void signed_greater_equal(Node, Node a, Node b, int) { print("{}.signed_greater_equal({})", a, b); }
-	void unsigned_greater_than(Node, Node a, Node b, int) { print("{} > {}", a, b); }
-	void unsigned_greater_equal(Node, Node a, Node b, int) { print("{} >= {}", a, b); }
-	void logical_shift_left(Node, Node a, Node b, int, int) { print("{} << {}", a, b); }
-	void logical_shift_right(Node, Node a, Node b, int, int) { print("{} >> {}", a, b); }
-	void arithmetic_shift_right(Node, Node a, Node b, int, int) { print("{}.arithmetic_shift_right({})", a, b); }
-	void mux(Node, Node a, Node b, Node s, int) { print("{2}.any() ? {1} : {0}", a, b, s); }
-	void pmux(Node, Node a, Node b, Node s, int, int) { print("{0}.pmux({1}, {2})", a, b, s); }
-	void constant(Node, RTLIL::Const value) {
+	void buf(Node, Node n) override { print("{}", n); }
+	void slice(Node, Node a, int offset, int out_width) override { print("{0}.slice<{2}>({1})", a, offset, out_width); }
+	void zero_extend(Node, Node a, int out_width) override { print("{}.zero_extend<{}>()", a, out_width); }
+	void sign_extend(Node, Node a, int out_width) override { print("{}.sign_extend<{}>()", a, out_width); }
+	void concat(Node, Node a, Node b) override { print("{}.concat({})", a, b); }
+	void add(Node, Node a, Node b) override { print("{} + {}", a, b); }
+	void sub(Node, Node a, Node b) override { print("{} - {}", a, b); }
+	void mul(Node, Node a, Node b) override { print("{} * {}", a, b); }
+	void unsigned_div(Node, Node a, Node b) override { print("{} / {}", a, b); }
+	void unsigned_mod(Node, Node a, Node b) override { print("{} % {}", a, b); }
+	void bitwise_and(Node, Node a, Node b) override { print("{} & {}", a, b); }
+	void bitwise_or(Node, Node a, Node b) override { print("{} | {}", a, b); }
+	void bitwise_xor(Node, Node a, Node b) override { print("{} ^ {}", a, b); }
+	void bitwise_not(Node, Node a) override { print("~{}", a); }
+	void unary_minus(Node, Node a) override { print("-{}", a); }
+	void reduce_and(Node, Node a) override { print("{}.all()", a); }
+	void reduce_or(Node, Node a) override { print("{}.any()", a); }
+	void reduce_xor(Node, Node a) override { print("{}.parity()", a); }
+	void equal(Node, Node a, Node b) override { print("{} == {}", a, b); }
+	void not_equal(Node, Node a, Node b) override { print("{} != {}", a, b); }
+	void signed_greater_than(Node, Node a, Node b) override { print("{}.signed_greater_than({})", a, b); }
+	void signed_greater_equal(Node, Node a, Node b) override { print("{}.signed_greater_equal({})", a, b); }
+	void unsigned_greater_than(Node, Node a, Node b) override { print("{} > {}", a, b); }
+	void unsigned_greater_equal(Node, Node a, Node b) override { print("{} >= {}", a, b); }
+	void logical_shift_left(Node, Node a, Node b) override { print("{} << {}", a, b); }
+	void logical_shift_right(Node, Node a, Node b) override { print("{} >> {}", a, b); }
+	void arithmetic_shift_right(Node, Node a, Node b) override { print("{}.arithmetic_shift_right({})", a, b); }
+	void mux(Node, Node a, Node b, Node s) override { print("{2}.any() ? {1} : {0}", a, b, s); }
+	void pmux(Node, Node a, Node b, Node s) override { print("{0}.pmux({1}, {2})", a, b, s); }
+	void constant(Node, RTLIL::Const value) override {
 		std::stringstream ss;
 		bool multiple = value.size() > 32;
 		ss << "Signal<" << value.size() << ">(" << std::hex << std::showbase;
@@ -151,11 +151,11 @@ template<class NodePrinter> struct CxxPrintVisitor {
 		ss << ")";
 		print("{}", ss.str());
 	}
-	void input(Node, IdString name) { print("input.{}", input_struct[name]); }
-	void state(Node, IdString name) { print("current_state.{}", state_struct[name]); }
-	void memory_read(Node, Node mem, Node addr, int, int) { print("{}.read({})", mem, addr); }
-	void memory_write(Node, Node mem, Node addr, Node data, int, int) { print("{}.write({}, {})", mem, addr, data); }
-	void undriven(Node, int width) { print("Signal<{}>(0)", width); }
+	void input(Node, IdString name) override { print("input.{}", input_struct[name]); }
+	void state(Node, IdString name) override { print("current_state.{}", state_struct[name]); }
+	void memory_read(Node, Node mem, Node addr) override { print("{}.read({})", mem, addr); }
+	void memory_write(Node, Node mem, Node addr, Node data) override { print("{}.write({}, {})", mem, addr, data); }
+	void undriven(Node, int width) override { print("Signal<{}>(0)", width); }
 };
 
 struct CxxModule {
diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index 113fb710080..c35a48dd809 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -109,7 +109,7 @@ class SmtStruct {
 	}
 };
 
-struct SmtPrintVisitor {
+struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor<SExpr> {
 	using Node = FunctionalIR::Node;
 	std::function<SExpr(Node)> n;
 	SmtStruct &input_struct;
@@ -134,35 +134,35 @@ struct SmtPrintVisitor {
 		return list(list("_", "extract", offset + out_width - 1, offset), std::move(arg));
 	}
 
-	SExpr buf(Node, Node a) { return n(a); }
-	SExpr slice(Node, Node a, int, int offset, int out_width) { return extract(n(a), offset, out_width); }
-	SExpr zero_extend(Node, Node a, int, int out_width) { return list(list("_", "zero_extend", out_width - a.width()), n(a)); }
-	SExpr sign_extend(Node, Node a, int, int out_width) { return list(list("_", "sign_extend", out_width - a.width()), n(a)); }
-	SExpr concat(Node, Node a, int, Node b, int) { return list("concat", n(b), n(a)); }
-	SExpr add(Node, Node a, Node b, int) { return list("bvadd", n(a), n(b)); }
-	SExpr sub(Node, Node a, Node b, int) { return list("bvsub", n(a), n(b)); }
-	SExpr mul(Node, Node a, Node b, int) { return list("bvmul", n(a), n(b)); }
-	SExpr unsigned_div(Node, Node a, Node b, int) { return list("bvudiv", n(a), n(b)); }
-	SExpr unsigned_mod(Node, Node a, Node b, int) { return list("bvurem", n(a), n(b)); }
-	SExpr bitwise_and(Node, Node a, Node b, int) { return list("bvand", n(a), n(b)); }
-	SExpr bitwise_or(Node, Node a, Node b, int) { return list("bvor", n(a), n(b)); }
-	SExpr bitwise_xor(Node, Node a, Node b, int) { return list("bvxor", n(a), n(b)); }
-	SExpr bitwise_not(Node, Node a, int) { return list("bvnot", n(a)); }
-	SExpr unary_minus(Node, Node a, int) { return list("bvneg", n(a)); }
-	SExpr reduce_and(Node, Node a, int) { return from_bool(list("=", n(a), literal(RTLIL::Const(State::S1, a.width())))); }
-	SExpr reduce_or(Node, Node a, int) { return from_bool(list("distinct", n(a), literal(RTLIL::Const(State::S0, a.width())))); }
-	SExpr reduce_xor(Node, Node a, int) {
+	SExpr buf(Node, Node a) override { return n(a); }
+	SExpr slice(Node, Node a, int offset, int out_width) override { return extract(n(a), offset, out_width); }
+	SExpr zero_extend(Node, Node a, int out_width) override { return list(list("_", "zero_extend", out_width - a.width()), n(a)); }
+	SExpr sign_extend(Node, Node a, int out_width) override { return list(list("_", "sign_extend", out_width - a.width()), n(a)); }
+	SExpr concat(Node, Node a, Node b) override { return list("concat", n(b), n(a)); }
+	SExpr add(Node, Node a, Node b) override { return list("bvadd", n(a), n(b)); }
+	SExpr sub(Node, Node a, Node b) override { return list("bvsub", n(a), n(b)); }
+	SExpr mul(Node, Node a, Node b) override { return list("bvmul", n(a), n(b)); }
+	SExpr unsigned_div(Node, Node a, Node b) override { return list("bvudiv", n(a), n(b)); }
+	SExpr unsigned_mod(Node, Node a, Node b) override { return list("bvurem", n(a), n(b)); }
+	SExpr bitwise_and(Node, Node a, Node b) override { return list("bvand", n(a), n(b)); }
+	SExpr bitwise_or(Node, Node a, Node b) override { return list("bvor", n(a), n(b)); }
+	SExpr bitwise_xor(Node, Node a, Node b) override { return list("bvxor", n(a), n(b)); }
+	SExpr bitwise_not(Node, Node a) override { return list("bvnot", n(a)); }
+	SExpr unary_minus(Node, Node a) override { return list("bvneg", n(a)); }
+	SExpr reduce_and(Node, Node a) override { return from_bool(list("=", n(a), literal(RTLIL::Const(State::S1, a.width())))); }
+	SExpr reduce_or(Node, Node a) override { return from_bool(list("distinct", n(a), literal(RTLIL::Const(State::S0, a.width())))); }
+	SExpr reduce_xor(Node, Node a) override {
 		vector<SExpr> s { "bvxor" };
 		for(int i = 0; i < a.width(); i++)
 			s.push_back(extract(n(a), i));
 		return s;
 	}
-	SExpr equal(Node, Node a, Node b, int) { return from_bool(list("=", n(a), n(b))); }
-	SExpr not_equal(Node, Node a, Node b, int) { return from_bool(list("distinct", n(a), n(b))); }
-	SExpr signed_greater_than(Node, Node a, Node b, int) { return from_bool(list("bvsgt", n(a), n(b))); }
-	SExpr signed_greater_equal(Node, Node a, Node b, int) { return from_bool(list("bvsge", n(a), n(b))); }
-	SExpr unsigned_greater_than(Node, Node a, Node b, int) { return from_bool(list("bvugt", n(a), n(b))); }
-	SExpr unsigned_greater_equal(Node, Node a, Node b, int) { return from_bool(list("bvuge", n(a), n(b))); }
+	SExpr equal(Node, Node a, Node b) override { return from_bool(list("=", n(a), n(b))); }
+	SExpr not_equal(Node, Node a, Node b) override { return from_bool(list("distinct", n(a), n(b))); }
+	SExpr signed_greater_than(Node, Node a, Node b) override { return from_bool(list("bvsgt", n(a), n(b))); }
+	SExpr signed_greater_equal(Node, Node a, Node b) override { return from_bool(list("bvsge", n(a), n(b))); }
+	SExpr unsigned_greater_than(Node, Node a, Node b) override { return from_bool(list("bvugt", n(a), n(b))); }
+	SExpr unsigned_greater_equal(Node, Node a, Node b) override { return from_bool(list("bvuge", n(a), n(b))); }
 
 	SExpr extend(SExpr &&a, int in_width, int out_width) {
 		if(in_width < out_width)
@@ -170,24 +170,24 @@ struct SmtPrintVisitor {
 		else
 			return std::move(a);
 	}
-	SExpr logical_shift_left(Node, Node a, Node b, int, int) { return list("bvshl", n(a), extend(n(b), b.width(), a.width())); }
-	SExpr logical_shift_right(Node, Node a, Node b, int, int) { return list("bvlshr", n(a), extend(n(b), b.width(), a.width())); }
-	SExpr arithmetic_shift_right(Node, Node a, Node b, int, int) { return list("bvashr", n(a), extend(n(b), b.width(), a.width())); }
-	SExpr mux(Node, Node a, Node b, Node s, int) { return list("ite", to_bool(n(s)), n(b), n(a)); }
-	SExpr pmux(Node, Node a, Node b, Node s, int, int) {
+	SExpr logical_shift_left(Node, Node a, Node b) override { return list("bvshl", n(a), extend(n(b), b.width(), a.width())); }
+	SExpr logical_shift_right(Node, Node a, Node b) override { return list("bvlshr", n(a), extend(n(b), b.width(), a.width())); }
+	SExpr arithmetic_shift_right(Node, Node a, Node b) override { return list("bvashr", n(a), extend(n(b), b.width(), a.width())); }
+	SExpr mux(Node, Node a, Node b, Node s) override { return list("ite", to_bool(n(s)), n(b), n(a)); }
+	SExpr pmux(Node, Node a, Node b, Node s) override {
 		SExpr rv = n(a);
 		for(int i = 0; i < s.width(); i++)
 			rv = list("ite", to_bool(extract(n(s), i)), extract(n(b), a.width() * i, a.width()), rv);
 		return rv;
 	}
-	SExpr constant(Node, RTLIL::Const value) { return literal(value); }
-	SExpr memory_read(Node, Node mem, Node addr, int, int) { return list("select", n(mem), n(addr)); }
-	SExpr memory_write(Node, Node mem, Node addr, Node data, int, int) { return list("store", n(mem), n(addr), n(data)); }
+	SExpr constant(Node, RTLIL::Const value) override { return literal(value); }
+	SExpr memory_read(Node, Node mem, Node addr) override { return list("select", n(mem), n(addr)); }
+	SExpr memory_write(Node, Node mem, Node addr, Node data) override { return list("store", n(mem), n(addr), n(data)); }
 
-	SExpr input(Node, IdString name) { return input_struct.access("inputs", name); }
-	SExpr state(Node, IdString name) { return state_struct.access("state", name); }
+	SExpr input(Node, IdString name) override { return input_struct.access("inputs", name); }
+	SExpr state(Node, IdString name) override { return state_struct.access("state", name); }
 
-	SExpr undriven(Node, int width) { return literal(RTLIL::Const(State::S0, width)); }
+	SExpr undriven(Node, int width) override { return literal(RTLIL::Const(State::S0, width)); }
 };
 
 struct SmtModule {
diff --git a/kernel/functional.h b/kernel/functional.h
index 09a8826433c..09f66c9813b 100644
--- a/kernel/functional.h
+++ b/kernel/functional.h
@@ -109,7 +109,7 @@ struct ComputeGraph
         {
             auto found = graph_->sparse_attrs.find(index_);
             log_assert(found != graph_->sparse_attrs.end());
-            return *found;
+            return found->second;
         }
     };
 
diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc
index b8fa6b88e5f..9b8076a0ef7 100644
--- a/kernel/functionalir.cc
+++ b/kernel/functionalir.cc
@@ -21,6 +21,83 @@
 
 YOSYS_NAMESPACE_BEGIN
 
+const char *FunctionalIR::fn_to_string(FunctionalIR::Fn fn) {
+	switch(fn) {
+	case FunctionalIR::Fn::invalid: return "invalid";
+	case FunctionalIR::Fn::buf: return "buf";
+	case FunctionalIR::Fn::slice: return "slice";
+	case FunctionalIR::Fn::zero_extend: return "zero_extend";
+	case FunctionalIR::Fn::sign_extend: return "sign_extend";
+	case FunctionalIR::Fn::concat: return "concat";
+	case FunctionalIR::Fn::add: return "add";
+	case FunctionalIR::Fn::sub: return "sub";
+	case FunctionalIR::Fn::mul: return "mul";
+	case FunctionalIR::Fn::unsigned_div: return "unsigned_div";
+	case FunctionalIR::Fn::unsigned_mod: return "unsigned_mod";
+	case FunctionalIR::Fn::bitwise_and: return "bitwise_and";
+	case FunctionalIR::Fn::bitwise_or: return "bitwise_or";
+	case FunctionalIR::Fn::bitwise_xor: return "bitwise_xor";
+	case FunctionalIR::Fn::bitwise_not: return "bitwise_not";
+	case FunctionalIR::Fn::reduce_and: return "reduce_and";
+	case FunctionalIR::Fn::reduce_or: return "reduce_or";
+	case FunctionalIR::Fn::reduce_xor: return "reduce_xor";
+	case FunctionalIR::Fn::unary_minus: return "unary_minus";
+	case FunctionalIR::Fn::equal: return "equal";
+	case FunctionalIR::Fn::not_equal: return "not_equal";
+	case FunctionalIR::Fn::signed_greater_than: return "signed_greater_than";
+	case FunctionalIR::Fn::signed_greater_equal: return "signed_greater_equal";
+	case FunctionalIR::Fn::unsigned_greater_than: return "unsigned_greater_than";
+	case FunctionalIR::Fn::unsigned_greater_equal: return "unsigned_greater_equal";
+	case FunctionalIR::Fn::logical_shift_left: return "logical_shift_left";
+	case FunctionalIR::Fn::logical_shift_right: return "logical_shift_right";
+	case FunctionalIR::Fn::arithmetic_shift_right: return "arithmetic_shift_right";
+	case FunctionalIR::Fn::mux: return "mux";
+	case FunctionalIR::Fn::pmux: return "pmux";
+	case FunctionalIR::Fn::constant: return "constant";
+	case FunctionalIR::Fn::input: return "input";
+	case FunctionalIR::Fn::state: return "state";
+	case FunctionalIR::Fn::multiple: return "multiple";
+	case FunctionalIR::Fn::undriven: return "undriven";
+	case FunctionalIR::Fn::memory_read: return "memory_read";
+	case FunctionalIR::Fn::memory_write: return "memory_write";
+	}
+	log_error("fn_to_string: unknown FunctionalIR::Fn value %d", (int)fn);
+}
+
+struct PrintVisitor : FunctionalIR::DefaultVisitor<std::string> {
+	using Node = FunctionalIR::Node;
+	std::function<std::string(Node)> np;
+	PrintVisitor(std::function<std::string(Node)> np) : np(np) { }
+	// as a general rule the default handler is good enough iff the only arguments are of type Node
+	std::string slice(Node, Node a, int offset, int out_width) override { return "slice(" + np(a) + ", " + std::to_string(offset) + ", " + std::to_string(out_width) + ")"; }
+	std::string zero_extend(Node, Node a, int out_width) override { return "zero_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; }
+	std::string sign_extend(Node, Node a, int out_width) override { return "sign_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; }
+	std::string constant(Node, RTLIL::Const value) override { return "constant(" + value.as_string() + ")"; }
+	std::string input(Node, IdString name) override { return "input(" + name.str() + ")"; }
+	std::string state(Node, IdString name) override { return "state(" + name.str() + ")"; }
+	std::string undriven(Node, int width) override { return "undriven(" + std::to_string(width) + ")"; }
+	std::string default_handler(Node self) override {
+		std::string ret = FunctionalIR::fn_to_string(self.fn());
+		ret += "(";
+		for(size_t i = 0; i < self.arg_count(); i++) {
+			if(i > 0) ret += ", ";
+			ret += np(self.arg(i));
+		}
+		ret += ")";
+		return ret;
+	}
+};
+
+std::string FunctionalIR::Node::to_string()
+{
+	return to_string([](Node n) { return RTLIL::unescape_id(n.name()); });
+}
+
+std::string FunctionalIR::Node::to_string(std::function<std::string(Node)> np)
+{
+	return visit(PrintVisitor(np));
+}
+
 template <class T, class Factory>
 class CellSimplifier {
 	Factory &factory;
@@ -47,11 +124,6 @@ class CellSimplifier {
 		return neg_if(a, a_width, sign(a, a_width));
 	}
 public:
-	T reduce_or(T a, int width) {
-		if (width == 1)
-			return a;
-		return factory.reduce_or(a, width);
-	}
 	T extend(T a, int in_width, int out_width, bool is_signed) {
 		if(in_width == out_width)
 			return a;
@@ -153,8 +225,8 @@ class CellSimplifier {
 			else
 				log_abort();
 		}else if(cellType.in({ID($logic_or), ID($logic_and)})){
-			T a = reduce_or(inputs.at(ID(A)), a_width);
-			T b = reduce_or(inputs.at(ID(B)), b_width);
+			T a = factory.reduce_or(inputs.at(ID(A)), a_width);
+			T b = factory.reduce_or(inputs.at(ID(B)), b_width);
 			T y = cellType == ID($logic_and) ? factory.bitwise_and(a, b, 1) : factory.bitwise_or(a, b, 1);
 			return extend(y, 1, y_width, false);
 		}else if(cellType == ID($not)){
@@ -166,11 +238,11 @@ class CellSimplifier {
 			T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed);
 			return factory.unary_minus(a, y_width);
 		}else if(cellType == ID($logic_not)){
-			T a = reduce_or(inputs.at(ID(A)), a_width);
+			T a = factory.reduce_or(inputs.at(ID(A)), a_width);
 			T y = factory.bitwise_not(a, 1);
 			return extend(y, 1, y_width, false);
 		}else if(cellType.in({ID($reduce_or), ID($reduce_bool)})){
-			T a = reduce_or(inputs.at(ID(A)), a_width);
+			T a = factory.reduce_or(inputs.at(ID(A)), a_width);
 			return extend(a, 1, y_width, false);
 		}else if(cellType == ID($reduce_and)){
 			T a = factory.reduce_and(inputs.at(ID(A)), a_width);
@@ -244,7 +316,7 @@ class CellSimplifier {
 					// which equals the negative of (-a) / b with rounding up rather than down
 					// note that to handle the case where a = most negative value properly,
 					// we have to calculate a1_sign from the original values rather than using sign(a1, width)
-					T a1_sign = factory.bitwise_and(factory.not_equal(sign(a, width), sign(b, width), 1), reduce_or(a, width), 1);
+					T a1_sign = factory.bitwise_and(factory.not_equal(sign(a, width), sign(b, width), 1), factory.reduce_or(a, width), 1);
 					T a2 = factory.mux(a1, factory.bitwise_not(a1, width), a1_sign, width);
 					T y1 = factory.unsigned_div(a2, b1, width);
 					T y2 = extend(y1, width, y_width, false);
@@ -560,6 +632,7 @@ void FunctionalIR::forward_buf() {
     _graph.permute(perm, alias);
 }
 
+// Quoting routine to make error messages nicer
 static std::string quote_fmt(const char *fmt)
 {
 	std::string r;
diff --git a/kernel/functionalir.h b/kernel/functionalir.h
index 99fc872a81a..e586695695a 100644
--- a/kernel/functionalir.h
+++ b/kernel/functionalir.h
@@ -31,45 +31,123 @@ YOSYS_NAMESPACE_BEGIN
 
 class FunctionalIR {
 public:
+	// each function is documented with a short pseudocode declaration or definition
+	// standard C/Verilog operators are used to describe the result
+	// 
+	// the types used in this are:
+	// - bit[N]: a bitvector of N bits
+	//   bit[N] can be indicated as signed or unsigned. this is not tracked by the functional backend
+	//   but is meant to indicate how the value is interpreted
+	//   if a bit[N] is marked as neither signed nor unsigned, this means the result should be valid with *either* interpretation
+	// - memory[N, M]: a memory with N address and M data bits
+	// - int: C++ int
+	// - Const[N]: yosys RTLIL::Const (with size() == N)
+	// - IdString: yosys IdString
+	// - any: used in documentation to indicate that the type is unconstrained
+	//
+	// nodes in the functional backend are either of type bit[N] or memory[N,M] (for some N, M: int)
+	// additionally, they can carry a constant of type int, Const[N] or IdString
+	// each node has a 'sort' field that stores the type of the node
+	// slice, zero_extend, sign_extend use the type field to store out_width
 	enum class Fn {
+		// invalid() = known-invalid/shouldn't happen value
+		// TODO: maybe remove this and use e.g. std::optional instead?
 		invalid,
+		// buf(a: any): any = a
+		// no-op operation
+		// when constructing the compute graph we generate invalid buf() nodes as a placeholder
+		// and later insert the argument
 		buf,
+		// slice(a: bit[in_width], offset: int, out_width: int): bit[out_width] = a[offset +: out_width]
+		// required: offset + out_width <= in_width
 		slice,
+		// zero_extend(a: unsigned bit[in_width], out_width: int): unsigned bit[out_width] = a (zero extended)
+		// required: out_width > in_width
 		zero_extend,
+		// sign_extend(a: signed bit[in_width], out_width: int): signed bit[out_width] = a (sign extended)
+		// required: out_width > in_width
 		sign_extend,
+		// concat(a: bit[N], b: bit[M]): bit[N+M] = {b, a} (verilog syntax)
+		// concatenates two bitvectors, with a in the least significant position and b in the more significant position
 		concat,
+		// add(a: bit[N], b: bit[N]): bit[N] = a + b
 		add,
+		// sub(a: bit[N], b: bit[N]): bit[N] = a - b
 		sub,
+		// mul(a: bit[N], b: bit[N]): bit[N] = a * b
 		mul,
+		// unsigned_div(a: unsigned bit[N], b: unsigned bit[N]): bit[N] = a / b
 		unsigned_div,
+		// unsigned_mod(a: signed bit[N], b: signed bit[N]): bit[N] = a % b
 		unsigned_mod,
+		// bitwise_and(a: bit[N], b: bit[N]): bit[N] = a & b
 		bitwise_and,
+		// bitwise_or(a: bit[N], b: bit[N]): bit[N] = a | b
 		bitwise_or,
+		// bitwise_xor(a: bit[N], b: bit[N]): bit[N] = a ^ b
 		bitwise_xor,
+		// bitwise_not(a: bit[N]): bit[N] = ~a
 		bitwise_not,
+		// reduce_and(a: bit[N]): bit[1] = &a
 		reduce_and,
+		// reduce_or(a: bit[N]): bit[1] = |a
 		reduce_or,
+		// reduce_xor(a: bit[N]): bit[1] = ^a
 		reduce_xor,
+		// unary_minus(a: bit[N]): bit[N] = -a
 		unary_minus,
+		// equal(a: bit[N], b: bit[N]): bit[1] = (a == b)
 		equal,
+		// not_equal(a: bit[N], b: bit[N]): bit[1] = (a != b)
 		not_equal,
+		// signed_greater_than(a: signed bit[N], b: signed bit[N]): bit[1] = (a > b)
 		signed_greater_than,
+		// signed_greater_equal(a: signed bit[N], b: signed bit[N]): bit[1] = (a >= b)
 		signed_greater_equal,
+		// unsigned_greater_than(a: unsigned bit[N], b: unsigned bit[N]): bit[1] = (a > b)
 		unsigned_greater_than,
+		// unsigned_greater_equal(a: unsigned bit[N], b: unsigned bit[N]): bit[1] = (a >= b)
 		unsigned_greater_equal,
+		// logical_shift_left(a: bit[N], b: unsigned bit[M]): bit[N] = a << b
+		// required: M <= clog2(N + 1)
 		logical_shift_left,
+		// logical_shift_right(a: unsigned bit[N], b: unsigned bit[M]): unsigned bit[N] = a >> b
+		// required: M <= clog2(N + 1)
 		logical_shift_right,
+		// arithmetic_shift_right(a: signed bit[N], b: unsigned bit[M]): signed bit[N] = a >> b
+		// required: M <= clog2(N + 1)
 		arithmetic_shift_right,
+		// mux(a: bit[N], b: bit[N], s: bit[1]): bit[N] = s ? b : a
 		mux,
+		// pmux(a: bit[N], b: bit[N*M], s: bit[M]): bit[N]
+		// required: no more than one bit in b is set
+		// if s[i] = 1 for any i, then returns b[i * N +: N]
+		// returns a if s == 0
 		pmux,
+		// constant(a: Const[N]): bit[N] = a
 		constant,
+		// input(a: IdString): any
+		// returns the current value of the input with the specified name
 		input,
+		// state(a: IdString): any
+		// returns the current value of the state variable with the specified name
 		state,
+		// multiple(a: any, b: any, c: any, ...): any
+		// indicates a value driven by multiple inputs
 		multiple,
+		// undriven(width: int): bit[width]
+		// indicates an undriven value
 		undriven,
+		// memory_read(memory: memory[addr_width, data_width], addr: bit[addr_width]): bit[data_width] = memory[addr]
 		memory_read,
+		// memory_write(memory: memory[addr_width, data_width], addr: bit[addr_width], data: bit[data_width]): memory[addr_width, data_width]
+		// returns a copy of `memory` but with the value at `addr` changed to `data`
 		memory_write
 	};
+	// returns the name of a FunctionalIR::Fn value, as a string literal
+	static const char *fn_to_string(Fn);
+	// FunctionalIR::Sort represents the sort or type of a node
+	// currently the only two types are signal/bit and memory
 	class Sort {
 		std::variant<int, std::pair<int, int>> _v;
 	public:
@@ -77,13 +155,18 @@ class FunctionalIR {
 		Sort(int addr_width, int data_width) : _v(std::make_pair(addr_width, data_width)) { }
 		bool is_signal() const { return _v.index() == 0; }
 		bool is_memory() const { return _v.index() == 1; }
+		// returns the width of a bitvector type, errors out for other types
 		int width() const { return std::get<0>(_v); }
+		// returns the address width of a bitvector type, errors out for other types
 		int addr_width() const { return std::get<1>(_v).first; }
+		// returns the data width of a bitvector type, errors out for other types
 		int data_width() const { return std::get<1>(_v).second; }
 		bool operator==(Sort const& other) const { return _v == other._v; }
 		unsigned int hash() const { return mkhash(_v); }
 	};
 private:
+	// one NodeData is stored per Node, containing the function and non-node arguments
+	// note that NodeData is deduplicated by ComputeGraph
 	class NodeData {
 		Fn _fn;
 		std::variant<
@@ -107,9 +190,14 @@ class FunctionalIR {
 			return _fn == other._fn && _extra == other._extra;
 		}
 	};
+	// Attr contains all the information about a note that should not be deduplicated
 	struct Attr {
 		Sort sort;
 	};
+	// our specialised version of ComputeGraph
+	// the sparse_attr IdString stores a naming suggestion, retrieved with name()
+	// the key is currently used to identify the nodes that represent output and next state values
+	// the bool is true for next state values
 	using Graph = ComputeGraph<NodeData, Attr, IdString, std::pair<IdString, bool>>;
 	Graph _graph;
 	dict<IdString, Sort> _inputs;
@@ -132,53 +220,17 @@ class FunctionalIR {
 	}
 public:
 	class Factory;
+	// Node is an immutable reference to a FunctionalIR node
 	class Node {
 		friend class Factory;
 		friend class FunctionalIR;
-		Graph::Ref _ref;
-		explicit Node(Graph::Ref ref) : _ref(ref) { }
-		operator Graph::Ref() { return _ref; }
-		template<class NodePrinter> struct PrintVisitor {
-			NodePrinter np;
-			PrintVisitor(NodePrinter np) : np(np) { }
-			std::string buf(Node, Node n) { return "buf(" + np(n) + ")"; }
-			std::string slice(Node, Node a, int, int offset, int out_width) { return "slice(" + np(a) + ", " + std::to_string(offset) + ", " + std::to_string(out_width) + ")"; }
-			std::string zero_extend(Node, Node a, int, int out_width) { return "zero_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; }
-			std::string sign_extend(Node, Node a, int, int out_width) { return "sign_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; }
-			std::string concat(Node, Node a, int, Node b, int) { return "concat(" + np(a) + ", " + np(b) + ")"; }
-			std::string add(Node, Node a, Node b, int) { return "add(" + np(a) + ", " + np(b) + ")"; }
-			std::string sub(Node, Node a, Node b, int) { return "sub(" + np(a) + ", " + np(b) + ")"; }
-			std::string mul(Node, Node a, Node b, int) { return "mul(" + np(a) + ", " + np(b) + ")"; }
-			std::string unsigned_div(Node, Node a, Node b, int) { return "unsigned_div(" + np(a) + ", " + np(b) + ")"; }
-			std::string unsigned_mod(Node, Node a, Node b, int) { return "unsigned_mod(" + np(a) + ", " + np(b) + ")"; }
-			std::string bitwise_and(Node, Node a, Node b, int) { return "bitwise_and(" + np(a) + ", " + np(b) + ")"; }
-			std::string bitwise_or(Node, Node a, Node b, int) { return "bitwise_or(" + np(a) + ", " + np(b) + ")"; }
-			std::string bitwise_xor(Node, Node a, Node b, int) { return "bitwise_xor(" + np(a) + ", " + np(b) + ")"; }
-			std::string bitwise_not(Node, Node a, int) { return "bitwise_not(" + np(a) + ")"; }
-			std::string unary_minus(Node, Node a, int) { return "unary_minus(" + np(a) + ")"; }
-			std::string reduce_and(Node, Node a, int) { return "reduce_and(" + np(a) + ")"; }
-			std::string reduce_or(Node, Node a, int) { return "reduce_or(" + np(a) + ")"; }
-			std::string reduce_xor(Node, Node a, int) { return "reduce_xor(" + np(a) + ")"; }
-			std::string equal(Node, Node a, Node b, int) { return "equal(" + np(a) + ", " + np(b) + ")"; }
-			std::string not_equal(Node, Node a, Node b, int) { return "not_equal(" + np(a) + ", " + np(b) + ")"; }
-			std::string signed_greater_than(Node, Node a, Node b, int) { return "signed_greater_than(" + np(a) + ", " + np(b) + ")"; }
-			std::string signed_greater_equal(Node, Node a, Node b, int) { return "signed_greater_equal(" + np(a) + ", " + np(b) + ")"; }
-			std::string unsigned_greater_than(Node, Node a, Node b, int) { return "unsigned_greater_than(" + np(a) + ", " + np(b) + ")"; }
-			std::string unsigned_greater_equal(Node, Node a, Node b, int) { return "unsigned_greater_equal(" + np(a) + ", " + np(b) + ")"; }
-			std::string logical_shift_left(Node, Node a, Node b, int, int) { return "logical_shift_left(" + np(a) + ", " + np(b) + ")"; }
-			std::string logical_shift_right(Node, Node a, Node b, int, int) { return "logical_shift_right(" + np(a) + ", " + np(b) + ")"; }
-			std::string arithmetic_shift_right(Node, Node a, Node b, int, int) { return "arithmetic_shift_right(" + np(a) + ", " + np(b) + ")"; }
-			std::string mux(Node, Node a, Node b, Node s, int) { return "mux(" + np(a) + ", " + np(b) + ", " + np(s) + ")"; }
-			std::string pmux(Node, Node a, Node b, Node s, int, int) { return "pmux(" + np(a) + ", " + np(b) + ", " + np(s) + ")"; }
-			std::string constant(Node, RTLIL::Const value) { return "constant(" + value.as_string() + ")"; }
-			std::string input(Node, IdString name) { return "input(" + name.str() + ")"; }
-			std::string state(Node, IdString name) { return "state(" + name.str() + ")"; }
-			std::string memory_read(Node, Node mem, Node addr, int, int) { return "memory_read(" + np(mem) + ", " + np(addr) + ")"; }
-			std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { return "memory_write(" + np(mem) + ", " + np(addr) + ", " + np(data) + ")"; }
-			std::string undriven(Node, int width) { return "undriven(" + std::to_string(width) + ")"; }
-		};
+		Graph::ConstRef _ref;
+		explicit Node(Graph::ConstRef ref) : _ref(ref) { }
+		explicit operator Graph::ConstRef() { return _ref; }
 	public:
+		// the node's index. may change if nodes are added or removed
 		int id() const { return _ref.index(); }
+		// a name suggestion for the node, which need not be unique
 		IdString name() const {
 			if(_ref.has_sparse_attr())
 				return _ref.sparse_attr();
@@ -187,55 +239,135 @@ class FunctionalIR {
 		}
 		Fn fn() const { return _ref.function().fn(); }
 		Sort sort() const { return _ref.attr().sort; }
+		// returns the width of a bitvector node, errors out for other nodes
 		int width() const { return sort().width(); }
+		size_t arg_count() const { return _ref.size(); }
 		Node arg(int n) const { return Node(_ref.arg(n)); }
+		// visit calls the appropriate visitor method depending on the type of the node
 		template<class Visitor> auto visit(Visitor v) const
 		{
+			// currently templated but could be switched to AbstractVisitor &
 			switch(_ref.function().fn()) {
 			case Fn::invalid: log_error("invalid node in visit"); break;
 			case Fn::buf: return v.buf(*this, arg(0)); break;
-			case Fn::slice: return v.slice(*this, arg(0), arg(0).width(), _ref.function().as_int(), sort().width()); break;
-			case Fn::zero_extend: return v.zero_extend(*this, arg(0), arg(0).width(), width()); break;
-			case Fn::sign_extend: return v.sign_extend(*this, arg(0), arg(0).width(), width()); break;
-			case Fn::concat: return v.concat(*this, arg(0), arg(0).width(), arg(1), arg(1).width()); break;
-			case Fn::add: return v.add(*this, arg(0), arg(1), sort().width()); break;
-			case Fn::sub: return v.sub(*this, arg(0), arg(1), sort().width()); break;
-			case Fn::mul: return v.mul(*this, arg(0), arg(1), sort().width()); break;
-			case Fn::unsigned_div: return v.unsigned_div(*this, arg(0), arg(1), sort().width()); break;
-			case Fn::unsigned_mod: return v.unsigned_mod(*this, arg(0), arg(1), sort().width()); break;
-			case Fn::bitwise_and: return v.bitwise_and(*this, arg(0), arg(1), sort().width()); break;
-			case Fn::bitwise_or: return v.bitwise_or(*this, arg(0), arg(1), sort().width()); break;
-			case Fn::bitwise_xor: return v.bitwise_xor(*this, arg(0), arg(1), sort().width()); break;
-			case Fn::bitwise_not: return v.bitwise_not(*this, arg(0), sort().width()); break;
-			case Fn::unary_minus: return v.unary_minus(*this, arg(0), sort().width()); break;
-			case Fn::reduce_and: return v.reduce_and(*this, arg(0), arg(0).width()); break;
-			case Fn::reduce_or: return v.reduce_or(*this, arg(0), arg(0).width()); break;
-			case Fn::reduce_xor: return v.reduce_xor(*this, arg(0), arg(0).width()); break;
-			case Fn::equal: return v.equal(*this, arg(0), arg(1), arg(0).width()); break;
-			case Fn::not_equal: return v.not_equal(*this, arg(0), arg(1), arg(0).width()); break;
-			case Fn::signed_greater_than: return v.signed_greater_than(*this, arg(0), arg(1), arg(0).width()); break; 
-			case Fn::signed_greater_equal: return v.signed_greater_equal(*this, arg(0), arg(1), arg(0).width()); break;
-			case Fn::unsigned_greater_than: return v.unsigned_greater_than(*this, arg(0), arg(1), arg(0).width()); break; 
-			case Fn::unsigned_greater_equal: return v.unsigned_greater_equal(*this, arg(0), arg(1), arg(0).width()); break;
-			case Fn::logical_shift_left: return v.logical_shift_left(*this, arg(0), arg(1), arg(0).width(), arg(1).width()); break;
-			case Fn::logical_shift_right: return v.logical_shift_right(*this, arg(0), arg(1), arg(0).width(), arg(1).width()); break;
-			case Fn::arithmetic_shift_right: return v.arithmetic_shift_right(*this, arg(0), arg(1), arg(0).width(), arg(1).width()); break;
-			case Fn::mux: return v.mux(*this, arg(0), arg(1), arg(2), arg(0).width()); break;
-			case Fn::pmux: return v.pmux(*this, arg(0), arg(1), arg(2), arg(0).width(), arg(2).width()); break;
+			case Fn::slice: return v.slice(*this, arg(0), _ref.function().as_int(), sort().width()); break;
+			case Fn::zero_extend: return v.zero_extend(*this, arg(0), width()); break;
+			case Fn::sign_extend: return v.sign_extend(*this, arg(0), width()); break;
+			case Fn::concat: return v.concat(*this, arg(0), arg(1)); break;
+			case Fn::add: return v.add(*this, arg(0), arg(1)); break;
+			case Fn::sub: return v.sub(*this, arg(0), arg(1)); break;
+			case Fn::mul: return v.mul(*this, arg(0), arg(1)); break;
+			case Fn::unsigned_div: return v.unsigned_div(*this, arg(0), arg(1)); break;
+			case Fn::unsigned_mod: return v.unsigned_mod(*this, arg(0), arg(1)); break;
+			case Fn::bitwise_and: return v.bitwise_and(*this, arg(0), arg(1)); break;
+			case Fn::bitwise_or: return v.bitwise_or(*this, arg(0), arg(1)); break;
+			case Fn::bitwise_xor: return v.bitwise_xor(*this, arg(0), arg(1)); break;
+			case Fn::bitwise_not: return v.bitwise_not(*this, arg(0)); break;
+			case Fn::unary_minus: return v.unary_minus(*this, arg(0)); break;
+			case Fn::reduce_and: return v.reduce_and(*this, arg(0)); break;
+			case Fn::reduce_or: return v.reduce_or(*this, arg(0)); break;
+			case Fn::reduce_xor: return v.reduce_xor(*this, arg(0)); break;
+			case Fn::equal: return v.equal(*this, arg(0), arg(1)); break;
+			case Fn::not_equal: return v.not_equal(*this, arg(0), arg(1)); break;
+			case Fn::signed_greater_than: return v.signed_greater_than(*this, arg(0), arg(1)); break; 
+			case Fn::signed_greater_equal: return v.signed_greater_equal(*this, arg(0), arg(1)); break;
+			case Fn::unsigned_greater_than: return v.unsigned_greater_than(*this, arg(0), arg(1)); break; 
+			case Fn::unsigned_greater_equal: return v.unsigned_greater_equal(*this, arg(0), arg(1)); break;
+			case Fn::logical_shift_left: return v.logical_shift_left(*this, arg(0), arg(1)); break;
+			case Fn::logical_shift_right: return v.logical_shift_right(*this, arg(0), arg(1)); break;
+			case Fn::arithmetic_shift_right: return v.arithmetic_shift_right(*this, arg(0), arg(1)); break;
+			case Fn::mux: return v.mux(*this, arg(0), arg(1), arg(2)); break;
+			case Fn::pmux: return v.pmux(*this, arg(0), arg(1), arg(2)); break;
 			case Fn::constant: return v.constant(*this, _ref.function().as_const()); break;
 			case Fn::input: return v.input(*this, _ref.function().as_idstring()); break;
 			case Fn::state: return v.state(*this, _ref.function().as_idstring()); break;
-			case Fn::memory_read: return v.memory_read(*this, arg(0), arg(1), arg(1).width(), width()); break;
-			case Fn::memory_write: return v.memory_write(*this, arg(0), arg(1), arg(2), arg(1).width(), arg(2).width()); break;
+			case Fn::memory_read: return v.memory_read(*this, arg(0), arg(1)); break;
+			case Fn::memory_write: return v.memory_write(*this, arg(0), arg(1), arg(2)); break;
 			case Fn::multiple: log_error("multiple in visit"); break;
 			case Fn::undriven: return v.undriven(*this, width()); break;
 			}
 		}
-		template<class NodePrinter> std::string to_string(NodePrinter np)
-		{
-			return visit(PrintVisitor(np));
-		}
+		std::string to_string();
+		std::string to_string(std::function<std::string(Node)>);
+	};
+	// AbstractVisitor provides an abstract base class for visitors
+	template<class T> struct AbstractVisitor {
+		virtual T buf(Node self, Node n) = 0;
+		virtual T slice(Node self, Node a, int offset, int out_width) = 0;
+		virtual T zero_extend(Node self, Node a, int out_width) = 0;
+		virtual T sign_extend(Node self, Node a, int out_width) = 0;
+		virtual T concat(Node self, Node a, Node b) = 0;
+		virtual T add(Node self, Node a, Node b) = 0;
+		virtual T sub(Node self, Node a, Node b) = 0;
+		virtual T mul(Node self, Node a, Node b) = 0;
+		virtual T unsigned_div(Node self, Node a, Node b) = 0;
+		virtual T unsigned_mod(Node self, Node a, Node b) = 0;
+		virtual T bitwise_and(Node self, Node a, Node b) = 0;
+		virtual T bitwise_or(Node self, Node a, Node b) = 0;
+		virtual T bitwise_xor(Node self, Node a, Node b) = 0;
+		virtual T bitwise_not(Node self, Node a) = 0;
+		virtual T unary_minus(Node self, Node a) = 0;
+		virtual T reduce_and(Node self, Node a) = 0;
+		virtual T reduce_or(Node self, Node a) = 0;
+		virtual T reduce_xor(Node self, Node a) = 0;
+		virtual T equal(Node self, Node a, Node b) = 0;
+		virtual T not_equal(Node self, Node a, Node b) = 0;
+		virtual T signed_greater_than(Node self, Node a, Node b) = 0;
+		virtual T signed_greater_equal(Node self, Node a, Node b) = 0;
+		virtual T unsigned_greater_than(Node self, Node a, Node b) = 0;
+		virtual T unsigned_greater_equal(Node self, Node a, Node b) = 0;
+		virtual T logical_shift_left(Node self, Node a, Node b) = 0;
+		virtual T logical_shift_right(Node self, Node a, Node b) = 0;
+		virtual T arithmetic_shift_right(Node self, Node a, Node b) = 0;
+		virtual T mux(Node self, Node a, Node b, Node s) = 0;
+		virtual T pmux(Node self, Node a, Node b, Node s) = 0;
+		virtual T constant(Node self, RTLIL::Const value) = 0;
+		virtual T input(Node self, IdString name) = 0;
+		virtual T state(Node self, IdString name) = 0;
+		virtual T memory_read(Node self, Node mem, Node addr) = 0;
+		virtual T memory_write(Node self, Node mem, Node addr, Node data) = 0;
+		virtual T undriven(Node self, int width) = 0;
+	};
+	// DefaultVisitor provides defaults for all visitor methods which just calls default_handler
+	template<class T> struct DefaultVisitor : public AbstractVisitor<T> {
+		virtual T default_handler(Node self) = 0;
+		T buf(Node self, Node) override { return default_handler(self); }
+		T slice(Node self, Node, int, int) override { return default_handler(self); }
+		T zero_extend(Node self, Node, int) override { return default_handler(self); }
+		T sign_extend(Node self, Node, int) override { return default_handler(self); }
+		T concat(Node self, Node, Node) override { return default_handler(self); }
+		T add(Node self, Node, Node) override { return default_handler(self); }
+		T sub(Node self, Node, Node) override { return default_handler(self); }
+		T mul(Node self, Node, Node) override { return default_handler(self); }
+		T unsigned_div(Node self, Node, Node) override { return default_handler(self); }
+		T unsigned_mod(Node self, Node, Node) override { return default_handler(self); }
+		T bitwise_and(Node self, Node, Node) override { return default_handler(self); }
+		T bitwise_or(Node self, Node, Node) override { return default_handler(self); }
+		T bitwise_xor(Node self, Node, Node) override { return default_handler(self); }
+		T bitwise_not(Node self, Node) override { return default_handler(self); }
+		T unary_minus(Node self, Node) override { return default_handler(self); }
+		T reduce_and(Node self, Node) override { return default_handler(self); }
+		T reduce_or(Node self, Node) override { return default_handler(self); }
+		T reduce_xor(Node self, Node) override { return default_handler(self); }
+		T equal(Node self, Node, Node) override { return default_handler(self); }
+		T not_equal(Node self, Node, Node) override { return default_handler(self); }
+		T signed_greater_than(Node self, Node, Node) override { return default_handler(self); }
+		T signed_greater_equal(Node self, Node, Node) override { return default_handler(self); }
+		T unsigned_greater_than(Node self, Node, Node) override { return default_handler(self); }
+		T unsigned_greater_equal(Node self, Node, Node) override { return default_handler(self); }
+		T logical_shift_left(Node self, Node, Node) override { return default_handler(self); }
+		T logical_shift_right(Node self, Node, Node) override { return default_handler(self); }
+		T arithmetic_shift_right(Node self, Node, Node) override { return default_handler(self); }
+		T mux(Node self, Node, Node, Node) override { return default_handler(self); }
+		T pmux(Node self, Node, Node, Node) override { return default_handler(self); }
+		T constant(Node self, RTLIL::Const) override { return default_handler(self); }
+		T input(Node self, IdString) override { return default_handler(self); }
+		T state(Node self, IdString) override { return default_handler(self); }
+		T memory_read(Node self, Node, Node) override { return default_handler(self); }
+		T memory_write(Node self, Node, Node, Node) override { return default_handler(self); }
+		T undriven(Node self, int) override { return default_handler(self); }
 	};
+	// a factory is used to modify a FunctionalIR. it creates new nodes and allows for some modification of existing nodes.
 	class Factory {
 		FunctionalIR &_ir;
 		friend class FunctionalIR;
@@ -243,19 +375,29 @@ class FunctionalIR {
 		Node add(NodeData &&fn, Sort &&sort, std::initializer_list<Node> args) {
 			Graph::Ref ref = _ir._graph.add(std::move(fn), {std::move(sort)});
 			for (auto arg : args)
-				ref.append_arg(Graph::Ref(arg));
+				ref.append_arg(Graph::ConstRef(arg));
 			return Node(ref);
 		}
+		Graph::Ref mutate(Node n) {
+			return _ir._graph[n._ref.index()];
+		}
 		void check_basic_binary(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && a.sort() == b.sort()); }
 		void check_shift(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && b.sort().is_signal()); }
 		void check_unary(Node const &a) { log_assert(a.sort().is_signal()); }
 	public:
 		Node slice(Node a, int, int offset, int out_width) {
 			log_assert(a.sort().is_signal() && offset + out_width <= a.sort().width());
+			if(offset == 0 && out_width == a.width())
+				return a;
 			return add(NodeData(Fn::slice, offset), Sort(out_width), {a});
 		}
 		Node extend(Node a, int, int out_width, bool is_signed) {
-			log_assert(a.sort().is_signal() && a.sort().width() < out_width);
+			int in_width = a.sort().width();
+			log_assert(a.sort().is_signal());
+			if(in_width == out_width)
+				return a;
+			if(in_width < out_width)
+				return slice(a, in_width, 0, out_width);
 			if(is_signed)
 				return add(Fn::sign_extend, Sort(out_width), {a});
 			else
@@ -275,9 +417,24 @@ class FunctionalIR {
 		Node bitwise_xor(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::bitwise_xor, a.sort(), {a, b}); }
 		Node bitwise_not(Node a, int) { check_unary(a); return add(Fn::bitwise_not, a.sort(), {a}); }
 		Node unary_minus(Node a, int) { check_unary(a); return add(Fn::unary_minus, a.sort(), {a}); }
-		Node reduce_and(Node a, int) { check_unary(a); return add(Fn::reduce_and, Sort(1), {a}); }
-		Node reduce_or(Node a, int) { check_unary(a); return add(Fn::reduce_or, Sort(1), {a}); }
-		Node reduce_xor(Node a, int) { check_unary(a); return add(Fn::reduce_xor, Sort(1), {a}); }
+		Node reduce_and(Node a, int) {
+			check_unary(a);
+			if(a.width() == 1)
+				return a;
+			return add(Fn::reduce_and, Sort(1), {a});
+		}
+		Node reduce_or(Node a, int) {
+			check_unary(a);
+			if(a.width() == 1)
+				return a;
+			return add(Fn::reduce_or, Sort(1), {a});
+		}
+		Node reduce_xor(Node a, int) { 
+			check_unary(a);
+			if(a.width() == 1)
+				return a;
+			return add(Fn::reduce_xor, Sort(1), {a});
+		}
 		Node equal(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::equal, Sort(1), {a, b}); }
 		Node not_equal(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::not_equal, Sort(1), {a, b}); }
 		Node signed_greater_than(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::signed_greater_than, Sort(1), {a, b}); }
@@ -313,7 +470,7 @@ class FunctionalIR {
 		void update_pending(Node node, Node value) {
 			log_assert(node._ref.function() == Fn::buf && node._ref.size() == 0);
 			log_assert(node.sort() == value.sort());
-			node._ref.append_arg(value._ref);
+			mutate(node).append_arg(value._ref);
 		} 
 		Node input(IdString name, int width) {
 			_ir.add_input(name, Sort(width));
@@ -333,7 +490,7 @@ class FunctionalIR {
 		Node multiple(vector<Node> args, int width) {
 			auto node = add(Fn::multiple, Sort(width), {});
 			for(const auto &arg : args)
-				node._ref.append_arg(arg._ref);
+				mutate(node).append_arg(arg._ref);
 			return node;
 		}
 		Node undriven(int width) {
@@ -341,18 +498,18 @@ class FunctionalIR {
 		}
 		void declare_output(Node node, IdString name, int width) {
 			_ir.add_output(name, Sort(width));
-			node._ref.assign_key({name, false});
+			mutate(node).assign_key({name, false});
 		}
 		void declare_state(Node node, IdString name, int width) {
 			_ir.add_state(name, Sort(width));
-			node._ref.assign_key({name, true});
+			mutate(node).assign_key({name, true});
 		}
 		void declare_state_memory(Node node, IdString name, int addr_width, int data_width) {
 			_ir.add_state(name, Sort(addr_width, data_width));
-			node._ref.assign_key({name, true});
+			mutate(node).assign_key({name, true});
 		}
 		void suggest_name(Node node, IdString name) {
-			node._ref.sparse_attr() = name;
+			mutate(node).sparse_attr() = name;
 		}
 	};
 	static FunctionalIR from_module(Module *module);

From 7f8f21b980770f2771aae61f830a5784fc16fbe6 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Wed, 17 Jul 2024 12:42:24 +0100
Subject: [PATCH 412/499] remove widths parameters from FunctionalIR factory
 methods and from functionalir.cc

---
 kernel/functionalir.cc | 391 +++++++++++++++++++----------------------
 kernel/functionalir.h  |  66 ++++---
 2 files changed, 216 insertions(+), 241 deletions(-)

diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc
index 9b8076a0ef7..48baad7168b 100644
--- a/kernel/functionalir.cc
+++ b/kernel/functionalir.cc
@@ -98,87 +98,75 @@ std::string FunctionalIR::Node::to_string(std::function<std::string(Node)> np)
 	return visit(PrintVisitor(np));
 }
 
-template <class T, class Factory>
 class CellSimplifier {
-	Factory &factory;
-	T reduce_shift_width(T b, int b_width, int y_width, int &reduced_b_width) {
+	using Node = FunctionalIR::Node;
+	FunctionalIR::Factory &factory;
+	Node reduce_shift_width(Node b, int y_width) {
 		log_assert(y_width > 0);
 		int new_width = ceil_log2(y_width + 1);
-		if (b_width <= new_width) {
-			reduced_b_width = b_width;
+		if (b.width() <= new_width) {
 			return b;
 		} else {
-			reduced_b_width = new_width;
-			T lower_b = factory.slice(b, b_width, 0, new_width);
-			T overflow = factory.unsigned_greater_than(b, factory.constant(RTLIL::Const(y_width, b_width)), b_width);
-			return factory.mux(lower_b, factory.constant(RTLIL::Const(y_width, new_width)), overflow, new_width);
+			Node lower_b = factory.slice(b, 0, new_width);
+			Node overflow = factory.unsigned_greater_than(b, factory.constant(RTLIL::Const(y_width, b.width())));
+			return factory.mux(lower_b, factory.constant(RTLIL::Const(y_width, new_width)), overflow);
 		}
 	}
-	T sign(T a, int a_width) {
-		return factory.slice(a, a_width, a_width - 1, 1);
+	Node sign(Node a) {
+		return factory.slice(a, a.width() - 1, 1);
 	}
-	T neg_if(T a, int a_width, T s) {
-		return factory.mux(a, factory.unary_minus(a, a_width), s, a_width);
+	Node neg_if(Node a, Node s) {
+		return factory.mux(a, factory.unary_minus(a), s);
 	}
-	T abs(T a, int a_width) {
-		return neg_if(a, a_width, sign(a, a_width));
+	Node abs(Node a) {
+		return neg_if(a, sign(a));
 	}
 public:
-	T extend(T a, int in_width, int out_width, bool is_signed) {
-		if(in_width == out_width)
-			return a;
-		if(in_width > out_width)
-			return factory.slice(a, in_width, 0, out_width);
-		return factory.extend(a, in_width, out_width, is_signed);
-	}
-	T logical_shift_left(T a, T b, int y_width, int b_width) {
-		int reduced_b_width;
-		T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width);
-		return factory.logical_shift_left(a, reduced_b, y_width, reduced_b_width);
+	Node logical_shift_left(Node a, Node b) {
+		Node reduced_b = reduce_shift_width(b, a.width());
+		return factory.logical_shift_left(a, reduced_b);
 	}
-	T logical_shift_right(T a, T b, int y_width, int b_width) {
-		int reduced_b_width;
-		T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width);
-		return factory.logical_shift_right(a, reduced_b, y_width, reduced_b_width);
+	Node logical_shift_right(Node a, Node b) {
+		Node reduced_b = reduce_shift_width(b, a.width());
+		return factory.logical_shift_right(a, reduced_b);
 	}
-	T arithmetic_shift_right(T a, T b, int y_width, int b_width) {
-		int reduced_b_width;
-		T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width);
-		return factory.arithmetic_shift_right(a, reduced_b, y_width, reduced_b_width);
+	Node arithmetic_shift_right(Node a, Node b) {
+		Node reduced_b = reduce_shift_width(b, a.width());
+		return factory.arithmetic_shift_right(a, reduced_b);
 	}
-	T bitwise_mux(T a, T b, T s, int width) {
-		T aa = factory.bitwise_and(a, factory.bitwise_not(s, width), width);
-		T bb = factory.bitwise_and(b, s, width);
-		return factory.bitwise_or(aa, bb, width);
+	Node bitwise_mux(Node a, Node b, Node s) {
+		Node aa = factory.bitwise_and(a, factory.bitwise_not(s));
+		Node bb = factory.bitwise_and(b, s);
+		return factory.bitwise_or(aa, bb);
 	}
-	CellSimplifier(Factory &f) : factory(f) {}
+	CellSimplifier(FunctionalIR::Factory &f) : factory(f) {}
 private:
-	T handle_pow(T a0, int a_width, T b, int b_width, int y_width, bool is_signed) {
-		T a = extend(a0, a_width, y_width, is_signed);
-		T r = factory.constant(Const(1, y_width));
-		for(int i = 0; i < b_width; i++) {
-			T b_bit = factory.slice(b, b_width, i, 1);
-			r = factory.mux(r, factory.mul(r, a, y_width), b_bit, y_width);
-			a = factory.mul(a, a, y_width);
+	Node handle_pow(Node a0, Node b, int y_width, bool is_signed) {
+		Node a = factory.extend(a0, y_width, is_signed);
+		Node r = factory.constant(Const(1, y_width));
+		for(int i = 0; i < b.width(); i++) {
+			Node b_bit = factory.slice(b, i, 1);
+			r = factory.mux(r, factory.mul(r, a), b_bit);
+			a = factory.mul(a, a);
 		}
 		if (is_signed) {
-			T a_ge_1 = factory.unsigned_greater_than(abs(a0, a_width), factory.constant(Const(1, a_width)), a_width);
-			T zero_result = factory.bitwise_and(a_ge_1, sign(b, b_width), 1);
-			r = factory.mux(r, factory.constant(Const(0, y_width)), zero_result, y_width);
+			Node a_ge_1 = factory.unsigned_greater_than(abs(a0), factory.constant(Const(1, a0.width())));
+			Node zero_result = factory.bitwise_and(a_ge_1, sign(b));
+			r = factory.mux(r, factory.constant(Const(0, y_width)), zero_result);
 		}
 		return r;
 	}
-	T handle_bmux(T a, T s, int a_width, int a_offset, int width, int s_width, int sn) {
+	Node handle_bmux(Node a, Node s, int a_offset, int width, int sn) {
 		if(sn < 1)
-			return factory.slice(a, a_width, a_offset, width);
+			return factory.slice(a, a_offset, width);
 		else {
-			T y0 = handle_bmux(a, s, a_width, a_offset, width, s_width, sn - 1);
-			T y1 = handle_bmux(a, s, a_width, a_offset + (width << (sn - 1)), width, s_width, sn - 1);
-			return factory.mux(y0, y1, factory.slice(s, s_width, sn - 1, 1), width);
+			Node y0 = handle_bmux(a, s, a_offset, width, sn - 1);
+			Node y1 = handle_bmux(a, s, a_offset + (width << (sn - 1)), width, sn - 1);
+			return factory.mux(y0, y1, factory.slice(s, sn - 1, 1));
 		}
 	}
 public:
-	T handle(IdString cellType, dict<IdString, Const> parameters, dict<IdString, T> inputs)
+	Node handle(IdString cellType, dict<IdString, Const> parameters, dict<IdString, Node> inputs)
 	{
 		int a_width = parameters.at(ID(A_WIDTH), Const(-1)).as_int();
 		int b_width = parameters.at(ID(B_WIDTH), Const(-1)).as_int();
@@ -187,208 +175,202 @@ class CellSimplifier {
 		bool b_signed = parameters.at(ID(B_SIGNED), Const(0)).as_bool();
 		if(cellType.in({ID($add), ID($sub), ID($and), ID($or), ID($xor), ID($xnor), ID($mul)})){
 			bool is_signed = a_signed && b_signed;
-			T a = extend(inputs.at(ID(A)), a_width, y_width, is_signed);
-			T b = extend(inputs.at(ID(B)), b_width, y_width, is_signed);
+			Node a = factory.extend(inputs.at(ID(A)), y_width, is_signed);
+			Node b = factory.extend(inputs.at(ID(B)), y_width, is_signed);
 			if(cellType == ID($add))
-				return factory.add(a, b, y_width);
+				return factory.add(a, b);
 			else if(cellType == ID($sub))
-				return factory.sub(a, b, y_width);
+				return factory.sub(a, b);
 			else if(cellType == ID($mul))
-				return factory.mul(a, b, y_width);
+				return factory.mul(a, b);
 			else if(cellType == ID($and))
-				return factory.bitwise_and(a, b, y_width);
+				return factory.bitwise_and(a, b);
 			else if(cellType == ID($or))
-				return factory.bitwise_or(a, b, y_width);
+				return factory.bitwise_or(a, b);
 			else if(cellType == ID($xor))
-				return factory.bitwise_xor(a, b, y_width);
+				return factory.bitwise_xor(a, b);
 			else if(cellType == ID($xnor))
-				return factory.bitwise_not(factory.bitwise_xor(a, b, y_width), y_width);
+				return factory.bitwise_not(factory.bitwise_xor(a, b));
 			else
 				log_abort();
 		}else if(cellType.in({ID($eq), ID($ne), ID($eqx), ID($nex), ID($le), ID($lt), ID($ge), ID($gt)})){
 			bool is_signed = a_signed && b_signed;
 			int width = max(a_width, b_width);
-			T a = extend(inputs.at(ID(A)), a_width, width, is_signed);
-			T b = extend(inputs.at(ID(B)), b_width, width, is_signed);
+			Node a = factory.extend(inputs.at(ID(A)), width, is_signed);
+			Node b = factory.extend(inputs.at(ID(B)), width, is_signed);
 			if(cellType.in({ID($eq), ID($eqx)}))
-				return extend(factory.equal(a, b, width), 1, y_width, false);
+				return factory.extend(factory.equal(a, b), y_width, false);
 			else if(cellType.in({ID($ne), ID($nex)}))
-				return extend(factory.not_equal(a, b, width), 1, y_width, false);
+				return factory.extend(factory.not_equal(a, b), y_width, false);
 			else if(cellType == ID($lt))
-				return extend(is_signed ? factory.signed_greater_than(b, a, width) : factory.unsigned_greater_than(b, a, width), 1, y_width, false);
+				return factory.extend(is_signed ? factory.signed_greater_than(b, a) : factory.unsigned_greater_than(b, a), y_width, false);
 			else if(cellType == ID($le))
-				return extend(is_signed ? factory.signed_greater_equal(b, a, width) : factory.unsigned_greater_equal(b, a, width), 1, y_width, false);
+				return factory.extend(is_signed ? factory.signed_greater_equal(b, a) : factory.unsigned_greater_equal(b, a), y_width, false);
 			else if(cellType == ID($gt))
-				return extend(is_signed ? factory.signed_greater_than(a, b, width) : factory.unsigned_greater_than(a, b, width), 1, y_width, false);
+				return factory.extend(is_signed ? factory.signed_greater_than(a, b) : factory.unsigned_greater_than(a, b), y_width, false);
 			else if(cellType == ID($ge))
-				return extend(is_signed ? factory.signed_greater_equal(a, b, width) : factory.unsigned_greater_equal(a, b, width), 1, y_width, false);
+				return factory.extend(is_signed ? factory.signed_greater_equal(a, b) : factory.unsigned_greater_equal(a, b), y_width, false);
 			else
 				log_abort();
 		}else if(cellType.in({ID($logic_or), ID($logic_and)})){
-			T a = factory.reduce_or(inputs.at(ID(A)), a_width);
-			T b = factory.reduce_or(inputs.at(ID(B)), b_width);
-			T y = cellType == ID($logic_and) ? factory.bitwise_and(a, b, 1) : factory.bitwise_or(a, b, 1);
-			return extend(y, 1, y_width, false);
+			Node a = factory.reduce_or(inputs.at(ID(A)));
+			Node b = factory.reduce_or(inputs.at(ID(B)));
+			Node y = cellType == ID($logic_and) ? factory.bitwise_and(a, b) : factory.bitwise_or(a, b);
+			return factory.extend(y, y_width, false);
 		}else if(cellType == ID($not)){
-			T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed);
-			return factory.bitwise_not(a, y_width);
+			Node a = factory.extend(inputs.at(ID(A)), y_width, a_signed);
+			return factory.bitwise_not(a);
 		}else if(cellType == ID($pos)){
-			return extend(inputs.at(ID(A)), a_width, y_width, a_signed);
+			return factory.extend(inputs.at(ID(A)), y_width, a_signed);
 		}else if(cellType == ID($neg)){
-			T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed);
-			return factory.unary_minus(a, y_width);
+			Node a = factory.extend(inputs.at(ID(A)), y_width, a_signed);
+			return factory.unary_minus(a);
 		}else if(cellType == ID($logic_not)){
-			T a = factory.reduce_or(inputs.at(ID(A)), a_width);
-			T y = factory.bitwise_not(a, 1);
-			return extend(y, 1, y_width, false);
+			Node a = factory.reduce_or(inputs.at(ID(A)));
+			Node y = factory.bitwise_not(a);
+			return factory.extend(y, y_width, false);
 		}else if(cellType.in({ID($reduce_or), ID($reduce_bool)})){
-			T a = factory.reduce_or(inputs.at(ID(A)), a_width);
-			return extend(a, 1, y_width, false);
+			Node a = factory.reduce_or(inputs.at(ID(A)));
+			return factory.extend(a, y_width, false);
 		}else if(cellType == ID($reduce_and)){
-			T a = factory.reduce_and(inputs.at(ID(A)), a_width);
-			return extend(a, 1, y_width, false);
+			Node a = factory.reduce_and(inputs.at(ID(A)));
+			return factory.extend(a, y_width, false);
 		}else if(cellType.in({ID($reduce_xor), ID($reduce_xnor)})){
-			T a = factory.reduce_xor(inputs.at(ID(A)), a_width);
-			T y = cellType == ID($reduce_xnor) ? factory.bitwise_not(a, 1) : a;
-			return extend(y, 1, y_width, false);
+			Node a = factory.reduce_xor(inputs.at(ID(A)));
+			Node y = cellType == ID($reduce_xnor) ? factory.bitwise_not(a) : a;
+			return factory.extend(y, y_width, false);
 		}else if(cellType == ID($shl) || cellType == ID($sshl)){
-			T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed);
-			T b = inputs.at(ID(B));
-			return logical_shift_left(a, b, y_width, b_width);
+			Node a = factory.extend(inputs.at(ID(A)), y_width, a_signed);
+			Node b = inputs.at(ID(B));
+			return logical_shift_left(a, b);
 		}else if(cellType == ID($shr) || cellType == ID($sshr)){
 			int width = max(a_width, y_width);
-			T a = extend(inputs.at(ID(A)), a_width, width, a_signed);
-			T b = inputs.at(ID(B));
-			T y = a_signed && cellType == ID($sshr) ?
-				arithmetic_shift_right(a, b, width, b_width) :
-				logical_shift_right(a, b, width, b_width);
-			return extend(y, width, y_width, a_signed);
+			Node a = factory.extend(inputs.at(ID(A)), width, a_signed);
+			Node b = inputs.at(ID(B));
+			Node y = a_signed && cellType == ID($sshr) ?
+				arithmetic_shift_right(a, b) :
+				logical_shift_right(a, b);
+			return factory.extend(y, y_width, a_signed);
 		}else if(cellType == ID($shiftx) || cellType == ID($shift)){
 			int width = max(a_width, y_width);
-			T a = extend(inputs.at(ID(A)), a_width, width, cellType == ID($shift) && a_signed);
-			T b = inputs.at(ID(B));
-			T shr = logical_shift_right(a, b, width, b_width);
+			Node a = factory.extend(inputs.at(ID(A)), width, cellType == ID($shift) && a_signed);
+			Node b = inputs.at(ID(B));
+			Node shr = logical_shift_right(a, b);
 			if(b_signed) {
-				T sign_b = sign(b, b_width);
-				T shl = logical_shift_left(a, factory.unary_minus(b, b_width), width, b_width);
-				T y = factory.mux(shr, shl, sign_b, width);
-				return extend(y, width, y_width, false);
+				Node shl = logical_shift_left(a, factory.unary_minus(b));
+				Node y = factory.mux(shr, shl, sign(b));
+				return factory.extend(y, y_width, false);
 			} else {
-				return extend(shr, width, y_width, false);
+				return factory.extend(shr, y_width, false);
 			}
 		}else if(cellType == ID($mux)){
-			int width = parameters.at(ID(WIDTH)).as_int();
-			return factory.mux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S)), width);
+			return factory.mux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S)));
 		}else if(cellType == ID($pmux)){
-			int width = parameters.at(ID(WIDTH)).as_int();
-			int s_width = parameters.at(ID(S_WIDTH)).as_int();
-			return factory.pmux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S)), width, s_width);
+			return factory.pmux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S)));
 		}else if(cellType == ID($concat)){
-			T a = inputs.at(ID(A));
-			T b = inputs.at(ID(B));
-			return factory.concat(a, a_width, b, b_width);
+			Node a = inputs.at(ID(A));
+			Node b = inputs.at(ID(B));
+			return factory.concat(a, b);
 		}else if(cellType == ID($slice)){
 			int offset = parameters.at(ID(OFFSET)).as_int();
-			T a = inputs.at(ID(A));
-			return factory.slice(a, a_width, offset, y_width);
+			Node a = inputs.at(ID(A));
+			return factory.slice(a, offset, y_width);
 		}else if(cellType.in({ID($div), ID($mod), ID($divfloor), ID($modfloor)})) {
 			int width = max(a_width, b_width);
 			bool is_signed = a_signed && b_signed;
-			T a = extend(inputs.at(ID(A)), a_width, width, is_signed);
-			T b = extend(inputs.at(ID(B)), b_width, width, is_signed);
+			Node a = factory.extend(inputs.at(ID(A)), width, is_signed);
+			Node b = factory.extend(inputs.at(ID(B)), width, is_signed);
 			if(is_signed) {
 				if(cellType == ID($div)) {
 					// divide absolute values, then flip the sign if input signs differ
 					// but extend the width first, to handle the case (most negative value) / (-1)
-					T abs_y = factory.unsigned_div(abs(a, width), abs(b, width), width);
-					T out_sign = factory.not_equal(sign(a, width), sign(b, width), 1);
-					return neg_if(extend(abs_y, width, y_width, false), y_width, out_sign);
+					Node abs_y = factory.unsigned_div(abs(a), abs(b));
+					Node out_sign = factory.not_equal(sign(a), sign(b));
+					return neg_if(factory.extend(abs_y, y_width, false), out_sign);
 				} else if(cellType == ID($mod)) {
 					// similar to division but output sign == divisor sign
-					T abs_y = factory.unsigned_mod(abs(a, width), abs(b, width), width);
-					return neg_if(extend(abs_y, width, y_width, false), y_width, sign(a, width));
+					Node abs_y = factory.unsigned_mod(abs(a), abs(b));
+					return neg_if(factory.extend(abs_y, y_width, false), sign(a));
 				} else if(cellType == ID($divfloor)) {
 					// if b is negative, flip both signs so that b is positive
-					T b_sign = sign(b, width);
-					T a1 = neg_if(a, width, b_sign);
-					T b1 = neg_if(b, width, b_sign);
+					Node b_sign = sign(b);
+					Node a1 = neg_if(a, b_sign);
+					Node b1 = neg_if(b, b_sign);
 					// if a is now negative, calculate ~((~a) / b) = -((-a - 1) / b + 1)
 					// which equals the negative of (-a) / b with rounding up rather than down
 					// note that to handle the case where a = most negative value properly,
-					// we have to calculate a1_sign from the original values rather than using sign(a1, width)
-					T a1_sign = factory.bitwise_and(factory.not_equal(sign(a, width), sign(b, width), 1), factory.reduce_or(a, width), 1);
-					T a2 = factory.mux(a1, factory.bitwise_not(a1, width), a1_sign, width);
-					T y1 = factory.unsigned_div(a2, b1, width);
-					T y2 = extend(y1, width, y_width, false);
-					return factory.mux(y2, factory.bitwise_not(y2, y_width), a1_sign, y_width);
+					// we have to calculate a1_sign from the original values rather than using sign(a1)
+					Node a1_sign = factory.bitwise_and(factory.not_equal(sign(a), sign(b)), factory.reduce_or(a));
+					Node a2 = factory.mux(a1, factory.bitwise_not(a1), a1_sign);
+					Node y1 = factory.unsigned_div(a2, b1);
+					Node y2 = factory.extend(y1, y_width, false);
+					return factory.mux(y2, factory.bitwise_not(y2), a1_sign);
 				} else if(cellType == ID($modfloor)) {
 					// calculate |a| % |b| and then subtract from |b| if input signs differ and the remainder is non-zero
-					T abs_b = abs(b, width);
-					T abs_y = factory.unsigned_mod(abs(a, width), abs_b, width);
-					T flip_y = factory.bitwise_and(factory.bitwise_xor(sign(a, width), sign(b, width), 1), factory.reduce_or(abs_y, width), 1);
-					T y_flipped = factory.mux(abs_y, factory.sub(abs_b, abs_y, width), flip_y, width);
+					Node abs_b = abs(b);
+					Node abs_y = factory.unsigned_mod(abs(a), abs_b);
+					Node flip_y = factory.bitwise_and(factory.bitwise_xor(sign(a), sign(b)), factory.reduce_or(abs_y));
+					Node y_flipped = factory.mux(abs_y, factory.sub(abs_b, abs_y), flip_y);
 					// since y_flipped is strictly less than |b|, the top bit is always 0 and we can just sign extend the flipped result
-					T y = neg_if(y_flipped, width, sign(b, b_width));
-					return extend(y, width, y_width, true);
+					Node y = neg_if(y_flipped, sign(b));
+					return factory.extend(y, y_width, true);
 				} else
 					log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str());
 			} else {
 				if(cellType.in({ID($mod), ID($modfloor)}))
-					return extend(factory.unsigned_mod(a, b, width), width, y_width, false);
+					return factory.extend(factory.unsigned_mod(a, b), y_width, false);
 				else
-					return extend(factory.unsigned_div(a, b, width), width, y_width, false);
+					return factory.extend(factory.unsigned_div(a, b), y_width, false);
 			}
 		} else if(cellType == ID($pow)) {
-			return handle_pow(inputs.at(ID(A)), a_width, inputs.at(ID(B)), b_width, y_width, a_signed && b_signed);
+			return handle_pow(inputs.at(ID(A)), inputs.at(ID(B)), y_width, a_signed && b_signed);
 		} else if (cellType == ID($lut)) {
 			int width = parameters.at(ID(WIDTH)).as_int();
 			Const lut_table = parameters.at(ID(LUT));
 			lut_table.extu(1 << width);
-			return handle_bmux(factory.constant(lut_table), inputs.at(ID(A)), 1 << width, 0, 1, width, width);
+			return handle_bmux(factory.constant(lut_table), inputs.at(ID(A)), 0, 1, width);
 		} else if (cellType == ID($bwmux)) {
-			int width = parameters.at(ID(WIDTH)).as_int();
-			T a = inputs.at(ID(A));
-			T b = inputs.at(ID(B));
-			T s = inputs.at(ID(S));
+			Node a = inputs.at(ID(A));
+			Node b = inputs.at(ID(B));
+			Node s = inputs.at(ID(S));
 			return factory.bitwise_or(
-				factory.bitwise_and(a, factory.bitwise_not(s, width), width),
-				factory.bitwise_and(b, s, width), width);
+				factory.bitwise_and(a, factory.bitwise_not(s)),
+				factory.bitwise_and(b, s));
 		} else if (cellType == ID($bweqx)) {
-			int width = parameters.at(ID(WIDTH)).as_int();
-			T a = inputs.at(ID(A));
-			T b = inputs.at(ID(B));
-			return factory.bitwise_not(factory.bitwise_xor(a, b, width), width);
+			Node a = inputs.at(ID(A));
+			Node b = inputs.at(ID(B));
+			return factory.bitwise_not(factory.bitwise_xor(a, b));
 		} else if(cellType == ID($bmux)) {
 			int width = parameters.at(ID(WIDTH)).as_int();
 			int s_width = parameters.at(ID(S_WIDTH)).as_int();
-			return handle_bmux(inputs.at(ID(A)), inputs.at(ID(S)), width << s_width, 0, width, s_width, s_width);
+			return handle_bmux(inputs.at(ID(A)), inputs.at(ID(S)), 0, width, s_width);
 		} else if(cellType == ID($demux)) {
 			int width = parameters.at(ID(WIDTH)).as_int();
 			int s_width = parameters.at(ID(S_WIDTH)).as_int();
 			int y_width = width << s_width;
 			int b_width = ceil_log2(y_width + 1);
-			T a = extend(inputs.at(ID(A)), width, y_width, false);
-			T s = factory.extend(inputs.at(ID(S)), s_width, b_width, false);
-			T b = factory.mul(s, factory.constant(Const(width, b_width)), b_width);
-			return factory.logical_shift_left(a, b, y_width, b_width);
+			Node a = factory.extend(inputs.at(ID(A)), y_width, false);
+			Node s = factory.extend(inputs.at(ID(S)), b_width, false);
+			Node b = factory.mul(s, factory.constant(Const(width, b_width)));
+			return factory.logical_shift_left(a, b);
 		} else {
 			log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str());
 		}
 	}
 };
 
-template <class T, class Factory>
 class FunctionalIRConstruction {
+	using Node = FunctionalIR::Node;
 	std::deque<DriveSpec> queue;
-	dict<DriveSpec, T> graph_nodes;
+	dict<DriveSpec, Node> graph_nodes;
 	idict<Cell *> cells;
 	DriverMap driver_map;
-	Factory& factory;
-	CellSimplifier<T, Factory> simplifier;
+	FunctionalIR::Factory& factory;
+	CellSimplifier simplifier;
 	vector<Mem> memories_vector;
 	dict<Cell*, Mem*> memories;
 
-	T enqueue(DriveSpec const &spec)
+	Node enqueue(DriveSpec const &spec)
 	{
 		auto it = graph_nodes.find(spec);
 		if(it == graph_nodes.end()){
@@ -400,7 +382,7 @@ class FunctionalIRConstruction {
 			return it->second;
 	}
 public:
-	FunctionalIRConstruction(Factory &f) : factory(f), simplifier(f) {}
+	FunctionalIRConstruction(FunctionalIR::Factory &f) : factory(f), simplifier(f) {}
 	void add_module(Module *module)
 	{
 		driver_map.add(module);
@@ -410,7 +392,7 @@ class FunctionalIRConstruction {
 		}
 		for (auto wire : module->wires()) {
 			if (wire->port_output) {
-				T node = enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width)));
+				Node node = enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width)));
 				factory.declare_output(node, wire->name, wire->width);
 			}
 		}
@@ -420,37 +402,34 @@ class FunctionalIRConstruction {
 				memories[mem.cell] = &mem;
 		}
 	}
-	T concatenate_read_results(Mem *, vector<T> results)
+	Node concatenate_read_results(Mem *, vector<Node> results)
 	{
         /* TODO: write code to check that this is ok to do */
 		if(results.size() == 0)
 			return factory.undriven(0);
-		T node = results[0];
-		int size = results[0].width();
-		for(size_t i = 1; i < results.size(); i++) {
-			node = factory.concat(node, size, results[i], results[i].width());
-			size += results[i].width();
-		}
+		Node node = results[0];
+		for(size_t i = 1; i < results.size(); i++)
+			node = factory.concat(node, results[i]);
 		return node;
 	}
-	T handle_memory(Mem *mem)
+	Node handle_memory(Mem *mem)
 	{
-		vector<T> read_results;
+		vector<Node> read_results;
 		int addr_width = ceil_log2(mem->size);
 		int data_width = mem->width;
-		T node = factory.state_memory(mem->cell->name, addr_width, data_width);
+		Node node = factory.state_memory(mem->cell->name, addr_width, data_width);
 		for (auto &rd : mem->rd_ports) {
 			log_assert(!rd.clk_enable);
-			T addr = enqueue(driver_map(DriveSpec(rd.addr)));
-			read_results.push_back(factory.memory_read(node, addr, addr_width, data_width));
+			Node addr = enqueue(driver_map(DriveSpec(rd.addr)));
+			read_results.push_back(factory.memory_read(node, addr));
 		}
 		for (auto &wr : mem->wr_ports) {
-			T en = enqueue(driver_map(DriveSpec(wr.en)));
-			T addr = enqueue(driver_map(DriveSpec(wr.addr)));
-			T new_data = enqueue(driver_map(DriveSpec(wr.data)));
-			T old_data = factory.memory_read(node, addr, addr_width, data_width);
-			T wr_data = simplifier.bitwise_mux(old_data, new_data, en, data_width);
-			node = factory.memory_write(node, addr, wr_data, addr_width, data_width);
+			Node en = enqueue(driver_map(DriveSpec(wr.en)));
+			Node addr = enqueue(driver_map(DriveSpec(wr.addr)));
+			Node new_data = enqueue(driver_map(DriveSpec(wr.data)));
+			Node old_data = factory.memory_read(node, addr);
+			Node wr_data = simplifier.bitwise_mux(old_data, new_data, en);
+			node = factory.memory_write(node, addr, wr_data);
 		}
 		factory.declare_state_memory(node, mem->cell->name, addr_width, data_width);
 		return concatenate_read_results(mem, read_results);
@@ -459,16 +438,13 @@ class FunctionalIRConstruction {
 	{
 		for (; !queue.empty(); queue.pop_front()) {
 			DriveSpec spec = queue.front();
-			T pending = graph_nodes.at(spec);
+			Node pending = graph_nodes.at(spec);
 
 			if (spec.chunks().size() > 1) {
 				auto chunks = spec.chunks();
-				T node = enqueue(chunks[0]);
-				int width = chunks[0].size();
-				for(size_t i = 1; i < chunks.size(); i++) {
-					node = factory.concat(node, width, enqueue(chunks[i]), chunks[i].size());
-					width += chunks[i].size();
-				}
+				Node node = enqueue(chunks[0]);
+				for(size_t i = 1; i < chunks.size(); i++)
+					node = factory.concat(node, enqueue(chunks[i]));
 				factory.update_pending(pending, node);
 			} else if (spec.chunks().size() == 1) {
 				DriveChunk chunk = spec.chunks()[0];
@@ -476,18 +452,18 @@ class FunctionalIRConstruction {
 					DriveChunkWire wire_chunk = chunk.wire();
 					if (wire_chunk.is_whole()) {
 						if (wire_chunk.wire->port_input) {
-							T node = factory.input(wire_chunk.wire->name, wire_chunk.width);
+							Node node = factory.input(wire_chunk.wire->name, wire_chunk.width);
 							factory.suggest_name(node, wire_chunk.wire->name);
 							factory.update_pending(pending, node);
 						} else {
 							DriveSpec driver = driver_map(DriveSpec(wire_chunk));
-							T node = enqueue(driver);
+							Node node = enqueue(driver);
 							factory.suggest_name(node, wire_chunk.wire->name);
 							factory.update_pending(pending, node);
 						}
 					} else {
 						DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.wire->width);
-						T node = factory.slice(enqueue(whole_wire), wire_chunk.wire->width, wire_chunk.offset, wire_chunk.width);
+						Node node = factory.slice(enqueue(whole_wire), wire_chunk.offset, wire_chunk.width);
 						factory.update_pending(pending, node);
 					}
 				} else if (chunk.is_port()) {
@@ -497,21 +473,22 @@ class FunctionalIRConstruction {
 							if (port_chunk.cell->type.in(ID($dff), ID($ff)))
 							{
 								Cell *cell = port_chunk.cell;
-								T node = factory.state(cell->name, port_chunk.width);
+								Node node = factory.state(cell->name, port_chunk.width);
 								factory.suggest_name(node, port_chunk.cell->name);
 								factory.update_pending(pending, node);
 								for (auto const &conn : cell->connections()) {
 									if (driver_map.celltypes.cell_input(cell->type, conn.first)) {
-										T node = enqueue(DriveChunkPort(cell, conn));
+										Node node = enqueue(DriveChunkPort(cell, conn));
 										factory.declare_state(node, cell->name, port_chunk.width);
 									}
 								}
 							}
 							else
 							{
-								T cell = enqueue(DriveChunkMarker(cells(port_chunk.cell), 0, port_chunk.width));
+								Node cell = enqueue(DriveChunkMarker(cells(port_chunk.cell), 0, port_chunk.width));
 								factory.suggest_name(cell, port_chunk.cell->name);
-								T node = factory.cell_output(cell, port_chunk.cell->type, port_chunk.port, port_chunk.width);
+								//Node node = factory.cell_output(cell, port_chunk.cell->type, port_chunk.port, port_chunk.width);
+								Node node = cell;
 								factory.suggest_name(node, port_chunk.cell->name.str() + "$" + port_chunk.port.str());
 								factory.update_pending(pending, node);
 							}
@@ -521,37 +498,37 @@ class FunctionalIRConstruction {
 						}
 					} else {
 						DriveChunkPort whole_port(port_chunk.cell, port_chunk.port, 0, GetSize(port_chunk.cell->connections().at(port_chunk.port)));
-						T node = factory.slice(enqueue(whole_port), whole_port.width, port_chunk.offset, port_chunk.width);
+						Node node = factory.slice(enqueue(whole_port), port_chunk.offset, port_chunk.width);
 						factory.update_pending(pending, node);
 					}
 				} else if (chunk.is_constant()) {
-					T node = factory.constant(chunk.constant());
+					Node node = factory.constant(chunk.constant());
 					factory.suggest_name(node, "$const" + std::to_string(chunk.size()) + "b" + chunk.constant().as_string());
 					factory.update_pending(pending, node);
 				} else if (chunk.is_multiple()) {
-					vector<T> args;
+					vector<Node> args;
 					for (auto const &driver : chunk.multiple().multiple())
 						args.push_back(enqueue(driver));
-					T node = factory.multiple(args, chunk.size());
+					Node node = factory.multiple(args, chunk.size());
 					factory.update_pending(pending, node);
 				} else if (chunk.is_marker()) {
 					Cell *cell = cells[chunk.marker().marker];
 					if (cell->is_mem_cell()) {
 						Mem *mem = memories.at(cell, nullptr);
 						log_assert(mem != nullptr);
-						T node = handle_memory(mem);
+						Node node = handle_memory(mem);
 						factory.update_pending(pending, node);
 					} else {
-						dict<IdString, T> connections;
+						dict<IdString, Node> connections;
 						for(auto const &conn : cell->connections()) {
 							if(driver_map.celltypes.cell_input(cell->type, conn.first))
 								connections.insert({ conn.first, enqueue(DriveChunkPort(cell, conn)) });
 						}
-						T node = simplifier.handle(cell->type, cell->parameters, connections);
+						Node node = simplifier.handle(cell->type, cell->parameters, connections);
 						factory.update_pending(pending, node);
 					}
 				} else if (chunk.is_none()) {
-					T node = factory.undriven(chunk.size());
+					Node node = factory.undriven(chunk.size());
 					factory.update_pending(pending, node);
 				} else {
 					log_error("unhandled drivespec: %s\n", log_signal(chunk));
@@ -567,7 +544,7 @@ class FunctionalIRConstruction {
 FunctionalIR FunctionalIR::from_module(Module *module) {
     FunctionalIR ir;
     auto factory = ir.factory();
-    FunctionalIRConstruction<FunctionalIR::Node, FunctionalIR::Factory> ctor(factory);
+    FunctionalIRConstruction ctor(factory);
     ctor.add_module(module);
     ctor.process_queue();
     ir.topological_sort();
diff --git a/kernel/functionalir.h b/kernel/functionalir.h
index e586695695a..44e3589db2d 100644
--- a/kernel/functionalir.h
+++ b/kernel/functionalir.h
@@ -385,78 +385,79 @@ class FunctionalIR {
 		void check_shift(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && b.sort().is_signal()); }
 		void check_unary(Node const &a) { log_assert(a.sort().is_signal()); }
 	public:
-		Node slice(Node a, int, int offset, int out_width) {
+		Node slice(Node a, int offset, int out_width) {
 			log_assert(a.sort().is_signal() && offset + out_width <= a.sort().width());
 			if(offset == 0 && out_width == a.width())
 				return a;
 			return add(NodeData(Fn::slice, offset), Sort(out_width), {a});
 		}
-		Node extend(Node a, int, int out_width, bool is_signed) {
+		// extend will either extend or truncate the provided value to reach the desired width
+		Node extend(Node a, int out_width, bool is_signed) {
 			int in_width = a.sort().width();
 			log_assert(a.sort().is_signal());
 			if(in_width == out_width)
 				return a;
-			if(in_width < out_width)
-				return slice(a, in_width, 0, out_width);
+			if(in_width > out_width)
+				return slice(a, 0, out_width);
 			if(is_signed)
 				return add(Fn::sign_extend, Sort(out_width), {a});
 			else
 				return add(Fn::zero_extend, Sort(out_width), {a});
 		}
-		Node concat(Node a, int, Node b, int) {
+		Node concat(Node a, Node b) {
 			log_assert(a.sort().is_signal() && b.sort().is_signal());
 			return add(Fn::concat, Sort(a.sort().width() + b.sort().width()), {a, b});
 		}
-		Node add(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::add, a.sort(), {a, b}); }
-		Node sub(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::sub, a.sort(), {a, b}); }
-		Node mul(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::mul, a.sort(), {a, b}); }
-		Node unsigned_div(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::unsigned_div, a.sort(), {a, b}); }
-		Node unsigned_mod(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::unsigned_mod, a.sort(), {a, b}); }
-		Node bitwise_and(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::bitwise_and, a.sort(), {a, b}); }
-		Node bitwise_or(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::bitwise_or, a.sort(), {a, b}); }
-		Node bitwise_xor(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::bitwise_xor, a.sort(), {a, b}); }
-		Node bitwise_not(Node a, int) { check_unary(a); return add(Fn::bitwise_not, a.sort(), {a}); }
-		Node unary_minus(Node a, int) { check_unary(a); return add(Fn::unary_minus, a.sort(), {a}); }
-		Node reduce_and(Node a, int) {
+		Node add(Node a, Node b) { check_basic_binary(a, b); return add(Fn::add, a.sort(), {a, b}); }
+		Node sub(Node a, Node b) { check_basic_binary(a, b); return add(Fn::sub, a.sort(), {a, b}); }
+		Node mul(Node a, Node b) { check_basic_binary(a, b); return add(Fn::mul, a.sort(), {a, b}); }
+		Node unsigned_div(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_div, a.sort(), {a, b}); }
+		Node unsigned_mod(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_mod, a.sort(), {a, b}); }
+		Node bitwise_and(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_and, a.sort(), {a, b}); }
+		Node bitwise_or(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_or, a.sort(), {a, b}); }
+		Node bitwise_xor(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_xor, a.sort(), {a, b}); }
+		Node bitwise_not(Node a) { check_unary(a); return add(Fn::bitwise_not, a.sort(), {a}); }
+		Node unary_minus(Node a) { check_unary(a); return add(Fn::unary_minus, a.sort(), {a}); }
+		Node reduce_and(Node a) {
 			check_unary(a);
 			if(a.width() == 1)
 				return a;
 			return add(Fn::reduce_and, Sort(1), {a});
 		}
-		Node reduce_or(Node a, int) {
+		Node reduce_or(Node a) {
 			check_unary(a);
 			if(a.width() == 1)
 				return a;
 			return add(Fn::reduce_or, Sort(1), {a});
 		}
-		Node reduce_xor(Node a, int) { 
+		Node reduce_xor(Node a) { 
 			check_unary(a);
 			if(a.width() == 1)
 				return a;
 			return add(Fn::reduce_xor, Sort(1), {a});
 		}
-		Node equal(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::equal, Sort(1), {a, b}); }
-		Node not_equal(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::not_equal, Sort(1), {a, b}); }
-		Node signed_greater_than(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::signed_greater_than, Sort(1), {a, b}); }
-		Node signed_greater_equal(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::signed_greater_equal, Sort(1), {a, b}); }
-		Node unsigned_greater_than(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::unsigned_greater_than, Sort(1), {a, b}); }
-		Node unsigned_greater_equal(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::unsigned_greater_equal, Sort(1), {a, b}); }
-		Node logical_shift_left(Node a, Node b, int, int) { check_shift(a, b); return add(Fn::logical_shift_left, a.sort(), {a, b}); }
-		Node logical_shift_right(Node a, Node b, int, int) { check_shift(a, b); return add(Fn::logical_shift_right, a.sort(), {a, b}); }
-		Node arithmetic_shift_right(Node a, Node b, int, int) { check_shift(a, b); return add(Fn::arithmetic_shift_right, a.sort(), {a, b}); }
-		Node mux(Node a, Node b, Node s, int) {
+		Node equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::equal, Sort(1), {a, b}); }
+		Node not_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::not_equal, Sort(1), {a, b}); }
+		Node signed_greater_than(Node a, Node b) { check_basic_binary(a, b); return add(Fn::signed_greater_than, Sort(1), {a, b}); }
+		Node signed_greater_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::signed_greater_equal, Sort(1), {a, b}); }
+		Node unsigned_greater_than(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_greater_than, Sort(1), {a, b}); }
+		Node unsigned_greater_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_greater_equal, Sort(1), {a, b}); }
+		Node logical_shift_left(Node a, Node b) { check_shift(a, b); return add(Fn::logical_shift_left, a.sort(), {a, b}); }
+		Node logical_shift_right(Node a, Node b) { check_shift(a, b); return add(Fn::logical_shift_right, a.sort(), {a, b}); }
+		Node arithmetic_shift_right(Node a, Node b) { check_shift(a, b); return add(Fn::arithmetic_shift_right, a.sort(), {a, b}); }
+		Node mux(Node a, Node b, Node s) {
 			log_assert(a.sort().is_signal() && a.sort() == b.sort() && s.sort() == Sort(1));
 			return add(Fn::mux, a.sort(), {a, b, s});
 		}
-		Node pmux(Node a, Node b, Node s, int, int) {
+		Node pmux(Node a, Node b, Node s) {
 			log_assert(a.sort().is_signal() && b.sort().is_signal() && s.sort().is_signal() && a.sort().width() * s.sort().width() == b.sort().width());
 			return add(Fn::pmux, a.sort(), {a, b, s});
 		}
-		Node memory_read(Node mem, Node addr, int, int) {
+		Node memory_read(Node mem, Node addr) {
 			log_assert(mem.sort().is_memory() && addr.sort().is_signal() && mem.sort().addr_width() == addr.sort().width());
 			return add(Fn::memory_read, Sort(mem.sort().data_width()), {mem, addr});
 		}
-		Node memory_write(Node mem, Node addr, Node data, int, int) {
+		Node memory_write(Node mem, Node addr, Node data) {
 			log_assert(mem.sort().is_memory() && addr.sort().is_signal() && data.sort().is_signal() &&
 				mem.sort().addr_width() == addr.sort().width() && mem.sort().data_width() == data.sort().width());
 			return add(Fn::memory_write, mem.sort(), {mem, addr, data});
@@ -484,9 +485,6 @@ class FunctionalIR {
 			_ir.add_state(name, Sort(addr_width, data_width));
 			return add(NodeData(Fn::state, name), Sort(addr_width, data_width), {});
 		}
-		Node cell_output(Node node, IdString, IdString, int) {
-			return node;
-		}
 		Node multiple(vector<Node> args, int width) {
 			auto node = add(Fn::multiple, Sort(width), {});
 			for(const auto &arg : args)

From c0c90c2c312e8f1675613904a67d5e016a62bb03 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Wed, 17 Jul 2024 13:26:53 +0100
Subject: [PATCH 413/499] functional backend: require shift width ==
 clog2(operand width)

---
 kernel/functionalir.cc          | 48 ++++++++++++++++-----------------
 kernel/functionalir.h           | 10 ++++---
 tests/functional/rtlil_cells.py |  5 +++-
 3 files changed, 34 insertions(+), 29 deletions(-)

diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc
index 48baad7168b..ddd821adafa 100644
--- a/kernel/functionalir.cc
+++ b/kernel/functionalir.cc
@@ -101,17 +101,6 @@ std::string FunctionalIR::Node::to_string(std::function<std::string(Node)> np)
 class CellSimplifier {
 	using Node = FunctionalIR::Node;
 	FunctionalIR::Factory &factory;
-	Node reduce_shift_width(Node b, int y_width) {
-		log_assert(y_width > 0);
-		int new_width = ceil_log2(y_width + 1);
-		if (b.width() <= new_width) {
-			return b;
-		} else {
-			Node lower_b = factory.slice(b, 0, new_width);
-			Node overflow = factory.unsigned_greater_than(b, factory.constant(RTLIL::Const(y_width, b.width())));
-			return factory.mux(lower_b, factory.constant(RTLIL::Const(y_width, new_width)), overflow);
-		}
-	}
 	Node sign(Node a) {
 		return factory.slice(a, a.width() - 1, 1);
 	}
@@ -121,19 +110,30 @@ class CellSimplifier {
 	Node abs(Node a) {
 		return neg_if(a, sign(a));
 	}
-public:
-	Node logical_shift_left(Node a, Node b) {
-		Node reduced_b = reduce_shift_width(b, a.width());
-		return factory.logical_shift_left(a, reduced_b);
-	}
-	Node logical_shift_right(Node a, Node b) {
-		Node reduced_b = reduce_shift_width(b, a.width());
-		return factory.logical_shift_right(a, reduced_b);
-	}
-	Node arithmetic_shift_right(Node a, Node b) {
-		Node reduced_b = reduce_shift_width(b, a.width());
-		return factory.arithmetic_shift_right(a, reduced_b);
+	Node handle_shift(Node a, Node b, bool is_right, bool is_signed) {
+		// to prevent new_width == 0, we handle this case separately
+		if(a.width() == 1) {
+			if(!is_signed)
+				return factory.bitwise_and(a, factory.bitwise_not(factory.reduce_or(b)));
+			else
+				return a;
+		}
+		int new_width = ceil_log2(a.width());
+		Node b_truncated = factory.extend(b, new_width, false);
+		Node y =
+			!is_right ? factory.logical_shift_left(a, b_truncated) :
+			!is_signed ? factory.logical_shift_right(a, b_truncated) :
+			factory.arithmetic_shift_right(a, b_truncated);
+		if(b.width() <= new_width)
+			return y;
+		Node overflow = factory.unsigned_greater_equal(b, factory.constant(RTLIL::Const(a.width(), b.width())));
+		Node y_if_overflow = is_signed ? factory.extend(sign(a), a.width(), true) : factory.constant(RTLIL::Const(State::S0, a.width()));
+		return factory.mux(y, y_if_overflow, overflow);
 	}
+public:
+	Node logical_shift_left(Node a, Node b) { return handle_shift(a, b, false, false); }
+	Node logical_shift_right(Node a, Node b) { return handle_shift(a, b, true, false); }
+	Node arithmetic_shift_right(Node a, Node b) { return handle_shift(a, b, true, true); }
 	Node bitwise_mux(Node a, Node b, Node s) {
 		Node aa = factory.bitwise_and(a, factory.bitwise_not(s));
 		Node bb = factory.bitwise_and(b, s);
@@ -348,7 +348,7 @@ class CellSimplifier {
 			int width = parameters.at(ID(WIDTH)).as_int();
 			int s_width = parameters.at(ID(S_WIDTH)).as_int();
 			int y_width = width << s_width;
-			int b_width = ceil_log2(y_width + 1);
+			int b_width = ceil_log2(y_width);
 			Node a = factory.extend(inputs.at(ID(A)), y_width, false);
 			Node s = factory.extend(inputs.at(ID(S)), b_width, false);
 			Node b = factory.mul(s, factory.constant(Const(width, b_width)));
diff --git a/kernel/functionalir.h b/kernel/functionalir.h
index 44e3589db2d..0559eae8921 100644
--- a/kernel/functionalir.h
+++ b/kernel/functionalir.h
@@ -109,13 +109,13 @@ class FunctionalIR {
 		// unsigned_greater_equal(a: unsigned bit[N], b: unsigned bit[N]): bit[1] = (a >= b)
 		unsigned_greater_equal,
 		// logical_shift_left(a: bit[N], b: unsigned bit[M]): bit[N] = a << b
-		// required: M <= clog2(N + 1)
+		// required: M == clog2(N)
 		logical_shift_left,
 		// logical_shift_right(a: unsigned bit[N], b: unsigned bit[M]): unsigned bit[N] = a >> b
-		// required: M <= clog2(N + 1)
+		// required: M == clog2(N)
 		logical_shift_right,
 		// arithmetic_shift_right(a: signed bit[N], b: unsigned bit[M]): signed bit[N] = a >> b
-		// required: M <= clog2(N + 1)
+		// required: M == clog2(N)
 		arithmetic_shift_right,
 		// mux(a: bit[N], b: bit[N], s: bit[1]): bit[N] = s ? b : a
 		mux,
@@ -373,6 +373,8 @@ class FunctionalIR {
 		friend class FunctionalIR;
 		explicit Factory(FunctionalIR &ir) : _ir(ir) {}
 		Node add(NodeData &&fn, Sort &&sort, std::initializer_list<Node> args) {
+			log_assert(!sort.is_signal() || sort.width() > 0);
+			log_assert(!sort.is_memory() || sort.addr_width() > 0 && sort.data_width() > 0);
 			Graph::Ref ref = _ir._graph.add(std::move(fn), {std::move(sort)});
 			for (auto arg : args)
 				ref.append_arg(Graph::ConstRef(arg));
@@ -382,7 +384,7 @@ class FunctionalIR {
 			return _ir._graph[n._ref.index()];
 		}
 		void check_basic_binary(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && a.sort() == b.sort()); }
-		void check_shift(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && b.sort().is_signal()); }
+		void check_shift(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && b.sort().is_signal() && b.width() == ceil_log2(a.width())); }
 		void check_unary(Node const &a) { log_assert(a.sort().is_signal()); }
 	public:
 		Node slice(Node a, int offset, int out_width) {
diff --git a/tests/functional/rtlil_cells.py b/tests/functional/rtlil_cells.py
index b4c0ad1c1ef..7858e3781d5 100644
--- a/tests/functional/rtlil_cells.py
+++ b/tests/functional/rtlil_cells.py
@@ -206,7 +206,10 @@ def write_rtlil_file(self, path, parameters):
     (32, 32, 64, True, True),
     (32, 32, 64, False, True),
     # at least one test where the result is going to be truncated
-    (32, 6, 16, False, False)
+    (32, 6, 16, False, False),
+    # since 1-bit shifts are special cased
+    (1, 4, 1, False, False),
+    (1, 4, 1, True, False),
 ]
 
 rtlil_cells = [

From 13bacc5c8f77fc98cf20d3d2c67d1f5dee1c84a6 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Wed, 17 Jul 2024 13:35:58 +0100
Subject: [PATCH 414/499] eliminate pmux in functional backend

---
 backends/functional/cxx.cc            |  1 -
 backends/functional/cxx_runtime/sim.h | 19 -------------------
 backends/functional/smtlib.cc         |  6 ------
 kernel/functionalir.cc                | 11 +++++++++--
 kernel/functionalir.h                 | 12 ------------
 5 files changed, 9 insertions(+), 40 deletions(-)

diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index 920ccf363bc..0fa310164a6 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -136,7 +136,6 @@ template<class NodePrinter> struct CxxPrintVisitor : public FunctionalIR::Abstra
 	void logical_shift_right(Node, Node a, Node b) override { print("{} >> {}", a, b); }
 	void arithmetic_shift_right(Node, Node a, Node b) override { print("{}.arithmetic_shift_right({})", a, b); }
 	void mux(Node, Node a, Node b, Node s) override { print("{2}.any() ? {1} : {0}", a, b, s); }
-	void pmux(Node, Node a, Node b, Node s) override { print("{0}.pmux({1}, {2})", a, b, s); }
 	void constant(Node, RTLIL::Const value) override {
 		std::stringstream ss;
 		bool multiple = value.size() > 32;
diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h
index 950d4c5e10b..ed1a25ed40f 100644
--- a/backends/functional/cxx_runtime/sim.h
+++ b/backends/functional/cxx_runtime/sim.h
@@ -368,25 +368,6 @@ class Signal {
         return ret;
     }
 
-    template<size_t ns>
-    Signal<n> pmux(Signal<n*ns> const &b, Signal<ns> const &s) const
-    {
-        bool found;
-        Signal<n> ret;
-
-        found = false;
-        ret = *this;
-        for(size_t i = 0; i < ns; i++){
-            if(s._bits[i]){
-                if(found)
-                    return 0;
-                found = true;
-                ret = b.template slice<n>(n * i);
-            }
-        }
-        return ret;
-    }
-
     template<size_t m>
     Signal<n+m> concat(Signal<m> const& b) const
     {
diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index c35a48dd809..a2bb6666c3a 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -174,12 +174,6 @@ struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor<SExpr> {
 	SExpr logical_shift_right(Node, Node a, Node b) override { return list("bvlshr", n(a), extend(n(b), b.width(), a.width())); }
 	SExpr arithmetic_shift_right(Node, Node a, Node b) override { return list("bvashr", n(a), extend(n(b), b.width(), a.width())); }
 	SExpr mux(Node, Node a, Node b, Node s) override { return list("ite", to_bool(n(s)), n(b), n(a)); }
-	SExpr pmux(Node, Node a, Node b, Node s) override {
-		SExpr rv = n(a);
-		for(int i = 0; i < s.width(); i++)
-			rv = list("ite", to_bool(extract(n(s), i)), extract(n(b), a.width() * i, a.width()), rv);
-		return rv;
-	}
 	SExpr constant(Node, RTLIL::Const value) override { return literal(value); }
 	SExpr memory_read(Node, Node mem, Node addr) override { return list("select", n(mem), n(addr)); }
 	SExpr memory_write(Node, Node mem, Node addr, Node data) override { return list("store", n(mem), n(addr), n(data)); }
diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc
index ddd821adafa..4b2ad8c0bf9 100644
--- a/kernel/functionalir.cc
+++ b/kernel/functionalir.cc
@@ -52,7 +52,6 @@ const char *FunctionalIR::fn_to_string(FunctionalIR::Fn fn) {
 	case FunctionalIR::Fn::logical_shift_right: return "logical_shift_right";
 	case FunctionalIR::Fn::arithmetic_shift_right: return "arithmetic_shift_right";
 	case FunctionalIR::Fn::mux: return "mux";
-	case FunctionalIR::Fn::pmux: return "pmux";
 	case FunctionalIR::Fn::constant: return "constant";
 	case FunctionalIR::Fn::input: return "input";
 	case FunctionalIR::Fn::state: return "state";
@@ -165,6 +164,14 @@ class CellSimplifier {
 			return factory.mux(y0, y1, factory.slice(s, sn - 1, 1));
 		}
 	}
+	Node handle_pmux(Node a, Node b, Node s) {
+		// TODO : what to do about multiple b bits set ?
+		log_assert(b.width() == a.width() * s.width());
+		Node y = a;
+		for(int i = 0; i < s.width(); i++)
+			y = factory.mux(y, factory.slice(b, a.width() * i, a.width()), factory.slice(s, i, 1));
+		return y;
+	}
 public:
 	Node handle(IdString cellType, dict<IdString, Const> parameters, dict<IdString, Node> inputs)
 	{
@@ -266,7 +273,7 @@ class CellSimplifier {
 		}else if(cellType == ID($mux)){
 			return factory.mux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S)));
 		}else if(cellType == ID($pmux)){
-			return factory.pmux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S)));
+			return handle_pmux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S)));
 		}else if(cellType == ID($concat)){
 			Node a = inputs.at(ID(A));
 			Node b = inputs.at(ID(B));
diff --git a/kernel/functionalir.h b/kernel/functionalir.h
index 0559eae8921..d0ec1bce6ba 100644
--- a/kernel/functionalir.h
+++ b/kernel/functionalir.h
@@ -119,11 +119,6 @@ class FunctionalIR {
 		arithmetic_shift_right,
 		// mux(a: bit[N], b: bit[N], s: bit[1]): bit[N] = s ? b : a
 		mux,
-		// pmux(a: bit[N], b: bit[N*M], s: bit[M]): bit[N]
-		// required: no more than one bit in b is set
-		// if s[i] = 1 for any i, then returns b[i * N +: N]
-		// returns a if s == 0
-		pmux,
 		// constant(a: Const[N]): bit[N] = a
 		constant,
 		// input(a: IdString): any
@@ -277,7 +272,6 @@ class FunctionalIR {
 			case Fn::logical_shift_right: return v.logical_shift_right(*this, arg(0), arg(1)); break;
 			case Fn::arithmetic_shift_right: return v.arithmetic_shift_right(*this, arg(0), arg(1)); break;
 			case Fn::mux: return v.mux(*this, arg(0), arg(1), arg(2)); break;
-			case Fn::pmux: return v.pmux(*this, arg(0), arg(1), arg(2)); break;
 			case Fn::constant: return v.constant(*this, _ref.function().as_const()); break;
 			case Fn::input: return v.input(*this, _ref.function().as_idstring()); break;
 			case Fn::state: return v.state(*this, _ref.function().as_idstring()); break;
@@ -320,7 +314,6 @@ class FunctionalIR {
 		virtual T logical_shift_right(Node self, Node a, Node b) = 0;
 		virtual T arithmetic_shift_right(Node self, Node a, Node b) = 0;
 		virtual T mux(Node self, Node a, Node b, Node s) = 0;
-		virtual T pmux(Node self, Node a, Node b, Node s) = 0;
 		virtual T constant(Node self, RTLIL::Const value) = 0;
 		virtual T input(Node self, IdString name) = 0;
 		virtual T state(Node self, IdString name) = 0;
@@ -359,7 +352,6 @@ class FunctionalIR {
 		T logical_shift_right(Node self, Node, Node) override { return default_handler(self); }
 		T arithmetic_shift_right(Node self, Node, Node) override { return default_handler(self); }
 		T mux(Node self, Node, Node, Node) override { return default_handler(self); }
-		T pmux(Node self, Node, Node, Node) override { return default_handler(self); }
 		T constant(Node self, RTLIL::Const) override { return default_handler(self); }
 		T input(Node self, IdString) override { return default_handler(self); }
 		T state(Node self, IdString) override { return default_handler(self); }
@@ -451,10 +443,6 @@ class FunctionalIR {
 			log_assert(a.sort().is_signal() && a.sort() == b.sort() && s.sort() == Sort(1));
 			return add(Fn::mux, a.sort(), {a, b, s});
 		}
-		Node pmux(Node a, Node b, Node s) {
-			log_assert(a.sort().is_signal() && b.sort().is_signal() && s.sort().is_signal() && a.sort().width() * s.sort().width() == b.sort().width());
-			return add(Fn::pmux, a.sort(), {a, b, s});
-		}
 		Node memory_read(Node mem, Node addr) {
 			log_assert(mem.sort().is_memory() && addr.sort().is_signal() && mem.sort().addr_width() == addr.sort().width());
 			return add(Fn::memory_read, Sort(mem.sort().data_width()), {mem, addr});

From 3cd5f4ed83413cf4df695217ff85e3190ae4a8c7 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Wed, 17 Jul 2024 16:33:34 +0100
Subject: [PATCH 415/499] add support for RTLIL cells with multiple outputs to
 the functional backend, implement $fa,$lcu,$alu

---
 kernel/functionalir.cc              | 123 ++++++++++++++++++++++------
 tests/functional/rtlil_cells.py     |  21 ++++-
 tests/functional/test_functional.py |   8 +-
 3 files changed, 118 insertions(+), 34 deletions(-)

diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc
index 4b2ad8c0bf9..e768be4005d 100644
--- a/kernel/functionalir.cc
+++ b/kernel/functionalir.cc
@@ -18,6 +18,7 @@
  */
 
 #include "kernel/functionalir.h"
+#include <optional>
 
 YOSYS_NAMESPACE_BEGIN
 
@@ -172,8 +173,38 @@ class CellSimplifier {
 			y = factory.mux(y, factory.slice(b, a.width() * i, a.width()), factory.slice(s, i, 1));
 		return y;
 	}
+	dict<IdString, Node> handle_fa(Node a, Node b, Node c) {
+		Node t1 = factory.bitwise_xor(a, b);
+		Node t2 = factory.bitwise_and(a, b);
+		Node t3 = factory.bitwise_and(c, t1);
+		Node y = factory.bitwise_xor(c, t1);
+		Node x = factory.bitwise_or(t2, t3);
+		return {{ID(X), x}, {ID(Y), y}};
+	}
+	Node handle_lcu(Node p, Node g, Node ci) {
+		Node rv = factory.bitwise_or(factory.slice(g, 0, 1), factory.bitwise_and(factory.slice(p, 0, 1), ci));
+		Node c = rv;
+		for(int i = 1; i < p.width(); i++) {
+			c = factory.bitwise_or(factory.slice(g, i, 1), factory.bitwise_and(factory.slice(p, i, 1), c));
+			rv = factory.concat(rv, c);
+		}
+		return rv;
+	}
+	dict<IdString, Node> handle_alu(Node a_in, Node b_in, int y_width, bool is_signed, Node ci, Node bi) {
+		Node a = factory.extend(a_in, y_width, is_signed);
+		Node b_uninverted = factory.extend(b_in, y_width, is_signed);
+		Node b = factory.mux(b_uninverted, factory.bitwise_not(b_uninverted), bi);
+		Node x = factory.bitwise_xor(a, b);
+		Node a_extra = factory.extend(a, y_width + 1, false);
+		Node b_extra = factory.extend(b, y_width + 1, false);
+		Node y_extra = factory.add(factory.add(a_extra, b_extra), factory.extend(ci, a.width() + 1, false));
+		Node y = factory.slice(y_extra, 0, y_width);
+		Node carries = factory.bitwise_xor(y_extra, factory.bitwise_xor(a_extra, b_extra));
+		Node co = factory.slice(carries, 1, y_width);
+		return {{ID(X), x}, {ID(Y), y}, {ID(CO), co}};
+	}
 public:
-	Node handle(IdString cellType, dict<IdString, Const> parameters, dict<IdString, Node> inputs)
+	std::variant<dict<IdString, Node>, Node> handle(IdString cellType, dict<IdString, Const> parameters, dict<IdString, Node> inputs)
 	{
 		int a_width = parameters.at(ID(A_WIDTH), Const(-1)).as_int();
 		int b_width = parameters.at(ID(B_WIDTH), Const(-1)).as_int();
@@ -360,17 +391,23 @@ class CellSimplifier {
 			Node s = factory.extend(inputs.at(ID(S)), b_width, false);
 			Node b = factory.mul(s, factory.constant(Const(width, b_width)));
 			return factory.logical_shift_left(a, b);
+		} else if(cellType == ID($fa)) {
+			return handle_fa(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(C)));
+		} else if(cellType == ID($lcu)) {
+			return handle_lcu(inputs.at(ID(P)), inputs.at(ID(G)), inputs.at(ID(CI)));
+		} else if(cellType == ID($alu)) {
+			return handle_alu(inputs.at(ID(A)), inputs.at(ID(B)), y_width, a_signed && b_signed, inputs.at(ID(CI)), inputs.at(ID(BI)));
 		} else {
-			log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str());
+			log_error("`%s' cells are not supported by the functional backend\n", cellType.c_str());
 		}
 	}
 };
 
 class FunctionalIRConstruction {
 	using Node = FunctionalIR::Node;
-	std::deque<DriveSpec> queue;
+	std::deque<std::variant<DriveSpec, Cell *>> queue;
 	dict<DriveSpec, Node> graph_nodes;
-	idict<Cell *> cells;
+	dict<std::pair<Cell *, IdString>, Node> cell_outputs;
 	DriverMap driver_map;
 	FunctionalIR::Factory& factory;
 	CellSimplifier simplifier;
@@ -388,6 +425,24 @@ class FunctionalIRConstruction {
 		}else
 			return it->second;
 	}
+	Node enqueue_cell(Cell *cell, IdString port_name)
+	{
+		auto it = cell_outputs.find({cell, port_name});
+		if(it == cell_outputs.end()) {
+			queue.emplace_back(cell);
+			std::optional<Node> rv;
+			for(auto const &[name, sigspec] : cell->connections())
+				if(driver_map.celltypes.cell_output(cell->type, name)) {
+					auto node = factory.create_pending(sigspec.size());
+					factory.suggest_name(node, cell->name.str() + "$" + name.str());
+					cell_outputs.emplace({cell, name}, node);
+					if(name == port_name)
+						rv = node;
+				}
+			return *rv;
+		} else
+			return it->second;
+	}
 public:
 	FunctionalIRConstruction(FunctionalIR::Factory &f) : factory(f), simplifier(f) {}
 	void add_module(Module *module)
@@ -395,7 +450,7 @@ class FunctionalIRConstruction {
 		driver_map.add(module);
 		for (auto cell : module->cells()) {
 			if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($check)))
-				enqueue(DriveBitMarker(cells(cell), 0));
+				queue.emplace_back(cell);
 		}
 		for (auto wire : module->wires()) {
 			if (wire->port_output) {
@@ -441,10 +496,44 @@ class FunctionalIRConstruction {
 		factory.declare_state_memory(node, mem->cell->name, addr_width, data_width);
 		return concatenate_read_results(mem, read_results);
 	}
+	void process_cell(Cell *cell)
+	{
+		if (cell->is_mem_cell()) {
+			Mem *mem = memories.at(cell, nullptr);
+			log_assert(mem != nullptr);
+			Node node = handle_memory(mem);
+			factory.update_pending(cell_outputs.at({cell, ID(RD_DATA)}), node);
+		} else {
+			dict<IdString, Node> connections;
+			IdString output_name; // for the single output case
+			int n_outputs = 0;
+			for(auto const &[name, sigspec] : cell->connections()) {
+				if(driver_map.celltypes.cell_input(cell->type, name))
+					connections.insert({ name, enqueue(DriveChunkPort(cell, {name, sigspec})) });
+				if(driver_map.celltypes.cell_output(cell->type, name)) {
+					output_name = name;
+					n_outputs++;
+				}
+			}
+			std::variant<dict<IdString, Node>, Node> outputs = simplifier.handle(cell->type, cell->parameters, connections);
+			if(auto *nodep = std::get_if<Node>(&outputs); nodep != nullptr) {
+				log_assert(n_outputs == 1);
+				factory.update_pending(cell_outputs.at({cell, output_name}), *nodep);
+			} else {
+				for(auto [name, node] : std::get<dict<IdString, Node>>(outputs))
+					factory.update_pending(cell_outputs.at({cell, name}), node);
+			}
+		}
+	}
 	void process_queue()
 	{
 		for (; !queue.empty(); queue.pop_front()) {
-			DriveSpec spec = queue.front();
+			if(auto p = std::get_if<Cell *>(&queue.front()); p != nullptr) {
+				process_cell(*p);
+				continue;
+			}
+
+			DriveSpec spec = std::get<DriveSpec>(queue.front());
 			Node pending = graph_nodes.at(spec);
 
 			if (spec.chunks().size() > 1) {
@@ -492,11 +581,7 @@ class FunctionalIRConstruction {
 							}
 							else
 							{
-								Node cell = enqueue(DriveChunkMarker(cells(port_chunk.cell), 0, port_chunk.width));
-								factory.suggest_name(cell, port_chunk.cell->name);
-								//Node node = factory.cell_output(cell, port_chunk.cell->type, port_chunk.port, port_chunk.width);
-								Node node = cell;
-								factory.suggest_name(node, port_chunk.cell->name.str() + "$" + port_chunk.port.str());
+								Node node = enqueue_cell(port_chunk.cell, port_chunk.port);
 								factory.update_pending(pending, node);
 							}
 						} else {
@@ -518,22 +603,6 @@ class FunctionalIRConstruction {
 						args.push_back(enqueue(driver));
 					Node node = factory.multiple(args, chunk.size());
 					factory.update_pending(pending, node);
-				} else if (chunk.is_marker()) {
-					Cell *cell = cells[chunk.marker().marker];
-					if (cell->is_mem_cell()) {
-						Mem *mem = memories.at(cell, nullptr);
-						log_assert(mem != nullptr);
-						Node node = handle_memory(mem);
-						factory.update_pending(pending, node);
-					} else {
-						dict<IdString, Node> connections;
-						for(auto const &conn : cell->connections()) {
-							if(driver_map.celltypes.cell_input(cell->type, conn.first))
-								connections.insert({ conn.first, enqueue(DriveChunkPort(cell, conn)) });
-						}
-						Node node = simplifier.handle(cell->type, cell->parameters, connections);
-						factory.update_pending(pending, node);
-					}
 				} else if (chunk.is_none()) {
 					Node node = factory.undriven(chunk.size());
 					factory.update_pending(pending, node);
diff --git a/tests/functional/rtlil_cells.py b/tests/functional/rtlil_cells.py
index 7858e3781d5..4dbea6015bd 100644
--- a/tests/functional/rtlil_cells.py
+++ b/tests/functional/rtlil_cells.py
@@ -123,6 +123,21 @@ class SliceCell(BaseCell):
     def __init__(self, name, values):
         super().__init__(name, ['A_WIDTH', 'OFFSET', 'Y_WIDTH'], {'A': 'A_WIDTH'}, {'Y': 'Y_WIDTH'}, values)
 
+class FACell(BaseCell):
+    def __init__(self, name, values):
+        super().__init__(name, ['WIDTH'], {'A': 'WIDTH', 'B': 'WIDTH', 'C': 'WIDTH'}, {'X': 'WIDTH', 'Y': 'WIDTH'}, values)
+        self.sim_preprocessing = "techmap" # because FA is not implemented in yosys sim
+
+class LCUCell(BaseCell):
+    def __init__(self, name, values):
+        super().__init__(name, ['WIDTH'], {'P': 'WIDTH', 'G': 'WIDTH', 'CI': 1}, {'CO': 'WIDTH'}, values)
+        self.sim_preprocessing = "techmap" # because LCU is not implemented in yosys sim
+
+class ALUCell(BaseCell):
+    def __init__(self, name, values):
+        super().__init__(name, ['A_WIDTH', 'B_WIDTH', 'Y_WIDTH', 'A_SIGNED', 'B_SIGNED'], {'A': 'A_WIDTH', 'B': 'B_WIDTH', 'CI': 1, 'BI': 1}, {'X': 'Y_WIDTH', 'Y': 'Y_WIDTH', 'CO': 'Y_WIDTH'}, values)
+        self.sim_preprocessing = "techmap" # because ALU is not implemented in yosys sim
+
 class FailCell(BaseCell):
     def __init__(self, name):
         super().__init__(name, [], {}, {})
@@ -231,9 +246,9 @@ def write_rtlil_file(self, path, parameters):
     ShiftCell("sshr", shift_widths),
     ShiftCell("shift", shift_widths),
     ShiftCell("shiftx", shift_widths),
-#    ("fa", ["A", "B", "C", "X", "Y"]),
-#    ("lcu", ["P", "G", "CI", "CO"]),
-#    ("alu", ["A", "B", "CI", "BI", "X", "Y", "CO"]),
+    FACell("fa", [8, 20]),
+    LCUCell("lcu", [1, 10]),
+    ALUCell("alu", binary_widths),
     BinaryCell("lt", binary_widths),
     BinaryCell("le", binary_widths),
     BinaryCell("eq", binary_widths),
diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py
index 86e515d90a9..150642a00db 100644
--- a/tests/functional/test_functional.py
+++ b/tests/functional/test_functional.py
@@ -27,9 +27,9 @@ def yosys_synth(verilog_file, rtlil_file):
     yosys(f"read_verilog {quote(verilog_file)} ; prep ; clk2fflogic ; write_rtlil {quote(rtlil_file)}")
 
 # simulate an rtlil file with yosys, comparing with a given vcd file, and writing out the yosys simulation results into a second vcd file
-def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file):
+def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""):
     try:
-        yosys(f"read_rtlil {quote(rtlil_file)}; sim -r {quote(vcd_reference_file)} -scope gold -vcd {quote(vcd_out_file)} -timescale 1us -sim-gold")
+        yosys(f"read_rtlil {quote(rtlil_file)}; {preprocessing}; sim -r {quote(vcd_reference_file)} -scope gold -vcd {quote(vcd_out_file)} -timescale 1us -sim-gold")
     except:
         # if yosys sim fails it's probably because of a simulation mismatch
         # since yosys sim aborts on simulation mismatch to generate vcd output
@@ -53,7 +53,7 @@ def test_cxx(cell, parameters, tmp_path, num_steps, rnd):
     compile_cpp(vcdharness_cc_file, vcdharness_exe_file, ['-I', tmp_path, '-I', str(base_path / 'backends/functional/cxx_runtime')])
     seed = str(rnd(cell.name + "-cxx").getrandbits(32))
     run([str(vcdharness_exe_file.resolve()), str(vcd_functional_file), str(num_steps), str(seed)])
-    yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file)
+    yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
 
 def test_smt(cell, parameters, tmp_path, num_steps, rnd):
     import smt_vcd
@@ -67,4 +67,4 @@ def test_smt(cell, parameters, tmp_path, num_steps, rnd):
     yosys(f"read_rtlil {quote(rtlil_file)} ; write_functional_smt2 {quote(smt_file)}")
     run(['z3', smt_file]) # check if output is valid smtlib before continuing
     smt_vcd.simulate_smt(smt_file, vcd_functional_file, num_steps, rnd(cell.name + "-smt"))
-    yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file)
\ No newline at end of file
+    yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
\ No newline at end of file

From 4722f13a5d917d2c464ef74de7facabd85fc63aa Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 18 Jul 2024 07:50:49 +0100
Subject: [PATCH 416/499] functional backend: reduce $lcu to $alu

---
 kernel/functionalir.cc | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc
index e768be4005d..778b6a825d3 100644
--- a/kernel/functionalir.cc
+++ b/kernel/functionalir.cc
@@ -181,20 +181,14 @@ class CellSimplifier {
 		Node x = factory.bitwise_or(t2, t3);
 		return {{ID(X), x}, {ID(Y), y}};
 	}
-	Node handle_lcu(Node p, Node g, Node ci) {
-		Node rv = factory.bitwise_or(factory.slice(g, 0, 1), factory.bitwise_and(factory.slice(p, 0, 1), ci));
-		Node c = rv;
-		for(int i = 1; i < p.width(); i++) {
-			c = factory.bitwise_or(factory.slice(g, i, 1), factory.bitwise_and(factory.slice(p, i, 1), c));
-			rv = factory.concat(rv, c);
-		}
-		return rv;
-	}
 	dict<IdString, Node> handle_alu(Node a_in, Node b_in, int y_width, bool is_signed, Node ci, Node bi) {
 		Node a = factory.extend(a_in, y_width, is_signed);
 		Node b_uninverted = factory.extend(b_in, y_width, is_signed);
 		Node b = factory.mux(b_uninverted, factory.bitwise_not(b_uninverted), bi);
 		Node x = factory.bitwise_xor(a, b);
+		// we can compute the carry into each bit using (a+b+c)^a^b. since we want the carry out,
+		// i.e. the carry into the next bit, we have to add an extra bit to a and b, and
+		// then slice off the bottom bit of the result.
 		Node a_extra = factory.extend(a, y_width + 1, false);
 		Node b_extra = factory.extend(b, y_width + 1, false);
 		Node y_extra = factory.add(factory.add(a_extra, b_extra), factory.extend(ci, a.width() + 1, false));
@@ -203,6 +197,9 @@ class CellSimplifier {
 		Node co = factory.slice(carries, 1, y_width);
 		return {{ID(X), x}, {ID(Y), y}, {ID(CO), co}};
 	}
+	Node handle_lcu(Node p, Node g, Node ci) {
+		return handle_alu(g, factory.bitwise_or(p, g), g.width(), false, ci, factory.constant(Const(State::S0, 1))).at(ID(CO));
+	}
 public:
 	std::variant<dict<IdString, Node>, Node> handle(IdString cellType, dict<IdString, Const> parameters, dict<IdString, Node> inputs)
 	{

From 145af6f10dd38441f0b549bfcd7547b7e749b8bb Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 18 Jul 2024 14:10:15 +0100
Subject: [PATCH 417/499] fix memory handling in functional backend, add more
 error messages and comments for memory edgecases

---
 kernel/functionalir.cc              | 52 +++++++++++++++++++++++------
 tests/functional/rtlil_cells.py     | 45 +++++++++++++++++++++++--
 tests/functional/test_functional.py |  6 ++--
 3 files changed, 86 insertions(+), 17 deletions(-)

diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc
index 778b6a825d3..f6d2f556061 100644
--- a/kernel/functionalir.cc
+++ b/kernel/functionalir.cc
@@ -461,11 +461,19 @@ class FunctionalIRConstruction {
 				memories[mem.cell] = &mem;
 		}
 	}
-	Node concatenate_read_results(Mem *, vector<Node> results)
+	Node concatenate_read_results(Mem *mem, vector<Node> results)
 	{
-        /* TODO: write code to check that this is ok to do */
-		if(results.size() == 0)
-			return factory.undriven(0);
+		// sanity check: all read ports concatenated should equal to the RD_DATA port
+		const SigSpec &rd_data = mem->cell->connections().at(ID(RD_DATA));
+		int current = 0;
+		for(size_t i = 0; i < mem->rd_ports.size(); i++) {
+			int width = mem->width << mem->rd_ports[i].wide_log2;
+			log_assert (results[i].width() == width);
+			log_assert (mem->rd_ports[i].data == rd_data.extract(current, width));
+			current += width;
+		}
+		log_assert (current == rd_data.size());
+		log_assert (!results.empty());
 		Node node = results[0];
 		for(size_t i = 1; i < results.size(); i++)
 			node = factory.concat(node, results[i]);
@@ -473,16 +481,23 @@ class FunctionalIRConstruction {
 	}
 	Node handle_memory(Mem *mem)
 	{
+		// To simplify memory handling, the functional backend makes the following assumptions:
+		// - Since async2sync or clk2fflogic must be run to use the functional backend,
+		//   we can assume that all ports are asynchronous.
+		// - Async rd/wr are always transparent and so we must do reads after writes,
+		//   but we can ignore transparency_mask.
+		// - We ignore collision_x_mask because x is a dont care value for us anyway.
+		// - Since wr port j can only have priority over wr port i if j > i, if we do writes in
+		//   ascending index order the result will obey the priorty relation.
 		vector<Node> read_results;
 		int addr_width = ceil_log2(mem->size);
 		int data_width = mem->width;
 		Node node = factory.state_memory(mem->cell->name, addr_width, data_width);
-		for (auto &rd : mem->rd_ports) {
-			log_assert(!rd.clk_enable);
-			Node addr = enqueue(driver_map(DriveSpec(rd.addr)));
-			read_results.push_back(factory.memory_read(node, addr));
-		}
-		for (auto &wr : mem->wr_ports) {
+		for (size_t i = 0; i < mem->wr_ports.size(); i++) {
+			const auto &wr = mem->wr_ports[i];
+			if (wr.clk_enable)
+				log_error("Write port %zd of memory %s.%s is clocked. This is not supported by the functional backend. "
+					"Call async2sync or clk2fflogic to avoid this error.\n", i, log_id(mem->module), log_id(mem->memid));
 			Node en = enqueue(driver_map(DriveSpec(wr.en)));
 			Node addr = enqueue(driver_map(DriveSpec(wr.addr)));
 			Node new_data = enqueue(driver_map(DriveSpec(wr.data)));
@@ -490,6 +505,17 @@ class FunctionalIRConstruction {
 			Node wr_data = simplifier.bitwise_mux(old_data, new_data, en);
 			node = factory.memory_write(node, addr, wr_data);
 		}
+		if (mem->rd_ports.empty())
+			log_error("Memory %s.%s has no read ports. This is not supported by the functional backend. "
+				"Call opt_clean to remove it.", log_id(mem->module), log_id(mem->memid));
+		for (size_t i = 0; i < mem->rd_ports.size(); i++) {
+			const auto &rd = mem->rd_ports[i];
+			if (rd.clk_enable)
+				log_error("Read port %zd of memory %s.%s is clocked. This is not supported by the functional backend. "
+					"Call memory_nordff to avoid this error.\n", i, log_id(mem->module), log_id(mem->memid));
+			Node addr = enqueue(driver_map(DriveSpec(rd.addr)));
+			read_results.push_back(factory.memory_read(node, addr));
+		}
 		factory.declare_state_memory(node, mem->cell->name, addr_width, data_width);
 		return concatenate_read_results(mem, read_results);
 	}
@@ -497,7 +523,11 @@ class FunctionalIRConstruction {
 	{
 		if (cell->is_mem_cell()) {
 			Mem *mem = memories.at(cell, nullptr);
-			log_assert(mem != nullptr);
+			if (mem == nullptr) {
+				log_assert(cell->has_memid());
+				log_error("The design contains an unpacked memory at %s. This is not supported by the functional backend. "
+					"Call memory_collect to avoid this error.\n", log_const(cell->parameters.at(ID(MEMID))));
+			}
 			Node node = handle_memory(mem);
 			factory.update_pending(cell_outputs.at({cell, ID(RD_DATA)}), node);
 		} else {
diff --git a/tests/functional/rtlil_cells.py b/tests/functional/rtlil_cells.py
index 4dbea6015bd..90417579e5d 100644
--- a/tests/functional/rtlil_cells.py
+++ b/tests/functional/rtlil_cells.py
@@ -176,14 +176,52 @@ def write_rtlil_file(self, path, parameters):
     input wire clk,
     input wire [{1}:0] WA,
     input wire [{0}:0] WD,
+    input wire [{1}:0] RA,
     output reg [{0}:0] RD
 );
-    reg [{0}:0] mem[0:{1}];
+    reg [{0}:0] mem[0:{2}];
     always @(*)
         RD = mem[RA];
     always @(posedge clk)
         mem[WA] <= WD;
-endmodule""".format(parameters['DATA_WIDTH'] - 1, parameters['ADDR_WIDTH'] - 1))
+endmodule""".format(parameters['DATA_WIDTH'] - 1, parameters['ADDR_WIDTH'] - 1, 2**parameters['ADDR_WIDTH'] - 1))
+        yosys_synth(verilog_file, path)
+
+class MemDualCell(BaseCell):
+    def __init__(self, name, values):
+        super().__init__(name, ['DATA_WIDTH', 'ADDR_WIDTH'],
+                         {'WA1': 'ADDR_WIDTH', 'WA2': 'ADDR_WIDTH',
+                          'RA1': 'ADDR_WIDTH', 'RA2': 'ADDR_WIDTH',
+                          'WD1': 'DATA_WIDTH', 'WD2': 'DATA_WIDTH'},
+                         {'RD1': 'DATA_WIDTH', 'RD2': 'DATA_WIDTH'}, values)
+        self.sim_preprocessing = "memory_map" # issue #4496 in yosys -sim prevents this example from working without memory_map
+    def write_rtlil_file(self, path, parameters):
+        from test_functional import yosys_synth
+        verilog_file = path.parent / 'verilog.v'
+        with open(verilog_file, 'w') as f:
+            f.write("""
+module gold(
+    input wire clk,
+    input wire [{1}:0] WA1,
+    input wire [{0}:0] WD1,
+    input wire [{1}:0] WA2,
+    input wire [{0}:0] WD2,
+    input wire [{1}:0] RA1,
+    input wire [{1}:0] RA2,
+    output reg [{0}:0] RD1,
+    output reg [{0}:0] RD2
+);
+                    (*keep*)
+    reg [{0}:0] mem[0:{2}];
+    always @(*)
+        RD1 = mem[RA1];
+    always @(*)
+        RD2 = mem[RA2];
+    always @(posedge clk) begin
+        mem[WA1] <= WD1;
+        mem[WA2] <= WD2;
+    end
+endmodule""".format(parameters['DATA_WIDTH'] - 1, parameters['ADDR_WIDTH'] - 1, 2**parameters['ADDR_WIDTH'] - 1))
         yosys_synth(verilog_file, path)
 
 binary_widths = [
@@ -284,7 +322,8 @@ def write_rtlil_file(self, path, parameters):
     BWCell("bweqx", [10, 16, 40]),
     BWCell("bwmux", [10, 16, 40]),
     FFCell("ff", [10, 20, 40]),
-    MemCell("mem", [(32, 4)])
+    MemCell("mem", [(16, 4)]),
+    MemDualCell("mem-dual", [(16, 4)]),
 #    ("assert", ["A", "EN"]),
 #    ("assume", ["A", "EN"]),
 #    ("live", ["A", "EN"]),
diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py
index 150642a00db..c31f4b86f5c 100644
--- a/tests/functional/test_functional.py
+++ b/tests/functional/test_functional.py
@@ -24,7 +24,7 @@ def compile_cpp(in_path, out_path, args):
     run(['g++', '-g', '-std=c++17'] + args + [str(in_path), '-o', str(out_path)])
 
 def yosys_synth(verilog_file, rtlil_file):
-    yosys(f"read_verilog {quote(verilog_file)} ; prep ; clk2fflogic ; write_rtlil {quote(rtlil_file)}")
+    yosys(f"read_verilog {quote(verilog_file)} ; prep ; write_rtlil {quote(rtlil_file)}")
 
 # simulate an rtlil file with yosys, comparing with a given vcd file, and writing out the yosys simulation results into a second vcd file
 def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""):
@@ -49,7 +49,7 @@ def test_cxx(cell, parameters, tmp_path, num_steps, rnd):
     vcd_yosys_sim_file = tmp_path / 'yosys.vcd'
 
     cell.write_rtlil_file(rtlil_file, parameters)
-    yosys(f"read_rtlil {quote(rtlil_file)} ; write_functional_cxx {quote(cc_file)}")
+    yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_cxx {quote(cc_file)}")
     compile_cpp(vcdharness_cc_file, vcdharness_exe_file, ['-I', tmp_path, '-I', str(base_path / 'backends/functional/cxx_runtime')])
     seed = str(rnd(cell.name + "-cxx").getrandbits(32))
     run([str(vcdharness_exe_file.resolve()), str(vcd_functional_file), str(num_steps), str(seed)])
@@ -64,7 +64,7 @@ def test_smt(cell, parameters, tmp_path, num_steps, rnd):
     vcd_yosys_sim_file = tmp_path / 'yosys.vcd'
 
     cell.write_rtlil_file(rtlil_file, parameters)
-    yosys(f"read_rtlil {quote(rtlil_file)} ; write_functional_smt2 {quote(smt_file)}")
+    yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_smt2 {quote(smt_file)}")
     run(['z3', smt_file]) # check if output is valid smtlib before continuing
     smt_vcd.simulate_smt(smt_file, vcd_functional_file, num_steps, rnd(cell.name + "-smt"))
     yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
\ No newline at end of file

From 6d329e142dbe16edfe772864a5c9debc72896e0f Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 18 Jul 2024 14:23:00 +0100
Subject: [PATCH 418/499] functional backend: error out if multiply driven or
 undriven signals are seen, dont bother putting them in functionalir

---
 backends/functional/cxx.cc    |  1 -
 backends/functional/smtlib.cc |  5 +----
 kernel/functionalir.cc        | 14 ++++----------
 kernel/functionalir.h         | 19 -------------------
 4 files changed, 5 insertions(+), 34 deletions(-)

diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index 0fa310164a6..69f1973f2cb 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -154,7 +154,6 @@ template<class NodePrinter> struct CxxPrintVisitor : public FunctionalIR::Abstra
 	void state(Node, IdString name) override { print("current_state.{}", state_struct[name]); }
 	void memory_read(Node, Node mem, Node addr) override { print("{}.read({})", mem, addr); }
 	void memory_write(Node, Node mem, Node addr, Node data) override { print("{}.write({}, {})", mem, addr, data); }
-	void undriven(Node, int width) override { print("Signal<{}>(0)", width); }
 };
 
 struct CxxModule {
diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index a2bb6666c3a..d40a4489f6a 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -180,8 +180,6 @@ struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor<SExpr> {
 
 	SExpr input(Node, IdString name) override { return input_struct.access("inputs", name); }
 	SExpr state(Node, IdString name) override { return state_struct.access("state", name); }
-
-	SExpr undriven(Node, int width) override { return literal(RTLIL::Const(State::S0, width)); }
 };
 
 struct SmtModule {
@@ -227,8 +225,7 @@ struct SmtModule {
 			     list("state", state_struct.name)),
 			list("Pair", output_struct.name, state_struct.name)));
 		auto inlined = [&](FunctionalIR::Node n) {
-			return n.fn() == FunctionalIR::Fn::constant ||
-				   n.fn() == FunctionalIR::Fn::undriven;
+			return n.fn() == FunctionalIR::Fn::constant;
 		};
 		SmtPrintVisitor visitor(input_struct, state_struct);
 		auto node_to_sexpr = [&](FunctionalIR::Node n) -> SExpr {
diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc
index f6d2f556061..155cb3bbc53 100644
--- a/kernel/functionalir.cc
+++ b/kernel/functionalir.cc
@@ -56,8 +56,6 @@ const char *FunctionalIR::fn_to_string(FunctionalIR::Fn fn) {
 	case FunctionalIR::Fn::constant: return "constant";
 	case FunctionalIR::Fn::input: return "input";
 	case FunctionalIR::Fn::state: return "state";
-	case FunctionalIR::Fn::multiple: return "multiple";
-	case FunctionalIR::Fn::undriven: return "undriven";
 	case FunctionalIR::Fn::memory_read: return "memory_read";
 	case FunctionalIR::Fn::memory_write: return "memory_write";
 	}
@@ -75,7 +73,6 @@ struct PrintVisitor : FunctionalIR::DefaultVisitor<std::string> {
 	std::string constant(Node, RTLIL::Const value) override { return "constant(" + value.as_string() + ")"; }
 	std::string input(Node, IdString name) override { return "input(" + name.str() + ")"; }
 	std::string state(Node, IdString name) override { return "state(" + name.str() + ")"; }
-	std::string undriven(Node, int width) override { return "undriven(" + std::to_string(width) + ")"; }
 	std::string default_handler(Node self) override {
 		std::string ret = FunctionalIR::fn_to_string(self.fn());
 		ret += "(";
@@ -625,14 +622,11 @@ class FunctionalIRConstruction {
 					factory.suggest_name(node, "$const" + std::to_string(chunk.size()) + "b" + chunk.constant().as_string());
 					factory.update_pending(pending, node);
 				} else if (chunk.is_multiple()) {
-					vector<Node> args;
-					for (auto const &driver : chunk.multiple().multiple())
-						args.push_back(enqueue(driver));
-					Node node = factory.multiple(args, chunk.size());
-					factory.update_pending(pending, node);
+					log_error("Signal %s has multiple drivers. This is not supported by the functional backend. "
+						"If tristate drivers are used, call tristate -formal to avoid this error.\n", log_signal(chunk));
 				} else if (chunk.is_none()) {
-					Node node = factory.undriven(chunk.size());
-					factory.update_pending(pending, node);
+					log_error("The design contains an undriven signal %s. This is not supported by the functional backend. "
+						"Call setundef with appropriate options to avoid this error.\n", log_signal(chunk));
 				} else {
 					log_error("unhandled drivespec: %s\n", log_signal(chunk));
 					log_abort();
diff --git a/kernel/functionalir.h b/kernel/functionalir.h
index d0ec1bce6ba..852937612a7 100644
--- a/kernel/functionalir.h
+++ b/kernel/functionalir.h
@@ -127,12 +127,6 @@ class FunctionalIR {
 		// state(a: IdString): any
 		// returns the current value of the state variable with the specified name
 		state,
-		// multiple(a: any, b: any, c: any, ...): any
-		// indicates a value driven by multiple inputs
-		multiple,
-		// undriven(width: int): bit[width]
-		// indicates an undriven value
-		undriven,
 		// memory_read(memory: memory[addr_width, data_width], addr: bit[addr_width]): bit[data_width] = memory[addr]
 		memory_read,
 		// memory_write(memory: memory[addr_width, data_width], addr: bit[addr_width], data: bit[data_width]): memory[addr_width, data_width]
@@ -277,8 +271,6 @@ class FunctionalIR {
 			case Fn::state: return v.state(*this, _ref.function().as_idstring()); break;
 			case Fn::memory_read: return v.memory_read(*this, arg(0), arg(1)); break;
 			case Fn::memory_write: return v.memory_write(*this, arg(0), arg(1), arg(2)); break;
-			case Fn::multiple: log_error("multiple in visit"); break;
-			case Fn::undriven: return v.undriven(*this, width()); break;
 			}
 		}
 		std::string to_string();
@@ -319,7 +311,6 @@ class FunctionalIR {
 		virtual T state(Node self, IdString name) = 0;
 		virtual T memory_read(Node self, Node mem, Node addr) = 0;
 		virtual T memory_write(Node self, Node mem, Node addr, Node data) = 0;
-		virtual T undriven(Node self, int width) = 0;
 	};
 	// DefaultVisitor provides defaults for all visitor methods which just calls default_handler
 	template<class T> struct DefaultVisitor : public AbstractVisitor<T> {
@@ -357,7 +348,6 @@ class FunctionalIR {
 		T state(Node self, IdString) override { return default_handler(self); }
 		T memory_read(Node self, Node, Node) override { return default_handler(self); }
 		T memory_write(Node self, Node, Node, Node) override { return default_handler(self); }
-		T undriven(Node self, int) override { return default_handler(self); }
 	};
 	// a factory is used to modify a FunctionalIR. it creates new nodes and allows for some modification of existing nodes.
 	class Factory {
@@ -475,15 +465,6 @@ class FunctionalIR {
 			_ir.add_state(name, Sort(addr_width, data_width));
 			return add(NodeData(Fn::state, name), Sort(addr_width, data_width), {});
 		}
-		Node multiple(vector<Node> args, int width) {
-			auto node = add(Fn::multiple, Sort(width), {});
-			for(const auto &arg : args)
-				mutate(node).append_arg(arg._ref);
-			return node;
-		}
-		Node undriven(int width) {
-			return add(Fn::undriven, Sort(width), {});
-		}
 		void declare_output(Node node, IdString name, int width) {
 			_ir.add_output(name, Sort(width));
 			mutate(node).assign_key({name, false});

From 12a31a4418d5fcc33c93cef192fc3066ab999f86 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Wed, 24 Jul 2024 17:23:18 +0100
Subject: [PATCH 419/499] add MemContents class to mem.h

---
 kernel/mem.cc | 216 ++++++++++++++++++++++++++++++++++++++++++++++++++
 kernel/mem.h  | 116 +++++++++++++++++++++++++++
 2 files changed, 332 insertions(+)

diff --git a/kernel/mem.cc b/kernel/mem.cc
index 01c866770f5..46e4331c5a7 100644
--- a/kernel/mem.cc
+++ b/kernel/mem.cc
@@ -1679,3 +1679,219 @@ SigSpec MemWr::decompress_en(const std::vector<int> &swizzle, SigSpec sig) {
 		res.append(sig[i]);
 	return res;
 }
+
+using addr_t = MemContents::addr_t;
+
+MemContents::MemContents(Mem *mem) :
+	MemContents(ceil_log2(mem->size), mem->width)
+{
+	for(const auto &init : mem->inits) {
+		if(init.en.is_fully_zero()) continue;
+		log_assert(init.en.size() == _data_width);
+		if(init.en.is_fully_ones())
+			insert_concatenated(init.addr.as_int(), init.data);
+		else {
+			// TODO: this case could be handled more efficiently by adding
+			// a flag to reserve_range that tells it to preserve
+			// previous contents
+			addr_t addr = init.addr.as_int();
+			addr_t words = init.data.size() / _data_width;
+			RTLIL::Const data = init.data;
+			log_assert(data.size() % _data_width == 0);
+			for(addr_t i = 0; i < words; i++) {
+				RTLIL::Const previous = (*this)[addr + i];
+				for(int j = 0; j < _data_width; j++)
+					if(init.en[j] != State::S1)
+						data[_data_width * i + j] = previous[j];
+			}
+			insert_concatenated(init.addr.as_int(), data);
+		}
+	}
+}
+
+MemContents::iterator & MemContents::iterator::operator++() {
+	auto it = _memory->_values.upper_bound(_addr);
+	if(it == _memory->_values.end()) {
+		_memory = nullptr;
+		_addr = ~(addr_t) 0;
+	} else
+		_addr = it->first;
+	return *this;
+}
+
+void MemContents::check() {
+	log_assert(_addr_width > 0 && _addr_width < (int)sizeof(addr_t) * 8);
+	log_assert(_data_width > 0);
+	log_assert(_default_value.size() == _data_width);
+	if(_values.empty()) return;
+	auto it = _values.begin();
+	for(;;) {
+		log_assert(!it->second.empty());
+		log_assert(it->second.size() % _data_width == 0);
+		auto end1 = _range_end(it);
+		log_assert(_range_begin(it) < (1<<_addr_width));
+		log_assert(end1 <= (1<<_addr_width));
+		if(++it == _values.end())
+			break;
+		// check that ranges neither overlap nor touch
+		log_assert(_range_begin(it) > end1);
+	}
+}
+
+bool MemContents::_range_contains(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) const {
+	// if addr < begin, the subtraction will overflow, and the comparison will always fail
+	// (since we have an invariant that begin + size <= 2^(addr_t bits))
+	return it != _values.end() && addr - _range_begin(it) < _range_size(it);
+}
+
+
+bool MemContents::_range_contains(std::map<addr_t, RTLIL::Const>::iterator it, addr_t begin_addr, addr_t end_addr) const {
+	// note that we assume begin_addr <= end_addr
+	return it != _values.end() && _range_begin(it) <= begin_addr && end_addr - _range_begin(it) <= _range_size(it);
+}
+
+bool MemContents::_range_overlaps(std::map<addr_t, RTLIL::Const>::iterator it, addr_t begin_addr, addr_t end_addr) const {
+	if(it == _values.end() || begin_addr >= end_addr)
+		return false;
+	auto top1 = _range_end(it) - 1;
+	auto top2 = end_addr - 1;
+	return !(top1 < begin_addr || top2 < _range_begin(it));
+}
+
+std::map<addr_t, RTLIL::Const>::iterator MemContents::_range_at(addr_t addr) const {
+	// allow addr == 1<<_addr_width (which will just return end())
+	log_assert(addr <= 1<<_addr_width);
+	// get the first range with base > addr
+	// (we use const_cast since map::iterators are only passed around internally and not exposed to the user
+	// and using map::iterator in both the const and non-const case simplifies the code a little,
+	// at the cost of having to be a little careful when implementing const methods)
+	auto it = const_cast<std::map<addr_t, RTLIL::Const> &>(_values).upper_bound(addr);
+	// if we get the very first range, all ranges are past the addr, so return the first one
+	if(it == _values.begin())
+		return it;
+	// otherwise, go back to the previous interval
+	// this must be the last interval with base <= addr
+	auto it_prev = std::next(it, -1);
+	if(_range_contains(it_prev, addr))
+		return it_prev;
+	else
+		return it;
+}
+
+RTLIL::Const MemContents::operator[](addr_t addr) const {
+	auto it = _range_at(addr);
+	if(_range_contains(it, addr))
+		return it->second.extract(_range_offset(it, addr), _data_width);
+	else
+		return _default_value;
+}
+
+addr_t MemContents::count_range(addr_t begin_addr, addr_t end_addr) const {
+	addr_t count = 0;
+	for(auto it = _range_at(begin_addr); _range_overlaps(it, begin_addr, end_addr); it++) {
+		auto first = std::max(_range_begin(it), begin_addr);
+		auto last = std::min(_range_end(it), end_addr);
+		count += last - first;
+	}
+	return count;
+}
+
+void MemContents::clear_range(addr_t begin_addr, addr_t end_addr) {
+	if(begin_addr >= end_addr) return;
+	// identify which ranges are affected by this operation
+	// the first iterator affected is the first one containing any addr >= begin_addr
+	auto begin_it = _range_at(begin_addr);
+	// the first iterator *not* affected is the first one with base addr > end_addr - 1
+	auto end_it = _values.upper_bound(end_addr - 1);
+	if(begin_it == end_it)
+		return; // nothing to do
+	// the last iterator affected is one before the first one not affected
+	auto last_it = std::next(end_it, -1);
+	// the first and last range may need to be truncated, the rest can just be deleted
+	// to handle the begin_it == last_it case correctly, do the end case first by inserting a new range past the end
+	if(_range_contains(last_it, end_addr - 1)) {
+		auto new_begin = end_addr;
+		auto end = _range_end(last_it);
+		// if there is data past the end address, preserve it by creating a new range
+		if(new_begin != end)
+			end_it = _values.emplace_hint(last_it, new_begin, last_it->second.extract(_range_offset(last_it, new_begin), (_range_end(last_it) - new_begin) * _data_width));
+		// the original range will either be truncated in the next if() block or deleted in the erase, so we can leave it untruncated
+	}
+	if(_range_contains(begin_it, begin_addr)) {
+		auto new_end = begin_addr;
+		// if there is data before the start address, truncate but don't delete
+		if(new_end != begin_it->first) {
+			begin_it->second.extu(_range_offset(begin_it, new_end));
+			++begin_it;
+		}
+		// else: begin_it will be deleted
+	}
+	_values.erase(begin_it, end_it);
+}
+
+std::map<addr_t, RTLIL::Const>::iterator MemContents::_reserve_range(addr_t begin_addr, addr_t end_addr) {
+	if(begin_addr >= end_addr)
+		return _values.end(); // need a dummy value to return, end() is cheap
+	// find the first range containing any addr >= begin_addr - 1
+	auto lower_it = begin_addr == 0 ? _values.begin() : _range_at(begin_addr - 1);
+	// check if our range is already covered by a single range
+	// note that since ranges are not allowed to touch, if any range contains begin_addr, lower_it equals that range
+	if (_range_contains(lower_it, begin_addr, end_addr))
+		return lower_it;
+	// find the first range containing any addr >= end_addr
+	auto upper_it = _range_at(end_addr);
+	// check if either of the two ranges we just found touch our range
+	bool lower_touch = begin_addr > 0 && _range_contains(lower_it, begin_addr - 1);
+	bool upper_touch = _range_contains(upper_it, end_addr);
+	if (lower_touch && upper_touch) {
+		log_assert (lower_it != upper_it); // lower_it == upper_it should be excluded by the check above
+		// we have two different ranges touching at either end, we need to merge them
+		auto upper_end = _range_end(upper_it);
+		// make range bigger (maybe reserve here instead of resize?)
+		lower_it->second.bits.resize(_range_offset(lower_it, upper_end), State::Sx);
+		// copy only the data beyond our range
+		std::copy(_range_data(upper_it, end_addr), _range_data(upper_it, upper_end), _range_data(lower_it, end_addr));
+		// keep lower_it, but delete upper_it
+		_values.erase(std::next(lower_it), std::next(upper_it));
+		return lower_it;
+	} else if (lower_touch) {
+		// we have a range to the left, just make it bigger and delete any other that may exist.
+		lower_it->second.bits.resize(_range_offset(lower_it, end_addr), State::Sx);
+		// keep lower_it and upper_it
+		_values.erase(std::next(lower_it), upper_it);
+		return lower_it;
+	} else if (upper_touch) {
+		// we have a range to the right, we need to expand it
+		// since we need to erase and reinsert to a new address, steal the data
+		RTLIL::Const data = std::move(upper_it->second);
+		// note that begin_addr is not in upper_it, otherwise the whole range covered check would have tripped
+		data.bits.insert(data.bits.begin(), (_range_begin(upper_it) - begin_addr) * _data_width, State::Sx);
+		// delete lower_it and upper_it, then reinsert
+		_values.erase(lower_it, std::next(upper_it));
+		return _values.emplace(begin_addr, std::move(data)).first;
+	} else {
+		// no ranges are touching, so just delete all ranges in our range and allocate a new one
+		// could try to resize an existing range but not sure if that actually helps
+		_values.erase(lower_it, upper_it);
+		return _values.emplace(begin_addr, RTLIL::Const(State::Sx, (end_addr - begin_addr) * _data_width)).first;
+	}
+}
+
+void MemContents::insert_concatenated(addr_t addr, RTLIL::Const const &values) {
+	addr_t words = (values.size() + _data_width - 1) / _data_width;
+	log_assert(addr < 1<<_addr_width);
+	log_assert(words <= (1<<_addr_width) - addr);
+	auto it = _reserve_range(addr, addr + words);
+	auto to_begin = _range_data(it, addr);
+	std::copy(values.bits.begin(), values.bits.end(), to_begin);
+	// if values is not word-aligned, fill any missing bits with 0
+	std::fill(to_begin + values.size(), to_begin + words * _data_width, State::S0);
+}
+
+std::vector<State>::iterator MemContents::_range_write(std::vector<State>::iterator it, RTLIL::Const const &word) {
+	auto from_end = word.size() <= _data_width ? word.bits.end() : word.bits.begin() + _data_width;
+	auto to_end = std::copy(word.bits.begin(), from_end, it);
+	auto it_next = std::next(it, _data_width);
+	std::fill(to_end, it_next, State::S0);
+	return it_next;
+}
\ No newline at end of file
diff --git a/kernel/mem.h b/kernel/mem.h
index 8c484274ccf..4be4b68649e 100644
--- a/kernel/mem.h
+++ b/kernel/mem.h
@@ -224,6 +224,122 @@ struct Mem : RTLIL::AttrObject {
 	Mem(Module *module, IdString memid, int width, int start_offset, int size) : module(module), memid(memid), packed(false), mem(nullptr), cell(nullptr), width(width), start_offset(start_offset), size(size) {}
 };
 
+// this class is used for implementing operator-> on iterators that return values rather than references
+// it's necessary because in C++ operator-> is called recursively until a raw pointer is obtained
+template<class T>
+struct arrow_proxy {
+	T v;
+	explicit arrow_proxy(T const & v) : v(v) {}
+	T* operator->() { return &v; }
+};
+
+// MemContents efficiently represents the contents of a potentially sparse memory by storing only those segments that are actually defined
+class MemContents {
+public:
+	class range; class iterator;
+	using addr_t = uint32_t;
+private:
+	// we ban _addr_width == sizeof(addr_t) * 8 because it adds too many cornercases
+	int _addr_width;
+	int _data_width;
+	RTLIL::Const _default_value;
+	// for each range, store the concatenation of the words at the start address
+	// invariants:
+	// - no overlapping or adjacent ranges
+	// - no empty ranges
+	// - all Consts are a multiple of the word size
+	std::map<addr_t, RTLIL::Const> _values;
+	// returns an iterator to the range containing addr, if it exists, or the first range past addr
+	std::map<addr_t, RTLIL::Const>::iterator _range_at(addr_t addr) const;
+	addr_t _range_size(std::map<addr_t, RTLIL::Const>::iterator it) const { return it->second.size() / _data_width; }
+	addr_t _range_begin(std::map<addr_t, RTLIL::Const>::iterator it) const { return it->first; }
+	addr_t _range_end(std::map<addr_t, RTLIL::Const>::iterator it) const { return _range_begin(it) + _range_size(it); }
+	// check if the iterator points to a range containing addr
+	bool _range_contains(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) const;
+	// check if the iterator points to a range containing [begin_addr, end_addr). assumes end_addr >= begin_addr.
+	bool _range_contains(std::map<addr_t, RTLIL::Const>::iterator it, addr_t begin_addr, addr_t end_addr) const;
+	// check if the iterator points to a range overlapping with [begin_addr, end_addr)
+	bool _range_overlaps(std::map<addr_t, RTLIL::Const>::iterator it, addr_t begin_addr, addr_t end_addr) const;
+	// return the offset the addr would have in the range at `it`
+	size_t _range_offset(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) const { return (addr - it->first) * _data_width; }
+	// assuming _range_contains(it, addr), return an iterator pointing to the data at addr
+	std::vector<State>::iterator _range_data(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) { return it->second.bits.begin() + _range_offset(it, addr); }
+	// internal version of reserve_range that returns an iterator to the range
+	std::map<addr_t, RTLIL::Const>::iterator _reserve_range(addr_t begin_addr, addr_t end_addr);
+	// write a single word at addr, return iterator to next word
+	std::vector<State>::iterator _range_write(std::vector<State>::iterator it, RTLIL::Const const &data);
+public:
+	class range {
+		int _data_width;
+		addr_t _base;
+		RTLIL::Const const &_values;
+		friend class iterator;
+		range(int data_width, addr_t base, RTLIL::Const const &values)
+		: _data_width(data_width), _base(base), _values(values) {}
+	public:
+		addr_t base() const { return _base; }
+		addr_t size() const { return ((addr_t) _values.size()) / _data_width; }
+		addr_t limit() const { return _base + size(); }
+		RTLIL::Const const &concatenated() const { return _values; }
+		RTLIL::Const operator[](addr_t addr) const {
+			log_assert(addr - _base < size());
+			return _values.extract((addr - _base) * _data_width, _data_width);
+		}
+		RTLIL::Const at_offset(addr_t offset) const { return (*this)[_base + offset]; }
+	};
+	class iterator {
+		MemContents const *_memory;
+		// storing addr instead of an iterator gives more well-defined behaviour under insertions/deletions
+		// use ~0 for end so that all end iterators compare the same
+		addr_t _addr;
+		friend class MemContents;
+		iterator(MemContents const *memory, addr_t addr) : _memory(memory), _addr(addr) {}
+	public:
+		using iterator_category = std::input_iterator_tag;
+		using value_type = range;
+		using pointer = arrow_proxy<range>;
+		using reference = range;
+		using difference_type = addr_t;
+		reference operator *() const { return range(_memory->_data_width, _addr, _memory->_values.at(_addr)); }
+		pointer operator->() const { return arrow_proxy<range>(**this); }
+		bool operator !=(iterator const &other) const { return _memory != other._memory || _addr != other._addr; }
+		iterator &operator++();
+	};
+	MemContents(int addr_width, int data_width, RTLIL::Const default_value)
+		: _addr_width(addr_width), _data_width(data_width)
+		, _default_value((default_value.extu(data_width), std::move(default_value)))
+	{ log_assert(_addr_width > 0 && _addr_width < (int)sizeof(addr_t) * 8); log_assert(_data_width > 0); }
+	MemContents(int addr_width, int data_width) : MemContents(addr_width, data_width, RTLIL::Const(State::Sx, data_width)) {}
+	explicit MemContents(Mem *mem);
+	int addr_width() const { return _addr_width; }
+	int data_width() const { return _data_width; }
+	RTLIL::Const const &default_value() const { return _default_value; }
+	// return the value at the address if it exists, the default_value of the memory otherwise. address must not exceed 2**addr_width.
+	RTLIL::Const operator [](addr_t addr) const;
+	// return the number of defined words in the range [begin_addr, end_addr)
+	addr_t count_range(addr_t begin_addr, addr_t end_addr) const;
+	// allocate memory for the range [begin_addr, end_addr), but leave the contents undefined.
+	void reserve_range(addr_t begin_addr, addr_t end_addr) { _reserve_range(begin_addr, end_addr); }
+	// insert multiple words (provided as a single concatenated RTLIL::Const) at the given address, overriding any previous assignment.
+	void insert_concatenated(addr_t addr, RTLIL::Const const &values);
+	// insert multiple words at the given address, overriding any previous assignment.
+	template<typename Iterator> void insert_range(addr_t addr, Iterator begin, Iterator end) {
+		auto words = end - begin;
+		log_assert(addr < 1<<_addr_width); log_assert(words <= (1<<_addr_width) - addr);
+		auto range = _reserve_range(addr, addr + words);
+		auto it = _range_data(range, addr);
+		for(; begin != end; ++begin)
+			it = _range_write(it, *begin);
+	}
+	// undefine all words in the range [begin_addr, end_addr)
+	void clear_range(addr_t begin_addr, addr_t end_addr);
+	// check invariants, abort if invariants failed
+	void check();
+	iterator end() const { return iterator(nullptr, ~(addr_t) 0); }
+	iterator begin() const { return _values.empty() ? end() : iterator(this, _values.begin()->first); }
+	bool empty() const { return _values.empty(); }
+};
+
 YOSYS_NAMESPACE_END
 
 #endif

From bdb59ffc8e82985b99dc9fed3311f177c0caa885 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Wed, 24 Jul 2024 17:33:32 +0100
Subject: [PATCH 420/499] add -fst-noinit flag to sim for not initializing the
 state from the fst file

---
 passes/sat/sim.cc | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index dd17a2eba9d..c83dfe254aa 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -123,6 +123,7 @@ struct SimShared
 	std::vector<TriggeredAssertion> triggered_assertions;
 	std::vector<DisplayOutput> display_output;
 	bool serious_asserts = false;
+	bool fst_noinit = false;
 	bool initstate = true;
 };
 
@@ -1553,7 +1554,7 @@ struct SimWorker : SimShared
 				bool did_something = top->setInputs();
 
 				if (initial) {
-					did_something |= top->setInitState();
+					if (!fst_noinit) did_something |= top->setInitState();
 					initialize_stable_past();
 					initial = false;
 				}
@@ -2688,6 +2689,10 @@ struct SimPass : public Pass {
 		log("        fail the simulation command if, in the course of simulating,\n");
 		log("        any of the asserts in the design fail\n");
 		log("\n");
+		log("    -fst-noinit\n");
+		log("        do not initialize latches and memories from an input FST or VCD file\n");
+		log("        (use the initial defined by the design instead)\n");
+		log("\n");
 		log("    -q\n");
 		log("        disable per-cycle/sample log message\n");
 		log("\n");
@@ -2850,6 +2855,10 @@ struct SimPass : public Pass {
 				worker.serious_asserts = true;
 				continue;
 			}
+			if (args[argidx] == "-fst-noinit") {
+				worker.fst_noinit = true;
+				continue;
+			}
 			if (args[argidx] == "-x") {
 				worker.ignore_x = true;
 				continue;

From 99effb6789b1c3ff62879d5404102da91a2bf70d Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Wed, 24 Jul 2024 17:37:17 +0100
Subject: [PATCH 421/499] add support for initializing registers and memories
 to the functional backend

---
 backends/functional/cxx.cc            | 101 ++++++-----
 backends/functional/cxx_runtime/sim.h |   3 +
 backends/functional/smtlib.cc         |  68 +++++---
 backends/functional/test_generic.cc   |  99 +++++++++++
 kernel/functionalir.cc                |  64 +++----
 kernel/functionalir.h                 |  84 +++++-----
 tests/functional/rtlil_cells.py       |  19 ++-
 tests/functional/smt_vcd.py           |  21 +--
 tests/functional/test_functional.py   |   4 +-
 tests/functional/vcd_harness.cc       | 233 +++++++++++++-------------
 10 files changed, 416 insertions(+), 280 deletions(-)

diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index 69f1973f2cb..324a8831c86 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -69,35 +69,48 @@ struct CxxType {
 using CxxWriter = FunctionalTools::Writer;
 
 struct CxxStruct {
-  std::string name;
-  dict<IdString, CxxType> types;
-  CxxScope<IdString> scope;
-  CxxStruct(std::string name)
-    : name(name) {
-    scope.reserve("fn");
-    scope.reserve("visit");
-  }
-  void insert(IdString name, CxxType type) {
-    scope(name, name);
-    types.insert({name, type});
-  }
-  void print(CxxWriter &f) {
-    f.print("\tstruct {} {{\n", name);
-    for (auto p : types) {
-      f.print("\t\t{} {};\n", p.second.to_string(), scope(p.first, p.first));
-    }
-    f.print("\n\t\ttemplate <typename T> void visit(T &&fn) {{\n");
-    for (auto p : types) {
-      f.print("\t\t\tfn(\"{}\", {});\n", RTLIL::unescape_id(p.first), scope(p.first, p.first));
-    }
-    f.print("\t\t}}\n");
-    f.print("\t}};\n\n");
-  };
-  std::string operator[](IdString field) {
-    return scope(field, field);
-  }
+	std::string name;
+	dict<IdString, CxxType> types;
+	CxxScope<IdString> scope;
+	CxxStruct(std::string name) : name(name)
+	{
+		scope.reserve("fn");
+		scope.reserve("visit");
+	}
+	void insert(IdString name, CxxType type) {
+		scope(name, name);
+		types.insert({name, type});
+	}
+	void print(CxxWriter &f) {
+		f.print("\tstruct {} {{\n", name);
+		for (auto p : types) {
+			f.print("\t\t{} {};\n", p.second.to_string(), scope(p.first, p.first));
+		}
+		f.print("\n\t\ttemplate <typename T> void visit(T &&fn) {{\n");
+		for (auto p : types) {
+			f.print("\t\t\tfn(\"{}\", {});\n", RTLIL::unescape_id(p.first), scope(p.first, p.first));
+		}
+		f.print("\t\t}}\n");
+		f.print("\t}};\n\n");
+	};
+	std::string operator[](IdString field) {
+		return scope(field, field);
+	}
 };
 
+std::string cxx_const(RTLIL::Const const &value) {
+	std::stringstream ss;
+	ss << "Signal<" << value.size() << ">(" << std::hex << std::showbase;
+	if(value.size() > 32) ss << "{";
+	for(int i = 0; i < value.size(); i += 32) {
+		if(i > 0) ss << ", ";
+		ss << value.extract(i, 32).as_int();
+	}
+	if(value.size() > 32) ss << "}";
+	ss << ")";
+	return ss.str();
+}
+
 template<class NodePrinter> struct CxxPrintVisitor : public FunctionalIR::AbstractVisitor<void> {
 	using Node = FunctionalIR::Node;
 	CxxWriter &f;
@@ -136,20 +149,7 @@ template<class NodePrinter> struct CxxPrintVisitor : public FunctionalIR::Abstra
 	void logical_shift_right(Node, Node a, Node b) override { print("{} >> {}", a, b); }
 	void arithmetic_shift_right(Node, Node a, Node b) override { print("{}.arithmetic_shift_right({})", a, b); }
 	void mux(Node, Node a, Node b, Node s) override { print("{2}.any() ? {1} : {0}", a, b, s); }
-	void constant(Node, RTLIL::Const value) override {
-		std::stringstream ss;
-		bool multiple = value.size() > 32;
-		ss << "Signal<" << value.size() << ">(" << std::hex << std::showbase;
-		if(multiple) ss << "{";
-		while(value.size() > 32) {
-			ss << value.as_int() << ", ";
-			value = value.extract(32, value.size() - 32);
-		}
-		ss << value.as_int();
-		if(multiple) ss << "}";
-		ss << ")";
-		print("{}", ss.str());
-	}
+	void constant(Node, RTLIL::Const const & value) override { print("{}", cxx_const(value)); }
 	void input(Node, IdString name) override { print("input.{}", input_struct[name]); }
 	void state(Node, IdString name) override { print("current_state.{}", state_struct[name]); }
 	void memory_read(Node, Node mem, Node addr) override { print("{}.read({})", mem, addr); }
@@ -184,8 +184,24 @@ struct CxxModule {
 		output_struct.print(f);
 		state_struct.print(f);
 		f.print("\tstatic void eval(Inputs const &, Outputs &, State const &, State &);\n");
+		f.print("\tstatic void initialize(State &);\n");
 		f.print("}};\n\n");
 	}
+	void write_initial_def(CxxWriter &f) {
+		f.print("void {0}::initialize({0}::State &state)\n{{\n", module_name);
+		for (auto [name, sort] : ir.state()) {
+			if (sort.is_signal())
+				f.print("\tstate.{} = {};\n", state_struct[name], cxx_const(ir.get_initial_state_signal(name)));
+			else if (sort.is_memory()) {
+				const auto &contents = ir.get_initial_state_memory(name);
+				f.print("\tstate.{}.fill({});\n", state_struct[name], cxx_const(contents.default_value()));
+				for(auto range : contents)
+					for(auto addr = range.base(); addr < range.limit(); addr++)
+						f.print("\tstate.{}[{}] = {};\n", state_struct[name], addr, cxx_const(range[addr]));
+			}
+		}
+		f.print("}}\n\n");
+	}
 	void write_eval_def(CxxWriter &f) {
 		f.print("void {0}::eval({0}::Inputs const &input, {0}::Outputs &output, {0}::State const &current_state, {0}::State &next_state)\n{{\n", module_name);
 		CxxScope<int> locals;
@@ -204,7 +220,7 @@ struct CxxModule {
 			f.print("\tnext_state.{} = {};\n", state_struct[name], node_name(ir.get_state_next_node(name)));
 		for (auto [name, sort] : ir.outputs())
 			f.print("\toutput.{} = {};\n", output_struct[name], node_name(ir.get_output_node(name)));
-		f.print("}}\n");
+		f.print("}}\n\n");
 	}
 };
 
@@ -225,6 +241,7 @@ struct FunctionalCxxBackend : public Backend
 		mod.write_header(f);
 		mod.write_struct_def(f);
 		mod.write_eval_def(f);
+		mod.write_initial_def(f);
 	}
 
 	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h
index ed1a25ed40f..6cce4e8456c 100644
--- a/backends/functional/cxx_runtime/sim.h
+++ b/backends/functional/cxx_runtime/sim.h
@@ -410,6 +410,9 @@ class Memory {
         ret._contents[addr.template as_numeric<size_t>()] = data;
         return ret;
     }
+    // mutating methods for initializing a state
+    void fill(Signal<d> data) { _contents.fill(data); }
+    Signal<d> &operator[](Signal<a> addr) { return _contents[addr.template as_numeric<size_t>()]; }
 };
 
 #endif
diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index d40a4489f6a..0d2763d3201 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -109,6 +109,13 @@ class SmtStruct {
 	}
 };
 
+std::string smt_const(RTLIL::Const const &c) {
+	std::string s = "#b";
+	for(int i = c.size(); i-- > 0; )
+		s += c[i] == State::S1 ? '1' : '0';
+	return s;
+}
+
 struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor<SExpr> {
 	using Node = FunctionalIR::Node;
 	std::function<SExpr(Node)> n;
@@ -117,13 +124,6 @@ struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor<SExpr> {
 
 	SmtPrintVisitor(SmtStruct &input_struct, SmtStruct &state_struct) : input_struct(input_struct), state_struct(state_struct) {}
 
-	std::string literal(RTLIL::Const c) {
-		std::string s = "#b";
-		for(int i = c.size(); i-- > 0; )
-			s += c[i] == State::S1 ? '1' : '0';
-		return s;
-	}
-
 	SExpr from_bool(SExpr &&arg) {
 		return list("ite", std::move(arg), "#b1", "#b0");
 	}
@@ -149,8 +149,8 @@ struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor<SExpr> {
 	SExpr bitwise_xor(Node, Node a, Node b) override { return list("bvxor", n(a), n(b)); }
 	SExpr bitwise_not(Node, Node a) override { return list("bvnot", n(a)); }
 	SExpr unary_minus(Node, Node a) override { return list("bvneg", n(a)); }
-	SExpr reduce_and(Node, Node a) override { return from_bool(list("=", n(a), literal(RTLIL::Const(State::S1, a.width())))); }
-	SExpr reduce_or(Node, Node a) override { return from_bool(list("distinct", n(a), literal(RTLIL::Const(State::S0, a.width())))); }
+	SExpr reduce_and(Node, Node a) override { return from_bool(list("=", n(a), smt_const(RTLIL::Const(State::S1, a.width())))); }
+	SExpr reduce_or(Node, Node a) override { return from_bool(list("distinct", n(a), smt_const(RTLIL::Const(State::S0, a.width())))); }
 	SExpr reduce_xor(Node, Node a) override {
 		vector<SExpr> s { "bvxor" };
 		for(int i = 0; i < a.width(); i++)
@@ -174,7 +174,7 @@ struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor<SExpr> {
 	SExpr logical_shift_right(Node, Node a, Node b) override { return list("bvlshr", n(a), extend(n(b), b.width(), a.width())); }
 	SExpr arithmetic_shift_right(Node, Node a, Node b) override { return list("bvashr", n(a), extend(n(b), b.width(), a.width())); }
 	SExpr mux(Node, Node a, Node b, Node s) override { return list("ite", to_bool(n(s)), n(b), n(a)); }
-	SExpr constant(Node, RTLIL::Const value) override { return literal(value); }
+	SExpr constant(Node, RTLIL::Const const &value) override { return smt_const(value); }
 	SExpr memory_read(Node, Node mem, Node addr) override { return list("select", n(mem), n(addr)); }
 	SExpr memory_write(Node, Node mem, Node addr, Node data) override { return list("store", n(mem), n(addr), n(data)); }
 
@@ -199,6 +199,7 @@ struct SmtModule {
 		, output_struct(scope.unique_name(module->name.str() + "_Outputs"), scope)
 		, state_struct(scope.unique_name(module->name.str() + "_State"), scope)
 	{
+		scope.reserve(name + "-initial");
 		for (const auto &input : ir.inputs())
 			input_struct.insert(input.first, input.second);
 		for (const auto &output : ir.outputs())
@@ -207,18 +208,8 @@ struct SmtModule {
 			state_struct.insert(state.first, state.second);
 	}
 
-	void write(std::ostream &out)
-	{    
-		SExprWriter w(out);
-
-		input_struct.write_definition(w);
-		output_struct.write_definition(w);
-		state_struct.write_definition(w);
-
-		w << list("declare-datatypes",
-			list(list("Pair", 2)),
-			list(list("par", list("X", "Y"), list(list("pair", list("first", "X"), list("second", "Y"))))));
-
+	void write_eval(SExprWriter &w)
+	{
 		w.push();
 		w.open(list("define-fun", name,
 			list(list("inputs", input_struct.name),
@@ -245,6 +236,39 @@ struct SmtModule {
 		state_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.get_state_next_node(name)); });
 		w.pop();
 	}
+
+	void write_initial(SExprWriter &w)
+	{
+		std::string initial = name + "-initial";
+		w << list("declare-const", initial, state_struct.name);
+		for (const auto &[name, sort] : ir.state()) {
+			if(sort.is_signal())
+				w << list("assert", list("=", state_struct.access(initial, name), smt_const(ir.get_initial_state_signal(name))));
+			else if(sort.is_memory()) {
+				auto contents = ir.get_initial_state_memory(name);
+				for(int i = 0; i < 1<<sort.addr_width(); i++) {
+					auto addr = smt_const(RTLIL::Const(i, sort.addr_width()));
+					w << list("assert", list("=", list("select", state_struct.access(initial, name), addr), smt_const(contents[i])));
+				}
+			}
+		}
+	}
+
+	void write(std::ostream &out)
+	{    
+		SExprWriter w(out);
+
+		input_struct.write_definition(w);
+		output_struct.write_definition(w);
+		state_struct.write_definition(w);
+
+		w << list("declare-datatypes",
+			list(list("Pair", 2)),
+			list(list("par", list("X", "Y"), list(list("pair", list("first", "X"), list("second", "Y"))))));
+		
+		write_eval(w);
+		write_initial(w);
+	}
 };
 
 struct FunctionalSmtBackend : public Backend {
diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc
index 172ac7fd6f5..ba713b36c32 100644
--- a/backends/functional/test_generic.cc
+++ b/backends/functional/test_generic.cc
@@ -19,10 +19,100 @@
 
 #include "kernel/yosys.h"
 #include "kernel/functionalir.h"
+#include <random>
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+struct MemContentsTest {
+	int addr_width, data_width;
+	MemContents state;
+	using addr_t = MemContents::addr_t;
+	std::map<addr_t, RTLIL::Const> reference;
+	MemContentsTest(int addr_width, int data_width) : addr_width(addr_width), data_width(data_width), state(addr_width, data_width, RTLIL::Const(State::S0, data_width))  {}
+	void check() {
+		state.check();
+		for(auto addr = 0; addr < (1<<addr_width); addr++) {
+			auto it = reference.find(addr);
+			if(it != reference.end()) {
+				if(state.count_range(addr, addr + 1) != 1) goto error;
+				if(it->second != state[addr]) goto error;
+			} else {
+				if(state.count_range(addr, addr + 1) != 0) goto error;
+			}
+		}
+		return;
+		error:
+		printf("FAIL\n");
+		int digits = (data_width + 3) / 4;
+		
+		for(auto addr = 0; addr < (1<<addr_width); addr++) {
+			if(addr % 8 == 0) printf("%.8x   ", addr);
+			auto it = reference.find(addr);
+			bool ref_def = it != reference.end();
+			RTLIL::Const ref_value = ref_def ? it->second : state.default_value();
+			std::string ref_string = stringf("%.*x", digits, ref_value.as_int());
+			bool sta_def = state.count_range(addr, addr + 1) == 1;
+			RTLIL::Const sta_value = state[addr];
+			std::string sta_string = stringf("%.*x", digits, sta_value.as_int());
+			if(ref_def && sta_def) {
+				if(ref_value == sta_value) printf("%s%s", ref_string.c_str(), string(digits, ' ').c_str());
+				else printf("%s%s", ref_string.c_str(), sta_string.c_str());
+			} else if(ref_def) {
+				printf("%s%s", ref_string.c_str(), string(digits, 'M').c_str());
+			} else if(sta_def) {
+				printf("%s%s", sta_string.c_str(), string(digits, 'X').c_str());
+			} else {
+				printf("%s", string(2*digits, ' ').c_str());
+			}
+			printf(" ");
+			if(addr % 8 == 7) printf("\n");
+		}
+		printf("\n");
+		//log_abort();
+	}
+	void clear_range(addr_t begin_addr, addr_t end_addr) {
+		for(auto addr = begin_addr; addr != end_addr; addr++)
+			reference.erase(addr);
+		state.clear_range(begin_addr, end_addr);
+		check();
+	}
+	void insert_concatenated(addr_t addr, RTLIL::Const const &values) {
+		addr_t words = ((addr_t) values.size() + data_width - 1) / data_width;
+		for(addr_t i = 0; i < words; i++) {
+			reference.erase(addr + i);
+			reference.emplace(addr + i, values.extract(i * data_width, data_width));
+		}
+		state.insert_concatenated(addr, values);
+		check();
+	}
+	template<typename Rnd> void run(Rnd &rnd, int n) {
+		std::uniform_int_distribution<addr_t> addr_dist(0, (1<<addr_width) - 1);
+		std::poisson_distribution<addr_t> length_dist(10);
+		std::uniform_int_distribution<uint64_t> data_dist(0, ((uint64_t)1<<data_width) - 1);
+		while(n-- > 0) {
+			addr_t low = addr_dist(rnd);
+			//addr_t length = std::min((1<<addr_width) - low, length_dist(rnd));
+			//addr_t high = low + length - 1;
+			addr_t high = addr_dist(rnd);
+			if(low > high) std::swap(low, high);
+			if((rnd() & 7) == 0) {
+				log_debug("clear %.2x to %.2x\n", (int)low, (int)high);
+				clear_range(low, high + 1);
+			} else {
+				log_debug("insert %.2x to %.2x\n", (int)low, (int)high);
+				RTLIL::Const values;
+				for(addr_t addr = low; addr <= high; addr++) {
+					RTLIL::Const word(data_dist(rnd), data_width);
+					values.bits.insert(values.bits.end(), word.bits.begin(), word.bits.end());
+				}
+				insert_concatenated(low, values);
+			}
+		}
+	}
+
+};
+
 struct FunctionalTestGeneric : public Pass
 {
 	FunctionalTestGeneric() : Pass("test_generic", "test the generic compute graph") {}
@@ -40,6 +130,14 @@ struct FunctionalTestGeneric : public Pass
 		size_t argidx = 1;
 		extra_args(args, argidx, design);
 
+		MemContentsTest test(8, 16);
+
+		std::random_device seed_dev;
+		std::mt19937 rnd(23); //seed_dev());
+		test.run(rnd, 1000);
+
+/*
+
 		for (auto module : design->selected_modules()) {
             log("Dumping module `%s'.\n", module->name.c_str());
 			auto fir = FunctionalIR::from_module(module);
@@ -50,6 +148,7 @@ struct FunctionalTestGeneric : public Pass
 			for(auto [name, sort] : fir.state())
 				std::cout << RTLIL::unescape_id(name) << " = " << RTLIL::unescape_id(fir.get_state_next_node(name).name()) << "\n";
 		}
+*/
 	}
 } FunctionalCxxBackend;
 
diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc
index 155cb3bbc53..bc21b4d3648 100644
--- a/kernel/functionalir.cc
+++ b/kernel/functionalir.cc
@@ -19,6 +19,8 @@
 
 #include "kernel/functionalir.h"
 #include <optional>
+#include "ff.h"
+#include "ffinit.h"
 
 YOSYS_NAMESPACE_BEGIN
 
@@ -70,7 +72,7 @@ struct PrintVisitor : FunctionalIR::DefaultVisitor<std::string> {
 	std::string slice(Node, Node a, int offset, int out_width) override { return "slice(" + np(a) + ", " + std::to_string(offset) + ", " + std::to_string(out_width) + ")"; }
 	std::string zero_extend(Node, Node a, int out_width) override { return "zero_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; }
 	std::string sign_extend(Node, Node a, int out_width) override { return "sign_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; }
-	std::string constant(Node, RTLIL::Const value) override { return "constant(" + value.as_string() + ")"; }
+	std::string constant(Node, RTLIL::Const const& value) override { return "constant(" + value.as_string() + ")"; }
 	std::string input(Node, IdString name) override { return "input(" + name.str() + ")"; }
 	std::string state(Node, IdString name) override { return "state(" + name.str() + ")"; }
 	std::string default_handler(Node self) override {
@@ -407,6 +409,8 @@ class FunctionalIRConstruction {
 	CellSimplifier simplifier;
 	vector<Mem> memories_vector;
 	dict<Cell*, Mem*> memories;
+	SigMap sig_map; // TODO: this is only for FfInitVals, remove this once FfInitVals supports DriverMap
+	FfInitVals ff_initvals;
 
 	Node enqueue(DriveSpec const &spec)
 	{
@@ -438,8 +442,11 @@ class FunctionalIRConstruction {
 			return it->second;
 	}
 public:
-	FunctionalIRConstruction(FunctionalIR::Factory &f) : factory(f), simplifier(f) {}
-	void add_module(Module *module)
+	FunctionalIRConstruction(Module *module, FunctionalIR::Factory &f)
+		: factory(f)
+		, simplifier(f)
+		, sig_map(module)
+		, ff_initvals(&sig_map, module)
 	{
 		driver_map.add(module);
 		for (auto cell : module->cells()) {
@@ -447,9 +454,12 @@ class FunctionalIRConstruction {
 				queue.emplace_back(cell);
 		}
 		for (auto wire : module->wires()) {
+			if (wire->port_input)
+				factory.add_input(wire->name, wire->width);
 			if (wire->port_output) {
-				Node node = enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width)));
-				factory.declare_output(node, wire->name, wire->width);
+				factory.add_output(wire->name, wire->width);
+				Node value = enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width)));
+				factory.set_output(wire->name, value);
 			}
 		}
 		memories_vector = Mem::get_all_memories(module);
@@ -487,9 +497,9 @@ class FunctionalIRConstruction {
 		// - Since wr port j can only have priority over wr port i if j > i, if we do writes in
 		//   ascending index order the result will obey the priorty relation.
 		vector<Node> read_results;
-		int addr_width = ceil_log2(mem->size);
-		int data_width = mem->width;
-		Node node = factory.state_memory(mem->cell->name, addr_width, data_width);
+		factory.add_state(mem->cell->name, FunctionalIR::Sort(ceil_log2(mem->size), mem->width));
+		factory.set_initial_state(mem->cell->name, MemContents(mem));
+		Node node = factory.get_current_state(mem->cell->name);
 		for (size_t i = 0; i < mem->wr_ports.size(); i++) {
 			const auto &wr = mem->wr_ports[i];
 			if (wr.clk_enable)
@@ -513,7 +523,7 @@ class FunctionalIRConstruction {
 			Node addr = enqueue(driver_map(DriveSpec(rd.addr)));
 			read_results.push_back(factory.memory_read(node, addr));
 		}
-		factory.declare_state_memory(node, mem->cell->name, addr_width, data_width);
+		factory.set_next_state(mem->cell->name, node);
 		return concatenate_read_results(mem, read_results);
 	}
 	void process_cell(Cell *cell)
@@ -527,6 +537,17 @@ class FunctionalIRConstruction {
 			}
 			Node node = handle_memory(mem);
 			factory.update_pending(cell_outputs.at({cell, ID(RD_DATA)}), node);
+		} else if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
+			FfData ff(&ff_initvals, cell);
+			if (!ff.has_gclk)
+				log_error("The design contains a %s flip-flop at %s. This is not supported by the functional backend. "
+					"Call async2sync or clk2fflogic to avoid this error.\n", log_id(cell->type), log_id(cell));
+			factory.add_state(ff.name, FunctionalIR::Sort(ff.width));
+			Node q_value = factory.get_current_state(ff.name);
+			factory.suggest_name(q_value, ff.name);
+			factory.update_pending(cell_outputs.at({cell, ID(Q)}), q_value);
+			factory.set_next_state(ff.name, enqueue(ff.sig_d));
+			factory.set_initial_state(ff.name, ff.val_init);
 		} else {
 			dict<IdString, Node> connections;
 			IdString output_name; // for the single output case
@@ -572,7 +593,7 @@ class FunctionalIRConstruction {
 					DriveChunkWire wire_chunk = chunk.wire();
 					if (wire_chunk.is_whole()) {
 						if (wire_chunk.wire->port_input) {
-							Node node = factory.input(wire_chunk.wire->name, wire_chunk.width);
+							Node node = factory.get_input(wire_chunk.wire->name);
 							factory.suggest_name(node, wire_chunk.wire->name);
 							factory.update_pending(pending, node);
 						} else {
@@ -590,24 +611,8 @@ class FunctionalIRConstruction {
 					DriveChunkPort port_chunk = chunk.port();
 					if (port_chunk.is_whole()) {
 						if (driver_map.celltypes.cell_output(port_chunk.cell->type, port_chunk.port)) {
-							if (port_chunk.cell->type.in(ID($dff), ID($ff)))
-							{
-								Cell *cell = port_chunk.cell;
-								Node node = factory.state(cell->name, port_chunk.width);
-								factory.suggest_name(node, port_chunk.cell->name);
-								factory.update_pending(pending, node);
-								for (auto const &conn : cell->connections()) {
-									if (driver_map.celltypes.cell_input(cell->type, conn.first)) {
-										Node node = enqueue(DriveChunkPort(cell, conn));
-										factory.declare_state(node, cell->name, port_chunk.width);
-									}
-								}
-							}
-							else
-							{
-								Node node = enqueue_cell(port_chunk.cell, port_chunk.port);
-								factory.update_pending(pending, node);
-							}
+							Node node = enqueue_cell(port_chunk.cell, port_chunk.port);
+							factory.update_pending(pending, node);
 						} else {
 							DriveSpec driver = driver_map(DriveSpec(port_chunk));
 							factory.update_pending(pending, enqueue(driver));
@@ -641,8 +646,7 @@ class FunctionalIRConstruction {
 FunctionalIR FunctionalIR::from_module(Module *module) {
     FunctionalIR ir;
     auto factory = ir.factory();
-    FunctionalIRConstruction ctor(factory);
-    ctor.add_module(module);
+    FunctionalIRConstruction ctor(module, factory);
     ctor.process_queue();
     ir.topological_sort();
     ir.forward_buf();
diff --git a/kernel/functionalir.h b/kernel/functionalir.h
index 852937612a7..e0af89d9f3a 100644
--- a/kernel/functionalir.h
+++ b/kernel/functionalir.h
@@ -189,24 +189,11 @@ class FunctionalIR {
 	// the bool is true for next state values
 	using Graph = ComputeGraph<NodeData, Attr, IdString, std::pair<IdString, bool>>;
 	Graph _graph;
-	dict<IdString, Sort> _inputs;
-	dict<IdString, Sort> _outputs;
-	dict<IdString, Sort> _state;
-	void add_input(IdString name, Sort sort) {
-		auto [it, found] = _inputs.emplace(name, std::move(sort));
-		if(found)
-			log_assert(it->second == sort);
-	}
-	void add_state(IdString name, Sort sort) {
-		auto [it, found] = _state.emplace(name, std::move(sort));
-		if(found)
-			log_assert(it->second == sort);
-	}
-	void add_output(IdString name, Sort sort) {
-		auto [it, found] = _outputs.emplace(name, std::move(sort));
-		if(found)
-			log_assert(it->second == sort);
-	}
+	dict<IdString, Sort> _input_sorts;
+	dict<IdString, Sort> _output_sorts;
+	dict<IdString, Sort> _state_sorts;
+	dict<IdString, RTLIL::Const> _initial_state_signal;
+	dict<IdString, MemContents> _initial_state_memory;
 public:
 	class Factory;
 	// Node is an immutable reference to a FunctionalIR node
@@ -306,7 +293,7 @@ class FunctionalIR {
 		virtual T logical_shift_right(Node self, Node a, Node b) = 0;
 		virtual T arithmetic_shift_right(Node self, Node a, Node b) = 0;
 		virtual T mux(Node self, Node a, Node b, Node s) = 0;
-		virtual T constant(Node self, RTLIL::Const value) = 0;
+		virtual T constant(Node self, RTLIL::Const const & value) = 0;
 		virtual T input(Node self, IdString name) = 0;
 		virtual T state(Node self, IdString name) = 0;
 		virtual T memory_read(Node self, Node mem, Node addr) = 0;
@@ -343,7 +330,7 @@ class FunctionalIR {
 		T logical_shift_right(Node self, Node, Node) override { return default_handler(self); }
 		T arithmetic_shift_right(Node self, Node, Node) override { return default_handler(self); }
 		T mux(Node self, Node, Node, Node) override { return default_handler(self); }
-		T constant(Node self, RTLIL::Const) override { return default_handler(self); }
+		T constant(Node self, RTLIL::Const const &) override { return default_handler(self); }
 		T input(Node self, IdString) override { return default_handler(self); }
 		T state(Node self, IdString) override { return default_handler(self); }
 		T memory_read(Node self, Node, Node) override { return default_handler(self); }
@@ -452,30 +439,41 @@ class FunctionalIR {
 			log_assert(node._ref.function() == Fn::buf && node._ref.size() == 0);
 			log_assert(node.sort() == value.sort());
 			mutate(node).append_arg(value._ref);
-		} 
-		Node input(IdString name, int width) {
-			_ir.add_input(name, Sort(width));
-			return add(NodeData(Fn::input, name), Sort(width), {});
 		}
-		Node state(IdString name, int width) {
-			_ir.add_state(name, Sort(width));
-			return add(NodeData(Fn::state, name), Sort(width), {});
+		void add_input(IdString name, int width) {
+			auto [it, inserted] = _ir._input_sorts.emplace(name, Sort(width));
+			if (!inserted) log_error("input `%s` was re-defined", name.c_str());
 		}
-		Node state_memory(IdString name, int addr_width, int data_width) {
-			_ir.add_state(name, Sort(addr_width, data_width));
-			return add(NodeData(Fn::state, name), Sort(addr_width, data_width), {});
+		void add_output(IdString name, int width) {
+			auto [it, inserted] = _ir._output_sorts.emplace(name, Sort(width));
+			if (!inserted) log_error("output `%s` was re-defined", name.c_str());
 		}
-		void declare_output(Node node, IdString name, int width) {
-			_ir.add_output(name, Sort(width));
-			mutate(node).assign_key({name, false});
+		void add_state(IdString name, Sort sort) {
+			auto [it, inserted] = _ir._state_sorts.emplace(name, sort);
+			if (!inserted) log_error("state `%s` was re-defined", name.c_str());
 		}
-		void declare_state(Node node, IdString name, int width) {
-			_ir.add_state(name, Sort(width));
-			mutate(node).assign_key({name, true});
+		Node get_input(IdString name) {
+			return add(NodeData(Fn::input, name), Sort(_ir._input_sorts.at(name)), {});
 		}
-		void declare_state_memory(Node node, IdString name, int addr_width, int data_width) {
-			_ir.add_state(name, Sort(addr_width, data_width));
-			mutate(node).assign_key({name, true});
+		Node get_current_state(IdString name) {
+			return add(NodeData(Fn::state, name), Sort(_ir._state_sorts.at(name)), {});
+		}
+		void set_output(IdString output, Node value) {
+			log_assert(_ir._output_sorts.at(output) == value.sort());
+			mutate(value).assign_key({output, false});
+		}
+		void set_initial_state(IdString state, RTLIL::Const value) {
+			Sort &sort = _ir._state_sorts.at(state);
+			value.extu(sort.width());
+			_ir._initial_state_signal.emplace(state, std::move(value));
+		}
+		void set_initial_state(IdString state, MemContents value) {
+			log_assert(Sort(value.addr_width(), value.data_width()) == _ir._state_sorts.at(state));
+			_ir._initial_state_memory.emplace(state, std::move(value));
+		}
+		void set_next_state(IdString state, Node value) {
+			log_assert(_ir._state_sorts.at(state) == value.sort());
+			mutate(value).assign_key({state, true});
 		}
 		void suggest_name(Node node, IdString name) {
 			mutate(node).sparse_attr() = name;
@@ -487,9 +485,11 @@ class FunctionalIR {
 	Node operator[](int i) { return Node(_graph[i]); }
 	void topological_sort();
 	void forward_buf();
-	dict<IdString, Sort> inputs() const { return _inputs; }
-	dict<IdString, Sort> outputs() const { return _outputs; }
-	dict<IdString, Sort> state() const { return _state; }
+	dict<IdString, Sort> inputs() const { return _input_sorts; }
+	dict<IdString, Sort> outputs() const { return _output_sorts; }
+	dict<IdString, Sort> state() const { return _state_sorts; }
+	RTLIL::Const  const &get_initial_state_signal(IdString name) { return _initial_state_signal.at(name); }
+	MemContents const &get_initial_state_memory(IdString name) { return _initial_state_memory.at(name); }
 	Node get_output_node(IdString name) { return Node(_graph({name, false})); }
 	Node get_state_next_node(IdString name) { return Node(_graph({name, true})); }
 	class Iterator {
diff --git a/tests/functional/rtlil_cells.py b/tests/functional/rtlil_cells.py
index 90417579e5d..ed867b695b4 100644
--- a/tests/functional/rtlil_cells.py
+++ b/tests/functional/rtlil_cells.py
@@ -153,15 +153,17 @@ def write_rtlil_file(self, path, parameters):
         from test_functional import yosys_synth
         verilog_file = path.parent / 'verilog.v'
         with open(verilog_file, 'w') as f:
-            f.write("""
+            width = parameters['WIDTH']
+            f.write(f"""
 module gold(
     input wire clk,
-    input wire [{0}:0] D,
-    output reg [{0}:0] Q
+    input wire [{width-1}:0] D,
+    output reg [{width-1}:0] Q
 );
+    initial Q = {width}'b{("101" * width)[:width]};
     always @(posedge clk)
         Q <= D;
-endmodule""".format(parameters['WIDTH'] - 1))
+endmodule""")
         yosys_synth(verilog_file, path)
 
 class MemCell(BaseCell):
@@ -180,6 +182,10 @@ def write_rtlil_file(self, path, parameters):
     output reg [{0}:0] RD
 );
     reg [{0}:0] mem[0:{2}];
+    integer i;
+    initial
+        for(i = 0; i <= {2}; i = i + 1)
+            mem[i] = 9192 * (i + 1);
     always @(*)
         RD = mem[RA];
     always @(posedge clk)
@@ -211,8 +217,11 @@ def write_rtlil_file(self, path, parameters):
     output reg [{0}:0] RD1,
     output reg [{0}:0] RD2
 );
-                    (*keep*)
     reg [{0}:0] mem[0:{2}];
+    integer i;
+    initial
+        for(i = 0; i <= {2}; i = i + 1)
+            mem[i] = 9192 * (i + 1);
     always @(*)
         RD1 = mem[RA1];
     always @(*)
diff --git a/tests/functional/smt_vcd.py b/tests/functional/smt_vcd.py
index 37d2a209f71..c23be440e3b 100644
--- a/tests/functional/smt_vcd.py
+++ b/tests/functional/smt_vcd.py
@@ -81,25 +81,6 @@ def handle_datatype(lst):
     parser.finish()
     assert smt_io.check_sat() == 'sat'
 
-    def initial_state(states):
-        mk_state_parts = []
-        rv = []
-        for name, width in states.items():
-            if isinstance(width, int):
-                binary_string = format(0, '0{}b'.format(width))
-                mk_state_parts.append(f"#b{binary_string}")
-            else:
-                binary_string = format(0, '0{}b'.format(width[1]))
-                rv.append(f"(declare-const test_state_initial_mem_{name} (Array (_ BitVec {width[0]}) (_ BitVec {width[1]})))")
-                rv.append(f"(assert (forall ((i (_ BitVec {width[0]}))) (= (select test_state_initial_mem_{name} i) #b{binary_string})))")
-                mk_state_parts.append(f"test_state_initial_mem_{name}")
-        if len(states) == 0:
-            mk_state_call = "gold_State"
-        else:
-            mk_state_call = "(gold_State {})".format(" ".join(mk_state_parts))
-        rv.append(f"(define-const test_state_step_n0 gold_State {mk_state_call})\n")
-        return rv
-
     def set_step(inputs, step):
         # This function assumes 'inputs' is a dictionary like {"A": 5, "B": 4}
         # and 'input_values' is a dictionary like {"A": 5, "B": 13} specifying the concrete values for each input.
@@ -118,7 +99,7 @@ def set_step(inputs, step):
             f"(define-const test_state_step_n{step+1} gold_State (second test_results_step_n{step}))\n",
         ]
 
-    smt_commands = initial_state(states)
+    smt_commands = [f"(define-const test_state_step_n0 gold_State gold-initial)\n"]
     for step in range(num_steps):
         for step_command in set_step(inputs, step):
             smt_commands.append(step_command)
diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py
index c31f4b86f5c..7bfe19fc494 100644
--- a/tests/functional/test_functional.py
+++ b/tests/functional/test_functional.py
@@ -29,14 +29,14 @@ def yosys_synth(verilog_file, rtlil_file):
 # simulate an rtlil file with yosys, comparing with a given vcd file, and writing out the yosys simulation results into a second vcd file
 def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""):
     try:
-        yosys(f"read_rtlil {quote(rtlil_file)}; {preprocessing}; sim -r {quote(vcd_reference_file)} -scope gold -vcd {quote(vcd_out_file)} -timescale 1us -sim-gold")
+        yosys(f"read_rtlil {quote(rtlil_file)}; {preprocessing}; sim -r {quote(vcd_reference_file)} -scope gold -vcd {quote(vcd_out_file)} -timescale 1us -sim-gold -fst-noinit")
     except:
         # if yosys sim fails it's probably because of a simulation mismatch
         # since yosys sim aborts on simulation mismatch to generate vcd output
         # we have to re-run with a different set of flags
         # on this run we ignore output and return code, we just want a best-effort attempt to get a vcd
         subprocess.run([base_path / 'yosys', '-Q', '-p',
-            f'read_rtlil {quote(rtlil_file)}; sim -vcd {quote(vcd_out_file)} -a -r {quote(vcd_reference_file)} -scope gold -timescale 1us'],
+            f'read_rtlil {quote(rtlil_file)}; sim -vcd {quote(vcd_out_file)} -a -r {quote(vcd_reference_file)} -scope gold -timescale 1us -fst-noinit'],
             capture_output=True, check=False)
         raise
 
diff --git a/tests/functional/vcd_harness.cc b/tests/functional/vcd_harness.cc
index f01adf21832..7232172348a 100644
--- a/tests/functional/vcd_harness.cc
+++ b/tests/functional/vcd_harness.cc
@@ -7,140 +7,139 @@
 
 #include "my_module_functional_cxx.cc"
 
-std::string vcd_name_mangle(std::string name) {
-  std::string ret = name;
-  bool escape = ret.empty() || !isalpha(ret[0]) && ret[0] != '_';
-  for(size_t i = 0; i < ret.size(); i++) {
-    if(isspace(ret[i])) ret[i] = '_';
-    if(!isalnum(ret[i]) && ret[i] != '_' && ret[i] != '$')
-      escape = true;
-  }
-  if(escape)
-    return "\\" + ret;
-  else
-    return ret;
-}
-std::unordered_map<std::string, std::string> codes; 
-
-struct DumpHeader {
-  std::ofstream &ofs;
-  std::string code = "!";
-  DumpHeader(std::ofstream &ofs) : ofs(ofs) {}
-  void increment_code() {
-    for(size_t i = 0; i < code.size(); i++)
-      if(code[i]++ == '~')
-        code[i] = '!';
-      else
-        return;
-    code.push_back('!');
-  }
-  template <size_t n>
-  void operator()(const char *name, Signal<n> value) {
-    ofs << "$var wire " << n << " " << code << " " << vcd_name_mangle(name) << " $end\n";
-    codes[name] = code;
-    increment_code();
-  }
-  template <size_t n, size_t m>
-  void operator()(const char *name, Memory<n, m> value) {
-  }
-};
-
-struct Dump {
-  std::ofstream &ofs;
-  Dump(std::ofstream &ofs) : ofs(ofs) {}
-  template <size_t n>
-  void operator()(const char *name, Signal<n> value) {
-    // Bit
-    if (n == 1) {
-      ofs << (value[0] ? '1' : '0');
-      ofs << codes[name] << "\n";
-      return;
-    }
-    // vector (multi-bit) signals
-    ofs << "b";
-    for (size_t i = n; i-- > 0;)
-      ofs << (value[i] ? '1' : '0');
-    ofs << " " << codes[name] << "\n";
-  }
-  template <size_t n, size_t m>
-  void operator()(const char *name, Memory<n, m> value) {
-  }
+class VcdFile {
+	std::ofstream &ofs;
+	std::string code_alloc = "!";
+	std::unordered_map<std::string, std::string> codes;
+	std::string name_mangle(std::string name) {
+		std::string ret = name;
+		bool escape = ret.empty() || !isalpha(ret[0]) && ret[0] != '_';
+		for(size_t i = 0; i < ret.size(); i++) {
+			if(isspace(ret[i])) ret[i] = '_';
+			if(!isalnum(ret[i]) && ret[i] != '_' && ret[i] != '$')
+			escape = true;
+		}
+		if(escape)
+			return "\\" + ret;
+		else
+			return ret;
+	}
+	std::string allocate_code() {
+		std::string ret = code_alloc;
+		for (size_t i = 0; i < code_alloc.size(); i++)
+			if (code_alloc[i]++ == '~')
+				code_alloc[i] = '!';
+			else
+				return ret;
+		code_alloc.push_back('!');
+		return ret;
+	}
+public:
+	VcdFile(std::ofstream &ofs) : ofs(ofs) {}
+	struct DumpHeader {
+		VcdFile *file;
+		explicit DumpHeader(VcdFile *file) : file(file) {}
+		template <size_t n> void operator()(const char *name, Signal<n> value)
+		{
+			auto it = file->codes.find(name);
+			if(it == file->codes.end())
+				it = file->codes.emplace(name, file->allocate_code()).first;
+			file->ofs << "$var wire " << n << " " << it->second << " " << file->name_mangle(name) << " $end\n";
+		}
+		template <size_t n, size_t m> void operator()(const char *name, Memory<n, m> value) {}
+	};
+	struct Dump {
+		VcdFile *file;
+		explicit Dump(VcdFile *file) : file(file) {}
+		template <size_t n> void operator()(const char *name, Signal<n> value)
+		{
+			if (n == 1) {
+				file->ofs << (value[0] ? '1' : '0');
+				file->ofs << file->codes.at(name) << "\n";
+			} else {
+				file->ofs << "b";
+				for (size_t i = n; i-- > 0;)
+					file->ofs << (value[i] ? '1' : '0');
+				file->ofs << " " << file->codes.at(name) << "\n";
+			}
+		}
+		template <size_t n, size_t m> void operator()(const char *name, Memory<n, m> value) {}
+	};
+	void begin_header() {
+		constexpr int number_timescale = 1;
+		const std::string units_timescale = "us";
+		ofs << "$timescale " << number_timescale << " " << units_timescale << " $end\n";
+		ofs << "$scope module gold $end\n";
+	}
+	void end_header() {
+		ofs << "$enddefinitions $end\n$dumpvars\n";
+	}
+	template<typename... Args> void header(Args ...args) {
+		begin_header();
+		DumpHeader d(this);
+		(args.visit(d), ...);
+		end_header();
+	}
+	void begin_data(int step) {
+		ofs << "#" << step << "\n";
+	}
+	template<typename... Args> void data(int step, Args ...args) {
+		begin_data(step);
+		Dump d(this);
+		(args.visit(d), ...);
+	}
+	DumpHeader dump_header() { return DumpHeader(this); }
+	Dump dump() { return Dump(this); }
 };
 
-template<size_t n>
-Signal<n> random_signal(std::mt19937 &gen) {
-  std::uniform_int_distribution<uint32_t> dist;
-  std::array<uint32_t, (n+31)/32> words;
-  for(auto &w : words)
-    w = dist(gen);
-  return Signal<n>::from_array(words);
+template <size_t n> Signal<n> random_signal(std::mt19937 &gen)
+{
+	std::uniform_int_distribution<uint32_t> dist;
+	std::array<uint32_t, (n + 31) / 32> words;
+	for (auto &w : words)
+		w = dist(gen);
+	return Signal<n>::from_array(words);
 }
 
-struct Reset {
-  template <size_t n>
-  void operator()(const char *, Signal<n> &signal) {
-    signal = 0;
-  }
-};
-
 struct Randomize {
-  std::mt19937 &gen;
-  Randomize(std::mt19937 &gen) : gen(gen) {}
+	std::mt19937 &gen;
+	Randomize(std::mt19937 &gen) : gen(gen) {}
 
-  template <size_t n>
-  void operator()(const char *, Signal<n> &signal) {
-    signal = random_signal<n>(gen);
-  }
+	template <size_t n> void operator()(const char *, Signal<n> &signal) { signal = random_signal<n>(gen); }
 };
 
 int main(int argc, char **argv)
 {
-  if (argc != 4) {
-    std::cerr << "Usage: " << argv[0] << " <functional_vcd_filename> <steps> <seed>\n";
-    return 1;
-  }
+	if (argc != 4) {
+		std::cerr << "Usage: " << argv[0] << " <functional_vcd_filename> <steps> <seed>\n";
+		return 1;
+	}
 
-  const std::string functional_vcd_filename = argv[1];
-  const int steps = atoi(argv[2]);
-  const uint32_t seed = atoi(argv[3]);
+	const std::string functional_vcd_filename = argv[1];
+	const int steps = atoi(argv[2]);
+	const uint32_t seed = atoi(argv[3]);
 
-  constexpr int number_timescale = 1;
-  const std::string units_timescale = "us";
-  gold::Inputs inputs;
-  gold::Outputs outputs;
-  gold::State state;
-  gold::State next_state;
+	gold::Inputs inputs;
+	gold::Outputs outputs;
+	gold::State state;
+	gold::State next_state;
 
-  std::ofstream vcd_file(functional_vcd_filename);
+	std::ofstream vcd_file(functional_vcd_filename);
+	VcdFile vcd(vcd_file);
+	vcd.header(inputs, outputs, state);
 
-  vcd_file << "$timescale " << number_timescale << " " << units_timescale << " $end\n";
-  vcd_file << "$scope module gold $end\n";
-  {
-    DumpHeader d(vcd_file);
-    inputs.visit(d);
-    outputs.visit(d);
-    state.visit(d);
-  }
-  vcd_file << "$enddefinitions $end\n$dumpvars\n";
-  std::mt19937 gen(seed);
+	std::mt19937 gen(seed);
 
-  inputs.visit(Reset());
+	gold::initialize(state);
 
-  for (int step = 0; step < steps; ++step) {
-    vcd_file << "#" << step << "\n";
-    gold::eval(inputs, outputs, state, next_state);
-    {
-      Dump d(vcd_file);
-      inputs.visit(d);
-      outputs.visit(d);
-      state.visit(d);
-    }
+	for (int step = 0; step < steps; ++step) {
+		inputs.visit(Randomize(gen));
 
-    state = next_state;
-    inputs.visit(Randomize(gen));
-  }
+		gold::eval(inputs, outputs, state, next_state);
+		vcd.data(step, inputs, outputs, state);
 
-  vcd_file.close();
+		state = next_state;
+	}
 
-  return 0;
+	return 0;
 }

From 95d28c22a2d6aecc7bdb400f85896b271561c95a Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Wed, 24 Jul 2024 18:50:03 +0100
Subject: [PATCH 422/499] functional backend: make Memory in the C++ simulation
 library read-only again

---
 backends/functional/cxx.cc            | 17 +++++++++++++++--
 backends/functional/cxx_runtime/sim.h |  5 ++---
 2 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index 324a8831c86..8d53c9e0391 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -156,6 +156,14 @@ template<class NodePrinter> struct CxxPrintVisitor : public FunctionalIR::Abstra
 	void memory_write(Node, Node mem, Node addr, Node data) override { print("{}.write({}, {})", mem, addr, data); }
 };
 
+bool equal_def(RTLIL::Const const &a, RTLIL::Const const &b) {
+	if(a.size() != b.size()) return false;
+	for(int i = 0; i < a.size(); i++)
+		if((a[i] == State::S1) != (b[i] == State::S1))
+			return false;
+	return true;
+}
+
 struct CxxModule {
 	FunctionalIR ir;
 	CxxStruct input_struct, output_struct, state_struct;
@@ -193,11 +201,16 @@ struct CxxModule {
 			if (sort.is_signal())
 				f.print("\tstate.{} = {};\n", state_struct[name], cxx_const(ir.get_initial_state_signal(name)));
 			else if (sort.is_memory()) {
+				f.print("\t{{\n");
+				f.print("\t\tstd::array<Signal<{}>, {}> mem;\n", sort.data_width(), 1<<sort.addr_width());
 				const auto &contents = ir.get_initial_state_memory(name);
-				f.print("\tstate.{}.fill({});\n", state_struct[name], cxx_const(contents.default_value()));
+				f.print("\t\tmem.fill({});\n", cxx_const(contents.default_value()));
 				for(auto range : contents)
 					for(auto addr = range.base(); addr < range.limit(); addr++)
-						f.print("\tstate.{}[{}] = {};\n", state_struct[name], addr, cxx_const(range[addr]));
+						if(!equal_def(range[addr], contents.default_value()))
+							f.print("\t\tmem[{}] = {};\n", addr, cxx_const(range[addr]));
+				f.print("\t\tstate.{} = mem;\n", state_struct[name]);
+				f.print("\t}}\n");
 			}
 		}
 		f.print("}}\n\n");
diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h
index 6cce4e8456c..c50bc2cd818 100644
--- a/backends/functional/cxx_runtime/sim.h
+++ b/backends/functional/cxx_runtime/sim.h
@@ -400,6 +400,8 @@ template<size_t a, size_t d>
 class Memory {
     std::array<Signal<d>, 1<<a> _contents;
 public:
+    Memory() {}
+    Memory(std::array<Signal<d>, 1<<a> const &contents) : _contents(contents) {}
     Signal<d> read(Signal<a> addr) const
     {
         return _contents[addr.template as_numeric<size_t>()];
@@ -410,9 +412,6 @@ class Memory {
         ret._contents[addr.template as_numeric<size_t>()] = data;
         return ret;
     }
-    // mutating methods for initializing a state
-    void fill(Signal<d> data) { _contents.fill(data); }
-    Signal<d> &operator[](Signal<a> addr) { return _contents[addr.template as_numeric<size_t>()]; }
 };
 
 #endif

From 7ac0e92d35e49704a9eb37d6ed5b451fa0db60fd Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 25 Jul 2024 07:59:00 +0100
Subject: [PATCH 423/499] functional backend: rename get_input and
 get_current_state to input and current_state (more consistent with other
 methods)

---
 kernel/functionalir.cc | 6 +++---
 kernel/functionalir.h  | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc
index bc21b4d3648..195e47b12ac 100644
--- a/kernel/functionalir.cc
+++ b/kernel/functionalir.cc
@@ -499,7 +499,7 @@ class FunctionalIRConstruction {
 		vector<Node> read_results;
 		factory.add_state(mem->cell->name, FunctionalIR::Sort(ceil_log2(mem->size), mem->width));
 		factory.set_initial_state(mem->cell->name, MemContents(mem));
-		Node node = factory.get_current_state(mem->cell->name);
+		Node node = factory.current_state(mem->cell->name);
 		for (size_t i = 0; i < mem->wr_ports.size(); i++) {
 			const auto &wr = mem->wr_ports[i];
 			if (wr.clk_enable)
@@ -543,7 +543,7 @@ class FunctionalIRConstruction {
 				log_error("The design contains a %s flip-flop at %s. This is not supported by the functional backend. "
 					"Call async2sync or clk2fflogic to avoid this error.\n", log_id(cell->type), log_id(cell));
 			factory.add_state(ff.name, FunctionalIR::Sort(ff.width));
-			Node q_value = factory.get_current_state(ff.name);
+			Node q_value = factory.current_state(ff.name);
 			factory.suggest_name(q_value, ff.name);
 			factory.update_pending(cell_outputs.at({cell, ID(Q)}), q_value);
 			factory.set_next_state(ff.name, enqueue(ff.sig_d));
@@ -593,7 +593,7 @@ class FunctionalIRConstruction {
 					DriveChunkWire wire_chunk = chunk.wire();
 					if (wire_chunk.is_whole()) {
 						if (wire_chunk.wire->port_input) {
-							Node node = factory.get_input(wire_chunk.wire->name);
+							Node node = factory.input(wire_chunk.wire->name);
 							factory.suggest_name(node, wire_chunk.wire->name);
 							factory.update_pending(pending, node);
 						} else {
diff --git a/kernel/functionalir.h b/kernel/functionalir.h
index e0af89d9f3a..fdbdcbde306 100644
--- a/kernel/functionalir.h
+++ b/kernel/functionalir.h
@@ -452,10 +452,10 @@ class FunctionalIR {
 			auto [it, inserted] = _ir._state_sorts.emplace(name, sort);
 			if (!inserted) log_error("state `%s` was re-defined", name.c_str());
 		}
-		Node get_input(IdString name) {
+		Node input(IdString name) {
 			return add(NodeData(Fn::input, name), Sort(_ir._input_sorts.at(name)), {});
 		}
-		Node get_current_state(IdString name) {
+		Node current_state(IdString name) {
 			return add(NodeData(Fn::state, name), Sort(_ir._state_sorts.at(name)), {});
 		}
 		void set_output(IdString output, Node value) {

From 8c0f625c3aaeb378a4b86cb2e75fc801cf4bef2c Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 25 Jul 2024 10:35:32 +0100
Subject: [PATCH 424/499] functional backend: topological sort starts with the
 output and next states nodes, other nodes get deleted

---
 backends/functional/test_generic.cc | 10 +++-----
 kernel/functional.h                 | 18 +++++++++++++-
 kernel/functionalir.cc              | 20 ++++++++++-----
 kernel/topo_scc.h                   | 38 +++++++++++++++++++----------
 passes/cmds/example_dt.cc           |  4 +--
 5 files changed, 62 insertions(+), 28 deletions(-)

diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc
index ba713b36c32..5d93492767f 100644
--- a/backends/functional/test_generic.cc
+++ b/backends/functional/test_generic.cc
@@ -129,14 +129,13 @@ struct FunctionalTestGeneric : public Pass
 
 		size_t argidx = 1;
 		extra_args(args, argidx, design);
-
+/*
 		MemContentsTest test(8, 16);
 
 		std::random_device seed_dev;
 		std::mt19937 rnd(23); //seed_dev());
 		test.run(rnd, 1000);
-
-/*
+*/
 
 		for (auto module : design->selected_modules()) {
             log("Dumping module `%s'.\n", module->name.c_str());
@@ -144,11 +143,10 @@ struct FunctionalTestGeneric : public Pass
 			for(auto node : fir)
 				std::cout << RTLIL::unescape_id(node.name()) << " = " << node.to_string([](auto n) { return RTLIL::unescape_id(n.name()); }) << "\n";
 			for(auto [name, sort] : fir.outputs())
-				std::cout << RTLIL::unescape_id(name) << " = " << RTLIL::unescape_id(fir.get_output_node(name).name()) << "\n";
+				std::cout << "output " << RTLIL::unescape_id(name) << " = " << RTLIL::unescape_id(fir.get_output_node(name).name()) << "\n";
 			for(auto [name, sort] : fir.state())
-				std::cout << RTLIL::unescape_id(name) << " = " << RTLIL::unescape_id(fir.get_state_next_node(name).name()) << "\n";
+				std::cout << "state " << RTLIL::unescape_id(name) << " = " << RTLIL::unescape_id(fir.get_state_next_node(name).name()) << "\n";
 		}
-*/
 	}
 } FunctionalCxxBackend;
 
diff --git a/kernel/functional.h b/kernel/functional.h
index 09f66c9813b..77e965f6474 100644
--- a/kernel/functional.h
+++ b/kernel/functional.h
@@ -268,6 +268,19 @@ struct ComputeGraph
         return added;
     }
 
+    void compact_args()
+    {
+        std::vector<int> new_args;
+        for (auto &node : nodes)
+        {
+            int new_offset = GetSize(new_args);
+            for (int i = 0; i < node.arg_count; i++)
+                new_args.push_back(args[node.arg_offset + i]);
+            node.arg_offset = new_offset;
+        }
+        std::swap(args, new_args);
+    }
+
     void permute(std::vector<int> const &perm)
     {
         log_assert(perm.size() <= nodes.size());
@@ -276,7 +289,7 @@ struct ComputeGraph
         for (int i = 0; i < GetSize(perm); ++i)
         {
             int j = perm[i];
-            log_assert(j >= 0 && j < GetSize(perm));
+            log_assert(j >= 0 && j < GetSize(nodes));
             log_assert(inv_perm[j] == -1);
             inv_perm[j] = i;
         }
@@ -301,15 +314,18 @@ struct ComputeGraph
         std::swap(nodes, new_nodes);
         std::swap(sparse_attrs, new_sparse_attrs);
 
+        compact_args();
         for (int &arg : args)
         {
             log_assert(arg < GetSize(inv_perm));
+            log_assert(inv_perm[arg] >= 0);
             arg = inv_perm[arg];
         }
 
         for (auto &key : keys_)
         {
             log_assert(key.second < GetSize(inv_perm));
+            log_assert(inv_perm[key.second] >= 0);
             key.second = inv_perm[key.second];
         }
     }
diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc
index 195e47b12ac..223fdaa913e 100644
--- a/kernel/functionalir.cc
+++ b/kernel/functionalir.cc
@@ -657,19 +657,27 @@ void FunctionalIR::topological_sort() {
     Graph::SccAdaptor compute_graph_scc(_graph);
     bool scc = false;
     std::vector<int> perm;
-    topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) {
+    TopoSortedSccs toposort(compute_graph_scc, [&](int *begin, int *end) {
         perm.insert(perm.end(), begin, end);
         if (end > begin + 1)
         {
-            log_warning("SCC:");
-            for (int *i = begin; i != end; ++i)
-                log(" %d", *i);
+            log_warning("Combinational loop:\n");
+            for (int *i = begin; i != end; ++i) {
+				Node node(_graph[*i]);
+                log("- %s = %s\n", RTLIL::unescape_id(node.name()).c_str(), node.to_string().c_str());
+			}
             log("\n");
             scc = true;
         }
-    }, /* sources_first */ true);
+    });
+	for(const auto &[name, sort]: _state_sorts)
+		toposort.process(get_state_next_node(name).id());
+	for(const auto &[name, sort]: _output_sorts)
+		toposort.process(get_output_node(name).id());
+	// any nodes untouched by this point are dead code and will be removed by permute
     _graph.permute(perm);
-    if(scc) log_error("combinational loops, aborting\n");
+    if(scc) log_error("The design contains combinational loops. This is not supported by the functional backend. "
+		"Try `scc -select; simplemap; select -clear` to avoid this error.\n");
 }
 
 static IdString merge_name(IdString a, IdString b) {
diff --git a/kernel/topo_scc.h b/kernel/topo_scc.h
index 89df8928aa2..7e730bb27dc 100644
--- a/kernel/topo_scc.h
+++ b/kernel/topo_scc.h
@@ -194,7 +194,7 @@ class IntGraph {
 };
 
 template<typename G, typename ComponentCallback>
-void topo_sorted_sccs(G &graph, ComponentCallback component, bool sources_first = false)
+class TopoSortedSccs
 {
     typedef typename G::node_enumerator node_enumerator;
     typedef typename G::successor_enumerator successor_enumerator;
@@ -210,14 +210,20 @@ void topo_sorted_sccs(G &graph, ComponentCallback component, bool sources_first
         {}
     };
 
+    G &graph;
+    ComponentCallback component;
+
     std::vector<dfs_entry> dfs_stack;
     std::vector<node_type> component_stack;
     int next_index = 0;
 
+public:
+    TopoSortedSccs(G &graph, ComponentCallback component)
+    : graph(graph), component(component) {}
 
-    node_enumerator nodes = graph.enumerate_nodes();
-
-    if (sources_first) {
+    // process all sources (nodes without a successor)
+    TopoSortedSccs &process_sources() {
+        node_enumerator nodes = graph.enumerate_nodes();
         while (!nodes.finished()) {
             node_type node = nodes.next();
             successor_enumerator successors = graph.enumerate_successors(node);
@@ -231,16 +237,23 @@ void topo_sorted_sccs(G &graph, ComponentCallback component, bool sources_first
                 graph.dfs_index(node) = INT_MAX;
             }
         }
-        nodes = graph.enumerate_nodes();
+        return *this;
     }
 
-    // iterate over all nodes to ensure we process the whole graph
-    while (!nodes.finished()) {
-        node_type node = nodes.next();
+    // process all remaining nodes in the graph
+    TopoSortedSccs &process_all() {   
+        node_enumerator nodes = graph.enumerate_nodes();
+        // iterate over all nodes to ensure we process the whole graph
+        while (!nodes.finished())
+            process(nodes.next());
+        return *this;
+    }
+
+    // process all nodes that are reachable from a given start node
+    TopoSortedSccs &process(node_type node) {
         // only start a new search if the node wasn't visited yet
         if (graph.dfs_index(node) >= 0)
-            continue;
-
+            return *this;
         while (true) {
             // at this point we're visiting the node for the first time during
             // the DFS search
@@ -299,7 +312,7 @@ void topo_sorted_sccs(G &graph, ComponentCallback component, bool sources_first
                     // continues the search at the parent node or returns to
                     // the outer loop if we already are at the root node.
                     if (dfs_stack.empty())
-                        goto next_search;
+                        return *this;
                     auto &dfs_top = dfs_stack.back();
 
                     node = dfs_top.node;
@@ -336,9 +349,8 @@ void topo_sorted_sccs(G &graph, ComponentCallback component, bool sources_first
                 }
             }
         }
-    next_search:;
     }
-}
+};
 
 YOSYS_NAMESPACE_END
 
diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc
index 859b0b7ba4b..4b836d75b88 100644
--- a/passes/cmds/example_dt.cc
+++ b/passes/cmds/example_dt.cc
@@ -183,7 +183,7 @@ struct ExampleDtPass : public Pass
 
 
 			std::vector<int> perm;
-			topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) {
+			TopoSortedSccs(compute_graph_scc, [&](int *begin, int *end) {
 				perm.insert(perm.end(), begin, end);
 				if (end > begin + 1)
 				{
@@ -192,7 +192,7 @@ struct ExampleDtPass : public Pass
 						log(" %d", *i);
 					log("\n");
 				}
-			}, /* sources_first */ true);
+			}).process_sources().process_all();
 			compute_graph.permute(perm);
 
 

From 850b3a6c29b8b1ffd76ed24493d85ffa721f8109 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 25 Jul 2024 12:10:59 +0100
Subject: [PATCH 425/499] convert class FunctionalIR to a namespace Functional,
 rename functionalir.h to functional.h, rename functional.h to compute_graph.h

---
 Makefile                                  |   2 +-
 backends/functional/cxx.cc                |  20 +-
 backends/functional/smtlib.cc             |  22 +-
 backends/functional/test_generic.cc       |   4 +-
 kernel/compute_graph.h                    | 403 ++++++++++
 kernel/{functionalir.cc => functional.cc} | 111 ++-
 kernel/functional.h                       | 935 +++++++++++++---------
 kernel/functionalir.h                     | 575 -------------
 kernel/mem.h                              |  11 +-
 kernel/utils.h                            |   9 +
 passes/cmds/example_dt.cc                 |   2 +-
 11 files changed, 1055 insertions(+), 1039 deletions(-)
 create mode 100644 kernel/compute_graph.h
 rename kernel/{functionalir.cc => functional.cc} (90%)
 delete mode 100644 kernel/functionalir.h

diff --git a/Makefile b/Makefile
index 68e6fda4a0c..e61948cb4f1 100644
--- a/Makefile
+++ b/Makefile
@@ -640,7 +640,7 @@ $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h))
 OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o
 OBJS += kernel/binding.o
 OBJS += kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o kernel/sexpr.o
-OBJS += kernel/drivertools.o kernel/functionalir.o
+OBJS += kernel/drivertools.o kernel/functional.o
 ifeq ($(ENABLE_ZLIB),1)
 OBJS += kernel/fstdata.o
 endif
diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index 8d53c9e0391..a4755e144c3 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -18,7 +18,7 @@
  */
 
 #include "kernel/yosys.h"
-#include "kernel/functionalir.h"
+#include "kernel/functional.h"
 #include <ctype.h>
 
 USING_YOSYS_NAMESPACE
@@ -42,7 +42,7 @@ const char *reserved_keywords[] = {
 	nullptr
 };
 
-template<typename Id> struct CxxScope : public FunctionalTools::Scope<Id> {
+template<typename Id> struct CxxScope : public Functional::Scope<Id> {
 	CxxScope() {
 		for(const char **p = reserved_keywords; *p != nullptr; p++)
 			this->reserve(*p);
@@ -53,8 +53,8 @@ template<typename Id> struct CxxScope : public FunctionalTools::Scope<Id> {
 };
 
 struct CxxType {
-	FunctionalIR::Sort sort;
-	CxxType(FunctionalIR::Sort sort) : sort(sort) {}
+	Functional::Sort sort;
+	CxxType(Functional::Sort sort) : sort(sort) {}
 	std::string to_string() const {
 		if(sort.is_memory()) {
 			return stringf("Memory<%d, %d>", sort.addr_width(), sort.data_width());
@@ -66,7 +66,7 @@ struct CxxType {
 	}
 };
 
-using CxxWriter = FunctionalTools::Writer;
+using CxxWriter = Functional::Writer;
 
 struct CxxStruct {
 	std::string name;
@@ -111,8 +111,8 @@ std::string cxx_const(RTLIL::Const const &value) {
 	return ss.str();
 }
 
-template<class NodePrinter> struct CxxPrintVisitor : public FunctionalIR::AbstractVisitor<void> {
-	using Node = FunctionalIR::Node;
+template<class NodePrinter> struct CxxPrintVisitor : public Functional::AbstractVisitor<void> {
+	using Node = Functional::Node;
 	CxxWriter &f;
 	NodePrinter np;
 	CxxStruct &input_struct;
@@ -165,12 +165,12 @@ bool equal_def(RTLIL::Const const &a, RTLIL::Const const &b) {
 }
 
 struct CxxModule {
-	FunctionalIR ir;
+	Functional::IR ir;
 	CxxStruct input_struct, output_struct, state_struct;
 	std::string module_name;
 
 	explicit CxxModule(Module *module) :
-		ir(FunctionalIR::from_module(module)),
+		ir(Functional::IR::from_module(module)),
 		input_struct("Inputs"),
 		output_struct("Outputs"),
 		state_struct("State")
@@ -222,7 +222,7 @@ struct CxxModule {
 		locals.reserve("output");
 		locals.reserve("current_state");
 		locals.reserve("next_state");
-		auto node_name = [&](FunctionalIR::Node n) { return locals(n.id(), n.name()); };
+		auto node_name = [&](Functional::Node n) { return locals(n.id(), n.name()); };
 		CxxPrintVisitor printVisitor(f, node_name, input_struct, state_struct);
 		for (auto node : ir) {
 			f.print("\t{} {} = ", CxxType(node.sort()).to_string(), node_name(node));
diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index 0d2763d3201..7fd6fe564c2 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -17,7 +17,7 @@
  *
  */
 
-#include "kernel/functionalir.h"
+#include "kernel/functional.h"
 #include "kernel/yosys.h"
 #include "kernel/sexpr.h"
 #include <ctype.h>
@@ -42,7 +42,7 @@ const char *reserved_keywords[] = {
 	nullptr
 };
 
-struct SmtScope : public FunctionalTools::Scope<int> {
+struct SmtScope : public Functional::Scope<int> {
 	SmtScope() {
 		for(const char **p = reserved_keywords; *p != nullptr; p++)
 			reserve(*p);
@@ -53,8 +53,8 @@ struct SmtScope : public FunctionalTools::Scope<int> {
 };
 
 struct SmtSort {
-	FunctionalIR::Sort sort;
-	SmtSort(FunctionalIR::Sort sort) : sort(sort) {}
+	Functional::Sort sort;
+	SmtSort(Functional::Sort sort) : sort(sort) {}
 	SExpr to_sexpr() const {
 		if(sort.is_memory()) {
 			return list("Array", list("_", "BitVec", sort.addr_width()), list("_", "BitVec", sort.data_width()));
@@ -116,8 +116,8 @@ std::string smt_const(RTLIL::Const const &c) {
 	return s;
 }
 
-struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor<SExpr> {
-	using Node = FunctionalIR::Node;
+struct SmtPrintVisitor : public Functional::AbstractVisitor<SExpr> {
+	using Node = Functional::Node;
 	std::function<SExpr(Node)> n;
 	SmtStruct &input_struct;
 	SmtStruct &state_struct;
@@ -183,7 +183,7 @@ struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor<SExpr> {
 };
 
 struct SmtModule {
-	FunctionalIR ir;
+	Functional::IR ir;
 	SmtScope scope;
 	std::string name;
 	
@@ -192,7 +192,7 @@ struct SmtModule {
 	SmtStruct state_struct;
 
 	SmtModule(Module *module)
-		: ir(FunctionalIR::from_module(module))
+		: ir(Functional::IR::from_module(module))
 		, scope()
 		, name(scope.unique_name(module->name))
 		, input_struct(scope.unique_name(module->name.str() + "_Inputs"), scope)
@@ -215,11 +215,11 @@ struct SmtModule {
 			list(list("inputs", input_struct.name),
 			     list("state", state_struct.name)),
 			list("Pair", output_struct.name, state_struct.name)));
-		auto inlined = [&](FunctionalIR::Node n) {
-			return n.fn() == FunctionalIR::Fn::constant;
+		auto inlined = [&](Functional::Node n) {
+			return n.fn() == Functional::Fn::constant;
 		};
 		SmtPrintVisitor visitor(input_struct, state_struct);
-		auto node_to_sexpr = [&](FunctionalIR::Node n) -> SExpr {
+		auto node_to_sexpr = [&](Functional::Node n) -> SExpr {
 			if(inlined(n))
 				return n.visit(visitor);
 			else
diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc
index 5d93492767f..83ea09d8ddb 100644
--- a/backends/functional/test_generic.cc
+++ b/backends/functional/test_generic.cc
@@ -18,7 +18,7 @@
  */
 
 #include "kernel/yosys.h"
-#include "kernel/functionalir.h"
+#include "kernel/functional.h"
 #include <random>
 
 USING_YOSYS_NAMESPACE
@@ -139,7 +139,7 @@ struct FunctionalTestGeneric : public Pass
 
 		for (auto module : design->selected_modules()) {
             log("Dumping module `%s'.\n", module->name.c_str());
-			auto fir = FunctionalIR::from_module(module);
+			auto fir = Functional::IR::from_module(module);
 			for(auto node : fir)
 				std::cout << RTLIL::unescape_id(node.name()) << " = " << node.to_string([](auto n) { return RTLIL::unescape_id(n.name()); }) << "\n";
 			for(auto [name, sort] : fir.outputs())
diff --git a/kernel/compute_graph.h b/kernel/compute_graph.h
new file mode 100644
index 00000000000..aeba17f8c1f
--- /dev/null
+++ b/kernel/compute_graph.h
@@ -0,0 +1,403 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Jannis Harder <jix@yosyshq.com> <me@jix.one>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef COMPUTE_GRAPH_H
+#define COMPUTE_GRAPH_H
+
+#include <tuple>
+#include "kernel/yosys.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+template<
+    typename Fn, // Function type (deduplicated across whole graph)
+    typename Attr = std::tuple<>, // Call attributes (present in every node)
+    typename SparseAttr = std::tuple<>, // Sparse call attributes (optional per node)
+    typename Key = std::tuple<> // Stable keys to refer to nodes
+>
+struct ComputeGraph
+{
+    struct Ref;
+private:
+
+    // Functions are deduplicated by assigning unique ids
+    idict<Fn> functions;
+
+    struct Node {
+        int fn_index;
+        int arg_offset;
+        int arg_count;
+        Attr attr;
+
+        Node(int fn_index, Attr &&attr, int arg_offset, int arg_count = 0)
+            : fn_index(fn_index), arg_offset(arg_offset), arg_count(arg_count), attr(std::move(attr)) {}
+
+        Node(int fn_index, Attr const &attr, int arg_offset, int arg_count = 0)
+            : fn_index(fn_index), arg_offset(arg_offset), arg_count(arg_count), attr(attr) {}
+    };
+
+
+    std::vector<Node> nodes;
+    std::vector<int> args;
+    dict<Key, int> keys_;
+    dict<int, SparseAttr> sparse_attrs;
+
+public:
+    template<typename Graph>
+    struct BaseRef
+    {
+    protected:
+        friend struct ComputeGraph;
+        Graph *graph_;
+        int index_;
+        BaseRef(Graph *graph, int index) : graph_(graph), index_(index) {
+            log_assert(index_ >= 0);
+            check();
+        }
+
+        void check() const { log_assert(index_ < graph_->size()); }
+
+        Node const &deref() const { check(); return graph_->nodes[index_]; }
+
+    public:
+        ComputeGraph const &graph() const { return graph_; }
+        int index() const { return index_; }
+
+        int size() const { return deref().arg_count; }
+
+        BaseRef arg(int n) const
+        {
+            Node const &node = deref();
+            log_assert(n >= 0 && n < node.arg_count);
+            return BaseRef(graph_, graph_->args[node.arg_offset + n]);
+        }
+
+        std::vector<int>::const_iterator arg_indices_cbegin() const
+        {
+            Node const &node = deref();
+            return graph_->args.cbegin() + node.arg_offset;
+        }
+
+        std::vector<int>::const_iterator arg_indices_cend() const
+        {
+            Node const &node = deref();
+            return graph_->args.cbegin() + node.arg_offset + node.arg_count;
+        }
+
+        Fn const &function() const { return graph_->functions[deref().fn_index]; }
+        Attr const &attr() const { return deref().attr; }
+
+        bool has_sparse_attr() const { return graph_->sparse_attrs.count(index_); }
+
+        SparseAttr const &sparse_attr() const
+        {
+            auto found = graph_->sparse_attrs.find(index_);
+            log_assert(found != graph_->sparse_attrs.end());
+            return found->second;
+        }
+    };
+
+    using ConstRef = BaseRef<ComputeGraph const>;
+
+    struct Ref : public BaseRef<ComputeGraph>
+    {
+    private:
+        friend struct ComputeGraph;
+        Ref(ComputeGraph *graph, int index) : BaseRef<ComputeGraph>(graph, index) {}
+        Node &deref() const { this->check(); return this->graph_->nodes[this->index_]; }
+
+    public:
+        Ref(BaseRef<ComputeGraph> ref) : Ref(ref.graph_, ref.index_) {}
+
+        void set_function(Fn const &function) const
+        {
+            deref().fn_index = this->graph_->functions(function);
+        }
+
+        Attr &attr() const { return deref().attr; }
+
+        void append_arg(ConstRef arg) const
+        {
+            log_assert(arg.graph_ == this->graph_);
+            append_arg(arg.index());
+        }
+
+        void append_arg(int arg) const
+        {
+            log_assert(arg >= 0 && arg < this->graph_->size());
+            Node &node = deref();
+            if (node.arg_offset + node.arg_count != GetSize(this->graph_->args))
+                move_args(node);
+            this->graph_->args.push_back(arg);
+            node.arg_count++;
+        }
+
+        operator ConstRef() const
+        {
+            return ConstRef(this->graph_, this->index_);
+        }
+
+        SparseAttr &sparse_attr() const
+        {
+            return this->graph_->sparse_attrs[this->index_];
+        }
+
+        void clear_sparse_attr() const
+        {
+            this->graph_->sparse_attrs.erase(this->index_);
+        }
+
+        void assign_key(Key const &key) const
+        {
+            this->graph_->keys_.emplace(key, this->index_);
+        }
+
+    private:
+        void move_args(Node &node) const
+        {
+            auto &args = this->graph_->args;
+            int old_offset = node.arg_offset;
+            node.arg_offset = GetSize(args);
+            for (int i = 0; i != node.arg_count; ++i)
+                args.push_back(args[old_offset + i]);
+        }
+
+    };
+
+    bool has_key(Key const &key) const
+    {
+        return keys_.count(key);
+    }
+
+    dict<Key, int> const &keys() const
+    {
+        return keys_;
+    }
+
+    ConstRef operator()(Key const &key) const
+    {
+        auto it = keys_.find(key);
+        log_assert(it != keys_.end());
+        return (*this)[it->second];
+    }
+
+    Ref operator()(Key const &key)
+    {
+        auto it = keys_.find(key);
+        log_assert(it != keys_.end());
+        return (*this)[it->second];
+    }
+
+    int size() const { return GetSize(nodes); }
+
+    ConstRef operator[](int index) const { return ConstRef(this, index); }
+    Ref operator[](int index) { return Ref(this, index); }
+
+    Ref add(Fn const &function, Attr &&attr)
+    {
+        int index = GetSize(nodes);
+        int fn_index = functions(function);
+        nodes.emplace_back(fn_index, std::move(attr), GetSize(args));
+        return Ref(this, index);
+    }
+
+    Ref add(Fn const &function, Attr const &attr)
+    {
+        int index = GetSize(nodes);
+        int fn_index = functions(function);
+        nodes.emplace_back(fn_index, attr,  GetSize(args));
+        return Ref(this, index);
+    }
+
+    template<typename T>
+    Ref add(Fn const &function, Attr const &attr, T &&args)
+    {
+        Ref added = add(function, attr);
+        for (auto arg : args)
+            added.append_arg(arg);
+        return added;
+    }
+
+    template<typename T>
+    Ref add(Fn const &function, Attr &&attr, T &&args)
+    {
+        Ref added = add(function, std::move(attr));
+        for (auto arg : args)
+            added.append_arg(arg);
+        return added;
+    }
+
+    Ref add(Fn const &function, Attr const &attr, std::initializer_list<Ref> args)
+    {
+        Ref added = add(function, attr);
+        for (auto arg : args)
+            added.append_arg(arg);
+        return added;
+    }
+
+    Ref add(Fn const &function, Attr &&attr, std::initializer_list<Ref> args)
+    {
+        Ref added = add(function, std::move(attr));
+        for (auto arg : args)
+            added.append_arg(arg);
+        return added;
+    }
+
+    template<typename T>
+    Ref add(Fn const &function, Attr const &attr, T begin, T end)
+    {
+        Ref added = add(function, attr);
+        for (; begin != end; ++begin)
+            added.append_arg(*begin);
+        return added;
+    }
+
+    void compact_args()
+    {
+        std::vector<int> new_args;
+        for (auto &node : nodes)
+        {
+            int new_offset = GetSize(new_args);
+            for (int i = 0; i < node.arg_count; i++)
+                new_args.push_back(args[node.arg_offset + i]);
+            node.arg_offset = new_offset;
+        }
+        std::swap(args, new_args);
+    }
+
+    void permute(std::vector<int> const &perm)
+    {
+        log_assert(perm.size() <= nodes.size());
+        std::vector<int> inv_perm;
+        inv_perm.resize(nodes.size(), -1);
+        for (int i = 0; i < GetSize(perm); ++i)
+        {
+            int j = perm[i];
+            log_assert(j >= 0 && j < GetSize(nodes));
+            log_assert(inv_perm[j] == -1);
+            inv_perm[j] = i;
+        }
+        permute(perm, inv_perm);
+    }
+
+    void permute(std::vector<int> const &perm, std::vector<int> const &inv_perm)
+    {
+        log_assert(inv_perm.size() == nodes.size());
+        std::vector<Node> new_nodes;
+        new_nodes.reserve(perm.size());
+        dict<int, SparseAttr> new_sparse_attrs;
+        for (int i : perm)
+        {
+            int j = GetSize(new_nodes);
+            new_nodes.emplace_back(std::move(nodes[i]));
+            auto found = sparse_attrs.find(i);
+            if (found != sparse_attrs.end())
+                new_sparse_attrs.emplace(j, std::move(found->second));
+        }
+
+        std::swap(nodes, new_nodes);
+        std::swap(sparse_attrs, new_sparse_attrs);
+
+        compact_args();
+        for (int &arg : args)
+        {
+            log_assert(arg < GetSize(inv_perm));
+            log_assert(inv_perm[arg] >= 0);
+            arg = inv_perm[arg];
+        }
+
+        for (auto &key : keys_)
+        {
+            log_assert(key.second < GetSize(inv_perm));
+            log_assert(inv_perm[key.second] >= 0);
+            key.second = inv_perm[key.second];
+        }
+    }
+
+    struct SccAdaptor
+    {
+    private:
+        ComputeGraph const &graph_;
+        std::vector<int> indices_;
+    public:
+        SccAdaptor(ComputeGraph const &graph) : graph_(graph)
+        {
+            indices_.resize(graph.size(), -1);
+        }
+
+
+        typedef int node_type;
+
+        struct node_enumerator {
+        private:
+            friend struct SccAdaptor;
+            int current, end;
+            node_enumerator(int current, int end) : current(current), end(end) {}
+
+        public:
+
+            bool finished() const { return current == end; }
+            node_type next() {
+                log_assert(!finished());
+                node_type result = current;
+                ++current;
+                return result;
+            }
+        };
+
+        node_enumerator enumerate_nodes() {
+            return node_enumerator(0, GetSize(indices_));
+        }
+
+
+        struct successor_enumerator {
+        private:
+            friend struct SccAdaptor;
+            std::vector<int>::const_iterator current, end;
+            successor_enumerator(std::vector<int>::const_iterator current, std::vector<int>::const_iterator end) :
+                current(current), end(end) {}
+
+        public:
+            bool finished() const { return current == end; }
+            node_type next() {
+                log_assert(!finished());
+                node_type result = *current;
+                ++current;
+                return result;
+            }
+        };
+
+        successor_enumerator enumerate_successors(int index) const {
+            auto const &ref = graph_[index];
+            return successor_enumerator(ref.arg_indices_cbegin(), ref.arg_indices_cend());
+        }
+
+        int &dfs_index(node_type const &node) { return indices_[node]; }
+
+        std::vector<int> const &dfs_indices() { return indices_; }
+    };
+
+};
+
+
+
+YOSYS_NAMESPACE_END
+
+
+#endif
diff --git a/kernel/functionalir.cc b/kernel/functional.cc
similarity index 90%
rename from kernel/functionalir.cc
rename to kernel/functional.cc
index 223fdaa913e..ad507187db2 100644
--- a/kernel/functionalir.cc
+++ b/kernel/functional.cc
@@ -17,55 +17,55 @@
  *
  */
 
-#include "kernel/functionalir.h"
-#include <optional>
+#include "kernel/functional.h"
+#include "kernel/topo_scc.h"
 #include "ff.h"
 #include "ffinit.h"
 
 YOSYS_NAMESPACE_BEGIN
+namespace Functional {
 
-const char *FunctionalIR::fn_to_string(FunctionalIR::Fn fn) {
+const char *fn_to_string(Fn fn) {
 	switch(fn) {
-	case FunctionalIR::Fn::invalid: return "invalid";
-	case FunctionalIR::Fn::buf: return "buf";
-	case FunctionalIR::Fn::slice: return "slice";
-	case FunctionalIR::Fn::zero_extend: return "zero_extend";
-	case FunctionalIR::Fn::sign_extend: return "sign_extend";
-	case FunctionalIR::Fn::concat: return "concat";
-	case FunctionalIR::Fn::add: return "add";
-	case FunctionalIR::Fn::sub: return "sub";
-	case FunctionalIR::Fn::mul: return "mul";
-	case FunctionalIR::Fn::unsigned_div: return "unsigned_div";
-	case FunctionalIR::Fn::unsigned_mod: return "unsigned_mod";
-	case FunctionalIR::Fn::bitwise_and: return "bitwise_and";
-	case FunctionalIR::Fn::bitwise_or: return "bitwise_or";
-	case FunctionalIR::Fn::bitwise_xor: return "bitwise_xor";
-	case FunctionalIR::Fn::bitwise_not: return "bitwise_not";
-	case FunctionalIR::Fn::reduce_and: return "reduce_and";
-	case FunctionalIR::Fn::reduce_or: return "reduce_or";
-	case FunctionalIR::Fn::reduce_xor: return "reduce_xor";
-	case FunctionalIR::Fn::unary_minus: return "unary_minus";
-	case FunctionalIR::Fn::equal: return "equal";
-	case FunctionalIR::Fn::not_equal: return "not_equal";
-	case FunctionalIR::Fn::signed_greater_than: return "signed_greater_than";
-	case FunctionalIR::Fn::signed_greater_equal: return "signed_greater_equal";
-	case FunctionalIR::Fn::unsigned_greater_than: return "unsigned_greater_than";
-	case FunctionalIR::Fn::unsigned_greater_equal: return "unsigned_greater_equal";
-	case FunctionalIR::Fn::logical_shift_left: return "logical_shift_left";
-	case FunctionalIR::Fn::logical_shift_right: return "logical_shift_right";
-	case FunctionalIR::Fn::arithmetic_shift_right: return "arithmetic_shift_right";
-	case FunctionalIR::Fn::mux: return "mux";
-	case FunctionalIR::Fn::constant: return "constant";
-	case FunctionalIR::Fn::input: return "input";
-	case FunctionalIR::Fn::state: return "state";
-	case FunctionalIR::Fn::memory_read: return "memory_read";
-	case FunctionalIR::Fn::memory_write: return "memory_write";
+	case Fn::invalid: return "invalid";
+	case Fn::buf: return "buf";
+	case Fn::slice: return "slice";
+	case Fn::zero_extend: return "zero_extend";
+	case Fn::sign_extend: return "sign_extend";
+	case Fn::concat: return "concat";
+	case Fn::add: return "add";
+	case Fn::sub: return "sub";
+	case Fn::mul: return "mul";
+	case Fn::unsigned_div: return "unsigned_div";
+	case Fn::unsigned_mod: return "unsigned_mod";
+	case Fn::bitwise_and: return "bitwise_and";
+	case Fn::bitwise_or: return "bitwise_or";
+	case Fn::bitwise_xor: return "bitwise_xor";
+	case Fn::bitwise_not: return "bitwise_not";
+	case Fn::reduce_and: return "reduce_and";
+	case Fn::reduce_or: return "reduce_or";
+	case Fn::reduce_xor: return "reduce_xor";
+	case Fn::unary_minus: return "unary_minus";
+	case Fn::equal: return "equal";
+	case Fn::not_equal: return "not_equal";
+	case Fn::signed_greater_than: return "signed_greater_than";
+	case Fn::signed_greater_equal: return "signed_greater_equal";
+	case Fn::unsigned_greater_than: return "unsigned_greater_than";
+	case Fn::unsigned_greater_equal: return "unsigned_greater_equal";
+	case Fn::logical_shift_left: return "logical_shift_left";
+	case Fn::logical_shift_right: return "logical_shift_right";
+	case Fn::arithmetic_shift_right: return "arithmetic_shift_right";
+	case Fn::mux: return "mux";
+	case Fn::constant: return "constant";
+	case Fn::input: return "input";
+	case Fn::state: return "state";
+	case Fn::memory_read: return "memory_read";
+	case Fn::memory_write: return "memory_write";
 	}
-	log_error("fn_to_string: unknown FunctionalIR::Fn value %d", (int)fn);
+	log_error("fn_to_string: unknown Functional::Fn value %d", (int)fn);
 }
 
-struct PrintVisitor : FunctionalIR::DefaultVisitor<std::string> {
-	using Node = FunctionalIR::Node;
+struct PrintVisitor : DefaultVisitor<std::string> {
 	std::function<std::string(Node)> np;
 	PrintVisitor(std::function<std::string(Node)> np) : np(np) { }
 	// as a general rule the default handler is good enough iff the only arguments are of type Node
@@ -76,7 +76,7 @@ struct PrintVisitor : FunctionalIR::DefaultVisitor<std::string> {
 	std::string input(Node, IdString name) override { return "input(" + name.str() + ")"; }
 	std::string state(Node, IdString name) override { return "state(" + name.str() + ")"; }
 	std::string default_handler(Node self) override {
-		std::string ret = FunctionalIR::fn_to_string(self.fn());
+		std::string ret = fn_to_string(self.fn());
 		ret += "(";
 		for(size_t i = 0; i < self.arg_count(); i++) {
 			if(i > 0) ret += ", ";
@@ -87,19 +87,18 @@ struct PrintVisitor : FunctionalIR::DefaultVisitor<std::string> {
 	}
 };
 
-std::string FunctionalIR::Node::to_string()
+std::string Node::to_string()
 {
 	return to_string([](Node n) { return RTLIL::unescape_id(n.name()); });
 }
 
-std::string FunctionalIR::Node::to_string(std::function<std::string(Node)> np)
+std::string Node::to_string(std::function<std::string(Node)> np)
 {
 	return visit(PrintVisitor(np));
 }
 
 class CellSimplifier {
-	using Node = FunctionalIR::Node;
-	FunctionalIR::Factory &factory;
+	Factory &factory;
 	Node sign(Node a) {
 		return factory.slice(a, a.width() - 1, 1);
 	}
@@ -138,7 +137,7 @@ class CellSimplifier {
 		Node bb = factory.bitwise_and(b, s);
 		return factory.bitwise_or(aa, bb);
 	}
-	CellSimplifier(FunctionalIR::Factory &f) : factory(f) {}
+	CellSimplifier(Factory &f) : factory(f) {}
 private:
 	Node handle_pow(Node a0, Node b, int y_width, bool is_signed) {
 		Node a = factory.extend(a0, y_width, is_signed);
@@ -400,12 +399,11 @@ class CellSimplifier {
 };
 
 class FunctionalIRConstruction {
-	using Node = FunctionalIR::Node;
 	std::deque<std::variant<DriveSpec, Cell *>> queue;
 	dict<DriveSpec, Node> graph_nodes;
 	dict<std::pair<Cell *, IdString>, Node> cell_outputs;
 	DriverMap driver_map;
-	FunctionalIR::Factory& factory;
+	Factory& factory;
 	CellSimplifier simplifier;
 	vector<Mem> memories_vector;
 	dict<Cell*, Mem*> memories;
@@ -442,7 +440,7 @@ class FunctionalIRConstruction {
 			return it->second;
 	}
 public:
-	FunctionalIRConstruction(Module *module, FunctionalIR::Factory &f)
+	FunctionalIRConstruction(Module *module, Factory &f)
 		: factory(f)
 		, simplifier(f)
 		, sig_map(module)
@@ -497,7 +495,7 @@ class FunctionalIRConstruction {
 		// - Since wr port j can only have priority over wr port i if j > i, if we do writes in
 		//   ascending index order the result will obey the priorty relation.
 		vector<Node> read_results;
-		factory.add_state(mem->cell->name, FunctionalIR::Sort(ceil_log2(mem->size), mem->width));
+		factory.add_state(mem->cell->name, Sort(ceil_log2(mem->size), mem->width));
 		factory.set_initial_state(mem->cell->name, MemContents(mem));
 		Node node = factory.current_state(mem->cell->name);
 		for (size_t i = 0; i < mem->wr_ports.size(); i++) {
@@ -542,7 +540,7 @@ class FunctionalIRConstruction {
 			if (!ff.has_gclk)
 				log_error("The design contains a %s flip-flop at %s. This is not supported by the functional backend. "
 					"Call async2sync or clk2fflogic to avoid this error.\n", log_id(cell->type), log_id(cell));
-			factory.add_state(ff.name, FunctionalIR::Sort(ff.width));
+			factory.add_state(ff.name, Sort(ff.width));
 			Node q_value = factory.current_state(ff.name);
 			factory.suggest_name(q_value, ff.name);
 			factory.update_pending(cell_outputs.at({cell, ID(Q)}), q_value);
@@ -643,8 +641,8 @@ class FunctionalIRConstruction {
 	}
 };
 
-FunctionalIR FunctionalIR::from_module(Module *module) {
-    FunctionalIR ir;
+IR IR::from_module(Module *module) {
+	IR ir;
     auto factory = ir.factory();
     FunctionalIRConstruction ctor(module, factory);
     ctor.process_queue();
@@ -653,7 +651,7 @@ FunctionalIR FunctionalIR::from_module(Module *module) {
     return ir;
 }
 
-void FunctionalIR::topological_sort() {
+void IR::topological_sort() {
     Graph::SccAdaptor compute_graph_scc(_graph);
     bool scc = false;
     std::vector<int> perm;
@@ -687,7 +685,7 @@ static IdString merge_name(IdString a, IdString b) {
 		return a;
 }
 
-void FunctionalIR::forward_buf() {
+void IR::forward_buf() {
     std::vector<int> perm, alias;
     perm.clear();
 
@@ -734,7 +732,7 @@ static std::string quote_fmt(const char *fmt)
 	return r;
 }
 
-void FunctionalTools::Writer::print_impl(const char *fmt, vector<std::function<void()>> &fns)
+void Writer::print_impl(const char *fmt, vector<std::function<void()>> &fns)
 {
 	size_t next_index = 0;
 	for(const char *p = fmt; *p != 0; p++)
@@ -770,4 +768,5 @@ void FunctionalTools::Writer::print_impl(const char *fmt, vector<std::function<v
 		}
 }
 
+}
 YOSYS_NAMESPACE_END
diff --git a/kernel/functional.h b/kernel/functional.h
index 77e965f6474..e0592259c7f 100644
--- a/kernel/functional.h
+++ b/kernel/functional.h
@@ -1,7 +1,7 @@
 /*
  *  yosys -- Yosys Open SYnthesis Suite
  *
- *  Copyright (C) 2024  Jannis Harder <jix@yosyshq.com> <me@jix.one>
+ *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -20,384 +20,571 @@
 #ifndef FUNCTIONAL_H
 #define FUNCTIONAL_H
 
-#include <tuple>
 #include "kernel/yosys.h"
+#include "kernel/compute_graph.h"
+#include "kernel/drivertools.h"
+#include "kernel/mem.h"
+#include "kernel/utils.h"
 
+USING_YOSYS_NAMESPACE
 YOSYS_NAMESPACE_BEGIN
 
-template<
-    typename Fn, // Function type (deduplicated across whole graph)
-    typename Attr = std::tuple<>, // Call attributes (present in every node)
-    typename SparseAttr = std::tuple<>, // Sparse call attributes (optional per node)
-    typename Key = std::tuple<> // Stable keys to refer to nodes
->
-struct ComputeGraph
-{
-    struct Ref;
-private:
-
-    // Functions are deduplicated by assigning unique ids
-    idict<Fn> functions;
-
-    struct Node {
-        int fn_index;
-        int arg_offset;
-        int arg_count;
-        Attr attr;
-
-        Node(int fn_index, Attr &&attr, int arg_offset, int arg_count = 0)
-            : fn_index(fn_index), arg_offset(arg_offset), arg_count(arg_count), attr(std::move(attr)) {}
-
-        Node(int fn_index, Attr const &attr, int arg_offset, int arg_count = 0)
-            : fn_index(fn_index), arg_offset(arg_offset), arg_count(arg_count), attr(attr) {}
-    };
-
-
-    std::vector<Node> nodes;
-    std::vector<int> args;
-    dict<Key, int> keys_;
-    dict<int, SparseAttr> sparse_attrs;
-
-public:
-    template<typename Graph>
-    struct BaseRef
-    {
-    protected:
-        friend struct ComputeGraph;
-        Graph *graph_;
-        int index_;
-        BaseRef(Graph *graph, int index) : graph_(graph), index_(index) {
-            log_assert(index_ >= 0);
-            check();
-        }
-
-        void check() const { log_assert(index_ < graph_->size()); }
-
-        Node const &deref() const { check(); return graph_->nodes[index_]; }
-
-    public:
-        ComputeGraph const &graph() const { return graph_; }
-        int index() const { return index_; }
-
-        int size() const { return deref().arg_count; }
-
-        BaseRef arg(int n) const
-        {
-            Node const &node = deref();
-            log_assert(n >= 0 && n < node.arg_count);
-            return BaseRef(graph_, graph_->args[node.arg_offset + n]);
-        }
-
-        std::vector<int>::const_iterator arg_indices_cbegin() const
-        {
-            Node const &node = deref();
-            return graph_->args.cbegin() + node.arg_offset;
-        }
-
-        std::vector<int>::const_iterator arg_indices_cend() const
-        {
-            Node const &node = deref();
-            return graph_->args.cbegin() + node.arg_offset + node.arg_count;
-        }
-
-        Fn const &function() const { return graph_->functions[deref().fn_index]; }
-        Attr const &attr() const { return deref().attr; }
-
-        bool has_sparse_attr() const { return graph_->sparse_attrs.count(index_); }
-
-        SparseAttr const &sparse_attr() const
-        {
-            auto found = graph_->sparse_attrs.find(index_);
-            log_assert(found != graph_->sparse_attrs.end());
-            return found->second;
-        }
-    };
-
-    using ConstRef = BaseRef<ComputeGraph const>;
-
-    struct Ref : public BaseRef<ComputeGraph>
-    {
-    private:
-        friend struct ComputeGraph;
-        Ref(ComputeGraph *graph, int index) : BaseRef<ComputeGraph>(graph, index) {}
-        Node &deref() const { this->check(); return this->graph_->nodes[this->index_]; }
-
-    public:
-        Ref(BaseRef<ComputeGraph> ref) : Ref(ref.graph_, ref.index_) {}
-
-        void set_function(Fn const &function) const
-        {
-            deref().fn_index = this->graph_->functions(function);
-        }
-
-        Attr &attr() const { return deref().attr; }
-
-        void append_arg(ConstRef arg) const
-        {
-            log_assert(arg.graph_ == this->graph_);
-            append_arg(arg.index());
-        }
-
-        void append_arg(int arg) const
-        {
-            log_assert(arg >= 0 && arg < this->graph_->size());
-            Node &node = deref();
-            if (node.arg_offset + node.arg_count != GetSize(this->graph_->args))
-                move_args(node);
-            this->graph_->args.push_back(arg);
-            node.arg_count++;
-        }
-
-        operator ConstRef() const
-        {
-            return ConstRef(this->graph_, this->index_);
-        }
-
-        SparseAttr &sparse_attr() const
-        {
-            return this->graph_->sparse_attrs[this->index_];
-        }
-
-        void clear_sparse_attr() const
-        {
-            this->graph_->sparse_attrs.erase(this->index_);
-        }
-
-        void assign_key(Key const &key) const
-        {
-            this->graph_->keys_.emplace(key, this->index_);
-        }
-
-    private:
-        void move_args(Node &node) const
-        {
-            auto &args = this->graph_->args;
-            int old_offset = node.arg_offset;
-            node.arg_offset = GetSize(args);
-            for (int i = 0; i != node.arg_count; ++i)
-                args.push_back(args[old_offset + i]);
-        }
-
-    };
-
-    bool has_key(Key const &key) const
-    {
-        return keys_.count(key);
-    }
-
-    dict<Key, int> const &keys() const
-    {
-        return keys_;
-    }
-
-    ConstRef operator()(Key const &key) const
-    {
-        auto it = keys_.find(key);
-        log_assert(it != keys_.end());
-        return (*this)[it->second];
-    }
-
-    Ref operator()(Key const &key)
-    {
-        auto it = keys_.find(key);
-        log_assert(it != keys_.end());
-        return (*this)[it->second];
-    }
-
-    int size() const { return GetSize(nodes); }
-
-    ConstRef operator[](int index) const { return ConstRef(this, index); }
-    Ref operator[](int index) { return Ref(this, index); }
-
-    Ref add(Fn const &function, Attr &&attr)
-    {
-        int index = GetSize(nodes);
-        int fn_index = functions(function);
-        nodes.emplace_back(fn_index, std::move(attr), GetSize(args));
-        return Ref(this, index);
-    }
-
-    Ref add(Fn const &function, Attr const &attr)
-    {
-        int index = GetSize(nodes);
-        int fn_index = functions(function);
-        nodes.emplace_back(fn_index, attr,  GetSize(args));
-        return Ref(this, index);
-    }
-
-    template<typename T>
-    Ref add(Fn const &function, Attr const &attr, T &&args)
-    {
-        Ref added = add(function, attr);
-        for (auto arg : args)
-            added.append_arg(arg);
-        return added;
-    }
-
-    template<typename T>
-    Ref add(Fn const &function, Attr &&attr, T &&args)
-    {
-        Ref added = add(function, std::move(attr));
-        for (auto arg : args)
-            added.append_arg(arg);
-        return added;
-    }
-
-    Ref add(Fn const &function, Attr const &attr, std::initializer_list<Ref> args)
-    {
-        Ref added = add(function, attr);
-        for (auto arg : args)
-            added.append_arg(arg);
-        return added;
-    }
-
-    Ref add(Fn const &function, Attr &&attr, std::initializer_list<Ref> args)
-    {
-        Ref added = add(function, std::move(attr));
-        for (auto arg : args)
-            added.append_arg(arg);
-        return added;
-    }
-
-    template<typename T>
-    Ref add(Fn const &function, Attr const &attr, T begin, T end)
-    {
-        Ref added = add(function, attr);
-        for (; begin != end; ++begin)
-            added.append_arg(*begin);
-        return added;
-    }
-
-    void compact_args()
-    {
-        std::vector<int> new_args;
-        for (auto &node : nodes)
-        {
-            int new_offset = GetSize(new_args);
-            for (int i = 0; i < node.arg_count; i++)
-                new_args.push_back(args[node.arg_offset + i]);
-            node.arg_offset = new_offset;
-        }
-        std::swap(args, new_args);
-    }
-
-    void permute(std::vector<int> const &perm)
-    {
-        log_assert(perm.size() <= nodes.size());
-        std::vector<int> inv_perm;
-        inv_perm.resize(nodes.size(), -1);
-        for (int i = 0; i < GetSize(perm); ++i)
-        {
-            int j = perm[i];
-            log_assert(j >= 0 && j < GetSize(nodes));
-            log_assert(inv_perm[j] == -1);
-            inv_perm[j] = i;
-        }
-        permute(perm, inv_perm);
-    }
-
-    void permute(std::vector<int> const &perm, std::vector<int> const &inv_perm)
-    {
-        log_assert(inv_perm.size() == nodes.size());
-        std::vector<Node> new_nodes;
-        new_nodes.reserve(perm.size());
-        dict<int, SparseAttr> new_sparse_attrs;
-        for (int i : perm)
-        {
-            int j = GetSize(new_nodes);
-            new_nodes.emplace_back(std::move(nodes[i]));
-            auto found = sparse_attrs.find(i);
-            if (found != sparse_attrs.end())
-                new_sparse_attrs.emplace(j, std::move(found->second));
-        }
-
-        std::swap(nodes, new_nodes);
-        std::swap(sparse_attrs, new_sparse_attrs);
-
-        compact_args();
-        for (int &arg : args)
-        {
-            log_assert(arg < GetSize(inv_perm));
-            log_assert(inv_perm[arg] >= 0);
-            arg = inv_perm[arg];
-        }
-
-        for (auto &key : keys_)
-        {
-            log_assert(key.second < GetSize(inv_perm));
-            log_assert(inv_perm[key.second] >= 0);
-            key.second = inv_perm[key.second];
-        }
-    }
-
-    struct SccAdaptor
-    {
-    private:
-        ComputeGraph const &graph_;
-        std::vector<int> indices_;
-    public:
-        SccAdaptor(ComputeGraph const &graph) : graph_(graph)
-        {
-            indices_.resize(graph.size(), -1);
-        }
-
-
-        typedef int node_type;
-
-        struct node_enumerator {
-        private:
-            friend struct SccAdaptor;
-            int current, end;
-            node_enumerator(int current, int end) : current(current), end(end) {}
-
-        public:
-
-            bool finished() const { return current == end; }
-            node_type next() {
-                log_assert(!finished());
-                node_type result = current;
-                ++current;
-                return result;
-            }
-        };
-
-        node_enumerator enumerate_nodes() {
-            return node_enumerator(0, GetSize(indices_));
-        }
-
-
-        struct successor_enumerator {
-        private:
-            friend struct SccAdaptor;
-            std::vector<int>::const_iterator current, end;
-            successor_enumerator(std::vector<int>::const_iterator current, std::vector<int>::const_iterator end) :
-                current(current), end(end) {}
-
-        public:
-            bool finished() const { return current == end; }
-            node_type next() {
-                log_assert(!finished());
-                node_type result = *current;
-                ++current;
-                return result;
-            }
-        };
-
-        successor_enumerator enumerate_successors(int index) const {
-            auto const &ref = graph_[index];
-            return successor_enumerator(ref.arg_indices_cbegin(), ref.arg_indices_cend());
-        }
-
-        int &dfs_index(node_type const &node) { return indices_[node]; }
-
-        std::vector<int> const &dfs_indices() { return indices_; }
-    };
-
-};
-
-
+namespace Functional {
+	// each function is documented with a short pseudocode declaration or definition
+	// standard C/Verilog operators are used to describe the result
+	// 
+	// the types used in this are:
+	// - bit[N]: a bitvector of N bits
+	//   bit[N] can be indicated as signed or unsigned. this is not tracked by the functional backend
+	//   but is meant to indicate how the value is interpreted
+	//   if a bit[N] is marked as neither signed nor unsigned, this means the result should be valid with *either* interpretation
+	// - memory[N, M]: a memory with N address and M data bits
+	// - int: C++ int
+	// - Const[N]: yosys RTLIL::Const (with size() == N)
+	// - IdString: yosys IdString
+	// - any: used in documentation to indicate that the type is unconstrained
+	//
+	// nodes in the functional backend are either of type bit[N] or memory[N,M] (for some N, M: int)
+	// additionally, they can carry a constant of type int, Const[N] or IdString
+	// each node has a 'sort' field that stores the type of the node
+	// slice, zero_extend, sign_extend use the type field to store out_width
+	enum class Fn {
+		// invalid() = known-invalid/shouldn't happen value
+		// TODO: maybe remove this and use e.g. std::optional instead?
+		invalid,
+		// buf(a: any): any = a
+		// no-op operation
+		// when constructing the compute graph we generate invalid buf() nodes as a placeholder
+		// and later insert the argument
+		buf,
+		// slice(a: bit[in_width], offset: int, out_width: int): bit[out_width] = a[offset +: out_width]
+		// required: offset + out_width <= in_width
+		slice,
+		// zero_extend(a: unsigned bit[in_width], out_width: int): unsigned bit[out_width] = a (zero extended)
+		// required: out_width > in_width
+		zero_extend,
+		// sign_extend(a: signed bit[in_width], out_width: int): signed bit[out_width] = a (sign extended)
+		// required: out_width > in_width
+		sign_extend,
+		// concat(a: bit[N], b: bit[M]): bit[N+M] = {b, a} (verilog syntax)
+		// concatenates two bitvectors, with a in the least significant position and b in the more significant position
+		concat,
+		// add(a: bit[N], b: bit[N]): bit[N] = a + b
+		add,
+		// sub(a: bit[N], b: bit[N]): bit[N] = a - b
+		sub,
+		// mul(a: bit[N], b: bit[N]): bit[N] = a * b
+		mul,
+		// unsigned_div(a: unsigned bit[N], b: unsigned bit[N]): bit[N] = a / b
+		unsigned_div,
+		// unsigned_mod(a: signed bit[N], b: signed bit[N]): bit[N] = a % b
+		unsigned_mod,
+		// bitwise_and(a: bit[N], b: bit[N]): bit[N] = a & b
+		bitwise_and,
+		// bitwise_or(a: bit[N], b: bit[N]): bit[N] = a | b
+		bitwise_or,
+		// bitwise_xor(a: bit[N], b: bit[N]): bit[N] = a ^ b
+		bitwise_xor,
+		// bitwise_not(a: bit[N]): bit[N] = ~a
+		bitwise_not,
+		// reduce_and(a: bit[N]): bit[1] = &a
+		reduce_and,
+		// reduce_or(a: bit[N]): bit[1] = |a
+		reduce_or,
+		// reduce_xor(a: bit[N]): bit[1] = ^a
+		reduce_xor,
+		// unary_minus(a: bit[N]): bit[N] = -a
+		unary_minus,
+		// equal(a: bit[N], b: bit[N]): bit[1] = (a == b)
+		equal,
+		// not_equal(a: bit[N], b: bit[N]): bit[1] = (a != b)
+		not_equal,
+		// signed_greater_than(a: signed bit[N], b: signed bit[N]): bit[1] = (a > b)
+		signed_greater_than,
+		// signed_greater_equal(a: signed bit[N], b: signed bit[N]): bit[1] = (a >= b)
+		signed_greater_equal,
+		// unsigned_greater_than(a: unsigned bit[N], b: unsigned bit[N]): bit[1] = (a > b)
+		unsigned_greater_than,
+		// unsigned_greater_equal(a: unsigned bit[N], b: unsigned bit[N]): bit[1] = (a >= b)
+		unsigned_greater_equal,
+		// logical_shift_left(a: bit[N], b: unsigned bit[M]): bit[N] = a << b
+		// required: M == clog2(N)
+		logical_shift_left,
+		// logical_shift_right(a: unsigned bit[N], b: unsigned bit[M]): unsigned bit[N] = a >> b
+		// required: M == clog2(N)
+		logical_shift_right,
+		// arithmetic_shift_right(a: signed bit[N], b: unsigned bit[M]): signed bit[N] = a >> b
+		// required: M == clog2(N)
+		arithmetic_shift_right,
+		// mux(a: bit[N], b: bit[N], s: bit[1]): bit[N] = s ? b : a
+		mux,
+		// constant(a: Const[N]): bit[N] = a
+		constant,
+		// input(a: IdString): any
+		// returns the current value of the input with the specified name
+		input,
+		// state(a: IdString): any
+		// returns the current value of the state variable with the specified name
+		state,
+		// memory_read(memory: memory[addr_width, data_width], addr: bit[addr_width]): bit[data_width] = memory[addr]
+		memory_read,
+		// memory_write(memory: memory[addr_width, data_width], addr: bit[addr_width], data: bit[data_width]): memory[addr_width, data_width]
+		// returns a copy of `memory` but with the value at `addr` changed to `data`
+		memory_write
+	};
+	// returns the name of a Fn value, as a string literal
+	const char *fn_to_string(Fn);
+	// Sort represents the sort or type of a node
+	// currently the only two types are signal/bit and memory
+	class Sort {
+		std::variant<int, std::pair<int, int>> _v;
+	public:
+		explicit Sort(int width) : _v(width) { }
+		Sort(int addr_width, int data_width) : _v(std::make_pair(addr_width, data_width)) { }
+		bool is_signal() const { return _v.index() == 0; }
+		bool is_memory() const { return _v.index() == 1; }
+		// returns the width of a bitvector type, errors out for other types
+		int width() const { return std::get<0>(_v); }
+		// returns the address width of a bitvector type, errors out for other types
+		int addr_width() const { return std::get<1>(_v).first; }
+		// returns the data width of a bitvector type, errors out for other types
+		int data_width() const { return std::get<1>(_v).second; }
+		bool operator==(Sort const& other) const { return _v == other._v; }
+		unsigned int hash() const { return mkhash(_v); }
+	};
+	class Factory;
+	class Node;
+	class IR {
+		friend class Factory;
+		friend class Node;
+		// one NodeData is stored per Node, containing the function and non-node arguments
+		// note that NodeData is deduplicated by ComputeGraph
+		class NodeData {
+			Fn _fn;
+			std::variant<
+				std::monostate,
+				RTLIL::Const,
+				IdString,
+				int
+			> _extra;
+		public:
+			NodeData() : _fn(Fn::invalid) {}
+			NodeData(Fn fn) : _fn(fn) {}
+			template<class T> NodeData(Fn fn, T &&extra) : _fn(fn), _extra(std::forward<T>(extra)) {}
+			Fn fn() const { return _fn; }
+			const RTLIL::Const &as_const() const { return std::get<RTLIL::Const>(_extra); }
+			IdString as_idstring() const { return std::get<IdString>(_extra); }
+			int as_int() const { return std::get<int>(_extra); }
+			int hash() const {
+				return mkhash((unsigned int) _fn, mkhash(_extra));
+			}
+			bool operator==(NodeData const &other) const {
+				return _fn == other._fn && _extra == other._extra;
+			}
+		};
+		// Attr contains all the information about a note that should not be deduplicated
+		struct Attr {
+			Sort sort;
+		};
+		// our specialised version of ComputeGraph
+		// the sparse_attr IdString stores a naming suggestion, retrieved with name()
+		// the key is currently used to identify the nodes that represent output and next state values
+		// the bool is true for next state values
+		using Graph = ComputeGraph<NodeData, Attr, IdString, std::pair<IdString, bool>>;
+		Graph _graph;
+		dict<IdString, Sort> _input_sorts;
+		dict<IdString, Sort> _output_sorts;
+		dict<IdString, Sort> _state_sorts;
+		dict<IdString, RTLIL::Const> _initial_state_signal;
+		dict<IdString, MemContents> _initial_state_memory;
+	public:
+		static IR from_module(Module *module);
+		Factory factory();
+		int size() const { return _graph.size(); }
+		Node operator[](int i);
+		void topological_sort();
+		void forward_buf();
+		dict<IdString, Sort> inputs() const { return _input_sorts; }
+		dict<IdString, Sort> outputs() const { return _output_sorts; }
+		dict<IdString, Sort> state() const { return _state_sorts; }
+		RTLIL::Const  const &get_initial_state_signal(IdString name) { return _initial_state_signal.at(name); }
+		MemContents const &get_initial_state_memory(IdString name) { return _initial_state_memory.at(name); }
+		Node get_output_node(IdString name);
+		Node get_state_next_node(IdString name);
+		class iterator {
+			friend class IR;
+			IR *_ir;
+			int _index;
+			iterator(IR *ir, int index) : _ir(ir), _index(index) {}
+		public:
+			using iterator_category = std::input_iterator_tag;
+			using value_type = Node;
+			using pointer = arrow_proxy<Node>;
+			using reference = Node;
+			using difference_type = ptrdiff_t;
+			Node operator*();
+			iterator &operator++() { _index++; return *this; }
+			bool operator!=(iterator const &other) const { return _ir != other._ir || _index != other._index; }
+			bool operator==(iterator const &other) const { return !(*this != other); }
+			pointer operator->();
+			// TODO: implement operator-> using the arrow_proxy class currently in mem.h
+		};
+		iterator begin() { return iterator(this, 0); }
+		iterator end() { return iterator(this, _graph.size()); }
+	};
+	// Node is an immutable reference to a FunctionalIR node
+	class Node {
+		friend class Factory;
+		friend class IR;
+		IR::Graph::ConstRef _ref;
+		explicit Node(IR::Graph::ConstRef ref) : _ref(ref) { }
+		explicit operator IR::Graph::ConstRef() { return _ref; }
+	public:
+		// the node's index. may change if nodes are added or removed
+		int id() const { return _ref.index(); }
+		// a name suggestion for the node, which need not be unique
+		IdString name() const {
+			if(_ref.has_sparse_attr())
+				return _ref.sparse_attr();
+			else
+				return std::string("\\n") + std::to_string(id());
+		}
+		Fn fn() const { return _ref.function().fn(); }
+		Sort sort() const { return _ref.attr().sort; }
+		// returns the width of a bitvector node, errors out for other nodes
+		int width() const { return sort().width(); }
+		size_t arg_count() const { return _ref.size(); }
+		Node arg(int n) const { return Node(_ref.arg(n)); }
+		// visit calls the appropriate visitor method depending on the type of the node
+		template<class Visitor> auto visit(Visitor v) const
+		{
+			// currently templated but could be switched to AbstractVisitor &
+			switch(_ref.function().fn()) {
+			case Fn::invalid: log_error("invalid node in visit"); break;
+			case Fn::buf: return v.buf(*this, arg(0)); break;
+			case Fn::slice: return v.slice(*this, arg(0), _ref.function().as_int(), sort().width()); break;
+			case Fn::zero_extend: return v.zero_extend(*this, arg(0), width()); break;
+			case Fn::sign_extend: return v.sign_extend(*this, arg(0), width()); break;
+			case Fn::concat: return v.concat(*this, arg(0), arg(1)); break;
+			case Fn::add: return v.add(*this, arg(0), arg(1)); break;
+			case Fn::sub: return v.sub(*this, arg(0), arg(1)); break;
+			case Fn::mul: return v.mul(*this, arg(0), arg(1)); break;
+			case Fn::unsigned_div: return v.unsigned_div(*this, arg(0), arg(1)); break;
+			case Fn::unsigned_mod: return v.unsigned_mod(*this, arg(0), arg(1)); break;
+			case Fn::bitwise_and: return v.bitwise_and(*this, arg(0), arg(1)); break;
+			case Fn::bitwise_or: return v.bitwise_or(*this, arg(0), arg(1)); break;
+			case Fn::bitwise_xor: return v.bitwise_xor(*this, arg(0), arg(1)); break;
+			case Fn::bitwise_not: return v.bitwise_not(*this, arg(0)); break;
+			case Fn::unary_minus: return v.unary_minus(*this, arg(0)); break;
+			case Fn::reduce_and: return v.reduce_and(*this, arg(0)); break;
+			case Fn::reduce_or: return v.reduce_or(*this, arg(0)); break;
+			case Fn::reduce_xor: return v.reduce_xor(*this, arg(0)); break;
+			case Fn::equal: return v.equal(*this, arg(0), arg(1)); break;
+			case Fn::not_equal: return v.not_equal(*this, arg(0), arg(1)); break;
+			case Fn::signed_greater_than: return v.signed_greater_than(*this, arg(0), arg(1)); break; 
+			case Fn::signed_greater_equal: return v.signed_greater_equal(*this, arg(0), arg(1)); break;
+			case Fn::unsigned_greater_than: return v.unsigned_greater_than(*this, arg(0), arg(1)); break; 
+			case Fn::unsigned_greater_equal: return v.unsigned_greater_equal(*this, arg(0), arg(1)); break;
+			case Fn::logical_shift_left: return v.logical_shift_left(*this, arg(0), arg(1)); break;
+			case Fn::logical_shift_right: return v.logical_shift_right(*this, arg(0), arg(1)); break;
+			case Fn::arithmetic_shift_right: return v.arithmetic_shift_right(*this, arg(0), arg(1)); break;
+			case Fn::mux: return v.mux(*this, arg(0), arg(1), arg(2)); break;
+			case Fn::constant: return v.constant(*this, _ref.function().as_const()); break;
+			case Fn::input: return v.input(*this, _ref.function().as_idstring()); break;
+			case Fn::state: return v.state(*this, _ref.function().as_idstring()); break;
+			case Fn::memory_read: return v.memory_read(*this, arg(0), arg(1)); break;
+			case Fn::memory_write: return v.memory_write(*this, arg(0), arg(1), arg(2)); break;
+			}
+		}
+		std::string to_string();
+		std::string to_string(std::function<std::string(Node)>);
+	};
+	inline Node IR::operator[](int i) { return Node(_graph[i]); }
+	inline Node IR::get_output_node(IdString name) { return Node(_graph({name, false})); }
+	inline Node IR::get_state_next_node(IdString name) { return Node(_graph({name, true})); }
+	inline Node IR::iterator::operator*() { return Node(_ir->_graph[_index]); }
+	inline arrow_proxy<Node> IR::iterator::operator->() { return arrow_proxy<Node>(**this); }
+	// AbstractVisitor provides an abstract base class for visitors
+	template<class T> struct AbstractVisitor {
+		virtual T buf(Node self, Node n) = 0;
+		virtual T slice(Node self, Node a, int offset, int out_width) = 0;
+		virtual T zero_extend(Node self, Node a, int out_width) = 0;
+		virtual T sign_extend(Node self, Node a, int out_width) = 0;
+		virtual T concat(Node self, Node a, Node b) = 0;
+		virtual T add(Node self, Node a, Node b) = 0;
+		virtual T sub(Node self, Node a, Node b) = 0;
+		virtual T mul(Node self, Node a, Node b) = 0;
+		virtual T unsigned_div(Node self, Node a, Node b) = 0;
+		virtual T unsigned_mod(Node self, Node a, Node b) = 0;
+		virtual T bitwise_and(Node self, Node a, Node b) = 0;
+		virtual T bitwise_or(Node self, Node a, Node b) = 0;
+		virtual T bitwise_xor(Node self, Node a, Node b) = 0;
+		virtual T bitwise_not(Node self, Node a) = 0;
+		virtual T unary_minus(Node self, Node a) = 0;
+		virtual T reduce_and(Node self, Node a) = 0;
+		virtual T reduce_or(Node self, Node a) = 0;
+		virtual T reduce_xor(Node self, Node a) = 0;
+		virtual T equal(Node self, Node a, Node b) = 0;
+		virtual T not_equal(Node self, Node a, Node b) = 0;
+		virtual T signed_greater_than(Node self, Node a, Node b) = 0;
+		virtual T signed_greater_equal(Node self, Node a, Node b) = 0;
+		virtual T unsigned_greater_than(Node self, Node a, Node b) = 0;
+		virtual T unsigned_greater_equal(Node self, Node a, Node b) = 0;
+		virtual T logical_shift_left(Node self, Node a, Node b) = 0;
+		virtual T logical_shift_right(Node self, Node a, Node b) = 0;
+		virtual T arithmetic_shift_right(Node self, Node a, Node b) = 0;
+		virtual T mux(Node self, Node a, Node b, Node s) = 0;
+		virtual T constant(Node self, RTLIL::Const const & value) = 0;
+		virtual T input(Node self, IdString name) = 0;
+		virtual T state(Node self, IdString name) = 0;
+		virtual T memory_read(Node self, Node mem, Node addr) = 0;
+		virtual T memory_write(Node self, Node mem, Node addr, Node data) = 0;
+	};
+	// DefaultVisitor provides defaults for all visitor methods which just calls default_handler
+	template<class T> struct DefaultVisitor : public AbstractVisitor<T> {
+		virtual T default_handler(Node self) = 0;
+		T buf(Node self, Node) override { return default_handler(self); }
+		T slice(Node self, Node, int, int) override { return default_handler(self); }
+		T zero_extend(Node self, Node, int) override { return default_handler(self); }
+		T sign_extend(Node self, Node, int) override { return default_handler(self); }
+		T concat(Node self, Node, Node) override { return default_handler(self); }
+		T add(Node self, Node, Node) override { return default_handler(self); }
+		T sub(Node self, Node, Node) override { return default_handler(self); }
+		T mul(Node self, Node, Node) override { return default_handler(self); }
+		T unsigned_div(Node self, Node, Node) override { return default_handler(self); }
+		T unsigned_mod(Node self, Node, Node) override { return default_handler(self); }
+		T bitwise_and(Node self, Node, Node) override { return default_handler(self); }
+		T bitwise_or(Node self, Node, Node) override { return default_handler(self); }
+		T bitwise_xor(Node self, Node, Node) override { return default_handler(self); }
+		T bitwise_not(Node self, Node) override { return default_handler(self); }
+		T unary_minus(Node self, Node) override { return default_handler(self); }
+		T reduce_and(Node self, Node) override { return default_handler(self); }
+		T reduce_or(Node self, Node) override { return default_handler(self); }
+		T reduce_xor(Node self, Node) override { return default_handler(self); }
+		T equal(Node self, Node, Node) override { return default_handler(self); }
+		T not_equal(Node self, Node, Node) override { return default_handler(self); }
+		T signed_greater_than(Node self, Node, Node) override { return default_handler(self); }
+		T signed_greater_equal(Node self, Node, Node) override { return default_handler(self); }
+		T unsigned_greater_than(Node self, Node, Node) override { return default_handler(self); }
+		T unsigned_greater_equal(Node self, Node, Node) override { return default_handler(self); }
+		T logical_shift_left(Node self, Node, Node) override { return default_handler(self); }
+		T logical_shift_right(Node self, Node, Node) override { return default_handler(self); }
+		T arithmetic_shift_right(Node self, Node, Node) override { return default_handler(self); }
+		T mux(Node self, Node, Node, Node) override { return default_handler(self); }
+		T constant(Node self, RTLIL::Const const &) override { return default_handler(self); }
+		T input(Node self, IdString) override { return default_handler(self); }
+		T state(Node self, IdString) override { return default_handler(self); }
+		T memory_read(Node self, Node, Node) override { return default_handler(self); }
+		T memory_write(Node self, Node, Node, Node) override { return default_handler(self); }
+	};
+	// a factory is used to modify a FunctionalIR. it creates new nodes and allows for some modification of existing nodes.
+	class Factory {
+		friend class IR;
+		IR &_ir;
+		explicit Factory(IR &ir) : _ir(ir) {}
+		Node add(IR::NodeData &&fn, Sort &&sort, std::initializer_list<Node> args) {
+			log_assert(!sort.is_signal() || sort.width() > 0);
+			log_assert(!sort.is_memory() || sort.addr_width() > 0 && sort.data_width() > 0);
+			IR::Graph::Ref ref = _ir._graph.add(std::move(fn), {std::move(sort)});
+			for (auto arg : args)
+				ref.append_arg(IR::Graph::ConstRef(arg));
+			return Node(ref);
+		}
+		IR::Graph::Ref mutate(Node n) {
+			return _ir._graph[n._ref.index()];
+		}
+		void check_basic_binary(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && a.sort() == b.sort()); }
+		void check_shift(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && b.sort().is_signal() && b.width() == ceil_log2(a.width())); }
+		void check_unary(Node const &a) { log_assert(a.sort().is_signal()); }
+	public:
+		Node slice(Node a, int offset, int out_width) {
+			log_assert(a.sort().is_signal() && offset + out_width <= a.sort().width());
+			if(offset == 0 && out_width == a.width())
+				return a;
+			return add(IR::NodeData(Fn::slice, offset), Sort(out_width), {a});
+		}
+		// extend will either extend or truncate the provided value to reach the desired width
+		Node extend(Node a, int out_width, bool is_signed) {
+			int in_width = a.sort().width();
+			log_assert(a.sort().is_signal());
+			if(in_width == out_width)
+				return a;
+			if(in_width > out_width)
+				return slice(a, 0, out_width);
+			if(is_signed)
+				return add(Fn::sign_extend, Sort(out_width), {a});
+			else
+				return add(Fn::zero_extend, Sort(out_width), {a});
+		}
+		Node concat(Node a, Node b) {
+			log_assert(a.sort().is_signal() && b.sort().is_signal());
+			return add(Fn::concat, Sort(a.sort().width() + b.sort().width()), {a, b});
+		}
+		Node add(Node a, Node b) { check_basic_binary(a, b); return add(Fn::add, a.sort(), {a, b}); }
+		Node sub(Node a, Node b) { check_basic_binary(a, b); return add(Fn::sub, a.sort(), {a, b}); }
+		Node mul(Node a, Node b) { check_basic_binary(a, b); return add(Fn::mul, a.sort(), {a, b}); }
+		Node unsigned_div(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_div, a.sort(), {a, b}); }
+		Node unsigned_mod(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_mod, a.sort(), {a, b}); }
+		Node bitwise_and(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_and, a.sort(), {a, b}); }
+		Node bitwise_or(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_or, a.sort(), {a, b}); }
+		Node bitwise_xor(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_xor, a.sort(), {a, b}); }
+		Node bitwise_not(Node a) { check_unary(a); return add(Fn::bitwise_not, a.sort(), {a}); }
+		Node unary_minus(Node a) { check_unary(a); return add(Fn::unary_minus, a.sort(), {a}); }
+		Node reduce_and(Node a) {
+			check_unary(a);
+			if(a.width() == 1)
+				return a;
+			return add(Fn::reduce_and, Sort(1), {a});
+		}
+		Node reduce_or(Node a) {
+			check_unary(a);
+			if(a.width() == 1)
+				return a;
+			return add(Fn::reduce_or, Sort(1), {a});
+		}
+		Node reduce_xor(Node a) { 
+			check_unary(a);
+			if(a.width() == 1)
+				return a;
+			return add(Fn::reduce_xor, Sort(1), {a});
+		}
+		Node equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::equal, Sort(1), {a, b}); }
+		Node not_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::not_equal, Sort(1), {a, b}); }
+		Node signed_greater_than(Node a, Node b) { check_basic_binary(a, b); return add(Fn::signed_greater_than, Sort(1), {a, b}); }
+		Node signed_greater_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::signed_greater_equal, Sort(1), {a, b}); }
+		Node unsigned_greater_than(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_greater_than, Sort(1), {a, b}); }
+		Node unsigned_greater_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_greater_equal, Sort(1), {a, b}); }
+		Node logical_shift_left(Node a, Node b) { check_shift(a, b); return add(Fn::logical_shift_left, a.sort(), {a, b}); }
+		Node logical_shift_right(Node a, Node b) { check_shift(a, b); return add(Fn::logical_shift_right, a.sort(), {a, b}); }
+		Node arithmetic_shift_right(Node a, Node b) { check_shift(a, b); return add(Fn::arithmetic_shift_right, a.sort(), {a, b}); }
+		Node mux(Node a, Node b, Node s) {
+			log_assert(a.sort().is_signal() && a.sort() == b.sort() && s.sort() == Sort(1));
+			return add(Fn::mux, a.sort(), {a, b, s});
+		}
+		Node memory_read(Node mem, Node addr) {
+			log_assert(mem.sort().is_memory() && addr.sort().is_signal() && mem.sort().addr_width() == addr.sort().width());
+			return add(Fn::memory_read, Sort(mem.sort().data_width()), {mem, addr});
+		}
+		Node memory_write(Node mem, Node addr, Node data) {
+			log_assert(mem.sort().is_memory() && addr.sort().is_signal() && data.sort().is_signal() &&
+				mem.sort().addr_width() == addr.sort().width() && mem.sort().data_width() == data.sort().width());
+			return add(Fn::memory_write, mem.sort(), {mem, addr, data});
+		}
+		Node constant(RTLIL::Const value) {
+			return add(IR::NodeData(Fn::constant, std::move(value)), Sort(value.size()), {});
+		}
+		Node create_pending(int width) {
+			return add(Fn::buf, Sort(width), {});
+		}
+		void update_pending(Node node, Node value) {
+			log_assert(node._ref.function() == Fn::buf && node._ref.size() == 0);
+			log_assert(node.sort() == value.sort());
+			mutate(node).append_arg(value._ref);
+		}
+		void add_input(IdString name, int width) {
+			auto [it, inserted] = _ir._input_sorts.emplace(name, Sort(width));
+			if (!inserted) log_error("input `%s` was re-defined", name.c_str());
+		}
+		void add_output(IdString name, int width) {
+			auto [it, inserted] = _ir._output_sorts.emplace(name, Sort(width));
+			if (!inserted) log_error("output `%s` was re-defined", name.c_str());
+		}
+		void add_state(IdString name, Sort sort) {
+			auto [it, inserted] = _ir._state_sorts.emplace(name, sort);
+			if (!inserted) log_error("state `%s` was re-defined", name.c_str());
+		}
+		Node input(IdString name) {
+			return add(IR::NodeData(Fn::input, name), Sort(_ir._input_sorts.at(name)), {});
+		}
+		Node current_state(IdString name) {
+			return add(IR::NodeData(Fn::state, name), Sort(_ir._state_sorts.at(name)), {});
+		}
+		void set_output(IdString output, Node value) {
+			log_assert(_ir._output_sorts.at(output) == value.sort());
+			mutate(value).assign_key({output, false});
+		}
+		void set_initial_state(IdString state, RTLIL::Const value) {
+			Sort &sort = _ir._state_sorts.at(state);
+			value.extu(sort.width());
+			_ir._initial_state_signal.emplace(state, std::move(value));
+		}
+		void set_initial_state(IdString state, MemContents value) {
+			log_assert(Sort(value.addr_width(), value.data_width()) == _ir._state_sorts.at(state));
+			_ir._initial_state_memory.emplace(state, std::move(value));
+		}
+		void set_next_state(IdString state, Node value) {
+			log_assert(_ir._state_sorts.at(state) == value.sort());
+			mutate(value).assign_key({state, true});
+		}
+		void suggest_name(Node node, IdString name) {
+			mutate(node).sparse_attr() = name;
+		}
+	};
+	inline Factory IR::factory() { return Factory(*this); }
+	template<class Id> class Scope {
+	protected:
+		char substitution_character = '_';
+		virtual bool is_character_legal(char) = 0;
+	private:
+		pool<std::string> _used_names;
+		dict<Id, std::string> _by_id;
+	public:
+		void reserve(std::string name) {
+			_used_names.insert(std::move(name));
+		}
+		std::string unique_name(IdString suggestion) {
+			std::string str = RTLIL::unescape_id(suggestion);
+			for(size_t i = 0; i < str.size(); i++)
+				if(!is_character_legal(str[i]))
+					str[i] = substitution_character;
+			if(_used_names.count(str) == 0) {
+				_used_names.insert(str);
+				return str;
+			}
+			for (int idx = 0 ; ; idx++){
+				std::string suffixed = str + "_" + std::to_string(idx);
+				if(_used_names.count(suffixed) == 0) {
+					_used_names.insert(suffixed);
+					return suffixed;
+				}
+			}
+		}
+		std::string operator()(Id id, IdString suggestion) {
+			auto it = _by_id.find(id);
+			if(it != _by_id.end())
+				return it->second;
+			std::string str = unique_name(suggestion);
+			_by_id.insert({id, str});
+			return str;
+		}
+	};
+	class Writer {
+		std::ostream *os;
+		void print_impl(const char *fmt, vector<std::function<void()>>& fns);
+	public:
+		Writer(std::ostream &os) : os(&os) {}
+		template<class T> Writer& operator <<(T&& arg) { *os << std::forward<T>(arg); return *this; }
+		template<typename... Args>
+		void print(const char *fmt, Args&&... args)
+		{
+			vector<std::function<void()>> fns { [&]() { *this << args; }... };
+			print_impl(fmt, fns);
+		}
+		template<typename Fn, typename... Args>
+		void print_with(Fn fn, const char *fmt, Args&&... args)
+		{
+			vector<std::function<void()>> fns { [&]() {
+				if constexpr (std::is_invocable_v<Fn, Args>)
+					*this << fn(args);
+				else
+					*this << args; }...
+			};
+			print_impl(fmt, fns);
+		}
+	};
+
+}
 
 YOSYS_NAMESPACE_END
 
-
 #endif
diff --git a/kernel/functionalir.h b/kernel/functionalir.h
deleted file mode 100644
index fdbdcbde306..00000000000
--- a/kernel/functionalir.h
+++ /dev/null
@@ -1,575 +0,0 @@
-/*
- *  yosys -- Yosys Open SYnthesis Suite
- *
- *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef FUNCTIONALIR_H
-#define FUNCTIONALIR_H
-
-#include "kernel/yosys.h"
-#include "kernel/functional.h"
-#include "kernel/drivertools.h"
-#include "kernel/mem.h"
-#include "kernel/topo_scc.h"
-
-USING_YOSYS_NAMESPACE
-YOSYS_NAMESPACE_BEGIN
-
-class FunctionalIR {
-public:
-	// each function is documented with a short pseudocode declaration or definition
-	// standard C/Verilog operators are used to describe the result
-	// 
-	// the types used in this are:
-	// - bit[N]: a bitvector of N bits
-	//   bit[N] can be indicated as signed or unsigned. this is not tracked by the functional backend
-	//   but is meant to indicate how the value is interpreted
-	//   if a bit[N] is marked as neither signed nor unsigned, this means the result should be valid with *either* interpretation
-	// - memory[N, M]: a memory with N address and M data bits
-	// - int: C++ int
-	// - Const[N]: yosys RTLIL::Const (with size() == N)
-	// - IdString: yosys IdString
-	// - any: used in documentation to indicate that the type is unconstrained
-	//
-	// nodes in the functional backend are either of type bit[N] or memory[N,M] (for some N, M: int)
-	// additionally, they can carry a constant of type int, Const[N] or IdString
-	// each node has a 'sort' field that stores the type of the node
-	// slice, zero_extend, sign_extend use the type field to store out_width
-	enum class Fn {
-		// invalid() = known-invalid/shouldn't happen value
-		// TODO: maybe remove this and use e.g. std::optional instead?
-		invalid,
-		// buf(a: any): any = a
-		// no-op operation
-		// when constructing the compute graph we generate invalid buf() nodes as a placeholder
-		// and later insert the argument
-		buf,
-		// slice(a: bit[in_width], offset: int, out_width: int): bit[out_width] = a[offset +: out_width]
-		// required: offset + out_width <= in_width
-		slice,
-		// zero_extend(a: unsigned bit[in_width], out_width: int): unsigned bit[out_width] = a (zero extended)
-		// required: out_width > in_width
-		zero_extend,
-		// sign_extend(a: signed bit[in_width], out_width: int): signed bit[out_width] = a (sign extended)
-		// required: out_width > in_width
-		sign_extend,
-		// concat(a: bit[N], b: bit[M]): bit[N+M] = {b, a} (verilog syntax)
-		// concatenates two bitvectors, with a in the least significant position and b in the more significant position
-		concat,
-		// add(a: bit[N], b: bit[N]): bit[N] = a + b
-		add,
-		// sub(a: bit[N], b: bit[N]): bit[N] = a - b
-		sub,
-		// mul(a: bit[N], b: bit[N]): bit[N] = a * b
-		mul,
-		// unsigned_div(a: unsigned bit[N], b: unsigned bit[N]): bit[N] = a / b
-		unsigned_div,
-		// unsigned_mod(a: signed bit[N], b: signed bit[N]): bit[N] = a % b
-		unsigned_mod,
-		// bitwise_and(a: bit[N], b: bit[N]): bit[N] = a & b
-		bitwise_and,
-		// bitwise_or(a: bit[N], b: bit[N]): bit[N] = a | b
-		bitwise_or,
-		// bitwise_xor(a: bit[N], b: bit[N]): bit[N] = a ^ b
-		bitwise_xor,
-		// bitwise_not(a: bit[N]): bit[N] = ~a
-		bitwise_not,
-		// reduce_and(a: bit[N]): bit[1] = &a
-		reduce_and,
-		// reduce_or(a: bit[N]): bit[1] = |a
-		reduce_or,
-		// reduce_xor(a: bit[N]): bit[1] = ^a
-		reduce_xor,
-		// unary_minus(a: bit[N]): bit[N] = -a
-		unary_minus,
-		// equal(a: bit[N], b: bit[N]): bit[1] = (a == b)
-		equal,
-		// not_equal(a: bit[N], b: bit[N]): bit[1] = (a != b)
-		not_equal,
-		// signed_greater_than(a: signed bit[N], b: signed bit[N]): bit[1] = (a > b)
-		signed_greater_than,
-		// signed_greater_equal(a: signed bit[N], b: signed bit[N]): bit[1] = (a >= b)
-		signed_greater_equal,
-		// unsigned_greater_than(a: unsigned bit[N], b: unsigned bit[N]): bit[1] = (a > b)
-		unsigned_greater_than,
-		// unsigned_greater_equal(a: unsigned bit[N], b: unsigned bit[N]): bit[1] = (a >= b)
-		unsigned_greater_equal,
-		// logical_shift_left(a: bit[N], b: unsigned bit[M]): bit[N] = a << b
-		// required: M == clog2(N)
-		logical_shift_left,
-		// logical_shift_right(a: unsigned bit[N], b: unsigned bit[M]): unsigned bit[N] = a >> b
-		// required: M == clog2(N)
-		logical_shift_right,
-		// arithmetic_shift_right(a: signed bit[N], b: unsigned bit[M]): signed bit[N] = a >> b
-		// required: M == clog2(N)
-		arithmetic_shift_right,
-		// mux(a: bit[N], b: bit[N], s: bit[1]): bit[N] = s ? b : a
-		mux,
-		// constant(a: Const[N]): bit[N] = a
-		constant,
-		// input(a: IdString): any
-		// returns the current value of the input with the specified name
-		input,
-		// state(a: IdString): any
-		// returns the current value of the state variable with the specified name
-		state,
-		// memory_read(memory: memory[addr_width, data_width], addr: bit[addr_width]): bit[data_width] = memory[addr]
-		memory_read,
-		// memory_write(memory: memory[addr_width, data_width], addr: bit[addr_width], data: bit[data_width]): memory[addr_width, data_width]
-		// returns a copy of `memory` but with the value at `addr` changed to `data`
-		memory_write
-	};
-	// returns the name of a FunctionalIR::Fn value, as a string literal
-	static const char *fn_to_string(Fn);
-	// FunctionalIR::Sort represents the sort or type of a node
-	// currently the only two types are signal/bit and memory
-	class Sort {
-		std::variant<int, std::pair<int, int>> _v;
-	public:
-		explicit Sort(int width) : _v(width) { }
-		Sort(int addr_width, int data_width) : _v(std::make_pair(addr_width, data_width)) { }
-		bool is_signal() const { return _v.index() == 0; }
-		bool is_memory() const { return _v.index() == 1; }
-		// returns the width of a bitvector type, errors out for other types
-		int width() const { return std::get<0>(_v); }
-		// returns the address width of a bitvector type, errors out for other types
-		int addr_width() const { return std::get<1>(_v).first; }
-		// returns the data width of a bitvector type, errors out for other types
-		int data_width() const { return std::get<1>(_v).second; }
-		bool operator==(Sort const& other) const { return _v == other._v; }
-		unsigned int hash() const { return mkhash(_v); }
-	};
-private:
-	// one NodeData is stored per Node, containing the function and non-node arguments
-	// note that NodeData is deduplicated by ComputeGraph
-	class NodeData {
-		Fn _fn;
-		std::variant<
-			std::monostate,
-			RTLIL::Const,
-			IdString,
-			int
-		> _extra;
-	public:
-		NodeData() : _fn(Fn::invalid) {}
-		NodeData(Fn fn) : _fn(fn) {}
-		template<class T> NodeData(Fn fn, T &&extra) : _fn(fn), _extra(std::forward<T>(extra)) {}
-		Fn fn() const { return _fn; }
-		const RTLIL::Const &as_const() const { return std::get<RTLIL::Const>(_extra); }
-		IdString as_idstring() const { return std::get<IdString>(_extra); }
-		int as_int() const { return std::get<int>(_extra); }
-		int hash() const {
-			return mkhash((unsigned int) _fn, mkhash(_extra));
-		}
-		bool operator==(NodeData const &other) const {
-			return _fn == other._fn && _extra == other._extra;
-		}
-	};
-	// Attr contains all the information about a note that should not be deduplicated
-	struct Attr {
-		Sort sort;
-	};
-	// our specialised version of ComputeGraph
-	// the sparse_attr IdString stores a naming suggestion, retrieved with name()
-	// the key is currently used to identify the nodes that represent output and next state values
-	// the bool is true for next state values
-	using Graph = ComputeGraph<NodeData, Attr, IdString, std::pair<IdString, bool>>;
-	Graph _graph;
-	dict<IdString, Sort> _input_sorts;
-	dict<IdString, Sort> _output_sorts;
-	dict<IdString, Sort> _state_sorts;
-	dict<IdString, RTLIL::Const> _initial_state_signal;
-	dict<IdString, MemContents> _initial_state_memory;
-public:
-	class Factory;
-	// Node is an immutable reference to a FunctionalIR node
-	class Node {
-		friend class Factory;
-		friend class FunctionalIR;
-		Graph::ConstRef _ref;
-		explicit Node(Graph::ConstRef ref) : _ref(ref) { }
-		explicit operator Graph::ConstRef() { return _ref; }
-	public:
-		// the node's index. may change if nodes are added or removed
-		int id() const { return _ref.index(); }
-		// a name suggestion for the node, which need not be unique
-		IdString name() const {
-			if(_ref.has_sparse_attr())
-				return _ref.sparse_attr();
-			else
-				return std::string("\\n") + std::to_string(id());
-		}
-		Fn fn() const { return _ref.function().fn(); }
-		Sort sort() const { return _ref.attr().sort; }
-		// returns the width of a bitvector node, errors out for other nodes
-		int width() const { return sort().width(); }
-		size_t arg_count() const { return _ref.size(); }
-		Node arg(int n) const { return Node(_ref.arg(n)); }
-		// visit calls the appropriate visitor method depending on the type of the node
-		template<class Visitor> auto visit(Visitor v) const
-		{
-			// currently templated but could be switched to AbstractVisitor &
-			switch(_ref.function().fn()) {
-			case Fn::invalid: log_error("invalid node in visit"); break;
-			case Fn::buf: return v.buf(*this, arg(0)); break;
-			case Fn::slice: return v.slice(*this, arg(0), _ref.function().as_int(), sort().width()); break;
-			case Fn::zero_extend: return v.zero_extend(*this, arg(0), width()); break;
-			case Fn::sign_extend: return v.sign_extend(*this, arg(0), width()); break;
-			case Fn::concat: return v.concat(*this, arg(0), arg(1)); break;
-			case Fn::add: return v.add(*this, arg(0), arg(1)); break;
-			case Fn::sub: return v.sub(*this, arg(0), arg(1)); break;
-			case Fn::mul: return v.mul(*this, arg(0), arg(1)); break;
-			case Fn::unsigned_div: return v.unsigned_div(*this, arg(0), arg(1)); break;
-			case Fn::unsigned_mod: return v.unsigned_mod(*this, arg(0), arg(1)); break;
-			case Fn::bitwise_and: return v.bitwise_and(*this, arg(0), arg(1)); break;
-			case Fn::bitwise_or: return v.bitwise_or(*this, arg(0), arg(1)); break;
-			case Fn::bitwise_xor: return v.bitwise_xor(*this, arg(0), arg(1)); break;
-			case Fn::bitwise_not: return v.bitwise_not(*this, arg(0)); break;
-			case Fn::unary_minus: return v.unary_minus(*this, arg(0)); break;
-			case Fn::reduce_and: return v.reduce_and(*this, arg(0)); break;
-			case Fn::reduce_or: return v.reduce_or(*this, arg(0)); break;
-			case Fn::reduce_xor: return v.reduce_xor(*this, arg(0)); break;
-			case Fn::equal: return v.equal(*this, arg(0), arg(1)); break;
-			case Fn::not_equal: return v.not_equal(*this, arg(0), arg(1)); break;
-			case Fn::signed_greater_than: return v.signed_greater_than(*this, arg(0), arg(1)); break; 
-			case Fn::signed_greater_equal: return v.signed_greater_equal(*this, arg(0), arg(1)); break;
-			case Fn::unsigned_greater_than: return v.unsigned_greater_than(*this, arg(0), arg(1)); break; 
-			case Fn::unsigned_greater_equal: return v.unsigned_greater_equal(*this, arg(0), arg(1)); break;
-			case Fn::logical_shift_left: return v.logical_shift_left(*this, arg(0), arg(1)); break;
-			case Fn::logical_shift_right: return v.logical_shift_right(*this, arg(0), arg(1)); break;
-			case Fn::arithmetic_shift_right: return v.arithmetic_shift_right(*this, arg(0), arg(1)); break;
-			case Fn::mux: return v.mux(*this, arg(0), arg(1), arg(2)); break;
-			case Fn::constant: return v.constant(*this, _ref.function().as_const()); break;
-			case Fn::input: return v.input(*this, _ref.function().as_idstring()); break;
-			case Fn::state: return v.state(*this, _ref.function().as_idstring()); break;
-			case Fn::memory_read: return v.memory_read(*this, arg(0), arg(1)); break;
-			case Fn::memory_write: return v.memory_write(*this, arg(0), arg(1), arg(2)); break;
-			}
-		}
-		std::string to_string();
-		std::string to_string(std::function<std::string(Node)>);
-	};
-	// AbstractVisitor provides an abstract base class for visitors
-	template<class T> struct AbstractVisitor {
-		virtual T buf(Node self, Node n) = 0;
-		virtual T slice(Node self, Node a, int offset, int out_width) = 0;
-		virtual T zero_extend(Node self, Node a, int out_width) = 0;
-		virtual T sign_extend(Node self, Node a, int out_width) = 0;
-		virtual T concat(Node self, Node a, Node b) = 0;
-		virtual T add(Node self, Node a, Node b) = 0;
-		virtual T sub(Node self, Node a, Node b) = 0;
-		virtual T mul(Node self, Node a, Node b) = 0;
-		virtual T unsigned_div(Node self, Node a, Node b) = 0;
-		virtual T unsigned_mod(Node self, Node a, Node b) = 0;
-		virtual T bitwise_and(Node self, Node a, Node b) = 0;
-		virtual T bitwise_or(Node self, Node a, Node b) = 0;
-		virtual T bitwise_xor(Node self, Node a, Node b) = 0;
-		virtual T bitwise_not(Node self, Node a) = 0;
-		virtual T unary_minus(Node self, Node a) = 0;
-		virtual T reduce_and(Node self, Node a) = 0;
-		virtual T reduce_or(Node self, Node a) = 0;
-		virtual T reduce_xor(Node self, Node a) = 0;
-		virtual T equal(Node self, Node a, Node b) = 0;
-		virtual T not_equal(Node self, Node a, Node b) = 0;
-		virtual T signed_greater_than(Node self, Node a, Node b) = 0;
-		virtual T signed_greater_equal(Node self, Node a, Node b) = 0;
-		virtual T unsigned_greater_than(Node self, Node a, Node b) = 0;
-		virtual T unsigned_greater_equal(Node self, Node a, Node b) = 0;
-		virtual T logical_shift_left(Node self, Node a, Node b) = 0;
-		virtual T logical_shift_right(Node self, Node a, Node b) = 0;
-		virtual T arithmetic_shift_right(Node self, Node a, Node b) = 0;
-		virtual T mux(Node self, Node a, Node b, Node s) = 0;
-		virtual T constant(Node self, RTLIL::Const const & value) = 0;
-		virtual T input(Node self, IdString name) = 0;
-		virtual T state(Node self, IdString name) = 0;
-		virtual T memory_read(Node self, Node mem, Node addr) = 0;
-		virtual T memory_write(Node self, Node mem, Node addr, Node data) = 0;
-	};
-	// DefaultVisitor provides defaults for all visitor methods which just calls default_handler
-	template<class T> struct DefaultVisitor : public AbstractVisitor<T> {
-		virtual T default_handler(Node self) = 0;
-		T buf(Node self, Node) override { return default_handler(self); }
-		T slice(Node self, Node, int, int) override { return default_handler(self); }
-		T zero_extend(Node self, Node, int) override { return default_handler(self); }
-		T sign_extend(Node self, Node, int) override { return default_handler(self); }
-		T concat(Node self, Node, Node) override { return default_handler(self); }
-		T add(Node self, Node, Node) override { return default_handler(self); }
-		T sub(Node self, Node, Node) override { return default_handler(self); }
-		T mul(Node self, Node, Node) override { return default_handler(self); }
-		T unsigned_div(Node self, Node, Node) override { return default_handler(self); }
-		T unsigned_mod(Node self, Node, Node) override { return default_handler(self); }
-		T bitwise_and(Node self, Node, Node) override { return default_handler(self); }
-		T bitwise_or(Node self, Node, Node) override { return default_handler(self); }
-		T bitwise_xor(Node self, Node, Node) override { return default_handler(self); }
-		T bitwise_not(Node self, Node) override { return default_handler(self); }
-		T unary_minus(Node self, Node) override { return default_handler(self); }
-		T reduce_and(Node self, Node) override { return default_handler(self); }
-		T reduce_or(Node self, Node) override { return default_handler(self); }
-		T reduce_xor(Node self, Node) override { return default_handler(self); }
-		T equal(Node self, Node, Node) override { return default_handler(self); }
-		T not_equal(Node self, Node, Node) override { return default_handler(self); }
-		T signed_greater_than(Node self, Node, Node) override { return default_handler(self); }
-		T signed_greater_equal(Node self, Node, Node) override { return default_handler(self); }
-		T unsigned_greater_than(Node self, Node, Node) override { return default_handler(self); }
-		T unsigned_greater_equal(Node self, Node, Node) override { return default_handler(self); }
-		T logical_shift_left(Node self, Node, Node) override { return default_handler(self); }
-		T logical_shift_right(Node self, Node, Node) override { return default_handler(self); }
-		T arithmetic_shift_right(Node self, Node, Node) override { return default_handler(self); }
-		T mux(Node self, Node, Node, Node) override { return default_handler(self); }
-		T constant(Node self, RTLIL::Const const &) override { return default_handler(self); }
-		T input(Node self, IdString) override { return default_handler(self); }
-		T state(Node self, IdString) override { return default_handler(self); }
-		T memory_read(Node self, Node, Node) override { return default_handler(self); }
-		T memory_write(Node self, Node, Node, Node) override { return default_handler(self); }
-	};
-	// a factory is used to modify a FunctionalIR. it creates new nodes and allows for some modification of existing nodes.
-	class Factory {
-		FunctionalIR &_ir;
-		friend class FunctionalIR;
-		explicit Factory(FunctionalIR &ir) : _ir(ir) {}
-		Node add(NodeData &&fn, Sort &&sort, std::initializer_list<Node> args) {
-			log_assert(!sort.is_signal() || sort.width() > 0);
-			log_assert(!sort.is_memory() || sort.addr_width() > 0 && sort.data_width() > 0);
-			Graph::Ref ref = _ir._graph.add(std::move(fn), {std::move(sort)});
-			for (auto arg : args)
-				ref.append_arg(Graph::ConstRef(arg));
-			return Node(ref);
-		}
-		Graph::Ref mutate(Node n) {
-			return _ir._graph[n._ref.index()];
-		}
-		void check_basic_binary(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && a.sort() == b.sort()); }
-		void check_shift(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && b.sort().is_signal() && b.width() == ceil_log2(a.width())); }
-		void check_unary(Node const &a) { log_assert(a.sort().is_signal()); }
-	public:
-		Node slice(Node a, int offset, int out_width) {
-			log_assert(a.sort().is_signal() && offset + out_width <= a.sort().width());
-			if(offset == 0 && out_width == a.width())
-				return a;
-			return add(NodeData(Fn::slice, offset), Sort(out_width), {a});
-		}
-		// extend will either extend or truncate the provided value to reach the desired width
-		Node extend(Node a, int out_width, bool is_signed) {
-			int in_width = a.sort().width();
-			log_assert(a.sort().is_signal());
-			if(in_width == out_width)
-				return a;
-			if(in_width > out_width)
-				return slice(a, 0, out_width);
-			if(is_signed)
-				return add(Fn::sign_extend, Sort(out_width), {a});
-			else
-				return add(Fn::zero_extend, Sort(out_width), {a});
-		}
-		Node concat(Node a, Node b) {
-			log_assert(a.sort().is_signal() && b.sort().is_signal());
-			return add(Fn::concat, Sort(a.sort().width() + b.sort().width()), {a, b});
-		}
-		Node add(Node a, Node b) { check_basic_binary(a, b); return add(Fn::add, a.sort(), {a, b}); }
-		Node sub(Node a, Node b) { check_basic_binary(a, b); return add(Fn::sub, a.sort(), {a, b}); }
-		Node mul(Node a, Node b) { check_basic_binary(a, b); return add(Fn::mul, a.sort(), {a, b}); }
-		Node unsigned_div(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_div, a.sort(), {a, b}); }
-		Node unsigned_mod(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_mod, a.sort(), {a, b}); }
-		Node bitwise_and(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_and, a.sort(), {a, b}); }
-		Node bitwise_or(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_or, a.sort(), {a, b}); }
-		Node bitwise_xor(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_xor, a.sort(), {a, b}); }
-		Node bitwise_not(Node a) { check_unary(a); return add(Fn::bitwise_not, a.sort(), {a}); }
-		Node unary_minus(Node a) { check_unary(a); return add(Fn::unary_minus, a.sort(), {a}); }
-		Node reduce_and(Node a) {
-			check_unary(a);
-			if(a.width() == 1)
-				return a;
-			return add(Fn::reduce_and, Sort(1), {a});
-		}
-		Node reduce_or(Node a) {
-			check_unary(a);
-			if(a.width() == 1)
-				return a;
-			return add(Fn::reduce_or, Sort(1), {a});
-		}
-		Node reduce_xor(Node a) { 
-			check_unary(a);
-			if(a.width() == 1)
-				return a;
-			return add(Fn::reduce_xor, Sort(1), {a});
-		}
-		Node equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::equal, Sort(1), {a, b}); }
-		Node not_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::not_equal, Sort(1), {a, b}); }
-		Node signed_greater_than(Node a, Node b) { check_basic_binary(a, b); return add(Fn::signed_greater_than, Sort(1), {a, b}); }
-		Node signed_greater_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::signed_greater_equal, Sort(1), {a, b}); }
-		Node unsigned_greater_than(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_greater_than, Sort(1), {a, b}); }
-		Node unsigned_greater_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_greater_equal, Sort(1), {a, b}); }
-		Node logical_shift_left(Node a, Node b) { check_shift(a, b); return add(Fn::logical_shift_left, a.sort(), {a, b}); }
-		Node logical_shift_right(Node a, Node b) { check_shift(a, b); return add(Fn::logical_shift_right, a.sort(), {a, b}); }
-		Node arithmetic_shift_right(Node a, Node b) { check_shift(a, b); return add(Fn::arithmetic_shift_right, a.sort(), {a, b}); }
-		Node mux(Node a, Node b, Node s) {
-			log_assert(a.sort().is_signal() && a.sort() == b.sort() && s.sort() == Sort(1));
-			return add(Fn::mux, a.sort(), {a, b, s});
-		}
-		Node memory_read(Node mem, Node addr) {
-			log_assert(mem.sort().is_memory() && addr.sort().is_signal() && mem.sort().addr_width() == addr.sort().width());
-			return add(Fn::memory_read, Sort(mem.sort().data_width()), {mem, addr});
-		}
-		Node memory_write(Node mem, Node addr, Node data) {
-			log_assert(mem.sort().is_memory() && addr.sort().is_signal() && data.sort().is_signal() &&
-				mem.sort().addr_width() == addr.sort().width() && mem.sort().data_width() == data.sort().width());
-			return add(Fn::memory_write, mem.sort(), {mem, addr, data});
-		}
-		Node constant(RTLIL::Const value) {
-			return add(NodeData(Fn::constant, std::move(value)), Sort(value.size()), {});
-		}
-		Node create_pending(int width) {
-			return add(Fn::buf, Sort(width), {});
-		}
-		void update_pending(Node node, Node value) {
-			log_assert(node._ref.function() == Fn::buf && node._ref.size() == 0);
-			log_assert(node.sort() == value.sort());
-			mutate(node).append_arg(value._ref);
-		}
-		void add_input(IdString name, int width) {
-			auto [it, inserted] = _ir._input_sorts.emplace(name, Sort(width));
-			if (!inserted) log_error("input `%s` was re-defined", name.c_str());
-		}
-		void add_output(IdString name, int width) {
-			auto [it, inserted] = _ir._output_sorts.emplace(name, Sort(width));
-			if (!inserted) log_error("output `%s` was re-defined", name.c_str());
-		}
-		void add_state(IdString name, Sort sort) {
-			auto [it, inserted] = _ir._state_sorts.emplace(name, sort);
-			if (!inserted) log_error("state `%s` was re-defined", name.c_str());
-		}
-		Node input(IdString name) {
-			return add(NodeData(Fn::input, name), Sort(_ir._input_sorts.at(name)), {});
-		}
-		Node current_state(IdString name) {
-			return add(NodeData(Fn::state, name), Sort(_ir._state_sorts.at(name)), {});
-		}
-		void set_output(IdString output, Node value) {
-			log_assert(_ir._output_sorts.at(output) == value.sort());
-			mutate(value).assign_key({output, false});
-		}
-		void set_initial_state(IdString state, RTLIL::Const value) {
-			Sort &sort = _ir._state_sorts.at(state);
-			value.extu(sort.width());
-			_ir._initial_state_signal.emplace(state, std::move(value));
-		}
-		void set_initial_state(IdString state, MemContents value) {
-			log_assert(Sort(value.addr_width(), value.data_width()) == _ir._state_sorts.at(state));
-			_ir._initial_state_memory.emplace(state, std::move(value));
-		}
-		void set_next_state(IdString state, Node value) {
-			log_assert(_ir._state_sorts.at(state) == value.sort());
-			mutate(value).assign_key({state, true});
-		}
-		void suggest_name(Node node, IdString name) {
-			mutate(node).sparse_attr() = name;
-		}
-	};
-	static FunctionalIR from_module(Module *module);
-	Factory factory() { return Factory(*this); }
-	int size() const { return _graph.size(); }
-	Node operator[](int i) { return Node(_graph[i]); }
-	void topological_sort();
-	void forward_buf();
-	dict<IdString, Sort> inputs() const { return _input_sorts; }
-	dict<IdString, Sort> outputs() const { return _output_sorts; }
-	dict<IdString, Sort> state() const { return _state_sorts; }
-	RTLIL::Const  const &get_initial_state_signal(IdString name) { return _initial_state_signal.at(name); }
-	MemContents const &get_initial_state_memory(IdString name) { return _initial_state_memory.at(name); }
-	Node get_output_node(IdString name) { return Node(_graph({name, false})); }
-	Node get_state_next_node(IdString name) { return Node(_graph({name, true})); }
-	class Iterator {
-		friend class FunctionalIR;
-		FunctionalIR *_ir;
-		int _index;
-		Iterator(FunctionalIR *ir, int index) : _ir(ir), _index(index) {}
-	public:
-		Node operator*() { return Node(_ir->_graph[_index]); }
-		Iterator &operator++() { _index++; return *this; }
-		bool operator!=(Iterator const &other) const { return _index != other._index; }
-	};
-	Iterator begin() { return Iterator(this, 0); }
-	Iterator end() { return Iterator(this, _graph.size()); }
-};
-
-namespace FunctionalTools {
-	template<class Id> class Scope {
-	protected:
-		char substitution_character = '_';
-		virtual bool is_character_legal(char) = 0;
-	private:
-		pool<std::string> _used_names;
-		dict<Id, std::string> _by_id;
-	public:
-		void reserve(std::string name) {
-			_used_names.insert(std::move(name));
-		}
-		std::string unique_name(IdString suggestion) {
-			std::string str = RTLIL::unescape_id(suggestion);
-			for(size_t i = 0; i < str.size(); i++)
-				if(!is_character_legal(str[i]))
-					str[i] = substitution_character;
-			if(_used_names.count(str) == 0) {
-				_used_names.insert(str);
-				return str;
-			}
-			for (int idx = 0 ; ; idx++){
-				std::string suffixed = str + "_" + std::to_string(idx);
-				if(_used_names.count(suffixed) == 0) {
-					_used_names.insert(suffixed);
-					return suffixed;
-				}
-			}
-		}
-		std::string operator()(Id id, IdString suggestion) {
-			auto it = _by_id.find(id);
-			if(it != _by_id.end())
-				return it->second;
-			std::string str = unique_name(suggestion);
-			_by_id.insert({id, str});
-			return str;
-		}
-	};
-	class Writer {
-		std::ostream *os;
-		void print_impl(const char *fmt, vector<std::function<void()>>& fns);
-	public:
-		Writer(std::ostream &os) : os(&os) {}
-		template<class T> Writer& operator <<(T&& arg) { *os << std::forward<T>(arg); return *this; }
-		template<typename... Args>
-		void print(const char *fmt, Args&&... args)
-		{
-			vector<std::function<void()>> fns { [&]() { *this << args; }... };
-			print_impl(fmt, fns);
-		}
-		template<typename Fn, typename... Args>
-		void print_with(Fn fn, const char *fmt, Args&&... args)
-		{
-			vector<std::function<void()>> fns { [&]() {
-				if constexpr (std::is_invocable_v<Fn, Args>)
-					*this << fn(args);
-				else
-					*this << args; }...
-			};
-			print_impl(fmt, fns);
-		}
-	};
-}
-
-YOSYS_NAMESPACE_END
-
-#endif
diff --git a/kernel/mem.h b/kernel/mem.h
index 4be4b68649e..8c935adc13b 100644
--- a/kernel/mem.h
+++ b/kernel/mem.h
@@ -22,6 +22,7 @@
 
 #include "kernel/yosys.h"
 #include "kernel/ffinit.h"
+#include "kernel/utils.h"
 
 YOSYS_NAMESPACE_BEGIN
 
@@ -224,15 +225,6 @@ struct Mem : RTLIL::AttrObject {
 	Mem(Module *module, IdString memid, int width, int start_offset, int size) : module(module), memid(memid), packed(false), mem(nullptr), cell(nullptr), width(width), start_offset(start_offset), size(size) {}
 };
 
-// this class is used for implementing operator-> on iterators that return values rather than references
-// it's necessary because in C++ operator-> is called recursively until a raw pointer is obtained
-template<class T>
-struct arrow_proxy {
-	T v;
-	explicit arrow_proxy(T const & v) : v(v) {}
-	T* operator->() { return &v; }
-};
-
 // MemContents efficiently represents the contents of a potentially sparse memory by storing only those segments that are actually defined
 class MemContents {
 public:
@@ -303,6 +295,7 @@ class MemContents {
 		reference operator *() const { return range(_memory->_data_width, _addr, _memory->_values.at(_addr)); }
 		pointer operator->() const { return arrow_proxy<range>(**this); }
 		bool operator !=(iterator const &other) const { return _memory != other._memory || _addr != other._addr; }
+		bool operator ==(iterator const &other) const { return !(*this != other); }
 		iterator &operator++();
 	};
 	MemContents(int addr_width, int data_width, RTLIL::Const default_value)
diff --git a/kernel/utils.h b/kernel/utils.h
index 3216c5eb5f0..99f327db4cd 100644
--- a/kernel/utils.h
+++ b/kernel/utils.h
@@ -253,6 +253,15 @@ template <typename T, typename C = std::less<T>, typename OPS = hash_ops<T>> cla
 	}
 };
 
+// this class is used for implementing operator-> on iterators that return values rather than references
+// it's necessary because in C++ operator-> is called recursively until a raw pointer is obtained
+template<class T>
+struct arrow_proxy {
+	T v;
+	explicit arrow_proxy(T const & v) : v(v) {}
+	T* operator->() { return &v; }
+};
+
 YOSYS_NAMESPACE_END
 
 #endif
diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc
index 4b836d75b88..aaf07dadddd 100644
--- a/passes/cmds/example_dt.cc
+++ b/passes/cmds/example_dt.cc
@@ -1,7 +1,7 @@
 #include "kernel/yosys.h"
 #include "kernel/drivertools.h"
 #include "kernel/topo_scc.h"
-#include "kernel/functional.h"
+#include "kernel/compute_graph.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN

From fbee31080e04ebef3ae99e1dfd876a93060c24d2 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 25 Jul 2024 12:25:19 +0100
Subject: [PATCH 426/499] add optional header and hashlib implementation for
 optional

---
 kernel/hashlib.h      | 12 ++++++++++++
 kernel/yosys_common.h |  1 +
 2 files changed, 13 insertions(+)

diff --git a/kernel/hashlib.h b/kernel/hashlib.h
index d32db6832fa..157ccf4ce2d 100644
--- a/kernel/hashlib.h
+++ b/kernel/hashlib.h
@@ -205,6 +205,18 @@ template<typename... T> struct hash_ops<std::variant<T...>> {
 	}
 };
 
+template<typename T> struct hash_ops<std::optional<T>> {
+	static inline bool cmp(std::optional<T> a, std::optional<T> b) {
+		return a == b;
+	}
+	static inline unsigned int hash(std::optional<T> a) {
+		if(a.has_value())
+			return mkhash(*a);
+		else
+			return 0;
+	}
+};
+
 inline int hashtable_size(int min_size)
 {
 	// Primes as generated by https://oeis.org/A175953
diff --git a/kernel/yosys_common.h b/kernel/yosys_common.h
index e71e94a78c5..ec1b5aba2ba 100644
--- a/kernel/yosys_common.h
+++ b/kernel/yosys_common.h
@@ -31,6 +31,7 @@
 #include <unordered_set>
 #include <initializer_list>
 #include <variant>
+#include <optional>
 #include <stdexcept>
 #include <memory>
 #include <cmath>

From 8f774942635a09cd9a30733612d47a92b11fcbd5 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 25 Jul 2024 12:54:58 +0100
Subject: [PATCH 427/499] silence some warnings

---
 kernel/drivertools.h | 8 +++++---
 kernel/functional.h  | 3 ++-
 kernel/mem.h         | 2 +-
 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/kernel/drivertools.h b/kernel/drivertools.h
index 48c846b5f79..b0e435f400f 100644
--- a/kernel/drivertools.h
+++ b/kernel/drivertools.h
@@ -388,6 +388,8 @@ struct DriveBit
 			case DriveType::MULTIPLE:
 				inner = multiple_.hash();
 				break;
+			default:
+				log_abort();
 		}
 		return mkhash((unsigned int)type_, inner);
 	}
@@ -412,7 +414,7 @@ struct DriveBit
 			case DriveType::MULTIPLE:
 				return multiple_ == other.multiple_;
 		}
-		log_assert(false);
+		log_abort();
 	}
 
 	bool operator!=(const DriveBit &other) const
@@ -958,7 +960,7 @@ struct DriveChunk
 			case DriveType::MULTIPLE:
 				return multiple_ == other.multiple_;
 		}
-		log_assert(false);
+		log_abort();
 	}
 
 	bool operator!=(const DriveChunk &other) const
@@ -985,7 +987,7 @@ struct DriveChunk
 			case DriveType::MULTIPLE:
 				return multiple_ < other.multiple_;
 		}
-		log_assert(false);
+		log_abort();
 	}
 
 	DriveType type() const { return type_; }
diff --git a/kernel/functional.h b/kernel/functional.h
index e0592259c7f..08b7b99ca2a 100644
--- a/kernel/functional.h
+++ b/kernel/functional.h
@@ -295,6 +295,7 @@ namespace Functional {
 			case Fn::memory_read: return v.memory_read(*this, arg(0), arg(1)); break;
 			case Fn::memory_write: return v.memory_write(*this, arg(0), arg(1), arg(2)); break;
 			}
+			log_abort();
 		}
 		std::string to_string();
 		std::string to_string(std::function<std::string(Node)>);
@@ -384,7 +385,7 @@ namespace Functional {
 		explicit Factory(IR &ir) : _ir(ir) {}
 		Node add(IR::NodeData &&fn, Sort &&sort, std::initializer_list<Node> args) {
 			log_assert(!sort.is_signal() || sort.width() > 0);
-			log_assert(!sort.is_memory() || sort.addr_width() > 0 && sort.data_width() > 0);
+			log_assert(!sort.is_memory() || (sort.addr_width() > 0 && sort.data_width() > 0));
 			IR::Graph::Ref ref = _ir._graph.add(std::move(fn), {std::move(sort)});
 			for (auto arg : args)
 				ref.append_arg(IR::Graph::ConstRef(arg));
diff --git a/kernel/mem.h b/kernel/mem.h
index 8c935adc13b..4a6a9a431f4 100644
--- a/kernel/mem.h
+++ b/kernel/mem.h
@@ -318,7 +318,7 @@ class MemContents {
 	// insert multiple words at the given address, overriding any previous assignment.
 	template<typename Iterator> void insert_range(addr_t addr, Iterator begin, Iterator end) {
 		auto words = end - begin;
-		log_assert(addr < 1<<_addr_width); log_assert(words <= (1<<_addr_width) - addr);
+		log_assert(addr < (addr_t)(1<<_addr_width)); log_assert(words <= (addr_t)(1<<_addr_width) - addr);
 		auto range = _reserve_range(addr, addr + words);
 		auto it = _range_data(range, addr);
 		for(; begin != end; ++begin)

From 79a1b691ea159230ee5c3938f1e136a25fc896b0 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 25 Jul 2024 13:11:56 +0100
Subject: [PATCH 428/499] silence some more warnings, undo mistaken addition

---
 kernel/drivertools.h |  3 +--
 kernel/mem.cc        | 10 +++++-----
 2 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/kernel/drivertools.h b/kernel/drivertools.h
index b0e435f400f..8a51b88d9ef 100644
--- a/kernel/drivertools.h
+++ b/kernel/drivertools.h
@@ -388,8 +388,6 @@ struct DriveBit
 			case DriveType::MULTIPLE:
 				inner = multiple_.hash();
 				break;
-			default:
-				log_abort();
 		}
 		return mkhash((unsigned int)type_, inner);
 	}
@@ -1028,6 +1026,7 @@ struct DriveChunk
 			case DriveType::MULTIPLE:
 				return multiple_.size();
 		}
+		log_abort();
 	}
 };
 
diff --git a/kernel/mem.cc b/kernel/mem.cc
index 46e4331c5a7..80be52a0eee 100644
--- a/kernel/mem.cc
+++ b/kernel/mem.cc
@@ -1729,8 +1729,8 @@ void MemContents::check() {
 		log_assert(!it->second.empty());
 		log_assert(it->second.size() % _data_width == 0);
 		auto end1 = _range_end(it);
-		log_assert(_range_begin(it) < (1<<_addr_width));
-		log_assert(end1 <= (1<<_addr_width));
+		log_assert(_range_begin(it) < (addr_t)(1<<_addr_width));
+		log_assert(end1 <= (addr_t)(1<<_addr_width));
 		if(++it == _values.end())
 			break;
 		// check that ranges neither overlap nor touch
@@ -1760,7 +1760,7 @@ bool MemContents::_range_overlaps(std::map<addr_t, RTLIL::Const>::iterator it, a
 
 std::map<addr_t, RTLIL::Const>::iterator MemContents::_range_at(addr_t addr) const {
 	// allow addr == 1<<_addr_width (which will just return end())
-	log_assert(addr <= 1<<_addr_width);
+	log_assert(addr <= (addr_t)(1<<_addr_width));
 	// get the first range with base > addr
 	// (we use const_cast since map::iterators are only passed around internally and not exposed to the user
 	// and using map::iterator in both the const and non-const case simplifies the code a little,
@@ -1879,8 +1879,8 @@ std::map<addr_t, RTLIL::Const>::iterator MemContents::_reserve_range(addr_t begi
 
 void MemContents::insert_concatenated(addr_t addr, RTLIL::Const const &values) {
 	addr_t words = (values.size() + _data_width - 1) / _data_width;
-	log_assert(addr < 1<<_addr_width);
-	log_assert(words <= (1<<_addr_width) - addr);
+	log_assert(addr < (addr_t)(1<<_addr_width));
+	log_assert(words <= (addr_t)(1<<_addr_width) - addr);
 	auto it = _reserve_range(addr, addr + words);
 	auto to_begin = _range_data(it, addr);
 	std::copy(values.bits.begin(), values.bits.end(), to_begin);

From 50047d25b3806fb614c983a950de85b09db8fcfc Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Tue, 6 Aug 2024 09:56:28 +0100
Subject: [PATCH 429/499] functional backend: add different types of
 input/output/state variables

---
 backends/functional/cxx.cc          |  38 +++----
 backends/functional/smtlib.cc       |  36 +++---
 backends/functional/test_generic.cc |   8 +-
 kernel/functional.cc                | 112 +++++++++++++++----
 kernel/functional.h                 | 163 ++++++++++++++++++----------
 5 files changed, 237 insertions(+), 120 deletions(-)

diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index a4755e144c3..19740777fb7 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -150,8 +150,8 @@ template<class NodePrinter> struct CxxPrintVisitor : public Functional::Abstract
 	void arithmetic_shift_right(Node, Node a, Node b) override { print("{}.arithmetic_shift_right({})", a, b); }
 	void mux(Node, Node a, Node b, Node s) override { print("{2}.any() ? {1} : {0}", a, b, s); }
 	void constant(Node, RTLIL::Const const & value) override { print("{}", cxx_const(value)); }
-	void input(Node, IdString name) override { print("input.{}", input_struct[name]); }
-	void state(Node, IdString name) override { print("current_state.{}", state_struct[name]); }
+	void input(Node, IdString name, IdString type) override { log_assert(type == ID($input)); print("input.{}", input_struct[name]); }
+	void state(Node, IdString name, IdString type) override { log_assert(type == ID($state)); print("current_state.{}", state_struct[name]); }
 	void memory_read(Node, Node mem, Node addr) override { print("{}.read({})", mem, addr); }
 	void memory_write(Node, Node mem, Node addr, Node data) override { print("{}.write({}, {})", mem, addr, data); }
 };
@@ -175,12 +175,12 @@ struct CxxModule {
 		output_struct("Outputs"),
 		state_struct("State")
 	{
-		for (auto [name, sort] : ir.inputs())
-			input_struct.insert(name, sort);
-		for (auto [name, sort] : ir.outputs())
-			output_struct.insert(name, sort);
-		for (auto [name, sort] : ir.state())
-			state_struct.insert(name, sort);
+		for (auto input : ir.inputs())
+			input_struct.insert(input->name, input->sort);
+		for (auto output : ir.outputs())
+			output_struct.insert(output->name, output->sort);
+		for (auto state : ir.states())
+			state_struct.insert(state->name, state->sort);
 		module_name = CxxScope<int>().unique_name(module->name);
 	}
 	void write_header(CxxWriter &f) {
@@ -197,19 +197,19 @@ struct CxxModule {
 	}
 	void write_initial_def(CxxWriter &f) {
 		f.print("void {0}::initialize({0}::State &state)\n{{\n", module_name);
-		for (auto [name, sort] : ir.state()) {
-			if (sort.is_signal())
-				f.print("\tstate.{} = {};\n", state_struct[name], cxx_const(ir.get_initial_state_signal(name)));
-			else if (sort.is_memory()) {
+		for (auto state : ir.states()) {
+			if (state->sort.is_signal())
+				f.print("\tstate.{} = {};\n", state_struct[state->name], cxx_const(state->initial_value_signal()));
+			else if (state->sort.is_memory()) {
 				f.print("\t{{\n");
-				f.print("\t\tstd::array<Signal<{}>, {}> mem;\n", sort.data_width(), 1<<sort.addr_width());
-				const auto &contents = ir.get_initial_state_memory(name);
+				f.print("\t\tstd::array<Signal<{}>, {}> mem;\n", state->sort.data_width(), 1<<state->sort.addr_width());
+				const auto &contents = state->initial_value_memory();
 				f.print("\t\tmem.fill({});\n", cxx_const(contents.default_value()));
 				for(auto range : contents)
 					for(auto addr = range.base(); addr < range.limit(); addr++)
 						if(!equal_def(range[addr], contents.default_value()))
 							f.print("\t\tmem[{}] = {};\n", addr, cxx_const(range[addr]));
-				f.print("\t\tstate.{} = mem;\n", state_struct[name]);
+				f.print("\t\tstate.{} = mem;\n", state_struct[state->name]);
 				f.print("\t}}\n");
 			}
 		}
@@ -229,10 +229,10 @@ struct CxxModule {
 			node.visit(printVisitor);
 			f.print(";\n");
 		}
-		for (auto [name, sort] : ir.state())
-			f.print("\tnext_state.{} = {};\n", state_struct[name], node_name(ir.get_state_next_node(name)));
-		for (auto [name, sort] : ir.outputs())
-			f.print("\toutput.{} = {};\n", output_struct[name], node_name(ir.get_output_node(name)));
+		for (auto state : ir.states())
+			f.print("\tnext_state.{} = {};\n", state_struct[state->name], node_name(state->next_value()));
+		for (auto output : ir.outputs())
+			f.print("\toutput.{} = {};\n", output_struct[output->name], node_name(output->value()));
 		f.print("}}\n\n");
 	}
 };
diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index 7fd6fe564c2..ec9e6b24279 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -178,8 +178,8 @@ struct SmtPrintVisitor : public Functional::AbstractVisitor<SExpr> {
 	SExpr memory_read(Node, Node mem, Node addr) override { return list("select", n(mem), n(addr)); }
 	SExpr memory_write(Node, Node mem, Node addr, Node data) override { return list("store", n(mem), n(addr), n(data)); }
 
-	SExpr input(Node, IdString name) override { return input_struct.access("inputs", name); }
-	SExpr state(Node, IdString name) override { return state_struct.access("state", name); }
+	SExpr input(Node, IdString name, IdString type) override { log_assert(type == ID($input)); return input_struct.access("inputs", name); }
+	SExpr state(Node, IdString name, IdString type) override { log_assert(type == ID($state)); return state_struct.access("state", name); }
 };
 
 struct SmtModule {
@@ -200,12 +200,12 @@ struct SmtModule {
 		, state_struct(scope.unique_name(module->name.str() + "_State"), scope)
 	{
 		scope.reserve(name + "-initial");
-		for (const auto &input : ir.inputs())
-			input_struct.insert(input.first, input.second);
-		for (const auto &output : ir.outputs())
-			output_struct.insert(output.first, output.second);
-		for (const auto &state : ir.state())
-			state_struct.insert(state.first, state.second);
+		for (auto input : ir.inputs())
+			input_struct.insert(input->name, input->sort);
+		for (auto output : ir.outputs())
+			output_struct.insert(output->name, output->sort);
+		for (auto state : ir.states())
+			state_struct.insert(state->name, state->sort);
 	}
 
 	void write_eval(SExprWriter &w)
@@ -232,8 +232,8 @@ struct SmtModule {
 				w.comment(SmtSort(n.sort()).to_sexpr().to_string(), true);
 			}
 		w.open(list("pair"));
-		output_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.get_output_node(name)); });
-		state_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.get_state_next_node(name)); });
+		output_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.output(name).value()); });
+		state_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.state(name).next_value()); });
 		w.pop();
 	}
 
@@ -241,14 +241,14 @@ struct SmtModule {
 	{
 		std::string initial = name + "-initial";
 		w << list("declare-const", initial, state_struct.name);
-		for (const auto &[name, sort] : ir.state()) {
-			if(sort.is_signal())
-				w << list("assert", list("=", state_struct.access(initial, name), smt_const(ir.get_initial_state_signal(name))));
-			else if(sort.is_memory()) {
-				auto contents = ir.get_initial_state_memory(name);
-				for(int i = 0; i < 1<<sort.addr_width(); i++) {
-					auto addr = smt_const(RTLIL::Const(i, sort.addr_width()));
-					w << list("assert", list("=", list("select", state_struct.access(initial, name), addr), smt_const(contents[i])));
+		for (auto state : ir.states()) {
+			if(state->sort.is_signal())
+				w << list("assert", list("=", state_struct.access(initial, state->name), smt_const(state->initial_value_signal())));
+			else if(state->sort.is_memory()) {
+				const auto &contents = state->initial_value_memory();
+				for(int i = 0; i < 1<<state->sort.addr_width(); i++) {
+					auto addr = smt_const(RTLIL::Const(i, state->sort.addr_width()));
+					w << list("assert", list("=", list("select", state_struct.access(initial, state->name), addr), smt_const(contents[i])));
 				}
 			}
 		}
diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc
index 83ea09d8ddb..1617d54c069 100644
--- a/backends/functional/test_generic.cc
+++ b/backends/functional/test_generic.cc
@@ -142,10 +142,10 @@ struct FunctionalTestGeneric : public Pass
 			auto fir = Functional::IR::from_module(module);
 			for(auto node : fir)
 				std::cout << RTLIL::unescape_id(node.name()) << " = " << node.to_string([](auto n) { return RTLIL::unescape_id(n.name()); }) << "\n";
-			for(auto [name, sort] : fir.outputs())
-				std::cout << "output " << RTLIL::unescape_id(name) << " = " << RTLIL::unescape_id(fir.get_output_node(name).name()) << "\n";
-			for(auto [name, sort] : fir.state())
-				std::cout << "state " << RTLIL::unescape_id(name) << " = " << RTLIL::unescape_id(fir.get_state_next_node(name).name()) << "\n";
+			for(auto output : fir.all_outputs())
+				std::cout << RTLIL::unescape_id(output->type) << " " << RTLIL::unescape_id(output->name) << " = " << RTLIL::unescape_id(output->value().name()) << "\n";
+			for(auto state : fir.all_states())
+				std::cout << RTLIL::unescape_id(state->type) << " " << RTLIL::unescape_id(state->name) << " = " << RTLIL::unescape_id(state->next_value().name()) << "\n";
 		}
 	}
 } FunctionalCxxBackend;
diff --git a/kernel/functional.cc b/kernel/functional.cc
index ad507187db2..202eaa50221 100644
--- a/kernel/functional.cc
+++ b/kernel/functional.cc
@@ -65,6 +65,51 @@ const char *fn_to_string(Fn fn) {
 	log_error("fn_to_string: unknown Functional::Fn value %d", (int)fn);
 }
 
+vector<IRInput const*> IR::inputs(IdString type) const {
+	vector<IRInput const*> ret;
+	for (const auto &[name, input] : _inputs)
+		if(input.type == type)
+			ret.push_back(&input);
+	return ret;
+}
+
+vector<IROutput const*> IR::outputs(IdString type) const {
+	vector<IROutput const*> ret;
+	for (const auto &[name, output] : _outputs)
+		if(output.type == type)
+			ret.push_back(&output);
+	return ret;
+}
+
+vector<IRState const*> IR::states(IdString type) const {
+	vector<IRState const*> ret;
+	for (const auto &[name, state] : _states)
+		if(state.type == type)
+			ret.push_back(&state);
+	return ret;
+}
+
+vector<IRInput const*> IR::all_inputs() const {
+	vector<IRInput const*> ret;
+	for (const auto &[name, input] : _inputs)
+		ret.push_back(&input);
+	return ret;
+}
+
+vector<IROutput const*> IR::all_outputs() const {
+	vector<IROutput const*> ret;
+	for (const auto &[name, output] : _outputs)
+		ret.push_back(&output);
+	return ret;
+}
+
+vector<IRState const*> IR::all_states() const {
+	vector<IRState const*> ret;
+	for (const auto &[name, state] : _states)
+		ret.push_back(&state);
+	return ret;
+}
+
 struct PrintVisitor : DefaultVisitor<std::string> {
 	std::function<std::string(Node)> np;
 	PrintVisitor(std::function<std::string(Node)> np) : np(np) { }
@@ -73,8 +118,8 @@ struct PrintVisitor : DefaultVisitor<std::string> {
 	std::string zero_extend(Node, Node a, int out_width) override { return "zero_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; }
 	std::string sign_extend(Node, Node a, int out_width) override { return "sign_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; }
 	std::string constant(Node, RTLIL::Const const& value) override { return "constant(" + value.as_string() + ")"; }
-	std::string input(Node, IdString name) override { return "input(" + name.str() + ")"; }
-	std::string state(Node, IdString name) override { return "state(" + name.str() + ")"; }
+	std::string input(Node, IdString name, IdString type) override { return "input(" + name.str() + ", " + type.str() + ")"; }
+	std::string state(Node, IdString name, IdString type) override { return "state(" + name.str() + ", " + type.str() + ")"; }
 	std::string default_handler(Node self) override {
 		std::string ret = fn_to_string(self.fn());
 		ret += "(";
@@ -199,7 +244,7 @@ class CellSimplifier {
 		return handle_alu(g, factory.bitwise_or(p, g), g.width(), false, ci, factory.constant(Const(State::S0, 1))).at(ID(CO));
 	}
 public:
-	std::variant<dict<IdString, Node>, Node> handle(IdString cellType, dict<IdString, Const> parameters, dict<IdString, Node> inputs)
+	std::variant<dict<IdString, Node>, Node> handle(IdString cellName, IdString cellType, dict<IdString, Const> parameters, dict<IdString, Node> inputs)
 	{
 		int a_width = parameters.at(ID(A_WIDTH), Const(-1)).as_int();
 		int b_width = parameters.at(ID(B_WIDTH), Const(-1)).as_int();
@@ -392,6 +437,26 @@ class CellSimplifier {
 			return handle_lcu(inputs.at(ID(P)), inputs.at(ID(G)), inputs.at(ID(CI)));
 		} else if(cellType == ID($alu)) {
 			return handle_alu(inputs.at(ID(A)), inputs.at(ID(B)), y_width, a_signed && b_signed, inputs.at(ID(CI)), inputs.at(ID(BI)));
+		} else if(cellType.in({ID($assert), ID($assume), ID($live), ID($fair), ID($cover)})) {
+			Node a = factory.mux(factory.constant(Const(State::S1, 1)), inputs.at(ID(A)), inputs.at(ID(EN)));
+			auto &output = factory.add_output(cellName, cellType, Sort(1));
+			output.set_value(a);
+			return {};
+		} else if(cellType.in({ID($anyconst), ID($allconst), ID($anyseq), ID($allseq)})) {
+			int width = parameters.at(ID(WIDTH)).as_int();
+			auto &input = factory.add_input(cellName, cellType, Sort(width));
+			return factory.value(input);
+		} else if(cellType == ID($initstate)) {
+			if(factory.ir().has_state(ID($initstate), ID($state)))
+				return factory.value(factory.ir().state(ID($initstate)));
+			else {
+				auto &state = factory.add_state(ID($initstate), ID($state), Sort(1));
+				state.set_initial_value(RTLIL::Const(State::S1, 1));
+				state.set_next_value(factory.constant(RTLIL::Const(State::S0, 1)));
+				return factory.value(state);
+			}
+		} else if(cellType == ID($check)) {
+			log_error("The design contains a $check cell `%s'. This is not supported by the functional backend. Call `chformal -lower' to avoid this error.\n", cellName.c_str());
 		} else {
 			log_error("`%s' cells are not supported by the functional backend\n", cellType.c_str());
 		}
@@ -448,16 +513,15 @@ class FunctionalIRConstruction {
 	{
 		driver_map.add(module);
 		for (auto cell : module->cells()) {
-			if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($check)))
+			if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover), ID($check)))
 				queue.emplace_back(cell);
 		}
 		for (auto wire : module->wires()) {
 			if (wire->port_input)
-				factory.add_input(wire->name, wire->width);
+				factory.add_input(wire->name, ID($input), Sort(wire->width));
 			if (wire->port_output) {
-				factory.add_output(wire->name, wire->width);
-				Node value = enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width)));
-				factory.set_output(wire->name, value);
+				auto &output = factory.add_output(wire->name, ID($output), Sort(wire->width));
+				output.set_value(enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width))));
 			}
 		}
 		memories_vector = Mem::get_all_memories(module);
@@ -495,9 +559,9 @@ class FunctionalIRConstruction {
 		// - Since wr port j can only have priority over wr port i if j > i, if we do writes in
 		//   ascending index order the result will obey the priorty relation.
 		vector<Node> read_results;
-		factory.add_state(mem->cell->name, Sort(ceil_log2(mem->size), mem->width));
-		factory.set_initial_state(mem->cell->name, MemContents(mem));
-		Node node = factory.current_state(mem->cell->name);
+		auto &state = factory.add_state(mem->cell->name, ID($state), Sort(ceil_log2(mem->size), mem->width));
+		state.set_initial_value(MemContents(mem));
+		Node node = factory.value(state);
 		for (size_t i = 0; i < mem->wr_ports.size(); i++) {
 			const auto &wr = mem->wr_ports[i];
 			if (wr.clk_enable)
@@ -521,7 +585,7 @@ class FunctionalIRConstruction {
 			Node addr = enqueue(driver_map(DriveSpec(rd.addr)));
 			read_results.push_back(factory.memory_read(node, addr));
 		}
-		factory.set_next_state(mem->cell->name, node);
+		state.set_next_value(node);
 		return concatenate_read_results(mem, read_results);
 	}
 	void process_cell(Cell *cell)
@@ -540,25 +604,25 @@ class FunctionalIRConstruction {
 			if (!ff.has_gclk)
 				log_error("The design contains a %s flip-flop at %s. This is not supported by the functional backend. "
 					"Call async2sync or clk2fflogic to avoid this error.\n", log_id(cell->type), log_id(cell));
-			factory.add_state(ff.name, Sort(ff.width));
-			Node q_value = factory.current_state(ff.name);
+			auto &state = factory.add_state(ff.name, ID($state), Sort(ff.width));
+			Node q_value = factory.value(state);
 			factory.suggest_name(q_value, ff.name);
 			factory.update_pending(cell_outputs.at({cell, ID(Q)}), q_value);
-			factory.set_next_state(ff.name, enqueue(ff.sig_d));
-			factory.set_initial_state(ff.name, ff.val_init);
+			state.set_next_value(enqueue(ff.sig_d));
+			state.set_initial_value(ff.val_init);
 		} else {
 			dict<IdString, Node> connections;
 			IdString output_name; // for the single output case
 			int n_outputs = 0;
 			for(auto const &[name, sigspec] : cell->connections()) {
-				if(driver_map.celltypes.cell_input(cell->type, name))
+				if(driver_map.celltypes.cell_input(cell->type, name) && sigspec.size() > 0)
 					connections.insert({ name, enqueue(DriveChunkPort(cell, {name, sigspec})) });
 				if(driver_map.celltypes.cell_output(cell->type, name)) {
 					output_name = name;
 					n_outputs++;
 				}
 			}
-			std::variant<dict<IdString, Node>, Node> outputs = simplifier.handle(cell->type, cell->parameters, connections);
+			std::variant<dict<IdString, Node>, Node> outputs = simplifier.handle(cell->name, cell->type, cell->parameters, connections);
 			if(auto *nodep = std::get_if<Node>(&outputs); nodep != nullptr) {
 				log_assert(n_outputs == 1);
 				factory.update_pending(cell_outputs.at({cell, output_name}), *nodep);
@@ -591,7 +655,7 @@ class FunctionalIRConstruction {
 					DriveChunkWire wire_chunk = chunk.wire();
 					if (wire_chunk.is_whole()) {
 						if (wire_chunk.wire->port_input) {
-							Node node = factory.input(wire_chunk.wire->name);
+							Node node = factory.value(factory.ir().input(wire_chunk.wire->name));
 							factory.suggest_name(node, wire_chunk.wire->name);
 							factory.update_pending(pending, node);
 						} else {
@@ -668,10 +732,12 @@ void IR::topological_sort() {
             scc = true;
         }
     });
-	for(const auto &[name, sort]: _state_sorts)
-		toposort.process(get_state_next_node(name).id());
-	for(const auto &[name, sort]: _output_sorts)
-		toposort.process(get_output_node(name).id());
+	for(const auto &[name, state]: _states)
+		if(state.has_next_value())
+			toposort.process(state.next_value().id());
+	for(const auto &[name, output]: _outputs)
+		if(output.has_value())
+			toposort.process(output.value().id());
 	// any nodes untouched by this point are dead code and will be removed by permute
     _graph.permute(perm);
     if(scc) log_error("The design contains combinational loops. This is not supported by the functional backend. "
diff --git a/kernel/functional.h b/kernel/functional.h
index 08b7b99ca2a..f7ff08228b1 100644
--- a/kernel/functional.h
+++ b/kernel/functional.h
@@ -152,11 +152,60 @@ namespace Functional {
 		bool operator==(Sort const& other) const { return _v == other._v; }
 		unsigned int hash() const { return mkhash(_v); }
 	};
+	class IR;
 	class Factory;
 	class Node;
+	class IRInput {
+		friend class Factory;
+	public:
+		IdString name;
+		IdString type;
+		Sort sort;
+	private:
+		IRInput(IR &, IdString name, IdString type, Sort sort)
+		: name(name), type(type), sort(std::move(sort)) {}
+	};
+	class IROutput {
+		friend class Factory;
+		IR &_ir;
+	public:
+		IdString name;
+		IdString type;
+		Sort sort;
+	private:
+		IROutput(IR &ir, IdString name, IdString type, Sort sort)
+		: _ir(ir), name(name), type(type), sort(std::move(sort)) {}
+	public:
+		Node value() const;
+		bool has_value() const;
+		void set_value(Node value);
+	};
+	class IRState {
+		friend class Factory;
+		IR &_ir;
+	public:
+		IdString name;
+		IdString type;
+		Sort sort;
+	private:
+		std::variant<RTLIL::Const, MemContents> _initial;
+		IRState(IR &ir, IdString name, IdString type, Sort sort)
+		: _ir(ir), name(name), type(type), sort(std::move(sort)) {}
+	public:
+		Node next_value() const;
+		bool has_next_value() const;
+		RTLIL::Const const& initial_value_signal() const { return std::get<RTLIL::Const>(_initial); }
+		MemContents const& initial_value_memory() const { return std::get<MemContents>(_initial); }
+		void set_next_value(Node value);
+		void set_initial_value(RTLIL::Const value) { value.extu(sort.width()); _initial = std::move(value); }
+		void set_initial_value(MemContents value) { log_assert(Sort(value.addr_width(), value.data_width()) == sort); _initial = std::move(value); }
+	};
 	class IR {
 		friend class Factory;
 		friend class Node;
+		friend class IRInput;
+		friend class IROutput;
+		friend class IRState;
 		// one NodeData is stored per Node, containing the function and non-node arguments
 		// note that NodeData is deduplicated by ComputeGraph
 		class NodeData {
@@ -164,7 +213,7 @@ namespace Functional {
 			std::variant<
 				std::monostate,
 				RTLIL::Const,
-				IdString,
+				std::pair<IdString, IdString>,
 				int
 			> _extra;
 		public:
@@ -173,7 +222,7 @@ namespace Functional {
 			template<class T> NodeData(Fn fn, T &&extra) : _fn(fn), _extra(std::forward<T>(extra)) {}
 			Fn fn() const { return _fn; }
 			const RTLIL::Const &as_const() const { return std::get<RTLIL::Const>(_extra); }
-			IdString as_idstring() const { return std::get<IdString>(_extra); }
+			std::pair<IdString, IdString> as_idstring_pair() const { return std::get<std::pair<IdString, IdString>>(_extra); }
 			int as_int() const { return std::get<int>(_extra); }
 			int hash() const {
 				return mkhash((unsigned int) _fn, mkhash(_extra));
@@ -190,13 +239,12 @@ namespace Functional {
 		// the sparse_attr IdString stores a naming suggestion, retrieved with name()
 		// the key is currently used to identify the nodes that represent output and next state values
 		// the bool is true for next state values
-		using Graph = ComputeGraph<NodeData, Attr, IdString, std::pair<IdString, bool>>;
+		using Graph = ComputeGraph<NodeData, Attr, IdString, std::tuple<IdString, IdString, bool>>;
 		Graph _graph;
-		dict<IdString, Sort> _input_sorts;
-		dict<IdString, Sort> _output_sorts;
-		dict<IdString, Sort> _state_sorts;
-		dict<IdString, RTLIL::Const> _initial_state_signal;
-		dict<IdString, MemContents> _initial_state_memory;
+		dict<std::pair<IdString, IdString>, IRInput> _inputs;
+		dict<std::pair<IdString, IdString>, IROutput> _outputs;
+		dict<std::pair<IdString, IdString>, IRState> _states;
+		IR::Graph::Ref mutate(Node n);
 	public:
 		static IR from_module(Module *module);
 		Factory factory();
@@ -204,13 +252,24 @@ namespace Functional {
 		Node operator[](int i);
 		void topological_sort();
 		void forward_buf();
-		dict<IdString, Sort> inputs() const { return _input_sorts; }
-		dict<IdString, Sort> outputs() const { return _output_sorts; }
-		dict<IdString, Sort> state() const { return _state_sorts; }
-		RTLIL::Const  const &get_initial_state_signal(IdString name) { return _initial_state_signal.at(name); }
-		MemContents const &get_initial_state_memory(IdString name) { return _initial_state_memory.at(name); }
-		Node get_output_node(IdString name);
-		Node get_state_next_node(IdString name);
+		IRInput const& input(IdString name, IdString type) const { return _inputs.at({name, type}); }
+		IRInput const& input(IdString name) const { return input(name, ID($input)); }
+		IROutput const& output(IdString name, IdString type) const { return _outputs.at({name, type}); }
+		IROutput const& output(IdString name) const { return output(name, ID($output)); }
+		IRState const& state(IdString name, IdString type) const { return _states.at({name, type}); }
+		IRState const& state(IdString name) const { return state(name, ID($state)); }
+		bool has_input(IdString name, IdString type) const { return _inputs.count({name, type}); }
+		bool has_output(IdString name, IdString type) const { return _outputs.count({name, type}); }
+		bool has_state(IdString name, IdString type) const { return _states.count({name, type}); }
+		vector<IRInput const*> inputs(IdString type) const;
+		vector<IRInput const*> inputs() const { return inputs(ID($input)); }
+		vector<IROutput const*> outputs(IdString type) const;
+		vector<IROutput const*> outputs() const { return outputs(ID($output)); }
+		vector<IRState const*> states(IdString type) const;
+		vector<IRState const*> states() const { return states(ID($state)); }
+		vector<IRInput const*> all_inputs() const;
+		vector<IROutput const*> all_outputs() const;
+		vector<IRState const*> all_states() const;
 		class iterator {
 			friend class IR;
 			IR *_ir;
@@ -236,6 +295,9 @@ namespace Functional {
 	class Node {
 		friend class Factory;
 		friend class IR;
+		friend class IRInput;
+		friend class IROutput;
+		friend class IRState;
 		IR::Graph::ConstRef _ref;
 		explicit Node(IR::Graph::ConstRef ref) : _ref(ref) { }
 		explicit operator IR::Graph::ConstRef() { return _ref; }
@@ -290,8 +352,8 @@ namespace Functional {
 			case Fn::arithmetic_shift_right: return v.arithmetic_shift_right(*this, arg(0), arg(1)); break;
 			case Fn::mux: return v.mux(*this, arg(0), arg(1), arg(2)); break;
 			case Fn::constant: return v.constant(*this, _ref.function().as_const()); break;
-			case Fn::input: return v.input(*this, _ref.function().as_idstring()); break;
-			case Fn::state: return v.state(*this, _ref.function().as_idstring()); break;
+			case Fn::input: return v.input(*this, _ref.function().as_idstring_pair().first, _ref.function().as_idstring_pair().second); break;
+			case Fn::state: return v.state(*this, _ref.function().as_idstring_pair().first, _ref.function().as_idstring_pair().second); break;
 			case Fn::memory_read: return v.memory_read(*this, arg(0), arg(1)); break;
 			case Fn::memory_write: return v.memory_write(*this, arg(0), arg(1), arg(2)); break;
 			}
@@ -300,9 +362,14 @@ namespace Functional {
 		std::string to_string();
 		std::string to_string(std::function<std::string(Node)>);
 	};
+	inline IR::Graph::Ref IR::mutate(Node n) { return _graph[n._ref.index()]; }
 	inline Node IR::operator[](int i) { return Node(_graph[i]); }
-	inline Node IR::get_output_node(IdString name) { return Node(_graph({name, false})); }
-	inline Node IR::get_state_next_node(IdString name) { return Node(_graph({name, true})); }
+	inline Node IROutput::value() const { return Node(_ir._graph({name, type, false})); }
+	inline bool IROutput::has_value() const { return _ir._graph.has_key({name, type, false}); }
+	inline void IROutput::set_value(Node value) { log_assert(sort == value.sort()); _ir.mutate(value).assign_key({name, type, false}); }
+	inline Node IRState::next_value() const { return Node(_ir._graph({name, type, true})); }
+	inline bool IRState::has_next_value() const { return _ir._graph.has_key({name, type, true}); }
+	inline void IRState::set_next_value(Node value) { log_assert(sort == value.sort()); _ir.mutate(value).assign_key({name, type, true}); }
 	inline Node IR::iterator::operator*() { return Node(_ir->_graph[_index]); }
 	inline arrow_proxy<Node> IR::iterator::operator->() { return arrow_proxy<Node>(**this); }
 	// AbstractVisitor provides an abstract base class for visitors
@@ -336,8 +403,8 @@ namespace Functional {
 		virtual T arithmetic_shift_right(Node self, Node a, Node b) = 0;
 		virtual T mux(Node self, Node a, Node b, Node s) = 0;
 		virtual T constant(Node self, RTLIL::Const const & value) = 0;
-		virtual T input(Node self, IdString name) = 0;
-		virtual T state(Node self, IdString name) = 0;
+		virtual T input(Node self, IdString name, IdString type) = 0;
+		virtual T state(Node self, IdString name, IdString type) = 0;
 		virtual T memory_read(Node self, Node mem, Node addr) = 0;
 		virtual T memory_write(Node self, Node mem, Node addr, Node data) = 0;
 	};
@@ -373,8 +440,8 @@ namespace Functional {
 		T arithmetic_shift_right(Node self, Node, Node) override { return default_handler(self); }
 		T mux(Node self, Node, Node, Node) override { return default_handler(self); }
 		T constant(Node self, RTLIL::Const const &) override { return default_handler(self); }
-		T input(Node self, IdString) override { return default_handler(self); }
-		T state(Node self, IdString) override { return default_handler(self); }
+		T input(Node self, IdString, IdString) override { return default_handler(self); }
+		T state(Node self, IdString, IdString) override { return default_handler(self); }
 		T memory_read(Node self, Node, Node) override { return default_handler(self); }
 		T memory_write(Node self, Node, Node, Node) override { return default_handler(self); }
 	};
@@ -383,7 +450,7 @@ namespace Functional {
 		friend class IR;
 		IR &_ir;
 		explicit Factory(IR &ir) : _ir(ir) {}
-		Node add(IR::NodeData &&fn, Sort &&sort, std::initializer_list<Node> args) {
+		Node add(IR::NodeData &&fn, Sort const &sort, std::initializer_list<Node> args) {
 			log_assert(!sort.is_signal() || sort.width() > 0);
 			log_assert(!sort.is_memory() || (sort.addr_width() > 0 && sort.data_width() > 0));
 			IR::Graph::Ref ref = _ir._graph.add(std::move(fn), {std::move(sort)});
@@ -391,13 +458,11 @@ namespace Functional {
 				ref.append_arg(IR::Graph::ConstRef(arg));
 			return Node(ref);
 		}
-		IR::Graph::Ref mutate(Node n) {
-			return _ir._graph[n._ref.index()];
-		}
 		void check_basic_binary(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && a.sort() == b.sort()); }
 		void check_shift(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && b.sort().is_signal() && b.width() == ceil_log2(a.width())); }
 		void check_unary(Node const &a) { log_assert(a.sort().is_signal()); }
 	public:
+		IR &ir() { return _ir; }
 		Node slice(Node a, int offset, int out_width) {
 			log_assert(a.sort().is_signal() && offset + out_width <= a.sort().width());
 			if(offset == 0 && out_width == a.width())
@@ -480,45 +545,31 @@ namespace Functional {
 		void update_pending(Node node, Node value) {
 			log_assert(node._ref.function() == Fn::buf && node._ref.size() == 0);
 			log_assert(node.sort() == value.sort());
-			mutate(node).append_arg(value._ref);
+			_ir.mutate(node).append_arg(value._ref);
 		}
-		void add_input(IdString name, int width) {
-			auto [it, inserted] = _ir._input_sorts.emplace(name, Sort(width));
+		IRInput &add_input(IdString name, IdString type, Sort sort) {
+			auto [it, inserted] = _ir._inputs.emplace({name, type}, IRInput(_ir, name, type, std::move(sort)));
 			if (!inserted) log_error("input `%s` was re-defined", name.c_str());
+			return it->second;
 		}
-		void add_output(IdString name, int width) {
-			auto [it, inserted] = _ir._output_sorts.emplace(name, Sort(width));
+		IROutput &add_output(IdString name, IdString type, Sort sort) {
+			auto [it, inserted] = _ir._outputs.emplace({name, type}, IROutput(_ir, name, type, std::move(sort)));
 			if (!inserted) log_error("output `%s` was re-defined", name.c_str());
+			return it->second;
 		}
-		void add_state(IdString name, Sort sort) {
-			auto [it, inserted] = _ir._state_sorts.emplace(name, sort);
+		IRState &add_state(IdString name, IdString type, Sort sort) {
+			auto [it, inserted] = _ir._states.emplace({name, type}, IRState(_ir, name, type, std::move(sort)));
 			if (!inserted) log_error("state `%s` was re-defined", name.c_str());
+			return it->second;
 		}
-		Node input(IdString name) {
-			return add(IR::NodeData(Fn::input, name), Sort(_ir._input_sorts.at(name)), {});
-		}
-		Node current_state(IdString name) {
-			return add(IR::NodeData(Fn::state, name), Sort(_ir._state_sorts.at(name)), {});
-		}
-		void set_output(IdString output, Node value) {
-			log_assert(_ir._output_sorts.at(output) == value.sort());
-			mutate(value).assign_key({output, false});
-		}
-		void set_initial_state(IdString state, RTLIL::Const value) {
-			Sort &sort = _ir._state_sorts.at(state);
-			value.extu(sort.width());
-			_ir._initial_state_signal.emplace(state, std::move(value));
-		}
-		void set_initial_state(IdString state, MemContents value) {
-			log_assert(Sort(value.addr_width(), value.data_width()) == _ir._state_sorts.at(state));
-			_ir._initial_state_memory.emplace(state, std::move(value));
+		Node value(IRInput const& input) {
+			return add(IR::NodeData(Fn::input, std::pair(input.name, input.type)), input.sort, {});
 		}
-		void set_next_state(IdString state, Node value) {
-			log_assert(_ir._state_sorts.at(state) == value.sort());
-			mutate(value).assign_key({state, true});
+		Node value(IRState const& state) {
+			return add(IR::NodeData(Fn::state, std::pair(state.name, state.type)), state.sort, {});
 		}
 		void suggest_name(Node node, IdString name) {
-			mutate(node).sparse_attr() = name;
+			_ir.mutate(node).sparse_attr() = name;
 		}
 	};
 	inline Factory IR::factory() { return Factory(*this); }

From 831da512554aa5adc6875b8894be4a413656b2fb Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 8 Aug 2024 15:38:24 +0100
Subject: [PATCH 430/499] add picorv test to functional backend

---
 kernel/functional.cc                |   17 +-
 tests/functional/picorv32.v         | 3044 +++++++++++++++++++++++++++
 tests/functional/picorv32_tb.v      |   62 +
 tests/functional/rtlil_cells.py     |   11 +
 tests/functional/test_functional.py |    3 +
 5 files changed, 3135 insertions(+), 2 deletions(-)
 create mode 100644 tests/functional/picorv32.v
 create mode 100644 tests/functional/picorv32_tb.v

diff --git a/kernel/functional.cc b/kernel/functional.cc
index 202eaa50221..eaae3f09808 100644
--- a/kernel/functional.cc
+++ b/kernel/functional.cc
@@ -530,6 +530,7 @@ class FunctionalIRConstruction {
 				memories[mem.cell] = &mem;
 		}
 	}
+private:
 	Node concatenate_read_results(Mem *mem, vector<Node> results)
 	{
 		// sanity check: all read ports concatenated should equal to the RD_DATA port
@@ -632,6 +633,17 @@ class FunctionalIRConstruction {
 			}
 		}
 	}
+	void undriven(const char *name) {
+		log_error("The design contains an undriven signal %s. This is not supported by the functional backend. "
+			"Call setundef with appropriate options to avoid this error.\n", name);
+	}
+	// we perform this check separately to give better error messages that include the wire or port name
+	void check_undriven(DriveSpec const& spec, std::string const& name) {
+		for(auto const &chunk : spec.chunks())
+			if(chunk.is_none())
+				undriven(name.c_str());
+	}
+public:
 	void process_queue()
 	{
 		for (; !queue.empty(); queue.pop_front()) {
@@ -660,6 +672,7 @@ class FunctionalIRConstruction {
 							factory.update_pending(pending, node);
 						} else {
 							DriveSpec driver = driver_map(DriveSpec(wire_chunk));
+							check_undriven(driver, RTLIL::unescape_id(wire_chunk.wire->name));
 							Node node = enqueue(driver);
 							factory.suggest_name(node, wire_chunk.wire->name);
 							factory.update_pending(pending, node);
@@ -677,6 +690,7 @@ class FunctionalIRConstruction {
 							factory.update_pending(pending, node);
 						} else {
 							DriveSpec driver = driver_map(DriveSpec(port_chunk));
+							check_undriven(driver, RTLIL::unescape_id(port_chunk.cell->name) + " port " + RTLIL::unescape_id(port_chunk.port));
 							factory.update_pending(pending, enqueue(driver));
 						}
 					} else {
@@ -692,8 +706,7 @@ class FunctionalIRConstruction {
 					log_error("Signal %s has multiple drivers. This is not supported by the functional backend. "
 						"If tristate drivers are used, call tristate -formal to avoid this error.\n", log_signal(chunk));
 				} else if (chunk.is_none()) {
-					log_error("The design contains an undriven signal %s. This is not supported by the functional backend. "
-						"Call setundef with appropriate options to avoid this error.\n", log_signal(chunk));
+					undriven(log_signal(chunk));
 				} else {
 					log_error("unhandled drivespec: %s\n", log_signal(chunk));
 					log_abort();
diff --git a/tests/functional/picorv32.v b/tests/functional/picorv32.v
new file mode 100644
index 00000000000..cfc7ce0627a
--- /dev/null
+++ b/tests/functional/picorv32.v
@@ -0,0 +1,3044 @@
+/*
+ *  PicoRV32 -- A Small RISC-V (RV32I) Processor Core
+ *
+ *  Copyright (C) 2015  Claire Xenia Wolf <claire@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+/* verilator lint_off WIDTH */
+/* verilator lint_off PINMISSING */
+/* verilator lint_off CASEOVERLAP */
+/* verilator lint_off CASEINCOMPLETE */
+
+`timescale 1 ns / 1 ps
+// `default_nettype none
+// `define DEBUGNETS
+// `define DEBUGREGS
+// `define DEBUGASM
+// `define DEBUG
+
+`ifdef DEBUG
+  `define debug(debug_command) debug_command
+`else
+  `define debug(debug_command)
+`endif
+
+`ifdef FORMAL
+  `define FORMAL_KEEP (* keep *)
+  `define assert(assert_expr) assert(assert_expr)
+`else
+  `ifdef DEBUGNETS
+    `define FORMAL_KEEP (* keep *)
+  `else
+    `define FORMAL_KEEP
+  `endif
+  `define assert(assert_expr) empty_statement
+`endif
+
+// uncomment this for register file in extra module
+// `define PICORV32_REGS picorv32_regs
+
+// this macro can be used to check if the verilog files in your
+// design are read in the correct order.
+`define PICORV32_V
+
+
+/***************************************************************
+ * picorv32
+ ***************************************************************/
+
+module picorv32 #(
+	parameter [ 0:0] ENABLE_COUNTERS = 1,
+	parameter [ 0:0] ENABLE_COUNTERS64 = 1,
+	parameter [ 0:0] ENABLE_REGS_16_31 = 1,
+	parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
+	parameter [ 0:0] LATCHED_MEM_RDATA = 0,
+	parameter [ 0:0] TWO_STAGE_SHIFT = 1,
+	parameter [ 0:0] BARREL_SHIFTER = 0,
+	parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
+	parameter [ 0:0] TWO_CYCLE_ALU = 0,
+	parameter [ 0:0] COMPRESSED_ISA = 0,
+	parameter [ 0:0] CATCH_MISALIGN = 1,
+	parameter [ 0:0] CATCH_ILLINSN = 1,
+	parameter [ 0:0] ENABLE_PCPI = 0,
+	parameter [ 0:0] ENABLE_MUL = 0,
+	parameter [ 0:0] ENABLE_FAST_MUL = 0,
+	parameter [ 0:0] ENABLE_DIV = 0,
+	parameter [ 0:0] ENABLE_IRQ = 0,
+	parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
+	parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
+	parameter [ 0:0] ENABLE_TRACE = 0,
+	parameter [ 0:0] REGS_INIT_ZERO = 0,
+	parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
+	parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
+	parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
+	parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
+	parameter [31:0] STACKADDR = 32'h ffff_ffff
+) (
+	input clk, resetn,
+	output reg trap,
+
+	output reg        mem_valid,
+	output reg        mem_instr,
+	input             mem_ready,
+
+	output reg [31:0] mem_addr,
+	output reg [31:0] mem_wdata,
+	output reg [ 3:0] mem_wstrb,
+	input      [31:0] mem_rdata,
+
+	// Look-Ahead Interface
+	output            mem_la_read,
+	output            mem_la_write,
+	output     [31:0] mem_la_addr,
+	output reg [31:0] mem_la_wdata,
+	output reg [ 3:0] mem_la_wstrb,
+
+	// Pico Co-Processor Interface (PCPI)
+	output reg        pcpi_valid,
+	output reg [31:0] pcpi_insn,
+	output     [31:0] pcpi_rs1,
+	output     [31:0] pcpi_rs2,
+	input             pcpi_wr,
+	input      [31:0] pcpi_rd,
+	input             pcpi_wait,
+	input             pcpi_ready,
+
+	// IRQ Interface
+	input      [31:0] irq,
+	output reg [31:0] eoi,
+
+`ifdef RISCV_FORMAL
+	output reg        rvfi_valid,
+	output reg [63:0] rvfi_order,
+	output reg [31:0] rvfi_insn,
+	output reg        rvfi_trap,
+	output reg        rvfi_halt,
+	output reg        rvfi_intr,
+	output reg [ 1:0] rvfi_mode,
+	output reg [ 1:0] rvfi_ixl,
+	output reg [ 4:0] rvfi_rs1_addr,
+	output reg [ 4:0] rvfi_rs2_addr,
+	output reg [31:0] rvfi_rs1_rdata,
+	output reg [31:0] rvfi_rs2_rdata,
+	output reg [ 4:0] rvfi_rd_addr,
+	output reg [31:0] rvfi_rd_wdata,
+	output reg [31:0] rvfi_pc_rdata,
+	output reg [31:0] rvfi_pc_wdata,
+	output reg [31:0] rvfi_mem_addr,
+	output reg [ 3:0] rvfi_mem_rmask,
+	output reg [ 3:0] rvfi_mem_wmask,
+	output reg [31:0] rvfi_mem_rdata,
+	output reg [31:0] rvfi_mem_wdata,
+
+	output reg [63:0] rvfi_csr_mcycle_rmask,
+	output reg [63:0] rvfi_csr_mcycle_wmask,
+	output reg [63:0] rvfi_csr_mcycle_rdata,
+	output reg [63:0] rvfi_csr_mcycle_wdata,
+
+	output reg [63:0] rvfi_csr_minstret_rmask,
+	output reg [63:0] rvfi_csr_minstret_wmask,
+	output reg [63:0] rvfi_csr_minstret_rdata,
+	output reg [63:0] rvfi_csr_minstret_wdata,
+`endif
+
+	// Trace Interface
+	output reg        trace_valid,
+	output reg [35:0] trace_data
+);
+	localparam integer irq_timer = 0;
+	localparam integer irq_ebreak = 1;
+	localparam integer irq_buserror = 2;
+
+	localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16;
+	localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS;
+	localparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS;
+
+	localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV;
+
+	localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0};
+	localparam [35:0] TRACE_ADDR   = {4'b 0010, 32'b 0};
+	localparam [35:0] TRACE_IRQ    = {4'b 1000, 32'b 0};
+
+	reg [63:0] count_cycle, count_instr;
+	reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out;
+	reg [4:0] reg_sh;
+
+	reg [31:0] next_insn_opcode;
+	reg [31:0] dbg_insn_opcode;
+	reg [31:0] dbg_insn_addr;
+
+	wire dbg_mem_valid = mem_valid;
+	wire dbg_mem_instr = mem_instr;
+	wire dbg_mem_ready = mem_ready;
+	wire [31:0] dbg_mem_addr  = mem_addr;
+	wire [31:0] dbg_mem_wdata = mem_wdata;
+	wire [ 3:0] dbg_mem_wstrb = mem_wstrb;
+	wire [31:0] dbg_mem_rdata = mem_rdata;
+
+	assign pcpi_rs1 = reg_op1;
+	assign pcpi_rs2 = reg_op2;
+
+	wire [31:0] next_pc;
+
+	reg irq_delay;
+	reg irq_active;
+	reg [31:0] irq_mask;
+	reg [31:0] irq_pending;
+	reg [31:0] timer;
+
+`ifndef PICORV32_REGS
+	reg [31:0] cpuregs [0:regfile_size-1];
+
+	integer i;
+	initial begin
+		if (REGS_INIT_ZERO) begin
+			for (i = 0; i < regfile_size; i = i+1)
+				cpuregs[i] = 0;
+		end
+	end
+`endif
+
+	task empty_statement;
+		// This task is used by the `assert directive in non-formal mode to
+		// avoid empty statement (which are unsupported by plain Verilog syntax).
+		begin end
+	endtask
+
+`ifdef DEBUGREGS
+	wire [31:0] dbg_reg_x0  = 0;
+	wire [31:0] dbg_reg_x1  = cpuregs[1];
+	wire [31:0] dbg_reg_x2  = cpuregs[2];
+	wire [31:0] dbg_reg_x3  = cpuregs[3];
+	wire [31:0] dbg_reg_x4  = cpuregs[4];
+	wire [31:0] dbg_reg_x5  = cpuregs[5];
+	wire [31:0] dbg_reg_x6  = cpuregs[6];
+	wire [31:0] dbg_reg_x7  = cpuregs[7];
+	wire [31:0] dbg_reg_x8  = cpuregs[8];
+	wire [31:0] dbg_reg_x9  = cpuregs[9];
+	wire [31:0] dbg_reg_x10 = cpuregs[10];
+	wire [31:0] dbg_reg_x11 = cpuregs[11];
+	wire [31:0] dbg_reg_x12 = cpuregs[12];
+	wire [31:0] dbg_reg_x13 = cpuregs[13];
+	wire [31:0] dbg_reg_x14 = cpuregs[14];
+	wire [31:0] dbg_reg_x15 = cpuregs[15];
+	wire [31:0] dbg_reg_x16 = cpuregs[16];
+	wire [31:0] dbg_reg_x17 = cpuregs[17];
+	wire [31:0] dbg_reg_x18 = cpuregs[18];
+	wire [31:0] dbg_reg_x19 = cpuregs[19];
+	wire [31:0] dbg_reg_x20 = cpuregs[20];
+	wire [31:0] dbg_reg_x21 = cpuregs[21];
+	wire [31:0] dbg_reg_x22 = cpuregs[22];
+	wire [31:0] dbg_reg_x23 = cpuregs[23];
+	wire [31:0] dbg_reg_x24 = cpuregs[24];
+	wire [31:0] dbg_reg_x25 = cpuregs[25];
+	wire [31:0] dbg_reg_x26 = cpuregs[26];
+	wire [31:0] dbg_reg_x27 = cpuregs[27];
+	wire [31:0] dbg_reg_x28 = cpuregs[28];
+	wire [31:0] dbg_reg_x29 = cpuregs[29];
+	wire [31:0] dbg_reg_x30 = cpuregs[30];
+	wire [31:0] dbg_reg_x31 = cpuregs[31];
+`endif
+
+	// Internal PCPI Cores
+
+	wire        pcpi_mul_wr;
+	wire [31:0] pcpi_mul_rd;
+	wire        pcpi_mul_wait;
+	wire        pcpi_mul_ready;
+
+	wire        pcpi_div_wr;
+	wire [31:0] pcpi_div_rd;
+	wire        pcpi_div_wait;
+	wire        pcpi_div_ready;
+
+	reg        pcpi_int_wr;
+	reg [31:0] pcpi_int_rd;
+	reg        pcpi_int_wait;
+	reg        pcpi_int_ready;
+
+	generate if (ENABLE_FAST_MUL) begin
+		picorv32_pcpi_fast_mul pcpi_mul (
+			.clk       (clk            ),
+			.resetn    (resetn         ),
+			.pcpi_valid(pcpi_valid     ),
+			.pcpi_insn (pcpi_insn      ),
+			.pcpi_rs1  (pcpi_rs1       ),
+			.pcpi_rs2  (pcpi_rs2       ),
+			.pcpi_wr   (pcpi_mul_wr    ),
+			.pcpi_rd   (pcpi_mul_rd    ),
+			.pcpi_wait (pcpi_mul_wait  ),
+			.pcpi_ready(pcpi_mul_ready )
+		);
+	end else if (ENABLE_MUL) begin
+		picorv32_pcpi_mul pcpi_mul (
+			.clk       (clk            ),
+			.resetn    (resetn         ),
+			.pcpi_valid(pcpi_valid     ),
+			.pcpi_insn (pcpi_insn      ),
+			.pcpi_rs1  (pcpi_rs1       ),
+			.pcpi_rs2  (pcpi_rs2       ),
+			.pcpi_wr   (pcpi_mul_wr    ),
+			.pcpi_rd   (pcpi_mul_rd    ),
+			.pcpi_wait (pcpi_mul_wait  ),
+			.pcpi_ready(pcpi_mul_ready )
+		);
+	end else begin
+		assign pcpi_mul_wr = 0;
+		assign pcpi_mul_rd = 32'bx;
+		assign pcpi_mul_wait = 0;
+		assign pcpi_mul_ready = 0;
+	end endgenerate
+
+	generate if (ENABLE_DIV) begin
+		picorv32_pcpi_div pcpi_div (
+			.clk       (clk            ),
+			.resetn    (resetn         ),
+			.pcpi_valid(pcpi_valid     ),
+			.pcpi_insn (pcpi_insn      ),
+			.pcpi_rs1  (pcpi_rs1       ),
+			.pcpi_rs2  (pcpi_rs2       ),
+			.pcpi_wr   (pcpi_div_wr    ),
+			.pcpi_rd   (pcpi_div_rd    ),
+			.pcpi_wait (pcpi_div_wait  ),
+			.pcpi_ready(pcpi_div_ready )
+		);
+	end else begin
+		assign pcpi_div_wr = 0;
+		assign pcpi_div_rd = 32'bx;
+		assign pcpi_div_wait = 0;
+		assign pcpi_div_ready = 0;
+	end endgenerate
+
+	always @* begin
+		pcpi_int_wr = 0;
+		pcpi_int_rd = 32'bx;
+		pcpi_int_wait  = |{ENABLE_PCPI && pcpi_wait,  (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait,  ENABLE_DIV && pcpi_div_wait};
+		pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready};
+
+		(* parallel_case *)
+		case (1'b1)
+			ENABLE_PCPI && pcpi_ready: begin
+				pcpi_int_wr = ENABLE_PCPI ? pcpi_wr : 0;
+				pcpi_int_rd = ENABLE_PCPI ? pcpi_rd : 0;
+			end
+			(ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin
+				pcpi_int_wr = pcpi_mul_wr;
+				pcpi_int_rd = pcpi_mul_rd;
+			end
+			ENABLE_DIV && pcpi_div_ready: begin
+				pcpi_int_wr = pcpi_div_wr;
+				pcpi_int_rd = pcpi_div_rd;
+			end
+		endcase
+	end
+
+
+	// Memory Interface
+
+	reg [1:0] mem_state;
+	reg [1:0] mem_wordsize;
+	reg [31:0] mem_rdata_word;
+	reg [31:0] mem_rdata_q;
+	reg mem_do_prefetch;
+	reg mem_do_rinst;
+	reg mem_do_rdata;
+	reg mem_do_wdata;
+
+	wire mem_xfer;
+	reg mem_la_secondword, mem_la_firstword_reg, last_mem_valid;
+	wire mem_la_firstword = COMPRESSED_ISA && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword;
+	wire mem_la_firstword_xfer = COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg);
+
+	reg prefetched_high_word;
+	reg clear_prefetched_high_word;
+	reg [15:0] mem_16bit_buffer;
+
+	wire [31:0] mem_rdata_latched_noshuffle;
+	wire [31:0] mem_rdata_latched;
+
+	wire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word;
+	assign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst);
+
+	wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
+	wire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) &&
+			(!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer));
+
+	assign mem_la_write = resetn && !mem_state && mem_do_wdata;
+	assign mem_la_read = resetn && ((!mem_la_use_prefetched_high_word && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) ||
+			(COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg) && !mem_la_secondword && &mem_rdata_latched[1:0]));
+	assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2'b00} : {reg_op1[31:2], 2'b00};
+
+	assign mem_rdata_latched_noshuffle = (mem_xfer || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q;
+
+	assign mem_rdata_latched = COMPRESSED_ISA && mem_la_use_prefetched_high_word ? {16'bx, mem_16bit_buffer} :
+			COMPRESSED_ISA && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} :
+			COMPRESSED_ISA && mem_la_firstword ? {16'bx, mem_rdata_latched_noshuffle[31:16]} : mem_rdata_latched_noshuffle;
+
+	always @(posedge clk) begin
+		if (!resetn) begin
+			mem_la_firstword_reg <= 0;
+			last_mem_valid <= 0;
+		end else begin
+			if (!last_mem_valid)
+				mem_la_firstword_reg <= mem_la_firstword;
+			last_mem_valid <= mem_valid && !mem_ready;
+		end
+	end
+
+	always @* begin
+		(* full_case *)
+		case (mem_wordsize)
+			0: begin
+				mem_la_wdata = reg_op2;
+				mem_la_wstrb = 4'b1111;
+				mem_rdata_word = mem_rdata;
+			end
+			1: begin
+				mem_la_wdata = {2{reg_op2[15:0]}};
+				mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011;
+				case (reg_op1[1])
+					1'b0: mem_rdata_word = {16'b0, mem_rdata[15: 0]};
+					1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]};
+				endcase
+			end
+			2: begin
+				mem_la_wdata = {4{reg_op2[7:0]}};
+				mem_la_wstrb = 4'b0001 << reg_op1[1:0];
+				case (reg_op1[1:0])
+					2'b00: mem_rdata_word = {24'b0, mem_rdata[ 7: 0]};
+					2'b01: mem_rdata_word = {24'b0, mem_rdata[15: 8]};
+					2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]};
+					2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]};
+				endcase
+			end
+		endcase
+	end
+
+	always @(posedge clk) begin
+		if (mem_xfer) begin
+			mem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
+			next_insn_opcode <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
+		end
+
+		if (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin
+			case (mem_rdata_latched[1:0])
+				2'b00: begin // Quadrant 0
+					case (mem_rdata_latched[15:13])
+						3'b000: begin // C.ADDI4SPN
+							mem_rdata_q[14:12] <= 3'b000;
+							mem_rdata_q[31:20] <= {2'b0, mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6], 2'b00};
+						end
+						3'b010: begin // C.LW
+							mem_rdata_q[31:20] <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
+							mem_rdata_q[14:12] <= 3'b 010;
+						end
+						3'b 110: begin // C.SW
+							{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
+							mem_rdata_q[14:12] <= 3'b 010;
+						end
+					endcase
+				end
+				2'b01: begin // Quadrant 1
+					case (mem_rdata_latched[15:13])
+						3'b 000: begin // C.ADDI
+							mem_rdata_q[14:12] <= 3'b000;
+							mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
+						end
+						3'b 010: begin // C.LI
+							mem_rdata_q[14:12] <= 3'b000;
+							mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
+						end
+						3'b 011: begin
+							if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
+								mem_rdata_q[14:12] <= 3'b000;
+								mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3],
+										mem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4'b 0000});
+							end else begin // C.LUI
+								mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
+							end
+						end
+						3'b100: begin
+							if (mem_rdata_latched[11:10] == 2'b00) begin // C.SRLI
+								mem_rdata_q[31:25] <= 7'b0000000;
+								mem_rdata_q[14:12] <= 3'b 101;
+							end
+							if (mem_rdata_latched[11:10] == 2'b01) begin // C.SRAI
+								mem_rdata_q[31:25] <= 7'b0100000;
+								mem_rdata_q[14:12] <= 3'b 101;
+							end
+							if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
+								mem_rdata_q[14:12] <= 3'b111;
+								mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
+							end
+							if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
+								if (mem_rdata_latched[6:5] == 2'b00) mem_rdata_q[14:12] <= 3'b000;
+								if (mem_rdata_latched[6:5] == 2'b01) mem_rdata_q[14:12] <= 3'b100;
+								if (mem_rdata_latched[6:5] == 2'b10) mem_rdata_q[14:12] <= 3'b110;
+								if (mem_rdata_latched[6:5] == 2'b11) mem_rdata_q[14:12] <= 3'b111;
+								mem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2'b00 ? 7'b0100000 : 7'b0000000;
+							end
+						end
+						3'b 110: begin // C.BEQZ
+							mem_rdata_q[14:12] <= 3'b000;
+							{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
+									$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
+											mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
+						end
+						3'b 111: begin // C.BNEZ
+							mem_rdata_q[14:12] <= 3'b001;
+							{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
+									$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
+											mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
+						end
+					endcase
+				end
+				2'b10: begin // Quadrant 2
+					case (mem_rdata_latched[15:13])
+						3'b000: begin // C.SLLI
+							mem_rdata_q[31:25] <= 7'b0000000;
+							mem_rdata_q[14:12] <= 3'b 001;
+						end
+						3'b010: begin // C.LWSP
+							mem_rdata_q[31:20] <= {4'b0, mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2'b00};
+							mem_rdata_q[14:12] <= 3'b 010;
+						end
+						3'b100: begin
+							if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
+								mem_rdata_q[14:12] <= 3'b000;
+								mem_rdata_q[31:20] <= 12'b0;
+							end
+							if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
+								mem_rdata_q[14:12] <= 3'b000;
+								mem_rdata_q[31:25] <= 7'b0000000;
+							end
+							if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
+								mem_rdata_q[14:12] <= 3'b000;
+								mem_rdata_q[31:20] <= 12'b0;
+							end
+							if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
+								mem_rdata_q[14:12] <= 3'b000;
+								mem_rdata_q[31:25] <= 7'b0000000;
+							end
+						end
+						3'b110: begin // C.SWSP
+							{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00};
+							mem_rdata_q[14:12] <= 3'b 010;
+						end
+					endcase
+				end
+			endcase
+		end
+	end
+
+	always @(posedge clk) begin
+		if (resetn && !trap) begin
+			if (mem_do_prefetch || mem_do_rinst || mem_do_rdata)
+				`assert(!mem_do_wdata);
+
+			if (mem_do_prefetch || mem_do_rinst)
+				`assert(!mem_do_rdata);
+
+			if (mem_do_rdata)
+				`assert(!mem_do_prefetch && !mem_do_rinst);
+
+			if (mem_do_wdata)
+				`assert(!(mem_do_prefetch || mem_do_rinst || mem_do_rdata));
+
+			if (mem_state == 2 || mem_state == 3)
+				`assert(mem_valid || mem_do_prefetch);
+		end
+	end
+
+	always @(posedge clk) begin
+		if (!resetn || trap) begin
+			if (!resetn)
+				mem_state <= 0;
+			if (!resetn || mem_ready)
+				mem_valid <= 0;
+			mem_la_secondword <= 0;
+			prefetched_high_word <= 0;
+		end else begin
+			if (mem_la_read || mem_la_write) begin
+				mem_addr <= mem_la_addr;
+				mem_wstrb <= mem_la_wstrb & {4{mem_la_write}};
+			end
+			if (mem_la_write) begin
+				mem_wdata <= mem_la_wdata;
+			end
+			case (mem_state)
+				0: begin
+					if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin
+						mem_valid <= !mem_la_use_prefetched_high_word;
+						mem_instr <= mem_do_prefetch || mem_do_rinst;
+						mem_wstrb <= 0;
+						mem_state <= 1;
+					end
+					if (mem_do_wdata) begin
+						mem_valid <= 1;
+						mem_instr <= 0;
+						mem_state <= 2;
+					end
+				end
+				1: begin
+					`assert(mem_wstrb == 0);
+					`assert(mem_do_prefetch || mem_do_rinst || mem_do_rdata);
+					`assert(mem_valid == !mem_la_use_prefetched_high_word);
+					`assert(mem_instr == (mem_do_prefetch || mem_do_rinst));
+					if (mem_xfer) begin
+						if (COMPRESSED_ISA && mem_la_read) begin
+							mem_valid <= 1;
+							mem_la_secondword <= 1;
+							if (!mem_la_use_prefetched_high_word)
+								mem_16bit_buffer <= mem_rdata[31:16];
+						end else begin
+							mem_valid <= 0;
+							mem_la_secondword <= 0;
+							if (COMPRESSED_ISA && !mem_do_rdata) begin
+								if (~&mem_rdata[1:0] || mem_la_secondword) begin
+									mem_16bit_buffer <= mem_rdata[31:16];
+									prefetched_high_word <= 1;
+								end else begin
+									prefetched_high_word <= 0;
+								end
+							end
+							mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3;
+						end
+					end
+				end
+				2: begin
+					`assert(mem_wstrb != 0);
+					`assert(mem_do_wdata);
+					if (mem_xfer) begin
+						mem_valid <= 0;
+						mem_state <= 0;
+					end
+				end
+				3: begin
+					`assert(mem_wstrb == 0);
+					`assert(mem_do_prefetch);
+					if (mem_do_rinst) begin
+						mem_state <= 0;
+					end
+				end
+			endcase
+		end
+
+		if (clear_prefetched_high_word)
+			prefetched_high_word <= 0;
+	end
+
+
+	// Instruction Decoder
+
+	reg instr_lui, instr_auipc, instr_jal, instr_jalr;
+	reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;
+	reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
+	reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
+	reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
+	reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak;
+	reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
+	wire instr_trap;
+
+	reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
+	reg [31:0] decoded_imm, decoded_imm_j;
+	reg decoder_trigger;
+	reg decoder_trigger_q;
+	reg decoder_pseudo_trigger;
+	reg decoder_pseudo_trigger_q;
+	reg compressed_instr;
+
+	reg is_lui_auipc_jal;
+	reg is_lb_lh_lw_lbu_lhu;
+	reg is_slli_srli_srai;
+	reg is_jalr_addi_slti_sltiu_xori_ori_andi;
+	reg is_sb_sh_sw;
+	reg is_sll_srl_sra;
+	reg is_lui_auipc_jal_jalr_addi_add_sub;
+	reg is_slti_blt_slt;
+	reg is_sltiu_bltu_sltu;
+	reg is_beq_bne_blt_bge_bltu_bgeu;
+	reg is_lbu_lhu_lw;
+	reg is_alu_reg_imm;
+	reg is_alu_reg_reg;
+	reg is_compare;
+
+	assign instr_trap = (CATCH_ILLINSN || WITH_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr,
+			instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu,
+			instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw,
+			instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai,
+			instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and,
+			instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh,
+			instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer};
+
+	wire is_rdcycle_rdcycleh_rdinstr_rdinstrh;
+	assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
+
+	reg [63:0] new_ascii_instr;
+	`FORMAL_KEEP reg [63:0] dbg_ascii_instr;
+	`FORMAL_KEEP reg [31:0] dbg_insn_imm;
+	`FORMAL_KEEP reg [4:0] dbg_insn_rs1;
+	`FORMAL_KEEP reg [4:0] dbg_insn_rs2;
+	`FORMAL_KEEP reg [4:0] dbg_insn_rd;
+	`FORMAL_KEEP reg [31:0] dbg_rs1val;
+	`FORMAL_KEEP reg [31:0] dbg_rs2val;
+	`FORMAL_KEEP reg dbg_rs1val_valid;
+	`FORMAL_KEEP reg dbg_rs2val_valid;
+
+	always @* begin
+		new_ascii_instr = "";
+
+		if (instr_lui)      new_ascii_instr = "lui";
+		if (instr_auipc)    new_ascii_instr = "auipc";
+		if (instr_jal)      new_ascii_instr = "jal";
+		if (instr_jalr)     new_ascii_instr = "jalr";
+
+		if (instr_beq)      new_ascii_instr = "beq";
+		if (instr_bne)      new_ascii_instr = "bne";
+		if (instr_blt)      new_ascii_instr = "blt";
+		if (instr_bge)      new_ascii_instr = "bge";
+		if (instr_bltu)     new_ascii_instr = "bltu";
+		if (instr_bgeu)     new_ascii_instr = "bgeu";
+
+		if (instr_lb)       new_ascii_instr = "lb";
+		if (instr_lh)       new_ascii_instr = "lh";
+		if (instr_lw)       new_ascii_instr = "lw";
+		if (instr_lbu)      new_ascii_instr = "lbu";
+		if (instr_lhu)      new_ascii_instr = "lhu";
+		if (instr_sb)       new_ascii_instr = "sb";
+		if (instr_sh)       new_ascii_instr = "sh";
+		if (instr_sw)       new_ascii_instr = "sw";
+
+		if (instr_addi)     new_ascii_instr = "addi";
+		if (instr_slti)     new_ascii_instr = "slti";
+		if (instr_sltiu)    new_ascii_instr = "sltiu";
+		if (instr_xori)     new_ascii_instr = "xori";
+		if (instr_ori)      new_ascii_instr = "ori";
+		if (instr_andi)     new_ascii_instr = "andi";
+		if (instr_slli)     new_ascii_instr = "slli";
+		if (instr_srli)     new_ascii_instr = "srli";
+		if (instr_srai)     new_ascii_instr = "srai";
+
+		if (instr_add)      new_ascii_instr = "add";
+		if (instr_sub)      new_ascii_instr = "sub";
+		if (instr_sll)      new_ascii_instr = "sll";
+		if (instr_slt)      new_ascii_instr = "slt";
+		if (instr_sltu)     new_ascii_instr = "sltu";
+		if (instr_xor)      new_ascii_instr = "xor";
+		if (instr_srl)      new_ascii_instr = "srl";
+		if (instr_sra)      new_ascii_instr = "sra";
+		if (instr_or)       new_ascii_instr = "or";
+		if (instr_and)      new_ascii_instr = "and";
+
+		if (instr_rdcycle)  new_ascii_instr = "rdcycle";
+		if (instr_rdcycleh) new_ascii_instr = "rdcycleh";
+		if (instr_rdinstr)  new_ascii_instr = "rdinstr";
+		if (instr_rdinstrh) new_ascii_instr = "rdinstrh";
+
+		if (instr_getq)     new_ascii_instr = "getq";
+		if (instr_setq)     new_ascii_instr = "setq";
+		if (instr_retirq)   new_ascii_instr = "retirq";
+		if (instr_maskirq)  new_ascii_instr = "maskirq";
+		if (instr_waitirq)  new_ascii_instr = "waitirq";
+		if (instr_timer)    new_ascii_instr = "timer";
+	end
+
+	reg [63:0] q_ascii_instr;
+	reg [31:0] q_insn_imm;
+	reg [31:0] q_insn_opcode;
+	reg [4:0] q_insn_rs1;
+	reg [4:0] q_insn_rs2;
+	reg [4:0] q_insn_rd;
+	reg dbg_next;
+
+	wire launch_next_insn;
+	reg dbg_valid_insn;
+
+	reg [63:0] cached_ascii_instr;
+	reg [31:0] cached_insn_imm;
+	reg [31:0] cached_insn_opcode;
+	reg [4:0] cached_insn_rs1;
+	reg [4:0] cached_insn_rs2;
+	reg [4:0] cached_insn_rd;
+
+	always @(posedge clk) begin
+		q_ascii_instr <= dbg_ascii_instr;
+		q_insn_imm <= dbg_insn_imm;
+		q_insn_opcode <= dbg_insn_opcode;
+		q_insn_rs1 <= dbg_insn_rs1;
+		q_insn_rs2 <= dbg_insn_rs2;
+		q_insn_rd <= dbg_insn_rd;
+		dbg_next <= launch_next_insn;
+
+		if (!resetn || trap)
+			dbg_valid_insn <= 0;
+		else if (launch_next_insn)
+			dbg_valid_insn <= 1;
+
+		if (decoder_trigger_q) begin
+			cached_ascii_instr <= new_ascii_instr;
+			cached_insn_imm <= decoded_imm;
+			if (&next_insn_opcode[1:0])
+				cached_insn_opcode <= next_insn_opcode;
+			else
+				cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]};
+			cached_insn_rs1 <= decoded_rs1;
+			cached_insn_rs2 <= decoded_rs2;
+			cached_insn_rd <= decoded_rd;
+		end
+
+		if (launch_next_insn) begin
+			dbg_insn_addr <= next_pc;
+		end
+	end
+
+	always @* begin
+		dbg_ascii_instr = q_ascii_instr;
+		dbg_insn_imm = q_insn_imm;
+		dbg_insn_opcode = q_insn_opcode;
+		dbg_insn_rs1 = q_insn_rs1;
+		dbg_insn_rs2 = q_insn_rs2;
+		dbg_insn_rd = q_insn_rd;
+
+		if (dbg_next) begin
+			if (decoder_pseudo_trigger_q) begin
+				dbg_ascii_instr = cached_ascii_instr;
+				dbg_insn_imm = cached_insn_imm;
+				dbg_insn_opcode = cached_insn_opcode;
+				dbg_insn_rs1 = cached_insn_rs1;
+				dbg_insn_rs2 = cached_insn_rs2;
+				dbg_insn_rd = cached_insn_rd;
+			end else begin
+				dbg_ascii_instr = new_ascii_instr;
+				if (&next_insn_opcode[1:0])
+					dbg_insn_opcode = next_insn_opcode;
+				else
+					dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]};
+				dbg_insn_imm = decoded_imm;
+				dbg_insn_rs1 = decoded_rs1;
+				dbg_insn_rs2 = decoded_rs2;
+				dbg_insn_rd = decoded_rd;
+			end
+		end
+	end
+
+`ifdef DEBUGASM
+	always @(posedge clk) begin
+		if (dbg_next) begin
+			$display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*");
+		end
+	end
+`endif
+
+`ifdef DEBUG
+	always @(posedge clk) begin
+		if (dbg_next) begin
+			if (&dbg_insn_opcode[1:0])
+				$display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
+			else
+				$display("DECODE: 0x%08x     0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
+		end
+	end
+`endif
+
+	always @(posedge clk) begin
+		is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
+		is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub};
+		is_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt};
+		is_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu};
+		is_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw};
+		is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu};
+
+		if (mem_do_rinst && mem_done) begin
+			instr_lui     <= mem_rdata_latched[6:0] == 7'b0110111;
+			instr_auipc   <= mem_rdata_latched[6:0] == 7'b0010111;
+			instr_jal     <= mem_rdata_latched[6:0] == 7'b1101111;
+			instr_jalr    <= mem_rdata_latched[6:0] == 7'b1100111 && mem_rdata_latched[14:12] == 3'b000;
+			instr_retirq  <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ;
+			instr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && ENABLE_IRQ;
+
+			is_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7'b1100011;
+			is_lb_lh_lw_lbu_lhu          <= mem_rdata_latched[6:0] == 7'b0000011;
+			is_sb_sh_sw                  <= mem_rdata_latched[6:0] == 7'b0100011;
+			is_alu_reg_imm               <= mem_rdata_latched[6:0] == 7'b0010011;
+			is_alu_reg_reg               <= mem_rdata_latched[6:0] == 7'b0110011;
+
+			{ decoded_imm_j[31:20], decoded_imm_j[10:1], decoded_imm_j[11], decoded_imm_j[19:12], decoded_imm_j[0] } <= $signed({mem_rdata_latched[31:12], 1'b0});
+
+			decoded_rd <= mem_rdata_latched[11:7];
+			decoded_rs1 <= mem_rdata_latched[19:15];
+			decoded_rs2 <= mem_rdata_latched[24:20];
+
+			if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS)
+				decoded_rs1[regindex_bits-1] <= 1; // instr_getq
+
+			if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ)
+				decoded_rs1 <= ENABLE_IRQ_QREGS ? irqregs_offset : 3; // instr_retirq
+
+			compressed_instr <= 0;
+			if (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2'b11) begin
+				compressed_instr <= 1;
+				decoded_rd <= 0;
+				decoded_rs1 <= 0;
+				decoded_rs2 <= 0;
+
+				{ decoded_imm_j[31:11], decoded_imm_j[4], decoded_imm_j[9:8], decoded_imm_j[10], decoded_imm_j[6],
+				  decoded_imm_j[7], decoded_imm_j[3:1], decoded_imm_j[5], decoded_imm_j[0] } <= $signed({mem_rdata_latched[12:2], 1'b0});
+
+				case (mem_rdata_latched[1:0])
+					2'b00: begin // Quadrant 0
+						case (mem_rdata_latched[15:13])
+							3'b000: begin // C.ADDI4SPN
+								is_alu_reg_imm <= |mem_rdata_latched[12:5];
+								decoded_rs1 <= 2;
+								decoded_rd <= 8 + mem_rdata_latched[4:2];
+							end
+							3'b010: begin // C.LW
+								is_lb_lh_lw_lbu_lhu <= 1;
+								decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+								decoded_rd <= 8 + mem_rdata_latched[4:2];
+							end
+							3'b110: begin // C.SW
+								is_sb_sh_sw <= 1;
+								decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+								decoded_rs2 <= 8 + mem_rdata_latched[4:2];
+							end
+						endcase
+					end
+					2'b01: begin // Quadrant 1
+						case (mem_rdata_latched[15:13])
+							3'b000: begin // C.NOP / C.ADDI
+								is_alu_reg_imm <= 1;
+								decoded_rd <= mem_rdata_latched[11:7];
+								decoded_rs1 <= mem_rdata_latched[11:7];
+							end
+							3'b001: begin // C.JAL
+								instr_jal <= 1;
+								decoded_rd <= 1;
+							end
+							3'b 010: begin // C.LI
+								is_alu_reg_imm <= 1;
+								decoded_rd <= mem_rdata_latched[11:7];
+								decoded_rs1 <= 0;
+							end
+							3'b 011: begin
+								if (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin
+									if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
+										is_alu_reg_imm <= 1;
+										decoded_rd <= mem_rdata_latched[11:7];
+										decoded_rs1 <= mem_rdata_latched[11:7];
+									end else begin // C.LUI
+										instr_lui <= 1;
+										decoded_rd <= mem_rdata_latched[11:7];
+										decoded_rs1 <= 0;
+									end
+								end
+							end
+							3'b100: begin
+								if (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // C.SRLI, C.SRAI
+									is_alu_reg_imm <= 1;
+									decoded_rd <= 8 + mem_rdata_latched[9:7];
+									decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+									decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
+								end
+								if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
+									is_alu_reg_imm <= 1;
+									decoded_rd <= 8 + mem_rdata_latched[9:7];
+									decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+								end
+								if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
+									is_alu_reg_reg <= 1;
+									decoded_rd <= 8 + mem_rdata_latched[9:7];
+									decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+									decoded_rs2 <= 8 + mem_rdata_latched[4:2];
+								end
+							end
+							3'b101: begin // C.J
+								instr_jal <= 1;
+							end
+							3'b110: begin // C.BEQZ
+								is_beq_bne_blt_bge_bltu_bgeu <= 1;
+								decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+								decoded_rs2 <= 0;
+							end
+							3'b111: begin // C.BNEZ
+								is_beq_bne_blt_bge_bltu_bgeu <= 1;
+								decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+								decoded_rs2 <= 0;
+							end
+						endcase
+					end
+					2'b10: begin // Quadrant 2
+						case (mem_rdata_latched[15:13])
+							3'b000: begin // C.SLLI
+								if (!mem_rdata_latched[12]) begin
+									is_alu_reg_imm <= 1;
+									decoded_rd <= mem_rdata_latched[11:7];
+									decoded_rs1 <= mem_rdata_latched[11:7];
+									decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
+								end
+							end
+							3'b010: begin // C.LWSP
+								if (mem_rdata_latched[11:7]) begin
+									is_lb_lh_lw_lbu_lhu <= 1;
+									decoded_rd <= mem_rdata_latched[11:7];
+									decoded_rs1 <= 2;
+								end
+							end
+							3'b100: begin
+								if (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
+									instr_jalr <= 1;
+									decoded_rd <= 0;
+									decoded_rs1 <= mem_rdata_latched[11:7];
+								end
+								if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
+									is_alu_reg_reg <= 1;
+									decoded_rd <= mem_rdata_latched[11:7];
+									decoded_rs1 <= 0;
+									decoded_rs2 <= mem_rdata_latched[6:2];
+								end
+								if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
+									instr_jalr <= 1;
+									decoded_rd <= 1;
+									decoded_rs1 <= mem_rdata_latched[11:7];
+								end
+								if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
+									is_alu_reg_reg <= 1;
+									decoded_rd <= mem_rdata_latched[11:7];
+									decoded_rs1 <= mem_rdata_latched[11:7];
+									decoded_rs2 <= mem_rdata_latched[6:2];
+								end
+							end
+							3'b110: begin // C.SWSP
+								is_sb_sh_sw <= 1;
+								decoded_rs1 <= 2;
+								decoded_rs2 <= mem_rdata_latched[6:2];
+							end
+						endcase
+					end
+				endcase
+			end
+		end
+
+		if (decoder_trigger && !decoder_pseudo_trigger) begin
+			pcpi_insn <= WITH_PCPI ? mem_rdata_q : 'bx;
+
+			instr_beq   <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000;
+			instr_bne   <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001;
+			instr_blt   <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b100;
+			instr_bge   <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b101;
+			instr_bltu  <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b110;
+			instr_bgeu  <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b111;
+
+			instr_lb    <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b000;
+			instr_lh    <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b001;
+			instr_lw    <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b010;
+			instr_lbu   <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b100;
+			instr_lhu   <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b101;
+
+			instr_sb    <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b000;
+			instr_sh    <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b001;
+			instr_sw    <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b010;
+
+			instr_addi  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b000;
+			instr_slti  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b010;
+			instr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b011;
+			instr_xori  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b100;
+			instr_ori   <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b110;
+			instr_andi  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b111;
+
+			instr_slli  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_srli  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_srai  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
+
+			instr_add   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_sub   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0100000;
+			instr_sll   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_slt   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b010 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_sltu  <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b011 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_xor   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b100 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_srl   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_sra   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
+			instr_or    <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b110 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_and   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b111 && mem_rdata_q[31:25] == 7'b0000000;
+
+			instr_rdcycle  <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000000000010) ||
+			                   (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS;
+			instr_rdcycleh <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000000000010) ||
+			                   (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
+			instr_rdinstr  <=  (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS;
+			instr_rdinstrh <=  (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
+
+			instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) ||
+					(COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002));
+
+			instr_getq    <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
+			instr_setq    <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
+			instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ;
+			instr_timer   <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER;
+
+			is_slli_srli_srai <= is_alu_reg_imm && |{
+				mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
+				mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
+				mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
+			};
+
+			is_jalr_addi_slti_sltiu_xori_ori_andi <= instr_jalr || is_alu_reg_imm && |{
+				mem_rdata_q[14:12] == 3'b000,
+				mem_rdata_q[14:12] == 3'b010,
+				mem_rdata_q[14:12] == 3'b011,
+				mem_rdata_q[14:12] == 3'b100,
+				mem_rdata_q[14:12] == 3'b110,
+				mem_rdata_q[14:12] == 3'b111
+			};
+
+			is_sll_srl_sra <= is_alu_reg_reg && |{
+				mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
+				mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
+				mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
+			};
+
+			is_lui_auipc_jal_jalr_addi_add_sub <= 0;
+			is_compare <= 0;
+
+			(* parallel_case *)
+			case (1'b1)
+				instr_jal:
+					decoded_imm <= decoded_imm_j;
+				|{instr_lui, instr_auipc}:
+					decoded_imm <= mem_rdata_q[31:12] << 12;
+				|{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}:
+					decoded_imm <= $signed(mem_rdata_q[31:20]);
+				is_beq_bne_blt_bge_bltu_bgeu:
+					decoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0});
+				is_sb_sh_sw:
+					decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]});
+				default:
+					decoded_imm <= 1'bx;
+			endcase
+		end
+
+		if (!resetn) begin
+			is_beq_bne_blt_bge_bltu_bgeu <= 0;
+			is_compare <= 0;
+
+			instr_beq   <= 0;
+			instr_bne   <= 0;
+			instr_blt   <= 0;
+			instr_bge   <= 0;
+			instr_bltu  <= 0;
+			instr_bgeu  <= 0;
+
+			instr_addi  <= 0;
+			instr_slti  <= 0;
+			instr_sltiu <= 0;
+			instr_xori  <= 0;
+			instr_ori   <= 0;
+			instr_andi  <= 0;
+
+			instr_add   <= 0;
+			instr_sub   <= 0;
+			instr_sll   <= 0;
+			instr_slt   <= 0;
+			instr_sltu  <= 0;
+			instr_xor   <= 0;
+			instr_srl   <= 0;
+			instr_sra   <= 0;
+			instr_or    <= 0;
+			instr_and   <= 0;
+		end
+	end
+
+
+	// Main State Machine
+
+	localparam cpu_state_trap   = 8'b10000000;
+	localparam cpu_state_fetch  = 8'b01000000;
+	localparam cpu_state_ld_rs1 = 8'b00100000;
+	localparam cpu_state_ld_rs2 = 8'b00010000;
+	localparam cpu_state_exec   = 8'b00001000;
+	localparam cpu_state_shift  = 8'b00000100;
+	localparam cpu_state_stmem  = 8'b00000010;
+	localparam cpu_state_ldmem  = 8'b00000001;
+
+	reg [7:0] cpu_state;
+	reg [1:0] irq_state;
+
+	`FORMAL_KEEP reg [127:0] dbg_ascii_state;
+
+	always @* begin
+		dbg_ascii_state = "";
+		if (cpu_state == cpu_state_trap)   dbg_ascii_state = "trap";
+		if (cpu_state == cpu_state_fetch)  dbg_ascii_state = "fetch";
+		if (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1";
+		if (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2";
+		if (cpu_state == cpu_state_exec)   dbg_ascii_state = "exec";
+		if (cpu_state == cpu_state_shift)  dbg_ascii_state = "shift";
+		if (cpu_state == cpu_state_stmem)  dbg_ascii_state = "stmem";
+		if (cpu_state == cpu_state_ldmem)  dbg_ascii_state = "ldmem";
+	end
+
+	reg set_mem_do_rinst;
+	reg set_mem_do_rdata;
+	reg set_mem_do_wdata;
+
+	reg latched_store;
+	reg latched_stalu;
+	reg latched_branch;
+	reg latched_compr;
+	reg latched_trace;
+	reg latched_is_lu;
+	reg latched_is_lh;
+	reg latched_is_lb;
+	reg [regindex_bits-1:0] latched_rd;
+
+	reg [31:0] current_pc;
+	assign next_pc = latched_store && latched_branch ? reg_out & ~1 : reg_next_pc;
+
+	reg [3:0] pcpi_timeout_counter;
+	reg pcpi_timeout;
+
+	reg [31:0] next_irq_pending;
+	reg do_waitirq;
+
+	reg [31:0] alu_out, alu_out_q;
+	reg alu_out_0, alu_out_0_q;
+	reg alu_wait, alu_wait_2;
+
+	reg [31:0] alu_add_sub;
+	reg [31:0] alu_shl, alu_shr;
+	reg alu_eq, alu_ltu, alu_lts;
+
+	generate if (TWO_CYCLE_ALU) begin
+		always @(posedge clk) begin
+			alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
+			alu_eq <= reg_op1 == reg_op2;
+			alu_lts <= $signed(reg_op1) < $signed(reg_op2);
+			alu_ltu <= reg_op1 < reg_op2;
+			alu_shl <= reg_op1 << reg_op2[4:0];
+			alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
+		end
+	end else begin
+		always @* begin
+			alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
+			alu_eq = reg_op1 == reg_op2;
+			alu_lts = $signed(reg_op1) < $signed(reg_op2);
+			alu_ltu = reg_op1 < reg_op2;
+			alu_shl = reg_op1 << reg_op2[4:0];
+			alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
+		end
+	end endgenerate
+
+	always @* begin
+		alu_out_0 = 'bx;
+		(* parallel_case, full_case *)
+		case (1'b1)
+			instr_beq:
+				alu_out_0 = alu_eq;
+			instr_bne:
+				alu_out_0 = !alu_eq;
+			instr_bge:
+				alu_out_0 = !alu_lts;
+			instr_bgeu:
+				alu_out_0 = !alu_ltu;
+			is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
+				alu_out_0 = alu_lts;
+			is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
+				alu_out_0 = alu_ltu;
+		endcase
+
+		alu_out = 'bx;
+		(* parallel_case, full_case *)
+		case (1'b1)
+			is_lui_auipc_jal_jalr_addi_add_sub:
+				alu_out = alu_add_sub;
+			is_compare:
+				alu_out = alu_out_0;
+			instr_xori || instr_xor:
+				alu_out = reg_op1 ^ reg_op2;
+			instr_ori || instr_or:
+				alu_out = reg_op1 | reg_op2;
+			instr_andi || instr_and:
+				alu_out = reg_op1 & reg_op2;
+			BARREL_SHIFTER && (instr_sll || instr_slli):
+				alu_out = alu_shl;
+			BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai):
+				alu_out = alu_shr;
+		endcase
+
+`ifdef RISCV_FORMAL_BLACKBOX_ALU
+		alu_out_0 = $anyseq;
+		alu_out = $anyseq;
+`endif
+	end
+
+	reg clear_prefetched_high_word_q;
+	always @(posedge clk) clear_prefetched_high_word_q <= clear_prefetched_high_word;
+
+	always @* begin
+		clear_prefetched_high_word = clear_prefetched_high_word_q;
+		if (!prefetched_high_word)
+			clear_prefetched_high_word = 0;
+		if (latched_branch || irq_state || !resetn)
+			clear_prefetched_high_word = COMPRESSED_ISA;
+	end
+
+	reg cpuregs_write;
+	reg [31:0] cpuregs_wrdata;
+	reg [31:0] cpuregs_rs1;
+	reg [31:0] cpuregs_rs2;
+	reg [regindex_bits-1:0] decoded_rs;
+
+	always @* begin
+		cpuregs_write = 0;
+		cpuregs_wrdata = 'bx;
+
+		if (cpu_state == cpu_state_fetch) begin
+			(* parallel_case *)
+			case (1'b1)
+				latched_branch: begin
+					cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4);
+					cpuregs_write = 1;
+				end
+				latched_store && !latched_branch: begin
+					cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out;
+					cpuregs_write = 1;
+				end
+				ENABLE_IRQ && irq_state[0]: begin
+					cpuregs_wrdata = reg_next_pc | latched_compr;
+					cpuregs_write = 1;
+				end
+				ENABLE_IRQ && irq_state[1]: begin
+					cpuregs_wrdata = irq_pending & ~irq_mask;
+					cpuregs_write = 1;
+				end
+			endcase
+		end
+	end
+
+`ifndef PICORV32_REGS
+	always @(posedge clk) begin
+		if (resetn && cpuregs_write && latched_rd)
+`ifdef PICORV32_TESTBUG_001
+			cpuregs[latched_rd ^ 1] <= cpuregs_wrdata;
+`elsif PICORV32_TESTBUG_002
+			cpuregs[latched_rd] <= cpuregs_wrdata ^ 1;
+`else
+			cpuregs[latched_rd] <= cpuregs_wrdata;
+`endif
+	end
+
+	always @* begin
+		decoded_rs = 'bx;
+		if (ENABLE_REGS_DUALPORT) begin
+`ifndef RISCV_FORMAL_BLACKBOX_REGS
+			cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0;
+			cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0;
+`else
+			cpuregs_rs1 = decoded_rs1 ? $anyseq : 0;
+			cpuregs_rs2 = decoded_rs2 ? $anyseq : 0;
+`endif
+		end else begin
+			decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
+`ifndef RISCV_FORMAL_BLACKBOX_REGS
+			cpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0;
+`else
+			cpuregs_rs1 = decoded_rs ? $anyseq : 0;
+`endif
+			cpuregs_rs2 = cpuregs_rs1;
+		end
+	end
+`else
+	wire[31:0] cpuregs_rdata1;
+	wire[31:0] cpuregs_rdata2;
+
+	wire [5:0] cpuregs_waddr = latched_rd;
+	wire [5:0] cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs;
+	wire [5:0] cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0;
+
+	`PICORV32_REGS cpuregs (
+		.clk(clk),
+		.wen(resetn && cpuregs_write && latched_rd),
+		.waddr(cpuregs_waddr),
+		.raddr1(cpuregs_raddr1),
+		.raddr2(cpuregs_raddr2),
+		.wdata(cpuregs_wrdata),
+		.rdata1(cpuregs_rdata1),
+		.rdata2(cpuregs_rdata2)
+	);
+
+	always @* begin
+		decoded_rs = 'bx;
+		if (ENABLE_REGS_DUALPORT) begin
+			cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0;
+			cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0;
+		end else begin
+			decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
+			cpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0;
+			cpuregs_rs2 = cpuregs_rs1;
+		end
+	end
+`endif
+
+	assign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask));
+
+	always @(posedge clk) begin
+		trap <= 0;
+		reg_sh <= 'bx;
+		reg_out <= 'bx;
+		set_mem_do_rinst = 0;
+		set_mem_do_rdata = 0;
+		set_mem_do_wdata = 0;
+
+		alu_out_0_q <= alu_out_0;
+		alu_out_q <= alu_out;
+
+		alu_wait <= 0;
+		alu_wait_2 <= 0;
+
+		if (launch_next_insn) begin
+			dbg_rs1val <= 'bx;
+			dbg_rs2val <= 'bx;
+			dbg_rs1val_valid <= 0;
+			dbg_rs2val_valid <= 0;
+		end
+
+		if (WITH_PCPI && CATCH_ILLINSN) begin
+			if (resetn && pcpi_valid && !pcpi_int_wait) begin
+				if (pcpi_timeout_counter)
+					pcpi_timeout_counter <= pcpi_timeout_counter - 1;
+			end else
+				pcpi_timeout_counter <= ~0;
+			pcpi_timeout <= !pcpi_timeout_counter;
+		end
+
+		if (ENABLE_COUNTERS) begin
+			count_cycle <= resetn ? count_cycle + 1 : 0;
+			if (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0;
+		end else begin
+			count_cycle <= 'bx;
+			count_instr <= 'bx;
+		end
+
+		next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx;
+
+		if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin
+			timer <= timer - 1;
+		end
+
+		decoder_trigger <= mem_do_rinst && mem_done;
+		decoder_trigger_q <= decoder_trigger;
+		decoder_pseudo_trigger <= 0;
+		decoder_pseudo_trigger_q <= decoder_pseudo_trigger;
+		do_waitirq <= 0;
+
+		trace_valid <= 0;
+
+		if (!ENABLE_TRACE)
+			trace_data <= 'bx;
+
+		if (!resetn) begin
+			reg_pc <= PROGADDR_RESET;
+			reg_next_pc <= PROGADDR_RESET;
+			if (ENABLE_COUNTERS)
+				count_instr <= 0;
+			latched_store <= 0;
+			latched_stalu <= 0;
+			latched_branch <= 0;
+			latched_trace <= 0;
+			latched_is_lu <= 0;
+			latched_is_lh <= 0;
+			latched_is_lb <= 0;
+			pcpi_valid <= 0;
+			pcpi_timeout <= 0;
+			irq_active <= 0;
+			irq_delay <= 0;
+			irq_mask <= ~0;
+			next_irq_pending = 0;
+			irq_state <= 0;
+			eoi <= 0;
+			timer <= 0;
+			if (~STACKADDR) begin
+				latched_store <= 1;
+				latched_rd <= 2;
+				reg_out <= STACKADDR;
+			end
+			cpu_state <= cpu_state_fetch;
+		end else
+		(* parallel_case, full_case *)
+		case (cpu_state)
+			cpu_state_trap: begin
+				trap <= 1;
+			end
+
+			cpu_state_fetch: begin
+				mem_do_rinst <= !decoder_trigger && !do_waitirq;
+				mem_wordsize <= 0;
+
+				current_pc = reg_next_pc;
+
+				(* parallel_case *)
+				case (1'b1)
+					latched_branch: begin
+						current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc;
+						`debug($display("ST_RD:  %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);)
+					end
+					latched_store && !latched_branch: begin
+						`debug($display("ST_RD:  %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);)
+					end
+					ENABLE_IRQ && irq_state[0]: begin
+						current_pc = PROGADDR_IRQ;
+						irq_active <= 1;
+						mem_do_rinst <= 1;
+					end
+					ENABLE_IRQ && irq_state[1]: begin
+						eoi <= irq_pending & ~irq_mask;
+						next_irq_pending = next_irq_pending & irq_mask;
+					end
+				endcase
+
+				if (ENABLE_TRACE && latched_trace) begin
+					latched_trace <= 0;
+					trace_valid <= 1;
+					if (latched_branch)
+						trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32'hfffffffe);
+					else
+						trace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out);
+				end
+
+				reg_pc <= current_pc;
+				reg_next_pc <= current_pc;
+
+				latched_store <= 0;
+				latched_stalu <= 0;
+				latched_branch <= 0;
+				latched_is_lu <= 0;
+				latched_is_lh <= 0;
+				latched_is_lb <= 0;
+				latched_rd <= decoded_rd;
+				latched_compr <= compressed_instr;
+
+				if (ENABLE_IRQ && ((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin
+					irq_state <=
+						irq_state == 2'b00 ? 2'b01 :
+						irq_state == 2'b01 ? 2'b10 : 2'b00;
+					latched_compr <= latched_compr;
+					if (ENABLE_IRQ_QREGS)
+						latched_rd <= irqregs_offset | irq_state[0];
+					else
+						latched_rd <= irq_state[0] ? 4 : 3;
+				end else
+				if (ENABLE_IRQ && (decoder_trigger || do_waitirq) && instr_waitirq) begin
+					if (irq_pending) begin
+						latched_store <= 1;
+						reg_out <= irq_pending;
+						reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
+						mem_do_rinst <= 1;
+					end else
+						do_waitirq <= 1;
+				end else
+				if (decoder_trigger) begin
+					`debug($display("-- %-0t", $time);)
+					irq_delay <= irq_active;
+					reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
+					if (ENABLE_TRACE)
+						latched_trace <= 1;
+					if (ENABLE_COUNTERS) begin
+						count_instr <= count_instr + 1;
+						if (!ENABLE_COUNTERS64) count_instr[63:32] <= 0;
+					end
+					if (instr_jal) begin
+						mem_do_rinst <= 1;
+						reg_next_pc <= current_pc + decoded_imm_j;
+						latched_branch <= 1;
+					end else begin
+						mem_do_rinst <= 0;
+						mem_do_prefetch <= !instr_jalr && !instr_retirq;
+						cpu_state <= cpu_state_ld_rs1;
+					end
+				end
+			end
+
+			cpu_state_ld_rs1: begin
+				reg_op1 <= 'bx;
+				reg_op2 <= 'bx;
+
+				(* parallel_case *)
+				case (1'b1)
+					(CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin
+						if (WITH_PCPI) begin
+							`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+							reg_op1 <= cpuregs_rs1;
+							dbg_rs1val <= cpuregs_rs1;
+							dbg_rs1val_valid <= 1;
+							if (ENABLE_REGS_DUALPORT) begin
+								pcpi_valid <= 1;
+								`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
+								reg_sh <= cpuregs_rs2;
+								reg_op2 <= cpuregs_rs2;
+								dbg_rs2val <= cpuregs_rs2;
+								dbg_rs2val_valid <= 1;
+								if (pcpi_int_ready) begin
+									mem_do_rinst <= 1;
+									pcpi_valid <= 0;
+									reg_out <= pcpi_int_rd;
+									latched_store <= pcpi_int_wr;
+									cpu_state <= cpu_state_fetch;
+								end else
+								if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
+									pcpi_valid <= 0;
+									`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
+									if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
+										next_irq_pending[irq_ebreak] = 1;
+										cpu_state <= cpu_state_fetch;
+									end else
+										cpu_state <= cpu_state_trap;
+								end
+							end else begin
+								cpu_state <= cpu_state_ld_rs2;
+							end
+						end else begin
+							`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
+							if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
+								next_irq_pending[irq_ebreak] = 1;
+								cpu_state <= cpu_state_fetch;
+							end else
+								cpu_state <= cpu_state_trap;
+						end
+					end
+					ENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
+						(* parallel_case, full_case *)
+						case (1'b1)
+							instr_rdcycle:
+								reg_out <= count_cycle[31:0];
+							instr_rdcycleh && ENABLE_COUNTERS64:
+								reg_out <= count_cycle[63:32];
+							instr_rdinstr:
+								reg_out <= count_instr[31:0];
+							instr_rdinstrh && ENABLE_COUNTERS64:
+								reg_out <= count_instr[63:32];
+						endcase
+						latched_store <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+					is_lui_auipc_jal: begin
+						reg_op1 <= instr_lui ? 0 : reg_pc;
+						reg_op2 <= decoded_imm;
+						if (TWO_CYCLE_ALU)
+							alu_wait <= 1;
+						else
+							mem_do_rinst <= mem_do_prefetch;
+						cpu_state <= cpu_state_exec;
+					end
+					ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_out <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						latched_store <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+					ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_out <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						latched_rd <= latched_rd | irqregs_offset;
+						latched_store <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+					ENABLE_IRQ && instr_retirq: begin
+						eoi <= 0;
+						irq_active <= 0;
+						latched_branch <= 1;
+						latched_store <= 1;
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+					ENABLE_IRQ && instr_maskirq: begin
+						latched_store <= 1;
+						reg_out <= irq_mask;
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						irq_mask <= cpuregs_rs1 | MASKED_IRQ;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+					ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin
+						latched_store <= 1;
+						reg_out <= timer;
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						timer <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+					is_lb_lh_lw_lbu_lhu && !instr_trap: begin
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_op1 <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						cpu_state <= cpu_state_ldmem;
+						mem_do_rinst <= 1;
+					end
+					is_slli_srli_srai && !BARREL_SHIFTER: begin
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_op1 <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						reg_sh <= decoded_rs2;
+						cpu_state <= cpu_state_shift;
+					end
+					is_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && BARREL_SHIFTER: begin
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_op1 <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm;
+						if (TWO_CYCLE_ALU)
+							alu_wait <= 1;
+						else
+							mem_do_rinst <= mem_do_prefetch;
+						cpu_state <= cpu_state_exec;
+					end
+					default: begin
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_op1 <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						if (ENABLE_REGS_DUALPORT) begin
+							`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
+							reg_sh <= cpuregs_rs2;
+							reg_op2 <= cpuregs_rs2;
+							dbg_rs2val <= cpuregs_rs2;
+							dbg_rs2val_valid <= 1;
+							(* parallel_case *)
+							case (1'b1)
+								is_sb_sh_sw: begin
+									cpu_state <= cpu_state_stmem;
+									mem_do_rinst <= 1;
+								end
+								is_sll_srl_sra && !BARREL_SHIFTER: begin
+									cpu_state <= cpu_state_shift;
+								end
+								default: begin
+									if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
+										alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
+										alu_wait <= 1;
+									end else
+										mem_do_rinst <= mem_do_prefetch;
+									cpu_state <= cpu_state_exec;
+								end
+							endcase
+						end else
+							cpu_state <= cpu_state_ld_rs2;
+					end
+				endcase
+			end
+
+			cpu_state_ld_rs2: begin
+				`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
+				reg_sh <= cpuregs_rs2;
+				reg_op2 <= cpuregs_rs2;
+				dbg_rs2val <= cpuregs_rs2;
+				dbg_rs2val_valid <= 1;
+
+				(* parallel_case *)
+				case (1'b1)
+					WITH_PCPI && instr_trap: begin
+						pcpi_valid <= 1;
+						if (pcpi_int_ready) begin
+							mem_do_rinst <= 1;
+							pcpi_valid <= 0;
+							reg_out <= pcpi_int_rd;
+							latched_store <= pcpi_int_wr;
+							cpu_state <= cpu_state_fetch;
+						end else
+						if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
+							pcpi_valid <= 0;
+							`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
+							if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
+								next_irq_pending[irq_ebreak] = 1;
+								cpu_state <= cpu_state_fetch;
+							end else
+								cpu_state <= cpu_state_trap;
+						end
+					end
+					is_sb_sh_sw: begin
+						cpu_state <= cpu_state_stmem;
+						mem_do_rinst <= 1;
+					end
+					is_sll_srl_sra && !BARREL_SHIFTER: begin
+						cpu_state <= cpu_state_shift;
+					end
+					default: begin
+						if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
+							alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
+							alu_wait <= 1;
+						end else
+							mem_do_rinst <= mem_do_prefetch;
+						cpu_state <= cpu_state_exec;
+					end
+				endcase
+			end
+
+			cpu_state_exec: begin
+				reg_out <= reg_pc + decoded_imm;
+				if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin
+					mem_do_rinst <= mem_do_prefetch && !alu_wait_2;
+					alu_wait <= alu_wait_2;
+				end else
+				if (is_beq_bne_blt_bge_bltu_bgeu) begin
+					latched_rd <= 0;
+					latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
+					latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
+					if (mem_done)
+						cpu_state <= cpu_state_fetch;
+					if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin
+						decoder_trigger <= 0;
+						set_mem_do_rinst = 1;
+					end
+				end else begin
+					latched_branch <= instr_jalr;
+					latched_store <= 1;
+					latched_stalu <= 1;
+					cpu_state <= cpu_state_fetch;
+				end
+			end
+
+			cpu_state_shift: begin
+				latched_store <= 1;
+				if (reg_sh == 0) begin
+					reg_out <= reg_op1;
+					mem_do_rinst <= mem_do_prefetch;
+					cpu_state <= cpu_state_fetch;
+				end else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin
+					(* parallel_case, full_case *)
+					case (1'b1)
+						instr_slli || instr_sll: reg_op1 <= reg_op1 << 4;
+						instr_srli || instr_srl: reg_op1 <= reg_op1 >> 4;
+						instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4;
+					endcase
+					reg_sh <= reg_sh - 4;
+				end else begin
+					(* parallel_case, full_case *)
+					case (1'b1)
+						instr_slli || instr_sll: reg_op1 <= reg_op1 << 1;
+						instr_srli || instr_srl: reg_op1 <= reg_op1 >> 1;
+						instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1;
+					endcase
+					reg_sh <= reg_sh - 1;
+				end
+			end
+
+			cpu_state_stmem: begin
+				if (ENABLE_TRACE)
+					reg_out <= reg_op2;
+				if (!mem_do_prefetch || mem_done) begin
+					if (!mem_do_wdata) begin
+						(* parallel_case, full_case *)
+						case (1'b1)
+							instr_sb: mem_wordsize <= 2;
+							instr_sh: mem_wordsize <= 1;
+							instr_sw: mem_wordsize <= 0;
+						endcase
+						if (ENABLE_TRACE) begin
+							trace_valid <= 1;
+							trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
+						end
+						reg_op1 <= reg_op1 + decoded_imm;
+						set_mem_do_wdata = 1;
+					end
+					if (!mem_do_prefetch && mem_done) begin
+						cpu_state <= cpu_state_fetch;
+						decoder_trigger <= 1;
+						decoder_pseudo_trigger <= 1;
+					end
+				end
+			end
+
+			cpu_state_ldmem: begin
+				latched_store <= 1;
+				if (!mem_do_prefetch || mem_done) begin
+					if (!mem_do_rdata) begin
+						(* parallel_case, full_case *)
+						case (1'b1)
+							instr_lb || instr_lbu: mem_wordsize <= 2;
+							instr_lh || instr_lhu: mem_wordsize <= 1;
+							instr_lw: mem_wordsize <= 0;
+						endcase
+						latched_is_lu <= is_lbu_lhu_lw;
+						latched_is_lh <= instr_lh;
+						latched_is_lb <= instr_lb;
+						if (ENABLE_TRACE) begin
+							trace_valid <= 1;
+							trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
+						end
+						reg_op1 <= reg_op1 + decoded_imm;
+						set_mem_do_rdata = 1;
+					end
+					if (!mem_do_prefetch && mem_done) begin
+						(* parallel_case, full_case *)
+						case (1'b1)
+							latched_is_lu: reg_out <= mem_rdata_word;
+							latched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]);
+							latched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]);
+						endcase
+						decoder_trigger <= 1;
+						decoder_pseudo_trigger <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+				end
+			end
+		endcase
+
+		if (ENABLE_IRQ) begin
+			next_irq_pending = next_irq_pending | irq;
+			if(ENABLE_IRQ_TIMER && timer)
+				if (timer - 1 == 0)
+					next_irq_pending[irq_timer] = 1;
+		end
+
+		if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin
+			if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
+				`debug($display("MISALIGNED WORD: 0x%08x", reg_op1);)
+				if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
+					next_irq_pending[irq_buserror] = 1;
+				end else
+					cpu_state <= cpu_state_trap;
+			end
+			if (mem_wordsize == 1 && reg_op1[0] != 0) begin
+				`debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);)
+				if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
+					next_irq_pending[irq_buserror] = 1;
+				end else
+					cpu_state <= cpu_state_trap;
+			end
+		end
+		if (CATCH_MISALIGN && resetn && mem_do_rinst && (COMPRESSED_ISA ? reg_pc[0] : |reg_pc[1:0])) begin
+			`debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);)
+			if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
+				next_irq_pending[irq_buserror] = 1;
+			end else
+				cpu_state <= cpu_state_trap;
+		end
+		if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin
+			cpu_state <= cpu_state_trap;
+		end
+
+		if (!resetn || mem_done) begin
+			mem_do_prefetch <= 0;
+			mem_do_rinst <= 0;
+			mem_do_rdata <= 0;
+			mem_do_wdata <= 0;
+		end
+
+		if (set_mem_do_rinst)
+			mem_do_rinst <= 1;
+		if (set_mem_do_rdata)
+			mem_do_rdata <= 1;
+		if (set_mem_do_wdata)
+			mem_do_wdata <= 1;
+
+		irq_pending <= next_irq_pending & ~MASKED_IRQ;
+
+		if (!CATCH_MISALIGN) begin
+			if (COMPRESSED_ISA) begin
+				reg_pc[0] <= 0;
+				reg_next_pc[0] <= 0;
+			end else begin
+				reg_pc[1:0] <= 0;
+				reg_next_pc[1:0] <= 0;
+			end
+		end
+		current_pc = 'bx;
+	end
+
+`ifdef RISCV_FORMAL
+	reg dbg_irq_call;
+	reg dbg_irq_enter;
+	reg [31:0] dbg_irq_ret;
+	always @(posedge clk) begin
+		rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn;
+		rvfi_order <= resetn ? rvfi_order + rvfi_valid : 0;
+
+		rvfi_insn <= dbg_insn_opcode;
+		rvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
+		rvfi_rs2_addr <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
+		rvfi_pc_rdata <= dbg_insn_addr;
+		rvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0;
+		rvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0;
+		rvfi_trap <= trap;
+		rvfi_halt <= trap;
+		rvfi_intr <= dbg_irq_enter;
+		rvfi_mode <= 3;
+		rvfi_ixl <= 1;
+
+		if (!resetn) begin
+			dbg_irq_call <= 0;
+			dbg_irq_enter <= 0;
+		end else
+		if (rvfi_valid) begin
+			dbg_irq_call <= 0;
+			dbg_irq_enter <= dbg_irq_call;
+		end else
+		if (irq_state == 1) begin
+			dbg_irq_call <= 1;
+			dbg_irq_ret <= next_pc;
+		end
+
+		if (!resetn) begin
+			rvfi_rd_addr <= 0;
+			rvfi_rd_wdata <= 0;
+		end else
+		if (cpuregs_write && !irq_state) begin
+`ifdef PICORV32_TESTBUG_003
+			rvfi_rd_addr <= latched_rd ^ 1;
+`else
+			rvfi_rd_addr <= latched_rd;
+`endif
+`ifdef PICORV32_TESTBUG_004
+			rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata ^ 1 : 0;
+`else
+			rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata : 0;
+`endif
+		end else
+		if (rvfi_valid) begin
+			rvfi_rd_addr <= 0;
+			rvfi_rd_wdata <= 0;
+		end
+
+		casez (dbg_insn_opcode)
+			32'b 0000000_?????_000??_???_?????_0001011: begin // getq
+				rvfi_rs1_addr <= 0;
+				rvfi_rs1_rdata <= 0;
+			end
+			32'b 0000001_?????_?????_???_000??_0001011: begin // setq
+				rvfi_rd_addr <= 0;
+				rvfi_rd_wdata <= 0;
+			end
+			32'b 0000010_?????_00000_???_00000_0001011: begin // retirq
+				rvfi_rs1_addr <= 0;
+				rvfi_rs1_rdata <= 0;
+			end
+		endcase
+
+		if (!dbg_irq_call) begin
+			if (dbg_mem_instr) begin
+				rvfi_mem_addr <= 0;
+				rvfi_mem_rmask <= 0;
+				rvfi_mem_wmask <= 0;
+				rvfi_mem_rdata <= 0;
+				rvfi_mem_wdata <= 0;
+			end else
+			if (dbg_mem_valid && dbg_mem_ready) begin
+				rvfi_mem_addr <= dbg_mem_addr;
+				rvfi_mem_rmask <= dbg_mem_wstrb ? 0 : ~0;
+				rvfi_mem_wmask <= dbg_mem_wstrb;
+				rvfi_mem_rdata <= dbg_mem_rdata;
+				rvfi_mem_wdata <= dbg_mem_wdata;
+			end
+		end
+	end
+
+	always @* begin
+`ifdef PICORV32_TESTBUG_005
+		rvfi_pc_wdata = (dbg_irq_call ? dbg_irq_ret : dbg_insn_addr) ^ 4;
+`else
+		rvfi_pc_wdata = dbg_irq_call ? dbg_irq_ret : dbg_insn_addr;
+`endif
+
+		rvfi_csr_mcycle_rmask = 0;
+		rvfi_csr_mcycle_wmask = 0;
+		rvfi_csr_mcycle_rdata = 0;
+		rvfi_csr_mcycle_wdata = 0;
+
+		rvfi_csr_minstret_rmask = 0;
+		rvfi_csr_minstret_wmask = 0;
+		rvfi_csr_minstret_rdata = 0;
+		rvfi_csr_minstret_wdata = 0;
+
+		if (rvfi_valid && rvfi_insn[6:0] == 7'b 1110011 && rvfi_insn[13:12] == 3'b010) begin
+			if (rvfi_insn[31:20] == 12'h C00) begin
+				rvfi_csr_mcycle_rmask = 64'h 0000_0000_FFFF_FFFF;
+				rvfi_csr_mcycle_rdata = {32'h 0000_0000, rvfi_rd_wdata};
+			end
+			if (rvfi_insn[31:20] == 12'h C80) begin
+				rvfi_csr_mcycle_rmask = 64'h FFFF_FFFF_0000_0000;
+				rvfi_csr_mcycle_rdata = {rvfi_rd_wdata, 32'h 0000_0000};
+			end
+			if (rvfi_insn[31:20] == 12'h C02) begin
+				rvfi_csr_minstret_rmask = 64'h 0000_0000_FFFF_FFFF;
+				rvfi_csr_minstret_rdata = {32'h 0000_0000, rvfi_rd_wdata};
+			end
+			if (rvfi_insn[31:20] == 12'h C82) begin
+				rvfi_csr_minstret_rmask = 64'h FFFF_FFFF_0000_0000;
+				rvfi_csr_minstret_rdata = {rvfi_rd_wdata, 32'h 0000_0000};
+			end
+		end
+	end
+`endif
+
+	// Formal Verification
+`ifdef FORMAL
+	reg [3:0] last_mem_nowait;
+	always @(posedge clk)
+		last_mem_nowait <= {last_mem_nowait, mem_ready || !mem_valid};
+
+	// stall the memory interface for max 4 cycles
+	restrict property (|last_mem_nowait || mem_ready || !mem_valid);
+
+	// resetn low in first cycle, after that resetn high
+	restrict property (resetn != $initstate);
+
+	// this just makes it much easier to read traces. uncomment as needed.
+	// assume property (mem_valid || !mem_ready);
+
+	reg ok;
+	always @* begin
+		if (resetn) begin
+			// instruction fetches are read-only
+			if (mem_valid && mem_instr)
+				assert (mem_wstrb == 0);
+
+			// cpu_state must be valid
+			ok = 0;
+			if (cpu_state == cpu_state_trap)   ok = 1;
+			if (cpu_state == cpu_state_fetch)  ok = 1;
+			if (cpu_state == cpu_state_ld_rs1) ok = 1;
+			if (cpu_state == cpu_state_ld_rs2) ok = !ENABLE_REGS_DUALPORT;
+			if (cpu_state == cpu_state_exec)   ok = 1;
+			if (cpu_state == cpu_state_shift)  ok = 1;
+			if (cpu_state == cpu_state_stmem)  ok = 1;
+			if (cpu_state == cpu_state_ldmem)  ok = 1;
+			assert (ok);
+		end
+	end
+
+	reg last_mem_la_read = 0;
+	reg last_mem_la_write = 0;
+	reg [31:0] last_mem_la_addr;
+	reg [31:0] last_mem_la_wdata;
+	reg [3:0] last_mem_la_wstrb = 0;
+
+	always @(posedge clk) begin
+		last_mem_la_read <= mem_la_read;
+		last_mem_la_write <= mem_la_write;
+		last_mem_la_addr <= mem_la_addr;
+		last_mem_la_wdata <= mem_la_wdata;
+		last_mem_la_wstrb <= mem_la_wstrb;
+
+		if (last_mem_la_read) begin
+			assert(mem_valid);
+			assert(mem_addr == last_mem_la_addr);
+			assert(mem_wstrb == 0);
+		end
+		if (last_mem_la_write) begin
+			assert(mem_valid);
+			assert(mem_addr == last_mem_la_addr);
+			assert(mem_wdata == last_mem_la_wdata);
+			assert(mem_wstrb == last_mem_la_wstrb);
+		end
+		if (mem_la_read || mem_la_write) begin
+			assert(!mem_valid || mem_ready);
+		end
+	end
+`endif
+endmodule
+
+// This is a simple example implementation of PICORV32_REGS.
+// Use the PICORV32_REGS mechanism if you want to use custom
+// memory resources to implement the processor register file.
+// Note that your implementation must match the requirements of
+// the PicoRV32 configuration. (e.g. QREGS, etc)
+module picorv32_regs (
+	input clk, wen,
+	input [5:0] waddr,
+	input [5:0] raddr1,
+	input [5:0] raddr2,
+	input [31:0] wdata,
+	output [31:0] rdata1,
+	output [31:0] rdata2
+);
+	reg [31:0] regs [0:30];
+
+	always @(posedge clk)
+		if (wen) regs[~waddr[4:0]] <= wdata;
+
+	assign rdata1 = regs[~raddr1[4:0]];
+	assign rdata2 = regs[~raddr2[4:0]];
+endmodule
+
+
+/***************************************************************
+ * picorv32_pcpi_mul
+ ***************************************************************/
+
+module picorv32_pcpi_mul #(
+	parameter STEPS_AT_ONCE = 1,
+	parameter CARRY_CHAIN = 4
+) (
+	input clk, resetn,
+
+	input             pcpi_valid,
+	input      [31:0] pcpi_insn,
+	input      [31:0] pcpi_rs1,
+	input      [31:0] pcpi_rs2,
+	output reg        pcpi_wr,
+	output reg [31:0] pcpi_rd,
+	output reg        pcpi_wait,
+	output reg        pcpi_ready
+);
+	reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
+	wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
+	wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
+	wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
+	wire instr_rs2_signed = |{instr_mulh};
+
+	reg pcpi_wait_q;
+	wire mul_start = pcpi_wait && !pcpi_wait_q;
+
+	always @(posedge clk) begin
+		instr_mul <= 0;
+		instr_mulh <= 0;
+		instr_mulhsu <= 0;
+		instr_mulhu <= 0;
+
+		if (resetn && pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
+			case (pcpi_insn[14:12])
+				3'b000: instr_mul <= 1;
+				3'b001: instr_mulh <= 1;
+				3'b010: instr_mulhsu <= 1;
+				3'b011: instr_mulhu <= 1;
+			endcase
+		end
+
+		pcpi_wait <= instr_any_mul;
+		pcpi_wait_q <= pcpi_wait;
+	end
+
+	reg [63:0] rs1, rs2, rd, rdx;
+	reg [63:0] next_rs1, next_rs2, this_rs2;
+	reg [63:0] next_rd, next_rdx, next_rdt;
+	reg [6:0] mul_counter;
+	reg mul_waiting;
+	reg mul_finish;
+	integer i, j;
+
+	// carry save accumulator
+	always @* begin
+		next_rd = rd;
+		next_rdx = rdx;
+		next_rs1 = rs1;
+		next_rs2 = rs2;
+
+		for (i = 0; i < STEPS_AT_ONCE; i=i+1) begin
+			this_rs2 = next_rs1[0] ? next_rs2 : 0;
+			if (CARRY_CHAIN == 0) begin
+				next_rdt = next_rd ^ next_rdx ^ this_rs2;
+				next_rdx = ((next_rd & next_rdx) | (next_rd & this_rs2) | (next_rdx & this_rs2)) << 1;
+				next_rd = next_rdt;
+			end else begin
+				next_rdt = 0;
+				for (j = 0; j < 64; j = j + CARRY_CHAIN)
+					{next_rdt[j+CARRY_CHAIN-1], next_rd[j +: CARRY_CHAIN]} =
+							next_rd[j +: CARRY_CHAIN] + next_rdx[j +: CARRY_CHAIN] + this_rs2[j +: CARRY_CHAIN];
+				next_rdx = next_rdt << 1;
+			end
+			next_rs1 = next_rs1 >> 1;
+			next_rs2 = next_rs2 << 1;
+		end
+	end
+
+	always @(posedge clk) begin
+		mul_finish <= 0;
+		if (!resetn) begin
+			mul_waiting <= 1;
+		end else
+		if (mul_waiting) begin
+			if (instr_rs1_signed)
+				rs1 <= $signed(pcpi_rs1);
+			else
+				rs1 <= $unsigned(pcpi_rs1);
+
+			if (instr_rs2_signed)
+				rs2 <= $signed(pcpi_rs2);
+			else
+				rs2 <= $unsigned(pcpi_rs2);
+
+			rd <= 0;
+			rdx <= 0;
+			mul_counter <= (instr_any_mulh ? 63 - STEPS_AT_ONCE : 31 - STEPS_AT_ONCE);
+			mul_waiting <= !mul_start;
+		end else begin
+			rd <= next_rd;
+			rdx <= next_rdx;
+			rs1 <= next_rs1;
+			rs2 <= next_rs2;
+
+			mul_counter <= mul_counter - STEPS_AT_ONCE;
+			if (mul_counter[6]) begin
+				mul_finish <= 1;
+				mul_waiting <= 1;
+			end
+		end
+	end
+
+	always @(posedge clk) begin
+		pcpi_wr <= 0;
+		pcpi_ready <= 0;
+		if (mul_finish && resetn) begin
+			pcpi_wr <= 1;
+			pcpi_ready <= 1;
+			pcpi_rd <= instr_any_mulh ? rd >> 32 : rd;
+		end
+	end
+endmodule
+
+module picorv32_pcpi_fast_mul #(
+	parameter EXTRA_MUL_FFS = 0,
+	parameter EXTRA_INSN_FFS = 0,
+	parameter MUL_CLKGATE = 0
+) (
+	input clk, resetn,
+
+	input             pcpi_valid,
+	input      [31:0] pcpi_insn,
+	input      [31:0] pcpi_rs1,
+	input      [31:0] pcpi_rs2,
+	output            pcpi_wr,
+	output     [31:0] pcpi_rd,
+	output            pcpi_wait,
+	output            pcpi_ready
+);
+	reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
+	wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
+	wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
+	wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
+	wire instr_rs2_signed = |{instr_mulh};
+
+	reg shift_out;
+	reg [3:0] active;
+	reg [32:0] rs1, rs2, rs1_q, rs2_q;
+	reg [63:0] rd, rd_q;
+
+	wire pcpi_insn_valid = pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001;
+	reg pcpi_insn_valid_q;
+
+	always @* begin
+		instr_mul = 0;
+		instr_mulh = 0;
+		instr_mulhsu = 0;
+		instr_mulhu = 0;
+
+		if (resetn && (EXTRA_INSN_FFS ? pcpi_insn_valid_q : pcpi_insn_valid)) begin
+			case (pcpi_insn[14:12])
+				3'b000: instr_mul = 1;
+				3'b001: instr_mulh = 1;
+				3'b010: instr_mulhsu = 1;
+				3'b011: instr_mulhu = 1;
+			endcase
+		end
+	end
+
+	always @(posedge clk) begin
+		pcpi_insn_valid_q <= pcpi_insn_valid;
+		if (!MUL_CLKGATE || active[0]) begin
+			rs1_q <= rs1;
+			rs2_q <= rs2;
+		end
+		if (!MUL_CLKGATE || active[1]) begin
+			rd <= $signed(EXTRA_MUL_FFS ? rs1_q : rs1) * $signed(EXTRA_MUL_FFS ? rs2_q : rs2);
+		end
+		if (!MUL_CLKGATE || active[2]) begin
+			rd_q <= rd;
+		end
+	end
+
+	always @(posedge clk) begin
+		if (instr_any_mul && !(EXTRA_MUL_FFS ? active[3:0] : active[1:0])) begin
+			if (instr_rs1_signed)
+				rs1 <= $signed(pcpi_rs1);
+			else
+				rs1 <= $unsigned(pcpi_rs1);
+
+			if (instr_rs2_signed)
+				rs2 <= $signed(pcpi_rs2);
+			else
+				rs2 <= $unsigned(pcpi_rs2);
+			active[0] <= 1;
+		end else begin
+			active[0] <= 0;
+		end
+
+		active[3:1] <= active;
+		shift_out <= instr_any_mulh;
+
+		if (!resetn)
+			active <= 0;
+	end
+
+	assign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1];
+	assign pcpi_wait = 0;
+	assign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1];
+`ifdef RISCV_FORMAL_ALTOPS
+	assign pcpi_rd =
+			instr_mul    ? (pcpi_rs1 + pcpi_rs2) ^ 32'h5876063e :
+			instr_mulh   ? (pcpi_rs1 + pcpi_rs2) ^ 32'hf6583fb7 :
+			instr_mulhsu ? (pcpi_rs1 - pcpi_rs2) ^ 32'hecfbe137 :
+			instr_mulhu  ? (pcpi_rs1 + pcpi_rs2) ^ 32'h949ce5e8 : 1'bx;
+`else
+	assign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd);
+`endif
+endmodule
+
+
+/***************************************************************
+ * picorv32_pcpi_div
+ ***************************************************************/
+
+module picorv32_pcpi_div (
+	input clk, resetn,
+
+	input             pcpi_valid,
+	input      [31:0] pcpi_insn,
+	input      [31:0] pcpi_rs1,
+	input      [31:0] pcpi_rs2,
+	output reg        pcpi_wr,
+	output reg [31:0] pcpi_rd,
+	output reg        pcpi_wait,
+	output reg        pcpi_ready
+);
+	reg instr_div, instr_divu, instr_rem, instr_remu;
+	wire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu};
+
+	reg pcpi_wait_q;
+	wire start = pcpi_wait && !pcpi_wait_q;
+
+	always @(posedge clk) begin
+		instr_div <= 0;
+		instr_divu <= 0;
+		instr_rem <= 0;
+		instr_remu <= 0;
+
+		if (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
+			case (pcpi_insn[14:12])
+				3'b100: instr_div <= 1;
+				3'b101: instr_divu <= 1;
+				3'b110: instr_rem <= 1;
+				3'b111: instr_remu <= 1;
+			endcase
+		end
+
+		pcpi_wait <= instr_any_div_rem && resetn;
+		pcpi_wait_q <= pcpi_wait && resetn;
+	end
+
+	reg [31:0] dividend;
+	reg [62:0] divisor;
+	reg [31:0] quotient;
+	reg [31:0] quotient_msk;
+	reg running;
+	reg outsign;
+
+	always @(posedge clk) begin
+		pcpi_ready <= 0;
+		pcpi_wr <= 0;
+		pcpi_rd <= 'bx;
+
+		if (!resetn) begin
+			running <= 0;
+		end else
+		if (start) begin
+			running <= 1;
+			dividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1;
+			divisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;
+			outsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]);
+			quotient <= 0;
+			quotient_msk <= 1 << 31;
+		end else
+		if (!quotient_msk && running) begin
+			running <= 0;
+			pcpi_ready <= 1;
+			pcpi_wr <= 1;
+`ifdef RISCV_FORMAL_ALTOPS
+			case (1)
+				instr_div:  pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h7f8529ec;
+				instr_divu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h10e8fd70;
+				instr_rem:  pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h8da68fa5;
+				instr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h3138d0e1;
+			endcase
+`else
+			if (instr_div || instr_divu)
+				pcpi_rd <= outsign ? -quotient : quotient;
+			else
+				pcpi_rd <= outsign ? -dividend : dividend;
+`endif
+		end else begin
+			if (divisor <= dividend) begin
+				dividend <= dividend - divisor;
+				quotient <= quotient | quotient_msk;
+			end
+			divisor <= divisor >> 1;
+`ifdef RISCV_FORMAL_ALTOPS
+			quotient_msk <= quotient_msk >> 5;
+`else
+			quotient_msk <= quotient_msk >> 1;
+`endif
+		end
+	end
+endmodule
+
+
+/***************************************************************
+ * picorv32_axi
+ ***************************************************************/
+
+module picorv32_axi #(
+	parameter [ 0:0] ENABLE_COUNTERS = 1,
+	parameter [ 0:0] ENABLE_COUNTERS64 = 1,
+	parameter [ 0:0] ENABLE_REGS_16_31 = 1,
+	parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
+	parameter [ 0:0] TWO_STAGE_SHIFT = 1,
+	parameter [ 0:0] BARREL_SHIFTER = 0,
+	parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
+	parameter [ 0:0] TWO_CYCLE_ALU = 0,
+	parameter [ 0:0] COMPRESSED_ISA = 0,
+	parameter [ 0:0] CATCH_MISALIGN = 1,
+	parameter [ 0:0] CATCH_ILLINSN = 1,
+	parameter [ 0:0] ENABLE_PCPI = 0,
+	parameter [ 0:0] ENABLE_MUL = 0,
+	parameter [ 0:0] ENABLE_FAST_MUL = 0,
+	parameter [ 0:0] ENABLE_DIV = 0,
+	parameter [ 0:0] ENABLE_IRQ = 0,
+	parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
+	parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
+	parameter [ 0:0] ENABLE_TRACE = 0,
+	parameter [ 0:0] REGS_INIT_ZERO = 0,
+	parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
+	parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
+	parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
+	parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
+	parameter [31:0] STACKADDR = 32'h ffff_ffff
+) (
+	input clk, resetn,
+	output trap,
+
+	// AXI4-lite master memory interface
+
+	output        mem_axi_awvalid,
+	input         mem_axi_awready,
+	output [31:0] mem_axi_awaddr,
+	output [ 2:0] mem_axi_awprot,
+
+	output        mem_axi_wvalid,
+	input         mem_axi_wready,
+	output [31:0] mem_axi_wdata,
+	output [ 3:0] mem_axi_wstrb,
+
+	input         mem_axi_bvalid,
+	output        mem_axi_bready,
+
+	output        mem_axi_arvalid,
+	input         mem_axi_arready,
+	output [31:0] mem_axi_araddr,
+	output [ 2:0] mem_axi_arprot,
+
+	input         mem_axi_rvalid,
+	output        mem_axi_rready,
+	input  [31:0] mem_axi_rdata,
+
+	// Pico Co-Processor Interface (PCPI)
+	output        pcpi_valid,
+	output [31:0] pcpi_insn,
+	output [31:0] pcpi_rs1,
+	output [31:0] pcpi_rs2,
+	input         pcpi_wr,
+	input  [31:0] pcpi_rd,
+	input         pcpi_wait,
+	input         pcpi_ready,
+
+	// IRQ interface
+	input  [31:0] irq,
+	output [31:0] eoi,
+
+`ifdef RISCV_FORMAL
+	output        rvfi_valid,
+	output [63:0] rvfi_order,
+	output [31:0] rvfi_insn,
+	output        rvfi_trap,
+	output        rvfi_halt,
+	output        rvfi_intr,
+	output [ 4:0] rvfi_rs1_addr,
+	output [ 4:0] rvfi_rs2_addr,
+	output [31:0] rvfi_rs1_rdata,
+	output [31:0] rvfi_rs2_rdata,
+	output [ 4:0] rvfi_rd_addr,
+	output [31:0] rvfi_rd_wdata,
+	output [31:0] rvfi_pc_rdata,
+	output [31:0] rvfi_pc_wdata,
+	output [31:0] rvfi_mem_addr,
+	output [ 3:0] rvfi_mem_rmask,
+	output [ 3:0] rvfi_mem_wmask,
+	output [31:0] rvfi_mem_rdata,
+	output [31:0] rvfi_mem_wdata,
+`endif
+
+	// Trace Interface
+	output        trace_valid,
+	output [35:0] trace_data
+);
+	wire        mem_valid;
+	wire [31:0] mem_addr;
+	wire [31:0] mem_wdata;
+	wire [ 3:0] mem_wstrb;
+	wire        mem_instr;
+	wire        mem_ready;
+	wire [31:0] mem_rdata;
+
+	picorv32_axi_adapter axi_adapter (
+		.clk            (clk            ),
+		.resetn         (resetn         ),
+		.mem_axi_awvalid(mem_axi_awvalid),
+		.mem_axi_awready(mem_axi_awready),
+		.mem_axi_awaddr (mem_axi_awaddr ),
+		.mem_axi_awprot (mem_axi_awprot ),
+		.mem_axi_wvalid (mem_axi_wvalid ),
+		.mem_axi_wready (mem_axi_wready ),
+		.mem_axi_wdata  (mem_axi_wdata  ),
+		.mem_axi_wstrb  (mem_axi_wstrb  ),
+		.mem_axi_bvalid (mem_axi_bvalid ),
+		.mem_axi_bready (mem_axi_bready ),
+		.mem_axi_arvalid(mem_axi_arvalid),
+		.mem_axi_arready(mem_axi_arready),
+		.mem_axi_araddr (mem_axi_araddr ),
+		.mem_axi_arprot (mem_axi_arprot ),
+		.mem_axi_rvalid (mem_axi_rvalid ),
+		.mem_axi_rready (mem_axi_rready ),
+		.mem_axi_rdata  (mem_axi_rdata  ),
+		.mem_valid      (mem_valid      ),
+		.mem_instr      (mem_instr      ),
+		.mem_ready      (mem_ready      ),
+		.mem_addr       (mem_addr       ),
+		.mem_wdata      (mem_wdata      ),
+		.mem_wstrb      (mem_wstrb      ),
+		.mem_rdata      (mem_rdata      )
+	);
+
+	picorv32 #(
+		.ENABLE_COUNTERS     (ENABLE_COUNTERS     ),
+		.ENABLE_COUNTERS64   (ENABLE_COUNTERS64   ),
+		.ENABLE_REGS_16_31   (ENABLE_REGS_16_31   ),
+		.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
+		.TWO_STAGE_SHIFT     (TWO_STAGE_SHIFT     ),
+		.BARREL_SHIFTER      (BARREL_SHIFTER      ),
+		.TWO_CYCLE_COMPARE   (TWO_CYCLE_COMPARE   ),
+		.TWO_CYCLE_ALU       (TWO_CYCLE_ALU       ),
+		.COMPRESSED_ISA      (COMPRESSED_ISA      ),
+		.CATCH_MISALIGN      (CATCH_MISALIGN      ),
+		.CATCH_ILLINSN       (CATCH_ILLINSN       ),
+		.ENABLE_PCPI         (ENABLE_PCPI         ),
+		.ENABLE_MUL          (ENABLE_MUL          ),
+		.ENABLE_FAST_MUL     (ENABLE_FAST_MUL     ),
+		.ENABLE_DIV          (ENABLE_DIV          ),
+		.ENABLE_IRQ          (ENABLE_IRQ          ),
+		.ENABLE_IRQ_QREGS    (ENABLE_IRQ_QREGS    ),
+		.ENABLE_IRQ_TIMER    (ENABLE_IRQ_TIMER    ),
+		.ENABLE_TRACE        (ENABLE_TRACE        ),
+		.REGS_INIT_ZERO      (REGS_INIT_ZERO      ),
+		.MASKED_IRQ          (MASKED_IRQ          ),
+		.LATCHED_IRQ         (LATCHED_IRQ         ),
+		.PROGADDR_RESET      (PROGADDR_RESET      ),
+		.PROGADDR_IRQ        (PROGADDR_IRQ        ),
+		.STACKADDR           (STACKADDR           )
+	) picorv32_core (
+		.clk      (clk   ),
+		.resetn   (resetn),
+		.trap     (trap  ),
+
+		.mem_valid(mem_valid),
+		.mem_addr (mem_addr ),
+		.mem_wdata(mem_wdata),
+		.mem_wstrb(mem_wstrb),
+		.mem_instr(mem_instr),
+		.mem_ready(mem_ready),
+		.mem_rdata(mem_rdata),
+
+		.pcpi_valid(pcpi_valid),
+		.pcpi_insn (pcpi_insn ),
+		.pcpi_rs1  (pcpi_rs1  ),
+		.pcpi_rs2  (pcpi_rs2  ),
+		.pcpi_wr   (pcpi_wr   ),
+		.pcpi_rd   (pcpi_rd   ),
+		.pcpi_wait (pcpi_wait ),
+		.pcpi_ready(pcpi_ready),
+
+		.irq(irq),
+		.eoi(eoi),
+
+`ifdef RISCV_FORMAL
+		.rvfi_valid    (rvfi_valid    ),
+		.rvfi_order    (rvfi_order    ),
+		.rvfi_insn     (rvfi_insn     ),
+		.rvfi_trap     (rvfi_trap     ),
+		.rvfi_halt     (rvfi_halt     ),
+		.rvfi_intr     (rvfi_intr     ),
+		.rvfi_rs1_addr (rvfi_rs1_addr ),
+		.rvfi_rs2_addr (rvfi_rs2_addr ),
+		.rvfi_rs1_rdata(rvfi_rs1_rdata),
+		.rvfi_rs2_rdata(rvfi_rs2_rdata),
+		.rvfi_rd_addr  (rvfi_rd_addr  ),
+		.rvfi_rd_wdata (rvfi_rd_wdata ),
+		.rvfi_pc_rdata (rvfi_pc_rdata ),
+		.rvfi_pc_wdata (rvfi_pc_wdata ),
+		.rvfi_mem_addr (rvfi_mem_addr ),
+		.rvfi_mem_rmask(rvfi_mem_rmask),
+		.rvfi_mem_wmask(rvfi_mem_wmask),
+		.rvfi_mem_rdata(rvfi_mem_rdata),
+		.rvfi_mem_wdata(rvfi_mem_wdata),
+`endif
+
+		.trace_valid(trace_valid),
+		.trace_data (trace_data)
+	);
+endmodule
+
+
+/***************************************************************
+ * picorv32_axi_adapter
+ ***************************************************************/
+
+module picorv32_axi_adapter (
+	input clk, resetn,
+
+	// AXI4-lite master memory interface
+
+	output        mem_axi_awvalid,
+	input         mem_axi_awready,
+	output [31:0] mem_axi_awaddr,
+	output [ 2:0] mem_axi_awprot,
+
+	output        mem_axi_wvalid,
+	input         mem_axi_wready,
+	output [31:0] mem_axi_wdata,
+	output [ 3:0] mem_axi_wstrb,
+
+	input         mem_axi_bvalid,
+	output        mem_axi_bready,
+
+	output        mem_axi_arvalid,
+	input         mem_axi_arready,
+	output [31:0] mem_axi_araddr,
+	output [ 2:0] mem_axi_arprot,
+
+	input         mem_axi_rvalid,
+	output        mem_axi_rready,
+	input  [31:0] mem_axi_rdata,
+
+	// Native PicoRV32 memory interface
+
+	input         mem_valid,
+	input         mem_instr,
+	output        mem_ready,
+	input  [31:0] mem_addr,
+	input  [31:0] mem_wdata,
+	input  [ 3:0] mem_wstrb,
+	output [31:0] mem_rdata
+);
+	reg ack_awvalid;
+	reg ack_arvalid;
+	reg ack_wvalid;
+	reg xfer_done;
+
+	assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid;
+	assign mem_axi_awaddr = mem_addr;
+	assign mem_axi_awprot = 0;
+
+	assign mem_axi_arvalid = mem_valid && !mem_wstrb && !ack_arvalid;
+	assign mem_axi_araddr = mem_addr;
+	assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000;
+
+	assign mem_axi_wvalid = mem_valid && |mem_wstrb && !ack_wvalid;
+	assign mem_axi_wdata = mem_wdata;
+	assign mem_axi_wstrb = mem_wstrb;
+
+	assign mem_ready = mem_axi_bvalid || mem_axi_rvalid;
+	assign mem_axi_bready = mem_valid && |mem_wstrb;
+	assign mem_axi_rready = mem_valid && !mem_wstrb;
+	assign mem_rdata = mem_axi_rdata;
+
+	always @(posedge clk) begin
+		if (!resetn) begin
+			ack_awvalid <= 0;
+		end else begin
+			xfer_done <= mem_valid && mem_ready;
+			if (mem_axi_awready && mem_axi_awvalid)
+				ack_awvalid <= 1;
+			if (mem_axi_arready && mem_axi_arvalid)
+				ack_arvalid <= 1;
+			if (mem_axi_wready && mem_axi_wvalid)
+				ack_wvalid <= 1;
+			if (xfer_done || !mem_valid) begin
+				ack_awvalid <= 0;
+				ack_arvalid <= 0;
+				ack_wvalid <= 0;
+			end
+		end
+	end
+endmodule
+
+
+/***************************************************************
+ * picorv32_wb
+ ***************************************************************/
+
+module picorv32_wb #(
+	parameter [ 0:0] ENABLE_COUNTERS = 1,
+	parameter [ 0:0] ENABLE_COUNTERS64 = 1,
+	parameter [ 0:0] ENABLE_REGS_16_31 = 1,
+	parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
+	parameter [ 0:0] TWO_STAGE_SHIFT = 1,
+	parameter [ 0:0] BARREL_SHIFTER = 0,
+	parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
+	parameter [ 0:0] TWO_CYCLE_ALU = 0,
+	parameter [ 0:0] COMPRESSED_ISA = 0,
+	parameter [ 0:0] CATCH_MISALIGN = 1,
+	parameter [ 0:0] CATCH_ILLINSN = 1,
+	parameter [ 0:0] ENABLE_PCPI = 0,
+	parameter [ 0:0] ENABLE_MUL = 0,
+	parameter [ 0:0] ENABLE_FAST_MUL = 0,
+	parameter [ 0:0] ENABLE_DIV = 0,
+	parameter [ 0:0] ENABLE_IRQ = 0,
+	parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
+	parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
+	parameter [ 0:0] ENABLE_TRACE = 0,
+	parameter [ 0:0] REGS_INIT_ZERO = 0,
+	parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
+	parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
+	parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
+	parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
+	parameter [31:0] STACKADDR = 32'h ffff_ffff
+) (
+	output trap,
+
+	// Wishbone interfaces
+	input wb_rst_i,
+	input wb_clk_i,
+
+	output reg [31:0] wbm_adr_o,
+	output reg [31:0] wbm_dat_o,
+	input [31:0] wbm_dat_i,
+	output reg wbm_we_o,
+	output reg [3:0] wbm_sel_o,
+	output reg wbm_stb_o,
+	input wbm_ack_i,
+	output reg wbm_cyc_o,
+
+	// Pico Co-Processor Interface (PCPI)
+	output        pcpi_valid,
+	output [31:0] pcpi_insn,
+	output [31:0] pcpi_rs1,
+	output [31:0] pcpi_rs2,
+	input         pcpi_wr,
+	input  [31:0] pcpi_rd,
+	input         pcpi_wait,
+	input         pcpi_ready,
+
+	// IRQ interface
+	input  [31:0] irq,
+	output [31:0] eoi,
+
+`ifdef RISCV_FORMAL
+	output        rvfi_valid,
+	output [63:0] rvfi_order,
+	output [31:0] rvfi_insn,
+	output        rvfi_trap,
+	output        rvfi_halt,
+	output        rvfi_intr,
+	output [ 4:0] rvfi_rs1_addr,
+	output [ 4:0] rvfi_rs2_addr,
+	output [31:0] rvfi_rs1_rdata,
+	output [31:0] rvfi_rs2_rdata,
+	output [ 4:0] rvfi_rd_addr,
+	output [31:0] rvfi_rd_wdata,
+	output [31:0] rvfi_pc_rdata,
+	output [31:0] rvfi_pc_wdata,
+	output [31:0] rvfi_mem_addr,
+	output [ 3:0] rvfi_mem_rmask,
+	output [ 3:0] rvfi_mem_wmask,
+	output [31:0] rvfi_mem_rdata,
+	output [31:0] rvfi_mem_wdata,
+`endif
+
+	// Trace Interface
+	output        trace_valid,
+	output [35:0] trace_data,
+
+	output mem_instr
+);
+	wire        mem_valid;
+	wire [31:0] mem_addr;
+	wire [31:0] mem_wdata;
+	wire [ 3:0] mem_wstrb;
+	reg         mem_ready;
+	reg [31:0] mem_rdata;
+
+	wire clk;
+	wire resetn;
+
+	assign clk = wb_clk_i;
+	assign resetn = ~wb_rst_i;
+
+	picorv32 #(
+		.ENABLE_COUNTERS     (ENABLE_COUNTERS     ),
+		.ENABLE_COUNTERS64   (ENABLE_COUNTERS64   ),
+		.ENABLE_REGS_16_31   (ENABLE_REGS_16_31   ),
+		.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
+		.TWO_STAGE_SHIFT     (TWO_STAGE_SHIFT     ),
+		.BARREL_SHIFTER      (BARREL_SHIFTER      ),
+		.TWO_CYCLE_COMPARE   (TWO_CYCLE_COMPARE   ),
+		.TWO_CYCLE_ALU       (TWO_CYCLE_ALU       ),
+		.COMPRESSED_ISA      (COMPRESSED_ISA      ),
+		.CATCH_MISALIGN      (CATCH_MISALIGN      ),
+		.CATCH_ILLINSN       (CATCH_ILLINSN       ),
+		.ENABLE_PCPI         (ENABLE_PCPI         ),
+		.ENABLE_MUL          (ENABLE_MUL          ),
+		.ENABLE_FAST_MUL     (ENABLE_FAST_MUL     ),
+		.ENABLE_DIV          (ENABLE_DIV          ),
+		.ENABLE_IRQ          (ENABLE_IRQ          ),
+		.ENABLE_IRQ_QREGS    (ENABLE_IRQ_QREGS    ),
+		.ENABLE_IRQ_TIMER    (ENABLE_IRQ_TIMER    ),
+		.ENABLE_TRACE        (ENABLE_TRACE        ),
+		.REGS_INIT_ZERO      (REGS_INIT_ZERO      ),
+		.MASKED_IRQ          (MASKED_IRQ          ),
+		.LATCHED_IRQ         (LATCHED_IRQ         ),
+		.PROGADDR_RESET      (PROGADDR_RESET      ),
+		.PROGADDR_IRQ        (PROGADDR_IRQ        ),
+		.STACKADDR           (STACKADDR           )
+	) picorv32_core (
+		.clk      (clk   ),
+		.resetn   (resetn),
+		.trap     (trap  ),
+
+		.mem_valid(mem_valid),
+		.mem_addr (mem_addr ),
+		.mem_wdata(mem_wdata),
+		.mem_wstrb(mem_wstrb),
+		.mem_instr(mem_instr),
+		.mem_ready(mem_ready),
+		.mem_rdata(mem_rdata),
+
+		.pcpi_valid(pcpi_valid),
+		.pcpi_insn (pcpi_insn ),
+		.pcpi_rs1  (pcpi_rs1  ),
+		.pcpi_rs2  (pcpi_rs2  ),
+		.pcpi_wr   (pcpi_wr   ),
+		.pcpi_rd   (pcpi_rd   ),
+		.pcpi_wait (pcpi_wait ),
+		.pcpi_ready(pcpi_ready),
+
+		.irq(irq),
+		.eoi(eoi),
+
+`ifdef RISCV_FORMAL
+		.rvfi_valid    (rvfi_valid    ),
+		.rvfi_order    (rvfi_order    ),
+		.rvfi_insn     (rvfi_insn     ),
+		.rvfi_trap     (rvfi_trap     ),
+		.rvfi_halt     (rvfi_halt     ),
+		.rvfi_intr     (rvfi_intr     ),
+		.rvfi_rs1_addr (rvfi_rs1_addr ),
+		.rvfi_rs2_addr (rvfi_rs2_addr ),
+		.rvfi_rs1_rdata(rvfi_rs1_rdata),
+		.rvfi_rs2_rdata(rvfi_rs2_rdata),
+		.rvfi_rd_addr  (rvfi_rd_addr  ),
+		.rvfi_rd_wdata (rvfi_rd_wdata ),
+		.rvfi_pc_rdata (rvfi_pc_rdata ),
+		.rvfi_pc_wdata (rvfi_pc_wdata ),
+		.rvfi_mem_addr (rvfi_mem_addr ),
+		.rvfi_mem_rmask(rvfi_mem_rmask),
+		.rvfi_mem_wmask(rvfi_mem_wmask),
+		.rvfi_mem_rdata(rvfi_mem_rdata),
+		.rvfi_mem_wdata(rvfi_mem_wdata),
+`endif
+
+		.trace_valid(trace_valid),
+		.trace_data (trace_data)
+	);
+
+	localparam IDLE = 2'b00;
+	localparam WBSTART = 2'b01;
+	localparam WBEND = 2'b10;
+
+	reg [1:0] state;
+
+	wire we;
+	assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
+
+	always @(posedge wb_clk_i) begin
+		if (wb_rst_i) begin
+			wbm_adr_o <= 0;
+			wbm_dat_o <= 0;
+			wbm_we_o <= 0;
+			wbm_sel_o <= 0;
+			wbm_stb_o <= 0;
+			wbm_cyc_o <= 0;
+			state <= IDLE;
+		end else begin
+			case (state)
+				IDLE: begin
+					if (mem_valid) begin
+						wbm_adr_o <= mem_addr;
+						wbm_dat_o <= mem_wdata;
+						wbm_we_o <= we;
+						wbm_sel_o <= mem_wstrb;
+
+						wbm_stb_o <= 1'b1;
+						wbm_cyc_o <= 1'b1;
+						state <= WBSTART;
+					end else begin
+						mem_ready <= 1'b0;
+
+						wbm_stb_o <= 1'b0;
+						wbm_cyc_o <= 1'b0;
+						wbm_we_o <= 1'b0;
+					end
+				end
+				WBSTART:begin
+					if (wbm_ack_i) begin
+						mem_rdata <= wbm_dat_i;
+						mem_ready <= 1'b1;
+
+						state <= WBEND;
+
+						wbm_stb_o <= 1'b0;
+						wbm_cyc_o <= 1'b0;
+						wbm_we_o <= 1'b0;
+					end
+				end
+				WBEND: begin
+					mem_ready <= 1'b0;
+
+					state <= IDLE;
+				end
+				default:
+					state <= IDLE;
+			endcase
+		end
+	end
+endmodule
diff --git a/tests/functional/picorv32_tb.v b/tests/functional/picorv32_tb.v
new file mode 100644
index 00000000000..1404c2d8c27
--- /dev/null
+++ b/tests/functional/picorv32_tb.v
@@ -0,0 +1,62 @@
+module gold(
+	input wire clk,
+	output reg resetn,
+	output wire trap,
+	output wire mem_valid,
+	output wire mem_instr,
+	output wire mem_ready,
+	output wire [31:0] mem_addr,
+	output wire [31:0] mem_wdata,
+	output wire [31:0] mem_wstrb,
+	output wire [31:0] mem_rdata,
+);
+
+	initial resetn = 1'b0;
+	always @(posedge clk) resetn <= 1'b1;
+
+	reg [31:0] rom[0:15];
+
+	initial begin
+		rom[0]  = 32'h00200093;
+		rom[1]  = 32'h00200113;
+		rom[2]  = 32'h00111863;
+		rom[3]  = 32'h00102023;
+		rom[4]  = 32'h00108093;
+		rom[5]  = 32'hfe0008e3;
+		rom[6]  = 32'h00008193;
+		rom[7]  = 32'h402181b3;
+		rom[8]  = 32'hfe304ee3;
+		rom[9]  = 32'hfe0186e3;
+		rom[10] = 32'h00110113;
+		rom[11] = 32'hfc000ee3;
+	end
+
+	assign mem_ready = 1'b1;
+	assign mem_rdata = rom[mem_addr[5:2]];
+
+	wire pcpi_wr = 1'b0;
+	wire [31:0] pcpi_rd = 32'b0;
+	wire pcpi_wait = 1'b0;
+	wire pcpi_ready = 1'b0;
+
+	wire [31:0] irq = 32'b0;
+
+	picorv32 picorv32_i(
+		.clk(clk),
+		.resetn(resetn),
+		.trap(trap),
+		.mem_valid(mem_valid),
+		.mem_instr(mem_instr),
+		.mem_ready(mem_ready),
+		.mem_addr(mem_addr),
+		.mem_wdata(mem_wdata),
+		.mem_wstrb(mem_wstrb),
+		.mem_rdata(mem_rdata),
+		.pcpi_wr(pcpi_wr),
+		.pcpi_rd(pcpi_rd),
+		.pcpi_wait(pcpi_wait),
+		.pcpi_ready(pcpi_ready),
+		.irq(irq)
+	);
+
+endmodule
diff --git a/tests/functional/rtlil_cells.py b/tests/functional/rtlil_cells.py
index ed867b695b4..964d81ddf50 100644
--- a/tests/functional/rtlil_cells.py
+++ b/tests/functional/rtlil_cells.py
@@ -233,6 +233,16 @@ def write_rtlil_file(self, path, parameters):
 endmodule""".format(parameters['DATA_WIDTH'] - 1, parameters['ADDR_WIDTH'] - 1, 2**parameters['ADDR_WIDTH'] - 1))
         yosys_synth(verilog_file, path)
 
+class PicorvCell(BaseCell):
+    def __init__(self):
+        super().__init__("picorv", [], {}, {}, [()])
+        self.smt_max_steps = 50 # z3 is too slow for more steps
+    def write_rtlil_file(self, path, parameters):
+        from test_functional import yosys, base_path, quote
+        tb_file = base_path / 'tests/functional/picorv32_tb.v'
+        cpu_file = base_path / 'tests/functional/picorv32.v'
+        yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; flatten; write_rtlil {quote(path)}")
+
 binary_widths = [
     # try to cover extending A operand, extending B operand, extending/truncating result
     (16, 32, 48, True, True),
@@ -353,6 +363,7 @@ def write_rtlil_file(self, path, parameters):
 #    ("original_tag", ["A", "Y"]),
 #    ("future_ff", ["A", "Y"]),
 #    ("scopeinfo", []),
+    PicorvCell()
 ]
 
 def generate_test_cases(per_cell, rnd):
diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py
index 7bfe19fc494..107ca6862e5 100644
--- a/tests/functional/test_functional.py
+++ b/tests/functional/test_functional.py
@@ -63,6 +63,9 @@ def test_smt(cell, parameters, tmp_path, num_steps, rnd):
     vcd_functional_file = tmp_path / 'functional.vcd'
     vcd_yosys_sim_file = tmp_path / 'yosys.vcd'
 
+    if hasattr(cell, 'smt_max_steps'):
+        num_steps = min(num_steps, cell.smt_max_steps)
+
     cell.write_rtlil_file(rtlil_file, parameters)
     yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_smt2 {quote(smt_file)}")
     run(['z3', smt_file]) # check if output is valid smtlib before continuing

From f456761e88886053c503393fb2356afa45ef750f Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Tue, 13 Aug 2024 14:04:04 +0100
Subject: [PATCH 431/499] add sandia copyright notice to the functional backend

---
 backends/functional/cxx.cc            | 1 +
 backends/functional/cxx_runtime/sim.h | 1 +
 backends/functional/smtlib.cc         | 1 +
 backends/functional/test_generic.cc   | 1 +
 kernel/functional.cc                  | 1 +
 kernel/functional.h                   | 1 +
 6 files changed, 6 insertions(+)

diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index 19740777fb7..282eb8f673c 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -2,6 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
+ *  Copyright (C) 2024 National Technology and Engineering Solutions of Sandia, LLC
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h
index c50bc2cd818..941f067b930 100644
--- a/backends/functional/cxx_runtime/sim.h
+++ b/backends/functional/cxx_runtime/sim.h
@@ -2,6 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
+ *  Copyright (C) 2024 National Technology and Engineering Solutions of Sandia, LLC
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index ec9e6b24279..4e176c2fd3e 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -2,6 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
+ *  Copyright (C) 2024 National Technology and Engineering Solutions of Sandia, LLC
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc
index 1617d54c069..aab2260f177 100644
--- a/backends/functional/test_generic.cc
+++ b/backends/functional/test_generic.cc
@@ -2,6 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
+ *  Copyright (C) 2024 National Technology and Engineering Solutions of Sandia, LLC
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
diff --git a/kernel/functional.cc b/kernel/functional.cc
index eaae3f09808..1ece145e59f 100644
--- a/kernel/functional.cc
+++ b/kernel/functional.cc
@@ -2,6 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
+ *  Copyright (C) 2024 National Technology and Engineering Solutions of Sandia, LLC
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
diff --git a/kernel/functional.h b/kernel/functional.h
index f7ff08228b1..88a48dba9ec 100644
--- a/kernel/functional.h
+++ b/kernel/functional.h
@@ -2,6 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
+ *  Copyright (C) 2024 National Technology and Engineering Solutions of Sandia, LLC
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above

From 91e3773b51b905a00876b66e965fcd36a8cad79e Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Mon, 19 Aug 2024 16:56:08 +0200
Subject: [PATCH 432/499] Ensure signed constants are correctly parsed,
 represented, and exported in RTLIL. Add a test to check parsing and exporting

---
 backends/rtlil/rtlil_backend.cc         |  3 +++
 frontends/rtlil/rtlil_lexer.l           |  2 +-
 frontends/rtlil/rtlil_parser.y          | 16 +++++++++++++++-
 tests/various/rtlil_signed_attribute.ys | 10 ++++++++++
 4 files changed, 29 insertions(+), 2 deletions(-)
 create mode 100644 tests/various/rtlil_signed_attribute.ys

diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc
index 574eb3aaad1..032954d8cd6 100644
--- a/backends/rtlil/rtlil_backend.cc
+++ b/backends/rtlil/rtlil_backend.cc
@@ -51,6 +51,9 @@ void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int wi
 			}
 		}
 		f << stringf("%d'", width);
+		if (data.flags & RTLIL::CONST_FLAG_SIGNED) {
+			f << stringf("s");
+		}
 		if (data.is_fully_undef_x_only()) {
 			f << "x";
 		} else {
diff --git a/frontends/rtlil/rtlil_lexer.l b/frontends/rtlil/rtlil_lexer.l
index e164132167a..c374dd39575 100644
--- a/frontends/rtlil/rtlil_lexer.l
+++ b/frontends/rtlil/rtlil_lexer.l
@@ -88,7 +88,7 @@ USING_YOSYS_NAMESPACE
 "\\"[^ \t\r\n]+		{ rtlil_frontend_yylval.string = strdup(yytext); return TOK_ID; }
 "$"[^ \t\r\n]+		{ rtlil_frontend_yylval.string = strdup(yytext); return TOK_ID; }
 
-[0-9]+'[01xzm-]*	{ rtlil_frontend_yylval.string = strdup(yytext); return TOK_VALUE; }
+[0-9]+'s?[01xzm-]*	{ rtlil_frontend_yylval.string = strdup(yytext); return TOK_VALUE; }
 -?[0-9]+		{
 	char *end = nullptr;
 	errno = 0;
diff --git a/frontends/rtlil/rtlil_parser.y b/frontends/rtlil/rtlil_parser.y
index 7d99b2c4220..874e6fdd0c0 100644
--- a/frontends/rtlil/rtlil_parser.y
+++ b/frontends/rtlil/rtlil_parser.y
@@ -412,8 +412,16 @@ constant:
 	TOK_VALUE {
 		char *ep;
 		int width = strtol($1, &ep, 10);
+		bool is_signed = false;
+		if (*ep == '\'') {
+			ep++;
+		}
+		if (*ep == 's') {
+			is_signed = true;
+			ep++;
+		}
 		std::list<RTLIL::State> bits;
-		while (*(++ep) != 0) {
+		while (*ep != 0) {
 			RTLIL::State bit = RTLIL::Sx;
 			switch (*ep) {
 			case '0': bit = RTLIL::S0; break;
@@ -424,7 +432,9 @@ constant:
 			case 'm': bit = RTLIL::Sm; break;
 			}
 			bits.push_front(bit);
+			ep++;
 		}
+
 		if (bits.size() == 0)
 			bits.push_back(RTLIL::Sx);
 		while ((int)bits.size() < width) {
@@ -438,6 +448,10 @@ constant:
 		$$ = new RTLIL::Const;
 		for (auto it = bits.begin(); it != bits.end(); it++)
 			$$->bits.push_back(*it);
+		if (is_signed) {
+			$$->flags |= RTLIL::CONST_FLAG_SIGNED;
+			log("Setting SIGNED flag for constant with width %d\n", width);
+		}
 		free($1);
 	} |
 	TOK_INT {
diff --git a/tests/various/rtlil_signed_attribute.ys b/tests/various/rtlil_signed_attribute.ys
new file mode 100644
index 00000000000..900fe589fce
--- /dev/null
+++ b/tests/various/rtlil_signed_attribute.ys
@@ -0,0 +1,10 @@
+! mkdir -p temp
+read_rtlil <<EOT
+module \test
+  attribute \bottom_bound 3's101
+  wire width 3 output 1 \a
+  connect \a 3'001
+end
+EOT
+write_rtlil temp/rtlil_signed_attribute.il
+! grep -F -q "attribute \bottom_bound 3's101" temp/rtlil_signed_attribute.il

From 27c143225336661a22a517d3267b2f6f30977287 Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Mon, 19 Aug 2024 17:03:27 +0200
Subject: [PATCH 433/499] Remove log

---
 frontends/rtlil/rtlil_parser.y | 1 -
 1 file changed, 1 deletion(-)

diff --git a/frontends/rtlil/rtlil_parser.y b/frontends/rtlil/rtlil_parser.y
index 874e6fdd0c0..3d9862ebbe3 100644
--- a/frontends/rtlil/rtlil_parser.y
+++ b/frontends/rtlil/rtlil_parser.y
@@ -450,7 +450,6 @@ constant:
 			$$->bits.push_back(*it);
 		if (is_signed) {
 			$$->flags |= RTLIL::CONST_FLAG_SIGNED;
-			log("Setting SIGNED flag for constant with width %d\n", width);
 		}
 		free($1);
 	} |

From 2ffafadf2244c31b994546aef5e87f542cf993ee Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 22 Aug 2024 10:03:58 +1200
Subject: [PATCH 434/499] Docs: Add note on verific

Having a verific license does not provide access to the verific frontend.
---
 docs/source/using_yosys/more_scripting/load_design.rst | 8 ++++++++
 docs/source/using_yosys/synthesis/memory.rst           | 3 +++
 2 files changed, 11 insertions(+)

diff --git a/docs/source/using_yosys/more_scripting/load_design.rst b/docs/source/using_yosys/more_scripting/load_design.rst
index d64c50959bd..07c2bd8e58e 100644
--- a/docs/source/using_yosys/more_scripting/load_design.rst
+++ b/docs/source/using_yosys/more_scripting/load_design.rst
@@ -27,6 +27,14 @@ keyword: Frontends
 .. todo:: more info on other ``read_*`` commands, also is this the first time we
    mention verific?
 
+.. note::
+
+   The Verific frontend for Yosys, which provides the :cmd:ref:`verific`
+   command, requires the commercial `Tabby CAD Suite`_.  This is not the same as
+   simply having a Verific license when using Yosys.
+
+.. _Tabby CAD Suite: https://www.yosyshq.com/tabby-cad-datasheet
+
 Others:
 
 - :doc:`/cmd/read`
diff --git a/docs/source/using_yosys/synthesis/memory.rst b/docs/source/using_yosys/synthesis/memory.rst
index 0f5e1bd3010..8306c82b9fb 100644
--- a/docs/source/using_yosys/synthesis/memory.rst
+++ b/docs/source/using_yosys/synthesis/memory.rst
@@ -697,6 +697,9 @@ TDP with multiple read ports
 Patterns only supported with Verific
 ------------------------------------
 
+The following patterns are only supported when Yosys is built with the Verific
+front-end.
+
 Synchronous SDP with write-first behavior via blocking assignments
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 

From e18a2f1e27cb699c13556181e75d6d3c20683aa6 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 22 Aug 2024 10:03:58 +1200
Subject: [PATCH 435/499] Docs: Section/folder for yosys source details

Move test_suites page into said folder.
Placeholder page for building with verific.
---
 docs/source/getting_started/installation.rst   | 5 +++--
 docs/source/index.rst                          | 2 +-
 docs/source/yosys_source/build_verific.rst     | 2 ++
 docs/source/yosys_source/index.rst             | 7 +++++++
 docs/source/{ => yosys_source}/test_suites.rst | 0
 5 files changed, 13 insertions(+), 3 deletions(-)
 create mode 100644 docs/source/yosys_source/build_verific.rst
 create mode 100644 docs/source/yosys_source/index.rst
 rename docs/source/{ => yosys_source}/test_suites.rst (100%)

diff --git a/docs/source/getting_started/installation.rst b/docs/source/getting_started/installation.rst
index aea8b6a2dd2..76b5aa4faf6 100644
--- a/docs/source/getting_started/installation.rst
+++ b/docs/source/getting_started/installation.rst
@@ -138,7 +138,8 @@ To use a compiler different than the default, use:
 
 .. seealso:: 
 
-   Refer to :doc:`/test_suites` for details on testing Yosys once compiled.
+   Refer to :doc:`/yosys_source/test_suites` for details on testing Yosys once
+   compiled.
 
 Source tree and build system
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -193,7 +194,7 @@ directories:
 
 ``tests/``
    This directory contains the suite of unit tests and regression tests used by
-   Yosys.  See :doc:`/test_suites`.
+   Yosys.  See :doc:`/yosys_source/test_suites`.
 
 The top-level Makefile includes :file:`frontends/{*}/Makefile.inc`,
 :file:`passes/{*}/Makefile.inc` and :file:`backends/{*}/Makefile.inc`. So when
diff --git a/docs/source/index.rst b/docs/source/index.rst
index 582551f7486..dd8fc9e775c 100644
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@@ -40,6 +40,6 @@ available, go to :ref:`commandindex`.
    getting_started/index
    using_yosys/index
    yosys_internals/index
-   test_suites
+   yosys_source/index
 
    appendix
diff --git a/docs/source/yosys_source/build_verific.rst b/docs/source/yosys_source/build_verific.rst
new file mode 100644
index 00000000000..4cceb368ec1
--- /dev/null
+++ b/docs/source/yosys_source/build_verific.rst
@@ -0,0 +1,2 @@
+Compiling with Verific library
+------------------------------
diff --git a/docs/source/yosys_source/index.rst b/docs/source/yosys_source/index.rst
new file mode 100644
index 00000000000..e93b01d4f2c
--- /dev/null
+++ b/docs/source/yosys_source/index.rst
@@ -0,0 +1,7 @@
+Yosys source details
+--------------------
+
+.. toctree::
+
+   build_verific
+   test_suites
diff --git a/docs/source/test_suites.rst b/docs/source/yosys_source/test_suites.rst
similarity index 100%
rename from docs/source/test_suites.rst
rename to docs/source/yosys_source/test_suites.rst

From d97a243c22cd682e4e043bb50d45b4a7cde2ff15 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 22 Aug 2024 10:03:59 +1200
Subject: [PATCH 436/499] Docs: Intro to Yosys source section

---
 docs/source/yosys_internals/extending_yosys/extensions.rst | 2 ++
 docs/source/yosys_source/index.rst                         | 4 ++++
 2 files changed, 6 insertions(+)

diff --git a/docs/source/yosys_internals/extending_yosys/extensions.rst b/docs/source/yosys_internals/extending_yosys/extensions.rst
index f10c634b015..fa4ad51f8f4 100644
--- a/docs/source/yosys_internals/extending_yosys/extensions.rst
+++ b/docs/source/yosys_internals/extending_yosys/extensions.rst
@@ -8,6 +8,8 @@ Writing extensions
 
 .. todo:: update to use :file:`/code_examples/extensions/test*.log`
 
+.. todo:: should this be moved to yosys_source section?
+
 This chapter contains some bits and pieces of information about programming
 yosys extensions. Don't be afraid to ask questions on the YosysHQ Slack.
 
diff --git a/docs/source/yosys_source/index.rst b/docs/source/yosys_source/index.rst
index e93b01d4f2c..c1d8e3f18ba 100644
--- a/docs/source/yosys_source/index.rst
+++ b/docs/source/yosys_source/index.rst
@@ -1,6 +1,10 @@
 Yosys source details
 --------------------
 
+This section goes into additional detail on the Yosys source code and git
+repository.  This information is not needed for simply using Yosys, but may be
+of interest for developers looking to customise Yosys builds.
+
 .. toctree::
 
    build_verific

From 53b223f0dfa6cb86aacbccf8f99814b5a551f55b Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 22 Aug 2024 10:03:59 +1200
Subject: [PATCH 437/499] Docs: Initial build_verific.rst

From verific.md

Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
---
 docs/source/yosys_source/build_verific.rst | 158 ++++++++++++++++++++-
 1 file changed, 157 insertions(+), 1 deletion(-)

diff --git a/docs/source/yosys_source/build_verific.rst b/docs/source/yosys_source/build_verific.rst
index 4cceb368ec1..f8870e0c13b 100644
--- a/docs/source/yosys_source/build_verific.rst
+++ b/docs/source/yosys_source/build_verific.rst
@@ -1,2 +1,158 @@
 Compiling with Verific library
-------------------------------
+==============================
+
+YosysHQ creates build for TabbyCAD Suite that includes Verific with additional
+patches and our own extensions library. However, if you have licensed Verific
+library in source or binary form you can still compile Yosys and have at least
+partial support.
+
+Compile options
+---------------
+
+To enable Verific support ``ENABLE_VERIFIC`` has to be set to ``1`` and
+``VERIFIC_DIR`` needs to point to location where library is located.
+
+============== ========================== ===============================
+Parameter      Default                    Description
+============== ========================== ===============================
+ENABLE_VERIFIC 0                          Enable compilation with Verific
+VERIFIC_DIR    /usr/local/src/verific_lib Library and headers location
+============== ========================== ===============================
+
+Since there are multiple Verific library builds and they can have different
+features, there are compile options to select them.
+
+================================= ======= ===================================
+Parameter                         Default Description
+================================= ======= ===================================
+ENABLE_VERIFIC_SYSTEMVERILOG      1       SystemVerilog support
+ENABLE_VERIFIC_VHDL               1       VHDL support
+ENABLE_VERIFIC_HIER_TREE          1       Hierarchy tree support
+ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 1       YosysHQ specific extensions support
+ENABLE_VERIFIC_EDIF               0       EDIF support
+ENABLE_VERIFIC_LIBERTY            0       Liberty file support
+================================= ======= ===================================
+
+Supported build
+---------------
+
+Default options values are created in such way to represent supported build.
+This one includes SystemVerilog and VHDL support with RTL elaboration, hierarchy
+tree and static elaboration for both languages.
+
+Fully supported build includes additional YosysHQ patch that can be bought for
+**only** this Verific library configuration.
+
+NOTE: TabbyCAD builds also have additional EDIF and Liberty file support enabled
+as well. YosysHQ extensions library is only part of TabbyCAD as a product.
+
+Partialy supported builds
+-------------------------
+
+Note that these builds can be used with Yosys but will miss some of important
+features.
+
+1. SystemVerilog + RTL elaboration
+
+================================= =======
+Parameter                         Default
+================================= =======
+ENABLE_VERIFIC_SYSTEMVERILOG      1
+ENABLE_VERIFIC_VHDL               0
+ENABLE_VERIFIC_HIER_TREE          0
+ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 0
+================================= =======
+
+2. VHDL + RTL elaboration
+
+================================= =======
+Parameter                         Default
+================================= =======
+ENABLE_VERIFIC_SYSTEMVERILOG      0
+ENABLE_VERIFIC_VHDL               1
+ENABLE_VERIFIC_HIER_TREE          0
+ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 0
+================================= =======
+
+3. SystemVerilog + VHDL + RTL elaboration
+
+================================= =======
+Parameter                         Default
+================================= =======
+ENABLE_VERIFIC_SYSTEMVERILOG      1
+ENABLE_VERIFIC_VHDL               1
+ENABLE_VERIFIC_HIER_TREE          0
+ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 0
+================================= =======
+
+3. SystemVerilog + RTL elaboration + Static elaboration + Hier tree
+
+================================= =======
+Parameter                         Default
+================================= =======
+ENABLE_VERIFIC_SYSTEMVERILOG      1
+ENABLE_VERIFIC_VHDL               0
+ENABLE_VERIFIC_HIER_TREE          1
+ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 0
+================================= =======
+
+3. VHDL + RTL elaboration + Static elaboration + Hier tree
+
+================================= =======
+Parameter                         Default
+================================= =======
+ENABLE_VERIFIC_SYSTEMVERILOG      0
+ENABLE_VERIFIC_VHDL               1
+ENABLE_VERIFIC_HIER_TREE          1
+ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 0
+================================= =======
+
+4. SystemVerilog + VHDL + RTL elaboration + Static elaboration + Hier
+   tree
+
+================================= =======
+Parameter                         Default
+================================= =======
+ENABLE_VERIFIC_SYSTEMVERILOG      1
+ENABLE_VERIFIC_VHDL               1
+ENABLE_VERIFIC_HIER_TREE          1
+ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 0
+================================= =======
+
+NOTE:
+
+In case your Verific build have EDIF and/or Liberty support, you can enable
+those options, these are not mentioned above for simplification and since they
+are disabled by default.
+
+NOTE: To be able to compile Yosys+Verific you need Verific library that have at
+least one of HDL languages support with RTL elaboration enabled. Please note
+that without YosysHQ specific extensions of Verific library, support is limited.
+
+Verific Features that should be enabled in your Verific library
+===============================================================
+
+Please be aware that next Verific configuration build parameter needs to be
+enabled in order to create fully supported build.
+
+::
+
+   database/DBCompileFlags.h:
+       DB_PRESERVE_INITIAL_VALUE
+
+Additional features included with Yosys Verific patch
+=====================================================
+
+New cells
+---------
+
+============== ===========
+Cell           Description
+============== ===========
+$initstate    
+$set_tag      
+$get_tag      
+$overwrite_tag
+$original_tag 
+$future_ff    
+============== ===========

From 8e618cac450ea9c9b0855ba8dba0b1ee1eb3534e Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 22 Aug 2024 10:03:59 +1200
Subject: [PATCH 438/499] Docs: Update build_verific.rst

Move patch section to top.
Add todos for open questions.
Reformat partially supported builds into a single table.
General language tidy up/reflow.
---
 docs/source/yosys_source/build_verific.rst | 208 +++++++++------------
 1 file changed, 89 insertions(+), 119 deletions(-)

diff --git a/docs/source/yosys_source/build_verific.rst b/docs/source/yosys_source/build_verific.rst
index f8870e0c13b..626d045de13 100644
--- a/docs/source/yosys_source/build_verific.rst
+++ b/docs/source/yosys_source/build_verific.rst
@@ -1,16 +1,48 @@
 Compiling with Verific library
 ==============================
 
-YosysHQ creates build for TabbyCAD Suite that includes Verific with additional
-patches and our own extensions library. However, if you have licensed Verific
-library in source or binary form you can still compile Yosys and have at least
-partial support.
+The easiest way to get Yosys with Verific support is to `contact YosysHQ`_ for a
+`Tabby CAD Suite`_ evaluation license and download link.  The TabbyCAD Suite
+includes additional patches and a custom extensions library in order to get the
+most out of the Verific parser when using Yosys.
+
+If you already have a license for the Verific parser, in either source or binary
+form, you may be able to compile Yosys with partial Verific support yourself.
+
+.. _contact YosysHQ : https://www.yosyshq.com/contact
+.. _Tabby CAD Suite: https://www.yosyshq.com/tabby-cad-datasheet
+
+The Yosys-Verific patch
+-----------------------
+
+.. todo:: Fill out section on Yosys-Verific patch
+
+* Yosys-Verific patch developed for best integration
+* Needed for some of the formal verification front-end tools
+* `contact YosysHQ`_ about licensing this patch for your own Yosys builds
+* Unable to provide support for builds without this patch
+
+New cells
+~~~~~~~~~
+
+============== ===========
+Cell           Description
+============== ===========
+$initstate    
+$set_tag      
+$get_tag      
+$overwrite_tag
+$original_tag 
+$future_ff    
+============== ===========
+
+.. todo:: (sub)section on features only available with TabbyCAD
 
 Compile options
 ---------------
 
 To enable Verific support ``ENABLE_VERIFIC`` has to be set to ``1`` and
-``VERIFIC_DIR`` needs to point to location where library is located.
+``VERIFIC_DIR`` needs to point to the location where the library is located.
 
 ============== ========================== ===============================
 Parameter      Default                    Description
@@ -34,125 +66,63 @@ ENABLE_VERIFIC_LIBERTY            0       Liberty file support
 ================================= ======= ===================================
 
 Supported build
----------------
-
-Default options values are created in such way to represent supported build.
-This one includes SystemVerilog and VHDL support with RTL elaboration, hierarchy
-tree and static elaboration for both languages.
-
-Fully supported build includes additional YosysHQ patch that can be bought for
-**only** this Verific library configuration.
-
-NOTE: TabbyCAD builds also have additional EDIF and Liberty file support enabled
-as well. YosysHQ extensions library is only part of TabbyCAD as a product.
-
-Partialy supported builds
--------------------------
-
-Note that these builds can be used with Yosys but will miss some of important
-features.
-
-1. SystemVerilog + RTL elaboration
-
-================================= =======
-Parameter                         Default
-================================= =======
-ENABLE_VERIFIC_SYSTEMVERILOG      1
-ENABLE_VERIFIC_VHDL               0
-ENABLE_VERIFIC_HIER_TREE          0
-ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 0
-================================= =======
-
-2. VHDL + RTL elaboration
-
-================================= =======
-Parameter                         Default
-================================= =======
-ENABLE_VERIFIC_SYSTEMVERILOG      0
-ENABLE_VERIFIC_VHDL               1
-ENABLE_VERIFIC_HIER_TREE          0
-ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 0
-================================= =======
-
-3. SystemVerilog + VHDL + RTL elaboration
-
-================================= =======
-Parameter                         Default
-================================= =======
-ENABLE_VERIFIC_SYSTEMVERILOG      1
-ENABLE_VERIFIC_VHDL               1
-ENABLE_VERIFIC_HIER_TREE          0
-ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 0
-================================= =======
-
-3. SystemVerilog + RTL elaboration + Static elaboration + Hier tree
-
-================================= =======
-Parameter                         Default
-================================= =======
-ENABLE_VERIFIC_SYSTEMVERILOG      1
-ENABLE_VERIFIC_VHDL               0
-ENABLE_VERIFIC_HIER_TREE          1
-ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 0
-================================= =======
-
-3. VHDL + RTL elaboration + Static elaboration + Hier tree
-
-================================= =======
-Parameter                         Default
-================================= =======
-ENABLE_VERIFIC_SYSTEMVERILOG      0
-ENABLE_VERIFIC_VHDL               1
-ENABLE_VERIFIC_HIER_TREE          1
-ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 0
-================================= =======
-
-4. SystemVerilog + VHDL + RTL elaboration + Static elaboration + Hier
-   tree
-
-================================= =======
-Parameter                         Default
-================================= =======
-ENABLE_VERIFIC_SYSTEMVERILOG      1
-ENABLE_VERIFIC_VHDL               1
-ENABLE_VERIFIC_HIER_TREE          1
-ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 0
-================================= =======
-
-NOTE:
-
-In case your Verific build have EDIF and/or Liberty support, you can enable
-those options, these are not mentioned above for simplification and since they
-are disabled by default.
-
-NOTE: To be able to compile Yosys+Verific you need Verific library that have at
-least one of HDL languages support with RTL elaboration enabled. Please note
-that without YosysHQ specific extensions of Verific library, support is limited.
+~~~~~~~~~~~~~~~
+
+The default values for options represent the only fully supported configuration
+of Yosys with Verific. This build includes SystemVerilog and VHDL support with
+RTL elaboration, hierarchy tree and static elaboration for both languages.  This
+is the only configuration for which the Yosys-Verific patch is available.
+
+.. note:: 
+
+   TabbyCAD builds also have additional EDIF and Liberty file support enabled.
+   YosysHQ extensions library is only part of TabbyCAD as a product.
+
+.. todo:: is "YosysHQ extensions library" == "YosysHQ specific extensions support" ?
+
+   If not, they need to be better distinguished.  If they are, then how is it
+   possible for someone to build the supported configuration?
+
+Partially supported builds
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+To be able to compile Yosys with Verific, the Verific library must have support
+for at least one HDL language with RTL elaboration enabled.  The following table
+lists a series of build configurations which are possible, but only provide a
+limited subset of features.  Please note that support is limited without YosysHQ
+specific extensions of Verific library.
+
++--------------------------------------------------------------------------+---------------+------+-----------+--------------------+
+|                                                                          | Configuration values beginning with ENABLE_VERIFIC\_  |
++--------------------------------------------------------------------------+---------------+------+-----------+--------------------+
+| Features                                                                 | SYSTEMVERILOG | VHDL | HIER_TREE | YOSYSHQ_EXTENSIONS |
++==========================================================================+===============+======+===========+====================+
+| SystemVerilog + RTL elaboration                                          |             1 |    0 |         0 |                  0 |
++--------------------------------------------------------------------------+---------------+------+-----------+--------------------+
+| VHDL + RTL elaboration                                                   |             0 |    1 |         0 |                  0 |
++--------------------------------------------------------------------------+---------------+------+-----------+--------------------+
+| SystemVerilog + VHDL + RTL elaboration                                   |             1 |    1 |         0 |                  0 |
++--------------------------------------------------------------------------+---------------+------+-----------+--------------------+
+| SystemVerilog + RTL elaboration + Static elaboration + Hier tree         |             1 |    0 |         1 |                  0 |
++--------------------------------------------------------------------------+---------------+------+-----------+--------------------+
+| VHDL + RTL elaboration + Static elaboration + Hier tree                  |             0 |    1 |         1 |                  0 |
++--------------------------------------------------------------------------+---------------+------+-----------+--------------------+
+| SystemVerilog + VHDL + RTL elaboration + Static elaboration + Hier tree  |             1 |    1 |         1 |                  0 |
++--------------------------------------------------------------------------+---------------+------+-----------+--------------------+
+
+.. note::
+
+   In case your Verific build has EDIF and/or Liberty support, you can enable
+   those options. These are not mentioned above for simplification and since
+   they are disabled by default.
 
 Verific Features that should be enabled in your Verific library
-===============================================================
+---------------------------------------------------------------
 
-Please be aware that next Verific configuration build parameter needs to be
-enabled in order to create fully supported build.
+Please be aware that the following Verific configuration build parameter needs
+to be enabled in order to create the fully supported build.
 
 ::
 
    database/DBCompileFlags.h:
        DB_PRESERVE_INITIAL_VALUE
-
-Additional features included with Yosys Verific patch
-=====================================================
-
-New cells
----------
-
-============== ===========
-Cell           Description
-============== ===========
-$initstate    
-$set_tag      
-$get_tag      
-$overwrite_tag
-$original_tag 
-$future_ff    
-============== ===========

From 00bb3b6fc2f903d7eb32ae978cff2abd11832cae Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 22 Aug 2024 10:03:59 +1200
Subject: [PATCH 439/499] Docs: Merge yosys_source into extending_yosys

Move abc_flow content into synthesis/abc document.
---
 docs/source/using_yosys/synthesis/abc.rst     | 84 ++++++++++++++++++-
 .../extending_yosys/abc_flow.rst              | 76 -----------------
 .../extending_yosys}/build_verific.rst        |  0
 .../yosys_internals/extending_yosys/index.rst | 11 ++-
 .../extending_yosys}/test_suites.rst          |  0
 docs/source/yosys_source/index.rst            | 11 ---
 6 files changed, 88 insertions(+), 94 deletions(-)
 delete mode 100644 docs/source/yosys_internals/extending_yosys/abc_flow.rst
 rename docs/source/{yosys_source => yosys_internals/extending_yosys}/build_verific.rst (100%)
 rename docs/source/{yosys_source => yosys_internals/extending_yosys}/test_suites.rst (100%)
 delete mode 100644 docs/source/yosys_source/index.rst

diff --git a/docs/source/using_yosys/synthesis/abc.rst b/docs/source/using_yosys/synthesis/abc.rst
index 928b320186d..fca9ddec063 100644
--- a/docs/source/using_yosys/synthesis/abc.rst
+++ b/docs/source/using_yosys/synthesis/abc.rst
@@ -1,5 +1,5 @@
 The ABC toolbox
----------------
+===============
 
 .. role:: yoscrypt(code)
    :language: yoscrypt
@@ -21,7 +21,7 @@ global view of the mapping problem.
 .. _ABC: https://github.com/berkeley-abc/abc
 
 ABC: the unit delay model, simple and efficient
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------------------
 
 The :cmd:ref:`abc` pass uses a highly simplified view of an FPGA:
 
@@ -66,7 +66,7 @@ But this approach has drawbacks, too:
   before clock edge) which affect the delay of a path.
 
 ABC9: the generalised delay model, realistic and flexible
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------------------------
 
 ABC9 uses a more detailed and accurate model of an FPGA:
 
@@ -101,3 +101,81 @@ optimise better around those boxes, and also permute inputs to give the critical
 path the fastest inputs.
 
 .. todo:: more about logic minimization & register balancing et al with ABC
+
+Setting up a flow for ABC9
+--------------------------
+
+Much of the configuration comes from attributes and ``specify`` blocks in
+Verilog simulation models.
+
+``specify`` syntax
+~~~~~~~~~~~~~~~~~~
+
+Since ``specify`` is a relatively obscure part of the Verilog standard, a quick
+guide to the syntax:
+
+.. code-block:: verilog
+
+   specify                           // begins a specify block
+     (A => B) = 123;                 // simple combinational path from A to B with a delay of 123.
+     (A *> B) = 123;                 // simple combinational path from A to all bits of B with a delay of 123 for all.
+     if (FOO) (A => B) = 123;        // paths may apply under specific conditions.
+     (posedge CLK => (Q : D)) = 123; // combinational path triggered on the positive edge of CLK; used for clock-to-Q arrival paths.
+     $setup(A, posedge CLK, 123);    // setup constraint for an input relative to a clock.
+   endspecify                        // ends a specify block
+
+By convention, all delays in ``specify`` blocks are in integer picoseconds.
+Files containing ``specify`` blocks should be read with the ``-specify`` option
+to :cmd:ref:`read_verilog` so that they aren't skipped.
+
+LUTs
+^^^^
+
+LUTs need to be annotated with an ``(* abc9_lut=N *)`` attribute, where ``N`` is
+the relative area of that LUT model. For example, if an architecture can combine
+LUTs to produce larger LUTs, then the combined LUTs would have increasingly
+larger ``N``. Conversely, if an architecture can split larger LUTs into smaller
+LUTs, then the smaller LUTs would have smaller ``N``.
+
+LUTs are generally specified with simple combinational paths from the LUT inputs
+to the LUT output.
+
+DFFs
+^^^^
+
+DFFs should be annotated with an ``(* abc9_flop *)`` attribute, however ABC9 has
+some specific requirements for this to be valid: - the DFF must initialise to
+zero (consider using :cmd:ref:`dfflegalize` to ensure this). - the DFF cannot
+have any asynchronous resets/sets (see the simplification idiom and the Boxes
+section for what to do here).
+
+It is worth noting that in pure ``abc9`` mode, only the setup and arrival times
+are passed to ABC9 (specifically, they are modelled as buffers with the given
+delay). In ``abc9 -dff``, the flop itself is passed to ABC9, permitting
+sequential optimisations.
+
+Some vendors have universal DFF models which include async sets/resets even when
+they're unused. Therefore *the simplification idiom* exists to handle this: by
+using a ``techmap`` file to discover flops which have a constant driver to those
+asynchronous controls, they can be mapped into an intermediate, simplified flop
+which qualifies as an ``(* abc9_flop *)``, ran through :cmd:ref:`abc9`, and then
+mapped back to the original flop. This is used in :cmd:ref:`synth_intel_alm` and
+:cmd:ref:`synth_quicklogic` for the PolarPro3.
+
+DFFs are usually specified to have setup constraints against the clock on the
+input signals, and an arrival time for the ``Q`` output.
+
+Boxes
+^^^^^
+
+A "box" is a purely-combinational piece of hard logic. If the logic is exposed
+to ABC9, it's a "whitebox", otherwise it's a "blackbox". Carry chains would be
+best implemented as whiteboxes, but a DSP would be best implemented as a
+blackbox (multipliers are too complex to easily work with). LUT RAMs can be
+implemented as whiteboxes too.
+
+Boxes are arguably the biggest advantage that ABC9 has over ABC: by being aware
+of carry chains and DSPs, it avoids optimising for a path that isn't the actual
+critical path, while the generally-longer paths result in ABC9 being able to
+reduce design area by mapping other logic to larger-but-slower cells.
+
diff --git a/docs/source/yosys_internals/extending_yosys/abc_flow.rst b/docs/source/yosys_internals/extending_yosys/abc_flow.rst
deleted file mode 100644
index 86afd3336f6..00000000000
--- a/docs/source/yosys_internals/extending_yosys/abc_flow.rst
+++ /dev/null
@@ -1,76 +0,0 @@
-Setting up a flow for ABC9
---------------------------
-
-Much of the configuration comes from attributes and ``specify`` blocks in
-Verilog simulation models.
-
-``specify`` syntax
-~~~~~~~~~~~~~~~~~~
-
-Since ``specify`` is a relatively obscure part of the Verilog standard, a quick
-guide to the syntax:
-
-.. code-block:: verilog
-
-   specify                           // begins a specify block
-     (A => B) = 123;                 // simple combinational path from A to B with a delay of 123.
-     (A *> B) = 123;                 // simple combinational path from A to all bits of B with a delay of 123 for all.
-     if (FOO) (A => B) = 123;        // paths may apply under specific conditions.
-     (posedge CLK => (Q : D)) = 123; // combinational path triggered on the positive edge of CLK; used for clock-to-Q arrival paths.
-     $setup(A, posedge CLK, 123);    // setup constraint for an input relative to a clock.
-   endspecify                        // ends a specify block
-
-By convention, all delays in ``specify`` blocks are in integer picoseconds.
-Files containing ``specify`` blocks should be read with the ``-specify`` option
-to :cmd:ref:`read_verilog` so that they aren't skipped.
-
-LUTs
-^^^^
-
-LUTs need to be annotated with an ``(* abc9_lut=N *)`` attribute, where ``N`` is
-the relative area of that LUT model. For example, if an architecture can combine
-LUTs to produce larger LUTs, then the combined LUTs would have increasingly
-larger ``N``. Conversely, if an architecture can split larger LUTs into smaller
-LUTs, then the smaller LUTs would have smaller ``N``.
-
-LUTs are generally specified with simple combinational paths from the LUT inputs
-to the LUT output.
-
-DFFs
-^^^^
-
-DFFs should be annotated with an ``(* abc9_flop *)`` attribute, however ABC9 has
-some specific requirements for this to be valid: - the DFF must initialise to
-zero (consider using :cmd:ref:`dfflegalize` to ensure this). - the DFF cannot
-have any asynchronous resets/sets (see the simplification idiom and the Boxes
-section for what to do here).
-
-It is worth noting that in pure ``abc9`` mode, only the setup and arrival times
-are passed to ABC9 (specifically, they are modelled as buffers with the given
-delay). In ``abc9 -dff``, the flop itself is passed to ABC9, permitting
-sequential optimisations.
-
-Some vendors have universal DFF models which include async sets/resets even when
-they're unused. Therefore *the simplification idiom* exists to handle this: by
-using a ``techmap`` file to discover flops which have a constant driver to those
-asynchronous controls, they can be mapped into an intermediate, simplified flop
-which qualifies as an ``(* abc9_flop *)``, ran through :cmd:ref:`abc9`, and then
-mapped back to the original flop. This is used in :cmd:ref:`synth_intel_alm` and
-:cmd:ref:`synth_quicklogic` for the PolarPro3.
-
-DFFs are usually specified to have setup constraints against the clock on the
-input signals, and an arrival time for the ``Q`` output.
-
-Boxes
-^^^^^
-
-A "box" is a purely-combinational piece of hard logic. If the logic is exposed
-to ABC9, it's a "whitebox", otherwise it's a "blackbox". Carry chains would be
-best implemented as whiteboxes, but a DSP would be best implemented as a
-blackbox (multipliers are too complex to easily work with). LUT RAMs can be
-implemented as whiteboxes too.
-
-Boxes are arguably the biggest advantage that ABC9 has over ABC: by being aware
-of carry chains and DSPs, it avoids optimising for a path that isn't the actual
-critical path, while the generally-longer paths result in ABC9 being able to
-reduce design area by mapping other logic to larger-but-slower cells.
diff --git a/docs/source/yosys_source/build_verific.rst b/docs/source/yosys_internals/extending_yosys/build_verific.rst
similarity index 100%
rename from docs/source/yosys_source/build_verific.rst
rename to docs/source/yosys_internals/extending_yosys/build_verific.rst
diff --git a/docs/source/yosys_internals/extending_yosys/index.rst b/docs/source/yosys_internals/extending_yosys/index.rst
index c2dc6cd2b8b..2a4d2dfef04 100644
--- a/docs/source/yosys_internals/extending_yosys/index.rst
+++ b/docs/source/yosys_internals/extending_yosys/index.rst
@@ -1,11 +1,14 @@
-Extending Yosys
----------------
+Working with the Yosys codebase
+-------------------------------
 
-.. todo:: brief overview for the extending Yosys index
+This section goes into additional detail on the Yosys source code and git
+repository.  This information is not needed for simply using Yosys, but may be
+of interest for developers looking to customise Yosys builds.
 
 .. toctree::
    :maxdepth: 3
 
    extensions
-   abc_flow
+   build_verific
+   test_suites
 
diff --git a/docs/source/yosys_source/test_suites.rst b/docs/source/yosys_internals/extending_yosys/test_suites.rst
similarity index 100%
rename from docs/source/yosys_source/test_suites.rst
rename to docs/source/yosys_internals/extending_yosys/test_suites.rst
diff --git a/docs/source/yosys_source/index.rst b/docs/source/yosys_source/index.rst
deleted file mode 100644
index c1d8e3f18ba..00000000000
--- a/docs/source/yosys_source/index.rst
+++ /dev/null
@@ -1,11 +0,0 @@
-Yosys source details
---------------------
-
-This section goes into additional detail on the Yosys source code and git
-repository.  This information is not needed for simply using Yosys, but may be
-of interest for developers looking to customise Yosys builds.
-
-.. toctree::
-
-   build_verific
-   test_suites

From cfba26ca8ba335ee3a66f69994ab008effd89ead Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 22 Aug 2024 10:03:59 +1200
Subject: [PATCH 440/499] Docs: Verific progress

---
 .../extending_yosys/build_verific.rst         | 80 +++++++++----------
 1 file changed, 38 insertions(+), 42 deletions(-)

diff --git a/docs/source/yosys_internals/extending_yosys/build_verific.rst b/docs/source/yosys_internals/extending_yosys/build_verific.rst
index 626d045de13..3ae1925b632 100644
--- a/docs/source/yosys_internals/extending_yosys/build_verific.rst
+++ b/docs/source/yosys_internals/extending_yosys/build_verific.rst
@@ -15,28 +15,19 @@ form, you may be able to compile Yosys with partial Verific support yourself.
 The Yosys-Verific patch
 -----------------------
 
-.. todo:: Fill out section on Yosys-Verific patch
-
-* Yosys-Verific patch developed for best integration
+* To provide the best integration between Yosys and Verific, some features are
+  required to be patched into the Verific library.  
+* Synthesis from RTL may be possible without this patch, however we are unable
+  to provide support for any Yosys+Verific builds without it.
 * Needed for some of the formal verification front-end tools
-* `contact YosysHQ`_ about licensing this patch for your own Yosys builds
-* Unable to provide support for builds without this patch
-
-New cells
-~~~~~~~~~
+* `contact YosysHQ`_ about licensing this patch for your own Yosys builds.
 
-============== ===========
-Cell           Description
-============== ===========
-$initstate    
-$set_tag      
-$get_tag      
-$overwrite_tag
-$original_tag 
-$future_ff    
-============== ===========
+.. warning::
 
-.. todo:: (sub)section on features only available with TabbyCAD
+   Some of the formal verification front-end tools may not be fully supported
+   without the full TabbyCAD suite.  If you are wanting to use these tools, make
+   sure to `contact YosysHQ`_ and ask us if the Yosys-Verific patch is right for
+   you.
 
 Compile options
 ---------------
@@ -65,23 +56,39 @@ ENABLE_VERIFIC_EDIF               0       EDIF support
 ENABLE_VERIFIC_LIBERTY            0       Liberty file support
 ================================= ======= ===================================
 
-Supported build
-~~~~~~~~~~~~~~~
+Required Verific features
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The following features, along with their corresponding Yosys build parameters,
+are required for the Yosys-Verific patch:
+
+* RTL elaboration with
+   * SystemVerilog with ENABLE_VERIFIC_SYSTEMVERILOG, and/or
+   * VHDL support with ENABLE_VERIFIC_VHDL.
+* Hierarchy tree support and static elaboration with ENABLE_VERIFIC_HIER_TREE.
+
+Please be aware that the following Verific configuration build parameter needs
+to be enabled in order to create the fully supported build:
+
+::
+
+   database/DBCompileFlags.h:
+       DB_PRESERVE_INITIAL_VALUE
 
-The default values for options represent the only fully supported configuration
-of Yosys with Verific. This build includes SystemVerilog and VHDL support with
-RTL elaboration, hierarchy tree and static elaboration for both languages.  This
-is the only configuration for which the Yosys-Verific patch is available.
+.. note::
 
-.. note:: 
+   Yosys+Verific builds may compile without these features, but we provide no
+   guarantees and cannot offer support if they are disabled or the Yosys-Verific
+   patch is not used.
 
-   TabbyCAD builds also have additional EDIF and Liberty file support enabled.
-   YosysHQ extensions library is only part of TabbyCAD as a product.
+Optional Verific features
+~~~~~~~~~~~~~~~~~~~~~~~~~
 
-.. todo:: is "YosysHQ extensions library" == "YosysHQ specific extensions support" ?
+The following Verific features are available with TabbyCAD and can be enabled in
+Yosys builds:
 
-   If not, they need to be better distinguished.  If they are, then how is it
-   possible for someone to build the supported configuration?
+* EDIF support with ENABLE_VERIFIC_EDIF, and
+* Liberty file support with ENABLE_VERIFIC_LIBERTY.
 
 Partially supported builds
 ~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -115,14 +122,3 @@ specific extensions of Verific library.
    In case your Verific build has EDIF and/or Liberty support, you can enable
    those options. These are not mentioned above for simplification and since
    they are disabled by default.
-
-Verific Features that should be enabled in your Verific library
----------------------------------------------------------------
-
-Please be aware that the following Verific configuration build parameter needs
-to be enabled in order to create the fully supported build.
-
-::
-
-   database/DBCompileFlags.h:
-       DB_PRESERVE_INITIAL_VALUE

From 88bb785dcd729b5df31fab4462269d86be72122d Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 22 Aug 2024 10:03:59 +1200
Subject: [PATCH 441/499] Docs: Verific but with sentences

---
 .../extending_yosys/build_verific.rst         | 19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/docs/source/yosys_internals/extending_yosys/build_verific.rst b/docs/source/yosys_internals/extending_yosys/build_verific.rst
index 3ae1925b632..ea21fda0868 100644
--- a/docs/source/yosys_internals/extending_yosys/build_verific.rst
+++ b/docs/source/yosys_internals/extending_yosys/build_verific.rst
@@ -15,18 +15,17 @@ form, you may be able to compile Yosys with partial Verific support yourself.
 The Yosys-Verific patch
 -----------------------
 
-* To provide the best integration between Yosys and Verific, some features are
-  required to be patched into the Verific library.  
-* Synthesis from RTL may be possible without this patch, however we are unable
-  to provide support for any Yosys+Verific builds without it.
-* Needed for some of the formal verification front-end tools
-* `contact YosysHQ`_ about licensing this patch for your own Yosys builds.
+YosysHQ maintains and develops a patch for Verific in order to better integrate
+with Yosys and to provide features required by some of the formal verification
+front-end tools.  Synthesis from RTL may be possible without this patch, however
+we are unable to provide support for any Yosys+Verific builds without it.  To
+license this patch for your own Yosys builds, `contact YosysHQ`_.
 
 .. warning::
 
    Some of the formal verification front-end tools may not be fully supported
-   without the full TabbyCAD suite.  If you are wanting to use these tools, make
-   sure to `contact YosysHQ`_ and ask us if the Yosys-Verific patch is right for
+   without the full TabbyCAD suite.  If you are wanting to use these tools,
+   including SBY, make sure to ask us if the Yosys-Verific patch is right for
    you.
 
 Compile options
@@ -93,6 +92,10 @@ Yosys builds:
 Partially supported builds
 ~~~~~~~~~~~~~~~~~~~~~~~~~~
 
+.. todo:: still unclear on the purpose of this section.
+
+   Are these the configurations we have tested as being able to compile?
+
 To be able to compile Yosys with Verific, the Verific library must have support
 for at least one HDL language with RTL elaboration enabled.  The following table
 lists a series of build configurations which are possible, but only provide a

From 36ad07e1d5bf1e4ca9759062555600182ae7f4b5 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 22 Aug 2024 10:03:59 +1200
Subject: [PATCH 442/499] Docs: Update build_verific

Clarify partially supported builds section.
Update parameter defaults.
Include note on finding compile options with `yosys-config`.
Fix remaining references to `/yosys_source/`.
---
 docs/source/getting_started/installation.rst      |  6 +++---
 docs/source/index.rst                             |  1 -
 .../extending_yosys/build_verific.rst             | 15 +++++++++++----
 3 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/docs/source/getting_started/installation.rst b/docs/source/getting_started/installation.rst
index 76b5aa4faf6..4d1a2f36a58 100644
--- a/docs/source/getting_started/installation.rst
+++ b/docs/source/getting_started/installation.rst
@@ -138,8 +138,8 @@ To use a compiler different than the default, use:
 
 .. seealso:: 
 
-   Refer to :doc:`/yosys_source/test_suites` for details on testing Yosys once
-   compiled.
+   Refer to :doc:`/yosys_internals/extending_yosys/test_suites` for details on
+   testing Yosys once compiled.
 
 Source tree and build system
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -194,7 +194,7 @@ directories:
 
 ``tests/``
    This directory contains the suite of unit tests and regression tests used by
-   Yosys.  See :doc:`/yosys_source/test_suites`.
+   Yosys.  See :doc:`/yosys_internals/extending_yosys/test_suites`.
 
 The top-level Makefile includes :file:`frontends/{*}/Makefile.inc`,
 :file:`passes/{*}/Makefile.inc` and :file:`backends/{*}/Makefile.inc`. So when
diff --git a/docs/source/index.rst b/docs/source/index.rst
index dd8fc9e775c..106ddbab86b 100644
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@@ -40,6 +40,5 @@ available, go to :ref:`commandindex`.
    getting_started/index
    using_yosys/index
    yosys_internals/index
-   yosys_source/index
 
    appendix
diff --git a/docs/source/yosys_internals/extending_yosys/build_verific.rst b/docs/source/yosys_internals/extending_yosys/build_verific.rst
index ea21fda0868..d8502d7bb67 100644
--- a/docs/source/yosys_internals/extending_yosys/build_verific.rst
+++ b/docs/source/yosys_internals/extending_yosys/build_verific.rst
@@ -50,11 +50,18 @@ Parameter                         Default Description
 ENABLE_VERIFIC_SYSTEMVERILOG      1       SystemVerilog support
 ENABLE_VERIFIC_VHDL               1       VHDL support
 ENABLE_VERIFIC_HIER_TREE          1       Hierarchy tree support
-ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 1       YosysHQ specific extensions support
+ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 0       YosysHQ specific extensions support
 ENABLE_VERIFIC_EDIF               0       EDIF support
 ENABLE_VERIFIC_LIBERTY            0       Liberty file support
 ================================= ======= ===================================
 
+To find the compile options used for a given Yosys build, call `yosys-config
+--cxxflags`. This documentation was built with the following compile options:
+
+.. literalinclude:: /generated/yosys-config
+    :start-at: --cxxflags
+    :end-before: --linkflags
+
 Required Verific features
 ~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -92,9 +99,9 @@ Yosys builds:
 Partially supported builds
 ~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-.. todo:: still unclear on the purpose of this section.
-
-   Are these the configurations we have tested as being able to compile?
+This section describes Yosys+Verific configurations which we have confirmed as
+working in the past, however they are not a part of our regular tests so we
+cannot guarantee they are still functional.
 
 To be able to compile Yosys with Verific, the Verific library must have support
 for at least one HDL language with RTL elaboration enabled.  The following table

From 0327ad97f2e7ddeaa553c1fca768cd32ec29056e Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 22 Aug 2024 10:03:59 +1200
Subject: [PATCH 443/499] Docs: Fix code formatting

Gets me everytime
---
 .../extending_yosys/build_verific.rst             | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/docs/source/yosys_internals/extending_yosys/build_verific.rst b/docs/source/yosys_internals/extending_yosys/build_verific.rst
index d8502d7bb67..16ec53645b2 100644
--- a/docs/source/yosys_internals/extending_yosys/build_verific.rst
+++ b/docs/source/yosys_internals/extending_yosys/build_verific.rst
@@ -55,8 +55,8 @@ ENABLE_VERIFIC_EDIF               0       EDIF support
 ENABLE_VERIFIC_LIBERTY            0       Liberty file support
 ================================= ======= ===================================
 
-To find the compile options used for a given Yosys build, call `yosys-config
---cxxflags`. This documentation was built with the following compile options:
+To find the compile options used for a given Yosys build, call ``yosys-config
+--cxxflags``. This documentation was built with the following compile options:
 
 .. literalinclude:: /generated/yosys-config
     :start-at: --cxxflags
@@ -69,9 +69,10 @@ The following features, along with their corresponding Yosys build parameters,
 are required for the Yosys-Verific patch:
 
 * RTL elaboration with
-   * SystemVerilog with ENABLE_VERIFIC_SYSTEMVERILOG, and/or
-   * VHDL support with ENABLE_VERIFIC_VHDL.
-* Hierarchy tree support and static elaboration with ENABLE_VERIFIC_HIER_TREE.
+   * SystemVerilog with ``ENABLE_VERIFIC_SYSTEMVERILOG``, and/or
+   * VHDL support with ``ENABLE_VERIFIC_VHDL``.
+* Hierarchy tree support and static elaboration with
+  ``ENABLE_VERIFIC_HIER_TREE``.
 
 Please be aware that the following Verific configuration build parameter needs
 to be enabled in order to create the fully supported build:
@@ -93,8 +94,8 @@ Optional Verific features
 The following Verific features are available with TabbyCAD and can be enabled in
 Yosys builds:
 
-* EDIF support with ENABLE_VERIFIC_EDIF, and
-* Liberty file support with ENABLE_VERIFIC_LIBERTY.
+* EDIF support with ``ENABLE_VERIFIC_EDIF``, and
+* Liberty file support with ``ENABLE_VERIFIC_LIBERTY``.
 
 Partially supported builds
 ~~~~~~~~~~~~~~~~~~~~~~~~~~

From 8145461c7898754985595f84787f4058e0c9aa8d Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 22 Aug 2024 10:03:59 +1200
Subject: [PATCH 444/499] Docs: Fix Verific builds table formatting

PDF don't like the long headers, so instead use placeholders a-d with elaborations below.
---
 .../extending_yosys/build_verific.rst         | 40 +++++++++++--------
 1 file changed, 23 insertions(+), 17 deletions(-)

diff --git a/docs/source/yosys_internals/extending_yosys/build_verific.rst b/docs/source/yosys_internals/extending_yosys/build_verific.rst
index 16ec53645b2..ae453886f99 100644
--- a/docs/source/yosys_internals/extending_yosys/build_verific.rst
+++ b/docs/source/yosys_internals/extending_yosys/build_verific.rst
@@ -110,23 +110,29 @@ lists a series of build configurations which are possible, but only provide a
 limited subset of features.  Please note that support is limited without YosysHQ
 specific extensions of Verific library.
 
-+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+
-|                                                                          | Configuration values beginning with ENABLE_VERIFIC\_  |
-+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+
-| Features                                                                 | SYSTEMVERILOG | VHDL | HIER_TREE | YOSYSHQ_EXTENSIONS |
-+==========================================================================+===============+======+===========+====================+
-| SystemVerilog + RTL elaboration                                          |             1 |    0 |         0 |                  0 |
-+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+
-| VHDL + RTL elaboration                                                   |             0 |    1 |         0 |                  0 |
-+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+
-| SystemVerilog + VHDL + RTL elaboration                                   |             1 |    1 |         0 |                  0 |
-+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+
-| SystemVerilog + RTL elaboration + Static elaboration + Hier tree         |             1 |    0 |         1 |                  0 |
-+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+
-| VHDL + RTL elaboration + Static elaboration + Hier tree                  |             0 |    1 |         1 |                  0 |
-+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+
-| SystemVerilog + VHDL + RTL elaboration + Static elaboration + Hier tree  |             1 |    1 |         1 |                  0 |
-+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+
++--------------------------------------------------------------------------+---+---+---+-----------+
+|                                                                          | Configuration values  |
++--------------------------------------------------------------------------+-----+-----+-----+-----+
+| Features                                                                 |   a |   b |   c |   d |
++==========================================================================+=====+=====+=====+=====+
+| SystemVerilog + RTL elaboration                                          |   1 |   0 |   0 |   0 |
++--------------------------------------------------------------------------+-----+-----+-----+-----+
+| VHDL + RTL elaboration                                                   |   0 |   1 |   0 |   0 |
++--------------------------------------------------------------------------+-----+-----+-----+-----+
+| SystemVerilog + VHDL + RTL elaboration                                   |   1 |   1 |   0 |   0 |
++--------------------------------------------------------------------------+-----+-----+-----+-----+
+| SystemVerilog + RTL elaboration + Static elaboration + Hier tree         |   1 |   0 |   1 |   0 |
++--------------------------------------------------------------------------+-----+-----+-----+-----+
+| VHDL + RTL elaboration + Static elaboration + Hier tree                  |   0 |   1 |   1 |   0 |
++--------------------------------------------------------------------------+-----+-----+-----+-----+
+| SystemVerilog + VHDL + RTL elaboration + Static elaboration + Hier tree  |   1 |   1 |   1 |   0 |
++--------------------------------------------------------------------------+-----+-----+-----+-----+
+
+Configuration values:
+  a. ``ENABLE_VERIFIC_SYSTEMVERILOG``
+  b. ``ENABLE_VERIFIC_VHDL``
+  c. ``ENABLE_VERIFIC_HIER_TREE``
+  d. ``ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS``
 
 .. note::
 

From 6431534c2455ffb091d70a510581cf00f73ca79e Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 22 Aug 2024 10:03:59 +1200
Subject: [PATCH 445/499] Docs: Some other fixes

---
 docs/source/using_yosys/more_scripting/load_design.rst     | 7 +++----
 docs/source/yosys_internals/extending_yosys/extensions.rst | 2 --
 2 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/docs/source/using_yosys/more_scripting/load_design.rst b/docs/source/using_yosys/more_scripting/load_design.rst
index 07c2bd8e58e..cf6a1dc1f3f 100644
--- a/docs/source/using_yosys/more_scripting/load_design.rst
+++ b/docs/source/using_yosys/more_scripting/load_design.rst
@@ -30,10 +30,9 @@ keyword: Frontends
 .. note::
 
    The Verific frontend for Yosys, which provides the :cmd:ref:`verific`
-   command, requires the commercial `Tabby CAD Suite`_.  This is not the same as
-   simply having a Verific license when using Yosys.
-
-.. _Tabby CAD Suite: https://www.yosyshq.com/tabby-cad-datasheet
+   command, requires Yosys to be built with Verific.  This is not the same as
+   simply having a Verific license when using Yosys.  Check
+   :doc:`/yosys_internals/extending_yosys/build_verific` for more.
 
 Others:
 
diff --git a/docs/source/yosys_internals/extending_yosys/extensions.rst b/docs/source/yosys_internals/extending_yosys/extensions.rst
index fa4ad51f8f4..f10c634b015 100644
--- a/docs/source/yosys_internals/extending_yosys/extensions.rst
+++ b/docs/source/yosys_internals/extending_yosys/extensions.rst
@@ -8,8 +8,6 @@ Writing extensions
 
 .. todo:: update to use :file:`/code_examples/extensions/test*.log`
 
-.. todo:: should this be moved to yosys_source section?
-
 This chapter contains some bits and pieces of information about programming
 yosys extensions. Don't be afraid to ask questions on the YosysHQ Slack.
 

From 3317d80480e98539d44d474d7f85cab6f83be168 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 22 Aug 2024 10:04:00 +1200
Subject: [PATCH 446/499] Docs: Clarify verific caveats

---
 .../extending_yosys/build_verific.rst         | 21 +++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/docs/source/yosys_internals/extending_yosys/build_verific.rst b/docs/source/yosys_internals/extending_yosys/build_verific.rst
index ae453886f99..ae9e4f1d44a 100644
--- a/docs/source/yosys_internals/extending_yosys/build_verific.rst
+++ b/docs/source/yosys_internals/extending_yosys/build_verific.rst
@@ -17,12 +17,21 @@ The Yosys-Verific patch
 
 YosysHQ maintains and develops a patch for Verific in order to better integrate
 with Yosys and to provide features required by some of the formal verification
-front-end tools.  Synthesis from RTL may be possible without this patch, however
-we are unable to provide support for any Yosys+Verific builds without it.  To
-license this patch for your own Yosys builds, `contact YosysHQ`_.
+front-end tools.  To license this patch for your own Yosys builds, `contact
+YosysHQ`_.
 
 .. warning::
 
+   While synthesis from RTL may be possible without this patch, YosysHQ provides
+   no guarantees of correctness and is unable to provide support.
+
+We recommend against using unpatched Yosys+Verific builds in conjunction with
+the formal verification front-end tools unless you are familiar with their inner
+workings. There are cases where the tools will appear to work, while producing
+incorrect results.
+
+.. note::
+
    Some of the formal verification front-end tools may not be fully supported
    without the full TabbyCAD suite.  If you are wanting to use these tools,
    including SBY, make sure to ask us if the Yosys-Verific patch is right for
@@ -62,6 +71,10 @@ To find the compile options used for a given Yosys build, call ``yosys-config
     :start-at: --cxxflags
     :end-before: --linkflags
 
+.. note::
+
+   The YosysHQ specific extensions are only available with the TabbyCAD suite.
+
 Required Verific features
 ~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -110,7 +123,7 @@ lists a series of build configurations which are possible, but only provide a
 limited subset of features.  Please note that support is limited without YosysHQ
 specific extensions of Verific library.
 
-+--------------------------------------------------------------------------+---+---+---+-----------+
++--------------------------------------------------------------------------+-----+-----+-----+-----+
 |                                                                          | Configuration values  |
 +--------------------------------------------------------------------------+-----+-----+-----+-----+
 | Features                                                                 |   a |   b |   c |   d |

From 27b51cb3516ca6d430d35aa4ced5c0236b48596e Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Thu, 22 Aug 2024 00:18:24 +0000
Subject: [PATCH 447/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index d5e7e52356a..6cccac5b1b0 100644
--- a/Makefile
+++ b/Makefile
@@ -153,7 +153,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.44+39
+YOSYS_VER := 0.44+42
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 9b5e81b13fbc2e4947ad591bd49971a278082247 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 22 Aug 2024 10:40:56 +0100
Subject: [PATCH 448/499] drivertools: fix C++20 "incomplete type" error by
 moving constructors below other definitions

---
 kernel/drivertools.h | 24 +++++++++++++++---------
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/kernel/drivertools.h b/kernel/drivertools.h
index 8a51b88d9ef..079701c35cc 100644
--- a/kernel/drivertools.h
+++ b/kernel/drivertools.h
@@ -146,11 +146,8 @@ struct DriveBitMultiple
 	pool<DriveBit> multiple_;
 
 public:
-	DriveBitMultiple() {}
-	DriveBitMultiple(DriveBit const &single)
-	{
-		multiple_.emplace(single);
-	}
+	DriveBitMultiple();
+	DriveBitMultiple(DriveBit const &single);
 
 	pool<DriveBit> const &multiple() const { return multiple_; }
 
@@ -467,6 +464,11 @@ struct DriveBit
 
 };
 
+inline DriveBitMultiple::DriveBitMultiple() {}
+inline DriveBitMultiple::DriveBitMultiple(DriveBit const &single)
+{
+	multiple_.emplace(single);
+}
 
 struct DriveChunkWire
 {
@@ -626,10 +628,7 @@ struct DriveChunkMultiple
 public:
 	pool<DriveChunk> const &multiple() const { return multiple_; }
 
-	DriveChunkMultiple(DriveBitMultiple const &bit) : width_(1) {
-		for (auto const &bit : bit.multiple())
-			multiple_.emplace(bit);
-	}
+	DriveChunkMultiple(DriveBitMultiple const &bit);
 
 	int size() const { return width_; }
 
@@ -1030,6 +1029,13 @@ struct DriveChunk
 	}
 };
 
+inline DriveChunkMultiple::DriveChunkMultiple(DriveBitMultiple const &bit)
+	: width_(1)
+{
+	for (auto const &bit : bit.multiple())
+		multiple_.emplace(bit);
+}
+
 struct DriveSpec
 {
 private:

From 761eff594f0d21f73af3cfc4d9d9c3fe08d61edc Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 22 Aug 2024 11:13:58 +0100
Subject: [PATCH 449/499] functional backend: missing includes for stl
 containers

---
 kernel/functional.cc            | 1 +
 tests/functional/vcd_harness.cc | 1 +
 2 files changed, 2 insertions(+)

diff --git a/kernel/functional.cc b/kernel/functional.cc
index 1ece145e59f..11f030eae14 100644
--- a/kernel/functional.cc
+++ b/kernel/functional.cc
@@ -22,6 +22,7 @@
 #include "kernel/topo_scc.h"
 #include "ff.h"
 #include "ffinit.h"
+#include <deque>
 
 YOSYS_NAMESPACE_BEGIN
 namespace Functional {
diff --git a/tests/functional/vcd_harness.cc b/tests/functional/vcd_harness.cc
index 7232172348a..30238429b6e 100644
--- a/tests/functional/vcd_harness.cc
+++ b/tests/functional/vcd_harness.cc
@@ -4,6 +4,7 @@
 #include <random>
 #include <ctype.h>
 #include <vector>
+#include <unordered_map>
 
 #include "my_module_functional_cxx.cc"
 

From 583d820dc2cd1ef9e385145452550ab71be9115f Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 23 Aug 2024 09:23:57 +1200
Subject: [PATCH 450/499] Docs: Apply verific docs suggestions

---
 .../using_yosys/more_scripting/load_design.rst  |  5 +++--
 docs/source/using_yosys/synthesis/memory.rst    |  4 ++--
 .../extending_yosys/build_verific.rst           | 17 ++++++++---------
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/docs/source/using_yosys/more_scripting/load_design.rst b/docs/source/using_yosys/more_scripting/load_design.rst
index cf6a1dc1f3f..bbc55a36bd2 100644
--- a/docs/source/using_yosys/more_scripting/load_design.rst
+++ b/docs/source/using_yosys/more_scripting/load_design.rst
@@ -30,8 +30,9 @@ keyword: Frontends
 .. note::
 
    The Verific frontend for Yosys, which provides the :cmd:ref:`verific`
-   command, requires Yosys to be built with Verific.  This is not the same as
-   simply having a Verific license when using Yosys.  Check
+   command, requires Yosys to be built with Verific.  For full functionality,
+   custom modifications to the Verific source code from YosysHQ are required,
+   but limited useability can be achieved with some stock Verific builds.  Check
    :doc:`/yosys_internals/extending_yosys/build_verific` for more.
 
 Others:
diff --git a/docs/source/using_yosys/synthesis/memory.rst b/docs/source/using_yosys/synthesis/memory.rst
index 8306c82b9fb..e95a648757a 100644
--- a/docs/source/using_yosys/synthesis/memory.rst
+++ b/docs/source/using_yosys/synthesis/memory.rst
@@ -697,8 +697,8 @@ TDP with multiple read ports
 Patterns only supported with Verific
 ------------------------------------
 
-The following patterns are only supported when Yosys is built with the Verific
-front-end.
+The following patterns are only supported when the design is read in using the
+Verific front-end.
 
 Synchronous SDP with write-first behavior via blocking assignments
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/source/yosys_internals/extending_yosys/build_verific.rst b/docs/source/yosys_internals/extending_yosys/build_verific.rst
index ae9e4f1d44a..b20517bd3dd 100644
--- a/docs/source/yosys_internals/extending_yosys/build_verific.rst
+++ b/docs/source/yosys_internals/extending_yosys/build_verific.rst
@@ -33,9 +33,8 @@ incorrect results.
 .. note::
 
    Some of the formal verification front-end tools may not be fully supported
-   without the full TabbyCAD suite.  If you are wanting to use these tools,
-   including SBY, make sure to ask us if the Yosys-Verific patch is right for
-   you.
+   without the full TabbyCAD suite.  If you want to use these tools, including
+   SBY, make sure to ask us if the Yosys-Verific patch is right for you.
 
 Compile options
 ---------------
@@ -123,6 +122,12 @@ lists a series of build configurations which are possible, but only provide a
 limited subset of features.  Please note that support is limited without YosysHQ
 specific extensions of Verific library.
 
+Configuration values:
+  a. ``ENABLE_VERIFIC_SYSTEMVERILOG``
+  b. ``ENABLE_VERIFIC_VHDL``
+  c. ``ENABLE_VERIFIC_HIER_TREE``
+  d. ``ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS``
+
 +--------------------------------------------------------------------------+-----+-----+-----+-----+
 |                                                                          | Configuration values  |
 +--------------------------------------------------------------------------+-----+-----+-----+-----+
@@ -141,12 +146,6 @@ specific extensions of Verific library.
 | SystemVerilog + VHDL + RTL elaboration + Static elaboration + Hier tree  |   1 |   1 |   1 |   0 |
 +--------------------------------------------------------------------------+-----+-----+-----+-----+
 
-Configuration values:
-  a. ``ENABLE_VERIFIC_SYSTEMVERILOG``
-  b. ``ENABLE_VERIFIC_VHDL``
-  c. ``ENABLE_VERIFIC_HIER_TREE``
-  d. ``ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS``
-
 .. note::
 
    In case your Verific build has EDIF and/or Liberty support, you can enable

From 72f77dd97bad06935aa2d347ae5250c0d92c7d44 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Fri, 23 Aug 2024 00:18:22 +0000
Subject: [PATCH 451/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 6cccac5b1b0..0888ae3b53c 100644
--- a/Makefile
+++ b/Makefile
@@ -153,7 +153,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.44+42
+YOSYS_VER := 0.44+60
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 2e1335a0233abcfc833df2b5f6169f817ed12c40 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 23 Aug 2024 10:06:32 +1200
Subject: [PATCH 452/499] Docs: Fix local builds

Based on the docs-test-fork PR branch, includes PR preview announcement, linking to the relevant tyrtd page
---
 docs/source/conf.py | 22 +++++++++++++++-------
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/docs/source/conf.py b/docs/source/conf.py
index 23efe2b43c2..4719dc89e6a 100644
--- a/docs/source/conf.py
+++ b/docs/source/conf.py
@@ -41,13 +41,21 @@
 pygments_style = 'colorful'
 highlight_language = 'none'
 
-extensions = ['sphinx.ext.autosectionlabel', 'sphinxcontrib.bibtex', 'rtds_action']
-
-# rtds_action
-rtds_action_github_repo = "YosysHQ/yosys"
-rtds_action_path = "."
-rtds_action_artifact_prefix = "cmd-ref-"
-rtds_action_github_token = os.environ["GITHUB_TOKEN"]
+extensions = ['sphinx.ext.autosectionlabel', 'sphinxcontrib.bibtex']
+
+if os.getenv("READTHEDOCS"):
+    # Use rtds_action if we are building on read the docs and have a github token env var
+    if os.getenv("GITHUB_TOKEN"):
+        extensions += ['rtds_action']
+        rtds_action_github_repo = "YosysHQ/yosys"
+        rtds_action_path = "."
+        rtds_action_artifact_prefix = "cmd-ref-"
+        rtds_action_github_token = os.environ["GITHUB_TOKEN"]
+    else:
+        # We're on read the docs but have no github token, this is probably a PR preview build
+        html_theme_options["announcement"] = 'Missing content? Check <a class="reference internal" href="https://tyrtd--2.org.readthedocs.build/en/2/appendix/building_docs.html#pr-previews-and-limitations">PR preview limitations</a>.'
+        html_theme_options["light_css_variables"]["color-announcement-background"] = "var(--color-admonition-title-background--caution)"
+        html_theme_options["light_css_variables"]["color-announcement-text"] = "var(--color-content-foreground)"
 
 # Ensure that autosectionlabel will produce unique names
 autosectionlabel_prefix_document = True

From 0b53b10770f747926ecedd46a68571eb6ef1ee73 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 23 Aug 2024 12:36:41 +1200
Subject: [PATCH 453/499] Makefile: Stop unconditionally install docs prereqs

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 0888ae3b53c..1967f0c639c 100644
--- a/Makefile
+++ b/Makefile
@@ -1010,7 +1010,7 @@ docs/reqs:
 	$(Q) $(MAKE) -C docs reqs
 
 DOC_TARGET ?= html
-docs: docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage docs/reqs
+docs: docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage
 	$(Q) $(MAKE) -C docs $(DOC_TARGET)
 
 clean:

From 5d5d890d5b8283ac42c7f912d3c23f5a70387b2c Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 23 Aug 2024 12:52:15 +1200
Subject: [PATCH 454/499] Docs: macos-safe build

Swap `cp -u` for `rsync -t`.
Drop the workaround to get the list of dot files after copying them, and instead just run the makefile twice.
Swap `$(wildcard **/*.x)` for `$(shell find . -name *.x)`,
---
 docs/Makefile                |  1 +
 docs/source/_images/Makefile | 16 +++++++---------
 2 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/docs/Makefile b/docs/Makefile
index 701157ee6c3..8be970391a3 100644
--- a/docs/Makefile
+++ b/docs/Makefile
@@ -250,6 +250,7 @@ test-macros:
 .PHONY: images
 images:
 	$(MAKE) -C source/_images
+	$(MAKE) -C source/_images convert
 
 .PHONY: reqs
 reqs:
diff --git a/docs/source/_images/Makefile b/docs/source/_images/Makefile
index 955805f9c58..26cc47284c3 100644
--- a/docs/source/_images/Makefile
+++ b/docs/source/_images/Makefile
@@ -8,24 +8,22 @@ FAKETIME := TZ='Z' faketime -f '2022-01-01 00:00:00 x0,001'
 CODE_EXAMPLES := ../code_examples/*/Makefile
 examples: $(CODE_EXAMPLES)
 
-# target to convert specified dot file(s)
+# target to convert all dot files
+# needs to be run *after* examples, otherwise no dot files will be found
 .PHONY: convert
-TARG_DOT ?=
-convert: $(TARG_DOT:.dot=.pdf) $(TARG_DOT:.dot=.svg)
+DOT_FILES := $(shell find . -name *.dot)
+convert: $(DOT_FILES:.dot=.pdf) $(DOT_FILES:.dot=.svg)
 
-# use empty FORCE target because .PHONY ignores % expansion, using find allows
-# us to generate everything in one pass, since we don't know all of the possible
-# outputs until the sub-makes run
+# use empty FORCE target because .PHONY ignores % expansion
 FORCE:
 ../%/Makefile: FORCE
 	@make -C $(@D) dots
 	@mkdir -p $*
-	@find $(@D) -name *.dot -exec cp -u {} -t $* \;
-	@find $* -name *.dot -printf "%p " | xargs -i make --no-print-directory convert TARG_DOT="{}"
+	@find $(@D) -name *.dot -exec rsync -t {} $* \;
 
 # find and build all tex files
 .PHONY: all_tex
-TEX_FILES := $(wildcard **/*.tex)
+TEX_FILES := $(shell find . -name *.tex)
 all_tex: $(TEX_FILES:.tex=.pdf) $(TEX_FILES:.tex=.svg)
 
 %.pdf: %.dot

From 7d63fdd88eb99e4d6951fd86dab87537eff3bb43 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 23 Aug 2024 12:53:38 +1200
Subject: [PATCH 455/499] README: building docs on macos

---
 README.md | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/README.md b/README.md
index 7437bb2832b..c806ec28340 100644
--- a/README.md
+++ b/README.md
@@ -629,6 +629,10 @@ following are used for building the website:
 
 	$ sudo apt install pdf2svg faketime
 
+Or for MacOS, using homebrew:
+
+  $ brew install pdf2svg libfaketime
+
 PDFLaTeX, included with most LaTeX distributions, is also needed during the
 build process for the website.  Or, run the following:
 

From 98d26bdd2c054d31cb17785e3192ccaa944972f9 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Mon, 26 Aug 2024 10:55:01 +1200
Subject: [PATCH 456/499] Docs: Fix nested list on build_verific page

---
 .../yosys_internals/extending_yosys/build_verific.rst       | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/docs/source/yosys_internals/extending_yosys/build_verific.rst b/docs/source/yosys_internals/extending_yosys/build_verific.rst
index b20517bd3dd..2585ebae4b3 100644
--- a/docs/source/yosys_internals/extending_yosys/build_verific.rst
+++ b/docs/source/yosys_internals/extending_yosys/build_verific.rst
@@ -81,8 +81,10 @@ The following features, along with their corresponding Yosys build parameters,
 are required for the Yosys-Verific patch:
 
 * RTL elaboration with
-   * SystemVerilog with ``ENABLE_VERIFIC_SYSTEMVERILOG``, and/or
-   * VHDL support with ``ENABLE_VERIFIC_VHDL``.
+
+  * SystemVerilog with ``ENABLE_VERIFIC_SYSTEMVERILOG``, and/or
+  * VHDL support with ``ENABLE_VERIFIC_VHDL``.
+
 * Hierarchy tree support and static elaboration with
   ``ENABLE_VERIFIC_HIER_TREE``.
 

From 83692075df13430e641c8e263c0615136dd3857e Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 27 Aug 2024 09:50:29 +1200
Subject: [PATCH 457/499] ci: Don't cancel previous builds

Which is what the comment said, but the code didn't match.
---
 .github/workflows/test-verific.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml
index 627a70d4794..07c2aa4d181 100644
--- a/.github/workflows/test-verific.yml
+++ b/.github/workflows/test-verific.yml
@@ -13,7 +13,7 @@ jobs:
         with:
           paths_ignore: '["**/README.md"]'
           # don't cancel previous builds
-          cancel_others: 'true'
+          cancel_others: 'false'
           # only run on push *or* pull_request, not both
           concurrent_skipping: 'same_content_newer'
           # we have special actions when running on main, so this should be off

From a20756676cc9dc56bdd42686525736f8145dcb84 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 27 Aug 2024 09:56:07 +1200
Subject: [PATCH 458/499] ci: Update RTDs trigger conditional

Trigger on main, on a branch called `docs-preview*`, or on any tag.
---
 .github/workflows/test-verific.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml
index 07c2aa4d181..18172324257 100644
--- a/.github/workflows/test-verific.yml
+++ b/.github/workflows/test-verific.yml
@@ -112,7 +112,7 @@ jobs:
             docs/source/code_examples
 
       - name: Trigger RTDs build
-        if: ${{ github.ref == 'refs/heads/main' }}
+        if: ${{ github.ref == 'refs/heads/main' || startsWith(github.ref, 'refs/heads/docs-preview') || startsWith(github.ref, 'refs/tags/') }}
         uses: dfm/rtds-action@v1.1.0
         with:
           webhook_url: ${{ secrets.RTDS_WEBHOOK_URL }}

From ecff434886f685b1dce0637ed7af62a342d0d304 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 27 Aug 2024 10:21:31 +1200
Subject: [PATCH 459/499] Docs: Use version name from readthedocs

Latest still gets -dev, but if it's a docs preview use the tag/branch name.
---
 docs/source/conf.py | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/docs/source/conf.py b/docs/source/conf.py
index 4719dc89e6a..2dc370c4b4d 100644
--- a/docs/source/conf.py
+++ b/docs/source/conf.py
@@ -62,8 +62,12 @@
 autosectionlabel_maxdepth = 1
 
 # set version
-if os.getenv("READTHEDOCS") and os.getenv("READTHEDOCS_VERSION") == "latest":
-    release = yosys_ver + "-dev"
+if os.getenv("READTHEDOCS"):
+    rtds_version = os.getenv("READTHEDOCS_VERSION")
+    if rtds_version == "latest":
+        release = yosys_ver + "-dev"
+    else:
+        release = rtds_version
 else:
     release = yosys_ver
 

From 459e6b913a95beed390b650fef787a466b582332 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Tue, 27 Aug 2024 11:11:02 +0100
Subject: [PATCH 460/499] add functional ir documentation

---
 .../extending_yosys/functional_ir.rst         | 42 +++++++++++++++++++
 kernel/functional.h                           |  1 -
 2 files changed, 42 insertions(+), 1 deletion(-)
 create mode 100644 docs/source/yosys_internals/extending_yosys/functional_ir.rst

diff --git a/docs/source/yosys_internals/extending_yosys/functional_ir.rst b/docs/source/yosys_internals/extending_yosys/functional_ir.rst
new file mode 100644
index 00000000000..c0794519df3
--- /dev/null
+++ b/docs/source/yosys_internals/extending_yosys/functional_ir.rst
@@ -0,0 +1,42 @@
+Writing a new backend using FunctionalIR
+===========================================
+
+To simplify the writing of backends for functional languages or similar targets, Yosys provides an alternative intermediate representation called FunctionalIR which maps more directly on those targets.
+
+FunctionalIR represents the design as a function `(inputs, current_state) -> (outputs, next_state)`.
+This function is broken down into a series of assignments to variables.
+Those assignments only use simple operations, like a simple addition.
+Unlike RTLIL cells there is no support for automatically extending operands, every sign and zero extension has to be encoded as a separate operation.
+
+Like SSA form, each variable is assigned to exactly once.
+We can thus treat variables and assignments as equivalent and, since this is a graph-like representation, those variables are also called "nodes".
+Unlike RTLIL's cells and wires representation, this representation is strictly ordered (topologically sorted) with definitions preceding their use.
+
+Nodes are strongly typed, the two types (also called "sorts") available are
+- `bit[n]` for an `n`-bit bitvector, and
+- `memory[n,m]` for an immutable array of `2**n` values of type `bit[m]`.
+
+In terms of actual code, Yosys provides a class `Functional::IR` that represents a design in FunctionalIR.
+`Functional::IR::from_module` generates an instance from an RTLIL module.
+The entire design is stored as a whole in an internal data structure.
+To access the design, the `Functional::Node` class provides a reference to a particular node in the design.
+The `Functional::IR` class supports the syntax `for(auto node : ir)` to iterate over every node.
+
+`Functional::IR` also keeps track of inputs, outputs and "states" (registers and memories).
+They all have a name (equal to their name in RTLIL), a sort and a "type".
+The "type" field usually remains as the default value `$input`, `$output` or `$state`, however some RTLIL cells such as `$assert` or `$anyseq` generate auxiliary inputs/outputs/states that are given a different type to distinguish them from ordinary RTLIL inputs/outputs/states.
+- To access an individual input/output/"state", use `ir.input(name, type)`, `ir.output(name, type)` or `ir.state(name, type)`. `type` defaults to the default type.
+- To iterate over all inputs/outputs/"states" of a certain "type", methods `ir.inputs`, `ir.outputs`, `ir.states` are provided. Their argument defaults to the default types mentioned.
+- To iterate over inputs/outputs/"states" of any "type", use `ir.all_inputs`, `ir.all_outputs` and `ir.all_states`.
+- Outputs have a node that indicate the value of the output, this can be retrieved via `output.value()`.
+- States have a node that indicate the next value of the state, this can be retrieved via `state.next_value()`.
+  They also have an initial value that is accessed as either `state.initial_value_signal()` or `state.initial_value_memory()`, depending on their sort.
+
+Each node has a "function", which defines its operation (for a complete list of functions and a specification of their operation, see `functional.h`).
+Functions are represented as an enum `Functional::Fn` and the function field can be accessed as `node.fn()`.
+Since the most common operation is a switch over the function that also accesses the arguments, the `Node` class provides a method `visit` that implements the visitor pattern.
+For example, for an addition node `node` with arguments `n1` and `n2`, `node.visit(visitor)` would call `visitor.add(node, n1, n2)`.
+Thus typically one would implement class with a method for every function.
+Visitors should inherit from either `Functional::AbstractVisitor<ReturnType>` or `Functional::DefaultVisitor<ReturnType>`.
+The former will produce a compiler error if a case is unhandled, the latter will call `default_handler(node)` instead.
+Visitor methods should be marked as `override` to provide compiler errors if the arguments are wrong.
\ No newline at end of file
diff --git a/kernel/functional.h b/kernel/functional.h
index 88a48dba9ec..bc7b86ac15c 100644
--- a/kernel/functional.h
+++ b/kernel/functional.h
@@ -287,7 +287,6 @@ namespace Functional {
 			bool operator!=(iterator const &other) const { return _ir != other._ir || _index != other._index; }
 			bool operator==(iterator const &other) const { return !(*this != other); }
 			pointer operator->();
-			// TODO: implement operator-> using the arrow_proxy class currently in mem.h
 		};
 		iterator begin() { return iterator(this, 0); }
 		iterator end() { return iterator(this, _graph.size()); }

From b428bf4600774b49de780e1dae7ff00f6564e72f Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Tue, 27 Aug 2024 13:10:34 +0100
Subject: [PATCH 461/499] functional backends: identifiers in c++/smtlib may
 not start with digits

---
 backends/functional/cxx.cc    | 4 ++--
 backends/functional/smtlib.cc | 4 ++--
 kernel/functional.h           | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index 282eb8f673c..de7737a420e 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -48,8 +48,8 @@ template<typename Id> struct CxxScope : public Functional::Scope<Id> {
 		for(const char **p = reserved_keywords; *p != nullptr; p++)
 			this->reserve(*p);
 	}
-	bool is_character_legal(char c) override {
-		return isascii(c) && (isalnum(c) || c == '_' || c == '$');
+	bool is_character_legal(char c, int index) override {
+		return isascii(c) && (isalpha(c) || (isdigit(c) && index > 0) || c == '_' || c == '$');
 	}
 };
 
diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index 4e176c2fd3e..ae6ae40ca4b 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -48,8 +48,8 @@ struct SmtScope : public Functional::Scope<int> {
 		for(const char **p = reserved_keywords; *p != nullptr; p++)
 			reserve(*p);
 	}
-	bool is_character_legal(char c) override {
-		return isascii(c) && (isalnum(c) || strchr("~!@$%^&*_-+=<>.?/", c));
+	bool is_character_legal(char c, int index) override {
+		return isascii(c) && (isalpha(c) || (isdigit(c) && index > 0) || strchr("~!@$%^&*_-+=<>.?/", c));
 	}
 };
 
diff --git a/kernel/functional.h b/kernel/functional.h
index bc7b86ac15c..2afdd7fc339 100644
--- a/kernel/functional.h
+++ b/kernel/functional.h
@@ -576,7 +576,7 @@ namespace Functional {
 	template<class Id> class Scope {
 	protected:
 		char substitution_character = '_';
-		virtual bool is_character_legal(char) = 0;
+		virtual bool is_character_legal(char, int) = 0;
 	private:
 		pool<std::string> _used_names;
 		dict<Id, std::string> _by_id;
@@ -587,7 +587,7 @@ namespace Functional {
 		std::string unique_name(IdString suggestion) {
 			std::string str = RTLIL::unescape_id(suggestion);
 			for(size_t i = 0; i < str.size(); i++)
-				if(!is_character_legal(str[i]))
+				if(!is_character_legal(str[i], i))
 					str[i] = substitution_character;
 			if(_used_names.count(str) == 0) {
 				_used_names.insert(str);

From 27efed27c2ed94bd9778f6b4fc9640c2ebd1bf5b Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Wed, 28 Aug 2024 11:28:24 +0100
Subject: [PATCH 462/499] functional backend: more documentation

---
 .../extending_yosys/functional_ir.rst         | 65 +++++++++++++++----
 1 file changed, 54 insertions(+), 11 deletions(-)

diff --git a/docs/source/yosys_internals/extending_yosys/functional_ir.rst b/docs/source/yosys_internals/extending_yosys/functional_ir.rst
index c0794519df3..887d44a6ec1 100644
--- a/docs/source/yosys_internals/extending_yosys/functional_ir.rst
+++ b/docs/source/yosys_internals/extending_yosys/functional_ir.rst
@@ -5,16 +5,17 @@ To simplify the writing of backends for functional languages or similar targets,
 
 FunctionalIR represents the design as a function `(inputs, current_state) -> (outputs, next_state)`.
 This function is broken down into a series of assignments to variables.
-Those assignments only use simple operations, like a simple addition.
-Unlike RTLIL cells there is no support for automatically extending operands, every sign and zero extension has to be encoded as a separate operation.
+Each assignment is a simple operation, such as an addition.
+Complex operations are broken up into multiple steps.
+For example, an RTLIL addition will be translated into a sign/zero extension of the inputs, followed by an addition.
 
 Like SSA form, each variable is assigned to exactly once.
 We can thus treat variables and assignments as equivalent and, since this is a graph-like representation, those variables are also called "nodes".
 Unlike RTLIL's cells and wires representation, this representation is strictly ordered (topologically sorted) with definitions preceding their use.
 
-Nodes are strongly typed, the two types (also called "sorts") available are
+Every node has a "sort" (the FunctionalIR term for what might otherwise be called a "type"). The sorts available are
 - `bit[n]` for an `n`-bit bitvector, and
-- `memory[n,m]` for an immutable array of `2**n` values of type `bit[m]`.
+- `memory[n,m]` for an immutable array of `2**n` values of sort `bit[m]`.
 
 In terms of actual code, Yosys provides a class `Functional::IR` that represents a design in FunctionalIR.
 `Functional::IR::from_module` generates an instance from an RTLIL module.
@@ -22,12 +23,14 @@ The entire design is stored as a whole in an internal data structure.
 To access the design, the `Functional::Node` class provides a reference to a particular node in the design.
 The `Functional::IR` class supports the syntax `for(auto node : ir)` to iterate over every node.
 
-`Functional::IR` also keeps track of inputs, outputs and "states" (registers and memories).
-They all have a name (equal to their name in RTLIL), a sort and a "type".
+`Functional::IR` also keeps track of inputs, outputs and states.
+By a "state" we mean a pair of a "current state" input and a "next state" output.
+One such pair is created for every register and for every memory.
+Every input, output and state has a name (equal to their name in RTLIL), a sort and a "type".
 The "type" field usually remains as the default value `$input`, `$output` or `$state`, however some RTLIL cells such as `$assert` or `$anyseq` generate auxiliary inputs/outputs/states that are given a different type to distinguish them from ordinary RTLIL inputs/outputs/states.
-- To access an individual input/output/"state", use `ir.input(name, type)`, `ir.output(name, type)` or `ir.state(name, type)`. `type` defaults to the default type.
-- To iterate over all inputs/outputs/"states" of a certain "type", methods `ir.inputs`, `ir.outputs`, `ir.states` are provided. Their argument defaults to the default types mentioned.
-- To iterate over inputs/outputs/"states" of any "type", use `ir.all_inputs`, `ir.all_outputs` and `ir.all_states`.
+- To access an individual input/output/state, use `ir.input(name, type)`, `ir.output(name, type)` or `ir.state(name, type)`. `type` defaults to the default type.
+- To iterate over all inputs/outputs/states of a certain "type", methods `ir.inputs`, `ir.outputs`, `ir.states` are provided. Their argument defaults to the default types mentioned.
+- To iterate over inputs/outputs/states of any "type", use `ir.all_inputs`, `ir.all_outputs` and `ir.all_states`.
 - Outputs have a node that indicate the value of the output, this can be retrieved via `output.value()`.
 - States have a node that indicate the next value of the state, this can be retrieved via `state.next_value()`.
   They also have an initial value that is accessed as either `state.initial_value_signal()` or `state.initial_value_memory()`, depending on their sort.
@@ -36,7 +39,47 @@ Each node has a "function", which defines its operation (for a complete list of
 Functions are represented as an enum `Functional::Fn` and the function field can be accessed as `node.fn()`.
 Since the most common operation is a switch over the function that also accesses the arguments, the `Node` class provides a method `visit` that implements the visitor pattern.
 For example, for an addition node `node` with arguments `n1` and `n2`, `node.visit(visitor)` would call `visitor.add(node, n1, n2)`.
-Thus typically one would implement class with a method for every function.
+Thus typically one would implement a class with a method for every function.
 Visitors should inherit from either `Functional::AbstractVisitor<ReturnType>` or `Functional::DefaultVisitor<ReturnType>`.
 The former will produce a compiler error if a case is unhandled, the latter will call `default_handler(node)` instead.
-Visitor methods should be marked as `override` to provide compiler errors if the arguments are wrong.
\ No newline at end of file
+Visitor methods should be marked as `override` to provide compiler errors if the arguments are wrong.
+
+Utility classes
+-----------------
+
+`functional.h` also provides utility classes that are independent of the main FunctionalIR representation but are likely to be useful for backends.
+
+`Functional::Writer` provides a simple formatting class that wraps a `std::ostream` and provides the following methods:
+- `writer << value` wraps `os << value`.
+- `writer.print(fmt, value0, value1, value2, ...)` replaces `{0}`, `{1}`, `{2}`, etc in the string `fmt` with `value0`, `value1`, `value2`, resp.
+  Each value is formatted using `os << value`.
+  It is also possible to write `{}` to refer to one past the last index, i.e. `{1} {} {} {7} {}` is equivalent to `{1} {2} {3} {7} {8}`.
+- `writer.print_with(fn, fmt, value0, value1, value2, ...)` functions much the same as `print` but it uses `os << fn(value)` to print each value and falls back to `os << value` if `fn(value)` is not legal.
+
+`Functional::Scope` keeps track of variable names in a target language.
+It is used to translate between different sets of legal characters and to avoid accidentally re-defining identifiers.
+Users should derive a class from `Scope` and supply the following:
+- `Scope<Id>` takes a template argument that specifies a type that's used to uniquely distinguish variables.
+  Typically this would be `int` (if variables are used for `Functional::IR` nodes) or `IdString`.
+- The derived class should provide a constructor that calls `reserve` for every reserved word in the target language.
+- A method `bool is_legal_character(char c, int index)` has to be provided that returns `true` iff `c` is legal in an identifier at position `index`.
+Given an instance `scope` of the derived class, the following methods are then available:
+- `scope.reserve(std::string name)` marks the given name as being in-use
+- `scope.unique_name(IdString suggestion)` generates a previously unused name and attempts to make it similar to `suggestion`.
+- `scope(Id id, IdString suggestion)` functions similar to `unique_name`, except that multiple calls with the same `id` are guaranteed to retrieve the same name (independent of `suggestion`).
+
+`sexpr.h` provides classes that represent and pretty-print s-expressions.
+S-expressions can be constructed with `SExpr::list`, for example `SExpr expr = SExpr::list("add", "x", SExpr::list("mul", "y", "z"))` represents `(add x (mul y z))`
+(by adding `using SExprUtil::list` to the top of the file, `list` can be used as shorthand for `SExpr::list`).
+For prettyprinting, `SExprWriter` wraps an `std::ostream` and provides the following methods:
+- `writer << sexpr` writes the provided expression to the output, breaking long lines and adding appropriate indentation.
+- `writer.open(sexpr)` is similar to `writer << sexpr` but will omit the last closing parenthesis.
+  Further arguments can then be added separately with `<<` or `open`.
+  This allows for printing large s-expressions without needing the construct the whole expression in memory first.
+- `writer.open(sexpr, false)` is similar to `writer.open(sexpr)` but further arguments will not be indented.
+  This is used to avoid unlimited indentation on structures with unlimited nesting.
+- `writer.close(n = 1)` closes the last `n` open s-expressions.
+- `writer.push()` and `writer.pop()` are used to automatically close s-expressions.
+  `writer.pop()` closes all s-expressions opened since the last call to `writer.push()`.
+- `writer.comment(string)` writes a comment on a separate-line.
+  `writer.comment(string, true)` appends a comment to the last printed s-expression.
\ No newline at end of file

From 4eeb8d326acbd2c3d4fcdc4cef798abb1a2e0728 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Wed, 28 Aug 2024 12:39:41 +0100
Subject: [PATCH 463/499] functional backend: rename "type" to either "kind" or
 "sort" to make the terminology consistent

---
 backends/functional/cxx.cc                    |  4 +-
 backends/functional/smtlib.cc                 |  4 +-
 backends/functional/test_generic.cc           |  4 +-
 .../extending_yosys/functional_ir.rst         | 10 +--
 kernel/functional.cc                          | 16 ++--
 kernel/functional.h                           | 88 +++++++++----------
 6 files changed, 63 insertions(+), 63 deletions(-)

diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index de7737a420e..b8b25df8b12 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -151,8 +151,8 @@ template<class NodePrinter> struct CxxPrintVisitor : public Functional::Abstract
 	void arithmetic_shift_right(Node, Node a, Node b) override { print("{}.arithmetic_shift_right({})", a, b); }
 	void mux(Node, Node a, Node b, Node s) override { print("{2}.any() ? {1} : {0}", a, b, s); }
 	void constant(Node, RTLIL::Const const & value) override { print("{}", cxx_const(value)); }
-	void input(Node, IdString name, IdString type) override { log_assert(type == ID($input)); print("input.{}", input_struct[name]); }
-	void state(Node, IdString name, IdString type) override { log_assert(type == ID($state)); print("current_state.{}", state_struct[name]); }
+	void input(Node, IdString name, IdString kind) override { log_assert(kind == ID($input)); print("input.{}", input_struct[name]); }
+	void state(Node, IdString name, IdString kind) override { log_assert(kind == ID($state)); print("current_state.{}", state_struct[name]); }
 	void memory_read(Node, Node mem, Node addr) override { print("{}.read({})", mem, addr); }
 	void memory_write(Node, Node mem, Node addr, Node data) override { print("{}.write({}, {})", mem, addr, data); }
 };
diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index ae6ae40ca4b..3eacf407cf2 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -179,8 +179,8 @@ struct SmtPrintVisitor : public Functional::AbstractVisitor<SExpr> {
 	SExpr memory_read(Node, Node mem, Node addr) override { return list("select", n(mem), n(addr)); }
 	SExpr memory_write(Node, Node mem, Node addr, Node data) override { return list("store", n(mem), n(addr), n(data)); }
 
-	SExpr input(Node, IdString name, IdString type) override { log_assert(type == ID($input)); return input_struct.access("inputs", name); }
-	SExpr state(Node, IdString name, IdString type) override { log_assert(type == ID($state)); return state_struct.access("state", name); }
+	SExpr input(Node, IdString name, IdString kind) override { log_assert(kind == ID($input)); return input_struct.access("inputs", name); }
+	SExpr state(Node, IdString name, IdString kind) override { log_assert(kind == ID($state)); return state_struct.access("state", name); }
 };
 
 struct SmtModule {
diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc
index aab2260f177..10a7a50f018 100644
--- a/backends/functional/test_generic.cc
+++ b/backends/functional/test_generic.cc
@@ -144,9 +144,9 @@ struct FunctionalTestGeneric : public Pass
 			for(auto node : fir)
 				std::cout << RTLIL::unescape_id(node.name()) << " = " << node.to_string([](auto n) { return RTLIL::unescape_id(n.name()); }) << "\n";
 			for(auto output : fir.all_outputs())
-				std::cout << RTLIL::unescape_id(output->type) << " " << RTLIL::unescape_id(output->name) << " = " << RTLIL::unescape_id(output->value().name()) << "\n";
+				std::cout << RTLIL::unescape_id(output->kind) << " " << RTLIL::unescape_id(output->name) << " = " << RTLIL::unescape_id(output->value().name()) << "\n";
 			for(auto state : fir.all_states())
-				std::cout << RTLIL::unescape_id(state->type) << " " << RTLIL::unescape_id(state->name) << " = " << RTLIL::unescape_id(state->next_value().name()) << "\n";
+				std::cout << RTLIL::unescape_id(state->kind) << " " << RTLIL::unescape_id(state->name) << " = " << RTLIL::unescape_id(state->next_value().name()) << "\n";
 		}
 	}
 } FunctionalCxxBackend;
diff --git a/docs/source/yosys_internals/extending_yosys/functional_ir.rst b/docs/source/yosys_internals/extending_yosys/functional_ir.rst
index 887d44a6ec1..38d00055627 100644
--- a/docs/source/yosys_internals/extending_yosys/functional_ir.rst
+++ b/docs/source/yosys_internals/extending_yosys/functional_ir.rst
@@ -26,11 +26,11 @@ The `Functional::IR` class supports the syntax `for(auto node : ir)` to iterate
 `Functional::IR` also keeps track of inputs, outputs and states.
 By a "state" we mean a pair of a "current state" input and a "next state" output.
 One such pair is created for every register and for every memory.
-Every input, output and state has a name (equal to their name in RTLIL), a sort and a "type".
-The "type" field usually remains as the default value `$input`, `$output` or `$state`, however some RTLIL cells such as `$assert` or `$anyseq` generate auxiliary inputs/outputs/states that are given a different type to distinguish them from ordinary RTLIL inputs/outputs/states.
-- To access an individual input/output/state, use `ir.input(name, type)`, `ir.output(name, type)` or `ir.state(name, type)`. `type` defaults to the default type.
-- To iterate over all inputs/outputs/states of a certain "type", methods `ir.inputs`, `ir.outputs`, `ir.states` are provided. Their argument defaults to the default types mentioned.
-- To iterate over inputs/outputs/states of any "type", use `ir.all_inputs`, `ir.all_outputs` and `ir.all_states`.
+Every input, output and state has a name (equal to their name in RTLIL), a sort and a kind.
+The kind field usually remains as the default value `$input`, `$output` or `$state`, however some RTLIL cells such as `$assert` or `$anyseq` generate auxiliary inputs/outputs/states that are given a different kind to distinguish them from ordinary RTLIL inputs/outputs/states.
+- To access an individual input/output/state, use `ir.input(name, kind)`, `ir.output(name, kind)` or `ir.state(name, kind)`. `kind` defaults to the default kind.
+- To iterate over all inputs/outputs/states of a certain kind, methods `ir.inputs`, `ir.outputs`, `ir.states` are provided. Their argument defaults to the default kinds mentioned.
+- To iterate over inputs/outputs/states of any kind, use `ir.all_inputs`, `ir.all_outputs` and `ir.all_states`.
 - Outputs have a node that indicate the value of the output, this can be retrieved via `output.value()`.
 - States have a node that indicate the next value of the state, this can be retrieved via `state.next_value()`.
   They also have an initial value that is accessed as either `state.initial_value_signal()` or `state.initial_value_memory()`, depending on their sort.
diff --git a/kernel/functional.cc b/kernel/functional.cc
index 11f030eae14..c270a2bb631 100644
--- a/kernel/functional.cc
+++ b/kernel/functional.cc
@@ -67,26 +67,26 @@ const char *fn_to_string(Fn fn) {
 	log_error("fn_to_string: unknown Functional::Fn value %d", (int)fn);
 }
 
-vector<IRInput const*> IR::inputs(IdString type) const {
+vector<IRInput const*> IR::inputs(IdString kind) const {
 	vector<IRInput const*> ret;
 	for (const auto &[name, input] : _inputs)
-		if(input.type == type)
+		if(input.kind == kind)
 			ret.push_back(&input);
 	return ret;
 }
 
-vector<IROutput const*> IR::outputs(IdString type) const {
+vector<IROutput const*> IR::outputs(IdString kind) const {
 	vector<IROutput const*> ret;
 	for (const auto &[name, output] : _outputs)
-		if(output.type == type)
+		if(output.kind == kind)
 			ret.push_back(&output);
 	return ret;
 }
 
-vector<IRState const*> IR::states(IdString type) const {
+vector<IRState const*> IR::states(IdString kind) const {
 	vector<IRState const*> ret;
 	for (const auto &[name, state] : _states)
-		if(state.type == type)
+		if(state.kind == kind)
 			ret.push_back(&state);
 	return ret;
 }
@@ -120,8 +120,8 @@ struct PrintVisitor : DefaultVisitor<std::string> {
 	std::string zero_extend(Node, Node a, int out_width) override { return "zero_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; }
 	std::string sign_extend(Node, Node a, int out_width) override { return "sign_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; }
 	std::string constant(Node, RTLIL::Const const& value) override { return "constant(" + value.as_string() + ")"; }
-	std::string input(Node, IdString name, IdString type) override { return "input(" + name.str() + ", " + type.str() + ")"; }
-	std::string state(Node, IdString name, IdString type) override { return "state(" + name.str() + ", " + type.str() + ")"; }
+	std::string input(Node, IdString name, IdString kind) override { return "input(" + name.str() + ", " + kind.str() + ")"; }
+	std::string state(Node, IdString name, IdString kind) override { return "state(" + name.str() + ", " + kind.str() + ")"; }
 	std::string default_handler(Node self) override {
 		std::string ret = fn_to_string(self.fn());
 		ret += "(";
diff --git a/kernel/functional.h b/kernel/functional.h
index 2afdd7fc339..f1fb2767f6f 100644
--- a/kernel/functional.h
+++ b/kernel/functional.h
@@ -34,7 +34,7 @@ namespace Functional {
 	// each function is documented with a short pseudocode declaration or definition
 	// standard C/Verilog operators are used to describe the result
 	// 
-	// the types used in this are:
+	// the sorts used in this are:
 	// - bit[N]: a bitvector of N bits
 	//   bit[N] can be indicated as signed or unsigned. this is not tracked by the functional backend
 	//   but is meant to indicate how the value is interpreted
@@ -43,12 +43,12 @@ namespace Functional {
 	// - int: C++ int
 	// - Const[N]: yosys RTLIL::Const (with size() == N)
 	// - IdString: yosys IdString
-	// - any: used in documentation to indicate that the type is unconstrained
+	// - any: used in documentation to indicate that the sort is unconstrained
 	//
-	// nodes in the functional backend are either of type bit[N] or memory[N,M] (for some N, M: int)
-	// additionally, they can carry a constant of type int, Const[N] or IdString
-	// each node has a 'sort' field that stores the type of the node
-	// slice, zero_extend, sign_extend use the type field to store out_width
+	// nodes in the functional backend are either of sort bit[N] or memory[N,M] (for some N, M: int)
+	// additionally, they can carry a constant of sort int, Const[N] or IdString
+	// each node has a 'sort' field that stores the sort of the node
+	// slice, zero_extend, sign_extend use the sort field to store out_width
 	enum class Fn {
 		// invalid() = known-invalid/shouldn't happen value
 		// TODO: maybe remove this and use e.g. std::optional instead?
@@ -136,7 +136,7 @@ namespace Functional {
 	// returns the name of a Fn value, as a string literal
 	const char *fn_to_string(Fn);
 	// Sort represents the sort or type of a node
-	// currently the only two types are signal/bit and memory
+	// currently the only two sorts are signal/bit and memory
 	class Sort {
 		std::variant<int, std::pair<int, int>> _v;
 	public:
@@ -144,11 +144,11 @@ namespace Functional {
 		Sort(int addr_width, int data_width) : _v(std::make_pair(addr_width, data_width)) { }
 		bool is_signal() const { return _v.index() == 0; }
 		bool is_memory() const { return _v.index() == 1; }
-		// returns the width of a bitvector type, errors out for other types
+		// returns the width of a bitvector sort, errors out for other sorts
 		int width() const { return std::get<0>(_v); }
-		// returns the address width of a bitvector type, errors out for other types
+		// returns the address width of a bitvector sort, errors out for other sorts
 		int addr_width() const { return std::get<1>(_v).first; }
-		// returns the data width of a bitvector type, errors out for other types
+		// returns the data width of a bitvector sort, errors out for other sorts
 		int data_width() const { return std::get<1>(_v).second; }
 		bool operator==(Sort const& other) const { return _v == other._v; }
 		unsigned int hash() const { return mkhash(_v); }
@@ -160,22 +160,22 @@ namespace Functional {
 		friend class Factory;
 	public:
 		IdString name;
-		IdString type;
+		IdString kind;
 		Sort sort;
 	private:
-		IRInput(IR &, IdString name, IdString type, Sort sort)
-		: name(name), type(type), sort(std::move(sort)) {}
+		IRInput(IR &, IdString name, IdString kind, Sort sort)
+		: name(name), kind(kind), sort(std::move(sort)) {}
 	};
 	class IROutput {
 		friend class Factory;
 		IR &_ir;
 	public:
 		IdString name;
-		IdString type;
+		IdString kind;
 		Sort sort;
 	private:
-		IROutput(IR &ir, IdString name, IdString type, Sort sort)
-		: _ir(ir), name(name), type(type), sort(std::move(sort)) {}
+		IROutput(IR &ir, IdString name, IdString kind, Sort sort)
+		: _ir(ir), name(name), kind(kind), sort(std::move(sort)) {}
 	public:
 		Node value() const;
 		bool has_value() const;
@@ -186,12 +186,12 @@ namespace Functional {
 		IR &_ir;
 	public:
 		IdString name;
-		IdString type;
+		IdString kind;
 		Sort sort;
 	private:
 		std::variant<RTLIL::Const, MemContents> _initial;
-		IRState(IR &ir, IdString name, IdString type, Sort sort)
-		: _ir(ir), name(name), type(type), sort(std::move(sort)) {}
+		IRState(IR &ir, IdString name, IdString kind, Sort sort)
+		: _ir(ir), name(name), kind(kind), sort(std::move(sort)) {}
 	public:
 		Node next_value() const;
 		bool has_next_value() const;
@@ -253,20 +253,20 @@ namespace Functional {
 		Node operator[](int i);
 		void topological_sort();
 		void forward_buf();
-		IRInput const& input(IdString name, IdString type) const { return _inputs.at({name, type}); }
+		IRInput const& input(IdString name, IdString kind) const { return _inputs.at({name, kind}); }
 		IRInput const& input(IdString name) const { return input(name, ID($input)); }
-		IROutput const& output(IdString name, IdString type) const { return _outputs.at({name, type}); }
+		IROutput const& output(IdString name, IdString kind) const { return _outputs.at({name, kind}); }
 		IROutput const& output(IdString name) const { return output(name, ID($output)); }
-		IRState const& state(IdString name, IdString type) const { return _states.at({name, type}); }
+		IRState const& state(IdString name, IdString kind) const { return _states.at({name, kind}); }
 		IRState const& state(IdString name) const { return state(name, ID($state)); }
-		bool has_input(IdString name, IdString type) const { return _inputs.count({name, type}); }
-		bool has_output(IdString name, IdString type) const { return _outputs.count({name, type}); }
-		bool has_state(IdString name, IdString type) const { return _states.count({name, type}); }
-		vector<IRInput const*> inputs(IdString type) const;
+		bool has_input(IdString name, IdString kind) const { return _inputs.count({name, kind}); }
+		bool has_output(IdString name, IdString kind) const { return _outputs.count({name, kind}); }
+		bool has_state(IdString name, IdString kind) const { return _states.count({name, kind}); }
+		vector<IRInput const*> inputs(IdString kind) const;
 		vector<IRInput const*> inputs() const { return inputs(ID($input)); }
-		vector<IROutput const*> outputs(IdString type) const;
+		vector<IROutput const*> outputs(IdString kind) const;
 		vector<IROutput const*> outputs() const { return outputs(ID($output)); }
-		vector<IRState const*> states(IdString type) const;
+		vector<IRState const*> states(IdString kind) const;
 		vector<IRState const*> states() const { return states(ID($state)); }
 		vector<IRInput const*> all_inputs() const;
 		vector<IROutput const*> all_outputs() const;
@@ -364,12 +364,12 @@ namespace Functional {
 	};
 	inline IR::Graph::Ref IR::mutate(Node n) { return _graph[n._ref.index()]; }
 	inline Node IR::operator[](int i) { return Node(_graph[i]); }
-	inline Node IROutput::value() const { return Node(_ir._graph({name, type, false})); }
-	inline bool IROutput::has_value() const { return _ir._graph.has_key({name, type, false}); }
-	inline void IROutput::set_value(Node value) { log_assert(sort == value.sort()); _ir.mutate(value).assign_key({name, type, false}); }
-	inline Node IRState::next_value() const { return Node(_ir._graph({name, type, true})); }
-	inline bool IRState::has_next_value() const { return _ir._graph.has_key({name, type, true}); }
-	inline void IRState::set_next_value(Node value) { log_assert(sort == value.sort()); _ir.mutate(value).assign_key({name, type, true}); }
+	inline Node IROutput::value() const { return Node(_ir._graph({name, kind, false})); }
+	inline bool IROutput::has_value() const { return _ir._graph.has_key({name, kind, false}); }
+	inline void IROutput::set_value(Node value) { log_assert(sort == value.sort()); _ir.mutate(value).assign_key({name, kind, false}); }
+	inline Node IRState::next_value() const { return Node(_ir._graph({name, kind, true})); }
+	inline bool IRState::has_next_value() const { return _ir._graph.has_key({name, kind, true}); }
+	inline void IRState::set_next_value(Node value) { log_assert(sort == value.sort()); _ir.mutate(value).assign_key({name, kind, true}); }
 	inline Node IR::iterator::operator*() { return Node(_ir->_graph[_index]); }
 	inline arrow_proxy<Node> IR::iterator::operator->() { return arrow_proxy<Node>(**this); }
 	// AbstractVisitor provides an abstract base class for visitors
@@ -403,8 +403,8 @@ namespace Functional {
 		virtual T arithmetic_shift_right(Node self, Node a, Node b) = 0;
 		virtual T mux(Node self, Node a, Node b, Node s) = 0;
 		virtual T constant(Node self, RTLIL::Const const & value) = 0;
-		virtual T input(Node self, IdString name, IdString type) = 0;
-		virtual T state(Node self, IdString name, IdString type) = 0;
+		virtual T input(Node self, IdString name, IdString kind) = 0;
+		virtual T state(Node self, IdString name, IdString kind) = 0;
 		virtual T memory_read(Node self, Node mem, Node addr) = 0;
 		virtual T memory_write(Node self, Node mem, Node addr, Node data) = 0;
 	};
@@ -547,26 +547,26 @@ namespace Functional {
 			log_assert(node.sort() == value.sort());
 			_ir.mutate(node).append_arg(value._ref);
 		}
-		IRInput &add_input(IdString name, IdString type, Sort sort) {
-			auto [it, inserted] = _ir._inputs.emplace({name, type}, IRInput(_ir, name, type, std::move(sort)));
+		IRInput &add_input(IdString name, IdString kind, Sort sort) {
+			auto [it, inserted] = _ir._inputs.emplace({name, kind}, IRInput(_ir, name, kind, std::move(sort)));
 			if (!inserted) log_error("input `%s` was re-defined", name.c_str());
 			return it->second;
 		}
-		IROutput &add_output(IdString name, IdString type, Sort sort) {
-			auto [it, inserted] = _ir._outputs.emplace({name, type}, IROutput(_ir, name, type, std::move(sort)));
+		IROutput &add_output(IdString name, IdString kind, Sort sort) {
+			auto [it, inserted] = _ir._outputs.emplace({name, kind}, IROutput(_ir, name, kind, std::move(sort)));
 			if (!inserted) log_error("output `%s` was re-defined", name.c_str());
 			return it->second;
 		}
-		IRState &add_state(IdString name, IdString type, Sort sort) {
-			auto [it, inserted] = _ir._states.emplace({name, type}, IRState(_ir, name, type, std::move(sort)));
+		IRState &add_state(IdString name, IdString kind, Sort sort) {
+			auto [it, inserted] = _ir._states.emplace({name, kind}, IRState(_ir, name, kind, std::move(sort)));
 			if (!inserted) log_error("state `%s` was re-defined", name.c_str());
 			return it->second;
 		}
 		Node value(IRInput const& input) {
-			return add(IR::NodeData(Fn::input, std::pair(input.name, input.type)), input.sort, {});
+			return add(IR::NodeData(Fn::input, std::pair(input.name, input.kind)), input.sort, {});
 		}
 		Node value(IRState const& state) {
-			return add(IR::NodeData(Fn::state, std::pair(state.name, state.type)), state.sort, {});
+			return add(IR::NodeData(Fn::state, std::pair(state.name, state.kind)), state.sort, {});
 		}
 		void suggest_name(Node node, IdString name) {
 			_ir.mutate(node).sparse_attr() = name;

From bdb5d45591d7501825349bedcb2952d0b80a1112 Mon Sep 17 00:00:00 2001
From: George Rennie <georgerennie@gmail.com>
Date: Wed, 28 Aug 2024 15:38:27 +0100
Subject: [PATCH 464/499] proc_dff: respect sync rule priorities when
 generating complex dffsrs

* This fixes #4560, where previously the order that sync rules were
  processed in depended on the order they were pulled out of a std::map.
  This PR changes this to process them in the order they are found in,
  respecting the priorities among the async signals
---
 passes/proc/proc_dff.cc | 211 +++++++++++++++-------------------------
 1 file changed, 76 insertions(+), 135 deletions(-)

diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index fd56786f28b..3aad9ac1c6e 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -54,90 +54,35 @@ RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc)
 }
 
 void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity,
-		std::map<RTLIL::SigSpec, std::set<RTLIL::SyncRule*>> &async_rules, RTLIL::Process *proc)
+		std::vector<std::pair<RTLIL::SigSpec, RTLIL::SyncRule*>> &async_rules, RTLIL::Process *proc)
 {
+	// A signal should be set/cleared if there is a load trigger that is enabled
+	// such that the load value is 1/0 and it is the highest priority trigger
 	RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.size());
 	RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.size());
 
-	for (auto &it : async_rules)
+	// Reverse iterate through the rules as the first ones are the highest priority
+	// so need to be at the top of the mux trees
+	for (auto it = async_rules.crbegin(); it != async_rules.crend(); it++)
 	{
-		RTLIL::SigSpec sync_value = it.first;
-		RTLIL::SigSpec sync_value_inv;
-		RTLIL::SigSpec sync_high_signals;
-		RTLIL::SigSpec sync_low_signals;
-
-		for (auto &it2 : it.second)
-			if (it2->type == RTLIL::SyncType::ST0)
-				sync_low_signals.append(it2->signal);
-			else if (it2->type == RTLIL::SyncType::ST1)
-				sync_high_signals.append(it2->signal);
-			else
-				log_abort();
-
-		if (sync_low_signals.size() > 1) {
-			RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($reduce_or));
-			cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
-			cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_low_signals.size());
-			cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
-			cell->setPort(ID::A, sync_low_signals);
-			cell->setPort(ID::Y, sync_low_signals = mod->addWire(NEW_ID));
-		}
+		const auto& [sync_value, rule] = *it;
+		const auto pos_trig = rule->type == RTLIL::SyncType::ST1 ? rule->signal : mod->Not(NEW_ID, rule->signal);
 
-		if (sync_low_signals.size() > 0) {
-			RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($not));
-			cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
-			cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_low_signals.size());
-			cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
-			cell->setPort(ID::A, sync_low_signals);
-			cell->setPort(ID::Y, mod->addWire(NEW_ID));
-			sync_high_signals.append(cell->getPort(ID::Y));
-		}
-
-		if (sync_high_signals.size() > 1) {
-			RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($reduce_or));
-			cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
-			cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_high_signals.size());
-			cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
-			cell->setPort(ID::A, sync_high_signals);
-			cell->setPort(ID::Y, sync_high_signals = mod->addWire(NEW_ID));
-		}
+		// If pos_trig is true, we have priority at this point in the tree so
+		// set a bit if sync_value has a set bit. Otherwise, defer to the rest
+		// of the priority tree
+		sig_sr_set = mod->Mux(NEW_ID, sig_sr_set, sync_value, pos_trig);
 
-		RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, ID($not));
-		inv_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
-		inv_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig_d.size());
-		inv_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(sig_d.size());
-		inv_cell->setPort(ID::A, sync_value);
-		inv_cell->setPort(ID::Y, sync_value_inv = mod->addWire(NEW_ID, sig_d.size()));
-
-		RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, ID($mux));
-		mux_set_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
-		mux_set_cell->setPort(ID::A, sig_sr_set);
-		mux_set_cell->setPort(ID::B, sync_value);
-		mux_set_cell->setPort(ID::S, sync_high_signals);
-		mux_set_cell->setPort(ID::Y, sig_sr_set = mod->addWire(NEW_ID, sig_d.size()));
-
-		RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, ID($mux));
-		mux_clr_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
-		mux_clr_cell->setPort(ID::A, sig_sr_clr);
-		mux_clr_cell->setPort(ID::B, sync_value_inv);
-		mux_clr_cell->setPort(ID::S, sync_high_signals);
-		mux_clr_cell->setPort(ID::Y, sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()));
+		// Same deal with clear bit
+		const auto sync_value_inv = mod->Not(NEW_ID, sync_value);
+		sig_sr_clr = mod->Mux(NEW_ID, sig_sr_clr, sync_value_inv, pos_trig);
 	}
 
 	std::stringstream sstr;
 	sstr << "$procdff$" << (autoidx++);
 
-	RTLIL::Cell *cell = mod->addCell(sstr.str(), ID($dffsr));
+	RTLIL::Cell *cell = mod->addDffsr(sstr.str(), clk, sig_sr_set, sig_sr_clr, sig_d, sig_q, clk_polarity);
 	cell->attributes = proc->attributes;
-	cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
-	cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
-	cell->parameters[ID::SET_POLARITY] = RTLIL::Const(true, 1);
-	cell->parameters[ID::CLR_POLARITY] = RTLIL::Const(true, 1);
-	cell->setPort(ID::D, sig_d);
-	cell->setPort(ID::Q, sig_q);
-	cell->setPort(ID::CLK, clk);
-	cell->setPort(ID::SET, sig_sr_set);
-	cell->setPort(ID::CLR, sig_sr_clr);
 
 	log("  created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
 			cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
@@ -204,7 +149,6 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 	while (1)
 	{
 		RTLIL::SigSpec sig = find_any_lvalue(proc);
-		bool free_sync_level = false;
 
 		if (sig.size() == 0)
 			break;
@@ -213,13 +157,17 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 				mod->name.c_str(), log_signal(sig), mod->name.c_str(), proc->name.c_str());
 
 		RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
-		RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
-		RTLIL::SyncRule *sync_level = NULL;
 		RTLIL::SyncRule *sync_edge = NULL;
 		RTLIL::SyncRule *sync_always = NULL;
 		bool global_clock = false;
 
-		std::map<RTLIL::SigSpec, std::set<RTLIL::SyncRule*>> many_async_rules;
+		// A priority ordered set of rules, pairing the value to be assigned for
+		// that rule to the rule
+		std::vector<std::pair<RTLIL::SigSpec, RTLIL::SyncRule*>> async_rules;
+
+		// Needed when the async rules are collapsed into one as async_rules
+		// works with pointers to SyncRule
+		RTLIL::SyncRule single_async_rule;
 
 		for (auto sync : proc->syncs)
 		for (auto &action : sync->actions)
@@ -228,14 +176,9 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 				continue;
 
 			if (sync->type == RTLIL::SyncType::ST0 || sync->type == RTLIL::SyncType::ST1) {
-				if (sync_level != NULL && sync_level != sync) {
-					// log_error("Multiple level sensitive events found for this signal!\n");
-					many_async_rules[rstval].insert(sync_level);
-					rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
-				}
-				rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
+				RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
 				sig.replace(action.first, action.second, &rstval);
-				sync_level = sync;
+				async_rules.emplace_back(rstval, sync);
 			}
 			else if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) {
 				if (sync_edge != NULL && sync_edge != sync)
@@ -260,59 +203,51 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 			action.first.remove2(sig, &action.second);
 		}
 
-		if (many_async_rules.size() > 0)
+		// If all async rules assign the same value, priority ordering between
+		// them doesn't matter so they can be collapsed together into one rule
+		// with the disjunction of triggers
+		if (!async_rules.empty() &&
+		    std::all_of(async_rules.begin(), async_rules.end(), [&](auto& p) {
+		        return p.first == async_rules.front().first;
+		    }))
 		{
-			many_async_rules[rstval].insert(sync_level);
-			if (many_async_rules.size() == 1)
-			{
-				sync_level = new RTLIL::SyncRule;
-				sync_level->type = RTLIL::SyncType::ST1;
-				sync_level->signal = mod->addWire(NEW_ID);
-				sync_level->actions.push_back(RTLIL::SigSig(sig, rstval));
-				free_sync_level = true;
-
-				RTLIL::SigSpec inputs, compare;
-				for (auto &it : many_async_rules[rstval]) {
-					inputs.append(it->signal);
-					compare.append(it->type == RTLIL::SyncType::ST0 ? RTLIL::State::S1 : RTLIL::State::S0);
-				}
-				log_assert(inputs.size() == compare.size());
-
-				RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($ne));
-				cell->parameters[ID::A_SIGNED] = RTLIL::Const(false, 1);
-				cell->parameters[ID::B_SIGNED] = RTLIL::Const(false, 1);
-				cell->parameters[ID::A_WIDTH] = RTLIL::Const(inputs.size());
-				cell->parameters[ID::B_WIDTH] = RTLIL::Const(inputs.size());
-				cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
-				cell->setPort(ID::A, inputs);
-				cell->setPort(ID::B, compare);
-				cell->setPort(ID::Y, sync_level->signal);
-
-				many_async_rules.clear();
-			}
-			else
-			{
-				rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
-				sync_level = NULL;
-			}
+			const auto rstval = async_rules.front().first;
+
+			// The trigger is the disjunction of existing triggers
+			// (with appropriate negation)
+			RTLIL::SigSpec triggers;
+			for (const auto &[_, it] : async_rules)
+				triggers.append(it->type == RTLIL::SyncType::ST1 ? it->signal : mod->Not(NEW_ID, it->signal));
+
+			// Put this into the dummy sync rule so it can be treated the same
+			// as ones coming from the module
+			single_async_rule.type = RTLIL::SyncType::ST1;
+			single_async_rule.signal = mod->ReduceOr(NEW_ID, triggers);
+			single_async_rule.actions.push_back(RTLIL::SigSig(sig, rstval));
+
+			// Replace existing rules with this new rule
+			async_rules.clear();
+			async_rules.emplace_back(rstval, &single_async_rule);
 		}
 
 		SigSpec sig_q = sig;
 		ce.assign_map.apply(insig);
-		ce.assign_map.apply(rstval);
 		ce.assign_map.apply(sig);
 
-		if (rstval == sig && sync_level) {
-			if (sync_level->type == RTLIL::SyncType::ST1)
-				insig = mod->Mux(NEW_ID, insig, sig, sync_level->signal);
+		// If the reset value assigns the reg to itself, add this as part of
+		// the input signal and delete the rule
+		if (async_rules.size() == 1 && async_rules.front().first == sig) {
+			const auto& [_, rule] = async_rules.front();
+			if (rule->type == RTLIL::SyncType::ST1)
+				insig = mod->Mux(NEW_ID, insig, sig, rule->signal);
 			else
-				insig = mod->Mux(NEW_ID, sig, insig, sync_level->signal);
-			rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
-			sync_level = NULL;
+				insig = mod->Mux(NEW_ID, sig, insig, rule->signal);
+
+			async_rules.clear();
 		}
 
 		if (sync_always) {
-			if (sync_edge || sync_level || many_async_rules.size() > 0)
+			if (sync_edge || !async_rules.empty())
 				log_error("Mixed always event with edge and/or level sensitive events!\n");
 			log("  created direct connection (no actual register cell created).\n");
 			mod->connect(RTLIL::SigSig(sig, insig));
@@ -322,28 +257,34 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 		if (!sync_edge && !global_clock)
 			log_error("Missing edge-sensitive event for this signal!\n");
 
-		if (many_async_rules.size() > 0)
+		// More than one reset value so we derive a dffsr formulation
+		if (async_rules.size() > 1)
 		{
 			log_warning("Complex async reset for dff `%s'.\n", log_signal(sig));
-			gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, many_async_rules, proc);
+			gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, async_rules, proc);
+			return;
 		}
-		else if (!rstval.is_fully_const() && !ce.eval(rstval))
+
+		// If there is a reset condition in the async rules, use it
+		SigSpec rstval = async_rules.empty() ? RTLIL::SigSpec(RTLIL::State::Sz, sig.size()) : async_rules.front().first;
+		RTLIL::SyncRule* sync_level = async_rules.empty() ? nullptr : async_rules.front().second;
+		ce.assign_map.apply(rstval);
+
+		if (!rstval.is_fully_const() && !ce.eval(rstval))
 		{
 			log_warning("Async reset value `%s' is not constant!\n", log_signal(rstval));
 			gen_aldff(mod, insig, rstval, sig_q,
 					sync_edge->type == RTLIL::SyncType::STp,
 					sync_level && sync_level->type == RTLIL::SyncType::ST1,
 					sync_edge->signal, sync_level->signal, proc);
+			return;
 		}
-		else
-			gen_dff(mod, insig, rstval.as_const(), sig_q,
-					sync_edge && sync_edge->type == RTLIL::SyncType::STp,
-					sync_level && sync_level->type == RTLIL::SyncType::ST1,
-					sync_edge ? sync_edge->signal : SigSpec(),
-					sync_level ? &sync_level->signal : NULL, proc);
 
-		if (free_sync_level)
-			delete sync_level;
+		gen_dff(mod, insig, rstval.as_const(), sig_q,
+				sync_edge && sync_edge->type == RTLIL::SyncType::STp,
+				sync_level && sync_level->type == RTLIL::SyncType::ST1,
+				sync_edge ? sync_edge->signal : SigSpec(),
+				sync_level ? &sync_level->signal : NULL, proc);
 	}
 }
 

From 8206951f77a95f0d7818d98aaf3e577a7aff5fae Mon Sep 17 00:00:00 2001
From: George Rennie <georgerennie@gmail.com>
Date: Wed, 28 Aug 2024 16:24:47 +0100
Subject: [PATCH 465/499] proc_dff: add tests

---
 tests/proc/proc_dff.ys | 80 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 80 insertions(+)
 create mode 100644 tests/proc/proc_dff.ys

diff --git a/tests/proc/proc_dff.ys b/tests/proc/proc_dff.ys
new file mode 100644
index 00000000000..1b719da367c
--- /dev/null
+++ b/tests/proc/proc_dff.ys
@@ -0,0 +1,80 @@
+read_verilog -formal <<EOT
+// From https://github.com/YosysHQ/yosys/pull/4568#issuecomment-2313740948
+
+module top(input clk, a, b, c, input [1:0] d, output reg [1:0] q);
+
+always @(posedge clk, posedge a, posedge b, posedge c) begin
+	if      (a) q <= '0;
+	else if (b) q <= 2'b10;
+	else if (c) q <= '0;
+	else        q <= d;
+end
+
+always @* begin
+	if      (a) assert(q == '0);
+	else if (b) assert(q == 2'b10);
+	else if (c) assert(q == '0);
+end
+
+endmodule
+EOT
+
+proc
+select -assert-count 1 t:$dffsr
+clk2fflogic
+select -assert-count 3 t:$assert
+sat -tempinduct -verify -prove-asserts
+
+design -reset
+
+read_verilog -formal <<EOT
+// Tests aload combined with reset. The aload gets refactored into the set/reset
+// logic
+module top(input clk, rst, aload_n, input [1:0] l, d, output reg [1:0] q);
+
+always @(posedge clk, posedge rst, negedge aload_n) begin
+	if      (rst)      q <= '0;
+	else if (!aload_n) q <= l;
+	else               q <= d;
+end
+
+always @* begin
+	if      (rst)      assert(q == '0);
+	else if (!aload_n) assert(q == l);
+end
+
+endmodule
+EOT
+
+proc
+select -assert-count 1 t:$dffsr
+clk2fflogic
+select -assert-count 2 t:$assert
+sat -tempinduct -verify -prove-asserts
+
+design -reset
+
+read_verilog -formal <<EOT
+// Tests combining of common reset signals
+module top(input clk, rst_a, rst_b, rst_c, input [1:0] d, output reg [1:0] q);
+
+always @(posedge clk, posedge rst_a, posedge rst_b, negedge rst_c) begin
+	if      (rst_a)  q <= '1;
+	else if (rst_b)  q <= '1;
+	else if (!rst_c) q <= '1;
+	else             q <= d;
+end
+
+always @* if (rst_a || rst_b || !rst_c) assert(q == '1);
+
+endmodule
+
+EOT
+
+proc
+select -assert-count 1 t:$adff
+clk2fflogic
+select -assert-count 1 t:$assert
+sat -tempinduct -verify -prove-asserts
+
+design -reset

From 2b8db94aa01394a3d25576439e5492cb52beab9d Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Thu, 29 Aug 2024 13:14:18 +0100
Subject: [PATCH 466/499] functional backend: add test to verify test_generic

---
 Makefile                            | 5 +++--
 tests/functional/test_functional.py | 8 +++++++-
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/Makefile b/Makefile
index e61948cb4f1..fbe09904263 100644
--- a/Makefile
+++ b/Makefile
@@ -1052,9 +1052,10 @@ clean_coverage:
 	find . -name "*.gcda" -type f -delete
 
 coverage_functional:
-	rm -rf coverage.info coverage_html
+	rm -rf coverage.info coverage2.info coverage_html
 	lcov --capture -d backends/functional --no-external -o coverage.info
-	genhtml coverage.info --output-directory coverage_html
+	lcov --capture -d kernel --include kernel/functional.cc --include kernel/functional.h --include kernel/sexpr.cc --include kernel/sexpr.h --include kernel/compute_graph.h --no-external -o coverage2.info
+	genhtml coverage.info coverage2.info --output-directory coverage_html
 
 qtcreator:
 	echo "$(CXXFLAGS)" | grep -o '\-D[^ ]*' | tr ' ' '\n' | sed 's/-D/#define /' | sed 's/=/ /'> qtcreator.config
diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py
index 107ca6862e5..55e4acc3340 100644
--- a/tests/functional/test_functional.py
+++ b/tests/functional/test_functional.py
@@ -70,4 +70,10 @@ def test_smt(cell, parameters, tmp_path, num_steps, rnd):
     yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_smt2 {quote(smt_file)}")
     run(['z3', smt_file]) # check if output is valid smtlib before continuing
     smt_vcd.simulate_smt(smt_file, vcd_functional_file, num_steps, rnd(cell.name + "-smt"))
-    yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
\ No newline at end of file
+    yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
+
+def test_print_graph(tmp_path):
+    tb_file = base_path / 'tests/functional/picorv32_tb.v'
+    cpu_file = base_path / 'tests/functional/picorv32.v'
+    # currently we only check that we can print the graph without getting an error, not that it prints anything sensibl
+    yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; flatten; clk2fflogic; test_generic")

From 840c515ffc61cf6c8f5b79f9435c8fabbc8f7c75 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 3 Sep 2024 10:20:24 +1200
Subject: [PATCH 467/499] RTDs: Fail on warning

Fix outstanding sphinx warnings;
- Change mycells.lib to use `text` parsing instead of (currently) unsupported `Liberty`.
- Remove unused `troubleshooting.rst`, moving the todo into the index.
---
 .readthedocs.yaml                                          | 1 +
 docs/source/using_yosys/more_scripting/index.rst           | 2 ++
 docs/source/using_yosys/more_scripting/troubleshooting.rst | 6 ------
 docs/source/using_yosys/synthesis/cell_libs.rst            | 4 +++-
 4 files changed, 6 insertions(+), 7 deletions(-)
 delete mode 100644 docs/source/using_yosys/more_scripting/troubleshooting.rst

diff --git a/.readthedocs.yaml b/.readthedocs.yaml
index cb700dc1c72..4a04219de98 100644
--- a/.readthedocs.yaml
+++ b/.readthedocs.yaml
@@ -13,6 +13,7 @@ formats:
 
 sphinx:
   configuration: docs/source/conf.py
+  fail_on_warning: true
 
 python:
   install:
diff --git a/docs/source/using_yosys/more_scripting/index.rst b/docs/source/using_yosys/more_scripting/index.rst
index 490a5a7ad8b..090b9e0b950 100644
--- a/docs/source/using_yosys/more_scripting/index.rst
+++ b/docs/source/using_yosys/more_scripting/index.rst
@@ -3,6 +3,8 @@ More scripting
 
 .. todo:: brief overview for the more scripting index
 
+.. todo:: troubleshooting document(?)
+
 .. toctree::
    :maxdepth: 3
 
diff --git a/docs/source/using_yosys/more_scripting/troubleshooting.rst b/docs/source/using_yosys/more_scripting/troubleshooting.rst
deleted file mode 100644
index a17a552d2e4..00000000000
--- a/docs/source/using_yosys/more_scripting/troubleshooting.rst
+++ /dev/null
@@ -1,6 +0,0 @@
-Troubleshooting
-~~~~~~~~~~~~~~~
-
-.. todo:: troubleshooting document(?)
-
-See :doc:`/cmd/bugpoint`
diff --git a/docs/source/using_yosys/synthesis/cell_libs.rst b/docs/source/using_yosys/synthesis/cell_libs.rst
index 92b6dab3f58..4e800bdf2b6 100644
--- a/docs/source/using_yosys/synthesis/cell_libs.rst
+++ b/docs/source/using_yosys/synthesis/cell_libs.rst
@@ -90,8 +90,10 @@ Mapping to hardware
 For this example, we are using a Liberty file to describe a cell library which
 our internal cell library will be mapped to:
 
+.. todo:: find a Liberty pygments style?
+
 .. literalinclude:: /code_examples/intro/mycells.lib
-   :language: Liberty
+   :language: text
    :linenos:
    :name: mycells-lib
    :caption: :file:`mycells.lib`

From a97d99cbac73d52b71aeea655790fd5877617e97 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 3 Sep 2024 11:00:28 +1200
Subject: [PATCH 468/499] ci: Verific skipping conditional on github.ref

Docs jobs should not skip on concurrent jobs (in case a non-docs job is already
running, such as when a commit has been tagged for docs-preview). However, a
successful `test-verific` can allow for a future docs job to skip testing and go
straight to the preview.
---
 .github/workflows/test-verific.yml | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml
index 18172324257..c7190fd183a 100644
--- a/.github/workflows/test-verific.yml
+++ b/.github/workflows/test-verific.yml
@@ -1,6 +1,10 @@
 name: Build and run tests with Verific (Linux)
 
 on: [push, pull_request]
+# docs builds are needed for anything on main, any tagged versions, and any tag
+# or branch starting with docs-preview
+env:
+  is_docs_job: ${{ github.ref == 'refs/heads/main' || startsWith(github.ref, 'refs/heads/docs-preview') || startsWith(github.ref, 'refs/tags/') }}
 
 jobs:
   pre-job:
@@ -16,8 +20,8 @@ jobs:
           cancel_others: 'false'
           # only run on push *or* pull_request, not both
           concurrent_skipping: 'same_content_newer'
-          # we have special actions when running on main, so this should be off
-          skip_after_successful_duplicate: 'false'
+          # we can skip testing if it has already passed
+          skip_after_successful_duplicate: 'true'
 
   test-verific:
     needs: pre-job
@@ -74,7 +78,6 @@ jobs:
   prepare-docs:
     name: Generate docs artifact
     needs: [pre-job, test-verific]
-    if: needs.pre-job.outputs.should_skip != 'true'
     runs-on: [self-hosted, linux, x64, fast]
     steps:
       - name: Checkout Yosys
@@ -82,11 +85,13 @@ jobs:
         with:
           persist-credentials: false
           submodules: true
+
       - name: Runtime environment
         run: |
           echo "procs=$(nproc)" >> $GITHUB_ENV
 
       - name: Build Yosys
+        if: ${{ (needs.pre-job.outputs.should_skip != 'true') || env.is_docs_job }}
         run: |
           make config-clang
           echo "ENABLE_VERIFIC := 1" >> Makefile.conf
@@ -97,11 +102,13 @@ jobs:
           make -j${{ env.procs }} ENABLE_LTO=1
 
       - name: Prepare docs
+        if: ${{ (needs.pre-job.outputs.should_skip != 'true') || env.is_docs_job }}
         shell: bash
         run:
           make docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage docs/reqs TARGETS= EXTRA_TARGETS=
 
       - name: Upload artifact
+        if: ${{ (needs.pre-job.outputs.should_skip != 'true') || env.is_docs_job }}
         uses: actions/upload-artifact@v4
         with:
           name: cmd-ref-${{ github.sha }}
@@ -112,7 +119,7 @@ jobs:
             docs/source/code_examples
 
       - name: Trigger RTDs build
-        if: ${{ github.ref == 'refs/heads/main' || startsWith(github.ref, 'refs/heads/docs-preview') || startsWith(github.ref, 'refs/tags/') }}
+        if: ${{ env.is_docs_job }}
         uses: dfm/rtds-action@v1.1.0
         with:
           webhook_url: ${{ secrets.RTDS_WEBHOOK_URL }}

From cab781d958476a1f549084f26965021988167a13 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 29 Aug 2024 09:58:41 +1200
Subject: [PATCH 469/499] Makefile: Move docs prereqs to separate target

---
 Makefile | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 1967f0c639c..21608126db2 100644
--- a/Makefile
+++ b/Makefile
@@ -1009,8 +1009,11 @@ docs/usage: $(addprefix docs/source/generated/,$(DOCS_USAGE_STDOUT) $(DOCS_USAGE
 docs/reqs:
 	$(Q) $(MAKE) -C docs reqs
 
+.PHONY: docs/prep
+docs/prep: docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage
+
 DOC_TARGET ?= html
-docs: docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage
+docs: docs/prep
 	$(Q) $(MAKE) -C docs $(DOC_TARGET)
 
 clean:

From 6c833d83b8670694d0216858527e893443b5374a Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 29 Aug 2024 09:59:20 +1200
Subject: [PATCH 470/499] ci: Use docs/prep target

---
 .github/workflows/test-verific.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml
index c7190fd183a..1b38b5f4254 100644
--- a/.github/workflows/test-verific.yml
+++ b/.github/workflows/test-verific.yml
@@ -105,7 +105,7 @@ jobs:
         if: ${{ (needs.pre-job.outputs.should_skip != 'true') || env.is_docs_job }}
         shell: bash
         run:
-          make docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage docs/reqs TARGETS= EXTRA_TARGETS=
+          make docs/prep TARGETS= EXTRA_TARGETS=
 
       - name: Upload artifact
         if: ${{ (needs.pre-job.outputs.should_skip != 'true') || env.is_docs_job }}

From e92de01ab30c5402ff633a99c6a696a67785b11f Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 3 Sep 2024 11:40:47 +1200
Subject: [PATCH 471/499] ci: Split out prepare-docs

---
 .github/workflows/prepare-docs.yml | 52 ++++++++++++++++++++++++++++
 .github/workflows/test-verific.yml | 55 ------------------------------
 2 files changed, 52 insertions(+), 55 deletions(-)
 create mode 100644 .github/workflows/prepare-docs.yml

diff --git a/.github/workflows/prepare-docs.yml b/.github/workflows/prepare-docs.yml
new file mode 100644
index 00000000000..9233e6295b4
--- /dev/null
+++ b/.github/workflows/prepare-docs.yml
@@ -0,0 +1,52 @@
+name: Build docs artifact with Verific
+
+on: push
+
+jobs:
+  prepare-docs:
+    # docs builds are needed for anything on main, any tagged versions, and any tag
+    # or branch starting with docs-preview
+    if: ${{ github.ref == 'refs/heads/main' || startsWith(github.ref, 'refs/heads/docs-preview') || startsWith(github.ref, 'refs/tags/') }}
+    runs-on: [self-hosted, linux, x64, fast]
+    steps:
+      - name: Checkout Yosys
+        uses: actions/checkout@v4
+        with:
+          persist-credentials: false
+          submodules: true
+
+      - name: Runtime environment
+        run: |
+          echo "procs=$(nproc)" >> $GITHUB_ENV
+
+      - name: Build Yosys
+        run: |
+          make config-clang
+          echo "ENABLE_VERIFIC := 1" >> Makefile.conf
+          echo "ENABLE_VERIFIC_EDIF := 1" >> Makefile.conf
+          echo "ENABLE_VERIFIC_LIBERTY := 1" >> Makefile.conf
+          echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1" >> Makefile.conf
+          echo "ENABLE_CCACHE := 1" >> Makefile.conf
+          make -j${{ env.procs }} ENABLE_LTO=1
+
+      - name: Prepare docs
+        shell: bash
+        run:
+          make docs/prep TARGETS= EXTRA_TARGETS=
+
+      - name: Upload artifact
+        uses: actions/upload-artifact@v4
+        with:
+          name: cmd-ref-${{ github.sha }}
+          path: |
+            docs/source/cmd
+            docs/source/generated
+            docs/source/_images
+            docs/source/code_examples
+
+      - name: Trigger RTDs build
+        uses: dfm/rtds-action@v1.1.0
+        with:
+          webhook_url: ${{ secrets.RTDS_WEBHOOK_URL }}
+          webhook_token: ${{ secrets.RTDS_WEBHOOK_TOKEN }}
+          commit_ref: ${{ github.ref }}
diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml
index 1b38b5f4254..7b55be7792c 100644
--- a/.github/workflows/test-verific.yml
+++ b/.github/workflows/test-verific.yml
@@ -1,10 +1,6 @@
 name: Build and run tests with Verific (Linux)
 
 on: [push, pull_request]
-# docs builds are needed for anything on main, any tagged versions, and any tag
-# or branch starting with docs-preview
-env:
-  is_docs_job: ${{ github.ref == 'refs/heads/main' || startsWith(github.ref, 'refs/heads/docs-preview') || startsWith(github.ref, 'refs/tags/') }}
 
 jobs:
   pre-job:
@@ -74,54 +70,3 @@ jobs:
         if: ${{ github.ref == 'refs/heads/main' }}
         run: |
           make -C sby run_ci
-
-  prepare-docs:
-    name: Generate docs artifact
-    needs: [pre-job, test-verific]
-    runs-on: [self-hosted, linux, x64, fast]
-    steps:
-      - name: Checkout Yosys
-        uses: actions/checkout@v4
-        with:
-          persist-credentials: false
-          submodules: true
-
-      - name: Runtime environment
-        run: |
-          echo "procs=$(nproc)" >> $GITHUB_ENV
-
-      - name: Build Yosys
-        if: ${{ (needs.pre-job.outputs.should_skip != 'true') || env.is_docs_job }}
-        run: |
-          make config-clang
-          echo "ENABLE_VERIFIC := 1" >> Makefile.conf
-          echo "ENABLE_VERIFIC_EDIF := 1" >> Makefile.conf
-          echo "ENABLE_VERIFIC_LIBERTY := 1" >> Makefile.conf
-          echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1" >> Makefile.conf
-          echo "ENABLE_CCACHE := 1" >> Makefile.conf
-          make -j${{ env.procs }} ENABLE_LTO=1
-
-      - name: Prepare docs
-        if: ${{ (needs.pre-job.outputs.should_skip != 'true') || env.is_docs_job }}
-        shell: bash
-        run:
-          make docs/prep TARGETS= EXTRA_TARGETS=
-
-      - name: Upload artifact
-        if: ${{ (needs.pre-job.outputs.should_skip != 'true') || env.is_docs_job }}
-        uses: actions/upload-artifact@v4
-        with:
-          name: cmd-ref-${{ github.sha }}
-          path: |
-            docs/source/cmd
-            docs/source/generated
-            docs/source/_images
-            docs/source/code_examples
-
-      - name: Trigger RTDs build
-        if: ${{ env.is_docs_job }}
-        uses: dfm/rtds-action@v1.1.0
-        with:
-          webhook_url: ${{ secrets.RTDS_WEBHOOK_URL }}
-          webhook_token: ${{ secrets.RTDS_WEBHOOK_TOKEN }}
-          commit_ref: ${{ github.ref }}

From 25623b1010bcdb00f6b16724687aea63494d38b8 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 3 Sep 2024 11:45:00 +1200
Subject: [PATCH 472/499] ci: test-verific no longer needs special casing

---
 .github/workflows/test-verific.yml | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml
index 7b55be7792c..43b68e06dca 100644
--- a/.github/workflows/test-verific.yml
+++ b/.github/workflows/test-verific.yml
@@ -11,13 +11,11 @@ jobs:
       - id: skip_check
         uses: fkirc/skip-duplicate-actions@v5
         with:
-          paths_ignore: '["**/README.md"]'
-          # don't cancel previous builds
-          cancel_others: 'false'
+          paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]'
+          # cancel previous builds if a new commit is pushed
+          cancel_others: 'true'
           # only run on push *or* pull_request, not both
           concurrent_skipping: 'same_content_newer'
-          # we can skip testing if it has already passed
-          skip_after_successful_duplicate: 'true'
 
   test-verific:
     needs: pre-job

From 558f313a78ecdf3ad6692ac17a4aede4afe23a73 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 29 Aug 2024 10:43:01 +1200
Subject: [PATCH 473/499] Docs: Show todos in previews

That includes local builds.
Also fix release version numbers.
---
 docs/source/conf.py | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/docs/source/conf.py b/docs/source/conf.py
index 2dc370c4b4d..723a0ea7fc4 100644
--- a/docs/source/conf.py
+++ b/docs/source/conf.py
@@ -61,15 +61,24 @@
 autosectionlabel_prefix_document = True
 autosectionlabel_maxdepth = 1
 
+# include todos for previews
+extensions.append('sphinx.ext.todo')
+
 # set version
 if os.getenv("READTHEDOCS"):
     rtds_version = os.getenv("READTHEDOCS_VERSION")
     if rtds_version == "latest":
         release = yosys_ver + "-dev"
+        todo_include_todos = False
+    elif rtds_version.startswith("yosys-"):
+        release = yosys_ver
+        todo_include_todos = False
     else:
         release = rtds_version
+        todo_include_todos = True
 else:
     release = yosys_ver
+    todo_include_todos = True
 
 # assign figure numbers
 numfig = True
@@ -84,10 +93,6 @@
 '''
 }
 
-# include todos during rewrite
-extensions.append('sphinx.ext.todo')
-todo_include_todos = False
-
 # custom cmd-ref parsing/linking
 sys.path += [os.path.dirname(__file__) + "/../"]
 extensions.append('util.cmdref')

From 6b9321250b25c6904daca34f56b502bafd9dfb35 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Tue, 3 Sep 2024 00:20:12 +0000
Subject: [PATCH 474/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 0888ae3b53c..8b3b721969e 100644
--- a/Makefile
+++ b/Makefile
@@ -153,7 +153,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.44+60
+YOSYS_VER := 0.44+71
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From c0ce0b82a8382dca94fe501aa624a20198bbd10d Mon Sep 17 00:00:00 2001
From: "Emily (aiju)" <aiju@phicode.de>
Date: Thu, 22 Aug 2024 11:54:20 +0100
Subject: [PATCH 475/499] docs: gvpack on macos requires the file name to
 appear after the flags

---
 docs/source/code_examples/opt/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/source/code_examples/opt/Makefile b/docs/source/code_examples/opt/Makefile
index 4cb51e90bec..12c1c93b1c8 100644
--- a/docs/source/code_examples/opt/Makefile
+++ b/docs/source/code_examples/opt/Makefile
@@ -13,7 +13,7 @@ dots: $(DOTS)
 	$(YOSYS) $<
 
 %.dot: %_full.dot
-	gvpack -u $*_full.dot -o $@
+	gvpack -u -o $@ $*_full.dot
 
 .PHONY: clean
 clean:

From 9c1bcb38d97eca203e44872109a9d1e92c363c4f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Tue, 3 Sep 2024 08:53:51 +0200
Subject: [PATCH 476/499] write_xaiger: Get by without endianness helpers

---
 backends/aiger/xaiger.cc | 60 ++++++++--------------------------------
 1 file changed, 11 insertions(+), 49 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 68c2ff52f55..3ca8b205a78 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -18,32 +18,6 @@
  *
  */
 
-// https://stackoverflow.com/a/46137633
-#ifdef _MSC_VER
-#include <stdlib.h>
-#define bswap32 _byteswap_ulong
-#elif defined(__APPLE__)
-#include <libkern/OSByteOrder.h>
-#define bswap32 OSSwapInt32
-#elif defined(__GNUC__)
-#define bswap32 __builtin_bswap32
-#else
-#include <cstdint>
-inline static uint32_t bswap32(uint32_t x)
-{
-	// https://stackoverflow.com/a/27796212
-	register uint32_t value = number_to_be_reversed;
-	uint8_t lolo = (value >> 0) & 0xFF;
-	uint8_t lohi = (value >> 8) & 0xFF;
-	uint8_t hilo = (value >> 16) & 0xFF;
-	uint8_t hihi = (value >> 24) & 0xFF;
-	return (hihi << 24)
-		| (hilo << 16)
-		| (lohi << 8)
-		| (lolo << 0);
-}
-#endif
-
 #include "kernel/yosys.h"
 #include "kernel/sigtools.h"
 #include "kernel/utils.h"
@@ -52,16 +26,6 @@ inline static uint32_t bswap32(uint32_t x)
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-inline int32_t to_big_endian(int32_t i32) {
-#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-	return bswap32(i32);
-#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
-	return i32;
-#else
-#error "Unknown endianness"
-#endif
-}
-
 void aiger_encode(std::ostream &f, int x)
 {
 	log_assert(x >= 0);
@@ -537,9 +501,12 @@ struct XAigerWriter
 
 		f << "c";
 
-		auto write_buffer = [](std::stringstream &buffer, int i32) {
-			int32_t i32_be = to_big_endian(i32);
-			buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
+		auto write_buffer = [](std::ostream &buffer, unsigned int u32) {
+			typedef unsigned char uchar;
+			unsigned char u32_be[4] = {
+				(uchar) (u32 >> 24), (uchar) (u32 >> 16), (uchar) (u32 >> 8), (uchar) u32
+			};
+			buffer.write((char *) u32_be, sizeof(u32_be));
 		};
 		std::stringstream h_buffer;
 		auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
@@ -640,14 +607,12 @@ struct XAigerWriter
 
 			f << "r";
 			std::string buffer_str = r_buffer.str();
-			int32_t buffer_size_be = to_big_endian(buffer_str.size());
-			f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
+			write_buffer(f, buffer_str.size());
 			f.write(buffer_str.data(), buffer_str.size());
 
 			f << "s";
 			buffer_str = s_buffer.str();
-			buffer_size_be = to_big_endian(buffer_str.size());
-			f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
+			write_buffer(f, buffer_str.size());
 			f.write(buffer_str.data(), buffer_str.size());
 
 			RTLIL::Design *holes_design;
@@ -664,22 +629,19 @@ struct XAigerWriter
 
 				f << "a";
 				std::string buffer_str = a_buffer.str();
-				int32_t buffer_size_be = to_big_endian(buffer_str.size());
-				f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
+				write_buffer(f, buffer_str.size());
 				f.write(buffer_str.data(), buffer_str.size());
 			}
 		}
 
 		f << "h";
 		std::string buffer_str = h_buffer.str();
-		int32_t buffer_size_be = to_big_endian(buffer_str.size());
-		f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
+		write_buffer(f, buffer_str.size());
 		f.write(buffer_str.data(), buffer_str.size());
 
 		f << "i";
 		buffer_str = i_buffer.str();
-		buffer_size_be = to_big_endian(buffer_str.size());
-		f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
+		write_buffer(f, buffer_str.size());
 		f.write(buffer_str.data(), buffer_str.size());
 		//f << "o";
 		//buffer_str = o_buffer.str();

From 89cbca4f44aec2912024a0f60d8a14244bf323f9 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 3 Sep 2024 09:15:12 +0200
Subject: [PATCH 477/499] Add macOS instructions for latexpdf

---
 README.md | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/README.md b/README.md
index c806ec28340..d215d844201 100644
--- a/README.md
+++ b/README.md
@@ -638,6 +638,12 @@ build process for the website.  Or, run the following:
 
 	$ sudo apt install texlive-latex-base texlive-latex-extra latexmk
 
+Or for MacOS, using homebrew:
+
+  $ brew install basictex
+  $ sudo tlmgr update --self   
+  $ sudo tlmgr install collection-latexextra latexmk tex-gyre
+
 The Python package, Sphinx, is needed along with those listed in
 `docs/source/requirements.txt`:
 

From 556c705a897015f940fa4199fc1c9cfb70f5b850 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 3 Sep 2024 10:15:50 +0200
Subject: [PATCH 478/499] Cleanup of synth_nanoxplore pass

---
 techlibs/nanoxplore/synth_nanoxplore.cc | 13 +------------
 1 file changed, 1 insertion(+), 12 deletions(-)

diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index 8349caa21d5..4674559fb96 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -53,7 +53,6 @@ struct SynthNanoXplorePass : public ScriptPass
 		log("        - medium: NG-Medium\n");
 		log("        - large: NG-Large\n");
 		log("        - ultra: NG-Ultra\n");
-		log("        - u300: NG-Ultra300\n");
 		log("\n");
 		log("    -json <file>\n");
 		log("        write the design to the specified JSON file. writing of an output file\n");
@@ -90,9 +89,6 @@ struct SynthNanoXplorePass : public ScriptPass
 		log("    -nobram\n");
 		log("        do not use block NX_RAM cells in output netlist\n");
 		log("\n");
-		log("    -nodsp\n");
-		log("        do not map multipliers to NX_DSP cells\n");
-		log("\n");
 		log("    -noiopad\n");
 		log("        do not insert IO buffers\n");
 		log("\n");
@@ -108,7 +104,7 @@ struct SynthNanoXplorePass : public ScriptPass
 	}
 
 	string top_opt, json_file, family;
-	bool flatten, abc9, nocy, nodffe, norfram, nobram, nodsp, noiopad, no_rw_check;
+	bool flatten, abc9, nocy, nodffe, norfram, nobram, noiopad, no_rw_check;
 	std::string postfix;
 	int min_ce_use, min_srst_use;
 
@@ -123,7 +119,6 @@ struct SynthNanoXplorePass : public ScriptPass
 		nodffe = false;
 		norfram = false;
 		nobram = false;
-		nodsp = false;
 		noiopad = false;
 		no_rw_check = false;
 		postfix = "";
@@ -195,10 +190,6 @@ struct SynthNanoXplorePass : public ScriptPass
 				nobram = true;
 				continue;
 			}
-			if (args[argidx] == "-nodsp") {
-				nodsp = true;
-				continue;
-			}
 			if (args[argidx] == "-iopad") {
 				noiopad = false;
 				continue;
@@ -222,8 +213,6 @@ struct SynthNanoXplorePass : public ScriptPass
 
 		if (family == "ultra") {
 			postfix = "_u";
-		} else if (family == "u300") {
-			postfix = "_u";
 		} else if (family == "medium") {
 			postfix = "_m";
 		} else if (family == "large") {

From 3e0dc2ff1ee0dfec10e96b7eaaa774231ba4a248 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 3 Sep 2024 10:28:56 +0200
Subject: [PATCH 479/499] Release version 0.45

---
 CHANGELOG           | 7 ++++++-
 Makefile            | 4 ++--
 docs/source/conf.py | 2 +-
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index 3d22bfe6008..855d6f59793 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,8 +2,13 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.44 .. Yosys 0.45-dev
+Yosys 0.44 .. Yosys 0.45
 --------------------------
+ * Various
+    - Added cell types help messages.
+
+ * New back-ends
+    - Added initial NG-Ultra support. ( synth_nanoxplore )
 
 Yosys 0.43 .. Yosys 0.44
 --------------------------
diff --git a/Makefile b/Makefile
index 209eac337c7..fc2955f1d74 100644
--- a/Makefile
+++ b/Makefile
@@ -153,7 +153,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.44+71
+YOSYS_VER := 0.45
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -169,7 +169,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 80ba43d.. | wc -l`/;" Makefile
+#	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 80ba43d.. | wc -l`/;" Makefile
 
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
 
diff --git a/docs/source/conf.py b/docs/source/conf.py
index 723a0ea7fc4..4b7dc1737a3 100644
--- a/docs/source/conf.py
+++ b/docs/source/conf.py
@@ -5,7 +5,7 @@
 project = 'YosysHQ Yosys'
 author = 'YosysHQ GmbH'
 copyright ='2024 YosysHQ GmbH'
-yosys_ver = "0.44"
+yosys_ver = "0.45"
 
 # select HTML theme
 html_theme = 'furo'

From 9ed031ddd588442f22be13ce608547a5809b62f0 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 3 Sep 2024 12:28:25 +0200
Subject: [PATCH 480/499] Fix TODOs in docs

---
 docs/source/conf.py | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/docs/source/conf.py b/docs/source/conf.py
index 4b7dc1737a3..4371b79f16a 100644
--- a/docs/source/conf.py
+++ b/docs/source/conf.py
@@ -70,12 +70,12 @@
     if rtds_version == "latest":
         release = yosys_ver + "-dev"
         todo_include_todos = False
-    elif rtds_version.startswith("yosys-"):
-        release = yosys_ver
-        todo_include_todos = False
-    else:
+    elif rtds_version.startswith("docs"):
         release = rtds_version
         todo_include_todos = True
+    else:
+        release = yosys_ver
+        todo_include_todos = False
 else:
     release = yosys_ver
     todo_include_todos = True

From 8b29629ca9873e7caff091223170e33014598aed Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 23 Aug 2024 09:05:44 +1200
Subject: [PATCH 481/499] smtr: Fork smtlib for rosette

---
 backends/functional/Makefile.inc      |   1 +
 backends/functional/smtlib_rosette.cc | 303 ++++++++++++++++++++++++++
 2 files changed, 304 insertions(+)
 create mode 100644 backends/functional/smtlib_rosette.cc

diff --git a/backends/functional/Makefile.inc b/backends/functional/Makefile.inc
index 13c962c99ff..16d1c054273 100644
--- a/backends/functional/Makefile.inc
+++ b/backends/functional/Makefile.inc
@@ -1,3 +1,4 @@
 OBJS += backends/functional/cxx.o
 OBJS += backends/functional/smtlib.o
+OBJS += backends/functional/smtlib_rosette.o
 OBJS += backends/functional/test_generic.o
diff --git a/backends/functional/smtlib_rosette.cc b/backends/functional/smtlib_rosette.cc
new file mode 100644
index 00000000000..601f311af96
--- /dev/null
+++ b/backends/functional/smtlib_rosette.cc
@@ -0,0 +1,303 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
+ *  Copyright (C) 2024 National Technology and Engineering Solutions of Sandia, LLC
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/functional.h"
+#include "kernel/yosys.h"
+#include "kernel/sexpr.h"
+#include <ctype.h>
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+using SExprUtil::list;
+
+const char *reserved_keywords[] = {
+	// reserved keywords from the racket spec
+	"struct", "lambda", "values", "extract", "concat", "bv", "let", "define", "cons", "list", "read", "write",
+	"stream", "error", "raise", "exit", "for", "for/list", "begin", "when", "unless", "module", "require",
+	"provide", "apply", "if", "cond", "even", "odd", "any", "and", "or", "match", "match-define", "values",
+
+	// reserved for our own purposes
+	"inputs", "state", "name",
+	nullptr
+};
+
+struct SmtrScope : public Functional::Scope<int> {
+	SmtrScope() {
+		for(const char **p = reserved_keywords; *p != nullptr; p++)
+			reserve(*p);
+	}
+	bool is_character_legal(char c, int index) override {
+		return isascii(c) && (isalpha(c) || (isdigit(c) && index > 0) || strchr("~!@$%^&*_-+=<>.?/", c));
+	}
+};
+
+struct SmtrSort {
+	Functional::Sort sort;
+	SmtrSort(Functional::Sort sort) : sort(sort) {}
+	SExpr to_sexpr() const {
+		if(sort.is_memory()) {
+			return list("list", list("bitvector", sort.addr_width()), list("bitvector", sort.data_width()));
+		} else if(sort.is_signal()) {
+			return list("bitvector", sort.width());
+		} else {
+			log_error("unknown sort");
+		}
+	}
+};
+
+class SmtrStruct {
+	struct Field {
+		SmtrSort sort;
+		std::string accessor;
+		std::string name;
+	};
+	idict<IdString> field_names;
+	vector<Field> fields;
+	SmtrScope &scope;
+public:
+	std::string name;
+	SmtrStruct(std::string name, SmtrScope &scope) : scope(scope), name(name) {}
+	void insert(IdString field_name, SmtrSort sort) {
+		field_names(field_name);
+		auto base_name = RTLIL::unescape_id(field_name);
+		auto accessor = name + "-" + base_name;
+		scope.reserve(accessor);
+		fields.emplace_back(Field{sort, accessor, base_name});
+	}
+	void write_definition(SExprWriter &w) {
+		vector<SExpr> field_list;
+		for(const auto &field : fields) {
+			field_list.emplace_back(field.name);
+		}
+		w.push();
+		w.open(list("struct", name, field_list, "#:transparent"));
+		if (field_names.size()) {
+			for (const auto &field : fields) {
+				auto bv_type = field.sort.to_sexpr();
+				w.comment(field.name + " " + bv_type.to_string());
+			}
+		}
+		w.pop();
+	}
+	template<typename Fn> void write_value(SExprWriter &w, Fn fn) {
+		w.open(list(name));
+		for(auto field_name : field_names) {
+			w << fn(field_name);
+			w.comment(RTLIL::unescape_id(field_name), true);
+		}
+		w.close();
+	}
+	SExpr access(SExpr record, IdString name) {
+		size_t i = field_names.at(name);
+		return list(fields[i].accessor, std::move(record));
+	}
+};
+
+std::string smt_const(RTLIL::Const const &c) {
+	std::string s = "#b";
+	for(int i = c.size(); i-- > 0; )
+		s += c[i] == State::S1 ? '1' : '0';
+	return s;
+}
+
+struct SmtrPrintVisitor : public Functional::AbstractVisitor<SExpr> {
+	using Node = Functional::Node;
+	std::function<SExpr(Node)> n;
+	SmtrStruct &input_struct;
+	SmtrStruct &state_struct;
+
+	SmtrPrintVisitor(SmtrStruct &input_struct, SmtrStruct &state_struct) : input_struct(input_struct), state_struct(state_struct) {}
+
+	SExpr from_bool(SExpr &&arg) {
+		return list("bool->bitvector", std::move(arg));
+	}
+	SExpr to_bool(SExpr &&arg) {
+		return list("bitvector->bool", std::move(arg));
+	}
+	SExpr to_list(SExpr &&arg) {
+		return list("bitvector->bits", std::move(arg));
+	}
+
+	SExpr buf(Node, Node a) override { return n(a); }
+	SExpr slice(Node, Node a, int offset, int out_width) override { return list("extract", offset + out_width - 1, offset, n(a)); }
+	SExpr zero_extend(Node, Node a, int out_width) override { return list("zero-extend", n(a), list("bitvector", out_width)); }
+	SExpr sign_extend(Node, Node a, int out_width) override { return list("sign-extend", n(a), list("bitvector", out_width)); }
+	SExpr concat(Node, Node a, Node b) override { return list("concat", n(b), n(a)); }
+	SExpr add(Node, Node a, Node b) override { return list("bvadd", n(a), n(b)); }
+	SExpr sub(Node, Node a, Node b) override { return list("bvsub", n(a), n(b)); }
+	SExpr mul(Node, Node a, Node b) override { return list("bvmul", n(a), n(b)); }
+	SExpr unsigned_div(Node, Node a, Node b) override { return list("bvudiv", n(a), n(b)); }
+	SExpr unsigned_mod(Node, Node a, Node b) override { return list("bvurem", n(a), n(b)); }
+	SExpr bitwise_and(Node, Node a, Node b) override { return list("bvand", n(a), n(b)); }
+	SExpr bitwise_or(Node, Node a, Node b) override { return list("bvor", n(a), n(b)); }
+	SExpr bitwise_xor(Node, Node a, Node b) override { return list("bvxor", n(a), n(b)); }
+	SExpr bitwise_not(Node, Node a) override { return list("bvnot", n(a)); }
+	SExpr unary_minus(Node, Node a) override { return list("bvneg", n(a)); }
+	SExpr reduce_and(Node, Node a) override { return list("apply", "bvand", to_list(n(a))); }
+	SExpr reduce_or(Node, Node a) override { return list("apply", "bvor", to_list(n(a))); }
+	SExpr reduce_xor(Node, Node a) override { return list("apply", "bvxor", to_list(n(a))); }
+	SExpr equal(Node, Node a, Node b) override { return from_bool(list("bveq", n(a), n(b))); }
+	SExpr not_equal(Node, Node a, Node b) override { return from_bool(list("not", list("bveq", n(a), n(b)))); }
+	SExpr signed_greater_than(Node, Node a, Node b) override { return from_bool(list("bvsgt", n(a), n(b))); }
+	SExpr signed_greater_equal(Node, Node a, Node b) override { return from_bool(list("bvsge", n(a), n(b))); }
+	SExpr unsigned_greater_than(Node, Node a, Node b) override { return from_bool(list("bvugt", n(a), n(b))); }
+	SExpr unsigned_greater_equal(Node, Node a, Node b) override { return from_bool(list("bvuge", n(a), n(b))); }
+
+	SExpr extend(SExpr &&a, int in_width, int out_width) {
+		if(in_width < out_width)
+			return list("zero-extend", std::move(a), list("bitvector", out_width));
+		else
+			return std::move(a);
+	}
+	SExpr logical_shift_left(Node, Node a, Node b) override { return list("bvshl", n(a), extend(n(b), b.width(), a.width())); }
+	SExpr logical_shift_right(Node, Node a, Node b) override { return list("bvlshr", n(a), extend(n(b), b.width(), a.width())); }
+	SExpr arithmetic_shift_right(Node, Node a, Node b) override { return list("bvashr", n(a), extend(n(b), b.width(), a.width())); }
+	SExpr mux(Node, Node a, Node b, Node s) override { return list("if", to_bool(n(s)), n(b), n(a)); }
+	SExpr constant(Node, RTLIL::Const const& value) override { return list("bv", smt_const(value), value.size()); }
+	SExpr memory_read(Node, Node mem, Node addr) override { return list("list-ref-bv", n(mem), n(addr)); }
+	SExpr memory_write(Node, Node mem, Node addr, Node data) override { return list("list-set-bv", n(mem), n(addr), n(data)); }
+
+	SExpr input(Node, IdString name, IdString kind) override { log_assert(kind == ID($input)); return input_struct.access("inputs", name); }
+	SExpr state(Node, IdString name, IdString kind) override { log_assert(kind == ID($state)); return state_struct.access("state", name); }
+};
+
+struct SmtrModule {
+	Functional::IR ir;
+	SmtrScope scope;
+	std::string name;
+	
+	SmtrStruct input_struct;
+	SmtrStruct output_struct;
+	SmtrStruct state_struct;
+
+	SmtrModule(Module *module)
+		: ir(Functional::IR::from_module(module))
+		, scope()
+		, name(scope.unique_name(module->name))
+		, input_struct(scope.unique_name(module->name.str() + "_Inputs"), scope)
+		, output_struct(scope.unique_name(module->name.str() + "_Outputs"), scope)
+		, state_struct(scope.unique_name(module->name.str() + "_State"), scope)
+	{
+		scope.reserve(name + "_initial");
+		for (auto input : ir.inputs())
+			input_struct.insert(input->name, input->sort);
+		for (auto output : ir.outputs())
+			output_struct.insert(output->name, output->sort);
+		for (auto state : ir.states())
+			state_struct.insert(state->name, state->sort);
+	}
+
+	void write(std::ostream &out)
+	{    
+		SExprWriter w(out);
+
+		input_struct.write_definition(w);
+		output_struct.write_definition(w);
+		state_struct.write_definition(w);
+
+		w.push();
+		w.open(list("define", list(name, "inputs", "state")));
+		auto inlined = [&](Functional::Node n) {
+			return n.fn() == Functional::Fn::constant;
+		};
+		SmtrPrintVisitor visitor(input_struct, state_struct);
+		auto node_to_sexpr = [&](Functional::Node n) -> SExpr {
+			if(inlined(n))
+				return n.visit(visitor);
+			else
+				return scope(n.id(), n.name());
+		};
+		visitor.n = node_to_sexpr;
+		for(auto n : ir)
+			if(!inlined(n)) {
+				w.open(list("let", list(list(node_to_sexpr(n), n.visit(visitor)))), false);
+				w.comment(SmtrSort(n.sort()).to_sexpr().to_string(), true);
+			}
+		w.open(list("cons"));
+		output_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.output(name).value()); });
+		state_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.state(name).next_value()); });
+		w.pop();
+
+		w.push();
+		auto initial = name + "_initial";
+		w.open(list("define", initial));
+		w.open(list(state_struct.name));
+		for (auto state : ir.states()) {
+			if (state->sort.is_signal())
+				w << list("bv", smt_const(state->initial_value_signal()), state->sort.width());
+			else if (state->sort.is_memory()) {
+				const auto &contents = state->initial_value_memory();
+				w.open(list("list"));
+				for(int i = 0; i < 1<<state->sort.addr_width(); i++) {
+					w << list("bv", smt_const(contents[i]), state->sort.data_width());
+				}
+				w.close();
+			}
+		}
+		w.pop();
+	}
+};
+
+struct FunctionalSmtrBackend : public Backend {
+	FunctionalSmtrBackend() : Backend("functional_rosette", "Generate Rosette compatible Racket from Functional IR") {}
+
+    	void help() override {
+        	//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    write_functional_rosette [options] [selection] [filename]\n");
+		log("\n");
+		log("Functional Rosette Backend.\n");
+		log("\n");
+		log("    -provides\n");
+		log("        include 'provide' statement(s) for loading output as a module\n");
+		log("\n");
+	}
+
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		auto provides = false;
+
+		log_header(design, "Executing Functional Rosette Backend.\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-provides")
+				provides = true;
+			else
+				break;
+		}
+		extra_args(f, filename, args, argidx);
+
+		*f << "#lang rosette\n";
+		if (provides) {
+			*f << "(provide (all-defined-out))\n";
+		}
+
+		for (auto module : design->selected_modules()) {
+			log("Processing module `%s`.\n", module->name.c_str());
+			SmtrModule smtr(module);
+			smtr.write(*f);
+		}
+	}
+} FunctionalSmtrBackend;
+
+PRIVATE_NAMESPACE_END

From 7fe9157df2f38c871cdb912cd2150ea701574358 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 23 Aug 2024 09:05:44 +1200
Subject: [PATCH 482/499] smtr: Add rkt to functional tests

---
 tests/functional/.gitignore         |   1 +
 tests/functional/rkt_vcd.py         | 115 ++++++++++++++++++++++++++++
 tests/functional/test_functional.py |  13 ++++
 3 files changed, 129 insertions(+)
 create mode 100644 tests/functional/rkt_vcd.py

diff --git a/tests/functional/.gitignore b/tests/functional/.gitignore
index 1ffe9926ef6..f0c4cf14e45 100644
--- a/tests/functional/.gitignore
+++ b/tests/functional/.gitignore
@@ -3,3 +3,4 @@ my_module_functional_cxx.cc
 vcd_harness
 *.vcd
 *.smt2
+*.rkt
diff --git a/tests/functional/rkt_vcd.py b/tests/functional/rkt_vcd.py
new file mode 100644
index 00000000000..1b2cf31e384
--- /dev/null
+++ b/tests/functional/rkt_vcd.py
@@ -0,0 +1,115 @@
+from __future__ import annotations
+from pathlib import Path
+import re
+import subprocess
+from typing import Dict, List, Tuple
+from random import Random
+
+vcd_version = "Yosys/tests/functional/rkt_vcd.py"
+StepList = List[Tuple[int, str]]
+SignalStepMap = Dict[str, StepList]
+SignalWidthMap = Dict[str, int]
+
+def write_vcd(filename: Path, signals: SignalStepMap, timescale='1 ns', date='today'):
+    with open(filename, 'w') as f:
+        # Write the header
+        f.write(f"$date\n    {date}\n$end\n")
+        f.write(f"$timescale {timescale} $end\n")
+        
+        # Declare signals
+        f.write("$scope module gold $end\n")
+        for signal_name, changes in signals.items():
+            signal_size = len(changes[0][1])
+            f.write(f"$var wire {signal_size - 1} {signal_name} {signal_name} $end\n")
+        f.write("$upscope $end\n")
+        f.write("$enddefinitions $end\n")
+        
+        # Collect all unique timestamps
+        timestamps = sorted(set(time for changes in signals.values() for time, _ in changes))
+        
+        # Write initial values
+        f.write("#0\n")
+        for signal_name, changes in signals.items():
+            for time, value in changes:
+                if time == 0:
+                    f.write(f"{value} {signal_name}\n")
+        
+        # Write value changes
+        for time in timestamps:
+            if time != 0:
+                f.write(f"#{time}\n")
+                for signal_name, changes in signals.items():
+                    for change_time, value in changes:
+                        if change_time == time:
+                            f.write(f"{value} {signal_name}\n")
+
+def simulate_rosette(rkt_file_path: Path, vcd_path: Path, num_steps: int, rnd: Random):
+    signals: dict[str, list[str]] = {}
+    inputs: SignalWidthMap = {}
+    outputs: SignalWidthMap = {}
+
+    current_struct_name: str = ""
+    with open(rkt_file_path, 'r') as rkt_file:
+        for line in rkt_file:
+            m = re.search(r'gold_(Inputs|Outputs|State)', line)
+            if m:
+                current_struct_name = m.group(1)
+                if current_struct_name == "State": break
+            elif not current_struct_name: continue # skip lines before structs
+            m = re.search(r'; (.+?)\b \(bitvector (\d+)\)', line)
+            if not m: continue # skip non matching lines (probably closing the struct)
+            signal = m.group(1)
+            width = int(m.group(2))
+            if current_struct_name == "Inputs":
+                inputs[signal] = width
+            elif current_struct_name == "Outputs":
+                outputs[signal] = width
+
+    for signal, width in inputs.items():
+        step_list: list[int] = []
+        for step in range(num_steps):
+            value = rnd.getrandbits(width)
+            binary_string = format(value, '0{}b'.format(width))
+            step_list.append(binary_string)
+        signals[signal] = step_list
+
+    test_rkt_file_path = rkt_file_path.with_suffix('.tst.rkt')
+    with open(test_rkt_file_path, 'w') as test_rkt_file:
+        test_rkt_file.writelines([
+            '#lang rosette\n',
+            f'(require "{rkt_file_path.name}")\n',
+        ])
+
+        for step in range(num_steps):
+            this_step = f"step_{step}"
+            value_list: list[str] = []
+            for signal, width in inputs.items():
+                value = signals[signal][step]
+                value_list.append(f"(bv #b{value} {width})")
+            gold_Inputs = f"(gold_Inputs {' '.join(value_list)})"
+            gold_State = f"(cdr step_{step-1})" if step else "gold_initial"
+            test_rkt_file.write(f"(define {this_step} (gold {gold_Inputs} {gold_State})) (car {this_step})\n")
+
+    cmd = ["racket", test_rkt_file_path]
+    status = subprocess.run(cmd, capture_output=True)
+    assert status.returncode == 0, f"{cmd[0]} failed"
+
+    for signal in outputs.keys():
+        signals[signal] = []
+
+    for line in status.stdout.decode().splitlines():
+        m = re.match(r'\(gold_Outputs( \(bv \S+ \d+\))+\)', line)
+        assert m, f"Incomplete output definition {line!r}"
+        for output, (value, width) in zip(outputs.keys(), re.findall(r'\(bv (\S+) (\d+)\)', line)):
+            assert isinstance(value, str), f"Bad value {value!r}"
+            assert value.startswith(('#b', '#x')), f"Non-binary value {value!r}"
+            assert int(width) == outputs[output], f"Width mismatch for output {output!r} (got {width}, expected {outputs[output]})"
+            int_value = int(value[2:], 16 if value.startswith('#x') else 2)
+            binary_string = format(int_value, '0{}b'.format(width))
+            signals[output].append(binary_string)
+
+    vcd_signals: SignalStepMap = {}
+    for signal, steps in signals.items():
+        vcd_signals[signal] = [(time, f"b{value}") for time, value in enumerate(steps)]
+
+    write_vcd(vcd_path, vcd_signals)
diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py
index 55e4acc3340..3b006676a14 100644
--- a/tests/functional/test_functional.py
+++ b/tests/functional/test_functional.py
@@ -72,6 +72,19 @@ def test_smt(cell, parameters, tmp_path, num_steps, rnd):
     smt_vcd.simulate_smt(smt_file, vcd_functional_file, num_steps, rnd(cell.name + "-smt"))
     yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
 
+def test_rkt(cell, parameters, tmp_path, num_steps, rnd):
+    import rkt_vcd
+
+    rtlil_file = tmp_path / 'rtlil.il'
+    rkt_file = tmp_path / 'smtlib.rkt'
+    vcd_functional_file = tmp_path / 'functional.vcd'
+    vcd_yosys_sim_file = tmp_path / 'yosys.vcd'
+
+    cell.write_rtlil_file(rtlil_file, parameters)
+    yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_rosette -provides {quote(rkt_file)}")
+    rkt_vcd.simulate_rosette(rkt_file, vcd_functional_file, num_steps, rnd(cell.name + "-rkt"))
+    yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
+
 def test_print_graph(tmp_path):
     tb_file = base_path / 'tests/functional/picorv32_tb.v'
     cpu_file = base_path / 'tests/functional/picorv32.v'

From 07b69080191c2112e817334d313e5e6d944d3a66 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 30 Aug 2024 09:56:08 +1200
Subject: [PATCH 483/499] smtr: Use rosette/safe

---
 backends/functional/smtlib_rosette.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/functional/smtlib_rosette.cc b/backends/functional/smtlib_rosette.cc
index 601f311af96..f2395374799 100644
--- a/backends/functional/smtlib_rosette.cc
+++ b/backends/functional/smtlib_rosette.cc
@@ -287,7 +287,7 @@ struct FunctionalSmtrBackend : public Backend {
 		}
 		extra_args(f, filename, args, argidx);
 
-		*f << "#lang rosette\n";
+		*f << "#lang rosette/safe\n";
 		if (provides) {
 			*f << "(provide (all-defined-out))\n";
 		}

From 5a29b3e1724e45b6d7afe30f3ebb3e7546f8845e Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 30 Aug 2024 10:44:35 +1200
Subject: [PATCH 484/499] smtr: More sanitization

---
 backends/functional/smtlib_rosette.cc | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/backends/functional/smtlib_rosette.cc b/backends/functional/smtlib_rosette.cc
index f2395374799..4e60576946b 100644
--- a/backends/functional/smtlib_rosette.cc
+++ b/backends/functional/smtlib_rosette.cc
@@ -31,8 +31,12 @@ using SExprUtil::list;
 const char *reserved_keywords[] = {
 	// reserved keywords from the racket spec
 	"struct", "lambda", "values", "extract", "concat", "bv", "let", "define", "cons", "list", "read", "write",
-	"stream", "error", "raise", "exit", "for", "for/list", "begin", "when", "unless", "module", "require",
-	"provide", "apply", "if", "cond", "even", "odd", "any", "and", "or", "match", "match-define", "values",
+	"stream", "error", "raise", "exit", "for", "begin", "when", "unless", "module", "require", "provide", "apply",
+	"if", "cond", "even", "odd", "any", "and", "or", "match", "command-line", "ffi-lib", "thread", "kill", "sync",
+	"future", "touch", "subprocess", "make-custodian", "custodian-shutdown-all", "current-custodian", "make", "tcp",
+	"connect", "prepare", "malloc", "free", "_fun", "_cprocedure", "build", "path", "file", "peek", "bytes",
+	"flush", "with", "lexer", "parser", "syntax", "interface", "send", "make-object", "new", "instantiate",
+	"define-generics", "set",
 
 	// reserved for our own purposes
 	"inputs", "state", "name",
@@ -45,7 +49,7 @@ struct SmtrScope : public Functional::Scope<int> {
 			reserve(*p);
 	}
 	bool is_character_legal(char c, int index) override {
-		return isascii(c) && (isalpha(c) || (isdigit(c) && index > 0) || strchr("~!@$%^&*_-+=<>.?/", c));
+		return isascii(c) && (isalpha(c) || (isdigit(c) && index > 0) || strchr("@$%^&_+=.", c));
 	}
 };
 

From a2abbcb33f3ae1c2287b4b2a3b9e419494ab8aa0 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 3 Sep 2024 22:05:17 +1200
Subject: [PATCH 485/499] smtr: Use scope.unique_name

---
 backends/functional/smtlib_rosette.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/functional/smtlib_rosette.cc b/backends/functional/smtlib_rosette.cc
index 4e60576946b..ff47f5706d1 100644
--- a/backends/functional/smtlib_rosette.cc
+++ b/backends/functional/smtlib_rosette.cc
@@ -81,7 +81,7 @@ class SmtrStruct {
 	SmtrStruct(std::string name, SmtrScope &scope) : scope(scope), name(name) {}
 	void insert(IdString field_name, SmtrSort sort) {
 		field_names(field_name);
-		auto base_name = RTLIL::unescape_id(field_name);
+		auto base_name = scope.unique_name("\\" + RTLIL::unescape_id(field_name));
 		auto accessor = name + "-" + base_name;
 		scope.reserve(accessor);
 		fields.emplace_back(Field{sort, accessor, base_name});

From d6c5e13bf31043173adf5667b7edc7d9940293db Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 3 Sep 2024 22:23:41 +1200
Subject: [PATCH 486/499] smtr: Structs have local scope

Also unique_name can take field_name directly.
---
 backends/functional/smtlib_rosette.cc | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/backends/functional/smtlib_rosette.cc b/backends/functional/smtlib_rosette.cc
index ff47f5706d1..ea14da85428 100644
--- a/backends/functional/smtlib_rosette.cc
+++ b/backends/functional/smtlib_rosette.cc
@@ -75,15 +75,16 @@ class SmtrStruct {
 	};
 	idict<IdString> field_names;
 	vector<Field> fields;
-	SmtrScope &scope;
+	SmtrScope &global_scope;
+	SmtrScope local_scope;
 public:
 	std::string name;
-	SmtrStruct(std::string name, SmtrScope &scope) : scope(scope), name(name) {}
+	SmtrStruct(std::string name, SmtrScope &scope) : global_scope(scope), local_scope(), name(name) {}
 	void insert(IdString field_name, SmtrSort sort) {
 		field_names(field_name);
-		auto base_name = scope.unique_name("\\" + RTLIL::unescape_id(field_name));
+		auto base_name = local_scope.unique_name(field_name);
 		auto accessor = name + "-" + base_name;
-		scope.reserve(accessor);
+		global_scope.reserve(accessor);
 		fields.emplace_back(Field{sort, accessor, base_name});
 	}
 	void write_definition(SExprWriter &w) {

From 0744fac883232fda4106a09100abf6f88eab1220 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 3 Sep 2024 12:39:38 +0200
Subject: [PATCH 487/499] Next dev cycle

---
 CHANGELOG | 3 +++
 Makefile  | 4 ++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index 855d6f59793..03bf5ac57c3 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 List of major changes and improvements between releases
 =======================================================
 
+Yosys 0.45 .. Yosys 0.46-dev
+--------------------------
+
 Yosys 0.44 .. Yosys 0.45
 --------------------------
  * Various
diff --git a/Makefile b/Makefile
index fc2955f1d74..61dc51bd529 100644
--- a/Makefile
+++ b/Makefile
@@ -153,7 +153,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.45
+YOSYS_VER := 0.45+0
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -169,7 +169,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-#	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 80ba43d.. | wc -l`/;" Makefile
+	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9ed031d.. | wc -l`/;" Makefile
 
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
 

From 75ed6d38fc20f490d0b8adcacf6bd26c5e1a8613 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Tue, 3 Sep 2024 14:21:56 +0100
Subject: [PATCH 488/499] fix rst formatting in functional_ir.rst

---
 .../extending_yosys/functional_ir.rst         | 115 ++++++++++--------
 1 file changed, 61 insertions(+), 54 deletions(-)

diff --git a/docs/source/yosys_internals/extending_yosys/functional_ir.rst b/docs/source/yosys_internals/extending_yosys/functional_ir.rst
index 38d00055627..29aaf398c28 100644
--- a/docs/source/yosys_internals/extending_yosys/functional_ir.rst
+++ b/docs/source/yosys_internals/extending_yosys/functional_ir.rst
@@ -3,7 +3,7 @@ Writing a new backend using FunctionalIR
 
 To simplify the writing of backends for functional languages or similar targets, Yosys provides an alternative intermediate representation called FunctionalIR which maps more directly on those targets.
 
-FunctionalIR represents the design as a function `(inputs, current_state) -> (outputs, next_state)`.
+FunctionalIR represents the design as a function ``(inputs, current_state) -> (outputs, next_state)``.
 This function is broken down into a series of assignments to variables.
 Each assignment is a simple operation, such as an addition.
 Complex operations are broken up into multiple steps.
@@ -14,72 +14,79 @@ We can thus treat variables and assignments as equivalent and, since this is a g
 Unlike RTLIL's cells and wires representation, this representation is strictly ordered (topologically sorted) with definitions preceding their use.
 
 Every node has a "sort" (the FunctionalIR term for what might otherwise be called a "type"). The sorts available are
-- `bit[n]` for an `n`-bit bitvector, and
-- `memory[n,m]` for an immutable array of `2**n` values of sort `bit[m]`.
 
-In terms of actual code, Yosys provides a class `Functional::IR` that represents a design in FunctionalIR.
-`Functional::IR::from_module` generates an instance from an RTLIL module.
+- ``bit[n]`` for an ``n``-bit bitvector, and
+- ``memory[n,m]`` for an immutable array of ``2**n`` values of sort ``bit[m]``.
+
+In terms of actual code, Yosys provides a class ``Functional::IR`` that represents a design in FunctionalIR.
+``Functional::IR::from_module`` generates an instance from an RTLIL module.
 The entire design is stored as a whole in an internal data structure.
-To access the design, the `Functional::Node` class provides a reference to a particular node in the design.
-The `Functional::IR` class supports the syntax `for(auto node : ir)` to iterate over every node.
+To access the design, the ``Functional::Node`` class provides a reference to a particular node in the design.
+The ``Functional::IR`` class supports the syntax ``for(auto node : ir)`` to iterate over every node.
 
-`Functional::IR` also keeps track of inputs, outputs and states.
+``Functional::IR`` also keeps track of inputs, outputs and states.
 By a "state" we mean a pair of a "current state" input and a "next state" output.
 One such pair is created for every register and for every memory.
 Every input, output and state has a name (equal to their name in RTLIL), a sort and a kind.
-The kind field usually remains as the default value `$input`, `$output` or `$state`, however some RTLIL cells such as `$assert` or `$anyseq` generate auxiliary inputs/outputs/states that are given a different kind to distinguish them from ordinary RTLIL inputs/outputs/states.
-- To access an individual input/output/state, use `ir.input(name, kind)`, `ir.output(name, kind)` or `ir.state(name, kind)`. `kind` defaults to the default kind.
-- To iterate over all inputs/outputs/states of a certain kind, methods `ir.inputs`, `ir.outputs`, `ir.states` are provided. Their argument defaults to the default kinds mentioned.
-- To iterate over inputs/outputs/states of any kind, use `ir.all_inputs`, `ir.all_outputs` and `ir.all_states`.
-- Outputs have a node that indicate the value of the output, this can be retrieved via `output.value()`.
-- States have a node that indicate the next value of the state, this can be retrieved via `state.next_value()`.
-  They also have an initial value that is accessed as either `state.initial_value_signal()` or `state.initial_value_memory()`, depending on their sort.
-
-Each node has a "function", which defines its operation (for a complete list of functions and a specification of their operation, see `functional.h`).
-Functions are represented as an enum `Functional::Fn` and the function field can be accessed as `node.fn()`.
-Since the most common operation is a switch over the function that also accesses the arguments, the `Node` class provides a method `visit` that implements the visitor pattern.
-For example, for an addition node `node` with arguments `n1` and `n2`, `node.visit(visitor)` would call `visitor.add(node, n1, n2)`.
+The kind field usually remains as the default value ``$input``, ``$output`` or ``$state``, however some RTLIL cells such as ``$assert`` or ``$anyseq`` generate auxiliary inputs/outputs/states that are given a different kind to distinguish them from ordinary RTLIL inputs/outputs/states.
+
+- To access an individual input/output/state, use ``ir.input(name, kind)``, ``ir.output(name, kind)`` or ``ir.state(name, kind)``. ``kind`` defaults to the default kind.
+- To iterate over all inputs/outputs/states of a certain kind, methods ``ir.inputs``, ``ir.outputs``, ``ir.states`` are provided. Their argument defaults to the default kinds mentioned.
+- To iterate over inputs/outputs/states of any kind, use ``ir.all_inputs``, ``ir.all_outputs`` and ``ir.all_states``.
+- Outputs have a node that indicate the value of the output, this can be retrieved via ``output.value()``.
+- States have a node that indicate the next value of the state, this can be retrieved via ``state.next_value()``.
+  They also have an initial value that is accessed as either ``state.initial_value_signal()`` or ``state.initial_value_memory()``, depending on their sort.
+
+Each node has a "function", which defines its operation (for a complete list of functions and a specification of their operation, see ``functional.h``).
+Functions are represented as an enum ``Functional::Fn`` and the function field can be accessed as ``node.fn()``.
+Since the most common operation is a switch over the function that also accesses the arguments, the ``Node`` class provides a method ``visit`` that implements the visitor pattern.
+For example, for an addition node ``node`` with arguments ``n1`` and ``n2``, ``node.visit(visitor)`` would call ``visitor.add(node, n1, n2)``.
 Thus typically one would implement a class with a method for every function.
-Visitors should inherit from either `Functional::AbstractVisitor<ReturnType>` or `Functional::DefaultVisitor<ReturnType>`.
-The former will produce a compiler error if a case is unhandled, the latter will call `default_handler(node)` instead.
-Visitor methods should be marked as `override` to provide compiler errors if the arguments are wrong.
+Visitors should inherit from either ``Functional::AbstractVisitor<ReturnType>`` or ``Functional::DefaultVisitor<ReturnType>``.
+The former will produce a compiler error if a case is unhandled, the latter will call ``default_handler(node)`` instead.
+Visitor methods should be marked as ``override`` to provide compiler errors if the arguments are wrong.
 
 Utility classes
 -----------------
 
-`functional.h` also provides utility classes that are independent of the main FunctionalIR representation but are likely to be useful for backends.
+``functional.h`` also provides utility classes that are independent of the main FunctionalIR representation but are likely to be useful for backends.
 
-`Functional::Writer` provides a simple formatting class that wraps a `std::ostream` and provides the following methods:
-- `writer << value` wraps `os << value`.
-- `writer.print(fmt, value0, value1, value2, ...)` replaces `{0}`, `{1}`, `{2}`, etc in the string `fmt` with `value0`, `value1`, `value2`, resp.
-  Each value is formatted using `os << value`.
-  It is also possible to write `{}` to refer to one past the last index, i.e. `{1} {} {} {7} {}` is equivalent to `{1} {2} {3} {7} {8}`.
-- `writer.print_with(fn, fmt, value0, value1, value2, ...)` functions much the same as `print` but it uses `os << fn(value)` to print each value and falls back to `os << value` if `fn(value)` is not legal.
+``Functional::Writer`` provides a simple formatting class that wraps a ``std::ostream`` and provides the following methods:
 
-`Functional::Scope` keeps track of variable names in a target language.
+- ``writer << value`` wraps ``os << value``.
+- ``writer.print(fmt, value0, value1, value2, ...)`` replaces ``{0}``, ``{1}``, ``{2}``, etc in the string ``fmt`` with ``value0``, ``value1``, ``value2``, resp.
+  Each value is formatted using ``os << value``.
+  It is also possible to write ``{}`` to refer to one past the last index, i.e. ``{1} {} {} {7} {}`` is equivalent to ``{1} {2} {3} {7} {8}``.
+- ``writer.print_with(fn, fmt, value0, value1, value2, ...)`` functions much the same as ``print`` but it uses ``os << fn(value)`` to print each value and falls back to ``os << value`` if ``fn(value)`` is not legal.
+
+``Functional::Scope`` keeps track of variable names in a target language.
 It is used to translate between different sets of legal characters and to avoid accidentally re-defining identifiers.
-Users should derive a class from `Scope` and supply the following:
-- `Scope<Id>` takes a template argument that specifies a type that's used to uniquely distinguish variables.
-  Typically this would be `int` (if variables are used for `Functional::IR` nodes) or `IdString`.
-- The derived class should provide a constructor that calls `reserve` for every reserved word in the target language.
-- A method `bool is_legal_character(char c, int index)` has to be provided that returns `true` iff `c` is legal in an identifier at position `index`.
-Given an instance `scope` of the derived class, the following methods are then available:
-- `scope.reserve(std::string name)` marks the given name as being in-use
-- `scope.unique_name(IdString suggestion)` generates a previously unused name and attempts to make it similar to `suggestion`.
-- `scope(Id id, IdString suggestion)` functions similar to `unique_name`, except that multiple calls with the same `id` are guaranteed to retrieve the same name (independent of `suggestion`).
-
-`sexpr.h` provides classes that represent and pretty-print s-expressions.
-S-expressions can be constructed with `SExpr::list`, for example `SExpr expr = SExpr::list("add", "x", SExpr::list("mul", "y", "z"))` represents `(add x (mul y z))`
-(by adding `using SExprUtil::list` to the top of the file, `list` can be used as shorthand for `SExpr::list`).
-For prettyprinting, `SExprWriter` wraps an `std::ostream` and provides the following methods:
-- `writer << sexpr` writes the provided expression to the output, breaking long lines and adding appropriate indentation.
-- `writer.open(sexpr)` is similar to `writer << sexpr` but will omit the last closing parenthesis.
-  Further arguments can then be added separately with `<<` or `open`.
+Users should derive a class from ``Scope`` and supply the following:
+
+- ``Scope<Id>`` takes a template argument that specifies a type that's used to uniquely distinguish variables.
+  Typically this would be ``int`` (if variables are used for ``Functional::IR`` nodes) or ``IdString``.
+- The derived class should provide a constructor that calls ``reserve`` for every reserved word in the target language.
+- A method ``bool is_legal_character(char c, int index)`` has to be provided that returns ``true`` iff ``c`` is legal in an identifier at position ``index``.
+
+Given an instance ``scope`` of the derived class, the following methods are then available:
+
+- ``scope.reserve(std::string name)`` marks the given name as being in-use
+- ``scope.unique_name(IdString suggestion)`` generates a previously unused name and attempts to make it similar to ``suggestion``.
+- ``scope(Id id, IdString suggestion)`` functions similar to ``unique_name``, except that multiple calls with the same ``id`` are guaranteed to retrieve the same name (independent of ``suggestion``).
+
+``sexpr.h`` provides classes that represent and pretty-print s-expressions.
+S-expressions can be constructed with ``SExpr::list``, for example ``SExpr expr = SExpr::list("add", "x", SExpr::list("mul", "y", "z"))`` represents ``(add x (mul y z))``
+(by adding ``using SExprUtil::list`` to the top of the file, ``list`` can be used as shorthand for ``SExpr::list``).
+For prettyprinting, ``SExprWriter`` wraps an ``std::ostream`` and provides the following methods:
+
+- ``writer << sexpr`` writes the provided expression to the output, breaking long lines and adding appropriate indentation.
+- ``writer.open(sexpr)`` is similar to ``writer << sexpr`` but will omit the last closing parenthesis.
+  Further arguments can then be added separately with ``<<`` or ``open``.
   This allows for printing large s-expressions without needing the construct the whole expression in memory first.
-- `writer.open(sexpr, false)` is similar to `writer.open(sexpr)` but further arguments will not be indented.
+- ``writer.open(sexpr, false)`` is similar to ``writer.open(sexpr)`` but further arguments will not be indented.
   This is used to avoid unlimited indentation on structures with unlimited nesting.
-- `writer.close(n = 1)` closes the last `n` open s-expressions.
-- `writer.push()` and `writer.pop()` are used to automatically close s-expressions.
-  `writer.pop()` closes all s-expressions opened since the last call to `writer.push()`.
-- `writer.comment(string)` writes a comment on a separate-line.
-  `writer.comment(string, true)` appends a comment to the last printed s-expression.
\ No newline at end of file
+- ``writer.close(n = 1)`` closes the last ``n`` open s-expressions.
+- ``writer.push()`` and ``writer.pop()`` are used to automatically close s-expressions.
+  ``writer.pop()`` closes all s-expressions opened since the last call to ``writer.push()``.
+- ``writer.comment(string)`` writes a comment on a separate-line.
+  ``writer.comment(string, true)`` appends a comment to the last printed s-expression.
\ No newline at end of file

From 7de8be14516bc059d2029859b7a5469a322548e7 Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Tue, 3 Sep 2024 14:30:56 +0100
Subject: [PATCH 489/499] functional_ir.rst: fix typo, document
 SExprWriter::flush

---
 .../yosys_internals/extending_yosys/functional_ir.rst       | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/docs/source/yosys_internals/extending_yosys/functional_ir.rst b/docs/source/yosys_internals/extending_yosys/functional_ir.rst
index 29aaf398c28..a763e050889 100644
--- a/docs/source/yosys_internals/extending_yosys/functional_ir.rst
+++ b/docs/source/yosys_internals/extending_yosys/functional_ir.rst
@@ -82,11 +82,13 @@ For prettyprinting, ``SExprWriter`` wraps an ``std::ostream`` and provides the f
 - ``writer << sexpr`` writes the provided expression to the output, breaking long lines and adding appropriate indentation.
 - ``writer.open(sexpr)`` is similar to ``writer << sexpr`` but will omit the last closing parenthesis.
   Further arguments can then be added separately with ``<<`` or ``open``.
-  This allows for printing large s-expressions without needing the construct the whole expression in memory first.
+  This allows for printing large s-expressions without needing to construct the whole expression in memory first.
 - ``writer.open(sexpr, false)`` is similar to ``writer.open(sexpr)`` but further arguments will not be indented.
   This is used to avoid unlimited indentation on structures with unlimited nesting.
 - ``writer.close(n = 1)`` closes the last ``n`` open s-expressions.
 - ``writer.push()`` and ``writer.pop()`` are used to automatically close s-expressions.
   ``writer.pop()`` closes all s-expressions opened since the last call to ``writer.push()``.
 - ``writer.comment(string)`` writes a comment on a separate-line.
-  ``writer.comment(string, true)`` appends a comment to the last printed s-expression.
\ No newline at end of file
+  ``writer.comment(string, true)`` appends a comment to the last printed s-expression.
+- ``writer.flush()`` flushes any buffering and should be called before any direct access to the underlying ``std::ostream``. It does not close unclosed parentheses.
+- The destructor calls ``flush`` but also closes all unclosed parentheses.

From 0ce7631956bf293524bbfc6f3356f5a8f722a219 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Tue, 3 Sep 2024 19:28:24 +0200
Subject: [PATCH 490/499] internal_stats: init, report current memory
 consumption on linux and mac

---
 passes/cmds/Makefile.inc      |   1 +
 passes/cmds/internal_stats.cc | 120 ++++++++++++++++++++++++++++++++++
 2 files changed, 121 insertions(+)
 create mode 100644 passes/cmds/internal_stats.cc

diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index 33e3ae1bc5a..f208e3e06ef 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -16,6 +16,7 @@ OBJS += passes/cmds/setundef.o
 OBJS += passes/cmds/splitnets.o
 OBJS += passes/cmds/splitcells.o
 OBJS += passes/cmds/stat.o
+OBJS += passes/cmds/internal_stats.o
 OBJS += passes/cmds/setattr.o
 OBJS += passes/cmds/copy.o
 OBJS += passes/cmds/splice.o
diff --git a/passes/cmds/internal_stats.cc b/passes/cmds/internal_stats.cc
new file mode 100644
index 00000000000..fe27bee5eb8
--- /dev/null
+++ b/passes/cmds/internal_stats.cc
@@ -0,0 +1,120 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <iterator>
+#include <optional>
+#include <stdint.h>
+
+#include "kernel/yosys.h"
+#include "kernel/celltypes.h"
+#include "passes/techmap/libparse.h"
+#include "kernel/cost.h"
+#include "libs/json11/json11.hpp"
+
+#if defined(__APPLE__) && defined(__MACH__)
+#include <mach/task.h>
+#include <mach/mach_init.h>
+#endif
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+std::optional<uint64_t> current_mem_bytes() {
+
+#if defined(__APPLE__)
+    task_basic_info_64_data_t basicInfo;
+    mach_msg_type_number_t count = TASK_BASIC_INFO_64_COUNT;
+    kern_return_t error = task_info(mach_task_self(), TASK_BASIC_INFO_64, (task_info_t)&basicInfo, &count);
+    if (error != KERN_SUCCESS) {
+        return {}; // Error getting task information
+    }
+    return basicInfo.resident_size; // Return RSS in KB
+
+#elif defined(__linux__)
+	// Not all linux distributions have to have this file
+    std::ifstream statusFile("/proc/self/status");
+    std::string line;
+    while (std::getline(statusFile, line)) {
+        if (line.find("VmRSS:") == 0) {
+            std::istringstream iss(line);
+            std::string token;
+			// Skip prefix
+            iss >> token;
+            uint64_t rss;
+            iss >> rss;
+            return rss * 1024;
+        }
+    }
+	// Error reading /proc/self/status
+    return {};
+
+#else
+	return {};
+#endif
+}
+
+struct InternalStatsPass : public Pass {
+	InternalStatsPass() : Pass("internal_stats", "print some internal statistics") { }
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n"); // TODO
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		bool json_mode = false;
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-json") {
+				json_mode = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		if(!json_mode)
+			log_header(design, "Printing internal statistics.\n");
+
+		log_experimental("internal_stats");
+
+		if (json_mode) {
+			log("{\n");
+			log("   \"creator\": %s,\n", json11::Json(yosys_version_str).dump().c_str());
+			std::stringstream invocation;
+			std::copy(args.begin(), args.end(), std::ostream_iterator<std::string>(invocation, " "));
+			log("   \"invocation\": %s,\n", json11::Json(invocation.str()).dump().c_str());
+			if (auto mem = current_mem_bytes()) {
+				log("   \"memory_now\": %s,\n", std::to_string(*mem).c_str());
+			}
+		}
+
+		// stats go here
+
+		if (json_mode) {
+			log("\n");
+			log("}\n");
+		}
+
+	}
+} InternalStatsPass;
+
+PRIVATE_NAMESPACE_END

From d56716417336a085afec954f8ecc24722721b98b Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Wed, 4 Sep 2024 00:19:13 +0000
Subject: [PATCH 491/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 61dc51bd529..7c52d984eb0 100644
--- a/Makefile
+++ b/Makefile
@@ -153,7 +153,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.45+0
+YOSYS_VER := 0.45+3
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 5a476a8d29c541d421d409a48a81f642de30b80e Mon Sep 17 00:00:00 2001
From: Emily Schmidt <emily@yosyshq.com>
Date: Wed, 4 Sep 2024 10:30:08 +0100
Subject: [PATCH 492/499] functional tests: run from make tests but not
 smtlib/rkt tests

---
 Makefile                            | 1 +
 tests/functional/conftest.py        | 6 +++++-
 tests/functional/run-test.sh        | 2 +-
 tests/functional/test_functional.py | 2 ++
 4 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index fbe09904263..2a4f4f58758 100644
--- a/Makefile
+++ b/Makefile
@@ -891,6 +891,7 @@ endif
 	+cd tests/xprop && bash run-test.sh $(SEEDOPT)
 	+cd tests/fmt && bash run-test.sh
 	+cd tests/cxxrtl && bash run-test.sh
+	+cd tests/functional && bash run-test.sh
 	@echo ""
 	@echo "  Passed \"make test\"."
 	@echo ""
diff --git a/tests/functional/conftest.py b/tests/functional/conftest.py
index 12db7f1d09b..a9fbb3c5947 100644
--- a/tests/functional/conftest.py
+++ b/tests/functional/conftest.py
@@ -4,6 +4,10 @@
 
 random_seed = random.getrandbits(32)
 
+def pytest_configure(config):
+    config.addinivalue_line("markers", "smt: test uses smtlib/z3")
+    config.addinivalue_line("markers", "rkt: test uses racket/rosette")
+
 def pytest_addoption(parser):
     parser.addoption("--per-cell", type=int, default=None, help="run only N tests per cell")
     parser.addoption("--steps", type=int, default=1000, help="run each test for N steps")
@@ -27,4 +31,4 @@ def pytest_generate_tests(metafunc):
         seed1 = metafunc.config.getoption("seed")
         rnd = lambda seed2: random.Random('{}-{}'.format(seed1, seed2))
         names, cases = generate_test_cases(per_cell, rnd)
-        metafunc.parametrize("cell,parameters", cases, ids=names)
\ No newline at end of file
+        metafunc.parametrize("cell,parameters", cases, ids=names)
diff --git a/tests/functional/run-test.sh b/tests/functional/run-test.sh
index b9a0595f663..9f70462eed9 100755
--- a/tests/functional/run-test.sh
+++ b/tests/functional/run-test.sh
@@ -1,2 +1,2 @@
 #!/usr/bin/env bash
-pytest -v "$@"
+pytest -v -m "not smt and not rkt" "$@"
diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py
index 3b006676a14..7a09966d897 100644
--- a/tests/functional/test_functional.py
+++ b/tests/functional/test_functional.py
@@ -55,6 +55,7 @@ def test_cxx(cell, parameters, tmp_path, num_steps, rnd):
     run([str(vcdharness_exe_file.resolve()), str(vcd_functional_file), str(num_steps), str(seed)])
     yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
 
+@pytest.mark.smt
 def test_smt(cell, parameters, tmp_path, num_steps, rnd):
     import smt_vcd
 
@@ -72,6 +73,7 @@ def test_smt(cell, parameters, tmp_path, num_steps, rnd):
     smt_vcd.simulate_smt(smt_file, vcd_functional_file, num_steps, rnd(cell.name + "-smt"))
     yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
 
+@pytest.mark.rkt
 def test_rkt(cell, parameters, tmp_path, num_steps, rnd):
     import rkt_vcd
 

From 21494d1f06457c2ec99669c06bf42c8bf9ee92d5 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 5 Sep 2024 11:43:31 +1200
Subject: [PATCH 493/499] Makefile: Update coverage_functional

Note sure if this is the best way to do it, but it works?
---
 Makefile | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/Makefile b/Makefile
index 2a4f4f58758..f377072fb25 100644
--- a/Makefile
+++ b/Makefile
@@ -1052,11 +1052,12 @@ coverage:
 clean_coverage:
 	find . -name "*.gcda" -type f -delete
 
+FUNC_KERNEL := functional.cc functional.h sexpr.cc sexpr.h compute_graph.h
+FUNC_INCLUDES := $(addprefix --include *,functional/* $(FUNC_KERNEL))
 coverage_functional:
-	rm -rf coverage.info coverage2.info coverage_html
-	lcov --capture -d backends/functional --no-external -o coverage.info
-	lcov --capture -d kernel --include kernel/functional.cc --include kernel/functional.h --include kernel/sexpr.cc --include kernel/sexpr.h --include kernel/compute_graph.h --no-external -o coverage2.info
-	genhtml coverage.info coverage2.info --output-directory coverage_html
+	rm -rf coverage.info coverage_html
+	lcov --capture -d backends/functional -d kernel $(FUNC_INCLUDES) --no-external -o coverage.info
+	genhtml coverage.info --output-directory coverage_html
 
 qtcreator:
 	echo "$(CXXFLAGS)" | grep -o '\-D[^ ]*' | tr ' ' '\n' | sed 's/-D/#define /' | sed 's/=/ /'> qtcreator.config

From 17ee367c7bc3421a180a2043b014f36ec24ba08c Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 5 Sep 2024 15:46:49 +1200
Subject: [PATCH 494/499] Docs: Use Read the Docs SPHINXOPTS

`-W --keep-going` will build everything but raise an error on any warnings.  Should mean that github actions will correctly flag a failure when attempting to build docs.  Including this current commit until the `internal_stats` command gets a help message.
---
 docs/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/Makefile b/docs/Makefile
index 8be970391a3..21fcd9623e0 100644
--- a/docs/Makefile
+++ b/docs/Makefile
@@ -2,7 +2,7 @@
 #
 
 # You can set these variables from the command line.
-SPHINXOPTS    =
+SPHINXOPTS    = -W --keep-going
 SPHINXBUILD   = sphinx-build
 PAPER         =
 BUILDDIR      = build

From bd6f7bb4a77096b5fbdedeb4376c0aee7c49aac2 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Thu, 5 Sep 2024 11:17:12 +0200
Subject: [PATCH 495/499] ff: improve comments

---
 kernel/ff.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/kernel/ff.h b/kernel/ff.h
index e684d3c4314..d6cf99b9bf8 100644
--- a/kernel/ff.h
+++ b/kernel/ff.h
@@ -131,9 +131,11 @@ struct FfData {
 	bool is_fine;
 	// True if this FF is an $anyinit cell.  Depends on has_gclk.
 	bool is_anyinit;
-	// Polarities, corresponding to sig_*.  True means active-high, false
-	// means active-low.
+	// Polarities, corresponding to sig_*.
+	// True means rising edge, false means falling edge.
 	bool pol_clk;
+	// True means active-high, false
+	// means active-low.
 	bool pol_ce;
 	bool pol_aload;
 	bool pol_arst;

From 14b91554920b8a99408631af37ef6338beae937c Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Thu, 5 Sep 2024 11:22:21 +0200
Subject: [PATCH 496/499] internal_stats: fix doc build by adding a help string

---
 passes/cmds/internal_stats.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/passes/cmds/internal_stats.cc b/passes/cmds/internal_stats.cc
index fe27bee5eb8..8cd62efb6ce 100644
--- a/passes/cmds/internal_stats.cc
+++ b/passes/cmds/internal_stats.cc
@@ -70,11 +70,11 @@ std::optional<uint64_t> current_mem_bytes() {
 }
 
 struct InternalStatsPass : public Pass {
-	InternalStatsPass() : Pass("internal_stats", "print some internal statistics") { }
+	InternalStatsPass() : Pass("internal_stats", "print internal statistics") { }
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-		log("\n"); // TODO
+		log("Print internal statistics for developers (experimental)\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{

From e8951aba29faf774e475f20c1405162993235d7f Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Fri, 6 Sep 2024 00:19:21 +0000
Subject: [PATCH 497/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 7c52d984eb0..e835d48142d 100644
--- a/Makefile
+++ b/Makefile
@@ -153,7 +153,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.45+3
+YOSYS_VER := 0.45+11
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From fc10a6eee2d12c18212fbe7ccabd6094408afd30 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 6 Sep 2024 08:47:43 +0200
Subject: [PATCH 498/499] Run functional tests on private runner only

---
 .github/workflows/test-verific.yml | 1 +
 Makefile                           | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml
index 627a70d4794..024f8cddcb1 100644
--- a/.github/workflows/test-verific.yml
+++ b/.github/workflows/test-verific.yml
@@ -41,6 +41,7 @@ jobs:
           echo "ENABLE_VERIFIC_LIBERTY := 1" >> Makefile.conf
           echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1" >> Makefile.conf
           echo "ENABLE_CCACHE := 1" >> Makefile.conf
+          echo "ENABLE_FUNCTIONAL_TESTS := 1" >> Makefile.conf
           make -j${{ env.procs }} ENABLE_LTO=1
 
       - name: Install Yosys
diff --git a/Makefile b/Makefile
index f377072fb25..c3d572a3686 100644
--- a/Makefile
+++ b/Makefile
@@ -38,6 +38,7 @@ ENABLE_LTO := 0
 ENABLE_CCACHE := 0
 # sccache is not always a drop-in replacement for ccache in practice
 ENABLE_SCCACHE := 0
+ENABLE_FUNCTIONAL_TESTS := 0
 LINK_CURSES := 0
 LINK_TERMCAP := 0
 LINK_ABC := 0
@@ -891,7 +892,9 @@ endif
 	+cd tests/xprop && bash run-test.sh $(SEEDOPT)
 	+cd tests/fmt && bash run-test.sh
 	+cd tests/cxxrtl && bash run-test.sh
+ifeq ($(ENABLE_FUNCTIONAL_TESTS),1)
 	+cd tests/functional && bash run-test.sh
+endif
 	@echo ""
 	@echo "  Passed \"make test\"."
 	@echo ""

From dcf9f583151cbeeabbc99e5f2c537090e3c1ee74 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Sat, 7 Sep 2024 00:18:42 +0000
Subject: [PATCH 499/499] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index f702b940e3d..b841c2fa69a 100644
--- a/Makefile
+++ b/Makefile
@@ -154,7 +154,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.45+11
+YOSYS_VER := 0.45+106
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo