From 5c628387fd74d7b5259b30465b72e876c374bc58 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Miguel=20S=C3=A1nchez=20Garc=C3=ADa?= Date: Fri, 11 Oct 2024 21:16:57 +0200 Subject: [PATCH] Prepend Verilog globals to module AST Fixes #4653. Further AST and RTLIL stages seem to be order-sensitive, and appending globals to the module children list did not work. --- frontends/ast/ast.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 127806fce69..78c85876d7f 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1394,7 +1394,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump if (child->type == AST_MODULE || child->type == AST_INTERFACE) { for (auto n : design->verilog_globals) - child->children.push_back(n->clone()); + child->children.insert(child->children.begin(), n->clone()); // append nodes from previous packages using package-qualified names for (auto &n : design->verilog_packages) {