From 1af9fa643c39c5c1a2dfd00cb48f735bed177992 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Wed, 14 Aug 2024 17:42:11 +0200 Subject: [PATCH] Add left and right bound properties to wire. Add some tests --- frontends/verific/verific.cc | 24 ++++++++++++++++++- tests/verific/large_integer_range.vhdl | 20 ++++++++++++++++ tests/verific/large_integer_range.ys | 2 ++ tests/verific/negative_integer_range.vhdl | 18 ++++++++++++++ tests/verific/negative_integer_range.ys | 2 ++ tests/verific/positive_integer_range.vhdl | 18 ++++++++++++++ tests/verific/positive_integer_range.ys | 2 ++ .../zero_to_positive_integer_range.vhdl | 18 ++++++++++++++ .../verific/zero_to_positive_integer_range.ys | 2 ++ 9 files changed, 105 insertions(+), 1 deletion(-) create mode 100644 tests/verific/large_integer_range.vhdl create mode 100644 tests/verific/large_integer_range.ys create mode 100644 tests/verific/negative_integer_range.vhdl create mode 100644 tests/verific/negative_integer_range.ys create mode 100644 tests/verific/positive_integer_range.vhdl create mode 100644 tests/verific/positive_integer_range.ys create mode 100644 tests/verific/zero_to_positive_integer_range.vhdl create mode 100644 tests/verific/zero_to_positive_integer_range.ys diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 2dd8aa09551..fa127ed54f0 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -450,8 +450,30 @@ void VerificImporter::import_attributes(dict &att auto type_range = nl->GetTypeRange(obj->Name()); if (!type_range) return; + if (type_range->IsTypeScalar()) { + const long long left_bound = type_range->GetScalarRangeLeftBound(); + const long long right_bound = type_range->GetScalarRangeRightBound(); + const unsigned bit_width = type_range->NumElements(); + + const std::bitset binary_left(left_bound); + log_assert(bit_width <= binary_left.size()); + std::vector bits_left(bit_width); + for (size_t i = 0; i < bit_width; ++i) { + bits_left[i] = binary_left[i]; + } + + const std::bitset binary_right(right_bound); + log_assert(bit_width <= binary_right.size()); + std::vector bits_right(bit_width); + for (size_t i = 0; i < bit_width; ++i) { + bits_right[i] = binary_right[i]; + } + + attributes.emplace(ID(left_bound), RTLIL::Const(bits_left)); + attributes.emplace(ID(right_bound), RTLIL::Const(bits_right)); + } if (!type_range->IsTypeEnum()) - return; + return; #ifdef VERIFIC_VHDL_SUPPORT if (nl->IsFromVhdl() && strcmp(type_range->GetTypeName(), "STD_LOGIC") == 0) return; diff --git a/tests/verific/large_integer_range.vhdl b/tests/verific/large_integer_range.vhdl new file mode 100644 index 00000000000..efd8b405a3d --- /dev/null +++ b/tests/verific/large_integer_range.vhdl @@ -0,0 +1,20 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity work is + Port ( + -- 32 bit range is -2,147,483,648 to 2,147,483,647 + -- 64 bit range is -9,223,372,036,854,775,808 to 9,223,372,036,854,775,807 + a : in INTEGER range -4 to 10147483749; + b : out INTEGER range -4 to 10147483748 + ); +end entity work; + +architecture Behavioral of work is +begin + process(a) + begin + b <= a; + end process; +end architecture Behavioral; diff --git a/tests/verific/large_integer_range.ys b/tests/verific/large_integer_range.ys new file mode 100644 index 00000000000..cb4759b4744 --- /dev/null +++ b/tests/verific/large_integer_range.ys @@ -0,0 +1,2 @@ +verific -vhdl2019 large_integer_range.vhdl +verific -import work \ No newline at end of file diff --git a/tests/verific/negative_integer_range.vhdl b/tests/verific/negative_integer_range.vhdl new file mode 100644 index 00000000000..cb0f934f78e --- /dev/null +++ b/tests/verific/negative_integer_range.vhdl @@ -0,0 +1,18 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity work is + Port ( + a : in INTEGER range -10 to 15; + b : out INTEGER range -9 to 15 + ); +end entity work; + +architecture Behavioral of work is +begin + process(a) + begin + b <= a; + end process; +end architecture Behavioral; diff --git a/tests/verific/negative_integer_range.ys b/tests/verific/negative_integer_range.ys new file mode 100644 index 00000000000..72cd431463f --- /dev/null +++ b/tests/verific/negative_integer_range.ys @@ -0,0 +1,2 @@ +verific -vhdl2019 negative_integer_range.vhdl +verific -import work \ No newline at end of file diff --git a/tests/verific/positive_integer_range.vhdl b/tests/verific/positive_integer_range.vhdl new file mode 100644 index 00000000000..0e0bba90a31 --- /dev/null +++ b/tests/verific/positive_integer_range.vhdl @@ -0,0 +1,18 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity work is + Port ( + a : in INTEGER range 1 to 15; + b : out INTEGER range 2 to 15 + ); +end entity work; + +architecture Behavioral of work is +begin + process(a) + begin + b <= a; + end process; +end architecture Behavioral; diff --git a/tests/verific/positive_integer_range.ys b/tests/verific/positive_integer_range.ys new file mode 100644 index 00000000000..df3a5bdbeaf --- /dev/null +++ b/tests/verific/positive_integer_range.ys @@ -0,0 +1,2 @@ +verific -vhdl2019 positive_integer_range.vhdl +verific -import work \ No newline at end of file diff --git a/tests/verific/zero_to_positive_integer_range.vhdl b/tests/verific/zero_to_positive_integer_range.vhdl new file mode 100644 index 00000000000..f90b2aeb295 --- /dev/null +++ b/tests/verific/zero_to_positive_integer_range.vhdl @@ -0,0 +1,18 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity work is + Port ( + a : in INTEGER range 0 to 15; + b : out INTEGER range 1 to 15 + ); +end entity work; + +architecture Behavioral of work is +begin + process(a) + begin + b <= a; + end process; +end architecture Behavioral; diff --git a/tests/verific/zero_to_positive_integer_range.ys b/tests/verific/zero_to_positive_integer_range.ys new file mode 100644 index 00000000000..bf60fdf750a --- /dev/null +++ b/tests/verific/zero_to_positive_integer_range.ys @@ -0,0 +1,2 @@ +verific -vhdl2019 zero_to_positive_integer_range.vhdl +verific -import work \ No newline at end of file