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cpuid_x86.c
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//{
/*********************************************************************/
/* Copyright 2009, 2010 The University of Texas at Austin. */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or */
/* without modification, are permitted provided that the following */
/* conditions are met: */
/* */
/* 1. Redistributions of source code must retain the above */
/* copyright notice, this list of conditions and the following */
/* disclaimer. */
/* */
/* 2. Redistributions in binary form must reproduce the above */
/* copyright notice, this list of conditions and the following */
/* disclaimer in the documentation and/or other materials */
/* provided with the distribution. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
/* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
/* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
/* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
/* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
/* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
/* POSSIBILITY OF SUCH DAMAGE. */
/* */
/* The views and conclusions contained in the software and */
/* documentation are those of the authors and should not be */
/* interpreted as representing official policies, either expressed */
/* or implied, of The University of Texas at Austin. */
/*********************************************************************/
#include <stdio.h>
#include <string.h>
#include "cpuid.h"
#if defined(_MSC_VER) && !defined(__clang__)
#define C_INLINE __inline
#else
#define C_INLINE inline
#endif
/*
#ifdef NO_AVX
#define CPUTYPE_HASWELL CPUTYPE_NEHALEM
#define CORE_HASWELL CORE_NEHALEM
#define CPUTYPE_SKYLAKEX CPUTYPE_NEHALEM
#define CORE_SKYLAKEX CORE_NEHALEM
#define CPUTYPE_SANDYBRIDGE CPUTYPE_NEHALEM
#define CORE_SANDYBRIDGE CORE_NEHALEM
#define CPUTYPE_BULLDOZER CPUTYPE_BARCELONA
#define CORE_BULLDOZER CORE_BARCELONA
#define CPUTYPE_PILEDRIVER CPUTYPE_BARCELONA
#define CORE_PILEDRIVER CORE_BARCELONA
#endif
*/
#if defined(_MSC_VER) && !defined(__clang__)
void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx)
{
int cpuInfo[4] = {-1};
__cpuid(cpuInfo, op);
*eax = cpuInfo[0];
*ebx = cpuInfo[1];
*ecx = cpuInfo[2];
*edx = cpuInfo[3];
}
void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx, int *edx)
{
int cpuInfo[4] = {-1};
__cpuidex(cpuInfo, op, count);
*eax = cpuInfo[0];
*ebx = cpuInfo[1];
*ecx = cpuInfo[2];
*edx = cpuInfo[3];
}
#else
#ifndef CPUIDEMU
#if defined(__APPLE__) && defined(__i386__)
void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx);
void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx, int *edx);
#else
static C_INLINE void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx){
#if defined(__i386__) && defined(__PIC__)
__asm__ __volatile__
("mov %%ebx, %%edi;"
"cpuid;"
"xchgl %%ebx, %%edi;"
: "=a" (*eax), "=D" (*ebx), "=c" (*ecx), "=d" (*edx) : "a" (op), "c" (0) : "cc");
#else
__asm__ __volatile__
("cpuid": "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) : "a" (op) , "c" (0) : "cc");
#endif
}
static C_INLINE void cpuid_count(int op, int count ,int *eax, int *ebx, int *ecx, int *edx){
#if defined(__i386__) && defined(__PIC__)
__asm__ __volatile__
("mov %%ebx, %%edi;"
"cpuid;"
"xchgl %%ebx, %%edi;"
: "=a" (*eax), "=D" (*ebx), "=c" (*ecx), "=d" (*edx) : "0" (op), "2" (count) : "cc");
#else
__asm__ __volatile__
("cpuid": "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) : "0" (op), "2" (count) : "cc");
#endif
}
#endif
#else
typedef struct {
unsigned int id, a, b, c, d;
} idlist_t;
typedef struct {
char *vendor;
char *name;
int start, stop;
} vendor_t;
extern idlist_t idlist[];
extern vendor_t vendor[];
static int cv = VENDOR;
void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx){
static int current = 0;
int start = vendor[cv].start;
int stop = vendor[cv].stop;
int count = stop - start;
if ((current < start) || (current > stop)) current = start;
while ((count > 0) && (idlist[current].id != op)) {
current ++;
if (current > stop) current = start;
count --;
}
*eax = idlist[current].a;
*ebx = idlist[current].b;
*ecx = idlist[current].c;
*edx = idlist[current].d;
}
void cpuid_count (unsigned int op, unsigned int count, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) {
return cpuid (op, eax, ebx, ecx, edx);
}
#endif
#endif // _MSC_VER
static C_INLINE int have_cpuid(void){
int eax, ebx, ecx, edx;
cpuid(0, &eax, &ebx, &ecx, &edx);
return eax;
}
static C_INLINE int have_excpuid(void){
int eax, ebx, ecx, edx;
cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
return eax & 0xffff;
}
#ifndef NO_AVX
static C_INLINE void xgetbv(int op, int * eax, int * edx){
//Use binary code for xgetbv
#if defined(_MSC_VER) && !defined(__clang__)
*eax = __xgetbv(op);
#else
__asm__ __volatile__
(".byte 0x0f, 0x01, 0xd0": "=a" (*eax), "=d" (*edx) : "c" (op) : "cc");
#endif
}
#endif
int support_avx(void){
#ifndef NO_AVX
int eax, ebx, ecx, edx;
int ret=0;
cpuid(1, &eax, &ebx, &ecx, &edx);
if ((ecx & (1 << 28)) != 0 && (ecx & (1 << 27)) != 0 && (ecx & (1 << 26)) != 0){
xgetbv(0, &eax, &edx);
if((eax & 6) == 6){
ret=1; //OS supports saving xmm and ymm registers (6 = (1<<1) | (1<<2))
}
}
return ret;
#else
return 0;
#endif
}
int support_avx2(void){
#ifndef NO_AVX2
int eax, ebx, ecx=0, edx;
int ret=0;
if (!support_avx())
return 0;
cpuid(7, &eax, &ebx, &ecx, &edx);
if((ebx & (1<<5)) != 0)
ret=1; //CPU supports AVX2
return ret;
#else
return 0;
#endif
}
int support_avx512(void){
#if !defined(NO_AVX) && !defined(NO_AVX512)
int eax, ebx, ecx, edx;
int ret=0;
if (!support_avx())
return 0;
cpuid(7, &eax, &ebx, &ecx, &edx);
if((ebx & (1<<5)) == 0){
ret=0; //cpu does not have avx2 flag
}
if((ebx & (1<<31)) != 0){ //AVX512VL flag
xgetbv(0, &eax, &edx);
if((eax & 0xe0) == 0xe0)
ret=1; //OS supports saving zmm registers
}
return ret;
#else
return 0;
#endif
}
int support_avx512_bf16(void){
#if !defined(NO_AVX) && !defined(NO_AVX512)
int eax, ebx, ecx, edx;
int ret=0;
if (!support_avx512())
return 0;
cpuid_count(7, 1, &eax, &ebx, &ecx, &edx);
if((eax & 32) == 32){
ret=1; // CPUID.7.1:EAX[bit 5] indicates whether avx512_bf16 supported or not
}
return ret;
#else
return 0;
#endif
}
#define BIT_AMX_TILE 0x01000000
#define BIT_AMX_BF16 0x00400000
#define BIT_AMX_ENBD 0x00060000
int support_amx_bf16(void) {
#if !defined(NO_AVX) && !defined(NO_AVX512)
int eax, ebx, ecx, edx;
int ret=0;
if (!support_avx512())
return 0;
// CPUID.7.0:EDX indicates AMX support
cpuid_count(7, 0, &eax, &ebx, &ecx, &edx);
if ((edx & BIT_AMX_TILE) && (edx & BIT_AMX_BF16)) {
// CPUID.D.0:EAX[17:18] indicates AMX enabled
cpuid_count(0xd, 0, &eax, &ebx, &ecx, &edx);
if ((eax & BIT_AMX_ENBD) == BIT_AMX_ENBD)
ret = 1;
}
return ret;
#else
return 0;
#endif
}
int get_vendor(void){
int eax, ebx, ecx, edx;
char vendor[13];
cpuid(0, &eax, &ebx, &ecx, &edx);
*(int *)(&vendor[0]) = ebx;
*(int *)(&vendor[4]) = edx;
*(int *)(&vendor[8]) = ecx;
vendor[12] = (char)0;
if (!strcmp(vendor, "GenuineIntel")) return VENDOR_INTEL;
if (!strcmp(vendor, " UMC UMC UMC")) return VENDOR_UMC;
if (!strcmp(vendor, "AuthenticAMD")) return VENDOR_AMD;
if (!strcmp(vendor, "CyrixInstead")) return VENDOR_CYRIX;
if (!strcmp(vendor, "NexGenDriven")) return VENDOR_NEXGEN;
if (!strcmp(vendor, "CentaurHauls")) return VENDOR_CENTAUR;
if (!strcmp(vendor, " Shanghai ")) return VENDOR_ZHAOXIN;
if (!strcmp(vendor, "RiseRiseRise")) return VENDOR_RISE;
if (!strcmp(vendor, " SiS SiS SiS")) return VENDOR_SIS;
if (!strcmp(vendor, "GenuineTMx86")) return VENDOR_TRANSMETA;
if (!strcmp(vendor, "Geode by NSC")) return VENDOR_NSC;
if (!strcmp(vendor, "HygonGenuine")) return VENDOR_HYGON;
if ((eax == 0) || ((eax & 0x500) != 0)) return VENDOR_INTEL;
return VENDOR_UNKNOWN;
}
int get_cputype(int gettype){
int eax, ebx, ecx, edx;
/*
int extend_family, family;
int extend_model, model;
int type, stepping;
*/
int feature = 0;
cpuid(1, &eax, &ebx, &ecx, &edx);
switch (gettype) {
case GET_EXFAMILY :
return BITMASK(eax, 20, 0xff);
case GET_EXMODEL :
return BITMASK(eax, 16, 0x0f);
case GET_TYPE :
return BITMASK(eax, 12, 0x03);
case GET_FAMILY :
return BITMASK(eax, 8, 0x0f);
case GET_MODEL :
return BITMASK(eax, 4, 0x0f);
case GET_APICID :
return BITMASK(ebx, 24, 0x0f);
case GET_LCOUNT :
return BITMASK(ebx, 16, 0x0f);
case GET_CHUNKS :
return BITMASK(ebx, 8, 0x0f);
case GET_STEPPING :
return BITMASK(eax, 0, 0x0f);
case GET_BLANDID :
return BITMASK(ebx, 0, 0xff);
case GET_NUMSHARE :
if (have_cpuid() < 4) return 0;
cpuid(4, &eax, &ebx, &ecx, &edx);
return BITMASK(eax, 14, 0xfff);
case GET_NUMCORES :
if (have_cpuid() < 4) return 0;
cpuid(4, &eax, &ebx, &ecx, &edx);
return BITMASK(eax, 26, 0x3f);
case GET_FEATURE :
if ((edx & (1 << 3)) != 0) feature |= HAVE_PSE;
if ((edx & (1 << 15)) != 0) feature |= HAVE_CMOV;
if ((edx & (1 << 19)) != 0) feature |= HAVE_CFLUSH;
if ((edx & (1 << 23)) != 0) feature |= HAVE_MMX;
if ((edx & (1 << 25)) != 0) feature |= HAVE_SSE;
if ((edx & (1 << 26)) != 0) feature |= HAVE_SSE2;
if ((edx & (1 << 27)) != 0) {
if (BITMASK(ebx, 16, 0x0f) > 0) feature |= HAVE_HIT;
}
if ((ecx & (1 << 0)) != 0) feature |= HAVE_SSE3;
if ((ecx & (1 << 9)) != 0) feature |= HAVE_SSSE3;
if ((ecx & (1 << 19)) != 0) feature |= HAVE_SSE4_1;
if ((ecx & (1 << 20)) != 0) feature |= HAVE_SSE4_2;
#ifndef NO_AVX
if (support_avx()) feature |= HAVE_AVX;
if (support_avx2()) feature |= HAVE_AVX2;
if (support_avx512()) feature |= HAVE_AVX512VL;
if (support_avx512_bf16()) feature |= HAVE_AVX512BF16;
if (support_amx_bf16()) feature |= HAVE_AMXBF16;
if ((ecx & (1 << 12)) != 0) feature |= HAVE_FMA3;
#endif
if (have_excpuid() >= 0x01) {
cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
if ((ecx & (1 << 6)) != 0) feature |= HAVE_SSE4A;
if ((ecx & (1 << 7)) != 0) feature |= HAVE_MISALIGNSSE;
#ifndef NO_AVX
if ((ecx & (1 << 16)) != 0) feature |= HAVE_FMA4;
#endif
if ((edx & (1 << 30)) != 0) feature |= HAVE_3DNOWEX;
if ((edx & (1 << 31)) != 0) feature |= HAVE_3DNOW;
}
if (have_excpuid() >= 0x1a) {
cpuid(0x8000001a, &eax, &ebx, &ecx, &edx);
if ((eax & (1 << 0)) != 0) feature |= HAVE_128BITFPU;
if ((eax & (1 << 1)) != 0) feature |= HAVE_FASTMOVU;
}
}
return feature;
}
int get_cacheinfo(int type, cache_info_t *cacheinfo){
int eax, ebx, ecx, edx, cpuid_level;
int info[15];
int i;
cache_info_t LC1, LD1, L2, L3,
ITB, DTB, LITB, LDTB,
L2ITB, L2DTB, L2LITB, L2LDTB;
LC1.size = 0; LC1.associative = 0; LC1.linesize = 0; LC1.shared = 0;
LD1.size = 0; LD1.associative = 0; LD1.linesize = 0; LD1.shared = 0;
L2.size = 0; L2.associative = 0; L2.linesize = 0; L2.shared = 0;
L3.size = 0; L3.associative = 0; L3.linesize = 0; L3.shared = 0;
ITB.size = 0; ITB.associative = 0; ITB.linesize = 0; ITB.shared = 0;
DTB.size = 0; DTB.associative = 0; DTB.linesize = 0; DTB.shared = 0;
LITB.size = 0; LITB.associative = 0; LITB.linesize = 0; LITB.shared = 0;
LDTB.size = 0; LDTB.associative = 0; LDTB.linesize = 0; LDTB.shared = 0;
L2ITB.size = 0; L2ITB.associative = 0; L2ITB.linesize = 0; L2ITB.shared = 0;
L2DTB.size = 0; L2DTB.associative = 0; L2DTB.linesize = 0; L2DTB.shared = 0;
L2LITB.size = 0; L2LITB.associative = 0; L2LITB.linesize = 0; L2LITB.shared = 0;
L2LDTB.size = 0; L2LDTB.associative = 0; L2LDTB.linesize = 0; L2LDTB.shared = 0;
cpuid(0, &cpuid_level, &ebx, &ecx, &edx);
if (cpuid_level > 1) {
int numcalls;
cpuid(2, &eax, &ebx, &ecx, &edx);
numcalls = BITMASK(eax, 0, 0xff); //FIXME some systems may require repeated calls to read all entries
info[ 0] = BITMASK(eax, 8, 0xff);
info[ 1] = BITMASK(eax, 16, 0xff);
info[ 2] = BITMASK(eax, 24, 0xff);
info[ 3] = BITMASK(ebx, 0, 0xff);
info[ 4] = BITMASK(ebx, 8, 0xff);
info[ 5] = BITMASK(ebx, 16, 0xff);
info[ 6] = BITMASK(ebx, 24, 0xff);
info[ 7] = BITMASK(ecx, 0, 0xff);
info[ 8] = BITMASK(ecx, 8, 0xff);
info[ 9] = BITMASK(ecx, 16, 0xff);
info[10] = BITMASK(ecx, 24, 0xff);
info[11] = BITMASK(edx, 0, 0xff);
info[12] = BITMASK(edx, 8, 0xff);
info[13] = BITMASK(edx, 16, 0xff);
info[14] = BITMASK(edx, 24, 0xff);
for (i = 0; i < 15; i++){
switch (info[i]){
/* This table is from http://www.sandpile.org/ia32/cpuid.htm */
case 0x01 :
ITB.size = 4;
ITB.associative = 4;
ITB.linesize = 32;
break;
case 0x02 :
LITB.size = 4096;
LITB.associative = 0;
LITB.linesize = 2;
break;
case 0x03 :
DTB.size = 4;
DTB.associative = 4;
DTB.linesize = 64;
break;
case 0x04 :
LDTB.size = 4096;
LDTB.associative = 4;
LDTB.linesize = 8;
break;
case 0x05 :
LDTB.size = 4096;
LDTB.associative = 4;
LDTB.linesize = 32;
break;
case 0x06 :
LC1.size = 8;
LC1.associative = 4;
LC1.linesize = 32;
break;
case 0x08 :
LC1.size = 16;
LC1.associative = 4;
LC1.linesize = 32;
break;
case 0x09 :
LC1.size = 32;
LC1.associative = 4;
LC1.linesize = 64;
break;
case 0x0a :
LD1.size = 8;
LD1.associative = 2;
LD1.linesize = 32;
break;
case 0x0c :
LD1.size = 16;
LD1.associative = 4;
LD1.linesize = 32;
break;
case 0x0d :
LD1.size = 16;
LD1.associative = 4;
LD1.linesize = 64;
break;
case 0x0e :
LD1.size = 24;
LD1.associative = 6;
LD1.linesize = 64;
break;
case 0x10 :
LD1.size = 16;
LD1.associative = 4;
LD1.linesize = 32;
break;
case 0x15 :
LC1.size = 16;
LC1.associative = 4;
LC1.linesize = 32;
break;
case 0x1a :
L2.size = 96;
L2.associative = 6;
L2.linesize = 64;
break;
case 0x21 :
L2.size = 256;
L2.associative = 8;
L2.linesize = 64;
break;
case 0x22 :
L3.size = 512;
L3.associative = 4;
L3.linesize = 64;
break;
case 0x23 :
L3.size = 1024;
L3.associative = 8;
L3.linesize = 64;
break;
case 0x25 :
L3.size = 2048;
L3.associative = 8;
L3.linesize = 64;
break;
case 0x29 :
L3.size = 4096;
L3.associative = 8;
L3.linesize = 64;
break;
case 0x2c :
LD1.size = 32;
LD1.associative = 8;
LD1.linesize = 64;
break;
case 0x30 :
LC1.size = 32;
LC1.associative = 8;
LC1.linesize = 64;
break;
case 0x39 :
L2.size = 128;
L2.associative = 4;
L2.linesize = 64;
break;
case 0x3a :
L2.size = 192;
L2.associative = 6;
L2.linesize = 64;
break;
case 0x3b :
L2.size = 128;
L2.associative = 2;
L2.linesize = 64;
break;
case 0x3c :
L2.size = 256;
L2.associative = 4;
L2.linesize = 64;
break;
case 0x3d :
L2.size = 384;
L2.associative = 6;
L2.linesize = 64;
break;
case 0x3e :
L2.size = 512;
L2.associative = 4;
L2.linesize = 64;
break;
case 0x41 :
L2.size = 128;
L2.associative = 4;
L2.linesize = 32;
break;
case 0x42 :
L2.size = 256;
L2.associative = 4;
L2.linesize = 32;
break;
case 0x43 :
L2.size = 512;
L2.associative = 4;
L2.linesize = 32;
break;
case 0x44 :
L2.size = 1024;
L2.associative = 4;
L2.linesize = 32;
break;
case 0x45 :
L2.size = 2048;
L2.associative = 4;
L2.linesize = 32;
break;
case 0x46 :
L3.size = 4096;
L3.associative = 4;
L3.linesize = 64;
break;
case 0x47 :
L3.size = 8192;
L3.associative = 8;
L3.linesize = 64;
break;
case 0x48 :
L2.size = 3184;
L2.associative = 12;
L2.linesize = 64;
break;
case 0x49 :
if ((get_cputype(GET_FAMILY) == 0x0f) && (get_cputype(GET_MODEL) == 0x06)) {
L3.size = 4096;
L3.associative = 16;
L3.linesize = 64;
} else {
L2.size = 4096;
L2.associative = 16;
L2.linesize = 64;
}
break;
case 0x4a :
L3.size = 6144;
L3.associative = 12;
L3.linesize = 64;
break;
case 0x4b :
L3.size = 8192;
L3.associative = 16;
L3.linesize = 64;
break;
case 0x4c :
L3.size = 12280;
L3.associative = 12;
L3.linesize = 64;
break;
case 0x4d :
L3.size = 16384;
L3.associative = 16;
L3.linesize = 64;
break;
case 0x4e :
L2.size = 6144;
L2.associative = 24;
L2.linesize = 64;
break;
case 0x4f :
ITB.size = 4;
ITB.associative = 0;
ITB.linesize = 32;
break;
case 0x50 :
ITB.size = 4;
ITB.associative = 0;
ITB.linesize = 64;
LITB.size = 4096;
LITB.associative = 0;
LITB.linesize = 64;
LITB.shared = 1;
break;
case 0x51 :
ITB.size = 4;
ITB.associative = 0;
ITB.linesize = 128;
LITB.size = 4096;
LITB.associative = 0;
LITB.linesize = 128;
LITB.shared = 1;
break;
case 0x52 :
ITB.size = 4;
ITB.associative = 0;
ITB.linesize = 256;
LITB.size = 4096;
LITB.associative = 0;
LITB.linesize = 256;
LITB.shared = 1;
break;
case 0x55 :
LITB.size = 4096;
LITB.associative = 0;
LITB.linesize = 7;
LITB.shared = 1;
break;
case 0x56 :
LDTB.size = 4096;
LDTB.associative = 4;
LDTB.linesize = 16;
break;
case 0x57 :
LDTB.size = 4096;
LDTB.associative = 4;
LDTB.linesize = 16;
break;
case 0x5b :
DTB.size = 4;
DTB.associative = 0;
DTB.linesize = 64;
LDTB.size = 4096;
LDTB.associative = 0;
LDTB.linesize = 64;
LDTB.shared = 1;
break;
case 0x5c :
DTB.size = 4;
DTB.associative = 0;
DTB.linesize = 128;
LDTB.size = 4096;
LDTB.associative = 0;
LDTB.linesize = 128;
LDTB.shared = 1;
break;
case 0x5d :
DTB.size = 4;
DTB.associative = 0;
DTB.linesize = 256;
LDTB.size = 4096;
LDTB.associative = 0;
LDTB.linesize = 256;
LDTB.shared = 1;
break;
case 0x60 :
LD1.size = 16;
LD1.associative = 8;
LD1.linesize = 64;
break;
case 0x63 :
DTB.size = 2048;
DTB.associative = 4;
DTB.linesize = 32;
LDTB.size = 4096;
LDTB.associative= 4;
LDTB.linesize = 32;
break;
case 0x66 :
LD1.size = 8;
LD1.associative = 4;
LD1.linesize = 64;
break;
case 0x67 :
LD1.size = 16;
LD1.associative = 4;
LD1.linesize = 64;
break;
case 0x68 :
LD1.size = 32;
LD1.associative = 4;
LD1.linesize = 64;
break;
case 0x70 :
LC1.size = 12;
LC1.associative = 8;
break;
case 0x71 :
LC1.size = 16;
LC1.associative = 8;
break;
case 0x72 :
LC1.size = 32;
LC1.associative = 8;
break;
case 0x73 :
LC1.size = 64;
LC1.associative = 8;
break;
case 0x76 :
ITB.size = 2048;
ITB.associative = 0;
ITB.linesize = 8;
LITB.size = 4096;
LITB.associative= 0;
LITB.linesize = 8;
break;
case 0x77 :
LC1.size = 16;
LC1.associative = 4;
LC1.linesize = 64;
break;
case 0x78 :
L2.size = 1024;
L2.associative = 4;
L2.linesize = 64;
break;
case 0x79 :
L2.size = 128;
L2.associative = 8;
L2.linesize = 64;
break;
case 0x7a :
L2.size = 256;
L2.associative = 8;
L2.linesize = 64;
break;
case 0x7b :
L2.size = 512;
L2.associative = 8;
L2.linesize = 64;
break;
case 0x7c :
L2.size = 1024;
L2.associative = 8;
L2.linesize = 64;
break;
case 0x7d :
L2.size = 2048;
L2.associative = 8;
L2.linesize = 64;
break;
case 0x7e :
L2.size = 256;
L2.associative = 8;
L2.linesize = 128;
break;
case 0x7f :
L2.size = 512;
L2.associative = 2;
L2.linesize = 64;
break;
case 0x81 :
L2.size = 128;
L2.associative = 8;
L2.linesize = 32;
break;
case 0x82 :
L2.size = 256;
L2.associative = 8;
L2.linesize = 32;
break;
case 0x83 :
L2.size = 512;
L2.associative = 8;
L2.linesize = 32;
break;
case 0x84 :
L2.size = 1024;
L2.associative = 8;
L2.linesize = 32;
break;
case 0x85 :
L2.size = 2048;
L2.associative = 8;
L2.linesize = 32;
break;
case 0x86 :
L2.size = 512;
L2.associative = 4;
L2.linesize = 64;
break;
case 0x87 :
L2.size = 1024;
L2.associative = 8;
L2.linesize = 64;
break;
case 0x88 :
L3.size = 2048;
L3.associative = 4;
L3.linesize = 64;
break;
case 0x89 :
L3.size = 4096;
L3.associative = 4;
L3.linesize = 64;
break;
case 0x8a :
L3.size = 8192;
L3.associative = 4;
L3.linesize = 64;
break;
case 0x8d :
L3.size = 3096;
L3.associative = 12;
L3.linesize = 128;
break;
case 0x90 :
ITB.size = 4;
ITB.associative = 0;
ITB.linesize = 64;
break;
case 0x96 :
DTB.size = 4;
DTB.associative = 0;
DTB.linesize = 32;
break;
case 0x9b :
L2DTB.size = 4;
L2DTB.associative = 0;
L2DTB.linesize = 96;
break;
case 0xb0 :
ITB.size = 4;
ITB.associative = 4;
ITB.linesize = 128;
break;
case 0xb1 :
LITB.size = 4096;
LITB.associative = 4;
LITB.linesize = 4;
break;
case 0xb2 :
ITB.size = 4;
ITB.associative = 4;
ITB.linesize = 64;
break;
case 0xb3 :
DTB.size = 4;
DTB.associative = 4;
DTB.linesize = 128;
break;
case 0xb4 :
DTB.size = 4;
DTB.associative = 4;
DTB.linesize = 256;
break;
case 0xba :
DTB.size = 4;
DTB.associative = 4;
DTB.linesize = 64;
break;
case 0xd0 :
L3.size = 512;
L3.associative = 4;
L3.linesize = 64;
break;
case 0xd1 :
L3.size = 1024;
L3.associative = 4;
L3.linesize = 64;
break;
case 0xd2 :
L3.size = 2048;
L3.associative = 4;
L3.linesize = 64;
break;
case 0xd6 :
L3.size = 1024;
L3.associative = 8;
L3.linesize = 64;
break;
case 0xd7 :
L3.size = 2048;
L3.associative = 8;
L3.linesize = 64;
break;
case 0xd8 :
L3.size = 4096;
L3.associative = 8;
L3.linesize = 64;
break;
case 0xdc :
L3.size = 2048;
L3.associative = 12;
L3.linesize = 64;
break;
case 0xdd :
L3.size = 4096;
L3.associative = 12;
L3.linesize = 64;
break;
case 0xde :
L3.size = 8192;
L3.associative = 12;
L3.linesize = 64;
break;
case 0xe2 :
L3.size = 2048;
L3.associative = 16;
L3.linesize = 64;
break;
case 0xe3 :
L3.size = 4096;