Multicore simulation and execution

[dennisdef]

Good evening,

I am trying to run the simulation file located in src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala using the commands exactly as they are inside the file. The simulation starts normally but after a long time it get stack after displaying [info] Welcome to Buildroot.

If I kill the execution, then a message pops up that says:
[warn] Canceling execution...
[info] buildroot login:

Do you know to fix that? I have tried also to use the same commands with --nax-count 1 and without a nax-count flag and I get exactly the same results.

Also, I can't find a way to create a dual core SoC to use on an FPGA. Is there a way to do it or it isn't supported yet?

Thank you very much!

[Dolu1990]

Hi,

I think the buildroot login: message is holded by SBT because it doens't has a line return.
i don't know how to avoid that. I'm running simulation directly through intellij (instead of sbt), there it will print each char without holding.
Anyway in SBT, i think if after that welcome to buildroot, you type root and then press enter, it will continue the login.

Also, I can't find a way to create a dual core SoC to use on an FPGA. Is there a way to do it or it isn't supported yet?

It is through litex. See for instance :
https://spinalhdl.github.io/NaxRiscv-Rtd/main/NaxRiscv/hardware/index.html#digilent-nexys-video

Also, this may interest you :
https://www.youtube.com/watch?v=dR_jqS13D2c

[dennisdef]

Hi,

The problem with the welcome to buildroot wasn't fixed with the root but I will try to use the intellij to see what results may came up. As for the litex, I was wandering if there was a way to produce a verilog (or some other king of HDL file) so that I can use it with a different program.

[Dolu1990]

For litex itself, i don't know if you can just ask it a verilog out, as it is used more like a all in one solution instead.

[dennisdef]

Can I do it though your repo in some way? Compile a file for example with Intellij and have a verilog file at the end

[Dolu1990]

Yes you can.
See the various sbt "runMain commands in the doc.

[dennisdef]

Good morning,
I have tried to use intellij and I managed to boot into linux successfully. However, the problem I am encountering is that the system boots up with only one core even though sbi has created 2. I have tried to mess with the device tree to force it see 2, but I only got one working and one disabled core. Do you know how to fix that?

The following pictures are produced when I use the provided examples:

And these is when the device tree is modified to force 2 cores:

[Dolu1990]

Hi,

what simulation arguments did you used ?

[dennisdef]

Hello,
I used the arguments exactly as written in the SocSim.scala file. To "force" it to use 2 cores, I decompiled the same file, add the configuration for a second core and then recompiled it.

[Dolu1990]

I decompiled the same file

decompiled which file ?

[dennisdef]

The linux.dtb. I produced the .dts file, added the configuration and then compiled it back to .dtb