diff --git a/include/tcg/exec.h b/include/tcg/exec.h index c23ce89..028060a 100644 --- a/include/tcg/exec.h +++ b/include/tcg/exec.h @@ -30,7 +30,7 @@ * Note: the address of search data can be obtained by adding @size to @ptr. */ struct tb_tc { - void *ptr; /* pointer to the translated code */ + void *ptr; /* pointer to the translated code */ size_t size; }; diff --git a/include/tcg/helper-gen.h b/include/tcg/helper-gen.h index 8e1e52e..4ccab60 100644 --- a/include/tcg/helper-gen.h +++ b/include/tcg/helper-gen.h @@ -6,70 +6,56 @@ #include "helper-head.h" -#define DEF_HELPER_FLAGS_0(name, flags, ret) \ -static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret)) \ -{ \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 0, NULL); \ -} +#define DEF_HELPER_FLAGS_0(name, flags, ret) \ + static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret)) { \ + tcg_gen_callN(HELPER(name), dh_retvar(ret), 0, NULL); \ + } -#define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ -static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1)) \ -{ \ - TCGTemp *args[1] = { dh_arg(t1, 1) }; \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 1, args); \ -} +#define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ + static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) dh_arg_decl(t1, 1)) { \ + TCGTemp *args[1] = {dh_arg(t1, 1)}; \ + tcg_gen_callN(HELPER(name), dh_retvar(ret), 1, args); \ + } -#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ -static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) \ -{ \ - TCGTemp *args[2] = { dh_arg(t1, 1), dh_arg(t2, 2) }; \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 2, args); \ -} +#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ + static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) { \ + TCGTemp *args[2] = {dh_arg(t1, 1), dh_arg(t2, 2)}; \ + tcg_gen_callN(HELPER(name), dh_retvar(ret), 2, args); \ + } -#define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ -static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \ -{ \ - TCGTemp *args[3] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3) }; \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 3, args); \ -} +#define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ + static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), \ + dh_arg_decl(t3, 3)) { \ + TCGTemp *args[3] = {dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3)}; \ + tcg_gen_callN(HELPER(name), dh_retvar(ret), 3, args); \ + } -#define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ -static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), \ - dh_arg_decl(t3, 3), dh_arg_decl(t4, 4)) \ -{ \ - TCGTemp *args[4] = { dh_arg(t1, 1), dh_arg(t2, 2), \ - dh_arg(t3, 3), dh_arg(t4, 4) }; \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 4, args); \ -} +#define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ + static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), \ + dh_arg_decl(t3, 3), dh_arg_decl(t4, 4)) { \ + TCGTemp *args[4] = {dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), dh_arg(t4, 4)}; \ + tcg_gen_callN(HELPER(name), dh_retvar(ret), 4, args); \ + } -#define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ -static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ - dh_arg_decl(t4, 4), dh_arg_decl(t5, 5)) \ -{ \ - TCGTemp *args[5] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ - dh_arg(t4, 4), dh_arg(t5, 5) }; \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 5, args); \ -} +#define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ + static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), \ + dh_arg_decl(t3, 3), dh_arg_decl(t4, 4), dh_arg_decl(t5, 5)) { \ + TCGTemp *args[5] = {dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), dh_arg(t4, 4), dh_arg(t5, 5)}; \ + tcg_gen_callN(HELPER(name), dh_retvar(ret), 5, args); \ + } -#define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ -static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ - dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6)) \ -{ \ - TCGTemp *args[6] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ - dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6) }; \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 6, args); \ -} +#define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ + static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), \ + dh_arg_decl(t3, 3), dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), \ + dh_arg_decl(t6, 6)) { \ + TCGTemp *args[6] = {dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6)}; \ + tcg_gen_callN(HELPER(name), dh_retvar(ret), 6, args); \ + } #include "helper.h" /*#include "trace/generated-helpers.h" -#include "trace/generated-helpers-wrappers.h"*/ #include "tcg-runtime.h" +#include "trace/generated-helpers-wrappers.h"*/ #undef DEF_HELPER_FLAGS_0 #undef DEF_HELPER_FLAGS_1 diff --git a/include/tcg/helper-head.h b/include/tcg/helper-head.h index 70c8377..fcbcdd2 100644 --- a/include/tcg/helper-head.h +++ b/include/tcg/helper-head.h @@ -50,16 +50,16 @@ #define dh_ctype(t) dh_ctype_##t //#ifdef NEED_CPU_H -# ifdef TARGET_LONG_BITS -# if TARGET_LONG_BITS == 32 -# define dh_alias_tl i32 -# else -# define dh_alias_tl i64 -# endif -# endif -# define dh_alias_env ptr -# define dh_ctype_tl target_ulong -# define dh_ctype_env CPUArchState * +#ifdef TARGET_LONG_BITS +#if TARGET_LONG_BITS == 32 +#define dh_alias_tl i32 +#else +#define dh_alias_tl i64 +#endif +#endif +#define dh_alias_env ptr +#define dh_ctype_tl target_ulong +#define dh_ctype_env CPUArchState * //#endif /* We can't use glue() here because it falls foul of C preprocessor @@ -102,7 +102,7 @@ #define dh_is_signed_f16 0 #define dh_is_signed_f32 0 #define dh_is_signed_f64 0 -#define dh_is_signed_tl 0 +#define dh_is_signed_tl 0 #define dh_is_signed_int 1 /* ??? This is highly specific to the host cpu. There are even special extension instructions that may be required, e.g. ia64's addp4. But @@ -112,42 +112,33 @@ #define dh_is_signed_env dh_is_signed_ptr #define dh_is_signed(t) dh_is_signed_##t -#define dh_callflag_i32 0 -#define dh_callflag_s32 0 -#define dh_callflag_int 0 -#define dh_callflag_i64 0 -#define dh_callflag_s64 0 -#define dh_callflag_f16 0 -#define dh_callflag_f32 0 -#define dh_callflag_f64 0 -#define dh_callflag_ptr 0 +#define dh_callflag_i32 0 +#define dh_callflag_s32 0 +#define dh_callflag_int 0 +#define dh_callflag_i64 0 +#define dh_callflag_s64 0 +#define dh_callflag_f16 0 +#define dh_callflag_f32 0 +#define dh_callflag_f64 0 +#define dh_callflag_ptr 0 #define dh_callflag_cptr dh_callflag_ptr #define dh_callflag_void 0 #define dh_callflag_noreturn TCG_CALL_NO_RETURN #define dh_callflag(t) glue(dh_callflag_, dh_alias(t)) -#define dh_sizemask(t, n) \ - ((dh_is_64bit(t) << (n*2)) | (dh_is_signed(t) << (n*2+1))) +#define dh_sizemask(t, n) ((dh_is_64bit(t) << (n * 2)) | (dh_is_signed(t) << (n * 2 + 1))) -#define dh_arg(t, n) \ - glue(glue(tcgv_, dh_alias(t)), _temp)(glue(arg, n)) +#define dh_arg(t, n) glue(glue(tcgv_, dh_alias(t)), _temp)(glue(arg, n)) #define dh_arg_decl(t, n) glue(TCGv_, dh_alias(t)) glue(arg, n) -#define DEF_HELPER_0(name, ret) \ - DEF_HELPER_FLAGS_0(name, 0, ret) -#define DEF_HELPER_1(name, ret, t1) \ - DEF_HELPER_FLAGS_1(name, 0, ret, t1) -#define DEF_HELPER_2(name, ret, t1, t2) \ - DEF_HELPER_FLAGS_2(name, 0, ret, t1, t2) -#define DEF_HELPER_3(name, ret, t1, t2, t3) \ - DEF_HELPER_FLAGS_3(name, 0, ret, t1, t2, t3) -#define DEF_HELPER_4(name, ret, t1, t2, t3, t4) \ - DEF_HELPER_FLAGS_4(name, 0, ret, t1, t2, t3, t4) -#define DEF_HELPER_5(name, ret, t1, t2, t3, t4, t5) \ - DEF_HELPER_FLAGS_5(name, 0, ret, t1, t2, t3, t4, t5) -#define DEF_HELPER_6(name, ret, t1, t2, t3, t4, t5, t6) \ - DEF_HELPER_FLAGS_6(name, 0, ret, t1, t2, t3, t4, t5, t6) +#define DEF_HELPER_0(name, ret) DEF_HELPER_FLAGS_0(name, 0, ret) +#define DEF_HELPER_1(name, ret, t1) DEF_HELPER_FLAGS_1(name, 0, ret, t1) +#define DEF_HELPER_2(name, ret, t1, t2) DEF_HELPER_FLAGS_2(name, 0, ret, t1, t2) +#define DEF_HELPER_3(name, ret, t1, t2, t3) DEF_HELPER_FLAGS_3(name, 0, ret, t1, t2, t3) +#define DEF_HELPER_4(name, ret, t1, t2, t3, t4) DEF_HELPER_FLAGS_4(name, 0, ret, t1, t2, t3, t4) +#define DEF_HELPER_5(name, ret, t1, t2, t3, t4, t5) DEF_HELPER_FLAGS_5(name, 0, ret, t1, t2, t3, t4, t5) +#define DEF_HELPER_6(name, ret, t1, t2, t3, t4, t5, t6) DEF_HELPER_FLAGS_6(name, 0, ret, t1, t2, t3, t4, t5, t6) /* MAX_OPC_PARAM_IARGS must be set to n if last entry is DEF_HELPER_FLAGS_n. */ diff --git a/include/tcg/helper-proto.h b/include/tcg/helper-proto.h index 6d0a056..9484c7b 100644 --- a/include/tcg/helper-proto.h +++ b/include/tcg/helper-proto.h @@ -6,29 +6,23 @@ #include "helper-head.h" -#define DEF_HELPER_FLAGS_0(name, flags, ret) \ -dh_ctype(ret) HELPER(name) (void); +#define DEF_HELPER_FLAGS_0(name, flags, ret) dh_ctype(ret) HELPER(name)(void); -#define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1)); +#define DEF_HELPER_FLAGS_1(name, flags, ret, t1) dh_ctype(ret) HELPER(name)(dh_ctype(t1)); -#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2)); +#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) dh_ctype(ret) HELPER(name)(dh_ctype(t1), dh_ctype(t2)); #define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3)); + dh_ctype(ret) HELPER(name)(dh_ctype(t1), dh_ctype(t2), dh_ctype(t3)); #define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ - dh_ctype(t4)); + dh_ctype(ret) HELPER(name)(dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), dh_ctype(t4)); #define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ - dh_ctype(t4), dh_ctype(t5)); + dh_ctype(ret) HELPER(name)(dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), dh_ctype(t4), dh_ctype(t5)); #define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ - dh_ctype(t4), dh_ctype(t5), dh_ctype(t6)); + dh_ctype(ret) HELPER(name)(dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), dh_ctype(t4), dh_ctype(t5), dh_ctype(t6)); #include "helper.h" // #include "trace/generated-helpers.h" diff --git a/include/tcg/helper-tcg.h b/include/tcg/helper-tcg.h index 4da88d0..86189a7 100644 --- a/include/tcg/helper-tcg.h +++ b/include/tcg/helper-tcg.h @@ -11,46 +11,46 @@ #define str(s) #s #define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \ - { .func = HELPER(NAME), .name = str(NAME), \ - .flags = FLAGS | dh_callflag(ret), \ - .sizemask = dh_sizemask(ret, 0) }, + {.func = HELPER(NAME), .name = str(NAME), .flags = FLAGS | dh_callflag(ret), .sizemask = dh_sizemask(ret, 0)}, #define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \ - { .func = HELPER(NAME), .name = str(NAME), \ - .flags = FLAGS | dh_callflag(ret), \ - .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) }, + {.func = HELPER(NAME), \ + .name = str(NAME), \ + .flags = FLAGS | dh_callflag(ret), \ + .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1)}, #define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \ - { .func = HELPER(NAME), .name = str(NAME), \ - .flags = FLAGS | dh_callflag(ret), \ - .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ - | dh_sizemask(t2, 2) }, + {.func = HELPER(NAME), \ + .name = str(NAME), \ + .flags = FLAGS | dh_callflag(ret), \ + .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) | dh_sizemask(t2, 2)}, #define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \ - { .func = HELPER(NAME), .name = str(NAME), \ - .flags = FLAGS | dh_callflag(ret), \ - .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ - | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) }, + {.func = HELPER(NAME), \ + .name = str(NAME), \ + .flags = FLAGS | dh_callflag(ret), \ + .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) | dh_sizemask(t2, 2) | dh_sizemask(t3, 3)}, #define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \ - { .func = HELPER(NAME), .name = str(NAME), \ - .flags = FLAGS | dh_callflag(ret), \ - .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ - | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) }, + {.func = HELPER(NAME), \ + .name = str(NAME), \ + .flags = FLAGS | dh_callflag(ret), \ + .sizemask = \ + dh_sizemask(ret, 0) | dh_sizemask(t1, 1) | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4)}, -#define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \ - { .func = HELPER(NAME), .name = str(NAME), \ - .flags = FLAGS | dh_callflag(ret), \ - .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ - | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ - | dh_sizemask(t5, 5) }, +#define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \ + {.func = HELPER(NAME), \ + .name = str(NAME), \ + .flags = FLAGS | dh_callflag(ret), \ + .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | \ + dh_sizemask(t4, 4) | dh_sizemask(t5, 5)}, -#define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \ - { .func = HELPER(NAME), .name = str(NAME), \ - .flags = FLAGS | dh_callflag(ret), \ - .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ - | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ - | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) }, +#define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \ + {.func = HELPER(NAME), \ + .name = str(NAME), \ + .flags = FLAGS | dh_callflag(ret), \ + .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | \ + dh_sizemask(t4, 4) | dh_sizemask(t5, 5) | dh_sizemask(t6, 6)}, #include // #include diff --git a/include/tcg/i386/tcg-target.h b/include/tcg/i386/tcg-target.h index ee743d5..77062da 100644 --- a/include/tcg/i386/tcg-target.h +++ b/include/tcg/i386/tcg-target.h @@ -25,15 +25,15 @@ #ifndef I386_TCG_TARGET_H #define I386_TCG_TARGET_H -#define TCG_TARGET_INSN_UNIT_SIZE 1 +#define TCG_TARGET_INSN_UNIT_SIZE 1 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 31 #ifdef __x86_64__ -# define TCG_TARGET_REG_BITS 64 -# define TCG_TARGET_NB_REGS 32 +#define TCG_TARGET_REG_BITS 64 +#define TCG_TARGET_NB_REGS 32 #else -# define TCG_TARGET_REG_BITS 32 -# define TCG_TARGET_NB_REGS 24 +#define TCG_TARGET_REG_BITS 32 +#define TCG_TARGET_NB_REGS 24 #endif typedef enum { @@ -103,111 +103,106 @@ extern bool have_avx1; extern bool have_avx2; /* optional instructions */ -#define TCG_TARGET_HAS_div2_i32 1 -#define TCG_TARGET_HAS_rot_i32 1 -#define TCG_TARGET_HAS_ext8s_i32 1 -#define TCG_TARGET_HAS_ext16s_i32 1 -#define TCG_TARGET_HAS_ext8u_i32 1 -#define TCG_TARGET_HAS_ext16u_i32 1 -#define TCG_TARGET_HAS_bswap16_i32 1 -#define TCG_TARGET_HAS_bswap32_i32 1 -#define TCG_TARGET_HAS_neg_i32 1 -#define TCG_TARGET_HAS_not_i32 1 -#define TCG_TARGET_HAS_andc_i32 have_bmi1 -#define TCG_TARGET_HAS_orc_i32 0 -#define TCG_TARGET_HAS_eqv_i32 0 -#define TCG_TARGET_HAS_nand_i32 0 -#define TCG_TARGET_HAS_nor_i32 0 -#define TCG_TARGET_HAS_clz_i32 1 -#define TCG_TARGET_HAS_ctz_i32 1 -#define TCG_TARGET_HAS_ctpop_i32 have_popcnt -#define TCG_TARGET_HAS_deposit_i32 1 -#define TCG_TARGET_HAS_extract_i32 1 -#define TCG_TARGET_HAS_sextract_i32 1 -#define TCG_TARGET_HAS_movcond_i32 1 -#define TCG_TARGET_HAS_add2_i32 1 -#define TCG_TARGET_HAS_sub2_i32 1 -#define TCG_TARGET_HAS_mulu2_i32 1 -#define TCG_TARGET_HAS_muls2_i32 1 -#define TCG_TARGET_HAS_muluh_i32 0 -#define TCG_TARGET_HAS_mulsh_i32 0 -#define TCG_TARGET_HAS_goto_ptr 1 -#define TCG_TARGET_HAS_direct_jump 1 +#define TCG_TARGET_HAS_div2_i32 1 +#define TCG_TARGET_HAS_rot_i32 1 +#define TCG_TARGET_HAS_ext8s_i32 1 +#define TCG_TARGET_HAS_ext16s_i32 1 +#define TCG_TARGET_HAS_ext8u_i32 1 +#define TCG_TARGET_HAS_ext16u_i32 1 +#define TCG_TARGET_HAS_bswap16_i32 1 +#define TCG_TARGET_HAS_bswap32_i32 1 +#define TCG_TARGET_HAS_neg_i32 1 +#define TCG_TARGET_HAS_not_i32 1 +#define TCG_TARGET_HAS_andc_i32 have_bmi1 +#define TCG_TARGET_HAS_orc_i32 0 +#define TCG_TARGET_HAS_eqv_i32 0 +#define TCG_TARGET_HAS_nand_i32 0 +#define TCG_TARGET_HAS_nor_i32 0 +#define TCG_TARGET_HAS_clz_i32 1 +#define TCG_TARGET_HAS_ctz_i32 1 +#define TCG_TARGET_HAS_ctpop_i32 have_popcnt +#define TCG_TARGET_HAS_deposit_i32 1 +#define TCG_TARGET_HAS_extract_i32 1 +#define TCG_TARGET_HAS_sextract_i32 1 +#define TCG_TARGET_HAS_movcond_i32 1 +#define TCG_TARGET_HAS_add2_i32 1 +#define TCG_TARGET_HAS_sub2_i32 1 +#define TCG_TARGET_HAS_mulu2_i32 1 +#define TCG_TARGET_HAS_muls2_i32 1 +#define TCG_TARGET_HAS_muluh_i32 0 +#define TCG_TARGET_HAS_mulsh_i32 0 +#define TCG_TARGET_HAS_goto_ptr 1 +#define TCG_TARGET_HAS_direct_jump 1 #if TCG_TARGET_REG_BITS == 64 /* Keep target addresses zero-extended in a register. */ -#define TCG_TARGET_HAS_extrl_i64_i32 (TARGET_LONG_BITS == 32) -#define TCG_TARGET_HAS_extrh_i64_i32 (TARGET_LONG_BITS == 32) -#define TCG_TARGET_HAS_div2_i64 1 -#define TCG_TARGET_HAS_rot_i64 1 -#define TCG_TARGET_HAS_ext8s_i64 1 -#define TCG_TARGET_HAS_ext16s_i64 1 -#define TCG_TARGET_HAS_ext32s_i64 1 -#define TCG_TARGET_HAS_ext8u_i64 1 -#define TCG_TARGET_HAS_ext16u_i64 1 -#define TCG_TARGET_HAS_ext32u_i64 1 -#define TCG_TARGET_HAS_bswap16_i64 1 -#define TCG_TARGET_HAS_bswap32_i64 1 -#define TCG_TARGET_HAS_bswap64_i64 1 -#define TCG_TARGET_HAS_neg_i64 1 -#define TCG_TARGET_HAS_not_i64 1 -#define TCG_TARGET_HAS_andc_i64 have_bmi1 -#define TCG_TARGET_HAS_orc_i64 0 -#define TCG_TARGET_HAS_eqv_i64 0 -#define TCG_TARGET_HAS_nand_i64 0 -#define TCG_TARGET_HAS_nor_i64 0 -#define TCG_TARGET_HAS_clz_i64 1 -#define TCG_TARGET_HAS_ctz_i64 1 -#define TCG_TARGET_HAS_ctpop_i64 have_popcnt -#define TCG_TARGET_HAS_deposit_i64 1 -#define TCG_TARGET_HAS_extract_i64 1 -#define TCG_TARGET_HAS_sextract_i64 0 -#define TCG_TARGET_HAS_movcond_i64 1 -#define TCG_TARGET_HAS_add2_i64 1 -#define TCG_TARGET_HAS_sub2_i64 1 -#define TCG_TARGET_HAS_mulu2_i64 1 -#define TCG_TARGET_HAS_muls2_i64 1 -#define TCG_TARGET_HAS_muluh_i64 0 -#define TCG_TARGET_HAS_mulsh_i64 0 +#define TCG_TARGET_HAS_extrl_i64_i32 (TARGET_LONG_BITS == 32) +#define TCG_TARGET_HAS_extrh_i64_i32 (TARGET_LONG_BITS == 32) +#define TCG_TARGET_HAS_div2_i64 1 +#define TCG_TARGET_HAS_rot_i64 1 +#define TCG_TARGET_HAS_ext8s_i64 1 +#define TCG_TARGET_HAS_ext16s_i64 1 +#define TCG_TARGET_HAS_ext32s_i64 1 +#define TCG_TARGET_HAS_ext8u_i64 1 +#define TCG_TARGET_HAS_ext16u_i64 1 +#define TCG_TARGET_HAS_ext32u_i64 1 +#define TCG_TARGET_HAS_bswap16_i64 1 +#define TCG_TARGET_HAS_bswap32_i64 1 +#define TCG_TARGET_HAS_bswap64_i64 1 +#define TCG_TARGET_HAS_neg_i64 1 +#define TCG_TARGET_HAS_not_i64 1 +#define TCG_TARGET_HAS_andc_i64 have_bmi1 +#define TCG_TARGET_HAS_orc_i64 0 +#define TCG_TARGET_HAS_eqv_i64 0 +#define TCG_TARGET_HAS_nand_i64 0 +#define TCG_TARGET_HAS_nor_i64 0 +#define TCG_TARGET_HAS_clz_i64 1 +#define TCG_TARGET_HAS_ctz_i64 1 +#define TCG_TARGET_HAS_ctpop_i64 have_popcnt +#define TCG_TARGET_HAS_deposit_i64 1 +#define TCG_TARGET_HAS_extract_i64 1 +#define TCG_TARGET_HAS_sextract_i64 0 +#define TCG_TARGET_HAS_movcond_i64 1 +#define TCG_TARGET_HAS_add2_i64 1 +#define TCG_TARGET_HAS_sub2_i64 1 +#define TCG_TARGET_HAS_mulu2_i64 1 +#define TCG_TARGET_HAS_muls2_i64 1 +#define TCG_TARGET_HAS_muluh_i64 0 +#define TCG_TARGET_HAS_mulsh_i64 0 #endif /* We do not support older SSE systems, only beginning with AVX1. */ -#define TCG_TARGET_HAS_v64 have_avx1 -#define TCG_TARGET_HAS_v128 have_avx1 -#define TCG_TARGET_HAS_v256 have_avx2 - -#define TCG_TARGET_HAS_andc_vec 1 -#define TCG_TARGET_HAS_orc_vec 0 -#define TCG_TARGET_HAS_not_vec 0 -#define TCG_TARGET_HAS_neg_vec 0 -#define TCG_TARGET_HAS_shi_vec 1 -#define TCG_TARGET_HAS_shs_vec 0 -#define TCG_TARGET_HAS_shv_vec 0 -#define TCG_TARGET_HAS_cmp_vec 1 -#define TCG_TARGET_HAS_mul_vec 1 -#define TCG_TARGET_HAS_sat_vec 1 -#define TCG_TARGET_HAS_minmax_vec 1 +#define TCG_TARGET_HAS_v64 have_avx1 +#define TCG_TARGET_HAS_v128 have_avx1 +#define TCG_TARGET_HAS_v256 have_avx2 + +#define TCG_TARGET_HAS_andc_vec 1 +#define TCG_TARGET_HAS_orc_vec 0 +#define TCG_TARGET_HAS_not_vec 0 +#define TCG_TARGET_HAS_neg_vec 0 +#define TCG_TARGET_HAS_shi_vec 1 +#define TCG_TARGET_HAS_shs_vec 0 +#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_cmp_vec 1 +#define TCG_TARGET_HAS_mul_vec 1 +#define TCG_TARGET_HAS_sat_vec 1 +#define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_deposit_i32_valid(ofs, len) \ - (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \ - ((ofs) == 0 && (len) == 16)) -#define TCG_TARGET_deposit_i64_valid TCG_TARGET_deposit_i32_valid + (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || ((ofs) == 0 && (len) == 16)) +#define TCG_TARGET_deposit_i64_valid TCG_TARGET_deposit_i32_valid /* Check for the possibility of high-byte extraction and, for 64-bit, zero-extending 32-bit right-shift. */ #define TCG_TARGET_extract_i32_valid(ofs, len) ((ofs) == 8 && (len) == 8) -#define TCG_TARGET_extract_i64_valid(ofs, len) \ - (((ofs) == 8 && (len) == 8) || ((ofs) + (len)) == 32) +#define TCG_TARGET_extract_i64_valid(ofs, len) (((ofs) == 8 && (len) == 8) || ((ofs) + (len)) == 32) -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ +static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { } -static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, - uintptr_t jmp_addr, uintptr_t addr) -{ +static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, uintptr_t addr) { /* patch the branch destination */ - atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); + atomic_set((int32_t *) jmp_addr, addr - (jmp_addr + 4)); /* no need to flush icache explicitly */ } @@ -222,7 +217,7 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) -#define TCG_TARGET_HAS_MEMORY_BSWAP 1 +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS diff --git a/include/tcg/tb.h b/include/tcg/tb.h index 2237198..c60b357 100644 --- a/include/tcg/tb.h +++ b/include/tcg/tb.h @@ -66,16 +66,16 @@ struct TranslationBlock { uint16_t size; /* size of target code for this block (1 <= size <= TARGET_PAGE_SIZE) */ -#define CF_COUNT_MASK 0x00007fff -#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ -#define CF_NOCACHE 0x00010000 /* To be freed after execution */ -#define CF_USE_ICOUNT 0x00020000 -#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held */ -#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */ +#define CF_COUNT_MASK 0x00007fff +#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ +#define CF_NOCACHE 0x00010000 /* To be freed after execution */ +#define CF_USE_ICOUNT 0x00020000 +#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held */ +#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */ #define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ #define CF_CLUSTER_SHIFT 24 - uint16_t cflags; /* compile flags */ + uint16_t cflags; /* compile flags */ // uint8_t *tc_ptr; /* pointer to the translated code */ // unsigned tc_size; /* size of the translated code */ @@ -88,7 +88,6 @@ struct TranslationBlock { struct TranslationBlock *page_next[2]; tb_page_addr_t page_addr[2]; - /* jmp_lock placed here to fill a 4-byte hole. Its documentation is below */ spinlock_t jmp_lock; @@ -99,9 +98,9 @@ struct TranslationBlock { * setting one of the jump targets (or patching the jump instruction). Only * two of such jumps are supported. */ - uint16_t jmp_reset_offset[2]; /* offset of original jump target */ + uint16_t jmp_reset_offset[2]; /* offset of original jump target */ #define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated */ - uintptr_t jmp_target_arg[2]; /* target address or offset */ + uintptr_t jmp_target_arg[2]; /* target address or offset */ /* * Each TB has a NULL-terminated list (jmp_list_head) of incoming jumps. @@ -124,7 +123,6 @@ struct TranslationBlock { uintptr_t jmp_list_next[2]; uintptr_t jmp_dest[2]; - uint32_t icount; #ifdef CONFIG_SYMBEX @@ -172,8 +170,7 @@ struct TranslationBlock { typedef struct TranslationBlock TranslationBlock; /* Hide the atomic_read to make code a little easier on the eyes */ -static inline uint32_t tb_cflags(const TranslationBlock *tb) -{ +static inline uint32_t tb_cflags(const TranslationBlock *tb) { return atomic_read(&tb->cflags); } diff --git a/include/tcg/tcg-mo.h b/include/tcg/tcg-mo.h index c2c5570..d1eebaa 100644 --- a/include/tcg/tcg-mo.h +++ b/include/tcg/tcg-mo.h @@ -31,18 +31,18 @@ typedef enum { This is of the form TCG_MO_A_B where A is before B in program order. */ - TCG_MO_LD_LD = 0x01, - TCG_MO_ST_LD = 0x02, - TCG_MO_LD_ST = 0x04, - TCG_MO_ST_ST = 0x08, - TCG_MO_ALL = 0x0F, /* OR of the above */ + TCG_MO_LD_LD = 0x01, + TCG_MO_ST_LD = 0x02, + TCG_MO_LD_ST = 0x04, + TCG_MO_ST_ST = 0x08, + TCG_MO_ALL = 0x0F, /* OR of the above */ /* Used to indicate the kind of ordering which is to be ensured by the instruction. These types are derived from x86/aarch64 instructions. It should be noted that these are different from C11 semantics. */ - TCG_BAR_LDAQ = 0x10, /* Following ops will not come forward */ - TCG_BAR_STRL = 0x20, /* Previous ops will not be delayed */ - TCG_BAR_SC = 0x30, /* No ops cross barrier; OR of the above */ + TCG_BAR_LDAQ = 0x10, /* Following ops will not come forward */ + TCG_BAR_STRL = 0x20, /* Previous ops will not be delayed */ + TCG_BAR_SC = 0x30, /* No ops cross barrier; OR of the above */ } TCGBar; #endif /* TCG_MO_H */ diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index bf48c0c..117a955 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -46,225 +46,150 @@ void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg); void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg); void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg); -static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1) -{ +static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1) { tcg_gen_op1(opc, tcgv_i32_arg(a1)); } -static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1) -{ +static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1) { tcg_gen_op1(opc, tcgv_i64_arg(a1)); } -static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1) -{ +static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1) { tcg_gen_op1(opc, a1); } -static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2) -{ +static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2) { tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2)); } -static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2) -{ +static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2) { tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2)); } -static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2) -{ +static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2) { tcg_gen_op2(opc, tcgv_i32_arg(a1), a2); } -static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2) -{ +static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2) { tcg_gen_op2(opc, tcgv_i64_arg(a1), a2); } -static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2) -{ +static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2) { tcg_gen_op2(opc, a1, a2); } -static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1, - TCGv_i32 a2, TCGv_i32 a3) -{ +static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3) { tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3)); } -static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1, - TCGv_i64 a2, TCGv_i64 a3) -{ +static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3) { tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3)); } -static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1, - TCGv_i32 a2, TCGArg a3) -{ +static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGArg a3) { tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3); } -static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1, - TCGv_i64 a2, TCGArg a3) -{ +static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGArg a3) { tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3); } -static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, - TCGv_ptr base, TCGArg offset) -{ +static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, TCGv_ptr base, TCGArg offset) { tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset); } -static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, - TCGv_ptr base, TCGArg offset) -{ +static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, TCGv_ptr base, TCGArg offset) { tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset); } -static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGv_i32 a4) -{ - tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4)); +static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4) { + tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3), tcgv_i32_arg(a4)); } -static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGv_i64 a4) -{ - tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4)); +static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4) { + tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3), tcgv_i64_arg(a4)); } -static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGArg a4) -{ - tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), a4); +static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGArg a4) { + tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3), a4); } -static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGArg a4) -{ - tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), a4); +static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGArg a4) { + tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3), a4); } -static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGArg a3, TCGArg a4) -{ +static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGArg a3, TCGArg a4) { tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4); } -static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGArg a3, TCGArg a4) -{ +static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGArg a3, TCGArg a4) { tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4); } -static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5) -{ - tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5)); +static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5) { + tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5)); } -static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5) -{ - tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5)); +static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5) { + tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5)); } -static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGv_i32 a4, TCGArg a5) -{ - tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5); +static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4, TCGArg a5) { + tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5); } -static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGv_i64 a4, TCGArg a5) -{ - tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5); +static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4, TCGArg a5) { + tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5); } -static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGArg a4, TCGArg a5) -{ - tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), a4, a5); +static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGArg a4, TCGArg a5) { + tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3), a4, a5); } -static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGArg a4, TCGArg a5) -{ - tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), a4, a5); +static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGArg a4, TCGArg a5) { + tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3), a4, a5); } -static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGv_i32 a4, - TCGv_i32 a5, TCGv_i32 a6) -{ - tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), +static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5, + TCGv_i32 a6) { + tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), tcgv_i32_arg(a6)); } -static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGv_i64 a4, - TCGv_i64 a5, TCGv_i64 a6) -{ - tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), +static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5, + TCGv_i64 a6) { + tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), tcgv_i64_arg(a6)); } -static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGv_i32 a4, - TCGv_i32 a5, TCGArg a6) -{ - tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6); +static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5, + TCGArg a6) { + tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6); } -static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGv_i64 a4, - TCGv_i64 a5, TCGArg a6) -{ - tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6); +static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5, + TCGArg a6) { + tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6); } -static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGv_i32 a4, - TCGArg a5, TCGArg a6) -{ - tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6); +static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4, TCGArg a5, + TCGArg a6) { + tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6); } -static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGv_i64 a4, - TCGArg a5, TCGArg a6) -{ - tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6); +static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4, TCGArg a5, + TCGArg a6) { + tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6); } - /* Generic ops. */ -static inline void gen_set_label(TCGLabel *l) -{ +static inline void gen_set_label(TCGLabel *l) { l->present = 1; tcg_gen_op1(INDEX_op_set_label, label_arg(l)); } -static inline void tcg_gen_br(TCGLabel *l) -{ +static inline void tcg_gen_br(TCGLabel *l) { l->refs++; tcg_gen_op1(INDEX_op_br, label_arg(l)); } @@ -304,26 +229,17 @@ void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); -void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, - unsigned int ofs, unsigned int len); -void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, - unsigned int ofs, unsigned int len); -void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, - unsigned int ofs, unsigned int len); -void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, - unsigned int ofs, unsigned int len); +void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, unsigned int ofs, unsigned int len); +void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len); +void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len); +void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len); void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *); void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *); -void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, - TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, - TCGv_i32 arg1, int32_t arg2); -void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, - TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2); -void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, - TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); -void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, - TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); +void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2); +void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); +void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); @@ -338,118 +254,89 @@ void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); -static inline void tcg_gen_discard_i32(TCGv_i32 arg) -{ +static inline void tcg_gen_discard_i32(TCGv_i32 arg) { tcg_gen_op1_i32(INDEX_op_discard, arg); } -static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) -{ +static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) { if (ret != arg) { tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); } } -static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) -{ +static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) { tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); } -static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); } -static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); } -static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); } -static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); } -static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); } -static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); } -static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); } -static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); } -static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); } -static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); } -static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); } -static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); } -static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); } -static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); } -static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); } -static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); } -static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); } -static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) -{ +static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) { if (TCG_TARGET_HAS_neg_i32) { tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); } else { @@ -457,8 +344,7 @@ static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) } } -static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) -{ +static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) { if (TCG_TARGET_HAS_not_i32) { tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); } else { @@ -497,26 +383,17 @@ void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); -void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, - unsigned int ofs, unsigned int len); -void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, - unsigned int ofs, unsigned int len); -void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, - unsigned int ofs, unsigned int len); -void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, - unsigned int ofs, unsigned int len); +void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, unsigned int ofs, unsigned int len); +void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len); +void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len); +void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len); void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *); void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *); -void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, - TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, - TCGv_i64 arg1, int64_t arg2); -void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, - TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2); -void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, - TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); -void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, - TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); +void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2); +void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); +void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); @@ -536,162 +413,118 @@ void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); #if TCG_TARGET_REG_BITS == 64 -static inline void tcg_gen_discard_i64(TCGv_i64 arg) -{ +static inline void tcg_gen_discard_i64(TCGv_i64 arg) { tcg_gen_op1_i64(INDEX_op_discard, arg); } -static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) -{ +static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) { if (ret != arg) { tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); } } -static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) -{ +static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) { tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); } -static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); } -static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); } -static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); } -static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); } -static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); } -static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); } -static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); } -static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); } -static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); } -static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); } -static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); } -static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); } -static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); } -static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); } -static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); } -static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); } -static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); } -static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); } -static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); } -static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); } -#else /* TCG_TARGET_REG_BITS == 32 */ -static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ +#else /* TCG_TARGET_REG_BITS == 32 */ +static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); } -static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); } -static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ +static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); } -static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), - TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); +static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { + tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); } -static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), - TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); +static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { + tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); } void tcg_gen_discard_i64(TCGv_i64 arg); @@ -714,8 +547,7 @@ void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); #endif /* TCG_TARGET_REG_BITS */ -static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) -{ +static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) { if (TCG_TARGET_HAS_neg_i64) { tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); } else { @@ -733,8 +565,7 @@ void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg); void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg); void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg); -static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi) -{ +static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi) { tcg_gen_deposit_i64(ret, lo, hi, 32, 32); } @@ -745,50 +576,38 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi) #endif #if TARGET_INSN_START_WORDS == 1 -# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS -static inline void tcg_gen_insn_start(target_ulong pc) -{ +#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS +static inline void tcg_gen_insn_start(target_ulong pc) { tcg_gen_op1(INDEX_op_insn_start, pc); } -# else -static inline void tcg_gen_insn_start(target_ulong pc) -{ - tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32)); +#else +static inline void tcg_gen_insn_start(target_ulong pc) { + tcg_gen_op2(INDEX_op_insn_start, (uint32_t) pc, (uint32_t)(pc >> 32)); } -# endif +#endif #elif TARGET_INSN_START_WORDS == 2 -# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS -static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) -{ +#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS +static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) { tcg_gen_op2(INDEX_op_insn_start, pc, a1); } -# else -static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) -{ - tcg_gen_op4(INDEX_op_insn_start, - (uint32_t)pc, (uint32_t)(pc >> 32), - (uint32_t)a1, (uint32_t)(a1 >> 32)); +#else +static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) { + tcg_gen_op4(INDEX_op_insn_start, (uint32_t) pc, (uint32_t)(pc >> 32), (uint32_t) a1, (uint32_t)(a1 >> 32)); } -# endif +#endif #elif TARGET_INSN_START_WORDS == 3 -# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS -static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, - target_ulong a2) -{ +#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS +static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, target_ulong a2) { tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2); } -# else -static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, - target_ulong a2) -{ - tcg_gen_op6(INDEX_op_insn_start, - (uint32_t)pc, (uint32_t)(pc >> 32), - (uint32_t)a1, (uint32_t)(a1 >> 32), - (uint32_t)a2, (uint32_t)(a2 >> 32)); +#else +static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, target_ulong a2) { + tcg_gen_op6(INDEX_op_insn_start, (uint32_t) pc, (uint32_t)(pc >> 32), (uint32_t) a1, (uint32_t)(a1 >> 32), + (uint32_t) a2, (uint32_t)(a2 >> 32)); } -# endif +#endif #else -# error "Unhandled number of operands to insn_start" +#error "Unhandled number of operands to insn_start" #endif /** @@ -854,65 +673,52 @@ void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp); void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp); void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp); -static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) -{ +static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) { tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB); } -static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) -{ +static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) { tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB); } -static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) -{ +static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) { tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW); } -static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) -{ +static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) { tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW); } -static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) -{ +static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) { tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL); } -static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) -{ +static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) { tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL); } -static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) -{ +static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) { tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEQ); } -static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) -{ +static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) { tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB); } -static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) -{ +static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) { tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW); } -static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) -{ +static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) { tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL); } -static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) -{ +static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) { tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEQ); } -void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32, - TCGArg, TCGMemOp); -void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, - TCGArg, TCGMemOp); +void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32, TCGArg, TCGMemOp); +void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, TCGArg, TCGMemOp); void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); @@ -985,8 +791,7 @@ void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); -void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r, - TCGv_vec a, TCGv_vec b); +void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); @@ -1102,7 +907,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); #define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i64 #define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i64 #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i64 -#define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec +#define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec #else #define tcg_gen_movi_tl tcg_gen_movi_i32 #define tcg_gen_mov_tl tcg_gen_mov_i32 @@ -1212,76 +1017,66 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); #define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i32 #define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i32 #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i32 -#define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec +#define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec #endif #if UINTPTR_MAX == UINT32_MAX -# define PTR i32 -# define NAT TCGv_i32 +#define PTR i32 +#define NAT TCGv_i32 #else -# define PTR i64 -# define NAT TCGv_i64 +#define PTR i64 +#define NAT TCGv_i64 #endif -static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o) -{ - glue(tcg_gen_ld_,PTR)((NAT)r, a, o); +static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o) { + glue(tcg_gen_ld_, PTR)((NAT) r, a, o); } -static inline void tcg_gen_discard_ptr(TCGv_ptr a) -{ - glue(tcg_gen_discard_,PTR)((NAT)a); +static inline void tcg_gen_discard_ptr(TCGv_ptr a) { + glue(tcg_gen_discard_, PTR)((NAT) a); } -static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b) -{ - glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b); +static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b) { + glue(tcg_gen_add_, PTR)((NAT) r, (NAT) a, (NAT) b); } -static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b) -{ - glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b); +static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b) { + glue(tcg_gen_addi_, PTR)((NAT) r, (NAT) a, b); } -static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a, - intptr_t b, TCGLabel *label) -{ - glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label); +static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a, intptr_t b, TCGLabel *label) { + glue(tcg_gen_brcondi_, PTR)(cond, (NAT) a, b, label); } -static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a) -{ +static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a) { #if UINTPTR_MAX == UINT32_MAX - tcg_gen_mov_i32((NAT)r, a); + tcg_gen_mov_i32((NAT) r, a); #else - tcg_gen_ext_i32_i64((NAT)r, a); + tcg_gen_ext_i32_i64((NAT) r, a); #endif } -static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a) -{ +static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a) { #if UINTPTR_MAX == UINT32_MAX - tcg_gen_extrl_i64_i32((NAT)r, a); + tcg_gen_extrl_i64_i32((NAT) r, a); #else - tcg_gen_mov_i64((NAT)r, a); + tcg_gen_mov_i64((NAT) r, a); #endif } -static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a) -{ +static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a) { #if UINTPTR_MAX == UINT32_MAX - tcg_gen_extu_i32_i64(r, (NAT)a); + tcg_gen_extu_i32_i64(r, (NAT) a); #else - tcg_gen_mov_i64(r, (NAT)a); + tcg_gen_mov_i64(r, (NAT) a); #endif } -static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a) -{ +static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a) { #if UINTPTR_MAX == UINT32_MAX - tcg_gen_mov_i32(r, (NAT)a); + tcg_gen_mov_i32(r, (NAT) a); #else - tcg_gen_extrl_i64_i32(r, (NAT)a); + tcg_gen_extrl_i64_i32(r, (NAT) a); #endif } diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 339137f..26ad445 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -37,9 +37,9 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END) #define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0) #if TCG_TARGET_REG_BITS == 32 -# define IMPL64 TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT +#define IMPL64 TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT #else -# define IMPL64 TCG_OPF_64BIT +#define IMPL64 TCG_OPF_64BIT #endif DEF(mb, 0, 0, 1, 0) @@ -150,12 +150,8 @@ DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64)) /* size changing ops */ DEF(ext_i32_i64, 1, 1, 0, IMPL64) DEF(extu_i32_i64, 1, 1, 0, IMPL64) -DEF(extrl_i64_i32, 1, 1, 0, - IMPL(TCG_TARGET_HAS_extrl_i64_i32) - | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0)) -DEF(extrh_i64_i32, 1, 1, 0, - IMPL(TCG_TARGET_HAS_extrh_i64_i32) - | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0)) +DEF(extrl_i64_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_extrl_i64_i32) | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0)) +DEF(extrh_i64_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_extrh_i64_i32) | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0)) DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64) DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64)) @@ -185,29 +181,23 @@ DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64)) DEF(muluh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muluh_i64)) DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64)) -#define TLADDR_ARGS (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2) -#define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2) +#define TLADDR_ARGS (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2) +#define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2) /* QEMU specific */ -DEF(insn_start, 0, 0, TLADDR_ARGS * TARGET_INSN_START_WORDS, - TCG_OPF_NOT_PRESENT) +DEF(insn_start, 0, 0, TLADDR_ARGS *TARGET_INSN_START_WORDS, TCG_OPF_NOT_PRESENT) DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) -DEF(goto_ptr, 0, 1, 0, - TCG_OPF_BB_EXIT | TCG_OPF_BB_END | IMPL(TCG_TARGET_HAS_goto_ptr)) +DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END | IMPL(TCG_TARGET_HAS_goto_ptr)) -DEF(qemu_ld_i32, 1, TLADDR_ARGS, 1, - TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) -DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 1, - TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) -DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1, - TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) -DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1, - TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) +DEF(qemu_ld_i32, 1, TLADDR_ARGS, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) +DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) +DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) +DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) /* Host vector support. */ -#define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec) +#define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec) DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) DEF(dupi_vec, 1, 0, 1, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) diff --git a/include/tcg/tcg-runtime.h b/include/tcg/tcg-runtime.h index 1d759ac..f927e83 100644 --- a/include/tcg/tcg-runtime.h +++ b/include/tcg/tcg-runtime.h @@ -31,51 +31,32 @@ DEF_HELPER_FLAGS_1(exit_atomic, TCG_CALL_NO_WG, noreturn, env) #ifdef CONFIG_SOFTMMU -DEF_HELPER_FLAGS_5(atomic_cmpxchgb, TCG_CALL_NO_WG, - i32, env, tl, i32, i32, i32) -DEF_HELPER_FLAGS_5(atomic_cmpxchgw_be, TCG_CALL_NO_WG, - i32, env, tl, i32, i32, i32) -DEF_HELPER_FLAGS_5(atomic_cmpxchgw_le, TCG_CALL_NO_WG, - i32, env, tl, i32, i32, i32) -DEF_HELPER_FLAGS_5(atomic_cmpxchgl_be, TCG_CALL_NO_WG, - i32, env, tl, i32, i32, i32) -DEF_HELPER_FLAGS_5(atomic_cmpxchgl_le, TCG_CALL_NO_WG, - i32, env, tl, i32, i32, i32) +DEF_HELPER_FLAGS_5(atomic_cmpxchgb, TCG_CALL_NO_WG, i32, env, tl, i32, i32, i32) +DEF_HELPER_FLAGS_5(atomic_cmpxchgw_be, TCG_CALL_NO_WG, i32, env, tl, i32, i32, i32) +DEF_HELPER_FLAGS_5(atomic_cmpxchgw_le, TCG_CALL_NO_WG, i32, env, tl, i32, i32, i32) +DEF_HELPER_FLAGS_5(atomic_cmpxchgl_be, TCG_CALL_NO_WG, i32, env, tl, i32, i32, i32) +DEF_HELPER_FLAGS_5(atomic_cmpxchgl_le, TCG_CALL_NO_WG, i32, env, tl, i32, i32, i32) #ifdef CONFIG_ATOMIC64 -DEF_HELPER_FLAGS_5(atomic_cmpxchgq_be, TCG_CALL_NO_WG, - i64, env, tl, i64, i64, i32) -DEF_HELPER_FLAGS_5(atomic_cmpxchgq_le, TCG_CALL_NO_WG, - i64, env, tl, i64, i64, i32) +DEF_HELPER_FLAGS_5(atomic_cmpxchgq_be, TCG_CALL_NO_WG, i64, env, tl, i64, i64, i32) +DEF_HELPER_FLAGS_5(atomic_cmpxchgq_le, TCG_CALL_NO_WG, i64, env, tl, i64, i64, i32) #endif #ifdef CONFIG_ATOMIC64 -#define GEN_ATOMIC_HELPERS(NAME) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), b), \ - TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_le), \ - TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_be), \ - TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_le), \ - TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_be), \ - TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), q_le), \ - TCG_CALL_NO_WG, i64, env, tl, i64, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), q_be), \ - TCG_CALL_NO_WG, i64, env, tl, i64, i32) +#define GEN_ATOMIC_HELPERS(NAME) \ + DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), b), TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ + DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_le), TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ + DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_be), TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ + DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_le), TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ + DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_be), TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ + DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), q_le), TCG_CALL_NO_WG, i64, env, tl, i64, i32) \ + DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), q_be), TCG_CALL_NO_WG, i64, env, tl, i64, i32) #else -#define GEN_ATOMIC_HELPERS(NAME) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), b), \ - TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_le), \ - TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_be), \ - TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_le), \ - TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_be), \ - TCG_CALL_NO_WG, i32, env, tl, i32, i32) +#define GEN_ATOMIC_HELPERS(NAME) \ + DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), b), TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ + DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_le), TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ + DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_be), TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ + DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_le), TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ + DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_be), TCG_CALL_NO_WG, i32, env, tl, i32, i32) #endif /* CONFIG_ATOMIC64 */ #else @@ -91,33 +72,21 @@ DEF_HELPER_FLAGS_4(atomic_cmpxchgq_le, TCG_CALL_NO_WG, i64, env, tl, i64, i64) #endif #ifdef CONFIG_ATOMIC64 -#define GEN_ATOMIC_HELPERS(NAME) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), b), \ - TCG_CALL_NO_WG, i32, env, tl, i32) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), w_le), \ - TCG_CALL_NO_WG, i32, env, tl, i32) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), w_be), \ - TCG_CALL_NO_WG, i32, env, tl, i32) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), l_le), \ - TCG_CALL_NO_WG, i32, env, tl, i32) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), l_be), \ - TCG_CALL_NO_WG, i32, env, tl, i32) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), q_le), \ - TCG_CALL_NO_WG, i64, env, tl, i64) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), q_be), \ - TCG_CALL_NO_WG, i64, env, tl, i64) +#define GEN_ATOMIC_HELPERS(NAME) \ + DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), b), TCG_CALL_NO_WG, i32, env, tl, i32) \ + DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), w_le), TCG_CALL_NO_WG, i32, env, tl, i32) \ + DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), w_be), TCG_CALL_NO_WG, i32, env, tl, i32) \ + DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), l_le), TCG_CALL_NO_WG, i32, env, tl, i32) \ + DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), l_be), TCG_CALL_NO_WG, i32, env, tl, i32) \ + DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), q_le), TCG_CALL_NO_WG, i64, env, tl, i64) \ + DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), q_be), TCG_CALL_NO_WG, i64, env, tl, i64) #else -#define GEN_ATOMIC_HELPERS(NAME) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), b), \ - TCG_CALL_NO_WG, i32, env, tl, i32) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), w_le), \ - TCG_CALL_NO_WG, i32, env, tl, i32) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), w_be), \ - TCG_CALL_NO_WG, i32, env, tl, i32) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), l_le), \ - TCG_CALL_NO_WG, i32, env, tl, i32) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), l_be), \ - TCG_CALL_NO_WG, i32, env, tl, i32) +#define GEN_ATOMIC_HELPERS(NAME) \ + DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), b), TCG_CALL_NO_WG, i32, env, tl, i32) \ + DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), w_le), TCG_CALL_NO_WG, i32, env, tl, i32) \ + DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), w_be), TCG_CALL_NO_WG, i32, env, tl, i32) \ + DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), l_le), TCG_CALL_NO_WG, i32, env, tl, i32) \ + DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), l_be), TCG_CALL_NO_WG, i32, env, tl, i32) #endif /* CONFIG_ATOMIC64 */ #endif /* CONFIG_SOFTMMU */ diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index ec76c84..b873b58 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -25,15 +25,15 @@ #ifndef TCG_H #define TCG_H +#include #include #include -#include #include #include #include -#include #include +#include #include "tcg-mo.h" // #include "qemu/int128.h" @@ -53,7 +53,7 @@ #define CPU_TLB_BITS 10 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) -#define QEMU_NORETURN __attribute__ ((__noreturn__)) +#define QEMU_NORETURN __attribute__((__noreturn__)) // XXX: these come from types.h #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) @@ -87,7 +87,7 @@ typedef uint64_t target_ulong __attribute__((aligned(TARGET_LONG_ALIGNMENT))); typedef struct tcg_settings_t { target_ulong tlb_flags_mask; // Set to TLB_FALGS_MASK on initialization - uintptr_t tlb_mask_offset; //offsetof(CPUArchState, tlb_mask) + uintptr_t tlb_mask_offset; // offsetof(CPUArchState, tlb_mask) uintptr_t tlb_entry_addend_offset; // offsetof(CPUTLBEntry, addend) target_ulong tlb_entry_addr_read_offset; @@ -123,7 +123,6 @@ static inline size_t get_cpu_arch_tlb_mask_offset(int mem_index) { return g_tcg_settings.tlb_mask_offset + mem_index * sizeof(uintptr_t); } - /* XXX: make safe guess about sizes */ #define MAX_OP_PER_INSTR 266 @@ -145,13 +144,13 @@ static inline size_t get_cpu_arch_tlb_mask_offset(int mem_index) { /* Default target word size to pointer size. */ #ifndef TCG_TARGET_REG_BITS -# if UINTPTR_MAX == UINT32_MAX -# define TCG_TARGET_REG_BITS 32 -# elif UINTPTR_MAX == UINT64_MAX -# define TCG_TARGET_REG_BITS 64 -# else -# error Unknown pointer size for tcg target -# endif +#if UINTPTR_MAX == UINT32_MAX +#define TCG_TARGET_REG_BITS 32 +#elif UINTPTR_MAX == UINT64_MAX +#define TCG_TARGET_REG_BITS 64 +#else +#error Unknown pointer size for tcg target +#endif #endif #if TCG_TARGET_REG_BITS == 32 @@ -168,8 +167,6 @@ typedef uint64_t tcg_target_ulong; #error unsupported #endif - - /* Oversized TCG guests make things like MTTCG hard * as we can't use atomics for cputlb updates. */ @@ -189,44 +186,44 @@ typedef uint64_t TCGRegSet; #if TCG_TARGET_REG_BITS == 32 /* Turn some undef macros into false macros. */ -#define TCG_TARGET_HAS_extrl_i64_i32 0 -#define TCG_TARGET_HAS_extrh_i64_i32 0 -#define TCG_TARGET_HAS_div_i64 0 -#define TCG_TARGET_HAS_rem_i64 0 -#define TCG_TARGET_HAS_div2_i64 0 -#define TCG_TARGET_HAS_rot_i64 0 -#define TCG_TARGET_HAS_ext8s_i64 0 -#define TCG_TARGET_HAS_ext16s_i64 0 -#define TCG_TARGET_HAS_ext32s_i64 0 -#define TCG_TARGET_HAS_ext8u_i64 0 -#define TCG_TARGET_HAS_ext16u_i64 0 -#define TCG_TARGET_HAS_ext32u_i64 0 -#define TCG_TARGET_HAS_bswap16_i64 0 -#define TCG_TARGET_HAS_bswap32_i64 0 -#define TCG_TARGET_HAS_bswap64_i64 0 -#define TCG_TARGET_HAS_neg_i64 0 -#define TCG_TARGET_HAS_not_i64 0 -#define TCG_TARGET_HAS_andc_i64 0 -#define TCG_TARGET_HAS_orc_i64 0 -#define TCG_TARGET_HAS_eqv_i64 0 -#define TCG_TARGET_HAS_nand_i64 0 -#define TCG_TARGET_HAS_nor_i64 0 -#define TCG_TARGET_HAS_clz_i64 0 -#define TCG_TARGET_HAS_ctz_i64 0 -#define TCG_TARGET_HAS_ctpop_i64 0 -#define TCG_TARGET_HAS_deposit_i64 0 -#define TCG_TARGET_HAS_extract_i64 0 -#define TCG_TARGET_HAS_sextract_i64 0 -#define TCG_TARGET_HAS_movcond_i64 0 -#define TCG_TARGET_HAS_add2_i64 0 -#define TCG_TARGET_HAS_sub2_i64 0 -#define TCG_TARGET_HAS_mulu2_i64 0 -#define TCG_TARGET_HAS_muls2_i64 0 -#define TCG_TARGET_HAS_muluh_i64 0 -#define TCG_TARGET_HAS_mulsh_i64 0 +#define TCG_TARGET_HAS_extrl_i64_i32 0 +#define TCG_TARGET_HAS_extrh_i64_i32 0 +#define TCG_TARGET_HAS_div_i64 0 +#define TCG_TARGET_HAS_rem_i64 0 +#define TCG_TARGET_HAS_div2_i64 0 +#define TCG_TARGET_HAS_rot_i64 0 +#define TCG_TARGET_HAS_ext8s_i64 0 +#define TCG_TARGET_HAS_ext16s_i64 0 +#define TCG_TARGET_HAS_ext32s_i64 0 +#define TCG_TARGET_HAS_ext8u_i64 0 +#define TCG_TARGET_HAS_ext16u_i64 0 +#define TCG_TARGET_HAS_ext32u_i64 0 +#define TCG_TARGET_HAS_bswap16_i64 0 +#define TCG_TARGET_HAS_bswap32_i64 0 +#define TCG_TARGET_HAS_bswap64_i64 0 +#define TCG_TARGET_HAS_neg_i64 0 +#define TCG_TARGET_HAS_not_i64 0 +#define TCG_TARGET_HAS_andc_i64 0 +#define TCG_TARGET_HAS_orc_i64 0 +#define TCG_TARGET_HAS_eqv_i64 0 +#define TCG_TARGET_HAS_nand_i64 0 +#define TCG_TARGET_HAS_nor_i64 0 +#define TCG_TARGET_HAS_clz_i64 0 +#define TCG_TARGET_HAS_ctz_i64 0 +#define TCG_TARGET_HAS_ctpop_i64 0 +#define TCG_TARGET_HAS_deposit_i64 0 +#define TCG_TARGET_HAS_extract_i64 0 +#define TCG_TARGET_HAS_sextract_i64 0 +#define TCG_TARGET_HAS_movcond_i64 0 +#define TCG_TARGET_HAS_add2_i64 0 +#define TCG_TARGET_HAS_sub2_i64 0 +#define TCG_TARGET_HAS_mulu2_i64 0 +#define TCG_TARGET_HAS_muls2_i64 0 +#define TCG_TARGET_HAS_muluh_i64 0 +#define TCG_TARGET_HAS_mulsh_i64 0 /* Turn some undef macros into true macros. */ -#define TCG_TARGET_HAS_add2_i32 1 -#define TCG_TARGET_HAS_sub2_i32 1 +#define TCG_TARGET_HAS_add2_i32 1 +#define TCG_TARGET_HAS_sub2_i32 1 #endif #ifndef TCG_TARGET_deposit_i32_valid @@ -244,71 +241,67 @@ typedef uint64_t TCGRegSet; /* Only one of DIV or DIV2 should be defined. */ #if defined(TCG_TARGET_HAS_div_i32) -#define TCG_TARGET_HAS_div2_i32 0 +#define TCG_TARGET_HAS_div2_i32 0 #elif defined(TCG_TARGET_HAS_div2_i32) -#define TCG_TARGET_HAS_div_i32 0 -#define TCG_TARGET_HAS_rem_i32 0 +#define TCG_TARGET_HAS_div_i32 0 +#define TCG_TARGET_HAS_rem_i32 0 #endif #if defined(TCG_TARGET_HAS_div_i64) -#define TCG_TARGET_HAS_div2_i64 0 +#define TCG_TARGET_HAS_div2_i64 0 #elif defined(TCG_TARGET_HAS_div2_i64) -#define TCG_TARGET_HAS_div_i64 0 -#define TCG_TARGET_HAS_rem_i64 0 +#define TCG_TARGET_HAS_div_i64 0 +#define TCG_TARGET_HAS_rem_i64 0 #endif /* For 32-bit targets, some sort of unsigned widening multiply is required. */ -#if TCG_TARGET_REG_BITS == 32 \ - && !(defined(TCG_TARGET_HAS_mulu2_i32) \ - || defined(TCG_TARGET_HAS_muluh_i32)) -# error "Missing unsigned widening multiply" +#if TCG_TARGET_REG_BITS == 32 && !(defined(TCG_TARGET_HAS_mulu2_i32) || defined(TCG_TARGET_HAS_muluh_i32)) +#error "Missing unsigned widening multiply" #endif -#if !defined(TCG_TARGET_HAS_v64) \ - && !defined(TCG_TARGET_HAS_v128) \ - && !defined(TCG_TARGET_HAS_v256) -#define TCG_TARGET_MAYBE_vec 0 -#define TCG_TARGET_HAS_neg_vec 0 -#define TCG_TARGET_HAS_not_vec 0 -#define TCG_TARGET_HAS_andc_vec 0 -#define TCG_TARGET_HAS_orc_vec 0 -#define TCG_TARGET_HAS_shi_vec 0 -#define TCG_TARGET_HAS_shs_vec 0 -#define TCG_TARGET_HAS_shv_vec 0 -#define TCG_TARGET_HAS_mul_vec 0 -#define TCG_TARGET_HAS_sat_vec 0 -#define TCG_TARGET_HAS_minmax_vec 0 +#if !defined(TCG_TARGET_HAS_v64) && !defined(TCG_TARGET_HAS_v128) && !defined(TCG_TARGET_HAS_v256) +#define TCG_TARGET_MAYBE_vec 0 +#define TCG_TARGET_HAS_neg_vec 0 +#define TCG_TARGET_HAS_not_vec 0 +#define TCG_TARGET_HAS_andc_vec 0 +#define TCG_TARGET_HAS_orc_vec 0 +#define TCG_TARGET_HAS_shi_vec 0 +#define TCG_TARGET_HAS_shs_vec 0 +#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_mul_vec 0 +#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_minmax_vec 0 #else -#define TCG_TARGET_MAYBE_vec 1 +#define TCG_TARGET_MAYBE_vec 1 #endif #ifndef TCG_TARGET_HAS_v64 -#define TCG_TARGET_HAS_v64 0 +#define TCG_TARGET_HAS_v64 0 #endif #ifndef TCG_TARGET_HAS_v128 -#define TCG_TARGET_HAS_v128 0 +#define TCG_TARGET_HAS_v128 0 #endif #ifndef TCG_TARGET_HAS_v256 -#define TCG_TARGET_HAS_v256 0 +#define TCG_TARGET_HAS_v256 0 #endif #ifndef TARGET_INSN_START_EXTRA_WORDS #error Must define TARGET_INSN_START_EXTRA_WORDS #else -# define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) +#define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) #endif typedef enum TCGOpcode { -#define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, +#define DEF(name, oargs, iargs, cargs, flags) INDEX_op_##name, #include "tcg-opc.h" #undef DEF NB_OPS, } TCGOpcode; -#define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) -#define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r))) -#define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) +#define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet) 1 << (r)) +#define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet) 1 << (r))) +#define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) #ifndef TCG_TARGET_INSN_UNIT_SIZE -# error "Missing TCG_TARGET_INSN_UNIT_SIZE" +#error "Missing TCG_TARGET_INSN_UNIT_SIZE" #elif TCG_TARGET_INSN_UNIT_SIZE == 1 typedef uint8_t tcg_insn_unit; #elif TCG_TARGET_INSN_UNIT_SIZE == 2 @@ -321,12 +314,18 @@ typedef uint64_t tcg_insn_unit; /* The port better have done this. */ #endif - #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS -# define tcg_debug_assert(X) do { assert(X); } while (0) +#define tcg_debug_assert(X) \ + do { \ + assert(X); \ + } while (0) #else -# define tcg_debug_assert(X) \ - do { if (!(X)) { __builtin_unreachable(); } } while (0) +#define tcg_debug_assert(X) \ + do { \ + if (!(X)) { \ + __builtin_unreachable(); \ + } \ + } while (0) #endif typedef struct TCGRelocation { @@ -334,7 +333,7 @@ typedef struct TCGRelocation { int type; tcg_insn_unit *ptr; intptr_t addend; -} TCGRelocation; +} TCGRelocation; typedef struct TCGLabel TCGLabel; struct TCGLabel { @@ -355,7 +354,7 @@ struct TCGLabel { typedef struct TCGPool { struct TCGPool *next; int size; - uint8_t data[0] __attribute__ ((aligned)); + uint8_t data[0] __attribute__((aligned)); } TCGPool; #define TCG_POOL_CHUNK_SIZE 32768 @@ -377,21 +376,21 @@ typedef enum TCGType { TCG_TYPE_COUNT, /* number of different types */ - /* An alias for the size of the host register. */ +/* An alias for the size of the host register. */ #if TCG_TARGET_REG_BITS == 32 TCG_TYPE_REG = TCG_TYPE_I32, #else TCG_TYPE_REG = TCG_TYPE_I64, #endif - /* An alias for the size of the native pointer. */ +/* An alias for the size of the native pointer. */ #if UINTPTR_MAX == UINT32_MAX TCG_TYPE_PTR = TCG_TYPE_I32, #else TCG_TYPE_PTR = TCG_TYPE_I64, #endif - /* An alias for the size of the target "long", aka register. */ +/* An alias for the size of the target "long", aka register. */ #if TARGET_LONG_BITS == 64 TCG_TYPE_TL = TCG_TYPE_I64, #else @@ -401,26 +400,26 @@ typedef enum TCGType { /* Constants for qemu_ld and qemu_st for the Memory Operation field. */ typedef enum TCGMemOp { - MO_8 = 0, - MO_16 = 1, - MO_32 = 2, - MO_64 = 3, - MO_SIZE = 3, /* Mask for the above. */ + MO_8 = 0, + MO_16 = 1, + MO_32 = 2, + MO_64 = 3, + MO_SIZE = 3, /* Mask for the above. */ - MO_SIGN = 4, /* Sign-extended, otherwise zero-extended. */ + MO_SIGN = 4, /* Sign-extended, otherwise zero-extended. */ - MO_BSWAP = 8, /* Host reverse endian. */ + MO_BSWAP = 8, /* Host reverse endian. */ #ifdef HOST_WORDS_BIGENDIAN - MO_LE = MO_BSWAP, - MO_BE = 0, + MO_LE = MO_BSWAP, + MO_BE = 0, #else - MO_LE = 0, - MO_BE = MO_BSWAP, + MO_LE = 0, + MO_BE = MO_BSWAP, #endif #ifdef TARGET_WORDS_BIGENDIAN - MO_TE = MO_BE, + MO_TE = MO_BE, #else - MO_TE = MO_LE, + MO_TE = MO_LE, #endif /* MO_UNALN accesses are never checked for alignment. @@ -450,39 +449,39 @@ typedef enum TCGMemOp { MO_ALIGN = MO_AMASK, MO_UNALN = 0, #endif - MO_ALIGN_2 = 1 << MO_ASHIFT, - MO_ALIGN_4 = 2 << MO_ASHIFT, - MO_ALIGN_8 = 3 << MO_ASHIFT, + MO_ALIGN_2 = 1 << MO_ASHIFT, + MO_ALIGN_4 = 2 << MO_ASHIFT, + MO_ALIGN_8 = 3 << MO_ASHIFT, MO_ALIGN_16 = 4 << MO_ASHIFT, MO_ALIGN_32 = 5 << MO_ASHIFT, MO_ALIGN_64 = 6 << MO_ASHIFT, /* Combinations of the above, for ease of use. */ - MO_UB = MO_8, - MO_UW = MO_16, - MO_UL = MO_32, - MO_SB = MO_SIGN | MO_8, - MO_SW = MO_SIGN | MO_16, - MO_SL = MO_SIGN | MO_32, - MO_Q = MO_64, - - MO_LEUW = MO_LE | MO_UW, - MO_LEUL = MO_LE | MO_UL, - MO_LESW = MO_LE | MO_SW, - MO_LESL = MO_LE | MO_SL, - MO_LEQ = MO_LE | MO_Q, - - MO_BEUW = MO_BE | MO_UW, - MO_BEUL = MO_BE | MO_UL, - MO_BESW = MO_BE | MO_SW, - MO_BESL = MO_BE | MO_SL, - MO_BEQ = MO_BE | MO_Q, - - MO_TEUW = MO_TE | MO_UW, - MO_TEUL = MO_TE | MO_UL, - MO_TESW = MO_TE | MO_SW, - MO_TESL = MO_TE | MO_SL, - MO_TEQ = MO_TE | MO_Q, + MO_UB = MO_8, + MO_UW = MO_16, + MO_UL = MO_32, + MO_SB = MO_SIGN | MO_8, + MO_SW = MO_SIGN | MO_16, + MO_SL = MO_SIGN | MO_32, + MO_Q = MO_64, + + MO_LEUW = MO_LE | MO_UW, + MO_LEUL = MO_LE | MO_UL, + MO_LESW = MO_LE | MO_SW, + MO_LESL = MO_LE | MO_SL, + MO_LEQ = MO_LE | MO_Q, + + MO_BEUW = MO_BE | MO_UW, + MO_BEUL = MO_BE | MO_UL, + MO_BESW = MO_BE | MO_SW, + MO_BESL = MO_BE | MO_SL, + MO_BEQ = MO_BE | MO_Q, + + MO_TEUW = MO_TE | MO_UW, + MO_TEUL = MO_TE | MO_UL, + MO_TESW = MO_TE | MO_SW, + MO_TESL = MO_TE | MO_SL, + MO_TEQ = MO_TE | MO_Q, MO_SSIZE = MO_SIZE | MO_SIGN, } TCGMemOp; @@ -493,8 +492,7 @@ typedef enum TCGMemOp { * * Extract the alignment size from the memop. */ -static inline unsigned get_alignment_bits(TCGMemOp memop) -{ +static inline unsigned get_alignment_bits(TCGMemOp memop) { unsigned a = memop & MO_AMASK; if (a == MO_UNALN) { @@ -562,23 +560,23 @@ typedef TCGv_ptr TCGv_env; /* call flags */ /* Helper does not read globals (either directly or through an exception). It implies TCG_CALL_NO_WRITE_GLOBALS. */ -#define TCG_CALL_NO_READ_GLOBALS 0x0001 +#define TCG_CALL_NO_READ_GLOBALS 0x0001 /* Helper does not write globals */ -#define TCG_CALL_NO_WRITE_GLOBALS 0x0002 +#define TCG_CALL_NO_WRITE_GLOBALS 0x0002 /* Helper can be safely suppressed if the return value is not used. */ -#define TCG_CALL_NO_SIDE_EFFECTS 0x0004 +#define TCG_CALL_NO_SIDE_EFFECTS 0x0004 /* Helper is QEMU_NORETURN. */ -#define TCG_CALL_NO_RETURN 0x0008 +#define TCG_CALL_NO_RETURN 0x0008 /* convenience version of most used call flags */ -#define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS -#define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS -#define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS -#define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) -#define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) +#define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS +#define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS +#define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS +#define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) +#define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) /* Used to align parameters. See the comment before tcgv_i32_temp. */ -#define TCG_CALL_DUMMY_ARG ((TCGArg)0) +#define TCG_CALL_DUMMY_ARG ((TCGArg) 0) /* Conditions. Note that these are laid out for easy manipulation by the functions below: @@ -588,64 +586,58 @@ typedef TCGv_ptr TCGv_env; bit 3 is used with bit 0 for swapping signed/unsigned. */ typedef enum { /* non-signed */ - TCG_COND_NEVER = 0 | 0 | 0 | 0, + TCG_COND_NEVER = 0 | 0 | 0 | 0, TCG_COND_ALWAYS = 0 | 0 | 0 | 1, - TCG_COND_EQ = 8 | 0 | 0 | 0, - TCG_COND_NE = 8 | 0 | 0 | 1, + TCG_COND_EQ = 8 | 0 | 0 | 0, + TCG_COND_NE = 8 | 0 | 0 | 1, /* signed */ - TCG_COND_LT = 0 | 0 | 2 | 0, - TCG_COND_GE = 0 | 0 | 2 | 1, - TCG_COND_LE = 8 | 0 | 2 | 0, - TCG_COND_GT = 8 | 0 | 2 | 1, + TCG_COND_LT = 0 | 0 | 2 | 0, + TCG_COND_GE = 0 | 0 | 2 | 1, + TCG_COND_LE = 8 | 0 | 2 | 0, + TCG_COND_GT = 8 | 0 | 2 | 1, /* unsigned */ - TCG_COND_LTU = 0 | 4 | 0 | 0, - TCG_COND_GEU = 0 | 4 | 0 | 1, - TCG_COND_LEU = 8 | 4 | 0 | 0, - TCG_COND_GTU = 8 | 4 | 0 | 1, + TCG_COND_LTU = 0 | 4 | 0 | 0, + TCG_COND_GEU = 0 | 4 | 0 | 1, + TCG_COND_LEU = 8 | 4 | 0 | 0, + TCG_COND_GTU = 8 | 4 | 0 | 1, } TCGCond; /* Invert the sense of the comparison. */ -static inline TCGCond tcg_invert_cond(TCGCond c) -{ +static inline TCGCond tcg_invert_cond(TCGCond c) { return (TCGCond)(c ^ 1); } /* Swap the operands in a comparison. */ -static inline TCGCond tcg_swap_cond(TCGCond c) -{ +static inline TCGCond tcg_swap_cond(TCGCond c) { return c & 6 ? (TCGCond)(c ^ 9) : c; } /* Create an "unsigned" version of a "signed" comparison. */ -static inline TCGCond tcg_unsigned_cond(TCGCond c) -{ +static inline TCGCond tcg_unsigned_cond(TCGCond c) { return c & 2 ? (TCGCond)(c ^ 6) : c; } /* Create a "signed" version of an "unsigned" comparison. */ -static inline TCGCond tcg_signed_cond(TCGCond c) -{ +static inline TCGCond tcg_signed_cond(TCGCond c) { return c & 4 ? (TCGCond)(c ^ 6) : c; } /* Must a comparison be considered unsigned? */ -static inline bool is_unsigned_cond(TCGCond c) -{ +static inline bool is_unsigned_cond(TCGCond c) { return (c & 4) != 0; } /* Create a "high" version of a double-word comparison. This removes equality from a LTE or GTE comparison. */ -static inline TCGCond tcg_high_cond(TCGCond c) -{ +static inline TCGCond tcg_high_cond(TCGCond c) { switch (c) { - case TCG_COND_GE: - case TCG_COND_LE: - case TCG_COND_GEU: - case TCG_COND_LEU: - return (TCGCond)(c ^ 8); - default: - return c; + case TCG_COND_GE: + case TCG_COND_LE: + case TCG_COND_GEU: + case TCG_COND_LEU: + return (TCGCond)(c ^ 8); + default: + return c; } } @@ -657,23 +649,23 @@ typedef enum TCGTempVal { } TCGTempVal; typedef struct TCGTemp { - TCGReg reg:8; - TCGTempVal val_type:8; - TCGType base_type:8; - TCGType type:8; - unsigned int fixed_reg:1; - unsigned int indirect_reg:1; - unsigned int indirect_base:1; - unsigned int mem_coherent:1; - unsigned int mem_allocated:1; + TCGReg reg : 8; + TCGTempVal val_type : 8; + TCGType base_type : 8; + TCGType type : 8; + unsigned int fixed_reg : 1; + unsigned int indirect_reg : 1; + unsigned int indirect_base : 1; + unsigned int mem_coherent : 1; + unsigned int mem_allocated : 1; /* If true, the temp is saved across both basic blocks and translation blocks. */ - unsigned int temp_global:1; + unsigned int temp_global : 1; /* If true, the temp is saved across basic blocks but dead at the end of translation blocks. If false, the temp is dead at the end of basic blocks. */ - unsigned int temp_local:1; - unsigned int temp_allocated:1; + unsigned int temp_local : 1; + unsigned int temp_allocated : 1; tcg_target_long val; struct TCGTemp *mem_base; @@ -689,29 +681,27 @@ typedef struct TCGTemp { typedef struct TCGContext TCGContext; -typedef struct TCGTempSet { - unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; -} TCGTempSet; +typedef struct TCGTempSet { unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; } TCGTempSet; /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding, this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands. There are never more than 2 outputs, which means that we can store all dead + sync data within 16 bits. */ -#define DEAD_ARG 4 -#define SYNC_ARG 1 +#define DEAD_ARG 4 +#define SYNC_ARG 1 typedef uint16_t TCGLifeData; /* The layout here is designed to avoid a bitfield crossing of a 32-bit boundary, which would cause GCC to add extra padding. */ typedef struct TCGOp { - TCGOpcode opc : 8; /* 8 */ + TCGOpcode opc : 8; /* 8 */ /* Parameters for this opcode. See below. */ - unsigned param1 : 4; /* 12 */ - unsigned param2 : 4; /* 16 */ + unsigned param1 : 4; /* 12 */ + unsigned param2 : 4; /* 16 */ /* Lifetime data of the operands. */ - unsigned life : 16; /* 32 */ + unsigned life : 16; /* 32 */ /* Next and previous opcodes. */ QTAILQ_ENTRY(TCGOp) link; @@ -723,11 +713,11 @@ typedef struct TCGOp { TCGRegSet output_pref[2]; } TCGOp; -#define TCGOP_CALLI(X) (X)->param1 -#define TCGOP_CALLO(X) (X)->param2 +#define TCGOP_CALLI(X) (X)->param1 +#define TCGOP_CALLO(X) (X)->param2 -#define TCGOP_VECL(X) (X)->param1 -#define TCGOP_VECE(X) (X)->param2 +#define TCGOP_VECL(X) (X)->param1 +#define TCGOP_VECE(X) (X)->param2 /* Make sure operands fit in the bitfields above. */ QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); @@ -806,9 +796,9 @@ struct TCGContext { size_t tb_phys_invalidate_count; /* Track which vCPU triggers events */ - CPUState *cpu; /* *_trans */ + CPUState *cpu; /* *_trans */ - /* These structures are private to tcg-target.inc.c. */ +/* These structures are private to tcg-target.inc.c. */ #ifdef TCG_TARGET_NEED_LDST_LABELS QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; #endif @@ -880,109 +870,90 @@ extern TCGContext tcg_init_ctx; extern __thread TCGContext *tcg_ctx; extern TCGv_env cpu_env; -static inline size_t temp_idx(TCGTemp *ts) -{ +static inline size_t temp_idx(TCGTemp *ts) { ptrdiff_t n = ts - tcg_ctx->temps; tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps); return n; } -static inline TCGArg temp_arg(TCGTemp *ts) -{ - return (uintptr_t)ts; +static inline TCGArg temp_arg(TCGTemp *ts) { + return (uintptr_t) ts; } -static inline TCGTemp *arg_temp(TCGArg a) -{ - return (TCGTemp *)(uintptr_t)a; +static inline TCGTemp *arg_temp(TCGArg a) { + return (TCGTemp *) (uintptr_t) a; } /* Using the offset of a temporary, relative to TCGContext, rather than its index means that we don't use 0. That leaves offset 0 free for a NULL representation without having to leave index 0 unused. */ -static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) -{ - uintptr_t o = (uintptr_t)v; - TCGTemp *t = (void *)tcg_ctx + o; +static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) { + uintptr_t o = (uintptr_t) v; + TCGTemp *t = (void *) tcg_ctx + o; tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o); return t; } -static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) -{ - return tcgv_i32_temp((TCGv_i32)v); +static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) { + return tcgv_i32_temp((TCGv_i32) v); } -static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) -{ - return tcgv_i32_temp((TCGv_i32)v); +static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) { + return tcgv_i32_temp((TCGv_i32) v); } -static inline TCGTemp *tcgv_vec_temp(TCGv_vec v) -{ - return tcgv_i32_temp((TCGv_i32)v); +static inline TCGTemp *tcgv_vec_temp(TCGv_vec v) { + return tcgv_i32_temp((TCGv_i32) v); } -static inline TCGArg tcgv_i32_arg(TCGv_i32 v) -{ +static inline TCGArg tcgv_i32_arg(TCGv_i32 v) { return temp_arg(tcgv_i32_temp(v)); } -static inline TCGArg tcgv_i64_arg(TCGv_i64 v) -{ +static inline TCGArg tcgv_i64_arg(TCGv_i64 v) { return temp_arg(tcgv_i64_temp(v)); } -static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) -{ +static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) { return temp_arg(tcgv_ptr_temp(v)); } -static inline TCGArg tcgv_vec_arg(TCGv_vec v) -{ +static inline TCGArg tcgv_vec_arg(TCGv_vec v) { return temp_arg(tcgv_vec_temp(v)); } -static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) -{ - (void)temp_idx(t); /* trigger embedded assert */ - return (TCGv_i32)((void *)t - (void *)tcg_ctx); +static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) { + (void) temp_idx(t); /* trigger embedded assert */ + return (TCGv_i32)((void *) t - (void *) tcg_ctx); } -static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) -{ - return (TCGv_i64)temp_tcgv_i32(t); +static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) { + return (TCGv_i64) temp_tcgv_i32(t); } -static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) -{ - return (TCGv_ptr)temp_tcgv_i32(t); +static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) { + return (TCGv_ptr) temp_tcgv_i32(t); } -static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) -{ - return (TCGv_vec)temp_tcgv_i32(t); +static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) { + return (TCGv_vec) temp_tcgv_i32(t); } #if TCG_TARGET_REG_BITS == 32 -static inline TCGv_i32 TCGV_LOW(TCGv_i64 t) -{ +static inline TCGv_i32 TCGV_LOW(TCGv_i64 t) { return temp_tcgv_i32(tcgv_i64_temp(t)); } -static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) -{ +static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) { return temp_tcgv_i32(tcgv_i64_temp(t) + 1); } #endif -static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) -{ +static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) { op->args[arg] = v; } -static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v) -{ +static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v) { #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS tcg_set_insn_param(op, arg, v); #else @@ -992,14 +963,12 @@ static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v) } /* The last op that was emitted. */ -static inline TCGOp *tcg_last_op(void) -{ +static inline TCGOp *tcg_last_op(void) { return QTAILQ_LAST(&tcg_ctx->ops); } /* Test for whether to terminate the TB for using too many opcodes. */ -static inline bool tcg_op_buf_full(void) -{ +static inline bool tcg_op_buf_full(void) { /* This is not a hard limit, it merely stops translation when * we have produced "enough" opcodes. We want to limit TB size * such that a RISC host can reasonably use a 16-bit signed @@ -1031,8 +1000,7 @@ void tcg_tb_foreach(GTraverseFunc func, gpointer user_data); size_t tcg_nb_tbs(void); /* user-mode: Called with mmap_lock held. */ -static inline void *tcg_malloc(int size) -{ +static inline void *tcg_malloc(int size) { TCGContext *s = tcg_ctx; uint8_t *ptr, *ptr_end; @@ -1058,86 +1026,69 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb); void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); -TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, - intptr_t, const char *); +TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, intptr_t, const char *); TCGTemp *tcg_temp_new_internal(TCGType, bool); void tcg_temp_free_internal(TCGTemp *); TCGv_vec tcg_temp_new_vec(TCGType type); TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); -static inline void tcg_temp_free_i32(TCGv_i32 arg) -{ +static inline void tcg_temp_free_i32(TCGv_i32 arg) { tcg_temp_free_internal(tcgv_i32_temp(arg)); } -static inline void tcg_temp_free_i64(TCGv_i64 arg) -{ +static inline void tcg_temp_free_i64(TCGv_i64 arg) { tcg_temp_free_internal(tcgv_i64_temp(arg)); } -static inline void tcg_temp_free_ptr(TCGv_ptr arg) -{ +static inline void tcg_temp_free_ptr(TCGv_ptr arg) { tcg_temp_free_internal(tcgv_ptr_temp(arg)); } -static inline void tcg_temp_free_vec(TCGv_vec arg) -{ +static inline void tcg_temp_free_vec(TCGv_vec arg) { tcg_temp_free_internal(tcgv_vec_temp(arg)); } -static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, - const char *name) -{ +static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, const char *name) { TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name); return temp_tcgv_i32(t); } -static inline TCGv_i32 tcg_temp_new_i32(void) -{ +static inline TCGv_i32 tcg_temp_new_i32(void) { TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false); return temp_tcgv_i32(t); } -static inline TCGv_i32 tcg_temp_local_new_i32(void) -{ +static inline TCGv_i32 tcg_temp_local_new_i32(void) { TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true); return temp_tcgv_i32(t); } -static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, - const char *name) -{ +static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, const char *name) { TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name); return temp_tcgv_i64(t); } -static inline TCGv_i64 tcg_temp_new_i64(void) -{ +static inline TCGv_i64 tcg_temp_new_i64(void) { TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false); return temp_tcgv_i64(t); } -static inline TCGv_i64 tcg_temp_local_new_i64(void) -{ +static inline TCGv_i64 tcg_temp_local_new_i64(void) { TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true); return temp_tcgv_i64(t); } -static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, - const char *name) -{ +static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, const char *name) { TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name); return temp_tcgv_ptr(t); } -static inline TCGv_ptr tcg_temp_new_ptr(void) -{ +static inline TCGv_ptr tcg_temp_new_ptr(void) { TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false); return temp_tcgv_ptr(t); } -static inline TCGv_ptr tcg_temp_local_new_ptr(void) -{ +static inline TCGv_ptr tcg_temp_local_new_ptr(void) { TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true); return temp_tcgv_ptr(t); } @@ -1151,7 +1102,9 @@ static inline TCGv_ptr tcg_temp_local_new_ptr(void) void tcg_clear_temp_count(void); int tcg_check_temp_count(void); #else -#define tcg_clear_temp_count() do { } while (0) +#define tcg_clear_temp_count() \ + do { \ + } while (0) #define tcg_check_temp_count() 0 #endif @@ -1159,11 +1112,11 @@ int64_t tcg_cpu_exec_time(void); void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf); void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf); -#define TCG_CT_ALIAS 0x80 +#define TCG_CT_ALIAS 0x80 #define TCG_CT_IALIAS 0x40 #define TCG_CT_NEWREG 0x20 /* output requires a new register */ -#define TCG_CT_REG 0x01 -#define TCG_CT_CONST 0x02 /* any constant of register size */ +#define TCG_CT_REG 0x01 +#define TCG_CT_CONST 0x02 /* any constant of register size */ typedef struct TCGArgConstraint { uint16_t ct; @@ -1178,21 +1131,21 @@ typedef struct TCGArgConstraint { /* Bits for TCGOpDef->flags, 8 bits available. */ enum { /* Instruction exits the translation block. */ - TCG_OPF_BB_EXIT = 0x01, + TCG_OPF_BB_EXIT = 0x01, /* Instruction defines the end of a basic block. */ - TCG_OPF_BB_END = 0x02, + TCG_OPF_BB_END = 0x02, /* Instruction clobbers call registers and potentially update globals. */ TCG_OPF_CALL_CLOBBER = 0x04, /* Instruction has side effects: it cannot be removed if its outputs are not used, and might trigger exceptions. */ TCG_OPF_SIDE_EFFECTS = 0x08, /* Instruction operands are 64-bits (otherwise 32-bits). */ - TCG_OPF_64BIT = 0x10, + TCG_OPF_64BIT = 0x10, /* Instruction is optional and not implemented by the host, or insn is generic and should not be implemened by the host. */ - TCG_OPF_NOT_PRESENT = 0x20, + TCG_OPF_NOT_PRESENT = 0x20, /* Instruction operands are vectors. */ - TCG_OPF_VECTOR = 0x40, + TCG_OPF_VECTOR = 0x40, }; typedef struct TCGOpDef { @@ -1214,11 +1167,11 @@ typedef struct TCGTargetOpDef { const char *args_ct_str[TCG_MAX_OP_ARGS]; } TCGTargetOpDef; -#define tcg_abort() \ -do {\ - fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\ - abort();\ -} while (0) +#define tcg_abort() \ + do { \ + fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__); \ + abort(); \ + } while (0) bool tcg_op_supported(TCGOpcode op); @@ -1241,11 +1194,11 @@ TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec); TCGv_vec tcg_const_ones_vec_matching(TCGv_vec); #if UINTPTR_MAX == UINT32_MAX -# define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x))) -# define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x))) +#define tcg_const_ptr(x) ((TCGv_ptr) tcg_const_i32((intptr_t)(x))) +#define tcg_const_local_ptr(x) ((TCGv_ptr) tcg_const_local_i32((intptr_t)(x))) #else -# define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x))) -# define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x))) +#define tcg_const_ptr(x) ((TCGv_ptr) tcg_const_i64((intptr_t)(x))) +#define tcg_const_local_ptr(x) ((TCGv_ptr) tcg_const_local_i64((intptr_t)(x))) #endif TCGLabel *gen_new_label(void); @@ -1257,9 +1210,8 @@ TCGLabel *gen_new_label(void); * Encode a label for storage in the TCG opcode stream. */ -static inline TCGArg label_arg(TCGLabel *l) -{ - return (uintptr_t)l; +static inline TCGArg label_arg(TCGLabel *l) { + return (uintptr_t) l; } /** @@ -1270,9 +1222,8 @@ static inline TCGArg label_arg(TCGLabel *l) * encoding of the TCG opcode stream. */ -static inline TCGLabel *arg_label(TCGArg i) -{ - return (TCGLabel *)(uintptr_t)i; +static inline TCGLabel *arg_label(TCGArg i) { + return (TCGLabel *) (uintptr_t) i; } /** @@ -1288,8 +1239,7 @@ static inline TCGLabel *arg_label(TCGArg i) * correct result. */ -static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b) -{ +static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b) { return a - b; } @@ -1302,8 +1252,7 @@ static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b) * to the destination address. */ -static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target) -{ +static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target) { return tcg_ptr_byte_diff(target, s->code_ptr); } @@ -1315,8 +1264,7 @@ static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target) * This is used to fill in qemu's data structures for goto_tb. */ -static inline size_t tcg_current_code_size(TCGContext *s) -{ +static inline size_t tcg_current_code_size(TCGContext *s) { return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); } @@ -1330,8 +1278,7 @@ typedef uint32_t TCGMemOpIdx; * * Encode these values into a single parameter. */ -static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx) -{ +static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx) { tcg_debug_assert(idx <= 15); return (op << 4) | idx; } @@ -1342,8 +1289,7 @@ static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx) * * Extract the memory operation from the combined value. */ -static inline TCGMemOp get_memop(TCGMemOpIdx oi) -{ +static inline TCGMemOp get_memop(TCGMemOpIdx oi) { return oi >> 4; } @@ -1353,8 +1299,7 @@ static inline TCGMemOp get_memop(TCGMemOpIdx oi) * * Extract the mmu index from the combined value. */ -static inline unsigned get_mmuidx(TCGMemOpIdx oi) -{ +static inline unsigned get_mmuidx(TCGMemOpIdx oi) { return oi & 15; } @@ -1403,17 +1348,16 @@ static inline unsigned get_mmuidx(TCGMemOpIdx oi) * to this default (which just calls the prologue.code emitted by * tcg_target_qemu_prologue()). */ -#define TB_EXIT_MASK 3 -#define TB_EXIT_IDX0 0 -#define TB_EXIT_IDX1 1 -#define TB_EXIT_IDXMAX 1 +#define TB_EXIT_MASK 3 +#define TB_EXIT_IDX0 0 +#define TB_EXIT_IDX1 1 +#define TB_EXIT_IDXMAX 1 #define TB_EXIT_REQUESTED 3 #ifdef HAVE_tcg_libcpu_tb_exec uintptr_t tcg_libcpu_tb_exec(CPUArchState *env, uint8_t *tb_ptr); #else -# define tcg_libcpu_tb_exec(env, tb_ptr) \ - ((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_ptr) +#define tcg_libcpu_tb_exec(env, tb_ptr) ((uintptr_t(*)(void *, void *)) tcg_ctx->code_gen_prologue)(env, tb_ptr) #endif void tcg_register_jit(void *buf, size_t buf_size); @@ -1424,8 +1368,7 @@ void tcg_register_jit(void *buf, size_t buf_size); return < 0 if we must call tcg_expand_vec_op. */ int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned); #else -static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) -{ +static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) { return 0; } #endif @@ -1436,148 +1379,113 @@ void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...); /* Replicate a constant C accoring to the log2 of the element size. */ uint64_t dup_const(unsigned vece, uint64_t c); -#define dup_const(VECE, C) \ - (__builtin_constant_p(VECE) \ - ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \ - : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \ - : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \ - : dup_const(VECE, C)) \ - : dup_const(VECE, C)) - +#define dup_const(VECE, C) \ + (__builtin_constant_p(VECE) \ + ? ((VECE) == MO_8 \ + ? 0x0101010101010101ull * (uint8_t)(C) \ + : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \ + : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) : dup_const(VECE, C)) \ + : dup_const(VECE, C)) /* * Memory helpers that will be used by TCG generated code. */ #ifdef CONFIG_SOFTMMU /* Value zero-extended to tcg register size. */ -tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); -uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); -uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); +uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); +uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); /* Value sign-extended to tcg register size. */ -tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); - -void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, - TCGMemOpIdx oi, uintptr_t retaddr); -void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - TCGMemOpIdx oi, uintptr_t retaddr); -void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - TCGMemOpIdx oi, uintptr_t retaddr); -void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - TCGMemOpIdx oi, uintptr_t retaddr); -void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - TCGMemOpIdx oi, uintptr_t retaddr); -void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - TCGMemOpIdx oi, uintptr_t retaddr); -void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - TCGMemOpIdx oi, uintptr_t retaddr); - -uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); -uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); -uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); -uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); -uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); -uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); -uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); + +void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, TCGMemOpIdx oi, uintptr_t retaddr); +void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, TCGMemOpIdx oi, uintptr_t retaddr); +void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, TCGMemOpIdx oi, uintptr_t retaddr); +void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, TCGMemOpIdx oi, uintptr_t retaddr); +void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, TCGMemOpIdx oi, uintptr_t retaddr); +void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, TCGMemOpIdx oi, uintptr_t retaddr); +void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, TCGMemOpIdx oi, uintptr_t retaddr); + +uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); +uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); +uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); +uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); +uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); +uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); +uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); /* Temporary aliases until backends are converted. */ #ifdef TARGET_WORDS_BIGENDIAN -# define helper_ret_ldsw_mmu helper_be_ldsw_mmu -# define helper_ret_lduw_mmu helper_be_lduw_mmu -# define helper_ret_ldsl_mmu helper_be_ldsl_mmu -# define helper_ret_ldul_mmu helper_be_ldul_mmu -# define helper_ret_ldl_mmu helper_be_ldul_mmu -# define helper_ret_ldq_mmu helper_be_ldq_mmu -# define helper_ret_stw_mmu helper_be_stw_mmu -# define helper_ret_stl_mmu helper_be_stl_mmu -# define helper_ret_stq_mmu helper_be_stq_mmu -# define helper_ret_ldw_cmmu helper_be_ldw_cmmu -# define helper_ret_ldl_cmmu helper_be_ldl_cmmu -# define helper_ret_ldq_cmmu helper_be_ldq_cmmu +#define helper_ret_ldsw_mmu helper_be_ldsw_mmu +#define helper_ret_lduw_mmu helper_be_lduw_mmu +#define helper_ret_ldsl_mmu helper_be_ldsl_mmu +#define helper_ret_ldul_mmu helper_be_ldul_mmu +#define helper_ret_ldl_mmu helper_be_ldul_mmu +#define helper_ret_ldq_mmu helper_be_ldq_mmu +#define helper_ret_stw_mmu helper_be_stw_mmu +#define helper_ret_stl_mmu helper_be_stl_mmu +#define helper_ret_stq_mmu helper_be_stq_mmu +#define helper_ret_ldw_cmmu helper_be_ldw_cmmu +#define helper_ret_ldl_cmmu helper_be_ldl_cmmu +#define helper_ret_ldq_cmmu helper_be_ldq_cmmu #else -# define helper_ret_ldsw_mmu helper_le_ldsw_mmu -# define helper_ret_lduw_mmu helper_le_lduw_mmu -# define helper_ret_ldsl_mmu helper_le_ldsl_mmu -# define helper_ret_ldul_mmu helper_le_ldul_mmu -# define helper_ret_ldl_mmu helper_le_ldul_mmu -# define helper_ret_ldq_mmu helper_le_ldq_mmu -# define helper_ret_stw_mmu helper_le_stw_mmu -# define helper_ret_stl_mmu helper_le_stl_mmu -# define helper_ret_stq_mmu helper_le_stq_mmu -# define helper_ret_ldw_cmmu helper_le_ldw_cmmu -# define helper_ret_ldl_cmmu helper_le_ldl_cmmu -# define helper_ret_ldq_cmmu helper_le_ldq_cmmu +#define helper_ret_ldsw_mmu helper_le_ldsw_mmu +#define helper_ret_lduw_mmu helper_le_lduw_mmu +#define helper_ret_ldsl_mmu helper_le_ldsl_mmu +#define helper_ret_ldul_mmu helper_le_ldul_mmu +#define helper_ret_ldl_mmu helper_le_ldul_mmu +#define helper_ret_ldq_mmu helper_le_ldq_mmu +#define helper_ret_stw_mmu helper_le_stw_mmu +#define helper_ret_stl_mmu helper_le_stl_mmu +#define helper_ret_stq_mmu helper_le_stq_mmu +#define helper_ret_ldw_cmmu helper_le_ldw_cmmu +#define helper_ret_ldl_cmmu helper_le_ldl_cmmu +#define helper_ret_ldq_cmmu helper_le_ldq_cmmu #endif -uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, - uint32_t cmpv, uint32_t newv, - TCGMemOpIdx oi, uintptr_t retaddr); -uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr, - uint32_t cmpv, uint32_t newv, +uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, uint32_t cmpv, uint32_t newv, TCGMemOpIdx oi, + uintptr_t retaddr); +uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr, uint32_t cmpv, uint32_t newv, TCGMemOpIdx oi, uintptr_t retaddr); -uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr, - uint32_t cmpv, uint32_t newv, +uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr, uint32_t cmpv, uint32_t newv, TCGMemOpIdx oi, uintptr_t retaddr); -uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr, - uint64_t cmpv, uint64_t newv, +uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr, uint64_t cmpv, uint64_t newv, TCGMemOpIdx oi, uintptr_t retaddr); -uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr, - uint32_t cmpv, uint32_t newv, +uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr, uint32_t cmpv, uint32_t newv, TCGMemOpIdx oi, uintptr_t retaddr); -uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr, - uint32_t cmpv, uint32_t newv, +uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr, uint32_t cmpv, uint32_t newv, TCGMemOpIdx oi, uintptr_t retaddr); -uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr, - uint64_t cmpv, uint64_t newv, +uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr, uint64_t cmpv, uint64_t newv, TCGMemOpIdx oi, uintptr_t retaddr); -#define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \ -TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu \ - (CPUArchState *env, target_ulong addr, TYPE val, \ - TCGMemOpIdx oi, uintptr_t retaddr); +#define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \ + TYPE helper_atomic_##NAME##SUFFIX##_mmu(CPUArchState *env, target_ulong addr, TYPE val, TCGMemOpIdx oi, \ + uintptr_t retaddr); #ifdef CONFIG_ATOMIC64 -#define GEN_ATOMIC_HELPER_ALL(NAME) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \ - GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \ +#define GEN_ATOMIC_HELPER_ALL(NAME) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \ + GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \ GEN_ATOMIC_HELPER(NAME, uint64_t, q_be) #else -#define GEN_ATOMIC_HELPER_ALL(NAME) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ +#define GEN_ATOMIC_HELPER_ALL(NAME) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) #endif @@ -1615,21 +1523,15 @@ GEN_ATOMIC_HELPER_ALL(xchg) * the ld/st functions are only defined if HAVE_ATOMIC128, * as defined by . */ -Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr, - Int128 cmpv, Int128 newv, - TCGMemOpIdx oi, uintptr_t retaddr); -Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr, - Int128 cmpv, Int128 newv, - TCGMemOpIdx oi, uintptr_t retaddr); - -Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); -Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); -void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val, - TCGMemOpIdx oi, uintptr_t retaddr); -void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val, - TCGMemOpIdx oi, uintptr_t retaddr); +Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr, Int128 cmpv, Int128 newv, TCGMemOpIdx oi, + uintptr_t retaddr); +Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr, Int128 cmpv, Int128 newv, TCGMemOpIdx oi, + uintptr_t retaddr); + +Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); +Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); +void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val, TCGMemOpIdx oi, uintptr_t retaddr); +void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val, TCGMemOpIdx oi, uintptr_t retaddr); void tcg_dump_ops(TCGContext *s, bool have_prefs); diff --git a/src/i386/tcg-target.inc.c b/src/i386/tcg-target.inc.c index a4d4c18..b045bf3 100644 --- a/src/i386/tcg-target.inc.c +++ b/src/i386/tcg-target.inc.c @@ -25,66 +25,34 @@ #include "../tcg-pool.inc.c" #ifdef CONFIG_DEBUG_TCG -static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { +static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { #if TCG_TARGET_REG_BITS == 64 - "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", + "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", #else - "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", + "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", #endif - "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", - "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7", + "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", + "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7", #if TCG_TARGET_REG_BITS == 64 - "%xmm8", "%xmm9", "%xmm10", "%xmm11", - "%xmm12", "%xmm13", "%xmm14", "%xmm15", + "%xmm8", "%xmm9", "%xmm10", "%xmm11", "%xmm12", "%xmm13", "%xmm14", "%xmm15", #endif }; #endif static const int tcg_target_reg_alloc_order[] = { #if TCG_TARGET_REG_BITS == 64 - TCG_REG_RBP, - TCG_REG_RBX, - TCG_REG_R12, - TCG_REG_R13, - TCG_REG_R14, - TCG_REG_R15, - TCG_REG_R10, - TCG_REG_R11, - TCG_REG_R9, - TCG_REG_R8, - TCG_REG_RCX, - TCG_REG_RDX, - TCG_REG_RSI, - TCG_REG_RDI, - TCG_REG_RAX, + TCG_REG_RBP, TCG_REG_RBX, TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, TCG_REG_R10, TCG_REG_R11, TCG_REG_R9, + TCG_REG_R8, TCG_REG_RCX, TCG_REG_RDX, TCG_REG_RSI, TCG_REG_RDI, TCG_REG_RAX, #else - TCG_REG_EBX, - TCG_REG_ESI, - TCG_REG_EDI, - TCG_REG_EBP, - TCG_REG_ECX, - TCG_REG_EDX, - TCG_REG_EAX, + TCG_REG_EBX, TCG_REG_ESI, TCG_REG_EDI, TCG_REG_EBP, TCG_REG_ECX, TCG_REG_EDX, TCG_REG_EAX, #endif - TCG_REG_XMM0, - TCG_REG_XMM1, - TCG_REG_XMM2, - TCG_REG_XMM3, - TCG_REG_XMM4, - TCG_REG_XMM5, + TCG_REG_XMM0, TCG_REG_XMM1, TCG_REG_XMM2, TCG_REG_XMM3, TCG_REG_XMM4, TCG_REG_XMM5, #ifndef _WIN64 /* The Win64 ABI has xmm6-xmm15 as caller-saves, and we do not save any of them. Therefore only allow xmm0-xmm5 to be allocated. */ - TCG_REG_XMM6, - TCG_REG_XMM7, + TCG_REG_XMM6, TCG_REG_XMM7, #if TCG_TARGET_REG_BITS == 64 - TCG_REG_XMM8, - TCG_REG_XMM9, - TCG_REG_XMM10, - TCG_REG_XMM11, - TCG_REG_XMM12, - TCG_REG_XMM13, - TCG_REG_XMM14, + TCG_REG_XMM8, TCG_REG_XMM9, TCG_REG_XMM10, TCG_REG_XMM11, TCG_REG_XMM12, TCG_REG_XMM13, TCG_REG_XMM14, TCG_REG_XMM15, #endif #endif @@ -93,25 +61,19 @@ static const int tcg_target_reg_alloc_order[] = { static const int tcg_target_call_iarg_regs[] = { #if TCG_TARGET_REG_BITS == 64 #if defined(_WIN64) - TCG_REG_RCX, - TCG_REG_RDX, + TCG_REG_RCX, TCG_REG_RDX, #else - TCG_REG_RDI, - TCG_REG_RSI, - TCG_REG_RDX, - TCG_REG_RCX, + TCG_REG_RDI, TCG_REG_RSI, TCG_REG_RDX, TCG_REG_RCX, #endif - TCG_REG_R8, - TCG_REG_R9, + TCG_REG_R8, TCG_REG_R9, #else - /* 32 bit mode uses stack based calling convention (GCC default). */ +/* 32 bit mode uses stack based calling convention (GCC default). */ #endif }; -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_EAX, +static const int tcg_target_call_oarg_regs[] = {TCG_REG_EAX, #if TCG_TARGET_REG_BITS == 32 - TCG_REG_EDX + TCG_REG_EDX #endif }; @@ -125,11 +87,11 @@ static const int tcg_target_call_oarg_regs[] = { registers on x86_64, and two random call clobbered registers on i386. */ #if TCG_TARGET_REG_BITS == 64 -# define TCG_REG_L0 tcg_target_call_iarg_regs[0] -# define TCG_REG_L1 tcg_target_call_iarg_regs[1] +#define TCG_REG_L0 tcg_target_call_iarg_regs[0] +#define TCG_REG_L1 tcg_target_call_iarg_regs[1] #else -# define TCG_REG_L0 TCG_REG_EAX -# define TCG_REG_L1 TCG_REG_EDX +#define TCG_REG_L0 TCG_REG_EAX +#define TCG_REG_L1 TCG_REG_EDX #endif /* The host compiler should supply to enable runtime features @@ -141,11 +103,11 @@ static const int tcg_target_call_oarg_regs[] = { /* For 64-bit, we always know that CMOV is available. */ #if TCG_TARGET_REG_BITS == 64 -# define have_cmov 1 +#define have_cmov 1 #elif defined(CONFIG_CPUID_H) static bool have_cmov; #else -# define have_cmov 0 +#define have_cmov 0 #endif /* We need these symbols in tcg-target.h, and we can't properly conditionalize @@ -160,141 +122,135 @@ static bool have_movbe; static bool have_bmi2; static bool have_lzcnt; #else -# define have_movbe 0 -# define have_bmi2 0 -# define have_lzcnt 0 +#define have_movbe 0 +#define have_bmi2 0 +#define have_lzcnt 0 #endif static tcg_insn_unit *tb_ret_addr; -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, - intptr_t value, intptr_t addend) -{ +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { value += addend; - switch(type) { - case R_386_PC32: - value -= (uintptr_t)code_ptr; - if (value != (int32_t)value) { - return false; - } + switch (type) { + case R_386_PC32: + value -= (uintptr_t) code_ptr; + if (value != (int32_t) value) { + return false; + } /* FALLTHRU */ - case R_386_32: - tcg_patch32(code_ptr, value); - break; - case R_386_PC8: - value -= (uintptr_t)code_ptr; - if (value != (int8_t)value) { - return false; - } - tcg_patch8(code_ptr, value); - break; - default: - tcg_abort(); + case R_386_32: + tcg_patch32(code_ptr, value); + break; + case R_386_PC8: + value -= (uintptr_t) code_ptr; + if (value != (int8_t) value) { + return false; + } + tcg_patch8(code_ptr, value); + break; + default: + tcg_abort(); } return true; } #if TCG_TARGET_REG_BITS == 64 -#define ALL_GENERAL_REGS 0x0000ffffu -#define ALL_VECTOR_REGS 0xffff0000u +#define ALL_GENERAL_REGS 0x0000ffffu +#define ALL_VECTOR_REGS 0xffff0000u #else -#define ALL_GENERAL_REGS 0x000000ffu -#define ALL_VECTOR_REGS 0x00ff0000u +#define ALL_GENERAL_REGS 0x000000ffu +#define ALL_VECTOR_REGS 0x00ff0000u #endif /* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch(*ct_str++) { - case 'a': - ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX); - break; - case 'b': - ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX); - break; - case 'c': - ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX); - break; - case 'd': - ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX); - break; - case 'S': - ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI); - break; - case 'D': - ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI); - break; - case 'q': - /* A register that can be used as a byte operand. */ - ct->ct |= TCG_CT_REG; - ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf; - break; - case 'Q': - /* A register with an addressable second byte (e.g. %ah). */ - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xf; - break; - case 'r': - /* A general register. */ - ct->ct |= TCG_CT_REG; - ct->u.regs |= ALL_GENERAL_REGS; - break; - case 'W': - /* With TZCNT/LZCNT, we can have operand-size as an input. */ - ct->ct |= TCG_CT_CONST_WSZ; - break; - case 'x': - /* A vector register. */ - ct->ct |= TCG_CT_REG; - ct->u.regs |= ALL_VECTOR_REGS; - break; +static const char *target_parse_constraint(TCGArgConstraint *ct, const char *ct_str, TCGType type) { + switch (*ct_str++) { + case 'a': + ct->ct |= TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX); + break; + case 'b': + ct->ct |= TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX); + break; + case 'c': + ct->ct |= TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX); + break; + case 'd': + ct->ct |= TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX); + break; + case 'S': + ct->ct |= TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI); + break; + case 'D': + ct->ct |= TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI); + break; + case 'q': + /* A register that can be used as a byte operand. */ + ct->ct |= TCG_CT_REG; + ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf; + break; + case 'Q': + /* A register with an addressable second byte (e.g. %ah). */ + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xf; + break; + case 'r': + /* A general register. */ + ct->ct |= TCG_CT_REG; + ct->u.regs |= ALL_GENERAL_REGS; + break; + case 'W': + /* With TZCNT/LZCNT, we can have operand-size as an input. */ + ct->ct |= TCG_CT_CONST_WSZ; + break; + case 'x': + /* A vector register. */ + ct->ct |= TCG_CT_REG; + ct->u.regs |= ALL_VECTOR_REGS; + break; /* qemu_ld/st address constraint */ - case 'L': - ct->ct |= TCG_CT_REG; - ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1); - break; - - case 'e': - ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_S32); - break; - case 'Z': - ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_U32); - break; - case 'I': - ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_I32); - break; - - default: - return NULL; + case 'L': + ct->ct |= TCG_CT_REG; + ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff; + tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1); + break; + + case 'e': + ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_S32); + break; + case 'Z': + ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_U32); + break; + case 'I': + ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_I32); + break; + + default: + return NULL; } return ct_str; } /* test if a constant matches the constraint */ -static inline int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct) -{ +static inline int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) { int ct = arg_ct->ct; if (ct & TCG_CT_CONST) { return 1; } - if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { + if ((ct & TCG_CT_CONST_S32) && val == (int32_t) val) { return 1; } - if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { + if ((ct & TCG_CT_CONST_U32) && val == (uint32_t) val) { return 1; } - if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) { + if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t) ~val) { return 1; } if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { @@ -303,177 +259,177 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, return 0; } -# define LOWREGMASK(x) ((x) & 7) +#define LOWREGMASK(x) ((x) &7) -#define P_EXT 0x100 /* 0x0f opcode prefix */ -#define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */ -#define P_DATA16 0x400 /* 0x66 opcode prefix */ +#define P_EXT 0x100 /* 0x0f opcode prefix */ +#define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */ +#define P_DATA16 0x400 /* 0x66 opcode prefix */ #if TCG_TARGET_REG_BITS == 64 -# define P_REXW 0x1000 /* Set REX.W = 1 */ -# define P_REXB_R 0x2000 /* REG field as byte register */ -# define P_REXB_RM 0x4000 /* R/M field as byte register */ -# define P_GS 0x8000 /* gs segment override */ +#define P_REXW 0x1000 /* Set REX.W = 1 */ +#define P_REXB_R 0x2000 /* REG field as byte register */ +#define P_REXB_RM 0x4000 /* R/M field as byte register */ +#define P_GS 0x8000 /* gs segment override */ #else -# define P_REXW 0 -# define P_REXB_R 0 -# define P_REXB_RM 0 -# define P_GS 0 +#define P_REXW 0 +#define P_REXB_R 0 +#define P_REXB_RM 0 +#define P_GS 0 #endif -#define P_EXT3A 0x10000 /* 0x0f 0x3a opcode prefix */ -#define P_SIMDF3 0x20000 /* 0xf3 opcode prefix */ -#define P_SIMDF2 0x40000 /* 0xf2 opcode prefix */ -#define P_VEXL 0x80000 /* Set VEX.L = 1 */ - -#define OPC_ARITH_EvIz (0x81) -#define OPC_ARITH_EvIb (0x83) -#define OPC_ARITH_GvEv (0x03) /* ... plus (ARITH_FOO << 3) */ -#define OPC_ANDN (0xf2 | P_EXT38) -#define OPC_ADD_GvEv (OPC_ARITH_GvEv | (ARITH_ADD << 3)) -#define OPC_AND_GvEv (OPC_ARITH_GvEv | (ARITH_AND << 3)) -#define OPC_BLENDPS (0x0c | P_EXT3A | P_DATA16) -#define OPC_BSF (0xbc | P_EXT) -#define OPC_BSR (0xbd | P_EXT) -#define OPC_BSWAP (0xc8 | P_EXT) -#define OPC_CALL_Jz (0xe8) -#define OPC_CMOVCC (0x40 | P_EXT) /* ... plus condition code */ -#define OPC_CMP_GvEv (OPC_ARITH_GvEv | (ARITH_CMP << 3)) -#define OPC_DEC_r32 (0x48) -#define OPC_IMUL_GvEv (0xaf | P_EXT) -#define OPC_IMUL_GvEvIb (0x6b) -#define OPC_IMUL_GvEvIz (0x69) -#define OPC_INC_r32 (0x40) -#define OPC_JCC_long (0x80 | P_EXT) /* ... plus condition code */ -#define OPC_JCC_short (0x70) /* ... plus condition code */ -#define OPC_JMP_long (0xe9) -#define OPC_JMP_short (0xeb) -#define OPC_LEA (0x8d) -#define OPC_LZCNT (0xbd | P_EXT | P_SIMDF3) -#define OPC_MOVB_EvGv (0x88) /* stores, more or less */ -#define OPC_MOVL_EvGv (0x89) /* stores, more or less */ -#define OPC_MOVL_GvEv (0x8b) /* loads, more or less */ -#define OPC_MOVB_EvIz (0xc6) -#define OPC_MOVL_EvIz (0xc7) -#define OPC_MOVL_Iv (0xb8) -#define OPC_MOVBE_GyMy (0xf0 | P_EXT38) -#define OPC_MOVBE_MyGy (0xf1 | P_EXT38) -#define OPC_MOVD_VyEy (0x6e | P_EXT | P_DATA16) -#define OPC_MOVD_EyVy (0x7e | P_EXT | P_DATA16) -#define OPC_MOVDDUP (0x12 | P_EXT | P_SIMDF2) +#define P_EXT3A 0x10000 /* 0x0f 0x3a opcode prefix */ +#define P_SIMDF3 0x20000 /* 0xf3 opcode prefix */ +#define P_SIMDF2 0x40000 /* 0xf2 opcode prefix */ +#define P_VEXL 0x80000 /* Set VEX.L = 1 */ + +#define OPC_ARITH_EvIz (0x81) +#define OPC_ARITH_EvIb (0x83) +#define OPC_ARITH_GvEv (0x03) /* ... plus (ARITH_FOO << 3) */ +#define OPC_ANDN (0xf2 | P_EXT38) +#define OPC_ADD_GvEv (OPC_ARITH_GvEv | (ARITH_ADD << 3)) +#define OPC_AND_GvEv (OPC_ARITH_GvEv | (ARITH_AND << 3)) +#define OPC_BLENDPS (0x0c | P_EXT3A | P_DATA16) +#define OPC_BSF (0xbc | P_EXT) +#define OPC_BSR (0xbd | P_EXT) +#define OPC_BSWAP (0xc8 | P_EXT) +#define OPC_CALL_Jz (0xe8) +#define OPC_CMOVCC (0x40 | P_EXT) /* ... plus condition code */ +#define OPC_CMP_GvEv (OPC_ARITH_GvEv | (ARITH_CMP << 3)) +#define OPC_DEC_r32 (0x48) +#define OPC_IMUL_GvEv (0xaf | P_EXT) +#define OPC_IMUL_GvEvIb (0x6b) +#define OPC_IMUL_GvEvIz (0x69) +#define OPC_INC_r32 (0x40) +#define OPC_JCC_long (0x80 | P_EXT) /* ... plus condition code */ +#define OPC_JCC_short (0x70) /* ... plus condition code */ +#define OPC_JMP_long (0xe9) +#define OPC_JMP_short (0xeb) +#define OPC_LEA (0x8d) +#define OPC_LZCNT (0xbd | P_EXT | P_SIMDF3) +#define OPC_MOVB_EvGv (0x88) /* stores, more or less */ +#define OPC_MOVL_EvGv (0x89) /* stores, more or less */ +#define OPC_MOVL_GvEv (0x8b) /* loads, more or less */ +#define OPC_MOVB_EvIz (0xc6) +#define OPC_MOVL_EvIz (0xc7) +#define OPC_MOVL_Iv (0xb8) +#define OPC_MOVBE_GyMy (0xf0 | P_EXT38) +#define OPC_MOVBE_MyGy (0xf1 | P_EXT38) +#define OPC_MOVD_VyEy (0x6e | P_EXT | P_DATA16) +#define OPC_MOVD_EyVy (0x7e | P_EXT | P_DATA16) +#define OPC_MOVDDUP (0x12 | P_EXT | P_SIMDF2) #define OPC_MOVDQA_VxWx (0x6f | P_EXT | P_DATA16) #define OPC_MOVDQA_WxVx (0x7f | P_EXT | P_DATA16) #define OPC_MOVDQU_VxWx (0x6f | P_EXT | P_SIMDF3) #define OPC_MOVDQU_WxVx (0x7f | P_EXT | P_SIMDF3) -#define OPC_MOVQ_VqWq (0x7e | P_EXT | P_SIMDF3) -#define OPC_MOVQ_WqVq (0xd6 | P_EXT | P_DATA16) -#define OPC_MOVSBL (0xbe | P_EXT) -#define OPC_MOVSWL (0xbf | P_EXT) -#define OPC_MOVSLQ (0x63 | P_REXW) -#define OPC_MOVZBL (0xb6 | P_EXT) -#define OPC_MOVZWL (0xb7 | P_EXT) -#define OPC_PACKSSDW (0x6b | P_EXT | P_DATA16) -#define OPC_PACKSSWB (0x63 | P_EXT | P_DATA16) -#define OPC_PACKUSDW (0x2b | P_EXT38 | P_DATA16) -#define OPC_PACKUSWB (0x67 | P_EXT | P_DATA16) -#define OPC_PADDB (0xfc | P_EXT | P_DATA16) -#define OPC_PADDW (0xfd | P_EXT | P_DATA16) -#define OPC_PADDD (0xfe | P_EXT | P_DATA16) -#define OPC_PADDQ (0xd4 | P_EXT | P_DATA16) -#define OPC_PADDSB (0xec | P_EXT | P_DATA16) -#define OPC_PADDSW (0xed | P_EXT | P_DATA16) -#define OPC_PADDUB (0xdc | P_EXT | P_DATA16) -#define OPC_PADDUW (0xdd | P_EXT | P_DATA16) -#define OPC_PAND (0xdb | P_EXT | P_DATA16) -#define OPC_PANDN (0xdf | P_EXT | P_DATA16) -#define OPC_PBLENDW (0x0e | P_EXT3A | P_DATA16) -#define OPC_PCMPEQB (0x74 | P_EXT | P_DATA16) -#define OPC_PCMPEQW (0x75 | P_EXT | P_DATA16) -#define OPC_PCMPEQD (0x76 | P_EXT | P_DATA16) -#define OPC_PCMPEQQ (0x29 | P_EXT38 | P_DATA16) -#define OPC_PCMPGTB (0x64 | P_EXT | P_DATA16) -#define OPC_PCMPGTW (0x65 | P_EXT | P_DATA16) -#define OPC_PCMPGTD (0x66 | P_EXT | P_DATA16) -#define OPC_PCMPGTQ (0x37 | P_EXT38 | P_DATA16) -#define OPC_PMAXSB (0x3c | P_EXT38 | P_DATA16) -#define OPC_PMAXSW (0xee | P_EXT | P_DATA16) -#define OPC_PMAXSD (0x3d | P_EXT38 | P_DATA16) -#define OPC_PMAXUB (0xde | P_EXT | P_DATA16) -#define OPC_PMAXUW (0x3e | P_EXT38 | P_DATA16) -#define OPC_PMAXUD (0x3f | P_EXT38 | P_DATA16) -#define OPC_PMINSB (0x38 | P_EXT38 | P_DATA16) -#define OPC_PMINSW (0xea | P_EXT | P_DATA16) -#define OPC_PMINSD (0x39 | P_EXT38 | P_DATA16) -#define OPC_PMINUB (0xda | P_EXT | P_DATA16) -#define OPC_PMINUW (0x3a | P_EXT38 | P_DATA16) -#define OPC_PMINUD (0x3b | P_EXT38 | P_DATA16) -#define OPC_PMOVSXBW (0x20 | P_EXT38 | P_DATA16) -#define OPC_PMOVSXWD (0x23 | P_EXT38 | P_DATA16) -#define OPC_PMOVSXDQ (0x25 | P_EXT38 | P_DATA16) -#define OPC_PMOVZXBW (0x30 | P_EXT38 | P_DATA16) -#define OPC_PMOVZXWD (0x33 | P_EXT38 | P_DATA16) -#define OPC_PMOVZXDQ (0x35 | P_EXT38 | P_DATA16) -#define OPC_PMULLW (0xd5 | P_EXT | P_DATA16) -#define OPC_PMULLD (0x40 | P_EXT38 | P_DATA16) -#define OPC_POR (0xeb | P_EXT | P_DATA16) -#define OPC_PSHUFB (0x00 | P_EXT38 | P_DATA16) -#define OPC_PSHUFD (0x70 | P_EXT | P_DATA16) -#define OPC_PSHUFLW (0x70 | P_EXT | P_SIMDF2) -#define OPC_PSHUFHW (0x70 | P_EXT | P_SIMDF3) -#define OPC_PSHIFTW_Ib (0x71 | P_EXT | P_DATA16) /* /2 /6 /4 */ -#define OPC_PSHIFTD_Ib (0x72 | P_EXT | P_DATA16) /* /2 /6 /4 */ -#define OPC_PSHIFTQ_Ib (0x73 | P_EXT | P_DATA16) /* /2 /6 /4 */ -#define OPC_PSUBB (0xf8 | P_EXT | P_DATA16) -#define OPC_PSUBW (0xf9 | P_EXT | P_DATA16) -#define OPC_PSUBD (0xfa | P_EXT | P_DATA16) -#define OPC_PSUBQ (0xfb | P_EXT | P_DATA16) -#define OPC_PSUBSB (0xe8 | P_EXT | P_DATA16) -#define OPC_PSUBSW (0xe9 | P_EXT | P_DATA16) -#define OPC_PSUBUB (0xd8 | P_EXT | P_DATA16) -#define OPC_PSUBUW (0xd9 | P_EXT | P_DATA16) -#define OPC_PUNPCKLBW (0x60 | P_EXT | P_DATA16) -#define OPC_PUNPCKLWD (0x61 | P_EXT | P_DATA16) -#define OPC_PUNPCKLDQ (0x62 | P_EXT | P_DATA16) -#define OPC_PUNPCKLQDQ (0x6c | P_EXT | P_DATA16) -#define OPC_PUNPCKHBW (0x68 | P_EXT | P_DATA16) -#define OPC_PUNPCKHWD (0x69 | P_EXT | P_DATA16) -#define OPC_PUNPCKHDQ (0x6a | P_EXT | P_DATA16) -#define OPC_PUNPCKHQDQ (0x6d | P_EXT | P_DATA16) -#define OPC_PXOR (0xef | P_EXT | P_DATA16) -#define OPC_POP_r32 (0x58) -#define OPC_POPCNT (0xb8 | P_EXT | P_SIMDF3) -#define OPC_PUSH_r32 (0x50) -#define OPC_PUSH_Iv (0x68) -#define OPC_PUSH_Ib (0x6a) -#define OPC_RET (0xc3) -#define OPC_SETCC (0x90 | P_EXT | P_REXB_RM) /* ... plus cc */ -#define OPC_SHIFT_1 (0xd1) -#define OPC_SHIFT_Ib (0xc1) -#define OPC_SHIFT_cl (0xd3) -#define OPC_SARX (0xf7 | P_EXT38 | P_SIMDF3) -#define OPC_SHUFPS (0xc6 | P_EXT) -#define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16) -#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2) -#define OPC_TESTL (0x85) -#define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3) -#define OPC_UD2 (0x0b | P_EXT) -#define OPC_VPBLENDD (0x02 | P_EXT3A | P_DATA16) -#define OPC_VPBLENDVB (0x4c | P_EXT3A | P_DATA16) +#define OPC_MOVQ_VqWq (0x7e | P_EXT | P_SIMDF3) +#define OPC_MOVQ_WqVq (0xd6 | P_EXT | P_DATA16) +#define OPC_MOVSBL (0xbe | P_EXT) +#define OPC_MOVSWL (0xbf | P_EXT) +#define OPC_MOVSLQ (0x63 | P_REXW) +#define OPC_MOVZBL (0xb6 | P_EXT) +#define OPC_MOVZWL (0xb7 | P_EXT) +#define OPC_PACKSSDW (0x6b | P_EXT | P_DATA16) +#define OPC_PACKSSWB (0x63 | P_EXT | P_DATA16) +#define OPC_PACKUSDW (0x2b | P_EXT38 | P_DATA16) +#define OPC_PACKUSWB (0x67 | P_EXT | P_DATA16) +#define OPC_PADDB (0xfc | P_EXT | P_DATA16) +#define OPC_PADDW (0xfd | P_EXT | P_DATA16) +#define OPC_PADDD (0xfe | P_EXT | P_DATA16) +#define OPC_PADDQ (0xd4 | P_EXT | P_DATA16) +#define OPC_PADDSB (0xec | P_EXT | P_DATA16) +#define OPC_PADDSW (0xed | P_EXT | P_DATA16) +#define OPC_PADDUB (0xdc | P_EXT | P_DATA16) +#define OPC_PADDUW (0xdd | P_EXT | P_DATA16) +#define OPC_PAND (0xdb | P_EXT | P_DATA16) +#define OPC_PANDN (0xdf | P_EXT | P_DATA16) +#define OPC_PBLENDW (0x0e | P_EXT3A | P_DATA16) +#define OPC_PCMPEQB (0x74 | P_EXT | P_DATA16) +#define OPC_PCMPEQW (0x75 | P_EXT | P_DATA16) +#define OPC_PCMPEQD (0x76 | P_EXT | P_DATA16) +#define OPC_PCMPEQQ (0x29 | P_EXT38 | P_DATA16) +#define OPC_PCMPGTB (0x64 | P_EXT | P_DATA16) +#define OPC_PCMPGTW (0x65 | P_EXT | P_DATA16) +#define OPC_PCMPGTD (0x66 | P_EXT | P_DATA16) +#define OPC_PCMPGTQ (0x37 | P_EXT38 | P_DATA16) +#define OPC_PMAXSB (0x3c | P_EXT38 | P_DATA16) +#define OPC_PMAXSW (0xee | P_EXT | P_DATA16) +#define OPC_PMAXSD (0x3d | P_EXT38 | P_DATA16) +#define OPC_PMAXUB (0xde | P_EXT | P_DATA16) +#define OPC_PMAXUW (0x3e | P_EXT38 | P_DATA16) +#define OPC_PMAXUD (0x3f | P_EXT38 | P_DATA16) +#define OPC_PMINSB (0x38 | P_EXT38 | P_DATA16) +#define OPC_PMINSW (0xea | P_EXT | P_DATA16) +#define OPC_PMINSD (0x39 | P_EXT38 | P_DATA16) +#define OPC_PMINUB (0xda | P_EXT | P_DATA16) +#define OPC_PMINUW (0x3a | P_EXT38 | P_DATA16) +#define OPC_PMINUD (0x3b | P_EXT38 | P_DATA16) +#define OPC_PMOVSXBW (0x20 | P_EXT38 | P_DATA16) +#define OPC_PMOVSXWD (0x23 | P_EXT38 | P_DATA16) +#define OPC_PMOVSXDQ (0x25 | P_EXT38 | P_DATA16) +#define OPC_PMOVZXBW (0x30 | P_EXT38 | P_DATA16) +#define OPC_PMOVZXWD (0x33 | P_EXT38 | P_DATA16) +#define OPC_PMOVZXDQ (0x35 | P_EXT38 | P_DATA16) +#define OPC_PMULLW (0xd5 | P_EXT | P_DATA16) +#define OPC_PMULLD (0x40 | P_EXT38 | P_DATA16) +#define OPC_POR (0xeb | P_EXT | P_DATA16) +#define OPC_PSHUFB (0x00 | P_EXT38 | P_DATA16) +#define OPC_PSHUFD (0x70 | P_EXT | P_DATA16) +#define OPC_PSHUFLW (0x70 | P_EXT | P_SIMDF2) +#define OPC_PSHUFHW (0x70 | P_EXT | P_SIMDF3) +#define OPC_PSHIFTW_Ib (0x71 | P_EXT | P_DATA16) /* /2 /6 /4 */ +#define OPC_PSHIFTD_Ib (0x72 | P_EXT | P_DATA16) /* /2 /6 /4 */ +#define OPC_PSHIFTQ_Ib (0x73 | P_EXT | P_DATA16) /* /2 /6 /4 */ +#define OPC_PSUBB (0xf8 | P_EXT | P_DATA16) +#define OPC_PSUBW (0xf9 | P_EXT | P_DATA16) +#define OPC_PSUBD (0xfa | P_EXT | P_DATA16) +#define OPC_PSUBQ (0xfb | P_EXT | P_DATA16) +#define OPC_PSUBSB (0xe8 | P_EXT | P_DATA16) +#define OPC_PSUBSW (0xe9 | P_EXT | P_DATA16) +#define OPC_PSUBUB (0xd8 | P_EXT | P_DATA16) +#define OPC_PSUBUW (0xd9 | P_EXT | P_DATA16) +#define OPC_PUNPCKLBW (0x60 | P_EXT | P_DATA16) +#define OPC_PUNPCKLWD (0x61 | P_EXT | P_DATA16) +#define OPC_PUNPCKLDQ (0x62 | P_EXT | P_DATA16) +#define OPC_PUNPCKLQDQ (0x6c | P_EXT | P_DATA16) +#define OPC_PUNPCKHBW (0x68 | P_EXT | P_DATA16) +#define OPC_PUNPCKHWD (0x69 | P_EXT | P_DATA16) +#define OPC_PUNPCKHDQ (0x6a | P_EXT | P_DATA16) +#define OPC_PUNPCKHQDQ (0x6d | P_EXT | P_DATA16) +#define OPC_PXOR (0xef | P_EXT | P_DATA16) +#define OPC_POP_r32 (0x58) +#define OPC_POPCNT (0xb8 | P_EXT | P_SIMDF3) +#define OPC_PUSH_r32 (0x50) +#define OPC_PUSH_Iv (0x68) +#define OPC_PUSH_Ib (0x6a) +#define OPC_RET (0xc3) +#define OPC_SETCC (0x90 | P_EXT | P_REXB_RM) /* ... plus cc */ +#define OPC_SHIFT_1 (0xd1) +#define OPC_SHIFT_Ib (0xc1) +#define OPC_SHIFT_cl (0xd3) +#define OPC_SARX (0xf7 | P_EXT38 | P_SIMDF3) +#define OPC_SHUFPS (0xc6 | P_EXT) +#define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16) +#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2) +#define OPC_TESTL (0x85) +#define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3) +#define OPC_UD2 (0x0b | P_EXT) +#define OPC_VPBLENDD (0x02 | P_EXT3A | P_DATA16) +#define OPC_VPBLENDVB (0x4c | P_EXT3A | P_DATA16) #define OPC_VPBROADCASTB (0x78 | P_EXT38 | P_DATA16) #define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16) #define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16) #define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16) -#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_REXW) -#define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL) -#define OPC_VZEROUPPER (0x77 | P_EXT) -#define OPC_XCHG_ax_r32 (0x90) +#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_REXW) +#define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL) +#define OPC_VZEROUPPER (0x77 | P_EXT) +#define OPC_XCHG_ax_r32 (0x90) -#define OPC_GRP3_Ev (0xf7) -#define OPC_GRP5 (0xff) -#define OPC_GRP14 (0x73 | P_EXT | P_DATA16) +#define OPC_GRP3_Ev (0xf7) +#define OPC_GRP5 (0xff) +#define OPC_GRP14 (0x73 | P_EXT | P_DATA16) /* Group 1 opcode extensions for 0x80-0x83. These are also used as modifiers for OPC_ARITH. */ #define ARITH_ADD 0 -#define ARITH_OR 1 +#define ARITH_OR 1 #define ARITH_ADC 2 #define ARITH_SBB 3 #define ARITH_AND 4 @@ -489,54 +445,46 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, #define SHIFT_SAR 7 /* Group 3 opcode extensions for 0xf6, 0xf7. To be used with OPC_GRP3. */ -#define EXT3_NOT 2 -#define EXT3_NEG 3 -#define EXT3_MUL 4 -#define EXT3_IMUL 5 -#define EXT3_DIV 6 -#define EXT3_IDIV 7 +#define EXT3_NOT 2 +#define EXT3_NEG 3 +#define EXT3_MUL 4 +#define EXT3_IMUL 5 +#define EXT3_DIV 6 +#define EXT3_IDIV 7 /* Group 5 opcode extensions for 0xff. To be used with OPC_GRP5. */ -#define EXT5_INC_Ev 0 -#define EXT5_DEC_Ev 1 -#define EXT5_CALLN_Ev 2 -#define EXT5_JMPN_Ev 4 +#define EXT5_INC_Ev 0 +#define EXT5_DEC_Ev 1 +#define EXT5_CALLN_Ev 2 +#define EXT5_JMPN_Ev 4 /* Condition codes to be added to OPC_JCC_{long,short}. */ #define JCC_JMP (-1) -#define JCC_JO 0x0 +#define JCC_JO 0x0 #define JCC_JNO 0x1 -#define JCC_JB 0x2 +#define JCC_JB 0x2 #define JCC_JAE 0x3 -#define JCC_JE 0x4 +#define JCC_JE 0x4 #define JCC_JNE 0x5 #define JCC_JBE 0x6 -#define JCC_JA 0x7 -#define JCC_JS 0x8 +#define JCC_JA 0x7 +#define JCC_JS 0x8 #define JCC_JNS 0x9 -#define JCC_JP 0xa +#define JCC_JP 0xa #define JCC_JNP 0xb -#define JCC_JL 0xc +#define JCC_JL 0xc #define JCC_JGE 0xd #define JCC_JLE 0xe -#define JCC_JG 0xf +#define JCC_JG 0xf static const uint8_t tcg_cond_to_jcc[] = { - [TCG_COND_EQ] = JCC_JE, - [TCG_COND_NE] = JCC_JNE, - [TCG_COND_LT] = JCC_JL, - [TCG_COND_GE] = JCC_JGE, - [TCG_COND_LE] = JCC_JLE, - [TCG_COND_GT] = JCC_JG, - [TCG_COND_LTU] = JCC_JB, - [TCG_COND_GEU] = JCC_JAE, - [TCG_COND_LEU] = JCC_JBE, - [TCG_COND_GTU] = JCC_JA, + [TCG_COND_EQ] = JCC_JE, [TCG_COND_NE] = JCC_JNE, [TCG_COND_LT] = JCC_JL, [TCG_COND_GE] = JCC_JGE, + [TCG_COND_LE] = JCC_JLE, [TCG_COND_GT] = JCC_JG, [TCG_COND_LTU] = JCC_JB, [TCG_COND_GEU] = JCC_JAE, + [TCG_COND_LEU] = JCC_JBE, [TCG_COND_GTU] = JCC_JA, }; #if TCG_TARGET_REG_BITS == 64 -static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) -{ +static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) { int rex; if (opc & P_GS) { @@ -554,10 +502,10 @@ static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) } rex = 0; - rex |= (opc & P_REXW) ? 0x8 : 0x0; /* REX.W */ - rex |= (r & 8) >> 1; /* REX.R */ - rex |= (x & 8) >> 2; /* REX.X */ - rex |= (rm & 8) >> 3; /* REX.B */ + rex |= (opc & P_REXW) ? 0x8 : 0x0; /* REX.W */ + rex |= (r & 8) >> 1; /* REX.R */ + rex |= (x & 8) >> 2; /* REX.X */ + rex |= (rm & 8) >> 3; /* REX.B */ /* P_REXB_{R,RM} indicates that the given register is the low byte. For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do, @@ -583,8 +531,7 @@ static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) tcg_out8(s, opc); } #else -static void tcg_out_opc(TCGContext *s, int opc) -{ +static void tcg_out_opc(TCGContext *s, int opc) { if (opc & P_DATA16) { tcg_out8(s, 0x66); } @@ -606,28 +553,24 @@ static void tcg_out_opc(TCGContext *s, int opc) /* Discard the register arguments to tcg_out_opc early, so as not to penalize the 32-bit compilation paths. This method works with all versions of gcc, whereas relying on optimization may not be able to exclude them. */ -#define tcg_out_opc(s, opc, r, rm, x) (tcg_out_opc)(s, opc) +#define tcg_out_opc(s, opc, r, rm, x) (tcg_out_opc)(s, opc) #endif -static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) -{ +static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) { tcg_out_opc(s, opc, r, rm, 0); tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); } -static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v, - int rm, int index) -{ +static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v, int rm, int index) { int tmp; /* Use the two byte form if possible, which cannot encode VEX.W, VEX.B, VEX.X, or an m-mmmm field other than P_EXT. */ - if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_REXW)) == P_EXT - && ((rm | index) & 8) == 0) { + if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_REXW)) == P_EXT && ((rm | index) & 8) == 0) { /* Two byte VEX prefix. */ tcg_out8(s, 0xc5); - tmp = (r & 8 ? 0 : 0x80); /* VEX.R */ + tmp = (r & 8 ? 0 : 0x80); /* VEX.R */ } else { /* Three byte VEX prefix. */ tcg_out8(s, 0xc4); @@ -642,30 +585,29 @@ static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v, } else { g_assert_not_reached(); } - tmp |= (r & 8 ? 0 : 0x80); /* VEX.R */ - tmp |= (index & 8 ? 0 : 0x40); /* VEX.X */ - tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */ + tmp |= (r & 8 ? 0 : 0x80); /* VEX.R */ + tmp |= (index & 8 ? 0 : 0x40); /* VEX.X */ + tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */ tcg_out8(s, tmp); - tmp = (opc & P_REXW ? 0x80 : 0); /* VEX.W */ + tmp = (opc & P_REXW ? 0x80 : 0); /* VEX.W */ } - tmp |= (opc & P_VEXL ? 0x04 : 0); /* VEX.L */ + tmp |= (opc & P_VEXL ? 0x04 : 0); /* VEX.L */ /* VEX.pp */ if (opc & P_DATA16) { - tmp |= 1; /* 0x66 */ + tmp |= 1; /* 0x66 */ } else if (opc & P_SIMDF3) { - tmp |= 2; /* 0xf3 */ + tmp |= 2; /* 0xf3 */ } else if (opc & P_SIMDF2) { - tmp |= 3; /* 0xf2 */ + tmp |= 3; /* 0xf2 */ } - tmp |= (~v & 15) << 3; /* VEX.vvvv */ + tmp |= (~v & 15) << 3; /* VEX.vvvv */ tcg_out8(s, tmp); tcg_out8(s, opc); } -static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm) -{ +static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm) { tcg_out_vex_opc(s, opc, r, v, rm, 0); tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); } @@ -675,18 +617,16 @@ static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm) mode for absolute addresses, ~RM is the size of the immediate operand that will follow the instruction. */ -static void tcg_out_sib_offset(TCGContext *s, int r, int rm, int index, - int shift, intptr_t offset) -{ +static void tcg_out_sib_offset(TCGContext *s, int r, int rm, int index, int shift, intptr_t offset) { int mod, len; if (index < 0 && rm < 0) { if (TCG_TARGET_REG_BITS == 64) { /* Try for a rip-relative addressing mode. This has replaced the 32-bit-mode absolute addressing encoding. */ - intptr_t pc = (intptr_t)s->code_ptr + 5 + ~rm; + intptr_t pc = (intptr_t) s->code_ptr + 5 + ~rm; intptr_t disp = offset - pc; - if (disp == (int32_t)disp) { + if (disp == (int32_t) disp) { tcg_out8(s, (LOWREGMASK(r) << 3) | 5); tcg_out32(s, disp); return; @@ -695,7 +635,7 @@ static void tcg_out_sib_offset(TCGContext *s, int r, int rm, int index, /* Try for an absolute address encoding. This requires the use of the MODRM+SIB encoding and is therefore larger than rip-relative addressing. */ - if (offset == (int32_t)offset) { + if (offset == (int32_t) offset) { tcg_out8(s, (LOWREGMASK(r) << 3) | 4); tcg_out8(s, (4 << 3) | 5); tcg_out32(s, offset); @@ -718,7 +658,7 @@ static void tcg_out_sib_offset(TCGContext *s, int r, int rm, int index, mod = 0, len = 4, rm = 5; } else if (offset == 0 && LOWREGMASK(rm) != TCG_REG_EBP) { mod = 0, len = 0; - } else if (offset == (int8_t)offset) { + } else if (offset == (int8_t) offset) { mod = 0x40, len = 1; } else { mod = 0x80, len = 4; @@ -752,37 +692,28 @@ static void tcg_out_sib_offset(TCGContext *s, int r, int rm, int index, } } -static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, - int index, int shift, intptr_t offset) -{ +static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, int index, int shift, intptr_t offset) { tcg_out_opc(s, opc, r, rm < 0 ? 0 : rm, index < 0 ? 0 : index); tcg_out_sib_offset(s, r, rm, index, shift, offset); } -static void tcg_out_vex_modrm_sib_offset(TCGContext *s, int opc, int r, int v, - int rm, int index, int shift, - intptr_t offset) -{ +static void tcg_out_vex_modrm_sib_offset(TCGContext *s, int opc, int r, int v, int rm, int index, int shift, + intptr_t offset) { tcg_out_vex_opc(s, opc, r, v, rm < 0 ? 0 : rm, index < 0 ? 0 : index); tcg_out_sib_offset(s, r, rm, index, shift, offset); } /* A simplification of the above with no index or shift. */ -static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, - int rm, intptr_t offset) -{ +static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm, intptr_t offset) { tcg_out_modrm_sib_offset(s, opc, r, rm, -1, 0, offset); } -static inline void tcg_out_vex_modrm_offset(TCGContext *s, int opc, int r, - int v, int rm, intptr_t offset) -{ +static inline void tcg_out_vex_modrm_offset(TCGContext *s, int opc, int r, int v, int rm, intptr_t offset) { tcg_out_vex_modrm_sib_offset(s, opc, r, v, rm, -1, 0, offset); } /* Output an opcode with an expected reference to the constant pool. */ -static inline void tcg_out_modrm_pool(TCGContext *s, int opc, int r) -{ +static inline void tcg_out_modrm_pool(TCGContext *s, int opc, int r) { tcg_out_opc(s, opc, r, 0, 0); /* Absolute for 32-bit, pc-relative for 64-bit. */ tcg_out8(s, LOWREGMASK(r) << 3 | 5); @@ -790,8 +721,7 @@ static inline void tcg_out_modrm_pool(TCGContext *s, int opc, int r) } /* Output an opcode with an expected reference to the constant pool. */ -static inline void tcg_out_vex_modrm_pool(TCGContext *s, int opc, int r) -{ +static inline void tcg_out_vex_modrm_pool(TCGContext *s, int opc, int r) { tcg_out_vex_opc(s, opc, r, 0, 0, 0); /* Absolute for 32-bit, pc-relative for 64-bit. */ tcg_out8(s, LOWREGMASK(r) << 3 | 5); @@ -799,8 +729,7 @@ static inline void tcg_out_vex_modrm_pool(TCGContext *s, int opc, int r) } /* Generate dest op= src. Uses the same ARITH_* codes as tgen_arithi. */ -static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src) -{ +static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src) { /* Propagate an opcode prefix, such as P_REXW. */ int ext = subop & ~0x7; subop &= 0x7; @@ -808,89 +737,83 @@ static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src) tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src); } -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) -{ +static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { int rexw = 0; if (arg == ret) { return; } switch (type) { - case TCG_TYPE_I64: - rexw = P_REXW; + case TCG_TYPE_I64: + rexw = P_REXW; /* fallthru */ - case TCG_TYPE_I32: - if (ret < 16) { - if (arg < 16) { - tcg_out_modrm(s, OPC_MOVL_GvEv + rexw, ret, arg); - } else { - tcg_out_vex_modrm(s, OPC_MOVD_EyVy + rexw, arg, 0, ret); - } - } else { - if (arg < 16) { - tcg_out_vex_modrm(s, OPC_MOVD_VyEy + rexw, ret, 0, arg); + case TCG_TYPE_I32: + if (ret < 16) { + if (arg < 16) { + tcg_out_modrm(s, OPC_MOVL_GvEv + rexw, ret, arg); + } else { + tcg_out_vex_modrm(s, OPC_MOVD_EyVy + rexw, arg, 0, ret); + } } else { - tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg); + if (arg < 16) { + tcg_out_vex_modrm(s, OPC_MOVD_VyEy + rexw, ret, 0, arg); + } else { + tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg); + } } - } - break; + break; - case TCG_TYPE_V64: - tcg_debug_assert(ret >= 16 && arg >= 16); - tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg); - break; - case TCG_TYPE_V128: - tcg_debug_assert(ret >= 16 && arg >= 16); - tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx, ret, 0, arg); - break; - case TCG_TYPE_V256: - tcg_debug_assert(ret >= 16 && arg >= 16); - tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx | P_VEXL, ret, 0, arg); - break; + case TCG_TYPE_V64: + tcg_debug_assert(ret >= 16 && arg >= 16); + tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg); + break; + case TCG_TYPE_V128: + tcg_debug_assert(ret >= 16 && arg >= 16); + tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx, ret, 0, arg); + break; + case TCG_TYPE_V256: + tcg_debug_assert(ret >= 16 && arg >= 16); + tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx | P_VEXL, ret, 0, arg); + break; - default: - g_assert_not_reached(); + default: + g_assert_not_reached(); } } -static void tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, - TCGReg r, TCGReg a) -{ +static void tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg r, TCGReg a) { if (have_avx2) { static const int dup_insn[4] = { - OPC_VPBROADCASTB, OPC_VPBROADCASTW, - OPC_VPBROADCASTD, OPC_VPBROADCASTQ, + OPC_VPBROADCASTB, OPC_VPBROADCASTW, OPC_VPBROADCASTD, OPC_VPBROADCASTQ, }; int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0); tcg_out_vex_modrm(s, dup_insn[vece] + vex_l, r, 0, a); } else { switch (vece) { - case MO_8: - /* ??? With zero in a register, use PSHUFB. */ - tcg_out_vex_modrm(s, OPC_PUNPCKLBW, r, a, a); - a = r; + case MO_8: + /* ??? With zero in a register, use PSHUFB. */ + tcg_out_vex_modrm(s, OPC_PUNPCKLBW, r, a, a); + a = r; /* FALLTHRU */ - case MO_16: - tcg_out_vex_modrm(s, OPC_PUNPCKLWD, r, a, a); - a = r; + case MO_16: + tcg_out_vex_modrm(s, OPC_PUNPCKLWD, r, a, a); + a = r; /* FALLTHRU */ - case MO_32: - tcg_out_vex_modrm(s, OPC_PSHUFD, r, 0, a); - /* imm8 operand: all output lanes selected from input lane 0. */ - tcg_out8(s, 0); - break; - case MO_64: - tcg_out_vex_modrm(s, OPC_PUNPCKLQDQ, r, a, a); - break; - default: - g_assert_not_reached(); + case MO_32: + tcg_out_vex_modrm(s, OPC_PSHUFD, r, 0, a); + /* imm8 operand: all output lanes selected from input lane 0. */ + tcg_out8(s, 0); + break; + case MO_64: + tcg_out_vex_modrm(s, OPC_PUNPCKLQDQ, r, a, a); + break; + default: + g_assert_not_reached(); } } } -static void tcg_out_dupi_vec(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) -{ +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg) { int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0); if (arg == 0) { @@ -921,48 +844,46 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, } } -static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) -{ +static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg) { tcg_target_long diff; switch (type) { - case TCG_TYPE_I32: + case TCG_TYPE_I32: #if TCG_TARGET_REG_BITS == 64 - case TCG_TYPE_I64: + case TCG_TYPE_I64: #endif - if (ret < 16) { - break; - } + if (ret < 16) { + break; + } /* fallthru */ - case TCG_TYPE_V64: - case TCG_TYPE_V128: - case TCG_TYPE_V256: - tcg_debug_assert(ret >= 16); - tcg_out_dupi_vec(s, type, ret, arg); - return; - default: - g_assert_not_reached(); + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + tcg_debug_assert(ret >= 16); + tcg_out_dupi_vec(s, type, ret, arg); + return; + default: + g_assert_not_reached(); } if (arg == 0) { tgen_arithr(s, ARITH_XOR, ret, ret); return; } - if (arg == (uint32_t)arg || type == TCG_TYPE_I32) { + if (arg == (uint32_t) arg || type == TCG_TYPE_I32) { tcg_out_opc(s, OPC_MOVL_Iv + LOWREGMASK(ret), 0, ret, 0); tcg_out32(s, arg); return; } - if (arg == (int32_t)arg) { + if (arg == (int32_t) arg) { tcg_out_modrm(s, OPC_MOVL_EvIz + P_REXW, 0, ret); tcg_out32(s, arg); return; } /* Try a 7 byte pc-relative lea before the 10 byte movq. */ - diff = arg - ((uintptr_t)s->code_ptr + 7); - if (diff == (int32_t)diff) { + diff = arg - ((uintptr_t) s->code_ptr + 7); + if (diff == (int32_t) diff) { tcg_out_opc(s, OPC_LEA | P_REXW, ret, 0, 0); tcg_out8(s, (LOWREGMASK(ret) << 3) | 5); tcg_out32(s, diff); @@ -973,12 +894,11 @@ static void tcg_out_movi(TCGContext *s, TCGType type, tcg_out64(s, arg); } -static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) -{ - if (val == (int8_t)val) { +static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) { + if (val == (int8_t) val) { tcg_out_opc(s, OPC_PUSH_Ib, 0, 0, 0); tcg_out8(s, val); - } else if (val == (int32_t)val) { + } else if (val == (int32_t) val) { tcg_out_opc(s, OPC_PUSH_Iv, 0, 0, 0); tcg_out32(s, val); } else { @@ -986,8 +906,7 @@ static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) } } -static inline void tcg_out_mb(TCGContext *s, TCGArg a0) -{ +static inline void tcg_out_mb(TCGContext *s, TCGArg a0) { /* Given the strength of x86 memory ordering, we only need care for store-load ordering. Experimentally, "lock orl $0,0(%esp)" is faster than "mfence", so don't bother with the sse insn. */ @@ -998,92 +917,82 @@ static inline void tcg_out_mb(TCGContext *s, TCGArg a0) } } -static inline void tcg_out_push(TCGContext *s, int reg) -{ +static inline void tcg_out_push(TCGContext *s, int reg) { tcg_out_opc(s, OPC_PUSH_r32 + LOWREGMASK(reg), 0, reg, 0); } -static inline void tcg_out_pop(TCGContext *s, int reg) -{ +static inline void tcg_out_pop(TCGContext *s, int reg) { tcg_out_opc(s, OPC_POP_r32 + LOWREGMASK(reg), 0, reg, 0); } -static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, - TCGReg arg1, intptr_t arg2) -{ +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, intptr_t arg2) { switch (type) { - case TCG_TYPE_I32: - if (ret < 16) { - tcg_out_modrm_offset(s, OPC_MOVL_GvEv, ret, arg1, arg2); - } else { - tcg_out_vex_modrm_offset(s, OPC_MOVD_VyEy, ret, 0, arg1, arg2); - } - break; - case TCG_TYPE_I64: - if (ret < 16) { - tcg_out_modrm_offset(s, OPC_MOVL_GvEv | P_REXW, ret, arg1, arg2); + case TCG_TYPE_I32: + if (ret < 16) { + tcg_out_modrm_offset(s, OPC_MOVL_GvEv, ret, arg1, arg2); + } else { + tcg_out_vex_modrm_offset(s, OPC_MOVD_VyEy, ret, 0, arg1, arg2); + } break; - } + case TCG_TYPE_I64: + if (ret < 16) { + tcg_out_modrm_offset(s, OPC_MOVL_GvEv | P_REXW, ret, arg1, arg2); + break; + } /* FALLTHRU */ - case TCG_TYPE_V64: - tcg_debug_assert(ret >= 16); - tcg_out_vex_modrm_offset(s, OPC_MOVQ_VqWq, ret, 0, arg1, arg2); - break; - case TCG_TYPE_V128: - tcg_debug_assert(ret >= 16); - tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx, ret, 0, arg1, arg2); - break; - case TCG_TYPE_V256: - tcg_debug_assert(ret >= 16); - tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx | P_VEXL, - ret, 0, arg1, arg2); - break; - default: - g_assert_not_reached(); - } -} - -static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) -{ + case TCG_TYPE_V64: + tcg_debug_assert(ret >= 16); + tcg_out_vex_modrm_offset(s, OPC_MOVQ_VqWq, ret, 0, arg1, arg2); + break; + case TCG_TYPE_V128: + tcg_debug_assert(ret >= 16); + tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx, ret, 0, arg1, arg2); + break; + case TCG_TYPE_V256: + tcg_debug_assert(ret >= 16); + tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx | P_VEXL, ret, 0, arg1, arg2); + break; + default: + g_assert_not_reached(); + } +} + +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { switch (type) { - case TCG_TYPE_I32: - if (arg < 16) { - tcg_out_modrm_offset(s, OPC_MOVL_EvGv, arg, arg1, arg2); - } else { - tcg_out_vex_modrm_offset(s, OPC_MOVD_EyVy, arg, 0, arg1, arg2); - } - break; - case TCG_TYPE_I64: - if (arg < 16) { - tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_REXW, arg, arg1, arg2); + case TCG_TYPE_I32: + if (arg < 16) { + tcg_out_modrm_offset(s, OPC_MOVL_EvGv, arg, arg1, arg2); + } else { + tcg_out_vex_modrm_offset(s, OPC_MOVD_EyVy, arg, 0, arg1, arg2); + } break; - } + case TCG_TYPE_I64: + if (arg < 16) { + tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_REXW, arg, arg1, arg2); + break; + } /* FALLTHRU */ - case TCG_TYPE_V64: - tcg_debug_assert(arg >= 16); - tcg_out_vex_modrm_offset(s, OPC_MOVQ_WqVq, arg, 0, arg1, arg2); - break; - case TCG_TYPE_V128: - tcg_debug_assert(arg >= 16); - tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx, arg, 0, arg1, arg2); - break; - case TCG_TYPE_V256: - tcg_debug_assert(arg >= 16); - tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx | P_VEXL, - arg, 0, arg1, arg2); - break; - default: - g_assert_not_reached(); - } -} - -static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs) -{ + case TCG_TYPE_V64: + tcg_debug_assert(arg >= 16); + tcg_out_vex_modrm_offset(s, OPC_MOVQ_WqVq, arg, 0, arg1, arg2); + break; + case TCG_TYPE_V128: + tcg_debug_assert(arg >= 16); + tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx, arg, 0, arg1, arg2); + break; + case TCG_TYPE_V256: + tcg_debug_assert(arg >= 16); + tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx | P_VEXL, arg, 0, arg1, arg2); + break; + default: + g_assert_not_reached(); + } +} + +static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, TCGReg base, intptr_t ofs) { int rexw = 0; if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { - if (val != (int32_t)val) { + if (val != (int32_t) val) { return false; } rexw = P_REXW; @@ -1095,8 +1004,7 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, return true; } -static void tcg_out_shifti(TCGContext *s, int subopc, int reg, int count) -{ +static void tcg_out_shifti(TCGContext *s, int subopc, int reg, int count) { /* Propagate an opcode prefix, such as P_DATA16. */ int ext = subopc & ~0x7; subopc &= 0x7; @@ -1109,61 +1017,50 @@ static void tcg_out_shifti(TCGContext *s, int subopc, int reg, int count) } } -static inline void tcg_out_bswap32(TCGContext *s, int reg) -{ +static inline void tcg_out_bswap32(TCGContext *s, int reg) { tcg_out_opc(s, OPC_BSWAP + LOWREGMASK(reg), 0, reg, 0); } -static inline void tcg_out_rolw_8(TCGContext *s, int reg) -{ +static inline void tcg_out_rolw_8(TCGContext *s, int reg) { tcg_out_shifti(s, SHIFT_ROL + P_DATA16, reg, 8); } -static inline void tcg_out_ext8u(TCGContext *s, int dest, int src) -{ +static inline void tcg_out_ext8u(TCGContext *s, int dest, int src) { /* movzbl */ tcg_debug_assert(src < 4 || TCG_TARGET_REG_BITS == 64); tcg_out_modrm(s, OPC_MOVZBL + P_REXB_RM, dest, src); } -static void tcg_out_ext8s(TCGContext *s, int dest, int src, int rexw) -{ +static void tcg_out_ext8s(TCGContext *s, int dest, int src, int rexw) { /* movsbl */ tcg_debug_assert(src < 4 || TCG_TARGET_REG_BITS == 64); tcg_out_modrm(s, OPC_MOVSBL + P_REXB_RM + rexw, dest, src); } -static inline void tcg_out_ext16u(TCGContext *s, int dest, int src) -{ +static inline void tcg_out_ext16u(TCGContext *s, int dest, int src) { /* movzwl */ tcg_out_modrm(s, OPC_MOVZWL, dest, src); } -static inline void tcg_out_ext16s(TCGContext *s, int dest, int src, int rexw) -{ +static inline void tcg_out_ext16s(TCGContext *s, int dest, int src, int rexw) { /* movsw[lq] */ tcg_out_modrm(s, OPC_MOVSWL + rexw, dest, src); } -static inline void tcg_out_ext32u(TCGContext *s, int dest, int src) -{ +static inline void tcg_out_ext32u(TCGContext *s, int dest, int src) { /* 32-bit mov zero extends. */ tcg_out_modrm(s, OPC_MOVL_GvEv, dest, src); } -static inline void tcg_out_ext32s(TCGContext *s, int dest, int src) -{ +static inline void tcg_out_ext32s(TCGContext *s, int dest, int src) { tcg_out_modrm(s, OPC_MOVSLQ, dest, src); } -static inline void tcg_out_bswap64(TCGContext *s, int reg) -{ +static inline void tcg_out_bswap64(TCGContext *s, int reg) { tcg_out_opc(s, OPC_BSWAP + P_REXW + LOWREGMASK(reg), 0, reg, 0); } -static void tgen_arithi(TCGContext *s, int c, int r0, - tcg_target_long val, int cf) -{ +static void tgen_arithi(TCGContext *s, int c, int r0, tcg_target_long val, int cf) { int rexw = 0; if (TCG_TARGET_REG_BITS == 64) { @@ -1179,8 +1076,7 @@ static void tgen_arithi(TCGContext *s, int c, int r0, if (TCG_TARGET_REG_BITS == 64) { /* The single-byte increment encodings are re-tasked as the REX prefixes. Use the MODRM encoding. */ - tcg_out_modrm(s, OPC_GRP5 + rexw, - (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0); + tcg_out_modrm(s, OPC_GRP5 + rexw, (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0); } else { tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0); } @@ -1193,7 +1089,7 @@ static void tgen_arithi(TCGContext *s, int c, int r0, tcg_out_ext32u(s, r0, r0); return; } - if (val == (uint32_t)val) { + if (val == (uint32_t) val) { /* AND with no high bits set can use a 32-bit operation. */ rexw = 0; } @@ -1208,12 +1104,12 @@ static void tgen_arithi(TCGContext *s, int c, int r0, } } - if (val == (int8_t)val) { + if (val == (int8_t) val) { tcg_out_modrm(s, OPC_ARITH_EvIb + rexw, c, r0); tcg_out8(s, val); return; } - if (rexw == 0 || val == (int32_t)val) { + if (rexw == 0 || val == (int32_t) val) { tcg_out_modrm(s, OPC_ARITH_EvIz + rexw, c, r0); tcg_out32(s, val); return; @@ -1222,22 +1118,20 @@ static void tgen_arithi(TCGContext *s, int c, int r0, tcg_abort(); } -static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) -{ +static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) { if (val != 0) { tgen_arithi(s, ARITH_ADD + P_REXW, reg, val, 0); } } /* Use SMALL != 0 to force a short forward branch. */ -static void tcg_out_jxx(TCGContext *s, int opc, TCGLabel *l, int small) -{ +static void tcg_out_jxx(TCGContext *s, int opc, TCGLabel *l, int small) { int32_t val, val1; if (l->has_value) { val = tcg_pcrel_diff(s, l->u.value_ptr); val1 = val - 2; - if ((int8_t)val1 == val1) { + if ((int8_t) val1 == val1) { if (opc == -1) { tcg_out8(s, OPC_JMP_short); } else { @@ -1275,9 +1169,7 @@ static void tcg_out_jxx(TCGContext *s, int opc, TCGLabel *l, int small) } } -static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2, - int const_arg2, int rexw) -{ +static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2, int const_arg2, int rexw) { if (const_arg2) { if (arg2 == 0) { /* test r, r */ @@ -1290,142 +1182,109 @@ static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2, } } -static void tcg_out_brcond32(TCGContext *s, TCGCond cond, - TCGArg arg1, TCGArg arg2, int const_arg2, - TCGLabel *label, int small) -{ +static void tcg_out_brcond32(TCGContext *s, TCGCond cond, TCGArg arg1, TCGArg arg2, int const_arg2, TCGLabel *label, + int small) { tcg_out_cmp(s, arg1, arg2, const_arg2, 0); tcg_out_jxx(s, tcg_cond_to_jcc[cond], label, small); } #if TCG_TARGET_REG_BITS == 64 -static void tcg_out_brcond64(TCGContext *s, TCGCond cond, - TCGArg arg1, TCGArg arg2, int const_arg2, - TCGLabel *label, int small) -{ +static void tcg_out_brcond64(TCGContext *s, TCGCond cond, TCGArg arg1, TCGArg arg2, int const_arg2, TCGLabel *label, + int small) { tcg_out_cmp(s, arg1, arg2, const_arg2, P_REXW); tcg_out_jxx(s, tcg_cond_to_jcc[cond], label, small); } #else /* XXX: we implement it at the target level to avoid having to handle cross basic blocks temporaries */ -static void tcg_out_brcond2(TCGContext *s, const TCGArg *args, - const int *const_args, int small) -{ +static void tcg_out_brcond2(TCGContext *s, const TCGArg *args, const int *const_args, int small) { TCGLabel *label_next = gen_new_label(); TCGLabel *label_this = arg_label(args[5]); - switch(args[4]) { - case TCG_COND_EQ: - tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2], - label_next, 1); - tcg_out_brcond32(s, TCG_COND_EQ, args[1], args[3], const_args[3], - label_this, small); - break; - case TCG_COND_NE: - tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2], - label_this, small); - tcg_out_brcond32(s, TCG_COND_NE, args[1], args[3], const_args[3], - label_this, small); - break; - case TCG_COND_LT: - tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3], - label_this, small); - tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2], - label_this, small); - break; - case TCG_COND_LE: - tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3], - label_this, small); - tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2], - label_this, small); - break; - case TCG_COND_GT: - tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3], - label_this, small); - tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2], - label_this, small); - break; - case TCG_COND_GE: - tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3], - label_this, small); - tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2], - label_this, small); - break; - case TCG_COND_LTU: - tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3], - label_this, small); - tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2], - label_this, small); - break; - case TCG_COND_LEU: - tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3], - label_this, small); - tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2], - label_this, small); - break; - case TCG_COND_GTU: - tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3], - label_this, small); - tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2], - label_this, small); - break; - case TCG_COND_GEU: - tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3], - label_this, small); - tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2], - label_this, small); - break; - default: - tcg_abort(); + switch (args[4]) { + case TCG_COND_EQ: + tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2], label_next, 1); + tcg_out_brcond32(s, TCG_COND_EQ, args[1], args[3], const_args[3], label_this, small); + break; + case TCG_COND_NE: + tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2], label_this, small); + tcg_out_brcond32(s, TCG_COND_NE, args[1], args[3], const_args[3], label_this, small); + break; + case TCG_COND_LT: + tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3], label_this, small); + tcg_out_jxx(s, JCC_JNE, label_next, 1); + tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2], label_this, small); + break; + case TCG_COND_LE: + tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3], label_this, small); + tcg_out_jxx(s, JCC_JNE, label_next, 1); + tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2], label_this, small); + break; + case TCG_COND_GT: + tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3], label_this, small); + tcg_out_jxx(s, JCC_JNE, label_next, 1); + tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2], label_this, small); + break; + case TCG_COND_GE: + tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3], label_this, small); + tcg_out_jxx(s, JCC_JNE, label_next, 1); + tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2], label_this, small); + break; + case TCG_COND_LTU: + tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3], label_this, small); + tcg_out_jxx(s, JCC_JNE, label_next, 1); + tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2], label_this, small); + break; + case TCG_COND_LEU: + tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3], label_this, small); + tcg_out_jxx(s, JCC_JNE, label_next, 1); + tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2], label_this, small); + break; + case TCG_COND_GTU: + tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3], label_this, small); + tcg_out_jxx(s, JCC_JNE, label_next, 1); + tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2], label_this, small); + break; + case TCG_COND_GEU: + tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3], label_this, small); + tcg_out_jxx(s, JCC_JNE, label_next, 1); + tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2], label_this, small); + break; + default: + tcg_abort(); } tcg_out_label(s, label_next, s->code_ptr); } #endif -static void tcg_out_setcond32(TCGContext *s, TCGCond cond, TCGArg dest, - TCGArg arg1, TCGArg arg2, int const_arg2) -{ +static void tcg_out_setcond32(TCGContext *s, TCGCond cond, TCGArg dest, TCGArg arg1, TCGArg arg2, int const_arg2) { tcg_out_cmp(s, arg1, arg2, const_arg2, 0); tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest); tcg_out_ext8u(s, dest, dest); } #if TCG_TARGET_REG_BITS == 64 -static void tcg_out_setcond64(TCGContext *s, TCGCond cond, TCGArg dest, - TCGArg arg1, TCGArg arg2, int const_arg2) -{ +static void tcg_out_setcond64(TCGContext *s, TCGCond cond, TCGArg dest, TCGArg arg1, TCGArg arg2, int const_arg2) { tcg_out_cmp(s, arg1, arg2, const_arg2, P_REXW); tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest); tcg_out_ext8u(s, dest, dest); } #else -static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, - const int *const_args) -{ +static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, const int *const_args) { TCGArg new_args[6]; TCGLabel *label_true, *label_over; - memcpy(new_args, args+1, 5*sizeof(TCGArg)); + memcpy(new_args, args + 1, 5 * sizeof(TCGArg)); - if (args[0] == args[1] || args[0] == args[2] - || (!const_args[3] && args[0] == args[3]) - || (!const_args[4] && args[0] == args[4])) { + if (args[0] == args[1] || args[0] == args[2] || (!const_args[3] && args[0] == args[3]) || + (!const_args[4] && args[0] == args[4])) { /* When the destination overlaps with one of the argument registers, don't do anything tricky. */ label_true = gen_new_label(); label_over = gen_new_label(); new_args[5] = label_arg(label_true); - tcg_out_brcond2(s, new_args, const_args+1, 1); + tcg_out_brcond2(s, new_args, const_args + 1, 1); tcg_out_movi(s, TCG_TYPE_I32, args[0], 0); tcg_out_jxx(s, JCC_JMP, label_over, 1); @@ -1443,7 +1302,7 @@ static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, label_over = gen_new_label(); new_args[4] = tcg_invert_cond(new_args[4]); new_args[5] = label_arg(label_over); - tcg_out_brcond2(s, new_args, const_args+1, 1); + tcg_out_brcond2(s, new_args, const_args + 1, 1); tgen_arithi(s, ARITH_ADD, args[0], 1, 0); tcg_out_label(s, label_over, s->code_ptr); @@ -1451,9 +1310,7 @@ static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, } #endif -static void tcg_out_cmov(TCGContext *s, TCGCond cond, int rexw, - TCGReg dest, TCGReg v1) -{ +static void tcg_out_cmov(TCGContext *s, TCGCond cond, int rexw, TCGReg dest, TCGReg v1) { if (have_cmov) { tcg_out_modrm(s, OPC_CMOVCC | tcg_cond_to_jcc[cond] | rexw, dest, v1); } else { @@ -1464,27 +1321,19 @@ static void tcg_out_cmov(TCGContext *s, TCGCond cond, int rexw, } } -static void tcg_out_movcond32(TCGContext *s, TCGCond cond, TCGReg dest, - TCGReg c1, TCGArg c2, int const_c2, - TCGReg v1) -{ +static void tcg_out_movcond32(TCGContext *s, TCGCond cond, TCGReg dest, TCGReg c1, TCGArg c2, int const_c2, TCGReg v1) { tcg_out_cmp(s, c1, c2, const_c2, 0); tcg_out_cmov(s, cond, 0, dest, v1); } #if TCG_TARGET_REG_BITS == 64 -static void tcg_out_movcond64(TCGContext *s, TCGCond cond, TCGReg dest, - TCGReg c1, TCGArg c2, int const_c2, - TCGReg v1) -{ +static void tcg_out_movcond64(TCGContext *s, TCGCond cond, TCGReg dest, TCGReg c1, TCGArg c2, int const_c2, TCGReg v1) { tcg_out_cmp(s, c1, c2, const_c2, P_REXW); tcg_out_cmov(s, cond, P_REXW, dest, v1); } #endif -static void tcg_out_ctz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, - TCGArg arg2, bool const_a2) -{ +static void tcg_out_ctz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, TCGArg arg2, bool const_a2) { if (have_bmi1) { tcg_out_modrm(s, OPC_TZCNT + rexw, dest, arg1); if (const_a2) { @@ -1500,9 +1349,7 @@ static void tcg_out_ctz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, } } -static void tcg_out_clz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, - TCGArg arg2, bool const_a2) -{ +static void tcg_out_clz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, TCGArg arg2, bool const_a2) { if (have_lzcnt) { tcg_out_modrm(s, OPC_LZCNT + rexw, dest, arg1); if (const_a2) { @@ -1526,11 +1373,10 @@ static void tcg_out_clz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, } } -static void tcg_out_branch(TCGContext *s, int call, tcg_insn_unit *dest) -{ +static void tcg_out_branch(TCGContext *s, int call, tcg_insn_unit *dest) { intptr_t disp = tcg_pcrel_diff(s, dest) - 5; - if (disp == (int32_t)disp) { + if (disp == (int32_t) disp) { tcg_out_opc(s, call ? OPC_CALL_Jz : OPC_JMP_long, 0, 0, 0); tcg_out32(s, disp); } else { @@ -1540,23 +1386,20 @@ static void tcg_out_branch(TCGContext *s, int call, tcg_insn_unit *dest) be able to re-use the pool constant for more calls. */ tcg_out_opc(s, OPC_GRP5, 0, 0, 0); tcg_out8(s, (call ? EXT5_CALLN_Ev : EXT5_JMPN_Ev) << 3 | 5); - new_pool_label(s, (uintptr_t)dest, R_386_PC32, s->code_ptr, -4); + new_pool_label(s, (uintptr_t) dest, R_386_PC32, s->code_ptr, -4); tcg_out32(s, 0); } } -static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) -{ +static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) { tcg_out_branch(s, 1, dest); } -static void tcg_out_jmp(TCGContext *s, tcg_insn_unit *dest) -{ +static void tcg_out_jmp(TCGContext *s, tcg_insn_unit *dest) { tcg_out_branch(s, 0, dest); } -static void tcg_out_nopn(TCGContext *s, int n) -{ +static void tcg_out_nopn(TCGContext *s, int n) { int i; /* Emit 1 or 2 operand size prefixes for the standard one byte nop, * "xchg %eax,%eax", forming "xchg %ax,%ax". All cores accept the @@ -1594,10 +1437,8 @@ static void tcg_out_nopn(TCGContext *s, int n) First argument register is clobbered. */ -static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, - int mem_index, TCGMemOp opc, - tcg_insn_unit **label_ptr, int which) -{ +static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, int mem_index, TCGMemOp opc, + tcg_insn_unit **label_ptr, int which) { const TCGReg r0 = TCG_REG_L0; const TCGReg r1 = TCG_REG_L1; TCGType ttype = TCG_TYPE_I32; @@ -1624,14 +1465,11 @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, } tcg_out_mov(s, tlbtype, r0, addrlo); - tcg_out_shifti(s, SHIFT_SHR + tlbrexw, r0, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + tcg_out_shifti(s, SHIFT_SHR + tlbrexw, r0, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0, - get_cpu_arch_tlb_mask_offset(mem_index)); + tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0, get_cpu_arch_tlb_mask_offset(mem_index)); - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0, - s->env_offset_tlb[mem_index]); + tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0, s->env_offset_tlb[mem_index]); /* If the required alignment is at least as large as the access, simply copy the address and mask. For lesser alignments, check that we don't @@ -1641,7 +1479,7 @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, } else { tcg_out_modrm_offset(s, OPC_LEA + trexw, r1, addrlo, s_mask - a_mask); } - tlb_mask = (target_ulong)TARGET_PAGE_MASK | a_mask; + tlb_mask = (target_ulong) TARGET_PAGE_MASK | a_mask; tgen_arithi(s, ARITH_AND + trexw, r1, tlb_mask, 0); /* cmp 0(r0), r1 */ @@ -1669,22 +1507,15 @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, /* TLB Hit. */ /* add addend(r0), r1 */ - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0, - g_tcg_settings.tlb_entry_addend_offset); + tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0, g_tcg_settings.tlb_entry_addend_offset); } - /* * Record the context of a call to the out of line helper code for the slow path * for a load or store, so that we can later generate the correct helper code */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64, - TCGMemOpIdx oi, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addrhi, - tcg_insn_unit *raddr, - tcg_insn_unit **label_ptr) -{ +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64, TCGMemOpIdx oi, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, tcg_insn_unit *raddr, tcg_insn_unit **label_ptr) { TCGLabelQemuLdst *label = new_ldst_label(s); label->is_ld = is_ld; @@ -1704,8 +1535,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64, /* * Generate code for the slow path for a load at the end of block */ -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ +static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { TCGMemOpIdx oi = l->oi; TCGMemOp opc = get_memop(oi); TCGReg data_reg; @@ -1735,53 +1565,52 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs); ofs += 4; - tcg_out_sti(s, TCG_TYPE_PTR, (uintptr_t)l->raddr, TCG_REG_ESP, ofs); + tcg_out_sti(s, TCG_TYPE_PTR, (uintptr_t) l->raddr, TCG_REG_ESP, ofs); } else { tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); /* The second argument is already loaded with addrlo. */ tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], oi); - tcg_out_movi(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[3], - (uintptr_t)l->raddr); + tcg_out_movi(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[3], (uintptr_t) l->raddr); } tcg_out_call(s, s->qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); data_reg = l->datalo_reg; switch (opc & MO_SSIZE) { - case MO_SB: - tcg_out_ext8s(s, data_reg, TCG_REG_EAX, rexw); - break; - case MO_SW: - tcg_out_ext16s(s, data_reg, TCG_REG_EAX, rexw); - break; + case MO_SB: + tcg_out_ext8s(s, data_reg, TCG_REG_EAX, rexw); + break; + case MO_SW: + tcg_out_ext16s(s, data_reg, TCG_REG_EAX, rexw); + break; #if TCG_TARGET_REG_BITS == 64 - case MO_SL: - tcg_out_ext32s(s, data_reg, TCG_REG_EAX); - break; + case MO_SL: + tcg_out_ext32s(s, data_reg, TCG_REG_EAX); + break; #endif - case MO_UB: - tcg_out_ext8u(s, data_reg, TCG_REG_EAX); - break; - case MO_UW: - tcg_out_ext16u(s, data_reg, TCG_REG_EAX); - break; - case MO_UL: - tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); - break; - case MO_Q: - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX); - } else if (data_reg == TCG_REG_EDX) { - /* xchg %edx, %eax */ - tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX, 0, 0, 0); - tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EAX); - } else { + case MO_UB: + tcg_out_ext8u(s, data_reg, TCG_REG_EAX); + break; + case MO_UW: + tcg_out_ext16u(s, data_reg, TCG_REG_EAX); + break; + case MO_UL: tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); - tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EDX); - } - break; - default: - tcg_abort(); + break; + case MO_Q: + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX); + } else if (data_reg == TCG_REG_EDX) { + /* xchg %edx, %eax */ + tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX, 0, 0, 0); + tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EAX); + } else { + tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); + tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EDX); + } + break; + default: + tcg_abort(); } /* Jump to the code corresponding to next IR of qemu_st */ @@ -1791,8 +1620,7 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) /* * Generate code for the slow path for a store at the end of block */ -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ +static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { TCGMemOpIdx oi = l->oi; TCGMemOp opc = get_memop(oi); TCGMemOp s_bits = opc & MO_SIZE; @@ -1831,23 +1659,21 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) ofs += 4; retaddr = TCG_REG_EAX; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); + tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t) l->raddr); tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, ofs); } else { tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); /* The second argument is already loaded with addrlo. */ - tcg_out_mov(s, (s_bits == MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - tcg_target_call_iarg_regs[2], l->datalo_reg); + tcg_out_mov(s, (s_bits == MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), tcg_target_call_iarg_regs[2], l->datalo_reg); tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], oi); if (ARRAY_SIZE(tcg_target_call_iarg_regs) > 4) { retaddr = tcg_target_call_iarg_regs[4]; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); + tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t) l->raddr); } else { retaddr = TCG_REG_RAX; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, - TCG_TARGET_CALL_STACK_OFFSET); + tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t) l->raddr); + tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, TCG_TARGET_CALL_STACK_OFFSET); } } @@ -1856,45 +1682,40 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) tcg_out_jmp(s, s->qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); } #elif TCG_TARGET_REG_BITS == 32 -# define x86_guest_base_seg 0 -# define x86_guest_base_index -1 -# define x86_guest_base_offset guest_base +#define x86_guest_base_seg 0 +#define x86_guest_base_index -1 +#define x86_guest_base_offset guest_base #else static int x86_guest_base_seg; static int x86_guest_base_index = -1; static int32_t x86_guest_base_offset; -# if defined(__x86_64__) && defined(__linux__) -# include -# include +#if defined(__x86_64__) && defined(__linux__) +#include +#include int arch_prctl(int code, unsigned long addr); -static inline int setup_guest_base_seg(void) -{ +static inline int setup_guest_base_seg(void) { if (arch_prctl(ARCH_SET_GS, guest_base) == 0) { return P_GS; } return 0; } -# elif defined (__FreeBSD__) || defined (__FreeBSD_kernel__) -# include -static inline int setup_guest_base_seg(void) -{ +#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) +#include +static inline int setup_guest_base_seg(void) { if (sysarch(AMD64_SET_GSBASE, &guest_base) == 0) { return P_GS; } return 0; } -# else -static inline int setup_guest_base_seg(void) -{ +#else +static inline int setup_guest_base_seg(void) { return 0; } -# endif +#endif #endif /* SOFTMMU */ -static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, - TCGReg base, int index, intptr_t ofs, - int seg, bool is64, TCGMemOp memop) -{ +static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg base, int index, intptr_t ofs, + int seg, bool is64, TCGMemOp memop) { const TCGMemOp real_bswap = memop & MO_BSWAP; TCGMemOp bswap = real_bswap; int rexw = is64 * P_REXW; @@ -1906,98 +1727,84 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, } switch (memop & MO_SSIZE) { - case MO_UB: - tcg_out_modrm_sib_offset(s, OPC_MOVZBL + seg, datalo, - base, index, 0, ofs); - break; - case MO_SB: - tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + seg, datalo, - base, index, 0, ofs); - break; - case MO_UW: - tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, - base, index, 0, ofs); - if (real_bswap) { - tcg_out_rolw_8(s, datalo); - } - break; - case MO_SW: - if (real_bswap) { - if (have_movbe) { - tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, - datalo, base, index, 0, ofs); - } else { - tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, - base, index, 0, ofs); + case MO_UB: + tcg_out_modrm_sib_offset(s, OPC_MOVZBL + seg, datalo, base, index, 0, ofs); + break; + case MO_SB: + tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + seg, datalo, base, index, 0, ofs); + break; + case MO_UW: + tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, base, index, 0, ofs); + if (real_bswap) { tcg_out_rolw_8(s, datalo); } - tcg_out_modrm(s, OPC_MOVSWL + rexw, datalo, datalo); - } else { - tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + seg, - datalo, base, index, 0, ofs); - } - break; - case MO_UL: - tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); - if (bswap) { - tcg_out_bswap32(s, datalo); - } - break; -#if TCG_TARGET_REG_BITS == 64 - case MO_SL: - if (real_bswap) { - tcg_out_modrm_sib_offset(s, movop + seg, datalo, - base, index, 0, ofs); - if (bswap) { - tcg_out_bswap32(s, datalo); + break; + case MO_SW: + if (real_bswap) { + if (have_movbe) { + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, datalo, base, index, 0, ofs); + } else { + tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, base, index, 0, ofs); + tcg_out_rolw_8(s, datalo); + } + tcg_out_modrm(s, OPC_MOVSWL + rexw, datalo, datalo); + } else { + tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + seg, datalo, base, index, 0, ofs); } - tcg_out_ext32s(s, datalo, datalo); - } else { - tcg_out_modrm_sib_offset(s, OPC_MOVSLQ + seg, datalo, - base, index, 0, ofs); - } - break; -#endif - case MO_Q: - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, - base, index, 0, ofs); + break; + case MO_UL: + tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); if (bswap) { - tcg_out_bswap64(s, datalo); + tcg_out_bswap32(s, datalo); } - } else { + break; +#if TCG_TARGET_REG_BITS == 64 + case MO_SL: if (real_bswap) { - int t = datalo; - datalo = datahi; - datahi = t; - } - if (base != datalo) { - tcg_out_modrm_sib_offset(s, movop + seg, datalo, - base, index, 0, ofs); - tcg_out_modrm_sib_offset(s, movop + seg, datahi, - base, index, 0, ofs + 4); + tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); + if (bswap) { + tcg_out_bswap32(s, datalo); + } + tcg_out_ext32s(s, datalo, datalo); } else { - tcg_out_modrm_sib_offset(s, movop + seg, datahi, - base, index, 0, ofs + 4); - tcg_out_modrm_sib_offset(s, movop + seg, datalo, - base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVSLQ + seg, datalo, base, index, 0, ofs); } - if (bswap) { - tcg_out_bswap32(s, datalo); - tcg_out_bswap32(s, datahi); + break; +#endif + case MO_Q: + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, base, index, 0, ofs); + if (bswap) { + tcg_out_bswap64(s, datalo); + } + } else { + if (real_bswap) { + int t = datalo; + datalo = datahi; + datahi = t; + } + if (base != datalo) { + tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, movop + seg, datahi, base, index, 0, ofs + 4); + } else { + tcg_out_modrm_sib_offset(s, movop + seg, datahi, base, index, 0, ofs + 4); + tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); + } + if (bswap) { + tcg_out_bswap32(s, datalo); + tcg_out_bswap32(s, datahi); + } } - } - break; - default: - tcg_abort(); + break; + default: + tcg_abort(); } } /* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and EAX. It will be useful once fixed registers globals are less common. */ -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) -{ +static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) { TCGReg datalo, datahi, addrlo; TCGReg addrhi __attribute__((unused)); TCGMemOpIdx oi; @@ -2017,26 +1824,21 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) #if defined(CONFIG_SOFTMMU) mem_index = get_mmuidx(oi); - tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, - label_ptr, g_tcg_settings.tlb_entry_addr_read_offset); + tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, label_ptr, g_tcg_settings.tlb_entry_addr_read_offset); /* TLB Hit. */ tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, is64, opc); /* Record the current context of a load into ldst label */ - add_qemu_ldst_label(s, true, is64, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, true, is64, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); #else - tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index, - x86_guest_base_offset, x86_guest_base_seg, + tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index, x86_guest_base_offset, x86_guest_base_seg, is64, opc); #endif } -static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, - TCGReg base, int index, intptr_t ofs, - int seg, TCGMemOp memop) -{ +static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg base, int index, intptr_t ofs, + int seg, TCGMemOp memop) { /* ??? Ideally we wouldn't need a scratch register. For user-only, we could perform the bswap twice to restore the original value instead of moving to the scratch. But as it is, the L constraint @@ -2052,70 +1854,62 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, } switch (memop & MO_SIZE) { - case MO_8: - /* In 32-bit mode, 8-bit stores can only happen from [abcd]x. - Use the scratch register if necessary. */ - if (TCG_TARGET_REG_BITS == 32 && datalo >= 4) { - tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); - datalo = scratch; - } - tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg, - datalo, base, index, 0, ofs); - break; - case MO_16: - if (bswap) { - tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); - tcg_out_rolw_8(s, scratch); - datalo = scratch; - } - tcg_out_modrm_sib_offset(s, movop + P_DATA16 + seg, datalo, - base, index, 0, ofs); - break; - case MO_32: - if (bswap) { - tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); - tcg_out_bswap32(s, scratch); - datalo = scratch; - } - tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); - break; - case MO_64: - if (TCG_TARGET_REG_BITS == 64) { + case MO_8: + /* In 32-bit mode, 8-bit stores can only happen from [abcd]x. + Use the scratch register if necessary. */ + if (TCG_TARGET_REG_BITS == 32 && datalo >= 4) { + tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); + datalo = scratch; + } + tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg, datalo, base, index, 0, ofs); + break; + case MO_16: if (bswap) { - tcg_out_mov(s, TCG_TYPE_I64, scratch, datalo); - tcg_out_bswap64(s, scratch); + tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); + tcg_out_rolw_8(s, scratch); datalo = scratch; } - tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, - base, index, 0, ofs); - } else if (bswap) { - tcg_out_mov(s, TCG_TYPE_I32, scratch, datahi); - tcg_out_bswap32(s, scratch); - tcg_out_modrm_sib_offset(s, OPC_MOVL_EvGv + seg, scratch, - base, index, 0, ofs); - tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); - tcg_out_bswap32(s, scratch); - tcg_out_modrm_sib_offset(s, OPC_MOVL_EvGv + seg, scratch, - base, index, 0, ofs + 4); - } else { - if (real_bswap) { - int t = datalo; - datalo = datahi; - datahi = t; - } - tcg_out_modrm_sib_offset(s, movop + seg, datalo, - base, index, 0, ofs); - tcg_out_modrm_sib_offset(s, movop + seg, datahi, - base, index, 0, ofs + 4); - } - break; - default: - tcg_abort(); + tcg_out_modrm_sib_offset(s, movop + P_DATA16 + seg, datalo, base, index, 0, ofs); + break; + case MO_32: + if (bswap) { + tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); + tcg_out_bswap32(s, scratch); + datalo = scratch; + } + tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); + break; + case MO_64: + if (TCG_TARGET_REG_BITS == 64) { + if (bswap) { + tcg_out_mov(s, TCG_TYPE_I64, scratch, datalo); + tcg_out_bswap64(s, scratch); + datalo = scratch; + } + tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, base, index, 0, ofs); + } else if (bswap) { + tcg_out_mov(s, TCG_TYPE_I32, scratch, datahi); + tcg_out_bswap32(s, scratch); + tcg_out_modrm_sib_offset(s, OPC_MOVL_EvGv + seg, scratch, base, index, 0, ofs); + tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); + tcg_out_bswap32(s, scratch); + tcg_out_modrm_sib_offset(s, OPC_MOVL_EvGv + seg, scratch, base, index, 0, ofs + 4); + } else { + if (real_bswap) { + int t = datalo; + datalo = datahi; + datahi = t; + } + tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, movop + seg, datahi, base, index, 0, ofs + 4); + } + break; + default: + tcg_abort(); } } -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) -{ +static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) { TCGReg datalo, datahi, addrlo; TCGReg addrhi __attribute__((unused)); TCGMemOpIdx oi; @@ -2135,35 +1929,30 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) #if defined(CONFIG_SOFTMMU) mem_index = get_mmuidx(oi); - tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, - label_ptr, g_tcg_settings.tlb_entry_addr_write_offset); + tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, label_ptr, g_tcg_settings.tlb_entry_addr_write_offset); /* TLB Hit. */ tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc); /* Record the current context of a store into ldst label */ - add_qemu_ldst_label(s, false, is64, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, false, is64, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); #else - tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, x86_guest_base_index, - x86_guest_base_offset, x86_guest_base_seg, opc); + tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, x86_guest_base_index, x86_guest_base_offset, x86_guest_base_seg, + opc); #endif } -static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) -{ +static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { TCGArg a0, a1, a2; int c, const_a2, vexop, rexw = 0; #if TCG_TARGET_REG_BITS == 64 -# define OP_32_64(x) \ - case glue(glue(INDEX_op_, x), _i64): \ - rexw = P_REXW; /* FALLTHRU */ \ - case glue(glue(INDEX_op_, x), _i32) +#define OP_32_64(x) \ + case glue(glue(INDEX_op_, x), _i64): \ + rexw = P_REXW; /* FALLTHRU */ \ + case glue(glue(INDEX_op_, x), _i32) #else -# define OP_32_64(x) \ - case glue(glue(INDEX_op_, x), _i32) +#define OP_32_64(x) case glue(glue(INDEX_op_, x), _i32) #endif /* Hoist the loads of the most common arguments. */ @@ -2173,473 +1962,411 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const_a2 = const_args[2]; switch (opc) { - case INDEX_op_exit_tb: - /* Reuse the zeroing that exists for goto_ptr. */ - if (a0 == 0) { - tcg_out_jmp(s, s->code_gen_epilogue); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_EAX, a0); - tcg_out_jmp(s, tb_ret_addr); - } - break; - case INDEX_op_goto_tb: - if (s->tb_jmp_insn_offset) { - /* direct jump method */ - int gap; - /* jump displacement must be aligned for atomic patching; - * see if we need to add extra nops before jump - */ - gap = tcg_pcrel_diff(s, ALIGN_PTR_UP(s->code_ptr + 1, 4)); - if (gap != 1) { - tcg_out_nopn(s, gap - 1); + case INDEX_op_exit_tb: + /* Reuse the zeroing that exists for goto_ptr. */ + if (a0 == 0) { + tcg_out_jmp(s, s->code_gen_epilogue); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_EAX, a0); + tcg_out_jmp(s, tb_ret_addr); } - tcg_out8(s, OPC_JMP_long); /* jmp im */ - s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); - tcg_out32(s, 0); - } else { - /* indirect jump method */ - tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, -1, - (intptr_t)(s->tb_jmp_target_addr + a0)); - } - set_jmp_reset_offset(s, a0); - break; - case INDEX_op_goto_ptr: - /* jmp to the given host address (could be epilogue) */ - tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, a0); - break; - case INDEX_op_br: - tcg_out_jxx(s, JCC_JMP, arg_label(a0), 0); - break; - OP_32_64(ld8u): - /* Note that we can ignore REXW for the zero-extend to 64-bit. */ - tcg_out_modrm_offset(s, OPC_MOVZBL, a0, a1, a2); - break; - OP_32_64(ld8s): - tcg_out_modrm_offset(s, OPC_MOVSBL + rexw, a0, a1, a2); - break; - OP_32_64(ld16u): - /* Note that we can ignore REXW for the zero-extend to 64-bit. */ - tcg_out_modrm_offset(s, OPC_MOVZWL, a0, a1, a2); - break; - OP_32_64(ld16s): - tcg_out_modrm_offset(s, OPC_MOVSWL + rexw, a0, a1, a2); - break; + break; + case INDEX_op_goto_tb: + if (s->tb_jmp_insn_offset) { + /* direct jump method */ + int gap; + /* jump displacement must be aligned for atomic patching; + * see if we need to add extra nops before jump + */ + gap = tcg_pcrel_diff(s, ALIGN_PTR_UP(s->code_ptr + 1, 4)); + if (gap != 1) { + tcg_out_nopn(s, gap - 1); + } + tcg_out8(s, OPC_JMP_long); /* jmp im */ + s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); + tcg_out32(s, 0); + } else { + /* indirect jump method */ + tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, -1, (intptr_t)(s->tb_jmp_target_addr + a0)); + } + set_jmp_reset_offset(s, a0); + break; + case INDEX_op_goto_ptr: + /* jmp to the given host address (could be epilogue) */ + tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, a0); + break; + case INDEX_op_br: + tcg_out_jxx(s, JCC_JMP, arg_label(a0), 0); + break; + OP_32_64(ld8u) + : /* Note that we can ignore REXW for the zero-extend to 64-bit. */ + tcg_out_modrm_offset(s, OPC_MOVZBL, a0, a1, a2); + break; + OP_32_64(ld8s) : tcg_out_modrm_offset(s, OPC_MOVSBL + rexw, a0, a1, a2); + break; + OP_32_64(ld16u) + : /* Note that we can ignore REXW for the zero-extend to 64-bit. */ + tcg_out_modrm_offset(s, OPC_MOVZWL, a0, a1, a2); + break; + OP_32_64(ld16s) : tcg_out_modrm_offset(s, OPC_MOVSWL + rexw, a0, a1, a2); + break; #if TCG_TARGET_REG_BITS == 64 - case INDEX_op_ld32u_i64: + case INDEX_op_ld32u_i64: #endif - case INDEX_op_ld_i32: - tcg_out_ld(s, TCG_TYPE_I32, a0, a1, a2); - break; - - OP_32_64(st8): - if (const_args[0]) { - tcg_out_modrm_offset(s, OPC_MOVB_EvIz, 0, a1, a2); - tcg_out8(s, a0); - } else { - tcg_out_modrm_offset(s, OPC_MOVB_EvGv | P_REXB_R, a0, a1, a2); - } - break; - OP_32_64(st16): - if (const_args[0]) { - tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_DATA16, 0, a1, a2); - tcg_out16(s, a0); - } else { - tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_DATA16, a0, a1, a2); - } - break; + case INDEX_op_ld_i32: + tcg_out_ld(s, TCG_TYPE_I32, a0, a1, a2); + break; + + OP_32_64(st8) : if (const_args[0]) { + tcg_out_modrm_offset(s, OPC_MOVB_EvIz, 0, a1, a2); + tcg_out8(s, a0); + } + else { + tcg_out_modrm_offset(s, OPC_MOVB_EvGv | P_REXB_R, a0, a1, a2); + } + break; + OP_32_64(st16) : if (const_args[0]) { + tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_DATA16, 0, a1, a2); + tcg_out16(s, a0); + } + else { + tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_DATA16, a0, a1, a2); + } + break; #if TCG_TARGET_REG_BITS == 64 - case INDEX_op_st32_i64: + case INDEX_op_st32_i64: #endif - case INDEX_op_st_i32: - if (const_args[0]) { - tcg_out_modrm_offset(s, OPC_MOVL_EvIz, 0, a1, a2); - tcg_out32(s, a0); - } else { - tcg_out_st(s, TCG_TYPE_I32, a0, a1, a2); - } - break; + case INDEX_op_st_i32: + if (const_args[0]) { + tcg_out_modrm_offset(s, OPC_MOVL_EvIz, 0, a1, a2); + tcg_out32(s, a0); + } else { + tcg_out_st(s, TCG_TYPE_I32, a0, a1, a2); + } + break; - OP_32_64(add): - /* For 3-operand addition, use LEA. */ - if (a0 != a1) { - TCGArg c3 = 0; - if (const_a2) { - c3 = a2, a2 = -1; - } else if (a0 == a2) { - /* Watch out for dest = src + dest, since we've removed - the matching constraint on the add. */ - tgen_arithr(s, ARITH_ADD + rexw, a0, a1); + OP_32_64(add) + : /* For 3-operand addition, use LEA. */ + if (a0 != a1) { + TCGArg c3 = 0; + if (const_a2) { + c3 = a2, a2 = -1; + } else if (a0 == a2) { + /* Watch out for dest = src + dest, since we've removed + the matching constraint on the add. */ + tgen_arithr(s, ARITH_ADD + rexw, a0, a1); + break; + } + + tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a2, 0, c3); break; } + c = ARITH_ADD; + goto gen_arith; + OP_32_64(sub) : c = ARITH_SUB; + goto gen_arith; + OP_32_64(and) : c = ARITH_AND; + goto gen_arith; + OP_32_64(or) : c = ARITH_OR; + goto gen_arith; + OP_32_64 (xor) : c = ARITH_XOR; + goto gen_arith; + gen_arith: + if (const_a2) { + tgen_arithi(s, c + rexw, a0, a2, 0); + } else { + tgen_arithr(s, c + rexw, a0, a2); + } + break; - tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a2, 0, c3); + OP_32_64(andc) : if (const_a2) { + tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1); + tgen_arithi(s, ARITH_AND + rexw, a0, ~a2, 0); + } + else { + tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1); + } break; - } - c = ARITH_ADD; - goto gen_arith; - OP_32_64(sub): - c = ARITH_SUB; - goto gen_arith; - OP_32_64(and): - c = ARITH_AND; - goto gen_arith; - OP_32_64(or): - c = ARITH_OR; - goto gen_arith; - OP_32_64(xor): - c = ARITH_XOR; - goto gen_arith; - gen_arith: - if (const_a2) { - tgen_arithi(s, c + rexw, a0, a2, 0); - } else { - tgen_arithr(s, c + rexw, a0, a2); - } - break; - OP_32_64(andc): - if (const_a2) { - tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1); - tgen_arithi(s, ARITH_AND + rexw, a0, ~a2, 0); - } else { - tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1); - } - break; + OP_32_64(mul) : if (const_a2) { + int32_t val; + val = a2; + if (val == (int8_t) val) { + tcg_out_modrm(s, OPC_IMUL_GvEvIb + rexw, a0, a0); + tcg_out8(s, val); + } else { + tcg_out_modrm(s, OPC_IMUL_GvEvIz + rexw, a0, a0); + tcg_out32(s, val); + } + } + else { + tcg_out_modrm(s, OPC_IMUL_GvEv + rexw, a0, a2); + } + break; - OP_32_64(mul): - if (const_a2) { - int32_t val; - val = a2; - if (val == (int8_t)val) { - tcg_out_modrm(s, OPC_IMUL_GvEvIb + rexw, a0, a0); - tcg_out8(s, val); + OP_32_64(div2) : tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IDIV, args[4]); + break; + OP_32_64(divu2) : tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_DIV, args[4]); + break; + + OP_32_64(shl) + : /* For small constant 3-operand shift, use LEA. */ + if (const_a2 && a0 != a1 && (a2 - 1) < 3) { + if (a2 - 1 == 0) { + /* shl $1,a1,a0 -> lea (a1,a1),a0 */ + tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a1, 0, 0); + } else { + /* shl $n,a1,a0 -> lea 0(,a1,n),a0 */ + tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, -1, a1, a2, 0); + } + break; + } + c = SHIFT_SHL; + vexop = OPC_SHLX; + goto gen_shift_maybe_vex; + OP_32_64(shr) : c = SHIFT_SHR; + vexop = OPC_SHRX; + goto gen_shift_maybe_vex; + OP_32_64(sar) : c = SHIFT_SAR; + vexop = OPC_SARX; + goto gen_shift_maybe_vex; + OP_32_64(rotl) : c = SHIFT_ROL; + goto gen_shift; + OP_32_64(rotr) : c = SHIFT_ROR; + goto gen_shift; + gen_shift_maybe_vex: + if (have_bmi2) { + if (!const_a2) { + tcg_out_vex_modrm(s, vexop + rexw, a0, a2, a1); + break; + } + tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1); + } + /* FALLTHRU */ + gen_shift: + if (const_a2) { + tcg_out_shifti(s, c + rexw, a0, a2); } else { - tcg_out_modrm(s, OPC_IMUL_GvEvIz + rexw, a0, a0); - tcg_out32(s, val); + tcg_out_modrm(s, OPC_SHIFT_cl + rexw, c, a0); } - } else { - tcg_out_modrm(s, OPC_IMUL_GvEv + rexw, a0, a2); - } - break; - - OP_32_64(div2): - tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IDIV, args[4]); - break; - OP_32_64(divu2): - tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_DIV, args[4]); - break; - - OP_32_64(shl): - /* For small constant 3-operand shift, use LEA. */ - if (const_a2 && a0 != a1 && (a2 - 1) < 3) { - if (a2 - 1 == 0) { - /* shl $1,a1,a0 -> lea (a1,a1),a0 */ - tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a1, 0, 0); + break; + + OP_32_64(ctz) : tcg_out_ctz(s, rexw, args[0], args[1], args[2], const_args[2]); + break; + OP_32_64(clz) : tcg_out_clz(s, rexw, args[0], args[1], args[2], const_args[2]); + break; + OP_32_64(ctpop) : tcg_out_modrm(s, OPC_POPCNT + rexw, a0, a1); + break; + + case INDEX_op_brcond_i32: + tcg_out_brcond32(s, a2, a0, a1, const_args[1], arg_label(args[3]), 0); + break; + case INDEX_op_setcond_i32: + tcg_out_setcond32(s, args[3], a0, a1, a2, const_a2); + break; + case INDEX_op_movcond_i32: + tcg_out_movcond32(s, args[5], a0, a1, a2, const_a2, args[3]); + break; + + OP_32_64(bswap16) : tcg_out_rolw_8(s, a0); + break; + OP_32_64(bswap32) : tcg_out_bswap32(s, a0); + break; + + OP_32_64(neg) : tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NEG, a0); + break; + OP_32_64(not) : tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, a0); + break; + + OP_32_64(ext8s) : tcg_out_ext8s(s, a0, a1, rexw); + break; + OP_32_64(ext16s) : tcg_out_ext16s(s, a0, a1, rexw); + break; + OP_32_64(ext8u) : tcg_out_ext8u(s, a0, a1); + break; + OP_32_64(ext16u) : tcg_out_ext16u(s, a0, a1); + break; + + case INDEX_op_qemu_ld_i32: + tcg_out_qemu_ld(s, args, 0); + break; + case INDEX_op_qemu_ld_i64: + tcg_out_qemu_ld(s, args, 1); + break; + case INDEX_op_qemu_st_i32: + tcg_out_qemu_st(s, args, 0); + break; + case INDEX_op_qemu_st_i64: + tcg_out_qemu_st(s, args, 1); + break; + + OP_32_64(mulu2) : tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_MUL, args[3]); + break; + OP_32_64(muls2) : tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IMUL, args[3]); + break; + OP_32_64(add2) : if (const_args[4]) { + tgen_arithi(s, ARITH_ADD + rexw, a0, args[4], 1); + } + else { + tgen_arithr(s, ARITH_ADD + rexw, a0, args[4]); + } + if (const_args[5]) { + tgen_arithi(s, ARITH_ADC + rexw, a1, args[5], 1); } else { - /* shl $n,a1,a0 -> lea 0(,a1,n),a0 */ - tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, -1, a1, a2, 0); + tgen_arithr(s, ARITH_ADC + rexw, a1, args[5]); } break; - } - c = SHIFT_SHL; - vexop = OPC_SHLX; - goto gen_shift_maybe_vex; - OP_32_64(shr): - c = SHIFT_SHR; - vexop = OPC_SHRX; - goto gen_shift_maybe_vex; - OP_32_64(sar): - c = SHIFT_SAR; - vexop = OPC_SARX; - goto gen_shift_maybe_vex; - OP_32_64(rotl): - c = SHIFT_ROL; - goto gen_shift; - OP_32_64(rotr): - c = SHIFT_ROR; - goto gen_shift; - gen_shift_maybe_vex: - if (have_bmi2) { - if (!const_a2) { - tcg_out_vex_modrm(s, vexop + rexw, a0, a2, a1); - break; + OP_32_64(sub2) : if (const_args[4]) { + tgen_arithi(s, ARITH_SUB + rexw, a0, args[4], 1); } - tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1); - } - /* FALLTHRU */ - gen_shift: - if (const_a2) { - tcg_out_shifti(s, c + rexw, a0, a2); - } else { - tcg_out_modrm(s, OPC_SHIFT_cl + rexw, c, a0); - } - break; - - OP_32_64(ctz): - tcg_out_ctz(s, rexw, args[0], args[1], args[2], const_args[2]); - break; - OP_32_64(clz): - tcg_out_clz(s, rexw, args[0], args[1], args[2], const_args[2]); - break; - OP_32_64(ctpop): - tcg_out_modrm(s, OPC_POPCNT + rexw, a0, a1); - break; - - case INDEX_op_brcond_i32: - tcg_out_brcond32(s, a2, a0, a1, const_args[1], arg_label(args[3]), 0); - break; - case INDEX_op_setcond_i32: - tcg_out_setcond32(s, args[3], a0, a1, a2, const_a2); - break; - case INDEX_op_movcond_i32: - tcg_out_movcond32(s, args[5], a0, a1, a2, const_a2, args[3]); - break; - - OP_32_64(bswap16): - tcg_out_rolw_8(s, a0); - break; - OP_32_64(bswap32): - tcg_out_bswap32(s, a0); - break; - - OP_32_64(neg): - tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NEG, a0); - break; - OP_32_64(not): - tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, a0); - break; - - OP_32_64(ext8s): - tcg_out_ext8s(s, a0, a1, rexw); - break; - OP_32_64(ext16s): - tcg_out_ext16s(s, a0, a1, rexw); - break; - OP_32_64(ext8u): - tcg_out_ext8u(s, a0, a1); - break; - OP_32_64(ext16u): - tcg_out_ext16u(s, a0, a1); - break; - - case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, 0); - break; - case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, 1); - break; - case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, 0); - break; - case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, 1); - break; - - OP_32_64(mulu2): - tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_MUL, args[3]); - break; - OP_32_64(muls2): - tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IMUL, args[3]); - break; - OP_32_64(add2): - if (const_args[4]) { - tgen_arithi(s, ARITH_ADD + rexw, a0, args[4], 1); - } else { - tgen_arithr(s, ARITH_ADD + rexw, a0, args[4]); - } - if (const_args[5]) { - tgen_arithi(s, ARITH_ADC + rexw, a1, args[5], 1); - } else { - tgen_arithr(s, ARITH_ADC + rexw, a1, args[5]); - } - break; - OP_32_64(sub2): - if (const_args[4]) { - tgen_arithi(s, ARITH_SUB + rexw, a0, args[4], 1); - } else { - tgen_arithr(s, ARITH_SUB + rexw, a0, args[4]); - } - if (const_args[5]) { - tgen_arithi(s, ARITH_SBB + rexw, a1, args[5], 1); - } else { - tgen_arithr(s, ARITH_SBB + rexw, a1, args[5]); - } - break; + else { + tgen_arithr(s, ARITH_SUB + rexw, a0, args[4]); + } + if (const_args[5]) { + tgen_arithi(s, ARITH_SBB + rexw, a1, args[5], 1); + } else { + tgen_arithr(s, ARITH_SBB + rexw, a1, args[5]); + } + break; #if TCG_TARGET_REG_BITS == 32 - case INDEX_op_brcond2_i32: - tcg_out_brcond2(s, args, const_args, 0); - break; - case INDEX_op_setcond2_i32: - tcg_out_setcond2(s, args, const_args); - break; + case INDEX_op_brcond2_i32: + tcg_out_brcond2(s, args, const_args, 0); + break; + case INDEX_op_setcond2_i32: + tcg_out_setcond2(s, args, const_args); + break; #else /* TCG_TARGET_REG_BITS == 64 */ - case INDEX_op_ld32s_i64: - tcg_out_modrm_offset(s, OPC_MOVSLQ, a0, a1, a2); - break; - case INDEX_op_ld_i64: - tcg_out_ld(s, TCG_TYPE_I64, a0, a1, a2); - break; - case INDEX_op_st_i64: - if (const_args[0]) { - tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_REXW, 0, a1, a2); - tcg_out32(s, a0); - } else { - tcg_out_st(s, TCG_TYPE_I64, a0, a1, a2); - } - break; - - case INDEX_op_brcond_i64: - tcg_out_brcond64(s, a2, a0, a1, const_args[1], arg_label(args[3]), 0); - break; - case INDEX_op_setcond_i64: - tcg_out_setcond64(s, args[3], a0, a1, a2, const_a2); - break; - case INDEX_op_movcond_i64: - tcg_out_movcond64(s, args[5], a0, a1, a2, const_a2, args[3]); - break; - - case INDEX_op_bswap64_i64: - tcg_out_bswap64(s, a0); - break; - case INDEX_op_extu_i32_i64: - case INDEX_op_ext32u_i64: - case INDEX_op_extrl_i64_i32: - tcg_out_ext32u(s, a0, a1); - break; - case INDEX_op_ext_i32_i64: - case INDEX_op_ext32s_i64: - tcg_out_ext32s(s, a0, a1); - break; - case INDEX_op_extrh_i64_i32: - tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32); - break; -#endif + case INDEX_op_ld32s_i64: + tcg_out_modrm_offset(s, OPC_MOVSLQ, a0, a1, a2); + break; + case INDEX_op_ld_i64: + tcg_out_ld(s, TCG_TYPE_I64, a0, a1, a2); + break; + case INDEX_op_st_i64: + if (const_args[0]) { + tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_REXW, 0, a1, a2); + tcg_out32(s, a0); + } else { + tcg_out_st(s, TCG_TYPE_I64, a0, a1, a2); + } + break; - OP_32_64(deposit): - if (args[3] == 0 && args[4] == 8) { - /* load bits 0..7 */ - tcg_out_modrm(s, OPC_MOVB_EvGv | P_REXB_R | P_REXB_RM, a2, a0); - } else if (args[3] == 8 && args[4] == 8) { - /* load bits 8..15 */ - tcg_out_modrm(s, OPC_MOVB_EvGv, a2, a0 + 4); - } else if (args[3] == 0 && args[4] == 16) { - /* load bits 0..15 */ - tcg_out_modrm(s, OPC_MOVL_EvGv | P_DATA16, a2, a0); - } else { - tcg_abort(); - } - break; + case INDEX_op_brcond_i64: + tcg_out_brcond64(s, a2, a0, a1, const_args[1], arg_label(args[3]), 0); + break; + case INDEX_op_setcond_i64: + tcg_out_setcond64(s, args[3], a0, a1, a2, const_a2); + break; + case INDEX_op_movcond_i64: + tcg_out_movcond64(s, args[5], a0, a1, a2, const_a2, args[3]); + break; - case INDEX_op_extract_i64: - if (a2 + args[3] == 32) { - /* This is a 32-bit zero-extending right shift. */ - tcg_out_mov(s, TCG_TYPE_I32, a0, a1); - tcg_out_shifti(s, SHIFT_SHR, a0, a2); + case INDEX_op_bswap64_i64: + tcg_out_bswap64(s, a0); break; - } + case INDEX_op_extu_i32_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_extrl_i64_i32: + tcg_out_ext32u(s, a0, a1); + break; + case INDEX_op_ext_i32_i64: + case INDEX_op_ext32s_i64: + tcg_out_ext32s(s, a0, a1); + break; + case INDEX_op_extrh_i64_i32: + tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32); + break; +#endif + + OP_32_64(deposit) : if (args[3] == 0 && args[4] == 8) { + /* load bits 0..7 */ + tcg_out_modrm(s, OPC_MOVB_EvGv | P_REXB_R | P_REXB_RM, a2, a0); + } + else if (args[3] == 8 && args[4] == 8) { + /* load bits 8..15 */ + tcg_out_modrm(s, OPC_MOVB_EvGv, a2, a0 + 4); + } + else if (args[3] == 0 && args[4] == 16) { + /* load bits 0..15 */ + tcg_out_modrm(s, OPC_MOVL_EvGv | P_DATA16, a2, a0); + } + else { + tcg_abort(); + } + break; + + case INDEX_op_extract_i64: + if (a2 + args[3] == 32) { + /* This is a 32-bit zero-extending right shift. */ + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tcg_out_shifti(s, SHIFT_SHR, a0, a2); + break; + } /* FALLTHRU */ - case INDEX_op_extract_i32: - /* On the off-chance that we can use the high-byte registers. - Otherwise we emit the same ext16 + shift pattern that we - would have gotten from the normal tcg-op.c expansion. */ - tcg_debug_assert(a2 == 8 && args[3] == 8); - if (a1 < 4 && a0 < 8) { - tcg_out_modrm(s, OPC_MOVZBL, a0, a1 + 4); - } else { - tcg_out_ext16u(s, a0, a1); - tcg_out_shifti(s, SHIFT_SHR, a0, 8); - } - break; - - case INDEX_op_sextract_i32: - /* We don't implement sextract_i64, as we cannot sign-extend to - 64-bits without using the REX prefix that explicitly excludes - access to the high-byte registers. */ - tcg_debug_assert(a2 == 8 && args[3] == 8); - if (a1 < 4 && a0 < 8) { - tcg_out_modrm(s, OPC_MOVSBL, a0, a1 + 4); - } else { - tcg_out_ext16s(s, a0, a1, 0); - tcg_out_shifti(s, SHIFT_SAR, a0, 8); - } - break; - - case INDEX_op_mb: - tcg_out_mb(s, a0); - break; - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - case INDEX_op_mov_vec: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: - case INDEX_op_dupi_vec: - case INDEX_op_call: /* Always emitted via tcg_out_call. */ - default: - tcg_abort(); + case INDEX_op_extract_i32: + /* On the off-chance that we can use the high-byte registers. + Otherwise we emit the same ext16 + shift pattern that we + would have gotten from the normal tcg-op.c expansion. */ + tcg_debug_assert(a2 == 8 && args[3] == 8); + if (a1 < 4 && a0 < 8) { + tcg_out_modrm(s, OPC_MOVZBL, a0, a1 + 4); + } else { + tcg_out_ext16u(s, a0, a1); + tcg_out_shifti(s, SHIFT_SHR, a0, 8); + } + break; + + case INDEX_op_sextract_i32: + /* We don't implement sextract_i64, as we cannot sign-extend to + 64-bits without using the REX prefix that explicitly excludes + access to the high-byte registers. */ + tcg_debug_assert(a2 == 8 && args[3] == 8); + if (a1 < 4 && a0 < 8) { + tcg_out_modrm(s, OPC_MOVSBL, a0, a1 + 4); + } else { + tcg_out_ext16s(s, a0, a1, 0); + tcg_out_shifti(s, SHIFT_SAR, a0, 8); + } + break; + + case INDEX_op_mb: + tcg_out_mb(s, a0); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ + case INDEX_op_mov_i64: + case INDEX_op_mov_vec: + case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ + case INDEX_op_movi_i64: + case INDEX_op_dupi_vec: + case INDEX_op_call: /* Always emitted via tcg_out_call. */ + default: + tcg_abort(); } #undef OP_32_64 } -static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, - unsigned vecl, unsigned vece, - const TCGArg *args, const int *const_args) -{ - static int const add_insn[4] = { - OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ - }; - static int const ssadd_insn[4] = { - OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2 - }; - static int const usadd_insn[4] = { - OPC_PADDUB, OPC_PADDUW, OPC_UD2, OPC_UD2 - }; - static int const sub_insn[4] = { - OPC_PSUBB, OPC_PSUBW, OPC_PSUBD, OPC_PSUBQ - }; - static int const sssub_insn[4] = { - OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2 - }; - static int const ussub_insn[4] = { - OPC_PSUBUB, OPC_PSUBUW, OPC_UD2, OPC_UD2 - }; - static int const mul_insn[4] = { - OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_UD2 - }; - static int const shift_imm_insn[4] = { - OPC_UD2, OPC_PSHIFTW_Ib, OPC_PSHIFTD_Ib, OPC_PSHIFTQ_Ib - }; - static int const cmpeq_insn[4] = { - OPC_PCMPEQB, OPC_PCMPEQW, OPC_PCMPEQD, OPC_PCMPEQQ - }; - static int const cmpgt_insn[4] = { - OPC_PCMPGTB, OPC_PCMPGTW, OPC_PCMPGTD, OPC_PCMPGTQ - }; - static int const punpckl_insn[4] = { - OPC_PUNPCKLBW, OPC_PUNPCKLWD, OPC_PUNPCKLDQ, OPC_PUNPCKLQDQ - }; - static int const punpckh_insn[4] = { - OPC_PUNPCKHBW, OPC_PUNPCKHWD, OPC_PUNPCKHDQ, OPC_PUNPCKHQDQ - }; - static int const packss_insn[4] = { - OPC_PACKSSWB, OPC_PACKSSDW, OPC_UD2, OPC_UD2 - }; - static int const packus_insn[4] = { - OPC_PACKUSWB, OPC_PACKUSDW, OPC_UD2, OPC_UD2 - }; - static int const smin_insn[4] = { - OPC_PMINSB, OPC_PMINSW, OPC_PMINSD, OPC_UD2 - }; - static int const smax_insn[4] = { - OPC_PMAXSB, OPC_PMAXSW, OPC_PMAXSD, OPC_UD2 - }; - static int const umin_insn[4] = { - OPC_PMINUB, OPC_PMINUW, OPC_PMINUD, OPC_UD2 - }; - static int const umax_insn[4] = { - OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2 - }; +static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, const TCGArg *args, + const int *const_args) { + static int const add_insn[4] = {OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ}; + static int const ssadd_insn[4] = {OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2}; + static int const usadd_insn[4] = {OPC_PADDUB, OPC_PADDUW, OPC_UD2, OPC_UD2}; + static int const sub_insn[4] = {OPC_PSUBB, OPC_PSUBW, OPC_PSUBD, OPC_PSUBQ}; + static int const sssub_insn[4] = {OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2}; + static int const ussub_insn[4] = {OPC_PSUBUB, OPC_PSUBUW, OPC_UD2, OPC_UD2}; + static int const mul_insn[4] = {OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_UD2}; + static int const shift_imm_insn[4] = {OPC_UD2, OPC_PSHIFTW_Ib, OPC_PSHIFTD_Ib, OPC_PSHIFTQ_Ib}; + static int const cmpeq_insn[4] = {OPC_PCMPEQB, OPC_PCMPEQW, OPC_PCMPEQD, OPC_PCMPEQQ}; + static int const cmpgt_insn[4] = {OPC_PCMPGTB, OPC_PCMPGTW, OPC_PCMPGTD, OPC_PCMPGTQ}; + static int const punpckl_insn[4] = {OPC_PUNPCKLBW, OPC_PUNPCKLWD, OPC_PUNPCKLDQ, OPC_PUNPCKLQDQ}; + static int const punpckh_insn[4] = {OPC_PUNPCKHBW, OPC_PUNPCKHWD, OPC_PUNPCKHDQ, OPC_PUNPCKHQDQ}; + static int const packss_insn[4] = {OPC_PACKSSWB, OPC_PACKSSDW, OPC_UD2, OPC_UD2}; + static int const packus_insn[4] = {OPC_PACKUSWB, OPC_PACKUSDW, OPC_UD2, OPC_UD2}; + static int const smin_insn[4] = {OPC_PMINSB, OPC_PMINSW, OPC_PMINSD, OPC_UD2}; + static int const smax_insn[4] = {OPC_PMAXSB, OPC_PMAXSW, OPC_PMAXSD, OPC_UD2}; + static int const umin_insn[4] = {OPC_PMINUB, OPC_PMINUW, OPC_PMINUD, OPC_UD2}; + static int const umax_insn[4] = {OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2}; TCGType type = vecl + TCG_TYPE_V64; int insn, sub; @@ -2650,503 +2377,466 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, a2 = args[2]; switch (opc) { - case INDEX_op_add_vec: - insn = add_insn[vece]; - goto gen_simd; - case INDEX_op_ssadd_vec: - insn = ssadd_insn[vece]; - goto gen_simd; - case INDEX_op_usadd_vec: - insn = usadd_insn[vece]; - goto gen_simd; - case INDEX_op_sub_vec: - insn = sub_insn[vece]; - goto gen_simd; - case INDEX_op_sssub_vec: - insn = sssub_insn[vece]; - goto gen_simd; - case INDEX_op_ussub_vec: - insn = ussub_insn[vece]; - goto gen_simd; - case INDEX_op_mul_vec: - insn = mul_insn[vece]; - goto gen_simd; - case INDEX_op_and_vec: - insn = OPC_PAND; - goto gen_simd; - case INDEX_op_or_vec: - insn = OPC_POR; - goto gen_simd; - case INDEX_op_xor_vec: - insn = OPC_PXOR; - goto gen_simd; - case INDEX_op_smin_vec: - insn = smin_insn[vece]; - goto gen_simd; - case INDEX_op_umin_vec: - insn = umin_insn[vece]; - goto gen_simd; - case INDEX_op_smax_vec: - insn = smax_insn[vece]; - goto gen_simd; - case INDEX_op_umax_vec: - insn = umax_insn[vece]; - goto gen_simd; - case INDEX_op_x86_punpckl_vec: - insn = punpckl_insn[vece]; - goto gen_simd; - case INDEX_op_x86_punpckh_vec: - insn = punpckh_insn[vece]; - goto gen_simd; - case INDEX_op_x86_packss_vec: - insn = packss_insn[vece]; - goto gen_simd; - case INDEX_op_x86_packus_vec: - insn = packus_insn[vece]; - goto gen_simd; + case INDEX_op_add_vec: + insn = add_insn[vece]; + goto gen_simd; + case INDEX_op_ssadd_vec: + insn = ssadd_insn[vece]; + goto gen_simd; + case INDEX_op_usadd_vec: + insn = usadd_insn[vece]; + goto gen_simd; + case INDEX_op_sub_vec: + insn = sub_insn[vece]; + goto gen_simd; + case INDEX_op_sssub_vec: + insn = sssub_insn[vece]; + goto gen_simd; + case INDEX_op_ussub_vec: + insn = ussub_insn[vece]; + goto gen_simd; + case INDEX_op_mul_vec: + insn = mul_insn[vece]; + goto gen_simd; + case INDEX_op_and_vec: + insn = OPC_PAND; + goto gen_simd; + case INDEX_op_or_vec: + insn = OPC_POR; + goto gen_simd; + case INDEX_op_xor_vec: + insn = OPC_PXOR; + goto gen_simd; + case INDEX_op_smin_vec: + insn = smin_insn[vece]; + goto gen_simd; + case INDEX_op_umin_vec: + insn = umin_insn[vece]; + goto gen_simd; + case INDEX_op_smax_vec: + insn = smax_insn[vece]; + goto gen_simd; + case INDEX_op_umax_vec: + insn = umax_insn[vece]; + goto gen_simd; + case INDEX_op_x86_punpckl_vec: + insn = punpckl_insn[vece]; + goto gen_simd; + case INDEX_op_x86_punpckh_vec: + insn = punpckh_insn[vece]; + goto gen_simd; + case INDEX_op_x86_packss_vec: + insn = packss_insn[vece]; + goto gen_simd; + case INDEX_op_x86_packus_vec: + insn = packus_insn[vece]; + goto gen_simd; #if TCG_TARGET_REG_BITS == 32 - case INDEX_op_dup2_vec: - /* Constraints have already placed both 32-bit inputs in xmm regs. */ - insn = OPC_PUNPCKLDQ; - goto gen_simd; + case INDEX_op_dup2_vec: + /* Constraints have already placed both 32-bit inputs in xmm regs. */ + insn = OPC_PUNPCKLDQ; + goto gen_simd; #endif - gen_simd: - tcg_debug_assert(insn != OPC_UD2); - if (type == TCG_TYPE_V256) { - insn |= P_VEXL; - } - tcg_out_vex_modrm(s, insn, a0, a1, a2); - break; - - case INDEX_op_cmp_vec: - sub = args[3]; - if (sub == TCG_COND_EQ) { - insn = cmpeq_insn[vece]; - } else if (sub == TCG_COND_GT) { - insn = cmpgt_insn[vece]; - } else { - g_assert_not_reached(); - } - goto gen_simd; + gen_simd: + tcg_debug_assert(insn != OPC_UD2); + if (type == TCG_TYPE_V256) { + insn |= P_VEXL; + } + tcg_out_vex_modrm(s, insn, a0, a1, a2); + break; - case INDEX_op_andc_vec: - insn = OPC_PANDN; - if (type == TCG_TYPE_V256) { - insn |= P_VEXL; - } - tcg_out_vex_modrm(s, insn, a0, a2, a1); - break; - - case INDEX_op_shli_vec: - sub = 6; - goto gen_shift; - case INDEX_op_shri_vec: - sub = 2; - goto gen_shift; - case INDEX_op_sari_vec: - tcg_debug_assert(vece != MO_64); - sub = 4; - gen_shift: - tcg_debug_assert(vece != MO_8); - insn = shift_imm_insn[vece]; - if (type == TCG_TYPE_V256) { - insn |= P_VEXL; - } - tcg_out_vex_modrm(s, insn, sub, a0, a1); - tcg_out8(s, a2); - break; - - case INDEX_op_ld_vec: - tcg_out_ld(s, type, a0, a1, a2); - break; - case INDEX_op_st_vec: - tcg_out_st(s, type, a0, a1, a2); - break; - case INDEX_op_dup_vec: - tcg_out_dup_vec(s, type, vece, a0, a1); - break; - - case INDEX_op_x86_shufps_vec: - insn = OPC_SHUFPS; - sub = args[3]; - goto gen_simd_imm8; - case INDEX_op_x86_blend_vec: - if (vece == MO_16) { - insn = OPC_PBLENDW; - } else if (vece == MO_32) { - insn = (have_avx2 ? OPC_VPBLENDD : OPC_BLENDPS); - } else { + case INDEX_op_cmp_vec: + sub = args[3]; + if (sub == TCG_COND_EQ) { + insn = cmpeq_insn[vece]; + } else if (sub == TCG_COND_GT) { + insn = cmpgt_insn[vece]; + } else { + g_assert_not_reached(); + } + goto gen_simd; + + case INDEX_op_andc_vec: + insn = OPC_PANDN; + if (type == TCG_TYPE_V256) { + insn |= P_VEXL; + } + tcg_out_vex_modrm(s, insn, a0, a2, a1); + break; + + case INDEX_op_shli_vec: + sub = 6; + goto gen_shift; + case INDEX_op_shri_vec: + sub = 2; + goto gen_shift; + case INDEX_op_sari_vec: + tcg_debug_assert(vece != MO_64); + sub = 4; + gen_shift: + tcg_debug_assert(vece != MO_8); + insn = shift_imm_insn[vece]; + if (type == TCG_TYPE_V256) { + insn |= P_VEXL; + } + tcg_out_vex_modrm(s, insn, sub, a0, a1); + tcg_out8(s, a2); + break; + + case INDEX_op_ld_vec: + tcg_out_ld(s, type, a0, a1, a2); + break; + case INDEX_op_st_vec: + tcg_out_st(s, type, a0, a1, a2); + break; + case INDEX_op_dup_vec: + tcg_out_dup_vec(s, type, vece, a0, a1); + break; + + case INDEX_op_x86_shufps_vec: + insn = OPC_SHUFPS; + sub = args[3]; + goto gen_simd_imm8; + case INDEX_op_x86_blend_vec: + if (vece == MO_16) { + insn = OPC_PBLENDW; + } else if (vece == MO_32) { + insn = (have_avx2 ? OPC_VPBLENDD : OPC_BLENDPS); + } else { + g_assert_not_reached(); + } + sub = args[3]; + goto gen_simd_imm8; + case INDEX_op_x86_vperm2i128_vec: + insn = OPC_VPERM2I128; + sub = args[3]; + goto gen_simd_imm8; + gen_simd_imm8: + if (type == TCG_TYPE_V256) { + insn |= P_VEXL; + } + tcg_out_vex_modrm(s, insn, a0, a1, a2); + tcg_out8(s, sub); + break; + + case INDEX_op_x86_vpblendvb_vec: + insn = OPC_VPBLENDVB; + if (type == TCG_TYPE_V256) { + insn |= P_VEXL; + } + tcg_out_vex_modrm(s, insn, a0, a1, a2); + tcg_out8(s, args[3] << 4); + break; + + case INDEX_op_x86_psrldq_vec: + tcg_out_vex_modrm(s, OPC_GRP14, 3, a0, a1); + tcg_out8(s, a2); + break; + + default: g_assert_not_reached(); - } - sub = args[3]; - goto gen_simd_imm8; - case INDEX_op_x86_vperm2i128_vec: - insn = OPC_VPERM2I128; - sub = args[3]; - goto gen_simd_imm8; - gen_simd_imm8: - if (type == TCG_TYPE_V256) { - insn |= P_VEXL; - } - tcg_out_vex_modrm(s, insn, a0, a1, a2); - tcg_out8(s, sub); - break; - - case INDEX_op_x86_vpblendvb_vec: - insn = OPC_VPBLENDVB; - if (type == TCG_TYPE_V256) { - insn |= P_VEXL; - } - tcg_out_vex_modrm(s, insn, a0, a1, a2); - tcg_out8(s, args[3] << 4); - break; - - case INDEX_op_x86_psrldq_vec: - tcg_out_vex_modrm(s, OPC_GRP14, 3, a0, a1); - tcg_out8(s, a2); - break; - - default: - g_assert_not_reached(); - } -} - -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) -{ - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef ri_r = { .args_ct_str = { "ri", "r" } }; - static const TCGTargetOpDef re_r = { .args_ct_str = { "re", "r" } }; - static const TCGTargetOpDef qi_r = { .args_ct_str = { "qi", "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef r_q = { .args_ct_str = { "r", "q" } }; - static const TCGTargetOpDef r_re = { .args_ct_str = { "r", "re" } }; - static const TCGTargetOpDef r_0 = { .args_ct_str = { "r", "0" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_re = { .args_ct_str = { "r", "r", "re" } }; - static const TCGTargetOpDef r_0_re = { .args_ct_str = { "r", "0", "re" } }; - static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } }; - static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } }; - static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } }; - static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } }; - static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } }; - static const TCGTargetOpDef r_r_L_L - = { .args_ct_str = { "r", "r", "L", "L" } }; - static const TCGTargetOpDef L_L_L_L - = { .args_ct_str = { "L", "L", "L", "L" } }; - static const TCGTargetOpDef x_x = { .args_ct_str = { "x", "x" } }; - static const TCGTargetOpDef x_x_x = { .args_ct_str = { "x", "x", "x" } }; - static const TCGTargetOpDef x_x_x_x - = { .args_ct_str = { "x", "x", "x", "x" } }; - static const TCGTargetOpDef x_r = { .args_ct_str = { "x", "r" } }; + } +} + +static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { + static const TCGTargetOpDef r = {.args_ct_str = {"r"}}; + static const TCGTargetOpDef ri_r = {.args_ct_str = {"ri", "r"}}; + static const TCGTargetOpDef re_r = {.args_ct_str = {"re", "r"}}; + static const TCGTargetOpDef qi_r = {.args_ct_str = {"qi", "r"}}; + static const TCGTargetOpDef r_r = {.args_ct_str = {"r", "r"}}; + static const TCGTargetOpDef r_q = {.args_ct_str = {"r", "q"}}; + static const TCGTargetOpDef r_re = {.args_ct_str = {"r", "re"}}; + static const TCGTargetOpDef r_0 = {.args_ct_str = {"r", "0"}}; + static const TCGTargetOpDef r_r_ri = {.args_ct_str = {"r", "r", "ri"}}; + static const TCGTargetOpDef r_r_re = {.args_ct_str = {"r", "r", "re"}}; + static const TCGTargetOpDef r_0_re = {.args_ct_str = {"r", "0", "re"}}; + static const TCGTargetOpDef r_0_ci = {.args_ct_str = {"r", "0", "ci"}}; + static const TCGTargetOpDef r_L = {.args_ct_str = {"r", "L"}}; + static const TCGTargetOpDef L_L = {.args_ct_str = {"L", "L"}}; + static const TCGTargetOpDef r_L_L = {.args_ct_str = {"r", "L", "L"}}; + static const TCGTargetOpDef r_r_L = {.args_ct_str = {"r", "r", "L"}}; + static const TCGTargetOpDef L_L_L = {.args_ct_str = {"L", "L", "L"}}; + static const TCGTargetOpDef r_r_L_L = {.args_ct_str = {"r", "r", "L", "L"}}; + static const TCGTargetOpDef L_L_L_L = {.args_ct_str = {"L", "L", "L", "L"}}; + static const TCGTargetOpDef x_x = {.args_ct_str = {"x", "x"}}; + static const TCGTargetOpDef x_x_x = {.args_ct_str = {"x", "x", "x"}}; + static const TCGTargetOpDef x_x_x_x = {.args_ct_str = {"x", "x", "x", "x"}}; + static const TCGTargetOpDef x_r = {.args_ct_str = {"x", "r"}}; switch (op) { - case INDEX_op_goto_ptr: - return &r; - - case INDEX_op_ld8u_i32: - case INDEX_op_ld8u_i64: - case INDEX_op_ld8s_i32: - case INDEX_op_ld8s_i64: - case INDEX_op_ld16u_i32: - case INDEX_op_ld16u_i64: - case INDEX_op_ld16s_i32: - case INDEX_op_ld16s_i64: - case INDEX_op_ld_i32: - case INDEX_op_ld32u_i64: - case INDEX_op_ld32s_i64: - case INDEX_op_ld_i64: - return &r_r; - - case INDEX_op_st8_i32: - case INDEX_op_st8_i64: - return &qi_r; - case INDEX_op_st16_i32: - case INDEX_op_st16_i64: - case INDEX_op_st_i32: - case INDEX_op_st32_i64: - return &ri_r; - case INDEX_op_st_i64: - return &re_r; - - case INDEX_op_add_i32: - case INDEX_op_add_i64: - return &r_r_re; - case INDEX_op_sub_i32: - case INDEX_op_sub_i64: - case INDEX_op_mul_i32: - case INDEX_op_mul_i64: - case INDEX_op_or_i32: - case INDEX_op_or_i64: - case INDEX_op_xor_i32: - case INDEX_op_xor_i64: - return &r_0_re; - - case INDEX_op_and_i32: - case INDEX_op_and_i64: - { - static const TCGTargetOpDef and - = { .args_ct_str = { "r", "0", "reZ" } }; + case INDEX_op_goto_ptr: + return &r; + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i32: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i32: + case INDEX_op_ld16s_i64: + case INDEX_op_ld_i32: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + return &r_r; + + case INDEX_op_st8_i32: + case INDEX_op_st8_i64: + return &qi_r; + case INDEX_op_st16_i32: + case INDEX_op_st16_i64: + case INDEX_op_st_i32: + case INDEX_op_st32_i64: + return &ri_r; + case INDEX_op_st_i64: + return &re_r; + + case INDEX_op_add_i32: + case INDEX_op_add_i64: + return &r_r_re; + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + case INDEX_op_mul_i32: + case INDEX_op_mul_i64: + case INDEX_op_or_i32: + case INDEX_op_or_i64: + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + return &r_0_re; + + case INDEX_op_and_i32: + case INDEX_op_and_i64: { + static const TCGTargetOpDef and = {.args_ct_str = {"r", "0", "reZ"}}; return ∧ - } - break; - case INDEX_op_andc_i32: - case INDEX_op_andc_i64: - { - static const TCGTargetOpDef andc - = { .args_ct_str = { "r", "r", "rI" } }; + } break; + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: { + static const TCGTargetOpDef andc = {.args_ct_str = {"r", "r", "rI"}}; return &andc; - } - break; - - case INDEX_op_shl_i32: - case INDEX_op_shl_i64: - case INDEX_op_shr_i32: - case INDEX_op_shr_i64: - case INDEX_op_sar_i32: - case INDEX_op_sar_i64: - return have_bmi2 ? &r_r_ri : &r_0_ci; - case INDEX_op_rotl_i32: - case INDEX_op_rotl_i64: - case INDEX_op_rotr_i32: - case INDEX_op_rotr_i64: - return &r_0_ci; - - case INDEX_op_brcond_i32: - case INDEX_op_brcond_i64: - return &r_re; - - case INDEX_op_bswap16_i32: - case INDEX_op_bswap16_i64: - case INDEX_op_bswap32_i32: - case INDEX_op_bswap32_i64: - case INDEX_op_bswap64_i64: - case INDEX_op_neg_i32: - case INDEX_op_neg_i64: - case INDEX_op_not_i32: - case INDEX_op_not_i64: - case INDEX_op_extrh_i64_i32: - return &r_0; - - case INDEX_op_ext8s_i32: - case INDEX_op_ext8s_i64: - case INDEX_op_ext8u_i32: - case INDEX_op_ext8u_i64: - return &r_q; - case INDEX_op_ext16s_i32: - case INDEX_op_ext16s_i64: - case INDEX_op_ext16u_i32: - case INDEX_op_ext16u_i64: - case INDEX_op_ext32s_i64: - case INDEX_op_ext32u_i64: - case INDEX_op_ext_i32_i64: - case INDEX_op_extu_i32_i64: - case INDEX_op_extrl_i64_i32: - case INDEX_op_extract_i32: - case INDEX_op_extract_i64: - case INDEX_op_sextract_i32: - case INDEX_op_ctpop_i32: - case INDEX_op_ctpop_i64: - return &r_r; - - case INDEX_op_deposit_i32: - case INDEX_op_deposit_i64: - { - static const TCGTargetOpDef dep - = { .args_ct_str = { "Q", "0", "Q" } }; + } break; + + case INDEX_op_shl_i32: + case INDEX_op_shl_i64: + case INDEX_op_shr_i32: + case INDEX_op_shr_i64: + case INDEX_op_sar_i32: + case INDEX_op_sar_i64: + return have_bmi2 ? &r_r_ri : &r_0_ci; + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + return &r_0_ci; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + return &r_re; + + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: + case INDEX_op_not_i32: + case INDEX_op_not_i64: + case INDEX_op_extrh_i64_i32: + return &r_0; + + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + return &r_q; + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_extrl_i64_i32: + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: + case INDEX_op_sextract_i32: + case INDEX_op_ctpop_i32: + case INDEX_op_ctpop_i64: + return &r_r; + + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: { + static const TCGTargetOpDef dep = {.args_ct_str = {"Q", "0", "Q"}}; return &dep; } - case INDEX_op_setcond_i32: - case INDEX_op_setcond_i64: - { - static const TCGTargetOpDef setc - = { .args_ct_str = { "q", "r", "re" } }; + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: { + static const TCGTargetOpDef setc = {.args_ct_str = {"q", "r", "re"}}; return &setc; } - case INDEX_op_movcond_i32: - case INDEX_op_movcond_i64: - { - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "r", "re", "r", "0" } }; + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: { + static const TCGTargetOpDef movc = {.args_ct_str = {"r", "r", "re", "r", "0"}}; return &movc; } - case INDEX_op_div2_i32: - case INDEX_op_div2_i64: - case INDEX_op_divu2_i32: - case INDEX_op_divu2_i64: - { - static const TCGTargetOpDef div2 - = { .args_ct_str = { "a", "d", "0", "1", "r" } }; + case INDEX_op_div2_i32: + case INDEX_op_div2_i64: + case INDEX_op_divu2_i32: + case INDEX_op_divu2_i64: { + static const TCGTargetOpDef div2 = {.args_ct_str = {"a", "d", "0", "1", "r"}}; return &div2; } - case INDEX_op_mulu2_i32: - case INDEX_op_mulu2_i64: - case INDEX_op_muls2_i32: - case INDEX_op_muls2_i64: - { - static const TCGTargetOpDef mul2 - = { .args_ct_str = { "a", "d", "a", "r" } }; + case INDEX_op_mulu2_i32: + case INDEX_op_mulu2_i64: + case INDEX_op_muls2_i32: + case INDEX_op_muls2_i64: { + static const TCGTargetOpDef mul2 = {.args_ct_str = {"a", "d", "a", "r"}}; return &mul2; } - case INDEX_op_add2_i32: - case INDEX_op_add2_i64: - case INDEX_op_sub2_i32: - case INDEX_op_sub2_i64: - { - static const TCGTargetOpDef arith2 - = { .args_ct_str = { "r", "r", "0", "1", "re", "re" } }; + case INDEX_op_add2_i32: + case INDEX_op_add2_i64: + case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: { + static const TCGTargetOpDef arith2 = {.args_ct_str = {"r", "r", "0", "1", "re", "re"}}; return &arith2; } - case INDEX_op_ctz_i32: - case INDEX_op_ctz_i64: - { + case INDEX_op_ctz_i32: + case INDEX_op_ctz_i64: { static const TCGTargetOpDef ctz[2] = { - { .args_ct_str = { "&r", "r", "r" } }, - { .args_ct_str = { "&r", "r", "rW" } }, + {.args_ct_str = {"&r", "r", "r"}}, {.args_ct_str = {"&r", "r", "rW"}}, }; return &ctz[have_bmi1]; } - case INDEX_op_clz_i32: - case INDEX_op_clz_i64: - { + case INDEX_op_clz_i32: + case INDEX_op_clz_i64: { static const TCGTargetOpDef clz[2] = { - { .args_ct_str = { "&r", "r", "r" } }, - { .args_ct_str = { "&r", "r", "rW" } }, + {.args_ct_str = {"&r", "r", "r"}}, {.args_ct_str = {"&r", "r", "rW"}}, }; return &clz[have_lzcnt]; } - case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L; - case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L : &L_L_L; - case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS == 64 ? &r_L - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L - : &r_r_L_L); - case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS == 64 ? &L_L - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L_L - : &L_L_L_L); - - case INDEX_op_brcond2_i32: - { - static const TCGTargetOpDef b2 - = { .args_ct_str = { "r", "r", "ri", "ri" } }; + case INDEX_op_qemu_ld_i32: + return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L; + case INDEX_op_qemu_st_i32: + return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L : &L_L_L; + case INDEX_op_qemu_ld_i64: + return (TCG_TARGET_REG_BITS == 64 ? &r_L : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L : &r_r_L_L); + case INDEX_op_qemu_st_i64: + return (TCG_TARGET_REG_BITS == 64 ? &L_L : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L_L : &L_L_L_L); + + case INDEX_op_brcond2_i32: { + static const TCGTargetOpDef b2 = {.args_ct_str = {"r", "r", "ri", "ri"}}; return &b2; } - case INDEX_op_setcond2_i32: - { - static const TCGTargetOpDef s2 - = { .args_ct_str = { "r", "r", "r", "ri", "ri" } }; + case INDEX_op_setcond2_i32: { + static const TCGTargetOpDef s2 = {.args_ct_str = {"r", "r", "r", "ri", "ri"}}; return &s2; } - case INDEX_op_ld_vec: - case INDEX_op_st_vec: - return &x_r; - - case INDEX_op_add_vec: - case INDEX_op_sub_vec: - case INDEX_op_mul_vec: - case INDEX_op_and_vec: - case INDEX_op_or_vec: - case INDEX_op_xor_vec: - case INDEX_op_andc_vec: - case INDEX_op_ssadd_vec: - case INDEX_op_usadd_vec: - case INDEX_op_sssub_vec: - case INDEX_op_ussub_vec: - case INDEX_op_smin_vec: - case INDEX_op_umin_vec: - case INDEX_op_smax_vec: - case INDEX_op_umax_vec: - case INDEX_op_cmp_vec: - case INDEX_op_x86_shufps_vec: - case INDEX_op_x86_blend_vec: - case INDEX_op_x86_packss_vec: - case INDEX_op_x86_packus_vec: - case INDEX_op_x86_vperm2i128_vec: - case INDEX_op_x86_punpckl_vec: - case INDEX_op_x86_punpckh_vec: + case INDEX_op_ld_vec: + case INDEX_op_st_vec: + return &x_r; + + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_mul_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + case INDEX_op_andc_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_usadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_ussub_vec: + case INDEX_op_smin_vec: + case INDEX_op_umin_vec: + case INDEX_op_smax_vec: + case INDEX_op_umax_vec: + case INDEX_op_cmp_vec: + case INDEX_op_x86_shufps_vec: + case INDEX_op_x86_blend_vec: + case INDEX_op_x86_packss_vec: + case INDEX_op_x86_packus_vec: + case INDEX_op_x86_vperm2i128_vec: + case INDEX_op_x86_punpckl_vec: + case INDEX_op_x86_punpckh_vec: #if TCG_TARGET_REG_BITS == 32 - case INDEX_op_dup2_vec: + case INDEX_op_dup2_vec: #endif - return &x_x_x; - case INDEX_op_dup_vec: - case INDEX_op_shli_vec: - case INDEX_op_shri_vec: - case INDEX_op_sari_vec: - case INDEX_op_x86_psrldq_vec: - return &x_x; - case INDEX_op_x86_vpblendvb_vec: - return &x_x_x_x; - - default: - break; + return &x_x_x; + case INDEX_op_dup_vec: + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: + case INDEX_op_sari_vec: + case INDEX_op_x86_psrldq_vec: + return &x_x; + case INDEX_op_x86_vpblendvb_vec: + return &x_x_x_x; + + default: + break; } return NULL; } -int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) -{ +int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) { switch (opc) { - case INDEX_op_add_vec: - case INDEX_op_sub_vec: - case INDEX_op_and_vec: - case INDEX_op_or_vec: - case INDEX_op_xor_vec: - case INDEX_op_andc_vec: - return 1; - case INDEX_op_cmp_vec: - return -1; - - case INDEX_op_shli_vec: - case INDEX_op_shri_vec: - /* We must expand the operation for MO_8. */ - return vece == MO_8 ? -1 : 1; - - case INDEX_op_sari_vec: - /* We must expand the operation for MO_8. */ - if (vece == MO_8) { + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + case INDEX_op_andc_vec: + return 1; + case INDEX_op_cmp_vec: return -1; - } - /* We can emulate this for MO_64, but it does not pay off - unless we're producing at least 4 values. */ - if (vece == MO_64) { - return type >= TCG_TYPE_V256 ? -1 : 0; - } - return 1; - case INDEX_op_mul_vec: - if (vece == MO_8) { - /* We can expand the operation for MO_8. */ - return -1; - } - if (vece == MO_64) { - return 0; - } - return 1; + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: + /* We must expand the operation for MO_8. */ + return vece == MO_8 ? -1 : 1; + + case INDEX_op_sari_vec: + /* We must expand the operation for MO_8. */ + if (vece == MO_8) { + return -1; + } + /* We can emulate this for MO_64, but it does not pay off + unless we're producing at least 4 values. */ + if (vece == MO_64) { + return type >= TCG_TYPE_V256 ? -1 : 0; + } + return 1; - case INDEX_op_ssadd_vec: - case INDEX_op_usadd_vec: - case INDEX_op_sssub_vec: - case INDEX_op_ussub_vec: - return vece <= MO_16; - case INDEX_op_smin_vec: - case INDEX_op_smax_vec: - case INDEX_op_umin_vec: - case INDEX_op_umax_vec: - return vece <= MO_32 ? 1 : -1; + case INDEX_op_mul_vec: + if (vece == MO_8) { + /* We can expand the operation for MO_8. */ + return -1; + } + if (vece == MO_64) { + return 0; + } + return 1; + + case INDEX_op_ssadd_vec: + case INDEX_op_usadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_ussub_vec: + return vece <= MO_16; + case INDEX_op_smin_vec: + case INDEX_op_smax_vec: + case INDEX_op_umin_vec: + case INDEX_op_umax_vec: + return vece <= MO_32 ? 1 : -1; - default: - return 0; + default: + return 0; } } -static void expand_vec_shi(TCGType type, unsigned vece, bool shr, - TCGv_vec v0, TCGv_vec v1, TCGArg imm) -{ +static void expand_vec_shi(TCGType type, unsigned vece, bool shr, TCGv_vec v0, TCGv_vec v1, TCGArg imm) { TCGv_vec t1, t2; tcg_debug_assert(vece == MO_8); @@ -3163,10 +2853,8 @@ static void expand_vec_shi(TCGType type, unsigned vece, bool shr, (3) Step 2 leaves high half zero such that PACKUSWB (pack with unsigned saturation) does not modify the quantity. */ - vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, - tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); - vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, - tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); + vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); + vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); if (shr) { tcg_gen_shri_vec(MO_16, t1, t1, imm + 8); @@ -3178,68 +2866,59 @@ static void expand_vec_shi(TCGType type, unsigned vece, bool shr, tcg_gen_shri_vec(MO_16, t2, t2, 8); } - vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8, - tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2)); + vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8, tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2)); tcg_temp_free_vec(t1); tcg_temp_free_vec(t2); } -static void expand_vec_sari(TCGType type, unsigned vece, - TCGv_vec v0, TCGv_vec v1, TCGArg imm) -{ +static void expand_vec_sari(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGArg imm) { TCGv_vec t1, t2; switch (vece) { - case MO_8: - /* Unpack to W, shift, and repack, as in expand_vec_shi. */ - t1 = tcg_temp_new_vec(type); - t2 = tcg_temp_new_vec(type); - vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, - tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); - vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, - tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); - tcg_gen_sari_vec(MO_16, t1, t1, imm + 8); - tcg_gen_sari_vec(MO_16, t2, t2, imm + 8); - vec_gen_3(INDEX_op_x86_packss_vec, type, MO_8, - tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2)); - tcg_temp_free_vec(t1); - tcg_temp_free_vec(t2); - break; - - case MO_64: - if (imm <= 32) { - /* We can emulate a small sign extend by performing an arithmetic - * 32-bit shift and overwriting the high half of a 64-bit logical - * shift (note that the ISA says shift of 32 is valid). - */ + case MO_8: + /* Unpack to W, shift, and repack, as in expand_vec_shi. */ t1 = tcg_temp_new_vec(type); - tcg_gen_sari_vec(MO_32, t1, v1, imm); - tcg_gen_shri_vec(MO_64, v0, v1, imm); - vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32, - tcgv_vec_arg(v0), tcgv_vec_arg(v0), - tcgv_vec_arg(t1), 0xaa); + t2 = tcg_temp_new_vec(type); + vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); + vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); + tcg_gen_sari_vec(MO_16, t1, t1, imm + 8); + tcg_gen_sari_vec(MO_16, t2, t2, imm + 8); + vec_gen_3(INDEX_op_x86_packss_vec, type, MO_8, tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2)); tcg_temp_free_vec(t1); - } else { - /* Otherwise we will need to use a compare vs 0 to produce - * the sign-extend, shift and merge. - */ - t1 = tcg_const_zeros_vec(type); - tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1, t1, v1); - tcg_gen_shri_vec(MO_64, v0, v1, imm); - tcg_gen_shli_vec(MO_64, t1, t1, 64 - imm); - tcg_gen_or_vec(MO_64, v0, v0, t1); - tcg_temp_free_vec(t1); - } - break; + tcg_temp_free_vec(t2); + break; + + case MO_64: + if (imm <= 32) { + /* We can emulate a small sign extend by performing an arithmetic + * 32-bit shift and overwriting the high half of a 64-bit logical + * shift (note that the ISA says shift of 32 is valid). + */ + t1 = tcg_temp_new_vec(type); + tcg_gen_sari_vec(MO_32, t1, v1, imm); + tcg_gen_shri_vec(MO_64, v0, v1, imm); + vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32, tcgv_vec_arg(v0), tcgv_vec_arg(v0), tcgv_vec_arg(t1), + 0xaa); + tcg_temp_free_vec(t1); + } else { + /* Otherwise we will need to use a compare vs 0 to produce + * the sign-extend, shift and merge. + */ + t1 = tcg_const_zeros_vec(type); + tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1, t1, v1); + tcg_gen_shri_vec(MO_64, v0, v1, imm); + tcg_gen_shli_vec(MO_64, t1, t1, 64 - imm); + tcg_gen_or_vec(MO_64, v0, v0, t1); + tcg_temp_free_vec(t1); + } + break; - default: - g_assert_not_reached(); + default: + g_assert_not_reached(); } } -static void expand_vec_mul(TCGType type, unsigned vece, - TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) -{ +static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) { TCGv_vec t1, t2, t3, t4; tcg_debug_assert(vece == MO_8); @@ -3255,74 +2934,63 @@ static void expand_vec_mul(TCGType type, unsigned vece, * we distribute the expansion between temporaries. */ switch (type) { - case TCG_TYPE_V64: - t1 = tcg_temp_new_vec(TCG_TYPE_V128); - t2 = tcg_temp_new_vec(TCG_TYPE_V128); - tcg_gen_dup16i_vec(t2, 0); - vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, - tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t2)); - vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, - tcgv_vec_arg(t2), tcgv_vec_arg(t2), tcgv_vec_arg(v2)); - tcg_gen_mul_vec(MO_16, t1, t1, t2); - tcg_gen_shri_vec(MO_16, t1, t1, 8); - vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8, - tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t1)); - tcg_temp_free_vec(t1); - tcg_temp_free_vec(t2); - break; + case TCG_TYPE_V64: + t1 = tcg_temp_new_vec(TCG_TYPE_V128); + t2 = tcg_temp_new_vec(TCG_TYPE_V128); + tcg_gen_dup16i_vec(t2, 0); + vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, tcgv_vec_arg(t1), tcgv_vec_arg(v1), + tcgv_vec_arg(t2)); + vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, tcgv_vec_arg(t2), tcgv_vec_arg(t2), + tcgv_vec_arg(v2)); + tcg_gen_mul_vec(MO_16, t1, t1, t2); + tcg_gen_shri_vec(MO_16, t1, t1, 8); + vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8, tcgv_vec_arg(v0), tcgv_vec_arg(t1), + tcgv_vec_arg(t1)); + tcg_temp_free_vec(t1); + tcg_temp_free_vec(t2); + break; - case TCG_TYPE_V128: - case TCG_TYPE_V256: - t1 = tcg_temp_new_vec(type); - t2 = tcg_temp_new_vec(type); - t3 = tcg_temp_new_vec(type); - t4 = tcg_temp_new_vec(type); - tcg_gen_dup16i_vec(t4, 0); - vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, - tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t4)); - vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, - tcgv_vec_arg(t2), tcgv_vec_arg(t4), tcgv_vec_arg(v2)); - vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, - tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(t4)); - vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, - tcgv_vec_arg(t4), tcgv_vec_arg(t4), tcgv_vec_arg(v2)); - tcg_gen_mul_vec(MO_16, t1, t1, t2); - tcg_gen_mul_vec(MO_16, t3, t3, t4); - tcg_gen_shri_vec(MO_16, t1, t1, 8); - tcg_gen_shri_vec(MO_16, t3, t3, 8); - vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8, - tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t3)); - tcg_temp_free_vec(t1); - tcg_temp_free_vec(t2); - tcg_temp_free_vec(t3); - tcg_temp_free_vec(t4); - break; + case TCG_TYPE_V128: + case TCG_TYPE_V256: + t1 = tcg_temp_new_vec(type); + t2 = tcg_temp_new_vec(type); + t3 = tcg_temp_new_vec(type); + t4 = tcg_temp_new_vec(type); + tcg_gen_dup16i_vec(t4, 0); + vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t4)); + vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, tcgv_vec_arg(t2), tcgv_vec_arg(t4), tcgv_vec_arg(v2)); + vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(t4)); + vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, tcgv_vec_arg(t4), tcgv_vec_arg(t4), tcgv_vec_arg(v2)); + tcg_gen_mul_vec(MO_16, t1, t1, t2); + tcg_gen_mul_vec(MO_16, t3, t3, t4); + tcg_gen_shri_vec(MO_16, t1, t1, 8); + tcg_gen_shri_vec(MO_16, t3, t3, 8); + vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8, tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t3)); + tcg_temp_free_vec(t1); + tcg_temp_free_vec(t2); + tcg_temp_free_vec(t3); + tcg_temp_free_vec(t4); + break; - default: - g_assert_not_reached(); + default: + g_assert_not_reached(); } } -static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, - TCGv_vec v1, TCGv_vec v2, TCGCond cond) -{ - enum { - NEED_SWAP = 1, - NEED_INV = 2, - NEED_BIAS = 4 - }; +static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGv_vec v2, TCGCond cond) { + enum { NEED_SWAP = 1, NEED_INV = 2, NEED_BIAS = 4 }; static const uint8_t fixups[16] = { - [0 ... 15] = -1, - [TCG_COND_EQ] = 0, - [TCG_COND_NE] = NEED_INV, - [TCG_COND_GT] = 0, - [TCG_COND_LT] = NEED_SWAP, - [TCG_COND_LE] = NEED_INV, - [TCG_COND_GE] = NEED_SWAP | NEED_INV, - [TCG_COND_GTU] = NEED_BIAS, - [TCG_COND_LTU] = NEED_BIAS | NEED_SWAP, - [TCG_COND_LEU] = NEED_BIAS | NEED_INV, - [TCG_COND_GEU] = NEED_BIAS | NEED_SWAP | NEED_INV, + [0 ... 15] = -1, + [TCG_COND_EQ] = 0, + [TCG_COND_NE] = NEED_INV, + [TCG_COND_GT] = 0, + [TCG_COND_LT] = NEED_SWAP, + [TCG_COND_LE] = NEED_INV, + [TCG_COND_GE] = NEED_SWAP | NEED_INV, + [TCG_COND_GTU] = NEED_BIAS, + [TCG_COND_LTU] = NEED_BIAS | NEED_SWAP, + [TCG_COND_LEU] = NEED_BIAS | NEED_INV, + [TCG_COND_GEU] = NEED_BIAS | NEED_SWAP | NEED_INV, }; TCGv_vec t1, t2; uint8_t fixup; @@ -3352,8 +3020,7 @@ static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, tcg_debug_assert(cond == TCG_COND_EQ || cond == TCG_COND_GT); /* Expand directly; do not recurse. */ - vec_gen_4(INDEX_op_cmp_vec, type, vece, - tcgv_vec_arg(v0), tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); + vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0), tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); if (t1) { tcg_temp_free_vec(t1); @@ -3366,10 +3033,8 @@ static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, } } -static void expand_vec_minmax(TCGType type, unsigned vece, - TCGCond cond, bool min, - TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) -{ +static void expand_vec_minmax(TCGType type, unsigned vece, TCGCond cond, bool min, TCGv_vec v0, TCGv_vec v1, + TCGv_vec v2) { TCGv_vec t1 = tcg_temp_new_vec(type); tcg_debug_assert(vece == MO_64); @@ -3379,15 +3044,12 @@ static void expand_vec_minmax(TCGType type, unsigned vece, TCGv_vec t2; t2 = v1, v1 = v2, v2 = t2; } - vec_gen_4(INDEX_op_x86_vpblendvb_vec, type, vece, - tcgv_vec_arg(v0), tcgv_vec_arg(v1), - tcgv_vec_arg(v2), tcgv_vec_arg(t1)); + vec_gen_4(INDEX_op_x86_vpblendvb_vec, type, vece, tcgv_vec_arg(v0), tcgv_vec_arg(v1), tcgv_vec_arg(v2), + tcgv_vec_arg(t1)); tcg_temp_free_vec(t1); } -void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, - TCGArg a0, ...) -{ +void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { va_list va; TCGArg a2; TCGv_vec v0, v1, v2; @@ -3398,44 +3060,44 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, a2 = va_arg(va, TCGArg); switch (opc) { - case INDEX_op_shli_vec: - case INDEX_op_shri_vec: - expand_vec_shi(type, vece, opc == INDEX_op_shri_vec, v0, v1, a2); - break; - - case INDEX_op_sari_vec: - expand_vec_sari(type, vece, v0, v1, a2); - break; - - case INDEX_op_mul_vec: - v2 = temp_tcgv_vec(arg_temp(a2)); - expand_vec_mul(type, vece, v0, v1, v2); - break; - - case INDEX_op_cmp_vec: - v2 = temp_tcgv_vec(arg_temp(a2)); - expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); - break; - - case INDEX_op_smin_vec: - v2 = temp_tcgv_vec(arg_temp(a2)); - expand_vec_minmax(type, vece, TCG_COND_GT, true, v0, v1, v2); - break; - case INDEX_op_smax_vec: - v2 = temp_tcgv_vec(arg_temp(a2)); - expand_vec_minmax(type, vece, TCG_COND_GT, false, v0, v1, v2); - break; - case INDEX_op_umin_vec: - v2 = temp_tcgv_vec(arg_temp(a2)); - expand_vec_minmax(type, vece, TCG_COND_GTU, true, v0, v1, v2); - break; - case INDEX_op_umax_vec: - v2 = temp_tcgv_vec(arg_temp(a2)); - expand_vec_minmax(type, vece, TCG_COND_GTU, false, v0, v1, v2); - break; - - default: - break; + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: + expand_vec_shi(type, vece, opc == INDEX_op_shri_vec, v0, v1, a2); + break; + + case INDEX_op_sari_vec: + expand_vec_sari(type, vece, v0, v1, a2); + break; + + case INDEX_op_mul_vec: + v2 = temp_tcgv_vec(arg_temp(a2)); + expand_vec_mul(type, vece, v0, v1, v2); + break; + + case INDEX_op_cmp_vec: + v2 = temp_tcgv_vec(arg_temp(a2)); + expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); + break; + + case INDEX_op_smin_vec: + v2 = temp_tcgv_vec(arg_temp(a2)); + expand_vec_minmax(type, vece, TCG_COND_GT, true, v0, v1, v2); + break; + case INDEX_op_smax_vec: + v2 = temp_tcgv_vec(arg_temp(a2)); + expand_vec_minmax(type, vece, TCG_COND_GT, false, v0, v1, v2); + break; + case INDEX_op_umin_vec: + v2 = temp_tcgv_vec(arg_temp(a2)); + expand_vec_minmax(type, vece, TCG_COND_GTU, true, v0, v1, v2); + break; + case INDEX_op_umax_vec: + v2 = temp_tcgv_vec(arg_temp(a2)); + expand_vec_minmax(type, vece, TCG_COND_GTU, false, v0, v1, v2); + break; + + default: + break; } va_end(va); @@ -3443,49 +3105,36 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, static const int tcg_target_callee_save_regs[] = { #if TCG_TARGET_REG_BITS == 64 - TCG_REG_RBP, - TCG_REG_RBX, + TCG_REG_RBP, TCG_REG_RBX, #if defined(_WIN64) - TCG_REG_RDI, - TCG_REG_RSI, + TCG_REG_RDI, TCG_REG_RSI, #endif - TCG_REG_R12, - TCG_REG_R13, - TCG_REG_R14, /* Currently used for the global env. */ + TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, /* Currently used for the global env. */ TCG_REG_R15, #else TCG_REG_EBP, /* Currently used for the global env. */ - TCG_REG_EBX, - TCG_REG_ESI, - TCG_REG_EDI, + TCG_REG_EBX, TCG_REG_ESI, TCG_REG_EDI, #endif }; /* Compute frame size via macros, to share between tcg_target_qemu_prologue and tcg_register_jit. */ -#define PUSH_SIZE \ - ((1 + ARRAY_SIZE(tcg_target_callee_save_regs)) \ - * (TCG_TARGET_REG_BITS / 8)) +#define PUSH_SIZE ((1 + ARRAY_SIZE(tcg_target_callee_save_regs)) * (TCG_TARGET_REG_BITS / 8)) -#define FRAME_SIZE \ - ((PUSH_SIZE \ - + TCG_STATIC_CALL_ARGS_SIZE \ - + CPU_TEMP_BUF_NLONGS * sizeof(long) \ - + TCG_TARGET_STACK_ALIGN - 1) \ - & ~(TCG_TARGET_STACK_ALIGN - 1)) +#define FRAME_SIZE \ + ((PUSH_SIZE + TCG_STATIC_CALL_ARGS_SIZE + CPU_TEMP_BUF_NLONGS * sizeof(long) + TCG_TARGET_STACK_ALIGN - 1) & \ + ~(TCG_TARGET_STACK_ALIGN - 1)) /* Generate global QEMU prologue and epilogue code */ -static void tcg_target_qemu_prologue(TCGContext *s) -{ +static void tcg_target_qemu_prologue(TCGContext *s) { int i, stack_addend; /* TB prologue */ /* Reserve some stack space, also for TCG temps. */ stack_addend = FRAME_SIZE - PUSH_SIZE; - tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, - CPU_TEMP_BUF_NLONGS * sizeof(long)); + tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, CPU_TEMP_BUF_NLONGS * sizeof(long)); /* Save all callee saved registers. */ for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { @@ -3493,20 +3142,18 @@ static void tcg_target_qemu_prologue(TCGContext *s) } #if TCG_TARGET_REG_BITS == 32 - tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, - (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4); tcg_out_addi(s, TCG_REG_ESP, -stack_addend); /* jmp *tb. */ tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP, - (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4 - + stack_addend); + (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4 + stack_addend); #else -# if !defined(CONFIG_SOFTMMU) && TCG_TARGET_REG_BITS == 64 +#if !defined(CONFIG_SOFTMMU) && TCG_TARGET_REG_BITS == 64 if (guest_base) { int seg = setup_guest_base_seg(); if (seg != 0) { x86_guest_base_seg = seg; - } else if (guest_base == (int32_t)guest_base) { + } else if (guest_base == (int32_t) guest_base) { x86_guest_base_offset = guest_base; } else { /* Choose R12 because, as a base, it requires a SIB byte. */ @@ -3515,7 +3162,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, x86_guest_base_index); } } -# endif +#endif tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); tcg_out_addi(s, TCG_REG_ESP, -stack_addend); /* jmp *tb. */ @@ -3543,8 +3190,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_opc(s, OPC_RET, 0, 0, 0); } -static void tcg_out_nop_fill(tcg_insn_unit *p, int count) -{ +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) { memset(p, 0x90, count); } @@ -3580,8 +3226,7 @@ void tcg_target_force_tb_exit(uintptr_t gen_code, uintptr_t max_addr) { *code++ = 0xe1; } -static void tcg_target_init(TCGContext *s) -{ +static void tcg_target_init(TCGContext *s) { #ifdef CONFIG_CPUID_H unsigned a, b, c, d, b7 = 0; int max = __get_cpuid_max(0, 0); @@ -3614,7 +3259,7 @@ static void tcg_target_init(TCGContext *s) /* The xgetbv instruction is not available to older versions of * the assembler, so we encode the instruction manually. */ - asm(".byte 0x0f, 0x01, 0xd0" : "=a" (xcrl), "=d" (xcrh) : "c" (0)); + asm(".byte 0x0f, 0x01, 0xd0" : "=a"(xcrl), "=d"(xcrh) : "c"(0)); if ((xcrl & 6) == 6) { have_avx1 = (c & bit_AVX) != 0; have_avx2 = (b7 & bit_AVX2) != 0; @@ -3671,68 +3316,59 @@ typedef struct { QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); #if !defined(__ELF__) - /* Host machine without ELF. */ +/* Host machine without ELF. */ #elif TCG_TARGET_REG_BITS == 64 #define ELF_HOST_MACHINE EM_X86_64 -static const DebugFrame debug_frame = { - .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ - .h.cie.id = -1, - .h.cie.version = 1, - .h.cie.code_align = 1, - .h.cie.data_align = 0x78, /* sleb128 -8 */ - .h.cie.return_column = 16, - - /* Total FDE size does not include the "len" member. */ - .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), - - .fde_def_cfa = { - 12, 7, /* DW_CFA_def_cfa %rsp, ... */ - (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ - (FRAME_SIZE >> 7) - }, - .fde_reg_ofs = { - 0x90, 1, /* DW_CFA_offset, %rip, -8 */ - /* The following ordering must match tcg_target_callee_save_regs. */ - 0x86, 2, /* DW_CFA_offset, %rbp, -16 */ - 0x83, 3, /* DW_CFA_offset, %rbx, -24 */ - 0x8c, 4, /* DW_CFA_offset, %r12, -32 */ - 0x8d, 5, /* DW_CFA_offset, %r13, -40 */ - 0x8e, 6, /* DW_CFA_offset, %r14, -48 */ - 0x8f, 7, /* DW_CFA_offset, %r15, -56 */ - } -}; +static const DebugFrame debug_frame = {.h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ + .h.cie.id = -1, + .h.cie.version = 1, + .h.cie.code_align = 1, + .h.cie.data_align = 0x78, /* sleb128 -8 */ + .h.cie.return_column = 16, + + /* Total FDE size does not include the "len" member. */ + .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), + + .fde_def_cfa = {12, 7, /* DW_CFA_def_cfa %rsp, ... */ + (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ + (FRAME_SIZE >> 7)}, + .fde_reg_ofs = { + 0x90, 1, /* DW_CFA_offset, %rip, -8 */ + /* The following ordering must match tcg_target_callee_save_regs. */ + 0x86, 2, /* DW_CFA_offset, %rbp, -16 */ + 0x83, 3, /* DW_CFA_offset, %rbx, -24 */ + 0x8c, 4, /* DW_CFA_offset, %r12, -32 */ + 0x8d, 5, /* DW_CFA_offset, %r13, -40 */ + 0x8e, 6, /* DW_CFA_offset, %r14, -48 */ + 0x8f, 7, /* DW_CFA_offset, %r15, -56 */ + }}; #else #define ELF_HOST_MACHINE EM_386 -static const DebugFrame debug_frame = { - .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ - .h.cie.id = -1, - .h.cie.version = 1, - .h.cie.code_align = 1, - .h.cie.data_align = 0x7c, /* sleb128 -4 */ - .h.cie.return_column = 8, - - /* Total FDE size does not include the "len" member. */ - .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), - - .fde_def_cfa = { - 12, 4, /* DW_CFA_def_cfa %esp, ... */ - (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ - (FRAME_SIZE >> 7) - }, - .fde_reg_ofs = { - 0x88, 1, /* DW_CFA_offset, %eip, -4 */ - /* The following ordering must match tcg_target_callee_save_regs. */ - 0x85, 2, /* DW_CFA_offset, %ebp, -8 */ - 0x83, 3, /* DW_CFA_offset, %ebx, -12 */ - 0x86, 4, /* DW_CFA_offset, %esi, -16 */ - 0x87, 5, /* DW_CFA_offset, %edi, -20 */ - } -}; +static const DebugFrame debug_frame = {.h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ + .h.cie.id = -1, + .h.cie.version = 1, + .h.cie.code_align = 1, + .h.cie.data_align = 0x7c, /* sleb128 -4 */ + .h.cie.return_column = 8, + + /* Total FDE size does not include the "len" member. */ + .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), + + .fde_def_cfa = {12, 4, /* DW_CFA_def_cfa %esp, ... */ + (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ + (FRAME_SIZE >> 7)}, + .fde_reg_ofs = { + 0x88, 1, /* DW_CFA_offset, %eip, -4 */ + /* The following ordering must match tcg_target_callee_save_regs. */ + 0x85, 2, /* DW_CFA_offset, %ebp, -8 */ + 0x83, 3, /* DW_CFA_offset, %ebx, -12 */ + 0x86, 4, /* DW_CFA_offset, %esi, -16 */ + 0x87, 5, /* DW_CFA_offset, %edi, -20 */ + }}; #endif #if defined(ELF_HOST_MACHINE) -void tcg_register_jit(void *buf, size_t buf_size) -{ +void tcg_register_jit(void *buf, size_t buf_size) { tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } #endif diff --git a/src/optimize.c b/src/optimize.c index 84b454b..6c25d11 100644 --- a/src/optimize.c +++ b/src/optimize.c @@ -28,19 +28,15 @@ typedef union MMXReg MMXReg; typedef union XMMReg XMMReg; -#include #include +#include #include -#define CASE_OP_32_64(x) \ - glue(glue(case INDEX_op_, x), _i32): \ - glue(glue(case INDEX_op_, x), _i64) +#define CASE_OP_32_64(x) glue(glue(case INDEX_op_, x), _i32) : glue(glue(case INDEX_op_, x), _i64) -#define CASE_OP_32_64_VEC(x) \ - glue(glue(case INDEX_op_, x), _i32): \ - glue(glue(case INDEX_op_, x), _i64): \ - glue(glue(case INDEX_op_, x), _vec) +#define CASE_OP_32_64_VEC(x) \ + glue(glue(case INDEX_op_, x), _i32) : glue(glue(case INDEX_op_, x), _i64) : glue(glue(case INDEX_op_, x), _vec) struct tcg_temp_info { bool is_const; @@ -50,34 +46,28 @@ struct tcg_temp_info { tcg_target_ulong mask; }; -static inline struct tcg_temp_info *ts_info(TCGTemp *ts) -{ +static inline struct tcg_temp_info *ts_info(TCGTemp *ts) { return ts->state_ptr; } -static inline struct tcg_temp_info *arg_info(TCGArg arg) -{ +static inline struct tcg_temp_info *arg_info(TCGArg arg) { return ts_info(arg_temp(arg)); } -static inline bool ts_is_const(TCGTemp *ts) -{ +static inline bool ts_is_const(TCGTemp *ts) { return ts_info(ts)->is_const; } -static inline bool arg_is_const(TCGArg arg) -{ +static inline bool arg_is_const(TCGArg arg) { return ts_is_const(arg_temp(arg)); } -static inline bool ts_is_copy(TCGTemp *ts) -{ +static inline bool ts_is_copy(TCGTemp *ts) { return ts_info(ts)->next_copy != ts; } /* Reset TEMP's state, possibly removing the temp for the list of copies. */ -static void reset_ts(TCGTemp *ts) -{ +static void reset_ts(TCGTemp *ts) { struct tcg_temp_info *ti = ts_info(ts); struct tcg_temp_info *pi = ts_info(ti->prev_copy); struct tcg_temp_info *ni = ts_info(ti->next_copy); @@ -90,15 +80,12 @@ static void reset_ts(TCGTemp *ts) ti->mask = -1; } -static void reset_temp(TCGArg arg) -{ +static void reset_temp(TCGArg arg) { reset_ts(arg_temp(arg)); } /* Initialize and activate a temporary. */ -static void init_ts_info(struct tcg_temp_info *infos, - TCGTempSet *temps_used, TCGTemp *ts) -{ +static void init_ts_info(struct tcg_temp_info *infos, TCGTempSet *temps_used, TCGTemp *ts) { size_t idx = temp_idx(ts); if (!test_bit(idx, temps_used->l)) { struct tcg_temp_info *ti = &infos[idx]; @@ -112,14 +99,11 @@ static void init_ts_info(struct tcg_temp_info *infos, } } -static void init_arg_info(struct tcg_temp_info *infos, - TCGTempSet *temps_used, TCGArg arg) -{ +static void init_arg_info(struct tcg_temp_info *infos, TCGTempSet *temps_used, TCGArg arg) { init_ts_info(infos, temps_used, arg_temp(arg)); } -static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts) -{ +static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts) { TCGTemp *i; /* If this is already a global, we can't do better. */ @@ -147,8 +131,7 @@ static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts) return ts; } -static bool ts_are_copies(TCGTemp *ts1, TCGTemp *ts2) -{ +static bool ts_are_copies(TCGTemp *ts1, TCGTemp *ts2) { TCGTemp *i; if (ts1 == ts2) { @@ -168,13 +151,11 @@ static bool ts_are_copies(TCGTemp *ts1, TCGTemp *ts2) return false; } -static bool args_are_copies(TCGArg arg1, TCGArg arg2) -{ +static bool args_are_copies(TCGArg arg1, TCGArg arg2) { return ts_are_copies(arg_temp(arg1), arg_temp(arg2)); } -static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg val) -{ +static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg val) { const TCGOpDef *def; TCGOpcode new_op; tcg_target_ulong mask; @@ -204,8 +185,7 @@ static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg val) di->mask = mask; } -static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) -{ +static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) { TCGTemp *dst_ts = arg_temp(dst); TCGTemp *src_ts = arg_temp(src); const TCGOpDef *def; @@ -254,260 +234,233 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) } } -static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y) -{ +static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y) { uint64_t l64, h64; switch (op) { - CASE_OP_32_64(add): - return x + y; - - CASE_OP_32_64(sub): - return x - y; - - CASE_OP_32_64(mul): - return x * y; - - CASE_OP_32_64(and): - return x & y; - - CASE_OP_32_64(or): - return x | y; + CASE_OP_32_64(add) : return x + y; - CASE_OP_32_64(xor): - return x ^ y; + CASE_OP_32_64(sub) : return x - y; - case INDEX_op_shl_i32: - return (uint32_t)x << (y & 31); + CASE_OP_32_64(mul) : return x * y; - case INDEX_op_shl_i64: - return (uint64_t)x << (y & 63); + CASE_OP_32_64(and) : return x & y; - case INDEX_op_shr_i32: - return (uint32_t)x >> (y & 31); + CASE_OP_32_64(or) : return x | y; - case INDEX_op_shr_i64: - return (uint64_t)x >> (y & 63); + CASE_OP_32_64 (xor) : return x ^ y; - case INDEX_op_sar_i32: - return (int32_t)x >> (y & 31); + case INDEX_op_shl_i32: + return (uint32_t) x << (y & 31); - case INDEX_op_sar_i64: - return (int64_t)x >> (y & 63); + case INDEX_op_shl_i64: + return (uint64_t) x << (y & 63); - case INDEX_op_rotr_i32: - return ror32(x, y & 31); + case INDEX_op_shr_i32: + return (uint32_t) x >> (y & 31); - case INDEX_op_rotr_i64: - return ror64(x, y & 63); + case INDEX_op_shr_i64: + return (uint64_t) x >> (y & 63); - case INDEX_op_rotl_i32: - return rol32(x, y & 31); + case INDEX_op_sar_i32: + return (int32_t) x >> (y & 31); - case INDEX_op_rotl_i64: - return rol64(x, y & 63); + case INDEX_op_sar_i64: + return (int64_t) x >> (y & 63); - CASE_OP_32_64(not): - return ~x; + case INDEX_op_rotr_i32: + return ror32(x, y & 31); - CASE_OP_32_64(neg): - return -x; + case INDEX_op_rotr_i64: + return ror64(x, y & 63); - CASE_OP_32_64(andc): - return x & ~y; + case INDEX_op_rotl_i32: + return rol32(x, y & 31); - CASE_OP_32_64(orc): - return x | ~y; + case INDEX_op_rotl_i64: + return rol64(x, y & 63); - CASE_OP_32_64(eqv): - return ~(x ^ y); + CASE_OP_32_64(not) : return ~x; - CASE_OP_32_64(nand): - return ~(x & y); + CASE_OP_32_64(neg) : return -x; - CASE_OP_32_64(nor): - return ~(x | y); + CASE_OP_32_64(andc) : return x & ~y; - case INDEX_op_clz_i32: - return (uint32_t)x ? clz32(x) : y; + CASE_OP_32_64(orc) : return x | ~y; - case INDEX_op_clz_i64: - return x ? clz64(x) : y; + CASE_OP_32_64(eqv) : return ~(x ^ y); - case INDEX_op_ctz_i32: - return (uint32_t)x ? ctz32(x) : y; + CASE_OP_32_64(nand) : return ~(x & y); - case INDEX_op_ctz_i64: - return x ? ctz64(x) : y; + CASE_OP_32_64(nor) : return ~(x | y); - case INDEX_op_ctpop_i32: - return ctpop32(x); + case INDEX_op_clz_i32: + return (uint32_t) x ? clz32(x) : y; - case INDEX_op_ctpop_i64: - return ctpop64(x); + case INDEX_op_clz_i64: + return x ? clz64(x) : y; - CASE_OP_32_64(ext8s): - return (int8_t)x; + case INDEX_op_ctz_i32: + return (uint32_t) x ? ctz32(x) : y; - CASE_OP_32_64(ext16s): - return (int16_t)x; + case INDEX_op_ctz_i64: + return x ? ctz64(x) : y; - CASE_OP_32_64(ext8u): - return (uint8_t)x; + case INDEX_op_ctpop_i32: + return ctpop32(x); - CASE_OP_32_64(ext16u): - return (uint16_t)x; + case INDEX_op_ctpop_i64: + return ctpop64(x); - CASE_OP_32_64(bswap16): - return bswap_16(x); + CASE_OP_32_64(ext8s) : return (int8_t) x; - CASE_OP_32_64(bswap32): - return bswap_32(x); + CASE_OP_32_64(ext16s) : return (int16_t) x; - case INDEX_op_bswap64_i64: - return bswap_64(x); + CASE_OP_32_64(ext8u) : return (uint8_t) x; - case INDEX_op_ext_i32_i64: - case INDEX_op_ext32s_i64: - return (int32_t)x; + CASE_OP_32_64(ext16u) : return (uint16_t) x; - case INDEX_op_extu_i32_i64: - case INDEX_op_extrl_i64_i32: - case INDEX_op_ext32u_i64: - return (uint32_t)x; + CASE_OP_32_64(bswap16) : return bswap_16(x); - case INDEX_op_extrh_i64_i32: - return (uint64_t)x >> 32; + CASE_OP_32_64(bswap32) : return bswap_32(x); - case INDEX_op_muluh_i32: - return ((uint64_t)(uint32_t)x * (uint32_t)y) >> 32; - case INDEX_op_mulsh_i32: - return ((int64_t)(int32_t)x * (int32_t)y) >> 32; + case INDEX_op_bswap64_i64: + return bswap_64(x); - case INDEX_op_muluh_i64: - mulu64(&l64, &h64, x, y); - return h64; - case INDEX_op_mulsh_i64: - muls64(&l64, &h64, x, y); - return h64; + case INDEX_op_ext_i32_i64: + case INDEX_op_ext32s_i64: + return (int32_t) x; - case INDEX_op_div_i32: - /* Avoid crashing on divide by zero, otherwise undefined. */ - return (int32_t)x / ((int32_t)y ? : 1); - case INDEX_op_divu_i32: - return (uint32_t)x / ((uint32_t)y ? : 1); - case INDEX_op_div_i64: - return (int64_t)x / ((int64_t)y ? : 1); - case INDEX_op_divu_i64: - return (uint64_t)x / ((uint64_t)y ? : 1); + case INDEX_op_extu_i32_i64: + case INDEX_op_extrl_i64_i32: + case INDEX_op_ext32u_i64: + return (uint32_t) x; - case INDEX_op_rem_i32: - return (int32_t)x % ((int32_t)y ? : 1); - case INDEX_op_remu_i32: - return (uint32_t)x % ((uint32_t)y ? : 1); - case INDEX_op_rem_i64: - return (int64_t)x % ((int64_t)y ? : 1); - case INDEX_op_remu_i64: - return (uint64_t)x % ((uint64_t)y ? : 1); + case INDEX_op_extrh_i64_i32: + return (uint64_t) x >> 32; + + case INDEX_op_muluh_i32: + return ((uint64_t)(uint32_t) x * (uint32_t) y) >> 32; + case INDEX_op_mulsh_i32: + return ((int64_t)(int32_t) x * (int32_t) y) >> 32; + + case INDEX_op_muluh_i64: + mulu64(&l64, &h64, x, y); + return h64; + case INDEX_op_mulsh_i64: + muls64(&l64, &h64, x, y); + return h64; + + case INDEX_op_div_i32: + /* Avoid crashing on divide by zero, otherwise undefined. */ + return (int32_t) x / ((int32_t) y ?: 1); + case INDEX_op_divu_i32: + return (uint32_t) x / ((uint32_t) y ?: 1); + case INDEX_op_div_i64: + return (int64_t) x / ((int64_t) y ?: 1); + case INDEX_op_divu_i64: + return (uint64_t) x / ((uint64_t) y ?: 1); + + case INDEX_op_rem_i32: + return (int32_t) x % ((int32_t) y ?: 1); + case INDEX_op_remu_i32: + return (uint32_t) x % ((uint32_t) y ?: 1); + case INDEX_op_rem_i64: + return (int64_t) x % ((int64_t) y ?: 1); + case INDEX_op_remu_i64: + return (uint64_t) x % ((uint64_t) y ?: 1); - default: - fprintf(stderr, - "Unrecognized operation %d in do_constant_folding.\n", op); - tcg_abort(); + default: + fprintf(stderr, "Unrecognized operation %d in do_constant_folding.\n", op); + tcg_abort(); } } -static TCGArg do_constant_folding(TCGOpcode op, TCGArg x, TCGArg y) -{ +static TCGArg do_constant_folding(TCGOpcode op, TCGArg x, TCGArg y) { const TCGOpDef *def = &tcg_op_defs[op]; TCGArg res = do_constant_folding_2(op, x, y); if (!(def->flags & TCG_OPF_64BIT)) { - res = (int32_t)res; + res = (int32_t) res; } return res; } -static bool do_constant_folding_cond_32(uint32_t x, uint32_t y, TCGCond c) -{ +static bool do_constant_folding_cond_32(uint32_t x, uint32_t y, TCGCond c) { switch (c) { - case TCG_COND_EQ: - return x == y; - case TCG_COND_NE: - return x != y; - case TCG_COND_LT: - return (int32_t)x < (int32_t)y; - case TCG_COND_GE: - return (int32_t)x >= (int32_t)y; - case TCG_COND_LE: - return (int32_t)x <= (int32_t)y; - case TCG_COND_GT: - return (int32_t)x > (int32_t)y; - case TCG_COND_LTU: - return x < y; - case TCG_COND_GEU: - return x >= y; - case TCG_COND_LEU: - return x <= y; - case TCG_COND_GTU: - return x > y; - default: - tcg_abort(); + case TCG_COND_EQ: + return x == y; + case TCG_COND_NE: + return x != y; + case TCG_COND_LT: + return (int32_t) x < (int32_t) y; + case TCG_COND_GE: + return (int32_t) x >= (int32_t) y; + case TCG_COND_LE: + return (int32_t) x <= (int32_t) y; + case TCG_COND_GT: + return (int32_t) x > (int32_t) y; + case TCG_COND_LTU: + return x < y; + case TCG_COND_GEU: + return x >= y; + case TCG_COND_LEU: + return x <= y; + case TCG_COND_GTU: + return x > y; + default: + tcg_abort(); } } -static bool do_constant_folding_cond_64(uint64_t x, uint64_t y, TCGCond c) -{ +static bool do_constant_folding_cond_64(uint64_t x, uint64_t y, TCGCond c) { switch (c) { - case TCG_COND_EQ: - return x == y; - case TCG_COND_NE: - return x != y; - case TCG_COND_LT: - return (int64_t)x < (int64_t)y; - case TCG_COND_GE: - return (int64_t)x >= (int64_t)y; - case TCG_COND_LE: - return (int64_t)x <= (int64_t)y; - case TCG_COND_GT: - return (int64_t)x > (int64_t)y; - case TCG_COND_LTU: - return x < y; - case TCG_COND_GEU: - return x >= y; - case TCG_COND_LEU: - return x <= y; - case TCG_COND_GTU: - return x > y; - default: - tcg_abort(); + case TCG_COND_EQ: + return x == y; + case TCG_COND_NE: + return x != y; + case TCG_COND_LT: + return (int64_t) x < (int64_t) y; + case TCG_COND_GE: + return (int64_t) x >= (int64_t) y; + case TCG_COND_LE: + return (int64_t) x <= (int64_t) y; + case TCG_COND_GT: + return (int64_t) x > (int64_t) y; + case TCG_COND_LTU: + return x < y; + case TCG_COND_GEU: + return x >= y; + case TCG_COND_LEU: + return x <= y; + case TCG_COND_GTU: + return x > y; + default: + tcg_abort(); } } -static bool do_constant_folding_cond_eq(TCGCond c) -{ +static bool do_constant_folding_cond_eq(TCGCond c) { switch (c) { - case TCG_COND_GT: - case TCG_COND_LTU: - case TCG_COND_LT: - case TCG_COND_GTU: - case TCG_COND_NE: - return 0; - case TCG_COND_GE: - case TCG_COND_GEU: - case TCG_COND_LE: - case TCG_COND_LEU: - case TCG_COND_EQ: - return 1; - default: - tcg_abort(); + case TCG_COND_GT: + case TCG_COND_LTU: + case TCG_COND_LT: + case TCG_COND_GTU: + case TCG_COND_NE: + return 0; + case TCG_COND_GE: + case TCG_COND_GEU: + case TCG_COND_LE: + case TCG_COND_LEU: + case TCG_COND_EQ: + return 1; + default: + tcg_abort(); } } /* Return 2 if the condition can't be simplified, and the result of the condition (0 or 1) if it can */ -static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x, - TCGArg y, TCGCond c) -{ +static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x, TCGArg y, TCGCond c) { tcg_target_ulong xv = arg_info(x)->val; tcg_target_ulong yv = arg_info(y)->val; if (arg_is_const(x) && arg_is_const(y)) { @@ -522,12 +475,12 @@ static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x, return do_constant_folding_cond_eq(c); } else if (arg_is_const(y) && yv == 0) { switch (c) { - case TCG_COND_LTU: - return 0; - case TCG_COND_GEU: - return 1; - default: - return 2; + case TCG_COND_LTU: + return 0; + case TCG_COND_GEU: + return 1; + default: + return 2; } } return 2; @@ -535,8 +488,7 @@ static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x, /* Return 2 if the condition can't be simplified, and the result of the condition (0 or 1) if it can */ -static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c) -{ +static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c) { TCGArg al = p1[0], ah = p1[1]; TCGArg bl = p2[0], bh = p2[1]; @@ -553,12 +505,12 @@ static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c) } if (b == 0) { switch (c) { - case TCG_COND_LTU: - return 0; - case TCG_COND_GEU: - return 1; - default: - break; + case TCG_COND_LTU: + return 0; + case TCG_COND_GEU: + return 1; + default: + break; } } } @@ -568,8 +520,7 @@ static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c) return 2; } -static bool swap_commutative(TCGArg dest, TCGArg *p1, TCGArg *p2) -{ +static bool swap_commutative(TCGArg dest, TCGArg *p1, TCGArg *p2) { TCGArg a1 = *p1, a2 = *p2; int sum = 0; sum += arg_is_const(a1); @@ -585,8 +536,7 @@ static bool swap_commutative(TCGArg dest, TCGArg *p1, TCGArg *p2) return false; } -static bool swap_commutative2(TCGArg *p1, TCGArg *p2) -{ +static bool swap_commutative2(TCGArg *p1, TCGArg *p2) { int sum = 0; sum += arg_is_const(p1[0]); sum += arg_is_const(p1[1]); @@ -602,8 +552,7 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2) } /* Propagate constants and copies, fold constant expressions. */ -void tcg_optimize(TCGContext *s) -{ +void tcg_optimize(TCGContext *s) { int nb_temps, nb_globals; TCGOp *op, *op_next, *prev_mb = NULL; struct tcg_temp_info *infos; @@ -655,30 +604,26 @@ void tcg_optimize(TCGContext *s) /* For commutative operations make constant second argument */ switch (opc) { - CASE_OP_32_64_VEC(add): - CASE_OP_32_64_VEC(mul): - CASE_OP_32_64_VEC(and): - CASE_OP_32_64_VEC(or): - CASE_OP_32_64_VEC(xor): - CASE_OP_32_64(eqv): - CASE_OP_32_64(nand): - CASE_OP_32_64(nor): - CASE_OP_32_64(muluh): - CASE_OP_32_64(mulsh): - swap_commutative(op->args[0], &op->args[1], &op->args[2]); + CASE_OP_32_64_VEC(add) + : CASE_OP_32_64_VEC(mul) + : CASE_OP_32_64_VEC(and) + : CASE_OP_32_64_VEC(or) + : CASE_OP_32_64_VEC (xor) + : CASE_OP_32_64(eqv) + : CASE_OP_32_64(nand) + : CASE_OP_32_64(nor) + : CASE_OP_32_64(muluh) + : CASE_OP_32_64(mulsh) : swap_commutative(op->args[0], &op->args[1], &op->args[2]); break; - CASE_OP_32_64(brcond): - if (swap_commutative(-1, &op->args[0], &op->args[1])) { + CASE_OP_32_64(brcond) : if (swap_commutative(-1, &op->args[0], &op->args[1])) { op->args[2] = tcg_swap_cond(op->args[2]); } break; - CASE_OP_32_64(setcond): - if (swap_commutative(op->args[0], &op->args[1], &op->args[2])) { + CASE_OP_32_64(setcond) : if (swap_commutative(op->args[0], &op->args[1], &op->args[2])) { op->args[3] = tcg_swap_cond(op->args[3]); } break; - CASE_OP_32_64(movcond): - if (swap_commutative(-1, &op->args[1], &op->args[2])) { + CASE_OP_32_64(movcond) : if (swap_commutative(-1, &op->args[1], &op->args[2])) { op->args[5] = tcg_swap_cond(op->args[5]); } /* For movcond, we canonicalize the "false" input reg to match @@ -688,44 +633,38 @@ void tcg_optimize(TCGContext *s) op->args[5] = tcg_invert_cond(op->args[5]); } break; - CASE_OP_32_64(add2): - swap_commutative(op->args[0], &op->args[2], &op->args[4]); + CASE_OP_32_64(add2) : swap_commutative(op->args[0], &op->args[2], &op->args[4]); swap_commutative(op->args[1], &op->args[3], &op->args[5]); break; - CASE_OP_32_64(mulu2): - CASE_OP_32_64(muls2): - swap_commutative(op->args[0], &op->args[2], &op->args[3]); - break; - case INDEX_op_brcond2_i32: - if (swap_commutative2(&op->args[0], &op->args[2])) { - op->args[4] = tcg_swap_cond(op->args[4]); - } - break; - case INDEX_op_setcond2_i32: - if (swap_commutative2(&op->args[1], &op->args[3])) { - op->args[5] = tcg_swap_cond(op->args[5]); - } - break; - default: + CASE_OP_32_64(mulu2) : CASE_OP_32_64(muls2) : swap_commutative(op->args[0], &op->args[2], &op->args[3]); break; + case INDEX_op_brcond2_i32: + if (swap_commutative2(&op->args[0], &op->args[2])) { + op->args[4] = tcg_swap_cond(op->args[4]); + } + break; + case INDEX_op_setcond2_i32: + if (swap_commutative2(&op->args[1], &op->args[3])) { + op->args[5] = tcg_swap_cond(op->args[5]); + } + break; + default: + break; } /* Simplify expressions for "shift/rot r, 0, a => movi r, 0", and "sub r, 0, a => neg r, a" case. */ switch (opc) { - CASE_OP_32_64(shl): - CASE_OP_32_64(shr): - CASE_OP_32_64(sar): - CASE_OP_32_64(rotl): - CASE_OP_32_64(rotr): - if (arg_is_const(op->args[1]) - && arg_info(op->args[1])->val == 0) { + CASE_OP_32_64(shl) + : CASE_OP_32_64(shr) + : CASE_OP_32_64(sar) + : CASE_OP_32_64(rotl) + : CASE_OP_32_64(rotr) : if (arg_is_const(op->args[1]) && arg_info(op->args[1])->val == 0) { tcg_opt_gen_movi(s, op, op->args[0], 0); continue; } break; - CASE_OP_32_64_VEC(sub): - { + CASE_OP_32_64_VEC(sub) : { TCGOpcode neg_op; bool have_neg; @@ -746,8 +685,7 @@ void tcg_optimize(TCGContext *s) if (!have_neg) { break; } - if (arg_is_const(op->args[1]) - && arg_info(op->args[1])->val == 0) { + if (arg_is_const(op->args[1]) && arg_info(op->args[1])->val == 0) { op->opc = neg_op; reset_temp(op->args[0]); op->args[1] = op->args[2]; @@ -755,98 +693,85 @@ void tcg_optimize(TCGContext *s) } } break; - CASE_OP_32_64_VEC(xor): - CASE_OP_32_64(nand): - if (!arg_is_const(op->args[1]) - && arg_is_const(op->args[2]) - && arg_info(op->args[2])->val == -1) { + CASE_OP_32_64_VEC (xor) + : CASE_OP_32_64(nand) + : if (!arg_is_const(op->args[1]) && arg_is_const(op->args[2]) && arg_info(op->args[2])->val == -1) { i = 1; goto try_not; } break; - CASE_OP_32_64(nor): - if (!arg_is_const(op->args[1]) - && arg_is_const(op->args[2]) - && arg_info(op->args[2])->val == 0) { + CASE_OP_32_64(nor) + : if (!arg_is_const(op->args[1]) && arg_is_const(op->args[2]) && arg_info(op->args[2])->val == 0) { i = 1; goto try_not; } break; - CASE_OP_32_64_VEC(andc): - if (!arg_is_const(op->args[2]) - && arg_is_const(op->args[1]) - && arg_info(op->args[1])->val == -1) { + CASE_OP_32_64_VEC(andc) + : if (!arg_is_const(op->args[2]) && arg_is_const(op->args[1]) && arg_info(op->args[1])->val == -1) { i = 2; goto try_not; } break; - CASE_OP_32_64_VEC(orc): - CASE_OP_32_64(eqv): - if (!arg_is_const(op->args[2]) - && arg_is_const(op->args[1]) - && arg_info(op->args[1])->val == 0) { + CASE_OP_32_64_VEC(orc) + : CASE_OP_32_64(eqv) + : if (!arg_is_const(op->args[2]) && arg_is_const(op->args[1]) && arg_info(op->args[1])->val == 0) { i = 2; goto try_not; } break; - try_not: - { - TCGOpcode not_op; - bool have_not; - - if (def->flags & TCG_OPF_VECTOR) { - not_op = INDEX_op_not_vec; - have_not = TCG_TARGET_HAS_not_vec; - } else if (def->flags & TCG_OPF_64BIT) { - not_op = INDEX_op_not_i64; - have_not = TCG_TARGET_HAS_not_i64; - } else { - not_op = INDEX_op_not_i32; - have_not = TCG_TARGET_HAS_not_i32; - } - if (!have_not) { - break; - } - op->opc = not_op; - reset_temp(op->args[0]); - op->args[1] = op->args[i]; - continue; + try_not : { + TCGOpcode not_op; + bool have_not; + + if (def->flags & TCG_OPF_VECTOR) { + not_op = INDEX_op_not_vec; + have_not = TCG_TARGET_HAS_not_vec; + } else if (def->flags & TCG_OPF_64BIT) { + not_op = INDEX_op_not_i64; + have_not = TCG_TARGET_HAS_not_i64; + } else { + not_op = INDEX_op_not_i32; + have_not = TCG_TARGET_HAS_not_i32; + } + if (!have_not) { + break; } + op->opc = not_op; + reset_temp(op->args[0]); + op->args[1] = op->args[i]; + continue; + } default: break; } /* Simplify expression for "op r, a, const => mov r, a" cases */ switch (opc) { - CASE_OP_32_64_VEC(add): - CASE_OP_32_64_VEC(sub): - CASE_OP_32_64_VEC(or): - CASE_OP_32_64_VEC(xor): - CASE_OP_32_64_VEC(andc): - CASE_OP_32_64(shl): - CASE_OP_32_64(shr): - CASE_OP_32_64(sar): - CASE_OP_32_64(rotl): - CASE_OP_32_64(rotr): - if (!arg_is_const(op->args[1]) - && arg_is_const(op->args[2]) - && arg_info(op->args[2])->val == 0) { + CASE_OP_32_64_VEC(add) + : CASE_OP_32_64_VEC(sub) + : CASE_OP_32_64_VEC(or) + : CASE_OP_32_64_VEC (xor) + : CASE_OP_32_64_VEC(andc) + : CASE_OP_32_64(shl) + : CASE_OP_32_64(shr) + : CASE_OP_32_64(sar) + : CASE_OP_32_64(rotl) + : CASE_OP_32_64(rotr) + : if (!arg_is_const(op->args[1]) && arg_is_const(op->args[2]) && arg_info(op->args[2])->val == 0) { tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); continue; } break; - CASE_OP_32_64_VEC(and): - CASE_OP_32_64_VEC(orc): - CASE_OP_32_64(eqv): - if (!arg_is_const(op->args[1]) - && arg_is_const(op->args[2]) - && arg_info(op->args[2])->val == -1) { + CASE_OP_32_64_VEC(and) + : CASE_OP_32_64_VEC(orc) + : CASE_OP_32_64(eqv) + : if (!arg_is_const(op->args[1]) && arg_is_const(op->args[2]) && arg_info(op->args[2])->val == -1) { tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); continue; } break; - default: - break; + default: + break; } /* Simplify using known-zero bits. Currently only ops with a single @@ -854,177 +779,158 @@ void tcg_optimize(TCGContext *s) mask = -1; affected = -1; switch (opc) { - CASE_OP_32_64(ext8s): - if ((arg_info(op->args[1])->mask & 0x80) != 0) { - break; - } - CASE_OP_32_64(ext8u): - mask = 0xff; - goto and_const; - CASE_OP_32_64(ext16s): - if ((arg_info(op->args[1])->mask & 0x8000) != 0) { + CASE_OP_32_64(ext8s) : if ((arg_info(op->args[1])->mask & 0x80) != 0) { break; } - CASE_OP_32_64(ext16u): - mask = 0xffff; + CASE_OP_32_64(ext8u) : mask = 0xff; goto and_const; - case INDEX_op_ext32s_i64: - if ((arg_info(op->args[1])->mask & 0x80000000) != 0) { + CASE_OP_32_64(ext16s) : if ((arg_info(op->args[1])->mask & 0x8000) != 0) { break; } - case INDEX_op_ext32u_i64: - mask = 0xffffffffU; + CASE_OP_32_64(ext16u) : mask = 0xffff; goto and_const; + case INDEX_op_ext32s_i64: + if ((arg_info(op->args[1])->mask & 0x80000000) != 0) { + break; + } + case INDEX_op_ext32u_i64: + mask = 0xffffffffU; + goto and_const; - CASE_OP_32_64(and): - mask = arg_info(op->args[2])->mask; - if (arg_is_const(op->args[2])) { - and_const: - affected = arg_info(op->args[1])->mask & ~mask; - } - mask = arg_info(op->args[1])->mask & mask; - break; + CASE_OP_32_64(and) : mask = arg_info(op->args[2])->mask; + if (arg_is_const(op->args[2])) { + and_const: + affected = arg_info(op->args[1])->mask & ~mask; + } + mask = arg_info(op->args[1])->mask & mask; + break; - case INDEX_op_ext_i32_i64: - if ((arg_info(op->args[1])->mask & 0x80000000) != 0) { + case INDEX_op_ext_i32_i64: + if ((arg_info(op->args[1])->mask & 0x80000000) != 0) { + break; + } + case INDEX_op_extu_i32_i64: + /* We do not compute affected as it is a size changing op. */ + mask = (uint32_t) arg_info(op->args[1])->mask; break; - } - case INDEX_op_extu_i32_i64: - /* We do not compute affected as it is a size changing op. */ - mask = (uint32_t)arg_info(op->args[1])->mask; - break; - CASE_OP_32_64(andc): - /* Known-zeros does not imply known-ones. Therefore unless - op->args[2] is constant, we can't infer anything from it. */ - if (arg_is_const(op->args[2])) { - mask = ~arg_info(op->args[2])->mask; - goto and_const; - } - /* But we certainly know nothing outside args[1] may be set. */ - mask = arg_info(op->args[1])->mask; - break; + CASE_OP_32_64(andc) + : /* Known-zeros does not imply known-ones. Therefore unless + op->args[2] is constant, we can't infer anything from it. */ + if (arg_is_const(op->args[2])) { + mask = ~arg_info(op->args[2])->mask; + goto and_const; + } + /* But we certainly know nothing outside args[1] may be set. */ + mask = arg_info(op->args[1])->mask; + break; - case INDEX_op_sar_i32: - if (arg_is_const(op->args[2])) { - tmp = arg_info(op->args[2])->val & 31; - mask = (int32_t)arg_info(op->args[1])->mask >> tmp; - } - break; - case INDEX_op_sar_i64: - if (arg_is_const(op->args[2])) { - tmp = arg_info(op->args[2])->val & 63; - mask = (int64_t)arg_info(op->args[1])->mask >> tmp; - } - break; + case INDEX_op_sar_i32: + if (arg_is_const(op->args[2])) { + tmp = arg_info(op->args[2])->val & 31; + mask = (int32_t) arg_info(op->args[1])->mask >> tmp; + } + break; + case INDEX_op_sar_i64: + if (arg_is_const(op->args[2])) { + tmp = arg_info(op->args[2])->val & 63; + mask = (int64_t) arg_info(op->args[1])->mask >> tmp; + } + break; - case INDEX_op_shr_i32: - if (arg_is_const(op->args[2])) { - tmp = arg_info(op->args[2])->val & 31; - mask = (uint32_t)arg_info(op->args[1])->mask >> tmp; - } - break; - case INDEX_op_shr_i64: - if (arg_is_const(op->args[2])) { - tmp = arg_info(op->args[2])->val & 63; - mask = (uint64_t)arg_info(op->args[1])->mask >> tmp; - } - break; + case INDEX_op_shr_i32: + if (arg_is_const(op->args[2])) { + tmp = arg_info(op->args[2])->val & 31; + mask = (uint32_t) arg_info(op->args[1])->mask >> tmp; + } + break; + case INDEX_op_shr_i64: + if (arg_is_const(op->args[2])) { + tmp = arg_info(op->args[2])->val & 63; + mask = (uint64_t) arg_info(op->args[1])->mask >> tmp; + } + break; - case INDEX_op_extrl_i64_i32: - mask = (uint32_t)arg_info(op->args[1])->mask; - break; - case INDEX_op_extrh_i64_i32: - mask = (uint64_t)arg_info(op->args[1])->mask >> 32; - break; + case INDEX_op_extrl_i64_i32: + mask = (uint32_t) arg_info(op->args[1])->mask; + break; + case INDEX_op_extrh_i64_i32: + mask = (uint64_t) arg_info(op->args[1])->mask >> 32; + break; - CASE_OP_32_64(shl): - if (arg_is_const(op->args[2])) { - tmp = arg_info(op->args[2])->val & (TCG_TARGET_REG_BITS - 1); - mask = arg_info(op->args[1])->mask << tmp; - } - break; + CASE_OP_32_64(shl) : if (arg_is_const(op->args[2])) { + tmp = arg_info(op->args[2])->val & (TCG_TARGET_REG_BITS - 1); + mask = arg_info(op->args[1])->mask << tmp; + } + break; - CASE_OP_32_64(neg): - /* Set to 1 all bits to the left of the rightmost. */ - mask = -(arg_info(op->args[1])->mask - & -arg_info(op->args[1])->mask); - break; + CASE_OP_32_64(neg) + : /* Set to 1 all bits to the left of the rightmost. */ + mask = -(arg_info(op->args[1])->mask & -arg_info(op->args[1])->mask); + break; - CASE_OP_32_64(deposit): - mask = deposit64(arg_info(op->args[1])->mask, - op->args[3], op->args[4], - arg_info(op->args[2])->mask); - break; + CASE_OP_32_64(deposit) + : mask = + deposit64(arg_info(op->args[1])->mask, op->args[3], op->args[4], arg_info(op->args[2])->mask); + break; - CASE_OP_32_64(extract): - mask = extract64(arg_info(op->args[1])->mask, - op->args[2], op->args[3]); - if (op->args[2] == 0) { - affected = arg_info(op->args[1])->mask & ~mask; - } - break; - CASE_OP_32_64(sextract): - mask = sextract64(arg_info(op->args[1])->mask, - op->args[2], op->args[3]); - if (op->args[2] == 0 && (tcg_target_long)mask >= 0) { - affected = arg_info(op->args[1])->mask & ~mask; - } - break; + CASE_OP_32_64(extract) : mask = extract64(arg_info(op->args[1])->mask, op->args[2], op->args[3]); + if (op->args[2] == 0) { + affected = arg_info(op->args[1])->mask & ~mask; + } + break; + CASE_OP_32_64(sextract) : mask = sextract64(arg_info(op->args[1])->mask, op->args[2], op->args[3]); + if (op->args[2] == 0 && (tcg_target_long) mask >= 0) { + affected = arg_info(op->args[1])->mask & ~mask; + } + break; - CASE_OP_32_64(or): - CASE_OP_32_64(xor): - mask = arg_info(op->args[1])->mask | arg_info(op->args[2])->mask; - break; + CASE_OP_32_64(or) + : CASE_OP_32_64 (xor) : mask = arg_info(op->args[1])->mask | arg_info(op->args[2])->mask; + break; - case INDEX_op_clz_i32: - case INDEX_op_ctz_i32: - mask = arg_info(op->args[2])->mask | 31; - break; + case INDEX_op_clz_i32: + case INDEX_op_ctz_i32: + mask = arg_info(op->args[2])->mask | 31; + break; - case INDEX_op_clz_i64: - case INDEX_op_ctz_i64: - mask = arg_info(op->args[2])->mask | 63; - break; + case INDEX_op_clz_i64: + case INDEX_op_ctz_i64: + mask = arg_info(op->args[2])->mask | 63; + break; - case INDEX_op_ctpop_i32: - mask = 32 | 31; - break; - case INDEX_op_ctpop_i64: - mask = 64 | 63; - break; + case INDEX_op_ctpop_i32: + mask = 32 | 31; + break; + case INDEX_op_ctpop_i64: + mask = 64 | 63; + break; - CASE_OP_32_64(setcond): - case INDEX_op_setcond2_i32: - mask = 1; - break; + CASE_OP_32_64(setcond) : case INDEX_op_setcond2_i32 : mask = 1; + break; - CASE_OP_32_64(movcond): - mask = arg_info(op->args[3])->mask | arg_info(op->args[4])->mask; - break; + CASE_OP_32_64(movcond) : mask = arg_info(op->args[3])->mask | arg_info(op->args[4])->mask; + break; - CASE_OP_32_64(ld8u): - mask = 0xff; - break; - CASE_OP_32_64(ld16u): - mask = 0xffff; - break; - case INDEX_op_ld32u_i64: - mask = 0xffffffffu; - break; + CASE_OP_32_64(ld8u) : mask = 0xff; + break; + CASE_OP_32_64(ld16u) : mask = 0xffff; + break; + case INDEX_op_ld32u_i64: + mask = 0xffffffffu; + break; - CASE_OP_32_64(qemu_ld): - { - TCGMemOpIdx oi = op->args[nb_oargs + nb_iargs]; - TCGMemOp mop = get_memop(oi); - if (!(mop & MO_SIGN)) { - mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1; + CASE_OP_32_64(qemu_ld) : { + TCGMemOpIdx oi = op->args[nb_oargs + nb_iargs]; + TCGMemOp mop = get_memop(oi); + if (!(mop & MO_SIGN)) { + mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1; + } } - } - break; + break; - default: - break; + default: + break; } /* 32-bit ops generate 32-bit results. For the result is zero test @@ -1032,7 +938,7 @@ void tcg_optimize(TCGContext *s) need to record that the high bits contain garbage. */ partmask = mask; if (!(def->flags & TCG_OPF_64BIT)) { - mask |= ~(tcg_target_ulong)0xffffffffu; + mask |= ~(tcg_target_ulong) 0xffffffffu; partmask &= 0xffffffffu; affected &= 0xffffffffu; } @@ -1050,470 +956,415 @@ void tcg_optimize(TCGContext *s) /* Simplify expression for "op r, a, 0 => movi r, 0" cases */ switch (opc) { - CASE_OP_32_64_VEC(and): - CASE_OP_32_64_VEC(mul): - CASE_OP_32_64(muluh): - CASE_OP_32_64(mulsh): - if (arg_is_const(op->args[2]) - && arg_info(op->args[2])->val == 0) { + CASE_OP_32_64_VEC(and) + : CASE_OP_32_64_VEC(mul) + : CASE_OP_32_64(muluh) + : CASE_OP_32_64(mulsh) : if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val == 0) { tcg_opt_gen_movi(s, op, op->args[0], 0); continue; } break; - default: - break; + default: + break; } /* Simplify expression for "op r, a, a => mov r, a" cases */ switch (opc) { - CASE_OP_32_64_VEC(or): - CASE_OP_32_64_VEC(and): - if (args_are_copies(op->args[1], op->args[2])) { + CASE_OP_32_64_VEC(or) : CASE_OP_32_64_VEC(and) : if (args_are_copies(op->args[1], op->args[2])) { tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); continue; } break; - default: - break; + default: + break; } /* Simplify expression for "op r, a, a => movi r, 0" cases */ switch (opc) { - CASE_OP_32_64_VEC(andc): - CASE_OP_32_64_VEC(sub): - CASE_OP_32_64_VEC(xor): - if (args_are_copies(op->args[1], op->args[2])) { + CASE_OP_32_64_VEC(andc) + : CASE_OP_32_64_VEC(sub) : CASE_OP_32_64_VEC (xor) : if (args_are_copies(op->args[1], op->args[2])) { tcg_opt_gen_movi(s, op, op->args[0], 0); continue; } break; - default: - break; + default: + break; } /* Propagate constants through copy operations and do constant folding. Constants will be substituted to arguments by register allocator where needed and possible. Also detect copies. */ switch (opc) { - CASE_OP_32_64_VEC(mov): - tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); + CASE_OP_32_64_VEC(mov) : tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); break; - CASE_OP_32_64(movi): - case INDEX_op_dupi_vec: - tcg_opt_gen_movi(s, op, op->args[0], op->args[1]); + CASE_OP_32_64(movi) : case INDEX_op_dupi_vec : tcg_opt_gen_movi(s, op, op->args[0], op->args[1]); break; - case INDEX_op_dup_vec: - if (arg_is_const(op->args[1])) { - tmp = arg_info(op->args[1])->val; - tmp = dup_const(TCGOP_VECE(op), tmp); - tcg_opt_gen_movi(s, op, op->args[0], tmp); - break; - } - goto do_default; - - CASE_OP_32_64(not): - CASE_OP_32_64(neg): - CASE_OP_32_64(ext8s): - CASE_OP_32_64(ext8u): - CASE_OP_32_64(ext16s): - CASE_OP_32_64(ext16u): - CASE_OP_32_64(ctpop): - CASE_OP_32_64(bswap16): - CASE_OP_32_64(bswap32): - case INDEX_op_bswap64_i64: - case INDEX_op_ext32s_i64: - case INDEX_op_ext32u_i64: - case INDEX_op_ext_i32_i64: - case INDEX_op_extu_i32_i64: - case INDEX_op_extrl_i64_i32: - case INDEX_op_extrh_i64_i32: - if (arg_is_const(op->args[1])) { - tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0); - tcg_opt_gen_movi(s, op, op->args[0], tmp); - break; - } - goto do_default; - - CASE_OP_32_64(add): - CASE_OP_32_64(sub): - CASE_OP_32_64(mul): - CASE_OP_32_64(or): - CASE_OP_32_64(and): - CASE_OP_32_64(xor): - CASE_OP_32_64(shl): - CASE_OP_32_64(shr): - CASE_OP_32_64(sar): - CASE_OP_32_64(rotl): - CASE_OP_32_64(rotr): - CASE_OP_32_64(andc): - CASE_OP_32_64(orc): - CASE_OP_32_64(eqv): - CASE_OP_32_64(nand): - CASE_OP_32_64(nor): - CASE_OP_32_64(muluh): - CASE_OP_32_64(mulsh): - CASE_OP_32_64(div): - CASE_OP_32_64(divu): - CASE_OP_32_64(rem): - CASE_OP_32_64(remu): - if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { - tmp = do_constant_folding(opc, arg_info(op->args[1])->val, - arg_info(op->args[2])->val); - tcg_opt_gen_movi(s, op, op->args[0], tmp); - break; - } - goto do_default; - - CASE_OP_32_64(clz): - CASE_OP_32_64(ctz): - if (arg_is_const(op->args[1])) { - TCGArg v = arg_info(op->args[1])->val; - if (v != 0) { - tmp = do_constant_folding(opc, v, 0); + case INDEX_op_dup_vec: + if (arg_is_const(op->args[1])) { + tmp = arg_info(op->args[1])->val; + tmp = dup_const(TCGOP_VECE(op), tmp); tcg_opt_gen_movi(s, op, op->args[0], tmp); - } else { - tcg_opt_gen_mov(s, op, op->args[0], op->args[2]); + break; } - break; - } - goto do_default; - - CASE_OP_32_64(deposit): - if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { - tmp = deposit64(arg_info(op->args[1])->val, - op->args[3], op->args[4], - arg_info(op->args[2])->val); - tcg_opt_gen_movi(s, op, op->args[0], tmp); - break; - } - goto do_default; + goto do_default; - CASE_OP_32_64(extract): - if (arg_is_const(op->args[1])) { - tmp = extract64(arg_info(op->args[1])->val, - op->args[2], op->args[3]); - tcg_opt_gen_movi(s, op, op->args[0], tmp); - break; - } - goto do_default; + CASE_OP_32_64(not) + : CASE_OP_32_64(neg) + : CASE_OP_32_64(ext8s) + : CASE_OP_32_64(ext8u) + : CASE_OP_32_64(ext16s) + : CASE_OP_32_64(ext16u) + : CASE_OP_32_64(ctpop) + : CASE_OP_32_64(bswap16) + : CASE_OP_32_64(bswap32) + : case INDEX_op_bswap64_i64 : case INDEX_op_ext32s_i64 : case INDEX_op_ext32u_i64 + : case INDEX_op_ext_i32_i64 + : case INDEX_op_extu_i32_i64 + : case INDEX_op_extrl_i64_i32 + : case INDEX_op_extrh_i64_i32 + : if (arg_is_const(op->args[1])) { + tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0); + tcg_opt_gen_movi(s, op, op->args[0], tmp); + break; + } + goto do_default; - CASE_OP_32_64(sextract): - if (arg_is_const(op->args[1])) { - tmp = sextract64(arg_info(op->args[1])->val, - op->args[2], op->args[3]); - tcg_opt_gen_movi(s, op, op->args[0], tmp); - break; - } - goto do_default; + CASE_OP_32_64(add) + : CASE_OP_32_64(sub) + : CASE_OP_32_64(mul) + : CASE_OP_32_64(or) + : CASE_OP_32_64(and) + : CASE_OP_32_64 (xor) + : CASE_OP_32_64(shl) + : CASE_OP_32_64(shr) + : CASE_OP_32_64(sar) + : CASE_OP_32_64(rotl) + : CASE_OP_32_64(rotr) + : CASE_OP_32_64(andc) + : CASE_OP_32_64(orc) + : CASE_OP_32_64(eqv) + : CASE_OP_32_64(nand) + : CASE_OP_32_64(nor) + : CASE_OP_32_64(muluh) + : CASE_OP_32_64(mulsh) + : CASE_OP_32_64(div) + : CASE_OP_32_64(divu) + : CASE_OP_32_64(rem) + : CASE_OP_32_64(remu) : if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { + tmp = do_constant_folding(opc, arg_info(op->args[1])->val, arg_info(op->args[2])->val); + tcg_opt_gen_movi(s, op, op->args[0], tmp); + break; + } + goto do_default; - CASE_OP_32_64(setcond): - tmp = do_constant_folding_cond(opc, op->args[1], - op->args[2], op->args[3]); - if (tmp != 2) { - tcg_opt_gen_movi(s, op, op->args[0], tmp); - break; - } - goto do_default; + CASE_OP_32_64(clz) : CASE_OP_32_64(ctz) : if (arg_is_const(op->args[1])) { + TCGArg v = arg_info(op->args[1])->val; + if (v != 0) { + tmp = do_constant_folding(opc, v, 0); + tcg_opt_gen_movi(s, op, op->args[0], tmp); + } else { + tcg_opt_gen_mov(s, op, op->args[0], op->args[2]); + } + break; + } + goto do_default; - CASE_OP_32_64(brcond): - tmp = do_constant_folding_cond(opc, op->args[0], - op->args[1], op->args[2]); - if (tmp != 2) { - if (tmp) { - bitmap_zero(temps_used.l, nb_temps); - op->opc = INDEX_op_br; - op->args[0] = op->args[3]; - } else { - tcg_op_remove(s, op); + CASE_OP_32_64(deposit) : if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { + tmp = deposit64(arg_info(op->args[1])->val, op->args[3], op->args[4], arg_info(op->args[2])->val); + tcg_opt_gen_movi(s, op, op->args[0], tmp); + break; } - break; - } - goto do_default; + goto do_default; - CASE_OP_32_64(movcond): - tmp = do_constant_folding_cond(opc, op->args[1], - op->args[2], op->args[5]); - if (tmp != 2) { - tcg_opt_gen_mov(s, op, op->args[0], op->args[4-tmp]); - break; - } - if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) { - tcg_target_ulong tv = arg_info(op->args[3])->val; - tcg_target_ulong fv = arg_info(op->args[4])->val; - TCGCond cond = op->args[5]; - if (fv == 1 && tv == 0) { - cond = tcg_invert_cond(cond); - } else if (!(tv == 1 && fv == 0)) { - goto do_default; + CASE_OP_32_64(extract) : if (arg_is_const(op->args[1])) { + tmp = extract64(arg_info(op->args[1])->val, op->args[2], op->args[3]); + tcg_opt_gen_movi(s, op, op->args[0], tmp); + break; } - op->args[3] = cond; - op->opc = opc = (opc == INDEX_op_movcond_i32 - ? INDEX_op_setcond_i32 - : INDEX_op_setcond_i64); - nb_iargs = 2; - } - goto do_default; - - case INDEX_op_add2_i32: - case INDEX_op_sub2_i32: - if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) - && arg_is_const(op->args[4]) && arg_is_const(op->args[5])) { - uint32_t al = arg_info(op->args[2])->val; - uint32_t ah = arg_info(op->args[3])->val; - uint32_t bl = arg_info(op->args[4])->val; - uint32_t bh = arg_info(op->args[5])->val; - uint64_t a = ((uint64_t)ah << 32) | al; - uint64_t b = ((uint64_t)bh << 32) | bl; - TCGArg rl, rh; - TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32); - - if (opc == INDEX_op_add2_i32) { - a += b; - } else { - a -= b; + goto do_default; + + CASE_OP_32_64(sextract) : if (arg_is_const(op->args[1])) { + tmp = sextract64(arg_info(op->args[1])->val, op->args[2], op->args[3]); + tcg_opt_gen_movi(s, op, op->args[0], tmp); + break; } + goto do_default; - rl = op->args[0]; - rh = op->args[1]; - tcg_opt_gen_movi(s, op, rl, (int32_t)a); - tcg_opt_gen_movi(s, op2, rh, (int32_t)(a >> 32)); - break; - } - goto do_default; - - case INDEX_op_mulu2_i32: - if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) { - uint32_t a = arg_info(op->args[2])->val; - uint32_t b = arg_info(op->args[3])->val; - uint64_t r = (uint64_t)a * b; - TCGArg rl, rh; - TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32); - - rl = op->args[0]; - rh = op->args[1]; - tcg_opt_gen_movi(s, op, rl, (int32_t)r); - tcg_opt_gen_movi(s, op2, rh, (int32_t)(r >> 32)); - break; - } - goto do_default; - - case INDEX_op_brcond2_i32: - tmp = do_constant_folding_cond2(&op->args[0], &op->args[2], - op->args[4]); - if (tmp != 2) { - if (tmp) { - do_brcond_true: - bitmap_zero(temps_used.l, nb_temps); - op->opc = INDEX_op_br; - op->args[0] = op->args[5]; - } else { - do_brcond_false: - tcg_op_remove(s, op); + CASE_OP_32_64(setcond) : tmp = do_constant_folding_cond(opc, op->args[1], op->args[2], op->args[3]); + if (tmp != 2) { + tcg_opt_gen_movi(s, op, op->args[0], tmp); + break; } - } else if ((op->args[4] == TCG_COND_LT - || op->args[4] == TCG_COND_GE) - && arg_is_const(op->args[2]) - && arg_info(op->args[2])->val == 0 - && arg_is_const(op->args[3]) - && arg_info(op->args[3])->val == 0) { - /* Simplify LT/GE comparisons vs zero to a single compare - vs the high word of the input. */ - do_brcond_high: - bitmap_zero(temps_used.l, nb_temps); - op->opc = INDEX_op_brcond_i32; - op->args[0] = op->args[1]; - op->args[1] = op->args[3]; - op->args[2] = op->args[4]; - op->args[3] = op->args[5]; - } else if (op->args[4] == TCG_COND_EQ) { - /* Simplify EQ comparisons where one of the pairs - can be simplified. */ - tmp = do_constant_folding_cond(INDEX_op_brcond_i32, - op->args[0], op->args[2], - TCG_COND_EQ); - if (tmp == 0) { - goto do_brcond_false; - } else if (tmp == 1) { - goto do_brcond_high; + goto do_default; + + CASE_OP_32_64(brcond) : tmp = do_constant_folding_cond(opc, op->args[0], op->args[1], op->args[2]); + if (tmp != 2) { + if (tmp) { + bitmap_zero(temps_used.l, nb_temps); + op->opc = INDEX_op_br; + op->args[0] = op->args[3]; + } else { + tcg_op_remove(s, op); + } + break; } - tmp = do_constant_folding_cond(INDEX_op_brcond_i32, - op->args[1], op->args[3], - TCG_COND_EQ); - if (tmp == 0) { - goto do_brcond_false; - } else if (tmp != 1) { - goto do_default; + goto do_default; + + CASE_OP_32_64(movcond) : tmp = do_constant_folding_cond(opc, op->args[1], op->args[2], op->args[5]); + if (tmp != 2) { + tcg_opt_gen_mov(s, op, op->args[0], op->args[4 - tmp]); + break; } - do_brcond_low: - bitmap_zero(temps_used.l, nb_temps); - op->opc = INDEX_op_brcond_i32; - op->args[1] = op->args[2]; - op->args[2] = op->args[4]; - op->args[3] = op->args[5]; - } else if (op->args[4] == TCG_COND_NE) { - /* Simplify NE comparisons where one of the pairs - can be simplified. */ - tmp = do_constant_folding_cond(INDEX_op_brcond_i32, - op->args[0], op->args[2], - TCG_COND_NE); - if (tmp == 0) { - goto do_brcond_high; - } else if (tmp == 1) { - goto do_brcond_true; + if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) { + tcg_target_ulong tv = arg_info(op->args[3])->val; + tcg_target_ulong fv = arg_info(op->args[4])->val; + TCGCond cond = op->args[5]; + if (fv == 1 && tv == 0) { + cond = tcg_invert_cond(cond); + } else if (!(tv == 1 && fv == 0)) { + goto do_default; + } + op->args[3] = cond; + op->opc = opc = (opc == INDEX_op_movcond_i32 ? INDEX_op_setcond_i32 : INDEX_op_setcond_i64); + nb_iargs = 2; } - tmp = do_constant_folding_cond(INDEX_op_brcond_i32, - op->args[1], op->args[3], - TCG_COND_NE); - if (tmp == 0) { - goto do_brcond_low; - } else if (tmp == 1) { - goto do_brcond_true; + goto do_default; + + case INDEX_op_add2_i32: + case INDEX_op_sub2_i32: + if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) && arg_is_const(op->args[4]) && + arg_is_const(op->args[5])) { + uint32_t al = arg_info(op->args[2])->val; + uint32_t ah = arg_info(op->args[3])->val; + uint32_t bl = arg_info(op->args[4])->val; + uint32_t bh = arg_info(op->args[5])->val; + uint64_t a = ((uint64_t) ah << 32) | al; + uint64_t b = ((uint64_t) bh << 32) | bl; + TCGArg rl, rh; + TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32); + + if (opc == INDEX_op_add2_i32) { + a += b; + } else { + a -= b; + } + + rl = op->args[0]; + rh = op->args[1]; + tcg_opt_gen_movi(s, op, rl, (int32_t) a); + tcg_opt_gen_movi(s, op2, rh, (int32_t)(a >> 32)); + break; } goto do_default; - } else { + + case INDEX_op_mulu2_i32: + if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) { + uint32_t a = arg_info(op->args[2])->val; + uint32_t b = arg_info(op->args[3])->val; + uint64_t r = (uint64_t) a * b; + TCGArg rl, rh; + TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32); + + rl = op->args[0]; + rh = op->args[1]; + tcg_opt_gen_movi(s, op, rl, (int32_t) r); + tcg_opt_gen_movi(s, op2, rh, (int32_t)(r >> 32)); + break; + } goto do_default; - } - break; - case INDEX_op_setcond2_i32: - tmp = do_constant_folding_cond2(&op->args[1], &op->args[3], - op->args[5]); - if (tmp != 2) { - do_setcond_const: - tcg_opt_gen_movi(s, op, op->args[0], tmp); - } else if ((op->args[5] == TCG_COND_LT - || op->args[5] == TCG_COND_GE) - && arg_is_const(op->args[3]) - && arg_info(op->args[3])->val == 0 - && arg_is_const(op->args[4]) - && arg_info(op->args[4])->val == 0) { + case INDEX_op_brcond2_i32: + tmp = do_constant_folding_cond2(&op->args[0], &op->args[2], op->args[4]); + if (tmp != 2) { + if (tmp) { + do_brcond_true: + bitmap_zero(temps_used.l, nb_temps); + op->opc = INDEX_op_br; + op->args[0] = op->args[5]; + } else { + do_brcond_false: + tcg_op_remove(s, op); + } + } else if ((op->args[4] == TCG_COND_LT || op->args[4] == TCG_COND_GE) && arg_is_const(op->args[2]) && + arg_info(op->args[2])->val == 0 && arg_is_const(op->args[3]) && + arg_info(op->args[3])->val == 0) { /* Simplify LT/GE comparisons vs zero to a single compare vs the high word of the input. */ - do_setcond_high: - reset_temp(op->args[0]); - arg_info(op->args[0])->mask = 1; - op->opc = INDEX_op_setcond_i32; - op->args[1] = op->args[2]; - op->args[2] = op->args[4]; - op->args[3] = op->args[5]; - } else if (op->args[5] == TCG_COND_EQ) { - /* Simplify EQ comparisons where one of the pairs - can be simplified. */ - tmp = do_constant_folding_cond(INDEX_op_setcond_i32, - op->args[1], op->args[3], - TCG_COND_EQ); - if (tmp == 0) { - goto do_setcond_const; - } else if (tmp == 1) { - goto do_setcond_high; - } - tmp = do_constant_folding_cond(INDEX_op_setcond_i32, - op->args[2], op->args[4], - TCG_COND_EQ); - if (tmp == 0) { - goto do_setcond_high; - } else if (tmp != 1) { + do_brcond_high: + bitmap_zero(temps_used.l, nb_temps); + op->opc = INDEX_op_brcond_i32; + op->args[0] = op->args[1]; + op->args[1] = op->args[3]; + op->args[2] = op->args[4]; + op->args[3] = op->args[5]; + } else if (op->args[4] == TCG_COND_EQ) { + /* Simplify EQ comparisons where one of the pairs + can be simplified. */ + tmp = do_constant_folding_cond(INDEX_op_brcond_i32, op->args[0], op->args[2], TCG_COND_EQ); + if (tmp == 0) { + goto do_brcond_false; + } else if (tmp == 1) { + goto do_brcond_high; + } + tmp = do_constant_folding_cond(INDEX_op_brcond_i32, op->args[1], op->args[3], TCG_COND_EQ); + if (tmp == 0) { + goto do_brcond_false; + } else if (tmp != 1) { + goto do_default; + } + do_brcond_low: + bitmap_zero(temps_used.l, nb_temps); + op->opc = INDEX_op_brcond_i32; + op->args[1] = op->args[2]; + op->args[2] = op->args[4]; + op->args[3] = op->args[5]; + } else if (op->args[4] == TCG_COND_NE) { + /* Simplify NE comparisons where one of the pairs + can be simplified. */ + tmp = do_constant_folding_cond(INDEX_op_brcond_i32, op->args[0], op->args[2], TCG_COND_NE); + if (tmp == 0) { + goto do_brcond_high; + } else if (tmp == 1) { + goto do_brcond_true; + } + tmp = do_constant_folding_cond(INDEX_op_brcond_i32, op->args[1], op->args[3], TCG_COND_NE); + if (tmp == 0) { + goto do_brcond_low; + } else if (tmp == 1) { + goto do_brcond_true; + } + goto do_default; + } else { goto do_default; } - do_setcond_low: - reset_temp(op->args[0]); - arg_info(op->args[0])->mask = 1; - op->opc = INDEX_op_setcond_i32; - op->args[2] = op->args[3]; - op->args[3] = op->args[5]; - } else if (op->args[5] == TCG_COND_NE) { - /* Simplify NE comparisons where one of the pairs - can be simplified. */ - tmp = do_constant_folding_cond(INDEX_op_setcond_i32, - op->args[1], op->args[3], - TCG_COND_NE); - if (tmp == 0) { - goto do_setcond_high; - } else if (tmp == 1) { - goto do_setcond_const; - } - tmp = do_constant_folding_cond(INDEX_op_setcond_i32, - op->args[2], op->args[4], - TCG_COND_NE); - if (tmp == 0) { - goto do_setcond_low; - } else if (tmp == 1) { - goto do_setcond_const; + break; + + case INDEX_op_setcond2_i32: + tmp = do_constant_folding_cond2(&op->args[1], &op->args[3], op->args[5]); + if (tmp != 2) { + do_setcond_const: + tcg_opt_gen_movi(s, op, op->args[0], tmp); + } else if ((op->args[5] == TCG_COND_LT || op->args[5] == TCG_COND_GE) && arg_is_const(op->args[3]) && + arg_info(op->args[3])->val == 0 && arg_is_const(op->args[4]) && + arg_info(op->args[4])->val == 0) { + /* Simplify LT/GE comparisons vs zero to a single compare + vs the high word of the input. */ + do_setcond_high: + reset_temp(op->args[0]); + arg_info(op->args[0])->mask = 1; + op->opc = INDEX_op_setcond_i32; + op->args[1] = op->args[2]; + op->args[2] = op->args[4]; + op->args[3] = op->args[5]; + } else if (op->args[5] == TCG_COND_EQ) { + /* Simplify EQ comparisons where one of the pairs + can be simplified. */ + tmp = do_constant_folding_cond(INDEX_op_setcond_i32, op->args[1], op->args[3], TCG_COND_EQ); + if (tmp == 0) { + goto do_setcond_const; + } else if (tmp == 1) { + goto do_setcond_high; + } + tmp = do_constant_folding_cond(INDEX_op_setcond_i32, op->args[2], op->args[4], TCG_COND_EQ); + if (tmp == 0) { + goto do_setcond_high; + } else if (tmp != 1) { + goto do_default; + } + do_setcond_low: + reset_temp(op->args[0]); + arg_info(op->args[0])->mask = 1; + op->opc = INDEX_op_setcond_i32; + op->args[2] = op->args[3]; + op->args[3] = op->args[5]; + } else if (op->args[5] == TCG_COND_NE) { + /* Simplify NE comparisons where one of the pairs + can be simplified. */ + tmp = do_constant_folding_cond(INDEX_op_setcond_i32, op->args[1], op->args[3], TCG_COND_NE); + if (tmp == 0) { + goto do_setcond_high; + } else if (tmp == 1) { + goto do_setcond_const; + } + tmp = do_constant_folding_cond(INDEX_op_setcond_i32, op->args[2], op->args[4], TCG_COND_NE); + if (tmp == 0) { + goto do_setcond_low; + } else if (tmp == 1) { + goto do_setcond_const; + } + goto do_default; + } else { + goto do_default; } - goto do_default; - } else { - goto do_default; - } - break; + break; - case INDEX_op_call: - if (!(op->args[nb_oargs + nb_iargs + 1] - & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) { - for (i = 0; i < nb_globals; i++) { - if (test_bit(i, temps_used.l)) { - reset_ts(&s->temps[i]); + case INDEX_op_call: + if (!(op->args[nb_oargs + nb_iargs + 1] & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) { + for (i = 0; i < nb_globals; i++) { + if (test_bit(i, temps_used.l)) { + reset_ts(&s->temps[i]); + } } } - } - goto do_reset_output; + goto do_reset_output; - default: - do_default: - /* Default case: we know nothing about operation (or were unable - to compute the operation result) so no propagation is done. - We trash everything if the operation is the end of a basic - block, otherwise we only trash the output args. "mask" is - the non-zero bits mask for the first output arg. */ - if (def->flags & TCG_OPF_BB_END) { - bitmap_zero(temps_used.l, nb_temps); - } else { - do_reset_output: - for (i = 0; i < nb_oargs; i++) { - reset_temp(op->args[i]); - /* Save the corresponding known-zero bits mask for the - first output argument (only one supported so far). */ - if (i == 0) { - arg_info(op->args[i])->mask = mask; + default: + do_default: + /* Default case: we know nothing about operation (or were unable + to compute the operation result) so no propagation is done. + We trash everything if the operation is the end of a basic + block, otherwise we only trash the output args. "mask" is + the non-zero bits mask for the first output arg. */ + if (def->flags & TCG_OPF_BB_END) { + bitmap_zero(temps_used.l, nb_temps); + } else { + do_reset_output: + for (i = 0; i < nb_oargs; i++) { + reset_temp(op->args[i]); + /* Save the corresponding known-zero bits mask for the + first output argument (only one supported so far). */ + if (i == 0) { + arg_info(op->args[i])->mask = mask; + } } } - } - break; + break; } /* Eliminate duplicate and redundant fence instructions. */ if (prev_mb) { switch (opc) { - case INDEX_op_mb: - /* Merge two barriers of the same type into one, - * or a weaker barrier into a stronger one, - * or two weaker barriers into a stronger one. - * mb X; mb Y => mb X|Y - * mb; strl => mb; st - * ldaq; mb => ld; mb - * ldaq; strl => ld; mb; st - * Other combinations are also merged into a strong - * barrier. This is stricter than specified but for - * the purposes of TCG is better than not optimizing. - */ - prev_mb->args[0] |= op->args[0]; - tcg_op_remove(s, op); - break; - - default: - /* Opcodes that end the block stop the optimization. */ - if ((def->flags & TCG_OPF_BB_END) == 0) { + case INDEX_op_mb: + /* Merge two barriers of the same type into one, + * or a weaker barrier into a stronger one, + * or two weaker barriers into a stronger one. + * mb X; mb Y => mb X|Y + * mb; strl => mb; st + * ldaq; mb => ld; mb + * ldaq; strl => ld; mb; st + * Other combinations are also merged into a strong + * barrier. This is stricter than specified but for + * the purposes of TCG is better than not optimizing. + */ + prev_mb->args[0] |= op->args[0]; + tcg_op_remove(s, op); break; - } + + default: + /* Opcodes that end the block stop the optimization. */ + if ((def->flags & TCG_OPF_BB_END) == 0) { + break; + } /* fallthru */ - case INDEX_op_qemu_ld_i32: - case INDEX_op_qemu_ld_i64: - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_st_i64: - case INDEX_op_call: - /* Opcodes that touch guest memory stop the optimization. */ - prev_mb = NULL; - break; + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st_i64: + case INDEX_op_call: + /* Opcodes that touch guest memory stop the optimization. */ + prev_mb = NULL; + break; } } else if (opc == INDEX_op_mb) { prev_mb = op; diff --git a/src/tcg-common.c b/src/tcg-common.c index 0d97e52..43405fa 100644 --- a/src/tcg-common.c +++ b/src/tcg-common.c @@ -22,16 +22,15 @@ * THE SOFTWARE. */ -#include #include +#include #if defined(CONFIG_TCG_INTERPRETER) uintptr_t tci_tb_ptr; #endif TCGOpDef tcg_op_defs[] = { -#define DEF(s, oargs, iargs, cargs, flags) \ - { #s, oargs, iargs, cargs, iargs + oargs + cargs, flags }, +#define DEF(s, oargs, iargs, cargs, flags) {#s, oargs, iargs, cargs, iargs + oargs + cargs, flags}, #include #undef DEF }; diff --git a/src/tcg-ldst.inc.c b/src/tcg-ldst.inc.c index 47f41b9..7863656 100644 --- a/src/tcg-ldst.inc.c +++ b/src/tcg-ldst.inc.c @@ -21,19 +21,18 @@ */ typedef struct TCGLabelQemuLdst { - bool is_ld; /* qemu_ld: true, qemu_st: false */ + bool is_ld; /* qemu_ld: true, qemu_st: false */ TCGMemOpIdx oi; - TCGType type; /* result type of a load */ - TCGReg addrlo_reg; /* reg index for low word of guest virtual addr */ - TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */ - TCGReg datalo_reg; /* reg index for low word to be loaded or stored */ - TCGReg datahi_reg; /* reg index for high word to be loaded or stored */ - tcg_insn_unit *raddr; /* gen code addr of the next IR of qemu_ld/st IR */ + TCGType type; /* result type of a load */ + TCGReg addrlo_reg; /* reg index for low word of guest virtual addr */ + TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */ + TCGReg datalo_reg; /* reg index for low word to be loaded or stored */ + TCGReg datahi_reg; /* reg index for high word to be loaded or stored */ + tcg_insn_unit *raddr; /* gen code addr of the next IR of qemu_ld/st IR */ tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */ QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next; } TCGLabelQemuLdst; - /* * Generate TB finalization at the end of block */ @@ -41,8 +40,7 @@ typedef struct TCGLabelQemuLdst { static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l); static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l); -static bool tcg_out_ldst_finalize(TCGContext *s) -{ +static bool tcg_out_ldst_finalize(TCGContext *s) { TCGLabelQemuLdst *lb; /* qemu_ld/st slow paths */ @@ -57,7 +55,7 @@ static bool tcg_out_ldst_finalize(TCGContext *s) one operation beginning below the high water mark cannot overrun the buffer completely. Thus we can test for overflow after generating code without having to check during generation. */ - if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { + if (unlikely((void *) s->code_ptr > s->code_gen_highwater)) { return false; } } @@ -68,8 +66,7 @@ static bool tcg_out_ldst_finalize(TCGContext *s) * Allocate a new TCGLabelQemuLdst entry. */ -static inline TCGLabelQemuLdst *new_ldst_label(TCGContext *s) -{ +static inline TCGLabelQemuLdst *new_ldst_label(TCGContext *s) { TCGLabelQemuLdst *l = tcg_malloc(sizeof(*l)); QSIMPLEQ_INSERT_TAIL(&s->ldst_labels, l, next); diff --git a/src/tcg-op.c b/src/tcg-op.c index cc76680..59a4b51 100644 --- a/src/tcg-op.c +++ b/src/tcg-op.c @@ -25,9 +25,9 @@ typedef union MMXReg MMXReg; typedef union XMMReg XMMReg; -#include -#include #include +#include +#include /* Reduce the number of ifdefs below. This assumes that all uses of TCGV_HIGH and TCGV_LOW are properly protected by a conditional that @@ -35,33 +35,29 @@ typedef union XMMReg XMMReg; #if TCG_TARGET_REG_BITS == 64 extern TCGv_i32 TCGV_LOW_link_error(TCGv_i64); extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64); -#define TCGV_LOW TCGV_LOW_link_error +#define TCGV_LOW TCGV_LOW_link_error #define TCGV_HIGH TCGV_HIGH_link_error #endif -void tcg_gen_op1(TCGOpcode opc, TCGArg a1) -{ +void tcg_gen_op1(TCGOpcode opc, TCGArg a1) { TCGOp *op = tcg_emit_op(opc); op->args[0] = a1; } -void tcg_gen_op2(TCGOpcode opc, TCGArg a1, TCGArg a2) -{ +void tcg_gen_op2(TCGOpcode opc, TCGArg a1, TCGArg a2) { TCGOp *op = tcg_emit_op(opc); op->args[0] = a1; op->args[1] = a2; } -void tcg_gen_op3(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3) -{ +void tcg_gen_op3(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3) { TCGOp *op = tcg_emit_op(opc); op->args[0] = a1; op->args[1] = a2; op->args[2] = a3; } -void tcg_gen_op4(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, TCGArg a4) -{ +void tcg_gen_op4(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, TCGArg a4) { TCGOp *op = tcg_emit_op(opc); op->args[0] = a1; op->args[1] = a2; @@ -69,9 +65,7 @@ void tcg_gen_op4(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, TCGArg a4) op->args[3] = a4; } -void tcg_gen_op5(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, - TCGArg a4, TCGArg a5) -{ +void tcg_gen_op5(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, TCGArg a4, TCGArg a5) { TCGOp *op = tcg_emit_op(opc); op->args[0] = a1; op->args[1] = a2; @@ -80,9 +74,7 @@ void tcg_gen_op5(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, op->args[4] = a5; } -void tcg_gen_op6(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, - TCGArg a4, TCGArg a5, TCGArg a6) -{ +void tcg_gen_op6(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, TCGArg a4, TCGArg a5, TCGArg a6) { TCGOp *op = tcg_emit_op(opc); op->args[0] = a1; op->args[1] = a2; @@ -92,8 +84,7 @@ void tcg_gen_op6(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, op->args[5] = a6; } -void tcg_gen_mb(TCGBar mb_type) -{ +void tcg_gen_mb(TCGBar mb_type) { if (tcg_ctx->tb_cflags & CF_PARALLEL) { tcg_gen_op1(INDEX_op_mb, mb_type); } @@ -101,8 +92,7 @@ void tcg_gen_mb(TCGBar mb_type) /* 32 bit ops */ -void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ +void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { /* some cases can be optimized here */ if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); @@ -113,8 +103,7 @@ void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) } } -void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) -{ +void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) { if (arg1 == 0 && TCG_TARGET_HAS_neg_i32) { /* Don't recurse with tcg_gen_neg_i32. */ tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg2); @@ -125,8 +114,7 @@ void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) } } -void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ +void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { /* some cases can be optimized here */ if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); @@ -137,38 +125,36 @@ void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) } } -void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ +void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { TCGv_i32 t0; /* Some cases can be optimized here. */ switch (arg2) { - case 0: - tcg_gen_movi_i32(ret, 0); - return; - case -1: - tcg_gen_mov_i32(ret, arg1); - return; - case 0xff: - /* Don't recurse with tcg_gen_ext8u_i32. */ - if (TCG_TARGET_HAS_ext8u_i32) { - tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg1); + case 0: + tcg_gen_movi_i32(ret, 0); return; - } - break; - case 0xffff: - if (TCG_TARGET_HAS_ext16u_i32) { - tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg1); + case -1: + tcg_gen_mov_i32(ret, arg1); return; - } - break; + case 0xff: + /* Don't recurse with tcg_gen_ext8u_i32. */ + if (TCG_TARGET_HAS_ext8u_i32) { + tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg1); + return; + } + break; + case 0xffff: + if (TCG_TARGET_HAS_ext16u_i32) { + tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg1); + return; + } + break; } t0 = tcg_const_i32(arg2); tcg_gen_and_i32(ret, arg1, t0); tcg_temp_free_i32(t0); } -void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ +void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { /* Some cases can be optimized here. */ if (arg2 == -1) { tcg_gen_movi_i32(ret, -1); @@ -181,8 +167,7 @@ void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) } } -void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ +void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { /* Some cases can be optimized here. */ if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); @@ -196,8 +181,7 @@ void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) } } -void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ +void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { tcg_debug_assert(arg2 >= 0 && arg2 < 32); if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); @@ -208,8 +192,7 @@ void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) } } -void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ +void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { tcg_debug_assert(arg2 >= 0 && arg2 < 32); if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); @@ -220,8 +203,7 @@ void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) } } -void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ +void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { tcg_debug_assert(arg2 >= 0 && arg2 < 32); if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); @@ -232,8 +214,7 @@ void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) } } -void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *l) -{ +void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *l) { if (cond == TCG_COND_ALWAYS) { tcg_gen_br(l); } else if (cond != TCG_COND_NEVER) { @@ -242,8 +223,7 @@ void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *l) } } -void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *l) -{ +void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *l) { if (cond == TCG_COND_ALWAYS) { tcg_gen_br(l); } else if (cond != TCG_COND_NEVER) { @@ -253,9 +233,7 @@ void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *l) } } -void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, - TCGv_i32 arg1, TCGv_i32 arg2) -{ +void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (cond == TCG_COND_ALWAYS) { tcg_gen_movi_i32(ret, 1); } else if (cond == TCG_COND_NEVER) { @@ -265,16 +243,13 @@ void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, } } -void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, - TCGv_i32 arg1, int32_t arg2) -{ +void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { TCGv_i32 t0 = tcg_const_i32(arg2); tcg_gen_setcond_i32(cond, ret, arg1, t0); tcg_temp_free_i32(t0); } -void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ +void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { if (arg2 == 0) { tcg_gen_movi_i32(ret, 0); } else if (is_power_of_2(arg2)) { @@ -286,8 +261,7 @@ void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) } } -void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (TCG_TARGET_HAS_div_i32) { tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2); } else if (TCG_TARGET_HAS_div2_i32) { @@ -301,8 +275,7 @@ void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) } } -void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (TCG_TARGET_HAS_rem_i32) { tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2); } else if (TCG_TARGET_HAS_div_i32) { @@ -321,8 +294,7 @@ void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) } } -void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (TCG_TARGET_HAS_div_i32) { tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2); } else if (TCG_TARGET_HAS_div2_i32) { @@ -335,8 +307,7 @@ void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) } } -void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (TCG_TARGET_HAS_rem_i32) { tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2); } else if (TCG_TARGET_HAS_div_i32) { @@ -355,8 +326,7 @@ void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) } } -void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (TCG_TARGET_HAS_andc_i32) { tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2); } else { @@ -367,8 +337,7 @@ void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) } } -void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (TCG_TARGET_HAS_eqv_i32) { tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2); } else { @@ -377,8 +346,7 @@ void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) } } -void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (TCG_TARGET_HAS_nand_i32) { tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2); } else { @@ -387,8 +355,7 @@ void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) } } -void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (TCG_TARGET_HAS_nor_i32) { tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2); } else { @@ -397,8 +364,7 @@ void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) } } -void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (TCG_TARGET_HAS_orc_i32) { tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2); } else { @@ -409,8 +375,7 @@ void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) } } -void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (TCG_TARGET_HAS_clz_i32) { tcg_gen_op3_i32(INDEX_op_clz_i32, ret, arg1, arg2); } else if (TCG_TARGET_HAS_clz_i64) { @@ -429,15 +394,13 @@ void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) } } -void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) -{ +void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) { TCGv_i32 t = tcg_const_i32(arg2); tcg_gen_clz_i32(ret, arg1, t); tcg_temp_free_i32(t); } -void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (TCG_TARGET_HAS_ctz_i32) { tcg_gen_op3_i32(INDEX_op_ctz_i32, ret, arg1, arg2); } else if (TCG_TARGET_HAS_ctz_i64) { @@ -449,10 +412,8 @@ void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) tcg_gen_extrl_i64_i32(ret, t1); tcg_temp_free_i64(t1); tcg_temp_free_i64(t2); - } else if (TCG_TARGET_HAS_ctpop_i32 - || TCG_TARGET_HAS_ctpop_i64 - || TCG_TARGET_HAS_clz_i32 - || TCG_TARGET_HAS_clz_i64) { + } else if (TCG_TARGET_HAS_ctpop_i32 || TCG_TARGET_HAS_ctpop_i64 || TCG_TARGET_HAS_clz_i32 || + TCG_TARGET_HAS_clz_i64) { TCGv_i32 z, t = tcg_temp_new_i32(); if (TCG_TARGET_HAS_ctpop_i32 || TCG_TARGET_HAS_ctpop_i64) { @@ -475,8 +436,7 @@ void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) } } -void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) -{ +void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) { if (!TCG_TARGET_HAS_ctz_i32 && TCG_TARGET_HAS_ctpop_i32 && arg2 == 32) { /* This equivalence has the advantage of not requiring a fixup. */ TCGv_i32 t = tcg_temp_new_i32(); @@ -491,8 +451,7 @@ void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) } } -void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg) -{ +void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg) { if (TCG_TARGET_HAS_clz_i32) { TCGv_i32 t = tcg_temp_new_i32(); tcg_gen_sari_i32(t, arg, 31); @@ -505,8 +464,7 @@ void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg) } } -void tcg_gen_ctpop_i32(TCGv_i32 ret, TCGv_i32 arg1) -{ +void tcg_gen_ctpop_i32(TCGv_i32 ret, TCGv_i32 arg1) { if (TCG_TARGET_HAS_ctpop_i32) { tcg_gen_op2_i32(INDEX_op_ctpop_i32, ret, arg1); } else if (TCG_TARGET_HAS_ctpop_i64) { @@ -521,8 +479,7 @@ void tcg_gen_ctpop_i32(TCGv_i32 ret, TCGv_i32 arg1) } } -void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (TCG_TARGET_HAS_rot_i32) { tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2); } else { @@ -539,8 +496,7 @@ void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) } } -void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2) -{ +void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2) { tcg_debug_assert(arg2 < 32); /* some cases can be optimized here */ if (arg2 == 0) { @@ -561,8 +517,7 @@ void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2) } } -void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ +void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (TCG_TARGET_HAS_rot_i32) { tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2); } else { @@ -579,8 +534,7 @@ void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) } } -void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2) -{ +void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2) { tcg_debug_assert(arg2 < 32); /* some cases can be optimized here */ if (arg2 == 0) { @@ -590,9 +544,7 @@ void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2) } } -void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, - unsigned int ofs, unsigned int len) -{ +void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, unsigned int ofs, unsigned int len) { uint32_t mask; TCGv_i32 t1; @@ -625,9 +577,7 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, tcg_temp_free_i32(t1); } -void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, - unsigned int ofs, unsigned int len) -{ +void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len) { tcg_debug_assert(ofs < 32); tcg_debug_assert(len > 0); tcg_debug_assert(len <= 32); @@ -637,8 +587,7 @@ void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, tcg_gen_shli_i32(ret, arg, ofs); } else if (ofs == 0) { tcg_gen_andi_i32(ret, arg, (1u << len) - 1); - } else if (TCG_TARGET_HAS_deposit_i32 - && TCG_TARGET_deposit_i32_valid(ofs, len)) { + } else if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) { TCGv_i32 zero = tcg_const_i32(0); tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, zero, arg, ofs, len); tcg_temp_free_i32(zero); @@ -646,46 +595,44 @@ void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, /* To help two-operand hosts we prefer to zero-extend first, which allows ARG to stay live. */ switch (len) { - case 16: - if (TCG_TARGET_HAS_ext16u_i32) { - tcg_gen_ext16u_i32(ret, arg); - tcg_gen_shli_i32(ret, ret, ofs); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i32) { - tcg_gen_ext8u_i32(ret, arg); - tcg_gen_shli_i32(ret, ret, ofs); - return; - } - break; + case 16: + if (TCG_TARGET_HAS_ext16u_i32) { + tcg_gen_ext16u_i32(ret, arg); + tcg_gen_shli_i32(ret, ret, ofs); + return; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8u_i32) { + tcg_gen_ext8u_i32(ret, arg); + tcg_gen_shli_i32(ret, ret, ofs); + return; + } + break; } /* Otherwise prefer zero-extension over AND for code size. */ switch (ofs + len) { - case 16: - if (TCG_TARGET_HAS_ext16u_i32) { - tcg_gen_shli_i32(ret, arg, ofs); - tcg_gen_ext16u_i32(ret, ret); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i32) { - tcg_gen_shli_i32(ret, arg, ofs); - tcg_gen_ext8u_i32(ret, ret); - return; - } - break; + case 16: + if (TCG_TARGET_HAS_ext16u_i32) { + tcg_gen_shli_i32(ret, arg, ofs); + tcg_gen_ext16u_i32(ret, ret); + return; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8u_i32) { + tcg_gen_shli_i32(ret, arg, ofs); + tcg_gen_ext8u_i32(ret, ret); + return; + } + break; } tcg_gen_andi_i32(ret, arg, (1u << len) - 1); tcg_gen_shli_i32(ret, ret, ofs); } } -void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, - unsigned int ofs, unsigned int len) -{ +void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len) { tcg_debug_assert(ofs < 32); tcg_debug_assert(len > 0); tcg_debug_assert(len <= 32); @@ -701,48 +648,46 @@ void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, return; } - if (TCG_TARGET_HAS_extract_i32 - && TCG_TARGET_extract_i32_valid(ofs, len)) { + if (TCG_TARGET_HAS_extract_i32 && TCG_TARGET_extract_i32_valid(ofs, len)) { tcg_gen_op4ii_i32(INDEX_op_extract_i32, ret, arg, ofs, len); return; } /* Assume that zero-extension, if available, is cheaper than a shift. */ switch (ofs + len) { - case 16: - if (TCG_TARGET_HAS_ext16u_i32) { - tcg_gen_ext16u_i32(ret, arg); - tcg_gen_shri_i32(ret, ret, ofs); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i32) { - tcg_gen_ext8u_i32(ret, arg); - tcg_gen_shri_i32(ret, ret, ofs); - return; - } - break; + case 16: + if (TCG_TARGET_HAS_ext16u_i32) { + tcg_gen_ext16u_i32(ret, arg); + tcg_gen_shri_i32(ret, ret, ofs); + return; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8u_i32) { + tcg_gen_ext8u_i32(ret, arg); + tcg_gen_shri_i32(ret, ret, ofs); + return; + } + break; } /* ??? Ideally we'd know what values are available for immediate AND. Assume that 8 bits are available, plus the special case of 16, so that we get ext8u, ext16u. */ switch (len) { - case 1 ... 8: case 16: - tcg_gen_shri_i32(ret, arg, ofs); - tcg_gen_andi_i32(ret, ret, (1u << len) - 1); - break; - default: - tcg_gen_shli_i32(ret, arg, 32 - len - ofs); - tcg_gen_shri_i32(ret, ret, 32 - len); - break; + case 1 ... 8: + case 16: + tcg_gen_shri_i32(ret, arg, ofs); + tcg_gen_andi_i32(ret, ret, (1u << len) - 1); + break; + default: + tcg_gen_shli_i32(ret, arg, 32 - len - ofs); + tcg_gen_shri_i32(ret, ret, 32 - len); + break; } } -void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, - unsigned int ofs, unsigned int len) -{ +void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len) { tcg_debug_assert(ofs < 32); tcg_debug_assert(len > 0); tcg_debug_assert(len <= 32); @@ -755,62 +700,59 @@ void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, } if (ofs == 0) { switch (len) { - case 16: - tcg_gen_ext16s_i32(ret, arg); - return; - case 8: - tcg_gen_ext8s_i32(ret, arg); - return; + case 16: + tcg_gen_ext16s_i32(ret, arg); + return; + case 8: + tcg_gen_ext8s_i32(ret, arg); + return; } } - if (TCG_TARGET_HAS_sextract_i32 - && TCG_TARGET_extract_i32_valid(ofs, len)) { + if (TCG_TARGET_HAS_sextract_i32 && TCG_TARGET_extract_i32_valid(ofs, len)) { tcg_gen_op4ii_i32(INDEX_op_sextract_i32, ret, arg, ofs, len); return; } /* Assume that sign-extension, if available, is cheaper than a shift. */ switch (ofs + len) { - case 16: - if (TCG_TARGET_HAS_ext16s_i32) { - tcg_gen_ext16s_i32(ret, arg); - tcg_gen_sari_i32(ret, ret, ofs); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8s_i32) { - tcg_gen_ext8s_i32(ret, arg); - tcg_gen_sari_i32(ret, ret, ofs); - return; - } - break; + case 16: + if (TCG_TARGET_HAS_ext16s_i32) { + tcg_gen_ext16s_i32(ret, arg); + tcg_gen_sari_i32(ret, ret, ofs); + return; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8s_i32) { + tcg_gen_ext8s_i32(ret, arg); + tcg_gen_sari_i32(ret, ret, ofs); + return; + } + break; } switch (len) { - case 16: - if (TCG_TARGET_HAS_ext16s_i32) { - tcg_gen_shri_i32(ret, arg, ofs); - tcg_gen_ext16s_i32(ret, ret); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8s_i32) { - tcg_gen_shri_i32(ret, arg, ofs); - tcg_gen_ext8s_i32(ret, ret); - return; - } - break; + case 16: + if (TCG_TARGET_HAS_ext16s_i32) { + tcg_gen_shri_i32(ret, arg, ofs); + tcg_gen_ext16s_i32(ret, ret); + return; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8s_i32) { + tcg_gen_shri_i32(ret, arg, ofs); + tcg_gen_ext8s_i32(ret, ret); + return; + } + break; } tcg_gen_shli_i32(ret, arg, 32 - len - ofs); tcg_gen_sari_i32(ret, ret, 32 - len); } -void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, - TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2) -{ +void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2) { if (cond == TCG_COND_ALWAYS) { tcg_gen_mov_i32(ret, v1); } else if (cond == TCG_COND_NEVER) { @@ -830,9 +772,7 @@ void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, } } -void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, - TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh) -{ +void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh) { if (TCG_TARGET_HAS_add2_i32) { tcg_gen_op6_i32(INDEX_op_add2_i32, rl, rh, al, ah, bl, bh); } else { @@ -847,9 +787,7 @@ void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, } } -void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, - TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh) -{ +void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh) { if (TCG_TARGET_HAS_sub2_i32) { tcg_gen_op6_i32(INDEX_op_sub2_i32, rl, rh, al, ah, bl, bh); } else { @@ -864,8 +802,7 @@ void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, } } -void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2) -{ +void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2) { if (TCG_TARGET_HAS_mulu2_i32) { tcg_gen_op4_i32(INDEX_op_mulu2_i32, rl, rh, arg1, arg2); } else if (TCG_TARGET_HAS_muluh_i32) { @@ -886,8 +823,7 @@ void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2) } } -void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2) -{ +void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2) { if (TCG_TARGET_HAS_muls2_i32) { tcg_gen_op4_i32(INDEX_op_muls2_i32, rl, rh, arg1, arg2); } else if (TCG_TARGET_HAS_mulsh_i32) { @@ -926,8 +862,7 @@ void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2) } } -void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2) -{ +void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2) { if (TCG_TARGET_REG_BITS == 32) { TCGv_i32 t0 = tcg_temp_new_i32(); TCGv_i32 t1 = tcg_temp_new_i32(); @@ -953,8 +888,7 @@ void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2) } } -void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg) -{ +void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg) { if (TCG_TARGET_HAS_ext8s_i32) { tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg); } else { @@ -963,8 +897,7 @@ void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg) } } -void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) -{ +void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) { if (TCG_TARGET_HAS_ext16s_i32) { tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg); } else { @@ -973,8 +906,7 @@ void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) } } -void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg) -{ +void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg) { if (TCG_TARGET_HAS_ext8u_i32) { tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg); } else { @@ -982,8 +914,7 @@ void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg) } } -void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) -{ +void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) { if (TCG_TARGET_HAS_ext16u_i32) { tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg); } else { @@ -992,8 +923,7 @@ void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) } /* Note: we assume the two high bytes are set to zero */ -void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg) -{ +void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg) { if (TCG_TARGET_HAS_bswap16_i32) { tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg); } else { @@ -1007,8 +937,7 @@ void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg) } } -void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) -{ +void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) { if (TCG_TARGET_HAS_bswap32_i32) { tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg); } else { @@ -1016,16 +945,16 @@ void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) TCGv_i32 t1 = tcg_temp_new_i32(); TCGv_i32 t2 = tcg_const_i32(0x00ff00ff); - /* arg = abcd */ - tcg_gen_shri_i32(t0, arg, 8); /* t0 = .abc */ - tcg_gen_and_i32(t1, arg, t2); /* t1 = .b.d */ - tcg_gen_and_i32(t0, t0, t2); /* t0 = .a.c */ - tcg_gen_shli_i32(t1, t1, 8); /* t1 = b.d. */ - tcg_gen_or_i32(ret, t0, t1); /* ret = badc */ + /* arg = abcd */ + tcg_gen_shri_i32(t0, arg, 8); /* t0 = .abc */ + tcg_gen_and_i32(t1, arg, t2); /* t1 = .b.d */ + tcg_gen_and_i32(t0, t0, t2); /* t0 = .a.c */ + tcg_gen_shli_i32(t1, t1, 8); /* t1 = b.d. */ + tcg_gen_or_i32(ret, t0, t1); /* ret = badc */ - tcg_gen_shri_i32(t0, ret, 16); /* t0 = ..ba */ - tcg_gen_shli_i32(t1, ret, 16); /* t1 = dc.. */ - tcg_gen_or_i32(ret, t0, t1); /* ret = dcba */ + tcg_gen_shri_i32(t0, ret, 16); /* t0 = ..ba */ + tcg_gen_shli_i32(t1, ret, 16); /* t1 = dc.. */ + tcg_gen_or_i32(ret, t0, t1); /* ret = dcba */ tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); @@ -1033,23 +962,19 @@ void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) } } -void tcg_gen_smin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) -{ +void tcg_gen_smin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) { tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, a, b); } -void tcg_gen_umin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) -{ +void tcg_gen_umin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) { tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, a, b); } -void tcg_gen_smax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) -{ +void tcg_gen_smax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) { tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, b, a); } -void tcg_gen_umax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) -{ +void tcg_gen_umax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) { tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, b, a); } @@ -1058,64 +983,54 @@ void tcg_gen_umax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) #if TCG_TARGET_REG_BITS == 32 /* These are all inline for TCG_TARGET_REG_BITS == 64. */ -void tcg_gen_discard_i64(TCGv_i64 arg) -{ +void tcg_gen_discard_i64(TCGv_i64 arg) { tcg_gen_discard_i32(TCGV_LOW(arg)); tcg_gen_discard_i32(TCGV_HIGH(arg)); } -void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) -{ +void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) { tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); } -void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) -{ +void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) { tcg_gen_movi_i32(TCGV_LOW(ret), arg); tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32); } -void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) -{ +void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); } -void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) -{ +void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset); tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); } -void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) -{ +void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); } -void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) -{ +void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset); tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); } -void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) -{ +void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); } -void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) -{ +void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); } -void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) -{ - /* Since arg2 and ret have different types, - they cannot be the same temporary */ +void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { +/* Since arg2 and ret have different types, + they cannot be the same temporary */ #ifdef HOST_WORDS_BIGENDIAN tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4); @@ -1125,8 +1040,7 @@ void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) #endif } -void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) -{ +void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) { #ifdef HOST_WORDS_BIGENDIAN tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4); @@ -1136,49 +1050,41 @@ void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) #endif } -void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); } -void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); } -void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); } -void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { gen_helper_shl_i64(ret, arg1, arg2); } -void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { gen_helper_shr_i64(ret, arg1, arg2); } -void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { gen_helper_sar_i64(ret, arg1, arg2); } -void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { TCGv_i64 t0; TCGv_i32 t1; t0 = tcg_temp_new_i64(); t1 = tcg_temp_new_i32(); - tcg_gen_mulu2_i32(TCGV_LOW(t0), TCGV_HIGH(t0), - TCGV_LOW(arg1), TCGV_LOW(arg2)); + tcg_gen_mulu2_i32(TCGV_LOW(t0), TCGV_HIGH(t0), TCGV_LOW(arg1), TCGV_LOW(arg2)); tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2)); tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); @@ -1191,8 +1097,7 @@ void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) } #endif /* TCG_TARGET_REG_SIZE == 32 */ -void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ +void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { /* some cases can be optimized here */ if (arg2 == 0) { tcg_gen_mov_i64(ret, arg1); @@ -1203,8 +1108,7 @@ void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) } } -void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) -{ +void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) { if (arg1 == 0 && TCG_TARGET_HAS_neg_i64) { /* Don't recurse with tcg_gen_neg_i64. */ tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg2); @@ -1215,8 +1119,7 @@ void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) } } -void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ +void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { /* some cases can be optimized here */ if (arg2 == 0) { tcg_gen_mov_i64(ret, arg1); @@ -1227,8 +1130,7 @@ void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) } } -void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ +void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { TCGv_i64 t0; if (TCG_TARGET_REG_BITS == 32) { @@ -1239,39 +1141,38 @@ void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) /* Some cases can be optimized here. */ switch (arg2) { - case 0: - tcg_gen_movi_i64(ret, 0); - return; - case -1: - tcg_gen_mov_i64(ret, arg1); - return; - case 0xff: - /* Don't recurse with tcg_gen_ext8u_i64. */ - if (TCG_TARGET_HAS_ext8u_i64) { - tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg1); - return; - } - break; - case 0xffff: - if (TCG_TARGET_HAS_ext16u_i64) { - tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg1); + case 0: + tcg_gen_movi_i64(ret, 0); return; - } - break; - case 0xffffffffu: - if (TCG_TARGET_HAS_ext32u_i64) { - tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg1); + case -1: + tcg_gen_mov_i64(ret, arg1); return; - } - break; + case 0xff: + /* Don't recurse with tcg_gen_ext8u_i64. */ + if (TCG_TARGET_HAS_ext8u_i64) { + tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg1); + return; + } + break; + case 0xffff: + if (TCG_TARGET_HAS_ext16u_i64) { + tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg1); + return; + } + break; + case 0xffffffffu: + if (TCG_TARGET_HAS_ext32u_i64) { + tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg1); + return; + } + break; } t0 = tcg_const_i64(arg2); tcg_gen_and_i64(ret, arg1, t0); tcg_temp_free_i64(t0); } -void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ +void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); @@ -1289,8 +1190,7 @@ void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) } } -void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ +void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); @@ -1309,9 +1209,7 @@ void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) } } -static inline void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1, - unsigned c, bool right, bool arith) -{ +static inline void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned c, bool right, bool arith) { tcg_debug_assert(c < 64); if (c == 0) { tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); @@ -1358,8 +1256,7 @@ static inline void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1, } } -void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ +void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { tcg_debug_assert(arg2 >= 0 && arg2 < 64); if (TCG_TARGET_REG_BITS == 32) { tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); @@ -1372,8 +1269,7 @@ void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) } } -void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ +void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { tcg_debug_assert(arg2 >= 0 && arg2 < 64); if (TCG_TARGET_REG_BITS == 32) { tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); @@ -1386,8 +1282,7 @@ void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) } } -void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ +void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { tcg_debug_assert(arg2 >= 0 && arg2 < 64); if (TCG_TARGET_REG_BITS == 32) { tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); @@ -1400,25 +1295,21 @@ void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) } } -void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *l) -{ +void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *l) { if (cond == TCG_COND_ALWAYS) { tcg_gen_br(l); } else if (cond != TCG_COND_NEVER) { l->refs++; if (TCG_TARGET_REG_BITS == 32) { - tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, TCGV_LOW(arg1), - TCGV_HIGH(arg1), TCGV_LOW(arg2), - TCGV_HIGH(arg2), cond, label_arg(l)); + tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2), + cond, label_arg(l)); } else { - tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, - label_arg(l)); + tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_arg(l)); } } } -void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *l) -{ +void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *l) { if (cond == TCG_COND_ALWAYS) { tcg_gen_br(l); } else if (cond != TCG_COND_NEVER) { @@ -1428,18 +1319,15 @@ void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *l) } } -void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, - TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { if (cond == TCG_COND_ALWAYS) { tcg_gen_movi_i64(ret, 1); } else if (cond == TCG_COND_NEVER) { tcg_gen_movi_i64(ret, 0); } else { if (TCG_TARGET_REG_BITS == 32) { - tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), - TCGV_LOW(arg1), TCGV_HIGH(arg1), - TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); + tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), + TCGV_HIGH(arg2), cond); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); } else { tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond); @@ -1447,16 +1335,13 @@ void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, } } -void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, - TCGv_i64 arg1, int64_t arg2) -{ +void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { TCGv_i64 t0 = tcg_const_i64(arg2); tcg_gen_setcond_i64(cond, ret, arg1, t0); tcg_temp_free_i64(t0); } -void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ +void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { if (arg2 == 0) { tcg_gen_movi_i64(ret, 0); } else if (is_power_of_2(arg2)) { @@ -1468,8 +1353,7 @@ void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) } } -void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { if (TCG_TARGET_HAS_div_i64) { tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2); } else if (TCG_TARGET_HAS_div2_i64) { @@ -1483,8 +1367,7 @@ void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) } } -void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { if (TCG_TARGET_HAS_rem_i64) { tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2); } else if (TCG_TARGET_HAS_div_i64) { @@ -1500,12 +1383,11 @@ void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) tcg_temp_free_i64(t0); } else { abort(); - //gen_helper_rem_i64(ret, arg1, arg2); + // gen_helper_rem_i64(ret, arg1, arg2); } } -void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { if (TCG_TARGET_HAS_div_i64) { tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2); } else if (TCG_TARGET_HAS_div2_i64) { @@ -1519,8 +1401,7 @@ void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) } } -void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { if (TCG_TARGET_HAS_rem_i64) { tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2); } else if (TCG_TARGET_HAS_div_i64) { @@ -1540,8 +1421,7 @@ void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) } } -void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) -{ +void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); @@ -1553,8 +1433,7 @@ void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) } } -void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) -{ +void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); @@ -1566,8 +1445,7 @@ void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) } } -void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) -{ +void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); @@ -1579,8 +1457,7 @@ void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) } } -void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) -{ +void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); @@ -1591,8 +1468,7 @@ void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) } } -void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) -{ +void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); @@ -1603,8 +1479,7 @@ void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) } } -void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) -{ +void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); @@ -1616,8 +1491,7 @@ void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) } /* Note: we assume the six high bytes are set to zero */ -void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) -{ +void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg)); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); @@ -1635,8 +1509,7 @@ void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) } /* Note: we assume the four high bytes are set to zero */ -void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) -{ +void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg)); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); @@ -1647,17 +1520,17 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) TCGv_i64 t1 = tcg_temp_new_i64(); TCGv_i64 t2 = tcg_const_i64(0x00ff00ff); - /* arg = ....abcd */ - tcg_gen_shri_i64(t0, arg, 8); /* t0 = .....abc */ - tcg_gen_and_i64(t1, arg, t2); /* t1 = .....b.d */ - tcg_gen_and_i64(t0, t0, t2); /* t0 = .....a.c */ - tcg_gen_shli_i64(t1, t1, 8); /* t1 = ....b.d. */ - tcg_gen_or_i64(ret, t0, t1); /* ret = ....badc */ + /* arg = ....abcd */ + tcg_gen_shri_i64(t0, arg, 8); /* t0 = .....abc */ + tcg_gen_and_i64(t1, arg, t2); /* t1 = .....b.d */ + tcg_gen_and_i64(t0, t0, t2); /* t0 = .....a.c */ + tcg_gen_shli_i64(t1, t1, 8); /* t1 = ....b.d. */ + tcg_gen_or_i64(ret, t0, t1); /* ret = ....badc */ - tcg_gen_shli_i64(t1, ret, 48); /* t1 = dc...... */ - tcg_gen_shri_i64(t0, ret, 16); /* t0 = ......ba */ - tcg_gen_shri_i64(t1, t1, 32); /* t1 = ....dc.. */ - tcg_gen_or_i64(ret, t0, t1); /* ret = ....dcba */ + tcg_gen_shli_i64(t1, ret, 48); /* t1 = dc...... */ + tcg_gen_shri_i64(t0, ret, 16); /* t0 = ......ba */ + tcg_gen_shri_i64(t1, t1, 32); /* t1 = ....dc.. */ + tcg_gen_or_i64(ret, t0, t1); /* ret = ....dcba */ tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); @@ -1665,8 +1538,7 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) } } -void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) -{ +void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) { if (TCG_TARGET_REG_BITS == 32) { TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); @@ -1685,24 +1557,24 @@ void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) TCGv_i64 t1 = tcg_temp_new_i64(); TCGv_i64 t2 = tcg_temp_new_i64(); - /* arg = abcdefgh */ + /* arg = abcdefgh */ tcg_gen_movi_i64(t2, 0x00ff00ff00ff00ffull); - tcg_gen_shri_i64(t0, arg, 8); /* t0 = .abcdefg */ - tcg_gen_and_i64(t1, arg, t2); /* t1 = .b.d.f.h */ - tcg_gen_and_i64(t0, t0, t2); /* t0 = .a.c.e.g */ - tcg_gen_shli_i64(t1, t1, 8); /* t1 = b.d.f.h. */ - tcg_gen_or_i64(ret, t0, t1); /* ret = badcfehg */ + tcg_gen_shri_i64(t0, arg, 8); /* t0 = .abcdefg */ + tcg_gen_and_i64(t1, arg, t2); /* t1 = .b.d.f.h */ + tcg_gen_and_i64(t0, t0, t2); /* t0 = .a.c.e.g */ + tcg_gen_shli_i64(t1, t1, 8); /* t1 = b.d.f.h. */ + tcg_gen_or_i64(ret, t0, t1); /* ret = badcfehg */ tcg_gen_movi_i64(t2, 0x0000ffff0000ffffull); - tcg_gen_shri_i64(t0, ret, 16); /* t0 = ..badcfe */ - tcg_gen_and_i64(t1, ret, t2); /* t1 = ..dc..hg */ - tcg_gen_and_i64(t0, t0, t2); /* t0 = ..ba..fe */ - tcg_gen_shli_i64(t1, t1, 16); /* t1 = dc..hg.. */ - tcg_gen_or_i64(ret, t0, t1); /* ret = dcbahgfe */ + tcg_gen_shri_i64(t0, ret, 16); /* t0 = ..badcfe */ + tcg_gen_and_i64(t1, ret, t2); /* t1 = ..dc..hg */ + tcg_gen_and_i64(t0, t0, t2); /* t0 = ..ba..fe */ + tcg_gen_shli_i64(t1, t1, 16); /* t1 = dc..hg.. */ + tcg_gen_or_i64(ret, t0, t1); /* ret = dcbahgfe */ - tcg_gen_shri_i64(t0, ret, 32); /* t0 = ....dcba */ - tcg_gen_shli_i64(t1, ret, 32); /* t1 = hgfe.... */ - tcg_gen_or_i64(ret, t0, t1); /* ret = hgfedcba */ + tcg_gen_shri_i64(t0, ret, 32); /* t0 = ....dcba */ + tcg_gen_shli_i64(t1, ret, 32); /* t1 = hgfe.... */ + tcg_gen_or_i64(ret, t0, t1); /* ret = hgfedcba */ tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); @@ -1710,8 +1582,7 @@ void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) } } -void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) -{ +void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg)); tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); @@ -1722,8 +1593,7 @@ void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) } } -void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); @@ -1737,8 +1607,7 @@ void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) } } -void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); @@ -1750,8 +1619,7 @@ void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) } } -void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); @@ -1763,8 +1631,7 @@ void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) } } -void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); @@ -1776,8 +1643,7 @@ void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) } } -void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); @@ -1791,8 +1657,7 @@ void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) } } -void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { if (TCG_TARGET_HAS_clz_i64) { tcg_gen_op3_i64(INDEX_op_clz_i64, ret, arg1, arg2); } else { @@ -1801,12 +1666,9 @@ void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) } } -void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) -{ - if (TCG_TARGET_REG_BITS == 32 - && TCG_TARGET_HAS_clz_i32 - && arg2 <= 0xffffffffu) { - TCGv_i32 t = tcg_const_i32((uint32_t)arg2 - 32); +void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) { + if (TCG_TARGET_REG_BITS == 32 && TCG_TARGET_HAS_clz_i32 && arg2 <= 0xffffffffu) { + TCGv_i32 t = tcg_const_i32((uint32_t) arg2 - 32); tcg_gen_clz_i32(t, TCGV_LOW(arg1), t); tcg_gen_addi_i32(t, t, 32); tcg_gen_clz_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), t); @@ -1819,8 +1681,7 @@ void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) } } -void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { if (TCG_TARGET_HAS_ctz_i64) { tcg_gen_op3_i64(INDEX_op_ctz_i64, ret, arg1, arg2); } else if (TCG_TARGET_HAS_ctpop_i64 || TCG_TARGET_HAS_clz_i64) { @@ -1847,20 +1708,15 @@ void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) } } -void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) -{ - if (TCG_TARGET_REG_BITS == 32 - && TCG_TARGET_HAS_ctz_i32 - && arg2 <= 0xffffffffu) { - TCGv_i32 t32 = tcg_const_i32((uint32_t)arg2 - 32); +void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) { + if (TCG_TARGET_REG_BITS == 32 && TCG_TARGET_HAS_ctz_i32 && arg2 <= 0xffffffffu) { + TCGv_i32 t32 = tcg_const_i32((uint32_t) arg2 - 32); tcg_gen_ctz_i32(t32, TCGV_HIGH(arg1), t32); tcg_gen_addi_i32(t32, t32, 32); tcg_gen_ctz_i32(TCGV_LOW(ret), TCGV_LOW(arg1), t32); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); tcg_temp_free_i32(t32); - } else if (!TCG_TARGET_HAS_ctz_i64 - && TCG_TARGET_HAS_ctpop_i64 - && arg2 == 64) { + } else if (!TCG_TARGET_HAS_ctz_i64 && TCG_TARGET_HAS_ctpop_i64 && arg2 == 64) { /* This equivalence has the advantage of not requiring a fixup. */ TCGv_i64 t = tcg_temp_new_i64(); tcg_gen_subi_i64(t, arg1, 1); @@ -1874,8 +1730,7 @@ void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) } } -void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg) -{ +void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg) { if (TCG_TARGET_HAS_clz_i64 || TCG_TARGET_HAS_clz_i32) { TCGv_i64 t = tcg_temp_new_i64(); tcg_gen_sari_i64(t, arg, 63); @@ -1889,8 +1744,7 @@ void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg) } } -void tcg_gen_ctpop_i64(TCGv_i64 ret, TCGv_i64 arg1) -{ +void tcg_gen_ctpop_i64(TCGv_i64 ret, TCGv_i64 arg1) { if (TCG_TARGET_HAS_ctpop_i64) { tcg_gen_op2_i64(INDEX_op_ctpop_i64, ret, arg1); } else if (TCG_TARGET_REG_BITS == 32 && TCG_TARGET_HAS_ctpop_i32) { @@ -1904,8 +1758,7 @@ void tcg_gen_ctpop_i64(TCGv_i64 ret, TCGv_i64 arg1) } } -void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { if (TCG_TARGET_HAS_rot_i64) { tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2); } else { @@ -1921,8 +1774,7 @@ void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) } } -void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2) -{ +void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2) { tcg_debug_assert(arg2 < 64); /* some cases can be optimized here */ if (arg2 == 0) { @@ -1943,8 +1795,7 @@ void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2) } } -void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { if (TCG_TARGET_HAS_rot_i64) { tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2); } else { @@ -1960,8 +1811,7 @@ void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) } } -void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2) -{ +void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2) { tcg_debug_assert(arg2 < 64); /* some cases can be optimized here */ if (arg2 == 0) { @@ -1971,9 +1821,7 @@ void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2) } } -void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, - unsigned int ofs, unsigned int len) -{ +void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, unsigned int ofs, unsigned int len) { uint64_t mask; TCGv_i64 t1; @@ -1993,14 +1841,12 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, if (TCG_TARGET_REG_BITS == 32) { if (ofs >= 32) { - tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), - TCGV_LOW(arg2), ofs - 32, len); + tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_LOW(arg2), ofs - 32, len); tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); return; } if (ofs + len <= 32) { - tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1), - TCGV_LOW(arg2), ofs, len); + tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2), ofs, len); tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1)); return; } @@ -2021,9 +1867,7 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, tcg_temp_free_i64(t1); } -void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, - unsigned int ofs, unsigned int len) -{ +void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len) { tcg_debug_assert(ofs < 64); tcg_debug_assert(len > 0); tcg_debug_assert(len <= 64); @@ -2033,16 +1877,14 @@ void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, tcg_gen_shli_i64(ret, arg, ofs); } else if (ofs == 0) { tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); - } else if (TCG_TARGET_HAS_deposit_i64 - && TCG_TARGET_deposit_i64_valid(ofs, len)) { + } else if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) { TCGv_i64 zero = tcg_const_i64(0); tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, zero, arg, ofs, len); tcg_temp_free_i64(zero); } else { if (TCG_TARGET_REG_BITS == 32) { if (ofs >= 32) { - tcg_gen_deposit_z_i32(TCGV_HIGH(ret), TCGV_LOW(arg), - ofs - 32, len); + tcg_gen_deposit_z_i32(TCGV_HIGH(ret), TCGV_LOW(arg), ofs - 32, len); tcg_gen_movi_i32(TCGV_LOW(ret), 0); return; } @@ -2055,60 +1897,58 @@ void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, /* To help two-operand hosts we prefer to zero-extend first, which allows ARG to stay live. */ switch (len) { - case 32: - if (TCG_TARGET_HAS_ext32u_i64) { - tcg_gen_ext32u_i64(ret, arg); - tcg_gen_shli_i64(ret, ret, ofs); - return; - } - break; - case 16: - if (TCG_TARGET_HAS_ext16u_i64) { - tcg_gen_ext16u_i64(ret, arg); - tcg_gen_shli_i64(ret, ret, ofs); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i64) { - tcg_gen_ext8u_i64(ret, arg); - tcg_gen_shli_i64(ret, ret, ofs); - return; - } - break; + case 32: + if (TCG_TARGET_HAS_ext32u_i64) { + tcg_gen_ext32u_i64(ret, arg); + tcg_gen_shli_i64(ret, ret, ofs); + return; + } + break; + case 16: + if (TCG_TARGET_HAS_ext16u_i64) { + tcg_gen_ext16u_i64(ret, arg); + tcg_gen_shli_i64(ret, ret, ofs); + return; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8u_i64) { + tcg_gen_ext8u_i64(ret, arg); + tcg_gen_shli_i64(ret, ret, ofs); + return; + } + break; } /* Otherwise prefer zero-extension over AND for code size. */ switch (ofs + len) { - case 32: - if (TCG_TARGET_HAS_ext32u_i64) { - tcg_gen_shli_i64(ret, arg, ofs); - tcg_gen_ext32u_i64(ret, ret); - return; - } - break; - case 16: - if (TCG_TARGET_HAS_ext16u_i64) { - tcg_gen_shli_i64(ret, arg, ofs); - tcg_gen_ext16u_i64(ret, ret); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i64) { - tcg_gen_shli_i64(ret, arg, ofs); - tcg_gen_ext8u_i64(ret, ret); - return; - } - break; + case 32: + if (TCG_TARGET_HAS_ext32u_i64) { + tcg_gen_shli_i64(ret, arg, ofs); + tcg_gen_ext32u_i64(ret, ret); + return; + } + break; + case 16: + if (TCG_TARGET_HAS_ext16u_i64) { + tcg_gen_shli_i64(ret, arg, ofs); + tcg_gen_ext16u_i64(ret, ret); + return; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8u_i64) { + tcg_gen_shli_i64(ret, arg, ofs); + tcg_gen_ext8u_i64(ret, ret); + return; + } + break; } tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); tcg_gen_shli_i64(ret, ret, ofs); } } -void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, - unsigned int ofs, unsigned int len) -{ +void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len) { tcg_debug_assert(ofs < 64); tcg_debug_assert(len > 0); tcg_debug_assert(len <= 64); @@ -2141,56 +1981,55 @@ void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, goto do_shift_and; } - if (TCG_TARGET_HAS_extract_i64 - && TCG_TARGET_extract_i64_valid(ofs, len)) { + if (TCG_TARGET_HAS_extract_i64 && TCG_TARGET_extract_i64_valid(ofs, len)) { tcg_gen_op4ii_i64(INDEX_op_extract_i64, ret, arg, ofs, len); return; } /* Assume that zero-extension, if available, is cheaper than a shift. */ switch (ofs + len) { - case 32: - if (TCG_TARGET_HAS_ext32u_i64) { - tcg_gen_ext32u_i64(ret, arg); - tcg_gen_shri_i64(ret, ret, ofs); - return; - } - break; - case 16: - if (TCG_TARGET_HAS_ext16u_i64) { - tcg_gen_ext16u_i64(ret, arg); - tcg_gen_shri_i64(ret, ret, ofs); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i64) { - tcg_gen_ext8u_i64(ret, arg); - tcg_gen_shri_i64(ret, ret, ofs); - return; - } - break; + case 32: + if (TCG_TARGET_HAS_ext32u_i64) { + tcg_gen_ext32u_i64(ret, arg); + tcg_gen_shri_i64(ret, ret, ofs); + return; + } + break; + case 16: + if (TCG_TARGET_HAS_ext16u_i64) { + tcg_gen_ext16u_i64(ret, arg); + tcg_gen_shri_i64(ret, ret, ofs); + return; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8u_i64) { + tcg_gen_ext8u_i64(ret, arg); + tcg_gen_shri_i64(ret, ret, ofs); + return; + } + break; } /* ??? Ideally we'd know what values are available for immediate AND. Assume that 8 bits are available, plus the special cases of 16 and 32, so that we get ext8u, ext16u, and ext32u. */ switch (len) { - case 1 ... 8: case 16: case 32: - do_shift_and: - tcg_gen_shri_i64(ret, arg, ofs); - tcg_gen_andi_i64(ret, ret, (1ull << len) - 1); - break; - default: - tcg_gen_shli_i64(ret, arg, 64 - len - ofs); - tcg_gen_shri_i64(ret, ret, 64 - len); - break; + case 1 ... 8: + case 16: + case 32: + do_shift_and: + tcg_gen_shri_i64(ret, arg, ofs); + tcg_gen_andi_i64(ret, ret, (1ull << len) - 1); + break; + default: + tcg_gen_shli_i64(ret, arg, 64 - len - ofs); + tcg_gen_shri_i64(ret, ret, 64 - len); + break; } } -void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, - unsigned int ofs, unsigned int len) -{ +void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len) { tcg_debug_assert(ofs < 64); tcg_debug_assert(len > 0); tcg_debug_assert(len <= 64); @@ -2203,15 +2042,15 @@ void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, } if (ofs == 0) { switch (len) { - case 32: - tcg_gen_ext32s_i64(ret, arg); - return; - case 16: - tcg_gen_ext16s_i64(ret, arg); - return; - case 8: - tcg_gen_ext8s_i64(ret, arg); - return; + case 32: + tcg_gen_ext32s_i64(ret, arg); + return; + case 16: + tcg_gen_ext16s_i64(ret, arg); + return; + case 8: + tcg_gen_ext8s_i64(ret, arg); + return; } } @@ -2247,66 +2086,63 @@ void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, return; } - if (TCG_TARGET_HAS_sextract_i64 - && TCG_TARGET_extract_i64_valid(ofs, len)) { + if (TCG_TARGET_HAS_sextract_i64 && TCG_TARGET_extract_i64_valid(ofs, len)) { tcg_gen_op4ii_i64(INDEX_op_sextract_i64, ret, arg, ofs, len); return; } /* Assume that sign-extension, if available, is cheaper than a shift. */ switch (ofs + len) { - case 32: - if (TCG_TARGET_HAS_ext32s_i64) { - tcg_gen_ext32s_i64(ret, arg); - tcg_gen_sari_i64(ret, ret, ofs); - return; - } - break; - case 16: - if (TCG_TARGET_HAS_ext16s_i64) { - tcg_gen_ext16s_i64(ret, arg); - tcg_gen_sari_i64(ret, ret, ofs); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8s_i64) { - tcg_gen_ext8s_i64(ret, arg); - tcg_gen_sari_i64(ret, ret, ofs); - return; - } - break; + case 32: + if (TCG_TARGET_HAS_ext32s_i64) { + tcg_gen_ext32s_i64(ret, arg); + tcg_gen_sari_i64(ret, ret, ofs); + return; + } + break; + case 16: + if (TCG_TARGET_HAS_ext16s_i64) { + tcg_gen_ext16s_i64(ret, arg); + tcg_gen_sari_i64(ret, ret, ofs); + return; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8s_i64) { + tcg_gen_ext8s_i64(ret, arg); + tcg_gen_sari_i64(ret, ret, ofs); + return; + } + break; } switch (len) { - case 32: - if (TCG_TARGET_HAS_ext32s_i64) { - tcg_gen_shri_i64(ret, arg, ofs); - tcg_gen_ext32s_i64(ret, ret); - return; - } - break; - case 16: - if (TCG_TARGET_HAS_ext16s_i64) { - tcg_gen_shri_i64(ret, arg, ofs); - tcg_gen_ext16s_i64(ret, ret); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8s_i64) { - tcg_gen_shri_i64(ret, arg, ofs); - tcg_gen_ext8s_i64(ret, ret); - return; - } - break; + case 32: + if (TCG_TARGET_HAS_ext32s_i64) { + tcg_gen_shri_i64(ret, arg, ofs); + tcg_gen_ext32s_i64(ret, ret); + return; + } + break; + case 16: + if (TCG_TARGET_HAS_ext16s_i64) { + tcg_gen_shri_i64(ret, arg, ofs); + tcg_gen_ext16s_i64(ret, ret); + return; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8s_i64) { + tcg_gen_shri_i64(ret, arg, ofs); + tcg_gen_ext8s_i64(ret, ret); + return; + } + break; } tcg_gen_shli_i64(ret, arg, 64 - len - ofs); tcg_gen_sari_i64(ret, ret, 64 - len); } -void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, - TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2) -{ +void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2) { if (cond == TCG_COND_ALWAYS) { tcg_gen_mov_i64(ret, v1); } else if (cond == TCG_COND_NEVER) { @@ -2314,16 +2150,12 @@ void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, } else if (TCG_TARGET_REG_BITS == 32) { TCGv_i32 t0 = tcg_temp_new_i32(); TCGv_i32 t1 = tcg_temp_new_i32(); - tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0, - TCGV_LOW(c1), TCGV_HIGH(c1), - TCGV_LOW(c2), TCGV_HIGH(c2), cond); + tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0, TCGV_LOW(c1), TCGV_HIGH(c1), TCGV_LOW(c2), TCGV_HIGH(c2), cond); if (TCG_TARGET_HAS_movcond_i32) { tcg_gen_movi_i32(t1, 0); - tcg_gen_movcond_i32(TCG_COND_NE, TCGV_LOW(ret), t0, t1, - TCGV_LOW(v1), TCGV_LOW(v2)); - tcg_gen_movcond_i32(TCG_COND_NE, TCGV_HIGH(ret), t0, t1, - TCGV_HIGH(v1), TCGV_HIGH(v2)); + tcg_gen_movcond_i32(TCG_COND_NE, TCGV_LOW(ret), t0, t1, TCGV_LOW(v1), TCGV_LOW(v2)); + tcg_gen_movcond_i32(TCG_COND_NE, TCGV_HIGH(ret), t0, t1, TCGV_HIGH(v1), TCGV_HIGH(v2)); } else { tcg_gen_neg_i32(t0, t0); @@ -2352,9 +2184,7 @@ void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, } } -void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, - TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) -{ +void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) { if (TCG_TARGET_HAS_add2_i64) { tcg_gen_op6_i64(INDEX_op_add2_i64, rl, rh, al, ah, bl, bh); } else { @@ -2370,9 +2200,7 @@ void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, } } -void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, - TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) -{ +void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) { if (TCG_TARGET_HAS_sub2_i64) { tcg_gen_op6_i64(INDEX_op_sub2_i64, rl, rh, al, ah, bl, bh); } else { @@ -2388,8 +2216,7 @@ void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, } } -void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2) { if (TCG_TARGET_HAS_mulu2_i64) { tcg_gen_op4_i64(INDEX_op_mulu2_i64, rl, rh, arg1, arg2); } else if (TCG_TARGET_HAS_muluh_i64) { @@ -2403,15 +2230,14 @@ void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2) tcg_gen_mul_i64(t0, arg1, arg2); abort(); - //gen_helper_muluh_i64(rh, arg1, arg2); + // gen_helper_muluh_i64(rh, arg1, arg2); tcg_gen_mov_i64(rl, t0); tcg_temp_free_i64(t0); } } -void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2) { if (TCG_TARGET_HAS_muls2_i64) { tcg_gen_op4_i64(INDEX_op_muls2_i64, rl, rh, arg1, arg2); } else if (TCG_TARGET_HAS_mulsh_i64) { @@ -2450,8 +2276,7 @@ void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2) } } -void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2) -{ +void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2) { TCGv_i64 t0 = tcg_temp_new_i64(); TCGv_i64 t1 = tcg_temp_new_i64(); TCGv_i64 t2 = tcg_temp_new_i64(); @@ -2466,79 +2291,66 @@ void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2) tcg_temp_free_i64(t2); } -void tcg_gen_smin_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) -{ +void tcg_gen_smin_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) { tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, a, b); } -void tcg_gen_umin_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) -{ +void tcg_gen_umin_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) { tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, a, b); } -void tcg_gen_smax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) -{ +void tcg_gen_smax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) { tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, b, a); } -void tcg_gen_umax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) -{ +void tcg_gen_umax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) { tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, b, a); } /* Size changing operations. */ -void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg) -{ +void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_mov_i32(ret, TCGV_LOW(arg)); } else if (TCG_TARGET_HAS_extrl_i64_i32) { - tcg_gen_op2(INDEX_op_extrl_i64_i32, - tcgv_i32_arg(ret), tcgv_i64_arg(arg)); + tcg_gen_op2(INDEX_op_extrl_i64_i32, tcgv_i32_arg(ret), tcgv_i64_arg(arg)); } else { - tcg_gen_mov_i32(ret, (TCGv_i32)arg); + tcg_gen_mov_i32(ret, (TCGv_i32) arg); } } -void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg) -{ +void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_mov_i32(ret, TCGV_HIGH(arg)); } else if (TCG_TARGET_HAS_extrh_i64_i32) { - tcg_gen_op2(INDEX_op_extrh_i64_i32, - tcgv_i32_arg(ret), tcgv_i64_arg(arg)); + tcg_gen_op2(INDEX_op_extrh_i64_i32, tcgv_i32_arg(ret), tcgv_i64_arg(arg)); } else { TCGv_i64 t = tcg_temp_new_i64(); tcg_gen_shri_i64(t, arg, 32); - tcg_gen_mov_i32(ret, (TCGv_i32)t); + tcg_gen_mov_i32(ret, (TCGv_i32) t); tcg_temp_free_i64(t); } } -void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) -{ +void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_mov_i32(TCGV_LOW(ret), arg); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); } else { - tcg_gen_op2(INDEX_op_extu_i32_i64, - tcgv_i64_arg(ret), tcgv_i32_arg(arg)); + tcg_gen_op2(INDEX_op_extu_i32_i64, tcgv_i64_arg(ret), tcgv_i32_arg(arg)); } } -void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) -{ +void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_mov_i32(TCGV_LOW(ret), arg); tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); } else { - tcg_gen_op2(INDEX_op_ext_i32_i64, - tcgv_i64_arg(ret), tcgv_i32_arg(arg)); + tcg_gen_op2(INDEX_op_ext_i32_i64, tcgv_i64_arg(ret), tcgv_i32_arg(arg)); } } -void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high) -{ +void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high) { TCGv_i64 tmp; if (TCG_TARGET_REG_BITS == 32) { @@ -2563,8 +2375,7 @@ void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high) tcg_temp_free_i64(tmp); } -void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg) -{ +void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg) { if (TCG_TARGET_REG_BITS == 32) { tcg_gen_mov_i32(lo, TCGV_LOW(arg)); tcg_gen_mov_i32(hi, TCGV_HIGH(arg)); @@ -2574,17 +2385,15 @@ void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg) } } -void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg) -{ +void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg) { tcg_gen_ext32u_i64(lo, arg); tcg_gen_shri_i64(hi, arg, 32); } /* QEMU specific operations. */ -void tcg_gen_exit_tb(TranslationBlock *tb, unsigned idx) -{ - uintptr_t val = (uintptr_t)tb + idx; +void tcg_gen_exit_tb(TranslationBlock *tb, unsigned idx) { + uintptr_t val = (uintptr_t) tb + idx; if (tb == NULL) { tcg_debug_assert(idx == 0); @@ -2606,8 +2415,7 @@ void tcg_gen_exit_tb(TranslationBlock *tb, unsigned idx) tcg_gen_op1i(INDEX_op_exit_tb, val); } -void tcg_gen_goto_tb(unsigned idx) -{ +void tcg_gen_goto_tb(unsigned idx) { /* We only support two chained exits. */ tcg_debug_assert(idx <= TB_EXIT_IDXMAX); #ifdef CONFIG_DEBUG_TCG @@ -2621,27 +2429,26 @@ void tcg_gen_goto_tb(unsigned idx) } } -static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st) -{ +static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st) { /* Trigger the asserts within as early as possible. */ - (void)get_alignment_bits(op); + (void) get_alignment_bits(op); switch (op & MO_SIZE) { - case MO_8: - op &= ~MO_BSWAP; - break; - case MO_16: - break; - case MO_32: - if (!is64) { - op &= ~MO_SIGN; - } - break; - case MO_64: - if (!is64) { - tcg_abort(); - } - break; + case MO_8: + op &= ~MO_BSWAP; + break; + case MO_16: + break; + case MO_32: + if (!is64) { + op &= ~MO_SIGN; + } + break; + case MO_64: + if (!is64) { + tcg_abort(); + } + break; } if (st) { op &= ~MO_SIGN; @@ -2649,9 +2456,7 @@ static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st) return op; } -static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr, - TCGMemOp memop, TCGArg idx) -{ +static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr, TCGMemOp memop, TCGArg idx) { TCGMemOpIdx oi = make_memop_idx(memop, idx); #if TARGET_LONG_BITS == 32 tcg_gen_op3i_i32(opc, val, addr, oi); @@ -2664,9 +2469,7 @@ static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr, #endif } -static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr, - TCGMemOp memop, TCGArg idx) -{ +static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr, TCGMemOp memop, TCGArg idx) { TCGMemOpIdx oi = make_memop_idx(memop, idx); #if TARGET_LONG_BITS == 32 if (TCG_TARGET_REG_BITS == 32) { @@ -2676,16 +2479,14 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr, } #else if (TCG_TARGET_REG_BITS == 32) { - tcg_gen_op5i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), - TCGV_LOW(addr), TCGV_HIGH(addr), oi); + tcg_gen_op5i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), TCGV_LOW(addr), TCGV_HIGH(addr), oi); } else { tcg_gen_op3i_i64(opc, val, addr, oi); } #endif } -static void tcg_gen_req_mo(TCGBar type) -{ +static void tcg_gen_req_mo(TCGBar type) { #ifdef TCG_GUEST_DEFAULT_MO type &= TCG_GUEST_DEFAULT_MO; #endif @@ -2695,14 +2496,12 @@ static void tcg_gen_req_mo(TCGBar type) } } -void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) -{ +void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) { TCGMemOp orig_memop; tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop = tcg_canonicalize_memop(memop, 0, 0); - trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, - addr, trace_mem_get_info(memop, 0)); + trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, trace_mem_get_info(memop, 0)); orig_memop = memop; if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { @@ -2717,42 +2516,40 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) if ((orig_memop ^ memop) & MO_BSWAP) { switch (orig_memop & MO_SIZE) { - case MO_16: - tcg_gen_bswap16_i32(val, val); - if (orig_memop & MO_SIGN) { - tcg_gen_ext16s_i32(val, val); - } - break; - case MO_32: - tcg_gen_bswap32_i32(val, val); - break; - default: - g_assert_not_reached(); + case MO_16: + tcg_gen_bswap16_i32(val, val); + if (orig_memop & MO_SIGN) { + tcg_gen_ext16s_i32(val, val); + } + break; + case MO_32: + tcg_gen_bswap32_i32(val, val); + break; + default: + g_assert_not_reached(); } } } -void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) -{ +void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) { TCGv_i32 swap = NULL; tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop = tcg_canonicalize_memop(memop, 0, 1); - trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, - addr, trace_mem_get_info(memop, 1)); + trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, trace_mem_get_info(memop, 1)); if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { swap = tcg_temp_new_i32(); switch (memop & MO_SIZE) { - case MO_16: - tcg_gen_ext16u_i32(swap, val); - tcg_gen_bswap16_i32(swap, swap); - break; - case MO_32: - tcg_gen_bswap32_i32(swap, val); - break; - default: - g_assert_not_reached(); + case MO_16: + tcg_gen_ext16u_i32(swap, val); + tcg_gen_bswap16_i32(swap, swap); + break; + case MO_32: + tcg_gen_bswap32_i32(swap, val); + break; + default: + g_assert_not_reached(); } val = swap; memop &= ~MO_BSWAP; @@ -2765,8 +2562,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) } } -void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) -{ +void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) { TCGMemOp orig_memop; if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) { @@ -2781,8 +2577,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop = tcg_canonicalize_memop(memop, 1, 0); - trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, - addr, trace_mem_get_info(memop, 0)); + trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, trace_mem_get_info(memop, 0)); orig_memop = memop; if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { @@ -2797,29 +2592,28 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) if ((orig_memop ^ memop) & MO_BSWAP) { switch (orig_memop & MO_SIZE) { - case MO_16: - tcg_gen_bswap16_i64(val, val); - if (orig_memop & MO_SIGN) { - tcg_gen_ext16s_i64(val, val); - } - break; - case MO_32: - tcg_gen_bswap32_i64(val, val); - if (orig_memop & MO_SIGN) { - tcg_gen_ext32s_i64(val, val); - } - break; - case MO_64: - tcg_gen_bswap64_i64(val, val); - break; - default: - g_assert_not_reached(); + case MO_16: + tcg_gen_bswap16_i64(val, val); + if (orig_memop & MO_SIGN) { + tcg_gen_ext16s_i64(val, val); + } + break; + case MO_32: + tcg_gen_bswap32_i64(val, val); + if (orig_memop & MO_SIGN) { + tcg_gen_ext32s_i64(val, val); + } + break; + case MO_64: + tcg_gen_bswap64_i64(val, val); + break; + default: + g_assert_not_reached(); } } } -void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) -{ +void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) { TCGv_i64 swap = NULL; if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) { @@ -2829,25 +2623,24 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop = tcg_canonicalize_memop(memop, 1, 1); - trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, - addr, trace_mem_get_info(memop, 1)); + trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, trace_mem_get_info(memop, 1)); if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { swap = tcg_temp_new_i64(); switch (memop & MO_SIZE) { - case MO_16: - tcg_gen_ext16u_i64(swap, val); - tcg_gen_bswap16_i64(swap, swap); - break; - case MO_32: - tcg_gen_ext32u_i64(swap, val); - tcg_gen_bswap32_i64(swap, swap); - break; - case MO_64: - tcg_gen_bswap64_i64(swap, val); - break; - default: - g_assert_not_reached(); + case MO_16: + tcg_gen_ext16u_i64(swap, val); + tcg_gen_bswap16_i64(swap, swap); + break; + case MO_32: + tcg_gen_ext32u_i64(swap, val); + tcg_gen_bswap32_i64(swap, swap); + break; + case MO_64: + tcg_gen_bswap64_i64(swap, val); + break; + default: + g_assert_not_reached(); } val = swap; memop &= ~MO_BSWAP; @@ -2859,4 +2652,3 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) tcg_temp_free_i64(swap); } } - diff --git a/src/tcg-pool.inc.c b/src/tcg-pool.inc.c index 7af5513..152aec6 100644 --- a/src/tcg-pool.inc.c +++ b/src/tcg-pool.inc.c @@ -29,12 +29,8 @@ typedef struct TCGLabelPoolData { tcg_target_ulong data[]; } TCGLabelPoolData; - -static TCGLabelPoolData *new_pool_alloc(TCGContext *s, int nlong, int rtype, - tcg_insn_unit *label, intptr_t addend) -{ - TCGLabelPoolData *n = tcg_malloc(sizeof(TCGLabelPoolData) - + sizeof(tcg_target_ulong) * nlong); +static TCGLabelPoolData *new_pool_alloc(TCGContext *s, int nlong, int rtype, tcg_insn_unit *label, intptr_t addend) { + TCGLabelPoolData *n = tcg_malloc(sizeof(TCGLabelPoolData) + sizeof(tcg_target_ulong) * nlong); n->label = label; n->addend = addend; @@ -43,8 +39,7 @@ static TCGLabelPoolData *new_pool_alloc(TCGContext *s, int nlong, int rtype, return n; } -static void new_pool_insert(TCGContext *s, TCGLabelPoolData *n) -{ +static void new_pool_insert(TCGContext *s, TCGLabelPoolData *n) { TCGLabelPoolData *i, **pp; int nlong = n->nlong; @@ -65,19 +60,15 @@ static void new_pool_insert(TCGContext *s, TCGLabelPoolData *n) } /* The "usual" for generic integer code. */ -static inline void new_pool_label(TCGContext *s, tcg_target_ulong d, int rtype, - tcg_insn_unit *label, intptr_t addend) -{ +static inline void new_pool_label(TCGContext *s, tcg_target_ulong d, int rtype, tcg_insn_unit *label, intptr_t addend) { TCGLabelPoolData *n = new_pool_alloc(s, 1, rtype, label, addend); n->data[0] = d; new_pool_insert(s, n); } /* For v64 or v128, depending on the host. */ -static inline void new_pool_l2(TCGContext *s, int rtype, tcg_insn_unit *label, - intptr_t addend, tcg_target_ulong d0, - tcg_target_ulong d1) -{ +static inline void new_pool_l2(TCGContext *s, int rtype, tcg_insn_unit *label, intptr_t addend, tcg_target_ulong d0, + tcg_target_ulong d1) { TCGLabelPoolData *n = new_pool_alloc(s, 2, rtype, label, addend); n->data[0] = d0; n->data[1] = d1; @@ -85,11 +76,8 @@ static inline void new_pool_l2(TCGContext *s, int rtype, tcg_insn_unit *label, } /* For v128 or v256, depending on the host. */ -static inline void new_pool_l4(TCGContext *s, int rtype, tcg_insn_unit *label, - intptr_t addend, tcg_target_ulong d0, - tcg_target_ulong d1, tcg_target_ulong d2, - tcg_target_ulong d3) -{ +static inline void new_pool_l4(TCGContext *s, int rtype, tcg_insn_unit *label, intptr_t addend, tcg_target_ulong d0, + tcg_target_ulong d1, tcg_target_ulong d2, tcg_target_ulong d3) { TCGLabelPoolData *n = new_pool_alloc(s, 4, rtype, label, addend); n->data[0] = d0; n->data[1] = d1; @@ -99,13 +87,9 @@ static inline void new_pool_l4(TCGContext *s, int rtype, tcg_insn_unit *label, } /* For v256, for 32-bit host. */ -static inline void new_pool_l8(TCGContext *s, int rtype, tcg_insn_unit *label, - intptr_t addend, tcg_target_ulong d0, - tcg_target_ulong d1, tcg_target_ulong d2, - tcg_target_ulong d3, tcg_target_ulong d4, - tcg_target_ulong d5, tcg_target_ulong d6, - tcg_target_ulong d7) -{ +static inline void new_pool_l8(TCGContext *s, int rtype, tcg_insn_unit *label, intptr_t addend, tcg_target_ulong d0, + tcg_target_ulong d1, tcg_target_ulong d2, tcg_target_ulong d3, tcg_target_ulong d4, + tcg_target_ulong d5, tcg_target_ulong d6, tcg_target_ulong d7) { TCGLabelPoolData *n = new_pool_alloc(s, 8, rtype, label, addend); n->data[0] = d0; n->data[1] = d1; @@ -121,8 +105,7 @@ static inline void new_pool_l8(TCGContext *s, int rtype, tcg_insn_unit *label, /* To be provided by cpu/tcg-target.inc.c. */ static void tcg_out_nop_fill(tcg_insn_unit *p, int count); -static bool tcg_out_pool_finalize(TCGContext *s) -{ +static bool tcg_out_pool_finalize(TCGContext *s) { TCGLabelPoolData *p = s->pool_labels; TCGLabelPoolData *l = NULL; void *a; @@ -133,9 +116,8 @@ static bool tcg_out_pool_finalize(TCGContext *s) /* ??? Round up to qemu_icache_linesize, but then do not round again when allocating the next TranslationBlock structure. */ - a = (void *)ROUND_UP((uintptr_t)s->code_ptr, - sizeof(tcg_target_ulong) * p->nlong); - tcg_out_nop_fill(s->code_ptr, (tcg_insn_unit *)a - s->code_ptr); + a = (void *) ROUND_UP((uintptr_t) s->code_ptr, sizeof(tcg_target_ulong) * p->nlong); + tcg_out_nop_fill(s->code_ptr, (tcg_insn_unit *) a - s->code_ptr); s->data_gen_ptr = a; for (; p != NULL; p = p->next) { @@ -148,7 +130,7 @@ static bool tcg_out_pool_finalize(TCGContext *s) a += size; l = p; } - patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend); + patch_reloc(p->label, p->rtype, (intptr_t) a - size, p->addend); } s->code_ptr = a; diff --git a/src/tcg.c b/src/tcg.c index 47bd6eb..4cc2321 100644 --- a/src/tcg.c +++ b/src/tcg.c @@ -29,13 +29,13 @@ #include #include #include +#include +#include #include #include #include #include #include -#include -#include #include #include @@ -67,14 +67,14 @@ tcg_settings_t g_tcg_settings; TCGContext tcg_init_ctx; #if UINTPTR_MAX == UINT32_MAX -# define ELF_CLASS ELFCLASS32 +#define ELF_CLASS ELFCLASS32 #else -# define ELF_CLASS ELFCLASS64 +#define ELF_CLASS ELFCLASS64 #endif #ifdef HOST_WORDS_BIGENDIAN -# define ELF_DATA ELFDATA2MSB +#define ELF_DATA ELFDATA2MSB #else -# define ELF_DATA ELFDATA2LSB +#define ELF_DATA ELFDATA2LSB #endif #include "elf.h" @@ -82,14 +82,12 @@ TCGContext tcg_init_ctx; extern FILE *logfile; #define qemu_log(...) fprintf(logfile, __VA_ARGS__) - /* Forward declarations for functions declared in tcg-target.inc.c and used here. */ static void tcg_target_init(TCGContext *s); static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode); static void tcg_target_qemu_prologue(TCGContext *s); -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, - intptr_t value, intptr_t addend); +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend); /* The CIE and FDE header definitions will be common to all hosts. */ typedef struct { @@ -114,40 +112,28 @@ typedef struct __attribute__((packed)) { DebugFrameFDEHeader fde; } DebugFrameHeader; -static void tcg_register_jit_int(void *buf, size_t size, - const void *debug_frame, - size_t debug_frame_size) +static void tcg_register_jit_int(void *buf, size_t size, const void *debug_frame, size_t debug_frame_size) __attribute__((unused)); /* Forward declarations for functions declared and used in tcg-target.inc.c. */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type); -static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, - intptr_t arg2); +static const char *target_parse_constraint(TCGArgConstraint *ct, const char *ct_str, TCGType type); +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, intptr_t arg2); static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); -static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg); -static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, - const int *const_args); +static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); +static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args); #if TCG_TARGET_MAYBE_vec -static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, - unsigned vece, const TCGArg *args, +static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, const TCGArg *args, const int *const_args); #else -static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, - unsigned vece, const TCGArg *args, - const int *const_args) -{ +static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, const TCGArg *args, + const int *const_args) { g_assert_not_reached(); } #endif -static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, - intptr_t arg2); -static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs); +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2); +static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, TCGReg base, intptr_t ofs); static void tcg_out_call(TCGContext *s, tcg_insn_unit *target); -static int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct); +static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct); #ifdef TCG_TARGET_NEED_LDST_LABELS static bool tcg_out_ldst_finalize(TCGContext *s); #endif @@ -178,11 +164,11 @@ struct tcg_region_state { void *start_aligned; void *end; size_t n; - size_t size; /* size of one region */ + size_t size; /* size of one region */ size_t stride; /* .size + guard size */ /* fields protected by the lock */ - size_t current; /* current region index */ + size_t current; /* current region index */ size_t agg_size_full; /* aggregate size of full regions */ }; @@ -198,21 +184,17 @@ static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT]; static TCGRegSet tcg_target_call_clobber_regs; #if TCG_TARGET_INSN_UNIT_SIZE == 1 -static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t v) -{ +static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t v) { *s->code_ptr++ = v; } -static __attribute__((unused)) inline void tcg_patch8(tcg_insn_unit *p, - uint8_t v) -{ +static __attribute__((unused)) inline void tcg_patch8(tcg_insn_unit *p, uint8_t v) { *p = v; } #endif #if TCG_TARGET_INSN_UNIT_SIZE <= 2 -static __attribute__((unused)) inline void tcg_out16(TCGContext *s, uint16_t v) -{ +static __attribute__((unused)) inline void tcg_out16(TCGContext *s, uint16_t v) { if (TCG_TARGET_INSN_UNIT_SIZE == 2) { *s->code_ptr++ = v; } else { @@ -222,9 +204,7 @@ static __attribute__((unused)) inline void tcg_out16(TCGContext *s, uint16_t v) } } -static __attribute__((unused)) inline void tcg_patch16(tcg_insn_unit *p, - uint16_t v) -{ +static __attribute__((unused)) inline void tcg_patch16(tcg_insn_unit *p, uint16_t v) { if (TCG_TARGET_INSN_UNIT_SIZE == 2) { *p = v; } else { @@ -234,8 +214,7 @@ static __attribute__((unused)) inline void tcg_patch16(tcg_insn_unit *p, #endif #if TCG_TARGET_INSN_UNIT_SIZE <= 4 -static __attribute__((unused)) inline void tcg_out32(TCGContext *s, uint32_t v) -{ +static __attribute__((unused)) inline void tcg_out32(TCGContext *s, uint32_t v) { if (TCG_TARGET_INSN_UNIT_SIZE == 4) { *s->code_ptr++ = v; } else { @@ -245,9 +224,7 @@ static __attribute__((unused)) inline void tcg_out32(TCGContext *s, uint32_t v) } } -static __attribute__((unused)) inline void tcg_patch32(tcg_insn_unit *p, - uint32_t v) -{ +static __attribute__((unused)) inline void tcg_patch32(tcg_insn_unit *p, uint32_t v) { if (TCG_TARGET_INSN_UNIT_SIZE == 4) { *p = v; } else { @@ -257,8 +234,7 @@ static __attribute__((unused)) inline void tcg_patch32(tcg_insn_unit *p, #endif #if TCG_TARGET_INSN_UNIT_SIZE <= 8 -static __attribute__((unused)) inline void tcg_out64(TCGContext *s, uint64_t v) -{ +static __attribute__((unused)) inline void tcg_out64(TCGContext *s, uint64_t v) { if (TCG_TARGET_INSN_UNIT_SIZE == 8) { *s->code_ptr++ = v; } else { @@ -268,9 +244,7 @@ static __attribute__((unused)) inline void tcg_out64(TCGContext *s, uint64_t v) } } -static __attribute__((unused)) inline void tcg_patch64(tcg_insn_unit *p, - uint64_t v) -{ +static __attribute__((unused)) inline void tcg_patch64(tcg_insn_unit *p, uint64_t v) { if (TCG_TARGET_INSN_UNIT_SIZE == 8) { *p = v; } else { @@ -281,14 +255,12 @@ static __attribute__((unused)) inline void tcg_patch64(tcg_insn_unit *p, /* label relocation processing */ -static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, - TCGLabel *l, intptr_t addend) -{ +static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, TCGLabel *l, intptr_t addend) { TCGRelocation *r; if (l->has_value) { /* FIXME: This may break relocations on RISC targets that - modify instruction fields in place. The caller may not have + modify instruction fields in place. The caller may not have written the initial value. */ bool ok = patch_reloc(code_ptr, type, l->u.value, addend); tcg_debug_assert(ok); @@ -303,9 +275,8 @@ static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, } } -static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr) -{ - intptr_t value = (intptr_t)ptr; +static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr) { + intptr_t value = (intptr_t) ptr; TCGRelocation *r; tcg_debug_assert(!l->has_value); @@ -319,14 +290,11 @@ static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr) l->u.value_ptr = ptr; } -TCGLabel *gen_new_label(void) -{ +TCGLabel *gen_new_label(void) { TCGContext *s = tcg_ctx; TCGLabel *l = tcg_malloc(sizeof(TCGLabel)); - *l = (TCGLabel){ - .id = s->nb_labels++ - }; + *l = (TCGLabel){.id = s->nb_labels++}; #ifdef CONFIG_DEBUG_TCG QSIMPLEQ_INSERT_TAIL(&s->labels, l, next); #endif @@ -334,8 +302,7 @@ TCGLabel *gen_new_label(void) return l; } -static void set_jmp_reset_offset(TCGContext *s, int which) -{ +static void set_jmp_reset_offset(TCGContext *s, int which) { size_t off = tcg_current_code_size(s); s->tb_jmp_reset_offset[which] = off; /* Make sure that we didn't overflow the stored offset. */ @@ -345,8 +312,7 @@ static void set_jmp_reset_offset(TCGContext *s, int which) #include "i386/tcg-target.inc.c" /* compare a pointer @ptr and a tb_tc @s */ -static int ptr_cmp_tb_tc(const void *ptr, const struct tb_tc *s) -{ +static int ptr_cmp_tb_tc(const void *ptr, const struct tb_tc *s) { if (ptr >= s->ptr + s->size) { return 1; } else if (ptr < s->ptr) { @@ -355,8 +321,7 @@ static int ptr_cmp_tb_tc(const void *ptr, const struct tb_tc *s) return 0; } -static gint tb_tc_cmp(gconstpointer ap, gconstpointer bp) -{ +static gint tb_tc_cmp(gconstpointer ap, gconstpointer bp) { const struct tb_tc *a = ap; const struct tb_tc *b = bp; @@ -386,13 +351,11 @@ static gint tb_tc_cmp(gconstpointer ap, gconstpointer bp) return ptr_cmp_tb_tc(b->ptr, a); } -static void tcg_region_trees_init(void) -{ +static void tcg_region_trees_init(void) { size_t i; tree_size = ROUND_UP(sizeof(struct tcg_region_tree), qemu_dcache_linesize); - int ret = posix_memalign(®ion_trees, qemu_dcache_linesize, region.n * tree_size); if (ret != 0) { abort(); @@ -406,8 +369,7 @@ static void tcg_region_trees_init(void) } } -static struct tcg_region_tree *tc_ptr_to_region_tree(void *p) -{ +static struct tcg_region_tree *tc_ptr_to_region_tree(void *p) { size_t region_idx; if (p < region.start_aligned) { @@ -424,8 +386,7 @@ static struct tcg_region_tree *tc_ptr_to_region_tree(void *p) return region_trees + region_idx * tree_size; } -void tcg_tb_insert(TranslationBlock *tb) -{ +void tcg_tb_insert(TranslationBlock *tb) { struct tcg_region_tree *rt = tc_ptr_to_region_tree(tb->tc.ptr); mutex_lock(&rt->lock); @@ -433,8 +394,7 @@ void tcg_tb_insert(TranslationBlock *tb) mutex_unlock(&rt->lock); } -void tcg_tb_remove(TranslationBlock *tb) -{ +void tcg_tb_remove(TranslationBlock *tb) { struct tcg_region_tree *rt = tc_ptr_to_region_tree(tb->tc.ptr); mutex_lock(&rt->lock); @@ -447,11 +407,10 @@ void tcg_tb_remove(TranslationBlock *tb) * tb->tc.ptr <= tc_ptr < tb->tc.ptr + tb->tc.size * Return NULL if not found. */ -TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr) -{ - struct tcg_region_tree *rt = tc_ptr_to_region_tree((void *)tc_ptr); +TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr) { + struct tcg_region_tree *rt = tc_ptr_to_region_tree((void *) tc_ptr); TranslationBlock *tb; - struct tb_tc s = { .ptr = (void *)tc_ptr }; + struct tb_tc s = {.ptr = (void *) tc_ptr}; mutex_lock(&rt->lock); tb = g_tree_lookup(rt->tree, &s); @@ -459,8 +418,7 @@ TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr) return tb; } -static void tcg_region_tree_lock_all(void) -{ +static void tcg_region_tree_lock_all(void) { size_t i; for (i = 0; i < region.n; i++) { @@ -470,8 +428,7 @@ static void tcg_region_tree_lock_all(void) } } -static void tcg_region_tree_unlock_all(void) -{ +static void tcg_region_tree_unlock_all(void) { size_t i; for (i = 0; i < region.n; i++) { @@ -481,8 +438,7 @@ static void tcg_region_tree_unlock_all(void) } } -void tcg_tb_foreach(GTraverseFunc func, gpointer user_data) -{ +void tcg_tb_foreach(GTraverseFunc func, gpointer user_data) { size_t i; tcg_region_tree_lock_all(); @@ -494,8 +450,7 @@ void tcg_tb_foreach(GTraverseFunc func, gpointer user_data) tcg_region_tree_unlock_all(); } -size_t tcg_nb_tbs(void) -{ +size_t tcg_nb_tbs(void) { size_t nb_tbs = 0; size_t i; @@ -509,8 +464,7 @@ size_t tcg_nb_tbs(void) return nb_tbs; } -static void tcg_region_tree_reset_all(void) -{ +static void tcg_region_tree_reset_all(void) { size_t i; tcg_region_tree_lock_all(); @@ -524,8 +478,7 @@ static void tcg_region_tree_reset_all(void) tcg_region_tree_unlock_all(); } -static void tcg_region_bounds(size_t curr_region, void **pstart, void **pend) -{ +static void tcg_region_bounds(size_t curr_region, void **pstart, void **pend) { void *start, *end; start = region.start_aligned + curr_region * region.stride; @@ -542,8 +495,7 @@ static void tcg_region_bounds(size_t curr_region, void **pstart, void **pend) *pend = end; } -static void tcg_region_assign(TCGContext *s, size_t curr_region) -{ +static void tcg_region_assign(TCGContext *s, size_t curr_region) { void *start, *end; tcg_region_bounds(curr_region, &start, &end); @@ -554,8 +506,7 @@ static void tcg_region_assign(TCGContext *s, size_t curr_region) s->code_gen_highwater = end - TCG_HIGHWATER; } -static bool tcg_region_alloc__locked(TCGContext *s) -{ +static bool tcg_region_alloc__locked(TCGContext *s) { if (region.current == region.n) { return true; } @@ -568,8 +519,7 @@ static bool tcg_region_alloc__locked(TCGContext *s) * Request a new region once the one in use has filled up. * Returns true on error. */ -static bool tcg_region_alloc(TCGContext *s) -{ +static bool tcg_region_alloc(TCGContext *s) { bool err; /* read the region size now; alloc__locked will overwrite it on success */ size_t size_full = s->code_gen_buffer_size; @@ -587,14 +537,12 @@ static bool tcg_region_alloc(TCGContext *s) * Perform a context's first region allocation. * This function does _not_ increment region.agg_size_full. */ -static inline bool tcg_region_initial_alloc__locked(TCGContext *s) -{ +static inline bool tcg_region_initial_alloc__locked(TCGContext *s) { return tcg_region_alloc__locked(s); } /* Call from a safe-work context */ -void tcg_region_reset_all(void) -{ +void tcg_region_reset_all(void) { unsigned int n_ctxs = atomic_read(&n_tcg_ctxs); unsigned int i; @@ -614,8 +562,7 @@ void tcg_region_reset_all(void) } #ifdef CONFIG_USER_ONLY -static size_t tcg_n_regions(void) -{ +static size_t tcg_n_regions(void) { return 1; } #else @@ -625,8 +572,7 @@ static size_t tcg_n_regions(void) * reasonable size. If that's not possible we make do by evenly dividing * the code_gen_buffer among the vCPUs. */ -static size_t tcg_n_regions(void) -{ +static size_t tcg_n_regions(void) { size_t i; /* Use a single region if all we have is one vCPU thread */ @@ -679,8 +625,7 @@ static size_t tcg_n_regions(void) * in practice. Multi-threaded guests share most if not all of their translated * code, which makes parallel code generation less appealing than in softmmu. */ -void tcg_region_init(void) -{ +void tcg_region_init(void) { void *buf = tcg_init_ctx.code_gen_buffer; void *aligned; size_t size = tcg_init_ctx.code_gen_buffer_size; @@ -730,7 +675,7 @@ void tcg_region_init(void) tcg_region_trees_init(); - /* In user-mode we support only one ctx, so do the initial allocation now */ +/* In user-mode we support only one ctx, so do the initial allocation now */ #ifdef CONFIG_USER_ONLY { bool err = tcg_region_initial_alloc__locked(tcg_ctx); @@ -756,13 +701,11 @@ void tcg_region_init(void) * over the array (e.g. tcg_code_size() the same for both softmmu and user-mode. */ #ifdef CONFIG_USER_ONLY -void tcg_register_thread(void) -{ +void tcg_register_thread(void) { tcg_ctx = &tcg_init_ctx; } #else -void tcg_register_thread(void) -{ +void tcg_register_thread(void) { TCGContext *s = g_malloc(sizeof(*s)); unsigned int i, n; bool err; @@ -798,8 +741,7 @@ void tcg_register_thread(void) * Do not confuse with tcg_current_code_size(); that one applies to a single * TCG context. */ -size_t tcg_code_size(void) -{ +size_t tcg_code_size(void) { unsigned int n_ctxs = atomic_read(&n_tcg_ctxs); unsigned int i; size_t total; @@ -823,8 +765,7 @@ size_t tcg_code_size(void) * regions. * See also: tcg_code_size() */ -size_t tcg_code_capacity(void) -{ +size_t tcg_code_capacity(void) { size_t guard_size, capacity; /* no need for synchronization; these variables are set at init time */ @@ -834,8 +775,7 @@ size_t tcg_code_capacity(void) return capacity; } -size_t tcg_tb_phys_invalidate_count(void) -{ +size_t tcg_tb_phys_invalidate_count(void) { unsigned int n_ctxs = atomic_read(&n_tcg_ctxs); unsigned int i; size_t total = 0; @@ -849,11 +789,10 @@ size_t tcg_tb_phys_invalidate_count(void) } /* pool based memory allocation */ -void *tcg_malloc_internal(TCGContext *s, int size) -{ +void *tcg_malloc_internal(TCGContext *s, int size) { TCGPool *p; int pool_size; - + if (size > TCG_POOL_CHUNK_SIZE) { /* big malloc: insert a new pool (XXX: could optimize) */ p = g_malloc(sizeof(TCGPool) + size); @@ -874,7 +813,7 @@ void *tcg_malloc_internal(TCGContext *s, int size) p = g_malloc(sizeof(TCGPool) + pool_size); p->size = pool_size; p->next = NULL; - if (s->pool_current) + if (s->pool_current) s->pool_current->next = p; else s->pool_first = p; @@ -889,8 +828,7 @@ void *tcg_malloc_internal(TCGContext *s, int size) return p->data; } -void tcg_pool_reset(TCGContext *s) -{ +void tcg_pool_reset(TCGContext *s) { TCGPool *p, *t; for (p = s->pool_first_large; p; p = t) { t = p->next; @@ -917,11 +855,9 @@ static GHashTable *helper_table; static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)]; static void process_op_defs(TCGContext *s); -static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, - TCGReg reg, const char *name); +static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, TCGReg reg, const char *name); -void tcg_context_init(TCGContext *s) -{ +void tcg_context_init(TCGContext *s) { int op, total_args, n, i; TCGOpDef *def; TCGArgConstraint *args_ct; @@ -938,7 +874,7 @@ void tcg_context_init(TCGContext *s) /* Count total number of arguments and allocate the corresponding space */ total_args = 0; - for(op = 0; op < NB_OPS; op++) { + for (op = 0; op < NB_OPS; op++) { def = &tcg_op_defs[op]; n = def->nb_iargs + def->nb_oargs; total_args += n; @@ -947,7 +883,7 @@ void tcg_context_init(TCGContext *s) args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args); sorted_args = g_malloc(sizeof(int) * total_args); - for(op = 0; op < NB_OPS; op++) { + for (op = 0; op < NB_OPS; op++) { def = &tcg_op_defs[op]; def->args_ct = args_ct; def->sorted_args = sorted_args; @@ -961,8 +897,7 @@ void tcg_context_init(TCGContext *s) helper_table = g_hash_table_new(NULL, NULL); for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) { - g_hash_table_insert(helper_table, (gpointer)all_helpers[i].func, - (gpointer)&all_helpers[i]); + g_hash_table_insert(helper_table, (gpointer) all_helpers[i].func, (gpointer) &all_helpers[i]); } tcg_target_init(s); @@ -984,12 +919,12 @@ void tcg_context_init(TCGContext *s) } tcg_ctx = s; - /* - * In user-mode we simply share the init context among threads, since we - * use a single region. See the documentation tcg_region_init() for the - * reasoning behind this. - * In softmmu we will have at most max_cpus TCG threads. - */ +/* + * In user-mode we simply share the init context among threads, since we + * use a single region. See the documentation tcg_region_init() for the + * reasoning behind this. + * In softmmu we will have at most max_cpus TCG threads. + */ #ifdef CONFIG_USER_ONLY tcg_ctxs = &tcg_ctx; n_tcg_ctxs = 1; @@ -1006,15 +941,14 @@ void tcg_context_init(TCGContext *s) * Allocate TBs right before their corresponding translated code, making * sure that TBs and code are on different cache lines. */ -TranslationBlock *tcg_tb_alloc(TCGContext *s) -{ +TranslationBlock *tcg_tb_alloc(TCGContext *s) { uintptr_t align = qemu_icache_linesize; TranslationBlock *tb; void *next; - retry: - tb = (void *)ROUND_UP((uintptr_t)s->code_gen_ptr, align); - next = (void *)ROUND_UP((uintptr_t)(tb + 1), align); +retry: + tb = (void *) ROUND_UP((uintptr_t) s->code_gen_ptr, align); + next = (void *) ROUND_UP((uintptr_t)(tb + 1), align); if (unlikely(next > s->code_gen_highwater)) { if (tcg_region_alloc(s)) { @@ -1027,8 +961,7 @@ TranslationBlock *tcg_tb_alloc(TCGContext *s) return tb; } -void tcg_prologue_init(TCGContext *s) -{ +void tcg_prologue_init(TCGContext *s) { size_t prologue_size, total_size; void *buf0, *buf1; @@ -1061,7 +994,7 @@ void tcg_prologue_init(TCGContext *s) #endif buf1 = s->code_ptr; - flush_icache_range((uintptr_t)buf0, (uintptr_t)buf1); + flush_icache_range((uintptr_t) buf0, (uintptr_t) buf1); /* Deduct the prologue from the buffer. */ prologue_size = tcg_current_code_size(s); @@ -1086,13 +1019,11 @@ void tcg_prologue_init(TCGContext *s) for (i = 0; i < data_size; i += sizeof(tcg_target_ulong)) { if (sizeof(tcg_target_ulong) == 8) { - qemu_log("0x%08" PRIxPTR ": .quad 0x%016" PRIx64 "\n", - (uintptr_t)s->data_gen_ptr + i, - *(uint64_t *)(s->data_gen_ptr + i)); + qemu_log("0x%08" PRIxPTR ": .quad 0x%016" PRIx64 "\n", (uintptr_t) s->data_gen_ptr + i, + *(uint64_t *) (s->data_gen_ptr + i)); } else { - qemu_log("0x%08" PRIxPTR ": .long 0x%08x\n", - (uintptr_t)s->data_gen_ptr + i, - *(uint32_t *)(s->data_gen_ptr + i)); + qemu_log("0x%08" PRIxPTR ": .long 0x%08x\n", (uintptr_t) s->data_gen_ptr + i, + *(uint32_t *) (s->data_gen_ptr + i)); } } } else { @@ -1110,8 +1041,7 @@ void tcg_prologue_init(TCGContext *s) } } -void tcg_func_start(TCGContext *s) -{ +void tcg_func_start(TCGContext *s) { tcg_pool_reset(s); s->nb_temps = s->nb_globals; @@ -1133,15 +1063,13 @@ void tcg_func_start(TCGContext *s) #endif } -static inline TCGTemp *tcg_temp_alloc(TCGContext *s) -{ +static inline TCGTemp *tcg_temp_alloc(TCGContext *s) { int n = s->nb_temps++; tcg_debug_assert(n < TCG_MAX_TEMPS); return memset(&s->temps[n], 0, sizeof(TCGTemp)); } -static inline TCGTemp *tcg_global_alloc(TCGContext *s) -{ +static inline TCGTemp *tcg_global_alloc(TCGContext *s) { TCGTemp *ts; tcg_debug_assert(s->nb_globals == s->nb_temps); @@ -1152,9 +1080,7 @@ static inline TCGTemp *tcg_global_alloc(TCGContext *s) return ts; } -static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, - TCGReg reg, const char *name) -{ +static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, TCGReg reg, const char *name) { TCGTemp *ts; if (TCG_TARGET_REG_BITS == 32 && type != TCG_TYPE_I32) { @@ -1172,17 +1098,13 @@ static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, return ts; } -void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size) -{ +void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size) { s->frame_start = start; s->frame_end = start + size; - s->frame_temp - = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, reg, "_frame"); + s->frame_temp = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, reg, "_frame"); } -TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, - intptr_t offset, const char *name) -{ +TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, intptr_t offset, const char *name) { TCGContext *s = tcg_ctx; TCGTemp *base_ts = tcgv_ptr_temp(base); TCGTemp *ts = tcg_global_alloc(s); @@ -1195,8 +1117,7 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, /* We do not support double-indirect registers. */ tcg_debug_assert(!base_ts->indirect_reg); base_ts->indirect_base = 1; - s->nb_indirects += (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64 - ? 2 : 1); + s->nb_indirects += (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64 ? 2 : 1); indirect_reg = 1; } @@ -1236,8 +1157,7 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, return ts; } -TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local) -{ +TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local) { TCGContext *s = tcg_ctx; TCGTemp *ts; int idx, k; @@ -1281,23 +1201,22 @@ TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local) return ts; } -TCGv_vec tcg_temp_new_vec(TCGType type) -{ +TCGv_vec tcg_temp_new_vec(TCGType type) { TCGTemp *t; #ifdef CONFIG_DEBUG_TCG switch (type) { - case TCG_TYPE_V64: - assert(TCG_TARGET_HAS_v64); - break; - case TCG_TYPE_V128: - assert(TCG_TARGET_HAS_v128); - break; - case TCG_TYPE_V256: - assert(TCG_TARGET_HAS_v256); - break; - default: - g_assert_not_reached(); + case TCG_TYPE_V64: + assert(TCG_TARGET_HAS_v64); + break; + case TCG_TYPE_V128: + assert(TCG_TARGET_HAS_v128); + break; + case TCG_TYPE_V256: + assert(TCG_TARGET_HAS_v256); + break; + default: + g_assert_not_reached(); } #endif @@ -1306,8 +1225,7 @@ TCGv_vec tcg_temp_new_vec(TCGType type) } /* Create a new temp of the same type as an existing temp. */ -TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match) -{ +TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match) { TCGTemp *t = tcgv_vec_temp(match); tcg_debug_assert(t->temp_allocated != 0); @@ -1316,8 +1234,7 @@ TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match) return temp_tcgv_vec(t); } -void tcg_temp_free_internal(TCGTemp *ts) -{ +void tcg_temp_free_internal(TCGTemp *ts) { TCGContext *s = tcg_ctx; int k, idx; @@ -1337,32 +1254,28 @@ void tcg_temp_free_internal(TCGTemp *ts) set_bit(idx, s->free_temps[k].l); } -TCGv_i32 tcg_const_i32(int32_t val) -{ +TCGv_i32 tcg_const_i32(int32_t val) { TCGv_i32 t0; t0 = tcg_temp_new_i32(); tcg_gen_movi_i32(t0, val); return t0; } -TCGv_i64 tcg_const_i64(int64_t val) -{ +TCGv_i64 tcg_const_i64(int64_t val) { TCGv_i64 t0; t0 = tcg_temp_new_i64(); tcg_gen_movi_i64(t0, val); return t0; } -TCGv_i32 tcg_const_local_i32(int32_t val) -{ +TCGv_i32 tcg_const_local_i32(int32_t val) { TCGv_i32 t0; t0 = tcg_temp_local_new_i32(); tcg_gen_movi_i32(t0, val); return t0; } -TCGv_i64 tcg_const_local_i64(int64_t val) -{ +TCGv_i64 tcg_const_local_i64(int64_t val) { TCGv_i64 t0; t0 = tcg_temp_local_new_i64(); tcg_gen_movi_i64(t0, val); @@ -1370,14 +1283,12 @@ TCGv_i64 tcg_const_local_i64(int64_t val) } #if defined(CONFIG_DEBUG_TCG) -void tcg_clear_temp_count(void) -{ +void tcg_clear_temp_count(void) { TCGContext *s = tcg_ctx; s->temps_in_use = 0; } -int tcg_check_temp_count(void) -{ +int tcg_check_temp_count(void) { TCGContext *s = tcg_ctx; if (s->temps_in_use) { /* Clear the count so that we don't give another @@ -1392,293 +1303,289 @@ int tcg_check_temp_count(void) /* Return true if OP may appear in the opcode stream. Test the runtime variable that controls each opcode. */ -bool tcg_op_supported(TCGOpcode op) -{ - const bool have_vec - = TCG_TARGET_HAS_v64 | TCG_TARGET_HAS_v128 | TCG_TARGET_HAS_v256; +bool tcg_op_supported(TCGOpcode op) { + const bool have_vec = TCG_TARGET_HAS_v64 | TCG_TARGET_HAS_v128 | TCG_TARGET_HAS_v256; switch (op) { - case INDEX_op_discard: - case INDEX_op_set_label: - case INDEX_op_call: - case INDEX_op_br: - case INDEX_op_mb: - case INDEX_op_insn_start: - case INDEX_op_exit_tb: - case INDEX_op_goto_tb: - case INDEX_op_qemu_ld_i32: - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_ld_i64: - case INDEX_op_qemu_st_i64: - return true; + case INDEX_op_discard: + case INDEX_op_set_label: + case INDEX_op_call: + case INDEX_op_br: + case INDEX_op_mb: + case INDEX_op_insn_start: + case INDEX_op_exit_tb: + case INDEX_op_goto_tb: + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_st_i64: + return true; - case INDEX_op_goto_ptr: - return TCG_TARGET_HAS_goto_ptr; - - case INDEX_op_mov_i32: - case INDEX_op_movi_i32: - case INDEX_op_setcond_i32: - case INDEX_op_brcond_i32: - case INDEX_op_ld8u_i32: - case INDEX_op_ld8s_i32: - case INDEX_op_ld16u_i32: - case INDEX_op_ld16s_i32: - case INDEX_op_ld_i32: - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: - case INDEX_op_st_i32: - case INDEX_op_add_i32: - case INDEX_op_sub_i32: - case INDEX_op_mul_i32: - case INDEX_op_and_i32: - case INDEX_op_or_i32: - case INDEX_op_xor_i32: - case INDEX_op_shl_i32: - case INDEX_op_shr_i32: - case INDEX_op_sar_i32: - return true; + case INDEX_op_goto_ptr: + return TCG_TARGET_HAS_goto_ptr; - case INDEX_op_movcond_i32: - return TCG_TARGET_HAS_movcond_i32; - case INDEX_op_div_i32: - case INDEX_op_divu_i32: - return TCG_TARGET_HAS_div_i32; - case INDEX_op_rem_i32: - case INDEX_op_remu_i32: - return TCG_TARGET_HAS_rem_i32; - case INDEX_op_div2_i32: - case INDEX_op_divu2_i32: - return TCG_TARGET_HAS_div2_i32; - case INDEX_op_rotl_i32: - case INDEX_op_rotr_i32: - return TCG_TARGET_HAS_rot_i32; - case INDEX_op_deposit_i32: - return TCG_TARGET_HAS_deposit_i32; - case INDEX_op_extract_i32: - return TCG_TARGET_HAS_extract_i32; - case INDEX_op_sextract_i32: - return TCG_TARGET_HAS_sextract_i32; - case INDEX_op_add2_i32: - return TCG_TARGET_HAS_add2_i32; - case INDEX_op_sub2_i32: - return TCG_TARGET_HAS_sub2_i32; - case INDEX_op_mulu2_i32: - return TCG_TARGET_HAS_mulu2_i32; - case INDEX_op_muls2_i32: - return TCG_TARGET_HAS_muls2_i32; - case INDEX_op_muluh_i32: - return TCG_TARGET_HAS_muluh_i32; - case INDEX_op_mulsh_i32: - return TCG_TARGET_HAS_mulsh_i32; - case INDEX_op_ext8s_i32: - return TCG_TARGET_HAS_ext8s_i32; - case INDEX_op_ext16s_i32: - return TCG_TARGET_HAS_ext16s_i32; - case INDEX_op_ext8u_i32: - return TCG_TARGET_HAS_ext8u_i32; - case INDEX_op_ext16u_i32: - return TCG_TARGET_HAS_ext16u_i32; - case INDEX_op_bswap16_i32: - return TCG_TARGET_HAS_bswap16_i32; - case INDEX_op_bswap32_i32: - return TCG_TARGET_HAS_bswap32_i32; - case INDEX_op_not_i32: - return TCG_TARGET_HAS_not_i32; - case INDEX_op_neg_i32: - return TCG_TARGET_HAS_neg_i32; - case INDEX_op_andc_i32: - return TCG_TARGET_HAS_andc_i32; - case INDEX_op_orc_i32: - return TCG_TARGET_HAS_orc_i32; - case INDEX_op_eqv_i32: - return TCG_TARGET_HAS_eqv_i32; - case INDEX_op_nand_i32: - return TCG_TARGET_HAS_nand_i32; - case INDEX_op_nor_i32: - return TCG_TARGET_HAS_nor_i32; - case INDEX_op_clz_i32: - return TCG_TARGET_HAS_clz_i32; - case INDEX_op_ctz_i32: - return TCG_TARGET_HAS_ctz_i32; - case INDEX_op_ctpop_i32: - return TCG_TARGET_HAS_ctpop_i32; - - case INDEX_op_brcond2_i32: - case INDEX_op_setcond2_i32: - return TCG_TARGET_REG_BITS == 32; - - case INDEX_op_mov_i64: - case INDEX_op_movi_i64: - case INDEX_op_setcond_i64: - case INDEX_op_brcond_i64: - case INDEX_op_ld8u_i64: - case INDEX_op_ld8s_i64: - case INDEX_op_ld16u_i64: - case INDEX_op_ld16s_i64: - case INDEX_op_ld32u_i64: - case INDEX_op_ld32s_i64: - case INDEX_op_ld_i64: - case INDEX_op_st8_i64: - case INDEX_op_st16_i64: - case INDEX_op_st32_i64: - case INDEX_op_st_i64: - case INDEX_op_add_i64: - case INDEX_op_sub_i64: - case INDEX_op_mul_i64: - case INDEX_op_and_i64: - case INDEX_op_or_i64: - case INDEX_op_xor_i64: - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: - case INDEX_op_ext_i32_i64: - case INDEX_op_extu_i32_i64: - return TCG_TARGET_REG_BITS == 64; - - case INDEX_op_movcond_i64: - return TCG_TARGET_HAS_movcond_i64; - case INDEX_op_div_i64: - case INDEX_op_divu_i64: - return TCG_TARGET_HAS_div_i64; - case INDEX_op_rem_i64: - case INDEX_op_remu_i64: - return TCG_TARGET_HAS_rem_i64; - case INDEX_op_div2_i64: - case INDEX_op_divu2_i64: - return TCG_TARGET_HAS_div2_i64; - case INDEX_op_rotl_i64: - case INDEX_op_rotr_i64: - return TCG_TARGET_HAS_rot_i64; - case INDEX_op_deposit_i64: - return TCG_TARGET_HAS_deposit_i64; - case INDEX_op_extract_i64: - return TCG_TARGET_HAS_extract_i64; - case INDEX_op_sextract_i64: - return TCG_TARGET_HAS_sextract_i64; - case INDEX_op_extrl_i64_i32: - return TCG_TARGET_HAS_extrl_i64_i32; - case INDEX_op_extrh_i64_i32: - return TCG_TARGET_HAS_extrh_i64_i32; - case INDEX_op_ext8s_i64: - return TCG_TARGET_HAS_ext8s_i64; - case INDEX_op_ext16s_i64: - return TCG_TARGET_HAS_ext16s_i64; - case INDEX_op_ext32s_i64: - return TCG_TARGET_HAS_ext32s_i64; - case INDEX_op_ext8u_i64: - return TCG_TARGET_HAS_ext8u_i64; - case INDEX_op_ext16u_i64: - return TCG_TARGET_HAS_ext16u_i64; - case INDEX_op_ext32u_i64: - return TCG_TARGET_HAS_ext32u_i64; - case INDEX_op_bswap16_i64: - return TCG_TARGET_HAS_bswap16_i64; - case INDEX_op_bswap32_i64: - return TCG_TARGET_HAS_bswap32_i64; - case INDEX_op_bswap64_i64: - return TCG_TARGET_HAS_bswap64_i64; - case INDEX_op_not_i64: - return TCG_TARGET_HAS_not_i64; - case INDEX_op_neg_i64: - return TCG_TARGET_HAS_neg_i64; - case INDEX_op_andc_i64: - return TCG_TARGET_HAS_andc_i64; - case INDEX_op_orc_i64: - return TCG_TARGET_HAS_orc_i64; - case INDEX_op_eqv_i64: - return TCG_TARGET_HAS_eqv_i64; - case INDEX_op_nand_i64: - return TCG_TARGET_HAS_nand_i64; - case INDEX_op_nor_i64: - return TCG_TARGET_HAS_nor_i64; - case INDEX_op_clz_i64: - return TCG_TARGET_HAS_clz_i64; - case INDEX_op_ctz_i64: - return TCG_TARGET_HAS_ctz_i64; - case INDEX_op_ctpop_i64: - return TCG_TARGET_HAS_ctpop_i64; - case INDEX_op_add2_i64: - return TCG_TARGET_HAS_add2_i64; - case INDEX_op_sub2_i64: - return TCG_TARGET_HAS_sub2_i64; - case INDEX_op_mulu2_i64: - return TCG_TARGET_HAS_mulu2_i64; - case INDEX_op_muls2_i64: - return TCG_TARGET_HAS_muls2_i64; - case INDEX_op_muluh_i64: - return TCG_TARGET_HAS_muluh_i64; - case INDEX_op_mulsh_i64: - return TCG_TARGET_HAS_mulsh_i64; - - case INDEX_op_mov_vec: - case INDEX_op_dup_vec: - case INDEX_op_dupi_vec: - case INDEX_op_ld_vec: - case INDEX_op_st_vec: - case INDEX_op_add_vec: - case INDEX_op_sub_vec: - case INDEX_op_and_vec: - case INDEX_op_or_vec: - case INDEX_op_xor_vec: - case INDEX_op_cmp_vec: - return have_vec; - case INDEX_op_dup2_vec: - return have_vec && TCG_TARGET_REG_BITS == 32; - case INDEX_op_not_vec: - return have_vec && TCG_TARGET_HAS_not_vec; - case INDEX_op_neg_vec: - return have_vec && TCG_TARGET_HAS_neg_vec; - case INDEX_op_andc_vec: - return have_vec && TCG_TARGET_HAS_andc_vec; - case INDEX_op_orc_vec: - return have_vec && TCG_TARGET_HAS_orc_vec; - case INDEX_op_mul_vec: - return have_vec && TCG_TARGET_HAS_mul_vec; - case INDEX_op_shli_vec: - case INDEX_op_shri_vec: - case INDEX_op_sari_vec: - return have_vec && TCG_TARGET_HAS_shi_vec; - case INDEX_op_shls_vec: - case INDEX_op_shrs_vec: - case INDEX_op_sars_vec: - return have_vec && TCG_TARGET_HAS_shs_vec; - case INDEX_op_shlv_vec: - case INDEX_op_shrv_vec: - case INDEX_op_sarv_vec: - return have_vec && TCG_TARGET_HAS_shv_vec; - case INDEX_op_ssadd_vec: - case INDEX_op_usadd_vec: - case INDEX_op_sssub_vec: - case INDEX_op_ussub_vec: - return have_vec && TCG_TARGET_HAS_sat_vec; - case INDEX_op_smin_vec: - case INDEX_op_umin_vec: - case INDEX_op_smax_vec: - case INDEX_op_umax_vec: - return have_vec && TCG_TARGET_HAS_minmax_vec; - - default: - tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS); - return true; + case INDEX_op_mov_i32: + case INDEX_op_movi_i32: + case INDEX_op_setcond_i32: + case INDEX_op_brcond_i32: + case INDEX_op_ld8u_i32: + case INDEX_op_ld8s_i32: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16s_i32: + case INDEX_op_ld_i32: + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_add_i32: + case INDEX_op_sub_i32: + case INDEX_op_mul_i32: + case INDEX_op_and_i32: + case INDEX_op_or_i32: + case INDEX_op_xor_i32: + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + return true; + + case INDEX_op_movcond_i32: + return TCG_TARGET_HAS_movcond_i32; + case INDEX_op_div_i32: + case INDEX_op_divu_i32: + return TCG_TARGET_HAS_div_i32; + case INDEX_op_rem_i32: + case INDEX_op_remu_i32: + return TCG_TARGET_HAS_rem_i32; + case INDEX_op_div2_i32: + case INDEX_op_divu2_i32: + return TCG_TARGET_HAS_div2_i32; + case INDEX_op_rotl_i32: + case INDEX_op_rotr_i32: + return TCG_TARGET_HAS_rot_i32; + case INDEX_op_deposit_i32: + return TCG_TARGET_HAS_deposit_i32; + case INDEX_op_extract_i32: + return TCG_TARGET_HAS_extract_i32; + case INDEX_op_sextract_i32: + return TCG_TARGET_HAS_sextract_i32; + case INDEX_op_add2_i32: + return TCG_TARGET_HAS_add2_i32; + case INDEX_op_sub2_i32: + return TCG_TARGET_HAS_sub2_i32; + case INDEX_op_mulu2_i32: + return TCG_TARGET_HAS_mulu2_i32; + case INDEX_op_muls2_i32: + return TCG_TARGET_HAS_muls2_i32; + case INDEX_op_muluh_i32: + return TCG_TARGET_HAS_muluh_i32; + case INDEX_op_mulsh_i32: + return TCG_TARGET_HAS_mulsh_i32; + case INDEX_op_ext8s_i32: + return TCG_TARGET_HAS_ext8s_i32; + case INDEX_op_ext16s_i32: + return TCG_TARGET_HAS_ext16s_i32; + case INDEX_op_ext8u_i32: + return TCG_TARGET_HAS_ext8u_i32; + case INDEX_op_ext16u_i32: + return TCG_TARGET_HAS_ext16u_i32; + case INDEX_op_bswap16_i32: + return TCG_TARGET_HAS_bswap16_i32; + case INDEX_op_bswap32_i32: + return TCG_TARGET_HAS_bswap32_i32; + case INDEX_op_not_i32: + return TCG_TARGET_HAS_not_i32; + case INDEX_op_neg_i32: + return TCG_TARGET_HAS_neg_i32; + case INDEX_op_andc_i32: + return TCG_TARGET_HAS_andc_i32; + case INDEX_op_orc_i32: + return TCG_TARGET_HAS_orc_i32; + case INDEX_op_eqv_i32: + return TCG_TARGET_HAS_eqv_i32; + case INDEX_op_nand_i32: + return TCG_TARGET_HAS_nand_i32; + case INDEX_op_nor_i32: + return TCG_TARGET_HAS_nor_i32; + case INDEX_op_clz_i32: + return TCG_TARGET_HAS_clz_i32; + case INDEX_op_ctz_i32: + return TCG_TARGET_HAS_ctz_i32; + case INDEX_op_ctpop_i32: + return TCG_TARGET_HAS_ctpop_i32; + + case INDEX_op_brcond2_i32: + case INDEX_op_setcond2_i32: + return TCG_TARGET_REG_BITS == 32; + + case INDEX_op_mov_i64: + case INDEX_op_movi_i64: + case INDEX_op_setcond_i64: + case INDEX_op_brcond_i64: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + case INDEX_op_add_i64: + case INDEX_op_sub_i64: + case INDEX_op_mul_i64: + case INDEX_op_and_i64: + case INDEX_op_or_i64: + case INDEX_op_xor_i64: + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + return TCG_TARGET_REG_BITS == 64; + + case INDEX_op_movcond_i64: + return TCG_TARGET_HAS_movcond_i64; + case INDEX_op_div_i64: + case INDEX_op_divu_i64: + return TCG_TARGET_HAS_div_i64; + case INDEX_op_rem_i64: + case INDEX_op_remu_i64: + return TCG_TARGET_HAS_rem_i64; + case INDEX_op_div2_i64: + case INDEX_op_divu2_i64: + return TCG_TARGET_HAS_div2_i64; + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i64: + return TCG_TARGET_HAS_rot_i64; + case INDEX_op_deposit_i64: + return TCG_TARGET_HAS_deposit_i64; + case INDEX_op_extract_i64: + return TCG_TARGET_HAS_extract_i64; + case INDEX_op_sextract_i64: + return TCG_TARGET_HAS_sextract_i64; + case INDEX_op_extrl_i64_i32: + return TCG_TARGET_HAS_extrl_i64_i32; + case INDEX_op_extrh_i64_i32: + return TCG_TARGET_HAS_extrh_i64_i32; + case INDEX_op_ext8s_i64: + return TCG_TARGET_HAS_ext8s_i64; + case INDEX_op_ext16s_i64: + return TCG_TARGET_HAS_ext16s_i64; + case INDEX_op_ext32s_i64: + return TCG_TARGET_HAS_ext32s_i64; + case INDEX_op_ext8u_i64: + return TCG_TARGET_HAS_ext8u_i64; + case INDEX_op_ext16u_i64: + return TCG_TARGET_HAS_ext16u_i64; + case INDEX_op_ext32u_i64: + return TCG_TARGET_HAS_ext32u_i64; + case INDEX_op_bswap16_i64: + return TCG_TARGET_HAS_bswap16_i64; + case INDEX_op_bswap32_i64: + return TCG_TARGET_HAS_bswap32_i64; + case INDEX_op_bswap64_i64: + return TCG_TARGET_HAS_bswap64_i64; + case INDEX_op_not_i64: + return TCG_TARGET_HAS_not_i64; + case INDEX_op_neg_i64: + return TCG_TARGET_HAS_neg_i64; + case INDEX_op_andc_i64: + return TCG_TARGET_HAS_andc_i64; + case INDEX_op_orc_i64: + return TCG_TARGET_HAS_orc_i64; + case INDEX_op_eqv_i64: + return TCG_TARGET_HAS_eqv_i64; + case INDEX_op_nand_i64: + return TCG_TARGET_HAS_nand_i64; + case INDEX_op_nor_i64: + return TCG_TARGET_HAS_nor_i64; + case INDEX_op_clz_i64: + return TCG_TARGET_HAS_clz_i64; + case INDEX_op_ctz_i64: + return TCG_TARGET_HAS_ctz_i64; + case INDEX_op_ctpop_i64: + return TCG_TARGET_HAS_ctpop_i64; + case INDEX_op_add2_i64: + return TCG_TARGET_HAS_add2_i64; + case INDEX_op_sub2_i64: + return TCG_TARGET_HAS_sub2_i64; + case INDEX_op_mulu2_i64: + return TCG_TARGET_HAS_mulu2_i64; + case INDEX_op_muls2_i64: + return TCG_TARGET_HAS_muls2_i64; + case INDEX_op_muluh_i64: + return TCG_TARGET_HAS_muluh_i64; + case INDEX_op_mulsh_i64: + return TCG_TARGET_HAS_mulsh_i64; + + case INDEX_op_mov_vec: + case INDEX_op_dup_vec: + case INDEX_op_dupi_vec: + case INDEX_op_ld_vec: + case INDEX_op_st_vec: + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + case INDEX_op_cmp_vec: + return have_vec; + case INDEX_op_dup2_vec: + return have_vec && TCG_TARGET_REG_BITS == 32; + case INDEX_op_not_vec: + return have_vec && TCG_TARGET_HAS_not_vec; + case INDEX_op_neg_vec: + return have_vec && TCG_TARGET_HAS_neg_vec; + case INDEX_op_andc_vec: + return have_vec && TCG_TARGET_HAS_andc_vec; + case INDEX_op_orc_vec: + return have_vec && TCG_TARGET_HAS_orc_vec; + case INDEX_op_mul_vec: + return have_vec && TCG_TARGET_HAS_mul_vec; + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: + case INDEX_op_sari_vec: + return have_vec && TCG_TARGET_HAS_shi_vec; + case INDEX_op_shls_vec: + case INDEX_op_shrs_vec: + case INDEX_op_sars_vec: + return have_vec && TCG_TARGET_HAS_shs_vec; + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: + return have_vec && TCG_TARGET_HAS_shv_vec; + case INDEX_op_ssadd_vec: + case INDEX_op_usadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_ussub_vec: + return have_vec && TCG_TARGET_HAS_sat_vec; + case INDEX_op_smin_vec: + case INDEX_op_umin_vec: + case INDEX_op_smax_vec: + case INDEX_op_umax_vec: + return have_vec && TCG_TARGET_HAS_minmax_vec; + + default: + tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS); + return true; } } /* Note: we convert the 64 bit args to 32 bit and do some alignment and endian swap. Maybe it would be better to do the alignment and endian swap in tcg_reg_alloc_call(). */ -void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) -{ +void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) { int i, real_args, nb_rets, pi; unsigned sizemask, flags; TCGHelperInfo *info; TCGOp *op; - info = g_hash_table_lookup(helper_table, (gpointer)func); + info = g_hash_table_lookup(helper_table, (gpointer) func); flags = info->flags; sizemask = info->sizemask; -#if defined(__sparc__) && !defined(__arch64__) \ - && !defined(CONFIG_TCG_INTERPRETER) +#if defined(__sparc__) && !defined(__arch64__) && !defined(CONFIG_TCG_INTERPRETER) /* We have 64-bit values in one register, but need to pass as two separate parameters. Split them. */ int orig_sizemask = sizemask; @@ -1690,7 +1597,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) reth = NULL; if (sizemask != 0) { for (i = real_args = 0; i < nargs; ++i) { - int is_64bit = sizemask & (1 << (i+1)*2); + int is_64bit = sizemask & (1 << (i + 1) * 2); if (is_64bit) { TCGv_i64 orig = temp_tcgv_i64(args[i]); TCGv_i32 h = tcg_temp_new_i32(); @@ -1708,8 +1615,8 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) } #elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64 for (i = 0; i < nargs; ++i) { - int is_64bit = sizemask & (1 << (i+1)*2); - int is_signed = sizemask & (2 << (i+1)*2); + int is_64bit = sizemask & (1 << (i + 1) * 2); + int is_signed = sizemask & (2 << (i + 1) * 2); if (!is_64bit) { TCGv_i64 temp = tcg_temp_new_i64(); TCGv_i64 orig = temp_tcgv_i64(args[i]); @@ -1727,8 +1634,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) pi = 0; if (ret != NULL) { -#if defined(__sparc__) && !defined(__arch64__) \ - && !defined(CONFIG_TCG_INTERPRETER) +#if defined(__sparc__) && !defined(__arch64__) && !defined(CONFIG_TCG_INTERPRETER) if (orig_sizemask & 1) { /* The 32-bit ABI is going to return the 64-bit value in the %o0/%o1 register pair. Prepare for this by using @@ -1764,7 +1670,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) real_args = 0; for (i = 0; i < nargs; i++) { - int is_64bit = sizemask & (1 << (i+1)*2); + int is_64bit = sizemask & (1 << (i + 1) * 2); if (TCG_TARGET_REG_BITS < 64 && is_64bit) { #ifdef TCG_TARGET_CALL_ALIGN_ARGS /* some targets want aligned 64 bit args */ @@ -1773,16 +1679,16 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) real_args++; } #endif - /* If stack grows up, then we will be placing successive - arguments at lower addresses, which means we need to - reverse the order compared to how we would normally - treat either big or little-endian. For those arguments - that will wind up in registers, this still works for - HPPA (the only current STACK_GROWSUP target) since the - argument registers are *also* allocated in decreasing - order. If another such target is added, this logic may - have to get more complicated to differentiate between - stack arguments and register arguments. */ +/* If stack grows up, then we will be placing successive + arguments at lower addresses, which means we need to + reverse the order compared to how we would normally + treat either big or little-endian. For those arguments + that will wind up in registers, this still works for + HPPA (the only current STACK_GROWSUP target) since the + argument registers are *also* allocated in decreasing + order. If another such target is added, this logic may + have to get more complicated to differentiate between + stack arguments and register arguments. */ #if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP) op->args[pi++] = temp_arg(args[i] + 1); op->args[pi++] = temp_arg(args[i]); @@ -1797,7 +1703,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) op->args[pi++] = temp_arg(args[i]); real_args++; } - op->args[pi++] = (uintptr_t)func; + op->args[pi++] = (uintptr_t) func; op->args[pi++] = flags; TCGOP_CALLI(op) = real_args; @@ -1805,11 +1711,10 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) tcg_debug_assert(TCGOP_CALLI(op) == real_args); tcg_debug_assert(pi <= ARRAY_SIZE(op->args)); -#if defined(__sparc__) && !defined(__arch64__) \ - && !defined(CONFIG_TCG_INTERPRETER) +#if defined(__sparc__) && !defined(__arch64__) && !defined(CONFIG_TCG_INTERPRETER) /* Free all of the parts we allocated above. */ for (i = real_args = 0; i < orig_nargs; ++i) { - int is_64bit = orig_sizemask & (1 << (i+1)*2); + int is_64bit = orig_sizemask & (1 << (i + 1) * 2); if (is_64bit) { tcg_temp_free_internal(args[real_args++]); tcg_temp_free_internal(args[real_args++]); @@ -1827,7 +1732,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) } #elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64 for (i = 0; i < nargs; ++i) { - int is_64bit = sizemask & (1 << (i+1)*2); + int is_64bit = sizemask & (1 << (i + 1) * 2); if (!is_64bit) { tcg_temp_free_internal(args[i]); } @@ -1835,8 +1740,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) #endif /* TCG_TARGET_EXTEND_ARGS */ } -static void tcg_reg_alloc_start(TCGContext *s) -{ +static void tcg_reg_alloc_start(TCGContext *s) { int i, n; TCGTemp *ts; @@ -1854,9 +1758,7 @@ static void tcg_reg_alloc_start(TCGContext *s) memset(s->reg_to_temp, 0, sizeof(s->reg_to_temp)); } -static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size, - TCGTemp *ts) -{ +static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size, TCGTemp *ts) { int idx = temp_idx(ts); if (ts->temp_global) { @@ -1869,18 +1771,15 @@ static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size, return buf; } -static char *tcg_get_arg_str(TCGContext *s, char *buf, - int buf_size, TCGArg arg) -{ +static char *tcg_get_arg_str(TCGContext *s, char *buf, int buf_size, TCGArg arg) { return tcg_get_arg_str_ptr(s, buf, buf_size, arg_temp(arg)); } /* Find helper name. */ -static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val) -{ +static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val) { const char *ret = NULL; if (helper_table) { - TCGHelperInfo *info = g_hash_table_lookup(helper_table, (gpointer)val); + TCGHelperInfo *info = g_hash_table_lookup(helper_table, (gpointer) val); if (info) { ret = info->name; } @@ -1888,61 +1787,35 @@ static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val) return ret; } -static const char * const cond_name[] = -{ - [TCG_COND_NEVER] = "never", - [TCG_COND_ALWAYS] = "always", - [TCG_COND_EQ] = "eq", - [TCG_COND_NE] = "ne", - [TCG_COND_LT] = "lt", - [TCG_COND_GE] = "ge", - [TCG_COND_LE] = "le", - [TCG_COND_GT] = "gt", - [TCG_COND_LTU] = "ltu", - [TCG_COND_GEU] = "geu", - [TCG_COND_LEU] = "leu", - [TCG_COND_GTU] = "gtu" -}; - -static const char * const ldst_name[] = -{ - [MO_UB] = "ub", - [MO_SB] = "sb", - [MO_LEUW] = "leuw", - [MO_LESW] = "lesw", - [MO_LEUL] = "leul", - [MO_LESL] = "lesl", - [MO_LEQ] = "leq", - [MO_BEUW] = "beuw", - [MO_BESW] = "besw", - [MO_BEUL] = "beul", - [MO_BESL] = "besl", - [MO_BEQ] = "beq", +static const char *const cond_name[] = {[TCG_COND_NEVER] = "never", [TCG_COND_ALWAYS] = "always", + [TCG_COND_EQ] = "eq", [TCG_COND_NE] = "ne", + [TCG_COND_LT] = "lt", [TCG_COND_GE] = "ge", + [TCG_COND_LE] = "le", [TCG_COND_GT] = "gt", + [TCG_COND_LTU] = "ltu", [TCG_COND_GEU] = "geu", + [TCG_COND_LEU] = "leu", [TCG_COND_GTU] = "gtu"}; + +static const char *const ldst_name[] = { + [MO_UB] = "ub", [MO_SB] = "sb", [MO_LEUW] = "leuw", [MO_LESW] = "lesw", + [MO_LEUL] = "leul", [MO_LESL] = "lesl", [MO_LEQ] = "leq", [MO_BEUW] = "beuw", + [MO_BESW] = "besw", [MO_BEUL] = "beul", [MO_BESL] = "besl", [MO_BEQ] = "beq", }; -static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] = { +static const char *const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] = { #ifdef ALIGNED_ONLY - [MO_UNALN >> MO_ASHIFT] = "un+", - [MO_ALIGN >> MO_ASHIFT] = "", + [MO_UNALN >> MO_ASHIFT] = "un+", [MO_ALIGN >> MO_ASHIFT] = "", #else - [MO_UNALN >> MO_ASHIFT] = "", - [MO_ALIGN >> MO_ASHIFT] = "al+", + [MO_UNALN >> MO_ASHIFT] = "", [MO_ALIGN >> MO_ASHIFT] = "al+", #endif - [MO_ALIGN_2 >> MO_ASHIFT] = "al2+", - [MO_ALIGN_4 >> MO_ASHIFT] = "al4+", - [MO_ALIGN_8 >> MO_ASHIFT] = "al8+", - [MO_ALIGN_16 >> MO_ASHIFT] = "al16+", - [MO_ALIGN_32 >> MO_ASHIFT] = "al32+", - [MO_ALIGN_64 >> MO_ASHIFT] = "al64+", + [MO_ALIGN_2 >> MO_ASHIFT] = "al2+", [MO_ALIGN_4 >> MO_ASHIFT] = "al4+", + [MO_ALIGN_8 >> MO_ASHIFT] = "al8+", [MO_ALIGN_16 >> MO_ASHIFT] = "al16+", + [MO_ALIGN_32 >> MO_ASHIFT] = "al32+", [MO_ALIGN_64 >> MO_ASHIFT] = "al64+", }; -static inline bool tcg_regset_single(TCGRegSet d) -{ +static inline bool tcg_regset_single(TCGRegSet d) { return (d & (d - 1)) == 0; } -static inline TCGReg tcg_regset_first(TCGRegSet d) -{ +static inline TCGReg tcg_regset_first(TCGRegSet d) { if (TCG_TARGET_NB_REGS <= 32) { return ctz32(d); } else { @@ -1950,12 +1823,11 @@ static inline TCGReg tcg_regset_first(TCGRegSet d) } } -void tcg_dump_ops(TCGContext *s, bool have_prefs) -{ +void tcg_dump_ops(TCGContext *s, bool have_prefs) { char buf[128]; TCGOp *op; - QTAILQ_FOREACH(op, &s->ops, link) { + QTAILQ_FOREACH (op, &s->ops, link) { int i, k, nb_oargs, nb_iargs, nb_cargs; const TCGOpDef *def; TCGOpcode c; @@ -1984,12 +1856,11 @@ void tcg_dump_ops(TCGContext *s, bool have_prefs) nb_cargs = def->nb_cargs; /* function name, flags, out args */ - col += qemu_log(" %s %s,$0x%" TCG_PRIlx ",$%d", def->name, - tcg_find_helper(s, op->args[nb_oargs + nb_iargs]), - op->args[nb_oargs + nb_iargs + 1], nb_oargs); + col += + qemu_log(" %s %s,$0x%" TCG_PRIlx ",$%d", def->name, tcg_find_helper(s, op->args[nb_oargs + nb_iargs]), + op->args[nb_oargs + nb_iargs + 1], nb_oargs); for (i = 0; i < nb_oargs; i++) { - col += qemu_log(",%s", tcg_get_arg_str(s, buf, sizeof(buf), - op->args[i])); + col += qemu_log(",%s", tcg_get_arg_str(s, buf, sizeof(buf), op->args[i])); } for (i = 0; i < nb_iargs; i++) { TCGArg arg = op->args[nb_oargs + i]; @@ -2007,8 +1878,7 @@ void tcg_dump_ops(TCGContext *s, bool have_prefs) nb_cargs = def->nb_cargs; if (def->flags & TCG_OPF_VECTOR) { - col += qemu_log("v%d,e%d,", 64 << TCGOP_VECL(op), - 8 << TCGOP_VECE(op)); + col += qemu_log("v%d,e%d,", 64 << TCGOP_VECL(op), 8 << TCGOP_VECE(op)); } k = 0; @@ -2016,39 +1886,35 @@ void tcg_dump_ops(TCGContext *s, bool have_prefs) if (k != 0) { col += qemu_log(","); } - col += qemu_log("%s", tcg_get_arg_str(s, buf, sizeof(buf), - op->args[k++])); + col += qemu_log("%s", tcg_get_arg_str(s, buf, sizeof(buf), op->args[k++])); } for (i = 0; i < nb_iargs; i++) { if (k != 0) { col += qemu_log(","); } - col += qemu_log("%s", tcg_get_arg_str(s, buf, sizeof(buf), - op->args[k++])); + col += qemu_log("%s", tcg_get_arg_str(s, buf, sizeof(buf), op->args[k++])); } switch (c) { - case INDEX_op_brcond_i32: - case INDEX_op_setcond_i32: - case INDEX_op_movcond_i32: - case INDEX_op_brcond2_i32: - case INDEX_op_setcond2_i32: - case INDEX_op_brcond_i64: - case INDEX_op_setcond_i64: - case INDEX_op_movcond_i64: - case INDEX_op_cmp_vec: - if (op->args[k] < ARRAY_SIZE(cond_name) - && cond_name[op->args[k]]) { - col += qemu_log(",%s", cond_name[op->args[k++]]); - } else { - col += qemu_log(",$0x%" TCG_PRIlx, op->args[k++]); - } - i = 1; - break; - case INDEX_op_qemu_ld_i32: - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_ld_i64: - case INDEX_op_qemu_st_i64: - { + case INDEX_op_brcond_i32: + case INDEX_op_setcond_i32: + case INDEX_op_movcond_i32: + case INDEX_op_brcond2_i32: + case INDEX_op_setcond2_i32: + case INDEX_op_brcond_i64: + case INDEX_op_setcond_i64: + case INDEX_op_movcond_i64: + case INDEX_op_cmp_vec: + if (op->args[k] < ARRAY_SIZE(cond_name) && cond_name[op->args[k]]) { + col += qemu_log(",%s", cond_name[op->args[k++]]); + } else { + col += qemu_log(",$0x%" TCG_PRIlx, op->args[k++]); + } + i = 1; + break; + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_st_i64: { TCGMemOpIdx oi = op->args[k++]; TCGMemOp op = get_memop(oi); unsigned ix = get_mmuidx(oi); @@ -2062,24 +1928,22 @@ void tcg_dump_ops(TCGContext *s, bool have_prefs) col += qemu_log(",%s%s,%u", s_al, s_op, ix); } i = 1; - } - break; - default: - i = 0; - break; + } break; + default: + i = 0; + break; } switch (c) { - case INDEX_op_set_label: - case INDEX_op_br: - case INDEX_op_brcond_i32: - case INDEX_op_brcond_i64: - case INDEX_op_brcond2_i32: - col += qemu_log("%s$L%d", k ? "," : "", - arg_label(op->args[k])->id); - i++, k++; - break; - default: - break; + case INDEX_op_set_label: + case INDEX_op_br: + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + case INDEX_op_brcond2_i32: + col += qemu_log("%s$L%d", k ? "," : "", arg_label(op->args[k])->id); + i++, k++; + break; + default: + break; } for (; i < nb_cargs; i++, k++) { col += qemu_log("%s$0x%" TCG_PRIlx, k ? "," : "", op->args[k]); @@ -2133,9 +1997,9 @@ void tcg_dump_ops(TCGContext *s, bool have_prefs) qemu_log("%s", tcg_target_reg_names[reg]); #endif } else if (TCG_TARGET_NB_REGS <= 32) { - qemu_log("%#x", (uint32_t)set); + qemu_log("%#x", (uint32_t) set); } else { - qemu_log("%#" PRIx64, (uint64_t)set); + qemu_log("%#" PRIx64, (uint64_t) set); } } } @@ -2145,8 +2009,7 @@ void tcg_dump_ops(TCGContext *s, bool have_prefs) } /* we give more priority to constraints with less registers */ -static int get_constraint_priority(const TCGOpDef *def, int k) -{ +static int get_constraint_priority(const TCGOpDef *def, int k) { const TCGArgConstraint *arg_ct; int i, n; @@ -2158,7 +2021,7 @@ static int get_constraint_priority(const TCGOpDef *def, int k) if (!(arg_ct->ct & TCG_CT_REG)) return 0; n = 0; - for(i = 0; i < TCG_TARGET_NB_REGS; i++) { + for (i = 0; i < TCG_TARGET_NB_REGS; i++) { if (tcg_regset_test_reg(arg_ct->u.regs, i)) n++; } @@ -2167,16 +2030,15 @@ static int get_constraint_priority(const TCGOpDef *def, int k) } /* sort from highest priority to lowest */ -static void sort_constraints(TCGOpDef *def, int start, int n) -{ +static void sort_constraints(TCGOpDef *def, int start, int n) { int i, j, p1, p2, tmp; - for(i = 0; i < n; i++) + for (i = 0; i < n; i++) def->sorted_args[start + i] = start + i; if (n <= 1) return; - for(i = 0; i < n - 1; i++) { - for(j = i + 1; j < n; j++) { + for (i = 0; i < n - 1; i++) { + for (j = i + 1; j < n; j++) { p1 = get_constraint_priority(def, def->sorted_args[start + i]); p2 = get_constraint_priority(def, def->sorted_args[start + j]); if (p1 < p2) { @@ -2188,8 +2050,7 @@ static void sort_constraints(TCGOpDef *def, int start, int n) } } -static void process_op_defs(TCGContext *s) -{ +static void process_op_defs(TCGContext *s) { TCGOpcode op; for (op = 0; op < NB_OPS; op++) { @@ -2220,9 +2081,8 @@ static void process_op_defs(TCGContext *s) def->args_ct[i].u.regs = 0; def->args_ct[i].ct = 0; while (*ct_str != '\0') { - switch(*ct_str) { - case '0' ... '9': - { + switch (*ct_str) { + case '0' ... '9': { int oarg = *ct_str - '0'; tcg_debug_assert(ct_str == tdefs->args_ct_str[i]); tcg_debug_assert(oarg < def->nb_oargs); @@ -2235,21 +2095,20 @@ static void process_op_defs(TCGContext *s) def->args_ct[i].ct |= TCG_CT_IALIAS; def->args_ct[i].alias_index = oarg; } - ct_str++; - break; - case '&': - def->args_ct[i].ct |= TCG_CT_NEWREG; - ct_str++; - break; - case 'i': - def->args_ct[i].ct |= TCG_CT_CONST; - ct_str++; - break; - default: - ct_str = target_parse_constraint(&def->args_ct[i], - ct_str, type); - /* Typo in TCGTargetOpDef constraint. */ - tcg_debug_assert(ct_str != NULL); + ct_str++; + break; + case '&': + def->args_ct[i].ct |= TCG_CT_NEWREG; + ct_str++; + break; + case 'i': + def->args_ct[i].ct |= TCG_CT_CONST; + ct_str++; + break; + default: + ct_str = target_parse_constraint(&def->args_ct[i], ct_str, type); + /* Typo in TCGTargetOpDef constraint. */ + tcg_debug_assert(ct_str != NULL); } } } @@ -2263,26 +2122,25 @@ static void process_op_defs(TCGContext *s) } } -void tcg_op_remove(TCGContext *s, TCGOp *op) -{ +void tcg_op_remove(TCGContext *s, TCGOp *op) { TCGLabel *label; switch (op->opc) { - case INDEX_op_br: - label = arg_label(op->args[0]); - label->refs--; - break; - case INDEX_op_brcond_i32: - case INDEX_op_brcond_i64: - label = arg_label(op->args[3]); - label->refs--; - break; - case INDEX_op_brcond2_i32: - label = arg_label(op->args[5]); - label->refs--; - break; - default: - break; + case INDEX_op_br: + label = arg_label(op->args[0]); + label->refs--; + break; + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + label = arg_label(op->args[3]); + label->refs--; + break; + case INDEX_op_brcond2_i32: + label = arg_label(op->args[5]); + label->refs--; + break; + default: + break; } QTAILQ_REMOVE(&s->ops, op, link); @@ -2294,8 +2152,7 @@ void tcg_op_remove(TCGContext *s, TCGOp *op) #endif } -static TCGOp *tcg_op_alloc(TCGOpcode opc) -{ +static TCGOp *tcg_op_alloc(TCGOpcode opc) { TCGContext *s = tcg_ctx; TCGOp *op; @@ -2312,30 +2169,26 @@ static TCGOp *tcg_op_alloc(TCGOpcode opc) return op; } -TCGOp *tcg_emit_op(TCGOpcode opc) -{ +TCGOp *tcg_emit_op(TCGOpcode opc) { TCGOp *op = tcg_op_alloc(opc); QTAILQ_INSERT_TAIL(&tcg_ctx->ops, op, link); return op; } -TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *old_op, TCGOpcode opc) -{ +TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *old_op, TCGOpcode opc) { TCGOp *new_op = tcg_op_alloc(opc); QTAILQ_INSERT_BEFORE(old_op, new_op, link); return new_op; } -TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old_op, TCGOpcode opc) -{ +TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old_op, TCGOpcode opc) { TCGOp *new_op = tcg_op_alloc(opc); QTAILQ_INSERT_AFTER(&s->ops, old_op, new_op, link); return new_op; } /* Reachable analysis : remove unreachable code. */ -static void reachable_code_pass(TCGContext *s) -{ +static void reachable_code_pass(TCGContext *s) { TCGOp *op, *op_next; bool dead = false; @@ -2345,61 +2198,60 @@ static void reachable_code_pass(TCGContext *s) int call_flags; switch (op->opc) { - case INDEX_op_set_label: - label = arg_label(op->args[0]); - if (label->refs == 0) { - /* - * While there is an occasional backward branch, virtually - * all branches generated by the translators are forward. - * Which means that generally we will have already removed - * all references to the label that will be, and there is - * little to be gained by iterating. - */ - remove = true; - } else { - /* Once we see a label, insns become live again. */ - dead = false; - remove = false; - - /* - * Optimization can fold conditional branches to unconditional. - * If we find a label with one reference which is preceded by - * an unconditional branch to it, remove both. This needed to - * wait until the dead code in between them was removed. - */ - if (label->refs == 1) { - TCGOp *op_prev = QTAILQ_PREV(op, link); - if (op_prev->opc == INDEX_op_br && - label == arg_label(op_prev->args[0])) { - tcg_op_remove(s, op_prev); - remove = true; + case INDEX_op_set_label: + label = arg_label(op->args[0]); + if (label->refs == 0) { + /* + * While there is an occasional backward branch, virtually + * all branches generated by the translators are forward. + * Which means that generally we will have already removed + * all references to the label that will be, and there is + * little to be gained by iterating. + */ + remove = true; + } else { + /* Once we see a label, insns become live again. */ + dead = false; + remove = false; + + /* + * Optimization can fold conditional branches to unconditional. + * If we find a label with one reference which is preceded by + * an unconditional branch to it, remove both. This needed to + * wait until the dead code in between them was removed. + */ + if (label->refs == 1) { + TCGOp *op_prev = QTAILQ_PREV(op, link); + if (op_prev->opc == INDEX_op_br && label == arg_label(op_prev->args[0])) { + tcg_op_remove(s, op_prev); + remove = true; + } } } - } - break; - - case INDEX_op_br: - case INDEX_op_exit_tb: - case INDEX_op_goto_ptr: - /* Unconditional branches; everything following is dead. */ - dead = true; - break; + break; - case INDEX_op_call: - /* Notice noreturn helper calls, raising exceptions. */ - call_flags = op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op) + 1]; - if (call_flags & TCG_CALL_NO_RETURN) { + case INDEX_op_br: + case INDEX_op_exit_tb: + case INDEX_op_goto_ptr: + /* Unconditional branches; everything following is dead. */ dead = true; - } - break; + break; - case INDEX_op_insn_start: - /* Never remove -- we need to keep these for unwind. */ - remove = false; - break; + case INDEX_op_call: + /* Notice noreturn helper calls, raising exceptions. */ + call_flags = op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op) + 1]; + if (call_flags & TCG_CALL_NO_RETURN) { + dead = true; + } + break; - default: - break; + case INDEX_op_insn_start: + /* Never remove -- we need to keep these for unwind. */ + remove = false; + break; + + default: + break; } if (remove) { @@ -2408,31 +2260,27 @@ static void reachable_code_pass(TCGContext *s) } } -#define TS_DEAD 1 -#define TS_MEM 2 +#define TS_DEAD 1 +#define TS_MEM 2 -#define IS_DEAD_ARG(n) (arg_life & (DEAD_ARG << (n))) +#define IS_DEAD_ARG(n) (arg_life & (DEAD_ARG << (n))) #define NEED_SYNC_ARG(n) (arg_life & (SYNC_ARG << (n))) /* For liveness_pass_1, the register preferences for a given temp. */ -static inline TCGRegSet *la_temp_pref(TCGTemp *ts) -{ +static inline TCGRegSet *la_temp_pref(TCGTemp *ts) { return ts->state_ptr; } /* For liveness_pass_1, reset the preferences for a given temp to the * maximal regset for its type. */ -static inline void la_reset_pref(TCGTemp *ts) -{ - *la_temp_pref(ts) - = (ts->state == TS_DEAD ? 0 : tcg_target_available_regs[ts->type]); +static inline void la_reset_pref(TCGTemp *ts) { + *la_temp_pref(ts) = (ts->state == TS_DEAD ? 0 : tcg_target_available_regs[ts->type]); } /* liveness analysis: end of function: all temps are dead, and globals should be in memory. */ -static void la_func_end(TCGContext *s, int ng, int nt) -{ +static void la_func_end(TCGContext *s, int ng, int nt) { int i; for (i = 0; i < ng; ++i) { @@ -2447,8 +2295,7 @@ static void la_func_end(TCGContext *s, int ng, int nt) /* liveness analysis: end of basic block: all temps are dead, globals and local temps should be in memory. */ -static void la_bb_end(TCGContext *s, int ng, int nt) -{ +static void la_bb_end(TCGContext *s, int ng, int nt) { int i; for (i = 0; i < ng; ++i) { @@ -2456,16 +2303,13 @@ static void la_bb_end(TCGContext *s, int ng, int nt) la_reset_pref(&s->temps[i]); } for (i = ng; i < nt; ++i) { - s->temps[i].state = (s->temps[i].temp_local - ? TS_DEAD | TS_MEM - : TS_DEAD); + s->temps[i].state = (s->temps[i].temp_local ? TS_DEAD | TS_MEM : TS_DEAD); la_reset_pref(&s->temps[i]); } } /* liveness analysis: sync globals back to memory. */ -static void la_global_sync(TCGContext *s, int ng) -{ +static void la_global_sync(TCGContext *s, int ng) { int i; for (i = 0; i < ng; ++i) { @@ -2479,8 +2323,7 @@ static void la_global_sync(TCGContext *s, int ng) } /* liveness analysis: sync globals back to memory and kill. */ -static void la_global_kill(TCGContext *s, int ng) -{ +static void la_global_kill(TCGContext *s, int ng) { int i; for (i = 0; i < ng; i++) { @@ -2490,8 +2333,7 @@ static void la_global_kill(TCGContext *s, int ng) } /* liveness analysis: note live globals crossing calls. */ -static void la_cross_call(TCGContext *s, int nt) -{ +static void la_cross_call(TCGContext *s, int nt) { TCGRegSet mask = ~tcg_target_call_clobber_regs; int i; @@ -2514,8 +2356,7 @@ static void la_cross_call(TCGContext *s, int nt) /* Liveness analysis : update the opc_arg_life array to tell if a given input arguments is dead. Instructions updating dead temporaries are removed. */ -static void liveness_pass_1(TCGContext *s) -{ +static void liveness_pass_1(TCGContext *s) { int nb_globals = s->nb_globals; int nb_temps = s->nb_temps; TCGOp *op, *op_prev; @@ -2540,8 +2381,7 @@ static void liveness_pass_1(TCGContext *s) const TCGOpDef *def = &tcg_op_defs[opc]; switch (opc) { - case INDEX_op_call: - { + case INDEX_op_call: { int call_flags; int nb_call_regs; @@ -2577,8 +2417,7 @@ static void liveness_pass_1(TCGContext *s) op->output_pref[i] = 0; } - if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS | - TCG_CALL_NO_READ_GLOBALS))) { + if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS | TCG_CALL_NO_READ_GLOBALS))) { la_global_kill(s, nb_globals); } else if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) { la_global_sync(s, nb_globals); @@ -2606,9 +2445,7 @@ static void liveness_pass_1(TCGContext *s) * to be filled in below. For args that will be on * the stack, reset to any available reg. */ - *la_temp_pref(ts) - = (i < nb_call_regs ? 0 : - tcg_target_available_regs[ts->type]); + *la_temp_pref(ts) = (i < nb_call_regs ? 0 : tcg_target_available_regs[ts->type]); ts->state &= ~TS_DEAD; } } @@ -2618,213 +2455,209 @@ static void liveness_pass_1(TCGContext *s) for (i = 0; i < MIN(nb_call_regs, nb_iargs); i++) { ts = arg_temp(op->args[i + nb_oargs]); if (ts) { - tcg_regset_set_reg(*la_temp_pref(ts), - tcg_target_call_iarg_regs[i]); + tcg_regset_set_reg(*la_temp_pref(ts), tcg_target_call_iarg_regs[i]); } } - } - break; - case INDEX_op_insn_start: - break; - case INDEX_op_discard: - /* mark the temporary as dead */ - ts = arg_temp(op->args[0]); - ts->state = TS_DEAD; - la_reset_pref(ts); - break; + } break; + case INDEX_op_insn_start: + break; + case INDEX_op_discard: + /* mark the temporary as dead */ + ts = arg_temp(op->args[0]); + ts->state = TS_DEAD; + la_reset_pref(ts); + break; - case INDEX_op_add2_i32: - opc_new = INDEX_op_add_i32; - goto do_addsub2; - case INDEX_op_sub2_i32: - opc_new = INDEX_op_sub_i32; - goto do_addsub2; - case INDEX_op_add2_i64: - opc_new = INDEX_op_add_i64; - goto do_addsub2; - case INDEX_op_sub2_i64: - opc_new = INDEX_op_sub_i64; - do_addsub2: - nb_iargs = 4; - nb_oargs = 2; - /* Test if the high part of the operation is dead, but not - the low part. The result can be optimized to a simple - add or sub. This happens often for x86_64 guest when the - cpu mode is set to 32 bit. */ - if (arg_temp(op->args[1])->state == TS_DEAD) { - if (arg_temp(op->args[0])->state == TS_DEAD) { - goto do_remove; + case INDEX_op_add2_i32: + opc_new = INDEX_op_add_i32; + goto do_addsub2; + case INDEX_op_sub2_i32: + opc_new = INDEX_op_sub_i32; + goto do_addsub2; + case INDEX_op_add2_i64: + opc_new = INDEX_op_add_i64; + goto do_addsub2; + case INDEX_op_sub2_i64: + opc_new = INDEX_op_sub_i64; + do_addsub2: + nb_iargs = 4; + nb_oargs = 2; + /* Test if the high part of the operation is dead, but not + the low part. The result can be optimized to a simple + add or sub. This happens often for x86_64 guest when the + cpu mode is set to 32 bit. */ + if (arg_temp(op->args[1])->state == TS_DEAD) { + if (arg_temp(op->args[0])->state == TS_DEAD) { + goto do_remove; + } + /* Replace the opcode and adjust the args in place, + leaving 3 unused args at the end. */ + op->opc = opc = opc_new; + op->args[1] = op->args[2]; + op->args[2] = op->args[4]; + /* Fall through and mark the single-word operation live. */ + nb_iargs = 2; + nb_oargs = 1; } - /* Replace the opcode and adjust the args in place, - leaving 3 unused args at the end. */ - op->opc = opc = opc_new; - op->args[1] = op->args[2]; - op->args[2] = op->args[4]; - /* Fall through and mark the single-word operation live. */ + goto do_not_remove; + + case INDEX_op_mulu2_i32: + opc_new = INDEX_op_mul_i32; + opc_new2 = INDEX_op_muluh_i32; + have_opc_new2 = TCG_TARGET_HAS_muluh_i32; + goto do_mul2; + case INDEX_op_muls2_i32: + opc_new = INDEX_op_mul_i32; + opc_new2 = INDEX_op_mulsh_i32; + have_opc_new2 = TCG_TARGET_HAS_mulsh_i32; + goto do_mul2; + case INDEX_op_mulu2_i64: + opc_new = INDEX_op_mul_i64; + opc_new2 = INDEX_op_muluh_i64; + have_opc_new2 = TCG_TARGET_HAS_muluh_i64; + goto do_mul2; + case INDEX_op_muls2_i64: + opc_new = INDEX_op_mul_i64; + opc_new2 = INDEX_op_mulsh_i64; + have_opc_new2 = TCG_TARGET_HAS_mulsh_i64; + goto do_mul2; + do_mul2: nb_iargs = 2; + nb_oargs = 2; + if (arg_temp(op->args[1])->state == TS_DEAD) { + if (arg_temp(op->args[0])->state == TS_DEAD) { + /* Both parts of the operation are dead. */ + goto do_remove; + } + /* The high part of the operation is dead; generate the low. */ + op->opc = opc = opc_new; + op->args[1] = op->args[2]; + op->args[2] = op->args[3]; + } else if (arg_temp(op->args[0])->state == TS_DEAD && have_opc_new2) { + /* The low part of the operation is dead; generate the high. */ + op->opc = opc = opc_new2; + op->args[0] = op->args[1]; + op->args[1] = op->args[2]; + op->args[2] = op->args[3]; + } else { + goto do_not_remove; + } + /* Mark the single-word operation live. */ nb_oargs = 1; - } - goto do_not_remove; + goto do_not_remove; - case INDEX_op_mulu2_i32: - opc_new = INDEX_op_mul_i32; - opc_new2 = INDEX_op_muluh_i32; - have_opc_new2 = TCG_TARGET_HAS_muluh_i32; - goto do_mul2; - case INDEX_op_muls2_i32: - opc_new = INDEX_op_mul_i32; - opc_new2 = INDEX_op_mulsh_i32; - have_opc_new2 = TCG_TARGET_HAS_mulsh_i32; - goto do_mul2; - case INDEX_op_mulu2_i64: - opc_new = INDEX_op_mul_i64; - opc_new2 = INDEX_op_muluh_i64; - have_opc_new2 = TCG_TARGET_HAS_muluh_i64; - goto do_mul2; - case INDEX_op_muls2_i64: - opc_new = INDEX_op_mul_i64; - opc_new2 = INDEX_op_mulsh_i64; - have_opc_new2 = TCG_TARGET_HAS_mulsh_i64; - goto do_mul2; - do_mul2: - nb_iargs = 2; - nb_oargs = 2; - if (arg_temp(op->args[1])->state == TS_DEAD) { - if (arg_temp(op->args[0])->state == TS_DEAD) { - /* Both parts of the operation are dead. */ + default: + /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */ + nb_iargs = def->nb_iargs; + nb_oargs = def->nb_oargs; + + /* Test if the operation can be removed because all + its outputs are dead. We assume that nb_oargs == 0 + implies side effects */ + if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) { + for (i = 0; i < nb_oargs; i++) { + if (arg_temp(op->args[i])->state != TS_DEAD) { + goto do_not_remove; + } + } goto do_remove; } - /* The high part of the operation is dead; generate the low. */ - op->opc = opc = opc_new; - op->args[1] = op->args[2]; - op->args[2] = op->args[3]; - } else if (arg_temp(op->args[0])->state == TS_DEAD && have_opc_new2) { - /* The low part of the operation is dead; generate the high. */ - op->opc = opc = opc_new2; - op->args[0] = op->args[1]; - op->args[1] = op->args[2]; - op->args[2] = op->args[3]; - } else { goto do_not_remove; - } - /* Mark the single-word operation live. */ - nb_oargs = 1; - goto do_not_remove; - default: - /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */ - nb_iargs = def->nb_iargs; - nb_oargs = def->nb_oargs; + do_remove: + tcg_op_remove(s, op); + break; - /* Test if the operation can be removed because all - its outputs are dead. We assume that nb_oargs == 0 - implies side effects */ - if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) { + do_not_remove: for (i = 0; i < nb_oargs; i++) { - if (arg_temp(op->args[i])->state != TS_DEAD) { - goto do_not_remove; - } - } - goto do_remove; - } - goto do_not_remove; - - do_remove: - tcg_op_remove(s, op); - break; - - do_not_remove: - for (i = 0; i < nb_oargs; i++) { - ts = arg_temp(op->args[i]); - - /* Remember the preference of the uses that followed. */ - op->output_pref[i] = *la_temp_pref(ts); - - /* Output args are dead. */ - if (ts->state & TS_DEAD) { - arg_life |= DEAD_ARG << i; - } - if (ts->state & TS_MEM) { - arg_life |= SYNC_ARG << i; - } - ts->state = TS_DEAD; - la_reset_pref(ts); - } + ts = arg_temp(op->args[i]); - /* If end of basic block, update. */ - if (def->flags & TCG_OPF_BB_EXIT) { - la_func_end(s, nb_globals, nb_temps); - } else if (def->flags & TCG_OPF_BB_END) { - la_bb_end(s, nb_globals, nb_temps); - } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { - la_global_sync(s, nb_globals); - if (def->flags & TCG_OPF_CALL_CLOBBER) { - la_cross_call(s, nb_temps); - } - } + /* Remember the preference of the uses that followed. */ + op->output_pref[i] = *la_temp_pref(ts); - /* Record arguments that die in this opcode. */ - for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { - ts = arg_temp(op->args[i]); - if (ts->state & TS_DEAD) { - arg_life |= DEAD_ARG << i; + /* Output args are dead. */ + if (ts->state & TS_DEAD) { + arg_life |= DEAD_ARG << i; + } + if (ts->state & TS_MEM) { + arg_life |= SYNC_ARG << i; + } + ts->state = TS_DEAD; + la_reset_pref(ts); } - } - /* Input arguments are live for preceding opcodes. */ - for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { - ts = arg_temp(op->args[i]); - if (ts->state & TS_DEAD) { - /* For operands that were dead, initially allow - all regs for the type. */ - *la_temp_pref(ts) = tcg_target_available_regs[ts->type]; - ts->state &= ~TS_DEAD; + /* If end of basic block, update. */ + if (def->flags & TCG_OPF_BB_EXIT) { + la_func_end(s, nb_globals, nb_temps); + } else if (def->flags & TCG_OPF_BB_END) { + la_bb_end(s, nb_globals, nb_temps); + } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { + la_global_sync(s, nb_globals); + if (def->flags & TCG_OPF_CALL_CLOBBER) { + la_cross_call(s, nb_temps); + } } - } - /* Incorporate constraints for this operand. */ - switch (opc) { - case INDEX_op_mov_i32: - case INDEX_op_mov_i64: - /* Note that these are TCG_OPF_NOT_PRESENT and do not - have proper constraints. That said, special case - moves to propagate preferences backward. */ - if (IS_DEAD_ARG(1)) { - *la_temp_pref(arg_temp(op->args[0])) - = *la_temp_pref(arg_temp(op->args[1])); + /* Record arguments that die in this opcode. */ + for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { + ts = arg_temp(op->args[i]); + if (ts->state & TS_DEAD) { + arg_life |= DEAD_ARG << i; + } } - break; - default: + /* Input arguments are live for preceding opcodes. */ for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { - const TCGArgConstraint *ct = &def->args_ct[i]; - TCGRegSet set, *pset; - ts = arg_temp(op->args[i]); - pset = la_temp_pref(ts); - set = *pset; - - set &= ct->u.regs; - if (ct->ct & TCG_CT_IALIAS) { - set &= op->output_pref[ct->alias_index]; - } - /* If the combination is not possible, restart. */ - if (set == 0) { - set = ct->u.regs; + if (ts->state & TS_DEAD) { + /* For operands that were dead, initially allow + all regs for the type. */ + *la_temp_pref(ts) = tcg_target_available_regs[ts->type]; + ts->state &= ~TS_DEAD; } - *pset = set; + } + + /* Incorporate constraints for this operand. */ + switch (opc) { + case INDEX_op_mov_i32: + case INDEX_op_mov_i64: + /* Note that these are TCG_OPF_NOT_PRESENT and do not + have proper constraints. That said, special case + moves to propagate preferences backward. */ + if (IS_DEAD_ARG(1)) { + *la_temp_pref(arg_temp(op->args[0])) = *la_temp_pref(arg_temp(op->args[1])); + } + break; + + default: + for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { + const TCGArgConstraint *ct = &def->args_ct[i]; + TCGRegSet set, *pset; + + ts = arg_temp(op->args[i]); + pset = la_temp_pref(ts); + set = *pset; + + set &= ct->u.regs; + if (ct->ct & TCG_CT_IALIAS) { + set &= op->output_pref[ct->alias_index]; + } + /* If the combination is not possible, restart. */ + if (set == 0) { + set = ct->u.regs; + } + *pset = set; + } + break; } break; - } - break; } op->life = arg_life; } } /* Liveness analysis: Convert indirect regs to direct temporaries. */ -static bool liveness_pass_2(TCGContext *s) -{ +static bool liveness_pass_2(TCGContext *s) { int nb_globals = s->nb_globals; int nb_temps, i; bool changes = false; @@ -2874,8 +2707,7 @@ static bool liveness_pass_2(TCGContext *s) call_flags = TCG_CALL_NO_WRITE_GLOBALS; } else { /* No effect on globals. */ - call_flags = (TCG_CALL_NO_READ_GLOBALS | - TCG_CALL_NO_WRITE_GLOBALS); + call_flags = (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS); } } @@ -2885,9 +2717,7 @@ static bool liveness_pass_2(TCGContext *s) if (arg_ts) { dir_ts = arg_ts->state_ptr; if (dir_ts && arg_ts->state == TS_DEAD) { - TCGOpcode lopc = (arg_ts->type == TCG_TYPE_I32 - ? INDEX_op_ld_i32 - : INDEX_op_ld_i64); + TCGOpcode lopc = (arg_ts->type == TCG_TYPE_I32 ? INDEX_op_ld_i32 : INDEX_op_ld_i64); TCGOp *lop = tcg_op_insert_before(s, op, lopc); lop->args[0] = temp_arg(dir_ts); @@ -2926,16 +2756,14 @@ static bool liveness_pass_2(TCGContext *s) /* Liveness should see that globals are synced back, that is, either TS_DEAD or TS_MEM. */ arg_ts = &s->temps[i]; - tcg_debug_assert(arg_ts->state_ptr == 0 - || arg_ts->state != 0); + tcg_debug_assert(arg_ts->state_ptr == 0 || arg_ts->state != 0); } } else { for (i = 0; i < nb_globals; ++i) { /* Liveness should see that globals are saved back, that is, TS_DEAD, waiting to be reloaded. */ arg_ts = &s->temps[i]; - tcg_debug_assert(arg_ts->state_ptr == 0 - || arg_ts->state == TS_DEAD); + tcg_debug_assert(arg_ts->state_ptr == 0 || arg_ts->state == TS_DEAD); } } @@ -2954,9 +2782,7 @@ static bool liveness_pass_2(TCGContext *s) /* Sync outputs upon their last write. */ if (NEED_SYNC_ARG(i)) { - TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32 - ? INDEX_op_st_i32 - : INDEX_op_st_i64); + TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32 ? INDEX_op_st_i32 : INDEX_op_st_i64); TCGOp *sop = tcg_op_insert_after(s, op, sopc); sop->args[0] = temp_arg(dir_ts); @@ -2976,47 +2802,42 @@ static bool liveness_pass_2(TCGContext *s) } #ifdef CONFIG_DEBUG_TCG -static void dump_regs(TCGContext *s) -{ +static void dump_regs(TCGContext *s) { TCGTemp *ts; int i; char buf[64]; - for(i = 0; i < s->nb_temps; i++) { + for (i = 0; i < s->nb_temps; i++) { ts = &s->temps[i]; printf(" %10s: ", tcg_get_arg_str_ptr(s, buf, sizeof(buf), ts)); - switch(ts->val_type) { - case TEMP_VAL_REG: - printf("%s", tcg_target_reg_names[ts->reg]); - break; - case TEMP_VAL_MEM: - printf("%d(%s)", (int)ts->mem_offset, - tcg_target_reg_names[ts->mem_base->reg]); - break; - case TEMP_VAL_CONST: - printf("$0x%" TCG_PRIlx, ts->val); - break; - case TEMP_VAL_DEAD: - printf("D"); - break; - default: - printf("???"); - break; + switch (ts->val_type) { + case TEMP_VAL_REG: + printf("%s", tcg_target_reg_names[ts->reg]); + break; + case TEMP_VAL_MEM: + printf("%d(%s)", (int) ts->mem_offset, tcg_target_reg_names[ts->mem_base->reg]); + break; + case TEMP_VAL_CONST: + printf("$0x%" TCG_PRIlx, ts->val); + break; + case TEMP_VAL_DEAD: + printf("D"); + break; + default: + printf("???"); + break; } printf("\n"); } - for(i = 0; i < TCG_TARGET_NB_REGS; i++) { + for (i = 0; i < TCG_TARGET_NB_REGS; i++) { if (s->reg_to_temp[i] != NULL) { - printf("%s: %s\n", - tcg_target_reg_names[i], - tcg_get_arg_str_ptr(s, buf, sizeof(buf), s->reg_to_temp[i])); + printf("%s: %s\n", tcg_target_reg_names[i], tcg_get_arg_str_ptr(s, buf, sizeof(buf), s->reg_to_temp[i])); } } } -static void check_regs(TCGContext *s) -{ +static void check_regs(TCGContext *s) { int reg; int k; TCGTemp *ts; @@ -3026,18 +2847,15 @@ static void check_regs(TCGContext *s) ts = s->reg_to_temp[reg]; if (ts != NULL) { if (ts->val_type != TEMP_VAL_REG || ts->reg != reg) { - printf("Inconsistency for register %s:\n", - tcg_target_reg_names[reg]); + printf("Inconsistency for register %s:\n", tcg_target_reg_names[reg]); goto fail; } } } for (k = 0; k < s->nb_temps; k++) { ts = &s->temps[k]; - if (ts->val_type == TEMP_VAL_REG && !ts->fixed_reg - && s->reg_to_temp[ts->reg] != ts) { - printf("Inconsistency for temp %s:\n", - tcg_get_arg_str_ptr(s, buf, sizeof(buf), ts)); + if (ts->val_type == TEMP_VAL_REG && !ts->fixed_reg && s->reg_to_temp[ts->reg] != ts) { + printf("Inconsistency for temp %s:\n", tcg_get_arg_str_ptr(s, buf, sizeof(buf), ts)); fail: printf("reg state:\n"); dump_regs(s); @@ -3047,16 +2865,13 @@ static void check_regs(TCGContext *s) } #endif -static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) -{ +static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) { #if !(defined(__sparc__) && TCG_TARGET_REG_BITS == 64) /* Sparc64 stack is accessed with offset of 2047 */ - s->current_frame_offset = (s->current_frame_offset + - (tcg_target_long)sizeof(tcg_target_long) - 1) & - ~(sizeof(tcg_target_long) - 1); + s->current_frame_offset = + (s->current_frame_offset + (tcg_target_long) sizeof(tcg_target_long) - 1) & ~(sizeof(tcg_target_long) - 1); #endif - if (s->current_frame_offset + (tcg_target_long)sizeof(tcg_target_long) > - s->frame_end) { + if (s->current_frame_offset + (tcg_target_long) sizeof(tcg_target_long) > s->frame_end) { tcg_abort(); } ts->mem_offset = s->current_frame_offset; @@ -3069,23 +2884,18 @@ static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet); /* Mark a temporary as free or dead. If 'free_or_dead' is negative, mark it free; otherwise mark it dead. */ -static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead) -{ +static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead) { if (ts->fixed_reg) { return; } if (ts->val_type == TEMP_VAL_REG) { s->reg_to_temp[ts->reg] = NULL; } - ts->val_type = (free_or_dead < 0 - || ts->temp_local - || ts->temp_global - ? TEMP_VAL_MEM : TEMP_VAL_DEAD); + ts->val_type = (free_or_dead < 0 || ts->temp_local || ts->temp_global ? TEMP_VAL_MEM : TEMP_VAL_DEAD); } /* Mark a temporary as dead. */ -static inline void temp_dead(TCGContext *s, TCGTemp *ts) -{ +static inline void temp_dead(TCGContext *s, TCGTemp *ts) { temp_free_or_dead(s, ts, 1); } @@ -3093,9 +2903,8 @@ static inline void temp_dead(TCGContext *s, TCGTemp *ts) registers needs to be allocated to store a constant. If 'free_or_dead' is non-zero, subsequently release the temporary; if it is positive, the temp is dead; if it is negative, the temp is free. */ -static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs, - TCGRegSet preferred_regs, int free_or_dead) -{ +static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs, TCGRegSet preferred_regs, + int free_or_dead) { if (ts->fixed_reg) { return; } @@ -3104,30 +2913,26 @@ static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs, temp_allocate_frame(s, ts); } switch (ts->val_type) { - case TEMP_VAL_CONST: - /* If we're going to free the temp immediately, then we won't - require it later in a register, so attempt to store the - constant to memory directly. */ - if (free_or_dead - && tcg_out_sti(s, ts->type, ts->val, - ts->mem_base->reg, ts->mem_offset)) { - break; - } - temp_load(s, ts, tcg_target_available_regs[ts->type], - allocated_regs, preferred_regs); + case TEMP_VAL_CONST: + /* If we're going to free the temp immediately, then we won't + require it later in a register, so attempt to store the + constant to memory directly. */ + if (free_or_dead && tcg_out_sti(s, ts->type, ts->val, ts->mem_base->reg, ts->mem_offset)) { + break; + } + temp_load(s, ts, tcg_target_available_regs[ts->type], allocated_regs, preferred_regs); /* fallthrough */ - case TEMP_VAL_REG: - tcg_out_st(s, ts->type, ts->reg, - ts->mem_base->reg, ts->mem_offset); - break; + case TEMP_VAL_REG: + tcg_out_st(s, ts->type, ts->reg, ts->mem_base->reg, ts->mem_offset); + break; - case TEMP_VAL_MEM: - break; + case TEMP_VAL_MEM: + break; - case TEMP_VAL_DEAD: - default: - tcg_abort(); + case TEMP_VAL_DEAD: + default: + tcg_abort(); } ts->mem_coherent = 1; } @@ -3137,8 +2942,7 @@ static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs, } /* free register 'reg' by spilling the corresponding temporary if necessary */ -static void tcg_reg_free(TCGContext *s, TCGReg reg, TCGRegSet allocated_regs) -{ +static void tcg_reg_free(TCGContext *s, TCGReg reg, TCGRegSet allocated_regs) { TCGTemp *ts = s->reg_to_temp[reg]; if (ts != NULL) { temp_sync(s, ts, allocated_regs, 0, -1); @@ -3155,10 +2959,8 @@ static void tcg_reg_free(TCGContext *s, TCGReg reg, TCGRegSet allocated_regs) * The allocated register must be in @required_regs & ~@allocated_regs, * but if we can put it in @preferred_regs we may save a move later. */ -static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet required_regs, - TCGRegSet allocated_regs, - TCGRegSet preferred_regs, bool rev) -{ +static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet required_regs, TCGRegSet allocated_regs, TCGRegSet preferred_regs, + bool rev) { int i, j, f, n = ARRAY_SIZE(tcg_target_reg_alloc_order); TCGRegSet reg_ct[2]; const int *order; @@ -3186,8 +2988,7 @@ static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet required_regs, } else { for (i = 0; i < n; i++) { TCGReg reg = order[i]; - if (s->reg_to_temp[reg] == NULL && - tcg_regset_test_reg(set, reg)) { + if (s->reg_to_temp[reg] == NULL && tcg_regset_test_reg(set, reg)) { return reg; } } @@ -3219,29 +3020,26 @@ static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet required_regs, /* Make sure the temporary is in a register. If needed, allocate the register from DESIRED while avoiding ALLOCATED. */ -static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, - TCGRegSet allocated_regs, TCGRegSet preferred_regs) -{ +static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, TCGRegSet allocated_regs, + TCGRegSet preferred_regs) { TCGReg reg; switch (ts->val_type) { - case TEMP_VAL_REG: - return; - case TEMP_VAL_CONST: - reg = tcg_reg_alloc(s, desired_regs, allocated_regs, - preferred_regs, ts->indirect_base); - tcg_out_movi(s, ts->type, reg, ts->val); - ts->mem_coherent = 0; - break; - case TEMP_VAL_MEM: - reg = tcg_reg_alloc(s, desired_regs, allocated_regs, - preferred_regs, ts->indirect_base); - tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset); - ts->mem_coherent = 1; - break; - case TEMP_VAL_DEAD: - default: - tcg_abort(); + case TEMP_VAL_REG: + return; + case TEMP_VAL_CONST: + reg = tcg_reg_alloc(s, desired_regs, allocated_regs, preferred_regs, ts->indirect_base); + tcg_out_movi(s, ts->type, reg, ts->val); + ts->mem_coherent = 0; + break; + case TEMP_VAL_MEM: + reg = tcg_reg_alloc(s, desired_regs, allocated_regs, preferred_regs, ts->indirect_base); + tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset); + ts->mem_coherent = 1; + break; + case TEMP_VAL_DEAD: + default: + tcg_abort(); } ts->reg = reg; ts->val_type = TEMP_VAL_REG; @@ -3250,8 +3048,7 @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, /* Save a temporary to memory. 'allocated_regs' is used in case a temporary registers needs to be allocated to store a constant. */ -static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs) -{ +static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs) { /* The liveness analysis already ensures that globals are back in memory. Keep an tcg_debug_assert for safety. */ tcg_debug_assert(ts->val_type == TEMP_VAL_MEM || ts->fixed_reg); @@ -3260,8 +3057,7 @@ static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs) /* save globals to their canonical location and assume they can be modified be the following code. 'allocated_regs' is used in case a temporary registers needs to be allocated to store a constant. */ -static void save_globals(TCGContext *s, TCGRegSet allocated_regs) -{ +static void save_globals(TCGContext *s, TCGRegSet allocated_regs) { int i, n; for (i = 0, n = s->nb_globals; i < n; i++) { @@ -3272,22 +3068,18 @@ static void save_globals(TCGContext *s, TCGRegSet allocated_regs) /* sync globals to their canonical location and assume they can be read by the following code. 'allocated_regs' is used in case a temporary registers needs to be allocated to store a constant. */ -static void sync_globals(TCGContext *s, TCGRegSet allocated_regs) -{ +static void sync_globals(TCGContext *s, TCGRegSet allocated_regs) { int i, n; for (i = 0, n = s->nb_globals; i < n; i++) { TCGTemp *ts = &s->temps[i]; - tcg_debug_assert(ts->val_type != TEMP_VAL_REG - || ts->fixed_reg - || ts->mem_coherent); + tcg_debug_assert(ts->val_type != TEMP_VAL_REG || ts->fixed_reg || ts->mem_coherent); } } /* at the end of a basic block, we assume all temporaries are dead and all globals are stored at their canonical location. */ -static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) -{ +static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) { int i; for (i = s->nb_globals; i < s->nb_temps; i++) { @@ -3304,10 +3096,8 @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) save_globals(s, allocated_regs); } -static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, - tcg_target_ulong val, TCGLifeData arg_life, - TCGRegSet preferred_regs) -{ +static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, tcg_target_ulong val, TCGLifeData arg_life, + TCGRegSet preferred_regs) { if (ots->fixed_reg) { /* For fixed registers, we do not do any constant propagation. */ tcg_out_movi(s, ots->type, ots->reg, val); @@ -3328,16 +3118,14 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, } } -static void tcg_reg_alloc_movi(TCGContext *s, const TCGOp *op) -{ +static void tcg_reg_alloc_movi(TCGContext *s, const TCGOp *op) { TCGTemp *ots = arg_temp(op->args[0]); tcg_target_ulong val = op->args[1]; tcg_reg_alloc_do_movi(s, ots, val, op->life, op->output_pref[0]); } -static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) -{ +static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) { const TCGLifeData arg_life = op->life; TCGRegSet allocated_regs, preferred_regs; TCGTemp *ts, *ots; @@ -3367,8 +3155,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) the SOURCE value into its own register first, that way we don't have to reload SOURCE the next time it is used. */ if (ts->val_type == TEMP_VAL_MEM) { - temp_load(s, ts, tcg_target_available_regs[itype], - allocated_regs, preferred_regs); + temp_load(s, ts, tcg_target_available_regs[itype], allocated_regs, preferred_regs); } tcg_debug_assert(ts->val_type == TEMP_VAL_REG); @@ -3397,8 +3184,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) /* When allocating a new register, make sure to not spill the input one. */ tcg_regset_set_reg(allocated_regs, ts->reg); - ots->reg = tcg_reg_alloc(s, tcg_target_available_regs[otype], - allocated_regs, preferred_regs, + ots->reg = tcg_reg_alloc(s, tcg_target_available_regs[otype], allocated_regs, preferred_regs, ots->indirect_base); } tcg_out_mov(s, otype, ots->reg, ts->reg); @@ -3412,10 +3198,9 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) } } -static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) -{ +static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) { const TCGLifeData arg_life = op->life; - const TCGOpDef * const def = &tcg_op_defs[op->opc]; + const TCGOpDef *const def = &tcg_op_defs[op->opc]; TCGRegSet i_allocated_regs; TCGRegSet o_allocated_regs; int i, k, nb_iargs, nb_oargs; @@ -3430,14 +3215,12 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) nb_iargs = def->nb_iargs; /* copy constants */ - memcpy(new_args + nb_oargs + nb_iargs, - op->args + nb_oargs + nb_iargs, - sizeof(TCGArg) * def->nb_cargs); + memcpy(new_args + nb_oargs + nb_iargs, op->args + nb_oargs + nb_iargs, sizeof(TCGArg) * def->nb_cargs); i_allocated_regs = s->reserved_regs; o_allocated_regs = s->reserved_regs; - /* satisfy input constraints */ + /* satisfy input constraints */ for (k = 0; k < nb_iargs; k++) { TCGRegSet i_preferred_regs, o_preferred_regs; @@ -3446,8 +3229,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) arg_ct = &def->args_ct[i]; ts = arg_temp(arg); - if (ts->val_type == TEMP_VAL_CONST - && tcg_target_const_match(ts->val, ts->type, arg_ct)) { + if (ts->val_type == TEMP_VAL_CONST && tcg_target_const_match(ts->val, ts->type, arg_ct)) { /* constant is OK for instruction */ const_args[i] = 1; new_args[i] = ts->val; @@ -3476,10 +3258,9 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) if (ts->val_type == TEMP_VAL_REG) { int k2, i2; reg = ts->reg; - for (k2 = 0 ; k2 < k ; k2++) { + for (k2 = 0; k2 < k; k2++) { i2 = def->sorted_args[nb_oargs + k2]; - if ((def->args_ct[i2].ct & TCG_CT_IALIAS) && - reg == new_args[i2]) { + if ((def->args_ct[i2].ct & TCG_CT_IALIAS) && reg == new_args[i2]) { goto allocate_in_reg; } } @@ -3495,19 +3276,17 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) /* nothing to do : the constraint is satisfied */ } else { allocate_in_reg: - /* allocate a new register matching the constraint + /* allocate a new register matching the constraint and move the temporary register into it */ - temp_load(s, ts, tcg_target_available_regs[ts->type], - i_allocated_regs, 0); - reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs, - o_preferred_regs, ts->indirect_base); + temp_load(s, ts, tcg_target_available_regs[ts->type], i_allocated_regs, 0); + reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs, o_preferred_regs, ts->indirect_base); tcg_out_mov(s, ts->type, reg, ts->reg); } new_args[i] = reg; const_args[i] = 0; tcg_regset_set_reg(i_allocated_regs, reg); } - + /* mark dead temporaries and free the associated registers */ for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { if (IS_DEAD_ARG(i)) { @@ -3519,7 +3298,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) tcg_reg_alloc_bb_end(s, i_allocated_regs); } else { if (def->flags & TCG_OPF_CALL_CLOBBER) { - /* XXX: permit generic clobber register list ? */ + /* XXX: permit generic clobber register list ? */ for (i = 0; i < TCG_TARGET_NB_REGS; i++) { if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) { tcg_reg_free(s, i, i_allocated_regs); @@ -3531,29 +3310,25 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) an exception. */ sync_globals(s, i_allocated_regs); } - + /* satisfy the output constraints */ - for(k = 0; k < nb_oargs; k++) { + for (k = 0; k < nb_oargs; k++) { i = def->sorted_args[k]; arg = op->args[i]; arg_ct = &def->args_ct[i]; ts = arg_temp(arg); - if ((arg_ct->ct & TCG_CT_ALIAS) - && !const_args[arg_ct->alias_index]) { + if ((arg_ct->ct & TCG_CT_ALIAS) && !const_args[arg_ct->alias_index]) { reg = new_args[arg_ct->alias_index]; } else if (arg_ct->ct & TCG_CT_NEWREG) { - reg = tcg_reg_alloc(s, arg_ct->u.regs, - i_allocated_regs | o_allocated_regs, - op->output_pref[k], ts->indirect_base); + reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs | o_allocated_regs, op->output_pref[k], + ts->indirect_base); } else { /* if fixed register, we try to use it */ reg = ts->reg; - if (ts->fixed_reg && - tcg_regset_test_reg(arg_ct->u.regs, reg)) { + if (ts->fixed_reg && tcg_regset_test_reg(arg_ct->u.regs, reg)) { goto oarg_end; } - reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs, - op->output_pref[k], ts->indirect_base); + reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs, op->output_pref[k], ts->indirect_base); } tcg_regset_set_reg(o_allocated_regs, reg); /* if a fixed register is used, then a move will be done afterwards */ @@ -3575,14 +3350,13 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) /* emit instruction */ if (def->flags & TCG_OPF_VECTOR) { - tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op), - new_args, const_args); + tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op), new_args, const_args); } else { tcg_out_op(s, op->opc, new_args, const_args); } /* move the outputs in the correct register if needed */ - for(i = 0; i < nb_oargs; i++) { + for (i = 0; i < nb_oargs; i++) { ts = arg_temp(op->args[i]); reg = new_args[i]; if (ts->fixed_reg && ts->reg != reg) { @@ -3602,8 +3376,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) #define STACK_DIR(x) (x) #endif -static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) -{ +static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) { const int nb_oargs = TCGOP_CALLO(op); const int nb_iargs = TCGOP_CALLI(op); const TCGLifeData arg_life = op->life; @@ -3617,7 +3390,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) int allocate_args; TCGRegSet allocated_regs; - func_addr = (tcg_insn_unit *)(intptr_t)op->args[nb_oargs + nb_iargs]; + func_addr = (tcg_insn_unit *) (intptr_t) op->args[nb_oargs + nb_iargs]; flags = op->args[nb_oargs + nb_iargs + 1]; nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs); @@ -3627,8 +3400,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) /* assign stack slots first */ call_stack_size = (nb_iargs - nb_regs) * sizeof(tcg_target_long); - call_stack_size = (call_stack_size + TCG_TARGET_STACK_ALIGN - 1) & - ~(TCG_TARGET_STACK_ALIGN - 1); + call_stack_size = (call_stack_size + TCG_TARGET_STACK_ALIGN - 1) & ~(TCG_TARGET_STACK_ALIGN - 1); allocate_args = (call_stack_size > TCG_STATIC_CALL_ARGS_SIZE); if (allocate_args) { /* XXX: if more than TCG_STATIC_CALL_ARGS_SIZE is needed, @@ -3644,15 +3416,14 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) #endif if (arg != TCG_CALL_DUMMY_ARG) { ts = arg_temp(arg); - temp_load(s, ts, tcg_target_available_regs[ts->type], - s->reserved_regs, 0); + temp_load(s, ts, tcg_target_available_regs[ts->type], s->reserved_regs, 0); tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_offset); } #ifndef TCG_TARGET_STACK_GROWSUP stack_offset += sizeof(tcg_target_long); #endif } - + /* assign input registers */ allocated_regs = s->reserved_regs; for (i = 0; i < nb_regs; i++) { @@ -3677,14 +3448,14 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) tcg_regset_set_reg(allocated_regs, reg); } } - + /* mark dead temporaries and free the associated registers */ for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { if (IS_DEAD_ARG(i)) { temp_dead(s, arg_temp(op->args[i])); } } - + /* clobber call registers */ for (i = 0; i < TCG_TARGET_NB_REGS; i++) { if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) { @@ -3705,7 +3476,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) tcg_out_call(s, func_addr); /* assign output registers and emit moves if needed */ - for(i = 0; i < nb_oargs; i++) { + for (i = 0; i < nb_oargs; i++) { arg = op->args[i]; ts = arg_temp(arg); reg = tcg_target_call_oarg_regs[i]; @@ -3735,23 +3506,21 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) #ifdef CONFIG_PROFILER /* avoid copy/paste errors */ -#define PROF_ADD(to, from, field) \ - do { \ - (to)->field += atomic_read(&((from)->field)); \ +#define PROF_ADD(to, from, field) \ + do { \ + (to)->field += atomic_read(&((from)->field)); \ } while (0) -#define PROF_MAX(to, from, field) \ - do { \ - typeof((from)->field) val__ = atomic_read(&((from)->field)); \ - if (val__ > (to)->field) { \ - (to)->field = val__; \ - } \ +#define PROF_MAX(to, from, field) \ + do { \ + typeof((from)->field) val__ = atomic_read(&((from)->field)); \ + if (val__ > (to)->field) { \ + (to)->field = val__; \ + } \ } while (0) /* Pass in a zero'ed @prof */ -static inline -void tcg_profile_snapshot(TCGProfile *prof, bool counters, bool table) -{ +static inline void tcg_profile_snapshot(TCGProfile *prof, bool counters, bool table) { unsigned int n_ctxs = atomic_read(&n_tcg_ctxs); unsigned int i; @@ -3791,30 +3560,25 @@ void tcg_profile_snapshot(TCGProfile *prof, bool counters, bool table) #undef PROF_ADD #undef PROF_MAX -static void tcg_profile_snapshot_counters(TCGProfile *prof) -{ +static void tcg_profile_snapshot_counters(TCGProfile *prof) { tcg_profile_snapshot(prof, true, false); } -static void tcg_profile_snapshot_table(TCGProfile *prof) -{ +static void tcg_profile_snapshot_table(TCGProfile *prof) { tcg_profile_snapshot(prof, false, true); } -void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf) -{ +void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf) { TCGProfile prof = {}; int i; tcg_profile_snapshot_table(&prof); for (i = 0; i < NB_OPS; i++) { - cpu_fprintf(f, "%s %" PRId64 "\n", tcg_op_defs[i].name, - prof.table_op_count[i]); + cpu_fprintf(f, "%s %" PRId64 "\n", tcg_op_defs[i].name, prof.table_op_count[i]); } } -int64_t tcg_cpu_exec_time(void) -{ +int64_t tcg_cpu_exec_time(void) { unsigned int n_ctxs = atomic_read(&n_tcg_ctxs); unsigned int i; int64_t ret = 0; @@ -3828,21 +3592,17 @@ int64_t tcg_cpu_exec_time(void) return ret; } #else -void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf) -{ +void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf) { cpu_fprintf(f, "[TCG profiler not compiled]\n"); } -int64_t tcg_cpu_exec_time(void) -{ +int64_t tcg_cpu_exec_time(void) { printf("%s: TCG profiler not compiled", __func__); exit(EXIT_FAILURE); } #endif - -int tcg_gen_code(TCGContext *s, TranslationBlock *tb) -{ +int tcg_gen_code(TCGContext *s, TranslationBlock *tb) { #ifdef CONFIG_PROFILER TCGProfile *prof = &s->prof; #endif @@ -3853,9 +3613,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) { int n = 0; - QTAILQ_FOREACH(op, &s->ops, link) { - n++; - } + QTAILQ_FOREACH (op, &s->ops, link) { n++; } atomic_set(&prof->op_count, prof->op_count + n); if (n > prof->op_count_max) { atomic_set(&prof->op_count_max, n); @@ -3870,8 +3628,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #endif #ifdef DEBUG_DISAS - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP) - && qemu_log_in_addr_range(tb->pc))) { + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP) && qemu_log_in_addr_range(tb->pc))) { qemu_log_lock(); qemu_log("OP:\n"); tcg_dump_ops(s, false); @@ -3888,8 +3645,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) QSIMPLEQ_FOREACH(l, &s->labels, next) { if (unlikely(!l->present) && l->refs) { - qemu_log_mask(CPU_LOG_TB_OP, - "$L%d referenced but not present.\n", l->id); + qemu_log_mask(CPU_LOG_TB_OP, "$L%d referenced but not present.\n", l->id); error = true; } } @@ -3915,8 +3671,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) if (s->nb_indirects > 0) { #ifdef DEBUG_DISAS - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND) - && qemu_log_in_addr_range(tb->pc))) { + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND) && qemu_log_in_addr_range(tb->pc))) { qemu_log_lock(); qemu_log("OP before indirect lowering:\n"); tcg_dump_ops(s, false); @@ -3936,8 +3691,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #endif #ifdef DEBUG_DISAS - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT) - && qemu_log_in_addr_range(tb->pc))) { + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT) && qemu_log_in_addr_range(tb->pc))) { qemu_log_lock(); qemu_log("OP after optimization and liveness analysis:\n"); tcg_dump_ops(s, true); @@ -3959,7 +3713,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #endif num_insns = -1; - QTAILQ_FOREACH(op, &s->ops, link) { + QTAILQ_FOREACH (op, &s->ops, link) { TCGOpcode opc = op->opc; #ifdef CONFIG_PROFILER @@ -3967,52 +3721,52 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #endif switch (opc) { - case INDEX_op_mov_i32: - case INDEX_op_mov_i64: - case INDEX_op_mov_vec: - tcg_reg_alloc_mov(s, op); - break; - case INDEX_op_movi_i32: - case INDEX_op_movi_i64: - case INDEX_op_dupi_vec: - tcg_reg_alloc_movi(s, op); - break; - case INDEX_op_insn_start: - if (num_insns >= 0) { - size_t off = tcg_current_code_size(s); - s->gen_insn_end_off[num_insns] = off; - /* Assert that we do not overflow our stored offset. */ - assert(s->gen_insn_end_off[num_insns] == off); - } - num_insns++; - for (i = 0; i < TARGET_INSN_START_WORDS; ++i) { - target_ulong a; + case INDEX_op_mov_i32: + case INDEX_op_mov_i64: + case INDEX_op_mov_vec: + tcg_reg_alloc_mov(s, op); + break; + case INDEX_op_movi_i32: + case INDEX_op_movi_i64: + case INDEX_op_dupi_vec: + tcg_reg_alloc_movi(s, op); + break; + case INDEX_op_insn_start: + if (num_insns >= 0) { + size_t off = tcg_current_code_size(s); + s->gen_insn_end_off[num_insns] = off; + /* Assert that we do not overflow our stored offset. */ + assert(s->gen_insn_end_off[num_insns] == off); + } + num_insns++; + for (i = 0; i < TARGET_INSN_START_WORDS; ++i) { + target_ulong a; #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - a = deposit64(op->args[i * 2], 32, 32, op->args[i * 2 + 1]); + a = deposit64(op->args[i * 2], 32, 32, op->args[i * 2 + 1]); #else - a = op->args[i]; + a = op->args[i]; #endif - s->gen_insn_data[num_insns][i] = a; - } - break; - case INDEX_op_discard: - temp_dead(s, arg_temp(op->args[0])); - break; - case INDEX_op_set_label: - tcg_reg_alloc_bb_end(s, s->reserved_regs); - tcg_out_label(s, arg_label(op->args[0]), s->code_ptr); - break; - case INDEX_op_call: - tcg_reg_alloc_call(s, op); - break; - default: - /* Sanity check that we've not introduced any unhandled opcodes. */ - tcg_debug_assert(tcg_op_supported(opc)); - /* Note: in order to speed up the code, it would be much - faster to have specialized register allocator functions for - some common argument patterns */ - tcg_reg_alloc_op(s, op); - break; + s->gen_insn_data[num_insns][i] = a; + } + break; + case INDEX_op_discard: + temp_dead(s, arg_temp(op->args[0])); + break; + case INDEX_op_set_label: + tcg_reg_alloc_bb_end(s, s->reserved_regs); + tcg_out_label(s, arg_label(op->args[0]), s->code_ptr); + break; + case INDEX_op_call: + tcg_reg_alloc_call(s, op); + break; + default: + /* Sanity check that we've not introduced any unhandled opcodes. */ + tcg_debug_assert(tcg_op_supported(opc)); + /* Note: in order to speed up the code, it would be much + faster to have specialized register allocator functions for + some common argument patterns */ + tcg_reg_alloc_op(s, op); + break; } #ifdef CONFIG_DEBUG_TCG check_regs(s); @@ -4021,14 +3775,14 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) one operation beginning below the high water mark cannot overrun the buffer completely. Thus we can test for overflow after generating code without having to check during generation. */ - if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { + if (unlikely((void *) s->code_ptr > s->code_gen_highwater)) { return -1; } } tcg_debug_assert(num_insns >= 0); s->gen_insn_end_off[num_insns] = tcg_current_code_size(s); - /* Generate TB finalization at the end of block */ +/* Generate TB finalization at the end of block */ #ifdef TCG_TARGET_NEED_LDST_LABELS if (!tcg_out_ldst_finalize(s)) { return -1; @@ -4041,14 +3795,13 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #endif /* flush instruction cache */ - flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr); + flush_icache_range((uintptr_t) s->code_buf, (uintptr_t) s->code_ptr); return tcg_current_code_size(s); } #ifdef CONFIG_PROFILER -void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf) -{ +void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf) { TCGProfile prof = {}; const TCGProfile *s; int64_t tb_count; @@ -4061,51 +3814,31 @@ void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf) tb_div_count = tb_count ? tb_count : 1; tot = s->interm_time + s->code_time; - cpu_fprintf(f, "JIT cycles %" PRId64 " (%0.3f s at 2.4 GHz)\n", - tot, tot / 2.4e9); - cpu_fprintf(f, "translated TBs %" PRId64 " (aborted=%" PRId64 " %0.1f%%)\n", - tb_count, s->tb_count1 - tb_count, - (double)(s->tb_count1 - s->tb_count) - / (s->tb_count1 ? s->tb_count1 : 1) * 100.0); - cpu_fprintf(f, "avg ops/TB %0.1f max=%d\n", - (double)s->op_count / tb_div_count, s->op_count_max); - cpu_fprintf(f, "deleted ops/TB %0.2f\n", - (double)s->del_op_count / tb_div_count); - cpu_fprintf(f, "avg temps/TB %0.2f max=%d\n", - (double)s->temp_count / tb_div_count, s->temp_count_max); - cpu_fprintf(f, "avg host code/TB %0.1f\n", - (double)s->code_out_len / tb_div_count); - cpu_fprintf(f, "avg search data/TB %0.1f\n", - (double)s->search_out_len / tb_div_count); - - cpu_fprintf(f, "cycles/op %0.1f\n", - s->op_count ? (double)tot / s->op_count : 0); - cpu_fprintf(f, "cycles/in byte %0.1f\n", - s->code_in_len ? (double)tot / s->code_in_len : 0); - cpu_fprintf(f, "cycles/out byte %0.1f\n", - s->code_out_len ? (double)tot / s->code_out_len : 0); - cpu_fprintf(f, "cycles/search byte %0.1f\n", - s->search_out_len ? (double)tot / s->search_out_len : 0); + cpu_fprintf(f, "JIT cycles %" PRId64 " (%0.3f s at 2.4 GHz)\n", tot, tot / 2.4e9); + cpu_fprintf(f, "translated TBs %" PRId64 " (aborted=%" PRId64 " %0.1f%%)\n", tb_count, s->tb_count1 - tb_count, + (double) (s->tb_count1 - s->tb_count) / (s->tb_count1 ? s->tb_count1 : 1) * 100.0); + cpu_fprintf(f, "avg ops/TB %0.1f max=%d\n", (double) s->op_count / tb_div_count, s->op_count_max); + cpu_fprintf(f, "deleted ops/TB %0.2f\n", (double) s->del_op_count / tb_div_count); + cpu_fprintf(f, "avg temps/TB %0.2f max=%d\n", (double) s->temp_count / tb_div_count, s->temp_count_max); + cpu_fprintf(f, "avg host code/TB %0.1f\n", (double) s->code_out_len / tb_div_count); + cpu_fprintf(f, "avg search data/TB %0.1f\n", (double) s->search_out_len / tb_div_count); + + cpu_fprintf(f, "cycles/op %0.1f\n", s->op_count ? (double) tot / s->op_count : 0); + cpu_fprintf(f, "cycles/in byte %0.1f\n", s->code_in_len ? (double) tot / s->code_in_len : 0); + cpu_fprintf(f, "cycles/out byte %0.1f\n", s->code_out_len ? (double) tot / s->code_out_len : 0); + cpu_fprintf(f, "cycles/search byte %0.1f\n", s->search_out_len ? (double) tot / s->search_out_len : 0); if (tot == 0) { tot = 1; } - cpu_fprintf(f, " gen_interm time %0.1f%%\n", - (double)s->interm_time / tot * 100.0); - cpu_fprintf(f, " gen_code time %0.1f%%\n", - (double)s->code_time / tot * 100.0); - cpu_fprintf(f, "optim./code time %0.1f%%\n", - (double)s->opt_time / (s->code_time ? s->code_time : 1) - * 100.0); - cpu_fprintf(f, "liveness/code time %0.1f%%\n", - (double)s->la_time / (s->code_time ? s->code_time : 1) * 100.0); - cpu_fprintf(f, "cpu_restore count %" PRId64 "\n", - s->restore_count); - cpu_fprintf(f, " avg cycles %0.1f\n", - s->restore_count ? (double)s->restore_time / s->restore_count : 0); + cpu_fprintf(f, " gen_interm time %0.1f%%\n", (double) s->interm_time / tot * 100.0); + cpu_fprintf(f, " gen_code time %0.1f%%\n", (double) s->code_time / tot * 100.0); + cpu_fprintf(f, "optim./code time %0.1f%%\n", (double) s->opt_time / (s->code_time ? s->code_time : 1) * 100.0); + cpu_fprintf(f, "liveness/code time %0.1f%%\n", (double) s->la_time / (s->code_time ? s->code_time : 1) * 100.0); + cpu_fprintf(f, "cpu_restore count %" PRId64 "\n", s->restore_count); + cpu_fprintf(f, " avg cycles %0.1f\n", s->restore_count ? (double) s->restore_time / s->restore_count : 0); } #else -void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf) -{ +void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf) { cpu_fprintf(f, "[TCG profiler not compiled]\n"); } #endif @@ -4124,11 +3857,7 @@ void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf) */ /* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */ -typedef enum { - JIT_NOACTION = 0, - JIT_REGISTER_FN, - JIT_UNREGISTER_FN -} jit_actions_t; +typedef enum { JIT_NOACTION = 0, JIT_REGISTER_FN, JIT_UNREGISTER_FN } jit_actions_t; struct jit_code_entry { struct jit_code_entry *next_entry; @@ -4145,19 +3874,17 @@ struct jit_descriptor { }; void __jit_debug_register_code(void) __attribute__((noinline)); -void __jit_debug_register_code(void) -{ +void __jit_debug_register_code(void) { asm(""); } /* Must statically initialize the version, because GDB may check the version before we can set it. */ -struct jit_descriptor __jit_debug_descriptor = { 1, 0, 0, 0 }; +struct jit_descriptor __jit_debug_descriptor = {1, 0, 0, 0}; /* End GDB interface. */ -static int find_string(const char *strtab, const char *str) -{ +static int find_string(const char *strtab, const char *str) { const char *p = strtab + 1; while (1) { @@ -4168,145 +3895,160 @@ static int find_string(const char *strtab, const char *str) } } -static void tcg_register_jit_int(void *buf_ptr, size_t buf_size, - const void *debug_frame, - size_t debug_frame_size) -{ +static void tcg_register_jit_int(void *buf_ptr, size_t buf_size, const void *debug_frame, size_t debug_frame_size) { struct __attribute__((packed)) DebugInfo { - uint32_t len; - uint16_t version; - uint32_t abbrev; - uint8_t ptr_size; - uint8_t cu_die; - uint16_t cu_lang; + uint32_t len; + uint16_t version; + uint32_t abbrev; + uint8_t ptr_size; + uint8_t cu_die; + uint16_t cu_lang; uintptr_t cu_low_pc; uintptr_t cu_high_pc; - uint8_t fn_die; - char fn_name[16]; + uint8_t fn_die; + char fn_name[16]; uintptr_t fn_low_pc; uintptr_t fn_high_pc; - uint8_t cu_eoc; + uint8_t cu_eoc; }; struct ElfImage { ElfW(Ehdr) ehdr; ElfW(Phdr) phdr; ElfW(Shdr) shdr[7]; - ElfW(Sym) sym[2]; + ElfW(Sym) sym[2]; struct DebugInfo di; - uint8_t da[24]; - char str[80]; + uint8_t da[24]; + char str[80]; }; struct ElfImage *img; - static const struct ElfImage img_template = { - .ehdr = { - .e_ident[EI_MAG0] = ELFMAG0, - .e_ident[EI_MAG1] = ELFMAG1, - .e_ident[EI_MAG2] = ELFMAG2, - .e_ident[EI_MAG3] = ELFMAG3, - .e_ident[EI_CLASS] = ELF_CLASS, - .e_ident[EI_DATA] = ELF_DATA, - .e_ident[EI_VERSION] = EV_CURRENT, - .e_type = ET_EXEC, - .e_machine = ELF_HOST_MACHINE, - .e_version = EV_CURRENT, - .e_phoff = offsetof(struct ElfImage, phdr), - .e_shoff = offsetof(struct ElfImage, shdr), - .e_ehsize = sizeof(ElfW(Shdr)), - .e_phentsize = sizeof(ElfW(Phdr)), - .e_phnum = 1, - .e_shentsize = sizeof(ElfW(Shdr)), - .e_shnum = ARRAY_SIZE(img->shdr), - .e_shstrndx = ARRAY_SIZE(img->shdr) - 1, + static const struct ElfImage + img_template = + { + .ehdr = + { + .e_ident[EI_MAG0] = ELFMAG0, + .e_ident[EI_MAG1] = ELFMAG1, + .e_ident[EI_MAG2] = ELFMAG2, + .e_ident[EI_MAG3] = ELFMAG3, + .e_ident[EI_CLASS] = ELF_CLASS, + .e_ident[EI_DATA] = ELF_DATA, + .e_ident[EI_VERSION] = EV_CURRENT, + .e_type = ET_EXEC, + .e_machine = ELF_HOST_MACHINE, + .e_version = EV_CURRENT, + .e_phoff = offsetof(struct ElfImage, phdr), + .e_shoff = offsetof(struct ElfImage, shdr), + .e_ehsize = sizeof(ElfW(Shdr)), + .e_phentsize = sizeof(ElfW(Phdr)), + .e_phnum = 1, + .e_shentsize = sizeof(ElfW(Shdr)), + .e_shnum = ARRAY_SIZE(img->shdr), + .e_shstrndx = ARRAY_SIZE(img->shdr) - 1, #ifdef ELF_HOST_FLAGS - .e_flags = ELF_HOST_FLAGS, + .e_flags = ELF_HOST_FLAGS, #endif #ifdef ELF_OSABI - .e_ident[EI_OSABI] = ELF_OSABI, + .e_ident[EI_OSABI] = ELF_OSABI, #endif - }, - .phdr = { - .p_type = PT_LOAD, - .p_flags = PF_X, - }, - .shdr = { - [0] = { .sh_type = SHT_NULL }, - /* Trick: The contents of code_gen_buffer are not present in - this fake ELF file; that got allocated elsewhere. Therefore - we mark .text as SHT_NOBITS (similar to .bss) so that readers - will not look for contents. We can record any address. */ - [1] = { /* .text */ - .sh_type = SHT_NOBITS, - .sh_flags = SHF_EXECINSTR | SHF_ALLOC, - }, - [2] = { /* .debug_info */ - .sh_type = SHT_PROGBITS, - .sh_offset = offsetof(struct ElfImage, di), - .sh_size = sizeof(struct DebugInfo), - }, - [3] = { /* .debug_abbrev */ - .sh_type = SHT_PROGBITS, - .sh_offset = offsetof(struct ElfImage, da), - .sh_size = sizeof(img->da), - }, - [4] = { /* .debug_frame */ - .sh_type = SHT_PROGBITS, - .sh_offset = sizeof(struct ElfImage), - }, - [5] = { /* .symtab */ - .sh_type = SHT_SYMTAB, - .sh_offset = offsetof(struct ElfImage, sym), - .sh_size = sizeof(img->sym), - .sh_info = 1, - .sh_link = ARRAY_SIZE(img->shdr) - 1, - .sh_entsize = sizeof(ElfW(Sym)), - }, - [6] = { /* .strtab */ - .sh_type = SHT_STRTAB, - .sh_offset = offsetof(struct ElfImage, str), - .sh_size = sizeof(img->str), - } - }, - .sym = { - [1] = { /* code_gen_buffer */ - .st_info = ELF_ST_INFO(STB_GLOBAL, STT_FUNC), - .st_shndx = 1, - } - }, - .di = { - .len = sizeof(struct DebugInfo) - 4, - .version = 2, - .ptr_size = sizeof(void *), - .cu_die = 1, - .cu_lang = 0x8001, /* DW_LANG_Mips_Assembler */ - .fn_die = 2, - .fn_name = "code_gen_buffer" - }, - .da = { - 1, /* abbrev number (the cu) */ - 0x11, 1, /* DW_TAG_compile_unit, has children */ - 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */ - 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */ - 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */ - 0, 0, /* end of abbrev */ - 2, /* abbrev number (the fn) */ - 0x2e, 0, /* DW_TAG_subprogram, no children */ - 0x3, 0x8, /* DW_AT_name, DW_FORM_string */ - 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */ - 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */ - 0, 0, /* end of abbrev */ - 0 /* no more abbrev */ - }, - .str = "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0" - ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer", - }; + }, + .phdr = + { + .p_type = PT_LOAD, .p_flags = PF_X, + }, + .shdr = {[0] = {.sh_type = SHT_NULL}, + /* Trick: The contents of code_gen_buffer are not present in + this fake ELF file; that got allocated elsewhere. Therefore + we mark .text as SHT_NOBITS (similar to .bss) so that readers + will not look for contents. We can record any address. */ + [1] = + { + /* .text */ + .sh_type = SHT_NOBITS, + .sh_flags = SHF_EXECINSTR | SHF_ALLOC, + }, + [2] = + { + /* .debug_info */ + .sh_type = SHT_PROGBITS, + .sh_offset = offsetof(struct ElfImage, di), + .sh_size = sizeof(struct DebugInfo), + }, + [3] = + { + /* .debug_abbrev */ + .sh_type = SHT_PROGBITS, + .sh_offset = offsetof(struct ElfImage, da), + .sh_size = sizeof(img->da), + }, + [4] = + { + /* .debug_frame */ + .sh_type = SHT_PROGBITS, + .sh_offset = sizeof(struct ElfImage), + }, + [5] = + { + /* .symtab */ + .sh_type = SHT_SYMTAB, + .sh_offset = offsetof(struct ElfImage, sym), + .sh_size = sizeof(img->sym), + .sh_info = 1, + .sh_link = ARRAY_SIZE(img->shdr) - 1, + .sh_entsize = sizeof(ElfW(Sym)), + }, + [6] = + { + /* .strtab */ + .sh_type = SHT_STRTAB, + .sh_offset = offsetof(struct ElfImage, str), + .sh_size = sizeof(img->str), + }}, + .sym = {[1] = + { + /* code_gen_buffer */ + .st_info = ELF_ST_INFO(STB_GLOBAL, STT_FUNC), + .st_shndx = 1, + }}, + .di = {.len = sizeof(struct DebugInfo) - 4, + .version = 2, + .ptr_size = sizeof(void *), + .cu_die = 1, + .cu_lang = 0x8001, /* DW_LANG_Mips_Assembler */ + .fn_die = 2, + .fn_name = "code_gen_buffer"}, + .da = + { + 1, /* abbrev number (the cu) */ + 0x11, 1, /* DW_TAG_compile_unit, has children */ + 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */ + 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */ + 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */ + 0, 0, /* end of abbrev */ + 2, /* abbrev number (the fn) */ + 0x2e, 0, /* DW_TAG_subprogram, no children */ + 0x3, 0x8, /* DW_AT_name, DW_FORM_string */ + 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */ + 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */ + 0, 0, /* end of abbrev */ + 0 /* no more abbrev */ + }, + .str = "\0" + ".text\0" + ".debug_info\0" + ".debug_abbrev\0" + ".debug_frame\0" + ".symtab\0" + ".strtab\0" + "code_gen_buffer", + }; /* We only need a single jit entry; statically allocate it. */ static struct jit_code_entry one_entry; - uintptr_t buf = (uintptr_t)buf_ptr; + uintptr_t buf = (uintptr_t) buf_ptr; size_t img_size = sizeof(struct ElfImage) + debug_frame_size; DebugFrameHeader *dfh; @@ -4339,7 +4081,7 @@ static void tcg_register_jit_int(void *buf_ptr, size_t buf_size, img->di.fn_low_pc = buf; img->di.fn_high_pc = buf + buf_size; - dfh = (DebugFrameHeader *)(img + 1); + dfh = (DebugFrameHeader *) (img + 1); memcpy(dfh, debug_frame, debug_frame_size); dfh->fde.func_start = buf; dfh->fde.func_len = buf_size; @@ -4370,20 +4112,15 @@ static void tcg_register_jit_int(void *buf_ptr, size_t buf_size, /* No support for the feature. Provide the entry point expected by exec.c, and implement the internal function we declared earlier. */ -static void tcg_register_jit_int(void *buf, size_t size, - const void *debug_frame, - size_t debug_frame_size) -{ +static void tcg_register_jit_int(void *buf, size_t size, const void *debug_frame, size_t debug_frame_size) { } -void tcg_register_jit(void *buf, size_t buf_size) -{ +void tcg_register_jit(void *buf, size_t buf_size) { } #endif /* ELF_HOST_MACHINE */ #if !TCG_TARGET_MAYBE_vec -void tcg_expand_vec_op(TCGOpcode o, TCGType t, unsigned e, TCGArg a0, ...) -{ +void tcg_expand_vec_op(TCGOpcode o, TCGType t, unsigned e, TCGArg a0, ...) { g_assert_not_reached(); } #endif