From 3ea082cdaaec2787cb38f556e53792f67ee24b9f Mon Sep 17 00:00:00 2001 From: RDSik Date: Sat, 21 Dec 2024 02:13:16 +0300 Subject: [PATCH] Upd sim folders --- .gitignore | 4 +- README.md | 4 +- .../cocotb/si5340_config_loader_tb.py | 14 +- sim/{modelsim => }/cocotb/test.py | 2 +- sim/{modelsim => }/cocotb/wave.do | 0 sim/modelsim/{hdlmake => }/Manifest.py | 4 +- sim/modelsim/{hdlmake => }/wave.do | 0 sim/verilator/si5340_config_loader.sv | 183 --------- sim/verilator/si5340_config_loader_tb.py | 50 --- sim/verilator/test.py | 57 --- src/gtkw.gtkw | 353 +++++++++--------- 11 files changed, 197 insertions(+), 474 deletions(-) rename sim/{modelsim => }/cocotb/si5340_config_loader_tb.py (78%) rename sim/{modelsim => }/cocotb/test.py (97%) rename sim/{modelsim => }/cocotb/wave.do (100%) rename sim/modelsim/{hdlmake => }/Manifest.py (72%) rename sim/modelsim/{hdlmake => }/wave.do (100%) delete mode 100644 sim/verilator/si5340_config_loader.sv delete mode 100644 sim/verilator/si5340_config_loader_tb.py delete mode 100644 sim/verilator/test.py diff --git a/.gitignore b/.gitignore index 4348ab3..32ca0e7 100644 --- a/.gitignore +++ b/.gitignore @@ -2,11 +2,11 @@ sim/verilator/* !si5340_config_loader_tb.py !si5340_config_loader.sv !test.py -sim/modelsim/cocotb/* +sim/cocotb/* !test.py !si5340_config_loader_tb.py !wave.do -sim/modelsim/hdlmake/* +sim/modelsim/* !Manifest.py !wave.do syn/* diff --git a/README.md b/README.md index 5aaaf19..51e11b9 100644 --- a/README.md +++ b/README.md @@ -51,14 +51,14 @@ py config_parser.py .\Si5340-RevD-Si5340-Registers.txt ```bash py -m venv myenv .\myenv\Scripts\activate.ps1 -cd .\sim\modelsim\cocotb +cd .\sim\cocotb py -m pytest test.py deactivate ``` ### Using hdlmake: ```bash -cd .\sim\modelsim\hdlmake\ +cd .\sim\modelsim\ py -m hdlmake make ``` diff --git a/sim/modelsim/cocotb/si5340_config_loader_tb.py b/sim/cocotb/si5340_config_loader_tb.py similarity index 78% rename from sim/modelsim/cocotb/si5340_config_loader_tb.py rename to sim/cocotb/si5340_config_loader_tb.py index 716b4ea..050ae9e 100644 --- a/sim/modelsim/cocotb/si5340_config_loader_tb.py +++ b/sim/cocotb/si5340_config_loader_tb.py @@ -1,5 +1,6 @@ import cocotb import random +import logging from cocotb.clock import Clock from cocotb.triggers import Timer, RisingEdge, FallingEdge, ClockCycles from cocotb.utils import get_sim_time @@ -9,9 +10,14 @@ class Test: def __init__(self, dut): self.dut = dut + + self.log = logging.getLogger('cocotb.tb') + self.log.setLevel(logging.DEBUG) + dut.arstn_i.setimmediatevalue(0) dut.load_i.setimmediatevalue(0) dut.write_i.setimmediatevalue(0) + cocotb.start_soon(Clock(self.dut.clk_i, clk_per, units = 'ns').start()) async def init(self): @@ -28,24 +34,24 @@ async def write(self, n): for i in range(n): self.dut.load_i = 1 self.dut.write_i = 1 - print(f"Load and Write at {get_sim_time('ns')} ns.") + self.dut.log.info(f"Load and Write at {get_sim_time('ns')} ns.") await Timer(clk_per*2, units="ns") self.dut.load_i = 0 self.dut.write_i = 0 await Timer(clk_per*256, units="ns") - print(f"Get cmd_ack at {get_sim_time('ns')} ns.") + self.dut.log.info(f"Get cmd_ack at {get_sim_time('ns')} ns.") await Timer(clk_per*750, units="ns") async def read(self, n): for i in range(n): self.dut.load_i = 1 self.dut.write_i = 0 - print(f"Load and Read at {get_sim_time('ns')} ns.") + self.dut.log.info(f"Load and Read at {get_sim_time('ns')} ns.") await Timer(clk_per*2, units="ns") self.dut.load_i = 0 self.dut.write_i = 0 await Timer(clk_per*256, units="ns") - print(f"Get cmd_ack at {get_sim_time('ns')} ns.") + self.dut.log.info(f"Get cmd_ack at {get_sim_time('ns')} ns.") await Timer(clk_per*1300, units="ns") @cocotb.test() diff --git a/sim/modelsim/cocotb/test.py b/sim/cocotb/test.py similarity index 97% rename from sim/modelsim/cocotb/test.py rename to sim/cocotb/test.py index ed64e91..7423511 100644 --- a/sim/modelsim/cocotb/test.py +++ b/sim/cocotb/test.py @@ -6,7 +6,7 @@ from cocotb.runner import get_runner def test_runner(): - src = Path("../../../src") + src = Path("../../src") hdl_toplevel_lang = os.getenv("HDL_TOPLEVEL_LANG", "verilog") sim = os.getenv("SIM", "questa") diff --git a/sim/modelsim/cocotb/wave.do b/sim/cocotb/wave.do similarity index 100% rename from sim/modelsim/cocotb/wave.do rename to sim/cocotb/wave.do diff --git a/sim/modelsim/hdlmake/Manifest.py b/sim/modelsim/Manifest.py similarity index 72% rename from sim/modelsim/hdlmake/Manifest.py rename to sim/modelsim/Manifest.py index f95ab81..e0641ad 100644 --- a/sim/modelsim/hdlmake/Manifest.py +++ b/sim/modelsim/Manifest.py @@ -13,6 +13,6 @@ ], } -mem_file_path = Path("../../../src") +mem_file_path = Path("../../src") -shutil.copyfile(mem_file_path / 'config.mem', 'config.mem') \ No newline at end of file +shutil.copyfile(mem_file_path / 'config.mem', 'config.mem') diff --git a/sim/modelsim/hdlmake/wave.do b/sim/modelsim/wave.do similarity index 100% rename from sim/modelsim/hdlmake/wave.do rename to sim/modelsim/wave.do diff --git a/sim/verilator/si5340_config_loader.sv b/sim/verilator/si5340_config_loader.sv deleted file mode 100644 index 18ea8c1..0000000 --- a/sim/verilator/si5340_config_loader.sv +++ /dev/null @@ -1,183 +0,0 @@ -// Status: Testing - -`include "cfg_pkg.svh" - -import cfg_pkg::*; - -module si5340_config_loader #( - parameter PAUSE_NS = 10 -) ( - input logic clk_i, - input logic arstn_i, - input logic load, - input logic write, - - // inout wire sda, // SCL-line - // inout wire scl // SDA-line - - // I2C - input scl_pad_i, // SCL-line input - output scl_pad_o, // SCL-line output (always 1'b0) - output scl_padoen_o, // SCL-line output enable (active low) - input sda_pad_i, // SDA-line input - output sda_pad_o, // SDA-line output (always 1'b0) - output sda_padoen_o // SDA-line output enable (active low) -); - - // wire scl_pad_i; // SCL-line input - // wire scl_pad_o; // SCL-line output (always 1'b0) - // wire scl_padoen_o; // SCL-line output enable (active low) - // wire sda_pad_i; // SDA-line input - // wire sda_pad_o; // SDA-line output (always 1'b0) - // wire sda_padoen_o; // SDA-line output enable (active low) - - // assign scl_pad_i = scl; - // assign sda_pad_i = sda; - // assign scl = scl_padoen_o ? 1'bz : scl_pad_o; - // assign sda = sda_padoen_o ? 1'bz : sda_pad_o; - - i2_ctrl_if s_i2_ctrl_if(); - - i2c_master_byte_ctrl i2c_inst ( - .clk (clk_i ), - .rst (0 ), - .nReset (arstn_i ), - .ena (1 ), - .clk_cnt (CLK_CNT ), - .start (s_i2_ctrl_if.start ), - .stop (s_i2_ctrl_if.stop ), - .read (s_i2_ctrl_if.read ), - .write (s_i2_ctrl_if.write ), - .ack_in (s_i2_ctrl_if.ack_in ), - .din (s_i2_ctrl_if.din ), - .cmd_ack (s_i2_ctrl_if.cmd_ack), - .ack_out ( ), - .i2c_busy( ), - .i2c_al ( ), - .dout (s_i2_ctrl_if.dout ), - .scl_i (scl_pad_i ), - .scl_o (scl_pad_o ), - .sda_i (sda_pad_i ), - .sda_o (sda_pad_o ), - .scl_oen (scl_padoen_o ), - .sda_oen (sda_padoen_o ) - ); - - localparam QUEUE_WIDTH = 6; - localparam QUEUE_LEN = $clog2(QUEUE_WIDTH); - - logic [QUEUE_LEN-1:0] queue_index; - logic [QUEUE_LEN-1:0] queue_len; - - logic [$clog2(PAUSE_NS)-1:0 ] pause_cnt; - logic [$clog2(MEM_DEPTH)-1:0] mem_index; - - logic [MEM_WIDTH-1:0] mem [MEM_DEPTH-1:0]; // [23:8] - addr, [7:0] - data - - struct packed { - logic [DATA_WIDTH-1:0] data; - r_w rw; - logic start; - logic stop; - } queue [QUEUE_WIDTH-1:0]; - - enum logic [2:0] { - IDLE = 3'b000, - ACK = 3'b001, - WAIT_ACK = 3'b010, - PAUSE = 3'b011, - QUEUE_INDEX = 3'b100, - MEM_INDEX = 3'b101, - STOP = 3'b110, - WAIT_STOP = 3'b111 - } state; - - initial $readmemh(CONFIG_MEM, mem); - - always_ff @(posedge clk_i or negedge arstn_i) begin - if (~arstn_i) begin - pause_cnt <= 0; - mem_index <= 0; - queue_index <= 0; - state <= IDLE; - end else begin - case (state) - IDLE: if (load) state <= ACK; - else state <= IDLE; - ACK: state <= WAIT_ACK; - WAIT_ACK: if (s_i2_ctrl_if.cmd_ack) begin - if (queue[queue_index].stop) state <= STOP; - else state <= PAUSE; - end - PAUSE: if (pause_cnt == PAUSE_NS) begin - pause_cnt <= 0; - state <= QUEUE_INDEX; - end else begin - pause_cnt <= pause_cnt + 1; - state <= PAUSE; - end - MEM_INDEX: begin - state <= IDLE; - if (mem_index == MEM_DEPTH - 1) mem_index <= 0; - else mem_index <= mem_index + 1; - end - QUEUE_INDEX: if (queue_index == queue_len) begin - queue_index <= 0; - state <= MEM_INDEX; - end else begin - queue_index <= queue_index + 1; - state <= ACK; - end - STOP: state <= WAIT_STOP; - WAIT_STOP: if (s_i2_ctrl_if.cmd_ack) state <= QUEUE_INDEX; - else state <= WAIT_STOP; - default: state <= IDLE; - endcase - end - end - - always_comb begin - s_i2_ctrl_if.din = queue[queue_index].data; - if (state == ACK || state == STOP) s_i2_ctrl_if.ack_in = 1; - else s_i2_ctrl_if.ack_in = 0; - if (state == ACK && queue[queue_index].start) s_i2_ctrl_if.start = 1; - else s_i2_ctrl_if.start = 0; - if (state == STOP && queue[queue_index].stop) s_i2_ctrl_if.stop = 1; - else s_i2_ctrl_if.stop = 0; - if (state == ACK && queue[queue_index].rw == READ) s_i2_ctrl_if.read = 1; - else s_i2_ctrl_if.read = 0; - if (state == ACK && queue[queue_index].rw == WRITE) s_i2_ctrl_if.write = 1; - else s_i2_ctrl_if.write = 0; - end - - always_ff @(posedge clk_i) begin - if (~arstn_i) queue_len <= 0; - else if (state == IDLE && load) begin - if (write) begin // Write - queue[0] <= {{SLAVE_ADDR, WRITE}, WRITE, 1'b1, 1'b0}; - queue[1] <= {mem[mem_index][(CYCLES-1)*DATA_WIDTH +: DATA_WIDTH], WRITE, 1'b0, 1'b0}; // [23:16] - addr - queue[2] <= {mem[mem_index][(CYCLES-2)*DATA_WIDTH +: DATA_WIDTH], WRITE, 1'b0, 1'b0}; // [15:8] - addr - queue[3] <= {mem[mem_index][(CYCLES-3)*DATA_WIDTH +: DATA_WIDTH], WRITE, 1'b0, 1'b1}; // [7:0] - data - queue_len <= QUEUE_WIDTH - 3; - end else begin // Read - queue[0] <= {{SLAVE_ADDR, WRITE}, WRITE, 1'b1, 1'b0}; - queue[1] <= {mem[mem_index][(CYCLES-1)*DATA_WIDTH +: DATA_WIDTH], WRITE, 1'b0, 1'b0}; // [23:16] - addr - queue[2] <= {{SLAVE_ADDR, WRITE}, WRITE, 1'b1, 1'b0}; - queue[3] <= {mem[mem_index][(CYCLES-2)*DATA_WIDTH +: DATA_WIDTH], WRITE, 1'b0, 1'b1}; // [15:8] - addr - queue[4] <= {{SLAVE_ADDR, READ}, WRITE, 1'b1, 1'b0}; - queue[5] <= {mem[mem_index][(CYCLES-3)*DATA_WIDTH +: DATA_WIDTH], READ, 1'b0, 1'b1}; // [7:0] - data - queue_len <= QUEUE_WIDTH - 1; - end - end - end - - `ifdef COCOTB_SIM - initial begin - $dumpfile ("si5340_config_loader.vcd"); - $dumpvars (0, si5340_config_loader); - // verilator lint_off STMTDLY - #1; - end - `endif - -endmodule diff --git a/sim/verilator/si5340_config_loader_tb.py b/sim/verilator/si5340_config_loader_tb.py deleted file mode 100644 index c093eae..0000000 --- a/sim/verilator/si5340_config_loader_tb.py +++ /dev/null @@ -1,50 +0,0 @@ -import cocotb -import random -from cocotb.clock import Clock -from cocotb.triggers import Timer, RisingEdge, FallingEdge, ClockCycles -from cocotb.utils import get_sim_time - -clk_per = 8 - -async def reset(dut, cycles): - dut.arstn_i.value = 0 - await ClockCycles(dut.clk_i, cycles) - dut.arstn_i.value = 1 - -async def write(dut, n): - for i in range(n): - dut.load = 1 - dut.write = 1 - print(f"Load and Write at {get_sim_time('ns')} ns.") - await Timer(clk_per*2, units="ns") - dut.load = 0 - dut.write = 0 - await Timer(clk_per*256, units="ns") - print(f"Get cmd_ack at {get_sim_time('ns')} ns.") - await Timer(clk_per*750, units="ns") - -async def read(dut, n): - for i in range(n): - dut.load = 1 - dut.write = 0 - print(f"Load and Read at {get_sim_time('ns')} ns.") - await Timer(clk_per*2, units="ns") - dut.load = 0 - dut.write = 0 - await Timer(clk_per*256, units="ns") - print(f"Get cmd_ack at {get_sim_time('ns')} ns.") - await Timer(clk_per*1300, units="ns") - -async def init(dut): - - cocotb.start_soon(Clock(dut.clk_i, clk_per, units = 'ns').start()) - - await reset(dut, 2) - await read(dut, 1) - await write(dut, 1) - -@cocotb.test() -async def test_si5340_config_loader(dut): - - #------------------Order of test execution ------------------- - await init(dut) diff --git a/sim/verilator/test.py b/sim/verilator/test.py deleted file mode 100644 index 9863a23..0000000 --- a/sim/verilator/test.py +++ /dev/null @@ -1,57 +0,0 @@ -import os -import shutil -from pathlib import Path - -import cocotb -from cocotb.runner import get_runner - -def test_runner(): - src = Path("../../src") - - hdl_toplevel_lang = os.getenv("HDL_TOPLEVEL_LANG", "verilog") - sim = os.getenv("SIM", "verilator") - - build_dir = Path('sim_si5340_config_loader') - build_dir.mkdir(exist_ok=True) - - shutil.copyfile(src / 'config.mem', build_dir / 'config.mem') - shutil.copyfile(src / 'cfg_pkg.svh', build_dir / 'cfg_pkg.svh') - shutil.copyfile(src / 'timescale.v', build_dir / 'timescale.v') - shutil.copyfile(src / 'i2c_master_defines.v', build_dir / 'i2c_master_defines.v') - - verilog_sources = [ - src / "cfg_pkg.svh", - src / "i2c_ctrl_if.sv", - src / "i2c_master_bit_ctrl.v", - src / "i2c_master_byte_ctrl.v", - src / "i2c_master_byte_ctrl.v", - src / "i2c_master_defines.v", - src / "timescale.v", - "si5340_config_loader.sv", - ] - - hdl_toplevel = 'si5340_config_loader' # HDL module name - test_module = 'si5340_config_loader_tb' # Python module name - # pre_cmd = ['do ../wave.do'] # Macro file - # parameters = {"PAUSE_NS": "10"} # HDL module parameters - build_args = ['--no-timing', '--assert', '-Wno-MODDUP'] - - runner = get_runner(sim) - - runner.build( - verilog_sources=verilog_sources, - hdl_toplevel=hdl_toplevel, - build_dir=build_dir, - always=True, # Always rebuild project - build_args=build_args, - ) - - runner.test( - hdl_toplevel=hdl_toplevel, - test_module=test_module, - waves=True, - gui=True, - # pre_cmd=pre_cmd, - # parameters=parameters, - ) - diff --git a/src/gtkw.gtkw b/src/gtkw.gtkw index 4d15695..519de1b 100644 --- a/src/gtkw.gtkw +++ b/src/gtkw.gtkw @@ -1,181 +1,188 @@ [*] -[*] GTKWave Analyzer v3.3.116 (w)1999-2023 BSI -[*] Thu Nov 7 17:24:54 2024 +[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI +[*] Fri Dec 20 20:07:51 2024 [*] -[dumpfile] "/home/rds/fpga/my_projects/si5340-config-loader/sim/verilator/si5340_config_loader_tb.vcd" -[dumpfile_mtime] "Thu Nov 7 17:21:16 2024" -[dumpfile_size] 135107 -[savefile] "/home/rds/fpga/my_projects/si5340-config-loader/sim/verilator/gtkw.gtkw" +[dumpfile] "/home/rds/fpga/my_projects/si5340-config-loader/src/si5340_config_loader_tb.vcd" +[dumpfile_mtime] "Fri Dec 20 20:06:30 2024" +[dumpfile_size] 135092 +[savefile] "/home/rds/fpga/my_projects/si5340-config-loader/src/gtkw.gtkw" [timestart] 0 -[size] 1920 927 -[pos] -27 -24 -*-21.494638 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[size] 1920 1000 +[pos] -103 -103 +*-21.498796 -1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +[treeopen] si5340_config_loader_tb. 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+si5340_config_loader_tb.dut.i2c_inst.bit_controller.ena +si5340_config_loader_tb.dut.i2c_inst.bit_controller.fSCL[2:0] +si5340_config_loader_tb.dut.i2c_inst.bit_controller.fSDA[2:0] +@22 +si5340_config_loader_tb.dut.i2c_inst.bit_controller.filter_cnt[13:0] +si5340_config_loader_tb.dut.i2c_inst.bit_controller.idle[17:0] @28 -TOP.si5340_config_loader_tb.dut.arstn_i -TOP.si5340_config_loader_tb.dut.clk_i -@22 -TOP.si5340_config_loader_tb.dut.i2c_inst.ST_ACK[4:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.ST_IDLE[4:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.ST_READ[4:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.ST_START[4:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.ST_STOP[4:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.ST_WRITE[4:0] -@28 -TOP.si5340_config_loader_tb.dut.i2c_inst.ack_in -TOP.si5340_config_loader_tb.dut.i2c_inst.ack_out -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.al -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.busy -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.cSCL[1:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.cSDA[1:0] -@22 -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.c_state[17:0] -@28 -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.clk -@22 -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.clk_cnt[15:0] -@28 -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.clk_en -@22 -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.cmd[3:0] -@28 -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.cmd_ack -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.cmd_stop -@22 -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.cnt[15:0] -@28 -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.dSCL -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.dSDA -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.din -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.dout -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.dscl_oen -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.ena -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.fSCL[2:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.fSDA[2:0] -@22 -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.filter_cnt[13:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.idle[17:0] -@28 -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.nReset -@22 -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.rd_a[17:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.rd_b[17:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.rd_c[17:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.rd_d[17:0] -@28 -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.rst -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.sSCL -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.sSDA -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.scl_i -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.scl_o -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.scl_oen -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.scl_sync -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.sda_chk -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.sda_i -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.sda_o -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.sda_oen -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.slave_wait -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.sta_condition -@22 -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.start_a[17:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.start_b[17:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.start_c[17:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.start_d[17:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.start_e[17:0] -@28 -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.sto_condition -@22 -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.stop_a[17:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.stop_b[17:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.stop_c[17:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.stop_d[17:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.wr_a[17:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.wr_b[17:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.wr_c[17:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.bit_controller.wr_d[17:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.c_state[4:0] -@28 -TOP.si5340_config_loader_tb.dut.i2c_inst.clk -@22 -TOP.si5340_config_loader_tb.dut.i2c_inst.clk_cnt[15:0] -@28 -TOP.si5340_config_loader_tb.dut.i2c_inst.cmd_ack -TOP.si5340_config_loader_tb.dut.i2c_inst.cnt_done -TOP.si5340_config_loader_tb.dut.i2c_inst.core_ack -@22 -TOP.si5340_config_loader_tb.dut.i2c_inst.core_cmd[3:0] -@28 -TOP.si5340_config_loader_tb.dut.i2c_inst.core_rxd -TOP.si5340_config_loader_tb.dut.i2c_inst.core_txd -TOP.si5340_config_loader_tb.dut.i2c_inst.dcnt[2:0] -@22 -TOP.si5340_config_loader_tb.dut.i2c_inst.din[7:0] -TOP.si5340_config_loader_tb.dut.i2c_inst.dout[7:0] -@28 -TOP.si5340_config_loader_tb.dut.i2c_inst.ena -TOP.si5340_config_loader_tb.dut.i2c_inst.go -TOP.si5340_config_loader_tb.dut.i2c_inst.i2c_al -TOP.si5340_config_loader_tb.dut.i2c_inst.i2c_busy -TOP.si5340_config_loader_tb.dut.i2c_inst.ld -TOP.si5340_config_loader_tb.dut.i2c_inst.nReset -TOP.si5340_config_loader_tb.dut.i2c_inst.read -TOP.si5340_config_loader_tb.dut.i2c_inst.rst -TOP.si5340_config_loader_tb.dut.i2c_inst.scl_i -TOP.si5340_config_loader_tb.dut.i2c_inst.scl_o -TOP.si5340_config_loader_tb.dut.i2c_inst.scl_oen -TOP.si5340_config_loader_tb.dut.i2c_inst.sda_i -TOP.si5340_config_loader_tb.dut.i2c_inst.sda_o -TOP.si5340_config_loader_tb.dut.i2c_inst.sda_oen -TOP.si5340_config_loader_tb.dut.i2c_inst.shift -@22 -TOP.si5340_config_loader_tb.dut.i2c_inst.sr[7:0] -@28 -TOP.si5340_config_loader_tb.dut.i2c_inst.start -TOP.si5340_config_loader_tb.dut.i2c_inst.stop -TOP.si5340_config_loader_tb.dut.i2c_inst.write -TOP.si5340_config_loader_tb.dut.load_i -@22 -TOP.si5340_config_loader_tb.dut.mem_index[8:0] -TOP.si5340_config_loader_tb.dut.pause_cnt[3:0] -TOP.si5340_config_loader_tb.dut.queue[0][10:0] -TOP.si5340_config_loader_tb.dut.queue[1][10:0] -TOP.si5340_config_loader_tb.dut.queue[2][10:0] -TOP.si5340_config_loader_tb.dut.queue[3][10:0] -TOP.si5340_config_loader_tb.dut.queue[4][10:0] -TOP.si5340_config_loader_tb.dut.queue[5][10:0] -@28 -TOP.si5340_config_loader_tb.dut.queue_index[2:0] -TOP.si5340_config_loader_tb.dut.queue_len[2:0] -TOP.si5340_config_loader_tb.dut.s_i2_ctrl_if.ack_in -TOP.si5340_config_loader_tb.dut.s_i2_ctrl_if.cmd_ack -@22 -TOP.si5340_config_loader_tb.dut.s_i2_ctrl_if.din[7:0] -TOP.si5340_config_loader_tb.dut.s_i2_ctrl_if.dout[7:0] -@28 -TOP.si5340_config_loader_tb.dut.s_i2_ctrl_if.read -TOP.si5340_config_loader_tb.dut.s_i2_ctrl_if.start -TOP.si5340_config_loader_tb.dut.s_i2_ctrl_if.stop -TOP.si5340_config_loader_tb.dut.s_i2_ctrl_if.write -TOP.si5340_config_loader_tb.dut.scl_pad_i -TOP.si5340_config_loader_tb.dut.scl_pad_o -TOP.si5340_config_loader_tb.dut.scl_padoen_o -TOP.si5340_config_loader_tb.dut.sda_pad_i -TOP.si5340_config_loader_tb.dut.sda_pad_o -TOP.si5340_config_loader_tb.dut.sda_padoen_o -TOP.si5340_config_loader_tb.dut.state[2:0] -TOP.si5340_config_loader_tb.dut.write_i -TOP.si5340_config_loader_tb.dut_if.arstn_i -TOP.si5340_config_loader_tb.dut_if.clk_i -TOP.si5340_config_loader_tb.dut_if.load_i -TOP.si5340_config_loader_tb.dut_if.scl_pad_i -TOP.si5340_config_loader_tb.dut_if.scl_pad_o -TOP.si5340_config_loader_tb.dut_if.scl_padoen_o -TOP.si5340_config_loader_tb.dut_if.sda_pad_i -TOP.si5340_config_loader_tb.dut_if.sda_pad_o -TOP.si5340_config_loader_tb.dut_if.sda_padoen_o -TOP.si5340_config_loader_tb.dut_if.write_i +si5340_config_loader_tb.dut.i2c_inst.bit_controller.nReset +@22 +si5340_config_loader_tb.dut.i2c_inst.bit_controller.rd_a[17:0] +si5340_config_loader_tb.dut.i2c_inst.bit_controller.rd_b[17:0] +si5340_config_loader_tb.dut.i2c_inst.bit_controller.rd_c[17:0] +si5340_config_loader_tb.dut.i2c_inst.bit_controller.rd_d[17:0] +@28 +si5340_config_loader_tb.dut.i2c_inst.bit_controller.rst +si5340_config_loader_tb.dut.i2c_inst.bit_controller.sSCL +si5340_config_loader_tb.dut.i2c_inst.bit_controller.sSDA +si5340_config_loader_tb.dut.i2c_inst.bit_controller.scl_i +si5340_config_loader_tb.dut.i2c_inst.bit_controller.scl_o +si5340_config_loader_tb.dut.i2c_inst.bit_controller.scl_oen +si5340_config_loader_tb.dut.i2c_inst.bit_controller.scl_sync +si5340_config_loader_tb.dut.i2c_inst.bit_controller.sda_chk +si5340_config_loader_tb.dut.i2c_inst.bit_controller.sda_i +si5340_config_loader_tb.dut.i2c_inst.bit_controller.sda_o +si5340_config_loader_tb.dut.i2c_inst.bit_controller.sda_oen +si5340_config_loader_tb.dut.i2c_inst.bit_controller.slave_wait +si5340_config_loader_tb.dut.i2c_inst.bit_controller.sta_condition +@22 +si5340_config_loader_tb.dut.i2c_inst.bit_controller.start_a[17:0] +si5340_config_loader_tb.dut.i2c_inst.bit_controller.start_b[17:0] +si5340_config_loader_tb.dut.i2c_inst.bit_controller.start_c[17:0] +si5340_config_loader_tb.dut.i2c_inst.bit_controller.start_d[17:0] +si5340_config_loader_tb.dut.i2c_inst.bit_controller.start_e[17:0] +@28 +si5340_config_loader_tb.dut.i2c_inst.bit_controller.sto_condition +@22 +si5340_config_loader_tb.dut.i2c_inst.bit_controller.stop_a[17:0] +si5340_config_loader_tb.dut.i2c_inst.bit_controller.stop_b[17:0] +si5340_config_loader_tb.dut.i2c_inst.bit_controller.stop_c[17:0] +si5340_config_loader_tb.dut.i2c_inst.bit_controller.stop_d[17:0] +si5340_config_loader_tb.dut.i2c_inst.bit_controller.wr_a[17:0] +si5340_config_loader_tb.dut.i2c_inst.bit_controller.wr_b[17:0] +si5340_config_loader_tb.dut.i2c_inst.bit_controller.wr_c[17:0] +si5340_config_loader_tb.dut.i2c_inst.bit_controller.wr_d[17:0] +si5340_config_loader_tb.dut.i2c_inst.c_state[4:0] +@28 +si5340_config_loader_tb.dut.i2c_inst.clk +@22 +si5340_config_loader_tb.dut.i2c_inst.clk_cnt[15:0] +@28 +si5340_config_loader_tb.dut.i2c_inst.cmd_ack +si5340_config_loader_tb.dut.i2c_inst.cnt_done +si5340_config_loader_tb.dut.i2c_inst.core_ack +@22 +si5340_config_loader_tb.dut.i2c_inst.core_cmd[3:0] +@28 +si5340_config_loader_tb.dut.i2c_inst.core_rxd +si5340_config_loader_tb.dut.i2c_inst.core_txd +si5340_config_loader_tb.dut.i2c_inst.dcnt[2:0] +@22 +si5340_config_loader_tb.dut.i2c_inst.din[7:0] +si5340_config_loader_tb.dut.i2c_inst.dout[7:0] +@28 +si5340_config_loader_tb.dut.i2c_inst.ena +si5340_config_loader_tb.dut.i2c_inst.go +si5340_config_loader_tb.dut.i2c_inst.i2c_al +si5340_config_loader_tb.dut.i2c_inst.i2c_busy +si5340_config_loader_tb.dut.i2c_inst.ld +si5340_config_loader_tb.dut.i2c_inst.nReset +si5340_config_loader_tb.dut.i2c_inst.read +si5340_config_loader_tb.dut.i2c_inst.rst +si5340_config_loader_tb.dut.i2c_inst.scl_i +si5340_config_loader_tb.dut.i2c_inst.scl_o +si5340_config_loader_tb.dut.i2c_inst.scl_oen +si5340_config_loader_tb.dut.i2c_inst.sda_i +si5340_config_loader_tb.dut.i2c_inst.sda_o +si5340_config_loader_tb.dut.i2c_inst.sda_oen +si5340_config_loader_tb.dut.i2c_inst.shift +@22 +si5340_config_loader_tb.dut.i2c_inst.sr[7:0] +@28 +si5340_config_loader_tb.dut.i2c_inst.start +si5340_config_loader_tb.dut.i2c_inst.stop +si5340_config_loader_tb.dut.i2c_inst.write +si5340_config_loader_tb.dut.load_i +@22 +si5340_config_loader_tb.dut.mem_index[8:0] +si5340_config_loader_tb.dut.pause_cnt[3:0] +si5340_config_loader_tb.dut.queue[0][10:0] +si5340_config_loader_tb.dut.queue[1][10:0] +si5340_config_loader_tb.dut.queue[2][10:0] +si5340_config_loader_tb.dut.queue[3][10:0] +si5340_config_loader_tb.dut.queue[4][10:0] +si5340_config_loader_tb.dut.queue[5][10:0] +@28 +si5340_config_loader_tb.dut.queue_index[2:0] +si5340_config_loader_tb.dut.queue_len[2:0] +si5340_config_loader_tb.dut.s_i2_ctrl_if.ack_in +si5340_config_loader_tb.dut.s_i2_ctrl_if.cmd_ack +@22 +si5340_config_loader_tb.dut.s_i2_ctrl_if.din[7:0] +si5340_config_loader_tb.dut.s_i2_ctrl_if.dout[7:0] +@28 +si5340_config_loader_tb.dut.s_i2_ctrl_if.read +si5340_config_loader_tb.dut.s_i2_ctrl_if.start +si5340_config_loader_tb.dut.s_i2_ctrl_if.stop +si5340_config_loader_tb.dut.s_i2_ctrl_if.write +si5340_config_loader_tb.dut.scl_pad_i +si5340_config_loader_tb.dut.scl_pad_o +si5340_config_loader_tb.dut.scl_padoen_o +si5340_config_loader_tb.dut.sda_pad_i +si5340_config_loader_tb.dut.sda_pad_o +si5340_config_loader_tb.dut.sda_padoen_o +si5340_config_loader_tb.dut.state[2:0] +si5340_config_loader_tb.dut.write_i +si5340_config_loader_tb.dut_if.arstn_i +si5340_config_loader_tb.dut_if.clk_i +si5340_config_loader_tb.dut_if.load_i +si5340_config_loader_tb.dut_if.scl_pad_i +si5340_config_loader_tb.dut_if.scl_pad_o +si5340_config_loader_tb.dut_if.scl_padoen_o +si5340_config_loader_tb.dut_if.sda_pad_i +si5340_config_loader_tb.dut_if.sda_pad_o +si5340_config_loader_tb.dut_if.sda_padoen_o +si5340_config_loader_tb.dut_if.write_i [pattern_trace] 1 [pattern_trace] 0