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to_verilog("file.v") creates two empty lines at beginning of file #44

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kiteloopdesign opened this issue May 18, 2021 · 0 comments

kiteloopdesign commented May 18, 2021

Verilog output file has two empty lines before the module keyword

('\n'
 '\n'
 'module blinkled #\n'
 '(\n'
 '  parameter WIDTH = 8\n'
 ')\n'
 '(\n'
 '  input CLK,\n'
 '  input RST,\n'
 '  output reg [WIDTH-1:0] LED\n'
 ');\n'

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