From 983f42c9c519c2a053d7fcc5e57cf8574d38d059 Mon Sep 17 00:00:00 2001 From: shtaxxx Date: Tue, 26 Nov 2019 11:40:55 +0900 Subject: [PATCH 01/13] PyPI document as Markdown --- Makefile | 6 +- README.rst | 517 ----------------------------------------------------- setup.py | 3 +- 3 files changed, 5 insertions(+), 521 deletions(-) delete mode 100644 README.rst diff --git a/Makefile b/Makefile index 8b565b5..27d13a5 100644 --- a/Makefile +++ b/Makefile @@ -15,6 +15,6 @@ clean: make clean -C ./tests rm -rf *.egg-info build dist *.pyc __pycache__ parsetab.py .cache tmp.v uut.vcd *.out *.png *.dot -.PHONY: release -release: - pandoc README.md -t rst > README.rst +#.PHONY: release +#release: +# pandoc README.md -t rst > README.rst diff --git a/README.rst b/README.rst deleted file mode 100644 index 231321a..0000000 --- a/README.rst +++ /dev/null @@ -1,517 +0,0 @@ -Pyverilog -========= - -|Build Status| - -Python-based Hardware Design Processing Toolkit for Verilog HDL - -Copyright 2013, Shinya Takamaeda-Yamazaki and Contributors - -License -======= - -Apache License 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - -Note that this software package includes PLY-3.4 in “vparser/ply”. The -license of PLY is BSD. - -Publication -=========== - -If you use Pyverilog in your research, please cite the following paper. - -- Shinya Takamaeda-Yamazaki: Pyverilog: A Python-based Hardware Design - Processing Toolkit for Verilog HDL, 11th International Symposium on - Applied Reconfigurable Computing (ARC 2015) (Poster), Lecture Notes - in Computer Science, Vol.9040/2015, pp.451-460, April 2015. - `Paper `__ - -:: - - @inproceedings{Takamaeda:2015:ARC:Pyverilog, - title={Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL}, - author={Takamaeda-Yamazaki, Shinya}, - booktitle={Applied Reconfigurable Computing}, - month={Apr}, - year={2015}, - pages={451-460}, - volume={9040}, - series={Lecture Notes in Computer Science}, - publisher={Springer International Publishing}, - doi={10.1007/978-3-319-16214-0_42}, - url={http://dx.doi.org/10.1007/978-3-319-16214-0_42}, - } - -What’s Pyverilog? -================= - -Pyverilog is an open-source hardware design processing toolkit for -Verilog HDL. All source codes are written in Python. - -Pyverilog includes **(1) code parser, (2) dataflow analyzer, (3) -control-flow analyzer and (4) code generator**. You can create your own -design analyzer, code translator and code generator of Verilog HDL based -on this toolkit. - -Contribute to Pyverilog -======================= - -Pyverilog project always welcomes questions, bug reports, feature -proposals, and pull requests on -`GitHub `__. - -for questions, bug reports, and feature proposals -------------------------------------------------- - -Please leave your comment on the `issue -tracker `__ on GitHub. - -for pull requests ------------------ - -Please check “CONTRIBUTORS.md” for the contributors who provided pull -requests. - -Pyverilog uses **pytest** for the integration testing. **When you send a -pull request, please include a testing example with pytest.** To write a -testing code, please refer the existing testing examples in “tests” -directory. - -If the pull request code passes all the tests successfully and has no -obvious problem, it will be merged to the *develop* branch by the main -committers. - -Installation -============ - -Requirements ------------- - -- Python3: 3.6 or later -- Icarus Verilog: 10.1 or later - -:: - - sudo apt install iverilog - -- Jinja2: 2.10 or later - -:: - - pip3 install jinja2 - -Optional installation for testing ---------------------------------- - -These are required for automatic testing of **tests**. We recommend to -install these testing library to verify experimental features. - -- pytest: 3.8.1 or later -- pytest-pythonpath: 0.7.3 or later - -:: - - pip3 install pytest pytest-pythonpath - -Optional installation for visualization ---------------------------------------- - -These are required for graph visualization by dataflow/graphgen.py and -controlflow/controlflow_analyzer.py. - -- Graphviz: 2.38.0 or later -- Pygraphviz: 1.3.1 or later - -:: - - sudo apt install graphviz - pip3 install pygraphviz - -Install -------- - -Now you can install Pyverilog using setup.py script: - -:: - - python3 setup.py install - -Tools -===== - -This software includes various tools for Verilog HDL design. - -- vparser: Code parser to generate AST (Abstract Syntax Tree) from - source codes of Verilog HDL. -- dataflow: Dataflow analyzer with an optimizer to remove redundant - expressions and some dataflow handling tools. -- controlflow: Control-flow analyzer with condition analyzer that - identify when a signal is activated. -- ast_code_generator: Verilog HDL code generator from AST. - -Getting Started -=============== - -First, please prepare a Verilog HDL source file as below. The file name -is ‘test.v’. This sample design adds the input value internally whtn the -enable signal is asserted. Then is outputs its partial value to the LED. - -.. code:: verilog - - module top - ( - input CLK, - input RST, - input enable, - input [31:0] value, - output [7:0] led - ); - reg [31:0] count; - reg [7:0] state; - assign led = count[23:16]; - always @(posedge CLK) begin - if(RST) begin - count <= 0; - state <= 0; - end else begin - if(state == 0) begin - if(enable) state <= 1; - end else if(state == 1) begin - state <= 2; - end else if(state == 2) begin - count <= count + value; - state <= 0; - end - end - end - endmodule - -Code parser ------------ - -Let’s try syntax analysis. Please type the command as below. - -:: - - python3 pyverilog/examples/example_parser.py test.v - -Then you got the result as below. The result of syntax analysis is -displayed. - -:: - - Source: (at 1) - Description: (at 1) - ModuleDef: top (at 1) - Paramlist: (at 0) - Portlist: (at 2) - Ioport: (at 3) - Input: CLK, False (at 3) - Ioport: (at 4) - Input: RST, False (at 4) - Ioport: (at 5) - Input: enable, False (at 5) - Ioport: (at 6) - Input: value, False (at 6) - Width: (at 6) - IntConst: 31 (at 6) - IntConst: 0 (at 6) - Ioport: (at 7) - Output: led, False (at 7) - Width: (at 7) - IntConst: 7 (at 7) - IntConst: 0 (at 7) - Decl: (at 9) - Reg: count, False (at 9) - Width: (at 9) - IntConst: 31 (at 9) - IntConst: 0 (at 9) - Decl: (at 10) - Reg: state, False (at 10) - Width: (at 10) - IntConst: 7 (at 10) - IntConst: 0 (at 10) - Assign: (at 11) - Lvalue: (at 11) - Identifier: led (at 11) - Rvalue: (at 11) - Partselect: (at 11) - Identifier: count (at 11) - IntConst: 23 (at 11) - IntConst: 16 (at 11) - Always: (at 12) - SensList: (at 12) - Sens: posedge (at 12) - Identifier: CLK (at 12) - Block: None (at 12) - IfStatement: (at 13) - Identifier: RST (at 13) - Block: None (at 13) - NonblockingSubstitution: (at 14) - Lvalue: (at 14) - Identifier: count (at 14) - Rvalue: (at 14) - IntConst: 0 (at 14) - NonblockingSubstitution: (at 15) - Lvalue: (at 15) - Identifier: state (at 15) - Rvalue: (at 15) - IntConst: 0 (at 15) - Block: None (at 16) - IfStatement: (at 17) - Eq: (at 17) - Identifier: state (at 17) - IntConst: 0 (at 17) - Block: None (at 17) - IfStatement: (at 18) - Identifier: enable (at 18) - NonblockingSubstitution: (at 18) - Lvalue: (at 18) - Identifier: state (at 18) - Rvalue: (at 18) - IntConst: 1 (at 18) - IfStatement: (at 19) - Eq: (at 19) - Identifier: state (at 19) - IntConst: 1 (at 19) - Block: None (at 19) - NonblockingSubstitution: (at 20) - Lvalue: (at 20) - Identifier: state (at 20) - Rvalue: (at 20) - IntConst: 2 (at 20) - IfStatement: (at 21) - Eq: (at 21) - Identifier: state (at 21) - IntConst: 2 (at 21) - Block: None (at 21) - NonblockingSubstitution: (at 22) - Lvalue: (at 22) - Identifier: count (at 22) - Rvalue: (at 22) - Plus: (at 22) - Identifier: count (at 22) - Identifier: value (at 22) - NonblockingSubstitution: (at 23) - Lvalue: (at 23) - Identifier: state (at 23) - Rvalue: (at 23) - IntConst: 0 (at 23) - -Dataflow analyzer ------------------ - -Let’s try dataflow analysis. Please type the command as below. - -:: - - python3 pyverilog/examples/example_dataflow_analyzer.py -t top test.v - -Then you got the result as below. The result of each signal definition -and each signal assignment are displayed. - -:: - - Directive: - Instance: - (top, 'top') - Term: - (Term name:top.led type:{'Output'} msb:(IntConst 7) lsb:(IntConst 0)) - (Term name:top.enable type:{'Input'} msb:(IntConst 0) lsb:(IntConst 0)) - (Term name:top.CLK type:{'Input'} msb:(IntConst 0) lsb:(IntConst 0)) - (Term name:top.count type:{'Reg'} msb:(IntConst 31) lsb:(IntConst 0)) - (Term name:top.state type:{'Reg'} msb:(IntConst 7) lsb:(IntConst 0)) - (Term name:top.RST type:{'Input'} msb:(IntConst 0) lsb:(IntConst 0)) - (Term name:top.value type:{'Input'} msb:(IntConst 31) lsb:(IntConst 0)) - Bind: - (Bind dest:top.count tree:(Branch Cond:(Terminal top.RST) True:(IntConst 0) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 0)) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 1)) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 2)) True:(Operator Plus Next:(Terminal top.count),(Terminal top.value))))))) - (Bind dest:top.state tree:(Branch Cond:(Terminal top.RST) True:(IntConst 0) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 0)) True:(Branch Cond:(Terminal top.enable) True:(IntConst 1)) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 1)) True:(IntConst 2) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 2)) True:(IntConst 0)))))) - (Bind dest:top.led tree:(Partselect Var:(Terminal top.count) MSB:(IntConst 23) LSB:(IntConst 16))) - -Let’s view the result of dataflow analysis as a picture file. Now we -select ‘led’ as the target. Please type the command as below. In this -example, Graphviz and Pygraphviz are installed. - -:: - - python3 pyverilog/examples/example_graphgen.py -t top -s top.led test.v - -Then you got a png file (out.png). The picture shows that the definition -of ‘led’ is a part-selection of ‘count’ from 23-bit to 16-bit. - -.. figure:: img/out.png - :alt: out.png - - out.png - -Control-flow analyzer ---------------------- - -Let’s try control-flow analysis. Please type the command as below. In -this example, Graphviz and Pygraphviz are installed. If don’t use -Graphviz, please append “–nograph” option. - -:: - - python3 pyverilog/examples/example_controlflow_analyzer.py -t top test.v - -Then you got the result as below. The result shows that the state -machine structure and transition conditions to the next state in the -state machine. - -:: - - FSM signal: top.count, Condition list length: 4 - FSM signal: top.state, Condition list length: 5 - Condition: (Ulnot, Eq), Inferring transition condition - Condition: (Eq, top.enable), Inferring transition condition - Condition: (Ulnot, Ulnot, Eq), Inferring transition condition - # SIGNAL NAME: top.state - # DELAY CNT: 0 - 0 --(top_enable>'d0)--> 1 - 1 --None--> 2 - 2 --None--> 0 - Loop - (0, 1, 2) - -You got also a png file (top_state.png), if you did not append -“–nograph”. The picture shows that the graphical structure of the state -machine. - -.. figure:: img/top_state.png - :alt: top_state.png - - top_state.png - -Code generator --------------- - -Finally, let’s try code generation. Please prepare a Python script as -below. The file name is ‘test.py’. A Verilog HDL code is represented by -using the AST classes defined in ‘vparser.ast’. - -.. code:: python - - from __future__ import absolute_import - from __future__ import print_function - import sys - import os - import pyverilog.vparser.ast as vast - from pyverilog.ast_code_generator.codegen import ASTCodeGenerator - - def main(): - datawid = vast.Parameter( 'DATAWID', vast.Rvalue(vast.IntConst('32')) ) - params = vast.Paramlist( [datawid] ) - clk = vast.Ioport( vast.Input('CLK') ) - rst = vast.Ioport( vast.Input('RST') ) - width = vast.Width( vast.IntConst('7'), vast.IntConst('0') ) - led = vast.Ioport( vast.Output('led', width=width) ) - ports = vast.Portlist( [clk, rst, led] ) - - width = vast.Width( vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), vast.IntConst('0') ) - count = vast.Reg('count', width=width) - - assign = vast.Assign( - vast.Lvalue(vast.Identifier('led')), - vast.Rvalue( - vast.Partselect( - vast.Identifier('count'), # count - vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), # [DATAWID-1: - vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('8'))))) # :DATAWID-8] - - sens = vast.Sens(vast.Identifier('CLK'), type='posedge') - senslist = vast.SensList([ sens ]) - - assign_count_true = vast.NonblockingSubstitution( - vast.Lvalue(vast.Identifier('count')), - vast.Rvalue(vast.IntConst('0'))) - if0_true = vast.Block([ assign_count_true ]) - - # count + 1 - count_plus_1 = vast.Plus(vast.Identifier('count'), vast.IntConst('1')) - assign_count_false = vast.NonblockingSubstitution( - vast.Lvalue(vast.Identifier('count')), - vast.Rvalue(count_plus_1)) - if0_false = vast.Block([ assign_count_false ]) - - if0 = vast.IfStatement(vast.Identifier('RST'), if0_true, if0_false) - statement = vast.Block([ if0 ]) - - always = vast.Always(senslist, statement) - - items = [] - items.append(count) - items.append(assign) - items.append(always) - - ast = vast.ModuleDef("top", params, ports, items) - - codegen = ASTCodeGenerator() - rslt = codegen.visit(ast) - print(rslt) - - if __name__ == '__main__': - main() - -Please type the command as below at the same directory with Pyverilog. - -:: - - python3 test.py - -Then Verilog HDL code generated from the AST instances is displayed. - -.. code:: verilog - - module top # - ( - parameter DATAWID = 32 - ) - ( - input CLK, - input RST, - output [7:0] led - ); - - reg [DATAWID-1:0] count; - assign led = count[DATAWID-1:DATAWID-8]; - - always @(posedge CLK) begin - if(RST) begin - count <= 0; - end else begin - count <= count + 1; - end - end - - - endmodule - -Related Project and Site -======================== - -`Veriloggen `__ - A Mixed-Paradigm -Hardware Construction Framework - -`NNgen `__ - A Fully-Customizable -Hardware Synthesis Compiler for Deep Neural Network - -`IPgen `__ - IP-core package generator -for AXI4/Avalon - -`PyCoRAM `__ - Python-based Portable -IP-core Synthesis Framework for FPGA-based Computing - -`flipSyrup `__ - Cycle-Accurate -Hardware Simulation Framework on Abstract FPGA Platforms - -`Pyverilog_toolbox `__ - -Pyverilog_toolbox is Pyverilog-based verification/design tool, which is -developed by Fukatani-san and uses Pyverilog as a fundamental library. -Thanks for your contribution! - -`shtaxxx.hatenablog.com `__ -- Blog entry for introduction and examples of Pyverilog (in Japansese) - -.. |Build Status| image:: https://travis-ci.org/PyHDI/Pyverilog.svg - :target: https://travis-ci.org/PyHDI/Pyverilog diff --git a/setup.py b/setup.py index 1282975..6a427ff 100644 --- a/setup.py +++ b/setup.py @@ -15,7 +15,8 @@ def read(filename): setup(name='pyverilog', version=version, description='Python-based Hardware Design Processing Toolkit for Verilog HDL: Parser, Dataflow Analyzer, Controlflow Analyzer and Code Generator', - long_description=read('README.rst'), + long_description=read('README.md'), + long_description_content_type="text/markdown", keywords='Verilog HDL, Lexer, Parser, Dataflow Analyzer, Control-flow Analyzer, Code Generator, Visualizer', author='Shinya Takamaeda-Yamazaki', license="Apache License 2.0", From 6b13dc005bc5fc17764a6980f9cb198d432f1d2a Mon Sep 17 00:00:00 2001 From: shtaxxx Date: Tue, 26 Nov 2019 13:00:10 +0900 Subject: [PATCH 02/13] Removing README.rst from MANIFEST.in --- MANIFEST.in | 1 - 1 file changed, 1 deletion(-) diff --git a/MANIFEST.in b/MANIFEST.in index be356f1..bd31932 100644 --- a/MANIFEST.in +++ b/MANIFEST.in @@ -1,5 +1,4 @@ include README.md -include README.rst include LICENSE include pytest.ini include .travis.yml From d8f0166e49c2d44166c9e4cabaaacc8859f3cdd8 Mon Sep 17 00:00:00 2001 From: shtaxxx Date: Tue, 26 Nov 2019 13:30:13 +0900 Subject: [PATCH 03/13] __version__ in __init__.py --- pyverilog/__init__.py | 1 + pyverilog/utils/version.py | 1 - setup.py | 7 ++----- 3 files changed, 3 insertions(+), 6 deletions(-) delete mode 100644 pyverilog/utils/version.py diff --git a/pyverilog/__init__.py b/pyverilog/__init__.py index e69de29..c68196d 100644 --- a/pyverilog/__init__.py +++ b/pyverilog/__init__.py @@ -0,0 +1 @@ +__version__ = "1.2.0" diff --git a/pyverilog/utils/version.py b/pyverilog/utils/version.py deleted file mode 100644 index 848258f..0000000 --- a/pyverilog/utils/version.py +++ /dev/null @@ -1 +0,0 @@ -VERSION = "1.2.0" diff --git a/setup.py b/setup.py index 6a427ff..b9a6fa0 100644 --- a/setup.py +++ b/setup.py @@ -1,11 +1,8 @@ from setuptools import setup, find_packages -import pyverilog.utils.version import re import os - -m = re.search(r'(\d+\.\d+\.\d+(-.+)?)', pyverilog.utils.version.VERSION) -version = m.group(1) if m is not None else '0.0.0' +import pyverilog def read(filename): @@ -13,7 +10,7 @@ def read(filename): setup(name='pyverilog', - version=version, + version=pyverilog.__version__, description='Python-based Hardware Design Processing Toolkit for Verilog HDL: Parser, Dataflow Analyzer, Controlflow Analyzer and Code Generator', long_description=read('README.md'), long_description_content_type="text/markdown", From 1ff455432787fcb1777a68194b2cbf9381492beb Mon Sep 17 00:00:00 2001 From: shtaxxx Date: Tue, 26 Nov 2019 13:52:33 +0900 Subject: [PATCH 04/13] Removing setup.cfg --- setup.cfg | 2 -- 1 file changed, 2 deletions(-) delete mode 100644 setup.cfg diff --git a/setup.cfg b/setup.cfg deleted file mode 100644 index 5aef279..0000000 --- a/setup.cfg +++ /dev/null @@ -1,2 +0,0 @@ -[metadata] -description-file = README.rst From 3cdc5996d00d88ce4a5f310ede24638993489b7c Mon Sep 17 00:00:00 2001 From: shtaxxx Date: Tue, 26 Nov 2019 14:08:02 +0900 Subject: [PATCH 05/13] VERSION as TEXT --- MANIFEST.in | 2 ++ pyverilog/VERSION | 1 + pyverilog/__init__.py | 7 ++++++- setup.py | 9 +++++---- 4 files changed, 14 insertions(+), 5 deletions(-) create mode 100644 pyverilog/VERSION diff --git a/MANIFEST.in b/MANIFEST.in index bd31932..ffd0fd8 100644 --- a/MANIFEST.in +++ b/MANIFEST.in @@ -3,6 +3,8 @@ include LICENSE include pytest.ini include .travis.yml include Makefile +include pyverilog/Makefile +include pyverilog/VERSION recursive-include tests * recursive-include examples * recursive-include verilogcode * diff --git a/pyverilog/VERSION b/pyverilog/VERSION new file mode 100644 index 0000000..26aaba0 --- /dev/null +++ b/pyverilog/VERSION @@ -0,0 +1 @@ +1.2.0 diff --git a/pyverilog/__init__.py b/pyverilog/__init__.py index c68196d..3b4e375 100644 --- a/pyverilog/__init__.py +++ b/pyverilog/__init__.py @@ -1 +1,6 @@ -__version__ = "1.2.0" +from __future__ import absolute_import +from __future__ import print_function + +import os + +__version__ = open(os.path.join(os.path.dirname(__file__), "VERSION")).read().splitlines()[0] diff --git a/setup.py b/setup.py index b9a6fa0..e68cb0b 100644 --- a/setup.py +++ b/setup.py @@ -2,15 +2,15 @@ import re import os -import pyverilog def read(filename): - return open(os.path.join(os.path.dirname(__file__), filename), encoding='utf8').read() + # return open(os.path.join(os.path.dirname(__file__), filename), encoding='utf8').read() + return open(os.path.join(os.path.dirname(__file__), filename)).read() setup(name='pyverilog', - version=pyverilog.__version__, + version=read('pyverilog/VERSION'), description='Python-based Hardware Design Processing Toolkit for Verilog HDL: Parser, Dataflow Analyzer, Controlflow Analyzer and Code Generator', long_description=read('README.md'), long_description_content_type="text/markdown", @@ -19,7 +19,8 @@ def read(filename): license="Apache License 2.0", url='https://github.com/PyHDI/Pyverilog', packages=find_packages(), - package_data={'pyverilog.ast_code_generator': ['template/*'], }, + package_data={'pyverilog': ['VERSION'], + 'pyverilog.ast_code_generator': ['template/*'], }, install_requires=['Jinja2>=2.10'], extras_require={ 'test': ['pytest>=3.8.1', 'pytest-pythonpath>=0.7.3'], From 164115e93aa5e5848e98a6aad835a54bb4c700c1 Mon Sep 17 00:00:00 2001 From: shtaxxx Date: Tue, 26 Nov 2019 14:11:36 +0900 Subject: [PATCH 06/13] removing re --- setup.py | 1 - 1 file changed, 1 deletion(-) diff --git a/setup.py b/setup.py index e68cb0b..1f37bf8 100644 --- a/setup.py +++ b/setup.py @@ -1,6 +1,5 @@ from setuptools import setup, find_packages -import re import os From 3daf3fe2975c8df2d00d7188dc9161788e3ca592 Mon Sep 17 00:00:00 2001 From: shtaxxx Date: Tue, 26 Nov 2019 16:54:53 +0900 Subject: [PATCH 07/13] strip the tail return. --- setup.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/setup.py b/setup.py index 1f37bf8..dd39fef 100644 --- a/setup.py +++ b/setup.py @@ -9,7 +9,7 @@ def read(filename): setup(name='pyverilog', - version=read('pyverilog/VERSION'), + version=read('pyverilog/VERSION').splitlines()[0], description='Python-based Hardware Design Processing Toolkit for Verilog HDL: Parser, Dataflow Analyzer, Controlflow Analyzer and Code Generator', long_description=read('README.md'), long_description_content_type="text/markdown", From 3c9bc918bcaac0ce9a0bde600f0c54f0d9c846ab Mon Sep 17 00:00:00 2001 From: JaewonHur Date: Mon, 30 Dec 2019 12:28:41 +0900 Subject: [PATCH 08/13] add parsing rule, integer declaration and initialization --- pyverilog/vparser/ast.py | 5 ++++- pyverilog/vparser/parser.py | 15 ++++++++++----- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/pyverilog/vparser/ast.py b/pyverilog/vparser/ast.py index eb21669..e48e569 100644 --- a/pyverilog/vparser/ast.py +++ b/pyverilog/vparser/ast.py @@ -272,15 +272,18 @@ class StringConst(Constant): class Variable(Value): attr_names = ('name', 'signed') - def __init__(self, name, width=None, signed=False, dimensions=None, lineno=0): + def __init__(self, name, value=None, width=None, signed=False, dimensions=None, lineno=0): self.lineno = lineno self.name = name + self.value = value self.width = width self.signed = signed self.dimensions = dimensions def children(self): nodelist = [] + if self.value: + nodelist.append(self.value) if self.width: nodelist.append(self.width) if self.dimensions: diff --git a/pyverilog/vparser/parser.py b/pyverilog/vparser/parser.py index 5098425..076c182 100644 --- a/pyverilog/vparser/parser.py +++ b/pyverilog/vparser/parser.py @@ -682,21 +682,21 @@ def p_declassign_element_delay(self, p): # Integer def p_integerdecl(self, p): 'integerdecl : INTEGER integernamelist SEMICOLON' - intlist = [Integer(r, + intlist = [Integer(rname, rvalue, Width(msb=IntConst('31', lineno=p.lineno(2)), lsb=IntConst('0', lineno=p.lineno(2)), lineno=p.lineno(2)), - signed=True, lineno=p.lineno(2)) for r in p[2]] + signed=True, lineno=p.lineno(2)) for rname, rvalue in p[2]] p[0] = Decl(tuple(intlist), lineno=p.lineno(1)) p.set_lineno(0, p.lineno(1)) def p_integerdecl_signed(self, p): 'integerdecl : INTEGER SIGNED integernamelist SEMICOLON' - intlist = [Integer(r, + intlist = [Integer(rname, rvalue, Width(msb=IntConst('31', lineno=p.lineno(3)), lsb=IntConst('0', lineno=p.lineno(3)), lineno=p.lineno(3)), - signed=True, lineno=p.lineno(3)) for r in p[2]] + signed=True, lineno=p.lineno(3)) for rname, rvalue in p[2]] p[0] = Decl(tuple(intlist), lineno=p.lineno(1)) p.set_lineno(0, p.lineno(1)) @@ -710,9 +710,14 @@ def p_integernamelist_one(self, p): p[0] = (p[1],) p.set_lineno(0, p.lineno(1)) + def p_integername_init(self, p): + 'integername: ID EQUALS rvalue' + p[0] = (p[1], p[3]) + p.set_lineno(0, p.lineno(1)) + def p_integername(self, p): 'integername : ID' - p[0] = p[1] + p[0] = (p[1], None) p.set_lineno(0, p.lineno(1)) # Real From 9352c20c9fe6147d863a95700d4d47111b163fb2 Mon Sep 17 00:00:00 2001 From: JaewonHur Date: Mon, 30 Dec 2019 12:36:27 +0900 Subject: [PATCH 09/13] add parsing rule, integer declaration and initialization r1 --- pyverilog/vparser/parser.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pyverilog/vparser/parser.py b/pyverilog/vparser/parser.py index 076c182..e94b344 100644 --- a/pyverilog/vparser/parser.py +++ b/pyverilog/vparser/parser.py @@ -711,7 +711,7 @@ def p_integernamelist_one(self, p): p.set_lineno(0, p.lineno(1)) def p_integername_init(self, p): - 'integername: ID EQUALS rvalue' + 'integername : ID EQUALS rvalue' p[0] = (p[1], p[3]) p.set_lineno(0, p.lineno(1)) From e8940d4d4a251d6e08028250ffe0c73945c6c44d Mon Sep 17 00:00:00 2001 From: JaewonHur Date: Mon, 30 Dec 2019 12:59:58 +0900 Subject: [PATCH 10/13] add parsing rule, function integer ID --- pyverilog/vparser/parser.py | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/pyverilog/vparser/parser.py b/pyverilog/vparser/parser.py index 5098425..11290cc 100644 --- a/pyverilog/vparser/parser.py +++ b/pyverilog/vparser/parser.py @@ -2058,6 +2058,15 @@ def p_function_nowidth(self, p): p[4], lineno=p.lineno(1)) p.set_lineno(0, p.lineno(1)) + def p_function_integer(self, p): + 'function : FUNCTION INTEGER ID SEMICOLON function_statement ENDFUNCTION' + p[0] = Function(p[3], + Width(IntConst('31', lineno=p.lineno(1)), + IntConst('0', lineno=p.lineno(1)), + lineno=p.lineno(1)), + p[5], lineno=p.lineno(1)) + p.set_lineno(0, p.lineno(1)) + def p_function_statement(self, p): 'function_statement : funcvardecls function_calc' p[0] = p[1] + (p[2],) From 3034745292c050bc9368283c4afa82e5f370daf9 Mon Sep 17 00:00:00 2001 From: Peter Birch Date: Mon, 3 Feb 2020 11:34:32 +0000 Subject: [PATCH 11/13] Adding basic support for CASEZ statements --- pyverilog/vparser/ast.py | 4 ++++ pyverilog/vparser/lexer.py | 2 +- pyverilog/vparser/parser.py | 8 ++++++++ 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/pyverilog/vparser/ast.py b/pyverilog/vparser/ast.py index eb21669..b3865a5 100644 --- a/pyverilog/vparser/ast.py +++ b/pyverilog/vparser/ast.py @@ -882,6 +882,10 @@ class CasexStatement(CaseStatement): pass +class CasezStatement(CaseStatement): + pass + + class UniqueCaseStatement(CaseStatement): pass diff --git a/pyverilog/vparser/lexer.py b/pyverilog/vparser/lexer.py index 1d43192..94501da 100644 --- a/pyverilog/vparser/lexer.py +++ b/pyverilog/vparser/lexer.py @@ -56,7 +56,7 @@ def token(self): 'INPUT', 'INOUT', 'OUTPUT', 'TRI', 'REG', 'LOGIC', 'WIRE', 'INTEGER', 'REAL', 'SIGNED', 'PARAMETER', 'LOCALPARAM', 'SUPPLY0', 'SUPPLY1', 'ASSIGN', 'ALWAYS', 'ALWAYS_FF', 'ALWAYS_COMB', 'ALWAYS_LATCH', 'SENS_OR', 'POSEDGE', 'NEGEDGE', 'INITIAL', - 'IF', 'ELSE', 'FOR', 'WHILE', 'CASE', 'CASEX', 'UNIQUE', 'ENDCASE', 'DEFAULT', + 'IF', 'ELSE', 'FOR', 'WHILE', 'CASE', 'CASEX', 'CASEZ', 'UNIQUE', 'ENDCASE', 'DEFAULT', 'WAIT', 'FOREVER', 'DISABLE', 'FORK', 'JOIN', ) diff --git a/pyverilog/vparser/parser.py b/pyverilog/vparser/parser.py index 5098425..13e1513 100644 --- a/pyverilog/vparser/parser.py +++ b/pyverilog/vparser/parser.py @@ -1413,6 +1413,7 @@ def p_basic_statement(self, p): """basic_statement : if_statement | case_statement | casex_statement + | casez_statement | unique_case_statement | for_statement | while_statement @@ -1656,6 +1657,11 @@ def p_casex_statement(self, p): p[0] = CasexStatement(p[3], p[5], lineno=p.lineno(1)) p.set_lineno(0, p.lineno(1)) + def p_casez_statement(self, p): + 'casez_statement : CASEZ LPAREN case_comp RPAREN casecontent_statements ENDCASE' + p[0] = CasezStatement(p[3], p[5], lineno=p.lineno(1)) + p.set_lineno(0, p.lineno(1)) + def p_unique_case_statement(self, p): 'unique_case_statement : UNIQUE CASE LPAREN case_comp RPAREN casecontent_statements ENDCASE' p[0] = UniqueCaseStatement(p[3], p[5], lineno=p.lineno(1)) @@ -2092,6 +2098,7 @@ def p_function_calc(self, p): | while_statement | case_statement | casex_statement + | casez_statement | block | namedblock """ @@ -2161,6 +2168,7 @@ def p_task_calc(self, p): | while_statement | case_statement | casex_statement + | casez_statement | block | namedblock """ From a1bf312e9608ba47d3724dacbb98928b66ef561c Mon Sep 17 00:00:00 2001 From: shtaxxx Date: Thu, 12 Mar 2020 22:11:10 +0900 Subject: [PATCH 12/13] Aargument order is changed for the backward compatibility. --- pyverilog/vparser/ast.py | 8 ++++---- pyverilog/vparser/parser.py | 12 ++++++++---- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/pyverilog/vparser/ast.py b/pyverilog/vparser/ast.py index d2ae901..492adc9 100644 --- a/pyverilog/vparser/ast.py +++ b/pyverilog/vparser/ast.py @@ -272,22 +272,22 @@ class StringConst(Constant): class Variable(Value): attr_names = ('name', 'signed') - def __init__(self, name, value=None, width=None, signed=False, dimensions=None, lineno=0): + def __init__(self, name, width=None, signed=False, dimensions=None, value=None, lineno=0): self.lineno = lineno self.name = name - self.value = value self.width = width self.signed = signed self.dimensions = dimensions + self.value = value def children(self): nodelist = [] - if self.value: - nodelist.append(self.value) if self.width: nodelist.append(self.width) if self.dimensions: nodelist.append(self.dimensions) + if self.value: + nodelist.append(self.value) return tuple(nodelist) diff --git a/pyverilog/vparser/parser.py b/pyverilog/vparser/parser.py index 1a9af0d..c3c2f7e 100644 --- a/pyverilog/vparser/parser.py +++ b/pyverilog/vparser/parser.py @@ -682,21 +682,25 @@ def p_declassign_element_delay(self, p): # Integer def p_integerdecl(self, p): 'integerdecl : INTEGER integernamelist SEMICOLON' - intlist = [Integer(rname, rvalue, + intlist = [Integer(rname, Width(msb=IntConst('31', lineno=p.lineno(2)), lsb=IntConst('0', lineno=p.lineno(2)), lineno=p.lineno(2)), - signed=True, lineno=p.lineno(2)) for rname, rvalue in p[2]] + signed=True, + value=rvalue, + lineno=p.lineno(2)) for rname, rvalue in p[2]] p[0] = Decl(tuple(intlist), lineno=p.lineno(1)) p.set_lineno(0, p.lineno(1)) def p_integerdecl_signed(self, p): 'integerdecl : INTEGER SIGNED integernamelist SEMICOLON' - intlist = [Integer(rname, rvalue, + intlist = [Integer(rname, Width(msb=IntConst('31', lineno=p.lineno(3)), lsb=IntConst('0', lineno=p.lineno(3)), lineno=p.lineno(3)), - signed=True, lineno=p.lineno(3)) for rname, rvalue in p[2]] + signed=True, + value=rvalue, + lineno=p.lineno(3)) for rname, rvalue in p[2]] p[0] = Decl(tuple(intlist), lineno=p.lineno(1)) p.set_lineno(0, p.lineno(1)) From ad5e96b41e1fa509adf2663573fc7de491cebe7e Mon Sep 17 00:00:00 2001 From: shtaxxx Date: Sun, 3 May 2020 15:14:05 +0900 Subject: [PATCH 13/13] 1.2.1-rc --- pyverilog/VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pyverilog/VERSION b/pyverilog/VERSION index 26aaba0..6085e94 100644 --- a/pyverilog/VERSION +++ b/pyverilog/VERSION @@ -1 +1 @@ -1.2.0 +1.2.1