From 2208f17bc54599aa55b9b10ab5921bb8255046f4 Mon Sep 17 00:00:00 2001
From: chengguanghui <wissycgh@gmail.com>
Date: Tue, 10 Dec 2024 15:58:27 +0800
Subject: [PATCH 1/2] feat(Smcntrpmf): support Smcntrpmf extension

 * add csrs: mcyclecfg, minstretcfg
---
 .../backend/fu/NewCSR/MachineLevel.scala      | 33 ++++++++++++-------
 .../xiangshan/backend/fu/NewCSR/NewCSR.scala  | 20 +++++++++++
 2 files changed, 42 insertions(+), 11 deletions(-)

diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
index 9ea3d640758..9a1c7d90d9b 100644
--- a/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
+++ b/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
@@ -297,10 +297,10 @@ trait MachineLevel { self: NewCSR =>
     val MML   = RO( 0) // Smepmp
   })).setAddr(CSRs.mseccfg)
 
-  val mcycle = Module(new CSRModule("Mcycle") with HasMachineCounterControlBundle {
+  val mcycle = Module(new CSRModule("Mcycle") with HasMachineCounterControlBundle with SmcntrpmfBundle {
     when(w.wen) {
       reg := w.wdata
-    }.elsewhen(!this.mcountinhibit.CY.asUInt.asBool) {
+    }.elsewhen(!this.mcountinhibit.CY.asUInt.asBool && countingEn) {
       reg := reg.ALL.asUInt + 1.U
     }.otherwise {
       reg := reg
@@ -308,10 +308,10 @@ trait MachineLevel { self: NewCSR =>
   }).setAddr(CSRs.mcycle)
 
 
-  val minstret = Module(new CSRModule("Minstret") with HasMachineCounterControlBundle with HasRobCommitBundle {
+  val minstret = Module(new CSRModule("Minstret") with HasMachineCounterControlBundle with HasRobCommitBundle with SmcntrpmfBundle {
     when(w.wen) {
       reg := w.wdata
-    }.elsewhen(!this.mcountinhibit.IR && robCommit.instNum.valid) {
+    }.elsewhen(!this.mcountinhibit.IR && robCommit.instNum.valid && countingEn) {
       reg := reg.ALL.asUInt + robCommit.instNum.bits
     }.otherwise {
       reg := reg
@@ -335,6 +335,12 @@ trait MachineLevel { self: NewCSR =>
     }).setAddr(CSRs.mhpmcounter3 - 3 + num)
   )
 
+  val mcyclecfg = Module(new CSRModule("Mcyclecfg", new EventInhibitBundle))
+    .setAddr(CSRs.mcyclecfg)
+
+  val minstretcfg = Module(new CSRModule("Minstretcfg", new EventInhibitBundle))
+    .setAddr(CSRs.minstretcfg)
+
   val mvendorid = Module(new CSRModule("Mvendorid") { rdata := 0.U })
     .setAddr(CSRs.mvendorid)
 
@@ -417,6 +423,8 @@ trait MachineLevel { self: NewCSR =>
     mncause,
     mnstatus,
     mnscratch,
+    mcyclecfg,
+    minstretcfg,
   ) ++ mhpmevents ++ mhpmcounters
 
   val machineLevelCSRMap: SeqMap[Int, (CSRAddrWriteBundle[_], UInt)] = SeqMap.from(
@@ -674,13 +682,16 @@ class MipToMvip extends IpValidBundle {
   this.SEIP.bits.setRW()
 }
 
-class MhpmeventBundle extends CSRBundle {
-  val OF      = RW(63).withReset(0.U)
+class EventInhibitBundle extends CSRBundle {
   val MINH    = RW(62).withReset(0.U)
   val SINH    = RW(61).withReset(0.U)
   val UINH    = RW(60).withReset(0.U)
   val VSINH   = RW(59).withReset(0.U)
   val VUINH   = RW(58).withReset(0.U)
+}
+
+class MhpmeventBundle extends EventInhibitBundle {
+  val OF      = RW(63).withReset(0.U)
   val OPTYPE2 = OPTYPE(54, 50, wNoFilter).withReset(OPTYPE.OR)
   val OPTYPE1 = OPTYPE(49, 45, wNoFilter).withReset(OPTYPE.OR)
   val OPTYPE0 = OPTYPE(44, 40, wNoFilter).withReset(OPTYPE.OR)
@@ -753,10 +764,10 @@ trait HasPerfCounterBundle { self: CSRModule[_] =>
   val toMhpmeventOF = IO(Output(Bool()))
 }
 
-trait HasPerfEventBundle { self: CSRModule[_] =>
-  val perfEvents = IO(Input(Vec(perfCntNum, UInt(XLEN.W))))
-}
-
 trait HasLocalInterruptReqBundle { self: CSRModule[_] =>
   val lcofiReq = IO(Input(Bool()))
-}
\ No newline at end of file
+}
+
+trait SmcntrpmfBundle { self: CSRModule[_] =>
+  val countingEn    = IO(Input(Bool()))
+}
diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
index 1abd03599ce..72a7fae635d 100644
--- a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
+++ b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
@@ -1175,6 +1175,26 @@ class NewCSR(implicit val p: Parameters) extends Module
       m.lcofiReq := lcofiReq
     case _ =>
   }
+  // Smcntrpmf extension
+  mcycle match {
+    case m: SmcntrpmfBundle =>
+      m.countingEn := (privState.isModeM && !mcyclecfg.regOut.MINH) ||
+        (privState.isModeHS && !mcyclecfg.regOut.SINH)  ||
+        (privState.isModeHU && !mcyclecfg.regOut.UINH)  ||
+        (privState.isModeVS && !mcyclecfg.regOut.VSINH) ||
+        (privState.isModeVU && !mcyclecfg.regOut.VUINH)
+    case _ =>
+  }
+
+  minstret match {
+    case m: SmcntrpmfBundle =>
+      m.countingEn := (privState.isModeM && !minstretcfg.regOut.MINH) ||
+        (privState.isModeHS && !minstretcfg.regOut.SINH)  ||
+        (privState.isModeHU && !minstretcfg.regOut.UINH)  ||
+        (privState.isModeVS && !minstretcfg.regOut.VSINH) ||
+        (privState.isModeVU && !minstretcfg.regOut.VUINH)
+    case _ =>
+  }
   /**
    * perf_end
    */

From a1a2dfc5012cbabae0785de5c5a789341df55d60 Mon Sep 17 00:00:00 2001
From: chengguanghui <wissycgh@gmail.com>
Date: Tue, 10 Dec 2024 16:00:55 +0800
Subject: [PATCH 2/2] submodule(rocket-chip): bump rocket-chip to support
 Smcntrpmf extension

---
 rocket-chip | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rocket-chip b/rocket-chip
index bb4baf85c5b..edd731ec0d9 160000
--- a/rocket-chip
+++ b/rocket-chip
@@ -1 +1 @@
-Subproject commit bb4baf85c5bd4b55ffdcda12a75648fef212ab69
+Subproject commit edd731ec0d953f7272bed6019652dcb0767f0bbb