The UF flag in the fcsr register is different

[fly-1011]

Before start

• I have read the RISC-V ISA Manual and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册，这不是一个指令集相关的问题。
• I have read the XiangShan Documents. 我已经阅读过香山文档。
• I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。
• I have searched the previous discussions and did not find anything relevant. 我已经搜索过之前的 discussions，并没有找到相关的。
• I have reviewed the commit messages from the relevant commit history. 我已经浏览过相关的提交历史和提交信息。

Describe the question

describe

When I was testing Xiangshan, when executing the following test sample, there would be inconsistencies in the fcsr register, specifically the UF flag.

Log screenshot

The inconsistent information between nemu and spike is as follows

Test samples and log information:fcsr.zip

Version Information

xiangshan:commit b00d582 (HEAD -> master, origin/master, origin/HEAD)
ready-to-run:commit 457f091898b2bcd26c8f6e983f3df174f990af43 (HEAD -> master, origin/master, origin/HEAD)

I also noticed that there seems to be a fix for the OF and UF flags in the yunsuan module(OpenXiangShan/YunSuan@548dbea), but the Xiangshan version I use has already been merged.

[HeiHuDie]

xiangshan: edb1dfa
ready-to-run: c1dc496545b9d62bb10264cd4485cb6fe7c60798
YunSuan: 2cafaa74daf43e2693bca80093a0af22678616a3
Sorry,I cannot reproduce this bug on the latest version of XiangShan.
I think this may be a problem caused by a certain version not matching.

[fly-1011]

Thank you for your reply. I will update to the latest version and conduct the testing again. I am also looking forward to the update of the yunsuan module being merged into Xiangshan. Thank you again😄