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Sign bit handling error #3951

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4 tasks done
fly-1011 opened this issue Nov 28, 2024 · 2 comments
Open
4 tasks done

Sign bit handling error #3951

fly-1011 opened this issue Nov 28, 2024 · 2 comments
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answered bug report Bugs to be confirmed

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@fly-1011
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Before start

  • I have read the RISC-V ISA Manual and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册,这不是一个指令集本身的问题。
  • I have read the XiangShan Documents. 我已经阅读过香山文档。
  • I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue,并没有找到相关的。
  • I have reviewed the commit messages from the relevant commit history. 我已经浏览过相关的提交历史和提交信息。

Describe the bug

When executing fadd.h ft0, fa0, fa0 instruction, the value of fa0 is 0xffffffffffff8000 (-0.0 in half precision format), and the results of Xiangshan and nemu are different.

Expected behavior

Log information:
image
image
image

The log information of spike is also shown above

To Reproduce

Initialize fa0: 0xffffffffffff8000
Execute fadd.h ft0, fa0, fa0

Environment

  • XiangShan branch:
  • XiangShan commit id: b00d582 (HEAD -> master, origin/master, origin/HEAD)
  • NEMU commit id:
  • SPIKE commit id:
    ready-to-run:457f091898b2bcd26c8f6e983f3df174f990af43 (HEAD -> master, origin/master, origin/HEAD)

Additional context

No response

@fly-1011 fly-1011 added the bug report Bugs to be confirmed label Nov 28, 2024
@HeiHuDie
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HeiHuDie commented Nov 28, 2024

Thanks, this is a known bug and has been fixed, but it has not been merged into master

@fly-1011
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fly-1011 commented Nov 28, 2024

Thank you for your reply. Thanks to your reminder, I noticed that the fix has been made in the yunsuan module, but it hasn't been merged into Xiangshan yet. I’m looking forward to the merge!😄

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