Omega2S-Footprint.asc

!PADS-POWERPCB-V9.5-BASIC! DESIGN DATABASE ASCII FILE 1.0 PCB GENERAL PARAMETERS OF THE PCB DESIGN

UNITS 1 2=Inches 1=Metric 0=Mils USERGRID 15000 15000 Space between USER grid points MAXIMUMLAYER 2 Maximum routing layer WORKLEVEL 1 Level items will be created on DISPLAYLEVEL 1 toggle for displaying working level last LAYERPAIR 1 2 Layer pair used to route connection VIAMODE T Type of via to use when routing between layers LINEWIDTH 381000 Width items will be created with TEXTSIZE 3810000 381000 Height and LineWidth text will be created with JOBTIME 5 Amount of time spent on this PCB design DOTGRID 38100000 38100000 Space between graphic dots SCALE 17.219 Scale of window expansion ORIGIN 381000000 381000000 User defined origin location WINDOWCENTER 379214352 377714817 Point defining the center of the window BACKUPTIME 20 Number of minutes between database backups REAL WIDTH 381000 Widths greater then this are displayed real size ALLSIGONOFF 1 All signal nets displayed on/off REFNAMESIZE 3810000 381000 Height and LineWidth used by part ref. names HIGHLIGHT 0 Highlight nets flag JOBNAME 15.pcb CONCOL 1 FBGCOL 1 0 HATCHGRID 381000 Copper pour hatching grid TEARDROP 2713690 Teardrop tracks THERLINEWID 571500 Copper pour thermal line width PSVIAGRID 15000 15000 Push & Shove Via Grid PADFILLWID 381000 CAM finger pad fill width THERSMDWID 381000 Copper pour thermal line width for SMD MINHATAREA 0 Minimum hatch area HATCHMODE 0 Hatch generation mode HATCHDISP 0 Hatch display flag DRILLHOLE 228600 Drill hole checking spacing MITRERADII 0.5 1.0 1.5 2.0 2.5 3.0 3.5 MITRETYPE 1 Mitring type HATCHRAD 0.500000 Hatch outline smoothing radius MITREANG 180 180 180 180 180 180 90 HATCHANG 0 Hatch angle THERFLAGS 0 Copper pour thermal line flags DRLOVERSIZE 114300 Drill oversize for plated holes PLANERAD 0.000000 Plane outline smoothing radius PLANEFLAGS OUTLINE THERMALS Y Y Y N N Y Y Y N N Y Y N Y Y N N N Plane and Test Points flags COMPHEIGHT 0 Board Top Component Height Restriction KPTHATCHGRID 3810000 Copper pour hatching grid BOTCMPHEIGHT 0 Board Bottom Component Height Restriction FANOUTGRID 952500 952500 Fanout grid FANOUTLENGTH 9525000 Maximum fanout length ROUTERFLAGS 83879441 Autorouter specific flags VERIFYFLAGS 1861 Verify Design flags FABCHKFLAGS 3967 Fabrication checks flags ATMAXSIZE 114300 Acid Traps Maximum Size ATMAXANGLE 161999820 Acid Traps Maximum Angle SLMINCOPPER 114300 Slivers Minimum Copper SLMINMASK 114300 Slivers Minimum Mask STMINCLEAR 5 Starved Thermal Minimum Clearance STMINSPOKES 4 Starved Thermal Minimum Spokes TPMINWIDTH 114300 Minimum Trace Width TPMINSIZE 114300 Mimimum Pad Size SSMINGAP 114300 Silk Screen Over Pads Minimum Gap SBMINGAP 114300 Solder Bridges Minimum Gap SBLAYER 1 Solder Bridges Layer ARPTOM 114300 Pad To Mask Annular Ring ARPTOMLAYER 1 Pad To Mask Annular Ring Layer ARDTOM 114300 Drill To Mask Annular Ring ARDTOMLAYER 1 Drill To Mask Annular Ring Layer ARDTOP 114300 Drill To Pad Annular Ring ARDTOPLAYER 0 Drill To Pad Annular Ring Layer VIAPSPACING 3810000 Via patterns via spacing VIAPSHAPE 228600 Via patterns via to shape spacing VIAPTOTRACE -1 Via patterns via to edge spacing VIAPFILL 1 Via patterns fill type VIAPSHSIG NONE VIAPSHVIA NONE VIAPFLAG 4 Via patterns flags FLOWFLAGS 0 Flow Flags OSNAP 502 Object snap flags OSNAPRAD 3810000 Object snap radius BOTTOMVIEW 0 Bottom view flag PLNSEPGAP 228600 Plane separation gap IDFSHAPELAY 0 IDF shapes layer ASSOCIATEDNETNETCOUNT 5 ASSOCIATEDNETPLANEPINCOUNT 25 ASSOCIATEDNETPREFIX0 ASSOCIATEDNETPREFIX1 ASSOCIATEDNETPREFIX2 ASSOCIATEDNETPREFIX3 ASSOCIATEDNETPREFIX4

TEARDROPDATA 90 90 REUSE

REMARK TYPE TYPENAME REMARK TIMESTAMP SECONDS REMARK PART NAMING PARTNAMING REMARK PART NAME REMARK NET NAMING NETNAMING REMARK NET MERGE NAME REMARK REUSE INSTANCENM PARTNAMING NETNAMING X Y ORI GLUED

TEXT FREE TEXT

REMARK XLOC YLOC ORI LEVEL HEIGHT WIDTH MIRRORED HJUST VJUST .REUSE. INSTANCENM REMARK FONTSTYLE FONTFACE

LINES LINES ITEMS

REMARK NAME TYPE XLOC YLOC PIECES TEXT SIGSTR REMARK .REUSE. INSTANCE RSIGNAL REMARK PIECETYPE CORNERS WIDTHHGHT LINESTYLE LEVEL [RESTRICTIONS] REMARK XLOC YLOC BEGINANGLE DELTAANGLE REMARK XLOC YLOC ORI LEVEL HEIGHT WIDTH MIRRORED HJUST VJUST

VIA ITEMS

REMARK NAME DRILL STACKLINES [DRILL START] [DRILL END] REMARK LEVEL SIZE SHAPE [INNER DIAMETER] [CORNER RADIUS]

JMPVIA_AAAAA 1409700 3 -2 2095500 R -1 2667000 R 0 2095500 R

STANDARDVIA 1409700 3 -2 2095500 R -1 2095500 R 0 2095500 R

PARTDECAL ITEMS

REMARK NAME UNITS ORIX ORIY PIECES TERMINALS STACKS TEXT LABELS REMARK PIECETYPE CORNERS WIDTHHGHT LINESTYLE LEVEL [RESTRICTIONS] REMARK PIECETYPE CORNERS WIDTH LINESTYLE LEVEL [PINNUM] REMARK XLOC YLOC BEGINANGLE DELTAANGLE REMARK XLOC YLOC ORI LEVEL HEIGHT WIDTH MIRRORED HJUST VJUST REMARK VISIBLE XLOC YLOC ORI LEVEL HEIGTH WIDTH MIRRORED HJUST VJUST RIGHTREADING REMARK FONTSTYLE FONTFACE REMARK T XLOC YLOC NMXLOC NMYLOC PINNUMBER REMARK PAD PIN STACKLINES REMARK LEVEL SIZE SHAPE IDIA [CORNERRADIUS] [DRILL [PLATED]] REMARK LEVEL SIZE SHAPE FINORI FINLENGTH FINOFFSET [CORNERRADIUS] [DRILL [PLATED]]

TSOP64 M 615000 0 1 64 15 0 2 CLOSED 5 190500 0 0 0 2430000 30090000 2430000 30090000 -48795000 0 -48795000 0 2430000 VALUE -615000 0 0.000 1 1905000 190500 N LEFT UP Regular <Romansim Stroke Font> Part Type VALUE -615000 0 0.000 1 1905000 190500 N LEFT DOWN Regular <Romansim Stroke Font> Ref.Des. T0 0 0 0 1 T0 -1905000 0 -1905000 2 T0 -3810000 0 -3810000 3 T0 -5715000 0 -5715000 4 T0 -7620000 0 -7620000 5 T0 -9525000 0 -9525000 6 T0 -11430000 0 -11430000 7 T0 -13335000 0 -13335000 8 T0 -15240000 0 -15240000 9 T0 -17145000 0 -17145000 10 T0 -19050000 0 -19050000 11 T0 -20955000 0 -20955000 12 T0 -22860000 0 -22860000 13 T0 -24765000 0 -24765000 14 T0 -26670000 0 -26670000 15 T0 -28575000 0 -28575000 16 T0 -30480000 0 -30480000 17 T0 -32385000 0 -32385000 18 T0 -34290000 0 -34290000 19 T0 -36195000 0 -36195000 20 T0 -38100000 0 -38100000 21 T0 -40005000 0 -40005000 22 T0 -41910000 0 -41910000 23 T0 -43815000 0 -43815000 24 T0 -45720000 0 -45720000 25 T3600000 -48736500 3600000 -48736500 26 T5505000 -48736500 5505000 -48736500 27 T7410000 -48736500 7410000 -48736500 28 T9315000 -48736500 9315000 -48736500 29 T11220000 -48736500 11220000 -48736500 30 T13125000 -48736500 13125000 -48736500 31 T15030000 -48736500 15030000 -48736500 32 T16935000 -48736500 16935000 -48736500 33 T18840000 -48736500 18840000 -48736500 34 T20745000 -48736500 20745000 -48736500 35 T22650000 -48736500 22650000 -48736500 36 T24555000 -48736500 24555000 -48736500 37 T26460000 -48736500 26460000 -48736500 38 T30120000 -45720000 30120000 -45720000 39 T30120000 -43815000 30120000 -43815000 40 T30120000 -41910000 30120000 -41910000 41 T30120000 -40005000 30120000 -40005000 42 T30120000 -38100000 30120000 -38100000 43 T30120000 -36195000 30120000 -36195000 44 T30120000 -34290000 30120000 -34290000 45 T30120000 -32385000 30120000 -32385000 46 T30120000 -30480000 30120000 -30480000 47 T30120000 -28575000 30120000 -28575000 48 T30120000 -26670000 30120000 -26670000 49 T30120000 -24765000 30120000 -24765000 50 T30120000 -22860000 30120000 -22860000 51 T30120000 -20955000 30120000 -20955000 52 T30120000 -19050000 30120000 -19050000 53 T30120000 -17145000 30120000 -17145000 54 T30120000 -15240000 30120000 -15240000 55 T30120000 -13335000 30120000 -13335000 56 T30120000 -11430000 30120000 -11430000 57 T30120000 -9525000 30120000 -9525000 58 T30120000 -7620000 30120000 -7620000 59 T30120000 -5715000 30120000 -5715000 60 T30120000 -3810000 30120000 -3810000 61 T30120000 -1905000 30120000 -1905000 62 T30120000 0 30120000 0 63 T15360000 -26040000 15360000 -26040000 64 PAD 0 3 -2 1500000 RF 0.000 3435000 0 0 0 -1 0 R 0 0 R PAD 26 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 27 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 28 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 29 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 30 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 31 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 32 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 33 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 34 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 35 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 36 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 37 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 38 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 64 3 -2 9000000 S 0 0 -1 0 R 0 0 R

TSOP64-OMEGA2S M 615000 0 1 64 15 0 2 CLOSED 5 190500 0 0 0 2430000 30090000 2430000 30090000 -48795000 0 -48795000 0 2430000 VALUE -615000 0 0.000 1 1905000 190500 N LEFT UP Regular <Romansim Stroke Font> Part Type VALUE -615000 0 0.000 1 1905000 190500 N LEFT DOWN Regular <Romansim Stroke Font> Ref.Des. T0 0 0 0 1 T0 -1905000 0 -1905000 2 T0 -3810000 0 -3810000 3 T0 -5715000 0 -5715000 4 T0 -7620000 0 -7620000 5 T0 -9525000 0 -9525000 6 T0 -11430000 0 -11430000 7 T0 -13335000 0 -13335000 8 T0 -15240000 0 -15240000 9 T0 -17145000 0 -17145000 10 T0 -19050000 0 -19050000 11 T0 -20955000 0 -20955000 12 T0 -22860000 0 -22860000 13 T0 -24765000 0 -24765000 14 T0 -26670000 0 -26670000 15 T0 -28575000 0 -28575000 16 T0 -30480000 0 -30480000 17 T0 -32385000 0 -32385000 18 T0 -34290000 0 -34290000 19 T0 -36195000 0 -36195000 20 T0 -38100000 0 -38100000 21 T0 -40005000 0 -40005000 22 T0 -41910000 0 -41910000 23 T0 -43815000 0 -43815000 24 T0 -45720000 0 -45720000 25 T3600000 -48736500 3600000 -48736500 26 T5505000 -48736500 5505000 -48736500 27 T7410000 -48736500 7410000 -48736500 28 T9315000 -48736500 9315000 -48736500 29 T11220000 -48736500 11220000 -48736500 30 T13125000 -48736500 13125000 -48736500 31 T15030000 -48736500 15030000 -48736500 32 T16935000 -48736500 16935000 -48736500 33 T18840000 -48736500 18840000 -48736500 34 T20745000 -48736500 20745000 -48736500 35 T22650000 -48736500 22650000 -48736500 36 T24555000 -48736500 24555000 -48736500 37 T26460000 -48736500 26460000 -48736500 38 T30120000 -45720000 30120000 -45720000 39 T30120000 -43815000 30120000 -43815000 40 T30120000 -41910000 30120000 -41910000 41 T30120000 -40005000 30120000 -40005000 42 T30120000 -38100000 30120000 -38100000 43 T30120000 -36195000 30120000 -36195000 44 T30120000 -34290000 30120000 -34290000 45 T30120000 -32385000 30120000 -32385000 46 T30120000 -30480000 30120000 -30480000 47 T30120000 -28575000 30120000 -28575000 48 T30120000 -26670000 30120000 -26670000 49 T30120000 -24765000 30120000 -24765000 50 T30120000 -22860000 30120000 -22860000 51 T30120000 -20955000 30120000 -20955000 52 T30120000 -19050000 30120000 -19050000 53 T30120000 -17145000 30120000 -17145000 54 T30120000 -15240000 30120000 -15240000 55 T30120000 -13335000 30120000 -13335000 56 T30120000 -11430000 30120000 -11430000 57 T30120000 -9525000 30120000 -9525000 58 T30120000 -7620000 30120000 -7620000 59 T30120000 -5715000 30120000 -5715000 60 T30120000 -3810000 30120000 -3810000 61 T30120000 -1905000 30120000 -1905000 62 T30120000 0 30120000 0 63 T15945000 -24961500 15945000 -24961500 64 PAD 0 3 -2 1500000 RF 0.000 3435000 0 0 0 -1 0 R 0 0 R PAD 26 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 27 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 28 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 29 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 30 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 31 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 32 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 33 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 34 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 35 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 36 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 37 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 38 3 -2 1500000 RF 90.000 3435000 0 0 0 -1 0 R 0 0 R PAD 64 4 -2 0 S 0 0 -1 0 R 0 0 R 26 9000000 S 0

PARTTYPE ITEMS

REMARK NAME DECALNM TYPE GATES SIGPINS UNUSEDPINNMS FLAGS ECO REMARK G/S SWAPTYPE PINS REMARK PINNUMBER SWAPTYPE.PINTYPE REMARK SIGPIN PINNUMBER SIGNAME REMARK PINNUMBER

TSOP64 TSOP64:TSOP64-OMEGA2S UND 1 0 0 0 Y G 0 64 1.0.U. 2.0.U. 3.0.U. 4.0.U. 5.0.U. 6.0.U. 7.0.U. 8.0.U. 9.0.U. 10.0.U. 11.0.U. 12.0.U. 13.0.U. 14.0.U. 15.0.U. 16.0.U. 17.0.U. 18.0.U. 19.0.U. 20.0.U. 21.0.U. 22.0.U. 23.0.U. 24.0.U. 25.0.U. 26.0.U. 27.0.U. 28.0.U. 29.0.U. 30.0.U. 31.0.U. 32.0.U. 33.0.U. 34.0.U. 35.0.U. 36.0.U. 37.0.U. 38.0.U. 39.0.U. 40.0.U. 41.0.U. 42.0.U. 43.0.U. 44.0.U. 45.0.U. 46.0.U. 47.0.U. 48.0.U. 49.0.U. 50.0.U. 51.0.U. 52.0.U. 53.0.U. 54.0.U. 55.0.U. 56.0.U. 57.0.U. 58.0.U. 59.0.U. 60.0.U. 61.0.U. 62.0.U. 63.0.U. 64.0.U.

PART ITEMS

REMARK REFNM PTYPENM X Y ORI GLUE MIRROR ALT CLSTID CLSTATTR BROTHERID LABELS REMARK .REUSE. INSTANCE RPART REMARK VISIBLE XLOC YLOC ORI LEVEL HEIGTH WIDTH MIRRORED HJUST VJUST RIGHTREADING REMARK FONTSTYLE FONTFACE

J1 TSOP64@TSOP64-OMEGA2S -15240000 22860000 0.000 U N 0 -1 0 -1 2 VALUE -615000 0 0.000 1 1905000 190500 N LEFT DOWN Regular <Romansim Stroke Font> Ref.Des. VALUE -615000 0 0.000 1 1905000 190500 N LEFT UP Regular <Romansim Stroke Font> Part Type

TESTPOINT

MISC MISCELLANEOUS PARAMETERS

REMARK PARENT_KEYWORD PARENT_VALUE REMARK [ { REMARK CHILD_KEYWORD CHILD_VALUE REMARK [ CHILD_KEYWORD CHILD_VALUE REMARK [ { REMARK GRAND_CHILD_KEYWORD GRAND_CHILD_VALUE […​] REMARK } ]] REMARK } ]

DFT_CONFIGURATION PARENT { UNITS METRIC PROBING_STRATEGY PARENT { PROBE_TOP_SIDE NO PROBE_VIAS YES PROBE_NO_CONNECT NO } DFT_RULES PARENT { PROBE 100 { DRILL_SIZE 1.7526 ENABLE NO } PROBE 75 { DRILL_SIZE 1.0922 ENABLE NO } PROBE 50 { DRILL_SIZE 0.635 ENABLE YES } MIN_VIA_SIZE 0.635 MIN_PAD_SIZE 0.635 PIN_TO_PIN 0.1524 PIN_TO_BOARD 0.1524 PIN_TO_COMPONENT 0.1524 } DIF_FILE PARENT { VIA_PREFIX VIA TP_PART_TYPE TP100 TP_PART_TYPE TP150 TP_PREFIX TP TP_PREFIX PN_TP TP_PREFIX TP_SMD TH_PART_TYPE MTHOLE1 TH_PART_TYPE MTHOLE2 TH_PREFIX TH TH_PREFIX MH NC_NET N.C. INCLUDE_TP YES } RETURN_OPTIONS PARENT { AUTO_RETURN YES ADD_TP_VIAS_ON_RETURN YES ADD_MULTIPLE_FOR_POWERNET NO TP_VIA_TYPE STANDARDVIA PPCB_NOT_CONNECTED_NET_NAME NOT_CONNECTED } } LAYER DATA { LAYER 0 { LAYER_THICKNESS 0 DIELECTRIC 3.300000 } LAYER 1 { LAYER_NAME Top LAYER_TYPE ROUTING PLANE NONE ROUTING_DIRECTION HORIZONTAL ASSOCIATED_SILK_SCREEN Silkscreen Top ASSOCIATED_PASTE_MASK Paste Mask Top ASSOCIATED_SOLDER_MASK Solder Mask Top ASSOCIATED_ASSEMBLY Assembly Drawing Top COMPONENT Y ROUTABLE Y VISIBLE Y SELECTABLE Y ENABLED Y COLORS : { ROUTE 11 VIA 1 PAD 11 COPPER 25 2DLINE 5 TEXT 11 ERROR 15 TOPCOMPONENT 1 BOTTOMCOMPONENT 0 REFDES 1 PARTTYPE 0 ATTRIBUTE 11 KEEPOUT 27 PINNUMBER 1 NETNAME 12 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 381000 COPPER_THICKNESS 51435 DIELECTRIC 4.300000 COST 0 } LAYER 2 { LAYER_NAME Bottom LAYER_TYPE ROUTING PLANE NONE ROUTING_DIRECTION VERTICAL ASSOCIATED_SILK_SCREEN Silkscreen Bottom ASSOCIATED_PASTE_MASK Paste Mask Bottom ASSOCIATED_SOLDER_MASK Solder Mask Bottom ASSOCIATED_ASSEMBLY Assembly Drawing Bottom COMPONENT Y ROUTABLE Y SELECTABLE Y ENABLED Y COLORS : { ROUTE 3 VIA 1 PAD 3 COPPER 28 2DLINE 13 TEXT 3 ERROR 15 TOPCOMPONENT 0 BOTTOMCOMPONENT 27 REFDES 27 PARTTYPE 0 ATTRIBUTE 3 KEEPOUT 20 PINNUMBER 14 NETNAME 11 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 51435 DIELECTRIC 3.300000 COST 0 } LAYER 3 { LAYER_NAME Layer_3 LAYER_TYPE UNASSIGNED PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 0 COPPER 0 2DLINE 0 TEXT 0 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 0 KEEPOUT 0 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 4 { LAYER_NAME Layer_4 LAYER_TYPE UNASSIGNED PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 0 COPPER 0 2DLINE 0 TEXT 0 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 0 KEEPOUT 0 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 5 { LAYER_NAME Layer_5 LAYER_TYPE UNASSIGNED PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 0 COPPER 0 2DLINE 0 TEXT 0 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 0 KEEPOUT 0 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 6 { LAYER_NAME Layer_6 LAYER_TYPE UNASSIGNED PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 0 COPPER 0 2DLINE 0 TEXT 0 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 0 KEEPOUT 0 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 7 { LAYER_NAME Layer_7 LAYER_TYPE UNASSIGNED PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 0 COPPER 0 2DLINE 0 TEXT 0 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 0 KEEPOUT 0 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 8 { LAYER_NAME Layer_8 LAYER_TYPE UNASSIGNED PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 0 COPPER 0 2DLINE 0 TEXT 0 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 0 KEEPOUT 0 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 9 { LAYER_NAME Layer_9 LAYER_TYPE UNASSIGNED PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 0 COPPER 0 2DLINE 0 TEXT 0 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 0 KEEPOUT 0 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 10 { LAYER_NAME Layer_10 LAYER_TYPE UNASSIGNED PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 0 COPPER 0 2DLINE 0 TEXT 0 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 0 KEEPOUT 0 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 11 { LAYER_NAME Layer_11 LAYER_TYPE UNASSIGNED PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 0 COPPER 0 2DLINE 0 TEXT 0 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 0 KEEPOUT 0 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 12 { LAYER_NAME Layer_12 LAYER_TYPE UNASSIGNED PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 0 COPPER 0 2DLINE 0 TEXT 0 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 0 KEEPOUT 0 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 13 { LAYER_NAME Layer_13 LAYER_TYPE UNASSIGNED PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 0 COPPER 0 2DLINE 0 TEXT 0 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 0 KEEPOUT 0 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 14 { LAYER_NAME Layer_14 LAYER_TYPE UNASSIGNED PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 0 COPPER 0 2DLINE 0 TEXT 0 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 0 KEEPOUT 0 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 15 { LAYER_NAME Layer_15 LAYER_TYPE UNASSIGNED PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 0 COPPER 0 2DLINE 0 TEXT 0 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 0 KEEPOUT 0 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 16 { LAYER_NAME Layer_16 LAYER_TYPE UNASSIGNED PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 0 COPPER 0 2DLINE 0 TEXT 0 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 0 KEEPOUT 0 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 17 { LAYER_NAME Layer_17 LAYER_TYPE UNASSIGNED PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 0 COPPER 0 2DLINE 0 TEXT 0 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 0 KEEPOUT 0 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 18 { LAYER_NAME Layer_18 LAYER_TYPE UNASSIGNED PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 0 COPPER 0 2DLINE 0 TEXT 0 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 0 KEEPOUT 0 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 19 { LAYER_NAME Layer_19 LAYER_TYPE UNASSIGNED PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 0 COPPER 25 2DLINE 5 TEXT 1 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 0 KEEPOUT 0 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 20 { LAYER_NAME Layer_20 LAYER_TYPE UNASSIGNED PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 0 COPPER 0 2DLINE 0 TEXT 0 ERROR 0 TOPCOMPONENT 13 BOTTOMCOMPONENT 5 REFDES 0 PARTTYPE 0 ATTRIBUTE 0 KEEPOUT 0 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 21 { LAYER_NAME Solder Mask Top LAYER_TYPE SOLDER_MASK PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 10 PAD 10 COPPER 10 2DLINE 10 TEXT 10 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 10 KEEPOUT 10 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 22 { LAYER_NAME Paste Mask Bottom LAYER_TYPE PASTE_MASK PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 16 PAD 16 COPPER 16 2DLINE 16 TEXT 16 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 16 KEEPOUT 16 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 23 { LAYER_NAME Paste Mask Top LAYER_TYPE PASTE_MASK PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 29 PAD 29 COPPER 29 2DLINE 29 TEXT 29 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 29 KEEPOUT 29 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 24 { LAYER_NAME Drill Drawing LAYER_TYPE DRILL PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 0 COPPER 9 2DLINE 9 TEXT 9 ERROR 0 TOPCOMPONENT 9 BOTTOMCOMPONENT 9 REFDES 0 PARTTYPE 0 ATTRIBUTE 9 KEEPOUT 9 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 25 { LAYER_NAME Layer_25 LAYER_TYPE UNASSIGNED PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 14 PAD 14 COPPER 14 2DLINE 14 TEXT 14 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 14 KEEPOUT 14 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 26 { LAYER_NAME Silkscreen Top LAYER_TYPE SILK_SCREEN PLANE NONE ROUTING_DIRECTION NO_PREFERENCE VISIBLE Y SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 27 COPPER 1 2DLINE 1 TEXT 1 ERROR 0 TOPCOMPONENT 1 BOTTOMCOMPONENT 0 REFDES 1 PARTTYPE 0 ATTRIBUTE 1 KEEPOUT 1 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 27 { LAYER_NAME Assembly Drawing Top LAYER_TYPE ASSEMBLY PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 30 COPPER 30 2DLINE 30 TEXT 30 ERROR 0 TOPCOMPONENT 30 BOTTOMCOMPONENT 0 REFDES 30 PARTTYPE 0 ATTRIBUTE 30 KEEPOUT 30 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 28 { LAYER_NAME Solder Mask Bottom LAYER_TYPE SOLDER_MASK PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 27 PAD 27 COPPER 27 2DLINE 27 TEXT 27 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 0 REFDES 0 PARTTYPE 0 ATTRIBUTE 27 KEEPOUT 27 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 29 { LAYER_NAME Silkscreen Bottom LAYER_TYPE SILK_SCREEN PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 0 COPPER 19 2DLINE 19 TEXT 19 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 19 REFDES 19 PARTTYPE 0 ATTRIBUTE 19 KEEPOUT 19 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } LAYER 30 { LAYER_NAME Assembly Drawing Bottom LAYER_TYPE ASSEMBLY PLANE NONE ROUTING_DIRECTION NO_PREFERENCE SELECTABLE Y ENABLED Y COLORS : { ROUTE 0 VIA 0 PAD 17 COPPER 17 2DLINE 17 TEXT 17 ERROR 0 TOPCOMPONENT 0 BOTTOMCOMPONENT 17 REFDES 17 PARTTYPE 0 ATTRIBUTE 17 KEEPOUT 17 PINNUMBER 0 NETNAME 0 TOPPLACEMENT 0 BOTTOMPLACEMENT 0 } LAYER_THICKNESS 0 COPPER_THICKNESS 0 DIELECTRIC 0.000000 COST 0 } } SELECTABILITY DATA { PARTS Y PINS Y TRACES Y VIAS Y TACKS Y UNROUTED Y EDGES Y NODES Y SHAPES Y DIMENSIONS Y TEXT Y AREA_PARTS Y AREA_PINS Y AREA_TRACES Y AREA_VIAS Y AREA_TACKS Y AREA_UNROUTED Y AREA_EDGES Y AREA_NODES Y AREA_SHAPES Y AREA_DIMENSIONS Y AREA_TEXT Y } VISIBILITY DATA { PADS Y TRACKS Y VIAS Y COPPER Y LINES Y TEXT Y ERRORS Y CLUSTER Y TOP_COMPONENT Y BOTTOM_COMPONENT Y PLANE_THERMAL Y REFDES Y PARTTYPES Y ATTRIBUTES Y KEEPOUTS Y SELECTION_COLOR 15 HIGHLIGHT_COLOR 14 FIXED_COLOR 3 FONT_FACE <Romansim Stroke Font> { } }

MISC MISCELLANEOUS PARAMETERS

REMARK PARENT_KEYWORD PARENT_VALUE REMARK [ { REMARK CHILD_KEYWORD CHILD_VALUE REMARK [ CHILD_KEYWORD CHILD_VALUE REMARK [ { REMARK GRAND_CHILD_KEYWORD GRAND_CHILD_VALUE […​] REMARK } ]] REMARK } ]

RULES_SECTION PARENT { NET_CLASS DATA GROUP DATA ASSOCIATED_NET DATA DESIGN RULES { RULE_SET (1) { FOR : { DEFAULT : } AGAINST : { DEFAULT : } LAYER 0 CLEARANCE_RULE : { TRACK_TO_TRACK 228600 VIA_TO_TRACK 228600 VIA_TO_VIA 228600 PAD_TO_TRACK 228600 PAD_TO_VIA 228600 PAD_TO_PAD 228600 SMD_TO_TRACK 228600 SMD_TO_VIA 228600 SMD_TO_PAD 228600 SMD_TO_SMD 228600 COPPER_TO_TRACK 228600 COPPER_TO_VIA 228600 COPPER_TO_PAD 228600 COPPER_TO_SMD 228600 COPPER_TO_COPPER 228600 TEXT_TO_TRACK 228600 TEXT_TO_VIA 228600 TEXT_TO_PAD 228600 TEXT_TO_SMD 228600 OUTLINE_TO_TRACK 228600 OUTLINE_TO_VIA 228600 OUTLINE_TO_PAD 228600 OUTLINE_TO_SMD 228600 OUTLINE_TO_COPPER 228600 DRILL_TO_TRACK 228600 DRILL_TO_VIA 228600 DRILL_TO_PAD 228600 DRILL_TO_SMD 228600 DRILL_TO_COPPER 228600 SAME_NET_SMD_TO_VIA 228600 SAME_NET_SMD_TO_CRN 228600 SAME_NET_VIA_TO_VIA 228600 SAME_NET_PAD_TO_CRN 228600 MIN_TRACK_WIDTH 457200 REC_TRACK_WIDTH 457200 MAX_TRACK_WIDTH 457200 DRILL_TO_DRILL 228600 BODY_TO_BODY 228600 SAME_NET_TRACK_TO_CRN 0 } } RULE_SET (2) { FOR : { DEFAULT : } AGAINST : { DEFAULT : } LAYER 0 HIGH_SPEED_RULE : { MIN_LENGTH 0 MAX_LENGTH 1904999936 STUB_LENGTH 0 PARALLEL_LENGTH 38100000 PARALLEL_GAP 7620000 TANDEM_LENGTH 38100000 TANDEM_GAP 7620000 MIN_DELAY 0.000000 MAX_DELAY 10.000000 MIN_CAPACITANCE 0.000000 MAX_CAPACITANCE 10.000000 MIN_IMPEDANCE 50.000000 MAX_IMPEDANCE 150.000000 SHIELD_NET * SHIELD_GAP 7620000 MATCH_LENGTH_TOLERANCE 7620000 } } RULE_SET (3) { FOR : { DEFAULT : } AGAINST : { DEFAULT : } LAYER 0 ROUTE_RULE : { LENGTH_MINIMIZATION_TYPE 1 VIA_SHARE Y TRACE_SHARE Y AUTO_ROUTE Y RIPUP Y SHOVE Y ROUTE_PRIORITY 3 MAX_NUMBER_OF_VIAS -1 VALID_LAYER 1 VALID_LAYER 2 VALID_VIA_TYPE STANDARDVIA } } } }

MISC MISCELLANEOUS PARAMETERS

REMARK PARENT_KEYWORD PARENT_VALUE REMARK [ { REMARK CHILD_KEYWORD CHILD_VALUE REMARK [ CHILD_KEYWORD CHILD_VALUE REMARK [ { REMARK GRAND_CHILD_KEYWORD GRAND_CHILD_VALUE […​] REMARK } ]] REMARK } ]

CAM_SECTION PARENT { CAM_VERSION V2007.0 CAM_DOC_LIST PARENT { } CAM_AUGMENT_ON_THE_FLY Y CAM_DRILL_SYMBOL_TABLE_EXTENDED PARENT { MARKER_SIZE 3048000 MARKER_LINE_WIDTH 381000 MARKER_CHAR_HEIGHT 1905000 CHART_TEXT_HEIGHT 4572000 CHART_LINE_WIDTH 381000 SIZE_VALUES_SORTING_ORDER 0 QUANTITY_VALUES_SORTING_ORDER 0 PLATED_VALUES_SORTING_ORDER 0 DEFAULT_TOLERANCE +/-0.0 DRILL_UNIT 1 THROUGH_PARTIAL N } }

MISC MISCELLANEOUS PARAMETERS

REMARK PARENT_KEYWORD PARENT_VALUE REMARK [ { REMARK CHILD_KEYWORD CHILD_VALUE REMARK [ CHILD_KEYWORD CHILD_VALUE REMARK [ { REMARK GRAND_CHILD_KEYWORD GRAND_CHILD_VALUE […​] REMARK } ]] REMARK } ]

MISC MISCELLANEOUS PARAMETERS

ATTRIBUTES DICTIONARY { ATTRIBUTE Rules.Fanout.Alignment { TYPE LIST N { Aligned Alternate } INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Fanout.Alignment.Multi-Row { TYPE BOOLEAN INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Fanout.Direction { TYPE LIST N { Inside Outside Both Sides } INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Fanout.ViaSpacing { TYPE LIST N { Use Grid 1 Trace 2 Trace } INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Fanout.Sharing.Pin { TYPE BOOLEAN INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Fanout.Sharing.SMD { TYPE BOOLEAN INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Fanout.Sharing.Via { TYPE BOOLEAN INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Fanout.Sharing.Trace { TYPE BOOLEAN INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Fanout.Nets.Plane { TYPE BOOLEAN INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Fanout.Nets.Signal { TYPE BOOLEAN INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Fanout.Nets.UnusedPins { TYPE BOOLEAN INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Fanout.Length.Unlimited { TYPE BOOLEAN INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Fanout.Length.Maximum { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 76200000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Fanout.AlignmentBGA { TYPE LIST N { Diagonal Quadrant X-pattern } INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Fanout.DirectionBGA { TYPE LIST N { 45 135 225 315 Clockwise Counterclockwise } INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Fanout.DirectionBGAstaggered { TYPE LIST N { Horizontal Vertical } INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.PadEntry.Side { TYPE BOOLEAN INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.PadEntry.Corner { TYPE BOOLEAN INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.PadEntry.AnyAngle { TYPE BOOLEAN INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.PadEntry.Soft { TYPE BOOLEAN INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.ViaAtSMD { TYPE BOOLEAN INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.ViaAtSMD.FitInside { TYPE BOOLEAN INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.ViaAtSMD.Center { TYPE BOOLEAN INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.ViaAtSMD.Ends { TYPE BOOLEAN INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Trace.Trace { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Via.Trace { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Via.Via { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Pad.Trace { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Pad.Via { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Pad.Pad { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.SMD.Trace { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.SMD.Via { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.SMD.Pad { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.SMD.SMD { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Copper.Trace { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Copper.Via { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Copper.Pad { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Copper.SMD { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Text.Trace { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Text.Via { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Text.Pad { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Text.SMD { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Board.Trace { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Board.Via { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Board.Pad { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Board.SMD { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Drill.Trace { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Drill.Via { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Drill.Pad { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Clearance.Drill.SMD { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.SameNet.SMD.Via { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.SameNet.SMD.Crn { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.SameNet.Via.Via { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.SameNet.Pad.Crn { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.SameNet.Trace.Crn { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Width.Minimum { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 9525000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Width.Recommended { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 9525000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Rules.Width.Maximum { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 9525000dbunit INHERITANCE PCB INHERITANCE PART DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Value { TYPE FREETEXT N INHERITANCE PART PARTTYPE ECO_REGISTRATION Y READONLY N SYSTEM Y HIDDEN N } ATTRIBUTE Tolerance { TYPE FREETEXT N INHERITANCE PART PARTTYPE ECO_REGISTRATION Y READONLY N SYSTEM Y HIDDEN N } ATTRIBUTE Part Number { TYPE FREETEXT N INHERITANCE PART PARTTYPE ECO_REGISTRATION Y READONLY N SYSTEM N HIDDEN N } ATTRIBUTE Description { TYPE FREETEXT N INHERITANCE PART PARTTYPE ECO_REGISTRATION Y READONLY N SYSTEM N HIDDEN N } ATTRIBUTE Cost { TYPE FREETEXT N INHERITANCE PART PARTTYPE ECO_REGISTRATION Y READONLY N SYSTEM N HIDDEN N } ATTRIBUTE Manufacturer #1 { TYPE FREETEXT N INHERITANCE PART PARTTYPE ECO_REGISTRATION Y READONLY N SYSTEM N HIDDEN N } ATTRIBUTE Manufacturer #2 { TYPE FREETEXT N INHERITANCE PART PARTTYPE ECO_REGISTRATION Y READONLY N SYSTEM N HIDDEN N } ATTRIBUTE ASSEMBLY_OPTIONS { TYPE FREETEXT N INHERITANCE PCB INHERITANCE PART INHERITANCE JUMPER ECO_REGISTRATION Y READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE PowerGround { TYPE BOOLEAN INHERITANCE NET NETCLASS PCB ECO_REGISTRATION Y READONLY N SYSTEM Y HIDDEN N } ATTRIBUTE Voltage { TYPE QUANTITY QUANTITY Voltage ABBR V UNIT Volt MIN -100kV MAX 100kV INHERITANCE NET NETCLASS ECO_REGISTRATION Y READONLY N SYSTEM Y HIDDEN N } ATTRIBUTE Geometry.Height { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 952500000dbunit INHERITANCE PCB INHERITANCE PART PARTTYPE DECAL ECO_REGISTRATION N READONLY N SYSTEM Y HIDDEN N } ATTRIBUTE DFT.Nail Count Per Net { TYPE INTEGER MIN 0 MAX 1000 INHERITANCE NET NETCLASS PCB ECO_REGISTRATION Y READONLY N SYSTEM Y HIDDEN N } ATTRIBUTE DFT.Nail Diameter { TYPE FREETEXT N INHERITANCE PIN INHERITANCE VIA ECO_REGISTRATION N READONLY N SYSTEM Y HIDDEN N } ATTRIBUTE DFT.Nail Number { TYPE FREETEXT N INHERITANCE PIN INHERITANCE VIA ECO_REGISTRATION N READONLY N SYSTEM Y HIDDEN N } ATTRIBUTE DFT.Probe to Trace Clearance { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DFT.Probe to Pad Clearance { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 38100000dbunit INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DFT.Generate Test Points { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DFT.Allow Stubs { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DFT.Stub Length { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 76200000dbunit INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DFT.Use Via Grid { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DFT.Grid X-Coordinate { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 76200000dbunit INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DFT.Grid Y-Coordinate { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 76200000dbunit INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DFT.Preserve Test Points { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DFT.Insert Test Point Vias { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DFT.Probe Pins { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE HyperLynx.Model { TYPE FREETEXT N INHERITANCE PART PARTTYPE ECO_REGISTRATION Y READONLY N SYSTEM Y HIDDEN N } ATTRIBUTE HyperLynx.Model File { TYPE FREETEXT N INHERITANCE PART PARTTYPE ECO_REGISTRATION Y READONLY N SYSTEM Y HIDDEN N } ATTRIBUTE HyperLynx.Sim Direction { TYPE LIST N { SIM_BOTH SIM_IN SIM_OUT } INHERITANCE PIN ECO_REGISTRATION Y READONLY N SYSTEM Y HIDDEN N } ATTRIBUTE HyperLynx.Frequency { TYPE QUANTITY QUANTITY Frequency ABBR Hz UNIT Hertz MIN 0Hz MAX 1000GHz INHERITANCE NET NETCLASS ECO_REGISTRATION Y READONLY N SYSTEM Y HIDDEN N } ATTRIBUTE HyperLynx.Duty Cycle { TYPE QUANTITY QUANTITY ABBR % UNIT percent MIN 0% MAX 100% INHERITANCE NET NETCLASS ECO_REGISTRATION Y READONLY N SYSTEM Y HIDDEN N } ATTRIBUTE HyperLynx.Signal Type { TYPE LIST N { Address Analog High Speed Analog Low Speed Clock Data Do Not Analyze Power Supply Strobe } INHERITANCE NET NETCLASS ECO_REGISTRATION Y READONLY N SYSTEM Y HIDDEN N } ATTRIBUTE HyperLynx.Default IC.Model { TYPE FREETEXT N INHERITANCE NET NETCLASS ECO_REGISTRATION Y READONLY N SYSTEM Y HIDDEN N } ATTRIBUTE HyperLynx.Default IC.Model File { TYPE FREETEXT N INHERITANCE NET NETCLASS ECO_REGISTRATION Y READONLY N SYSTEM Y HIDDEN N } ATTRIBUTE HyperLynx.Default IC.Model Pin { TYPE FREETEXT N INHERITANCE NET NETCLASS ECO_REGISTRATION Y READONLY N SYSTEM Y HIDDEN N } ATTRIBUTE Strategy.Fanout.Pass { TYPE LIST N { No Yes Done } INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Fanout.Protect { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Fanout.Pause { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Fanout.Intensity { TYPE LIST N { Low Medium High } INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Fanout.Priority { TYPE INTEGER MIN 0 INHERITANCE NET NETCLASS PCB INHERITANCE PART INHERITANCE PINPAIR ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Fanout.PlanePriority { TYPE INTEGER MIN 0 INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Fanout.DiffPairPriority { TYPE INTEGER MIN 0 INHERITANCE NET INHERITANCE PINPAIR ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Fanout.MLGPriority { TYPE INTEGER MIN 0 INHERITANCE NET NETCLASS PCB INHERITANCE PINPAIR GROUP ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Patterns.Pass { TYPE LIST N { No Yes Done } INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Patterns.Protect { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Patterns.Pause { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Patterns.Intensity { TYPE LIST N { Low Medium High } INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Patterns.Priority { TYPE INTEGER MIN 0 INHERITANCE NET NETCLASS PCB INHERITANCE PART INHERITANCE PINPAIR ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Patterns.PlanePriority { TYPE INTEGER MIN 0 INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Patterns.DiffPairPriority { TYPE INTEGER MIN 0 INHERITANCE NET INHERITANCE PINPAIR ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Patterns.MLGPriority { TYPE INTEGER MIN 0 INHERITANCE NET NETCLASS PCB INHERITANCE PINPAIR GROUP ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Route.Pass { TYPE LIST N { No Yes Done } INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Route.Protect { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Route.Pause { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Route.Intensity { TYPE LIST N { Low Medium High } INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Route.Priority { TYPE INTEGER MIN 0 INHERITANCE NET NETCLASS PCB INHERITANCE PART INHERITANCE PINPAIR ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Route.PlanePriority { TYPE INTEGER MIN 0 INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Route.DiffPairPriority { TYPE INTEGER MIN 0 INHERITANCE NET INHERITANCE PINPAIR ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Route.MLGPriority { TYPE INTEGER MIN 0 INHERITANCE NET NETCLASS PCB INHERITANCE PINPAIR GROUP ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Optimize.Pass { TYPE LIST N { No Yes Done } INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Optimize.Protect { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Optimize.Pause { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Optimize.Intensity { TYPE LIST N { Low Medium High } INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Optimize.Priority { TYPE INTEGER MIN 0 INHERITANCE NET NETCLASS PCB INHERITANCE PART INHERITANCE PINPAIR ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Optimize.PlanePriority { TYPE INTEGER MIN 0 INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Optimize.DiffPairPriority { TYPE INTEGER MIN 0 INHERITANCE NET INHERITANCE PINPAIR ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Optimize.MLGPriority { TYPE INTEGER MIN 0 INHERITANCE NET NETCLASS PCB INHERITANCE PINPAIR GROUP ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Miters.Pass { TYPE LIST N { No Yes Done } INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Miters.Protect { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Miters.Pause { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Miters.Intensity { TYPE LIST N { Low Medium High } INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Miters.Priority { TYPE INTEGER MIN 0 INHERITANCE NET NETCLASS PCB INHERITANCE PART INHERITANCE PINPAIR ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Miters.PlanePriority { TYPE INTEGER MIN 0 INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Miters.DiffPairPriority { TYPE INTEGER MIN 0 INHERITANCE NET INHERITANCE PINPAIR ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Miters.MLGPriority { TYPE INTEGER MIN 0 INHERITANCE NET NETCLASS PCB INHERITANCE PINPAIR GROUP ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.TestPoint.Pass { TYPE LIST N { No Yes Done } INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.TestPoint.Protect { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.TestPoint.Pause { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.TestPoint.Intensity { TYPE LIST N { Low Medium High } INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.TestPoint.Priority { TYPE INTEGER MIN 0 INHERITANCE NET NETCLASS PCB INHERITANCE PART INHERITANCE PINPAIR ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.TestPoint.PlanePriority { TYPE INTEGER MIN 0 INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.TestPoint.DiffPairPriority { TYPE INTEGER MIN 0 INHERITANCE NET INHERITANCE PINPAIR ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.TestPoint.MLGPriority { TYPE INTEGER MIN 0 INHERITANCE NET NETCLASS PCB INHERITANCE PINPAIR GROUP ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Center.Pass { TYPE LIST N { No Yes Done } INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Center.Protect { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Center.Pause { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Center.Intensity { TYPE LIST N { Low Medium High } INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Center.PlanePriority { TYPE INTEGER MIN 0 INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Center.Priority { TYPE INTEGER MIN 0 INHERITANCE NET NETCLASS PCB INHERITANCE PART INHERITANCE PINPAIR ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Center.DiffPairPriority { TYPE INTEGER MIN 0 INHERITANCE NET INHERITANCE PINPAIR ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Center.MLGPriority { TYPE INTEGER MIN 0 INHERITANCE NET NETCLASS PCB INHERITANCE PINPAIR GROUP ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Tune.Pass { TYPE LIST N { No Yes Done } INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Tune.Protect { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Tune.Pause { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Tune.Intensity { TYPE LIST N { Low Medium High } INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Tune.PlanePriority { TYPE INTEGER MIN 0 INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Tune.Priority { TYPE INTEGER MIN 0 INHERITANCE NET NETCLASS PCB INHERITANCE PART INHERITANCE PINPAIR ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Tune.DiffPairPriority { TYPE INTEGER MIN 0 INHERITANCE NET INHERITANCE PINPAIR ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Strategy.Tune.MLGPriority { TYPE INTEGER MIN 0 INHERITANCE NET NETCLASS PCB INHERITANCE PINPAIR GROUP ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DIE.FormatId { TYPE FREETEXT N INHERITANCE DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DIE.ChipLength { TYPE FREETEXT N INHERITANCE DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DIE.ChipWidth { TYPE FREETEXT N INHERITANCE DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DIE.ChipHeight { TYPE FREETEXT N INHERITANCE DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DIE.WBRules.MinLength { TYPE FREETEXT N INHERITANCE DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DIE.WBRules.MaxLength { TYPE FREETEXT N INHERITANCE DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DIE.WBRules.WToWDistance { TYPE FREETEXT N INHERITANCE DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DIE.WBRules.WBtoPad { TYPE FREETEXT N INHERITANCE DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DIE.WBRules.MaxAngle { TYPE FREETEXT N INHERITANCE DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DIE.SBPCount { TYPE FREETEXT N INHERITANCE DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DIE.SBP1 { TYPE FREETEXT N INHERITANCE DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DIE.CBPCount { TYPE FREETEXT N INHERITANCE DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DIE.CBP1 { TYPE FREETEXT N INHERITANCE DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DIE.WBCount { TYPE FREETEXT N INHERITANCE DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DIE.WB1 { TYPE FREETEXT N INHERITANCE DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DIE.SBPGuideCount { TYPE FREETEXT N INHERITANCE DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DIE.SBPGuide1 { TYPE FREETEXT N INHERITANCE DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DIE.CBPAssignment1 { TYPE FREETEXT N INHERITANCE DECAL ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE AutoDimensioning.Marker_Shape { TYPE FREETEXT N INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE AutoDimensioning.Text_NumberPrecision { TYPE FREETEXT N INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE AutoDimensioning.Text_AngularPrecision { TYPE FREETEXT N INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE AutoDimensioning.Text_Suffix { TYPE FREETEXT N INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE AutoDimensioning.Text_Layer { TYPE INTEGER MIN 0 MAX 250 INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE AutoDimensioning.Line_Layer { TYPE INTEGER MIN 0 MAX 250 INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE AutoDimensioning.Preview_Type { TYPE INTEGER MIN 1 MAX 5 INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Placement.Grid.Use { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Placement.Grid.X { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 76200000dbunit INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Placement.Grid.Y { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 76200000dbunit INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Accordion.Amplitude.Min { TYPE INTEGER MIN 3 MAX 300 INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Accordion.Amplitude.Max { TYPE INTEGER MIN 4 MAX 300 INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Accordion.Gap.Min { TYPE INTEGER MIN 1 MAX 10 INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Accordion.HierarchyLevel { TYPE INTEGER MIN 1 MAX 8 INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Accordion.Miters.Arcs { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Accordion.Miters.Ratio { TYPE FLOAT MIN 0.5 MAX 250 INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Routing.MaxChannelWidth { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN 0dbunit MAX 381000000dbunit INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Routing.SoftLengthRrules { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Routing.MeanderBeforeTune { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Routing.ExtraLengthPercent { TYPE INTEGER MIN 0 MAX 100 INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE MatchLength.Name { TYPE FREETEXT N INHERITANCE NET NETCLASS INHERITANCE PINPAIR GROUP ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Planning.Scheduled { TYPE BOOLEAN INHERITANCE NET ECO_REGISTRATION Y READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Library.Timestamp { TYPE FREETEXT N INHERITANCE DECAL INHERITANCE PARTTYPE ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Design.Timestamp { TYPE FREETEXT N INHERITANCE DECAL INHERITANCE PARTTYPE ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DiffPair.RestrictPairTuneInGap { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DiffPair.RestrictSmallAccordionsInPairs { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE DiffPair.TunePairsToZeroTolerance { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE CAM.Solder mask.Adjust { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN -9525000dbunit MAX 9525000dbunit INHERITANCE PCB INHERITANCE PART DECAL INHERITANCE VIA ECO_REGISTRATION N READONLY N SYSTEM Y HIDDEN N } ATTRIBUTE CAM.Paste mask.Adjust { TYPE QUANTITY QUANTITY Size/Dimension ABBR UNIT MIN -9525000dbunit MAX 9525000dbunit INHERITANCE PCB INHERITANCE PART DECAL INHERITANCE VIA ECO_REGISTRATION N READONLY N SYSTEM Y HIDDEN N } ATTRIBUTE CAM.Apply Oversize To All Pads { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY N SYSTEM Y HIDDEN N } ATTRIBUTE CHK.Use Visible Workspace Box for Latium Checking { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY N SYSTEM Y HIDDEN Y } ATTRIBUTE Single Sided Board { TYPE BOOLEAN INHERITANCE PCB ECO_REGISTRATION N READONLY N SYSTEM Y HIDDEN Y } ATTRIBUTE DxDesigner.ProjectFilePath { TYPE FREETEXT N INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE iCDB.DesignName { TYPE FREETEXT N INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE iCDB.RootBlock { TYPE FREETEXT N INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE iCDB.MainSnapshotName { TYPE FREETEXT N INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE iCDB.TempSnapshotName { TYPE FREETEXT N INHERITANCE PCB ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE Bridges { TYPE FREETEXT N INHERITANCE NET ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE AssociatedNetAssociateNets { TYPE BOOLEAN INHERITANCE NET INHERITANCE PART ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE AssociatedNetAllowPrefix { TYPE BOOLEAN INHERITANCE NET INHERITANCE PART ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } ATTRIBUTE AssociatedNetDiscreteLength { TYPE FLOAT INHERITANCE PCB INHERITANCE PART ECO_REGISTRATION N READONLY Y SYSTEM Y HIDDEN Y } } ATTRIBUTE VALUES { DECAL TSOP64 { Design.Timestamp 2017.10.12.09.00.04 } DECAL TSOP64-OMEGA2S { Design.Timestamp 2020.04.01.12.31.56 } PARTTYPE TSOP64 { Design.Timestamp 2017.10.12.08.09.51 } PCB DEFAULT { Accordion.Amplitude.Min 3 Accordion.Gap.Min 1 AutoDimensioning.Line_Layer 24 AutoDimensioning.Marker_Shape YYNNNY AutoDimensioning.Preview_Type 1 AutoDimensioning.Text_AngularPrecision 0 0 0 AutoDimensioning.Text_Layer 24 AutoDimensioning.Text_NumberPrecision 3 1 2 AutoDimensioning.Text_Suffix milmm" "CAM.Apply Oversize To All Pads" Yes "DFT.Allow Stubs" Yes "DFT.Generate Test Points" No "DFT.Grid X-Coordinate" 952500dbunit "DFT.Grid Y-Coordinate" 952500dbunit "DFT.Insert Test Point Vias" No "DFT.Preserve Test Points" No "DFT.Probe Pins" Yes "DFT.Probe to Pad Clearance" 228600dbunit "DFT.Probe to Trace Clearance" 228600dbunit "DFT.Stub Length" 19050000dbunit "DFT.Use Via Grid" Yes Placement.Grid.Use No Placement.Grid.X 3810000dbunit Placement.Grid.Y 3810000dbunit Routing.MaxChannelWidth 3810000dbunit Routing.MeanderBeforeTune No Routing.SoftLengthRrules Yes Rules.ViaAtSMD No Rules.Fanout.Length.Maximum 9525000dbunit Rules.Fanout.Length.Unlimited Yes Rules.Fanout.Nets.Plane Yes Rules.Fanout.Nets.Signal No Rules.Fanout.Nets.UnusedPins No Rules.Fanout.Sharing.Pin Yes Rules.Fanout.Sharing.SMD Yes Rules.Fanout.Sharing.Trace No Rules.Fanout.Sharing.Via Yes Rules.PadEntry.AnyAngle Yes Rules.PadEntry.Corner Yes Rules.PadEntry.Side Yes Rules.PadEntry.Soft Yes Rules.ViaAtSMD.Center Yes Rules.ViaAtSMD.Ends Yes Rules.ViaAtSMD.FitInside Yes } }

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