From 53698182920fbb7ab7f437359ecbf0fe77481716 Mon Sep 17 00:00:00 2001 From: Fernando Mosquera Date: Wed, 18 Dec 2024 09:08:29 -0600 Subject: [PATCH 1/4] Added Mimas ECP5 Mini board Following the Apio requirements --- app/resources/boards/Mimas-ECP5-Mini/info.json | 2 +- app/resources/boards/menu.json | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/app/resources/boards/Mimas-ECP5-Mini/info.json b/app/resources/boards/Mimas-ECP5-Mini/info.json index fcaf32bd0..e4162e770 100644 --- a/app/resources/boards/Mimas-ECP5-Mini/info.json +++ b/app/resources/boards/Mimas-ECP5-Mini/info.json @@ -1 +1 @@ -{"label":"Mimas-ECP5-Mini","SysClkMhz":100,"datasheet":"https://numato.com/docs/mimas-ecp5-mini-fpga-development-board","interface":"FTDI","arch":"ecp5","FPGAResources":{"ffs":5280,"luts":5280,"pios":39,"plbs":660,"brams":30}} \ No newline at end of file +{"label":"Mimas ECP5 Mini","SysClkMhz":100,"datasheet":"https://numato.com/docs/mimas-ecp5-mini-fpga-development-board","interface":"FTDI","arch":"ecp5","FPGAResources":{"ffs":5280,"luts":5280,"pios":39,"plbs":660,"brams":30}} \ No newline at end of file diff --git a/app/resources/boards/menu.json b/app/resources/boards/menu.json index 49b44595b..dd544195b 100644 --- a/app/resources/boards/menu.json +++ b/app/resources/boards/menu.json @@ -1 +1 @@ -[{"type":"HX1K","boards":["icezum","go-board","icestick"]},{"type":"HX8K","boards":["Alchitry-Cu","alhambra-ii","blackice","blackice-ii","blackice-mx","edu-ciaa-fpga","icoboard","kefir","iCE40-HX8K","icefun","iceWerx","ThetaMachines-ETH4K"]},{"type":"LP8K","boards":["TinyFPGA-B2","TinyFPGA-BX"]},{"type":"LP1K","boards":["iCESugar-nano"]},{"type":"U4K","boards":["ODT_IcyBlue_Feather", "ODT_RPGA_Feather"]},{"type":"UP5K","boards":["MCH2022_badge","iCEBreaker","iCEBreaker-bitsy0","iCEBreaker-bitsy1","upduino","upduino2","upduino21","upduino3","upduino31","fpga101","iCE40-UP5K","fomu","iCESugar_1_5","OK-iCE40Pro","pico-ice"]},{"type":"ECP5","boards":["ulx3s-12f","ulx3s-25f","ulx3s-45f","ulx3s-85f","Butterstick-r10-2g-85k","Butterstick-r10-2g-85k_(FT2232H)","Butterstick-r10-2g-85k_(FT232H)","orangecrab-r02-25f","orangecrab-r02-85f","ColorLight-5A-75B-V61","ColorLight-5A-75B-V7","ColorLight-5A-75B-V8","ColorLight-5A-75E-V6","ColorLight-5A-75E-V71_(FT2232H)","ColorLight-5A-75E-V71_(FT232H)","ColorLight-5A-75E-V71_(USB-Blaster)","ColorLight-i5-v7.0_(FT2232H)","ColorLight-i5-v7.0_(FT232H)","ColorLight-i5-v7.0_(USB-Blaster)","iCESugar-Pro_(FT2232H)","iCESugar-Pro_(FT232H)","iCESugar-Pro_(USB-Blaster)","FleaFPGA-Ohm_(FT2232H)","FleaFPGA-Ohm_(FT232H)","FleaFPGA-Ohm_(USB-Blaster)","ECP5-Evaluation-Board","ECP5-Mini-12_(FT2232H)","ECP5-Mini-25_(FT2232H)","ColorLight-i9-v7.2_(FT2232H)","ColorLight-i9-v7.2_(FT232H)","ColorLight-i9-v7.2_(USB-Blaster)","Cynthion-r1.4","Mimas-ECP5-Mini"]}] +[{"type":"HX1K","boards":["icezum","go-board","icestick"]},{"type":"HX8K","boards":["Alchitry-Cu","alhambra-ii","blackice","blackice-ii","blackice-mx","edu-ciaa-fpga","icoboard","kefir","iCE40-HX8K","icefun","iceWerx","ThetaMachines-ETH4K"]},{"type":"LP8K","boards":["TinyFPGA-B2","TinyFPGA-BX"]},{"type":"LP1K","boards":["iCESugar-nano"]},{"type":"U4K","boards":["ODT_IcyBlue_Feather", "ODT_RPGA_Feather"]},{"type":"UP5K","boards":["MCH2022_badge","iCEBreaker","iCEBreaker-bitsy0","iCEBreaker-bitsy1","upduino","upduino2","upduino21","upduino3","upduino31","fpga101","iCE40-UP5K","fomu","iCESugar_1_5","OK-iCE40Pro","pico-ice"]},{"type":"ECP5","boards":["ulx3s-12f","ulx3s-25f","ulx3s-45f","ulx3s-85f","Butterstick-r10-2g-85k","Butterstick-r10-2g-85k_(FT2232H)","Butterstick-r10-2g-85k_(FT232H)","orangecrab-r02-25f","orangecrab-r02-85f","ColorLight-5A-75B-V61","ColorLight-5A-75B-V7","ColorLight-5A-75B-V8","ColorLight-5A-75E-V6","ColorLight-5A-75E-V71_(FT2232H)","ColorLight-5A-75E-V71_(FT232H)","ColorLight-5A-75E-V71_(USB-Blaster)","ColorLight-i5-v7.0_(FT2232H)","ColorLight-i5-v7.0_(FT232H)","ColorLight-i5-v7.0_(USB-Blaster)","iCESugar-Pro_(FT2232H)","iCESugar-Pro_(FT232H)","iCESugar-Pro_(USB-Blaster)","FleaFPGA-Ohm_(FT2232H)","FleaFPGA-Ohm_(FT232H)","FleaFPGA-Ohm_(USB-Blaster)","ECP5-Evaluation-Board","ECP5-Mini-12_(FT2232H)","ECP5-Mini-25_(FT2232H)","ColorLight-i9-v7.2_(FT2232H)","ColorLight-i9-v7.2_(FT232H)","ColorLight-i9-v7.2_(USB-Blaster)","Cynthion-r1.4","mimas-ecp5-mini"]}] From 6abcbcc9493713c9cfc8d89af9b64ebe9432ae4f Mon Sep 17 00:00:00 2001 From: Fernando Mosquera Date: Wed, 18 Dec 2024 09:10:47 -0600 Subject: [PATCH 2/4] Delete app/resources/boards/Mimas-ECP5-Mini directory Delete directory with Upercases name to substitute later by lowecases name --- .../boards/Mimas-ECP5-Mini/info.json | 1 - .../boards/Mimas-ECP5-Mini/pinout.json | 944 ------------------ .../boards/Mimas-ECP5-Mini/rules.json | 1 - 3 files changed, 946 deletions(-) delete mode 100644 app/resources/boards/Mimas-ECP5-Mini/info.json delete mode 100644 app/resources/boards/Mimas-ECP5-Mini/pinout.json delete mode 100644 app/resources/boards/Mimas-ECP5-Mini/rules.json diff --git a/app/resources/boards/Mimas-ECP5-Mini/info.json b/app/resources/boards/Mimas-ECP5-Mini/info.json deleted file mode 100644 index e4162e770..000000000 --- a/app/resources/boards/Mimas-ECP5-Mini/info.json +++ /dev/null @@ -1 +0,0 @@ -{"label":"Mimas ECP5 Mini","SysClkMhz":100,"datasheet":"https://numato.com/docs/mimas-ecp5-mini-fpga-development-board","interface":"FTDI","arch":"ecp5","FPGAResources":{"ffs":5280,"luts":5280,"pios":39,"plbs":660,"brams":30}} \ No newline at end of file diff --git a/app/resources/boards/Mimas-ECP5-Mini/pinout.json b/app/resources/boards/Mimas-ECP5-Mini/pinout.json deleted file mode 100644 index fd92e15b8..000000000 --- a/app/resources/boards/Mimas-ECP5-Mini/pinout.json +++ /dev/null @@ -1,944 +0,0 @@ -[ - { - "type": "input", - "name": "clk", - "value": "C7" - }, - { - "type": "output", - "name": "led_4", - "value": "C13" - }, - { - "type": "output", - "name": "led_3", - "value": "D12" - }, - { - "type": "output", - "name": "led_2", - "value": "D13" - }, - { - "type": "output", - "name": "led_1", - "value": "E12" - }, - { - "type": "output", - "name": "led_r_n", - "value": "T6" - }, - { - "type": "output", - "name": "led_g_n", - "value": "R6" - }, - { - "type": "output", - "name": "led_b_n", - "value": "R7" - }, - { - "type": "input", - "name": "sw_1", - "value": "A8" - }, - { - "type": "input", - "name": "sw_2", - "value": "A7" - }, - { - "type": "input", - "name": "sw_3", - "value": "A15" - }, - { - "type": "input", - "name": "sw_4", - "value": "B14" - }, - { - "type": "inout", - "name": "flash_clk", - "value": "U3", - "pullmode": "DOWN" - }, - { - "type": "inout", - "name": "flash_mosi", - "value": "W2", - "pullmode": "UP" - }, - { - "type": "inout", - "name": "flash_miso", - "value": "V2", - "pullmode": "UP" - }, - { - "type": "inout", - "name": "flash_holdn", - "value": "W1", - "pullmode": "UP" - }, - { - "type": "inout", - "name": "flash_wpn", - "value": "Y2", - "pullmode": "UP" - }, - { - "type": "inout", - "name": "P7_D0", - "value": "D11", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P7_D1", - "value": "E11", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P7_D2", - "value": "A9", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P7_D3", - "value": "A10", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P7_D4", - "value": "B12", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P7_D5", - "value": "C12", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P7_D6", - "value": "H14", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P7_D7", - "value": "G14", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P10_D0", - "value": "D10", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P10_D1", - "value": "E10", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P10_D2", - "value": "B10", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P10_D3", - "value": "C10", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P10_D4", - "value": "A11", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P10_D5", - "value": "A12", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P10_D6", - "value": "A13", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P10_D7", - "value": "A14", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_1_P", - "value": "B16", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_2_P", - "value": "C16", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_3_P", - "value": "D16", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_4_P", - "value": "G12", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_5_P", - "value": "F16", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_6_P", - "value": "G16", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_7_P", - "value": "H12", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_8_P", - "value": "K13", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_9_P", - "value": "J16", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_10_P", - "value": "J14", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_11_P", - "value": "K16", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_12_P", - "value": "L16", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_13_P", - "value": "N16", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_14_P", - "value": "P16", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_15_P", - "value": "N13", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_16_P", - "value": "P13", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_1_N", - "value": "B15", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_2_N", - "value": "C15", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_3_N", - "value": "E15", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_4_N", - "value": "G13", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_5_N", - "value": "G15", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_6_N", - "value": "H15", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_7_N", - "value": "H13", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_8_N", - "value": "K12", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_9_N", - "value": "J15", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_10_N", - "value": "K14", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_11_N", - "value": "K15", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_12_N", - "value": "L15", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_13_N", - "value": "P15", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_14_N", - "value": "R16", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_15_N", - "value": "P14", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_16_N", - "value": "R14", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_17", - "value": "T13", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_18", - "value": "R12", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_19", - "value": "M11", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P4_20", - "value": "N11", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_21", - "value": "C14", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_22", - "value": "E16", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_23", - "value": "D14", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_24", - "value": "F15", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_25", - "value": "F14", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_26", - "value": "E14", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_27", - "value": "F13", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_28", - "value": "F12", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_29", - "value": "B9", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_30", - "value": "C9", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_31", - "value": "D9", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_32", - "value": "E9", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_33", - "value": "B8", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_34", - "value": "C8", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_35", - "value": "D8", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_36", - "value": "E8", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_37", - "value": "J12", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_38", - "value": "J13", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_39", - "value": "L12", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_40", - "value": "L13", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_41", - "value": "N12", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_42", - "value": "M12", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_43", - "value": "P11", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_44", - "value": "P12", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_45", - "value": "M13", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_46", - "value": "M14", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_47", - "value": "N14", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_48", - "value": "R13", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_49", - "value": "M15", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_50", - "value": "L14", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_51", - "value": "T14", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_52", - "value": "T15", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_53", - "value": "R15", - "pullmode": "NONE" - }, - { - "type": "inout", - "name": "P5_54", - "value": "M16", - "pullmode": "NONE" - }, - { - "type": "output", - "name": "DDR3_ADDR0", - "value": "N6", - "pullmode": "NONE" - }, - { - "type": "output", - "name": "DDR3_ADDR1", - "value": "C1", - "pullmode": "NONE" - }, - { - "type": "output", - "name": "DDR3_ADDR2", - "value": "F2", - "pullmode": "NONE" - }, - { - "type": "output", - "name": "DDR3_ADDR3", - "value": "E1", - "pullmode": "NONE" - }, - { - "type": "output", - "name": "DDR3_ADDR4", - "value": "F3", - "pullmode": "NONE" - }, - { - "type": "output", - "name": "DDR3_ADDR5", - "value": "G5", - "pullmode": "NONE" - }, - { - "type": "output", - "name": "DDR3_ADDR6", - "value": "C3", - "pullmode": "NONE" - }, - { - "type": "output", - "name": "DDR3_ADDR7", - "value": "D1", - "pullmode": "NONE" - }, - { - "type": "output", - "name": "DDR3_ADDR8", - "value": "D3", - "pullmode": "NONE" - }, - { - "type": "output", - "name": "DDR3_ADDR9", - "value": "G4", - "pullmode": "NONE" - }, - { - "type": "output", - "name": "DDR3_ADDR10", - "value": "E2", - "pullmode": "NONE" - }, - { - "type": "output", - "name": "DDR3_ADDR11", - "value": "C2", - "pullmode": "NONE" - }, - { - "type": "output", - "name": "DDR3_ADDR12", - "value": "F4", - "pullmode": "NONE" - }, - { - "type": "output", - "name": "DDR3_ADDR13", - "value": "M16", - "pullmode": "NONE" - }, - { - "type": "output", - "name": "DDR3_BA2", - "value": "R3", - "pullmode": "NONE" - }, - { - "type": "output", - "name": "DDR3_BA1", - "value": "P4", - "pullmode": "NONE" - }, - { - "type": "output", - "name": "DDR3_BA0", - "value": "T2", - "pullmode": "NONE" - }, - { - "type": "output", - "name": "DDR3_CKE", - "value": "R5", - "pullmode": "NONE" - }, - { - "type": "output", - "name": "DDR3_CK_P", - "value": "N4", - "pullmode": "NONE" - }, - { - "type": "output", - "name": "DDR3_CK_N", - "value": "P3", - "pullmode": "NONE" - }, - { - "type": "output", - "name": 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app/resources/boards/mimas-ecp5-mini/info.json create mode 100644 app/resources/boards/mimas-ecp5-mini/pinout.json create mode 100644 app/resources/boards/mimas-ecp5-mini/pinout_pld____.lpf create mode 100644 app/resources/boards/mimas-ecp5-mini/rules.json diff --git a/app/resources/boards/mimas-ecp5-mini/info.json b/app/resources/boards/mimas-ecp5-mini/info.json new file mode 100644 index 000000000..e4162e770 --- /dev/null +++ b/app/resources/boards/mimas-ecp5-mini/info.json @@ -0,0 +1 @@ +{"label":"Mimas ECP5 Mini","SysClkMhz":100,"datasheet":"https://numato.com/docs/mimas-ecp5-mini-fpga-development-board","interface":"FTDI","arch":"ecp5","FPGAResources":{"ffs":5280,"luts":5280,"pios":39,"plbs":660,"brams":30}} \ No newline at end of file diff --git a/app/resources/boards/mimas-ecp5-mini/pinout.json b/app/resources/boards/mimas-ecp5-mini/pinout.json new file mode 100644 index 000000000..fd92e15b8 --- /dev/null +++ b/app/resources/boards/mimas-ecp5-mini/pinout.json @@ -0,0 +1,944 @@ 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+ "value": "T4", + "pullmode": "NONE" + }, + { + "type": "output", + "name": "DDR3_ODT", + "value": "T3", + "pullmode": "NONE" + }, + { + "type": "output", + "name": "DDR3_RESET_N", + "value": "J3", + "pullmode": "NONE" + }, + { + "type": "inout", + "name": "DDR3_DQ15", + "value": "G2", + "pullmode": "NONE" + }, + { + "type": "inout", + "name": "DDR3_DQ14", + "value": "J5", + "pullmode": "NONE" + }, + { + "type": "inout", + "name": "DDR3_DQ13", + "value": "F1", + "pullmode": "NONE" + }, + { + "type": "inout", + "name": "DDR3_DQ12", + "value": "J2", + "pullmode": "NONE" + }, + { + "type": "inout", + "name": "DDR3_DQ11", + "value": "H3", + "pullmode": "NONE" + }, + { + "type": "inout", + "name": "DDR3_DQ10", + "value": "K2", + "pullmode": "NONE" + }, + { + "type": "inout", + "name": "DDR3_DQ9", + "value": "H5", + "pullmode": "NONE" + }, + { + "type": "inout", + "name": "DDR3_DQ8", + "value": "H4", + "pullmode": "NONE" + }, + { + "type": "inout", + "name": "DDR3_DQ7", + "value": "L4", + "pullmode": "NONE" + }, + { + "type": "inout", + "name": "DDR3_DQ6", + "value": "L1", + "pullmode": "NONE" + }, + { + "type": "inout", + "name": "DDR3_DQ5", + "value": "L3", + "pullmode": "NONE" + }, + { + "type": "inout", + "name": "DDR3_DQ4", + "value": "M4", + "pullmode": "NONE" + }, + { + "type": "inout", + "name": "DDR3_DQ3", + "value": "M2", + "pullmode": "NONE" + }, + { + "type": "inout", + "name": "DDR3_DQ2", + "value": "P1", + "pullmode": "NONE" + }, + { + "type": "inout", + "name": "DDR3_DQ1", + "value": "L2", + "pullmode": "NONE" + }, + { + "type": "inout", + "name": "DDR3_DQ0", + "value": "N3", + "pullmode": "NONE" + }, + { + "type": "inout", + "name": "DDR3_DQS_0_P", + "value": "N1", + "pullmode": "NONE" + }, + { + "type": "inout", + "name": "DDR3_DQS_0_N", + "value": "P2", + "pullmode": "NONE" + }, + { + "type": "inout", + "name": "DDR3_DQS_1_P", + "value": "G1", + "pullmode": "NONE" + }, + { + "type": "inout", + "name": "DDR3_DQS_1_N", + "value": "H2", + "pullmode": "NONE" + }, + { + "type": "output", + "name": "FPGA_TX", + "value": "D6", + "pullmode": "NONE" + }, + { + "type": "input", + "name": "FPGA_RX", + "value": "E6", + "pullmode": "NONE" + }, + { + "type": "input", + "name": "RXE_N", + "value": "C4", + "pullmode": "NONE" + }, + { + "type": "input", + "name": "TXE_N", + "value": "B4", + "pullmode": "NONE" + }, + { + "type": "input", + "name": "RXLED", + "value": "A3", + "pullmode": "NONE" + }, + { + "type": "input", + "name": "TXLED", + "value": "A3", + "pullmode": "NONE" + }, + { + "type": "output", + "name": "NULL", + "value": "NULL", + "pullmode": "NONE" + }, + { + "type": "input", + "name": "NULL", + "value": "NULL", + "pullmode": "NONE" + } +] \ No newline at end of file diff --git a/app/resources/boards/mimas-ecp5-mini/pinout_pld____.lpf b/app/resources/boards/mimas-ecp5-mini/pinout_pld____.lpf new file mode 100644 index 000000000..05ef87149 --- /dev/null +++ b/app/resources/boards/mimas-ecp5-mini/pinout_pld____.lpf @@ -0,0 +1,456 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; +## Mimas ECP5 Mini + +# The clock "usb" and "gpdi" sheet +LOCATE COMP "clk_12mhz" SITE "G2"; +IOBUF PORT "clk_12mhz" PULLMODE=NONE IO_TYPE=LVCMOS33; +FREQUENCY PORT "clk_25mhz" 12 MHZ; + +# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash +# write to FLASH possible any time from JTAG: +#SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=ENABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; +# write to FLASH possible from user bitstream: +# SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=DISABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; + +## USBSERIAL FTDI-FPGA serial port "usb" sheet +LOCATE COMP "ftdi_rxd" SITE "L4"; # FPGA transmits to ftdi +LOCATE COMP "ftdi_txd" SITE "M1"; # FPGA receives from ftdi +LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives +LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives +LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives +IOBUF PORT "ftdi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ftdi_txd" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33; + +## LED indicators "blinkey" and "gpio" sheet +LOCATE COMP "led[7]" SITE "H3"; +LOCATE COMP "led[6]" SITE "E1"; +LOCATE COMP "led[5]" SITE "E2"; +LOCATE COMP "led[4]" SITE "D1"; +LOCATE COMP "led[3]" SITE "D2"; +LOCATE COMP "led[2]" SITE "C1"; +LOCATE COMP "led[1]" SITE "C2"; +LOCATE COMP "led[0]" SITE "B2"; +IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet +LOCATE COMP "btn[0]" SITE "D6"; # BTN_PWRn (inverted logic) +LOCATE COMP "btn[1]" SITE "R1"; # FIRE1 +LOCATE COMP "btn[2]" SITE "T1"; # FIRE2 +LOCATE COMP "btn[3]" SITE "R18"; # UP W1->R18 +LOCATE COMP "btn[4]" SITE "V1"; # DOWN +LOCATE COMP "btn[5]" SITE "U1"; # LEFT +LOCATE COMP "btn[6]" SITE "H16"; # RIGHT Y2->H16 +IOBUF PORT "btn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## DIP switch "blinkey", "gpio" sheet +LOCATE COMP "sw[0]" SITE "E8"; # SW1 +LOCATE COMP "sw[1]" SITE "D8"; # SW2 +LOCATE COMP "sw[2]" SITE "D7"; # SW3 +LOCATE COMP "sw[3]" SITE "E7"; # SW4 +IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet +LOCATE COMP "oled_clk" SITE "P4"; +LOCATE COMP "oled_mosi" SITE "P3"; +LOCATE COMP "oled_dc" SITE "P1"; +LOCATE COMP "oled_resn" SITE "P2"; +LOCATE COMP "oled_csn" SITE "N2"; +IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI Flash chip "flash" sheet +LOCATE COMP "flash_csn" SITE "R2"; +LOCATE COMP "flash_clk" SITE "U3"; +LOCATE COMP "flash_mosi" SITE "W2"; +LOCATE COMP "flash_miso" SITE "V2"; +LOCATE COMP "flash_holdn" SITE "W1"; +LOCATE COMP "flash_wpn" SITE "Y2"; +#LOCATE COMP "flash_csspin" SITE "AJ3"; +#LOCATE COMP "flash_initn" SITE "AG4"; +#LOCATE COMP "flash_done" SITE "AJ4"; +#LOCATE COMP "flash_programn" SITE "AH4"; +#LOCATE COMP "flash_cfg_select[0]" SITE "AM4"; +#LOCATE COMP "flash_cfg_select[1]" SITE "AL4"; +#LOCATE COMP "flash_cfg_select[2]" SITE "AK4"; +IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_holdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_wpn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SD card "sdcard", "usb" sheet +LOCATE COMP "sd_clk" SITE "H2"; # sd_clk WiFi_GPIO14 +LOCATE COMP "sd_cmd" SITE "J1"; # sd_cmd_di (MOSI) WiFi GPIO15 +LOCATE COMP "sd_d[0]" SITE "J3"; # sd_dat0_do (MISO) WiFi GPIO2 +LOCATE COMP "sd_d[1]" SITE "H1"; # sd_dat1_irq WiFi GPIO4 +LOCATE COMP "sd_d[2]" SITE "K1"; # sd_dat2 WiFi_GPIO12 +LOCATE COMP "sd_d[3]" SITE "K2"; # sd_dat3_csn WiFi_GPIO13 +LOCATE COMP "sd_wp" SITE "P5"; # not connected +LOCATE COMP "sd_cdn" SITE "N5"; # not connected +IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement +IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## ADC SPI (MAX11123) "analog", "ram" sheet +LOCATE COMP "adc_csn" SITE "R17"; +LOCATE COMP "adc_mosi" SITE "R16"; +LOCATE COMP "adc_miso" SITE "U16"; +LOCATE COMP "adc_sclk" SITE "P17"; +IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## Audio 4-bit DAC "analog", "gpio" sheet +# 4-bit mode can drive down to 75 ohm load impedance. +# Lower impedance leads to IO overload, +# FPGA will stop working and need reboot. +# For standard 17 ohm earphones on PCB v1.7: +# use bits 2,3 as input (High-Z) and drive only bits 0,1. +# PCB v2.1.2 can use full 4 bits and 16mA drive for 17 ohm earphones. +LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio) +LOCATE COMP "audio_l[2]" SITE "C3"; +LOCATE COMP "audio_l[1]" SITE "D3"; +LOCATE COMP "audio_l[0]" SITE "E4"; +LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio) +LOCATE COMP "audio_r[2]" SITE "D5"; +LOCATE COMP "audio_r[1]" SITE "B5"; +LOCATE COMP "audio_r[0]" SITE "A3"; +LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio) +LOCATE COMP "audio_v[2]" SITE "F5"; +LOCATE COMP "audio_v[1]" SITE "F2"; +LOCATE COMP "audio_v[0]" SITE "H5"; +IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; + +## WiFi ESP-32 "wifi", "usb", "flash" sheet +# other pins are shared with GP/GN, SD card and JTAG +LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi +LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi +LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi +LOCATE COMP "wifi_gpio0" SITE "L2"; +LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED +LOCATE COMP "wifi_gpio16" SITE "L1"; # Serial1 RX +LOCATE COMP "wifi_gpio17" SITE "N3"; # Serial1 TX +# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active +IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +# IOBUF PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PCB antenna 433 MHz (may be also used for FM) "usb" sheet +LOCATE COMP "ant_433mhz" SITE "G1"; +IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Second USB port "US2" going directly into FPGA "usb", "ram" sheet +LOCATE COMP "usb_fpga_dp" SITE "E16"; # single ended or differential input only +LOCATE COMP "usb_fpga_dn" SITE "F16"; +IOBUF PORT "usb_fpga_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # differential bidirectional +LOCATE COMP "usb_fpga_bd_dn" SITE "E15"; +IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4; +LOCATE COMP "usb_fpga_pu_dp" SITE "B12"; # pull up/down control +LOCATE COMP "usb_fpga_pu_dn" SITE "C12"; +IOBUF PORT "usb_fpga_pu_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "usb_fpga_pu_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; + +## JTAG ESP-32 "usb" sheet +# connected to FT231X and ESP-32 +# commented out because those are dedicated pins, not directly useable as GPIO +# but could be used by some vendor-specific JTAG bridging (boundary scan) module +#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives +#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits +#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives +#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives +#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SDRAM "ram" sheet +LOCATE COMP "sdram_clk" SITE "F19"; +LOCATE COMP "sdram_cke" SITE "F20"; +LOCATE COMP "sdram_csn" SITE "P20"; +LOCATE COMP "sdram_wen" SITE "T20"; +LOCATE COMP "sdram_rasn" SITE "R20"; +LOCATE COMP "sdram_casn" SITE "T19"; +LOCATE COMP "sdram_a[0]" SITE "M20"; +LOCATE COMP "sdram_a[1]" SITE "M19"; +LOCATE COMP "sdram_a[2]" SITE "L20"; +LOCATE COMP "sdram_a[3]" SITE "L19"; +LOCATE COMP "sdram_a[4]" SITE "K20"; +LOCATE COMP "sdram_a[5]" SITE "K19"; +LOCATE COMP "sdram_a[6]" SITE "K18"; +LOCATE COMP "sdram_a[7]" SITE "J20"; +LOCATE COMP "sdram_a[8]" SITE "J19"; +LOCATE COMP "sdram_a[9]" SITE "H20"; +LOCATE COMP "sdram_a[10]" SITE "N19"; +LOCATE COMP "sdram_a[11]" SITE "G20"; +LOCATE COMP "sdram_a[12]" SITE "G19"; +LOCATE COMP "sdram_ba[0]" SITE "P19"; +LOCATE COMP "sdram_ba[1]" SITE "N20"; +LOCATE COMP "sdram_dqm[0]" SITE "U19"; +LOCATE COMP "sdram_dqm[1]" SITE "E20"; +LOCATE COMP "sdram_d[0]" SITE "J16"; +LOCATE COMP "sdram_d[1]" SITE "L18"; +LOCATE COMP "sdram_d[2]" SITE "M18"; +LOCATE COMP "sdram_d[3]" SITE "N18"; +LOCATE COMP "sdram_d[4]" SITE "P18"; +LOCATE COMP "sdram_d[5]" SITE "T18"; +LOCATE COMP "sdram_d[6]" SITE "T17"; +LOCATE COMP "sdram_d[7]" SITE "U20"; +LOCATE COMP "sdram_d[8]" SITE "E19"; +LOCATE COMP "sdram_d[9]" SITE "D20"; +LOCATE COMP "sdram_d[10]" SITE "D19"; +LOCATE COMP "sdram_d[11]" SITE "C20"; +LOCATE COMP "sdram_d[12]" SITE "E18"; +LOCATE COMP "sdram_d[13]" SITE "F18"; +LOCATE COMP "sdram_d[14]" SITE "J18"; +LOCATE COMP "sdram_d[15]" SITE "J17"; +IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +# GPDI differential interface (Video) "gpdi" sheet +LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue + +LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue - +LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green + +LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green - +LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red + +LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Red - +LOCATE COMP "gpdi_dp[3]" SITE "A17"; # Clock + +LOCATE COMP "gpdi_dn[3]" SITE "B18"; # Clock - +LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet + +LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet - +LOCATE COMP "gpdi_cec" SITE "A18"; +LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC +LOCATE COMP "gpdi_scl" SITE "E12"; # I2C shared with RTC C12->E12 +IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet +# Pins enumerated gp[0-27], gn[0-27]. +# With differential mode enabled on Lattice, +# gp[] (+) are used, gn[] (-) are ignored from design +# as they handle inverted signal by default. +# To enable differential, rename LVCMOS33->LVCMOS33D +LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 +LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 +LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 +LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 +LOCATE COMP "gp[2]" SITE "A9"; # J1_9+ GP2 +LOCATE COMP "gn[2]" SITE "B10"; # J1_9- GN2 +LOCATE COMP "gp[3]" SITE "B9"; # J1_11+ GP3 +LOCATE COMP "gn[3]" SITE "C10"; # J1_11- GN3 +LOCATE COMP "gp[4]" SITE "A7"; # J1_13+ GP4 +LOCATE COMP "gn[4]" SITE "A8"; # J1_13- GN4 +LOCATE COMP "gp[5]" SITE "C8"; # J1_15+ GP5 +LOCATE COMP "gn[5]" SITE "B8"; # J1_15- GN5 +LOCATE COMP "gp[6]" SITE "C6"; # J1_17+ GP6 +LOCATE COMP "gn[6]" SITE "C7"; # J1_17- GN6 +IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[7]" SITE "A6"; # J1_23+ GP7 +LOCATE COMP "gn[7]" SITE "B6"; # J1_23- GN7 +LOCATE COMP "gp[8]" SITE "A4"; # J1_25+ GP8 +LOCATE COMP "gn[8]" SITE "A5"; # J1_25- GN8 +LOCATE COMP "gp[9]" SITE "A2"; # J1_27+ GP9 +LOCATE COMP "gn[9]" SITE "B1"; # J1_27- GN9 +LOCATE COMP "gp[10]" SITE "C4"; # J1_29+ GP10 WIFI_GPIO27 +LOCATE COMP "gn[10]" SITE "B4"; # J1_29- GN10 +LOCATE COMP "gp[11]" SITE "F4"; # J1_31+ GP11 WIFI_GPIO25 +LOCATE COMP "gn[11]" SITE "E3"; # J1_31- GN11 WIFI_GPIO26 +LOCATE COMP "gp[12]" SITE "G3"; # J1_33+ GP12 WIFI_GPIO32 +LOCATE COMP "gn[12]" SITE "F3"; # J1_33- GN12 WIFI_GPIO33 +LOCATE COMP "gp[13]" SITE "H4"; # J1_35+ GP13 WIFI_GPIO34 +LOCATE COMP "gn[13]" SITE "G5"; # J1_35- GN13 WIFI_GPIO35 +IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[14]" SITE "U18"; # J2_5+ GP14 +LOCATE COMP "gn[14]" SITE "U17"; # J2_5- GN14 +LOCATE COMP "gp[15]" SITE "N17"; # J2_7+ GP15 +LOCATE COMP "gn[15]" SITE "P16"; # J2_7- GN15 +LOCATE COMP "gp[16]" SITE "N16"; # J2_9+ GP16 +LOCATE COMP "gn[16]" SITE "M17"; # J2_9- GN16 +LOCATE COMP "gp[17]" SITE "L16"; # J2_11+ GP17 +LOCATE COMP "gn[17]" SITE "L17"; # J2_11- GN17 +LOCATE COMP "gp[18]" SITE "H18"; # J2_13+ GP18 +LOCATE COMP "gn[18]" SITE "H17"; # J2_13- GN18 +LOCATE COMP "gp[19]" SITE "F17"; # J2_15+ GP19 +LOCATE COMP "gn[19]" SITE "G18"; # J2_15- GN19 +LOCATE COMP "gp[20]" SITE "D18"; # J2_17+ GP20 +LOCATE COMP "gn[20]" SITE "E17"; # J2_17- GN20 +IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[21]" SITE "C18"; # J2_23+ GP21 +LOCATE COMP "gn[21]" SITE "D17"; # J2_23- GN21 +LOCATE COMP "gp[22]" SITE "B15"; # J2_25+ GP22 D15->B15 +LOCATE COMP "gn[22]" SITE "C15"; # J2_25- GN22 E15->C15 +LOCATE COMP "gp[23]" SITE "B17"; # J2_27+ GP23 +LOCATE COMP "gn[23]" SITE "C17"; # J2_27- GN23 +LOCATE COMP "gp[24]" SITE "C16"; # J2_29+ GP24 +LOCATE COMP "gn[24]" SITE "D16"; # J2_29- GN24 +LOCATE COMP "gp[25]" SITE "D14"; # J2_31+ GP25 B15->D14 +LOCATE COMP "gn[25]" SITE "E14"; # J2_31- GN25 C15->E14 +LOCATE COMP "gp[26]" SITE "B13"; # J2_33+ GP26 +LOCATE COMP "gn[26]" SITE "C13"; # J2_33- GN26 +LOCATE COMP "gp[27]" SITE "D13"; # J2_35+ GP27 +LOCATE COMP "gn[27]" SITE "E13"; # J2_35- GN27 +IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PROGRAMN (reload bitstream from FLASH, exit from bootloader) +# PCB v2.0.5 and higher +LOCATE COMP "user_programn" SITE "M4"; +IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) +# on PCB v1.7 shutdown is not connected to FPGA +LOCATE COMP "shutdown" SITE "G16"; # FPGA receives +IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; diff --git a/app/resources/boards/mimas-ecp5-mini/rules.json b/app/resources/boards/mimas-ecp5-mini/rules.json new file mode 100644 index 000000000..3cfb9bac1 --- /dev/null +++ b/app/resources/boards/mimas-ecp5-mini/rules.json @@ -0,0 +1 @@ +{"input":[{"port":"clk","pin":"C7"}]} \ No newline at end of file From 4787c02ab33b43358fc66a2f4f11bb4b9c41d4df Mon Sep 17 00:00:00 2001 From: Fernando Mosquera Date: Wed, 18 Dec 2024 09:15:18 -0600 Subject: [PATCH 4/4] Delete app/resources/boards/mimas-ecp5-mini/pinout_pld____.lpf --- .../boards/mimas-ecp5-mini/pinout_pld____.lpf | 456 ------------------ 1 file changed, 456 deletions(-) delete mode 100644 app/resources/boards/mimas-ecp5-mini/pinout_pld____.lpf diff --git a/app/resources/boards/mimas-ecp5-mini/pinout_pld____.lpf b/app/resources/boards/mimas-ecp5-mini/pinout_pld____.lpf deleted file mode 100644 index 05ef87149..000000000 --- a/app/resources/boards/mimas-ecp5-mini/pinout_pld____.lpf +++ /dev/null @@ -1,456 +0,0 @@ -BLOCK RESETPATHS; -BLOCK ASYNCPATHS; -## Mimas ECP5 Mini - -# The clock "usb" and "gpdi" sheet -LOCATE COMP "clk_12mhz" SITE "G2"; -IOBUF PORT "clk_12mhz" PULLMODE=NONE IO_TYPE=LVCMOS33; -FREQUENCY PORT "clk_25mhz" 12 MHZ; - -# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash -# write to FLASH possible any time from JTAG: -#SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=ENABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; -# write to FLASH possible from user bitstream: -# SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=DISABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; - -## USBSERIAL FTDI-FPGA serial port "usb" sheet -LOCATE COMP "ftdi_rxd" SITE "L4"; # FPGA transmits to ftdi -LOCATE COMP "ftdi_txd" SITE "M1"; # FPGA receives from ftdi -LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives -LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives -LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives -IOBUF PORT "ftdi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "ftdi_txd" PULLMODE=UP IO_TYPE=LVCMOS33; -IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33; -IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33; -IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33; - -## LED indicators "blinkey" and "gpio" sheet -LOCATE COMP "led[7]" SITE "H3"; -LOCATE COMP "led[6]" SITE "E1"; -LOCATE COMP "led[5]" SITE "E2"; -LOCATE COMP "led[4]" SITE "D1"; -LOCATE COMP "led[3]" SITE "D2"; -LOCATE COMP "led[2]" SITE "C1"; -LOCATE COMP "led[1]" SITE "C2"; -LOCATE COMP "led[0]" SITE "B2"; -IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "led[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "led[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "led[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "led[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; - -## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet -LOCATE COMP "btn[0]" SITE "D6"; # BTN_PWRn (inverted logic) -LOCATE COMP "btn[1]" SITE "R1"; # FIRE1 -LOCATE COMP "btn[2]" SITE "T1"; # FIRE2 -LOCATE COMP "btn[3]" SITE "R18"; # UP W1->R18 -LOCATE COMP "btn[4]" SITE "V1"; # DOWN -LOCATE COMP "btn[5]" SITE "U1"; # LEFT -LOCATE COMP "btn[6]" SITE "H16"; # RIGHT Y2->H16 -IOBUF PORT "btn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; - -## DIP switch "blinkey", "gpio" sheet -LOCATE COMP "sw[0]" SITE "E8"; # SW1 -LOCATE COMP "sw[1]" SITE "D8"; # SW2 -LOCATE COMP "sw[2]" SITE "D7"; # SW3 -LOCATE COMP "sw[3]" SITE "E7"; # SW4 -IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; - -## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet -LOCATE COMP "oled_clk" SITE "P4"; -LOCATE COMP "oled_mosi" SITE "P3"; -LOCATE COMP "oled_dc" SITE "P1"; -LOCATE COMP "oled_resn" SITE "P2"; -LOCATE COMP "oled_csn" SITE "N2"; -IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; - -## SPI Flash chip "flash" sheet -LOCATE COMP "flash_csn" SITE "R2"; -LOCATE COMP "flash_clk" SITE "U3"; -LOCATE COMP "flash_mosi" SITE "W2"; -LOCATE COMP "flash_miso" SITE "V2"; -LOCATE COMP "flash_holdn" SITE "W1"; -LOCATE COMP "flash_wpn" SITE "Y2"; -#LOCATE COMP "flash_csspin" SITE "AJ3"; -#LOCATE COMP "flash_initn" SITE "AG4"; -#LOCATE COMP "flash_done" SITE "AJ4"; -#LOCATE COMP "flash_programn" SITE "AH4"; -#LOCATE COMP "flash_cfg_select[0]" SITE "AM4"; -#LOCATE COMP "flash_cfg_select[1]" SITE "AL4"; -#LOCATE COMP "flash_cfg_select[2]" SITE "AK4"; -IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "flash_holdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "flash_wpn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; - -## SD card "sdcard", "usb" sheet -LOCATE COMP "sd_clk" SITE "H2"; # sd_clk WiFi_GPIO14 -LOCATE COMP "sd_cmd" SITE "J1"; # sd_cmd_di (MOSI) WiFi GPIO15 -LOCATE COMP "sd_d[0]" SITE "J3"; # sd_dat0_do (MISO) WiFi GPIO2 -LOCATE COMP "sd_d[1]" SITE "H1"; # sd_dat1_irq WiFi GPIO4 -LOCATE COMP "sd_d[2]" SITE "K1"; # sd_dat2 WiFi_GPIO12 -LOCATE COMP "sd_d[3]" SITE "K2"; # sd_dat3_csn WiFi_GPIO13 -LOCATE COMP "sd_wp" SITE "P5"; # not connected -LOCATE COMP "sd_cdn" SITE "N5"; # not connected -IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement -IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; - -## ADC SPI (MAX11123) "analog", "ram" sheet -LOCATE COMP "adc_csn" SITE "R17"; -LOCATE COMP "adc_mosi" SITE "R16"; -LOCATE COMP "adc_miso" SITE "U16"; -LOCATE COMP "adc_sclk" SITE "P17"; -IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; - -## Audio 4-bit DAC "analog", "gpio" sheet -# 4-bit mode can drive down to 75 ohm load impedance. -# Lower impedance leads to IO overload, -# FPGA will stop working and need reboot. -# For standard 17 ohm earphones on PCB v1.7: -# use bits 2,3 as input (High-Z) and drive only bits 0,1. -# PCB v2.1.2 can use full 4 bits and 16mA drive for 17 ohm earphones. -LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio) -LOCATE COMP "audio_l[2]" SITE "C3"; -LOCATE COMP "audio_l[1]" SITE "D3"; -LOCATE COMP "audio_l[0]" SITE "E4"; -LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio) -LOCATE COMP "audio_r[2]" SITE "D5"; -LOCATE COMP "audio_r[1]" SITE "B5"; -LOCATE COMP "audio_r[0]" SITE "A3"; -LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio) -LOCATE COMP "audio_v[2]" SITE "F5"; -LOCATE COMP "audio_v[1]" SITE "F2"; -LOCATE COMP "audio_v[0]" SITE "H5"; -IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; - -## WiFi ESP-32 "wifi", "usb", "flash" sheet -# other pins are shared with GP/GN, SD card and JTAG -LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi -LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi -LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi -LOCATE COMP "wifi_gpio0" SITE "L2"; -LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED -LOCATE COMP "wifi_gpio16" SITE "L1"; # Serial1 RX -LOCATE COMP "wifi_gpio17" SITE "N3"; # Serial1 TX -# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active -IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -# IOBUF PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; - -## PCB antenna 433 MHz (may be also used for FM) "usb" sheet -LOCATE COMP "ant_433mhz" SITE "G1"; -IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; - -## Second USB port "US2" going directly into FPGA "usb", "ram" sheet -LOCATE COMP "usb_fpga_dp" SITE "E16"; # single ended or differential input only -LOCATE COMP "usb_fpga_dn" SITE "F16"; -IOBUF PORT "usb_fpga_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # differential bidirectional -LOCATE COMP "usb_fpga_bd_dn" SITE "E15"; -IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4; -IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4; -LOCATE COMP "usb_fpga_pu_dp" SITE "B12"; # pull up/down control -LOCATE COMP "usb_fpga_pu_dn" SITE "C12"; -IOBUF PORT "usb_fpga_pu_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "usb_fpga_pu_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; - -## JTAG ESP-32 "usb" sheet -# connected to FT231X and ESP-32 -# commented out because those are dedicated pins, not directly useable as GPIO -# but could be used by some vendor-specific JTAG bridging (boundary scan) module -#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives -#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits -#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives -#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives -#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; - -## SDRAM "ram" sheet -LOCATE COMP "sdram_clk" SITE "F19"; -LOCATE COMP "sdram_cke" SITE "F20"; -LOCATE COMP "sdram_csn" SITE "P20"; -LOCATE COMP "sdram_wen" SITE "T20"; -LOCATE COMP "sdram_rasn" SITE "R20"; -LOCATE COMP "sdram_casn" SITE "T19"; -LOCATE COMP "sdram_a[0]" SITE "M20"; -LOCATE COMP "sdram_a[1]" SITE "M19"; -LOCATE COMP "sdram_a[2]" SITE "L20"; -LOCATE COMP "sdram_a[3]" SITE "L19"; -LOCATE COMP "sdram_a[4]" SITE "K20"; -LOCATE COMP "sdram_a[5]" SITE "K19"; -LOCATE COMP "sdram_a[6]" SITE "K18"; -LOCATE COMP "sdram_a[7]" SITE "J20"; -LOCATE COMP "sdram_a[8]" SITE "J19"; -LOCATE COMP "sdram_a[9]" SITE "H20"; -LOCATE COMP "sdram_a[10]" SITE "N19"; -LOCATE COMP "sdram_a[11]" SITE "G20"; -LOCATE COMP "sdram_a[12]" SITE "G19"; -LOCATE COMP "sdram_ba[0]" SITE "P19"; -LOCATE COMP "sdram_ba[1]" SITE "N20"; -LOCATE COMP "sdram_dqm[0]" SITE "U19"; -LOCATE COMP "sdram_dqm[1]" SITE "E20"; -LOCATE COMP "sdram_d[0]" SITE "J16"; -LOCATE COMP "sdram_d[1]" SITE "L18"; -LOCATE COMP "sdram_d[2]" SITE "M18"; -LOCATE COMP "sdram_d[3]" SITE "N18"; -LOCATE COMP "sdram_d[4]" SITE "P18"; -LOCATE COMP "sdram_d[5]" SITE "T18"; -LOCATE COMP "sdram_d[6]" SITE "T17"; -LOCATE COMP "sdram_d[7]" SITE "U20"; -LOCATE COMP "sdram_d[8]" SITE "E19"; -LOCATE COMP "sdram_d[9]" SITE "D20"; -LOCATE COMP "sdram_d[10]" SITE "D19"; -LOCATE COMP "sdram_d[11]" SITE "C20"; -LOCATE COMP "sdram_d[12]" SITE "E18"; -LOCATE COMP "sdram_d[13]" SITE "F18"; -LOCATE COMP "sdram_d[14]" SITE "J18"; -LOCATE COMP "sdram_d[15]" SITE "J17"; -IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; - -# GPDI differential interface (Video) "gpdi" sheet -LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue + -LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue - -LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green + -LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green - -LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red + -LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Red - -LOCATE COMP "gpdi_dp[3]" SITE "A17"; # Clock + -LOCATE COMP "gpdi_dn[3]" SITE "B18"; # Clock - -LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet + -LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet - -LOCATE COMP "gpdi_cec" SITE "A18"; -LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC -LOCATE COMP "gpdi_scl" SITE "E12"; # I2C shared with RTC C12->E12 -IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; - -# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet -# Pins enumerated gp[0-27], gn[0-27]. -# With differential mode enabled on Lattice, -# gp[] (+) are used, gn[] (-) are ignored from design -# as they handle inverted signal by default. -# To enable differential, rename LVCMOS33->LVCMOS33D -LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 -LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 -LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 -LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 -LOCATE COMP "gp[2]" SITE "A9"; # J1_9+ GP2 -LOCATE COMP "gn[2]" SITE "B10"; # J1_9- GN2 -LOCATE COMP "gp[3]" SITE "B9"; # J1_11+ GP3 -LOCATE COMP "gn[3]" SITE "C10"; # J1_11- GN3 -LOCATE COMP "gp[4]" SITE "A7"; # J1_13+ GP4 -LOCATE COMP "gn[4]" SITE "A8"; # J1_13- GN4 -LOCATE COMP "gp[5]" SITE "C8"; # J1_15+ GP5 -LOCATE COMP "gn[5]" SITE "B8"; # J1_15- GN5 -LOCATE COMP "gp[6]" SITE "C6"; # J1_17+ GP6 -LOCATE COMP "gn[6]" SITE "C7"; # J1_17- GN6 -IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -LOCATE COMP "gp[7]" SITE "A6"; # J1_23+ GP7 -LOCATE COMP "gn[7]" SITE "B6"; # J1_23- GN7 -LOCATE COMP "gp[8]" SITE "A4"; # J1_25+ GP8 -LOCATE COMP "gn[8]" SITE "A5"; # J1_25- GN8 -LOCATE COMP "gp[9]" SITE "A2"; # J1_27+ GP9 -LOCATE COMP "gn[9]" SITE "B1"; # J1_27- GN9 -LOCATE COMP "gp[10]" SITE "C4"; # J1_29+ GP10 WIFI_GPIO27 -LOCATE COMP "gn[10]" SITE "B4"; # J1_29- GN10 -LOCATE COMP "gp[11]" SITE "F4"; # J1_31+ GP11 WIFI_GPIO25 -LOCATE COMP "gn[11]" SITE "E3"; # J1_31- GN11 WIFI_GPIO26 -LOCATE COMP "gp[12]" SITE "G3"; # J1_33+ GP12 WIFI_GPIO32 -LOCATE COMP "gn[12]" SITE "F3"; # J1_33- GN12 WIFI_GPIO33 -LOCATE COMP "gp[13]" SITE "H4"; # J1_35+ GP13 WIFI_GPIO34 -LOCATE COMP "gn[13]" SITE "G5"; # J1_35- GN13 WIFI_GPIO35 -IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -LOCATE COMP "gp[14]" SITE "U18"; # J2_5+ GP14 -LOCATE COMP "gn[14]" SITE "U17"; # J2_5- GN14 -LOCATE COMP "gp[15]" SITE "N17"; # J2_7+ GP15 -LOCATE COMP "gn[15]" SITE "P16"; # J2_7- GN15 -LOCATE COMP "gp[16]" SITE "N16"; # J2_9+ GP16 -LOCATE COMP "gn[16]" SITE "M17"; # J2_9- GN16 -LOCATE COMP "gp[17]" SITE "L16"; # J2_11+ GP17 -LOCATE COMP "gn[17]" SITE "L17"; # J2_11- GN17 -LOCATE COMP "gp[18]" SITE "H18"; # J2_13+ GP18 -LOCATE COMP "gn[18]" SITE "H17"; # J2_13- GN18 -LOCATE COMP "gp[19]" SITE "F17"; # J2_15+ GP19 -LOCATE COMP "gn[19]" SITE "G18"; # J2_15- GN19 -LOCATE COMP "gp[20]" SITE "D18"; # J2_17+ GP20 -LOCATE COMP "gn[20]" SITE "E17"; # J2_17- GN20 -IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -LOCATE COMP "gp[21]" SITE "C18"; # J2_23+ GP21 -LOCATE COMP "gn[21]" SITE "D17"; # J2_23- GN21 -LOCATE COMP "gp[22]" SITE "B15"; # J2_25+ GP22 D15->B15 -LOCATE COMP "gn[22]" SITE "C15"; # J2_25- GN22 E15->C15 -LOCATE COMP "gp[23]" SITE "B17"; # J2_27+ GP23 -LOCATE COMP "gn[23]" SITE "C17"; # J2_27- GN23 -LOCATE COMP "gp[24]" SITE "C16"; # J2_29+ GP24 -LOCATE COMP "gn[24]" SITE "D16"; # J2_29- GN24 -LOCATE COMP "gp[25]" SITE "D14"; # J2_31+ GP25 B15->D14 -LOCATE COMP "gn[25]" SITE "E14"; # J2_31- GN25 C15->E14 -LOCATE COMP "gp[26]" SITE "B13"; # J2_33+ GP26 -LOCATE COMP "gn[26]" SITE "C13"; # J2_33- GN26 -LOCATE COMP "gp[27]" SITE "D13"; # J2_35+ GP27 -LOCATE COMP "gn[27]" SITE "E13"; # J2_35- GN27 -IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; - -## PROGRAMN (reload bitstream from FLASH, exit from bootloader) -# PCB v2.0.5 and higher -LOCATE COMP "user_programn" SITE "M4"; -IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; - -## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) -# on PCB v1.7 shutdown is not connected to FPGA -LOCATE COMP "shutdown" SITE "G16"; # FPGA receives -IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;