Sys68_inst.v.bak

// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
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// to the terms and conditions of the Altera Program License 
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// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
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// Generated by Quartus II 64-Bit Version 13.0 (Build Build 232 06/12/2013)
// Created on Sat Jun 16 19:13:33 2018

Sys68 Sys68_inst
(
	.SysClk(SysClk_sig) ,	// input  SysClk_sig
	.Reset_n(Reset_n_sig) ,	// input  Reset_n_sig
	.ram_csn(ram_csn_sig) ,	// output  ram_csn_sig
	.ram_wrln(ram_wrln_sig) ,	// output  ram_wrln_sig
	.ram_wrun(ram_wrun_sig) ,	// output  ram_wrun_sig
	.ram_addr(ram_addr_sig) ,	// output [16:0] ram_addr_sig
	.ram_data(ram_data_sig) ,	// inout [15:0] ram_data_sig
	.LED(LED_sig) ,	// output  LED_sig
	.rxbit(rxbit_sig) ,	// input  rxbit_sig
	.txbit(txbit_sig) ,	// output  txbit_sig
	.rts_n(rts_n_sig) ,	// output  rts_n_sig
	.cts_n(cts_n_sig) ,	// input  cts_n_sig
	.cf_rst_n(cf_rst_n_sig) ,	// output  cf_rst_n_sig
	.cf_cs0_n(cf_cs0_n_sig) ,	// output  cf_cs0_n_sig
	.cf_cs1_n(cf_cs1_n_sig) ,	// output  cf_cs1_n_sig
	.cf_rd_n(cf_rd_n_sig) ,	// output  cf_rd_n_sig
	.cf_wr_n(cf_wr_n_sig) ,	// output  cf_wr_n_sig
	.cf_cs16_n(cf_cs16_n_sig) ,	// output  cf_cs16_n_sig
	.cf_a(cf_a_sig) ,	// output [2:0] cf_a_sig
	.cf_d(cf_d_sig) ,	// inout [15:0] cf_d_sig
	.porta(porta_sig) ,	// inout [7:0] porta_sig
	.portb(portb_sig) ,	// inout [7:0] portb_sig
	.timer_out(timer_out_sig) ,	// output  timer_out_sig
	.bus_addr(bus_addr_sig) ,	// output [15:0] bus_addr_sig
	.bus_data(bus_data_sig) ,	// inout [7:0] bus_data_sig
	.bus_rw(bus_rw_sig) ,	// output  bus_rw_sig
	.bus_cs(bus_cs_sig) ,	// output  bus_cs_sig
	.bus_clk(bus_clk_sig) ,	// output  bus_clk_sig
	.bus_reset(bus_reset_sig) 	// output  bus_reset_sig
);